1985_MMI_LSI_Databook_6ed 1985 MMI LSI Databook 6ed

User Manual: 1985_MMI_LSI_Databook_6ed

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LSI DATABOOK
SIXTH EDITION

PAL,'!' (prograrpmable Array,LogiC),

HAL~ (Hard Array LogiC),

IHilr

Monolithic 1!t!1I
MemorIes U1Jn.U

and SKINNYDI,P® are

registered,trad~marks o,t Mpnolithic rv'iemori,es,tnc;:.

Double-Density PLUS'" Interface, PLETt. and PALASM'" are trademarks of Monolithic Memories Inc.

"Copyright 1978,1981,1982,1984,1985
Monolithic Memories Inc.' 2175 Mission College Blvd.' Santa Clara, CA 95954-1592. (408) 970-9700' (910) 970-9700. (910) 338-2374

,

"

.<:

Introd"c;ti~n .
This book has been prepared to give the user a concise list of all lSI Products
offered by. Monolithic Memories. It is divided by products into sections on Military
Products DiviSion, PROMs; PlE'", PAl@/HAl@ Circuits, System Building Blocks/
HMSI'", FIFOs, Memory Support, Arithmetic Elements and logic, Multipliers!
DividerS, a:.Bit Interface, Double-Density PLUS'" Interface, (CMOS products
included), ECl10KH and General Information which has a Listing of Available
Literature. Each section has been designed to allow the user the most useable
format .for the pr.oc\ucts described. The PROM section gives data in the "generic"
form allowing a quick review of the trade-off between devices. Inserted also are
newer PROM data sheets shown with more detail. Cross references and selection
guides are giiten where applicable. FIFO, PAUHAl Circuits, HMSI, Arithmetic
Elements, MultiplierslOividers,8-Bit Interface, Double-Density PLUS Interface,
ECl10KH and. Interface data sheets are shown in detail for each product .
. Advanced Information Sheets are included to inform you of soon-to-be released
. products. This LSI data bo.ok was formatted with you, the user, in mind. For more
infprmation, contact the looal Monolithic Memories sales representative or franchised distributor. In .section 170f this book Monolithic Memories Sales Reps and
Franchised. Distributors are listed, for your convenience.
Prpducts listed in the Advanced Information section were due for imminent release
at the time of printing. Ple.ase.contact Monolithic Memories for current availability
and full parametriC specifications.

IIIIonoIHhIc

m""e"""'.

Ordering Information

PAL®
Programmable Array Logie Circuits
PAl

=prog.

::Jma~1.

L

SHRP

618 -2

Family

SHRP = ~~n:;;W~'~nhanced

NUMBER OF

PACKAGE TYPE

XXXX = Hi-Rei

ARRAY INPUTS

3 ::: Programmable
Read Only Memory
(PROM)

N = Plastic Dip

=Active High
::: Active Low

J
F

C = Complementary
P = Programmable
R = Registered
RA ::: Registered Asynchronous
S =Shared
X =Exclusive OR Registered
A =Arithmetic Registered

::: Ceramic Dip
= Flat Pack

UNIOUE TWO-DIGIT
PART NUMBER

NL = Plastic Leadless
Chip Carrier
NS = Plastic SKINNY DIP
JS =ceramic SKINNYDIP
L =Loadless
Chip ~rrier
P = Pin Gnd Array
C = Commercial
M =MIlitary

SPEED/POWER-------'
A =High Speed
-2 =1/2 Power
-4 = 1/4 Power
A-2 = High Speed and 1/2 Power
A-4 = High Speed and 1/4 Power

PERFORMANCE
-1 = SchoHky Process (PROMs)
-2 ::: Improved Performance

Over·l

High Performance PROMs
53S328 1

'-------TEMPERATURE CODE

NUMBER OF OUTPUTS

J = Ceramic Dip
F :: Flat Pack - Side Brazed
L = Leadless Chip
W =Cerpack

PRODUCT

PACKAGE

OUTPUT TYPE

HI-REL
883B SCREENIN.G.
=MII-Std-883.LE.VEL
Cia.. B
XXXX = Other Hi Rei

CODE
6 = Commercial
5 = Military

OPTIONAL PROCESSING

family

TEMPERATU.
CODE
6
5

~-11

=Commercial
= Military

AJ

.1

8838

B838L s.=CREEN.
MII-Std-883.
Cia
.. B
L H.I_RE.
ING LE.
VEL
XXXX ::: Other HI Rei

I.

PACKAGE TYPE·
PRODUCT

J ::: Ceramic Dip

3 ::: Programmable
Read Only Memory

F ::: Flat Pack - Side Brazed
L :: Leadless Chip

¥I : : Cerpack

(PROM)
FAMlly--_ _--'

PLETM
Programmable Logic Element
PlE5P8

PROGRAMMABlET~

LOGIC ELEMENT

MJ

..

T.EMPERATUREJ3~41. _JL~.
[2

~ER.NNUMBER.

Mc=J

HAL = Hard Array

H
L

Standard Performance PROMs

MEMORY SIZE - - - - - - '

8838

E-C..

1 ::: 1024 bits

HI-REL
883B SCREENING
=MII-Std-883.LEVEL
Cia.. B
XXXX

=Other HI Rei

PERFORMANCE

S ::: Schottky
AA ::: Registered
Asynchronous
RS ::: Registered
Synchronous
o '" Diagnostic
DA " Diagnostic
Asynchronous

2
4

:=

8::: 8192 bits

None ::: Standard
A
:;: Enhanced
' - - - - - OUTPUT DESIGNATOR

o~

Open

Collector

1 = Three Slate
3 = TWo State

' - - - - - - NUMBER OF OUTPUTS
4 = 4 biOs
8::: 8 bits

2048 bits 16::: 16384 bits
32::: 32768 bits

=4096 bits

NUMBER OF INPUTS
PACKAGE TYPE
OUTPUT TYPE

P = Programmable Polarity
R = Registered
NUMBER OF OUTPUTS

J = Ceramic Dip
F = Flat Pack - Side Brazed
L =Leadlesa Chip
W = Cerpack
C

SN54lS373

=Commercial

M = Military

r

S-BitlDouble-Density PLUSTM Interface

TEMPERATURE CODE

STANDARD---IJ
PREFIX
TEMPERATURE CODE
74 =Commercial
54::: Military

J

8838

FAMILy-------'
S ::: SchoHky
LS ::: Low-Power Schottky
ACT::: Advanced CMOS, TTL-Compatible

Monolithiom Memories

L_~~~~,

883B = MII-Std-883. Class B

PACKAGE TYPE

J ::: Ceramic Dip
L ::: Leadless Chip
W = Cerpack
UNIQUE THREE-DIGIT
PART NUMBER'

1-3

Ordering Information

Prices
All prices are in U.S. dollars and are
subject to change without notice.

Minimum Order Requirements
For all orders placed in the factory
there is a minimum order requirement
of $1000 ($250 per line item) except
for the following:
HAL® Circuits-The $3-4K N.R.E. and
mask charge can be amortized over
the initial production commitment. The
minimum initial production commitment is 5K units within one year; the
minimum quantity per line item release
is2K.
Pro PAL Circuits-When purchased the
initial phase Of HAL Circuit. there is no
additional N.R.E. and there is a nominal
adderfor programming and testing. The
minimum quantity per release is 500
units. When purchased without a followon the $1-2K N.R.E. can be amortized
over a minimum initial production
commitment of $2500 units.
There will be a minimum of $250 and
$50 per line item for drop-ship orders.

Terms
70%/30 days. 30%/45 days from date
of invoice. FOB Sunnyvale. California.

Commercial/Military
Codes
The letter codes "C" and" M" are used
to denote commercial and military
device limits as follows:
Commercial-TA = OOC to+ 75°C
VCC=5V±5%
Military-TA = -55°C to
+125°C
VCC= 5V±10%

Package Codes
All devices ordered must include a
package code as a suffix to the part
number. The package code definitions
are shown below.
PACKAGE
DESCRIPTION
CODE
Ceramic dual-in-lineJ
see below
JS
Ceramic dual-in-linesee below
Plastic dual-in-lineN
see below
NS
Plastic dual-in-linesee below
NL
Molded lead less chip
carrier
Flat Pack - Bottom Brazed
F
Leadless-Ceramic
L
T
Inverted "0" package
W
Ceramic Flat Pack
See "Part Numbering Systems" for
complete part descriptions.

20pin
24pin

1·4

Monolithic

N.J

m

Memories

General
Unless otherwise specified the standard packages are "J" or "N" packages.
In some instances the "0" package
is the only package available. Other
non-standard packages and other
military Level 883B devices not listed
may be available. Contact a sales
representative of Monolithic Memories.
Non-standard devices are considered
nonreturnable by distribution to
Monolithic Memories.

Screening Options
PROCESS LEVEL
MIL'STO-883
Method 5004 and 5005
LevelB
SHRP
Super High Reliability
Product

PART
MARKING
883B
(Suffix)
SHRP

Ordering Information
In-House PROM Programming Guide Lines
1) Minimum Order Size:
XK-SK 5K pcs/yr/pattern
500 pes/shipment
16K-32K 2.5K pcs/yr/pattern
250 pcs/shipment
2) Lead Time: Initial code acceptance six weeks.
Standard lead time plus two weeks after code acceptance.
3) Cancellations: 60Days
4) Schedule Change: 30 Days
5) Price Adder:
ORDEF SIZE
Density
Min-10K
10K-25K
25K+
XK-2K
50~
40~
30~
4K-SK
60~
50~
4O~
16K-32K
S5~
70~
55~
REG/DIAG
Price mcludes mk markmg With customer pattern number.
'.
6) Inputs: Truth Table
Paper Tape
Disk
Master
A combination of two inputs are required.
If only one input is supplied, a sample lot must be signed off by
the customer.

..

Monolithic Memories Software Support
SYSTEM

PALASM1
OBJECT
$200

PALASM1.
SOURCE

PALASM2
OBJECT

PALASM2
SOURCE

Contaqt Factory

$500

PLeAsM

'PLEASM
SOURCE

OBJECT
No Charge

No Charge
PLE-VMS8-MT

OEC VAX VM~ MT

PAL1-VMSE~MT

PAL1-VMS8-MT

PAL2-VMSE-MT

PA12-VMS8-MT

PLE-VMSE..MT

OEC VAX UNIX Mt

PAL1-UNXE-MT

PAL1-UNXS-Mt

PAL2-UNXE-MT

PAL2-UNX8-MT

PLE-UNXE-MT

PLE-UNX8-MT

PlE-RSXE~MT

PLE~RSX8-Mt

PLE-RSXE-BO ,

PLE"RSXE-80

PLE-IBME-MT

PLE-IBM8-MT

PLE-IPCE-50

PLE·IPC8-S0

PLE-IPCE-5C

PL~-IPCS-SC

OEC POP-11 RSX MT

PAL1-RSX8-MT

OECPOP-11 RSX80

P,4,L1-RSX8-80.

,

..

IBM MAINFRAME MT

PAL1-IBME~MT

PAL1-IBMS..MT

IBM PC (008)50

PAL1-IPCE-SO

PAL1-IPCS-SO

)BM PC (CPM) SC

PAL 1-IPCE-50

PAL1-IPC8-5C

INTEL MOS SO

PAL1cMOSE-8S

PAL1-MOS8-8S

PLE-MOSE-8S

PLE"MOS8-8S

PAL2-IPCE-50

PAL2-fPCS-50

"

,

INTELMDSDO

PAL1-MOSE-80

PAL1-MOS8-80

PLE-MDSE-80 •

PLE-MOSS-80

APPLE (CPM) 50

PAL1-APLE-SC

PAi.1~APLS-5C

PLE-APLE-5C

PLE-APLS-5C

IBM-3740 CPM 80

PAL1-CPME-8C

PAL1-CPMS-8C

PLE-CPME-8C

PLE-CPME-8C

KAYPRO (CPM) 50

PAL1-KAYE-5C

PAL1-KAYS-SC

PLE-KAYE-5C

PLE-KAYS-SC

ASCIIMT

PAL1-ASCE-MT

PAL1~ASC8-MT

PLE-ASCE-MT

PLE-ASCS-MT

EBCOICMT

PAL1-EBOE-MT

PAL.1-EB08-MT

PLE-EBOE-MT

PLE-EB08-MT

SPECIAL FORMATS

PAL1.GENE-XX

PAL1.GENS-XX

PLE-GENE-XX

PLE-GEN8-XX

MANUAL

PAL-MANUAL

,',

Notes: PALASM1: Supports small and ,medium PAL Oevio,,'(20124 pin non-registered devices)
PALASM2: Supports MegaPAL!levlces and Registered devices (RA and RS) as well as standard ;10124 pin parts.
PLEASM: Supports PLEIPROM devices upta 4096x12.
APPLE and CPM ""rslons require 64 Kb RAM.
IBM PC versions require 128 Kb RAM
Please contact IdeaLogic before placing arders:tor Special Formats.

.source Code order$: require a signed Sc?urce License Agreeme~t'before,.order is sryipped. Contact Idealogic.

MonoIIthlCmMe~.

Ordering Information
Military Ordering Information
Products have different numbering formats: These formats in conjunction with the product selection guides by function will enable you
to select the proper military level component.

PAL®
Programmable Array Logic

e

Standard Performance PROMs

PROGRAMMAB~E!j-J~L14L4 eJM
~'-RELSCREEN'NGLEVEL

ARRAY LOGIC
FAMILY

~

883B = MU-Std-883, Cless B

CODE
TEMPERAT;:JRE....J.
6 ::: Commercial
5::: Military

PACKAGE TYPE
J =. Ceramic Dip

NUMBER OF ARRAY
INPUTS

F ::: Flat Pack .. Side Brazed

PRODUCT
3 = Programmable
Read Only Memory
(PROM)

L = Leadl... Chip
W = Cerpack

OUTPUT TYPE
H = Active High
L = Active Low
,TEMPERATURE RANGE
C = Complementary
M::: -S5"C to +125°C
P ::: Programmable
~---SPEED/POWER
R = Registered
RA ::: Registered Asynchronous
A = High Speed
A-2 = High Speed
S = Shared
X ::: Exclusive OR Registered
and 112 Power
A-4 = High Speed
A ::: Arithmetic Registered
and 1/4 Power

xxxx = Other HI R.I

'

FAMILY-------'
S = Schdttky

o = Open Collector

~----NUMBER

OF OUTPUTS
4=4blts

MEMORY SIZE - - - - '
1 = 1024 bits 8 = 8192 bUs
2 = 2048 blls 16 = 16384 blls
4= 4096 bits 32 = 32768 bits

8= 8 bits

DESC Drawing Numbering System

L. HI-REL
883B =SCREENING
MU-Std-883, LEVEL'
Class B

PART NUMBER

T

82008 B1 J X

PACKAGE TYPE
J = Ceramic Dip
L = Leadless Chip
W=Cerpack

DRAWIN,GNUMBER:::::J
FOR
PRODUCT OR
FAMILY

UNIQUE THREE-DIGIT

LS ::: Low-Power SChottky
ACT::: Advanced CMOS, TTL-Compatible

' - - - - OUTPUT DESIGNATOR
1 :: Three State
3 = Two Stale

Asynchronous

SN54LS373 J 8838

TEMPERATURE CODE
74 = Commercial
54 = Military

PERFORMANCE
None = Standard
A
=Enhanced

Synchronous
D ,. Diagnostic
DA ,. Diagnostic

TEMPERATURE CODE
C ::: Commercial
M = Mlillary

J ,r.

PACKAGE TYPE
J =Ceramic Dip
F =F1at Pack - Side Brazed
L = Leadiess Chip
W = Cerpack

FAMILY------'
S = Schdttky
RA '= Registered
Asynchronous
RS =Registered

a-BitlDouble-Density PLUSTM Interface
STANDARD--.:J,
'
PREFIX

HI-REL SCREENING LEVEL
883B = MII-Std-883, Class B
XXXX = Other HI Rei

PRODUCT
3 =Programmable'
Read Only Memory
(PROM)

PACKAGE TYPE
J = Ceramic Dip
F = Flat Pock - Sid. Brazed
L = Lead.... Chip
W = Cerpack

NUMBER OF OUTPUT

1[

53S328 1 A J 883B

--1

e

OUTPUT TYPE
P = Programmable Polarity
R = Ragiltered

PERFORMANCE
-1 = Schottky Process (PROMs)
-2 = Improved Perfonnance
Over-1

TEMPERATURE
CODE
6 ,. Commercial
5 = Mililary

EM
3BHI_RELSCR,
EENI.NG LEVEL
883B = MU-std-883,
Ciess B

,

NUMBER OF INPUTS

PACKAGE TYPE
J = Ceramic Dip
F = Flat Pack .. Side Brazed
L = Leadless Chip
W = Cerpack

High Performance PROMs

PLE'M
Programmable Logic Element

AMMAB~E~JE~5P8 J ~.

----c:::-HI-REL SCREENING LEVEL
883B = MU-Std-883, Class B
XXXX = Other HI Ret

UNIQUE TWO-DIGIT
PART NUMBER

' - - - - NUMBER OF OUTPUTS

PRO,
GR.ELEMENT
LOGIC

E

5341 -2 J 8838

D

"

PROGRAMMING
PROCEDURE!
DEVICE TYPE

JAN Part Numbering System
,

JM385101 503 01 BRA

JANDESIGNATORJ"
Parts cannot be marked with

~':te:~Ir:~~~~PL.
GENERAL

A = Hot Solder Dip

~ : ~:I:;'~te
X = Any Lead Finish

PROCUREMENT SPEC

1-6

r~~~

REFERS TO DETAIL SPEC
203 = 1K PROM (256 x 4)
204 = 2K PROM (512 x 4)
206 = 4K PROM (1K x 4)
207 = 256 PROM (32 x 8)
208 = 4K PROM (S12 x 8)
209 = 8K PROM (1K x 8,2K x 4)
210 = 16K PROM 12K x 8.4K x 4)
211 = 32K PROM (8K x 8)
503 = Programmable Array Logic
504 = Programmable logic

PACKAGE TYPE
E = 16 Lead 1/4 x 7/8 Dip
F = 16 Lead 1/4 x 3/8 Fletpack
J = 24 Lead 1/2x 1-1/4 Dip
K = 24 Lead 3/8 x 5/8 FI.lpock
R = 20 Lead 1/4 x 1-1/16,Dip'
V = 18 Lead 1/4 x 15116 Dip
2 = 20 Lead 0.35 x 0.35 LCC
X = 24 Lead 3/ax 3/8 Flatpack"
Y = 20 Lead 3/8 x 3/8 Flatpack"
Y = 20 Lead 5/16 x 1.0 Dip"
Z = 24 Lead 1/4 x 3/8 Flatpack
3 = 28 Lead 0.45 x OAS LCC

DEFINES DEVICE T Y P E - - - - - - - '
• PAL Siaeh Sheet
•• PROM Slash Sheet

PROCESSING LEVEL
ClessS
ClessB

NIonoIithio

W Memories

LLEADFINISH,
A = Hot 50_ Dip
B = Tin PlaIa
C = Gold Plaia
.
X = Any Lead Flnlah
CASE OUTLINE
(same as JAN
38510 DuBin..)

Table of Contents
Introduction ....................... ; ................ 1-2
Ordering Information ............................... 1-3
Table of Contents ................................... 1-7
Numericallndex ................................... 1-12
Tenns and Conditions of Sales (General Provisions) .. 1-16
Product Assurance Program ........................ 1-18

MILITARY PRODUCTS DIVISION
Contents for Section 2 ............................... 2-2
Introduction ........................................ 2-3
Standard Processing Flows ........................... 2-3
JAN Program ..... ,................................. 2-4
M38510 Slash Sheet Cross Reference to
Generic Part Number .............................. 2-4
DESC Drawing Program .................. .... .. . . . .. 2-5
DESC Drawing/Generic Part Type Cross Reference ..... 2-5
Small PAL20 Devices ................................ 2-5
New DESC Drawing Number Insert ................... 2-6
Medium PAL20 Devices .............................. 2-6
Quality Programs ................................... 2-1
Generic Data ....................................... 2-8
Manufacturing and Screening Locations ............... 2-8
Manufacturing Capabilities ........................... 2-8
A.C. Testing ........................................ 2-8
VIUVIH Parametric Information ..............•........ 2-9
Electro Static Discharge ............................. 2-9
Major Program Participation .......................... 2-9
Military PROM Performance Analysis ................. 2-10
Package Information ............................... 2-11

PROMs
Contents of Section 3 ................................ 3-2
PROM Selection Guide .............................. 3-3
PROM Cross Reference Guide ........................ 3-4
TiW PROM Family
53/63S080
32x8 bit
Standard TiW ........... 3-5
53/63S081
32x8 bit
Standard TiW ........... 3-5
63S081A
32x8 bit
Standard TiW ........... 3-5
53/63S140
256x4 bit
Standard TiW ........... 3-9
53/63S141
256x4 bit
Standard TiW ........... 3-9
Standard TiW .-.......... 3-9
53/63S141A
256x4 bit
512x4 bit
53/63S240
Standard TiW .......... 3-13
Standard TiW .......... 3-13
53/63S241
512x4 bit
53/63S241A
512x4 bit
Standard TiW .......... 3-13
53/63S280
256x8 bit
Standard TiW .......... 3~17
256x8 bit
Standard TiW .......... 3-17
53/63S281
256x8 bit
Standard TiW .......... 3-17
53/63S281A
1024x4 bit
Standard TiW .......... 3-21
53/63S440
53/63S441
1024x4 bit
Standard TiW .......... 3-21
53/63S441A
1024x4 bit
Standard TiW ....... , . . 3-21
53/63S480
512x8 bit
Standard TiW .......... 3-25
53/63S481
512x8 bit
Standard TiW .......... 3-25
~

53/63S481A
512x8 bit
Standard TiW .......... 3-25
53/63S841
2048x4 bit
Standard TiW .......... 3-29
53/63S841A
2048x4 bit
Standard TiW .......... 3-29
53/63S1641
4096x4 bit
Standard TiW .......... 3-33
53/63S1641A 4096x4 bit
Standard TiW .......... 3-33
53/63S1681
2048x8bit
Standard TiW .......... 3-37
53/63S1681A 2048x8 bit
Standard TiW .......... 3-37
53/63S3281
4096x8 bit
StandardTiW .......... 3-41
53/63S3281A 4096x8 bit
Standard TiW .......... 3-41
53/63RA481
512x8 bit
Registered ............. 3-45
Registered ............. 3-45
53/63RA481A 512x8 bit
53/63RS881
1024x8 bit
Registered ...•......... 3-50
Registered ............. 3-50
53/63RS881A 1024x8 bit
53/63RA1681 2048x8 bit Registered w/Asyn. Enable .. 3-55
53/63RA1681A 2048x8 bit Registered w/Asyn. Enable .. 3-55
53/63RSl681 2048x8 bit Registered w/Sync. Enable .. 3-60
53/63RS1681A2048x8 bit Registered w/Sync. Enable .. 3-60
53/63DA441
1024x4 bit Diagnostic Registered
3-65
1024x4 bit Diagnostic Registered
3-65
53/63DA442
2048x4 bit Diagnostic Registered
53/63DA841
with Asynchronous Enable
and Output Initialization ............ 3-76
53/63D1641
4096x4 bit Diagnostic Registered ...... 3-84
53/63DA1643 4096x4 bit Diagnostic Registered
Outpullnilialization ................ 3-92
TiW PROM Programmer Reference Chart ........•... 3-100
Generic NCR Family .............................. 3-102
53/6308-1
256x8 bit
Standard PROM .... ;.. 3-102
53/6309-1
256x8 bit
Standard PROM ....... 3-102
53/6340-1
512x8 bit
Standard PROM ....... 3-102
53/6341-1
512x8 bit
Standard PROM ....... 3-102
53/6341-2
512x8 bit
Standard PROM ....... 3-102
53/6348-1
512x8 bit
Standard PROM.: ..... 3"102
53/6349-1
512x8 bit
Standard PROM ....... 3-102
512x8 bit
Standard PROM ....... 3-102
53/6349-2
53/6380-1
1024x8 bit
Standard PROM ....... 3-102
53/6380-2
1024x8 bit
Standard PROM ....... 3-102
53/6381-1
1024x8 bit
Standard PROM ....... 3-102
53/6381-2
1024x8 bit
Standard PROM ....... 3-102
NiCr PROM Programmer Reference Chart ........... 3·109

PLE
Contents for Section 4 ................................ 4-2
PLE to PROM Cross Reference Guide .................. 4-2
Selection Guide ...................................... 4-3
PLE means Programmable Logic Element ............... 4-4
Registered PLE ............................ , . . . . . . . . .. 4-4
PLEASM'" ........................................... 4-5
Logic Diagrams .................................... 4-6/7
Specifications ........................................ 4-8
PLE Family Programming Instructions .......•......... 4-14
PLE Family Programming Equipment Suppliers ......... 4-15
PLE Family Block Diagram ............... ; ........... .4-16
PLE Programmer Reference Chart ..................... 4-20

MonollthicW Memories

1-7

..

Table of Contents
PAL®/HAL® CIRCUITS
Contents for Section 5 ................................ 5-2
The PAL IntroductionfThe PAL Concept ................ 5-3
PAUHAl Description ................................ 5-16
PAUHAl logic Symbols ...................... ,...... 5-21
10H8
Octal 10 Input And-Or-Gate Array ............. 5-26
12H6
Hex 12 Input And-Or-Gate Array .............. 5-26
14H4
Quad 14 Input And-Or-Gate Array ............. 5-26
16H2
Dual 16 Input And-Or-Gate Array ............• 5-26
16Cl
16 Input And-Or-/And-Or-Invert Gate Array .... 5-26
1018
Octal 10 Input And-Or-lnvertGate Array ....... 5-26
1216
Hex 12 Input And-Or-Invert Gate Array ........ 5-26
1414
Quad 14 Input And-Or-lnvertGate Array ....... 5-26
1612
Dual 16 Input And-Or-Invert Gate Array ........ 5-26
12110 Deca 12 Input And-Or-Invert Gate Array ....... 5-27
1418
Octal 14 Input And-Or-Invert Gate Array ....... 5-27
1616
Hex 16 Input And-Or-Invert Gate Array ........ 5-27
1814
Quad 18 Input And-Or-Invert Gate Array ....... 5-27
2012
Dual 20 Input And-Or-Invert Gate Array ........ 5-27
20Cl
20 Input And-Or-/ And-Or Invert Gate Array .... 5-27
16lB
Octal 16 Input And-Or-Invert Gate Array ....... 5-2B
16R8
Octal 16 Input Registered And-Or-Gate Array ... 5-28
16R6
Hex 113 Input Registered And-Or-Gate Array .... 5-28
16R4
Quad 16 Input Registered And-Or-Gate Array .. 5-28
16X4
Quad 16 Input Registered
And-Or-Xor Gate Array .................... 5-28
16A4
Quad 16 Input Registered
And-Carry-Or-Xor Gate Array ............... 5-28
20Xl0 Deca 20 Input Registered
And-Or-Xor Gate Array .................... 5-29
20XB
Octal 20 Input Registered
And-Or-Xor Gate Array .................... 5-29
20X4
Quad 20 Input Registered
And-Or-Xor Gate Array .................... 5-29
20L10 Deca 20 Input And-Or-Invert Gate Array ....... 5-29
16l8A Octal 16 Input And-Or-Invert Gate Array ....... 5-30
16R8A Octal 16 Input Registered And-Or Gate Array ... 5-30
16R6A Hex 16 Input Registered And-Or Gate Array .... 5-30
16R4A Quad 16 Input Registered And-Or Gate Array ... 5-30
16P8A Octal 16 Input Registered
And-Or Invert Gate Array ..............•.... 5-30
16RP8A Octal 16 Input Registered And-Or Gate Array .... 5-30
16RP6A Hex 16 Input Registered And-Or Gate Array .... 5-30
16RP4A Quad 16 Input Registered And-Or Gate Array ... 5-30
20lBA Octal 20 Input And-Or-Invert Gate Array ....... 5-31
20R8A Octal 20 Input Registered And-Or ............. 5-31
20R6A Hex 20 Input Registered And-Or .............. 5-31
20R4A Quad 20 Input Registered And-Or ............. 5-31
10H8-2 Octal 10 Input And-Or Gate Array ............. 5-3~
12H6-2 Hex 12 Input And-Or Gate Array .............. 5-32
14H4-2 Quad 14 Input And-Or Gate Array ............. 5-32
16H2-2 Dual 16 Input And-Or Gate Array. . . . . . . . . . . . .. 5-32
16Cl-2 16 Input and-Or Invert Gate Array ............. 5-32
10l8-2 Octal 10 Input And-Or-Invert Gate Array ....... 5-32
12l6-2 Hex 12 Input And-Or-Invert Gate Array ..•..... 5-32
14l4-2 Quad 14 Input And-Or-Invert Gate Array ....... 5-32
16l2-2 Dual 16 Input And-Or-Invert Gate Array ........ 5-32
16l8A-2 Octal 16 Input And-Or-Invert Gate Array ....... 5-33
16R8A-2 Octal 16 Input Registered
And-Or-Gate Array ........................ 5-33
16R6A-2 Hex 16 Input Registered
And-Or-Gate Array ........................ 5-33
16R4A-2 Quad 16 Input Registered
And-Or-Gate Array ...................... ... 5-33
16l8A-4 Octal 16 Input And-Or-Invert Gate Array ....... 5-34
16R8A-4 Octal 16 Input Registered
And-Or-Gate Array ........................ 5-34

1·8

16R6A-4 Hex 16 Input Registered
And-Or-Gate Array ........................
16R4A-4Quad 16 Input Registered
And-Or-Gate Array ........................
PAl20RA10 Deca 20 Input Registered
Asynchronous And-Or ..................
24RS Series .........................................
20S10 Deca 20 Input And-Or-Array
with product term sharing ..................
20RS10 Deca 20 Input Register And-Or Gate Array
with product term sharing ..................
20RS8 Octal 20 Input Register And-Or Gate Array
with product term sharing ..................
20RS4 Quad 20 Input Register And-Or Gate Array
with product term sharing .............. ,...
32R16 1500 Gates, 32 Inputs, 16 Outputs .............
64R32 5000 Gates, 64 Inputs, 32 Outputs .............
PAUHAl Waveforms ................................

5-36
5-37
5-38
5-40

logic Diagrams
10H8 ...............................................
12H6 ...............................................
14H4 ...............................................
16H2 ...............................................
16Cl ...............................................
1018 ...............................................
1216 ...............................................
1414 ...............................................
1612 ...............................................
1618 ...............................................
16R8 ...............................................
16R6 ...............................................
16R4 ...............................................
16X4 ......................•........................
16A4 ...............................................
16P8 ...............................................
16RP8 ..............................................
16RP6 ..............................................
16RP4 ..............................................
12110 ..............................................
1418 ..........................................•....
1616 ...............................................
1814 ...............................................
2012 ...............................................
20Cl ...............................................
20110 ..............................................
20Xl0 ..............................................
20X8 .................•.............................
20X4 ...............................................
2018 ...............................................
20R8 ...............................................
20R6 ...............................................
20R4 ...............................................
20RA10 .................................•...........
20S10 ..............................................
20RS4 ..............................................
20RS8 ......................•.......................
20RS10 .............................................
32R16 ..............................................
64R32 ..............................................
Programmer/Development System ..•.................

5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59
5-60
5-61
5-62
5-63
5-64
5-65
5-66
5-67
5-68
5-69
5-70
5"71
5-72
5-73
5-74
5-75
5-76
5-77
5-78
5-79
5-80
5-81

5-34
5-34
5-35
5-36
5-36
5-36
5-36

Die Configuration
PAl20RA 10 ......................................... 5-81
PAl32R16 .......................................... 5-82
PAl64R32 .......................................... 5-82

Monolithic WMemorles

Table of Contents
SYSTEM BUILDINGBLOCKS/HMSI™
Contents for Section 6 .................•....•........ 6-3
System Building Blocks/HMSI Selection Guide ...•.•... 6-3
SN54174LS461 8-Bit Counter / ..•.......... :......... 6-4
SN54174LS469 8-Bit UplDown Counter .•..••.......• 6-8
SN54174LS498 8-Bit Shift Register .••......•.•...... 6-12
SN54174LS380 Multifunction 8-Bit Register •••...•••• 6-16
SN54174LS491 10-Bit Counter. • . . . . . . • . • • • • • . . . • . •. 6-20
SN54174LS450 16:1 Mux .•.................•......• 6-24
SN54174LS451 Dual 8:1 Mux ......... , .•.•.....••.. 6-28
SN54174LS453 Quad 4:1 MUx ,..................... 6-32
SN54174LS460 10-Bit Comparator. o';'.': ............. 6-36

FIFO
Contents for Section 7 ............................... 7-2
FIFO Selection Guide ..•..•.•••.••........•....•••... 7-2
fiFOs: Rubber-Band Memories to Hold Your
System Together ......••..........•....•.....•.... 7-3
74S225/A Asynchronous First-In First-Out Memory •.... 7-8
057/67401
Cascadable ...•............•.•. , .. 7~ 16
C57167402
Cascadable. .. . . . • . . . . .. . . . . • . . . .. 7-16
057/67401 A
Cascadable ....................... 7-16
O57/67402A
Cascadable ....................... 7-16
O57/67401BCascadabie ••..•..•....•••.•..•. '•. 7"16
057/67402B
Cascadable •..•.....•...••........ 7-16
57/67401
Standalone, •.....•...... '.••..•.... 7-28
Standalone .......... ~ •. ; . • • . . . .. .. 7-28
57/67402
57/67401 A
Standalone" .•. , ...............•... 7-28
57/67402A
Standalone ........................ 7-28
57/67401B
Standalone, ....•.........•......... 7-28
57/67402B
Standalone; •... ,.••.•.•.. " ... ; • . . .. 7-28
67L401
Low Power Cascadable Memory >.... 7-39
67L402
Low Power Cascadable Memory ...• '. 7-48 .
574l3A35 MHz,(Standalone) 64x5 Memory
7-57
67413A
35 MHz.(Standalone) 64x5Memory
7-57
67413
35 MHz (Standalone) 64x5 Memory .. 7-57
67417
Serializing First-In-First-Out
64x8/9 Memory •••.••
7'-69
0"

••

,

••••• ,.

MEMORY SUPPORT
Contents for Section 8 ••... ;~ ••••.:;.................. 8-2
Memory Support Selection Guide .•..••.....• ~ .. ",' • . ... 8-2
improving Your Memory with
'S700-Family MOS Drivers ... • . . • . • . . . • . . . . • . . . . • .. 8-3
Dynamic RAM Controller!,Qrlver SN74S408/
SN74S408/DP8408 Dynamic RAM
'
Controller Driver .•..•...•..•....•.•• ; ••......:... • •. 8;-10
SN74S408-21DP8408-2 Dynamic RJIiM
Controller Driver ..
8-10
SN74S408;-3/DP8408-3 Dynamic, RAM ,
Controller Driver ....•.••••:•.: :;; .•• : •• ; • '. . . • . •• . •. 8-10
SN74S4Q9/DP8409 Multi-Mode;oynamic RAM
Controller Driver ......... : ; .•.• ,; . , .. 0" ....... , "" 8-27
SN74S409-21DP8409-2 Multi"ModeDynamic RAM,
Controller Driver ......................... 0.:...•.. · 8-27
SN74S4Q9-3/DP8409-3·Multi-M,ode·Dynamic RAM
Controller Driver .......................... o' •••••• '. 8-27
SN54174S700/-1 8-Bit Dynamic RAM Driver
with Three-State Outputs ..•..•••.. '0. '.0 ..... , .... 8~51
0

...................... ,

....

,

,'.

SN54174S730/-1 8-Bit DynamiC RAM Driver
with Three-State Outputs .........................
SN54174S731/-1 8-Bit Dynamic RAM Driver
with Three-State Outputs .........................
SN54174S734/-1 8-Bit DynamiC RAM Driver
with Three-State Outputs ....... :.................
HDI'-6600-S Quad Power Strobe ........•.....• ~ . . . •.
HDI-6600-5 Quad Power Strobe .....• . . . . . . . . . . . . . ..
HDI-6600-2 Quad Power Strobe .....................

8-51
8-51
8-51
8'-61
8-61
8-61

ARITHMETIC ELEMENTS AND LOGIC
Contents for Section 9 ...................... , ... ;.;.. 9-2
Arithmetic Elements Selection Guide, . . . . . . . . . . . . . • . .. 9-2
SN54174S381 Arithmetic Logic
Unit/Function Generator ....... ; . .. .. . . . . . . . . .. . . ... 9-3
SN54174S182 Look-Ahead Carry Generators ..........• 9-9
SN54174S148 High Speed Schottky Priority Encoders .. 9-12
SN54174S348 High Speed Schottky Priority Encoders .. 9-12

MULTIPLIERS/DIVIDERS
Contents for Section 10 ..... , •... ,.................. 10-2
Multiplier/Divider Selection Guide..•.....•............ 10-2
"Five NewWays to Go Forth and Multiply ......•..•... 10-3
SN54174S5088x8 Multiplier/Divider. ,o' •••••••••••••••• 10-8
SN74S516 16x16 Multiplier/Divider ...•...•.......•... 10-21
SN54174S556 Flow-Thru'· Multiplier Slice '..•..•...... 10-37
SN54174S557 8x8 High Speed Schottky Multipliers .... 1(}'50
SN54174S558 8x8 High Speed Schottky Multipliers ...• 10-50
Ole Configuration

a-siT INTERFACE'

for

Contents
Section 11 ........ :.................... 11-2
8-Bit Interface Selection Guide ........ . • • . . . • . . • . . •. 11-3
Pi.ck thE! Right 8-Bit or 16-13it
Interface Part for the Job'. .. .. .. .. .. .. . . .. .. . .. . ... 11-4
SN54174LS210 8-Bit Buffers ...................... 11-15
SN54174LS240 8-Bit Buffers •.........•.•.....••... 11-15
SN54174LS241 8-Bit Buffers ......... .. .. .. .. .. ... 11-15
SN54174LS244 8-Bit Buffers ...................... 11-15
SN54174S210
8-Bit Buffers , ...... : .............. 11-15
SN54174S240
8-81t Buffers ..... , ................ 11-15
SN54174S241
8-BitBuffers ...................... 11-15
SN54174S244
8-Bit Buffers , . i ........... , .. , . . . .. 11-15
SN54174LS310 8-Bit Buffers with'
'
,
SchmittTrig!iler Inputs. . . • • . • . • • .. 11-23
SN54/74LS340 8-BitBufferswitj1
Schmitt Trigger' Inputs •• , ..• o'.,... 11-23
'SN54/74LS341 8-Bit Buffers with '
Schmitt Trigger Inputs ....... to .•• 11-23
SN54174L8344 8-8it Buffers with
Schmitt Trigger Inputs ...•..•....• 11-23
SN54174S310
8-Bit Buffers with
Schmitt Trigger Inputs •.•••....•.• 11-23
SN54174S340
8-Bit Buffers with.
Schmitt Trigger Inputs ..•.•••.••.• 11-23
SN54174S:341
8-Bit Buffers wjth
Schmitt Trigger,lnputs .•.•••••.... 11-23
SN541748344
8-8it l;3uffers with
Schmitt Trigger Inputs ............ 11-23

MonoI/th/oWMemorie.

1·9

Table of ContentS
SN54174LS245 8-Bit Buffer Transceiver ••..•....•..
SN54174LS645 8-:Bit Buffer Transceiver ••.•......•.
SN54174LS645-1 8-Bit Buffer Transceiver ...........
SN54174LS273 8-BitRegisters with Master Reset
orClock Enable ............ ~ ....
SN54174LS377 a.:Bit Reg isters with Master Reset
or Clock Enable .................
SN54174S273
8-Bit flegisters with Master Reset
or Clock Enable .................
SN54174S377
8-ait Registers with Master Reset
or Clock Emible .................
SN54174LS373 8-Bit Latcl:1 ........................
SN54174LS374 8-Bit Register ................ ; .....
8-Sit I.,atch ....... ," ... , .. .. .. .....
SN54174S3~3
8-Bit Register ., •••••..• '....•.,. . . . • ..
SN54174g;374
8-Bit Register with Clock Enable
SN54/74S383
and Open-Collector Outputs ...•..
SN54174LS533 B-Bit I.,atch with Inverting Outputs •..
SN54174L~ 8-Bit Flegister with
Inverting Outputs. • . • . •• • . . . • . • ••
SN54174S533
8-Bit Latch with Inverting Outputs •••
SN54174S534
8-Bit Register witt)
,
Inverting 'Outputs ................
SN74S531
8-Bit Latch with 32 mA Outputs •.....
8-Bit Register with 32 mA Outputs ...
SN74S532
8-Bit Latch with Inverting,
SN74S535
32 mA Outputs. '........... " • ....
8-Bit Register with Inverting,
SN74S536
32 mA Outputs ..................
SN54174S7oo/-1· 8-Bit Dynamic-RAM Driver
with Three State Outputs
SN54174S7oo/-1 8-Bit Dynamic-RAM Driver
with Three State Outputs
SN54174S7oo/-1 8-Bit Dynamic-RAM Driver
with Three State Outputs
SN54174S7oo/-1 8-Bit Dynamic-RAM Driver
with Three State Outputs
SN54174S818
8-Bit Diagnostic Register •..••••..••

11-31
11-32
11-32
'
11-33
11-33
11-33
11-33
,11-40
11-40
11-40
11-40
11-46
11-50
11-50
11-50
11"sO
11-56
11-56
1H50
11-60
11-64
11-64
11-64
11~

11.:a5

DOUBLE-DENSITY PLU$™INTERFACE
Contents for Section 12 ............................. 12-2
Double-Density PLUS Selection Guide •.•..•.....•... 12-2
Small But Mighty; New Components Give YOu
More Logic in Less Chips ......................... 12-3
SN54174LS245 8-Bit Buffer Transceiver ..............12-6
SN54174LS645 8-Bit Buffer Transceiver ; ....•.. : ••• 12-10
SN54174LS645-1 8-Bit Buffer Transceiver .•...••.••• 12-10
SN54174LS546 8-Bit Bus Register Transceiver ..••••• 12-14
SN54174LS547 B-Bit Bus Register Transceiver ....•.. 12-14
SN54174LS566 8-Bit Bus Register T18nsceiver , ..•••. 12-14
SN54174LS567 8-Bit Bus Register Transceiver ....... 12-14
SN54174LS646 8-Bit Bus Front-Loading-Latch
Transceiver ...................... 12-34
SN54174LS647 B-Bit Bus Front-Loading-Latch
Transceiver ..................... 12-34
SN54174LS648 8-Bit Bus Front-Loading-Latch
Transceiver .. '....... ; . .. .. .. . ... 12-34
SN54174LS649 B-Bit Bus Front-Loading-Latch
Transceiver .................... .12-34
SN54174LS651 8-BitBus Front-Loading-Latch
Transceiver ..................... 12-47

1-10

8-Bit Bus Front~Loading·Latcli
Transceiver ..................... 12-47
SN54174LS653 8-Bit Bus Front-Loading-Latch ' .'
Transceiver ....................... 12-47
SN54174LS654 8-Bit BysFront-LOliding:.utch
. Transceiver ..................... 12-47
SN54174LS548 8-Bit Two-Stage
Pipelined Register/Latch . . . . . . . . • . .12-62
SN54174LS549 8-Bit Two-Stage
Pipelined Register/Latch ..•• '.' . . . .1.2-62
SN54174LS793 8-Bit Latch/Register
with Readback ................ ,. 12-74
SN54174LS794 8-Bit Latch/Register
with Readback .................. 12-74
SN74S818
8-Bit Diagnostic Register .......•... 12-79
54174ACT646j8-Bit Bus Front-Loading Latch Transceivers
5417 4ACT648 Advanced CMOS.TTL Compatible ..• 12-91
54174ACT651
B-Bit Bus Front-Loading Latch Transceivers
54174ACT652 Advanced CMOS-TTL Compatible •• 12-102
SN54174LS652

ECL10KH
Contents for Section 13 ............................. 13'2
Selection Guide for ECL10KH ....................... 13'2
ECL10KH for High Performance System Design ..•..•• 13-3
MC10H101 Quad OR/NOR Gate ..•...•.......•..•• 13-4
MC10H103 Quad 2-lnput OR Gate ..•..•.••....•.... 13-6
MC10H102 Quad 2-lnput NOR Gate ••..••.•......•. 13-6
MC10H105 Triple 2-3-2 Input OR/NOR Gate ••..•.... 13-6
MC10H104 Quad 2-lnput and Gate .. , ............. 13'10
MC10H107 Triple 2-lnput Exclusive OR/NOR Gate •• 13'10
MC10H109 Dual 4-5 Input OR/NOR Gate .•.•.•••••• 13'10
MC10H130 Dual Latch ......... ; ................. 13'12
MC10H131 Dual Master-Slave TypeD Flip-Flop ••••• 13-14
MC10H141 Four-Bit Universal Shift Register ..•....• 13'17
MC10H158 Quad 2-lnput Multiplexer ••..•.•....••. 13'19
MC10H159 Quad 2-lnputlnverting Multiplexer
with Enable ...•......•....•••••••••• 13'21
MC10H173 Quad 2-lnput Multiplexer with Latch ..... 13-23
MC10H210 3-lnput OR/NOR Gate ...•..••.•••••••• 13-25
MC10H211 3-0utput OR/NOR Gate .•....•••.••••• 13-25

GENERAL INFORMATION.
Defihition of Terms Waveforms ••••••••.•••••••.•..•. 14-2
Available Literature List ............................. 14-4

ADVANCED INFORMATiOr-.! ,
Contents for Section 15 ........................ ,.. ... 15-2
53163S880
1024)(8 bjt PROM ......... ,............ 15-3
S881
1024x8 bit PROM ............... ,.;.... 15-3
S881A 1024x8 bit PROM •.•..•.•. , ~; •.• ;. •• • . •• 15-3
53/63S6481. 8192x8 bit PROM •.•..•.•..•• , ••••••.•• 15-4
S6481A 8192x8 bit PROM,' •...• ,',.. • • . • . . • •• . • .15-4
541745419 FIFO RAM Controller .•..•.•..• , .• ,.: .•••• 15-5
SN74S480 SiBER (Single Burst Error Recovery IC) ••••• ' 15-6
PAL20B Series ..................................... 15-7
PAL® Series 20AP w/Programmable Output Polarity ,... 15-9
PAL@> Series 24AP w/Programrilable Output Polarity •• 15-11
10 HPAL 20PB (ECL PAL) ........................... 15-'13
ZHAL'· 20 CMOS Hard Array Logic Devices ••••••••• 15-15

IIIIonoIIthlo'W M.morIe.

Table of Contents
PACKAGE DRAWINGS
Contents for Section 16 ............................. 16-2
Side Brazed - Flat Pack
Lel;ldsiFinish •••.•••••••• '.' • • . . . . . . • . . . • . . . . • . . • • • ••
Package Body .•.••••.•.••••.....•..•.•...••..•••••
Aluminum Bonding Wire ..•••.....•.......•..•......
Side Brazed ••.••.....••...•....••.....•..•.•••.•...
480 ...•..••.••••..•.•......••.••.••••••••••••.•.•.
Flat Pack ••...•...•......•..•.•••••••••.••••••....•
16F-4I5 .• ;........................................
18F-213 •••.•.•......•.•.••..•............•...•••••
2OF-3 •..•.••.••••••••.•••••....•...•.......•...••.
24F-3 •..•.•••••••••••.•••••....•.....•.•.....•••.•
24F-4/6 .................. :.:.......................

16-3
16-3
16-3
1~
16-5
16-6
16-7
16-7
16-8
16-8
16-9

Cerdip
Caps and Bases •••••••••••••.........•....•.•..•••. 16-10
Cavity/Die Attach ••••••••••••............•... : •••..16-10
Leadframe Material/Lead Finish ....•.......•....•••. 16-10
Cerdip •....••••••••••••••••.....••...••.••... , ••• 16-10
14J .•.•.. ; .•.••••••.•••.••.•...•.....•••.•.••.•••• 16-11
16J •.•.•....•..•..•....•...•..•..•.•....•. ; .••.••. 16-11
18J ••••••......•......••...• '.' ................... 16-12
20J .............................................. 16-12
24JS ............................................. 16-13
24J ............................................... 16-13
40J ............................................ ; •.. 16-14
.J.eadless Chip carriers
Lelidless Chip Carrier •••••...•....•.........•..••••
20L ..............................................
28L ...............................................
44L .................. , ............................
52L ........................................ ; ••••..
84L-l .............................................
84L-2 •.•..•....•.....•••...••••••••••••••••••....
84L-2 Socket ••••.•••••••••••....•.•...•....•.••••

16-15
16-16
16-16
16-17
16-17
16-18
16-19
16-20

Molded Dips - Chip Carriers
Leadframe ......•••..... ;......................... 16-21
Gold Bonding Wire ................................ 16-21
Package Body .•...•••••••••••••••.•....•.••••••.• 16-21
Lead Finish ...•.•..••••....•.•.........•.•••••...• 16-21
Die Attach Pad/Bonding ........................... 16-21
Molded'Dip ....................................... 16-22
16N •...••....••....••.•.............•••••••..••.. 16-23
18N ........•......•........•........•••..•.•..... 16-23
20N ............................................... 16-24
24NS .. ·.......................................... 16-24
24N ••••.•.••.•••.........•.•.•.••.••.••.•...•.•. :' 16-25
40N ..................................... ·......... ·16-25
48N ....... ; ...................................... 16-26
Molded Chip Carrier •..•..•...........••.•••.•..... 16-27
20NL ............................................ 16-28
28NL ........................................... ~ 16-29
44NL ......••.••.••...•.•......................... 16-:30
Pin Grid Array
Pin Grid Array ••.........•..•...•••••.•.•...••...• 16-31
88P-l ............................................ 16-32
88P-2 .••..........••.••••.•..........••••••••••.. 16-33
Top Brazed Ceramic
TopBrazed ....................................... 16-34
24T ............ : .................... , ............ 16-35
Cerpack
Cerpack ................... :...................... 16-36
16W-3 ..............................................16-37
18W-l ............................................ 16-37
20W-2 ............................................. 16-38
24W-2 .................' .............. ,............. : 1s:38.
Thermal Measurement
Power Dissipation Determination ., ••....••.••.•• ; •• 16-39
Therrnl;lllmp6ctance Measurement Procedure ••••••••. 16-39
Therrnal.~esistance Curves .•...... ; .•••••••••. ; •. , 1~1
Representatives/Distributors ..................... ,... 17-.1

1-11

..

,Numei'ical'lndex:
C57401 ....•.•.•.•...•...•
C57401A .•.•...•....••....
C57401B .•..•.•.•.•.•.•.••
C57402 •.....•.• : .......•.
C57402A ...•.•.•.•...•.•.•
C57402B •.••.•.....•.•....

7-16
7-16
7-16
7-16
7-16
7-16

C67402 ..••.••.•..••...•..
C67401A •..........•.....•
C67401B ..•...............
C67402 ••..........•.•....
C67402A ...•.•.••..•.•..••
C67402B .....•.....•.....•

7-16
7-16
7-16
7-16
7-16
7-16

HAL10H8 .....•.•. ~ .•••.•.
HAll0H8-2 .•.•.•.•.•.•.•.
HAll0L8 ....•.•..••......
HAl,10L8-2 .•.....•.•.•....
HAL12H6 .•..•...•.••...•.
HAl12H6-2 ....•.•.•.•....
HAL12l6 ........• • . . . . . ..
HAL12l6-2 ..•.•.••.••.••••
HAl12l10 .•.•.•.••....••.
HAl14H4 .••...•...•...•..
HAL.14H4-2 .•.•••.•.•.•.•.
HAL1414 .; .••.•.••••..•.•
HA~14l4-2 ••.....•.•...•..
HAL14L8 ..•.••.••.•••••••
HAL16A4 .......•.•.......
HAL16Cl .•.•..•...•..•...
HAL16Cl-2 ...•.•...•••.•.
HAL16H2 ...•.......•.....
HAL16H2-2 .•.....•.•.....
HAL1612 .••.•.•.•.•.•.•..
HAl16L2-2 .••...••.•......
HAL16l6 • • . • . • . • . • . • . • • •.
HAl16l8 .....••••..•..•.•
HAL16L8A ...••.•.•.....•.
HAL16L8A-2 •.•.....•.•.••
HAl16L8A-4 •.•••.•.•.•.•.
HAl16PSA •.•..•..•.•.•...
HAL16R4 ••.•.•••.•..•••..

5-26
5-32
5-26
5-32
5-26
5-32
5-26
5-32
5-27
5-26
5-32
5-26
5-32
5-27
5-28
5-26
5-32
5-26
5-32
5-26
5-32
5-27
5-28
5-30
5-33

5-34

5-30
5-28

HAL16R4A ...•...•.•....•.
HAL 16R4A~2 ...•...•....•.
HAL16R4A-4 .•.•.•.•.•..•.
HAL16RS ....•...•.....•..
HALJ 6R6A •.•.... ;........
HAL16R6A-2: • . . . . • • . . . . . .•
HAL16R6A-4 .•...•.•...••.
HAl16R8. . • • • . . . • • . . • . • ..
HAL16R8A :........... .•.•
HAL16R8A-2' ....... ).".....
HAL16R8A-4 ............ '..
HAl16RP4A ••...•••...••.•
HAL16RP6A ...............
HAl16RP8A .•...•.•.•.••..
HAl16X4 .................
HAl18L4' ............ ~ ....
HAl20Ct ..•.•.•.•.•.•.••.
HAL20l2 .................
HAl20L8A .•.•.•.•.•.•..•.
HAl20l10 •..........•.••.
HAL20R4A ................
HAL20R6A ..•.•.•.•.•.....
HAL20R~A •.•..••..•.•..•.
HAl20RA10 ...............
HAL20RS4 ................
HAL20RSS ••..•••.......•.
HAl20RS10 •...... : .......
HAL2OS10 ................
HAL20X4 •••..•..•..••.•.•
HAL20X8 .................
HAl20Xl0 .•..•...........
HAl32R16 ................
HAl64R32 •.•.•.....•.•..•

5-30
5-33
5-34
5-28

5-30
5-33

5-34
.5-28

5-30
5-33

5-34
5-30
5-30

5-30
5-28
5-27
5-27
5-27
5-31
5-29
5-31
5-31
5-31
5-35
5-36
5-36
5-36
5-36
5-29
5-29
5-29
5-37
5-38

HDI-6600-2 •.••.••.•. : • . .. 8-61
HDI-660Q-5 •.•.•.•........ 8-61
HDI-6600-8 .•.•.•..••.•..• 8-61
MC10Hl0l
MC10Hl02
MC10Hl03
MC10H104

................ 13-4
................ 13-6
•.......•..•...• 13-6
..•••.•.•.•.... 13-10

MC10H105; •.. :,L ..... ·.:.:.:·1~
MC10Hl07 ............... 13-10
MC10H130 ........••. ::: .13-12
MC10H131 .: ....... "";'" 13-14
MC10H141 ............... 13-17
MC10Hl58 .......... ;~ .... 13-19
MC10H159 ............ ,., 13-21
MC10H173 ............... 13-23
MC10H210 ............... 13-25
MC10H211 ............... 13-26
PAL1 OH8 ................. 5-26
PAll0H8-2 ................ 5-32
PAll0l8 .................. 5-26
PAll0L8-2 ................ 5-32
PAL1 OP8A ................ ,15-9
PAl12H6, ................. 5-26
PAL12H6-2 ................ 5-32
PAL12l6 .................. 5-26
PAL12l6-2 ................ 5-32
PAl12l10 ................. 5-27
PAl12P6A ................ 15-9
PAl12Pl0A .............. 15;-11
PAL14H4 ................. 5-26
PAl14H4-2 ................ 5-32
PAl14l4 ........ ; ........ : 5-26
PAL14l4-2 ................ 5-32
PAL14L8 .................. 5-27
PAL14P4A ................ 15-9
PAl14P8A ............... 15-11
PAl16A4 .................. 5-28
PAL16C1 ................. 5-26
PAL16C1-2 ................ 5-32
PAL16C1A ................ 15-9
PAL16H2 ................. 5-26
PAL16H2-2 ................ 5-32
PAl16l2 .................. 5-26
PAL16l2-2 ................ 5-32
PAL1616 .................. 5-27
PAL16l8 .................. 5-28
PAL16l8A .. . .. .. .. .. .. ... 5-30
PAL16l8A-2 ............... 5-33

Numerical Index
PAL16L8A-4 ............... 5-34

PAL20X10 ................. 5-29

538241

PAL16L8B ..•..•.......... 15-7

PAL32R16 ....•.•...••.... 5-37

538241A .................. 3-13

PAL16P2A ....•.•••....... 15-9
PAL16P6A ............... 15-11
PAL16P8A ...........•.... 5-30

PAL64R32

.......•.......• 5-38

538280 ................... 3-17
538281 ................... 3-17
538281A .................. 3-17

PAL16R4 .•.........••..... 5-28
PAL16R4A .•......•.•...•. 5-30

PLE5P8A ...•.......•.•.... 4-2

PLE13P8 .................. 15-4

................... 3-13

538440 ................... 3-21
538441 ................... 3-21

PAL 16R4A-2 .•..•......... 5-33

PLE5P8 ...........•......•• 4-2
PLE8P4 •...............•..• 4-2

538441A .................. 3-21

PAL16R4A-4 .••.•..•.....• 5-34
PAL16R4B ...•..•...•..•.. 15-7

PLE8P8 ......•.......•..... 4-2
PLE9P4 •...•.•......••..... 4-2

538480 ................... 3-25
538481 ................... 3-25

PAL16R6 .•........•....... 5-28
PAL 16R6A .••....•........ 5-30

PLE9P8 .........•.....••... 4-2
PLE9R8 ..........•......... 4-2

538481A .................. 3-25
538841 ................... 3-29

PLE10P4 •...••............. 4-2

538841A .................. 3-29
538880 ................... 15-3
538881 ................... 15-3
53888lA .............. ; ... 15-3

PAL16R6A-2 ....•...•..... 5-33
PAL16R6A-4 ••............ 5-34
PAL16R6B .....•.......... 15-7
PAL16R8 ..........•....... 5-28

PLE10P8 ........••.•....••• 4-2
PLE10R8 ..................• 4-2
PLE11 P4 ...•............... 4-2

PAL16R8A .•..........••.. 5-30

PLE11 P8 ••.•..•.....••..... 4-2

5381641 .................. 3-33

PAL16R8A-2 ..•...••.....• 5-33
PAL16R8A-4 ••............ 5-34

PLE11 RA8 •......•...•..•.. 4-2

5381641A ................. 3-33
5381681 .................. 3-37

PAL16R8B •.•..•.•........ 15-7
PAL16RP4A •.....•........ 5-30
PAL16RP6A •............•. 5-30

PLE11RSB ................• 4-2
PLE12P4 •..••.......•...... 4-2
PLE12P8 •.....•.•.....•••.. 4-2

5381681A ................. 3-37
53$3281 .................. 3-41
53$3281A ................. 3-41

PAL16RP8A ....••......... 5-30

531)1641 •....•............ 3-84

5386481

PAL16X4 .............•.... 5-28
PAL18L4 ..............•... 5-27

53DA441 .......•.......... 3-65

5386481A ................. 15-4

53DA442 .........••...•.•. 3-65
53DA841 ..............•••. 3-76
53DA1643 ................. 3-92

5308-1 ................... 3-102
5309-1 ................... 3-102

PAL18P4A ............... 15-11
PAL20C1 • . • • . . . . . . . . • . . .. 5-27
PAL20C1A ..........•.... 15-11
PAL20L2 ......•........... 5-27
PAL20L8A .....•.........• 5-31
PAL20L10 ....•............ 5-29
PAL20P2A .....•......••. 15-11
PAL20R4A ....•.........•. 5-31
PAL20R6A ....•........•.. 5-31
PAL20R8A ....•........•.. 5-31
PAL20RA10 ............... 5-35
PAL20R84 ................ 5-36
PAL20R88 ....•.•....•.... 5-36
PAL20R810 ••............. 5-36
PAL20810 .•...•..•...•.... 5:36
PAL20X4 .........•...•.... 5-29
PAL20X8 .................. 5-29

53RA481 ....•.......•..... 3-45

.................. 15-4

5340-1 ................... 3-102
5341-1 ................... 3-102

53RA481A ...............• 3-45
53RA1681 ................. 3-55

5341-2 •.•................ 3-102

53RA1681A ..•.........•.. 3-55
53RSB81 .•.....•.......••. 3-50

5348-1 ................... 3-102
5349-1 ................... 3-102

53RSB81A ................ 3-50
53R81681 ................. 3-60

5349-2 ................... 3-102
5380-1 ................... 3~102

53R81681A •..•........•.. 3-80

5380-2 ................... 3-102
5381-1 ................... 3-102
5381-2 ................... 3-102

538080 .................... 3-5
538081 .••...•............. 3-5
5388140 ................... 3-9
538141 .................... 3-9
538141A ................... 3-9
538240 ................... 3-13

MonoIHhlom""emorles

54ACT646 ............... 12-91
54ACT648 ............... 12-91
54ACT651

.............. 12-102

54ACT652 .............. 12-102

1·13

..

Numerical Index
54L5210
54L5240
54L5241
54L5244
54L5245
54L5273
54L5310
54L5340
54L5341
54L5344
54L5373
541.5374
54L5377
54LS380
54L5450
54L5451
54LS453
54LS460
54LS461
54L5469
54L5491
54L5498
54L5533
54LS534
54L5546
54L5547
54L5548
54LS549
54LS566
54LS567
54LS645
54LS646
54L5647
54J,.5648
54L5649
54L5651
54L5652
54LS653
54LS654
541.S793
54L5794

1....4

................. 11-15
................. 11-15
................. 1H5
................. 11-15
.................. 12-6
................. 11-33
................. 11-23
................. 11-23
................. 11-23
................. 11-23
.......... , .. .... 11-40
................. 11-40
.... ,............ 11-33
.................. 6-16
.................. 6-24
.................. ,6-28
.................. 6-32
.................. 6-36
......•.••.•...... , 6-4
................... e.a
...... ,........... 6-20
.................. 6-12
................. 11-50
..•.•..•..•.••..• 11-50
................. 12-14
•.•....•..•.•.... 12~14
................. 12-62
................. 12-62
................. 12-14
................. 12·14
•.•.•.•...•.••... 12-10
................. 12-34
................. 12-34
.•.•.•.....••.•.. 12-34
................. 12-34
................. 12-47
................. 12-47
................. 12-47
................. 12-47
•.•......•..•.• ;. 12-74
.••.••.•.•.•..... 12-74

545148 ............•.•. :'.• 9-12
545182 ..................... 9-9
545210 ................ '" 11-15
'545240 .................. 11-15
545241 ,.................. 11-15
545244 •....••.••.•.•.•.. 11-15
545273 .................. 11-33
545310 .................. 11-23
545340 .•.•.•.••.•.•.•..• 11-23
545341 .•...•.••...•.•..• 11.23
545344 .................. 11-23
545348 ................... 9-12
545373 ......•..•...••..• 11-40'
545374 •.•...•.••.•.•.... 11-40
545377 .................. 11-33
545381 ........•...••...•.• 9-3
545383 .................. 11-48
546419 ................... 15-5
545508 ................... ' 10-8
545533 .................. 11-50
545534 .................. 11-50
545556 .................. 10-37
545557 .....•......•..... 10-50
545558 .................. 10-50
545700 .......•....•.•.••. 8-51
545700-1 .. .. • .. .. • .. ..... 8-51
545730 ....•....•.•....•.• 8-51
545730-1 ................. 8-51
545731 •....••...•.•..•.•. 8-51
545731-1 ................. 8-51
545734 ..........•.•....•. 8-51
545734-1 ................. 8-51
57401 .....................
57401A •..............•...
57402 .....................
57402A ..........•.•..•.•.
57413A ...•...•....•...••.

7-28
7"28
7-28
7-28
7-57

6301641 .................. 3-84
630A441 .•.•.•.•..•.•..... 3-65
630A442 .•..••.••••.•.•... ,3-85

IIIIonoIIIhIc

m"..,.""",.

630A841 .............. ; ...
630A1643 ............. ~ ...
63RA481 ........... " ......
63RA481A •••.•..•.....•.•
63RA1681 ..••.•.••..•...••
63RA1681A ...............
63RS881 ..••.... ,.........
63RS881A ••.•...•••. '••.•.
63RS1681 .................
63R51681A ...............

3-76
3-92
3-45
3-45
,3-55
3-55
3-50
3-50
3-60
3-60

635080 ....•......••.•...•. 3-5'
635081 ............... " ... 3-5
635081A •.....•..•..•..•.•. 3-5
635140 ................. , .. 3-9,
635141 ...••.•.••.......... 3-9
635141A ................... 3-9
635240 ..•••.•.•.....•.... 3-13
635241 ................... 3-13
635241A ................ :.3-13
635280 ................... 3-17
635281 .•.••....••.•.••... 3-17
635281A .................. 3-17
635440 ..•••.•.......... ;. 3-21
635441 ................... 3-21
635441A .................. 3-21
635480 ................... 3-25
635481 ................... 3-25
635481A .................. 3-25
638841 ...••...••..•.••..• ,3-29
635841A .................. 3-29
635880 ................... 15-3
63S881 ................... 15-3
63S881A .................. 15-3
6351641 .................. 3-33
6351641A ................. 3-33
6351681 .................. 3-37
6351681A ................. 3-37
6353281 ..•..•......•..•.• 3-41
63S3281A ................. 3-41
6356481 •...•.•.••..•.•..• 15-4
6356481A .•...•.•..•..•.•. 15-4

Numericsllndex
6308-1
6309-1
6340-1
6341-1
6341-2
6348-1
6349-1
6349-2
6380-1
6380-2
6381-1
6381-2

...................
.................•.
...........•...•...
...................
....•..............
........••.........
...................
.••.......•..•.....
...•.....•....•..••
...•.....•.........
•....••.....•.•....
..•.....••....•....

74ACT646
74ACT648
74ACT651
74ACT652
74L8210
74L8240
74L8241
74L8244
74L8245
74L8273
74L8310
74L8340
74L8341
74L8344
74L8373
74L8374
74L8377
74L8380
74LS450
74L8451
74L8453
74L8460
74L8401
74LS469
74L8491
74L8498
74L8533

3-102
3-102
3-102
3-102
3-102
3-102
3-102
3-102
3-102
3-102
3-102
3-102

....•....•..•.. 12-91
........•...•.• 12-91
.•............ 12-102
.• • . . . • . • . . . •. 12"102

.••.••........... 11-15
••....•••...•.... 11-15
.•..•..••....•... 11-15
..•...••......•.• 11-15
..••.••......•.... 12-6
................. 11-33
•...•..•••....... 11-23
.......••...••... 11-23
..•...••.....••.. 11-23
..•..........•..• 11-23
.•..••.....•..... 11-40
.......•..•.•..•. 11-40
•..•.••...•.•.... 11-33
.....••.....•....• 6-16
•.........•..••••. 6-24
..••...•.....•..•• 6-28
••...•.....•.....• 6-32
.....•..•.....•••. 6-36
..•...............• 6-4
....••......•....•• 6-8
.•..•.••..•.•••... 6-20
..•.......•....••. 6-12
••..........••.•. 11-50

74L8534 .................
74L8546 ........•.•......
74L8547 ....•............
74L8548 .................
74L8549 .................
74L8566 .••.....••.......
74L8567 .................
74L8645 .......••..•.••..
74L8645-1 .........•.....
74L8646 ...•.............
74L8647 •...........•...•
74L8648 ..•....•..••....•
74L8649 .....•...........
74L8651 .•...........•.•.
74L8652 .................
74L8653 •.•..............
74L8654 ••...............
74L8793 ...........•.....
74L8794 .................

11-50
12-14
12-14
12-62
12-62
12-14
12-14
12-10
12-10
12-34
12-34
12-34
12-34
12-47
12-47
12-47
12-47
12-74
12-74

748148 ..........•........ 9-12
748182 ...........••....... 9-9
748210 .................. 11-15
748225 ..................•• 7-8
748225A .....•............. 7-8
748240 .................. 11-15
748241 .......••.•....••. 11-15
748244 .................• 11"15
748273 ...•••••.•........ 11-33
748310 ..•••......••....• 11-23
748340 ....•..•.......... 11-23
748341 .•...•...••....... 11-23
748344 ..........•.••.••• 11-23
748348 ...•............... 9-12
748373 .....•••.•...•.... 11-40
748374 ...... ; .....•....• 11-40
748377 .................. 11-33
748381 .................... 9-3
748383 .••.......•.•.•... 11-46
748408 •................•• 8-10
748408-2 ....•............ 8-10

Monolithic WMemories

748408-3 ................. 8-1 0
748409 ...•....•••...•.•.. 8-27
748409-2 .........•..•.... 8-27
748409-3 ........••••..•.• 8-27
748419 ................... 15-5
748480 .......•......••••. 15-6
748508 ................... 10-8
748516 .....•.....•...•.. 10-21
748531 ....•......••..... 11-56
748532 ..........•....... 11-56
748533 .•...••.....•..... 11-50
748534 ••....•..•.....•.. 11-50
748535 .................. 11-60
748536 .....•••..••....•. 11-60
748700 .............•..... 8-51
748700-1 ......•.......... 8-51
748730 •.............•.... 8-51
748730-1 ......•••....•... 8-51
748731 ...••.....••..•.••• 8-51
748731-1 ...••............ 8-51
748734 ... 0 ••••••••••••••• 8-51
748734-1 .••..••••....•..• 8-51
748818 .............••... 12-79
748556 •...•....••...•.•• 10-37
748557 ...........•..•.•• 10-50
748558 .................. 10-50
67401 ....................... 7-28
67401A .......... ; .••..... 7-28
674016 ••....••......•...• 7-28
67402 ......•..... ; .•.....• 7~28
67402A •.•.........••...•. 7-28
674026 ••..•.•••.•.....••. 7-28
67413 ...••.•..•.••••..••• ; 7-57
67413A ..........•.••..•.• 767417 .: •.....•.....•...... 7-69
67L401 . . . . . . . . . • . . . . . . . .. 7-39
67L402 ...•....••••..••••. 7-48
10HPAL20P8 ..•...•...•.. 15"13
ZHAL .....•••....•......• 15-15

1-15

..

Tenns and Conditions of Sales

Monolithic Memories
Index
Terms and Conditions of Sale
General Provisions
1. ACCEPTANCE THE TERMS OF SALE CONTAINED HEREIN APPLY TO
ALL QUOTATIONS MADE AND PURCHASE ORDERS ENTERED INTO BY THE
SELLER. SOME OF THE TERMS SET OUT HERE MAY DIFFER FROM THOSE
IN BUYER'S PURCHASE ORDER AND SOME MAYBE NEW. THIS ACCEPT·
ANCE IS CONDITIONAL ON BUYER'S ASSENT TO THE TERMS SET OUT
HERE IN LIEU OF THOSE IN BUYER'S PURCHASE ORDER. SELLER'S FAILURE TO OBJECT TO PROVISIONS CONTAINED IN ANY COMMUNICATION
FROM BUYER SHALL NOT BE DEEMED A WAIVER OF THE PROVISIONS OF
THIS ACCEPTANCE. ANY CHANGES IN THE TERMS CONTAINED HEREIN
MUST SPECIFICALLY BE AGREED TO INWRITING BUY AN OFFICER OF THE
SELLER BEFORE BECOMING BINDING ON EITHER THE SELLER OR THE
BUYER. All orders or contracts must be. approved and acoepted by the Seller at its
home office. These terms shall be applicable whether or notthey are attached to or
enclosed wHh the products to be sold hereunder.

2. TAXES Unless otherwise specifically provided herein. the amount Of any pres'ent or future sales, revenue, excise or other tax applicable to the products covered
by this order or the manufacture of sale thereof, shall be added to the purchase
price and shall be paid by the Buyer, or in lieu thereof the Buyer shall provide the
Seller with a tax exemption certificate acceptable to the taxing authorities. In the
event Seller is required to pay any such tax, fee, or charge, at the time of sale or
thereafter, the Buyer shall reimburse Seller therefore.
3. RELEASE Prices apply only if the quantity hereunder is released wHhin twelve
(12) months and shipments scheduled no more than eighteen (18) months from
the date of Seller's receipt of Buyer's order; otherwise, Seller's standard prices in
eftect at the time of release date shall apply to the quanttty shippad, and Buyer
shall be invoiced for the difference in price, if any.
4. FOB POINT Shipments of goods within and outside the U.S. shall be delivered
FOB Seller's plant, and title and liabiltty for loss or damage thereto shall pass to
Buyer upon Seller's tender of delivery of the goods to a carrier forshlpment to
Buyer, and any loss or damage thereafter shall not relieve Buyer of any obligation
hereunder. Buyer shall reimburse Seller for taxes and any other expenses Incurred
or licenses or clearance required at port of entry and destination .. Seller may
deliver the goods in installments. Unless otherwise agreed, all items shall be
packaged and packed In accordance Wit~ Seller's normal practices.

5. DEUVERY All shipping dates are estimates only and are dependent upon
prompt receipt of all necessary information from Buyer. Shipments may be made in
installments. Sellllr shall be excused from. performance and shall. not be liable for
any delay in delivery or for nondelivery, in whole or in pari, caused by the oocu>
rence of any oontingency beyond the reasonable control of Seller, including but not
limited to, war (whether or not an acJual declaration thereof is made), sabotege;
insurrection, riot or other acJ of civil disobedience, acJ of a public enemy, failure or
.delay in transportation, act of any government or any agency or subdivision thereof
affecting the terms of this contracJ or otherwise, judicial action, labor dispute,
accident, defsults of suppliers, fire, explosion, flood, storm or other. acts of God,
shortage of labor. fuel, raw material or machinery or technical or Y.ield failures
where Seller has .exercised ordinary care' in the prevention thereof. H any such
contingency occurs, Seller may at its solll discretion allocate production and
delivery among Seller's customers.
6. PAYMENT TERMS (a) Unless otherwise agreed, payment terms are 700/.
thirty (30) days; 30% forty-five (45) days after date of invoice. No discounts are
authorizlld. Shipments, deliveries, and performance of work shall at all times be
subject to the apprOval of the Seller's credit department and the Seller may at any
time decline to make any shipments or deliveries or perform any workexcep! upon
receipt of payment or upon terms and condition or security satisfactory to such
department.
.

7. INSPECTION Unless otherwise specijied and agreed upon, the material to be
furnished under this order shall be subject to the Seller's standard Inspection at th.e
place of manufacture. If it has been agreed upon and specified in this order that
Buyer is to Inspect or provide for inspection at place of manufacJure such i~
lion shall be so conducled as to notint8rfere unreasonably with Seller's operatiOns
and !'Onsequerit approval or rejection Shall be made before.shipment of the materials. NotwHhstandlng the foregoing, if, upon receipt of such material by B.uyer, the
same s!]all appear not to conform to the' contract, the Buyer shall immediately
notify the. Seller of such conditions an(jafford the Seller a reasonable opportunity
to Inspect the material. No material sheil be returned Without Seller'S consent.
Seller's Return Malerial AuthOrization form must accompany such returned
material.
8. UMITED WARRANTY AND LIMITED REMEDY The Sellerwarrarits thBtthe
products to be. delivered under this purchase order will be free from .defects in
material and workmanship under normal use and service. Seller's cbligations under this Warranty, are limited to replacing or repairing or giving credit for, at its
option, at its faclory, any of said products which shall, wHhin one (1) year after
shipmen~ be returned to the Seller's factory of origin, transportation charges
prepaid, and which are, after examination, disclosed to the Seller's satlsfacJion to
be thus defective. THIS WARRANTY IS EXPRESSED IN LIEU OF ALL OTHER
WARRANTIES, EXPRESSED, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND OF ALL OTHER OBLIGATIONS OR LIABILITIES ON
THE SELLER'S PART, AND IT NEITHER ASSUMES NOR AUTHORIZES ANY
OTHER PERSON TO ASSUME FOR THE SELLER ANY OTHER LIABILITIES IN
CONNECTION WITH THE SALE OF THE SAID ARTICLES. This Warranty shall
not apply to any of such products which shall have been repaired or altered, except
by the Seller, or which shall have been subjected to misuse, negligence, or accident. The aforementioned proviSions do not extend the origlnill warranty period of
any product which has eHher been repaired or replaced by Seller.
It is understood that if this order catls for the delivery of semiconductor devices
which are not furnished and fully encapsulated, thai no warranty, statutoly, expressed or implied, including the implied warranty Qf merchantability and fitness fOr
a pariicular purpose, shall apply. All such devices are sold as-Is, where-is.
9. PATENT INDEMNIFICATION Buyer shall hold Seller harmless from and
defend Seller against any cost, expenses, damages or liabilities arising from Seiler's .compliance With Buyer's designs or specifications. Except as set forth above,
the Seller agrees.to protect and hold barmless the Buyer from any and all claims,
demands, proceedings, actions, liabHities and costs resulting from any alleged
infringement of patents in the United States owned by third parties by products
purchased by Buyer from Seller, provided the Buyer gives to Seller prompt notice
of any such claim· made against the Buyer and authorizes the Seller to settle or
defend any such claim, demand, proceeding or acJion and assists the Seller. In so
doing (at the Seller's expense) upon request by the Seller. Should, as a rSsuJi of
any such claim, demand, proceeding or acJion, the Buyer be enjoined from selling
or using the prodUC!, the Seller ehall.either (1) procure for the Buyer the right to use
or sell the producl; (2) modijy the product so thet It becomes noninfringlng; (3)
upon return of the product provide to the Buyer a noninfringing product meeting the
same functional speCifications as the product; 0; (4) authorize the retiJrn of the
product to the Selle. and upon its receipt refund to the Buyer the cost of the produCt
plus.transportation ,charges. The foregoing states the entire liabiltty olthe Seller for
Infringement of·the patents of .third parties and, in particular, the Seller has 'rio
obligation to indemnify the buyer for infringement of patents resulting from cornblnations of the product with other products whether or not supplied by the Seller.
THIS PROVISION IS STATED IN LIEU OF ANY OTHER EXPRESSED, IMPLIED,
OR STATUTORY WARRANTY AGAINSt INFRINGEMENT AND SHALL BE THE
SOLE AND EXCLUSIVE REMEDY FOR PATENT INFRINGEMENT OF ANY
KIND.

(b) If in the judgment of the Seller, the financial condition of the Buyer at any
time does not juatily continuation of production or shipment on the terms of payment originally specified, the Seller may require full or partial payment in advance
and, in the event of the bankruptcy or insolvency of the Buyer or in the event any
proceeding is brought by or against the Buyer under the bankruptcy or insolvency
laws. the Seller shall be entitied to cancel any order then outstanding and shall
receive reimbursement for its cancellation charges.

10. DAMAGE UMITATION INDEPENDENTLY OF ANY OTHER LIMITATION
HEREOF AND REGARDLESS OF WHETHER THE PURPOSE OF SUCH
LIMITATION IS SERVED, IT IS AGREED THAT IN NO EVENT SHALL SELLER
BE LIABLE FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF
ANY KIND UNDER THIS ORDER.

(c) Each shipment shall be considered a separate and independent transection,
and payment therefore shall be made accordingly. If shipments are delayed by the
Buyer, payments shall become due on the date when the Seller is prepared to
make shipment. If the work covered by the purchase order is delayed by the Buyer,
payments shall be made based on the purchase price and the percentage of
completion. Products held for the Buyer shall be at the risk and expense of the
Buyer.
•

11. SALE CONVEYS NO UCENSE Seller's producJs are offered for sale and are
sold by Seller subject in every case to the condition that such sale does not convey
any. license, expressly or by implicatiQn, estoppel or otherwisa, under any patent
claim With respect to which Seller can grant licenses covering a completed equipment, or any assembly, circuH, combination, method or process In which any such
products are used as components (notwHhstandlng the lacJ that such products
may have been designed for use in or may only be usatul in, such patented

1·16

MonoIlthloW.emorieS

Terms and Conditions of Sales

Monolithic Memories
Index
Terms and Conditions of Sale
General Provisions
equipment, assembly, circuit, cembination, method or process and that such products may have been pUl(:hasad and sol,d for such use), Seller e\cpressly reserves
all its rights under such patent claims.
12_ RETURNS AND ADJUSTMENTS Products may only be returned w~h prior
written approval of Seller. Adjustments for defective products are subject to Selle(s cencurrence thai the alleged defects exist, to Selle(s satisfaction, after
suitable inspectk>n and test by Seller. Adjustments may include cred~ or replacement at ,the option of the Seller.
13. TERMINATION AND CANCELLATION (a) Buyer may terminate this centract in whole or, from time to time, in part upon written notice to Seller. In such
event Buyer shall be liable for termination charges which shall include a price
adjustment basad on the qu~ of goods actually delivered; and all ccsts, direct
and indirect, incurred and committed for this contract together with a reasonable
allowance for prorated expenses and antiCipated profits.
(b) Unless otherwise specHied on the face hereof, all qua~ies must be
released no mote than twelve (12) months and shipments scheduled no more than
eighteen (18) months from the date of Seller's receipt of Buye(s oroer, otherwise
this centract may be cancelled by Seller end Buyer shall be liable for termination
charges as provided herein.
14. NONWAIVER OF DEFAULT In the event of any default by Buyer, Seller may
decline to make further shipments. II Seller elects to centinue to make shipments,
Selle(s ection shall not censtitute remedies for any such default.
15. APPUCABLE LAW The validity, performance and constructiOn of this contractshall be governed by the laws of the State of California.
16. U.s. GOVERNMENT CONTRACTS II Buye(s original purchase order indicates by centract number, that R is plaoed under a government centract, only the
following provisions of the current Federal AoquisiUon Regulations are applicable
in aoccrdance with the terms thereof, with an appropriate substitution of parties, as
the case may be-I.e., "Contracting Officer" shall mean "Buyer," "Contractor"
shall mean ':Seller," end the "Contract" shall mean this order.
,

gent Fees; 52.249-1, Termination lor Convenience 01 til!> Government (Fixed
Price) (Short Form) (only to the extent that Buye(s centract is terminated for the
convenience of the government); 52.2-1, Contractor Inspection Requirements;
52.227-1, Authorization and Consent; 52.227-2, Notice and Assistance Regarding,
Patent and Copyright Information; 52.247.1, Commercial Bills of lading Notations;
52.223-35, Alfinnative Action for Special Disabled end Vietnam Era Veterans;
52.222-1, Notice to the Government of Labor Disputes; 52.215: f, Examination 01
Records by Comptroller General; 52.220-3, Utilization 01 labor Surplus Area
Concerns.
17. ASSIGNMENT This ccntract shall be binding upon and in~re to the benefit 01
the parties and the successors and assigns 01 the entire business end good will 01
either Seller or Buyer, or 01 that part 01 the business 01 either '-Ised in th" performance of this centract, but shall not be otherwise assignable. '
18. MODIFICATION This contract constRutes the entire egreement between the
parties relating to the sale 01 goods described on the lace hereof; and no addition
to or modHlcaUon of any provision upon the face or reverse 01 this centract shall be
binding upon Seller unless made in writing and signed by a duly authorized repre_tive 01 Seller located in Santa Clara, California. Buyer hereby aCknowl<8PROM)

Listings are based on OPL-38510-61. dated 1 October 1984.

M38510
Slash Sheet Cross Reference to Generic Part Number
M38510

01

02

203

5300-1

5301-1

204

535240

538241

206

5~

53844i

207

53S08(}'

538081

208

5340-2

5341-2

209

53S84O

535841

04

211

05

07

06

06

10

09

.

,

,-'-

5348-2 ...
5380-2 '

..

5349-2

5381-2
(Will be adding 5381641)

5351681

210

5383281
12H6

503

10H8

504

16lBA

16R8A

505

20lBA

20RBA

2·4

03

14H4

16H2

16Cl

1018

1216

1414

16L2

16RBA

16R4A

16X4

lBA4

16lBA-2

16RBA-2

16R6A-2

20RBA

20R4A

16R4A-2

DESC Drawing Program
Monolithic Memories is an active participant in the DESC Drawing Program. For contracts invoking MIL-STD-454 we offer our
full PAL product line to DESC Drawings 81035 and 81036.
Monolithic Memories is also approved to supply the 32K PROM
to DESC Drawing 82008. The idea behind the DESC Drawing
Program is to standardize MIL-STD-8838 microcircuits where
fully qualified JAN product is not available. The advantage to
the user is that DESC Drawings are a cost effective alternative
to source control drawings and are offered as off-the-shelf
stocking items by IC manufacturers participating in the program.
Since semiconductor demand is on the rise, and lead times will
be a major concern, DESCDrawings should always be considered to improve availability over source control drawings. It is

standard practice at Monolithic Memories to convert our 8838
processing to DESC Drawings for all products which we are
approved to supply. Monolithic Memories Inc. then dual marks
devices with both the DESC Drawing Number and the Generic
Part Number. DESC approved products can then be procured
to either part number as standard product through both OEM
and distributor channels.
The following cross reference will allow you to determine the
appropriate DESC Drawing part numbers for each PAL product
and the 32K PROM. Future DESC print activity will inclde new
PAL products and registered PROMs. Monolithic Memories will
work with DESC to continually generate new drawings, which
will provide a steady flow of advanced technology products to
standardized specifications.

DESC Drawing/Generic Part 'lYpe Cross Reference
DESC DRAWING PART NO.:

81035

01

Y

X

DRAWING NO.

DEVICE TYPE

CASE OUTLINE

LEAD FINISH

Small PAL 20 Devices:
DESC Drawing

Generic Part Number

Replacement JAN Specification
Part Number

8103501RX
81035012X
8103501YX
8103502RX
81035022X
8103502YX
8103503RX
81035032X
8103503YX
8103504RX
81035042X
8103504YX
8103505RX
81035052X
8103505YX
8103506RX
81035062X
8103506YX
8103507RX
81035072X
8103507YX
8103508RX
81035082X
8103508YX
8103509RX
81035092X
8103509YX

PAL 10H8MJ883B
PAL 1OH8ML883B
PAL 10H8MF883B
PAL 12H6MJ883B
PAL 12H6ML883B
PAL12H6MF883B
PAL14H4MJ883B
PAL14H4ML883B
PAL 14H4MF883B
PAL 16H2MJ883B
PAL16H2ML883B
PAL 16H2MF883B
PAL 16C1MJ883B
PAL lSC1ML883B
PAL 16Cl MF883B
PAL 10L8MJ.883B
PAL 10L8ML883B
PAL 1OL8MF883B
PAL 12L6MJ883B
PAL12L6ML883B
PAL12L6MF883B
PAL14L4MJ883B
PAL 14L4ML883B
PAL 14L4MF883B
PAL 16L2MJ883B
PAL16L2ML883B
PAL 16L2MF883B

M3851 0/50301 BRX
M3851 0/50301 B2X
M3851 0/50301 BYX
M38510/50302BRX
M38510/50302B2X
M38510/50302BYX
M38510/50303BRX
M38510/50303B2X
M38510/50303BYX
M38510/50304BRX
M38510/50304B2X
M38510/50304BYX
M38510/50305BRX
M38510/50305B2X
M38510/50305BYX
M38510/50306BRX
M38510/50306B2X
M38510/50306BYX
M38510/50307BRX
M38510/50307B2X
M38510/50307BYX
M3851D/50308BRX
M38510/50308B2X
M38510/S0308BYX
M38510/50309BRX
M38510/50309B2X
M38510/50309BYX

Monolithic

W Memories

2-5

New DESC Drawing Number Insert

Medium PAL2Q Devices
DESC DRAWING
8103601RX·
8103601.2X
8103601YX
8103602RX
81036022X
8103602YX
8103603RX
81036032X
8103603YX
8103604RX
81036042X
8103604YX
810360SRX
810360S2X
810360SYX
8103606RX
81036062X
8103606YX
8103607RX
81036072X
8103607YX
8103608RX
81036082X
8103608YX
8103609RX
81036092X
8103609YX
8103610RX
81 0361 02X
81 0361 OYX
8103611RX
81036112X
81 03611 Yx
8103812RX
81036122X
8103812YX
8103613RX
81(36132)(
B103613YX
8103614RX
81036142X
8103614YX
8412901JX
84129013X
8412902JX
84129023X
8412903JX
841~9033X

8412904JX
88412904JX
84129043)(

GENERIC PART NUMBER
PAL 16L8MJ883B
PAL16L8ML883B
pAL16L8MF883B
PAL16R8MJ883B
PAL 16R8ML683B
PAL 16R8MF883B
PAL16R6MJ883B
PAL16R6ML683B
PAL16R6MF883B
PAL16R4MJ883B
PAL16R4ML683B
PAL 16R4MF883B
PAL16x4MJ883B
PAL 16x4ML683B
PAL16x4MF883B
PAL 16A4MJ883B
PAL16A4ML683B
PAL16A4MF883B
PAL 16L8AMJ863B
PAL 16LBAML883B
PAL.16L8AMF883B"
PAL16R8AMJ883B
PAL16R8AML883B
PAL16R8AMF883B"
PAL 16R6AMJ883B
PAL 16R6AML883B
PAL 16R6AMF883B"
PAL16R4AMJ883B
PAL16R4AMl883B
PAL 16R4AMF883B"
PAL 16L8A-2MJ883B
PAL16L8A-2ML883B
PAL16L8A-2MF883B"
PAL16R8A-2MJ883B
PAL 16R8A-2MLB83B
PAL 16R8A"2MF883B"
PAL 16R6A-2MJB83B
PAL 16R6A~2ML883B
PAL16R6A-ZMF883B"
PAL16R4A~2MJ883B
PAL 16R4A-2ML683B
PAL 16R4A-2MF883B"
PAL20L8AMJ883B
PAL20L8AML883B.
PAL20R8AMJ883B
PAL20R8AML883B
PAL20R6AMJ883B
PAL20R6AML883B
PAL20R4AMJ883B
PAL20R4AMJ883B
PAL20R4AML883B

~EPLACEMENT JAN. SPECIFICATION

PART NUMBER
M38S1 0/S0401 BRWt
M38S10/S0401 B2X'
M38S10/S0401BYX'
M38S1 0/S0401 B2X't
M38S10/S0402B2X'
M38S10/S0402BYX'
M38S10/50403BRX'
M38S10/S0403B2X'
M38S1O/S0403BYX'
M38S10/S0404BRX't
M38S10/S0404B2X'
M38S10/S0404BYX'
M38S10i'50405BRX
M38510/S040SB2X
M38S10/5040SBYX
M38S10/S0406BRX
M38S10/S0406B2X
M38S10/S0406BYx
M38S1 0/S0401 BRXt
M38S10/S0401 B2X
M38S1 0/50401 BYX
M38S10/S0402BRXt
M38S10/S0402B2X
M38S10/50402BYX
M38S10/S0403BRXt
M38510/S0403B2X
M38S10/50403BYX
M38S10/SD404BRXt
M38S10/S0404B2X
M38S10/S0404BYX
M38510/50407BRX
M38510/50407B2X
M38510/50407BYX
M38510/50408BRX
M38510/50408B2X
M38510/50408BVX
M38510/S0409BRX
M38510/50409B2X
M38510/50409BYX
M385tO/50410BRX
M38510/50410B2X
M38510/50410BYX
M38S1 0/50501 BJX
M3851 0/50501 B3X
M38510/50502BJX
M38510/5050293X
M38510/50503BJX
M38510/50503B3X
M38510/S05Q4BJX
M38510/50504BJX
M38510/5050493X

PROM:
82008B1JX
82008B2ZX

53S3281 MJ883B
5353281 ML683B

M3851 0t;111 02BJX
M38510/21102B2X

•. For New Medium 20-pin PAlDesigrls. only Ihe "A" versions of Ihese products are ri!commended. (See DESC Nos 8103607 Ihrough·'8103610). Only Ihe "A" .
versions of the me(Uuf.O PAL family are planned for JAN qualification by-Monolithic Memories Inc., and will be more readily available for cu'stomer production
needs over time.

*'"

The Military Products Division will be converting from the bottom-brazed flatpack toa "W" package cerpack during 1985.

t .Inactive for new design for Ihe R :Cas.eouiline only. Use applicable QPl M3a51 0 device.

QUality Programs
The Military Product Division quality system conforms to the
following MiI.standards:
Mil-M-38S10, Appendix A, "Product ASsurance Program"
Mil-Q-9858, "Quality Program Requirements"
MiI-I-45208, "Inspection System Requirements"
Monolithic Memories facilities in Sunnyvale are certified by the
Defense EleCtronics Supply Center (DESC), to manufacture
and qualify Schottky Bipolar PROMsand PAL CircuitS in accordance with Mil-M-38510 Class B. ThiS certification was a
result of a successful audit of our production and quality
systemstothestringent requirements of MiI-M-3851O. Monolithic
Memories has also demonstrated compliance with the strict
requirements of both controlled and captive lines connected
with special Military programs.

QualityAaaurance
Following 1000/0 scr~ning, the Military Products Division samples all prodUcts processed iri conformance with MIL-STD-883
Class B to the folloWing LTPD levels:

Teat
DC 25°C
DC +125°C
DC.,.55°C
Functional at 25°C
Functional at Temperature Extremes
AC25°C
~~~C

AC-55°C

LTPD
2
3
5
2.
5
2
3
5

The Military Products Division ensures outgoirig product quality and integrity by performing inspectiOri Lot Group'A's and B's
per Mil-Std-883M!!thod5005, conducting self audits in all areas
involved in screening tests per Method 5004 of Mil-Std-883,
gating all shipments to Our customers, and maintaining a calibration Control system In accordance with MiI.std-45662.
For products requiring programming prior to AC tests; testing
is performed utilizing MIL-M-38510 Slash Sheetsainpleplans.

Product Qualificatlonl

Gtiallty Conformance Ins.,.ctic)n(GCI)
The Military Products Division has a quality conformance testing program in accordance with MiI.std-883, Method 5005.

Quality Conformance Testing provides necessary feedback
and monitors several areas:
•
•
•
•
•

Reliability of ProductlProcesses
Vendor Qualification for Raw. Materials
Customer Quality Requirements
Maintain Product Qualification
Engineering Monitor on .Products/Processes

Stan.dard procedures for "!lW product .release specify that
Monolithic Memories' Reliability'Department, as:a minimum,
conduct full qualification testing per Method 5005 of Mil-Std883. Once qualified, each package type (from each assembly
line) and device. (by technology group as delineated in MiI-M38510) are incorporated into Monolithic Memories Quality ConformanC!! lrispection program which utilizes thi;i requirements
of MilcM-38510.
When Military Programs do not require that QCI data be run on
the specific 10tshipped,Monolithic Memories Quality Conformance program allows customers to obtain generic data on all
product flimilil!$ manufactUred'bythe Military Products Division. Generic Qualification Data enables customers·toeliininate costly qualification and desctruct unit charges, .and also.
improves delivery time by a 'factor of eight to ten weeks. The
fOlloWing generic"data is aVailable:
.
.

Group B-Package ntlated tests
• Qel is performed .every 6 weeks of manufacture on each
package type.
• Any device type in the same package type may be used
regardless of the specific part number.
• Purpose: To monitor asllembly integrity.

Group C-Product/Pr0ce8s ~ated tests
• QCI is performed every 13 weeks of manufacture,on repre-·
sentative devices from the same micrOCircuit group,
• Life test data.may be used to qualify simUar technologies.
• P!.!.rpose: To monitor the reliability 01 the process and.parametric performance for each product technology;
• Monolithic Memories Group.O~neric Families:
1.. Programmable Product
-PROMS-SchQttky Nichrome
~PROMg.::Titanium Tungsten
'';:''''PAL CircuitS
..
.
2. Logic, Multipler, Fifo
3. Octallnterflice

AfonoIIIhlCW""emorles

Group D - In-depth package related testa
• QCI is conducted every 26 weeks using devices which
represent the same package construction and lead finish.
• Any device type in the same package type may be used
regardless of the specific part number.
• Purpose: To monitor the reliability and Integrity of various
package materials and assembly processes.

Generic Data:
Monolithic Memories Generic Data Program is based on MILM-38510, which allows for shipments based on 26 weeks of
coverage for Group C Testing and 36 weeks of coverage for
Group D Testing
Should circumstances arise where generic coverage to MIL-M38510 is not possible, Monolithic Memories reserves the right to
ship product based on 52 weeks of generic Group C and/or D
coverage per MIL-M-883 Revision C, Paragraph 1.2.1b (17)
dated 15 August 1984.
.

Manufacturing and Screening Locations
JAN Products, Monolithic Memories Modified Level "S;' and
customer orders which call for U.S.A assembly, are manufactured in our DESC certified assembly line in Sunnyvale, California.
MiI~Std-883 Class B products, and orders to source control
drawings, where stateside build is not required, are assembled
at our Penang. Malaysia faCility. This facility is qualified by
Monolithic Memories Quality Department, as well as by many
of oui-customers, to manufacture Mil-Std-883 Class B product.
Conformance to Mil-Std-883 requirements is routinely monitored through audits at the Penang facility, as well as incoming
inspections in Sunnyvale prior to completion of Burn-In and
Final Test. Manufacturing capabilities for each Monolithic
Memories facility are highlighted on the chart below.

Manufacturing Capabilities
Assembly
Precap Inspection
Environmental Testing
Electrical Pre-Test
Bum-In
Post Bum-In Electrlcals
Group A Testing
Mark
Fadory Programming (when applicable)
Qualification and Quality
..
Conformance Testing

Sunnyva~

Panang

x

X
X

X
~
X

X
X

X
X
X

X.
X
X
X

X

X

To identify the assembly location of each military device, the
Country of origin is marked on all products prior to, shipment.
Products assembled. in our stateside facilitY in Sunnyvale, California, will have "US)I:' marked·on the topside ofthe device. The
exception to this is JAN 38510 product, whio,h is rnl\rked to the
Mil-M-38510requirements only.
Offshore built product, which. ill .manufactured in .. Penang,
Malaysia, will have "Malaysia" marked on the bottornsic;leofthe
device.
Marking Example:
USA

2-8

AC'ntstlng
Although Monolithic Memories offers a large selection of programmable products, it must be pointed out that AC Testing
cannot be performed on many of our product types without
their being programmed. For those devices which must be
programmed prier to, ACTests and are ordered unpregrammed,
Monolithic Memeries must "guarantee" their AC Perfermance.
Newer devices in the PROM and PAL families do allow preprogram AC testability.
Since the guaranteeing ef parameters can be a serieus concern
for the Military user, we have outlined··severalsppreaches to
address the AC screening issue~
1. Monolithic Memories can pull a Sample from a lot using our·
own Standard pattems (designed to, blew in excess of 50
percent of the fuses) and perform AC testing at 25·C, and
temperature extremes.
a) PAL products processed to DESC prints include programmability samples and AC testing at reem temperature as a standard.
b) AC at high- and lew-temPerature extremes is a cest adder
to, standard precessing.
2. Menelithic Memoi-ies can program parts using custem pregrams submitted by the custemer. AC can then be denewith
the fellewing optiens:
.
a) Sample AC at 25ci C
b) Sample AC at 25·C, -55·C, 125·C
c) 100% AC at 25·C
d) 1OO%AC at 25· C, -55· C and 125· C (net available on PAL
products)
Options bthreugh d are cqst adders to, basic processing.
On PAL products where custem programming is perfermed
and AC testing is required, additional vector generation and
fault coverage analysis is required, as well as AC program
checkout. Non-recurring engineering charges are applicable to
this type of requirement.
To give you an idea of delivery differences for the ·options
discussed above, general lead times are as follows:
• Unprogrammed:
Cerdip, 4-6 weeks
Flat pack, 8-12 weeks
Leadlelis, 6-12 weeks
(consult monthly leadtime guide for individual part types).
• Unprogrammed product using our standard pattero to verify
ACat room temperature on sample basis (option 1); Add 2
weeks to standard delivery.
• Programmed productusing customer programs with sample
AC (option 2a and b). Contact factory for delivery. Delivery
quoted will be after receipt of customer design package.
• 100% AC.testing at 25·C-S.tandard Monolithic Memories
pa~!,!rn or customer pattern, (option c). 9<>ntact factory.
Remember, for ProPALs, customer must provide design package includin!;j Boolean Ecjuations,"~" Junctio!1.teSt sequ",nce, package stipulation and ACtestvectors, when required,
Delivery. quotes for this type of product begin after receipt of
thisdsta from the customer.

VIL/VIH Parametric Informalion
VIL and VIH as specified are input conditions at which the device
is designed to meet all D.C. and functional performance
characteristics.
Typical test conditions used forVIL and VIH areO.O and 3.0volts.
When utilizing these as input conditions for testing purposes,
consideration must be given to test equipment noise levels and
equipment limitations. VIL and VIH limits are absolute values with
respect to the ground pin(s) on the device and includes all
overshoots due to test equipment noise.

An ESD identifier is marked on all products in front of the date
code, and all shipping containers are labeled with an ESD
Caution Message. These procedures have been implemented,
and will continually be reviewed, to ensure.that our customers
receive only the highest quality product form the Military
Products Division.

Major Program Participation

ElectroStatic Discharge
The Military Products Division of Monolithic Memories has fully
implemented static control procedures throughout its facilities
in Penang, Malaysia and Sunnyvale, California.
All manufacturing areas where product is processed or handled,
including our Reliability Labs, Engineering Labs, etc., have full
static control such as wrist straps, antistatic smocks, grounded
stainless steel tables, conductive mats and ion generators
wherever necessary.
All product is moved throughout our facilities and shipped to
customers in static shielded containers.

Monolithic Memories is a supplier of Military components to
most major Department of Defense Programs. A partial listing
of program participation is provided.
AMRAAM
ASPJ
AWACS
B-1
B-52
BATSON
CRUISE
DIVADS

Monolithic f!ilIMemorles

F-15
F-16
F-18
HARM
HARPOON
HAWK
HELLFIRE
IUS

LAMPS
LATIRN
MILSTAR
PATRIOT
PERSHING
PHALANX
SIDEWINDER
SPARROW

SUBACS
TRIDENT
UYK-43
I,JYK-44
VLS

...o•

~

Military PROM Performance Analysis
(Max. Military Limits - Three State Only)
Size
XK
32x8
1K
256x4
2K
256x8
2K
518X4

J

8
s:==cr

EJ

f
~

::L

=

4K
512x8

4K
1Kx4
8K
1Kx8
8KReg
1Kx8
8K
2Kx4
16K
2Kx8
16K Reg.
2Kx8
16K
4KX4
16K Diag.
4Kx4
32K
4Kx8

*

TCLK.

MMI
Part No.
TAA/lcc
5331-1
538081

5301-1
538141
5309-1
5306-1
538241
5341-1
5341-2
5349-1
5349-2
53RA481
53RA481A
538441
538441 A
53DA441
53DA442
5381-1
5381-2
53R8881
53R8881A
538841
538841 A
5381681
5381681A
53RA1681
53RA1681A
53R81681
53R81681A
5381641
5381641A
53D1641
53DA1643
5383281
538321 A

60/125
35/125

-

AMD
Part No.
TAA/lcc
27819
27819A

-

75/130
55/130

27821

80/155

-

75/130
55/130
80/155
70/155
80/155
70/155
* 25/180
*20/180
55/140
50/140
*25/180
*25/180
125/175
70/175
*25/180
*20/180
55/150
50/150
60/185
45/185
*25/185
*20/185
*25/185
*20/185
65/175
50/175
*25/190
*25/190
60/190
50/190

27813
27813A

27831

27829
27825
27825A

-

Raytheon
Part No. TAA/lcc

National
Part No. TAA/lcc

Signetics
Part No. TAA/lcc

Part No.

TI
TAA/lcc
50/110

-

-

7603-2

60/130

-

-

-

-

548288

45/110

65/85
35/110

-

-

-

-

-

828123
828123A

188030

-

-

-

-

-

-

75/130
65/130

60/130
-

70/125
35/125

75/100

-

828129
828129A

24810

-

7611-2
7611A-2

548287

60/130

-

-

-

-

28L22

75/100

-

-

50/115
35/115

-

-

-

-

-

54L8471

70/100

60/130
40/130

29611A

60/130

-

-

548571
548571A
548474

65/130
60/130
75/170

828131
828131A
828141

70/140
35/140
90/185

-

-

28846

70/135

-

-

-

-

-

-

29621
29621A

80/155
60/155

85/130
70/130
85/170
70/170
80/170

-

-

7621-2
7621A-2
7641-2
7641A-2
7649-2

75/165
60/165

70/135

-

828147
828147A

28842

-

-

75/170
60/155

-

548472
548472A
778R474

-

-

-

70/175

70/160
30/185
25/185

-

-

-

45/145
30/190
30/190

-

-

-

278181
27837
27837A
278185
278185A
278191
278191A
27845/47
27845/47A
27845/47
27845/47A
27841
27841A
27885
27885
27843
27843A

80/185
30/185
25/185
55/150
45/150
65/185
50/185
30/185
25/185
30/185
25/185
65/170
50/170
30/190
30/190
65/185
55/185

27833A
27865
27865

Harris
Part No. TAA/lcc

-

-

-

-

-

-

-

-

-

-

-

548573A

60/140

828137A

70/150

-

-

-

-

-

-

-

-

-

-

-

-

-

7681-2

90/170

-

-

-

828181
828181A

90/185
80/185

28886
28886A

65/170
50/170

-

-

-

-

-

29631
29631 A

90/170
60/170

-

-

-

-

-

29651 A

70/170

7685-2

-

90/170

778181

75/170

-

-

-

-

-

-

-

-

-

-

-

828185A

80/160

24881

85/175

-

-

-

778185

75/140

-

-

-

-

-

-

29681 A

70/180

76161-2

80/180

778191

80/175

828191A

70/185

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

76165-2

80/170

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

29671A

80/195

75/190

778321

-

-

-

-

-

76321-2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

65/190

828321

80/185

-

-

-

-

-

-

-

-

-

-

-

~

;:

.2

"~a=
'I

i.

:I
CD

::::I

a
~
::::I

CD

j

;.

Ordering Informalion

Package Informalion
Leadless Chip Carrier/Pin Grid Array
Monolithic Memories' Military Products Division offers, with few
exceptions, our entire product line in square, ceramic/gold
lead less chip carriers. In addition, we also offer the MEGAPAL
64R32 and the 54S556 in a square, ceramic/gold 88-pin-gridarray package.
INTERFACE CIRCUITS
• 20 square LCC
PROM CIRCUITS (Programmable Read Only Memories)
, 20 square LCC
• 28 square LCC

ARITHMETIC ELEMENT/LOGIC CIRCUITS
• 20 square LCC
MULTIPLIER CIRCUITS
• 44 square LCC
• 84 square LCC (cavity down)'-

PLE CIRCUITS (Programmable Logic Elements)
• 20 square LCC
• 28 square LCC

DRAM CONTROLLERS/DRIVER CIRCUITS
• 52 square LCC

PAU*HAL CIRCUITS (Programmable Array Logic)
• 20 square LCC
• 28 square LCC
• 44 square LCC
• 84 square LCC

PAU*HAL CIRCUIT (Programmable Array Logic)
• 88 square PGA
MULTIPLIER CIRCUIT
• 88 square PGA

HMSI CIRCUITS (High-Complexity Medium Scale Integration)
• 28 square LCC

Monolithic

FIFO CIRCUITS (First-In-First-Out Memories)
• 20 square LCC
• 28 square LCC
8 BIT/DOUBLE-DENSITY INTERFACE CIRCUITS
• 20 square LCC
• 28 square LCC

*

HALs are the mask-programmable versions of PAls.

W Memories

2-11

Notes

2 .. 12

~

:

~

13

Table of Contents
PROMs

Contents of Section 3 ...............•...........•..... 3-2
PROM SelectionG,uide ....•....•.................... 3-3
PROM Cross Reference Guide .............•.......... 3-4
TiW PROM Family
Standard TiW ........... 3-5
53/63S080
. 32x8 bit
Standard TiW ........... 3-5
53/63S08.1
32x8 bit
Standard TiW ......•.... 3-5
63S081 A
32x8 bit
Standard TiW ........... 3-9
53/63S14O
256x4 bit
Standard TiW ........... 3-9
53/63S 141
256x4 bit
Standard TiW ........... 3-9
53/63S141A
256x4 bit
Standard TiW ....••.... 3-13
53/63S240
512x4 bit
Standard TiW .•........ 3-13
53/63S241
512x4 bit
Standard TiW .•.....•.. 3-13
53/63S241A
512x4 bit
Standard TiW .......... 3-17
53/63S280
256X8 bit
Standard TiW .......... 3-17
53/63S281
25Sx8 bit
Standard TiW .......... 3-17
53/63S281A
256x8 bit
Standard TiW .......... 3-21
53/63S440
.1024x4 bit
StandardTiW ..... : .. ;. 3-21
53/638441
1024x4 bit
Standard TiW .......... 3-21
53/63S441A
1024x4 bit
Standard TiW .........• 3-25
53/638480
512x8 bit .
Standard TiW .......... 3-25
53/638481
512x8 bit
Standard TiW .......... 3-25
53/63S481 A
512x8 bit
Standard TiW ...•...•.. 3-29
53/63S841
2048x4 bit
Standard TiW .. .. .. .... 3-29
53/63S841A
2048x4bit
53/63S1641 .
4096><4 bit
Standard TiW .......... 3-33
Standard TiW ..... ... . .. 3-33
53/63S1641A 4096x4 bit
Standard TiW .......... 3-37
53/63S1681
2048)\8 bit
Standard TiW .......... 3-37
53/63S1681A 2048x8 bit
Standard TiW .......... 3-41
53/63S3281
4096x8 bit
Standard TiW ..•....... 3-41
53/63S3281A 4000)\8 bit

3-2

53/63RA481
53i63RA481A
53/63RS881
53/63RS881 A
53/63RA1681
53/63RA1681A
53/63RSl881
53/63RSl881A
53/63DA441
53/63DA442
53/63DA841

512x8 bit
Registered ..•..•....... 3-45
512x8 bit
Registered .....•....... 3-45
1024x8 bit
Registered ..........•.. 3-50
1024x8 bit
Registered. . . . . . . . . . . .. 3-50
2048X8 bit Registered w/Asyn. Enable .. 3-55
2048x8 bit Registered w/Asyn. Enable .. 3-55
2048x8 bit Registered w/Sync. Enable .. 3-60
2048x8 bit Registered w/Sync. Er)able .. 3-60
1024x4 bit Diagnostic Registered
3-65
1024x4 bit Diagnostic Registered
3-65
2048x4 bit Diagnostic Registered
with Asynchronous Enable
and Output Initialization ..•......... 3-76
53/63Dl641 '4096x4 bit Diagriostic Registered ...... 3-84
53/63DAl643 4096x4 bit Diagnostic Registered
Output Initialization .•....•......... 3-92
TiW PROM Programmer Reference Chart ..•.......•. 3-100
Generic NCR Family .............................. 3-102
53/6308-1
256x8 bit
Standard PROM ...•... 3-102
53/6309-1
256x8 bit
Standard PROM ....... 3-102
53/6340-1
512x8 bit
Standard PROM ....... 3-102
53/6341-1
512x8 bit
Standard PROM ....... 3-102
53/6341-2
512x8 bit
Standard PROM ....... 3-102
53/6348-1
512x8 bit
Standard PROM ....... 3-102
53/6349-1
512x8 bit
Standard PROM ....... 3~102
53/6349-2
512x8 bit
Standard PROM ....... 3-102
53/6380-1
1024x8 bit
Standard PROM .....•. 3-102
53/6380-2
1024x8 bit
Standard PROM ....... 3-102
53/6381-1
1024x8 bit
Standard PROM ....... 3-102
53/6381-2
1024x8 bit
Standard PROM ....... 3-102
NiCr PROM Programmer Reference Chart ..........• 3-109

MonoIlthlcmMemorles

PROM SELECTION GUIDE
PROMS

I;

I.
w

•'<,"
W

Device
Pins
. Number
.53/63S080
16
.53/63S081
(20)
63S081 A
53/63S140
16
.53/63S141
(20)
53/63S141A
53/63S240
1.6
53/638241
(20)
53/63S241A
53/6308-1
20
53/6309-1
53/635280
20
53/63S281 .
(20)
53/63S281 1\
'. 53/638440
18
53/63S441
(20)
53/63S441 A
53/6340-1
24
53/6341-1
(28)
.53/6341-2
53/6348-1
53/6349-1
20
. 53/6349-2
53/63S480
20
53/63S481.
(20)
53/63S481A
53/63S841
18
(28)
53/63S841A
53/6380-1
53/6381-1 .
24
53/6380-2
53/6381-2
,63S880*
24
638881*
(28)
63S881A*
53/63S1641
20
53/63S1641A
24
63/63S1681
53/63S1681 A .' (28) .
24
53/63S3281
53/63S3281A .(28)
*Preliminarv information

REGISTERED PROMS
Size
~K

32x8
1K
256x4
2K
512><4

2K
2.56><8

4K
1Kx4

Icc (mA)
Com'l/Mil

TS
.TS

TAA(ns)
Com'I/Mil
2.5/35
25/35
/25
45/55
45/.55
30/40
45/55
45/55
35/45

OG

70/80

1.55

Output

oe
TS
TS

oe
TS
TS

oe
TS.

oe

T8 .
TS

oe
TS
TS

. oe'
TS

'1"$
4K
512x8

OC
TS
TS

oe

8K
1Kx8

32K
4Kx8

TS
,

24
(28)
24
(28)

4K
512.x8
8K
1Kx8

24
(28)

16K
2Kx8

---

Output
TS
TS
TS
TS

,. .

Icc (mA)
Com'l/Mil

TCLK(ns)
Com'I/Mii
20/25
15/20
20/25
15/20
20/25
15/20
20/25
15/2~

180

180
185
185
'

..

140

140
155
155/175
155
155/175
155

90/12.5

175

70/90
55/70
50/60
50/60
30/40
50/65
35/50
50/65
35/50
50/60
40/50

TS

TS

Size

451.50

TS

16K
4KX4
16K
: 2Kx8

130

45/50
30/40·.·
50/55
35/50 .

TS

oe
TS
oe
TS
be

130

Pins

45/50
45/50
28/40·
45/55
45/55
35/50
70/80
70/80
56/70
70/80
.70/80
55/70

TS
.TS
8K
2Kx4

125

Device
Number
53/63RA481
53/63RA481A
.53/63RS881
53/63R8881A
53/63RA1681
53/63RA1681A
53/63RS1681
53/63R§>1f3!31 A

TS

(

150

DIAGNOSnC·REGISTERED PROMS.
170/175

175

Device
Number
53/630A441
53/630A442

185

53/630A841

190

53/6301641
53/630A1643

'.

Pins

Size

24
(28)
24
(28)
24
(28)

4K
1Kx4
8K
2Kx4
16K
4KX4

TCLK(ns)
Com'I/Mii
18/25
1fl125

ICC (mA)
Com'l/Mii

TS

20/25

185

TS
2S

20/25
20/25

190

Output

) = Chip Carrier Packiige: ' .

l!

TS

180

PROM Part Number Cross-Reference

w
•

...

Memory Description
Organization
Pins
Output
J4K
OC
16
32x8
T8
1K
OC
16
256X4
T8

OC

2K
256x8

20

2K
512 x4

16

T8
T8

OC
T8

OC
4K
512x8

20
24

J::I
t=:
I!
c

~

f
i:3-

=

T8
T8

OC
T8

MMI

AMD

638080
638081!A
638140
638141/A
6308-1
6309-1
638281/A
638240
638241/A
6348-1
6349-1, -2
638481/A
6340-1
6341-1,-2
63RA481
63RA481A
638440
638441/A
63DA441
63DA442
638841
638841A

27818
27819
27820
27821

-

27812
27813
27828
27829
278291
27830
27831

4KReg
24
.27825
T8
512x8
4K
OC
27832
18
1024X4
T8
27833
4K Diag.
T8
27865
24
1024x4
8K
18
278185
T8
2048x4
8K Diag.
24
63DA841
27875
T8
2048x4
6380-1, -2
278180
8K
OC
24
6381-1,-2
1024x8
T8
278181
1024x8
6381-1 J8
278281
24
T8
8KINNYDlp·
6381-2 J8
278281
8KReg
63R8881
24
T8
27835/37
1024x8
63R8881A
16K
6381681
24
278191
T8
2048x8
6381681A
2048x8
6381681 N8
278291
24
T8
8KINNYDIP
6381681AN8
278291A
16K Reg
63RA1681/A
27845/47
24
T8
2048x8
63R81681/A
16K
6381641
20
T8
27841
4096x4
6381641A
16K Diag.
T8
63D1641
27885
24
4096X4
63DA1643
28
32K
6383281
24
T8
27843
4096x8
6383281 A
NOTE: Only. Commercial Specification part numbers are listed.

Fairchild

-

Fujitsu

Harris

Motorola

-

-

7602
7603
7610
7611

7620
7621

7620
7621

-

-

7123
7124
7124

-

-

-

-

-

-

-

-

National
748188
748288
748387
748287

-

-

7649
7649
7640
7641

7640
7641

74L8471
74L8471
748570
748571
748473
748472
748472
748475
748474

-

-

-

-

93453

-

7642
7643

-

-

-

-

-

Raytheon

-

Signetics
82823
828123
828126
828129

-

29611

828135
828135
828130
828131

-

-

29621
29621

. 828147
828147

TI
188A030
188030
248A10
24810
188A22
18822
18822

-

-

828141

28842
28842
288A46
28846

878R474

-

-

-

7642
7643

748572
748573

-

828137

248A41
24841

-

-

-

-

-

-

7128

7685

7685

878185

29651

828185

24881

-

-

-

-

-

-

-

-

93Z450
93Z451

7131
7132
7132E-8K
7132E-8K

-

-

7681

7680
7681

29631
296318
296318

828180
828181
828181N3
828181N3

288A86
28886

-

-

-

-

-

-

-

-

-

-

878180
878181
878281
878281
878R181

-

-

-

-

-

-

93Z511

7138

76161

76161

878191

2.9681

828191

-

7138E-8K
7138Y-8K

6-76161

-

-

296818
29681A8

-

-

-

878291

-

-

-

-

-

-

-

-

-

7152

76165

-

-

-

-

-

-

-

-

-

7142

76321

-

-

-

-

-

6-7681

-

-

-

-

-

288166

-

828191BN3

-

-

-

-

-

-

-

-

-

-

878321

29671

828321

..

'

-

~

o

!I

l

::1-

z

c
3

,
In

~

Ii::I

a

53/635080
53/635081
635081A

HighPerformance

32x8PROM,

TiW PROM Fa~ily
Features/Benefits

Description

• 15.ns maximum access time

The 53/635080, 53/638081 and 638081Afeature low input current PNP inputs, full Schottky clamping and three-state and
open collector outputs: The titanium-tungsten fuses store a
logical low and are programmed to the high..state. SpeCial onchip circuitry and extra fuses provide preprogramming testing
which assures high programming yields and high reliabifity.

• Reliable titanium-tungsten fuses (TIW) guarantees
gie.ter than 98% programming yields
.' Low-voltage generic programming
• Pin-eompatible with standard Schottky PROMs

The 63 series is specified for operation Over the commercial
temperature and voltage range. The 53 series is specified for the
military ranges.

• PNP inputs for low Input current

Applications
• Programmable logic element (PLE'") 5 inputs, 8 outputs,
32 product terms pet output

• Address dec:cKl!H'
• PrIority encoder

Programming
The 53/638080, 53/63S081 and 63S081A are programmed with
the same programming algorithm' as all other Monolithic Memories' generic TiW PROMs. For details contact the factory.

Selection Guide
MEMORY

PACKAGE

PART NUM8ER
OUTPUT

SIZE'

ORGANIZATION

PINS

1/4 K

32xB

16
(20)

PERFORMANCE

TYPE

"

Enhanced

TS
N,J,F,W,
(NL),(L)

638081 A

-

"

53S081

638081

TS
Standard

OC

Pin Configurations

-55°C to +125°C

O°Cto+75°C

, '53S080

638080

Block Diagram

02 01 NCYCC

E

A4
A3

AO 10
A1 11
A2 12

3ha
PROGRAMMABLE
•
ARRAY

1 OF 32

A3 13

A4

14

NC

A1

,07GNO NC ,(laAD

PLE'" Is a trademark 01 Monolithic Memories.

2175MI..lonColJege Blvd. Santa Clara, CA95054-1S92 ,..1:

,,1
2
01 '02

3
03

4
04

5
05

6
06

',7
07

9
08

..0000,IfIIIoDD

(4~)970-9700,::;i :~::===::~",.,"" ",' ,

~·5

53/635080 53/635081 635081A

Absolute Maximum Ratings

Operating
Supply voltage Vee .......•......•.•...••••.......•.......................••... -0.5 V to 7 V
Input voltage ...•.....•.....•..•.........••.......•.....................•...•...• -1.5 V to 7 V
Input current ....... , ..................•...........•......••...........•.•.. -30 mA to +5 rnA
Off-state output voltage ....................................................... -0.5 V to 5.5 V
Storage temperature ...•......••. " •... " ......................•.......•... -65 °e to +150 °e

PrOgramming
..............' ..... 12 V
.................... 7V
................. '.•. 12.V

Operating Conditions
SYMBOL

MILITARY
MIN TYpt MAX

PARAMETER

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

5

COMMERCIAL
MIN TYpt MAX

5.5

4.75

125

0

5

UNIT
V .'

5.25
75

°e

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

TEST CONDITION

VIL

Low-level input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

II = -18mA

IlL

Low-level input current

Vee = MAX

VI = 0.4 V

IIH

High-level input current

Vee: MAX

VI: Vee MAX

VOL

Low-level output voltage

MIN TYPt MAX
0.8
2

Vee: MIN

10L = 16mA

I
I

40

p.A

0.45

MIL 10H : -2 mA

Vee= MAX

leEX

Open collector output current

Vee = MAX

lOS

Output short-circuit current!.

Vee = 5V

Ice

Supply current

Vee = MAX All inputs grounded. All outputs open.

IOlH

V
mA

eOM

Off-state output current *

lOlL

-1.5
-0.25

0.5

Vee'" MIN

2.4

eOM 10H = ,-3.2 mA

V

.
V

Va = 0.4 V

-40

VO=2.4V

40

VO=2.4V

40

VO=5.5V

100
-20

VO= OV

V
V

MIL

High-level output voltage'

VOH

UNIT

90

p.A

p.A

-90

mA

125

mA

Switching Characteristics Over Operating Conditions (See standard test load)
tAA (ns)
ADDRESS ACCESS TIME

OPERATING
CONDITIONS

MAX

TYPt

63S081A

9

15

9

20

9

25

9

20

538080,538081

9

35

9

30

Three-state only.

t

Not more than one output should be shorted at a time and duration of the short-dr-cuit should not exceed one second.
Typicalsat 5,OV Vee and 25°C TA'

3·6

MAX

638080.638081

COMMERCIAL

**

UNIT

DEVICE TYPE
TYPt

MILITARY

tEA AND tER (ns)
ENABLE ACCESS TIME
RECOVERY TIME

IIIIonoIHhIom .emorle.

ns

53/63S080 5.3/63S081 63S081A

Typical ICC vsTemperature
130

Typical TAA vs T.mperature
30

:

:I

I

120

,

25

I
110

r-----t

I

VCC

.

!'

ICC-mA

-r-- --

=5.5V

~

100

I

I
20
I

I
I

I--

TAli - ns

vcc=5:25'

",

90

.
80

10

-so

-25

o

25

50

75

±10%

~'"

I

I
I

Vec

1

---

;/

V

± 5%

I

,

1

-55 1
70
-75

I

rRcc

15.

100

125

o

, -55:

-75

TA -AMBIENT TEMPERATURE-'C

Switching Test Load

-50

-25

25

50

100

75

125

TA -AMBIE,NT TEMPERATURE-'C

Definition of Timing Diagram

;:1

:ri

RI

30011

OUTPUT

·'.}'&ll

CL*

Definition of Wav.fo......
-; ,
~

WAVEFORM

INPUTS

YIf9J11fIlO.

DON'T CARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

1t7 ~

NOT
APPLICABLE

CENTER UNE IS
HIGH IMPEDANCE STATE

IIJUST BE STEADY

WILL BE STEADY

OUTPUTS

'

NOTE8: 1. Input pulse amplitude 0 V to 3.0

V.'

2. Input rise and fall times 2-5 ns from 0:8 V to 2.0 V.
3. Input access measured at the 1.5 V level.

4. tAA and tEA are tested with switch 81 closed, CL = 30 pF and measured at 1.5 V output level.
5. Fer open collector devices. tEA and tER are measured at the 1.5 V output level with 8 1 closed and C L

=30 pF.

6. For three-state devices, tEA is measured at the 1.5 V output level with C L = 30 pF. 8 1 Is opsn for high Impedance to "I" test and
closed for high Impedance to "(]' test.
.
IER Is tested with C L = 5 pF. 8 1 ls,open for "I" to high iinpedance test, measured at V OH -0.5 V output level; 8, Is closed for
high impedance test measured at VOL +0.5 V output level.

"0" to .

3-7

53/635080 53/635081 635081 A

Commercial Programmers
Monolithic Memories PROMs are designed and tested to givea
programming yield greater than 98%. If your' programming
yield is lower, check your programmer. It may not be properlycalibrated.

ideally under the actual conditions of use. Eac~ timea new bOard
or a new programming module is inserted, the whole system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember - The best PROMs available can be' made
unreliable by Improper programming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

I

Metal Mask Layout

3-8

Data 1/0 Corp. _
10525 Willows Rd. N.E.
Redmond, WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
Sunnyvale, CA 94089

Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94089

HighPerformance
256x4 PROM
TiW PROM Family

53/635140
53/635141
53/635141A

Features/ Benefits

Description

• 30 ns maximum access time

The 53/638140 and 53/638141/A are 256x4 bipolar PROMs
featuring low input current PNP inputs. full 8chottky clamping.
and open collector or three-state outputs. The titanium-tungsten
fuses store a logical low and are programmed to the high state.
8pecial on-chip circuitry and extra fuses provide preprogramming testing which assureS high programming yields and high
reliability.

• Reliable titanium-tungsten fuses (TiW) guarantees
greater than 98% programming yields
• Low voltage generic programming
• Pin-compatible with standard Schottky PROMs
• PNP inputs for low input current

The 63 series is specified for operqtion over the commerciql
tempemture qnd voltqge range. The 53 series is specified 'for
the military ranges.

• Open collector or three-state outputs

Applications
• Microprogram control store
• Microprocessor program store
• Look-up table
• Character generator

Programming

• Code converter

The 53/638140 and 53/638141/A PROMs are programmed with
the same programming algorithm as all other Monolithic Memories'generic TiW PROMs. For details contact the factory.

• Programmable Logic Element (PLE'M) with 8 inputs,
4 outputs, and 256 product terms per output

Selection Guide
MEMORY

PACKAG.E

PART NUMBER
OUTPUT

SIZE

ORGANIZATION

PINS

TYPE

1K

256x4

16
(20)

N.J.
(NL).(L).

Enhanced

DOC to +75°C

-55° C to +125° C

638141A

538141A

638141

538141

638140

538140

T8

I

W.F

PERFORMANCE

8tandard
OC

Pin Configurations

Block Diagram

AS

AS

NC

vee

A7 15
A6 1
AS 2
A4 3
A3 4

A7

1 OF 32
ROW
DECODER

32X32
PROGRAMMABLE
ARRAY

Eli

A2 7
Al 6
AU 5
9

10

11

NC GND NC

12

13

04

03

1 OF 8
COLUMN
DECODER

02

PlE™ is a trademark

of MonolithiC Memories

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

lIIonollthlcr:mn
lIIemories InJn.LI

3·9

53/635140 53/63S141/A
Absolute Maximum. Ratings

Operating
Programming
Supply voltage vee ••••.•.••••..•.••••.•••..•...........•••...........•. ',' ~ ..•••• ~0.5 Vto 7 V.••••• ''',;'' ~ ...... :; .... ,12 V"':
Input voltage ................................................................... -1.5. V to 7 V ......... ; ............... 7 V
Input current .•••...••.•••..•...••.•.••..••..............•.....•....•.•...•. -30 mA to +5 mA
Off-state output voltage ••...••...•..•••.•••.•••..•••.•••.•••••••.••••.•.•.••••• -0.5 V to 5.5 V ••.•••..••••••••.••••• 12 V
Storage temperature ....••..., ............................. ; •••••.••••.••••.•••• _65° to +150o e

Operating' Conditions
MILITARY
MIN NOM MAX

PARAMETER

SYMBOL
Vee

Supply voltage

4.5

TA

Op~rating free"air temperature

-55

COMMERCIAL
MIN NOM MAX

5:5

4.75

125

0

5

5

UNIT

5.25

V

75

°e

Electrical Characteristic's Over Operating Condilions
PARAMETER

SYMBOL
Vil

low-level input voltage

TEST CONDITION

MIN TYPt MAX

VIH

High-level input voltage
Input clamp voltage

Vee= MIN

II = -18 mA

III

low-level input current

Vee = MAX

VI = 0.4 V

IIH

High-level input current

Vee = MAX

VI = Vee MAX

Val

low-level output voltage

Vee = MIN

10l = 16'mA

VOH

High-level output voltage*

Vee = MIN

Off-state output current*

Vee" MAX

leEX

Open collector output current

Vee = MAX

lOS

Output short-circuit currant!*

Vee = 5V

lee

Supply current

Vee = MAX. All inputs grounded. All outputs open.

V

2

I
I

eOM

-1.5

V

-0.25

mA

40

p.A

0.45

Mil

V

0.5

I'

eOM 10H: -3.2 mA

10ZH

V

0.8

Vie

IOZl

UNIT

V

2.4

Mil 10H = -2mA
Va: 0.4 V

-40

. Va: 2.4V

40

VO=2.4V

40

Va = 5.5V

100
;-20

Vo= OV

80

p.A

p.A

-90

mA

130

mA

Switching Characteristics Over Operating Conditions (See standard test load)
..
OPERATING
CONDITIONS

COMMERCIAL

MILITARY

*
**

t
,

D~VICETYPE

tAA (ns)
ADDRESS AcCESS TIME
TYPt

MAX

tEA AND tER (ns)
ENABLE ACCESS TIME
RECOVERY TIME
TYPt

MAX

63S141A

20

30

10

20

63S14O,63S141

20

45

10

25

53S141A

20

40

10

25

53S14O,53S141

20

55

10

30

Three-state only.
Not more than one output should .be shorted at a time and duration of the short-circuit should not exceed one second.
Typlcats at 5.0
.

3,;,10 .'

'.

v vee and 25'e TA.
.".

. "."; ~

!

UNIT

ns

53/635140 53/63S141/A

Typical ICC vs Temperature

Typical T AA vs Temperature

I
110

I

I

!

50

I

I

I

1

I

I
I

Ir- VCC=5.5V

I
--.:;.: t--

I
I
80

70

I

.'

I
I

r-.::~

\

I
I

"--VCC=5.25V

20

t~

10

!

60
-75

-00

75
100
50
o
25
-25
TA - AMBIENT TEMPERATURE - ·c

):1

:r{

-75

i

-so

-25

o

25

so

75

TA - AMBIENT TEMPERATURE -

WAVEFORM

R1

3OO11

".

".

R2
CL:;;f

~ VCC±5~·

100.

125

·c

Definition of Timing Diagram

Switching Test Load

OUTPUT.'

o
125

"-

I

I
I

l--

I

~

I

lr-VCC±10'10

/

xxxx
l2)

INPUTS
DONTCARE;
CHANGE PERMITTED

noUthic Memories.

:
:.
'. ." ."
TWX: 9.10-338-2;116
2175 Mission College alvd. Santa Clara, CA 95054-1592 Tel: (408)970-9700 TWX: 910-338-2374

8
9
11 12 13 14
03 04 05 06 07 08

I6Inollthlo l!1!n

.emor/es

vurw

3 .. 25

53/635480 53/63S4,1/A
Absolute Maximum Ratings

' Operating

~nU:~I~~~::~.~?~::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: =~:;~ :6~~

PrognilmmlnQ

::: ::::::::~::.

,:::;~f~

Input current ..•..•......................................................... -30 mA to +5 mA
Off-state output voltage ...................................................•.... -0.5 V to 5.5 V ........ , ........•..... 12 V
Storage temperature' ........................................................... _65° to +1SOOe
"

Operating Conditions
SYMBOL

MILITARY
MIN NOM MAX

PARAMETER

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

.,.COMMERCIAL
MIN NOM MAX

5:5

4.75

125

0

5

UNIT

5; 5.25
75

V
·e

DC Electrical Characteristics Over Operating Conditions
SYMBOL

TEST CONDITION

PARAMETER

MIN TVPt 'MAX

VIL

Low-level input voltage

Guaranteed input logical low voltage for all inputstt

VIH

High-level input voltage

Guaranteed input logical high voltage for all inputstt 2

Vie

Input clamp voltage

Vee = MIN

II = -18 mA

IlL

Low-level input current

Vee = MAX

VI = 0.4 V

IIH

High-level input current

Vee = MAX

VI = Vee MAX

VOL

Low-level output voltage

VOH

High-level output voltage

10ZL

Vee = MIN

.

Off-state output current·

I
I

IOL=16mA

lOS

Output short-circuit current:.

ICC

Supply current

V

-1.5

.y .

-:-0.25

mA

40

flA

V

eom

0.45
V.

.' 0:5

Mil

Vee = MAX

I'

Mil IOH = -2mA

2.4

V

Vo = 0.4 V

-40

Vo = 2.4 V

40

VO=2.4V
Open collector output current

0.8

eom IOH = -3.2 mA
Vee = MIN

10ZH
leEX

UNIT

Vee = MAX
., Vee = 5V
Vee

flA

40
..

Vo = 5.5 V
-20

Vo = OV

=MAX. All inputs grounded. All outputs open.

104

100

flA

-90

mA

155

rnA

Switchi ng Characteristics Over Operating Conditions (See standard test load)
OPERATING
CONDITIONS

DEVICE TYPE

*

Three-state only.

**

.,

lEA AND IER (ns)
ENABLE ACCESS TIME
RECOVERY TIME

TYPt

MAX

TYPt

63S481A

22

30

18

25

22

45

18

25

53S481A

22

40

18

30.

53S480, 538481

22

50

18

35

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

t Typicals at 5.0 V Vee and 25° eTA'
tt VIl:' and VIH li'tnits ar,e absolute v.aloeswitl1 respect to the device ground pin(s) and includes all overshoots due to test equipment noise.
3-26

MonoIIthlcW Memories

UNIT

MAX

638480, 638481

COMMERCIAL

MILITARY

IAA (ns)
ADDRESS ACCESS TIME

ns

,

53/635480 53/63S481/A

Typical ICC vs Temperature

Typical T AA vs Temperature

130

60

:

:
I

I
120

-

.II
110

I
I

ICC-rnA
100

I

90

:

I

50
IVcC

I

5.5V

I

I

r'--

40

r--.., .............

I"r r-..~.......

Vcc - 5.2h.../

I
I
80

I
I

TAft.. -ns

.........

I

30

""

20

10

f

:

I
VCC

5%

:

-.I

-

10~/o

I

I
I

-55 ;
70
-75

"'r-.I

I

[VCC .

I

o
-50

-25
0
25
50
75
T A -AMBIENT TEMPERATURE-"C

100

125

-75

I
-50

-25

25

50

75

100

125

TA -AMBIENT TEMPERATURE_oC

Definition of Timing Diagram

Switching Test Load
VCC

)S1

:r-1

300n

OUTPUT

-=

INPUTS

YXXX

OON'TCARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

B~

R1

CL~

WAVEFORM

R2
600n

OUTPUTS

Definition of Waveforms

NOTES: 1. Input pulse amplitude 0 V to 3.0 V.
2. Input rise and fall times 2-5 ns from"O.B V to 2.0 V.
3. Input access measured at the'1.5-V level.

4. tAA is tested with switch 81- closed, CL = 30 pF'and meas'ured at 1.5 V output level.
S. For open collector devices, TEA and TEA are measured at the 1.5 V output level with 81 closed and CL = 30 pF.
6. For three-state devices, TEA is measured at the 1.5 V output level with CL = 30 pF. 81 is open for high-impedance to "1" test
and closed for high-impedance to "0" test.
TER is tested with CL = 5 pF. 81 is open for "'" to high-impedance test, measured at VOH -0.5 V output level; S1 is closed for '0" to
high-impedance test measured at VOL +0.5 V output level.

Monolithio

W Memories

3·27

53/631480 53/63S481/A

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give
a programming yield greater than 98%. If your programming
yield is lower. check your programmer. It may not be properly
calibrated.

routine. ideally under the actual conditions of use. Each
time a new board or a new programming module is inserted.
the whole system should be checked. Both timing and
voltages must meet published specifications for the device.

Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular

Remember - The best PROMs available can be made
unreliable by improper programming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

Data I/O Corp.
10525 Willows Rd. N.E.
Redmond. WA 98073
Kontron Electronics. Inc.
630 Price Ave.
Redwood City. CA 94063

Digelec Inc.
586 Weddell Dr.
Suite 1
SUnnyvale. CA 94089

lIetal lI.k Layout

3·28

MonolithIc

w.•.

morle.

High Performance
2048x4PROM
Ti'W PROM Family

53/635841
53/635841A

Features/Benefits

Description

• 35-n8 maximum access time

The 53/63S841 and 53/63S841A are.2048x4 bipolar PROMs
featuring low input current PNP inputs, full Schottky clamping,
and three-state outputs, The titanium-tungsten fuses store a
logical low and are programmed to the high state, Special onchip circuitry and extra fuses provide preprogramming testing
which assures high programming yields and high reliability.

• Reliable titanium-tungsten fuses (TiW) guarantees greater
than 98%prograrnming yields
• Low voltage generiC progammlng
• Pin-compatible with standard Schottky PROMs

The 63 series is specified for operation over the commercial
temperature and voltage range. The 53 series is specified for the
military ranges.

• PNP Inputs for low input current

Applications
• Microprogram control store

Programming

• Microprocessor program store

The 53/638841 and 53f63Sa41 A PROMs are programmed with
the same programming algorithm as all other Monolithic Memories
'
'.
generic TiW PROMs,

• Look-up table
• Character generator
• Code converter
• Programmable Logic Element (PLE'") with eleven Inputs,
four outputs and 2048 product terms per output

Selection Guide
MEMORY

PACKAGE

SIZE

ORGANIZATION

PINS

TYPE

8K

2048x4

18
(20)

NL),(L)

OUTPUT

PERFORMANCE

N,J,
W,F

.

TS

-55°C to +125°C

Enhanced

638841 A

53S841A

Standard

638841

53S841

.

Block Diagram

Pin Configurations

vee
AS

PART NUMIiIER
O°Cto +75°C

A9 15
A8 16
A717
A6 1
AS 2

AS AI NCYCCA7

A7

1 OF 64
ROW
DECODER

64xl28
PROGRAMMABLE
ARRAY

A4
AI

AI

.u

AS

AS

01
01

Al

NC

A3 4

02
A2

GND

02

03

Al0

A27

Al 6
04 03

E

Al0 8
3 OF 32
COLUMN
DECODER

AO 5

E

10

. .,
,.
.....
TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970"97'00 TWX: 910-338-2374

. . . .,ltbIQm.
_.morl.s
3-29

53/635841

53/63S841A

Absolute Maximum Ratings

Operating
Programming
Supply voltage vee ............................................................. -0.5 Vto 7 V ...................•... 12 V
Input voltage ................................................................... -1.5 V to 7 V ....................... 7 V
Input cu rrent ............................................................... -30 mA to + 5 mA
Off-state output voltage .............. , ......................................... -0.5 V to 5.5 V ...................... 12 V
Storage temperature .......................................................... -65 0 to +1500 e

Operating Conditions
SYMBOL

I

PARAMETER

Vee

Supply voltage

TA

Operating free-air temperature

-t

MILITARY
MIN NOM MAX

5

4.5

5.5
125

i- 55

1

COMMERCIAL
MIN NOM MAX

I 4.75

5

I0

5.25

I

UNIT

I

V

751 °e

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL

Low-level input voltage

VIH

High-level input voltage

TEST CONDITION

UNIT
V

0.8
2

Vie

Input clamp voltage

Vee = MIN

II = -18 mA

IlL

Low-level input current

Vee = MAX

VI = 0.4 V

IIH

High-level input current

Vee = MAX

VI = Vee MAX

VOL

Low-Iaveloutput voltage

Vee= MIN

VOH

High-level output voltage

Vee = MIN

Off-stale output current

Vee=MAX

10ZL

MIN TYPt MAX

10L = 16mA

I
I

eOM

MIL 10H = -2 mA

-1.5

V

-0.25

mA

40

p.A

0.45

MIL

eOM 10H = -3.2 mA

10ZH

V

2.4

V

Va = 0.4 V

-40

Va = 2.4 V

40

lOS

Output short-circuit current*

Vee = 5V

ICC

Supply current

Vee = MAX. All inputs grounded. All outputs open.

-20

Vo= OV

V

0.5

p.A

-90

mA

150

mA

Switching Characteristics Over Operating Conditions (See standard test load)
OPERATING
CONDITIONS

DEVICE TYPE

lAA (ns)
ADDRESS ACCESS TIME
TYPt

COMMERCIAL

MILITARY

*

t

MAX

tEA AND tER (ns)
ENABLE ACCESS TIME
RECOVERY TIME
TYPt

35

63S841

50

25

53S841A

50

30

53S841

55

30

Typicals a15.0 V Vee and ~5°e TA'

3-30

25

63S841A

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

Monolithic

I!IFJ) lIIIemories

UNIT

MAX

ns

53/635841

53/63S841A

Typical ICC vs Temperature

Typical T AA vs Temperature

:I

:L

I
I
I

I
I
I

I
ICC -mA

I

--

]

120

.

I
I
I
I
I
I
I

110

100

TAA - ns

~.5V

VccJ5.~

~~

:
-75

.

-50

-25

tA

25

75

10!l

40.

30

20

'"

10

125

-75

:
I
I
I

.
o

25

50

75

100

125

Definition of Timing Diagram

;:1

:r1

300n

WAVEFORM

INPUTS

XXXX

DONTCARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

NOT
APPLICABLE

CENTER UNE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

1» ~

.

R1

R2

CL*

-25

TA - AMBIENT TEMPERATURE -'C

Switching Test Load

..

~

:
-so

- AMBIENT TEMPERATURE - ·C

OUTPUT·

vcc±~

I
I
I

OUTPUTS

":" 60011
t.

Definition of Waveforms

NOTES: 1. Input pulse amplitude 0 V to 3.0 V.
2. Input rise and fall times 2-5 os from 0.8 V. to 2.0 V.
3. Input access measured at the 1.5 V level.

4. tAA is tested with switch· Sl closed, CL : 30 pF and mea~ured at 1.5 V output level.
5. TEA is measured at the 1.0 V output level with CL : 30 pF. S, is open for high-impedance to "1" test and closed for
high-impedance to "0" test.
.
TER is tested with CL : 5 pF. Sl is open lor ':1" to high~impedance test, measured at VOH _0.5 V output level: SI is
closed for·'''O'' to high-impedance test measured at VOL + 0.5 V output le~el.

3·31

53/635841

53/635841 A

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give a
programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each time a new board
ora new programming module is inserted, the whole system
should be checked. Both timing and voltages must meet
published specifications for the deVice.

Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember - The best PROMs available can be' made
unreliable by Improper prOgramming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

Data 110 Corp.
10525 Willows Rd. N.E.
Redmond, WA 98073
Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Digelec Inc.
586 Weddell Dr.
Suite 1
Sunnyvale, CA 94089
Stag Microsystems Inc.

528-5 Weddell Dr.
Sunnyvale, CA 94089

Metal Mask Layout

Monolithic

W Memories

High Performance
4096x4PROM
TiW PROM Family

53/6351641
53/6351641A

Features/Benefits

Description

• 35 ns maximum access time

The 53/6381641 features low input current PNP inputs. full
8chottky clamping and three-state outputs. The titaniumtungsten fuses store a logical low and are programmed to the
high state. 8pecial on-chip circuitry and extra fuses provide
pre-programming testing which assures high programming yields
and high reliability.

• Reliable titanium-tungsten fuses (TiW)
• Low-voltage generic programming
• Pin-compatible with standard Schottky PROMs
• PNP Inputs for low Input current

The 63 series is specified for operation over the commercial
temperature and voltage range. The 53 series is specified for the
military ranges.

Applications
• Microprogram control stores
• Microprocessor program store
• Look-up table
• Character generator

Programming

• Code converter

The 53/6381641 PROM is programmed with the same programming algorithm as all other Monolithic Memories' generic
TiW PROMs. For details contact the factory.

• Programmable Logic Element (PLE'") 12 Inputs,
4 outputs, 4096 product terms per output

Selection Guide
MEMORY
SIZE
16K

ORGANIZATION
4Kx4

PART NUMBER
PACKAGE

PERFORMANCE
O°C to +75°C

-55°C to +125°C

N.J.
NL

8tandard

6381641

5381641

Enhanced

6381641A

5381641A

OUTPUT
T8

Block Diagram

Pin Configuration

All 17
Al0 18

A9 19
A8 1
A72
4321282726

A6

o

AS

!

A4....;5'...r----,

4096x4

A3 6

A27
12 13 14 15 16

128 X 128
PROGRAMMABLE
ARRAY

1 OF 128
ROW
DECODER

17' 18

Al 8

1 OF 32
COLUMN
DECODER

9

AO---.'-_ _--'

01

PLETlI is a trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara. CA95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

04

Monolithicm·
Memories
3·33

E'

53/6351641

53/6351641 A

Absolute ·Maximum Ratings

Operating
Supply voltage. vee ...................................................•.......... -0.5V to 7V
Input voltage .................................. " ...•.........•.................. -1.5V to 7V
Input current ................................................................ -30mA to +5mA
Off-state output voltage ......................................................... -0.5V to 5.5V
Storage temperature .................. , ..... " .............................. -65°e to +150oe

Programming
•........... : ........ 12V
...................... 7V
..................... 12V

Operating Conditions
PARAMETER

SYMBOL

MILITARY
MIN NOM MAX

COMMERCIAL
MIN NOM MAX

5.5

4.75

125

0

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

5

5

UNIT

5.25

V

75

°e

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

TEST CONDITION

VIL

Low-level input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

II = -18 mA

IlL

Low-level input current

Vee = MAX

VI = 0.4 V

IIH

High-level input current

Vee = MAX

VI = Vee MAX

UNIT

0.8

V

2

VOL

Low-level output voltage

Vee = MIN

VOH

High-level output voltage

Vee = MIN

Off-state output current

Vee = MAX

10ZL

MIN TYPt MAX

IOL = 16mA

I
I

-1.5

V

-0.25

mA

40

p.A

MIL

0.5

eOM

0.45

MIL IOH = -2 mA

10ZH

V

V

2.4

eOM IOH = -3.2 mA

V

Vo = 0.4 V

-40

VO=2.4V

40

lOS

Output short-circuit current *

Vee = 5V

lee

Supply current

Vee = MAX. All inputs grounded. All outputs open.

-20

Vo = OV

130

p.A

-90

mA

175

mA

Switching Characteristics Over Operating Conditions (See standard test load)
OPERATING
CONDITIONS

DEVICE TIME

COMMERCIAL

MILITARY

tAA (ns)
ADDRESS ACCESS TIME

tEA AND tER (ns)
ENABLE ACCESS TIME
RECOVERY TIME

TYPt

MAX

TYPt

MAX

63S1641A

28

35

12

25

63S1641

28

50

12

25

53S1641A

28

50

12

30

53S1641

28

65

12

30

*

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed, one second.

t

Typicals at 5.0 V Vee and 25°e T A-

3·34

MonolIthic WMemorles

UNIT

ns

53/6351641

Typical TAA vs Temperature

Typical ICC vs Temperature
180

53/63S1641A

:

:
:

170

I

60

I
I
I

160

VCC = 5.5 V

-.......

r-

t

-.....

I

ICC - rnA 150

50

I

"

I

~'"
VCC=5.25~

I
I

I

140

I
I
I

I
I
I
I

130

TAA -ns

"

:
-75

-50

50

25

-25

TA - AMBIENT TEMPERATURE -

I
I
30

'"

125

75

°c

40

I

vcc~

tI

20

~

Vee ±5C1fo

I
I

10
-75

:
-50

-25

o

25

50

75

TA - AMBIENT TEMPERATURE -

100

125

°c

Definition of Timing Diagram

Switching Test Load
VCC

)Sl

:r--1

30Dn

OUTPUT

Rl

R2

CL~

OUTPUTS

WAVEFORM

INPUTS

~

DONTCARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

111 ~

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

-=- 600n

Definition of Waveforms

NOTES: 1. Input pulse amplitude 0 V to 3.0 V.
2. Input rise and fall times

2~5

ns from O.S V to 2.0 V.

3. Input access measured at the 1.5 V level.
4. tAA is tested with switch Sl closed. C L = 30 pF and measured at 1.5 V output level.
5. tEA is measured at the 1.5 V output level with CL = 30 pF. Sl is open for high impedance to "1" test and closed for high impedance
to "0" test.
tER is tested with CL = 5 pF. Sl is open for "1" to high impedance test, measured at VOH - 0.5 output level; 51 is closed for "0" to high
impedance test measured at VOL + 0.5 V output level.

lIIIonoIithlc

W lIIIemories

3·35

53/8381641

53/8381841 A

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give a
programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly.
calibrated.

ideally under the actual conditions of use. Each time a new board
or a new programming rnodule is inserted, the whoie system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember - The best PROMs available can be made
unreliable by Improper programming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

Metal Mask Layout

3-38

Data 1/0 Corp.
10525 Willows Rd. N.E.
Redmond, WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
Sunnyvale, CA 94089

Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94089

High Performance
2048x8PROM
TiW PROM Family

53/6351681
53/6351681A

Features/Benefits

Description

• 35 ns maximum access time

The 53/63S1681 is a high-speed 2Kx8 PROM which uses
industry standard package and pinout. In addition, the device is
available in the 24-pin (().3 in.) SKINNYDIPI!!>.

• 16384-blt memory
• Reliable titanium-tungsten fuses (TIW)
• Pin-compatlble with standard Schottky PROMs

The family features low current PNP inputs, full Schottky
clamping and three-state outputs. TheTitaniurn-Tungsten fuses
store a logicall()w and are programmed to the high state.
Special on-chip circuitry and extra fu~ provide preprogramming tests· which assure high programming yields and high
reliability.·
. .
.

• Available In space saving SKINNYDIP@ package

Applications
• Microprogram control stores

The 63 series is speCified for operation oVer the commereial
temperature and voltage range. The 53 series is specified for
the military ranges.
.

• Microprocessor program store
• Look-up table
• Charaetar generator

Programming

• Code converter

The 53/63~1681 PROM is programmed with the same pro-:
gramming algorithm as all9ther Monolithic Memories' generiC
TiW PROMs. For details contact the factory.

• ·Programmable Logic Element (PLE"') 11 Inputs,
8 outputs, 2048 product terms per output

Selection Guide
MEMORY
. SIZE
16K

PACKAGE

PART NUMBER
PERFORMANCE

ORGANIZATION
2048x8

OUTPUT
..
TS

PINS

TYPE

24
(28),

N;NS,
J,JS,W,
(NL),(L)

Pin Configurations

O°Cto+75°C
Standard

63$1681

Enhanced

63S1681A

..

"55°C to +125°C
53S1681
53S1681A

Block. Diagram

}oS AI; A7 NCYCCAS iIs

AS
A7
Al0

E:i

~

AS

E2
E3
NC

08
07

A3
A2
A1
AD

12 13 14 15 1617 8
0203GNDNCQ4 05 06

Ei
E2
E3

SKINNYDlf"I is a registered trademark 01 Monolithic Memories.

P·LE'" is a trademark 01 Monolithic Me.mor!!>•• ,
. ;;
.>. TWX:. ~10-338"2371>
2175 Mission College Blvd. Santa Ciani, CA 95054-1592 Tei: (408) 970-9700 TWX: 910-338-2374'

_onolltMO
.

B'--"'----..
• • •. , . - . - . -

m.
3·37

53/6351681

53/63S1681A

Absolute Maximum R a t i n g s , o p e r a U n g
Programming
Supply voltage vec ..... , ...................................................... -0.5 Vto 7 V .................... 12V
Input voltage .•..•. ~ ........ ; ........... '..................................... , ••. :-1.5 Vto tv ...................... 7V'
Input current. .............................................................. ~30mA to +5 mA
Off-state output voltage ....................................................... -0.5 V to 5.5 V .....•.•.•...•...... 12V
Storage temperature .......... ; ... ; .. o' •••••••••' •• '•••••••••••••••••••••••••• -'65°e to +150 0 e
Operating Conditions
SYMBOL
Vee
TA

MILITARY
MIN TYpt MAX

PARAMETER
Supply voltage

4.5

Operating free air temperature

-55

5

COMMERCIAL
MIN TYpt MAX

5.5
125

4.75

5

0

UNIT

'5.25

V

75

°e

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

MIN TYPt MAX

TEST CONDITION

VIL

Low-level input voltage

VIH

High-level input voltage

VIC

Input clamp voltage

Vee = MIN

II = -18mA

IlL

Low-level input current

Vae=MAX

VI = 0.4 V

IIH

High-level input current

Vee = MAX

VI = Vee MAX

V

-1.5

V

-0.25

mA

40

p.A

V

I
I

MIL

0.5

COM

0.45

Low-level output voltage

Vee = MIN

VOH

High-level output voltage

Vee = MIN

Off-state output current

Vee = MAX

lOS

Output short"Ci!'cuit current*

Vee = 5V

ICC

Supply current

Vee = MAX',AII inputs TTL, all outputs open.

IOZL

0.8
2

VOL

10L = 16mA
MIL 10H = ~2 mA

10ZH

VA = 0.4 V

-40

Vo= 2.4 V

40
-20

Vo= OV

V

V

2.4

COM 10H = -3.2 mA

UNIT

130

p.A

-90

mA

175

mA

Switching Characteristics Over OperaUng Conditions (See standard test load)
OPERATING
CONDITIONS

COMMERCIAL
"

*

t

MILITARY

DEVICE TYPE

tAA (ns)
ADDRESS ACCESS TIME

tEA AND tER (ns)
ENABLE ACCESS TIME
RECOVERY TIME

TYPt

MAX

TYpt

MAX

63S1681A

27

35

18

25

63S1681

27

50

18

30

53S1681A

27

45

18

35,

53S1681

27

60

18'

35

Not more,than one qutput should be shorted at a time and duration of the short-circuit should not excead one second,
Typical. at S,O v VCC and 2SoC TA'

3-38

UNIT

ns'

53/6351681
Typical ICC vs Temperature
~

53/63S1681A
Typical T AA vs Temperature
70

:
I

:I

I

I

I

I

I

I

I

~
Icc-mA 140

r-- r--- i'-b
I'-..

I
I
I
I

120

I

l!VCC=5.5V

"

VCC=5.25V.../

:

100

T AA -ns 40

I

i~

30

I"-

[vr±lO'i'

V

VICC±5,J,J

:

~

,../

:.--

I
I
I

I
I

-55~

-75

:

-SSt
-25
25
50
75
100
TA-AMBIENT TEMPERATURE-'C

10

Switching Test Load

:ri

Rl
30011

.

-50

-25
0
25
50
75
TA-AMBIENT TEMPERATURE-'C

100

125

Definition of Timing Diagram

;:1

OUTPUT

-75

125

...:

WAVEFORM

INPUTS

rm;a

DONTCARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

B

~

OUTPUTS

112

CL:;:f

":' 60011

Definition of Waveforms

NOTES: 1. Input pulse amplitude 0 V to 3.0 V.
2. Input rise and fall times 2-5 ns from 0.8 V to 2.0 V.

3. Input access measured at the 1.5 V level.

AA

4.
is tested with switch Sl closed. C L =30pF and measured at 1.~ V output level.
5. tEA is measured at the 1.5 V output level with CL = 30 pF. 51 is open for high impedance to "1" test. and closed for high impedance to "0" test.
tER is tested with CL = 5 pF. Sl is open for "1" to high impedance test, (tleasured at VOH - 0.5 output level: Slis closed for "0" to
high impedance test measured at VOL + 0.5 V output level.

Monolithic

W Memories

3-39

53/6351681

53/6351681A

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give a
programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each time a new board
or a new programming module is inserted, thewhole system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember - The best PROMs available can be made
unreliable by improper programming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

Data I/O Corp.
10525 Willows Rd. N.E.
Redmond, WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
Sunnyvale, CA 94089

Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94089

Metal Mask Layout

A3

A2

A1

AO

3·40

IIIIonoIlthlc

m

Memories

High Performance
4096x8PROM
TiW PROM Family

53/6353281

53/6353281 A

Features/Benefits

Description

• 40 ns maximum access time

The 53/6353281 is a high-speed 4Kx8 PROM which uses
industry standard pin out.

• 32768-bit memory

The family features low-current PNP inputs. full Schottky
clamping and three-state outputs. The Titanium-Tungsten
fuses store a logical low and are programmed to the high state.
Special on-chip circuitry and extra fuses provide preprogramming testing which assure high programming yields and high
reliability.
The 63 series is specified for operation over the commercial
temperature and voltage range. The 53 series is specified for
the military ranges.

• Reliable titanium-tungsten fuses (TIW)
• Pln-compatlble with standard Schottky PROMs
• PNP inputs for low input current

Applications
• Microprogram control stores
• Microprocessor program store
• Look-up table
• Character generator

Programming

• Code converter

The 53/6383281 PROM is programmed with the same programming algorithm as all other Monolithic Memories' generic
TiW PROMs. For details contact the factory.

• Programmable Logic Element (PLE'") 12 Inputs,
4096 product terms, 8 outputs

Selection Guide
MEMORY

PART NUMBER

PACKAGE
PERFORMANCE

SIZE
32K

ORGANIZATION

OUTPUT

4096x8

TS

PINS

TYPE

24
(28)

N.J.
(NL).(L).
W

Pin Configurations

-55°C to +125°C

Standard

6353281

5383281

Enhanced

63S3281A

53S3281A

Block Diagram

AS A6 A7 NCVCC A6 A9

4096x8

O°C to +75°C

All
Al0
A9
A8
A7
A6
Al0 AS

A3

E1

A2

All

AI

E2

AO

NC

NC

08

01

07

19
21
22
23
1
2
3

128.256
PROGRAMMABLE
ARRAY

4
A4
5
A3
A2 6
AI

AO

02 03GNDNC 04 05 06

01

PLE'" is a trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

02

03 04 05 06 07

08

.onOlllhlem

••mor'es

3-41

53/6353281 53/63S3281A
Absolute Maximum Ratings

Operating
Supply voltage vee .......•.•.........•.....•.....•.....••...................... -0.5 V to 7V
Input voltage ........................ ; .......................................... -1.5 V to 7 V
Input current ........................................•....•........•........ -30 mA to +5 mA
Off-state output voltage .......•.........•....•................................. -0.5 V to 5.5 V
Storage temperature ......................................................... -65°e to +150oe

Programming
..........•.......... 12 V
................. ; .... 7V

..................... 12 V

Operating Conditions
MILITARY
MIN NOM MAX

PARAMETER

SYMBOL

Vce

Supply voltage

4.5

TA

Operating free-air temperature

-55

5

COMMERCIAL
MIN NOM MAX

5.5

4.75

125

0

5

UNIT

5.25

V

75

°e

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

UNIT

V

0.8

Vil

low-level input voltage

VIH

High-level input voltage

VIC

Input.clamp voltage

Vee = MIN

II = -18 mA

III

low-level input current

Vee = MAX

VI = 0.4 V

IIH

High-level input current

Vee = MAX

VI = Vee MAX

V

2

Val

low-level output voltage

Vee = MIN

VOH

High-level output voltage

Vee = MIN

10Zl

MIN TYpt MAX

TEST CONDITION

10l = 16mA

I
I

V

-0.25

mA

40

p.A

0.5

Mil

V

0.45

eOM

Mil 10H = -2 mA

-1.5

V

2.4

eOM 10H = -3.2 mA
Va = 0.4 V

-40

VO= 2.4V

40

Off-state output current

Vee = MAX

lOS

Output short-circuit current*

Vee= 5V

Ice

Supply current

Vee = MAX.AII inputs grounded. All outputs open.

10ZH

-20

VO= OV

150

p.A

-90

mA

190

mA

Switching Characteristics Over Operating Conditions (See standard test load)
OPERATING
CONDITIONS

DEVICE TYPE

lAA (ns)
ADDRESS ACCESS TIME
TYPt

*

t

MAX

TYPt

31

40

18

20

63S3281

31

50

18

30

53S3281A

31

50

18

35

5383281

31

60

18

35

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
Typic?1 at 5.0 V VCC and 25".C T A-

3-42

IIIIonoIlthlo

m

lIIIemories

UNIT

MAX

6383281 A
COMMERCIAL

MILITARY

tEA AND tER (ns)
ENABLE ACCESS TIME
RECOVERY TIME

ns

53/63S328153/63S3281A

Typical ICC vs Temperature

Typical T AA vs Temperature

,
2CIO

7o·

:
:

180

-

L1

180

1
1

1

.t:..vcc = 5.$11
.............

I

...........

~
1""-.. I
: '-."

...........

~ ..... ......, ~

rVCC ±10%

~

:

120

1

50

vcc=5.:aS J

1

:

60

~

ICC-mA l40

:

1

:

100

io

1

-55:
-75

1
1
1
1
1

LvCc=5%

--

-

............

-55,

-50

-25

0

25

50

75

100

125

10
-75

TA-AMBIENT TEMPERATURE-oC

0

25

50

75

100

125

Definition of Timing Diagram

;:1

Ti

R1

lOon

.'

CL~

-25

TA-AMBIENT TEMPERATURE-oC

Switching Test Load

OUTPUT

-50

WAVEFORM

~

~

DONTCARE;
CHANGE PERMITTED

CHANGING:
STATE UNKNOWN'

It).~

NOT
APPLICABLE

.CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

OUTPUTS

.

.

R2
-=-60011

Definition of Waveforms;.

:,o r
o

~_='==:====:======:==='=.:'=• ..•==1=): B=· ~9=Y=: :~: :

NOTES: 1. Input pulse amplitude a

t-'(k

v to 3.0 V.

2. Input rise and fall times 2-S ns from 0.8 V to 2.0 V.

3. Input access meesured at the 1.S V level.
4. tAA Is tested with switch 8 1 closed. C L = 30 pF and measured at 1.SVoutput level.
S. tEA Is measiJred at the 1.S V output level with C L = 30 pF. Sl is open for high Impedance to "1" test, and closed for high impedance to "0" test.
tER Is tested with CL = 5 pF. 81 is open for "1" to high impedance test, measured at VOH - O.S output leVel: 81 Is closed for "O"to
high impedance test measured at VOl • O.SV output level.
~

~.,

3.;43

53/63S3281 53/63S3281A

Commercial Programmers
Monolithic M~mories PROMs are designed and tested to give a
programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each time a new board
or a new programming moqule is inserted, the whole system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember- The best. PROMs available can be made
unreliable by improper programming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

Data I/O Corp.
10525 Willows Rd. N.E.
Redmond, WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
SunnYvale, CA 94089

Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94089

..

Metal Mask Layout

High Performance

53/63RA481
53/63RA481A

512x8
Registered PROM

Ordering Information

Features/Benefits
• Versatile synchronous and asynchronous enables

PACKAGE

. MEMORY

• Asynchronous preset and clear

SIZE PERFORMANCE PINS TYPE

• Edge-triggered "0' registers
• 8-bit-wide in 24-pln SKINNYOIP® for high board density

Standard

24
(28)

4K
Enhanced

• On-chip register simplifies system timing

OEVICETYPE
COM

MIL

NS,JS, 53RA481 63RA481
(NL),
(L) 53RA481A 63RA481A

• Faster cycle times

Flatpak - Contact the factory.

• 16 mA IOL output drive capability

Data is transferred into the output registers on the rising edge of
the clock. The data will appear at the outputs provided that both
the asynchronous (E) and synchronous (ES) enables are Low.
Prior to the positive clock edge, register data are not affected by
changes in addressing or synchronous enable. inputs.

• Reliable titanium-tungsten fuses (Ti-W), with programming
yields typically greater than 98%

Applications

Memory expansion and data control is made more flexible with
synchronous and asynchronous enable inputs. Outputs may be
set to the high-impedance state at any time by setting Eto a High
or if ES is High when the rising clock edge occurs. When Vee
power is first applied, the synchronous enable flip-flop will be in
the set condition causing the. outputs to be in the highimpedance state.

• Microprogram control store
• State sequencers/state machines
• Next address generation
• Mapping PROM

Description
The 53/63RA481 and 53/63RA481 A are 512x8 Registered PROMs
with on-chip "D" type registers, versatile output enable control
through synchronous and· asynchronous three-state enable
inputs, and asynchronous preset and clear.

The output registers will be set to all Highs when preset is
Low independent of the state of clock. The OUtput registers will
be reset to all Lows when clear is Low independent of the state
of clock. Note thatpreset and clear are exclusive operations and
cannot occur simultaneously.

Pin Configurations

Block Diagram

AS A6 A7 NCIICC A8
4

3

2

A8
A7
A6
AS

Pii

32 X 128
PROGRAMMABLE
ARRAY

10F32
ROW
DECODER

A4

1 28 27 26

it

0

ClR

ES
512x8

ClK
21

NC
07
06

A3
1 OF 16
A2
COLUMN
A1
DECODER
AO--

Pii

12 13 1415 16 17 18
01 02GNDNC Q3 Q4 05
ClK

ES

E
00 01

SKINNYDlpe is a register~d trademark of Monolithic Memories

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

02

03 04 05 Q6

07

m

.onollthIO.
• •morles

3·45

53/63RA481A

53/63RA481
Absolute Maximum Ratings

Operating
Programming
Supply voltage Vee ..•.•••.••........•.......•••.. " .... " •...•...........•..... -0.5 V to 7 V •........•.....•..... 12V
Input voltage ..•.•...•••.•....•.•...................•.......••.................. -1.5 Vto 7 V •..................... 7V
Input current ...........•................................................... -30 mA to +5 mA
Off-state output voltage •.••............••.....•.•.....•....................•.•. -0.5 V to 5.5 V ..........•.•.•....•. 12V
Storage temperature .....••....•..•.....•.. '" .••..•...•...................•• -65·e to +150·e

Operating Conditions
COMMERCIAL
SYMBOL

PARAMETER

TYPt

63RA481A

MILITARY

63RA481

53RA481A

53RA481

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX

Vee

Supply voltage

5.0

4.75 5.25

TA

Operating free-air temperature

25

0

tw

Width of clock (High or Low)

10

20

20

20

20

ns

tprw

Width of preset or clear
(Low) to Output (High or Low)

10

20

20

20

20

ns

tcl rw
tprr

Recovery from preset or clear
(Low) to clock High

11

20

20

25

25

ns

tcl rr
ts (A)

Setup time from address to clock

22

30

35

35

45

ns

ts (ES)

Setup time from ES to clock

7

10

10

15

15

ns

th (A)

Hold time from address to clock

-5

0

0

0

0

ns

th (ES)

Hold time from ES to clock

-3

5

5

5

5

ns

75

4.75 5.25

4.5

5.5

4.5

5.5

V

0

-55

125

-55

125

·e

75

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

TEST CONDITIONS

VIL

Low-level input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

Vee= MIN

II

= -18111A

IlL

Low-level input cu rrent

Vee = MAX

VI

= 0.4 V

IIH

High-level input current

Vee = MAX

VI

= Vee

VOL

Lowclevel output voltage

Vee= MIN

10L = 16mA

VOH

High-level output voltage

Vee= MIN

Off-state output current

Vee= MAX

10ZL

MAX UNIT

0.8
2.0

MIL 10H = -2 mA
eOM IOH = -3.2 mA

10ZH
lOS

Output short-circuit current*

Vee = 5V

lee

Supply eurrent

Vee = MAX

40

p,A

0.5

V
V

2.4

40

All inputs TTL; all outputs open.

t

Typical at 5.0 V vee and 25° eTA'

m

V
mA

-40

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

IIIIonoIlthlo

-1.2
-0.25

VO= 2.4 V
Vo= OV

l/IIemorles

V
V

VO=O.4V

*

3-46

MIN TYPt

-20
130

p,A

-90

mA

180

mA

53/63RA481
Switching Characteristics

53/63RA481A

Over Operating Conditions and using Standard Test load
COMMERCIAL

SYMBOL

t

PARAMETER

TYPt

MiliTARY

63RA481A

63RA481

53RA481A

53RA481

MIN MAX

MIN MAX

MIN MAX

MIN MAX

UNIT

tCLK

Clock to output Delay

11

15

20

20

25

ns

tESA

Clock to output access time (ES)

14

25

30

30

35

ns

tESR

Clock to output recovery time (ES)

14

25

30

30

35

ns

tEA

Enable to output access time (E)

10

20

30

25

35

ns

tER

Disable to output recovery time (E)

10

20

30

25

35

ns

tpR

Preset to output delay (PR)

15

25

25

25

30

ns

tCLR

Clear to output delay (CLR)

18

25

30

35

40

ns

Typical at 5.0 V VCC and 25°C T A-

Function Table

E

ES

ClK

PR

ClR

A8-AO

07-00

H
X
L
L
L
L

X
H
L
L
L
L

X

X
X
L
H
L
H

X
X
H
L
L
H

X
X
X
X
X
A

Z
Z
H
L

1
X
X
X

t

Data

Operation

High-Impedance
High-Impedance
Preset
Clear
Illegal Operation
Memory Access

Definition of Waveforms

A

-----------------.r~ r'"~..---------­

f7

--

9--l...--~--r--·/
E_ _

-----'-----'1 t-

----'-I

elK

Q

NOTES: ,. Input pulse amplitude 0 V to 3.0 V.
2. Input rise and fall times 2-5 ns from 0.8 V to 2.0 V.

3. Input access measured at the 1.5 V level.
~ 30 pF and outputs measured at '.5 V output level for all tests except t ESA and tESA.
5. tEA and tESA are measured at the '.5 V output level with CL ~ 30 pF. S, is open for high impedance to "1" test, and closed for high
impedance to "cr' test.
tER and tE5R is tested with Cl ~ 5 pF. 51 is open for "1" to high impedance test, measured at VOH -0.5 output level: 8 1 is closed for "0" to
high impedance test measured at VOL + O.5V output level.

4. Switch S, is closed. C l

IIIIonoIlthic

W Wlemorles

3-47

53/63RA481

53/63RA481A
Definition of Timing Diagram

Switching Test Load

WAVEFORM

):1

Ti

OUTPUTS

INPUTS
DON,. CARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

R1

300n

OUTPUT

.

"~

~.'"
R2

Schematic of Inputs and Outputs
EQUIVALENT OUTPUT

EQUIVALENT INPUT

--------------~--oVCC

Vcco-----~--------

INPUT

o-.--F---KI--+-L..r>l--+---oOUTPUT

ENABLE ••• _-+-_..J

3-48

IIIIonoIlthlc

W Memories

53/63RA481A

53/63RA481

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give a
programming yield greater than 98%. If your programming
yield is lower. check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each time a new board
or a new programming module is inserted. the whole system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine.

Remember - The best PROMs available can be made
unreliable by improper programming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

Data 1/0 Corp.
10525 Willows Rd. N.E.
Redmond. WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
Sunnyvale. CA 94089

Kontron Electronics. Inc.
630 Price Ave.
Redwood City. CA 94063

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale. CA 94089

Metal Mask Layout

I/IIonoIIthic

W IIIemories

3-49

High Performance

1024x8

53/63RS881
53/63RS881A

Registered PROM
Features/Benefits '

Ordering Information

• Edge triggered "D" registers

MEMORY

PACKAGE

DEVICE TYPE

• Synchronous and asynchronous enables
SIZE PERFORMANCE PINS TYPE

• Versatile 1:16 Initialization words
• 8-bit-wlde In 24-pin SKINNYDIP® for high board density
• Simplifies system timing

Standard
8K
Enhanced

Mil

COM

NS,JS, 53RS881 63RS881
(Nl),
(L),W 53RS881A 63RS881A

24
,(28)

• Faster cycle times
• 16 mA IOl output drive capabliHy

the positive clock edge, register data are not affected by
changes in addressing or synchronous enable inputs,

• Reliable titanium-tungsten fuses (TIW), with
programming yields typically greater than 98"/.

Memory expansion and data control is made flexible with synchronous and asynchronous enable inputs, Outputs may be set
to the high impedance state at any time by setting 'Eto a high or if
ES is high when the riSing clock edge occurs, When VCC power
is first applied the synchronous enable flip-flop will be in the set
condition causing the outputs to be in the high impedance state,

Applications
• Microprogram control store

• State sequencers
• Next address generation
• Mapping PROM

Description
The 53163RS881 and 53163RS881A are 1Kx8 PROMs with onchip "0" type registers, versatile output enable control through
synchronous and asynchronous enable inputs, and flexible start
up sequencing through programmable initialization,
Data is transferred into the output registers on the riSing edge of
the clock, Provided that the asynchronous (E) and synchronous
(ES) enables are low, the data will appear at the outputs, Priorto

The flexible initialization feature allows start up and time out
sequencing with 1:16 programmable words to be loaded into the
output registers, With the synchronous INITIALIZE (IS) pin low,
one of the 16 column words (A3-AO) will be set in the output
registers independent of the row addresses (A9-A4), The
unprogrammed state of is words are low, presenting a CLEAR
with is pin low, With all is column words (AS-AO) programmed
to the same pattern, the is function will be independent of both
row and column addressing and may be used as a single pin
control. With all is words programmed high a PRESET function
is performed.

BtocJt 'Diagram
Pin Configurations

Ail

AI
64X128
PROGRAMMABLE
ARRAY

A7

AI
AS

A4

AS Nl A7 NC1ItCNl A9
4
A4

3 2

0

E
,is
6,

A1

.CLK

AD

NC

NC

07

co

IS
A3
A2
A1
AD

Q6

12 13 14 15 16 17' 18
01 Q2GNONCQ3 Q4 Q5

,CLK

6

E
00

SKINNYDIP~ is a registered trademark of Monolithic Memories

TWX:. 910-338-2376 '

2175 Minion College Blvd. Sante Clara, CA 95054-1592 Tel: (408)

3..:50

970~9700 TWX: 910-338~2374

01

02

03

04

05

Q6

07

.onallthlorrrsn
marl. . II1.IlW

••

53/63RS881 53/63RS881A
.ings

Operating
Programming
.............................................. -0.5 V 10 7 V .................... 12 V
.............................................. -1.5Vl07V ...................... 7V
......................................... -30 rnA 10 +5 rnA
, .•.......... " ., ........ " ................. -0.5 V 105.5 V .......•....•......• 12 V
........................................• -65°e to +150 oe

MILITARY
IMETER

TYPt

53RS881A

COMMERCIAL

53RS881

63RS881A

63RS881

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX
lorlow)

10

20

20

20

20

Iress 10 clock

25

40

45

30

35

ns

8

15

15

15

15

ns

o clock

20

30

35

25

30

ns

) clock

-5

0

0

0

0

ns

-3

5

5

5

5

ns

-5

0

0

0

0

ns

10 clock

lrnperalure

5

4.5

5.5

4.5

5.5

4.755.25

25

-55

125

-55

125

0

75

ns

4.75 5.25
0

75

V
°e

CS Over Operating Conditions
TEST CONDITION

MIN TYPt MAX

e

0.8

je

2

= MIN
Vee = MAX
Vee = MAX
Vee = MIN
Vee

II

nl
ge

VI
VI

Vee = MIN

IOL=16rnA

,1

Vee = MAX
Vee = 5V

eOM IOH = -3.2 rnA

-1.2

V

-0.25

rnA

40

J.l.A

0.5

V

2.4

V

Vo = 0.4V

-40

Vo = 2.4 V

40

Vo = OV

Vee = MAX. All inpuls TTL; all oulpuls open

V
V

= -18rnA
= 0.4 V
= Vee MAX

MIL IOH = -2 rnA

1ge

Jrrenl*

II

UNIT

-20
130

J.l.A

-90

rnA

180

rnA

I at a time and duration of the short-circuit should not exceed one second.

MonoIHhlcWMemOries

3·51

53/63RS881 53/63RS881A
Switching Characteristics Over Operating Conditions and using Standard TestL
MILITARY
PARAMETER

SYMBOL

TYP

53RS881A
MIN

I
i

~

...

MAX

53RS881
MIN

MAX

tClK

Clock to output Delay

10

20

tESA

Clock to output access time (ES)

25

18

30

35

tESR

Clock to output recovery time (ES)

17

30

35

tEA

Enable to output access time (E)

18

30

35

tER

Disable to output recovery time (E)

17

30

35

Definition of Waveforms

.L-/·f__

ES _ _

IS(ES)

I

I

ClK

Q

NOTE5: 1. Input pulse amplitude 0 V to 3.0 V.
.2. Input rise and fall times 2-5 ns from 0.8 V to 2.0 V.
3. Input access measured at the 1.5 V level.

4. tAA is testedwilh sWitch 51 closed.Cl = 30 pF and measured at 1.5 V oulput level.
5. tEA and t ESA are measured at the 1.5 V output level with C l = 30 pF. 51 is open for high impedance
impedance to "0" test.

"1"

to high impedance lesl, measured at VOH -,
tER and tEA are measured. C l =5 pF. 51 Is open for
high impedance lest meesured at VOL + 0.5 V oulpul level.

t

ft

53/63RS881 53/63RS881A
Definition of Timing Diagram

Switching Test Load

;:1

, :rI'

3000

OUTPUT

'

'

CL~

"

R1

WAVEFOR~

'U&M

INPUTS
DON'T CARE;
CHANGE PERMITTED

mmNOT
APPLICABLE

.£D ill..

OUTPUTS
CHANGING;
STATE UNKNOWN

CENTER LINE IS
HIGH IMPEDANCE STATE

R2

'::' 6000
MUST BE STEADY

WILL BE STEADY

Schematic of Inputs and Outputs

EQUIVALENT jNPUT
VCC
1IlcfiNOM

TYPICAL OUTPUT

VCC
4O{l NOM

INPUT o-.-~--KI-1~
OUTPUT

53/63RS881 53/63RS881A

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give a
programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each time a new board
or a new programming module is inserted, the whole system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember - The best PROMs available can be made
unreliable by improper programming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

Data I/O Corp.
10525 Willows Rd. N.E.
Redmond, WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
Sunnyvale, CA 94089

Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94089

Metal Mask Layout

A4
A3

A2
A1

AO
QO

3·54

Q1

Q2

GND

IIIIonoIlthlo

Q3

m

Q4

QS

Memories

204SxS
Re.gistered PROM

53/63RA1681
53/63f1A1681A

with Asynchronous Enable

Ordering Information

Features/Benefits
• Synchronous output enable

MEMORY

• Edge-triggered "0" registers

OEVICETYPE

PACKAGE

SIZE PERFORMANCE PINS TYPE

• Versatile 1:16 user programmable initialization words
• 8"bit-wide in 24-pln SKINNYOIP® for high board density

Standard
16K

• Simplifies system timing

Enhanced

• Faster cycle times

MIL

COM

NS,
53RAl681 63RAl681
24 JS,W,
(2S) (NL),
(L) 53RAl681A 63RAl681A

• 16 mA IOL Qutput drive capability

Flat-pack - contact the factory

• Reliable titanium-tungsten fuses (TIW), with
, programming yields typically greater than 98"10

Data is transferred into the output registers on the rising edge of
the clock. Provided that the asynchronous enable IE'> is low, the
data will appear at the outPl!ts. Prior to the positive clock edge,
register data are not affected by changes in addressing.

Applications

Memory expansion and data control, is made flexible with
asynchrol)ous enable inputs. Outputs may be set to the high
impedance state at any time by setting E to a HIGH.

• Microprogram control store .
• State sequencers
• Next address generation
• Mapping PROM

Description
The 53/63RAl681 and 53/63RAl681A are 2KXS PROMs with
"Dn_type registers, Output enable control through an
asynchronous enable input and flexible start up sequencing
through programmable initialization words.

on~hip

A10,
A9
A8
A7
A6

AS /II, A7 NC1ICCAB AS

1211x128

PR.OGRAMMABLE
ARRAY

AS

4' 3

A4'

d

A10

2048x8

CLK

is
E

AS

1\2
A1

a

BIGeI( Diagram

Pin Configurations

.A4

The flexible initialization feature ~lIows start up and time out
sequencing with 1:16 programmablewords'tpbe loaded into the
output register's. With the synchronous INITIALIZE (IS) pin
LOW, one of the 16 column words (A3-AO) will be set in the
output registers independent of the row addresses (A9-A4).
With all is column words (A3-AO) programmed to the same
pattern, the IS functipn viiill ,bein~pende~t of both row and
column ~dressing arid rl)t\y be used as single pin control.
With all IS words ptOQrdmmed HIGH' a PRESET function is
performed. The unprogrf\mmed state of IS won;ls are LOW,
presenting a CLEAR with is pin LOW.

AI!

He

HC

07

QO

A3

A2

A1
AO

Q6

,'12 13 14 15 16 17 18
01 Q2GNDNC Q3 Q4

os

00

S!(INNVOIf'8 is a registered trademark of Monolithic M8morias

:.'
. .
,'TWX:910-338·2376
2175 Mistiion College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

01

02

03

04

05

06

07

53/83RA1881 53/83RA1881A

Absolute Maximum Ratings

Operating
Programming
Supply voltage Vec ....•. , ••.•. ". '.' •.•..•.•. ; .•.......•...•.....•..•.......... ~0.5 y,to 1 V ..................... 12V
Input voltage ............................................................... , .•. -1.5 'il to 7 V .•...•................ 7V
Input cu~r:ent ................ '.' ............................................... -30 mA to +5 mA
Off-state output voltage. . • . • . • . • . • . • . . .. • . . . .. . • . . . . . • . . . • . . . • . . . • . .. . . . . . . . .. -0.5 V to 5.5 V .................... 12V
Storage temperatura .........•... : ....;'.•...•.•.•.................•.......•.. -65·e to +15Q·e

Operating Conditions
MILITARY
SYMBOL

TYpt

PARAMETER

COMMERCIAL

53RA1681A 53RA1681 S3RA1681A 63RA1681

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX
tw

Width of clock (high or low)

10

20

20

20

20

ns

ta(A)

Setup time from address to clock

28

40

45

35

40

ns

ts(IS)

Setup time from IS to clock

20

30

35

25

30

ns

th(A)

Hold time address to clock

-5

0

0

0

0

ns

Hold time (IS)

-5

0

0

ns

th(IS)
Vee

Supply voltage

TA

Operating free-air temperature

0

0

5

4.5

5.5

4.5

5.5

4.75 5.25

4.755.25

25

-55

125

-55

125

0

0

75

75

V
·e

Electrical Characteristics Over OperalingCondHlons
SYMBOL

PARAMETER

TEST CONDITION

VIL

Low-level input voltage

VIH

High-level input voltage

VIC

Input clamp voltage

Vee = MIN

II = -18mA

IlL

Low-level input current

Vee = MAX

VI = 0.4 V

IIH

High-level input current

Vee = MAX

VI = Vee MAX

VOL

Low-level output voltage

Vee = MIN

IOL=16mA

VOH
IOZL

0.8
2.0

MIL 10H = -2 rnA

High-level output voltage

Vee = MIN

Off-state output current

Vee = MAX

10ZH

*

t

MIN TYPt, MAX

lOS

Output short-circuit current*

ICC

Supply current

.,

Vee = 5V

3·56

V
mA

40

p.A

0.5

V
V

-40

Vo = 2.4 V

40
-20

Vo= OV

140

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one.second.
Typical at 5.0 V Vee and 25'e TA'

-1.2
-0.25

VO=0.4V

Vee =' MAX. All Inputs TIL; all outputs open

.

V
V

2.4

COM 10H = -3.2 mA

UNIT

p.A

-90

mA

185

mA

53/63RA1681 53/63RA1681A

Switching Characteristics Over Operating Conditions and using Standard Test load
COMMERCIAL

MiliTARY
SYMBOL

Typt

PARAMETER

53RA1681A
MIN

t

MAX

53RA1681
MIN

63RA1681A

MAX

MIN

MAX

63RA1681
MIN

UNIT

MAX

tClK

Clock to output Delay

10

20

25

15

20

ns

tEA

Enable to output access time (E)

15

30

35

25

30

ns

tER

Disable to output recovery time (E)

15

30

35

25

30

ns

Typical at 5.0 V Vee and 25" eTA-

Definition of Waveforms

elK

I--tER~j
)

Q

l....-.tEA-!

\\-VOH-O.SV

____--'_'-'Z.....7-VOL +o.sv

or

ill..

NOTES: 1. Input pulse amplitude 0 V to 3.0 v.
2. Input rise and fall times 2-5 ns from 0.8 V to 2.0 V.
3. Input access measured at the 1.5 V level.
4. Switch 8 1 is closed. C L :: 30 pF and outputs measured at 1.5 V output level for all tests except tEA and t ER ,
5. tEA is measured at the 1.5 V output level with CL = 30 pF. 81 is open for high impedance to "1" test and closed for high

impedance to "0" te_st.
tER is tested with CL = 5 pF. 8 1 is open for "1" to high impedance test, measured at VOH -0.5 V output level; 51 is closed for "0" to
high impedance test measured at VOL + 0.5 V output level.

IIIonoIHhlo!!WI Memories

3-57

53/63RA1681 53/63RA1681A

Definition of Timing Diagram

Switching Test Load

;:1

WAVEFORM

:r-l

INPUTS

OUTPUTS

DON'T CARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

NOT
APPLICABLE

CENTER liNE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

Will BE STEADY

R1

3000

OUTPUT

.

R2

ClI
":'"

6000

":'"

Schematic of Inputs and Outputs

.:..TY:..:P..:.:IC::A=l--=O:.:U:..:T:...:PU::.:T~--<>VCC

EQUIVALENT INPUT
VCC
8kO NOM

400 NOM

INPUT O-~-fE'--KI--t-OUTPUT

3·58

IIIIonoIllhic

W Memorle.

53/63RA1681 53/63RA1681A

Commercial Programmers
Monolithic Memories PROMs are designed and tested to givea
programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each time a new board
or a new programming module is inserted, the whole system
should be checked. Both timing and voltages must meet
publ ished specifications for the device.

Programming is' final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember - The best PRQMs available can be made
unreliable by;mproper programming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

Data 1/0 Corp.
10525 Willows Rd. N.E.
Redmond, WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
Sunnyvale, CA 94089

Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94089

Metal Mask Layout
AS

A6

Monolithic

A7

vee

m

A8A9

Memories

3·59

2048x8

53/63RS1681
53/63RS1681A

Registered PROM
with Synchronous Enable

Ordering Information

Features/ Benefits
• Synchronous output enable

MEMORY

• Edge-triggered "0" registers

DEVICE TYPE

PACKAGE

SIZE PERFORMANCE PINS TYPE

• Versatile 1:16 user programmable initialization words
• 8-bit-wide in 24-pin SKINNYDIP® for high board density

Standard
16K

• Simplifies system timing

Enhanced

• Faster cycle times

MIL

COM

NS,
53RS1681
63RS1681
24 JS,W,
(28) (NL),
(L) 53RS1681A 63RS1681A

• 16 mA IOL output drive capability

Flat-pack - contact the factory

• Reliable titanium-tungsten fuses (TiW), with
programming yields typically greater than 98%

the data will appear at the outputs. Prior to the positive clock
edge, register data are not affected by changes in addressing or
synchronous enable inputs.
Memory expansion and data control is made flexible with synchronous enable inputs. Outputs may be set to the high impedance state by setting ES HIGH before the rising clock edge
occurs. When VCC power is first applied the synchronous enable flip-flop will be in the set condition causing the outputs to be
in the high impedance state.

Applications
• Microprogram control store
• State sequencers
• Next address generation
• Mapping PROM

Description
The 53/63RS1681 and 53/63RS1681A are 2Kx8 PROMs with
on-chip "0" type registers, versatile output enable control
through synchronous enable inputs and flexible start up sequencing through programmable initialization words.
Data is transferred into the output reg isters on the rising edge of
the clock. Provided that the synchronous (ES) enable is LOW,

Block Diagram

Pin Configurations

Al0
A9
A8
A7
A6
AS
A4

AS A6 A7 NCIItC A8 A9

4

3

2

1 OF 128
ROW
DECODER

128x128
PROGRAMMABLE
ARRAY

1 28 27 26

0

Al0

is
ES
Al

The flexible initialization feature allows start up and time out
sequencing with 1:16 programmable words to be loaded into the
output registers. With the synchronous INITIALIZE (IS) pin
LOW, one of the 16 column words (A3-AO) will be set in the
output registers independent of the row addresses (A10-A4).
With all IS column words (A3-AO) programmed to the same
pattern, the is function will be independent of both row and
column addreSSing and may be used as a single pin control.
With all 18 words programmed HIGH a PRESET function is
performed. The unprogrammed state of IS words are LOW,
presenting a CLEAR with "is pin LOW.

2048x8

ClK

AO

NC

NC

Q7

QO

IS
1.3
A2
Al
AO

Q6
12 13 14 15 16 17 18
Q1 Q2GND'NC Q3 Q4 Q5

QO

SKINNYOI?® is a registered trademark of Monolithic Memories

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

3-60

Ql

Q2

Q3

Q4

Q5

Q6

Q7

MonolIth/cOIl

Memories

S3/6.3RS1681 S3/63RS1681 A
Absolute Maximum Ratings

Operating
-0.5 V to 7 V
Supply voltage V
Input voltage ••••.•••.•...•.••....••.••••••••••..•• " ..•....••...•••.••••.••••.. -1.5 V to 7 V
Input current ............................................................... -30 mA to +5 mA
Off-state output voltage .•.•••••••••..••...•.•.•. """ ••.••••..•••.•••..•.•.... -0.5 V to 5.5 V
Storage temperature ........................................................ -65·C to +150·C

cc .......................... , .................................

. Programming

.................... 12V
..•••.•••••••••..••... 7V
.................... 12V

Operating Conditions
MILITARY
SYMBOL

COMMERCIAL

TYpt 53RS1681A 53RS1681 63RS1681A 63RS1681 UNIT

PARAMETER

MIN MAX MIN MAX MIN MAX MIN MAX
tw

Width of clock (high or low)

10

20

20

20

20

ns

ts(A)

Setup time from address to clock

28

40

45

35

40

ns

ts(ES)

Setup time from ES to clock

7

15

15

15

15

ns

ts(IS)

Setup time from IS to clock

20

30

35

25

30

ns

th(A)

Hold time address to clock

-5

0

0

0

0

ns

th(ES)

Hold time (ES)

-3

5

5

5

5

ns

th(IS)

Hold time (IS)

-5

0

0

0

0

ns

VCC

Supply voltage

TA

Operating free-air temperature

5

4.5

5.5

4.5

5.5

4.755.25

25

-55

125

-55

125

0

75

4.755.25
0

75

V
·C

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

TEST CONDITION

VIH

High-level input voltage

VIC

Input clamp voltage

VCC= MIN

I, = -1!lmA

I,L

Low-level input current

VCC = MAX

V, = 0.4 V

-0.25

mA

"H

High-level input current

VCC = MAX

V, = VCCMAX

40

pA

VOL

Low-level output voltage

VCC= MIN

IOL=16mA

0.5

V

'OZL

High-level output voltage

Off-state output current

MIL 10H = -2 mA
VCC =MIN

V

-1.2

V

VCC= MAX

V

2.4

V

COM 10H '" -3;2 mA
Va = 0.4 V

-40

VA = 2.4V

40

lOS

Output short-circuit current*

VCC = 5V

ICC

Supply current

VCC = MAX. All Inputs TTL; all outputs open

NQt more than one output should

0.8
2.0

'OZH

*

UNIT

V,L

VOH

t

MIN TYPt MAX

Low-level input voltage

VO= OV

-20
140

pA

-90

mA

185

mA

pe shorted at a time and duration of the stTort--circuit should not exceed one second.

Typical a15.0 V Vee and 25'e TA

3~61

53/63RS1681 53/63RS1681A

Switching Characteristics Over Operating Conditions and using Standard Test LOad
MILITARY
SYMBOL

PARAMETER

TYPt

53RS1681A
MIN

MIN

MAX

63RS1681A
MIN

MAX

63RS1681
MIN

UNIT

MAX

Clock to output Delay

10

20

25

15

20

ns

tESA

Clock to output access time (ESj

15

30

35

25

30

ns

tESR

Clock to output recovery time (ES)

15

30

35

25

30

ns

tCLK

t

MAX

COMMERCIAL

53RS1681

Typical at 5.0 V VCC and 25° C T A.

Definition of Waveforms

NOTES: 1. Input pulse amplitude 0 V to 3.0 V.
2. Input rise and fall times 2-5 ns from 0.8 V to 2.0 V.

3. Input access measured at the 1.5 V level.
4. Switch Sl is closed. C L = 30 pF and outputs measured at 1.5 V output level for all tests except t ESA and t ESR
5. tESA is measured at the 1.5 V output level with CL = 30 pF. Sl is open for high impedance to "1" test and closed for high
impedance to "0" test.
tESR is tested with CL =5 pF. Sl is open for "1" to high impedance test, measured at VOH -0.5 V output level; Sl is closed for "0" to
high impedance test measured at VOL + 0.5 V output level.

3·62

IIIIonollthlc WMemorles

·53/63RS1681 53/63RS1681 A

Switching Test Load

Definition of Timing Diagram

;:1

:rl

R1

WAVEFORM

INPUTS

'tIIItIIIItI/I.

DON'T CARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

1lj «{

NOT
APPLICABLE

CENTER liNE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

Will BE STEADY

OUTPUTS

300n

OUTPUT

Cl

R2
600n

I

~

":'

":"

Schematic of Inputs and Outputs

EQUIVALENT INPUT
VCC

BIen

NOM

TYPICAL OUTPUT

Vee
40fi NOM

INPUT o-..--fE--KIt-t-OUTPUT

3-83

53/63RS1681 53/63RS1681 A

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give a
programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each time a new board
or a new programming module is inserted, the whole system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing ~ it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember - The best PROMs available can be made
unreliable by improper programming techniques.

PROM PROGRAMMING EQUIPMENT INFORMATION
SOURCE AND LOCATION

Data I/O Corp.
10525 Willows Rd. N.E.
Redmond, WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
Sunnyvale, CA 94089

Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94089

Metal Mask Layout
AS

AS

A7 vee

.AS AS

1 024x4 Diagnostic
Registered PROM

53/63DA441
53/63DA442

Enables and Output Initialization
Features/Benefits
• Programmable asynchronous output initialization
• Three-state outputs with 2 enables
• Provides system diagnostic testing with system
controllability and observability
• Shadow register eliminates shifting hazards
• Edge-triggered "D~' registers simplifies system liming
• Cascadable for wide control words used in
microprogramming
• 24-pin SKINNYDIP® saves space
• 24-mA output drive capability
• Replaces embedded diagnostic code
• Guaranteed programming yields of greater than 98%

Applications
• Microprogram control store with built-in
system diagnostic testing

Patent Pend.

Shadow register diagnostics allow observation and control of
the system without introducing intermediate illegal states. The
output register, which can receive parallel data from either the
PROM array or the shadow register is loaded on the rising edge
of ClK. The shadow register, which can receive parallel data
from the output register or serial data from SOl; is loaded on the
rising edge of OClK. When the output drivers are disabled, the
shadow register receives its parallel data from the output bus.
During diagnostics, data loaded into the output register from the
PROM array can be parallel-loaded into the shadow register and
serially shifted out through SOO, allowing observation of the
system. Similarly, diagnostic data can be serially shifted into the
shadow register through SOl, and parallel-loaded into the
output register, allowing control. and test scanning to be
imposed on the system. Since the output register and the
shadow register are loaded by different input signals, they can
be operated independently of one another. In addition, diagnostic PROMs can be cascaded to construct wide control words
used in microprogramming.
When exercised, the initialization input loads the output register
with a user-programmable initialization word, independent of
the state of ClK. This features is a superset of preset and clear
functions, and can be used to generate an arbitrary microinstruction for system reset or interrupt.

• Serial character generator
• Serial code converter
• Parallel in/serial out memory
• Cost-effective board testing

Description
The 53/63DA441 and 53/63DA442 are 1Kx4 PROMs with registered outputs, programmable asynchronous initialization, 3stateoutputs with 2 enables and a shadow register for diagnostic
capabilities.

The distinguishing feature between the 53/630A441 and 53/
630A442 is on the output enable structure. The53/630A441 has
two asynchronous output enables, E1 and 82. Outputs will be
enabled when both E1 and 1:;2 are lOW. The 53/630A442 has
one asynchronous output enable Eand one synchronous output enable ES. Outputs will be enabled if Es is lOW during the
last rising edge of ClK and E is lOW.

Selection Guide
MEMORY
SIZE

ORGANIZATION

4K

1024 x4

PACKAGE
OPTIONS

PINS

TYPE

24
(28)

NS,JS,W,
(Nl),(l)

Two asynchronous enables
One synchronous enable,
one asynchronous enable

SKINNYDIP® is a registered trademark of Monolithic Memories

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

PART NUMBER

MILITARY

COMMERCIAL

530A441

630A441

530A442

63DA442

lfonolit.hicm
memor.es
3-65

53/63DA441

53/63DA442

Block Diagrams .
53/63DA442

53163DA441

,Ao

Ae-Ao

OCLK

OCLK

I-"""..,-~-+-"SOO .

SOl

·~~~--+--"SDO

SOl

I----i
CLK ......- - - I >

CLK----I>

E1

fi

ES

:=::[:)----Vf-----~

E==~-T--~~

______~

03-00

03-00

53163DA441
AS NO A7 Neva: NO AS

4321282726

Logic Symbols

o

A4

A3

53163DA442

53163DA441
00

A1

AO

NC

NC

01

MOOE

02
12 13 14 15 18 17 18

DCLK GNO
SOl

eLK
Q3
NC SDO

53163DA442
AS NO A7 Neva: NO AS

4321262726

o
A2
A1

00

NC

01

NC
Q2

MODE

12 13 1415 16 17 18

DCLK GND eLK
Q3
SOl
.Ne SDO

IIIonoIIthJc

m

lllleinorles

53/63DA441

53/63DA442

Function Table
INPUTS

OUTPUTS
OPERATION

MODE

SOl

ClK

OClK

03-00

sa-so

SOO

l

X

1

•

On- PROM

HOLD

53

load output register from PROM array

l

X

*

1

HOLD

53

Shift shadow register data

1

On- PROM

53

load output register from PROM array
while shifting shadow register data

l

*

t

X

1

Sn- Sn-1

50- 501
Sn -

Sn-1

50- 501

H

X

1

*

On-Sn

HOLD

501

load output register from shadow register

H

l

•

HOLD

Sn- On

501

load shadow register from output bus

H

H

*

1
1

HOLD

HOLD

501

No operationt

The MODE pin controls the output register multiplexer and the shadow register. When MODE is
lOW, the output register receives data from the
PROM array and the shadow register is configured as a shift register with 501 as its input. When
MODE is HIGH, the output register receives data
from the shadow register. The shadow register is
controlled by 501 as well as MODE With MODE
HIGH and 501 lOW, the shadow register receives parallel data from the output bus. With
MODE and 501 both HIGH, the shadow register
holds its present data.

03-00

On represents the data outputs of the output
register. During a shadow register load with outputs enabled, these pins are the internal data
inputs to the shadow register. With the outputs
three-stated, these pins are external data inputs
to the shadow register.

53-SO

Sn represents the internal shadow register outputs.

A9-AO

An represents the address inputs to the PROM
array.

Ef,E2, E

These Output Enable pints) operate independent of ClK. For '0441, outputs are enabled if, and
only if, both Ef and E2 are lOW. For '0442,
outputs are enabled only when ES is lOW at the
last rising edge of ClK and E is lOW.

Clock must be steady or falling.
Reserved operation for SN54174S818 8-Bit Diagnostic Register.

Definition of Signals
MODE

501

The Serial Data In pin is the input to the leastsignificant bit of the shadow register when operating in the shift mode. 501 is also a control input
to the shadow register when it is not in the shift
mode.

500

The Serial Data Out pin is the output from the
most significant bit of the shadow register when
operating in the shift mode. When the shadow
register is not in the shift mode, 500 displays the
logiC level present at 501, decreaSing serial shift
time for cascaded diagnostic PROMs.

ClK

The clock pin loads the output register on the
rising edge of ClK.

DClK

The diagnostic clock pin loads or shifts the
shadow register on the rising edge of DClK.

lIIIonoIIthIo

Synchronous Output Enable for 'DA442 only.
Outputs are enabled only when' ES is lOW at the
last rising edge of ClK and Eis lOW.

T

m

The asynchronous output register initialization
input pin operates independent of ClK. Whenlis
lOW, the output register is loaded with a userprogrammable initialization word. Programmable
initialization is a super set of preset and clear
functions, and can be used to generate any
microinstruction system reset or interrupt.

Memories

3·67

53/63DA441

53/63DA442

Logic Diagram
53/63DA441
1024x4 Diagnostic PROM
with Asynchronous Initialization
and Asynchronous Enables

AS

A4

1024x4
PROM

E1

E2

A3
03020100

3·68

A2

i

A1

00

I/IIonoIHhlc

IFlD MemorIes

53/63DA441

53/63DA442

Logic Diagram
53/63DA442
1024x4 Diagnostic PROM
with Asynchronous Initialization
and Both Asynchronous and Synchronous Enables

Vee
AS

AS

AS

A4

1024x4
PROM

A3

E

ES

D3 D2 D1 DO

A2

I,

QO

Q1

Q2

Q3

SDO

eLK

3-69

53/63DA441

53/63DA442

Absolute Maximum Ratings

Operating
Programming
Supply voltage vcc ............................................................. -0.5 V to 7 V ...................... 12 V
Input voltage ................................................................... -1.5 V to 7 V ....................... 7 V
Input current .......................................................•....... -30 mA to +5 mA
Off-state output voltage ........................................................ -0.5 V to 5.5 V ...................... 12 V
Storage temperature ......................................................... . -65° to +150' C

Operating Conditions
MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

Supply voltage

4.5

TA

Operating free-air temperature

tw

Width of ClK (HIGH or lOW)

SYMBOL

PARAMETER

UNIT

5

5.5

4.75

5

5.25

V

-55

25

125

0

25

75

°c

25

10

20

10

ns

tsu

Setup time from address to ClK

45

25

35

25

ns

th

Hold time for ClK

0

-15

0

-15

ns

twd

Width of DClK (HIGH or lOW)

35

15

25

15

ns

tsud

Setup time from control inputs (SDI, MODE) to ClK, DClK

50

20

40

20

ns

thd

Hold time for DClK

0

-5

0

-5

ns

ts(ES)

Setup time from ES to ClK (,DA442 only)

20

10

15

10

ns

th(ES)

Hold time (ES) ('DA442 only)

5

0

5

0

ns

tiw

Initialization pulse width (lOW)

25

10

20

10

ns

tir

Initialization recovery time

45

30

40

30

ns

MIN TYPt MAX

UNIT

VCC

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

Vil

low-level input voltage

VIH

High-level input voltage

TEST CONDITION

0.8
2.0

VIC

Input clamp voltage

VCC: MIN

II :

III

low-level input current

VCC: MAX

VI: 0.4 V

IIH

High-level input current

VCC: MAX

VI: VCC MAX

low-level output voltage

VCC: MIN

VOH

High-level output voltage

VCC: MIN

Off-state output current

Vce: MAX

10Zl

-18 mA

COM 10l : 24 mA
Mil 10H : -2 mA
COM 10H : -3.2 mA

10ZH

mA

40

p.A

0.5

V

2.4

V

Va: 2.4 V

40

Va: OV

Output short-circuit current"

VCC: MAX

Supply current

VCC : MAX. All outputs open. All inputs TTL.

t

Typical at 5.0 V vee and 25' eTA'

"

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

m

V

-0.25

-100

lOS

IIIIonollthic

-1.2

Va: 0.4 V

ICC

3-70

V

Mil 10l: 16 mA

Val

Memories

V

-20
130

p.A

-90

mA

180

mA

53/63DA441

53/63DA442

Switching Characteristics Over Operating Conditions and Using Standard Test Load
SYMBOL

t

MILITARY
MIN TYPt MAX

PARAMETER

COMMERCIAL
MIN TYpt MAX

UNIT

tClK

ClK to output

11

25

11

18

ns

tER

Disable time

14

30

14

25

ns

tEA

Enabletima

16

30

16

25

7

10

20

ns
MHz

tMAXD

Maximum diagnostic clock frequency

tDS

DClK to SDO delay (MODE = lOW)

17

35

17

30

tss

SDI to SDO delay (MODE = HIGH)

16

30

16

25

ns

tMS

MODE to SDO delay

14

30

14

25

ns

tlO

Initialization to output delay

22

35

22

30

ns

tESR

ClK to output disable time ('DA442 only)

22

35

22

30

ns

tESA

ClK to output enable time (,DA442 only)

15

35

15

30

ns

20

Typical at 5.0 V vee and 25° eTA

Definition of Wavefonna

. INITIALIZE OUTPUT REGISTER

LOAD OUTPUT REGISTER FROM PROM ARRAY

Normal PROM Operation (Mode = LOW)
(for both 53/63DA441 and 53/63DA442 with outputs eMbled)

I/IIonoIIIhIc

m

I/IIemories

ns

53/63DA441

53/63DA442

lOAD OUTPUT REGISTER
FROM PROM ARRAY

OUTPUT DISABlEIENABlE

Normal PROM Operation (Mode = LOW)
(for S3/63DA441 only with i = HIGH)

:~'"I·;r
I
elK

Q

lOAD OUTPUT REGISTER
FROM PROM ARRAY

OUTPUT DISABlEIENABlE

Normal PROM Operation (Mode = LOW)
(for 53/63DA442 only with I" = HIGH)

3-72

Monolithic

W lIIIemories

53/63DA441

53/63DA442

1

: t_I+--,
_ _f~_thd~--t---·
...------. 1
I'
"" I

I

i s-:t L

I

't-->.."
\.....;.-_

DCLK--:-i-+--i-L-L"F~"i \~:\-+-i_r-tw--+-r_tW-j_~i_
Q

SDO

~

-h i

J

6~-:-L---'MS\
g
f;;1'

f
r.:J' ~ fis1

I

IMS

SHIFT DATA INTO SHADOW REGISTER

I

lr
tss
~

LOAD OUTPUT REGISTER
FROM SHADOW REGISTER

I

SYSTEM CONTROL

:1 r f'~'~1--1
"" I

DCLK
Q

SDO

r,··
:
\~:
-\
+-1---+1---+-1
t.Ulth~
I
t I\

---+,---...--...!.-,-l...

tWdi-l

f

i

:

~"'~:

~tMS~

LOAD OUTPUT
REGISTER FROM
PROM ARRAY

I

'---_
l\tSUd-=1-

----1-

r-thd--i

r-tMs4~~tDs+t--

LOAD SHADOW
REGISTER FROM
OUTPUT REGISTER

I

SHIFT DATA OUT OF SHADOW REGISTER

SYSTEM OBSERVATION

Monolithic

WIIII.morla.

3-73

53/63DA441
Switching Test Load

OUTPUT

Definition of Timing Diagram

WAVEFORM

INPUTS

CHANGING;
STATE UNKNOWN

)51

'tU/:III#IIh

DON'T CARE;
CHANGE PERMITTED

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

.

L:;f

OUTPUTS

VCC

:rJ"
C

53/63DA442

])

-OUTPUT

3·82

53/63DA841
Metal Mask Layout

OCLK

GNO

SOl

CLOCK

SDO

03

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give
a programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly calibrated.
Programming is final manufacturing ....c it must be qualitycontrolled. Equipment must be calibrated as a regular routine, ideally under the actual conditions of use. Each time a

MANUFACTURER
Data I/O'

PROGRAMMER
TYPE
Unipack
Unipack2

Rev V07
Rev V05

new board or a new programming module is inserted, the
whole system should be checked. Both timing and voltage
must meet published specifications for the device.

Remember - The best PROMs available can be made unrelIable by improper programming techniques.

PRO(;RAMM1N(;
MODULE

SOCKET
CONFI(;URATION

Family Code AA

Pinout Code AD

• Use socket adapter 351 A-073 Rev. A .

......"",ml/llemorles

3·83

53D1641
63D1641

4096x4 Diagnostic
Registered PROM
Asynchronous Enable

Patent Pend.

Ordering Information

Features/Benefits
• Asynchronous output enable

MEMORY.
SIZE

ORG.

16K

4096x4

• Shadow register eliminates shifting hazards
• Edge-triggered "0" regis~rs simplifies system timing

Mil

-

Com

• C8sadable lor wide control words used in
microprogramming

Flat-pack -

• 24-pln SKINNYOlp® saves space
• 24-mA output drive capability
• Replaces embedded diagnostic code

Applications
• Microprogram control store with built-in
sy.~m diagnostic testing
• Serial character generator
• Serial code conv~r
• Parallelln/serial out memory
• Cost-effective board testing

Description
The 53/6301641 is a 4Kx4 PROM with registered three-state
outputs and a shadow register for diagnostic capabilities.

Block Diagram

PACKAGE
TEMP.

• Provides system diagnostic testing lor sys~m
controllability and observability

PART NO.
PINS

TYPE

24
(28)

NS,JS,W,
(Nl),(l)

5301641
6301641

contact the factory

Shadow register diagnostics allow observation and control of
the system without introducing intermediate illegal states. The
output register, which can receive parallel data from either the
PROM array or the shadow register, is loaded on the rising
edge of ClK, The shadow register, which can receive parallel
data from the output register or serial data from SOl, is loaded
on the rising edge of OClK. When the output drivers are disabled, the Shadow register receives its parallel data from the
output bus. Ouring diagnostics, data loaded into the output
register from the PROM array can be parallel-loaded into the
shadow register and serially shifted out through SOO, allowing
observation of the system. Similarly, diagnostic data can be
serially shifted into the shadow register through SOl, and parallel-loaded into the output register, allowing control and test
scanning to be imposed on the system. Since the output register and the shadow register are loaded by different input signals, they can be operated independent of one another. In addition, diagnostic PROMs can be cascaded to construct wide
control words used in microprogramming.

Pin Configurations

A11-AO

AS A6 A7 NCVCCA6 A9

4 3
DCLK
SOl

2

1 28 27 26

0

~-+-----+--.SDO

A10
A11

E

A2

MODE ......- - - - I

00

4096x4

NC

CLK--------.

NC

01

MODE

02
12 1314 15 16 17 18

DCLK GND

DCLK

SOl

"E-------------

I

SHIFT DATA INTO SHADOW REGISTER

lOAD OUTPUT REGISTER
FROM SHADOW REGISTER

SYSTEM CONTROL

lOAD OUTPUT
REGISTER FROM
PROM ARRAY

I

lOAD SHADOW
REGISTER FROM
OUTPUT REGISTER

SHIFT DATA OUT OF SHADOW REGISTER

SYSTEM OBSERVATION
Monolithic

m

Memories

3·89

53/63D1641
Definition of Timing Diagram

Switching Test Load

OUTPUTS

WAVEFORM

INPUTS

~

DON'T CARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

1» ~

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

NOTES: 1. For commercial oparatlng range Rl = 2000. R2 = 3900.
For military oparating range Rl

=3000. R2 =6000.

2. Input pulse amplitude 0 V to 3.0 V.
:j. Input rise and fall times 2-5 ns from 0.8 V to 2.0 V.

4. Input access measured at the 1.5 V level.
5. Data delay is tesled with switch 51 closed. CL = 30 pF and measured at 1.5 V outpullevel.
6. tEA is measured at the 1.5 V output level with CL = 30 pF. 51 is open for high impedance to "1" lesl and closed for high
impedance 10 "11' test.

IER is measured wilh CL =5 pF. 51 is opan for "1" to high impedance lesl, measured al VOH -0.5 V oulpul level; 51 is closed for "11' to
high impedance test measured al VOL + 0.5 V oUlpul level.

Schematic of Inputs and Outputs
EQUIVALENT OUTPUT

vcco-_E~Q~U~IV~A~L~EN~T~IN_P~U~T_

Vcc

INPUT 0-......-1:"---11<1--1>-OUTPUT

3-90

MonoIIthIo

W Memories

53/83D1841
Die Configuration

A4

AI

AI
A1

AO

MODE

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give
a programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly calibrated.
Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine, ideally under the actual conditions of use. Each time a

MANUFACTURER
Data I/O

PROGRAMMER

TYPE
Unipack
Unipack2

Rev-V07
Rev-Vas·

new board or a new programming mOdule is inserted, the
whole system should be checked. Both timing and voltage
must meet published specifications for the device.

Remember - The best PROMs available can be made unreliable by improper programming techniques.

PROGRAMMING
MODULE

SOCKET
CONFIGURATION.

Family Code 82

Pinout Code 80

3·91

4096x4 Diagnostic
Registered PROM

53DA1643
63DA1643

Output Initialization

Patent Pend.

Features/Benefits

Ordering Information

• Programmable asynchronous output initialization

MEMORY

• Provides system diagnostic testing with system
controllability and observability

PACKAGE
TEMP.

SIZE I

ORG.

• Shadow register eliminates shifting hazards

Mil
16K

• Edge-triggered "0" registers simplifies system timing

4096x4

i---

Com

• Cascadable for wide control words used in
microprogramming

PART NO.
TYPE

PINS

NS,JS,W, 530A1643
(Nl),(L)
630A1643

24
(28)

The 53/630A1643 is a 4Kx4 PROM with registered outputs,
programmable asynchronous initialization, and a shadow register for diagnostic capabilities. Shadow register diagnostics
allow observation and control of the system without introduc-

ingintermE!diate illegal states. The output register, which can
receiveparalleJ data from either the PROM array or the shadow
reigister is loaded on the rising edge of ClK. The shadow register, which can receive parallel data from the output register or
serial data from SOl, is loaded on the rising edge of OClK.
During diagnostics, data loaded into the output register from
the PROM array can be parallel-loaded into the shadow register
and serially shifted out through SDO, allowing observation of
the system. Similarly, diagnostic data can be serially shifted
into the shadow register through SOl, and parallel-loaded into
the output register, allowing control and test scanning to be
imposed on. the system. Since the output register and the
shadow register are loaded by different input signals, they can
be operated independently of one another. In addition, diagnostic PROMs can be cascaded to construct wide control
words used in microprogramming. When exercised, the Initialization input loads the output register with a user-programmable
initialization word, independent of the state of ClK. This feature is a superset of preset and clear functions, and can be used
to generate an arbitrary microinstruction for system reset or
interrupt

Block Diagram

Pin Configurations

c

• 24-pin SKINNYOIP® saves space
• 24-mA output drive capability
• Replaces embedded diagnostic code

Applications
• Microprogram control store with built-In
system diagnostiC testing
• Serial character generator
• Serial code converter
• Parallel in/serial out memory
• Cost-effective board testing

Description

AS All A7 NCYOC All A9

4
~~------~~SDO

2 1282726

0

E1

A3

E2

A2

T

A1

MODE .......----...1

4096x4

QO

NC

1-------1
CLK------;

3

A4

Ne

01

MODE

02
12 13 14 15 16 17 18

OUTPUT
REGISTER

GND CLK
Q3
SDI
NC SDO

cDClJ(

03-00
SKINNYDIP"" is a registered trademark of Monolithic Memories

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

3·92

•_OlJoI'thiOfrrsn
.morles uun.u

53/63DA1643
Function Table
INPUTS

OUTPUTS
OPERATION

MOOE

SOl

ClK

OClK

Q3-QO

S3-SO

SOO

l

X

t

*

On- PROM

HOLD

S3

load output register from PROM array

l

X

*

t

HOLD

Sn - Sn-1
SO- SOl

S3

Sh ift shadow register data

l

X

t

t

an-PROM

Sn - Sn-1
SO- SOl

S3

load output register from PROM array
while shifting shadow register data

H

X

t

*

On- Sn

HOLD

SOl

load output register from shadow register

H

L

*

HOLD

Sn- an

SOl

load shadow register from output bus

H

H

*

t
t

HOLD

HOLD

SOl

No operationt

*

Clock must be steady or falling.

t

Reserved operation for SN54174S818 8-Bit Diagnostic Register.

Definition of Signals

MODE

SOl

SOO

The MODE pin controls the output register multiplexer and the shadow register. When MODE
is lOW, the output register receives data from
the PROM array and the shadow register is configured as a shift register with SOl as its input.
When MODE is HIGH, the output register receives
data from the shadow register. The shadow register is controlled by SOl as well as MODE. With
MODE HIGH and SOl lOW, the shadow register receives parallel data from the output register.
With MODE and SOl both HIGH, the shadow
register holds its present data.
The Serial Data In pin is the input to the least
significant bit of the shadow register when
operating in the shift mode. SOl is also a control
input to the shadow register when it is not in the
shift mode.
The Serial Data Out pin is the output from the
most significant bit of the shadow register when
operating in the shift mode. When the shadow
register is not in the shift mode, SOO displays the
logic level present at SOl. decreasing serial shift
time for cascaded diagnostic PROMs.

ClK

The clOCk pin loads the output register on the
rising edge of ClK.

OClK

The diagnostic clock pin loads or shifts the
shadow register on the riSing edge of OClK.

Q3-QO

an represents the data outputs of the output
register. During a shadow register load these
pins are the internal data inputs to the shadow
register.

S3-80

Sn represents the internal shadow register
outputs.

A11-AO

An represents the address inputs to the PROM
array.

T

The asynchronous output register initialization
input pin operates independent of ClK. When Tis
LOW, the output register is loaded with a user
programmable initialization word. Programmable
initialization is a super set of preset and clear
functions, and can be used to generate any
microinstruction for system reset or interrupt.

3·93

53/63DA1643
Logic Diagram

4096x4 Diagnostic PROM
with Asynchronous Initialization

A6

AS

4096x4
PROM

A3

03020100

A1

3·94

53/63DA1643
Absolute Maximum Ratings

Operating
Programming
Supply voltage VCC ............................................... " ............ -0.5 V to 7 V ...................... 12 V
Input voltage ................................................................... -1.5 V to 7 V ....................... 7 V
Input current ............................................................... -30 mA to +5 mA
Off-state output voltage ........................................................ -0.5 V to 5.5 V ...................... 12 V
Storage temperature .......................................................... -65° to +150°C

Operating Conditions
MILITARY
MIN TYPt MAX

PARAMETER

SYMBOL

COMMERCIAL
MIN TYPt MAX

UNIT

VCC

Supply voltage

4.5

5

5.5

4.75

5

5.25

V

TA

Operating free-air temperature

-55

25

125

0

25

75

°c

tw

Width of elK (HIGH or lOW)

25

10

20

10

ns

tsu

Set up time from address to ClK

45

25

40

25

ns

th

Hold time for ClK

0

-15

0

-15

ns

twd

Widt~of

45

15

40

15

ns

tsud

Set up time from control inputs (SOl, MODE) to ClK, OClK

50

20

45

20

ns

thd

Hold time for DClK

0

-5

0

-5

ns

tiw

Initialization pulse width (lOW)

25

10

20

10

ns

tir

Initialization recovery time

45

25

25

ns

C-'

DCLK (HIGH or lOW)

. - ~40

Electrical Characteristics Over Operating Conditions
SYMBOL

*

t

TEST CONDITION

PARAMETER

Vil

low-level input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

III

low-level input current

IIH

High-level input current

-

=MIN
Vee = MAX
Vee = MAX
Vee

MIN TYPt MAX

+,

= OAV

VI = Vee MAX
Mil IOl = 16 mA

Val

low-level output voltage

Vee = MIN

VOH

High-level output voltage

Vce

= MIN

lOS

Output short-circuit current*

Vee

= MAX

ICC

Supply current

Vee = MAX. All inputs TIL; all outputs open

eOM IOl = 24 mA
Mil IOH = -2 mA
COM IOH = -3,2 mA
Va = OV

0.8

V

-1,2

V

V

II = -18mA
VI

UNIT

-0.25

mA

40

IJA

0.5

V

V

2.4
-20
140

-90

rnA

190

rnA

Not more than one output should be shorted at a time and duration of the short-circuit should,not exceed one second.
Typical at 5.0 V Vee and 25 0 eTA

MonolithiaW Memories

3·95

53/63DA1643
Switching Characteristics
SYMBOL
tClK

t

Over Operating Conditions and Using Standard Test Load

PARAMETER

MILITARY
MIN Typt MAX

COMMERCIAL
MIN Typt MAX

11

25

11

23

40

ClK to output

UNIT

20

ns

35

ns

t lO

Initialization to output delay

fMAXD

Maximum diagnostic clock frequency

tDS

DClK to SDO delay (MODE

17

35

17

30

ns

tss

SDI to SDO delay (MODE

16

30

16

25

ns

tMS

MODE to SDO delay

14

30

14

25

ns

= lOW)
=HIGH)

7

18

23
10

18

MHz

Typical at5.0V VCCand 25'CTA'

Definition of Waveforms

Q

INITIALIZE OUTPUT REGISTER

LOAD OUTPUT REGISTER FROM PROM ARRAY

NORMAL PROM OPERATION (MODE = LOW)

3-96

53J'63DA1643
Definition of Waveforms

r

: ~--;.-II-.....--------.
f~_lhd-t
j'

I

'H

CLK

Q

I

~. ~d-+~
1

---;--~I-.L..-I-~dl·

DCLK

,I

\o~~_f_.

Fis1.------;~

1;1 r.;;f

I

SHIFT DATA INTO SHAOOW REGISTER

Iw=f°\

,

T

~~I----:-I- ' - - - - - - - - 1 .1
--

\\

-pI i f.....---;..~~~-----!...6---..,.---II;""-"':is

SOD

1

I

17s1
I

kJ

LOAD OUTPUT REGISTER
FROM SHADOW REGISTER

i (
~I

J

SYSTEM CONTROL

Q

SDO

LOAD OUTPUT
REGISTER FROM
PROM ARRAY

I

LOAD SHADOW
REGISTER FROM
OUTPUT REGISTER

SHIFT DATA OUT OF SHADOW REGISTER

SYSTEM OBSERVATION
3·97

53/63DA1643
Definition of Timing Diagram

Switching Test Load

WAVEFORM

INPUTS

~

DON'T CARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

B

NOTES: I. For commercial operating range RI

=

~

OUTPUTS

=2OOn, R2 =390n.
=6oon.

For military operating range RI 300n, R2
2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2-5 ns from 0.8 V to 2.0 V.
4. Input access measured at the 1.5 V level.
5. Data delay is tested with switch 8 1 closed. C L = 30 pF and measured at 1.5 V output level.

Schematic of Inputs and Outputs
EQUIVALENT INPUT

VCCO-~~~~~~~

EQUIVALENT OUTPUT

Vce

a--+-

INPUT O-..--E=--.......

OUTPUT

53/63DA1643
Die Configuration
A5

A6

A7

vee

A8

A9

A10

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give
a programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each timea new board
or a new programming module is inserted, the whole system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing - it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember - The best PROMs available can be madEl unreliablEl
by improPElr programming techniques.

MANUFACTURER
Data I/O

PROGRAMMER
TYPE
Unipack
Unipack2

Rev-Va?
Rev-VaS

III/IOnoIlthlc

PROGRAMMING
MODULE

SOCKET
CONFIGURATION

Family Code AA

Pinout Code 87

m

MemorIes

3·99

w
o
o

~

MONOLtTHICMEMORIES PROM PROGRAMMER REFERENCE CHART
Source and
Location

Data I/O
10525 Willows Rd. N.E.
Redmond, WA 98073

Kontron Electronics
630 Price Ave.
Redwood City, CA 94063

Slag Microsystems
528-5 Weddell Dr.
Sunnyvale, CA 94089

Dlgelee
586-1 Weddell Dr.
Sunnyvale, CA 94089

Varix
1210 E. Campbell Rd.
Richardson, TX 75081

Programmer
Model(s)

Model 19/29
Model 22

Model MPP-805

Model PPX
Model PP17

UP803

OMNI

MMI Generic Bipolar UniPak
Rev 07
PROM Personality
UniPak II Rev 05
Module
(Not all PROMs are
supported by earlier
UniPak revisions

[

FAM Mod. No. 12

MOD16

iCS'

Socket Adapter(s)
and Device Code

I

63080/81

F18 P02
Model22A Adapter 351 A-064

SA3

AMll0-2
Code 21

DA No.2 Pinout lA
Switch Pos. 0-7 (638080)
Switch Pos. 0-6 (638081)

638080
63S081

63S140/41

FDl POl
Model 22AAdapter 351A-064

SA4-2

AM130-2
Code 21

DA No.7 Pinout 1B
Switch Pos. 0-7 (63S14O)
Switch Pos. 0-6 (63S141)

63S140
63S141

63S240/41

F18 P03
Model22A Adapter 351A~

SA4-1

AM130-3
Code 21

DA No.4 Pinout 1D
Switch Pos. 2-15 (63S240)
Switch Pos. 2-14 (638241)

63S240
63S241

63S280/81

F18 P08
ModeI22AAdapter 351 A-064

t

t

t

63S280
63S281

638440/41

F18 P05
Model 22AAdapter 351 A~

SA4

AM140-2
Code 21

DA No.3 Pinout 1E
Switch Pos. 0-7 (63S44O)
Switch Pos. 0-6 (638441)

63$440
638441

638480/81

F18 P09
ModeI22AAdapter 351A-064

t

t

t

638480
638481

63RA481

F18 P65t
Model 22AAdapter 351A-D74

SA31-2

t

Pinout lHt
Switch Pos. 5-14

t

63DA441/42

FAA PAC
Adapter 351A-D73

t

t

t

t

638841

F18 P06
Model 22AAdapter 351A-D64

SA4-4

AM 140-3
Code 21

DA No. Pinout 1L
63S840
Switch Pos. 5-15 (638640) 638841
Switch Pos. 5-14 (638641)

63RS881

F18 P86
Model 22AAdapter 351 A-D74
(300 inil pkg)

t

t

DA No. 64t
Switch Pos. 0-12

a-

~

•,.
!
~
;'

t

Contact manufacturer for availability and_programming information.

-

------

fI'.
"~

I:

t
----

Iit
3
I.

II
•~
~

MONOLITHIC MEMORIES PROM PROGRAMMER REFERENCE CHART
Source and,
Location

Data I/O
Kontron Electronics
10525 Willows Rd. N:E." 630,Price Ave.
Redmond, WA 98073
Redwood City,CA 94063

Stag Mlcrosystems
528-5 Weddell Dr.
Sunnyvale, CA 94089

Dlgel8C>'c
<
586-1 Weddeli Dr.
Sunnyvale, CA 94089

Varix
1210 E. Campbell Rd.
Richardson, TX 75081

Programmer
Model(s)

Model 19/29
Model 22

Model PPX
Model PP17

UP803

OMNI
'

MMI Generlcilipolar UniPak
Revil7
PROM Personality
UniPak 11 Rev 05
Module
(Not all PROMs are
supported by earl ier
UniPak revisions)

Model MPP-805
M0D16

I

i-

FAM Mod. No. 12

o

CS'

t

i

DA No. 70t
Switch Pas. 4-12

63S1641

I'

AM 100-5
Code 21

t

63S1681

t

t

t

t

t

t

t

FAA P87
Adapter 351 A-Q73

t

t

t

t

63PL1681
63PS1681

F18 P21

SA5-4

AM 100-5
Code 21

t

t

6353281

F18 P63

Socket Adapler(s)
and Device Code
r-----'------_.--------~----.-----------~--_r------------_.----~----~--_T-------------

FAA PAD
Adapter 351A-Q73

t

t

63S1641

F18 P53
Model22A Adapter 351A-Q64

SA20

AM 120-6
Code 21

63S1681

F18 P21

SA5-4

63RA1681
63RS1681

F18 PA3

t

6301641

FB2 P80
Adapter 351A-Q73

6301643

63DA841

II
1!1
r
t

t

",

'

t

t

t

•f....
•C;.

t
_

Contact manu_facturer for avaHabtiity and-programming informatton.

I"
1iii
:J
:J

'
DA No. 64 Pinout 47
.. Switch f'()S' a~ __

~

_

_ _______

:::l

an

•:r
~

...•
...o
fA)

I

"

Qenerlc
NiCR PROM Family
5,/63XX-1
~..

53/63XX-2

,

F..tu..../ . .n.fila

Description

• From 2048-bIt to a192-blt memory
• a-bit wide for byte-ortented appllcallons

The 53163XX series generic PROM family offers a wide selection
of size and organizations. The S-bit wide PROMs range from
256xSto 1024xS in a wide selection of package sizes including the
space-saving SKINNYDlf'iII' 24-pin .300-inch wide package. All
PROMs have the same programming specifications all
'nga
Single generic programmer.

• 1""

for ltaltlfard performance
.,......... for enhanced performance
• ''''blilty-proven nichrome fusible linn
(qualified for MIL-M-38510)

The family features low input current PNP in9lllSrfldn.~lPl1ItmKy
clamping, three-state and open-collector
fuses store a logical high and are pr
Special on-chip circuitry and
ming tests which assure
ng yields and high

• PNP Inputa for low Input current
• Compatible pin conflguratlonl for upward expansion

reliability.
~
The 63 series is sp
ied r
ration over the commercial
temperature~~olta
e. The 53 series is specified for the

Application
• Microprogram store

m~~

• Microprocessor program store

• Look up table

• Character generator
• Random logic

• Code converter

Generic PROM Selection
MEMO~
SIZE
2K

4K

SK

~~
~~
'\>

PACKAGE

~...... ,':"io., :TION

\ ~\~
\)

PINS

TYPE

OC
TS

20

N,J

OC
TS

24 (2S)

OC
TS
OC
TS

5308-1
5309-1

N,J, JS·,
F, (l)

6340-1
6341-1, -2

5340-1
5341-1, -2

20

N,J

634S-1
6349-1, -2

5348-1
5349-1, -2

24

N,J,JS·,F

6380-1, -2
63S1-1, -2

5380-1,-2
5381-1, -2

* JS IS the .300 Inch Wide SKINNVDIP package.

SKINNVDlpe Is a registered trademark of Monolithic Memories

TWX: 910-338-2376
2175 Mlsllon College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

3.t02

MILITARY

6308-1
6309-1

512xS

1024xS

DEVICE TYPE
COMMERCIAL

53/63XX
Pin Configurations

5316308-1

5316309-1.

5316348-1
5316349-1, .2

Ell

5316380-1, -2
5316381-1, -2

53/63XX
Absolute Maximum Ratings
Supply voltage Vee ....................................................................................... -0.5 V to 7 V
Input voltage ............................................................................................. -1.5 V to 7 V
Off-state output voltage .................................................................................. -0.5 V to 5.5 V
Storage temperature ................................................................................. -65°eto+150oe

Operating Conditions
SYMBOL
Vee

MILITARY
MIN NOM MAX

PARAMETER
Supply voltage

4.5

Operating free-air temperature

-55

5

SYMBOL

PARAMETER

TEST CONDITIONS

Low-level input voltage

VIH

High-level input voltage
Input clamp voltage

Vce= MIN

II

IlL

Low-level input current

Vee = MAX

VI = 0..45 V

IIH

High-level input current

Vi '. ",4.5V(program pin)
Vee=MAX.
',' VI "'Vee MAX (Other pins)

VOL

Low-level output voltage

Vee,,1III11\i'

•. ~~.

'.

High-levelqulptlf"V0lf"91l

10ZL

~~ \\

') ;

.:\\.::::. \.>. . >.

Off-s\.a~.e··output
\,

10ZH

v

=Q.~\(

\,>

*

current

Vec = MAX

~

Open collector output current

lOS

Output short-circuit current*t Vee = 5 V

Vee = MAX

-1$I:I\lE9 .2\SERIES UNIT
MIN MAX

;~INM41(

= -18mA •.........

.........

'2

*

t

<

-0..25

MIL

V

-1.5

V

V

-0..25

mA

40.

40

p.A

0.5

0..5

V

10H = -2 mA
2.4

2.4

V

COM IOH = -3.2 mA
Va = 0..5 V

-10.0.

-40

p.A

VO=2.4V

10.0.

40.

p.A

VO=2.4V

10.0.

....

40
10.0

Va = 5.5 V
-20.

Vo= o.V

Vce= MAX
All inputs
'40., '41, '48, '49
grounded. All
Outputs open
'80, '81

W Memories

-20.

-90.

p.A
mA

155

MIL

155

175

COM

155

155

MIL

175

175

COM

175

170.

Three-state only.

Monolithic

-90
155

Not more than one output should be shorted at a time and duration of the short-circuit should not exc€!ed one second.

3·104

0.8
2

-1.5

'0.8, '0.9

Supply current

V

COM 10L = 16 mA

"\ ",vee = MIN
VIL = 0..8 V
VIH =2V

leEX

ICC

5.25

·f;1IL 10L = 12 mA

\,,'c. .'. VH4:,~\t

~~'o .,:;0::/\>\ *
,\"'\

5

,\\..'.::'6.8
\\

....

VIC

VOH

4.75
0

UNIT

. . •. . . . <:\.\~.~»>
.....

VIL

5.5
125

Chara~teristics Over Operating Conditions

Electrical

COMMERCIAL
MIN NOM MAX

mA

53/63XX

Switching Characteristics Over Commercial Operating Conditions
tAA (ns)
ADDRESS ACCESS TIME

tEA AND tER (ns)
ENABLE ACCESS TIME
RECOVERY TIME

MAX

MAX

6308-1, 6309-1

70

30

6340-1,6341-1

70

30

6341-2

55

30

6348-1, 6349-1

70

30

6349-2

55

30

DEVICE TYPE

6380-1,6381-1

90

40

6380-2

70

30

6381-2

55

30

80
80

~

I\\'~''>

70

80",":":\'«>

5380-1,5381-1

/,

5380-2
5381-2

<""',"\

//

I<~\\\

"

MAi'

; ,.",'\\»::>

5348-1,5349-1

JQ\\

600

\',

\

"

\/

R1 (n)

R2 (n)

375

750

C:, «\''40\ \ , "

5341-2

5349-2

300

RECOVER~\TIM_>\))

MAX

5340-1,5341-1

R2(n)

tEA AND tER (ns)~"\\:,~, t::'~>':(~"C~NDITIONS
ENABLE ACCESS JiME\ \
::~\{See standard test load)

tAA (ns)
ADDRESS ACCESS TIME

5308-1,5309-1

R1(n)

/<:(;,,:,~

Switching Characteristics Over Military Operating Conditions
DEVICE TYPE

CONDITIONS
(See standard test load)

"<,:\
';

\ \;.

\\1"25""""", "

40
40
40
40
40

\~O

40

70

40

'\~{\,::~)\

Monolithic

IFJJ] Memories

3-105

53/63XX
Typical Characteristics

53/6309
Typical ICC vs Temperature

Typical T AA vs Temperature

150

:I
140

I

:
:

130

I

ICC-rnA

-...... ~

120

:

r-

I

110

:

rVee = 5.5V

""-r---...

".J '-.....

Vee = 5.25V

I

f'-....

100

I
-55:
90
-15

-50

-25

25

50

15

100

-25

125

0

25

50

15

100

125

TA -AMBIENT TEMPERATURE-'e

TA -AMBIENT TEMPERATURE-'C

/'~

;'\S'~;~«;:O\

\~&3/6341
53/6349
~'\

o

"
\

Typic~'Jec: ;,5 1~iI!perature
,f

\'\

Typical T AA vs Temperature

\"

150

/" (\,!.. \. /1
I""'"'-"I-I"""""""'''''''''''''''-"'"T""-'''''---'--''---'''

80

140

I---H---I---+--+--+--+--+__--I

10

\l: ,::',::"'"

r
I

I

:
130

I

1

I

60

:

t'---.

+r-- t--

:

I

ICC-mA

120

110

I

1

I

i

40

-I
-25

25

I
-55:

15

100

125

20
-15

I/IIonoIlthh:

-50

-25

25

50

15

TA -AMBIENT TEMPERATURE-'e

TA -AMBIENT TEMPERATURE-'C

3·106

vcc±D

I

I
50

~

:

Vec - 5.25V

1

-55 1

±v//'"

V

30

_:T

I
-50

,Vee = 5.5V_

t-- t--

100

90
-15

-t---fL-- t--r-.-

lice

/'

W MemorIes

100

125

53/63XX
Typical Characteristics

53/6381

Typicallc:C vs Temperature

Typical T AA vs Temperature

160

80

:I

:I

150

140

70

I
I
I

I
I

t-r- __ -....

60

rVcc = 5.5V

ICC-mA

130

:

120

I
vcc

:

--

r-,...

= 5.25V...../

r---+
.~
I

1

40

........

I

': I,:\~'\
!/ 1:>.\[\, :>

I
30

I

I

-55].

-551

-50

~

vcc±sB

:

110

100
-75

V

:

-----......... r--...

.....
I> E':·

I

-25

25

50

75

100

20
-75

125

-SQ...

. 0 ' ..''':25

50

cOl!ecto_~ d~Vtc~s ~ecreai~)~:t-c~ approximately

'\~t!fi~hion

.'-

Switching Test Load

~25.··

II:,,',,":' 1:::<::/\

"

'. \
.," ~."
\'t()I.VEFORM

])([

75

100

. . T~';l\.iII~,~~ TEMPERATURE-'C

TA -AMBIENT TEMPERATURE-'C
NOTE: Typical characteristic curves are for three-state devices. Equivalent open
approximately 6 ns.

/

'---.. ~IVCC ±10%

125

10 rnA and increase in T AA

of Timing Diagram
INPUTS

OUTPUTS

DON'T CARE;
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

Definitiott:Of Waveforms

NOTES: 1. Input pulse amplJlude 0 V to 3.0 V
2. Input rise and faU times 2-5 ns from 1.0 V to 2.0 V.
3. Input access measured at the 1.5 V levet

4. tAA is tested with switch S1 closed, C1 :: 30 pF and measured at 1.5 V output level.
5. For open collector devices, TEA and TER are measured at the 1.5 V output level with S1 closed and CL :::: 30 pF.
6. For three-state devices, TEA is measured at the 1.5 V output level with CL :::: 30 pF. S'l is open for high-impedance to "1 ' test and
closed for high-impedance to "0" test
TER is tested with CL = 5 pF. 81 is open for "1" to high-impedance test, measured at VOH -0.5 output level; 81 is closed for "0" to
high-impedance test measured at VOL +0.5 V output level

Monolithic

W Memories

3-107

53/63XX

Commercial Programmers
Monolithic Memories PROMs are designed and tested to give a
programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each time a new board
or a new programming module is inserted, the whole system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing - it must be qualitycontrolled. 'Equipment must be calibrated as a regular routine,

Remember - The best PROMs available cari be made
unreliable by Improper programming techniques.

PROM PROGRAMMfNG EQUIPMENT INFORMATION
SOURCE AND LOCATION

3-108

Data I/O Corp.
10525 Willows Rd. N.E.
Redmond, WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
Sunnyvale, CA 94089

Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94089

MONOLITHIC MEMORIES PROM PROGRAMMER REFERENCE CHART

II

~

•i,
!

Source and
LOcation

Data I/O
10525 Willows Rd. N.E.
Redmond, WA 98073

Kontron Electronics
630 Price Ave.
Redwood City, CA 94063

Sleg Mlcrosystems
528-5 Weddell Dr.
Sunnyvale, CA 94089

Dlgelec
586-1 Weddell Dr.
Sunnyvale, CA 94089

Varix
1210 E. Campbell Rd~
Richardson, TX 75081

Programmer
Model(s)

Model 19/29
Model 22

Model MPP-805

Model PPX
Model PP17

UP803

OMNI

MMI Generic Bipolar UniPak
Rev 07
PROM Personality
UniPak" Rev 05
Module
(All NiCr PROMs
should be programmed
on these or later
revisions)

MOD4

I

::a

o

,.

II

6308/09

FD1 P08
ModeI22AAdapter 351A-{)64

SA6-1

AM120-2
Code 20

DA No. 27 Pinout 28
Switch Pos. 5-1S (6308)
Switch Pos. 5-14 (6309)

6308
6309

6340/41

FD1 P15
Model 22AAdapter 351A-{)74
(300 mil pkg)

SAS-1

AM100-3
Code 20

DA No. 7Pinout 1J
Switch Pos. 4-13 (6340)
Switch Pos. 4-12 (6341)

6340
6341

6348149

FD1 P09
ModeI22AAdapter 531A-{)64

SA6

AM120-3
Code 20

DA No.4 Pinout 1Q
Switch Pos. 4-15 (6348)
Switch Pos. 4-14 (6349)

6348

FD1 P16
ModeI22AAdapter 351A-{)74
(300 mil pkg)

SAS

AM100-4
Code 20

DA NO.7 Pinout 1K
Switch Pos. 4-11 (6380)
Switch Pos. 4-10 (6381)

6380

6380/81

_.

iCS'

I,.

FAM Mod. No. 12

Socket Adapler(s)
and Device Code

III

f2.

-

--

----

-

-

-

-

i

i

I.

~

6349

;

in

6381

-

_.

w
o

:.

CD

l!

_.

--

--

~

•:I.

Notes

3-110

Table of Contents
PLE
Contents for Section 4 ................................
PLE to PROM Cross Reference Guide ..................
Selection Guide ......................................
PLE means Programmable Logic Element ...............
Registered PLE .......................................
PLEASM'· ............ ~ .. . . . .. .. .. .. . . . . .. . . .. .. . .. ..

4-2
4-2
4-3
4-4
4-4
4-5

Logic Diagrams ....•............................... 4-617
Specifications ........................................ 4-8
PLE Family Programming Instructions ...........•..•.. 4-14
PLE Family Programming Equipment Suppliers ......... 4-15
PLE Family Block Diagram ........................... 4-16
PLE Programmer Reference Chart ..................... 4-20

PLE to PROM Cross Reference
TEMP.
RANGE

Com.

PLE
NUMBER

INPUTS

OUTPUTS

OUTPUT
TYPE

PACKAGE

5

8

Three-State

32 x 8

63S081

16N,J,(20),(NL)

Pi...E5P8AC

5

8

Three-State

32x 8

63S081 A

16N,J,(20),(NL)

PLE8P4C

8

4

Three-State

256 x 4

63S141A

16N,J,(20),(NL)

PLE8P8C

8

8

Th ree-State

256 x 8

63S281A

20N,J,NL

PLE9P4C

9

4

Th ree-State

512 x 8

63S241A

16N,J,(20),(NL)

PLE9P8C

9

8

Three-State

512 x 8

63S481A

20N,J,NL

PLE10P4C

10

4

Three-State

1024 x 4

63S841A

18N,J,(20),(NL)

PLE10P8C

10

8

Three-State

1024 x 8

63S1881A

24NS,JS,(28),(NL)

PLE11P4C

11

4

Three-State

2048 x 4

63S841A

18N,J,(28),(NL)

PLE11P8C

11

8

Three-State

2048 x 8

63S1681A

24N,J,NS,JS,(28),(NL)

PLE12P4C

12

4

Three-State

4096 x 4

63S1641A

20N,J,(28),(NL)

PLE12P8C

12

8

Th ree-State

4096 x 8

63S3281A

24N,J,(28),(NL)

PLE9R8C

9

8

Register

512 x 8

63RA481A

24NS,JS,(28),(NL)

PLE10R8C

10

8

Register

1024 x 8

63RS881A

24NS,JS,(28),(NL)

PLE11RA8C

11

8

Register

2048 x 8

63RA1681A

24NS,JS,(28),(NL)

PLE11RSsC

2048 x 8

63RS1681A

24NS,JS,(28),(NL)

53S081

16J,F,W,(20),(L)

11

8

Register

PLE5P8M

5

8

Three-State

32 x 8

PLE8P4M

8

4

Three-State

256 x4

53S141A

16J,F,W,(20),(L)

PLE8P8M

8

8

Three-State

256 x 8

53S281A

20J,W,L

PLE9P4M

9

4

Three-State

512 x 4

53S241A

16J,F,W,(20),(L)

PLE9P8M

9

8

Three-State

512 x 8

53S481A

20J,L*

PLE10P4M

10

4

Th ree-State

1024 x 4

53S441A

18J,F,W,(20).(L)

PLE11P4M

11

4

Th ree-State

2048 x 4

53S841A

18J,F,W,(28),(L)

PLE11P8M

11

8

Three-State

2048 x 8

53S1681A

24JS,J,W,(28),(L)

PLE12P4M

12

4

Three-State

4096 x 4

53S1641A

20J

PLE12P8M

12

8

Three-State

4096 x 8

53S3281A

24J,W,(28),(L)

PLE9R8M

9

8

Register

512 x 8

53RA481A

24JS,(28),(L)*

PLE10R8M

10

8

Register

1024 x 8

53RS881A

24JS,W,(28),(L)

PLE11RA8M

11

8

Register

2048 x 8

'53RA1681A

24JS,W,(28),(L)

PLE11RS8M

11

8

Register

2048 x 8

53RS1681A

24JS,W,(28),(L)

Contact Factory for Flat Pack.

4-2

PROM
NUMBER

PLESP8C

Mil.

'*

MEMORY
SIZE

lIIIonoIithic

m

Memories

Programmable Logic Element
PLETM Family

Ordering Information

Features/ Benefits
• Programmable replacement for conventional TTL logic

PlESP8 A C N SHRP

• Reduces IC inventories and simplifies their control
• Expedites and simplifies prototyplng and board layout
• Saves space with .3 inch SKINNYDIP® packages
• Programmed on standard PROM programmers
• Test and simulation made simple with PLEASM software
• Low-current PNP inputs
• Three-state outputs
• Reliable Ti-W fuses guarantee >98% programming yield

J

JJ

PR.OGRAMMABLE
LOGIC
ELEMENT
NUMBER OF INPUTS
OUTPUT TYPE
P

[LOPTIONAL PROCESSING
SHRP ~ Reliability
Enhanced
883B ~ MiI·Std·883
Method 5004

~ Non registered

~~e~~5

R ~ Registered
RA ~ Registered
.synchronous
enable
RS ~ Registered
synchrol'!ous
enable
NUMBER OF OUTPUTS
PERFORMANCE-----'
Blank ~ Standard
A;:;; Enhanced

PACKAGE
N = Plastic dip
NS ~ SKINNYDIP plastic
J :: Ceramic dip
JS ~ SKINNYDIP ceramic
F :: Flat Pack
l :;:;: Leadless chip carrier
NL ~ Plastic leaded chip
carrier
W ~ Cerpak
"----TEMPERATURE RANGE
C=QC Cto+75°C

M ~ _55°C to • 125°.C

PLE Selection Guide
PART
NUMBER

*

PRODUCT
TERMS

OUTPUT
REGISTERS

tpD (ns)
MAX'

INPUTS

OUTPUTS

PLE5P8

5

8

32

PLE5P8A

5

8

32

15

PLE8P4

8

4

256

30

PLE8P8

8

8

256

28

25

PLE9P4

9

4

512

35

PLE9P8

9

8

512

30

PLE10P4

10

4

1024

35

PLE11P4

11

4

2048

35

PLE11P8

11

8

2048

35

PLE12P4

12

4

4096

35

PLE12P8

12

8

4096

PLE9R8

9

8

512

40
8

15

PLE10R8

10

8

1024

8

15

PLE11RA8

11

8

2048

8

15

PLE11RS8

11

8

2048

8

15

Clock to output time for registered outputs.

NOTE: Comr:nerciallimits specified.

PLFM is a trademark of MonoJlthic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

lIIonolithic.IIT!R
lIIemories U\U1U
4·3

,PLE FamUy
PLE means Programmable
Logic Element

Registered PLEa

Joining the world of IdeaLogic'" is a new generation of highspeed PROMs which the designer can use as Programmable
Logic Elements. The combination of PLEs as logic elements with
PALs can greatly enhance system speed while providing almost
unlimited design freedom.
Basically, PLEs are ideal when a large number of product terms
is required. On the other hand, a PAlls best suited for situations
when many inputs are needed.
The PLEtransferfunction is the familiar OR of products. Like the
PAL, the PLE has a Single array of fusible links. Unlike the PAL.
the PLEcircuits have a programmable OR array driven by afixed
AND array (the PAL is a programmed AND array driving a fixed
OR array).
PRODUCT TERM AND INPUT LINES
PLE

Product Terms
Input Lines

PAL

32 to 4096

2 to 16

5t012

10to20

The PLE family features common electrical parameters and
programming algorithm, low-current PNP inputs, full Schottky
clamping and three-state outputs.
The entire PLE family is programmed on conventional PROM
programmers with the appropriate personality cards and socket
adapters.

The registered PLEs have oil-chip "0" type registers, versatile
output enable control through synchronous and asynchronous
enable inputs, and flexible start-up sequencing through programmable initialization.
Data is transferred into the output registers ~ the rising edge of
the clock. Provided that the asynchronous (E) and synchronous
(ES) enables are Low, the data will appear at the outputs. Prior to
the positive clock,edge, register data are not affected by changes
in addressing or synchronous enable inputs.
Data control is made flexible with synchronous and asynchronous enable inputs, Outputs may be set to the high-Impedance
state at any time by setting E to a High or ifES is High when the
rising clock edge occurs. When Vee power is first applied the
synchronous enable flip-flop will be In the set condition causing
the outputs to be in the high-Impedance state.
A flexible initialization feature allows start~up and time-out
sequencing with 1:16 programmable words to be loaded into the
output registers. With the synchronous INITIALIZE (IS) pin Low,
one ofthe 16 initialize words, addressed through pins 5,6,7 and 8
will be set in the output registers Independent of all other input
pins. The unprogremmed state of is words are Low, presenting
a CLEAR with is pin Low. With all is column words (A3-AO)
programmed to the same pattern, the is function will be
independent of both row and column addressing and may be
used asa single pin control. With all is words programmed High
a PRESET function is performed.
The PLE9R8 has asynchronous PRESET and CLEAR functions.
With the chip enabled, a Low,on the PR input will cause all
outputs to be set to the High state. When the CLR input is set
Low the output registers are reset and all outputs will be set to
the Low state. The PR and CLR functions are common to all
output registers and independent of all other data input states.

AND

OR

OUTPUT OPTIONS

PLE

Fixed

Prog

TS, Registered Outputs,
Fusible Polarity

FPLA

Prog

Prog

TS, OC, Fusible Polarity

FPGA

Prog

Prog

TS, OC, Fusible Polarity

FPLS

Prog

Prog

TS, Registered Feedback I/O

PAL

Prog

Fixed

TS, Registered Feedback I/O
Fusible Polarity

PLE Family
PLEASMTI.
Software that makes programmable logic easy.
Monolithic Memories has developed a software tool to assist in
designing and programming PROMs as PLEs. This package
called "PLEASM" (PLE Assembler) is available for several
computers including the VAXNMS and IBM PC/DOS. PLEASM

convertS design equation (Boolean and arith-metic)' into truth
tables and fonnats compatible with PROM programmers. A
simulator is also provided to test a design using a Function Table
before actually programming the PLE.
PLEASM may be requested through the Monolithic Memories
IdeaLogic Exchange.

PAL

PLE (PROM)

n INPUTS

13

'I

,

12

V IV

INPUTS

10

11

V

7 '

V

13'
·OR" ARRAY
(PROGRAMMABLE),

-

V-

12

11

IV

V

,

10

'I

"OR"ARRAY
FIXED

7

~

i'"""\

---'
i'"""\

~
~

l=<
l=<

~

K
F<

~

l=<

1,.,../

l=<

r=-.

P=<

r=<

I==:

f=<

~

~
~
~

~

F<
K

r=<
r=<
r=<
L-I
"AND" ARRAY
FIXED

F=<

~

~

9V99

"

"AND" ARRAY
(PROGRAMMABLE)

9999
03 02,' 01 00

03 02 01 00

Note: • = Hardwired 'connection
X = Programmable fuse with a diode

4·5

PLEFamily
Logic Symbols

PLESPS
PLE5PS/A

PLESP4

PLE9P4

PLE10PS

PLE9P8
PLE10P4

4·6

IIIIonoIlthlcW Memories

PLE11P4

PLEFamlly
Logic Symbols

PLE11P8

PLE12P8

PLE12P4

PLE9R8

PLE10R8

PLE11RAS

PLE11RSS

4-7

PLE Family
Absolute Maximum Ratings

Operating
Programming
Supply voltage vee .............................................•............... -0.5 V to 7 V ..............•....... 12 V
Input voltage ..............................•.................................... -1.5 V to 7 V .........•............. 7 V
Off-state output voltage ........................................................ -0.5 V to 5.5 V ...................... 12 V
Storage temperature. '; ..... " ................................................. -650 to +1500e

Operating Conditions

I

COMMERCIAL
MIN NOM MAX

MIN NOM MAX

Vee

Supply voltage

4.75

5

5.25

4.5

5

5.5

TA

Operating free-air temperature

0

25

75

-55

25

1251

SYMpOL

PARAMETER

MILITARY

UNIT

I

V
°e

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

TEST CONDITION

UNIT

VIL

Low-Ieval input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

11= -lS mA

-O.S

IlL

Low-level input current

Vee = MAX

VI = 0.4 V

-0.02 -0.25

mA

IIH

High-level input current

Vee = MAX

VI = Vee

40

p.A

O.S
2.0

VOL

Low-level output voltage

Vee = MIN

VOH

High-level output voltage

Vee = MIN

Off-state output current

Vee = MAX

Output short-circuit current"

Vee = 5 V

10ZL

10L = 16 mA

lOS

eom 10H = -3.2 mA

Supply current

All inputs TTL;
all outputs open

Monolithic

eom

0.3

.45

Mil

0.3

0.5

2.4

2.9

V

V

V
-40

VO=2.4V

40
-50

-90

5PS

90

125

5PSA

90

125

SP4

SO

130

SPS

90

140

9P4

90

130

9PS

104

155

10P4

95

140

llP4

110

150

-20

lS5

l1PS

135

12P4

130

175

12PS

150

190

9RS

130

lS0

10RS

130

lS0

llRAS

140

lS5

llRSS

140

lS5

TYPical at 5,0 V Vee and 25 0 eTA-

4·8

-1.5

Vo = 0.4 V

Vo = OV

Vee = MAX
lee

I
I

V
V

Mil 10H = -2 mA

10ZH

.

MIN TYP* MAX

W ••mQrles

p.A
mA

mA

PLE Family
Switching Characteristics Over Military Operating Conditions

MAX

tpzx AND tpxz (nl)
iNPUT TO OUTPUT
ENABLE/DISABLE TIME
MAX

15

20
20

tPD (ns)
PROPAGATION DELAY

DEVICE TYPE

5P8AC
5P8C

25

8P4C

30

20

8P8C

28

25

9P4C

35

20

9P8C

30

25

10P4C

35

25

11P4C

35

25

11P8C

35

12P4C

35

12P8C

..

40

25
...

25
30

Switching Characteristics Over COmmercial Operating COnditions
DEVICE TYPE

MAX

tpzx AND tpxz (nl)
INPUT TO OUTPUT
ENABLE/DISABLE TIME
MAX

tpD (nl)
PROPAGATION DELAY

5P8M

35

30

8P4M

40

30

8P8M

40

30

9P4M

45

30

9P8M

40

30

10P4M

50

30

11P4M

50

30

11P8M

50

30

12P4M

50

30

12P8M

50

35

MonoIHhlcm Memories

4·9

PLE9R8
Operating Conditions
SYMBOL

PARAMETER

COMMERCIAL
MIN TYP* MAX

MiliTARY
MIN TYP* MAX

UNIT

tw

Width of clock (High or low)

20

10

20

10

ns

tprw

Width of preset or clear
(low) to Output (High or low)

20

10

20

10

ns

Recovery from preset or clear
(low) to clock High

20

11

25

11

ns

tsu

Setup time from input to clock

30

22

35

22

ns

ts(ES)

Setup time from ES to clock

10

7

15

7

ns

th

Hold time from inputtoclock

0

~5

0

-5

ns

th (ES)

Hold time from ES to clock

5

-3

5

-3

ns

MiliTARY
MIN TYP* MAX

UNIT

tclrw
tprr
tclrr

Switching Characteristics Over Operating Conditions and using Standard Test load
SYMBOL

PARAMETER

COMMERCIAL
MIN TYP* MAX

tClK

Clock to output delay

11

15

20

ns

tpR

Preset to output delay

15

25

11
15

25

ns

tClR

Clear to output delay

18

25

18

35

ns

tpzx (ClK)

Clock to output enable time

14

25

14

30

ns

tpxz (ClK)

Clock to output disable time

14

25

14

30

ns

tpzx

Input to output enable time

10

20

10

25

ns

tpxz

Input to output disable time

10

20

10

25

ns

• Typical at s.o V VCC and 2SoC T A .

4·10

Monolithic

W Memories

PLE 9R8
Definition of Waveforms

Input------------.;("j'l...--------

Fl-r--j- -

«:~

E-------!.~-----:-----1

t-

elK

a
VOL +0.5 V

NOTES: 1.

Input pulse amplitude

0 V 10 3.0 V.

2. Input rise and fall times 2·5 ns from 0.8 V to 2.0 V.
3. Input access measured at the 1.5 V level.
4. Switch 81 is closed. CL

=30 pF and outputs measured at 1.5 V level for all tests except tpxz and tpZX'

5. tpzx and tPZX(CLK) are measured at the 1.5 V output level with CL = 30 pF. 81 is open for high impedance to "1" test and closed for
high impedance to "0" test.
tpxz and tPXZ(CLK) are tested with CL = 5 pF. 81 is open for "1" to high impedance test, measured at VOH-C,S V output level;
81 is closed for "0" to high impedance test measured at VOL +0.5 V output level.

Monolithic

m

Memories

4·11

PLE 1 OR8;11 RA8, 11 RS8

Operating Conditions
SYMBOL

COMMERCIAL
MIN TYP* MAX

PARAMETER

MILITARY
MIN TYP*. MAX

UNIT

tw

Width of clock (High or Low)

20

10

20

10

ns

isu

Setup time from input to clock (10RS)

30

25

40

25

ns

isu

Setup time from input to clock (l1RAS, )1RSS)

35

28

40

28

os

is (ES)

Setup time from ES to clock

15

7

15

7

ns

is (is)

Setup time from IS to clock

25

20

30

20

ns

th

Hold time input to clock

0

-5

0

-5

ns

~(ES)

Hold time (ES)

5

-3

5

-3

ns

th (IS)

Hold time (is)

0

-5

0

-5

ns

COMMERCIAL
MIN TYP* MAX

MILITARY
MIN TYP* MAX

UNIT

,c

Switching Characteristics Over Operating Conditions and using Standard Telt Load
SYMBOL

*

PARAMETER

tClK

Clock to output delay

10

15

10

20

ns

tpzx (ClK)

Clock to output enable time

17

25

17

30

ns

17

30

ns

tpxz (ClK)

Clock to output disable time

17

25

tpzx

Input to output enable time

17

25

17

30

ns

tpxz

Input to output disable time

17

25

17

30

ns

Typical at 5.0 V V CC and 25° C T A"

Definition of Waveforms

Input---------;:--IJ.--Lrn______
I

1?1
.
I

!

!

/.!~~tJ~1

il

-----L-f'"."

.".i" +

j

CLK

!_tpxz-!

I-tpzx-!

~~--~---~I,-~--~~-VOH-O~V
Q

- - - - - - - / I ' - - - - - £ . . ) -....
t++-:o~~~y----1~~~_ _ _ _ _ _....III-----'-.... -VOL _O.SV

NOTES: 1. Input pulse amplitude 0 Vlo 3.0 V.
2. Input rise and fall times 2-5 ns from 0.8 V

to 2.0 V.

3. Input access measured at the 1.5 V level.
4. Switch 51 is closed. CL = 30 pF and outputs measured at 1.5 V level for all tests except tpzx and tpXZ'
5. tpzxand tPZX(CLK) are measured at the 1.5 V output level with CL
high impedance to "0" test.

=30 pF. 5, is open for high impedance to .. , .. test and closed lor

tpxz and tPXZ(CLK) are tested with CL =5 pF. 51 is open for .. , .. to high impedance lest. measured at VOWO.5 V output levet:
$1 is closed for ''0'' to high impedance test measured at VOL +0.5 V output level.

4·12

MonolIthic

W ..""".,..

PLE Family
Definition of Timing Diagram

SWitching Test Load

;:1

:ri

OUTPUTS

WAVEFORM

INPUTS

~

OONTCARE;
CHANGE PERMITTEO

CHANGING;
STATE UNKNOWN

1t1 ~

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

R1

OUTPUT

.

CL

~

R2

-::-

Definition of Waveforms

:,

o~~===t"-----{~>k'oo-~'
t.::L
~""""'---------------'-'-"-~-~
VOL +0.5 V

NOTES;

Apply to electrical and switching characteristics
Typical at 5.0 V Vee and 25' eTA.

Measurements are absolute voltages with respect to the ground pin on the device and includes all overshoots due to system and/or tester noise.
In all PLE devices unused inputs must be tied to either ground orVCC. Theseries resistor required for unused inputs on standard TTL is"NOT required for
PLE devices, thus using less parts.
*Not more than on output should be shorted at a time and duration of the short-circuit should not exceed one second.
1. For commercial operating range R1 ~ 2000. R2 = 3900. For military operating range Rl
2. Input pulse amplitude 0 V to 3.0 V.

= 300!}, R2 = 600n.

3. Input rise and fall times 2-5 ns from 0.8 to 2.0 V.
4. Input access measured at the 1.5 V level.
5. Data delay is tested with switch 81 closed. CL

= 30 pF and measured at 1.5 V output level.

6. tpzx is measured at the 1.5 V output level with CL = 30 pF. 81 is open for high-impedance to "1" test and closed for high-impedance to "0" test.
tpxz is measured CL = 5 pF. 81 is open for "1" to high-impedance test, measured at VOH-O.5 V output level: 81 is closed for "0" to high-impedance
test measured at VOL + 0.5 V output level.

MonolIthIc

W MemorIes

4·13

PLETM Family
Programming Instructions
Device Description
All of the members Of the PLE family are manufactured with all
outputs LOW in all storage locations. To produce a HIGH at a
particular word, a Titanium-Tungsten Fusible-Link must be
changed from a low resistance to a high resistance. This procedure is called programming.

1.
2.
3.
4.
5.

Select the appropriate address with chip disabled
Increase VCC to programming voltage
Increase appropriate output voltage to programming voltage
Enable chip for programming pulse width
Decrease VOUT and VCC to normal levels

Programming Timing
Programming Description
To program a particular bit normal TTL levels are applied to all
inputs. Programming occurs when:
1. VCC is raised to an elevated level.
2. The output to be programmed is raised to an elevated level.
3. The device is enabled.
In order to avoid misprogramming the PLE only one output at a
time is to be programmed. Outputs not being programmed
should be connected to VCC via 5 KO resistors.
Unless specified, Inputs should be at VIL.

In order to insure the proper sequence, a delay of 100 ns or
greater must be allowed between steps. The enabling pulse
must not occur less than lOOns after the output voltage reaches
programming level. The rise time of the voltage on VCC and the
output must be between 1 and 10 Vips.

Verification
After each programming pulse verification of the programmed
bit should be made with both low and high Vcc. The loading of
the output is not critical and any loading within the DC specifications of the part is satisfactory.

Programming Sequence

Additional Pulses

The sequence of programming conditions is critical and must
occur in the following order:

Up to 10 programming pulses should be applied until verification indicates that the bit has programmed. Following verification, apply fiVe additional programming pulses to the bit being
programmed.

Programming Parameters Do not test these parameters or you may program the device
SYMBOL

PARAMETER

MIN

RECOMMENDED
VALUE

MAX

UNIT

VCCP

Required Vce for programming

11.5

11.75

12.0

VOP

Required output voltage for programming

10.5

11.0

1U

V

tR

Rise time of VCC or VOUT

1.0

5.0

10.0

VipS

ICCp

Current limit of Vccp supply

800

1200

lOp

Current limit of Vop supply

15

20

tpw

Programming pulse width (enabled)

9

10

11

pS

VCC

Low VCC for verification

4.2

4.3

4.4

V

VCC

High VCC for verification

5.8

6.0

6.2

V

25

25

120

MDC

Maximum duty cycle of Vccp

to

Delay time between programming steps

100

VIL

Input low level

0

VIH

Input high level

2.4

PLET " is a trademark of Monolithic Memories.

4·14

IIIIonoIlthle

W Memories

V

mA
mA

%

ns

a

0.5

V

3.0

5.5

V

PLE Family

Programming Equipment Suppliers
Monolithic Memories PLEs are designed and tested to give a
programming yield greater than 98%. If your programming
yield is lower, check your programmer. It may not be properly
calibrated.

ideally under the actual conditions of use. Each timea new board
or a new programming module is inserted, the whole system
should be checked. Both timing and voltages must meet
published specifications for the device.

Programming is final manufacturing- it must be qualitycontrolled. Equipment must be calibrated as a regular routine,

Remember - The best PLEs available can be made unreliable by Improper programming techniques.

SOURCE AND LOCATION

Data 1/0 Gorp.
10525 Willows Rd. N.E.
Redmond, WA 98073

Digelec Inc.
586 Weddell Dr. Suite 1
Sunnyvale, CA 94089

Kontron Electronics, Inc.
630 Price Ave.
Redwood City, CA 94063

Varix Gorp.
1210 E. Campbell Rd. Suite 100
Richardson, TX' 75081

Monolith/O

m

illemories

lID

4·15

PLE Family
Block Diagrams
PLESP4

PLE5PS/A

AO
A1
A2
A3
A4

10
11

A7 15
A6 1
A5 2
A4 3
A3 4

32< 8
PROGRAMMABLE
ARRAY

1 OF 32
12
13 DECODER
14

1 OF 32
ROW
DECODER

32X32
PROGRAMMABLE
ARRAY

E 15
A2 7
A1 6
AO 5

1 OF S
COLUMN
DECODER

PLESP8

A7
A6
A5
A1

19
18
17

PLE9P4

AS14
A7 15
A6 1
A5 2
A4 3

32X64
PROGRAMMABLE
ARRAY

1 OF 32
ROW
DECODER

AO

A4
A3
A2

4

A3

4

A27
A1 6

E1

AO

Eli

10F32
ROW
DECODER

1 OF 16
COLUMN
DECODER

5

_13
E
01

4·16

02

03

04

05

06

07

08

IWonoIIthIc

W Memories

32X64
PROGRAMMABLE
ARRAY

PLE Family
·Block Diagrams
PLE9P8

PLE10P4

.A8 19
A7 18
17
A6
16
A5
2
A1
1
AO

A4

1 OF 64
ROW
DECODER

64X64
PROGRAMMABLE
ARRAY

1 OF 64
ROW
DECODER

5

4
A3
3
A2

10F8
COLUMN
DECODER

A3 4

A27
A1 6

E

10F16
COLUMN
DECODER

AO 5

15

PLE11P4

PLE10P8

AS· 22·
A8 23
1
A7

2
3
AS
4
A4
A6

A3

A2
A1

AO

64X64
PROGRAMMABLE
ARRAY

5
6

1 OF 64
ROW
DECODER

128 x 64
PROGRAMMABLE
ARRAY

A9 15
A8 16
A717
A6 1
A5 2

1 OF 64
ROW
DECODER

64 X 128
PROGRAMMABLE
ARRAY

A4

A1e) 8
A3

4

A2 7
A1

6

10F32
COLUMN
DECOD.,R

AO 5

~ 10

4·17

PLE Family
Block Diagrams
PLE12P4

PLE11P8

Al0

21

A9

22

AS 23

128.128
PROGRAMMABLE
ARRAY

A7
A6

All 17
Al0 18
A9 19

2

A8 1
A7 2

AS
A4

A3
A2
Al
AO

A6
A5

4

6
7

8

1 OF 16
COLUMN
DECODER

!

128 X 128
PROGRAMMABLE
ARRAY

1 OF 128
ROW
DECODER

A4
A3 6
7

A2

E1

Al

E2
E3

AO

1 OF 32
COLUMN
DECODER

01

PLE12P8

All 19
Al0 21
A9 22
A8 23
A7
A6

1 OF 128
ROW
DECODER

128.256
PROGRAMMABLE
ARRAY

2

A5

A4
A3
A2

4
5
6

Al

AO

01

4-18

Monolithic

W Memories

02

03

04

PLE Family
Block Diagrams
PLE9R8

A8 23
1
A7
A6
AS

PLE10R8

A9
1 OF 32
ROW
DECODER

A8

32 X 128
PROGRAMMABLE
ARRAY

A7
AS
AS

A4

22
23
2
3

64 X 128
PROGRAMMABLE
ARRAY

1 OF 64
ROW
DECODER

A3
6

A2
Al

7

AD

8

1 OF 16
COLUMN
DECODER

A3
A2
Al
AD

B-BIT EDGE-TRIGGERED
REGISTER

Es
E

E 21
01

PLE11RS8

PLE11RAS

A1D
A9
A8
A7
A6
AS
A4

-is

21
22

23
2
3
4

Al0
1 OF 128
ROW
DECODER

~
23

128.128
PROGRAMMABLE
ARRAY

1 OF 128

128 X 128
PROGRAMMABLE
ARRAY

20

A3
A2
Al
AO

01

02

03

04

07

08

-is selects 1:16 programmable initialization words.

MonolIthic WIIII.morla$

4-19

••

MONOLITHIC MEMORIES PLE PROGRAMMER REFERENCE CHART

tI)

Source and
Location

o

Programmer
Model(st
MMI Generic Bipolar
PLE Personality
Module

I

Socket Adapter(s)
and Device Code
PLE5PSI
PLE5PSA
PLE8P4

f2.

PLE9P4

i

PLESPS

~

PLE10P4

a'

f!

~
;.

I

PLE9PS

PLE9R8

til

PLEllP4

PLE10RS

PLE12P4

PLEllRA8
PLEllRS8
PLEllP8
PLE12PS
--------

t

---------

Data 1/0
10525 Willows Rd. N.E.
Redmond, WA 9S073
Model 19/29
Model 22
UniPak Rev 07
UniPak II Rev 05
(Not all PLEs are
supported by earlier
UniPak revisions

Kontron Electronics
630 Price Ave.
Redwood City, CA 94063
Model MPP-805

Stag Microsystems
52S-5 Weddell Dr.
Sunnyvale, CA 940S9
Model PPX
Model PP17

MOD4

Digelec
5S6-1 Weddell Dr.
Sunnyvale, CA 940S9
UP803

Varix

1210 E. Campbell Rd.
Richatdson, TX 750S1
OMNI

FAM Mod. No. 12

I:
o

§.
::;:

F1B P02
Model 22AAdapter 351 A-064
F18 POI
Model 22AAdapter 3.51 A-064
F18 P03
Model 22AAdapter 351 A-064
F18 P08
Model 22AAdapter 351A-064
F18 P05
Model 22AAdapter 351A-064
F18 P08
Model 22AAdapter 351A-G64
F18 P65t
Model 22AAdapter 351A-074
F18 P06
Model 22AAdapter 351 A-064
F18 P86t
Model 22AAdapter 351A-074
(300 mil pkg)
F18 P53
Model 22AAdapter 351A-064
F18 PA3

AMll0-2
Code 21

SA3

SA4-2

DA No.2 Pinout 1A
Switch Pos. 0-6

63S081

AM130-2
Code 21

DA No.2 Pinout 1B
Switch Pos. 0-6

63S141

SA4-1

AM130-3
Code 21

DA No.1 Pinout 10
Switch Pos. 2-14

63S241

t

t

t

63S280
63S281

SA4

AM140-2
Code 21

DA No.3 Pinout 1E
Switch Pos. 0-6

63S441

t

t

t

63S480
63S481

SA31-2

t

Pinout lH t
Switch Pos. 5-14

t

SA4-4

AM140-3
Code 21

DA No. Pinout 1 L
Switch 5-14

63S841

t

DA No. 64 t
Switch Pes. 0-12

t

SA20

AM120-6
Code 21

DA No. t
Switch Pos. 4-12

63S1641

t

t

t

t .

F18P21

SA5-4

AM100-5
Code 21

t

63S1681

F18P63

t

L -_ _ _ _ _ _ _ _ _ _ _ _ _

Contact manufacturer for availability and programming information.

::r

(i'

I:
CD

..
:i

o

i'

".-m
.i"
iii

:i

I

f§
()

t
---

-

---

--

- - -----

DA No. 64 Pinout 47
t
,---,switch Pos. 0-4____ L.._

;

::1.

'"

c

'

, ' c " c

~

"'

,

'Cc

,

PAL®/HAL® Circuits

"

"'"

,

"

"

,

2

,\)" "

~"'~

',"

,

~"',,

5·1

EI
B

Table of Contents
PAL®/HAL® CIRCUITS
Contents for Section 5 ................................ 5-2
The PAL IntroductionlThe PAL Concept ................ 5-3
PAUHAl Description ..........•..................... 5-16
PAUHAl logic Symbols ............................. 5-21
10H8
Octal 10 Input And-Or-Gate Array .•.......... : 5-26
12H6
Hex 12 Input And-Or-Gate Array ....... , ..... ; 5-26
14H4
Quad 14 Input And-Or-Gate Array.. . . . . . . . . . . .. 5-26
16H2
Dual 16 Input And-Or-Gate Array ........•.... 5-26
16C1
16 Input And-Or-/And-Or-Invert Gate Array .... 5-26
1018
Octal 10 Input ~hd-Or-Invert Gate Array ...... , 5-26
1216
Hex 12 Input And-Or-Invert Gate Array ........ 5-26
14l4Quad 14 Input And-Or~lnvert Gate Array ....... 5-26
1612
Dual 16 Input And-Or-Invert Gate Array ........ 5-26
12110 Deca 12 Input And-Or-Invert Gate Array ....... 5-27
1418
Octal 14 Input And-Or-Invert Gate Array .; ..... 5-27
1616
Hex 16 Input Arid-Or-Invert Gate Array ........ 5-27
1814
Quad 18 Input And-Or-Invert Gate Array ....... 5-27
.20L2
Dual 20 Input And-Or-Invert Gate Array ........ 5-27
20C1
20 InputAnd-Or-/And-Or Invert Gate Array .... 5~27
1618
Octal 16 Input And-Or~lnvert Gate Array ....... 5-28
16R8
Octal 16 Input Registered And-Or-Gate Array ... 5-28
laR6
Hex 16 Input Registered And-Or-Gate Array .... 5-28
16R4
Quad 16 Input Registered And-Or-Gate Array .. 5-28
16X4
Quad 16 Input Registered
.
And-Or-Xor Gate Array ................. ,.. 5-28
16A4
Quad 16 Input Registered
. And-Carry-Or-Xor Gate Array .......... ,.... 5-28
20X10 Deca 20 Input Registered
And-Or-Xor Gate Array .................... 5-29
20X8· Octal 20 Input Registered
And-Or-Xor Gate Array .................... 5-29
20X4
Quad 20 Input Registered
And-Or-Xor Gate Array •................... 5-29
20110 Deca .20 Input And-Or-Invert Gate Array ....... 5-29
16l8A Octal 16 Input And-Or-Invert Gate Array ....... 5-30
16R8A Octal 16 Input Registered And-Or Gate Array ... 5-30
16R6A Hex 16 Input Registered And-Or Gate Array .... 5-30
16R4A Quad 16 Input Registered And-Or Gate Array ... 5-30
16P8A Octal 16 Input Registered
And-Or Invert Gate Array •.................. 5-30
16RP8A Octal 16 Input Registered And-Or Gate Array ... 5-30
16RP6A Hex 16 Irlput Registered And-Or Gate Array ... , 5-30
16RP4A Quad 16 Input Registered And-Or Gate Array ... 5-30
2Ol8A Octal 20 Input And-Or-lnvert Gate Array· .. . . . .. 5-31
20R8A Octal.20 Input Registered And-Or ............. 5-31
20R6A Hex 20 Input Registered AndcOr •......•....•. 5-31
20R4A Quad 20 Input Registered And-Or ............. 5-31
10H8-2 Octal 10 IhputArid-Or Gate Array ............. 5-3~
12H6-2 Hex 12 Input And-Or Gate Array .............. 5-32
14H4-2 QU\ld 14 Input And-Or Gate Array ....• :....... 5-32
.16H2-2 Dual 16 Input And-Or Gate Array ...•....... , .• 5-32
16C1-2 16 Input and-Or Invert Gate Array •............ 5-32
10LS-20cta110 Input And-Or-lmiertGate Array ...•... 5-32
12l6-2 . Hex 12 Input And~Or-lnvert Gate Array ...•.•.•. 5-32
14L4-2 Quad 14Inpu(And-Or-lnvert Gate Array ....... 5-32
16L2~2 Dual 16 Input And-Or-lnvertGilte Array. , ...... 5-32
16L8.A-2 Octal 16 Input And-Or-Invert Gate Array ....... 5-33
16R8A-20ctal16lnputRegistered
And-Or-Gate Array.. . . . . . . . . . . . . . • . . . . • ... 5-33
16R6A-2 Hex 16 Input Registered
. And-Or-Gate Array ..................... ;.. 5-33
16R4A-2Quad 16 Input Registered
And-Or-Gate Array ........................ 5-33
16l8A-4 Octal 16 Input And-Or-Invert Gate Array ....•.. 5-34
16R8A-40ctal16lnput Registered
And-Or-Gate Array ........................ 5-34

5-2

IIIIonoIIthIc

16R6A-4Hex 16 Input Registered
And-Or-Gate Array ........................
16R4A-4Quad 16 Input Registered
And-Or-Gate Array ........................
PAl20RA10 Deca 20 Input Registered
Asynchronous And-Or ..................
24RS Series .........................................
20S10 Deca 20 Input And-Or-Array
with product term sharing ..................
20RS10 Deca 20 Input Register And-Or Gate Array
with product term sharing ..................
20RS8 Octal 20 Input Register And-Or Gate Array
with product term sharing ..................
20RS4 Quad 20 Input Register And-Or Gate Array
with product term sharing ..................
32R16 1500 Gates. 32 Inputs. 16 Outputs .............
64R32 5000 Gates. 64 Inputs. 32 Outputs .............
PAUHAl Waveforms ................................
logic Diagrams
10H8 ...............................................
12H6 ................................................
14H4 ...............................................
16H2 ...............................................
16C1 ...............................................
1018 ...............................................
12L6 ...............................................
1414 ...............................................
16L2 ...............................................
1618 ...............................................
16R8 ...............................................
16R6 ...............................................
16R4 ...............................................
16X4 ...............................................
16A4 ...............................................
16P8 ...............................................
16RP8 ..............................................
16RP6 ..............................................
16RP4 ..............................................
12110 ..............................................
14L8 ...............................................
1616 ............................................•..
1814 ...............................................
2012 ...............................................
20C1 ...........•...................................
20L10 ..............................................
20X10 ..............................................
20X8 ...............................................
20X4 ...............................................
2018 ...............................................
20R8 ......................................•....•...
20R6 ...............................................
20R4 ............................•...........•......
20RAlO .............................................
20S10 ...................•..........................
20RS4 .....•........•............. ;.................
20RSS ..............................................
20RS10 .............................................
32R16 .....•..............................•.........
64R32 ..............................................
Programmer/Development System ....................

5-34
5-34
5-35
5-36
5-36
5-36
5-36
5-36
5-37
5-38
5-40

5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59·
5-60
5-61
5-62
5-63
5-64
5-65
5-66
5-67
5-68
5-69
5-70
5-71
5-72
5-73
5-74
5-75
5-76
5-77
5-78.
5-79
5-80
5-81

Die Configuration
\
PAL20RA10 .....•................................... 5-81
PAL32R16 .......................................... 5-82
PAl64R32 .......................................... 5-82

W .emorles

PAL Introduction

The PAL® Concept
Monolithic Memories' family of PAL devices gives designers a powerful tool with unique capabilities for use in
new and existing logic designs. The PAL saves time and
money by solving many of the system partitioning and
interface problems brought about by increases in
semiconductor device technology.

The designer is confronted with another problem when a
product is designed. Often the function is well defined and
could derive significant benefits from fabrication as an
integrated circuit. However, the design cycle for a custom
circuit is long and the costs can be very high. This makes
the risk significant enough to deter most users. The technology to support maximum flexibility combined with fast
turnaround on custom logic has simply not been available.
Monolithic Memories offers the programmable solution.

Rapid advances in large scale integration technology
have led to larger and larger standard logic functions;
single I. C.S now pei"form functions that formerly required
complete circuit cards. While LSI offers many advantages, advances have been made at the expanse of
device flexibility. Most LSI devices still require large
numbers of SSI/MSI devices for interfacing with user
systems. Designers are still forced to turn to random
logic for many applications.

The PAL family offers a fresh approach to using fuse
programmable logic. PAL circuits area conceptually
unified group of devices which combine programmable
flexibility with high speed and an extensive selection of
interface options. PAL devices can lower inventory, cut
design cycles and provide high complexity with maximum flexibility. These features, COmbined with lower
package cOunt and high reliability, truly make the PAL a
circuit deSigner's best friend.

IIIIonoIIthlc

W Memories

PAL" is a registered trademark of Monolithic Memories.

5·3

PAL Introduction
array. Since the sum of products form can express any Boolean
transfer function, the PAL circuit uses are only limited by the
number of terms available in the AND - OR arrays. PAL devices
come in different sizes to allow for effective logic optimization.

The PAL-Teaching Old PROMs
New Tricks

Figure 1 shows the basic PAL structure for a two input, one output
logic segment. The general logic equation for this segment is
Output = (11+i1)(11+f2)(12+f3)(j2+i;;) +

r

'\

(11 +15)(1"1+16)(12+17) (l2+fs)
where the "f" terms represent the state of the fusible links in the
PAL AND array. An unblown link represents a logic 1. Thus,
fuse blown, f = 0
fuse intact, f

=

1

An unprogrammed PAL has all fuses intact.

OUTPUT

MMI developed the modern PROM and introduced many of the
architectures and techniques now regarded as industry
standards. As the world's largest PROM manufacturer, MMI has
the proven technology and high volume production capability
required to manufacture and support the PAL.
The PAL is an extension of the fusible link technology pioneered
by Monolithic Memories for use in bi-polar PROMs. The fusible
link PROM first gave the di~ital systems designer the power to
"write on silicon." In a few seconds he was able to transform a
blank PROM from a general purpose device into one containing
a custom algorithm, microprogram, or Boolean transfer function.
This opened up new horizons for the use of PROMs in computer
control stores, character generators, data storage tables and
many other applications. The wide acceptance of this
technology is clearly demonstrated by today's multi-million
dollar PROM market.

Figure 1

PAL Notation

The key to the PROM's success is that it allows the designer to
quickly and easily customize the chip to fit his unique
requirements. The PAL extends this programmable flexibility by
utilizing proven fusible link technology to implement logic
functions. Using PAL circuits the designer can quickly and effec"
tively implement custom logic varying in complexity from random gates to complex arithmetic functions.

ANDs and ORs
The PAL implements the familiar sum of products logic by using
a programmable AND array whose output terms feed a fixed OR

5·4

MonolIthic

Logic equations, while convenient for small functions, rapidly
become cumbersome in large systems. To reduce possible
confusion,complex logic networks are generally defined by logic
diagrams and truth tableS. Figure 2 shows the logic convention
adoPted to keep PAL logic easy to understand and use. In the
figure, an "x" represents an intact fuse used to perform the logic
AND function. (Note: the input terms on the common line with
the x's are not connected together.) The logic symbology shown
in Figure 2 has been informally adopted by integrated circuit
manufacturers because it clearly establishes a one-to-one
correspondence between the chip layout and the logic diagram.
It also allows the logic diagram and truth table to be combined
into a compact and easy to read form, thereby serving as a
convenient shorthand for PAL circuits. The two input - one output example from Figure 1 redrawn using the new logic convention is shown in Figure 3.

W ""emorles

PAL Introduction
used to store computer programs and data. In these applications the fixed input is aeomputer memory address; the
output is the contents of that ~emory location.
AB?
}-A·B·C
C ~_--II...._

PROM
16 Words X4 Bits

Figure 2

·OR" ARRAY
(PROGRAMMABLE)

~

7'

7~

7~

7

IV \) V IV

=<
=<
=<
K
=<
=<
=<
=f.
.=<
=<
=(

Figure 3
As a simple PAL example, consider the implementation of the
transfer function:
Output", 11i2

+ GI2

The normal combinatorial logic diagram for this function is
shown in figure 4, with the PAL logic eqUivalent shown in figureS.

,

"""'"
=<

OUTPUT

I
~

.

=<

.,

=<

?<
.. L......!'

YYYY

Figure 4

. ANO.. ARRAY
(FIXED)

Figure 6

Figure 5

Using this logic convention it is now possible to compare the
PAL structure to the structure of the more familiar PROM and
PLA. The basic logic structure' of a PROM consists of a fixed
AND. array whose outputs feed a programmable OR array
(figure 6). PROMs are low-cost, easy to program, and available
in .<1 variety of sizes and organjzations. They are most commonly

The basic logic structure of the PLA. consists of a programmable
: AND-array whose outputs :feed a programmable OR array
(Figure .7). Since the designer has complete control over all inputs and outputs, the PLAprovides the ultimate flexibility for implementing logic functions. They are used ina wide variety of
applications. However, this generality makes PLAs expensive,
quite formidable to understand, and costly to program (they
require special programmers).

The basic logic structure of the PAL, as mentioned earlier,
consists of programmable AND array whose outputs feed a
fixed OR array (Figure 8). The PAL combines much :of the
flexibility of the PLA with the low cost and easy programmability
of the PROM. Table 1 summarizes the characteristics of the
PROM, PLA, and PAL logic families:

a

PAL Introduction

PAL
4 In.4 Out.16 Products

FPLA
4 In.4 Out.16 Products
"OR" ARRAY
(PROGRAMMABLE)

7

~

r'J

1

7~

7~

rv V

,

"OR" ARRAY
(FIXED)

7

N [\)

~

7'

7

~

~

rv

7

~

r-"'I.

I=<

F<
K
K
K
K
K
F<

F<
F<

l==<
L........I

..

r==::;,.

I=<

=<
=<

K
K
K
K
K
K
K

K
K
K
K
K

b,..J

~

yyyy

"AND" ARRAY

.

"ANO ARRAY
(PROGRAMMABLE)

(PROGRAMMABLE)

Figure 8

Figure 7

PROM
FPLA
FPGA
FPLS
PAL·

AND

OR

OUTPUT OPTIONS

Fixed
Prog
.prog
Prog
Prog

Prog
Prog
None
Prog
Fixed

TS.OC
TS. OC. Fusible Polarity
TS. OC. Fusible Polarity
TS. Registered Feedback .. I/O
TS. Registered i Feedback. 1/0,

Table 1

5·6

PAL Introduction
PAL Input/Output/Function/Performance Chart·
PART

INPUT OUTPUT

NO.
10H8
12H6
14H4
16H2
16C1
10L8
.12L6
14L4
16L2
12L10
14L8
16L6
18L4
20L2
2OC1
16LS
20LS
2OL10

10
12
14
16
16
10
12
14
16
12
14
16
18
20
20
10
14
12

2
10
8
6
4
2
2
2
2
2

16R8

8

8

16R6

8

6

PROG.

I/O'S

FEEDBACK

AND-OR
AND-OR
AND-OR
AND-OR
BOTH'
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR

8
6
4
2
2
8
6

4

80TI:"I'
6
6
8

AND-NOR
AND-NOR
AND-NOR
8

AND-NOR

2

6

ANQ-NOR

4

4

AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR

16R4

8

4

2OR8
2/)R6
20R4
20X10
2OX8
2OX4
16X4

12
12
12
10
10
10
8

8
6
4
10
8
4
4

2
6
4

8
6
4
10
8
4
4

16A4

8

4

4

4

16P8
16RP8
16RP6
16RP4
20RA10
20RSio
20RSS
20RS4
20810
32R16
64R32

10
8
8

2
8
6
4

6

8
10
10
10
10
10
16
32

PERFORMANCE

OUTPUT

FUNCTIONS

REGISTER POLARITY

2
4

8
6
4
103
10

2
4
103

8

2
6
10

4

163
323

163
323

PROG 2
PROG 2
PROG2
PROG2
PROG2
PROG2
PROG2
PROG2
PROG2.
PROG2
PROG2

STD A -2 A-2
AND-OR Gate Array
AND-OR Gate Array
AND-OR Gate Array
AND-QR Gate Array
AND-QR/NOR Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-QR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-ORINOR Gate Array
AND-OR Invert Gate Array
AND-QR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
w/Regs
AND-OR Invert Gate Array
w/Regs
AND-OR Invert Gate Array
w/Regs
AND-OR Invert w/Regs
AND-OR Invert w/Regs
AND-OR I.nvert w/Regs
AND-OR-XOR Invert w/Regs
AND-OR-XOR Invert w/Regs
ANQ-OR-XOR Invert w/Regs
AND~OR-XOR Invert w/Regs
AND-CARRY-OR-XOR
Invert w/Regs
AND-OR Gate Array
AND-QR Gate Arrayw/Regs
AND-OR Gate Array w/Regs
AND-OR Gate Array w/Regs
Asynchronous Gate Array
AND-OR Gate Array w/Regs
AND-QR Gate Array w/Regs
AND-OR Gate Array w/Regs
AND-OR Gate Array
AND-OR Gate Array w/Regs
AND-OR Gate Array w/Regs

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

A-4

X
X
X
X
X
X
X
X
X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X
X
X
X
X
X
X

...

?<
X
X

X
X
X
X
X
X
X
X
X

.Table2
, Simuhaneous AND-OR and AND-NOR outputs
2programmable active high or active low. i.e. AND-OR or AND-NOR
3 Output can be registered or non·registerSd

PAL Circuits For Every Task

Gate Arrays

The members of the PAL family and their characteristics are
summari~ in Table 2. They are designed to cover the spectrum
of logic functions at reduced cost and lower package count.
This allows the designer to select the PAL that best fits his
application. PAL units come in the following basic configurations:

PAL gate arrays are available in sizes froni 12x 10 (12 input terms,
10 output terms) to 201(2, with both active high and ective low
output configurations available (figure 9). This wide variety of
input/output formats allows the· PAL to replace many different
sized blocks of combinatorial logic with single packages.

Monolithic W""emorle$

5·7

PAL Introduction
INPUTS AND OUTPUTS

""

./
~

.
".

Figure 9

Programmable 1/0
A feature of the high-end members of the PAL family is
programmable input/output. This allows the product terms to
directly control the outputs of the PAL (Figure 10). One product
term is used to enable the three-state buffer, which in turn gates
the summation term to the output pin. The output is also fed

back into the PAL array as an input. Thus the PAL drives the 1/0
pin when the three-state gate is enabled; the I/O pin is an input
to the PAL array when the three-state gate is disabled. This
feature can be used to allocate available pins for I/O functions or
to provide bi-directional output pins for operations such as
shifting and rotating serial data.

INPUTS, FEEDBACK AND I/O

,

..........

...

I

~

I

>-J

I/O

....

.~

Figure 10

Registered Outputs with Feedback
Another feature of the high end members of the PAL family is
registered data outputs with registered feedback. Each product
term is stored into a Ootype output flip-flop on the rising edge of
the system clock (Figure 11). The Q output of the flip-flop can
then be gated to the output pin by enabling the active low threestate buffer.

In addition to being available for transmission, the Q output is
fed back into the PAL array as an input term. This feedback
allows the PAL to "remember" the previous state, and it can
aiter its function based upon that state. This allows the designer
to configure the PAL as a state sequencer which can be
programmed to execute such elementary functions as count up,
count down, skip, shift, and branch. These functions can be
executed by the registered PAL at rates of up to 25 MHz.

INPUTS, FEEDBACK AND /0

I~

BIIIIIIIIIIIIIIIIIII t: "O~'
Figure 11

XOR PALs
These PAL devices feature an exclusive OR function. The sum of
products is segmented into two sums which are then exclusive
ORed (XOR) at the input of the Ootype flip-flop (Figure 12). All

of the features of the Registered PAls are included in the XOR
PAL unit. The XOR function provides an easy implementation of
the HOLD operation used in counters and other state sequencers.

INPUTS, FEEDBACK AND 1/0
CLOCK

Dc

,~IIIIIIIIIIIIIIIIIII!rulllllllllllll~o
Figure 12

5-8

Monollthio mMemories

PAL Introduction
Arithmetic Gated Feedback
The arithmetic functions (add, subtract, greater than, and less
than) are implemented by addition of gated feedback to the
features of the XOR PAL device. The XOR at the input of the
D-type flip-flop allows carrys from previous operations to be
XORed with two variable sums generated by the PAL array. The
flip-flop Q output is fed ~ck to be gated with input terms A

I (Figure 13). This gated feedback provides anyone of the 16

possible Boolean combinations which are mapped in the Karnaugh map (Figure 15). Figure 14 shows how the PAL array can
be programmed to perform these 16 operations. These features
provide for versatile operations on two variables and facilitate
the parallel generation of carrys necessary for fast arithmetic
operations.

INPUTS, FEEDBACK AND 1/0
CLOCK

......

~

=
B

~

OC

~

~

Figure 13

A--~~----~--~r-----,
s---i~--~t-~-r~--.

l-------A.a
l-------A

q-

r.,

}------A.S

.~

.~

or..,

'r., • •~
~

l-------S

-x

xx

x-

A.a

A

A.S

l-------A-S
}------A:.:S
}------A.S

-x

A.S

A:.:S

A-S

S

xx

A

A-S

0

A-S

x-

A.a

a

A-a

A:-:S

}------A

}------A-S

}------o
}------A-S
}------A:-:S

Figure 15

}------A-a

)----a
}------A.a
A.S

(AS)

A.S
(AS)

A.S

A.S

(AS)

(AS)

Figure 14

MonoIlthlcW Memories

5·9

PAL Introduction
Advanced PAL Featul'8$
For 1985, a number of new features have been incorporated into
the PAL family, including:
• Programmable output polarity for active high or active low
. operation
• Register preload which allows complete functional testing
• Product term sharing', a feature making the number of product terms per output user-determinable

devices. PALASM is availlible upon request for many computers
and is documented in the PAL Design Concepts section.

HAL (Hard Array LOgic)
The HAL family is the mask programmed version of a PAL. The
HAL is to a PAL just as a ROM is to a PROM. A standard wafer is
fabricated to the 6th mask. Then a custom metal mask is used to
fabricate Aluminum links for a HAL instead of the programmable
Ti-W fuse array used in a PAL.

• Register bypass facilitating registered or combinatorial outputs
• Asynchronous clocks, sets, resets and output enables

.The HAL is a cost-effective solution for large quantities and is
unique in that it is a gate array with a programmable prototype.

A full description of each function is given on page 5-1'7.

PAL Technology

PAL Programming
PAL devices can be programmed in most standard PROM programmers with the addition of a PAL personality card. The PAL
appears to the programmer as a PROM. During programming
half of the PAL outputs are selected for programming while
the other outputs and the inputs are used for addressing. The
outputs are then switched to program the other locations.
Verification uses the same procedure with the programming
lines held in a low state.

PALASM (PAL Assembler)
PALASM is the software used to define, simulate, build, and test
PAL units. PALASM accepts the PAL Design Specification as an
input file. It verifies the design against an OPtional function table
and generates the fuse plot which is used to program the PAL

*

PAL circuits are manufactured using the proven TTL Schottky
bipolar Ti-W fuse process to make fusible-link PROMs. An NPN
emitter follower array forms the programmable AND array. PNP
inputs provide high impedance inputs (0.25 mA max) to the array.
All outputs are standard TTL drivers with internal active pull-up
transistors. Typical PAL propagation delay time is less than 25 ns.

PAL Data Security
The circuitry used for programming and logic verification can
be used at any time to determine the logic pattern stored in the
PAL array. For security, the PAL has a "last fuse" which can
be blown to disable the verification logic. This provides a significant deterrent to potential copiers, and it can be used to
effectively protect proprietary designs.

Patent pending.

5-10

MonoIIIhIcW Memories

PAL Introduction

vice
ROLL

..

r-;=b'"
-r

'.

r;;,W

rLJ
J

-..

"

.

.'

r-LJ .

,

J.J

03

"---

,

1

""'7.,

~

-

~
1'If
29011

1'If

r-

I.A

120ll

~

05~'

-

1",:

r;;-;W
1>ij6
'--

12011
"

r;-;;J "
1>07

"---

I>Qa
'--

rW

j

J", .

r;;a;w

~

rW
IA "

.\

r---. "

-

Ln

,

-#-

~J
f-

,

2K

12011

Q4
'--

,

=u- ~

20K

":"

~

.'

20K

"--

~

-

'~1~.

Q2

.

~

[X r--td~~

2K

t~~

"

+5Y

2_2

~J
D 02
.

-

.'

~,.
····.~t't·

f-~r-r

~

J

.

I.A 12011

IN
290ll

I.A

r-

1'If

!--

I.A

12011

r~

Figure 16

5-11

PAL Introduction
PAL Part Numbers
The PAL part number is unique in that the part number code
also defines the part's logic operation. The PAL parts code
system is shown in Figure 17. For example, a PAL14L4CN
would be a 14 input term, 4 output term, active-low PAL with a
commercial temperature range packaged in a 2D-pin plastic dip.

PAL16L8 ~2 MJ SHRP P01234

E~ANNUMBER

Progra::JgJ::T.

PAL = Family,
HAL = Hard Array
Family

,

' 0 ,PTIONAL, ,PROCESSING

,

NUMBER OF
ARRAY INPUTS

XXXX

=H~ReJ

PACI-----------------,

-\:.he
PAL16R6

U~'

Pl~"
Pl~'
J1dl~

~~'
~fV'"

,'~Jt ~
'~

".""""""

PAL16R6 Logic Symbols

PAL16R6 Logic Diagram
INPUT

PROGRAMMABLE

CIRCUIT
IDENTIFICATION

OUTPUT
BUFFERS

CURRENT SOURCE
AND PROGRAMMABLE
CIRCUITRY

REGISTERS

MISCELLANEOUS
AND TESTING
CIRCUITRY

THREE-STATE

PAL 16R6 Melallzation
Monolithic

m

Memories

5·15

PAL®.Programmable Array Logic
HA"Hard Array Logic
Featu..../B.nef...

In addition the PAL/HAL provides .these options:

• RecIuceI SSlJMSI cI1lp count greater than 5 to 1

• Variable Input/output pin ratio

• SavelIjHICII with SKINNYDIPI!l packages

• Programmable three-state outputs

• Reduces Ie Inventortes IUbltantlally

• Registers with feedback

• Expedites and IImpll.... prototyplng and boarcllayout

• Artthmetic capability

• PALASM'"

IlIIcon compiler provIdeI auto routing and teat

vecton

• Exclusive-OR gates
• Other options Identified on page 5-17

• Security .... raduces poaalbility of copying by compatltors

Description
The PAL family utilizes an advanced Schottky TTL process and
the Bipolar PROM fusible link technology to provide user programmable logic for replacing conventional SSI/MSI gates and
flip-flops at reduced chip count.
The HAL family utilizes standard LOW-POwer Schottky TTL
process and automated mask pattern generation directly from
logiC equations to provide a semi-custom gate array for
replacing conventional SSI/MSI gates and flip-flops at reduced
chip count.
There are four different speed/power families offered. Choose
from either the standard, high speed, half power, or quarter
power family to maximize desi!!n performance.
The PAL/HAL lets the systems engineer "design his own Chip"
by blowing fusible links to configure AND and OR gates to
perform his desired logic function. Complex interconnections
which previously required time-consuming layout are thus
"lifted" from PC board etch and placed on silicon where they
can be easily modified during prototype check-out or production.
The PAL transfer function is the familiar sum of products. Like
the PROM, the PAL has a single array of fusible links. Unlike the
PROM, the PAL is a programmable AND array driving a fixed
OR array (the PROM is Ii fixed AND array driving a programmable OR array).
The HAL transfer function is the familiar sum of products.·Like
the ROM, the HAL has a single array of selectable gates. Unlike
the ROM, the HAL is a selectable AND array driving a fixed OR
array (the ROM is 8 fixed AND array driving a selectable OR
array).

Unused inputs are tied directly to Vee or GND. Product terms
with ail fuses blown assume the logical high state, and product
terms connected .to both true and· complement of any single
input assume the logical low state. Registers consist of 0 type
flip-flops which are loaded on the low-to-high transition of the
clock. PAL/HAL LogiC Diagrams are shown with ali fuses blown,
enabling the designer to use the diagrams as coding sheets.
The entire PAL family Is programmed using inexpensive conventional PROM programmers with appropriate personality and
socket adapter cards. Once the PAL is programmed and verified, two additional fuses may be blown to defeat verification.
This feature gives the user a proprietary circuit which is very
difficult to copy.
To design a HAL, the user first programs and debugs a PAL
using PALASM and the "PAL DESIGN SPECIFICATION"
standard format. This specification is submitted to Monolithic
Memories where it is computer proceSsed and assigned a bit
pattern number, e.g., P01234.
Monolithic Memories will provide a PAL sample for customer
qualification. The user then submits a purchase order for a HAL
of the specified bit pattern number, e.g., HAL18L4 P01234. See
Ordering Information below.

Ord.rlng Information
PAL =

HAL =

Prog::I_~16L8 -2M .JESHRP~RNNUMBER
~::IL..y

.

SHRP -

NUMBER OF
ARRAY INPUTS

..

.

OUTPUT TYPE
H =-

.

:-' :=:n..Exd.A

:

OR

NS = _
SKINNYDIP
JS= ceramic SKINNYDIP
L = I..Ndea
_ Chip cerrler
P - PIn GrId Array

~

=ArIlhmollc Reglotentd

'---~-TEMPERATURE

NUMBER OF OUTPUTS

C

SPEEDIPOWER----"'"---'
A = HlghSpoed
-2 =1/2_
-4 =1/4_
1102 = High Speed and 1/2 _
A-4 = HIgh Speed and 1/4 _

TWX: 910-338-2376
2175 Mission College QJvd. Santa Clara, CA 95054-1592 "Tel: (408) 970~9700 TWX: 910-338-2374

5-16

~ ~ =~~IP
F

R =Reg_.
Asynchronous

X

~Enhancod

XXXX = HI-ReI
PACKAGE
= Flat Pock
NL=PJuacLeed....
Chip Cantor

High

L =_Low
C = Com~
P = PtogqlnrnabIe

PALe, (Programmable Array Logic), f>ALASMe, HALe, and SKINNYDIP4I
are registered trademsrks and PMSI, and HMSI are trademsrks of
Monolithic MemorieS Inc.

L-OPTIO~ PROCESSING

FomBy

CODE

=CornmoIQaI

M=MIIIIary

···lIIIonoIlthlc 1I·1In
Memorl•• InJrW

PAL/HAL
Register Bypass

PAL Testability Features

Outputs within a bank must either be all registered or all combinatorial. Whether or not a bank of registers is bypassed
depends on how the outputs are defined in the equations. A
colon followed by an equal sign [; = J specifies a registered output
with feedback which is updated after the low-to-high transition of
the clock. An equal sign [= J defines a combinatorial output
which bypasses the register. Registers are bypassed in banks of
eight. Bypassing a bank of registers eliminates the feedback
lines for those outputs.

Preload pins have been added to enable the testability of each
state in state-machine design. Typically, for a modulo-n counter
or a state machine there are many unreachable states for the
registers. These states, and the logic which controls them are
untestable without a way to "set-in" the desired starting state of
the registers. In addition, long test sequences are sometimes
needed to test a state machine simply to reach those starting
states which are legal. Since complete logic verification is
needed to ensure the proper exit from "illegal" or unused states,
a way to enter these states must be provided. The ability to pr&load a given bank of registers is provided in this device.

Output Polarity

To use the preload feature, several steps must be followed. First,
a high level on an assertive-low output enable pin disables the
outputs for that bank of registers. Next, the data to be loaded is
presented at the output pins. This data is then loaded into the
register by placing alow level on the PRELOAD pin. PRELOAD
is asynchronous with respect to the clock.

Output polarity is defined by comparison of the pin list and the
equations. If the logic sense of a specific output in the pin list is
different from the logic sense of that output as defined by its
equation, the output is inverted or active low polarity. If the logic
sense of a specific output in the pin list is the same as the logic
sense of that output as defined by its equation, the output is
active high polarity.

Product Term Sharing
The basic configuration is sixteen product terms shared between
two output cells. For a typical output pair, each productterm can
be used by either output; but, since product term sharing is
exclusive, a product term can be used by only one output, not
both. If equations call for an output pairto use the same product
term, two product terms are generated, one for each output. This
shOUld be taken into account when writing equations: PAL
assemblers configure product terms automatically.
This example uses the 84-pin package. Four output equations
are shown to demonstrate functionality. Pin names are arbitrary.

Product Term Editing
A unique feature of product term sharing is the ability to edit the
design after the device has been programmed. Without this
feature, a new PAL device had to be programmed if the user
needed to change his design. Product term editing allows the
user to delete an unwanted product term and reprogram a
preViously unused product term to the desired fuse pattern. This
feature is made possible by the product term sharing architecture. Since each product term can be routed to either output in a
given pair by selecting one of two steering fuses, itis possible to
blow both of the steering fuses thereby completely disabling that
product term. Once disabled, that product term i.s powered
down, saving typically 0.25 mA. The desired change may now be
programmed into one of the previously unused product terms
corresponding to that output pair. Additional edits can be made
as long as there are unused product terms for the output in
question.

Programmable Set and Reset
(PAL20RA 1 o only)
In each SMAC, two product lines are dedicated to asynchronous
set and reset. If the set product line is high, the register output
becomes a logiC 1. If the reset product I.ine is high, the register
output becomes a logic O. The operation of the programmable
set and reset overrides the clock.

Individually Programmable
Register Bypass (PAL20RA 10 only)
If both the set and reset product lines are high, the sum-ofproducts bypasses the register and appears immediately at the
output, thus making the output combinatorial. This allows each
output to be configured inthe registered or combinatorial mode.

PRESET Feature (PAL64R32 only)

Programmable Clock
(PAL20RA10 only)

Register banks of eight may be PRESET to all highs on the outputs by setting the PRESET pin (PS) to a Low level. Note from the
Logic Diagram that when the state of an output is High, the state
of the register is Low due to the inverting tri-state buffer.

One olthe product linesin each group is connected to the clock.
This provides the user with the additional flexibility of a programmable clock, so each output can be clocked independently
of all the others.

Monollthlo WMemorles

5·17

20/24·Pln PAL/HAL
PAL Input/Output/Function/Pertormance Chart
GENERI C PINS
LOGIC

PACKAGE

10H8

2,0

N,J,F,L,NL

1;2HS

20

N,J,F,L,NL

14H4

20

N,J,F,L,NL

1SH2

20

N,J,F,L,NL

16C1

20

N,J,F,L,NL

10L8

20

N,J,F,L,NL

12L6

20

N,J,F,L,NL

14L4

20

N,J,F,L,NL

16L2

20

N,J,F,L,NL

16L8

20

N,J,F,L,NL

16R8

20

N,J,F,L,NL

16R6

20

N,J,F,L,NL

16R4

20

N,J,F,L,NL

16X4

20

N,J,F,L,NL

16A4

20

N,J,F,L,NL

12L10

24(28) NS,JS,F,(L),(NL)

14L8

24(28) NS,JS,F,(L),(NL)

16L6

24(28) NS,JS,F,(L),(NL)

18L4

24(28) NS,JS,F,(L),(NL)

20L2

24(28) NS,JS,F,(L),(NL)

20C1

24(28) NS,JS,F,(L),(NL)

20L10

24(28) NS,JS,F,(L),(NL)

20X10

24(28) NS,JS;F,(L),(NL)

20X8

·24(28) NS,JS,F,(L),(NL)

20X4

24(28) NS,JS;F,(L),(NL)

20L8

24(28) NS,JS,F,(L),(NL)

20R8

24(28) NS,JS,F,(L),(NL)

20R6

24(28) NS,JS,F,(L};(NL)

20R4

24(28) NS,JS,F,(L),(NL)

DESCRIPTION

Octal 10 Input And-Or
Gate Array
Hex 12 Input And-Or
Gate Array
Quad 14 Input And-Or
Gate Array
Dual 16 Input And-Or
Gate Array
16 Input And-Or/Nor
Gate Array
Octal 10 Input And-Or
I nvert Gate Array
Hex 12 Input And~Or-lnvert
Gate Array
Quad 14 Input And-Or-Invert
Gate Array
Dual 16 Input And-Or-Invert
Gate Array
Octal 16 Input And-Or-Invert
Gate Array
Octal 16 Input Registered
And-Or Invert Gate Array
Hex 16 Input Registered
And-Or Invert Gate Array
Quad 16 Input Registered
And-Or Invert Gate Array
Quad 16 Input Registered
And-Or-Xor Invert Gate Array
Quad 16 Input Registered
And-Carry-Or-Xor Invert
Gate Array
Deca 12 Input And-Or-Invert
Gate Array
Octal 14 Input And-Or-Invert
Gate Array
Hex 16 Input And-Or-Invert
.
Gate Array
Quad 18 Input And-Or-Invert
Gate Array
Dual 20 Input And-Or-Invert
Gate Array
20 Input And-Or/Nor.
Gate Array
Deca 20 Input And-Or-Invert
Gate Array
Deca 20 Input Registered
And-Or-Xor Invert Gate Array
Octal 20 Input Registered
And-Or-Xor Invert Gate Array
Quad 20 Input Registered
And-Or-Xof Invert Gate Array
Octal 20 Input And-Or-Invert
Gate Array
Octal 20 Input Registered
And-Or Invert Gate Array
Hex 20 Input Registe,red
And-Or InVert Gate Array
Quad 20 Input Registered
And-Or Invert Gate Array

PART NUMBER
STANDAR o HIGH SPEED

PAL10H8
HAL10H8
PAL12HS
HAL12HS
PAL14H4
HAL14H4
PAL16H2
HAL16H2
PAL16C1
HAL16C1
PAL10L8
HAL10L8
PAL12L6
HAL12L6
PAL14L4
HAL14L4
PAL16L2
HAL16L2
PAL16L8
HAL16L8
PAL16R8
HAL16R8
PAL16R6
HAL16R6
PAL16R4
HAL16R4
PAL16X4
HAL16X4
PAL16A4
HAL16A4
PAL12L10
HAL12L10
PAL14L8
HAL14L8
PAL16L6
HAL16L6
PAL18L4
HAL18L4
PAL20L2
HAL20L2
PAL20C1
HAL20C1
PAL20L10
HAL20L10
PAL20X10
HAL20X10
PAL20X8
HAL20X8
PAL20X4
HAL20X4

..
() =MIlitary Product Standard.

5·18

PAL16L8A
HAL16L8A
PAL16R8A
HAL16R8A
PAL16R6A
HAL16R6A
PAL16R4A
HAL16R4A

IIIIonoIlthlc WMemorles

PAL20L8A
HAL20L8A
PAL20R8A
HAL20R8A
PAL20R6A
HAL20R6A'
PAL20R4A
HAL20R4A

1/2 POWER
PAL10H8-2
HAL10H8-2
PAL12HS-2
HAL12HS-2
PAL14H4-2
HAL14H4-2
PAL 16H2-2
HAL16H2-2
PAL16C1-2
HAL16C1-2
PAL10L8-2
HAL10L8-2
PAL12L6-2
HAL12L6-2
PAL14L4-2
HAL 14L4-2~
PAL16L2-2
HAL16L2-2
PAL16L8A-2
HAL16L8A-2
PAL16R8A-2
HAL16R8A-2
PAL16R6A-2
HAL16R6A-2
PAL16R4A-2
HAL16R4A-2

114 POWER

~

.

PAL16L8A-4
HAL16L8A-4
PAL16R8A-4
HAL16R8A-4
PAL16R6A-4
HAL16R6A-4
PAL16R4A-4
HAL16R4A-4

20/24-Pin PAL/HAL
PAL Input/Output/Function/Performance Chart
GENERIC
PINS
.LOGIC

*

PACKAGE

DESCRIPTION

PART NUMBER
STANDARD HIGH SPEED

*16P8

20

I N,J,L,NL

*16RP8

20

N,J,L,NL

*16RP6

20

N,J,L,NL

*16RP4

20

N,J,L,NL

20S10

24(28)

N,J,W,(L),(NL)

20RS10 24(28)

N,J,W,(L),(NL)

20RS8

24(28)

N,J,W,(L),(NL)

20RS4

24(28)

N,J,W,(L),(NL)

20RA10 24(28)

N,J,W,(L),(NLj

32R16

40(44)

N,J,(L),(NL)

64R32

84(88)

L,(P)

Octal 16 Input And-Or
Array w/Programmable
Polarity
Octa,l 16 input Registered
And-Or Array
w/Programmable Polarity
!-lex 16 Input Registered
And-Or Array
w/Programmable Polarity
Quad 16 Input Registered
And-Or Array
w/Programmable Polarity
Oeca 20 Input Arid-Or Array
w/Product Term Sharing
Deca 20 Input Registered
And-Or Array
w/Product Term Sharing
Octal 20 Input Registered
And-Or Array
w/Product Term Sharina
Quad 20 Input Registered
And-Or Array
w/Product Term Sharing
Deca 20 Input Registered
Asynchronous And-Or Array
16 Output, 32 Input
Registered And-Or
Gate Array
32 Output, 64 Input
Registered And"Or
Gate Array

Contact Factory for Flat Pack

Die Configuration: PAL16L8

PAL16P8A
HAL16P8A
PAL16RP8A
HAL16RP8A
PAL16RP6A
HAL16RP6A
PAL16RP.4A
HAL16RP4A
PAL20S10
HAL20S10
PAL20RS10
HAL20RS10
PAL20RS8
HAL2ORS8
PAL20RS4
HAL20RS4
PAL20RA10
HAL20RA10
PAL32R16
HAL32R16
PAL64R32
HAL64R32

1/2 POWER

1/4 POWER

PAL/HAL
Absolute Maximum Ratings

Operating

Programming

Supply Voltage, vee " ............................................. , .. -O.5V to 7.0V ....................... -O.5V to 12.0V
-1.0 to 22V
Input Voltage ........... , ............................................. -1.5V to 5.5V. . . .. . .. . . . .. . .. . .. .. ..
Off-state output Voltage·· ................................................
5.5V ............................... 12.OV
Storage temperature... . ... ............................. .....
. ............................ --65° to +150°C

Schematic of Inputs and Outputs

Test Load
5V

v cc 0 EQUIVALENT INPUT

E"~

)

Rj
OUTPUT o--~-rTEST POINT

R2

-

'T 50pF

~
OUTPUT

Other loads may be used.

4-1.

Typical notes for all the following specifications (pages 5-21 - 5-39)
Notes: Apply to electrical and switching characteristics

t

110 pin leakage is the worst case of 10ZX or 'IX e;g .• IlL and 10ZH-

• These are absolute voltages with respect to the ground pin On the device and includes all overshoots due to system and/or
tester noise. Do not attempt to test these values without suitable equipment.
•• Only one output shorted at a time.

5-20

Monolithic

W IIIIemorles

20·Pin PAL/HAL
1OH8

12H6

14H4

16H2

16C1

10L8

12L6

14L4

16L2

16L8

16R8

16R6

16R4

16X4

16A4

MotIoIlthlc

W Memories

5·21

20-Pin. PAL/HAL

5-22

PAL16P8

PAL16RP8

PAL16RP6

PAL16RP4

Monolithic

miD Memories

24·Pin PAL/HAL
12L10

14L8

16L6

18L4

20L2

2OC1

20L10

20X10

20X8

20X4

20L8

20R8

2OR6

2OR4

I

(
IIIIonoIlthlo

W Memories

5·23

24·Pin PAL/HAL

2OS10

20RS4

20RSS

20RA10

Pi:
10

00

11

01

12

02

13
14
/

15
16

5·24

17

07

18

08

19

09

OND

DE

20RS10

MegaPAL

64R32

32R16

32R16

MoneIItblcWMemorle$

5-25

Standard PAL/HAL Serl.. 20
10H8,12H8,14H4,18H2,18C1,10L8,12L8,14L4,18L2

Operating Conditions
MILITARY
MIN TYP MAX

PARAMETER

SYMBOL

Vce

Supply voltage

4.5

TA

Operating free-air temperature

-55

TC

Operating case temperature

Electrical Characteristics
SYMBOL

Vil

*
*

4.75

5

0

5.25
75

Over Operaling Conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

low-level input voltage

MAX

0.8
2

High-level input voltage

VIC

Input clamp voltage

III

low-level input current

Vce

IIH

High-level input current

VCC

II

Maximum input current

Vee

= MIN
= MAX
= MAX
= MAX

Val

low-level output voltage

VCC

= MIN

VCC

High-level output voltage

lOS

Output short-circuit current

ICC

Su pply current

V
·C
·C

125

VIH

VOH

5.5

5

COMMERCIAL
UNIT
MIN TYP MAX

VCC

**

II
VI
VI
VI

= -18mA
= O.4V
= 2.4V
= 5.5V
=

SmA

COM

10l

=

SmA

Mil

IOH

= -2mA

COM

10H

= -3.2mA
= OV

0.3

= MIN

VCC

= 5V

VCC

= MAX

-1.5

-0.02 -0.25

10l

2.4

Vo

-30

V
V

-0.8

Mil

UNIT

V
mA

25

fJA

1

mA

0.5

2.8

V

V

-70

-130

mA

55

90

mA

Switching Characteristics

In put or feedtpD

5·26

back to output

I

I

MILITARY

TEST

PARAMETER

SYMBOL

CONDITIONS

Except 16C1
16C1

IIIIonolithic

MIN

= 560n
= 1.1kn

R1
R2

m

Memories

COMMERCIAL

TYP

MAX

25
25

MIN

TYP

MAX

45

25

35

45

25

40

UNIT

ns

Standard PAL/HAL Serl.. 24

12L10, 14L8,18L8,18L4,20L2,20C1

Operating COl;ldltions
PARAMETER

SYMB()L

MILITARY
MIN TYP MAX

COMMERCIAL
UNIT
MIN TYP MAX
4.75

Vcc
TA

Supply voltage

4.5

Operating free-air temperature

-55

TC

Operating case temperature

Electrical Characteristics
SYMBOL

5

5.5

5

0

5.25

V

75

·C

125

·C

Over Operating Condilions
~.ST CONDITIONS

PARAMETER

MIN'TYP

MAX UNIT

Vil ...
VIH

....

low~level

input voltage

0.8

High-level input voltage

V

2

V

VIC

Input clamp voltage

VCC = MIN

II = -18mA

III

low-level input current

VCC = MAX

VI=0.4V

-0.02 -0.25

IIH

High-level input current

Vce = MAX

VI = 2.4V

25

J1A

II

Maximum input current

Vce = MAX

VI = 5.5V

1

mA

VOL

low-level output voltage

VOH

Mil

-0.8

:

.tOl = SmA

High-level 0\ltput voltage

COM

10l = 8mA

Mil

tOH = -2mA

VCC = MIN

.,'

","

COM
lOS

Output short::Cfrcuit current'" ...

VCC = 5V

tec

Supply current

Vec = MAX

Switching Characteristics
'.

SYMBoL
tpo

PARAMETER
I"put or feedback to output

0.3

Vcc = MIN

?.4

-1.5

V
mA

0.5

V

2.8

V

10H = -3.2mA

-36

'Vo = OV

-70 '. -130

mA

100

inA

6P

Over Operating Conditions

TEST
CONDITIONS
Rt ,; 5600,
R2 = 1.1kO

MIN

'

.'

MILITARY
COMMER~IAL
UNIT
TYP MAX MIN TYP MAX
25

45
,

"

:,'

25

ns

40

','

,

5-27

Standard PALl HAL Beri. . 20
18L8, 1.8R8, 18R8, 18R4, 18X4, 18A4

Operating Conditions
PARAMETER

SYMBOL

Vee

Supply voltage

tw

Width of clock

tsu

Set up time from
input or feedback to clock

th

Hold time

4.5

5

4.75

5

25

High

25

10
10

25
25

10
10

45

25

35

25

55

30

45

30
-15

16R6 16R4

l6RS

Operating free-air temperature

Te

Operating case temperature

COMMERCIAL
UNIT
MIN TYP MAX

low

16X416A4

TA

MILITARY
MIN TYP MAX

*
VIH *

Vil

Vee

IIH

Vee

II

Maximum input current

Vee

VOH

low-level input current

low-level output voltage

Vee

High-level output voltage

Vee

= MIN
= MAX
= MAX
= MAX

II
VI
VI
VI

= -lSmA
= O.4V
= 2.4V
= 5.5V

Off-state output current t

Vee

**

Vee

Switching Characteristics

eOM

IOH

= -3.2mA

Vo

= 0.4V

-100

Vo

= 2.4V
= OV

100

/J A

-70

-130

mA

120

180

0.3

2.4

= 5V

Vo
16R6

16RS

-30

16lS

0.5

2.S

V

V

16X4

160

225

16A4

170

240

/J A

mA

Over Operating Conditions
TEST
CONDITIONS

MILITARY
MIN TYP MAX

tpzx

Pin 11 to output enable except 16lS

15

25

tpxz

Pin 11 to output disable except 16la
Input to
16R6 16R4 16L8
output enable
16X4 16A4
Input to
16R6 16R4 16lS
output disable
16X4 16A4

15

25

25
30

45
45
45
45

5·28

mA

= -2mA

telK

Maximum
frequency

1

IOH

45
45

fMAX

/J A

Mil

25
30
15

tpxz

25

= 24mA

16R6 16R4 16lS
16X4 16A4
elock to output or feedback

tpzx

V
rnA

IOl

Input or feedback to output

tpD

-1.5

-0.02 -0.25

eOM

= MAX

PARAMETER

SYMBOL

V

= 12mA

= MIN

Vee =MAX

Supply current

UNIT

IOl

= MIN

16R4
lee

MAX

Mil

10ZH
Output short-<:ircuit current

°e

V
-O.S

IOZl

lOS

TYP

2
Vee

VOL

ns

O.S

t
High-level input current t

III

ns

°e

MIN

High-level input voltage

V
ns

125

TEST CONDITIONS

PARAMETER

5.25

75

0

low-level input voltage

Input clamp voltage

Vie

0

-15

0
-55

.
.
Electrical Characteristics Over Operating Conditions
SYMBOL

5.5

16RS 16R6 16R4
16X4 16A4

Rl = 200n
R2 = 390n

25
30
14
12

25
22

COMMERCIAL
UNIT
MIN TYP MAX

25
30
15

35
40
25

ns
ns
ns

15
15

25

ns

25

ns

35
40
35

ns
ns

16

25
30
25
30
25

14

22

25

40

ns
ns

MHz

S18ndanlPAL/HAL Serl. . 24
20Xt 0, 20X8" 20X4, 20L to

Operating Conditions
SYMBOL'
Vee

PARAMETER
Supply voltage
low

tw

Width of clock

tsu

Set up time from
input or feedback to clOCk

th

Hold time

High

TA

Operating free-air temperature

Te

Operating case temperature

Ilectrical Characteristics
'. :
SYMBOL

MILITARY
MIN TYP MAX

COMMERCIAL
UNrT
MIN TYP MAX

4.5

5

4.75

5

40
30

20
10

35
25

20
10

ns

60

38

50

38

ns

0
-55

-15

5.5

0

-15
75

0

125

0.,.

Over Operalln9 CqnclU

PARAMETER

5.25

"

V

ns
·C
·e

;

, , : ' , c/

TEST CONDITIONS

MAX UNIT

MIN TYP

*
VIH *

High-level input voltage

Vie

Inpulclamp voltage

Vee = MIN

II" -18mA

Vee"; MAX

VI = O.4V

-0.02 -0.25

'IH

t
High-level inplJt current t

Vee" MAX

Vi = ,2AV

25

Jl.A

II

Maximum input current

Vee = MAX

VI=5.SV.

1

mA

VOL,

low-level output voltage

Vil

Ill~

low-level, input voltage

0.8
2

, LOW-level input current

VOH

10l

= 12mA

.IOL

= 24mA

= MIN
eOM

High-level output voltage

,Mil

10H " -2mA

eOM

'OH = ""3.2mA

Off-state output current

t

• Output short-circuit current

0.5

2.8

V
mA

V

V

" 0.4V

-100

p,A

Vo " 2.4V

100

p,A

-70

-130

mA

120

160

mA

Vee = MAX

10ZH';
lOS

-1.5

0:3

2.4

Vee" MIN

Vo

'OZl

V
-0.8

Mil
Vee

V

**

'VO =OV

Vee = 5V

lee;

Supply current

Vee = MAX

2OX10

lee

Supply current

Vee = MAX

2Oll0

20X8

:...:30'

20X4

90 "

:,",

165 "'mA;'

SwitchlngCharactMisticaoveroperatlng Conditions

tpo
tOlK'
tpXZlZX

I tpzx

.

COMMERCIAL
MILITARY
UNIT
MIN TYP MAX MIN TvP MAX

TEST
CONDITIONs

PARAMETER

SYMBQl

ns

35

60

35

50

Clock to output Or feeqback

.2()

30

ns

20

35
45

20

Pin 13 to output disable/enable except 2Ol10

20

35

ns

35

55

35

45

.ns

35

55

35

45

. ns

Input' or feedbackJo output
' , '

Input to output enable except 2OX10

tpxz

Input to output disable except 2OX10

fMAX

Maxim.um frequency

.~'

Rl" 2000
R2=3900

.

"

".

10.5

1&

:.

,12.5

16

MHz
.

Fast PAL/HAL Serl. . 2PAJ~OAP
16L8A, 16R8A, 16R6A,1"6R4A, 16P8Al 16RP8A, 16RP6A, 16RP4A

Operating Conditions
,PARAMETER

SYMBOL
Supply voltage

VCC

Low

Width of clock

tw

High

Set up time. from
Isu

input or feedback to clock

th

MILITARY
MIN TYP" MAX

COMMERCIAL
UNIT
MIN TYP MAX
4.75

5
10

4.5

5

'20
20

10
10

15
15

30

15

25

15

-10

0

-10

16RBA 16R6A 16R4A
16RPBA 16RP6A 16RP4A

Hold time

0

TA

Operating free-air temperature

-55

TC

qperating case tel11 perature,

Electrical Characteristics
SYMBOL
VIL

*

•

VIC

Input clamp voltage

IlL

LOW-level input current

II

Maximum input current

VOL

Low-level output voltage

..

TEST CONDITIONS

lOS

Output short-circuit current

ICC

Supply current

-O.B

tCLK

-{).02 -0.25

VCC = MAX

VI = 2.4V

25

pA

VCC = MAX

VI = 5.5V

1

mA

MIL

IOL = 12mA

COM

IOL = 24mA

MIL

IOH = -2mA

COM

IOH = -3.2mA

0.3

2.4

Va = 2.4V

100

**

/lA

-130

mA

Va

VCC = 5V

.= OV

-30

VCC = MAX

-70
1'20

180

mA

Over OperalingCondllions
TEST
CONDITIONS

MILlTAAv
MIN TYP MAX

16R6A 16R4A 16L8A
16RPSA 16RP4A 16P8A

10

tpzx

Pin 1110 output enable except 16LBA 16PBA

10

20
", 25

tpxz

Pin 11:10 output disable except 16L8A 16P8A
InpuUo
16R6A 16R4A 16LBA
output enable
16RPSA16RP4A 16P8A

11
10

Maximum
frequency

V

/lA

Clock to output or feedback

fMAX

2.B

V

-100

30

Input to
output disable

0.5

V
mA

= 0.4V

15

tpxz

-1.5

II = -lBmA

PARAMETER.
Inpuror feedback to output

V

VCC = MAX

Switching Characteristics

tpD

V

VI = 0.4V

VCC = MIN

t

UNIT

VCC = MAX

Va

SY"'~OL

MAX

"

Vee = MIN

10ZH

5-30

MIN ··TYP

VCC = MIN

High-Ieval output voltage

Off-state output current

tpzx

" '"
O.B

IIH

ns·
··C
·C

2

t
High-level input current t

10ZL

ns

125

Low-level input voltage

VIH

ns

75

>ii, .. . ,",

Over Operating CondHlons

I

'V

?25

10

0

.

PARAMETER

High-level input voliage

VOH

5.5

:16R6A16R4A 16LBA
16RPSA 16RP4A 16PBA
16RBA 16R6A 16R4A
16RPBA 16RPSA 16RP4A

Rl =2000
R2= 3900

" , .,13
20

40

COMMERCIAL
UNIT
MIN TYP MAX
15

25

ns
ns

10

15

10"

20·

ns

25

11

20

ns

30

10

25

ns

30.

13.

25

ns

28.5

40

MHz

Fast ....... 24A
20LaA,20R8A,20R8A,20R4A

Operating Conditions
SYMBOL
Vee

COMMERCIAL
UNIT
MIN TYP MAX

4.5

5

4.75

5

7
7

15

7

High

20
20

15

7

20RSA 20R6A 2OR4A

30

15

25

15

,-10

Supply voltage
low

tw

Width of clock

tsu

Set up time from
input or feedback to clock
Hold time

0

TA

Operating free-air temperature

~

Te

Operating caSe temperature

th

Electrical Characteristics
SYMBOL

Vie

Input clamp voltage

Maximum input current

VOL

low-level output voltage

ns
75

MIN

TYP

MAX

lOS

Su pply current

V

-1.5

Vee = MIN

II = -1SmA

Vee = MAX

VI = 0.4V

-0.02 -0.25

Vee = MAX

VI = 2.4V

25

IlA

Vee = MAX

VI = 5.5V

1

mA

V
inA

MIL

10l = 12mA

eOM

10l = 24mA

.MIL

10H = -2mA

eOM

10H

= -3.2mA

Vo

= 0.4V

-100

Il A

. Vo

= 2.4V

100

Il A

-90

-130

mA

160

210

mA

0.3

2.4

0.5

2.S

V

V

Vee = MAX

10lH

lee

UNIT

V
-O.S

Vee = MIN

t

Output shcirt-<:ircuit current

°e
°e

Vee = MIN

High-level output voltage

**

Switching Characteristics

tpo

Input or feedback to output

telK

elock to output or feedback

Vo = O¥

Vee = 5V

-30

Vee = MAX
.

Over Opel'lltlng Condillons

PARAMETER

SYMBOL

ns

O.S

II

Off-state output current

ns

2

IIH

V

Over Operating CondHIons

Low-level input current

lOll

5.25

.,10

0

low-level input voltage

t
High-level input current t

VOH

0

TEST CONDITIONS

High-level input voltage

IlL

5.5

125

PARAMETER

*
VIH*

Vil

--

MILITARY
MIN TYP MAX

PARAMETER

TEST
CONDITIONS

MIN

20R6A 2OR4A 20lSA

MILITARY
TVP MAX

COMMERCIAL
UNIT
MIN TYP MAX
ns

15

30

15

25

10

20

10

15

ns

20

ns

tplX

Pin 13 to output enable except 20LBA

10

25

10

tpXl

Pin 13 to output disable except 2OL8A

11

25

11

20

ns

tplX

Input to
output enable

2OR6A 2OR4A 20LBA

10

30

10

25

ns

tpxz

Input to
output disable

2OR6A 20R4A 20LBA

13

30

13

25

ns

fMAX

Maximum
frequency

20RBA 2OR6A 2OR4A

R1 = 2000
R2= 3900

20

40

2S.5

40

MHz

Helf Power Sari.. 20-2
10H8-2, 12H8-2, 14H4-2; 18H2.2, 18C1-2, 101.8-2, 12L8-2, 14L4-2, 18L2-2

Operating Conditions
MILITARY
MIN TYP MAX

PARAMETER

SYMBOL
Vee

Supply voltage

4.5

TA

Operating free-alr temperature

-65

Electrical Characteristics
SYMBOL

Over Operating

5

COMMERCIAL
UNIT
MIN TYP MAX

5.5

4.75

125

0

5

5.25
75

V
'e

ConcitlOIll
TEST CONDITIONS

PARAMETER

MIN TYP

MAX UNIT

...

*
VIH*

Low-level input voltage

Vie

Input clamp voltage

Vee: MIN

II : -18mA

-1.5

V

IlL

Low-level input current

Vee: MAX

VI : 0.4V

-0.02 -0.25

mA

IIH

High-level input current

Vee: MAX

VI : 2.4V

25

Il A

II

Maximum input current

Vee: MAX

VI : 5.5V

1

mA

VOL

Low-level output voltage

0.5

V

VIL

VOH

0.8
2

High-level input voltage

High-level output voltage.

lOS

Output short~ircuit current

lee

Supply current

tpo

MIL

IOL :

4mA

eOM

IOL :

4mA

MIL

IOH : -1mA

eOM

IOH = -1mA

0.3

2.4

Vee: MIN

**

Vo : OV

Vee: 5V

-30

Vee = MAX

Switching Characteristics
SYMBOL

-0.8

Vee: MIN

PARAMETER

Input or feedback to output

V
V

2.8

V

-70

-130

mA

30

45

mA

Over Operating Concltlons
TEST
R1 = 1.12kO
R2 = 2.2kO

MILITARY
MIN TYP MAX

45

80

COMMERCIAL
UNIT
MIN TYP MAX

45

60

ns

Helf Power Serl.. 20A-2
18L8A-2, 18R8A-2, 18R8A-2, 18R4A-2

Operating Conditions
PARAMETER

SYMBOL

Vee

Supply voltage
Low

tw

Width of clock

tsu

Set up time from
input or feedback to clock

th
TA

High

5

4.75

5

10
10

25
25

10
10

ns

50

25

35

25

ns

Vie

Input clamp voltage

IlL

Low-level input current

Low-level output voltage

Vee
Vee
Vee

MIN

= MIN
= MAX
= MAX
= MAX

II
VI
VI
VI

= -18mA
= O.4V
= 2.4V
= 5.5V

TYP

MIL

10L = 12mA

eOM

10L = 24mA

Vee

MIL

10H

eOM

IOH = -3.2mA

t

Vee

lOS
lee

Supply current

**

=

V

V

-{).02 -0.25

mA

25

/1 A

1

mA

0.5

V

-2mA

= MIN

2.4

2.8

V

Vo

= 0.4V

-100

/1 A

Vo

= 2.4V

100

/1 A

Vo

= OV

-70

-130

mA

60

90

mA

COMMERCIAL
MIN TYP MAX

UNIT

MAX

Vee = 5V

-30

Vee = MAX

Switching Characteristics

Over Operating Conditions
TEST
CONDITIONS

PARAMETER

Input or feedback to output

=

UNIT

-1.5

0.3

10ZH

SYMBOL

MAX

V
-0.8

Vee = MIN

High-level output voltage

Output short.:circuit current

°e

Over Operating Conditions

Vee

VOL

Off-state output current

ns

0.8

Maximum input current

V

75

2

II

IOZl

5.25

-15

0

Low-level input voltage

IIH

teLK
tpXZlZX

0
125

TEST CONDITIONS

t
High-level input current t

tpo

5.5

-15

0
-55

PARAMETER

High-level input voltage

VOH

16R8A-2

4.5
25
25

Hold time

*
VIH *

Vll

16R4A-2

COMMERCIAL
UNIT
MIN TYP MAX

Operating free-air temperature

Electrical Characteristics
SYMBOL

16R6A-2

MILITARY
MIN TYP MAX

MIN

25

16L6A-216R6A-216R4A-2

tpzx
tpxz

Input to
output disable

16R8A-2' 16R6A-2 16R4A-2

fMAX

Maximum
frequency

16RBA-2 16R6A-2 16R4A-2

50

25

35

ns

15

25

15

25

ns

R1= 2000

15

25

15

25

ns

R2 = 3900

25

45

25

35

ns

25

45

25

35

ns

elock to output or feedback
Pin 11 to output disable/enable except 16L8A-2
Input to
16LBA-2'16R6A-2 16R4A-2
output enable

MILITARY
TYP MAX

MonoIlthh) W""emorles

14

25

16

25

MHz

5-33

Quarter Po. .r ....... 20A-4
18L8A-4, 18R8A-4, 18R8A-4, 18R4A-4

Operating Conditions
SYMBOL

MILITARY
MIN TVP MAX

PARAMETER
Supply voltage

VCC

4.5

5

40
40

20
20

90

45

Hold time

0

-15

Operating free-air temperature

-55

.1

tw

Width of clock

loW
16R8A-4 16R8A-4 16R4A-4 , High

tsu

Set up time from
input or feedback to clock

16R8A-4 16R6A-4 16R4A-4

th
TA

Electrical Characteristics
SYMBOL

.

Vil •
ViH

High-level input voltage

TEST CONDITIONS

IIH

Vee

II

Maximum input current

Vee

VOL

low-level output voltage

Vee

= MIN

III

VOH

High-level output voltage

VCC
Vce

Vee

II
VI
VI
VI

Output short-circuit current*·

COM

IOl = SmA

ns

0

-15

Mil

·IOH = -1mA

telK
tpXZlZX
tpzx

back to output

Vee

2.4

Vce

5-34

V
V

-1.5

V
mA

25

IJA

1

mA

0.5

2.8

V

V

= 0.4V

-100

IJA

Vo = 2.4V

100

IJA

-70

-130

mA

30

50

mA

= MAX
= 5V

Vec = MAX

Vo

= OV

-30

16R4A-4 16R6A-4 16R8A-4 16L8A-4

Over Operating Concltlons
TEST

MILITARY
COMMERCIAL
UNIT
MIN TYP MAX MIN TVP MAX

16R8A-4 16R4A-4 16l8A-4

35

75

35

55

ns

Clock to output or feedback

20

45

20

35

ns

R1 = SOOO

15

40

15

30

ns

R2 = 1.56kO

30

65

30

50

ns

30

65

30

50

ns

output disable

16R6A-4 16R4A-4 16L8A-4

Maximum
fMAX

MAX UNIT

Pin 11 tooutputdisablelenable-except16L8A-4
Input to
16R6A-4 16R4A-4 16L8A-4
output enable
Input to

tpxz

·C

10H =-1 mA

Input or feedtpo

V

ns
75

0

0.3

= MIN

PARAMETER

SYMBOL

45

-0.02 -0.25

10l = 4mA

10ZH

Switching Characteristics

60

-0.8

Vo
Off-state output currentt

ICC

ns

MIN TVP

Mil

10Zl

Supply current

30

= -18mA
= 0.4V
= 2.4V
= 5.5V

COM

lOS

5.25

0.8

= MIN
= MAX
= MAX
= MAX

Input clamp voltage
low-level input current

5

20
20

2

t
High-level input current t

VIC

125

4.75

30

Over Operating CondltlOlll

PARAMETER
low-level input voltage

5.5

COMMERCIAL
UNIT
MIN TVP MAX

frequency

16R8A-4 16RSA-4 16R4A-4

8

18

1'1

18

MHz

PAL20RA10
Operating Conditions
SYMBOL

MILITARY
MIN TYP MAX

PARAMETER

Supply voltage

4.5

5

4.75

5

tw

Width of clock

25

13

20

13

ns

twp

Preload pulse width

45

15

35

15

ns

tsu

Setup time for input or feedback to clock

25

10

20

10

ns

tsup

Preload setup time

30

5

25

5

ns

Polarity fuse intact

10

-2

10

-2

Polarity fuse blown

0

-6

0

-6

5

I
I

Hold time

thp

Preload hold time

30

TA

Operating free-air temperature

-55

TC

Operating case temperature

25

5.25

UNIT

VCC

th

5.5

COMMERCIAL
MIN TYP MAX

ns
ns

5

0

V

75

125

°c
°c

Electrical Characteristics Over Operating Conditions
SYMBOL

VIL *

Low-level input voltage

VIH

High-level input voltage

,

TEST CONDITION

PARAMETER

MIN TYP MAX

0.8

V

-1.5

V

2

VIC

Input clamp voltage

IlL

Low-level input current

= MIN
Vee = MAX

IIH

High-level input current

Vce = MAX

II

Maximum input current

Vee

VOL

Low-level output voltage

Vee = MIN

VOH

High-level output voltage

Vee

10Z

Off-state output current

Vee

lOS

Output short-circuit current"

Vee

lee

Supply current

Vee = MAX

V

II = -18mA

Vce

= MAX

-0.8

= 0.4 V
= 2.4 V

-0.02 -0.25
25

p.A

VI = 5.5 V

1

mA

VI
VI

0.3

10L = 8mA

= MIN
= MAX
= 5V

UNIT

2.4

10H: Mil-2 mA Com-3.2 mA
Vo

= 2.4 VIVo = 0.4 V

-100
-30

Vo = OV

0.5

2.8

mA

V
V

100

p.A

-70

-130

mA

155

200

mA

Switching Characteristics Over Operating Conditions
SYMBOL

TEST
CONDITIONS

PARAMETER

tpo

Input or feedback to output

telK

Clock to output or feedback

ts

Input to asynchronous set

tR

Input to asynchronous reset

tpzx

Pin 13 to output enable

tpxz

Pin 13 to output disable

tpzx

Input to output enable

tpxz

Input to output disable

fMAX

Maximum frequency

MILITARY
MIN TYP MAX

fose intact
II Polarity
Polarity fuse blown
10

R1 = 5600
R2 = 1.1 KO

16

MonoIlthlclRlD Memories

COMMERCIAL
MIN TYP MAX

UNIT

20

35

20

30

25

40

25

35

17

35

17

30

ns

22

40

22

35

ns

27

45

27

40

ns

10

25

10

20

ns

10

25

10

20

ns

18

35

18

30

ns

15

35

15

30

35

10

20

35

ns

ns
MHz

5·35

SERIES 24RS, 20S10, 20RS10, 20RS8, 20RS4
Operating Conditions
SYMBOL

Vee

MILITARY
MIN TYP MAX

PARAMETER

Supply voltage

COMMERCIAL
MIN TYP MAX

5.5 ·4.75

4.5

5

Low

20

10

15

10

High

20

10

15

10

20HS10
20RS8
20RS4

40

25

35

25

0

-10

tw

Width of clock

tsu

Setup time from input
or feedback to clock

th

Hold time

0

TA

Operating free-air temperature

-55

TC

Operating case temperature

-10

5

0

5.25

UNIT

V
ns

ns
ns
75

125

°c
°c

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL *

Low-level input voltage

VIH *

High-level input voltage

VIC

Input clamp voltage

TEST CONDITION

MIN

TYP

MAX UNIT

0.8
2

V
V

Vee = MIN

II = -18 mA

-0.8

-1.5

V

III

low-level input current

t

Vee = MAX

VI = 0.4 V

-.0.02 -0.25

IIH

High-level input current

t

Vee = MAX

VI = 2.4 V

25

/J A

II

Maximum input current

Vee = MAX

VI = 5.5 V

1

mA

VOL

Low-level output voltage

Vee = MIN

VOH
10Zl

High-level output voltage

Vee = MIN

Off-state output currentt

Vee = MAX

Mil

IOl = 12mA

COM

10l = 24mA

Mil

10H = -2mA

COM

IOH = -3.2 mA

Output short-circuit current **

Vec = 5V

ICC

Supply current

Vee = MAX

2.4

Va = 0.4 V

Vo

0.5

2.8

=OV

V

V
-100

/J A

100

VOL = 2.4mA

IOZH
lOS

0.3

mA

.-30

-70

-130

mA

175

240

mA

Switching Characteristics Over Operating Conditions
SYMBOL

TEST
CONDITIONS

PARAMETER

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

UNIT

Polarity fuse intact

25

40

25

35

Polarity fuse blown

30

45

30

40

Clock to output or feedback

12

20

12

17

ns

tpzx

Pin 13 to output enable except 20S10

10

25

10

20

ns

tpxz

Pil"l13 to output disable except 20S10

11

25

11

20

ns

tpzx

Input to
output enable

20S10,20RS8,
20RS4

25

35

25

35

ns

tpxz

Input to
output disable

20S10,20RS8
20RP4

13

25

13

25

ns

fMAX

20R510,20RS8,20RS4
Maximum frequency

tpD

20S10,20RS8,20RS4
Input or feedbacK to
output

tClK

5·36

R1 = 200 fl
R2 = 390 Kfl

18

IIIIonoIlthlc

W lIIIemorles

28

20

28

ns

MHz

PAL 32R16
HAL PARAMETERS MAY DIFFER. CONTACT FACTORY FOR DETAILS.

Operating Conditions
SYMBOL

PARAMETER

VCC

Supply voltage

tw

Width of clock

twp

Preload pulse width

tsu

Setup time for input to clock

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

4.5

4.75

5

5.5

I
I

Low

25

.20

High

25

20

45

35

I

Polarity fuse intact

50

40

Polarity fuse blown

50

40

tsup

Preload setup time

30

th

Hold time

0

thp

Preload hold time

10

5

TA

Operating free-air temperature

-55

0

Tc .•...

Operating case temperature

5

5.25

ns
ns
ns
-10

0

125

V
ns

25
-10

UNIT

ns
ns
75

.

DC
·C

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL*

Low-level input voltage

VIH*

High-level input voltage

Vic

Input clamp voltage

TEST CONDITION

MIN TYP MAX

V

-1.5

V

2
Vee = MIN

II = -1SmA

UNIT

O.S

V
-0~13

IlL

Low-level input current

VCC= MAX

VI = 0.4 V

-0.02 -0.25

IIH

High-level input current

VCC=MAX

VI = 2.4 V

25

p.A

II

Maximum input current

Vce= MAX

VI = 5.5 V

1

mA

VOL

Low-level output voltage

Vec= MIN

VOH

High-level output voltage

VCC = MIN

Off-state output current

Vee = MAX

lOS

Output short-circuit current**

Vec= MAX

ICC

Supply current

VeC = MAX

10ZL

MIL

10L = SmA

COM

10L = SmA

MIL

10H = -2mA.

COM

10H= -3.2mA

10ZH

0.3

2.4

0.5

2.S

mA

V

V

Vo = 0.4 V

-100

Vo = 2.4V

100

/lA

-70 -130

rnA

280

mA

Vo =OV

-30

200

p.A

Switching Characteristics Over OperatIng Conditions
SYMBOL
.tpD

MILITARY
MIN.TYP MAX

COMMERCIAL
MIN TYP MAX

Polarity fuse intact

50

Polarity fuse blown

55

40
45

ns

30

25

ns

25

20 I ns

25

20

PARAMETER
Input to output

I

I

tCLK

Clock to output or feedback

tpzx

Output enable

tpxz

Output disable

fMAX

Ma~imum

frequency

TEST
CONDITIONS

R1 = 5600
R2=1.1KO
14

16

UNIT

ns
MHz

PAL 64R32
HAL PARAMETERS MAY DIFFER. CONTACT FACTORY FOR DETAILS.

Operating Conditions
SYMBOL

MILITARY
MIN TYP MAX

PARAMETER

Vee

Supply voltage

tw

Width of clock

tsu

Setup time for input to clock

th

Hold time

4.5
low
High
Polarity fuse intact
Polarity fuse blown

TA

Operating free-air temperature
Operating case temperature

5.5

4.75

5

5.25

UNIT

V

25

20

ns

50

40

ns

0

Te

5

COMMERCIAL
MIN TYP MAX

-10

0

-55

-10

0

ns
.75

De
De

125

Electrical Characteristics Over Operating Conditions
SYMBOL

MIN TYP MAX

TEST CONDITION

PARAMETER

O.B

UNIT

V

Vll*

low-level input voltage

VIH*

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

II = -1BmA

-O.B

III

low-level input current

Vee = MAX

VI = 0.4 V

-0.02 -0.25

IIH

High-level input current

Vee = MAX

VI = 2.4 V

25

p.A

II

Maximum input current

Vee = MAX

VI = 5.5V

1

mA

VOL

low-level output voltage

Vee = MIN

VOH

High-level output voltage

Vee = MIN

Off-state output current

Vee=MAX

lOS

Output short-circuit current**

Vee= MAX

lee

Supply current

Vee = MAX

IOZl

2

Mil

IOL = BmA

eOM

IOL = BmA

Mil

IOH = ~.4mA

COM

IOH = ~.4mA

10ZH

..

V

0.3

2.4

-1.5

0.5

2.B

V
mA

V

V

Vo = 0.4 V

-100

p.A

Vo = 2.4V

100

p.A

-40

--M

mA

400

640

mA

-10

Vo =OV

Switching Characteristics Over Operating Conditions
SYMBOL

tpD

PARAMETER

I nput to output

MILITARY.
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

55

50

60

55

I Polarity fuse intact
I Polarity fuse blown

teLK

elock to output or feedback

tpzx

Output enable

tpxz

Output disable

tpRH

Preset to output

fMAX

Maximum frequency

5-381

TEST
CONDITIONS

R1 = 5600
R2 =1.1 KH

ns

30

22

ns

35

30

ns

:30

ns

351
40
12.5

UNIT

35
16

20

ns
MHz

PAL64R32

HAL PARAMETERS MAY DIFFER. CONTACT FACTORY FOR DETAILS.

Testing Conditions
SYMBOL

PARAMETER

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

UNIT

twp

Preload pulse width

45

35

ns

tsup

Preload setup time

60

50

ns

thp

Preload hold time

10

5

ns

tpRW

Preset pulse width

30

25

ns

tpRR

Preset recovery time

40

35

ns

Monolithic

W Memories

5·39

PAL/HAL
Switching Waveforms
INPUTS 1/0
REGISTEREO
FEEDBACK

CK

L ",

ASYNCHRONOUS
PRESET

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r-----~----rrnm

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h

31

7

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6

11

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4581

B 91011

11131415

, .. nUll

2.0212~2:J

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28213031

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11

5·45

PAL/HAL Logic Diagram
10L8
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2 3

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••

1213

1611

2021

2425

21291031

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0
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~

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PAL/HAL Logic Diagram

12L8
01 Z:J

1

2

4561

89

1213

1617

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24252621

28293031

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5-47

PAL/HAL Logic Diagram
14L4
012 1

1

...

2

...

456

891011

1213

1611

20212223

24252627

28293031

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r

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PAL/HAL Logic Diagram
18L2

1

2

3

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45 Ii 7

8911111

12131415

16171819

20212223

242:'2627

28293031

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5·49

PAL/HAL Logic Diagram

iSLa
0123

4581

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191"1

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11

PAL/HAL Logic Diagram
18R8
1

,

012 J

4 S 6 1

8 9 1011

12131415

16171819

20212223

24252621

28293031

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1
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PAL/HAL Logic Diagram
20RA10
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,

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78

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PAL/HAL Logic Diagram

20$10

, .....
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··
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a

1

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12131415

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5-75

PAL/HAL Logic Diagram
20RS4

1

....

....

0123

4567

891011

12131415

16'171819

20212223

24252ti27

2829331

32333435

363138311

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5
6

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11

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15
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IB

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13

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20

30
31

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39

35
36

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Q

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PAL/HAL Logic Diagram
20RS8

' .....
.....

D 123

4517

891DII

t!IS1415

11171

20212223

2421521V

,
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5·77

PAL/HAL Logic Diagram
20RS10

, ....

...

Q 123

4587

881011

1213141

1111

20212223

24

1

3

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PAL/HAL Logic Diag~am
32R16

(18) (17) (16)
16 NC 15

(15) (14) (13) (12)(11)(10) (9)
14 13 12 11 10 9
8

~

(19) 17

(20) 18

(21) 19

(22)20

.cr:--

r:--

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r:--

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84 PIN LCC
(88 PGA)

(7)
6

****vcc* ***

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7

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1

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1

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1

J.

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37 (41)

(28)NC

40 PIN DIP
(44 PIN LCC)

~ ~

~ ~

ffGNDf f
26 27 28 29 30 31 32 33 34
(29) (30) (31) (32)(33)(34) (35) (36) (37)

MonOllthlcW Memories

~

r

35 NC 36
(38) (39) (40)

5·79

PAL/HAL Logic Diagram
84 PIN LCC
(88 PGA)

64R32
(121 (11)(101 (91
HC
II 10 9
(13112 -,-------, ,,[,
(14113

m

(81
(6J (51 (41 (3J (2J (II (881(871(861(85118411831(821(811
8 7 654 3 2 I M M ~ m ~ N mn

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m 75

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VCC-'74 (771
,------------,-73 (78J
72(751

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71 (741

(16115

70(731

(17116
(18117

68(711

(111118
(201 19

68(8111

(21120

85(681

(22121

M(87I

AND
ARRAY
32K
FUSES

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62(851

(25124

III (831

(26125

(27126

(ZIII27

58(811

129128
56(5111

tJll29
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5·80

HC
(341

33 34
(3511361

35 36 37 38 39 4041 42 43 44 45 46 47 48 49 50
~~~~~~~~~~~~~~~~

~

51 52 53

(53J (54) (551

MC
(56J

PAL/HAL

Programmer/Development System
VENDOR

PAL20RA10

PAL24RS

Data 1/0

-Logic PAK
(32R16 only)

Kontron

-

-

-

Structured
Design

-

-

Stag
Varix

*

MegaPAL

Omni
Programmer

Valley Data
Sciences

-

Storey Systems

-

Digelec

-

-Logic PAK

-

-

-Logic PAK

PAL20

PAL24

PAL24A

-Logic PAK

-Logic PAK

-Logic PAK

-EEP80*
PAL Adapter

-EEP80
PAL Adapter

-EEP80
PAL Adapter

-

-SO 1000

-SO 1000

-SO 1000

-ZL30

-ZL30

-ZL30

-Omni*
Programmer

-Omni
Programmer

-Omni
Programmer

-

-Model 160

-Model 160

-Model 160

-

-P240*

-P240

-P240

-

·UP803*

-UP803

-UP803

Except 16P8A, 16RP8A, 16RP6A, 16RP4A

The above chart represents those units which, at the time of printing, have been submitted to Monolithic Memories for evaluation
and have demonstrated the capability to satisfactorily program the indicated devices.

Die Configuration
PAL20RA10

5·81

PAL/HAL
Die Configurations

PAL32R16

PAL64R32

K

5·82

C 5 L
ell

v

c

C

K

L 5
4 4

MonolithicW Memories

System Building Blocks/HMSpM ~

6·1

6·2

Monolithic WMemories

Table of Contents
SYSTEM BUILDING BLOCKSIHMSI™
Contents for Section 6 ............................... 6-3
System Building Blocks/HMSI Selection Guide ......... 6-3
SN54/74LS461 8-Bit Counter ........................ 6-4
SN54174LS469 8-Bit Up/Down Counter .............. 6-8
SN54/74LS498 8-Bit Shift Hegister .................. 6-12
SN54/74LS380 Multifunction 8-Bit Register .......... 6-16
SN54/74LS491 10-Bit Counter ...................... 6-20
SN54/74LS450 16:1 Mux ........................... 6-24
SN54/74LS451 Dual 8:1 Mux ....................... 6-28
SN54/74LS453 Quad 4:1 Mux ...................... 6-32
SN54174LS460 10-Bit Comparator .................. 6-36

System Building Blocks/HMSI Selection Guide
FUNCTION

PART NUMBER

8-Bit Counter

SN54174LS461

8-Bit Up/Down Counter

SN5417 4LS469

8-Bit Shift Register

SN54174LS498

Multifunction 8-Bit Register

SN54/74LS380

1d~Bit Counter

SN54174LS491

16:1 Mux

SN54/74LS450

Dua18:1 Mux

SN54/74LS451

Quad 4:1 Mux

SN54174LS453

10-Bit Comparator

SN54174LS460

1/IIonoI1th/c

W Memo,.les

6·3

a-Bit Counter
SN54/74LS461
Ordering Information

Features/Benefits
• 8-bit counter for microprogram-counter, OMA-controller
and general-purpose counting applications
• 8 bits match byte boundaries
• Bus-structured pinout

PACKAGE

PART NUMBER
SN54LS461

JS,F

SN74LS461

NS, JS

TEMPERATURE

12BL

I

Logic Symbol

• 24-pln SKINNYOIP® saves space
• Three-state outputs drive bus lines
• Low-current PNP inputs reduce loading
• Expandable in 8-bit increments

Description
The 'LS461 is an B-bit synchronous counter with parallel load,
clear, and hold capability, Two function select inputs (10, 11)
provide one of four operations which occur synchronously on
the rising edge of the clock (CK),
The LOAD operation loads the inputs 1(07-00) into the output
register (07-00). The CLEAR operation resets the output
register to all LOWs. The HOLD operation holds the previous
value regardless of clock transitions. The INCREMENT operation adds one to the output register when the carry-in input is
TRUE (CI = LOW), otherwise the operation is a HOLD. The
carry-out (CO) is TRUE (CO = LOW) when the output register
(07"00) is all HIGHs, otherwise FALSE (CO = HIGH).

DATA
IN

Die Configuration
Die Size: 140x172 mil 2

The data output pins are enabled when OE is LOW, and disabled
(HI-Z) when OE is HIGH. The output drivers will sink the 24 mA
required for many bus interlace standards.
Two or more 'LS461 B-bit counters may be cascaded to provide
larger counters. The operation codes were chosen such that
when 11 is HIGH, 10 may be used to select between LOAD and
INCREMENT as in a program counter (JUMP/INCREMENT).

Function Table

*

OE

CK

H
L
L
L
L
L

*
t
t
t
t
t

11

*

L
L
H
H
H

10

*
L
H
L
H
H

CI

07-00

*

*
X
X
0
X
X

X
X
X
H
L

07-00

OPERATION

HI-Z*
Z
L
CLEAR
0
HOLD
0
LOAD
HOLD
0
Oplus1 INCREMENT

DE

When
is HIGH, the three-state outputs are disabled lathe high-impedance
states; however, sequential operation of the counter is not affected.

SKINNYDIP@ is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592. Tel: (408) 970-9700 TWX: 910-338-2374

6·4

MIL
COM

SN54/74LS461
Logic Diagram
8-Bit Counter

~Wllllemories

6·5

SN54/74LS461
Absolute Maximum Ratings
Supply voltage vee ...................................................... ......................................... 7 V
Input voltage ................................................................................................... 5.5 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Storage temperature ................................................................................... -65° to +150° e

Operating Conditions
PARAMETER

SYMBOL

vce

Supply voltage

TA

Operating free-air temperature

tw

I
I

Width of clock

MILITARY
MIN TYP MAX

COMMERCIAL
UNIT
MIN TYP MAX

4.5

4.75

Low

-55
40

High

30

tsu

Setup time

60

th

Hold time

0

5.5

5

5

125* 0

5.25

V

75

°C

35
25

ns

50
-15

ns

0

-15

MIN

TyptMAX UNIT

.. Case temperature

Electrical Characteristics
SYMBOL

TEST CONDITIONS

low-level input voltage

Vil
VIH
VIC
III
IIH
II

High-level input voltage
Input clamp voltage
low-level input current
High-level input current
Maximum input current

Val

low-level output voltage

VOH

10Zl
10ZH
lOS
ICC

Over Operating Conditions

PARAMETER

O.S

-

2

Vee = MIN
Vee - MAX
Vee - MAX
Vee - MAX
Vee = MIN
VIL = O.SV
VIH = 2V

II = '-1SmA
VI - O.4V
VI = 2.4V
VI - 5.5V

Vee - MIN
Vil = O.SV
VIH = 2V

High-level output voltage

MIL

10l

COM

10l

Mil

10H

COM

10H

= MAX
Vil = O.SV
VIH =2V
Vee - 5.0V

Vee
Off-state output current
Output short-circuit current
Supply current

*

Vce

-1.5
0.25
25
1

= 12mA
= 24m A
= -2mA
=-3.2mA

Va
Va

= 0.4V
= 2.4V

Va

= OV

0.5

/i A
mA

V

V

2.4

-100
100
-30

= MAX

V
V
V
mA

120

/i A
/i A

-130

mA

1S0

mA

* No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
t All typical values are at vee = 5V, TA = 25°C
Switching Characteristics

telK
tpD
tpzx
tpxz

TEST CONDITIONS
(See Test Load)

PARAMETER

SYMBOL
fMAX
tpD

Over Operating Conditions

R2
390n

= 50 pF
= 2000
= 3900

el
R1
R2

b.,t-l--e
-=

*

TEST POINT*

MonoIIthlO

m"'.merles

TYP

MAX

35
95
55

35
20
55
35

50
30
SO
45

55

35

45

60

The "Test Point" is driven by the outputs under test,
and observed by instrUmentation.

50pF

6·6

35
20
55
35
35

Rl
200n

~5V

COMMERCIAL
MIN
12.5

10.5

Maximum clock frequency
el to CO delay
Clock to Q
Clock to CO
Output enable delay
Output disable delay

Test Load

MILITARY
typ MAX

MIN

UNIT
MHz
ns
ns
ns
ns
ns

SN54/74LS461
Application

16-Bit Counter

BUS OUT ENABLE
COUNT ENABLE

INSTR

{

CK
10
11

16-BIT
DATA BUS
IN

rrr~~
IT---, I r-~

tS-BIT
DATA BUS
OUT

CI
~
12. -DO10::'..
CK OOr-~

r.:"

D1

Ot-

~

-D2
'5
L.;;,

02-

i20I
~

r'4
L.;;. -

8

D3 BIT 0 3 - ~
~
CNTR
D4
04t--

'6 -

~

rw

a.l. -

~

rs -~
..2.

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~

os

OSt--

~

-D6

OSt--

';&I

'iii -

Drt

~
~

rw

OEC~7t-- ~

.... ~1L- ~

Iji

m

~
~

CARRY

--(I

.....---.. ,----.
~

IT~ I r-lm10 v CI
~
~ -DO CK OO-~

r.:"
..

:I

-Dt

Ot-iE

3: ~D2

02-~

IT -

D3

.r:'

B~T

03 -

tr!:

':::I

CNTR

..?. -

D4

04t--.l!..

rs I--

DS

OSt--

L.;;.

'9
r..;. I-- os

...

rut
~

osl-- ~
~

ITo I-- °rtOEc%71-- ~
~
-fi'i
.... ~·IL-

m

NOTE:fMAX=

m-,...
~

ALL HIGH

t

tpD ClK TO CO+ tsu

MonolIthic

W Memories

6·7

8-Blt Up/Down Counter
SN54/74LS469
Ordering Information

Features/Benefits
• 8-b" up/down counter for microprogram-counter, OMAcontroller and general-purpose counting applications
• 8 bits match byte boundaries
• Bus-structured pinout

PART NUMBER

.TEMPERATURE

PACKAQE

SN54LS469

JS,F

SN74LS469

NS,JS

128L

MIL

I

COM

Logic Symbol

• 24-pln SKINNYOII'® saves space
• Three-state outputs drive bus lines
• Low-current PNP Inputs reduce loading

23

• Expandable In 8-b" Increments

Ciii CARRY/BORROW
IN

Description
The 'LS469 is an 8-bit synchronous up/down counter. with
parallel load and hold capability. Three function-select inputs
(LD, UD, CBI) provide one of four operations which occur synchronously on the riSing edge of the clock (CK).
The LOAD operation loads the inputs (D7-DO) into the output
register (07-QO). The HOLD operation holds the previous value
regardless of clock transitions. The INCREMENT operation
adds one to the output register when the carry-in input is TRUE
(CBI = LOW), and the up/down control line {UD~OW, otherwise the operation is a HOLD. The carry-out (CBO) is TRUE
(CBO = LOW) when the output register (07-QO) is all HIGHs,
otherwise FALSE (CBO = HIGH). The DECREMENT operation
subtracts one from the output register when the borrow-in input
is TRUE (CBI = LOW), and the up/down control line (UD) is
HIGH, otherwise the operation is a HOLD. The borrow--4

I'----'-+--+--+--I::i- DOLD c"KC[ROO
~
I'--..,.--+--+--+--I.!
- D1
Q1
1'----+--+--+--117 - D2
Q2
::;
8
1'----+--+--+--11 - D3 BIT Q3
1.:0
REG
I'----:-+---+--+--I:i - D4
Q4

!mi·-+--+-+-----'I
1:::11
~I,,--1--+--1r-----1

1'----+--+--+--118
- OS
1.:0

as

~
•.:.·-+-If--+----/I
joOoioI

1'-----'-+--+--+--1.. ,... DB

as

:; _
I'-----+--+--+--I~.

D7...A7
~L~M

1ziI.·--_t_-1I---'-+-----:.... 1

b:

E191--+-11--+----.... 1

~.-_t_-1r---+-----:....1
ii'1~-+-Ir--+---..,.-.... 1
;
~.--t--Ir--+-----

::E ---.J[ L-.,!!:

fi!

....I

~I-··-+·-II-~

6-19

1 O-Sit Counter
SN54/74LS491
Ordering Information

Features/Benefits
• CRT vertical and horizontal timing generation

PART NUMBER

PACKAGE

• Bus-structured pinout

SN54LS491

JS,F

• 24-pln SKINNYDII'@> saves space

SN74LS491

NS, JS

• Three-state outputs drive bus lines

TEMPERATURE

128L

I

Logic Symbol

• Low-current PNP inputs reduce loading

DATA
IN

Description
The'LS491 is a 10-bit up/down counter with set, load and hold
capabilities for two LSB, two MSB and six middle bits that are
HIGH or LOW as a group. Five control inputs (SET, LD, CNT,
CIN and UP) provide one of five operations which occur synchronously on the rising edge of the clock (CK).
The SET operation sets the output register (09-00) to all HIGHs.
The LOAD operation loads the inputs (09-00) into the register.
When COUNT or CARRY IN are not asserted (00 = HIGH or
CIN = HIGH), the HOLD operation holds the previous value
regardless of clock transitions. The COUNT UP operation adds'
one to the output of the register when the count up input is
asserted (UP = LOW). The COUNT DOWN operation subtracts
one from the output register when the count up input is not
asserted (UP = HIGH). SET overrides both LOAD and COUNT,
LOAD overrides COUNT, and COUNT is conditional on CARRY
IN.

DATA
DUT

Die Configuration

The data output pins are enabled when OE is LOW, and disabled
(HI-Z) when OE is HIGH. The 24 mA IOL outputs are suitable for
driving RAM/PROM address lines in video graphics systems.

Function Table
OE

*

CK

SET LD

H

*

L

I

*
H

L
L

I

L

I

L

L

I

L

L

I

L

L

I

L

*
X
L
H
H
H
H

CNT CIN
*
X
X
H
L
L
L

*
X
X
X
H
L
L

UP
*
X
X
X
X
L
H

D9-DO

*
X
D
X
X
X
X

Q9-QO

OPERATION

z

HI-Z*
SET all HIGH
LOAD D
. HOLD

H
D
'0

0

o plus 1
o miJ1us 1

HOLD

COUNT UP
COUNT ON

When OE is HIGH, the three-state outputs are disabled to the high-Impedan.ce
states; however, sequential operation of the counter is not af~ected.

SKINNYDIP" Is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
21.75 Mission college Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-11700 TWX: 9.10-338-2374

6·20

MIL
COM

Ole Size: 14011172 mll2

SN54/74LS491
Logic Diagram

10-Bit Up/Down Counter

1/IIo_lithlc

W Memories.

6-21

SN54/74LS491
Absolute Maximum Ratings
Supply voltage vee ....... '" .. . . .. . . . . .. . . . . .. . . ... . . . . . . .. . . . . . ... . ... . .. . . . .. . . .. . . .. ... . . ... • .. . . . .. . . ... . .. 7'.0 V
Input voltage ...............•..........................•..........•...........................••••..........•... 5.5 V
Off-state output voltage .......................................................................................... 5.5 V
Storage temperature ..................................................•••.....•.....•...............•.• _65· to +150·e

Operating Conditions
PARAMETER

SYMBOL
Vee
TA
tw

Supply voltage
Operating free-air temperature

MILITARY
MIN TYP MAX

COMMERCIAL
UNIT
MIN TYP MAX

4.5

4.75
0

I High

Width of clock

5

-55

I Low

5.5
125'

40

40

35

35

tsu

Setup time

60

th

Hold time

0

5

5.25
75

ns

50
-15

0

V
·e

ns

-15

" case temperature

Electrical Characteristics

Over Operating Conditions

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYPt MAX UNIT

Low-level input voltage

VIL
VIH
VIC
IlL
IIH
II

High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current

VOL

Low-level output voltage

VOH

High-level output voltage

0.8
-1.5
0.25
25
1

V
V
V
mA
p.A
mA

0.5

V

2
Vee
Vee
Vee
Vee
Vee

=
=
=
=

II
VI
VI
VI

MIN
MAX
MAX
MAX
MIN
0.8V
2V

VIL
VIH
Vee - MIN
VIL = O.BV
VIH = 2V

10ZL

Off-state output current

10ZH
lOS
ICC

Output short-circuit current

*

Supply current

-

-18mA
O.4V
2.4V
5.5V

MIL

10L = 12mA

COM

10L = 24mA

MIL

10H = -2mA

COM

10H = -3.2mA

Vee - MAX
VIL = 0.8V
VIH = 2V
Vee = 5.0V
MAX
Vee

Vo
Vo

= 0.4V
= 2.4V

Vo

- OV

V

2.4

-30
120

-100
100

p.A
p.A

-130
180

mA
mA

* No more than one output should be shorted at a time and duration of the short- circuit should not exceed one second.

t All typical values are at VCC =SV. TA

= 2SoC

•

Switching Characteristics
PARAMETER

SYMBOL
fMAX

Maximum clock frequency

teLK

Clock to Q

tpzx

Output enable delay

tpxz

Output disable delay

Over Operating Conditions
TEST CONDITIONS
(See Test Load,)
eL = 50pF
Rl = 2000
R2 = 3900

MILITARY
MIN TYP MAX

COMMERCIAL
UNIT
MIN TYP MAX

10.5

12.5

35

20

30

ns

35

55

35

45

ns

35

55

35

45

ns

Test Load
*

MHz

20

The "Test Point" is driven by the outputs under test.
and observed by instrumentation.

SNS4/74LS491
Application
Video Horizontal Timing and Blanking
OOT
CLOCK

La~~vcc
-II
~I--"""f""------------'
DO

CK

--ij f- 01
-[! f- 02-7

QO

01

......!:.'s:!-

Lf! .... -

tm-~I---+-"""f""-----------1f---I-rr

02:E

::!

-1'5 t- D8
03:m
~;;

'4
::;:
.!

L!. r- 09
_

100BIT Q4

~

_COUNTER
:....-LO
OS:!Ii

L-_-+-I-G: f~f-~

:l

Q6:m

r;

Lr;jjp

07E

I'

-

~
~

08

~1----+--+-+++-r-+-+~----1---I.!

09

E

IE

-I.:,

~

r--m:

SET

mi

~

__

~

4

l.I

il

vcc

El-VBLANk

~ ~SCAN
DO

AND
DR
GATE
ARRAY

~

rw

-po-

r!!-

~"'J ~

BLANK

iiMAX(ii:1)

... - '-ii7. ;>0. ~VHBLANK

~ ~~

~

rw
~

~

~

~

-<30

tEl- ~

HO HI H2 H3 H4 H5 H6 H7 till HI!
HORIZQNTAL ADORESS

Timing Analysis;
Path 1 - Outpu" of 74LS491 setting up at PAL18R4A Inpu"
tpDCK-Ofl4LS491 + tSUPAL16R4A
'" 3Ons+25ns

=55 ns
Path

~...,:

Outpu" of PAL18R4A ..~n, up at 741.84,t1Inpu"
tPDCK-O/PAL16A + tSU741-,S491

= 25n5+50ns
'" 75 ns
Accordingly, the worst-casellmlng 01 the two pathsi. 75 ns, which results In a maximum video dot clock Irequency 0113.33 MHz. Strict interpretation 01 the 60 Hz field
rate NTSC Stand!lrd .ugge~ts that up to 52.11'59C 01 time is avaUable lor active-raster-line duration. In practice however, most CAT monitors overscan the screen to
correct horizontal sweep nonlinearitie.s. Asa consequence, the horlZQntal blanking time is increased, and the active video time decreased, typically to about 40 "sec.
For the application cireui! shown. above, over 512110," (pixels) for one line can be displayed:

4.0 ;.tsec per line

;, 533 pixels

75 ns per pixel per line
Normall'y, at least a 10-bi! coun!er is required to provide 8 video timing chain for such resolutions. The 74LS491, combined with a high-speed PAL (PAL16A4A) is
capable of generating a completesetof video timing signals. Note thatin thaapplication circuit, t!Jemaximum horizontal count [H MAX (n-l)] is decoded one clock
early, due to the Hevel pipeUni~~ use~ toobt.ain circuit speed.

6-23

16:1 Mux
SN54/74LS450
Ordering Information

Featuresl Benefits
• 24-pin SKINNYDIP® saves space
• Similar to 74150 (Fat DIP)
• Low-current PNP inputs reduce loading

PACKAGE

PART NUMBER
SN54LS450

JS,F

SN74LS450

NS, JS

128L

I

Logic Symbol
Description
The 16:1 Mux selects one of sixteen inputs, EO through E15,
specified by four binary select inputs, A, B, C and D. The true
data is output on Y and the inverted data on W. Propagation
delays are the same for both inputs and addresses and are
specified for 50 pP"loading. Outputs conform to the standard
8 mA LS totem-pole drive standard.

Function Table
INPUT
SELECT

OUTPUT

W Y

0

C

B

A

L

L

L

L

EO

EO

L

L

L

H

E1

E1

L

L

H

L

L

L

H

H

L

H

L

L

E2 E2
E3 E3
54 E4

L

H

L

H

E5

E5

L

H

H

L

E6
E8

L

H

H

H

E6
E7

H

L

L

L

Ea

H

L

L

H

E9 E9

H

L

H

L

E10

H

L

H

H

E11

E11

H

H

L

L

E12

E12

H

H

E13

E13

H

L
H

H

H

L

E14

E14

H

H

H

H

ill

E15

Die Configuration
Die Size: 140x131 mll 2

E7

E10

SKINNYOIP® is a registered trademark of Monolithic Memories.

TWX: 910-338-;;!376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

6·24

TEMPERATURE
MIL
COM

SN54/74LS450
Logic Diagram
16:1 Mux

6·25

SN54/74LS450
Absolute Maximum Ratings
Supply voltage vee ......................•....................•...............•...................•............• 7.0 V
Input voltage .................••................•.......•....•......................•........................... 5.5 V
Off-state output voltage .......•....................•..•.••.••.............................•....••....•.........•• 5.5 V
Storage temperature ................................................................................... _65° to +1500 e

Operating Conditions
MILITARY

PARAMETER

SYMBOL

COMMERCIAL

MIN NOM MAX

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

5

5.5
125"

MIN
4.75

NOM MAX
5

0

.UNIT

5.25

V

75

°e

• case temperature

Electrical Characteristics
PARAMETER

SYMBOL

TEST' CONDITIONS

MIN

TYPtMAX UNIT

LOW-level input voltage

0.8

VIL
VIH
VIC
IlL
IIH
II

High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current

VOL

Low-level output voltage

VOH

High-level output voltage

lOS
ICC

Over Operating Conditions

Output short-circuit current
Supply current

-1.5
0.25
25
1

V
V
V
mA
p.A
mA

0.5

V

2
Vec = MIN
VCC - MAX
Vec = MAX
Vee = MAX
Vee = MIN
Vil = 0.8V
VIH = 2V

II - -18mA
VI - 0.4V
VI = 2.4V
VI - 5.5V
10l =8mA

Vee = MIN
VIL = 0.8V
VIH = 2V

*

MIL

10H = -2mA

COM

10H

Vee = 5.OV
Vee = MAX.

Vo

=-3.2mA

V

2.4
-30

- OV

-130

60

100

mA
mA

• No more than one output should b$ st)orted at a time and duration of t~e short· circutt should not exceed one second.

t AlitypicalvaluesareatVCC =5V,TA = 25°C

Switching Characteristics
SYMBOL

tpD

Over Operating CondHions
TlST CONDITIONS

PARAMETER

(SHTest Load)
eL = 50pF
R1 = 5600
R2 " 1.1kO

Any input to Y or W

MILITARY
MIN

COMMERCIAL

TVP

MAX

25

45

MIN

TVP

MAX

25

40

Test Load

R2

Rt

'I::

.

. ' . TESTW
POINT"

'::' .5Opf

6·26

*

The "Test POint" Is driven by the outputs under test,
and obserVed by instrumentation.

UNIT

ns

SN54/74LS450
Application

Test Condition Mux

TEST { : : - - - - - - - - - - ,
SELECT
21 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,

2°-----------------------------------------,

TEST

°

TEST 1
TEST 2
TEST 3
TEST 4
TEST 5

TEST

TEST 6

TEsT

TEST 7
TEST 8
TEST 9
TEST 10
TEST 11
<

TEST 12
TEST 13
TEST 14
TEST 15

Monolithic

W"'emorles

6-27

Dual 8:1 Mux
SN54/74LS451
Ordering Information

Features/Benefits
• 24-pin SKINNYDIP® saves space

PACKAGE

PART NUMBER

• Twice the density of 74LS151
• Low-current PNP inputs reduce loading

SN54LS451

JS, F

SN74LS451

NS, JS

128L

I

Logic Symbol

Description
The Dual 8:1 Mux selects one of eight inputs, DO through D7,
specified by three binary select inputs, A, Band C. The true data
is output on Y when strobed by S. Propagation delays are the
same for inputs, addresses and strobes and are specified for
50 pF loading. Outputs conform to the standard 8 mA LS totempole drive standard.

Die Configuration

Function Table

Die Size: 140x131 mil2

INPUTS

OUTPUTS
STROBE

SELECT

Y

C

B

A

S

X

x

X

H

H

L

L

L

L

DO

L

L

H

L

D1

L

H

L

L

D2

L

H

H

L

D3

H

L

L

L

D4

H

L

H

L

D5

H

H

L

L

D6

H

H

H

L

D7

SKINNYDIP® is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

6-28

TEMPERATURE
MIL
COM

SN54/74LS451
Logic Diagram
Dual 8:1 Mux

8-29

SN54/74LS451
Absolute Maximum Ratings
Supply voltage Vee ........................................... , ............................•.................... 7.0V
Input voltage ................................................•.................................................. 5.5 V
Off-state output voltage .............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Storage temperature ...•.....................•......... : .......•............•.......................... -650 to+150oe

Operating Conditions
SYMBOL

MILITARY
MIN 'NOM MAX

PARAMETER

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

5

5.5
125-

COMMERCIAL
MIN NOM MAX
4.75

5

UNIT

5.25

V

75

°e

0

Case temperature

Electrical Characteristics.
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYPt MAX UNIT

Low-level input voltage

Vil
VIH
VIC
III
IIH
II

High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current

Val

Low-level output voltage

VOH

High-level output voltage

lOS
Ice

Over Operating Conditions

O.S
-1.5
0.25
25
1

V
V
V
mA
p.A
mA

0.5

V

2
Vee
Vee
Vec
Vee
Vce

:=
=
=

MIN
MAX
MAX
MAX
MIN
O.SV
2V

II
VI
VI
VI

VIL
VIH
Vec - MIN
V il = O.SV
VIH = 2V

=
.,

IOl = SmA
MIL

IOH = -2mA

COM

IOH = -3.2mA

2.4

Vcc. - 5.OV
MAX
Vee

Output short-drcuit current*
Supply current

-1SmA
OAV
2AV
5.5V

Va

- OV

V

-30

-130
60

100

mA
mA

* No more than one output should be sflorte"d'a(a time and duration of the short· circuit should not exceed one second.
t All typical values are at Vee =5V, T A =25'<:

Switching Characteristics

TEST CONDITIONS

PARAMETER

SYMBOL

tpD

Over Operating Conditions

(See Test Load)
eL = 50pF
R1 = 560n
R2 = 1.1kfi

Any input to Y
\

.. '

MILITARY
MIN

COMMERCIAL

TYPMAX
25

.

45

MIN

TYP

MAX

25

40

Test Load
R2

R1

~5V
J:--l~TEST POINT"
-:SOpF

6-30

*

The "Test Point" is d'fiven by the outputs under test,
and observed by instrumentation.

UNIT

ns

SN54/74LS451
Application

4-Bit Wide 8:1 Bus Multiplexer
BUS
SELECT

IN
BUS
ABCOEFGH

20
BIT 0

:r

-

I"!'

BIT 0
BIT 0
..

,...--..-

BIT 0

100

BIT 0

:::r t-- 102

B

:! t--

C

{!f--

103

BIT 0
BIT 1
BIT 1

~ t-- 201

BIT 1

Ij'j f--

....

:m
t- :m
t-

S-

105

:::r t-- 106
:! f-- 107
::! t-- 200

BIT 0

II'

~

1YI--

~

BIT 0

2Y I--

~

BIT 1

2071--~.

~
205 I-- ~
206 I--

202 204 I-203

~

~

m

BIT 1

~

A t- ~

::It-- 104

,
BUS
OUT
22 STROBE BUS

1:::1

..! t-- 10.1

BIT 0

21

BIT 1
BIT 1
BIT 1
BIT 1

::i ~IEl

BIT 2
BIT 2

100

I"'!'

..! f--

101

:] t--

102

B I--

::! t--

103

C I--

BIT 2

!] t--

104

BIT 2

::!

BIT 2

BIT 2
BIT 2

t--105

107
200

2061--

~

201

2051--

~

::! I--

-m I-'ii I-....

m

BIT~

SI--~
1Y I-- ~

rw

{! I--

BIT 3

~

:E

I-"
2071--~.

BIT 3
BIT 3

1::'1
tll-

2Y I--

11
... I--

106

BIT 2

..

AI--

BIT 2
BIT 3

202 204t--~
203

~

BIT 3·

..

B1T 3
BIT 3

...

BIT.3

. MonoIIthIt:

W Memories

6·31

Quad 4:1 Mux
SN54/74LS453
Featuresl Benefits
• 24-pln SKINNYDIf>® saves space
• Twice the density of 74LS153
• Low-current PNP inputs reduce loading

Ordering Information
PART NUMBER

PACKAGE

SN54LS453

JS. F

SN74LS453

NS. JS

TEMPERATURE

128L

MIL

I

COM

Logic Symbol

Description
The Quad 4:1 Mux selects one of four inputs. CO through C3.
specified by two binary select inputs. A and B. The true data is
output on Y. Propagation delays are the sallie for inputs and
addresses and are specified for 50 pF loading. Outputs conform
to the standard 8 rnA LS totem-pole drive standard.

Die Configuration
Die Size: 140x131 mll 2
3CO

2C3 2C2 2C1 2CO

Function Table
INPUT
SELECT
B

OUTPUTS
Y

A

L

L

CO

L

H

C1

H

L

C2

H

H

C3

SKINNYDIP" is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

6-32

1C3

SN54/74LS453
Logic Diagram
Quad 4:1 Mux

lIIIonoIithic

W Memories

6·33

SN54J'74LS453
Absolute Maximum Ratings
Supply voltage vee ............................................................................................. 7.0 V
Input voltage ...............................................................•................................... 5.5 V
Off-state output voltage .....................................................................•.............•...... 5.5 V
Storage temperature ................................................................................... _65· to +150·e

Operating Conditions
MILITARY

PARAMETER

SYMBOL

MIN

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

COMMERCIAL

NOM MAX
5

5.5
125'

MIN
4.75

NOM MAX
5

0

UNIT

5.25

V

75

·e

Case temperature

Electrical Characteristics
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYPt MAX UNIT

Low-level input voltage

VIL
VIH
Vie
IlL
IIH
II

High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current

VOL

Low-level output voltage

VOH

High-level output voltage

lOS
lec

OVer Operating Conditions

Output short-circuit current
Supply current

-1.5
0.25
25
1

V
V
V
mA
p.A
mA

0.5

V

O.B
2
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=

VIL
VIH
Vee VIL =
VIH =
Vee Vce =

*

MIN
MAX
MAX
MAX
MIN
0.8V
2V

II
VI
VI
VI

MIN
O.BV
2V
5.0V
MAX

-

-18mA
O.4V
2.4V
5.5V
10L = BmA

MIL

10H = -2mA

eOM

10H = -3.2mA

2.4
Vo

- OV

V

-30

-130

60

100

mA
mA

* No more than one output should be shorted at a time and duration of the short circuit should not exce8d one second.
t All typical values are atVcc =5V. T A

= 25°C

Switching Characteristics

TEST CONDITIONS

PARAMETER

SYMBOL

tpD

Over Operating Conditions

MIN

CL = 50pF
R1 = 5600
R2 = 1.1kO

Any input to Y

COMMERCIAL

MILITARY

(See Test Load)

TYP

MAX

25

45

MIN

TYP

MAX

25

40

Test Load
R2
1.1M

R1
5601l

~5V

J:-1~TEST POINT'
.". 50pF

6-34

*

The "Test POint" is driven by the outputs under test,
and observed by instrumentation.

UNIT

ns

4SN54/74LS453
Application
8-Bit Wide 4:1 Bus Multiplexer

IN

BUS

o

C

B

BUS
SELECT
2 0 21

A

BITO
BITO
BITO
BITO
BIT 1
BIT1
BITl
BITl
BIT2
BIT2
BIT2

r:"~1EJ
..!.
24
~
lCO
1=1
a.l f - lCl
A I-- ~
~r-1C2
B'--~
~1--1C3 4C3-~
~I-- 2CO 1Y-~
(!:I--

2Y-~

2Cl

~ I-- 2C2

cr
cr

OUT

BUS

BIT

a

BIT 1

3Y I--

tID-

BIT 2

2C3

4Y I--

;TIl

BIT 3

I-- 3CO

4C2 I--

~

I--

ffi I-- 3Cl

4Cl

r--

;m

El-I~

Iii
I-- 3C23C34CO ....

m
BIT2
BIT3
BIT3
BIT3
BIT3

BIT4
BIT4
BIT4
BIT4
BITS
BITS
BITS
BITS
BIT6

IT -- - El
lCl

r"] -

lC2

BI--

ii'
.;;;,t

&.!

lC3

4C3 I--

ijI

2CO

lY I--

2C1

2Y

~

BIT 5

2C2

3Y

--

201

BIT 4

.;;;,t

~

BIT 6

2C3

4Y

-

~

BIT 7

~-'5 ~
L! '7 -

::;&.! r; ~

BIT6
BIT 6

BIT 6

lCO

'2
~

3CO

ffi I-- 3Cl

23'

A I-- .:0::.1

4C2

.;;..;J

~
~

~

- ~
~

~
Iii
I-- 3C23C34CO I-- ~
....

m

4Cl I--

~

BIT 7
BIT 7
BIT 7
BIT 7

IIIIonoilthlo

IRE] Memories

6·35

1 O-Bit Comparator
SN54/74LS460
Ordering Information

Features/ Benefits
• True and complement comparison status outputs
• 24-pin SKINNYDIP® saves space
• Low-current PNP inputs reduce loading

PART NUMBER

PACKAGE

SN54LS460

JS, F

SN74LS460

NS, JS

TEMP

i28L

1

• Expandable in 10-bit increments

MIL
COM

Logic Symbol

• Useful for address decoding

Description
The 'LS460 is a 10-bit comparator with true and complement
com parison status outputs. The device compares two 10-bit
data strings (A9-AO and B9-BO) to establish if this data is
Equivalent (EO = HIGH and NE = LOW) or Not Equivalent (EO =
LOW and NE = HIGH).
Outputs conform to the usual 8-mA LS totem-pole drive
standard.

19

GND

NE }COMPARISON
EO
STATUS

--a._ _ _- - r -

Die Configuration
Die size: 140 x 131 mil

Function Table
INPUTS

OUTPUTS

(A9-AO) * ,(B9-BO) * EQ

OPERATION
NE

(A9-AO) = (B9-BO)

1

0

Bit strings equivalent

(A9-AO) t (B9-BO)

0

1

Bit strings not equivalent

*

The parentheses ( ... ) denotea 10-bit string from either InputAor B, as given

by the symbols within the parentheses.

SKINNYDlp® is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

6·36

Monolithic l!T!n
Memories uun.u

SN54/74LS460
Logic Diagram
10-Bit Comparator

IWonoIIINoWMemories

6-37

SN54/74LS460
Absolute Maximum Ratings
Supply voltage vee ............................................................................................. 7.0 V
Input voltage ................................................................................................... 5.5 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Storage temperature .....................•.................•........................................... _65° to +150o e

Operating Conditions
MILITARY

PARAMETER

SYMBOL

MIN

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

COMMERCIAL.

NOM MAX
5

5.5

MIN
4.75

NOM MAX
5

125" O'

UNIT

5.25

V

75

°e

• case temperature

Electrical Characteristics
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYPt MAX UNIT

Low-level inPut voltage

0.8

VIL
VIH
VIC
IlL
IIH
II

High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current

VOL

Low-level output voltage

VOH

High-level output voltage

lOS
lee

OVer Operating Conditions

-1.5
0.25
25
1

V
V
V
mA
p.A
mA

0.5

V

2
Vee
Vee
Vee
Vee
Vee

Output short-circuit current
Supply current

*

= MIN
= MAX
= MAX
= MAX
- MIN
= 0.8V
= 2V

VIL
VIH
Vee VIL =
VIH =
Vee Vee =

II
VI
VI
VI

MIN
0.8V
2V
5.0V
MAX

-

-18mA
O.4V
2.4V
5.5V
10L =8mA

MIL

10H = -2mA

eOM

10H = -3.2mA
Vo

= OV

2.4

V

-30

-130

60

100

mA
mA

* No more than one output should be shorted at a time and duration of the short· circuit should not exceed one second.
t

All typical values are at

Vee = 5V. T A

= 25"C

Switching Characteristics

TEST CONDITIONS

PARAMETER

SYMBOL

tpD

Over Operating Conditions

(See Test Load')
eL = 50 pF
R1 = 5600
R2 = 1.1kO

Any input to EQ or NE

MILITARY
MIN

COMMERCIAL

TYP

MAX

25

45

MIN

TYP

MAX

25

40

Test Load

Ra

R1

~sv

J:---1.,.t-4
':' 50pF

6·38

TEST POINT"

*

The "Test Point" is d6~n by the outputs under test,
and observed by.instrumentation.

UNIT

ns

SN54/74LS460
Application

10-Bit Up Counter/Down Counter Comparator

+5V

UP COUNTER

'LS491
.--

0: r----=l
riI r-

CK

00 CK 00 ' -

COUNT

-

~ t--

01

01 -

~ I--

02-7

02 -

:ill

-:E

09 BIT 04

....
t-- .!!I

""iI t-- 10
---II f-----< D5

os I-- .!!I

~f----< CN'f

OS

6

CNTR

7

t-(I f-----< UP
~ I--

~

m-I-

03

~I-- os

SET

a-

illJ-

r-m

....

07

L.!.~24

3
t-- :ill

I--

as I--

SET

+5V



:

"':\~~~
.... : - - : ; - _ _ _

~e.

~

_

~

,.

"A L.ESS OBVIOUS BUT INTUESTING APPL.ICATlON'OFFIF05 IS AS
AUTOMATIC 'BUS-WATCHE~S' ... "

References
(1) "First In First Out Memorles ..,:Operations and Applications," applications
note 'pub'lished fIiIarch 1978 by Monolithic Memories Inc. and being

reissued. '

"

,

(2) "Understanding FIFO's," applications note published by Monolithic
Memories Inc. The.author. Alan Weissberger, has also gotten a modified
version of this note' published as a magazine article, "FIFOs Eliminate the
Delay when Data Rates Differ," in Electronio Design, November 27. 1981,
Qespite the g~nera!' title, the emphasis is on digitaLcQfJlmuni"cations
applications.
'"
, (3) "PROMs, PALs, FIFps and Multipliers Team Up ,.to Implement Sing I...
Board High-Performance Audio Spectrum., Analyzer," applicaUons note
published by Monolithic Memorieslnc.TheauthOr. Richard Wm. Blasco.
also got this nole published in Electronic Design in two instaliments. in the
issues of,August 20 and September 3. l~l~nder the titles "PAL Shrinks
Audio 'Spectrum AnalYzer" and'''P'At improves Spectrum Analyzer Per- '

formance" respectively.

Asynchronous First-In Fiia-st-Out Memory
(FIFO) .16x5
74S225/A
Featu.res/ Benefits

Orderi"g ·I"formatio"

• OC to,20-MHz shift-Inlshift-out .rates

PACKAGE

, TEMPERATURE

74S225

J, N

10 MHz Com

74S225A

J,N

20 MHz Com

PART NUMBER '.

• Fully expandable by word width and depth
• Three-state outpuIS
• 'TTL-compatlble Inputs and outputs
.

• Functionally compatible with T.I. SN74S225
• Deslgmid for exlended.l~tabili'y

Descriptio"
Tt)e 74S225/A is a SCllottky-clamped transistor-transistor logic
(S'TTL) 16x5 First-In-First-Out memory (FIFO) which operates
from DC to 10/20 MHz. The data is loaded and emptied on a

first-in-first-out basis through asynchronousiilput and output
ports. These devices are used in digital systems performing data
transfers when source and receiver are not operating at the
same data rate. FIFOs are also used as data buffers where the
source and receiver are not operating at the same time. Both
word length and FIFO depth are expandable. Unload clock
output (Pin 3) is designed for testability of VOL'

Pi" Names
PIN #

PIN NAME

DESCRIPTION

1

CLKA

Load clock A .

2

IR

Input ready

UNCKOUT

Unload clock output

DO-04

Data inputs

3
4-8
9

OE

Output enable

10

GND

Ground pin

04-00

Data outputs

11-15

Pi" Co"figuration
74S225/A •• J or N Package
(Top View)

c·

UNCKOUT

3
OR

01

16

UNCLKIN

Unload clock input

17

OR

Output ready

18

CLR

Clear

19

CLKB

Load clock B

20

VCC

Supply voltage'

DATA'.

02

01

03

D4

BloCk Diagram

}.~~.

9 OUTPUT ENABLE

DO

4

01
02
D3
D4

5
8
7
8

15

INPut
STAGE

16x5
REGISTER

FIFO
OUTPUT
STAGE

--,~----i-=:::--:-"l

UNLOAD CLOCK OUT
INPUT READY
LOAD CLOCK A 1
LOAD CLOCK B 19

....,=----'--1

~~1~8

00 .

14
FIFO

01
02
03
04

13
12
11

0'16

.UNLOAD
CLOCK IN

17

~~~T

_ _~~_ _~_ _~_ _ _ _~______~_~

".

'!!I!!2m

M•.O.'lHJ
.o
.-.-.-

TWX:.910-338-2376
.2175 MIssIon College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9.700 TWX: 910-338-2374 . "

7·8

74S225/A
Absolute Maximum Ratings

Tnu:~i~:,~~~;e.~~~.:::::::::::::: ::::::::::::: :::::::::::::::::: ::::::::::: ::::::::::::::::::::::::::::::: =~:; ~!~~ ~

. Ott-state output voltage ............ ; .................................................. : .................. -0.5 V to 5.5V
Storage temperature ....................................................................•. , ............. -65 to +150°C

Operating Conditions
SYMBOL

PARAMETER

745225
MIN TYP MAX

FIGURE

VCC

SUpply voltage

4.75

tA

Operating. tree-air temperature

0

5.25
75

745225A
MIN TYP MAX
4.75

UNIT

5.25

V

0

75

°c

36

ns

tlCKH

lOAD GLOCK pulse width, A or B, tw (HIGH)

2

25

22

tlDS

Setup time, data to load clock

2

-201*

-201*

ns

tlDH

Hold time, data trom load clock

2

701

501

ns

tUCKl

UNLOAD CLOCK INPUT pulse width, tw (lOW)

4

7

tClW

CLEAR pulse width, tw (low)

tClCK

Setup time, clear release to load clock, tsu

'.

7

36

ns

·2

40

20

ns

2

251

10

ns

745225
MIN TYP .MAX

74522SA
MIN TYP MAX

UNIT

10

20

MHz

* D,ata must be setup within 20 ns 'after valid Load Clock (A or B) pulse (positive transition).
t ::: .Arrow indicates that it is referenced to the a-high trai1~ition.

Switching Characteristics' Over Operating CondItions
5,(M~OL

PARAMETER

I
I

load clock A or clock B

tiN
tlCIRl

ClK A or ClK B to IRI **

tlCCOl

ClKA or ClK B to UNCK

FIGURE

Cascade Mode**
2

Standalone Mode

20

22

2

55

75

43

55

ns

oun

2

25

50

31

40

ns

I
I

4

Cascade Mode***

MHz

tUCKORl

UNCK.IN 1 to OR lOW

4

30

45

26

35

ns

tUCKORH

UNCK IN 1 to OR HIGH

4

40

60

32

45

ns

tODH

Output data hold, UNCK IN tooutputdata

75

tODS

4.:
4

50

Output data setup, UNCI< IN to output data

50

75

i

tRIP

elK A or ClK B to OR

tClOl

ClR to OR I

tCLIH

ClRto IRI

tUCKOW

Pulse width, UNCK pUT, tw

,

tORD

OR I to output data

tBUBI

UNCK

tBUBC

UNCK IN to UNCK OUT I (bubble-back time) '.'

,

.'

30

300 ,.

ns

39
41

55

ns

7

190

167'

220

ns

6

35

60

31

40

ns

6

16

35·

15

20

ns

2

14

7
.'

7

ns

11

10

20

9

15

ns

8

255

400

214

290

ns

8

270

400

226

290

ns

4

ItJ to IR 1 (bubble-back time)

20

22

Unload clock input

Standalone Mode

10

20

tOUT

.l 'Arrow indicates that it is referenceCJ to the high-ta-Iow transition .

. **

16th word only

* **

Devices connected to provide FIFO of greater than '16 word depth.

. . .

7-9

74S225/A
Switching Characteristics
SYMBOL
tpHZ

Over Operating Conditions

PARAMETER

FIGURE

74S225
MIN TYP MAX

Output disable delay, OE to ai, CL

= 5 pF

1

10

25

Output enable delay, OE to ai, CL

= 5 pF

1

25

40

74S225A
MIN TYP MAX

tpLZ
tpZL
tpZH

Test Load for Bi-State Output

8

25

18

25

19

40

23

40

Test Load for Three-State Output

TEST POINT" vcc

•

TEST POINT"

•

RL
OUTPUT o--t----!~-;

OUTPUT

51

0--t----.,.-114----.,
1KO

CL=30pF
RL= 3000

CL = 5 pF
RL = 300n
" The "TEST POINT" is driven by the output under test,
and observed by instrumentation.

Input Pulse Amplitude = 3.0 V
Input Rise and Fall Time (15%-90%) = 2.5 ns
Measurements made at 1.5 V

3V
OUTPUT ENABLE

VT
OV
_tpZL
_ _ _ 1.5 V
0.5 V
VOL

DATA OUTPUT
WAVEFORM 1

DATA OUTPUT
WAVEFORM 2

VOH
0.5 V
-1.5V

S10PEN
S2CLOSED

51 AND
S2CL05ED

Figure 1. Enable and Disable
'vVaveform 1 is for an output with internal conditions such that the output is
low except when disabled.
Waveform 2 is for an output with internal conditions such that the output is high
except when disabled.

7-10

Monolithic WMeinorles

UNIT
ns

ns

74S225/A
Electrical Characteristics
SYMBOL

PARAMETER

Vil

low-level input voltage

VIH

High-level input voltage

VIC

Input clamp voltage

11L1
IIl2

Over Operating Conditions

low-level
input current

I
J

MIN TYP MAX

TEST CONDITIONS

UNIT

O.B

V

2.0
VCC =MIN

00- 0 4

VCC = MAX

V

-1.5

II = -1BmA
VI = 0.5 V

All others

IIH

High-level input current

VCC = MAX

VI = 2.7V

II

Maximum input current

VCC = MAX

VI=5.5V

,

VOL

low-level output voltage

VOH

High-level output voltage

lOS

Output short-circuit current"

I

1

mA

-.25

mA

Data inputs

40

Others

25

/.LA

1

10l = 16 mA (Data outputs)
VCC = MIN

V

-1

mA

0.5

V

10l = B mA (All others)
10H = -6.5 mA (Data outputs)

'HZ

Off-state output current

IlZ
ICC

*
**

Supply current

VCC = MIN
VCC = MAX

V

2.4
10H = -3.2 mA (All others)
-100

-30

Vo =OV

VCC = MAX

Vo = 2.4 V

50

VCC = MAX

VO=0.5V

-50

VCC = MAX

Inputs low. All
outputs open

l

J

74S225

BO

120

74S225A

BO

125

mA
/.LA
/.LA
mA

To measure VOL on Pin 3, force 10 V on Pin 9 (Extended Testability).
Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

When new valid data is shifted to the output stage, OR goes
HIGH. If the FIFO is emptied, OR stays lOW and Data remains
valid for the last word.

Functional Description
Data Input

After power up the CLEAR is pulsed low (Figure5) to prepare the
FIFO to accept data in the first location. Clear must be applied
prior to use to ensure proper operation. When Input Ready (IR)
is HIGH, the first location is ready to accept data from the Ox
inputs. Data then present atthedata inputs is entered into the first
location when both load Clocks (ClK A and ClK B) are brought
HIGH. The ClK A HIGH and ClK B HIGH signal causes the IR
and UNCK OUTto pulse lOW. Once data is entered into the first
cell. the transfer of data from any full cell to the adjacent (downstream) empty cell is automatic. activated by an on-chip control.
Thus data will stack up at the end of the device while empty
locations will "bubble"to the front. tRIP defines the time required
for the first data to travel from input to the output of a previously
empty device. When the sixteenth word is clocked into the
device. the memory is full (sixteen warps) and IR remains low.
The Unload Clock Output is provided chiefly for use in cascading
devices to extend FIFO depth (Figure 9). When Input Ready is
low. do not attempt to shift-in new data.
Data Output

Data is read from the Ox outputs. When data is shifted to the
output stage. Output Ready (OR) goes HIGH. indicating the
presence of valid data. When the OR is HIGH, data may be
shifted out by bringing the Unload Clock Input.{UNCK IN) lOIN.
A lOWsignal at UNCK IN causes the ORto go lOIN. \/alid data is
maintained while the UNCK IN is lOIN. When UNCK INis
brought HIGH the upstream data. provided that stage has valid
data, is shifted to the output stage.

Input Ready and Output Ready may also be used as status
signals indicating that the FIFO is completely full (Input Ready
stays lOW for at least tBUBI) or completely empty (Output
Ready stays lOW for at least tRIP).

AC Test and High·Speed App. Notes
Since the FIFO is a high-speed device, care must be exercised in
the design of the hardware and the timing utilized within the PC
board design. Device grounding and decoupling is crucial to
correct operation as the FIFO will respond to very small glitches
due to long reflective lines. high capacitances and/or poor
supply decoupling and grounding. We recommend a monolithic ceramic capacitor of 0.1 /.LF directly between VCCand GND
with very short lead length. In addition. care must be exercised in
how the timing is set up and how the parameters are measured.
For example. sincean AND gate function is associated with both
the load Clocks (A. B) - Unload Clock Output-Input Ready
combination. as well as the Unload Clock Input-Output Ready
combination. timing measurements may be misleading. i.e .• rising edge of the load Clock pulse is not recognized until Input
Ready is HIGH. If Input Ready is not high due to (a) too high a
frequency. or (b) FIFO being full or affected by (ClR). the
lOAD-CK activity will be ignored. This will affecUhe device
from a functional standpoint. and will also cause the "effective"
timing of Input Data Hold time (tIDH) and the next activity of
Input Ready (tlCIRLl to be extended relative to load Clock (A or
B) going HIGH.

Monollthlo WMemorles

7·11

74S22S/A
LOAD CLOCK
(BORA)

LOAD CLOCK'
(A ORB):

INPUT READY

UNLOAD' _ _ _ _ _!-....,.
CLOCK:
OUTPUT·

INPUT DATA
ICLCK-+-;"--'

INITIAL CYCLE ONLY

NOTES: 1. Permissible negative setup time for input data
2, Measure tLCIRL for 16th input word only

Figure 2. Input Timing

LOAD CLOCK
(BORA)

\~-----

/

---'

LOAD CLOCK
(A OR B)

INPUT READY

\

14)

~------~=---------------------

UNLOAD
CLOCK OUTPUT

INPUT

DATA~o----STABLE DATA----o

'-_ _ __

NOTES: 1. Input Ready HIGH indicates space is available and a Load Clock (A and B) pulse may be applied:
2. ,Input Data is loaded into the first word.
3. Unload Clock Output pulses indicating the first word is full and the Data from the first word is released for "fall-through" to
second word.
4. If the second word is already full, then the data remains at the first word. Since the FIFO is now full. Input Ready remains LOW.

Figure 3. The Mechanism of Clocking Data Into the FIFO

7·12

Monolithic

[F.ilI Memories

74S225/A

UNLOAD
CLOCK INPUT

OUTPUT DATA

Figure 4; Output Timing

UNLOAD
CLOCK INPUT

OUTPUT READY

NOTES: 1. Output Ready HIGH Indicates that data Is avallable and an Unload CJqck Input pulse may be appli$d.
2. Unload Clock Input goes LOW creating an empty position at word 16 for word 15to 'Yall-Ihrough" to,
3. Output Ready goes LOW.
4. Unload Clock Input goa. HIGH, causing Output Ready to go HIGH, indicating that new data (B) is now available at the FIFO outputs.
5. If t~. FIFO ·has only one word load$d (A-DATA), then Output Ready stays LOW and the A-DATA remains on the outputs.
NOTE: Assume FIFO Initially contains at leasi two words.

Figure 5. The Mechanism of Shifting Data Out of the FIFO

7-13

74S225/A

_~I"}.

LOAD CLOCK
(A AND B)

tCLCK

NOTE: Assume FIFO is full before CLEAR goes active.

Figure 6. Clear Timing
LOAD CLOCK
(A OR B)

LOAD C L O C K - 0.________________________
(BOR~

t R I P _ I ,_ _ _ _ __
OUTPUTREADY__________________

-"~
/HIGH

UNLOAD CLOCK
INPUT
NOTES: 1. FIFO is initially empty.
2. Unload Clock Input and one Load Clock held HIGH throughout.

Figure 7. tRIP Specifications
UNLOAD CLOCK
.
INPUT
_IBUBIINPUT READY

UNLOAD CLOCK
OUTPUT
/HIGH
LOAD CLOCK
(A and B)

NOTES: 1. FIFO is initially full.
2. Load Clock (A and B) held HIGH throughout.

Figure 8. tSUSI. tSUBC Specifications

7-14

Monolithic

W Memories

748225/A

VCCCLOCK IN

--

NC

~c~

LD
CKe

g:lfut
IA
DO
0.1
D2
D3
0.4 CLA

CLEAA

A~:~10 BITS
DATA IN

ro:

DA

vee ~~
I---"- pocfa
",""D

r-- CKOOT
III .
QO
r-- DII
..01 r-- Dt
02 I---"- 0.2
Q3 r-- 0.3
aeQ4 r-- 0.4 CLA
UNLE! •
CKIN

NC.~

t::"1

.

vec I"1.D
C~
.Lo.
OA
CKe
.UNlD
~. I--- CKOUt CkIN
IA.
QO f - - 00
QO
Q1 f - - D1
Q1
Q2 I--- 0.2
02
03 I--- D3
.
03,
OA

I--- I"

UhLD

-

Oi

04

f--

D4 CLA

~

.

.. .

vec _ I",LD CLII ill!'
V6e Iii'IoD ~Ocl
vee pLD Ct.A OE
.
CKA··
.
.~.
.
CKA
LD
Oil ~
OA f--p LD
011 tCKB(!KB
CKII
UNLo.
UNlo.
1Jf!IJ' UNLD
UN1.D UNLD
CKOUT CK";'
~ CKiN'I--- CKout CKIN I--

~

r-NC'"

III

1ft

00

GO f-=-: .bQ.

0.1
0.2

Q1 --'-

02 r-- D2

D3
D4

Q3 '---"- DS
04.
Q4

-

01

.

NC- IR

QO

r-

QO
Q1
Q2
QS
Q4

DO
01 I--- 0.1
Q21--Q31--- 0.3
041--- D4

..

Figure 9. 48x10 FIFO with 54/7482251A

Metal Mask Layout of the 748225/A

'OUTPUT"
AEADY.·
UNLOAD
CLDCK

0104

PU>

NC

--

rU"-:

1O'BITS
DATA OUt

First-In First-Out (FIFO) 64x4 64x5
Cascadable Memory
C5/67401 C5/67401A C67401B
C5/67402 C5/67402A C67402B
Ordering Information

Features/Benefits
• Choice of 16,7, 15 and 10 MHz shift-out/shift-in rates
• Choice of 4-blt or 5-bit data width
• TTL inputs and outputs

PART
NUMBER

PKG

TEMP

C57401

J,w(20)(L)

Mil

7 MHz

64x4

FIFO

10 MHz

64x4

FIFO

7 MHz

64x5

FIFO

Com

10 MHz 64x5

FIFO

J,W(20)(L)

Mil

10 MHz 64x4

FIFO

C67401A

J,N

Com

15 MHz 64x4

FIFO

C57402A

J,W(20)(L)

Mil

10 MHz

64x5

FIFO

C67402A

J,N

Com

15 MHz

64x5

FIFO

C67401B

J

Com

16.7 MHz 64x4 FIFO

C67402B

J

Com

16.7 MHz 64x5 FI FO

• Readily expandable in the word and bit dimensions

C67401

J,N

Com

• Structured pinouts, Output pins directly opposite corresponding input pins

C57402

J,W(20)(L)

Mil

C67402

J,N

• Asynchronous operation
• Pin-compatible with Fairchild's F3341 MOS FIFO and many
times faster

Description
The C5/C67401 B/2B/1A12A11/2 are "fall-through" high speed
First-In First-Out (FIFO) memory organized 64 words by 4 bits
and 64 words by 5 bits respectively. A 16.7 MHz data rate allows
usage in digital video systems; a 15 MHz data rate ailows usage
in high speed tape or disc controllers and communications buffer
applications. Both word length and FIFO depth are expandable.

DESCRIPTION

C57401A

Block Diagrams
C57401/A 64x4
C67401A1B 64x4

C57402lA 64x5
C67402AlB 64x5
00
0,
02
03

SHIFT

OUT

,.

OUTPUT"
READY

DO

INPUT
READY

SHIFT
IN

00
0,
02
03
O.

SHIFT

OUT
OUTPUT

READY

Pin Configurations

INPUT READY

2

SHIFT IN

3

00

4

1

OATAIN :

03

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

7·16

Monolithic ~1!n
Memories uun.u

C67401 B/2B Cascadable
Absolute Maximum Ratings
Supply voltage vee ....................................................................................... -0.5 V to 7 V
Input voltage .................................•........................................................... -1.5 V to 7 V
Off-state output voltage ... . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 5.5 V
Storage temperature ................................................................................... _65° to +150° e

Operating Conditions C67401 B/2B
PARAMETER

SYMBOL

FIGURE

COMMERCIAL
MIN
TYP
MAX

Vee

Supply voltage

4.75

TA

Operating free-air temperature

0

.5

UNIT

5.25

V

75

°e

tSIHt

Shift in HIGH time

1

18

ns

tSIL

Shift in LOW time

1

18

ns

tlDS

Input data setup

1

0

ns

tlDH

Input data hold time

1

40

ns

tSOHt

Shift Out HIGH time

5

18

ns

tSOL

Shift Out LOW time

5

18

ns

tMRW

Master Reset pulse

10

35

ns

tMRS

Master Reset to SI

10

35

ns

* Case temperature.

Switching Characteristics C67401B/2B
Over Operating Conditions
SYMBOL

PARAMETER

FIGURE

MIN

COMMERCIAL
MAX
TYP

UNIT

fiN

Shift in rate

1

tlRL

Shift In to Input Ready LOW

1

35

tlRHt

Shift In to Input Ready HIGH

1

37

fOUT

Shift Out rate

5

tORLt

Shift Out to Output Ready LOW

5

38

ns

tORHt

Shift Out to Output Ready HIGH

5

46

ns

tODH

Output Data Hold (previous word)

5

taos

Output Data Shift (next word)

5

44

tpT

Data throughput or "fall through"

4,8

1.3

jJ.S

tMRORL

Master Reset to OR LOW

10

55

ns

tMRIRH

Master Reset to IR HIGH

10

55

ns

tIPH*

Input Ready pulse HIGH

4

20

ns

Output Ready pulse HIGH

8

20

ns

~ tOPH*

16.7

MHz

16.7

ns
ns
MHz

5

ns
ns

tsee AC test and High Speed application note.

*This parameter applies to FIFOs communicating with each other in a cascaded mode.

WIonoIHhlc WMemOrles

7-17

CS/C67401 A/2A Cascadable

Absolute Maximum Ratings
Supply voltage vee ....................................................................................... -0.5 V to 7 V
Input voltage ............................................................................................. -1.5 V to 7 V
Off-state output voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 5.5 V
Storage temperature ................................................................................... -65° to +1500 e

Operating Conditions CS/C67401 A/2A
FIGURE

PARAMETER

SYMBOL

MILITARY
MIN

TYP

5

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

MAX

5.5
*125

COMMERCIAL
MIN
MAX
TYP

4.75

5

5.25
75

0

UNIT

V
°e

tSIHt

Shift in HIGH time

1

35

23

ns

tSIL

Shift in LOW time

1

35

25

ns

lIDS

Input data setup

1

0

0

ns

tlDH

Input data hold time

1

45

40

ns

tSOHt

Shift Out HIGH time

5

35

23

ns

tSOL

Shift Out LOW time

5

35

25

ns

tMRW

Master Reset pulse

10

40

35

ns

tMRS

Master Reset to S I

10

45

35

ns

*Case temperature

Switching Characteristics CS/C67401 A/2A
Over Operating Conditions
SYMBOL

PARAMETER

FIGURE

MIN

MILITARY
TYP
MAX

COMMERCIAL
MIN
TYP
MAX

UNIT

fiN

Shift in rate

1

tlRL t

Shift In to Input Ready LOW

1

50

40

ns

tlRHt

Shift In to Input Ready HIGH

1

50

40

ns

fOUT

Shift Out rate

5

tORL t

Shift Out to Output Ready LOW

5

65

45

ns

tORHt

Shift Out to Output Ready HIGH

5

65

50

ns

tODH

Output Data Hold (previous word)

5

to OS

Output Data Shift (next word)

5

60

45

ns

10

15

MHz

15

10

10

MHz

10

ns

tpT

Data throughput or "fall through"

4, 8

2.2

1.6

tMRORL

Master Reset to OR LOW

10

65

60

"s
ns

tMRIRH

Master Reset to IR HIGH

10

65

60

ns

tIPH*

Input Ready pulse HIGH

4

30

30

ns

tOPH*

Output Ready pulse HIGH

8

30

30

ns

t See AC test and High Speed application note.

* This parameter applies to FIFOs communicating with each other in a cascaded mode.

7·18

IIIIonollthlc

m

lIIIemorles

CS/C67401/2 Cascadable

Absolute Maximum Ratings
Supply voltage vee .......................................................................... '" ............ -0.5 V to·7 V
Input voltage ..........................•......•.................................•.•....•.•..•... ; .....•... -1.5 V to 7V
Off-state output voltage .. . . .. . . .. . • . . . . . . . . .. . .. . .. • .. . .. • . .. . .. . .. .. • • . .. .. . . .. . . . . . . . . . . . . ... .. ... .. . .. -0.5 V to 5.5 V
Storage temperature ......................................................................... : ......... '.' -65. to +1500e

Operating Conditions CS/C67401/2
PARAMETER

SYMBOL

FIGURE

.COMMERCIAL
MIN
TYP
MAX

MILITARY
TYP
MAX

MIN

4.5

vee

Supply voltage

TA

Operating free-air temperature

tSIHt

Shift in HIGH time

1

45

35

r'lS

tSIL

Shift in lOW time

1

45

35

os

tlDS

Input data setup

1

0

0

ns

tlDH

Input data hold time

1

55

45

ns

5

-55

5.5

4.75

UNIT

5

5.25

V

75

··e

0

*125

tSOHt

Shift Out HIGH time

5

45

35

ns

tSOl

Shift Out lOW time

5

45

35

ns

tMRW

Master Reset pulse

10

30

35

ns

tMRS

Master Reset to SI

10

45

35

ns

*Case temperature.

SWitching CharacteristicsCS/C6740.1/2
Over Operating Conditions
SYMBOL

PARAMETER

FIGURE

COMMERCIAL
MIN
MAX.

MILITARY
MAX
TYP

MIN

UNIT

TYP

fiN

Shift in rate

1

tlRl t

Shift In to Input Ready lOW

1

60

45

tlRHt

Shift In to Input Ready HIGH

1

60

,45

fOUT

Shift Out rate

5

tORlt

Shift Out to Output Ready lOW

5

65

55

tORHt

Shift Out to Output Ready HIGH

5

70

60

tODH

Output Data Hold ,(previous word)

5

tODS

Output Data Shift (next word)

5

7

10

7

.'

,

nS
ns
MHz

10

10

MH:z

ns
ns ...

10

ns
ns

55

65

tpT

Data throughput or "fall thro)Jgh:'

4,8

4

3

J,lS

tMR,ORl

Master Reset to OR lOW

10

65

60

ns

tMRIRH

Master Reset to. IR HI~H

10

65

60

tIPH*

Input Ready pulse HIGH

4

. 30

30

tOPH*

Output Ready pulse HIGH

8

30

30

n$'
ns

"

.

ns

t See AC test and High Speed application note,

*This parameter applies to FI~Os communicating with each other in a cascaded mode.
Test Load
Input Pulse 0 to 3'11:

5V

.. .'c
5100

~ The ''TlOin. POINT" is driven by the output under test,
anq observed by instrumentation.

'.'

.'

."

f ; J .

1.1KO

30pF

'

TEST POINT*

,(~O%.

,

InputRiS.,eand.FaUTi.me
..
,-5!Q%)
2:-5nS.
".,j,
M~ure.ments made at 1.5 V
,
"

','

.'

7·19

I'

C5/C67401 BI A/2B/2A/1/2 Cascadable
Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

TEST CONDITIONS

VIL

Low-level input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

11L1
IIL2

Low-level
input current

IIH

High-level input current

II

Maximum input current

VCC

VOL

Low-level output voltage

VCC - MIN

VOH

High-level output voltage

lOS

Output short-circuit current

II

VCC

= MAX

VI

= O.4SV

VCC

= MAX
= MAX

VI

- 2.4V

VI

= S.SV
= 8mA
= -0.9mA
= OV

ISI,SO

VCC

*

= -18mA

Vee - MIN

Vce

Vce
ICC

UNIT

0.8t

V

-1.S

V

-0.8

mA

-1.6

mA

2t

100-04' MR

Supply current

MIN TYP MAX

= MIN
= MAX
= MAX

Inputs low.
outputs open

10L
10H
Vo

V

SO

p.A

1

mA

2.4
-20

V

160

CS/67402

180
170
190

C67401B
C67402B

mA

-90

CS/67401
CS/67401A
CS/67402A

V

O.S

lTlA

180
200

-

*Not more than one output should be shorted at a time and duration of the short Circuit should not exceed one secon d.
tThere are absolute voltage with respect to device GND (Pin 8 or 9) and includes all overshoots due to test equipment

Functional Description
Data Input
After power up the Master Reset is pulsed low (Fig. 10) to
prepare the FIFO to accept data in the first location. When Input
Ready (JR) is HIGH the location is ready to accept data from the
Ox inputs. Data then present at the data inputs is entered into
the first location when the Shift In (SI) is brought HIGH. A SI
HIGH signal causes the IR to go LOW. Data remains .at the first
location until SI is brought LOW. When SI is brought LOW and
the FIFO is not full, IR will go HIGH, indicatinij that more room
is available. Simultaneously, data will propagate to the second
location and continue shifting until it reaches the output stage
or a.fuillocation. The first word is present at the outputs before
a shift out is applied. If the memory is full, IR will remain lOW.

Data Transfer
Once data is entered into the second cell, the transfer of any full
cell to the adjacent (downstream) empty cell is automatic,
activated by an on-chip control, Thus data will stack up at the
end of the device while empty locations will "bubble" to the front.
tPT defines the time required for the first data to travel from input
to the output of a previously empty device.

Data Output
Data is read from the Ox outputs. When data is shifted to the
output stage, Output Ready'(OR) goes HIGH, indicating the
presence of valid data. When the OR is HIGH, data may be
shifted out by bringing the Shift Out (SO) HIGH.'A HIGH signal
at SO causes the OR to go LOW. Valid data is maintained while
the SO is HIGH. When sO is brought lOW the upstream data,
provided that stage has valid data, is shifted to the output stage.
When new valid data is'shifted to the output stage, OR goes

7·20

HIGH.IUhe FIFO is emptied, OR stays LOW, and Ox remains
as before, (I.e. data does not change if FIFO is empty). Input
Ready and Output Ready may also be used as status signals
indicating thatthe FIFO iscompletelyfull (Input Ready stays
LOW for at least tPT) or completely empty (Output Ready
stays LOW for at least tPT).

AC Test and High Sp. .d App. Notes
Since the FIFO is a very-high-speed device, care must be
exercised in the design of the hardware and the timing utilized within the design. The internal shift rate of the FIFO
typically exceeds 20 MHz in operation. Device grounding and
decoupling is crucial to correct operation as the FIFO will
respond to very small glitches due to long reflective lines,
high capacitanceand/or poorsupplydecoupling and grounding. We recommend a monolithic ceramic capacitor of 0.1
p.F directly between Vce and GND with very short lead
length. In addition, care must be exercised in how the timing
is set up and how the parameters are measured. For example,
since an AND gate function is associated with both the Shift
In-Input Ready combination, as well as the Shift Out-Output
Ready combination, timing IT)easurements may be misleading, I.e. rising edge of the Shift-In pulse is not recognized
until I nput-Ready is High. If Input-Ready is not high due to
too t- .;;Jh a frequency or FIFO being full or affected by Master
Reset, the Shift-In activity will be ignored. This will affect the
device from a functional standpoint, and will also cause the
"effective" timing of Input Data Time (tIDH) and the next
activity of Input Ready (tlRLl to be extended relative to ShiftIn gOing High. This same type of problem is also related to
tIRH, tORl and tORH as related to Shift-Out.

C5/C67401 A/2A/1 /2, C67401 B/2B Cascadable
1 + - - - - - - - - l / f,N

-------..r.-------1If,N

---~---...,

SHIFT IN
1+---,---tIRH-----;~

INPUTREADY----+-____________--.

INPUT DATA

Figure 1. Input Timing

----------lof-t---------'100ns-----.,.;---+-!

SHIFT IN

INPUT DATA

45n8

Figure 2. Typical Waveforms for 10 MHz Shift In Data Rate

SHIFT IN

CD

INPUTREADY~----------------------t_----~

o

@

,'--_,---________

®

..J------~

INPUT DATA _ _ _ _ _ _ _S_T_A_B_L_E_D_A_T_A______..J

Figure 3. The Mechanism of Shifting Data Into the FIFO

CD

o
o

o

Input Ready HIGH indicates space is available and a Shift In pulse- may 'be applied
Input Data is loaded into the first word.
Input Ready goes LOW indicating the first word

is full.

The Data from the _first word is released for "fall-thrQugh" to second word

@ The Data from the' first word is transferred to second word. The first word is now empty as i~dicated by input Ready HI~H.

®

If the second word,-iS already full then the data remains at 'the first word.

Sjn~e the

FIFO is now full Input Ready remains low,

NOTE: Shift In pulses applied while Input Ready is LOW will be ignored (See Figure 4).

IIIIonoIlthlo Wllllemories

7·21

l

SHIFT OUT

1

.•

SHIFT IN

-.,.-,;. , -,.,. '-' .·~;,-I.~l. . -·IIPH~,-

I,

_ _ _ _ _ __

INPUT READY

-_-_-_-_~-_S_TA_B_L_E-D-/li.-T-'A- -.J~

INPUTD A T A I .
.....

__

.figure 4. Data is Shilled In Whenever ShIft In and Input Ready are Bolit HIGH

oCD

FIFO is initially full.
Shift Out pulaa is applied. An amply location starts "bubtliing" 10 ti1l/ ,rOI11.

(!)Shlft In is held HIGH.

o

®

As. soon as Input Ready becomes ·HIGH the Input Data is iOaded inlo the lirst word· .
fhe Data Irom the lirst word. is released for "fall through." to second word.

!4------1I10UT----..,-..........-----IIIIOUT-------'--.1

SHIFT OUT

OUTPUT RI;ADV.----__j-,-___...;;."""___

C~DATA

o
CD

The diagram assumes. that al this lime. words 63. 62. 61

~rell!adflt'with A. iI. C Oilta. respectively.

Data is shifted out when' Shift Out makes a HIGH 10 LOW traASilidn, .

"

7·22

C5/C67401 A/2A/1/2, C67401 B/2B Caseadable

~----------100n.-------------+

__-----------100n·----------~·~1

SHIFT OUT

OUTPUT REAOY

-----+-t-------,.

C-DATA
OUTPu;rDATA

Figure 6. Typical Wavefonns for 10 MHz Shift Out Data Rate

.0
<

0

The diagram ullumes. that at this time. words 63. 62. 61 are loaded with A. B. C Data. respectively.
Data in the crosshatched region may be A or B Data.

SHIFT OUT

OUTPUT READY

-~-------+--------~

---~----OUTPUT DATA

A-DATA

~

8-DATA

----------------------------------II~'~----------------Figure 7_ The Mechanism of Shifting Data Out of the FIFO.

o
o
o

o

Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied..
Shift Out goes HIGH causing the next step.
Output Ready goes LOW.
Contents of word 62 (B·OATA) is released for "fall lhrpugh" to word 63.

@ Oulput Ready goes HIGH indicating that new data (B) is now available at the FIFO outpuls.

®

"the FIFO has only one word loaded (A-?ATA) then Output Ready stays LOW and the A-DATA remains unchanged at the outputs.
~~"

NOTE: Shift Out pulses applied when Output Ready is LOW will be ignored.

C5/C67401 A/2A/1/2, C67401 B/2B Cascadable

SHIFT IN

SHIFT OUT

OUTPUT READY

o

-,~

___
I ________________

:_··_-_-_-_-_-_-_-_-_-_-_-_-_-_-_~_tP_T~~~~~~~~_-_-_-_-_-_-_-_~~~~PH~~~

FIFO initially empty.

Figure

a.

___________

tPT and tOPH Specification

SHIFT OUT

rllTIITI ITI ITT
IIIIIIIIIIIIII

"""0::--------------..1

OUTPUT READY - -__

~

OUTPUT DATA

______________A_-_DA_T_A________________

J~

Figure 9. Data i8 Shifted Out Whenever Shift Out and Output Ready are Both HIGH.

o
o

CD

o

Word 63 is empty.

o

New data (A) arrives at the outputs (word 63).

Since

Shi~ Out is held HIGH. Output Ready goes immediately LOW.

As soon as Shift Out goes LOW the Output Data is subject to change
as shown by the dashed line on Output Ready.

Output Ready goes HIGH indicating the arrivaf 01 the new data.

,

I---IMRW----'--

MASTER RESET

\

I
J

tMRIRH

INPUT READY

fo

OUTPUT READY

I

,

IMRORL

\

IM_R_S~~~~~~~~~~~;r~'-------------------------

__________________________I_.____________

o

SHIFT IN
FIFO initially full.

7·24

Figure 10. U_ter Reset Timing

C5/C67401 A/2A/1/2, C67401 8/28 Caseadable

INPUT READY

IR

SHIFT IN

SO,

IR

OR

SI

00

Do

0,

0,

02

02

03

03

SHIFT OUT
OUTPUT READY

OR

0,

}
MR

OA"O~

03

MASTER RESET o-----,--'-------~----.J

Figure 11.

Cascading FIFO. to Form 128x4 FIFO with C5IC67401A11

FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the
FIFOs themselves.
'
'

Do

SO
OR
00

-0,

0,

-

IR
51

-- D3
~

iiR

02
03

IR
51

DO
0,
02

Do

0,

0,

0,-

~

02 03 -

00 -

D3 iiii

']'

)'
COMPOSITE

r'""1-

IR
SI

so

so

OR

IR
SI

OR

IR
51

Do

00

Do

00

Do

-0,

0,

0,

0,

~

D2
iiR 03

0,
02

03

'-J-

-

- Da

~

t
SHIFT IN

SHIFT OUT

SO
OR

02

D3 iii Oa

Y

COMPOSITE
INPUT READY

IR
51

SO
OR
00

- Do
-0,
- D2
- Da

02
03

-

T
so

so

-

IR
SI

OR

IR
SI

OR

00

Do

00

Do

OQ

0102
03

0,

0,

0,

0,

02

~

~

ijiiOa

03

02
03

I

,---t.....'

01 02
03

OR

iii

~TPUTREADY

-

D3 iiR

T
so

IR
SI

iiii

00 -

SO
OR

)'

Da iiR

)'

-

M.ASTER RESET

Figure 12. '192x12 FIFO with C5IC67401/1A11B

FIFOs are expandable in depth and width. However,in 'forming wider words two external gates are required to generate composite
Input and Output Ready flags. This need is due to the different fall-through times of the FiFOs.

C5/C67401A/2A/1/2, C67401 B/2B Cascadable

Applications

RESET

NOTE: The output of monostable holds off the "Buffer full" interrupt for
l00nS.1f lOOns aftershift in, there has not been an input Ready to reset
the :'0 Flip-flop" an interrupt is issued, as the FIFO is full. The CPU
then empties the FIFO before the mixt character is output from the
tape drive.

Figure 13. Slow Steady Rate to Fast ''Siocked" Rate

sI--------------~

~---------------SO

---------------1

1---------------. OR

tR

NOTE: Both depth and width expansion can be used in this mode. The IR and
OR signals are-~he anded versions of the in~ividuallR and OR signals.

Figure 14. Bidirectional FIFO Application

7·26

C5/C67401 A/2A/1/1, C67401 8/28 Cascadable
Die Configurations
57401 Die Pattem

Step:G
Die Size: 128x166 ml~

~1182p~~ 1~i!1 ~.~.~
so

03

MR

T

•

.15
·SHIFTOUT

.14
OUTPUT NC
READY

.13 _12
00 .01

1

203
1t

TT

~
~

.3

GNDI

SHIFT IN NC TEST PADS (TYP).oo

Dt

• ••••• 1]1 . . . . . . . . . . . .511 •

~600,.+I ~1SOOI'------I13247!

MR

T

SHIFT OUT

i--736I'-=ij

.16 _t5
OUTPUT 02
READY

t057,.

1

203
1~

ALL PADS £XCIiPT·GNI1 AND Vee
1001' x 1001'
(DIE SIZE 1611 It.128 mils)

TT

(PIN1-NC)

9401'

~

-.-

2

INPUT
-READY

3601'

-L

·~mll/l.morIe.

t1P

J;j",
TWX: 910.-338"2376··,
2175. Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338,-2374

7';'28

. ' .

.••
"""'"'o,m=n
mar,e. ·.1nIW

67401 B/2BStandalone
Absolute Maximum Ratings
Supply:voltageVcc ....................................................................................... -1.5Vt07V
Inpufvoltage ...................•......................................................•.................. -1.5 v' to 7 V
OIl-state output voltage ............................................................................... , .. -0.5 V to 5.5V
Storage temperature ................................................................................... -65° to +150°C,

Operating Conditions 67401 B/2B
PARAMETER

SYMBOL

COMMERCIAL
TYP
MAX
MIN

FIGURE

Vee

SUpply voltage

4.75

TA

Operating Iree-air temperature

0

5

UNIT

5.25

V

75

DC

tSIHt

Shift in. HIGH time

1

18

ns

tSIL

Shift in LOW time

1

18

ns

tlDS

Input-data setup

1

5

nS

tlDH

I nput data hold tline

1.

40

ns

tSOHt

Shift Out HIGH time

5

18

tSOL

Shift Out LOW time

5

18

ns

tMRW·

Master Reset. pulse

10

35

ns

tMRS'

Master Reset to SI

10

35

ns

.

ns

*Case temperature.

Switching Characteristics 674()1 B/2B
Over Operating Conditions
SyMBOL

'j

PARAMETER

FIGURE

liN

Shift in rate

1

tll:IL

Shift In, to input re;ldy LOW

1

tIRH·

Shift In to input ready HIGH

1

lOUT

Sh ift Out rate

5

tORLf

Shift Out to Output Ready LOW

5

tORHt

Shift Out to Output Ready HIGH

5

tODH

Output Data Hold (previous word)

5

tODS

Output Data Shift (next word)

tpT

Data throughput or "Iall through"

tMRORL

Master Reset to OR' LOW

COMMERCIAL'
MIN
TVP
MAX

UNIT

16.7

MHz

'.' tlPH
tOPH

ns

37

ns
MHz

16.7

.

ns

38

.

44
;

5

ns
. ns

5

44

ns

4,8

1.:3

p.S

"

10

55
'"

tMRIRH

35

~5

.

ns

.

ns

Master Reset tolR HIGH

10

Input Ready 'pul~~ HIGH

4

15

ns

8

15

ns

Output Ready pulse HIGH

,.

tSee -"CTest and High Speed Application Note.

7-29

5167401 Al2AStandalone
Absolute Maximum Ratings
Supply voltage vee ....................................................................................... -0.5 V to 7 V
Input voltage ............................................................................................. -1.5 V to 7 V
Off-state output voltage ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 5.5 V
Storage temperature ................................................................................... _65° to +1500 e

Operating Conditions 5167401 A/2A
SYMBOL

PARAMETER

Vee

Su pply voltage

TA

Operating free-air temperature

FIGURE

MILITARY
MIN

4.5

TYP

5

MAX

5.5

COMMERCIAL
MIN
MAX
TYP

4.75
0

5

UNIT

5.25

V

75

°C

tSIHt

Shift in HIGH time

1

-55
35

tSIL

Shift in LOW time

1

35

25

ns

tlDS

Input data setup

1

tlDH

Input data hold time

1

5
45

5
40

ns

*125

23

28t

ns

ns

tSOHt

Shift Out HIGH time

5

35

23

ns

tSOL

Shift Out LOW time

5

35

25

ns

tMRW

Master Reset pulse

10

40

35

ns

tMRS

Master Reset to SI

10

45

35

ns

*Case temperature.

Switching Characteristics 5167401 Al2A
Over Operating Conditions
SYMBOL

PARAMETER

FIGURE

MIN

MILITARY
TYP
MAX

10

COMMERCIAL
MIN
TYP
MAX

UNIT

15

MHz

fiN

Sh ift in rate

1

tlRL t

Shift In to Input Ready LOW

1

tlRHt

Shift In to Input Ready HIGH

1

fOUT

Shift Out rate

5

tORL t

Shift Out to Output Ready LOW

5

65

45

ns

tORHt

Shift Out to Output Ready HIGH

5

65

50

ns

tODH

Output Data Hold (previous word)

5

tODS

Output Data Shift (next word)

5

50

40

ns

50

40

ns

10

15

10

MHz

10

ns

60
2.2

45

ns

1.6

/lS

65

60

ns

65

60

ns

tpT

Data throughput or "fall through"

tMRORL

Master Reset to OR LOW

4, 8
10

tMRIRH

Master Reset to IR HIGH

10

·tIPH

Input Ready pulse HIGH

4

20

20

ns

Output Ready pulse HIGH

8

20

20

ns

tOPH

7-30

IIIIonoIlthlc

W lIIIemories

5/67401/2 Standalone

Absolute Maximum Ratings
Supply voltage vee ............................................... ; .......................... .."....... , ... -0.5 Vto 7 V
Input voltage ......................................•..........................••••••.........'.; .......•.•• -1.5 V to 7 V
Off-state output voltage ..... . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . . . .. • . • . . . . . . .• -0.5 V to 5.5 V
Storage'temperature ................. , .............................•............•...................' ..• -650 to +l50o

e

Operating Conditions 5/67401/2
PARAMETER

SYMBOL

FIGURE

MIN

Vee

Supply voltage

4,5

TA

Operating free-air temperature

-55

MILITARY
MAX
TYP
5

5.5
*125

COMMERCIAL
TYP
MAX

,MIN
4.75

5

UNIT

V
°e

5.25
75

0

tSIHt

Shift in HIGH time

1

45

35

ns

t~JL

Shift in LOW time

1

45

35

ns
ns

tlDS

Input data setup

1

10

5,

tIDH'

Input data hold time

1

55

45

ns

tSOHt

Shift Out HIGH time

5

45

35

ns

tSOL

Shift Out LOW, time

5

45

35

ns

tMRW

Master Reset pulset

10

30

35

ns

tMRS

Master Reset to SI

10

45

35

ns

*Case temperature.

Switching Characteristics 5/67401/2
Over Operating CondlUons
PARAMETER

SYMBOL

FIGURE

1

fiN

Shift in rate

tlRLt

Shift In

tlRHt

Shift In to input ready HIGH

1

fOUT

Shift, Out rat~

5

tORLt
tORHt,
tODH

to inpui ready

MIN

,

LOW

MILITARY
TYP
MAX

7

1

COMr.'IERCIAL
TYP
MAX

MIN
10

MHi

45

60

60
7

UNIT

4$
10

ns
ns
MHz,

Shift Out to Output Ready LOW

5

65

55

ns

, Shift Out to Output Ready HIGH

5

70

60

ns

Output Data Hold (previous word)

5
5

65

55

" ns

' 10

10

ns

tODS

Output Data Shift (next word)

tF'T

Data throughput or "fall through"

4,8

4

3

J.LS

tMRORL

Master Reset to QR LOW

10

65

60

ns

60

tMRIRH

Master Reset to IR HIGH

10

tlPH

Input Ready pulse HIGH

4

20

20

tOPH

Output Ready pulse HIGH

8

20

20

65
,

ns
os
ns

tSee AC test and hlghspeed application note,

Test Load

5V

5800

*

The "TEST POINT" is driven,by the output under test,
and observed ~Y instrurne':ltati9r1 .

+--~H.) TEST POINT*
1.1KO

Input Pulse 0 to 3 V
Input Rise and Fall Time (10% to 90%)
2-,5ns.
MeaSurements made at 1.5 V

30pF

7·31

5.167401 A.l2A.l1.12,67401 B/2B Standalone

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL

Low-level input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

IILl

Low-level
input current

IIH

High-level input current

II

UNIT

a.8t
2t
Vee = MIN

lDo-D4: MR

IIL2

MIN TVP MAl(

TEST CONDITIONS

II

= -18mA

I

V
V

':'1.5

V

-0.8

mA

-1.6

mA

VI

= O.45V

Vee = MAX

VI

= 2.4V

50

p.A

Maximum input current

vee = MAX

VI

= 5.5V

1

mA

VOL

Low-level output voltage

Vee = MIN

10L = SmA

VOH

High-Ieveloutpul voltage

Vee = MIN

10H = -0.9mA

2.4

Vee = MAX

= OV

,-20

lOS

151 • 50

Output short-<:ircuit current

*

Vee = MAX

Vo

0.5

5/67401
Vee = MAX
lee

Supply current

Inputs low.
outputs open.

V
V

-90

mA

160

5/67402

180

5/67401 A

170

5/67402A

190

674018

180

674028

200

* Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
tThere are absolute.voltagea with respect to degree \3ND (PIN 8 or 9) and includes all overshoots due to

Functional Descrlpti,on
Data Input
After power up the Master Reset is pulsed low (Fig. 10} to
prepare the FIFO to accept data in the first location. When Input
Ready (lR) is HIGH the location is ready to accept data from the
Dx inputs. Data then present at the data inputs is entered into
the first location when the Shift In (51) is brought HIGH. A 51
HIGH signal causes the IR to go LOW. Data remains at the first
location until 51 is brought LOW, When 51 is brought LOW and
the FIFO is not full. IR will go HIGH. indicating that more room
is available. Simultaneously. data will propagate to the second
location and continue shifting until it reaches the output stage
or a full location. The first word is present at the outputs before
a shift out is applied. If the memory is full. IR will remain LbW.

Data Transfer
Once data is entered into the second cell. the transfer of any full
cell to the adjacent (downstream) empty cell is automatic.
activated by an on-<:hip control. 'Thus data will stack up at the
end of the device while empty locations will "bubble" to the front.
tPT defines the time required for the first data to travel from input
to the output of a previously empty device,

Data Output
Data is read from the Ox outputs. When data is shifted to the
output stage. Output Ready (OR) goes HIGH. indicating the
presence of valid data. When the bR.is HIGH. data may be
shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal
at SO causes the OR to go LOW. Valid data is maintained while
the SO is HIGH. When SO is brought LOW the upstream data.
provided that stage has valid data. is shifted to the output stage.
When new valid data is shifted to the output stage. OR goes

7·32

test equipment.

HIGH.lfthe FIFO is emptied. OR stays LOW. and Ox remains as
before. (i.e. data does not change if FIFO is empty).
Input Ready and Output Ready may also be used as status
signals indicating that the FIFO is completely full (Input Ready
stays LOW for at least tPT) or completely empty (Output Ready
stays LOW for at least tPT).

AC Test and High Speed App. Notes
Since the FIFO is a very-high-speed device. care must be exercised inthedesign ofthe hardware and the timing utilized within
the design. The internal shift rate of the FIFO typically exceeds
20 MHz in operation. Device grounding and decoupling is crucial to correct operation as the FIFO will respond to very small
glitches due to long reflective lines. hign capacitance and/or
poor supply decoupling and grounding. We recommend a
monolithic ceramic capacitor ofO.1j.tF directly between Vee
and GND with very short lead length. In addition. care must be
exercised inhowthe timing is set up and how the parameters are
measured. For example •. since an AND gate function is associated with both the Shift In-Input Ready cpmbination. as well as
the Shift Out-Output-Readycombination. timing measurements
may be misleading. i.e .• rising edge otthe Shift-In pulse is not
recognized until Input-Ready is High.1f Input-Ready is not high, .
due to too high a frequency or FIFO being full or affected by
Master Reset. the Shift-In activity will be ignored. This will affect
the device from a functional standpoint. and will also cause the
"effective" timing of Input Data Time (tIDH) and the next activity
of Input Ready (tIRU to be extended relative to Shift-In going
High. This same type of problem is also related to tlRH tORL'
arid tORH as related to Shift-Out.

51'67401 AI'2AI' 1 1'2, 67401 BI'2B Standalone
i-------- 1i
 
N -------,~o--------1iIIN ----~--~

SHIFT IN
i4----IIRH----+I
INPUTREADY----+-------------~

INPUT DATA

Flgu.. 1. Input Timing

SHIFT IN

INPUT DATA
F.lgure, 2. . Typlll8l WavelDnnsfor ,1 o MHz .Shift In ',Data, Rate, (67401/2)

SHIFT IN
INPUTREADY'~~------------~~--~~----~

INPUTDATA,~~ ~-S~T-A-B-L~E-D-,A~~~----~
__

,~'u"3. The M.c:ha"l~ of Shlftlrlg
(})

o

o
o

\-;;1$ ,
-~
;
Input Ready;"HIGH indic~les space is·availabl~'~nd·a sllifi'i,(pulse may be applied,
Input

D~ta is

Data Info the, FIFO

loaded into' the first word.

Input Ready goes LOW indicating the firsl word is full.

T~e Data from the first word

is

releas~~

for

"fall~through" 'to second word.

@ The Data from ~he first wortHs transfe;red to second word. The"first w~rd is now empty as indicated"bY Jnput Ready HIGH.
@ If the sec~~~,word. is already full' then the 'data remains at the first word. Since the FIFO is ~~.~' !~1l1npu~.Re~dy remains ..I~r"
NOTE: Shift In pulses applied while Input Ready is LOW will be ignored. (See Figure 4.)

5/67401 A/2A!1 12, 67401 B/2B Standalone

SHIFT OUT

SHIFT IN

INPUT READY

INPUT

DATA\,:~~~~~~S_T_'A_B_L_E_D_A_T_'A

___

...I~

Figure 4. Deta II Shifted In Whenever Shift In and Input Reedy are Both HIGH

o
o

o

FIFO is initially full.·
Shift Out pulse is applied. An empty location starts ''bubbling'' to the front.
Shift In is held HIGH.

0AS soon as Input Ready becomes HIGH the Input Data is loaded into the first word.

o

The Data from the first WO~d is released

for 'itall through"

to second word.

1~·o------IIfOUT------~.-----I/IOUT------+-1

SHIFT OUT

OUTPUTREADY-.-~--+------~~_,

OUTPUT DATA

C-OATA

Figure 5. Output Timing.

,

o
o

The diagram assumes. that

a~

!hiS time. words 63, f)2, 61 are loaded with A, ,B. C Qata. respectively.

Data is shifted out wheri:Shlft Out makes a HIGH to LOW·transition.

7-34

5/67401 A/2A/1/2, 674018/28 Standalone

~------------100ns------------~j..------------l00ns------------·~1

SHIFT OUT

OUTPUT READV

-----+-1------.,.

C-DATA
OUTPUT DATA

Figure 6.

o
o

Typical Wavefonns for 10 MHz Shift Out Data Rate (67401/2)

The diagram assumes, that at this time. words 63, 62, 61 are loaded with A, B. C Data, respectively
Data in the crosshatched region may be A or 8 Data.

SHIFT OUT

OUTPUT READY

---~------

OUTPUT DATA

_______~
A-DATA

)p

B·DATA

fl~~''------

Figure 7. The Mechanism of Shifting Data Out of the FIFO.

o

o
o
o

Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.

Shift Out goes HIGH causing the next step.
Output Ready goes LOW.
Contents of word 62 (a-DATA) is released for "fall through" to word 63.

@) Output Ready goes HIGH indicating that new data (8) is now available at the FIFO outputs

®

If the FIFO has only one word loaded (A-DATA) then Output Ready stays LOW and the A-DATA remains unchanged at the outputs.

NOTE: Shift Out pulses applied when Output Ready is LOW will be ignored.

III/IonoIIthIc

m

Memories

7·35

,

5/67401 A/2A/1 /2,674018/28 Standalone

SHIFT IN

SHIFT OUT

OUTPUT READY

-4~

___
I ________________

:~~~~~~~~~~~~~~~~ tP_T~~~~~~~~_-_-_-_-_-_-_-_~_~tOPH~~~
__

___________

Figure 8. tpT and tOPH Specification

o

FIFO initially empty.

SHIFT OUT

{IIII lIliTI I/!J
/ // / / / /I / / / / / /

OUTPUTREADY----~--------------J

OUTPUT DATA

A·DATA

Figure 9. Data is Shifted Out Whenever Shift Out and Output Ready are Both HIGH.

o
o

CD

o

o

Word 63 is empty
New data (A) arrives at the outputs (word 63)

Output Ready goes HIGH Indicating the arrival of the new data.
SInce Shift Out is held HIGH, Output Ready goes immedIately LOW
As soon as Shift Out goes LOW the Output Data is subject to change as shown by the dashed line on Output Ready

7-36

Monolithic

m

Memories

5/67401 A/2A/1 /2, 67401 8/28 Standalone

~IMRW-

MASTER RESET

I

\
~

IMRtRH

1/
I

INPUT READY

)D

OUTPUT READY

tMRORl

\
~

I_~

tM_R_S~~~~~~~~~~~~.r------------------------

_______________________ ___________
SHIFT IN

Figure 10. Master Reset Timing

o

FIFO initially full

IIIIonoIHhlc

W Memories

7-37

51'67401 A1'2A1' 1 1'2, 67401 B1'2B Standalone

Die Configurations
57401 Ole Pattern
Step:G
Die Size: 128x166 mll2

-T

03

.15
SHIFT OUT

.14 •
OUTPUT NC
READY

.13
00

It

203
1

940"

~
--.360"
--.L

.11
02

.10
03

"M""AS""T"'EftR"R""ES"'ET""

1057"

TT

.12
01

ALL PADS EXCEPT GND AND VCC
100" x 100"
(DIE SIZE 166 x 128 mils)

IVCC
16

~230"

~

=

(PIN1-NC)
8

GNDI

;Tsl
Dl
D3 -,............411...5-.
......•D26.7

SHIFT IN NC TEST PADS (TYP) DO
.3
•
1-600,,-1 1~1500w---'"

I-I

II
-+i r-15O"

r- 736,,-1

324"

57402 Die Pattern
Step:G
Ole Size: 128x166 mll 2

,,----1 ~ I~~I ~ ~ I~

1 -1182
04
MR

T

.17

.18 .15
OUTPUT 02
READY

SHIFT OUT

.14 .13
01
02

1057"

.L

~

Ivcc
18

--.--.L

SHIFT IN DO
_3

l~

100"

9

-.l

GNDI

.4

1-600"..,

7·38

1720"

(PIN l-NC)
INPUT
2-READY

360"

T

ALL PADS EXCEPT GND AND VCC =
100" x 100"
(DIE SIZE 186 x 128 mils)

100"

940"

t23O"

•

MASTER RESET 10

2~31

TT

.12 .11
03
04

MM157402G

Dl

D2

D3 D4

•••••••••••• 5 •••••• ....... 7.8

r---1500"---1 ~
r-736w--:Li
324"
-

;Ts3
-.L

~ 150"

Low Power
First-In First-Out (FIFO) 64x4
Cascadable.Memory
67L401
Features/Benefits

Ordering Information

• Guaranteed 5 MHz shIH·out/shIH·ln rates

• Low Power ConsumpUon .

PART

PKG

TEMP

DESCRIPTION

67L401

N

COM

5 MHz 64x4 FIFO

67L401

J

COM

5 MHz 64x4 FIFO

NUMBER

• TTL Inputs III1d outputs
• ReadllyellPllndable In the word and bit dimensions

• Structured pinouts. Output pins directly opposHe corres·
pondlnllinput pins
• Asynchronous operation

Block Diagram

• Pin compatible with Fairchild's F3341 MOS FIFO and much
faster

67L401 64x4
DO
0,

Description
The 67L401 is a low-power First In/First Out (FIFO) memory
devicewith TTL speed. This device is organized in a 64x4-bit
structure and easily. cascadablewith similar FIFOs to any
depttl or width. A 5MHz data rate with fast ''fall through" time
allows usage in tape and disc controllers, printers· and com"
munications 'buffer applications. This data rate lsmuch faster
than a comparable MO$ device. The FIFO is a register-based
deviee.Oata entered at the inputs ''falls through" to the empty
space closesito the output. Data is shifted out in the same
sequence it is shifted in. FIFOs can be cascaded to any depth
in it handshake.mode. Also, the width can be Increas.ed by
putting the Input Ready signais through an AND gate to give
a composite Input Ready. Similarly, the Output Ready signals
should be gateq to form. a composite Output Ready.

OUTPUT

READY

IN

Pin Configuration

TWX: 910-338-2376
2175 MISSion College Blvd. Santa Clara, CA 95054-1592 Tal: (408) 970-9700 TWX: 910-338·2374
.

OUT

SHIFT

Generally, FIFOs are used in digital systems performing
data transfers when source and receiver are not operating at
the same data rate. FIFOs are also used as data buffers
where the source and receiver are not operating at the same'
time, The 67L401 is particularly useful where low-power consumption .is'critical.

.

SHIFT

INPUT
READV

14 OIm'llT READY

Mononthla m1!n
Memories. LnJrW.
7-38

67L401

Absolute Maximum Ratings
Supply voltage vee ....................................................................................... -0.5 V to 7 V
Input voltage ............................................................................................. -1.5 V to 7 V
Off-state output voltage ................................................ " ; . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. -0.5 V to 5.5 V
Storage temperature ................................................................................... -65° to +150 0 e

Operating Conditions
SYMBOL

PARAMETER

FIGURE

MIN

COMMERCIAL
TYP

MAX

5

5.25

V

75

°e

Vee

Supply voltage

4.75

TA

Operating free-air temperature

0

UNIT

tSIHt

Shift in HIGH time

1

55

ns

tSIL

Shift in LOW time

1

55

ns

tlOS

Input data setup

1

10

ns

tlOH

Input data hold time

1

80

ns

tSOHt

Shift Out HIGH time

5

55

ns

tSOL

Shift Out LOW time

5

55

ns

tMRW

Master Reset pulse

10

40

ns

tMRS

Master Reset to SI

10

35

ns

Switching Characteristics
Over Operating Conditions
SYMBOL·

-t

PARAMETER

FIGURE

MIN

COMMERCIAL
TYP

MAX.

5

UNIT

fiN

Shift in rate

1

tlRLt

Shift in to Input Ready LOW

1

75

tlRHt

Shift in to Input Ready HIGH

1

75

fOUT

Sh ift Out rate

5

tORLt

Shift Out to Output Ready LOW

5

75

ns

tORHt

Shift Out to Output Ready HIGH

5

80

ns

tODH

Output OataHold (previous word)

5

to OS

Output Data Shift (next word)

5

tpT

Data throughput or ''fall through"

MHz

5

ns
ns
MHz

8

ns
ns

4,8

70
4

J1.S

tMRORL

Master Reset to OR LOW

10

85

ns

tMRIRH

Master Reset to IR HIGH

10

85

ns

tlPH *

Input Ready pulse HIGH

4

20

ns

tOPH *

Output Heady pulse HIGH

8

20

ns

See AC test and application note .

• This parameter applies to FIFOs communicating with -each other in a cascade mode.

Test Load

*

The "TEST POINT" is driven by the output under test,
and observed by instrumentation.

7-40

&
SSO!!
5V
,
Uk!!

TEST POINT*

30pF

IIIIonoIHhic WMemorles

Input Pulse = 3V
Input Rise and Fall Time (10% - 90%)
2 - 5 ns.
Measurements made at 1.5 V

67L401

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL

Low-level input voltage

VIH

High-level input voltage

VIC

Input clamp voltage

11L1

Low-level

IIL2

input current

IIH
II

I

00- 0 3 MR

TEST CONDITIONS

MIN

TYP

MAX
0.8

= -18mA

II

V
V

2t
VCC= MIN

UNIT

= O.45V

-1.5

V

-0.8

rnA

-1.6

rnA

VCC= MAX

VI

High-level input current

VCC= MAX

VI

=2.4V

50

p.A

Maximum input current

VCC= MAX

VI

= 5.5V

1

rnA

SI, SO

VOL

Low-level output voltage

VCC= MIN

IIOL = SmA

VOH

High-level output voltage

VCC= MIN

I 10H = -0.9mA

lOS

Output short-circuit current"

VCC= MAX

ICC

Supply Current

VCC= MAX

Vo

=OV

Inputs Low,

Outputs Open

0.5

V

-90

rnA

110

rnA

2.4

V

-20
95

* Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

t This is an absolute vOltage with respect to device GND (pin 8 or 9) and includes all overshoots due to test equipment.

Functional Description
Data Input
After power up the Master Reset is pulsed low (Fig. 11) to
prepare the FIFO to accept data in the first location. When Input
Ready (IR) is HIGH the location is ready to accept data from the
Ox inputs. Data then present at the data inputs is entered into
the first location when the Shift In (SI) is brought HIGH. A SI
HIGH signal causes the IR to go LOW. Data remains at the first
location until SI is brought LOW. When SI is brought LOW and
the FIFO is not full, IR will go HIGH, indicating that more room
is available. Simultaneously, data will propagate to the second
location and continue shifting until it reaches the output stage
or a full location. The first word is present at the outputs before
a shift out is applied. If the memory is full, IR will remain LOW.

Data Transfer
Once data Is entered into the second cell, the transfer of any full
cell to the adjacent (downstream) empty cell is automatic,
activated by an on-chip control. Thus data will stack up at the
end of the device while empty locations will "bubble" to the front.
tPT defines the time required for the first data to travel from input
to the output of a previously empty device.

Data Output
Data is read from the Ox outputs. When data is shifted to the
output stage, Output Ready (OR) goes HIGH, indicating the
presence of valid data. When the OR is HIGH, data may be
shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal
at SO causes the OR to go LOW. Valid data is maintained while
the SO is HIGH. When SO is brought LOW the upstream data,
provided that stage has valid data, is shifted to the output stage.
When new valid data is shifted to the output stage, OR goes
HIGH. If the FIFO is emptied, OR stays LOW, and Ox remains
as before, (i.e. data does not change if FIFO is empty).

fIIIonollthlc

Input Ready and Output Ready may also be used as status
signals indicating that the FIFO is completely full (Input Ready
slays LOW forat leastlpT) or completely empty (Output Ready
stays LOW for at leasttpT)'

AC Test and Application Note
Since the FIFO is a very-high-speed device, care must be exercised in the design of the hardware and the timing. Though the
external data rate is 5 MHz internally the device is several times
as fast. Device grounding and decoupling is crucial to correct
operation, as the FI Fa will respond to very small glitches caused
by long reflective lines, high capacitances and/or poor supply
decoupling and grounding. We recommend a monolithic ceramic
capacitor of 0.1 ,"F directly between Vce and GND with very
short lead length. In addition, care must be exercised in timing
set up and measurement of parameters. For example, since an
AND gate function is associated with both tM Shift In-Input
Ready Combination, as well as the Shift Out-Output Ready
Combination, timing measurements may be misleading, i.e.,
rising edge of the Shift-In pulse is not recognized until Inpute
Ready is High.lflnput-Ready is not high due to too high a
Ireq uency, or the FI Fa being full or affected by Master Reset, the
Shift-In activity will be ignored. This will affect the device from a
functional standpoint, and will also cause the "effective" timing
of Input Data Time (tIDH) and the next activity of Input Ready
(tIRLl to be extended relative to Shift-In going High.

W Memories

7-41

67L401
1 + - - - - - - - - 1 1 1IN - - - - - - - . r . . - - - - - - - 1 1 1 I N -------~

SHIFT IN

INPUT R E A D y - - i - - - - - - - " \

INPUT DATA

Figure 1. Input Timing
,------------~~-----------200M------------~

SHIFT IN

INPUT DATA

Figure 2. Typical Wavefom1s for 5 MHz Shift In Data Rate

SHIFT IN

INPUTREADY'~~-----~----;---~

®

~-------.;;-----...I------':::....

IN~UT

o
o
o
o

S_:I:_A_B_L_E_D_A_T~A

DATA _ _
• ___

_ _ _-,

Figure 3. The ~Bnlam of Shifting Oata Into the FIFO
Inpul Ready HIGH indIcates space is available and a Shift In pulse may be applied.
Input Oata is loaded .into the first word.
Input Ready goes LOW indicati"!g the first word is full.

The Dala. from the first word is released for "fall-through" to second word.

@ The Data from the first word is transferred to second word. The first word is now empty as indicated by Input Ready HIGH.
@ If the second word is already. full then the data remains at the first word. Since the FIFO is now full Input Ready remains low.
NOTE: Shift In pulses applied while Input Ready is LOW will be.ignored (See Figure 5).

7io42

67L401

SHIFT OUT

SHIFT IN

\'----

INPUT READY

INPUT D A T A \ ,
..._ _ _ _S_1:_'A_B_L_E_D_A_TA
___

--'~

Figure 4. Data is Shifted in Whenever Shift In and Input Ready are Both HIGH

o
o

FIFO is initially full
Shift Out pulse is applied. An empty location start "bubbling" to the front.

@Shift In is held HIGH

o

®

As soon as Input Ready becomes HIGH the Input Data is loaded into the first word
The Data from the first word is released for "fall through" to second word

SHIFT OUT

OUTPUTREADY---------t----~--~r_--""I

tOD(min)
OUTPUT DATA

o

The diagram assumes. that at this time, words 63, 62. 61 are loaded with A, B, C Data, respectively

Figure 5. Output Timing

Monolithic

m

Memories

7·43

67L401

~------------~ns------------~~------------~n·------------·~I

SHIFT OUT

OUTPUT READY

C-DATA
OUTPUT DATA

Figure 6. Typical Wavefonn for 5 MHz Shift Out Data Rate

o

The diagram assumes, that at this time. words 63. 62. 61 are loaded with A, B. C Data, respectively.

[ ) Data in the crosshatched region may be A or B Data

SHIFT OUT

OUTPUT READY --~------------+---------~

---~----OUTPUT DATA

~

A-DATA

8-DATA

------'~~'-----.-Figure 7. The Mechanism of Shifting Data Out of the FIFO

o

Output Ready HI'GH indicates that data is available and a Shift Out pulse may be applied:

[ ) Shift Out goes HIGH causing the next step.

o

o

®
®

Output Ready goes LOW.
Contents of word 62 (B-DATA) is released for "fall through" to word 63.
Output Ready goes HIGH indicating that new data (8) is now available at the FIFO outputs.
If the FIFO has only one word loaded (A-DATA) then Output Ready stays LOW and the A-DATA remains unchanged at the outputs.

7·44

Monolithic

W Memories

67L401

SHIFT IN

o

FIFO inilially emply.

Figure 8. tpT and tOPH Specification

SHIFT OUT

rllTIITI ITI 177:
IIIIIIIIIIIIII

OUTPUT READY --~-------..1

OUTPUT DATA

o

o
o

Figure 9. Data is ,Shifted Out Whenever Shift Out and Output Ready are Both HIGH

~} Since Shift Out

Word 63 is emply

0.

New data (A) arrives at the outputs (word 63).
Output Ready goes HIGH indicating. the arrival" of the new data.

,

is held HIGH, Output Ready goes immediately LOW

As ,soon as Shift Out goes LOW 'the Outpu! Data is subject to change
as shown by the dashed line on Output Ready

r---IMRW------+

MASTER RESET

1\

1/
~

IMRIRH

INPUT READY

OUTPUT READY

II
J

)D

IMRORL
.

\

lMRSi~t
SHIFT IN

o

--------------------------------~~

FIFO inilially full.

Figure 10. Master Reset TIming

MonoIithicWMemories

7-45

67L401

SHIFT IN

OR

SI

OR

OUTPUT READY

INPUT READY

SO

IR

SO

SHIFT OUT

00

DO

00

0,

0,

02

02

03

03

67L401

.0,
02

MR

} 0'" 0"'

03

MASTER RESET o---------~------------------~

Figure 11. Cascading FIFOs to Form 128 x 4 FIFO with 67L401's

FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the
FIFOs themselves.

SOIt-__~____________~S~H~IFT~O~UT

IR
SI
Do

ORt---+--...,

67L401

Qo

D1

Q1

D2

Q2

COMPOSITE
INPUT READY

COMPOSITE
OUTPUT READY

IR

SO

=SH~I~FT~I~N~________-4~SI
Do

ORt---~~

67L401

Qo

D1

Q1

MASTER RESET

Figure 12. 64 x 8 FIFO wilh two 67L401's

FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite
Input and Output Ready flags. This need is due to the different fall through times of the FIFOs.

7·46

I/IIonoIIlhlc

m

Memories

87L401

Applications
FIFOs are typically used as temporary data buffers between
mismatching data rates. Such an application is shown in
Figure 13.

The 67L401 can also be used in a bidirectional operation as
shown in Figurt314.

PAPER
TAPE
READER
ENBLSI

so'----\

1--,.--.lSI
IR

OR

10-RDY

Figure 13. FIFO as data buffer between slow steady rate and fast 'burst'

rate

so

Sl ~-------~

IR .--------42x67L401 1 - - - - - - - - " OR

2x67L401
64.8
OR . .- - - - - - - 4

I--~-----"IR

so

",~----,---SI

--------~

NOTE: Both depth and width expansion can be used in this mode.

Figure 14. Bldlrecllonal FIFO.appllcatlon

Die Configurations
57401 Die Pattern
Step: G
Die Size: 128x166 mll2
__

so
Mfi

'T

1182~-1 !56~ 1~8'!.j ~48!:! ~8!: :!",8~1

.15
SHIFT OUT

i

IR

~
"T"
360~

...L

.12
01

.11
°2

.10
03

•

1230~

I

203
1±:

940~

.13
00

MASTER RESET 9

1057;'

1
rr

•

.14
OUTPUT NC
READY

Ivcc

I

ALL PADS EXCEPT GND AND VCC =
100~ • 100~
(DIE SIZE 166 • 128 mils)

I

1720~

12~~

16
(PIN1-NC)

100~

8
INPUT
2. READY

.. 1 !

GNDI

• I

D2 ~
SHIFT IN NC TEST PADS (TYP) DO
D1
.3
•
• ••••••••••• 4.... 5•• ....... 6.7

,

366~

7-47

.

Low Power First-In First-Out (FIFO)
64x5 Cascadable Memory
67L402
Features/Benefits
• Guaranteed 5 MHz shift-out/shift-in rates

Ordering Information

• Low power consumption

PART
PACKAGE

• TTL Inputs and outputs
• Readily expandable in the word and bit dimensions

PKG

TEMP

DESCRIPTION

67L402

N

COM

5 MHz 64x5 FIFO

67L402

J

COM

5 MHz 64x5 FIFO

• Structured pinouts. Output pins directly opposite corresponding input pins
• Asynchronous operation

Description
The 67L402 is a low-power First-In First-Out (FIFO) memory
device with TTL speed. This device is organized in a 64x5-bit
structure and easily cascadable with similar FIFOs to any depth
or width. A 5 MHz data rate with fast ''fall through" time allows
usage in tape and disc controllers, printers and communications
buffer applications. This data rate is much faster than a comparable MOS device. The FIFO is a register-based device. Data
entered at the inputs "falls through" to the empty space closest
to the output. Data is shifted out in the same sequence it is
shifted in. FIFOs can be cascaded to any depth in a handshake
mode. Also, the width can be increased by putting the Input
Ready signals through an AND gate to give a composite Input
Ready. Similarly, the Output Ready signals should be gated to
form a composite Output Ready.
Generally. FIFOs are used in digital systems performing data
transfers when source and receiver are not operating at the
same data rate. FIFOs are also used as data buffers where the
source and receiver are not operating at the same time. The
67L402 is particularly useful where low-power consumption is
critical.

Block Diagram
67L40264x5

INPUT
READY
SHIFT
IN

Pin Configuration
vcc
INPUT READY

2

SHIFT IN

3

DO 4

SHIFT OUT
16 OUTPUT READY

67L402

01

(
DATA IN

O2

03
04
MASTER RESET

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

7-48

lIIonolithic l!1!ft
lIIemorles UlUW

67L402
Absolute Maximum Ratings
Supply voltage vee ..................................................................................... -0.5 V to 7 V
Input voltage ............................................................. , •................ , , . . . . .. . . . . .. -1.5 V to 7 V
Off-state output voltage .....................................................•......................... -0.5 V to 5.5 V
Storage temperature .•..........................................•.................................... -65° to+150°C

Operating Conditions
SYMBOL
Vee

PARAMETER

FIGURE

Supply voltage

MIN

COMMERCIAL
TYP

MAX

4.75

5

5.25

V

75

°e

UNIT

TA

Operating free-air temperature

tSIHt

Shift in HIGH time

1

55

tSIL

Shift in LOW time

1

55

ns

liDS

Input data setup

1

10

ns

0

ns

t'DH

Input data hold time

1

80

ns

tSOHt

Shift Out HIGH time

5

55

ns

tSOL

Shift Out LOW time

5

55

ns

tMRW

Master Reset pulse

10

40

ns

tMRS

Master Reset to SI

10

35

ns

.'

Switching Characteristics
Over OperatIng Conditions
SYMBOL

PARAMETER

COMMERCIAL

FIGURE

fiN

Shift in rate

1

t'RLt

Shift in to Input Ready LOW

1

t'RHt

Shift in to Input Ready HIGH

1

fOUT

Shift Out rate

5

MIN

TYP.

MAX

UNIT
MHz

5
75
75

5

ns
ns
MHz

tORLt

Shift Out to Output Ready LOW

5

75

ns

'ORHt

Shift Out to Output Ready HIGH

5

80

ns

'ODH

Output Data Hold (previous word)

5

tODS

Output Data Shift (next word)

5

tPi"

Data throughput or "fall through~'

4,8

ns

8

.

"

70

ns

4

p.S

85

ns

as

ns

tMRORL

Master Reset to OR LOW

10

tMRIRH

Master Reset to IR HIGH

10

tIPH'

Input Ready pulse HIGH

4

20

ns

tOPH *

OUtput Ready pulse HIGH

8

20

ns

"

tSee AC test and applicatlOl1 note..
• ThIs Parameter applies to FIFeS communicating with each other in a' c:ascede mode.

Test Load
*

The "TEST POINT" is driven by the output under test,
and observed by instrumentation.

.

~5V560n
TEST POINT*

1.lkll

.

. . .30pF

Input Pulse=3V
Input Rise and Fall Time (10% - 90%)
. 2-5n5.:
Measurements made at 1.5 V

7·49

67L402
Electrical Characteristics Over OperaUng Conditions
SYMBOL

PARAMETER

VIL

Low-level input voltage

VIH

High-level input voltage

VIC

Input clamp voltage

I00-0 3 MR

TEST CONDITIONS

MIN TYP MAX
O.S

V

-1.S

V

-O.S

mA

-1.6

mA

SO

}J.A
mA

V

2t
Vee = MIN

II

= -1SmA

Vee = MAX

VI

= O.4SV

VI

= 2.4V

VI

UNIT

11L1

Low-level

IIL2

input current

IIH

High-level input current

Vee = MAX

II

Maximum input current

Vee = MAX

= S.SV

1

VOL

Low-level output voltage

Vee = MIN

IIOL = SmA

O.S

V

VOH

High-level output voltage

Vee = MIN

I 10H = -O.9mA

lOS

Output short-circuit current"

Vee = MAX

-90

mA

ICC

Supply Current

Vee = MAX

130

mA

SI, SO

Vo = OV
Inputs Low,

Outputs Open

*

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

t

This is an absolute voltage with respect to device GND (Pin 8 or 9) and includes all overshoots due to test equipment.

2.4

V

-20
113

Functional Description
Data Input
After power up the Master Reset is pulsed low (Fig. 11) to
prepare the FIFO to accept data in the first location. When Input
Ready (IR) is HIGH the location is ready to accept data from the
Ox inputs. Data then present at the data inputs is entered into
the first location when the Shift In (SI) is brought HIGH. A SI
HIGH signal causes the IR to go LOW. Data remains at the first
location until SI is brought LOW. When SI is brought LOW and
the FIFO is not full, IR will go HIGH, indicating that more room
is available. Simultaneously, data will propagate to the second
location and continue shifting until it reaches the output stage
or a full location. The first word is present at the outputs before
a shift out is applied. If the memory is full, IR will remain LOW.

Data Transfer
Once data is entered into the second cell, the transfer of any full
cell to the adjacent (downstream) empty cell is automatic,
activated by an on-chip control. Thus data will stack up at the
end of the device while empty locations will "bubble" to the front.
tPT defines the time required for the first data to travel from input
to the output of a previously empty device.

Data Output
Data is read from the Ox outputs. When data is shifted to the
output stage, Output Ready (OR) goes HIGH, indicating the
presence of valid data. When the OR is HIGH, data may be
shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal
at SO causes the OR to go LOW. Valid data is maintained while
the SO is HIGH. When SO is brought LOW the upstream data,
provided that stage has valid data, is shifted to the output stage.
When new valid data is shifted to the output stage, OR goes
HIGH. If the FIFO is emptied, OR stays LOW, and Ox remains
as before, (i.e. data does not change if FIFO is empty).

7·50

Input Ready and Output Ready may also be used as status
signals indicating that the FIFO is completely full (Input Ready
stays LOW for at least tPT) or completely empty (Output Ready
stays LOW for at least tPT).

AC Test and Application Note
Since the FIFO isa high"speed device, care must be exercised in
design of the hardware and the timing. Though the external data
rate isS MHz, internally the device is several times as fast. Device
grounding and decoupling is crucial to correct operation, as the
FIFO is sensitive to very small glitches caused by long reflective
lines, high capacitances, and/or poor supply decoupling and
grounding. We recommend a monolithic ceramic capaCitor of
0.1 }J.F directly between Vee and GND with a very short lead
length. In addition, care must be exercised in timing setup and
measurement of parameters. For example, since an AND gate
function is aSSOCiated with both the Shift In-Input Ready Combination as well as the Shift Out-Output Ready Combination,
timing measurements may be misleading. i.e., rising edge of the
Shift-In pulse is not recognized until Input-Ready is High. If
Input-Ready is not high dueto too high a frequency, orthe FIFO
being full or affected by Master Reset, the ShifHn activity will be
ignored. This will affect the device from a functional standpOint,
and will also cause the "effective" timing of Input Data Time
(tIDH) and the next activity of Input Ready (tIRU to be extended
relative to Shift-In going High.

Monolithic WMemories

67L402
1 - - - - - - - - 1 I IIN

--------'------1-------- 1IIIN ---'-------+1

SHIFT IN

INPUTREADY----+-------------~

INPUT DATA

Figure 1. Input Timing
-----~-~~~~-------200n.---~--~~

SHIFT IN

INPUTREADY----~--~--------~

INPUT DATA

Figure 2. Typical Wavefonns for 5 MHz Shift in Data Rate

SHIFT IN

@

INPUT·READy'"""':....----------+---"\

®

------------'.------~
INPUT DATA . . . . . .____S_.T_A_B_L_E,..D_A_T_A_____- '

Figure 3.11Ie Mechanism. of Shifting Data Into the FIFO

CD

o
o

o

Inpul Ready HIGH indicales space is available and a Shift In pulse may be applied
Input Data is loaded into the first word.
Input Ready goes lOW indicating the first word j's full.

The Dati from the first word is released for "fall-through" to second word,

@ The Data from the first word is transferred to second word. The first word is now empty as indicated by Input Ready HIGH.

®

If the second word is already full then the data remains at the first word. Since the FIFO is now fU"1/ Input Ready remains low.

NOTE: Shift In pulsll$ applied while Input Ready is LOW will be ignored (See Figure 5) ..

Monolithic

m

Memories

67L402

SHIFT OUT

SHIFT IN

l~ot_~----lpT

-----.:)-4..:..,

;>1/

INPUT READY

\'----

.J¥lI#lMI

INPUT D A T A \ , C_ _ _ _S_TA_B_L_E_D_AT_A_ _ _ _

Figure 4.· Data is Shifted in Whenever Shift In and Input Ready are Both HIGH

G) FIFO is initially full.
(1) Shift Out pulse is applied

An empty location start "bubbling" to the front.

0Shift Inls held HIGH

o

®

As soon as Input Ready becomes HIGH ,the Input Data is loaded into the first word
The Data from the first word is released for ,"fall through" to second word

SHIFT OUT

OUTPUTREADY--------+----------~--"'

IOD(min)
C-DATA

OUTPUT DATA

(2) The diagram assumes, that at this time. words'63, 62. 61 are loaded with A, S, C Data, respectively
Figure 5. Output Timing

7·52

Monolithic

W Memories

67L402


__-----200ns-----~I__-----200ns-------o~1

SHIFT OUT

OUTPUT READY

---------+--~----------~

C-DATA
OUTPUT DATA

Figure 6. Typical Wavefonnfor 5 MHz Shift Out Data Rate

o

o

'The d'iagram assumes, that at this

Data in the

crossh~tched

~ime. words 63. 62. 61

are loaded with A,

e. C

Data, respectively.

region may be A or B Data.

SHIFT OUT

OUTPUT .READY

--~------+...;..---"""-'\

---~----OUTPUT DATA

~

A-DATA

:~DATA

--------------~-------------~/~\~~~--~------Figure 7. The MechanlllJl of.Shlfting Data Out oftha FIFO

0.

o
CD
o

Output l'Ieady HIGH indl.cates that data. is available and a Shift Out pulse may be applied.
Shift Out goes HIGH causing the next step.
Output Ready goes LOW.
Contents of word 62 (B-DATA) is released for "fall through" to word 63.

@ Output' Ready goes HIGH indicating that new dafalB)· is 'nOw available 8' the FIFO oulpu,ts.
@ If the FIFO has only one Word loaded (A-DATA) then Output R,,!,~y ,stays LOw~nd the~-DATA remains unchanged a!.the outputs.
MOnoIIIhic

UD ••morla.

7-53

67L402

SHIFT IN

SHIFT OUT

OUTPUTAEADY

o

-'jD
__

l ________

FIFO initially empty.

~·~~~~~~~~~~~~~~~~ IPT_-_-_-_-_-_-_-_~~~~~~~~~FtOPH-t"_
.....

_ _ _ _ __

Figure 8. tPT and tOPH SpecIfication

SHIFT OUT

rTiT/7TI 1/1 171t
IIIIIIIIIIIIII

OUTPUTAEADY---~~-------'

~_ _ _ _ _ _ _A_-_DA_T_A_ _ _ _ _ _ _ _J~

OUTPUT DATA

o
o

o

Figure 9. Data Is .Shifted Out Whenever Shift Out and Output Ready are Both HIGH

o
o

Word 63 is empty.
New data (A) arrives at the outputs (word 63).
Output Ready goes HIGH indicating the arrival' 01 the new data.

,

1\

Output Ready goes immediately LOW.

V
J
'tMRIRH

OUTPUT READY

HIGH,

As soon as Shift Out goes LOW the Output Data is subject to change
as shown by the dashed line on Output Ready.

~tMAW-

MASTER RESET

INpUTAEADY

Since Shift Out is held

fo

tMRORL

1/

,
,1\

_____________________I_.________----tM-R-S~~~~~~~~~~~)I~r-------------------------SHIFT IN

o

FIFO initially lull.

7-54

Figure 10-. Malter ReNt T1mlng

J6onoIHbIcW.emorles

67L402

OUTPUT READY
SHIFT OUT
67L402
) DATA OUT

MASTERRESET--------~~------~----~

Figure 11. Cascading FIFOs to Form 128x4 FIFO with 67L402's

FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the
FIFOs themselves.

SO~--1--------- SHIFT OUT

IR
Sl
DO
01 67L402

ORI--l--,
00
01

02

02

COMPOSITE
OUTPUT READY

COMPOSITE
INPUT READY
IR
SHIFT I N - - - - - -......---!SI
DO
D167L402

SO
OR I---+~
00
01

02

' - - - - - - - - - - _ - -_____ MASTERRESET

Figure 12. 64x8 FIFO with 67L402's

FIFOs are expandable in depth and width. However, in forming wider words. two external gates are required to generate composite
Input and Output Ready flags. This need is due to the different fall through times of the FIFOs.

Monolithic

m

Memories

7-55

67L402

Applications
The 67LS402 can also be used in a bidirectional operation as
shown in Figure 14.

FI FOs are typically used as temporary data buffers between
mismatching data rates. Such an application is shown in
Figure 13.

Mii

I

RESET

T

~

~/D

PAPER
TAPE
READER

10-BIT
DATA

ob

2x67L402
64xlO
FIFO
BUFFER

v

CPU

DATA

51
JR

ENBLSI

I

SO
OR

10-ROY

Figure 13. FIFO as Data Buffer Between Slow Steady Rate and Fast 'Burst' Rate

Sl

'------~-~I

~

SO

IR .....- - - - - - - - l 2 x 6 7 L 4 0 2 1 - - - - - - - - . OR
64xlO

2x67L402
64xlO
OR .....-----~--l

I--------.IR

SO---------~

I·~o_-------SI

NOTE: Both depth and width expansion can be used in this mode.

Figure 14. Bidirectional FIFO application

Die Configurations
57402 Die Pattern
Step:G
Die Size: 128x166 mil 2

1-1182"------Il~ 1~08~1 ~~ll~l
SO

T

Mii

.16 .15
OUTPUT 02
READY

.17
SHIFT OUT

2~31

940"

~
---.-

IR

Ivcc

7-56

03°4

Monolithic

I
I

=

1720"

12~6"

(PIN l-NC)
9
INPUT
2-READY
_3

DO

t

18

.4

1-600"-1

W Nlemorie$

~ 100"

_1

GNDI

360"
i _ SHIFT IN DO
51

1230"

•

ALL PADS EXCEPT GND AND Vcc
100" x 100"
(DIE SIZE 166 x 128 mils)

100"

TT

.12 .11
03
04

MASTER RESET10

1057"

l

.14 .13
01
02

MMI57402G
01
02
03 0 4
••••••••• • •• 5 ••••&11. ....... 7.8

r---

15OOp---------I 1·-·1
324"

I-

736"

·LI L

,

:J6"

150"

t

First-In First-Out (FIFO)
64x5 Memory
35 MHz (Standalone)

57413A
67413A
67413

Ordering Information

Featuresl Benefits
• High-speed 35 MHz shift-In/shift-out rates
• High-drive capability
• Three-state outputs
• Half-full and Almost-full/Empty status flags
• Structured pinouts. Output pins directly opposite
corresponding input pins.

PART
NUMBER

PKG

TEMP

DESCRIPTION

57413A

J,W(l28}

Mil

25 MHz-in/out

67413A

J

Com

35 MHz-in/out

57413

J

Com

25 MHz-in/out

• Asynchronous operation
• TTL-compatible inputs and outputs
vcc

Description

ALMOST FULL!
EMPTY

The 5/67413A, 67413 are high-speed, 64x5 First-In-First-Out
memories (FIFOs) which operate at 35-MHz input/output rates
(67413 operates at 25-MHz in-out). The data. is loaded and
emptied on a first-in-first-out basis. It is a three-state device with
high-drive (IOl = 24 mAl data outputs. These devices can be
connected in parallel to give FIFOs of any word length. It has a
Half-full flag (thirty-two or more words full) and an almost
full/empty flag (fifty-six or more words or eight or less words).
The main applications . of 5/67413A, 67413 are rate buffers;
sourcing andabsorbingdata at different rates. Other appliclltions
are high-speed tape and. disk controllers, data commullications
systems and plotter control systems.

'SHIFTOUT

02

. DATA

OUTPUT

GND

Block Diagram

DE
1

DO----f-'-

D1----:rD2----s03-

D4~

FIFO
INPUT
STAGE

64.5
REGISTER

FIFO
OUTPUT
STAGE

INPUT READY

16
15
,14
13
12

00
01

02
03

04

SHIFT OUT
OUTPUT
READY

SHIFT IN

FLAG
CONTROL
. LOGIC

MASTERRESET __1~1~i)~~~__~~H~A~L~F~F=U=LL~~__~AL=M=0~S~T~F~U=LL=/=EM~PT~Y~____~~______~~.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408)970-9700 TWX: 910-338-2374

Monolithic. m'
..
memories
7·57

S./67413A
Absolute Maximum Ratings

~;;I~~~~::e.~~~.::::::::::: ::::::: :::: ::: ::: ::: ::: ::: ::: :::::: :::.:: ::::::::: :':::::::/ ... ::::: :::::: ::: !~::~::~~
Off-state output voltage ....................................... :........................................... -0.5 V to 5.5 V
Storage temperature .................. : .. : ............................. ~ ...........•... : ................

S/67413A Operating Conditions Over Temperalure Range
SYMBOL

PARAMETER

FIGURE

-65o to +150°C

.

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TVP MAX

5.5

4.75

125

0

Vec

Supply voltage

4.5

TA·

Operating free-air temperature

-55

5

5'

5.25
75

UNIT

V
~C

tSIHt

Shift in HIGH time

1

16

9

ns

tSILt

Shift in LOW time

1

20

17

'ns

tlDS

Inputdiita set up ,.

1

0

0

ns

tlDH

Input data hold time

1

25

15

ns

tSOHt

Shift Out HIGH time

5

16

9

ns

tSOL

Shift Out LOW time

5

20

17

ns

tMRW

Master Reset pulse t

10

35

30

ns.

tMRS

Master Reset to $1

10

35

35

ns

5/67413ASWltching Characteristics Over Operating Conditions
SYMBOL

FIGURE

PARAMETER

1

MILITARY
MIN TVP MAX

DC

H30

DC

ttt;35

Shift in rate

tlAd

Shift In I to Input Ready LOW

1

12

28

12

18

ns

tlRHt

Shift In I to Input Ready HIGH

1

14

25

14

20

ns

Shi~.Out rate

5

.

25

UNIT

fiN

fOUT

DC

COMMERCIAL
MiN TYP MAX

25

DC

DC

tt30

DC

ttt35

MHz

MHz

tORLt

Shift Out I to Output Ready LOW

5

12

28

12

18

ns

tORHt

Shift Out I to Output Ready HIGH

5

14

25

14

20

ns

tODHt

Output Data Hold {previous word)

5

tODS

,Qutput Data Shirt (next word)

5

tpT

Data throughputor ''1.allthrough''·

4,8

510

750

tMRORL

Master Reset I to 'Output Ready LOW

10

18

30

tMRIRH

Master Reset I to Input Ready HIGH

10

21

30

10

18

10

32

12

10

,

34

ns

51Q

650

ns

18

.28

ns

21

28

ns

30

18

28

ns

55

32

45

ns

....

tMRIRL

Master Reset I Input Ready LOW*

tMRO

Master Reset I to Outplits LOW

.

.c·;

Note: Typical is maasured 5 V, 25° C.
* 'if the FIFO:;s nol full jlR Hlgh),MR iow forces IR low, follo\Ne(fbyIB returning high wilen MR goes.hlgh.
See AC test and high-speed application note.

t
': tt Tested.' . '
.'
'.
;rtf' ~arant~d b~do:sign(S~te~, loadl·
,

ns

AO.

•

•

' . :.; :;.;)_.,,'.'"

<

S/67413A
S/67413A Switching Characteristics Over Operating Conditions (continued)
SYMBOL

FIGURE

PARAMETER

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

UNiT

tlPH

Input ready pulse HIGH

4

5

12

5

12

ns

tOPH

Output ready pulse HIGH

8

5

12

5

12

ns

tORD

Output ready I HIGH to Data Valid

5

tAEH *

Shift Out I to AF/E HIGH

11

100

145

100

18

ns

135

ns

20

tAEL *

Shift In I to AF/E l.OW

11

450

650

450

600

ns

tAFL *

Shift Out I to AF/E LOW

12

450

650

450

600

ns

tAFH *

Shift In I to AF/E HIGH

12

100

1.45

100

135

ns

tHFH *

Shift In I to HF HIGH

13 .

280

380

280

360

ns

tHFL *

Shift Out I to HF LOW

13

280

380

280

360

s

A

14

30

14

25

ns

tpHZ

Output Disable Delay

tpLZ

A

14

30

14

25

ns

tpZL

A

14

30

14

25

ns

A

24

50

24

38

ns

Output Enable Delay

tpZH
Note: Input rise and fall time (10%-90%) ::: 2.5 ns.

*

See timing diagram for explanation of parameters.

S/67413A/67413
Standard Test Load

Design Test Load
sv

ir-

.OUTPUT .... ....

..v .

R2

IOL

R1

R2

24mA

2000

3000

12mA

3900

7600

8mA

6000

12000

2Kll

Itl

.. TEST POINT

30pF

TypicallCevs TemperatUre
(Vee = MAX)

Input Pulse Amplitude = 3V
Input Rise and Fall Time (10%-90%) = 2.5 ns
Measurements made at 1.5 V
OUTPut
CONTROL
(Low-level
enabling)

230
220

~----3V

I'"
I
I

1

210

t'-..

'\

~

i

",413A(VCC =5.5V)

I

200

I
I

ICc(mA)

.",,-

190
WAVEFORM 2

I

1.SV

1

190

I

Figure A. Enable and Disable

170

Waveform 1 is for an output with internal conditions such that the output is
low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is
high except when disabled by the output control.

67413/A (Vcc

~

""I'"

=5.25 ~ ~

I
I
1

160

IIIIonoIIthlc·W Memories

-55 -50

75
-25
50
o 25
CASE TEMPERATURE rCI

'"

100

125

67413
Absolute Maximum Ratings
Supply voltage VCC ............ : ........................................................................... -0.5 V to 7 V
Input voltage ................................................................... ; .......................... -1.5 V to 7 V
Off-state ou'tput voltage .............................. ,. . . . . . . . . . .. .. . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . ... -0.5 V to 5.5 V
Storage temperature .................................................................................... -65 0 to + 1500 C

67413 Operating Conditions Over Temperature Range
SYMBOL

FIGURE

PARAMETER

MIN

COMMERCIAL
TYP

MAX

5

5.25

V

75

°c

UNIT

VCC

Supply voltage

4.75

TA

Operating free-air temperature

0

tSIHt

Shift in HIGH time

1

16

ns

tSILt

Shift in LOW time

1

20

ns

tlDS

Input data set up

1

0

ns

tlDH

Input data hold time

1

25

ns

tSOHt

Shift Out HIGH time

5

16

ns

tSOL

Shift Out LOW time

5

20

ns

tMRW

Master Reset pulse t

10

35

ns

tMRS

Master Reset to SI

10

35

ns

67413 Switching Characteristics Over Temperature Range
SyMBOL

PARAMETER

FIGURE

MIN

COMMERCIAL:
TYP

MAX

UNIT

fiN

Shift ihnHe

1

25

MHz

tlRLt

Shift In I to Input Ready LOW.

1

12

28

ns

tlRHt

Shift In ! to Ir1put Ready HIGH

1

14

25

ns

fOUT

Shift

25

MHz

O~t r~t~

DC

5

DC

tORLt

Shift Out'! to Output Ready LOW

5

12

28

ns

tORHt

Shift Out j to Output Ready HIGH

5

14

25

ns

tODHt

Output Data Hold (previous word)

5

tODS

Output Data Shift (next word)

5

40

ns
ns

10

ns

tpT

Data throughput or "fall through"

4,8

51.0

750

tMRORL

Master Reset j to Output Ready LOW

10

18

30

ns

.tMRIRH

Master Reset! to Input Ready HIGH

10

21

30

ns

..

tMRIRL

Master Reset.! 'Input Ready LOW*

10

18

30

ns

tMRO

Master Reset j to Outputs LOW

10

32

55

ns

Note: Typical is measured at 5 V, 25°C.

*

t

If the FIFO is not full (IR High),

'M'R' low forces

IR low, followed by-IR returning high when

MR goes high.

See AC test and high-speed application note.

Mo~olithic

m

MemorieS

67413
67413 Switching Characteristics Over Operating Conditions (continued)
SYMBOL

PARAMETER

Input ready pulse HIGH

tlPH

FIGURE

I

MIN

COMMERCIAL
TYP

4

5

12

5

12

MAX

UNIT

ns

tOPH

Output ready pulse HIGH

8

tORD
tAEH *

Output ready I HIGH to Data Valid

5

Shift Out I to AF/E HIGH

11 ..

100

145

ns

tAEL *

Shift In I to AF/E LOW

11

450

650

ns

tAFL *
tAFH *

Shift Out I to AF/E LOW

l2

450

650

ns

Shift In I to AF/E HIGH

12

100

145

ns

tHFH *

Shift In I to HF HIGH

13

280

380

ns

tHFL*

Shift Out I to HF LOW

13

280

380

ns

A

14

30

ns

tpHZ

Output Disable Delay

ns

20

ns

tpLZ

A

14

30

ns

tpZL

A

14

30

ns

A

24 .

50

ns

Output Enable Delay

tpZH
Note:

*

Input rise and fall time (10%-90%)

='

2.5 ns.

See timing diagram for explanation of parameters.

Monoillbic

W M~mor/~s

7-61

5/67413./67413
Electrical Charac~eristic" ()ver Operating Conditions
"

SYMBOL

PARAMETER

VIL

Low-level input voltage

V1H

High-level input voltage

,

MIN TYPMAX UNIT

TEST CONDITION
,

.

O.st

II : -1SmA

V
V

2t
-1.5

V

-250

pA

Vie

Input clamp voltage

Vee: MIN

111-

Low-level input current

Vee: MAX VI: 0.45 V

IIH

High-level input current

Vee : MAX VI : 2.4 V

50

p.A

II

Maximum input current

Vee: MAX VI: 5.5V

1

mA

,

10L (Data outputs)

VOL

,Lo~-Ievel

output voltage

Vee: MIN

57413A

12mA

67413A

24mA

10L(IR,OR)

5/67413A,
67413

SmAtt

10L (Flag outputs)

5/67413A,
67413

SmA
-'3.0mA

10H (Data outputs)
VOH

High-level output voltage

Vee: MIN

0.5 .' V

5/67413,
67413

10H (lR,OR)

-O.gmA

2.4

V

-0.9mA

IOH (Flag outputs)
"

lOS
1HZ

Off-state output current

vee: MAX vo: 2.4 V

-90 mA
+20

p.A

20

p.A

""240

mA

Vee: MAX Vb: 0.4 V

III
lee

-20

Output short-circuit current" Vee: MAX Vo: OV

Supply current

Vee: MAX. Inputs low, outputs open (5/67413A/67413)

Nat more than one output should be shorted a.t a time and duration of the short circuit should not exceed one second.

••

See curve for ICC lIS. temp.

t

1here are absolute voltages with resPect to GND (PIN 8 or 9) and Includes all overshoots due 10 lest equipment.

tt care should be taken 10 minimize eo much' eo possible Ihe DC and capacllill9 load On IR and OR 'when opatating al frequencies aboll9 25 MHz.

Functional Description
Data Input
After power up the Master Reset is pulSed 16w (Figure 10) to
prepare the FIFO to accept data in the, first location. Master
Reset must be appli~d prior to use to ensure proper operation.
When Input Fleady (11'1) is HIGH the 1irstlacetion is ready to
accept data from the Ox inputs. Data tlTen present at the data
inputs is entered into the first location when the Shift-In (SI) is
brought HIGH. A SII'iIGH signal causes the IR togo LOW. Once
data is entered into the first cell, the tranSfer of data ,in any full
cell to theadjatent (downstream) empty cell is automatically
activated by an on-chip control. Thus data will stack up at the
end of the device (while empty locations will "bubble" to the
front when data Is shifted out). tpT defines the time required for
the first data to travel from input to the output of a previously
empty.device. When SI is brought LOW and the FIFO is not full,
IRwili go HIGH, iridicatingmore room is availabr~.lfthe memory
'
is fuil,lR will remain LOW.
Data Output
Data is read from the Ox outputs. When data is shifted to the
output stage, Output Ready (OR) goes HIGH, indicating the

presence of valid data. When the OR is HIGH, data may be
shifted out by bringing the Shift Out(SO) HIGH. A HIGH signal
at SO causes the OR to go LOW. Valid data is maintained while
the SO is HIGH. When S0 is brought LOW the upstream data,
provided that there is valid upstream data, is Shifted to the output
stage. \/Iihen new valid data is shifted to the output stage, OR
goes HIGH. If the FIFO is emptied, OR stays LOW artd Data
outputwilinOl be valid.
'
Input Ready alldOutput Ready may also be used as status
signals indicating that the FIFO is completely full (Input Ready
stays LOW for at least tfIT)orcomplet$ly empty (Output Ready
stays LQWfor at leasttPT).

AC Test and High-Speed App. Not••
Since the F.IFO Is a very-high-speed device~ care must be exercised Inthe design of the hardware and the timing utilized with in
the design. The internal shift rate of the FI FO typically exceeds
60 MHz in operation. Device grounding and decoupling is cru,oial to, correct operation as the F.IFO will reSpond to very sm~1
glitches due to long,refleotive lines,high capacitances and r
poor supply decOupling and grounding. Monolithic Memon .
recommends a monoiithic ceramic capacitor of 0.1 I'F direc Iy
bet~en Vee and GNDwith very short lead length. In addition,

S/67413A/67413
care must be exercised in how the timing is set up and how the
parameters are measured. For example, since an AND gate
function is associated with both the Shift-In-Input Ready
combination, as well as the Shift-aut-Output Ready combination, timing measurements may be misleading, i.e., rising edge
of the Shift-In pulse is not recognized until Input Ready is HIGH.
If Input Ready is not high due to (a) too high a frequency, or (b)
FIFO being full or effected by Master Reset, the Shift-In activity

will be ignored. This will affect the device from a funcitonal
standpoint, and will also cause the "effective" timing of
Input Data Hold time(TIDH) and the next activity of Input Ready
(TIRU to be extended relative to Shift-ingoing HIGH. This same
type of problem is also related to TIRH, TORL and TORH as
related to Shift-Out. Data outputs driving a bus should be limited
to 10 MHz frequency. For high-speed applications, proper
grounding technique is essential.

1--------lIIi N - ' - " - - - - - - - - l - - - - - - - -IIfIN----'"-,.,-"--1
SHIFT IN

INPUT READY

Figure 1. Input Timing

1-----'---(40"5)28.6"5-----_1__-----(40"5)28.6"5-'-_---_1
SHIFT IN

INPUT READY

Figure 2. Typical Waveforms for (25) 35 MHz Shift-In Data Rate [(57413A) 67413A]

' '..LI,_ _~
~

SHIFT IN

r-

~

\'

1

\

\~-----+-'~~------------------

INPUTREADY~~~--------------t~~~~~~~~~~_3

____________________

l

~ ~_======·~:,,~/r_-_--~=5-_--_--_~_-_--_
___

INPUT DATA , _ - S T A B L E DATA _ _ _ _ _ _ _ _....._ _ _ _ _ _ __

Figure 3., The Mechanism of Shifting Data into the FIFO

CD
(1)

CD
CD
CD

Input Ready HIGH indicates space is available and a Shiff-In p'ulse may be applied.
Inp,ut Data is loaded into the first word. The 'Data from the first word is released for "fall-through" to second word.

_~

Input Ready goes LOW indicating the first word is full.

Shift-In going LOWallows Input Ready to sense the status Of fi'rst word. The first word is now 'empty as iridicatedl)y Input Ready HIGH,
If the second word is already full then the data remains a~ the first word. Since the FIFO is now ,full Input Ready remains low.'
Note: Shift-In pulses applied while Input Ready is LOWwili be ignored (See Figure 5).

Monolithic

m

Memories

7·63

S/87413AJ'87413

,

\~.__~------------~r~r--~~----~--~"~"'-4+---....:.....::.....------...:,---,---------------,---,...,..-----"'''\
...___
SHIFTINy,..
•..

INPUT READY

-:-

)J

~1••~----------tPT----------~~~/~~;~---~-~-P-H-...,..-.~~'"
.

_____________

..J~

INPUT DATA _

...._____-'.$_TA_I_L_E_.DA_T_A_-_--'-_-_-_-_....

FI.Slure 4. Dlta Is Sh.lfted In Whenever Shift In. and Input Ready are Both HIGH

.

,',':

.'

,.'' '

\

:HDt-6600-8/HD1-1660S-8
HD1-6600-S/HD1-660S-S
;
HP1 :.aSOO-2/HD1-660S-2

Useful to "power down" devices
to reduce totar system power

,

MonoIilhicW.emories

14

8-27
8-S1
8-S1
8-S1
8-S1
8-61
8-61
8-61

Improving Your Memory With
'S700-Family MOS Drivers
Chuck Hastings and

Su,,~eIRajpal

Introduction
Today, fast-access-time high-density dYnamic . randomaccess-memory integrated circuits (DRAMs) are where it's at
in the design of commercial computer memories of any size,
fromtabletop personal-computer memories to giant mainframe
memories; magnetic cores are, now, "but a distantmemory,"
As a, 'computer~scene coroilary to Parkinson':> First' Law r1 ,
"Work' expands to fill the time available," it is observably
always. true that. "Computer software expands to fill the
memory available, .. Thus; the rapid advancements ~hich have
been made in the cost, density, availability, second-!10urce"
standardization, and reliability of DRAMs have generally
come just in the nick of time to keep.upwith the computer
industry's insatiable demand for ever-larger main memories,
To pick but one e~ample, the Hewlett-Packard 3000-series
minicomputer family was originally introduced wilha maximum
main-memory configuration of 131,072'bytes;today, the maidmum configuration is 8,388,608 bytes" and plans for even
larger configurations are already taking shape,
Unfortunately,'. the technological 'advancements in the
peripheral integrated circLiits needed ,to drive. all of these
DRAMs have, to say the least, been. noticeably less·rapid, The
usual design practice has been to,drive large DRAM arrays
with high-current buffers ~uch as 'S240s,. cOlJpled with external.
series resistors in th!i drIVen signal l.ines, NoW, with the
introduction of th.e Monolithic Memories ,'s7001730/731 1734
MOS drivers, the memory designer's task is greatly simpJified. "
The'S700; '5730; "S731,'and 's734 are f,ast.ilnd,powerfUI
Schottky-technOlogy nL 8-bit buffer~,SPeciaiiied to ctriv(!
large numbers of dynamic RAMs, Their internaldesign,is
particularly well adapted to driving signal lines with lots and
lots of distributed capac;i~nce. They are ,dtop~iti, plncompatible. replacements' for the respective firSt~gener!itiQn
'S240-famfly high.:current drivers - 'S?10,'S240, '8241, and
'S244,'whichexcel forlheir inten,ded high-currentapplications
or even for lui11ped-capacitance applicatkms but can be
awkWard to use in typical' DRAf)/I memorY-board designs. '

. n: .. THE, MONoLITIIIC .M~~\ES "S:700,'Sis({ "5731,.~
'51.34. ARE .... SPECI41.IZEQTO O~IY£.LAIl/;E, NUMBEflS 'OF'

P'INAMIC IIAMS. ;,;n

,

,.

So tha.t you understand the essentials of what you need to
know to. design memory boards whii:h Wprk, we'll first take a
quick glance at the electrical. situation, co(T1plete with equations.
Oon't worry- we won't actually derive these e~uatiOI)S here;
d~ri",ations are readily available in theliteratur~ ,r3,and our
purpose is simply to motivate some otherwise arbitrarysounding statement&'as to wba,t constitutes. good layout
practice. Following that, we'll. presemt the rationale behind the~
various members of the family and their differing functional
behavior or "architecture." Finally, we'll discuss some pragmatic
desi,gn issues; hoVi to a"Clid information loss due to glitches in
battery-backup-protE!cted memory systems d:uring power
failure, and when .and where,to)!se:the ~S700.and:'S7;31
complenientary"enaple parts.

The Memory-Board Design Problem
The central problem facing the. designer of amemory board is
to Cfrive a large number of highly..{;aplicitativeDRAM address,
data, and CO,ntrolinputs' just as fast ast'hey can safely be
driven, since memory speed ,(like memory Size) is something.
which computer"system designers can never get quite enough
of. Typically, a designer places from 70 to 300 DRAMs on a,
single poari:J, Now, the address and data inpufsofa DRAM
have very non"negijgible input capaqitances- 3;!)pi~Wa(J.S
(pf) typical, and 5 or even 7 pi worst-case; the control inputs
may have as muofl as'lOp(worst-cas~.PiSsuming 5. pI; the
totalcapacitimceper addressor deitaline per board must by
simple multipiication falibetween:J50 pf arid 1500 pf .c:c. even
. more whenthecapacitailce of tl)e printed-circuit-board (PCB)
wiringttaces is reckoned with. These numbers are not at all
the sort of nui11bersy6u normally see on the, data sheets .for
moS!of'theindustry-standardB-bit buffers -those have fOr'
many years conventionally been.specl1iedby'all vendors at 15'
pf, ,50 pt,. etc. apparently according to the prOposition·th:a:t
"small is'beautiiul,' I.e., the logic delays and waveformS come
out more ,agreeably at those numbers: ' ,.
.
In keepi~g.with ···motherhood and apple pie, the memo~­
board design obviously must be optimized for speed; reliability,
physical area, and dollar cOst; the topology (the physical
organization and length of the wiring tr!iqes) and thEl number
of drivel'SareChoSen accordingly.S'fnce contemporatj( DRAMs
r~cei'iie their ()oni'plete addresses In two pieces, a "row. address"
and a"colurl1n addr~sU(corresponding to. the cell. layout
within the DRAM chip), thespel3dofthe addresscdriving
circuits is parlicularly.pijicilJ sinc~ the, bit pattern transmitted
on the addres$ lines must b~ changed tWice during each
complete memory read or write cycle. In DRAM "architecture:
the row and coJurnn addresses are,ofequallehgth, say, 0' bits,
and the width: of the data Word,within the DRAM !Sone bffin
most con1empbraryparts. The'first DJilAMs,witl1 th'isarcl1itecture;
in the m[<;H970si had n "6; and thll~>werl!212x1= 4096x1dr
"4K" DRAtIIls. By n9w, of course; such tiny DRAM sites are'

....

.-:-II

Improving Your Memory with 'S700·FamilyMOS Drivers
,

obsolete, and even 16K (16384x1) DRAMs are a super-Iowcost commodity.· Much commercial deSign today is being
done with 64K (65536x1) DRAMs, and even larger DRAMs are
coming soon; 256K (262144x1) DRAMs pin-eompatible with
the usual 64K types have been announced.

Zo

= the c;;racterist(iC

'~

.

~= ,im),Pedance .

- - - - In . - - - ohms
. O.EiW-tt '

Je r +1.41

Td= the trace propagation velocitY.
When all of these factors are taken into aC90unt, the practical
upper limit to how many. DRAM inputs can be hung on one
trace is. usually thought to be in the range of 80 to 100. This
limit has some implications with respect toword length ancj
word organization. The combin.ed effect of the system word
length as seen by the computer programmer, the number of
check..cooe bits used for whatever checking scheme is employed,
and the num~r of different words simultaneously acceSsed o.n
one memory operation is to make certain .odd-sounding total
word lengths popular:

Organization

Total
Word
Length

Data
Word
Length

Check
Blts/
Word

Checking
Scheme

17x4

68

16

1

Simple parity

72x1

72

64

8

Hamming code

39x2

78

32

7

HamminQ code

22x4

88

16

6

Hamming code

Table 1. CommOn DRAM Memory-Board Organizations

A..umptions and Equations
The. key to good memory-board design is optimization of the
layout and impedance of the wiring traces, and the choice of
efficient RAM drivers. In prototype wirewrapped boards, the
characteristic impedance of. a wire which is at a varying
distance from a ground plane as it crosses hill-and-dale over
other wires may. be difficult to control or predict, but is likely to
be within the range 01.100 to 120 ohms. In production memory
boards, however,. it is often a good approach to use microsirips
to interconnect the array of DRAMs. A microstrip is simply a
PCB wiring. trace over a ground plane, separat8d from that
ground plane by a thin layer of insulating medium such as
fibElrglass. A cross section of a microstrip is Shown iriFigure 1.

'~~r+

= 0.0848 J 0.475e r + 0.67 nsec/inch
Co

= the trace cl;lpacitance.
= 1000 (Td/Zo) pflinch

Cd

"the equivalent trace capacitance associated with each
DRAM. It takes 0.5 inches to interconnect one DRAM.
'=

3.5 pflO.5 inch = 7 pflinch

Z'o= the modified trace'iinpedance due to the capacitive.
loading of the DRAMs.
.Zo

J 1 + Cd/Co
T'd

= \he modified trace propagation time due to the
capacitive loading of the DRAMs.
= Td

Where:
e r = the
h = the
w = the
t
= the

J1 + Cd/Co

relative dielectric constant of the PC board.
distance from the trace to the ground plime.
width ()f the trace.
thickness of the trace.

Design Approaches and Their
Consequences
Very well then, let's charge right in and see what these
formidable-looking equations predict will happen when a memory
board is laid out in an obvious, common-sense manner. To
make the example specific, we choose the 39x2 organization,
so. that from a circuit point of view tlie word length on the
memory board is 78, bits. Now:, each wiring trace has a
capacitance (CTRACE) and an inductance (LTRACE) per
DRAM; assuming that the DRAMs are deployed at uniform
intervals along the trace, these values are.determinable easily
from the values per-un it-length from the microstrip equations
just presented, once the spaCing in inches between DRAMs has
been specified. (The value for LTRACE has been buried in the
equation for Zo above and won't appear in any subsequent
equations.) To be specific, we'll make the realistic. assumption
of one DRAM per 1/2 inch of trace. Each DRAM input also has
a capacitance (CORAM) and an inductance (whicI1Yie're justified in neglecting); we'll assume that these are uniform, although
the most sophisticated designers 'consider .distributions of
DRAM capacitances. The electrical situation which results is
shown in Figure 2:
39 INcHElss----.~-~·'1
~
LTRACE

I-

figure 1. MIcroIlrlP CI'OIII SectIon
The equations needed to design a memory board for a DRAM
array interconnected by microstripsare listed below. Their
rationale and derivation can be found in references. on the.
application of electromagnetic field theory to circuit-board
.
designr2, r 3 . ,

' <240 .ctRACa 1 cTRACal
DRIVER

J

ICoRAM llCDRAM

------DRAM # 1

-=n
J

DRAM # 2

tDRAM

------DRAM # 78

figure 2. Tranamlsslon-Une Equivalent of a
SIngle DRAM Wiring

nac:e

Improving Your Memory with 'S700-Family MOS Drivers
Typically, this trace has the following .characteristics:
er
h
w
t

=
=
=
"

switch S may be thought of as in position #1; when it is driving
Low, S is in position #2. The effective output impedance of the
'S240 is thus about 30 ohms when driving from a previous Low
state to High, but only about 10 ohms when driving from High
to.Low - a 3:1 difference. Thus, as the large lower transistor in
the output 'totem-pole" structure turns on very fast because of
this low impedance, the fall time is extremely fast, and when
ringing occurs the result may be undershoot ~ the voltage in
the trace actually falls below ground.

5 (for G 10 glass epoxy)
.30 mils
15mils
3 mils

The following values can then be calculated using the
approPriate equations:
20 =
Td =
Co =
20'=
Td' =

85 ohms
0.15nsec/inch
1.76 pflinch
38 ohms
0.35 nsec/inch

An obvious consequence of ringing in the signal trace is that
the system designer must allow much longer for the driver
voltages, as seen by the DRAM inputs, to settle down after a
transition since the ringing may be severe enough to repeatedly
cross the switching threshold for the DRAMs. If this settling
only had to happen once per memory access it would be bad
enough, but it happens twice - remember that first the row
address, and then the. column address, gets transmitted over
the address lines. Thus the allowances made for ringing cause
memory performance, as measured by access time and/or cycle
time, to significantly deteriorate.

If we just string the DRAMs right down the trace like Christmastree lights, it will take 39 inches of trace to connect all 78 of
them. So the actual propagation delay of the drive signal as it surges
down this trace will be Td'times 39 inches, or 0.35x39= 13.7 nsec.
Notice that we are embarked on a design which is specific to
the properties, including CORAM, of. DRAMs which we are
using; a final board design is inevitably, to some extent, "tuned"
to a specific DRAM type. If CORAM changes, even in what
might be considered the favorable direction (smaller, obviously!),
the trace impedance gets changed and the design may no
longer be "tuned." But we won't worry about that here.

vcc

,t
vcc

3Dll

-+-os

21.. s

'Oll

Now, an 'S240 driver, such as we have assumed to be driving
the trace, has a signal rise time or fall time of anywhere from 2 nsec
to 10 nsec, depending on semiconductor manufacturing
parameters. (The rise lime is, to be precise, defined as the time
it takes for the output voltage to go from .10% of fu II-scale to
90% of full'-scale;the fall time is the obvious converse.) A good
rule-of-thumb for circuit-board designers is that twice the
propagation delay of the trace should be .Iess than the rise time
or fall time of.the driver in order to avoid .serious signal ref/ections, in which a "reflected" electromagnetic wave comes
bouncing back from the other end of the trace. In other words,
2x13.7 nsec + 27.4 nsec must be less than 2-to-10 nsec, which it
obviously isn't. Hence there .will be reflections on this line, and
ringing of the Signal will occur, resulting in a waveform in the
trace which looks like that of Figure 3 for a High-to-Low transition at the 'S240 output. The .amplitude of the ringing voltage
in real systems· may be· as much as 2v or even 2.5v.

=

1; LOGIC
... HIGH

s= 2; LOGIC LOW

Figure 4. Typical Schottky-Driver Output Impedances
Even worse things can happen because of undershoot. First, if
the voltage as seen by.the DRAM inputs ever falls below -1.av,
that is, more than a volt below the steady-state PCB ground
voltage at the DRAM ground pins, the contents of the "rowaddress. registers" within the DRAMs can be .altered. (Some
DRAMs are supposed to be able tostand-2vfor 20 nsec, but
others just can't handle it.) Thus,. if a write oPeration is in
progress, the data word can get written helter-skelter into
different .address locations in· different DRAMs (remember,
each DRAM is just 1· bit wide!), so that the entire memory
system very rapidly forgets everything it once knew. Second,
the current surges resulting from severe undershoot may cause
some 'S240-type drivers themselves to rather quickly· selfdestruct, which can be particularly annoying if they have been
dip-soldered into place.

"HIGH"
LOGIC
LEVEL

At this point it appears that our. simple, common-sense first cut
at memory-board layout is a naive recipe for disaster. So what
can we do to imprOVe on this naive approach and get the
memory bO,ard to work?

t,

=

First, we can series terminate the trace with a to-ohm resistor
to improve the impedance match. "Series termination"simply
means that the resistor is located right at the 'S24O output,
between it and the rest olthe trace. 10 ohmS is probably the
minimum value for this resistor; othervaluesof up to 33 ohms
are also in use, according to the deSign context.

TIME TO AN ACCEPTABLE ZERO.

Figure 3. Une Ringing Due To Driver Mismatch
An 'S240 has a Schottky-driver output stage which may
simplistically and approximately be represented as shown in
Figure.4. When the 'S240 is driving to the logic High state, the

IIIonoIHhlo

Second, rnuch of our problem ca(l1t;l about t;>ecause of the
sheer physical length of the trace, so we can mOdify the
topology to cut that in haif by having two "legs" rather than just

m

Memories

8-5

Improving Your Memory with 'S700-FamUy MOS Drivers
one off the driver output, which should essentially cut the
propagation time for the trace in half.

The 'S700-Family Drivers to the Rescue

Third, if need be, we could also vary the trace width, w, to change
the trace impedance, Zo' to a value more to our liking, in order to .
fine-tune the design, but we won't pursue that possibility here.
The result is the significantly-different layout of Figure 5, with
all of the cute little capacitors and inductors omitted for clarity
(or actually for sheer laziness):

I'"'. . . - - - - - - 1 9 . 5 ;n··---_ _ _......".I

~~~--~------------~--------Figure 5. An Improved Layout

When the calculations are repeated, it turns out that the
propagation delay down each leg of the trace is half as much,
or 6.9 nsec; and the output impedances of the 'S240-plusseries-resistor are now 40 ohms when driving from Low to
High, and 20 ohms when driving from High to Low, which is
only a 2:1 difference. The trace impedance seen by this 'S240plus-series-resistor is that of two 38-ohm legs in parallel, or 19
ohms, which is a very much better match to its effective output
impedance. Also, the .series resistor acts to slow down the
exceedingly-rapid fall time of the 'S240, to the point where it
may not be a great deal less than (or may even exceed) twice
the trace propagation delay. So, ot;>viously, we're a lot better off
than we were.
Unfortunately, we're still not home free. We've also slowed
down the rise time of the 'S240, i.e., the Low-to-High transition,
which we weren't intending to do since it wasn't a problem.
What we really would like is for the Low-to-High transition time
and the High-to-Low transition time to become virtually the
same, i.e., "symmetric." Now, DRAM addresses and data have a
generally unpredictable salt-and-pepper mixture of ones and
zeroes, and there is no way to take advantage under system
conditions of a circuit design with one of these transition times
much faster than the other. So computer-systems people, who
have to be brutal realists rather than cockeyed optimists if their
systems are to work reliably under real-world assumptions,
normally just take whichever of these two transition times is
"worse" (that is, longer) as the "logic delay" of the part as it
operates within a system. Which is only reasonable! And thus
it comes about that a deterioration. in transition-time symmetry
translates as a deterioration in net system speed.
So what do we do next? Well, we could try applying the same
improvements a second time, by breaking the trace into four
legs; however, physically interconnecting these four legs then
will add more trace length, so that topology has to be traded off
against interconnection efficiency. What would just get us out
of this whole mess is if we. could get inside the 'S240 and put
the series resistor someplace where it will result in the effective
output impedance of the driver being the same whether it is
driving from Low-tcrHighor from High-Io-Low. But we can't do
that. Can we? Can we???

8-6

IIIonollthlc

Well, we can't exactly get inside an 'S240 and stick in a series
resistor. We can, however, pull the 'S240 out of the socket it is
occupying, and pop in an 'S730 - which is a pin-compatible
drop-in replacement, and has the series resistor in exactly the
right place. If we had been using a different 'S240-family driver,
we could still have done the same thing - an 'S734 replaces an
'S244, an 'S700 replaces an 'S210, and an 'S731 replaces an
'S241; more on the various part types shortly.
When thus popped in as 'S240-type driver replacements, 'S700,
'S730, 'S731, and 'S734 drivers will generally speed up the total
effective access and cycle times for most DRAM boards. This
speed improvement is ach ieved by a sophisticated, rather than
a brute-force, circuit-design approach. We've already let the cat
out of the bag; they feature a new type of output stage,
incorporating a built-in series limiting resistor, designed to
efficiently drive highly-capacitative loads such as arrays of
DRAM inputs interconnected by typical printed-circuit-board
(PCB) wiring traces. This series resistor is located in the ideal
place - between the collector of the lower output transistor in
the totem-pole structure and the output pin. (See Figure 6.)

DRIVER OUTLINE
-------,
VCC
I

INTERNAL SERIES
LIMITING RESISTOR

I

I
I

/

.

WHERE THE EXTERNAL SERIES
L.IMITING RESISTOR WOULD HAVE
TO GO IF AN 'S240-FAMILY
DRIVER HAD BEEN USED
SHUNT-TO-GROUND
EFFECTIVE
CAPACITANCES
OF DYNAMIC RAMS
AND WIRING

Figure 6. The Dynamic-RAM-Driver Circuit Output Stage

Now that the all-important resistor is safely inside the drive
chip, its value is chosen as 20-25 ohms, so that the in-system
Low-to-Highand High-to-Low transition times of the resulting
driver output stage remain symmetric, with the series resistor
accounted for, under a wide range of circuit-loading conditions.
The equivalent to Figure 4 forthis new improved output stage is:

..0--0

s

21. s

2511
= 1; LOGIC. HIG.H
S = 2; LOGIC LOW

Figure 7. Driver Output Stage lor

W lIIIemorles

'S700~Series

Buffers

Improving Your Memory with.'S700.Family MOSOrivers
Whaidoes that additional resistor in the.transistor buy you?
Plenty., when coupled with the other design features incorporated
into the 'S7OO, 'S73O,· 'S731 , and 'S734. First, there is a balanced
impedance of about 25 ohms for· either the Low-to-High
transition or the High-to-Low transition. Since the effective
impedance for the Low-to-High transition is now considerably
higher than it was when using an 'S240, the undershoot
problem goes away - the output voltage can never have an
·undershoot worse than 0.5v. Ringing can still occur; however,
the time taken to reach an aeceptable zero level is smaller than
it was when using an 'S240, as shown in Figure 8..
Another adVantage olthe 'S700;'S730,'S731, and 'S734 is the
high-state output voltage, now guaranteed to reach at least
V -l.lSv. Certain MOS DRAM inputs are specified to require a
m~gimum "IH of 2.7 volts. More on this I!Ind other specification
issues in just a minute.
.
"HIGH" ·1
LOGIC

LEVEL

by AMD, which has also·. designated them . alternatively as
AmZ8165 and AmZ8166.
.
The othertwo buffers-the 'S700 and 'S731 "....arecomplementaryenable versions the 'S730 and 'S734 respectively, just as the
'S210 and ;S241 are complementary-enable versions of the
'S240 and 'S244. Complementary-enable parts .e.xcel in driving
buses where the information to be placed on the bus can come
from two different but physically adjacent origins, such as
inStruction addressesanddB'ta addresses in a bit-slice bipolar
microcomputer system, ot row-address fields and column~
address fields on a DRAM memory board; more on this later.

of

TheSe fo·ur new 'S700-family buffers may be grouped with
Monolithic Memories' other buffers in a 2x2 matrix chart.or
"Karnaugh map," with the dimensions of this map chosen to be
the assertiveness of the second-buffer-group enable input E2
(here across the tOPi or X-axis) and the.polarity althe databuffer logicalelernentsthemselves (here down the side, or Yaxis). This chart is Table 20f "Pick the Right 8-bit or 16-bit Interface Part for the Job: in section 13 of this databook.

for

each 'of theSe four parts are$hOwn on the
The logic symbols
first page ofthe data sheet, iii part-number order.·Except f()r the
differences already noted in the assertiveness of signal E20@lld
in the output polarity of the data biJffers, these parts are all mutually pin-compatible.
.'

11 = T!ME TO AC~EPTABLE "LOW" LOGIC LEVEL FOR THE 'S240 WITHPUT
AN EXTERNAL RESISTOR.

. .

12 =riMETo ACCEPTABLE "LOW' LOGIC LEVEi:FO~, THE 'S730.
Figure 8. COl11parisonQf

Undershoots;'~24Q

and 'S730

Undershoot control, balanced High-stilte and Low-state output
impedances, and appropriate voltage levels make the 'S700,
'S73O, 'S731 , and 'S734 very efficient RAM drivers. Consequently,
although 'S240-family buffers may exhibit greater speed under
light loading conditions and may even sink larger currents
when operated In test jigs, 'S700-family buffers are likely to
perform better under realistic system conditions when driving
large capacitive loads is a major factor in the application. There
may even be some non·DRAM bus-driving applications where
such is the case!

You will ha~e an easier time keeping these four parts straight
once you notice ttiat'the part (lumber for one particular
"architecture" .of 'S7.0Q-series buffer Is ahvays the part number
of the corresponding high-currant buffer, plus 490., Since
hundreds of 54/74 part numbers have already been aSSigned,
even thGugh riot all of the corresponding parts are yet in
production. obtaining part numbers with even this much m~thod
in the madness was not exactly a piece of cake! Anyhow; If you
want to easily remember what the part number should be when
you replace an 'S240-family buffer with an 'S700-family buffer,
you must add 490 to its part number: e.g., 'S241 + 490 = 'S731 ,
and so forth.
Like other Monolithic Memories' 20-pin 8-bit interface circuits,
the '8700 '5730'8731 and '$734 come in the celebrated 3OO-mil
SKINNy6IP~ ~ckage. They also come in eutectic-seal-flatpack
and leadiess-ehlp-carrierpackages. .

And, as small added bonuses, the de!,igner no longer has to
find "the' physical. sRace onhis/her. board 10r the. external
liiniting resistors, and the resistors, themselves no lon~er ~ave
to be paid for; and ngbody has to be paid to .,stuff them Into
place on production copies of the board. All in all, an acrossthe-board "win-win" situation.
.

Keeping t~ Family Straigh~ .
Of·the four new buff~rs in the 'S700 family, ~o '- the 'S730 and
'S734 ~ .are altemate-source versions of the· Am2965 . and
Am2966 respectively. These two parts were originally introduced

" ... THE '57.00, '5730, "!S731, .AND '5734 cOME IN. THe:
C£I.EBIlATED 300-MII. '5KINN'IPIP'" PACKAGE ... "

Improving Your Memory with 'S700-Family MOS Drivers
S700,73O

A Few Subtleties Regarding
'S700-Family Driver Specifications
If you are used to regular run-of-the-mill TtL data sheets, you shoUld
beCOme sensitive tathe fact that in several respectS the Monolithic
Memories 'S7oo-family data sheet (and, to be fair to a friendly
competitor; AMD's Am2965/6 data sheet) represents a substantial
departure from this norm.
First, since 'S7oo-family MOS drivers are Obvi~~Sly intended, to
mingle freely in the MOS world, they are specified to operate
properly witH as m!Jchasa ± 10% power-s!Jpply-level fI!Jct!Jation
over the entire commercial temperat!Jre range, instead of j!Jst
the !Jsual, TTL ± 5%. The ± ,10% standard is !Js!Jal for MOS
parts; b!Jt in the TTL world it is normally met only by ,selected
milltary.:version parts specified over the military temperature
range. Th!Js, the Vcc seen by YO!Jr commercial 'S700:.series
parts may fluct!Jate (even tho!Jgh yO!J hope it won't) fromA.50v
to 5;5Ov instead of only from 4.75v to 5.25v as for most
commercial TTL.
Sec9nd, as already mentioned, an.acceptableo!Jtp!Jt logic High
iscohsidered to be Vcc -1.15v, or 3,B5v ass!Jming that YO!Jr
power s!Jpply really is !Jnder control after all. MOSparts are
specified to think they're still seeing a Low up to O.Bv at an
input, and to be seeing a High above either 2.4v or 2.7v; in
between is, of course, the usual transitional or no-mans-Iand
region. In keeping with the needs of the MOS world, 'S7OOfamily Low-to-High logic propagation delays are measured
from when the input crosses the usual TTL threshold somewhere
in this no-mans-Iand (say 1.5v)to when the output crosses 2:7v
- not merely to when the output crosses the TTL threshold.
Likewise, 'S700-family High-to-Low logic propagation delays
are measured from when the input crosses the TTL threshold
to when the output crosses O.Bv. (See Figure 9).

r-----3.0II
S731, 734

011

II'l,H

OUTPUT

.~~~~==~~--~~========~~~~~~
" =II = 2.5ns
1=2.5MHz
Ipw=2OOns

Figure 9. S700-FamllyOutput-Voltaae-:Level
SpeclflcatlQn Conventions

Third,both minimum and maximum propagation delays are
specified '(at 25° C and 5v), so that you don't need to worry
about· any unwanted consequences in your system if your
memory-access time for some bit positions turns out to be
unexpectedly low relative to that for other bit positions. Worstcase skew between two buffer elements on the same chip is
also specified.
Fourth, ,in keeping with the pledge thatthese parts can drive
highly-capacitative lines, they are specified that way - at 500
pF loading, not only at 500 pF loading.
Fifth, unlike 'S240-family buffers, 'S700-family MOS drivers do
not feature designed-in hYl!teresis.

Power-Failure-Proof Operation of Your
DRAM Memory
It's generally nice if your computer, of whatever size, doesn't
forget everything it was in the midst of doing and remembering
if a-c power suddenly goes off. In fact, for large mainframe
computers and for high-reliability control computers it may be
.downright critical. So, increasingly, memory designs include
power-failure-protection logic, and DRAM "refresh" ci.rC;uitry
can run on battery-backup power. A typical design implementation is shown in Figure 10.
USE ·S700·FAMILY DRIVER HERE
NORMAL
ADDRESS
TO DRAM ADDRESS
REFRESH'
ADDRESS

B = BATTERY·BACKED LOGIC

Figure 10. Battery Backlip for Refresh-Address logic

The refresh operations for the memory array. must be
uninterrupted during the tranSitions from a-c power to battery
power and back, or else data will be lost; consequently, al/ of
the logic associated with the DRAM refresh operations must
be backed up. For economic reasons, other logic may not be
backed up; hence, great care must be t!!ken in the design althe
DRAM interface, so thattransients oroS5;illations are not
introduced into the DRAM input .lines by the non-backed-up
logic thrashing around as a-c power g~ down or comes back up.

" .•• 'S1(JQ

FNi'LV MOS DRIVERS.,. AgE SPEcIRED

"foOP9A1'E PRoPeRLY WJ11.I AS MIlCH AS A ±IO'%
PowCR-SIJPPt.'H.EVEL FWCTUATION OvER 'THE
EJJ1'IRe ~eRCIAL ~M(lEAA"~ RA~GE'
ItJSTEAD OF'fHEOSOAL.T1'L tSO/o ..•. " •.

8-8

Returning to Fig'ure10, notethatit is thenormai address path
which is a potentil!l source of DRAM input glitches, s.ince the
refresh-address-pilth buffet preSumably nElVer goes down.
Again 'S7OQ-family drivers can come riding to the rescue,since
they are guaranteed to maintain glitch-free operation during
either power-up or power-down.

Improving Your Memory with 'S700-Family MOSDrivers
Where to Use Complementary-Enable
MOS Drivers
Driving a dynamic-MOS RAM address bus with a multiplexed
row/column address can conveniently be done with an 'S700
as shown in Figure 9 of "Pick the Right 8-bitor 16-bit Interface
PartfortheJob," in Section 11 ofthisdatabook. This part isan inverting complementary-enable buffer with a series-resistor output structure, which is an ideal combination of characteristics
here:
First of all, a TTL inverting buffer normally has one less
transistor -and hence one less delay - in its internal data path
than does an equivalent non inverting buffer, and hence is
faster. And dynamic MOS RAMs really don't care if their
addresses come in "true" or "complemented" form as long as
that form never changes.
Second, a complementary-enable buffer can easily multiplex
two different address sources to the same set of outputs
without introducing extra switching delay, or allowing a
momentary "bus fight" condition, if the same control signal
(here CAS or "Column Address Strobe") is tied directly to both
E1 and E2' and the two 4-bit groups of outputs are tied
together.
Like other three-state buffers, these parts operate in a "breakbefore-make" manner - it is faster to disable an output than to
enable an output, by design. (The worst-case data-sheet a-c
parameters don't always imply "break-before-make" operation,
but the parts themselves do operate that way.) So, if two outputs
are tied together and exchange control Of the bus, they can't
"fight," i.e., try simultaneously to drive the bus in opposite
directions; at any given instant, one of the two will always be
"floating" in the hi-Z state.
The 8 data input lines to. each 'S700 must, of course, be
parceled out with 4 lines coming from the row address and 4
lines coming from the column address.
These same advantages continue to accrue when an 'S700 is
used, for example, to select between instruction addresses and
data addresses' in a minicomputer, or between next-microinstruction and branch addresses in a microengine, or between
input and output addresses in a multiplexed input/output data
channel, assuming that in each of these cases the address
being produced is to go to the DRAMs without further ado.
Notice that the 'S700s here are accomplishing driving (that is,
power amplification and impedance matching) and multiplexing
simultaneously. You could have used an MSI multiplexer part
followed by an '8730 to accomplish this very same thing, but
with more logic delay.
If what you need in your application is a non-inverting driver,
then everything we've just said above about the'S700 continues
to hold for the '8731.

IIIIonoIlthlc

The Bottom Line
The '8700, 'S73O, 'S731 , and 'S734, because of their unique
output stage with an internal series resistor and balancedimpedance characteristics, can drive highly-capacitive loads of
up to perhaps 100 dynamic-MOS RAM inputs. Since undershoot
is limited to -0.5v already and so no external series limiting
resistors are needed, the result is a net system speed gain,
since Low-to-High and High-to-Low transition times remain
symmetric. Otherwise, the logic delay would get degraded,
since it must always be taken as the worst of these two
transition times, and the use' of an external series resistor
greatly lengthens the Low-to-High transition time.
These second-generation MOS drivers also guarantee an
output High voltage of VCC -1.15v, and provide glitch-free
operation during power-up and power-down. All of these
featur!'lsmake them especially suitable for driving the address,
data,and controllines.of arrays of MOS DRAMs.

Credit Where Credit Is Due
A couple of years ago, many Monolithic Memories customers
approached us with the emphatiC suggestion that we should
produce MOS drivers of this type, backed up by technical
arguments which we have attempted herein to distil and
present. In particular, the advice and assistance of Tak Witanabe
of the Hewlett-Packard Computer Systems Division in Cupertino,
California, has been utterly essential in the preparation of this
application note.
Also, it was originally at Tak's suggestion that Monolithic
Memories decided to produce the '8700 and 'S731
complementary-enable drivers, as well as the 'S73O and '8734
assertive-low-enable drivers. Tak's contributions, and those of
other sage electronics-industry designers with whom we have
spoken, are hereby gratefully acknowledged.

References
r1. Parkinson's Law and Other Studies in Administration, C.
Northcote Parkinson, Houghton Mifflin Company, Boston,
MA, 1957; also Ballantine Books, N.Y.,1964.
r2. MECL System Design Handbook, William R. Blood, Jr.,
Motorola Semiconductor Products Inc., Mesa, AZ, May
1983 (Fourth Edition); see in particular chapter 7.
r3.

"Characteristics of Microstrip Transmission Lines," H. R.
Kaupp, IEEE Transactions on Electronic Computers, April
1967 (\Qlume EC-16, Number 2); pages 185-193.

m

Memories

8-9

Dynamic RAM
Controller/Driver

SN74S40S/DPS408
SN7 4S408~2/DPS408·2
SN74S40S·3/DP840S·3
Ordering Information

Features/Benefits
' .. All DRAM drive functions on one chip have on-chip high-'
cipacitance-Ioad drivers (specified up to 88 DRAMs)
• Drives directly all 16K and 64K
addressing up to 256K words

DRAM~: Capable 01

• Propagation delays 01 25 nsec typical at 500-pF load '

PACKAGE

TEMPERATURE

SN74S40B

N4B; D4B (L52)

COM

SN74S40B-2

N48, 048 (L52)

COM, SPEED OPTION

, SN74S408-3

N48, 048 (L52)

PART NUMBER

• Supports RE~D,WRITEand READ-MODIFY-WRITE cycles
• Six operating modes support extemally-controlled access
and relresh, automatic acCess, as well as special memory
Initialization access

COM, AC OPTION",

Pin Configuration

• On-chip 8-bit refresh cou"nter with selectabie End-ol-Colint
(127 or 255)

RIC

I

CASIN

2

• Direct replacement lor National DP8408'

,
MODE

M2 (RFSH) 5

MODE OF OPERATION

ADS

Externally-controlled relresh

0,1,2
3

Externally-controlled AIl-RASwrite

4

Externally-controlled access

5

Auto access,slow tRAH

6

Auto access, fast tRAH

7

Set end of count

SYSTEM
CONTROL

SN74S408

RAM
CONTROL
6

10

749408
SYSTEM

18
SYS-':\OM
ADDRESS

DYNAMIC RAM
CONTROLLERI
DRIVE

SOOpfDRIVE

MEMORY

8
RAM
ADPRESS

"61< or 14k
DYNAMIC
RAJiI aANKS

74S408lnterface: Between:Systern and DRAM, 'Banks

NC = NO CONNECtiON
Portions of this Data Sheet are reprinted courtesy of National SemicondLictor Corporation.

TWX: 910-338-2376
2175 Mission Conege Blvd:Sanla ciara, CA95054-1592 Tel: (408r970~9700 'TWX: 910-338-2374'

8-10

___"'hle l!T!n
.emorles '1rWUI

SN74S408/DP8408 SN74S408·2/DP8408·2 SN74S408-3/DP8408·3
Block Diagram
RO-7 _ _~

ROW
ADDRESS

\

INPUT LATCH

~--~;f~
I

HIGH CAPACITIVE DRIVE
CAPABILITY OUTPUTS
WHEN ENABLED

I
I

........ QO-7

'

I

a-BIT
REFRESH
COUNTER

......_

I

'INDICATES THAT THERE
IS A 3kn PULL-UP
RESISTOR ON THESE
OUTPUTS WHEN THEY
ARE DISABLED

I

I
I

REFRESH

r - - r - - L ) - - - - . - RAS 3

RAS
DECODER
B1 BO _

BANK SELECT
INPUT LATCH

RASO

Cs_
RASIN-

R/CCASIN_

WiN

-----+---+---t---r------t>--WE
RF 1/0

M2 (RFSH)

Ml

MO

Figure 1. 745408 Functional Block Diagram

Description
The 74S408 is a Multi-Mode Dynamic RAM Controller/Driver
capable of driving directly up to 88 DRAMs. 18 address lines
allow the 74S408 to drive all 16K and 64K DRAMs and addresses up to 256K words. Since the 74S408 is a one-chip
solution (including capacitive·load drivers), it minimizes
propagation delay skews, and saves board space.
The 74S408's 6 operating modes offer extemally-controlled
or on-chip automatic access and externally-controlled
refresh. An on-chip refresh counter makes refreshing less
complicated; and automatic memory initialization is both
simple and fast.
The 74S408 is a 48-pin DRAM ControlierlDriver with 8
multiplexed address outputs and 6 control signals. It consists of two 8-bit address latches, an 8-bit refresh counter,

and control logic. All address output drivers are capable of
driving 500pf loads with propagation delays ·of 25nsec. The
74S408 timing parameters are specified driving the typical
load capitance of 88 DRAMs, including trace capitance.
The 74S408 can drive up to 4 banks of DRAMs, with each
bank comprised of 16Ks, or 64Ks. Control signal outputs
RAS, CAS, and WE are provided with the same driving capability. Each RAS output drives one bank of DRAMs sothat
the four RAS outputs are used to select the banks, while
CAS, WE and the multiplexed addresses can be. connected
to all the banks of DRAMs. This leaves the nonselected
banks in the standby mode (less than one tenth of the
operating power) with the data output. in three-state. Only
the bank with its associated RAS low will be written to or
read from, except in mode 3 where all RASsignals go low to
.
allow fast memory initialization.

Monolithic Wllllemories

8·11

SN74S40S/DPS40S SN74S40S-2/DPS40S-2 SN74S40S-3/DPS40S-3
Pin Definitions
vcc GND, GND-Vcc =5V ± 5%. The three supply pins have
been assigned to the center of the package to reduce
voltage drops, both DC and AC. There are also two ground
pins to reduce the low level noise. The second ground pin is
located two pins from Vcc,so that decoupling capacitors
can be inserted directly next to these pins. It is important to
adequately decouple this device, due to the high switching
currents that will occur when all 8 address bits change in
thesame direction simultaneously. Recommended solution
would be a 11'F multilayer ceramic capacitor in parallel with
a low-voltage tantalum capacitor, both connected close to
pins 36 and 38 to reduce lead inductance.

CAS transitions low following valid column addreSs. In
Modes 3 and 4, it goes low. after RIC goes low, or follOWS
CASIN going low if RIC is already low. CAS is high during
refresh. '
RAS 0-3: Row Address Strobe Outputs-When M2(RFSH) is
high (modes 4-7), the selected row address strobe output
(decoded from Signals BO, B1) follows the RASIN input.
When M2 (RFSH) is low (modes 0-3) all RAS n outputs go low
togetherfoliowingRASIN'going low.
BANK SELECT
(STROBED BY ADS)
• B1
BO

RO-R7: Row Address Inputs.
CO-C7: Column Address Inputs.
BO, B1: Bank Select Inputs-Strobed by ADS. Decoded to
enable one of the RAS outputs when RASINgoes low, in
modes 4-6. In mode 7 BO, B1 are used to define End-ofCount (see table 3).
00-08: Multiplexed Address Outputs"":Selected from the
Row Address Input Latch, the Column Address Input Latch,
or the Refresh Cou·nter.
RASIN: Row Address Strobe Input-Enables selected RAS n
output when M2 (RFSH) is high (modes 4-6), and all RAS n
outputs in modes 0, 1, 2 and 3.
Ric: Row/Column Select Input-Selects either the row or
column address input latch onto the output bus.
CASIN: Column Address Strobe Input--Inhibits CAS output
when high in Modes 4 and 3. In Mode 6 it can be used to prolong CAS output.
ADS: Address (Latch) Strobe Input-Strobes Input Row Address, Column Address, and Bank Select Inputs into respective latches when high; latches on High-te-Low transition.
CS: Chip Select Input-Three-state's the Address Outputs
and puts the control signal into a high-impedance logic "1"
state when high(unless refreshing in mode 0, 1, 2). Enables
all outputs whe.n low.
MO, M1, M2 (RFSH): Mode Control Inputs-These 3 control
pins determine the 6 modes of operation of the 74S408 as
depicted in Table 1.
RF. 1/0-the 1/0 pin functions as a Reset Counter Input
when set low from an external open-collector gate, or as a
flag output. The flag goes active (low) when M2 "0 (modes 0,
1,2 or 3)andthe End-of-Co,unt output is at 127 Or 255 (see
Table 3).
.
WIN: Write Enable Input.
WE: Write Enable Output-Buffered output from WIN.
CAS: Column Address Strobe Output-In Modes 5 and 6,

MonoIIIhIc

a

0

a

1

1

0
1

1

ENABLED RAS n
RASa
RASl
RAS2
RAS3

Table 1. Memory Bank Decode

Input Addressing
The address block consists of a row-address latch, a
column-.address latch, and a resettable refresh counter. The
address latches are fall-through when ADS is high and latch
when ADS goes low. If the address bus contains valid addresses until after the valid address time, ADS can be permanently high. Otherwise ADS must go low while the addresses.are still valid. .
In normal memory access operation, RASIN and RIC are initially high. When the address inputs are enabled into the address latches (modes 4-6) the row addresses appear on the
outputs. The Address Strobe also inputs the bank-select
address, (BO and B1). If CS is low, all outputs are enabled.
When CS is transitioned high, the address outputs go threestate and the control outputs first go high through a low impedance, and then are held by an on-chip high impedance.
This allows output paralleling with other 74S408s for multiaddressing. All outputs go active about 50ns after the chip
is selected again. If CS is high, and a refresh cycle begins,
all the outputs become active until the end of the refresh
cycle.

a

Drive Capability
The 74S408 has timing parameters that are specified with
up to 600pF loads for CAS, 500pF loads for 0 0-0, and WE,
and 150 pF loads for RAS n outputs. In a typical memory
system this is equivalent to about. 885V-only DRAMs, with
trace lengths kept to a minimum. Therefore, ,the chip can
drive. lour banks each of 16.or22 bits, or two banks of 32 or
39 bits, or one bank of 64 or 72 bits.
Less loading will slightly reduce the timing parameters, and
more loading will increase the timing parameters, according
to the graph of Figure 6). The AC performance parameters
are specified with the typical load capacitance of 88
DRAMs. This graph can be used to extrapolate the variations expected with other loading.

IUD JIIemorles

SN74S40S/DPS40SSN74S40S-2/DPS40S-2SN74S40S-3/DPS40S-3
74$408 Driving Any 16K, 64K or 256K
DRAMs
The 74S408 can drive any 16K or 64K DRAMs. The on-chip
8-bit counter with selectable End-of-Count can support
refresh of 128 or 512 rows, while the 8 address and 4 RAS n
outputs can address 4 banks of 16K or 64K DRAMs.

Read, Write, and Read·Modify.Write
Cycles
'
The output signal, WE, determines what type of memory access cycle the memory will perform. If WE is kept high while
CAS goes low, a read cycle occurs. If WE goes, low before
CAS goes low, a write cycle occurs and DATA at 01 (ORAM
input data) is written into the DRAM as CAS goes low. If WE
goes low later than tCWD after CAS goes low, first a read
occurs and DO (DRAM output data) becomes valid; then
data 01 is written into the same address in the DRAMwhen
WE goes low. In this read-modify-write case, 01 and DO can-

MODE

4
., 5
6
7

M1

MO

0
0
1
1

0
1
0

c----- 0
0

0
1

1

1

1

1

0
1

0
0
0

0,1,2
3

(RFSH)
M2

..,

0
1
1

I

1

not be linkeugh an external
open-collector driver.

Mode 3-Externally Controlled
AII·RAS Write .
,',
This mode is useful at systeminitializlltion. The memory address is provided by the processor, which also perform the
incrementing. All four RAS oulputsfollow RASIN (Supplied
by the processor), strobing the row address into the DRAMs:
RIC ~annowgo low, while CASiN may be, used to control
CAS (as in the Externally Controlled Access mode), so that
CAS strobes the column address contents into the DRAMs.
At this time WE should be low; causing the data to be writ·
ten into all four banks of DRAMs. At the end of the write cycle, the input address is incremented and latched by the
74S408 for the next write cycle .

During (efresh, RASTlii and M.(RFSH) can transition low
.simultaneously because the refresh counter becomes$ (27ns); to rows held (50 ns); to col,
umns valid (25 ns); to CAS (23 ns) 140 ns (that is, 125 ns
from RASIN), All of these typical figures are for heavy capacitive loading, of approximately 88 DRAMs. This. mode is
therefore extremely . fast. The external timing is greatly
simplified for the memory system designer: the only system
signal required is RASiiii.

in applications requiring fast access times; RASINto CAS is
typically 105 ns.

=

In this mode, the RIC pin is not used, but CASIN is used to
allow an exterjded CAS after RAS has already terminated.
Refer to Figure 5b. This is desirable with fast cycle·times
where RAS has to be terminated as soon as possible before
the next RAS begins (to meet the precharge time, or tAP, requirements of the DRAM). CAS may then be held low by
CASIN to extend the data output valid time from the DRAM
to allow the system to read the data. CASIN subsequently
going high ends CAS. Ilthis extended CAS is not required,
CASIN should be set high in Mode 6.

Mode 6-Fast Automatic Access
The Fast Access mode is similar to Mode 5, but has a faster
tRAH of 20 ns, minimum. It therefore can only be used with
fast 16k or 64k DRAMs (which have a tAAH of 10 ns to 15 ns)

~tADS~·

INPUTS

.

'R'Cl

ADS

-

ADDRESS INPUTSI
DATA

'ASA I-'AHA -

./

"

, - - - - -r - - - -

READ
" , - ~~L~ W~T~ _ _ _

__ J'

I
'ASR·-I

1-

----....,

-I'CRS - ' R I C H -

.'RPdH-1

--'RpdL--

OUTPUTS

00-7

~

ADDRESS VALID

o'Apd-1

<-::»;:;;
.'''/»:;
~~
~;:~:;;~/

--

J

--'RAH--.

'j

ROWS

V~LlD
'ASC

-'RCV

~

COLUMNS VALID

.

'RCDL

-

--

'CCDH

-

--'DS·--

r----

READ

I

--WRITE----

-'WCS·-·--

.INDI:::::::::-IC-R-A-M-P-A-R-AM-ET-E-R-S-----+j,- ~ ~ ~ ~ ~ -'R-A-C.-

-_~_.,j-.

-'CAC·-

_-_-_-_-_-_-_-_

Figure 5b. Mode 6 Timing, Extended CAS

S·1S

.J

-

'OFF·

~

---V-A-LI-D-(-RE-A-D-)--.....

SN74S40S/DPS40S SN74S40S·2/DPS40S·2 SN74S40S·3/DPS40S·3
Mode 7-Set End-of-Count

and BO = 1, EOC is 255; and with B1 = 1 and BO =0, EOC is
127. This selected value of EOC will be used until the next
Mode 7 selection. At power-up the EOC is automatically set
to 127 (B1 and BO set to 11).

The End-ai-Count can be externally selected in Mode 7, using ADS to strobe in the respective value 01 B1 and BO (see
Table 3). With B1 and BO the same EOC is 127; with B1 0

=

BANK SELIOCT
(STROBED BY ADS)

END OF COUNT
SELECTED

B1

BO

0

0

127

0

1

255

1

0

127

1

1

127

10

ns

0

-5

-10

V
o

/
200

V

/

400

/

600

/

800

1000

C pF

Figure 6. Change in Propagation Delay vs Loading Capacitance Relative to a 500pF Load

IIIIonoIlthic

m

lIIIemories

S·19

SN74S408/DP8408 SN74S408-2/DP8408-2 SN74S408-3/DP8408-3
SN74S408/-2 Specifications:
Absolute Maximum Ratings (Note 1)
Supply voltage vee ..................................................................... , ..•............ -0.5 V to 7.0 V
Storage temperature range .............................................................................. -65° to +150° e
Input voltage ........................................................................................... -1.5 V to 5.5 V
Output current ................................................................................................ 150 mA
Lead temperature (soldering, 10 seconds) ........................................................................ 3000 e
NOTE1: "Absolute Maximum Ratings" are the values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should

be operated at these limits. The table of operating conditions provides conditions for actual device operation.

Operating Conditions
SYMBOL

PARAMETER

FIGURE

MIN

'S408
TYP MAX

MIN

'S408·2
UNIT
TYP MAX

Vee

Supply voltage

4.75

5.25

4.25

5.25

V

TA

Operating free-air temperature

0

+75

0

+75

°e

Address setup time to ADS

Figures 4a,4b,5a,5b

15

15

ns

tAHA

Address hold time from ADS

Figures 4a,4b,5a,5b

15

15

ns

tAOS

Address strobe pulse width

Figures 4a,4b,5a,5b

30

30

ns

Row address held from column select

Figure 4a

10

10

ns

Figure 2

50

50

ns

Figure 2

70

70

ns

tASA

--

tRHA
---

tRASINL,H Pulse width of RASIN during refresh
tRST

counter reset pulse width

Electrical Characteristics: vcc =S.OV ± S.O%, 0·C..TA.. 7S·C Typicals are for VCC =SV, TA =2S·C
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Vee

= MIN, IC =

-0.8

-1.2

V

VIN

= 2.5V

2.0

100

JAA

Input high current for other inputs, except RF I/O VIN

= 2.5V

1.0

50

JAA

IIRSI

Output load current for RF I/O

VIN

-1.5

-2.5

mA

IICTL

Output load current for RAS, CAS, WE

VIN

-1.5

-2.5

mA

IIL1

Input low current for ADS. RIC only

VIN

-0.1

-1.0

mA

11L2

Input low current for other inputs, except RF I/O

VIN

= 0.5V, output high
= 0.5V, chip deselect
= 0.5V
= 0.5V

-0.05

-0.5

mA

VIL**

Input low threshold

VIH**

Input high threshold

VOL1

Output low voltage, except RF I/O

Ve

Input clamp voltage

IIH1

Input high current for ADS. RIC only.

IIH2

2.0
10L

= 20mA
= 10mA
= -1mA
= -100JAA
= 0.8V (Note 3)
= 2.7V (Note 3)

VOL2

Output low voltage for RF I/O

10L

VOH1

Output high voltage, except RF I/O

VOH

VOH2

Output high voltage for RF I/O

10H

110

Output high drive current except RF I/O

VOUT

100

Output low drive current, except RF I/O

VOUT

10Z

Three-state output current
(add ress outputs)

0.4V"VOUT"2.7V,
CS
2.0V, Mode 4

=

ICC

Supply current

VCC

CIN

Input capacitance ADS, RIC

TA

CIN

Input capacitance all other inputs

8-20

-12mA

TA

= MAX
= 25°e
= 25°C

0.8

V

0.3

0.5

V

0.3

0.5

V

V

2.4

3.5

2.4

3.5

V

-200

mA

200

mA

-50

V

1.0

50

JAA

210

285

mA

8

pF

5

pF

SN74S408/DP8408SN74S40S .. 2/DP8408 ..2SN74S408-3/DPS408-3
Switching Characteristics: vcc
closed unless
SYMBOL

oth~rwlse

= S.OV::!: S.O%, O°C TA 7S0C S~e Figure 7 for test lo.ad (switches S1 and S2 are
specified) typicals are for VCC = SV, TA = 2SoC.

ACCESS PARAMETER

TEST CONDITIONS

'S408
MIN' TYP MAX

MIN

'S408-2
UNIT
TYP MAX

tRICl

RASIN to CAS output delay (Mode 5)

Figure 5a

95

125

160

75

100

13Q

tRICl

RASIN to CAS output delay (Mode 6)

Figures 5a,5b

80

105

140

65

90

115

ns

tRICH

RASIN to CAS output delay (Mode 5)

Figur.e 5a

40

48

60

40

48

60

ns

tRICH

RASI.N to CAS output delay (Mode 6)

Figures 5a,5b

50

63

80

50

63

80

ns

tRCDl

RAS to CAS output delay (Mode 5)

Figure 5a

98

125

75

100

ns

tRCDl

RAS to CAS output delay (Mode 6)

Figures 5a,5b

78

105

65

85

ns

tRCDH

RAS to CAS output delay (Mode 5)

Figure 5a

27

40

27

40

ns

tRCDH

RAS to CAS output delay (Mode 6)

Figure 5a

40

65

40

65

ns

tCCDH

CASIN to CAS output delay (Mode 6)

Figure 5b

54

70

54

70

ns

tRCY

RASIN to column address valid (Mode 5) Figure 5a

90

120

30

105

ns

tRCY

RASIN to column address valid (Mode 6) Figure 5a.

75

105

70

90

ns

tRPDl

RASIN to RAS delay

Figures 4a,4b,5a,5b

20

27

35

20

27

35

ns

tRPbH

RASIN to RAS delay

Figures4a,4b,5a,5b

15

23

32

15

23

32

ns

tAPDl

Address input to output low delay

Figures 4a,4b,5a,5b

25

40

25

40

ns

tAPDH

Address input to output high delay

Figures 4a,4b,5a,5b

25

40

25

40

ns

tSPDl

Address strobe to address output low

Fi9We 4b,4a

40

60

40

60

ns

tSPDH

Address strobe to address output high

Fibure4b,4a

40

60

40

60

ns

tWPDL

WIN to WE output delay

Figure 4b .

15

25

30

15

25

30

ns

tWPDH

WIN to WE output delay

Figure 4b

15

30

60

15

30

60

ns

tCPDl

CASIN to CAS delay (RiC) low in Mode 4) Figure4b

32

41

58

32

41

58

ns

tCPDH

CASIN to CAS delay

.Figure 4b

25

39

SO.

25

39

50

ns

tRCC

Column select to column address valid

Figure 4a

40

58

40

58

ns·

tRCR

Row select to row address valid

Figure 4a,4b

40

58

40.

58

ns

tCTl

RF I/O low to counter outputs aI/ low

Figure 2

100

ns

tRFPDl

RASIN to RAS delay during refresh

Figure 2

35

50

70

35

50

70

ns

tRFPDH

RASIN to RAS delay during refresh

Figure 2

30

40

55

30

40

55

ns

tRFlCT

RFSH low to counter address valid

CS = X, .Figure 2

47

60

47

60

ns

tRFHRV

RFSH high to row address valid

Figure 2

45

60

45

60

ns

tROHNC

RAS high to new count valid

Figure 2

30

55

30

55

ns

tRLEOC

RASINiow to end·ot·count low

CL=50pF, Figure 2

80

80. ns

tRHEOC

RASIN high to end·ot·count high

Cl = 50pF, Figure 2

80

80

tRAHI

Row address hoid time (Mode 5)

Figure 5a

30

20

ns

tRAH

Row address hold trme (Mode 6)

Figures 5a,5b

20

12

ns

tASC

Column address setup time (Mode 5)

Figure 5a

8

3

nS

tASC

Column address setup time (Mode 6)

Figures 5a,5b

6

3

ns

tRHA

Row address held from column select

Figure 4a

10

10

ns

tCRS

Casin setup time to Rasin high (Mode 6)

Figure 5b

35

35

ns

.

40

..

40

100

ns

ns

SN74S40S/DPS40S SN74S40S-2/DPS40S-2 SN74S40S-3/DPS40S-3

Switching Characteristics: (ConI.)
SYMBOL

ACCESS PARAMETER

'8408

TEST CONDITIONS
MIN

'8408·2

TYP

MAX

35

MIN

UNIT

TYP

MAX

60

35

60

ns

20

40

20

40

ns

35

60

35

60

ns

25

50

25

50

ns

50

80

50

80

ns

40

75

45

75

ns

45

75

45

75

ns

50

80

50

80 ms

THREE·STATE PARAMETER
Figure 7
R1 = 3.5k
R2 = 1.5K

tZH

C5 low to address output high from
HI-Z

tHZ

C5 high to address output Hi·Z from high

TZL

C5 low to address output low from Hi·Z

tLl

C5 high to address output Hi·Z from low

THZH

C5 low to control output high from
Hi.'Z high

tHHZ

C5 high to control output Hi·Z high
from high

CL = 15pF
Figure 7.
R2 = 750Q, 51 open

tHZL

C5 low to control output low from
Hi·Z high'

Figure 7 ,51,
52 open

tLHZ

C5 high to control output Hi·Z high
from low'

CL = 15pF
Figure 7
R2 = 750Q
51 open

CL = 15p, Figure 7
R2 = 1k, 51 open
Figure 7
R1 = 3.5k
R2 = 1.5k
CL = 15pF, Figure 7
R1 = 1k 52 aDen
Figure 7
R2 = 750 Q
51 open

*Internally the device contains a 3K resistor in' series with a Schottky Diode to

Vee.

Note 1: Output load capacitance is typical for 4 banks of 22 DRAMs or 88 DRAMs including trace capacitance. These values are:
RAS CL
150 pF; CAS CL
600pF unless otherwise noted.

=

=

Note 2: All typical values are for TA

00·08, WE CL

= 500 pF;

= 25° and Vc = 5.0V.

Note 3: This test is provided as a monitor of driver output source and sink current capability. Caution should be exercised in testing this parameter. In testing these
parameters a 15U resistor should be placed in ;;eries with each output under test. One output should be tested at a time and test time should not exceed 1 second.
Note 4: Input pulse OV to 3.0V, tR
2.7V for High and 0.8V for Low.

= tF = 2.5 ns, f = 2.5 MHz, tpw = 200 ns. Input reference pOint on AC measurements is 1.5V. Output reference points are

Note 5: The load capacitance on RF 1/0 should not exceed 50 pF.

Test Load

INPUT
OUTPUT
UNDERo-~~~-,----~~--~~

TEST

TEST POINT*

1511

ClU.

}-_ _ _ _ HfGH Z----..:....-=f'

S2

R2

R1, R2 = 4.7K Except as specified

Figure 7. Waveform

, The "TEST POINT" is driven by the output under test,
and observed by instrumentation.

S-22

SN74S40S/DPS40S SN74S40S-2/DPS40S-2 SN74S40S-3/DPS40S-3
SN74S40S-3 Specifications:
Absolute Maximum Ratings

(Note 1)

Supply voltage VCC ..................................................................................... -0.5 V to 7.0 V
Storage temperature range .............................................................................. -65° to +150°C
Input voltage ..............................................................•......•.................... .-1.5 V to 5.5 V
Output current .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 150 mA
Lead temperature (soldering, 10 seconds) ........................................................................ 300°C
NOTE 1: "Absolute Maximum Ratings" are the values beyond which the safety of the device cannot be guaranteed. They are not meant toimplythat the device should
be operated at these limits. The table of operating conditions provides conditions for actual device operation.

Operating Conditions
SYMBOL

PARAMETER

'5408·3

FIGURE

MIN

TYP

MAX

5.25
V
--------I;~o
+ 75°C
4.75

VCQ.
TA

--

15

tASA

--~---

..- . - - - - - -

15

tAHA

ns
ns

tAOS

ns

tRHA
tRASINl,H Pulse width of RASIN during refresh
counter reset pulse width

tRST

Figure 2

50

ns

Figure 2

70

ns

Electrical Characteristics: vee =5.0V:!: 5.0%, O°C';.A';75°C Typicals are

! IIH1

I

PARAMETER

TEST CONDITIONS

Input clamp voltage

VCC

= MIN, IC =

Input high current for ADS. RIC only.

VIN

= 2.5V

IIH2

Input high current for other inputs, except RF 1/0 VIN

IIRSI

Output load current for RF 1/0

VIN

IICTl

Output load current ,tor RAS, CAS, WE

,VIN

11L1

Input low current for. ADS. RIC only

VIN

IIL2

Input low current for other inputs, except RF 110

Vil"

Input low threshold

VIH"

Input high threshold

VOL1
VOl2
VOH1
VOH2

for VCC = 5V, TA

I

SYMBOL
Vc

--

ns

= 2.5V
= 0.5V, output high
= 0.5V, chip deselect
= 0.5V
= 0.5V
2.0

low voltage for RF 110

Output high voltage, except RFI/O

I Output

-12mA

TYP

MAxi UNIT
I

-0.8

-1.2

V

2.0

100

J.lA

1.0

50

J.lA

-1.5

-2.5

mA

-1.5

-2.5

mA

-0.1

-1.0

mA

-0.05

-0.5

mA

0.8

Output low voltage, except RF 1/0
! Output

VIN

I MIN

=25°C

high voltage for RF 1/0

V

V

10l

= 20mA

0.3

0.5

V

10l

=

10mA

0.3

0.5

V

IOH

=
=

-1mA

10H

-100J.lA

2.4

3.5

V

2.4

3.5

V

110

Output high drive current except RF 1/0

VOUT =0.8V (Note 3)

-200

mA

100

Output low drive current, except RF 1/0

VOUT

= 2.7V(Note 3)

200

mA

10Z

THREE-STATE output current
(address outputs)

0.4 V.; Vo Ur"'2.7V,
CS = 2.0V, Mode 4

ICC
CIN
CIN

**

~50

1.0

50

J.lA

285

mA

VCC

= MAX

210

capacitance ADS, RIC

TA

= 25°C

8

pF

Input capacitance all other inputs

TA

= 25°C

5

pF

Supply current

I Input

These are absolute voltages with respect to pins, 13 or 38 on the device and include all overshoots due to system or tester no'ise. Do not attempt to test these values
without suitable equipment.

Monolithic

W Memories

S-23

SN74S408/DP8408 SN74S408-2/DP8408-2 SN74S408-3/DP8408-3

=

Switching Characteristics: Ycc
s.OY:s.O%, O°C TA 75°C See Figure 7 for test load
(switches S1 and S2 are closed unless otherwise specified) typicals are for YCC
SY, TA = 25°C.
SYMBOL

8-24

ACCESS PARAMETER

=

TEST CONDITIONS

'S4()8.3
MIN

TYP

MAX

UNIT

tRICL

RASIN to CAS output delay (Mode 5)

Figure 5a

95

125

185

ns

tRICL

RASIN to CAS output delay (Mode 6)

Figures 5a,5b

80

105

160

ns

tRICH

RASIN to CAS output delay (Mode 5)

Figure 5a

40

48

70

ns

tRICH

RASIN to CAS output delay (Mode 6)

Figures 5a,5b

50

63

95

ns

tRCDL

RAS to CAS output delay (Mode 5)

Figure 5a

98

145

ns

tRCDL

RAS to CAS output delay (Mode 6)

Figures 5a,5b

78

120

ns

tRCDH

RAS to CAS output delay (Mode 5)

Figure 5a

27

40

ns

tRCDH

RAS to CAS output delay (Mode 6)

Figure 5a

40

65

ns

tCCDH

CASIN to CAS output delay (Mode 6)

Figure 5b

54

80

ns

tRCY

RASIN to column address valid (Mode 5)

Figure 5a

90

140

ns

tRCY

RASIN to column address valid (Mode 6)

Figure 5a

75

120

ns

40

tRPDL

RASIN to

RAS delay

Figures 4a,4b,5a,5b

20

27

40

ns

tRPDH

RASIN to RAS delay

Figures 4a,4b,5a,5b

15

23

37

ns

tAPDL

Address input to output low delay

Figures 4a,4b,5a,5b

25

46

ns

tAPDH

Address input to output high delay

Figures 4a,4b,5a,5b

25

46

ns

tSPDL

Address strobe to address output low

Figure 4b,4a

40

70

ns

tSPDH

Address strobe to address output high

Figure 4b,4a

40

70

ns

tWPDL

WIN to WE output delay

Figure 4b

15

25

35

ns

tWPDH

WIN to WE output delay

Figure 4b

15

30

70

ns

tCPDL

CASIN to

Figure 4b

32

41

67

ns

tCPDH

CASIN to CAS delay

Figure 4b

25

39

60

ns

tRCC

Column select to column address valid

Figure 4a

40

67

ns

tRCR

Row select to row address valid

Figure 4a,4b

40

67

ns

tCTL

RF 110 low to counter outputs all low

Figure 2

100

ns

tRFPDL

RASIN to RAS delay during refresh

Figure 2

35

50

80

ns

tRFPDH

RASIN to RAS delay during refresh

Figure 2

30

40

65

ns

tRFLCT

RFSH low to counter address valid

CS

47

70

ns

tRFHRV

RFSH high to row address valid

Figure 2

45

70

ns

CAS delay (RiC) low in Mode 4)

= X, Figure 2

tROHNC

RAS high to new count valid

Figure 2

30

55

ns

tRLEOC

RASIN low to end-of-count low

CL

80

ns

ns

tRHEOC

RASIN high toend-of-cQunt high

= 5OpF, Figure 2
CL = 50pF, Figure 2

80

ns

tRAHI

Row address hold time (Mode 5)

Figure 5a

tRAH

Row address hold time {Mode 6)

tASC

Column address setup time (Mode 5)

tASC

30

ns

Figures 5a,5b

20

ns

Figure 5a

8

ns

Column address setup ~me' (Mode 6)

Figures 5a,5b

6

ns

tRHA

Row address held from column select

Figure 4a

10

ns

tCRS

Casin setup time to Rasin high (Mode 6) Figure 5b

35

,ns

SN74S4081'DP8408 SN74S408-2I'DP8408.;2 SN74S408-3I'DP8408-3

=

Switching Characteristics: vcc
5.0V:!:5.0%, O°C TA 75°C See Figure 7 for test load
(switches S1 and S2 are closed unless otherwise specified) typicals are for VCC = 5V, TA = 25°C.
SYMBOL

ACCESS PARAMETER

'S4()8..3

TEST CONDITIONS
MIN

TYP

UNIT

MAX

THREE·STATE PARAMETER
tZH

tHZ
TZL

tu
THZH

Figure 8
R1 = 3.5k,
R2 = 1.5K

C5 low to address outpufhigh from
HI-Z

35

60

ns

20

40

ns

35

50

ns

=

25

50

ns

=

50

80

ns

=
=

40

75

ns

45

75

ns

50

80

ns

CL = 15p, Figure 8
C5 high to address output .Hi·Z from high R2= 1k, 51 open
Figure 8
R1 = 3.5k,
R2 = 1.5k

C5 low to address output low from Hi·Z

"

CL = 15pF,F!gure8,
C5 high to address output Hi·Z from low R1
1k 52 open
Figure 8
C5 low to controi output high from
R2
7502,
Hi·Z high
51 ()pen

tHHZ

C5 high to contrOl output HI:Z high
from high

CL
15pF,
Figure 8,
R2
7502, 51 open

tHZL

C5 low to control outpuilow from
Hi·Z high"

Figure 8, 51,
52 open

tLHZ

C5 high to control output Hi·Z high
from low"

.

CL == 15pF,
Figure 8,
. R2
7502,

=

510pe~
"Internally the device contains a 3K resistor in series with a Schottky Di,Ode

~o

Vee-

Note 1: Output load capacitance is typical for 4 banks of 22 DRAMs or 88 DRAMs including trace capacitance. These values are:
RAS,cL 150 pF; CAS CL 600pF unless otherwise noted.

=

=

Note 2: All typical values are for TA

= 25° and Vc

00·08,

WE CL' =

500 pF;

= S.OV.

Note 3: This test is provided as a monitor of driver output source and sink current capab.ility. Caution should be exercised in testing this parameter. In testing these
parameters a 150 resistor should be placed in series with each output under test. One output should be tested at a time and test time should not exceed 1 second.
Note 4: Input pulse OV to 3.0V, tR = tF = 2.5 ns, f = 2.5 MHz, tpw = 200 ns.lnput reference point on AC measurements is 1.5V. Output reference pOints are
2.7V for High and 0.8V for Low.
Note 5: The load capacitance on RF 1/0 should not 'exceed 50 pF.

8-25

SN74S40S/DPS40S SN74S40S-2/DPS40a-2 SN74S408-3/DPS40S-3
Die Configuration

28

10

Die Size: 161x129 mil2

S-26

14

15

Multi-Mode .
Dynamic RAM
Controller/Driver

SN74S409/DP8409
SN74S409-2/DP8409-2
SN74S409-3/DP8409-3

Features/Benefits

O....lhg Information

• All DRAM drive functions on one chip haVe on-chip highcapacitance load drivers (specified up to 88 DRAMs)

PART NUMBER

• Drives dlrecUy all 16K, 64K and.256K DRAMS; capable
of addressing up to 1M word•.
• Propagation delays of 25 nsec typical at 500 pF load

PACKAGE

SN74S409

N48. 048 (L52)

SN74S409-2

N48,

SN74S409-3

N48, 048 (L52)

048 (L52)

• Supports READ, WRITE and READ.MODIFY-WRITE
cycles
• Eight modes of operation support extemally-controlled and
automatic access and refresh, as well. as special memory
Initialization access
• On-chip 9-blt refresh counter with selectable End"of-Count
(127,255 or 511)

Pin Configuration
RIC (RFCK) I
CASIN (RGCK)

2

• Direct replacement for. National DP8409

M2 (iiFiH) 5

Operating Modes
Externally-controlled fresh
Auto refresh - forced
Automatic burst refresh
AII-RAS auto write
Externally-controlled AII-RAS write
Exter'nally-controlled access
Auto access, slow tRAH. hidden refresh
Auto access. fasttRAH
Set end of count

0
1

2
3a
3b
4
5

6
7

SYSTEM

RAM

~

CONTROL

CONTR.
10 OL

SYSTEM

20

SYSTEM
ADDIIESS

74S408
OYNAMICIIAM
CONTROLLER
DRIVER

8
_DRIVE MEMORY

•

RAM
ADORESS

18k, 14k, OR
ZSIk DYNAMIC
RAM IANKS

Interlace liIetween System and DRAM Banks

Portions of this Data Sheet are repri~t.d courtesy of II/aiional SemiCQnductor Corporation.

/
TWX: 910-338-2376
2H5~ll8Ion. Qollege Blvd. Santa Clara, CA950s4~1592 T81::(406) 970-9700:TW1C:. 9107~-2314·•.

.SN74S409

TEMPERATURE
COM
COM. SPEED OPTION
COM, AC OPTION

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3
Block Diagram
RO-8

ADS

,ROW
ADDRESS

~

CO-8

.

\

COLUMN
ADDRESS

~

J
.I iI

___

iI

L----"......._ _.... 00-8

~.

INPUT LATCH

I

9-BIT

!

~~~~~SE~

HIGH CAPACITIVE DRIVE
CAPABILITY OUTPUTS
WHEN ENABLED

-~

. -,-..
B1 BO _

BANK SELECT
INPUT LATCH

RAS 1

RASO

Cs_
RASIN_
R/C(RFCK)CASIN(RGCK)-

~~----~--~----~~
WIN-----~--_+---4----4~-----_I

RF 1/0

M2 (RFSH)

M1

MO

Figure 1. 748409 Functional Block Diagram

Description
The 74S409 is aMulti-Mode Dynamic RAM Controller/Driver
capable of directly driving up to 88 DRAMs. 20 address lines
to the 74S409 allOW it to address up to 1M words and it can
drive 16K, 64K and 256K DRAMs. Since the 74S409 is a
one-chip solution (including capacitive-load drivers). it min-.
imizes propagation delay skews, and saves board space.
The 74S409'5 8 operating modes offer externally-controlled
or on-chip automatic access and refresh. An on-chip refresh
counter makes refreshing (either externally or automatically
controlled) less complicated; and automatic memory initialization is both simple and fast.
The 74S409 is a48-pin DRAM Controller/Driver with 9 multiplexed address outputs and 6 control- signals. It consists of
two 9-bit address latches, a 9-bit refresh counter, and control

8-28

IIIIIonoIlthIc

logic. The 74S409 timing parameters are specified when driving
the typical load capitance of 88 DRAMs, including trace
capacitance.
The 748409 can drive up to 4 banks of DRAMs, with each
bank comprised of 16Ks, 64Ks or 256Ks. Control signal
outputs CAS and WEare provided with the same driving
capability. Each RAS output drives one bank of DRAMs so
that the four RAS outputs are used to select the banks,
while CAS, WE and the multiplexed addresses can be connected to all the banks of DRAMs. This leaves the nonselected banks in the standby mode (less than one tenth of
the operating power) with the respective data outputs in
three-state. Only the bank with its associated RAS low will
be written to or read from, except in mode 3 where all RAS
signals go low to allow fast memory initialization.

m

MemorIes

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3
Pin DefInitions

vee GNP, GNP-Vcc =5V ± 5%. The three supply pins have
been assigned to the center of the package to reduce voltage drops, both DC and Ac. There are also two ground pins
to reduce the low level· noise. The second ground pin is
located two pins from Vcc , so that decoupling capacitors can
be inserted directly next to these phis. It is important to
adequately decouple this device, due to the high switching
currents that will occur when all 9 address bits change in the
same direction simultaneously. A recommended solution
is a l-~F multilayer ceramic capacitor in parallel with a lowvoltage tantalum capacitor, both connected close to pins 36 and
38 to reduce lead· inductance.

BANK SELECT
(STROBEP BY APS)
B1

BO

0
0
1
1

0
1
0
1

ENABLEP RJ;Sn

"RASO
"RAS1
FiAS2
RAS3
Table 1. Memory Bank Decode

RO-R8: Row Address Inputs.

3a when the End-of-Count output is at 127, 255, or 511 (see

CO-C8: Column Address Inputs.

Table 3). In Auto-Refresh Mode (mode 5) it is the Refresh
.
.
Request (RFRQ)output

BO, B1: Bank Select Inputs-Strobed by ADS. Decoded to
enable one of the RAS outputs when RASIN goes low, in
modes 4-6. In mode 7 BO, B1 are used to define End-ofCount (see table 3), and select mode 3a or 3b.

WE: Write Enable Output- Buffered output from WIN.

QO-Q8: Multiplexed Address Outputs-Selected from the
Row Address Input Latch, the Column Address Input Latch,
or the Refresh Counter.
RASIN: RoW Address Strobe Input- Enables selected RAS n
output when M2 (RFSH) is high (modes 4-6), and all RAS n
outputs in modes 0 and 3. RASIN input is disabled in modes
l-and2 ..

RIC (RFCK) -In Auto-Refresh Mode this pin is the external
Refresh Clock Input: one refresh cycle has to be performed
each clock period. In all other modes it is RowlColumn
Select Input, selecting either the row or column address
input latch onto the output bus.
CASIN (RGCK)-In modes 1, 2 and 3a, this pin is the RAS
Generator Clock input. In all other modes it is CASIN (Column
Address Strobelnput),which inhibits CAS output when high
in Modes 3b and 4. In Mode 6 it can be used to prolong CAS
output.
APS: Address (Latch) Strobe Input-Strobes Input Row
Address, Column Address, and Bank Select Inputs into
respective latches when high; latches on High-to-Low
transition.

CS:

Chip select Input-three-state's the Address Outputs
and puts the control signal into a high-impedance logic
"1" state when high (unless refreshing in one of the Refresh
Modes). Enables all outputs when low.
MO, M1, M2 (RFSH): Mode Control Inputs-These 3 control
pins determine the 8 major modes of operation of the 74S409
as depicted in Table 2.

RF I/O RFRQ - This 1/0 pin functions as a Reset Counter
Input when set low from an external open~ollector gate, or
as a flag output. The flag goes active-low in Modes 0, 2 and

WIN: Write Enable Input.
CAS: Column Address Strobe Output-In Modes 3a, 5, and
6, CAS transitions low following valid column address. In
Modes 3b and 4, it goes low after RIC goes low,or follows
CASIN going low if RIC is already low. CAS is high during
refresh.
RAS 0-3: Row Address Strobe Outputs-When M2(RFSj.n
is high (modes 4-6), the selected row address strobe output
(decoded from signals BO, 81) follows theRASIN input.
WhenM2""(RFSHj is low (modes 0-3) all RAS n outputs go
low together following RASIN going low in modes 0 and 3
and automatically in modes 1 and 2.

Input Addressing
The address block consists of a row-address latch, a columnaddress latch, and a resettable refresh-counter.
The address latches are fall-through when ADS is high and
latch when ADS goes low" If the address bus contains valid
address until after the valid address time, ADS can be permanently high. Otherwise ADS must go low while the address
is stlll valid~
In normal memory-access .operation, RASiN and RIC are
initially high. When the address inputs.are enabled into the
address latches (modes 3-6) the row addresses appear on
the Q outputs. The Address Strobe also inputs the bankselect address, (BO and Bl). If CS is low, all outputs are
enabled. When CS goes"high, the address outputs gothreestate and the. control outputs first go .high. through a low
impedance, and then are held by an on-chip high impedance.
This allows output paralleling with other 74S409s for multiaddressing. All outputs go active about 50ns after the chip is
selected again. If CS is high, and a refresh cycle begins, all
the outputs become active until the end of the refresh cycle.

8-29

5N745409/DP8409 5N745409-2/DP8409-2 5N745409-3/DP8409-3
Drive Capability
The 74S409 has timing parameters that are specified with up
to 600pF loads for CAS and WE, 500pF loads for 00-08, and
150pF loads for RAS n outputs. In a typical memory system
this is equivalent to about 88 5V-only DRAMs, with trace
lengths kept to a minimum. Therefore, the chip can drive four
banks each of 16 or 22 bits, or two banks of 32 or 39 bits,
or one bank of 64 or 72 bits.
Less loading will slightly reduce the timing parameters, and
more loading will increase the timing parameters, according
to the graph of Figure 14.The AC performance parameters
are specified with the typical load capacitance of 88 DRAMs.
This graph can be used to extrapolate the variations
expected with other loading.

745409 Driving Any 16K, 64K or 256K
DRAMs
The 74S409 can drive any 16K, 64K, or 256K DRAMs. The
on-chip 9-bit counter with selectable End-of-Count can support refresh of 128, 256 and 512 rows, while the 9 address
and 4 RAS n outputs can add ress 4 banks of 16K, 64K or
256K DRAMs.

before CAS goes low,a write cycle occurs and data at 01
(DRAM input data) is written into the DRAM as CAS goes
low. If WE goes low later than tCWD after CAS goes low, first
a read occurs and DO (DRAM output data) becomes valid;
then data 01 is written into the same address in the DRAM
when WE goes low. In this read-modify-write case, 01 and
DO cannot be linked together. The type of cycle is therefore
controlled byWE, which follows WIN.
.

Power-Up Initialize
When VCC is first applied to the 74S409, an internal pulse
clears the refresh counter. the internal control flip-flops, and
sets the End-of-Count of the refresh counter to 127 (which
may be changed via Mode 7). As VCC increases to about 2.3
volts, it holds the output control signals at a level of one
Schottky diode-drop below VCe. and the output address to
three-state. As VCC increases above 2.3 volts, control of
these outputs is granted to the system.

745409 Functional Modes Description
The 74S409 operates in 8 different functional modes
s.elected by signals Mo,M"M2. Mode 3 splits further to modes
3a and 3b determined by signals Bo,B, in mode 7.

Read, Write, and Read-Modify-Write
Cycles

Mode 0 and mode 1 are generally used as Refresh modes
for mode 4 and mode 5 respectively, and therefore will be
described as mode-pairs 0,4 and 1,5.

The output signal, WE, determines what type of memory
access cycle the memory will perform. If WE is kept high
while CAS goes low, a read cycle occurs. If WE goes low

Mode 6 is a fast access made for very fast DRAMs and mode 7
is used only to determine choice of mode 3a or 3b and for
setting End-of-Count forthe refresh modes.

(RFSH)
M2

M1

MO

0
1

0

0

0

Externally-controlled refresh

0

0

1

Auto refresh - forced

RF I/O = Refresh request (RFRO)

2

0

RF 110 =EJC

0
0

0
1

Automatic burst refresh

3a*
3b*

1
1
1

1

AII-RAS auto write
Externally-controlled AII-RAS write

RFI/O =EJC; all RAS active
AII-RAS active

MODE

MODE OF OPERATION

CONDITIONS
RF I/O=EJC

4

1

0

0

Externally-controlled access

Active RAS defined by Table 2

5

1

0

1

Auto access, slow tRAH, hidden refresh

Active RAS defined by Table 2

6

1
1

1
1

0

Auto access, fast tRAH
Set end of count; determines mode 3a or 3b

Active RAS defined by Table 2
See Table 3 for Mode 7

7

1

'Mode 3. is selected by setting Bo.B, to 01, 00, or 10 in mode 7.
'Mode 3b is selected by setting B"Bo to 11 in mode 7.

Table 2. 74S409 Mode Select Options

8-30

MonoHthlc

W lIIIemor/es

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3
RF 1/0 goes low when the count equals End-of-Count (as
set in mode 7), and RASIN is low. The 9-bit counter will always
roll-over to zero at 512, regardless of End-of-Count. However,
the counter can be reset at anytime by driving RF 1/0 low through
an external open-collector.

Mode 0 - Externally-Controlled Refresh
Mode 4 - Externally-Controlled Access
Modes 0 and 4 facilitate external control of all timing parameters associated with the DRAMs. These modes are independent modes of operation though generally used together in
the same application as shown in Figure 2.

During refresh, RASIN and M2 (RFSH) can transition low
simultaneously because the refresh counter becomes valid
on the output bus tRFLCT after RFSH goes low, which is a
shorter time than tRFPDL. This means the counter address
is valid on the Q outputs before RAS occurs on all RAS
outputs, strobing the counter address into that row of all the
DRAMs (see Figure 2.). To perform externally-controlled
burst refresh, RFSH initially can again have the same edge
as RASIN, but then maintains a low state, since RASIN going
low-to-high increments the counter (performing the burst
refresh) .

Mode O-Externally-Controlled Refresh
In this mode the input address latches are disabled from the
address outputs and the refresh counter is enabled. All RAS
outputs go low following RASIN and refresh the enabled row
in all four banks. CASIN and RIC inputs are not used and
CAS is inhibited. The refresh counter increments when either
RASIN or M2 (RFSH) switch high while the other is still low.

. - - - - - , - - -...... RAS
.-----t~1 CAS

DRAMs MAY BE 16K, 64K, OR 256K x 1 bit
FOR 4 BANKS, CAN DRIVE 16 DATA BITS
+6 CHECK BIT$ FOR ECC.
FOR 2 BANKS, CAN DRIVE 32 DATA BITS
+7 CHECK BITS FOR ECC.
FOR 1 BANK, CAN DRIVE 64 DATA BITS
+8 CHECK BITS FOR ECG.

RAS 3

INPUT CAS '-------+lCASIN
ALEI
~ ADS

RAS 2
RAS 11----4-4~·· ..
RAS 0

A0-15, 17, 19

745409

INPUT RAS

------I.~IRASIN

r"1

CAS
ROW/COLUMN SEL

R/C

1----+....-4

WEI----4~~/~~~

WRITE r-------t~WIN
REFRESH ,.I-----..;~~I M2 (Rl'SH)
~__~CSr-M~1__M~O____~

Figure 2. Typical Application of 745409 Using Externally-Controlled Access and Refresh in Modes 0 and 4

NIonoIlthioW Memories

8-31

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3

S409INPUTS

CASiiii AND RIC
S409 OUTPUTS
RASO

iiAs1, 2, 3
'ROHNC

n+1

REFRESHCTR

COUNTER RESET

REFRESH COUNT n

"RF 110

L ___

I

1-

~

_____________

tRLEOC

I

---l

I

~

I-tRHEOC

END Of COUNT
LOW If n = END-Of-COUNT
·INDICATES DYNAMIC RAM PARAMI'TERS

Figure 3. Ellternal Control RefreSh Cycle (Mode 0)

8-32

COUNTER RESET
INPUT FROM
OPEN COLLECTOR

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3
Mode 4 - Externally-Controlled Access
This mode facilitates externally controlling all access-timing
parameters associated with the DRAMs. Figures 4 and 5
show the timing for read and write cycles.

contents are transfered to the.multiplexed address bus output 00-08. RASIN can go low after the row addresses have
been ..set up on 00-08, and enables one RAS output selected
by signals BO, B1 to strobe the 0 outputs into the desired
bank of memory. After the row-address hold-time of the
DRAMs, RIC can go low so that about 40 nsec later. the
column address appears on Jhe 0 output.

Output Address Selection
In this mode CS has to be low at least 50 nsec before the
outputs will be valid. With RIC high, the row address latch

S4091NPUTS

I~I ~II~I---11-----.;..1--,----

RIC

S409 OUTPUTS

RASO, 1, 2, 3 -...:...I--.-..:.I-t-S-Pd...:.------I----;L..._t....
R...
H_A_-_-.....:,.I..,.1_ _ _ _ _ _ _ _ _ _

~ tApd'_

~~~~~~~

tASR-I- tRAH"'----+
ROWS VALID

_ I tRCR

1-

r------------~
~I----ROWS
COLUMNS VALID

tAsc-,

l - tCAC- - - -

------~~~--~--~--~

I~~

DRAM DATA OUT

__._.

tRAC_L...----+---------'

------------------------<1

DATA OUT VALID

-INDICATES DYNAMIC RAM PARAMETERS

Figure 4. Read Cycle Tinling (Mode'4)

IIIonoIIthIa

liD 1IIIe".,..",..·...

8-33

SN74S408/1)P8408 SN74$408-2/DP8408-2 SN74S408-3/DP8408-3

S409INPUTS

ADS (ALE)

-1...

~

-----~DS----

1...--

.

~

________

~

__________________________

~

____

~

tASA~""-':~- tAHA-~

SYSTEM "'."";,,.,.~_/""'/""
ADDRESS .. "/..-;. /

ADDRESS VALID

BUS~~~ ~--__--------------~~~~~~~~~~~~~~~~~~~

~--------------------------~I~I

I-I

\I

IcpdL .

Ric

W.IN

DRAM DATA IN

----1---+----....:.----------:----<1

I~I

S409 OUTPUTS

DATA IN VALID ~~--"":'--!.----i--------

_ ISpd ___ _

RAIO. 1. 2. 3
+-

IApd _

IASR"I- IRAH"----

~'77"'?'''''';''""""",,

QO~8 ::~<~>;>.

ROWS

COLUMNS VALID

ROWS VALID

I

I

-I ICpdH 1-

cM------------------~I~_------·-'-~-c-r~I~·----~------~I~----________

----~-----------IW-P-d_;L- - - - - . ,

WE

.

.

·1

...

-'---

1____ 1~'~Wpd~H-----------

IWCH"

---.1

"INDICATES DYNAMIC RAM PARAMETERS

Figure 5. Write CVcle Timing (Mode 4)

Automatic CAS Generation
In a normal memory access cycle CAS can be derived from
inputs CASiN or RIC. If CASiN is high. then RIC going low
switches the address output drivers from rows to columns. .
CAS1N then going low causes CAS to go low approximately
40-ns later, allowing CAS to occur at a predictable tinie (see
Figure 5). For maximum system speed. CASIN can be kept
low. since CAS will automatically occur approximately 60ns
after RiC goes low (see Figure 4). Most DRAMs have a
column address set-up time before CAS (tASC)of 0 'ns or
-10 ns, In other words. a tASC greater than 0 ns is safe. This

8-34

feature reduces timing-skew problems. thereby improving
access time olthe system.

Fast Memo.., Access
For faster access time. RIC can go Iowa time delay (tRPDL
+ tRAH - tRHAl after "RASfN goes low; where tRAH is the
Row-Address hold-time of the DRAM. and CAS IN can go low
tRCC - tcPOL tAse (min.) after RIC goes low (see tDiF1.
tDiF2 switching characteristics).

+

SN74S409/DP8409 SN74S409-2/DP84V9-2 SN74S409-3/DP8409-3
Mode i-Automatic Forced Refresh
Mode 5 -Automatic Access
with Hidden Refresh
Mode 1 and Mode 5 are generally used together incorporating the advantages of the "h.idden refresh" performed in
mode 5 with the possibiity to force a refresh by changing to
mode 1. An advantage of the Automatic Access over the
Externally-Controlled Access is the reduced memory access
time, due to the fact that the output control signals are.derived
internally from one input signal (RASIN).

Hidden and Forced Refresh
Hidden Refresh is a term describing memory refresh performed when the system does not access the portion of
memory controlled by the 74S409 (CS = 1). A hidden refresh
will occur once per Refresh Clock (RFCK) cycle provided CS
went high and RASIN went low. If no hidden refresh occurred
while RFCK was high, the RF I/O (RFRQ) goes low immediately after RFCK goes low, indicating to the system when a
forced refresh is required. The system must allow a forced
refresh to take place while RFCK is low by driving M2 (RFSH)
low, thereby changing mode of operation to Mode 1.
The Refresh Request on RF .1/0 (RFRQ) is terminated as
soon as RAS goes low, indicating to the system that the
faced refresh has been done. The system should then drive
M2 (RFSH) high, changing the mode of operation back to Mode 5
(see Figure 6).

Mode i-Automatic Forced Refresh
In Mode 1, the R/C (RFCK) pin functions as RFCK (refresh
cycle clock) instead ofR/C, and CAS remains high. If RFCK
is kept permanently high then whenever M2 (RFSH) goes

Monolithic

low, an externally-controlled refresh will occur and all RAS
outputs will follow RASIN, strobing the refresh counter contents to the DRAMs. The RF I/O pin will always output high,
but can be set low externally through an open-collector
driver. to reset the refresh counter.
If RFCK is an input ciock, one and only one refresh cycle
must take place every RFCK cycle. If a hidden refresh does
not occur while RFCK is high, in Mode 5, then RF I/O
(Refresh Request) goes low immediately after RFCK goes
low, indicating to the system that a forced refresh is required.
The system must allow a forced refresh to take place while
RFCK is low The Refresh Request signal on RF I/O may be
connected to a Hold or Bus Request input to the system.
The system acknowledges the- Hold or Bus ReQUeSt when
ready, and outputs Hold Acknowledge or Bus Request
Acknowledge. If this is connected to the M2 (RFSH) pin, a
forced-refresh cycle will be initiated by the S409, and RAS
will be internally generated on all four RAS outputs, strobing
the refresh counter contents on the address ouputs into all
the DRAMs. An external RAS Generator Clock (RGCK) is
requred for this function. It is fed tothe CASIN (RGCK) pin,
and may be up to 10 MHz. Whenever M2 goes low (inducing
a forced refresh), RAS remains high for one to two periods of
RGCK, depending on when M2goes low relative to the highto-low triggering edge of RGCK; RAS then goes low for two
periods, performing a refresh on all banks. In order to obtain
the minimum delay fromM2 going low to RAS going low, M2
should go low tRFSRG before the next falling edge of RGCK.
The Refresh Request on RF I/O is terminated as RAS begins,
so that by the time the system has acknowledged the removal
of the request and disabled its Acknowledge, (i.e., M2 goes
high),Refresh RAS will have ended, and normal operations
can begin again in the Automatic Access mode (Mode 5). If it
is desired that Refresh RAS end in less than 2 periods of
RGCK from the time RAS went low; then M2 may go high
earlier than tFRQH after RF I/O goes high and RASWiligo
high tRFRH after M2.

W Memories

8-35

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409;.3/DP8409-3
Mode 5 -Automatic Access with

Hidden Refresh
In this mode all address outputs, RAS and CAS are initiated
from RASIN making the DRAM access appear similar to
static RAM access. The hidden refresh feature enables
DRAM refresh accomplished with no time-loss to the system.
Provided the input address is valid as ADS goes low, RASIN
can go low any time after ADS. This is because the selected
RAS occurs typically 27 ns later, by which time the row
address is already valid on the address output of the 74$409.
The Address Set-Up time (tASR), is 0 ns on most DRAMs.
The 74S409 in this mode (with ADS and RASIN edges simultaneously applied) produces aminimum tASR of 0 ns. This is
true provided the input address was valid tASR before ADS
went low (see Figure 7).
Next, the row address is disabled tRAH after RAS goes low
(30 ns minimum); in most DRAMs, tRAH minimum is less
than 30 ns. The column address is then set up and (tAscl~
CAS occurs. The only other control input required is WIN.
When a write cycle is required, WIN must go low at least
30 ns before CAS is output low.
This gives a total typical delay from: input address valid to
RASIN (15 ns); ,to RAS (27 ns); to rows held (50 ns); to columns valid (25 ns); to CAS (23 ns) = 140 ns (that is, 125 ns
from RASIN). All of these typical figures are for heavy capacitive loading, of approximately 88 DRAMS.

Refreshing
In this mode R/C (RFCK) functions as Refresh Clock and

CASll'J (RGCK) functions as RAS Generator Clock.
One refresh cycle must occur during each refresh clock period,
and then the refresh actdress must be incremented before the
next refresh cycle. As long as 128 rows are refreshed every 2 ms
(one row every 161's), all 16K and 64K DRAMs will be correctly
refreshed. The cycle time of RFCK must, therefore, be less than
16 jLS. RFCK going high sets an internal refresh-requestflipflop.
First the 748409 will attempt to perform a hidden refresh so that
the system thruput will not be affected. If, during the time RFCK

8-36

is high, CSon the 74S409goes high and RASIN occurs, a hidden
refresh will occur. In this case, RASIN should be consillered a
common read/write strobe. ·In other words, if the processor is
accessing elsewhere (other than the DRAMs) while RFCK is high,
the 748409 will perform a refresh. The refresh counter is enabled
to the address outputs whenever CS goes high with RFCK high,
and all RAS outputs follow RASIN. If a hidden refresh is taking
place as RFCK goes low, the refresh continues. Atthe start ofthe
hidden refresh, the refresh-request flipflop is reset so on further
refresh can occur until the next RFCK period starts with the positive-going edge of RFCK (see Figure 6). RASIN should go low at
least 20 ns before RFCK goes low, to ensure occurrence of the
hidden refresh.
To determine the probability of a hidden. refresh occurring,
goes low, (and the internal-request flipflop has. not been
for 8jLS, then the system has 20 chances to not select the
74S409. If during this time a hidden refresh did not occur,
then the 74S409 forces a refresh while RFCK is low, but the
system chooses when the refresh takes place. After RFCK
goes low, (and the internal-request flip-flop has not been
reset), RF I/O goes low indicating that a refresh is requested
to the system. Only when the system acknowledges this
request by setting M2 (RFSH) low does the 74S409 initiate a
forced refresh (which is performed automatically). Refer to
Mode 1, and Figure 6. The internal refresh request flipflop is
then reset.
.
Figure 6 illustrates the refresh alternatives in Mode 5. If a
hidden refresh has occurred and CS again goes high before
RFCK goes low, the chip is deselected. All the control signals go high-il'T)pedance high (logic "'1") and the address outputs go three-state \JntilCS again goes low. This mode
(combined with Mode 1) allows very fast access, and automatic refreshing (possibly not even slowing down the
system), with no extra ICs. Careful system design can, and
should, provide a higher probability of hidden refresh
occurring. The duty cycle of RFCK need not be 50 percent;
in fact, the low-time should be designed to 'be a minimum.
This is determined by the worst-case time (required by the
system) to respond to the 74S409's forced-refresh request.

SN74S409/DP8409SN74S409-2/DP8409-2 SN74S409-3/DP8409-3

_I
-I
HOLD OR
BUS REQUEST
HOLD ACK
OR BUS ACK

RFRQ

4

RF 1/0

r'RGCKL 1

-.'ROHRFH:.;(;..M_oD_E_'.;,.1_ _ _ __

I

1

"0"_ M1

(MODE II

I -II--I

"1"_ MO
RGCK

t

t

IRFCK

I~

--I r- 'RGCKH

JlJlrulnJlJ

ROCK

RFSH (M2)

RFCK

t

RF 1/0 (AFRO)

--~

-I

'FROH

I

I·

1 -I.

1- 'RFHR.

-I I-.'RGRHI

j--'RGRL

---T"I-'-I-.-'-IUr--':""'-,--r-1

Tn.

RAS 0, " 2, 3"T"""1

~ >IRP---i

00-8

ROWS

REFRESH TO

ALL BANKS

\

ACCESS TO

SELECTED BANKS

=X===C=O=LS==~XL._RE_FR_E_SH_C_O_U_N_TE_R_~
-I

r-'CTRFL

~--------la.~K'-------·

I •.-----------IRFCKH---~----~

FORCES REFRESH

HIDDEN REFRESH ALLOWED

··------,----"'FCK---~--­

RFCK

~--------~----PR'I)CIESSiOR

ACCESSING
ELSEWHERE

(CASIN) RGCK

~

(RI'RQ)

HIDDEN REFRESH ALREADY
PERFORMED_ NO SUBSEQUENT
REFRESH ALLOWED IN THIS CYCLE_

M2(RFSFi)

00-8

"INDICATES DYNAMIC RAM PARAMETERS

CD RFCK GOES LOW
CD lfFRO GOES LOW IN NO HIDDEN
REFRESH OCCURRED WHILE RFCK WAS HIGH
CD M2 (Rl'SR) DRIVEN LOW EXTERNALLY

u

I

I..
HI Z
1 HIGH ....

CD REFRESH REQUEST RELEASED

o
o

RU 0-3 GO LOW TO PERFORM REFRESH
M2 (RFSH) RELEASED

Figure 6_ Hidden Refreshing (Mode 5) and Forced Refreshing (Mode 1) Timing

8 ..37

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3

J I~_______- I--'ADS--j

ADS

r---ADDRESSINPUTS/_~-{,~DDIRESS
DATA
VALIDr--~~~~~~~·R~ID+----~-------

aO-8

--- -WRITE--- ---

DATA OUTPUT

--------+-----.,.------<

"INDICATES DYNAMIC RAM PARAMETERS

Figure 7. Mode 5 Timing

8-38

MonoIIthIcm

Memories

VALID (REAI;I)

SN74S408/DP8408 SN74S408-2/DP8408-2SN74S408-3/DP8408-3

Mode 2 -Automatic Bum Refresh
This mode is normally used before and/or after a DMA operation to ensure that all rows remain refreshed, provided the
DMA transfer takes less than 2 ms (see Figure 8). When the
748409 enters this mode, CA81N (RGCK) becomes the RAS
Generator Clock (RGCK), and RASIN is disabled. CA8
remains high, and RF I/O goes low when the refresh counter
has reached the selected End-of-Count and the last RA8
has ended. RF I/O then remains low until the Auto-Burst
Refresh mode is terminated: RF I/O can therefore be used
as an interrupt to indicate the ·End-of-Burst condition.
The signal on all four RAg outputs is just a divide-by~four of
RGCK; in other words, if RGCI< has a 100 ns period, RASis
high and low for 200 ns each. cycle. The refresh counter
increments at the end of each RAS, starting from the count it
contained when the mode was entered; If this was zero then
for a. RGCK with a 100 ns period with End-of Count set to
127, RF I/O will go low after 128 x 0:4!lS, or 51.21'8. During this
time, the system may be performing operations that do. not
involve DRAM. If all rows need to be burst'refreshed, the
refresh counter may be cleared by setting RF I/O low
externally before the burst begins.

Burst-mode refreshing is also useful when powering down
systems for long periods of time, but with data retention still
required while the DRAMs are. in standby. To maintain valid
refreshing, power can be applied to the 748499 (set to Mode,
2), causing it to perform a complete burst refresh. When
end-of-bust occurs (after 261'8), power can then be removed
from the 748409 for 2 ms, consuming an average power of
1.3% of normal operating power. No control signal glitches
occur when switching. power to the 748409.

Mode 3a -All-US Automatic Write
Mode 3a is useful at system initialization, when the memory
is being cleared (i.e., with all-zeroes in the data field and the
corresponding check bi.ts for error detection and correction).
This requires writing the same data to each location of memory (every row of each column of each bank). All RA8 outputs are activated, as in refresh, and so are CAS and WE. To
write to all four banks simultaneously, every row is .strobed in
each column, in sequence, until data has been written to all
locations. The refresh counter is used to address the rows,
andRAS is low for two RGCK cycles and high for two cycles.

.....
...
.

DRAMs

MODE

MODE2 :

RGCK

QQ..

RF110 (EOC)

Figure 8. Auto-8urst Mode, Mode 2

8-38

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP84.09-3
In this mode, Ric is disabled, WE is permanently enabled
low, and CASIN (RGCK) becomes RGCK. RF 1/0 goes low
whenever the relresh counter is 127, 255, or 511 (as set by
End-ol-Count in Mode 7). and the RAS outputs are active.

To select this mode, B1 and BO must have previously been
set to 00, 01, or 10 in Mode 7, depending on the DRAM size.
For example, lor 16K DRAMs, B1 and BO are 00. For 64K
DRAMs, B1 and BOare01.

REQUIRED IF
SYSTEM STILL
OPERATING
WHILE 74S409 ..~
IN MODE 3A
~
PROCESSOR
ADDRESS
6US

RASIN--~---4~~------+-----~1

WRITE
PROCESSOR ADS

WIN
CASIN
M2 Ml MO (RGCK)
-H--_~--1I------'

ENA6LE
PAL

745409 Extra Circuitry Required for AII-RA5 Auto Write Mode, Mode 3a

MODE

~M2, Ml, MO =011

61 60

=10 ~~ODE 7)

PROCESSOR
ADDRESSES
MODE SELECT
PAL

RGCK

RAS 0-3

OCTAL
HIZ
COUNTER - - - " ' \ 0
OUTPUT

INTERRUPT

ENA6LE COUNTER
6UFFER

IEJ

I~

RF I/O (EOC)

:==x-

/',

EOC

/1

:3

/I

1/

/I

/',

I

HIZ

r

INTERRUPT PROCESSOR

I

Figure 9. 748409 AII-RA8 Auto Write Mode, Mode 3a, Timing Waveform

8-40

I/IIonollthic WMemorles

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3

Mode 3b - Externally-Controlled
AII-RAS Write
To select this mode, 81 and 80 must first have been set to 11
in Mode 7. This mode is useful at system initialization, but
under processor control. The memory address is provided by
the processor, which also performs the incrementing. All four
RAS outputs follow RASIN (supplied by the processor),
strobing the row address into the DRAMs. RIC can now go
low, while CASIN may be used to control CAS (as in the
Externally-Controlled Access mode), so that CAS strobes the
column address contents into the DRAMs. At this time WE
should be low, causing the data to be written into all four
banks of DRAMs. At the end of the write cycle, the input
address is incremented and latched by the 74S409 for the
next write cycle. This method is slower than Mode 3a, since
the processor must perform the incrementing and accessing.
Thus the processor is occupied during RAM initialization,
and is not free for other initialization operations. However,
initialization sequence timing is under system control, which
may provide some system advantage.

Mode 4 - Externally-Controlled
Access

Set-Up time (tASR), is 0 ns on most DRAMs. The 74S409 in
this mode (with ADS and RASIN edges simultaneously
applied) produces a minimum tASR of 0 ns. This is true provided the input address was valid tASA before ADS went low
(see Figure 10).
Next, the row address is disabled tRAH after RAS goes low
(20 ns minimum); the column address is then set up and tASC
later, CAS occurs. The only other control input required is
WIN. When a write cycle is required, WIN must go low at
least 30 ns before CAS is output low.
This gives a total typical delay from: input address valid to
RASIN (15 ns); to RAS (27 ns): to rows valid (50 ns); to columns valid (25 ns); toGAS (23 ns) = 140 ns (that is, 125 ns
from RASrn). All of these typical figures are lor heavy capacitive loading, of approximately 88 DRAMs.
This mode is therefore extremely fast. The external timing is
greatly simplified for the memory system designer: the only
system signal required is RASrn.
In this mode, the RIC (RFCK) pin is not used, but 'CASTf\I
(RGCK) is used as 'CASTf\I to allow an extended CAS after
RAS has already terminated. Reier to Figure 11.

Mode 4 is described in with mode 0 in section "Mode 0 and
Mode 4:'

Mode 7 - Set End-of-Count (3a, 3b select)

Mode 5 -Automatic Access with
Hidden Refresh

The End-ai-Count can be externally selected in Mode 7,
using ADS to strobe in the respective value of 81 and 80
(see Table 3). With 81 and 80 the same
is 127; with 81
= 0 and 80 = 1,
is 255; and with 81 = 1 and 80 = 0,
EOC is 511. This selected value of
will be used until the
next Mode 7 selection. At power-up the "roc is automatically setto 127 (81 and 80 setto 11).

See description of mode 0 and mode 5.

Mode 6- Fast Automatic Access
The Fast Automatic Access mode can only be used with fast
DRAMs which have tRAH of 10 nsec-15nsec. The typical
RASIN to CAS delay is 105nsec. In this mode CAS can be
extended after RAS goes high to extend the data output
valid time. This feature is useful in applications with short
cycles where RAS has to be terminated as soon as possible to
meet the precharge (tRP) requirements of the DRAM.
Mode6timing is illustrated in Figures 10and 11. Provided that the
input address is valid as ADS goes low, RASIN can go low
any time after ADS. This is because the selected RAS occurs
typically 27 ns later, by which time the row address is already
valid on the address output of the 74S409. The Address

IIIIonoIlthIo

roc

roc::

roc

When 8,,82 are set to 11 in mode 7, mode 3b wi II be selected
if mode 3 is selected (M2, M" Mo = 0, 1, 1). If 8,,82 is set to
00,01 or 10 then mode 3a will be selected.
BANK SELECT

(STROBED BY ADS)
B1
BO
0
0
1
1

END OF COUNT

SELECTED
127
255
511
127

0
1
0
1
Table 3. Mode 7

WMemorles

8-41

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3

f-

ADS

J

IADS-----l
L . . . I_

_

_

_

_

_

_

_

~

_

_

~

_ _

ADDRE~!T~PUTSI ---(.~DCIRE!IS V'ALIID}---E--::-::=-7':":":7.:'""±-::==~IEAD+----I4-'---

QO·8

--WRITE--

DATA O U T P U T - - - - - - - - - + - - - - - - - - - <

"INDICATES DYNAMIC RAM PARAMETERS

Figure 10. Mode 6 Timing (CASIN High)

8-42

VALID (READ)

~.~I

____________________________________________________________________________________
_
SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3

PI

INPUTS

I--IADS-I
A D S J I'----_ _ _ _ _ _ _

ADDRE~!T~PUTS/---<

'f---t----"

OUTPUTS

COLUMNS VALID

- - -WRITE- - - - -

DATAOUTPUT------------------r--------------------(

VALID (READ)

·INDICATES DYNAMIC RAM PARAMETERS

Figure 11. Mode 6 Timing, Extended CAS

I

I

·;1
"

\'j

/1rl,,1

1'~I:!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!~
MonoIHhleWlfemories

1

I

8-43

SN74S4091DP8409·· SN74S409-2/DP8409-2 SN74S409-3/DP8409-3
SN74S409/-2 Specifications:
Absolute Maximum Ratings (Note 1)
Supply voltage VCC .................................................................... , ................. -0.5 V to 7.0 V
Storage temperature range .............................................................................. _65° to +150°C
Input voltage .. , '.' . .. . .. . . . .. ..... .. . • • .. .. .. . .. . .. . .. . .. . . . . . .. . .. . .. . .. . . . • . .. . . .. .. . .. . . . . . . . .. .. .. . ... -1.5 V to 5.5 V
Output current ......................................................... , ............ '.' .................... , ... 150 mA
lead temperature (soldering, 10 seconds) ........................................... : .................... , ........ 300°C
NOTE 1: "Absolute Maximum Ratings" are the values beyond which the safety olthe device cannot be guaranteed. They are not meantto Implythatthe device should
be operated at these limits. The table of operaUng conditions .provides conditions for actual device operation.

Operating Conditions
PARAMETER

SYMBOL

Vee
TA
tASA
tAHA
tAOS
tRASINL,H
tRST
. tRFCKL H
T
tRGCKL
tRGCKH
tCSRL
tRFSRG
tRQHRF

MIN

Supply voltage
Operating free-air temperature
Address setup time to ADS
Address hold time from ADS
Address strobe pulse width

Figures4,5, 7, 10, 11
Figures 4.5,7.10,11
Figures 4.5,7,10,11

4.75
0
15
15
30

Pulse width of RASIN during refresh
Counter reset pulse width
Minimum pulse width of RFCK.
Period of RAS generator clock
Minimum pulse width low of RGCK
Minimum pulse width high of RGCK
CS low to access RASIN low
RFSH low set-up to RGCK low (Mode 1)
RFSH hold time from RF'ffQ (RF 1/0)

Figure 3
Figure 3
Figure 6
Figure 6
Figure 6
Figure 6
See Mode 5 description
See Mode 1 deScription
Figure 6

50
70
100
100
35
35
10
35
2T

Electrical Characteristics:

'S409
TYP MAX
5.25
75

MIN

'S409-2
TYP MAX

4.75
0
15
15
30

5.25
75

UNIT
V
°C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

50
70
100
100
35
35
10
35
2T

Vee = 5.0V ± S.O%, OOC:5 TA ~ 75° C Typicals are for Vec = Sv, TA = 2SoC.

PARAMETER

SYMBOL

**

FIGURE

TEST CONDITIONS

MIN

TVP

MAX

-0.8

-1.2

V

2.0

100

pA

UNIT

Vc

Input clamp voltage

Vee

::;: MIN,le = -12mA

IIH1

Input high current for.ADS, R/C only

VIN

=2.5V

IIH2
IIRSI

Input high current for other inputs, except RF I/O

VIN

=2.5V

Output load current for RF I/O

VIN

= O.Sv, output high

IICTl

Output load current for 'RAS, CAS, WE

VIN

11L1

Input low current for ADS, RIC only

VIN

IIL2

Input low current for other inputs, except RF I/O

VIN

VIL**

Input low threshold

VIH**

Input high threshold

VOL1

Output low voltage, except RF I/O

10L

=20mA

0.3

O.S

V

VOL2

Output low voltage for RF I/O

10L

=10mA

0.3

O.S

V

VOH1

Output high voltage, except RF I/O

IOH

=-1mA

2.4

3:s

V

VOH2

Output high voltage for RF I/O

2.4

3.S

V

110

Output high drive current, except RF I/O

10H = -1oopA
VOUT = 0.8V (Note 3)

100

Output low drive current, except RF I/O

VOUT = 2.7V (Note 3)

10Z

Three-state output current
(address outputs)

0.4V ~ VOUT ~ 2.7v,
es = 2.0V. Mode 4

1.0

sO

pA

-1.S

-2.S

mAY

= O.Sv, chip deselct

-1.S

-2.S

mA

=O.SV

-0.1

-1.0

mA

=O.SV

-O.OS -O.S

mA

0.8
2.0

-sO

V
V

-200

mA

200

mA

1.0

SO

pA

32S

mA

Ice

Supply current

Vce

= MAX

2s0

CIN

Input capacitance ADS, RIC

TA

= 25°C

8

pF

CIN

Input capaCitance all other inputs

TA

=2SoC

S

pF

These are absolute voltages with respect to pins 13 or 38 on the device and include all overshoots due to system or tester noise. Do not attempt to test these values
without suitable equipment.

,~I

____________________________________________________________
___
SN74S409/DP8409 SN74S409-2/DP8409-2

t~~"I

. . Switching Characteristics:

Vee = 5.0V ± 5.0%, ooe ~ TA ~ 75°C See Figure 12 for test load (switches S1
and S2 are closed unless otherwise specified) typicals are for Vee = 5V, TA = 25°C.
SYMBOL

ACCESS PARAMETER

FIGURE

MIN

'S409
TYP MAX

MIN

'S409-2
TYP MAX

UNIT

,

tRHA
i
I

tRICL
tRICl

!

tRICH
tRICH
tacDL
tRCOL
tRCOH
tRCOH
tCCOH
tRCV
tRCV

I

I

tRPDL
tRPOH
tAPOL

i

tAPOH
!s£D.L
tSPOH
twPOL
twPOH
tCRS
tCPDL
tCPDH
tRCC
tRCR
tRAH
tRAH
tASC
tASC
tOiF1
tOiF2

SYMBOL

Row address held from column select
RASIN to CAS output delay (Mode 5)

Figure4
Figures 7, 10

10
95

RASI N to CAS output delay (Mode 6)
RASIN to CAS output delay (Mode 5)
RASI N to CAS output delay (Mode 6)
RAS to CAS output delay (Mode 5)
RAS to CAS output delay (Mode 6)

Figures 7, 10, 11
Figures 7,10
Figures 7,10,11
Figures 7,10
Figures 7,10,11.
Figures 7, 10

80
40

RAS to CAS output delay (Mode 5)
RAS to CAS output delay (Mode 6)
CASI N to CAS output delay Mode 6)

Figures 7,10
Figure 11

RASIN to column address valid (Mode 5)
RASIN to column address valid (Mode 6)
RASI N to RAS delay

Figures 7,10
Figures 7,10,11
Figures 4, 5, 7, 10, 11

RASIN to RAS delay
Address input to output low delay
Address input to output high delay

Figures 4, 5, 7, 10, 11
Figures 4, 5,7, 10,11
Figures 4, 5, 7, 10, 11

Address strobe to address output low
Address strobe to address output high
WIN to WE output delay
WI N to WE output delay
CASIN setup time to RASIN high (Mode 6)

Figures 4, 5
Figures 4, 5
Figure 5
Figure 5
Figure 11

CASIN to CAS delay (RIC low in Mode 4)

Figure 5
Figure 5

CASIN to CAS delay
Column select to column address valid
Row select to row address valid

50

Figures 7, 10
Figures 7, 10, 11
Figures 7,10

Column address setup time (Mode 6)

Figures 7, 10, 11

160
140

48
63

60

98
78
27
40

20
15

40
54
90
75
27
23
25
25

40
65
70
120
105
35
32
40

35
32

41

58

39
40
40

50
58·
58

25

60
30
60

30
20
8
6

130
115

48

60
80
100
85
40

63
75
65
27

40
40

54

20

80
70
27

15

15
15
35
32
25

23
25
25

TEST CONDITIONS

MIN

=
=

CL 50 pF, Figure 6
CL 50pF, Figure 6
Figure 6

'S409
TYP MAX

CS high to RFSH counter valid
RF I/O low to counter outputs all low
RASiN to RAS delay during refresh

tRFPOH
tRFLCT
tRFHRV

RASIN to RAS delay during refresh
RFSH low to counter address valid

CS -

45

60

tROHNC

R FSH high to row address valid
RAS high to new count valid

X, Figures 3, 6, 8
Figures 3, 6
Figures3,8

30

tRLEOC
tRHEOC

RASIN low to end-of-count low
RASIN high to end-of-count high

CL
CL

55
80
80

tRGEOB
tMCEOB

RGCK low to end-of·burst low
Mode change to end-of-burst high

CL - 50pF, Figure 8

95
75

= 50pF, Figure 3
= 50pF, Figure 3
CL = 50pF, Figure 8

Monolithic WMemorles

50
40
55

35
30

40
40
60
60
30
60

41

58

39
40
40

50
58
58

15
15

20
50
65
60

30
75
95
85

80

110

55

70
100
70

50
40
47

MIN

55
60

50
40
55

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

3

tCSCT
tCTL
tRFPDL

Figure 6
See Mode 1
description
Figure 6
Figure 3
Figures 3, 6
Figures 3, 6

65
70
105
90
35
32

40
40
25
30

15
15

tRFRH

tRGRH

65
40
50

100
90

20
12
3

RFCK low to forced RFRQ low
RGCK low to force RFRQ high ._.
RGCK low to RAS' low
RGCK low to RAS high
RFSH high to RAS high
(encoding forced RFSH)

tFRQL
tFRQH
tRGRL

10
75

40
60

15
15

Maximum (tRPDL - tRHA)(Mode 4)
Maximum (tRC~ - tCPOL) (Mode 4)

REFRESH PARAMETER

80
125
105

40
40
25
30

Figure 4
Figures 4, 5

Row address hold time (Mode 5)
Row address hold time (Mode 6)
Column address setup time (Mode 5)

125
105

'8409-2
TYP MAX

ns
ns
ns

UNIT

20
50
65
60

30
75
95
85

ns
ns
ns

80

110

ns

55

70
100
70

ns
ns

35

50

30

40
47
45
30

55
60
60
55
80
80
95
75

ns

ns

ns
ns
ns
ns
ns
ns
ns
ns

8-45

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3

Switching Characteristics:
SYMBOL

(Cont'd)

ACCESS PARAMETER

TEST CONDITIONS

MIN

'S409
TYP. MAX

MIN

'S409-2
TYP MAX

UNIT

THREE-STATE PARAMETER
CS low to address output high from Hi

Figures 6, 12
R1
3.5k, R2

Cl3 high to address output Hi-Z from high

Cl -15pF, Figures 6,12
R2 1k, Sl Open

CS low to address output low from Hi~Z

Figures 6,12
R1
3.5k, R2 1.5k
Cl 15pF, Figures 6,13
R1
1k, S20pen
Figures 6,12
R2 7500, S1 open

tZH
tHZ
tZl

=

tlZ

CS high to address output Hi-Z from low

tHZH

CS low to control output (WE,~,
(RASO-3) high from Hi-Z high

tHHZ

CS high to control output (WE, CAS,
(RASO-3) Hi-Z high from high

tHZl

CS low to control output (WE, ~,
(RASO-3) low from Hi-Z high

=

=
=
=

=

=
=
=

Cl 15pF
R2 7500, Sl open
Figure 12
Sl,S20pen
Cl 15pF, Figure 12
R2 7500, S 1 open

=
=

CS ~9h to control output (WE, CAS,
(RA 0-3) Hi-Z high from low

tlHZ

= 1.5k

35

60

35

60

ns

20

40

20

40

ns

35

60

35

60

ns

25

50

25

50

ns

50

80

50

80

ns

40

75

40

75

ns

45

75

45

75

ns

50

80

50

80

ns

'Inlernally Ihe device conlains a 3K reslslor in senes with a Schottky Diode
10VCC'
Nole 1: Oulpul load capacilance is typical for 4 banks of 22 DRAMs or 88
DRAMs including Irace capacilance. These values are: 00-08. CL 500pF;
RASO-RAS3, CL 150pF; CAS CL 600pF unless olherwise noled.

=

=

=

Nole 2: Aillypical values are for TA

10

=25"C and VCC =5.0V.

Nole 3: This lesl is provided as a monilor of Driver oulpul source and sink
currenl capability. Caulion should be exercised in lesling Ihis parameler.
In lesling Ihese paramelers, a 150 resislor should be placed in series wilh
each oulpul under lest. One oulpul should be lesled al a lime and lesllime
should nol eXCeed 1 second.
Nole 4: Inpul pulse OV 10 3.0V, IR

= IF = 2.5 ns, f = 2.5 MHz. IpW = 200 ns.

5

no

0

Input reference point on AC measurements is 1.SV. Output reference points

are 2. 7V for High and 0.8V for Low.

Test Load
SV

1

-5

f1

-10

V
o

OUTPUT
UNDER
TEST

/
200

V

L

400

V
800

/

800

CpF

O-..JOw..........--~~-_!l

TEST POINT*

150

Figure 13. Change in Propagation Delay vs Loading
S2

CL·U

Capacitance Relative to a 500 pF Load

R2

R1, R2 = 4.7K EXCEPT AS SPECIFIED.

*

The "TEST POINT" is driven by Ihe oulpul under lesl,
and observed by instrumentation.

INPUT

}-_ _ _ _ HIGH Z_ _ _ _"'"'<,
OUTPUT VOL

...;;.;'-----'\---0.5V

-1

0.8V

.IHZL - IZL

-IILHZ
III

Figure 12. Waveform

8-46

1000

IIIIonoIIIhIo

W Memories

SN74S409/DP8409 SN74S409-21DP8409-2 SN74S409-3/DP8409-3

ii

tl iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
~i

tl SN7 4S409-3 Specifications:
11 Absolute Maximum Ratings

(Note 1)

,..

';,i Supply
voltage vee··· .. ···· .. ·,·· .. ···· .. ··· .. · ......... ··· .. · .. · .. ·· .. ····· .. · .. · .. · ...... ···•··•· .. ·· ,.0.5 V to 7.0 V
Storage temperature range .............................................................................. _65° to +1WC
I

Input voltage ....................................................... ; ............................,........ -1.5Vto5.5V

I Output current ............ '.' .......................................................~ ....................... '.' .. 150 mA
i

lead temperature (soldering, 10 seconds) ...................................................... ; .................. 3QO°C

of

, NOTE 1: "Absolute MaximLlm Ratings" are the values beyond which the safety the device cannot beguaranlee>d. They are not meant to imply that the ~vice Sho.uld
be operated at these limits. The table of operating conditions provides conditions for actual device operation.

Operating Conditions
SYMBOL
VCC
TA
tASA
tAHA
tAOS
tRASINl.H
tRST
tRFCKLH

T
tRGCKl
tRGCKH
tCSRl
tRFSRG
tROHRF

PARAMETER

MIN

Supply voltage
Operating free-air temperature
Address setup time to ADS
Address hold time from ADS
Address strobe pulse width

Figures 4. 5, 7. 10. 11
Figures 4, 5, 7. 10, 1.1
Figures 4. 5.7; 10; 11

4.75
0
15
15
30

Pulse width·of RASIN during refresh
Counter reset pulse width
Minimum pulse width of RFCK
Period of RAS generator clock
Minimum pulse width low of RGCK"
Minimum pulse width high of RGCK
CS low to access RASI N low
RFSH low set-up toRGCK iow (Mode t)
RFSH hold time from RFRQ (RF 1/0)

Figure 3
Figure 3
FigureS
FigureS
..
FigUreS
FigureS
See Mode 5 description
See Mode,1description
FigureS

50
70
100
100
35
35
10
35
2t

Electrical Characteristics:
SYMBOL

Vee

=5.0V ± 5;0%, OOC:5 TA:5 75° C

PARAMETER

rip

VCC

=MIN.IC= -12mA

VIN

==

MAX

UN"

5.25
75

°C

V
1\$

ns
ns.
ns
.1\$

ns
ns
ns
ns
nS
ns
ns

Typicalsare for Vee

TEST CONDITIONS

I nput clamp voltage
Ve
IIH1' .,. Input higf'rcurrentfor ADS.R/Conly

**

'S409-3

FIGURE

MIN

2.5V

=5V, TA :;: 25°C.
UNIT

TYP

MAX

-0.8

~1.2.

V

2.0

100

p.A.

1.0

50

p.A.

IIH2

Input high current for other inputs, except RF I/O

VIN

=2:5V

IIRSI

outputload currentfor RF I/O

VIN

= 0.5V, output high

-1,5

-2.5

mAV

IICTl

Output load current for RAS; CAS.WE

VIN

= 0.5\/, chip deselct

-1.5

-2.5

mA

11L1

Input low current for ADS. R/C only

VIN

== 0.5V,

-1.0

mA

IIl2

!nput low current for other inputs. exceptRF I/O

VIN

=0.5V

,','

-0.1

-0.05 -0.5

mA

VIL**

Input low threshold.

VIH**

Input high threshold .

VOL1

Output low voltage. except RF I/O

10l

=20mA

0.3

0.5

V

VOL2

Outputlow voltage for RF I/O

lOt:

= 10rnA

0.3

0,5

V

VOH1

Output high voltage. except RF I/O

10H

=-1mA

VOH2

Output high voltage for RF I/O

110

Output high drive current. except RF I/O

VOUT '" 0.8V (Note 3)

-200

m~

100

Output low drive current. except RF I/O

VOUT = 2.1V (Note 3)

200

mA

10Z

Three-state output current
(address outputs)

OAV :5 VOUr.::; ;2,7Y,
CS = 2.0V, Moqe .4

ICC

Supply current

VCC

= MAX

CIN

I nput capacitance ADS; R/C

TA

= 25°C

8 .....·.

!IF

CIN

Input capacitance all other inputs

TA

= ,25°C

5

pF

O,e
2.0

.

10H .: =. --'1 00p.A.

V
V

2.4

3.5

V

2.4

3.5

V

....

-50
.'

1.0

50

p.A.

250

325

rt1A

These are absolute voltages with respect to pins 13 or 38 on the device and jnclude,all overshoots due, -to system ortester noise. Do not attemptto test these values
without suitable equipment.
'

SN74S409-3/DP8409.3

=

Switching Characteristics: vee 5.0V ± 5.0%, ooe:5 TA:5 75°C See Figure 12 for test load
(switches S1 and S2 are closed unless otherwise specified) typicals are for Vee 5V., TA 25°e
SYMBOL
tRHA
tRICl

Row address held from column select
RASIN to CAS output delay (Mode 5)

tRICl

RASIN to CAS output delay (Mode 6)
RASIN to CAS output delay (Mode 5)

tRICH

RASIN to CAS output delay (Mode 6)
RAS to CAS output delay (Mode 5)
RAS to CAS output delay (Mode 6)
RAS to CAS output delay (Mode 5)
RAS to CAS output delay (Mode 6)

tRICH
tRCDL
tRCDL
tRCDH
tRCDH

CASIN to CAS output delay Mode 6)
RASIN to column address valid (Mode 5)
RASIN to column address valid (Mode 6)

tcCDH
tRCIt
tReV
tRPDl

RASIN to RASdelay
RASIN to RAS delay
Address input to output low delay
Address input to output high delay

tRPDH
tAPDL .
tAPDH
t!':PDl

Address strobe to address output low
Address strobe to address output high
WIN to WE output delay
WIN to WE output delay

tSPDH
twPDl
twPDH
tCRS

CASIN setup time to RASIN high (Mode 6)
CASIN to CAS delay (RIC low in Mode 4)

tcPDL
tcPDH
tRCC
tRCR

CASIN to CAS delay
Column select to column address valid
Row select to row address valid
Row address hold time (Mode 5)
Row address hold time (Mode 6)
Colu·mn address setup time (Mode 5)

tRAH
tRAH
tASC
tASC

Column address setup time (Mode 6)

tDiF1
tDiF2

Maximum (tRPDL - tRHAl (Mode 4)
Maximum (tRCC - tcPDU (Mode 4)

SYMBOL

REFRESH PARAMETER

tFROl

RFCK low to forced RFRQ low

tFROH
tRGRL

RGCK low to lorce RFRQ high
RGCK low to RAS low

tRGRH

RGCK low to RAS high
RFSH high to RAS high
(encoding forced RFSH)
CS high to RFSH counter valid

tRFRH
tCSCT
tCTL
tRFPDl

RF I/O low to counter outpu\Salllow
RASIN to RAS delay during refresh
RASIN to RAS delay during refresh

tRFPDH
tRFlCT
tRFHRV
tROHNC
tRLEOC
tRHEOC
tRGEOB
tMCEOB

8-48

=

FIGURE

ACCESS PARAMETER

-.

Figure 4
Figures 7, 10
Figures 7, 10, 11
Figures 7, 10
Figures 7,10,11
Figures 7, 10
_Figures 7,10, 11
Figures 7, 10
Figures 7, 10
Figure 11
Figures 7, 10
Figures 7, 10, 11
Figures 4, 5, 7,10,11
Figures 4, 5, 7, 10, 11

=

'S409-3
MIN TYP MAX
10
95
80
40
50

125
105
48
63
98
78
27

40

20
15

120
40

ns
ns
ns

65

80

90

140
120

ns
ns
ns

40
37

ns
ns

46
46
70

ns
ns
ns

70

ns
ns
ns

75
27
23

Figures 4, 5
Figures 4, 5
Figure 5
Figure 5
Figure 11

40
40
25
30

35

41
39
40

67

70

35
32
25

ns
ns
ns

40

25
25

Figure 5
Figure 5
Figure 4

95
145

ns
ns
ns

54

Figures 4, 5, 7, 10, 11
Figures 4, 5, 7, 10, 11

15
15

185
160
70-

UNIT

ns

40

60
67
67

ns
ns
i'ls

Figures 4, 5
Figures 7, 10

30

ns
ns

Figures 7, 10, 11
Figures 7, 10
Figures 7, 10, 11

20
8
6

ns
ns
ns
20

20

TEST CONDITIONS
CL = 50 pF, Figure 6
CL = 50pF, Figure 6
Figure 6
Figure 6
See Mode 1
description
Figure 6
Figure 3
Figures 3,6
Figl,lres3,6

MIN

'S409-3
TYP MAX
20
50

lis
ns
ns

85

ns

65
60

55

80

125

ns

55

75
100
70

ns
ns
ns
ns

35
30

50
40

CS= X, Figures 3, 6, 8

47

Figures 3, 6
Figures3,8

45
30

RASIN low to end-of-count low
RASIN high to end-of-count high
RGCK low to end-ol-burst low
Mode change to end-of-burst high

CL
Cl
Cl
Cl

5OpF, Figure 3
50pF, Figure 3
50pF, Figure 8
50pF, Figure 8

UNIT

30
75
95

40

50

RFSH low to counter address valid
RFSH high to row address valid
RAS high to new countvalid

=
=
=
=

ns
ns

55
70
70
55
80
80
95
75

ns
ns
ns
ns
ns
ns
ns

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3
Switching Characteristics:
SYMBOL

(Cont'd)

ACCESS PARAMETER

TEST CONDITIONS

MIN

'S409-3
TYP MAX

UNIT

THREE-STATE PARAMETER
CS low to address output high from Hi

Figures 6, 13
R1 = 3,5k, R2 = 1.5k

35

60

ns

CS high to address output Hi-Z from high

CL = 15pF, Figures 6, 13
R2 = 1k, S1 Open

20

40

ns

CS low to address output low from Hi-Z

Figures 6,13
R1 = 3.5k, R2 = 1.5k

35

60

ns

tLZ

CS high to address output Hi-Z from low

CL = 15pF, Figures 6,14
Rl= 1k,S20pen

25

50

ns

tHZH

CS low to control output (WE, CAS,
(RASO-3J high from Hi-Z high

Figures 6,13
R2 = 7500, S1 open

50

80

ns

tHHZ

CS high to control output (WE, CAS,
(RASO-3J Hi-Z high from high

Cl': 15pF
R2 = 7500, S1 open

40

75

ns

tHZL

CS low to control output (WE, CAS,
(RASO-3J low from Hi-Z high

Figure 13
S1,S20pen

45

75

ns

tLHZ

CS high to control output (WE, CAS,
(RASO-3J Hi-Z high from low

CL = 15pF, Figure 13,
R2 = 7500, S1 open

50

80

ns

tzH
tHZ
tZL

,
,

;lnternaIlY the device contains a 3K resistor in series with a SChO.ttkY Diode

!toVCC·

INote1: Output load capacitance is typical for 4 banks of 22 DRAMs or 88
IDRAMS including trace capacitance. These values are: 00-08. CL '" 500pF;
,RASO-RAS3, CL 150pF; CAS CL 600pF unless otherwise noted.

=

=

.. INote2: All typical values are forTA = 25°C and VCC = 5.0\/.
I
I

'1

I

Note 3: This test is provided as a monitor of Driver output source and sink
current capability. Caution should be exercised in testing this parameter.
In testing these parameters, a 150 resistor should be placed in series with
each· output under test. One output should be tested at a time and test time
should not exceed 1 second.
Note 4: Input pulse Oil. to 3.0\/, tR = tF = 2,5 ns, f = 2.5 MHz. tpw = 200 ns .
fnput reference point on AC measurements is 1.5\/. Output reference pOints
are 2.711. for High and.0.8V for Low.
Note 5: The load capacitance on RFIIO should not exceed 50 pF.

SN74S409/DP8409 SN74S409-2/DP8409-2 SN74S409-3/DP8409-3
Applications

chips to provide refresh clock and chip select is shown in
Figure 14.

The 748409 Dynamic RAM Controller provides all the
address and control signals necessary to access and refresh
dynamic RAMs. 8ince the 748409 is not compatible with a
specific bus or microprocessor, an interface is often necessary between the 748409 and the system. A general application using PAL to implement the interface and two additional

<

{r

u

V

S2-SO

ADDRESS

CHIP
SELECT

The 748409 operating modes may vary from application to
application. For efficient refresh it is recommended to use
mode 1 and mode 5 to take advantage of the hidden
(transparent) refresh with forced refresh backup.

ADDRESS BUS

U.tJ

B1-BO Cli'O

eso r-

.:

L

RII'O

,~

I

::..

I\.

RASo - - - - + - RAS
~cs

011'0

--=>

AII'O

.- WE

CS7 f-

DYNAMIC
RAM

'I

- ~
CAS

t--

-=>

RAS1

CPU

T

A

CONTROL
ClK

RFCK

RFCK
REFRESH
CLOCK
GENERA'lOR

I

SN74S409
DYNAMIC
RAM
CONTROllER

I

K
AI ~

RAS
A8-0

...... WE

DYNAMIC
RAM

K

'I

f.--J

CAS

I

K...

RAS

RAS2

~

ADS

AII'O

r- WE

WIN

DYNAMIC
RAM

CAs

~L

f---J

MO

I

M1
RFSH

iiAsiN
INTERFACE
PAl8

RFSH 1M2)

RAS3

RASIN

'---

RFRO CAS

WE

,J..

RAS

P

AII'O

WE

DYNAMIC
RAM
CAS

~L

f.--J

CAS

~

<

DATA

t
DA11.BUS

Figure 14. 74S4091n General Application

'"

a-Bit Dynamic-RAM Driver
with Three-state Outputs
SN54/74S700/·1
SN54/74S731/·1

SN54/74S730/·1
SN54/74S734/·1
Ordering Information

Features/Benefits:
I • Provides MOS voltage levels for 16K and 64K DRAMs
• Undershoot of low-going output is less than -0.5 V
Large capacitive drive capabilily
Symmetric rise and fall times due to balanced output impedance
Glitch-free outputs at power-up and power-down
20-pin SKINNYDIP® saves space
'S7301734 are exact replacement for the Am2965/66
'S70017301731 /734 are pin-compatible with 'S21 0/240/241 /244,
and can replace them in many applications
• 'S7OO-1 /730-1 1731-1 /734-1 have a larger resistor in the output
stage for better undershoot protection

SN54S700/-1

J,W,L

Mil

SN74S700/-1

N,J

Com

SN54S730/-1

J,W,L

Mil

SN74S730/-1

N,J

Com

SN54S731/-1

J,W,L

Mil

SN74S731/-1

N,J

Com

SN54S734/-1

J,W,L

Mil

• Commercial devices are specified at VCC±100f0.

SN74S734/-1

N,J

Com

•
•
•
•
•
•

,I

Description:
The 'S700, 'S730, 'S731, and 'S734 are buffers that can drive
multiple address and control lines of MOS dynamic RAMs. The
'S700 and 'S730 are inverting drivers, and the 'S731 and 'S734
are non-inverting drivers. The 'S7001731 are pin-compatible
with the 'S21 0/241 and have complementary enables. The 'S730
is pin-compatible with the 'S240 and an exact replacement for
the Am2965. The 'S734 is pin-compatible with the 'S244 and an
, exact replacement for the Am2966.

~,I

PART NUMBER PKG TEMP ENABLE POLARITY POWER

These devices have been designed with an additional internal

~: resistor in the lower output driver transistor circuit, unlike regular
\, 8-bit buffers. This resistor serves two purposes: it causes a
slower fall time for a high-to-Iow transition, and it limits the
undershoot without the use of an external series resistor.
The 'S700, 'S730, 'S731 , and 'S734 have been designed to drive
the highly-capacitive input lines of dynamic RAMs. The drivers
provide a guaranteed VOH of VCC - 1.15 volts, limit undershoot
'S730 (Am2965)
'S730-1

Invert
Low
S
HighLow

NonInvert

Low

to 0.5V, and exhibit a rise time symmetrical to their fall time by
hailing balanced outputs. These features enhance dynamic
RAM performance.
For a better-controlled undershoot for lightly capacitive-loaded
circuits the 'S700-1, 'S730-1, 'S731-1 and'S734-1 provide a larger
resistor in the lower output stage. Also an improved undershoot
voltage of -0.3 V is provided in the 'S700-1 series.
A typical fully-loaded-board dynamic-RAM array consists of 4
banks of dynamic-RAM memory. Each bank has its own RAS
and CAS, but has identical address lines. The RAS and CAS
inputs to the array can come from one driver, reducing the skew
between the RAS and CAS signals. Also, only one driver is
needed to drive eight address lines of a dynamic RAM. Th~
propagation delays are specified for SOpfand 500pf loaq
capacitances, and the commercial-range specifications are extended
to VCC± 10%.
All of the octal devices are packaged in the popular 20-pin
SKINNYDIP'".

Logic Symbols
'S7oo/-1

HighLow

'S731/-1

'S734 (Am2966)
'S734-1

SKINNYOIP® is a registered trademarkof Monolithic Memories

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

Monolithic l!1!n
IIIemorle. InJnJ.I
8-51

SN54/74S700/-1 SN54/74S730/-1 SN54/74S731/';1 SN54/74S734/-1
Function Tables
'S700/-1

'S730/-1

E1

E2

1A

2A

L
L
L
L
L
L
H
H
H

L
L
H
H
H
H
H
H
L

L
H
L
L
H
H
X
X
X

.x
X
L
H
L
H
L
H
X

.1Y

2Y

E1

E2

1A

2A

1Y

2Y

H
L

Z
Z
H
L
H
L
H
L
Z

L
L
L
L
L
L
H
H
H

L
L
L
L
H
H

L
L
H
H
L
H
X
X
X

L
H
L
H
X
X
L
H
X

H
H
L
L
H
L
Z
Z
Z

H
.L
H
L
Z
Z
H
L
Z

I:l
H
L
L
Z
Z
Z

L
L
H

'S734/-1

'S731/-1

E1

E2

1A

2A

1Y

2Y

E1

E2

1A

.2A

1Y

2Y

L
L
L
L
L
L
H
H
H

L
L
H
H
H
H
H
H
L

L
H
L
L
H
H
X
X
X

X
X
L
H
L
H
L
H
X

L
H
L
L
H
H
Z
Z
Z

Z
Z
L
H
L
H
L
H
Z

L
L
L
L
L
L
H
H
H

L
L
L
L
H
H
L
L
H

L
L
H
H
L
H
X
X
X

L
H
L
H
X
X
L
H
X

L
L
H
H
L
H

L
H
L
H
Z
Z
L
H
Z

8-52

IIIIonoIIthIo

m

Memories

.z

Z
Z

SN54/74S7001-1

SN54/74S7301-1

SN54/74S731/-1

SN54/74S734/~1

IEEE Symbol

'8700/-1
1

E1

~i
;1
'11
.,

E1

~.

2

lAl

~"I

'S730-1

..... J EN
t>

4

lA2
lA3
lA4

I

1Y2

lA2

14

1Y3

lA3

8

12

tY4

lA4

E2

EN

'1

r

t>

13

2A2

I
2A3
2A4

lAl

6

11

2Al

"

lYl

18

19

E2

18

9

"

7

15

5

17

3

2Yl

2Al

2Y2

2A2

2Y3

2A3

2Y4

2A4

1

.... IEN
~.

2

t>

.' ;

4
6

"-

8

18

lYl

16."

tY2

14
12

19 .....

tY4

I EN
~.

11

t>

13

"

15

.

I-

9

2Yt

7
5

17

t-.

3

2,\,4

I
'S734-1

'S731/-1

E1
lAl
lA2
lA3
lA4

E2
2Al
2A2
2A3
2A4

1

.......

E1

EN

2

t>

4

"

6
'8

19
11
13

18

-

,

16
14
12

1Yl

lAl

lY2

lA2

1Y3

tA3

lY4

1A4

E2

,

EN·

t>

"

'9

t-.

7

15

5

17

3

2Y1

2A1

2Y2

2A2

2Y3

' 2A3

2Y4

2A4

1

r-..J EN
~.

2

t>

4

"

18
16

6

14

8

12

19 .....
11
13

,

tYl

,

lY2
tY3
1Y4

EN

r .

t>

"

9
7

15

5

17

3

2Yl
2Y2 .
2Y3
2Y4

fl~~~~~~~~~~~~~~~
IIIIonoIIIbIo

m."""".,..,

8·53

SN54/74$700/-1 SN54/74S730/-1 SN54/74S731/-1 SN54/74S734/-1

Absolute Maximum Ratings
Supply voltage Vee ..................................................................................... -0.5 V to 7.0 V
Input voltage .. ,........................................................................................ -1.5 V to 7.0 V
Off-state output voltage ............................................................................. -0.5 V to +Vee max
Storage temperature range .............................................................................. -65 0 to +150 0 e
Output current ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 200 mA

Operating Conditions
SYMBOL

Vee
TA

MIN

TYP

Supply voltage

4.5

5

Operating free-air temperature

-55

Electrical Characteristics
SYMBOL

Vll

,

MILITARY

PARAMETER

PARAMETER

MIN

" l

low-level
input current

"H

High-level input current

Vee

c

II

Maximum input current

Vee

c

VOL

low-level output voltage

MIN

Any A

Vee

Any E

c

II

UNIT

5.5

V

75

°e

MAX

COMMERCIAL
MIN TYP MAX

0.8

High-level output voltage

IOZH

t

-1.2

-0.2

-0.2

V

-0.4

-0.4

MAX

VI

20

MAX

VI

- 7V

0.1

20
0.1

IOl

= 1mA

0.5

0.5

IOl

= 12mA

0.8

0.8

IOH

= -1mA

Va

= 0.4V

- 200

- 200

/i A

Va

= 2.7V

100

100

/i A

Vil

= 0.8V

VIH

= 2V

Vil

= 0.8V

VIH

= 2V

VIH

= 2V

Vee

c

Output sink current

Val = 2.0V

IOH

Output source current

VOH - 2.0V

Outputs
High
Vee = MAX
Outputs open

mA
/i A

mA
V

MAX

IOl

Outputs
Disabled

-1.2

- 2.7V

, 5 7XX-1

I-1.15
Vee Vee
-.7

Vee Vee
-1.15 - .7

- 200

-60
'S 7XX

Outputs
low

V

= O.4V

Vee = MAX
Vil = O.8V

Off-state output current

UNIT

V

2

- -18mA

Vee = MIN

50

V

- 200

-60

40

40

- 35

-35

mA

5700/-1

S730/-1

S731/-1

5734/-1

53

75

53

75

5700/-1

5730/-1

86

125

86

125

5731/-1

5734/-1

92

130

92

130

5700/-1

5730/-1

86

125

86

125

5731/-1

5734/-1

116

150

116

150

24

"These are absolute voltages with respect to pin 10 on the device and includes all overshoots due to system and/or test noise.
Do not attempt to test these values without suitable equipment.

IIIIonoIlthio W",emorles

50

mA
mA

50

t'Na! more than one output should be shorted at a time and duration of the short-cHcult should not exceed one second

8-54

5

0

MAX

V,

MAX

Vee = MIN

5u pply Current

4.5

2
Vee

Output short-ci rCUIt current

5.5
125

0.8

Input clamp voltage

lee

TYP

low-level input voltage

Vie

lOS

TYP

MILITARY

TEST CONDITIONS

High-level input voltage

'OZl

MIN

Over Operating Conditions

VIH'

VOH

COMMERCIAL

MAX

24

50

mA

SN54/74S700/-1 SN54/74S730/-1 SN54/74S731/-1 S"54/74S734/-1

~

f
iSwitching Characteristics vcc = 5 V, TA = 25°C
i~

SYMBOL

~

";;:,
I

i

Data to. output delay

tpZL

1.&3

tpLZ

Output enable delay

2&4

Output disable delay

2&4

*it

tpHZ
tSKEW

Output-to-output skew

i

VONP

Output vOltage undershoot

~

~

TEST CONDITIONS

tpHL

~ tpZH

f

FIGURE

tpLH

\1-

t~

PARAMETER

For the 'S7OO, 'S73O, 'S731, 'S734
MIN

TYP

MAX UNIT

CL =SOpf

6

9

15

CL=SOOp!

18

22

30

CL=SOpf

5

7

15

CL =SOOp!

18

22

30

S

= 1

12

.20

S

=2

12

20

ns

ns

S

=1

11

20

S

=2

~.S

12

1&3

CL = SOp!

±O.S

±3;0

nl!

1 &3

CL = SOp!

0

-0.5

It

ns

~ *The SKEW·timing specification is guaranteed by design, but not test~.

~Switching Characteristics

Over Operating Range"" For the 'S700, 'S73O, 'S731, ;S734

tt

SYMBOL

PARAMETER

FIGURE

TEST CONDITIONS

.

CL = SOpf

tpLH
Data to output delay

1 &3

tpHL

iII

tPZL

.\"

Output enable delay

Output disable delay

VONP

Output voltage undershoot

4

4

20

'.' 1"1-

CL = SOOp!

18

40

18

35

C L = SOp!

4

20

4

17

CL = SOOp!

H!

40

18

35

= 1t

. 28

28

S

= 2t

28

28

S

= 1t

24

24

·8

=2t

16

Hi

-0.5

-0.5

2&4

2&4

tpHZ

COMMERCIAL
VCC= 5~OV ±10"lo
MIN T·YP M~X UNIT

S

tpZH
tpLZ

MILITAR·Y
VCC =5.0V±10"lo
MIN TYP MAX

1&3

CL = SOp!

I.,AC performance over the operating temperature I~ guaranteed by testing as defined In Group .A, Subgroup 9, Mil Std 8838.

ns

ns

ns

.'

V

:t"s = 1" and "5 = 2" refer to the switch setting In Figure 2.

IttT

c: -5510

+ 125°C forflatpack versions.

.

!Switching Characteristics vcc = 5 V, TA =.25°C
SYMBOL

PARAMETER

FIGURE

tpLH
Data to output delay

1&3

tpHL

:,
I
~

tpZL

tpLZ

i

2&4

Output disable delay

2&4

tpHZ

{;, tSKEW

i~

Output enable delay

tpZH

VONP

For the 'S700-1, 'S73O-1,

'S731~1, 'S734-1

TEST CONDITIONS

MIN

TYP MAX

CL:= SOp!

6

9

15

CL =' SOOp!

.18

22

30

CL= SOp!

5

7

15.

CL = SOOp!

18

22

40

S '=1

12

20

=2

12

20

S =1

11

20

S =2

6.5

12

S

Qulput-to-ouiput skew

1&3

CL = SOpf

Output voltage undershoot

1&3

CL = SOp!

.

UNIT

ns

ns

ns

±O.S

±3.0

ns

0

-0.3

V

The SKEW timing speCificallonisguarenteed by design, but not test~.

MonoIIthIcm ..~

8";55

SN54/74S700b1 SN54/74S7:JCU-1 SN54/74S731/-1 SN54/74S734/-1

..

Switching CharacterlBtI.cs

over Operati.,g Range" For the 'S700-1, 'S73O-1, 'S731-1, 'S734-1

PARAMETER

S.YMBOL

FIGURE

Data to output delay

1&3

tpHL
Output enable delay

2&4

tpZH
tpLZ

Output disable delay

2&4

tpHZ
VONP

Output voltage undershoot

1&3

= 50p!

MILlTARYtt
COMMERCIAL
Vcc = S.OV ±10"1. VCC = S.OV ±10%
MIN TYP MAX ~IN TYP MAX UNIT
4

20

4

17

C L = 500p!

18

40

18

35

CL = 50p!

4

20

4

17

CL = 500p!

18

50 18

45

S

28

28

S

28

28

24

24

16

16

-0.3

-0.3

CL

tpLH

tpZL

TEST CONDITIONS

= 1t
=2t
S = 1t
S =2t
CL = 50p!

•• AC performance over the operating temperature is guaranteed by testing as defined in Group A, Subgroup 9, Mil SId 8838.

t"s = 1" and "5 =2"

reler to the switch selling in Figure 2 ..

tt T C =-55 to + 125· C lor ftatpac. versions.

T••tLoad.
VCC

R
680n

J

LZ,ZL

TESTPOINT* ~

1

lCL
50
PF

·tpd specified at CL = 50 and 500pF

~lO1HZ, ZH
"::"

*. Th';"TEST POINT" is driven by the output under test,
and observed by instrumentation.

figure 1. capacitive Load Switching

8-56

Figure 2. Three-State Enable/Disable

ns

I
I
I

I

ns

!

ns
V

I

I

SN54/74S7001-1 SN54/74S7301-1 SN54/74S731/;;,1 SN54/74S734/-1
Typical Switching Characteristics
VOLTAGE WAVEFORMS

ENABLE
INPUT

'------oV
S700, 730/-1
---_----.,..

IPHZ

3.0V

---:______....J)IE.sV

S731,734/-1

VOH

ov

~J

IPLH

'----~~,------~OV

~----~~-+~-----Vct

OUTPUT

=========~____~~~======~~~~VOL
OV

OUTPUT
0.5V

f

---VOL

t

I, ~ II ~ 2.505
I ~2.5MHz

Ir ~II ~2.5ns

IpW~2OOns

IpW~8OOns

1~2.5MHz

Figure 4. Three-State Control levels

Figure 3. Output Voltage levels

Typical Performance Characteristics:

...a.,
...

1000

I
100 r---

(J
III
(J

z

E
~
c(J

....,

"<'

~.~,

"Ai,,:;;,,"

a.

...

fI

(J
III
(J

Z

~

(J

~

10

~
c

cc
c

...

10

...C!
1.0

o

10

20

30

40

.'

1.0

50

0

10

20

IpLH-ns

30

40

50

IPHL -ns
'" INOICATE MINIMUM VALUES AT 2S'C•
• INOICATE MAXIMUM VALUE AT 2S'C.

I

)

Figure Sa. tplH forVOH ~ 2-7 V va. Cl' for the 'S7OO series
1000

...

!il

100

'~.

t

lOOO~~--~--~L--~--~
~

'

I-ii

t!
u

.~

s.. tPHL for VOL ~ o.a,Vvs. Cl' for the 'S7OGseries

..
c, ,r..~1
~'

!i

(J
III

figure

.

j~~V

..• ..
~

~x_ --:"

10

...~
1.0 0

10

20

30

40

1.0 0!----I1L,. 0-...J2O-...,..J30'-.....I
4O-....J
5O

50

'PHL -05
I,',.,

i
,

IpLH -. ns

"'INDICATE MINIMUM VALUES IIif 2S'C.
WINDICATE MAXIMUM VALUE AT 2!i'C.

Figure 5b; tPLH fot VOH "2-7 V va. CL. for the 'S700-:1series

IIIIenoIIIhIo

Rgure lb. tpHl for VOL = o.a V YS. Cl. for the 'S7(JO.;.1181ies

W Memories

SN54/74S700/-1 SN54/74S730/-1 SN54/74S731/-1 SN54/74Sl'34/-1
Applications

The 'S700, 'S730, ·S731. and 'S734 have a modification in their
output stage, in that an internal resistor is added to the lower I
output stage as shown in Figure 10.

The'S700, 'S730, 'S731 and 'S734 are 8-bit bipolar dynamic RAM
drivers and are pin-compatible with the 'S21 0, 'S240, 'S241 and
'S244 respectively.

The 'S7OO-1, 'S730-1, 'S731-1 and 'S734-1 have a larger resistor,
R2, com parted to the "non-dash" parts, which give better
undershoot protection at a slightly slower switching performance.

The actual circuit conditions that arise for driving dynamic RAM
memories are as follows: Typically, in dynamic RAM .. arrays
address lines and control lines, RAS, CAS, and WE have a fair
amount of "daisy chaining." The daisy chaining causes an
inductive effect due to the traces in the printed cir~uit board; the
dominant factor in the RAM loading is input capacitance, and
these two conditions contribute to the actual driver conditions
shown in Figure 7. The result is a transmission line with
distributed inductance and capacitance connected to the driver
outputs.
ENABLE
ADDRESSI
CONTROL
RAM INPUT
CAPACITANCE

/

TBACE INDUCTANCE

.-A'

Figure 7.

I

I

I

...

The structure in Figure 10 provides a driver output impedance
of approximately 18n to 2Sn in either high (S = 1) or low (S = 2)
states as shown in Figure 11.ln addition, thiscircuitlimits undershoot to -O.SV, essentially eliminating that problem; provides a
symmetrical rise and fall time; and guarantees output levels of
VCC -1.1SV needed for MOS High levels. Also, when using the
'S700, 'S730, 'S731 and 'S734, no external resistors are needed.
'S240-series parts used with external resistors to provide drive
capability, but the rise times and fall times are unsymmetrical
due to higher impedance for low-to-high transitions.

~

Figure 12 shows the undershoot problem using a 'S240 without
external resistors and the elimination of the problem by using
the 'S730. Thus from a dynamic-RAM system-design viewpoint,
the 'S7OO, 'S730, ·S731. and 'S734 are very effective RAM drivers.

T

-+----+_---<10-

RAM Driver Output To Array

The transmission line effect can imply reflections, which in turn
cause ringing, and it takes some time before the output settles
from the low-to-high transition. On the high-to-Iow transition,
along with ringing, a voltage undershoot can occur, and the
circuit takes even longer to settle to an acceptable zero level.
The main cause for the shorter high-to-Iow transition as
compared to the low-to-high transition is the output impedance
of typical Schottky drivers. Figure 8, shows a typical Schottky
driver output stage and Figure 9 shows the output impedance
for high and low output states.

Figure 12. Comparison ot Undershoots and tpHL

Figure 8. Typical Schottky
Figure 9. Driver
Driver Output
Output Impedance
In Figure 9 when S=1, the output is high and the driver output
impedance is approximately 3011. When S=2, the output is low
and the driver output impedance is approximately 311. There is
a 10:1 ratio for the output impedances for the low and high
states. The high-to-Iow transition causes a problem as the
output transistor turns on fast due to the low impedance and
undershoot results at the RAM inputs.

t~

VCC

1

18·2SU

40

2!~
Figure 10. '5700, '5730, 'S731,
and '5734 Output Stage

8-58

18-2S!l

Figure 11. Driver Output
Impedance For the 'S700,
'S730, 'S731, and 'S734

IIIIonoIlthlc

An application using these 8-bit drivers to interface address and
control lines (and data lines) to a dynamic RAM array using
64K DRAMs is discussed. The signals needed for the controls
are RAS, CAS, and WE. The address lines are AD-A7 and the
data lines are shown as the high and low byte. The array is
shown in Figure 13. It consists of four rows of DRAMs; each
row has individual RAS, CAS, and WE lines. However, all four
rows have common address lines AD-A7. The RAM capacitive
loading for RAS, CAS, and WE is about 10 pf per input. The
loading of the address lines is about S to 7 pf per input. The
loading of the RASi' CASi and WEj inputs to each row of
memories is 160 pf. Note that RASi and CASi come from the
same driver. which reduces timings skews which might arise if
they were output from separate drivers. The address lines are
outputs from another driver, and the loading on each line is 320
pf (S pf loading times 64 DRAMS). At this point it is worth
noting that if a 320-pf loading affects performance unduly, then
the address lines can be split between two drivers with each
having a load of 160 pt. reducing overall signal delay.
If an error-detection-and-correction scheme is used, then typically
the row size expands to 22 bits from the 16 bits shown in the
example. The 'S7OO, 'S730, 'S731 and 'S734 drivers lend themselves
to such expansion, as their propagation delays are specified at
SOpF and also at SOO pF.

W lIIIemo"'es

I
SN54/74S700/-1 SN54/74S730/-1 SN54/74S731/-1 SN54/74S734/-1
jl~~~~~~~~~~~~~iiiiiiliiiiiiiiiiiiiiliiiiiiiiiliiiiiiiiiiii

11
DATA IN
HIGH BYTE

;1

llll~lll

~

:1

I

S700/73017311734/-1
RAM DRIVER

"fa

','

DIN

8,(64KIC1)DRl\Ms

S700173017311734/-1
RAM DRivER

I I

l l l

~

S700/7301731/734/-1
RAM DRIVER

DATA IN
LOW BYTE

1
a

I

S700173017311734/-1
RAM DRIVER

RAS

CASii

CAS

CAS

WED

WE

WE

DIN

8 (64K x l)ORAMs

AO'A7

DOUT

'~

I J
DIN
8 (64K x 1) DRAMs

1
a

RASO

RAS

AO-A7

DOUT
"

WRITE ENABLE
INPUT(S)

RASAND CAS
INPUTS

RAS
CAS

RASl

liAs

CASI

CAS

WEI

WE

I

DIN
,

a(64Kxl)DRAMs

WE

AO-A7 ,,'
,

DOUT

I

AO'A7

+,'
°IN

8 (64K x l),DI'IAMs

RAS

-CAS

,'RAS2
CAS2

WE ~E2

,

.:

,:'

.

J J

:

RAS
CAS

WE

DIN

8(64Kxl)DRAMs

AO-A7

DOUT

+

DIN
8(64Kxl)DRAMs

RAS
CAS
WE

",

"

AO-A7

I

DbuT

DOUT

+

liAS3

RAS

CAS3

CAS

WE3

I

DIN

8(64Kxl)DRAMs

WE

AO-A7
AO'A7

DOUT

DAJ:UT
,HIGH BYTE

S700/730/731/734/-1
RAM DRIVER

{a
ROW/COLUMN ADDRESS

Figure 13. 256KX 16 Dynamic RAM Array with RAM Driverls '

DOUT

OArl OUT
,LOW BYTE:

SN54/74S700/-1 SN54/74S730/-1 SN54/74S731/-1 SN54/74S734/-1
Die Configurations
SN54/74S730/-1

SN54174S700/-1
20

9
2Y1

1

20

E1

vee

19

Eli

11
2A1

10

GND

Die Size: 62x87 mil 2

SN54/74S734/-1

SN54/74S731/-1
1

20

E1

2A1

a-6()

2Y1

IIIIonollthlc

W Memo,./es

20

vee

19

Eli

~I

Quad Power Strobe

II HD1·6600·8
t HD1.6600·5

t

t HD1·6600·2
I
.··1
I

Ordering Information

Features/Benefits
•
•
•
•

High drive current-ZOO mA
High speed-40 ns typical
Low fan-In (250 p.A Max), TTL-compatible
.Low po_r: Standby
30 mW/clrcult
Active
120 mW/circult
• Several different po_r-supply levels

PART
NUMBER

PACKAGE

TYPE

TEMPERATURE
RANGE

HDH)6OQ-5

J14

Power

O' to +75'e

HD1-6600-2

J14

Power

-55' to+125'C·

HD1-6600-8*

J14

Power

,.55'

to +125'e

Description
The HD1-6600 quad power strobe are four high-current drivers
used for power-clown mode of ROM/PROM and other logic
devices. Vee can be removed from nonactive devices in or(lerto
reduce total system power.

Pin Configuration

Block Diagram

Test Load

Test Waveforms
1/4 HD1-6600
>O-"--H~ TEST POINT*

INPUT

PULSE
GENERATOR

*

Ii

The "TEST POINT" is driven by the output under test,
and observed by instrumentation.

"Note: Parts suffixed -8 are equivalent to parts suffixed -2 screened In accordance with MIL-STD 883 method 5004, Class B.

~" --------------------------------------------------iiiiiiiiii----;;;;;;;;;iiiiii;;;;;;;;;;;;;;;;;~~
. . . .
.. "
. "."
."
.
~~ mllft

I.·

TWX: 910-338-2376
[ 2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

~·I
i

"mOM

::-UWW
"8~61

HD1·6600·2

HD1·6600·5 HD1·6600·8

Absolute Maximum Ratings
Supply voltage. VCC1 ...................................................................................•........ +8 V
VCC2 ................................................................................ +18 V (HD1-6600)
VCC3 ................................................................................ +18 V (HD1-6600)
Input voltage .......................................................................................... -1.5 V to +5.5 V
Input current ......•...................................................................... ;.......... -25 mA to +5 mA
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -300 mA
Storage temperature range .............................................................................. _65° to +150°C

Operating Conditions
PARAMETER

SYMBOL
VCC1

Supply voltage 1

VCC2
VCC3

MILITARY

COMMERCIAL

MIN TYP MAX

MIN TYP MAX

4.5

5

5.5

Supply voltage 2

10

12

13.8

Supply voltage 3

4.5

5

5.5

-150

-200

IOH

High-level output current

TA

Operating free-air temperature

-55

125

4.5

5

5.5

10

12

UNIT
V

13.8

V

5

5.5

V

-150

-200

mA

75

°C

4.75

0

Electrical Characteristics Over Operating Conditions
Over Recommended Operating Free Air Temperature Range VCC2 = 12.0V VCC3 = 5.0V
SYMBOL

TEST CONDITIONS

PARAMETER
= 2.4V
=O.4V

IIR
IIF

Input current

VIN
VIN

VIH
Vll

Input threshold voltage

VCC1 = 4.5V

VOH

Output voltage
(One strobe enabled)

VCC1 = 5.5V

= -150mA

VOL

VCC1 = 5.0V
VIN =2.4V

10l

= 500p.A

ICC1

VCC1 = 5.5V

VIN

= 2.4V

ICC1

VCC1 = 5.5V

VIN

= O.4V

VCC1 = 5.5V
VIN =O.4V

10H

= -150mA

VCC1 = 5.5V
VIN =2.4V

10l

=0

ICC2

30
-250
0.8

10H

ICC2

-80
2.0

VCC1 = 5.0V
VIN =O.4V

Supply current
(All strobes enabled)

MIN TYP MAX

4.75

4.85
0.9

UNIT
p.A
V
V

1.0

V

4

6.0

mA

4

6.4

mA

50

60

mA

10

12

mA

Switching Characteristics
VCC1 = 5.OV VCC2 = 12.0V VCC3 = 5.0V TA = 25°C
TEST CONDITIONS
SYMBOL

I

PARAMETER

(SEE STANDARD TEST LOAD)

MIN TYP MAX

UNIT

Ion

Turn On delay

40

75

ns

toff

Turn Off delay

Rl = 31.60

40

75

ns

tr

Rise time

Cl = 620pF

35

65

ns

It

Fall time

35

65

ns

8-82

Monolithic WMemorles

H01-6600-2 H01-6600-5 H01-6600-8

Oie Configuration

12

GND

Ne

13

Die Size: 90x67 mil2

I

I

IIIIonoIHhIc WMemories

8-63

Notes

8-64

IIIIonoIHhIcW.emories

Table of Contents
ARITHMETIC ELEMENTS AND LOGIC
Contents for Section 9 .....................•......... 9-2
Arithmetic Elements Selection Guide .................. 9-2
SN54/74S381 Arithmetic Logic
Unit/Function Generator ........................... 9-3
SN54174S182 Look-Ahead Carry Generators ........... 9-9
SN5417 4S148 High Speed Schottky Priority Encoders .. 9-12
SN54174S348 High Speed Schottky Priority Encoders .. 9-12

Arithmetic Elements and Logic Selection Guide
Arithmetic and Logic Elements
DESCRIPTION
4-bit ALU
4 Grol,lp

carry-took~head

generator

PART NUMBER

MAX ADD
TIME

MAX CARRY (OR
GENERATE) TIME

PINS

51748381

27 ns

20 ns

20

7 ns

16

51748182

Encoder Priority
DESCRIPTION

PART NUMBER

OUTPUT

MAX LOGIC DELAYS

PINS

High-Speed Schottky Priority Encoders

SN54174S148
SN54/74S348

Totem-Pole
3-State

0; - Ai = 13nsec
0i - GS. EO = 15nsec

16

MonolIthic

IU1I ""emorl_

Arithmetic Logic Unit/
, Function Generator
SN54S381

I

SN74S381
Ordering Information

Featuresl Benefits
• A fully parallel 4-bit ALU

TEMPERATURE

PART NUMBER

PACKAGE

SN548381

J,W,L

Military

SN748381

N,J

Commercial

• Ideally suited for high-speed processors
• Generate and propagate outputs for full carry lookahead
• Three arithmetic functions
• Three logic functions
• Preset and clear functions

Pin Configuration

• Available in 20-pin SKINNYDIP®

SN54S381, SN74S381

Description
The '8381 is a Schottky TTL arithmetic logic unit (ALU)/function
generator that performs eight binary arithmetic/logic operations
on two 4-bit words as shown in the function table. These operations are selected by the three function-select lines (80, 81, 82).
A fuiliookahead carry circuit is provided for fast, simultaneous
carry generation by means of two cascaded outputs (P and G) for
the four bits in the package.

Function Table
I

Logic Symbol

I

SELECTION
B

A

Cn

t
tt

Sl

L

L

L

L

L

H

B minus A

SO

I

I

Clear

t

L

H

L

A minus B

L

H

H

A plus B

H

L

L

A0B

H

L

H

A

H

H

L

AB

H

H

H

Preset

+

B

tt

Force all F outputs to be Lows.
Force ali F outputs to be Highs.

SKINNYOIP® is a registered trademark of Monolithic Memories.
!

ARITHMETIC/LOGIC OPERATION

S2

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

Monollthlo I!tln
MemorIes uun.u
9·3

SN54S381 SN74S381
Logic Diagram
en
10

~

....
....

:::1

....

r-rJc
-

>=

....

~D-

FO

AD

;;;;;;;.

11

'>

....
....

~

=t

....
....

•

.At

......;::::;;.

82

....

....
....
....

~

=I

-

A2

F2

=I

13

....
....
....

....

"'"

so

....
....

51

....
....

52

.....
....

I

g)

'"

. . P-- ~
.... 1
~
.....~ rL',
....1
....
....

•
•-

::I

A3

9-4

F1

Lh

~D- F3

SN54S381

SN74S381

Function Table
OUTPUTS

INPUTS
FUNCTION
Clear

B minus A
(Inverse
Subtraction)

S2

S1

SO

0.

0.

0.

0.

A minus B
(Subtract)

0.

0.

F3

F2

F1

FO

G

P

X

X

X

X

X

X

X

X

X

0.

0.

0.

0.

0.

0.

0.
0.
0.
0.

0.

0.
0.

0.
0.

0.
0.

0.

0.

0.

0.

1

1

1

1
1

1
1

1

1

1
1

1

0.

0.

0.
0.

1
1

1
1

1
1

1
1

0.

0.

0.

0.

0.

0.

0.

0.
0.

1

1

1

1

1

1

1

1
1
1
1

0.
0.

0.
0.

0.
0.

0.
0.

0.

0.

0.

0.

0.

0.

.0.

1

0.

1

1

:1

1

1

1

1

1
1

1
1

1
1

1
1

.0.

0.

0.

0.

1

1

1

0.
0.

0.
0.

1
1

1

0.
0.

0.
0.
0.
0.

0.
0.

0.
0.

0.
0.

0.
0.

0.

0.

0.

0.

1

1

1

1

1

1

1

1

0.

0.

0.

1
1

1
1

1
1

1
1

0.

0.

0.

0.

1

1

1

1

1
1

1
1

1
1

0.
0.

1
1
1

0.
0.

0.
0.

0.
0.

0.
0.

0.

0.

0.

0.

1

1

1

1

0.
0.

0.
0.

0.
0.

1
1

1
1

1
1

1
1

0.
1

0.
1

0.
1

0.

1

1

1

1
1

0.

1

0.

0.

0.

0.

1

0.
0.
0.
0.

0.
0.
1

0.
0.
1

0.
0.

0.
0.

0.

0.

0.

0.

0.

0.

1

1

1

1
1

0.

1
1
1
1

0.
0.
1

0.
0.

0.
0.

0.
0.

1
1

1
1

1
1

0.

0.
1
0.
1
0.

1
0.
0.
0.

1

1

1

1

1
0.
0.
0.
1

.1
1
1

1
1
1

1
0.
1
0.

0.
1
0.

1
1

1

1
1

1
1

0.
1

1

0.
1
0.
1
0.
1
0.

Cn A3 A2 A1 AO 83 82 81 80

1

0.

1

1

A plus B
(Add)

0.

1

1

1

1

1

0.

1

0.

1

FUNCTION

S2 S1

A0B
(OR)

A0B
(XOR)

A-B
(AND)

Preset

1 = HIGH voltage level

o = LOW vollage level
X = Don't care

1

1

1

1

0.

0.

1

1

SO

0.:'
1
0.

0.
1
0.
1

0.

X
X
X
X

0.
0.
1
1

1
1

1
1

1

1

1

0.
0.

0.
0.

0.
0.

0.
0.

0.

1

X
X
X
X

1
1

1
1

1
1

1
1

0.

0. 0.
l' 1
0. 0.

1

,

,1

1

X
X
X
.X

0.
0.

0.
0.

0.
0.

0.
0.

0.

0.

0.

0.

1

1

1

1

1
1

1
1

1
1

1
1

0.

0.

0.

1

1

0.

1

X
X
X
X

0.
0.

0.
0.

0.
0.
1

0.
1

0.

1

0.

0.

0.

1
1

1
1

1
1

1
1

0.
1

0.

0.

0.

0.

0.

0.

0.

0.

0.

1

1
1
1

1
1
1

1
1
1

1
1
1

0.
0.
0.

0.
0.
0.

.0

0.

0.
0.
0.

1

1

1

1

1

1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

0.
0.

0. .0.
0. 0.

0.

0.

0.

1

1

1

1

1
1

1
1

1
1

0.

0.
1

0.

0.

1

1

1
1

1

0.
0.
0.

1
1
1

0.

0.

0.
0.

0.

1

1

0.,

0.

1

F3 F2 F1 FO

0.
0.

1

0.
0.
0.
1
0.

1
1

0.

0.

0.

1
1

0.
0.
0.

OUTPUTS

Cn A3 A2 A1 AO 83 82 81 80

0.

0.
1
0.
0.

Function Table
INPUTS

1
1
1

1
1
1

1

1

0.
0.
1

0.
0.
0.
1

0.
0.
0.

SN54S381

SN74S381

Absolute Maximum Ratings
Supply voltage Vee ................................................................................................ 7 V
Input voltage ...................•........•...................•......•............................................. 5.5 V
Storage temperature range ......................................•.............................•...........-65° to +1500 e

Operating Conditions
SYMBOL

MILITARY
MIN TYP MAX

PARAMETER

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

5

COMMERCIAL
MIN TYP MAX

5.5

4.75

125

0

5

UNIT

5.25

V

75

°e

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL

Low-level
input voltage

VIH

High-level
input voltage

Vie

Input clamp
voltage

IlL

Low-level
input current

TEST CONDITIONS

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

0.8

0.8

2
Vee = MIN

Vee = MAX

-1.2

-1.2

Any S input

-2

-2

en

-8

-8

All others

-6

-6

Any S input
IIH

*

High-level
input current

Vee = MAX

VI=2.7V

II

Maximum
input current

Vee = MAX

VI = 5.5 V

VOL

Low-Level
output voltage

Vee = MIN
VIL = 0.8V

VIH = 2 V
10L = 20mA

VOH

High-level
output voltage

Vee = MIN
VIL = 0.8 V

VIH = 2 V
10H = -1 mA

lOS

Output shortVee = MAX
circuit current *

lee

Supply current Vee = MAX

50

50

en

250

250

All others

200

200

1

1

0.5

0.5

2.4

3.4

-40

2.7
-100

105

160

Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

9·6

MonolHhlc

W Memories

V
V

11= -18mA

VI = 0.5 V

UNIT

3.4

-40
105

V

mA

/lA

mA
V
V

-100

mA

160

mA

SN54S381 SN74S381
Switching Characteristics vcc =5 V, TA =25°C
SYMBOL

TEST CON[)ITIONS

PARAMETER

FROM
(IN PUn

(See Interface Tell LoadlWaveIonnl'

TO
(OUTPUT)

5174S381
TYP MAX

UNIT

tp

Propagation delay time

C

Any F

10

17

ns

tp

Propagation delay time

Any Aor B

G

12

20

ns

tp

Propagation delay time

Any A o.r B

P

11

18

ns

tpLH

Propagation delay,
low-to-high

18

27

ns

AnyAorB

AnyF
16

25

ns

18

30

ns

tpHL

Propagation delay,
high-to-Iow

tp

Propagation delay time

CL=15pF

RL = 280!l

AnyF, G, P

AnyS

Test Load
*TESTPOINT

*

The "TEST POINT" is driven by the output under test,
and observed by instrumentation.

16-BIT ALU (USING 74S381)
748381

WORST CASE PATH DELAY I!J!!I::l!l!]

MAXIMUM DELAY OF ADDITION/SUBTRACTION.
74S381 + 74S182
1-4 bits
5-16 bits
17-64 bits

27ns
44ns
64ns

.. MonoIllhlc Wllllamories

9·7

SN54S381 SN74S381
Die Configuration

: Die Size: 83 x 86 mU 2

9·8

I/IIonolithic W·ftllemories

Look-Ahead Carry Generators
SN54S182 SN74S182
i

Ordering Information

Features/Benefits
• Provides lookaheadcarry seross a group of four 'S3815

j

~I

PART NUMBER

PACKAGE

• Capable of multllevellookahead carry for high-speed
arithmetic operations over long wordlength5

TEMPERATURE

8N548182

F,J,W,(20L)

Military

• High-speed operation

8N748182

N,J

Commercial

I Description
The 8NM8182 and 8N748182 are high-speed, lookahead
darry generators capable of anticipating a carry acroSs four
bin,ary adders OJ group of adders. They are cascadable to
pertorm full lookahe!fd across n-bit adders. Carry, carrygenerate and carry-propagate functions are provided as enumer,ated in the pin designation table below.

Logic Diagram

t:=::i
~

::>
)

+ P2 P1 GO + P2, P1 PO Cn

G" G3+ P3 G2 + P3 P2 G1
P :;'P3 P2

-

Summarizing Tables
FUNCTION TABLE

Cn+z = Y2 {X2 + Y1 IX1 +YO (XO + Cn)])

FOR Cn+y OUTPUT

Y :; Y3(X3 + Y2) (X3 + X2 + Y1) (X3 + X2 + X1 + YO)
X = X3 + X2 + X1 +xo

c:D-

en

or

Pin, Configuration

en +x

Go

P1 PO

Cn+y = Y1 IX1 + YO (XO + Cn)]

Cn+y

)

J

Po

+ P3 P2 P1 GO

Cn+x :; YO (XO + Cn)

.:>.

~

Cn+y:; G1 +P1 GO + P1. PO Cn

=: G2 + P2G1

en +z

--<

The carry functions (input, outputs, generate and propagate)
of the carry lookahead generators are implemented in the
compatible fonn for directed connection to the ALu. Logic
equations for the '8182 are:
Cn+x :;GO + PO Cn
Cn+z

::>

;=::;

When used in conjunction with 748381, 74F381, 748181 or
2901 arithmetic logic units (ALU), these generators provide
high-speed carry lookahead capability for any word length.
Each '$182 generates the lookahead (anticipated carry) across
a group of four ALUs and, in addition, other carry lookahead
circuits may be employed to antiCipate carry across sections of
four look-ahead packages upto any number of levels.

G1 GO P1 Po en

INPUTS

OUTPUT
Cn+y

LXXXX

H

XLLXX

H

XXLLH

H

INPUTS
GO prj" en

INPUTS

OUTPUT

P

L

L

L

L

L

All other
combinations

FUNCTION TASlE FOR ~ Ol:rrPUT

INPUts

X X X L L

L. L

H

X L H

H

All other
combtnations

H

FUN~ON' TAB~E FOR Cn+ z OUTPUT

INPUTS

OUTPUT

02 "G1· GO ,P2 P1 'PO en

Cn+ z

'L

·L

L

,x

X X X X X
X L X X L X X

L X

L X X

G

x

X L X L

OUTPUT
Cn+ x

OUTPUT

G3 G2, G1 GO P3 P2. 1'1

x

FUNCTION TABLE
FOR Cn+ x OUTPUT

P3P2P1 Po

Alrother
combinations

L

FUNCTION TABLE
FOR POUTPUT

All other
combinations

X X 'X
L X L

X X X
X X X

H
H

L

X X

L

X

X

H

l

X X,

L

L H

H

H

All other
con:Jbinitions

H =: High Level, L = Low Level, X = IrrelElvant. Any inputs not
shown in a given table are irrelevant with respect to that output.

i

SKINNYDIP" is a registered trademark of MonoliihicMemories.

TWX: 910·338·2316
2'f75Misslon College BlVd. Sania Clara; CA 95054·1592 Tel: (408)'970·9700 TWX: 910:338.2374

.II::!~'I:,':

m
·9·9

SN54S182 SN74S182
Absolute Maximum R a t i n g s ,
Supply voltage Vcc .............. '..................................................................................7 V
Input voltage ......................................................... ; ................... ; ....... ,................. 5.5 V
Storage temperature range ........................................................:; '.......'....•.•..•..... _65°, to +15O"C

Operating Conditions
MILITARY
MIN TYP MAX

PARAMETER

SYMBOL
VCC

Supply VOltage

4.5,

TA

Operating free-air temperature

-55

5

COMMERCIAL
MIN TYP MAX

5.5

4.75

125

0

5

UNIT

5.25

V

75

°c

Electrical Characteristics Over Operating Conditions
SYMBOL
VIL

Low-level
input voltage

VIH

High-level
input voltage

VIC

Input clamp
voltage

Low-level
input current

IlL

High-level
input current

IIH

*

PARAMETER

TEST CONDITIONS

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

O.B

O.B

VCC= MAX

VCC = MAX

-1.2

-1.2

V

Cn input

-2

-2

V

P3 input

-4

-4

II = -1BmA

VI = 0.5V

VI = 2.7V

P2 input

-6

-6

PO, P1, or
G3input

-B

-B

GOor G2

-14

-14

G1 input

-16

-16

Cn input

50

50

P3 input

100

100

P2 input

150

150

PO, P1, or
G3input

200

200

GOorG2

350

350

G1 input

400

400

1

1

0.5

0.5

II

Maximum
inpu,t current

VCC = MAX

VI = 5.5V

VOL

Low-level
output voltage

Vcc = MIN
VIL =O.B V

VIH = 2V
10L = 20mA

VOH

High-level
output voltage

VCC = MIN VIH = 2V
VIL = O.BV 10H= -1 mA

lOS

Output shortcircuit current* VCC= MAX

ICCL

Supply current,
VCC = MAX See Note 1
all outputs low

69

ICCH

Supply current,
all outputs high VCC =5V

35

2.5

See Note 2

9~10

2.7
-100
109

of the short circuit should not exceed one second,

G1 and G2 at 4.5 V; ahd allothera inputs grounded:
leCH Is ~easured with all outputs open, Inputs P3 and G3 at 4.5 V, and all others Inputs grounded.

NOTE: 1. leeL Is measured with all outputs open, inputs GO,
2.

3.4

-40

Not more than one oulputshould be shorted at 8'tlme and duration

Monolithic

V
V

2
VCC= MIN

UNIT

W Memories

3.4

-40
69

35

mA

pA

mA
V
V

-100

mA

99

mA
mA

SN54S182

SN74S182

Switching Characteristics vcc = 5 V, TA = 25°C
TEST CONDITIONS

PARAMETER

SYMBOL

FROM
(INPUn

(See Interlace Test LoacllWavefonnl)

tpLH

Propagation delay
time, low-to-high

GO,G1,G2,G3

tpHL

Propagation delay
time, high-to-Iow

PO,P1,P2 or P3

tpLH

Propagation de.lay
time, low-to-high

GO,G1,G2,G3

tpHL

Propagation delay
time, high-to-Iow

tpLH

Propagation delay,
low-to-high

tpHL

Propagation delay,
high-to-Iow

tpLH

Propagation delay,
low-to-high

tpHL

TO
(OUTPUn
Cn+ x, Cn + y
or
Cn +z

5174S182
TYP MAX
4.5

7

ns

4.7

7

ns

5

7.5

ns

7

10.5

ns

4.5

S.5

ns

S.5

10

ns

6.5

10

ns

10.5

ns

G
CL = 15pF

P1,P2, or P3

RL = 2800

PO,P1,P2or P3

Cn

Propagation delay
high-to-Iow

P

Cn + x, Cn +y
or
Cn +z

7

r-------------------~~4===========~======~~~~CODE

Standard Test Load

co ..

* TEST POINT

Vee

00-

280Il
C4

P

ii'

*

UNIT

Pi

a;

The "TEST POINr' is driven by the output under test,
and observed by instrumentation.

Die Configuration

A 24-b11 ALU made from 'S381s and 'S1828

Ole Size: 53x57 ml12

Monolithic

m

""emorle.

High.Speed SchoHky
Priority Encoders
SN54/74S148 (93S18)
SN54/74S348
Features/Benefits

Ordering Information

• Second-generatlon Schottky designs feature VERY-HlghSpeed compared to other TTL priority encoders

PART NUMBER

PKG

• Totem-pole outputs on SN54n4S148

SN54S148

J,F,W(20L)

Mil

• 111ree-state outputs on SN54n4S348

SN74S148

N,J

Com

Totempole

• SN54n4S148Is speed upgrade for SN54n4148,
SN54n4LS148, 9318, 93L18

SN545348

J,F,W(20L)

Mil

Three-

SN74S348

N,J

Com

state

• SN54n4S348Is speed upgrade for SN54n4LS348

TEMP OUTPUTS

POWER

S

• Encode eight data lines to 3-bit binary (octal) code
• Cascadable In several different ways

Block Diagram

• Glitch on GS line In other TTL priority encoders has been
designed out
• Applications include:
• Interruptlstatus scanning
• Resource allocation In processors/peripherals
• Normalization In floating-point arithmetic units
DATA
INPUT

• Bus arbitration

BUFFERS

• Maximum logic Delays:
-

• OJ -

GS
EO

• tZX(EI to Aj)
• tXZ(EI to Aj)

13nS}
15ns

ENCODING
MATRIX

'5148 and 'S348

15ns

3

CODE
OUTPUT

BUFFERS!

18ns
} 'S348 Only
15ns
!

Disabled outputs are High for 54174S148 and Hi-Z for 54fl4S34B.

Description
The SN54n45148 and SN54n45348 high-speed Schottky TTL
priority encoders scan 8 data-input lines, and output a 3-bit
binary (that is, "octal") code which is the line number of the
highest-priority data input being asserted. To allow expansion
by cascading, in some cases without external logic, both
devices provide three control signals: Ei (Enable Input),EO
(Enable Output), and GS (Group Select).

Pin Configuration

When Ef is not being asserted, the code outputs are forced High
in the 'S148 and into Hi-Z state in the 'S348. When Ei is being
asserted, these outputs are forced to the line-number code; see
"Function Table." Also, when Ei is being asserted, EO and GS
are complementary; EO indicates that no data-input line is
being asserted, whereas GS indicates that at least one of them
is being asserted.

Ei and EO may be used to link encoders together in a "daisychained" configuration. Also, in a two-level cascaded configuration, the GS signals from the first-level encoders are the
data inputs for the second-level encoder(s); see "Applications."
SKINNYDIP" is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Ciara; CA 95054-1592 Tel: (408) 970~!i700TWX: 910-338-2374

9-12

Monolithic I!T!II
lIIemories·· uun.u

5N54/745148 (93518) 5N54/745348

The line-number-code outputs (A2' A1. Aol are totem-pole in
the '8148 and are three-state in the '8348. All inputs and
outputs of both devices are TTL-compatible. Data inputs
present two standard 5481748 normalized loads; Ei, however.
presents only a half of one such load.
The "Function Table" has been stated in terms of High (Hl and
Low (Ll signal levels rather than in terms of "ones" and
"zeroes." The most natural interpretation· of the operation of
these parts is that al/ signals, outputs as well as inputs, are
assertive-low - that is. L is identified with "one" and H with
"zero." Consequently, the highest-priority data input is named
"07" and the output code it produces when asserted is LLL. In
like manner. asserting the input 04 produces the output code
LHH if none of the higher-priority data~input lines 07, 06. or 05
is being asserted; and so forth.

Logic Diagram
E"S

-10

DO

It is consistent with this interpretation that an '8148 outputs a
code of HHH either when it is disabled, or when it is enabled
but none of its data inputs are being asserted. Under the same
circumstances, the code outputs of an '8348 go into Hi-Z state.

Function Table
INPUTS

DD DDD DDD

OUTPUTS

A
2

A

EI

o

H

X X X X X X X X H/Z·

L

H H H H H H H H H/Z· H/Z·

L

X X X X X X X L

L

1 234 567

1

A
0

-

GS

EO

H/Z· H/Z·

H

H

H/Z··

H

L

L

L

L

H
H

L

X X X X X X L H

L

L

H

L

L

X X X X X L H H

L

H

L

L

H

L

X X X X L H H H

L

H

H

L

H

L

X X X L H H H H

H

L

L

L

H

L

X X L H H HHH

H

L

H

L

H

L

X L H H H H H H

H

H

L

L

H

L

L H H H H H H H

H

H

H

L

H

• NOTE: "H" for'S 148, "Z:' for '8348

I

I

9·13

SN54/74S148 (93S18) SN54/74S348
Absolute Maximum Ratings
Operating
Supply voltage vee .......................•..•......... '" .......... , ......•.............................. -0;5 V to 7 V
Input voltage .....................................................•.......•..........•...................• -1.5 Vto 7 V
Off-state output voltage ........•.........•......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .. -0.5 V to 5.5 V
Storage'temperature range •.... , ......................................•.......................... ; ...... ~65° to +150o e

Recommended Operating Conditions
SYMBOL

PARAMETER

Vee

Supply voltage

10H

High level output current'

10L

Low level output current

TA

Operating free air temperature

VIL

Low-level input voltage
High-level input voltage

Vie

Input clamp voltage

4.5

4.75

5

5.5

5

20
-55

+125

0

5.25

V

-1

mA

20

mA

+75

°e

Over Recommended Operating Free Air Temperature Range

PARAMETER

VIH

COMMERCIAL
UNIT
MIN TYP MAX

-1

Electrical Characteristics
SYMBOL

MILITARY
MIN TYP MAX

TEST CONDITIONS

MILITARY
MIN TYP MAX

COMMERCIAL
UNIT
MIN TYP MAX

0.8
2
Vee = MIN

0.8
2

11= -18mA

Ellnput
VI = 0.5V

V
V

-1.2

-1.2

-0.8

-0.8

-3.2

-3.2

V

IlL

Low-level input current Any Input Vee = MAX
ExceptEi

IIH

High-level input current

Vee = MAX

VI = 2.7V

50

50

p.A

Input current

Vee = MAX

VI = 5.5V

1

1

mA

Low-level output voltage

VIH = 2V

10L = 20mA

.5

.5

V

II

mA

Vee = MIN
VOL

VIL =0.8V
Vee = MIN
VOH

High-level output voltage

10H = -1.OmA

VIH = 2V

2.5

2.7

3.4

3.4

V

VIL = 0.8V
10ZL

('s34a

Off-state output current
Low-level voltage applied

Only)

Vee=MAX
VIL = 0.8V
VIH

Off-state output current
High-level voltage applied

Vee=MAX
(,S348
VIL= 0.8V
Only)
VIH =2V

lOS

Short-circuit output current

t

lee

Supply current

10ZH

See note 1

'S148

Vo = O.4V

-50

-50

p.A

VO= 2.7V

50

50

p.A

-100

mA

115

1110

mA

125

120

= 2V

Vee = MAX

-40

Vee = MAX

'S348

0; and Ei Low, other inputs High, and outputs open.
t Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.
NOTE 1: ICC is measured with inputs

9-14

IIIIonoIIthIo

W /#IIemorie.

-100

-40

SN54/74S148 (93S18) SN54/74S348
Switching Characteristics vcc =5 V, TA =25°C
SYMBOL

PARAMETER

tpLH

Low to High

tpHL

High to Low

TO

TEST

(OUTPUT)

CONDITIONS

D1thru D7

AO' A1. or A2

Low to High

tpLH

...

FROM
(INPUT)

tpHL

Propagation

High to Low

tpLH

delay

Low to High

tpHL

High to Low

tpLH

Low to High

. tpHL

High to Low

GS

CL= 15pt

Dothru D7
EO

RL = 2800

GS

Ei

MIN

TYP

MAX UNIT

9

13

ns

9

13

ns

11

15

ns

11

15

ns

12

15

ns

12

15

ns

6

9

ns

6

9

ns

SN54n4S148 ONLY
Low to High

tpLH
tpHL

Propagation

High to Low

tpLH

delay

Low to High

Ei
A()o A1' orA2

High to Low

tpHL

8

12

ns

CL = 15pt

8

12

ns

RL = 2800

10

13

ns

10

13

ns

CL = 15pt

11

14

ns

RL = 2800

11

14

ns

CL = 50pt

12

18

ns

RL =2800

12

18

ns

CL = 5pt

8

15

ns

RL = 2800

8

15

ns

EO

SN54n4S348 ONLY
tpLH

Low to High

tpHL

High to Low

tpZH

Three-state
to High
Three-state
to Low

tpZL
tpHZ

Propagation
delay

Low to
Three-state

tpZH

Th ree-state
to High

tpHZ
tpLZ

A()o A 1• orA2

Ei

High to
Three-state

tpLZ

tpZL

EO

AO' A 1• orA2

Th ree-state
to Low
High to
Three-state

13

ns

13

ns

20

ns

26

ns

A()o A 1• orA2
N/At

DO thru D7'

Low to
Th ree-state

AO' A 1• orA2

" NOTE: Refer to second line of "Function Table".

t NOTE: These values are furnished for the purpose of estimating the logic delays of a combination such as shown in Fig. 1 and 2.
They are design guidelines only and are not tested and therefore not guaranteed.

IIIIonoIIthIc

mMemories

9·15

SN54/74S148(93S18) SN54/74S348
Applications

of this result. Figure 3 shows the highest-speed ''totally-parallel''
approach, which eliminates the potential delay due to daisychaining the enable signal through the first-level parts. The Ei
signals for all of the encoders are grounded, and an 8-way 3-bit
multiplexer comprised of three 'S151s or three 'S251s is used to
select the code outputs of the highest-priority first-level encoder
which has any data-input lines being asserted. The address
lines of these multiplexers are controlled by the code outputs of
the second-level encoder.

The basic logic function performed by these priority encoders
is to scan a paralieLword of any length for the most-significant
Low signal in a field of Highs. Although a single part has only 8
data inputs and hence can only scan a one-byte field, the
architecture of these parts supports several different cascading
schemes.
The Enable Input (EI), when not being asserted, forces the
code outputs (A2, A1, AO) High in an 'S148 or into Hi-Z (hlghimpedance) state In an 'S348. Since all input signals and all
output signals for these parts are conventionally considered as
assertive-low, the effect is to disable the code outputs in the
manner appropriate for a totem-pole part (,S148) or a threestate part ('S348). When Ei is asserted, the code outputs are
forced to the code of the highest-priority data inputs being
asserted; if no data input is being asserted, the code outputs
remain as if the part were not enabled.

Yet another cascading scheme, not shown, uses a single
decoder such as an 'S138 instead of three multiplexers. The
decoder's address-input I.ines are controlled by the secondlevel-encoder outputs as in Figure 3. Its outputs go to the E1
inputs of the first-level encoders, so that only the. highestpriority first-level encoder which has any data-input lines being
asserted gets enabled. The first-level-encoder code outputs are
bussed together as in Figure 2. This scheme is not quite as fast
as that of Figure 3, but is faster than that of Figure 2 since the
daisy-chaining delay is still eliminated.

Also, when Ei is being asserted, the EO and GS signals operate
as complementary "presence" signals. When the encoder asserts
EO, this condition means that none of the data inputs for that
encoder are being asserted, and that a lower-priority encoder
should therefore be enabled to examine its data inputs. Thus,
several encoders may be daisy-chained as in Figures 1 and 2,
with EO from the highest-priority encodercontrolling EI for the
next-highest-priority encoder, and so forth. The highest-priorityencoder is always enabled. In such daisy-chain arrangements,
code outputs may simply be bussed together if three-stilte
encoders are being used, or combined using external assertivelow "OR" logic. Figure 1 illustrates a three-encoder daisy chain
to scan 24 lines; a two-encoder daisy-chain may likewise be
used to scan 16 lines. In each of these cases, no other components besides encoders are needed.

The scheme of Figure 3 can be implemented with either totempole or three-state parts; the others require three-state parts.
Additional schemes are possible. If more than 64 lines must be
scanned, more than two levels of encoders can be used.
Obviously, also, if only 48 or 56 lines must be scanned, a
partially-populated version of one of the 64-bit schemes can do
the job.
Although the original system purpose of priority encoders was
to scan interrupt lines, they are also ideally suited for highspeed normalization scanning of the result of a floating-point
adder/subtracter, in order to determine how many leading
zeroes the result contG\ins in order that the normalization shift
may be performed in one operation by a "barrel shifter" or
"matrix shifter." This result must be in "Negative Absolute
Value" form because of the assertive-low behavior of the
encoder. (See Monolithic Memories Application note AN-111,
"Big, Fast, and Simple - Algorithms, Architecture, and
Components for High-End-Superminis," by Ehud Gordon and
Chuck Hastings, pages 7-8.) Another important application is
"resource control" in computer systems having several semiautonomous active units; for instance, a single encoder followed
by a decoder can arbitrate requests on 8 bus-request lines and
return a single busilrant signal on one of 8 busilrant lines.

A slightly different approach is needed to scan more than 24
lines. Figure 2 shows a 64-line scanner which uses 9 'S3485 and
no other components. These encoders are on two "levels"; the
GS outputs from the first-level encoders are the inputs for the
second-level encoder, and indicate when asserted that the
corresponding first-level encoders do indeed have inputs being
asserted. The bussed first-Ievel-encoder outputs form the leastsignificant octal digit of the 6-bit line-number code for the
highest-priority data-input line being asserted; the outputs of
the second-level encoder form the most-significant octal digit
HIGHEST-PRIORITY OR MOST-SIGNIFICANT

LOWEST-PRIORITY OR LEAST-SIGNIFICANT
0706 05 04 03 02 01 00

23 22 21 20 19 18 17 16

15 14 13 12 11 10 09 08

A A A AA A A 6

666.""-)')')")"

)., )., )., ).,)., )., )., ).,

070605 04 03 02 01 DO

07 06 05 04 03 02 01 DO

07 06 05 04 03 02 01 DO

I~

GS

'S348

EO

A2

Ai

I

r

Au

y

o--cEi
GS

'S348

A2

EO

Ai

y

1

-

NOTES: 1. The two S348s to the right form a 16-81t Interrupt Scanner If EI
for the middle one is grounded.
2. If all 24 inputs are High. 0'2. '01• and 0'0 are in Hi-Z state; 0'4 and 03 are high.

p---<

To

Ei
Gs

r

'S348

EO

A2

Ai

Au

-

-

-

P--

'(

1.

1

.;;;Q;:,4_ _Q=3:!-_Q;;:;:2~_Q::.1,-----,Q;::,0 HIGH IF AT LEAST
ONE OF THE 24
ASSERTIVE-LOW CODE
INPUTS IS LOW
FROM 00000 TO 10111

Figure 1. 24-Bit Leading-Zeroes Detector or Interrupt Scanner Using 'S348s and No Extemal COmponents

9·16

SN54/74S148(93S18) SN54/74S348
63 62

~ ~

56

55 54

••• 6 6 6 •••

07 0 6

00

07 0 6

48

,I,
00

Ei '5348 EO p.:Ei '5348 EO
-

*

as A2A1Ao
IY

1

GS

A2A1Ao

YY't
1

47 46

40

39 38

32

31 30

24

23 22

16

15 14

08

0706

00

07 0 6

00

07 0 6

00

07 0 6

00

07 0 6

00

07 0 6

00

07 0 6

00

b ~ ••• b 6 b··· b 6 b··· b 6 6 ••• ~ i l ... 1, 1)'···)'
Ei '5348 EO p.:Ei '5348 EO
-GS

Ei '5348 EO

-GS A2A1Ao

A2A1Ao

Y Y't

YY't

1

A2A1Ao

AiA1Ao

GS

Ei '5348 EO ~
GS

YY'1'

1

1

A2A1Ao

YYY
I

GS3 BITS 31-24

~BITS23-16

11 ),

), 11

GS7 BITS 63-56

A2A1Ao

Ei '5348 EO
-

Ei '5348 EO
-GS

YY't

1
GS4 BITS 39-32

GS5 BITS 47-40
GS6 BITS 55-48

GS

GS1BITS 15-08

GSO BITS 07-00

070605 04 03 02 01 00

~Ei
-GS
ZERO

MANTISSA
NOTE: II all 54 inputs are High,
Qs-Qo are in Hi-Z state

..

-

'5348

J

~

06

EO

ZERO

MANTISSA

A2A1Ao
yyy

f~:

Qi

Figure 2. 64-Bit Leading-Zeroes Detector or Interrupt Scanner Using '5348s and No External Components
LOWEST-PRIORITY OR LEAST-SIGNIFICANT

HIGHEST-PRIORITY OR MOST-SIGNIFICANT

6362 ... 56

5554 ... 48

4746 ... 40

3938 ... 32

3130 ... 24

GS4
BITS
39-32

2322 ... 16

1514 ... 08

0706 ... 00

GS3
BITS
31-24
GS2 BITS 23-16

GS5 BITS 47-40

GS1 BITS 15-08

GS6 BITS 55-48

GSO BITS 07-00

GS7 BITS 63-56

06 (ZERO MANTISSA)
06 ,ZERO MANTISSA)
I

1-

05~----------~--------------~--------------~----t---~-,
04~~--------~----------------~~------------------~--~---h
03~~--------------------------~~----------------------~~-Hh

NOTE: Encoder. here may be 'S148s or 'S348s; muxe. may be '8151. or '8251 •. If all 64 inputs are High, 05-03 are in Hi-lstate, and °2"00 are notmeaninglul.

Figure 3. Totally-Parallel 64-Bit Leading-Zeroes Detector or Interrupt Scanner

/IIIonoIIIhIc

W Memories

9-17

SN54/74S148(83S18) SN54/74S348

Test Loads
TESTPOINT*

VCC
TESTPOINT*
Rl

F~~~E~~~~T_+-t4-+

(SEE NOTE B)

I

Cl
(SEE NOTE A) -:::

S2

lOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS

lOAD CIRCUIT FOR
THREE-STATE OUTPUTS

*

The "TEST POINr' is driven by the output under test,
and observed by instrumentation.

Test Waveforms
3V
INPUT
OV

OUTPUT
CONTROL
(low-level
enebling)

.,--------3V
'-----------~~---------OV

VOH

IN-PHASE
OUTPUT ______~--,

VOL

WAVEFORM 1
(See_C)

VOH

OUT OF PHASE
OUTPUT
(See_F)

1.SV
VOL

PROPAGATION DELAY

ENABLE AND DISABLE

NOTES: A. C l includes probe and jig capacitance.
B. All diodes are lN916 or 1N3064.
C. Waveform 1 is. for an output with internal conditions such that the output is low except when
disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except whep.
disabled by the output control.
0, In the examples above. the phase relati.onships between inputs and oufputs have, been
chosen arbitrarily.
E. All input pulses are supplied by generators having the following characteristics: PRR
,,1 MHz, Zout = SOOand:
F. When measuring propagation delay times of ~tate outputs, switches 51 and 82 ate closed.

G. Vr= 1.5V

8·18

SN54/74S148(93S18) SN54/74S348
Die Configurations
SN54174S148

GS
PIN 14

i53
PIN 13

56
PIN 3

52
D7

PIN 12

PIN 4

51

E1

PIN 11

PIN 5

DO
PIN 10

Ole Size: 81x70 mil2

SN54174S348

GS
PIN 14

i53
PIN 13

56
PIN 3

52
PIN 12

D7
PIN 4

51

E1

PIN 11

PIN 5

DO
PIN 10

PIN 6

PIN 7

PIN 8

Die Size: 81x70 mil2

IIIIonoIlthlc

W Memories

9-19

Notes

9·20

Mu~tipliers/Dividers . , [ •

:

c

10-1.

J

14

Table of Contents
MULTIPLIERS/DIVIDERS
Contents for Section 10 ....................... ,..... 10-2
Multiplier/Divider Selection Guide .................... 10-2
"Five New Ways to Go Forth and Multiply ............. 10-3
SN54/74S508 8x8 Multiplier/Divider .................. 10-8
SN74S516 16x16 Multiplier/Divider .................. 10-21
SN54174S556 Flow-Thru'· Multiplier Slice ............ 10-37
SN54174S557 8x8 High Speed Schottky Multipliers .... 10-50
SN54/74S558 8x8 High Speed Schottky Multipliers .... 10-50
Die Configuration

Multiplier/Divider Selection Guide
Co-Processor Multiplier/Divider with Accumulator
PART NUMBER

MAX MULTIPLICATION TIME!
MAX DIVISION TIME

PINS

8 Bits

SN74S508
SN54S508

0.8 p.S/2.2 P.s

24

16 Bits

SN74S516

1.5 p.s/3.5 p.S

24

MAXDELAV

PINS

Cra, Multipliers
DESCRIPTION

PART NUMBER

8x8 Multiplier (latched)
8x8 Multiplier (latched)
8x8 Multiplier (latched)
8x8 Multiplier (latched)

SN74S557
SN54S557
SN74S558
SN54S557

60 ns (Xi' Vi; to S15)
60 ns
60 ns
60 ns

40
40
40
40

16x16 Multipliers

SN74S556

90ns

84

Monolithic. Memories

i

Five New Ways to Go Forth and Multiply
Chuck Hastings

Our Multiplier Population Explosion
Recently, it has seemed as if every time you turned around
Monolithic Memories was announcing another new multiplier.
Want to catch your breath, and find out where each of these fits
into the overall scheme of things? Read on.
Actually, there have been five new multipliers in all within the last
three years, plus two which had previously been available for
several years. In time order of introduction, these are:

Parts No.

Description A

57/67558
57/67558-1
54fl4S508

150-nsec 8x8 Flow-Through Cray MultiplierB
125-nsec 8x8 Flow-Through Cray MultiplierB
8-Bit Bus-Oriented Sequential Multiplier/
Divider
6O-nsee 8x8 Flow-Through Cray Multiplier
6O-nsee 8x8 Flow-Through Cray Multiplierwith
Transparent Output Latches
16-Bit Bus-Oriented Sequential Multiplier/
Divider
9O-nsec 16x16 Flow-Through Cray Multiplier
with Transparent Input and Output Latches

54fl4S558
54fl4S557
54fl4S516
54fl4S556

You will notice that the above parts fall into two categories:
flow-through Cray multipliers, and bus-oriented sequential multiplier/dividers. Although all of these parts get referred to rather
casually as "multipliers," there are major differences between
the two general types; see Table 1 below.

The Cray Multipliers
The essential idea of a Cray multiplier, 'as originally put
together by Seymour Cray in the late 1950$ with discrete
logic at Control Data Corporation, is to wire up an array 6f full
adders in the form of a binary-arithmetic-multiplication
pencil-and-paper example,3 That is, everywhere that there
is a "1"or a "0" in a longhand binary-multiplication example, the Cray type of multiplication uses a full adder. One
may visualize a Cray multiplier functionally as a "diamond:'
as follows:
'MULTIPLICAND

MULTIPLIER

NOTES: A. Times are worst-case times for commercial-te~perature-range
parts.
B. Obsolete. 541745558 replaces these in both new and existing

LOWER
,HALF

designs.

DOUBLE·LENGTH PRODUCT

Figure 1. Pencil-and-Paper Analogy to Cray-MultlplierOperation

FI_-Tllrougll Cray Multiplle~

Bus-Oriented &equential Multiplier/Divider

Bui/ding-block role -as many as 34,partsus!!d in one superminicomputer (NORD-SOC from Norsk Data').

Co-processor role - one, or occasionally two, parts used in
one microcomputer'.
'

Static arithmetic-logic network; multiplies without being,
using eight bits of the multiplier at a time,

State machine; requires clocking to operate; contains edgetriggered registers; sequenced by a state counter; multiplies
using two bits olthe multiplier at a time".

External
Control

Controlled by several mode-control input signals.

Controlled by sequences of micro-opcodas which come from
a microprocessor, a registered PAL, or some other seqU'entialcontrol device.

Package

Role in
System
Internal
Operation

clocked~

40-pin DIP (,S557/8); 84-pin LCC or 88-pin PGA (,S556)

24-pin DIP.

Operations
Performed

Can only perform multiplication.

Can perform multiplication, division, and multiplication-wlth'
accumulation.

Storage
Capabilities

Either no storage capabilities ('558 types), or optional storage
for the double-length product only ('557 type), or full
product and input slorage ('556 type).

Four full-length registers; capable of storing both input operands and the double-length product.
'

Second
Sources
Where
Used
Future
Prospects

8x8, Multiple-sourced'(AMD, Fairchild"Monolithic Memories),

Sole-sourced;only bipolar dividers on the market.

Initial usage has been in high-:end minicomputers, array processors, and signal processo(s.

Initial usage has been in industrial-control 'microcomputers,
digital modems. military avionics, CRT graphic systems, video
games, and cartographic analysis systems.

Potential large market today since these parts are now low.
cost and multiple-sourced, and should be used in al/ new millicomputer design~!
'

Potential huge world-wide market for enhancement of microprocessor, bit-slice processor, and microcomputer capabilities,
and for sman-scale signal processing!

Table 1. A comp.tlSOll of the two types of MOn!JIHhiC Memorle. Multiplier.

10..3"

Five New Ways toGo Forth and
Our 57/67558, introduced in the mid-1970s, was the original
single-chip Cray multiplier. To achieve what was for that time
very high performance for a Schottky-TTL-technology part, the
internal design of the 57/67558 also exploited other speed-freak
multiplication techniques such as Booth multiplication 4 and.
Wallace-Tree additions. All ofthese techniques achieve increased
speed through extensive parallelism, and can be used at the
system level as well as within LSI components. Subsequently,
process improvements made it possible to offer a fasterfinaHest
option, the 57/67550-1, which attained a sales-volume level
essentially equal to that of the original part.
About five years ago, AMD paid us the sincere compliment
of second-sourcing these parts with the 75-nsec 258558. Three
years ago, we returned the compliment with the 6O-nsec
54n4S55.8. All of these '558 parts, and the 7D-nsec 54n4F558
announced by Fairchild, are fully compatible drop-in equivalents except for the variations in logic delay.

Multipl~

References 5 and 6discuss technical approaches t6 using Cray
multipliers in high-performance minicomputers. The '8558,
together with PROMs organized in a "Wallace-tree" configuration. can sail right along at the rate of four 56x56 multiplications every microsecond, on the basis of fixed-point
arithmetic with no renormalization. (8ee table 7 on page 16
of reference 5; the multiplication time is 238 nsec for a "division step;' which is afixed-point multiplication. and 319 nsec
for a floafing-point multiplication where extra time is required
for renormalization and correction of the exponent of the
product.) 34 'S558s or 'S557s are required to perform this
multiplication if the computer system architecture does not
call for the computation of the least-significant half of the
double-length product; 49 are required if it does.

\\ .. ,~ 'S558,10GEniER wl'n-l

P~SORGANtza,J

1""·WACI.ACE-l'R€E"CONFI(,URA'110N. CAN SAlt..

RIGHT ALONG AT mE RATE OF FOUR 66" 56

MULTlPl..ICATION5 EVERV MICR066CONP ... "

• Au. Of 11<£SE 'fWoINIQUES ACHI9I€ ItIC_SIOO
SP""O"!ll""IIIE f'ARe:u.e~ISM·"

.

When AMO introduced the 258558, they introduced along
with it the 80-nsec 258557, a "metal option" of the same
basic design with "transparent" output latches to hold the
double-length product. "Transparent" means that the latches
go away when you don't want them there; a latch-control line
like that of the 54/748373 controls whether these output
latches store information, or simply behave as output buffers.
Anyway, when we introduced our 54/748558, we followed it
within a few weeks with the 60-nsec 54/748557, which is a
much faster drop-in replacement for AMO's part. And subsequently, Fairchild has announced a 70-nsec 54/74F557.
Because AMO's '8557 has the output latches implemented in TTL technology after the ECL-to-TTL converters,
whereas our '8557 has them implemented in ECL technology
before' the conversion, the latches operate much faster in
ours. Our '8557 is typically only about a nanosecond slower
than our '8558, whereas the logic~delay difference between
AMD's two parts is considerably greater. Consequently, our
margin of superiority over AMO for the 'S557 is even greater
than for the '8558.
More recently, we introduced the 9O-nsec 'S556, which is a
16x16 direct size-upgrade of the 'S557/8 architecture, with the
addition of input latches. In a "pipelined" mode, an 'S556 can
produce a new 32-bit product every 75 nsec.
'S557i8 Cray multipliers come in a 40-pin duaHnline package,
either ceramic or plastic. Worst-case power-supply current is
280 mA. The 'S556 comes in your choice of. an 84-pin LCC
(Leadless Chip Carrier) or an 88-pin PGA (Pin-Grid Array)
package. Worst-case power-supply current is 800 mA (909 mA
over military temperature range). The data-bus outputs can sink.
up to 8 mA IOL, for all of.these multipliers.
..

10·4

The "local" architecture of the multiplier section of a digital system can take two rather different forms. A minicomputer~ which executes an unpredictable mixture of arithmetic
and logical instructions one after the other, typically needs to
be able to get the complete multiplication over and done with
before gOing on to the next program step-which is probably not another multiplication. An array processor or digital
correlator. however. tends to do very regular iterative computations; and the performance of such a system can often be
greatly increased by a technique called "pipelining;' in which
the arithmetic unit consists of stages with registers or latches
in betWeen each stage, and partial computational results
move from one stage to the next on each clock.
The "flow-through" architecture of the '8558 works
equally well in synchronous or asynchronous pipelined systems, but registers or latches must be provided externally.
The '8557, however, is actually a superset of the '8558, and
the added internal-output-Iatch feature adapts it particularly
well to pipelined systems. The '8556 provides latches atboth ends.

..... THE .WW·l"Iit numbers togetheranp output their entire 32-bit product in 90nsec worst case... less .time· than it would take a
speeding bullet to move the distance Elqual to the thickness of
this piece of paper, How's that for Supermultiplier?

as

The Mul"pll.rIOivi,ders
The Monolithic Memories 'S516 and.'S508 are state-of-theart TTL-compatible irite!ligent peripherals for microprocessors, somElwherebetWeen arithmetic sequential circu)ts
and specialized bipolar microprocessors .. The'S516anO
'S508 each can perform any of 28 differ~nt multiplyanO
multiply-and-accumulate instructions,'plUs any of 13 differ-.
ent divide instructions, at bipolar speeds·underthe control
of an internal statecQUnter. (see'.Figure.20f the ,'S516 data
Sheet.) The state counter'sl!8qtlenpe is. in lurngulded by3-bit
instruction codes which are external inputs to the 'S516/508The '8516 computes with 1&..b.lt bil:1ary numbers, and the '8508
computes with &-bit binary numbers, as the part numbers nonetoo-subtly imply., .
..
.'
. .
A i6-bit bi~directional data bus connects the 'S516 with
the .outside world for bringingin'll'Jultillliers, .. multiplicanps,
dividends, and divisors; and returning products, quotients
and remainders. It also has olock (CK) anc! tun/wait (GO)
inputs, and an overflow indication (OVA) output.

The 'S508 has all of the above inputs and outputs also,
except that it has only an 8-bit bidirectional data bus. Since
it comes in the same 24-pin package as the 'S516, it obviously has eight more pins available for other purposes. Four
of these are used to bring out the internal-state-counter
value; one each is used for a completion (DONE) status
output, an output-enable control (OE) input, and a masterreset(MR) control input; and one is not used atall.
,A Simple, general Interfacing $Chemecan be used to team
a '8516 with any of the currently popular 16-bit microprocessors,or
an '8508 with any 8-bit microprocessor. (See Figure 7ofthe'8516
data sheet.) With a couple extra inierfacecircuits, an'S516 can
also be interfaced to an &-bit microprocessor.Particularly If the
system software is written in a highly-structurecllanguage such
as PASCAL.orFORTH, an'S516/508 can be retrofitted into an
existing system .with a large gain in performance and very little
impact on e,ither hardware or software--; calls to the previous
software-implemented one-stepc8tc8-timemultiply and divide
subroutines are simply rerouted to substitUte a command 'from
the microprocessor to the 'S516/508 to a~Rt an operand and
start its oparation sequence.
.
. .
The 'S516 and 'S5.08 are in fact two ,different "metal
options'" of one basic design; the'S516 hllS twice as many
data bits in each internal register. The 'S516.. and 'S508 /::loth
have a worst-case clock rate ot6 MHz (commercial) or 5
MHz (military); the typical rate is 8 MHz, ThElo sitT,plest cpmplete twos-complement 16x16 multiplication instructiorican
be performed in nine clockcydes by an 'S51.6: or in five by
an 'S508, since 2-bits-at-a.time Booth multiplication is
, used;~ thus, the worst-case time require(jby. tM '6516 to:,
multiply in this modEl is 1..5 /1Soofor ,a commercial' part, and~:";
for.an 'S508 it is 833 nSl;!c. On the same basis, 32/16 division'
can be done in ·21 clock cycles; or 3~5 /1Sec worst-case, by an
'S516;and 16/8 division can be done In .13 clock cycles,' or
2.2 psec worst-case, by an 'S508,' .
An'S516/508.can perform either, positive or. nl;!gative multiplication or multiply-accumulation, and many of the instructions provide for "chaining'" ofsuccessiVEl computations to"
eliminate extra operand transfers on the bus; these features,
further enhance the computational speed of the '6516/508,
in particular applications. Arithmetic can be either integer or
fractional with respect to positioning of the results.
An 'S516 can powerfully enhance the capabilities of any
present-day 16,bit'.or 8-bitmicroprocessor ina compute·
bound application. In fact, it can be usee! in any digital system
where there/sa need .tomultiply and divide on.a bus. An
'S508 can likewise.enhance thecapabi/iti9!! of any 8-bit
microprocessor.

rr;.

...:.

Five New Way. toGo Forth and Multiply
The '5516 comes in an industry-standard 600-mil 24-pin
dual-inline package, modified to include an integral aluminum heatsink w!'lich does not add appreciably to the package
height. It requires only +5V and ground power connections,
and draws a worst-case power~supply current of 450mA
(commercial) or 500mA (military). Power consumption is
greatest at cold temperatures, and decreases substantially'as
operating temperature increases. The 16 databus inputs
require at most 0.25mAinput current; the other inputs
require at most 1mA. The 16 databus outputs can sink up to
8mA 10l. The '5508 also fits the abo,ve description, except
that its worst-case power-supply current is 380mA (commercial) or 400mA (military), and it has only 8 databus inputs
and outputs.
In describing applications of these paris, it is difficult to know
where to start - they can be used in almost any design where a
, microprocessor can be used, and you know how many places
that is today. So, perhaps a good starting point is to see what
uses customers have thought up all by themselves. One customer
even used two '55165 in "pingpong' mode on a single 1&-bit busl
So, rather than merely speculating as to whatthese parts might
be good for, here's a list of what Monolithic Memories's customers have already ptoventhey are good for:
• Real-time control of heavy machinery9
• Low-cost, high-performance digital modems
• CRT graphics, including video games
.. Military avionics
• cartographic analysis
'As it happens, the above are '5516 applications, except
that digital modem designs have been done with both the
'5516 and the 'S508. Several of the 'SS16 designs are already in,
production. In each of these applications, the microprocessor
could have coped all right with the computational complexity, albeit at its own less-than-tremendous speed, but a '5516
used together with the 'microprocessor can provide extra
muscle forh'andling formidable problems.

priced bipolar 16-bit multiplier, an(j the other microprocessor
peripheraLchipswhich can perform division as well as multie
plication are relatively.slow M05,devices. In one case, an
8-bit cascadable CM05 part requires a 50% reduction in
clock rate to do 16-bit arithmetic, And considerable numerical-analysis and programming sophisticatiOn are requiredto
implement Newton-Raphson division with fixed-point operands, (It's'easier with floating-point operands.) In contrast,
the '5516/508 can be easily interlaced to almost any microprocessor using one or two PALs," and can perform either
multiplication or division on command~
The '8516 is so much faster than the competing M08
chips that it can even take them on for floating-poiht computations (which some of them are designed to do) and win. A
conference paperIO describes the design of an 'SS16-based
8-100-bus card' capable of beating an Intel 8087 2:1 on
floating-point arithmetic.
50me competing parts, inparticular the AMI 2811 and
Nippon Electric I'PD7720, include an on-board ROM which
must be mask-programmed at the,factory, which makes life
difficult for small companies (or even larger ones) which are
trying to get a microprocessor-based product to market
quickly. Also, some competing parts require sequencing by
external TTL jellybeans.
And, as for using AMD/TRW 64-pin 16x16 Cray multiplier
chips as microprocessor peripherals, these cost much more
than the '5516, occupy about three times the circuit-bo,ard
space, multiply faster, don't divide at all except by NewtonRaphson iteration, and also require one or two "overhead"
microprocessor instrGctions to interface for a given arithmetic operatioh. From a system viewpoint, when this overhead
time is reckoned with, these chips provide little actual gain in
multiply performance over the '8516 at lots of extra cost, and
an actual loss in divide performance: the '5516 is much more
cost-effective overall.
'8516s potentially fit into many, many places in commercial, industrial, and military electronics, particularly, into
small-scale real-time systems, The part is fast enough to
enhance the performance of a 16-bit Motorola 68000, Zilog
Z8000, or Intel 8086, as well as that of any 8~bit microprocessor. It is also fast enough to considerably improve the multiplicationand division performance of 16-bit 2901-based
"bit-slice" bipolar microcomputers, which are often used as
processors in desktop graphics CF'lT terminals.
It is worth bringing the '8516 to the attention of any
designer who is developing:
• A personal computer or small business computer.
• A word processor, or a more grandiose "office automation
system:'
• A cruise missile, or any other "smart weapon:'
• A digital modem.
• A small-scale speech-processing system. (These are very
multiplication-intensive. We have one maga:zine article on
the 'SS16 in such an application~l)

• Asml;lrt instrument, which (joes data conversion.
Competition? Well, since there are nO second $Ources for
the '8516, and no competitor at present has a similar fast part
capable of performing division as well as multjplication, right
now the '5516 has no direct competition. hlOirectly, there are
$OlTie competing parts which perform only multiplication, and
would have to perform division by Newton-Raphson iteration
to be usable for any application where division is required.
However, the '5516 is (as far as we know) by far the lowest-

10-6

• ,An industrial control system, particularly one which must
do many coordinate transformations:
• A.n all-digital studio-quality high-fidelity system,

• A cost-reduced'computerized medical scanning system.
• A multiprocessor system for scientific computations~2)

If an '8516/508 is introduced into a system configured
around an older microprocessor as a "co-processor" or

Five New Ways to Go Forth and Multiply
helpmate for the microprocessor, and the application is
arithmetic-intensive, the end effect can be a major upgrading of performance at the system level. 27 Consequently, a
major reason for designing these parts in is microprocessor
life-cycle enhancement. In particular. many MOS micropro'cessors have single-length and double-length add and subtract instructions: but either they have no multiply or divide
instructions at all, or else they perform their multiply and
divide instructions so slowly as to jeopardize the ability 01 the
entire system to handle its computing load in real time.
So picture; if you will, the entrepreneur or chief engineer
of a firm making a successful microprocesSot"based widget
which has been on the market for a few months, which uses
an older 8-bit microprocessor such as a 6800 or 8085 or Z80.
Just when his/her sales are really taking off, here comes a
new start-up competitor with a similar system, using a
Motorola 68000, with added features and faster performance
made possible by the 68000's 16-bit word length and
multiply/divide capabilities. The 'S516 can, in this instance,
serve as a "great equalizer" - it can be retrofitted into the
older system as previously described, and provides even
higher-speed multiplication and division than the 68000.
(Enough so, actually, that there are designers using the 'S5.16
with the 68000.) Thus, the 'S516 can dramatically extend the
life cycle of existing microcomputer systems based on
microprocessors which either don't have multiplication and
division instructions, or perform these operations relatively
slowly.

'S508s are somewhat easier to control from a logic~esign
viewpoint than 'S516s, purely because they have more control inputs and outputs. However. the shorter 'S508 word
length makes the part naturally fit into smaller-scale systems
than those which might use an 'S516. Essentially, the 'S508
is optimized for small-scale systems.
Now that you know what these parts are, can't you think of
at least half a dozen prime uses for them right in your own
back yard?

References (all available from
Monolithic Memories)
1. "Combinatorial Floating Point Processor as an Integral
Part of the Computer," Tor Undheim, Electro/80 Professional
Program Session Record, Session 14 reprint, paper 14/1,
2. "SN54174S516 Co-Processor Supercharges 68000 arithmetic,"
Richard Wm. Blasco, Vincent Coli, Chuck Hastings.and
Suneel Rajpal, Monolithic Memories Application Note
AN-114.
3. "How to Design Superspeed Cray Multipliers with 558s;"
Chuck Hastings, included within the SN54174S557/8 data
sheet.
4. "Doing Your Own Thing in High-Speed Digital Arithmetic,"
Chu.ck Hastings, MonolithicMemories Conference Proceedings reprint CP-102.
5. "Big, Fast, and Simple - Algorithms, Architecture, and
Components for High-End Superminis," Ehud Gordon
and Chuck Hastings, Monolithic Memories Application
Note AN-111.
6. "Fast 64x64 Multiplication Using 16x16 Flow-Through Multipliers and Wallace Trees," Marvin Fox, Chuck Hastings and
Suneel Rajpal, Monolithic MemoriesConference Proceedings reprint CP-111.
7. "An 8x8 Multiplierand8-bit,..p Perform 16x16 Bit MulHplication," Shai Mor, EON, November 5,1979. Monolithic Memories Article Reprint AR-109.
8. "Using a 16x16 Cray Multiplier as a 16-Bit Microprocessor
Peripheral to Perform 32-Bit Multiplication and Division,"
Chuck Hastings, Monolithic Memories Conference Proceedings reprint CP-140

" ... THE'SSlb CAN I>RAMATICA~~Y EXTENt> THE l.1F'(
CycLe OF ElO.!STINGo ",'CROCOMPUTE~ SYSTEMS BAseD ON
MIC~Om:>cESSORl; WHICH EITHER. Do.rT HAVE /lNJLTIf'l.ICATION
ANI) DIVISION INSTRUCTIONS,OR PE:RFORMTHESE:
OPERATIONS REUITIVELY SWWLY ... "

9. "The Design and Application of a High-Speed Multiply/
Divide Board for the STD Bus," Michael Linse, Gary Oliver,
Kirk Bailey, and Michael Alan Baxter, Monolithic Memories
Application Note AN"115.
10. "Minimum Chip-Count Number Cruncher Uses Bipolar
Co-Processor," C. Hastings, E. Gordon, and R. BlaSCO.
Monolithic Memories Conference Proceedings reprint
CP-109.
11. "Medium"5peed Multipliers Trim Cost, Shrink Band-width
in Speed Transmission/' Shlomo'Naser lind Allen Peterson,
Electronic Design, February 1, 1979; pages 58-65.
Monolithic Memories Article Reprint AR-107.
12. ''A Synchronous Multi-Microprocessor SYstem forlmple.
menting.Digital Signal Processing Algorithms," TP. Barnwell,
III and C.J,M. Hodges, SQuthc.on/82 Professional Program
Session Record, Session 21 reprint, paper 21/4.

ItIIonoIIthIo

W Memories

10-7

8x8 Mu Itipl ierIDivider
SN54174S508
Featu..../Ben.flte·

Ord.rlnglnformation

• Co-pl'OC8llOr for enhancing the arithmetic speed of all
present a-bit mlcroprocaallorl
• Bus-oriented organl.Uon

PART NUMBER

PACKAGE

TEMPERATURE

SN54S508
SN74S508

024
D24

Military
Commercial

• 24-pln pi!Ckage
• ,8/8 or .16/8 division In leas .than 2.2 I'MC
• 8118 munlpllcatlon In leas than .a 1'88C
• 28 different mulUpllcatlon Instructions such as "fractional
multiply and accumulate"
• 13 dHferent divide Inatruc:tlona

Logic Symbol
STATE COUNTER

INSTRUCTION

4

3

• Self-contained and ml~roprogremmable

VDATABUS

GO

SN54174S50a

Description
The SN54n4S508 ('S508) is a bus-organized8x8 Multiplierf
Divider. The device provides both multiplication and division of
2s-complement 8-bit numbers at high speed. There are 28
different multiply options, including: positive and 'negative
multiply, positive and negative accumulation, mUltipli98tion by a
constant, .and both single-length and double-length addition in
conjunction with multiplication. 13 different divide options allow
single-length or double-length division, division of a previouslygenerated result,division by a constant, and continued division
of a remainder or quotient.
The '8508 is a time-sequenced device requiring a single clock. It
loads operands from, and presentS r8$ults to, a bidirectional 8bit
Loading of the operands, reading of thf;lresults, and
sequential control of the device is performed by a 3-bitinstruction field.

v

~8
OVERFLOW

CLOCK

DONE

t

MASTER RESET
OUTPUT ENABLE

I

Pin Configuration.

bus.

The 'S508has the additional feature that operands and r8$ults
can be either integers or fractions; when it deals with fractions,
automatic scaling occurs. Results can berouMed if required,
and ariOverflow output indicates whenever a result is outside
the nOrmally-accepted rll/mber range.
For a simple multiplication of Iwooperands and reading of the
double-length r8$ult, the device takes five clock periods - one
for initialization, .and·fourfor tfNi actual multiplication. A.typical
clock period is 125ns,whlchgives a multiplication time 01500
ns tYPical for 8x8 multiplication, plus 125 Os ildditionallyfor
initialization, or 625 nsin all. More complex multipiications will
take additional clocl( periods for loading the additional oper.:,
ands. A simpie division operation' requires 8 ;". 4 = 12c1ook
periods for a typiealtJmeof 1.5!'5 (18 bitsl8 bits), also plus
125 ns for initialization,or 1.625 '!'5 iri all. .

SN54n4S508

7Mii'

8A}
B

STATE

.:

COUNTER

.. , .'
..'.
. . '0
,.. ' . .
.
. ' ... '
TVVX: 910-3~~:!=!76
2175 Mission College Blvd. Siinta Clara, CA 95054-1592 Tel: (408) 970~9700' TWX: 910-338-2374

10·8

_.morl•• uun.u
,."""lthlo 111111

SN54/74S508
INSTRUCTION
SEQUENCE

OPERATION

Ci.OCK
CYCLES

ARITHMETIC OPERATIONS

0

X1 • Y

5

1 -X1 • Y

5

2 X1 • Y + K z ' Kw

5

3

5

-X1 • Y + Kz,Kw

13

4

5/6

K z ' Kw'X1
0 X·Y
1 -X, Y

5/6

2 X· Y + Kz,Kw

5/6

3

-X, Y + K Z' Kw

5/6

4
5

KwlX
Kz/X

0

X· Y+Z

5/6

5/6

516 6
5/6

6

6
6

6

2

6

3, -X·y + Kz '

7
7

z-8

7
7

4

Z, WIX

15

6

5

ZIX

15

5/6

6

6

0 X'Y+Z,W

8

5/6

6

6

1 -X, Y + Z, W

8

5/6

6

6

2 X'Y+Wsign

8

5/6

6

6

3

5/6

6

5/6
5/6

16

6

6
6

5 Wsign/X
6 (See Note 9 below)

16

6

6

7 La,ad X, Load Z, Load W, Clear Z

3

'READING OPERATIONS

7

ReadZ

.7 Relld Z, W.

1

2

7

7

7, Read Z,W, Z

3

.7

7

7

Read Z,W; Z, W

4

5

7

Round, then Read Z

2

7

.7 Round, then Read Z, W

3

5

CK

Clock pulse input

00

Chip activation input

Intemal-state-counter outputs

OE

Output enable input

MR

Master reset input

OVR

Arithmetic overflow output

DONE

Arithmetic-operation completion output

Description

(continued)

The '8508 device uses standard low-power Schottky technology,
requires a single +5V power supply, and is fully TIL compatible;
Bus inputs require at most 250 p.A input current, and control and
clock inputs require at most 1 mA input current. Bus outputs are
three-state, and are capable of sinking 8 mA at the low logic
level. The '8508 is available in both commerCial-temperature
and military-temperature ranges, in a 600-mil 24-pin dual-in-line
ceramic package,

8

-X·Y +Wsign
6 ·4 WIX

7

Instruction (sequential control) input

6

5/6 6

.7

IZ-IO
A, B, C, D

6

5/6

516 5/6

Bidirectional data bus inputs/outputs

14

X·Y+KZ ·Z-8

5/6

BrBo

14

1 -X, Y + Z

5/6

SUMMARY OF SIGNALS/PINS

NOTES:
" X,Y ar~ input multiplier and multiplicand.
2, XI is the previous contents olthe firstrank olthe X register, (eltherthe old X
or a new X),
3, Fractional or integer arithmetic is specified by having the next-to-the-Iast

a

operand loaded using 5 or 6 instruction respectively. All ro~ beginning
with, "5/f?'~' i",~ffect repre~nt two instructions. 5 does fractional arjthmetiq .•\,
and 6 does integer arithmetic.
4.
Wis a doubie-precision number,. Z is the mostsignific~nthalf.Z, W
represents addend upon input, and product (or accumulated sum) 'after
multiplication.
' .
,.

t,

5. K z , Kw represents previous accumulator contents. Kz is the most':'signiflcant half.
6, Wsign isa s,ingle-Iength sIgned number, with sign extension.
7, Maximum ,clock cycle =167 ns f!lr al6-MHz clock" ,
'
8, If n Instruction.codes are shown at the left un----<~--+
TEST

11200

Figure 7.

IIIItinoIIthIG

m

Memories·'

10·43

54/745556
Recommended Bypass Capacitors
The s~itching currents when the outputs change can be fairly
high, and bypass capacitors are recommended to adequately
decouple the VCC and GND connectiol'ls.
For example, on the 84-terminal LCC package, pins 21 and 22
are VCC2 supplies and should be decoupled with pin 33, a GND
input, using a 0.1 p.f monolithic ceramic disk capacitor. The

capaCitor must have good high-frequency characteristics. Also
pins 64 and 65, VCC1 and VCC2, should be decoupled with pin
74, a GND input, with a similar capacitor arrangement.
For the 88-pin-grid-array package pins 21 and 22 are VCC2
supplies and should be decoupled with pin 35, the GND pin. Pins
66 and 67, VCC1 and VCC2, shouJd be decoupled with pin
theGND pin.

n,

Decoupling Capecltors Shown with the 84-Terminal LCC Package

r-------------,GND
0.1 "F

VCC2

VCC1

0.1 "F

GND

Typical Supply Current Over Temperature Range
54S556

74S556
1000

1000

rVCC=UOV

r
400
-20

o

20

40

TEMPERATURE (" C)

10-44

II

Vcc =5.2SV

80

80

400
-80

-40

o

40

TEMPERATURE (OC)

80

120

54/745556
88 Pin-Grid-Array
Pin Locations
Bottom View

@@@@@@@@@@@®®
®®@@@@@@@@@@@
CD@)
@@
00
@@
IDENTIFIER
CD CD
@ @
FOR PIN 1 ~
1112
33
Q)(V
34
@@
CD@.
1
@@
88
@@
@@
55
®@
78 77
56
@ @
@@
®®
@@
@@
@@@@@@@@@@®®®
@@®®@@®®@@@®®
Pin-Guide For Pin Grid Array

*

Pin No.

Pin Name

1

X9

Pin Name

Pin No.

Pin Name

45

825

67

23

N/C*

2

Xl0

24

Y8

VCC2t

46

824

68

3

Xll

25

N/C*

Y9

47

823

69

4

X12

87

26

Yl0

48

822

70

5

X13

86

27

Yll

49

821

71

85

6
7

X14

28

Y12

50

820

72

84

X15

29

Y13

51

819

73

83

8

XM

30

Y14

52

818

74

82

9

GX

31

Y15

53

817

75

81

Pin No.

Pin Name

Pin No.

10

R8

32

YM

54

816

76

80

11

RU

33

GY

55

GND

77

GND

12

GND

34

N/C*

56

TRil (OEl)

78

N/C*

13

YO

35

GND

57

Gl

79

GND

14

Yl

36

TRIM (OEM)

58

815

80

XO

15

Y2

37

GM

59

814

81

Xl

16

Y3

38

831

60

813

82

X2

17

Y4

39

831

61

812

83

X3

18

Y5

40

830

62

811

84

X4

19

Y6

41

829

63

810

85

X5

20

Y7

42

828

64

89

86

X6

21

VCC2t

43

827

65

88

87

X7

22

VCC2t

44

826

66

VCC1tt

88

X8

Not connected .. t VCC2 = Logic VCC.

tt

VCC1 = Output buffer VCC.

Monolithic

W Memories

10-45

54/745556
Rounding

0.05 to the number and truncating the LSB:
39.28 + 0.05 =39.33 - 39.3

Multiplication of two n-bit operands results in a 2n-bit productt.
Therefore, in a pure n-bit system it is necessary to convert the
double-length product into a Single-length product. Thiscan be
accomplished by truncating or rounding. The following examples illustrate the difference between the two conversion techniques in decimal arithmetic:
39.2-39
39.6 - 39

The situation in binary arithmetic is quite similar, but two cases
need to be considered; signed and unsigned data representation. In signed multiplication, the two MSBs of the result are
identical, except when both operands are -1 ; therefore, the best
Single-length product is shifted one position to the right with
respect to the unsigned multiplications. Figure 8 illustrates these
two cases for the, 16x16 multiplier. In the signed case, adding
one-half of the S15 weight is accomplished by adding 1 in bit
position 14, and in the unsigned case by adding 1 in bit position
15. Therefore, the '5556 multiplier has two rounding inputs. RS
and RU. Thus, to get a rounded Single-length result, the appropriate R input is tied to Vee (logiC High) and the other R input is
grounded. If a double-length result is desired, both R inputs are
grounded. '

Truncating

39.2 + 0.5 = 39.7 - 39
39.6 + 0.5 = 40.1 - 40

Rounding

Obviously, rounding maintains more precision than truncating,
but it may take one more step to implement. The additional step
involves adding one-half of the weight of the Single-length L5B
to the M5B of the discarded part; e.g., in decimal arithmetic
rounding 39.28 to one decimal point is accomplished by adding
tin general multiplication of an M-bit operand by an N-bit operand results in an

(a) SIGNED MULTIPLY (OMIT S31 as s30 ~ S31

(M + N)-bit product.

=sign of result)

FULL 32·BIT ]
PRODUCT
)(

515:I 514 513 ...

o •

+ o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

I

o:

:

515:

S:io •

I

50

~",:~..uJ

WEIGHT OF THE
DISCARDED PART
BEST 16-BIT PRODUCT

(b) UNSIGNED MULTIPLY
BINARY POINT

• X15 X14 X13 X12 X11 )(10 X9

X8

X7

Xa

X5

X4

X3

X2

X1

)(

·~5~~3~2~1~0~

~

~

~

~

~

~

~

~

+

·000000000000000

• 531 S30 S29 S28 S27 S26 S25 S24 S23 522 S21 S20 S19 S18 S17

FULL 32·BIT ]
PRODUCT

514 513 ...

',oo.:". ..

...

50

J

WEIGHT OF THE
DISCARDED PART

BEST 16-BIT PRODUCT
NOTES:

(a) In signed (twos-complement) notation, the MSBofeach operand isthe sign bit, and the binary point is to the right of the MSB. The resulting product hasa redundant
ttirough S15' and rounding'is pe,rformed by adding "1"
sign bit and the binary point is to the right of the second MSB of the product. The best 16-bitproduct is from
to bit position S14'

Sso

(b) In unsigned notation the best 16-bit product is the most significant half of the product and is corrected by adding "1· to bit position S15'

FIgure 8. RoundIng the Result of Binary Fractional Multiplication.

10·46

MonoI~/o m.e~orIe$

54/745556
Using the '5556 in a Pipelined
Positive-Edge Triggered Clock System

latched results) and new data is presented to the input latches,
which are opened. This is shown by the relation between GX, GY
and GL, GM in Figure 9. The set-up time tS3 is shown as one
value but strictly speaking, it is split as tS3L and tS3M for the
least significant and most significant half 01 the productrespectively. The value of tS3L is less than tS3M' for applications
requiring the least significant bits of the result as fast as
possible.

The 'SS56 has internal latches which can be used affectively in
systems where things happen on positive-going clock edges.
This application is an extension of the gated multiply mode
shown in Figure 1, in which a 32-bit product can be latched every
tS3 nsec in the 'S556.
!

il

If the signals GX, GY, GM and GL can be derived from the
system clock then the latches can almost have the same effect as
having a register. The basic philosophy behind the recommended timing is that the. input latches are closed when the
output latches are open; the outputs are then closed (and have

One note of caution is that a design must always meet the set-up
and hold times for Xi, Ri with respect to GX and for Yi with
respect to GY.
The result Si is available tD2 after the rising edge of GM and GL.

I

SYS~
ClK

GX,GY
~--------,~--------~~

GloGM
'~"H3 = SETUP, HOLD TIMES OF

GX, GY TO GM,.Gl
X,Y,R
's1,'H1 = SETUP, HOLD TIMES OF
Xi> RI TO GX AND YI TO GY

s
f+---~*- '02

=PROPAGATION DELAY OF
GM,GlTO Sl

Figure 9.

10-47

54/745556
Totally Paralle~ 32x32 Multiplier

A twos-complement 32x32 multiplication can be performed
within 220 nsecusing 4 '8556s;,20 '5381s, and 7 '8182s. This
32x32 multiply operation involves adding up four partial products asshown in Figure 10. These four partial products are
generated in four multiplier'S; tlJe outputs are XA*VA, XA*VB,
XS*VA, Xa*VB, where X31-16 = XB, X15-0 = XA, V31-16 = VB,
V15-D= VA.

x = XBXA -

32 BITS
Y=YBYA-32BITS

U= UNSIGNED
S = SIGNED

BITS

BITS

BITS

BITS

63-48

47-32

31-16

15~

The implementation of this twos-complement32x32 multiplier is
shown in Figure 11. The outputs of the 16x16 multipliers are
connected to two levels of adders to give a 64-bit product. The'
first level of adders is needed to add the two central partial
products of Figure 10, XA*VB and XB*VA. Notice the technique
which is used to generate the "sign extension", or the mostSignificant sum bit ofthe first level of adders. The '8556 provides,
as a direct output, the complement of the most-significant product bit; having this signal immediately speeds up the signextension computation, and reduces the external parts count.

64-BIT 2'S COMPLEMENT OUTPUT

Figure 10. Partial Products for a 32x32 Multiplication

INPUTS
V

Y31-16

X31·16

YM

vcc

Y15-0

vcc

Y31-16

'5556
S15-0

X15-0

Y15-0

X15-0

X15-0

X15-0

X15-0

U

YM

XM

YM

XM
'S556

S31-1&.

X31·16

XM

YM

XM

'5556

'5556

So

"::"

D

"::"

S31-17, S1&. S15-0

"::"

'S381 + 'S162*
F14-0

SIGN
EXT

Cln ~------'

'S381 + 'S162*

S47-32

S31-16

OUTPUTS

*

THESE ARE ADDER BLOCKS USING THE 'S381 , A4-BIT ALU FUNCTION GENERATOR, TO PERFORM A HIGH SPEED ADD
OPERATION. THE'S182IS A LOOK-AHEAD CARRY GENERATOR WHICH REDUCES THE PROPAGATION DELAY. ALL THE
ABOVE PART$ ARE AVAILABLE FROM MONOLITHIC MEMORIES INCORPORATED.
TOTAL MULTIPLY TIME = MULTIPLIER DELAY + ADDER lEVEL 1 DELAY + ADDER LEVEL 2 DELAY = 90 + 65 + 65 = 220 nsec

Figure 11. Implementation of the 32x32 Multiplier

10-48

54/745556

,I
I

~i

.,

I

For example, the inputs to the adder in the most significant
position are the S31 outputs from the two central multipliers.
The sign extension of the addition of XA*YB and XB*YA is
defined as
SIGN EXT = A.B. + A.C. + B.C., where
A is the most-significant bit of the term XA*YB;
B is the most-significant bit of the term XB*YA; and
C is the carry-in to the mostcsignificant bits of XA *YB arid
XB*YA, in the adder.
The sign extension can be computed as the negation of the
carry-outterm 9fthree terms, A, arid C. This term corresponds
to the negative of the carry-out of. the bit position just one place
to the right of the most-significant bit position of the first lev.elof
adders. The negative of the carry-out can" he generated by
presenting a carry-out and a binary "one" to the most significant
bit of the adder. The generated sum bit then corresponds to the
negation olthe carry-out olthe previous stage, which is the sign

extension required to be added to the 16 most-Significant bits of
the XB*YB partial productterm.
.
The second level of adders, which performs a 48-bit add function, is fairly straightforward. These adders can be implemented
using '5381 four-bit ALUs and.'S182 carry~bypasses ("carrylookahead generators") which are available from Monolithic
Memories Inc. and from other vendors.
Other configurations such as 48x48 and 64x64 multipliers can
be designed using the same metl"!odology, r1,

B.

References
1. "Fallt 64x64 Multiplication uBing16x16 Flow-through Multi'p1ier and Wallace Trees," Marvin Fox, Chuck Hastings, and
Suneel Rajpal, Monolithic Memories System Design Handbook, pages 4-77 to 4-84.
.

Die Configuration

Ole Size = 183x243 mll2

10·49

8x8 High Speed Schottky Multipliers
SN54/74S557 SN54/74S558
Features/Benefits
• Industry-standard 8x8 multiplier
• Multiplies two 8-bil numbers; gives 16-bit result
• Caseadable; 56x56 fully-parallel multiplication uses only 34
multipliers for the most-significant half of the product

Ordering Information
PART NUMBER

PACKAGE

54S557, 54S558

J, (44), (L)

748557, 748558

N,J,

Military
Commarcial

Logic Symbol
Gt/Ru
Rt/R

• Full 8x8 multiply in 60ns worst case

TEMPERATURE

I

S

x 18
• Three-state outputs for bus operation

r-.

8x8
MULTIPLIER

• Transparent 16-bit latch in 'S557

16

IY 18

• Plug-in compatible with original Monolithic Memories' 67558

Description
The 'S557/'S558 is a high-speed 8x8 combinatorial multiplier
which can multiply two eight-bit unsigned or Signed twoscomplement numbers and generate the sixteen-bit unsigned
or Signed product. Each input operand X and Y has an
associated Mode control line. XM andYM resoectivelv,When a
Mode control line is at a Low logic level. the operand is treated
as an unsigned eight-bit number; whereas, if the Mode control is
at a High logic level. the operand is treated as an eight-bit signed
twos-complement number. Additional inputs. RS and RU, (R, in
the'S557) allow the addition of a bit into the multiplier array at
the appropriate bit positions for rounding signed or unsigned
fractional numbers.

ry

OE

Pin Configuration
r-----",.._--,_
XM

So
51
52
53
54

54n4S558

The 'S557 internally develops proper. rounding for either
signed or unsigned numbers by combining the rounding input
RwithXM,YM,XM,andYM as follows:

54n4S557(tl

GND

R U = XM •YM • R = UnSigned rounding input to 27 adder.
RS = (XM + YM) R = Signed rounding input to 2 6 adder.
Since the '8558 has no latches. it does not require the use of pin 11
for the latch enable input G, so RS and RU are brought out
separately.

Yo

59

Y,

5'0

Y2

The most-significant product bit is available in both true and
complemented form to assist in expansion to larger signed
multipliers. The product outputs are three-state, controlled by
an assertive-low Output Enable which allows several multipliers to be connected to a parallel bus or be used in a pipelined system. The device uses a single +5V power supply and is
packaged in a standard 40-pin DIP.
tFor 54/745557 Pin 9 is R and Pin 11 is G.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970~9700 TWX: 910-338-2374

10·50

MonolIthIc I!l!n
MemorIes LnJlW

SN54/74S557

I

SN54/74S558

:1

:1

!

Logic Diagram
8-BIT X INPUT

X7 - - - - - - XO

Yo

I
I

8 x 8
MULTIPLIER
ARRAY

I
I

8-BIT

Y
INPUT

I
I
I

ROUND
DECODE

Y7

Rut

16
LATCH
ENABLE

(Gtl----!

TRAN5PARENT : _ ' 5 5 5 7 ONLY
~ ____ ~!C~!,.!I____ ~
16

515 5 1 5 - - - - - - 5 0
16-BIT PRODUCT

tFor 54fl4S557 Pin 9 is R Bnd Pin 11 is G.

Die Configurations
'S557
654321

'S558
37 36

65432140

Y4 Y5 YB Y7 YM
16 17 18 19 20

Die Size: 144x130 mll2

Die Size: 144x130 mll2

39363736

OE SiS 515 514 513
21 22 23 24 25

5N54/745557 5N54/745558
Absolute Maximum Ratings
Supply voltage vee ....................................•....................•..............•......•............. 7.0 V
Input voltage ...........................................•..................................•..................•. 7.0 V
Off-state output voltage ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .. 5.5 V
Storage temperature ................................•...•.............................................. -65° to +l50o e

Operating Conditions
PARAMETER

SYMBOL

DEVICE

MILITARY
MIN TYP MAX

COMMERCIAL
UNITS
MIN TYP MAX

4.75

Vee
TA
tsu

Supply voltage

all

4.5

Operating free-air temperature

all

-55

Xi, Yi to G set

'S557

50

th

Xi, Yi to G hold time
Latch enable pulse width

'S557

0
20

tw

'S557

5

5.5

5

125* 0

5.25

V

75

·e
ns

40
0
15

ns
ns

* Case temperature
Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

TEST CONDITIONS

MIN TYPt MAX

UNIT

VIL

Low-level input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

II

-1.5

V

IlL

Low-level input current

Vee = MAX

VI

= 0.5V

-1

mA

IIH

High-level input current

Vee = MAX

VI

= 2.4V

100

Il A

II

Maximum input current

Vee = MAX

VI

= 5.5V

1

mA

VOL

Low-level output voltage

Vee = MIN

10L = SmA

VOH

High-level output voltage

Vee = MIN

10H = -2mA

Off~state

Vee = MAX

O.S
2

V

= -lSmA

0.5
2.4

output current

-100

Vo = 2.4V

10lH
lOS

Output short-circuit current*

Vee = MAX

leC

Supply current.

Vee - MAX

Vo = OV

'.

-20

'.

V
V

Vo = 0.5V

lOlL

V

200

,.A

lOQ

,.A

-90

.mA

280

mA

* Not more than ooe output should bE! shorted "t a·time and duration of the short-circuit sho.uld not.exceed one second.
t

Typicals at 5.0VVCC and ;IS·CTA ·

5wit~hing
,

SYMBDL

Characteristics,

Over Operating CondHions

,

PARAMETER

,

DEVICE

TEST
CONDITIONS

.' MILITARY
COMMERCIAL
MIN TYPt MAX. MIN
MAX

TYPt

UNIT

tpOl

Xi'Yi IOS7-o

,All

40

60

40

50

ns

tp02

Xi, Yi tOSj5-8

All

45

70

45

60

ns

tPD3

Xi,Yi to$15

All

50

75

50

65

ns

20 .'

40

20

35

ns

20

40

20

30

ns

15

40

15

30

ns

'5557

tPD4

GIoSi

tpxz

OEtoS,

All

tpzx

OEtoS,

All

10-52

I6onoIIthIc

eL

= 30pF

RL = 5600

:

see test figures

IUD II/Iemorles

SN54/74S557 SN54/74S558
Timing Waveforms
Setup and Hold Times ('S557)

Test Waveforms

IHI§~~-.~'
i
i

TEST

Vx

OUTPUT WAVEFORM -MEAa LEVEL

AlllpD

5.0V

VOH
*1.5V
VOL

-.....----"------'---'----~:=~~:

lor

loi '

I pHZ II'LZ

VOH
O.SV

tpxz

I

O.OV

S.OV

lor

lor

O.SV
VOL

l&::::'"
O.OV

IPlH IpZL

2.8V~VOH

O.OV

O.OV,

1.5V

IPZX
S.OV

,

'

VOL

NOTE: lithe rising edge ofG occursbefore:(tSUMIN-tw MIN ) from the inputs
changing, then the applicable propagation delays are tpD, tpD2 and tpD3,
(and not tpD4)' In this case the time at which the results arrive althe outputs
depends on when the inputs change instead of when the rising edge of
G occurs.

Propagation, Delay

Test Load

.~.

INPUTS,

~-

3V
- , - ' - - --,- -,, - -,-: -,-,' -.-,- - - , - 1
O~SV

tpD1, 2, 3 "

V. (I.e tllble above)
TEST
POINT*

"

IN916 OR IN3064
RL
55O!l

112O!!

*

The ''TEST POINr' is driven by the outpul under test,
~nd

Definition: of Timing

Latch-Enable Pulse Width ('S557)

t, , J---~:
,.... ----~~~
, , f 'j'
,

,

3V

LOW-HIGH-LOW'

HIGH-LOW-HIGH
'---PULSE

3V

---

observed t;Jy i.nstrumentatlon.

----~V

-

WAVEFORM

1B (ft

D~agram

INPUTS

OUTPUTS

DON'T CARE;
CHANGE PERMITTED ,

CHANGING;
STATE UNKNOWN

NOT
APPLICABLE

CENTER LINE IS
HIGH IMPEOANCESTATE

MUST BE STEADY

WILL BE STEADY

10-53

SN54/74S557 SN54/74S558

SUMMARY OF SIGNALS/PINS

XrXo
Y7-Yo

ROUNDING INPUTS
'SS57

..

INPUTS

Multiplicand 8-bit data inputs
XM

Multiplier 8-bit data inputs

YM

26

L

L

H

YES

NO

H

H

NO

YES

L

H

NO

YES

H

H

NO

YES

L

NO

NO

Mode control inputs for each data word; LOW for
unsigned data 'and HIGH for twos-complement
data

H

S15-50

Product 16-bit output

H

Inverted MSB for expansion

X

X

RS·RU

R

L

XM. YM

S15

ADDS.
27

Rounding inputs for signed and unsigned data.
respectively (,S558 only)

G

Transparent latch enable (,8557 only)

DE

Three-state enable for S15-S0 and S15 outputs

R

Rounding input for signed or unsigned data;
combined internally with XM. YM ('S557 only)

'S558
INPUTS

ADDS

USUALLY USED WITH

RU

RS

27

L

L

NO

NO

X

X

L

H

NO

YES

Ht

H

L

YES

NO

L

Ht
L

H

H

YES

YES

*

*

26

XM

YM.

tin mixed mode, one of these could be Low but not both.
*Usually a nonsense operation. See applications section, of data sheet.

74S557 FUNCTION TABLE
PRODUCT
LATCH
RESULT CONTENTS
INPUTS
OUTPUTS
(INTERNAL
FROM
ARRAY
TO PART)
.
OE G

T,

Q,

S,

FUNCTION

MODE CONTROL INPUTS

L
L

L
L

X
X

L
H

L
H

Latched

L
L

H
H

L
H

(L)*
(H)*

L
H

Transparent

H
H

L
L

H

H

OPERATING
MODE
UnSigned

X

(L)
(H)

Z
Z

Hi-Z; Latched
Data not
Changed

Mixed

X

(X)*

Z

Hi-Z

Signed

X

*Iidentical with product result paaaing through latch.

10-54

INPUT; DATA
X7-X O

Y7-Y O

MODE
CONTROL
INPUTS
XM.
YM

Unsigned

Unsigned

L

L

Unsigned

Twos-Comp.

L

H

Twos-Comp.

Unsigned

H

L

H

H

Twos-Comp. Twos-Comp.

SN54/74S557 SN54/74S558
Functional Description

Rounding

The '5557 and '5558 multipliers are 8x8 full-adder Gray ar~YJ!
capable of multiplying numbers in unsigned, signed, twoscomplement, or mixed notation. Each 8-bit input operand X and'
Y has associated with it a mode control which determines
whether the array treats this number as Signed or unsigned. If
the mode control is at High logic lev~l, then the operand is
treated asa tWos-complemel)t.nurpberwith the most-significant
bit having a negative weight; whereas, if the mode control is at a
Low logic level, then the operand is treated as an unsigned
number.

Multiplication of two n-blt operands results in a 2n-blt productt. Therefore, in an n-bit system it is necessary to Convert the
double-length product into a single-iength prOduct. This can
be accomplished by truncating or rounding. The follOWing examples illustrate the difference between the two conversion
techniques in decimal arithmetic:

The multiplier provides all 16 product bits generated by the
multiplication. For expansion during signed or mixed multiplication the most-significant product bit is available in both true
and complemented form. This allows an adder to be uSed as a
subtractor in many applications and eliminates the need for
certain 551 circuits.
Two additi~>nal inputs to the array, R5 and RU' allow the addition of a bil at Ihe appropriate bit position SO as to provide
rounding 10 the best signed or unsigned· fractional eight-bit
result. These inputs can also be used for rounding in larger
multipliers. In the '5557, these two inputs are generated internally from the mode controls and a single R input.
The product outputs of the multiplier are controlled by an
assertive-low Output Enable control. When thi,s control is .. at a
Low logic level the multiplier outputs are active, while if the
control is at a High logic level then the outputs are placed in a
high-impedance state. This three-state capability . allows
several multipliers to drive a common' bus, and also allows
pipelining of multipiication for higher-speed systems.
tin general: multiplication of an M-tJit operand by an

N-tJ~ operand,esults in

"(~'~~~
Y7 0 Y6

Y5

Y4

Y3

515 514 0 513

512

$11

510

0

0

0
510

X

.
(a) 51GNED
MULTIPLICATION

+

* OMITS 15
SINCE S14 = S15

.

0 0

*514 0513 512

...

if.OMITS15
SINCE 514 = 515

(b) UN51GNED
MULTIPLICATION

X5

X4

.

511

X3

X2

39.2-'39} T
t'
39.6 -39
runca Ing .
39.2 + 0.5 = 39.7_39} Rounding
.39.6 + 0.5 = 40.1-'40
ObviouJ!ly, rounding maintains more precision than truncating,
but it may take one more 'step to implement. The additional
step involves adding one-half of the weight of the single-length
L5B to the M5B of the discarded part; e.g., In decimal arithmetic rounding 39.28 to one decimal point is accomplished !>y
adding 0.05 to the number and truncating the L5B:
.39.28 + 0.05 = 39.33-'39.3.
The situation in binary arithmetic is quite similar, but two cases
need to be considered: Signed and unsigned data representation. In signed multiplication, the two 1I(15Bs of the result are
identical, except, when both operands are -1; therefore,the
best single-length product is shifted one pOSition to the right
with. respect to the unsigned multiplications. Figure 1 illustrates these two cases for the 8x8 multiplier. In the signed case,
adding one-half of the 57 weight is accomplished by adding 1
in bit position 6, arid in the unsigned ease 1 is added to bit position 7. Theretore, the '5558 multiplier has two rounding inputs,
R s and Ru' Thus, to get a rounded Single-length result, the
appropriate R input is tied to V cc (logiC High) and the other
R input is grounded. If a double-length result is desired, both
R inputs are grounded for the '8558, and the single R input
is grounded for the '5557.
an (M + N)-tJit·.P~uct.

I

Xl

Xo I

Y2

Yl

59

5a

YOI
57 56

55

54

53

52

51

50

0

0:

0: I 1

0

0

0

0

0

0

59

5a

56

$5

54

53

52

51

50 . . - FULL l8-BIT PRODUCT

0

0

0 ..-.ADD 1/2 THE M5B

57 I

I

o

X7

X6

X5

X4

X3

X2

Xl

Xo

o

Y7

Y6

Y5

Y4

Y3

Y2

Yl

YO I.

+

.515 514 513 512

511

510
,0

59

5a 157

0

'0"

511

5,u

S9

o I
S~ I

..

'

0

0"

0:

.

0515 514 513 512

1/2 THE M5B
WEIGHT OF THE
DI5CARDED PART

I
I

X

0 0

~ADD

"I

BEST 8-B1T PRODUCT

{

~..uu. lMIT PRODUCT

1

O· '0

0

O·

WEIGHT OF THE
DISCARDED PART

BEST B-BlT PRODUCT
NOTES:
(a) In signOd (twos-complement) ·notatlon. the MSB of each oPerand is the Sign bit, and the bina,ypoint is 10 the right of the MSB. The resulting product has a redundant
sign bit and the binary point is to the right of the second MSB of the product. The bast eight-blt product is from St4 through 57' and rounding Is performed by adding
"1" to bit positIon S6'
' .
(b) In unsigned notation the best a·blt product is the most significant half of the product and is corrected by adding,:'1" to bit position S1'

Figure 1. Rounding the ResuH of Binary" Fractional MaHij)Uc8tion

10-55

SN54114S557 SN54/74S558
Signed Expansion

adder is the sign extension b=it=.,...-=-_-=
Sign ext = AB + BC + CA = AS + BC + CA,

The mQllt-significant product bit has both true and complementoutputs available. When ~uilding larger signed, multipliers, Ihe partial products (except at the lower stages) are
signed numbers~ These unsigned and sighed partial products
must be addedtQgether to give the correct signed product.
Having both the true and complemented form .of the mostsignificant product bit available assists in this addition. For
example, say that two signed partial, products must be added
and MSI adders are used; we then have the situation of adding
together the carry from the previous adder stage plus the addition of the two negative most-significant partial-product bits.
The result of adding these variables must be a positive sum
and a negative carry (borrow). The equations for this are:
S=AEBBEBC
COUT" AS + BC+ CA
where C' is the carry-in and A and B are the sign bits of the two
partial products.
Now an adder produces the equations:
S= A Ell B Ql C
COUT =' AB + BC + CA
Examinmg these equations, it can be seen that, if the inversions
of A and B are used, then the, most significant sum bit of the
Vee

Y15-8

vcc

The 16-bit X operand is broken into two S-bit operands (X7-XO
and X15-XS), as is the Y operand. Since the situation Is that of a
cross-product, four partial products are generated as' follows:

A = XL * YL
B = XL * YH
C=XH*Y L
D=XH*YH
where the subscript L stands for bits 7-0, ("low Or least-significant half) .. and the subscript H stands for bits,15-8.
Expanded twos-complement multiplication requires a sign
extension of the Band C partial products. Thus, B15 and C15
need to be extended eight positions to the left (to align with
D15)' In this approach t~o more adders are required. But the
complement oflhe MSB (S15) on the '5557/S can be used to save
these two adders. Figure 2 shows the implementation of 16x16
signed twos-complement multiplication in this manner.

INPUTS
X15-8
Vcc

Y7-0

YM
'S557/8

and the sum remains the same.

16x1 e Twos-Complement
Multiplication

XM

X7-0

Y15-8

YM

XM

X7-0

X15-0
YNi

X1S-0
XM

U

'SSS7/8'

'S557/8

'SS57/8

Y7-0

';'

S15-9, S8

S7-0

';'

S7-0
OUTPUTS
• THESE ARE ADDER BLOCKS USING THE '5381, A4-BIT ALU FUNCTION GENERATOR, TO PERFORM A HIGH-SPEED ADD
OPERATION. THE 'S182IS ALOOKAHEAD'CARRY GENERATOR AND REDUCES THE PROPAGATION DELAY. ALL OFTHE
ABOVE PARTS ARE AVAILABLE FROM MONOLITHIC MEMORIES INCORPORATED.
TOTAL MULTIPLY nME =MULnPLIER DELAY + ADDER LEVEL 1 DELAY + ADDER LEVEL 2 DELAY =60+44+64 " 168 nlac
Figure 2_ 16x16 Twos-COmplement Signed Multiplication

1815
1015 014 013 012 011 010 09 oall 07
IC15
~31 S30 529 628 S27 526 525 524S23

B14
06
C14
S22

B13
05
C13
S21

812
04
C1:Z
520

B11
03
cn
519

810
02
C10
S,18

Bg
01
C9
S17

X15 "X14 X13 X12
Y1S Y14 Y13 Y12
sail B7 B6 85 B4
001lA15 A14 A13 A12
c811 c 7 C6 C5 C4
S16 S15 S14 S13 512

x11
Y11
83
An
C3
S11

X10
Y10
82
A10
C2
S10

Xg X8 X7
Yg Y8 V7
S1 sol
A9 Aall A7
C1 col
S9 Sa 57

X6 Xs X4 X3 X2
V6 Vs V4 ,V3 V2

X1
V1

Xo
Vo

A6 A5 A4 A3 A2 A1

Aol

S6 S5 S4 S3 S2 51

So

ROUNDED' RESULT
Figure 3. Unsigned ExpanSlons()f the 8x8 Multiplier to 16x16 Multiplication

SN54/74S557 SN54/74S558
Applications:
How to Design Superspeed Cray
Multipliers with '5585
by Chuck

I've left off the remarks this time, but they're just like the
remarks in the decimal example, at least in principle. Just in
case you doubt this answer, I'll convert it back:

Haslings

Multiplication, as most of us think of it, is performed by repeated
addition and shifting. When we multiply using pencil and paper,
according to the familiar elementary-school method, we first
write down the multiplicand, and then write down the multiplier
immediately under it and underline the multiplier. Then we take
the least-significant digit of the multiplier, multiply tha:! digit by
the entire multiplicand, and record the answer in the top row of
our workspace, underneath the line. then we repeat, using now
the second-least-significant multiplier digit, and record that
answer below the first one, pushed one digit position (that is,
"shifted") to the left. This process continues until we run out of
multiplier digits (or out of patience), at which point we add up
the constants of the whole diamond-shaped workspace and
record at the bottom an answer which consists of either
m + n - 1 digits or m + n digits, where there are m digits in the
multiplier and n digits in the multiplicand. An example, voila':

1
1
0,
0,
0,
0,
1
0,
1
0,
0,

64)
128)
256)
(12)
( 2048)

(16364)
(32768)

13375

Figure 6. Binary-Io-Decimal Conversion

125 (multiplicand)
x10,7 (multiplier)
875 (7 x 125)
0,00 (0, x 125, Shifted left one digit position)
(1 x 125, shifted left two digit positions)
125
13375 (sum of the above)

Figure 4. Decimal' Multiplication
The deCimal number system has no monopoly on truth our ancestors simply happened to have ten fingers at the
time when someone came up with the idea of counting. Binary
numbers, as you know, are more copacetic than are decimal
numbers with digital-logic elements, which like to settle
comfortably into one voltage state ("High) or another ("Low"),
rather than into one often different states. So we can repeat the
above. example using binary numbers, right? .First, we convert
our multiplicand and multiplier to binary:
12510 = 0,111110,12
10,710, = 0,110,10,11 2
The subscripts 10, and 2 refer to the "base" or "radix" of the
number system, 10, for decimal and 2 for binary. (Remember
your New Math?) For sneaky reasons to be revealed soon, I've
used 8-bit Qinary numbers, which is one bif more than
necessary for my example, and added a leading zero. So, we
multiply:

=

12510,
0,111110,12
x0,110,10,112 = 10,710
0,111110,1
0,111110,1
0,0,000000,
0,111110,1
0,0000000
0,111110,1
0,111110,1
0,0,000000
00110,10000111111

1

1
2
4
8
16
32
0,
0,
0,
0,
10,24
0,
4096
8192
0,
0,

=1337510,

Figure 5. Binary MultiplicatIon

Now look carefully at the diamond-shaped array of numbers in
the workspace in Figure 5. Each row is either the multiplicand
0, 11111 0, 1, or else all zeroes. The 0, 11111 0, 1 rows correspond
to "1" digits in the multiplier, and the all-zero rows to "0" digits in
the multiplier. Life does get simpler in some ways when we
switch to binary numbers: "multiplying a multiplier digit by the
multiplicand" now means just gating a copy of the multiplicand
into that position if the digit is "1," and not doing so if the digIt is
"0."
Seymour Cray, the master computer deSigner from Chippewa
Falls, Wisconsin, whose career has spanned fhree companies
(Univac, Control Data, and now Cray Research)' and many
inventions, first observed some time in the late 1950s that
computers also could actually multiply this way, if one merely
provided enough components. This last qualifying remark; in
those days when even transistors, let alone integrated Circuits,
in computers were still a novelty was by no means a trivial one!
To prove his point (and satisfy a government contract), Cray
designed, and c9ntrol Data built, a 48x48 multiplier which
operated in one microsecond, about 1960. This multiplier was
part of a special-purpose array processor for a classified
application, and was so big that a GDC 1604 (then considered a
large-scale processor) Served as its input/output controller. In
principle, such· a multiplier at that time would have haa to
consist of 48 48-bit full adders or "mills," each of which received
one input 48-bit number from the outputs of the mill immediately
aboVe it in the array, and the other 48-bit number from a gate
which either allowed the multiplicand to pass through, or else
supplied an all·zero 48-bit number. Actually, these mills have to
be somewhat longer than 48 bits. Anyway, that is at least 2304
full adders, and in 1960 a full-adder circuit normally occupied
one small pliJg"ih circuit card.
A later version of this multiplier, in the CDC 7600 supercomputer, could produce one 48x48 product out every 275
nanoseconds on" a pipelined basis. The pipelining was
asynchronous, and the entirll hUmungo\ls array of adders and
gating logic could have up to three different products rippling
down it at a given instant!

10-57

SN54/74S557 SN54/74S558
Back to the 1980s. Monolithic Memories has for several years
produced an 8x8 Cray multiplier, the 57/67558, as a single 600mil 4O-pin DIP. After we invented this part, AMD secondsourced it, and by now it has become an industry standard. We
now also have faster pin-compatible parts, the 54174S558 and
541748557. Like other West Coast companies 2,000 miles from
Wisconsin and Minnesota where Seymour Cray does his
inventing, Monolithic Memories previously used the tenm
"combinatorial multiplier" instead of "Cray multiplier" for this
type of part. However, "combinatorial multiplier" has nine extra
letters and five extra syllables, and also inadvertently implies
that the technique involves combinatorial logic rather than
arithmetic circuits. Some West Coast designs. including our
67558, use a modified internal array with only half as many fulladder circuits and slightly different interconnections, based on
the two-bit "Booth-multiplication" algorithm (see reference 1),
plus the "Wallace-tree" or "carry-save adder" technique (see
references 2 and 3). Conceptually, however, the entire chip or
system continues to operate as a Cray multiplier.
The'SS8, in particular can be thought of as a static logic network
which fits exactly the binary multiplication example of Figure 5.
(See now why I insisted on using 8-bit binary numbers?) There
are no flipflops or latches whatever in the '558 - it is a ''flowthrough" device. Its AO pins are used up as follows:
Input, Output,
or Voltage

Use of Pins
Multiplier
Multiplicand
Double-Length Product
Complement of MostSignificant Bit of DoubleLength Product
3-State Output Enable
Number-InterpretationMode Control
Rounding Control for Product
Power and Ground

Number
of Pins

I
I

o
o

8
8
16
1

RS Input

RU Input

Effect

L
L

H

L
H
L

H

H

Disable Rounding
Round Unsigned
Round Signed
Nonsense (see below)

Table 3. Rounding Control Input Encoding
Rounding is normally disabled if the entire 16-bit double-length
product' output is to be used. If only an 8-bit subset of this
product Is to be used, this subset can be either bits 15-8 for
unsigned rounding as shown in Figure 7, or bits 14-7 for
signed rounding as shown in Figure 8. In either case, a "1" is
forced into the '558's internal adder network at the bit position
indicated by the arrow; adding.a "1" into the bit pOSition be/ow
the least-significant bit of the final answer has the effect of
rounding, as you can see after a little thought. Obviously,
forcing a "1" into both of these adder positions at the same time
is a nonsense operation for most applications - it adds a "3"
into the middle of the double-length result.

KEEP

DISCARD

01
""'SIGN
BIT
_

FORCE-ADD
A "1" HERE

SIGNIFICANCE:
__
MOST
LEAST

Figure 7. Unsigned Rounding

1

2
I
V

2
_2_
40
_

Table 1. Use of Pins In the '558
The two number-interpretation-mode control pins, one for the
multiplier and one for the multiplicand, allow the format for each
of these two 8-bit input numbers to be chosen independently, as
follows:

FORCE-ADD
A "1" HERE
SIGNIFICANCE:
__
MOST
LEAST

Figure 8. Signed Rounding

Table 2. Mode Control Input Encoding

By now you probably have a fairly good idea of what a 'SS8 is,
and would like a few hints as to how to use it, right? First of all,
there is an occasional application in things like video games for
very fast multiplication, either 8x8 or 16x16, controlled by an 8bit microprocessor, where there would be one 'SS8 per system
(see reference 4). More typically, however, the 'SS8 is a building
block, and several of them are used within one system; in fact,
maybe more than several - "many."ln the usual Silicon-Valley
jargon, we can cascade a number of '558 (8x8) Cray-multiplier
chips to create larger Cray multipliers at the systems level.

The two rounding Control pins allow either integer (rightjustified) or fractional (left-justified) interpretation of the 14-bitsplus-sign double-length product of two 7-bits-plus-sign numbers
for internal rounding of the double-length result to the most
.
accurate 8-bit number. The control encoding is:

For the sake of concreteness, I'll' discuss the case of 56x56
multipliers, which are appropriate in410ating-point units which
deal with "IBM-long-format" numbers which have a 56-bit
mantissa. Any computer which emulates, or uses the same
floating-point format as, any of the following computers can use
such a multiplier:

Conlrollnput

L
H

10·58

Interpretation of &-bIt InPut Number
8-bit unsigned
7-bit plus a sign bit

SN54/74S557 SN54/74S558
IBM 3601370
Amdahl 470
Data General Eclipse
Gould/System Engineering SEL 32
Norsk Data 500 (different format)
There are two basic approaches: serial-parallel, and fully
parallel. The serial-parallel approach uses seven '558s, and
requires seven full multiply-and-add cycles. On the first cycle,
the least-significant eight bits of the multiplier are multiplied by
the entire multiplicand, and this partial product is saved. On the
second cycle, the next-least significant eight bits of the
multiplier are multiplied by the multiplicand, and that product
(shifted eight bit positions to the left) is added into the first
partial product to form the new partial product. And so forth, for
five more cycles. It's almost like our decimal-multiplication
example of Figure 1, except that instead of base-l0 decimal
digits we now have base-256 superdigits.

8-BIT PORTION
OF
MULTIPLIER

64-BIT PARTIAL
PRODUCT

FJgure11. 8x56 Cray Multiplier in "Diamond" Notation

The fuHy-paraliel approach totally applies Cray's usual design
philosophy (sometimes characterized as "big, fast, and simple")
at the systems level. It uses 49 '558s, in seven ranks; the 'i'th rank
performs an operation corresponding to that done during the
'i'th cycle in the serial-parallel implementation. In principle, a
complete mill is used to add the outputs of one rank of '558s to .
those of the rank above it. Or, alternatively, these mills can be
laid out in a "tree" arrangement, such as:
ABC

D

E

F

~ / +""'-.....64-BIT~/+
~ /

~ /

MILLS

'"

~ /

/

+~:-BI~-?+
'".D'T

u~ILL/

96-BIT MILL_+

Figure 9. "Tree" Summing Arrangement of Mills for a 56x56
Cray Multiplier
Each letter stands for one rank of '558s, and each "+" stands for
a mill of the indicated length. More involved "Wallace-tree"
techniques are usually preferable. (See reference 3). If the
least-significant half of the double-length product is never
needed, only 34 'S558s are required. There is one subtlety
which needs to be mentioned. If, conceptually, a '558 looks like
a diamondMULTIPLICAND

56-BIT
MULTIPLICAND

G

As you may discover after a moment's thought, each slanted
double line in Figure 8 calls for addition of the outputs of two
'558s - the eight most significant bits of one, and the eight
least-significant bits of the next one to the left. There must also
be an extra adder (or at least a "half adder") to propagate the
carries from this addition all the way over to theJeft end of the
result. The upshot is that an extra 56-bit mill is needed, in
addition to the '558s. The eight least-significant bits of the leastsignificant '558 do not have to go through this mill, since they do
not get added to anything else.
One final note: building up a large Cray-multiplier configuration
out of '558s requires a lot of full adders, or else a lot of
something else equivalent to them. Monolithic Memories also
makes the 54174S381 (a 4-bit "ALU" or "Arithmetic Logic Unit")
and the 54174S182 (a carry-bypass circuit which works well with
the '381); and two faster ALUs, the 54174F381 and the
54174F382 are in design. These ALUs and bypasses are
excellent building blocks from which to assemble the mills used'
for summation within a rank of '558s, and also the mills used for
tree-summation of the outputs of all ranks. For how to put
together one of these mills using '381s, '382s, and '182s, see
reference 1. For how to use PROMs as Wallace trees, see
reference 3.
Now you can go ahead, design your Cray multiplier out of '558s,
and start multiplying full-length numberS together in a fraction
of a microsecond. Sound like fun?

References
1. "Doing Your OWn Thing in High-Speed Digital Arithmetic,"
Chuck Hastings, Monolithic Memories Conference
Proceedings Reprint CP-l02
2. "Real-Time Processing Gains Ground with Fast Digital
Multiplier," Shlomo Waser and Allen Peterson, Electronics,
September 29, 1977.

MULTIPLIER

LOWER
HALF

3. "Big, Fast and Simple - Algorithms, Architecture, and
Components for High-End Superminis," Ehud "Udi" Gordon
and Chuck Hastings, 1982 Southcon Professional Program,
Orlando, Florida, March 23-25, 1982, paper no. 2113.

DOUBLE-LENGTH PRODUCT

Figure 10. A Single '558 In "Diamond" Notation
then, the 8x56 multiplier for the serial-parallel configuration
(which is also one rank of the fully-parallel configuration,
which has seven such ranks) looks like this:

4. "An 8x8 Multiplier and 8-bit IlP Perform 16x16-bit Multiplication," Shai Mar, EON, November 5, 1979, Monolithic
Memories Article Reprint AR-l09.
NOTE: All of these referel1ces are available as application ,notes from"
Monolithic Memories tne.
'

10':59

Notes

10-60

Monollthio

W Memories

11-1

Table of Contents
8-BIT INTERFACE
Contents for Section 11 ..........•.......•.......... 11-2
8-Bit Interface Selection Guide ......•..•............ 11-3
Pick the Right 8-Bit or 16-Bit
.' Interface Part for the Job ....•..•...•........•..... 11-4
SN54174LS210 B-Bit Buffers ..........•.••........ 11-15
SN54174LS240 B-Bit Buffers .........•............ 11-15
SN54174LS241 B-Bit Buffers ...........•...•...... 11-15
SN54174LS244 B-Bit Buffers ...........•.......•.. 11-15
SN54174S210
B-Bit Buffers .............•..••...• 11-15
SN54/74S24O
B-Bit Buffers ..........••..•....... 11-15
SN54174S241
8-Bit Buffers ....................•. 11-15
SN54174S244
B-Bit Buffers ..................•.•. 11-15
SN54174LS310 B-Bit Buffers with
Schmitt Trigger Inputs ........••.. 11-23
SN54174LS340 B-Bit Bufferswith
Schmitt Trigger Inputs ..........•. 11-23
SN54/74LS341 B-Bit Buffers with
Schmitt Trigger Inputs ....•....... 11-23
SN54/74LS344 8-Bit. Buffers with
Schmitt Trigger Inputs ............ 11-23
SN54174S310
B-Bit Buffers with
Schmitt Trigger Inputs ............ 11-23
. SN54174S34O
8-Bit Buffers with
Schmitt Trigger Inputs ............ 11-23
SN54174S341
B-Bit Buffers with
Schmitt Trigger Inputs ....•....... 11-23
SN54174S344
B-Bit BufferswithSchmitt Trigger Inputs ............ 11-23
SN54174LS245 B-Bit Buffer Transceiver ............ 11-31
SN54174LS645 B-Bit Buffer Transceiver ....•...•... 11-32
SN54174LS645-1 8-Bit Buffer Transceiver .......•... 11-32
SN54174LS273 B-Bit Registers with Master Reset
or Clock Enable ...............•. 11-33

.11-2

Monolithic

SN54174LS377
SN54174S273
SN541748377
SN54174LS373
SN54/74L8374
SN54/748373
SN54/748374
SN54/748383
SN54/74LS533
SN5417 4LS534
SN54174S533
SN54174S534
SN74S531
SN74S532
SN74S535
SN74S536
SN54/74S700/-1
SN54174S700/-1
SN54174S700/-1
SN54/74S700/-1
SN54/74S818

W Memories

B-Bit Registers with Master Reset
or Clock Enable .................
B-Bit Registers with Master Reset
or Clock Enable .................
8-Bit Registers with Master Reset
or Clock Enable .................
B-Bit Latch ........................
B-Bit Register ......................
B-Bit Latch ........................
B-Bit Register ...............•...•..
B-Bit Register with Clock Enable
and Open-Collector Outputs ......
B-Bit Latch with Inverting Outputs
B-Bit Register with
Inverting Outputs ................
B-Bit Latch with Inverting Outputs
B-Bit Register with
Inverting Outputs ............... .
8-Bit Latch with 32 rnA Outputs ..... .
8-Bit Register with 32 rnA Outputs .. .
8-Bit Latch with Inverting,
32 rnA Outputs ................. .
8-Bit Register with Inverting,
32 rnA Outputs ................. .
8-Bit Dynamic-RAM Driver
with Three State Outputs
B-Bit Dynamic-RAM Driver
with Three State Outputs
B-Bit Dynamic-RAM Driver
with Three State Outputs
8-Bit Dynamic-RAM Driver
with Three State Outputs
8-Bit Diagnostic Register .......... .

11-33
11-33
11-33
11-40
11-40
11-40
11-40

...

11-46
11-50

...

11-50
11-50
11-50
11-56
11-56
11-60
11-60
11-64
11-64
11-64
11-64
11-65

8·Bit Interface Selection Guide
8·Bit Interface
PART NUMBER
FUNCTION
COMMERCIAL

SN74LS241
SN74LS244
SN74LS341
SN74LS344

SN54LS241
SN54 LS244
SN54LS341
SN54LS344

SN74LS210
SN74LS240
SN74LS310
SN74LS340

SN54LS210
SN54LS240
SN54LS310
SN54LS340

SN74S241
SN74S244
SN74S341
SN74S344
SN74S731/-1
SN74S734/-1

SN54LS241
SN54S244
SN54S341
SN54S344
SN54S731/-1
SN54S734/-1

SN74S210
SN74S240
SN74S310
SN74S340
SN74S700/-1
SN74:8730/-1

SN54LS210
SN54S240
SN54S310
SN54S340
SN54S700/-1
.SN54S730/-1

SN74LS245
SN74Ls645
SN74LS645-1

SN54LS245
SN54LS645

SN74LS373

SN54LS373

SN74LS533

SN54LS533

SN74S373
SN74S531

SI\I54S373

SN74S533
SN74S535

SN54S533

SN74LS273

SN54l;S273

SN74LS374

SN54LS374

SN74LS377

SN54LS377

SN74LS534

SN54LS534

SN74S273

SN54S273

SN74S374

SN54S374

SN74S377

SN54S377

SN74S383

SN54S383

SN74S532
SN74S534
SN74S536

POWER

POLARITY

FEATURE

Noninvert

-

MILITARY

-

-

LS

Invert

-

Noninvert

S

Invert

Buffer
Transceiver

Noninvert
LS

Schmitt Trigger
Schmit! Trigger
MOS Driver
MOS Driver

48mA 10L

Invert

Latch

Schmit! Trigger
Schmit! Trigger
MOS Driver
MOS Driver

-

Noninvert
S
Invert

32mA 10L

32mA 10L
Master Reset

Noninvert
LS

Clock Enable .

Invert

Master Reset

-

Register
Noninvert

Clock Enable
Open Collector

S

-

-

Schmit! Trigger
Schmit! Trigger

-

Buffer

-

SN54S534

Schmitt Trigger
Schmitt Trigger

32mA 10L
Invert

32mA 10L

11·3

m

Pick the Right 8-Bit - or ie-Bit -Interface
p.rt for the Job
Chuck Hastings and Bernard Brafman

Introduction
A few years ago; 20-pin 8-bit buffers, registers, latches, and
transceivers came into existence as a rather haphazard
upwards evolution from the MSI devices available in' the
mid-1970s. As time went on, usage of these parts increased
until they became one of the fundamental computer-system
building-block "primitives" -the "glue" which holds the
entire system together. System designers demanded, and
semiconductor manufacturers provided, many refinements
such as inverting outputs to reduce parts count in assertivelow-bus systems, high-drive outputs to rescue designs with
overloaded buses, Schmitt-trigger inputs to likewise rescue
designs troubled with severe bus noise, high-voltage outputs specifically suited for driving MOS inputs, seriesresistor outputs for driving highly-capacitive loads such as
dynamic-MOS address buses, and so forth.
Today the demands are to reduce component costs and
system board area. Reducing parts count achieves both of
these objectives at one stroke. With the development of the
300-mil 24-pin SKINNYDIP'" package, it is now possible to
effectively incorporate the equivalent of two 20-pin 8-bit
interface parts into one 24-pin "16-bit interface" part. The
approach is to look for common configurations of pairs of
8-bit parts, and implement the pair as a single chip. Common
configurations include back-to-back "registered (or latched)
transceivers," with the same options already available in the
20-pin 8-bit parts read back registers or latches, and pipelined
registersor latches.

Interface Basics
Where Do Interface Circuits Fit In?
Interface circuits appear as unglamorous bread-and-butter
commodity items, as compared to many of the other more
complex integrated circuits of today: their sales volume is
very high, their average selling price is comparatively low,
and essentially interchangeable parts are offered by several
suppliers. They have the humble role of being the "glue"
which holds digital systems together; they are means rather
than ends in themselves.
.
When preliminary system block diagrams turn into detailed
schematics, the blocks turn into complex circuitsmicroprocessors, multipliers/dividers, automatic dynamicMQSRAM refresh controllers, high-speed FIFOs, programmable-logic circuits, arithmetic-logic units, and so forth. But
then, however. the lines between those blocks turn inlo
interface circuits, which must be there in the final design but
never explicitly get noticed during the conceptual-design
stage!
The term "interface" is actually a bit of a misnomer, since it
implies that these parts always occur at a boundary between
two somewhat different types of logic. That may have been
true once, and it is still true that many of the circuits commonly called "interface" have inputs and/or outputs which
are different electrically from those of, say, triple three-input
NAND gates produced using Ihe identical solid-state-circuit
technologies. But a general working definition of "interface
circuits.. also has to cover some other parts which get used

"INTEIlFACE CIIlCUITS ... TH~ 'GLUE'
WHICH HOLDS DIGITAL S'fSTEMS
TOGETHEIl ... "

in similar system roles, but have normal inputs and normal
totem-pole or three-state outputs. One such definition, current today at Monolithic Memories, is
n. •• ultra-high performance Integrated circuits which do not
lend themselves to higher levels of Integration, due either to
their parallel data structure or to the electrical properties of
their inputs and/or outputs."
Interface circuits get used wherever data must be held,
transmitted on demand, power-amplified, level-shifted, read
from a noisy bus, inverted, or otherwise operated upon in
some simple electrical way. If more complex transformations
of the data are called for. of a predominantly mathematical
rather than electrical nature, the designer will typically try to
perform the required operations with readymade LSI or MSI
circuits. Even here, of course, interface circuits often have
the inconspicuous but crucial role of performing format conversion so that several LSI circuits can communicate with
each other. Still, they are viewed as "overhead;' which
system designers try to minimize and semiconductor producers often rank well below their top level of corporate
priorities.
But interface circuits are here to stay, at least for several
more years. And the realization is.growing among both users
and producers of semiconductors that, since interface parts
are not about to vanish soon, they need to be treated as
something more than afterthoughts to the design process.
Users who select interface circuits shrewdly are achieving
real gains in system performance and reliability, and significant reductions in system size, weight, and power consumption. Producers who do a conscientious and professional job
of developing and marketing these humble parts are finding
increased demand for their wares, even during recessions.
Two major trends currently evident in the world of interface
circuits are:
• The emergence of an orderly, matrix-like approach to
Interface products, so that taken all together they form an
array rather than simply a splendid Jumble of assorted types.
• A strong emphasis on Increasing the number of data bltl
whiCh can be handled or accomodated by a single interfacecircuit package.

Pick the Right 8-Bitor 16-Bit Interface for the Job
This paper will discuss each of these trends in some detail,
and will then go on to present some realistic interface applications based on several actual designs.
What Kinds of Interface Circuits Are There?
Commonly, the label "interface circuit" is applied to any of a
diverse collection of miscellaneous devices which don't
seem to fit into any other classification. As the term is used
here, however, it means either one of three basic 8-bit
types-buffers, latches, and registers~which are simple
interface circuits, or else one of several 16-bit compound
interface circuit types such as transceivers and pipelines.
Buffers merely "pass" or transmit information at increased
power levels. Most contemporary buffer circuits, including
20-pin 8-bit buffers, also have an electronicallYcselectable
electrical-isolation capability. Such a three-state buffer has a
type of output which can be switched into a "hi-Z" (highimpedance) state in which it does not drive, nor appreciably
load, the circuit node to which it is attached.
True or noninverting buffers pass the input information along
with the same polarity (i.e., conventions in the representation of ones and zeroes by high and low voltages) that it had
when it was received. Inverting buffers reverse .the polarity
of the input information from what was received, complementing all ones to zeroes and all zeroes to ones.

Most buffers feature standard PNP inputs. However, the
'S/'LS340/341/344/310 buffers feature Schmitt-trigger inputs,

with a guaranteed 300/400-millivolt deadband (typically twice
that) centered about the switching threshold voltage. (This notation is shorthand for "54/74S340, 54/74S341 , 54/74S344,
54/7 4S31 0, 5417 4LS340, 54/74LS341 , 54/74LS344 and
54174LS310," and will be. used frequently. hereafter.) These
Schmitt-trigger buffers won't respond to input noise pulses
which would make buffers with normal inputs start to switch, as
long as the noise pulses do not completely cross the deadband;
thus noise immunity is improved.

inputs to be stored in the register, and then to remain present
at the register outputs until another rising edge occurs.
When the clock is in a steady-state condition (a "level"),
either on or off, or even when the clock goes through a
transition from on to off (a "falling edge"), the outputs of the
register do not change. Thus, unlike latches, registers lack a
mode in which they act exactly like buffers and pass information directly from their inputs to their outputs. This lack is a
consequence of the control signal being "edge-sensitive"
rather than "level-sensitive:'
Transceivers are bidirectional interface circuits capable of
interconnecting two buses so that information can pass in
either direction. Most of the transceiver parts in production
today are buffer transceivers-they are like two crosscoupled buffer circuits within a single 20-pin package. A
16-bit buffer transceiver has eight A-bus data pins and eight
B-bus data pins. Either the A-to-B buffers may be enabled,
or the B-to-A buffers, or neither; if both sets of buffers were
to be enabled, obviously there would be a race condition on
each of the data lines, and so the control structure of some
buffer transceivers specifically disallows that mode of operation. (Some other types do allow it.) Buffers which are not
enabled are, of course, in the hi-Z state. Thus each buffer
transceiver interface circuit consists of eight logical elements, and each of these logical elements consists of two
simple-buffer elements cross-coupled back-to-back so that
the input line for one is the output line for the other and
conversely.
Latch transceivers and.register transceivers. are now positioned
to become major factors in the marketplace; several semiconductor houses now offer such devices. In particular, Monolithic
Memories now supplies several different families of these devices in the 24-pin 300-mil SKINNYDIP® package; some of these
families are also supplied by Texas Instruments,.A variety of
speeds and architectures are available; see section 12 of this
Databook for details.
Pipelines are unidirectional interface circuits having more
than one full-width internal latch/register or"stage;' but typically having just one set of parallel data inputs and one set of
parallel data outputs. Two-stage latch pipelines, and both
two-stage and four-stage register pipelines, are available.
The four-stage devices can store twice as much information per
package, but the two-stage devices can be reconfigured more
flexibly and have a greater degree of separate control for each
stage.

Understanding and Using Interface
.. THE '\..5340/341/3441310 BUFFE~S FEATU~E
INPUTS, WITH A GUA~ANTEED ... DEADBAND.

SCHMlrr-T~I.GGE~

Latches and registers have the same basic capability as
buffers, but also have the additional capability that they
retain stored information as long as power is supplied to
them. Each of these circuit types requires an additional control signal in order to perform its system function.

More specifically, latches use an enable signal. When this
signal is on, they store information, and their outputs do not
change even if the information presented to their inputs
changes. When their enable signal is off, latches. act just like
buffers. Turning on the enable signal in effect "freezes" in
place whatever information was passing through the latch,
so that the latch stores it.

I

I

Registers use a clock signal instead of an enable signal.
When the.clock signal goes through a transition from off to
on, this "rising edge" causes the information present a.t the

How Designers Choose Interface Circuits
In the real world, a digital-logic designer doesn't set out
deliberately to use some particular interface circuit whose
properties he has carefully learned, in the same way that he
might for instance set out to use a bit-slice registered ALU or
a multiplier/divider. Rather, as we have said, it is much more
likely that it all starts with some innocent-looking little line
between two blocks on his preliminary system block diagram
which, it turns out, can't really be just a simple little line
aiter all.
Maybe the data which travels on that little line goes away at
the source unless the little line is actually also capable of
seizing it at the proper time and remembering it. Or maybe
the end of the little line is an assertive-low system bus, with
enough loads hanging off iUo call for almost 30 milliamps of
drive capability in whatever contemplates driving the bus,
which doesn't qujte jibe with the 2-milliamp drive capabilities and assertive-high outputs of the MOS LSI device from
which the data is coming.

Monolithic WNlemories

11-5

OJ

Pick the Right 8-Bit or i6-Bit Interface for the Job
At this point the designer needs an interface circuit, andwittingly or unwittingly"-he must go through a several-stage
decision process to determine what interface circuit he
needs to actually implement that little line., before his block
diagram can turn into a system. He must also fervently hope
that, by the time he gets to the final twig on his de~ision tree,
the interface part he needs will turnout to actually exist:
Figure 1 is an example.
A top-down design approach, as illustrated in Figure 1, isn't
always wise with integrated circuits, simply because the
chances are fairly good that the desperately needed circuit
actuany won't exist r1 . And there was a time, not all that long
ago, when only a quasi-random subset of all of the obviously
possible variations of the baSic interface parts had reached
full ·production status, so that they CQuid be bought and
plugged in. The hapless designer just had to memorize what
that subset was, and do his designbottorn-up from there.
Today, chaos is giving way to orde.r, and enough of the possible jnterface parts which a designer might want do by now
exist (or will exist.shortly) that the kind of top-down thought
process portrayed in Figure 1 really will work out all right
when designing with interface. For instance, the line of interface parts now in production at Monolithic Memories is sufficientlv orderlv to be oraanizable into the matrix of the
IntEirface Selection Guide oli page 11-3 of this databook.
Although this Guide is still somewhat irregular; it is at least
recognizable as first-cousin to a logic-design Karnaugh map,
and you can actually get your hands on any olthe interface parts
in the matrix.

face Selection Guide have been derived from a very few
basic tYpes, by implementing those combinations which
make $ense of several two:valued properties of interface
parts. These are:
• Commercial versus military temperature-range operation.
• High-speed Schottky (S-TTL) or low-power Schottky
(LS-TTL) speed/power range.
•. Noninverting or inverting outputs.
• No memory capabilities in the logical elements, so that
they operate as buffers; or memory capabilities therein,
further subdivided according to whether ·the logical elements operate as latches or registers.
• Compound f6-bit interface circuits or simple a-bit interface.circuits.
•. Hi-drive or standard levels of current-sinking capabilitY.
(loll at the outputs.
• Schmitt-trigger or standard inputs.
• For non-three-state parts, master-reset or clock-enable
.
control inputs.
• Series-resistor or standard outputs.
Obviously, not all imaginable combinations of the above
properties actually exist as parts, or would even be useful if
they did; and semiconductor houses cannot afford for long
to offer 2" interface-circuit part tYpes for rapidly increasing
n. Moreover, certain ofthe properties which in the past have had
justtwo possible major choices (e.g., S-TTL and LS-TTL) today
have more than two; for instance, Section 12 of this Oatabook
includes some CMOS parts..
...

DATA WORD WIDTH·

Nevertheless, by now the matrix approach has been fullyenough implemented to offer a very helpful perspective to
the working designer.

Part numbers today allow some of the properties of interface
circuits to be directly inferred, at least if the part number
follows the conventions of the industry-standard "54/74"
numbering series. 54/74 part numbers have a well-defined
format VVE4TxxxP. with the following interpretation:
• VV - a prefix which variessomewhatfromvendortovendor.
• E4 - a temperature-range environmental specification.
"54" implies the military temperature range (-55°C
to +125°C), and "74" the commercial temperature
range (OOC to + 70°C for several vendors, and OOC
to + 75°C for Monolithic Memories). Iii any case,
interface circuits must run properly over a very wide
temperature range.
• T

Figure 1. ·Interface-Circuit-Selection Decision Tree
The dimensions of variation for interface parts in any such
Karnaugh map are, of course, two-valued. "Boolean" vari"
abies. It is realistic from both logical and historical viewpoints to consider that all of the interface parts of the Inter-

11-6

-'- a solid-state-circuit technologY,· Upwards of a dozen
of these have been promoted, with widely varying
success, dUring the last decade. The earliest one,
plain old gold-doped TTL, omitted using any special
letter in part numbers. Today,. the two dominant
technologies are "S" (high-speed Schottky) and
"LS" (Low-power Schottky). Others becoming quite
important include "F" (f6r"FAST," a lower-power form
of high-speed Schottky); "ALS" (advanced low-power
Schottky); and "SC," "HCr and "ACT" (isoplanar
CMOS processed to be fully TTL-voltage-level
compatible).

• xxx - a two-digit, three-digit, and today sometimes even
four-digit n.umber which uniquely specifies the pinout of the part and its "fuliction-al behavior" (see the
explanation which follows), independent of s'peed/
power range.

Pick the Right· a-Bit or 16-Bit Interface for the Job

240 Octal Buller
OUTPUT}
ENABLE
GROUP 1

374 Octal Register

Ei
1A1

245 Octal Transceiver

OUTPUT
OUTPUT ENABLE OE 1

DIRECTION DIR 1 h:=-----,=;=o

DATA

20 VCC

='-++-'='4. " E OUTPUT

ENABLE
GROUP 2

2

ENABLE

DATA
B-BUS
IN/OUT

DATA

I!

-L..._ _~:!....Jr-" CK CLOCK

Figure 2. Pinouts for the Three Basic 20-Pin Interface Parts

• P

_ a package type: plastic, cerdip, flatpack, leadless
chip carrier, sidebrazed ceramic, small-outline
surface-mount; or whatever.

The functional behavior of'3 circuit can be defined somewhat circularly as "what a designer needs 10 know aboullhe
circuit in order 10 conslruct designs which operale properly
using parts from any supplier interchangeably:' This definition is akin to one classic definition of computer architecture
as" ... the structure of the compute.r a programmer needs to
know in order to be able to write any program that will corfelltly run on the computer."r2·
.

All of the buffers have the same pinout as the 'S240. They
differ in speed/power range, in the polarity of the outputs, in
the noise-rejection capabilities of the inputs (Schmitttrigger or standard), and in enable structure (complementary
or assertive-low) as shown in Figure 3, which really is
unequ,ivocallya Karnaugh map.
COMPLEMENTARY
ENABLES

ASSERTlve·LOW
ENABLES

..--....---.
'S210
'S310

'S241

'S244

'S240

'S341

'S344

'S340

}

I

--

}

'LS241 'LS244 'LS24O

.

,

INPUTS

SCHMtnTRIGGER
INPUTS

'LS310 'LS341 'LS344 'LS340
'LS210

USUAL

USUAL
INPUTS

'-,,-

INVERTING

NON·INVERTING

INVERTING

OUTPUTS

OUT~S

OUTPUTS

III

Figure 3, 8-Bit Three~State Buffers

~- ~'

"" . IIiiTERFACECIRcuiTS MUST
IIUN PROPER!.'lOVER A VEIl'l WIPE TEMPERATURE RANGE ... "

T\Noparts produced using different solid-state-circuit technologies may exhibit essentially the same functionaJbehavior.lfthat is the.case, and ifeither part will also satisfy system
timing constraints (which is an issue quite separate from that
of".functional behavior") and input/output voltage compatibility constraints, the designer does not need to care what
kind of internal gates are used within the part-Schottky
TTL, ECL, CMOS,. NMOS, or water wheels. On the other
hand, two parts produced using the same technology may
have subtle, or even drastic, differences in their luncti.onal
behavior; for example, one may have inverting outputs, or
hi.drive outputs, or Schmitt-trigger inputs whereas the other
does no!.
The Matrix of Interface Part 'TYpes
The intfirface parts of the Interfac(# Selection Guide mostly have
one of just three different pinouts; shown in Figure 2, in their
usual20-pin plastiC or cerdip SKINNYDIP form.

Most of the latches and registers have the same pinout as the
'8374,. They differ in whether the memory control line is
level-senshive (latch) or edge-sensitive (register)'. in
speed/power range, in the polarity of the outputs, and in the
10L (current-sinking drive) capability of the outputs as shown
in the Karnaugh map of Figure 4.

I
~TTl I

,

.

.

REGISTERS

LATCHES
-.~

'S533

'S373

'S374

'S534

'S535

'S531

'S532

'S536

--

--

8-TTL

-- --

----

'LS533 'LS373 'LS374 'LS534

-..-

-

,

}

I}

USUAL

(2I>mA)
OUTPUTS

HI·DRIVE
(32·mAJ
OUTPUTS

USUAL
(24-mA)

OUTPUTS

Figure 4; 8-BitThreecState Latches and Registers

11-7

Pick the RightS-Bit or 16-Bit Interface for the Job
The three transceivers of the Interface Selection Guide are
more specifically buffer transceivers-compound 16-bit
interface circuits like two 8-bit buffer circuits cross-coupled
"back-to-back" within a single device. They differ in inputcurrent and output-leakage-current specifications, which
here are indistinguishable for test purposes since every data
pin is both an input and an output; the 'LS245 specification
is tighter. (The 'L8245-1 is also specified as faster, but that is
not a difference in "functional behavior.") There is also a
difference in IOL capability; the 'LS645-1 is specified as
higher. Actually, all three devices undergo identical fabrication, and are separated only at final testing; for instance,
those 'LS645s capable of meeting the 48-mA IOL specification in both directions drop into a separate bin.
Upcoming developments in interface parts will tend in many
cases to follow the matrix approach, at least partially. Even
where the new parts do not fit perfectly into the matrix of
existing parts, some attention is likely to be paid to issues of
balance and symmetry over the entire interface-circuit

pr~~t"~~.:.:.: ~m'
., '
D~R~1-~ON-.. .

I'

24 mA

:! ~i;~:ION

"n"" '''"." ""'"
OF MEETING THE 48 MA 10l.
SPECIFICATION IN BOTH
DIRECTIONS DROP INTO ~
SEPARATE BIN
I

~~~~~
~,

~/'"

In some cases, new interface parts directly "fill in the holes" in
the matrix. For instance, some recent additions to Monolithic
Memories' line of interface parts are:
Speed/
Function
Polarity Feature
Part Number
Power
Register

8

Noninv.

Master
Reset

SN54/74S273

Register

8

Noninv.

SN54/74S377
8N54/74S383@

Buffer

8

Noninv.

Clock
Enable
8eries
Output
Resistor

Buffer

S

Noninv.

8eries
Output
Resistor

SN54/748731

Buffer

8

Inil.

8eries
Output
Resistor

8N54/748730*

8N54/748734*

Series
8N54/74S700
Output
Resistor
NOTES: @- The '8383 differs from the '8377 only in having open-collector outputs rather than totempole outputs.
*-The 'S734 is a direct replacement for AMO's
Am2966.
*- The 'S730 is a direct replacement for AMO's
Am2965.
Table 1. Recent Additions to the Monolithic Memories Interface-Part-Type Matrix
Buffer

11-S

8

Inv.

WIonoIithlc

" ... THE 'S273 ANO 'S377,
LIKE THEIR LS-TTL COUNTERPARTS, ARE PESIGNEP WITH
STANOARP TTL 'TOTEM-POLE'
OUTPUTS ... "

The 'S273 and 'S377 bring to higher-performance TTL systems the same functional behavior which has long been
available for medium-performance TTL systems, with the
popular 'LS273 and 'LS377 parts. The '8273 and 'S377, like
their LS-TTL counterparts, are designed with standard TTL
"totem-pole" outputs. Somehow, in the somewhat more chaotic early days of 8-bit interface, the need for high-speed
8chottky versions of these parts got overlooked by most
interface producers.
Since the 'S273 and '8377 are totem-pole-output parts, the
control pin which gets used on the '8374 (whose pinout they
otherwise follow) for "Output Enable" for the three-state
outputs is available for something else. The 'S273 uses it as
a "Master Reset" (MR) input, capable of forcing all of the
eight Ootype flipflops on the chip into the off (low) state
simultaneously, regardless of their previous state-or of the
state of the clock line and/or the data-input lines. The '8377,
on the other hand, uses that same pin as a "Clock Enable"
(Ci

18

V

4

16

6

to,

8

14
12

lYl

lAl

lY2

lA2

1Y3

lA3

1Y4

lA4

1
2

,....J EN

~

I>

18

'V

4

16

6

t:::"

8

14
12

tY1
lY2
lY3
1Y4

--.C

E2

2Al
2A2
2A3
2A4

19
11

lEN

E2

~

I>

9

'V

13

t:::"

15

7
5

......

17

3

.

2Yl

2Al

2Y2

2A2

2Y3

2A3

2Y4

.2A4

19 ..... .lEN
11

~

I>

13

to,.

7

15

t:::"

5

17

3

'241
1

lAl
lA2
lA3
lA4

E2

2Al
2A2
2A3
2A4

2

Ei

~

'V

18

4

16

6

14

8

12

19
11

lYl

tAl

1Y2

lA2

tY3

lA3

lY4

lA4

lEN

E2

~

I>

2Yl
2Y2

2Y3

2Y4

'244

r-.IEN

I>

9

'V

'V

9

13

7

15

5

17

3

2Yl

2Al

2Y2

2A2

2Y3

2A3

2Y4

2A4

1

..... J EN

t;

2

I>

18

'V

4

16

6

14

8

12

. 19
11

13·

1Y3
lY4

."

,....J EN

~

I>

9

'V
~

15
17

1Yt
1Y2

7
5

...

3

2Yl
2Y2
2Y3
2Y4

III

SN54/74LS210 SN54174LS240 SN54/74LS241

SN54/74LS244

Absolute Maximum Ratings
Supply voltage V CC ..•..........••..•.....•.•..••••.•..••..••.•.•.•...•..••.••..•..•...•.••••.••.•••..•......••..• 7 V
Input voltage .........••.....•...•..•....•..•...•.•••...••......•....•.•..•.••..••......•..••..•...•...........•.• 7 V
Off-state output voltage ••..••..•..•...••.•••.. . . . . • . . • . . . • • • . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . . . . . . . . . . . . . .• 5.5 V
Storage temperature ......................••..•...........•.............................•.........•.•.• _65· to +150· C

Operating Conditions
SYMBOL
Vcc
TA

MIN

TYP

Supply voltage

4.5

5

Operating free-air temperature

-55

Electrical Characteristics
SYMBOL

MILITARY

PARAMETER

TEST CONDITIONS

VIL

Low-level input voltage
High-level input voltage

VIC

Input clamp voltage

I:t.VT

Hysteresis (VT + - VT

MIN

TYP

MAX

5.5

4.75

5.

5.25

125

0

75

UNIT
V
·e

Over Operating Conditions

PARAMETER

VIH

COMMERCIAL

MAX

MILITARY
MIN

TYP

COMMERCIAL

MAX

MIN

TYP

0.8

0.7
Vee = MIN,

II

= -18mA

Vee = MIN

-1.5

-1.5
0.2

0.2

0.4

UNIT
V
V

2

2

J

MAX

V
V

0.4

IlL

Low-level input current

Vee = MAX,

VI

= 0.4V

-0.2

-0.2

IIH

High-level input current

Vee = MAX,

VI

= 2.7V

20

20

pA

II

Maximum input current

Vee = MAX,

VI

=7V

0.1

0.1

mA

Vec - MIN,

IOL

= 12mA

0.4

0.4

VOL

Low-level output voltage

10L

= 24mA

VIL

= MAX,

VIH

= 2V

VCC = MIN,
VOH

10ZL

High-level output voltage

= 0.5V,

VIH

= 2V

Vee = MAX,
Off-state output current

10ZH
lOS

VIL

Output short-circuit current

*

VIL

=" MAX,

VIH

= 2V

ICC

Supply
Current

Outputs
Low

Vee = MAX,
Outputs open

* Not more than one output should be shorted at a time and
Switching Characteristics

tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ

PARAMETER

10H - -3mA
10H = -12mA
10H - -15mA

'"

dura~lon

2.4

2.4

3.4

3.4
V

2
2
-20

-20

pA

Vo = 2.7V

20

20

pA

-225

mA

-40

-225

17

-40

27

17

27

LS241 , LS244

17

27

17

27

LS210, LS240

26

44

26

44

LS241 , LS244

27

46

27

46

LS210, LS240

29

50

29

50

LS241 , LS244

32

54

32

54

mA

I

of the short-CIrcuit should not exceed one second.

VCC = 5 V, TA = 25·C
TEST CONDITIONS
(See Tel' toacllWa••lorms,

Data to Output delay
eL : 45pF

RL : 6670

Output Enable delay
Output Disable delay

0.5

Vo = 0.4V

LS21 0, LS240

Outputs
Disabled

SYMBOL

V

Vee = MAX

OUtputs
High

mA

CL: 5pF

RL : 6670

LS210, LS240
MIN TYP MAX

LS241,LS244
MIN TYP ",,!AX

UNIT
ns

9

14

12

18

12

18

12

18

ns

20

30

20

30

ns

15

23

15

23

ns

15

25

15

25

ns

10

18

10

18

ns

,I
;"

SN54/74S210 SN54/74S240 SN54/74S241

SN54/74S244

Absolute Maximum Ratings
8upply voltage vee ..........................•.................................... , ...•..••...•.•..............•.. 7 V
Input voltage ............•.............................................................••...•................... 5.5 V
Off-state output voltage ..•....... . . . . . • . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • • • • . . . . • . .. 5.5 V
8torage temperature •....................................••...........•................................ -65. to +150·e

Operating Conditions
SYMBOL
Vee
TA

Supply voltage

4:5

Operating ,free-air ,temperature

-55

Electrical Characteristics
SYMBOL

TEST CONDITIONS

Vil

loW-level input voltage
High-level ,input voltage

VIC
tNT

'Input'clamp voltage

J

AriyA

Low-level
I' input current

..

Any E

75

COMMERCIAL
MIN TYP MAX

MILITARY
MIN TYP MAX

O.B

UNIT
V
·e

= MAX

VI

= 0.5V

-0.4

-0.4

-2

-2

= MAX
= MAX

VI

-' 2.7V

50

VI

- 5.5V

1

VOL

l6w~level output voltage

Vee
Vil
V IH

VIH
Vee

= MAX

Vil
VIH

= 0.8V

Vil

Off-state output current

10lH
,Output ,short-circuit currenff'

= MIN
= O.BV
= 2V
= MIN
= O.BV
= 2V

Vee
High-level output voltage

- -1BmA

= 2V

10l
10l

10H
10H - -3mA
10H - -12mA
10H

- -15mA

Vo

= 0.5V

Vo

= 2.4V

Vee = MAX
Outputs open

Outputs
Disabled

0.4

0.2

.

V
V
V
mA

50

/lA

1

mA

0:55
V

= 64mA'
= -1mA

0.55

2.4
2

2.7
2.4

3.4

3.4

V

2

-so
-50

-50

I

/lA

50

50

/lA

-225

-225

mA

-:50

BO

123

80

135

8241,8244

95

147

100

145

95
100

160

8210,8240
8241,8244

120

170

120

1BO

8210,S240

100

145

100

150

8241,S244

120

170

120

1BO

8210,8240

Outputs'
Low

0.4

= 4BmA

Vee- MAX

Outputs
High "

-1.2

-1.2
0.2

UNIT

V

2

Vee
Vee

ICC

5.25

Vee

Vee

Supply, Current

5

II

Max.imum.input current

lOS

0

= MIN
= MIN

High-level input current

lOll

4.75

O.B

IIH
II

VOH

5.5
125

2
Vee

Hysteresis, (VT + - VT

5

COMMERCIAL
MIN TYP MAX

Over Operating Conditions

PARAMETER

VIH

III

MILITARY
MIN TYP MAX

PARAMETER

150

mA

t Not more than one output should be shorted at a time and du(atlon of the short-CircUit should not exceed one.s.8cond,
Switching Characteristics VCC = 5 V, TA = 25·C
,;

SYMBOL
tplH
tpHL
tpll
tplH
tpll
tpHl

PARAMETER'

I

,

TEST CONDITIONS
(See Test LoadlWavelorlTlll)

Data to Output delay
eL = 50pF RL

= 900

Output Enable delay
"

"

Output Disable delay

el = 5pF

RL

= 900

S241, S244
S210, S240
MIN T:YP MAX " MIN' TYP MAX
4.5
4.5

UNIT

.,

6
6

9
9

ns

7
,15

10

15

ns

6.5

10'

B

12

ns
ns

10

" 15

10

15

ns

6

9

6

9

ns

10

• For the 8210 add 2 ns lor the E2 (Pin 19) enable

11-19

OJ

SN54/74LS210 SN54/74LS240 SN54./74LS241 SN54/74LS244

Die Configurations
'LS21 0

'LS240

Die Size: 85x146 mll 2
'LS244

'LS241

11-20

1IIIono"'hlc W.emorles

SN54/74S210 SN54/74S240 SN54/74S241

SN54/74S244

Die Configurations
'S240

'S21 0

Ole Size: 68x100 mll2
'S244

'S241

1m

·"';"'Uhlc

m

Memories

11-21

SN541'74LS210
SN541'74S210

SN541'74LS241
SN541'74S241

SN541'74LS240
SN54/74S240

SN541'74LS244
SN541'74S244

Test Load
(SEE NOTE B)
TEST POINT* (ei-..-----.--+oIf-......

~l-.
---<....-S1 0-0-,,,,.'1,--005
V

(SEE

~bTE A)

I
S2

* The "TEST POINT" is driven by the output under test,
and ob,served by instrumentation.

Test Waveforms
3V

OUTPUT
CONTROL
(Low-level
enabling)

INPUT
OV

~-----3V

'------~~--~-----OV

VOH

IN-PHASE
OUTPUT _ _ _~_,

WAVEFORM 1
(See Note· D)

VOL
VOH

OUT OF PHASE
OUTPUT
(See Note G)

VT
VOL

Enable and Disable

Propagation Delay

NOTES: A. .CL includes probe and jig capacitance.
B. All diodes are 1N9160r 1N3064.
C. For Series 54n4S, RO = 1K, VT = 1.5 V.
For Series 54n4LS, RO 5K, VT 1.3 V.

=

=

D. Waveform 1 is for an Dutputwith internal conditions such that the
output is low except when disabled by the output control.
Waveform 2 is foran output with internal conditions such that the
output is high except when disabled by the output control.

E. In ,the examples above, the phase relationships between- inputs
and outputs have been chosen arbitrarily.
F. All input pulses are supplied by generators having the following
characteristics: PRR :s; 1 MHz, ZOUT = 5onand:
For Serles 54n4S, tR:S; 2.5 ns, tF:S; 2.5 ns.
FOr Series 54n4LS and PAls, tR:S; 15 ns.tF:S; 6 ns.
G. When measuring propagation delay times of 3-8tate outputs,
switches S1 and S2 are closed.

11-22

Monolithic

W Memories

a-Bit Buffers with
Schmitt Trigger
Inputs
I

Features

Ordering Information

• Schmitt-trigger inputs guarantee high noise margin
• Three-state outputs drive bus lines
i •

SN54/74LS310 SN54/74S310
SN54/74LS340 SN54/74S340
SN54/74LS341SN54/74S341
SN54/74LS344 SN54/74S344

Typical input and output capacitance ,,;10 pf

• Low-current PNP inputs reduce loading
• 20-pin SKINNYDlp® saves space
• 8-blt data path matches byte boundaries
• Ideal for microprocessor interface
• Complementary-enable '310 and '341 types combine multiplexer and driver functions
• Pin-compatible with SN54174S210/24011/4 and
SN54174LS210/240/1/4; can be direct replacement in
systems with noise problems

Description
In addition to the standard Schottky and low-power Schottky
8-bit buffers, Monolithic Memories provides full hysteresis with
a ''true'' Schmitt-trigger circuit. The improved performance
characteristics are designed (1) for the low-power Schottky
I buffers, to be consistent with the SN54174LS14 hex Schmitt, trigger inverter, and to guarantee a full400mVtloise immunity;
. (2) forthe Schottky buffers, to have low propagation delays, and
I to guarantee a full500mVnoise immunity. The Schmitt-trigger
operation makes these LS/S buffers ideal for bus receivers in a
noisy environment.
These 8-bit buffers provide high-speed and high-current interface capability for bus-organized digital systems. The threestate drivers will source a termination to ground (up to 1330) or
sink a pull-up to Vee as in the popular 2200/3300 computer

PART
NUMBER
SN54LS310
SN74LS310
SN54LS340
SN74LS340
SN54LS341
SN74LS341
SN54LS344
SN74LS344
SN54S310
SN74S310
SN54S340
SN74S340
SN54S341
SN74S341
SN54S344
SN74S344

PKG* TEMP ENABLE POLARITY POWER
J,F
N,J
J,F
N,J
J,F
N,J
J,F
N,J
J,F
N,J
J,F
N,J
J,F
N,J
J,F
N,J

mil
com
mil
com
mil
com
mil
com
mil
com
mil
com
mil
com
mil
com

HighLow

Invert

Low
HighLow

LS
NonInvert

Low
HighLow

Invert

Low
HighLow

S
NonInvert

Low

peripheral termination. The PNP inputs provide improved fan-in
with 0.2 mA IlL for the low-power Schottky buffers and 0.25 mA
II L for the Schottky buffers.
The '340and '344 provide inverting and non-inverting outputs
respectively, with assertive-low enables. The '31 Oand '341 also
provide inverting and non-inverting outputs respectively, but
with complementary (both .assertive-Iow and assertive-high)
enables, to allow transceiver or multiplexer operation.
All of the 8-bit devices are packaged in the popular 2o-pin
SKINNYDlp®.

Logic Symbols
'310 8-Blt Buffer

'340 8-Bit Buffer

'341 8-Bit Buffer

'344 8-B it Buffer

*For other package types, please contact your local sales representative.

SKINNYDIP® is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

Monolithic ~.T!n
MemorIes U1Jl1.LI
11-23

SN54/74LS310/40/41/44SN5~/74S319/40/41/44

.EEE Symbols

'340

'310
1

lAl
lA2
1A3
1A4

E2

2Al
2A2
2A3
2A4

2

,.:...J,

E1

~N
.IT

t>

18

V

4

16

6

t-.

8

19

1,4
12

lAl

lYl
lY2

lA2

1Y3

lA3

lY4

lA4

lEN

E2

L;'

11

.IT

t>

V

9

13

7

15

5

17

3

2Yl

2Al

2Y2

2A2
2A3

2Y3
2Y4

2A4

1

....

EN
r

2

.IT

1A2
1A3
1A4

E2
2A1
2A2

2A3
,2A4

11-24

2

.0-

E1

I>

V

18

4

16

6

14

8

12

19
11

1Yl

lAl

lY2

lA2

1Y3

lA3

1Y4

1A4

lEN

E2

~

.0-

t>

18
16

6

14

8

12

19 ....
11

1Y1
1Y2
lY3
lY4

EN
.IT

I>

v

9

13

7

15

5

17

3

2Yl
2Y2
2Y3
2Y4

'344

.... J EN
~'

1Al

V

4

'341
1

t>

V

9

13

7

15

5

17

3

2Yl

2Al

2Y2

.2A2

2Y3

2A3

2Y4

2A4

Monolithic

m

1

....

2

EN
.IT

I>

V

18

4

16 ,

6

14

8

12

19
11

....

1Y2
1Y3
1Y4

EN
.0-

t>

V

9

13

7

15

5

17

3

Memories

1Y1

2Y1
2Y2

2Y3
2Y4

SN54/74LS310 SN54/74LS340 SN54/74LS341

SN54/74LS344

Absolute Maximum Ratings
Supply voltage vee ............................................................................................... 7 V
Input voltage ..................................................................................................... 7 V
Off-state output voltage ................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Storage temperature ........•.......................................................................... -65° to +1500 e

Operating Conditions
SYMBOL

MiliTARY
MIN TYP MAX

PARAMETER

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

5

COMMERCIAL
MIN TYP MAX

5.5

4.75

125

0

5

UNIT

5.25

V

75

°e

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

TEST CONDITIONS

COMMERCIAL
MIN TYP MAX

UNIT

VT+

Positive threshold voltage

AnyA*

1.5

1.7

2.0

1.5

1.7

2.0

V

VT-

Negative threshold voltage

AnyA*

0.6

0.9

1.1

0.6

0.9

1.1

V

VIC

Input clamp voltage

Vee = MIN

II = -18mA

AnyA*

0.4

AnyA*

0.4

0.8

0.4

ilVT

Hysteresis (VT+-VTJ
Dead band voltage

Vil

Input low voltage

Any E*

VIH

Input high voltage

Any E*

III

low-level input current

Vee = MAX

VI = 0.4 V

-0.2

IIH

High-level input current

Vee = MAX

VI=2.7V

20

II

Maximum· input current

Vee = MAX

VI = 7V

Low-level output voltage

Vee = MIN
VT+ =2 V
VT_ = 0.6 V

10l = 12mA

VOL

.

0.4

V

0.8

0.8

V

-0.2

mA

0.1

0.1

mA

0.4

0.4

2.0

V

2.0
...

p.A

V
10L = 24mA

0.5

10H = -3mA

2.4

VT+ = 2 V

10H = -12mA

2

VT_=0.6V

10H = -15 mA

Vee = MAX
VT+ = 2 V
VT_ = 0.6 V

Vo = 0.4 V

-20

-20

p.A

Off-state output current

VO=2.7V

20

20

p.A

Outputshort-circuit current"

Vee = MAX

-225

mA

10ZH

Outputs
High
Ice

V
V

0.8

Vee = MIN
High-level output voltage

10ZL

lOS

-1.5

-1.5

ilVOB

VOH

Supply
Current

Outputs
Low

3.4

2.4

3.4
V

2

-40

-.225

-40

'LS310,'LS340

17

27

17

27

'LS341, 'LS344

18

35

18

35

Vee = MAX

'LS310,'LS340

26

44

26

44

Outputs open

'LS341, 'LS344

32

46

32

46

'LS310, 'LS340

29

50

29

50

'LS341, 'LS344

34

54

34

54

..

Outputs
Disabled
**
*_

MILITARY
MIN TYP MAX

mA

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
"A" indicates data input, "E" indicates enable input.

WIonoIHhlc

m

IIIIemories

11·25

m

SN54/74LS310 SN54/74LS340 SN54/74LS341

SN54/74LS344

Switching Characteristics vcc =5 V, TA =25°C
'LS310, 'LS340
MIN TYP MAX

'LS341, 'LS344
MIN TYP MAX

UNIT

19

25

19

25

ns

19

25

19

25

ns

32

40

2.5

40

ns·

tpZH

23

35

24

35

ns

tpLZ

18

30

21

30

ns

15

25

18

25

·ns

. SYMBOL
tpLH

PARAMETER

(See Tetl LoadlWavelonna)

Data to Output delay

tpHL
tpZL

TEST CONDITIONS

CL = 45pF

RL= 6670

Output Enable delay

Output Disable delay

CL = 5pF

RL = 6670

tpHZ

Die Configurations
'LS310

E1

'LS340.

vecE2

Ei

2Y1

vee

GND 2A1

Ole Size: 85x146 mil2
'LS341

E1

U-26

vee E2

'LS344

E2

1Y4

SN54/74S310 SN54/74S340 SN54/74S341 SN54/74S344
Absolute Maximum Ratings
Supply voltage Vee ...............................................................•..•.......................... 7.0 V
Input voltage ........................................•......•............................•..... ',' .. .. . . .. .. .. ... 5.5 V
Off-state output voltage ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5,5 V
Storage temperature ................................................................................... -65° to +1500 e

Operating Conditions
SYMBOL

MILITARY
MIN TYP MAX

PARAMETER

Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

5

COMMERCIAL
MIN TYP MAX

5.5

4.75

125

0

5

UNIT

5.25

V

75

°e

Electrical Characteristics Over Openltlng CondHion.
SYMBOL

PARAMETER

TEST CONDITIONS

COMMERCIAL
MIN TYP MAX

MILITARY
MIN TVP MAX

UNIT

VT+

Positive tl1resl1old voltage

AnyA*

1.5

1.S

2.05

1.6

1.S

2.0

V

VT-

Negative tl1resl1old \loltag,e

AnyA*

O.S

1.1,

1.35

O.S

1.1

1.3

V

-1.2

V

0.5

0.7

Vie

Iflput ctampvoltage

Vee=MIN

ilVT

Hysteresis (VT+~VT-)

AnyA*

ilVDB

Dead band voltage

AnyA*

VIL

Input low voltage

AnyE*

VIH

Input high voltage

Any E*

IlL

Low-lever input current

Vee = MAX

VI = 0.5 V

-0.25

-0.25

IIH

High-level input current

Vee = MAX

VI=2.7V

50

50

pA

II

Maximum input current .

Vee = MAX

VI = 5.5 V

1

1

mA

-1.2

,

,0.5

0.7

V

0;3

0.15
,",

,

O;S

V
O.S

,

2.0

V
V

2;0

mA

,

i

VOL

II = -lSmA

Low-level output voltage

: Vee=MIN

IOL =4SmA

VT+ = 2V
VT_ = O.SV

10L= 64mA

0.55

"

V
0.55
"

Vee=MIN
VOH

High-level output voltage

10ZL
Off-state outpu! current
10ZH
lOS

lee

Output short-circuit c.urrent**

Supply
eurrent

2.7

10H =-1 mA
10H =-3mA

2.4

3.4

VT+= 2V

10H = -12 mA

2

VT_ = O.S V

10H =-15mA

Vee = MAX
VIH = 2.0V
VIL =O.SV

VO=0.5V

,-50

-50

pA

Va =2.7V

50

50

pA

-225

mA

2.4

V
2

"

-50

Vee = MAX

c

~225

olitputs

'S310:S3.uj

50 " 80

Hig~

'5341, 'S344

so

Outputs
,Low
Outputs
Disabled

3.4

130

-50
"

50

so

so

130

Vee = MAX

'S310, 'S340

110

155

100

155

Outputs open

'S341, 'S344

130

lS0

130

lS5

'S31 0, 'S340

135

180..

135

180

'S341 , 'S344

155

l!JO

150

200

mA

1

**

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

*

"A" indicates data input.

"e" indicates enable input.

11-27

III

SN54/74S310 SN54/74S340 SN54/74S341

SN54/74S344

SWitching Characteristics vcc = 5 V, TA = 25°C
SYMBOL

TEST CONDITIONS

PARAMETER

(See Teat LoadlWaveIonns)

'S31 0, 'S340
MIN TYP MAX

'S341, 'S344
MIN TYP MAX

UNIT

11

15

16

22

ns

16

22

10

15

ns

8

15

10

15

ns

tpZH

6

. 12

7

.12

ns.

tpLZ

10

15

10

15

ns

7

12

7

12

ns

tpLH

Data to Output delay

tpHL
tpZL

CL = 50pF

RL= 900.

Output Enable delay

Output Disable delay

CL = 5pF

RL= 900.

tpHZ

Die Configurations
'S310

Ole Size: 62x121 mil 2

'S341

'S344

GND

11-28

2A1

GND

IWonoIJIhIc

m"'emeries

2A1

SN54/74LS310/40/41/44 SN54/74S310/40/41/44
Function Tables

'340

'310
E1

E2

H

1YOUTPUTS

2YOUTPUTS

E1

E2

1YOUTPUTS

Z

Enabled
(Inverting)

H

H

Z

Z

H

2YOUTPUTS

L

Z

Z

H

L

Z

Enabled
(Inverting)

H

Enabled
(Inverting)

Enabled
(Inverting)

L

H

Enabled
(Inverting)

Z

L

L

Enabled
(Inverting)

Z

L

L

Enabled
(Inverting)

Enabled
(Inverting)

E1

E2

1YOUTPUTS

2YOUTPUTS

E1

E2

1YOUTPUTS

2YOUTPUTS

H
H
L
L

H
L
H
L

Z
Z
Enabled
Enabled

Enabled
Z
Enabled
Z

H
H
L
L

H
L
H
L

Z
Z
Enabled
Enabled

Z
Enabled
Z
Enabled

H
L

'341

'344

Z'" High impedance (output off).

INPUT VS OUTPUT VOLTAGE TRANSFER CHARACTERISTIC
OUTPUT

OUTPUT

YOH

rI
I

t
YOL

I
I
I

O'C

---~
~----~--~--.---~----------~INPUT

~

~--~--~--~--.-~-----------'INPUT

~

I~T~I

INVERTING DEVICE

~:l

NONINVERTING DEVICE

THRESHOLD VOLTAGE VS OPERATING TEMPERATURE
V

V

2.0

2.0

1.8

1.8

1.6
1.4

-----...----1-

VT"

1.6

DEAD BAND

1.4

1.2

1.2'

1.0

1.0

0.8

0.8

25

*

125

'C

MILITARY DEVICE

o

25

75

'C

COMMERCIAL DEVICE

Dead Band: The hysteresis is guaranteed at any operating temperature and voltage.

11-29

m

SN54/74LS310/40/41/44 SN54/74S310/40/41/44
Test Load

RL

TEST POINT*

(.I---.....- - - -.....- 4....--t--4.S1 0-NV--05V
CL

RO

(SEE NOTE AI(SEE NOTE C) ' - - - - - -.......-

2 V'-

LJ

3

17

4

16

5

15

8

14

7

13

8

12

9

11

B1

B2
B3

B4

as
B8
B7
B8

SKINNYOfP"!! is a registered trademark of Monolithic Memories.

.....~·lcm·
me....

';;
.
,.
_
TWX: 910-338-2376 . .
2175 Mission ColiegeBlvd. Santa. Clara, CA 95054-1.592 Tel: (408) 970-9700 TWX: 910-338·2374,

11-31

FOR
MORE DETAIL
SEE SECTION

8-Bit Buffer Transceiver
SN54/74LS645 SN74LS645-1
Features/Benefits
• Three-state outputs drive bus lines

• Low current PNP Inpuls ntduce 100ding
• Symmetric - equal driving capability In each dlrecUon
• 2o-pln SKINNYDII'® saves space

12

Ordering Information
PART
NUMBER
SN54LS645
SN74LS645
SN74LS645-1

TYPE
J,L,W
N,J

POLARITY

POWER

Noninvert

LS

Mil
Com
Com

J

• 8-blt data path matches byte boundaries
• Ideal

TEMP

for microprocessor Interface

• SN74LS645-1 rated at IOL

=48 mA

Description

Function Table

These 8-bit bus transceivers are designed for asynchronous
two-way communication between data buses. The control function implementation minimizes external timing requirements.
The device allows data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic level at
the direction control (DIR) input. The enable input (E) can be
used to disable the device so that the buses are effectively
isolated.
All of the a-bit devices are packaged in the popular 2O-pin
SKINNYDIP.

Logic Symbol

DIRECTION
CONTROL
DIR

ENABLE

E

B data to A bus
A data to B bus
Isolated

L

L
L

H

H

X

IEEE Symbol
'LS645/64S-1

E
DIR

8-BIt Transceiver
A1

A2
A3

A4
AS

A7
AI

19
1

G3
13EN1 (BA)
L-t,3EN2(AB)

2

.....

L

"71

18



2"7

LJ

3

17

4

16

5

15

8

14

7

13

8

12

9

11

·SK'NNYD}p~'·iS ~ regjster¢d trademark of M,onolithic Memo~ies.
.
TWX: 910,338-2376
2175 Mission College Blvd: Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

11-32

OPERATION

B

B

B3
4

B5
B8
B7
B8

a-Bit Registers
with Master Reset or Clock Enable
SN54/74LS273 SN54/74LS377
SN54/74S273 SN54/74S377
Ordering Information

Features/Benefits
• 20-Pin SKINNYDIP® saves space

PART
NUMBER

• a-bit data path matches byte boundaries
• Ideal for microprogram instruction registers
• Ideal for microprogram interface
• Suitable for pipeline data registers
• Useful in liming, sequencing, and control circuits
• Three '273s may replace four '174s
• Three '3ns may replace four '3785/Am25S07s

Description

PKG

TEMP

SN54LS273
SN74LS273

J,F,L,W Mil
N,J,L Com

SN54LS377
SN74LS377

J,F,L,w Mil
N,J,L Com

SN54S273
SN74S273

J,F,L,W Mil
N,J,L Com

SN54S377
SN74S377

J,F,L,W Mil
N,J,L Com

POLA- CONTROL
POWER
OPTION
RITY
Noninvert

Noninvert

Master
Reset

LS

Clock
Enable
Master
Reset

S

Clock
Enable

chronously cleared whenever the master reset line, MR, is low.
The '377 register is loaded on the rising edge of the clock provided
that the clock enable line, CK EN, is low.

These S-bit registers contain eight Ootype flip-flops, theyfeature
very low ICC (17 mA typical) on the low-power Schottky devices
and very"high-speed operation on the Schottky devices. The '273
register is loaded on the rising edge of the clock. (CK) and asyn-

All of the S-bit devices are packaged in the popular 20-pin
SKINNYOIP.

Function Table '273

Function Table '377

INPUTS

OUTPUT

INPUTS

OUTPUT

MR

CLOCK

DATA

Q

CKEN

CLOCK

DATA

Q

L
H
H
H

X

X

I
I

H
L
L

X

I
I

X

H
L

H
L

Lor H or j

X

L
H
L
00

X

Lor H or j

X

00
H
L
00

Logic Symbols

SKINNYDIP(~

8-Bit Register
with Master Reset
'273

8-Bit Register
with Clock Enable
'377

is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

Monolithio mT!ft
Memories InJrW
11·33

III

5N541'74L5273 5N541'74LS377 5N541'745273 5N541'745377

Absolute Maximum Ratings
Supplyvoltagevcc •••.••.••••••••••••••••••••••• ; •••••••••.••••••• , .••••• ; ••••••.•••••.•.•.•.....•.....•..........• 7V
Input voltage ••••••••••••.•.•........•.•.•.•.•......•...••...•.•...•.•...•.••..••.••.•••.••••••••••••••••••••••.•• 5.5 V
Off-state output voltage •••••••••••••••••••••••••••••••••••••.•••••••• , .......... ; •...........•..••••.....••.•••••••• 5.5 V
$toragetemperature range •••••••••••••••••••••••••••••••••••:••••••••••••••••••••.•.•.•.....••...•..... -65°C to + 150°C

IEEI 5ymbols
'273
Mii
CK
10
20
30
40
50
60
70
80

1
11
3

....

r,

10

1

CKEN

R
C1

11

CK
2

10

4

5

7

6

8

9

13

12

14

15

17

16

18

19

3

10

20

20

30

30

40

40

50

50

60

60

70

70

80

80

...

'377 .

,

G2
l2C1
2

10

4

5

7

6

8

9

13

12

14

15

17

16

18

19

10
20
3Q
4Q

so
6Q

70
80

Operating Conditions
SYMBOL

PARAMETER

TEST CONDITIONS

FIGURE

(See Interlace, Test
LoacllW•••'ormll

MILITARY
MIN TYP MAX

COMMERCIAL
UNIT
MIN TYP MAX

5.5

4.75

125

0

VCC

Supply voltage

4.5

TA

Operating free-air temperature

-55

tw

Width of clock

5

5

5.25

V

75

DC

High-tWH
1

20

20

ns

Low-tWMRL

2

20

20

ns

MRto CK
(,S273 only)

2

25 I

25 I

ns

Data input to CK

3

20 I

20 I

251

25 I

10 I

10 I

5I

51

5I

51

51

51

Low-tWL
Width of Master Reset

tWMR

(,LS273 only)

tree

lsu

Setup time
, .

Low CK EN to CK
(,LS377 only)
4

H,gh CK EN to CK
: (,LS377 only)
Data input

th

Hold time

3

Low CK EN to CK
('LS377 only)

ns

ns

4

High CK EN to CK
(,LS377 only)

11' The arrow indicates the transition of the ciock/enable input usod for referenco. I for the low-to-high transition. I for the high-to-Iow transition.

11,.34

NIonoIithlc

m

.emorles

SN54/74LS273 SN54/74LS377
Electrical Characteristics Over Operating CondHions
SYMBOL

PARAMETER

MILITARY
MIN TYP MAX

TEST CONDITIONS

COMMERCIAL
MIN TYP MAX

UNIT

I
I

VIL

Low-level input voltage

VIH

High-level input voltage

VIC

Input clamp voltage

VCC=MIN

II = -18 mA

-1.5

-1.5

V

IlL

Low-level input current

VCC=MAX

V,=0.4 V

-0.4

-0.4

mA

0.7

0.8

2

V
V

2

IIH

High-level input current

VCC= MAX

VI= 2.7V

20

20

p.A

Ii

Maximum input current

VCC= MAX

VI= 7V

0.1

0.1

mA

Low-level output voltage

VCC=MIN
VIL = MAX
VIH = 2V

10L =4mA

VOL

VOH

High-level output voltage

VCC= MIN
VIL = MAX
VIH = 2 V

lOS

Output short-circuit current*

VCC=MAX

Supply current t

VCC=MAX
Outputs open

ICC

0.25

0.4

10L =8mA
2.5

10H = -400j,lA

3.4

-20

0.25

0.4

0.35

0.5

2.7
-100

3.4

-20

V
-100

LS273

17

27

17

27

LS317

17

28

17

28

*

Note more than one output should b~ shorted a~ a time and duration of the short-circuit should not exceed one second

t

ICC is measured after first a momentary ground, and then 4.5 V is applied to clo~k, while the following other input conditions are held:
(a) fo, the 'LS273 - 4.5 V on all data and master-reset inputs.

V

mA
mA

(b) for the 'LS377 -ground on all data and clock-enable inputs.

SWitching Char-.cteristics
SYMBOL

PARAMETER

fMAX

Maximum Clock frequency

tpLH
tpHL
tpHL '.

VCC = 5V, TA = 25"C

....

TEST CONDITION.S .'.
(See Tell LoadIWav.forml)

LS27'3
MIN TYP MAX
30

Clock to .Output delay
Master Reset to output delay
(,LS273 only)

"

CL = 15pFRL = 2KO

..

LS377
MIN TYP MAX

UNIT

40

.~Hz

35,

40 :,.
27

27

ns

27

27

ns'

27

ns

III

SN54/74S273 SN54/74S377
Absolute Maximum Ratings
Supply voltlige VCc: ......... '.......••.... ':'.......................... : . . . . • • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V,
Input voltage ....•....•......... ,................................................................................ 5.5 V
Off-state output voltage ....., .•.....••.................•...............••...•..................................•... 5.5 V
Storage temperature range ..........•.................................•.....................•... '•... '.. -650 C to + 150" C

Operating Conditions
SYMBOL

TEST CONDITIONS

PARAMETER

VCC

Supply voltage

TA

Operating free-air temperature

tw

Width of clock

tWMR

Width of Master Reset
(,S273 only)

FIGURE

(See Interface, Test
LoadIWavelonns'

4.5

5.5

4.75

125

0

5

5.25

V

75

°C

1

7

7

ns

Low-tWMRL

2

10

10

ns

MR to CK
(,S273 only)

2

71

71

ns

3

51

51

Setup time

91

91

Hold time

Low Ci

"

2
5

7

6

8

9

13

12

14

15

17

16

18

19

10

10

20

20

30

3D

40

40

50

50

60

60

70
80

70
80

1
11
3
4

r-

EN

'f C1
10

!>

"

2
5

7

6

8

9

13

12

14

15

17

16

18

19

10

20
30
40
50
60
70
80

m

MonoIlthIoWMemories.

11-41

SN54/74LS374

SN54/74LS373
Absolute Maximum Ratings

Supply voltage Vcc ..•.••...............•.••................•.••.•••••.....•.....•....................•.....•...•. 7 V
Input voltage .......••............••..•.•..............••••.•....................•...........•.•..••.•..••••.••.•• 7 V
Off-state output voltage ...........•.•••.. . . . . . . . . . . . . . . • • . • . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . • • • . • • • • • . • • • • . • . • . • . . .. 5.5 V
Storage temperature ....•.••...•..............••.........•........•.•••••.••••.•.••.....•....•......... -65° to +150° C

Operating Conditions
MILITARY
MIN TYP MAX

PARAMETER

SYMBOL

Vcc

Supply voltage

4.5

TA

Operating free-air temperature

-55

tw

Width of Clock/Gate

tsu

Setup time

th

Hold time

5

COMMERCIAL
UNIT
MIN TYP MAX

5.5

4.75

125

a

High

15

15

Low

15

15

LS373

51

51

LS374

201

201

LS373

201

LS374

01

201
01

5.25

5

75

V
°c
ns

..

-

ns
ns

1I The arrow indicates the transition of the clock Input used for reference. 1for the low-to-high transition,l for the high-to-Iow transition.
Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL

Low-level input voltage

VIH
VIC
IlL
IIH
II

High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current

VOL

Low-level output voltage

VOH

TEST CONDITIONS

Off-state output current
10ZH

Ice

II
VI
VI
VI

= -18mA
= 0.4V
- 2.7V
=7V

VCC = MIN
VIL = MAX
VIH = 2V

IOL

= 12mA

IOL

= 24mA

Vec = MIN
VIL = MAX
VIH = 2V

IOH = -1mA

VCC
VCC
Vee
VCC

High-level output voltage

Output short-circuit current

COMMERCIAL
UNIT
MIN TYP MAX

0.7

*

Supply current

=
=
=

MIN
MAX
MAX
MAX

V

-1.5

-1.5
-0.4
20
0.1

V
V
mA
JiA
mA

-0.4

20
0.1
0.25

0.4

0.25

0.4

0.35

0.5

V
2.4

3.4

IOH = -2.6mA

VCC - MAX
VIL = MAX
VIH =2V

2.4

= 0.4V

-20

-20

JiA

Vo

= 2.7V

20

20

JiA

-130

mA

40
40

mA

-30
LS373

I

V

3.1

Vo

Vee = MAX
Vee = MAX
Outputs open

0.8
2

2

10ZL

lOS

MILITARY
MIN TYP MAX

LS374.

-130
24
27

-30
24
27

40
40

• Not more than one output should be shorted at a time and duration of the short-CIrcuit should not exceed one second.

Switching Charcteristics vcc =5 v, TA =25°C
SYMBOL

'MAX
tpLH
tpHL
tpLH
tpHL
tPZL
tpZH
tpLZ
tpHZ

11-42

PARAMETER

TEST CONDITIONS
(See Test LoadIWaveforms,

LS373
MIN TYP MAX

Maximum Clock frequency

35
12

Data to Output delay
CL = 45pF

RL = 6670

Clock/Gate to output delay,
Output Enable delay
Output Disable delay

LS374
MIN TYP MAX

CL = 5pF

RL = 6670

12
20
18
25
15
15
12

18
18
30
30

36
28
25

20

UNIT

MHz
ns

50

15
19

28
28

21
20
14
12

28
28
25

20

ns
ns
ns
ns
ns
ns
ns

SN54J'74S373

SN54J'74S374

Absolute Maximum Ratings
Supply voltage Vcc ....•................•.•...............•.....••........•.......................•............. 7.0 V
Input vOltage ........•..••......................................•............................................... 5.5 V
Off-state output voltage ........... . . • . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Storage temperature ., .. ; ......•....••... ; ..•... d •••••••••••••• , •••••.••••••••••••••••••••••••••••••••• -{)SO to +150°C

Operating Conditions
SYMBOL

PARAMETER

TEST CONDITIONS

Vcc

Supply voltage

4.5

TA

Operating free-air temperature

-55.

tw

Width of Clock/Gate

tsu

Setup time

th

Hold time

tl

5

COMMERCIAL
UNIT
MIN TYP MAX

5.5

4.75

125

0

High

6

6

Low

7.3

7.3

S373

01

01

8374

51

51

"

j

MILITARY
MIN TYP MAX

S373

101

101

S374

21

21

The arrow indicates the lransilion of Ihe clock inpul used for reference.

5

5.25
75

V
°c
ns

"

ns
ns

t for Ihe low-Ie-high transilion.l. for Ihe high-Io~low Iransilion.

Electricatl Characteristics Over Operating Conditions
~.

SYMBOL

PARAMETER

TEST. CONDITIONS

VIL

loW-level input voltage

VIH

High-level input vOltage

VIC

Input clamp voltage

Vce

IlL
IIH
II

Low-level input current
High-level input .current

VCC
VCC - MAX
VCC: MAX

Maximum input current

MIN
MAX

VOL

Low~level output ,":oltage

VOH

Highclevel output Yoliage

1·.Vec - MIN,
VIL : 0.8V
VIH : 2V

Off-state output current
10lH

0.8

V

-1.2

-12

'-0.25
50
1

-0.25
50
1

V
mA
/1 A
mA

0.5

0.5

lOS

VCC - MAX

ICC

Supply current

VCC - MAX
Outputs open

2

II - -18mA
VI : 0.5V
VI : 2.7V
VI - 5.5V
10L: 20mA

10H: -2mA

2.4

fMAX
tpLH
tpHL
tpLH
tpHL
tplL
tplH
tpLl
tpHl

PARAMETER

VO: 2.4V

:'50

50

-40
S373
S374

-100
105
90

-40

160
140

105
90

/lA

50

/1 A

-100

mA

160
140

mA

25°C
~~dlWavefQrms)

MIN

S373
TYP MAX

Maximum Clock frequency
Data to Output delay
CL: 15pF

RL = 2800

Clock/Gate to output l:ielay
Output Enable delay
Output Disable delay

3.1

":50

VO: 0.5V

TEST CONDITIONS
(See Test

V

V
2.4

* Not more than one ?utput snould be shorted at a time and duration of the short--ClrcUlt should not exceed o~e second.
Switching Characteristics Vec: 5 V, TA :

V

3.4

10H: -B.5mA

VCC - MAX
VIL : 0.8V
VIH : 2V

Output sh()rt-circuit current*

SYMBOL

COMMERCIAL
UNIT
MIN TYP MAX

0.8
2

'VCC: MIN
VIL : 0.8V
VIH : 2V

lOlL

MILITARY
MIN TYP MAX

CL: 5pF

RL: 2800

5374
MIN

TYP

75

100

MAX

UNIT
MHz
ns

7

12

7
7

12
14

8

12

18

11

17

ns
ns
ns

11

18

11

8

15

8

18
15

ns.
ns

8

12

7

12

6

9

5

9

ns
ns

15

11-43

m

SN54/74LS373 SN54/74LS374 SN54/74S373 SN54/74S374

Die Configurations
'LS374

'LS373
IQ

8Q

VCC

DE

80

80

70

7Q

7Q

6Q

6Q

60

60

50

50

4Q

lQ

OE

VCC

5Q

'S534
lQ

8Q

CK

GND

Ole Size: 76x87 mil2

'S533

OE

VCC8Q

. .....,.. . . . ./80

70

40

7Q
7Q

2Q

3Q

SQ

6Q

3D

60

60

4Q

G

GND

5Q

4Q

GND

CK

SQ

Ole Size: 63x100 mll 2

Test Load
TEST PDINT*

€I

1

"I

.of

I~

;

:~~
S2~

* the "TEST POINT" is driven by Ihe oulpul under lesl,
an~ observed by instrumentatton.

11-44

MonoIllhlcmMemor/fi.

FOR THE LS373/374
RO = 5KIl
RL' CL ARE SPECIFIED BY THE SWITCHING
CHARACTERISTICS TABLE
FOR THE LS373/374
RO = lKII
RL, C( ARE SPECIFIED BY THE SWITCHING
CHARACTERISTICS TABLE

SN54/74LS373 SN54/74LS374 SN54/74S373 SN54/74S374

'373 Timing Diagrams

'374 Timing Diagrams

E-

VT

VT

VT!'-

ClK

+-tou'" 1-"''''
Oi

JVT

------------~--~

1-1pd1

Test Waveforms
~--~i-------------3V

OUTPUT
CONTROL
(low-lIIvel
enabling)

INPUT
'----------:--oV

IN-PHASE
OUTPUT

OUT OF PHASE
OUTPUT
(See Note G)

~----3V

'--------~~--~-----oV

~-+~~-----------VOH

----f-,

'-----..;....- VOL

WAVEFORM 1
(See Note. 0)

."..----VOH
'--~~----------VOl

VT =l.5V

Propagation Delay

Enable and Disable

m

N()TES: A. CL includes probe and jig capacitance.
B. All diodes are lN9160r lN3064.
C. ForSeries54174S,RO= lK,VT= 1.5V.
For Series 54/74LS, RO = 5K. VT = 1.3 V.
D. Wavelorm lis lor an output with internal conditions such thatthe
output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such ttjat the

output is high except when disabled by the output control.
E. In the examples above, the phase relationships between inputs

and outputs have been chosen arbitrarily.
F. All input pulses are supplied by generators having the·lollowing
characteristics: PRR :5 1 MHz, ZOUT = 50iland:'
For Series 5417 4S, tR :5 2.5 ns, tF :5 2.5 ns.
For Series 54174LS and PALs, tR:5 15 ns. tF:5 6 os.
G. When measuring propagation delay times 01 ·3-stateoutpuls,
switches SI and S2 are closed.
.
.

MonolIthic

WMemories

11-45

8-Bit Register With Clock Enable and
Open-Collector Outputs
SN54/74S383
Features

Ordering Information

• 2O-Pln SKINNYDIP® Saves Space
• 8-blt data path matches byte boundaries
• Only available TTL open-collector-output register
• Ideal for certain microprocessor system buses

PART
NUMBER

PKG

TEMP

5N545383
5N745383

J,L,W
N,J

Com

POLAR- CONTROL
OPTIONS
ITY

Mil

Noninvert

POWER

Clock
Enable

5

• Suitable for pipeline data registers
• Excellent lor multiple, physlcally-separeted connections to
buses In microprocessor-based systems
• Wired-OR or wired-AND logic with outputs

Description
This 8-bit register contains 8 D-type flip-flops and features very
fast switching. The '5383 register is loaded on the rising edge
of the clock provided that the clock enable line, CK EN, is low.
Like other 8-bit interface devices, the '5383 is packaged in the
popular 2O-pin 5KINNYDIP.

Function Table '5383
INPUTS

OUTPUT

CKEN

CLOCK

DATA

Q

H

X

X
H

~

L
L

I
I

X

Lor H or!

L

L

X

00

Logic Symbol
8-Blt Register with Clock Enable
and Open-Collector Outputs
'S383

·IEEE Symbol

CKEN

CK

10
20
30
4D

50
60
70
80

1

,..

11
3

"l2C1
10

t>

0

2

4

5

7

6

8

9

13

12

14

15

17

16

18

19

'Indicates Open-Collector Output

SKINNYDIP" is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College BlVd. Ssnta Clara, CA'95054-1592 Tel: (408) 970.-9700 TWX: 910-338-2374

11·46

'S383

LG2

10
20
30
40

50
60
70

so

SN54/74S383
Absolute Maximum Ratings
Supply voltage VCC ............................................................................................. 7.0 V
Input voltage ...•....•............•......•..........................•............................'. . .. . .. . . . . . . .. 5.5 V
Off-state output voltage ....................................•......•..............................•............• " 5.5 V
Storage temperature ................................................................................... _65° to+150°C

Operating Conditions
l!
I

SYMBOL

PARAMETER

TEST CONDITIONS

FIGURE

(See Interface, Te.t

Load/Wavelormsl

MILITARY
MIN TYP MAX

COMMERCIAL
UNIT
MIN TYI',MAX

5.5

4.75

125

0

VCC

Supply voltage

4.5

TA

Operating free-air temperature

-55

tw

Width of clock

tsu

Setup time

High-tWH

1

7

5

5.25

V

75

V

7",

ns

Low-tWL
51

51

91

91

High CK EN to CK

91

91

Data input

31

31

31

31

01

01

Data inpuUo CK

th

5

Hold time

Low CK EN

to CK

2

LowCK EN to CK

2

High CKEN to CK

ns

ns

11 The arrow indicates the transition of the clock/enable input used for reference: I for the low-ta-high transition, j for the hlgh-ta-Iow transition.

Electrical Characteristics Over Operating Conditions
SYMBOL
V,L
V,H
V'C
I,L
"H

PARAMETER

TEST CONDITIONS

MILITARY
M,IN TYP MAX

Low-level input voltage
High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current

"

COMMERCIAL
UNIT
MIN TYP MAX
0.8

V

-1.2
-250
50
1

-1.2
-250
50
1

V
V
p.A.
jJ.A
mA

IOL : 24mA

0.5

0.5

V

YOH': 5.5V

250

250

p.A

Outputs HIGH
Outputs LOW

160
160

160
160

mA

0.8
2
VCC:
VCC:
VCC VCC:

MIN
MAX
MAX
MAX

VOL

Low-level output voltage

VCC: MIN
V'L :·MAX
V,H : 2V

IOH

High-level output current

Ii 'L : MAX

"
V,
V,
V,

'

2

- -18mA
- 0.5V
- 2.7V
: 5.5V

VCC: MIN
V,H,: 2V
ICC

Supply current

Vee: MAX
Outputs open

Switching Characteristics Vee: SV.,TA = 25°(:
SYMBOL
fMAX
tpLH
tpHL

PARAMETER
Maximum Clock frequency
Clock to output delay

MIN

'S383
TYP

75

110

TEST CONDiTiONS

(See t~'1 Load/WB..iorrriJl)

CL: 15 pF

RL :280!1

10
14

MAX

UNIT

17

MHz
ns

22

ns

11·47

m

SN54/74S383
Test Waveforms
DATA AND CLOCK ENABLE
SETUP AND HOLD TIMES

CLOCK PULSE WIDTH AND
CLOCK TO OUTPUT DELAYS

CK---J
CK

Q-------.......

v,. = 1.SV
Rgure2

v,. = 1.SV
Rgure 1

TestLoad

VI~!l

TEST POINT*

e-f

T-=

Cl15pi
(SEE NOTE A)

* The "TEST POINT' is driven by the output under test,
and observed by instrumentation.
lOAD CIRCUIT FOR
OPEN-COllECTOR OUTPUTS
A. Includes probe and jig capacitance, .

B.

In the examples above, the phase relationships between inputs and
outputs, have been chosen arbitrarily.

C.

All input pulses are aupplied by generators having the following
characteristics: PRR
$1 MHz, Zout = 5011 and:

For Series 54n 45, tR $2.5 ns, tF $2.5 ns.

Die Configuration
'S383
10

CKEN

VCC

so

Die Size: 58x93 mll2

aD

1D

2D

7D

20

70

3Q

so

3D

6D

4D

SD

4Q

50

GND

11·48

'CK

SN54/74S383

.i

Open Collector Bus Application Information For
Determination of AL For Wired-And Applications

1. CALCULATE RL(Mln):
.
RL(Mln)=

Vee - VOLlMax)
IOL - (TOTAL IlL)

TTL
Q~__~~+-__~__
LO~AD~~

SN54n4S383
REGISTER
OUTPUT

where IOL = 24 mA at
VoLlMax) = 0;5 V

IOL

•••

iI

•
••
•
••

OTHER
OPEN-COLLECTOR
OUTPUTS

2. CALCULATE RL(Max):
RL(Max)=

Vee -VOH(Min)
(TOTAL IOH + TOTAL IIH)

•
••

TTL
LOAD
Qr-~~1-~--~-------;

SN54n4S383
REGISTER
OUTPUT

IOH

•••

where IOH = 250 I1A at
VOH(Min) = 2.5V

•
••
•
••

OTHER
OPEN-COLLECTOR
OUTPUTS

•
•

III

1.5

3. SELECT a value for RL in the rangeOfRL(Min) to RL(Max),
based on power consumption and speed requirements:
1:0
/::,. -TPLH

o

-TPHL

vcc = 5.0 V
TA

10

.•

12

14

Tp(n.,

16

RL VI. Tp FOR sN54n4S383

=25·C

18

20

8·Bit Latches, S'·Bit Registers
with Inverting Outputs.
SN54/74LS533 SN54/74S533
SN54/74LS534 SN54/74S534
F..tu ..../Ben.flts

Ordering Information

• inverting outputs

PART
NUMBER

• Three-state outputs drive bus lines
• 2O-pln SKINNYDIP'8 saves space

PKG TEMP POLARITY
J,W,L
N,J

• Low current PNP Inputs reduce loading

548533
745533

Mil
.Com
J,W,L Mil
Com
N,J
J,W,L Mil
N,J
Com

• Ideal for microprocessor Interface

548534
748534

J,W,L
N,J

54LS533
74LS533

• 8-b" data path matches byte boundaries

54LS534
74LS534

• HysteresiS Improves noise margin

• Pln-compatlble with SN54174LS37314 or SN54n4S37314 can be direct replacement when bus polarity must be changed

Description

TYPE

POWER

Latch
LS
Register
Invert
Latch
S

Mil
Com

Register

when the gate (G) goes low. The register loads eight bits of input
data and passes it to the output on the "rising edge" of the clock,

In addition to the standard Sand LS latches and registers,
Monolithic Memories provides inverting outputs instead of noninverting outputs, The inverting outputs are intended for bus
applications that require inversion as in interfacing the Am2901 A
4-bit slice to an assertive-low bus.

The three-state outputs are active when DE is low, and highimpedance when DE is high, Schmitt-trigger buffers at the
gate/clock inputs improve system noise margin by providing
typically 400 mV of hysteresis.

The latch passes· eight bits of data from the inputs (0) to the
outPl,lts (0) when the gate (G) is high. The data is "latched"

All of the 8-bit devices are packaged in the popular 20-pin
SKINNYOIP.

Function Tabl••
'533 8-Blt Latch (Inverting)

'534 8-Bit Register (Inverting)

OE

G

0

Q

OE

CK

0

Q

L
L
L
H

H
H
L

H
L

L
H
00

L
L
L

t
t

H

H

L

Lor H or j

L
00

Z

H

X

X
X

X

X
X

Z

Logic Symbol.
'533 8-Blt Latch (Inverting)

SKINNYDIP-!t is a registered trademark of Monolithic Memories.

'533 8-Bit Register (Inverting)

Monol't'o m'.

TWX: 910c338-231e..
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338~2374 • •mD~..

ii-50

SN54/74LS533 SN54/74LS534 SN54/74S533 SN54/74S534

IEEE Symbols

DE

G
10

20
30
40
50
60
70
BO

1
11
3

r--- EN

'5533

'5534

=F G1
10

I>

V

1

CK

11

2

10

10

2Q

20

4

"-

5

7

---.,

6

3Q

B

......

9

4Q

13

DE

12

30
40

SCi

50

---.,

15

50

60

17

.....,

16

7Q

70

1B

......

19

so

14

,

BO

3

r--

.,1:0EN

10

C1

I>

2

v

5

B

r--.
r-..
r--.

13

r---

12

4
7

14

6
9

15

17

h

16

1B

r--.

19

1Q

2Q
3Q

4Q

5Q
6Q
7Q
BQ

m

Monolithic

m

Memories

ii-51

SN54/74LS533 SN54/74LS534
Absolute Maximum Ratings
Supply voltage VCC ............................................................................................... 7 V
Input voltage .•...•...................•.......•....•....................•.....••................•...........•..•.• 7 V
Off-state output voltage .. . . . . . . . . . . . . . . • . . . . . . . . . . • . . . . . . . . . . • . . . . . . . . . . • . • . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Storage temperature ................................................................................... -65. to +150· C

Operating Conditions
MILITARY
MIN TYP MAX

PARAMETER

SYMBOL
Vee

Supply voltage

4.5

TA

Operating free-air temperature

-55

tw

Width of Clock/Gate

tsu

Setup time

th

Hold time

5

COMMERCIAL
UNIT
MIN TYP MAX

5.5

4.75

125

0

High

15

15

low

15

15

lS533

31

31

lS534

201

201

lS533

101

101

LS534

01

01

tiThe arrow indicatea the transition of the clocklenable input used for reierence. t for the low-to-high transition,

5

5.25
75

V
·e
ns
ns
ns

1 for the high-ta-Iow transition,

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

Vil

Low-level input voltage

VIH

High-level input voltage

VIC

Input clamp voltage

III
IIH
II

low-level input current
High-level input current

VOL

VOH

TEST CONDITIONS

= -18mA
- O.4V
- 2.7V

Maximum input current

II
VI
VI
VI
IOl

= 12mA

low-level output voltage

Vee - MIN
Vil = MAX

IOl

= 24mA

High-level output voltage

VIH = 2V
Vee = MIN
Vil = MAX

Off-state output current

VIH = 2V
Vee = MAX
Vil = MAX

lOS

Output short~ircuit current ...

ICC

Supply current

10ZH

COMMERCIAL
UNIT
MIN TYP MAX

0,7

0.8

V

-1.5

-1.5

-0.4
20
0.1

-0.4
20
0.1

V
mA
I1A
mA

V

2

2
Vce = MIN
Vee = MAX
Vee = MAX
Vee = MAX

10Zl

MILITARY
MIN TYP MAX

=7V
0.25

0.4

0.25

0.4

0.35

0.5

V
IOH = -lmA

2.4

3.4
V

IOH = -2.6mA
Vo

= O.4V

VIH = 2V
Vec = MAX

Vo

= 2.7V

Vee = MAX
Outputs open

lS533
lS534

2.4

3.1

-20
20
-130

-30

36
27

*Not more than one output should be shorted at a time and duration of the short-CIrcUit should not exceed one second.

-30

48
48

36
27

I1A

20

I1A

-130

mA

48

mA

48

Switching Characteristics VCC = 5 V, TA = 25·C
SYMBOL
fMAX
tpLH
tpHL
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ

11·52

PARAMETER

TEST CONDITIONS
(See Tes' LoadlWavelorms)

LS533
MIN

TYP

LS534
MAX MIN

Maximum Clock frequency

35

20

25
25
35

18

35

25

36
30
29

17

Data to Output delay

12
el = 45pF

RL = 6670

Clock/Gate to output delay.
Output Enable delay
Output Disable delay

17
CL = 5pF

RL= 6670

18
16

24

TYP

MAX

50

UNIT
MHz
ns
ns

19
15
21

20
18
16

30
30

30
30
29
24

ns
ns
ns
ns
ns
ns

SN54.174S533

SN54.174S534

Absolute Maximum Ratings
Supply voltage Vcc .........•..................................................................................... 7 V
Input voltage ...•............................................................................................... 5.5 V
Off-state output voltage ........................ ;................................................................. 5.5 V
Storage temperature .................•................................................................. -650 to +150°C
I

Operating Conditions

I

tl

MILITARY
MIN TYP MAX

PARAMETER

SYMBOL
VCC

Supply voltage

4.5

TA

Operating free-air temperature

-55

tw

Width of Clock/Gate

tsu

Setup time

th

Hold time

5

COMMERCIAL
UNIT
MIN TYP MAX

5.5

4.75

125

0

5

5.25

V

75

°e

High

6

Low

7.3

6
7.3

ns

S533

01

01

ns

S534
. S533

51

51

101

101

51

51

S534

ns

t for the low-ta-high transition, l for the high-ta-Iow transition.

The arrow indicates the transition of the clock/enable input used for reference.

Electrical Characteristics Over Operating Conditions
SYMBOL

I

TEST CONDITIONS

PARAMETER

VIL
VIH
VIC
IlL
IIH
II

Low-level input voltage

VOL

Low-level output VOltage

VOH

High-level output voltage

VCC = MIN.
Vec - MAX.
Vce - MAX.
Vec = MAX,
Vec = MIN,
VIL = 0.8V,
VIH = 2V
Vec - MIN,
VIL = 0.8V,
Vec

10ZL
Off-state output. current
10ZH

*

lee

Supply current

*

VIL
VIH
Vcc

II
VI
VI
VI

- -18mA
= 0.5V
= 2.7V
- 5.5V

10L

= 20mA

10H

= 2V
= MAX,
= 0.8V,
= 2V
= MAX
= MAX,

10H
Va
Va

= -2mA
= -6.5mA
= 0.5V
= 2.4V

.

-1.2
-0.25
50
1

-1.2
-0.25

0.5

0.5

.
2.4

50
1

V
V
V
mA
/lA
mA
V

3.4
V
2.4

3.1
-50

-50
50

-40

-100
105
90

8533
8534

Vee
Outputs open

0.8
2

2

VIH

Output short-circuit current

COMMERCIAL
UNIT
MIN TYP MAX

0.8

High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current

lOS

MILITARY
MIN TYP MAX

-40

160

105
90

140

/lA

50

/lA

-100

mA

160
140

mA

Not more than one output.should be shorted at a time and duration of the short-CIrcuit should not exceed one second.

Switching Characteristics VCC =5 V, TA =25°C
SYMBOL
fMAX
tpLH
tpHL
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ

PARAMETER

TEST CONDITIONS
(See Test Load/Waveforms)

MIN

5533
TYP MAX

Maximum elock frequency

75

9

Data to Output delay
eL = 15pF

RL = 2800

Clock/Gate to output delay
Output Enable delay
Output Disable delay

MIN

eL

= 5pF

Monolithic

RL

= 2800

IRE] Memories

5
12
7
11
8
8
6

S534
UNIT
TYP MAX
100

MHz
ns

18
16
22
20
20
17
16
13

11
8
11
8
7
5

20
18

20
17
16
13

ns
ns
ns
ns
ns
ns
ns

11·53

OJ

SN54/74LS533 SN54/74LS534 SN54/74S533 SN54/74S534
Die Configurations
'LS533

'LS534
vee

10

80

80

80

70

70

70

70

60

60

60

60

50

50

40

GNO

Die Size: 76x87 mil2
10

DE

vee

10

80

. .. . ,. . .~/80

30

DE

vee

80

20
20

70

20

50

10

70

40

eK

'S534

'S533

60
30

3D

3D

60

40
40

GNO

G

50

40

Die Size: 63x100 mil2

11-54

Mono/ithicW Memories

GNO

eK

50

SN54/74S533 SN54/74S534
Test Waveforms
°i

°i

-;f- VT

VT

ClK

VT
-'au" _th_

OJ

Qi

--------------4----J

){VT

-!pd-=-!.
lIT = 1.3V

~--~_+---------------3V

OUTPUT
CONTROL
(low-level
enabling)

INPUT
'-------------oV

IN-PHASE
OUTPUT _ _ _ _ j - - '

'-----------~,~----------oV

~_+~~-----------VOH

WAVEFORM 1
(See Note 0)

'--------VOL

OUT OF PHASE
OUTPUT
(See Note G)

~-------3V

~----VOH

WAVEFORM 2
(See Note 0) S1 open S2 closed

'---~~---------VOL

VT = 1.3V

Propagation Delay

1.SV

Enable and Disable

Test Load
TESTPOINT*

Cl
(SEE NOTE A)

*

I

RO
1K

III

The '"TEST POINT' is driven by the output under test.
and observed py instrumentation.

NOTES: A. CL includes probe and jig capacitance.
B. All diodes are lN916 or lN3064.
C. For Series 54n4S. RO = 1K. VT = 1.5 V.
For Series 54n4LS. RO = 5K. VT = 1.3 V.
O. Waveform 1 is foran output with internal conditions such that the
output is low except when disabled by the output control.
Waveform 2 is for an output with interna"! conditions such that the
output is high except when disabled by the output control.
E. In the examples above', the phase- relationships between inputs
and outputs have been chosen arbitrarily.

F. All input pulses are supplied by generators having the following
characteristics: PRR ,;; 1 MHz. ZOUT = 500and:
For Series 54n4S. tR ,;; 2.5 ns. tF';; 2.5 ns.
For Series 54n4LS and PALs. tR';; 15 ns. tF';; 6 ns.
G. When measuring prOpagation 'delay times of 3-state outputs.
switches SI and S2 are closed.

MonoIlthlo

W Memories

11';55

a-Bit Latch, a-Bit Register
with 32 mA Outputs
SN74S531 SN74S532
Ordering Information

F..tu ..../Ben.flt.
• High drive capablllty.(IOL = 32 mAl
• Three-state outputs drive bus lines

PART
NUMBER

PKG

SN74S531

N,J

com

SN74S532

N,J

com

TEMP POLARITY

TYPE

POWER

• 2O-pln SKINNYDIP® saves space
• 8-blt data path matches byte bou.ndarles
• Hysteresis Improves noise margin

Noninvert

Latch
S
Register

• Low current PNP Inputs reduce loading
• Ideal for microprocessor Interface

Description

The latch passes eight bits of data from the inputs (D) to the
outputs (a) when the gate (G) is high. The data is "latched"
when the gate (G) goes low. The register loads eight bits of input
data and passes it to the output on the riSing edge of the clock.

In addition to the standard S and LS latches and registers,
Monolithic Memories provides increased output sink current
(loll from the standard Schottky IOL of 20 mA to an improved 32
mA.

The three-state outputs are active when OE is low, and highimpedance when OE is high. Schmitt-trigger buffers at the
gate/clock inputs improve system noise margin by providing
typically 400 mV of hysteresis.

The higher IOL is intended for upgrading systems which presently satiSfy 32-mA requirements with the SN54174365A1366A1
367Al368A hex buffers.

All of the 8-bit devices are packaged in the popular 2o-pin
SKINNYDIP®.

• Pin-compatible with SN74S373/4 - can be a direct
replacement when high drive capability is required

Function Tables
'S531 8-Blt Latch
OE

G

L
L
L
H

H
H
L

X

D

'8532 8-Blt Register
Q

H
L

H
L

X
X

00
Z

OE

CK

L
L
L
H

D

Q

I
I

H
L

H
L

Lor Hor!

X
X

00

X

Logic Symbol.
'S532 8-Bit Register

'S531 8-Bit Latch

SKINNYDIP" is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Sanla Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910~338-2374

11-56

.

Z

SN54/74LS531

SN54/74LS532

IEEE Symbols

'S532

'S531

6E
G

10
20
3D

40
50
60
70
80

1

....

11

6E

EN

.,-

I~G1

3

10

CK

[>

2

V

4

5

7

6

8

9

13

12

14

15

17

16

18

19

10

10

20

20

30

3D

40

40

50

50

60

60

70

70

80

80

1
11
3

t-

EN

of C1
10

[>

V

2

4

5

7

6

8

9

13

12

14

15

17

16

18

19

10
20
30
40
50
60
70
80

Die Configurations
'S532

'S531
10

OE

vce

80

10 .....~"_._

40

GNO

G

50

Die Size: 63x100 mil 2

Die Size: 66x106 mil 2

Monolithic

W Memories

11·57

sN74s531

sN74s532

Absolute Maximum Ratings

~U:~I~~~~~~e.~?~.:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::. ·5.~ ~
Off-state output voltage •...••.....••..................... . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Storage temperature ................................................................................... -65° to +150o e

Operating Conditions
PARAMETER

SYMBOL

II

MIN

COMMERCIAL
TYP

MAX

5

5.25

V

75

°C

Vee

Supply voltage

4.75

TA

Operating free air temperature

0

tw

Width of· Clock/Enable

tsu

Setup time

th

Hold time

High

6

Low

7.3

6

S531

01

01

Sf

5f

S531

101

101

S532

2f

2f

I

ns

7.3

S532

The arrow indicates the transition of the clock/enable input used for reference.

UNIT

ns
ns

for the low-to-high transition. I for the high-to-low transition.

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

TEST CONDITIONS

VIL
VIH
Vie
IlL
IIH
II

Low-level input voltage

VOL

Low-level output voltage

VIL = O.av,
VIH = 2V
VCC - MIN,

10L

= 32mA

VOH

High-level output voltage

VIL
VIH

= O.av,
= 2V

10H

= -6.5mA

2
II = -18mA
VI - 0.5V
VI - 2.7V
VI - 5.5V

Vec - MIN,
VCC = MAX,
Vee = MAX,
VCC = MAX,
Vec = MIN,

.

Vec - MAX,

10ZL
Off-state output current
10ZH
Output short-circuit current

ICC

·Supply. cLirrent

MAX
0.8

High-level input voltage
Input clamp voltage
Low-level input current
High-level input current
Maximum input current

lOS

COMMERCIAL
TYP

MIN

*

VIL
VIH
,VCC

Vo

2.4

3.1

105
90

8532

short~lrcUit

V
V
V
mA
J1A
mA
V

V

-40
8531

VCC= MAX,
OLitputs open

*Nol more than one output should be shorted at a time and duration of the

0.5

= 0.5V
= 2.4V

Vo

= O.av,
= 2V
= MAX,

-1.2
-0.25
50
1

UNIT

-50

J1A

50

J1A

-100
160
. 140

mA
mA

should not exceed one secpnd.

Switching Characteristics VCC = 5 V, TA = 25°C
SYMBOL
'MAX
tpLH
tpHL
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ

11·58

PARAMETER.

8531

TEST CONDITIONS
(See Telt Load/Waveforms)

MIN

TVP

8532
MAX MIN

Maximum Cloc.k frequency

75

Data to Output delay
CL = 15pF

RL

= 280.0

Clock/Gate to output delay
Output Enable delay
Output Disable delay

CL = 5pF

RL

= 280.0

7
7
7
12
11
8
8
6

12
12
14
18
18
15
12
9

TVP

MAX

100

8
11
11
8
7
5

UNIT
MHz
ns

15
17
18
15
12
9

ns
ns
ns
ns
ns
ns
ns

5N745531

5N745532

'5531 Timing Diagrams

'5532 Timing Diagrams
01

°i

ClK

Oi

G-O

0-0

Test Load
TESTPOINT*

Ct

RO

(SEE NOTE AI(SEE NOTE C)

'-------+---

Vr--

4

2

10

10

5

2Q

20

3Q

30

1

EN

11
f"C1
3

10

I>

4

I

30
40
50
60
70
80

7

6

8

9

4Q

40

13

12

50

50

14

15

so

60

17

16

7Q

70

18

19

so

80

7

v r--..

2

r-r--..

5

8

6
9

r--..
r--..

12

14
17

r--

16

18

r--

19

13

15

Die Configurations
'5535

'5536

III

Die Size: 61x112 mil2

Die Size: 66xl06 mil2

Monolithio

W Memories

11·61

SN74S535

8N74S538

Absolute Maximum Ratings
Supply voltage Vcc .........•....•...•.....•..............•.....•....•..•........••....•.....•. , •.........•...•... 7 V
Input voltage ...............................•....•....•...•....••......................•...•....•••.......•..... 5.5 V
Off-State output voltage ... . . . . . . . • . . . . . . . . . . . . . . . . . . . . . • • • . . • • • . • . • . . . • . . . . . . . . . • . . • . • . . . . . . • . • . . . . . . . . . • • . . . . . .. 5.5 V
Storage temperature •.........•...••..••......•.....................•.....................•.......•.... -650 to +150°C

Operating Conditions
MIN

COMMERCIAL
TYP

MAX

Supply voltage

4.75

5

5.25

V

Operating free air temperature

0

75

°C

PARAMETER

SYMBOL
VCC
TA
tw

Width of Clock/Enable

tsu

Setup time

th

Hold time

6

low

7.3

S535

6

ns

7.3

01

01

5f

5f

S535

101

101

S536

5f

2f

-

S536

Electrical Maximum Ratings
SYMBOL

High

ns
ns

OVer Operating Condilions

PARAMETER

TEST CONDITIONS

COMMERCIAL
TYP

MIN

MAX

low-level input voltage

Vil
VIH
VIC
IlL
IIH
II

High-level input voltage
Input clamp voltage
low-level input current
High-level input current
Maximum input current

Val

low-level output voitage

VOH

High-level output voltage

,

lOll
Off-state output current
10lH

UNIT

0.8
2
MIN
MAX
MAX
MAX

-

-18mA
0.5V
2.7V
5.5V

VCC
VCC
Vee
VCC

=
-

VCC
Vil
VIH
VCC
Vil
VIH

= MIN
= O.EN
= 2V

10L = 32mA

= MAX
= O.EN
= 2V

10H = -6.5mA

VCC = MIN.
. Vil = O.EN
ViH = 2V

lOS

'output short:cireuit c~.rrent*

Vec

ICC

-$upply current

VCC = MAX
Outputs open

II
VI
VI
VI

-1.2
-0.25
50
1
0.5

2.4

3.1

-50

Va = 2.4V
-:40
'"

105
'90

"

8536

V
V
V
mA
pA
mA
V

V

Va = 0.5V

S535

UNIT

pA

50

pA

-100
160
140

mA
mA

*Not more than one output Should be shorted at a time and.duratlon of the short-CIrcuIt should not exceed one.second.

Switching CharCterlstics vcc '" 5V, T A
-SYMBOL

PARAMETER
,

fMAX
tpLH
tpHL
tpLH
tpHL
tplL
tplH
tpLl
tpHl

11·82

'

= 25°C

,"

TEST CONDITIONS
(See Test LoadlWaveforms)

5535
MIN

JYP

MAX MIN

MaxiJ1ium CloCk frequencY.,

75

9

O~tatoOutput delay,'.
Cl = 15pF

Rl = 2800

Clock/Enable to ou!put delay
Output Enable delay
Output Disable delay

Cl = 5pF

Rl = 2800

5 "
12
7
11
8
8
6

18
16
22"
20
20

17
16
13

S536
TYP MAX
100

MHz
ns

"

.'

11
8
11
8
7
5

UNIT

20
18
20
17
16
13

ns
ns
ns
ns
ns
ns
ns

5535/536
'5535 Timing Diagrams

'5536 Timing Diagrams

°i

°i

~

VT-;I;-

ClK

VT

VTjrI-Isu - I-Ih-

OJ

~T

°i

--------------4----J

I-tpd

VT = 1.3V

Test Load
Rl
TESTPOINT*

Sl
Cl

o--NV--QSV

RO

(SEE NOTE AI(SEE NOTE C) ' - - - - - -.....-<1"

*

The "TEST POINT" is driven by the output under test,
and observed by instrumentation.

Test Waveforms
~

____~--------------- 3V

,_----3V

OUTPUT
CONTROL

INPUT
'---------~---OV

(Low~level

enabling)

IN-PHASE
OUTPUT ________~-'

OUT OF PHASE
OUTPUT
(See Note G)

'-----VOl

WAVEFORM 1
(See Note 0)

~------VOH

1.SV
'-----~-------------VOl

Enable and Disable

Propagation Delay

NOTES: A. CL includes probe and jig capacitance.

B. All diodes are lN916 or lN3064.
C. For Series 54n4S, RO = lK, VT = 1.5 V.
D. Waveform 115 for an output with internal conditions such that the
oUfput is low except when disabled by the output controL
Waveform 2 is for an output with internal conditions such that the
output is high except when disabled by the output control.

E. In ,the examples' above, the phase relationships between inputs
and outputs have been chosen arbitrarily.

F. All input pulses are supplied by generators having the following

characteristics: PRR'; 1 MHz, ZOUT = 50fland:
For Series 54/745, tR'; 2.5 ns, IF'; 2.5 ns.
For Series 54n4lS and PALs, IR'; 15 ns. IF'; 6 ns.
G. When measuring propagation delay times of 3-state outputs,
switches 81 and 82 are closed.

Monolithic

m

Memories

11-63

ID

8-Bit Dynamic-RAM Drivers
with Three-State Outputs
SN54/74S700/-1
SN54/74S731/-1

Ordering Information

Features/Benefits:
Large capacitive drive capability
Symmetric rise and fall times due to balanced output impedance
Glitch-free outputs at power-up and power-down
20-pin SKINNYDIP® saves space
8-bit data path matches byte boundaries
'S730/734 are exact replacement for the Am2965/66
'S700/730/731/734are pin-compatiblewith 'S210/240/241/244,
and can replace them in many applications
• 'S700-1/730-1/731-1/734-1 have a larger resistor in the output
stage for better undershoot protection
•
•
•
•
•
•
•

• Commercial devices are specified at VCC±10%.

Description:
The 'S700, 'S730, 'S731, and 'S734 are buffers that can drive
multiple address and control lines of MOS dynamic RAMs. The
'S700 and 'S730 are inverting drivers and the 'S731 and 'S734
are non-inverting drivers. The 'S7001731 are pin-compatible
with the 'S21 0/241 and have complementary enables. The 'S730
is pin-compatible with the 'S240 and an exact replacement for
the Am2965. The 'S734 is pin-compatible with the 'S244 and an
exact replacement for the Am2966.
These devices have been d'esigned with an additional internal
resistor in the lower output driver transistor circuit, unlike regular
8-bit buffers. This resistor serves two purposes: it causes a
slower fail time for a high-to-Iow transition, and it limits the
undershoot without the use of an external series resistor.
The 'S700, 'S730, 'S731 , and 'S734 have been designed to drive
the highly-capacitive input lines of dynamic RAMs. The drivers
provide a guaranteed VOH of VCC - 1.15 volts, limit undershoot

'S7oo/-1

'S730 (Am2965)
'S730-1

PART NUMBER PKG TEMP ENABLE POLARITY POWER
SN548700/-1

J,W,L

Mil

8N7487001-1

N,J

Com

8N5487301-1

J,W,L

Mil

8N7487301-1

N,J

Com

8N548731/-1

J,W,L

Mil

8N748731/-1

N,J

Com

8N548734/-1

J,W,L

Mil

8N748734/-1

N,J

Com

HighLow
Invert
Low
8
HighLow

NonInvert

Low

to 0.5V, and exhibit a rise time symmetrical to their fall time by
having balanced outputs. These features enhance dynamic
RAM performance.
For a better-controlled undershoot for lightly capacitive-loaded
circuits the '8700-1, '8730-1, '8731-1 and '8734-1 provide a
larger resistor in the lower output stage. Also an improved
undershoot volatge of -0.3 V is provided in the '8700-1 series.
A typical fully-loaded-board dynamic-RAM array consists ~
banks of dynamic-RAM memory. Each bank has its own RAS
and CAS, but has identical address lines. The RAS and CAS
inputs to the array can come from one driver, reducing the skew
between the RAS and CAS signals. Also, only one driver is
needed to drive eight address lines of a dynamic RAM. ThEj
propagation delays are specified for 50pf and 500p! loaq
capacitances, and the commercial-range specifications are extended
to VCC ± 10%.
All of the octal devices are packaged in the popular 20-pin
SKINNYDIP'".

'S731/-1

SKINNYDIP-..iW:1< CONFIGURA1"ION

-+----r--

IL _ _ _ _ _ _ _ _ _I .

CONTROLS

>DATA

8

Figure 2. The 546/547/566/567 Block Diagram

Two more families of back-to-back parts also. come in the
same pineut: the 'LS646/7/8/9 family, and the 'LS651/2/3/4
family. These differ frem each other in enable structure; the
'LS646 et. al. have a "direction-centrel line" so. that yeu
can't perferm certain eperatiens en beth sides efthe part
simultaneeusly, .whereas the 'LS651 et. al. have generally
independent eperatiens en beth sides. In each ef these
families there are two. nen-inverting parts and two. inverting
parts; in each case, there is a three-state part and an
epen-cellecter part. All ef the parts from beth families are
cemprised ef "frent-Ieading-Iatch" individual elements (see

12;'4

Figure 3); a front-loading latch is an edge-triggered flipflop in
parallel with a buffer, so that the data can be piped through the
buffer to. reach the eutput rapidly and then can besubsequently
recorded in the flipflop. It is also pessible, in a front-Ieadinglatch structure, to pipe data temporarily around the flipflep to the
output witheut ever recording it in the flipflop, The 'LS646/718/9
feature hysteresis on their data inputs as well as en their control
inputs, which makes them function well in high-noise environments. The 'LS653/4 are open-cellector in ene direction, but
three-state in the other directien.

Figure 3. The '646-SeriesI'651-Series Block Diagram

MonollthleW Memories

Small but Mighty; New Components Give You More Logic in Less Chips

Then there are two "readback" parts, which consists of a
latch or register back-to-back with a buffer: the 'LS793
readback latch, and the 'LS794 read back register. Both of
these are just 20-pin, and hence offer a full 2:1 saving in
board area as well as in parts count. They have structured
pinouts compatible with those of the 'LS573 and 'LS574, but
a very different internal architectun:l; each of the 8 elements
(latch or flipflop) has 2 outputs, one of which is totem-pole
and goes to the presumed "output pin" of that element, and
the other of which is three-state and goes back to the "input
pin" for the element (see Figure 4). Thus, it is possible to
read the contents of an 'LS793 or 'LS794 from its input lines
by enabling its three-state outputs.

r-----------l

CLOCK GATE /

DATA "78 •

I

~'

II 78/

, L_____ _____ J
OE

Figure 4. Th" '793/'794 Block Diagram

The 'LS793 and 'LS794 are intended for use' in decentralized
systems; fofinstanceindustrial-controlsystems in which a
large number of slowly-changing setpoints and displays are
under' the control of a central microprocessor. The readback
feature permits reading one of these, updating it, and
replacing it. Without the readbac;:k feature, the system would
, have to keep a redundant copy of the setpoint or display
value in main memory, which could cause additiona'i system
overhead due to the time-slicing of the microprocessor's
activities, or even due to virtual-memory page-faulting in
larger systems. Moreover. there is the reliability issue of
whether the alleged redunpant cOpy always agrees exactly
with the real thing out there' in the register controlling the
actuator or the display, and what happens whenever it doesn't.

Although they are not brand-new parts, it should also be
mentioned that the 'LS245 and 'LS640/1/2/3/4/5 (and
their "-1" high-drive options) are likewise in principle
Double-Density PLUS" Interface parts with a back-to-back
architecture.
Table 2 is a summary of the back-to-back Double-Density
PLUS" Interface presently available from Monoiithic
Memories.
Two other common and intuitively-plausible combinations of
a couple of B-bit latches or registersl\re "nose-to-tail" (one
after the other), and "side-by-side" (alternate). If two registers
are used in a nose-to-tail cornbination, for instance, data from
the inputs enters the first register when it is clocked, and
the outputs of the first register are the, inputs of the second
register. ,and thus the same data finally 'reach the, outputs of
the combination when the second register is subsequently
clocked. And, if two registers are used in a side~by-side
combination, their inputs come from the same input bus,
and their outputs go to the same output bus, but they can
be controlled separately and the output bus can be driven
from either one.
Although the nose-to-tail configuration and the side-by-side
configuration seem quite different, with the provision of
some internal multiplexing the same Double-Density PLUS"
Interface part can satisfy both reqUirements. S,uch a part is
called a pipeline - register or hitch, as the case may be. The
internal architecture of a two-level pipeline is showh in
Figure 5.
'
"
~----'--'--:---'--,--""""'~I'

I

'

I
DATA
8

"I

8,

I'"

,

I

I

CONTROLSI

8

8

DATA

--:fI
I
L _ _ _ _ _ _ _ _ _ _ _ _ _I
Figure 5. The '548/9 Block Diagram

CONFIGURATION BUFFERS
Back~to-Back

B/UR

LATCHES

'245(244)
'547(,373)
'645/-1 ('244') '567('533)

The 'LS546, with the edge-triggered registers, and the 'LS549,
with latches, follow the Figure 5 block diagram exactly. Their
pinouts resemblethose of'LS546,'LS646, and 'LS651 families.
Their speeds are 'similar, and they also'feature 32-mA-IOL
outputs.

'546('374)
'566('534)

'646fi('374)
'646/9('534)
'65214('374
'65113('534) ,

Back-to-Back
FronhLoading
Latches
Readback BiLlA

REGISTERS

'793(,373)

Typical applications for Double-Density PLUS Interface include
computer peripherals, minicomputers; and microcomputers.
Applications for the open-collector parts are ih the telecommunication and games areas. The drive of these parts enables them
to drive heavily-loaded buses, and flat cables.

794('374)

Table 2. The Back-to-Bac* and Other Double-Density PLUS
Interface Prcducls from Monolithic Memories

Note that the bracketed part numbers ,represent the element
inside the Double-Density PLUS Interface. For example, a '245
can replace two'244s, a '547 can repll\ce two '5335, and a '546
can replace two '374s. 'The same holds true for the '646 and '651 ,
series., However. the '7931'794 are the eqLJivalent of a :373/'374
arid a readgack bllff,er such as a '244.'
'

MonolIthic

taD Memories

12-5

8-Bit Buffer Transceiver
SN54/74LS245
Features/Benefits
• Three-state outputs drive bus lines

Ordering Information
PART
NUMBER

TYPE

• Symmetric - equal driving capability In each direction

SN54LS245

J,L,W

Mil

Non-

• 20-pin SKINNYDIP® saves space

SN74LS245

N,J

Com

invert

• Low current PNP Inputs reduce loading

TEMP

POLARITY

POWER
LS

• S-blt data path matches byte boundaries
• Ideal for microprocessor interface
• Pin-compatible with SN54/74LS645 - improved speed,
IlL and IOZL specifications

Function Table

Description
These 8-bit bus transceivers are designed for asynchronous
two-way communication between data buses. The control function implementation minimizes external timing requirements.

ENABLE

The device allows data transmission from the A bus to the B bus
orfrom the B bustotheA bus depending upon the logic level at
the direction-control (DIR) input. The enable input (E) can be
used to disable the device so that the buses are effectively isolated.

L
L
H

All of the 8-bit devices are packaged in the popular 20-pin
SKINNYDIP.

DIRECTION
CONTROL
DIR

E

OPERATION
B data toA bus
A data to B bus
Isolated

L
H
X

IEEE Symbol
'LS245

Logic Symbol

E

19

DIR

1

'LS245

r-J 3EN1 (BA)

YEN2(AB)
A1

A2

A3
A4
AS

A6
A7
A8

2

L

\71

18



2\7

U

3

17

4

16

5

15

6

14

7

13

8

12

9

11

SKINNYDIP® is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Sanla Clara,CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

12·6

"G3

B1

B2
B3
B4
B5
B6
B7
B8

MonolithIc 1!T!11
MemorIes In.IlW

SN54/74LS245
Absolute Maximum Ratings
Supply voltage Vee .•.•.........•.............••..•..........•......•...•..•.•........••.••.••..•••...•......... 7.0 V
Input voltage .......•.....................•...•.......•...........••....•..•.•••.••...••.••••••..••..••...•..... 7.0 V
Off-state output voltage .....•.........•.....•. . . . . • . . • • . . • . • . . • . . . . • . . . . • • . . . . . . . . . • . • . . . . • . • . . • • • • • • . . • . . • • . . . •• 5.5 V
Storage temperature .•....••..••.•••.••••.•.•..•••.•••............•..........•..•...................... _65° to +150° e

Operating Conditions
SYMBOL
Vee
TA

MILITARY
MIN TYP MAX

PARAMETER
Supply voltage

4.5

Operating free-air temperature

-55

5

COMMERCIAL
UNIT
MIN TYP MAX

5.5

4.75

125

0

5

5.25

V

75

°e

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

V,L

Low-level input voltage

V,H

High-level input voltage

Vie
AVT

Input clamp voltage

',L

Low-level input current.
High-level input current

"H

"
VOL

Hysteresis (VT +-VT J

Maximum
input current

MILITARY
MIN TYP MAX

TEST CONDITIONS

COMMERCIAL
MIN TYP MAX
0.8

0.7
2
"

Vee·=' MIN

I AorB

Vee = MAX.

V,

Vee "MAX.

V,

Low-level output voltage

0.4

= OAV
- 2.7V

VJ

= 5.5V

V,

= 7'(N

Vec= MIN.
VIL = MAX.

'ClL

= 12mA

V,H = 2V

10L

= 24mA

Vec - MIN.

10H = :...amA
10H =-12iT)A

VCC :·MAX."

I DIR or E

-1.5

0.2

0.25

-1.5
0.2

V
V

2

= -1BmA

Vee = MIN.

A orB

UNIT

V
V

0.4

-0.2

-0.2

20

20

mA
p.A

0.1

0.1

mA

0.4

0.25

0.4

0.35

0.5

V
-

VOH

'OlL

High-level output voltage:,

V,L' '" MAX•.
V,H = '2V
Vee = MAX.
V,L = MAX.

Off-state output current

'OlH
lOS

• 'OH'

.V'H .= 2V
Vee-MAX

Output short-circuit current '"

~

Supply
Current

Outputs
Low
Outputs.
Disabled

2.4

2

2

-15mA

I
"

-200

20

-40

Vec = MAX. Outputs open

V

-200

Vo '" 2.7V .'
<

3.4

2

Vo =·O.4V

Outputs
High;
ICC

2.,4·: 3.4

-225

-40

p.A

20

p.A

-225

mA

4B

70

4B

70

62

90

62

90

64

95

64

95

mA

*Not more than one output should btl shorted at a time and duration .of the short-circuit should not exceed one second.
SwitChing Characteristics
SYMBOL
tpLH
tpHL
tplL
tplH
tpLZ
tpHl

PARAMETER

VCC = 5 V. TA = 25°C
TEST CONDITIONS
(S.e Tel' LoadIWavelorms)

Data to Output delay
eL = 45pF

RL = 6670

Output Enable delay
Output Disable delay

CL = 5pF

RL = 6670

A to B DIRECTION B to A DIRECTION
UNIT
MIN TYP MAX MIN TYP MAX
8

12

8

12

27
25

40
40

15

25

15

25

ns

8
8

12
12

ns

27

40

ns

25

40

ns

15

25

ns

15

25

ns

12-7

LS245
Die Configuration

'LS245

Die Size: 65x111 mil 2

12-8

Monollthio

m

Memories

LS245
Test Load
TEST POINT"

S1

+---.......-+......

A)I

CL
(SEE NOTE

(SEE
NOTE B)

RO
1K

*

The "TEST POINT" is driven by the output ,under test;
and observed by Instrumentation.

Test Waveforms
~--~-r-------------3V

OUTPUT
CONTROL
(Low-level
enabling)

INPUT
'-------------oV

-+_,

IN-PHASE
OUTPUT _ _ _

OUT OF PHASE
OUTPUT
(See Note G)

~----3V

'------~~~~~-----oV

~-+~~----------VOH

'--------VOL

WAVEFORM 1
(See Note 0)

~----VOH

1.5V

Propagation Delay

VT = 1.3V

Enable and Disable

NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N9160r1N3064.
C. For Series 54/74LS, RO = 5K, VT = 1.3 V.
D. Waveform 1 isforanoutputwith internal conditions such thatthe
output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the

output Is high except when disabled by the output control.
E. In the examples above, the phase relationships betweeninpuls
and outputs have been chosen arbitrarily.
F. All input pulses are supplied by generators having the following
characteristics: PRR S 1 MHz, ZOUT = 500and:
For Series 541745, tR S 2.5 ns, tF S 2.5 ns.
For Series W74LS and PALs, tR S 15 ns.tF S 6 ns.
G. When measuring propagation delay times of 3-8tate' oulputs,
switches 51 and 52 are closed.
.,

.""""""" W ""emorle.

12~9

8-Bit Buffer Transceivers
SN54/74LS645 SN74LS645-1
Features/Benefits
• Three-state outputs drive bus lines
• Low current PNP inputs reduce loading
• Symmetric - equal driving capability In each direction
• 20-pin SKINNYDIP® saves space
• B-bit data path matches byte boundaries

Ordering Information
,
PART
NUMBER
SN54LS645
SN74LS645
SN74LS645-1

TYPE

TEMP

POLARITY

POWER

J,L,W
N,J

Mil
Com
Com

NOninvert

LS

J

• Ideal for microprocessor interface
• SN74LS645-1 rated at IOL = 48 mA

Function Table

Description
· These 8-bit bus transceivers are deSigned for asynchronous
two-way communication between data buses. The control function implementation minimizes external timing requirements.
The device allows data transmission from the A bus to the B bus
orfrom the B bus to theA bus depending upon the logic level at
the direction-control (DIR) input. The enable input (E) can be
used to disable the device so that the buses are effectively isolated.
All of the 8-bit devices are packaged in the popular 20-pin
SKINNYDIP.

Logic Symbol

ENABLE

E

OPERATION

L
H
X

B data to A bus
A data to B bus
Isolated

L
L

H

IEEE Symbol

DIR
.
A1

A2
A3
A4
AS

A7

4

19

E

'LS645/645-1

2

L
3

'LS645/645-1
G3
EN1 (BA)
3EN2(AB)
V'1



2V'

18

W
17

4

16

5

15

6

14

7

13

8

12

9

11

SKINNYDIP" is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College BI.vd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX:. 91 0-338-2374

12-10

DIRECTION
CONTROL
DIR

B1

B2

B3
B4
B5
B6
B7
B8

MonolithIc IIlIn
MemorIes uun.u

SN54/74LS645

SN74LS645-1

Absolute Maximum Ratings
I

Supply voltage Vee ............................................................................................. 7.0 V
Input voltage ................................................................................................... 7.0 V
Off-state output voltage .......................................................................................... 5.5 V
Storage temperature ................................................................................... -65° to +1500 e

Operating Conditions
SYMBOL

Vee
TA

Supply voltage

4.5

Operating free-air temperature

-55

Electrical Characteristics
SYMBOL

VIL

Low-level input voltage
High-level input voltage

Vie

Input clamp voltage
Hysteresis (VT + -VT

II

Maximum
input current

II

IDIR or E

High-level output voltage

Off-state output current

10lH
Output short-circuit current

*

Vee = MAX.

VI

- O.4V

Vee - MAX,

VI

- 2.7V

VI

= 5.5V

VI

- 7V

Vee'" MAX

IOL

= 12mA

10L

- 24mA

Supply
eurrent

5

UNIT

5.25

V

75

°e

COMMERCIAL
MIN TYP MAX

0.6

Outputs
Low

0.4

0.25

" MAX,

VIH

" 2V

10H - -15mA '

Vee = MAX, '"
VIL = MAX,

Vo = O.4V

VIH= 2V

Vo = 2.7V

2.4

Vee = MAX, OutplJtsopen

Outputs
Disabled

-0.4

rnA

20

JiA

0.1

0.1

rnA

0.4

2.4

3.4

0.25

0.4

0.35

0.5

0.4

0.5

V

3.4
V

2
2

.'

-400

-400

-40

Vec- MAX

V

0.4

-0.4
20

"

VIL

V
V

-1.5
0.2

UNIT

V

-1.5

10L - 48mAt
IOH - -3niA
IbH = -12mA

Outputs
High,
lee

"

0.1

Vee = MIN,
VIL = MAX,

Low-level output voltage

,

lOS

0

2

- -18mA

Vee = MIN

IA ()r B

I

lOlL

4.75

0.5

VIH = 2V
Vee - MI,N,
VOH

5.5
125

MILITARY
MIN TYP MAX

2

J A or B

Low-level input current
High-level input current

VOL

TEST CONDITIONS

Vee = MIN,

IIH

5

COMMERCIAL
MIN TYP MAX

Over Operating Conditions

PARAMETER

VIH

IlL

MILITARY
MIN TYP MAX

PARAMETER

JiA

20

20

JiA

-225

-225

rnA

-40

48

70

48

70

62

90

62

90

64

95

64

95

rnA

* Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
tThis specification applies only to the SN74LS645-1.

Switching Characteristics
SYMBOL

tpLH
tpHL
tplL
tplH
tpLZ
tpHl

PARAMETER

VCC

=5 V, TA =25°C
TEST CONDITIONS
(See Test Load/Waveforms)

Data to Output delay
CL = 45pF

RL = 6670

Output Enable delay
Output Disable delay

CL = 5pF

MonoIHhIO

RL = 6670

W lIIIemories

A TO B DIRECTION B, TO A DIRECTION
UNIT
MIN TYP MAX MIN TYP MAX

15
15

ns
ns

26

40
40

25

15

25

ns

25

15

25

ns

8

15

8

11

15

31

26

40
40

11
31

15
15

ns
ns

12-11

LS845,LS845-1
Die Configuration

'LS645, 'LS645-1

Die Size: 65li111 mH2

12-12

TestLoad
'rEST POINT*
I

• The "TEST POINT" is driven by Ihe oulpul under lesl.
and observed by instrumentation.
.

Test ;Wavefonn8
3V

3V

OUTPUT
CONTROL
(Low-level
enabling)

OV

OV

VOH

IN.-PHA$E
OUTPUT __~~~__,

VOL

WAVEFORM 1
(See Note D)

OUT OF PHAsE
OUTPUT
($ee Note G)

Ena,ble,ancf Disable"

Propagation Delay

NOTES: A. CL includes probe and jig capacilance.
B. All diodes are 1N916 or 1N3064.
C. For Series 54174LS. RO ; 5K. VT

o.

=1.3 V.

Waveform 1'i~fO~ ,8:n outputWi~'h inter'1'al co~djUons su.ch that the
outpul is low excepl when disabled by Ihe OiJlpui control.
.
Waveform 2 isfor an oulputwith inlern.lcondition~ such \hatthe
outpul is high except when disabled by the output conlrol.

E. In the examples above, the phase relationships between inputs
and outputs have been chosen arbitrarily.

F. All inpul pulses are supplied by generatQrshavinglhe following

s

characleristics:. PRR 1 MHz. ZOUT = seiland'
For Series 541745. tR:5 2.5 ns. tF:5 2.5 ns.
For Series 54174LS and PALs. tRS 15 ns. tF:5 6 ns.
G. When measuring propagation delay' limes of 3-state oulpuls;
swilches 51 and $2 are closed.
.

MonoIIthIo IUD Memories

12;'13

8 -Bit B~~,~.egis.J_rTran~ei~e~s
and Latch Transceivers
SN54/74LS546 SN54/74LS547
SN54/74LS566 SN54/74LS567
Features/Benefits

DeScription

• Bidirectional transceivers utilizing registers or latclles

Th~l!B devices are comprised

• Faster than other LS-TTL reglstersllatches

of a pai r of 8-bit registers (,LS546,
'LS566l, ora pair of 8-bit latches (,LS547, 'LS567).

OEBA.

• Independent reglstersllatches for A bus and B bus
• Data can be swapped between internal reglstersllatches
• 8-blt data paths match byte boundaries
• 'LS546/547/566/567 can replace two 'LS374/373/534/533
devices
• Independent clock/gate enables for rank A and rank B
• High drive capability: IOL = 32 mA (COM), 24 mA (MIL)
• 24-pin SKINNYDIP® saves space
• Three-state outputs drive bus lines
• The clock. clock-enable, and latch-enable Inputs typically
have 300 mY hysteresis

There are independent'clock and.clock e'lable controls for the
two directions namely CKA, CKB,CKEA, CKEB for 'LS54W
'LS566, and independent gate enable control GAl, GA2, GBl
and GB2 for 'LS547/'LS567. The CKAIB and CKEAlB can control the internal registers AiB to load data or hold data. Similarly,
the GAl, GA2, GBl and GB2 can govern the internal latches,
AlB to pass or hold data.

The direction of operation is controlled by OEAB and
When OEAB is Low and OEBA is High, the operation of the
, registers/latches is A-to-B direction; when OEAB is High and
OEBA is low, the operation of the registers/latches is B-to-A
direction; when OEAB and OEBA both are High, the A, B buses
both are inputs, data will be stored into registers/latches; when
OEAB and OEBA both are Low, the A,S'buseS'both are ouiputs,
data will transfer from internal registers/latches to A, B buses.
There are independent clock and clock enable controls for the
two directions: namely CKA, CKB, CKEA and' CKEB for
'LS5461'LS566, and independent gate enable control GAl, GA2,
GBl and GB2 for 'LS547I'LS567. The CKAIB and CKEATs can
control the internal ~ters AlB to load data or hold data.
Similarly, the GAl, GA2, GBl and GS2 govern the internal
latches, AlB to pass or hold data ..
The 'LS5461'547 provide non-inverting polarity; the 'LS566I'LS567
provide inverting polarity. The 'LS5461'LS547I'LS566/'LS567 all
have3-stateoutputs, and have 32-mA output drive IOL (COM)
over the commercial temperature range and 24-mA output drive
IOL (MIL), over the military temperature range.
All of the devices are packaged in the popular 24-pin SKINNYDIP package.

Ordering Information
PART NUMBER

PACKAGE

TEMPERATURE

SN54LS546

JS,W,L

Mil

SN74LS546

NS,JS

Com

POLARITY

TYPE

POWER

Register

SN54LS547

JS,W,L

Mil

SN74LS547

NS,JS

Com

SN54LS566

JS,W,L

Mil

Non-invert
Latch
LS
Register

SN74LS566

NS,JS·

Com

SN54LS567

JS,W,L

Mil

SN74LS567

NS,JS

Com

Invert
Latch

NOTE: L package here is L28. The other packages are 24-pin.

SKINNYDIP<,!!) is a registered trademark of Monolithic Memories..

TWX: 910-338-2376
2175 Mission College8Ivct;.Santa Clara, CA 95054-1592 'TlIl: (408)970-9700 TWX: '910-338-2374'"

12..14

m
,.emorl.. .' '.
......................

0

. . . . , . . . ,••••••

SN54/74LS546 SN54/74LS547 SN54/74LS566SN54/74LS567

Logic Diagram
SN54n4LS546
REGISTER TRANSCEIVER
NON-INVERTING OUTPUTS

Mo'noIlthio W.emorles

12-15.

SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567

Logic Diagram
SN54174LS547
LATCH TRANSCEIVER
NON-INVERTING OUTPUTS

12·16

Monolithic Wltllemorles

SN54/74LS546SN54/74LS547 SN54/74LS566SN54/74LS567
•. i

Logic Diagram
SN54174LS566
REGISTER TRANSCEIVER
INVERTING OUTPUTS

Monolithic

m

Memories

12·17

SN54/74LS546 SN54/74LS547 SN54174LS566 SN54/74LS567

Logic Diagram
SN54/74LS567
LATCH TRANSCEIVER
INVERTING OUTPUTS

12·18

Monolithic

W Memories

SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567

Block Diagrams

'LS546 (Non-inverting)

'LS547 (Non-inverting)

ABUS

ABUS

OEBA

CKEA
CKA

OEBA

CKEB
CKB

OEAB

GBl
GB2

B BUS

GAl
GA2

OEAB

BBUS

'LS566 (Inverting)

'LS567 (Inverting)

ABUS

A BUS

OEBA

CKEA
CKA

OEBA

CKEB
CKB

OEAB

GBl
GB2

BBUS

GAl
GA2

OEAB

B BUS

Monollthlo WMemorles

12·19

SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567
IEEE Symbols

'LS547

'LS546

0EiiA

21

OEAB
CKA

CKEA
CKB

eKES

EN2 [AB]

OEAB
GA2

G4
23
22

GBl

6C5

GB2

G6
\71



2\7

20

19

5

18

A2

17

A3

16
A4
15

AS
A6
A7

21
3

GAl

4C3

AD

Al

ENl [BA]

OEBA

10

14

11

13

BO

AD

Bl

Al

B2

A2

B3

A3

B4

A4

EN2[AB]
2:1

C3

2:1

C4

23
22

4

\71



2\7
19

5

18
17

AS

B6

A6
A7

15
10

14

11

13

OEBA
OEAB
CKA
CKEA
CKB
CKEB

1
2
23
22

AD

ENl [BA]

OEBA

EN2[AB]

OEAB

4C3

GA2

G4

GBl

6CS

GB2

G6



20

19

Al

18

A2

17

A3

16

A4
A5

A7

12·20

10
11

Bl
B2
B3
B4
B5
B6
B7

14

AO

Bl

Al

B2

A2

B3

A3

B4

A4

B5

A5

B6

A6

13
B7

ENl [BA]
EN2[AB]
2:1

C3

2:1

C4

23
22

20

BO

15

A6

21

GAl

\71

BO

'LS567

'LS566
21

20

16

B5

B7

2

ENl [BA]

A7

19
18

BO

B1
B2

17
B3
16
9

15

10

14

11

13

Monolithic IF.illftllemorles

B4
B5
B6
B7

SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567

Function Table
Nomenclature Description
AO-A7:

CKEAic'KEii:

Clock enable for rank AlB of 'LS546I'LS566.

CKA/CKB:

Clock for rank AlB of 'LS546I'LS566.

Eight input/output pins on the A side.

BO-B7:

Eight input/output pins on the B side.

x:

H or L state irrelevant ("Don't Care" conditions).

UC:

H or Lor j case (nonclocked operation).

f:

Positive edge of CK causes clocking, if clock
enable is asserted.
CKA

CKEA

RANK A

CKB

CKEB

RANKB

Disabled

UC

X

Disabled

GA1/GA2:

Gate enables for rank A of 'LS5471'LS567.

UC

X

GB1/GB2:

Gate enables for rank B of 'LS547I'LS567.

f

L

Enabled

f

L

Enabled

QoA/QoB:

Previous data of the internal rank AlB.

f

L

Enabled

f

H

Disabled

f

H

Disabled

f

L

Enabled

f

H

Disabled

f

H

Disabled

GA2

RANK A

L

L

Enabled
(Flush)

L

L

L
L

GB2

RANKB

L

L

Enabled
(Flush)

Enabled
(Flush)

L

H

Disabled
(Freeze)

L

Enabled
(Flush)

H

X

Enabled
(Flush)

H

Disabled
(Freeze)

H

X

Enabled
(Flush)

L

H

Disabled
(Freeze)

L

L

Enabled
(Flush)

L

H

Disabled
(Freeze)

L

H

Disabled
(Freeze)

GA1

GB1

I

L

L

Enabled
(Flush)

Enabled
(Flush)

L

H

Disabled
(Freeze)

Enabled
(Flush)

H

X

Enabled
(Flush)

H

X

Enabled
(Flush)

H

X

H

X

MonoIIthlfJ

0EAa:

To enable the A-to-B operation.

OEBA:

To enable the B-to-A operation.

0EAii

0EiiA

OPERATION DIRECTION

L

L

A, B buses both are outputs
(Transfer stored data to bus stored)
A-to-B

L

H

H

L

B-to-A

H

H

A, B buses both are inputs (storage)

Pin Configuration

m

(GAlt) CKA

1

(GA2t) CKEA

Z

",emorles

12-21

SN54/74LS546 SN54/74LS547 SN54/74LS566SN54/74LS567
Bus Operation For 'LS546
OPERATION

DIRECTION
CONTROL

0EAi

OEBA

GATE
ENABLE (A)

DATA 1/0
BLOCK DIAGRAM
AO-A7

BO-B7

CKA CKEA

H

H

Input

Input

A
BUS

S-to-A
Operation

H

L

Output
of
Input
Rank S

X

aoA

uc

X

aos

X

aoA

f

L

Sbus

UC

X

aoA

f

H

aos

f

L

A bus

UC

X

aos

f

L

Abus

f

L

Sbus

B

f

L

A bus

f

H

aos

BUS

f

H

aoA

UC

X

aos

f

H

aoA

f

L

S bus

I

H

aoA

f

H

aos

UC

X

aoA

UC

X

aos

uc

X

aoA

f

L

S bus

UC

X

aoA

f

H

aos

f

L

Rank S

UC

X

aos

f

L

Rank S

f

L

S bus

f

L

Rank S

f

H

aos

f

H

aoA

UC

X

aos

f

H

aoA

f

L

S bus

f

H

aoA

f

H

aos

UC

X

aoA

UC

X

aos

uc

X

aoA

f

L

Rank A

UC

X

aoA

f

H

aos

I

L

A bus .

UC

X

aoB

f

L

Abus

f

L

Rank A

f

L

Abus

f

H

aos

f

H

aoA

UC

X

aos

f

H

aoA

f

L

Rank A

-6:J-Lea"":'"' .
BUS

A

A-to-S
Operation

L

H

Input

Output
of
Rank A

.~

I
~B
ea

BUS

Transfer
Stored
Data

L

L

Output Output
of
of
Rank S Rank A

.:.

~

lrB~

B
BUS

12·22

RANKB

CKB CKEB

uc

l-EB-i
IRA:K!

GATE
ENABLE (B)

UC

A
Storage

RANK A

f

H

aoA

f

H

aos

UC

X

aoA

UC

X

aos

uc
uc

X

aoA

f

L

Rank A

X

aoA

f

H

aos

f

L

Rank S

UC

X

aos

f

L

Rank S

I

L

Rank A

f

L

Rank S

f

H

aos

f

H

aoA

UC

X

aos

f

H

aoA

f

L

Rank A

f

H

aoA

f

H

aos

AfonoilthlQW Memories

SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567
Bus Operation For 'LS547
OPERATION

DIRECTION
CONTROL
OEAB

OEBA

GATE
ENABLE (A)

DATA 1/0
BLOCK DIAGRAM
AO-A7

BO-B7

A

Storage

H

H

Input

Input

-~
~~ .
BUS

A

B-to-A
Operation

H

L

Output
of
Input
Rank B

BUS

-B:J~"':" .
BUS

A-to-B
Operation

L

H

Input

Output
of
Rank A

t

RANK

A

~I

B
BUS

A

Transfer
Stored
Data

L

L

Output Output
of
of
Rank B Rank A

-4:!t~.
BUS

RANK A

GATE
ENABLE (B)

RANKB

GB1

GB2

aoA

L

H

aoB

H

aoA

H

x

B bus

H

aoA

x

L

B bus

H

X

Abus

L

H

aoB

H

X

A bus

H

X

B bus

H

X

A bus

X

L

B bus

X

L

Abus

L

H

aoB

X

L

A bus

H

X

B bus

X

L

A bus

X

L

Bbus

L

H

aoA

L

H

aoB

L

H

aoA

H

X

B bus

L

H

aoA

X

L

Bbus

H

X

Rank B

L

H

aoB

H

X

Rank B

H

X

B bus

H

X

Rank B

X

L

Bbus

X

L

Rank B

L

H

aoB

X

L

Rank B

H

X

B bus

X

L

Rank B

X

L

Bbus

L

H

aoA

L

H

aoB

L

H

aoA

H

X

Rank A

L

H

aoA

X

L

Rank A

H

X

Abus

L

H

aoB
Rank A

GA1

GA2

L

H

L
L

H

X

Abus

H

X

H

X

Abus

X

L

Rank A

X

L

Abus

L

H

aoB

X

L

Abus

H

X

Rank A

X

L

Abus

X

L

Rank A

L

H

aoA

L

H

aoB

L

H

aoA

H

X

Rank A

L

H

aoA

X

L

Rank A

H

X

Rank B

L

H

aoB

H*

X

Rank B

H

X

Rank A

H*

X

Rank B

X

L

Rank A

X

L

Rank B

L

H

aoB

X*

L

Rank B

H

X

Rank A

X*

L

Rank B

X

L

Rank A

.

• NOTE: These controls for OEAB, OEBA, GA1, GA2, GB1 and GB2 can cause race conditions.

ItIIonollthlo WMemo,.IeS

12·23

SN54/74LS546 SN54/74LS547 SN54/74LS566 SN5t'74LS567
Bus Operation For 'LS566
OPERATION

DIRECTION
CONTROL
OEAB

OEBA

BLOCKDIAG.RAM
AO-A7

H

H

Input

Input

.~
\ RA:K \

63j

A

B-to-A
Operation

H

L

Output
of
Input
Rank B

~ L@J~
RA:K

Transfer
Stored
Data

L

L

H

L

Input

Output
of
Rank A

Output Output
of
of
Rank B Rank A

.~

~

,-EI ~

.~ Lffi~

UC
UC
UC

X
X

QoA
QoA

UC
t

X
L

QoB
B bus

X

QoA

t

H

QoB

t

L

Abus

UC

X

QoB

t

L

A bus

t

L

B bus

t

L

Abus

t

H

QoB

t

H

QoA

UC

X

QoB

t

H

QoA

t

L

B bus

t

H

QoA

t

H

QoB

UC
UC
UC

X

QoA

UC

X

QoB

X

QoA

t

L

B bus

X

QoA

t

H

QoB

B

I.
BUS

I
BUS

12·24

RANKB

CKB CKEB

B

1

A

CLOCK
ENABLE (B)

BUS

BUS

A-to-B
Operation

RANK A

CKA CKEA

BO.-B7

A

Storage

CLOCK
ENABLE (A)

DATA 1/0

t

L

Rank B

UC

X

QoB

t

L

Rank B

t

L

B bus

t

L

Rank B

t

H

QoB

t

H

QoA

UC

X

QoB

t

H

QoA

t

L

B bus

t

H

QoA

t

H

QoB

UC
UC
UC

X

QoA

UC

X

QoB

X

QoA

t

L

Rank A

X

QoA

t

H

QoB

t

L

Abus

UC

X

QoB

t

L

Abus

t

L

Rank A

t

L

Abus

t

H

QoB

t

H

QoA

UC

X

QoB

t

H

QoA

t

L

Rank A
QoB

t

H

QoA

t

H

UC
UC

X

QoA

UC

X

QoB

X

QoA

t

L

Rank A

uc

X

QoA

t

H

QoB

t

L

Rank B

UC

X

QoB

t

L

Rank B

t

L

Rank A

t

L

Rank B

t

H

QoB

t

H

QoA

UC

X

QoB

t

H

QoA

t

L

Rank A

t

H

QoA

t

H

QoB

Monollthla WMemorles

\

SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567
Bus Operation For 'LS567
,

I

OPERATION

DIRECTION
CONTROL

DATA 110

0EAi 0iiA

AO-A7 BO·87

A

~
H

Storage

I:l

1nput

.

H

L

RA/lK

.

'.
aus

'~

,.
.'

OIJ~ut

'

.~

~

Input

c'

B-to-A
Operation

GATE
. ENABLE (A)

BLOCK DIAGRAM

of
Input
Rank B

. RA/lK
".
B
.

.

"

"

RANK
A

B
BUS

GA1

GA2

L

H

L

H

L

RANK A

GATE
ENABLE (B)

Gii2

QoA

L

H

QoB

QoA

H

X

Bbus

H

QoA

X

L

Bbus

H

X

A bus

L

H

QoB

H

X

A bus

H

X

Bbus

H

X

A bus

X

L

Bbus

X

L

A bus

L

H

QoB

X

L

A bus

'H

X

Bbus

X

L

A bus

X

L

Bbus

L

H

QoA

L

H

QoB

L

H

QoA

H

X

Bbus

L

H

QoA

X

L

Bbus

H

X

Flank

L

H

QoB

H

X

Flank B

H

X

Bbus

H

X

Flank B

X

L

Bbus

X

L

Flank B

L

H

CoB

X

L

RankB

H

X

i3 bus

X

L

RankB

X

L

6 bus

L

tl

QoA

L

H

QoB

L

H

QoA

H

X

Rank A
RankA

B

.

.....

A

A-to-B
Operation

L

H

Input

Output
of

R'iifii(A

~
.-"':"
,

"A

B
BUS

.

L

H

QoA

X

L

H

X

Abus

L

H

QaB

H

X

A bus

H

X

Rank A

H

X

Abus

X

L

Rank A

X I L'

A.bus

L

H

QoB
Flank A

X

A

Transfer
Stored
Data

L

L

Output Output .
of
Rank A

2Lijank B

~
RAflIK

a·

!lANK
A'

a

BUS

RANKB

GB1

L
L

A bus

H

X

X

.Abus

X

L

L

H

QoA··

L

I H

L

H

QoA

H

X

RaQkA'
QoB
Rank A

L

H

QoA

X

L

Rank A

H

X

Rank B

L

H

QoB

H*

X

RankS

H

X

Rank. A

H*

X

Rank B

X

I-

Flank A

X

L

Flank B

L

H

QoB

X*

L

RankS

H

X

Rank A

X*

L

Rank B

X

L

Rank A

* NOTE: These controlslor.OEAB, DEiiA, GAt, G,A2,'GBI and Gi!i! can cause race conditions,

12-25

SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567

Absolute Maximum Ratings
Supply voltage VCC ....................................................................................... : ..... 7.0 V
Input voltage .....•....•........................................................................................ 7.0 V
Off-state output voltage ...•........................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 5.5 V
Storage temperature .•...............•...•................................................••........... -65° to +150°C

Operating Conditions
SYMBOL

,

PARAMETER

VCC

Supply voltage

TA

Operating free-air temperature

TW

Width of clock/gate

r--Low

'LS547
Tsu

Setup time
'LS566
'LS567
'LS546
'LS547

Th

Hold time
'LS566
'LS567

t l

4.5

5.5

4.75

125

0

CK

11

8

19

15

GA1,GB1 10

8

Low

GA2,GB2 18

16

5

UNIT

5.25

V

75

°c

ns

111

CKA, CKB

141

GA1, GB1

51

51

GA2, GB2

151

151

CKA, CKB

141

111

GA1, GB1

131

131

GA2, GB2

221

221

ns

CKA, CKB

01

01

GA1, GB1

131

131

GA2, GB2

51

51

CKA, CKB

01

01

GA1, GB1

111

111

GA2, GB2

51

51

151

111

ns

51

41

ns

Tsuce

Setup time for CKEA, CKEB, (,LS546, 'LS566 only)

Thee

Hold time for CKEA, CKEB (,LS546, 'LS566 only)

the arrow indicates the transition of the cloc'k/gate input used for reference:

t for the low-la-high transitions.
1 for the high-ta-Iow transitions.

12·26

5

High
'LS547, 'LS567
'LS546

COMMERCIAL
MIN TYP MAX

-55
High

'LS546, 'LS566

MILITARY
MIN TYP MAX

MonollthloW.emorles

ns

SN54/74LS546 SN54/14LS547 SN54/74LS566 SN54/74LS567

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL

Low-level input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

TEST CONDITIONS

11=-18mA

-1.5

-1.5

Vee = MAX
VI = 0.4 V

-250

-250

All others

-400

-400

VI = 2.7 V

20

20

p.A

0.1

0.1

mA

High-level input current

II

Maximum input
current

VOL

Low-level
output VOltage

Vee = MIN
VIL = MAX
VIH = 2V

VOH

High-level
output voltage

Vee = MIN
VIL = MAX
VIH = 2V

Off-state output current

Vee = MAX

Vee = MAX

VI = 5.5 V

Vee = MAX

Output short-circuit current*

IOL = 24mA

0.5

*

Supply current

10H = -1 mA

2.4

V
2.4
-250

-250

Vo = 2.4 V

20

20

p.A
-130
180

-30

-130

180

180

'LS566

180

180

'LS567

180

180

m

Memories

mA

180

'LS547

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

Monolithic

3.1

Va = 0.4 V

-30

Vee = MAX
Outputs open

0.5

3.4

10H = -2.6mA

Vee = MAX

I

p.A

V
0.35

10L = 32 mA

'LS546
lee

V

VI = 7.0 V

10ZH
lOS

V
V

A or B

IIH

10ZL

0.8
2

UNIT

Vee = MIN

Low-level input current

I All others

COMMERCIAL
MIN TYP MAX

0.8
2

IlL

I A or B

MILITARY
MIN TYP MAX

mA

SN54/14LS546 SN54/74 LS54 7
Switching Characteristics
SYMBOL

Over Operating Conditions

PARAMETER

fMAX

Maximum clock
frequency

tpLH/tpHL

CK to output delay
(,LS546 only)

TEST CONDITIONS

MILITARY
COMMERCIAL
UNIT
'LS546
'LS547
'LS546
'LS547
MIN MAX MIN MAX MIN MAX MIN MAX
33

43

MHz

26

21

ns

.

CL = 45 pF RL = 280n

tpLH/tpHL

GA1, GA2, GB1 or
GB2 to output
delay (,LS547 only)

tpLH/tpHL

Data D to output
delay (,LS547 only)

tpZL/tpZH

Output enable
delay

CL = 45 pF RL = 280 n

25

25

tpLz/tpHZ

Output disable
delay

CL = 5 pF RL = 280n

22

22

OE= L

27

24

ns

23

18

ns

21

21

ns

19

19

ns

Switching Characteristics vcc = 5 V, TA = 25°C
SYMBOL

PARAMETER

TEST CONDITIONS

'LS546
MAX
MIN

'LS547
MIN
MAX

UNIT

fMAX

Maximum clock frequency

50

MHz

tpLH/tpHL

CK to output delay
(,LS546 only)

19

ns

tpLH/tpHL

GA1, GA2, GB1 or GB2 to
output delay (,LS547 only)

tpLH/tpHL

Data D to output delay
(,LS547 only)

tpZL/tpZH

Output enable delay

CL = 45 pF

RL = 280 n

tpLZ/tpHZ

Output disable delay

CL = 5 pF RL = 280 n

12·28

CL = 45 pF

RL = 280 n
23

ns

17

ns

19

19

ns

17

17

ns

OE = L

Mono"'hloW Memories

SN54/74LS566 SN54/74LS567
Switching Characteristics
SYMBOL

Over Operating Conditions

PARAMETER

TEST CONDITIONS

COMMERCIAL
MILITARY
UNIT
'LS567
'LS567
'LS566
'LS566
MIN MAX MIN MAX MIN MAX MIN MAX

fMAX

Maximum clock
frequency

tpLH/tpHL

CK to output delay
(,LS566 only)

tpLH/tpHL

GA1, GA2, GB1 or
GB2 to output
delay (,LS567 only)

tpLH/tpHL

Data D to output
delay (,LS567 only)

tpZL/tpZH

Output enable
delay

CL = 45 pF

RL = 2800

25

25

tpLz/tpHZ

Output disable
delay

CL = 5 pF

RL = 2800

22

22

C L = 45 pF

RL = 280 0

33

43

MHz

26

21

ns

OE=L

26

24

ns

29

23

ns

21

21

ns

19

19

ns

Switching Characteristics vcc = 5 V, TA = 25°C
SYMBOL

PARAMETER

TEST CONDITIONS

'LS566
MAX
MIN

'LS567
MIN
MAX

UNIT

fMAX

Maximum clock frequency

50

MHz

tpLH/tpHL

CK to output delay
(,LS566 only)

19

ns

tpLH/tpHL

GA 1, GA2, GB1 or GB2 to
output delay (,LS567 only)

tpLH/tpHL

Data D to output delay
(,LS567 only)

tpZL/tpZH

Output enable delay

tpLZ/tpHZ

Output disable delay

CL = 45 pF

RL = 2800
21

ns

19

ns

19

19

ns

17

17

ns

OE = L

CL = 45 pF
CL = 5 pF

RL = 2800
RL

= 280 0

Monolithic WMemorles

12·29

SN54/74LS546 SN54/74LS566
Definition of Waveforms
'LS546/566
Setup and Hold

Clock CK to Output Delay
DATA
INPUT

r-----------------'----------3V
\

~

'---------0 V

OUTPUT

fLS566)

12·30

MonolithicW Memories

SN54/74LS547 SN54/74LS567

Definition of Waveforms
'LS547/567
Setup and Hold

\

J

DATA

INPUT

~VT

If.

VT

\ r.,.VT

VTJ
_ T.. _

-

-Th-

GA1,

I~~~ J

m, GB1 or Gi2 to Output Delay

~-------.------- 3V

\'"~- - - - - - o v

~----3V

GA1/GB1

'---", 1---_-r---~

OV

----_~3V

"-----OV
~-----~~~ - - - - - - 3 V

OUTPUT
fLS547) _ _--:-_

I'---ov

bf,;
tPHL

OUTPUT
fLS567)

3V

VT

--------~

----OV
tPLH

VT = 1.3V

IIIIonoIIthIoW""emories

12·31

SN54/74LS546 SN54/74LS547 SN54/74LS566 SN54/74LS567

Test Load
TEST POINT'
S1

CL
(SEE NOTE A)

*

OUTPUT
ENABLE
(LOW-LEVEL
ENABLING)

I

RO

1K

The "TEST POINT" is driven by the output under test,
and observed by instrumentation.

, - - - - - - - - - - 3V

OV
~tpZL---P

--4.5V
WAVEFORM 1
(SEE NOTE A)

S1 AND S2 CLOSED

S1 CLOSEO
S2 OPEN

WAVEFORM 2
S10PEN
_ _ _..J
(SEE NOTE A) _ _ _
S2CLOSEO

r--------------~====~!~VOH
1

0.5 V
--1.5V

VT

S1 ANO S CLOSED

ENABLE AND DISABLE
NOTES: A. CLfncludes probe and jig capacitance.

B. All diodes are 1N916 or 1N3064.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.

E. All input pulses are supplied by generators having the following characteristics: PRR :S 1 MHz, Zout
F. When measuring propagation delay times of 3-state outputs, switches 81 and 82 are closed.

12·32

Monolithic

W Memories

=

50U and tR ::.:; 15 ns tF ::.:; 6 ns.

SN54/74LS546 SN54/74LS547 .SN54/74LS566 SN54/74LS567

Die Configurations
'LS547

'LS546

Die Size: 100x147 mil2

'LS566

/IIIonoI"hlo lUll Memories

12·33

8-Bit Bus Front-Loading-Latch
Transceivers
SN54/74LS647
SN54/74LS649

SN54/74LS646
SN54/74LS648
Features/Benefits
• Bidirectional bus transceivers and registers
• Independent registers for A and B buses

Ordering Information
PART
NUMBER

TEMP POLARITY

PKG

• Real-time data transfer or stored data transfer

SN54LS646 JS,W,L

• 24-pin SKINNYDIP® saves space

SN74LS646 NS,JS Com

• 8-bit data path matches byte boundaries
• Three-state or open-collector outputs drive bus lines

OIP

POWER

Mil
3-state

SN54LS647 JS,W,L

Mil

Noninvert

SN74LS647 NS,JS Com
SN54LS648 JS,W,L

LS

Mil
3-state

SN74LS648 NS,JS Com
SN54LS649 JS,W,L

Opencollector

Mil

Invert

SN74LS649 NS,JS Com

Opencollector

NOTE: L package here is L28. The other packages are 24-pin.

Description
The 8-bit bus transceivers with 3-state (,LS646, 'LS648) or opencollector (,LS647, 'LS649) outputs have 16 D-type flip-flops and
multiplexers. The bus-oriented pinout ofthe parts is shown in the
Pin Configuration. The internal gate-level hardware configurations for the 'LS646/647 and 'LS648/649 are given in their respective Logic Diagrams. The basicrepeated element, consisting of
an edge-triggered flip-flop paralleled with a bypassing path or
"feed-through" into a two-way mux, is sometimes called a ''frontloading latch."

Pin Configuration
'LS646/647/648/649
8-Bit Bus Front-Loading-Latch Transceivers

A pair of multiplexers are used to distribute two bytes of data
through the part. The data-routing combinations offered by the
multiplexers provide flexibility in directing data to or from either
bus, andlor either register. Data is loaded into registers A or B
upon the rising edge of the appropriate clock signals. CKA
clocks register A, which receives data from the B bus directly at
its inputs. Similarly, CKB clocks register B, which has the A bus
available directly at its inputs. Control of the multiplexers is
provided by two select lines (one per register), SRA and SRB.
Command of the outputs is performed by enable line E, and
direction line DIR.
When Eis High data from the buses can be stored into register A
and B. When E is Low and DIR is High, the direction of operation
is from A to B; when E and DIR are LOW, the direction of
operation is from B to A.
SRA is used to select between register A and the B bus, and then
to route the data to a controlled buffer connected to the A bus.
Likewise, SRB selects between register B and the A bus, and
then routes the data to the.B bus through a controlled buffer.

SKINNYD1P@ is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

12-34

lIIonollthlc 1!T!I1
lIIemorles Il1UlJ.I

I.

IN54/74LSf$47

SN54174LS848

SN54/74LS848

SN54/74LS849

Logic Diagrams

CKA

DIR

lI"'"

3

.1 J

l-=n-

21
SRA
SRS

'LS646/647 (Non-Inverting)

...

23

22

I!o..

2

~
....

1

I!o.

.

' '

i

'.',

r-

.

-"'"
- ....

I-'----'-~'---

-"'"
....
---

-~~~~-- -.."
'.
~
iao

f---

lI"'"

,AD

1D

~EI
-

i

4

.

r-

I1

C1
---'-

1
1

RI;GIS,TER A .A
~

I

iD

---

...

. ,.

....

REGISTERS

L f-,--.:-.,----- r - -

1
1

.

I

C1

SO

I

1
1

_.J
---- !T"---.,--:----,.
,

TO 7 OTHER CHANNEI,S

* For the 'LS646 devices, the A and B bus outputs are 3-state.
For the 'LS647 devices, the A and B bus outputs are open-collector.

'LS6481649 (Inverting)
CKA

DIR

3

SRS

CKB

·"e_

lI"'"

.1 J

21
SRA

...

23

22

2
1

I~

...

-"'"

::....

".'-

....... r-'- --------- --I

-

I

AD

....

-"'"
....

I

4

I

1

'.

1

I
I

I

.•

'_.!.O.!.~~~~L_

...--10

.
11"1

-,1

C1

L-o....

I1

. REGI,STER A

1

I.
I

1D

':
C1

I;

. REGISTERS

L ----.,--,...--.- r - -

I~
,If --'

•

I
I

I
I
I

r:--.,.,.~-:---~-~-

T07 OTHER CHANNELS

*

--

r-l...-

I

f--.-

For the 'LS648 devices, the A and B bus outputs a~e 3-state.
For the 'LS649 devices, the A and B bus outputs are open-collector.

"- .J.

ao

SO

SN54/74LS647

SN54174LS646

SN54/74LS649

SN54/74LS648

IEEE Symbols
'LS646

E

21

DIR
CKA
SRA

'LS647

E

G3

DIR

3EN1 [SA]
23
22

CKB

3EN2[AS]
orrC4

CKA

ffG5

SRA
CKB

orrC6

SRB

21

ffG7

SRB
20

4

BO

AO

B1

A1

B2

A2

B3

A3

B4

A4

17
A3

22
1
2

3 EN2 [AS]
orrC4
ffG5
orrC6
ffG7
20

4

18
A2

23

BO

AO

19
A1

G3
3EN1 [SA]

5

19

6

18

B1
B2

17

7

B3
16

16
A4

B4

15
A5
10

15
B5

A5

B6

A6

14

A6
13

11
A7

B7

B5
10

14

11

13

B6

A7

B7

'LS648

E
DIR
CKA
SRA

21
3
23
22

CKB

'LS649

E

G3
3EN1 [BA]
3 EN2 [AB]
orrC4

CKA

.rJ1G5

SRA
CKB

ffG7

SRB

G3
3 EN1 [SA]

DIR

orrC6

SRB

21

23
22
2

3 EN2[AB]
orrC4
.rJ1G5

!lTC6
ffG7

20

5

\7 1 ,,1

AO

20
BO

5

6D

'i

ff

19

A1

81
6

82

9

15

10

14

A5
A6
11
A7

12-36

18

A2

82
17

83

A3

84

A4

16

A4

19
81

6

17
A3

'i

A1

18

A2

8

BO

5

6D

ff

5

~1 ,,1

AO

85

A5

86

A6

B7

A7

13

83

8

16

9

15

10

14

84
B5
B6
11

Monolithic WM.morles

13
87

SN54/74LS647

SN54/74LS646

SN54/74LS648

SN54/74LS649

Block Diagrams
'LS646/647 (Non-Inverting)

'LS648/649 (Inverting)

ABUS

ABUS

BBUS

BBUS

* For the 'LS646/648 devices, the A and B bus outputs are 3-8tate.
For the 'lS647/649 devices, the A and B bus outputs are open-collector.

!

I

Function Table
Nomenclature Description

SRAlSRB: To select the output data coming from the AlB
register if SRAlSRB is a High level; otherwise,
directly from the input data bus.

E:

To enable the A-to-B or B-to-A operation.

AO-A7:

Eight input/output pins on the A side.

DIR:

To select the direction of operatiOn.

BO"B7:

Eight input/output pinson the B side.

CKAICKB: Clock for Register AlB.

E

DIR

OPERATION DIRECTION

X:

H or L state irrelevant (HDon't Care" conditions).

B-to-A

t:

Positive edge of CK causes clocking, if clock enable
is asserted.

UC:

H or L or j case (nonclocked operation).

RGTR:

Register.

L

L

L

H

A-to-B

H

X

A and B buses both are inputs (storage)

MonolithlcWMemories

12-37

5N54J'74L5646 5N54 1'7 4L5647
Bus Operation for 'L5646J'647
CONTROL
OPERATION

Storage

E

H

BLOCK DIAGRAM

DIR SRA SRB AO-A7 BO-B7

X

X

CLOCK
ENABLE

DATA 110

X

Input

Input

CKA CKB

:.~
r
tern
B

B

'LS646/647

UC UC No operation
UC t Real time Abus data - RGTR B
t
UC Real time B bus data - RGTR A

BUS

eKB

CKA

.

t!:q

Real time
B-to-A

L

L

L

X

Output

.~

Input

Operation

t
CKA

B-to-A

L

L

H

X

Output

Input

M~
~~ .
r

Operation

t

B

UC
t

BUS

eKB

~l

Real time

H

X

L

Input

Real time B bus data - A bus
Real time Bbus data - RGTR B
Real time B bus data - A bus

UC Real time B bus data - RGTR A
t

Real time B bus data - A bus
Real time B bus data - RGTR A
Real time B bus data - RGTR B

t

RGTR A data - A bus
RGTR A data '-- RGTR B
Real time B bus data - RGTR A

UC RGTR A data - A bus
t

Real time B bus data - RGTR A
RGTR A data - A bus
RGTR A data -c- RGTR B

UC UC Realtime A buS data - B bus

.

BUS

L

t

CKA

t

A-to-B

Real time A bus data - RGTR B
Real time B bus data - RGTR A

UC UC RGTR A data - A bus

.

Stored data

UC

B
BUS

eKB

t

UC UC Real time B bus data - A bus

.-----.

BUS

t

~

Output

Operation

UC
t

t

Real time A bus data - B bus

UC Real time A bus data - RGTR A

B
BUS

t

eKA

CKB

Real time A bus data - B bus
Real time A bus data - RGTR B

t

Real time A bus data - B bus
Real time A bus data - RGTR A
Real time A bus data - RGTR B

UC UC RGTR B data - B bus

B~S

Stored data
A-to-B
Operation

L

H

X

H

Input

Output

[B

BJ:;l

UC
t

B

B
BUS

eKB

Monolithic

m

Memories

Realtime A bus dala- RGTR B
RGTR B data - B bus
RGTR B data - B bus

UC RGTR B data - RGTR A

eL

t

12·38

t

t

Real time A bus data - RGTR B
RGTR B data - B bus
RGTR B data - RGTR A

SN54/74LS648

SN54/74LS649

Bus Operation for 'LS648/649

CONTROL

BLOCK DIAGRAM

E

Storage

CLOCK
ENABLE

DATA 110

OPERATION

H

DIR SRA SRB AO-A7

X

X

X

Input

BO-B7

Input

'LS648/649

CKA CKB

.:. Mm I~"ll

r
IF·

uc uc

No operation

UC

Real time A bus data - RGTR B

t

t

UC Real time B bus data - RGTR A

BUS

eKB

CKA

t

t

Real time A bus data - RGTR B
Real time B bus data - RGTR A

UC UC Real time B bus data - A bus

A~

A
BUS

Real time
B-to-A

L

L

L

X

Output

L~~

Input

t

B
BUS

r

Operation

UC

CKB

CKA

t

UC
A
BUS

A~

Stored data
B-to-A

UC

...----.

L

L

H

X

OutpSt

~A

Input

r

Operation

RGTR
B

CKB

l

t

B
BUS

. B:J~

Real time
A-to-B

L

H

X

L

Input

Output

Operation

~.

A-to-S
Operation

L

H

X

H

Input

Output

UC RGTR A data - A bus
t

Real time B bus data - RGTR A

t

Real time B bus data - RGTR A
RGTR Adata - A bus
RGTR Adata - RGTR B

UC

Realtime A bus data - B bus
Real time A bus data - RGTR B

t

CKA

tc~m ~~I
J:

RGTR A data - A bus
RGTR Adata - RGTR B

UC RGTR A data - A bus

t

Real time A bus data - B bus

UC Real time Abus data - RGTR A

B
BUS

A
BUS

Real time B bus data - A bus
Real time B bus data - RGTR A
Real time B bus data - RGTR B

Real time A bus data - B bus

UC
Stored data

t

uc UC

t

CKB

Real time B bus data - A bus
Real time B bus data - RGTR B

time B bus data - A bus
UC Real
Real time B bus data - RGTR A

CKA

t

A
BUS

t

uc

v

t

t

Real time A bus data - B bus
Real time A bus data - RGTR A
Real time A bus data - RGTR B

UC RGTR B data - B bus
t

Real time A bus data - RGTR B
RGTR B data - B bus
RGTR B data - B bus

UC RGTR B data - RGTR A

BUS

CKB

CKA

t

Monolithic

W Memories

I

Real time A bus data - RGTR B
RGTR B data - B bus
RGTR B data - RGTR A

12-39

SN54174LS646 SN54/74LS648
Absolute Maximum Ratings
Supply voltage, vee ...............•....................................................•...•....•.......•........ 7.0 V
Input voltage, ..••.•.........................•.•• : ..••..••...•.•.•••.••.•...•••.•••.......•......•......... , .•....• 7.0 V
Oif-state output voltage •....•.•..•..••..........•..•......•..••..•..•....••.•..........•.......•...•....••..•...••. 5.5 V
Storage temperature •.............•..........•••.... '. '..••....•.••.••......•.•.•.•.•..•.•.••...•.......... -65°· to +150"·C

Operating Conditions
SYMBOL

MILITARY
MIN TYP MAX

PARAMETER

COMMERCIAL
MIN TYP MAX

UNIT

Vee

Supply voltage

4.5

TA

Operating free air temperature

-55

tw

Width of clock

tsu

Setup time

th

Hold time

1014

High-level output current

-12

-15

mA

10L

Low-level output current

12

24

mA

5

5.5

4.75

125

0

High

20

20

Low

20

20

'LS646

201

201

'LS648

201

201

'LS646

01

01

'LS648

01

01

5

5.25

V

75

°e
ns
ns
ns

t 1 The arrow indicates the transition of the clock input used for reference. t for the low-la-high transitions. 1for the high-la-low transitions.

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL

Low-level input voltage

VIH

High-level input voltage

TEST CONDITIONS

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

0.7
2

0.8

UNIT
V
V

2

Vie

Input clamp voltage

Vee= MIN

~VT

HystereSiS (VT+-VT_)

Vee= MIN

IlL

Low-level input current

Vee= MAX

VI= 0.4 V

-0.4

-0.4

mA

IIH

High-level input current

Vee= MAX

VI = 2.7 V

20

20

p.A

II

Maximum input
current

0.1

0.1

mA

VOL

Low-level output voltage

VOH

High-level output voltage

I AorS

I All others

Vee= MIN
VIL =MAX
VIH = 2 V

0.25

IOL=12mA

2

Off-state output cu rrent

Vee=MAX
VIL = MAX
VIH = 2V

VO=0.4 V
VO=2.7V

Output short-circuit current*

Vee= MAX

Vee=
MAX
'LS648

0.4

10L =24mA

10H= MAX

Supply current

-40

3.4

2.4

0.4

V
V

0.25

0.4

0.35

0.5.

V

3.4
V

2
-400

-400

20

20

p.A

-225

mA

-225

-40

Outputs High

145

145

Outputs Low

165

165

Outputs Disabled

165

165

Outputs High

145

145

Outputs Low

165

165

Outputs Disabled

165

165

* Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

12-40

-1.5
0.2

VI= 7V

2.4

'LS646

0.4

VI = 5.5 V

IOH=-3 mA

10ZH

lee

0.1

Vee= MIN
VIL =MAX
VIH = 2 V

10ZL

lOS

Vee= MAX

-1.5

II = -18 mA

p.A

mA

SN54/74LS646

SN54/74LS648

Switching Characteristics vcc = 5 V, TA = 25°C
SYMBOL

PARAMETER

TEST CONDITIONS

'LS646
MIN

(See Test Load/Waveforms)

'LS648
MAX

MIN

UNIT

MAX

18

18

ns

tpHL

20

25

ns

tpLH

25

25

ns

35

40

ns

40

55

ns

35

40

ns

50

40

ns

tpLH

Data to output delay

Clock to output delay

tpHL
tpLH
tpHL
tpLH

Select to output delay
(data input High)

CL = 45pF

RL = 667.0

Select to output delay
(data input Low)

25

40

ns

65

55

ns

tpZH

55

50

ns

tpLZ

35

35

ns

tpHZ

35

45

ns

tpZL

60

45

ns

tpZH

45

40

ns

tpLZ

30

30

ns

30

35

ns

tpHL
tpZL

I

Output enable delay

Output disable delay

Direction enable delay

Direction disable delay

CL = 5pF

RL = 667.0

RL = 667.0

CL = 45pF

CL = 5pF

RL = 667.0

tpHZ

Switching Characteristics Over Operating Range
TEST CONDITIONS
SYMBOL

PARAMETER

(See Test Load/Waveforms)

COM

25

18

25

18

tpHL

25

25

25

25

ns

tpLH

28

25

28

25

ns

tpLH

Data to output delay

Clock to output delay

ns

tpHL

35

40

35

40

ns

tpLH

40

55

40

55

ns

35

40

35

40

ns

50

40

50

40

ns

30

40

30

40

ns

65

55

65

55

ns

tpZH

55

50

55

50

ns

tpLZ

45

35

45

35

ns

45

50

45

50

ns

60

45

60

45

ns

tpHL
tpLH
tpHL
tpZL

Select to output delay t
(data input High)

CL = 45pF

RL = 667.0

Select to output delay t
(data input Low)
Output enable delay

Output disable delay

CL = 5pF

RL = 667.0

CL = 45pF

RL = 667.0

tpHZ
tpZL

Direction enable delay

tpZH

45

40

45

40

ns

tpLZ

40

30

40

30

ns

45

45

45

45

ns

tpHZ

t

MIL

'LS646
'LS648
'LS646
'LS648
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

Direction disable delay

CL = 5pF

RL = 6670

See Figure 4,

Monolithic WMemorles

12·41

SN54/74LS847 SN54/74.LS849

Absolute Maximum Ratings
Supply voltage, vee .............................. , ............................................................... 7.0 V
Input voltage, .......••.•.•.•.•......•............•...•.•....•...•.•...•....•.•..........•.....•.....•.....•...•.• 7.0 V
Off-state output voltage ...•.•....•......•...•......•....•.•.•.•....•...•.•.•.••.....•.....•..•......••....•.•..•.. 5.5 V
Storage temperature ..................................................................................... -65" to +15O"e

Operating Conditions
SYMBOL

MILITARY
MIN TYP MAX

PARAMETER

5

COMMERCIAL
MIN TYP .MAX

5.5

4.75

125

0

5

UNIT

5.25

V

75

·e

Vee

Supply voltage

4.5

TA

Operating free air temperature

-55

tw

Width of clock

tsu

Setup time

th

Hold time

VOH

High-level output voltage

5.5

5.5

V

IOL

Low-level output current

12

24

mA

High

20

20

Low

20

20

'LS647

201

201

'LS649

201

201

'LS647

01

01

'LS649

01

01

ns
ns
ns

1 I The arrow indicates the transition of the clock input used for reference. 1 for the low-to-high transitions. I for the high-t<>-Iow transitions.

Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL

Low-level input voltage

VIH

High-level input voltage

TEST CONDITIONS

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX
0.8

0.7
2

2

UNIT
V
V

-1.5

-1.5

V

Vie

Input clamp voltage

Vee= MIN

~VT

Hysteresis (VT+-VT-)

Vee= MIN

IlL

Low-level input current

Vee= MAX

VI = 0.4 V

-0.4

-0.4

mA

IIH

High-level input current

Vee=MAX

VI = 2.7 V

20

20

p.A

II

Maximum input
current

0.1

0.1

mA

VOL

Low-level output voltage

IOH

High-level output current

I AorB
I All others

Vee= MAX
Vee = MIN
VIL =MAX
VIH = 2 V
Vee = MIN
VIL = MAX
VIH = 2V
'LS647

lee

Supply current

Vee=
MAX
'LS649

II = -18 mA
0.1

0.4

0.2

VI= 5.5V
VI= 7V
IOL = 12 mA

0.25

0.4

IOL =24 mA

0.25

0.4

0.35

0.5

VOH=5.5V

100

100

Outputs High

130

130

Outputs Low

150

150

Outputs Disabled

150

150

Outputs High

130

130

Outputs Low

150

150

Outputs Disabled

150

150

• Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

12-42

V

0.4

WIonoIIIhIc IBJ) """'orl8.

V

p.A

mA

SN54/74LS647 SN54/74LS649
Switching Characteristics vcc = 5 V, TA = 25°C
SYMBOL

PARAMETER

TEST CONDITIONS

'LS647
MIN

(See Test Load/Waveforms)

'LS649
MAX

MIN

MAX

UNIT

26

25

ns

tpHL

27

30

ns

tpLH

35

30

ns

45

45

ns

50

55

ns

45

45

ns

60

45

ns

30

40

ns

tpLH

Data to output delay

Clock to output delay

tpHL
tpLH
tpHL
tpLH
tpHL

Select to output delayt
(data input High)
CL = 45pF

RL = 6670

Select to output delayt
(data input Low)

40

40

ns

tpHL

50

50

ns

tpLH

35

30

ns

40

45

ns

tpLH

Output enable delay

Direction enable delay

tpHL

Switching Characteristics Over Operating Range
TEST CONDITIONS
SYMBOL

PARAMETER

(See Test Load/Waveforms)

COM

32

35

32

35

ns

tpHL

27

30

27

30

ns

tpLH

35

40

35

40

ns

tpLH

Data to output delay

Clock to output delay

tpHL
tpLH
tpHL
tpLH

Select to output delayt
(data input High)
CL = 45pF

RL = 667[1

Select to output delayt
(data input Low)

45

45

45

45

ns

50

55

50

55

ns

45

45

45

45

ns

60

50

60

50

ns

30

40

30

40

ns

40

45

40

45

ns

tpHL

50

50

50

50

ns

tpLH

40

45

40

45

ns

40

45

40

45

ns

tpHL
tpLH

Output enable delay

Direction enable delay

tpHL

t

MIL

'LS649
'LS647
'LS649
'LS647
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

See Figure 4.

Monolithic

W Memories

12·43

SN54/74LS646

SN54/74LS648

SN54/74LS647

SN54/74LS649

Test Waveforms
Bus Data To Bus Output Delay

. Setup Time/Hold Time

r--------~,--~-------3V

BUS DATA

'------OV

,-------3v

CK

____________J+
"""l/~VT
_____________ OV

BUS OUTPUT
(,LS648/847)

------+--'

DATA
BUS OUTPUT
('LS84S/849)

VT

"""----r-..J~r---- VOL

=1.3 V

Figure 1.

Figure 2.

VT = 1.3 V

CK To Bus Output Propagation Delay Time
DATA 1 - r - V T - - - - - - - - - - - - \ I . - - - Y T - - - - - - - - - - : :

CK

Oy
r------------4-~;_-----VOH

BUS OUTPUT
('LS84SI847)

--t---J

BUS OUTPUT
('LS84S/649)

VOL
-

"'HL

Figure 3

VT= 1.3V

Select To Output Delay
--~~--------------------3V

DATA
OF BUS

DATA OF
REGISTER

~----~-------OV

r;;----~~--------3V

---J---r----------+-----------OV

-~---+----'

,...----'--- 3 V
SRAlSRB
~--_.~~--------OV

OUTPUTetOr:.
The S buS outputs are 3-state for both devices;
,

,,",

,1

I

I

I
I
I
I
I
I

II
I
I
I

J

20"

80

SN54/74LS651

SN54/74LS652

SN54/74LS653

SN54/74LS654

IEEE Symbols
'LS6S1

GsA
GAB
CKA
SRA
CKB
SRB

21
3

23
22
l'

'LS653

EN1 [BAI

GBA

EN2[AB]

GAB

C4

CKA
SRA
CKB

G5

C8

2'

07

SRB

21
.3

23
22
1
2
4

AD

AD

EN1 [BAI
EN2[ABI

.C4
G5
C6
G7 '

~1 ~<1 ~

20
BO

5

eo

7

'i

5
A1

..

19
B1

A1
8

A2

A2

A3

A3

A4

18
B2

7

17

8

16

B3
B4

A4
9

15

10

14

11

13

B5

AS

B6

A8

A6

B7

A7

A7

'LS6S4

"LS6S2

GsA
GAB
CKA
SRA

"

21
3

23
22

EN1 [BAl' .

GsA

EN2.[AB)

GAB

C4 .

CKA
SRA

1
CKB
2
SaB ..

CKB
SRB

21
3

23
22
1
2

BO

BO

19
B1

A1

B1

18

18
B2

A2

B2

A2

17
A3

17
B3

A3

B4

A4

16
A4
15

AS,

B5

AS

BS

AS

B7

A7

13
A7

B3
8

16

9

15

B4

B5
14

14
A8

C8
G7

AD

19
A1

.C4
G5

20

20

AD

EN1 [BAI
EN2[ABI

BS
13
B7

12-49

SN54/74LS652

SN54/74LS651

SN54/74LS653

SN54/74LS654

Block Diagrams
'LS6521654 (Non"lnvertlng)

'LS651/653 (Inverting)

ABUS'

A BUS

SRB

V---"tPu,- drive bus nlies
24-PlriSKINNYDIP~
sav" sp.~··.
.
,

• S-blt data path matches byte bouncllirles .. ,
• MultIPle.x,r ielec'- elth.er rank at Input/output .
• Output can .drlvebusdlrectly;.IOL32 m4,(com)~ 241QA (mil)
• Registersllatches ccinfigurable for no.se-to~tall or side-bySide operation .
., .
• IndlVt!:k!al clocklgate ~mables for each rarlk
• Registers for plpellned arithmetic ~nlts ~r.i:tlglta.·slgnal
Proceil8Ors
,'
.'
.
• Bus monitOr for popular 8-blt inl~oprociSSO'" to restart
InstruCtIons uponvlriual memorYPaue fault·
.
• Vldeodlsj)lay char8~r!attributepIPelinec:l registers
• Sequencelstatege.,.;atOr forsyslems: dual-rank reglstersl
latches allow storing a backup previous stata for .
redundancy. or diagnostics·
• Two-stage buffar for plpell.ned Interlacing Input/output

Description

.

.;-,

.'

;

NU"'IJ~R

PKl through the ~,,"e.
The arr~~gement ofregistets!latch~ within the;LS548j'LS549
can tJetflQ!Jght of a two8.:.bit storage ranks, rank. 1aJ,drank 2.
The 'L5543 has cOlf1rnonclook line CK, and separate clock
enablesCKE1ariWllentllUhe
in.rank
1 on, thepQIIllive
edge
QfOK.
if.,.'CKE1"has
i;leenpreviously
•. '
.,
""
'.
e.;-'· <

SKINNYDIP8 is a regist~~ trad~;"arl< of Monolithic Meniorie~

. TWX; 910-338-2376
2175 Mission College Blvd. Santa Clara, CA.95054,1592 Tel: (408) 970'9700 TWX:' 910-3M-2314

12·62

MonolIthIc mllll
Memorl•• IrUlUI

,

:i
!

SN54/74LS548 SN54/74LS549
Block Diagrams
'LS549

'LS548

D7-DO

D7-DO

INSEL

INSEL

CK

G

G2

OUTSEL

OUTSEL

OE

Oi

Y7-YO

Y7-YO

Typical Configurations.

INSEL = L

D7-DO

RANK 1
Q

D

RANK 2
Q

CKE1/G1

Y7-YO

D

CKE1
(G1)

D7-DO

CK/G
INSEL = L

OUTSEL =l

I--D........,~

CK/G

OE

INSEL= H

(8) Nose-to-Tail

(b) Side-by-5lde

Figure 1

Y7-YO

SN54/74LS548 SN54/74LS549
Function Table Nomenclature
Description

I = Positive edge of CK causes clocking,
if clocking is enabled.

D
V

00

54n4LS548.
CKE1/CKE2 = Clock enable line for the rank 11
rank 2 register in the 54n4LS548.

= Data at the. Do-D7 input pins.
= Data at the Vo-V7 output pins.

X = H or L state irrelevant ("don't care"
conditions)

CK

CKE1

CKE2

RANK 1

RANK 2

LorHorl

X

X

Disabled

Disabled

I

L

L

Enabled

Enabled

I

L

H

Enabled

Disabled

I

H

L

Disabled

Enabled

X

H

H

Disabled

Disabled

= Previous states of the internal
registerllatch data are retained.

Z = Indicates that the Vo-Y7 outputs are
in high-impedance state.
INSEL = Input select mux control pin; determines the source of input data for

rank 2.

.

INSEL

flANK 2 INPUT

L

Rank 1

H

D

G = The common latch control line for
the 54n4LS549.

G1/G2 = Latch enable line for the rank 1/
rank:1 latch in the 54n4LS549.

G
OUTSEL = Output select mux control pin; selects either rank 1 or rank 2 for
output

OUTSEL

OUTPUT

L

Rank 2

H

Rank 1

OE = Output enable pin.

12·64

= The common clock line for the

CK

Rank 1-0 or Rank 2-0 = Data available at the internal flipflopllatch outputs for the 8 rank 1 or
rank 2 registersllatches respectively.

OE

OUTPUT

L

Rank 1 or Rank 2

H

Hi-Z

G1

.G2

RANK 1

RANK 2
Enabled
(Flush)

L

L

L

Enabled
(Flush)

L

L

H

Enabled
(Flush)

Disabled
(Freeze)

L

H

L

Disabled
(Freeze)

Enabled
(Flush)

L

H

H

Disabled
(Freeze)

Disabled
(Freeze)

H

X

X

Enabled
(Flush)

Enabled
(Flush)

SN54/74LS548 SN54/74LS549
~.

; 'LS548 Function Table
CK

;

;

LorH
or I

I

,I
!

.. ,
I

t
t
t
t
t
t

CKE1

X

RANK 1
00

'LS549 Function Table
··INSEL

CKE2

X

X

RANK 2
00

H

00

H

X

L

0

H

X

00

L

0

L

L

Rank 1-0

L

0

L

H

0

H

00

l

L

Rank 1-0

00

L

H

0

H

00

0

01

RANK 1

02

INSEL

RANK 2

L

L

0

L

L

Rank 1-0

L

L

0

L

H

0

L

L

0

H

X

00

L

H

00

L

L

Rank 1-0

L

H

00

L

H

0

L

H

00·

H

X

00

H

X

0

X

X

0

!

'LS548/549 Output Function Table
OUTSEL

,

y

OE

L

L

H

L

X

H

Rank 2-0
.

Rank 1-0
Hi-Z

12-65

SN54/74LS548 SN54J'74LS549
Logic Diagram
54/74LS548 PlpelineciRegister

CK

CKE1

OUTSEL

INSEL

DO

D1

YO

D2

Y1

D3

Y2

D4

Y3

os

Y4

Y5

Y6

Y7

12-88

I

SN54/74LS548 SN54/74LS549

Logic Diagram
54/74LS549 Pipelined Latch

INSEL

DO

01

02

Y1

Y2

D4

Y3

Y4

De

Y5

07

Y6

GNO

12-67

SN54/74LS548 SN54/74LS549
Pin Configurations
'LS548

'LS549

De
YO
Y1

Y1

Y2

Y2

Y3

Y3

Y4

Y4

Y5

06

Y5

06

Y6

GNO

Y8

GNO

Y7

Y7

IEEE Symbols
'LS548

'LS549

OE

OE

OUTSEL

OUTSEL

INSEL

INSEL

CKE2

G2

Cffi

G1

CK

G
6

00

'6

02

04
05
06
07

12-68

20

7'\1
19

01

03

t>

8

18

7

17

8

16

9

15

10

14

11

13

YO
Y1

19

01

Y2

02

Y3

03

Y4

·04

Y5'

05

Y8

06

Y7

20

00

07

18
7

17

8

16

9

15

10

14

11

13

YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7

SN54/74LS548 SN54/74LS549
Absolute Maximum Ratings
Supply voltage VCC .•..........•........•....••......•...•......••..•..•......•........••••.•••...••..........•..• 7.0 V
Input voltage ••••.•.....•...•........•.....•..............•.•......•.•.. '.' ....... ; .......•.•..•.•.••...•.•...•••.. 7.0 V
Off-state output voltage ...•................•.•••...•........•...•........•...•.....•••••.•....•••.••.....•••••••.. 5.5 V
Storage temperature .....................................................................................-65° to +150°C

Operating Conditions
SYMBOL

MILITARY
MIN TYP MAX

PARAMETER

VCC

Supply voltage

4.5

TA

Operating free-air temperature

-55

High
Width ·of CK, G,

tw

G1, G2
Low

Setup time for D, G, GX

tsu

'LS548

CK

'LS549

G

15

5

COMMERCIAL
MIN TYP MAX

5.5

4.75

125

0
11

'LS548

CK

15

11

'LS549

G1,G2

18

16

'LS548

CK

201

151

'LS549
'LS548

G

101

61

G1,G2

171

41

CK

01

01

G

121

101

G1,G2

51

5

5

UNIT

5.25

V

75

°c
ns

ns

ns

th

Hold time for 0, G, GX

tsu~CKEX

Setup time for clock enables CKE1, CKE2 (,LS548 only)

151

101

th-GKEX

Hold time for clock enable CKE1, CKE2, (,LS548 only)

81

51

ns

tsu-INSEL

Setup time for INSEL1

30

25

ns

th-INSEL

Hold time for INSEL2

0

0

ns

'LS549

ns

ns

NOTES: 1. This is the minimum setup time needed lor INSEL prior to the rising edge of the clock/GX, and to the falling edge of the G, to ensure data transfer to
rank 2.
2. This Is the minimum hold time needed lor INSELafterthe rising edge of the clock/GX, and tothe falling edge 01 the G, to ensure data transfer to rank 2.

II

the arrow indicates the transition 01 the clock/gate Input used for reference:

I
I

for the low-to-high transitions,
for the high-to-Iow transitions.

12·69

SN54/74LS548 SN54/74LS549
Electrical Characteristics Over Operating Conditions
SYMBOL

PARAMETER

VIL

Low-level input voltage

VIH

High-level input voltage

Vie

Input clamp voltage

Vee = MIN
Vee = MAX
VI = 0.4 V

IIH

High-level input current

Vee = MAX

II

Maximum input
current

VOL

Low-level output voltage

High-level output voltage

10ZL
Off-state output current
10ZH

Vee = MIN
Vee = MIN
VIL = MAX
VIH = 2 V
Vee = MIN
VIL = MAX
VIH = 2 V

-1.5

-1.5
-250

All others

-400

-400

20

20

f.!.A

0.1

0.1

mA

VI=2.7V

Vee = MAX
Outputs open

0.35

10L = 32mA

f.!.A

0.5
V

0.5

10L = 24 mA
10H = -1 mA

2.4

3.4
V
2.4

10H = -2.6mA

Vo = 2.7 V

Supply current

V

VI = 7 V

VIH = 2 V

lee

V
V

-250

11=-18mA

Vo = 0.4 V

Vee = MAX

UNIT

DorY

Vee = MAX
VIL = MAX

Output short-circuit current*

0.8
2

VI = 5.5 V

lOS

-20
-30

-130

-30

3.1

-20

f.!.A

-130

mA

'LS548

150

150

'LS549

160

160

Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

12-70

COMMERCIAL
MIN TYP MAX

0.8

Low-level input current

I DorY
I All others

MILITARY
MIN TYP MAX

2

IlL

VOH

*

TEST CONDITIONS

MonoIHhlcWMemorlefi

mA

SN54J'74LS548 SN54J'74LS549

Switching Characteristics vcc = 5 V, TA = 25"~
SYMBOL

TEST CONDITIONS
(s.. Teat Load/Waveforms)

PARAMETER

fMAX.

Maximum clock frequency

tPLHItPHL

CK, G1, or G2to output delay

tPLHItPHL

G to output delay (,LS549)

tpl.H/tpHL

Data D to output delay (,LS549)

tPLHItPHL

Output multiplexer control
OUTSEL to output delay

'LS548
MIN
MAX

'LS549
MIN
MAX

50

UNIT
MHz

18

22

ns

23

ns

16

ns

20

20

ns

CL = 45 pF, RL = 2800
OE=L

"

tpZLltpZH

Output enable delay·.

CL = 45 pF, RL = 2800

18

18

ns

tpLZltpHZ

Output disable delay

CL = 5 pF, RL = 2800

15

15

ns

::

Switching CharacteriStics'. Over Operating CondlUons

fMAX

Maximum clock frequency

. tpLH/tPHL CK, G10rG2
to output delay

..

(SaeTea'
LosdiW...Io.....)·

PARAMETER

COM

MIL

TEST CONDitiONS
SYMBOL

~.LS548

'LS549
MIN MAX

MiN MAX

'L$549
MIN MAX

45

33

.

'L$548 '
MIN MAX

26

25

UNIT'
MHz

....

24

ns

28

25

ns

24

18

ns

22

ns

20

20

ns.

17

17

ns

20

'

tpLH/tpHL G to Output delay (,LS549)

CL = 45pF

.Oata 0 to output
tpLH/tpHL delay (,LS549)

RL = 2800
5E=L

'Output multiplexer. dOhtrol
tpLHftpHL OUYSEL tooutPlit delay
tpZL/tpZH Output enable

del~'y

tpLz/tpHi Output disable delay
.'.

,

I
27

27

CL =45pF
RL = 2800

23

23

CL =5pF
RL= 2800

20

20

22
..

....

12;'71

SN54/74LS548 SN54/74LS549
Teat Waveforms

'LS548··

Setuj)liild Hold

. CK toOt,.ltput Delay
CK

DATA

/
_---J

\\.-._-DATA

CK

OUTPUT

INSEL

G to Output Delay

DATA~.

Setup and Hold

'LS549

----~----------~~---~-----------3V

\'-------

G
'--..,.;----~--OV

~-------------3V

ox

G

~----------------J+---------------ov

DATA

OUTPUT·

INSEL

\

'su-INSEL

'h-INSEL

vT = 1.3 V
Data D to Output Delay
r---~----,-~---------3V

DATA

'-----------0 v

G

r--~+_-_.-----3V

OUTPUT
OV

12·72

SN54/74LS548 SN54/74LS549
Test Load
OUTPUT
ENABLE
(Low-level
enabling)

TEST POINT"

1 r - - - - 3V

'-------9----- OV
51 and

S1

CL
(SEE NOTE A)

WAVEFORM 1
(See Note A)

I

WAVEFORM 2
(See Note A)

J

51 open
52 closed

VT =1.3V

'LS5481549 Enable and Disable

S2

• The "TEST POINT" is drived by the output under test,
and observed by instrumentation.

Load Circuit for Three-state Outputs
NOTES: A. CLincludes probe and Jig capacitance.
B. All diodes are 1N916 or 1N3064.

C. Waveform 1 is for an output with internal conditions such that the output is low except when
disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when

disabled by the output control.

D. In the examples above, the phase relationships between inputs and, outputs have been
chosen arbitra~.ily.

E. All input pulses are supplied by generators having the followi~g charactt;lristics:
PRR ,; 1 MHz, Zout = 50 nand:
F. When measuring propagation delay times of 3-state outputs. switches 81 and 82 Bre ·closed.

Die Configurations
SN54/74LS548

SN54174LS549

04

I

.1

D6

07

GNO

Y7

Y6

Y5

Die Size: 89x150 mil2
I
I

MonolIthic

m

lIIIemories

12·73

8·BitLatchl Register
with Readback
SN54/74LS793 SN54/74LS794
Features/Benefits

Ordering Information

• 1/0 port configuration enables output data back onto
input bus
..

PART
NUMBER

PKG TEMP POLARITY

TYPE

SN54LS793
SN74LS793

J,W,L
N,J

Mil
Com

Latch

SN54LS794
SN74LS794

J,W,L
N,J

Mil
Com

POWER

• 2o-pln SKINNYDIP@ saves space
• S-blt data path matches byte boundaries
• Ideal for microprocessor Interface

Description
These 8-bit latches/registers are useful for I/O operations on a
microprocessor bus. An image of the output data can be read
back by the CPU. This operation is important in control algorithms which make decisions based on the previous status of
output controls. Rather than storing a redundant copy of the
output data in memory, simply reading the register as an 1/0 port
allows the data to be retrieved from where it has been stored in
an 'LS793/4, for verification and/or updating.

Noninvert

LS
Register

• W (Cerpak).p (Side-brazed ceramic dual-in-line) packagesarealsoBllaiiable
fer both parts.

Logic Symbols
'LS794

'LS793

The data is loaded in the registers on the low-to-high transition
of the clock (CK), for the 'LS794. The <;lata is passed through
the 'LS793when the gate, (G), is High, an<;l it is "latched" when G
changes to Low. The output enable, OE is used to enable data on
07-00. Whim OE is low the output of the latches/registers is
enabled on 00-07, enabling 0 as an output bus so that the host
can perform a read operation. When OE is High, 07-00are inputs
to the latches/registers configuring. Oas an input bus.
The output drive of these commercial parts for any output pin
is 10L = 24 rnA. They are available in .the popular 2O-pin
SKINNVOIP@ package.

'LS 793 Function Table
G
L
L
Ht
H

OE
.'

.

L
H
L
H

'.

'.

Q

00"
00"
0'

D

D
Output, 0
Input
Output, 0'
. Input

{,'_"'J

*

In this _case the output of the - latch ,--feeds the input,_ and s· "race"
condition results .

'LS794 Function Table
CK

OE

Q

Lor H or ~
LorHor.1

L
H
L
H

00
00
00
0

I
I

'.

D
Output, 0
Input
Output,O'
Input

• In this case the ou~put of the register is clocked to the inputs and the overall
Q output is unclianged_'at Q O'

•• 00 represents, the_ prev.iOus ''',latChed'' state~

t This transition is not a normal mode of op~uation and may produce hazards.
SKINNYDIP@ is a registered trademark of Monolithic Memories.

TWX: 910c338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910.-338-2374

12-74

MonolithIc mT!n
MemorIes InJn.LI

SH.54/74LS793 SH54/74LS794

IEEE Symbols

'LS793

9l
G

DO

D1
D2
D3
D4

D5
DB
D7

1
11

'LS794

...... J EN2

2

L

ai1
1D

t>

'\12



'\12

 Note A)

Sl AND S2 CLOSED

For the 'LS793, the latch control "G" should be low while testing
the enable and disable times, so thai the output (0) does nol
change. (VT = 1.3V).

* The "TEST POINr is drived by the output under test.
and observed by instrumentation.

MonoIlthIo

NOTES: A. Waveform
the output
waveform
the output

W lIIIemories

1 is for an output with internal conditions such that
is low except when disabled by the output control.
2 is. for an output with internal conditions such that
is high except when disabled by the output control.

12-77

SN54/74LS793 SN54/74LS794
Die Configurations

'LS793

'LS794

12-78

IIIIonoIllhlc

WlIIIemories,

,I

8-Bit Diagnostic Register
SN74S818
Features/Benefits

Ordering Information

•
•
•
•
•
•

High drive capability: IOl = 32 mA (Com), 24 mA (Mil)
Assists on-lIne and off-line system diagnostic testing
Swaps the content of shadow register and output register
Shadow register for dlagnOBllc t.lling
Edge-triggered "0" registers
Cascadable for wide control words as used In
microprogramming
• Features RAM write-back for wrlteble control store
InltlalizaHon
• PNP Inputs for Iow-lnput current
• 24-pln SKINNYOIP® saveS space
• 8~bit data path matches byte boundaries

*

PART NUMBER

PACKAGE

TEMPERATURE

SN74SS1S*

NS,JS

Com

Contact the factory for miliatry version.

Block Diagram

07-00

SOl --'..,..,.----;~

1--+-+--....

OCLK --..,+--t--Po

Applications

SOO

• Register for microprogram control store' ,
•
•
•
•
•
•
•
•

Status register
Oata register
Instruction register
Address register
Interrupt mask regiller
Pipeline register
General purpose register
Parallel-serlallserlal-parallel converter

Description

&-BIT
CLK----+ OUTPUT
REGISTER

The SN74SS1S is an S-bit register with diagnostic features.
There is a shadow register in each diagnostic register. Diagnostic data is shifted in serially into the shadow register (S7-80),
while the output register is loacled with either the content of the
shadow register or the input data (07-00). Moreover, D7-00 can
also be used as the outputs from tlie shadow register to the data
bus, while the outputs (B7-BO) can also be converted to inputs
when disabled.

E"-.:....---4V

B7-BO

Function
Table
. -INPUTS

8

MOOE~----~-~

OUTPUTS
OPERATION

MOOE

SOl

ClK

l

X

I

.

Bn'- On

l

X

*

t

L

X

t

H

X

*

B7-BO

SEE
FIG.

S7-S0

SOO

HOLD

S7

load output register from input bus

1

HOLD

Sn- Sn-1
SO- SOl

S7

Shift shadow register data

2

t

Bn- On

Sn-Sn-1
SO- SOl

S7

Load output register frorn input bus
while shifting shad,ow register data

1&2

I

*

Bn-Sn

HOLD

SOl

Load output register from shadow register

2,3,4

L

*

t

HOLD

Sn- Bn

SOl

Load shadow register from output bus

H

L

t

Sn- Bn

SOl

Swap shadow reg1stli!! and output register

H

*

t
t

Bn- Sn

H

HOLD

HOLD

SOl

Enable 07 -DO as outputs for RAM write-back

H

DClK,

.,

3

4

Clock must be steady or falling,

SKINNYDIf'<'> is a registered trademark of Monolithic Memories
Diagnostic On-Chip'· and DOC'" are trademarks of Monolithic Memones
TWX: 910-338-2378
2175 Milll!lon College Blvd. Santa Clara, CA 95054.1592 Tel: (408)970"9700 TWX: ,910-338,-2374

IIIIonolllhic ~T!n
MemorIes InJn.LI

SN74S818

Logic Diagram

vee

MODE

BO

81

82

B3

B4

B5

B6

87

$00

eLK

12-80

SN74S818

Absolute Maximum Ratings

Operating

Supply voltage VCC .............................................................................................. 7.0 V
Input voltage. ", .................................................................................................. 5.5 V
Off~state output voltage ........................................................................................... 5.5 V
Storage temperature ......................................................................................-65 to + 150" C

Operating Conditions
PARAMETER

SYMBOL

t

MIN

COMMERCIAL
TYP

MAX

5

5.25

V

75

·C

VCC

SUpply voltage

4.75

TA

Operating free-air temperature

0

tw

Width of ClK

twd

Width of DClK

UNIT

High

12

low

13

ns
ns

High

20

ns

low

20

ns

171

ns

tsue

Setup time from MODE to ClK

the

Hold time from ClK to MODE

tsud

Setup time from data to ClK

141

ns

thd

Hold time from ClK to data

01

ns
ns

" 01

ns

tsude

Setup time from SDI, MODE to DClK

20 I

thde

Hold time from DClK to SDI, MODE

01

ns

tsudq

Setup time from output to DClK

181

ns

thdq

Hold time from DlCK to output

01

L The arrow indicates the transition of the clock/gate input used for reference: t for the low-ta-high transitions.

ns
, for the high-la-low transitions.

12-81

SN74S818

Electrical Characteristics Over Operating Conditions
SYMBOL

VIL

PARAMETER

TEST CONDITIONS

High-level input voltage
Input clamp voltage

Vee = MIN

II = -18 mA

IlL

Low-level input current

Vee = MAX

IIH

High-level input current

Vee = MAX

II

Maximum input
current

10ZL
10ZH

Low-level
output voltage

High-level
output voltage

2

o or B
All
others
B7-BO

*

0.8

VIH

VOH

COMMERCIAL
TYP
MAX

Low-level input voltage

Vie

VOL

MIN

SOO
07-00
B7-BO
SOO
07-00

Off-state
output current

V
V

-1.2

V

VI = 0.5 V

-0.25

mA

VI = 2.7V

50

fJ.A

1

mA

VI= 5.5 V
Vee = MAX
VI = 7V
0.5

10L = 32 mA
Vee = MIN
VIL = MAX
VIH =2V

10L = 24 mA
0.5

10L = 8mA

V

10L = 4 mA
Vee = MIN
VIL = MAX
VIH =2V
Vee = MAX
V IL = MAX
VIH =2V

10H = 6.5 mA
2.4
VO=0.5V

-250

fJ.A

VO=2.4V

50

fJ.A

Output short-circuit current'

Vee = MAX

lee

Supply current

Vee = MAX. Outputs open

-40

Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

Monolithic

V

10H = -2 mA

lOS

12·82

UNIT

W lIIIemories

115

-100

mA

145

·mA

SN74S818
Switching Characteristics vcc = 5 V, TA = 25°C
SYMBOL

fMAX

TEST CONDITIONS

PARAMETER

(See Tes' Load/Waveforms)

CL = 50 pF RL = 2800 OE = L

Maximum output clock frequency

fMAXO

Maximum diagnostic clock frequency

tCLK

CLK to output delay

tss

SOl to SOO delay (MOOE = HIGH)

tMS

MOOE to SOO delay

tos

OCLK to SOO delay (MOOE = LOW)

I

MAX

CL = 5.0 pF RL = 2 K.o

UNIT

MHz

40
20

Cascaded
Uncascaded

MIN

MHz

25
14

ns

12

ns

17

ns

28

ns

25

ns

tOEZH

20

ns

tOOLZ

36

ns

60

ns

CL = 50 pF RL = 2800 OE = L

CL = 50 pF RL = 2 K.o

tOEZL
OCLK to 07-00 enable delay

CL = 50 pF RL= 2 K.o

CL = 5 pF RL = 2 Kn

OCLK to 07-00 disable delay

tOOHZ
toc

OCLK to CLK separation

tco

CLK to OCLK separation

ns

22
CL = 50 pF RL = 2800 OE = L

ns

35
19

ns

tpZH

13

ns

tpLZ

12

ns

22

ns

tpZL

Output enable delay

CL = 50 pF RL = 280.0

Output disable delay

CL = 5 pF RL = 280.0

tpHZ

Switching Characteristics Over Operating Range
SYMBOL

TEST CONDITIONS

PARAMETER

(See Tes' Load/Waveforms)

fMAX

Maximum output clock frequency

fMAXO

Maximum diagnostic
clock frequency

CL = 50 pF RL = 280.0 OE = L

Cascaded
Uncascaded

tCLK

CLK to output delay

tss

SOl to SOO delay (MOOE = HIGH)

tMS

MOOE to SOO delay

tos

OCLK to SOO delay (MOOE = LOW}

MIN

COMMERCIAL
MAX

MHz

40
20

CL = 50 pF RL = 2 KO

MHz

25

CL = 50 pFRL = 2800 OE = L

CL =50 pF RL =.2 KO

tOEZL

UNIT

14

ns

15

ns

18

ns

30

ns

25

ns

tOEZH

25

ns

tOOLZ

45

ns

80

ns

OGLK to 07-00 enable delay

OCLK to 07-00 disable delay

tOOHZ
toc

OCLK to CLK separation

tco

CLK to OCLK separation

tpZL

CL = 50 pF RL= 2 KO

CL = 5pF RL = 2 KO

.
CL = 50 pF RL = 2800 OE = L

Output enable delay

CL= 50 pF RL = .2800

Output disable delay

CL = 5 pF RL = 2800

tpZH
tpLZ
tpHZ

MonoIIthIoW.emorles

30

ns

40

ns

20

ns

15

ns

15

ns

25

ns

SN74S818

Timing Waveforms

ClK

MODE

07-00

87-80

VT

=1.5 V

Figure 1. Switching waveforms for typical register applications (OE = L)

•
OClK

•

Iwd(lOW)

•

Iwd(HIGH)

-IlvT

VT

VT

~

..

•

10C

. ..

....de
MODE

'

~ Ir-VT

.

~VT
j 1\

SOl

,

-~

•

.

~

~r-VT

- " u e - ~tr.c---

jllVT
....de

500

"'de

...-----.

-,IlVT
j

ClK

.

Iw(HIGH)

lOS

VT

'~

tVT

-

VT
VT = 1.5 V

Figure 2. Switching waveforms for shift-in followed by diagnostic load

12·84

IWonoIIthIe

mill Memorle.

SN74S818

Timing Waveforms

I

~.

ClK

-5 VT
VT

•

OClK

~-------------------------------------------------------ICO

~

•

-l-VT

-'~VT
lweI(lOW)

..

.

~~
IweI(HIGH)

- 'f-VT

SOl

. VT
~

MODE

SOO

.

•

100

T'J
V
I
.1~r-------"UdqlC-.---""'--". .r------Ihclq.--'-----+l~
' B7-BO------*-V-T--------'------------------*-V-T-----

i

07-00
(AS

OUTPUTS)

(.01

•

VT = 1.5 V
!

Figure 3. Switchin9 waveforms for data bus (07-00) disabling

12·85

SN74S818

Enable/Disable Delay

,------------------3 V
VT

OUTPUT ENABLE

~--------------Jr--------------------OV

WAVEFORM 1
,(See Nota,CI

\..~

__ ______
~

____ 1:5 V
-J1-=~=====~5V

VOL

(;.;------~------~lt====~~=VOH
--1.5V
~5V

WAVEFORM 2
(See Nole CI _ _ _ _ _ _ _ _J.

S1AND
S2CLOSED

Teat Load
TEST POINT"

CL

(SEE NOTE AI

*

I

RO
1K

The "TEST POINT" is drived by the output under test.
and observed by instrumentation.

NOTES: A. 'CL in.cludes probe and jig capacitance.
B. All diodes are 1N916 or 1N3064.
C. Waveform 1 Isfor an output with internal conditions such that the
output is low except when disabled by the output control.
WaY~form 2 is for an output with internal conditions such that the
output is high except when disabled by the output control.
D. In the examples above the phase relatio.nships between inputs
and outputs have been chosen arbitrarily.
E. All input pulses are supplied by generators having the following
characteristics: PRR S 1 MHz Zout =
and
for series 54n4S tR =2.5 ns tF S 2.5 ns.

son

F. When measuring propagation delay times of 3-state outputs,
switches S1and S2 are closed.

G.

12·86

B7-BO

07-00,500

1 Kn

SKH

SN74S818
a) Output ofthe preceding bit ofthe shadow register (or SOl for
the least significant bit).
b) Output of the same bit of the shadow register.
c) Data on the output pin of the same bit. This data may be the
output of the corresponding bit of the output register if there is
no output enable pin and the output is enabled. or the input to
that pin if there is an output enable pin and output is disabled.
Refer to Figure 6 for some general informatt2!!. on a typical
diagnostic functional part with output enable (OE).

Basics of Diagnostics
The basic theory of diagnostics is to insert test data to the inputs
of a typical system and sample the test results from certain
nodes of the circuits. For a combinatorial circuit. testing is very
easy since the circuit has no memory of the previous states. But
for a sequential circuit. the data to be sampled at a node depends
not only on the inputs. but also on the current state it is in. If the
previous state contains some error. it will possibly perform an
illegal jump. In that case. depending on which state the system is
currently in. the next state may be different. After several illegal
jumps. it will be quite impossible to keep track of the jumps
which it performs.
A way to solve the problem is by converting a sequential circuit
to a combinatorial one. A sequential circuit can often be viewed
as a network with a clock and a number of inputs and outputs.
with some outputs being routed back to the inputs (see Figure
5a). If the loop is broken and inputs which are fed back from the
outputs are instead fed in from some external sources (see
Figure 5b). the system can be viewed as combinatorial and
system testing will be easier. The "shadow register" concept
involves shifting in serial data to the hidden register (the shadow
register) and then loading test data to the output register.
Together with other system inputs. the test results will appear on
the output end of the network and can be sampled and analyzed.
and analysed.

'1

•

SOl

DLCK

1---t----1r-..... SDo

MODE~~-----~

elK - - - - - f "

.~ CL-_N_ETWO
__ ~~

OE---~~-----~

R_K_ _

OUTPUTS
B LINES, BI.DIRECTIONAl
(IF OUTPUT BUFFERS ARE
THREE-STATE)

Figure Sa. A typical digital system

~ CL-.;..._N_ETWO
__

§~

Figure 6. A typical functional block diagram
lor a diagnostic part

R_K_ _

Figure 5b. The feedback of figure Sa is broken to convert the
system to a non-sequential one

Diagnostic On·ChipTM (DOCTM) Using
Shadow Register
The diagnostic register is an B-bit register with two levels of
registers-a shadow register and an output register. A shadow
register is basically a buried register with shift capability. There
is also an output register whose outputs appear to the rest of the
system. There is an output flipflop to each shadow flipflop. An
output flipflop drives a three-state output buffer before going to
the output pin. If the output is disabled. the output pin may be
converted to an input pin. This feature is very important if the
output is driving a bus and sampling of data on the bus is
desired.
I

The input to a bit of the shadow register is a multiplexer which
can select from one of the following nodes:

Monolithic

The input to any bit of the output register is also selected from
one of the following nodes:
a) Corresponding input bit.
b) Corresponding output bit of the shadow register.
The.reasonswhy a shadow register is preferred, as compared to
shifting in diagnostic data directly to the output register, are:
a) The output register contains control Signals for the system.
Certain bits of this register may control different ports which are
driving the same bus. As diagnostic data is shifted in. these bits
become random and the ports they are controlling may drive a
bus simultaneously. Invalid data may appear and worst of all,
with a lOW-impedance path between the power supply. severe
damage may be done to these ports;
b) As a diagnostic word is shifted in, the system is performing
different tasks from what it is supposed to do. For example,
when an ALU is performing an addition. diagnostic data is
Shifted in. The ALU then performs some other functions. The
status of the system keeps changing. In some cases. illegal
states may appear which produces unpredictable test results;
for example. a flag may appear unpredictably.
C) The shadow register enables diagnostic data to .be shifted in
as background data without holding up the processor operation.

W Memories

12·87

SN74S818
The diagnostic register is one part in a series of diagnostic
products which follows a new standard for diagnostics. The
basic standard is described in Figure 6 and the table on page one.
This standard implies that all diagnostic parts in this series are
cascadable.

Diagnostic Pins
There are several pins in the diagnostic register in addition to the
regular 8-bit inputs and outputs:
1) Diagnostic Clock (DCLK)-The diagnostic clock is used to
clock the shadow register.
2) MODE-This pin is used in selecting the data to the registers. For the output register, MODE = LOW indicates that the
output register is being used as a normal register; MODE =
HIGH means that the next state of the output register will be
obtained from the shadow register. For the shadow register,
MODE = LOW indicates serial data from SDI (see below) is
shifted in every diagnostic clock; MODE = HIGH switches SDI
from a data input to a control input. See below for details.
3) Serial Data In (SDI)-When MODE = LOW, this pin is for
shifting serial data in. When MODE = HIGH, SDI serves as a
control pin. If MODE = HIGH and SDI = LOW, data from the
output pins will be loaded to the shadow register on the next
DCLK. MODE = HIGH and SDI = HIGH indicate a reserved
operation. The data from the diagnostic clock is held the same.
This reserved operation will be very significant when more
operations than what is described are needed. The diagnostic
register gives an example of how it can be used.
4) Serial Data Out (SDO)-When MODE= LOW, this pin carries
the shift-out bit of the shadow register. When MODE = HIGH,
the SDI becomes a control pin and the control signal should be
passed along if several diagnostic parts are connected together serially. So SDO should carry SDI along in this case.

Write-Back to RAMs
Due to the applications of a diagnostic register in a writable
microprogram control store, this part also includes an additional feature to initialize the control RAMs; when necessary, the
input data pins to the register can be operated as output
pins. In short, a diagnostic register is an 'asymmetric register
transceiver' with shift capability. The term 'asymmetric register
transceiver' means that there are two bidirectional registered
ports on a chip, and these ports are enabled with different
methodologies and have different timings. One port is still
primarily for inputs (D7~DO), while the other is primarily for
outputs (87-80).
When MODE and SDI are both HIGHs, the 07-DO will be
converted to an output port on the riSing edge of the next
DCLK by enabling the three-state buffers driving the D7 -DO.
The input for the three-state buffers is from the outputs of the
shadow register (S7-S0).

12-88

Applications
This part can be used as a: microprogram control store register,
data register, status register, address register, instruction register, interrupt mask register, interrupt vector, program counter,
stack pointer, and for other general purposes.
If the diagnostic registers are used in a system using microprogram control words, status registers, and instruction registers, etc., one way to connect them together is shown in Figure
7. There is only one data input and one data output to the
diagnostic parts. When serial data is shifted in or shifted out,
data has to be passed from one diagnostic chip to another.
Since SDI must be passed from chip-to-chip if it is used for
control, it is necessary for logic designers to make sure the
fall-through time of SDI to the last chip and the setup time from
SDI to DCLK are satisfied.

TEST
DATA
OUT

Figure 7. One way diagnostic registers can be linked together

The diagnostic registers are basically used for diagnostic purposes, although they may also function as parallel-to-serial
and serial-to-parallel converters.
Two e~amples of how the diagnostic parts can be built into a
system are shown in Figures 8, 9. The diagnostic registers are
used to substitute the instruction register, memory data registers,
status register, memory address registers, and the registers for a
non-writable (Figure 8) or awritable (Figure 9) microprogram
control store. The only additional block to a typical system
without diagnostic features is the diagnostics controller. The
diagnostics controller shOUld be able to supply the system with
signalS like MODE, SDI, DCLK, and the register clock (CLK).ln
order words, the diagnostics controller in itself is a supercontroller
of the processing unit. It should also be noted that all sequential
paths, except for the register files, should be converted to
combinatorial paths if all the diagnostic parts are to break the
sequential lOOps.

MonolIthic WMemorles

SN74S818

Figure 8. An application example of using diagnostic registers in a CPU using non-writable control store

Figure 9. An application example of using diagnostic registers in a CPU using writable control store

Mono/lth/o

W Memories

12·89

5N745818
In normal operation, the diagnostic controller will make the
diagnostic feature inactive by setting MODE = lOW and disabling DClK anc! have the ClK free running.
When diagnostics are needed, the following sequence is performed:
1) Shift in diagnostic test data bit-by-bit. In order to perform this
operation, ClK is disabled; MODE remains lOW; SDI contains
the bit to be shifted in, and the diagnostic clock is enabled. This
will continue until a full test vector is shifted into the shadow
register.
2) MODE switches to HIGH. Then DClK is disabled and ClK
is enabled. The contents of the shadow register, which is the
test vector, will be loaded into the output register.
3) The test result is set up at the inputs of the diagnostic
registers. MODE switches to lOW again. DClK is still disabled
and ClK is still enabled. The test result will be clocked into the
output register.
4) With MODE HIGH and DClK enabled and ClK disabled
'
the test result will be clocked to the shadow register.
5) With MODE held lOWand DClKstili enabled and ClKstill
disabled, the test result can be shifted out and analyzed while
another test vector is shifted in.

through the diagnostics controller. What this controller must
be able to do, in addition to what is described above (see
Figure 10), is to disable the outputs from the microprogram
sequencer and feed in the address through another diagnostic
register. There is a switch, S1, which switches the SDI to the
registers of the writable control store from some other register (in Figure 9, it is the memory address register) to the
diagnostic 'control store address' register. The initialization
data is shifted into the shadow register by resetting MODE to
lOW and enabling DClK. After all data is shifted into the
shadow register, MODE and SDI are set HIGH and then followed
by a ClK, a DClK, and a write to control store. The ClK loads
the present control store address in the output registers of the
'control store address' register, and the MODE= HIGH and SDI =
HIGH will enable the inputs to the diagnostic register as outputs,
so that the data in the shadow register can be written back to
the control store.
I-------_+_MOOE
RESET_
OTHER
CONTROL
SIGNALS
CLOCK

CENTRAL
CONTROL
UNIT

I-------_+_SOI
EXTENOOClK
OClK
EXTENOClK
ClK

A block diagram of such a diagnostics controller is shown in
Figure 10. The central control unit of this controller may be a
disk-based unitoreven a diagnostic PROM. Note that, in normal
operation, MODE remains lOW and only ClK is active.

SOO

Figure 9 is an example with writable programmable control
store where initialization of the control RAMs is necessary.
This can be done by loading in a sequence of data and address

Figure 10. A diagnostic controller unit

Die Configuration

Die Size: 92x112 mil2

12-90

IIIIonoIHhlc

W Memories

a-Bit Bus Front-Loading Latch
Transceivers Advanced CMOS-TTL Compatible
54/74ACT646

54/74ACT648

Features/ Benefits

Ordering Information

• Bidirectional bus transceiver and register

PART
NUMBER

PKG

54ACT646

JS,W,
L28

Mil

• Three-state outputs drive bus lines

74ACT646

NS,JS

Com

• Low quiescent supply current of <10 p.A (typical)

54ACT648

JS,W,
L28

Mil

74ACT648

NS,JS

Com

• Independent registers for A and B buses
• Real-time data transfer or stored data transfer
• 24-pin SKINNYDIP® saves space

Non-invert
3-state

• Active supply current at about 20% LS equivalent
• Wide commercial operating supply and temperature
ranges 4.5 V to 5.5 V; -40°C to +85°C

Description
This 8-bit bus transceiver with three-state outputs has sixteen
D-type flip-flops and multiplexers. The bus-oriented pinout of
the part is shown in the Pin Configuration. The internal gatei level hardware configurations for the 'ACT646/648 are given in
. the Logic Diagram. The basic repeated element, conSisting of an
!
edge-triggered flip-flop paralleled with a bypassing path, or
"feed-through", into a two-way multiplexer is sometimes called a
I "front-loading latch."
A pair of multiplexers are used to distribute two bytes of data
through the part. The data-routing combinations offered by the
i multiplexers provide flexibility in directing data to or from either
bus, and/or either register. Data is loaded into registers A orB
upon the riSing edge of the appropriate clock signals. CKA

.1

Pin Configuration

TEMP POLARITY OUTPUT TECH

CMOS

Invert

clocks register A, which receives data from the B bus directly at
its inputs. Similarly, CKB clocks register B, which has the A bus
available directly at its inputs. Control of the multiplexers is
provided by two select lines (one per register), SRA and SRB.
Command of the outputs is performed by enable line E, and
direction line DIR.
When E is High, data from the buses can be stored into register A
and B. When Eis Low and DIR is High, the direction of operation
is from A to B, when E and DIR are Low, the direction of
operation is from B to A.
SRA is used to select between register A and the B bus, and then
to route the data to a controlled buffer connected to the A bus.
Likewise, SRB selects between register B and the A bus, and
then routes the data to the B bus through a controlled buffer.

'ACT646/648
8-Bit Bus Front-Loading Latch Transceiver

SKINNYDIF'® is a registered trademark of Monolithic Memories.

TWX:. !J10-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

Monolithic l!T!ft
Memories Il1JlW
12·91

54/74ACT646 54/74ACT648

Logic Diagrams

'ACT646 (Non-Inverting)
CKA
OIR

23

3

SRB
CKB

P"

1 .J

21

SRA

...

1-=n-

22

.....

2

...~

1

.....
~

........
-

1 OF 8 CHANNELS
-I
r- ,-------- --- --- --------r--

I

I

AD

I

4

-~

.......

_

I
I

I
I

TVCC ........ ".,., ........ ,......,....................................................................... +20 rnA
, Output diode current, 10K:
",'I
VOVCC .... , .... ,',., ............ : ....... ',','
+20 rnA
•Storage temperature ••• , ... , •.. , ......••.••..•.•....•....•......•...•••..••.••...••.... , ••.... , .......•. -65 to +15O"C
' , 0 0 ' . , . : '. . . . . : , . . . . . . . . . ., . . . :

. . . . . . . . . . . 00 . . . . . . . . . . . . . . . .

Operating Conditions
MILITARY
MIN TVP MAX

COMMERCIAL
MIN TYP MAX

Supply voltage

4.5

5.5

4.5

TA

Operating free-air temperature

-55

125

-40

tw

Width of clock

, SYMBOL

PARAMETER

VCC

I
I

"

Set up time

tsti
0

'

t

'

20

Low

20

"'

20

5

" 5.5

V

85

·C

'"

ns
'

"

,,30t

':

",,}:'

,

"

Input ,~is,e time at VI; 4.5:Y

V

6
a

20",
'251

ns

or ,,'

at

HolCttime

',th'
tr

'

High

5

UNIT

,ns

500

0

500

ns

500

0

500

ns

tf "

Input fall time at VI ; 4.5

10H "

High-level output current'

-6

-6, ,mA

10L'

Low-leveFoutput current

12

12,

The arrOw indicates the L,9w:·tO.High transition of, the clock input used ;IS reference,

mA

54/74ACT648 54/7.4ACT648

Electrical Characteristics
SYMBOL·

PARAMETER

Over Operating Conditions
MILITARY
COMMERCIAL
25°C
UNIT
MIN TY; MAX MIN TYPMAX MIN TVP MAX

TEST CONDITIONS

VIL

Low-level input voltage

VIH

High-lEivel input voltage

liN

Input eu rrent

Vee = MAX

Low-level output voltage

10L = 20p.A
Vee = MIN
=
MAX
10L = 6mA
VIL
VIH = MIN
10L = 12mA

VOL

0.8
2
VI

= Vee
orGND

VOH

10Z

Off-state output current

lee

Quiescent supply current Vee = MAX VI
..

Ie.

Maximum quiescent
supply current

Vee = MAX

Vo= Vee
orGND
=Vee
orGND

± 1.0

0.1 .

0.1

V
V

2
±1.0

±1.0

Vee = MIN 10H = -20p.A 3.4
High-level output voltage VIL = MAX
VIH = MIN 10H = -6 rnA 2.4

. 0.8

0.7
2

p.A
..

0.1

0.32

0.4

0.37

.0.4

0.4

0.4

3.4

3.4

2.4

2.4

V

V

±30

p.A

40

lolA

±10

±50

10

80

1.5

2.0

1.9

25

35

33

I

Only one inVee = MAX put at 2.4 V

"

rnA

VI =2.4 V All inputs
or 0.5 V at 2.4 V

Switching Characteristics
SYMBOL
tpLH

PARAMETER

TEST CONDITIONS
(See Test
LoadIWavefomi)

Data to output delay

tpHL
tpLH

tpHL
tpLH
tpHL
tpZL

tpHZ

*

See Figure 4.

12-98

COMMERCIAL
UNIT
MIN
MAX

35

55

45

35

55

45
38

44

38.

Select to output delay*
(data input high)

28

40

35

28

40

35

Select to output delay*
(data input low)

28

40

35

28

40

35

40

50

45

40

50

45

eL = 50 pF

Output enable delay

Output disable delay
RL = 1KO
eL = 50pF
Direction enable delay

tpZH
tpLZ

MILITARY
MIN MAX

44

tpHZ
tpZL

MAX

30

tpZH
tpLZ

MIN

30

elock to output delay

tpHL
tpLH

COMIMIL
TA = 25°C

Direction disable delay

35

45

40

35

45

40

40

50

45

35

45

40

30

40

35

30

40

35

ns

ns

ns

ns

ns

ns

ns

ns

54/74ACT646 54/74ACT648

Test Waveforms
Setup Time/Hold Time

CK

Bus Data To Bus Output Delay

r----...,....-- 3V
____-------J+----___ OV

3v
BUS DATA
OV

BUS OUTPUT

DATA

VT = 1,3V

VT = 1.3V

Figu~1.

Figure 2,'
CK To Bus Output Propagation Delay Time

J-VT

.

r-~--------,---------3V

DATA

\'-_VT
______

OV

CK

OV

r--...,....-----__

-r~,-----VOH

VT = 1.3V

. Figure 3.

Select To Output Delay
3V
DATA
OF BUS

rD

OV
3V

DATA OF
REGISlER

OV
3V
SRAlSRB

OV
VOH
VOL

INPUT DATA HIGH

VT = 1.3V
NOTES! 1. When SRAlSRBisI6w. the input data wiirtrarisfer to output.bus.
2. WheM SRAlSRB is hiQh. 'th'. dllta of.ro,gister will transfer

ie' outPut bus:

3. For .~he in~rting devices, the timing i~.'$imilar. but the output is opposite .to that fodhe: "!lo~~inverting devie.as.

Figure 4.

12-99

54/74ACT646 54/74ACT648

Enable/Disable/Direction-Change Delay

3V

~k-VT

JF--VT

1\

DIR

---.J

OV
3V

~VT

\,-VT
OV

~tpZL~

WAVEFORM 1
(SEE NOTE 3)

I
_

_lpLZ--+
4.5V

~

l\VT
__

l
pZH

1.5V
0.5 V
VOL

!_t

PHZ _

(SEE NOTE 2)

VOH
WAVEFORM 2
(SEE NOTE 3)

0.5 V

..J,I'VT

1.5V

j

OV

Figure 5.

Test Load
Vcc
TEST POINT
RL

FROM OUTPUT
UNDER TEST
CL
(SEE NOTE 1)

r

Sl
(SEE NOTE 2)

1

Figure 6.

NOTES 1. CL includes probe and jig capacitance.

2. When measuring tpLZ and tpZL' 81 is tied to
S1 is tied to ground.

Vee. When measuring tpHZ and IpZH,

When measuring. propagation delay times of three-state outputs, 51 is open, i.e.,
not connected toVee 9r ground.
3. Waveform 1 is for an output with internal conditions such that the output is Low except when
disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is High except when
disabled by Ihe oulpul control.

4. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
5. All input pulses are supplied by generators having the following characteristics: PRR::;1 MHz, t r ::;6 ns,
If :56 ns, Zoul = 50 n.

12-100

MonollthlclFJlrMemorles

Die Configurations

54n4ACT646

54n4ACT648

Djltt~lze: 87x107 mU2

<'.,.:"

~'.. t01

8-Bit Bus Front-Loading Latch
Transceivers Advanced CMOS-TTL Compatible
54/74ACT651

54/74ACT652
Ordering Information

FeatureslBenefits
• Bidirectional bus transceiver and register
• Independent registers for A.and B.buses
• Real-time data transfer. or stored data transfer

PART
NUMBER
.
54ACT651

• Simultaneous outputs on both·buses

PKG

TEMP POLARITY OUTPUT TECH

JS,W,
L28

Mil

NS,JS

Com

Invert

• 24~pin SKINNYDIP® saves space

74ACT65'1

• Three-state outputs drive bus lines

54ACT652

JS,W,
L28

Mil

74ACT652

NS,JS

Com

"

• Low quiescent supply current of <10 /LA (typical)
• Active supply current at about 20% LS equivalent

3-state

CMOS

Non-invert

• Wide commercial operating supply and temperature
ranges 4.5 V to 5.5 V; -40°C to +85°C

Description
This 8-bit .bus transceiver with threEl-stateoutputs has sixteen
D-type flip~flops and multiplexers. The bus-oriElnted pinout of
the part is shown in the Pin Configuration. The inter~algate­
level hardware configurations for the 'ACT6511652 are given in
the Logic Diagrams. The basic repeated element, consisting of an
edge-triggered flip-flop paralleled with a bypassing path, or
"feed-through", into a two-way multiplexer is sometimes called a
'1ront-loading latCh."
A pair of multiplexers are used to distribute two bytes of data
through the part. The data-routing combinations offered by the
multiplexers provide flexibility in directing data to or from either
bus, and/or either register. Data is loaded into registers A or B
upon the riSing edge of the appropriate clock signals. CKA
clocks register A, which receives data from the B bus directly at

Pin Configuration

its inputs. Similarly, CKB clocks register B, which has the A bus
available directly at its inputs. Control of the multiplexers is
providedbylwo sEllect lines (one per register), SRA and SRB.
Command olthe outputs is performed by two enable lines, GAB
and GBA.
When GAB is low and GBA is high, data from the buses can be
loaded into registers A and B. When GBA is low, the A bus is
configured for output. When GAB is high, the B bus is configured
for output. The A and B buses can be enabled at the same time,
to operate as outputs simultaneously.
SRA is used to select between register Aand the B bus, and then
to route the data to a controlled buffer connected to the A bus.
Likewise, SRB selects between register B and the A bus, and
then routes the data to the B bus through a controlled buffer.

'ACT651/652
8-Bit Bus Front-Loading Latch Transceiver

SKINNYDIP@ is a registered trademark of'Monolithic Memories.

TWX: 910.-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

12-102

Monolith;" ~mn
MemorIes In.IlW

54/74ACT651 54/74ACT652
Logic Diagrams

'ACT651 (Inverting)
23
C~ -i~--~--------~-----------------------.
3

~-i>-----------~------------------------~
~~
~~O-~____~__~______~~~
2

CKI!

----- ....... :....-

.1 OF 8 CHANNELS

1
r

I

I

t·
I

4

I

AO-++-+-;

120

HH--j---BO
I
I
I

AEC>ISTERB

r

.....;;..-

-----.:.:-:--

I

J

TO 7 OTHER CHANNELS

'ACT652 (Non-Inverting)
C::~

GAil
SRA

SA8

GSA

23
3
.~'

2
21

CKB

1

1 OF 8 CHANNELS·

I

I

,,I
,,

+-+++'---!:;:'::""-SO
REGISTERS

--.

..

...... -------

.~----~--------~-----------TO 7 OTHER CHANNELS

12-103

.54/74ACT651

54/74ACT652

IEEE Symbols
'ACT652

'ACT651
GBA
GAB
CKA
SRA

21
3

23
22

CKB
SRB

EN1 [BAJ

GBA

EN2[ABJ

GAB

C4

CKA

G5

SRA

C6
G7

CKB
SREi

20

3
23
22
2

EN1 [BAJ
EN2[ABJ
C4
G6
C6

20

4

BO

AO

21

BO

AO

19
B1

A1
6

18

A2

B2

A2

B3

A3

17

7
A3
8

16

A4
9

B4

A4

B5

AS

15

AS
10

14

11

13

A6
A7

5

19

6

18

B1

A1

B6

A6

B7

A7

B2
7

17

8

16

9

15

10

14

11

13

B3
B4
B5
B6
B7

Block Diagrams
'ACT651 (Inverting)

'ACT652 (Non-inverting)
A BUS

A BUS

SRA

SRB

Uo-- on the B side.

CKAICKB:

Clock for register AlB.

X:

H orL state irrelevant ("Don't Care" condition).

T:

Positive edge ofCKcausescloeking, ifcl6ck enable
is asserted.

UC:

H or L or I case (nonclocked operation).

RGTR:

Register.

54/74ACT651
Bus Operation for' ACT651
CONTROL

OPERATION

BLOCK DIAGRAM
GAB GBA SRA SRB AO-A7

Storage

CLOCK
ENABLE

DATA 1/0

L

X

H

X

Input

BO-B7

Input

'ACT651

CKA CKB

.~

~

IfJ
r'

B

B

UC UC No operation
UC t Real time A bus data - RGTR B
t
UC Real time B bus data - RGTR A

BUS

eKB

CKA

t

t

Real time A bus data - RGTR B
Real time B bus data - RGTR A

UC UC Real time B bus data
A
BUS

A5:ij

Real time
B-to-A

L

L

L

X

Output

.~~

Input

UC
t

B
BUS

OperationeKB

eKA

t

t

time B bus data - A bus
UC Real
Real time B bus data - RGTR A
t

Real time B bus data - A bus
Real time B bus data - RGTR A
Real time B bus data - RGTR B

UC UC RGTR A data
A

I

Stored data
B-to-A

L

L

BUS

H

X

Output

Input

~

~ ~"
r

Operation

RGTR
B

eKB

l

B
BUS

UC
t

t

A bus

RGTR A data - A bus
RGTR A data - RGTR B

time B bus data - RGTR A
UC Real
RGTR A data - A bus

CKA

t

t

Real time B bus data - RGTR A
RGTR A data - A bus
RGTR A data - RGTR B

UC UC Real time A bus data
A
BUS

~6:]~.

Real time
A-to-B

H

H

X

L

Input

-~

Output

Operation

UC
t

t

t

eKA

B bus

Real time A bus data - B bus
Real time A bus data - RGTR B

time A bus data - B bus
UC Real
Real time A bus data - RGTR A

B
BUS

CKB

A bus

Real time B bus data - A bus
Real time B bus data - RGTR B

t

Real time A bus data - B bus
Real time A bus data - RGTR A
Real time A bus data - RGTR B

UC UC RGTR B data - B bus
A
BUS

Stored data
A-to-B

H

H

X

H

Input

Output

Operation

.
~~" ~~
JB~S
eKB

UC
t

t

RGTR B data - B bus
UC RGTR
§ data - RGTR A

eKA

1

Real time A bus data - RGTR B
RGTR § data - B bus

1

Real time A bus data - RGTR B
RGTR § data - B bus
RGTR § data - RGTR A

UC UC RGTR AlB data
A

BU~Jl
J,

Transfer
Stored
Data

uc

1

A

H

L

H

H

Outpu t Output

RGTRI
B

r

eKB

12·106

RGTR

AlB bus

RGTR AlB data - AlB bus
RGTR A data - RGTR B

Monolithio

...~

1

AlB data - AlB bus
UC RGTR
RGTR § data - RGTR A

B
BUS
eKA

W Memories

1

1

RGTR AlB data - AlB bus
RGTR A data - RGTR B
RGTR § data - RGTR A

54/74ACT652
Bus Operation for' ACT652
CONTROL

OPERATION

CLOCK
ENABLE

DATA I/O
BLOCK DIAGRAM

GAB GBAISRA SRB AO-A7

BO-B7

uc uc
uc t

~~

A
BUS

Storage

L

H

X

X

Input

Input

'ACT652

CKA CKB

t

No operation
Real time A bus data - RGTR B

UC Real time B bus data - RGTR A

BUS

CKB

t

CKA

UC

~

A
BUS

Real time
B-to-A

L

L

Operation

...

L

X

Output

.~

Input

A

Stored data
B-to-A

L

L

H

X

Output

Input

.~

t

Real time B bus data - A bus
Real time B bus data - RGTFl B
Realtime B bus data ~

Abus

UC Real time B bus data - RGTR A

B

t

CKA

t

Real time B bus data ~ A bus
Realtime B bus data - RGTR A
Real time B bus data - RGTR B

UC UC RGTR A data - A bus

ffiJ.
~' .
B

Operation

t

Real time A bus data ~ RGTR B
Real time B bus data - RGTR A

UC Real time B bus data - A bus

BUS

CKB

...

UC

I

uc
t

t

RGTR A data - A bus
RGTR A data - RGTR B
Real time B bus data - RGTR A

UC RGTR A data":" A bus

BUS

CKB

eKA

t

t

Real time Bbusdata ..c.. RGTR A
RGTR A data - A bus
RGTR A data - RGTR B

UC UC Real time A bus data - B bus
A
BUS

Real time
A-to-B

H

H

X

L

Input

Output

Operation

~

~

UC
I
B

I

UC

B~S

A-to-B

H

H

X

H

Input

Output

Operation

[6J

uc

~.I

B

cL

CKB

t

:

Real time A bus data - B bus
Real time Abus data - RGTR B

Real time A bus data - B bus
UC Real
time A bus data - RGTR A

BUS
CKA

.CKB

Stored data

t

t

Real time A bus data - B bus
Real time A bus data - RGTR A
Real time A bus data - RGTR B

UC RGTR B data - B bus
I

Real time A bus data - RGTR B
RGTR B data - B bus
RGTR B data - B bus

UC RGTR B data - RGTR A

BUS

I

t

Real time A bus data - RGTR B
RGTR B.data - B bus
RGTR B data - RGTR A

UC UC RGTR A/B data - AlB bus
A

~
RGTR

BUS

Transfer
Stored
Data

H

L

H

H

Output Output

~'
eKB

Monolithic

.

UC

lIIIemorles

t

RGTR AlB data - AlB bus
RGTR A data - RGTR B

RGTR AlB data - AlB bus
UC RGTR
Bdata - RGTR A

BUS

CKA

m

I

t

t

RGTR AlB data - AlB bus
RGTR A data - RGTR B
RGTR B data - RGTR A

12-107

54/74ACT65154/74ACT652
Absolute Maximum Ratings
Suppl{voltage, vee .................................................................................... -0.5 V to 7.0 V
DC input voltage, VI .................................................... , ................ , ......... -0.5 V to Vee +0.5 V
DC output voltage, Vo ..........•...............................................................•.. -0.5 V to Vee+0.5 V
DC output source/sink current per output pin, 10 ............................ : .................................... ±35 mA
DC Vee or ground current, ICC orlGND ....................................................................... ± 100 mA
Input diode current, 11K:
VI <0 ............•..................................................................... ;................ -20 mA
VI >Vee .........•.................................. , ........ , ......................................... +20 mA
Output diode current, 10K:
Vo <0 ..................................................•.......................................•...... -20mA
Vo>Vee ............ ; .................................................................................. +20mA
Storage temperature .................................................................................... -65 to +150o e

Operating Conditions
SYMBOL

PARAMETER

Vee

SlJpply voltage

TA

Operating freecair temperature

MILITARY
MIN TYP MAX

COMMERCIAL
MIN TYP MAX

4.5

5.5

4.5

125

-40

-55

I

5

High

20

20

Low

20

20

301

251

5

5.5

V

85

°e

tw

Width of clock

tsu

Set up time

th

Hold time

01

tr

Input rise time atVI

0

500

0

500

tf

= 4.5 V
input fall time at VI =4.5 V

0

500

0

10H

High-level output current

10L

Low-level output current

J

"

t The arrow indicates the Low-te-High transition of the clock input used as reference.

12 .. 108

Monolithicmi1] Memories

UNIT

ns
ns

01

ns
ns

500

ns

-6

-6

mA

12

12

mA

54/74ACT651
Electrical Characteristics
SYMBOL

PARAMETER

54/74ACT652

Over Operating Conditions

V,l

low-level input voltage

V,H

High-level input voltage

"N

Input Current

Vee = MAX

VOL

low-level output voltage

10l = 20 iJ.A
Vee = MIN
V,l = MAX 10l = 6mA
V,H = MIN
10l = 1.2 rnA

VOH

0.8
2
V,

= Vee
orGND

ICC

Quiescent supply current Vee = MAX V,

Maximum quiescent
supply current

± 1.0

± 1.0

0.1

0.1

Q.32

0.4

0.37

0.4

0.4

0.4

3.4

3.4

2.4

2.4

V
V

0.1

iJ. A

V

V

±10

±50

±30

iJ. A

10

80

40

iJ.A

1.5

2.0

1.9

25

35

33

= Vee
orGND

Only one inVee = MAX
put at 2.4 V
VI =2.4V
or 0.5 V

0.8
2

±1.0

Vee = MAX Vo = Vee
orGND

Off-state output current

0.7
2

Vee = MIN 10H = -20iJ.A 3.4
High-level output voltage Vil = MAX
V,H = MIN 10H = -6mA 2.4

'OZ

Ie

25°C
MILITARY
COMMERCIAL
UNIT
MIN TYP MAX ",IN TYP MAX MIN TYP MAX

TEST CONDITIONS

rnA

All inputs
at 2.4 V

Switching Characteristics
SYMBOL

PARAMETER

tplH

TEST CONDITIONS
(See Test
LoadlWaveform)

COM/MIL
TA = 25°C
MAX

MIN

Data to output delay

tpHl
tplH

Clock to output delay

tpHl
tplH
tpHl
tplH
tpHl
tpZl
tpZH
tplZ
tpHZ
tpZl
tpZH
tPlZ
tpHZ

*

el = 50 pF

MILITARY
MIN MAX

COMMERCIAL
UNIT
MIN
MAX

39

53

48

30

48

42

35

50

44

30

44

40

Select to output delay'
(data inputhigh)

32

44

40

32

44

40

Select to output delay'
(data input low)

35

50

44

30

40

36

25

35

32

25,

35

32

.

GBA to A bus
output enable delay
GBA to A bus
output disable delay
GAB to B bus
output enable delay

Rl = 1Kn
el = 50 pF

.'

25

35

32

35

40

38

30

35

33

25

35

32

35

32

40

38

25

GAB to B bus
output disable delay

35

See Figure 4.

Monolithic

m

Metnopies

...

ns

ns

ns

ns

ns

ns

ns

ns

54/74ACT651

54I74ACT652

Test Waveforms
Bus Qata To Bus Output Delay

Setup Time/Hold Time

r------3v

-l-VT

CK

r------~1r----------3V

BUS DATA

' -_ _ _ _ OV

-----------J-t------------OV

~~VT

DATA

BUS OUTPUT

'----

_ISU-!-Ih+

Figure 2
CK To Bus Output Propagation Delay Time
~--------~.----------------3V

DATA J V T

\ VT

OV

CK

r---------4-~.~-----VOH

VT = 1.3V

Figure 3

Select To Output Delay

(NON-INVERTING
DEVICES ONLY)

.......IpLH

IpLH
INPUT DATA LOW

INPUT DATA HIGH

NOTES: 1. When SRA/SRB is l.ow, the input data will transfer t.o output bus.
2. When SRA/SRB is high, the data 0.1 register will transfer to output bus.
3. For the inverting devices, the timing is similar, but the output is opposite to that for the non-inverting devices.

Figure 4

12·110

Monolithic

W Memories

5.4/74.ACT651

54/74ACT652

Enable/Disable/Direction-Change Delay

,----------- 3 V

~--------------J+-------------------OV
~--------------~·+_-------------------3V

GAB
~--~----~~-----OV

---'-~---,_I-'-- 4.5 V

WAVEFORM 1
(SEE NOTE 3)

+___~--.:~======1.5 V

\~V~T___

O~5 V
VOL

(SEE NOTE 2)

Figure 5

I

Test Load

Vee
TEHSPOINT
FROM OUTPUT .
UNDER TEST

(SEE

RL

S1·

1

(SEE NOTE 2)

NotEe~) I
-=

-=

Figure 6

NOTES 1. CL includes probe and jig capacitance.

2. When measuring tPl-Z and tpZL' S1' is tied to Vee- When measuring tpHZ and tpZH
81 is tied to ground.
When measuring propagation delay times of three-state outputs, 81 is open, i.e.,
not connected to Vee or ground.
3. Waveform 1 is for an output with internal c.onditions such that the output is low except when
disabled by the output control.
Waveform 2 is for an output with internal conditions such that the .output is High except when
disabled by the output control.

4. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
5. All input pulses are supplied by generators having the following characteristics: PRR::;:1 MHz, t r :56 ns,
tr:<:;6 ns, Zout :;: 50 !l.

MonolithicmMelfJories

12·111

54/74ACT651

54/74ACT652

Die Configurations

54/74ACT651

A6

A7

GND

54174ACT652

87

86

85

Die Size: 87x107 mil 2

12-112

l/IIonollthlc Wl/llemorles

I
I
I

.. .
' , ,.....

.
~

~

~

1

"

"

~

6
-

I$CL10KH

,to;"'

IS'

Table of Contents
ECL10KH
Contents for Section 13 ............................. 13-2
Selection Guide for ECl10KH ....................... 13-2
ECl10KH for High Performance System Design ....... 13-3
MC10H101 Quad ORINOR Gate ................... 13-4
MC10H103 Quad 2c lnput OR Gate .................. 13-6
MC10H102 Quad 2~lnput NOR Gate ................ 13-8
MC10H105 Triple 2-3-2 Input ORIN OR Gate ......... 13-8
. MC10H104 Quad 2-lnput and Gate ................ 13-10
MC10H107 Triple 2-lnput Exclusive ORIN OR Gate .. 13-10
MC10H109 Dual 4-5 Input ORINOR Gate ........... 13-10
MC10H130 Dual latch ........................... 13-12
MClOH131 Dual Master-Slave Type 0 Flip-Flop ..... 13-14
MC10H141 Four-Bit Universal Shift Register ........ 13-17
MC10H158 Quad 2-lnput Multiplexer .............. 13-19
MC10H159 Quad 2-lnput Inverting Multiplexer
with Enable ......................... 13-21
MC10H173 Quad 2-lnput Multiplexer with latch ..... 13-23
MC10H210 3-lnput ORINOR Gate ................. 13-25
MC10H211 3-0utput ORINOR Gate ............... 13-25

ECL 10KH Selection Guide
FUNCTION

DEVICE

PACKAGE

PINS

J, N

16

NOR Gate
MC10H102

Quad 2-lnput

MC10H211

Dual 3-lnput, 3-0utput
OR Gate
2~lnput

MC10H103

Quad

MC10H210

Dual 3-lnput, 3-0utput
AND Gates

MC10H104

Quad AND
Complex Gates

MC10H101

Quad OR/NOR

MC10H105

Triple 2-3-2InputOR/NOR

MClOH107

Triple Exclusive OR/NOR
Flip-Flop Latches

'.

MC10H130

Dual Latch

MC10H131

Dual 0 Master Slave Flip-Flop
Data Selector Multiplexer

MC10H158
MC10H159
MC10H173

Quad 2c lnput Multiplexers (Non-inverting)
•.. . Qvad2-lnput Multiplexers (Inverting)
QVad2-lnput Multiplexer latch
Special. Function

MC10H141

13-2

Universal Shift Register

MonolithIc

miD MemorIes

ECL10KH
for High Performance System Design.,

The designerof high-performalJqe digital s~tems nowhas nf:!W '
alternatives with the introduction of Monolithic Memories' ECl
10KH family of logic. Monolithic Memories' ECl 10KH deviceS '
are completely equivalent .to Motorola's MECl10KH. This
means thalthe s~tem designer can take advantage of the high
performance of ECl 10KH logic, and eliminate the woe{)f having
a sele-sourced logic family;
ECl logic is used in a broad range of applications that demand
high speed and a stable system environment. ECl 10KH represents a particular optimization of semiconductor technology
towards ease of use in ~tems. A summary of the advantages of
ECl 10KH may be of use to the system designer.
ECl1 OKH, in general,is compatible with 10K EC,llogic, biJl it is :
faster, offers better noise margin, and operates at equal powe~ as,
compared to MECl 10K logic. Propagation dela~, and clock

speeds are 100% better, and noise immunity is improved,75%
over the MECl 10K series. The basic power dissipation of 25
mW/Gate is comparable to MECl 10K.
To obtain better circuit speeds, new ~m[e6ndiJctor processing
is used with ECl 10KH. Smaller transistors resiJlt from this
processing, allowing greater speed. Other'llesign,chalJgesare,
employed in ECl 10KH, over the basic MECl 10Kgat~'structure,
which yield better DC performance as well. ECl 10KH is a "01tagErCompensated logic family, allowing guaranteed DC and AC
parameters over a ±5% power supply range. VoltagErCompensation allows for smaller semiconductor die sizes fOr a given
function as comparedwilh ECl devices employing bolhvoltage
compensation and te(Tlperature compensation. Smaller die sizes
translate into a lower production
which in tum mear1!i a
tower cost to the end user.
'

" , ; .' ,
, '.
, . .:. ." , ' " ' , ' , '
TWX: 910-338-2376
~17,!ii"I~lon C~II~~8ivd. Silnta Ctaf/i,C,A 95lJS4~~.~92 'Tel: (40.) 970-9700 rwX: 910-338-2374

cast,

ECL 1 OKH High·Speed
Emitter·CoupledLogic. F,amUy,
MC10H101··
...'.

pFi~LI·P.UNAAY .'...

.

I ItjlFORMATION

. . . ·Th

I

Quad OR/NOR Gate

;s'~o~~~~~t cJnta\ns spe-

cifications and information
which are subject to change.

Ordering Information

Features/Benefits
• Propagation delaY. 1 nl, typical

PART NUMBER

• Powerdl.-lpatlon25inW/gate.

PACKAGE

.'

J,N

MC.1Q1-!101

• Nol.. margin 150 mV

TEMPERATURE
COM

• Voltage qc)/II~,

•

ECL1OK~mpaUbie.

Description
The MC10H191 is a membero.f Mo~0Iithi(;Mem6ries' ECL family.
This ECL 10KH part is a funCtional/pinout duplication oj the

standard ECL 10K family part, with 100% improvement in propagatiOl'ldelay, and no'increase in power-supply current

Pin Configuration
MC10H101
Quad OR/NOR Gate

MC1OH101

. , Portions "I this Da.ta Sh'!81 r~produced with the courtesy 01 Motorola, Inc.
i,

'" ,

. ~ .'

"

."" "

. ''''''''

e

'

••

,

• y

,~"

MC10H101
I
. I
i
I

Absolute Maximum Ratings
Supply yoltage vEE (VCC = 0) ..........•................................ " ..... , ....................... ; ... -8.0 to 0 Vdc
Input Yoltage VI (VCC = 0) .......•.............................•................. ; .•..•. ; .. :.. , ...•........•. 0 Vdc to VEE
Output Current:
COntinuous .•.•....•....•........•.•..........•.............................................................. 50 mA
Surge .............•.............•........•.......................................•.......................... 100 mA

Operating Conditions
SYMBOL

PARAMETER

VEE

Supply Yoltage

TA

Operating temperature range

TSTG

Storage temperature range

COMMERCIAL
MIN TYP.MAX

UNIT

-5.46 -5.2 -4.94

V

0

75

Plastic

-55

150

Ceramic

-55

165

°c
°c

Electrical Characteristics VEE = -5.2 V ± 5% (See note)
DO
SYMBOL

25°

PARAMETER
MIN

MAX

75°

MIN

UNIT

MAX

MIN

MAX

IE

Power supply current

-

29

-

26

MC10H101

-

425

-

265

-

265

linH

.1
Input current high
'1

MC10H101 (Pin 12 only)

-

850

-

535

-

535

linL

Input current LOW

0.5

-

0.3

-

!J.A

VOH

HIGH output yoltage

-1.02

-0.98

-0.81

-0.92

-0.735

Vdc

-

0.5

-0.84

29

mA
!J.A

VOL

LOW output Yoltage

-1.95

-1.63

-1.95

-1.63

-1.95

-1.60

Vdc

VIH

HIGH input Yoltage

-1.17

-0.84

-1.13

-0.81

-1.07

-0.735

Vdc

VIL

LOW input Yoltage

-1.95

-1.48

-1.95

-1.48

-1.95

-1.45

Vdc

MIN

MAX

MIN

MAX

MIN

MAX

Propagation delay

0.7

1.6

0.7

1.5

0.7

1.7

tr

Rise time (20%-80%)

0.7

2.2

0.7

2.0

0.7

2.2

ns

tf

Fall time (80%-20%)

0.7

2.2

0.7

2.0

0.7

2.2

ns

Switching Characteristics

VEE = ·5.2 V ± SO/o (See note)
DOC

SYMBOL
tpd

25°C

75°C
UNIT

PARAMETER

ns

NOTE: Each Eel 10KH series circuit has been designed t.o meet the dc specifications shown in the test table, after thermal equilibrium has been established.
ThE!'circuit is in a test'socket or mounted on a printed circuit-board and transverse airflow greater than 500 linearfpm is maintained. Outputs are terminated
through a 50-ohm resistor to -2,.0 V;

Monolithic

m

Memories

ECL ~OKHlUgh-Speed
Emitter-Coupled Logic Family
MC10H103
Quad 2-lnput OR Gate

PRELIMINARY
INFORMATION
This document contains spec
cifications and information
which are subjectto change.

Ordering Information

Features/Benefits
• Propagation delay, 1.0 ns typical

PART NUMBER

• Power dissipation 25 mW/gate

PACKAGE

TEMPERATURE

J,N

Com

MC10H103

• Noise margin 150 mV
• Voltage compensated
• ECl 10K compatible

Logic Diagram
Description

MC10H103

The MC10H103 is a member of Monolithic Memories' ECl
family. This ECl 10KH part is a functional/pinout duplication of
the standard ECl 10K family part with 100% improvemen!in
propagation delay, and no increase in power-supply current

Atn1 4 _ _----,~I'~~ 2 AoUI
Ain2 5
'-

Bin16~3B

Bln2 7~ -- - -

12

Cinl
C in2 13

oul

:C~.15 Coul

Ai--- 9 c.;;;i

Dln110~14Dout

Dln211~

Pin Configuration.
MC10H103
Quad 2-lnput OR Gate

Portions' of this Data Sheet reproduced with the courtesy of Motorola, Inc.

TWX: 910-338-2376
2175".ission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

13-6

Monolithic. 1!.1!ft
Memories Il1JlW

MC10H103
Absolute Maximum Ratings

vee

Supply. voltage
(Vee = 0) ....................,' ................. ; ............ :..•.•• ~ •... '.',' .; •...•..... -8.0Vto 0 Vdc
.Input voltage VI (Vee = 0) •.. ,' ....... ,' .., ......... ,.:., ..•.• ,' ........................... : .................. .', ..... 0 Vdc to Vee
Output Current:
.. . . ,
, .
.Continuous ....... ;.••.. , .........................................'. ; .•.•.•.•.• ~ ............... '. ; ................... 50 rnA
Surge ....................................................................................................... 100mA

Operating Conditions

.'

SYMBOL

COMMERCIAL
MIN TYP MA~

PARAMETER

Vee

Supply voltage

.-5.46 -5.2 -4.94

TA

Operating temperature range

0

TSTG

Storage temperature range

Plastic

,

Ceramic

Electrical CharacterJstics
.' .

"

UNIT
V
Qe·':

75

:-55

150

-55

165

°C

=-5.2 V ±5% (See Note)

VEE

/

SYMBOL

o·

PARAMETER
'

Ie

Powefsupply current

. . ',

25°

75°
UNIT

MIN

MAX

MIN

M~X

MIN

MAX

-

29

-

26

29

rnA

425

-

265

-

265

pA

0.5

-

0.5.';

-

0.3

-

pA
Vdc

linH

Inpufliurrent HIGH

linL

Input «;:urrent LOW

VaH

HIGH output voltage

-1.02

-0.84

-0.91!~

-0.81

-0.92

-0.735

VOL

LOW ()tJtput voltage

-1.95

-1.63

,..1.9~

-1.63

-1.95

-1.60

Vdc

VIH

HIGHinput voltage

-1.17

-0.84

-1.13.

-0.81

-1.07 : -0.735

Wc

VIL

LOWinj:>ut voltage .. ;

-1.95

-1.48

-1.95

..,1.48

,,1.,95'

Vdc

.'

."

,

Switching CharaCt8l'''tl.

'P~RAME1"ER
. ::

SYMBOL

Prppegatlon delay

.'.

FalitilTle{8~26%)
.

,

'.

....

VEE = -5.2V ± 5% ($eeNote)·
"

:

,.0.7

".

.....

0.7
.

:.

15° .'

25°
MIN

.

-1.45

MAX

MlN.

MAX

>

MiN

UNIT
MAX

I

1.6

'0)

1:5

0.7 '", 1.7

ns

2~2

0.7

g·9

0.7

2.2

ns

2.2

0.7

2.0

0.7

2.2

ns

.

fliOTE: Each EeL .10KH series. circuit hes been designed to meet the dc specifications shown in the lest table. after thermal equilibrJum has' been established:,
, The,cifcui.t iSin.a:!.e~~~~c~etor rt)",\/nted 9,n a,pr!nt~d pircuit b!",r!! ~~ct tra~~vers.. airf!OIN ~r!'8t~r!"'~n,QllO.linear jpm is ,maiolail'ed. QUtputs ate Wmi(lated.,
,
through a ,50-p.hm,reillsJor to' ~2,O.y.;~'
~:

.i

,.~\c({;.~: ,

•

{"",~,

-=:CL1 OKH

PRELIMINARY
" INFORMATION

"igh~$,,"d

This document contains speEmiHer-Coupled Logic Family
. Cllicationsaild information .
.,.,hichare s\Jl>ject to change.
MC10H102/Quad 2-lnput NOR Gate
MC10H105/Tripie 2-3-2 Input ORINOR Gate

Ordering Information

Features/Benefits
• Propagation delay, 1 ne typical

PART NUMBER

• Power dissipation 25 mW/gate

MC10H102

• Noise margin 150 mY.

~,III

MC10Hf05

• Voltage compensated

PAC~GE

".

TEMPERATURE
..~

~ ,

COf)tl

• ECL 10Kcomp&tlble,

Description
. The MC1OH102 and MC10H105 are members of Monolithic
Memories new i:CLfamily.These ECl 10KH parts
functionall
pinout duplications of the standard EGl ·10K family parts, with .
100% improvement in propagation delay, and no increase in
power-supply current.

are

Pin Configurations
MC10H102
Quad 2~'nput NO.R .Gate.

M.C10H10S·
Tripi. 2~3-~Jnput O~NO~ Ga~

Logic' Diagrams.
MC10H10S

MC10H102

-Quad 2-lnput NOR Gate
Portions of this Data Sheet reproduced with the courtesy of Motorola Inc.
e"'''''

TWX: 910-338-2376
2.175 Misslo!' College81vd.,Sanla CIara.CA 95054.1592 T.eI:,(406) 970-97.00 .T\'I(X: '910.33114:374

13..,

"""'lthlc limn

. . . .orl.....mm.u

MC1 OH1 021'MC10H105
Absolute Maximum Ratings
Supply voltage VEE (VCC =0) ......... : .... ,. ~ ................ 'c' " : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8.0 V to 0 Vdc
Input voltage VI (VCC= 0) ............... ;;; ....' .................................. ; ......................... 0 Vdc to VEE
Output Current:
Continuous " ................. ; ............................................. ; ........................ , ....... 50 mA
Surge ................................................................. , ..................................... 100 rnA

Operating Conditions
SYMBOL

COMMERCIAL
MIN TYP MAX

PARAMETER

VEE

Supply voltage

-5.46 -5.2 -4.94

TA

Operating temperature range

0

TSTG

Storage temperature range

Electrical Characteristics
SYMBOL

75

Plastic

-55

150

Ceramic

-55

165

VEE = -5.2V

V
°c
°c

± 5% (See Note)
0°

PARAMETER
MIN

1MC10H102
I MC10H105

UNIT

25°
MAX

MIN

75°
MAX

MIN

UNIT
MAX

-

29

-

26

-,

29

-

23

-

21

-

23

Input current HIGH

-

425

-

265

-

265

linL

Input current LOW

0.5

-

VOH

HIGH output voltage,

-1.02

VOL

LOW output voltage

-1.95

-1.63

-1.95

-1.63

-1.95

-1.60

Vdc

VIH

HIGH input voltage

-1.17

-0.84

-1.13

-0.81

-1.07

-0,735

Vdc

VIL

LOW input voltage

-1.95

-1.48

-1.95

-1.48

-1.95

-lA5

Vdc

MAX

MIN

MAX

MIN

IE

Power supply current

linH .

Switching Characteristics
SYMBOL

-0.84

0.5

-

0.3

-0.98

-0.81

-0.92

-0.735

mA
I'A
p.A
Vdc

VEE = -5.2V ± 5% (See Note)
0°

PARAMETER
MIN

75°

25°

UNIT
MAX

tpd

Propagation delay

0.7

1.6

0.7

1.5

0.7 "

1.7

ns

tr

Rise time (20%-80%)

0.7

2.2

0.7

2.0

0.7

2.2

ns

tf

Fall time (.80%-20%)

0.7

2,2

0.7

2.0

0.7

2.2

ns

.

NOTE; Each ,Eel 10 ,KH series circuit has been designed to meet the:dc specifications shown in the test table, after thermal equilibrium has been established.
The circuit is in a testsocket.or m91,mted,on a printed, circuit board and transverse air.ftowgreaterthan 500Jinear fpm is maintained. Outputs are ter.minated
through a !;O-ohm resistor to.-2.0 V,

1.3 .. 9

ECL 10KH High-Speed
EmiHer-Coupled'LogicFamily
MC10H104/MC10H107

PRELIMINARY
INFORMATION
"

,

This docurneni containS'Specifications . and information
which are subject to change.

Quad 2-lnput AND Gate/Triple 2-lnput
Exclusive OR/NOR Gate

Ordering Information

Features' Benefits
• Propagation delay, 1 na typical

PART NUMBER

PACKAGE

MC10H104
MC10H107

J,N

TEMPERATURE

• Power dllllpaUon 35 mW/gate typical
• Noise margin 150 mY

'

'

..

Com

• Voltege compenseted
• ECL 10K-compatlble

Delcrlptlon
The MC10H104 and MC10H107 are members of Monolithic
Memories' new ECl family. These ECl 10KH parts are funclional/pinoutduplications of the standard ECl 10K family parts
with 100% improvement in propagation delay, and no increase in
power-supply current.

Pin Configurations

Logic Diagrams
MC1OH104

MC10H104

A1,4~

/t(J,"5'~ 2AOUT

il1 II ~- 3BOUT
B27~

VCC1 = PIN 1
VCC2= PIN 16
VEE = PIN a

C110~ "14.COUT
C211~

~ 15. DOUT .
9DOUT

D112
0213

Quad 2-lnput AND Gate .

MC10H107

MC10H107

A1' 4 ~2 .,iOiif..'
A2 5......,~3 AOUT
B1 9 ~~ 11 BOUT
B2 7......,~ 10 BOUT

\

VCCf=PIN1
VCC2= PIN 16
VEE = PINa
PIN6=NC

C11.4 ~ .12
UT
C215 ->eJ~ 13 COUT,
aro'f.

TrIple 2-lnput ,
ExclU81'" OR1NORG8te"
Portions of this Data SHeet reproduce,fwith the courtesy of Motorola'lnc,

2175 Minion College BlVd. Santa Clara, CA 95054-1592 Tel: (408)

1~O

.

!'!J.DI!IIII
utlnJJ

910-338-2376", .1iIotJoj
•.m.····..., .
970~9700 ,TWX:
TWX: 910-338-2374

....

MC10H104 MC10H107
Absolute Maximum Ratings
Power supply VEE (VCC =' 0) ...........................................•......••...•...............•. .' ••• -a.0 V to 0 Vde
Input voltage VI (VCC = 0) ........... , .........................•...............'•..•••............ ~ •...•...•.• 0 Vdc to VEE
Output current:
,
'
Continuous ........•......................................................................• : •....•...•....... 50'mA
"Surge ..• ;": i ...... . '; .• '.......•.... : ............................................. :' .......•..... :'..•....•........ 100 rnA

O.perating Conditions
"

SYMBOL-

'. COMMERCI~~
MIN
TYP
MAX

,PARAMETER

, -4.94

V

+75

' ·C

-55

, ,,+1,50

,·C

-55

+165

VEE

Supply Voltage

~5.46

TA

Operating temperature range

0

T stg

I

Storage temperature range

Plastic

'" 'Ceramic

,

-5,2

UNIT

,

,

Electrical Characteristics VEE = -5.~ V ± 5% (See Note)
MIN,

' MC10Hl04
MC10Hl07

1,-

75·

~5·

' Q?

PARAMETER

SYMBOL

MAX

;39
31

MIN~"

MAx

rnA

265

p.A

-0.92

0.735

Vdc

'-1.63

,.1.95

-1.60

Vdc

-1.13

-0.81

";1.07

..,0.735

Vec

;,lJa5

::1;48

'-1.95'

-:-1.4.9

vdc

Power ~tJPply current

linH

Inputcllrrent HIGH

linL

Input cllrren! LOW

VOH

HIGH,oullM VOltage

-1.02

'::'0.84'

-0.98

.::.O:al

VOL

LOW OlltPllt voltage

-1.95

-1.63

-1.95

VI/.j

HIGH inp!Jt voltage
LOW input voltage

-1,t7
-1:95

-0.84,

VIL

-1 AI:!

- ','

,

,"

425

;,"

,

-,

265

'O.!;i

0.5

UNIT

MAX,"
39
31

35
28

IE

I

MIN

p.A

0.3

I:

',.

Switching Characteristics VEE = -5.2 V -+ 5% (See Note)
<"

;

SYMBOL

PARAMETER
'.'

tpd

O·

:·,i

PrOQaglilion delay

tr

Riseti'me

tf

Falltfme

I
,'.'

'.,"

MC10Hl04
MC10Hl07

75·

25°,

UNIT

MIN

MAX

MIN

. MAX

MIN

MAX

0.7
.0.7

2.2
2.0

0.7
0.7

2.0
1.9

0]
0.7

2.2
2.0

ns

I"

I

0.7

2.2

0.7

2.0

0.7

,2.2

ns

0.7

2.• 2

0],

2.0

0.7

2.2

ns

13,-11

-;"

..

~'

ECL 10KH High-Speed
Emilter-Couple,d Logic Family
Dual Latch
MC10H130

",PRELIMINARY
INFORMATION
This document eo~tains speCifications and, information
wh'ich are subject to change.
"

Ordering Information

Features/Benefits
• Propagation dela)!. ,1 ns typical
• Power dissipation; 155 mW typical
,. NQlse margin 150 mV

PART NUMBER

PACKAGE

TEMPERATURE

MC10H130

J,N

Com.

• VoI'-gecompenaa'-d

• EeL 10K-compatlble

Description

Logic Diagram

The MC10H130 is a dual latch which has two different mechanisms to retain data through latch control sigrials. Each latchean
be operated separately by holdirig the common latch control
signal (C) LOW, then switching an individual latch control signal
(CE1/CE2"j from LOW to HIGH to cause retention of data in the
relevant latch. If simultaneous operation of both latches is
required, CE1 and CE2 are held LOW and the common latch
control C is switched from LOW to HIGH.
For either latch, data present atthe inputs (01102) will be seen at
the outputs (01/01 and 02/02) lII'hen both latch control signals
are LOW. This condition allows data to be setup within the latch,
after which time causing a positive transition to the HIGH state'
on either or both latch control signals causes data retention.
After either or both of these signals are HIGH, subsequent
changes in data at an input are ignored by the latch, provided the
hold time requirement is met. ,
An alternative means to load 'data iil the latches is to use the
direct set and reset (S1/S2 arid R1IR2,respectively) lines. These
inputs do not override the ,latch controls, or .!!!eEJ!le!!!! Instead,
set or reset are only effective when either C, CElICE2 or both,
are HIGH. Note thatthis relationship is differentthan the case for
a similar part, the MC10H131, which is a Dual Master-Slave
D-type Flip-Flop.

S1
D1

eli
H1
~'

R2

CE2
D2
S2

5

8

4
9
13

11

10

12

Pin Configuration

Function Table

,"

D

C

CE1/CE2

R

S

°n=l

L

L

L

X

X

L

H

L

L

X

X

H

X

H

X

L

L

on
H

L

H

H

L

L

X

H

H

N.D.

X

H

L

L

On

X

H

L

H

H

X

X

H

H

L

L

X

X

H

H

H

N.D.

X

H

X

X'

H

X'

X

H

X
X

"

MC10Hl30
Dual Latch

x - Dont Care
N.D. = Not Defined

, '
'
.
"
2175 Mission Coilege Blvd. santa Clara,CA 95054-1592

\ 13-12

2

7

Portions of this data sheet reproduced with the courtesy of Motorola Inc.

Tel:(~08) 970"9700. ,.'[WX:910-338.2376
TWX: 910-338~2374
'

'.~m"a'!.-'1
!p.Ij.r1 I1I111
In.UW
Vi

.1

MC10H130

Absolute Maximum Ratings
Supply voltage VEE (VCC = 0) ...................................................................... , ...... -M V toOVdC
Input voltag.e VI (VCC = 0) .................................. ; ............................................... OVdc to VEE
Output Current:
Continuous .................................................................................................... 50 mA
Surge .... ' ............•.................•................................................................... 100 mA

Operating Conditions
SYMBOL

VEE

PARAMETER

Supply voltage

I
I

Tstg

Storage temperature

TA

Operating temperature range

Electrical Characteristics

linH

-5.46 -5.2 -4.94

V

-55

+150

Ceramic

-55

+165

0

+75

7So

2So

UNIT
MAX

MIN

MAX

MAX

MIN

-

38

-

35

-

38

Pins 6,11

-

468

-

275

-

275

Pins 7, 9,10

-

545

-

320

-

Pins 4,5,12,13

-

,. 4.34

-

255

-

Power supply current

.

0.G

..

PARAMETER

Input current HIGH

°c

VEE = -S.2 V ±S% (See note)

MIN

IE

UNIT

Plastic

0°
SYMBOL

COMMERCIAL
MIN TYP MAX

320

Input current LOW

0.5

-

0.5

-

0.3

VO H

HIGH output voltage

-1.02

-0.84

-0.98

-0.81

-0.92

VOL

LOW output voltage

-1.95

-1.63

-1.95

"1.63

VIH

HIGH input voltage

-1.17

-0.84

-1.13

-0.81

VIL

LOW input voltage

~1.95

-1.48

-1.95

-1.48

c

JlA

255

.'

linL

mA

-

JlA

-0.735

Vdc.

-1.95

-1.60

Vdc

-1.07

-0.735

Vdc

-1.95

-1.45

Vdc

Switching Characteristics . VEE = -S.2V, ±S% (See note)
2So

0°
SYMBOL

MIN

tpd
tr

75°

PARAMETER

Propagation delay

MAX

MIN

... MAX

MIN

UNIT
MAX

Clock

0.7

2.2

0.7

2.1

0.7

2.2

Data, Set, Reset

0.7

2.0

0.7

1.8

0.7

2.0

0.7

2.2

0.7

2.0

0.7

2.2

ns

Rise time (20%-80%)

ns

tf

Fan time (80%-20%)

0.7

2.2

0.7

2.0

0;7-

2.2

ns

tset

Setup time

2.2

-

2.2

-

2.2

-

ns

thold

Hold time

0.7

-

0.7

-

0.7

-

ns

,

'.

NOTE: 5Each,ECL 10KH senes clrcUli"'has-been deSigned to meet the de speCifications_shown 'In the test table. after thermal eqUilibrium-has been. established .
. 'The,cirpuit if? In atest s~ck_et-o~ mounted on a printed circuit board and transverse airflow 9 reater than 500 linear fpm is maintained. Outpyts are terminated
through-. 50n:resistor'to -2.0V.

Monolithic

m

Memories

13·13

ECL 10KHHigh-Spef!d
Emitter-Coupled Logic Family
MC10H131
Dual Master-Slave Type D Flip-Flop
Features/Benefits

PRELIMINARY
INFORMATION
This document contains speCifications and information
which are subject to change.

Ordering Information

• Propagation delay, 1 ns typical

PART NUMBER

PACKAGE

TEMPERATURE

MC10H131

J,N

Com.

• Power dissipation, 235 mW typical
• Noise margin of 150 mV
• Voltage compensated
• ECL 10K-compatible

Description

Logic Diagram

The MC10H131 is a member of Monolithic Memories' ECL
family. The MC10H131 is a dual master-slave D-type flip-flop.
Asynchronous Set (S) and Reset (R) override Clock (Cel and
Clock Enable (CE) inputs. Each flip-flop may be clocked
separately by holding the common clock in the low state and
using the enable inputs for the clocking fuction. If the common
clock is to be used to clock the flip-flop, the Clock Enable inputs
must be in the low state. In this case, the enable inputs perform
the ·function of controlling the common clock.
The output states of the flip-flop change on the positive transition
of the controlling input(s). A change in the information present
at the data (D) input will not affect the data output at any other
time due to master slave construction.
This ECL 10KH part is a functional/pinout duplication of the
standard ECL 10K family part, with 100% improvement in clock
speed and propagation delay and no increase in power supply
current.

MC10H131
Sl
Dl

CEl

Rl
Cc
R2

CE2

D2
52

Function Tables

5
7

01

6

Ci1
4
9
13

02

11

10
12

> : denotes edge triggered clock

R-S TRUTH TABLE
R

Pin Configuration

S

an + 1

L

L

an

MC10H131

L

H

H

Dual Master-Slave Type D Flip-Flop

H

L

L

H

H

N.D.

VCC2

02

N.D. = NOIDefined.

02

CLOCKED TRUTH TABLE

R2

C

D

an +

L

X

an

HI

L

L

HI

H

H

x =Don't Care,
e =eE+ ee.

1

S2

Portions of this Data Sheet reprodu~ed with the courtesy of Motorola Inc.

TWX: 910-338-2376
2175 Mission College Blvd. Sanla Clara, CA 95054-1592. Tel: (408) 970~9700 TWX:.91.0-338-2374

13-14

Monolithic~!!"

Memories LnJrW

MC10H131
i

Absolute Maximum Ratings
Supply voltage VEE (VCC = 0) .............................................................................. -8.0 to 0 Vdc
Input voltage VI (VCC =0) .................................................................................. 0 Vdc to VEE
Output Current:
Continuous .................................................................................................. 50 mA
Surge ....................................................................................................... 100 mA

Operating Conditions
SYMBOL

PARAMETER

VEE

Supply voltage

TA

Operating temperature range

TSTG

Storage temperature range

Electrical Characteristics
SYMBOL

linL

Input current LOW

V

0

I
I

75
150

Ceramic

-55

165

°c
°c

VEE = -S.2 V ±S% (See note)
7So

2So

0°

UNIT

Power supply current

Input current HIGH

-5.46 -5.2 -4.94

-55

PARAMETER

linH

UNIT

Plastic

MIN
IE

COMMERCIAL
MIN TYP MAX

Pins 6, 11
Pin 9
Pins 7, 10
Pins 4, 5, 12, 13

MAX

MIN

-

62

-

-

530
660
485
790

-

0.5

-

-

MAX

MIN

MAX

56

-

62

mA

-

-

310
390
285
465

-

310
390
285
465

p.A

0.5

-

0.3

-

p.A

-

VOH

HIGH output voltage

-1.02

-0.84

-0.98

-0.81

-0.92

~0.735

Vdc

VOL

LOW output voltage

-1.95

-1.63

-1.95

-1.63

-1.95

-1.60

Vdc

VIH

HIGH input voltage

-1.17

-0.84

-1.13

-0.81

-1.07

-0.735

Vdc

VIL

LOW input voltage

-1.95

-1.48

-1.95

-1.48

-1.95

-1.45

Vdc

Switching Characteristics

vEE = -S.2 V ±S% (See note)
7So

2So

0°
SYMBOL

UNIT

PARAMETER

I

Clock to Q
Set, Reset to Q

MIN

MAX

MIN

MAX

MIN

MAX

0.7
0.7

2.0
2.0

0.7
0.7

2.0
2.0

0.7
0.7

2.1
2.1

ns

tpd

Propagation delay

tr

Rise time (20%-80%)

0.7

2.3

0.7

2.3

0.7

2.5

ns

tf

Fall time (80%-20%)

0.7

2.3

0.7

2.3

0.7

2.5

ns

I

tset

Setup time

0.7

-

0.7

-

0.7

-

ns

thold

Hold time

0.7

-

0.7

-

0.7

-

ns

ftog

Toggle frequency

250

-

250

-

250

-

MHz

NOTE: Each Eel 10KH series circuit has been designed to meet the de specifications shown in the test table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500linearfpm is maintained. Outputs are terminated
through a 50n resistor to -2.0 V.

MonoIIthlo

W Memories

13·15

MC10H131
Switching Time Comparison
ECL 10KH versus ECL 10K
CLOCKTOQ

CLOCKTOQ

CLOCK

MC1J131_

Ipd + +
1.508

rf]Vl V

CLOCK __

MC10131

v

1J

~/-

'rl008++

r

iJ',\ \~

v

) )J.

)

.\

1

1

MC10131

Irr8~

~

MC1OH131/
Ipd +-

l'T

I, FOR MC10H131: 1.4 08
I, FOR MC10131: 2.0 ns

"I, FOR MC10H131: 1.2 ns
I, FOR MC10131: 1.4 n.

SETIRESET TO Q

SETIRESET TO Q

MC1OH131 __

Ipd ++
1.4n.

v
SE'rIRESET

r~
j

lC V V
1/

I .I

r--J 'I V-

.--;-MC10131

1'1++

SETIRESET

v

1/,\
~

108

J

) tJ.J

)

\

~

r--MC10131

~\

MC1OH131/

11f.l~-1

I,

I, FOR MC10H131: 1.5 ns
I, FOR MC10131: 2.1 ns

NOTE:

t, and t f rneasu,ed f,orn the 20% to the 80% level 0' the output signal swing.

tpd is measured from the 50% level of the input to the 50% level of the output.

13·16

I

FOR MC10H131: 1.2 ns
" FOR MC10131: 1.5 ns

IIonoIIthIo

m.emorles

tr:.~;

ECL 10KH High.Speed
Emitter·Coupled Logic Family

PRELIMINARY
INFORMATION
This document contains specifications and information
which are subject to change.

MC10H141
Four-Bit Universal Shift Register
Features/Benefits

Ordering Information

• Shift frequency, 250.·MHz min
• Power dissipation, 425 mW typical
• Noise margin 150 mV

PART NUMBER

PACKAGE

TEMPERATURE

MC10H141

J, N

Com

• Voltage compensated
• ECl 10K-compatible

Description

Pin Configuration

The MC10H141 is a four-bit universal shift register which performs shift-Ieft,or shift-right, serial/parallel in, and serial/parallel
out operations with no external gating. Inputs S1 and S2 control.

MC10H141
Four-Bit Universal$hift Register

(See following page)

Function Table

VCC2

01

OUTPUTS

SELECT

02

OPERATION
S1

S2

L

L

00

01

02

03

Parallel entry

L

H

Q1n

Q2n

Q3 n

DR

Shift right*

H

L

OL

QOn

Q1n

Q2n

Shift left*

H

L

QOn

Q1n

Q2n

Q3 n

Stop shift

*

QOn-1 Q1 n -1 Q2n _1 Q3n -1

OL
DO

01
S1

02

outputs· e~jst after pq{se
at "e" inpu-t with input conditions as
shown (Pulse Positive transition 01 clock input).

as

appears

Logic Diagram
PARALLEL ENTER

03
51
10F4
DECODER

52

C~-C>---------------~----4---------~~~-+----------~----}---------~

> : Oeriotes edge triggered clock

03

02

01

00

Por:tions of this Data Sheet reproduced with the courtesy of Motorola Inc,

TWX: 9.10-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408). 97b~9700 TWX: 910-338-2374

MonollthlfJ~trn

Memories In.Il1.LI
13-17

MC10H141
Absolute Maximum Ratings
Supply voltage, VEE (V CC = 0) ......................................................................... , .. -8.0 V to 0 Vde
Input voltage, VI (VCC = 0) .....................................................................•........... 0 Vdc to VE:E
Output Current:
Continuous .........................................•......... ; ........................ ; ..................... 50 mA
Surge ................•..••.......... , .............................................................. , ......... 100 mA

Operating Conditions
SYMBOL

PARAMETER

VEE

Supply voltage

TA

Operating free-air temperature

TSTG

Electrical Characteristics

linH

V

75

-55

150

Ceramic

-55

165

25°

°c

75°

PARAMETER

Input current HIGH

°c

vEE = -5.2 V ±5% (See Note)
UNIT
MIN

MAX

MIN

MAX

MIN

MAX

-

112

-

102

112
255

Pins 5, 6. 9, 11, 12, 13

-

405

-

255

-

Pins 7,10

-

416

-

260

-

260

Power supply current

IE

-5.46 -5.2 -4.94

Plastic

0°

SYMBOL

UNIT

0

I
I

Storage temperature range

MILITARY
MIN TYPMAX

mA

p.A

-

510

-

320

-

320

0.5

-

0.5

-

0.3

-

VOH

HIGH output voltage

-1.02

-0.84

-0.98

-0.81

-0.92

-0.735

Vdc

VOL

lOW output voltage

-1.95

-1.63

-1.95

-1.63

-1.95

-1.60

Vdc

VIH

HIGH input voltage

-1.17

-0.84

-1.13

-0.81

-1.07

.,0.735

Vdc

VIL

lOW input voltage

-1.95

-1.48

-1.95

-1.48

-0.95

-1.45

Vdc

MIN

MAX

MIN

MAX

MIN

MAX

1.1

2.0

1.0

1.9

1.1

2.1

ns
ns

Pins 4,
linL

Input current LOW

Switching Characteristics

vEE = -5.2 V ±5% (See Note)

0°
SYMBOL

25°

75°

CHARACTERISTIC

tpd

Propagation delay

thold

Hold time

p.A

UNIT

I
I Select
Data

1.0

-

1.0

-

1.0

-

1.5

-

1.5

-

1.5

-

3.0

-

3.0

-

3.0

-

tset

Setup time

tr

Rise time (20%-80%)

0.7

2.4

0.7

2.2

0.7

2.4

If

fall time (80%-20%)

0.7

2.4

0.7

2.2

0.7

2.4

ns

fshift

Shift frequency

250

-

250

-

250

-

MHz

ns
ns

NOTE: Eacn Eel 10KH series circuit has been designed to m~et the de specifications shown in the test table, after thermal equilibrium has been established. The

circuit is in a test socket or ,mounted on -a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated
through a 500 resistor to -2.0 V.

Description (Continued)
the four possible operations ofthe register without external gating
ofthe clock. The flip-flops shiftinformation on the positive edge
of the Clock. The four operations are stop shift, shift-left, shiftright, and parallel entry of data. The other six inputs are all data

13·18

type inputs; four for parallel entry data, and one for shifting in from
the left (Dl) and one for shifting in from the right (DR). This device
is a functional/pinout duplication of the standard ECl 10K part,
with 100% improvement in propagation delay and operation frequencyand no increase in power supply current.

MonollthlcWMemorles

ECL 10KH High-Speed
EmiHer-Coupled Logic Family
MC10H158
QUAD 2-lnput Multiplexer
Features/Benefits
•

This document contains specifications and information
which are subject to change.

Ordering Information

• Propagation delay, 1.5 ns typical
I

PRELIMINARY
INFORMATION

PART NUMBER

Power dissipation, 197 mW typical

PACKAGE

TEMPERATURE

J, N

COM

MC10H158

• Noise margin 150 mV
• Voltage compensated
• ECl 10K-Compatible

Logic Diagram

Description
The MC10H158 is a member of Monolithic Memories' ECl
Family. The MCl OH158 is a quad 2-input multiplexer. When the
select line (SELECT) is lOW D_l data appear at the outputs
(03-00). Conversely, when the select input is HIGH, D_O data
appear at the outputs. This ECl part is a functional/pinout
duplication of the standard ECl 10K family part, with 1000/.
improvement in propagation delay and no increase in powersupply current.
.

MC1 OH158 Function Table

*

MC10H158
SELECT 9
001

5

011

3

010

4

SELECT

D_O*

D_1*

Q
021

12

l
l
H
H

X
X

l
H

020

13

l
H

X
X

l
H
l

H

031

10

030

11

D_O/O_1 indicate each of four bit positions for the "zero" or "one" inputs,
as controlled by the select line.

00

000

01

15

02

14

03

VEE Pin 8

X = Don't care.
I

2

Vee Pin 16

Pin Configuration
MC10H158
Quad 2-lnput Multiplexer
Vee
02
03

011

*

NC-No·connection

Portions of this data sheet reproduced with the courtesy of Motorola Inc.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

Monolithic IITlft
IIIemorles Il1.InL.I
13·19

MC10H158
Absolute Maximum Ratings
Supply voltage, vEE (VCC = 0) ...•.........................•....•........................................... -:,8.0 to OVdc
Input voltage, VI (VCC =0) ...............•..........•......... :./...............
. .. ; .• ; .....•...•.•. ,0 VdctoVEE
Output Current:
Continuous ............................... ; •....... , .; .••..............•.. " .. .' ... , ........ ; ............ , ...... 50 mA
Surge ..............•.•.•.. '" " ..•.•....•........•....... " ....•.............•. , ............................ 100 mA

Operating Conditions
COMMERCIAL
MIN TYPMAX

PARAMETER

SYMBOL
VEE

Supply Voltage

-5.46 -5.2

TA

Operating temperature range

0

TSTG

I

Storage temperature range

Electrical Characteristics

I

-55

150

Ceramic

-55

165

25°

Input current HIGH

V
°C
°C

75°

PARAMETER

UNIT
MIN

MAX

MIN

MAX

MIN

-

53

-

48

-

53

Pin 9

-

475

-

295

-

295

Pins 3-6 and 10-13

-

515

-

320

Power supply current

linH

UNIT

VEE = -5.2 V ±5% (See note)

'.
IE

75

Plastic

0°
SYMBOL

~4.94

I

MAX

-

mA
IlA

320

linL

Input current LOW

0.5

-

0.5

-

0.3

-

IlA

VOH

HIGH output voltage

-1.02

-0.84

-0.98

-0.81

:"0.92

-0.735

Vdc

VOL

LOW output voltage

-1.95

-1.63

-1.95

-1.63

-1,95

-1.60

Vdc

VIH

HIGH input voltage

-1.17

-0.84

-1.13

-0.81

-1.07

-0.735

Vdc

VIL

LOW input voltage

-1.95

-1.48

-1.95

-1.48

-1.95

-1.45

Vdc

Switching Characteristics

VEE = 5.2V ±5% (See nole)
25°

0°
SYMBOL

Propagation delay

tpd

UNIT

Data

....

Select
tr

Rise time (20%-80%)

tf

Fall time (80%-20%)

NOTES:

75°

PARAMETER

'.

MIN

MAX

MIN

MAX

MIN

MAX

1.0

1..9

1.0

1.8

1.0

2.0

1.0

.2.9

1.0

2.7

1.0

2.9

0.7

2.2

0.7

2.0

0.7

2.2

ns

0.7

2.2

0.7

2.0

0.7

2.2

ns

ns

Each Eel 10 KH series circuit has been designed to meet the de specificati'ons shown in the test table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 linearfpm is maintained. Outputs are term inated
through a 50n resistor to -2.0 V.

13-20

IIIIonollthlc

W Memories

PRELIMINARY

INFORMATION
ECL 1 OKH High~Speed
EmiHer-Coupled Logic Family
MC10H159
Quad 2-lnput Inverting Multiplexer with E"able

This document contains spe, cilications, ,and information
which are subject to change.

Features/Benefits

Ordering Information

• Propagation delay, 1.5 ns typical

,I •
I

PART NUMBER

Power dissipation, 218 mW typical

PACKAGE

TEMPERATURE

J, N'

COM

MC10H159

• 'Noise mmvin'150 mV

.' vOltage CXlmpensated

Logic Diagram

• ECl10K-pompatibie

MCtOtl159

Description,

i

The MC10H159 is a member of Monolithic Memories' ECL
family. The MC10H159is a quad 2-iriput inverting multiplexer
with enable. A HIGH levelon·the enable input (ENABLE)
overrides the select input (SELECT) and forces all ofthe outputs
(03-00) to the LOW Jevel. A LOW level on the enable input
allows multiplexer action, which is controlled by the select input.
When the select input is LOW, D...1 data appear at the outputs.
Cohy~rsely, 1(Vhen ,the select input is HI(lH, D...O data appear at '
the outputs.

SELECT

9

D01·

5

coo

6

1)11

3

010

4

QO

Q1

,ENABLE 7

MC1 OH1·59 Function Table
ENABLE
L
L
L
L
H

'*

SE,lECT

.

L
L

DO
"

~-

1:1
H
X

....

X
X
L
H

x'

D1
L
H

Q

I

H
L

'x

H

X
X

L
L

021

12

020

13

031

10

030

11

15

Q2

14

Q3

VEE Pin II

:
0_0/D_1 indicate each of 4 bit POSitions for the "zero" or: "one" mputs,

"vee Pin 16

as contrqlled by the select line.
~x • Don't care,

PinConfigur..tion
MC10H159
Quad 2-lnput Inverting Multiplexer with Enable

TWX: 910-338-2376

__ ',....
.
'''lIIIOnolltJ,"/c'm,
morle. ' ,,'.

2175MlssloW:COnege BlVd/Santa Ctara, CAlI50S'MS92 Tet: (408') 970-9700 TWX: 910-338.2374·· . . . .

MC10H159

Absolute Maximum Ratings
Supply voltage VEE (VCC = 0) ................................................................. ~ ....... : ... -8.0 to OVdc
Inputvoltagey~(~cc=O) ...... ,...............: .... , ............................................: ....... OVdctoVEE
Output Current:'. .
' : : . ' ,
Continuous. '" ...... , ..• .' ................... , ....... , ...............:.... .' .............. ,....... .' .................. ,.... ~mA
Surge ..•.•..•............••..••...•......•.. ; •....•.......................••.........•.................••. 100 mA

Operating Conditions
SYMBOL

,

VEE

Supply voltage

T,6.

Operating temperature range

,
"

Tstg

St~rage temperature range ~

Electrical Characteristics
SYMBOL
IE
linH

COMMERCIAL
UNIT
MIN TYPMAX:

PARAMETER

-5.46 -5.2 -4.94

Plastic

-55

150

Ceramic

-55

165

o·

Power supply current
Pin 9

25·
MIN

MAX

. MIN

MAX

-

58

-

53

-

58

295

-

320

-

475
515

320

295
p.A

-

p.A
Vdc"

-1.95

-1.60

Vdc

-1.07

-0.735

Vdc

-1.45

Vdc

0.5

-

0.5

-

0.3

VOH

-1.02

-0.84

-0.98

-0.81

~0.92

VOL

LOW output voltage

-1.95

-1.63

-1.95

-1.63

VIH

HIGH input voltage

-1.17

-0.84

-1.13

-0.81

VIL

LOW input voltage

-1.95

-1.48

-1.95

-1.48

-1.75

VEE = -5.2, V, ±5% (See Note)

O·

tpd

rnA

-0.735

Input current LOW
HIGH output voltage

Switching Characteristics

UNIT

MAX

linL

25·

75·

PARAMETER

' Propagation delay

·C

75·

MIN

Pins 3-7 and 10-13

SYMBOL

V
·C

VEE = -5.2 V ±5% (See Note)

PARAMETER

Input'current HIGH

75

0

UNIT
MIN

M.AX

Data

1.0

,2.2

Select

1.0

3.2

Enable

MIN

MAX

MAX

MIN

1.0

2.0

1.0

2.2

1.0

3.0

1.0

3.2

ns

1.0

3.2

1.0

3.0

1.0

3.2

tr

RisetirTIe (20%-80%)

0.7

2.2

0.7

2.0

0.7

2.2

ns

tf

Fall time (80%-20%)

0.7

2.2

0.7

2.0

0.7

2.2

ns

'.

NOTE: Each .EPL 10,KH "",ries Circuit,!:>'" been designed !Omeelll1e dcs'peclfic~lion. shown in the,ljlSt table, after thermal equilibrium has. been eSla~IIShed.
·1."h~ C!rCuit.i~1~~~,~~ts~~>~t ~~.~.o~nted on a prfnt~d Ci~p:uit b.oard anc;t transverse ai~flow greatertlJan 5QO linearfpm i,a maintained. Outputs'
....
'.
., "
. '., '. . ,.,.,rwX:910-3aa~31&
2175 Mission College Blvd. SanleClara, CA 95054-1592 Tel: (408) 97,,~9700 TWX: 910-338-2374

,

MC10H173
Absolute Maximum Ratings
Supply voltage, VEE (VCC = 0) .....................•..... " ....... , ........................•...•.. " .. .. .• -8.0 to 0 Vdc
Input voltage, VI (VCC =0) ........................................ , .•........•.....•...............•...•• ~ ... 0 Vdc to VEE
Output Current:
.
.
Continuous .................•...............•.......•...•......•.................•.....•..................... 50 mA
Surge ................................................................... .'.: ................................... 100 mA

Operating Conditions
SYMBOL

PARAMETER

COMMERCIAL
MIN TYP MAX

UNIT
V

VEE

Supply voltage

-5.46 :"5.2 -4.94

TA

Operating temperature range

0
....

TSTG

J

Storage temperature range

J

75

Plastic

-55

150

Ceramic

-55

165

°c
°c

Electrical Characteristics vEE = -5.2 V ± 5% (See Note)
25°

0°
MIN
IE

75°
UNIT

PARAMETER

SYMBOL

Power supply current

I Pins 3-7 and 10-13

MAX

. ' MIN

-

73

-

510
475

-

MAX

MIN

MAX

66

-

73

mA

320
300

-

320
300

p.A

0.3

-

p.A

linH

Input current HIGH

linL

Input current LOW

VOH

HIGH output voltage

-1.02 •

-0.84

-0.98

-0.81

-0.92

-0.735

Vdc

VOL

LOW outPl,Jt voltage

-1.95

-1.63

-1.95

-1.63

-1.95

-1.60

Vdc

VIH

HIGH input voltage

-1.17

-0.84

-1.13

-0.81

-1.07

-0.735

Vdc

VIL

LOW input voltage

-1.95

-1.48

-1.95

-1.48

-1.95

-1.45

Vdc

I Pin9

-

-

0.5

-

-

0.5

~

Switching Characteristics VEE = 5.2 V ± 5% (See Note)
0°
SYMBOL

25°

75°

PARAMETER

UNIT
MIN

MAX

MIN

MAX

MIN

MAX

tpd

Propagation delay

Data
Clock
Select

0.7
1.0
1.0

2.3
3.7
3.6

0.7
1.0
1.0

2.1
3.5
3.4

0.7
1.0
1.0

2.3
3.7
3;6

tset

Setup time

Data
Select

0.7
1.0

-

0.7
1.0

-

0.7
1.0

-

thold

Hold time

Data
Select

0.7
1.0

-

0.7
1.0

-

tr

Rise time (20%-80%)

0.7

2.4

0.7

tf

Fall time (SOOfo.'20%)

0.7

2.4

0.7

-

-

ns

ns

0.7
1.0

-

ns

2.1

0.7

2.4

ns

2.1

0.7

2.4

ns

NOTE: Each Eel 10KH series circuit has been designed to meet the de specifications shown in the test table, after thermal equilibrium has been established.
The circuit Is in-a--test sockator mounted on a"pr~nted circuit board and transverse ai-r flow greater than 500"linesr fpm is maintained. Outputs are terminated
thrOugh 8500 resistor to -2.0 V.

13·24

IIIIonoIlthIoW Memories

PRELIMINARY
INFORMATION

EeL .10 KHHigh-Speed
Emitter-Coupled Logic Family
MC10H210/MC10H211
3-lnput, 3-0utput OR/NOR Gates

. This document contains spe~
cifications" and information'
which ar~.subject to change.

Ordering Infonnation

Features/Benefits
• Propagation delay, 1.0 ns typical

PACKAGE. ····TEMPERATURE

PART NUMBER

• Power..dIsslpaUon, 160 mW typical
• No~ marglnJ50 mV (0""- operating voRage
and ternPeraturaral!ge)

J

MC1OH210
MC1OH211

Com

N'

• Voltage compensated

• ECl1OK-compatibie
MC1OH210

Description
The MC10H210 and MC10H211 ara members of Monolithic
Memories' ECl family. These devices ara dual3-input, 3-output
"OR" and "NOR" gates respectively. These ECl 10KH parts are
functional/pinout duplications of the standard ECl 10KH family
'parts, with 100% improvement in propagatiOn delay andno in- .
craase in power ~pply current.
.

MC1OH211

..... _ 6
2
Aln15~
7
3

~1n3'
c.

.

...

;;out.!

4A:::

~n! 5

Ajn3~

"IIU

.
3
~2:;

.4.

!..al~·'0~14
1,~,.~··
'.'
9'~~~ .a:::
~
.
a
1n1..
In3
hI2

',23'aa'out10ut2'"

14aOl!l3. '

a in1

l n3 11

.

Pin Configuration.
MC1OH210
3-INPUT 3-0UTPUT OR GATE

.. Pins 1 and 151ntemally connected

MC10H211
3-INPUT3-0UTPUT NOR GAT.E

*

Pinsl and 15 intemallyconneeted .

. Portions of Inis Data Sheet reproduced'with 1f>e 60urtesy of Motorola Inc.
.

".

,'".,,'

MC10H210/211
Absolute Maximum Ratings
Supply voltage, VEE.(VCC = 0) .............................................. c ............................... -8.0 V to 0 Vdc
Input voltage, VI (VCC= 0) ................................................ , ......... ; ......................0 Vdc to VEE
Output Current:
Continuous .................................................................................................. 50 mA
Surge ........ ; .. ; ........... ; ...... ; ... ; .................................................................... 100 mA

Operating Conditions

'.

SYMBOL

COMMERCIAL
MIN TYP MA.X

PARAMETER

VEE

Supply voltage

-5.46 ,..5.2 -4.94

TA

Operating free-air temperature

0

Electrical Characteristics

V

°c

VEE = -5.2 V ±5% (See Note)

0°
SYMBOL

75

UNIT

25°

75°

PARAMETER

UNIT
MIN

MAX

MIN

MAX

-

42

-

38

-

42

mA

'-

450

fJoA

IE

Power supply current

linH

Input current HIGH

-

720

-

450

linL

Input current LOW

0.5

-

0.5

-

MIN

MAX

0.3

-

fJoA

VOH

HIGH output voltage

-1.02

-0.84

-0.98

-0.81

-0.92

-0.735

Vdc

VOL

LOW output voltage

-1.95

-1.63

-1.95

-1.63

-1.95

-1.60

Vdc

-1.17

-0.84

-1.13

-0.81

-1.07

-0.735

Vdc

-1.95

-1.48

-1.95

-1.48

-1.95

-1.45

Vdc

VIH

HIGH input voltage

VIL

LOW input voltage

.

.

Switching Characteristics VEE -5.2 V, ± 5%,
0°
SYMBOL

25°

75°
UNIT

PARAMETER
MIN

MAX

MIN

MAX

MIN

MAX

tpd

Propagation delay

0.7

1.6

0.7

1.5

0.7

1.7

ns

tr

Rise time (20%-80%)

0.7

2.2

0.7

2.0

0.7

2.2

ns

tf

Fall time (80%-20%)

0.7

2.2

0.7

2.0

0.7

2.2

ns

NOTES: E~ch E,CL HJKH seri~s circuit has bee'n des_igned to meet the de specifications shown in the test table, after thermal equilibrium,has been established.
The circuit is in a test sock-et or mounted on a printed circuit board and transverse airflow greater than 500 linear fpm is maintained. Outputs are terminated
through a .50n resistor to·,..:.2.0 V.

MonolithIc WMemories

Definition of Terms and Waveforms

Setup Time
Setup time,

1l'uth Table Explanations

tau

The time interval between the application of a signal that Is
maintained at a specified input terminal and a consecutive active transition at another specified Input terminal.
NOTES: 1. The setup time is the actual time between two
"events and may be insufficient to'accomplish the
setup. A minimum value is specified that ,Is the
shortest Interval for which corre,ct operation, of the
logic· element is guaranteed. " , ;
, , ,2; Ths'$EiWptlme may have a negative, value in which
the rilinimum limit defines the longest Interval
(b!ltween the active transition and ,the application of
the otherslgnai) for which' correct Opel'!ltion of the
logic element Is guaranteed.

00

vOltage

On

case

"

HICih~lilV" Inputvoltag8, VIH

'" :An'lnput volta~ Within the ,mo~ positive ,(less negative) of the
, :IWO ranges of valUeS USed 10 represent the binary v,ariables.
"NOTE:' Amlnimum Is specified that is the least positive value of
"high.level vo"agefor which operation of tbe logic ele" ' mem,Withln, specification limits is guararit"$8d.

High-level output voltage, VOH

'

The ~oltage at an oUtput terminal with inputoonditidns !lPplied
that according tottie prQduct specification will establish a high
level at the, output: ,', , ' ,
,.
Input I?lamp yahge, VIC "
,An input VOltage in a region o/relatively low differlilntia1 resistance that, serves to limit the inpu,t voltage swing.

low-lev,.ilnputvoltag&,VIL\,.
An input voltage level within' the less positive (more negative) of
the two ranges of v,alues used to represent the binary variables.
NOTE: Amaiiimu~ i$ speci#EKI that is the most positive value of
loW-leVel input voltage'tOr which operation of the logic
element, within specification limits is guaranteed,
l.ow*v.r'oUtl'utvOnage, "OL
'The voltage alan output terminal, with input coriditioris applied
that according 'to the product Speqifioation wi,ll establish a low
levela:tthe.O~tput.:" "
.; ,'!
"

Ntt9at1ve:goi~ thresho.cfvolt8iJe.VT

·:~TIi&.voltage !~vel ~t aifan~iti~n-op~r!lted input that c~uses op,e,r!(tion 'of, thEl:'logjc etement according' to Spe6iljcatiO(las the
,Inp!.!! volt!lge falls "from, a level !lbove the,: positive-going
thr\ilshq!\l, voltage, YTf', ",
"
,

PO$iUv.1IoJn9 thr.s~I'd yoltage. Vn

Theyoltage level ,at, a" transitiB,no()perated :input that causes dp~
• • er'a~~n 1>'. the\lpgl,~ :ele.me,nt:atCOrdingt<>specificatiOri .'as th6
inpuLYQltage.ri~,Jrol;"('r, a level,b,e,low 'the,n~gali\le-going
threshold voltag~ \IT..,.

14·2

= high level (steady-state)

H
L

=

i

= transition from low to hig~ level

~

= transition from high to low level
= irrelevant (any Input, including tranSitions)

X
Z
aoOh
00

low level (steady-state)

= off (high-impedance) state of a 3-state output

=

the level of steady-state inputs at inputs A through
H respectively
= level of 0 before the indicated steady-state Input
conditions were established
= complement of 00 or level of 0 before the indicated
steady-state input conditions were established
level of 0 before the most recent active transition
indicated by ~ or i

If, in the input columns, a row contains only the symbols H, L.
and lor X, this means the indicated output is valid whenever the
input configuration is aChieved and regardless of the sequence
in which it is achieved. The output persists so long as the input
configuration is maintained.
If,in the input columns, a row contains H, L, andlor X together
with i and lor ~, this means the output is valid whenever the input
configuration is achieved but the transition(s) must occur following the achievement of the steady-state levels. If the output is
shown as a level (H, L, 00, or 00), H persists so long as the
steady-state input levels and the levels that terminate indicated
transitions are, maintained. Unless' otherwise indicated, input
transitions in the' opposite direction to those shown have no
effect at the output.

Definition of Terms and Waveforms
Clock Frequency

Output Enable and Disable Time

Maximum clock frequency, 'max

Output enable time (of a three-state output) to high level,
tPZH (or low level, tPZL)

The highest rate at which the clock input of a bistable circuit can
be driven through its required sequence while maintaining stable
transitions of logic level at the output with· input conditions established that should cause changes of output logic level in accordance with the specification.

The propagation delay time between. the specified reference
points on the input and output voltage waveforms with the
three-state output changing from a high"impedance(off) state to
the defined high (or low) level.

Output enable time (of a three-state output) to high or low
level, tPZX

Current
High-level input current, IIH
The current into • an input when a high-level voltage is. applied
to that input.

High-level output current, 10tt
!

The current into • an output with input conditions applied that
according to the product specification will establish a high level
at the output.

High-level output current, ICEX
The high-level leakage current of .an open collector output.

Low-level· Input current, IlL
The current into 'an input when a low-level voltage is applied to
that input.

Low-level output current, 10L
The current into. ' an output with input conditions applied that
according to the product specification will esta.blish a low level at
the output.

, Off-state (high-Impedance-state) output current (of a
three-state output~ 10Z

The propagation delay time between the specified reference
points on the input and output voltage waveforms with the
three-state output changing from a high-impedance (off) state to
either of the defined active levels (high or low).

Output disable time (of a three-state output) from high level,
tPHZ (or low level, tPLZ)
The propagation delay time between the specified reference
pOints on the input and output voltage waveforms with the
three-state output changing from the defined high (or low) level
to a high-impedance (off) sta.te.

Output disable time (of a three-state output) from high or
low level, tpxz
.
The propagation delay time between the specified reference
points on the input· and output voltage waveforms with the
three-state output Cl1anging from either of the. defined active
levels (high or low) to a high-impedance. (off) state.

tEA is the output enable access,tlme of memory devices.
tER is the output disable (enable recovery) time of memory
devices.

!

The current into' an output having three-state capability with
input conditions applied that according t6 the product specification will establish the high-impedance state at the output.

Short-circuit output current, lOS
The current into· an output when that output is short-circuited to
ground (or other speCified potential) with· .input conditions
applied to establish the output logic level farthest from ground
, potential (or other specified potential).

Supply current, ICC
The current into * the VCC supply terminal of an integrated
circuit.
* Current out of a terminal is given as a negative value.

Propagation Time
Propagation delay time, tPD
The time between the specified reference points on the input
and output voltage waveforms with the oVtpl,ll,changing from
one defined level (high or low) to the other defined level.

Propagation delay time,

10w-to-high~level

output, tpLH

The time between the specified reference points on the input
and output voltage waveforms with the output changing from the
defined low level to the defined high level.

Propagation delay time, high-to-Iow-level output, tPHL
The time between the specified reference points on the input
and output voltage waveforms with the output changing from the
defined high level to the defined low level.

Hold Time
Hold time, th
The interval during which a !lignal is retained at a specified input
terminal after an active transition occurs at another speCified
input terminal.
NOTES: 1. The hold time is the actual time between two
events and may be insufficientto accomplish the
intended result. A minimum valve is specified that
is the shortest interval for which correc! operation
of the logic element is guaranteed..
2. The hold time may have a negative value in which
case the minimum limit. defines the longest interval
(between the rblease of data and the active transitiOn) for which correct operation of the logic ele,
ment is guaranteed.

tAA Is the address (to output) access time of memory devices.

Pulse Width
Pulse Width, tw
The' time interval between specified reference pOints on the
leading and trailing edges of the pulse waveform.

MonolllhlclRlJ] Memories

14-3

f4 vailable Literature

AVAILABLE
LITERATURE
Military PrQductsOivision Brochure
Monolithic Memories Inc. Annual 'Report
PROM CrOSScReference Guide
.
SHRP:...super High Reliabiljt}tProduets BroCiln~e
PROM/Programmer'sReferance Guide
Leildlliss Brochure ' '.

BOOKS
LSI Data Book
PAL Handbook
System DeSign Handb6ok.
PLE Handbook

APPLICATION NOTES
(Standalone)
AN-100

PROMs, PALs, FIFOsi AND MULTIPLIERS TEAM UP TO
IMPLEMENT SINGLE-BOARD HIGH-PERFORr.tANCE
AUDIO. SPECTRUMANAL'lZER
(SyatemHandbook, seCtt.on1)
Theteilmwork of a logic device (PAL), a memory device (PROM),:a
buffer (FIFO), and multiplier chips makes cost-effective and efficient digital signal processing (OSP). This idea is illustrated
through the audio spectrum analyzer, but is not limited to that use.
Creative designers will soon develop low cost/high performance
architectures that can perform as well as the example given.
AN-115
THE DESIGN AND APPLICATION OF
A HIGH.SPEED MULTIPLY/DIVIDE
BOARD FOR 11fE STD BUS;
Northcon/82St1as1on 15
(System.DesIgi, Hailndbooki SectIon 5)
A fundamental limitation in most inicrocomputer systems is highspeed arithmetic computing speed, especially when multiplications or divisions are required: Ahardwarernultiply/divide board
designed to work efficiently with a STO BUS microcomputllr in an
industrial control system .is .presented.
The (lescribed. includes the. simultaneous calculation 01 several
digitally-controlled servo loops which. aUow control of machinery
to within the resolution of servo pOSition sensors at a bandwidth
th8tsoftWare alone cannot accomplish.
.AN-118
PSEUDORANDOM NUMBER GENERATOR
(A DISGUISED PAL)
(System De8l9n Handbook. SecUon 9)
Due to their interesting properties, Pseudo Random Numbe.rs
(PRN) are usefUl across a wide spectrum of applications, including
secure communication,' test pattern generation; ScratnbleHriand
radar ranging systems. For the requirements afa given application, a "customized" PRN generetor Is readily it(lp,lemented using
•
.
PAls.

14-4

AN-123
SHADOW REGISTER ARCHITECTURE SIMPLIFIES
.' D.IGITAJ.. DIAG.NOSIS
. '.
.
(System pe.ig~ Handbook, SecUon 2)
A series of new del/ices including register and PROMs with diagnostic, no.", make hasier for system. designers to include diagnostic circuitry in microprogramml!Cl systems. When in the diagnostic mode, these devices allow. for completesysteln controllability and observability with minimum of additional hardware.
Other schemes such as embedding diagnostic code i.n a digi\81
system and LSSO (Level-Sensitive Scan Design) have 'been uSed
in the pass but these techniques have tti'eir drawbacks. This new
.series of. products as' well as microprogrammed architectures
using these products will be explored in this paper.

a

AN-126
PROM.s AND PLEa: .AN APPLICATION PERSPECTIVE
Programmable Read Only Memories are widely used .in digital
systems, both as a memory device; as well as a .Programmable
Logic EIE!menl (PLE",). This' document describasthe u~ 01.
PROMs and PLEs in many practical applications ranging from
Diagnostic Microsequencers, to M-Blt Parallel CRC. The concept
of testability and built-In Diagnostics in the PROMs is also
illustrated.
AN-127
.'
..
,DIAGNOSTIC DeviCES AND ALGORITHMS FOR
TESTING DIGITAL SYSTEMS
A new concept called Diagnostics On Chip'" (OOC~"l was introduced in the Industry recently. A series of nE!W products with
shadow register diagnostic capability Is cOming. These new products use this new concept and will provide a cost-effective
sOlution to the. issue. of testability for digital systemS: .
AN-128
THE THIRD WAV.E HITS SILICON VALLEY
High-technology products and industries are not exempt fl:om
the effects of major long-term social trends. Some of todays trends
are customization or "de-massificatlon," decentrelization; selfhelp, user-friendliness or "high touch:.' and appropriate scale.
These trends are already affecting the ways in which semiconductors are dlilsigl)ed and used, and suc~ l:Iuman-factors :issues
will be crucialiy important in the near tiJiure.
. .
AN-129

HIGH·SPEEDPROMS WITH ON-Chip REGISTERS
AND DIAGNOSTICS
A family of High~Speed Registered and Diagnostic PROMs offer
new savings for systemd!lSigners.The REl9iStered ,PROM family
fe8tures on-chip "0" -type output registers WhlciT"Bre usefUl in
pipelined systems and state machinell. In ad~ition to output registers, the Oiagrio~~ic: PR9MsfeIItillll I! Shadow Register Which
makeS It easlerfbr system designerS to Include diagnostics in
niic;:rop,rogrammed~ystems.. Architectures .and applications for
these lIeviC$S are discussed in this peper.
AN~130

NEXT'GENERATIONPROGRAMMABLELOGIC
prOgrainmablelogicdevic~shave e~oliied from simple combinatorial 8riays to devices with features and densities lhat rival gate

Available Literature
The Single Burst Error Recovery chip, SiBER, can correct 5, a, or
11-bit bursts of error or detect double burst errors in high-speed
serial data bit streams. This paper describes serial-data error
detection and correction in host indepE!ndent and peripheralindependent environments. The SiBER implements the standard
CCITT CRC polynomial and a computer generated polynomial in
one 24-pin bipolar LSI chip.

arrays. This paper opens with a description of second generation
PAls; specifically, MegaPALs and Registered-Asynchronous PAls.
Then a new concept in programmable logiC, called PLE, is introduced. A discussion of design methodology for programmable
logic devices fOllows. The paper closes with a description of
present and next generation software tools, PALASM2 and
PLEASM, including several application examples using these
software tools.

CP-11.4
A DSP ARCHITECTURE FOR A 4800BPS MOD!;M
This paper describes a hardware configuration of a multiplier chip,
the 748516 and an a-bit microprocessor, the a051 , and together
with other IC's they form a digital signal processor.

AN-131
NEW PAL~ ARCHITECTURE PROVIDES SYNCHRONOUS AND
I ASYNCHRONOUS FEATURES IN A SINGLE PACKAGE
I
I

The new PAL20RA10 is the ultimate general purpose tool for
integrating random logic system "glue" and asynchronous control/handshake Circuitry. Both synchronous and asynchronous
circuits maybe integrated within the samE! PAl.., with a considerable reduction Of package count .

This DSP is used to build a modem where the main task is to
convert the received signal into a 48-bits/second serial stream.
CP-11S
MEMORY ALIASING TO IMPROVE
MATH PROCESSOR PERFORMANCE*

AN-132
ARITHMETIC COMPUTING FOR INDUSTRIAL CONTROL

During the past few years, microprocessors have found applications in almost every field. However, those areas requiring highspeed mathematical operations have been limited by the relatively
slow multiply and divide operations. The recent introduction of
high-spe.ed multipliers and multiplier/dividers has helped to alleviate this problem. In many cases, more time is now spent getting
data to and from these devices than is used for the actual computation. This paper presents a method called "Memory Aliasing" that
reduces the data flow time to half olthe nominal value. A discussion of what constitutes memory aliasing and how to use it is
provided. A case study illustrates the performance improvements
using a ZaOO2B. microprocessor and a Monolithic Memories'
748516 multiplier/divider.

The availability of various new multiplier/divider integrated circuits
has enabled inexpensive microprocessor systems to perform realtime control tesks that previously required high-performance minicomputers. By joining the speed ofa multiplier with the versatility of
a microprocessor, real-time control tasks can be implemented with
reasonable cost and goOd performance. Such real-time applications include motion-control, tool positioning and other related
servo-loop control functions.

I

This paper describes a hypothetical control system for an Indus"
trial process that' currently exists. The concept of an arithmeticaided microprocessor is presented mindful otthis real application,
and the subject is developed tutorially. By reviewing the various
issues of a real system and the benefits provided by the compOSite
of math IC and microprocessor in this manner, new applications
should become evident.

I

AN-134
.
DYNAMIC RAM CONTROLLER AND PAL~
SIMPLIFY MC6809ETO 64K DRAM INTERFACE

I

,I

!

I

I

CP-116
SYSTEM SOLUTIONS FOR A HIGH-SPEED PROCESSOR
USING INNOVATIVE ICs
The need for high-speed building blocks forpipelined processors
is prEivalent The following. article is a description otthe elements of
a high speed processor design that uses an instruction lookahead
unit, control store unit and floating point adders, subtracters and
multiplier.
.

Mostmicroprocessor systems use dynamic RAM for data and
program storage because it is still the most effective way of realizing large memory array configurations with a relatively.small total
component cost. Compared with static RAM,. dynamic RAM
requires more complex interface and .refresh control circuitry,
representing an increase in chip count on dynamic FlAM boards.
Fortunately, th.is problem of interface and refresh has' been
reduced by the availability of a number of dedicated LSI dynamic
RAM .controller chips. Also, with the application of PAL Programmable Array Logic, microprocessor and DRAM controller interface
may be simplified.

CP-117
LSI CONTROL AND ERROR
CORRECTION FOR DYNAMIC RAMS
Dynamic Random Access Memories (DRAMs) take a leading
place as a semiconductor volatile storage medium. Formerly used
strictly for moderate-performance low-cost applications, dynamic
memories tOday are more attractive fOr high-end applications due
to greater density and better ACPElrformance,and they draw more
designers to c<'pe with the more complicated access and refresh
schemes nileded fOr the dynamic RAMs.
The purpose of this paper is to present sev.eral LSI solutions for
DRAM control and Error Detection and Correction (EDC) along
with examples to Show their place in a system.

CONFERENCE PROCEEDINGS
CP-113.
SERIALIZING FIFO AND BURST ERROR PROCESSOR
TEAM UP TO ENHANCE SERIAL DATA RELIABILITY

CP-118(W1I/ be available soon.)
THE ABC OF DYNAMIC RAMS

In high-speed serial data transmission, as in state-of"the~art disk
drives and data communication there is a growing need fOr data
.
reliability.

Monolllhic

Dynamic Random Access Memories (DRAMs), being dense and
cost effective, take a leading place as semiconduclorvolatile

m

Memories

14-5

[9

I

I

Available Literature

storage medium. Forl\1erly used strictlyformoderate-performance
low-cost ..~pplications•. dynamic RAMS .. today get laster. and
become more attractive for high end applications as welt In order
to take advantage of thecostefiiciency of the dynamic RAMs,
more designers are willing to cope with. the more complicated
access and refresh schemes.
The purpose of this paper is to introduce the dynamic RAMs to the
designer unfamiliar with this form of memory. A short comparison
between static and dynamic RAMs is followed by descriptions of
access and refresh cycles for the dynamic RAMs. Several refresh
strategies are discussed and a system solution is presented.

CP-119 (Will be available soon.)
The· A-TO-Z OF HIGH-SPEED PRIORITY ENCODERS:
ARBITRATION TO ZERO DETECTION
Priority encoders are classical "Medium-Scale Integration" '(MSI)
logic-operator devices. They were originally developed for parallel
scanning of interrupts and status signals. Subsequently,theyhave
been L1sed fOr normalization scanning in hgh"performance floatingpoint adders/subtractors, for control of digital-system buses and
other centralized resources, and for other specialized applications
which assume the same basic logical form.
Today very-high-speed TfL-compatible. priority encoders are
finally available, in both totem-pole-output and three:state-output
forms. The cascadable architecture of these parts allows for
. economical and convenient scanning 6f any number of inputs.

CP-120 (Will be available soon.)
LSI CONTROL AND ERROR CORRECTION FOR
DYNAMIC RAMS
Dynamic Random Access Memories (DRAM), take a leading place
as semiconductor volatile storage mediul\1. Formerly used strictly
for moderate-performance low-cost applications, dynamiC memories today are more attractive for high-end applications due to the
greater density and better Ac performance,' and draw more
designers to cope with the more complicated access and refresh
schemes. needed for the dynamic RAMs.
The purpose of this paper is to present several LSI solutions for
DRAM control and Error Detection and Correction (EDC) aiong
with examples to show their place in a system.

CP-122
HIGH-PERFORMANCE DIGITAL MUSIC SYNTHESIS
The goal of presenting the digital synthesizer in this paper is to
demonstrate a more unified system for a variety of situations. The
synthesizer is useful for many artistic explorations besides traditional musical concerts. This design is aimed at new ~pplication
areas where the interface requirements preclude effective 'use of
present machines. It maintains the broad capabilities at a low cost.
Part of. the development of. this project is research into sound
generation metho~$. The primary signal processing teChnique for
the system is CORDIC. The CORDIC algorithm is introduced in this
paper along with a short history..
An expanding bibliography is included for the benefit of new
rese~rch. We hOPe that new applications will re.sult from sOl\1eof
the information.

CP-123
MULTIPROCESSING ARCHITECTURES: .
A NEW FRONTIER FOR VLSI.APPLICATIONS
Except for special.application areas, computer performance has
generally been enhanced and achieved by the requirements of
Von Neumann's baSic concepts. Advances in semiconductor
components have had more influence on computer performance
than any other single factor.
Over the last few decades, the major thrust in computer technology has been to increase the raw computing power of large
machines. For complex applications, high-speed number crunching, and new innovative applications, there isa demand·for multiple microprocessor systems to prOvide additional computing
power.
In t!:lis paper we will discuss the architecture of a typical system
which has a main microprocessor doing' decision jobs andnumber crunching, etc., while being helped by four other I/O
processors. In other words, this paper deals. with hardware building blocks for a multiprocessing system.

ARTICLE REPRINTS
AR.1.00
PAL SHRINKS AUDIO SPECTRUM ANALYZER
(PART 1 OF 2)
Using an audio spectrum analyzer as the example, the author
demonstrates how PAls can'reduce board space, maximize performance, save money, and. improve quality for DSP. Specific
diagrams' offer ways a designer. can· build versatility into the
microprogram to create other appJications.
AR-101
PAL SPECTRUM ANALYZER IMPROVES PERFORMANCE
(PART20F2)
Continuing the idea from the first part. of this two part paper
(AR-100), the author adds ideas from the reality of high performance to the use of PAls in DSP architecture. Control logic is the
key to success since PAls have flexibility coding. Simplified tables
and diagrams round out the author's illustration.
..
AR"1011
STATE.OF-THE-ART IN HIGH SPEED ARITHMETIC
INTEGRATED CIRCUITS
Use of bipolar technology to construct arithmetiC ICs has resulted
in deviceswith increasing switching speed and gate density and
low power' dissipation. Future· technological advances Should
have an even greater impact on product performance through
larger wafer diameters and sharper pattern fabrication.
AR-109
.,
AN II x II MULTIPLIER AND II-Bit MICROPROCESSOR
PERFORM 16 x 16 BIT MULTIPLICATION
A special algorithm implemented in software doubles an 8 x8-blt
multiplier's usual capabilities, permitting efficient 16 x16 multiplications of I!igned,unsigned or mixed two's-complementnumbers.
The articie presents this requisite multiplication algorithm as It 18
implemented on a zeo ,.p utilizing the SN74S558.

Monolithic WMemorles

Available Literature
AR-110
REAL-nME PROCESSING GAINS GROUND WITH
FAST DIGITAL MULnPLlCATION
RefinemenlS in algorithm and hardware have Improved the speed
and power of single-chip multipliers. These chips can speed the
complex operetions needed for digilal treatment which previously
could be carried out off line using large computers. Functions like
autocorrelation and fast Fourier transforms necessary for dlgilal
: filtering and compression, for example, can now be done in real
~ time using these new multipliers. Algorithms and specific appll,; I cations for these new multiplers are given in this paper.
\

AR-116
ON.cHIP CIRCUITRY REVEALS SYSTEM'S LOGIC STATES
As computer and data processing systems grow in size and complexity, designers must continue to refine the methods needed to
test them. One methOd, based on serial scan diagnostics, affords a
systematic diagnostic technique for pinpointing hardware failures
In a digilal system. The diagnostic capability is implemented in a
system by adding special hardware that enables key test poinlS to
be sampled and Important control signals to be stimulated. Systemscontaining the diagnostic hardware are simple to test and are
usually more reliable. this diagnostic technique and the two families of devices whch Incorporete this diagnostic hardware (Diagnostic PROMs and 8-Bit Register) are the subject of this paper.

AR-117
SINGLE-CHIP CONTROLLERS COVER RAMS
As dynamic RAMs become widely used, demand is growing for
automatic sequencing of RAM access signals and refresh controls. NSC's DP8408 and DP8409 are single-chip dynamic RAM
controllers available also from Monolithic Memories as the
74S408/9 series.

A short description of dynamiC RAM operation is provided and
both devices are described in several applications.
AR-118
PROGRAMMING CHIPS ON

PERSONAL COMPUTERS
Programmable Array Logic chips are fast becoming an economical alternative to custom integrated circuilS. Personal computers
can assist in the design of programmable arrays, further reducing
the cost of developing custom electronic logic. PALASM, the CAD
tool for PAls, which was previously available only for mainframes
and minicomputers, is now available for many popular personal
computers. This article outlines the design process for PAls using
PALASM and personal computers.
AR-119
BIPOLAR ARITHMETIC CHIP
SPEEDS 68OOO's MATH THROUGHPUT
Although no 68000-famlly coprocessor is yet available to help the
16-bit processor perform double-precision and floating-point
operations, a general-purpose multiplier/divider can, without significanUy boosting the system cost

Notes

14·8

Advanced Information

I f-'"M

Advanced Information Section
Products listed in this section were due for imminent release at
the time of printing. Please contact Monolithic Memories for
current availability and full parametric specifications.

Table of Contents
ADVANCED INFORMATION
Contents for Section 15 ............................. 15-2
53/63S880
1024x8 bit PROM ...................... 15-3
S881
1024x8 bit PROM ...................... 15-3
S881A 1024x8 bit PROM ...................... 15-3
53/63S6481 8192x8 bit PROM ...................... 15-4
S6481A 8192x8 bit PROM ...................... 15-4
54/74S419 FIFO RAM Controller ..................... 15-5
SN74S480 SiBER (Single Burst Error Recovery IC) ..... 15-6
PAl20B Series ..................................... 15-7
PAl® Series 20AP wlProgrammable Output Polarity ... 15-9
PAl® Series 24AP w/Programmable Output Polarity .. 15-11
10HPAl20P8 (ECl PAL) .......................... 15-13
ZHAl'· 20 CMOS Hard Array logic Devices ......... 15-15

15-2

Monolithic

m

Memories

Monolithic

W Memories

High Performance
1024x8PROM

53/635880
53/6358tJ1

53/635881 A

II I I II I III IIIII//i/i//////////////////////IIIIADVANCE INFORMATION
I

Featuresl Benefits

Applications

• 8192-bit memory

• Microprogram control stores

• Reliable titanium-tungsten fuses (TI-W) guarantees
greater than 98% programming yields

• Microprocessor program store

• Low voltage generic programming

• Character. generator

• Pin-compatible with standard Schottky PROMs

• Code converter

• PNP inputs for low input curre"t

• Programmable Logic Element (PLE'") with ten inputs,
eight outputs and 1024 product terms per output

• Open collector and three-state Ol!tputs

• Look-up table

• 24-pln SKINNYDIP® package and 28-pln plastic chip
carrier for high board density
,

Preliminary Data

Description

tAA = 35 ns
tEA/tER = 25 ns
ICC= 175 mA

The 53/63S880 and 53/63S881/A are1Kx8 bipolar PROMs
featuring low input current PNP inputs, full Schottky clamping
with open collector or th ree-state outputs. The titanium-tungsten
fuses store a logical low and are programmed to the high-state.
Special on-chip circuitry and extra fuses provide preprogramming testing which assures high programming yields and high
reliability.
'

Pin Configurations

I
The 63 series is specified for operation over the commercial
, temperature and voltage range. The 53 series is specified for the
military ranges.

Programming
The 53/63S880 and 53/63S881/A PROMs are programmed with
the same programming algorithm as all other Monolithic Mem"
ories' generic Ti-W PROMs. For details refer to Monolithic
Memories' LSI Data Book,

Block Diagram
22
AS
23
AS
1
A7
2
AS
AS

A4

A3
A2

1-0.3;n·-1

128x64
PROGRAMMABLE
' 'ARRAY

AS A6 A7 NC VCCAS A9

4

5
6

A4

E1

A3

E2

A2

E3

A1

A1

E4

AI)

AI)

NC

NC

08

01

07

02 03 GND NC 04 05 06
PALOO is a registe:reQ t~ademarKR~_Mo~olit~iC Memories.
PALASM'·,is a trademark 01 Monolithic Memories,

TWX: 910-338-2376

I 2175 Mission CQllegeBIYd.'Santa Clara,CA 95054-1592 Tel: {408) 970-9700 TWX: 910-338-2374

.lImn

Monolithic
Memories U1JlW
15.. 3

Monolithic

W Memories

High Performance
8192x8PROM

53/6356481
53/63564Q1A
PLE 13P8

I I I I I I I 1/ I I I I I I II IIIIIIIII/IIIIIIIIIIIIII///IADVANCE INFORMATION
-

Typical Applications

Features/Benefits

• Microprogram control store

• 65536-bit memory

• Microprocessor program store

• Greater than 99% programming yields
• Low voltage generic programming

• Look-up table

• Pin-compatible with standard Schottky PROMs

• Character generator

• PNP inputs for low input current

• Code converter

• Three-state output enable

• Programmable Logic Element (PLE'M) with thirteen inputs,
eight outputs and 8192 product terms per output

• 8-bit wide output

Preliminary Data

• 24-pin standard DIP package and 28-pin plastic chip
carrier for high board density

tAA =45 ns
tEA/tER = 25 ns
ICC = 190 mA

Pin Configurations

Description
The 53/63S6481 and 53/63S6481 A are high-speed 8Kx8 PROMs
which use industry standard pinouts.
The family features low-current PNP inputs, full Schottky
clamping, and three-state outputs. The fuses store a logical low
and are programmed to the high state. Special on-chip circuitry
and extra fuses provide preprogramming testing which assures
high programming yields and high reliability.
The 63 series is specified for operation over the commercial
temperature and voltage range. The 53 series is specified for the
military ranges.

Block Diagram
A12
All
Al0
A9
A8

18
19
21
22
23

A7

1

A6
AS

A4
A3
A2
Al

256x256
PROGRAMMABLE
ARRAV

1 OF 256
ROW
DECODER

AS A6 A7 NC VCCAB A9

2
3

1.-_---'
A4

Al0

A3

E

do~~:1'l

A2

All

DECODER

Al

A12

4 ,----.,

5
6
7

AO

01

PLE"'" is a

tradem~rk

02

03

04

05 .06

07

08

AO

NC

NC

08

01

07

02·. 03 GND NC 04 05 06

of Monolithic 'Memories.

TWX: 910-338-2376
2175 MiSSion College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

15·4

Monollthlo~1I11

Memories InJnJ.I

IIIIonollthlo

m

FIFO Ram Controller
54n4S419

lIIemorles

I I I I I I I III I IIIII/////////////////////////II!IADVANCE INFORMATION
Features/Benefits

Typical· Applications

• High speed

• LAN equipment

• Deep FIFOs - 16 addrelses for SRAM

• Data communication

• Arbitration readlwrite

• Dlakltape controllers

• COntrollignall for data latching

• Host to Dedicated Proceuor interface

• Full, half-full, emptY and almolt-fullflagl for any buffer lize
from 512 to64K

Pin Configuration

• Expandable

CLK.

1

• Three-state outputs

BFO

,

DescrIption
The. 54n4S419 FIFO Ram Controller provides addreSsing,
control, status and arbitration·for a.shared SRAM used.8S a
FiniHn-First-Out buffer. The 16 address lines can address up
to; 64K deep SRAM. Control signals include the Iii for SRAM,
handshake signals for REAOIWRITE porlS, and strokes for
external data latching.

BF1.

3

BF2.

4

iiii

s

WRDY

•

RRDY

1

WCLK

•

.RCLK

•

FULL

13

EM.PTY· ..

The '5419 allows single port S.RAM to resolve read and write
request conflicts accordingto a Simple priority rule. If priority is
selected on either read orwrite port, the operation requested is
serviced with no delay. For no priority mode, read and write
operations are alternjlted.:
.

1/2 FULL

15

ALMOST ..
WREQ.17

Block Diagram
BUFFER SIZE
SELECT
CLK

-:--

WRITE REQUE$T

---I

WRITE READY
WRITE .ENABLE

READ

'5419:':'

fl.:oAAM

CONTROLLER

mo

~I;.QIlES':

READ READY

READ ENABLE - -.....
PRIORITY .,..,...+2.......~

...-~-.;.;-... EMPTY
...-_ _-;-.... FULL

'---r---r-:-'

I

. STATUS

HAl,F . ..... FLAGS
Ai;MOST
0 " ·

MonolithiCW Memories

SiBER (Single Burst Error Recovery Ie)
SN74S480

I I I I I//IIIIIIIIIIIIIIIIIIIIIIII////////////IIADVANCE INFORMATION
Features/Benefits

Typical Applications

• Bipolar S TTL technology allows fast data rate

• Disk drives

• Selectable CRC or ECC polynomials

• Data communication

• Standard 16-bit CRC-CCITT polynomial detects errors

• High speed serial data transmission

• Computer-generated 32-bit ECC polynomial exceeds the
performance of Fire code polynomials

Description

• Double-burst error detection and single-burst error
correction with ECC polynomial
• Programmable correction span of five, eight, or eleven bits
• Hardware or software correction modes
• Hardware correction provides a user friendly correction cycle
which can be implemented without having to learn how to
decode the syndrome.
• Separate receiver and transmitter ports
• HOLD pin for idle operation
• Maximum of 1024 bytes of data
• Selective inversion of checkbits and initialization of registers
10 a high state improves reliability
• 24-pin package .

SiBi::R (Single Burst Error Recovery) is a LSI error-detectionand-correction circuit which may be used to insure data
integrity between two serial ports. SiBER implements the
standard 16-bit GRG-GCITT polynomial (x 16 + x 12 + x5 + 1),
and also one of Neal Glover's computer generated polynomials
(x32 + x 28 + x 26 + x 19 + x17 + x 10 + x6 + x 2 + 1).
The 16-bit CRC-CCITT polynomial can be used only to
generate the checkbits, while the 32-bit EGG polynomial can be
used to both generate and correct. The 32-bit EGG polynomial
can be used to correct 5-,8-, or ll-bit bursts of erroneous data,
or to detect double-burst errors in a data stream of up to 1024
bytes of data.
The SiBER has four m,odes of operation: transmit, receive,
correct and. search, which enables correction by software,
software/hardware, or hardware .. In addition, a HOLD pin is
provided for "idle" operation.

SHIFT
ERROR FLAG
REGISTERS / - - - - - - - - - - - - - ERROR PATTERN FLAG
A!'/D lOGIC
END OF CORRECTION
FLAG
SERIAL INPUT
TRANSMITTER DATA
TRANSMITTER---++....---+-+--------=~~---~~I RECEIVER
OUTPUT
CHECK BITS
MUX

DATA
OUT

SE:~~~II~:~T _ _-+-+_____-t-P_AS_S_R_E_C_E-'-IV~ER_DA_:l:_A.1
ERROR SYNDROME

STATUS
FLAGS

SERIAL OUTPUT
RECEIVER

DATA
IN

~~~~~6~~~----+-----,

I

SERIAL OUTPUT
TRANSMITTER

INITIALIZE
HOLD,
CRC/ECC
CONTROL
SIGNALS

RECEIVEITRANSMIT
TGS, RGS, CGS 3
CORRECTION 2
SPAN D, 1
ClKIN

1-----------~--------.ClKOUT

.
TWX: 910-338-2376
2175 Mission CpllegeEllvcl: ~anla CJl!~",CA 95054-1592 Tel: (408) 970'9700 TWX: 910-338-2374

15-6

Monollthlom
Memories

i
I

Monolithic

m

Programmable Array Logic
Very High Speed
PAL®20B Series

Memories

/ / / / / / / / / / / / / /////////////////////////////IIADVANCE INFORMATION
Features/ Benefits

Ordering Information

• 15 ns maximum propagation delay
• Fmax

= 40 MHz

.12 ns maximum from clock input to data output
• Advanced shallow-junction technology
• Instant prototyping and board layout
• Zero NRE charge
• Reduces chip count by greater than four to one

PART
NUMBER

PKG

PAL16L8B

N,J,L,NL

PAL 16R8B

N,J,L,NL

Octal 16 input Registered And-Or

PAL 16R6B

N,J,L,NL

Hex 16 input Registered And-Or

PAL 16R4B

N,J,L,NL

Quad 16 input Registered And-Or

GATE ARRAY DESCRIPTION

Octal 16 input And-Or

• Programmable replacement for TTL logic
• Programmed on standard PAL programmer
• Programmable three-state outputs
• Security fuse prevents duplication by competitors

The PAL transfer function is the familiar sum of products. The
PAL is a programmable AND array driving a fixed OR array. In
addition, the PAL provides these options:
• Variable input/output pin ratio
• Programmable three-state outputs
• Registers with feedback

Description

Unused inputs are tied directly to VCC or GND. Product terms
with all fuses blown assume the logical high state, and product
terms connected to both true and complement of any single
input assume the logical low state. Registers consist of D-type
flip-flops which are loaded on the low-to-high transition of the
clock. PAL Logic Diagrams are shown with all fuses blown,
enabling the designer to use the diagrams as coding sheets.

The PAL20B series, employing Monolithic Memories' advanced
shallow-junction technology is an enhanced version of the
PAL20A series, With 15 ns maximum propagation delay time, the
PAL20B series provides the highest speed performance in the
existing PAL family, The advanced shallow-junction technology
offers an impressive speed improvement for applications where
speed is critical. The PAL20B series contains the PAL 16L8B,
16R8B, 16R6B and 16R4B which are pin-compatible with the
PAL20 and 20A series,

The entire PAL family is programmed on conventional PAL
programmers with appropriate personality and socket adapter
modules. Once the PAL is programmed and verified, two additional fuses may be blown to defeat verification. This feature gives
the user a proprietary circuit which is very difficult to copy.

General Description

Typical Application

The PAL20B series utilizes Monolithic Memories' advanced
shallow-junction bipolar process and the bipolar fusible-link
technology to provide user-programmable logic for replacement
conventional SSI/MSI gates'and flip-flops at reduced chip count.

• DMA control
• State machine control
• High-speed video control
• Standard logic replacement

The family lets the systems engineer "design his or her own
chip" by blowing fusible links to configure AND and OR gates to
perform his or her desired logic function. Complex interconnectionswhich previously required time-consuming layout are thus
"lifted" from the PC board and are placed on silicon where they
can be easily mOdified during prototype check-out or production.

Preliminary Data
= 15 ns max
= 12 ns max
Maximum frequency = 40 MHz min

• Propagation delay

• Clock to output delay
•

• ICC = 180 mA max

PAL"; is a registered trademark of Monolithic Memories

TWX:. 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

WlonolilhiCm
Wlemorles
15-7

Very High Speed PAL20B Series

Pin Configuration

15-8

PAL16L8B

PAL16R8B

PAL16R6B

PAL16R4B

Monolithic

W Memories

Monolithic

m

Memories

Programmable Array Logic Family
PAL® Series 20 AP With
Programmable Output Polarity

/ / / / / / / / / / / / / /////////////////////////////IIADVANCE INFORMATION
Features/ Benefits
• 25 ns maximum propagation delay
I

•

Programmable output polarity

Product Description
PART
NUMBER

PKG

GATE ARRAY
DESCRIPTION

• Programmable replacement for TTL logic

PAL10P8A

J, N, L, NL

Octal 10-input And-Or

• Expedites prototyping and board layout

PAL12P6A

J, N, L, NL

Hex l2-input And-Or

PAL l4P4A

J, N, L, NL

Quad 14-input And-Or

PAL16P2A

J, N, L, NL

Dual l6-input And-Or

PAL l6C1A

J, N, L, NL

l6-input And-Or

• Programmed on standard PAL programmers
• Last fuse prevents duplication

Functional Description
The PAL series 20 AP represents an enhancement of existing
PAL architectures which provides greater design flexibility and
higher speed. The PAL series 20 AP comes with programmable
output polarity and is pin-for-pin compatible with the standard
PAL 20 series.

The PAL transfer function is the familiar sum 6f products. The
PAL has a single array of fusible links which is a programmable
AND array driving a fixed OR array.

The programmable output polarity feature allows the user to
program individual outputs either active high or active low. This
feature eliminates any possible need for inversion of signals
outside the device.

Unused inputs are tied directly to VCC or GND. Product terms
with all fuses blown assume the logical high state, and product
terms connected to both true and complement of any single
input assume the logical low state.

General Description
The PAL series utilizes Monolithic Memories' advanced. selfaligned washed-emitter high-speed bipolar process and the
bipolar fusible-link technology to provide user-programmable
logic for replacing conventional SSI/MSI gates and flip-flops at
reduced chip count.
The family lets the system engineer "design his own Chip" by
blowing fusible links to configure AND and OR gates to perform
the desired logic function. Complex interconnections which
previously required time-consuming layout are thus "lifted" from
the PC board and are placed on silicon where they can be easily
modified during prototype check-out or production.

The entire PAL family is programmed on inexpensive conventional PAL programmers with appropriate personality and socket
adapter modules. Once the PAL is programmed and verified two
additional fuses may be blown to defeat verification. This feature
gives the user a proprietary circuit which is very difficultto copy.

Preliminary Data
• T PD (max)

~

25 ns propagation delay

• ICC (max) ~ 90 mA

PAL® is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

.onolithicm
.emories
15-9

PAL® Series 20 AP with Programmable Output Polarity

PAL10P8A

PAL12P6A

PAL16P2A

15-10

PAL14P4A

PAL16C1A

Monolithic WMemories

Monolithic

m

Memories

Programmable Array Logic Family
PAL® Series 24 AP With
Programmable Output Polarity

I I I I I I I I I I I I I IIIIIIIIIII/////////////////IIIADVANCE INFORMATION
Features/ Benefits
• 25 ns maximum propagation delay
• Programmable output polarity

Product Description
PART
NUMBER

PKG

GATE ARRAY
DESCRIPTION

• Programmable replacement for TTL logic

PAL 12P10A JS, NS, (L), (NL)

• Expedites prototyping and board layout

PAL14PSA

JS, NS, (L), (NL) Octal 14-input And-Or

PAL 16P6A

JS, NS, (L), (NL) Hex 16-input And-Or

PAL1SP4A

JS, NS, (L), (NL)

Quad 1S-input And-Or

PAL20P2A

JS, NS, (Ll. (NL)

Dual 20-input And-Or

PAL20C1A

JS, NS, (L), (NL) 20-input And-Or

• Programmed on sta.ndard PAL programmers
• Last fuse prevents duplication

Functional Description
The PAL series 24 AP represents an enhancement of existing
PAL architectures which provides greater design flexibility and
higher speed. The PAL series 24 AP comes with programmable
output polarity and is pin-for-pin compatible with the standard
PAL 24 series.
The programmable output polarity feature allows the user to
program individual outputs either active high or active low. This
feature eliminates any possible need for inversion of signals
outside the device.

i

General Description
The PAL series utilizes Monolithic Memories' advanced selfaligned washed-emitter high-speed bipolar process and the
bipolar fusible-link technology to provide user-programmable
logiC for replacing conventional SSI/MSI gates and flip-flops at
reduced chip count.
The family lets the system engineer "design his own chip" by
blowing fusible links to configure AND and OR gates to perform
the desired logic function. Complex interconnections which
previously required time-consuming layout are thus "lifted" from
the PC board and are placed on silicon where they can be easily
modified during prototype check-out or production.

Deca 12-input And-Or

NOTE: Land NL options are 28..;pin chip carriers.

The PAL transfer function is the familiar sum of products. The
PAL has a single array of fusible links which is a programmable
AND array driving a fixed OR array.
Unused inputs are tied directly to VCC or GND. Product terms
with all fuses blown assume the logical high state, and product
terms connected to both true and complement of any single
input assume the logical low state.
The entire PAL family is programmed on inexpensive conventional PAL programmers with appropriate personality and socket
adapter modules. Once the PAL is programmed and verified two
additional fuses may be blown to defeat verification. This feature
gives the user a proprietary circuit which is verydifficultlo copy.

Preliminary Data
• T PD (max) = 25 ns propagation delay
• ICC (max) = 100 mA

PAL® is a registered trademark of Monolithic Memories.

TWX: 910-338-2376
2175. Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

Monolithic I! lin
Memories InJnJ.I
15-11

PAL®Series 24 AP with Programmable Output Polarity

15·12

PAL12P10A

PAL14P8A

PAL16P6A

PAL18P4A

PAL20P2A

PAL20C1A

MonollthloW.emorles

l!1!'n

Monolithic uun.u Memories

I

I

~

OHPAL20P8

II I I I I I I I II/IIII/IIIIIII//////ii////i///ii//I/ADVANCE INFORMATION
1------------------------------Features/ Benefits

Programmable Polarity

• 20 inputs; 12 external, 8 feedback

Output polarity is defined by comparison of the pin list and the
equations. If the log ic sense of a specific output is different from
the logic sense of that output as defined by its equation, the
output is inverted. If the logic sense of a specific output is the
same as the logic sense of that output as defined by its equation,
the output is active high polarity.

• 6 ns max. propagation delay
• 32 product terms
• Product term sharing
• Programmable output polarity
• 10KH ECl compatible
• 24-pin SKINNYOIP®
• SOil termination drive

• Input pull-down resistors

Preliminary Data
• 6 ns maximum propagation delay
• -230 mA maximum lEE current

• Voltage compensated
• Compatible with TTL programmers

Areas of Application
• High-performance communication equipment
• High-speed test instrumentation

I

Description
This ECl PAl® device has a 20P8 architecture, is ECl 10KH
compatible, and has a simple programming algorithm. The
10HPAl20P8 is a 20 c input, 8-output PAL part. Outputs have a
polarity fuse and can drive a 50 Il termination to -2.0 V.

'I

• Mainframes or Super-minis
• Computer-aided graphics

Pin Configuration

Product term sharing allows the choice of one oftwo outputs for
the given product term. Product terms are grouped in multiples
of eight per output pair allowing up to eight product terms to be
associated with any output term.

10HPAl20P8

, Features
The following description explains some of the features of the
10HPAl20P8. Features to be programmed into the PAL device
are completely specified by the Boolean equations and automatically configured by the PAL assembler (PALASM),M.

Product Term Sharing
The basic configuration is eight product terms shared between
two output cells. For each output a product term can be used by
either output, but since the product term sharing is exclusive, a
product term can be used by only one output, not both. If the
same product term is needed by the same output pair, then two
product terms are generated, one for each output.

*

Patent pending,

PAL'" and SKINNYDIP'R are registered trademarks of Monolithic Memories.
PALASM'" is a trademark of Monolithic Memories

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408)970-9700 TWX: 910-338-2374

lIIonolithior!mn
lIIemories InJlW

15-13

10HPAL20P8
Logic Diagram
10HPAL20PS

11--"

VCC3

0123

4567

891011

12131415

15171819

20212223

24252627

28293031

32333435

1

...

36373839

~

.....
~~

0

,
I

;:-r-

3

4
5

,

..r

7

I-

L.J

~

....

~

10

,,
10

11

;::

"
13

"15

II

~?

""1...)'""-

...
...
'--I.
--I

r-

1!--

VCC1

1

.f~
"tu
....

13

"
"
17

19

~

10

11

"
23

14

~

...

VCC2

--".

"
27

~

""

.fL

...

f~

...

....

30
31

23

12----.VEE

15·14

17

I

I!-- 18

.-...

24
15

2

f~
....

~

15

I

f::'

16

Monolithic

W Memories

19

20

Monolithic

m

Memories

ZHALTM 20 CMOS
Hard Array Logic Devices

II I I II I I I I I I I I IIIIII/IIII///////////////////IIADVANCE INFORMATION
Featuresl Benefits··

Area$ of Application

• Zero standby power

• Portable computers

• High speed, CMOS technology

• Battery-operated instrumentation

• Low cost alternlltive for Small and Medium 20 Pin PAL® series

• Low-power industrial or military equipment

• Fully CMOS/TTL level compatible

• Standard CMOSITTLIogic replacement

Description

Preliminary Data

The Medium 20 Pin ZHALtepresents a new concept in HAL
technology which offers the benefits o/virtually zero standby
power consumption and high speed operation. These benefits
are achieved as a result of Monolithic Memories' advanced 3
micron CMOS technology.
The ZHAL archite>cture is optimized for low cost and ease of
implementation in CMOS. It also provides a high degree of
flexibility whi.ch allows it to address 80-85% of all Medium 20Pin
PAL applications and allthe appl ications of the Small 20 Pin PAL
series.

ICC (Standby) = 100ILA (Max)
ICC@(FMAX) =90mA
VOL =.4V
VO H = 3.5V (HCT COMPATIBLE)
VOH = 2.4V (TTL)
10L = 8mA
10H = -6mA (HCT COMPATIBLE)

Generlll Description

10H = -4mA (TTL)

To design a ZHAL, the user first programs and debugs a pAL
using PALASMand the "PAL DESIGN.SPECIFICATION" standardformat. :rhis speCification is submitted. to Monolithic
MemorieS where it is computer proceissed and assigned a bit
pattern number, e.g. P01234.
Monolithic Memories will provide a·pAL sample for customer
qualification. The user then submits a purchaseorder for a ZHAL
of the specified bit pattlirn number, e.g. ZHAL16L8 P01234.

Propagation delay = 35ns max
Setup time = 30ns min
Clock to out time = 25ns max
FMAX=18MHz

MMI's New Zero Power Hard Array Logic (ZHAL) is Pin for Pin
Compatible and May Replace Most Patterns of The Following PALs:
10H8

12li6

14H4

16H2

.1

I

,I

I

~L!" i.S
HAL·~'

1

a registered trademark of Monolithi!; Mernpries
IS a registered trademark of Monolithic Memories

PALASMT~ is a trqdemark of Monolithic Memo~i~s
ZHAL'" is a trademark of Monolithic Memories

TWX: . 91'04338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408)970-9700 TWX: 910-338-2374

WlO_'ith/em··
Wle",orles
.
15-15

ZHALTM 20 CMOS Hard Array Logic Devices

14L4

.16L2

16L8

16PB

16RPB

16RP6 .

NotE: p~ conla9.t YPW;ioCaI MMI field application engineer for aSsistance in evaluating whether this ZHALdevice can be used:

16RP4

Package Drawings

.

"

-."

.1 [€I
"17

Table of Contents
PACKAGE DRAWINGS
Contents for Section 16 ............................. 16-2
Side Brazed - Flat Pack
Leads/Finish .;..................................... 16-3
Package Boc!y ...... ;; ............ : ........... ;.... 16-3
Aluminum Bonding Wire ..........•.. <; ••••••••••• , •• 16-3
, Side Brazed ..... : .•..... ; ..... :; .•..... ': ......... 16-4
48D .............. ; .............. ; ..• ;.<: •••<• • • • • • ;.16-5
Flat Pack .. ; ...... ; .. '......................... ; .... 16-6
16F-4/5 .: .................... ; .................... 16-7
16-7
18F-2/3 ................... ; ...
20F-3 ... ; ....... ;<; . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . 16-8
24F-3 ............................. ; ............... 16-8
24F-4/6 ...................... ;. . ... . . . . . . . . . . ... .. 16-9
< ••••••••••••

;

•••••••

Cerdip
Caps <;tnd Bases ................... , ...............
Cavity/Die Attach ............. , ...............•..•
Leadframe Material/Lead Finish <. • • • • • • •• • •• • • • •• • • ••
Cerdip ............ ,< . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14J •............... , ............. ,< •••••••••••••••
16J ..............................................
18J ..............................................
20J ..............................................
24JS , .............. ;< •••••••••••••••••••••••••••••
24J ..............................................
40J ............ ,., ..•............................

16-10
16-10
16-10
16-10
16-11
16-11
16-12
16-12
16-13
16-13
16-14

Leadless Chip Carriers
Leadless Chip Carrier ..............................
20L ....................................
28L ..............................................
44L ..............................................
52L .'............•.........•......................
84L-1 ............................ ; .. : ............
84L-2 ............................................
84L-2 Socket ..... " . . . . . .. . . . . . .• . . . .. . . . . . . . . ...

16-15
16-16
16-16
16-17
16-17
16-18
16-19
16-20

<. . . . . . . . . .

16·2

Monolithic

Molded Dips - Chip Carriers
Leadframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Gold Bonding Wire ................................
Package Body ....................................
Lead Finish .......................................
Die Attach Pad/Bonding ...........................
Molded Dip .......................................
16N ..............................................
18N ..............................................
20N ..............................................
24NS ............................................
24N ..............................................
40N ..............................................
48N ..............................................
Molded Chip Carrier ...............................
20NL ............................................
28NL ............................................
44NL ............................................

16-21
16-21
16-21
16-21
16-21
16-22
16-23
16-23
16-24
16-24
16-25
16-25
16-26
16-27
16-28
16-29
16-30

Pin Grid Array
Pin Grid Array .................................... 16-31
88P-1 ............................................ 16-32
88P-2 ............................................ 16-33
Top Brazed Ceramic
Top Brazed ....................................... 16-34
24T .............................................. 16-35
Cerpack
Cerpack ......................................... .
16W-3 .......................................... .
18W-1 .......................................... .
20W-2
24W-2

16-36
16-37
16-37
16-38
16-38

Thermal Measurement
Power Dissipation Determination ................... 16-39
Thermal Impedance Measurement Procedure ........ 16-39
Thermal Resistance Curves ........................ 16-41

mID Memories

Package Drawings
Leads/Finish

Package Body

Monolithic Memories Incorporated proyides high strength
nickel iron steel (Alloy 42) leads on all fiat pack and side braze
packaged deyices. In addition, the user is offered a choice of
two finishes, standard gold plate and solder dip oyer gold plate.

Monolithic Memories Incorporated utilizes high reliability
multilayer ceramics in the body of all side brazed packages.
The body ceramic is comprised of a mixture of 90% alumina
(AL20al with other ceramics such as silica (Si02), MgO and GaO.

"Alloy 42
Nickel
Manganese
Cobalt
Silicon
Chromium
Aluminum
Carbon
Phosphorous
Sulfur
Iron

Composition
(Nominal)

42.0%
.50%
.19%
.07%
.06"10
.024%
.012%
.006%
.001%
Balance

"Physical Properties

*

Melting Point

1,427°C

Curie Temperature

380°C

Density (g/cc)

8.11

Coefficient of Thermal Expansion

5.4X 10-6

cm/cmOC(21 - 343°C)

Thermal ConductiYity

.03

cal-cm/sq cm-secoC

I

i
I

71

Modulus of Elasticity (psi)

21.1 x 106

Tensile Strength (ksi)

97

Elongation

10%

Vickers Hardness

208

Lids
Monolithic Memories Incorporated utilizes high durability
KOVAR lids on all Flatpack, chip carriers and sidebrazed
packages.

29.0%
17.0%

Manganese

.20%

Carbon

.02% Maximum

Lid Finish -

17 to 21 grams

Elongation

1%to 4%

Resistance
(ohmslinch)

.94 to 1.1

Weight
(mg/foot)

.61 - .68

• Secon Metals Corp.• Data Sheet. 1975

balance
1,450°C

Curie Temperature

435°C

Density (glcc)

8.36

Thermal ConductiYity
(cal-cmlsq cm-secOC)

.05

Electrical ResistiYity
(micro ohm-cm at 20°C)

49

Aluminum
Silicon
Other

Tensile
Strength

Gold plating

Melting Point

10 kv/mm
10 14 ohm· cm (20°C)
10 9 ohm . cm (300°C)

Monolithic Memories Incorporated uses 1.25 mil aluminum
wire to connect I.C. chips to all hermetic packages. The same
high reliability wire is used in side brazed packages, fiat packs,
cerpacks, chip carriers, cerdip packages, and pin grid arrays.

.30%

Silicon
Iron

.20 Cai/gOC

Aluminum Bonding Wire

"Composition
Nickel

-0%
1,300
40,000 gSi
39X10' psi
6.5 X 10-6 (40°C-OO°C)
.04 Cal/cm . Sec· °C

Kyocera International Data Sheet

Composition

Cobalt

3.6 grams/cc

"Physical Properties

Electrical ResistiYity
(micro ohm-cm at 20"C)

• Stamping Technology Data Sheet
GarTech Data Sheet

I

"Physical Properties (nominal)
Bulk Density
Water Absorption
Vickers Hardness
Flexural Strength
Young's Modulus
Coefficient of Linear Expansion
Thermal ConductiYity
Specific Heat
Dielectric Strength
Volume ResistiYity
Volume ResistiYity

'CarTech Data Sheet

II/IonoHtNo WIII.mories .

99%
.85% to 1.15%
.009% maximum

Package Drawings
Package Drawing

Side Brazed Package

•

16-4

PACKAGE BODY

LID

LEAD MATERIAL

Alumina
(Standard Dark)

Gold Plated Kovar With
Nickel Underplating

Alloy 42

BONDING WIRE

CAVITY/SEAL RING

LEAD FINISHES

1.25 Mil Aluminum

Gold Over Nickel
Over Tungsten

Gold Plate (Standard)
Solder Dip Over Gold Plate

MonoIIthlD IHllllllenrories

Package Drawings
Package Drawing
48D Side Brazed Ceramic Dip

(1/2"x27/16")

.=

48

t
~

PIN#1
IDENTIFY

.495 +.005
12.573 ± .127

sa

IC:I;

c::I

-

D

25

24

1_

.590+.010

14.9B6±.2S4

-I

IL.· I1-.011

±"002~

.279±.0511

.152 + .015
3.861 ± .381

.605 + .015 _
15.367 ± .381

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

16-5

Package Drawings
Package Drawing

Flat Pack

LEAD~===l'::SEAL RING

16·6

PACKAGE BODY

LID

LEAD MATERIAL

Alumina

Gold Plated Kovar With
Nickel Underplating

Alloy 42

BONDING WIRE

CAVITY/SEAL RING

LEAD FINISHES

1.25 Mil Aluminum

Gold Over Nickel
Over Tungsten

Gold Plate (Standard)
Solder Dip Over Gold Plate

Monollthio

mMemo""'.

Package Drawings
Package Drawings
16F-4/5 Flat Pack
(1/4"x3/S")

PIN NO. 1
IDENTIFY
.011 ±.002

~L

r
~D6~.005BSC
t

.432+.051~.
.017+.002

.127

*
.045 MAX--"J
1.143

8

I

305 015
- ; . 747~·.381

~

9

10.058["381

L.oos

-II

1:

960

1_

,_

, r

~------~4~~==~~~======~~F=~[

.127±.025

T

MIN

.127

::::~:~
~ ±.2~ '~-----:--Ir--

.005 ± .001

.396 + .015

'II

180

.078 ±±.178
.007
1.981

L.025 ± .015
.635±.381

030

~572MIN~ r-:762 MIN

1SF-213 Flat Pack
(3/S"x3/S")
.017 ±.002
.432 ± .051

-I1-.Ol 1±.OO3

PIN NO.1
IDENTIFY

J-.

'" II

1~BSC~

D18~

r

,

.L

9

.360 + .010
9.144 +.254

10

I ..305 ± .015 I

.005 MIN

.127

.004 MIN

.102

j47.747 ±.381~

l

rtt

~.T
.127±.025

.279 ±.O76

J
.275 + .010
6.985 ±.254

.390MAX~

~

-I"

::.010
9 . 1 4 4 ± . 2 5 4 S ! 1 1•905 ±.203

•
1-.·

•

\-1
.11

.030 MIN
I- .762

J

~
.635 ±.381

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAl(. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLlME7ERS

ALL TOLERANCES ARE ± .007 INCHES

liIonolllhla

W liIemorles

16·7

Package Drawings
Package Drawings
20F·3 Flat Pack
(1/4"x3/B")

~BSC
1.270

_11_

PIN NO.1
IDENTIFY

.017 ±.002
.432±.051L

.011 ± .003
.279 ± .076

0
20

~

t

. 1011

t

.M!:MAX~
1.143

1

.398 +.010
1.0.109 +.254

!

'

Ir- 7.747
.305 ± .015 ....1
± .381

1:·:'
A :-

.075±.008

1.905 ±.203

~--------~4~~~~~~~~I========~=-L
180
~
I ~ 030

.005 ± .001 ~... .
.127 ± .025

24F·3 Flat Pack
(1/4"x3/B")

4.572

'---- H>-ll

~.~96

2.89

MAX

1-1-.~100 SSC
540

---

...-.036
.914

.200

~~~

.158 + .016'

t

=t'1~+'020

3.683 ±.508

7.899
.293 + .012

••

-A\

~_

.279 ± .051

I~

__

~..

.375 ± .025 '-»
9.525 ±.635

~

20 _130
REF. (2)

24J Ceramic DIP

(1/2"x1 1/4")

r-'=:W::L.C:J....l:::J.....J:::J..JD-r:::L='-=--=-=-r::::JL...

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

~~I.457± .102

I

I

Notes:
1. Specified body dimensions allow for differences between MSI and LSI packages.
2. Lead material tolerances are for tin plate finish only. Solder dip finish adds
2-10 mils thickness to all lead tip dimensions.

MonolithioW Memories

16·13

Package Drawings
Package Drawings
40.1 Ceramic DIP
(9/16"x21/16")

_.020 MIN
.508

.336:': .025
8.534:': .635
2.058 + .025'

"

1

j~~:M:.,:l1 ~

~MAX

I

5.715

.381

,~ ..fL9- =~

4.064

~ MAX
2.489

....

I

___ .036
.914

~~

.

.J.Q!!.. BSC
2.540

I
-

.145±.020
3.683 ± .508

.525 + .015'
13.335 ± .381 -

I

Ifl I ·1\
T

.161 + .020'

4.089 ± .509

II

2° _110
REF. (2) - -

.011 ± .002_ _
.279 ± .051

_

.658 + .030 _
16.713

± .762

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAlt IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

Notes:
1. Specified body dimensions allow for differences between MSI and
LSI packages.
2. Lead material tolerances are for tin plate finish only. Solder dip finish adds
2c 10 mils thickness to all lead tip dimensions.

16·14

MonolithicW Memories

1\

~

Package Drawings

Leadless Chip Carrier
PACKAGE BODY

TERMINALS

PACKAGE BODY

LID

Alumina
(Standard Dark)

Gold Plated Kovar With
Nickel Underplating

BONDING WIRE

CAVITY/SEAL RING

1.25 Mil Aluminum

Gold Over Nicker
Over Tungsten

TERMINALS

Gold Plating Over Tungsten

Package Drawings
Package Drawings
20L Leadless Chip Carrier
(.350"x.350")

.025 ± .003 TYP (20).1

.635 ± .076

I

.020 x 45'

[

.508

.~!~ MIN~-U-"S-U-"S-""-""--'----'--'-08-51r±

-.----=.::.:....- ~'\.

)

(AI

I

.008

2.159±.203

1 .210

5.080

BSC

(B)

.313 + .016
7.450 ± .406

6.350
REF

I(

~

!

!

~

·tlR~BSC

••••
I~

,.~~ll,~~
.075

.100

1.270

.050 + .005 TYP

uro,.>v

BSC

BOTTOM VIEW

TOP VIEW

28L Leadless Chip Carrier
(.450"x.450")
.020 x 45' TYP
[.506

1

t

(A)
.406 + .010
10.312±.254 (B)
.390 + .003
9.906± .076

1

.350 REF

r·

1 ----.,

.025 ± .003
635 ±.076

8.890--1.--

1 1
~

_ _ TYP

-j~~6X45'

_ _ .450+.006
SQ_
11.430 +
_ .203

TYP(3)

TOP VIEW
.060 ± .006

[~

BOTTOM VIEW
.072 ± .008

~i

LI Iii iii iii I

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALtDIMENSIONS MIN.-MAX. IN MILLIMETERS

·ALL TOLERANCES ARE ± .007 INCHES

Notes:
1. Solder fillets on lid edges not shown.

16-16

MonO"'hlC:.W Memories

I

i
Package Drawings
Package Drawings

TVP(44)

44L Leadless Chip Carrier

(.65U'x.650")

~

"

1

.525 + .033
13.335 ±.838

.501 +.032
12.725 ± .813

sa

I

.040 x45° (3)--.

1.016

i

l

~_.m,~J
16.510

I

.

05O ·BSC
1.270

__ .050 ± .005
1.270 ± .127

±.254

BOTTOM VIEW

TOP VIEW
~±~

~±~

[f.524±.15i
['-829
I Iii iii iii iii I I~

±.203

52LLeadiess Chip Carrier
(.750"x.750")
.020, X450 TVP

[-506

t
.750 +.011
19.05o ±.279

sa

1.016 TV P(3)

r=

--.~~j
13.970 ± .076

_

.580 + .006
14.732 ± .152

~

.010 R
.254 TYP (52)

t

F=

L~
~x 45.1

.015 MIN
.381

-'l

sa

1:::0 REF'

.050 + .005
1.270 ± .127

.-J.~
.075
1.905
REF

•
BOTTOM VIEW
UNLESS OTliERWlSE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

Notes:
1. Solder fillets on lid edges not shown.

16·17

Package Drawings
Package Drawings
84L-1 Leadless Chip Carrier (Cavity Up)
(1.150"x1.150")

.085 ± .008

r-21~y±~.~~3~~nn~~~~~rv~~
t

.~
.008 R
.~3

1

TYP(84)

1.150+.015
29.2 10 ± .381

so

.L
~ x 45 0
1.016
TYP(3)

c~~

J

cl~

--

1;~~8+±0~;6 sa __

--

.734 + .008
sa18.644 ± .203

"-':'-"-''-''-''-''''-''-'''-''-''-':'-''-.....-"-'......''-'''-''"':'J

~REF-1.905

--

I~..- - - - ;5~:! REF-----i..1
BOTTOM VIEW

TOP VIEW

r
t

.080 ± .008

.092 + .009
2.337 ± .229

2.ii32±.2031

Iii iii iii iii iii iii iii i ill

t

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

Notes:
1. Solder fillets on lid edges not shown.

16·18

l~BSC
1.270

.050 ± .005
1.27o± .127

Monollthicmml! Memories

Package Drawings
Package Drawings
84L-2 Leadless Ch'IP Carrier (Cavity Down)
(1.380"x1.380")

PIN # 1
IDENTIFY

PIN#l
IDENTIFY

D

-1

1

1.380 ± .010
35.052±.254

xr
1.050

Uml~

~~

.050

[1.27O
- ' -t

BSC

t
.500
12. 700 BSC

+

.............

--1-1(84) _J
____ .030 ± .005

.762 ± .127

I

. . .670 + .003
17.018 ±.076 SQ ..-

r

HEAT SINK
BASE

I

i

t

±['=43~2~~=T====b~= +TC·6~

.110 ± .017

__2._794

I~t_·_!

I

l.060 ± .006
1.524 ± .152

_ _ 1.150 + .010
29.210 ± .254 SQ -

HEAT SINK TOP

.063 ± .007

L

±.178
.245 ± .020

'j'~

BonOMVIEW

-t

..

-

-

~ ~:: ';;~~?-~ir"·';.}~
SOCKET
(SEE NOTE 4)

U~i~sgl~~~~~~~E SPECIFIED:
ALL DIMENSIONS =IN.-MAlC. IN INCHES
ALL TOLERANCES ~~.-MAX. IN MILLIMETERS
E ± .007 INCHES

Notes:
1. Solder fillets on lid ed ges not shown.

Monolith/oW Memor.es
.•

16-19

Package Drawings
84L-2 Socket

•

D

o

TOPYIEW

PIN MOUNT

~DIA
1.~

PIN MOUNT

~-------,-------------------.~ .~
.600

.008
.220

_~.050
1.270

--~=f=-=!=~

~___ ~1~.~~±~.~~~~~

.1~

3.7110

LOCATION PIN (OPTIONAL)

+~

.063-.004

1.BiiOTciiiO
SURFACE MOUNT

-.100

.~

.079±.020

.600

2.~±.6OO

SURFACE MOUNT

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.·MAlI. IN INCHES
ALL DIMENSIONS MIN.·MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

Socket SpecIfications (all values from Yamalchi/Nepenthe data sheet):

1.
2.
3.
4.
5.
6.

Insulation Resistance ..••.•....•..........•..•....•....•.•..•.•...•. ;................ 1,000 M n minimum at 500 V DC
Dielectric Withstanding Voltage ............................... " • .... • .. .. .. . .. .. ... 700 V AC RMS for one (1) minute
Contact Resistance ....... .. . .... .. .. .. .. .. .. . .. • .. • . .. .. . ..... .• • ... • .. .. .. • • .. ... 20 M n maximum at 10 mA, 20 mV
Rated Current Per Contact. . . . . • . • . • • • . . . . . • • • • . . • . • . . . . . . • . . . • . . . . • • . . • • . . . . . • . • . . • • • . . . • . . . . . . . . • . .• 1 A maximum
Operating Temperature ...•.....•......•...•.•.........•......•..........•..•...•....•.....•......... -55 to +100·C
Contact Force ................................................ ..... .... . . .. .. . . .. .. .. .. •. 85 grams min for each contact

16·20

"""""hlo W I/IIemories

Package Drawings
Molded Packages

Leadframe

Monolithic Memories Incorporated utilizes the latest highstrength, high-conductivity copper leadframes for assembling
devices in molded plastic packages. Depending on availability,
all copper leadframes will be stamped from either ALLOY 195 or
TAMAC5.
Listed below are the physical parameters of these two equivalent
alloys:

'I

Nominal
Composition
Copper
Iron
Tin
Phosphorous'
Cobalt
Zinc
Aluminum
Lead

(1) Alloy 195

(2) Taniac 5

97.0%
1.5%
.6%
.1%
.8%
.2% max.
.02% max.
.02% max.

98.0%
.75%
1.25%
.03%

Melting Point

1,090°C

1,075° C

Density (G/cc)

8.92

8.8

Coefficient of Thermal
Expansion
(20-3OO"C) cm/cm/oC

1.69 X 10-5

1.67 x 10-5

Thermal Conductivity
at 20°C cal" cmlsq cm sec_oC

.47

.33

Electrical
Resistivity
(microhm - cm~ 20·0)

3.94

4.93

Modulus of
Elasticity (psi)

1.73 x 107

1.71 x 107

Tensile Strength
(ksi)

75/85

69m

Elongation

2 -5%

4-7%

Vickers Hardness

157 - 175

150-

.00100
.00125
.00130

3 -6%

8-12
10 - 14
14 - 18

3 -6%
3 -6%

All leadframes are sufficiently strong so that leads in the
,finished package will survive two goo bends (bend is complete
cycle O· to 90° to 0°) without fracturing.
(1) OLIN Brass data sheet, 1971
(2) TAMAGAWA data sheet, 1980

Gold Bonding Wire
Monolithic Memories chips are connected to package leads
using 1.0'mil, 1.25 mil, or 1.30 gold wire, depending on
assembly and device requirements. In some cases, the
impuritiesofthe gold wire will vary to accommodate particular
devices. Listed below are typical parameters.
Composition
99.9990
.0001

.0001
.00001.
.0001
.0001
.0001
.001

.001
.001
.0002
.001
.001
.001
.001

1.13-1.202.83-3.20
.72 - .77 4.42 - 5.00
.67 - .71 4.78 - 5.41

• Secon Metal data sheet

Package Body
MOnolithic Memories utilizes a low-chlorinethermosetting epoxy
resin for all molded assembly. This moisture-resistant thermallyconductive plastic provides high-reliability protection ina
commercial environment.
1Thermoset Plastic
Thermal Expansion
Thermal Conductivity
Glass Transition Temperature
Heat Deflection Temperature
Water Absorption After
BOiling for 24 hrs.
Specific Gravity
Volume Resistivity
(Room Temperature)
Volume Resistivity (15OOC)
DielllCtric Constant (1 MHz)
Flexural Strength
Impact Strength'
FreNa+
Free CIHydrolyzable Chlorine

Mechanical Criteria

Gold
Silver
Calcium
Copper
Iron
Beryllium
Magnesium
Others

Tensile
'Resistance Weight
Diameter Elongation Strength (g) ohms per In. mg per ft

2.5 x 10-5·C max.
1.6X 10-3 caVseccmoCmin.
1500C min.
200·C min.
.5% max.
1.80-1.86
1015 0 - cm
1013 0 - cm
4.5 max.
19,000 psi
2.5 kgf. cmlmm 2
5 ppm max.
5 ppm max.
300 ppm max.

,lSumitomo Bakelite Company data sheet

Lead Finish
Monolithic Memories molded devices come standard with 300 600 microinches of tin plating on all exposed leads. This finish
provides the user with a solderable surface for PC board
attachment.
In addition to tin plating, Monolithic Memories offers a solder dip
finish. This finish puts a coating of solder on all exposed metal
and results in excellent solderability of the finished package.

Die AHach Pad/Bonding
Monolithic Memories utilizes high-strength conductive epoxy to
attach die to P-Dip leadframes. The leadframe is plated with 150
microinches of silver in the die attach area to enhance the
strength and reliability of the bond.
'Epoxy Characteristics (typical)
Specific Gravity
Shore "D" Hardness (ASTM-D-1706)
Coefficient of Thermal
Expansion (crn/cmo C)
Tensile Strength (ASTM-D"1002)
Measured at 25" C
Measured at 85" C
Volume Resistivity
(ohm - em, 25'" C -155" C)
Resistivity After 200 hrs.
Ag,ng at 1800C

2.31
84
2.5 X 10-5
2,100 psi
1,500 psi
.001
.0001

* A'micon Corporation data.. sheet

16-21

Package Drawings

Molded DIP

r-BO~IDINIG

Oil,

WIRE

LEAD

DIE IDEVICEI-J

16·22

LEAD FRAME

BONDING WIRE

PACKAGE BODY

Copper Alloy 195.
Copper Alloy Tamac 5.

1.25 Mil Gold Wire.

Thermoset Plastic.

LEAD FINISH

DIE PAD

DIE BOND

Tin Plating.
Solder Dip.

Spot Silver Plating
(150 Microinches).

Silver Filled Epoxy.

Monolithic

m

Memories

Package. Drawings
Package Drawings
16N Molded DIP

(1/4"x3/4")

.086

_II-I .018

1= .

± .004

.457±.102

PINNO'l'~'
J

.

IDENTIFY

2.184DIA (2)

i

.070 DIA

1.778

. 1S;TYP

'PIN NO. 1
IDENTIFY

'I

.

.

(EJECTOR PIN)
OPTIONAL

VERSION 2

.

VlJ

f
~1 ~'-A4f ::.:~
.300--1

7.620

J41100TYP

+

.on ±

.002]11

4-

"'"

.279 ± .051

•

•

1SN Molded DIP

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MIUIMETERS
ALL TOLERANCES ARE ± .007 INCHES

(1/4"x7/S")

PIN NO. 1
'IDENTiFY

,

t~~;1(~
~.

.360 +.025
9.144 ±.63S

_.035

~
~
.889

.:!!!!. DIA
1.718

PIN NO. 1
IDENTIFY
VERSION l '
VERSION 2'

--

--~
.914

Notes:
1. Lead material tolerances are. for tinplate finish only. Solder dip finish adds
2-10 mils thickness to all lead tip dimensions.
2. Both version 1 and version ,2 conf.igurationsare rnanufac~ured interchangeably.
3. Ejector pin marks on version 1 are optional.

lOMAR85

Package Drawings
Package Drawings
20N Molded DIP

.4S7±.102
--II'-~

(1/4"x1")

j:'DIA~
PINN.o.1
IDENTIFY

.

.

...

~lG;.

PIN NO. 1

W

IDENTIFY
VERSI.oN2"

p

VERSI.oN l'

"'~""I

I"

I

7.874

~1Jl-:\ l

1.020 + .015 _ _ __
25.908 ± .381

t

.257 ± .013
6.528

±.330

0

!10 TYP

I

f

5°-12°

~""I~_
.279 ± .051
'.to.. ~REF(2)
;It""
.360 ± .025
9.144 ±.63S

.........036
.914

24NS Molded SKINNYDIP

(1/4"x1 3/16")

~DIA{J
1.524

PIN N.o.1
IDENTIFY

~~P

PIN NO:1
IDENTIFY

~rr

UNLESS .oTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS

ALL TOLERANCES ARE ± .007 INCHES
1.196 + .015 _ _ _ _ _~
30.378 ± .381

'"
-~
.914
Notes:
1. Lead material telerances are fer tin plate finish .only. Solder dip finish adds
2-10 mils..thickness te all lead tip dimensiens.
2. Beth versien 1 and versien 2 configuratiens·are manufactured interchangeably.
3. Ejecter pin marks en versien 1 are .optienal.

MonolithIC W""emorles

10MAR85

Package Drawings
Package Drawings

-~
1.524

24N Molded DIP
(9/16"x1 114")

.086
2.184 DIA(2)

o

1..1)

~'....-'

PIN NO.1
IDENTIFY

~
3.048
DIA

(EJECTOR PIN)
OPTIONAL
PIN NO.1
IDENTIFY

b-rr-o-o-rr--o- r

"
..___ I
r-_______

1.256 + .015
-\
31_.90
_2
_±_.3_8_1_ _ _ _- i

t·

-',"':"'~-":"'/~2~"-~j
3~100

JumHmt
. ·1

REF

--

1

.100

.

- - 2.540

--

-15~~0-1

I
U+
I r~'~ -+--f1*-

~

MIN

3.810

~ .........
'10' TYP

I

.130 + .010

:~~:

.546 + .010 13.868 ± .254

~EF~;;

L

-------'

:~~ ~ :~~ -111:--

.660 + .025
16.764 ± .635

-=:

40N Molded DIP
(9/16")(2 1116") F'=,!d",!.,,!:d:,!,~~=k!=kk!:b!:,!:d,:!::.!="=!:b!d=b!:~"=k='="=~~9

o

~DIA(2)~

2.184
(EJECTOR PIN)
OPTIONAL

PIN NO. 1
IDENTIFY

~
3.048
DIA

PIN NO.1
IDENTIFY

-11-I

W

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAlt IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
I

2.0:E:~~:N l'

ALL TOLERANC1ES ARE ± .007 INCHES

I '

-,

52.222 ± .381

VERSION 2'

.

It~~
.~~~ ~ ~
~
_
7.620E:f_.254

-.r

I .300 ± .010

~REF

=,

LL

.150

3. 810

.130±.010

;'.'::,

- -::

,~U"

Notes:
1. Lead material tolerances are for tin plate finish only. Solder dip finis!) adds

2-10 mils thickness to all lead tip dimensions.
2. 80th version 1 and version 2 configurations are manufactured interchangeably.
3. Ejector pin marks on version

1

are optional.

.

~~i~ ~:~~~

U 1_
il

15.240

______I

.546 ± .010

j~
4'_11'

U

__

IY

REF (2)

...
.660 ± .025
16.764 ".635

NlonollthioW Memories

-~

13.868±.254 ",\ 110'TYP

II

. . . .'1'___.

7' TYP

__

1OMARS5

16-25

PeckageDrawlngs
Package Drawings
48N Molded DIP

(9116"x213/32")

o

.088 "
2.184 DIA (2)
(EJECTOR PIN)
OPTIONAL

.050 ...004 ' ....
1.270 ±.102

, I' ,.'
,
'"I
t
'
'
' .
.~~.
~,
~--.LMIN
2.408 +.015,

"

'

-:3i1

7.74? T"'
.
~~"
3.937

~'

'.

..:!!!!!..

, "

'

2.540

Jf'

"

".140±:010",
3.656 ±.254

... ~
.914

_.600_
15.24Q

.150 _

U10
PIN NO.1
IDENTIFY

~DIA
3.048
.011 ± .002 ....
.279 ±.OS1

'1S5
~W

~~

......

\~F~~;

.660+.025 _
-

11/.784 ±.635

UNLESS OTHERWISE SPEC;IFIED:

,
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ±.OO7INCHES
'

Notes:
1. Lead material tolerances are f()r ,in plate finish only: Solder dip finish /!.dds
2-10 milS thickness to all lead tip dimensions.
2. Both version l' and version 2configuriltions aremariufactured interchangeably.
3. Ejector pin marks on version 1 are optional.

16·26

10MAR85

Package Drawings
I
I

Molded Chip Carrier

i

DIE (DEVICE)
BONDING WIRE
LEAD FRAME

DIE PAD

PACKAGE BODY

,I

LEAD FRAME

BONDING WIRE

PACKAGE BODY

Copper Alloy 195.
Copper Alloy Tamac 5.

1.25 Mil Gold Wire

Thermoset Plastic.

I

LEAD FINISH

DIE PAD

DIE BOND

Tin Plating.
Solder Dip.

Spot Silver Plating
(150 Microinches).

Silver Filled Epoxy.

1

Monolithic

W Memories

16·27

Package Drawings
Package Drawing
20NL Molded Chip Carrier

(.351 "x.351 ")

1.143
~X4S0l

-I

--I

.010 ± .002

~ .254 ±.051

r;::=]

.353 ± .003
8.966 ±.076

sa

-t
.050 T Y P J
1.270

.390 ± .005

j
-- 1

9.906 ±.127

sa

r

.018 ± .003 TYP

.4S7±.076

-1--

.029 ± .003

.737±

.0761

TYP

-t-

O---~-

t

--::::

(EJECTOR PIN)

MonoIHhlc:WMemorles

030

.762

..,lli.
1.778

~;:,:,=,
.172

~ -3.~:DIA

i))

I

4.369

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.·MAlt IN INCHes
ALL DIMENSIONS MIN.·MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

16-28

.
e
]

Package Drawings
i

.1

Package Drawing
28NL Molded Chip

(.451"x.451")

.490 ±.005
12.446 ± .127

so

!

.050 T y p f
1.270

__f

.018 ± .003 TYP
.457 ±.076

-t
~TYP
.711±.076

~r

'03O

.762

1~;:8
.100 + .OOS
2.540 ± .127

.:lli..
4.369

L

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

Monolithic

W Memories

16·29

Package Drawings
Package Drawing
44NL Molded Chip Carrier

(.65O"x.650")

..:!!!lPINNO.l
.762 IDENTIFY

.050
1.27ii TYP

~x
45"
1.143

l

;.': DIA (2) (EJECTOR PIN)

MO±.07iL
.026 ±.003

-t

.125 ± .005 (2)
3.175 ±.127
(EJECTOR PIN)

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILUMETERS

ALL TOLERANCES ARE ± .007 INCHES

16-30

_I

I+I~

....1,·010±.G02

:254±.ii61

Package Drawings
, Package Drawing

Pin Grid Array

DIE (DEVICE)

SEAL RING

•
CA.VITY

PACJ(AGE B O D V 4 , _
. _ _ _ _\

PACKAGE BODY

LID

. PIN MATERIAL

Alumina
(Standard Dark)

Gold Plated Kovar With
Nickel Underplating

GoldPlated Kovar

BONDING WIRE

. CAVITY/SEALRING

1.25 Mil Aluminum

~old

Over Tungsten

Package Drawings
Package Draw·Ing
88p·1 Pin Grid Array (Cavity U )
(1.300"x1.30O")
p

PIN#1
IDENTIFY

78
76

r

.720 ±.008
18.288 ±.203 sa

BOTTOM VIEW

f[futvmh;u,_1__~_7'~~ f.'!~~
1.194 ±.203

PACKAGE BODY

-

l
.

. .134 + .015
3.404 ± .381

UNLESS OTHE
.
ALL DIMeNs:6":::E. SPECIFIED:
ALL DIMENSIONS ::N.-MAX. IN INCHES
Al,L TOLERANCES A~E·-MAX. IN MIL!JMETERS
.'
± .007 INCHES

16·32

MoneIithloW WIamoria.
.

Package Drawings
Package Drawing
88P-2 Pin Grid Array (Cavity Down)
(1.300"x 1.300")

PIN#1
IDENTIFY

.605 ± .003 SO
15.367 ± .076

.050 ± .003
1.270 ±.076

-t

1

.640 ±.008
16.256 ± .203

UOO±.013
33.020±.330

LmmlL---~

.

.018 + .002 DIA
.467±.061

T

HeAT$INK

.134 ± .015

BOTTOM VIEW

3.404 ± .361

r 4.ii64±:508 ~~::::::~~~-.
.160± .020 ,

+

!

•

,

.329 + .025
4357±.636

t

LID

UNLESS OTHERWISE SPECIFIED:
ALl DIMENSIONS MIN.-MAX. IN INCHES

ALL DIMENSIONS MIN:-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

16-33

Package.Drawlnga
Package Drawing·

Top Brazed

LEAD

PACKAGE BODY

LID

LEAD MATERIAL

HEAT SINK

Alumina

Gold Plated Kovar With
Nickel Underplating

Alloy 42

Blue Anodized
Aluminum

BONDING WIRE

CAVITY/SEAL RING

LEAD FINISHES

PREFORM

1.25 Mil Aluminum

Gold Over Tungsten

Gold Plate (Standard)
Solder Dip Over
Gold Plate

Conductive Epoxy

16~34

Package Drawings
Package Drawing
24T Top Brazed Ceramic Dip
(WIth Heat Sink)
(1/2"x1 114")

1
....I.....-.:.-,
_ PREFORM
_

~_

~J
.127±.025

.215 + .020
5.431 ±.508

-r---+-

T

E
"

,

1_

I
-

l'220+'015~
30.988
± .381
1.195 + .015
30.353 ± .381

_,

~'100

2540

.017±.002
.432 ± .051

~11__

.305 ±.010

~.254

1

.500 + .010

12.700 ±.254

-l

-1~+±~!~[

f

PREFORM

y-HEATSINK

.070 ± .010

1.778 ±.254

'

f

.036 ± . .914 ±.203

ffilririfITirrrl, [

'140+'010,J'j

3.1i5Il ± . 2 5 4 ,

~

~,I-~

PIN#l
IDENTIFY

D

~
5.334 ± .381

.•060 + .008

.

I~-------~I

__a_ .011 ±.003
~
,
.•630 + .025 --'I
.279 ± .076

O
16.002 ± .635

I

'·-t

1.524 ±.203

.' .

.012 ± .002
.305 ±, .051

1- LI-1~
r-

430 + 003
192

.385 + .003

"

9.779(.076

1

±.076-I

UNLESS OTHERWISE SPECIFIED:
All. DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS

All. TOLERANCES ARE ± .007 INCHES

1&-3,5

Package Drawings

Cerpack
BONOING WIRE

\

DIE (DEVICE)

BASEl

16·36

LEAD FRAME

~GLASS

LEAD FRAME

BONDING WIRE

CAP AND BASE

Alloy 42

1.25 Mil Aluminum

Pressed Alumina

GLASS

CAVITY

LEAD FINISHES

LS-0113

Gold Over Alumina
For Eutectic Die Attach

Tin Plate
Solder Dip

Monolithic WMemories

Package Drawings
Package Drawings
16W-3Cerpack
(1/4"x3/S")

.012:

:gg;

305 +.• 076
.
- .102

PIN #1
[IDENTIFY

1

16

1

t

~MAX

f/.016

t

~

1

.387 + •018
9.830 +. 457

.017 + . 0 0 2 J
.432 +.051

t

9

8

~BSCj
1.270

_
1

.305+.015
7.747 ± .381

~I

----.i

1

L.oo5

MIN

,127

r-- :'~083
':::~~!=~~==it====,====__======~~~~~~I;:::::::::::~__~[1'8~±'3~
t
l . II
t
I'"

+ 001

.

t

- .051

l.030± .010
.762 ±

1SW-1 Cerpack
(11/32"x1S/32")

012 + .003
~
.305 ~:~~;

253

.2~

~MAX-

7.239
(GLASS FLOW)

PIN #1
IpENTIFY ...

]
t

1.143

18

1

~

~ .:~

127+· 025
. . -.051

BscJII-

L

f

.406
11.786 ~ .432

~

.005

~

.'464~·.016
017

.017 ± . O O 2 J
.432 ±.O51

.050
1.270

.073 ± .012

6.. 426

.305 ± .015
7.747 ± .391

~

9

10

1

l.oos

MIN

.127

~9~:3 :.~

I.

I

~

1

't~--.'~~--=:---=---=---=---=--~I~~~~I======:1
I
. I
± .2~
I- 9~:i9 ----l
l.035± .1110
.889

MAX

(GLASS FLOW)
UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE± .007 INCHES

Monolithic

miD Memories

16·37

Package Drawings

Package Drawings
2OW-2 Cerpack
(1/4"x1/2")

.012 ~:::

,

PIN # 1
IDENTIFY

.045

MAX

~J~
~

.432±.051

.005

,

~.~

-+
025
.127._:051

I"

1

009
.271 ±.
6.883
±.229

1

076 + 016

! '
' i.930±·A06
~===~=~;;;;;;;;;;;~I:;:;=====--t_
[

.033

.1138

~.:11- ,J 1
~.~
I- ~
MAX-l

(GLASS FLOW)

24W-2 Cerpack

PlN#1
IDENTIFY

+003
.012 -.004

(3/8"x5/8")

[.30S~:~:

t
.017

"

1

.D45

24

±.OO2r

.613

+ .017

15.570 ~

1-

...:2l!2.BSCr~

.265 ± .015
6.731 ±.381

~

12

13

ltIIonoIIthJo

018

.432
457

=ct
----*-

.127

(GLASS FLOW)

16-38

-,-

1-

~
±.051

1.270

AX

[1.143 M

W""8morles

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAlt IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILUMETERS
ALL TOLERANCES ARE ± .007 INCHES

Package Drawings
Power Dissipation Determination
Introduction'
I

I

Thermal resistance for apackliged integrated circuit petermines
the operating temperature, and hence the performance and lifetime of the semiconductor device. For this reason, it is of interest
to know the thermal impedance of the package configurations
commonly in use and the effect of external factors such as air
circulation and board-mounting conditions on the device
temperature. To accomplish this end, measurement techniques
and standards have been established providing certain conven- ,
tions for data aquisitiOn. Monolithic Memories haS chosen to
conform to these conventions in measurement and provides
standard data for thermal impedance in the form of 8JC, 0CA'
and a provision for obtaining 8JA (reSistance from junction to
ambient) as a functiqn of air movement over the package or
package/board combination.

Use of Monolithic Memories data
In this publication data is presented. for a variety of packages and
ambient conditions. In order to simplify the data presentation,
graphs of 8CA vs. airflow are provided for packages in common
use: T~ include socket-mounted dual-in-linepackages such as
p-dip, cerdip, and side-brazed packages, bOard mounted cerpacks and flatpacks, and free-standing leadless.:chip Carriers.
Since8CA is a package geomettyJelated function, the user need
only look up the package type fOr the air-flow used.With this
number, and knowledge of the die attach type, the total thermal
resistanCe may be determined from the semiconductor junction

to the aml?ient. Since the 0JC is largely dependent on the
package type and di,e attach type,'a tal::lle hIlS been constructed
for easy use. (Although 0JC is a"die-size dependent Variable for
eutectic die attach, the effect of 8JC on IlJAis small enough that
a constant may be used:i'n most cases. For other die-attach
methods, the thermal re$istal)ce was only slightly dependent on '
die size). After obtaining 8JC and 8CA as described above, the.
total thermal resistance, 0JA, may be found by the:. addition of
8JC to 8CA as:..
'
8JA = 8JC + 8CA

Notes on the tabulated data
1. All side-brazed, Cerdip-sealed, and molded dual-in-line
packages were mounted in zero insertion force sockets and
placed transverse to the ,airstream. ThermocoupleS were
,mounted directly to the bottom of the package. ,
2. All cerpacks and flatpacks were boa;.d'mounted in direct
contact with a double-sided fiberglass-epoxy composite
printed circuit board. The thermocouple was placeddi~
rectly between the packagfil and the board and fastened to
the package.
3. All LCC packages except the 64 PIN Lee were freestanding,
suspended by 28 GA. tinned copper wire soldered to pads
corresponding to Vee ano GND. The 64 PIN LCC was
mounted in a single insertion socket. Thermocouples were
attaChedoirectly to the bottom of the parts. '

Thermatlmp~ance Measurement

Procedure
Definition
Thermal impedance of a device is defined as ,the rise in the junction temperature against some reference point per unit of power
dissipation or it may be described by the formula:
4 Tj (0C)
Tj = temperature of junction
Pd (Watts)
Pd = power dissipation

Theory
The pnnciple of measuring the Thermal Impedance of a device is
based on measuring the temperature of the hottest junction on
the die under power dissipation. This is done by using the substrate diode to monitor the chip temperature. By. reverse biasing
and forcing a small forward current (500 pA) through the device
under test (betWeen + VCC and ground), large number of substrate diodes become forward-biased. By doing this, the hottest
substrate diode juriction is automatically detected, since it has
the lowest voltage drop during this forward-biased condition. The
forward voltage drop across the substrate diode is quite linear
over a range of 25°C to 100°C. The hottest substrate diode is
used as Ii "thermometer" to monitor the chip under power.

a

Procedure
A block diagram of the Thermal Impedance setup is shown, in
Figure 1. The substrate diode is ,forward biased by the Constant
Current Source (-500 pAl. The VCC is supplied by the POwer
Supply, which is gated at 48.8 cycles/second, with a outy cycle
of '" 99.5%. The VF of the substrate diode is 'sampled' by the

.

SamplelHold circuit,which IS gated synchronously with the VCC
supply, sampling is done for 40 }.tS, during each 100 pS window
When the Vee power supply is OFF. In addition to the VFreadings,
the case temperature, (clQsest to die attach point) and the
AmbienttemperatiJre are monitored. The power dissipated (Pd)
by the device is measured byDVM and calculated:
Pd= ICCxVCC'
The oevice is mounted in a socket within a Wind Tunnel. The ,air
sPfiled within the wind tunnel is monitored with an Air Velocity
meter. The air sPfiled is ~justable from 0 to 1000 feet/min. The
use of a wind tunnel allows us to graph the temperature of the
die: in relationJo the COOling 'air sPfiled. The worst case 8JA is at
() air speed (STATIC).
_
.

Summary
The Thermallmpeda~ measurement can be summarizeO as
follows:
1). Calibration of the AVF/oC of the D.U.T. This is dema by
measuring the VF~t two different temperatures with the VCC
power supply OFF. and dividingtha 4VFby the 4°C.
2). Measurement of 4VF under operating conditions,unoer
differen~ air flow rates (0, 100, 500, l()()OfVmin.); while
measuring °c case, °C ambient, ICC and VCC- The readings
are recor(ied when the change in the c;ase (OCcase)
temperature iS,less than 2% (of 4 °C case - °C aml::l) over a
time of ,30 seconds..

PackageDl:'awings
3). Calculation of Thermal Impedance
Symbol of Definitions

VF1 =VF@ lowternp. cal. point (VCC OFF)
VF2 = VF(9),(ligh temp, cal. point (VCCOFF)
.
DC1= .Case DC @ low temp. cal. point (VCC OFF)
. DC2'",; Case 0C;:@ high temp. cal. point (VCC OFF)
VF3 =VF under power,stablized
.. °C3 ::: Cas~ °C under power, stabilized
~CA = Ambient DC
..
. ..

b) fJCA=

tCa _DCA)
Pd

Pd= ICCxVCC
c) iJJA

(.Junction to ambient).

iJJA=fJCA +fJJC=----··~C/W

.El1oc.k Diagram

1). Digital Thermometer measures °c case and °c ambient

r

I

I

2). DVM:l

m~asures VCC and ICC

3). DVM2 measures VF of the substrate diode

Ao

I

4). BINARY counter creates
thru Alt;
Ao = 100kHz, At = 50 kHz,
A2 = 25 kHz etc. synchronious.

IL__ _

5). Timing gate switches the power supply, arldress buffers,
and sample/hold circuits.

I
I

6). Constant current source provides -500 Jl.A to the VCC pin
for the VF measurement
7). The airflow meter measures the air velocity for airflow measurements.

F=48.B Hz
I;lUTY CYCLE = 99.5%

f}-----t

A-~-'-:If Vee ON

VCC

·vee OFF (VF LEVEL)
t-.---t--l00~.

ON (SAMPLEI

SIHGATE
1:1'-.--~

16-40

Monolithic W.emories

'"-----lJf OFF (HOLD)

Package Drawings
Package Drawings
MOLDED DIP (N) PACKAGES

LEADLESS CHIP CARRIER (L) PACKAGES

60.0

140.0

50.0

130.0

~j!1;

40.0

120.0

..i.,]

30.0

110.0

20.0

100.0

al
WI.)

II: •

15e.
j!:

I

I'
10.0

500

100

1000

AIR FLOW (IItmln)

60.0

50.0

R8JC(OCANATT)VALUES·
PACKAGE TYPE
DIE ATTACH

*

L

N

Au/Si Eutectic

<4

N/A

Epoxy

N/A

15

These are typical values for die of 8.000 mils2 .
Mo~t Monolithic Memories' products will be slightly 'lower.

40.0

30.0

20.0

R8JA + R8 J C + R8CA

10.0

100

SOO

1000

AIR FLOW (fllmln)

NOTES:
To determine Rli JA; first locate curve of A8eA vs air flow for the desired package. Read value of R8CA from this curve and add
R8JC from the table b e l o w . '
.
.

Monolithic

lUJI MeJliories

16-41

Package Drawings
Package Drawings

SIDE BRAZED (D) PACKAGES

CERDIP (J) PACKAGES

70.0

70.0

60.0

60.0

50.0

50.0

w

w

U

U

~~
!!!~

~~
!!!~

40.0

[fiu

[fiu
a:

a:

0

iiia:-'~
hon~;

.

(06) 385-6707
. Fax; (06) 330-6~H

17..a

Synderdyne Inc.
Ishibashi Bldg.
1-20-2 Dogenzaka
Shibuya-Ku
Tokyo 150
Phone: (03) 461-9311
Telex: J32457
Fax: (03)461-985

KOREA
Kortronics Enterprise
Rm 307, 9-Dong, B-Block
#604-1 Guro-Dong, Guro-GU
Seoul
Phone: 635" 1043
Telex: KORTRONK26759

NETHERLANDS
Alcom Electronics B.V.
P.O. Box 358
2900 AJ Capelle
AID lissel Holland
Phone: 010-519533
Telex: 26160

NORWAY
HenacoA/S
P.O. Box 126 Kaldbakken
Trondheimsveien 436 Ammerud
Oslo 9
Phone: 02-162110
Telex: 76716 HENACO

PORTUGAL
Digicontrole
Apartado 2-Sabugo 2715
Pero Pinheiro
Phone: 35-1-292-3924
Telex: 62551 STUREP P.

SINGAPORE
Monolithic Memories Singapore
Pte., Ltd.
19 Kepple Road 11-06
Jit Poh Building
Singapore 0208
Phone: 65-2257544
Telex: RS55650
Fax: 2246113
Dynamarlntemational Ltd.
Unit05-11,
12 Lo Rong Bakar Batu
Kolam Ayer Industrial Estate
Singapore 1334
Phone: 65-7476188
Telex: RS26283 DYNAMA
Fax: 65-747-2648

MonoIllhlc·W.emorles

SOUTH AFRICA
Promilect Pty Ltd.
P.O. Box 56310
Pinegowrie 2123
Phone: 27-11-789-1400
Telex: 424822

SOUTH AMERICA
Intectra
2629 Terminal Blvd
Mountain View, CA 94043
Phone: (415)967-8818
Telex: 910-345545
Intectra Do Brasil
Av. Paulista 807-S/415
Sao Paulo
Phone: 285-6305
Telex: 01139872 BRCOBR

SPAIN
Sagitron
C/Castello, 25, 2
Madrid 1
Phone: 1-402-6085
Telex: 43819

SWEDEN
Naxab
Box 4115
S 17104 Solna
Phone: 08-985140
Telex: 17912

SWITZERLAND
Industrade AG
Hertistrasse 1
. 8304 Wallisellen
Phone: 01-8305040
Telex: 56788

TAIWAN
Sertek
315 Fushing N. Road
Taipei 104, Taiwan R.O.C.
Phone: 886-2-7134022
.. Telex: 23756 or 19162 MULTIIC
Multitech Electronics Inc.
125 W. EI Camino
Sunnyvale, CA 94086
Phone: (408) 733-8400
Telex: 352070

Notes

Notes



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