1985_Mitsubishi_Microprocessors_And_Peripheral_Circuits 1985 Mitsubishi Microprocessors And Peripheral Circuits

) tsu< READY- '" ) DREQ setup time before clock Tos 0 0 0 ns READY setup time before clock T Rs 100 60 60 ns 1> -READY) READY hold time before clock TRH 20 20 20 ns tSU(HLDA- "') HLDA setup time before clock T Hs 100 75 75 ns tSU(DQ-MEMR) Data setup time before MEMR TlDs 250 190 170 ns th(MEMR_DQ) Data hold time after MEMR TIDH 0 a 0 ns the Note - A.C Testing waveform Input pulse level Input pulse rise time Input pulse fall time Reference level input Output o. 45-2. 4V 10ns 10ns V,H =2V, V,L =0. 8V VoH =2V, VOL =0. 8V • MITSUBISHI ;"ELECTRIC 5-37 MITSUBISHI LSls MSM82C37AFP,-4,-S CMOS PROGRAMMABLE DMA CONTROLLER SWITCHING CHARACTERISTIC (i) SLAVE MODE (T a=-20-75"C , Vcc =5V±10%, Vss=ov, unless otherwise noted) Parameter Symbol Alternate symbol tPZVCR-OQ) Data enable time after read T ROE tpvzeR-DQ) Data disable time after read TRDF (ii) Limits M5M 82C37 AFP Min 0 I I I Max M5M82C37AFP-4 Max Min 200 100 M5M82C37AFP-5 Unit I I I 140 ns 70 ns Min 200 100 0 0 Max DMA MODE Symbol Parameter Alternate symbol Limits M5M82C37AFP Min Max M5M82C37AFP-4 Min Max M5M82C37AFP-5 Min Unit Max j6 '-AEN) Propagation time from clock to AEN TAEL 300 225 200 ns tpHL< -AEN) Propagation time from clock to AEN TAET 200 150 130 ns t pzv ( '" -A) Propagation time from clock to address active TFAAB 250 190 170 ns t pHL ( Propagation time from clock to address stable TASM 250 190 170 ns Propagation time from clock to address floating TAFAB 150 120 90 ns '" -DO") Propagation time from clock to data bus TFADB 300 225 200 ns ~YZ(."'-DQ) Propagation time from clock to data bus TAFDB 250 190 170 ns tpLH ( ¢ .ADSTB) Propagation time from clock to ADSTB TSTL 200 150 130 ns tpHLt '" -ADSTB) Propagation time from clock to ADSTB TSTT 140 110 90 ns tSU(OB-ADSTB) Data output setup time before ADSTB TASS 100 100 100 th(ADSTB-OQ) Data output hold time before ADSTB TAHS 50 40 30 Propagation time from clock to read or write active T FAC 200 150 150 ns Propagation time from clock to read or write t pLH ( '" -A) t pvz ( '" t pZV ( t pzv( rp t pZV ( t pHL ( -A) -R) ns ns '" -w) 1> -R) t pHL( 1>-w) TOCL 270 200 190 ns t pLH ( f.-A} Propagation time from clock to read TOCTA 270 210 190 ns t pLH ( F·W) Propagation time from clock to write TOCTW 200 150 130 ns Propagation time from clock to read or write floating T AFC 150 120 120 ns t pvz ( '" -R) tpvze!>_w) thIR-A) Address output hold time after read TAHR tell)-100 tel I )-100 t ell)-100 ns thIW-A) Address output hold time after write TAHW tel II-50 tell )-50 tell )-50 ns tsu( OQ-MEMWl Data output setup time before MEMW T oDv 200 125 125 ns th(MEMW-OQ) Data output hold time after MEMW TacH 20 20 10 ns t pLH ( Propagation time from clock to DACK TAK 250 220 170 ns tpHLC '" -EOP) Propagation time from clock to EOP TAK 250 190 170 ns t pLH ( Propagation time from clcak to EOP TAK 250 190 170 ns t pLH ( '" -HRC) 160 120 120 t pHL{ '" -HRC) 250 190 120 5-38 '" -DACK) -EOP) Propagation time from clock to HRQ TOQ I"H"2.0V I "H"3,3V .• MITSUBISHI .... ELECTRIC ns MITSUBISHI LSls MSM82C37AFP,-4,-S CMOS PROGRAMMABLE DMA CONTROLLER TIMING DIAGRAMS Reset timing tSU(VCC-RESET) Vee RESET CLK tSU(RESET-R) II lOR tSU(RESET-wl lOW Slave mode timing (READ) CS. A3 -Ao ~ CS, ADDRESS VALID tSU(CS-R) th{R-CS} tSU(A_R) th(R_A) I lOR K - tW(Rl lr- -, tPVZ(A_DQ} tPZV(A-OQ) DB,-CBo I---DATA VALID • MITSUBISHI "ELECTRIC \ / 5-39 MITSUBISHI LSls MSM82C37AFP,-4,-S CMOS PROGRAMMABLE DMA CONTROLLER Slave mode timing (WRITE) tSu-DACK} -I, ~ f' DACK tPLH(¢-AEN) tPHL(¢-AEN) -+AEN 1 ] , tPHL(¢_A) tPZV(o;I>_A) ~ A 7 ........ A o f ::T' II tPVZ(¢_A) ~/ A7- AO tPlH(¢.-ADSTB) ADSTB - t- th(ADSTB_DB) tsu( DB-ADSTS) i....-k. DB 7 -DB o ~~ t pzv ( ¢-DO} tpvZ(¢-OQ) ,- Ipzvl o'R) "">-- ~ Lzt) tPLH(¢_Rl -- f-t- ,...: ~ ......... MEMR/IOR Ipzv~ l-- MEMW/IOW 1 . \L tPVZ(O/>_R) Ir- J _~'#:W) tPHL(f-wl . -t-t- ff) t pLH ( ¢-A) ___ j L - - 1 tpvz(¢-wl ~ft:-W) (---sign ifies expansion write) rl u-~ ~--~ I t tPHjU ¢-EOP} tPLH(-EOP) I 'U EOP (Inlerna I) tSU(EOP-¢) EOP (Exlerna I) j \ \' tW(EOPl • MITSUBISHI "ELECTRIC 5-41 MITSUBISHI LSls MSM82C37AFP,-4,-S CMOS PROGRAMMABLE DMA CONTROLLER READY input timing ClK READY MEMR/IOR MEMW/IOW }-----r--------J tPHL(-W) I ( - - - signifies expansion write) s, S4 s, ClK READY MEMR/IOR MEMW/IOW 5-42 • MITSUBISHI .... ELECTRIC S4 MITSUBISHI LSls MSM82C37AFP,-4,-S CMOS PROGRAMMABLE DMA CONTROLLER Inter-memory transmission ru '\J\jru[\JUrururvL 5" eLK 5" 5" 5'3 J\j , A7-AO -- ~ th(ADSTB-OQl tpHu ..... ADSTB) rh l - I- J" tpVZ(~DQ) tPZV(¢.-OQ) tSU(OQ-MEMA) tSU(OQ-MEMW) th(MEMR-OQl A,s-A. \ DB7-DBo J III \\\ Data input A1S --As II outpuy 1-;--' t(MEMW_OQl I -f-- -r-t-- t-- tPHU';"A) , MEMR I v-----!---.J Data 1\ tPLH(';"R) tPZV(-A) J A7- AO AD5TB 5 23 tPHU';"A} tpZV(~_A) tpLH ( ..... ADSTS) 522 5" \-- tPVZ (t,6-R) 1/ - tpzv(fl.-wl tPHL(¢-wl l- t-- tPlH(¢-W) tpvz(¢-w) , In MEMW tpHU¢.-EOP) tpLH(¢-EOP) I , EOP t- t..-.l (Interna il tSU (EOP-4» EOP (Extern al) \\\\ J/// tW(EOP) • MITSUBISHI .... ELECTRIC I 5-43 MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE DESCRIPTION The M5M82C51 AP is a universal synchronous/asynchronous receiver/transmitter (USART) IC chip designed for data communications use. It is produced using the silicon-gate CMOS process and is mainly used in combination with 8-bit microprocessors. PIN CONFIGURATION (TOP VIEW) BIDIRECTIONAL DATA BUS RECEIVERi~~~~ Single 5V supply voltage TTL compatible Synchronous and asynchronous operation Synchronous: 5-8-bit characters Internal or external synchronization Automatic SYNC character insertion Asynchronous system: 5-8-bit characters Clock rate- 1 , 16 or 64 times the baud rate 1 , 1y" or 2 stop bits False-start-bit detection Automatic break-state detection Baud rate: DC-64K-baud Full duplex, double-buffered transmitter/receiver Error detection: parity, overrun, and framing • • • APPLICATIONS • • Modem control of data communications using microcomputers Control of CRT, TTY and other terminal eqUipment FUNCTION The M5M82C51 AP is used in the peripheral circuits of a CPU. It permits assignments, by means of software, of operations in all the currently used serial-data transfer systems BLOCK DIAGRAM 01- I 03- 2 RxD - (OV)V ss FEATURES • • • r l 2 - 0 1} 3 26 Vcc (5V) 4 25 - Rx C 2 - 00 BIDIRECTIONAL DATA BUS BIDIRECTIONAL DATE BUS ~tg~~~~PUT DATA-TERMINAL READY OUTPUT REQUEST-TOSEND OUTPUT 21 - DSR m~ys:lJpuT RESET RESET INPUT 2 - ClK CHIP-S~~~8i 18 - TxEMPTY ~~~~~5i-~~i- %~~~~~tPNA:CT 17 - CTS ~~~~~J~UT T x RDY ~~~~~~5i-~~T 2 - T~t~~~liJ~ST WRITE-DATA CONTROL INPUT CONT~Et~i~~~~ READ~Eg5~~ST RxRDY - 16 14 _ _ _ _r15 - ~ CLOCK INPUT TRANSMITTERDATA OUTPUT ~6NDET/ g~~KD6~~~6~ Outline 28P4 including IBM's 'bi-sync'. The M5M82C51 AP receives parallel-format data from the CPU, converts it into a serial format, and then transmits via the TxD pin. It also receives data sent in via the RxD pin from the external circuit, and converts it into a parallel format for sending to the CPU. On receipt of parallel-format data for transmission from the CPU or serial data for the CPU from external devices, the M5M82C51AP informs the CPU using the TxRDY or RxRDY pin. In addition, the CPU can read the M5M82C51 AP status at any time. The M5M82C51 AP can detect the data received for errors and inform the CPU of the presence of errors as status information. Errors include parity, overrun and frame errors. ------------l RESET INPUT CLOCK INPUT CONTROL/DATA-CONTROL INPUT READ-DATA CONTROL INPUT WRITE-DATA CONTROL INPUT TRANSMITIER-DATA OUTPUT CHIP-SELECT INPUT TRANSMITIER·READY OUTPUT TRANSMITIER·EMPTY OUTPUT TRANSMITIER·CLOCK INPUT DATA-SET READY INPUT DATA· TERMINAL READY OUTPUT CLEAR-TO-SEND INPUT REQUEST -TO-SEND OUTPUT RECEIVER-READY OUTPUT 25 Rxe RECEIVER-CLOCK INPUT 16 SYNDET/BD SYNC DETECT/BREAK DETECT BIDIRECTIONAL DATA BUS RECEIVER-DATA INPUT 5-44 • MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE OPERATION Table The M5M82C51 AP interfaces with the system bus as shown in Fig.l, positioned between the CPU and the modem or terminal equipment, and offers all the functions required for data communication. 1 M5MB2C51AP Access Methods c/o RO WR CS Function L L H L Data bus - Data in USART L H L L USART - Data bus H L H L H H L L Control - Data bus X H H L 3-State - Data bus X X X H 3-State - _.-.- Data bus - Staus ----.----------~ 16 ADDRESS BUS Ao 4 IIOR IIOW RESET 8 ~ 2(TTl ReadlWrite Control Logic DATA BUS This logic consists of a control word register and command word register. It receives signals from the CPU control bus and generates internal-control signals for the elements. 8 Modem Control Circuit C/D CS Do-D7 RD INR RESET ClK M5MB2C51AP Fig. Data bus CONTROL BUS M5MB2C51AP interface to 80BOA standard sys- tem bus This is a general-purpose control-signal circuit designed to simplify the interface to the modem. Four types of control signal are available: output signals DTR and RTS are controlled by command instructions, input signal DSR is given to the CPU as status information and input signal CTS controls direct transmission. Data-Bus Buffer When using the M5M82C51 AP, it is necessary to program, as the initial setting, assignments for synchronous/asynchronous mode selection, baud rate, character length, parity check, and even/odd parity selection in accordance with the communication system used. Once programming is completed, functions appropriate to the communication system can be carried out continuously. When initial setting of the USART is completed, data communication becomes possible. Though the receiver is always in the enable state, the transmitter is placed in the transmitter-enable state (TxEN) by a command instruction, and the application of a low-level signal to the CTS pin prompts data-transfer start-up. Until this condition is satisfied, transmission is not executed. On receiving data, the receiver informs the CPU that reading for the receiver data in the USART by the CPU has become possible (the RxRDY terminal has turned to '1 '). Since data reception and the entry of the CPU into the data-readable state are output as status information, the CPU can assess USART status without accessing the RxRDY terminal. During receiving operation, the USART checks errors and gives out status information. There are three types of errors: parity, overrun, and frame. Even though an error occurs, the USART continues its operations,. and the error state is retained until error reset (ER) is effected by a command instruction. The M5M82C51 AP access methods are listed in Table 1. This is an 8-bit 3-state bidirectional bus through which control words, command words, status information, and transfer data are transferred. Fig. 2 shows the structure of the databus buffer. %2ID7 , Do Do .1 STATUS BUFFER L H RECEIVE-DATA .BUFFER r CONTROL BUFFER ~ H Y Fig. 2 TRANSMIT-DATA BUFFER ~ TO INT ERNAl D ATA BUS f-- Data-bus-buffer structure Transmit Buffer This buffer converts parallel-format data given to the databus buffer in to serial data with addition of a start bit, stop bits and a parity bit, and sends out the converted data through the T xD pin based on the control signal. Transmit-Control Circuit This circuit carries out all the controls required for serial data transmission. It controls transmitter data and outputs the signals required by external devices in accordance with the instructions of the read/write control logic. • MITSUBISHI ;"ELECTRIC 5-45 MITSUBISHI LSls MSM82CSIAP CMOS PROGRAMMABLE COMMUNICATION INTERFACE Receive Control Circuit This circuit offers all the controls required for normal reception of the input serial data. It controls receiver data and outputs signals for the external devices in accordace with the instructions of the read/write control logic. Receive Buffer This buffer converts serial data given via the RxD pin into a parallel format, checks the bits and characters in accordance with the communication format designated by mode setting, and transfers the assembled characters to the CPU via the data-bus buffer. Receiver-Data Input (RxD) Serial characters sent from another device are input to this pin and converted to a parallel-character format to serve as data for the CPU. Unless the '1' state is detected after a chip-master reset procedure (this resetting is carried out to prevent spurious operation such as that due to faulty connection of the RxD to the line in a break state), the serial characters are not received. This applies to only the asynchronous mode. When the RxD line enters the low state instantaneously because of noise, etc, the mis-start prevention function starts working. That is, the start bit is detected by its falling edge but in order to make sure that it is the correct start bit, the RxD line is strobed at the middle of the start bit to reconfirm the low state. If it is found to be high a faultystart judgment is made. Transmitter-Clock Input (rxC) This clock controls the baud rate for character transmission from the TxD pin. Serial data is shifted by the falling edge of the TxC signal. In the synchronous mode, the TxC frequency is equal to the actual baud rate. In the asynchronous mode, the frequency is specified as 1, 16, or 64 times the baud rate by the mode setting. Example When the baud rate is 110 bauds: TxC=110Hz(1X) TxC=l. 76kHz(16X) T xC=7. 04kHz(64X) Write-Data Control Input (WR) Data and control words output from the CPU by the lowlevel input are written in the M5M82C51 AP. This terminal is usually used in a form connected with the control bus I/OW of the CPU. Chip-Select Input (CS) This is a device-select signal that enables the USART by a low-level input. Usually, it is connected to the address bus directly or via the decoder. When this signal is in the high state, the M5M82C51 AP is disabled. Control/Data Control Input (C/O) This signal shows whether the information on the USART data bus is in thEt form of data characters or control words, or in the form of status information, in accordance with the RD and WR inputs while the CPU is accessing the M5M82C51 AP. The high level identifies control words or status information, and the low level, data characters. 5-46 Read-Data Control Input (RD) Receiver data and status information are output from the CPU by a low-level input for the CPU data bus. Receiver-Ready Output (RxRDY) This signal indicates that the received characters have entered the receiver buffer, and further, the receiver-data buffer in the data-bus buffer shown in Fig.2. It is possible to confirm the RxRDY status by using this signal as an interruption signal for the CPU or by allowing the CPU to read the D, bit of the status information by polling. The RxRDY is automatically reset when a character is read by the CPU. Even in the break state in which the RxD line is held at low, the RxRDY remains active. It can be 'masked by making the RxE( D2 ) of the command instruction O. Transmitter-Ready (TxRDY) This signal shows that the data is ready for transmission. It is possible to confirm the status of serial-data transmission by using it as an interruption signal for the CPU or by allowing the CPU to read the Do bit of the status information by polling. Since the TxRDY signal shows that the data buffer is empty, it is automatically reset when a transmission character is loaded by the CPU. The TxRDY bit of the status information means that the transmit-data buffer shown in Fig. 2 has become empty, while the TxRDY pin enters the highlevel state only when the transmit-data buffer is empty, TxEN equals '1', and a lowlevel input has been applied to the CTS pin. Status (Do): When transmit-data buffer (TDB) is empty, it becomes '1 '. TxRDY terminal: When (TDB is emptY)'(T xEN=l)'(CTS =0)=1 or resetting, it becomes active. Sync Detect/Break Detect Output-Input (SYNDET/BD) In the synchronous mode this pin is used for input and output operations. When it is specified for the internal synchronous mode by mode setting, this pin works as an output terminal. It enters the high state when a SYNC character is received through the RxD pin. If the M5M82C51 AP has been programmed for double SYNC characters (bi-sync), a high is entered in the middle of the last bit of the second SYNC character. This signal is automatically reset by reading the status information. On designation of the M5M82C51 AP to the external synchronous mode, this pin begins to serve for input operations. Applying a high signal to this pin prompts the M5M82C51 AP to begin assembling data characters at the next rising edge of the RxC. For the width of a high-level signal to be input, a minimum RxC period is required. Designation of the asynchronous mode causes this pin to function as a BD (output) pin. When the start, data, and parity bits and stop bits are all in the low state for two characters period, a high is entered. The BD (break detect) signal can also be read as the D6 bit of the status information. This signal is reset by resetting the chip master or by the RxD line's recovering the high state. • MITSUBISHI "'ELECTRIC MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE Clear-To-Send Input (CTS) When the T xEN bit (Do) of the command instruction has been set to '1' and the CTS input is low serial data is sent out from the T xD pin. Usually this is used as a clear-to-send signal for the modem. Note: CTS indicates the modem status as follows: ON means data transmission is possible; OFF means data transmission is impossible. Transmitter-Empty Output (TxEMPTY) When no transmisison characters are left in the transmit buffer, this pin enters the high state. In the asynchronous mode, the following transmission character is shifted to the transmit buffer when it is loaded from the CPU. Thus, it is automatically reset. In the synchronous mode, a SYNC character is loaded automatically on the transmit buffer when no transferdata characters are left. In this case, however, the TxEMPTY does not enter the low state when a SYNC character has been sent out, since T xEMPTY = H denotes the state in which there is no transfer character and one or two SYNC characters are being transferred or the state in which a SYNC character is being transferred as a filler. T xEMPTY is unrelated to the T xEN bit of the command instruction. Transmission-Data Output (TxD) Parallel-format transmission characters loaded on the M5M82C5l AP by the CPU are assembled into the format designated by the mode instruction and sent in serial-data form via the T xD pin. Data is output, however, only in cases where the Do bit (TxEN) of the command instruction is '1' and the CTS terminal is in the low state. Once reset, this pin is kept at the mark status (high level) until the first character is sent. ON means the modem can transmit and receive; OFF means it cannot. Request-To-Send Output (RTS) This is a general-purpose output signal but is used as a request-to-send signal for the modem. The RTS terminal is controlled by the D5 bit of the command instruction. When D5 is equal to '1', RTS= l, and when D5 is 0, RTS= H. Command register D5=l~RTS=l Command register D5=0~RTS=H Note: RTS controls the modem transmission carrier as follows: ON means carrier dispatch; OFF means carrier stop. Data-Terminal Ready Output (DTR) This is a general-purpose output signal, but is usually used as a data-terminal ready or rate-select signal to the modem. The DTR pin is controlled by the D, bit of the command instruction; if D,=l, DTR=l, and if D,=O, DTR=H. D, of the command register=l~DTR=l D, of the command register=O~DTR=H Receiver-Clock Input (R;;-C) This clock signal controls the baud rate for the sending in of characters via the RxD pin. The data is shifted in by the rising edge of the RxC signal. In the synchronous mode, the RxC frequency is equal to the actual baud rate. In the asynchronous mode, the frequency is specified as 1, 16, or 64 times the baud rate by mode setting. This relationship is parallel to that of T xC, and in usual communication-line systems the transmission and reception baud rates are equal. The TxC and RxC terminals are, therefore, used connected to the same baud-rate generator. Clock Input (ClK) This system-clock input is required for internal-timing generation and is usually connected to the clock-output (ClK) pin of the 8085A. Although there is no direct relation with the data-transfer baud rate, the clock-input (ClK) frequency is more than 30 times the T xC or RxC input frequency in the case of the synchronous system and more than 4.5 times in the case of the asynchronous system. Reset Input (RESET) Once the USART is shifted to the idle mode by a high-level input, this state continues until a new control word is set. Since this is a master reset, it is always necessary to load a control word following the reset process. The reset input requires a minimum 6-clock pulse width. Data-Set Ready Input (DSR) This is a general-purpose input Signal, but is usually used as a data-set ready signal to test modem status. Its status can be known from the status reading process. The D7 bit of the status information equals '1' when the DSR pin is in the low state, and '0' when in the high state. DSR=l ~D7 bit of status information=l DSR=H~D7 bit of status information=O Note: DSR indicates modem status as follows: PROGRAMMING It is necessary for the M5M82C5l AP to have the control word loaded by the CPU prior to data transfer. This must always be done following any resetting operation (by external RESET pin or command instruction IR). There are two types of control words: mode instructions specifying general operations required for communications and command instructions to control the M5M82C5l AP actual operations. Following the resetting operation, a mode instruction must be set first. This instruction sets the synchronous or asynchronous system to be used. In the sysnchronous system, a SYNC character is loaded from the CPU. In the case of the bi-sync system, however, a second SYNC character must be loaded in succession. loading a command instruction makes data transfer possible. This operation after resetting must be carried out for initializing the M5M82C5l AP. The USART command instruction contains an internal-reset IR instruction (Dsbit) that makes it possible to return the M5M82C5l AP to its reset state. The initialization flowchart is shown in Fig. 3 and the mode-instruction and command-instruction formats are shown in Figs. 4 and 5. • MITSUBISHI "ELECTRIC 5-47 II MITSUBISHI LSls MSM82CSIAP CMOS PROGRAMMABLE COMMUNICATION INTERFACE SINGLE CHARACTER SYNC EXTERNAL SYNC DETECT EVEN PARITY PARITY ENABLE SYNCHRONOUS~~~~~-'~~~~~~---r--~------­ MODEL-__L-~~~__~~~__-L__-L~~ EVEN PARITY PARITY ENABLE CHARACTER LENGTH o0 oI I I 0 I 5 6 7 8 Fig. 3 Initialization flow chart ASYNCHRONOUS MODE~~~~~~~~~L-~~~-=~ 0, Fig. 4 06 05 0, 03 Mode-instruction format 02 0, Do ( C/O=' ) WR =0 I I ENTER HUNT MODE ENTER HUNT MODE II-ENABLE SEARCH FOR SYNC CHARACTERS INTERNAL RESET rlNTERNAL RESET -II-TO INITIALIZATION 1 I I I I TRANSMISSION CARRIER . I CONTROL I-RTS-O REQUEST TO SEND I ERROR RESET r',~CLEAR ALL ERROR FLAGS PE OE. FE) ERROR RESET 1 SEND BREAK I SEND BREAK CHARACTER II-T,D=LOW I I RECEIVER ENABLE l'=ENABLE O=DISABLE Rx ENABLE DATA TERMINAL READY -I DATA-TERMINAL READY ll-DTR=o l A M TRANSMISSION ENABLE T ENABLE I = ENABLE x 0= DISABLE I EH I 0, Fig. 5-48 5 IR I RTSI ER ISBRKI RxE IOTA ITxENI 06 05 0, 03 0, 0, Command-instruction format • .MITSUBISHI ...... ELECTRIC Do - - (C/O=I. WR=O) I 1 MITSUBISHI LSls MSM82CSIAP CMOS PROGRAMMABLE COMMUNICATION INTERFACE Asynchronous Transmission Mode When data characters are loaded on the M5M82C51 AP after initial setting, the USART automatically adds a start bit (low) , an odd or even parity bit specified by the mode instruction during initialization, and a specified numbe( of stop bits (high). After that, the assembled data characters are transferred as serial data via the T xD pin if, transfer is enabled (T xEN = 1· CTS = U, In this case, the transfer data (baud rate) is shifted by the mode instruction at a rate of 1X, 1/16X, or 1/64X the T xC period. If the data characters are not loaded on the M5M82C51 AP, the T xD pin enters a mark state (high). When SBRK is programmed by the command instruction, break characters (low) are output continuously through the T xD pin. Asynchronous Reception Mode The RxD line usually starts operations in a mark state (high), triggered by the falling edge of a low-level pulse when it comes to this line. This signal is again strobed at the middle of the bit to confirm that it is a perfect start bit. The detection of a second low indicates the validity of the start bit (restrobing is carried out only in the case of 16X and 64X) , After that, the bit counter inside the M5M82C51 AP starts operating; each bit of the serial information on the RxD line is shifted in by the rising edge of RxC, and the data bit, parity bit (when necessary), and stop bit are sampled at the middle position. The occurrence of a parity error causes the setting of a parity-error flag. If the stop bit is in the low state, a frame error flag is set. Attention should be paid to the fact that the receiver requires only one stop bit even though the program has designated 1%or 2 stop bits. Reception up to the stop bit means reception of a complete character. This character is then transferred to the receiver-data buffer shown in Fig.2, and the RxRDY becomes active. In cases where this character is not read by the CPU and where the next character is transferred to the receiverdata buffer, the preceding character is destroyed and an overrun-error flag is set. These error flags can be read as the M5M82C51 AP status information. The occurrence of an error does not stop USART operations. The error flags are cleared by the ER( D4 bit) of the command instruction. The asynchronous-system transfer formats are shown in Figs. 6 and 7, Synchronous Transmission Mode In this mode the T xD pin remains in the high state until initial setting by the CPU is completed. After initialization, the state of CTS=L and TxEN =1 enables serial transmission of characters through the T xD pin. Then, data characters are sent out and shifted by the falling edge of the T xC signal. The transmission rate equals the T xC rate. Thus, once data-character transfer starts, it must continue through the T xD pin at the same rate as that of TxC. Unless data characters are provided from the CPU before the transmitter buffer becomes empty, one or two SYNC characters are automatically output from the TxD pin. In this case, it should be noted that the T xEMPTY pin enters the high state when there are no data characters left in the M5M82C51 AP to be transferred, and that the low state is not entered until the USART is provided with the next data character from the CPU. Care should also be taken over the fact that merely setting a command instruction does not effect SYNCcharacter insertion, because the SYNC character insertion is enabled after sending out the first data character. In this mode, too, break characters are sent out in succession from the T xD pin when SBRK is deSignated (D3= 1 ) by a command instruction. CPU-USART (5-8 BITS/CHARACTER) DATA CH~RACTER I ASSEMBLED RECEIPTION FORMAT DATA BITS (5-8) TRANSMITTER DATA OUTPUT (T,D) STD~ (I. 1 5.2) USART-CPU (5-8 BITS/CHARACTER) I DATA Note Fig. 6 Asynchronous transmission format I (transmission) PARIT BIT Fig. 7 • MITSUBISHI ...... ELECTRIC CHARA~TER (5-8) I When the data character is 5. 6, or 7 bits/character length. the unused bits (for USART - CPU) are set to zero. Asynchronous transmission format II (reception) 5-49 II MITsUBlsHI Lsis MSM82CSIAP CMOS PROGRAMMABLE COMMUNICATION INTERFACE Synchronous Reception Mode Character synchronization in this mode is carried out internally or externally by initial-setting designation. Programming in the internal synchronous mode requires that an EH instruction (D 7 = 1, enter hunt mode) is included in the first command instruction. Data on the RxD pin is sampled by the rising RxC signal, and the receiver-buffer contents are compared with the SYNC character each time a bit is input. Comparison continues until an agreement is reached. When the M5M82C51 AP has been programmed in the bi-sync mode, data received in further succession is compared. The detection of two SYNC characters in succession makes the USART end the hunt mode, setting the SYNDET pin to the high state. This reset operation is prompted by the reading of the status information. When the parity has been programmed, SYNDET is not set in the middle of the last data bit but in the middle of the parity bit. In the external synchronous mode, the M5M82C51 AP gets out of the hunt mode when a high synchronization signal is given to the SYNDET pin. The high signal requires a minimum duration of one RxC cycle. In the asynchronous mode, however, the EH signal does not affect the operation at all. Parity and overrun errors are checked in the same way as in the asynchronous system. During hunt-mode operations the parity bit is not checked, but parity checking is carried out even when the receiver is disabled. The CPU can command the receiver to enter the hunt mode, if synchronization is lost. This prevents the SYNC character from erroneously becoming equal to the received data when all the data in the receiver buffer is set to '1' Attention should be paid to the fact that the SYNDET F/F is reset each time status information is read irrespective of the synchronous mode's being internal or external. This, howev- er, does not return the M5M82C51 AP to the hunt mode. Synchronism .detection is carried out even though it is not the hunt mode. The synchronous transfer formats are shown in Figs. 8 and 9. Command Instruction This instruction defines actual operations in the communication mode designated by mode setting. Command instructions include transmitter/receiver enable error-reset, internal-reset, modem-control, enter-hunt and break transmission instructions. The mode is set following the reset operation. A SYNC character is set as required, and the writing of high-level signals on the control/data pin (C/D) that follows it is regarded as a command instruction. When the mode is set all over again from the beginning, the M5M82C51 AP can be reset by using inputting via the reset terminal or by internal resetting based on the command instruction. Note 1: The command error reset (ER), internal reset (IR) and enter-hunt-mode (EH) operations are only effective when the command instruction is loaded, so that these bits need not be returned to '0'. 2: When a break character is sent out by a command, the T xD enters the low state immediately irrespective of whether or not the USART has sent out data. 3: Operations of the USART's receiver section which is always in the enable state cannot be inhibited. The command instruction RxE = 0 does not mean that data reception via the RxD pin is inhibited; it means that the RxRDY is masked and error flags are inhibited. CPU-USART (5~8 BITS/CHARACTER) I DATA CH:fRACTER I ASSEMBLED TxD OUTPUT USART-CPU (5~8 BITS/CHARACTER) I Fig. 8 Synchronous transmission format I (transmission) Note Fig. 5-50 9 • MITsUBISHI ..... ELECTRIC DATA ~;ARACTER I When the data character is 5, 6, or 7 bits/character length, the unused bits (for USART- CPU) are set to zero. Synchronous transmission format II (reception) MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE Status Information FE: The CPU can always read USART status by setting the C/O to '1' and RD to '0'. The status information format is shown in Fig. 10. In this format RxRDY, TxEMPTY and SYNDET have the same definitions as those of the pins. This means that these three pieces of status information become '1' when each pin is in the high state. The other status information is defined as follows: DSR: When the DSR pin is in the low state, status information DSR becomes '1'. The occurrence of a frame error in the receiver section makes the status information FE '1 '. The occurrence of an overrun error in the receiver section makes the status information OE '1 '. The occurrence of a parity error in the receiver section makes this status information PE '1 '. This information becomes '1' when the transmit data buffer is empty. Be careful because this has a different meaning from the TxRDY pin that enters the high state only when the transmitter buffer is empty, when the CTS pin is in the low state, and when TxEN is '1 '. OE: PE: T xRDY: 11 I FOR DSR LOW LEVEL 0 FOR DSR HIGH LEVEL SAME DEFINITION AS SYNDET/BD PIN I FE IS SET WHEN A VALID STOP BIT IS NDT DETECTED AT THE END OF EVERY CHAR I ACTER (ASYNC ONLY) IT IS RESET BY THE ER BIT OF THE COMMAND INSTRUCTION I I FE DOES NOT INHIBIT OPERATION OF THE M5M82C51AP OE IS SET WHEN THE CPU DOES NOT READ A CHARACTER BEFORE THE NEXT ONE BECOMES AVAILABLE IT IS RESET BY THE ER BIT OF THE COMMAND INSTRUCTION OE DOES NOT INHIBIT OPERATION OF THE M5M82C51AP PE IS SET WHEN A PARITY ERROR IS DETECTED IT IS RESET BY THE ER BIT OF THE COMMAND INSTRUCTION PE DOES NOT INHIBIT OPERATION OF THE MSM82C51AP .I I DSR I 8~~ I D7 Fig. 10 D6 FE D5 I OE D, I PE I T xE D3 D2 I I I T~--j :~Y ~~Y D, SAME DEFINITION AS TxEMPTY PIN I SAME DEFINITION AS RxRDY PIN I 1 FOR TRANSMIT DATA BUFFER IS EMPTY I I Do Status information (C/D=l, RD=O) APPLICATION EXAMPLES Fig. 11 shows an application example for the M5M82C51AP in the asynchronous mode. When the port addresses of the M5M82C51 AP are assumed to be 00 # and 01 # in this figure, initial setting in the asynchronous mode is carried out in the following manner: MYI A,86# Mode setting OUT 01 # MYI A,27# Command instruction OUT 01 # In this case, the following are set by mode setting: Asynchronous mode 6 bits/character Parity enable (even) 1'/2stoP bits Baud rate: 16X Command instructions set the following RTS=l~RTS pin=L RxE=l DTR=l~DTR pin=L TxEN =l When the initial setting is complete, transfer operations are allowed. The RTS pin is initially set to the low-level by setting RTS to '1', and this serves as a CTS input with TxEN being equal to '1 '. For this reason the same definition applies to the status and pin of TxRDY, and '1' is assigned when the transmit-data buffer is empty. Actual transfer of data is carried out in the following way: IN 01 # Status read The IN instruction prompts the CPU to read the USART's status. The result is; if the TxRDY equals '1' transmitter data is sent from the CPU and written on the M5M82C51 AP. Transmitter data is written in the M5M82C51 AP in the following manner: MYI A,20# 2D 16 is an example of transmitter data. USART~(A) OUT 00# Receiver data is read in the following manner: IN 00# (A)~USART In the above example, the status information is read and as a result, the transmitter data is written and read. Interruption processing by using the TxRDY and RxRDY pins is also possible. Fig. 12 shows the status of the TxD pin when data written in the USART is transferred from the CPU. When the data shown in Fig.12 enters the RxD pin, data sent from the M5M82C51 AP to the CPU becomes 2D,6 and bits D6 and D7 are treated as '0'. • MITSUBISHI ..... ELECTRIC 5-51 II MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE r~rlDrti~ j RxC C TO EXTERNAL CIRCUIT { x, TxC L BAUD RATE GENERATOR (DIVIDER) RTS RD RD CTS WR WR p-- EXTERNAL CIRCUIT CPU 8085A p---- DSR 101M ADDRESS DECODER c/B I--TO TRANSMISSION FROM RESET IN RESET OUT RESET USART M5M82C51AP DTR CS x, ClK ClK A15-Ag Tx D LlNE{ Rx D 07 . . . . . 00 AD,-ADo 8 8 8 ALE j TO MEMORY AND OTHER PERIPHERAL DEVICES Fig. 11 Example of circuit using the asynchronous mode STOP BIT (l. 5 BITS) START Fig. 5-52 12 BIT~ DATA I I----~"'-'---~ If--L--I 1 I II--START PARITY BIT Example of data transmission .• MITSUBISHI ...... ELECTRIC BIT MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vee Power-supply yoltage V, Input Yoltage Vo Output Yoltage Topr Operating free-air temperature range Tstg Storage temperature range Conditions With respect to Vss RECOMMENDED OPERATING CONDITIONS Limits Unit -0.3-7 V -0. 3-Vee+0. 3 V -0. 3-Vee+0. 3 V -20-75 ·C -65-150 ·C (Ta =-20-75'C, unless otherwise noted.) Limits Symbol Parameter Min Vce Supply Yoltage Vss Power-supply voltage Unit Nom Max 5 5.5 4.5 0 ELECTRICAL CHARACTERISTICS V V (Ta =-20-75'C, Vcc =5V±10%, Vss=OV, unless otherwise noted.) Limits Symbol Parameter Unit Test conditions " - .._ - - " Min Typ Max " V'H High-level input voltage 2 V'L Low-level input voltage -0.3 V aH High-level output voltage IOH=-400"A VOL Low-level output voltage IOL=2.2mA lec Supply current from Vee I'H High-level input current VI=VCC I'L Low-level input current V,=ov laz Off-state input current Vss=OV, v,=ov-Vcc C, Input capacitance GIIO Input/output capacitance Vcc+0.3 V 0.8 V 2.4 V 0.45 V 5 rnA -10 10 f.lA -10 10 /.LA -10 10 f.lA Vcc=Vss, f=1 MHz, 25mVrms , T8=25'C 10 pF Vcc=Vss, f=1 MHz, 25mV rms , T8=25'C 20 pF • MITSUBISHI ;"ELECTRIC .- .- 5-53 II MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE TIMING REQUIREMENTS(T a =-20-75'C, Vcc=5V±tO%, Vss=OV, unless otherwise noted.) Alternative Symbol Parameter Limits Unit Test conditions Symbol Min Typ Max tce, ) Clock cycle time (Notesl, 2) tCY 320 1350 twe, ) Clock high pulse width t, 120 tce,)-90 tweT) Clock low pulse width tT 90 ns ns ns tr Clock rise time tR 20 ns tf Clock fall time tF 20 ns kHz lX baud rate hx DC 64 16X baud rate fTx DC 310 kHz 64X baud rate fTX DC 615 kHz Transmitter input clock hx frequency tWCTPWL) tWCTPWH) Transmitter input clock low lX baud rate tTPW 12 tC(' ) pulse width 16X, 64X baud rate hpw 1 tce. ) Transmitter input clock high lX baud rate tTPD 15 tC(' ) pulse width 16X, 64X baud rate hPD 3 lX baud rate fRx 16X baud rate 64 kHz fRx 310 kHz 64X baud rate fRx DC 615 Receiver input clock low lX baud rate tRPw pulse width 16X, 64X baud rate Receiver input clock high lX baud rate pulse width 16X, 64X baud rate Receiver input clock fRx frequency tWCRPWU tc (' ) DC DC tW(RPWH) kHz 12 tce. ) t RPW 1 tcC' ) tAPO 15 tRPO 3 tce. ) !~ tSUCA-R) Address setup time before read (CS, C/O) (Note3) tAR 0 ns th(R-A) Address hold time after read (CS, C/O) (Note3) tRA 0 ns tweR) Read pulse width tRR tSUCA-W) Address setup time before write tAW 0 ns theW-A) Address hold time after write tWA 0 ns twew) Write pulse width tww 250 (200) ns tSU(oo~w) Data setup time before write tow 150(100) ns two 20( 0 ) thew-DO) Data hold time after write tSU(ESO~AxC) ESYNOET setup time before RxC 250(200) t ES 18 ns ns tce. ) tSU(C-R) Control setup time before read tCR 20 tce. ) tRv Write recovery time between writes (Note4) tRv 6 tce. ) tSU(Rxo-tS) RxD setup time before internal sampling pulse tSRx 2 !-IS th{tS-RxD) RxD hold time after internal sampling pulse tHRx 2 !-IS Note 5-54 The T xC and RxC frequencies have the following limitations with respect to ClK. For 1X baud rate hx, fRx ;i;1/(30t c e.I). For 16X, 64X baud rate hx, f Rx ;i;1/(4, 5t c e,) Reset p-ulse width=6t c e'l minimum. System clock must be running during reset. CS, C/O are considered as address. This recovery time is for mode initialization only. Write data is allowed only when T xRDY=l. Recovery time between writes for asynchronous mode is 8tCI.), and that for synchronous mode is 16tce.). • MITSUBISHI ...... ELECTRIC MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE SWITCHING CHARACTERISTICS (T a=-20~75°C , Vcc =5V±10%, Vss=ov, unless otherwise noted.) Limits Alternative Symbol Test conditions (Noten Parameter ------ symbol tPZV(R-DQ) Output data enable time after read (Note5) tPVZ{R-DQ) Output data disable time after read ------ tPZV(TxC-TxD) tDF - - - - - - - - - - - - - - - - = - - - - - -f - - - - - - TXD enable time after falling edge of TxC -------------------- hxADY tPHUW-TxR) Propagation time from write data to TxRDY (Note6) hxRDY CLEAR IpLH(CLB-RxR) Propagation time from center of last bit to RxRDY (Nole6) tRxRDY tPHL(R-RxR} Propagation time from read data 10 RxRDY (:Iear (Note6) tRxRDY CLEAR Propagation time from rising edge of RxC to internal SYNDET (Note6) tiS Propagation time from center of last bit to TxEMPTY (Note6) hxEMPTY Propagation time from rising edge of WR to control (Note6) twc 6 7 8 /.LS 8 tCI .) 400 ns 26 tCI • ) .- ns 26 tpLH ( RxO- SYD) IpLH(cLB-TxE) -- ns 1 400 -- ------~~~----~ ns 100 -- r--- Propagation time from center of last bit to TxRDY clear (Note6) tpHL(w-C) 200(170J 10 tCTx l PLH (cLB-TxR) Note 5 Max CL=150pF tAD ------ -------------- -- Typ - - r-------~ -------------- --------- -- Unit Min Assumes that address is vaild before falling edge of RD. Status-up data can have a maximum delay of 28 clock periods from the event affecting the status. Input pulse level O. 45~2. 4V Reference level Input V ,H =2V, V,L =0. 8V Input pulse rise time 10ns Output VoH =2V, VOL =0. BV Input pulse fall time 10ns M5M82C51 AP is also invested with the extended specification showed in the brackets. tCI. ) 20 tcl. ) 8 tcl. ) 2.4--V o. 45-A;:;~ V- 0::;".::.~A- ..::8_ _ _ TIMING DIAGRAMS System clock (elK) tC( ~) tr If ClK Transmitter clock & data ~."=4[ 10 11 12 13 14 II } tW(1)) 15 16 T xC(16X) ~ __---t-"W-'-(T-'-P-'-W.:cLl-------7>K-------t....W:.:(-"TP....Wc.H:...)------~ T,C(lX) tPZVI TXC-TXD I T,D Receiver clock & data R,D Rx-BIT COUNTER STARTS HERE DATA BIT START BIT DATA BIT RxC(16X) RxC(lX) INTERNAL SAMPLING PULSE tW(¢) • MITSUBISHI .... ELECTRIC 5-55 MITSUBISHI LSls MSM82CSIAP CMOS PROGRAMMABLE COMMUNICATION INTERFACE Write control cycle (CPU-USART) U tSU(A_W) j cio t bA tSU(A-W) tWlw) ~. tSU(OQ-wl ) D)-DO (DATA INPUT) l!:hIW-D'i! VALID K tPHL(W-cl ) DTR, RTS Read control cycle (USART -CPU) tSU(C_R) DSR, CTS ) tSU(A-R) thIR-A) ftSUIA-RI th(R_A) c/o .11\ tWIRl ¥ RD tPVZIR_DQI ~ tPZV(R-DQ) D)-DO (DATA OUTPUT) 5-56 j!J ~, • MITSUBISHI .... ELECTRIC VALID MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE Write data cycle (CPU--+USART) h(W-A) tSU(A_W) c/o t 1 IhIW- AI ISUIA_wl tW(w) tSU{DQ-wl th(W_DQ} ~ } D7~DO (DATA INPUT) VALID K II TxRDY r Read data cycle (USART--+CPU) tSU(A_R) tSU(A-A} c/o D7~DO (DATA OUTPUT) Rx RDY • MITSUBISHI ..... ELECTRIC 5-57 MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE Transmitter control & flag timing (async mode) c/o ] \~~\~[]~~/____~~/____~~L__~ __~I WR-TxEN WR-DATA 1 WR-DATA 2 WR-DATA 3 \ WR-DATA4 _-----""'\ _ - - - - - , R " - - - - - - - - , TxRDY (PIN) Tx RDY (STATUS) TxEMPTY BREAK STATE Note 8: Example format = 7 bits/character with parity & 2 stop bits 9: TxRDY(pin)= 1 -(Transmit-data buller is empty) - (TxEN = 1 ) - (CTS= 0)= 1 10: TxRDY(status)= 1 -(Transmit-data buller is empty) = 1 Receiver control & flag timing (async mode) c/o -.J \L-_ _ _---l\L--LI_ _ _ _ _............/L-J1 RD DATA 1 RD DATA 3 ..J ~ \~_ ___I\----I.l_ ___JI V '" RD ALL 0 DATA \ WR-ER WR-Rx E WR-\jfi! U '1\ BD (PIN) DATA 2 LOST OE (STATUS) tpt.HI r:LO.Rx'R) ~ Rx RDY J:- n S/OIil213(415J61p DATAl p r WoN21*N61p1~ \sJoN213141*lp1~ DATA 2 p DATA 3 p Notell: Example format = 7 bits/character with parity 5-58 • MITSUBISHI ~ELECTRIC t S S \SOI23456P;SOI23456P~ BREAK STATE L-- MITSUBISHI LSls MSM82CS1AP CMOS PROGRAMMABLE COMMUNICATION INTERFACE Transmitter control & flat timing (sync mode) o WR DATA 1 WR DATA 2 WR DATA 3 I""""""---~ u WR DATA 4 ~-~ , \ WR DATA 5 1""""""------- I""""""---~ Tx RDY (PIN) Tx RDY (STATUS) TxEMPTY Tx D DATA I Note12: DATA 2 SYNC CH 1 SYNC CH 2 MARK STATE DATA3 DATA4 MARK STATE ~~~~~ DATA 5 SYNC CH 1 SYNC CH 2 11 Example format = 5 bits/character with parity, bi-sync characters. Receiver control & flag timing (sync mode) INTERNAL SYNC EXTERNAL SYNC MODE MODE :J ,\...______.L......J/L.J1 C/o \ \ fIL.U\. ] C;,;,H,;,,;2"-_ _ _ R_D..,STATUS 1""""""--+---+-- EXTERNAL SYNC (INPUT) ~:~~NAL (OUTPUT) RD DATA WR-EH-RxE WR-EH-RxE SYNDET (PIN) c tPLH(RxC-SYD) tSU(ESD-RxC} SYNDET (STATUS) OE (STATUS) DATA 2 LDST r+--~ Rx RDY RxD - SYNC' SYNC: : DATA 1 DATA2 DATA3 CH 1 CH 2 : : EXITS HUNT MODE SYNDET SET Note13: Example format = j SYNC CH 1 SYNC CH 2 lCHARACTER ASSEMBLY BEGINS 5 bits/character with parity, bi-sync characters. • MITSUBISHI ;"ELECTRIC 5-59 MITSUBISHI LSls MSM82CS1AFP CMOS PROGRAMMABLE COMMUNICATION INTERFACE DESCRIPTION The M5M82C51 AFP is a universal synchronous/asynchronous receiver/transmitter (USART) IC chip designed for data communications use. It is produced using the silicon-gate CMOS process and is mainly used in combination with 8-bit microprocessors. PIN CONFIGURATION (TOP VIEW) BIDIRECTIONAL DATA BUS RECEIVER;~~~~ • • • 3 26 Baud rate: DC-64K-baud Full duplex, double-buffered transmitter/receiver Error detection: parity, overrun, and framing APPLICATIONS • Modem control of data communications using microcomputers • Control of CRT, TTY and other terminal equipment FUNCTION The M5M82C51 AFP is used in the peripheral circuits of a CPU. It permits assignments, by means of software, of operations in all the currently used serial-data transfer systems including IBM's 'bi-sync'. The M5M82C51 AFP receives para- 2 ~ RTS BIDIRECTIONAL DATA BUS T~tg~~IIJ~~;: CON~~~C;~~~~ BIDIRECTIONAL DATE BUS V cc (5V) D4- 5 Single 5V supply voltage TTL compatible Synchronous and asynchronous operation Synchronous: 5-8-bit characters Internal or external synchronization Automatic SYNC character insertion Asynchronous system: 5-8-bit characters Clock rate- 1 , 16 or 64 times the baud rate 1 ,1 y., or 2 stop bits False-start-bit detection Automatic break-state detection BLOCK DIAGRAM Rx D ~ (OV)Vss FEATURES • • • 2 - 0 1} 2 -DO 2 ~ 21 ~ 2 ~ CLK RECEIVER· CI,OCK INPUT DATA·TERMINAL READY OUTPUT ~~~g~JT~~;' 0 SR ~~ItysfJpuT RESET RESET INPUT CLOCK INPUT 19 ~ T x 0 6~~~~MJn5~' 18 ~ T,EMPTY ~~'i.~W~Vr~~·T CHIP.S~~~Si %g~~~gIPN'lI~ CONTRREtE;~~~~ READ';!'g5~~~RxROY~ 14 '------~ Outline 17 ~ CTS ~f~t~J~UT 16 - ~~NDETI ~~~KDgm6~ 15 ~ Tx RDY ~~~~~~~~~~T 28P2W lIel-format data from the CPU, converts it into a serial format, and then transmits via the TxD pin. It also receives data sent in via the RxD pin from the external circuit, and converts it into a parallel format for sending to the CPU. On receipt of parallel-format data for transmission from the CPU or serial data for the CPU from external devices, the M5M82C51 AFP informs the CPU using the T xRDY or RxRDY pin. In addition, the CPU can read the M5M82C51 AFP status at any time. The M5M82C51 AFP can detect the data received for errors and inform the CPU of the presence of errors as status information. Errors include parity, overrun and frame errors. M5M82C51 AFP is different from M5M82C51 AP only in the package outline. Refer to the M5M82C51 AP for more details. -----------l RESET INPUT CLOCK INPUT CONTROL/DATA·CONTROL INPUT READ·DATA CONTROL INPUT WRITE·DATA CONTROL INPUT TRANSMITIER·DATA OUTPUT CHlp·SELECT INPUT Tx RDY TxEMPTY DATA·SET READY INPUT TRANSMlnER·READY OUTPUT TRANSMITIER·EMPTY OUTPUT TRANSMITIER·CLOCK INPUT DATA·TERMINAL READY OUTPUT CLEAR-TO·SEND INPUT REQUEST·TO·SEND OUTPUT RxRDY RECEIVER·READY OUTPUT 25 RxC RECEIVER·CLOCK INPUT 16 SYNDET/BD SYNC DETECT/BREAK DETECT BIDIRECTIONAL DATA BUS RECEIVER·DATA INPUT 5-60 •. MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSM82CS4P,-6 CMOS PROGRAMMABLE INTERVAL TIMER DESCRIPTION The M5M82C54P is a programmable general-purpose timer device developed by using the silicon-gate CMOS process. It offers counter and timer functions in systems using an 8-bit parallel-processing CPU. The use of the M5M82C54P frees the CPU from the execution of looped programs, countoperation programs and other simple processing involving many repetitive operations, thus contributing to improved system throughputs. The M5M82C54P works on a single power supply, and both its input and output can be connected to a TTL circuit. M5M82C54P Parameter Clock high pulse width 60ns Clock low pulse width 60ns Clock cycle time PIN CONFIGURATION (TOP VIEW) vee (5V) 23 - BIDIRECTIONAL DATA BUS 125ns Propagation time 120ns CS ~~~;.SELECT 18 17 CLOCK INPUT CLKO~ 9 CLK2 CLOCK INPUT ~OUT2 g~~~~R 16 -GATE2 GATE INPUT cg~~~~~ OUTO~ 10 15 - GATEO~ 11 14 ~GATEI 13 ~ OUTI g3¥~JiR GATE INPUT (Ov) GND from read to output RD READ INPUT 21 - 20 - Ao .}ADDRESS 19- A, INPUTS M5MB2C54P-6 55ns -110ns -165ns WR WRITE INPUT 22 - --..----~ 170ns CLK1 CLOCK INPUT GATE INPUT Outline 24P4 FEATURES • • • • Single 5V supply voltage TTL compatible Pin connection compatible with M5L8253P-5 Clock period: M5M82C54P-6 ...................... M5M82C54P ......................... FUNCTION DC~6MHz DC~8MHz • 3 independent bult-in 16-bit down counters • • • 6 counter modes freely assignable for each counter Binary or decimal counts Read-back command for monitoring the count and status APPLICATION Delayed-time setting, pulse counting and rate generation in microcomputers. Three independent 16-bit counters allow free programming based on mode-control instructions from the CPU. When roughly classified, there are 6 modes (O~5). Mode 0 is mainly used as an interruption timer and event counter, mode 1 as a digital one-shot, modes 2 and 3 as rate generators, mode 4 for a software triggered strobe, and mode 5 for a hardware triggered strobe. The count can be monitored and set at any time. Besides the count, the status of the counter can be monitored by Read-back command. The counter operates with either the binary or BCD system. BLOCK DIAGRAM (5V) vecf4[C~= --8--- ---iOv) GND 12 WORD REGISTER 8 tI -.. D/ BIDIRECTIONAL DATA BUS --~CLK a --~GATE a --(1)llOUT 0 D6 D5 D, 4 CLOCK INPUT GATE INPUT COUNTER OUTPUT CLOCK INPUT GATE INPUT COUNTER OUTPUT READ INPUT CLOCK INPUT WRITE INPUT GATE INPUT CHIP-SELECT INPUT COUNTER OUTPUT INTERNAL "------' _ ._ _ _ _ _ _D_A_T_A :_U_S_ _ _ • MITSUBISHI .... ELECTRIC -----.J 5-61 11 MITSUBISHI LSls MSM82CS4P,-6 CMOS PROGRAMMABLE INTERVAL TIMER DESCRIPTION OF FUNCTIONS CONTROL WORD AND INITIAL-VALUE LOADING Data-Bus Buffer This 3-state, bidirectional,. 8-bit buffer is used to interface the M5M82C54P to the system-side data bus. Transmission and reception of all the data including control words for mode designation and values written in, and read from, the counters are carried out through this buffer. Read/Write Logic The read/write logic accepts control signals (RD, WR) from the system and generates control signals for· each counter. It is enabled or disabled by the chip-select signal (CS); if CS is at the high-level the data-bus buffer enters a floating (high-impedance) state. Read Input (RD) The count of the counter designated by address inputs Ao and A1 on the low-level is output to the data bus. Write Input (WR) Data on the data bus is written in the counter or controlword register designated by address inputs Ao and A1 on the lowlevel. Address Inputs (Ao, Al) These are used for selecting one of the 3 internal counters and either of the control-word registers. Chip-Select Input (CS) A low-level on this input enables the M5M82C54P. Changes in the level of the CS input have no effect on the operation of the counters. Control-Word Register This register stores information required to give instructions about operational modes and to select binary or BCD counting. Unlike the counters, it allows no reading, only writing. Counters 0,1 and 2 These counters are identical in operation and independent of each other. Each is a 16-bit, presettable, down counter, and has clock-input, gate-input and output pins. The counter can operate in either binary or BCD using the falling edge of each clock. The mode of counter operation and the initial value from which to start counting can be designated by software. The count can be read by input instruction at any time, and there is a "read-on-the-fly" function which enables stable reading by latching each instantaneous count to the registers by a special counter-latch instruction. The function of the M5M82C54P depends on the system software. The operational mode of the counters can be specified by writing control words (Ao, A1 = 1, 1) into the controlword registers. The programmer must write out to the M5M82C54P the programmed number-of count register bytes (lor 2) prior to actually using the selected counter. Table 2 shows control-word format, which consists of 4 fields. Only the counter selected by the 0 7 and 0 6 bits of the control word is set for operation. Bits 0 5 and 04 are used for specifying operations to read values in the counter and to Initialize. Bits D3 ~ 0 1 are used for mode designation, and Do for speCifying binary or BCD counting. When Do = 0, binary counting is employed~ and any number from 0000 16 to FFFF16 can be loaded into the count register. The counter is counted down for each clock. The counting of 0000 16 causes the transmission of a time-out signal from the count-output pin. The maximum number of counts is obtained when 0000 16 is set as the initial value. When 0 0=1, BCD counting is employed, and any number from 0000 10 to 999910 can be loaded on the counter. Neither system resetting nor connecting to the power supply sets the control word to any specific value. Thus to bring the counters into operation, the above-mentioned control words for mode designation must be given to each counter, and then 1 ~ 2 byte initial counter values must be set. The following is an example of this programming step. To deSignate mode 0 for counter 1 ,with initial value 825316 set by binary count, the following program is used: MVI A, 70 16 Control word 70 16 OUT n1 is contrOl-ward-register address MVI A, 53 16 Low-order 8 bits OUT n2 is counter 1 address MVI High-order 8 bits OUT "2. n2 is counter 1 address Thus, the program generally has the follbwing sequence: (1) Control-word output to counter i (i=O, 1,2). (2) Initialization of low-order 8 counter bits (3) Initialization of high-order 8 counter bits The three counters can be executed in any sequence. It is possible, for instance, to designate the mode of each counter and then load initial values in a different order. Initialization of the counters deSignated by RL 1 and RL 0 must be executed in the order of the low-order 8 bits and then the high-order 8 bits for the counter in question. 5-62 • MITSUBISHI .... ELECTRIC "1 MITSUBISHI LSls MSM82CS4P,-6 CMOS PROGRAMMABLE INTERVAL TIMER Table Basic Functions cs AD WA A, AD 0 I 0 0 a Data bus-Counter 0 I 0 0 I Data bus-Counter 1 0 I a Data bus-Counter 2 I a a I 0 I Data bus-Control-word register 0 a I a Data bus-Counter 0 0 0 I a a I Data bus-Counter 1 0 0 I I a Data bus-Counter 2 0 0 I I I 3-state I X X X X 3-state 0 I I X X 3-state Table I I Function a 2 Control-Word Format II eSC(Select Counter) SCI sca 0 f------- a Select counter a I Select counter 1 1 a ------ a ------- Select counter 2 --~- I I Prohibited combination e RL( Read/Load) All ALa 0 a a ~---- Counter Latch Command - - Read/load low-order 8 bits only I 1---- - - - - - - - - - - - - - - - - - - I a Read/load high-order 8 bits only - - f--- 1 1 Read/load low-order 8 bits and then high-order 8 bits eM(Mode) M2 MI Ma a a 1------ a a - - --- a ModeO 1 Model X I a Mode2 X 1 I Mode3 a a a Mode4 1 Mode5 -------- -- I----~-- 1 1 1--- ----- 1--------- eBCD I~-- f--_ _ _ -+_B_in_a-=ry_c_o_u_nt_e_r_CI_6_b_it_sJ_ _ _ _ __ Binary-coded decimal counter (4 decades) I SCI I sca I RLl I----- sc - + - I RL RLa M2 Ml Ma BCD M ---+BCD-1 • MITSUBISHI .... ELECTRIC 5-63 MITSUBISHI LSls MSM82CS4P,-6 CMOS PROGRAMMABLE INTERVAL TIMER MODE DEFINITION Mode 0 (Interrupt on Terminal Count) Mode set and initialization cause the counter output to go low-level (see Fig. 1). When the counter is loaded with an initial value, it will start counting the clock input. When the terminal count is reached, the output will go high and remain high until the selected count register is reloaded with the mode. This mode can be used when the CPU is to be interrupted after a certain period or at the time of counting up. Fig. 1 shows a setting of 4 as the initial value. If gate input goes low, counting is inhibited for the duration of the lowlevel period. Reloading of the initial value during count operation will stop counting by the loading of the first byte and start the new count by the loading of the second byte. Mode 1 (Programmable One-Shot) The gate input functions as a trigger input. A gate-input rising edge causes the generation of low-level one-shot output with a predetermined clock length starting from the next clock. Fig. 2 shows an initial setting of 4. While the counter output is at the low-level (during one-shot), loading of a new value does not change the one-shot pulse width, which has already been output. The current count can be read at any time without affecting the width of the one-shot pulse being output. This mode permits retriggering. Mode 2 (Rate Generator) Low-level pulses during one clock operation are generated from the counter output at a rate of one per n clock inputs (where n is the value initially set for the counter). When a new value is loaded during the counter operation, it is reflected on the output after the pulses by the current count have been output. In the example shown in Fig. 3, n is given as 4 at the outset and is then changed to 3. In this mode, the gate input provides a reset function. While it is on the low-level, the output is maintained high; the counter restarts from the initial value, triggered by a rising gate-input edge. This gate input, therefore, makes possible external synchronization of the counter by hardware. After the mode is set, the counter does not start counting until the rate n is loaded into the count register, with the counter output remaining at the high-level. Mode 3 (Square Rate Generator) This is similar to Mode 2 except that it outputs a square wave with the half count of the set rate. When the set value n is odd, the square-wave output will be high for (n+l) 12 clock-input counts and low for (n-1 ) 12 counts. When a new rate is reloaded into the count register during its operation, it is immediately reflected on the count directly following the output transition (high-to-Iow or low-to-high) of the current count. Gate-input operations are exactly the same as in Mode 2. Fig. 4 shows an example of Mode 3 operation. Mode 4 (Software Triggered Strobe) After the mode is set, the output will be high. By loading a 5-64 number on the counter, however, clock-input counts can be started and on the terminal count, the output will go low for one input-clock period and then will go high again. Mode 4 differs from Mode 2 in that pulses are not output repeatedly with the same set count. The pulse output is delayed one clock period in Mode 2, as shown in Fig. 5. When a new value is loaded into the count register during its count operation, it is reflected on the next pulse output without affecting the current count. The count will be inhibited while the gate input is low-level. Mode 5 (Hardware Triggered Strobe) This is a variation of Mode 1. The gate input provides a trigger function, and the count is started by its rising edge. On the terminal count, the counter output goes low for on one clock period and then goes high. As in Mode 1, retriggering by the gate input is possible. An example of timing in Mode 5 is shown in Fig. 6. As mentioned above, the gate input plays different roles according to the mode. The functions are summarized in Table 3. Table 3 I~ Gate Operations Low or going low Rising High Mode 0 Enables counting Disables counting , (1) Initiates counting (2) Resets output after next clock 2 (11 Disables counting (2) Sets output high immediately (11 Reloads counter (2) Initiates counting Enables counting 3 (1) Disables counting (2) Sets output high immediately (1) Reloads counter (2) Initiates counting Enables counting 4 Disables counting 5 • MITSUBISHI .... ELECTRIC Enables counting Initiates counting MITSUBISHI LSls MSM82CS4P,-6 CMOS PROGRAMMABLE INTERVAL TIMER OUT( GATE="H") WR ~ :L-...J GATE :4 OUT Fig. 1 I I I Mode 4 4 I :3 : 2 1 0 I a Fig. 4 Mode 3 elK WR GATE ________~r_~-:--~~--~---------- 3 2 0 LJ OUT OUT GATE 2 OUT Fig. 2 L--J 1 OUT Mode 1 Fig. 5 ~ Mode 4 II GATE WR 4 0 3 OUT(GATE="H") OUT(n=4) GATE ~r---------------------_;:.4....3.....3'--... 3.....;:........:.._2;.......:,1 4 3 2 1 4 3 OUT ~ Mode 2 4 Sometimes the counter must be monitored by reading its count or using it as an event counter. The M5M82C54P offers the following two methods for count reading: Read Operation The count can be read by designating the address of the counter to be monitored and executing a simple I/O read operation. In order to ensure correct reading of the count, it is necessary to cause the clock input to pause by external logic or prevent a' change in the count by gate input. An example of a program to read the counter 1 count is shown below. If RLl, RLO=l, 1 has been specified in the control word, the first IN instruction enables the I'ow-order 8 bits to be read and the second I N instruction enables the highorder 8 bits. IN n2 is the counter 1 address MOV 0, A "2 .... "2 MOV E, A The IN instruction should be executed once or twice by the RLl and RLO designations in the control-word register. 3 OUT(n=4) Fig. 6 COUNTER MONITORING LJ GATE U IN 0 elK elK Fig. 3 h--i GATE Lr-- Mode 5 Read-on-the-Fly Operation This method makes it possible to read the current count without affecting the count operation at all. A special counter-latch command is first written in the control-word register. This causes latching of all the instantaneous counts to the register, allowing retention of stable counts. An example of a program to execute this operation for counter 2 is given below. MVI A, 1000XXXX .... 0 5 = 0 4 = 0 designates counter latching OUT IN "1 .... nl is the control-ward-register address "3 .... n3 is the counter 2 address MOV 0, A IN "3 MOV E, A In this example, the IN instruction is executed twice. Due to the internal logic of the M5M82C54P it is absolutely essential to complete the entire reading procedure. If two bytes are programmed to be read, then two bytes must be read before any OUT instruction can be executed to the same counter. • MITSUBISHI ..... ELECTRIC 5-65 MITSUBISHI LSls MSM82CS4P,-6 CMOS PROGRAMMABLE INTERVAL TIMER Read Back Command M5M82C54P has a function of reading not only the. count but also status (Read Back Command). The read' back command enables the next four functions. (1) read the current count "on the fly" (2) monitor the current state of the OUT pin (3) monitor the current state of the counter element (whether the count is loaded into the counter element or not) (4) read the control word Read back operation can be specified by writing read back command into the control Word registers (Ao, A, = 1.1). Fig. 7 shows the format of read back command . . Bits D7 and D6 are used for specifying read back command and fixed 1 (D 7 = 1, D6 = 1). Respectively bits D5 (count) and D, (status) are used for reading the count and the status of the counter selected by the D3 - D, bits. Bit Do must be fixed O. Only the count can be read "on the fly" by setting D5 =0 ' and D, = 1 as well as counter latch command above mentioned. If D3 - D, are set 1 all, the counts of three counters are simultaneously latched by one read back command. (By counter latch command, it must be latched for each counter.) Next, by read operation, the latched count is read out. Only the status can be latched by setting D5 = 1 and D, = 0. By read operation, the status shown in Fig. 8 can be 5-66 read. BIT D7 gives the current state of OUT pin. When D7 = 1, OUT = "H", and when D7 =0, OUT =" "L". Bit D6 indicates the current state of counter element. When D6 =1, the initial counter value has not been loaded to counter element. This state is following. (1) The control word is written, but the initial counter value is not loaded (2) The initial counter value is written to count register, and the ClK inputs are not. When D6 = 0, the initial counter value has already been loaded. It is the state when the CLK falls following the rising edge after the initial Vi.lue is written. Bits D5- Do show the current state of the control word regsiter. It is possi ble to read both the count and the status. By setting D5 = and D, = 0, the status can be read first, and the count next. The count and/or the status are unlatched when read, so by the next read operation the current counting value can be read. And they are unlatched too when the control word is set, so the read back command must be set on all such occasions. If multiple read back commands are written before the read operation, only the first one is valid. Thus, the read of the status is effective when the state of output and the timing of count reading can be monitored by software. • MITSUBISHI ..... ELECTRIC ° MITSUBISHI LSls MSM82CS4P,-6 CMOS PROGRAMMABLE INTERVAL TIMER , - - - - - - - - - - - - - - - - - e Read Back Command (0 7 =1, 0 6 =1 : fixed) , - - - - - - , - - - - - - - - - eCOUNT=O: Latch Count r - - - - - - - - - - - - - e STATUS=O : Latch Status I ~e { CNT2=1 CNT1=1 CNTO=1 Select Counter 2 Select Counter 1 Select Counter 0 ieFixed on 0 _ _ _A _ _ ~ ~ ~ ~ ~ I COUNT I STATUS I ~ CNT2 ~ I CNTl ~ I CNTO ~ I Fig. 7 Read Back Command Format II e State of OUT pin OUT o lOUT pin is "H" level Out pin is "L" level e State of counter element CNT I I I I Initial value unloaded Initial value loaded 1 I e State of control word. register (cf. Table 2) ~-----_A~-----_ 0, 06 05 OUT CNT RLl RLO 03 02 0, 00 M2 Ml MO BCO Fig. 8 Status Byte • MITSUBISHI .... ELECTRIC 5-67 MITSUBISHI LSls MSM82CS4P,-6 CMOS PROGRAMMABLE INTERVAL TIMER ABSOLUTE MAXIMUM RATINGS Symbol Power supply voltage V, Input voltage Va Output voltage Topr Operating free-air temperature range Tstg Storage temperature range Limits Unit -0.3-7 V -0. 3-Vee+0. 3 V Conditions Parameter Vee With respect to GND -0. 3-Vee+0. 3 V -20-75 'c 'c -65-150 RECOMMENDED OPERATING CONDITIONS (Ta =-20-75°C, unless otherwise noted) Limits Symbol Unit Parameter Min Vee Power supply voltage Vss Supply voltage (GND) r-- - Nom Max 5 5.50 4.50 0 ELECTRICAL CHARACTERISTICS V V (Ta=-20-75'C, Vcc =5V±10%, unless otherwise noted) Limits Symbol Parameter Unit Test condition Min V'H High-level input voltage 2.0 V'L Low-level input voltage -0.3 V OH High-level output voltage Vss=OV,loH =-400!,A VOL Low-level output voltage vss=OV, I'H High-level input current I'L loz IOl =2. OmA Typ Max Vcc+O.3 V 0.8 V V 2.4 0.45 V Vss=OV, V,=5. 50V ±10 J."A Low-level input current Vss=OV, V,=OV ±10 J."A Off-state output current Vss=OV, VI=O--VCC ±10 J."A 10 mA J."A Icc Power supply current I M5M82C54P Vss=OV, 1=8MHz i M5M82C54P-6 Vss=OV, 1=6MHz Icc Power supply current during STAND BY Vss=OV, other inputs are Vss or Vee 10 Gj Input capacitance VIL=VSS, 1=1 MHz, 25mVrms, Ta=25'C 10 pF Gila Input/output capacitance VI/OL =Vss, 1=1 MHz,25mVrms, Ta=25'C 20 pF 5-68 • MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSM82CS4P,-6 CMOS PROGRAMMABLE INTERVAL TIMER TIMING REQUIREMENTS (T a=-20-75'C , Vcc=5V±1 0%, Vss=ov, unless otherwise noted) Read cycle Alternative Symbol Limits Test condition Parameter symbol ---- Unit Typ Min Max twCR) Read pulse width tRR tSUCS-R) CS setup time before read tSR tSUCA-R) Address setup time before read tAR thCR-A) Address hold time after read 150 c---- -- -- 0 -------~ Read recovery time trecCR) f-----tRA C--------tRV CL=150pF - ns -~ -~ "---- ns ---- ----- 1------- 45 ns ------ "_0- __ -" -- 0 ns 200 ns -- Write cycle Alternative Symbol Limits Test condition Parameter symbol Unit Typ Min Max twL) Clock low puLse width M5M82C54P-6 t PWL 110 125 M5M82C54P t c ( -0) TIMING DIAGRAMS (Reference vollage: High=2.0V, low=0.8V) Read cycle ,,~ / tSU(S'-R) ~ j/' 1\ tSU(A-R) >< AD, A, tPZV(A-Q) I IWIRI r------ ~ IhIR-AI K IpzvlR-al I--- L} ~ tpVZ(R-Q) "'' ' ' 1oV/ Write cycle ~ ~ tSU(S-W) .J/F- ~~ ISUIA-Wl l Iwlwl I J )< tSU(D-W) ----- thlw-Ai K Ihlw-ol ~X X (Recovery time) RD, WR 5-70 I • MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSM82CS4P,·6 CMOS PROGRAMMABLE INTERVAL TIMER Clock and gate cycle tW(GL) tW(GHJ GATE elK OUT II • MITSUBISHI ..... ELECTRIC 5-71 MITSUBISHI LSls MSM82CS4FP,-6 CMOS PROGRAMMABLE INTERVAL TIMER DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M5M82C54FP is a programmable general-purpose timer device developed by using the silicon-gate CMOS process. It offers counter and timer functions in systems using an 8-bit parallel-processing CPU. The use of the M5M82C54FP frees the CPU from the execution of looped programs, countoperation programs and other simple processing involving many repetitive operations, thus contributing to improved system throughputs. The M5M82C54FP works on a single power supply, and both its input and output can be connected to a TTL circuit. Parameter M5M82C54FP M5M82C54FP-6 Clock high pulse width (Min.) 60ns 55ns Clock low pulse width (Min.) 60ns 110ns Clock cycle time (Min.) 125ns 165ns vee (5V) 23 ~ WR WRITE INPUT 22 ~ RD READ INPUT BIDIRECTIONAL DATA BUS 20 ~ Ao ADDRESS 19 ~ AI JINPUTS 1 CLOCK INPUT CLKO~ 9 C~~~~~~ OUTO~ 10 GATEO~ 11 GATE INPUT 10v) GND 170ns 120ns DJ- 18 ~ ClK2 CLOCK INPUT -~ (Max.) 21 ~ CS ~~~~SElECT 17 ~OUT2 g~¥~JiR r------~----- Access time D4- FEATURES 16 Single 5V supply voltage TTL compatible Pin connection compatible with M5L8253P-5 Clock period: M5M82C54FP-6 .................. · .. M5M82C54FP ....................... • • • • • 3 independent bult-in 16-bit down counters 6 counter modes freely assignable for each counter Binary or decimal counts Read-back command for monitoring the count and status Package in flat small outline package DC~8MHz ~GATEI ~OUTI g8¥~JfR GATE INPUT 24P2W based on mode-control instructions from the CPU. When roughly classified, there are 6 modes (O~5). Mode a is mainly used as an interruption timer and event counter, mode 1 as a digital one-shot, modes 2 and 3 as rate generators, mode 4 for a software triggered strobe, and mode 5 for a hardware triggered strobe. The count can be monitored and set at any time. Besides the count, the status of the counter can be monitored by Read-back command. The counter operates with either the binary or BCD system. Refer to M5M82C54P/P-6 for detail information. M5M82C54FP/FP-6's specification are fully compatible with M5M82C54P/P-6. Only package outline is different. Delayed-time setting, pulse counting and rate generation in microcomputers. FUNCTION Three independent 16-bit counters allow free programming 15V)vccr.c~~-~-I--- ~t' 10v) GND~ [REGISTER I 9 ClK r COUNTER D, 1 0 BIDIRECTIONALl~:' ~ DATA BUS D3 D2 D, Do a 11 GATE 0 ~OUT -J CLOCK INPUT GATE INPUT COUNTER OUTPUT 0 CLOCK INPUT GATE INPUT COUNTER OUTPUT READ INPUT CLOCK INPUT WRITE INPUT GATE INPUT CHIP-SELECT INPUT COUNTER OUTPUT INTERNAL DATA BUS I ---------------.-----1 5-72 14 DC~6MHz APPLICATION BLOCK DIAGRAM GATE INPUT CLOCK INPUT 13 ---.._----, Outline • • • • ~GATE2 15~ClKI • MITSUBISHI ..... ELECTRIC MITSUBISHI LSls MSM82CSSAP-S CMOS PROGRAMMABLE PERIPHERAL INTERFACE DESCRIPTION This is a family of general-purpose programmable input/ output devices designed for use with the 8/16-bit parallel CPU as input/output ports. This device is fabricated using silicon-gate CMOS technology for a single supply voltage. This LSI is a simple input and output interface for TTL circuits, having 24 input/output pins which correspond to three 8-bit input/output ports. PIN CONFIGURATION (TOP VIEW) ( j PA3 - INPUT/OUTPUT PA,_ PORT A PA,_ I lPAoREAD INPUT RD ~ CHIP FEATURES • • • • • • STh~8+cs~ (ov) GND 35 - RESET 'RESET INPUT PORT ADDRESS { A, ~ INPUTS Ao ~ Single 5 V supply voltage TTL compatible Improved DC driving capability Improved timing characteristics 24 programmable I/O pins Direct bit set/reset capability BI-DIRECTIONAL DATA BUS INPUT/OUTPUT PORT C APPLICATION Input/output ports for MELPS85, MELPS86, MELPS88 microprocessor INPUT/OUTPUT PORT B FUNCTION These PPls have 24 input/output pins which may be individually programmed in two 12-bit groups A and B with mode control commands from a CPU. They are used in three major modes of operation, mode 0 , mode 1 and mode 2 . Operating in mode 0 , each group of 12 pins may be programmed in sets of 4 to be inputs or outputs. In mode 1 , the 24 I/O terminals may be programmed in two 12-bit groups, group A and group B. Each group contains one 8-bit data port, which may be programmed to serve as input or output, and one 4-bit control port used for handshaking and interrupt II Outline 40P4 control signals. Mode 2 is used with group A only, as one 8bit bidirectional bus port and one 5-bit control port. Bit set/ reset is controlled by CPU. A high-level reset input (RESET) clears control register, and all ports are set to the input mode (high-impedance state). BLOCK DIAGRAM 1-----------------; READ INPUT RD WRITE INPUT WR ADDRESS INPUTS JA, t-----= t=: 6 --..<: 8 lAo 9 RESET INPUT RESET CHIP SELECT CS INPUT ~ ~~_IT' CONTROL LOGIC GROUP A CONTROL 8 ~ l~~ ~ 4 I ~ GROUP B CONTROL 8 8 2 (5V) Vee' (OV) H PORT C I MOST SIGNIFI- L GROUP B PORT C LEAST SIGNIFI CANT 4 BITS) 1 17 PC 3 PORT C 16 PC, 15 PC, 14 PCo PB 7 PB6 2 PB5 PB, INPUT/OUTPUT 21 PB 3 PORT B 2 PB, 19 PB, 18 PBo 2 2 GROUP B PORT B (8-BIT) L-.,. GND~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ • MITSUBISHI .... ELECTRIC I PC 5 PC, INPUT/OUTPUT L r 8 PAo :~:l GROUP A Wi r- DATA BUS 31~ BUFFER : 02 3 ~~: 3 4 CANT 4 BITS) 8-BIT INTERNAL DATA BUS :~;1 PA 5 40 PA, INPUT/OUTPUT I jlPORT A 2 ~ ~H I I~; Ig: 30~ ". r I ~: 'J GROUP A PORT A (8-BIT) 8 8 - 2 28~ D5 29)..,.- DATA BUS 8 J3j .Ijg ~ -.-J 5-73 MITSUBISHI LSls MSM82CSSAP-S CMOS PROGRAMMABLE PERIPHERAL INTERFACE FUNCTIONAL DESCRIPTION Basic Operations Table RD (Read) Input At low-level, the status or the data at the port is transferred to the CPU from the PPI. In essence, it allows the CPU to read data from the PPI. A, Ao CS RD WR 0 0 0 0 1 Data bus - Port A Operation 0 1 0 0 1 Data bus - Port B WR (Write) Input 1 0 0 0 1 Data bus - Port C At low-level, the data or control words are transferred from the CPU and written in the PPI. 0 0 0 1 0 Port A - Data bus 0 1 0 1 0 Port B - Data bus 1 0 0 1 0 Port C - Data bus 1 1 0 1 0 Cont~ol X X 1 X X Data bus is in high-impedance state 1 1 0 0 1 illegal condition Ao, A, (Port address) Input These input signals are used to select one of the three ports: port A, port B, and port C, or the control register. They are normally connected to the least significant two bits of the address bus. RESET (Reset) Input At high-level, the control register is cleared. Then all ports are set to the input mode (high-impedance state). CS (Chip-Select) Input At loW-level, the communication between the PPI and the CPU is enabled. While at high-level, the data busis kept in the high-impedance state, so that commands from the CPU are ignored. Then the previous data is kept at the output port. f---- register - Data bus Where, "0" indicates low level "1" indicates high-level Bit Set/Reset When port C is used as an output port, anyone bit of the eight bits can be set (high) or reset (low) by a control word from the CPU. This bit set/reset can be operated in the same way as the mode set, but the control word format is different. This operation is also used for INTE set/reset in mode 1 and mode 2 . Read/Write Control Logic The function of this block is to control transfers of both data and control words. It accepts the address signals (Ao, A" CS), I/O control signals (RD, WR) and RESET signal, and then issues commands to both of the control groups in the PPI. Bit set/reset flag I Active - Bit selection code Data Bus Buffer Port C Bit selected This three-state, bidirectional, eight-bit buffer is used to transfer the data when an input or output instruction is executed by the CPU. Control words and status information are also transferred through the data bus buffer. D, D, D, PC, 1 1 1 1 0 0 0 0 PC, PC5 PC, Group A and Group B Control PC, Accepting commands from the read/write control logic, the control blocks (Group A, Group B) receive 8-bit control words from the internal data bus and issue the proper commands for the associated ports. Control group A is associated with port A and the four high-order bits of port C. Control group B is associated with port B and the four low-order bits of port C. The control register, which stores control words, can only be written into. PC, PC, PCa 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 ,set/reset code Set (high) ID71D61D51D41031D21D,iDoi Fig. 1 Port A, Port B and Port C The PPI contains three 8-bit ports whose modes and input! output settings are programmed by th·e system software. Port A has an output latch/buffer and an input latch. Port B has an I/O latch/buffer and an input buffer. Port C has an output latch/buffer and an input buffer. Port C can be divided into two 4-bit ports which can be used as ports for control signals for port A and port B. The basic operations are shown in Table 1. 5-74 I a Don't care • MITSUBISHI ..... ELECTRIC - 1 Reset (low) = 0 J Control word format for port C set/reset MITSUBISHI LSls MSM82CSSAP-S CMOS PROGRAMMABLE PERIPHERAL INTERFACE BASIC OPERATING MODES The PPI can operate in anyone modes. Mode 0: Basic input/output Mode 1: Strobed input/output Mode 2: Bidirectional bus The mode of both group A and independently. The control word shown in Fig. 2. of three selected basic (group A, group B) (group A, group B) (group A only) group B can be selected format for mode set is PA,-PAo 0, 0, 050, 03 0, 0, Do 11101010101011101 07 06 05 04 03 02 0, Do 111 01010101011111 r - - - - - - - - Mode set flag 1Active PA,-PAo - 1 , - - - - - - - Group A mode set 0: 0" 0, 0 7 06 Os 04 03 02 D, Do 111 01010111 010101 0, 0 Mode ~ Mode 1: 0,. 0, ~ 0, 1 Mode 2: 0" 0, ~ 1, X 07 06 D5 0 4 03 D2 0, Do 111 01010111010llj ,..-_ _ _ _ Port A input/output set I output - 0 _ rnput ~ 1 ~ _ __ Port C (high-order four bits) input/output set I~utput _ rnput ~ ,.---'-.., I I I 10,10,10510,10310" 0,[001 - 0 ~ 1 I PAr-PAo 07 06 Os 04 03 02 01 Do _ 11101010111011101 1. 11 Port B input/output set Port C (low-order four brts) rnput/output set output - 0 input ~ I 1 I 07 06 0 5 04 03 02 0, Do Fig_ 2 0, 0, 05 0, 030, 0, Do 11101010111011llj 11101011101010101 Control word format for mode set. 07 0605 0 4 D3 D2 0, Do 11101011101010lq Mode 0 (Basic Input/Output) This functional configuration provides simple input and output operations for each of the three ports. No "handshaking" is required; data is simply written in, or read from, the specified port. Output data from the CPU to the port can be held, but input data from the port to the CPU cannot be held. Any one of the 8-bit ports and 4-bit ports can be used as an input port or an output port. The diagrams following show the baSic input/output operating modes. PAl-PAD 0 7 0 6 05 0 4 0 3 D2 01 Do 11 I 010111 0I 011 I 11 0, 0, 050, 03 O 0, Do 11101011111010101 0, 06 0, 0, 03 0, 0, Do 111010111110101 n 2 07 06 05 04 03 02 D1 Do 11101010101010101 0, 0, 05 0, 03 0, Dr Do 111010101010101 lj 0 7 06 0 5 0 4 03 D2 0, Do 11101011101011101 07 06 05 04 03 02 01 Do 11 I01011 11 I011 10 I • MITSUBISHI .... ELECTRIC 0, 0, 0, 0, 030, 0, Do 111010111110111 q 5-75 MITSUBISHI LSls MSM82CSSAP-S CMOS PROGRAMMABLE PERIPHERAL INTERFACE 2. Mode 1 (Strobed Input/Output) This function can be set in both group A and B. Both groups are composed of one 8-bit data port and one 4-bit control data port. The 8-bit port can be used as an input port or an output port. The 4-bit port is used for control and status signals affecting the 8-bit data port. The following shows operations in mode 1 for using input ports. ISF STB (Strobe Input) A low-level on this input latches the output data from the terminal units into the input register of the port. In short, this is a clock for data latching. The data from the terminal units can be latched by the PPI independent of the control signal from the CPU. This data is not sent to the data bus until the instruction I N is executed. IBF (Input Buffer Full Flag Output) A high-level on this output indicates that the data from the terminal units has been latched into the input register. IBF is set to high-level by the falling edge of the STB input, and is reset to low-level by the rising edge of the RD input. INTR (Interrupt Request Output) This can be used to interrupt the CPU when an input device is requesting service. When INTE (interrupt enable flag) of the PPI is high-level, INTR is set to high-level by the rising edge of the STB input and is reset to lOW-level by the falling edge of RD input. INTEA of group A is controlled by bit setting of PC 4 . INTEB of group B is controlled by bit setting of PC2. Mode 1 input state is shown in Fig. 3, and the timing chart is shown in Fig. 4. RD ---r----1-----------~ INTR PORT _-+__--1 _________-+::=~==: --+------_/ INPUT :=t;;:A==~=====t===+=== LATCH 00-0, Note 1 Fig. 4 OBF (Output Buffer Full Flag Output) This is reset to low-level by the rising edge of the WR signal and is set to high-level by the falling edge of the ACK (acknowledge input). In essence, the PPI indicates to the terminal units by the OBF signal that the CPU has sent data to the port. STS B ISF B INTRB CONTROL WORD RD CONTROL WORD 07 0 6 05 0, 0, 0, 0, Do 111xlxlxixll111xl Fig. 3 5-76 (Acknowledge Input) INTR (Interrupt Request) 8 1/0 Timing chart Receiving this signal from a terminal unit can indicate to the PPI that the terminal unit has accepted data from a port. MODE 1 (PORT S) 8 When INTE is low-level. INTR is always lOW-level. The following shows operations using mode 1 for output ports. ACI< MODE 1 (PORT A) ------~L~ When a peripheral unit is accepting data from the CPU, seting INTR to high-level can be used to interrupt the CPU. When INTE (interrupt enable flag) is high and OBI" is set to high-level by the rising edge of an ACK signal, then INTR will also be set to high-level by the rising edge of the ACK signal. Also, INTR is reset to lOW-level by the falling edge of the WR signal when the PPI has been receiving data from the CPU. I NTEA of group A is controlled by bit setting of PC6. I NTEB of group B is controlled by bit setting of PC2. Mode 1 output state is shown in Fig. 5, and the timing chart is shown in Fig. 6. Combinations for using port A and port B as input or output in mode 1 are shown in Fig. 7 and Fig. 8. An example of mode 1 input state • MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSM82CSSAP·S CMOS PROGRAMMABLE PERIPHERAL INTERFACE MODE 1 (PORT B) OBFs !lCKs INTRs OBF--+---" ACK--~~---~----~ INTR CONTROL WORD CONTROL WORD 0, 06 05 04 03 02 0, Do '-_-+_________--' (Note 2) PORT----~r_-----------­ OUTPUT-----~~------------- Illxlxlxl xillolxl Note 2: O=OUTPUT Fig. 5 Mode 1 output example PORT A (STROBED OUTPUT) PORT B (STROBED INPUT) Fig. 6 Timing diagram PC, IBFs PCa INTRs PORT A (STROBED INPUT) PORT B (STROBED OUTPUT) PCa CONTROL WORD CONTROL WORD O=OUTPUT Fig. 7 When INTE is low-level. then the output of INTR is aways low-level. Mode 1 port A and port B lID example O=OUTPUT Fig. 8 • MITSUBISHI .... ELECTRIC Mode 1 port A and port B lID example 5-77 MITSUBISHI LSls MSM82CSSAP-S CMOS PROGRAMMABLE PERIPHERAL INTERFACE 3. Mode 2 (Strobed Bidirectional Bus Input! Output) Mode 2 can provide bidirectional operations, using one 8-bit bus for communicating with terminal units. Mode 2 is only valid with group A and uses one 8-bit bidirectional bus port (port A) and a 5-bit control port (high-order five bits of port C). The bus port (port A) has two internal registers, one for input and the other for output. On the other hand, the control port (port C) is used for communicating control signals and bus-status signals. These control signals are similar to mode 1 and can also be used to control inte,rruption of the CPU. When group A is programmed as mode 2, group B can be programmed independently as mode or mode 1. When group A is in mode 2, the following five control signals can be used. a IBF OSF (Output Buffer Full Flag Output) The OBF output will go low-level to indicate that the CPU has sent data to the internal register of port A. This signal lets the terminal units know that the data is ready for transfer from the CPU. When this occurs, port A remains in the floating (high-impedance) state. ACK (Acknowledge Input) DATA FROM TERMINAL UNIT PORT A Fig, 9 DATA FROM CPU ------~C==~<=:::::~--- Mode 2 timing diagram Note 3: INTR=IBF' MASK, STB' FlD + OBF' MASK' ACK' WR A lOW-level ACK input will cause the data of the internal reg- ister to be transferred to port A. For a high-level ACK input, the output buffer will be in the floating (high-impedance) state. RD WR STB (Strobe Input) When the STB input is low-level, the data from terminal units will be held in the internal register, and the data will be sent to the system data bus with an RD signal to the PPI. IBF (Input Buffer Full Flag Output) When data from terminal units is held on the internal register, IBF will be high level. INTR (Interrupt Request Output) This output is used to interrupt the CPU and its operations the same as in mode 1. There are two interrupt enable flags that correspond to INTEA for mode 1 output and mode 1 input. INTEl is used in generating INTR signals in combination with OBF and ACK. INTEl is controlled by bit setting of PC6. INTE2 is used in generating INTR signals in combination with IBF and STB. INTE2 is controlled by bit setting of PC4. Fig. 9 shows the timing diagram of mode 2, and Fig. 10 is an example of mode 2 operation. 1/0 IBFA STB A CONTROL WORD ACK A OBF A 1/0 INTRA PC2~PCO 1 =INPUT o =OUTPUT L-._ _ _ PORT B 1 =INPUT o=OUTPUT L--_ _ _ _~ GROUP B MODE O=MODEO 1 =MODE 1 Fig. 10 5-78 • MITSUBISHI .... ELECTRIC An example of mode 2 operation MITSUBISHI LSls MSM82CSSAP-S CMOS PROGRAMMABLE PERIPHERAL INTERFACE 4. Control Signal Read Table In mode 1 or mode 2 when using port C as a control port, by CPU execution of an IN instruction, each control signal and bus status from port C can be read. Mode Mode 1, input .control word formats and operation details for mode 0, mode 1, mode 2 and set/reset control of port C are given in Tables 3, 4, 5 and 6, respectively. Table 3 Read-out control signals A Control Word Tables 5. 2 D7 D6 1/0 1/0 D3 D2 D, Do IBFA INTEA INTRA INTEB IBFB INTRB Mode 1. output OBFA INTEA Mode 2 D, D5 1/0 INTRA INTEB OBFB INTRB 1/0 IBFA INTE2 INTRA OBFA INTE, By group B mode Mode 0 control words 1---- Control words J~ Group A Group B r._D-,-~~._~D-,_~~~_~~~2"~~d~~aI _ Port A~= Por~~;;;;;;-4b,;;! -~CU~;;;~~P~B1 a a a a a a a 80 OUT OUT OUT OUT 1"-.--..- - - - - - -------------'r--.-----a a a a a a 81 OUT OUT IN OUT 1---r----- - - - .-f--- ----------I a a a a a 1 a...- - t--- .---82 OUT OUT OUT IN - - " " - - - . - - - - - - -.. .. IN 1 a a..- a -a- a -1-.. 1 83 OUT OUT IN f------.------.--.--"". r---- --------OUT a a a 1 a a a 88 OUT IN OUT 1 - - - - - - - - - - - - . - - - - ""-- - - - - - - t-------------I------~a a a 1 a a 1 89 OUT IN IN OUT ---~ --.-.--.--.--~---- ---~- ---~--_r-----~ ~------- --~- -~----------t--~--- f-----a-~a·----~- o-1--a---t8-A---0l;T-~IN ------~+-----O-U-T----+----IN-- - - _ . _ - - - - - - - - - - - + - - - - j - - - - - - - + - - - - - - - - - + - - - - - - - - - - - - - ---~------ a a a a 8B OUT IN IN ---~------~--------- IN ~--------- a a a a 90 IN OUT OUT OUT I----------------+----~-----t_---------+_-------~-------a a a 91 IN OUT IN OUT a a a a 92 IN OUT OUT IN I--------------~-+--~----------.--.-----------------+---a 1 a a 1 1 93 IN OUT IN IN I - - - - - - -..- -..-~----_+_- - ----.~--.. -.---.------------~-+_----__l a 1 1 a a a 98 IN IN OUT OUT . IN IN OUT a a a a 99 IN ..- - - -----+-------+-----------------_.._- ._-- ------ - - - - - - a a a a 9A IN IN OUT IN .. -1----IN a a a 9B IN IN IN -------------r-~---+_------+_----------+_---------- ~- ~.- ~- ----~- Note 4: OUT indicates output port, and IN indicates input port. Table 4 Mode 1 control words Control words 07 06 05 ----..-~ I' 04 03 02 01 I 1 a a 1 1 a a 1 a x t A4 OUT a 1 a 1 1 a x 1 1 1 X OBFA I a 1 1 a 1 1 1 1 1 a x 1 I I I AC AD a 1 I OUT PC3 INTRA ~--.--- -OBFA --ACKA I OUT INTRA - - OUT OBFA OBFA I PortB PC;'-I- PC~ _ _ _ _ PC2 --,-AC~FB STBB I IN INTRA A<5Ks ACKA IN INTRA -STBB IBFB 1 ~- OElFs IBFB i Note 5: 6: a 1 1 1 B4 1 INTRB INTRB IN ----~ OUT IN -- -- - - - - IBFA STBALTRA ACKB OBFB INTRB OUT IN OUT IBFA STB A ·1 INTRA -STBB IBFB INTRB IN IN IN IBFA STB A INTRB OUT i BC BD BE X OUT OUT IN B5 B7 1 INTRB f----- f----- II~TRA - - ACKB -OBFB ~- I INTRB --f---- 1---. -ACKA B6 a x -,- '-~ I - -- - - - AE OUT AF X -- I ACK A Group B _. Port C PC7 PC. PC6 PC5 1---.. .. '~G -_.- ~- a 1 1 a .------~-- porte ~- ~- a 1 a Group A L - - - - - - - - - -A5 --I A6 a a 1 1 X GA7O U T ._-_.. I PortA decimal ~~- 1 Hexa- ' Do -- I -.-----~-- -- IN IN BF IBFA STBA I-~ - - INTRA STB B IBFB INTRB IN Mode of group A and group B can be programmed independently. It is not necessary for both group A and group B to be in mode 1. • MITSUBISHI "ELECTRIC 5-79 II MITSUBISHI LSls MSM82CSSAP-S CMOS PROGRAMMABLE PERIPHERAL INTERFACE Table 5 Mode 2 control words Group A Control words D7 D, Ds D, D, D2 D, Do 1 1 X X X 1 1 X X X 1 1 X X X 1 1 X X X 1 1 X X X a a a a a 1 a 1 a a 1 1 1 a X 1 1 X X X 1 Table 6 1 X Group B Port C Hexadecimal Port A co Bidirectional C1 Bidirectional C2 (Ex) PortC Port B PC7 PC6 PCs PC. PC, OBF A ACK A IBFA STBA INTRA OUT OUT bus OBFA ACK A IBFA STBA INTRA IN OUT Bidirectional bus OBFA ACK A IBFA STBA INTRA OUT IN C3 Bidirectional bus OBFA ACK A IBFA STB A INTRA IN IN C4 Bidirectional bus OBFA ACK A IBFA STBA INTRA ACK B [ OBFB [INTRB OUT C6 Bidirectional OBFA ACK A IBFA STB A INTRA STBB bus bus PC2 I PC, I PCa I IBFB I INTRB Port C set/reset control words Port C Control words D7 D, D5 D, D, D2 D, a X X a x x a X X a x X a X X a X X Do Hexadecimal PC7 PC6 PCs PC, Remarks PC, PC2 PC, PCa a a a a a 1 a 1 a a 1 1 1 a a 00 X a a a a a 04 a INTEs set/reset for mode 1 input X 0 1 0 1 05 1 INTEs set/reset for mode 1 output 1 1 0 06 X X X X a 1 01 - a 02 03 1 0 X X X 0 a a X X X 0 1 1 1 07 X X X 1 0 0 0 08 0 INTEA set/reset for mode 1 input 0 X X X 1 0 0 1 09 1 INTE2 set/reset for mode 2 0 X X X 1 0 1 0 OA 0 X X X 1 a 1 1 OB 0 X X X 1 1 a a OC 0 INTEA set/reset for mode 1. output 0 X X X 1 1 0 1 00 1 INTEl set/reset for mode 2 0 X X X 1 1 1 0 OE 0 0 X X X 1 1 1 1 OF 1 Note 7: 8: 5-80 0 1 a 1 -- The terminais of port C should be programmed for the output mode, before the bit set/reset operation is executed. Also used lor controlling the interrupt enabie Ilag(INTE) •. MITSUBISHI ...... ELECTRIC IN MITSUBISHI LSls MSM82CSSAP-S CMOS PROGRAMMABLE PERIPHERAL INTERFACE ABSOLUTE MAXIMUM RATINGS Symbol 1----Vee ~-- Parameter Conditions -- - - - Unit -V Limits Supply voltage -0.3-7 --- V, Input voltage Va Output voltage T opr Operating free-air temperature range Tstg Storage temperature range -0. 3-Vee+0. 3 With respect to GND V ,-- ---~ -- RECOMMENDED OPERATING CONDITIONS Symbol Parameter -- Vee Supply voltage GND Supply voltage -~ V -20-75 'C -65-150 'C (T a =-20-75'C, unless otherwise noted) Limits -,----Min Nom 4.5 ---- ,--~ 5 I---~ Unit Max 5.5 V V 0 ELECTRICAL CHARACTERISTICS -0. 3-Vee+0. 3 (T a =-20-75'C, Vee=5V±10%, GND=OV, unless otherwise noted) Limits Symbol Parameter Test conditions Unit ~==Vv=',HL=====:~=H=i9=h=-I=e=ve=l=in=p=u=t=v=ol=ta=g=e======================:===============--,_-~~~_-,-_~===-_-_=- r-.:._M_20·_.i:3-+--T-y-P-+V--=C~0;.~80.3 -~--Vv~·~l- __ Low-level input voltage ~----'+-:-~-::-~-:-~o-i:-h-v:-~t-1:-:9-:---=(-N-o_t-e~'_o~)~~~-~~~__~-__-~=_=_=-__~~_J_>_:_~=_;~-,-:_:-_~-A_,,_A--~~=_-_-=-_-_-_-=~-~-------==-+t------2=.-4----++------------_~f--_-O-.-,~-__ 5-- ~_--_-~ __ _ lee I GND=OV, All input mode, RESET=OV, Other pins=Vce, Supply current from Vee 1----+---------------------------+-------------- 'a /-lA ------ ----+----+-------- I'L Input leak current GND=OV, V,=OV, Vee ±10 ___~ loz Off-state output current GND=OV, VI=O--VCC ±10 J-lA Cilo Input/output terminal capacitance VIIOL=GND, f=1 MHz, 25mVrms, T a=25"C 20 pF I - - - = - = - - + - - - - - - - = - - - - - - - - - - - - - - f - - ---------------+---+-----+--------------~-----_t-I-np-u-t-e-a-p-ac-i-ta-n-c-e--,-----------__+_V,L_=_G_N_D:f,",,' M~z:25m~r_m:!~=_25_o_C__ ___________ ~_~_ Note 9 Current flowing into an IC is positive, out is negative. 10: IOH current must be less than -4mA for each Port pin. TIMING REQUIREMENTS (T a =-20-75'C, Vcc=5V±10%, GND=OV, unless otherwise noted) Alternative Symbol Parameter Limits Test conditions symbol Min Unit Max 300 [200) tWCR) Read pulse width tSUCPE~R) Peripheral setup time before read t'R a the R~PE) Peripheral hold time after read tHR 0 tSU(A-R) Address setup time before read tAR a th(R-A) Address hold time after read tRA 0 tw.01 As 06 Os I I I LTIM 0, 04 ADI SNGL I IC4 I 0, 0, Do J (Note 1) J 1 Note I I I SINGLE CASCADE MODE JI: ICW4 NEEDED 0: NO ICW4 NEEDED I I 8085A ONLY ICW1 .1 VECTOR ADDRESS HIGH-ORDER BITS I (A15- A8)OR INTERRUPT TYPE (T,-T,) I I I I I A15/T71 A14/T61 A13/Tsl A12/T41 Ao 07 06 04 Os AI1IT, AlO Ag 0, 0, 0, I I A8 I Do ICW2 II I I I Ao I S7 0, IRn INPUT HAS A SLAVE IRn INPUT DOES NOT HAVE A SLAVE LO I S6 I I Ss I Os 06 S4 04 I S, s, s, 0, 0, 0, I I So Do I SLAVE IDENTIFICATION CODE ICW3 (MASTER DEVICE) 0 0 0 0 II I AD I 0 0, I o I 06 o Os I o 04 I 0 102 0, 0, I 10, 0, I I 100 I 2 3 4 5 6 0 0 0 I I I 0 I I 0 0 I I 0 I 0 I 0 7 I I I J Do ICW3 (SLAVE DEVICE) JI: SPECIAL FULLY NESTED MODE LO 0 X NON BUFFERED MODE I 0 BUFFERED MODE/SLAVE I 1 BUFFERED MODE/MASTER NOT SPECIAL FULLY NESTED MODE J 1: L0: J I: 10: I I Ao I 0 0, I 0 06 I 0 Os I SFNM I BUF 04 0, I M/S 0, I AEOI I ,uPM I 0, Do ICW4 Fig. 3 5-92 Initialization command word format • MITSUBISHI .... ELECTRIC AEOI MODE NORMAL EOI MODE 8086, 8088 MODE 8085A MODE MITSUBISHI LSls MSM82CS9AP CMOS PROGRAMMABLE INTERRUPT CONTROLLER =0 in ICW4. In the slave mode, three bits 102~IOD identify the slave. And then when the slave code released on the cascade lines from the master, matches the assigned 10 code, the vectored address is released by it onto the data bus at the next INTA pulse. M5M82C59AP, the device is ready to accept interrupt requests. There are three types of OCW s; explanation of each follows, and the format of oews is shown in Fig. 4. OCW1 The meaning of the bits of OCWl are explained in Fig. 4 along with their functions. Each bit of 1M R can be independently changed (set or reset) by OeWl. ICW4 Only when IC4 = 1 in ICWl is ICW4 valid. Otherwise all bits are set to zero. When ICW4 is valid it specifies special fully nested mode, buffer mode master/slave, automatic EOI and microprocessor mode. The format of ICW4 is shown in Fig. 3. OCW2 The OeW2 is used for issuing EOI commands to the M5M82C59AP and for changing the priority of the interrupt request inputs. Operation Command Words (OCWs ) OCW3 The operation command words are used to change the contents of IMR, the priority of interrupt request inputs and the special mask. After the ICW are programmed into the The OeW3 is used for specifying special mask mode, poll mode and status register read. , - - - - - - - - . - - , - - - - - - - , - - - , - - - r - - , - - - - - , - - - - - - - - f 1: INTERRUPT MASK SET INTERRUPT MASK RESET 0: OCW1 0 0 1 NON-SPECIFIC EOI 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 0 1 0 0 ROTATE ON NON-SPECIFIC EOI SETS AUTOMATIC ROTATION FLIP-FLOP } AUTOMATIC ROTATION RESET AUTOMATIC ROTATION FLIP-FLOP ROTATE ON SPECIFIC EOI (RESETS ISR BIT L2-Lol 0 I R I SL } SPECIFIC ROTATION SETS PRIORITY COMMAND (SET LOWEST PRIORITY BIT L2-Loi NO OPERATION ~ I IB } EOI SPECIFIC EOI (RESETS ISR BITS L,-Lol ID LEVEL TO BE ACTED UPON EOI Ao I 0 I 0 I L, I I L, 0 1 2 3 4 5 6 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 I 0 1 0 1 0 I I Lo 7 1 1 1 I Do 05 OCW2 0 1 X NO OPERATION 0 RESET SPECIAL MASK MODE 1 1 SETS SPECIAL MASK MODE 11 I0 0 1 1 I 0 Ao I 0 ESMM I SMM I D, D5 0 I 1 D3 I I P D2 I RR D, I POLL COMMAND NO POLL COMMAND X NO OPERATION 0 SETS STATUS READ REGISTER IN IRR 1 SETS STATUS READ REGISTER IN ISR I RIS I Do OCW3 Fig. 4 Operation command word format • MITSUBISHI ..... ELECTRIC 5-93 MITSUBISHI LSls MSM82CS9AP CMOS PROGRAMMABLE INTERRUPT CONTROLLER FUNCTION OF COMMAND Interrupt masks The mask register contains a mask for each individual interrupt request. These interrupt masks can be changed by programming using OCWl. Special mask mode When an interrupt request is acknowledged and the ISR bit corresponding to the interrupt request is not reset by EOI command (which means an interrupt service routine is executing) lower priority interrupt requests are ignored. In special mask mode interrupt requests received at interrupt request inputs which are masked by OCWI are disabled, but interrupts at all levels that are not masked are possible. This means that in the mask mode all level of interrupts are possible or individual inputs can be selectively programmed so all interrupts at the selected inputs are disabled. The masks are stored in IMR and special mask is set/reset by executing OCW3. 2. When an interrupt from a certain slave is being serviced the software must check ISR to determine if there are additional interrupts requests to be serviced. If the ISR bit is 0 the EOI command may be sent to the master too. But if it is not 0 the EOI command should not be sent to the master. Poll mode The poll mode is useful when the internal enable flip-flop of the microprocessor is reset, and interrupt input is disabled. Service to the device is a.chieved by a programmer initiative using a poll command. In the poll mode the M5M82C59AP at the next RD pulse puts 8 bits on the data bus which indicates whether there is an interrupt request and reads the priority level. The format of the information on the data bus is as shown below. Buffered mode Binary code of the highest priority The buffered mode will structure the M5M82C59AP to send an enable signal on SP/EN to enable the data bus buffer, when the data bus requires the data bus buffer or when cascading mode is used. In this mode, when data bus output of the M5M82C59AP is enabled, the SP/EN output becomes low-level. This allows the M5M82C59AP to be programmed whether it is a master or a slave by software. The buffered mode is set/reset by executing ICW4. Fully nested mode The fully ne.sted mode is the mode when no mode is specified and is the usual operational mode. In this mode, the priority of interrupt request terminals is fixed from the lowest IR7 to the highest IR o. When an interrupt request is acknowledged the CALL instruction and vectored address are released onto the data b'Js. At the same time the ISR bit corresponding to the accepted interrupt request is set. This ISR bit remains set until it is reset by the input of an EOI command or until the trailing edge of last INTA pulse in AEOI mode. While an interrupt service routine is being executed, interrupt requests of same or lower priority are disabled while the bit of ISR remains set. The priorities can be changed by OCW2. Special fully nested mode The special fully nested mode will be used when cascading is used and this mode will be programmed to the master by ICW4. The special fully nested mode is the same as the fully nested mode with the following two exceptions. 1. When an interrupt from a certain slave is being serviced. this slave is not locked out from the master priority logic. Higher priority interrupts within the slave will be recognized by the master and the master will initiate an interrupt request to the CPU. In general in the normal fully nested mode, a serviced slave is locked out from the master's priority, and so higher priority interrupts from the same slave are not serviced. 5-94 D, When 1=0 (no interrupt request), W2-WO is 111. The poll is valid from WR to RD and interrupt is frozen. This mode can be used for processing common service routines for interrupts from more than one line and does not require any INTA sequence. Poll command is issued by setting P= 1 in OCW3. End of interrupt (EO I) and specific EOI (SEOI) An EOI command is required by the M5M82C59AP to reset the ISR bit. So an EOI command must be issued to the M5M82C59AP before returning from an interrupt service routine. When AEOI is selected in ICW4, the ISR bit can be reset at the trailing edge of the last INTA pulse. When AEOI is not selected the ISR bit is reset by the EOI command issued to the M5M82C59AP before returning from an interrupt service routine. When programmed in the cascade mode the EOI command must be issued to the master once and to corresponding slave once. There are two forms of EOI command, specific EOI and non-specific EOL When the M5M82C59AP is used in the fully nested mode, the ISR bit being serviced is reset by the EOI command. When the non-specific EOI is issued the M5M82C59AP will automatically reset the highest ISR bit of those that are set. Other ISR bits are reset by a specific EOI and the bit to be reset is specified in the EOI by the program. The SEOI is useful in modes other than fully nested mode. When the M5M82C59AP is in special mask mode ISR bits masked in IMR are not reset by EOL EOI and SEOI are selected when OCW2 is executed. • MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSM82CS9AP CMOS PROGRAMMABLE INTERRUPT CONTROLLER Automatic EOI (AEOI) In the AEOI mode the M5M82C59AP executes non-specific EOI command automatically at the trailing edge of the last INTA pulse. When AEOI=l in ICW4, the M5M82C59AP is put in AEOI mode continuously until reprogrammed in ICW4. Automatic rotation The automatic rotation mode is used in applications where many interrupt requests of the same level are expected such as multichannel communication systems. In this mode when an interrupt request is serviced. that request is assigned the lowest priority so that if there are other interrupt requests they will have higher priorities. This means that the next request on the interrupt request being serviced must wait until the other interrupt requests are serviced (worst case is waiting for all 7 of the other controllers to be serviced) . The priority and serving status are rotated as shown in Fig. 5. BEFORE ROTATION (IR3 THE HIGHEST PRIORITY REQUIRING SERVICE) IS 7 ISR STATUS Is,; a I HIGHEST PRIORITY i I AFTER ROTATION (IR3 WAS SERVICED AND ALL OTHER PRIORITIES ROTATED CORRESPONDINGLY) ~ ISR STATUS a ~ I I 1& I~ I~ I~ 1& I~ LOWEST PRIORITY PRIORITY STATUS Fig. 5 Level triggered mode/Edge triggered mode Selection of level or edge triggered mode of the M5M82C59AP is made by ICW1, When using edge triggered mode not only is a transition from low to high required, but the high-level must be held until the first INTA. If the highlevel is not held until the first INTA, the interrupt request will be treated as if it were input on IR7, except that the ISR bit is not set. When level triggered mode is used the functions are the same as edge triggered mode except that the transition from low to high is not required to trigger the interrupt request. In the level triggered mode and using AEOI mode together, if the high-level is held too long the interrupt will occur immediately. To avoid this situation interrupts should be kept disabled until the end of the service routine or until the IR input returns low. In the edge. triggered mode this type of mistake is not possible because the interrupt request is edge triggered. Reading the M5M82C59AP internal status IS, LOWEST PRIORITY PRIORITY STATUS lowest or highest priority. Priority changes can be executed during an EOI command. ! An example of priority rotation In the non-specific EOI command automatic rotation mode is selected when R=l, EOI=l, SL=O in OCW2. The internal priority status is changed by EOI or AEOI commands. The rotation priority A flip-flop is set by R=l, EOI=O and SL=O which is useful when the M5M82C59AP is used in the AEOI mode. Specific rotation Specific rotation gives the user versatile capabilities in interrupt controlled operations. It serves in those applications in wh,ich a specific device's interrupt priority must be altered. As opposed to automatic rotation which automatically sets priorities, specific rotation is completely user controlled. That is, the user selects the interrupt level that is to receive The contents of IRR and ISR can be read by the CPU with status read. When an OCW3 is issued to the M5M82C59AP and an RD pulse issued the contents of IRR or ISR can be released onto the data bus. A special command is not required to read the contents of IMR. The contents of IMR can be released onto the data bus by issuing an RD pulse when Ao = 1. There is no need to issue a read register command every time the IRR or ISR is to be read. Once a read register command is received by the M5M82C59AP, it remains valid until it is changed. Remember that the programmer must issue a poll command every time to check whether there is an interrupt request and read the priority level. Polling overrides status read when P=l, RR=l in OCW3. Cascading The M5M82C59AP can be interconnected in a system of one master with up to eight slaves to handle up to 64 priority levels. A system of three units that can be used with the 8085A is shown in Fig. 6. The master can select a slave by outputting its identification code through the three cascade lines. The INT output of each slave is connected to the master interrupt request inputs. When an interrupt request of one of the slaves is to be serviced the master outputs the identification code of the slave through the cascade lines, so the slave will release the vectored address on the next INTA pulse. The cascade lines of the master are nomally low, and will contain the slave identification code from the leading edge of the first INTA pulse to the trailing edge of the last INTA pulse. The master and slave can be programmed to work in different modes. ICWs must be issued for each device, and EOI commands must be issued twice: once for the master and once for the corresponding slave. Each CS of the M5M82C59AP requires an address decoder. • MITSUBISHI ;"ELECTRIC 5-95 II MITSUBISHI LSls MSM82CS9AP CMOS PROGRAMMABLE INTERRUPT CONTROLLER 16 ADDRESS BUS CONTROL BUS DATA BUS 8 3 3 3 8 8 cs 8 I INT Ao M5M82C59AP MASTER CS 1 CASo CAS, i Vee 7 6 lcs INT CAS, ! 1l3! r ! I INT Ao CASo CASo SP/EN M, M, M5 M, M, M, M,Mo I Ao CAS, CAS, M5M82C59AP SLAVE SP/EN 7 6 ~ ----- 3 5 4 2 1 0 SP/EN tl!!tl!! GrD CAS, CAS, GlD M5M82C59AP SLAVE 765 4 3 2 1 0 ~!ll!!r! ~------------------------------~y~--------------------------------~-- INTERRUPT REQUEST INPUTS Fig. 6 Cascading the M5M82C59AP DEN DATA BUS ADDRESS BUS Do -D, (Note 1) ADo- AD, RD OR-I ORC WRORroWC INTA M/TO 8 Do-D, ~ Ao Ao A, A, A, A5 I ,.. ....... ...... y y .... .Joo.. ... .... A" A, - II RB cs = M,"""~[ - - Fig. 7 5-96 OE TO BUS BUFFER iNfA :;:: :;:: <.n REQUEST INPUTS Note 1: 5v WR SP/EN LS30 )0---< INTR INT CD -~ '"0<.n IRo ." IR, IR, IR, IR5 IR, IR, Do-D, of the M5M82C59AP are direct connected with ADo-AD, of the 8086. Example of interface with the 8086 • MITSUBISHI ..... ELECTRIC MITSUBISHI LSls MSM82CS9AP CMOS PROGRAMMABLE INTERRUPT CONTROLLER INSTRUCTION SET Item ~ Instruction code Mnemonic Function Ao 07 06 Os 0, 03 O2 0, A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 As As As As 0 0 0 0 As As As As 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Do ICW4 required? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ICW1 ICWI ICWI ICWI ICWI ICWI ICWI ICWI ICWI ICWI ICWI ICWI ICWI ICWI ICWI ICWI A B C 0 E F G H I J K L M N 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 a a A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 17 18 19 ICW2 ICW3 M ICW38 1 1 1 A,s 87 0 A,4 86 0 A13 8s 0 A,2 84 0 A" 83 0 AlO 82 102 Ag 8, 10, As 80 100 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 ICW4 A ICW4 B ICW4 C ICW4D ICW4 E ICW4 F ICW4 G ICW4 H ICW4 I ICW4 J ICW4 K ICW4 L ICW4 M ICW4 N ICW40 ICW4 P ICW4 NA ICW4 NB ICW4 NC ICW4 NO ICW4 NE ICW4 NF ICW4 NG ICW4 NH ICW4 NI ICW4 NJ ICW4 NK ICW4 NL ICW4 NM ICW4 NN ICW4 NO ICW4 NP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 a a a a a a a a a 0 a 0 0 0 a 0 a 0 a a a a a 0 0 1 52 53 54 55 56 57 58 59 60 61 62 63 OCWI OCW2 E OCW28E OCW2 RE OCW2 R8E OCW2 R OCW2 CR OCW2 R8 OCW3 P OCW3 RI8 OCW3 RR OCW38M OCW3 RSM 1 0 64 Note: 0 a a a 0 a a 0 a 0 a a a 0 a a a 0 0 a 0 a a a a a a a a a a 0 a a 0 a a a a a a a a a a a 0 a a a a a 0 a a a a a 0 0 0 0 0 0 0 a 0 0 0 0 0 0 0 0 0 0 0 a a a a a M7 0 0 1 1 1 M6 0 1 0 0 a 1 a a 1 a a a 0 1 1 a 1 a a a a a a a a a a a a a a a 0 a 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 a 1 1 1 1 1 1 1 1 a a a 0 1 1 1 1 a a a a 1 1 1 1 0 a a a 1 1 1 1 a 1 1 a a 1 1 a a 1 1 0 a 1 1 a 1 0 1 a 1 a 1 a 1 0 1 a 1 a 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a 0 a a a 0 a a 1 1 1 1 1 1 1 1 a 0 a 0 1 1 1 1 a 1 1 a M4 M3 M2 M, Mo L2 0 L2 L, La 0 La 0 0 L2 1 0 L, 0 1 1 a a 0 a a a a 0 0 0 0 a Ms 1 1 1 1 0 0 a a 0 0 a 1 a a a a a a a a a a a 0 a a 0 a 0 0 0 a 1 1 1 1 1 a a 0 a 1 1 1 1 a a a a 0 a a a 1 1 a a 1 1 a a 1 1 0 a a L, a a a 1 0 1 a 1 0 1 a I 1 a Intervel Single Trigger N N N N N N N N 4 4 4 4 8 8 8 8 Y Y Y y y y y y y y 4 4 4 8 8 8 8 E L E L E L E L E L E L E L E L N N y y N N y y N N 4 BUF AEOI 8086 N N N N N N N N N N N N N N N N y y y y y y y y y y y N N N N N N N N N N y y 1 a a 1 a a a Y Y 8FNM y y La N N 8-bit vectored address Slave connections (master mode) Slave identification code (slave mode) 1 0 1 a - 8 8 8 Y 8 Y M y M y M y M N N N N N N N N y 8 Y 8 y 8 y 8 y M y M Y M y M Y Y N N y y N N y Y N N y y N N Y Y Y Y Y Y Y N N y Y N N Y Y N N Y -- . Y . __ N N Y N y N II Y N Y N Y N Y N Y N y N Y N y N Y N Y N Y N Y N Y .- Interrupt mask EOI SEOI Rotate o~ Non-Specific EOI command (Automatic rotation) Rotate on Specific EOI command (Specific rotation) Rotate in AEOI Mode (SET) Rotate in AEOI Mode (CLEAR) Set priority without EOl Y: yes, N: no, E: edge, L: level, M: master, S: slave • MITSUBISHI ..... ELECTRIC 5-97 MITSUBISHI LSls MSM82CS9AP CMOS PROGRAMMABLE INTERRUPT CONTROLLER ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vee Power-supply voltage V, Input voltage Va Output voltage Topr Operating free-air temperature range TsIg Storage temperature range Conditions With respect to Vss RECOMMENDED OPERATING CONDITIONS limits Unit -0.3-7 V -0. 3-Vee+0. 3 V -0. 3-Vee+0. 3 V -20-75 °C -65-150 °C (Ta=-20-75°C, unless otherwise noted) Limits Symbol Parameter Unit Min Vee Supply voltage Vss Supply voltage Nom Max 5.5 5 4.5 V V 0 ELECTRICAL CHARACTERISTICS (T a=-20-75°C, Vcc =5V±10%, Vss=OV, unless otherwise noted) Limits Symbol Parameter Unit Test conditions Typ Min V'H High-level input voltage 2 V'L Low-level input voltage -0.3 V OH High-level output voltage VOH(INT) IOH=-400"A 2.4 IOH=-100"A 3.5 IOH=-400"A 2.4 Max Vcc+ O. 3 0.8 Low-level output voltage IOL=2.2mA Icc Standby supply current from Vee Vcc=5.5V, V,=Vcc or GND output open V V V High-level output voltage, interrupt request output VOL V 0.45 V 10 /-lA I'H High-level input current V(==Vcc -10 10 /-lA III Low-level input current V,=OV -10 10 /-lA loz Off-state output current Vss=O, VI=O---..VCC -10 10 /-lA IIH(IR) High-level input current, lnterrupt request inputs Vl=VCC 10 /-lA 'IUIA) Low-level input current, interrupt request inputs V,=OV Ci Input capacitance Vcc=Vss, 1=1 MHz, 25mVrms, Ta=25°C 10 pF Ci/o Input/output capacitance Vcc=Vss, 1=1 MHz, 25mVrms, Ta=25°C 20 pF TIMING REQUIREMENTS /-lA -300 (T a=-20-75°C , Vcc =5V±10%, Vss=OV, unless otherwise noted) Limits Alternative Symbol Unit Parameter Symbol Typ Min Max 1wcw) Write pulse width tWLWH 290(200) ns 1SUCA-W) Address setup time before write 1AHWL 0 ns Ih(w-Al Address hold time after write tWHAX 0 ns TSUCDO-W) Data setup time before write tOVWH 240(100) ns Ih(w-oQ) Data hold time after write tWHDX 0 ns IW(RI Read pulse width tALRH 235 (200) ns tSU(A-A) Address setup time before read tAHRL 0 ns Ih(R-Al Address hold time after read tRHAX 0 ns tW(IR) Interrupt request input width, low·level time, edge triggered mode tJLJH 100 ns tSU(CAS-INTA) Cascade setup time after INTA (slave) tCVIAL 55 ns IreC(wl Write recovery time tWHRL 190 ns treCCR) Read recovery time tRHRL 160 ns tCHCL 500 ns End of Command to next Command (Not same Command type) Id(Rw) End of INTA sequence to next INTA sequence. 5-98 • MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSM82CS9AP CMOS PROGRAMMABLE INTERRUPT CONTROLLER SWITCHING CHARACTERISTICS (Ta=-20-75°C, Vcc=5V±10%, Vss=OV, unless otherwise noted) Limits Alternative Symbol Unit Parameter Symbol Typ Min Max 200 [1 70) ns lOa ns 200[170) ns tRLEL 125 ns Propagation time from read to disable signal output tRHEH 150 ns t pLH ( IR-INT) Propagation time from interrupt request input to interrupt request output tJHIH 350 ns tPLV{INTA-CAS) Propagation time from INTA to cascade output (master) tlALGV 565 ns tPZV(CAS_OQ) Data output enable time after cascade output (slave) tCVDV 300 ns tPZV(R-DQ) Data output enable time after read tRLDV tPVZ(R_DQ) Data output disable time after read tRHDZ tPZV(A_OQ) Data output enable time after address tAHDV tPHLCR-EN) Propagation time from read to enable signal output tPLH(R-EN) Note 1 2 M5M82C59AP is also invested with the extended specification showed in the brackets, INTA signal is considered read signal CS signal is considered address signal Input pulse level 0,45-2, 4V 2 4 Input pulse rise time 10ns ' ~2 Input pulse fall time 10ns Reference level Input V'H=2V, VIL =0, 8V 0,45 0,8 Output VoH=2V, VoL =0,8'L_ Load capacitance C L =100pF, where SP!EN pin is 15pF 10 x= 2 0,8 TIMING DIAGRAM Write Mode CS, Ao IJ K } th(W-Al tSU(A-W) ~I-- \ ~ I-- /-- tW{w) ...,~ -- thlw-DQI tSU(DQ-wl ~~ 0,-00 I-- ~K Read Mode CS, Ao )( thlR-Ai tSU{A_R\ tW(Rl \ K .J jI k- tpVZ(R-OQ) tPZV(A-OQ) tpZV{A-OO) mf-- 0,-00 ~\ ~ktpHl(R-ENJ 1// tPLH(R-EN) I \ r- • MITSUBISHI "'ELECTRIC 5-99 MITSUBISHI LSls MSM82CS9AP CMOS PROGRAMMABLE INTERRUPT CONTROLLER Interrupt Sequence IR (Note 1) INT (Note 3) 07- 0 0 tpLV(INTA-CAS) 1< CA&,,-CASo Other Timing WR RO INTA / tdlRw) WR RO INTA Note 1 8086, 8088 mode 2 : 8085A mode 3 : 8086,8088 mode is in high-impedance state, pointer is released during the next INTA. When in single 8085A mode, data ~~eased by all INTAs. When master, CALL instruction is released during the first INTA, high impedance state during the second and third INTA. When slave, high impedance state during the first INTA, vectored address is released during the second and third INTA. 5-100 • MITSUBISHI .... ELECTRIC (Note 2) MITSUBISHI LSls MSM82CS9AFP CMOS PROGRAMMABLE INTERRUPT CONTROLLER DESCRIPTION The M5M82C59AFP is a programmable LSI for interrupt control. It is fabricated using silicon-gate CMOS technology and is designed to be used easily in connection with an 8085A, 8086 or 8088. PIN CONFIGURATION (TOP VIEW) CHIP ST~~8t CS~ 1 ~~~f WR ~ 2 CONTROL CONTROL I~~~ FEATURES • • • • • • • Single 5V supply voltage TTL compatible CALL instruction to the CPU is generated automatically Priority, interrupt mask and vectored address for each interrupt request input are programmable Up to 64 levels of interrupt requests can be controlled by cascading with M5M82C59AFP Vee (5V) 27 ~ ~ ~~T~~~tWPUT 26 ~INTA ACKNOWLEDGE RD ~ 3 07- 4 INPUT INTERRUPT REQUEST INPUTS BIDIRECTIONAL DATA BUS 19 ~IR, 18 -IRo 17 -INT INTERRUPT ~~~~~~T 16 -SP/EN ~~Hn~~LrrM BUFFER OUTPUT Polling functions Packaged in flat small outline package 15 -.. _ _ _ _ _..r- CAS, CASCADE LINES APPLICATION The M5M82C59AFP can be used as an interrupt controller for CPUs 8085A, 8086 and 8088 FUNCTION The M5M82C59AFP is a device specifically designed for use in real time, interrupt driven microcomputer systems. It manages eight level requests and has built-in features for expandability to other M5M82C59AFP's. The priority and interrupt mask can be changed or reconfigured at any time by the main program. When an interrupt is generated because of an interrupt Outline 28P2W request at 1 of the pins, the M5M82C59AFP based on the mask and priority will output an INT to the CPU. After that, when an INTA signal is received from the CPU or the system controller, a CALL instruction and a programmed vector address is released onto the data bus. Refer to M5M82C59AP for detail information. compatible with M5M82C59AFP's specifications are M5M82C59AP. Only package outline is different. BLOCK DIAGRAM ,..----- - - - - --- - --- - --- - ----, INTERRUPT ACK~OWLEDGE INPUT INTERRUPT REQUEST OUTPUT INTA CONTROL LOGIC BIDIRECTIONAL DATA BUS 2 WR WRITE CONTROL INPUT INTERRUPT REQUEST INPUTS 3 RD READ CONTROL INPUT 27 ;1: Ao ADDRESS INPUT ~:;}HI:A::~E:: ~:E:T 15 CAS, '-----{liS SP/EN - - - - --_. - - - - - --- - • MITSUBISHI IIhtt.ELECTRIC ----" SLAVE PROGRAM INPUT! ENABLE BUFFER OUTPUT 5-101 II MITSUBISHI LSls MS8992P CMOS CRT CONTROLLER DESCRIPTION The M58992P is a raster scan type CRT interface device, fabricated using silicon gate CMOS technology. This LSI is a one-chip type high-performance video display generator having the timing signal generator and attribute circuits required for CRT display so as to allow system configuration with a small number of components. FEATURES • • • • • • Single 5V supply voltage. Can generate· video display using simple external circuit 10 programmable display modes Some mode conditionally allows mixed use with other mode. Color display is programmable to use either 8 or 16 colors. The R, G and B Signals are provided as video output signals. • • Can superimpose on TV screen A 16K or 64K DRAM is used as the video RAM under control of the built-in DRAM controller. • The video RAM area can be used concurrently for storage of display data and microprocessor program. Paging and scrolling are possible. Cursor control; blinking, blanking, underline and reverse characters are possible. Light pen input control function is provided. Various interrupts generating function is provided. • • • • APPLICATION PIN CONFIGURATION (TOP VIEW) (OV)V55 DAD 7 2 DAD.- 3 MULTIPLEXED DADs DRAM DAD, ADDRESS/DATA DAD3 BUS 5 6 DAD 2 - 7 ROW ADDRESS DADo STROBE OUTPUT RAS - 10 ~~~g~~ ~~~~G~S CAS - WRITE ENABLE OU:~:O WE - OUTPUTS 9 I~: : B-15 1- 16 17 CLOCK M 19 MClK - 47 --+ READY READY OUTPUT SYSTEM CLOCK ClK --+ 20 BD~~G~G LIGHT PEN STROBE INPUT BLANK - 21 l TPEN --+ 22 ~~~~~K{6~ RASTER ADDRESS 24 25 26 CODE DATA jCDRD, READ OUTPUTS) CDRD 2 _ 27 OUTPUTS 46 - ~ft~g1~~8fDE CAL T HORIZONTAL HSYNC _ SYNCHRONIZE - OUTPUT VSYNC - ~~~~r~nUTPUT CHIP SELECT INPUT READ INPUT WRITE INPUT 28 DATA BUS 29 30 31 (Ov) v 55 OUTPUT Outline The information or data to be displayed on the screen is written in the video RAM by the microprocessor. The M58992P can read the video RAM in the order of the CRT scan, and can generate synchronization signal for a CRT. • MITSUBISHI .... ELECTRIC RESET RESET INPUT 45 --+ I NTR 44 - loiM IO/MEMORY INPUT RAo _ 23 IRA, RA2 RA3 _ FUNCTION 5-102 ADDRESS BUS 11 12 BURST OUTPUT BRST CLOCK B ~~~~~~6NIZE Display unit using home TV set or monitor TV set 4 64P48 DAD, DAD. DAD, DADo DAD? DAD, DAD3 DAD, Y'-. '-'-. '-. I '- '-. CDRD, CALT CDRD, RAo RA, RA, RA3 CAS RAS '- I WE '-. '-. '-. YY '-. '- '-. BLANK VSYNC BRST HSYNC '-c '- '-c R '- G B '-- '-- ~ IV I ,. "':I 1""- "'-I (")(1) -Ie:: ! A, ) \ A, A, C=;iii A? COLOR INTERFACE ENCODER ~ r-- \ ) A3 A. SYNCHRONIZE 16 8 1 ) J / J ~ :>0 0 VIDEO ADDRESS AND TIMING GENERATOR ::c X I--- START DISPLAY COMMAND COLOR ADDRESS MODE REGISTER REGISTER REGISTER REGISTER I---~ VIDEO AND ATTRIBUTE DATA CONTROLLER 8 8 III (fJ :; III A9 / ." A10 ;; A" '! A12 '/ A'3 ~ A,. ~:; A15 STATUS REGISTER joE ~~GG~~~~NI- LTPEN m (fJ (fJ c As J ~ A, ::10m = \ Ao M DAD BUS COMMAND AND CHARACTER GENERATOR INTERFACE DRAM INTERFACE .. 8 J ." m ::c / 8 MICROPROCESSOR COMMAND DECODER DATA BUS BUFFER L.....- 8 .. INTERNALBUS . .. c I IIIII111 MICROPROCESSOR BUS INTERFACE It III "-./"....-/~"--./'-...-/ D~ D~ D~ D~ D~ D~ D~ D~ WR RD CS loiM RESET CLOCK AND INTERNAL TIMING GENERATOR J (") s:0 (I) (") 1 I I I I --0----@-0 45 I-{ 47 ~ ~ INTR READY ::10 -I CLK BCLK MCLK Vss Vss Vee J (") 0 z -I ::10 0 r r U1 I '::10" Cl W I s: i: ~ CII c: GO ! U) U) (I) N r -a :5 ~ MITSUBISHI LSls MS8992P CMOS CRT CONTROLLER PIN DESCRIPTION Pin DAD7~ DADo Name Multiplexed DRAM address RAS strobe output Column address -~ CAS Input/output Idata bus Row address -~ Input/output strobe output Functions Causes data input from DRAM or data output for writing in DRAM by output of mltiplexed row and col- umn address to DRAM. ~ Output DRAM address input is latched at falling edge of RAS. Output DRAM address input is latched at falling edge of CAS. Output Data from microprocessor is written in DRAM when this signal is "L". ~ WE Write enable output R Video output R G Video output G B Video output B TTL level output of video signals R, G and 8. Output -~ Auxiliary output for R, G and B. By externC\1 Combination with R, G and B, up to 16 colors can be disVideo output luminance I played. 1= "H" indicates high luminance. BRST Burst output Output BClK Clock B Output MClK Clock M Output ClK System clock --BLANK Blanking output lTPEN Light pen strobe input Signal to indicate color burst signal position or sUb-carrier frequency phase-modulated by RGB in case of NTSC system. Frequency at 114 of clock input. Subcarrier frequency in NTSC color system. -- RA3~ RAo --CDRD1 --CDRD2 CAlT Input Output Input Internal timing clock. Indicates DRAM access by the M58992P for display when this signal is "L" in the text 1, text 2, graphic 1, graphic 2, graphic 3 or graphic 5 mode. 14.31818MHz for display using NTSC system. Indicates around the synchronizing pulse in horizontal or vertical blanking period of the M58992P. Signal to latch internal address value. Character generator raster address Output Least significant 4 bits of address for use of character generater to be used in text mode. outputs Signal to control external circuit for input of display code pattern to the M58992P. Code data read outputs Output --- --~ CDRD1 is the timing for direct data input from DRAM to the M58992P, and CDRD2 is the timing for input from character generator. Character code latch output Output Signal to cause external latching of character generator pointer output from DRAM. - --HSYNC ---VSYNC 5-104 Horizontal synchronize 'putput Vertical Open drain output Setting synchronizing signal input mode by command causes no generation of internal synchronizing nal but internal counter reset by external signal. synchronize output • MITSUBISHI ..... ELECTRIC sig~ MITSUBISHI LSls MS8992P CMOS CRT CONTROLLER PIN DESCR1P11ON (CONTINUED) Pin Input/output Name Functions 1------1----------1-----_+------------------.-------------------------1 DB7~DBo Data bus Input/output Data bus DB, : MSB -~ WR _._----, Write input Input _. Function t----- CS 101M RD WR r----------------~--~----r---~------- No LSI selection - RD Read input Input DRAM Read -- .- DRAM Write - CS Chip select input Input The M58992P register read -- The M58992P register write - 101M IO/memory input Input The M58992P starts DRAM access or internal register read/write upon CS. f-----+------.----+----~------ INTR Interrupt request output Output ----~.--- .. ---- Interrupt request output generated for any of four reasons in the M58992P can be masked. The status register detects the type of interrupt. The INTR signal is reset upon status read. f------I-------+---~-_+------------------------------------ RESET Reset input Input The M58992P system reset signal to initialize various registers. - - - - - - + - - - - - - - - + - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .- READY Ready output Output Normally "H" signal. Goes to "L" upon selection of DRAM and returns to "H" upon completion of DRAM read/write. This signal provides synchronism with the microprocessor. I-~-~--+--------~I----+------------------------------ Address bus Input - -.... --- Address input on the microprocessor side. A15 is the MSB. Ao to A3 are used for register reading or writing. • MITSUBISHI "ELECTRIC 5-105 II MITSUBISHI LSls MS8992P CMOS CRT CONTROLLER Table 1 The M58992P display mode list 8X8 dots 2000 16 bits/ FG: aX10 dots 16 colors BG: 8 colors aX8 dots BD: 16 colors allowed. character (8 bits for character and 8'bits for color 1600 Border colo designation, Unused 4000 designa- tion) 2X2 dots 3200 FG: 1 block: blinking possible without flickering. may be dis- Always ignated in possible character Flickering is caused at units. other than blinking. MSB 4 bits, 4 bits/dot BG color 16 colors X30 lines 40 characters X24 lines 80 characters X30 lines 80 characters X24 lines 160H 8000 16 colors BD: Multiple Always 2400 1920 positions Unused etc. 8X10 dots 1 block: Cursor X120V 4800 3840 9600 Unused Always 16000 2Xl dots Possible 160H X240V 19200 without FG : Semi 1 block: 1X1 dot flickering. 16 colors BD: 2 bits/dot Color pallet for FG 320H 16000 X240V 19200 16 colors FG: 1 block: 1X1 dot 16 colors BD: Border 4 bits/dot or, etc. col~ No MS84 bits, 32000 8G color Same as text 3 and 4 modes 16 colors 320H X240V 38400 Unused FG: One 1 block: 1X1 dot BG and FG seleted color 1 bits/dot BD: color de- Same as 16000 signation text 1 and 2 640H 19200 X240V modes 16 colors 1 block: 1X1 dot FG=Foreground 5-106 Same as graphic 3 8G=8ackground Same as 2 bits/dot Color pallet for FG 32000 text 3 and 4 modes BD=Border CLRG1 ....... 3=Color register • MITSUBISHI "'ELECTRIC 640H X240V 38400 APPLICATION MITSUBISHI LSls NOTICE FOR CMOS PERIPHERALS 1. INTRODUCTION 3. OPERATIONAL DESCRIPTION Mitsubishi Electric's microprocessor-support CMOS peripheral LSI devices are compatible with current NMOS peripheral devices, and feature the additional advantages listed below. Fig. 3 illustrates what happens when supply voltage (V cc ) is applied to the circuit shown in Fig. 2, varying input voltage from Vss to Vcc. The Va curve indicates the change in output voltage and supply current (Icc). As illustrated, these characteristics depend on input voltage, so can be better understood by dividing V, into three regions, I ~ ill. I : In this region, only the p-channel transistor T2 is on, so that the Va output voltage becomes Vcc. In this condition, practically no current Icc flows. IT : In this region, Va varies in accordance with V" When V, is increased from region I, the n-channel transistor T, begins to turn on, so that Va gradually decreases and at some point begins to decrease rapidly. The value of V, at this point of rapid Va decrease is known as the circuit threshold voltage. .When this voltage is exceeded, as V, is increased, Va approaches V ss. In the region IT, Va is determined by the ratio of the on resistances of T, and T 2 . Icc is always flowing in this region, and becomes maximum when V, is at the circuit threshold voltage. ill : In this region, since only T, is on, Va becomes the voltage Vss. In this region, as was the case for region I , virtually no Icc current flows. • Compatibility with 8251A, 8254, 8255A, 8237A, 8259A. • Low power dissipation • Wide supply voltage range, Vcc =5V±10% • Wide operating temperature range, T a= - 20~ 75"C • Improved timing conditions Due to these advantageous features, CMOS peripheral devices can be used to replace conventional NMOS devices in their typical applications, and can additionally be used in applications requiring low power dissipation. The following sections describe the basic characteristics of Mitsubishi Electric's CMOS peripheral LSI devices for microprocessor support, and explain precautions and methods of use. 2. BASIC CIRCUITS AND CONSTRUCTION The internal circuitry of CMOS devices consist of both pchannel and n-cha'nnel transistors. There are two types of NMOS transistors. In the depletiontype, drain-to-source remains on even when gate-to-source voltage is OV, and with the enhancement-type device, dropping gate-to-source voltage below the threshold voltage level turns the transistor off. CMOS devices employ the enhancement type, regardless of whether they are p-channel or n-channel devices. Fig. 1 shows the typical inverter, which is the basis of CMOS peripherals and Fig. 2 illustrates its equivalent circuit diagram. vee vss PROCESS TECHNOLOGY Fig.2 Single-stage inverter circuit Silicon Gate N-Well CMOS II ill vee o > .s"'" '5 > '5 c. '5 o Substrate P-(GND) ,\ \ Icc \ \ \ \ \ \ \ Fig.1 \ Single-stage inverter construction " Vee Input voltage V, Fig.3 Single-stage inverter voltage transfer and supply current vs. input voltage characteristics • MITSUBISHI .... ELECTRIC 6-3 MITSUBISHI LSls NOTICE FOR CMOS PERIPHERALS 4. TRANSFER CHARACTERISTICS AND POWER DISSIPATION For COMS devices, the circuit threshold voltage is approximately one-half of Vcc. Contrasted with NMOS logic, where threshold voltage is a fixed level not related to supply voltage, ideal transfer characteristics can be achieved. In order to maintain compatibility with the conventional NMOS devices, transfer characteristics of CMOS peripherals I/O circuits have been establiched at TTL level. Fig. 4 illustrates input voltage V'N versus supply current Icc for MSM82CS5AP-S. Here, when V'N reaches 1.3 to 1.5V, the resulting switch in internal circuits causes a sharp increase in Icc flow. creases power dissipation. The M5M82C5SAP-5 illustrated in Fig. 4 has parallelconnected I/O ports, and is relatively limited in switching operations. However, devices such as the programmable timer MSM82C54P are subjected to constant clock operations, and the current flow for each CMOS circuit must be added to get the total for the device. As shown in Fing. 5, currnet dissipation increases along with increases in operating frequency. 5 Vec=5V DUTY=50% Ta-25"C (PORT-Ao MODE 0 INPUT) 250 V1H min 3.15 Qi V 1H min > ~ V OH min Q) OJ E > V OH min 2.7 2.4 0 2.0 2.0 2 V 1H min V 1H min V1L max 1.5 V1L max 0.45 0.9 0.4 VOL max VOL CMOS peripherals max LSTTL (Note 1) VOL 0.05 max VOL max 0.1 Standard CMOS logic High-speed CMOS 4000B series 74HC series (Note 2) TTL level, Note VOH min=2. 4V Fig.? II V 1L max V1l max 0.8 0.8 TI 2 : JEDEC V ee =4. 5V DC noise margin comparison (V cc =5.0V) 6. FANOUT }IOH=-l~OI'A 5~~~____________~~~~~~~I~o~H= __ -~4rm~A T a=-40, 25, 90'C I Ta =-40'C o" > Ta =25'C Ta =90'C 5 Vee (V) Fig.8 V OH characteristics M5M82C55AP-5 The drive capability of CMOS peripheral devices generally exceeds that of NMOS logic devices. This can be seen in Fig. 8, where drive capability at "H" level is noticeably better than NMOS. This defference between logic types provides a slight difference when actually applied to ~riving a load such as a transistor, and the value of the load resistance can affect fanout capability. This point will be covered in more detail later. For reference purposes, the "L" level drive capability of M5M82C55AP-5 is illustrated in Fig. 9. When driving a MOS-IC with a peripheral LSI, since it is only necessary to drive the input leakage current of the DC-connected IC, fanout capability is quite good. However, where devices having many components (e.g., data bus, etc.) are connected, the stray capacitance of the wiring and device input capacitance (generally about 5pF) must also • MITSUBISHI ;"'ELECTRIC 6-5 MITSUBISHI LSls NOTICE FOR CMOS PERIPHERALS be driven, so signal switching response is slower. In this case, the load (s) to be driven must be divided (or allocated to several devices) as with previous devices. O.3~-----4-------+------~------+-----~ :; lfj iil ~~~:~i.y l ~8'Z I2t.C ~~~:;~~~~vee=4.5V I O. 2 ~------+-------+------~----;;>"":""';"'Vee=5. 5V Vee =4.5V Vee :5VI Vee -5. ~v f-«« e ~~ 0.1 I T - causing permanent demage to the device.. To prevent gate damage, the diodes and input resistor shown in the diagram form a protection circuit. Since threshold voltage for the input transistor is set at approximately 1.5V, as noted in section 4, input voltage becomes unstable around this level, and a through current starts to flow from Vcc to Vss. In systems where low dissipation current is required, this characteristic can cause problems in the design of the power supply. Where a data bus is left floating, through current is likely to become a particular problem, so bus lines should be fixed at a certain level with a pull-up (or pull-down) circuit having high resistance values. T vee=5vl -.!40.C .------------------------.., Vee =5.5V ! UNIT: v 10L (DATA BUS)(mA) Poly-Si Input Fig.9 10L-VOL V TH =C1. 5V Q9----'lM--+------+ characteristics M5M82C55AP-5 (at Vee =5V) R=cl k!1 7. INPUT CIRCUIT Fig. 10 shows an equivalent circuit diagram of the input circuit for CMOS peripheral devices. The gate oxide layer of the transistors is extremely thin, and high voltages applied directly to the gates are likely to rupture their insulation, Fig.10 CMOS peripheral device input circuit (equivalent diagram) DATA BUS TIMING READ WRITE (j) o ::< Address, CS Address, CS DATA (INPUT) RD z DATA (OUTPUT) WR Address, CS *(j) o ::< Address, CS min200ns DATA (INPUT) RD () '~. max170ns min200ns WR DATA (OUTPUT) - - - - - ' ( \ VALID }- "'--.----- * M5M82C37AP, C51 AP, C55AP-5, C59AP Fig.11 6-6 Bus timing characteristics • MITSUBISHI .... ELECTRIC MITSUBISHI LSls NOTICE FOR CMOS PERIPHERALS 8. TIMING CHARACTERISTICS Conditions (al or (el The timing conditions between the system and CMOS eWhen using a dual power supply When dual power supplies serve CMOS logic devices, differences in the rising edge of the power line signal tend to cause latchup. This can be eliminated by using a series connected resistor (R) to limit current flow to a maximum of 10mA. (Refer to Fig. 12) peripheral LSI devices have been improved over their NMOS type counterparts. Improvements include better setup and hold times, and microprocessor interfacing is easier. Fig. 11 summarizes there differences in comparison form. Whereas NMOS devices required ts and th time, these have been eliminated with CMOS peripherals by setting ts and th ta Ons. VCC2 Vee1 9. USAGE PRECAUTIONS (1) vee Dealing with NC input pins Vee R Leaving unused input pins open results in instability input voltage, which in turn can produce errors in output logic levels and increase current dissipation. Unused input pins Vss should therefore be tied to Vee or Vss. (2) Voltage supply lines Power dissipation of CMOS peripherals whose internal Vee VCC2 tance of approx. 0.111 F) wired close between Vee and Vss. Also, when devices such as M5L82C55AP-5 are used with surges, etc. When this happens, a large current flows from Vee to Vss , and if current flow continues, the device will be destroyed. Provision must be made to clear latchup to prevent overcurrents from destroying the device, and that can Vss ,...----Vee power line impedance to filter the spikes. To accomplich this, each device should be fitted with a ceramic capaCitor (having good high frequency characteristics and a capaci- The internal circuitry of CMOS devices often have parasitic bipolar transistors formed in the substrate, and these opearate like thyristors, being triggered by external voltage V, Vee, changes are small such as M5M82C55AP-5 and M5M82C59AP is extremely low. However, the through current spikes that occur during switching are dealt with using the traditional method applied to older ICs; by reducing a high current drive circuit connected to output, power lines should be run independently from the logic system and driver circuit to reduce adverse affect on the logic system. (3) Latchup Input Output Input Output V, >V e Fig.12 Preventing latchup when dual power supplies are used e When using differential circuits When differential circuits are used, it is possible for input voltage to exceed Vee or Vss , which could result in latchup. In this case, use a diode for voltage clamping, combined (a) (b) (c) V,>Vee+V F Vo>Vee+VF V, Vce. Where possible, separate power supplies should be used. If a common power supply must be used, (d) (e) Vo---4>----wv'v----v-o---Ilnput Output-- I ~;";;;:':.::jr::::::~_.J.=_---.:+:::~~Vcc=4. 5V V =5.5V it' cc --,----Lvcc=5V I Vcc =4.5V -2 -3 -4 IOH (rnA) IOL (rnA) 1.=For a base current I. of -lmA, the difference in VOH is approx. 1. 5V. Flg.16 M5L8255AP-5/M5M82C55AP-5 V OH output characteristics comparison • Fig.17 MITSUBISHI ~ELECTRIC M5L8255AP-5/M5M82C55AP-5 characteristics comparison VOL output 6-9 II MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 1. DESCRIPTION 5. The M5W1791-02P is a floppy disk formatter/controller de- PIN CONFIGURATION (fOP VIEW) vice which accommodates single and double density formats. NC WRITE Co~~~m WR ~ The device is designed for use with microprocessors or mic- CHIP S~~~8t CS ~ READ CO~~~8f RD ~ REGISTER J Ao ~ rocomputers. The device is fabricated with the Nchannel silicon gate Single 5V supply voltage • Accommodate singe and double density formats IBM 3740 single density format BIDIRECTIONAL DATA BUS IBM system 34 double density format • Selectable sector length (128, 256, 512 or 1024 bytes/ sector) • • Side select compare Single/multiple sector read or write with automatic sector search • Selectable track to track stepping time • • Write precompensation OMA or programmed data transfers • Window extension - READY RE1~~\~Wm ~ WD ~m-1>lrpATA ~ WG ~~~1>~f'A TE ~ 29 ~ TG 43 TG43 OUTPUT 4- D;"0;- • 33 32 31 30 DO EN ~~~NE1!~fl~PUT WPRT ~~rrf PROTECT fP INDEX PULSE INPUT TROD TRACK 00 INPUT WFNFOE ~~~/i~lT 37 36 35 - Do- FEATURES INTERRUPT 38 ~ DTRQ gt~~U~EQUEST S~~~8t 1 A, ~ EOMOS technology is packaged in a 40-pin OIL package. 2. NC 39 ~ INTRQ ~D9~o¥T 28 ~ HOLD ~D~~Jr0AD 27 - RAW READ ~P~TREAD 26 - RCLK FNEtST CLOCK 25 ~ RG READ GATE OUTPUT Vc c(5V) Outline 40P4 NC: NO CONNECTION systems. The hardware of the M5W1791-02P consists of a 3. • • APPLICATION Single or double density floppy disk drive formatter/con- floppy disk interface, a CPU interface and a PLA control logic. The total chip can be programmed by eleven 8-bit troller commands. The floppy disk interface portion performs the 8-inch or mini floppy disk interface communication with floppy disk drive under control of the PLA control logic. The CPU interface portion has five regis- 4. FUNCTION The M5W1791-02P is a floppy disk formatter/controller that ters - command, data, status, track and sector register and communicates with the CPU through the data bus. can be used with most microprocessor or microcomputer These functions are also controlled by the PLA. 6. BLOCK DIAGRAM BIDIRECTIONAL DATI\ BUS WRITE CONTROL INPUT Wii 2 CHIP SELECT INPUT C§ 3 READ CONTROL INPUT Ail • REGISTER SELECT{Ao 5 INPUT A, 6 r----,..·-{;311 WPRT WRITE PROTECT INPUT EARLY OUTPUT EARLY LATE OUTPUT LATE WRITE GATE OUTPUT WG WRITE DATA OUTPUT WD 17 18 30 31 R~:b' I~~~~ 27 RAW READ CLOCK 3 jj5 3 i'ROO r==j=rL:,,:,,~=~3 READY II 23 HOLT , - '-..J2'''9TG 43 2 TEST TEST INPUT I~~b~ 26 CLK . CLOCK INPUT 2. DDEN DOUBLE DENSITY MODE 37~----l>-----------~ SELECT INPUT 33 RG WF/VFOE RESET READ GATE ~~IT.M~gLT RESET INPUT OUTPUT CONTROL OUTPUT 6-10 INDEX PULSE INPUT TRACK 00 INPUT READY INPUT HEAD LOAD TIMING INPUT TG43 OUTPUT HEAD LOAD OUTPUT DIRECTION OUTPUT STEP OUTPUT • MITSUBISHI ..... ELECTRIC INTERRUPT REQUEST OUTPUT DATA REQUEST OUTPUT MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 7. PIN DESCRIPTION Pin Input or Name No internal NC NC(pin 1) is not internally connected connection Write control - WR input CS Chip select input - Read control RD Functions output input Input Write signal from a master CPU (Active low). Input Chip select (Active low). Input Read signal from a master CPU (Active low). ._- r--Register select inputs. These inputs select the register under the control of the RD and WR. A o, A, - - Do-D7 Register select Input input Bidirectional In/Oul data bus A, Ao 0 0 1 1 0 1 0 1 -- - RD WR STATUS REGISTER COMMAND REGISTER TRACK REGISTER TRACK REGISTER SECTOR REGISTER SECTOR REGISTER DATA REGISTER DATA REGISTER Three-state, inverted bidirectional data bus. - - - - t-----------.--- - - STEP Step output Output Step pulse output (Active high). DIRC Direction output Output Direction output. High level means the head is stepping in and low level means the head is stepping out. EARLY Early output Output - -- lATE Output Late output -- 1----RESET This signal is used for write precompensation. It indicates that the write data pulse should be shifted earty. This signal is also used for write precompensation. It indicates that the write data pulse should be shifted late. Reset input (Active low). The device is reset by this signal and automaticaily loads "03" (hexadecimal) into Reset input Input Test input Input the command register. The not-ready-status bit is also reset by this signal. When reset input is made to be high, the device executes restore command even unless READY is active and the device loads "01" (hexadecimal) to the sector register. - - TEST HDlT Head load timing input ---- Input Clock input RG Read gate output Output RClK Read clock input Input Raw read input Input READ HDlD Head load output actuated motors. When the device finds high level on this input, the device assumes that the head is engaged on the media. Active high. -- ClK r---= RAW This input is only used for test purposes, so user must tie it to Vee or leave it open unless using voice coli Input Output Clock input to generate internal timing. 2MHz for 8-inch drives, 1MHz for mini drives. This signal shows the external data separator that the syncfield is detected. This signal is internally used for the data window. Phasing relation to raw read data is specified but polarity (RCLK high or low) is not important. This input signal from the drive shall be low for each recorded flux transition. This output signal controls the loading of the head of the drive. The h~ad must be loaded on the media by this high-level output. • MITSUBISHI .... ELECTRIC 6-11 II MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER Pin Name Input or output Functions TG43 TG 43 output Output This output is valid only during disk readlwrite operation and it shows the position of the head. High level on this output indicates that head Is positioned between track 44 to 76. WG Write gate output Output This signal becomes active before disk write operations are to occur. WD Write data output Output READY Ready input Input This signal consists of data bits and clock bits. It becomes active for every flux transition. Active high. This signal shows the device the drive is ready. In the disk read/write operation except for TYPE 1 command operation, low level Input terminates current operation and the device generates the INTRQ. In the TYPE 1 command operation, this signal is neglected. Not ready bit in the status register is the inverted form of this input. This is a bidirectional signal. It becomes write fault input when WG is active. In the disk write operation, WFIVFOE Write fault Inputl VFO enable InlOut low level signal on this input terminates the write operation and makes INTRQ active. This signal also appears in the status register as the write fault bit. When WG is inactive, this signal works as VFO enable output. VFOE output is also an open drain type, so pull it up to Vee and never input active write fault signal output write WG is inactive. TROO Track 00 Input Input This signal indicates that the head is located on the track 00 to the device. Active low. IP Index pulse input Input This input indicates to the device that an index hole of the diskette has been encountered. --WPRT Write protect input Input write operations, this signal is sampled and an active low signal will terminate the current command and --- Double density Input This input determines the device operation mode. When DDEN=O, double density mode is selected. When DDEN= 1, Single density mode Is selected. Output that data is assembled in the data register. In the disk write mode, it indicates that the data register is DDEN DTRa INTRa NC 6..,...12 mode select input Data request output Interrupt request output No internal connection Low level signal on this inpLlt informs the device that the drive is in the write protected state. Before disk set INTRQ. The write protect status bit in the status register is also set. DTRQ is an open drain output, so pull up to Vce by the 10k resistor. In the disk read mode, DTRQ indicates empty. DTRQ is reset by the read data or write data operation. Output INTRQ is also a open drain output, so pull up to Vee by the 10k resistor. INTRQ becomes active at the completion of any command and is reset when the CPU reads the status or writes the command. NC (pin 40) is not internally connected. •. MITSUBISHI .... ELECTRIC -- MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 8. HARDWARE CONFIGURATION The following explanation is based on the block diagram is Section 6. The registers which are accessible by the CPU system through the input/output buffer of the M5W1791-02P are the command, status, track, sector and data registers. These are ali 8-bit registers. . The register select inpus Ao and A, select one register under RD, \Nfl and CS control as described in Section 7. 8.1 Retister Descriptions (1) Command Register This register is write-only, so the contents of the command register cannot be read onto the bi-directional data bus. The CPU system writes the command code into this register to be executed by the M5W1791-02P. Except the force interrupt command, the command register should not be loaded while the busy status bit is set. (2) Status Register This is the read-only register and holds the status information about the device and a connected floppy disk drive. The meaning of each status bit is varied by the executing command. (3) Track Register This register is bi-directional, so the CPU system can read or write the data through the data bus. The track register has the track number of the floppy disk's current head position. The type 1 commands have the update flag option according to this register. When this flag is set, the contents of the track register are updated by one for each step. They are incremented when the head is stepped in and decremented when the head is stepped out. When the type 2 command which performs the read/write operation for the floppy disk is executed, the track address of the floppy disk's ID field and the contents of the track register are compared. If they match, M5W1791-02P continues to check whether the sector address is the one appointed by the sector register. When the restore command is performed automatically by the -RESET input transition from "0" to "1" or when the CPU system executes the restore command, FF (HEX) is at first loaded into the track register and every time the step pulse is issued, the value of this register is decremented by one. The contents of the track register are set to 00 (HEX) when the TROO input is activated before the 255th step pulse issued or after the step pulse was generated 255 times. (4) Sector Register This is also a bi-directional register. For disk read or write operation, the CPU system must set the desired sector address into this register. By forcing the RESET input from "0" to "1", M5W1791- 02P also sets 01 (H EX) into the sector register, then begins the restore operation. In the type 2 command execution, the sector address of the disk's 10 field and the contents of the sector register are also compared as mentioned above. When the m flag bit of the type 2 command code is set to perform the multi-sector read/write operation, the sector register value is automatically incremented by one upon completion of the read/write operation of the one sector. When the read address command of the type 3 command has been executed, the track address which is read out from the first encountered 10 field is loaded into the sector register. (5) Data Register This register is bi-directional. During disk data read operation, the data read from the floppy disk is held in this register. During the write operation, byte of data from the CPU system is held. Prior to seek command execution, the desired track position must be written into the data register. By executing the restore command or the RESET input transition from "0" to "1", M5W1791-02P automatically loads 00 (HEX) into the data register. The hardware blocks of access to the user are only the reigsters mentioned above. Descriptions of inaccesible internal hardware blocks follow. 8.2 Control Circuit (1) ALU (Arithmetic Logic Unit) This one-bit serial ALU executes the comparisons of the serial data and is used for the modification and comparison of registers. (2) Status Control Logic The status control logic generates the status information for the status register. It is divided into two sections: one reflects the state of the M5W1791-02P and the other reflects the state fo the disk system. Disk states inclued write protect, index pulse, track 00, ready, head loak timing and write fault. (3) Head Control Logic This circuit generates the signal which controls head movement of the floppy disk. It provides the head load signal, direction signal, step signal and TG43 signal. The TG43 output controls the disk's write current. When the type 1 command with the head load flag h at "1" is executed, the head load output is set to "1" at the beginning of the command execution. The command execution where the head load flag h is initially at "0" makes the head load output "0" whether it has been "0" or "1 ". After issuing the step pulses, the M5W1791-02P checks • MITSUBISHI ...... ELECTRIC 6-13 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER the verify flag V in the command code. If V is "0", the command is terminated and the interrupt request output signal is sent. If V is "1", the head load output is set to "1" (if h ="1" , HDlD is already set to "1" at the beginning of this command), and after an internal 15 ms delay (ClK = 2MHz, TEST =1), the head load timing input HOLT is sampled until HDlD andHlDT ="1" (logic true). Then M5W1791-02P updates the TG43 output signal and commences the disk read operation. This means that during the type 1 command, the TG43 signal is not updated unless the V flag is set to "1". The TG43 output is set to "1" when the floppy disk head is positioned beyond the 43rd track. The type 2 and 3 commands confirm the ready input logic high, and after a 15 ms delay (if flag E is set; if E = 0, no internal delay is initiated), HDlT is sampled until HDlD and HDlT = "1" as mentioned above. M5W1791-02P then updates the TG43 output signal and begins the disk read/write operation. If the ready input is low, then the command is terminated and INTRa is generated. The head load output which was set to "1" is reset to "0" under the following two conditions: • If the M5W1791-02P is idle for 15 disk revolutions after the prevous command terminates, the head load signal resets to "0". • If the type 1 command is executed when h = "0", the head is also automatically disengaged. (4) Head Engage Timer/Step Speed Timer The M5W1791-02P can generate an internal 15 ms wait time (ClK = 2MHz) before the head load timing input is sampled. The HDlT signal shows M5W1791-02P that the floppy disk head is completely engaged after loading into the media. The step speed can be selected at 3 ms, 6 ms, 10 ms or 15 ms (ClK = 2M Hz) by the stepping motor rate bits r1 and r0 in the type 1 command. These operations are controlled by the 1 ms timer and presettable 4-bit binary counter inside the M5W1791-02P. This 1 ms timer is disabled by setting the test input TEST to "0", which initiates step pulse intervals of about 400",s in the single-density mode and about 200",s in the doubledensity mode (ClK = 2MHz). The 15 ms wait time is also reduced in the two modes to about 60",s and 30",s, respectively. The test input signal is used only for interfacing with the floppy disk drives and a voice coil motor. Table 8.1 shows the relationship between the stepping motor rate flags and the step pulse intervals. Table 8.1 Step Pulse Intervals (unit: ms) r11 0 elK (MHz) __________ DO EN 0, 0, 1, 1, 6-14 0 1 0 1 lMHz 2MHz 0 3 6 10 15 I 1 3 6 10 15 0 6 12 20 30 1 6 12 20 30 (5) Index Pulse Counter/Se't~ounter/ Step Pulse Counter As mentioned in Section 8.2 (3), the MlilW1791-02P has an index pulse counter that returns the head' load output to "0" in the idle state after command execution. This index pulse counter is used to terminate the command when the M5W1791-02P does not complete it within 5 index pulses. There are 12 reasons why the command may be terminated prematurely: • The synchronize pattern of the 10 field is not found. • The synchronize pattern of the 10 field is too short. • • • • • • • • • • AM1 of the 10 field is not found. AM1 of the ID field is not complete. The 10 track address is not equal to the contents of the track register. The 10 sector address is not equal to the contents of the sector register. The side number of the 10 field is not equal to the side select flag s in the command code when the side comparison flag C is set to "1 ". The 10 field CRC error occurs. The synchronize pattern of the data field is not found. The synchronize pattern of the data field is too short. AM2 of the data field cannot be found. AM2 of the data field not complets. When a CRC error of the data field occurs, an interrupt is generated without a retry. The index counter is also used as the sector counter/ step pulse counter. When this counter is used as a step pulse counter, it counts a maximum of 255 step pulses during the restore command as described in Section 8.1 (3) This counter is used as a sector counter in the type 2 command to count the data length of the data field for the destination sector. In this sense, it is more appropriate to call this counter the data length counter. The M5W1791-02P allows one of four different data length configurations in one sector: 128 bytes, 256 bytes, 512 bytes and 1024 bytes. The data length of the sector to be read or written by the M5W1791-02P is decided by the "sector length" parameter at the 4th byte of the ID field. When the read/write operation is commenced for the desired data field, the M5W1791-02P use's this sector counter to generate the data request signal at specified times in accordance with the ID sector length byte. (6) Interrupt Request Control Logic, Data Request Control Logic The interrupt request output INTRa is an open drain output that notifies the CPU of command termination. Once set, the interrupt request output INTRa is not reset to "0" until the status is read out from the status register or the command is written into the command register by the CPU. ."MITSUBISHI "ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER Refer to Section 11.5 concerning the response of the INTRQ during the type 4 command. The I NTRQ output· is not reset by the reset input signal. This state is undefined'8fter power is applied. The data request control output DTRQ is also an open drain output that requests the CPU to read out the data from the data register or write the data into the data register during the disk read or write operation. The DTRQ output is reset to "0" by writing the data into or reading the data out from the data register. The DTRQ output is changed to "0" by the reset input. (7) Write Control Logic The M5W1791-02P provides frequency-modulated (FM) data in the single-density mode or modified FM (MFM) data in the double-density mode. The data written into the data register from the CPU is sent to the data shift register and then it is modulated by the write control logic in accordance with the modulation type selected by the DDEN input. This modulated data is sent to the write data output WD. The special patterns including the missing clock required for disk formatting are also produced in the write control logic under the control of the write command control circuit. During the disk write operation, M5W1791-02P can predict the occurrence of the peak shift, depending on the previous bit pattern, so the write control logic provides the early and late output signals for write precompensation. (8) Write Track Command Control Logic The internal PlA program controls almost all the operations of the M5W1791-02P. However, when the write track command is executed, the PlA program control speed is too slow to perform the command. Therefore, the write track command control logic implements the write track operation directly. When the CPU writes the data into the data register for disk initialization, the contents are sent to the internal data shift register and the write track command control logic. When a special data byte is sent to the data register from the CPU, the write control logic operates under the control of the write track command control logic the provide the designated write data pattrern. When the other data bytes are written into the data register, they are first sent to the data shift register, then to the write control logic serially to be modulated according to the DDEN input. During the disk read operation, the internal data separator circuit demodulates the raw read data stream and produces the true data bit pattern. This demodulated data bit is shifted into the data shift register in series and transferred to the data register in parallel byte by byte. (2) CRC Logic The CRC (Cyclic Redundancy Check) circuit generates the cyclic redundancy check code. The polymonial is X'6 X12 + X + 1. + S The CRC code, generated by the CRC circuit from the write data stream, is written onto the floppy disk during the disk write operation. During the disk read operation, the last two CRC bytes read out in the 10 or data field are checked for errors by the CRC logic. (3) Prescaler A pair of internal clocks are required to drive the M5W179102P's logic circuitry. During the disk read operation, these clocks are derived from the read clock input RClK from the differential circuit, the data transfer clock logic and the internal clock control logic. At all times except for disk read operations, such as during type 1 commands or disk write operations, these two internal clocks are produced by the prescaler and the internal clock control logic from the ClK input signal. The prescaler generates the data transfer clock and the data separator clock by dividing the ClK input clock by 2 and 4 in the double density mode and by 4 and 8 in the single density mode. The internal PlA logic is driven by this data separator clock. (4) Differential Circuit, Data Transfer Clock Logic The differential circuit and the data transfer clock logic generate the internal data transfer clock by multiplying the PClK clock input and shaping its waveform. (5) Window Extension Logic When disk read operations are executed in the doubledensity mode, the raw read input occurs in both RClK clock windows. At this time, the window extension logic samples the raw read input at the edge of the internal data transfer clock which is derived from the RClK input to provide that the read clock input RClK window width is extended substantially. 8.3 Internal Control Logic (1) Data Shift Register (6) AM Detector Logic During the disk write operation, the data bytes written into the data register from the CPU are loaded into this register in parallel. The data shift register transfers the serial data to the write control logic for modulation. a signal which has been modulated by either FM or MFM. M5W1791-02P should synchronize the internal data separator clock with the data bit of the input data stream. For this The raw read signal input ""R"'"A;-;W-;-O;:R"'EA~D from the floppy disk is • MITSUBISHI .... ELECTRIC 6-15 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER purpose, the AM detector logic is employed to detect the special patterns which contain the missing clocks from' the input raw read stream, (7) Internal Clock Control Logic This logic generates the data transfer clock and data separator clock. (8) Data Separator This separates the data bit from the raw read input signal by using the data separator clock, (9) PLA This is the programmable logic array which controls the M5W1791-02P, The size of this PLA ROM is approximately 230 X 19 bits. 6-16 ," • ,." MITSUBISHI ..... ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 9. DESCRIPTION OF COMMANDS There are 11 different commands. By setting CS to "0", Ao to "0" and A, to "0" the commands are written inside the M5W1791-02P from the data bus at the rising edge of the Table 9.1 WR signal. The commands are classified into four types: type 1, type 2, type 3 and type 4. List of Commands Command type MSB Command Code a a t--Seek command a a Step command a a Step-in command 1 a Step-out command a 1 f - - - - - - - - - - - - - - - - ..- - - - 1----------Read sector command 1 a ----_.---Write sector command 1 a _ . _ - - - - ._---- ----------. Restore command f--~--- Type 1 commands Type 2 commands --- t----- Type 3 commands ---------.-,,-- Type 4 commands -- V r, ro 1 h V r, ro 1 u h V r, a u h V r, ro 1 u h V r, ro a m S E C a S E C ao E a a a a a ------0-- h ro --~ 1 m ------- 1 1 --------1 1 1 a a 1 1 -_.. a a a 0 1 Ie 1 Force interrupt command h a - - j - - - - - - - .. Read track command Write track command a 1 1 Read address command LSB a a -~ _ - _ .. _ - _ . _ - - - - - - - - - - - - - - - 1 E E I, 10 Note 1: Although the codes are written in TRUE form, the M5W1791-02P features a negative logic data bus. This means codes with 0 and 1 reversed are written into the M5W1791-02P. Each command comes with a flag option. These are identified in Table 9.2. • MITSUBISHI .... ELECTRIC 6-17 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER Table 9.2 Flag Options ..... Flag Description When h =1: The head is loaded at the beginning of the command execution. h : Head load flag When h =0: The head is loaded when the verify operation starts if the V flag is "1". It is not loaded if the V flag is "0·'. When V = 1: The contents of the track register are compared with the 10 track address after head V : Verify flag Type 1 positioning. The seek error status bit is set if the desired track address is not found by the time the diskette has gone through 6 rotations. When V =0: The track verification is not performed. commands r1, ro : Stepping rate flag The stepping rate is determined by the value of these 2 bits as well as by the elK frequency and TEST input pin. When u = 1: The track register is updated with each step pulse: It is incremented (or u : Update flag decremented) by 1 for each step-in (or step-out) pulse. When u =0: Track register is not updated. When E = 1: Sampling of the head load timing input starts with the 15ms delay after the head load output has been set to "1". An advance is made to the next step when HOLO'HLOT = "1" is Type 2/Type3 Commands E: 15ms delay flag(at 2MHz clock) established. When E =0: Sampling of the head load timing input starts immediately after the head load output has been set to "1 ". An advance is made to the next step when HOLD' HLOT = "1" is established. The "next step" is the TG43 output update. When m = 1: Multi-sector read/write is performed. Upon completion of one sector read/write, the sector register value is incremented by 1, the next sector is sought and read/write is performed m : Multi-sector read/write flag again. Upon completion of the final sector read/write operation, the next sector is not found even when sought and so at the sixth rotation of the diskette the RNF error bit is set and the operation is concluded. This command can also be concluded with the Type 4 command. When m =0: Read/write for single sector is performed. When S =1: "1" is compared with the 10 side number when the C flag is "1". Type 2 commands S : Side select flag When S =0: "0" is compared with the 10 side number when the C flag is "1". No comparison is performed when C =0. C : Side compare flag When C =1: The S flag and 10 side number are compared. When C =0: The 10 side number is not compared. When 80= 1: The deleted data mark "FS·' (hexadecimal) is written into the data field address ao : Data address mark flag mark. When ao =0: The data mark "FB" (hexadecimal) is written into the data field address mark. r-----c-- When 10 =1: The interrupt request output is set to "H" at the ready input rising edge. When h =1: The interrupt request output is set to "H" at the ready input falling edge. When 12 =1: The interrupt request output is set to "H" with the index pulse input. Type 4 command I : Interrupt condition flag When 13 =1: The command being executed is terminated and the interrupt request output is set to "H" immediately. When 10 =h =12 =13 =0: No interrupt request is generated but the command being executed is terminated. This command is executed so that the interrupt request output, which has been set by the Type 4 command, is reset by the following command write or status read. 6-18 • MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 10. DESCRIPTION OF OPERATION lists the flag options. The M5W1791-02P is provided with an interface section for the CPU system and an interface section for the floppy disk system. 10.1 CPU System Interface Section The CPU interface section is composed of the input/output buffer, input/output control logic, five internal registers, interrupt request control logic and data request control logic. The CPU reads/writes the contents of the internal registers through the M5W1791-02P's data bus. Upon the completion of each command, and interrupt to the CPU is generated by the interrupt control logic. INTRQ is reset by command register write or status register read. The M5W1791-02P generates the data request output OTRQ for the CPU system using its data request control circuit while reading or writing floppy disk data. The time required to transfer one byte of serial data when ClK is 2MHz is 32,us in the single-density mode and 16,us in the double-density mode. However, the maximum time from when OTRQ is set to "H" until the CPU system reads or writes the data is actually shorter than 32,us (or 161' s) and if the service is not completed whithin this time, the lost data status bit is set. When the CPU system does not respond to the first data request for write sector command or write track command within the required time, the subsequent operation of the commands are theminated and the interrupt request output is set. For instance, the service time Tservice (WR) for DTRQ when a write sector command is being executed in the single-density mode is 23.5,us maximum. This is because it takes 41' s for the DTRQ output to be set after the contents of the data register have been transferred to the data shift register, and 4.5,us at most for the M5W1791-02P to transfer data into the data register which has been written in response to DTRQ. In other words, unless the data is serviced within 23.5,us (i.e. 32 - 4 - 4.5 = 23.5,us), there will no longer be time to begin transfer of data from the next data register to the data shift register. For further details, refer to the section dealing with the description of the commands. 10.2 Floppy Disk Interface Section The floppy disk interface section is composed mainly of the floppy disk head control section which relates to the head pOSitioning control and the floppy disk read/write control section which controls the serial data transfer. (1) Floppy Disk Head Control Section For details on the operation of the floppy disk head control section, refer to Section 8.2 (3) on the read control circuit, Section 8.2 (4) on the head load time timer/stepping rate timer, and Section 8.2 (5) on the index pulse counter/sector counter/step pulse counter as well as to Table 9.2 which (2) Floppy Disk ReadlWrite Control Section The floppy disk read/write control section executes the disk read and disk write operations. The disk read and disk write operations have no direct relation to the read and write commands. For instance, when a write sector command is executed, the disk read operation is performed first to find the desired ID. After the 10 is found, the M5W1791-02P writes the sync pattern, data field address mark, data and CRC, after which the command is terminated. Disk Read Operation The M5W1791-02P is applicable to both the single- and double-density recording formats, and selection between these is performed by the ODEN double-density select input. When the disk read operation starts, the write fault input/ VFOE control output WFIVFOE is set to "l". (This pin is pulled up by a 10-kohm resistance since it serves as an opendrain output during signal output. The pin serves as the VFOE output when the write gate output WG = "l".) This output is kept at "l" until the disk read operation is terminated. The VFOE output can be used as the signal that indicates that the Pll circuit employed as the external RClK generator should enter into lock-in operation from its free-running state. The following description is for the single-density mode which is almost the same as the double-density mode. When the disk read operation starts and the 2-byte 00 (HEX) is found, this is treated as a sync pattern and the read gate output RG is set to "H". Address mark FE, FB or F8 (HEX) are retrieved within the 10-byte period that follows. When the address mark is not found, RG is reset to "l" and a retry is made to retrieve the 2-byte 00 (HEX). If the address mark is found on the 10 field and if the ID track address and sector address (and side number also when side compare bit C = "1") are correct, RG is held at "H" until CRC reading is completed and checked. Whether there is a CRe error or not, RG is then reset to "l". When there is no error, the sync pattern of the data field is retrieved. When ID is not found properly, that is, when AM1 cannot be read properly, the values of the track register and track address do not match, the values of the sector register and sector address do not match, the side select flag of the command and side number do not match (when e = 1), or when there is a eRC error in th ID field, RG is reset to "0" and a retry is made to retrieve the 2-byte 00 (HEX). However, when the read address command is executed, the data is read as far as the CRC byte if the sync pattern and AM1 are found properly, and the command is terminated • MrtsuBISHI .... ELECTRIC 6-19 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER regardless of whether there is a CRC error. When the data address mark is found, RG is held at "1" until the data and the CRC are read and CRC check is performed. RG is then reset to "0" regardless of whether there is a CRC error. If the command is single sector read or if a data field CRC error occurs, the INTRQ interrupt request output is set to "1" and the command is terminated. The CRC error status bit is set with a CRC error. The read gate output is active during reading of the valid data stream from the sync field to the CRC. It is the signal that controls the read data tracking sensitivity for the external PLL RCLK generator circuit. Operation in the double-density mode is the same as that for the single density mode except for the following points. In the double density mode the 4-byte "00" or "FF" (HEX) is treated as the sync pattern and the adress marks "A1" "A1" "A1" "FE", "A1" "A1" "A1" "FB", or "A1" "A1" "A1" "F8" Section 10 dealing with the DesCripJioii of Operation with data request output DTRQ duril}g:i;the :disk write operation. When the data is not written during"tn:e same service period, the command is continued with 00 (HEX) as the data which is written. The lost data status bit is set at this time. DRTQ is not reset if it is not serviced. During the disk write operation, the early output or the late output is made active in accordance with the write data. Both output signals are used when the user provides write pre-compensation for the write data output, and they predict late or early peak shifts of the disk write data which is output at the same time. The TG43 output is used to control the writing current of the floppy disk system. It is "0" at the time when the track register contents are 0 to 43, while it is "1" at 44 or above (up to 255). (HEX) are retrieved within the following 16-byte period. Note that the VFOE output is active when the read track command among the type 3 commands is executed but the RG output remains at "0". Also bear in mind the following pOints relating to the disk read operation. Even during the disk read operation, TG43 is updated in accordance with the track register contents before VFOE is made active. During the disk read or write operations mentioned below (the execution of type 2 and 3 commands), the READY input is checked at the beginning of the command's execution and if the input is not ready, the command is terminated, the interrpt request output is set to "1" and an interrupt is generated (this does not apply to type 1 and type 4 commands). In this case, the not ready status bit is set. Disk Write Operation During the disk write operation, the write gate output WG is first set to "1". This enables the user to apply the write fault input to the write fault inputlVFOE VFO control output pin. Then write data are output from output WD. If the write fault input is made active when WG = "1", the command is immediately terminated, interrupt reqest output INTRQ is set to "1", an interrupt is generated, and the write fault status bit is set. When the disk write operation is about to be suspended by the type 4 command and when the type 4 command is accepted into the M5W1791-02P's command register before the data field AM2 data mark or deleted data mark is written, the command is terminated when the type 4 command is written and an interrupt is generated. The type 4 command, which is written during disk write operation for the data field subsequent to the above mark writing, is also acknowledged immediately and the disk write operation is terminated. The CPU system must write the data into the data register during the service period mentioned at the beginning of 6-20 • MITSUBISHI "ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 11. DESCRIPTION OR COMMANDS 11.1 Command Standby Condition After the execution ofa command has been completed, the M5W1791-02P stands by for the next command to be executed. If the head load HDLD has been set to "1" by the previous command and 15 index pulses are counted in the standby condition, the head is unloaded from the media. After this the M5W1791-02P remains into the command standby condition. When a command is written in the command register, the M5W1791-02P comes into operation according to the execution flow for the command. 11.2 Type 1 Commands (1) Restore Command This command is used to position the head to track 00. This command is automatically executed when the reset input is set from "0" to "1". During reset, the h = "0", V = "0" and r" ro ="1,1" flags are set automatically. Refer to Section 8 dealing with the hardware configuration and in particular to Section 8.1 (3) on the track register for details on the execution of the command. When the V flag is "1", the verify operation is performed after the head opsitioning operation. 00 (HEX) is automatically set in the data register. (2) Seek Command This command is used to move the head onto the desired track. After the destination track number is written into the data register and the seek command is written into the command register, step pulses are generated until the contents of both the track register and data register match. The direction of head movement is indicated by direction output DIRC. The contents of the track register are updated every time a step pulse is output. When the V flag ="1", the verify operation is perfomed after the head positioning operation. (3) Step Command ates a single step pulse. When the u flag is "1", the contents of the track register are decremented by 1. When the V flag is "1", the verify operation is performed after the head pOSitioning operation. 11.3 Type 2 Commands Using the type 2 commands, reading/writing the data in the disk's data field is performed. When the desired sector is found, the data is transferred into/from the CPU system using the data request output DTRQ as the data transfer timing signal. Side number comparison and multi-sector read/write can be performed by setting the command flag. (1) Read Sector Command When the read sector command is executed, once the ID field is found properly, the data is sent from the data shift register to the data register and the M5W1791-02P requests through DTRQ that the CPU system read out the data from the data register. (For details on the service time for DTRQ, refer to Section 10 dealing with the Description of Operation.) Unless the CPU reads out the data within the service time, the next data is written from the data shift register into the data register. The data which has not been read is destroyed and the lost data status bit is set. DTRQ is reset by the data register readout, but when the data has not been read out during the service time, DTRQ remains at "1 ". The length of the data fields in each sector is indicated by the sector length of the disk 10. This value is saved inside the M5W1791-02P and DTRQ is generated for the necessary number of times in accordance with this value. The relationship between the number of data in a single sector and the data byte length is shown below. Table 11.3 Data Byte Length Sector length of the disk ID This generates a single step pulse. Direction output DIRC is not changed. Therefore, the head moves toward the same direction as it did the previous time. When the update flag u is "1", the contents of the track register are updated. When the V flag is "1", the verify operation is performed after the head positioning operation. OOH 01H 02H 03H Bytes/sector 128 256 512 1024 bytes bytes bytes bytes When, for instance, the sector length, i.e. the 4th byte of (4) Step-in Command 10 is 00 (HEX), data request output DTRQ is "1" for 128 This command sets direction output DIRC to "1" and generates a single step pulse. When the u flag is "1", the contents of the track regsiter are incremented by 1. When the V flag is "1", the verify operation is performed after the head positioning operation. times unless lost data occurs. If, for example, lost data occurs once, DTRQ is "1" for 127 times. For multi-sector read, refer to the section on flag option m in Table 9.2. Depending upon the data address mark of the data field, the record type status bit can be set. When the data mark is FB (H EX), the record type status bit is set to "0" and when the deleted data mark is F8 (HEX), it is set to "1". (5) Step-out Command This command sets direction output DIRC to "0" and gener- • MITSUBISHI ...... ELECTRIC 6-21 II MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER (2) Write Sector Command When the 10 field is found properly upon execution of the write sector command and the CRC check is completed without any errors detected, the M5W1791-02P generates a single data request output DTRQ. In response to this DTRQ, the CPU must write the data into the data register during the a-byte time (1-byte time is 32,us in the single-density mode and 16,us in the double-density mode with ClK = 2M Hz). Whether or not the service has been performed during the specified time is then determined. When the service has not been performed in the specified time, the lost data status bit is set, the execution of the command is terminated and interrupt request output INTRQ is set to "1 ". When the first service has been performed, the data is written after the sync pattern and AM2 have been written. After a lost data check, there is a 1-byte time delay (with the single-density mode), then the write gate output WG is set to "1", the 6-byte sync field 00 (HEX) is written into the disk, and FB or Fa (HEX) is written depending on the value of the command's data address mark flag aQ. DTRQ is generated and data is written in succession until the number per sector indicated by the 10 data length in that sector is reached. In the double-density mode, the write gate output WG is . set to "1" after 12-byte time delay following the lost data check, the 12-byte sync field 00 (HEX) is written, and the 3byte A1 (HEX) is written, after which the same operation is peformed as for the single-density mode. Unless the data are written into the data register from the CPU system within the prescribed service time for the second and further DTRQ data request outputs, data 00 (HEX) is written on the disk and the lost data status bit is set The behavior of the DTRQ output when lost data is generated is the same as that described in the section on the read sector command. Operations for multi-sector writing are the same as those during the read sector command. 11.4 Type 3 Commands Type 3 commands consist of 3 commands: read address, read track and write track. (1) Read Address Command The 6 bytes of the ID field found first are read out with the execution of the read address command. These 6 bytes in order are: 1) track number, 2) side number, 3) sector number, 4) data length and 5) 2-byte CRC. When data is sent to the data register, data request output DTRQ is generated from the M5W1791-02P and the CPU system is requested to read out the data from the data register. If DTRQ is not serviced within the service time, the lost data status bit is set and the next data is written from the data shift register into the data register as with the read sector command. When 6-22 the read address command is executed, the track number which has been read out is also written· into the sector regsiter of M5W1791-02P along with the CRC check. (2) Read Track Command The read track command serves to read .out all the data of an entire track, beginning and ending upon detection of the index pulse. Unlike the read sector or read address commands, all the data including the gaps and sync pattern are read out. The data are synchronized when the index mark, 10 address mark and data address mark are detected. "Data synchronization" refers to reading the data string from the floppy disk in 1-byte units. Read gate output RG, which gives notification that the sync pattern has been detected, is not output with this command. Neither side number comparison nor CRC check is conducted with the read track command. Unless the CPU read out data within the specified service time as with the other disk read command, the data is lost. (3) Write Track Command The write track command formats the tracks on the disk. Disk formatting requires not only that the gaps, sync pattern, 10 and data are written, but also that the marker including the missing clock and the CRC are written . When this command is executed, the first data request output DTRQ is generated after the head has been loaded into the media. In response to this, the CPU must complete the writing of the data whithin the 3-byte time. Unless the data are serviced during this time, the lost data status bit is set, subsequent commands are terminated the interrupt request output INTRQ is set to "1". When the data is serviced during the specified time, data write starts with the arrival of the index pulse. Then the CPU writes the data into the data register in accordance with the data request output When data written by the CPU are values from F5 to FE (HEX), M5W1791-02P performs special processing consisting of writing the markers and generating and writing the CRC. When other .data from 00 to F4 and FF (HEX) are written into the data register, the value is modulated as it is and written onto the disk. The write track command continues until the next index pulse input IP is detected. If the CPU hasn't loaded the data into the data register within the service time, 00 (HEX) is written and the lost data status bit is set Table 11.4 shows the control bytes of the write track command. •. MITSUBISHI ~ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER Table 11.4 Write Track Command Control Bytes Single-density format Data register contents Function Double-density format Data Clock pattern pattern Data written Function Missing clock onto disk -- OO-F4 r---- F5 Data ragister values are written onto the disk without modification. OO-F4 FF Non-usable ~. Data register values are written onto the disk without modification. Marker A1 is written. eRe is preset. OO-F4 ~ .. ------ - - - -~- Not generated A1 Generated -~ F6 Non-usable F7 2 calculated eRe bytes are written. F8-FB Writing as data. Used for writing data address mark. eRe is preset. Marker C2 is written. 2-byte eRe FF 2 calculated eRe bytes are written. F8-FB e7 Writing as data. Used for writing data address mark. eRe is preset. Generated e2 -- 2-byte eRe Not generated F8-FB Not generated ) Fe Index mark Fe is written. Fe 07 Index mark Fe is written. Fe FA Writing as data. FO FF Writing as data. FO Not generated ~ -- Not generated ------~ FE ID address mark is written. eRe is preset. FE e7 10 address mark is written. eRe is preset. FE Not generated FF Writing as data. FF FF Writing as data. FF Not generated Note: Hexadecimal notation is used throughout. 11.5 Type 4 Commands This command generates the interrupt through detection of conditions or generates the unconditional interrupt other commands may be executed only it the M5W1791-02P is in the standby condition (busy status bit is "a"), but the type 4 command may be executed at any time. When a preceding command is being executed, it is suspended and operation is keyed to the flag bit of the type 4 command. Refer to Table 9.2 for the flag bits. Interrupt request output INTRQ generated by the type 4 command is reset by reading the stauts register data or executing a command after the execution of the type 4 command with 10 -1 3 = "0"- • MITSUBISHI "ELECTRIC 6-23 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER COMMAND STANDBY CONDITION WARM START RESET '0' - '1' COLD START STATUS CLEAR, BUSY STATUS SET NO WHEN WRITE FAULT IS GENERATED TYPE 4 COMMAND IS EXECUTED AT ANY TIME EXCEPT IN COMMAND STANDBY NO COMMAND IS WRITTEN NO COMMAND IS WRITTEN STANDBY FOR NEW COMMAND YES 6-24 '.MITSUBISHI ;"ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER TYPE 1 COMMAND II Notel: 2: The track register, sector register, data register and data shift register are designated TR, SR, DR and DSR, respectively. Information in parentheses indicates the contents of the registers. "H" denotes hexadecimal notation. The 15 ms delay is not applied when the test input TEST is "0". 15 ms is the delay time when clock input elK is 2MHz. • MITSUBISHI "'ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER TYPE 2 COMMAND FROM WARM START 6-26 .JYllfSUBISHI .... ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER II NO • MITSUBISHI ~ELECTRIC J' 1 SECTOR~ WRITE COMPLETE 6-27 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER . TYPE 3 COMMAND FROM WARM START 6-28 .•.. MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER READ TRACK COMMAND READ ADDRESS COMMAND DR-(DSR) DTRQ-'1' SR-TRACK NUMBER NO •. MITSUBISHI .... ELECTRIC 6-29 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 12. STATUS The significance of the bits in the status register differs according to the command. The bit 0 of the status register is set during type 1, 2 and 3 commands to indicate the busy status. When this bit is set, the other status bits may be reset or updated. When the type 4 command has been executed, the busy status bit is reset, but whether the remaining status bits are reset or not depends on whether the previous command is being performed or not when the type 4 command is issued. When M5W1791-02P is in standby, the remaining status bits are reset or updates according to the same status bit configuration as the type 1 command. When the type 4 command has been issued during the execution of the pervious command, the remaining status bits show the status of the previous command. Tables 12.1 and 12.2 show the significance of each status bit. Tabl 12.1 Status Composition ~t Command Bit 7 Type 1 command Ni' Read sector Write sector .. o.E ~~ '"'m Co ~ ! Bit 6 Bit 5 ' Bit 4 Not ready Write protect Head loaded Not ready a Record type Not ready Write protect Bit 2 Bit 1 Bit Seek error CRC error Track 00 Index Busy Record not found CRC error Lost data Data request Busy Write fault Record not found CRC error Lost data Data request Busy 0 Record not found CRC error Lost data Data request Busy a a a a a a Lost data Data request Busy a Data request Busy Track 00 Index a Read track Not ready a a Write track Not ready write protect Write fault No preceding Command Not ready Write protect Head loaded Preceding command Same as definition of status bit based on preceding command. Read address Not ready .,. m 6-30 0 -- 1 Co ~ a Bit 3 • MI&tJBISHI .... ELECTRIC 0 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER Tabe 12.2 Command c---. Type 1 Status Register Contents Status bit Status Status Significance 7 Not ready "1" denotes that the disk is not ready. This status is provided by the OR relationship between the READY input inverted signal and the RESET input inverted signal. 6 Write protect "1" denotes that the disk is in the write protect status. This status is the inverted signal of the write protect input WPRT. 5 Head loaded "1" denotes that the head has been loaded onto the disk and stabilized. This status is provided by the AND relationship between the head load output HDLD and head load timing input HDL T. 4 Seek error "1" denotes that the verify opration was not successful. This status is reset at the beginning of the following command execution. 3 CRC error "1" denotes that there is a CRC error in the ID field. This status is reset at the beginning of the next command execution. (Note 1 ) 2 Track 00 -~ 1 Index "1" denotes that the head is on track 00. This status is the inverted signal of the track 00 input TROG. "1" denotes that the index pulse input IP is active. This status is the inverted signal of IP. Type 2/ 0 Busy "1" denotes that the type 1 command is being executed. After the CPU has written the command, a maximum of 24 clocks for single density and 12 clocks for double-denisty are required for the busy status flag to be set. 7 Write protect "1" denotes that the disk is not ready. This status is produced by the OR relationship between the READY input inverted signal and the RESET input inverted signal. 6 Write protect "1" denotes that the disk is in the write protect status. This status is the write protect input WPRT inverted signal. Record type The record type is set during read. "1" denotes that the address mark of the data field was the deleted data mark. "0" denotes that it was the data mark. During write operations, "1" denotes that the command has been suspended by the write fault iflput. This status is reset when the next command execution begins (Note 1 ) Type 3 5 Write fault Note 1 4 Record not found "1" denotes that the deSignated ID has not been properly detected. This status is reset when the next command execution begins. (Note 1 ) 3 CRC error "1" denotes that a CRC error is detected in the ID field or data field. This status is reset when the following command execution begins. (Note 1 ) 2 Lost data "1" denotes that lost data have arisen. This status is reset when the following command execution begins. (Note 1 ) 1 Data request 0 Busy "1" denotes that reading data from writing data to the data register is requested. This status is the same as the data request output DTRQ. -"1" denotes that the command is being executed. After the CPU system has written the command, a maximum of 24 clocks for single-density and 12 clocks for doubledenistyare required until the busy status flag is set. Refer to Table 12. 1 for details when the type 4 command is executed. • MITSUBISHI "ELECTRIC 6-31 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER DISK FORMATTI~G Disk formatting is performed by the write track command. Formatting examples are giben below for both singledensity 128 bytes/sector based on the IBM 3740 format and double-density 256 bytes/sector based on the IBM system 34 format. 13. Table 13.1 Table 13.2 Disk IBM System 34 Format Transfer byte number 80 12 3 1 50 (Note 1)'12 Disk IBM 3740 Format 3 Transfer byte number 40 6 1 26 (Note 1) ~ 6 1 1 1 1 1 1 11 6 1 128 1 27 (Note 2) 247 Note 2 6-32 Transfer data (HEX) -- FF 00 FC FF 00 FE 00~4C 00 or 01 01~lA 00 F7 FF 00 FB E5 F7 FF FF 1 1 1 1 1 1 22 12 Significance of transfer bytes I I Gap 4 Sync pattern index mark Gap 1 Sync Pattern 10 address mark Track number Side number Sector number Data length 2-byte CRC write Gap 2 Sync pattern Data mark Data 2-byte CRC write Gap 3 Gap 3 1 256 1 54 (Note 2) 598 Note ·1 2 This sequence is repeated 26 times while the sector number is updated. The formatting of one track is then completed. This is the standard value which keeps sending the FF data until the interrupt request output INTRQ is set. • MITSUBISHI ..... ELECTRIC Transfer data (HEX) 4E 00 F6 FC 4E 00 F5 FE 00~4C 00 or 01 01~lA 01 F7 4E 00 F5 FB 40 F7 4E 4E Significance of transfer bytes Gap 4 Sync pattern index mark index mark Gap 1 Sync Pattern 10 address mark 10 address mark Track number Side number Sector number Data length 2-by1e CRC write Gap 2 Sync pattern Data address mark Data mark Data 2-byte CRC write Gap 3 Gap 4 This sequence is repeated 26 times while the sector number is updated. The formatting of one track is then completed. This is the standard value which keeps sending the 4E data until the interrupt request output INTRQ is set. MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 14. TRACK FORMAT Track format is given in Fig. 14. INDEXP~ 10 GAP1 SYNC PATTERN DATA LENGTH CRC 2 BYTES GAP2 E 1ST SECTOR 10 FIELD GAP4 2ND SECTOR DATA FIELD ~ 10 FIELD Fig. 14 15. TYPICAL EXTERNAL READ CLOCK GENERATOR CIRCUIT LAST SECTOR GA P 3 -""'---.;.. Track format A read clock must be applied from an external oscillator with the M5W1791-02P. Described below is an example of an external read clock generator circuit used for an 8-inch floppy disk and employing a PLL circuit. The circuit itself is an analog PLL circuit containing a voltage-controlled oscilator (VCO) with a center frequency of 8M Hz. It is applicable to both single- and double-density modes, and is composed of a phase comparator, filter and VCO. Fig. 15.1 shows the phase coimparator and Fig. 15.2 shows the filter and VCO. In Fig. 15.1 the phase of the raw data read from the floppy disk is compared with the phase fo the signal produced by dividing the VCO CLOCK. If, as a result, the phases do not match, the VCO frequency is tracked by the UP or DOWN signal. When VFOE is not active, the reference clock is input. The filter in Fig. 15.2 acquires the required frequency gain characteristics by means of the NF loop RC elements. C, is for tracking the VCO with respect to the relatively low frequency fluctuations in the form of flutter during floppy disk rotation, etc. In contrast, C 2 is for reducing the VCO gain in the event for relatively high frequency fiuctuatiions. A 74S124 is required for the VCO TTL, since the 74LS124 is not sufficient as the 8MHz voltage-controlled oscillation. R" R2 and R3 determine the gain. R, and R2 are resistances from 500 ohms to 3.3 kohms. R3 has a resistance from 2.2 to 4.7 kohms. C 3 has a capacitance of 47pF for generating an 8MHz frequency when VR is set to its center position and the CO NT input is made 1/2Vee , R4 is for setting the operating pOint of TR, and it is provided with a resistance of 50 kohms to 1 Mohm. Care should be taken with parts layout and writing of the VCO circuit, especially for the power supply and ground line of the 74S124. Vee instability causes a marked deterioration in PLL response. In the above example there is no filter or gain switching by read gate output RG. Note: The circuit in the example given above has low sensitivity to elements value, and works stably. However, the actual circuit used should be determined with regard to the whole system, including the floppy disk system. C, has a capacitance of 0.047/1 F to 0.3/1 F while C2 has a value of 0.0011' F to 0.00331' F. • MITSUBISHI ...... ELECTRIC 6-33 II C"l I w .j>. I~..... ~ ." ~ III III (D () 3 Xl/2 M74LS74AP 0 3 "0 III a g REFERENCE CLOCK (0.5MHz) FROM CRYSTAL OSCILLATOR M74LS37P ~UP ,. r'I~ r-_ T- READ DATA R FROM FLOPPY DISK WG FROM M5W1791-02P II WFIVFOE 1 !-IS FOR SINGLE DENSITY 1/2 M74LS123 FROM M5W1791-02P r'I-I (')(1) -Ie RECORDING DENSITY CONTROL nCi5 FROM CPU SYSTEM TO M5W1791-02P ::111m = DDEN T DOWN R ." r o 1/2 M7 4LS7 4AP "a "a M74LS191P D QD C QC !2 (I) B A RCLK =-: TO M5W1791-02P ." o 200ns ::III LOAD i: E VCO CLOCK (SMHz) T U/D ~ '------~c1A ole> 1/2 M74LS123P RAW READ TO M5W1791-02P ,.. -I I: UI ~ :e! ...-1 Z U) (') o ...... (I) -I ::III ... (I) r r rrI ON r ... (I) ::III "iii o i- I:Z: MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER FROM REGULATED 5V POWER SUPPLY C, O.0022,uF 74S124 1kO C, O. 1,uF 4700 R, 100,uH R, 3. 3kO D, C, UP ---AJVIr----K.t--, 47pF 8200 R, DOWN VCO CLOCK --"'Wv----j~-.......-+_--"vVv--4 8 MHz TR2 D, - D TR,. TR, Fig. 15.2 Filter and : lS1588 : 2SC710 veo 16. TYPICAL WRITE PRECOMPENSATION CIRCUIT Fig. 16 gives an example of a write precompensation circuit. The amount of compensation must be set to a value which regulated for the floppy disk system. Clock generator 74S124, for the VCO of the external read clock generator cirucit in Section 15, has 2-channel VCO's so the extra one can be used also. In this case, the write data pulse width of the M74LS153 in Fig. 16 is determined by the clock and if required, it should be converted to the write data pulse width demanded by the floppy disk system using a one-shot multi-vibrator, etc. CLOCK FOR WRITE PRECOMPENSATION M74LS74AP, ETC. a. '" <;> 0; .... ~ '"::;: ::;: 0 cr LL EARLY OUTPUT EARLY (WRITE PRECOMPENSATION PROHIBIT SIGNAL) D, D, D, Do B A LATE OUTPUT WRITE DATA OUTPUTWD Y WRITE DATA OUTPUT S M74LS153P Fig. 16 Write precompensation circuit • MITSUBISHI ..... ELECTRIC 6-35 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 17. EXAMPLE OF A WRITE GATE OUTPUT AND WRITE FAULTNFO ENABLE CIRCUIT The WFNFOE serves as the write fault input or VFO enable output. dependin'g on the WG output. FROM WG OUTPUT } : > - - - - - - VFOE OUTPUT FROM M5W1791-02P 1 - - - - - WRITE FAULT INPUT FROM FLOPPY DISK SYSTEM ·OPEN COLLECTOR OUTPUT Fig. 17 Write faultlVFOE control circuit 18. AN EXAMPLE OF THE HEAD LOAD OUTPU AND HEAD LOAD TIMING CIRCUIT The head load timing input is made available after the settling time has elapsed from the head load output. FROM HOLD OUTPUT TO HLDT INPUT 6-36 HOLD OUTPUT '. MITSUBISHI "ELECTRIC MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 19 ELECTRICAL CHARACTERISTICS 19.1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vee Supply voltage V, Input voltage Va Output voltage Pd Power dissipation Topr Operating free-air temperature range Tstg Storage temperature range Conditions ------ - -- - - - - - - - - - - Limits Unit -0.5-7 V -0.5-7 V ~ With respect to Vss Ta~25'C -0.5-7 V 350 mW 0-70 'c 'c -65-150 19.2 RECOMMENDED OPERATING CONDITIONS (T a =O-70'C, unless otherwise noted) Limits Symbol Unit Parameter Min Vee Supply voltage Vss Supply voltage V'H High-level input voltage V'L LOW-level input voltage 19.3 Nom Max 5 5.25 4.75 0 V 2 V Vss -Q,5 ELECTRICAL CHARACTERISTICS V 0.8 V (T a =O-70'C, Vcc =5V±5%, unless otherwise noted) Limits Symbol Test condition Parameter Unit Min V OH High-level output voltage IOH=-200"A VOL Low-level output voltage 10L=1. 8mA lee Supply current Typ Max 2.4 V 0.4 V 70 mA Input current.(HDLT, TEST, WFIVFOE, WPRT, I, V,=Vcc-OV -100 10 J-IA Input current other inputs VI=VCC ....... OV -10 10 J-IA Off-state output current V,~Vcc-OV -10 10 J-IA DDEN) -- loz • MITSUBISHI ...... ELECTRIC 6-37 MITSUBISHI LSls MSW1791-02P FLOPP DISK FORMATTER/CONTROLLER 19.4 TIMING REQUIREMENTS (Ta =O-70·C, Vcc=5V±5%, Vss=OV, unlese otherwise noted) Alternativ~ Symbol Limits Parameter Test conditions symbol lSU(A-R) Unit Min Typ Max Address setup time before read and chip select TSET 50 ns Address hold time after read and chip select THLD 10 ns 280 ns 50 ns 10 ns 200 250 20 100 1600 800 800 1600 40 40 40 450 150 ns ns ns ns ns ns ns ns ns ns ns ns ns tSU(CS-R) th(R_A) th(R_CS) tW(R) Read pulse width TRE Address setup time before write and chip select TSET th(W-A) th(w-cs) Address hold time after write and chip select THLD tW(w) Write pulse width tSU(OQ-w) Data setup time before write thew-DO) Data hold time after ",rite tW(RR) Raw read pulse width tC(RR) Raw read cycle time lSUCA-w) C,=50pF tSU(cs-W) tW(RCLK) Read clock high-level width Read clock low-level width tC{RCLK) Read clock cycle time th(RCLK_RR) Read clock hold time before raw read TWE TDS TDH T pw Tbc Ta Tb Tc TX1 th(RR_RCLK) Read clock hold time after raw read TX2 tW(wo) Write data pulse width Twp Tbc TCD, TCD2 TMR TIP TWF tW(RCLK) tC(wo) Write data cycle time tW(. ) tW(. ) Clock high-level pulse width Clock low-level pulse width tW(RESET) Reset pulse width tW(IP) Index pulse width tW(WF) Write fault pulse width 19.5 SWITCHING CHARACTERISTICS (Notel. 2) (Note 3) (Note 4) (Note 4) FM MFM FM MFM 230 200 50 10 10 (Note 5) (Note 5) Test conditidns Parameter tPlH(WG-WO) tPlH(E-WD) Propagation time from early or late to write data Ts MFM (Note 5) 125 Propagation time from write data to early or late Th MFM (Note 5) 125 tPHUWD-l) tPHUWD-WG) Propagation time from write data to write gate Twt tPZV{R_DQ) Output enable time after read tPVZ(R_DQ) Output disable time after read tPHUR-DRO) Propagation time from read to DRO tpHu R-INTRO) Propagation time from read to INTRQ tPHUW-DRQ) Propagation time from write to DRO TDACC TDOH TDRR(RD) TIRR(RD) TDRR(WR) TIRR(WR) TSTP TDIR tPHL(W-INTRO) Propagation time from write to INTRQ tW(STP) Step pulse width tPlH(DIR-STP) Propagation time from direction to step tV(WD-ClK) Write data valid time before clock TWdl tV(ClK-WD) Write data valid time after clock TWd2 Note 1 2 3 4 5 6-38 ---_.Min FM (Note 5) MFM (Note 5) tPlH(l-WO) tPHUWD-E) symbol Twg Propagation time from write gate to write data 500 200 2,3,4 250 250 550 250 ILS 20000 20000 ns ns ILS ILS ILS (T a=O-70·C , Vcc=5V±5% , Vss=ov, unless otherwise noted) Alternative Symbol 250 2000 FM (Note 5) MFM (Note 5) C,-50pF C,-50pF MFM MFM MFM MFM Typ Unit Max 2 1 ILS ILS ns ns 2 1 50 (Note 5) (Note 5) (Note 5) (Note 5) CLK=lMHz CLK=2MHz CLK=1 MHz CLK=2MHz Limrts 2or4 12 200 30 50 50 250 150 250 500 250 500 ILS ILS ns ns ns ns ns ns ILS ILS ns ns ns ns The pulse of RAW READ may be any Width If pulse IS entirely wlthm RCLK. When the pulse occurs m the RCLK Window, RAW READ pulse width must be less than 300 ns for MFM mode and 600 ns for FM mode at CLK=2MHz. Times double for 1MHz. 100 ns pulse width is recommended for the RAW READ pulse in 8 MFM mode. RAW READ cycle time TC(AA) and WD cycle time TC'DfATE TG 43 TG43 OUTPUT HDLD ~D~~dTOAD 27 ~ 26 ~ RCLK FNift?T CLOCK 25 - RG READ GATE OUTPUT RAW READ l~p~lEAD oO~~at EARLY~ 17 LATE ~ 18 ~~~Ot RESET -19 ouMJIf (Ov)v ss 0 --...----~ NC: NO CONNECTION Outline 40P4 systems. The hardware of the M5W1793-02P consists of a floppy disk interface, a CPU interface and a PLA control logic. The total chip can be programmed by eleven 8-bit commands. The floppy disk interface portion performs the communication with the floppy disk drive under control of the PLA control logic. The CPU interface portion has five registers - command, data, status, track and sector register - and communicates with the CPU through the data bus. These functions are also controlled by the PLA. BIDIRECTIONAL DAT~ BUS D, D,DsD,D3D,DIDo 14 13 12 11 10 9 8 7 WRITE CONTROL INPUT WR CHIP SELECT INPUT C§ READ CONTROL INPUT lii5 REGISTER SELECT{Ao INPUT A, 2 3 4 5 6 ""--"o--{'36 WPRT WRITE PROTECT INPUT INDEX PULSE INPUT TRACK 00 INPUT r===t=~~~~==~3 READY READY INPUT II 23 HDLT HEAD LOAD TIMING INPUT TG43 OUTPUT HEAD LOAD OUTPUT DIRECTION OUTPUT STEP OUTPUT '--t-t--'+'t-~ jj5 'i'ROO EARLY OUTPUT EARLY Q;17H!~rrn LATE OUTPUT LATE 18 WRITE GATE OUTPUT WG 3 WRITE DATA OUTPUT WD 31 RAW R~~6' I~~~~ TEST INPUT 27 RCLK READ CLOCK INPUT CLK CLOCK INPUT DDEN DOUBLE DENSITY MODE()3:1}-----<>-----------~ SELECT INPUT 33 RG WFIVFOE RESET READ GATE ~~ITM~gLT RESET INPUT OUTPUT ENABLE OUTPUT 6-40 6MITSUBISHI "ELECTRIC INTERRUPT REQUEST OUTPUT DATA REQUEST OUTPUT MITSUBISHI LSls MSW1793-02P FLOPPY DISK FORMATTER/CONTROLLER 7. PIN DESCRIPTION Pin NC - WR Name NC(pin 1) is not internally connected connection Write control input CS Chip select input Read control input Functions output No internal - RD Input or Input Write signal from a master CPU (Active lOw). Inpul Chip select (Active lowl. Input Read signal from a master CPU (Active low). Register select inputs. These inputs select the register under the control of the RD and Ao. A, Do~D7 Register select input Bidirectional data bus Input - RD WR. - WR A, Ao 0 0 STATUS REGISTER COMMAND REGISTER 0 1 TRACK REGISTER TRACK REG ISTER 1 1 0 SECTOR REGISTER SECTOR REGISTER 1 DATA REGISTER DATA REGISTER InlOut Three-state, non-inverted bidirectional data bus. Step pulse output (Active high). STEP Step output Output DIRC Direction output Output Direction output. High level means the head is stepping in and low level means the head is stepping out. EARLY Early output Output This signal is used for write precompensation. It indicates that the write data pulse should be shifted earty. lATE Late output Output This signal is also used for write precompensation. It indicates that the write data pulse should be shifted late. Reset input (Active low). The device is reset by this signal and automaticaily loads "03" (hexadecimal) into --RESET Reset input Input the command register. The not-ready-status bit is also reset by this signal. When reset input is made to be high, the device executes restore command even unless READY is active and the device loads "01" (hexadecimal) to the sector register. "- -TEST HDlT Test input Head load timing input Input Input ClK Clock input RG Read gate output Output RClK Read clock input Input --- Raw read input Input HDlD Head load output RAW READ Input Output This input is only used for test purposes, so user must tie it to Vce or leave it open unless using voice call actuated motors. When the device finds high level on this input, the device assumes that the head is engaged on the media. Active high. Clock input to generate internal timing. 2MHz for 8-inch drives, 1MHz for mini drives. This signal shows the external data separator that the syncfield is detected. This signal is internally used for the data window, Phasing relation to raw read data is specified but polarity (RCLK high or low) Is not important. This input signal from the drive shall be low for each recorded flux transition. This output signal controls the loading of the head of the drive. The head must be loaded on the media by this high-level output. • MITSUBISHI ..... ELECTRIC 6-41 MITSUBISHI LSls MSW1793-02P FLOPPY DISK FORMATTER/CONTROLLER Name Pin Input or Functions output TG43 TG 43 output Output WG Write gate output Output WD Write data output Output This output is valid only during disk read/write operation and it shows the position of the head. High level on this output indicates that head is posmoned between track 44 to 76. This signal becomes active before disk write operations are to occur. This signal consists of data bits and clock bits. It becomes active for every flux transition. Active high. This signal shows the device the drive is ready. In the disk read/write operation except for TYPE 1 com- READY Ready input Input mand operation, low level input terminates current operation and the device generates the INTRQ. In the TYPE 1 command operation, this signal is neglected. Not ready bit in the status register is the inverted form of this input. This is a bidirectional signal. It becomes write fault input when WG is active. In the disk write operation, --- WFIVFOE Write fault input! VFO enable InlOut low level signal on this input terminates the write operation and makes INTRQ active. This signal also appears in the status register as the write fault bit. When WG is inactive, this signal works as VFO enable -- output. VFOE output is also an open drain type, so pull it up to Vee and never input active write fault signal output write WG is inactive. TROO Track 00 input Input This signal indicates that the head is located on the track 00 to the device. Active low. IP Index pulse input Input This input indicates to the device that an index hole of the diskette has been encountered. --WPRT Write protect Input write operations, this signal is sampled and an active low signal will terminate the current command and --DDEN Double density DTRQ INTRQ NG 6-42 input mode select input Data request output Interrupt request output No internal connection Low level signal on this input informs the device that the drive is in the write protected state. Before disk set INTRQ. The write protect status bit in the status register is also set. Input This input determines the device operation mode. When DDEN=O, double density mode is selected. When DDEN=l, single density mode is selected. DTRQ is an open drain output, so pull up to Vee by the 10k resistor. In the disk read mode, DTRQ indicates Output that data is assembled in the data register. In the disk write mode, it indicates that the data register is empty. DTRQ is reset by the read data or write data operation. Output INTRQ is also a open drain output, so pull up to Vec by the 10k resistor. INTRQ becomes active at the completion of any command and is reset when the CPU reads the status or writes the command. NC (pin 40) is not internally connected. • MITSUBISHI ;"ELECTRIC MITSUBISHI LSls M5W1793-02P FLOPPY DISK FORMATTER/CONTROLLER 8. COMMAND DESCRIPTION There are 11 different commands. By setting CS to "0" ,Ao to "0" and A, to "0", the commands are written into the M5W1793-02P from the data bus at the rising edge of the Table 8.1 WR signal. The commands are classified into four Types Type 2, Type 3 and Type 4. type 1, List of Commands Command type Type 1 commands Command MSB Restore command a Seek cc;>mmand 0 Step command a a h V f, fO 0 1 h V f, fo 0 1 u h V f, fa Slep-in command 0 1 0 u h V f, fa Step-out command 0 1 1 u h V f, fo Read sector command 1 a a m S E C 0 Write sector command 1 0 1 m S E C ao a a 0 E a 0 E 0 Type 2 commands Type 3 commands Type 4 commands LSB Code a a a Read address command 1 1 0 Read track command 1 1 1 Write track command 1 1 1 1 a E 0 a a a Force interrupt command 1 1 0 1 13 12 I, 10 Nole 1: The M5W1793-02P fealufes posilive logic dala bus and so the codes afe wfitten inlo Ihe M5W1793-02P without modificalion. Each command has a flag option. Refer to these options in Table. 8.2. II • MITSUBISHI . ~ELECTRIC 6-43 MITSUBISHI LSls MSW1793-02P FLOPPY DISK FORMATTER/CONTROLLER Table 8.2 Flag Options Flag Description When h =1: The head is loaded at the beginning of the command execution. h : Head load flag When h =0: The head is loaded when the verify operation starts if the V flag is "1". It is not loaded if the V flag is "0". When V =1: The contents of the track register are compared with the 10 track address after head V : Verify flag Type 1 positioning. The seek error status bit is set if the desired track address is not found by the time the diskette has gone through 6 rotations. When V =0: The track verification is not performed. commands n. fO : Stepping rate flag The stepping rate is determined by the value of these 2 bits as well as by the elK frequency and TEST input pin. When u = 1: The track register is updated with each step pulse: It is incremented (or u : Update flag decremented) by 1 for each step-in (or step-out) pulse. When u =0: Track register is not updated. When E =1: Sampling of the head load timing input starts with the 15ms delay after the head load output has been set to "1". An advance is made to the next step when HOLO'HLDT = "1" is Type 2/Type3 Commands E : ISms delay flag(at 2M Hz clock) established. When E =0: Sampling of the head load timing input starts immediately after the head load output has been set to "1 ". An advance is made to the next step when HOLD' HLOT = "1" is estaplished. The "next step" is the TG43 output update. When m =,: Multi-sector read/write is performed. Upon completion of one sector read/write, the sector register value is incremented by 1, the next sector is sought and read/write is performed m : Multi-sector read/write flag again. Upon completion of the final sector read/write operation, the next sector is not found even when sought and so at the sixth rotation of the diskette the RNF error bit is set and the operation is concluded. This command can also be concluded with the Type 4 cOFDmand. When m =0: Read/write for single sector is performed. When S =1: "1" is compared with the 10 side number when the C flag is ",". Type 2 commands S : Side select flag When S =0: "0" is compared with the ID side number when the C flag is ",". No comparison is performed when C =0. C : Side compare flag When C =1: The S flag and ID side number are compared. When C =0: The 10 side number is not compared. When ao= 1: The deleted data mark "FB" (hexadecimal) is written into the data field address ao : Data address mark flag mark. When ao =0: The data mark "FB" (hexadecimal)·is written into the data field address mark. When 10 =1: The interrupt request output is set to "H" at the ready input rising edge. When 1, =1: The interrupt request output is set to "H" at the ready input falling edge. When 1, =1: The interrupt request output is set to "B" with the index pulse input. Type 4 command I : Interrupt condition flag When 13 =1: The command being executed is terminated and the interrupt request output is set to "H" immediately. When 10 = h = 12 = 13 =0: No interrupt request is generated but the command being executed is terminated. This command is executed so that the interrupt request output, which has been set by the Type 4 command, is reset by the following command write or status read. 6-44 • MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSW1793-02P FLOPPY DISK FORMATTER/CONTROLLER 9. ELECTRICAL CHARACTERISTICS 9.1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vee Supply vollage V, Input voltage Va Output voltage Pd Power dissipation T opr Operating free-air temperature range Tstg Storage temperature range 9.2 limits Unit -0.5-7 V -0.5-7 V Conditions With respect to Vss -0.5-7 V 350 mW 0-70 ·C -65-150 ·C Ta=25·C RECOMMENDED OPERATING CONDITIONS -- (T a=0-70·C. unless otherwise noted) Limits Symbol Parameter Unit Min Vee Supply voltage Vss Supply voltage V ,H High-level input voltage V ,L Low-level input voltage 9.3 Nom Max 5 5.25 4.75 0 V 2 V Vss -O.5 ELECTRICAL CHARACTERISTICS V 0.8 V (T a =O-70·C, Vcc =5V±5%, unless otherwise noted) Limits Symbol Unit Test condition Parameter Min V OH High-level output voltage IOH=-200I'A VOL Low-level output voltage IOL=1.8mA lee Supply current Typ Max 2.4 V 0.4 V 70 mA Input current,(HDLT. TEST. WFIVFOE, WPRT, I, loz V,=VCC- OV -100 10 IJ-A Input current other inputs VI=VCC--'- OV -10 10 IJ-A Off-state output current VI=VCC--" OV -10 10 IJ-A DDEN) -- • MITSUBISHI ...... ELECTRIC 6-45 MITSUBISHI LSls MSW1793-02P FLOPPY DISK FORMATTER/CONTROLLER 9.4 TIMING REQUIREMENTS (T a =0-70·C, Vcc=5V±5%, Vss=OV, unlese otherwise noted) limits Alternative Symbol Parameter tSU(A_R) Unit Test conditions symbol Min Typ Max Address setup time before read and chip select TSET 50 ns Address hold time after read and chip select THLD 10 ns 280 ns 50 ns 10 ns 200 250 20 100 1600 800 800 1600 40 40 40 450 150 ns ns ns ns ns ns ns ns ns ns ns ns ns /-is ns ns tSU(CS-R) thCR_A) thcR-cs) Read pulse width TRE Address setup time before write and chip select TSET Address hold time after write and chip select THLD tw(w) Write pulse width tSU{OQ_w) Data setup time before write th(W-DQ) Data hold time after write tW(RRl Raw read pulse width tC(RR) Raw read cycle time tW(RCLK) Read clock high-level width tW(RCLK) Read clock low-level width tC(RCLK) Read clock cycle time th(RClK_RR) Read clock hold time before raw read TWE TDS TDH T pw Tbc Ta Tb Te TX1 th(RR-RCLK) Read clock hold time after raw read Txz tW(wo) Write data pulse width Twp tecWD) twc. ) t w (' ) Write data cycle time Tbe TCD , TCDz TMR TIP TWF tW(R) tSU(A-W) CL =50pF tSU(cs-w) thCW_A) thcw-cs) Clock high-level pulse width Clock low-level pulse width tW(RESETl Reset pulse width Index pulse width tW(IP) Write fault pulse width tW(WF) 9.5 SWITCHING CHARACTERISTICS (Notel. 2) (Note 3) (Note 4) (Note 4) FM MFM FM MFM 230 200 50 10 10 (Note 5) (Note 5) tPLH(E_WD) tPHL(WD_E) Twg FM (Note 5) MFM (Note 5) Propagation time from early or late to write data Ts MFM (Note 5) 125 Propagation time from write data to early or late Th MFM (Note 5) 125 tPHL(WD-WG) Propagation time from write data to write gate Twt tPZV(R-DOJ Output enable time after read tPVZ(R-DO) Output disable time after read tPHUW-INTRQ) Propagation time from write to INTRQ tW(STP) Step pulse width tPLH(DIR_STP} Propagation time from direction to step TDACC TDOH TDRR(RD) TIRR(RD) TDRR(WR) TIRR(WR) TSTP TDIR tV(WD_CLK) Write data valid time before clock TWd1 tV(CLK.WDJ Write data valid time after clock Twdz tPHUR-DRQ) Propagation time from read to ORO tPHL(R_INTRO) Propagation time from read to INTRQ tPHUW_DRO) Propagation time from write to ORO Note 1 2 3 4 5 6-46 /-is /-is /-is Unit Min Propagation time from write gate to write data tPHUWD-Ll 20000 20000 Test conditidns symbol tPLH(L_WD) 550 250 Umrts Parameter tPLH(WG.WD) 500 200 2,3,4 250 250 (Ta =0-70·C, Vcc =5V±5%, Vss=OV, unless otherwise noted) Alternative Symbol 250 2000 FM (Note 5) MFM (Note 5) CL =50pF CL =50pF MFM MFM MFM MFM Max 2 1 /-is /-is ns ns 2 1 50 (Note 5) (Note 5) (Note 5) (Note 5) CLK=l MHz CLK=2MHz CLK-l MHz CLK-2MHz Typ 20r4 12 200 30 50 50 250 150 250 500 250 500 /-is /-is ns ns ns ns ns ns /-is /-is ns ns ns ns The pulse of RAW READ may be any Width If pulse IS entirely within RCLK. When the pulse occurs In the RCLK Window, RAW READ pulse width must be less than 300 ns for MFM mode and 600 ns for FM mode at CLK=2MHz. Times double for 1MHz. 100 ns pulse width is recommended for the RAW READ pulse in 8 MFM mode. RAW READ cycle time T CCRR) and WD cycle time TCCWD) is normally 2/-is in MFM and 4/-is in FM. Times double when CLK=l MHz. The polarity of RCLK during RAW READ is not important. Times double when CLK=lMHz. • MITSUBISHI .... ELECTRIC MITSUBISHI LSls MSW1793-02P FLOPPY DISK FORMATTER/CONTROLLER 9.6 TIMING DIAGRAM Read Write -16 OR 32;lS -16 OR 32;lS OTRQ OTRQ INTRQ INTRQ Ao, A" Ao, 1. CS CS PO-;-;~~UT) --------- DO-07 (INPUT) Nole 6: 7: maximum value, FM: 27. 5;lS, MFM: 13. 5;lS maximum value; FM: 23. 5;lS, MFM: 11. 5;lS Write data Input data e J:: te(RRl ~tt:;;;;;;--;~===:;['J IW(RCLK) .J1 th(RCLK-AR) __ l\.....J RAW READ RCLK ISERvleE(RD) ISERVICE(WR) ~ It le(RcLK) I WIRCLK ) -( "-- th(RR-ACLKJ tPLH(E-WO) tpHUWD-EJ II 1 L -1 1 t'---tpLH(l-WOJ tpHUWD-Ll CLK~ wo tV(WD-CLKl tV(CLK-WOJ Others 10. OTHERS Refer to the description of M5W1791-02P for further information, • MITSUBISHI "ELECTRIC 6-47 CONTACT ADDRESSES FOR FURTHER INFORMATION FRANCE Mitsubishi Electric Europe GmbH 65 Avenue de Colmar Tour Albert 1er F-92507 Rueil Malmaison Cedex, France Telex: 202267 (MELCAM F) Telephone: (01) 7329234 Facsimile: (01) 7080405 JAPAN Electronics Marketing Division Mitsubishi Electric Corporation 2-3, Marunouchi 2-chome Chiyoda-ku, Tokyo 100, Japan Telex: 24532 MELCO J Telephone: (03) 218-3473 (03) 218-3499 Facsimile: (03) 214-5570 U.S.A. NORTHWEST Mitsubishi Electronics America, Inc. 1050 East Arques Ave. Sunnyvale, Ca 94086, U.S.A. Telex: 172296 MELA SUVL Twx: 910-339-9549 Telephone: (408) 730-5900 Facsimile: (408) 730-4972 Overseas Marketing Manager Kita-Itami Works 4-1, Mizuhara, Itami-shi, Hyogo-ken 664, Japan Telex: 526408 KMELCO J Telephone: (0727) 82-5131 Facsimile: (0727) 72-2329 SOUTHWEST Mitsubishi Electronics America, Inc. 991 Knox St. Torrance, CA 90502, U.S.A. Telex: 664787 MELA TRNC Telephone: (213) 515-3993 Facsimile: (213) 324-6578 HONG KONG Ryoden Electric Engineering Co., Ltd. 22nd fl., Leighton Centre 77, Leighton Road Causeway Bay, Hong Kong Telex: 73411 RYODEN HX Telephone: (5) 7907021 Facsimile: (852) 123-4344 SOUTH CENTRAL Mitsubishi Electronics America, Inc. 2105 Luna Road, Suite 320 Canollton, TX 75006, U.S.A. Telephone: (214) 484-1919 Facsimile: (214) 243-0207 SWEDEN Mitsubishi Electric Europe GmbH Lastbilsvagen 6B 5-19149 Sollentuna, Sweden Telex: 10877 (meab S) Telephone: (08) 960468 Facsimile: (08) 966877 NORTHERN Mitsubishi Electronics America, Inc. 15612 HWY 7 #243 Minnetonka, MN 55345, U.S.A. Telex: 291115 MELA MTKA Telephone: (612) 938-7779 Facsimile: (612) 938-5125 WEST GERMANY Mitsubishi Electric Europe GmbH Head Quater Gothear Str. 6 4030 Ratingen 1, West Germany Telex: 8585070 MED'D Telephone: (02102) 4860 Facsimile: (02102) 486-115 NORTH CENTRAL Mitsubishi Electronics America, Inc. 799 North Bierman Circle, Mt. Prospect, IL 60056, U.S.A. Telex: 270636 MESA CHIMPCT Telephone: (312) 298-9223 Facsimile: (312) 298-0567 U.K. Mitsubishi Electric (U.K.) Ltd. Centre Point, (18th Floor) 103 New Oxford st., London WC1, England, U.K. Telex: 296195 MELCO G Telephone: (01) 379-7160 Facsimile: (01) 836-0699 TAIWAN MELCO TAIWAN Co., Ltd. 6th fl., Chung-Ling Bldg., 363, Sec. 2, Fu-Hsing S. Road Taipei, R.O.C. Telephone: (704) 0247 Facsimile: (704) 4244 NORTHEAST Mitsubishi Electronics America, Inc. 200 Unicorn Park Drive Woburn, MA 01801, U.S.A. Telex: 951796 MELA WOBN Twx: 710-348-1229 Telephone: (617) 938-1220 Facsimile: (617) 938-1075 MID-ATLANTIC Mitsubishi Electronics America, Inc. Two University Plaza Hackensack, NJ 07601, U.S.A. Telex: 132205 MELA HAKI Twx: 710-991-0080 Telephone: (201) 488-1001 Facsimile: (201) 488-0059 SOUTH-ATLANTIC Mitsubishi Electronics America, Inc. 6575 The Carners Parkway. Suite 100 Norcross, GA 30092, U.S.A. Twx: 910-380-9555 Telephone: (404) 662-0813 Facsimile: (404) 662-5208 SOUTHEAST Mitsubishi Electronics America, Inc. Town Ex. CTR. 6100 Glades Rd. # 210 Boca Raton, FL 33433, U.S.A. Twx: 510-953-7608 Telephone: (305) 487-7747 Facsimile: (305) 487-2046 • MITSUBISHI .... ELECTRIC ITALY Mitsubishi Electric Europe GmbH Centro Direzionale Colleoni Palazzo Cassiopea 1 20041 Agrate Brianza I-Milano Telephone: (039) 636011 Facsimile: (039) 6360120 AUSTRALIA Mitsubishi Electric Australia Pty. Ltd. 73-75, Epping Road, North Ryde, N.S.W. 2113 Australia P.O. Box 1567 Macquarie Centre N.S. W. 2113 Australia Telex: MESYD AA 26614 Telephone: (02) 888-5777 Facsimile: (02) 887-3635 MITSUBISHI DATA BOOK MICROPROCESSORS AND PERIPHERAL CIRCUITS July, First Edition 1985 Editioned by Committee of editing of Mitsubishi Semiconductor Data Book Published by Mitsubishi Electric Corp., Semiconductor Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. MITSUBISHI SEMICONDUCTORS MICROPROCESSORS AND PERIPHERAL CIRCUITS 1985 ~MITSUBISHI ELECTRIC CORPORATION HEAD OFF IC E M ITSU BI5HI DENKI BLDG H-C5267 -C KI-8509 Printed in Japan (ROD) MA RUNOUC HI. TOKYO 100 TE LEX J2453 2 CA BLE M ELCO TOKYO Revised publication , effective Sept. 1985 . superseding public ation H-C5267-B of Ju l. 1985 . Spec ific ation s subj ect to change without noti ce.