1985_Motorola_Telecommunications_Device_Data 1985 Motorola Telecommunications Device Data

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Selection Guides •

Data Sheets •

Application Notes and •
Technical Articles

Glossary.

Handling and Design . .
Guidelines . .

Quality and Reliability •

Mechanical Data

II

,

MOTOROLA
TELECOMMUNICATIONS
DEVICE DATA
Prepared by
Technical Information Center

Motorola is a major supplier of Semiconductors to Telecommunications equipment manufacturers worldwide, and our data manuals for such standard products as dedicated MOS
and Bipolar Telecom ICs, CMOS Special Circuits, High-Speed CMOS, ECl, TIL, Linear,
Power Transistors, Microprocessors, and Memories, are on the reference shelves of
designers throughout the industry.
This data book pulls together Motorola's Semiconductor Products which are dedicated to
applications in Telecommunications. It reflects both the growing portfolio of Motorola
devices for Telecommunications and the need for designers to have product information at
hand in a convenient form.
Many of the products presented here are new, for new applications in an industry which is
presently one of the most dynamic and fastest growing-Telecommunications. It was possible only to include a limited amount of application material. Hence these products are supported by applications and product specialists within the Motorola Semiconductor organizations. Should you require further details or assistance in designing with any of these
devices, your Motorola Semiconductor Sales Office can put you in touch with the relevant
expertise within our organization.
Motorola reserves the right to make changes to any product herein to improve reliability,
function or design. Motorola does not assume any liability arising out of the application or
use of any product described herein; neither does it convey any license under its patent
rights nor the rights of others.
Motorola, Inc. general policy does not recommend the use of its components in life support applications, where in a failure or malfunction of the component may directly threaten
life or injury. Per Motorola Terms and Conditions of Sale, the user of Motorola components in
life support applications assumes all risk of such use and indemnifies Motorola against all
damages.

Series B

© MOTOROLA INC., 1985
Printed in U.S.A.

Previous Edition ©1984
"All Rights Reserved"

ALPHANUMERIC INDEX
This index includes all Motorola devices used specifically in telecommunication applications. Information for the devices identified with page numbers appears in this book. All
other devices are fully characterized in the book referenced at the right of the device
number.
Linear- See
MECL- See
MCU - See
MPU - See
Opto - See
RZD - See
SF
- See
SS
- See

Device
Number

MC1374
MC1376
MC1496
MC1648
MC3356
MC3357
MC3359
MC3361
MC3362
MC3393
MC3396
MC3416
MC3417
MC3418
MC3419
MC3419-1 L
MC34F19
MC3517
MC3518
MC6172
MC6173
MC6800
MC6801
MC6804
MC68HC04
MC6805
MC68HC05
MC6809
MC6850
MC68HC51
MC6852
MC68HC53
MC6854

DL 128, Linear and Interfaces Integrated Circuits
DL 122R1, MECL Device Data
DL 132R1, Single-Chip Microcomputer Data
DL133, 8-Bit Microprocessor & Peripheral Data
DL 118R1, Optoelectronics Device Data
DL 125, Rectifier and Zener Diodes Data
DL 130, CMOSINMOS Special Functions Data
DL 126, Small-Signal Transistor Data

Function

TV Modulator Circuit ....................... .
FM Modulator Circuit ....................... .
Balanced Modulator-Demodulator ........................... .
Voltage-Controlled Oscillator ............................... .
Wideband FSK Receiver ................................... .
Low Power FM IF ......................................... .
High Gain Low-Power FM IF ................................ .
Low-Voltage Narrow-Band FM IF. .
. ........... .
Low Voltage FM/FSK Receiver ............................. .
Two-Modulus Prescaler .................................... .
Divide-by-20 Prescaler ..................................... .
Crosspoint Switch (4 x 4 x 2) ................................ .
CVSD Modulator-Demodulator (3-Bit Algorithm) .............. .
CVSD Modulator-Demodulator (4-Bit Algorithm) .............. .
See MC34F19 ............................................ .
Subscriber Loop Interface Circuit ............................ .
Subscriber Loop Interface Circuit ............................ .
CVSD Modulator-Demodulator (3-Bit Algorithm)
CVSD Modulator-Demodulator (4-Bit Algorithm) .............. .
2400 bps Digital Modulator (DPSK) ..................... .
2400 bps Digital Demodulator (DPSK) ................... .
8-Bit Microprocessor Unit ............................. .
8-Bit Microcomputer Unit ........................... .
8-Bit Microcomputer Unit .................................. .
8-Bit HCMOS Microcomputer Unit .......................... .
8-Bit HMOS Microcomputer Series .......................... .
8-Bit HCMOS Microcomputer Series ......................... .
8-Bit Microprocessing Unit ................................. .
Asynchronous Communications Interface Adapter ............. .
Asynchronous Communications Interface Adapter ............. .
Synchronous Serial Data Adapter ........................... .
Asynchronous Communications Interface Adapter ......... .
Advanced Data-Link Controller .............................. .

iii

Page
Number

Linear
Linear
Linear
MECL
Linear
Linear
Linear
Linear
Linear
Linear
Linear
2-3
2-12
2-12
2-30
2-46
2-12
2-12
2-62
2-70
MPU
MCU
MCU
MCU
MCU
MCU
MPU
MPU
MPU
MPU
MPU
MPU

Device
Number
MC6860
MC12002
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
MC12018
MC12019
MC12022
MC12023
MC12071
MC12073
MC12074
MC12090
MC13010
MCl4400
MCl4401
MCl4402
MC14403
MC14405
MC14408
MC14409
MCl4410
MCl4411
MC14412
MC14413-1
MC14413-2
MC14414-1
MC14414-2
MCl4416
MCl4417
MCl4418
MCl4419
MC34010
MC34011
MC34012
MC34013
MC34014
MC34017
MC34018
MC34129
MC142100
MC142101
MC142103
MC143403
MC143404

Function
0-600 bps Modi Demodulator (Bell 103) ....................... .
Analog Mixer ............................................. .
Two-Modulus Prescaler (+ 51 + 6) ........................... .
Two-Modulus Prescaler (+ 81 + 9) ........................... .
Two-Moduls Prescaler (+ 101 + 11) ...................... '.... .
Low-Power Two-Modulus Prescaler (+ 321 + 33) ............... .
Low-Power Two-Modulus Prescaler (+48+ 41) ................ .
Low-power Two-Modulus Prescaler (+ 641 + 65) ............... .
520 MHz Low-Power Prescaler (+ 1281 + 129) ............. , ... .
Low-Power Two-Modulus Prescaler (+ 201 + 21) .. , ............ .
1.0 GHz Low-Power Two-Modulus Prescaler (+ 1281 + 129) ..... .
Low-Power Prescaler (+ 64) ................................ .
High-Speed Prescaler (+ 641 + 256) .......................... .
Low-Power Prescaler (+ 64) ................................ .
Low-Power Prescaler (+ 256) ............................... .
High-Speed Prescaler(+2) ................................. .
TV Parallel Sound IF and AFT ............................... .
Single-Chip PCM Codecl Filter Mono-circuit .................. .
Single-Chip PCM Codec/Filter Mono-circuit .................. .
Single-Chip PCM Codecl Filter Mono-circuit .................. .
Single-Chip PCM Codem/Filter Mono-circuit .................. .
Single-Chip PCM Codecl Filter Mono-circuit .................. .
Binary to Phone Pulse Converter ............................ .
Binary to Phone Pulse Converter ............................ .
2-of-8 Tone Encoder ....................................... .
Bit Rate Generator ........................................ .
0-600 bps Modulator (8e111031CCITT V.21) ................... .
PCM Band-Pass/Low-Pass Filter (CCITT) ..................... .
PCM Band-Pass/Low-Pass Filter (D3/D4) .................... .
PCM Dual Low-Pass Filter (CCITT) .......................... .
PCM Dual Low-Pass Filter (031 D4) .......................... .
Time Slot Assigner Circuit (Serial) ........................... .
Time Slot Assigner Circuit (Parallel) .......................... .
Time Slot Assigner Circuit (Programmable) ................... .
2-of-8 Keypad-to-Binary Encoder ............................ .
Electronic Telephone Circuit (MCU Interface) .................. .
Electronic Telephone Circuit ................................ .
Telephone Tone Ringer .................................... .
Speech Network and Tone Dialer ............................ .
Telephone Speech Network With Dialer Interface .............. .
Telephone Tone Ringer .................................... .
Speakerphone Network .................................... .
Low Power Switching Power Supply ......................... .
Crosspoint Switch With Control Memory (4 x 4 x 1) ............ .
Crosspoint Switch With Control Memory (4 x 4 x 2) ............ .
Transcoder .............................................. .
Quad Line Driver ............................ :.............. .
Quad Line Driver .......................................... .

iv

Page
Number
2-85
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
Linear
2-99
2-99
2-99
2-99
2-99
2-113
2-113
2-121
2-125
2-128
2-134
2-134
2-134
2-134
2-149
2-169
2-149
2-173
2-177
2-177
2-201
2-209
2-224
2-241
2-249
2-263
2-269
2-270
2-271
2-271

Device
Number
MC145026
MC145027
MC145028
MC145029
MC145100
MC145106
MC145145
MC145146
MC145151
MC145152
MC145155
MC145156
MC145157
MC145158
MC145159
MC145168
MC145402
MC145406
MC145409
MC145411
MC145412
MC145413
MC145414
MC145415
MC145418
MC145419
MC145421
MC145422
MC145425
MC145426
MC145428
MC145429
MC145432
MC145433
MC145439
MC145440
MC145441
MC145445
MC14545C
MC146805
MC68000
MC68153
MC68590
MC68452
MC68652
MC68661
MC68681
MC68901

Function
Programmable Encoder .................................... .
Programmable Decoder .................................... .
Programmable Decoder .................................... .
Prouammable Decoder. . . . . . . . . . . . . . . .. . ................. .
Crosspoint Switch With Control Memory (4 x 5 xl) ............ .
PLL Parallel Programmable Frequency Synthesizer ............. .
PLL 4-Bit Data Bus Programmable ........................... .
PLL 4-Bit Data Bl1s Programmable ........................... .
PLL Parallel Programmable ................................. .
PLL Parallel Programmable ................................. .
PLL Serial Programmable .............................. .
PLL Serial Programmable .................................. .
PLL Serial Programmable .................................. .
PLL Serial Programmable .................................. .
PLL Serial' Programmable .................................. .
Dual PLL 4-Bit BCD Programmable .......................... .
13-Bit Linear Codec ....................................... .
RS-232IV.28 Driver/Receiver ............................... .
Integrated Pulse Dialer With Redial .......................... .
Bit Rate Generator ........................................ .
PulselTone Repertory Dialer ................................ .
Pulse/Tone Repertory Dialer ................................ .
Dual Tunable Low-Pass Sampled Data Filter .................. .
Dual Tunable Linear Phase Low-Pass Sampled Data Filter ....... .
Digital-Loop Transceiver (Master) ........................... .
Digital-Loop Transceiver (Slave) ............................. .
160 kbps ISDN UDLT (Master) .............................. .
Universal Digital Loop Transceiver (2-Wire Master) ............. .
160 kbps ISDN UDL T (Slave) ............................... .
Universal Digital Loop Transceiver (2-Wire Slave) .............. .
Data Set Interface (D S I) ................................... .
Telset Audio Interface Circuit (TAlC) ......................... .
Notch/ Band-Pass 2600 Hz Tone Signalling Filter ............... .
Tunable Notch/ Band-Pass Filter ............................ .
Transcoder .............................................. .
300 bps Modem Band-Pass Switch Capacitor Filter (Bell 103) .... .
300 bps Modem Band-Pass Switch Capacitor Filter (CCITT V.21) ..
0-600 bps Mod/Demodulator (Belll03/CCITT V.21) ............ .
0-1800 bps Mod/Demodulator (BeI1202/CCITT V.23) ........... .
8-Bit CMOS Microprocessor Series .......................... .
16-Bit Microprocessor ..................................... .
Bus Interrupter Module .................................... .
LAN Controller for Ethernet ................................. .
Bus Arbitration Module .................................... .
Multi-Protocol Communications Controller .................... .
Enhanced Programmable Communications Interface ........... .
Dual Asynchronous Receiver/Transmitter (DUART) ............ .
Multi-Function Peripheral .................................. .

v

Page
Number
SF
SF
SF
SF
2-263
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
2-275
2-276
2-282
2-288
2-291
2-291
2-297
2-304
2-309
2-309
2-323
2-324
2-323
2-324
2-343
2-356
2-365
2-371
2-377
2-378
2-384
2-390
2-395
MCU

Device
Number

Function

Page
Number

DISCRETE DEVICES

MO-sorb Zener Overvoltage Suppressors ..................... .
1N6274
4N25
Opto Coupler ............................................. .
MDA220
Bridge Rectifier ............................ : .............. .
MFODll00
Pin Photo Diode for Fiber Optic Systems ...................... .
High-Power AIGaAs LED Fiber Optic Emitter .................. .
MFOE1200
MPN Power Transistors .................................... .
MJE270
MJE270
PNP Power Transistors .................................... .
MOC3030
Zero Voltage Crossing Optically Isolated Triac Driver ............ .
MPSA42/43 NPN 300 V1200 V TO-92 Transistors ......................... .

vi

RZD
Opto
RZD
Opto
Opto
Power
Power
Opto
SS

Selection Guides •

1-1

•

1-2

SELECTOR GUIDE
This index includes all Motorola devices used specifically in telecommunication applications. Information for the devices identified with page numbers appears in this book. All
other devices are fully characterized in the book referenced at the right of the device
number.
Linear- See
MECL-See
MCU - See
MPU - See
Opto - See
RZD - See
SF
- See
SS
- See

DL 128, Linear and Interfaces Integrated Circuits
DL122R1, MECL Device Data
DL132R1, Single-Chip Microcomputer Data
DL 133, 8-Bit Microprocessor & Peripheral Data
DL 118R1, Optoelectronics Device Data
DL 125, Rectifier and Zener Diodes Data
DL 130, CMOSINMOS Special Functions Data
DL 126, Small-Signal Transistor Data

Device
Number

Function

Page
Number

PCM Band-Pass/Low-Pass Filter (CCITT) ..................... .
PCM Band-Passl Low-Pass Filter (03/04) .................... .
PCM Dual Low-Pass Filter (CCITT) .................... .
PCM Dual Low-Pass Filter (03/04) .......................... .
Dual Tunable Low-Pass Sampled Data Filter .................. .
Dual Tunable Linear Phase Low-Pass Sampled Data Filter ....... .
Notchl Band-Pass 2600 Hz Tone Signalling Filter ............... .
Tunable Notchl Band-Pass Filter ............................ .
300 bps Modem Band-Pass Switch Capacitor Filter (Bell 103) .... .
300 bps Modem Band-Pass Switch Capacitor Filter (CCITT V.21) ..

2-134
2-134
2-134
2-134
2-297
2-304
2-365
2-371
2-378
2-384

FIL TERS

MC14413-1
MC14413-2
MC14414-1
MC14414-2
MC145414
MC145415
MC145432
MC145433
MC145440
MC145441

CENTRAL SWITCHING EQUIPMENT

MC3417
MC3418
MC3419
MC3419-11
MC34F19
MC3517
MC3518
MC14400
MC14401
MC14402
MC14403
MC14405
MC14416
MC14417
MC14418
MC142103
MC145439

CVSD Modulator-Demodulator (3-Bit Algorithm) ....... .
CVSD Modulator··Demodulator (4-Bit Algorithm)
See MC34F19 ....................................... .
Subscriber Loop Interface Circuit ............................ .
Subscriber Loop Interface Circuit ............................ .
CVSD Modulator-Demodulator (3-Bit Algorithm) .............. .
CVSD Modulator-Demodulator (4-Bit Algorithm) ..
. ....... .
Single-Chip PCM C6dec/Filter Mono-Circuit .................. .
Single-Chip PCM Codec/Filter Mono-Circuit .................. .
Single-Chip PCM Codec/Filter Mono-Circuit .................. .
Single-Chip PCM Codel Filter Mono-Circuit ................... .
Single-Chip PCM Codecl Filter Mono-Circuit .................. .
Time Slot Assigner Circuit (Serial) ........................... .
Time Slot Assigner Circuit (Parallel) .......................... .
Time Slot Assigner Circuit (Programmable) ................... .
Transcoder .............................................. .
Transcoder .............................................. .

1-3

2-12
2-12
2-30
2-46
2-12
2-12
2-99
2-99
2-99
2-99
2-99
2-149
2-169
2-149
2-270
2-377

•

•

Device
Number

Page
Number

Function

CROSSPOINT SWITCHES

MC3416
MC142100
MC145100
MC142101

Crosspoint
Crosspoint
Crosspoint
Crosspoint

Switch
Switch
Switch
Switch

(4 x 4 xl) ................................
With Control Memory (4 x 4 xl) ............
With Control Memory (4 x 4 xl) ............
With Central Memory (4 x 4 x 2) .............

.
.
.
.

2-3
2-263
2-263
2-269

Low Power Switching Power Supply ......................... .
Digital-Loop Transceiver (Master) ........................... .
Digital-Loop Transceiver (Slave) ............................. .
Universal Digital Loop Transceiver (2-Wire Master) ............. .
Universal Digital Loop Transceiver (2-Wire Slave) .............. .
Data Set Interface (oSI) ................................... .
Telset Audio Interface Circuit (TAlC) ......................... .
160 kbps ISDN UDLT (Master) .............................. .
160 kbps ISDN UDLT (Slave) ............................... .

2-309
2-309
2-324
2-324
2-343
2-356
2-323
2-323

INTEGRATED VOICE/DATA

MC34129
MC145418
MC145419
MC145422
MC145426
MC145428
MC145429
MC145421
MC145425

*

CORDED TELEPHONE

MC34010
MC34011
MC34012
MC34013
MC34014
MC34017
MC34018
MC34129
MCl4408
MCl4409
MCl4410
MCl4419
MC145409
MC145412
MC145413
MC145426
MC145428
MC145429

Electronic Telephone Circuit (MCU Interface) .................. .
Electronic Telephone Circuit ................................ .
Telephone Tone Ringer .................................... .
Speech Network and Tone Dialer ............................ .
Telephone Speech Network With Dialer Interface .............. .
Telephone Tone Ringer .................................... .
Speakerphone Network .................................... .
Low Power Switching Power Supply ......................... .
Binary to Phone Pulse Converter ............................ .
Binary to Phone Pulse Converter ............................ .
2-of-8 Tone Encoder ....................................... .
2-to-8 Keypad-to-Binary Encoder ............................ .
Integrated Pulse Dialer With Redial .......................... .
Pulse/Tone Repertory Dialer ................................ .
Pulse/Tone Repertory Dialer ................................ .
Universal Digital Loop Transceiver (2-Wire Slave) .............. .
Data Set Interface (oS!) .............................. _.... .
Telset Audio Interface Circuit (TAlC) ......................... .

2-177
2-177
2-201
2-209
2-224
2-241
2-249
*

2-1 i3
2-113
2-121
2-173
2-282
2-291
2-291
2-324
2-343
2-356

CORDLESS TELEPHONE

MC1376
MC1496

FM Modulator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Balanced Modulator-Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1·4

Linear
Linear

Device
Number
MC3356
MC3357
MC3359
MC3361
NC3362
MC12002
MC12015
MC12016
MC12017
MC12019
MC34012
MC34013
MC34014
MC145026
MC145027
MC145028
MC145029
MC145106
MC145145
MC145146
MC145151
MC145152
MC145155
MC145156
MC145157
MC145158
MC145168
MC145409
MC145412
MC145413

Function

Page
Number

Wideband FSK Receiver ................................... .
Low Power FM IF ......................................... .
High Gain Low-Power FM IF ................................ .
Low-Voltage Narrow-Band FM IF ............................ .
Low Voltage FM/FSK Receiver ............................. .
Analog Mixer ............................................. .
Low-Power Two-Modulus Prescaler (-;- 32/ -;- 33) ............... .
Low-Power Two-Modulus Prescaler (-;- 40/ -;- 41) ............... .
Low-Power Two-Modulus Prescaler ( -;- 64/ -;- 65) ............... .
Low-Power Two-Modulus Prescaler ( -;- 28/ -;- 21) ............... .
Telephone Tone Ringer .................................... .
Speech Network and Tone Dialer ............................ .
Telephone Speech Network With Redialer Interface ............ .
Programmable Encoder .................................... .
Programmable Decoder .................................... .
Programmable Decoder .................................... .
Programmable Decoder .................................... .
PLL Parallel Programmable Frequency Synthesizer ............. .
PLL 4-Bit Data Bus Programmable ........................... .
PLL 4-Bit Data Bus Programmable ........................... .
PLL Parallel Programmable ................................. .
PLL Parallel Programmable ................................. .
PLL Serial Programmable .................................. .
PLL Serial Programmable .................................. .
PLL Serial Programmable .................................. .
PLL Serial Programmable .................................. .
Dual PLL 4-Bit BCD Programmable .......................... .
Integrated Pulse Dialer With Redial .......................... .
Pulse/Tone Repertory Dialer ................................ .
Pulse/Toner Repertory Dialer ............................... .

Linear
Linear
Linear
Linear
Linear
MECL
MECL
MECL
MECL
MECL
2-201
2-209
2-224
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
SF
2-291
2-291

2400 bps Digital Modulator (DPSK) .......................... .
2400 bps Digital Demodulator (DPSK) ........................ .
8-600 bps Modulator/Demodulator (Bell 103) .................. .
Bit Rate Generator ........................................ .
0-600 bps Modulator/Demodulator (Bell 103/CCITT V.21) ....... .
Quad Line Driver .......................................... .
Quad Line Driver .......................................... .
RS-232IV.28 Driver/Receiver ............................... .
Bit Rate Generator ........................................ .
300 bps Modem Band-Pass Switch Capacitor Filter (Bell 103) .... .
300 bps Modem Band-Pass Switch Capacitor Filter (CCITT V .21) ..
0-600 bps Modulator/Demodulator (Bell 103/CCITT V.21) ....... .
0-1800 bps Modulator/Demodulator (Bell 202/CCITT V.23) ...... .

2-62
2-70
2-85
2-125
2-128
2-271
2-271
2-276
2-288
2-378
2-384
2-390
2-395

MODEMS
MC6172
MC6173
MC6860
MCl4411
MCl4412
MC143403
MC143404
MC145406
MC145411
MC145440
MC145441
MC145445
MC145450

1-5

•

•

Device
Number

Function

Page
Number

DATA COMMUNICATIONS
MC6850
MC68HC51
MC6852
MC68HC53
MC6854
MC68153
MC68452
MC68652
MC68661
MC68681
MC68901

Asynchronous Communications Interface Adapter ............. .
Asynchronous Communications Interface Adapter ............. .
Synchronous Serial Data Adapter ........................... .
Asynchronous Communications Interface Adapter ............. .
Advanced Data-Link Controller .............................. .
Bus Interrupter Module .................................... .
Bus Arbitration Module .................................... .
Multi-Protocol Communications Controller .................... .
Enhanced Programmable Communications Interface ........... .
Dual Asynchronous ReceiverlTransmitter (DUART) ............ .
Multi-Function Peripheral .................................. .

MPU
MPU
MPU
MPU
MPU

*

LOCAL AREA NETWORK
MC68590

LAN Controller for Ethernet ................................. .

RF MODEMS
MC1374
MC1376
MC1496
MC3356
MC3393
MC3396
MC12002
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
MC12018
MC12019
MC12022
MC12023
MC12071
MC12073
MC12074
MC12090
MC145106
MC145145

TV Modulator Circuit ...................................... .
FM Modulator Circuit ...................................... .
Balanced Modulator-Demodulator ........................... .
Wideband FSK Receiver ................................... .
Two-Modulus Prescaler .................................... .
Divide By 28 Prescaler ..................................... .
Analog Mixer ............................................. .
Two-Modulus Prescaler (-+- 5/ -+- 6) ........................... .
Two-Modulus Prescaler (-+- 8/ -+- 9) ........................... .
Two-Modulus Prescaler (-+- 10/ -+- 11) ......................... .
Low-Power Two-Modulus Prescaler (-+- 321 -;- 33) ............... .
Low-Power Two-Modulus Prescaler (-+- 481 -+- 41) ............... .
Low-Power Two-Modulus Prescaler (-+- 641 -+- 65) ............... .
520 MHz Low-Power Prescaler (-+- 1281 -+- 129) ................. .
Low-Power Two-Modulus Prescaler (-+- 281 -+- 21) ............... .
1.0 GHz Low-Power Two-Modulus Prescaler (-+- 128/ -+- 129) ..... .
Low-Power Prescaler (-+- 64) ................................ .
High-Speed Prescaler (-+- 641 -+- 256) .......................... .
Low-Power Prescaler (-+- 64) ................................ .
Low-Power Prescaler (-+- 256) ............................... .
High-Speed Prescaler (-+- 2) ................................. .
PLL Parallel Programmable Frequency Synthesizer ............. .
PLL 4-Bit Data Bus Programmable ........................... .

1-6

Linear
Linear
Linear
Linear
Linear
Linear
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
MECL
SF
SF

Device
Number
MC145146
MC145151
MC145152
MC145155
MC145156
MC145157
MC145158

Function
PLL 4-Bit Data Bus Programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Parallel Programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Parallel Programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Serial Programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Serial Programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Serial Programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Serial Programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page
Number
SF
SF
SF
SF
SF
SF
SF

MICROPROCESSOR PRODUCTS

MC6800
MC6809
MC6801
MC6804
MC68HC04
MC6805
MC146805
MC68HC05
MC68000

8-Bit Microprocessor Unit .................................. .
8-Bit Microprocessing Unit ................................. .
8-Bit Microcomputer Unit .................................. .
8-Bit Microcomputer Unit .................................. .
8-Bit HCMOS Microcomputer Unit .......................... .
8-Bit HMOS Microcomputer Series .......................... .
8-Bit CMOS Microprocessor Series .......................... .
8-Bit HCMOS Microcomputer Series ......................... .
16-Bit Microprocessor ..................................... .

MPU
MPU
MCU
MCU
MCU
MCU
MCU
MCU
*

VOLTAGE SUPRESSORS

1N6274
MDA220

MO-sorb Zener Overvoltage Supressors . . . . . . . . . . . . . . . . . . . . . . .
Bridge Rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RZD
RZD

POWER DRIVERS

MFODll00 Pin Photo Diode for Fiber Optic Systems. . . . . . . . . . . . . . . . . . . . . . .
MFOE1200
High-power AIGaAs LED Fiber Optic Emitter. . . . . . . . . . . . . . . . . . .
MPSA42/43 NPN 300V TO-92 Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Opto
Opto
SS

OPTICAL CIRCUITS

MOC3030
4N25

Triac Driver Coupler ....................................... .
OPTO Coupler ...................................... .

* Contact your Motorola representative for the most up-to-date information.

1-7

Opto
Opto

•

•

1-8

Data Sheets •

2-1

•

2-2

@

MC3416

MOTOROLA

Specifications and Applications
Information

4

4 x 4 x 2 CROSSPOINT SWITCH
The MC3416 consists of a pair of 4 x 4 matrices of dielectrically
isolated SCA's, triggered by a common selection matrix. The device is
intended for switching analog signals in communication systems. The
use of dielectric isolation processing provides excellent crosstalk
isolation while maintaining minimal insertion loss.
The selection array consists of PNP transistors with the input
thresholds compatible with either McMOS or MTTL logic families.
The MC3416 is a monolithic pin·for·pin replacement for the
discontinued MCBH7601 hybrid device.

= 6.0 Ohms

(Typ) @ IAK

=20 mA

•

Low Series Resistance - ron

•

High Series Resistance - roff = 100 MO (Min)

•

Pin Compatible with MCBH7601 or RC4444

•

High Breakdown Voltage - 30 V (Typ)

•

Selection Matrix Compatible with TTL or CMOS Logic Levels

•

Dielectric Isolation Insures Low Crosstalk and Low Insertion Loss

X

4

X

2 CROSSPOINT
SWITCH

DIELECTRICALLY ISOLATED
MONOLITHIC
INTEGRATED CIRCUIT

L SUFFIX
CERAMIC PACKAGE
CASE 623

~~
PSUFFIX
PLASTIC PACKAGE
CASE 649

FIGURE 1 - REPRESENTATIVE CELL SCHEMATIC
(Repeated 16 Times'

Row Select

Anode A1

Anode A2

IB1,Cl,Dl

(B2,C2,D2

are Equivalent)

PIN CONNECTIONS

are Equivalent)

W

".'.'Ca~~de
,. """"""" ~

SCR2

SeR1

(X1, Y1,Z1 are Equivalent)

Anode

Cathode W2
01
02
Column Select A

(X2,Y2,Z2 are Equivalent)

(B,C,D are Equivalent)

FIGURE 2 - MATRIX CONFIGURATION AND NOMENCLATURE
(X Indicates a Possible Connection)
A

1 2

W

1

2

8 Columns C

1 2

1 2

D
1 2

I

ASSOCiated Pairs
Triggered
Simultaneously

AI
Cathode
V,
RowS.lect
Z
Cnhode

Z,

A'
Anoda

Column

Anode

SelectC
Column
Select 0
Cathode

el

ZI
Row Select
y

BI
B,

Anode

e,

Anod.
01
Catt\ode

WI
Row Select
W

Cathode

1
0'

2

Rows
1
2

Z

Anode
Anode

VI

y

X
C.ttu:u:J.
W'

SelactA
Column
Sillect B

Cathode

X

x,

Cathode
Row Sel8e::1

1

2

2-3

XI

MC3416
MAXIMUM RATINGS (Unle .. otherwise noted TA = 25°C)
Symbol

Value

Unit

Anode-Cathode Current - Continuous
(only one SeA at a time)

IAK

150

mA

Enable Current

lEn
TA
T stg

10

rnA

o to +70

°c
°c
°c

Rating

Operating Ambient Temperature Range

•

Storage Temperature Range
Junction Temperature Range

TJ

-65 to +150
1500 C

ELECTRICAL CHARACTERISTICS (Unless otherwise noted. TA = 0 to 70 0 C)
Symbol

Min

Max

Unit

BVAK

25

-

Vdc

BVKA

25

Vdc

BVBK

25

Vdc

BVKB

25

-

Vdc

Base-Emitter Breakdown Voltage
IIBE = 25jlA)

BVBE

25

-

Vdc

Emitter-Cathode Breakdown Voltage

BVEK

25

-

Vdc

OFF State Resistance
(VAK = 10V)

roff

100

-

Mn

Dynamic ON Resistance
(Center Current = 10 mAl (See Figure 8)
(Center Current = 20 mAl

ron
4.0
2.0

12
10

Holding Current

IH

0.7

3.0

mA

lEn

4.0

-

mA

-

1.0

1.1

Characteristic
Anode Cathode Breakdown Voltage

IIAK = 25jlA)
Cathode-Anode Breakdown Voltage

(IKA=25jlA)
Base-Cathode Breakdown Voltage

(lBK = 25jlA)
Cathode-Base Breakdown Voltage

(lKB = 25jlA)

(IEK = 25jlAI

n

(See Figure 101
Enable Current

(VBE = 1.5 V) (See Figure 7)
Anode-Cathode ON Voltage
OAK = 10 rnA)
OAK = 20 rnA)

VAK

Gate Sharing Current Ratio @ Cathodes

GSh

0.8

1.25

rnA/rnA

V,nh

-

0.3

V

linh

-

0.1

mA

OFF State Capacitance
(V AK = 0 V) ( See F,gure 6)

Coff

-

2.0

pF

Turn-ON Time

ton

-

1.0

jlS

dv/dt

800

-

V/jls

V

(Under Select Conditions with Anodes Open) (See Figure 3)
Inhibit Voltage
(VB = 3.0 VI (See Figure 9)
Inhibit Current

(VB = 3.0 V) (See Figure 91

(See Figure 41
Minimum Voltage Ramp (Which Could Fire the SeR Under
Transient Conditions)

FIGURE 3 - TEST CIRCUIT

r

I;'

11

2-4

MC3416

FIGURE 4 - TEST CIRCUIT FOR dv/dt AND ton

Clock

O-t----~A;_;+=====~l
Q
Q

"MC7473

•

K

Q

K

I-+-t-

~
o o.S

,-

'"

I-

§
g
z

--:;;
O. 8

'"

~

'"

4

I--

TA=6 oc
~

t

f.---

-

.....-

~OC

-

J-

-

k- 1--1'"""
I-- r--

:- 0.1

o
o

~1L.O-....L.--1L.0--:2"-0--:3"-0- . . J4""0--:"5""0- . . J60----:'70:----:'80:-""'S""0

2.0

TA. AMBIENTTEMPERATURE {OCI

4.0

6.0

8.0

10

12

14

16

18

20

IAK. ANODE·CATHODE CURRENT {mAl

FIGURE 12 - DIFFERENCE IN ANODE-CATHODE ON
VOLTAGE (Between Associate Pairs of SCR's)
versus ANODE·CATHODE CURRENT

FIGURE 13 - OFF-5TATE CAPACITANCE versus ANODE·
CATHODE VOLTAGE
1.0

~ O.S
~

z

~ ±60r--r-~r-~r-~-~-~-~--+---+--~
w

~

o

>

±40r---r-~r-~r-~~~--~---+---+---+---4

0.8

t!

O. 7

~

06

w

0.5

~

0.4

o

0.3

.......

r--

J 0.2
O. 1

±2:EmEffm

o

2.0

4.0

6.0

8.0

10

12

14

16

18

o
0.1

20

FIGURE 14 - DYNAMIC ON RESISTANCE versus ANODE·
CATHODE CURRENT

1.0

2.0

10

\.
"\.

12

~

~

0.5

0;

""

10

z
~ 8.0

~

8

I--.

5.0

10

50

20

100

FIGURE 15 - DYNAMIC ON RESISTANCE versus
AMBIENT TEMPERATURE

14
(i)

0.2

VAK. ANODE·CATHODE VOLTAGE (VOLTS)

IAK. ANOOE·CATHODE CURRENT {mAl

-~

8.0

w

-

J--

J- IAK =10 mA

u

r-...

iZ

:l'
!;;

- -

...........

;;;
;; 4.0

IAK - 20 mA

~

r-

~ 6.0

6.0

~ 4.0

;:::

o>~ 20

>o

~ 2. 0
0
2.0

4.0

6.0

B.O

10

12

14

16

18

20

·10

IAK. ANOOE·CATHODE CURRENT {mAl

10

20

30

40

50

60

TA. AMBIENT TEMPERATURE {OCI

2-6

70

80

SO

MC3416
FIGURE 17 - CROSSTALK

FIGURE 18 - FEEOTHROUGH •• rlUl SIGNAL FREQUENCY

·70

r----. -

·70 -

-

~ ·80

~ -90

V

~

... ·110
·120
0.1

,/'

·80

,-,

o

'" ·100
1=

·130

V' ..us SIGNAL FREQUENCY

·60 ,..---r-,.-,-,...,,-rn---,.--,.-rrT'T"rTT--'-'r"'r''T'T''M''n

·60

,/".

f--I--l----+-+-f-t+++

~I--'

/"

---1--

(See Figure 18)

(SlIe Figure 19)

• 110 I----+-+++++++l--V-+-~-b-r'i-+j-H+-----=+---,.:.-+-H+l-+l
·120

.... 1--'
0.5

1.0

S.O

10

50

• 130 L,-_L-L-L-1-.L.lll.l-_.L-..LJ...,L,.LLJlJ.L_..L-L.L.l-Llili
0.1
O.S
1.0
S.O
10
SO
100

100

SIGNAL FREQUENCY IkHzl

SIGNAL FREQUENCY 1kHz!

FIGURE 1a - TEST CIRCUIT FOR FEEOTHROUGH vorlul FREQUENCY

600

€I)

1k
Wave
Ana1izer

,..-

-,

T A"" 25°C, Vi '" , 2 dBm, Crosspoints Off
Feedthrough = 20 LaglO (volvj)

FIGURE 19 - TEST CIRCUIT FOR CROSSTALK vorsus FREQUENCY

600

U
Wave
Anallzer

T A :: 26°C,

VI ""

12 dSrT'l, Crosspolnts On

Crosstalk = 20 LaglO (v o 2!v o l)

2-7

•

II
3C

o

~
~

CJ)
Anode Anode

Anode Anode
A2
91

Anode
A1

92

Anode
02

Anode Anode

C1

C2

01

"i5c:

:Jl

m

~
1
:Jl

m

"'0

:Jl

m
II>
m
Z
-i

N
CD

•

•

I I

r,;]

•

I I

•

I I

I~

»

-i

<:

m

!Il
:r
m
s:
»
-i
(;
0

~

G'l

:Jl

»
s:

Column
Select
A

Column
Select
9

Column
Select

C

Column

Select

o

MC3416
TELEPHONE APPLICATION OF THE CROSSPOINT SWITCH

The MC3416 crosspoint switch is deSigned to provide
a low·loss analog switching element for telephony signals.
It can be addressed and controlled from standard binary
decoders and is CMOS compatible. With proper system
organization the MC3416 can significantly reduce the size
and cost of existing crosspoint matrices.

tained through the SCR to retain an ac signal path. This
requires that each subscriber·input to the array be capable
of sourcing dc current as well as its ac signal. With each
subscriber acting as a dc source, each trunk output then
acts as a current sink. The instrument·to·trunk connection
in Figure 21 shows this configuration. However, with each
subscriber acting as a dc source, some method of inter·
connecting them without a trunk must be provided. Such
a local or intercom termination is shown in Figure 22.
Here both subscribers source dc current and exchange ac
signals. The central current sink accepts current from both
subscribers while the high output impedance of the current
sink does not disturb the system.
These configurations are system compatible. The dc

SIGNAL PATH CONSIDERATIONS

The MC3416 is a balanced 4 x 4 2·wire crosspoint array.
It is ideal for balanced transmission systems, but may be
applied effectively in a number of single ended applications.
Multiple chips may be interconnected to form larger cross·
point arrays. The major design 00 nstraint in using SCR
crosspoints is that a forward dc current must be main·

FIGURE 21 - INSTRUMENT·TO·TRUNK CONNECTION
+15

Emitter Selects
MeMOS Outputs

"

Di.e~::~~!

E
Trunk

1k

All MeMOS
Operated From
+15V Power
SupplV

500

--4--~-"-15 Volts

MeMOS Ouptuts Base Selects

FIGURE 22 - TYPICAL INSTRUMENT TO INSTRUMENT CONNECTION
-------.-----------------------------------------------------------~._------.. +15V
Emitter Selects are Active High MeMOS Outputs

500

500

Em..
1k

1 k

BaH Select_ Ar. Active
Low MeMOS OUtpUtl

Ollconnect
Enabll

All MeMOS LogiC
oparatld From +1SV

Powe, Suppl V

500
_ _...._

.....~_~....... -15V

2·9

•

MC3416

•

current restriction is not a restriction in the design of
an efficient crosspoint array. Because of the current sink
terminations, a signal path may use differing numbers of
crosspoints in any connection or in two sides of the same
connection further relaxing restrictions in array design.
Figure 23 demonstrates circuit operation. SI, S2, and
S3 are open. The Crosspoint SCR's are off as they have no
gate drive or dc current path through S1. By closing S2 and
S3, gate drive is provided, but the SCR's still remain off as
there is no dc current path to hold them on. Close SI and
the circuit is enabled, but with S2 and S3 off there is still
no signal path. Closing S2 and S3 with SI closed - current
is injected into both gates and they switch on. DC current
through R L splits around the center·tapped winding and
flows through each SCR, back through the lower winding
and through Sl to ground. If S2 and S3 are opened, that
current path still remains and the SCRs remain on. If an ac
signal is injected at either Gl or G2, it will be transmitted
to the other signal port with negligible loss in the SCR's. To
disconnect the ac signal path the SCR's must be com·
mutated off. By opening SI the de current path is inter-

rupted and the SCR 's switch off. The ac signal path is disconnected. With SI closed the circuit is enabled and may
be addressed again from S2 and S3. This circuit demonstrates a balanced transmission configuration. The transmission characteristics of the SCR's simulate a relay contact in that the ac signal does not incur a contact voltage
drop across the crosspoint. The memory characteristics of
the crosspoint are demonstrated'by the selective application
of SI, S2, and S3.
The selection of R l is governed by the power supply
voltage and the desired de current. If 10 mA is to flow
through each SCR then R l must pass 20 mA. Thus,
(VCC - VAK)/R l = 20 mAo The selection of Rp is governed
by the characteristics for crosspoint turn on. Adequate
enable current must be injected into the column select
and Rp should drop at least 1.5 Volts. The PNP transistor
has a typical gain of one. Thus, Rp should pass at least
2 mA to provide 4 mA column select current.

FIGURE 23- CROSSPOINT OPERATION
DEMONSTRATION CIRCUIT

G2

LJ

Vee

SI
S2
S3
ON
OFF
X
ON
OFF X
ON
ON
ON
ON
X
X
OFF X
X

LINE CONDITION
Enabled, Not Connected
Enabled, Not Connected
Addressed and Connected
G 1 Connected to G2
Disconnected.

X ::: irrelevant

Rp

ADDRESSING CONSIDERATIONS

The MC3416 crosspoint switch is addressed by selecting
and turning on the PNP transistor that controls the SCR
pair desired. The drive requirements of the MC3416 can be
met with standard MeMOS outputs. A particu lar crosspoi nt
is addressed by putting a logical "I" on the emitter and a
logical "0" on the base of the appropriate transistor. A
resistor in the base circuit of the transistor is required to
limit the current and must also drop 1.5 Volts to assure
forward bias of the two diodes in the collector circuits.

2-10

The gate current required for SCR turn on is 1 mA typically.
The MeMOS one-of·n decoders listed in Table I provide
both active high and active low outputs and are well su ited
for standard addressing organizations. The major design
constraint in organizing the addressing structure is that
any signal path which is to be addressed must create a de
path from a source to a sink. If that path requires two
crosspoints they must be addressed simultaneously. Of
course, once the path is selected, the addressing hardware
is free to initiate other signal paths. To meet the de path

MC3416

APPLICATIONS INFORMATION (continued)
requirement, crosspoint arrays should be designed in blocks
such that any given dc path requires only one crosspoint
per block, A signal path, however, may still use two cross·
points in the same block by sequentially addressing two
dc paths to the same terminator. For example, the left or
right pairs of crosspoints in Figure 22 must be addressed
simultaneously but the left pair may be addressed in
sequence after addressing the right pair. This is not a
difficult constraint to meet and it does not require unneces·
sary addressing hardware.
TABLE I

I

Dual Binary to 1 of 4
4·blt latch/4 to 16
BCD to Decimal Oecode

Active High Outputs
MC14555
MC14514
MC14028

Active Low Outputs
MC14556
MC14515

DISCONNECT TECHNIQUES
Since the crosspoint switch maintains signal paths by
keeping dc currents through active SCR's, disconnects are
easily accomplished by interrupting the dc current path.
This can be done anywhere in the circuit, but if the dis·
connect is done at the terminator then all signal paths
established to that terminator are broken simultaneously.
In both Figures 21 and 22 this is done by turning off the
current sink circuit with a McMOS buffer gate. MC14049
or MCl4050 buffers will drive the transistor switch. Once
a disconnect is completed, the terminator may be re·enabled
and used for another call. Usage of the terminators may be
easily monitored with optoelectronic couplers in the
collectors of the current sinks without disturbing trans·
mission characteristics.

See Application Note AN~760 for additional applications suggestions.

THERMAL INFORMATION
The maximum power consumption an integrated Circuit
can tolerate at a given operating ambient temperature can
be found from the equation:
TJ(max) -TA
PD(TA) = ROJA(Typ)

the sum of the products of the supply voltages and supply
currents at the worst case operating condition.
TJ(max)

Maximum Operating Junction Temperature
as listed in the Maximum Ratings Section
T A = Maximum Desired Operating Ambient
Temperature
ROJA(Typ) = Typical Thermal Resistance Junction to
Ambient

Where: PD(T A) = Power Dissipation allowable at a given
operating ambient temperature. This must be greater than

2-11

=

®

•

MC3417, MC3517
MC3418, MC3518

MOTOROLA

Specifications and Applications
Inforrn.ation

CONTINUOUSLY VARIABLE
SLOPE DELTA
MODULATOR/DEMODULATOR
LASER·TRIMMED
INTEGRATED CIRCUIT

CONTINUOUSL Y VAR IABLE SLOPE
DELTA MODULATOR/DEMODULATOR
Providing a simplified approach to digital speech encodingl
decoding, the MC3517/18 series of CVSDs is designed for military
secure communication and commercial telephone applications.
A single IC provides both encoding and decoding functions.
•

Encode and Decode Functions on the Same Chip with
a Digital Input for Selection

•

Utilization of Compatible 12L - Linear Bipolar Technology

•

CMOS Compatible Digital Output

•

Digital Input Threshold Selectable (VCC/2 reference
provided on chip)

LSUFFIX
CERAMIC PACKAGE

CASE 620

•

MC3417/MC3517 has a 3-Bit Algorithm (General
Communications)

•

MC3418/MC3518 has a 4-Bit Algorithm (Commercial Telephone)
PIN CONNECTIONS

Analog
Input

CVSD BLOCK DIAGRAM

(-)

16

Vee

(+)

15

Encode/
Decode

14

Clock

13

Digital Data
Input (-)

12

Digital
Threshold

11

COincidence
Output

10

Vee/2
Output

9

Digital
Output

Analog
Feedback

Syllabic

Encode'

~

Clock

Filter

Gatn
Analog Input

1

Control

Anal09 Feedback ~2q::=!~-t~~:.:;~"",,:;-;o;-::Digital
Data Input 13

4

Ref
Input (+J

12t:':-'=---iJHl-~w

Filter
11

Input ( -)

6

COincidence

~

Analog

Output

Output
5y 11 ahrf

VEE

S'

Gain Control

'GC

Analog
Output

Ref
Input

F dter
Input

{tl

(-I

ORDERING INFORMATION
Device

MC3417L
MC3418L
MC3517L
MC3518L

2-12

Package

Ceramic
Ceramic
Ceramic
Ceramic

DIP
DIP
DIP
DIP

Temperature
Range
OOC to +70 0 C
OOC to +70 0 C
-55°C to + 125°C
-55°C to + 125°C

MC3417, MC3517, MC3418, MC3518
MAXIMUM RATINGS
(All voltages referenced to VEE TA

= 2SoC unless otherwise noted)

Rating

Symbol

Value

Power Supply Voltage

VCC

-0.4 to +18

Vdc

Differential Analog Input Voltage

VID

±5.0

Vdc

VTH

-0.4 to VCC

Vdc

VLogic

-0.4 to +18

Vdc

Digital Threshold Voltage
Logic Input Voltage
(Clock, Digital Data, Encode/Decode)

Unit

Coincidence Output Voltage

VOICon

-0.4 to +18

Vdc

Syllabic Filter Input Voltage

VI(SYI)

-0.4 to VCC

Vdc

Gain Control Input Voltage

VI(GC)

-0.4 to VCC

Vdc

Reference Input Voltage

VI(Ref)

VCC/2 -1.0 to VCC

Vdc

IRef

-25

mA

VCC/2 Output Current

•

ELECTRICAL CHARACTERISTICS
(VCC

= 12 V, VEE =Gnd, TA =DoC to +70 0 C for MC3417/18, TA =-55°C to +125 0 C for MC3517/18 unless otherwise noted.)
MC3418/MC3518

MC3417/MC3517

Characteristic
Power Supply Voltage Range (Figure 1)
Power Supply Current (Figure 1)

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

VCCR

4.75

12

16.5

4.75

12

16.5

Vdc
mA

ICC

(Idle Channel)
(VCC = 5.0 V)
(VCC = 15 V)
Clock Rate
Gain Control CUrrent Range (Figure 2)
Analog Comparator Input Range

16 k

-

-

3.0

0.001

1.3

-

VCC -1.3

1.3

-

VCC -1.3

SR

-

IGCR

0.001

VI

Vo

3.7
6.0

5.0
10

3.7
6.0

5.0
10

32 k

3.0

mA

1.3

-

VCC -1.3

Vdc

1.3

-

VCC -1.3

Vdc

Samples/s

(Pins 1 and 2)
(4.75 V <; VCC <; 16.5 V)
Analog Output Range (Pin 7)

(4.75 V <; VCC <; 16.5 V, 10

= ± 5.0 mAl

Input Bias Currents (Figure 3)
(Comparator in Active Region)

-

Analog Input (11)
Analog Feedback (12)
Syllabic Filter Input (13)
Reference Input (15)
Input Offset Current
(Comparator in Active Region)
Analog Input! Analog Feedback

I'A

liB
0.5
0.5
0.06
-0.06

1.5
1.5
0.5
-0.5

-

-

-

0.25
0.25
0.06
-0.06

1.0
1.0
0.3
-0.3
I'A

110

-

0.15

0.6

-

0.05

0.4

-

0.02

0.2

-

0.01

0.1

-

2.0

6.0

-

2.0

6.0

0.1
1.0

0.3
10

-

0.1
1.0

0.3
10

-

-

1.0
0.8

2.5
2.5

-

1.0
0.8

2.5
2.5

-

1.0
0.8

3.0
2.0

-

1.0
0.8

3.0
2.0

-

0.12

0.25

-

0.12

0.25

Vdc

0.01

0.5

0.01

0.5

IlA

111-121- Figure 3
Integrator Amplifier

115-161 - Figure 4
Input Offset Voltage
V!I Converter (Pms 3 and 4) - Figure 5
Transconductance
VII Converter, 0 to 3.0 rnA
Integrator Amplifier, a to ± 5.0 mA Load
Propagation Delay Times (Note 1)
Clock Trigger to Digital Output

(CL

=25 pF to Gnd)

Clock Trigger to Coincidence Output

(CL = 25 pF to Gnd)
IRL ~ 4 kn to VCC)
Comcidence Output Voltage Low Logic State

(lOLICon)

gm

mV
mA/mV

I'S
tPLH
tPHL
tPLH
tpHL
VOLICon)

-

=3.0 mAl

Coincidence Output Leakage Current
High Logic State

(VOH

VIO

10H(Con)

= 15.0 V,OoC <; TA <; 70°C)

NOTE 1. All propagation delay times measured 50% to 50% from the negative gOing (from Vee to +0.4 VI edge of the clock.

2-13

MC3417, MC3517, MC3418, MC3518
ELECTRICAL'CHARACTERISTICS (continued)
MC341 j IMC3511
Charc:acteristfc

Applied DIgital Threshold Voltage Range

MC3418IMC3518

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

VTH

+1.2

-

Vce - 2.0.

+1.2

-

VCC - 2.0

Vdc

-

-

-

-

-10

5.0
-50

-10

5.0
-50

-

±5.0

-

-

mA

+10

IPin 12)
Digital Threshold Input Current

•

I'A

Illth)

11.2 V '" Vth '" Vee - 2.0 VI
IVIL applied to Pins 13, 14 and 151
(VIH'applied to Pins 13, 14 and 151

10

±5.0

VCC/2 Generator Maximum Output Current
(SQurce only)

IRef

+10

-

VCC/2 Generator Output Impedance

ZRef,

-

3.0

6.0

-

3.0

6.0

n

Er

-

-

±3.5

-

-

±3.5

%

Gnd
Vth + 0.4

-

Vth - OA
18.0

Gnd
Vth + OA

-

Vth- OA
18.0

Maximum Integrator AmpllfierQutput Current

rnA

(0 to +10 mAl
V CC/2 Generator Tolerance
(4.75 V '" Vee'" 16.5 V)

Logic Input Voltage (Pins 13, 14 and 15)

Low Logic State

Vdc
VIL
VIH

High Logic State

Dynamic Total Loop Offset Voltage
~Voffset
INote 2) - Figures 3, 4 and 5
IGe = 12.0 I'A, Vee = 12 V
TA = 25 0 C
MC3417/18
oDe", TA '" +70 0 e
-55 0 e '" TA '" +125 0 e MC3517/18
IGe = 33.0 itA, Vee = 12 V
TA = 25 0 e
MC3417118
oDe", TA '" +70 0 e
-55 0 e", T A'" +125 0 e MC35H/18
IGe = 12.0 itA, Vee = 5.0 V
TA = 25 0 e
MC3417/18
oDe", TA '" +70 0 e
-55 0 e", TA '" +125 0 e MC3517/18
IGe = 33.0 itA, Vee = 5.0 V
TA=25 0 e
MC3417/18
oDe", TA '" +70 0 e
-55 0 e", TA '" +125 0 e MC3517/18

-

mV

-

-

-

-

-

-

-

-

-

-

-

± 2.5
± 3.0
±4.5

± 5.0

-

-

± 7.5

-

-

-

±10

-

± 0.5
± 0.75
± 1.5

± 1.5
± 2.3
± 4.0

-

-

-

-

-

± 1.3

± 2.0
± 2.8

-

-

-

± 2.5

±

-

± 4.0

-

-

±

± 6.0
,8.0
± 10

-

-

-

-

-

-

-

0.4

-

-

-

4.5
± 5.5

± 1.0

5.0

Digital Output Voltage

Vdc

(lOL = 3.6 rnA)
(lOH = -0.35 rnA)

VOL
VOH

Syllabic Filter Applied Voltage (Pin 3)

VI(Syll

-

0.1
Vee -1.0 Vee -0.2

-

0.1
Vee - 1.0 Vee - 0.2

OA

-

+3.2

-

Vee

+3.2

-

Vee

Vdc

8.0

12
1.55
3.25

8.0

lA5

2.75

10
1.50
3.0

2.75

10
1.50
3.0

12
1.55
3.25

itA
rnA
rnA

-

± 100

± 250

-

± 100

± 250

mV

IFigure 21
Integrating Current (Figure 2)

IIlnt l

(lGe = 12.0 itA I
(lGe = 1.5 mAl
(lGe = 3.0 mAl

lA5

Dynamic Integrating Current Match

VO(Avel

(lGe = 1.5 rnA) Figure 6
I nput Current - High Logic State

itA

IIH

(VIH = 18 VI

-

Digital Data Input
Clock Input
Encode/Decode Input
Input Current - Low Logic State

-

-

-

+5.0
+5.0
+5.0

-

-

-

-

+5.0
+5.0
+5.0
itA

IlL

(VIL = 0 VI
Digital Data Input
Clock Input
Encode/Decode Input

Clock Input, VIL

~

OA V

-

-

-

--

-

-10
-360
-36
-72

-

-

-

-

-10
-360
-36

-72

NOTE 2. Dynamic total loop offset (:EVoffset) equals Via (comparator) (Figure 3) mmus VIOX (Figure 51. The Input offset voltages of the
analog comparator and of the integrator amplifier include the effects of input offset current through the mput resistors. The slope
polarity switch current mismatch appears as an average voltage across the 10 k Integrator resistor. For the MC3417/MC3517, the
clock frequency is 16.0 kHz. For the MC3418/MC3518, the clock frequency is 32.0 kHz. Idle channel performance is guaranteed if
this dynamic total loop offset is less than one-half of the change in Integrator output voltage during one clock cycle (ramp step size).
Laser trimming is used to insure good idle channel performance.

2-14

MC3417, MC3517, MC3418, MC3518
DEFINITIONS AND FUNCTION OF PINS
Pin 1 - Analog Input
This is the analog comparator inverting input where
the voice signal is applied. It may be ac or de coupled
depending on the application. If the voice signal is to be
level shifted to the internal reference voltage, then a bias
resistor between pins 1 and lOis used. The resistor
is used to establish the reference as the new dc average of
the ac coupled signal. The analog comparator was designed
for low hysteresis (typically less than 0.1 mV) and high
gain (typically 70 dB).

(lint) flows into pin 6 when the analog input (pin 1) is
high with respect to the analog feedback (pin 2) in the
encode mode or when the digital data input (pin 13) is
high in the decode mode. For the opposite states, lint
flows out of Pin 6. Single integration systems require a
capacitor and resistor between pins 6 and 7. Multipole
configurations will have different circuitry. The resistance
between pins 6 and 7 should always be between 8 kQ and
13 kQ to maintain good idle channel characteristics.
Pin 7 - Analog Output
This is the integrator op amp output. It is capable of
driving a 600·ohm load referenced to VCCI2 to +6 dBm
and can otherwise be treated as an op amp output. Pins 5,
6, and 7 provide full access to the integrator op amp
for designing integration filter networks. The slew rate
of the internally compensated integrator op amp is
typically 0.5 V/lls. Pin 7 output is current limited for
both polarities of current flow at typically 30 mAo

Pin 2 - Analog Feedback
This is the non·inverting input to the analog signal
comparator within the IC. In an encoder application it
should be connected to the analog output of the encoder
circuit. This may be pin 7 or a low pass filter output
connected to pin 7. In a decode circuit pin 2 is not used
and may be tied to VCC/2 on pin 10, ground or left open.
The analog input comparator ~as bias currents of
1.5 IlA max, thus the driving impedances of pins 1 and 2
should be equal to avoid disturbing the idle channel
characteristics of the encoder.

Pin B - VEE
The circuit IS designed to work In either single or dual
power supply applications. Pin 8 is always connected to
the most negative supply.

Pin 3 - Syllabic Filter
This is the point at which the syllabic filter voltage is
returned to the IC in order to control the integrator step
size. It is an NPN input to an op amp. The syllabic filter
consists of an RC network between pins 11 and 3. Typical
time constant values of 6 ms to 50 ms are used in voice
codecs.

Pin 9 - Digital Output
The digital output provides the results of the delta
modulator's conversion. It swings between VCC and
VEE and is CMOS or TTL compatible. Pin 9 is inverting
with respect to 'Pin 1 and non-inverting with respect
to pin 2. It is clocked on the fall ing edge of pin 14.
The typical 10% to 90% rise and fall times are 250 ns and
50 ns respectively for VCC = 12 V and CL = 25 pF
to ground.

Pin 4 - Gain Control Input
The syllabic filter voltage appears across Cs of the
syllabic filter and is the voltage between VCC and pin 3.
The active voltage to current (V -I) converter drives
pin 4 to the same voltage at a slew rate of typically
0.5 V Ills. Thus the currerit injected into pin 4 (IGC)
is the syllabic filter voltage divided by the Rx resistance.
Figure 6 shows the relationship between IGC (x·axis) and
the integrating current, lint (y·axis). The discrepancy,
which is most significant at very low currents, is due to
circuitry within the slope polarity switch which enables
trimming to a low total loop offset. The Rx resistor is
then varied to adjust the loop gain of the codec, but
should be no larger than 5.0 kQ to maintain stability.

Pin 10 - VCC/2 Output
An internal low impedance mid-supply reference is
provided for use of the MC3417/18 in single supply
appl ications. The internal regulator is a current source
and must be loaded with a resistor to insure its sinking
capability. If a + 6 dBmo signal is expected across a
600 ohm input bias resistor, then pin 10 must sink
2.2 V1600 Q = 3.66 mAo This is only possible if pin 10
sources 3.66 mA Into a resistor normally and will source
only the difference under peak load. The reference load
resistor is chosen accordingly. A 0.1 I'F bypass capacitor
from pin 10 to VEE is also recommended. The VCC/2
reference is capable of sourcing 10 rn II, and can be used

Pin 5 - Reference Input
This pin is the non·inverting input of the integrator
amplifier. It is used to reference the dc level of the output
signal. In an encoder circuit it must reference the same
voltage as pin 1 and is tied to pin 10.

as a reference elsewhere in the systerr Ircuitry.

Pin 11 - Coincidence Output
The duty cycle of this pin IS proportional to the
voltage across CS. The coinCidence output will be low
whenever the content of the Interndl shift register is all
ls or aliOs. In the MC3417 the ,,,gister is 3 bits long

Pin 6 - Filter Input
This inverting op amp input is used to connect the
integrator external components. The integrating current

2-15

•

MC3417, MC3517, MC3418, MC3518
DEFINITIONS AND FUNCTIONS OF PINS (continued)

•

while the MC3418 contains a 4 bit register. Pin 11 is an
open collector of an NPN device and requires a pull·up
resistor. If the syllabic filter is to have equal charge and
discharge time constants, the value of Rp should be
much less than RS. In systems requiring different charge
and discharge constants, the charging constant is RSCS
while the decaying constant is (RS + Rp)CS. Thus longer
decays are easily achievable. The NPN device should not
be required to sink more than 3 mA in any configuration.
The typical 10% to 90% rise and fall times are 200 ns and
100 ns respectively for RL = 4 kfl to +12 V and CL =
25 pF to ground.

can be transmitted. The digital data input level should be
maintained for 0.5 J,ls before and after the clock trigger
for proper clocking.
Pin 14 - Clock Input
The clock input determines the data rate of the codec
circuit. A 32K bit rate requires a 32 kHz clock. The
switching threshold of the clock input is set by pin 12.
The shift register circuit toggles on the falling edge of the
ciock input. The minimum width for a positive-going
pulse on the ciock input is 300 ns, whereas for a negativegoing pulse, it is 900 ns.
Pin 15 - Encode/Decode
This pin controls the connection of the analog input
comparator and the digital input comparator to the
internal shift register. If high, the result of the analog
comparison will be clocked into the register on the
falling edge at pin 14. If low, the digital input state will be
entered. This allows use of the Ie as an encoder/decoder
or simplex codec without external parts. Furthermore, it
allows non-voice patterns to be forced onto the transmission line through pin 13 in an encoder.

Pin 12 - Digital Threshold
This input sets the switching threshold for pins 13,14,
and 15. It is intended to aid in interfacing different logic
families without external parts. Often it is connected to
the VCCI2 reference for CMOS interface or can be biased
two diode drops above VEE for TTL interface.
Pin 13 - Digital Data Input
In a decode application, the digital data stream is
applied to pin 13. In an encoder it may be unused or may
be used to transmit signaling message under the con·
trol of pin 15. It is an inverting input with respect to
pin 9. When pins 9 and 13 are connected, a toggle
flip·flop is formed and a forced idle channel pattern

Pin 16 -Vce
The power supply range is from 4.75 to 16.5 volts
between pin Vee and VEE.

FIGURE 2 - IGCR, GAIN CONTROL RANGE and
lint - INTEGRATING CURRENT

FIGURE 1 - POWER SUPPLY CURRENT

Vce

-

Ice
1 k

16

u.

~1

Vee

u.

~lr·1jlF

10.1 ~F
16

1 k
15

2

14
4
5

CVSD

MC3517
MC3518

15
Clock

13

4

12
11

CVSD
MC3517
MC3518

14

·Clock

13

Digital
Data Input

12
11
10

10
10.1 ~F
8

9

8

9~l-"~

Output

Note. Digital Output = Digital Data Input
·For static testing, the clock is only necessary for
preconditiOning to obtarn proper state for a given input.

2-16

MC3417, MC3517, MC3418, MC3518
FIGURE 12 - CVSD WAVEFORMS

FIGURE 13 - BLOCK DIAGRAM OF THE CVSD DECODER

Clock

Digital
In

Audio
Out

Integrator

Slope
Pol.rity

Switch

2-17

MC3417, MC3517, MC3418, MC3518
FIGURE 14 - 16 kHz SIMPLEX VOICE CODEC
(Using MC3417, Single Pole Companding and Single Integration)
Digital Input

+50

Push
to Talk

Digital Output
(Norm.

Key

16K Bitt

open)

•

Encode/iStiCcid8
Clock

Out
9

15
7

Anal
~g~+
Inpu

4 "F

A-

1

A+

2

"

VTH12

I
10
0.1 JlF

l

Ana log
OutP ut

I~

Sh 1ft Register

I

VCC12
Ref

1.0
k

Input

7
Analog

Out

COin

LogIc

5
Ref

-=-

ISVCC

,----.
[> ;.

D13

10
k

lock

14

Camp

sao

600

16 kHz

++5.0

Digital

10 k

Out

I

~"."~,.",,

11

I
SylRS
In 3

I

I
6 Filter

18 k Cs

0.33 "F
2.4 Meg

GC<4

Switch

0.1/J. F

3.3 k Rp

13k

Rx

-b

fVEE

Ref

Vs

10 k

CIRCUIT DESCRIPTION
sign of the difference between the input voltage and
the integrator output. That sign bit is the digital output
and also controls the direction of ramp in the integrator.
The comparator is normally clocked so as to produce
a synchronous and band limited digital bit stream.
If the clocked serial bit stream is transmitted,
received, and delivered to a similar integrator at a remote
point, the remote integrator output is a copy of the
transmitting control loop integrator output. To the
extent that the integrator at the transmitting locations
tracks the input signal, the remote receiver reproduces
the input signal. Low pass filtering at the receiver output
will eliminate most of the quantizing noise, if the clock
rate of the bit stream is an octave or more above the
bandwidth of the input signal. Voice bandwidth is 4 kHz
and clock rates from 8 k and up are possible. Thus the
delta modulator digitizes and transmits the analog input
to a remote receiver. The serial, unframed nature of the
data is ideal for communications networks. With no
input at the transmitter. a continuous one zero alternation
is transmitted. If the two integrators are made leaky, then
during any loss of contact the receiver output decays to

The continuously variable slope delta modulator
(CVSD) is a simple alternative to more complex conven·
tional conversion techniques in systems requiring digital
communication of analog signals. The human voice is
analog, but digital transmission of any signal over great
distance is attractive. Signal/noise ratios do not vary with
distance in digital transmISSion and multiplexing,
switching and repeating hardware is more economical and
easier to design. However, instrumentation A to 0 con·
verters do not meet the communications requirements.
The CVSD A to 0 is well suited to the requirements of
digital communications and is an economically efficient
means of digitizing analog inputs for transmission.

The Delta Modulator
The innermost control loop of a CVSD converter is
a simple delta modulator. A block diagram CVSD Encoder
is shown in Figure 11. A delta modulator consists of a
comparator in the forward path and an integrator in
the feedback path of a simple control loop. The inputs
to the comparator are the input analog signal and the
integrator output. The comparator output reflects the

2-18

MC3417, MC3517, MC3418, MC3518
CIRCUIT DESCRIPTION (continued)
zero and receive restart begins without framing when the
receiver reacquires. Similarly a delta modulator is tolerant
of sporadic bit errors. Figure 12 shows the delta modulator waveforms while Figure 13 shows the corresponding
CVSD decoder block diagram.

if it contains all 1 s or as. This condition is called coinci·
dence. When it occurs, it indicates that the gain of the
integrator is too small. The coincidence output charges
a single pole low pass filter. The voltage output of this
syllabic filter controls the integrator gain through a pulse
amplitude modulator whose other irput is the sign bit
or up/down control.
The simplicity of the all ones, all zeros algorithm
should not be taken lightly. Many other control algorithms using the shift register have been tfled. The key to
the accepted algorithm is that It provides a measure of
the average power or level of the Input signal. Other

The Companding Algorithm

The fundamental advantages of the delta modulator
are its simplicity and the serial format of its output.
Its limitations are its ability to accurately convert the
input within a limited digital bit rate. The analog input
must be band limited and amplitude limited. The frequency limitations are governed by the nyquist rate while
the amplitude capabilities are set by the gain of the
integrator.
The frequency limits are bounded on the upper end;
that is, for any input bandwidth there exists a clock
frequency larger than that bandwidth which will transmit the signal with a specific noise· level. However, the
amplitude limits are bounded on both upper and lower
ends. For a signal level, one specific gain will achieve an
optimum noise level. Unfortunately, the basic delta
modulator has a small dynamic range over which the
noise level is constant.
The continuously variable slope circuitry provides
increased dynamic range by adjusting the gain of the
integrator. For a given clock frequency and input
bandwidth the additional circuitry increases the delta
modulator's dynamic range. External to the basic
delta modulator is an algorithm which monitors the
past few outputs of the delta modulator in a simple
shift register. The register is 3 or 4 bits long depending on
the appl ication. The accepted CVSD algorithm simply
monitors the contents of the shift register and indicates

techniques

provide

more

instantdneous

Information

about the shape of the input curve. The purpose of
the algorithm is to control the gain of the integrator
and to increase the dynamic range. Thus a measure of
the average input level is what is needed.
The algorithm is repeated in the receiver and thus
the level data is recovered in the receiver. Because the
algorithm only operates on the past serial data, it changes
the nature of the bit stream without changing the channel
bit rate.
The effect of the algorithm is to compand the input
signal. If a CVSD encoder IS played into a basic delta
modulator, the output of the delta modulator will reflect
the shape of the input signal but all of the output will
be at an equal level. Thus the algorithm at the output is
needed to restore the level variations. The bit stream
in the channel is as If it were from a standard delta modu·
lator with a constant level input.
The delta modulator encoder with the CVSD algorithm
provides an efficient method for digitIZing a vOice Input
in a manner which is especially convenient for digital
communciations requirements.

APPLICATIONS INFORMATION
CVSD DESIGN CONSIDERATIONS

2.
3.
4.
5.
6.
7.

A simple CVSD encoder using the MC3417 or MC3418
is shown in Figure 14. These ICs are general purpose
CVSD building blocks which allow the system designer
to tailor the encoder's transmission characteristics to the
application. Thus, the achievable transmission capabilities
are constrained by the fundamental lim itations of delta
modulation and the design of encoder parameters. The
performance is not dictated by the internal configuration
of the MC3417 and MC3418. There are seven design
considerations involved in designing these basic CVSD
building blocks into a specific codec application.

ReqUired number of shift register bits
Selection of loop gain
Selection of minimum step size
Design of integration filter transfer function
Design of syllabic filter transfer function
Design of low pass filter at the receiver

The circuit in Figure 14 is the most basic CVSD circuit
possible. For many applications in secure radio or other
intelligible voice channel requirements, It is entirely
sufficient. In this circuit, items 5 and 6 are reduced to
their simplest form. The syllabic and integration filters
are both single pole networks. The selection oi items
1 through 4 govern the codec performance.

These are listed below:
1. Selection of clock rate

2-19

•

II
3!:

o

CVSD CIRCUIT SCHEMATIC

20 k

20 k

...t

:"
3!:
ow

12 k

+

9
.. I
0 Dlglta
Output

...

U'I

~~

3!:

Analog 1

ow

Input

...
!»

Analog
Feedback

~

13

Digital
Data Input

alf-----'

Output

01-1----,

3!:

ow

...

e

U'I
N
I
N

12
DIgital
Threshold

Q)

o

4 Gain
Control

.------------00
14
Clock

o---.-----------l

Filter

Encode/ 15
Decode

oo--------------~-~~----~

Analog
Output

6
Vee/2

Ref

Output

Input

Filter
Input

aPVEE

MC3417, MC3517, MC3418, MC3518
CVSD DESIGN CONSIDERATIONS (continued)
Selection of Loop Gain
The gain of the circuit in Figure 14 is set by resistor
Rx. Rx must be selected to provide the proper integrator
step size for high level signals such that the companding
ratio does not exceed about 25%. The companding ratio
is' the active low duty cycle of the coincidence output on
pin 11 of the codec circuit. Thus the system gain is
dependent on:
1. The maximum level and frequency of the input
signal.
2. The transfer function of the integration filter.

Layout Considerations
Care should be exercised to isolate all digital signal
paths (pins 9, 11, 13, and 14) from analog signal paths
(pins 1- 7 and 10) in order to achieve proper idle channel
performance.
Clock Rate
With minor modifications the circuit in Figure 14
may be operated anywhere from 9.6 kHz to 64 kHz
clock rates. Obviously the higher the clock rate the higher
the SIN performance. The circuit in Figure 14 typically
produces the SIN performance shown in Figure 15.
The selection of clock rate is usually dictated by the
bandwidth of the transmission medium. Voice band·
width systems will require no higher than 9600 Hz.
Some radio systems will allow 12 kHz. Private 4·wire
telephone systems are often operated at 16 kHz and
commercial telephone performance can be achieved
at 32K bits and above. Other codecs may use bit rates
up to 200K bits/sec.

For voice codecs the typical input signal is taken to be
a sine wave at 1 kHz of 0 dBmo level. In practice, the
useful dynamic range extends about 6 dB above the design
level. In any system the companding ratio should not
exceed 30%.
To calculate the required step size current, we must
describe the transfer characteristics of the integration
filter. In the basic circuit of Figure 14, a single pole of
160 Hz IS used.
R = 10 kn, C = 0.1 !1F

FIGURE 15 - SIGNAL·TO·NOISE PERFORMANCE
OF MC3417 WITH SINGLE INTEGRATION, SINGLE·POLE
ANO COMPANDING AT 16K BITS - TYPICAL

Va
Ii

= _____

=_K_

CIS + l/RC)

S + Wo

Wo = 211"f

15

/

/
10

I
II

I

-30

"

Clock Rate ~ 16 kHz
Tesl Tone =: 1 kHz Sine Wave
NOIse Welgl'ltJllg C Message

f = 159.2 Hz
Note that the integration filter produces a single-pole
response from 300 to 3 kHz. The current required to
move the integrator output a specific voltage from zero
is simply:
Va CdVo
li=R+d"t

~

I

50

-40

--

10 3 = Wo = 211"f

-20

-10

Now a 0 dBmo sine wave has a peak value of 1.0954
volts. In 118 of a cycle of a sine wave centered around
the zero crossing, the sine wave changes by approximately
its peak val ue. The eVSD step should trace that change.
The required current for a 0 dBm 1 kHz sine wave is:

10

INPUT LEVEL (dBI RELATIVE TO SLOPE OVERLOAD

Shift Register Length (Algorithm)
The MC3417 has a three-bit algorithm and the MC3418
has a four-bit algorithm. For clock rates of 16 kHz and
below, the 3·bit algorithm is well suited. For 32 kHz
and higher clock rates, the 4-bit system is preferred.
Since the algorithm records a fixed past history of the
input signal, a longer shift register is required to obtain
the same internal hsitory. At 16 bits and below, the
4-bit algorithm will produce a sl ightly wider dynam ic
range at the expense of level change response. Basically
the MC3417 is designed for low bit rate systems and the
MC3418 is intended for high performance, high bit rate
system. At bit rates above 64K bits either part will
work well.

1'=
I

1.1V
+0.1!1F(1·1)=0.935mA
*2(10kn)
0.125ms

*The maximum voltage across R I when maximum
slew is required is:
1.1 V
2
Now the voltage range of the syllabic filter is the
power supply voltage, thus.
Rx = 0.25i'v'ed 0.935 mA
A similar procedure can be followed to establish the
proper gain for any input level and integration filter type.

2-21

MC3417, MC3517, MC3418, MC3518
CVSD DESIGN CONSIDERATIONS (continued)

•

Minimum Step Size
The final parameter to be selected for the simple codec
in Figure 14 is idle channel step size. With no input signal,
the digital output becomes a one-zero alternating pattern
and the analog output becomes a small triangle wave.
Mismatches of internal currents and offsets limit the
minimum step size which will produce a perfect idle
channel pattern. The MC3417 is tested to ensure that
a 20 mVp·p minimum step size at 16 kHz will attain a
proper idle channel. The idle channel step size must be
twice the specified total loop offset if a one· zero idle
pattern is desired. In some applications a much smaller
minimum step size (e.g., 0.1 mVi can produce quiet
performance without providing a 1-0 pattern.
To set the idle channel step size, the value of Rmin
must be selected. With no input signal, the slope control
algorithm is inactive. A long series of ones or zeros never
occurs. Thus, the voltage across the syllabic filter capaci·
tor (CSi would decay to zero. However, the voltage
divider of RS and Rmin (see Figure 14) sets the minimum
allowed voltage across the syllabic filter capacitor. That
voltage must produce the desired ramps at the analog
output. Again we write the filter input current equation:
Va

For values of Va near VCC/2 the VoIR term is negligible; thus

where .:IT is the clock period and .:lVo is the desired
peak·to·peak value of the idle output~ For a 16K-bit
system using the circuit in Figure 14
1·~O.I/1F 20mV ~33 A
I
62.5/1s
/1

The voltage on Cs which produces a 33 /1A current is
determined by the value of Rx.
liRx

~

Vsmin; for 33/1A, Vsmin

~

41.6 mV

In Figure 14 RS is 18 kQ. That selection is discussed
with the syllabic filter considerations. The voltage divider
of RS and Rmin must produce an output of 41.6 mV.
VCC

RS
~ VSmin
RS+ Rmin

Rmin'" 2.4 MQ

Having established these four parameters - clock rate,
number of shift register bits, loop gain and minimum
step size - the encoder circuit in Figure 14 will function
at near optimum performance for input levels around
OdBm.

dV o

li~R+Cdt

INCREASING CVSD PERFORMANCE
Integration Filter Design
The circuit in Figure 14 uses a single·pole integration
network formed with a 0.1 /1F capacitor and a 10 kQ
resistor. It is possible to improve the performance of the
circuit in Figure 14 by 1 or 2 dB by using a two·pole
integration network. The improved circuit is shown.
The first pole is still placed below 300 Hz to provide
the 1 IS voice content curve and a second pole is placed
somewhere above the 1 kHz trequency. For telephony
circuits, the second pole can be p,aCI,,' "bc.va 1.8 kHz
to exceed the 1633 touchtone frequency In other com·
munlcation systerns, values as ,low a!'l i kHz may be
selected. In general, the lower In frequency the second
pole IS placed, the greater the noise Improvement. Then,
to ensure the encoder loop stabil ity, a zero is added to
keep the phase shift less than 1800 . This zero should
be placed sl ightly above the low·pass output filter break
frequency so as not to reduce the effectiveness of the
second pole. A network of 235 Hz, 2 kHz and 5.2 kHz
is typical for telephone applications while 160 Hz.
1.2 kHz and 2.8 kHz might be used in voice only channels.
(Voice only channels can use an output low·pass filter
which breaks at aboul 2.5 kHz.i The two·pole network
in Figure 16 has a transfer function of:

FIGURE 16 - IMPROVED FILTER CONFIGURATION

112

Analog Output

o-.....-"v'V\~....--'-l-'C
600

C2
0.151'F

1:
R1600

Cl
0.1 "F

13 k

These component values are for the telephone channel circu it
poles deSCribed in the text. The R2, C2 product can be provided
With different valves of Rand C. R2 should be chosen to be equal

to the termination resistor on pm 1.

2-22

MC3417, MC3517, MC3418, MC3518
INCREASING CVSD PERFORMANCE (continued)
Thus the two poles and the zero can be selected arbitrarily
as long as the zero is at a higher frequency than the first
pole. The values in Figure 16 represent one implementation of the telephony filter requirement.
The selection of the two-pole filter network effects
the selection of the loop gain value and the minimum step
size resistor. The required integrator current for a given
change in voltage now becomes:

is optimum. Then record the syllabic filter voltage and
the current. Repeat this for all desired signal levels.
Then derive the resistor diode network which produces
that curve on a curve tracer.
Once the network is designed with the curve tracer,
it is then inserted in place of Rx in the circuit and the
forced optimum noise performance will be achieved
from the active syllabic algorithm.
Diode breakpoint networks may be very simple or
moderately complex and can improve the usable dynamic
range of any codec. In the past they have been used in
high performance telephone codecs.
Typical resistor-diode networks are shown in Figure 17.

R1Cl
Ii = -Va + (R2C2
-- +- + Cl~!!.Vo
-- +
RO
RO
RO
!!.T

~

R1C1R2C2)!!.V02
--.
R2C2C l +
RO
!!.T2

The calculation of desired gain resistor Rx then proceeds
exactly as previously described.
Syllabic Filter Design
The syllabic filter in Figure 14 is a simple single-pole
network of 18 kn and 0.33 J.l.F. This produces a 6.0 ms
time constant for the averaging of the coincidence output
signal. The voltage across the capacitor determines the
integrator current which in turn establishes the step size.
The integrator current and the resulting step size determine the companding ratio and the SIN performance.
The companding ratio is defined as the voltage across
CSNCC·
The SIN performance may be improved by modifying
the voltage to current transformation produced by Rx.
If different portions of the total Rx are shunted by diodes,
the integrator current can be other than (VCC - VS)/R x .
These breakpoint curves must be designed experimentally
for the particular system application. In general, one
would wish that the current would double with Input
level. To design the desired curve, supply current to pin 4
of the codec from an external source. Input a signal
level and adjust the current until the SIN performance

FIGURE 17 - RESISTOR-DIODE NETWORKS

01
R1

02 03
R2

~
01

If the performance of more complex diode networks
is desired, the cirCUit in Figure 18 should be used. It
simulates the companding characteristics of nonlinear
Rx elements in a different manner.
Output Low Pass Filter
A low pass filter is reqUired at the receiving circuit
output to eliminate quantizing noise. In general, the lower
the bit rate, the better the filter must be. The filter in
Figure 20 provides excellent performance for 12 kHz
to 40 kHz systems.

TELEPHONE CARRIER QUALITY CODEC USING MC3418
Two specifications aT the integrated Circuit are specifically intended to meet the performance requirements
of commercial telephone systems. First, slope polarity
switch current matching is laser trimmed to guarantee
proper idle channel performance with 5 mV minimum
step size and a typical 1% current match from 15 J.l.A
to 3 mAo Thus a 300 to 1 range of step size variation IS
possible. Second, the MC3418 provides the four·bit
algorithm currently used in subscriber loop telephone
systems. With these specifications and the circuit of Figure 18, a telephone quality codec can be mass produced.

The circuit in Figure 18 provides a 30 dB SINc ratio
over 50 dB of dynamic range for a 1 kHz test tone at
a 37.7K bit rate. At 37.7K bits, 40 voice channels may
be multiplexed on a standard 1.544 megabit Tl facility.
This codec has also been tested for 10-7 error rates with
asynchronous and synchronous data up to 2400 baud
and for reliable performance with DTMF signaling. Thus,
the deSign is applicable in telephone quality subscriber
loop carrier systems, subscriber loop concentrators and
small PABX installations.

2-23
-------.--

•

MC3417, MC3517, MC3418, MC3518
TELEPHONE CARRIER QUALITY CODEC USING MC3418 (continuedl

•

The Active Companding Network
The unique feature of the codec in Figure 18 is the
step size control circuit which uses a companding ratio
reference, the present step size, and the present syllabic
filter output to establish the optimum companding
ratios and step sizes for any given input level. The companding ratio of a CVSD codec is defined as the duty
cycle of the coincidence output_ It is the parameter
measured by the syllabic filter and is the voltage across
Cs divided by the voltage swing of the coincidence output_
In Figure 18, the voltage swing of pin 11 is 6 volts_ The
operating companding ratio is analoged by the voltage
between pins 10 and 4 by means of the virtual short
across pins 3 and 4 of the V to I op amp within the integrated circuit. Thus, the instantaneous companding
ratio of the codec is always available at the negative
input of A 1.
The diode Dl and the gain of Aland A2 provide
a companding ratio reference for any input level. If
the output of A2 is more than 0.7 volts below VCC/2,
then the positive input of Al is (VCC/2 - 0.71. The on
diode drop at the input of A 1 represents a 12% companding ratio (12% = 0.7 V/6 VI.
The present step size of the operating codec is directly

related to the voltage across Rx , which established the
integrator current. In Figure 18, the voltage across Rx is
amplified by the differential amplifier A2 whose output
is single ended with respect to pin 10 of the IC.
For large signal inputs, the step size is large and the
output of A2 is lower than 0.7 volts. Thus D1 is fully on_
The present step size is not a factor in the step size
control. However, the difference between 12% comppanding ratio and the instantaneous companding ratio at
pin 4 is amplified by A 1. The output of A 1 changes the
voltage across Rx in a direction which reduces the difference between the companding reference and the
operating ratio by changing the step size. The ratio of
R4 and R3 determines how closely the voltage at pin 4
will be forced to 12%. The selection of R3 and R4 is
initially experimental. However, the resulting companding
control is dependent on Rx , R3, R4, and the full diode
drop D1. These values are easy to reproduce from codec
to codec.
For small input levels, the companding ratio reference
becomes the output of A2 rather than the diode drop.
The operating companding ratio on pin 4 is then compared
to a companding ratio smaller than 12% which is determined by the voltage drop across Rx and the gain of A2

FIGURE 18 - TELEPHONE QUALITY DELTAMOD CODER
(Both double integration and active companding control are used to obtain improved CVSD performance.
Laser trimming of the integrated circuit provides reliable idle channel and step size range characteristics.)

Clock
Input

Voice/Non-VoIce
SELECT

37.7 kHz

Digital
Output
37.7 Bits

(Vce /2 )

+12 V
Analog
Input

15

16

14

0.22 f.lF

Vee

o----1~rl_--::t__l

1N914

Non-Voice 3.6 k
I nput
'---<~I-=h-1
L..-_.--J
(Digital
Input)

Analog

Output

R2

200 k

3.6 k

C2
O.025IJF

Al, A2,

'-..JINIr:::
R--' 13 k

'M'C'i4sii'
0.1 I'F

2-24

0.1 I'F

MC3417, MC3517, MC3418, MC3518
FIGURE 3 - INPUT BIAS CURRENTS, ANALOG
COMPARATOR OFFSET VOLTAGE AND CURRENT

FIGURE 4 - INTEGRATOR AMPLIFIER OFFSET
VOL TAGE AND CURRENT

Vee

v IO{comparator)

~lk

VCC

16

16

2

15
14
CVSD
MC3517
MC3518

Clock

15
14

3
0,1 jJF

13
12

4
5

CVSD
MC3517 13
MC3518
12

11

11

10

+

9

Amplifier
Offset
Voltage)

10

( Integrator
8

9

lo.,

"F

Note: The analog comparator offset voltage is tested
under dynamic conditions and therefore must
be measured with appropriate filtering.

FIGURE 5 - VII CONVERTER OFFSET VOLTAGE,
VloandVIOX

FIGURE 6 - DYNAMIC INTEGRATING CURRENT MATCH

*32 kHz MC3418/MC3518
16 kHz MC3417/MC3517

VCC
16
15
16
14

15

2
60mV

+

1\-

4
14

3

5k
4

CVSD

13

MC3517
MC3518

12

Clock"

10

Amplifier

8

plus Slope
PolaritY
Switch
Mismatch)

9

MC3517
MC3S18

12

C~l)ck

10

005 JJ.F
"-

8

VOIAVI
(Note 1)

"-

:::COO:

Offset
Voltage

13

11

11

VIOX

( Integrator

CVSD

9r--t--~

~O

*32 kHz MC3418/MC3518
16 kHz MC3417(MC3517

-

Notes: 1. Vo(AV), Dynamic Integrating Current Match,
IS the average voltage of the triangular waveform observed at the measurement points,
across 10 k,o resistor with IGC = '.5 mAo
2. See Note 2 of the Electrical Characteristics,
page 3.

Note: V'OX is the average voltage of the triangular

waveform observed at the measurement points.

2-25

MC3417, MC3517, MC3418, MC3518
TYPICAL PERFORMANCE CURVES
FIGURE 8 - NORMALIZED DYNAMIC
INTEGRATING CURRENT MATCH varsus VCC

FIGURE 7 - TYPICAL lint vorsus IGC (Mean ± 201
~

z

0:
I

•

4:

i
~!i
I

+B 0

70
50

0
0

30

.3

i!

100

A
0

20

P'

10

0

7.0
5.0

0

3.0

TA" 25 Q C

~V

1.0

2.0

1.0

0

Vee= 12 v

~

2.0

0

II
3.0

5.0 7.0

20

10

30

50

70

6.0

FIGURE 9 - NORMALIZED DYNAMIC INTEGRATING
CURRENT MATCH vorsus CLOCK FREQUENCY

E

+1. 0

i 5
"z ...."
>'"
o
to-

~ ~
::l'"
: B
o z
"''''
z i=
-'-"
~ ~

...... 1'-

0

I"-

""[\ '\

-2 5

-50

B.O

0

--

-~~

-75

-

0

10

11

~

30

40

50

70

100

13

14

15

"'"
"-

\

I"1\

J.

VCC'12V
TA'= 25°C
of---- (See Note 2 of Eletttlcal
Charactensltcs, page 3 )

1\

-100

12

'Ge= 12IJ.A

i

(See FigureS,

20

9.0

IGC'33"A

Normahllldto
IOkn@IGC·I.5mAl

10

-

\

'\

TA'" 25°C
VCC"2 V

::~

TA = 25°C
felK· 32 kHz
ISeeFigure6,
Normalized to 10 kn @IGc·1.5mA)

FIGURE 10 - DYNAMIC TOTAL LOOP
OFFSET .arsus CLOCK FREQUENCY

+50

+2 5 -

7.0

---

..--

VCC. SUPPLY VOLTAGE (VOLTS)

IGC. GAIN CONTROL CURRENT (pAl - PIN 4

;;

Vi-"""

,.,... .,......

-B0
5.0

100

V V

10

200

I 20I II30 I

\
50

70

100

tCLK. CLOCK FREQUENCY (kHz)

'CLK. CLOCK FREQUENCY (kHz)

FIGURE 11 - BLOCK DIAGRAM OF THE CVSD ENCODER
crock

Audio
In

2-26

200

MC3417, MC3517, MC3418, MC3518
TELEPHONE CARRIER QUALITY CODEC USING MC3418 (continued)
FIGURE 19 - SIGNAL-TO-NOISE PERFORMANCE
AND FREQUENCY RESPONSE

and A 1. The gain of A2 is also experimentally determined,
but once determined, the circuitry IS easily repeated.
With no input signal, the companding ratio at pin 4
goes to zero and the voltage across Rx goes to zero. The
voltage at the output of A2 becomes zero since there is
no drop across Rx. With no signal input, the actively
controlled step size vanished.
The minimum step size is established by the 500 k
resistor between Vee and Vee/2 and is therefore independently selectable.
The signal to nOise results of the active companding
network are shown in Figure 19. A smooth 2 dB drop is
realized from + 12 dBm to - 24 under the control of A 1.
At -24 dBm, A2 begins to degenerate the companding
reference and the resulting step size is reduced so as to
extend the dynamic range of the codec by 20 dBm.
The slope overload characteristic is also shown. The
active companding network produces improved performance with frequency. The 0 dBm slope overload pOint is
raised to 4.8 kHz because of the gain available In controlling the voltage across Rx. The curves demonstrate that
the level linearity has been maintained or improved:
The codec in Figure 18 IS designed specifically for
37_7K bit systems. However, the benefits of the active
companding network are not limlled to high bit rate
systems. By modifYing the crossover region (changing
the gain of A21. the active technique may be used to
improve the performance of lower bit rate systems.
The performance ami repeatability of the codec in
Figure 18 represents a slgillficant step forward In the art
and cost of eVSD codec designs.

(Showing the improvement realized with
the circuit in Figure 18.)

a. SIGNAL-TO-NOISE PERFORMANCE OF TELEPHONY
QUALITY DELTAMODULATOR
35

m
"0

30

1---"jr-:====::;;(us:=====1--1
50dB

o

4 BIT ALGORITHM

Z

37.7K BITS
1 kHz TEST TONE
C MESSAGE WEIGHT

~
__

____________________________

~

~

5

2

~

..J

~

~
~

"iii
20
-36

-48

-24

-12

12

INPUT LEVEL IN dBmO

b. FREQUENCY RESPONSE ve"us INPUT LEVEL
(SLOPE OVERLOAD CHARACTERISTIC)

o dBm
E

"
"0

INPUT

0
-

-10·

~

10 dBm INPUT

-20dBm INPUT

--' -20

w

>
w

-30

--'

I- -40
::J

"-

4 81T ALGORITHM
37.7 K BITS

I- -50
::J

0

• A larger value for e2 is required in the decoder circuit
than in the encoder to adjust the level linearity with
frequency. In Figure 18, 0.050 I1F would work well.

-60

o

2kHz

4kHz

6kHz

8kHz

10kHz

INPUT FREQUENCY IN Hz

FIGURE 20 - HIGH PERFORMANCE ELLIPTIC FILTER FOR CVSD OUTPUT
C1

Rl

R2

87.6 k

175 k

C3

C4

157 pF 78 pF

1J:7k

Designed for 0.28 dB ripple In the pass band

wn

~

3 kHz

Ws

=

~6kHz

AdS at Ws and above 29.5 dB

2-27

•

MC3417, MC3517, MC3418, MC3518
FIGURE 21 - FULL DUPLEX/32K BIT CVSD VOICE CODEC USING MC3517/18 AND MC3503/6 OP AMP

Digital OutPUt
Force Idle
Channel

9

+5 V

C2
16

II

C1
Analog Input

<>-l

;;:

R2
11

a:

CS1

MC3417

R1

MC3418

3

.

~~as
A3

I

: I A2 Mirrorl

_____________ JI

VEE

0

I

i+

VRX
1::

Hook
Status

--- -- --------,

~

Receiye Input

RRX

"
CRX

I C~ntr~1
[
Circuit

Bias

iii
a::

~

r

C

Analog Ground

VAG

VaB

2-30

CTX

TXO
RTX2
RH

"

+

Transmit
Output

v

RVTX

VTX

MC3419-1 L, MC3419A-1 L, MC3419C-1 L

MAXIMUM RATINGS (Voltages Referenced to VCC.I
Rating
Voltage
Powerdown Input Voltage Range
Sense Current

Symbol

Value

Unit

VEE
VOB

-60
VEE -1.0 V

Vdc

Vpj)j

+15to -15

PIN CONNECTIONS

Vdc
mAde

ITSI,IRSI
100
200

Steady State
Pulse - Figure 4
Storage Temperature Range

Tstg

-65 to + 150

TJ

150

Operating Junction Temperature
(8JA ~ 100'CIW Typ)

'c
'c

VCC
EP

Symbol

Value

Unit

TSI

Operating Ambient
Temperature Range

TA

a to

Loop Current

IL

10 to 120

rnA

RSI

Voltage

VEE
VOB

-20to -56
-20 to VEE

Vdc

BN

Analog Ground
(lL ~ a to 60 rnA)
(lL ~ a to 120 rnA)

VAG

Hook Status Output

EN
VEE

-2.0 to -20

Vdc

VHSO

+15 to -20

Vdc

RL

a to 2500

n

TRANSMISSION CHARACTERISTICS (RL

~

600

Characteristic
Transmit and Receive Gain Variation

n unless otherwise noted.)
Figure

Symbol

1

VTXNL,
VLNRX

(Insertion Loss)
(1.0 kHz @ 0 dBm Inputl
MC3419-1
MC3419A-1
MC3419C-1

Min

Transhybrid Rejection
(Input - 1 kHz @ a dBm)
Fixed (1%) Resistor Balance Network
MC3419-1, MC3419C-1
MC3419A-1
Trimmed Balance Network All Types

1

Level Linearity (-48 to +3.0 dBm, referenced to
o dBm @ 1 kHz)

1

a
a
a

+0.3
+0.15
+0.4

-35
-40
-55

-

-

dB

VTXNL
VLNRX

a dBm

-0.1
-0.1

0

a

+0.1
+0.1

1

1

Unit

dB

-

Reception

Max

VTXNRX

-23
-33

Tr~nsmission

Typ

dB

-0.3
-0.15
-0.4

Frequency Response (200-3400 Hz referenced to
1.0 kHz @ 0 dBm)
Transmission
Reception

POI

CC

Vdc

a to

VRSO,VTSO

Loop Resistance

Total Distortion @ 1.0 kHz,
(C-Message Filtered)

'c

+ 70

-12
-2.5 to -12

Supervisory Output Voltage
Compliance Range

RXI

BP

OPERATING CONDITIONS (Voltages Referenced to VCC.)
Rating

VAG

dB
VTXNL
VLNRX

-0.1
-0.1

a
a

VLNRX
VTXNL

-

-60
-60

2-31

+0.1
+0.1

-

dB

MC3419-1 L, MC3419A-1 L, MC3419C-1 L
TRANSMISSION CHARACTERISTICS (continued) (RL

•

~

600

n unless otherwise noted.)

Figure

Symbol

Idle Channel Noise (VRX = 0 V)
MC3419-1, MC3419A-l
MC3419C-l

1

VTX, VL

Return Loss (referenced to 600 ohms) @ 1.0 kHz,
OdBm
MC3419A-l
MC3419-1, MC3419C-l

1

longitudinal Induction (60 Hz)
(llON ~ 35 rnA RMS)

2

VTX

Longitudinal Balance
MC3419-1 (200-3000 Hz)
MC3419A-l (200-1000 Hz)
MC3419A-l (3000 Hz)
MC3419C-l (200-3000 Hz)

2

VTXNLON,
VLNLON

Characteristic

ELECTRICAL CHARACTERISTICS (VEl"
Characteristic
Propagation Delay

Typ

Max

Unit
dBrnC

-

RO +
- 600
20 Log I RO
600 1
36
30

-

3.0
4.0

-

10
13

-

5.0

-

-

-

-

dB
dB
dBrnC
dB

-45
-50
-48
-40

-

-

= -48 V VOB ~ VEE VAG ~ 0 V RL ~ 600 n TA ~ 25°C unless otherwise noted)

Figure

Symbol

1

Tp, VRX to VL
VRX to ITX

Supply Current - On-Hook
(VEE ~ VOB = 56 V, Rl > 100 Mn)
MC3419-1, MC3419A-l
MC3419C-l

3

On-Hook Power Dissipation
(Rl> 100 M!l)
MC3419-1, MC3419A-l
MC3419C-l

3

Power Supply Noise Rejection
(1,0 kHz @ 1,0 VRMS)
MC3419-1, MC3419A-l
MC3419C-l

3

Ouiet Battery Noise Rejection
(1.0 kHz @ 1.0 VRMS)

3

Sense Current
Tip
Ring

4

Fault Currents
Tip to VCC
Ring to VCC
Tip to Ring
Tip and Ring to VCC

1

Analog Ground Current

1

Min

-

Max

Unit

750
1,2

-

,....

-

40
100

200
500
rnW

Po

-

1.0
2.5

dB

VTXNee
-40
-30
VTXNqb

ns

pA.

-

-

-6.0

-

0.17
0.17

0.19
0,19

-

-

dB
rnA/rnA

ITSO/ITSI
IRSO/IRSI
ITip
IRing
ILoop
ITio and IRina
IVAG
IPOI
VIH
VIL
1

Typ

IVCC

Powerdown Logic Levels

Hook Status Output Current
(RL < 2.5 kn, VHSO = + 0.4 Vdc)
VHSO = - 0,4 Vdc)
(RL> 10 kn, VHSO = + 12 Vdc)
VHSO = -12 Vdc)

Min

0.15
0.15

-1.2

-

0
2.5
120
2.5

-

rnA

-

0.1

2.0

-1.0

-10

pA.

-4.0

Vdc
Vdc

-

-

-

pA.

IHSO
+1.0
-0.4

-

2-32

+3.0
-1,5
0
0

-'-

rnA
rnA

+50
-2.0

pA.
pA.

MC3419-1 L, MC3419A-1 L, MC3419C-1 L
FIGURE 1 -

AC TEST CIRCUIT
10

~IF

VRX
VCC

VAG

EP

RXI

BP

TXO

TSI

POI

18

MJE271

4

RL
600
2.0W Ring

17

9

•

VTX

16
15
90.09 k
14

CC

HSO

RSI

TSO

BN

RSO

EN

HST

VEE

VaB

4-

IHSO (+)

12V

IHSO(-)-

174 k

8

OV

13
12
11
10

232 k

43 k

-48V
(Tip & Ring) AC Termination Impedance, RO ~ 600
DC Feed Resistance, RF ~ 400

n

FIGURE 2 -

n

Transmit and Receive Gain ~ 0 dB
Al ~ MC1741N or Equivalent

LONGITUDINAL BALANCE TEST CIRCUIT

VCC

VAG

MJE271

368

TIp

4

EP

RXI

BP

TXO

TSI

PDI

18

OV

17
16
15
90.09 k

+
5

VL
174 k

368

::'~'"
rv

6
7
8

VLON

9

CC

HSO

RSI

TSO

BN

RSO

EN

HST

VEE

VaB

14
13
12
11
10
232 k

43 k

-48V
(Tip & Ring) AC Termination Impedance, RO ~ 600
DC Feed Resistance, RF ~ 400 n

n

2-33

Transmit and Receive Gain ~ 0 dB
Al ~ MC1741 N or Equivalent

MC3419-1 L, MC3419A-1 L, MC3419C-1 L
FIGURE 3 -

SUPPLY NOISE REJECTION TEST CIRCUIT

IVCC

IVAG

18

~--------+---~--

MJE271

•

TIp

4

RL
600
2.0W

5
174 k

Ring

6

8

EP

RXI

BP

TXO

TSI

PDI

CC

HSO

RSI

TSO

BN

RSO

EN

HST

VEE

VaB

17
16
15
90.09 k
14
13
12
11

9

43k

~-----

VEE

(Tip & Ring) AC Termination Impedance, RO = 600 fl
DC Feed Resistance, RF = 400 n

FIGURE 4 -

2

Transmit and Receive Gain = 0 dB
A1 = MC1741N or Equivalent

-

VAG

EP

RXI

BP

TXO

TSI

PDI

CC

HSO

RSI

TSO

BN

RSO

18
17

~

16

ITSI

-80 V

174 k
1200
20W
IRSI
-40 V

-

15
14
1 3 _ ITSO
-12 V

174 k

8

12

-12 V
- - IRSO

EN

HST

VEE

Vas

11
261 k

9

-48V

1-----51 V

TSO AND RSO SUPERVISORY OUTPUT TEST CIRCUIT

VCC

__---oOV

10

-48 V

2-34

MC3419-1 L, MC3419A-1 L, MC3419C-1 L

FIGURE 5 - QUIET BATTERY CURRENT IVQB
versus LOOP CURRENT IL

FIGURE 6 -

4. 0

LONGITUDINAL CAPACITY

;;{ 100
TYPical

~
>--

._.-

0

0

/"

~

0

./

V

IOB(mAI

V-

V

~

80

B
 10 kll. the HSO pin is inactive, i.e" VHSO = logic supply voltage.

15

PDf

Powerdown Input pin. This pin is used to deny service to the subscriber. A logic level "0" (VIL <
-4.0 V) powers down the MC3419-1 except for HSO, TSO and RSO. The voltage range of this
high impedance input pin is ± 15 V.

16

TXO

Transmit current Output. This output sinks current to VaB and is proportional to ITSI + IRSI by a
ratio of Kl where: K1 = 0.51. Its saturation voltage is VaB + 2.5 V typo (+3.5 V over the
temperature range). This pin is only active during the off-hook power-up condition.

17

RXI

Receive Input. This input sums ac currents from TXO and the receive voltage input (VRX) and
sources all the dc current to TXO. It has a low input impedance (15 ll) typically biased 4.5 V
below the VAG pin voltage during off-hook power-up conditions. During powerdown conditions.
the voltages on RXI and TXO can drift up to VAG.

18

VAG

Analog Ground Voltage reference input. The input impedance of this pin is much greater than 1.0 Mfi.
It should be ac coupled to system ground and could be direct coupled if system ground is
between 0 V and -12 V. AC coupling requires 300 kfi to Vce and 0.1 p.F to system ground. If
Vce and system ground are common, tie VAG directly to Vce. If dc loop currents are allowed to
go higher than 60 mA, VAG should be biased from -2.5 V to -12 V to avoid problems at high
ambient temperatures.

circuitry.

2-36

MC3419-1L, MC3419A-1L, MC3419C-1L
FUNCTIONAL DESCRIPTION
Referring to the functional block diagram on page 1,
line sensing resistors (RR and RT) at the TSI and RSI
pins convert voltages at the Tip and Ring terminals into
currents which are fed into current mirrors* A1 and A2.
An output of A1 is mirrored by A3 and summed together
with an output of A2 at the TXO terminal. Thus, a differential to single-ended conversion is performed from
the ac line signals to the TXO output.
All the dc current at the TXO output is fed back
through the RXI terminals to the 81 mirror input. The
inputs to 81 and 82 are made equal by mirroring the
81 input current to the 82 input through a unity gain
output of the 81 mirror. Both 81 and 82 mirrors have
high gain outputs (x95) which drive the subscriber lines
with balanced currents that are equal in amplitude and
1800 out of phase. The feedback from the TXO output,
through the B-Circuit mirrors, to the subscriber line
produces a dc feed resistance significantly less, but
proportional to the loop sensing resistors.
In most line-interface systems, the ac termination
impedance is desired to be greater than the dc feed
impedance. A differential ac generator on the subscriber
loop would be terminated by the dc feed impedance if
the total ac cu~rent at the TXO output were returned to
the B1 input along with the dc current. Instead, the
MC3419-1 system diverts part of the ac current from the
B-Circuit mirrors. This decreases the ac feedback current, causing the ac termination impedance at the line
interface to be greater than the dc feed impedance.
The ac current that is diverted from the 81 mirror
input is coupled to a current-to-voltage converter circuit
that has a low input impedance. This circuit consists of
an op amp (external to the MC3419-1) and a feedback
resistor which produces the transmit output voltage
(VTX) at the 4-wire interface. Transmission gain is programmed by the op amp feedback resistor (RVTX)'
Reception gain is realized by converting the ac coupled receive input voltage (VRX) to a current through
an external resistor (RRX) at the low impedance RXI
terminal. This current is summed at RXI with the dc and
ac feedback current from the A-Circuit mirrors and
drives the 81 mirror input. The 8-Circuit mirror outputs
drive the 2-wire port with balanced ac current proportional to the receive input voltage. Reception gain is
programmed by the RRX resistor.
Since receive input signals are transmitted through
the MC3419-1 to the 2-wire port, and the 2-wire port
signals are returned to the 4-wire transmit output, a
means of cancellation must be provided to maintain
4-wire signal separation (transhybrid rejection). Cancellation is complicated because the gain from the receive port to the transmit port depends on the impedance

of the subscriber loop. A passive "balance network" is
used to achieve transhybrid rejection by cancelling, at
the low impedance input to the transmit op amp, the
current reflected by the loop impedance to the 4-wire
transmit output. For a resistive loop impedance, a single
resistor provides the cancellation. For reactive loops,
the balance network should be reactive .
Longitudinal (common-mode) currents that may be
present on the subscriber lines are suppressed in the
MC3419-1 by two methods. The first is inherent in the
mirror configuration. Positive-going longitudinal currents into Tip and Ring create common-mode voltages
that cause a decreasing current through the Tip Sensing
resistor and an increasing current through the Ring
Sensing resistor. When these equal and opposite signal
currents are reflected through the A-Circuit mirrors and
summed together at TXO, the total current at TXO remains unchanged. Therefore, the ac currents due to the
common-mode signal are cancelled before reaching the
transmit output.
The second longitudinal suppression method is more
dominant, since it limits the amplitude of commonmode voltages that appear at the Tip and Ring terminals.
A common-mode suppression circuit detects common-mode inputs and drives the loop with balanced
currents to reduce the input amplitude. Subtracting currents from outputs of the A 1 and A2 mirrors produces
a signal current at the CC terminal in response to the
common-mode voltage at Tip and Ring. A transconductance amplifier (C-Circuit) generates a current proportional to the CC terminal voltage which is summed
with the current from the RXI terminal at the inputs of
current mirrors 81 and 82. The weighting and polarity
of the summing networks produce common-mode 81
and 82 mirror output currents at the 2-wire port. The
common-mode input impedance is inversely proportional to the gain of the longitudinal suppression circuit.
RC and Cc compensate the common-mode feedback
loop. At 60 Hz with typical component values, the 2-wire
common-mode impedance is less than 5 n.
The longitudinal suppression circuit output currents
are generated by modulating dc current fed to the loop
by the B1 and 82 current mirrors. This configuration
avoids the increased power dissipation attributed to
current mode loop drive because dc and longitudinal
currents are not cumulatively sourced to the loop.
However, driving common-mode currents through the
8-circuit current mirrors in this manner limits the longitudinal suppression capability. The suppression circuit
is unable to reverse 2-wire current polarities to maintain
a low-impedance termination when longitudinal currents exceed the dc loop current. At low dc loop currents, the common-mode signal capability, known as
longitudinal capacity, is limited by the loop current (Figure 6). At high-loop currents, longitudinal capacity is
limited by the maximum voltage swing of the CC terminal and is therefore independent of dc loop current.

*A current mirror is a circuit which behaves as a current controlled
current source. It has a single low-impedance input terminal with respect to a reference point and one or more high impedance outputs.

2-37

•

MC3419-1 L, MC3419A-1 L, MC3419C-1 L
FIGURE 7 -

BASIC SLiC CIRCUIT

r------1~_t--------------------._----------------------_t---------..Gnd

1 Vee

,--

EP

I
I

BP

MDA220
I

•

RXI

I
4
ITSI--

RT

...J

a:

>

RpR

TXO
TSI

PDI

ee

RR

Ring

VAG

_'RS'

I
I

I
I
IL __

6

RSI

HSO
TSO

I
I
I

7

I
I
I

8

_--l

BN

EN

RSO
HST

18
RRX

17

16
15
14
Hook
'------------·-------..~Status

13

Output
'--------------------_Tlp
Sense

12
11

'------------------------.-Rlng

Sense
VEE 9 10 VOB

RH

RC

'------------------______~--~~--~------------------------------__ -48V

The hook status control circuit supplies the bias currents to activate the B-Circuit op amps and other sections of the MC3419-1. To activate the bias currents, the
control circuit compares the current through the sense
resistors, RR and RT, and the load resistance RL with
the current through the hook status threshold programming resistor, RH, by using outputs from both A1 and
A2 mirrors. The A1 mirror output sources current to the
RH resistor. (This reduces all internal currents to near
zero during the on-hook state in order to eliminate unnecessary power consumption.) If this current is large
enough the voltage on the HST pin will trip an internal
comparator, then another circuit compares the current
from the A 1 output with that of an A2 output. These
currents must match within ± 15%. If so, HSO will be
activated and the bias circuits will turn on provided the
voltage on PDI is greater than -1.2 V. The HSO pin can
have either a pull-up resistor or a pull-down resistor
and when activated it will switch to VCC (0 volts).
Once the MC3419-1 is powered up, a circuit with a
gain of 20 feeds current to the RH resistor in order to
keep the bias circuitry active. (The sense resistors are
paralleled with the Darlington transistors which reduces

the sense input currents.) Should the sense input currents drop below one-twentieth of the required powerup current, the bias currents will be removed, forcing
a power-down condition.
Current mode analog signal processing is critically
dependent on voltage to current conversion at the
2-wire and 4-wire inputs. Precise, low-noise voltage
sensing through resistors RT, RR and RRX requires
quiet, low impedance terminations at terminals TSI, RSI
and RXI respectively. For 2-wire signals, terminal VaB
isolates the loop-sensing resistors and current mirrors
from noise at the high-current VEE terminal. EXternal
filtering from VCC to VaB ("quiet battery" terminal)
ensures loop voltages are sensed without interference
from system supply noise. VEE noise rejection at audio
frequencies is typically 60 dB or greater.
Receive input terminal RXI is referenced to the VAG
terminal which references the 4-wire input to the
"analog ground" ofthe 4-wire signal source, thus isolating the input from power ground voltage transients.
This isolation offers 70 dB of noise rejection at audio
frequencies.

SYSTEM EQUATIONS
K1 - The current gain from ITSI + IRSI to TXO only
during an off-hook power-up condition. K1 = 0.51 ±
1%.
'

For simplicity, the following equations do not use Kl
or K2. Instead the actual numerical value is used, for
instance (1 + [21K1K2) = 1 + 1.02 x 95 = 97.9 is approximately 98.

K2 - The current gain from RXI to the collectors of the
off-Chip Darlington transistors only during an off-hook
power-up condition. K2 = 95 ± 1%.

RL - Loop resistance. This is a load resistance from Tip
to Ring and can be either ac or de depending on context.

2-38

MC3419-1 L, MC3419A-1 L, MC3419C-1 L
LOOP CURRENT REGULATIONS
FIGURE 91a)

FIGURE Bla)

Gnd

Gnd

FIGURE Bib)
130
120
110
<" 100
E 90
>;z
80
~
=> 70
u
60
~
9 50
40
~
30
20

""

•

CaB

CaB

FIGURE 91bl

j 1~~

j jiffl~

Ib!1 [1 I~
\1,,1
l'!I

1

I

: ;1 ;1
, t (

I
j

III
t

I

j

[I

;;;'

E

>~

g§

:::>

u
"0

9
~

~ j I I,
I

130
110
110
100
90
BO
70
60
50
40
30
20
10

L

-~tI~HF~~f
t I "

F-.;

1

I

+

j

j

j

Standard 400 H
Feed ReSIStance

223 (lN53061
d~ i~
1.95 lN53051 1\.,i _ t I'
1.67 11N53031 ~
i'
1.39 11 N5301 I ~l
1.1211N529BI
0.84 (1 N52951
I,
,
i 0.5611N52911 " '

r:::-

!
I
,

I

i

~j, j

,

r

-

r-- j til jJill j JJiliHL_~~

--

oL

10 k

10

100
1.0 k
RL, LOOP RESISTANCE IHI

10 k

SYSTEM EQUATIONS (continued)
ignoring the effects of RL

Zl - loop impedance. This is used only to connote a
complex impedance loading on Tip and Ring.
Il -

loop current. The dc current flow through Rl'

RF

0
R - R _ 49RF (IVasl -4.0 VI
R- T IVaBI
- 6 0

(31

(41

The minimum value for RR and RT is 5.0 kO.
The first order value of RF can not be greater than the
desired value of the termination impedance (usually
600 0 or 900 0). To achieve dc feed resistances that are
greater, a resistor can be placed between VaB and VEE
along with a filter capacitor CaB which restores the
desired termination impedance and filters power supply
noise. A diode should also be placed between VaB and
VEE to prevent damage in case a catastrophic power
supply failure occurs.

(11

Because of the diode voltage drops on TSI and RSI, the
actual dc feed resistance is higher. The second order
equation is:
R _ IVaBI198 RL + RR + RT + 1200 il)
F98 (IIVOBI -4.0 VI
- RL

IVosl(RR + RT + 1200 HI
98 (IVoBI - 4.0 VI

So:

RF - Dc feed resistance. The synthesized resistance
from which battery (Vee and VEE) current is fed to Rl.
The battery feed resistance is balanced differential feed.
See Figure 7. (This assumes VaB = VEE.) The first order
equation is:
R _ RR + RT + 1200 il
F98

=

(2)

2-39

MC3419-1 L, MC3419A-1 L, MC3419C-1 L
IVQB - This is the current that is sourced from the VOB
pin and is proportional to the currents into and out of
RSI and TSI. When the SLiC is in the off-hook power-up
mode, IVOB is also proportional to IL.
IVOS = 2.15 IRSI
IVOS

•

+ 0.7 ITSI

(5)

= 0.029 IL

(6)

RFQ - Dc feed resistance. The synthesized resistance
from which battery current is fl'd to RL, see Figure 8.
(This assumes VQB is tied to VEE through a resistor
ROB.) RQB synthesizes additional dc feed resistance to
the RF value previously stated.
When using ROB, the de feed is effectively balance fed
from VCC and VQB instead of VEE. The sense resistors
(RR and RT) should be selected to make RF (first order)
less than the termination impedance.
R
_ IVEEI(98RL + RR + RT + 1200 + 2.85ROS)
Fa -

98(IVEEI -4.0 V)

(7)

IVEEI(RR
=

7.0

fO K
~

5.0 I - -

l"Standard 400 il Battery Feed

z
o

~ 4.0

III'"

in

15

3.0

50 mA Current Limit

co

~

20 - - 30 m~ C~;;rnr Limit

J" 1.0

1111

~-

............

o

111111

+ RT + 1200 + 2.85ROB)
98(IVEEI - 4.0 V)

(8)

< RT/196 -15

(12)

Using the voltage of VQB when IL is at its minimum offhook value (Typ. 20 mAl:

R
_ 98RFQ(IVEEI -4.0 V) - IVEEI(RR + RT + 1200 ill
OB 2.851VEEI
(9)

Power supply noise filter capacitor.
(10)

Figure 9B shows RQB replaced with a current regulating
device such as Motorola's 1N5283 family.
ICRQB - The current that is sourced to a current regulating device from the VOB pin. When this current
reaches the regulated value, the voltage differential between VEE and VOB increases causing the effective battery voltage to decrease which limits IL to a maximum
value as determined below:
IL = 34.5ICROB

10 k

tion resistors. These resistors should be as large i'n value
as possible. However, if they are too large, they will
interfere with the performance of the SLiC under worst
case conditions.
RpT

C
_ 2.85 ROB + RR + RT + 1200!l
OB - 2"f ROB (RR + RT + 1200 n)

r-

1.0 k
RL, LOOP RESISTANCE (il)

100

10

Therefore:

COB -

"-.....

- RL

Ignoring RL, this simplifies to:
RFQ

FIGURE 10 - TOTAL SLiC POWER DISSIPATION
versus LOOP RESISTANCE

(11)

The graph, Figure 9B, shows loop current versus loop
resistance using several values of ICROB. The closest
current regulating diode part number to that value is
also shown. A typical value for COB in this case is 10
/LF, 60 Vdc.
Figure 10 shows how power can be conserved on
the shorter loop lengths by utilizing current limiting
techniques.
Overvoltage protection on the 2-wire port is achieved
with the MDA220 diode bridge and the protection resistors RpR and RpT. Whenever the voltage on the
2-wire port exceeds the power supply rails (VCC and
VEE), the MDA220 diodes will forward bias and "clamp"
to the rail voltage. The current is limited by the protec-

RpR

< RR/196 + 251VEE - VOBI -15

(13)

The tolerance of these resistors is not critical due to
placement inside a closed loop. Positive temperature
co-efficient resistors (PTe) may be considered here.
Consult resistor manufacturers for component selections that will meet the surge current and peak voltage
requirements.
Because the MC3419-1 is a broadband device it requires compensation components to keep its circuits
stable.
CR & CT - Compensates the longitudinal gain of the
A and the B circuit mirrors. Their values range from
2000 pF to 5000 pF.
RC & Cc - Compensates the longitudinal "c" circuitry.
Their values can be ratioed according to:
RC x Cc = RT x CT.

(14)

Two off-chip power Darlington transistors are used
with the MC3419-1. These transistors reduce any temperature gradiant problems with the precision matched
devices on-chip and they alleviate thermal stress conditions that could occur for every on-hook and off-hook
transition. The power dissipation in these devices is:
POT = 'L 2(RT/98 - RpT - 4)
PaR = IL [IVEEI - 2 - 'L(RT/98

+ (2.0 V)lL

+ RL + RpR + 16)J

(15)
(16)

where IL = IVEEI/RFO or IL(max) in current limited
designs.

2-40

MC3419-1 L, MC3419A-1 L, MC3419C-1 L

SYSTEM EQUATIONS (continuedl
RH - The resistor that determines the hook status
threshold values of RL. RH is selected from a graph of
the following two equations:

lin ~

~

(171

S(RL + RR + RTI

R
(RR + RT + 1200 HII!VOB!min - !VAG!max - S.5 VI
TXl <
!VOB!min - 5.4 V
(231

On-hook threshold
RH

~

(181

27.25 [RL + O.01(RR + RTI)

Where:

FIGURE 11 - HOOK STATUS DETECTION
14
13
11
11
~ 10 _RH
~ 9.0
~ 8.0

7.0

~ 6.0
5.0

g

-::;, 4.0
 2'!T f RRXRB

1331

~

Where f is the minimum passband frequency, usually
200 Hz.

(201

Transhybrid Rejection - The voltage gain from VRX to
VTX. It is expressed in dS, the number should be negative and the larger the value the better, Transhybrid
rejection is achieved by summing a current from the
VRX input (RS) with the TXO current that flows to the
current to voltage converter. RS balances a resistive
load, RL.

and
K3 ~

-95 RL (RR + RT + 1200 {l)
RRX [(RR + RT + 120001 + RL(l + 97K31)

(191

So:
K3 ~

~

GRX

K3 - A constant, formed by RTX1 and RTX2, between
o and 1, which determines the ratio of the first order
value of RF to RO.
R

1291

GRX - The voltage gain from the VRX input to the 2wire port which is adjustable by RRX.

RO - Termination impedance of the 2-wire port. This
impedance is greater than the dc feed resistance RF
because of a current splitting network in the feedback
loop, RTXl and RTX2.

RR + RT + 12000
~
1 + 97K3

GTX(RR + RT + 1200 HI
1.02 (1 - K31

1281

(211

Zin - The input impedance of the current to voltage
converter op amp. This impedance is usually negligible,
it can be used to sway the selection of a 1% component
value.

RB ~

2-41

RRXll + 97K31 (RO + RLI
97RL 11- K31

1341

•

MC3419-1L, MC3419A-1L, MC3419C-1L
FIGURE 12 -

BALANCE NETWORK FOR CAPACITIVE LINES

~------------[]VRX

MJE271

•

TIp

CL

RL

RR

RIng

BN
'*:-----;"L------{ EN

FIGURE 13 -

BALANCE NETWORK FOR COMPLEX LOAD IMPEDANCES

RRX

CRX

1+

MJE271

T

[]VRX
VAG

,----,
I
I
I
RXII---.
'---"'W'v-----l

TSI

RTXl

RBl

I
I

I
I
I
I

I
~

I

I

RVTX
RB2 I
___ .J

+

~-~V'Ir_--~RSI

To scale Zb to its maximum values

BN

R
- R
_ RRX (I + 97K3)
bl b2 194 (I - K3)

135)

Zb = .!!.!l1(ZLi

(36)

'*---~--IEN

2RO

When the 2-wire port has a parallel Rand C load, then
(see Figure 12):
R
_ RRX(RR + RT + 120011)
bl 97RL (I - K31

(37)

R
_ RRX(RR + RT + 120011)
97RO( I - K3)
b2 -

(38)

Cb = RLCL
Rb2

(39)

ances using component values that are equal to the
load values (see Figure 13) then:
R
_ RRX(1 + 97K3)
bl 194(1",..:K.:::3:!.)_ _ _...."...----_ _ _ _ __

+

[ RRX(1 + 97K3)]
194(1 - K3)
Rb2 =

RORRX(1 + 97K3)
97(1 - K3)

RRX(1 + 97K3)
97(1 _ K3)
- RbI

Zb = ZL

When it is desirable to balance complex load imped-

Rb1 and Rb2 values are interchangeable.

2-42

(40)

(41)
(42)

MC3419-1 L, MC3419A-1 L, MC3419C-1 L
SYSTEM EQUATIONS (continued)
Figure 15 is an application circuit showing solid state
ringing insertion using an MOC3030 zero-crossing detector optocoupled triac to replace the conventional
electromechanical relay. This device inserts the ringing
signal on a zero voltage crossing which eliminates noise
in adjacent cable pairs and removes the signal on a zero
current crossing which eliminates inductive voltage
spikes that commonly destroy relay contacts. The ringing generator provides a continuous 40 V to 120 V RMS
signal from 15 to 66 Hz superimposed upon
- 48 Vdc. Ringing cadencing is inserted with the Ring
Enable Input. The 2N6558 and MPSA42 replace the
MJE270 for systems that use ringing generator voltages
greater than 70 VRMS' The MOA220 diode bridge is
replaced with a series 1N4007 on the Tip lead and a
shunting 1N4004 to VEE and to allow ringing voltage

The Tip and Ring Sense Output currents are proportional to the currents out of and into TSI and RSI,
respectively.
ITSI
ITSO ~ '""il
1431
IRSO

~ IRSI

144)

6

_ [VTiD - VccI - 2.0 V
.
ITSO 6 (RT + 60001
for VT,p < VCC

145)

_ [VRing - VaB[ -2.0 V
.
IRSO 6(RR + 600 m
for VRmg > Vas

146)

Digital interfacing to the MC3419-1 POI pin and the
HSO pin is shown in Figures 14a, 14b and 14c. If the PDI
pin is not used it should be terminated to VCC and if
HSO is not used, it can be left open.

FIGURE 14 -INTERFACE-TO-DIGITAL LOGIC

+5.0 V
10 k VOO

VOO

-12 V
-48V

-12V
750 k

(al
InterfaC8-to-Negative
Supply CMOS Logic

POI HSO
MC3419-1
VEE
-48 V

Ibl
Interface-to-LSlTL
+12 V

+12 V
62 k

160

MC14xxx

MC14xxx

kO

VCC

':"

POI

HSO
MC3419-1

1.0MO

VEE

-48V
Ic)
Interface-to-Positive Supply CMOS Logic

2-43

•

II
3:

o
FIGURE 15 -

~
......
•
......

PBX LINE CIRCUIT

CD

.r

MOC3030

r---,

REl

f-*-f
I
I 'l~ I

MPSA56
Logic Power

I

¥

.~.
I

RE2
Ring Enable

'I/VI,

RGl

I

Ringing Generator

I

L ___ JI

RHSO~

.r

RRT

Ground VCC

t
Tip

VAG 18

J--i----=-l BP

RpT
--'VV'v-

Analog Ground
RRX

RXI 17

Receive Input

TXO 16

RTXl

5· CC

POI 15

6 1RSI

HSO 14

RT

r------+----+--+~'I/IA

L

RTX2

Ring

- -J\.IIIIr - RpR

1N4007

f'
Tr.ansmit Output

lN4007

I

I 2N

I

: 6558

V* -i-i

MKl
135

I
I
.....L

RVTX

TSO 13
RSO 12
EN

lN4004

RH

HST 11
vaBllO

I
I
I

i
Q1N5303

COB

• -1E--,
J...

J~--------------JL---------------------------------------

L_______ ,

I
I

- -- -

~
......

CD

......

VCC

RG2

3:

o
o•

1
MPSA06

~
......

CD

~
......

CRT

Hook Status
Output

N

3:

o

,

Indicates Optional Components

Negative Battery

r

MC3419-1 L, MC3419A-1 L, MC3419C-1 L
SYSTEM EQUATIONS (continued)
on the Ring lead to exceed the power supply voltages,
a lN4007 and an MK1V-135 (Sidac) are used for protection. The forward voltage drop across the 1N4007,
during normal operation, will not affect the parametric
characteristics of the MC3419-1 since it is "inside" a
feedback circuit. If the MJE270 is used, the MK1V-135
should be replaced with a lower voltage Sidac or
MO·sorb transient suppressor.
An optocoupled transistor circuit is used for ring trip
detection on long lines. It samples only the ac and dc
ringing signal current and uses a simple one pole filter
to eliminate the low level ac signal. Under worst case
conditions this circuit will ring trip in 1V, to 4 cycles. In

systems serving only short loops «700 0), if RGl and
RG2 are 620 n or greater, the optotransistor circuit is
not needed, the Hook Status Output will perform ring
trip on a Zero Crossing. The Ring Enable input and the
Hook Status Output interface with standard CMOS and
TTL logic.
The op amp in this circuit is an integral part of the
following codecs, filters or combos:
MC341718 -

MC145414

MC14404/6/7 MC14401/2/3/5

MC14413/4

LONG LINES OFF-PREMISE LINES

Specifications
RF
IL(max)

- 200n
-60mA

RO
RX Gain

-

RL(max)

-1900n

TX Gain

-

600n
Od8
200-3400 Hz
OdS
200-3400 Hz

Off-Hook
On-Hook

-

<2500 n
>10 kn

VLogic
VEE

-

Protection

-

1000 V

VRinging

-

Ringer Equivalent -

+5.0 V
-42 to -56
Volts
(40 Vto 120
VRMSI+VEE

5

Parts List
MPSA56
2N3905
2N6558
MPSA42
MJE271
lN4007
MK1V135
lN4007
lN4007
lN5303
lN4004
MC3419-1

RR
RT
RpT
RpR
RGl
RG2
REl
RE2
RRT
RC
RH
RHSO

9.09 k
1% Matched
9.09 k
1% if desired
47 n
5%
75n
5%
620 n
5%
lOOn
5%
91 n
5%
3.0 k
5%
20 k
5%
24 k
5%
127 k 1-3%
10 k
5%

MOC3030
4N25

RTXl
RTS2
RRX
RS
RVTX
CT
CR
Cc
CRX
CTX
CRT
COB

12.1 k
1%
1%
5.76 k
28.7 k
1%
28.0 k
1%
1%
28.6 k
0.004 J.'F
0.004 J.'F
0.001 J.'F
1.0 J.'F/20 V
2.0 J.'F/40 V
20 J.'F/5.0 V
10 J.'F/60 V

SHORT LINES ON-PREMISE LINES
Specifications
500 n
700 n
<50 ms
2.5
600n

RF
RL(max)
Ring Trip
Ringer Equivalent
RO

-5.0 dB

RX Gain
TX Gain
VLogic
VEE
VRinging

o dB
+5.0 Volts
- 20 to - 56 Volts
(40 V to 70 VRMS) + VEE

Parts Ust
MJE271
MJE270
MPSA56
2N3905
lN4007
lN4007
MC3419C-l

RR
RT
RGl
RG2
REl
RE2
RH

19.6 k
19.6 k
620 n
620n
91 n
3.0 k
330 k

1%
1%

MOC3030

5%

CT
CR
Cc
CRX
CTX

5%
5%
5%

5%

2-45

0.004
0.004
0.004
0.1
0.5

J.'F
J.'F
J.'F
J.'F
J.'F

RHSO
RTXl
RTX2
RRX
RB
RVTX
RC

10
19.6
42.2
69.8
301
127
56

k
k
k
k
k
k
k

5%

1%

1%
1%
1%
1%

5%

•

®

MC34F19
MC34F19A

MOTOROLA
Advance Information

•

SUBSCRIBER LOOP
INTERFACE CIRCUIT
(SLlC)

TELEPHONE LINE FEED AND 2- TO 4-WIRE
CONVERSION CIRCUIT

BIPOLAR THIN-FILM
INTEGRATED CIRCUIT

· .. designed to replace the hybrid transformer circuit in Central
Office, PABX and Subscriber carrier equipment, providing signal
separation for two-wire differential to four-wire single-ended conversions and suppression of longitudinal signals at the two-wire
input. It provides de line current for powering the telset, operating
from up to a 56 V su pply.
• All Key Parameters Externally Programmable
• Current Sensing Outputs Monitor Status of Both Tip and Ring
Leads
• On-Hook Power Below 5.0 mW
• Digital Hook Status Output
• Power Down Input
• Ground Fault Protection
• Size and Weight Reduction Over Conventional 'Approaches

L SUFFIX
CERAMIC PACKAGE
CASE 726-01

• The sale of this product is licensed under patent No. 4,004,109.
All royalties related to this patent are included in the unit price.

FUNCTIONAL BLOCK DIAGRAM
VCC

r- -- ---- - - ------,
81 Mirror

I
I

J

,..----------I
I
I
I
I
L

~

EP

I

Tip

RT TSI

on

I
I
I
I
I

L. __

~

iI

A1 Mirror

Bias

RSI

r~~r
I
EN
I
IL ________

.,
I
I

L __

I

~

---

-0

~
RSO
TSO

r

RX

~

Receive Input

RRX

-(+
HSO

Hook
Status

I
~?r~~~1 I

HST

ffi

INetwork
Balance I

-- ----- --,

~

L:l!
-

Analog Ground

VAG

t

~_______ Ji

<}F
r-

I

CJ

-- --

CC
RR

on

"1"1 ! t

-

4' )

I

0

'" '"

1

BP
__ ~

i

0

:ll

B2Mirror:

RTX1

I
I
I

I

I
I
I

+

I

! tA2 MirrorJ

&p

.~

+

TX

BraS

RvTx"
VaB

This document contains information on a new product Specifications and information herein
are subject to change Without notice.

2-46

_Jf

RTX2

_____________ J

V EE

Transmit
Output

MC34F19, MC34F19A
MAXIMUM RATINGS
Rating

Voltage (Referenced to Vcc)
Sense Current

Symbol

Value

Unit

VEE
VOB

-60
VEE-1

Vdc
mAde

ITSI.IRSI
100
200

Steady State
Pulse - Figure 4
Storage Temperature Range
Operating Junction Temperature
(9JA = 100"CIW Typ)

-65 to

Tstg

+ 150

°c

150

TJ

°c

OPERATING CONDITIONS
Rating

Unit

Value

Symbol

Operating Ambient
Temperature Range

TA

o to

Loop Current

IL

20 to 120

Voltage

VEE
VOB

-20to -56
-20 to VEE

Analog Ground
OL = 0 to 60 mA
OL = Oto 120 mAl

VAG

Supervisory Output Voltage

PIN CONNECTIONS

+ 70

°c

o to -12
-2.5 to -12

VRSO. VTSO.
VHSO

-2.0to-20

Vcc
EP

RX

BP

TX

TSI

POI

CC

HSO

RSI

TSO

BN

RSO

EN

HST

VEE

VOS

mA
Vdc
Vdc

Vdc

PIN DESCRIPTIONS
Function

Name
VCC

The most positive supply voltage. This point is Earth Ground in most typical applications.

BP & BN

Are the base drive outputs for the PNP and NPN Darlington transistors.

EP& EN

Are loop CUlrent sensing inputs and are connected to the emitter of the PNP & NPN Darlington transistors.

TSI & RSI

Are the tip and ring current sensing inputs. They are low impedance inputs (approximately 600
translate the voltage on tip and ring to a current through Resistors RT and RR.

CC

Compensation capacitor input.

VEE

Is the most negative supply voltage.

VOB

Is the quiet battery connection, The voltage on this pin must not go more negative than VEE.

HST

Hook Status Threshold programming resistor input pin. This pin programs the value of loop resistance
which determines on-hook or off-hook status.

RSO

Ring Sense current Output. This output reflects the status of the Ring termi'rlal. The current is sourced from
this output and is one-sixth IRSI,

TSO

Tip Sense current Output. This output reflects the status of the Tip terminal. The current is sourced from
this output and is one-sixth ITSI.

HSO

Hook Status Output. This is a digital output lopen collector PNP) that sources current when the loop
resistance is less than the threshold resistance value set by RH,

POI

Power-Down Input pin. A logic level "0" powers down the MC34F19.

n

each) that

+ IRSI)/2.

TX

Transmit current output. This output sinks current proportional to OTSI

RX

Receive input. This input sums the currents from the TX output and signal input, This pin has a low input
impedance.

VAG

Analog ground reference supply voltage input.

2-47

•

MC34F19, MC34F19A
ELECTRICAL CHARACTERISTICS (VEE = -48 V, VQB = -48 V, VAG = -6.0 V, RL = 900 ll, TA = 25"C unless otherwise
noted)
Figure

Symbol

Min

Typ

Max

Unit

Transhybrid Gain Variation (1.0 kHz @ 0 dBm Input)
Transmission/Reception

I

VTXNL,
VLNRX

-0.3

0

+0.3

dB

Transhybrid Rejection (1.0 kHz @ 0 dBm Input)
Fixed (1%) Resistor Balance Network
Trimmed Balance Network

I

VTXNRX
-23

-

Level Linearity (-48 to +3.0 dBm, referenced to
output @ 1.0 kHz (a 0 dBm)

1

Characteristic

•

-

-55

dB

Transmission

VTXNL
VLNRX

Reception
Frequency Response (200-3400 Hz, referenced to
output @ 1.0 kHz (a 0 dBm)

dB

-

-0.1
-0.1

O.
0

+0.1
+0.1

I

dB

Transmission

VTXNL
VLNRX

Reception
Total Distortion
C-Message Filtered

I

VLNRX
VTXNL

-0.1
-0.1

-

0
0

+0.1
+0.1

-60
-60

-

-

Idle Channel Noise

1

VTX

-

Termination Resistance Tolerance (a 1.0 kHz

I

.1 Po

-

-

Longitudinal Induction - 60 Hz
ilL = 30 to 100 rnA. ILON = 35 rnA RMS)

2

VTX

-

5.0

-

Longitudinal Balance
MC34F1S (200-3000 Hz)
MC34F1SA (200-1000 Hz)
MC34F1SA (3000 Hz)

2

VTXNLON

-

-

Propagation Delay

1

-45
-50
-48
Tp, VRX to VL
VRX to ITX

Power Dissipation (RL > 100 Mll)

Po

Supply Current - On-Hook
(VEE = VQB = - 56 V, RL > 100 Mll)

ICC

Power Supply Noise Rejection (1.0 kHz (a 1.0 V RMS)

3

VTXlvee

Quiet Battery Noise Rejection (1.0 kHz (d 1.0 V RMSI

3

VTX/Vab

Sense Current
Tip
Ring

4

Fault Currents - On-Hook
Tip to VCC
Ring to VCC
Tip to Ring
Tip & Ring to VCC

1

-

-40

-

-

750
1.2

-

1.0
40

200

-

-

-6.0

dBrncO
%
dBrncO
dB

-

-

ns
J.I.S
mW

"A
dB
dB
rnA/rnA

ITSO/ITSI
IRSO/IRSI
ITip
IRing
ILoop
ITiD & IRina

0.15
0.15

-

0.17
0.17

-

0
2.5
120
2.5

Analog Ground Current

lAG

-

1.0

Power Down Logic Levels

IpDI
VIH
VIL

-

-1.0
0

Hook Status Output Current
(RL < 2.5 kll, POI = Logic 1)
(RL > 10 kll, or POI = Logic 0)

10
±5.0

dB

1

-1.2
-20

-

IHSO
200

-

2-48

400
0

0.1S
O.IS

-

rnA

-

10

-4.0 .
2.0

"A
"A
Vdc
Vdc

"A

MC34F19, MC34F19A

FUNCTIONAL DESCRIPTION
Referring to the functional block diagram, linesensing resistors at TSI and RSI convert voltages at the
Tip and Ring terminals into currents which are fed into
current mirrors' Aland A2. The output of Al is mirrored
by A3 and summed together with an output of A2 at
the TX terminal. Thus, a differential to single-ended conversion is performed from the ac line signals to the TX
output.
All the dc current at the TX output is fed back through
the RX terminal to the Bl mirror input. The inputs to Bl
and B2 are made equal by mirroring the Bl input current
to the B2 input through a low gain output (xl) of the Bl
mirror. Both Bl and B2 mirrors have high gain outputs
(x95) which drive the subscriber lines with balanced
currents that are equal in amplitude and 180' out of
phase. The feedback from the TX output, through the
B-Circuit mirrors, to the subscriber line produces a dc
feed resistance significantly less than the loop sensing
resistors.
In most line-interface systems, the ac termination
impedance is desired to be greater than the dc feed
impedance. A differential ac generator on the subscriber
loop would be terminated by the dc feed impedance if
the total ac cu rrent at the TX output were retu rned to
the Bl input along with the dc current. Instead, the
MC34F19 system diverts part of the ac current from the
B-Circuit mirrors. This decreases the ac feedback current, causing the ac termination impedance at the line
interface to be greater than the dc feed impedance.
The ac current that is diverted from the Bl mirror
input is coupled to a current-to-voltage converter circuit
that has a low input impedance. This circuit consists of
an op amp and a feedback resistor external to the
MC34F19 which produce the transmit output at the
4-wire interface. The transhybrid transmission gain is
programmed by the op amp feedback resistor.
Transhybrid reception is realized by converting the
ac coupled receive input voltage to a current through
an external resistor at the low impedance RX terminal.
This current is summed at RX with the dc and ac feedback current from the A-Circuit mirror and drives the
B1 mirror input. The B-Circuit mirror outputs drive the
line with balanced ac current proportional to the receive
input voltage. The transhybrid reception gain is programmed by the resistor at the RX input.
Since receive input signals are transmitted through
the MC34F19 to the 2-wire port, and the 2-wire port
signals are returned to the 4-wire transmit output, a
means of cancellation must be provided to maintain
4-wire signal separation (transhybrid rejection). Cancellation is complicated because the gain from the
receive port to the transmit port depends on the impedance of the subscriber loop. A passive "balance network" is used to achieve transhybrid rejection by cancelling, at the low impedance input to the transmit op
amp, the current reflected by the loop impedance to the
4-wire transmit output. For a resistive loop impedance,
a single resistor provides the cancellation. For reactive
loops, the balance network should be reactive.

Longitudinal (common-mode) currents that may be
present on the subscriber lines are suppressed in the
MC34F19 by two methods. The first mode of suppression is inherent in the mirror configuration. Positivegoing longitudinal currents into Tip and Ring create
common-mode voltages that cause a decreasing current through the Tip Sensing resistor and an increasing
current through the Ring Sensing resistor. When these
equal and opposite signal currents are reflected through
the A-Circuit and summed together at TX, the total current at TX remains unchanged. Therefore, the ac currents due to the common-mode signals are cancelled
before reaching the transmit output.
The second longitudinal suppression method is dominant, since it limits the amplitude of common-mode
voltages that appear at the Tip and Ring terminals.
Through an error-detecting circuit, the input of which
is a difference current between outputs of Al and A2,
the impedance at Tip and Ring to longitudinal currents
is kept very low. This is accomplished with a high gain
C-Circuit which produces Bl and B2 output currents that
are equal and in phase to cancel the longitudinal line
currents. Operation of this circuit does not affect the dc
line-current or the processing of normal differential line
signals.
The hook-status control circuit supplies the bias currents to activate the B-Circuit op amps and other sections of the MC34F19. If the PDI pin is a logic "one,"
the control circuit senses two outputs from the Aland
A2 mirrors. If both of these output currents are greater
than the preprogrammed current at the HST terminal,
the control circuit supplies currents to power up the
SLiC. At the same time it activates a digital status output, HSO.
In addition to the digital hook status output, the condition of Tip and Ring can be monitored at the TSO and
RSO outputs of the MC34F19. These outputs source currents proportional to the TSI and RSI input currents
respectively, and operate independently of the PDllogic
input.
The MC34F19 has two negative battery terminals. VEE
supplies the high current through the B2 mirror to drive
the line. B2 has a high output impedance and battery
noise will not be coupled to the line from the VEE terminal. However, VOB is quite sensitive to noise, since
the line-sensing resistor is referenced to this pin
through the A2 mirror, and should be bypassed with a
filter network to guarantee a high rejection of battery
noise.
The VAG input also plays a key role in reducing
power-supply related noise that can occur when the
MC34F19 system is coupled to a switching system. The
analog ground isolates the 4-wire receive and transmit
signal paths from noise on the system power ground
by establishing a common ac signal reference.
*A current mirror is a circuit which behaves as a current controlled.
current source. It has a single low-impedance input terminal and one
or more high impedance outputs.

2-49

•

MC34F19, MC34F19A
FIGURE 1 -

AC TEST CIRCUIT

1.0 J.O-;-:';~=-I

~2~~~9J

MC6172
Modulator

B2

DPSK Signal

MC1406
D/A
Converter

to Lme

Bl
Option B (U.S.)

BO

Signal Spactr.

0

Clk

-10

-20
-30

-50
1.8432 MHz
±O.005%

1.0

3,0

2.0
kHz

2-64

4.0

5.0

MC6172
DELAY TIMINGS (See Figures 4 and 5)

Characteristic

Symbol

~ to DBC Delay

tl

DBC to RTS Delay

t2

m-~Delay

t3

RTS-CTS Delay
CTSl = 0, CTS2= 1
CTS1=1, CTS2=0
CTSl = 1, CTS2= 1
CTS1-0, CTS2-0

\4"

CTS-DBC Delay
CTSl = 1, CTS2=0
CTSl = 1, CTS2= 1
CTS1-0, CTS2-0

t5

RTS to CTS Low

t6

Min

Typ

Max

Unit

8

I's

45

I's

35

I's

35

I's
ms
ms
ms

0
8.55
24.9
147.0

-

-

-

35

-

-

1.60

ms
ms

-

935
26.4
154.0
35
35

I'S

RTS Min Delay

t7

1.67

DBC to DRTS Delay

t8

35

I's

833.37

I'S

DBC Cycle Time

tD8C

833.28

833.33

"The reference frequency tolerance is not included.

FIGURE 4 - m-CTS AND m-~ DELAYS
2400 bps
Mode

Tx Clk

1200 bps
Mode

RTS-CTS delay options are selected by the CTSl and CTS2 inputs, and are stated as time delay Interval \4. An RTS Input signal
synchronized about pOint A will synchronize
with the positive

rn

transition of DBC (O,blt Clock). Delay t4 IS measured with respect to

the negative tranSItIOn of m.
RTS Signals synchronized with the posItive tranSItion of DBC
(point B), Will result In the same CTS delay (\41. For thiS case the
negative transItion of CiS' IS synchronized with the negative tranSItion of DBC with delay \4 measured with respect to the negative
transItIOn of R'i"S".

rn.

DRTS will go low within t3 of the ne~e transition of
With
the exception of the no-delay option, "CfS will go low within t5 of
the positive transition of DBC, following the \4 delay selected. ThiS
applies when
is synchronized to POlOt A as shown
If !ITS goes high and remains high", 20l's within time Interv~
a reset of the Internal lITS-CTS timer function Will occur. If Ri'S"
goes high for less than 20I'S, the CirCUit mayor may not respond to
thiS momentary loss of the
signal.

m-

m

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

2-65

•

MC6172
FIGURE 6 - LOSS OF

iiTs TO ffiii'S DELAY

•
A positive transition of RTS after CTS has become active can
result in different functional characteristics of the ffi and DRTS
output signals, depending on the time duration that
active.

Under all conditions,

m

remains in-

CfS will go high within t3 following a

m.

positive transition of
If R'TS goes high in the shaded region
shown (i.e., synchronized to the positive transition of DeC) and remains high beyond the time interval defined as t7, then ~ will

go high within IS of the ~ n~tive tranSition of DBC. If iITS were
to go low after t7, the RTS-CTS delay times given in Figure 4 will
result.

If RTS goes high In the shaded region shown, and then returns
low within time Interval 16, the negative transition of CfS will follow

within 35 J45, and ~ will remain in the active or low state. Under
these conditions, the normal m-~ delay times are not en-

countered when Ri'S is reactivated. If fITS goes low for less than
20 ,,8, the circuit mayor may not respond

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

DEVICE OPERATION
the negative transition of RTS, and goes negatIVe within t3
of the negative transition of RTS (Figure 4). The delay from a
positive transition of RTS to a positive transition of ORTS is
shown In Figure 5. The ~ delay allows data within the
modulator to be transmitted before transmission IS inhibited.

GENERAL
Figure 3 shows the modulator and its mtra-connections.
The data to be transmitted is presented in synchronous serial
format to the modulator for conversion to OPSK signals
used in transmission. The modulator output is digital;
therefore, a 0/ A converter and a filter transform the signal to
an analog form.
.
The control functions provide four different Clear-to-Send
delay options. An Answer-Back tone is available for
automatic answering appl;'catlons. The modulator has a
built-in 511-blt pseudorandom pattern generator for use in
system diagnostic tests.

Clear to Send (eTS)
CTS follows RTS to both the logic 0 and logic 1 levels. The
delay from a negative transition of
to a negative CTS
transition IS selectable by external strapping of CTS 1 and
CTS2. The delay from a positive transition of RTS to a
positive CTS transition is less than t4.
CTS will go low within t5 after the positive tranSition of the
Oibit Clock Isee Figure 41 except when the non-delay optIOn
is selected. For the no-delay option, CTS follows
within
t5·

m

INPUT/OUTPUT FUNCTIONS

m

Request to Send (RTS I
The RTS signal from the data terminal controls transmission from the modulator. A low level on
activates the
modulator data output. A constant mark, for synchronization, is sent dUring the RTS to C'i'S delay interval. Termination of the transmission IS accomplished by taking RTS high
(see Figures 4 and 51.

m

RTS-CTS Delay Options (CTS 1, CTS21
The RTS-CTS delays are selectable according to the
following strapping options

m-mOelay
0.0+0.035 ms, -0.0 ms
8.55 to 9.35 ms
24 90 to 26.4 ms
147.0 to 154.0 ms

Delayed Request to Send (D RTS I
This output can be used to control transmission as
specified by the Transmit Mark control input. ~ follows

2-66

CTS1

CTS2

0
1
1
0

1
0
1
0

MC6172
selected by the Test Pattern Enable Signal or any other Signal
that is found suitable.

Transmit Mark (Tx Mk)
The Transmit Mark control allows the system designer to
select whether the Delayed Request to Send activitates and
deactivates the transmission on the modulator chip or off the
chip in the output amplifier.
When Tx Mk is high, transmission is controlled on the
modulator ChiP, and occurs from the chip only when DRTS
or Answer Back IS In the logic 0 state Isee Figure 61.
When Tx Mk IS low, transmission is controlled off the
modulator chip. In this mode, the modulator chip transmits
marks at all times except when data 01 an Answer-Back tone
is being transmitted (see Figure 61.

The scrambling of data in the data comm environment is
not done in an attempt to encrypt information in the normal
sense of the word. Rather, the purpose of the scrambling of
data IS to guarantee that With respect to the modem carrier,
there IS always random data on the Ime With little chance for
a long string of ones or zeros to eXIst. This is particularly important if an adaptive equalizer IS being Incorporated at the
demodulator. The adaptive equalizer Will reqUire reasonably
evenly distributed data to optimize its statistical response to
the Incommg signal. The normally used code IS the CCITT
511 sequence which is exclUSive ORed With data
The test pattern generator can be enabled only when CTS
and RTS are logiC O. If TPE IS activated outSide thiS time interval, the previously stated RTS-CTS and RTS-DRTS
delays, shown in Figures 4 and 5, are not valid.

Test Pattern Enable (TPE)
A 511-bit test pattern generator is contained on the
modulator chip. ThiS pattern is in accord with CCITT
specification V52.
The 511-bit test pattern is activated by applying a logic 0 to
ill. A mark 1I0gic 11 condition on the Transmit Data Input
with TPE activated Ilogic 0) causes the test pattern to appear
at the data output. A space 1I0gic 0) condition on Tx Data
with ;IT activated causes the test pattern data to appear inverted at the data output.
Although the Motorola 2400 bps modulator contains a
CCITT 511 test pattern generator it does not Incorporate the
511 data randomlzer or scrambler.
Random data applied to Tx Data with TPE activated
causes the test pattern data to be scrambled lexclusive
NORedl with the data, and the result appears at the data
output.
The MC6173 demodulator does contain a built-In data
descrambler, which is enabled by TPEinput going active. To
scramble data using the modulator, the CIrCUit In Figure 7
must precede the Tx Data mput of the modulator Tx Data is
added to the scrambler output pattern. Then the data IS
delayed by a full data bit before being transmitted by the
modem. This assures a proper Transmit Data/Transmit
Clock phase relationship.
If the data scrambler is to be an optional feature, then the
transmit data multiplexer would also have to be built. This is

Data-Rate Select (DRS)
The modulator can transmit at either 2400 bps or 1200 bps.
Both data rates utilize an 1800 Hz carner Signal and employ
phase shifting at 1200 Hz. The 2400 bps rate IS obtained by
encoding two bits of data into each phase shift. The 2400 Hz
rate is selected by applymg a logiC 1 to the Data-Rate Select
lead. The 1200 Hz rate IS selected by applYing a logic 0 to
DRS.
Phase-Shift Select (PSS)
Option A ICCITT) or Option B (U.S.I phase shift can be
selected for 2400 bps operation. The input data format and
phase shift relationship for these two options are as follows:
PSS=O
Data
00
01
11
10

PSS=1
Option B
+45'
+135'
+225'
+315'

Option A*

0'
+90'
+ 180'
+270'

• See example Figure 8.

FIGURE 6 - TRANSMIT MARK CONTROL

I

I

I
I

No
Tx Mk = High

No

No

Signal

An Bk
Signal

Signal

Marl<

Data

Signal

Mark

An Bk
Signal

Mark

&.-1ark

0"",

Mark

2-67
---_._-----

•

MC6172
FIGURE 7 - MODULATOR CCITT 511 DATA SCRAMBLER

{1.." ' . - - - - - - 5 1 1 Oala Scrambler----l... }

{l.." " ' f - - - - - l-BII Delay

-------i...}
D

•

Q

Tx elk

Tx Oala ....- - - - - i

~~--------+--------------.--~
b-_T;.cx",D::;a::;ta::..-__ To Pin 9 Modulalor

{.."'f-----Data Mulliplexer - - - - l...}

FIGURE 8 - EXAMPLE-CARRIER PHASE SHIFTS FOR OPTION A

Serial Data

Dala

11011000

'\
Dibil

01
90°

II
lSOo

10
270°

PSS=O
OptionC
+90°
+270°

00
01
II
10

0°
90
ISO
270

Transmit Data (Tx Data)
Transmit Data is the serial binary information presented
for DPS K modulation. A high level represents a mark. For
timing, see Transmit Clock (Figure 4),

For .1200 bps operation, Option C (CCITTI or Option D
(U.S') phase shift can be selected:

Data
0
I

00
0°

Phase Shift

PSS=1
Option 0
+46°
+225°

Transmit Clock ITx Clk)
A 2400/1200 Hz Transmit Clock output is provided for the
communication terminal. The Transmit Data signal is sampled on the positive transition of Transmit Clock. The Transmit
Data to Transmit Clock setup and hold time requirements are
shown in the Electrical Characteristics Table and in Figure 2.

Option C is selected by applying a logic 0 to the Phase
Shift Select lead when the Data Rate Select lead is strapped
for 1200 bps operation (logic 0), Option D is selected by applying a logic 1 to PSS with DRS at logic O. The phase shifts
shown are the difference in phase between the signal at the
end of one dibit period and the new signal at the beginning
of the next dibit.

Dibit Clock IDBC)
A 1200 Hz Dibit Clock identifies the modulation timing.
This signal goes negative less than 100 I£S prior to the start of
dibit modulation.

2·68

MC6172
External Clock (Ex Clk)

from a transition on An Bk to the appropriate signal at the
modulator chip output is less than 2 ms.
Activation of An Bk (a logic 0) will disable all other operation modes including the Tx Mk function, and will reset CTS
to an inactive state along with the RTX-CTS internal timer.
An Bk should therefore be activated only before initiating
RTS or after loss of the "l5'm output signal. The combination of a logic 0 on An Bk with a logic 0 on TPE is not used in
normal system operation, and hence is used as a reset input
during device test.

A 2400/1200 Hz clock signal applied to the External Clock
lead causes Transmit Clock to be synchronized with Ex Clk.
This input must have an accuracy within ± 0.005%.
When no transitions occur on this input, the internal clock
provides the 2400/1200 Hz transmit timing signal. Fast synchronization of Tx Clk to Ex Clk is not provided on the chip.
When Ex elk is not used. it should be tied to either the logic 0
or logic 1 state.

1.8432 MHz (Clk)
This input must be a square wave with rise and fall times
of less than 40 ns and a 50 ± 20% duty cycle. The clock accuraey must be written ± 0.005% .

Digital Output (Bo-B5)
These outputs are designed to interface with a 6-bit
digital-to-analog converter. The resultant signal out of the
DI A is the differential phase shift keyed signal quantized at a
14.4 kHz rate. A low-pass filter can then be used to smooth
the data transitions. BO is the least-significant bit, and the
positive level the active state.

Answer Back (An Bk)
A logic 0 level applied to Answer Back causes a 2025 Hz
carrier to be generated on the modulator chip instead of a
phase shifted 1800 Hz carrier. A logic 1 level applied to An Bk
enables the modulator to generate the normal phase shifted
1800 Hz carrier signal, as shown in Figure 6. The time delay

T881: Clock (TST)
A test signal input is provided to decrease test time of the
chip. In normal operation this input must be strapped low.

2-69

•

®

•

MC6173

MOTOROLA

2400 bps DIGITAL DEMODULATOR

MOS
IN-CHANNEL, SILICON-GATE)

The MC6173 IS a MOS subsystem designed to be integrated Into a
wide range of equipment utilIZing senal data communication
The demodulator provides the necessary demodulation and control
functions to Implement a senal data commUnication link over a vOice
grade channel, utilizing differential phase Shift keying IDPSK) at bit
rates of 1200 or 2400 bps Phase optIOns are provided for both the U.S
and international markets The MC6173 can be Implemented Into a wide
range of data handling systems, including stand-alone modems, data
storage devices, remote data commUnication terminals, and 1/0 interfaces for counters
N-channel silicon gate technology permits the MC6173 to operate
uSing a single voltage supply and be fully TTL compatible.
The demodulator IS compatible with the M6800 microcomputer
family, and provides medium-speed data communications capability
•
•
•
•

Compatible with MC6172 Modulator
511-Bit CCITT V.52 Test Pattern
Terminal Interfaces Are TTL Compatible
Compatible Functions for 201B/C and V.26 Data Sets

•
•

CCITT and U. S Phase OptIOns
1200/2400 bps Operation

2400 bps
DEMODULATOR

L SUFFIX
CERDIP PACKAGE
CASE 623

P SUFFIX
PLASTIC PACKAGE
CASE 709

FIGURE 1 - TYPICAL APPLICATIONS

Telephone
Line

PIN ASSIGNMENT
VSS

8

'"

:;

"0
0

E

'"

'"c.

~
"0

8v
Rx Data

.g'"
'"
E

Rx Clk

~
en

U·

N

RDI

'"<0
u
=:;;

TStr

90° Eye

DBC

ADC

.0

"-

RDI

DCD

0° Eye

0

m

0° Car

"0

«
:J
0-

Data

=:;;

Rx Clk
CCor

TPE

ADS

PSS

Rx Data

TIn

Env
NSync
VCC

2-70

DRS

FCar

CarS
Clk
TClk

MC6173
MAXIMUM RATINGS
Rating

Symbol

-

Value

This device contains circuitry to protect the

Inputs against damage due to high static voltIt IS advised
that normal precautions be taken to avoid application of any voltage higher than maxI-

Unit

Supply Voltage

VCC

-03 to + 70

Input Voltage

Y,n

--03to+70

V

Operating Temperature Range

TA

o to 70

Storage Temperature Range

Tstg

- 55 to+ 150

'c
'c

Thermal Resistance

8JA

825

'C/W

-

ages or electric fields; however,

V

mum rated voltages to thiS high-Impedance

Circuit Reliability of operation IS enhanced If
unused Inputs are tied to an appropriate logic
voltage level Ie g., either VSS or VSSI

DC ELECTRICAL CHARACTERISTICS IVCC=5 0 ±0.25 Vdc, VSS=O, TA=TL to TH
all outputs loaded as shown rn Figure 3 unless otherwise noted)

Characteristic

Max

Symbol

Min

Typ

Input High Voltage

VIH

VSS + 2.0

-

VCC

V

Input Low Voltage

VIL

VSS

-

VSS+08

V

Input Current

IlL

-

-

-02

mA

lin

-

-

25

~A

VOHI
VOH2

VSS + 24
VCC-05V

-

VCC
VCC

V

-

Output Low Voltage
IIOL = 1 6 mA, Load AI

VOL

VSS

-

VSS + 0 4

V

Input Capacitance

CIn

-

50

-

pF

630

mW

Unit

IV,n = VILI Pins 3, 11, 13, 15, 16, 17, 18, 22, 24
Input Leakage Current

IV,n =5 25 Vdc, VCC=VSSI Pins 2,10,14,23
Output High Voltage
IIOH~ -004 mA, Load A)
IIOH = 00 mA, Load BI

If=O 1 MHz, TA=25'CI
Internal Power DISSipation (measured at TA::::: TL~

Pint

-

IAII Inputs at VSS except Pin 13= 576kHz and ALL Outputs Open)
Input Transition Times, 1 8432 MHz Input

tr
tf

IFrom08Vt020V)
Input Transition Times,

-

40
40

ns

-

-

tr,tf

_.

-

10'

~s

Output Transition Times (From 10% to 90% POints)

tr,tf

-

-

50

~s

Input Clock Duty Cycle, 1 8432 MHz Input IMeasured at 1 5 V levell

D.C

30

-

70

%

Data Setup T,me

tDS

770

-

-

ns
~s

All Inputs Except 1 8432 MHz Input IFrom 10% to 90% POlntsl

tsu

35

-

-

thlDI

0

-

-

ns

th

35

-

-

~s

Data-Clamp Delay Time
OptIOn 1
OptIOn 2
OptIOn 3
OptIOn 4

tDCDl
tDCD2
tDCD3
tDCD4

57
4135
20795
104 135

6
417
20.83
104.17

63
4205
20865
104 205

ns
ms
ms
ms

AID Clock to AID Strobe Delay Time

~s

Rx Data Setup Time
Data Hold Time
Rx Data Hold Time

tADCD

106

-

1.11

Envelope-to-Dlblt Clock Delay Time

tED

140

-

220

~s

Clock Frequency, ± 0005%

fClk

1.8432

-

MHz
~s

-

217

-

AID Clock Pulse Width

twlADCI

940

1000

1040

ns

AI D Strobe Pulse Width

twlADSI

-

10.85

-

ns

New Sync Input Pulse Width

tw
INSyncl

084

-

ms

tcyc

AID Clock Cycle Time IfClk/41

-MaXimum Input transition times are

s

-

0 lX pulse Width or the specified maximum of 10 p's, whichever

2-71

-

IS

smaller

•

MC6173
FIGURE 2 Data
Aate
Select

Clock

24

Carrier

•

DEMODULATOR BLOCK DIAGRAM

Envelope

14

19

20

17

21

Correction

Ax Clock

Phase
Shift
Select

7
5
4

D,b,t Clock IDBCI

0° Carner
0° Eye
90 0 Eye
Test Clock
Test Enable

Ax Data In (ADII

~Strabe

6
AID Clock
AID Strobe

8

2

Fast
Carner

1-_1-'9;.,. Ax Data Output (Ax Datal

New
Sync

FIGURE 3 - OUTPUT TEST LOADS
Load B

Load A - TTL Output Load

,----------,I
VCC

I
I
II
I
I
I

MMD6150
VI

AL

I
I
II
I
I
I
MMD7000 I
or Equlv.

50 k
I
± 1%
I
I
~I;.,I~~C-LO~_=_ _ _ _.J
CT = 20 pF = total parasitic capacitance. which Includes
probe, wiring, and load capacitances

2-72

MC6173
GENERAL DESCRIPTION

training allows for large corrections to be made In the internal timing of the demodulator. After the fast training period,
the timing should be reasonably well adjusted SmalJ adJustments are made automatically to maintain proper phase relationships internalJy after the fast-train period.
The FCar Input, which normalJy comes from the carner
threshold detect CIrCUitS, must remain at a low level dUring
the entire period of baud and carner synchronIZation
A pOSitive level on the FCar Input will disable the baud and
carner correction circuitry Baud and carner timing are then
direct derivatives of the 1.8432 MHz clock as Illustrated In
Figure 4.
The first positive edge of the envelope (Envl Input will be
totally asynchronous to the demodulator. This will be ± Y,
cycle of the 2400 clock (± 208 I'sl The nine following
positive edges will Introduce added tolerance equal to nine
times the offset of Env from the absolute 1200 Hz (as defined
by the 1.8432 MHz ±0.005% clockl. Thus.
Max Fast Train Time = 4.17 ms + 9 fEnv + 0.21 ms
= 4.38 ms + 9/fEnv
Min Fast Train Time =4.17 ms-0.21 ms+9/fEnv
= 3.96 ms + 9/fEnv

The MC6173 Phase-Shift Key (PSKI Demodulator serves
as an Integral part of a system to recover synchronous data
from an 1800 Hz PSK modulated carner. Data rates of 1200
and 2400 bits-per-second are available. In the case of 1200
bps operation, the MC6173 detects phase shifts of 0 to 180
degrees to represent digital "Os" and "ls" When 2400 bps
operations is desired, the MC6173 detects phase shifts of 0,
90, 180, and 270 (option AI or 45, 135, 225, and 315 (option
BI degrees to represent two bits of data called dib,ts. These
phase shifts decode to 00, 01, 10, and 11, respectively. In
either data rate, the 1800 Hz carner IS modulated at a 1200
rate.
Figure 1 shows the MC6173 demodulator In a tYPical application. The band-pass filter, equalIZer, analog-to-dlgltal
(AiDI converter, 1200 Hz envelope filter, AGC amplifier, and
1800 Hz carner detector are external to the MC6173. The
band-pass filter passes roughly 300 Hz to 3000 Hz eliminating
nOise, 60 Hz and 120 Hz pickup, and harmonics of 1800 Hz.
The output of this filter IS fed to the equalIZer which adjusts
phase versus amplitude such that a constant amplitude IS
maintained regardless of phase and IS fed Into the carner
detect Circuit. The AGC amplifier proVides a constant level
Signal regardless of the Input level from the equalIZer The
output of the AGC amplifier drives two baSIC sections of
external circuitry, I.e., the AID converter, and 1200 Hz
envelope filter
The AID converter samples each 1200 Hz cycle or dlblt 12
times. After each sample, digital data IS clocked serially to
the MC6173 receiver data Input (ROil. The MC6173
generates the sampling clock for AD Strobe (ADS I and the
serial clock (ADCI from the 1.8432 MHz Internal oscillator.
The 1200 Hz envelope filter recovers the 1200 Hz component of the equalizer output during fast training and
generates a 1200 Hz square wave. This square wave IS connected to the envelope (Envl input and IS used for Internal
timing.
The carner detect Circuit is used to Signal the fast carrier
(FCarl Input that a carrier IS present. Immediately after FCar
has received a negative tranSition, the Internal phase-lock
loop temporarily widens ItS band width so that it can qUickly
adjust the internal timing of the MC6173 with respect to the
1200 Hz Env Input (this IS called fast Sync or fast tralnlngl.
The timing adjustments are made so that each diblt can be
sampled at the most advantageous places.
The internal circuitry digests the diblt samples and produces the digital data (Rx Datal along with the receive data
clock (Rx Clkl. These two Signals are used to drive a serialto-parallel interface such as an MC6852 Synchronous Serial
Interface Adapter

DATA-CLAMP DELAY (DCD), Pin 3 - Data-clamp delay
enables the selection of one of four delays dUring which Rx
Data IS held to a logic-high condition. This delay IS measured
from the negative edge of FCar. The four options are available at one pin through the use of the Internal multipleXing In
the demodulator. Options 3 and 4 are available by demultiplexing the d,bit clock as demonstrated In Figure 5. The
available delay options are listed in Table 1, these times Will
be approximate due to their direct relationship to the Env
Input during the first 8.3 ms. Also, these times are further
dependent upon carrier offset. The delays given in Table 1
assume no carner offset and that Env IS synchronous with
the Tx Clk Figure 4 is illustrative of the timing and sequencIng of this CirCUit.
A scheme for program~ the data-clamp delay IS Illustrated in Figure 5. The DCD input may either be a constant high or low level which will produce options 1 and 2. If
the Input" A" IS exclusive ORed with the dlblt clock options 3
and 4 are produced at the same Input pin.
ENVELOPE (Env), Pin 10 - The envelope input comes
from the 1200 Hz envelope detection cirCUitry. Envelope
detection will normally consist of a 1200 Hz filter and a
voltage comparator to generate an approximate limited
square wave This is normally derived from a constant mark
Signal sent by the modulator for Sync acquIsition purposes.
Each positive edge that is Input to Env will reset both baud
timing and the dibit clock to a logic "0". The optimum timing
of the positive transition at the Env Input will be tED prior to
the falling edge of the dibit clock. Timing is illustrated in
Figure 6.
Env Will be effective in the training of baud timing and dibit
clock only If FCar is in the active low state.
Minimum positive pulse Width at the Env is 2:2.17 I's.

PIN DESCRIPTION
FAST CARRIER (FCar), Pin 2 - A negative transitton on
this Input will force a period of approximately 8 3 ms of fast
training for both baud and carner timing.' Fast Sync or fast

'The postlve transition of the 1200 Hz Signal, present at the
Env input, proVides a dlvlde-by-20 counter with every other
clock This will cause approximately 8 3 ms of fast training
to the incoming Signal at the demodulator.

NEW-SYNC (NSync), Pin 11 - This Input port is normally
controlled by the business machine. If FC8r IS at an active
low, then an active low pulse in excess of 0.84 ms on the
NSync lead will put the demodulator into the fast-Sync

2-73

•

MC6173
FIGURE 4 -

if

•

DEMODULATOR SYNC TIMING DIAGRAM

1!f

.""~

0,"

•

~~ 1\ f\ 1\ f\J fV\ r\ f\ f\ 1\
V\J\rCTVVV va V\JV
i i
JJ.

Carner

I

-83ms

-10 Bauds

_ _ _ _ _ _....L.I..., ' (

'~-71~-----+_ _Data Clamp Delay
Input
6~s

Low
High
High .. DBC
Low .. DBC

TABLE 1 -

417ms
2083 ms
104 17 ms

DATA-CLAMP DELAY OPTIONS

Option

A

C

Dcr>

1

1

0

6 ~s

2
3

0

0
0

1

4.17 ms±35~s

1

DBC

DBC

20.83 ms±35,.s

4

0

DBC

~

104.17 ms±35 ~s

FIGURE 5 -

DATA-CLAMP DELAY DEMULTIPLEXER

Data-Clamp Delay

MC6173

L-:..:c..",,--,--, Demodulator

2-74

MC6173
FIGURE 6 -

I..

1

Line

Signal

Db

I It

ENVELOPE CLOCK TIMING DIAGRAM

-II

/\,Jf\,Jf\ Af\ ",f\
vr\Tr Vv Vv
1

1

1

1

I

I

Rectified
Line

Signal

Env

DBC

or fast-train mode Ithese terms are synonymousl.
Activation of N Sync allows large corrections to be made
to both baud and carrier timing similar to Initial activation of
the Fear lead. These corrections will be applied for approximately 8.3 ms. The receiver must complete the 8.3 ms period
of fast Sync before another NSync IS recognIZed.

There are nine 1 fLs positive pulses occurlng at a 460 kHz
rate. The first pulse, along with ADS, IS used to begin the
AI D conversion sequence. The next seven positive edges
strobe data serially from the AID converter to the
demodulator Input IROII enabling the demodulator to properly decode the AI D data.
This signal IS also used to clock 0 and 90 degree eye data
out of the demodulator. This IS described In the Eye Pattern
section. When TEn is low, ADC monitors check accumulator
output Isee TEnl.

CARRIER-SYNC (CarS), Pin 15 - When CarS IS taken to
an active low, baud timing Will be taken from the Env Input
In addition, the slow carner correction Will be doubled in the
2400 baud mode as defined by the data-rate select IDRSI
and phase-shift selectlPSSllnputs. !This IS not the same as
the fast training that IS Incorporated when FCar or NSync are
, active, which IS a changing of the bandwidth of the Internal
phase-lock loop [PLLl). This Widening of the PLL band Width
. Will allow a faster search and lock on the 1800 Hz carrier This
Carner-Sync mode Will remain active as long as CarS IS held
In the active state. The normal application of this option
would be to extend the training or Sync time under the mark
input data condition that exceeds B3 ms.
If Fear IS at a logic" 1" Inactive state, this Input is Ignored
by the demodulator.

AID STROBE (ADS), Pin 8 - A positive going, approxImately 11 P.s, pulse IS used as an enable signal for a sample
and hold CIrcuit prior to the AI D converter The negative
edge of this pulse IS used to start the conversion process
Pulse rate of this signal is 14.4 kHz which allows each diM to
be sampled 12 times. ISee Figure 7.) When TEn is low, ADS
monitors zero crossings Isee TEnl.

RECEIVER DATA INPUT (ROn, Pin 23 -- The digital
decode of the line signal magnitude, as sampled by the AID,
IS input to the demodulator at this port. The data format IS
scaled binary This sign bit occurs on the second AI D clock,
followed by six magnitude bits which begin with the mostsignificant bit as shown In Figure 8. The data IS strobed syn-

AID CLOCK (AOC), Pin 6 - This output Will allow, In a
serial format. the SIX AID data bits plus sign Information to
be synchronously clocked Into the demodulator ISee Figure

8.1

2-75

•

MC6173
FIGURE 7 -

I~

•

ANALOG TO DIGITAL SAMPLE SCHEME

~I

Dib,t

J
11

11

Line

Slgnal-L--------------~----·--------.H--------------~-------------\------------~u---------

data marks and spaces (Rx Datal. Receive clock is present at
the demodulator chip output at all times; IS not clamped to
an inactive state when the carrier detected is not presented
on Fear; nor is Rx Clk clamped by any other combination of
inputs to the demodulator.
Timing corrections to the receive clock, that are generated
internally, are made following IZ8i' going active. As described in FCar, if CarS IS held active the receive clock is continuously updated from dibit Sync.
The positive transition of the Receive Clock, which occurs
In the middle of the data bit, should be used to strobe data
from the demodulator, under normal operating conditions
When TPE scrambler! descrambler is being incorporated,
then the negative edge of the Rx Clk will occur in the center
of the data bit.
Receive Clock Will be 2400 bps or 1200 bps depending on
the logic input at the DRS Input. The Rx Clk edges described
above apply to either 2400 bps or 1200 bps data rates.
Under iJ5l: active, the Dibit relation to Rx Clk does not
change. See Figure 9 for relative timing of Rx Clk, DBC and
Rx Data.
Figure 10 depicts the requirements at the demodulator if
the data scrambler is being incorporated. The exclusive Nor
gating of TPE and Rx Clk would then maintain proper phasing of Rx Clk as It goes to the RS-232 driver. This circuit
would be required since the pOSitive edge of Receive Clock is
a Data Communications Standard.

chronously with the positive edges of the ADC.
A logic one in the sign bit slot will represent a positive
value. The magnitude of the six data bits Increases from
00000o to 111111 with all ones always representing the mostpositive value as illustrated below:
Sign

1
1
0
0

MSB

1
0
1
0

Value

LSB

1
0
1
0

1
0
1
0

1
0
1
0

1
0
1
0

1
0
1
0

+63
0
-0
-63

RECEIVE DATA OUTPUT (Rx Data), Pin 9 - This pin IS
the demodulator output for mark and space serial data. Data
is synchronous with the receiver clock output with the
positive gOing edge of the receiver clock occurring In the
center of the data bit. A mark IS represented by a logic high
("1"1 level except for the conditions described under PSS
andTPE.
The Rx Data output is inhibited in a logic-high level when
Fear is in the inactive high state. The delay from the positive
edge of IZ8i' to the inhibiting of data is 2 /Ls.
RECEIVE CLOCK (Rx Clk), Pin 20 - The receive clock
output provides the 2400 Hz ± 0.005% timing signal to the
business machine for sampling the demodulated received

2-76

MC6173
FIGURE 8 - ANALOG-TO-DIGITAL TIMING DIAGRAM

I...

-I

twlADSI

ADS~~---------+r----~I_-___
-_-~l~
I
I
I
I
I
I
ADC

i

I

I
I
I

I
I
I

_________________________

4

3

LSB

vmzvm

ADS

~---tcyc---+l
r---~

ADC

50%

RDI

DATA RATE SELECT (DRS), Pin 24 levels are valid for either phase-shift select·
Logic high equals 2400 bps,
Logic low equals 1200 bps

The phase shifts shown are the difference In phase between
the signal at the end of one dib,t period and the new signal at
the beginning of the next dib,t
If the logic level inputs to PSS are EXORed with DBC
(dlbit clockl or DBC, then the test-pattern enable option may
be selected and produce the compliment of normal data at
Rx Data as explained In the TPE description. (See Figure 11.1

The following

PHASE-SHIFT SELECT (PSS), Pin 17 - Option A
(CCITT) or optIOn B (U.S. I phase shift can be selected for
2400 bps operation. The input data format and phase shift
relationship for these two options are as follows:

Data
()()

01
11
10

PSS=o

PSS=l

Option A
(Degreesl

Option B
(Degreesl

0
+90
+ 180
+270

+45
+ 135
+225
+315

TEST-PATTERN ENABLE (TPE), Pin 18 - Incorporated In
the demodulator IS the 511-blt test pattern shift register that
is in accord with CCITT speciflcallon V52. ThiS IS the pattern
that IS generated by feedback from the 5th and 9th stages of
a 9-blt shift register.
When the TPE Input IS allowed to be pulled up Internally,
there is normal data flow through the receiver. When the
i l l Input is pulled low, the incoming data IS passed through
this self-synchronous decoder which will produce the Inverse
of the 511-bit CCITT V52 pattern.
i l l works in coordination with PSS If PSS IS directly
pulled high or low to represent option A or option B, then
the presence of the 51 l-test pattern at the (ROil Input and
TPE active will result in logic "1" condition at Rx Data output. If the DBC opllon IS being utilized at the PSS input and
TPE is active while the 511-bit test pattern is being received,
the receiver data output will equal a logic "0". These options
(Figure 111 are summarized in Table 2.

For 1200 bps operation, option A (CCITTI or option B (U S.I
phase shift can be selected as follows·
PSS=O

PSS=l

Data

Option A
(Degrees)

Option B
(Degrees)

0
1

+90
+270

+45
+225

2-77

MC6173

•

If the TJ51: input is in the active state, it is Important to note
that the Rx elk phase changes. The necessary circuit to
regain proper phase is shown In Figure 10.
A scheme for programming the phase-shift select is illustrated in Figure 11. The PSS input may either be a constant
high or low level which will produce options 1 and 2. If the input" A" is exclusive ORed with the diM clock, options 3 and
4 are produced at the same input pin.

This assumes the modulator is sending the 511-bit test
pattern with Rx Data being either a constant mark !logic "1"1
or space !logic "0"1. If a logic "0" is received in options 1 or 2
or a logic" 1" is received in options 3 or 4, then a transmission error has occurred. The number of errors-per-unit time
is a measure of the transmission line quality.
A feature of the above type of pattern detector IS that it
will be self-synchronizing. It should be pointed out that there
will be at least two error counts each time an error is
detected.
FIGURE 9 -

CLOCK TIMING DIAGRAM

2400 BPS A or B OPTION

1200 BPS A or B OPTION
Rx Clk

Ax Clk

Ax Data

Ax Data

TPE=1

TPE= I

Ax Data

Rx Data

TPE=O

TPE=O

l'--_--'

DiM Clock

TPE=O
lorTPE=1 '

Dlblt Clock

SETUP AND HOLD TIME

AxClk

Note: Timmg measurements are referenced to and from a low voltage
of 0.8 volts and a high voltage of

Ax Data

2.0 volts, unless otherwIse noted.

FIGURE 10 - DEMODULATOR DATA SCRAMBLER RECEIVE
CLOCK PHASE CORRECTION REQUIREMENTS
Ax Clk From Demodulator ~----.

""

RXClk~

Rx Data

L

-.~~

Ax Clk

AXData~

2-78

Ax Clk

MC6173
FIGURE 11 -

PHASE-SHIFT SELECT DEMULTIPLEXER
FOR TEST PATIERN ENABLE

•

MC6173
L-'::":"--'.'-:"';';"...-J

TABLE 2 - TEST PATIERN ENABLE OPTIONS

Option TPE A

C

1

0

1

0
0

Phase
Option PSS
A

Output State

0

Rx Data Output - 1
Rx Data Output - 1

2

0

0

B

1

3

0

1 DBC

A

DBC

Rx Data Output - 0

4

0

o DBC

B

DBC

Rx Data Output - 0

CLOCK (Clk), Pin 14 -

TEST ENABLE (TEn), Pin 16; 0° Eye, Pin 5; 90° Eye, Pin 4;
0° Car, Pin 7; CCor, Pin 19 - These pins allow the monitoring of ten internal points within the demodulator. A low level
on TEn is normally associated with testing of the
demodulator such as In a production test environment or incoming testing. Activation of TEn affects internal timing.
TABLE 3 Output

TEn

ADS
IPIn 81

H
L

A 1.8432 MHz signal input

Pin
Pin
Pin
Pin

5

o Degree

4
7
19

a

Eye
go Degree Eye
Degree Carner
Carner Correction

These test outputs are explained In the test enable (TEN)
deSCriptIOn below

Function
See DeSCription Under ADS IP,n 8)
Monitors Zero Crossings

ADC
IP,n 61

H
L

See DeSCription Under ADC IP,n 61
Monitors Check Accumulator Output

H

Eye
IPIn 51

L

MaMors 0 Degree Eye 2s Complement
Information from 6 Tap Filter
Monitors Degree Eye 25 Complement
Informalion from 12 Tap Filter

go Degree

H

MOMors go Degree Eye 2s Complement Information from 12 Tap Filter

IPIn 71

H
L

Monitors 0 Degree Carner
Momtors Check Accumulator Compare Errors

CCor
(Pin 191

H
L

MOnitors Carner Correction Enable
Monitors Carner Correction Direction

Eye
IPIn 41

TEST-CLOCK (TClk), Pin 13 - This Input is used for production testing of the demodulator device. In normal operation this pin should be left open which will enable the Internal
pullup resistor.

INTERNAL MONITORS

o Degree

± 0 005% IS required at this port. The clock requirements are
the same as the modulator clock specificatIOns See Figure
12 for a suggested clock CirCUit
The receive clock IS generated by dividing down the 1 8432
MHz. Since receive clock accuracy must be at least
± 0 005%, the clock source must be of the same accuracy.

Demodulator

DOCar

a

OIBIT CLOCK (OBC), Pin 21 - ThiS output is a 1200 Hz
clock which is derived from incoming data envelope and proVides a dibit reference. ThiS signal is representative of "data
derived timing." When studYing the quality of the
demodulated signal, through the use of eye patterns, thiS
output is necessary for proper synchronIZation of the
oscilloscope.
TEST STROBE (TStr), Pin 22 - ThiS Input is used to
facilitate testing of the demodulator during the manufacturing process. It should be left unconnected which will result In

2-79

MC6173
FIGURE 12 - OSCILLATOR CONFIGURATION

The Motorola 2400 bps modulator contains a CCITT
511-bit test-pattern generator. It does not, however, incorporate the 511 data randomizer or scrambler. To scramble
data using the MC6172 modulator, the circuit in Figure 10
must precede the Tx Data input of the modulator. Tx Data is
added to the scrambler output pattern; then, the data is
delayed by a full data bit before being transmitted by the
modem. This assures a proper transmit-datal transmit-clock
phase relationship. If the data scrambler is to be an optional
feature, then the transmit-data multiplexer would also have
to be built. This is selected by the test-pattern enable signal
or any other signal that is found suitable.
The demodulator does contain a built-in data descrambler
which is enabled by the TPE input going active. The receive
phasing, with respect to data, changes when TPE goes active. The exclusive NOR gating of TPE and Rx Clk, as shown
in Figure 10 will maintain proper phase of Rx Clk. This circuit is required since the clocking of data on a positive edge
is a data communications standard.

To Clk Pin 14
10MD

•

15 PF

I

I

30PF

Ul = MCl4069
Yl = 1.8432± .005%

the internal pullup resistor causing the high level on this pin.
VSS Pin 1 = The most negative supply, typically ground.
VCC Pin 12 = The most positive supply, typically 5 volts.

-DATA SCRAMBLER
EYE PATTERN
The scrambling of data in the data communication environment is not done in an attempt to encrypt information in
the normal sense of the word. Rather, the purpose of the
scrambling of data is to guarantee that, with respect to the
modem carrier, there is always random data on the line with
little chance for a long string of "1 s" or "Os" to exist. This is
particularly important if an adaptive equalizer is being incorporated in the modem as the adaptive equalizer will require
reasonably evenly distributed data to optimize its statistical
response to the incoming signal. The normally used code is
the CCITT 511 sequence which is EXORed with data.

FIGURE 13 -

Tx Clk
(From RS-232

When performing an evaluation of an 2400 bps modem,
one common point of comparison is the quality of the eye
patterns produced by the demodulator. The eye pattern may
also be used as an indicator of the incoming signal with
respect to level and line perturbations. Eye patterns are for
test and evaluation only and are not used in the demodulation of the incoming signal. .
Timing information in the Motorola 2400 bps demodulator
is derived directly from the demodulated data signal. This IS
referred to as data derived timing. The advantage of data

MODULATOR cCln 511 DATA SCRAMBLER

>--....------------il-----------+------"j

Ul
U2
U3
U4
U5

MCI4006
MCl4070
MCl4069
MCI4011
MCl4013

Translatorl
Tx Data

(From

RS-232>-------~~-----'

Translatorl
TPE>-------------~--~~

10

Tx Data

Pin 9
Modulator

~------Data MultiPlexer------~

2-80

MC6173
derived time IS that It allows data to be sampled at optimum
times The demodulated signals, in differential phase-shift
keYing, take the form of "eye patterns" as shown in Figure
14 The demodulator, In optimizing ItS performance for
minimum error rates, strobes data at the pOint of maximum
eye opening The demodulator constantly examines the eye
opening to assure that the data sample IS being taken at
exactly the optimum point. As a result of constantly adJusting timing control, correct sampling IS maintained This
technique provides improvements In reception that are
significant, especially in a poor communications media environment.
The circuit in Figure 16 IS reqUired to observe the eye patterns. This circuit was built using Motorola CMOS devices.
The 0 and 90 degree eye data is strobed from pins 4 and 5,
respectively, into the shift register by the A/D clock The

A/ D strobe then latches the data sample Into the" D" type
storage devices. The output of the storage devices taken
across the scaled resistors will then represent the appropriate
value of the sample taken. To properly observe the actual
eye patterns, it is necessary to Sync on dlblt clock while
observing the a to 90 degree eye data. OverlaYing the two
patterns produces a two-level digital-eye pattern from which
the quality of the incoming signal may be Judged.
Figures 15 thru 17 show a tYPical receive/demodulator and
transmit/modulator circuit, respectively. The transmit filter
illustrated in Figure 17 limits the bandwidth of the signal to
those frequencies allowed on a telephone line. The receive
filter and equalizer in Figure 15 clean up and normalize the Incoming signal for the A/D network, 1200 Hz envelope detector, and 1800 Hz carrier detector.

FIGURE 14 - EYE PATTERN
~----Dlblt----~~

!-:...

I

I

J
I

Eye
Pattern

QOCarner

1800 Hz

9O°Carrier 1800 Hz

DBC 1200 Hz

J

L

J.--.J

I
I
I
I
I

J

I

I
I
I

I
I
I

I

I
I
I

I

I

I
I
I

I
I

I

Rx Clk 1200 Hz

I

~

I
I

I
I

I

I
I

I

Rx Clk 2400 Hz

- - - _ .. _ - - - .

---~.--

•

3:

o0)
~

~
R2

.......
Co)

R3

10 kO

158 kO

TP6

f Ca;r,crDe1eC1J

[~I

R40'

.12

Equail2er Strap-In

·5V

.12

10k

»>-______________---'

E2
,.--_ _--«(u
_ m __ El
,12

EJ
vol

7

co

•

I

I\)

•

01)
I\)

~-I

cia

-+12~-12

I

R29

R30

10 k

10 k

- 12

TP9

NOTES

:t 1 dbm

CI9
20 pF

SpeCifies ± 1% Resistor
IS recommended at all chips
capacitors In microfarads unless noted otherwise

U9, Ull
UIO
UI2

MLM4741

U13, 14, 18, 19

MLM311
MC14007
MC1408

UI5
UI6
UI7
R34

R28
10 k

U21.37
01-D5

10k

FIGURE 15 - 2400 BPS DPSK DEMODULATOR SYSTEM

NE571N
LF398N

MC14559
MC741S
IN914

Plnl

SAR 116 Plnl
Gp-Amp (8 Pm)

i:

Eye Pattern Generator (Optional)

(')
0')

AID Strobe

AID

U33

U33

U33

~4
AID

10

10 k
II

U33

12

U33

G 4R -

+5V

U33

~6

......

c~

100 pF

9

Co)

U34

15

3

2

14

TP12

90"

+5V

~

D U35 0 I

2
8

U36

0

cD

9

r---G-29"'

3 C
S

+I,V I 8432 MHz
114

U34

~4

Clk

A

Rx Clk 20

23 RDI
6 ADC

C

D

N
I
CO
Co)

C Cor ~

24 DRS

~I

DI

01 7

DO

00 2

TPII

ro
cD
cc

13 D3

5 4
lOI
,DC

3 10
04
U27

9

cD

cD

~

U27

7

00 2

DO

ReSIstors ( ± 1 %}

+5V

R50 ~ R58 ~ 4.84
R51 ~ R59~ 9.53
R52~ R60~ 19.1
R53~ R61 ~37 4
R54~ R62~ 75 k

21

12 111 2
04
15 01
D
U27
C

-=

'"cc "a:

R

+5 V
13
R 6

cc

14
':"

R55~R63~150

II

U20
MC6173

R56~R84~301

R57~ R65~604

TPE DCD
18 3
~
cc

Q

13 03
12

D.-

S-

~
~

L-

m

0

cD
a:

'"
cc

;;

N

'"cc

cc

9

GND, Pin 16~ + 5 V
8~ GND, Pin 16~ + 5 V
8~ GND, Pin 1 ~ +5 V
7~GND, Pin 14~ +5 V
Pln7~GND, Pin 14~ +5V

Pin
Pin
Pin
Pin

5

-

OI
HDc

1

4

3 10
04
U28

R 6

-=

~

12

7

,...--2
~

00 2

8~

03P

13 D3

02 ~
01 7

DO

ro

'"a:

~~

53 2i......

00 2

DO
R

R
I
Pin)
Pin)
Pin)
Pin)
Pin)

k
k
k
TP13

9
r---Li"31

116
116
116
114
114

k
k
k
k

0"

=0

MCI4015
MCI4175
MC14049
MC14013
MCI4073

Eye Out

03pL-

12

~
~

cD
cD

:Ii
cc

9
r--LJ30

I

II

-

~ :s---J
~

cD

cc

R

+5V

p.

N

I

90" Eye 4
5
0° Eye

17 PSS

G

~

Rx Clk
Rx Data

Rx Data 9
DBC 21

8 ADS
2FCar
10 Env

~

~

cc

Q2F---

12 D2

-=

cc

53~

13 D3

6
12

...a.

I
+5VJ 2/
13 12 1112r
04
15 DOl
U28
C

+5V

R 14

-=

II

FIGURE 16 - 2400 BPS DPSK DEMODULATOR SYSTEM

II

2,
a:

cD

'"cc

Eye Out

•

:r::

o

SCRAMBLER PARTS
U22
MC14006
U23
MCl4070
U24
MCl4069
U25
MCl4011
U26
MCl4013

Tx
Clk

en

....,

W

NOTES'
1 All ReSistors ± 1%
All Capacitors ± 5%
2 BypaSSing of power IS recommended at all chips
T1
IS a 600 600 0 telephone transformer
3

+Vref
125VI

Tx
Data
Scramble
Select
ISSI

Il--+ 5 V
21
U2
. MC1403

!

F

G
S2

II

+5V

-"
()

~lsi

N
I

00
01::00

(/J

oa.

+5V

-=

"

:;-'-a.
-"

+5V
12

~ CTS2
16
15
6
14
7
8

CTS1
DRS
TPE
An Bk
RTS
Tx Mk

~

17 ILSBllO A6
VEE

:;
"0

>6

+

OTPI
14 V p _p Full Scalel

C5
20pF

0

;:2
N

r--

L-...J

TP3
TP4

Data Clk

-=

112

22 IMSBI 51A 1
+ Vref
21
6
20
7
Dut l4
19
8
U3
18
9 MCl406

pss

:2

-=

111

R1
+Vref
124k
R12
R2
248k
2k

4 CTS
5-DRTS

§

-12

-=

:2

TP5
10M

13 110

R13
Y1

o

1 8432 MHz

1.8432 MHz

15 PF

J

R4
261 k

-=

C7 -L±O 005o/l C 6

J

Rl0

Sl
()--oo(

Ext
Clk

30 PF

'ilt:

Cl

Low-P~ss

I

2

100 PF l '
'::"

+ 12 dBm
to -3.2 dBm
FIGURE 17 - 2400 BPS DPSK MODULATOR SYSTEM

3

@

MC6860

MOTOROLA

MOS

0-600 bps DIGITAL MODEM
The MC6860 is a MOS subsystem designed to be integrated into a
wide range of equipment utilizing serial data communications.
The modem provides the necessary modulation, demodulation and
supervisory control functions to implement a serial data communications link, over a voice grade channel, utilizing frequency shift keying
(FSKI at bit rates up to 600 bps. The MC6860 can be Implemented into a
wide range of data handling systems, mcluding stand alone modems,
data storage devices, remote data communication terminals and 1/0 interfaces for mmicomputers.
N-channel Silicon-gate technology permits the MC6860 to operate usmg a single-voltage supply and be fully TTL compatible.
The modem is compatible with the M6800 microcomputer family, interfacing directly with the Asynchronous Communications Interface
Adapter to provide low-speed data communications capability.
•
•
•
•
•
•
•
•

IN-CHANNEL, SILICON-GATEI

0-600 bps
DIGITAL MODEM

L SUFFIX
CERAMIC PACKAGE
CASE 623

Originate and Answer Mode
Crystal or External Reference Control
Modem Self Test
Terminal Interfaces TTL-Compatible
Full-Duplex or Half-Duplex Operation
Automatic Answer and Disconnect
Compatible Functions for 100 Senes Data Sets
Compatible Functions for 1001 AI B Data Couplers

P SUFFIX
PLASTIC PACKAGE
CASE 700

FIGURE 1 - TYPICAL MC6860 SYSTEM CONFIGURATION
Telephone
Network
Control
Signals

Control

-,J

t
Data
Coupler

PIN ASSIGNMENT

I

Duplexer

Receive
Data

MCsaeo

Transmit
Data

ffi
ESD

Thneshold
Detect

I

I
Receive
Carrier

I

L

Receive

Filter

Threshold
Detector

Limiter

2-85

r~

SH

ELS

i3TR

ESS

RI

TO

I

Rx Dala

Rx Brk
An Ph

Transmit Carrier
Asynchronous
Communications
Interface
Adapter

VSS
Tx Data

Tx Brk
Brk R
Tx Car

FO
VCC

TST
Rx Car

ST
Mode
Rx Rale
Xlal

•

Me6S60
MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature Range

Symbol

Value

Vee
V,n
TA

-0.3 to + 7.0
0.3 to + 7.0
o to 70

Unit
V
V
'e

Tstg

-55to +150

'e

Symbol

Value

Unit

65

'e/w

Storage Temperature Range

•

THERMAL CHARACTERISTICS
Characteristics
Thermal Resistance
Ceramic

9JA

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautIons be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit.
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic
voltage level (e.g" either VSS or Vee!.

120

Plastic

POWER CONSIDERATIONS
The average chip-Junction temperature, T J, In
TJ=TA+(PO o9JAJ

'c can

be obtained from:
(1)

Where:
TA-Ambient TElmperature, 'c
9JA- Package Thermal Aesistance, Junctlon-to-Amblent, 'C/W
PO'" PINT + PPOAT
PINT"' iCC x V CC, Watts - Chip Internal Power
PPORT'" Port Power Oissipation, Watts - User Determined
For most appJications PPOATJ (Peak %1
7.0
4.7
3.5
2.6

Originate Mode
t/>J (Peak %1
3.7
2.5
1.8
1.4

Ring Indicator (Ril
The modem function will recognize the receipt of a call
from the CBT data coupler if at least 20 cycles of the
20-47 Hz ringing sin gal (low level ~ 50% of the duty cycle)
are present. The CBS data coupler AI signal must be levelconverted to TTL according to the EIA RS-232 specification
before interfacing it with the modem function. The receipt of
a call from the CBS data coupler is recognized if the Ai signal
is present for at least 51 ms. ThiS mput is held high except
during ringing. An Ai Signal automatically places the modem
function in the Answer Mode.

ORIGINATE MODE
Upon receipt of a Switch Hook (SHI command the
modem function is placed in the Originate Mode. If the Data
Terminal Ready input is enabled (lowl the modem will provide a logic high output at Answer Phone. The modem is
now ready to receive the 2225-Hz signal from the remote
answering modem. It will continue to look for this signal until
17 s after SH has been released. Disconnect occurs if the
handshaking routine is not established.
Upon receiving 2225± 100 Hz for 150 ms at an acceptable
amplitude, the receive Data output is unclamped from a
Mark condition and data reception can be accomplished.
450 ms after receiving a 2225-Hz signal, a 1270-Hz signal is
transmitted to the remote modem. 750 ms after receiving the
2225-Hz signal, the Clear-to-Send output is taken low and
data can now be transmitted as well as received. Refer to
Figure 6.

Switch Hook (SH)
SH interfaces directly with the CBT data coupler and via
the !LA RS-232 level conversion for the CBS data coupler.
An SH signal automatically places the modem function in the
Or!2!.nate Mode.
SH is low during origination of a call. The modem will
automatically hang up 17 s after releasing SH if the handshaking routine has not been accomplished.
Threshold Detect (TO)
This input is derived from an external threshold detector. If
the signal level is sufficient, the TO input must be low for
20 "s at least once every 32 ms to maintain normal operation. An insufficient signal level indicates the absence of the
Receive Carrier; an absence for less than 32 ms will not
cause channel establishment to be lost; however, data during this interval will be invalid.
If the signal is present and the level is acceptable at all
times, then the threshold input can be low permanently.
Loss of threshold for 51 ms or longer results in a loss of
Clear-to-Send. The Transmit Carrier of the originate modem
is clamped off and a constant Mark is transmitted from the
answer modem.

INITIATE DISCONNECT
In order to command the remote modem to automatically
hang up, a disconnect Signal is sent by the local modem.
This is accomplished by pulsing the normally low Data Terminal Ready into a high state for greater than 34 ms. The
local modem then sends a 3 s continuous space and hangs
up provided the Enable Space Disconnect is low. If the
remote modem hangs up before 3 s, loss of Threshold
Detect will cause loss of Clear-to-Send, which marks the line
in Answer Mode and turns the carrier off in the Originate
Mode.

2-89

•

MC6860

TIMING DIAGRAMS
FIGURE 4 - ANSWER MODE
Call Received

---I

•

r-

ms

51

Ring Indicator

~--------------------------------

Ring Indicator

CBT"lJl..fuulJr-------------------------------I

Mode {~~:::rte _
Data Terminal

Answer (Low)
On CLow)

I

r---------------------------------

Ready

I

Answer Phone

Transmit Carrier

I
------{\I
I

Receive Carrier - - - - - - - - - - - - -_ _ _ _ _-{

Threshold Detect --'(;,;H-",9::.h;;.I----------------h--,--,--,---,r-+-r-,-+,r-,--,--,---,r-Clear-ta-Send _0_1_1-,-(H--=i9c.h'-I_ _ _ _ _ _ _ _ _ _ _ _ _
-- 15
milliseconds.

Data

OrigInate

Mark
Space
Mark
Space

Originate
Answer
Answer

Test Clock nST)

Transmit
Frequency

1270
1070
2225
2025

Hz
Hz
Hz
Hz

Tolerance*
-0.15 Hz
0.90 Hz
-0.31 Hz
-0.71 Hz

'The reference frequency tolerance IS not Included.

A test signal input is provided to decrease the test time of
the chip. In normal operation this Input must be strapped
low.

The proper output frequency is transmitted within 3.0 "S
following a data bit change with no more than 2.0 "s phase
discontinuity. The typical output level is 0.35 V IRMS) into
100 k ohm load impedance.
The second harmOniC is typically 32 dB below the fundamental Isee Figure 10),

Self Test (ST)
When a low voltage level is placed on this input, the
demodulator is switched to the modulator frequency and
demodulates the transmitted FS K Signal. Channel
establishement, which occurred during the initial handshake,
is not lost during self test. The Mode Control ouput changes
state during Self Test, permitting the receive filters to pass
the local Transmit Carrier.
ST
SH
H
-U-'
H
H
L
"'"1...J'
L
H
'Note maximum SH low time

Mode

POWER-ON RESET
Power-on reset is provided on-chip to insure that when
power is first applied the Answer Phone output is in the low
linactive) state. This holds the modem in the inactive or idle
mode until a SH or AI signal has been applied. Once power
has been applied, a momentary loss of power at a later time
may not be of sufficient time to guarantee a chip reset
through the power-on reset circuit.
To insure initial power-on reset action, the external
parasitic capacitance on AT and SH should be <30 pF.
Capacitance values> 30 pF may require the use of an external pullup resistor to V CC on these inputs in addition to the
pullup devices already provided on chip.

RI
Mode
H
H
L
L
H
L
L
H
In Table 1.

Answer Phone (An Ph)
Upon receipt of Ring Indicator or Switch Hook signal and
Data Terminal Ready, the Answer Phone output goes high
[(SH+ AI).DTR1. ThiS signal drives the base of a transistor
which activates the Off Hook, and Data Transmission control
lines in the data coupler. Upon call completion, the Answer
Phone signal returns to a low level.
Mode
The Mode output indicates the Answer Ilow) or Originate
Ihigh) status of the modem. This output changes state when
a Self Test command is applied.
Clear-To-Send (CTS)
A low on the CTS output indicates the Transmit Data input has been unclamped from a steady Mark, thus allowing
data transmission.

>

6

;;
e"'

.

~

0.

E

'"

FIGURE 9 - TRANSMIT CARRIER SINE WAVE

Receive Data (Rx Data)
The Receive Data output is the data resulting from
demodulating the Receive Carner. A Mark is a high level.
Receive Break (Rx Brk)
Upon receipt of a continuous 150 ms space, the modem
automatically clamps the Receive Break output high. This
output is also clamped high until Clear-to-Send is established.
Digital Carrier IFO)
A test signal output is provided to decrease the chip test
time. The Signal is a square wave at the transmit frequency.
Transmit Carrier (Tx Car)
The Transmit Carrier is a digitally-synthesized sine wave
IFlgure 9) derived from the 1.0 MHz crystal reference. The
frequency characteristics are as follows:

Harmonics
Frequency

FIGURE 10 - TRANSMIT CARRIER
FREQUENCY SPECTRUM

2-93

MC6860
TABLE 1 - ASYNCHRONOUS INPUT PULSE WIOTH AND OUTPUT DELAY VARIATIONS
(Time delays specified do not include the 1-MHz reference toleranC8.~

•

Due to the asynchronous nature of the input signals with respect to the circuit internal clock, a delay variation or input
pulse width requirement will exist. Time delay A is the maximum time for which no response will occur. Time delay B is the minimum time required to guarantee an input response. Input, signal widths in the cross-hatched region (i.e., greater than A but less
than BI mayor may not be recognized as valid.
For output delays, time A is the minimum delay before an output will respond. Time B is the maximum delay for an output
to respond. Output signal response mayor may not occur in the cross-hatched region (i.e., greater than A but less than B).

INPUT PULSES

OUTPUT DELAYS

rJ

!m,,;;i

---.J

i5TR

S(:':~:~~sconnect) I

tA'32ms~

l'"

Tx Car-

ESD::=

-B==51ms

Low

A"

6ms

B "" 34 ms

~l

i5'i'R
SH

~

(Initiate Space
Disconnect)

~
6ms

--jA"

f--- ~
B

f-

34 ms

I

~:~'m.-"~

An Ph

I

~

B

TO
(Loss of

::=

5T'A

----1

I--

Threshold)

(Inltlate~

~
A ' 32 ms----l

:
I

r-- --

~~;coennect)

I,

-J

-lWf@I""

3056 ms

I

I

~

~'65m'~

Rx Brk

-B '" 51 m s - - - j

-B'=185ms

Answer Mode

15i'R

(In",a,e

~dueto Rx Car (1270 Hz)

TO

---.J

SP;;;-~

16msL-

A '

~_

Disconnect)

,

~

B

0

34 ms

I

I

,-J

CTS

or Rx Brk

i5T'R

Tx""Brk

~

J

~

-t'6ms~
8'" 34 ms

C

Wf@II

A ' 432 m, ---1

B' 451 m s - - - l

~
I

An Ph

Ai or SH '"

Low

W/W41

l"m.~

B '" 34 ms

--J
(continued)

• Digital Representation

2-94

MC6860

TABLE 1 - OUTPUT DELAY VARIATIONS Icontinuedl

Tx 8r~~___________________________

Rx

Dat~

I

I
Tx Car·

Rx

~k/SP

t

I

E'SS= High
m=Hlgh

B,,"34ms~

LB"7034ms

Da~ ~...:S.::.p.::.ac...:e_______________

!
An Ph

ESS -

Low
E'i:'S=-Hlgh

f-.-

To

--.-J

I

(Loss of
Th,eShO;".'.::.d;".)__-:-_ _ _ _ _ _ _ _--'~~~""'"~

~
I

"

f-. -..:., m. ~::1

An Ph

@@@Space

A, 16 ms--j

CTS 0' R x B,k

A " 282 ms ----4

L-B

ms

= 301

Space

~~----

------l

I---

---l

I
~B'51ms~
A ' 32 ms

Originate Mode

RXD~

I

AnPh

ffi"
ELs

HIgh

t~
A

Todue to Rx Car (2225 Hz)

Space

>--'-'------

~

1496 m s - - - j l

I

Low

B - 1520

ms--l

Originate Mode

R)(O~

I

Space

i'D

~-------

~ ) TO due to

Tx Car

Ax Brk

(1270 Hz)

I~

I--

A " 432 ms

I-----TABLE 2 - TRANSMIT BREAK AND DISCONNECT DELAYS

Tx Brk (Space Duration)
Space Disconnect (Space Duratlonl
IDTR -- HIgh,
and
Lowl

ESD

m"

Loss of Carner Disconnect
(Measured from positive edge of

tlve edge of An Ph, with

m

Min

Max

Unit

232

235

ms

3010

3023

ms

16965

17034

ms

16916

17101

ms

to nega·

Ri. SH, and -rn - High)

Overrrde Disconnect
(Measured from positive edge of AT or SH to
negative edge of An Ph, with
= Hlghl

ro

2-95

----j

I

B ' 451 mS--------1

• Digital Rel-lresentatlon

Function DeSCription

A)( Car (2225 Hz)

MC6B60

FIGURE 11 - FLOW DIAGRAM

•

No

No
Low
Ves

ST

No

No

High

No

5"i"'R
Low
Ves

Answer
Mode

No

Ves
An Ph Goes High
Remote Modem Sends
2225 Hz

No

Ves

No

2-96

Me6S60

FIGURE 11 - FLOW DIAGRAM (CONTINUED)

Answer
Mode

No

~~---------,
No

Receive
2225 Hz In
Band

No

Receive
2225 Hz

Band

Ye,
eeelye
1270 Hz

Ye,

No

>150ms

>150ms

Loss

of R x Car >_Y-,-e=-,__________~
"·51 ms

No

Note 1

Loss
Ot Ax Car
>Slms
No
No
No

CTS
Low

No

Note 1

02335
Delay

Note 2

Transmit Break, Initiate Space Disconnect,

and Receive Space are mutually exclusive events

Due to loss of Rx Car, the modem will clamp
Tx Data to a Mark In the Answer Mode and will
turn off Tx Car In the Originate Mode If Ax
Car IS detected before completion of Tx Srk or
Initiate Space Disconnect, normal operation of
Tx Srk or Initiate Space Disconnect Will con
llnue until completion of thel' respective time

delays

2-97

•

MC6860
FIGURE 11 - FLOW DIAGRAM {CONCLUDED)

•

Ve.

Note 2

Ves
Delay

No

0.145
Delay

No

3.0 s
Delay

0.3 s
Delay

Ve.

No

ESS
Low
No

1.5 s
Delay

Ve.

No

ITS
Low
No

17 •
Delay

Ve.

No

2-98

No

®

MCl4400
MCl4401
MCl4402
MCl4403
MCl440S

MOTOROLA

CODEC-FILTER PCM-MONO-CIRCUIT
The MCl4400, MCl4401 , MCl4402, MCl4403, and MCl4405 are all per
channel codec-filter PCM mono-circuits. These devices perform the voice
digitizinq and recovery, as well as the band limiting and signal restoration
necessa··y in PCM systems. The MCl4400 and MCl4403 are general purpose
devices that are offered In a 16-pin package. They are designed to operate in
both synchronous and asynchronous applications and contain an on-chip
precision voltage reference. The MCl4401 is the same device, but offered in
an 18-pin package. In addition, it offers the user the capability of selecting
from three peak overload voltages 12.5, 3.15 and 3.78 V!. The MCl4405 is a
synchronous device in a 16-pin package intended for instrument use. The
MCl4402 is the full feature device which presents all of the options available
on the chip. This device is packaged in a 22-pin DIP and 28-pin chip carrier
package, and contains all the features of the MCl4400 and MCl4401 plus
several more. Most of these features can be made available in a lower pin
count package tailored to a specific user's application. Contact the factory for
further details.
The devices were designed to be upward compatible with the
MCl4404/06/07 codecs and other industry standard codecs. They also maintain compatibility with Motorola's family of TSACs IMCl44161
MCl4417/MCl4418) as well as the MC3419 SLiC.
The PCM codec-filter mono-circuits utilize CMOS due to its reliable lowpower performance and proven capability for complex analogI digital LS I
functions.
MCl4400
• 16-Pin Package
• On-Chip Precision Voltage Reference 13.15 V)
• Power Dissipation - 45 mW at 2.048 MHz at 10 V
0.1 mW Powered Down at 10 V
• Compatibility with Various Supply Configurations: ± 5, ± 6, + 10,
+ 12 Volts 15%)
• Pin Selectable TTL and CMOS Digital Levels
• Automatic Prescale Divide of Any One of 5 Clock Frequencies
1128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or 2.56 MHzl to
Generate the Internal Sequencing Clock
• Pin Selection of 80th A-LAW/Mu-LAW Companding and D3/D4
or CCITT Digital Formats
• Output Drive Capability for 600 and 900 Ohm Loads of + 12 dBm
• Synchronous and Asynchronous Operation
• On-Chip Attendent Interrupt Conferencing
• Transmit Bandpass and Receive Low-Pass Filters on Chip
MCl4401 - All of the Above Plus:
• 18-Pin Package
• Selectable Peak Overload Voltages 12.5, 3.15 and 3.78 VOltsl
• Access to the "Minus" Input of the Tx Input Op Amp
MCl4402 - All of the Above Plus:
• 22-Pin Package
• Variable Data Clocks 164 kHz to 3.088 MHz)
• Access to Transmit Input Amplifier
• An External Precision Reference May Be Used
• External Gain Adjust for Complex SLiC Configurations
MCl4403
• 16-Pin Package
• Same Device as MCl4400 with Access to Transmit Input
Amplifier with Single Ended Receive Output
• MSI Tied Internally to TDE
MCl4405
• 16-Pin Package
• Same Device as MCl4403 with Common 64 kHz to 3.088 MHz Data Clocks

CMOS LSI
(LOW-POWER COMPLEMENTARY MOS)

CODEC-FILTER
PCM MONO-CIRCUIT

MCl4400/03/OS

L SUFFIX
CERAMIC PACKAGE
CASE 620

.1

MCl4401
L SUFFIX
CERAMIC PACKAGE
CASE 726

~-~~
1

CERAMIC PACKAGE
CASE 736

MCl4402
Z SUFFIX
28-PIN CHIP CARRIER
CASE 763

r"""'' '"

ORDERING INFORMATION
MC14XXXXX

L2

D3/D4 (PUB 43801)

L Ceramic Package

Z Leadless Ceramic Package

2-99
----~

.

-

.~~-----

•

MC14400, MC14401, MC14402, MC14403, MC14405
PCM MONO-CIRCUIT BLOCK DIAGRAM
Vref

ASI

•
Mu/AC)~--------------~------------------------------~--J

~
POI
MSI

MC14400/01/02/03f05
NOTE 9::: Controlled by VLS
* Ax _100 kG !Internal Resistor}

DEVICE DESCRIPTIONS
MCl4400 and MCl4401. The MCl4402 is Intended for bit
interleaved or word interleaved operation with data clock frequencies which are non standard or time varying. One of the
five standard frequencies (listed abovel is applied to the CCI
input and the data clock inputs can be any frequency between 64 kHz and 3.088 MHz. The V ref pin allows for use of
an external shared reference or selection of the internal
reference and RxG and + Tx provide maximum flexibility for
analog interface.

There are five distinct versions of the Motorola PCM
mono-circuit.

MCl4400
The MCl4400 PCM mono-circuit IS a PCM codec-filter intended for standard word interleaved synchronous or asynchronous applications. The TOC pin on this device is the input to both the TOC and CCI functions in the pin description.
Consequently, for MSI ~ 8 kHz, TOC can be one of five
discrete frequencies. These are 128 kHz (40 to 60% dutyl
1.536, 1.544, 2.048 or 2.56 MHz. (For other data clock frequencies see MCl4402 or MCl4405.1 The internal reference
is set for 3.15 volts peak full scale, and the full scale Input
level at Txl and output level at RxO is 6.3 volts peak-ta-peak.
This is the + 3 dBmO level of the PCM mona-circuit. All other
functions are described in the pin description.

MCl4403
The MCl4403 PCM mono-circuit is Intended for standard
word interleaved asynchronous or synchronous applications.
TOC can be one of five discrete frequencies. These are 128
kHz 140 to 60% dutyI1.536, 1.544,2.048 or 2.56 MHz. (For
other data clock frequencies see MCl4402 or MCl4405.1 The
internal reference is set of 3.15 volts peak full scale, and the
full scale input level at Txl and output level at RxO is6.3volts
peak-to-peak. This is the + 3 dBmO level of the PCM monocircuit. The + Tx and - Tx inputs provide maximum flexibility for analog interface. All other functions are described in
the pin description.

MCl4401
The MCl4401 PCM mono-circuit offers the same features
and IS for the same application as the MCl4400, but offers
two additional PinS and features. The reference select Input
allows the full scale level of the device to be set at 2.5 Vp,
3.15 Vp or 3.78 Vp. The - Tx pin allows for external transmit
gain adjust and simplifies interface to the MC3419 SLiC.
Otherwise, it is identical to MCl4400.

MCl4405
The MCl4405 PCM mono-circuit is intended for word
interleaved synchronous applications. The MCl4405 has all
the features of the MCl4403 but Internally connects TOC
and ROC (see pin description) to the OC pin. One of five
standard frequencies (listed above) should be applied to CCI
and the OC input can be any frequency between 64 kHz and
3.088 MHz.

MCl4402
The MCl4402 PCM mono-circuit is the full featured 22-pln
device. It is Intended for use in applications requinng maxImum fleXibility. The MCl4402 contains all the features of the

2-100

MC14400, MC14401, MC14402, MC14403, MC14405

VAG

VDD

VAG

VDD

RSI

VDD

Vref

RxO

RDD

RxD

RDD

VAG

17

RDD

VAG

+ Tx

RCE

RxO

RCE

RxO

16

RCE

RxO

13

RDC

Txl

RDC

RxO

15

RDC

RxG

4

-Tx

12

TDC

MulA

TOC

Txl

14

TOC

RxD

MulA

11

TDD

POi

TOD

-Tx

13

TOD

+ Tx

ro

10

TDE

VSS

TOE

MulA

12

TOE

Txl

9

VLS

VLS

MSI

VSS

8

8

MCl4403

9 MSI

MCl4400

ro

8

11

VSS

9

10

c:J_
 a:
VAG

RxO

RxO
RDC

NC

+Tx

NC

RxG

Txl

RxO

TOC

+ Tx
Txl

CCI

- Tx

NC

MulA

- Tx

NC

> >

Vi 0w
::;; .....

VDD
RDD
RCE

4

RDC
TOC
I

VLS

16

VDD

15

RDD

14

RCE

4

13

DC

12

CCI

•

CCI

- Tx

'.
6

PDI
VSS

(/) Ul U
Ul--'Z

RSI

TOD
TDE

PDI

10

MSI

VSS

11

VLS
MCl4402L

TOD

MulA

22
21

MulA

MCl4401

»

,.

11

TOD

10

TDE

8

VLS

MCl4405

MCl4402Z

MAXIMUM RATINGS IVoltage Referenced to VSS)
Rating
DC Supply Voltage
Voltage, Any Pin to VSS

Symbol

Value

Unit

VDD-VSS
V

-0.5 to 13

V

-0.5 to VDD+0.5

V

I

10

TA
T 5tg

-40 to +85

mAde
DC

-85 to +150

DC

DC Current Drain per Pin IExcluding VDD, VSS)
Operating Temperature Range
Storage Temperature Range

RECOMMENDED OPERATING CONDITIONS

a to 70 0 e

25°e

a to 70 0 e

Pins

Min

Typ

Max

Unit

DC Supply Voltage

VCC to VSS

6

10 to 12

13

V

Power DiSSipation
CMOS Mode 10 V
TTL Mode 10 V

VDD to VSS

-

45
75

70
110

mW

Parameter

Power Down DIssipatIOn 10 V

VDD to VSS
MS)

Frame Rate Transmit and Receive
Data Rate
MC14400, MCl4401, and MC14403
IMust Use One of These Frequencies)
±2%

TDC, RDC

Data Rate MC14402, MC14405
Full Scale Output and Input Levels MC14400, MC14403, MC14405
MC14401 and MC14402, Vref= VSS

RSI=VDD
RSI=VSS
RSI=VAG

2-101

RxO, Txl

-

01

10

mW

7.5

80

8.5

kHz

-

128
1536
1544
2048
2560

-

kHz

64
-

-

3088
-

kHz

-

Vp

-

3.15
3.78
3.15
250

-

-

MC14400, MC14401, MC14402, MC14403, MC14405
DIGITAL LEVELS (TA=O to 70·C)

TTL Mode
TOE, RCE, ROD,

•

POi,
POi,

Typ

Max

12

-

5.25

3.6

12

8.4

6.75

-

10

-

VLS+ 1.0

VLS+0.8

10

VLS+2.0

VLS+ 1.8

-

IOH

10

150

-

IOL

-

1.6

-

-

VDD toVSS

"0"

-

"1"

-

"0"

-

"1"

-

VOH=2.4 V
VOL =0.8 V

ROC, TOC, DC, CCI, MSI

ROC, TDC, DC, CCI, MSI

TOO Output Current
(TTL Model

Min

Symbol

Parameter
CMOS Mode
TOE, RCE, ROD,

Unit

V

V

".A

rna

ANALOG TRANSMISSION PERFORMANCE
(VDD=+5V ±5% VSS=-5V ±5% OdBmO=+6dBm@600Il,VLS=VAG=0, TA=Ot070·C, TOC=RDC; TOE = RCE=8
AID
DIA
E to E
Characteristic
Min
Min
Max
Max
Max
Min
-0.3
-0.3
-0.3
Absolute Gain (0 dBmO @ 1.02 kHzl
+0.3
+0.3
+0.3
Gain vs Level Tone (Relative to -10 dBmO, 1.02 kHz)
-0.4
-0.2
-0.2
+3 to -40 dBmO
+0.4
+0.2
+0.2
-40 to -50 dBmO
-0.8
-0.4
+0.4
-0.4
+0.8
+0.4
-1.6
-0.8
-55 dBmO
+1.6
-1.0
+1.0
+0.8
Gain vs Level - Pseudo Noise (A-Law Only, MCl44XXL1 Only)
(Relative to - 10 dBmO!
-0.45
-10 to -55 dBmO
+0.45
-60 dBmO
-0.90
+0.90
Total Distortion - 1.02 kHz Tone (C Messagel
o to -30 dBmO
35
36
35
-40 dBmO
29
29
30
-45 dBmO
24
24
25
Total Distortion with Noise (A-Law Only, MCl44XXL1 Onlyl
-3 dBmO
27.5
-6 to -27 dBmO
35
-34 dBmO
33.1
-40 dBmO
28.5
-55 dBmO
13.5
Idle Noise
18
18
13
(Mu Law, C Messagel
(A Law, Psophometric - MCl44XXL1 Only)
-68
-75
-68
Frequency Response (Relative to -10 dBmO, 1.02 kHz)
-23
-23
15to60Hz
0.15
300 to 3000 Hz
-0.30
+0.30
-0.15
+0.15
-0.15
+0.15
-1.6
-0.8
-0.8
0
0
0
3400 Hz
-14
-28
-14
4000 Hz
-32
4600 Hz
-60
-30
Inband Spurious (1.02 kHz@O dBmOI
-43
300 to 3400 Hz
-43
-43
-

kHz)
Unit
dB
dB

dB

dB

dB

-

Out-ol-Band Spurious (0 to 12 kHz in, @O dBmO)
o to 3400 Hz
3400 to 4600 Hz
4600 Hz to 12 kHz
Idle Noise Selective
@ 8 kHz with VAG= Txl Measure at RxO, 30 Hz Bandwidth
Group Delay Difference
o dBmO, TOC, RDC= 2.048 MHz
500 to 600 Hz
600 to 1000 Hz
1000 to 2600 Hz
2600 to 2800 Hz

-

-30
-28
-30

-

-30

-

-

-

-

-

-50

-

-

-

-

-

-

-

-

BO

-

-

60
140

-

-

BO

-

-

-

-

-

460

-

dBrnCo
dBmOp

dBmO

dBmO

dBmO

dBmO

".sec

Go to Return Crosstalk @O dBmO
Txl to TOO @ RxO
ROD to RxO @ TOO
Absolute Group Delay @ 1.02 kHz
TDC= RDC= 2.048 MHz

2-102

-65

-

-

-65

dBmO

-

-

I's

MC14400, MC14401, MC14402, MC14403, MC14405

-

ANALOG ELECTRICAL CHARACTERISTICS IVOO-ll0 12 V) ±5% 0 to 70·C)
Characteristic

Symbol

Min

Typ

- Tx, + Tx, ITxl for MCl4400)

lin

AC Input Impedance 11 kHz)

Txllfor MCl4400) to VAG

Zin

100

200

AC Input Impedance 11 kHz)

-Tx, +TxtoVAG

lin

1.5

-Tx, +Tx

VICR

RxO, RxO
Each
Output

Input Current

Input Common Mode Voltage Range VOO= 10.0 V
Output Voltage Range
RL=20ktoVAG
RL=600toVAG
RL=900toVAG
Output Current RxO, RxO

VOH- VOO-0.8
VOL =0.8

Power Supply Rejection Ratio
VOO= 12 V ±0.05 V peak@ 1 kHz

RxOtoVAG
RxOtoVAG

Shared External Reference

Vref to VAG

Vref Input Current

Unit
nA

5.0

-

MD

+1.5

-

+8.0

V

VORto
VAG

-4.0
-3.2
-3.9

+4.0
+3.2
+3.9

V

-

-5.0
+5.0

-

30
30

40
40

-

2.0

-

3.8

V

-

0.3

-

mA

PSRR

lin

VAG Output Current

Max

±0.01 ±30

kD

mA
dB

Source

IVAG

200

I'A

Sink

IVAG

8.0

rnA

MODE CONTROL LOGIC IVSS =0 V 0 to 70·C)

VOO
Vdc

Min

Typ

Max

Unit

VLS Voltage for TTL Mode

10
12

0
0

-

6.0
8.0

V

VLS Voltage for CMOS Mode

10
12

9.5
11.5

-

-

10
12
10
12
10
12

9.5
11.5
4.0
5.0

10
12
10
12
10
12

9.5
11.5
4.0
5.0

10
12

4.0
5.0

10
12

-

10
12

-

Characteristics

Mul A Select Voltage
Mu-Law Mode
Sign Magnitude Mode
A-Law Mode
3.78 V Mode

Reference Select Voltage

2.5 V Mode
3.15 V Mode
External Reference Mode

V ref Mode Voltage

Internal Reference Mode
Analog Test Mode Selection Frequency, MSI;" CCI
See Pin Descnption; Test Modes

2-103

-

-

-

-

-

-

-

-

6.0
7.0
0.5
0.5

-

-

-

-

-

128
128

V

-

V

V

6.0
7.0
0.5
0.5

V

-

V

-

V

0.5
0.5

-

kHz

•

MC14400, MC14401, MC14402, MC14403, MC144.05

SWITCHING CHARACTERISTICS IV'DO = 110 to 12 VI TOt
A= 0 70'C CL= 50 PF CMOS or TTL ModeI

•

Characteristic
Symbol
Output Rise Time
tTLH
Output Fall Time
TOO
tTHL
Input Rise Time
tTLH
Input Fall Time
DC, TOE, CCI, RCE, ROC, TOC, MSI
tTHL
Pulse Width
DC, TOE Low, CCI, RCE, ROC, TOC, MSI
tWH
Clock Pulse Frequency
DC,TOC,RDC
fCL
Clock Pulse Frequency IMSI- 8 kHzI
CCI
1
fCLl
This Pin Will Accept One of These 5 Discrete Clock Frequencies and Compensate
2
fCL2
to Produce Internal Sequencing.
3
fCL3
4
fCL4
5
fCL5
Propagation Delay Time
TTL
TOE to TOO Low Impedance
tpl
CMOS
TOE to TOO Low Impedance
tpl
TTL
TOE to TOO High Impedance
tp2
CMOS
TOE to TOO High Impedance
tp2
TTL
TDC' to TOO
tp3
CMOS
TDC' to TOO
tP3
TOE Rising Edge to TDC Falling Edge Setup Time
tsul
tsu2
RCE Rising Edge to ROC Failing Edge Setup Time
lsu3
ts 4
MSI Rising Edge to CCI Falling Edge Setup Time
tsu6
tsu7
ROD Valid to ROC Falling Edge Setup Time
tsu5
ROD Hold Time from ROC Falling Edge
th

Min

Typ

Max

Unit

-

30

80

ns

-

-

4

"s

100

-

-

ns
kHz

64

-

85
50

20
100
20
100
20
100
60
100

3088

128
1536
1544
2048
2560
130
100
50
20
120
80

180
160
75
40
180
160

-

-

-

-

-

-

40
60

-

-

kHz

ns

ns
ns
ns
ns
ns
ns
ns
ns

• For the sign bit, tP3 IS measured from TOE or TDC, whichever IS last.

PIN DESCRIPTION
DIGITAL
VLS selects CMOS or TTL compatibility for all digital I/0s.
VU:;=VOO; all liD is CMOS, IVOO to VSS swingl.
VLS
VAG), a 2.5 volt reference like the MCl403 is connected
from Vref to VAG. A single external reference may be shared
by tying together a number of V refS and V AGs from different
PCM monO-Circuits. In special applications, the reference
voltage may be between 2 and 4 volts. However, the gain
selection logiC associated with RSI must be considered to arrive at the deSired PCM monO-Circuit gain.
Internal Mode In the Internal reference mode
IVref= VSS), an internal reference supplies the reference
voltage for the PCM mono-circuIt.

A-Law
(CCITI)

Mu-Law
0000
1111
1111
0010

1010 1010
1101 0101
0101 0101
0010 1010

Step Select

~

a
Note' Startmg from sign magnitude, to change format.

To Mu-Law MSB IS unchanged ISlgnl
Invert remaining seven bits
If code IS 0000 0000, change to 0000
suppression)

RSI Reference Select Input (MCl4401 102 Only)
The RSI Input allows the selecliOn of three different
overload or full scale voltages independent of the Internal or
external reference mode. The selection of maximum signed
level IS made by connecting RSI to VDD, VAG or VSS. The
vanous modes of operation are summarized In the table
below The internal reference is deSigned to give Internal
gains equal to those obtained with an external 2.5 volt
reference.

0010 Ifor zero code

To A-Law MSB IS unchanged (slgnl
Invert odd numbered bits
Ignore zero code suppression

Mul A Select - This pin selects the companding law and
the data format at TDD and RDD
Mul A= VDD, Mu255 Companding D3 Data Format with
Zero Code Supress
Mul A= VAG, Mu255 Companding with Sign Magnitude
Data Format
Mul A= VSS, A-law Companding with CCITT Data Format Bit InverSions
PDI - The power down input disables the bias circUitry
and gates off all clock inputs. This puts the Txl, RxO, RxO,
and TDD outputs Into a high impedance state. The power
dissipation IS reduced to 0.1 mW when PDI= VLS or VSS.
The CIrcuit operates normally with PI5i = VDD or with a logiC
high as defined by connection at VLS. TDD will not come
out of high Impedance for two MSI cycles after PUi goes
high
DC - In the MCl4405, TDC and RDC are internally connected to this pin

RxO and RXO Receive Analog Outputs
These two complimentary outputs are generated from the
output of the receive filter. They are equal in magnitude and
out of phase. The maximum signal output of each is equal to
the maximum peak-to-peak signal described with the
reference. If a 2.5 V reference is used with RSI tied to VAG
and a + 3 dBmO sine wave is decoded, the RxO output will
be a 5 V peak-to-peak signal. RxO will also have a signal output of 5 V peak-to-peak External loads may be connected
from RxO to RxO for a 6 dB push-pull signal gain or from
either RxO or RXO to VAG. With RSI tied to VSS, each output will drive 600 Il to + g dBm. With RSI tied to VDD, each
output will drive 900 Il to + 9 dBm.
ADDITIONAL PIN DESCRIPTIONS
RxG Receive Output Gain Adjust (MCl4402 Only)
If RxG is left open, then the output signal at RxO will be inverted and output at RxO. Thus the push-pull gain to a load
from RxO to RxO is two times the output level at RxO If
external resistors are applied from RxO to RxG IRI) and from
RxG to RxO I RG), the gain of RxO can be set differently from
- 1. These resistors should be in the range of 10 kll. The
RxO output level is unchanged by the resistors and the RxO
gain is equal to minus RG/RIIVRxO). The purpose of RxG is
to allow external receive gain adjustment. The circuit for RxG
and RxO is shown In the block diagram.

ANALOG
VAG Analog Ground
Each version of the PCM mono-circuit produces ItS own
analog ground Internally. The DC voltage IS approximately
(VDD - VSSI/2. All analog functions within the deVice use
this as a reference pOint for signal processing. In symetnc
dual supply systems (± 5, ± 6, etc.) , VAG may externally be
lied to the system analog ground supply. The VAG output
Will Sink more than 8 mA of current, but can source only 200
p.A. When RxO or RxO are output drives for 600 or 900 loads
lied to VAG, a pull up resistor to VDD will be reqUired to
boost the source current capability If VAG IS not tied to the
supply ground
Vref Positive Voltage Reference Input (MCl4402 Only)
The Vref pin provides for the supply of an external voltage
reference or for the selection of an internal reference within
the PCM monO-Circuit If Vref IS tied to VSS, the Internal
reference IS selected If Vref > VAG, then the external mode

+ Tx Positive Tx Amplifier Input (MCl4402/03/05 Only)
- Tx Negative Tx Amplifier Input (MCl4401 102/03/05 Only)
The Txl pin is the input to the transmit bandpass filter. If
+ Tx or - Tx are available, then there is an Internal amplifier
preceding the filter whose pins are + Tx, - Tx and Txl.
These pins allow access to the amplifier terminals to tailor
the input gain with external resistors. The resistors should be
in the range of 10 k. If + Tx IS not available, It is internally tied
to VAG. If - Tx and + Tx are not available, the Txl is a unity
gain high impedance input.

2-105

•

MC14400, MC14401, MC14402, MC14403, MC14405

..

Txl Analog Input
Txl is the input to the transmit filter. It is also the output of
the transmit gain amplifiers of the MCl4401 102/03/05. The
input impedance is greater than 100 k to VAG in the
MCl4400. The Txl input has an internal gain of 1.0, such that
a + 3 dBmO signal at Txl corresponds to the peak-to-peak
swing ofAxO described above. For ± 2.5 V shared
references and RSI~VAG, the +3 dBmO input should be
5.0 volt peak-te-peak.

For single-supply systems, these are the only power pins.
VLS Will be tied to VSS or VDD and VAG IS an output. In
dual-supply systems, VLS may be digital ground and VAG
may be analog ground.
Testing Considerations (MCl4400/01/02 Onlyl
An analog test mode IS activated by connecting MSI and
CCI to 128 kHz. In this mode, the input of the codec (the output of the Tx filterl is available on the PDI pin. This input is a
DC auto zeroed access to the AID side of the codec. If
monitored with a high-impedance buffer, the output of the
Tx low-pass filter can also be measured at the PDI pin. ThiS
test mode allows Independent evaluation of the transmit
low-pass filter and AI D side of the codec. The receive channel of the mono-circuit is tested with the codec and filter
together.

Power Supplies
VOO - Most Positive Supply. VDD is typically 10 to 12
volts.
VSS - Most Negative Supply. This is the most negative
supply pin.

TEST CIACUIT

600

o

dBr
HP3779
dBr

o

5V

MCI4403

VAG

Ax
10 k

5k
Tx
681

*51 kO

VAG

VDD

RxO

ROD

I01~F

+ Tx

RCE

Enable

Txl

ROC

Clock

- Tx

TOC

MulA

TOO

POI

TOE

VSS

VLS

*To Define ROD
When TOO IS high Z

01~FI

-5V
OPTIONS AVAILABLE BY PIN SELECTION
ASI*
Pin Level

Vref*
Pin Level

Peak-to-Peak Overload Voltage (Txl, AxOI

VDD
VDD

VSS
VAG+VEXT

7.56 Vpp
(302 x VEXT) Vpp

VAG
VAG
VSS

VSS
VAG + VEXT
VSS

VSS

VAG

5 Vpp
12 x VEXTI Vpp
63 Vpp
12.52 x V~XT) Vpp

+

VEXT

·On MCI4400/03/05, ASI and Vref tied Internally to VSS
On MCI4401, Vref tied Internally to VSS.

SUMMARY OF OPERATION CONDITIONS USER PROGRAMMED
THROUGH PINS VDD, VAG, AND VSS

~
rogramrnad

Logic

RSI
Peak Overload
Voltage

MulA

Level

VDD
VAG
VSS

Mu-Law Companding Curve and 03/04
Digital Formats with Zero Code Suppress
Mu-Law Companding Curve and Sign

Magnitude Data Format
A-Law Companding Curve and
CCITT Digital Format

2-106

VLS

3.78

CMOS
LogiC Levels

250

TTL Levels
VAG Up

315

TTL Levels
VSS Up

i:

o.....

TRANSMIT TIMING DIAGRAM

t

TOE

o
9
i:

tsul

o.....

t

TOC

o.....

tp2

tP3

~

i:
TDD

PCM Data

High Impedance

High Impedance

o.....

...
~

• Data output dUring this period will vary depending on TDC rate and TOE timing.

,!')

RECEIVE TIMING DIAGRAM

i:

o
.....

N

.....•

o

5

RCE

.....

j,.)

_,ot

_,ot

tsu3

i:

o.....

ROC

tsu51

t.---~

----.~

ROD - - D - o n ' t C a r - e

th

•

SlgnBltlBOi

t

o

~

U'l

)(~
B1

CCI/MSI TIMING DIAGRAM

CCI

r--~---=r

---./

'~J

,~,

.1

MSI

II

MC14400, MC14401, MC14402, MC14403, MC14405

THE BASIC VOICE CHANNEL USING THE MCl4400 PCM CODEC/FllTER MONO-CIRCUIT
+5V

•

~

1\

O.l"~F

~II I

g

•
~

.-- VAG

VDD

RxO

RDD

1 ......

RxO

RCE

Receive Sync

r

Txl

RDC

Receive Clock

Transmit C.lock

2~

N=4

j

~

0.1 "F :;;;:;::

I

Ring

t--

TTL levels
Digitalin

MulA

TOC

POi

TOD

Digital Output

VSS

TOE

Transmit Sync

MSI
VlS

-1

Digital Gnd

Power Down
-5V
MCl4401 PCM MONO-CIRCUIT WITH MCl4417 TSAC

1 kO

..

°l~

G

O'lt F
MC14401 II

VR X
Zout=6OO 0

600

ROD

---

RxO

RCE

-r-

1- RxO

RDC

I A?
"''''

10 k

'" "'1

,AA

VT X

10 k

AA

VDD

Txl

TOC

- Tx

TOO

",YV

Zin = 600 n

~ MulA

r+-

PDI

~ VSS

l

TOE

J
-

Rx Data
Tx Data
Data Clock
Tx Sync
Rx Sync

r----- Power Down

MSI

(TT l levels)

VLSJ

+5V
MC14417
VCC

Hard-Wired
Time Slot

+12V

VAG

~ RSI

VDD

D5

ST

D4

TxE

I-

D3

RxE

t---

D2

DC

D1

lE -<

DO

T/R-

~ NDC

FSR

~ VSS

FST
Digital GND

2·108

s:::

A COMPLETE SINGLE PARTY CHANNEL UNIT USING
MC3419 SLlC, MCI4403 PCM MONO-CIRCUIT, MCI4418 TSAC

0.....
Gnd

-=-

~

8

F'

s:::

Rx Data
Tx Data

0.....

~
~

0

.....
s:::

v

Data Clock
Tx Sync

~
~

0

I

j\)

I
I

...o
N
I

CD

s:::

I
I
I

I
I
I

~

0.....

0.....
Hook Status

Vce

~
~

0
~

s:::

0.....
~
~

0

en

Bank Status
Bank Select
Address
Data
Clock

-12 V

-48V
RIng Bus

MC14400, MC14401, MC14402, MC14403, MC14405
HYBRID INTERFACES TO MCl4401 PCM COOEC FILTER MONO-CIRCUIT

Ro = 900

•

RSI

VOO

VAG

ROD

RxO

RCE

RX1S

ROC

Txl

TOC

-Tx

TOO

'MulA

TOE

Poi

MSI

VSS

VLS

4 Ro

10 k

MCl4401
Simplified Transformer Hybrid Using MCl4401

1/3 Ro

N=2

:::r ~
RSI

VOO

VAG

ROD

RxO

RCE

RX1S

ROC

Txl

TOC

-Tx'

TOO

-MulA

TOE

4/3 Ro
Ra
Rc'

1/3 Ro
Rb

Rai Rb= Ro
RbslO kll

'&:=4
Rb

Poi

MSI

VSS

VLS

MC14401

"T" Padded Transformer Hybrid Using MCl4401

2-110

MC14400, MC14401, MC14402, MC14403, MC14405
HYBRID INTERFACES TO THE MCI4402 PCM COOEC/FILTER MONO-CIRCUIT

RO = 600

+Vref

RSI

VAG

VOO

RxO

ROD

RxG

RCE

RxO

ROC

+Tx

TOC

Ro=900

•

Vss
R4
R3

Txl

CCI

- Tx

TOO

MulA

TOE

PiSi

MSI

VSS

VLS

Rl

Balance by R5 and R6 to equate the Txl gains through the inverting
and non-Inverting Input signal paths, respectively, IS given by

Rl (
R3) (, Rl)r_ R6
(R3) R5 l
2x R2 I- 1M =~ +ii2 l..R5+ R6 - 1M R5+ R6J

Tx Galn= Rl/R2
Rx Galn= 1 + R3/R4
R5, R6,,'0k
AdJust Rx Gain with R3
AdJust Tx Gain with Rl

MCI4402
Universal Transformer Hybrid Using MCI4402
R0= 600

~
~
~

-=1-1

$.,0 kG

T

RSI

+Vref

VSS
VAG

VOO

RxO

ROD

RxG

RCE

-RxO

ROC

+Tx

TOC

N=2
.A

10 kG

'"Ro

1

I
-'"

CCI

Txl

20 kG
- Tx

TOO

MulA

MOE

I5i5i

MSI

VSS

VLS

10 kG

Single-Ended Hybrid Using MCI4402

2-111

MCI4402

Ro=900

~

'0-:

•

( "~

128 CHANNEL GROUP COMMON CONTROL
IN A TYPICAL SWITCHING SYSTEM

i:
0
.....

""""

VOO~12V

Data Clock.

0

p

II

Master

Data Clock

Common

Control
LogIc

Tx Sync

Tx Sync

Optional
Concentration

Ax Sync

TSICS
1 to 4

Tx Data

Master
Frame Sync

TxData

XC145420

Tx Data
Highway

Rx Sync

Rx Data

Ax Tone

RxTSIC
Array
4 to 16

Ax Data

Rx Data
~

HIghway

al

E

XC145420

!

N

•
....
....
N

Hook

Status MUl<

Ii

to

l!

24
8 Bit Micro Bus

""""

0

~

0
.....

~

0
~

""""

Cl

i:

Memory
(ROM. RAM,
EPROM)

Bank Status

i:

0
.....

i:

j
.l:
,c
.=

Local Call
Processmg

"""".....

,!')

~

!

0
.....

0

1 to 4

IMSllS
and CMOS)

i:

0
.....

24

""""

Bank Select

0

en

Channel

Address

Group Call

Processor
IMlcrop)

Data

CIk

VSS~O

V

VEE'" -48
Rlngmg Bus

NOTE: See single party line drawing for line card details"

Intergroup

Dat8 Bus

®

MC14408
MC14409

MOTOROLA

BINARY TO PHONE PULSE CONVERTER SUBSYSTEM
The MC14408 and the MC14409 are devices designed to convert
a four bit binary input code to a number of serial output pulses
corresponding to the value of the input code.
The devices can be used in telephone pulse dialing applications
when combined with their companion device, the MC14419
(2·of·8 keypad·to·binary code converter). The devices have been
partitioned to allow convenient addition of RAM memory and
controls for repertoire dialing applications.
The MC14408 and MC14409 perform identical functions with
the exception of the signal output at the DRO (Dial Rotating
Output). In the MC14408, DRO remains high during continuous
outpulsing of all digits and in the MC14409 DRO is low between
each digit pulse burst.

•
•
•
•
•
•
•
•
•

•

On·Chip Oscillator
Diode Protection on All Inputs
Dialing of Numbers Up to 16 Digits Long
Memory Storage (FIFO) and Re·Dialing (single pin) of Last
Telephone Number
Hold Interrupt Control for Additional Interdigit Delays (such as
a Wait for Intermediate Dial Tones)
Selectable Dialing Rate (10 pps or 20 pps)
Selectable Interdigit Time (300 or 800 ms @ 10 pps;
150 or 400 ms@ 20 pps)
Selectable Make·Break Ratio (61% or 67%)
Buffered Outputs Compatible with Discrete Transistor Driver
Interface, One Low·power Schottky TTL Load or Two Low·
power TTL Loads Over the Rated Temperature Range.
Low Power Dissipation - IDD (operating with oscillator)
= 470 JlA typ@ VDD = 5.0 Vdc, fOsc = 16 kHz,
CL = 50 pF

CMOS LSI
(LOW·POWER COMPLEMENTARY MOSI

BINARY TO PHONE PULSE
CONVERTER SUBSYSTEM

L SUFFIX
CERAMIC PACKAGE
CASE 620

P SUFFIX
PLASTIC PACKAGE
CASE 648

PIN ASSIGNMENT

16
15
3

14

4

13
12

6

BLOCK DIAGRAM

11
10

8

9

Strobe 3 0 - - ST
40--- 04

Bmary

11

OutPulsing

12

Dial Rotating
Output

D3

Inputs

D2
D1 CFiCi
HaL
RED

ID~RO
MBR

This device contains circuitry to protect

the inputs against damage due to high static

Hold

9

1InterdI9~e~~~a~ :~=========~_--'
Call Request 13

Controllnpuu

VOD = Pin 16
VSS:: Pin a

Make Break Ratio 15 _ _ _ _ _ _ _ _-'

2-113

voltages or electric fields; however, it is
advised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to this high
impedance circuit. For proper operation it
is recommended that Vin and V out be
constrained to the range VSS ...;; (Vin or
V au,) " VOO'
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VOD).

•

MC14408, MC14409
MAXIMUM RATINGS (Voltages referenced to VSS Pin 81
Rating

DC Supply Voltage
Input Voltage, All Inputs

DC Current Drain per Pin

•

Operating Temperature Range

Storage Temperature Range

Unit

Symbol

Value

VDD

-0.5 to -lil.O

Vde

Vi"

-0.5
to
VDD +0.5

Vde

I

10

mAde

TA
T stg

-40 to +85

°c
uc

-65 to +150

ELECTRICAL CHARACTERISTICS

-

Characteristic
Supply Voltage
Output Voltage

"0" Level
"I" Level

25°C

-40OC

+85OC

Symbol

VDD
Vdc

Min

Max

Min

Typ

Max

Min

Max

VDD

-

3.0

6.0

3.0

5.0

6.0

3.0

6.0

Vde

Vout

5.0
5.0

-

0.05

-

0.05

-

0.05

4.95

-

4.95

0
5.0

-

4.95

-

Vde
Vdc

5.0
5.0

1.5
1.4

-

1.5
1.5

2.25
2.25

-

1.4
1.5

-

Vde
Vde

IOL

5.0
5.0
5.0

-1.0
-0.20
0.52

-

-0.80
-0.16
0.44

-1.7
-0.36
0.88

-

-0.60
-0.12
0.36

-

mAde

lin

6.0

0.3

-

±O.ooool

to.30

/lAde

-

-

1.0

Gin

-

12

pF

100

3
5
6

200
550
1000

/lAde

-

Unit

Noise Immunity

("V out .. 0.5 Vdel
("'V out .. 0.5 Vdel
Output Drive Current
(VOH ; 2.5 Vdcl
Source
(VOH ; 4.6 Vdcl
(VOL; 0.4 Vde)
Sink

VNL
VNH

mAde

IOH

I nput Current
Input Capacitance

12

-

5.0

12

250
700
1250

-

160
470
740

200
550
1000

(Vin; 01
Operating Supply Current

fel; 16kHz

(operating

with
oscl

or 04

ST

tSU( OS)

-

FIGURE 2
TIMING DIAGRAM - CALL REOUEST

FIGURE 1
TIMING DIAGRAM - DATA AND STROBE INPUTS

01'O2'O3'~I_

-

voo

Voo

I

-I- "I 'h

n

!----l'WH

Voo
(Power)

Vss

I-

VOO
CRQ

VSS

I

-I

VSS
tpc

I

VOO

VSS

If power is turned off after each call, CRa must stay high after
power is applied (for a duration of fPC) to ensure no spurious
outpulslng. For this use the redial function is invalid.

2-114

MC14408, MC14409
SWITCHING CHARACTERISTICS ICL = 50 pF TA = 25 0 C)
Characteristic
Output Rise Time**
tTLH = 13.0 ns/pF) CL

tTLH

VOO
5.0

tTHL

5.0

Min

Typ

Max

Unit

-

180

400

ns

100

200

ns

-

ms

-

ms

-

I'S

+ 30 ns

Output Fall Time··
tTHL = 11.5 nsipF) CL

Symbol

+ 25

ns

Power Up to Call Request Pause

tpc

3 t06

48/lel-

Call Request to First Strobe Pulse

tcs

3 to 6

48/101-

Strobe to Strobe Separation Time

tss

3 to 6

48/lel-

Strobe Pulse Width

twH

3 t06

1.0

-

Strobe to Data Hold Time

th

3 to 5

-

150

400

ns

Clock Frequency***

lei

3 to 6

12.5

16

100

kHz

%MB

3 to 6

-

61
67

-

-

10
20

-

Percent Break to Make Ratio

IMBR = 0)
IMBR = 1)
Outpulsing Rate IIOPL = -lel/1.6)
lei = 16 kHz
lei = 32 kHz

Interdigit Time
tID = 15 x lOT + 3)/IOPL
lOT = 0
10PL = 10 pps
10PL = 20 pps

10PL

tID

Strobe to Output Time

tSOI

%

pps

3 t06

-

3 t06

IDT= 1
10PL = 10 pps
10PL = 20 pps

ms

ms

-

300
150

-

-

800
400

-

-

-

3 t06

ms

Initial Outpulsing Stream

lOT = 0
10PL = 10 pps
10PL = 20 pps

300
150

-

400
200

IDT= 1
10PL = 10 pps
IOPL = 20 pps

BOO
400

-

900
450

Continued Outpulsing Stream

tsoc

3to 6

lOT = 0 or 1
10PL = 10 pps
10PL = 20 pps
Hold to Outpulse Time
IDT=Oorl

100
50
tHOL

Data to Strobe Setup Time (lei = 16 kHz)
Re-dial Pulse Width

(lei - 16 kHz)

*'!

3 t06

-

-

200
100

-

-

ms

-

100
50

tSUIDS)

3 to 6

1.5

-

-

3to 6

-

200

*fel In kHz
··The formula given is for the typical characteristics only.

* Minimum clock pulse width = 1.0 J.l.s.

2-115

200
100
m.

100
50
tORO

-

3 to 6

10PL = 10pp.
10PL = 20 pps

Dial Rotating Overlap Time.
10PL = 10pp.
10PL = 20 pp.

ms

-

1"
ns

MC14408, MC14409

FIGURE 3
PHONE DIALER SYSTEM TIMING DIAGRAM

'I'_____t_s_s____."I. . ;. . . ;________. .;. ___________

I-

CRD ~_t::_...:.
ST

•

j

___

n

1st (3)'

n

2nd (2)

3rd (S)

I

I..
I..
=:;:::;;::::;::::;::::;::::;:::;:;_----;~I;:-:;:--::;-;:::-:;:--:::j-=-:;::-~I:-----il--------

HOL===
ORO _ _ _

QP[~---

I

UUlf'

I

UU

I

I

~~"1r____-Y__lfOPL ~ ~tDRO

r

tDROj
tSOI

tID

B

%MB= 1 0
0-CRO _____________________
,B_+_M
____________________________

ST

HOL

---"4th (1)

_.

,

I

-----,,---t-----------------------i-·'

DRO==:J
....

lJlJlJlJlJ

I

I

I

I

I

I

W ..

I

I

I

~

CRD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ....J. - - -

ST::::::::::::n~:5t:h:(:6)::::::n~:6t:h:(:I)::::::::::::::::::::::::::::::::::

I

HOL

1------ --- --II!=;:=

DRO=;:::;:::;::::;::::::;:::!....,
OPL

I

LJUlJ1Jll1J

I

~ ~~OC

If'-

I

Notes:
(·)1st. 2nd, 3rd, etc., denotes Strobe pulse sequence - i.e., which digit
in the phone number Is being dialed. The number In parentheses denotes the numerical value of the digit being dialed. The examples

define the various voltage -

level and timing requirements, not a

complete phone number.
C")For the MC14408 the ORO signal will remain high provided digits
remain in the memory. or a digit for continuing outputslng Is strobed

in before the anticipated fallina edge of the most significant digit In
the memory. (i.e., [200 % MB1 ms after the most significant out·
pUlsing edge). The time from Strobe to 0 RO can be 0 to 100 m ••
(···)For the HOL signal to hold a next digit (e.g. the 4th, etc.,) the HOL
falling edge must not appear after {tIO-%MB + 100) rns the last
outpulsing edge of the previous digit.

2-116

1- - -

L-

MC14408, MC14409
FIGURE 4
COMPONENT SELECTION FOR OSCILLATOR/CLOCK FREQUENCY

fel
To PIn 1

7.118
= ..J----CC-

h

f·

were cl

~
~C2

In

kH

z,

L·

In

m

H

•

C=C1 =C2in}J.F

To Pin 2

"fel

= -0.5

[%C + %L] ±3,D where %fcl. "C, %L are
the frequency capacitor, and
Inductor tolerances in per-

cent. The ±3.0% accounts

~Cl

for supply voltage and am-

bient temperature variations.

EXAMPLE
L
5.0mH

C=Cl=C2

%C

t5.D

O.04I'F

±5,D

~16

kHz

tS.D

1'11110pps

O.OII'F

±5.0

r::1:132 kHz

±S.a.

r::1:120 pps

±5.D

5.0mH

OUTPULSING RATE
fOPL = f ell1·6

%L

fel

%fel

FIGURE 5
TRUTH TABLE

=

INPUTS

04030201

Am

ST

x x x x x
x x x x 0
x x x x SL

=

OUTPUTS
IDT

Number of pulse, M of nth
digit = binary COmbination of
04,03,02,01- •
DigIts of number
re-sent

-U-

1

x
x

X

X

o (Stead V State)

1 (Steady State)

"'nthb'-;rt'

x x x x
x x x x

DROt

MBR

In

memory

01

1

After concl uSlon 01
digIt being outpulsed

300 ms IMerdlSIt time
BOO ml Interdlglt time

X

During outpul,ing

Otherwise

l

i

f

Ounng outpulslng
Otherwise
After conclUSion of digit

bemg outpulled

6
cl.'- 1

kHz

61% 1"'" 61) Make-Break RatIO
67% 1""21) Make-Break RatiO

XXXXX

x = Don't Care
With the BKcaptlon of

0000 which will give 10 pulses.

t

Refer to timing diagram Figure 3

FIGURE 6
MEMORY CLEAR

FIGURE 7
REDIAL SEQUENCE

-------------------------------Voo

II+- 1

r-----Voo

Vss

Vss

tcs

ST

n

----------------

ST

~-------

2-117

MC14408, MC14409
DEVICE OPERATION
OSCILLATOR (Osc, Pin 1)
This pin is an input to the internal oscillator and feedback connection for the L-G rr-network_ An external clock
signal, if desired can be applied to Osc_

•

CLOCK (Clk, Pin 2)
This pin is an output from the internal oscillator and
feedback connection for the L-G rr-network and provides
the system clock for the MG14419 bounce eliminator
circuitry.

RE-OIAL (REO, Pin 10)
The Re-Oial Input, when taken low (REO= VSS) automatically outpulses the digits entered Into memory after the
last time a call was requested. (See Redial Sequence
Oiagram Figure 6.)

STROBE INPUT (ST, Pin 3)

OUTPULSING (OPL, Pin 11)
The Outpulsing output sends out bursts of pulses
equivalent to the digits of the telephone number stored in
the memory. The duty cycle and interdigit time of the
digit pulse bursts are controlled, respectively by the MBR
(Pin 15) and lOT (Pin 14)_

This Strobe input, when high (ST = VOO), signifies
that the data at the 01, 02, 03, and 04 inputs is valid,
and enters the 4-bit number into the internal FIFO
(First-In, First-Out) memory for subsequent outpulsing_
The first strobe pulse after a call is requested (CRQ
= low) clears the memory of any previous number and
enters the first digit of the new number. Successive
strobe pulses will store up to a maximum of 16 digits in
the internal FIFO memory, which ignores all digits
entered in excess of that amount until a new call is
requested.

DIAL ROTATING OUTPUT (ORO, Pin 12)
The Oial Rotating (also known as "Off Normal")
Output provides a signal which indicates that digit pulse
bursts are being sent_ In the MC14409, ORO goes high
(VOO) at the beginning of the first digit pulse burst and
goes low (VSS) between succeeding consecutive digit
pulse bursts. In the MC1440B, however, ORO goes high at
the beginning of the first digit pulse burst and remains
high until the last digit pulse burst of the telephone
number has been sent (see Timing Oiagram, Figure 3)_

DATA INPUTS (04, 03, 02, 01, Pins 4, 5, 6, 7)
These pi ns are the Oata inputs to the internal memory.
A binary coded digit number entered will result in an
equivalent number of pulses at the OPL (outpulsing)
output, except for the code 0000, which will outpulse
10 pulses.
NEGATIVE POWER SUPPLY (VSS, Pin 8)
This pin is the negative power supply connection.
Normally this pin is system ground.
HOLD (HOL, Pin 9)
When taken low (HOL = Vssl. the Hold input disables
the outpulsing at the completion of the digit being outpulsed. When taken high, outpulsing res~mes_ This feature
can be used in multi-dial-tone phone systems to provide
longer interdigit pauses when necessary_

CALL REQUEST (CRQ, Pin 13)
The Call Request Input when taken low ICRG = VSS)
resets internal counters and prepares the Internal logic to
either accept new digit Inputs to be dialed, or to re-dlal Isee
REO, Pin 10) the digits stored In the memory. The Relationship Between Memory Clear and Redial IS shown In Figure 7.
INTEROIGIT TIME (lOT, Pin 14)
The Interdigit Timing input determines the length of
time between consecutive digit pulse bursts. See the
Interdigit Time (tID) in the switching characteristics for
the length of time_
MAKE-BREAK RATIO (MBR, Pin 15)
The Make-to-Break Ratio input controls the duty cycle
of the digit pulse bursts at the OPL output. For MBR
= VOO, duty cycle = 67% low, 33% high; and for MBR
= VSS, duty cycle = 61% low, 39% high_
POSITIVE POWER SUPPLY (VOO, Pin 16)
This pin is the package positive power supply pin.

2-118

MC14408, MC14409
FIGURE 8 - KEYPAD TD PULSE DIALER FLDW DIAGRAM

Pick-up Head-set

I

~
Dial-tone heard

,.-----

I

~

Keyboard buttons pressed •
(previous number cleared).

Rs-dial button pressed
(previous number held).

Dial tone stops with 1st digit,
but receiver connects to line

Dial tone stops with 1 st digit,
but receiver connects to line
after each digit sent. t

after Bach digit sent. t

J

J

Error.

Error.

Data entry error

Too many digits put

recognized by

in <>16), Ignores

person dialing.

excess.

I

l

Error.
No number
in memory.

l

I

• A number can be interrupted between

Call made with success

digits by use of the Hold Input.

or busy signal.

tWith the MC1440S the line connects after
total outpulsing has stopped.

I
Hang-up Head-set

FIGURE 9 -

PHONE DIALER SYSTEM

MCl4419

MC14408, MCl4409
Binary..to-Phona Pulse Converter

2-of-8 Keypad-to-Binary Encoder

!

1

Row

14

From
Keypad

13

4

12

5

11

6

04
03

~~~uu~.n

02

=

01

Pin 16

= Pin 8

VSS
ST

I
I
I
I

OPI.

11

Outpulslng

ORO

12

Dial Rotating
Output··

04
03
02

10

{

I
Voo
VSS

3

ST

{

Inputs

I-

01

------- J
HOld

9

Call Request 13

MC1440Bi409
Control Inputs

Re-Dial 10
Interdlgit Time 14
Make-Break Ratio 15

·For Component Value Selec::tlon See Figure 4.

2-119

Vee

= Pin

16

VSS"" Pin 8

•• Between each digit
pulsetraln. MC14408
ORO stays high,
MC14409 ORO goes low.

MC14408, MC14409
FIGURE 10 -

STANDARD K-500 TELEPHONE

Diel Rotated
(Off Normal)

GN

,-=-----,

I

I
I

•

I

I
L __ _

I

I

To
Phone

I
I

Lines ---(\\:H---;'

I
Encapsulated

L

FIGURE 11 -

_

~OO Circuitr:Y....

I

.-J

MODIFIED K-500 TELEPHONE

lN4004

GN

,-=-----,

I

Receiver

I

I

I
To
Phone
Lines

I
I

L2

I
I

~~-4---i~---t=~:t::t-~

I
I

Ll

0.04 JJF

V 55

0--1

L

O.04JJF

'-.-f..,...,........~--J

r----o

_

Encapsulated
K-500 Circuitry-

V 55

Re-dial

Vss

2-120

(SPOT Momentary)

Voo

0- VSS

I

®

MC14410

MOTOROLA

2-0F-8 TONE ENCODER

CMOS LSI

The MC14410 2-of-8 tone encoder is constructed with complementary MOS enhancement mode devices. It is designed to accept
digital inputs in a 2·of·8 code format and to digitally synthesize the
high and low band sine waves specified by telephone tone dialing
systems. The Inputs are normally originated from a 4 x 4 matrix
keypad, which generates 4 row and 4 column input signals in a
2·of·8 code format 11 row and 1 column are simultaneously connected
to VSSI. The master clocking for the MC14410 is achieved from a
crystal controlled oscillator which is Included on the chip. Internal
clocks, which operate the logic, are enabled only by one or more
row and column signals being activated Simultaneously. The two
sine wave outputs have NPN bipolar structures on the same substrate
which allows for low output impedance and large source currents.
Applications of thiS deVice include telephone tone dialing, radiO and
mobile telephones, process control, point·of·sale terminals, and
credit card verification terminals.
•

Diode Protection on All Inputs

•

Noise Immunity = 45% of VOD Typical

•

Supply Voltage Range

(LOW-POWER COMPLEMENTARY MOSI

2-0F-8 TONE ENCODER

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE

CASE 648

= 4.4 Vdc to 6.0 Vdc

• On·Chlp Oscillator ICrystal or External Clock Source may be
applied to Pin 10)
PIN ASSIGNMENT

•

On·Chlp Pull·Up ReSistors on Rowand Column Inputs

•

DeSigned with Multiple Key Lockout IElimlnates Need for Mechanical Lockout in Keypad)

•

Two Sine Wave Generators On·Chlp

•

Frequency Accuracy ±0.2%

LB out

2

15

~H8out

14~C1

•

Low Harmonic Distortion

R1

•

Single Tone Capability

R2

4

13

Fast Oscillator Turn-On and Turn-Off Times

R3

5

12~C3

•

R4

6

11

TPA

7

10

VSS

8

9

~C2

C4
Oscin

OSCout

BLOCK DIAGRAM

3
Row

2 Low
Band Out

1
4

Inputs

:

This device contains circuitry to protect

OSCIllator

ConnectIons

Column
Inputs

I '~

7 Test
POint A

9

{"

13
12

11

-: N
Control

15 High
Band Out

Voo"" Pin 16
VSS:: Pin 8

2-121

the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high·impedance circuit. A destructive high-current mode may occur if Vin
and V out are not constrained to the range
Vss (V," or Vou,l .;; VDD'
Due to the sourcing capability of this
circuit, damage can occur to the device if
VOO IS applied, and the outputs are shorted
to Vss and are at a peak sinewave voltage.

•

MC14410
MAXIMUM RATINGS {Voltages relereneed to VSS. Pin 8.1
Value

VDD

-0.5 to +6.0

Vde

Input Voltage, All Inputs

V ,n

VSS -0.5
to
VDD + 0.5

Vde

Rating

•

Unit

Symbol

DC Supply Voltage

DC Current Drain per Pin
Operating Temperature Range
Storage Temperature Range

I

10

mAde

TA
T stg

-40 to +85

°c

-65 to +150

C

ELECTRICAL CHARACTERISTICS
Characteristic

Supply Voltage
"0" Level

Output Voltage
Pms 7 and 9

Min

Max

Min

Typ

Max

Min

Max

Unit

VDD

-

4.4

6.0

4.4

5.0

6.0

4.4

6.0

Vde

V aut

5.0

-

0.05

-

0

0.05

-

0.05

Vde

5.0

4.95

5.0

-

4.95

-

Vde

1.5

Vde

-

Vde

"1" Level

VIL

5.0

VIH

5.0

Output Drive Current

IOH
Source
Pin 7
Pin 9

(VOL: 0.4 Vde)

Sink
Pin 7

-

4.95

-

1.5

-

2.25

1.5

-

3.5

-

3.5

2.75

-

3.5

mAde
-0.04
-0.16

-

-

0.04
0.16

-

100

-

80

I'Ade

5.0

-

-

-

pF

-

0.2
0.55

0.4
1.1

-

0.33
0.9

-

-0.05
-0.20

-0.4
-1.7

5.0

0.05
0.23

-

-

0.05
0.20

0.20
0.78

-

6.0

-

140

-

30

-

-

-

-

4.4
6.0

-

0.48
1.3

-

-

mAde

IOL

IlL

-

-0.05
-0.23

5.0

Pin 9
Input Pull~Up Resistor Source Current

+85D C

25°C

VDD
Vde

Input Voltage
(VO : 4.5 or 0.5 Vde) "0" Level
(VO : 0.5 or 4.5 Vde) "I" Level
{VOH : 2.5 Vdel

-40o C

Symbol

Pins 3-6.11-14

(Von: 0 Vdel
Input Capacitance

Con

{Vin: 0 Vdel

Total Supply Current
{AL: 15 k!1. I : 1 MHzl
Low Band OutJjut

High Band Output
Voltage Swing

-

mAde

IT

(Oy'namic plus Quiescent)

Voltage Swing
(AL: 100 kl

mAde

IQ

Quiescent Current

4.4
6.0

-

1.7
3.5

-

0.7
1.45

1.4
2.9

-

-

-

1.15
2.4

4.4
6.0

400
800

600
1000

500
900

600
1000

700
1100

550
950

750
1150

4.4
6.0

600
1000

900
1400

700
1100

850
1350

1000
1500

800
1200

1100
1600

mVpp

VLpp
Pin 2 Only

mVpp

VHpp
Pin 15 Only

(AL: 100 k)

Low Band-High Band

t>.V

5.0

-

.-

--

2.5

-

-

-

dB

Zo

-

-

-

-

80

-

-

-

n

-

-20

-

-30

-25

--

-25

fel

4_4
to
6.0
4.4

-

-

-

1.0

-

1_1

-

MHz

ton

5.0

-

-

-

8.0

-

-

-

ms

Voltage Differential

Pon 2.15
Low Band-High Band
Output Impedance AC only

Pin 2.15 V2W V14H
Low Band-High Band
2nd thru 14th HarmOniCs
(AL: 15 knl
Maximum Clock Pulse Frequency
Turn-on Time
(Power on to oscillation)

2-122

dB

MC14410
TABLE 2 - OUTPUT FREQUENCY TABLE

TABLE 1 - FUNCTIONAL TRUTH TABLE
OUTPUTS

ACTIVE LOW INPUTS

Activated

Activated

Row Lines

Col umn lines
X"

None

Frequency Gen«sted··

Input Line

Low Band
Pin 2

High Band
Pin 15

Activated (low)

fL (Hzl

R1

697

de level

de level

R2

770

None

de level

de level

R3

852

One

One

tL •

R4

941

Two or more

One

de level

t H•
t H•

C1

One

Two or more

de level

C2

Two or more

Two or more

de level

C3

-

X"

t
de level

C4

·See Table 2
•• X = Don't care

fH (Hzl

1209
1336

1477
1633

• -All frequencies are accurate to ±O.2% (crystal tolerance
not Included).

FIGURE 2 - TYPICAL FREQUENCY SPECTRUM
(Pins 2 or 15, No External Filtering)

FIGURE 1 - TYPICAL SINE WAVE OUTPUT

(Pins 2 or 15, No External Filtering)

o

-20

iii

-1!

"9

.f

-

«

to

c

0.
E

-40

'.
-60

-80
Time

Fundamental

FIGURE 3 - TYPICAL CRYSTAL CIRCUIT

Rf= 15 Mn ± 10%

Crystal Mode

Column In

Row In

CRYSTAL SPECI FICATION

Parallel

Frequency

1 MHz

RS

5400 typ

Co

7.0 pF typ

Temperature Range

-40°C to +8SoC

Test Level

1 mW

Test Set

TS-330/TSM

1:

0.1%
High Band
Rt

MC1441Q
Low Band

or Equivalent

• Recommended Crystals. CTS'KN IGHT

2-123

•

MC14410
FIGURE 4 - TYPICAL TELEPHONE INTERFACE APPLICATION

•

Telephone

Re<,.I,I,erAssemblV
MDA9204

(oPtlonell

I

i~

:: Tel:~;:ne
I
IConnecttOns

Not.

I
I
I
I
I
I
I
I
I

Interface
C"cultrv

Appl":alI0n U$lIlg standard telephone keypad

FIGURE 6 - BATTERY POWERED OPERATION

FIGURE 5 - LOW LEVEL OUTPUT
TONE GENERATOR APPLICATION

(Driving Audio Speaker)

f-O.-----+-..

level ,nput

(-40d8Attenua"onl

NOle

Apphcallon ".mg Cham.rlC' Keypads

'ER21623 14 '0 ....

~

3 columns)

oiOEA21611 (4rl)w.x4coiumno)

2-124

®

MC14411

MOTOROLA

CMOS LSI

BIT RATE GENERATOR
The MCl4411 bit rate generator is constructed with complementary
MOS enhancement mode devices. It utilizes a frequency divider network to provide a wide range of output frequencies.
A crystal controlled oscillator is the clock source for the network. A
two-bit address is provided to select one of four multiple output clock
rates.
Applications include a selectable frequency source for equipment in
the data communications market, such as teleprinters, printers, CRT
terminals, and microprocessor systems.
• Single 5.0 Vdc (± 5% I Power Supply
• Internal Oscillator Crystal Controlled for Stability (1.8432 MHzl
• Sixteen Different Output Clock Rates
• 50% Output Duty Cycle
• Programmable Time Bases for One of Four Multiple Output Rates
•. Buffered Outputs Compatible with Low Power TTL
•
•
•
•

•

(LOW-POWER COMPLEMENTARY MOSI

BIT RATE GENERATOR

LSUFFIX
CERAMIC PACKAGE
CASE 623

P SUFFIX

4!'
"

PLASTIC PACKAGE .
CASE 709
24

Noise Immunity=45% of VDD TYPical
Diode Protection on All Inputs
External Clock May be Applied to Pin 21
Internal Pull up Resistor on Reset Input

','

.,. , ~ ~ .. "' ...

"~ .

11·' .

PIN ASSIGNMENT
F1

MAXIMUM RATINGS (Voltages referenced to VSS Pin 12 I
Rating
Symbol
OC Supply Voltage Range
VOO
Input Voltage, All Inputs
Vin
I

DC Current Dram per Pin
Operating Temperature Range

TA
Tstg

Storage Temperature Range

Value
5.25 to -0.5

Unit
V
V

VOO+0.5 to
VSS-0.5
10

• Crystalout 20

**
Re~t 10o-----------~~~--_+----------~

Xtalln

F8

Xtalout

F9

F15

°C
°C

F11

F2

F14

F4

f1eset

F6

17

F1
F2
F3

16

F4

3

F5
F6
F7
F8

Crystalln 21

F7

mA

1

Rate Selects 2 2 0 - - - - - - - - - - - - - - ,

RSs

F16

-85 to +150

Rate SelectA 2 3 0 - - - - - - - - - - - - - - - - - ,

RSA

F5

FlO

-40 to +85

BLOCK OIAGRAM

Voo

F3

7

F9

6

FlO
F11
F12
F13
F14

14
13
J9

Not Used

F12

VSS

F13

Voo= Pin 24
VSS= Pin 12

ThiS device contains circuitry to protect the
Inputs against damage due to high static
voltages or electriC fields; however, it is adVised that normal precautions be taken to
aVOid application of any voltage higher than
maximum rated voltages to this high impedance cirCUit. For proper operation it IS
recommended that Vin and Vout be constrained

to

the

range

VSS s (V in

or

VoutlsVOO·

* See Figure 2 for tYPical
crystal OSCillator cirCUIts.

* * When Reset = 0, outputs F1 thru F14 = 0, outputs F15 and F16 = 1.

2-125

18

F15

Unused Inputs must always be tied to an

19

F16

appropriate logic voltage level (e.g., either
VSS or VOOI.

MC14411
ELECTRICAL CHARACTERISTICS
Characteristic
Supply Voltage
Output Voltage

"0" Level
"1" Level

•

Input Voltage
(VO=4.5 or 0.5 VI

4QoC

Symbol

VDD
Vdc

Min

Max

Min

25°C
Typ

Max

Min

Max

VDD

-

4.75

5.25

4.75

5.0

5.25

4.75

5.25

V

5.0

-

0.05

-

0

0.05

-

0.05

V

5.0

4.95

-

4.95

5.0

-

4.95

-

V

Vout

+ 86°C

Unit

VIL

5.0

-

1.5

-

2.25

1.5

-

1.5

V

(VO=0.5 or 4.5 Vdcl

VIH

5.0

3.5

-

3.5

2.75

-

3.5

-

V

Output Drive Current
(VOH=2.5 VI Source

IOH

5.0

-0.23

-

-0.20

-1.7

-

-0.16

-

mA

IOL

5.0

0.23

-

0.20

0.78

-

0.16

-

mA

-

-

±0.1

-

±O.OOOOl

±0.1

-

-1.5

-

-7.5

-

5.0

-

0.015

25

-

(VOL =0.4 VI

Sink

Input Current
Pins 21, 22, 23

lin

Pin 10

5.0

m

-

±10

~A

-

~A

-

pF

15

mW

Input Capacitance (V,n = 01

C

Quiescent Dissipation

Po

5.0

Power Dissipation·· t
(Dynamic plus Ouiescent!
(C =15 pFI

Po

5.0

tTLH

5.0

-

-

-

70

200

-

-

ns

tTHL

5.0

-

-

-

70

200

-

-

ns

Output Rise Time"

2.5

mW

PO= (7.5 mW/MHzI f+ PQ

tr= (3.0 ns/pFI CL + 25 ns
Output Fall Time··
tf = 11.5 ns/pFI CL + 47 ns

fCL

5.0

-

1.85

-

-

1.85

-

1.85

MHz

Clock Pulse Width

tW(C!

200

-

200

-

-

200

tWIRl

500

-

500

-

-

500

-

ns

Reset Pulse WIdth

-

Input Clock Frequency

ext~rnal capacitance (CU refer to corresponding formula:
PT(CL = Po + 2.6 x 10- 3(CL -15 pF! V002f
where: PT, Po In mW, CL In pF, VOO In Vdc, and f In MHz.
··The formula given IS for the typical characteristics only.

tFor diSSipation at different

TABLE 1 -

OUTPUT CLOCK RATES

Rate Select

Output
Number
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FlO
Fll
F12
F13
F14
F15
F16·

Rate

B

A

0
0

0
1

Xl

1

0

X16

1

1

X64

X8

Output Rates (Hz!
X64

X16

XB

Xl

614.4 k
460.8 k
307.2 k
230.4 k
153.6 k
115.2 k
76.8 k
38.4k
19.2 k
12.8 k

153.6 k
115.2 k
76.8 k
57.6 k
38.4k
28.8 k
19.2 k

76.8 k
57.6 k
38.4k
28.8 k
19.2 k
14.4 k

9600

9600
8613.2
7035.5

4800
921.6 k
1.643 M

9600
4800
3200
2400
2153.3
1758.8
1200
921.6 k
1.643 M

• F16 IS buffered oscillator output.

2-126

9600
4800
2400
1800
1200
1076.6
879.4
800
921.6 k
1.643 M

7200

4800
3800
2400
1800
1200
800

300
200
150
134.5
109.9
75
921.6 k
1.643 M

ns

MC14411
FIGURE 1 - DYNAMIC SIGNAL WAVEFORMS

20 ns

20 ns

~VDD
Input

10%

o%

Output

VSS

~
90%

tTLH

VOH
VOL

tTHL

FIGURE 2 - TYPICAL CRYSTAL OSCILLATOR CIRCUIT

Rate Select

A

B

Bit Rate
Clock Outputs

D

-.- 12-pF

_

~

20
Rf~15

Xtalout

Crystal Spacifications
Crystal Mode
Frequency
RS

MIl±10%

Parallel

1.8432 MHz ±0.05%@13 pF
540 Il max
7.0 pF max
o to 70°C

Co
Temperature Range
Test Level
Test Set

1mW
TS - 330/TSM or EqUivalent

'Suggested Crystal Suppliers:
Tyco. CTS Knights

Circuit diagrams utilizing Motorola products are included as a means
of Illustrating typical semiconductor applications, consequently,
complete Information sufficient for construction purposes is not
necessanly given. The Information has been carefully checked and IS
believed to be entirely rehable. However, no responsibility IS assumed for InaccuraCies Furthermore, such mformatlon does not convey
to the purchaser of the semiconductor devices described any license
under the patent rights of Motorola Inc., or others.

2-127

®

MC14412

MOTOROLA

CMOS LSI

•

ILOW.pOWER COMPLEMENTARY MOS)

UNIVERSAL LOW SPEED MODEM (0-600 bpsl
The MCl4412 contains a complete FSK IFrequency-Shlft KeYing)
modulator and demodulator compatible with both foreign IC.C.I.T.T.
standardsl and U.S.A. low speed 10 to 600 Ibps) communication networks.

UNIVERSAL LOW SPEED
(0-600 bps)
MODEM

• On-Chip Crystal Oscillator with External Crystal
• Echo Suppressor Disable Tone Generator
• Originate and Answer Modes
• Simplex, Half-Duplex, and Full-Duplex Operation
• On-Chip Sine Wave Generator

L SUFFIX

P SUFFIX

• Modem Self Test Mode
• Single Supply:
VDD=4.75 to 15 Vdc MCl4412FP, MCl4412 FL
VDD=4.75 to 6.0 Vdc MCl4412VP, MCl4412VL

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648

• Selectable Data Rates: 0-300, 0-600 bps
• Post Detection Filter
• TTL or CMOS Compatible Inputs and Outputs

M"#~

1

ORDERING INFORMATION

tSUfflX

Denotes

L Ceramic Package

P Plastic Package
F 4.75 to 15 Vdc
V 4.75 to 6.0 Vdc

BLOCK DIAGRAM

OSCout

3

Osc 1n

4

Transmit Carner

Transmit

Enable

IFSK Output)
12

Transmit

Data
Mode 10
Type 14
Echo 13
TTL Pull Up 15
Disable

Receive Data Rate

Receive
Carner

60-"'-f---I-I~-------.t

Reset 5 c>-<~-r-..J
Receive Data 700.....-f---I-IH
VDD= Pin 16
VSS=PlnB
Self Test

20-...- - - - - - - - - - - - - - - - - - - - - - - - - '

2-128

MC14412

ELECTRICAL CHARACTERISTICS
Characteristic
Output Voltage Pin 7 Only
"0" Level
VIn=VODorO
"1" Level
VIn=OorVDD

Symbol

VOO**
Vdc

VOL

5.0
10
15

VOH

-40'C
Min

+25'C

+85'C

Min

Typ

Max

-

Max
0.05
005
005

-

0
0
0

005
005
005

5.0
10
15

4.95
995
14.95

-

4.95
995
1495

50
10
15

-

50
10
15

-

15
30
40

-

-

-

Min
-

-

Max
005
005
005

Unit

V

-

-

-

495
995
1495

225
450
675

15
30
40

-

15
30
40

VDD-08
35
70
110

VDD-2
275
550
825

-

VDD-O 85
35
70
110

-

-05
-05
-15

-15
-10
-36

-035
-035
-11

-

20
45
13

40
10
35

-

16
36
10

-

mA

-

V

-

Input Voltage"
"0" Level
1Vo=4.50rO.5VI
1VO=9.0 or 1.0 VI
1VO= 13 5 or 1.5 VI
"1" Level
Pin 15
IVO=0.5 or 4.5 VI
IVO=10or90VI
IVo=150r135VI

VIL

VIH

-

5 to 15 VDD-O 75
50
3.5
10
70
15·
110

-

-

V

V

-

Output Dnve Current

Pin 7 Only
IVOH=251
IVOH=9.51
IVOH= 13 51

IOH

IVOL =041
IVOL =051
IVOL=151

IOL

Input Current

IP,n 15= VDDI
Input Pull~Up ResIstor

5
10
15
475
10
15

-062
-062
-18
23
53
15

-

lin

-

-

-

-

± 000001

±01

-

-

~A

Ip

5

285

-

250

460

-

205

-

~A

Cin

-

-

-

-

-

-

pF

40
12
25

35

IT

50
11
40
80

-

45
13
27

-

-

5
10
15

ACC

5 to 15

-

-

-

05

-

-

-

%

V2H

5
15

-

-20
-25

- 25
- 32

-

d8

-

Vout

-

02
05
10

030
085
15

-

-

-

5
10
15

-

mA

-

Source Current
I

(P,n 15= VSS,
Vin = 2.4 Vdcl
Pins 1, 2, 5, 6,10,11
12,13, 14
Input Capacitance

Total Supply Current
IPIn 15=VDDI

11

mA

23

Modulator/Demodulator
Frequency

Accuracy
IExcludlng Crystal!
Transmit Carner Output

2nd HarmOniC
Transmit Carner Output

Voltage IRL = 100 kill
IPIn 91
MaXimum Receive
Carner Rise and Fal!

Minimum Clock. Pulse

Width

-

-

VRMS

5
10
15

-

15
50
40

-

-

15
50
40

-

15
50
40

~s

-

fmax

5

-

-

12

5

-

-

-

MHz

tw

5

-

-

-

50

350

-

-

ns

tr,tf

Times IPIn 11
MaXimum Oscillator
Frequency

-

-

-DC NOise Immunity (VIL, VIH) IS defmed as thp. maximum voltage change from an Ideal "0" or "1" mput level. that the Circuit Will withstand
before accepting an erroneous Input

""Note Only 5-Volt specificatIOns apply to MCl4412VP deVices

2·129

•

MC14412

MAXIMUM RATINGS IVoltages referenced to VSS Pin 81
Rating
Symbol
DC Supply Voltages
MC14412FP. FL
VDD
MC14412VP. VL
Input Voltages. All Inputs

•

DC Current Drain per Pin lexcept Pin 8. 71
DC Current Drain !Pin 8. 71
Operatmg Temperature Range
Storage Temperature Range

Value

Unit

-05to 15
-05 to 6.0

V

VDD+0.5 to
VSS-0.5
10
35
-40 to +85
-65 to + 150

Vin
I
I
TA
Tstg

V
mA
mA
°C
°C

ThiS deVice contains circUitry to protect the
Inputs agamst damage due to high static

voltages or electric fields; however, It IS advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to thiS high Impedance CircUit. For proper operation it IS
recommended that V In and Vout be constrained to the range Vsss (Vin or

VoutlsVDD·
Unused Inputs must always be tred to an

appropriate logic voltage level le.g .• either
VSS or VDDI.

PIN ASSIGNMENT
Rx Car

Ie

ST
OSCout

16 VDD
15 TTLD

3

14 Type

OSCin 4

13 Echo

Reset

12 Tx Enable

5

Rx Rate 6

11 Tx Data

Ax Data

10 Mode

VSS 8

g Tx Car

DEVICE OPERATION
GENERAL
Figure 1 shows the modem in a system application. The
data to be transmitted IS presented In serial format to the
modulator for conversion to FSK signals for transmission
over the telephone network. The modulator output is buffered/ amplified before driving the 600 ohm telephone line.
The FSK signal from the remote modem is received via the
telephone line and filtered to remove extraneous signals such
as the local Transmit Carner. ThiS filtering can be either a
bandpass which passes only the deSired band of frequencies
or a notch which rejects the known Interfenng signal. The
deSired signal IS then limited to preserve the axis crossings
and fed to the demodulator where the data is recovered from
the received FSK carrier.
INPUT/OUTPUT FUNCTIONS
Figure 2 shows the I/O interface for the MC14412 low-

2-130

speed modem. The following is a description of each indiVidual signal.
TYPE (Pin 14)
The Type Input selects either the U,S. or C.C.I.T.T, operational frequencies for both transmitting and receiving data.
When the Type input= "1", the U.S. standard is selected
and when the Type input="O", the C.C.I.T.T. standard IS
selected.
TRANSMIT DATA (Tx Data, Pin 11)
Transmit Data IS the binary information input. Data
entered for transmission is modulated using FSK techniques.
When operating in the U.S. standard IType="1") a logic
"1" input level represents a Mark or when operating in the
CCITT standard IType= "0") a logic "1" input level
represents a Mark.

MC14412

-

FIGUAE 1 - TYPICAL LOW-SPEED MODEM APPLICATION
Transmit Data

Parallel Format

r -----

I
I

I
Tx Data

I

Modulator

111

19

I

Telephone
Network

Ouplexer

t

FSK
Format

Bandpass

Ax
11 Car

Demodulator

I

Filter
and Limiter-

I

L -- -

Receive Data
Parallel Format

Tx
Car

I
I
I

MCl4412

I
Ax Data

.--

I

I
I
Terminal
Receiver

Data Flow

-,

__ .-.1

Since the modulator and demodulator sections of the MCl4412 are
functionally equivalent to those of the MC686Q, additional application
Information can be obtained from the following Motorola publlca~

tlons'
AN-731
AN-747

Low-speed Modem Fundamentals
Low-speed Modem System Design USing the MC6860
ApplicatIOn Performance of the MC6860 MODEM.

EB-49

FIGUAE 2 -

'CAYSTAL SPECIFICATION
Crystal Mode - Paraliel
Frequency - 1 MHz ±O 1%
AS =540 II typ
Co =7 pF typ
Temperature Aange -40'C to +85'C
Test Level - 1 mW
Suggested Crystal Suppliers
Tyco. CTS Knight and
Motorola Crystal Products

MC14412 INPUT/OUTPUT SIGNALS

10 MHz
Crystal

r

o

4

It-

AF

11 Osc,"
Tx Data
12 Tx E
13
Echo

3
USCout
Tx Car

9

Modulator

--------

AF=15 mll±20%
To
Data Terminal

Equipment

10 Mode
14 Type
15 TTLD

Control

Network

2 ST
7

--------

Ax Data
6
Aa Data Aate
5
Reset

2-131

To
Telephone

Ax Car

1

Demodulator

•

MC14412

•

TRANSMIT CARRIER (Tx Car, Pin 9)
The Transmit Carrier is a digital-synthesized sine wave
derived from a '.0 MHz oscillator reference. The Tx CAR has
an AC output impedance of 5 kD typical. The frequency
characteristics are as follows:
United States Standard
Type="'"
Echo = "0"
Mode
Originate
Originate
Answer
"0"
"0"
Answer

"'"'""

Tx Data
Mark
Space
"0"
Mark
"0"
Space

"'"
"'"

Tx Car
'270
'070
2225
2025

Hz
Hz
Hz
Hz

disabling line echo suppressors. During normal data
transmission, this input should be low= "0".
RECEIVE DATA (Rx Data, Pin 7)
The Receive Data output is the digital data resulting from
demodulating the Receive Carrier.
RECEIVE CARRIER (Rx Car, Pin ,)
The Receive Carrier is the FSK input to the demodulator.
This input must have either a CMOS or TTL compatible logic
level input (see TTL pull-up disable) at a duty cycle of 50%
± 2%, that is a square wave resulting from a signal limiter.
RECEIVE DATA RATE (Rx Rate, Pin 6)
The demodulator has been optimized for signal to noise
performance at 300, and 600 bps.

C.C.I.T.T. Standard
Type="O"
Echo= "0"
Mode
Channel
No. ,
Channel
No. 2

"'"
"'"

"0"
"0"

Tx Data
Mark
Space
"0"
Mark
Space
"0"

"'"
"'"

Tx Car

980 Hz

"80 Hz
'650 Hz
'850 Hz

SELF TEST (ST, Pin 2)
When a high level (ST = ",") is placed on this input, the
demodulator is switched to the modulator frequency and
demodulates the transmitted FSK signal.
RESET (Pin 5)
This input is provided to decrease the test time of the chip.
In normal operation, this input may be used to disable the
demodulator (Reset= ",") - otherwise it should be tied
low= "0". The reset pin does not reset Rx data pin 7.
CRYSTAL (Osein, OSCout, Pin 4, Pin 3, respectively)
A '.0 MHz crystal is required to utilize the on chip
oscillator. A 1.0 MHz square wave clock can also be applied
to the OSCin input to satisfy the clock requirement (see
Figure 21.
When utilizing the '.0 MHz crystal, external parasitic
capacitance, including crystal shunt capaCitance, must be
< 9 pF at the crystal Input (Pin 4). Pin 3 is capable of driving
only one CMOS input.

TRANSMIT ENABLE (Tx Enable, Pin '2)
The Transmit Carrier output is enabled when the Tx
Enable input= "'''. No output tone can be transmitted when
Tx Enable = "0".
MODE (Pin '0)
The Mode input selects the pair of transmitting and
receive frequencies used during modulation and demodulation. When Mode = ",", the U.S. originate mode is selected
(Type input= ",") or the C.C.I.T.T. Channel No. , (Type input="O"1. When mode="O", the U.S. answer mode is
selected (Type input="''') or the C.C.I.T.T. Channel No.2
(Type input= "0"1.

TTL PULL-UP DISABLE (TTLD, Pin 15)
To improve TTL interface compatibility, all of the inputs to
the MODEM have controllable P-Channel devices which act
as pull-up resistors when TTLD input is low ("0"). When the
input is taken high (",") the pull-up is disabled, thus reducing power dissipation when interfacing with CMOS. Pin '5
should be taken high (",") with VDD greater than 6 volts.

ECHO (Pin '3)
When the E9ho input="'" (Type="O", Mode="O", Tx
Data = ",") the modulator will transmit a 2'00 Hz tone for

FIGURE 3 - M6800 MICROCOMPUTER FAMILY BLOCK DIAGRAM

Telephone
Network
Address Data
Bus

Bus

2-132

MC14412

FIGURE 4 - TRANSMIT CARRIER SINEWAVE

•
Time

FIGURE 5 - TYPICAL TRANSMIT CARRIER FREQUENCY SPECTRUM

-20

m
D

c

-40

c'B

Frequency
Harmonic

2-133

®

MCl4413-1
MCl4413·2
MCl4414-1
MCl4414-2

MOTOROLA

CMOS LSI
PULSE CODE MODULATION SAMPLED DATA FILTERS

•

(LOW-POWER COMPLEMENTARY MOS)

PULSE CODE MODULATION
SAMPLED DATA FILTERS

The MC14413-1, -2 and MCl4414-1, -2 are sampled data, switChed
capacitor filter I Cs intended to provide the band limiting and signal
restoration filtering necessary in PCM Codec voice digitization systems.
Both ICs are capable of operating from either a single or split power
supply and can be powered-down when not in Lise. Included on both
chips are two totally uncommitted op amps for use elsewhere in the
systems as I to V converters, gain adjust buffers, etc.
•
•

Transmit Band-pass and Receive Low-pass (MCl4413.1, -2)
Transmit and Receive Low-pass (MCl4414-1, -21

fid~
,10nnr If
1~~n( ~ I
1111

16

• 03/04 Specifications (MCl4414-2/13-2)
• CCITT Specification (MCl4414-1/13-1)

1

•
•
•
•
•

Low Operating Power Consumption - 30 mW (Typical)
Power Down Capability - 1 mW (Maximum)
Single Supply Capability when Used with MCl4404/617 Codecs
±5 to ±8 Volt Power Supply Ranges
Receive Filter Compatible with 15% to 100% Duty Cycle PAM Inputs
with Sinx/x Correction
• No Precision Components Required (MCl4413-1, -2)
• TTL Compatible Inputs Using VLS Pin
• Two Operational Amplifiers Available to Reduce System Component
Count

BLOCK DIAGRAM

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648

PIN ASSIGNMENT
VAG

Txl

LPO (MC14414)

::~

TxO (MC14413)

:v
AO

+B

1r 11

u

VAG

+

RxO

Rxl

VOO
VSS

MSI

CCI

VLS

2-134

Ii'i'-'"i6

VOO

+A

2

15

-A

3

14 RxO

Rxl

AO

4

13 Txl

BO! 5

12

LPO/TxO

-B16

11

CCI

+B17

10 MSI

VSSI8

9 VLS

MC14413·1, MC14413·2, MC14414·1, MC14414·2
MAXIMUM RATINGS (Voltages referenced to Vssl
Rating
DC Supply Voltage
Input Voltage. All Pins

Svmbol

Value

Unit

VDD-VSS

-0.5 to 18

V

DC Current Drain per Pin (Excluding VDD. VSSI

Yin
I

Operating Temperature Range

TA

Storage Temperature Range

0.5 to VDD + 0.5 V
10
mA

-40 to 85
-65 to 150

Tstg

°C
°C

This device contains circuitry to protect
the Inputs against damage due to high static
voltages or electric fields; hovvever, It IS
advised that normal precautions be taken

to avoid application of any voltage higher
than maximum rated voltages to this high
impedance circuit. For proper operation it
is recommended that V in and V out be
constrained to the range VSS "'- (Vin or

RECOMMENDED OPERATING CONDITIONS
Parameter
DC Supply Voltage
Convert Clock Frequency
Master Sync Frequency

Symbol

Min

Typ

Max

Unit

VDD-VSS
CCI

10

12

50

128

16
400
32

kHz

MSI

-

8

V

Vou,1 '" VDD·
Unused inputs must always be tied to an
appropriate logic voltage level le.g., either
VSS or Vaal.

kHz

DIGITAL ELECTRICAL CHARACTERISTICS IVSS =0 VI
Symbol

Characteriatic
Operating Current

100
IpD

Power-Down Current IPDI-VSSI

VDD
Vdc
12
12

DOC
Min

Max

Min

25°C
Typ

Max

-

5.0

-

2.0

4.3

-

5.0

mA

50

-

10

40

-

50

~A

5.0

7.5

-

-

pF

V

12
Cin
MODE CONTROL LOGIC LEVELS

Input Capacitance

VLS Power-Down Mode
VLS TTL Mode
VLS CMOS Mode
VAG Power-Down Mode
VAG Analog-Ground Mode

86°C
Min Max

Unit

VIH

12
15

11.5
14.5

-

11
14

11
13

-

11.5
14.5

-

-

12
15

2
2

9.0
11.0

2.0
2.0

9
12.0

2
2

9.0
11.0

VIL

12
15

-

0.8
0.8

-

-

0.8
0.8

-

0.8
0.8

VIH

12
15

11.5
14.5

-

11.5
14.5

10.5
13.5

-

11.5
14.5

-

VIL

12
15

-

9.0
12.0

-

-

9.0
12.0

-

9.0
12.0

V

-

±0.00001

±0.3

-

±1.0

~A

50
-0.00001

100
-0.3

-

-

200
-1.0

~A

-

5.25
6.75

3.60
4.0

-

-

9.0
11.5

6.75
8.25

-

-

-

±O.ooool

±0.3

30

-

-

-

V

V
V

CMOS LOGIC LEVELS (VLS = VSSI
Input Current CCI
Input Current M SI
(Internal Pulldown Resistorsl

"1" Level
"0" Level

Input Voltage CCI. MSI

"0" Level
"I" Level

lin

12

lin

12
12

VIL

12
15

VIH

12
15

-

±1.0

200
-1.0

-

-

-

-

-

-

-

V
V

TTL LOGIC LEVELS IVLS=6 V. VSS=O VI
Input Current CCI
Input Current MSI
(Internal Pulldown Resistorl
Input Voltage CCI. MSI

"I" Level
"0" Level
"0" Level
"I" Level

lin

12

-

±1.0

lin

12
12

-

200
-1.0

VIL
VIH

12
12

-

-

2-135

VLS+2.0

-0.00001

-0.3

-

VLS +0.8

-

-

-

±1.0

~A

200
-1.0

~A

-

V

-

•

MC14413·1, MC14413·2, MC14414·1, MC14414~2
ANALOG ELECTRICAL CHARACTERISTICS IVDD= 12 V )
I

Input Current

Input Current
AC Input Impedance II kHz)

•

Symbol

Characteristic

Input Common Mode Voltage Aange
Output Voltage Aange
IAL =20 kO to VAG)
IAL =600 0 to VAG)
IAL =900 0 to VAG)
Small Signal Output Impedance 11 kHz)

Output Current
IVO=ll V)
IVO=lV)

O°C
Min Max

25°C
Typ

Min

86°C
Max

Min

-

±3O
±1.0

p.A
MO

VAG
Axl, Txl
Axl, Txl

-

±3O

-

-

±10

lin

-

-

±1.0

lin

1.0

-

1.0

±O.OOOOI
2.0

-

1.0

Txl, Axl

VICA

-

-

1.5

-

10.5

-

-

VOA

1.5
2.0
1.5

10.5
9.3
10.5

1.5
2.0
1.5

-

10.5
9.3
10.5

1.5
2.0
1.5

10.5
9.3
10.5

TxO IMCI4413)
LPO IMCI4414)
AxO

Zo

-

-

-

-

-

-

TxO, LPO, AxO
TxO, LPO, AxO

10H
10L

-5
5

-

-5
5

-

lin

Unit

Max

p.A
V

TxO, LPO, AxO

-

-

50
50
50

-

-5
5

-6.0
7

-

V

0

mA

OP AMP PERFORMANCE IVDD- VSS= 12 V)
O°C
Min Max

Characteristic

Min

25°C
Typ

Max
±70

-

±80

-

-

-

-

-

Input Bias Current

-

-

-

45
±0.1

Output Voltage Aange
IAL =20 kO to VAG)
IAL =600 0 to VAG)
IAL =900 0 to VAG)
Output Current

-

-

1.5
2.0
1.5

-

5.1
-5.1

7.0
-7.0

-

0

-

-

-

2

Input Offset Voltage
Open Loop Gain

lL - 600 0 + 200 pF to VAG

VOH 10.5
VOLO.5

Output Noise
Slew Aate

-

-

+80

Unit
mV
dB
p.A

10.5
9.3
10.5

-

86°C
Min Max

-

-

-

5.1
-5.1

mA

0

dBrncO

-

V/"s

3

-

V

-

-

RECEIVE FILTER SPECIFICATIONS
IVDD-VSS=12 V, CCI=128 kHz, MSI=8 kHz, Includes sinxlx correcllOn Vin= -10 dBmO full scale= +3 dBmO 7 V p-p)
Characteristic
Gain 11020 Hz)

O°C
Min Max

Min

25°C
Typ

Max

-0.3 0.30

-

±0.2

-

Aelative to 1.02 kHz@OdBmO -0.15 +0.15 -09
Out of Band Aejection Aelative to 1.02 kHz@OdBmO
MCl4414/13-1
3400Hz
MCl4414/13-2
- -1.5 -14
4000 Hz-4600 Hz
- -14.2
4600 Hz-64 kHz
-30
-28
Output NOise IAXI=VAGI
ref to 9000
Pass-band Alpple 150 Hz to 3000 Hzl

-

Dynamic Aange
Absolute Delay Difference
1150 to 2300 kHz Delay
1000 to 2600 kHz Delay
800 to 2700 kHz Delay

-

Crosstalk 0 dBm@3 kHz
Power Supply AeJection Aatio VDD= 12 V+O.l Vrms@l kHz

2·136

86°C
Min Max
-0.30 0.30

-0.15 +0.15
±0.08 -0.5 -0.9
-09
-0.8 -1.5
- -1.5
-15.5 -14
-

-33

-

Unit
dB
dB

dB

-

8

12

-28
-

-

dBrncO

-

81

83

-

-

-

dB

22

-

-

12
25
31

22
35
41

-

35
41

-

76

-

40

-

-

-

35
41

-

22

P.s

d8
dB

MC14413·1, MC14413·2, MC14414·1, MC14414·2
TRANSMIT FILTER SPECIFICATIONS IVDD- VSS-12
kHz MSI-8
- kHz V 1
n- -10 dBmO full scale- +3 dBmO 7 Vp pi
- V CC-128
ODC
86 DC
25 DC
Unit
Characteristic
Min Max Min Typ Max Min Max
MCl4413·1. ·2 -0.3 +0.3
MCl4414-1 ·2 -0.25 0.25

Gain 11020 Hz)
Pass·band Ripple
1300 Hz to 3000 Hz)

RelatIVe to 1.02 kHz@O dBmO

ReJection
50 Hz 1Relative to 1.02 kHz)
60Hz
180 Hz
3400 Hz

MCl4413·1. ·2 Only
MCl4413·1. ·2 Only
MCl4414·1/13·1
MCl4414·2113-2

4000 Hz-4600 Hz
4600 Hz-64 kHz
Output Noise
1300 Hz-34OO Hz)

MCl4413·1. ·2
MCl4414-1. ·2

Dynamic Range
17V p-pMaxl

MCl4413·1. ·2
MCl4414·1. ·2

Absolute Delay Difference
1150 to 2300 kHz Delay
1000 to 2500 kHz Delay
800 to 2700 kHz Delay
Crosstalk
Power Supply Rejection Ratio

-0.15

RXO. TXO
VDD= 12V+0.l VRMS@l kHz

±0.2
1+0.15

-

-0.3 +0.3
-0.25 0.25

dB

-

±O.OB

-

-0.15 0.15

dB

-26
-22

-28

-

-24
-22

-

-

-

-O.B
-0.8
-1.5

-14
-32

-

-

15
12

dBrneD

-

-

dB

35
41

-

22
35
41

76

-

-

40

-

-

-

-24
-22

-

-

-

-OB
-O.B
-1.5

-14
-32

-

-

15
12

-

10
7

15
10

-

7B
81

84
87

-

22
35
41

-

12
25
31

-

-

-

OdBm@3kHz

0.15

-

-

-

-25
-0.3
-0.5 -O.B
-0.6 -1.5
-14 -15.5 -32 -33
-

-

22

dB

I'S

dB
dB

SWITCHING CHARACTERISTICS IVDD - VSS = 10 V)
Symbol

Characteristics

o to 70 DC
Min

Typ

Max

Units

Input Rise Time
Input Fall Time

CCI.MSI

tTlH
tTHl

-

-

4

Pulse Width

CCI.MXI

tWH

200

-

-

ns

CCI

fCl

50

-

500

60

kHz
%

tsu

-30

-

+3.0

I's

Clock Pulse Frequency

40

CCI Duty Cycle
Setup Time
MSI Rising Edge to cel RISing Edge ICCI= 128 kHz)"

-

"Specifications assume use of 50% duty cycle for clocks.

CCI

MSI

2·137

I's

•

MC14413·1, MC14413·2, MC14414·1, MC14414·2
FUNCTIONAL DESCRIPTION OF PINS
Pin 1 - VAG (Analog Ground)

Pin 10 - MSI (Master Sync Input)
This pin should receive a low-to-high transition concurrent
with each new PAM sample received at the receive filter input, ADI. A new transmit filter output sample will be
presented 8 CCI clocks after this.

This pin should be held at approximately (VDD-VEElI2. All
analog inputs and outpus are referenced to this pin. If this
pin is brought to within approximately 1.0 V of VDD, the
chip will be powered down.

•

Pin 11 - CCI (Convert Clock Input)
Normally, a 128 kHz clock signal should be applied to this
pin to operate both filters at fo = 3100 Hz. For other break frequencies use the following equation: fo = 0.02422 f clock.

Pin2-+A
Noninverting input of op-amp A. .
Pin3--A
Inverting input of op-amp A.

Pin 12 - TxO (Transmit Band-pass Output-MCI4413-1, -2)
This is the output of the transmit band-pass filter. It is
100% duty cycle PAM at 8 kHz.

Pin4-AO
Output of uncommitted op-amp A.
Pin5-BO
Output of uncommitted op-amp B.

Pin 12 - LPO (Transmit Low-pass Output - MCI4414-1, -2)
ThiS is the output of the transmit low-pass filter. It IS 100%
duty cycle PAM at CCI frequency, normally 128 kHz.

Pin6- -B
Inverting input of op-amp B.

Pin 13 - Txl (Transmit Input)
This is the transmit-filter input.

Pin 7 - +B
Non-inverting input of op-amp B.

Pin 14 - RxO (Receive Output)
This pin is the output of the receive filter. It is 100% duty
cycle PAM at the same frequency as the CCI pin, normally
12B kHz.

Pin B - VSS
This is the most negative supply pin and digital ground for
the package.

Pin 15 - Rxl (Receive Input)
This is the receive filter input. It will accept 15% to 100%
duty cycle PAM at 8 kHz.

Pin 9 - VLS (Logic Shift Voltage)
The voltage on this pin determines the logic compatibility
for the cel and MSI inputs. If VLS is within 0.8 V of VSS,
the thresholds will be for CMOS operating between VDD
and VSS. If VLS is within 1.0 V of VDD, the chip will power
down. If VLS is between VDD-2 V and VSS+2 V, the
thresholds for logic inputs at CCI and MSI will be between
VLS +0.8 V and VLS +2.0 V for TTL compatibility.

Pin 16 - VDD
Nominally 12 volts.
NOTE: Both VAG and VLS are high-impedance Inputs.

PCM FILTER DESCRIPTION
Transmit Filter Description
The transmit filter in both the MCl4413-1, -2 and
MCl4414-1, -2 consists of a 5-pole elliptic low-pass section
operating at a sampling rate of 128 kHz. This filter provides
the band limiting necessary to prevent aliasing of the input
signal in the codec. Since the transmit filter itself samples at
a 128 kHz rate, its input (Txt) signal should be band limited to
124 kHz. If energy above 124 kHz could be present, a singlepole RC pre-filter should precede the transmit filter.
In addition to the low-pass section, the transmit filter of
the MCl4413-1, -2 incorporates a 3 pole Chebychev highpass filter to provide 50/60 Hz and 15 Hz rejection. Although
the MCl4414-1, -2 does not Include thiS filter, It can be externally realized uSing one of the on-board uncommitted op
amps as an active filter. This IS shown In Figures 10 and 11
Both the MCl4413-1, -2 and MCl4414-1, -2 can be used in
cascade to produce a sharper rollof!. This is especially useful
in testing the MCl4413-1, -2 since the 8 kHz PAM from the
Tx filter will be sampled and sinx/ x corrected by applying the
Tx output to the Rxl input and observing RxO.

band characteristic.
In normal use as a codec's receive filter, MSI will be an
8 kHz signal. With the MC14407 codec family, the filter MSI
is the same as the codec MSI. With other codecs, the MSI
signal is receive sync.
The MCl4414 may also be used in analog applications by
disabling the sinx/x correction. If MSI and CCI are tied
together, the receive filter has the same frequency response
as the transmit filter and a gain of 18 dB.
Timing And Synchronization
Timing and synchronization of the MCl4413-1, -2 and
MC14414-1, -2 are provided by the CCI and MSI inputs. A
128 kHz signal should be applied to CCI. An 8 kHz signal,
whose low-to-high transition coincides with a new output
sample from the PCM codec" should be applied to MSI. The
rising edges of theCCI and MSI Signals should be skewed no
more than 3.0 p.5 for proper operation.
Logic levels of these signals can be either TTL or CMOS
compatible, Choice of logic level can be user determined by
applying the appropriate voltage to the level shift control pin,
VLS·
Power Down
80th the MC14413-1, -2 and MC14414-1, -2 may be
powered down in either of two ways: by bringing VAG to
within 0.5 V of VDD or by bringing VLS to within 0.5 V of
Voo·
If used on a single supply with the MC1440617 PCM
Codec, the filter IC will power down automatically when the
codec does, since the codec raises its VAG pin to VDD in
power down. When used in a split supply configuration, the
circuit shown in Figure 7 may be utilized.

Receive Filter Description
The receive filter sections of the MCl4413-1, -2 and
MC14414-1, -2 are identical and are 5-pole elliptic low-pass
filters operating at a sampling rate of 128 kHz. These filters
are used to smooth the PAM output of the PCM Codec.
They are similar to the transmit low-pass sections with the
exception that they Include a 1/8 duty cycle 8 kHz presampler on their inputs (Rxll.
This circuitry resamples the codec's PAM output and
thereby ellecively eliminates the sinx/x distortion normally
associated with 15% to 100% B kHz PAM pulse trains and
eliminates the need to predistort the receive filter's pass-

2·138

MC14413·1, MC14413·2, MC14414·1, MC14414·2
FIGURE 1 - RECEIVE FILTER TYPICAL
AND GUARANTEED PERFORMANCE
IMCl4413-1, -2/MCl4414-1, -2, SINX/X CORRECTION INCLUDEDI

FIGURE 2 - RECEIVE FILTER TYPICAL
AND GUARANTEED PASS-BAND PERFORMANCE
(MCl4413-1, -2/MCl4414-1, -21

~

+0.1 5

0
iD
:2
.5

j

L~

j

... -20

J'"

-0.1 5

r-

-40

100

v
1.0.

-40

+0.15

."
iD
:2
.Ii

V

)

.$ -20

J

1k

FIGURE 4 - TRANSMIT FILTER TYPICAL
AND GUARANTEED PASS-BAND PERFORMANCE
(MCl4413-1, -2 AND MCl4414-1, -2 USING FIGURES 10 AND 111

FIGURE 3 - TRANSMIT FILTER TYPICAL
AND GUARANTEED PERFORMANCE
IMCl4413-1, -2 AND MCl4414-1, -2 USING FIGURES 10 AND 111

,
h

-0.15

I

I

V

100

.,~

fin, INPUT FREQUENCY 1Hz!

t,n, INPUT FREQUENCY IHzl

~

"

~

10 k

1k

,

100

1k

r'

~
1k

t,n, INPUT FREQUENCY (Hzl

fin, INPUT FREQUENCY IHzl

FIGURE 6 - TRANSMIT FILTER TYPICAL
AND GUARANTEED PERFORMANCE
(MCl4414-1, -21

FIGURE 5 - TRANSMIT FILTER TYPICAL
AND GUARANTEED PASS-BAND PERFORMANCE
(MCl4414-1, -2)

+0.15

LL

"

V- i\

I

.5 -20

)

-0.15

r-

-40

1k

."

",

"~
J

100

10 k

1k

lin, INPUT FREQUENCY IHzl

fin, INPUT FREQUENCY IHzl

2·139

•

MC14413·1, MC14413·2, MC14414·1, MC14414·2
FIGURE 7 - TYPICAL CIRCUIT CONFIGURATION
USING THE MC14407 CODEC AND MC14413-1. -2 FILTER
(SPLIT SUPPLYI

•

vout~

30k

Vin

O.l~FT TO.l~F

1
VAG
2 +A
3
-A
4 AO

-6

.+6

5 60
6

7

-6
+6

'"
±
'cO"
~

U
::;

8

128 kHz

..

Rx Data

u-

TxO

2000 pF
Rx Enable

U

Data Clock

~

12

CCl 11
MSl 10

"-

2000 pF
128 kHz

::;

27k

Tx Data

8 kHz

VLS 9

VSS

Tx Enable

-6

N C.

8 kHz
Power Down

-6

+6

14

11 COl
4700 pF

12

Iref

CO2
-6

1 ~F

FIGURE 8 - TYPICAL CIRCUIT CONFIGURATION
USING THE MCl4407 CODEC AND MC14413-1. -2 FILTER
(SINGLE SUPPLYI

+ 12

vout~

30 k

Vin

0.1 ~F

VDD

1 VAG

l.

2+A
3

-A

4 AO
5 60
0.1 ~F

6

-6

7+B
8 VSS

'±"

'"

16
VDD
Rxl 15

TxO 12

U

CCl 11
10
MSI

::;

Rx Data
2000 pF

Txl 13

cO

~

128 kHz

RxO 14

~

Rx Enable

U
::;

128 kHz

Data Clock
TOC 19
TOO 18

8 kHz
2.7k

VLS 9

-

N.C.

Tx Data

TOE 17
9 ~/A
10 ADO

'MSI

Tx Enable

16

8 kHz

POI 15

Power Down

11 COl
4700 pF

12 CO2

-

• Keep all capacitors as near to deVice pins as possible.

2·140

3:

FIGURE 9 - MOTOROLA CODEC FILTER EVALUATION BOARD

o
.....

V

"..
"..

.....
.:...

C5

W
CCI (128 kHzl

3:

R6
Channel Enable 18 kHzl

Rx

Data Clock: (1 544 or 2 048 MHzl

o.....
"..

"..
.....

w

R3
Rll

R4

~'N

Master Sync 18 kHz)

AO

3:

80

o.....

Tx

"..

"..
.....

"..

.:...

...
...
N
I

3:

o.....

01::0

"..

"..
.....

to

I\)

R6

Rll
R4

VAG
+A
-A
AO

C';'I

Cl, C2'
C3'
C5, C6'
C7, C4'
Rl
R2
R3
R4
R5
R6
R7
RB,
R11

VOO

Rxl

'"

RxQ

N

..:

Tx

• All capacitors should be as near to component pins as possible
-In nOIsy environments, R3-R6 should be 10 kO or less to minimiZe pickup

Vss

II

2000 pF
4700 pF
1 ~F
1 ~F
30k
27 k
237k
169 k
20 k
33 k
47k
10k

a

900

20%
20%
20%
20%
1%
1%
1%
1%
1%
1%
10%
10%
1%

MC14413·1, MC14413·2, MC14414·1, MC14414·2

TYPICAL END-TO-END CHANNEL PERFORMANCE FOR MOTOROLA
MCI4413-1, -2/14-1, -2-MCI4404/7 CODEC AND FILTER
MCI4407/13-2
SPECIFICATION BELL PUB 43801

•

MCI4404/13-1
SPECIFICATION CCITI G7.12

QUANTIZING DISTORTION
SINUSOIDAL INPUT
C MESSAGE WEIGHTED

QUANTIZING DISTORTION
PSEUDO RANDOM NOISE
3 kHz FLAT WEIGHTING

",40

40

"0

g3Q
.,

30

"6 20

20

a:

z

o

ic:

10

10

lO

OJ

cii
Input Level IdBml Referenced to 0 dBmO @ 1.02 kHz

Input Level IdBml Referenced to 0 dBmO @ 0.82 kHz

SINUSOIDAL GAIN TRACKING

PSEUDO-RANDOM NOISE GAIN TRACKING

Input Level IdBml Referenced to - 10 dBmO 0 82 kHz

Input LevelldBml Referenced to -10 dBmO @ 1 02 kHz

f';f~ -=:t: I
GAIN vs FREQUENCY, SINUSOIDAL

GAIN vs FREQUENCY, SINUSOIDAL

-0.3 dB

-0.3 dB

-1.8 dB
/7't+++-+---+---+--4-tH~oS"'+--l---l-

/7"I-+++-+-----if__-+--4i1i~.:4000 Hz Gain
Single Frequency SPUriOUS Response
In Band with Input 1 kHz @ 0 dBm
Out of Band with Input 0 to 12 kHz @ 0 d8m
Differential Delay Distortion
1150 to 2300
1000 to 2500
900 to 2700

FIGURE 10 -

>:33
>:30
>:27
>:22

16 dBrnoO
10 dBrncO

-60 dBmO

dB
dB
dB
dB

>33
>:30
>:27
>:22

dB
dB
dB
dB

s23 dBrncO
S 15 dBrncO
See Frequency Response

s -65 dBmOP
s -75 dBmOP
S - 50 dBmO

-

s -24 dB

-28 dB
-24 dB
±0.20 dB
-1.0 dB
-32 dB
< -62 dB
s -44 dB
s -32.5 dB

58 ~s
72 pos

s
s
>:
s
s

-

- 20 dB
±O 3 dB
- 30 dB
- 28 dB
-60 dB

s
>:
s
s

s -40 dB
s - 28 dB

s60

±O 5 dB
-1.8 dB
- 28 dB
-60 dB

s -40 dB
s - 25 dB

~s

s 100 ~s
s200 ~s

91 pos

FILTER SCHEMATIC FOR MCl4414-1, -2 WITH 60 Hz REJECT FILTER
R1

Cl
VTX-1
13
High Zin

7 V pop

12

.........------i.. ADI
C4

Tx Low-Pass

R4

VAG

LowZout

VRX

VAG

7V pop
14

Q

15

ADO

Ax Low-Pass
Cl, C2, C3
C4
R1
R2
R3
R4
*In nOIsy environments, R1-R4 should be 10 kO or less to minimiZe pickup

2·143

4700 pF

o 2 ~F
112kll
620 kll
223 kll
100 kll

±1%
-20% +80%
'!.W 1%
'!.W 1%
Y.W 1%
Y.W 10%

•

MC14413·1, MC14413·2, MC14414·1, MC14414·2
FIGURE 11 -

FILTER SCHEMATIC FOR MCl4414-1. -2 WITH 60 Hz REJECTION ANO 900 TERMINATION

Rl

13

•

tl

12

C4
ADI

Tx Low-Pass

Z,n=900 II
Vin Max= +3 dBm

R4

VAG
Zout=900 II
Vout Max+3 dBm

R9

14
R7

tl

15

ADO

Rx Low-Pass

Rl1

C1. C2. C3
C4
R1
R2
R3
R4
R5
R6
R7
RS
R9
RlO
R11

'In noisy enVIronments. Rl-RS should be 10 kll or less

FIGURE 12 -

4700 pF

o 2 ~F
236kll'!.W
294 kll '!.W
223kll'!.W
100 kll Y.W
200 kll '!.W
169 kll '!.W
24 kll '!.W
33 kll Y.W
1.Skll '!.W
90011 '!.W
~n~4W

±1%
-20% +60%
1%
1%
1%
10%
1%
1%
1%
1%
10%
1%
;%

TYPICAL 2-WIRE PORT INTERFACE USING MCl4413
r---~~----~~------------~-----------------VRX

RO
100 k

b.

Rx Low-Pass
14

Ring

15

ADO

~----------'---------VAG

~5_......_ _1"-f3

b.

Tx Band-Pass

12 ~ADI

R2

~~~~----~-----------------VTX

Rl

2·144

MC14413·1, MC14413·2, MC14414·1, MC14414·2
FIGURE 13 -

TYPICAL 4-WIRE PORT INTERFACE USING MCI4413
VRX

Rx Low-Pass

R3
14

Q

15

•

ADO

VAG
RO

Tx Band-Pass

13

12

~ADI

R2

Rl

Full Scale Voltage at TxO (LPO) Rxl

5 V pop

Port
Impedance
(RO)

Relative
Level

Rl

R2

R3

R4

600
900

4.16 dBr
2.4 dBr

161 k
198 k

100 k
150 k

23.9 k
51.8 k

100 k
100 k

6.2 V Pop,

+ 9 dBm

600
900

6.00 dBr
4.26 dBr

100 k
245 k

100 k
150 k

Short
18.5

Open
100 k

7.6 V POp,

+9

900

6.00 dBr

150 k

150 k

Short

Open

dBm

Interface to 2-w"e or 4-w"e ports uSing the MCI4413-1 ,-2 114-1, -2 IS shown In Figures 12 and 13, respectively The table above shows some
voltages typically used with the filter and the appropnate resIstor values for cases In whIch the codee/fllter OTL? IS less than or equal to the 0
dBm level. If the codec/fllter overload voltage IS greater than requIred for dBm levels In the load, the RxO output can be voltage divided by
two resIstors and the extra op amp used as a voltage follower

°

FIGURE 14 -

GENERATOR FOR 128 kHz IN SYSTEM USING 2.048 MHz CLOCK
3 ICs: MCl4520, MCI4013, MCl4069

8 kHz Sync

DC 2.048 MHz
VSS

CCI128 kHz

2-145

MC14413·1, MC14413·2, MC14414·1, MC14414·2
FIGURE 15 - 128 kHz FREQUENCY SYNTHESIZER USING 8 kHz INPUT

128 kHz Output

8 kHz Input

•

3

"

<{

~

u

0
Cl.

MCl4046B IPPU

"

(5
U

R1=12.5k
R2=250 k
R3=6.5 k
R4=9 k
C1 =0.001 ~F
C2=0.01 ~F

Vl
Vl

I

~

>

13

MCl4024 ICaunter)

9

5

R3

VSS RESET

>
11

7

8

VOO

2

14

R2

R4

+Voo
C2

-

FIGURE 16 - GENERATION OF 128 kHz IN SYSTEM USING 1.544 MHz CLOCK

Voo
3 ICo: MCl4520, MCl4013, MCl4572

8 kHz Sync

1.544 to 1.576 MHz

.------+----'
.--------i

128 kHz CCI

2·146

MC14413·1, MC14413·2, MC14414·1, MC14414·2
FIGURE 17 - TELEPHONY C-MESSAGE FILTER USING MCI4414-1, -2 FILTER
GNOo-----------------------------.---------------~------------o

Cl, C2, C3

Al
A2
A3

4700 pF
19.6 k
97.6 k
825 k

2%
1%
1%
1%

VAG, VLS connected to GNO
MSI, CCI connected to 134 kHz TTL clock
0.1 ~F, VDD to VAG and VSS to VAG
Ax Filter can also be used and will provide 18 dB of Input gain
VOO= +5 V, VSS= -5 V
NOTE: Op Amps A and B are the free op amps on the MCl4414-1, -2 filter.

o

/

-5

------.r----

.....

/

J

-10

ii

/

/

-15

s

j

/

-20

-25

/

-30

-35

100

/

V

"\

V

/

/
200

400

600

1k

FREDUENCY IH.)

2-147

2k

3k

4 k

I
3:
FIGURE 18 -

VDD

VAG

Rxl

+A

::

COB

N

....•
.1::00

Q)

if'

VSS

Analog
Output

.

w

.-

5

11
[

t
.-

r

Analog Input

""

o
.-

oELTAMoo VOICE DIGITIZER USING MC3417 AND MC14414-1,-2

J

VCC

-

+

C3

RxO

AAA

R9" "

S'

~

Txl

U

LPO

~

l

.J~ r---<

".l!

R4:
C5':::

-

MSI

-

VLS

T~

)0 R3

~

.A
R7

Cl "

"""
Rl

t- -

SYL

-==

I

1
-5

----

AAA

r

"Y"Rl0

~

r--

Encode! Decode

Clk

GC

~

Ref

:;;

r-

~

u

Bit Rate Clock
12 kHz to 32 kHz

DI

Digital Input

eOiN

AD

Vcc
2

3:

Digital Output

o
.-

,..-t

I

..

3:

o..:...

~

y"

w

~N

~

DO

VEE

,..-

,..-t

DTH

FIL

y

-

,..-o

R5~

E!O

~L~AAA2

:;;

CCI

~---H~r-

12

3:

j

)0
RS:

N

R6
128 kHz

-----

Cl
C2
C3
C4
C5
Rl
R2
R3
R4
A5
A6
R7
RS
A9
Al0

01 "F
0.01 "F
0.01 "F

033 "F
0.1 "F
9.1 k
51011
75 k
15 k
8.2 k
47 k
5.1 k
10 k
200 II
22 mil

20%
.20%

5%
5%
5%
5%
5%
5%
5%
5%
5%
5%

®

MCl4416
MCl4418

MOTOROLA

PER CHANNEL, ADDRESSABLE TIME SLOT ASSIGNER
CIRCUITS (TSACs)

MOS LSI

The MCl4416 and MCl4418 are per channel devices that allow
variable codee time slot assignment to be programmed through a serial
microprocessor pan (0-63 time slotsl' Both devices have Independent
transmit and receive frame syncs and enables. They also Include chip
select and clear to send signals which simplify system deSign.
The MCl4418 provides the additional addressing capability which
allows a parallel bus back plane In the channel group In addition, the
MCl4418 provides control bits which can be used for the power down,
ring enable and ring triP functions on a line CIrCUit.
The MCl4416 provides the ability to multiplex off hook signals for a
bank of TSACs
Both deVices are fabricated uSing the CMOS technology for reliable
low power performance The MCl4418 IS the full featured deVice produced In a 22-pln package The MCl4416 Without the addreSSing
capability IS offered In a 16-pln package
• Low Power
• 5-Volt Interface on Microprocessor Port

•

(LOW-POWER COMPLEMENTARY MOS)

TSAC
TIME SLOT ASSIGNER
CIRCUITS

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 736

PLASTIC PACKAGE
CASE 700

• 5-16 Volt Output LogiC Levels
• Independent Transmit and Receive Frame Syncs and Enables
• Up to 64 Time Slots Per Frame
• For Use With Up to 2 56 MHz Clocks
• Provides Power Down Control for Line CirCUitS
• Compatible With MCl4400/01/02/03/05 and MK5116 Codecs
• Provides the Ring Enable and Ring Trip Functions (MCl44181
• Allows Use of a Parallel Backplane for Line CirCUits Due to the
Hard Wired Address Feature IMCl44181

l SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648

• Off-Hook Multiplex Control (MCl44161
• CMOS Metal Gate for High Reliability
BLOCK DIAGRAM

DC

FST

FSR

PIN ASSIGNMENTS

MC14416
VCC

VOO

ClK

C1S

01

TXE

CS

RXE

OC2

OC1

OHO

OHI

PO

FSR

VSS

FST

VCC

VOO

CLK

CTS

A1

00

A2

01

01

TXE

AO

RXE

CS

OC1

A3

02

A4

R2

A5

FSR

VSS

FST

2-149

TXE
RXE

---

See FIgures 3 and 4

MC14416, MC14418
MAXIMUM RATINGS (Voltages referenced to VSSI
Symbol
Rating

•

Value

Un~

DC Supply Voltage

VDD

-0.5 to + 18

Vdc

Level Shift Voltage

VCC

-0.5 to VDD

Vdc

Input Voltage
Inputs Referenced to VDD
toVCC
DC Current Drain per Pin

Vinl
Vln2
I

-0.5 to VDD + 0.5
Vdc
-0.5 to VDD +0.5
10
mAdc

Dperating Temperature Range

TA

-40 to +85

Storage Temperature Range

Tstg

-65 to + 165

'c
'c

This device contains circuitry to protect the Inputs against damage due to high static voltages
or electnc fields; however, it IS advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper opera-

tion it is recommended that Yin and Vout be constrained to the range VSS:5 (V," or
Vout l :5VDD·
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or
VDDI.

ELECTRICAL CHARACTERISTICS (T A = 25'CI
Symbol

VOO

Min

Typ

Max

Un~

DC Supply Voltage

VSS=OV

VDD

-

4.5

12

16

V

DC Supply Voltage

VSS=OV

VCC

-

4.5

5

VDD

V

IOL

5
12

0.51
2.0
-0.20
-2.0

-

-

mAdc

4.0

Characteristic

Output CurrentTXE, RXE, 00, aI, 02, PO
(VOL =0.4 VI
(VOL=1.0VI
(VOH=4.6 VI
(VOH= 1.0 VI
Output Current CTS, OHO
(VOL =0.8 VI
(VOL =0.8 VI
(VOL = 1.5 VI
(VOH=0.8 VI
(VOH=2.0 VI
(VOH=0.8 VI
(VOH=2.0 VI
(VOH = 10.5 VI
Input Voltage (CMOSI
FST, FSR, R2, DC1, DC2, AI, A2
A3, A4. A5. OHI

5
12

IOL

5
12
12

IOH

"0" Level
"I" Level

Input Current OH I
(Active Pull Downl
Input Voltage (TTL!
CLK, CS, AD, DI

IOH

"a" Level

12.0
-8

-6
-40
-35
-15

VIL

5
12

-

VIH

5
12

4.0

linH

5
12

-4.0

-

5.5
11.5
20.0

-

-20
-18
-100

-90
-30

-40
-40
-200
-200

9.6
+1.5
+10

+4.0
+25

+15
+100

~Adc

VIL

5
12

-

0.8
0.8

Vdc

2.00
2.00

±10 5
5

±0.1

~Adc

7.5

pF

-

-

lin

15

-

Input Capacitance

Cln

-

-

IT

12
5

-

3
2

6

-

IpD

-

-

-

0.1

2-150

~Ade

1.0
2.4

VIH

DCl at 2.048 MHz

mAde

-

-

Input Current

Total Supply Current (Outputs Unloadedl
VDD=12V
VDD=5V
Total Supply Current (Power Downl MCl4418 Only
After CTS=VDD
CLK, CS, AD, DI Inputs :5 0.6 V

mAde

-60

5
12

VCC=5V

"I" Level

5
5
12
12
12

3.0

6.6

-

-

4

Vdc
Vdc

Vdc

mAde
mAdc

MC14416, MC14418

SWITCHING CHARACTERISTICS tCL = 50 pF T A = 25'C unless otherwise noted}
Characteristic
Output Rise Time
TXE, RXE,QO,Ql,Q2,
Output Fall Time
TXE, RXE,QO,Ql,Q2,

PO

PO

Min

Typ

Max

Unit

5
12

100
50

200
100

ns

-

5
12

-

100
50

200

1

5
12

-150
-75

-

1

5
12

200
100

-

-

1

5
12

130
80

180
125

ns

-

5
12

-

-

2.048
2.6

MHz

1

5
12

200
140

244
192

293
260

ns

0.3
0.3

MHz

tpWFS

DC to TXE, RXE INote 11

lPLHE,
tpHLE

Data Clock Frequency

foe

Data Clock Pulse Width lat fDCtMAX}1

tpWDC

Clock Frequency
Clock Pulse W,dlh lat fCLKIMAX}}
Address and Data Setup Time

DCl or FST to CTS
10K Pullup or EqUivalent
DC to PD
DC 10 QO-Q2
Propagation Delay - R to Q2

5
12

00
00

lpWC

2

5
12

0.5
05

-

-

-

-

2

5
12

300
300

-

-

2

5
12

200
200

-

-

2

5
12

-

250
150

2

5
12

-

-

300

-

200

2

5
12

-

300

2

5
12

tpCl
tpCH
lpQ
lpQ

tscs

Chip Select Hold Time
Failing CTS to Failing CS

tHCS

2
2
2

-

-

-

5

-

12

-

5

1
1

-

-

10

-

-

12
5
12

10

-

200

-

300

100
50

200
100

NOTE 1. For lime sial 0, lPHLE and tpLHE are measured from leading edge of DC or FST IFSR}, whichever occurs last

2-151

-

-

tp

Chip Select Setup Time
Leading CS to Failing CLK

-

100
+150
+ 75

fClK

th
DCl to CTS

-

-

tsu

Address and Data Hold Time

Propagation Delay

VOO

-

tSFS

Frame Sync Pulse Width

Propagation Delay

Fig.

tr
tf

Frame Sync Setup Time

Propagation Delay Cl =20 pF

Symbol

200

ns
ns
ns

,,"S

ns
ns
ns
ns
ns
ns
ns
,,"S

ns

MC14416, MC14418

FIGURE 1 - TIMING DIAGRAMS

DC

•

FST, FSR

NOTE: No restnctlon on failing edge.

DC

r-tPHLE
8 Data

TXE, RXE

2-152

CIOCkS---9--~", _____

:s:::

(')

.....
~
~
.....

s»
FIGURE 2 -

:s:::

PROPAGATION DELAYS FOR PROCESSOR INTERFACE PINS

(')

.....
t
.....

ClK

C»

CS
To Completion of
-

ProgrammIng Sequence

(Scale Changes)

DI, AD

N

....U1
I

'"

tr\

"

\r-

DCl

(0)

FST

PO (MCl44l6 Only)
00-02 (MCl44l8 Only)
tPCH
CTS

NOTE: tpCH

IS

measured from the rising edge of the latter of FST or DCl.

MC14416, MC14418

FIGURE 3 - MC1441a 22 PIN
A1

Vee

•

-Sl~m

I

6--81t Compare

t

t
5-81t Shift Reg

AD

22

10

20

3-Blt Reg

I

STr==

f
3-81t SA

I

e

14

15

19

EJ~~~C?

A5

es

L-........-- -

Address
Compare

elK

e~

'·'·"IT
a-Bit Shift Reg.

01

Q

"'~

~

'[=l1U
ST

21

:~
l~

CTS

Logic

'f

I
I

6-Blt Reg

ST

I

l

~
let'{
ST

ST

I
I

1
6·Blt Reg

~

Compare

Compare

in
~ 'il

1~
16

DC

1\

~

FSR

I

BrPGen

Strobe

"

~
Power Down
Latch

n-~

I

+64

2~ ~
3

+64

1

o--a

AX Compare

17

TX Reset

TX Compare

Strobe

F18
RX Reset

Gen

'r:
~

4

2-154

MC14416, MC14418

FIGURE 4 -

MCI4416 16 PIN

•

Voo

15

I--+-I--I--I-+-~

16[;]

6-81t Reg

STJ+-----+--+-+--+-++---+--f-{
Compare

c';;:m~\;:;a:;;re:f-t--+---------l

2-155

AXE

13

MC14416, MC14418

GENERAL DEVICE DESCRIPTION
The MCl4416 and MCl4418 TSACs are microprocessor
peripherals intended to be used to control and supervise per
channel codec subscriber channel units. The TSACs consist
of three basic functions.

•

The Serially Programmable Microprocessor Port consists
of VCC, ClK, DI, CS and CTS for the MCl4416 and further
includes AD and A 1 through A5 for the MCl4418. This port
allows the call processing microprocessor to access load
data into each TSAC. See the applications section for a
detailed description of the microprocessor port. Figure 5
defines the data word bit assignments.
The Supervision Controls consist of 00, 01, 02, R2 on the
MCl4418 and OHI, aHa and PD on the MCl4416. These
functions provide data path for the supervision and control
of user selected requirements in the subscriber channel unit.
Figure 3 shows some typical uses of these bits.

AD (Serial Address and Control Bits Input - MC14418 only) - 8-bit words are clocked into the device through AD
under the control of ClK after CS is brought high. AD words
are loaded in parallel with the 01 words. The first 3 bits of AD
program the control bits QO, Ql, and Q2 while the last 5 bits
are compared with the hardware address on A 1 through A5
to identify a specific TSAC in a bank. (See Figure 5 for the
format of the AD words.)
A1-A5 (Codec Address Inputs - MC14418 only) - These
five pins provide a unique identity for each TSAC. The TSAC
address pins are either hardwired on the PC board or in the
channel bank backplane. The processor loads the 5-bit address data into AD, and each MCl4418 in the selected bank
compares this data to the hardwired address set by its A 1-A5
to determine if the time slot data loaded into DI is intended
for that TSAC. By this process, only one of 32 TSACs in a
bank will accept the transmitted time slot data. Al-A5 are
CMOS inputs, logical "l"=VDD and logical "O"=VSS.

The Time Slot Computation section of the chip derives
separate transmit and receive time slot outputs ITXE and
RXE} for the controlled codec from the bit rate clock and
sync pins DC1, DC2, FST and FSR, respectively. The computed time slot is then derived from the information received
through the microprocessor port.

00, Ql, 02 (Status Bit Outputs - MC14418 Only) These three bits are programmed by the first 3 bits of the
8-bit word which is loaded into AD. The bits are used for the
basic control functions of a line circuit. See the applications
section (ref. Figure 11) for an example of how these status
bits are used. In this example, Ql selects to receive data
streams, QO is used for the power down control, and Q2 is
used for the ring enable. These are CMOS outputs.

PIN DESCRIPTIONS
VCC (Positive Supply for Microprocessor Port) - If this is
a 5-volt supply, AD, DI, CS and ClK are TTL compatible
CMOS inputs. VCC may be any voltage from 4.5 V to VDD
allowing either TTL or CMOS compatibility.

R2 (Reset Input for 021 - The R2 input provides a direct
reset of the Q2 output. When R2 is taken high, Q2 is set to
"0" independent of all other TSAC functions. See the applications section (ref Figure 111 for an example of how this
reset bit is used, i.e., the ring trip signal is used to reset Q2
which is the ring enable. This combination of R2 and Q2
allows a simple solution to the ring trip function.

CS (Chip Select Input) - For the MCl4418, the pin is used to select a bank of TSACs.
For the MCl4416, the CS is used to select that individual
TSAC. All CSs are normally held low. To PROGRAM A
SPECIFIC TSAC, CS must go high prior to the first falling
edge of ClK. CS must stay high until the selected CTS goes
low to guarantee a valid access.
CS is synchronous with DI, AD and ClK. CS can be asynchronouswith DC1, DC2, FSTor FSR.lThis pin is normally
intended to be set by a microprocessor.}
ClK (Microprocessor Clock Input) - Serial data is entered
through the AD and DI pins under the control of ClK. The
data is entered on the trailing edge of ClK. ClK is synchronous with CS, AD and DI and can be asynchronous with
the TSAC's data clocks (DCl or DC21.
01 (Serial TIme Slot Data and Mode Inpull - 8-bit words
are clocked into the device through D) under the control of
ClK after CS is brought high. The first 2 bits of DI control
the various programming modes while the last 6 bits are time
slot data. (See Figure 5 for the format of the DI word.)

CTS (Clear to Send Outputl - This output provides a simple diagnostic capability for the processor TSAC combination. The selected TSAC outputs the CTS signal after it has
accepted data. This output goes low three data clock cycles
afterthe next FST, and returns high on the subsequent FST.
For the MCl4418, only the TSAC which accepts transmitted
data will respond with CTS low. All other TSACs in the bank
will leave CTS high. The CTS output is an open drain transistor with a weak internal pullup. Normally a bank of CTS
outputs are wire ORed together to provide a single
diagnostic bus, which can be used to verify that transmitted
data was properly acknowledged by some TSAC in the bank.
CTS may also be used to strobe additional supervision
data into a selected channel unit, due to its dependence
upon the address selection logic of the MCl4418.
DC1, DC2 (Data Clock Inputl - The data clock input
establishes the bit rate of the TSAC and its associated
codec. It is intended to be between 1.536 and 2.56 MHz and
IS the same as the codec's bit rate clock. Both TSACs divide

2-156

MC14416, MC14418

these inputs by eight to derive the time slot rate. For the
MCl44l8, DCl provides the data rate clock for both transmit
and receive time slot computation. The MCl44l6 derives
transmit timing from DCl and receive timing from DC2. They
are CMOS compatible inputs.

and DC2 derive the receive time slot zero independently.
DCl and DC2 can be asynchronous. FSR and FST are
CMOS inputs.

TXE, RXE (Transmit Enable and Receive Enable Outputs)
- These are the outputs of the time slot computation circuitry. Each output is high for eight data clocks; i.e., an integral number of time slots alter the rising edge of FST and
FSR for TXE and RXE, respectively. The binary number
entered in the last 6 bits of the DI input indicates the number
of eight data clock intervals (time slots) between FST or FSR
and the eight data clock time slot, when TXE or RXE will be
high. These are CMOS B series outputs which will drive one
TTL LS input when VDD is five volts. SEl9 Figure 6 and
Figure 7 for detailed timing and numbering.

FST, FSR (Frame Sync Transmit and Frame Sync Receive
Inputs) - These Inputs are leading-edge sensitive synchronization pulses for establishing the position of time slot
zero in the transmit and receive frames, respectively.
The nSlng edge of DC (lor 2) associated with the rising
edge of FST or FSR identifies the sign bit penod of time slot
zero. See Figures 6 and 7 for detailed timing. In the
MCl4418, both zero time slots are derived from DCl but may
be different by an integral number of bits. In the MCl44l6,
FST and DCl derive the transmit time slot zero, while FSR

TABLE 1 -

BASIC OPERATION OF MCl441B

Input Conditions
TS Oata Address
Received Compare

bO

Action to Outputs After Next FST
bl

CTS

1
1
0
0
0
0

No

X

X

X

Yes

No

X

X

Yes

Yes
Yes

Yes

Yes

Yes

Yes

0
0
1
1

0

Yes

1

0
1

TX Reg. RX Reg.
Load
Load

bO

OataReg.
100-02)
Load

Time Slot
Counters
Running

No

No Change

No Change

No

No Change

No

No

No Change

No Change

No

No Change

Yes

Yes

No

No

Yes

Yes

Yes

No

No

No

Yes

Yes

No

Yes

No Change

No

Yes

Yes

X

Yes

Yes

Yes

Yes

No

BASIC OPERATION OF MCl4416

Input Conditions
CS

RXE
Disabled

No

TABLE 2 -

TXData
Received

TXE
Oisabled

Action to Outputs After Next FST
bl

CTS

1
1
0
0
0
0

No

X

X

X

Yes

0

X

X

Yes

1

0

Yes

1

0
0

1

Yes

1

1

0

Yes

1

1

1

TX Reg. RX Reg.
Load
Load

PO

TXE
Disabled

Output

No

No

No Change

No Change

No

No

No Change

No Change

Yes

Yes

No

1

Yes

No

No

No

Yes

No Change

No

No

Yes

1
1
0

Note 1: The OHO output remains operational when TXE is disabled.

2-157

II
iC

...o
...!»t
iC

....,...,..
...

o
FIGURE 5 -

FORMAT FOR 01 AND AD WORDS

MCl4418

01 Word Input

Results of Bit Pattern

ASSign TSAC 16 to the lirst time slot ITSO) for both receive and
transmit and set Its status bit to 011
ASSign TSAC 1 to time slot 8 for receIve only and set status

N

....UI
I

00

bits to 011
ASSign TSAC 8 to time slot 2 for transmit only and set status
bits to 011
Program TSAC 4 to Idle Ina time slot outputs) and set status
bits to 011
Codec 1 IS powered down 180 - 01
Line Circuit associated with cadee 2 IS programmed to nng the hne
ISee Fig, 13)

First Bit Sent
Time Slot
Data

Mode

ASSign the selected TSAC to time slot 8 for receive only and

set PD= 1
Ass~ the selected TSAC to time slot 2 for transmit only and
set PD= 1
Power down the selected TSAC, I.e , J5D to "0"

Address

Status
Bits

Data

bO

b1

t6

t5

t4

t3

t2

t1

q2

q1

'qO

a5

.4

.3

82

.i

0

0

0

0

0

0

0

0

0

1

1

1

0

0

0

0

1

0

0

0

1

0

0

0

0

1

1

0

0

0

0

1

0

1

0

0

0

0

1

0

0

1

1

0

1

0

0

0

1

1

X

X

X

X

X

X

0

1

1

0

0

1

0

0

X

X

X

X

X

X

X

X

0

1

0

0

0

0

Q

'I

X

X

X

X

X

X

X

X

1

1

1

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

o,

MCl4416

ASSign the selected T~C to the first time slot ITSO) for both receive
and transmit and set PD = 1

C»

AD Word Input

First Bit Sent

0

1

0

0

0

0

1

0'

1

1

X

X

X

X

X

X

"

·See Figures 12 and 13 for the hardware ImplementaMns uSing MCl4418 and MCl4416,

I

:s::
o
..".

oiloil-

..".

5»

:s::
o

..".

oiloil-

..".

FIGURE 6 -

DATA MULTIPLEX TIMING FOR 2.048 MHz

CD

Data Clock

2048 MHz

o

2
RX Data Clock Count

FST

FSR

s-----

_ _ _ _ _---'r
--~L-_ __

_ _- - - ' , - - - - .

I\)

....
I

C1I
CD

RXE Output

TXE Output

I

Programmed For Time Slot

-----'

Programmed For Time Slot 1

r

a

-lL________

rRX Data
(to Codecl

IromT~o~:~~

Time Slot 31-

~
L~TX
~. Time SIOI 0

.l-==!X~~'O~~f_---~

r - - - T X Time Slot 3 1 - - - 1

-..:....--------

I

II
s::

....o
:t
....

sn
s::
o....
~
~

....CD

FIGURE 7 - DATA MULTIPLEX TIMING FOR 1.644 MHz
TX Data Clock Count
Data Clock

0

1

2

3

4

2048 MHz

FST

a 1 2 3 4
AX Data Clock Count

J

Frame Bit Tlme~

_ u

__

-1L-_ _ __

_____

~

~r

------- ----,L--__

FSR

...
NI

c;,)

CI

1 Programmed For

RXE Output

TXE Output

Programmed For Time Slot 1

I

Time Slot 0

-- - - 1..________

rAX Data
(to Coded

,--_..
~TX

TX Data _.:....._ _ _ _ T,me
_ _Slota
_ _ __
/from CodecJ

AX Time Slot 24 -

~

-~X-.:r::m~'o~~~------~

~ TX Time Slot 24-----1

MC14416, MC14418
PO (Power Down Output - MCI4416 Only) The PO
output is normally high. It is set high whenever bO or bl is a
zero and the TSAC is programmed. If bO and bl are both
one, then PO will be set low. This output is intended to be
used to power down other circuitry in the channel unit when
the channel unit is idle. This is a CMOS B series output
which will drive one TTL LS load when VDD IS five volts.

VDD. Typically, these five pins are bused in parallel to 24 or
32 TSACs per processor port. If desired, AD, CLK, 01, and
CTS may be bused to greater than 32 TSACs by using the
CS input as a group select. A microprocessor port of eight
bits can thus control four groups of 32 TSACs with no additional decoding, as shown in Figure 8.
In order to program any given codec to a transmit or
receive time slot, the processor simply exercises the corresponding 8-bit port.
Beginning with CSl to CS4 low, all TSACs in the bank
have their data registers in the Ready for Data Mode. The
microprocessor takes the appropriate CS high and clocks in
two bits of data Into the 32 selected TSACs through 01 and
AD using CLK. The microprocessor presents data on the
leading edge of CLK and the TSACs clock in data on the
trailing edge of CLK. After eight CLK pulses (high, then lowl
the 32 selected TSACs will have two new 8-bit words; one in
the data register through 01 and one in the address register
through AD. The unique TSAC, whose last 5 bits of the address register match its hardwired address on A 1 through
A5, acknowledges the new data. After the next FST, the
selected TSAC will pull CTS low. ThiS event notifies the processor that its transmission has been recognized. If CTS occurs at any other time, the processor can recognize the fault
condition and restart the transmission using the reset function of the TSAC chip select. The uniquely selected TSAC
will load its new program data into the appropriate TIME
SLOT register on the next leading edge of FST. The bank of
32 TSACs will internally reset to the Ready for Data Mode
when the transmission is completed, after the next FST. The
TSAC, which was uniquely selected, and which has CTS
low, will clear CTS to the pulled-up condition with the next
FST. The processor may now program a new time slot immediately, with or without returning the selected CS low.
Time Slot data can thus be sent at the rate of once every
256l'sec. for 8 kHz sampling (FSTI. The processor need not
operate in an interrupt mode even though the TSAC's DC
and CLK are asynchronous.
The processor port of the MCl4416 works similarly to the
MCl4418, but will accept data if CS is high, and does not
compare a hardwired address to the address word.
Figure 11 shows the typical signal timing for programming
the microprocessor port.
To demonstrate the programming of the TSAC, consider
the following configuration. A microprocessor is used to
control four groups of thirty-two TSACs through an eight-bit
PIA port. Four of the PIA lines are used for group select
lines. The other four lines are dedicated to CLK, 01, AD, and
CTS. The TSACs are programmed by serially loading bits into the 01 and AD leads. Data bits are latched on the falling
edge of CLK. The PIA port is connected as shown In Figure
9. The flow chart in Figure 10 and the following program illustrate one method of TSAC programming.
Before running the following program, the address, time
slot, and group number must be entered in appropriate locations. During execution, CS (group selectl, AD, and 01
words are arranged for serial presentation to the TSACs. The
bits are presented with CLK high and are latched in with the
falling edge of CLK. After eight passes through the loop, the
TSAC is programmed, and CTS falls on the third data clock
pulse after the next FST. The program waits for CTS to go
high again before removing CS to prevent aborting the
TSAC's programming. This program allows a maximum rate
of programming equal to one TSAC per two frames.

OHI (Off Hook Input - MCI4416 Only) - The OHI is a
CMOS input with an internal pull-down resistor. A DC level
at this pin will appear at the OHO output during the programmed TXE time slot.
OHO (Off Hook Output Inverted - MCI4416 Onlv)
During the programmed transmit time slot, the data at OHI
appears inverte~OHO; otherwise OHO will be pulled high
passively. The OHO output is an open drain N-channel transistor with a weak pull-up to VDD. A number of these outputs can be wire ORed together to form a hook status bus
consisting of a serial stream of hook information from a bank
of channels. When the MCl4416 powers down its codec, the
TXE output IS disabled; but the OHO output continues to
multiplex out OHI and transmit time slot Information during
the previously entered transmit time slot.
Vss - This is the most negative supply pin and digital
ground for the package.
VDD - This is the most positive supply. VDD is typically
12 V with an operation range of 5 to 16 volts. All logic outputs swing the full supply voltage.

APPLICATIONS
The following section is intended to facilitate device
understanding through several application examples. Included are Data Multiplex Timing Diagrams, a description of the
TSAC Microprocessor port, a sample program, two circuit
configurations using Motorola's devices, a systems drawing
and two suggested clock circuits for obtaining codec data
and control clocks.
In Figures 6 and 7 are shown Data Multiplex Timing
Diagrams for 2.048 MHz and 1.544 MHz data clocks. The
major points to be seen from these examples are:
11 Receive and transmit programming for the MCl4418
are bit synchronous and word asynchronous. The
MCl4416 can be completely asynchronous.
21 The rising edges of FST and FSR initiate the programming frame for transmit and receive channels,
respectively, and identify transmit and receive time
slot "0," respectively.
3) Time slots identify eight data clock words. In this example: the transmit time slot is programmed as time
slot "1." Therefore, bits 8 through 15 after FST are
time slot "1."
4) For the 1.544 MHz clock, the framing bit IS at the
very end of the frame.
TSAC Microprocessor Port IMCI4418 and MCI4416) The MCl4418 provides four pins with S.volt microprocessor input characteristics. These are AD, CS, CLK,
and 01. The input supply for these inputs is V CC. The
CTS output is an open drain device with a weak pull up to

2-161

•

MC14416, MC14418

FIGURE 8 - TYPICAL 8-81T PORT

eLK

•

DI
AD
8-Bit CTS
PIA CS1
Port CS3

CS2
CS4

TSAC

a

- --

'---

TSAC
31

TSAC
32

'--'--

'---

-

--

TSAC

TSAC

63

64

'---

'---

FIGURE 9 - PIA PORT ASSIGNMENT

--

95

~

1

1

TSAC

96

'-----:-

-

--

TSAC
127

'---

FIGURE 10 - TSAC PROGRAMMING FLOW CHART

ClK
Group 1 Select

PIA

-

TSAC

Group 2 Select
Group 3 Select
Group 4 Select

AD
DI
CTS

2-162

MC14416, MC14418

Instructions for use.

load In AD word 102, 01, 00, A5, A4, A3, A2, All
DI word lbO, bl, t6, t5, t4, t3, t2, tl1
group word
Start routine.

ONE

TWO

THREE
START

WAIT

lOOP

ISITLO

LDAA GROUP
DECA
BNE ONE
lDAB 103
STAB SELECT
BRA START
DECA
BNE TWO
LDAB 105
STAB SELECT
BRA START
DECA
BNE THREE
lDAB 109
STAB SELECT
BRA START
lDAB '11
STAB SELECT
LDAA #00
STAA CONTRlB
lDAA I7F
STAA DDRB
lDAA '04
STAA CONTRlB
lDAB 180
BITB PIAOUT
BEO WAIT
lDAA 101
STAA PIAOUT
lDAA lOB
ST AA COUNTER
lDX 00
STX 02
lDAA SELECT
STAA PIAOUT
lDAA SELECT
ROl0002
BCC 02
ORAA 20
ROl0003
BCC 02
ORAA 40
STAA PIAOUT
DECA
NOP
NOP
STAA PIAOUT
DEC COUNTER
BNE LOOP
lDAB 180
BITB PIAOUT
BNE ISITlO
ClR PIAOUT
RTS

STORE GROUP' IN ACCA
CHECK IF EO. TO ONE
IF NOT GO TO NEXT TEST
EOUAlS ONE
lOAD PROPER SELECT BITS IN SELECT WORD
JUMP TO NEXT PART
IS GROUP EO. TO TWO?
IF NOT GO TO NEXT TEST
lOAD PROPER SELECT BITS IN SELECT WORD
JUMP TO NEXT PART
CHECK IF EO TO THREE
IF NOT IS EO. TO FOUR
lOAD PROPER SELECT BITS IN SELECT WORD
JUMP TO NEXT PART
lOAD GROUP SELECT BITS FOR GROUP FOUR
INITIALIZE PIA
INITIALIZE PIA
INITIALIZE PIA
INITIALIZE PIA
INITIALIZE PIA
INITIALIZE PIA
TEST FOR CTS HIGH
WAIT FOR CTS HIGH
NOW CTS IS HIGH, SET ClK HI AND lEAVE CS lOW
INITIALIZE lAP COUNTER
MOVE AD AND DI INPUTS
TO SHIFT lOCATIONS
BRING CS HIGH
START BIT STUFFING
CHECK AD WORD
CHECK AD WORD
CHECK AD WORD
CHECK DI WOAD
CHECK DI WOAD
CHECK DI WOAD
WRITE BITS TO TSAC
WRITE FALLING EDGE OF ClK
WRITE FALLING EDGE OF ClK
WRITE FALLING EDGE OF ClK
WRITE FALLING EDGE OF ClK
DECREMENT lAP COUNTER
TEST FOR lOOP COMPLETION
TEST AND WAIT FOR CTS lOW
TEST AND WAIT FOR CTS lOW
TEST AND WAIT FOR CTS lOW
REMOVE CS IGROUP SELECT!
RETURN FROM SUBROUTINE

2-163

II
s:

o
.....

t.....

$')

s:
o.....

t
.....

FIGURE 11 - MICROPROCESSOR PORT TIMING

CO
DCl
NOTE The FST pulse may safely occur wlthrn a data loading sequence,

t

FST
NOTE elK

IS

\\\

t-

r

\S\

I
I
I

ClK

N

....
en
I

CS

f

I :

Independent of DCl and DC2

\u\\u._ __

I
I
I

,.........,.,.....,~1 f"1 1"1. f"1 1"1. f"1 11. 1'1 Vl!/I//II/OIT/T/i/t.liJ(l/!I!1//
f lJ//Tfl/TIl!ITtf!111!I/lII/IIJlTfffl/.
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L...J t
: :
:

--.J

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- --- - - - -- . ---- -

!

I//JTflllll7ll!llfl!IlZ7lf:/IIlllIIll/
I

i

NOTE For Valid Programming, CS must stay high until CTS goes low

.j:Io

I

:

01

71111111t::S!i:X2S:X:EX~X~X:~:X.ITlIlIlllfl/(/!l/f1/Ilj/V/lJITIlI/IlIj/I/I/II!(lITJ/TI/!IlIllllT!IIl/
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AD~zmmm71ljla!llllvm!l!lzm(/IIzm.!/IVIZVomVZ7l/b
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I
I
I
I

II

_
CTS
PO (MCl4416 Only)
00.02 IMC144l8 Only'

I
I
I
I

:

I
I
I
I

Ir------------------

:
---------------------------------------------------------*,.........--------------------------------------NOTE For the MCl4416, the CTS hne
For the MCl4418, the CTS hne

IS
IS

pulled low by the device selected by the CS pm
pulled low by the device whose address matches the data loaded

In

through the AD pm

MC14416, MC14418

FIGURE 12 - TYPICAL CIRCUIT CONFIGURATION USING MCI4416
IN CONJUNCTION WITH MCI4400

+ t2V
+5 V

Hook Status

Rev Data
Rcv Clock

Analog Gnd

MCI4400
VAG
VDD

Analog Out

RxO

-

RDD ' - -

MCl4416
VCC
VDD
OHI

FSR
CLK

RxO

RCE

RXE

Txl

RDC

DC2

DI

-

MulA

TDC

DCl

CTS

-

PDI

TDD

VSS

TOE

VLS

MSI

Analog In

-

-

~

'---

TXE

r - - PO

-

VSS

Rev Sync

CS
OHO
FST

Hook Status

Tx Sync

Tx Clock
Tx Data

Gnd

2-165

•

FIGURE 13 - A COMPLETE SINGLE PARTY CHANNEL UNIT USING
MC3419 SLlC, MCl4403 PCM MONO-CIRCUIT, MCl4418 TSAC

•

i:

.,..,.....
....

(")

Gnd

s»

0:-

i:
Rx Data
Tx Data

.,..,.....
....

(")

CD

Data Clock
Tx Sync

I
I
I
I

I

...en
~
I

en

I

I
I

I

~

Hook Status

Vcc

Bank Status
Bank Select

Address

Data
Clock

-12 V
-48 V
Ring Bus

MC14416, MC14418
FIGURE 14 - CLOCK CIRCUIT AND TIMING
FOR CODEC DATA CLOCKS AT 2.048 MHz

2.048 MHz

o

22 Mil

4
47 PF

I

47pF

•

I

CCI

2.048 MHz

128 kHz

1

DC

2

3

4

5

6

7

8

9

10 11 12 13 14 15

16

+16
2.048 MHz

CCI
128 kHz

~I

L...-_ _ _---,__

----- ---

CCI
128 kHz

MSI

8 kHz

FST

1...1_ _ _ _ _ _ _ _ _ _ _ _ _ _- '

2-167

FST MSI
8 kHz

MC14416, MC14418
FIGURE 15 - CLOCK CIRCUIT AND TIMING
FOR CODEC DATA CLOCKS AT 1.544 MHz

•

I

39pF ":"

3
9
4

Frame

DCCCI

FST

DC
+12
3.088 MHz
CCI
128 kHz

.!.l.HH.l.UlQlllZ
IUUUUUUUUUUUl

MSI

8 kHz

128 kHz

DC

nnnnnnnnnnnnnn

+13.JUUUUUUUUUUUUUL

CCI

l'
t

Frame

I
'

CCI
128 kHz

MSI
8 kHz

FST

Frame

____________________

~n~

2-168

__________________

®

MCl4417

MOTOROLA

CMOS LSI
(LOW-POWER COMPLEMENTARY MOS)

BASIC TIME SLOT ASSIGNER CIRCUIT (TSAC)
The MC144171s a per channel Time Slot Assigner CirCUit (TSAC) that
produces B-blt receive and transmit time slots for a PCM Codec The
PinS DO to D5 are the time slot data Inputs which can be either hardwired on the printed CirCUit board for fixed time slot assignment, or externally programmed through the use of these pins and the latch enable
function. The receive and transmit frame syncs and enables are Independent. In addition, a T/R (TXE/RXE swap) Input IS proVided which
allows a Simplified sWitching mechanism for a small systems architecture Il.e., key systems)
The MC14417 can operate from a Single 5-volt supply for TTL levels
or up to 16-volts for CMOS levels. The MC14417 IS fabricated uSing the
CMOS technology for reliable low-power performance.
•

TTL and CMOS Level Compatibility

•
•

5 to 16 Volt Operation
Low Operating Power Consumption

•
•

For Use With Up to 2.56 MHz Clocks
Independent Transmit and Receive Frame Syncs and Enables

TSAC
TIME SLOT ASSIGNER
CIRCUIT

--

..

L SUFFIX

CERAMIC PACKAGE
CASE 726

18

1

P SUFFIX

PLASTIC PACKAGE
CASE 707

ORDERING INFORMATION

•

Up to 64 Time Slots Per Frame

•
•

Compatible with MC14400/01/02/03/05 PCM Mono-Circuits
Allows Swapping of Transmit Enable ITXE) and Receive Enable
IRXE) Signals

•

CMOS Metal Gate for High Reliability

MC14XXX

rL

~ SuffiX Denotes
Ceramic Package

PlastiC Package

PIN ASSIGNMENT
BLOCK DIAGRAM
VCC [ii\J"i8pVDD
D5 2

17pST

D4

16 PTXE

D3

15 ~RXE

D2

14

DC

D1

13

LE

DO

12 T/A

NDC 8

11

FSR

VSS ...9_ _ _
10-, FST

This deVice contains circUItry to protect the inputs against damage due to high static voltages
or electric fields; however, It IS adVised that normal precautions be taken to avord application of
any voltage higher than maximum rated voltages
to thiS high-Impedance Circuit. For proper operation It IS recommended that Vin and Vout be con-

strained to
VoutlsVDD

the

range

VSS S IV In

or

Unused inputs must always be tied to an ap-

propriate logiC voltage level le.g., either VSS or
VDDI.

12

2-169

MC14417

MAXIMUM RATINGS IVoltages referenced to VSSI
Symbol

Value

Unit

OC Supply Voltage

VOO

-0.5 to 18

V

Level Shift Voltage

VCC

a 5 to VDD

V

Rating

Input Voltage
Inputs Referenced to

Voo

V,n l
V,n2
I

to VCC

•

DC Current Dram per Pin
Operating Temperature Range

-0 5 to VDD+0.5
- 0.5 to VDD + 0.5

V

10

mA

Storage Temperature Range

'c
'c

40 to +85

TA
Tsto

65 to + 165

ELECTRICAL CHARACTERISTICS IT A = 25'CI
Symbol

VOO

Min

Typ

Max

Unit

DC Supply Voltage, VSS = a V

Characteristic

VDD

45

12

16

V

aV

VCC

-

45

5

VDD

V

5
12

051
20

-

5
12

-02
-20 -40

-

rnA

40

DC Supply Voltage, VSS -

Output Current TXE, RXE, ST
IVOL =0.4 VI
IVOL = 1.0 VI

IOl

IVOH=4.6 VI
IVOH= 11.0 VI
Input Voltage ICMOSI FST, FSR, DC1, DC2, NDC

IOH
"0"
"I"

InputVoltagelTTLI DO-05, lE, T/R, VCC-5V

Total Supply Current 10utputs Unloadedl OCI at 2.048 MHz

rnA

Vil

5
12

VIH

5
12

40
96

5
12
16

-

Vil

VIH

5
12

20
20

IT

5
12

-

VOO
5
12

Min

Typ

Max

Unit

-

100
50

200
100

ns

100
50

200
100

ns

+ 150
+75

ns

-

ns

180
125

ns

"0"

"1'

-

-

-

-

-

10
24

V

-

-

V

08
08
0.7

V

-

15
25

-

V
rnA

SWITCHING CHARACTERISTICS ICl = 50 pF TA = 25'C, Unless OtherWise Notedl
Symbol

Charactaristic
Dutput Rise Time, TXE, RXE, ST

tr

Output Fall Time, TXE, RXE, ST

tf

Frame Sync Setup Time ISee Figure I I
Frame Sync Pulse Width
Propagation Oelay INote II DCl to TXE, DC2 to RXE, Cl = 20 pF
Data Clock Frequency
Data Clock Pulse Width at fOC IMaxl
LE Pulse Width

5
12

-

tSFS

5
12

- 150
-75

tpWFS

5
12

200
100

-

tpHlE,
tpLHE

5
12

-

130
80

fOC

5
12

-

-

tpWOC

5
12

200
140

244
192

293
280

tpWlE

5
12

I
1

-

-

NDC to ST Propagation Delay

5
12

FST to ST Propagation Delay

5
12

-

-

-

-

NOTE 1: For time slot 0, tpHlE and tpLHE are measured from the leading edge of DC or FST IFSRI, whichever occurs last

2-170

2.048
MHz
2.6

-

ns
~s

120
80

ns

200
130

nS

MC14417

FIGURE 1 - TIMING DIAGRAMS

DC

FST, FSR

NOTE' No restriction on failing edge

DC

c
"'
"
r--

---.J
_

TXE, RXE

rtPHLE
8 Data CIOCks---9----t..._ _ _ __

PIN DESCRIPTIONS
FST (Frame Sync Transmit Input) - This input identifies
the beginning of the zero-transmit time slot by resetting the
divlde-by-8 and divide-by-64 counters, FST is a CMOS compatible input between VOO and VSS. The TXE output will
begin and end on one 8-bit word boundary which is synchronized with the FST Input, The FST signal should be
aligned with the leading edge of data clock and is typically
8 kHz.

VCC (Positive Supply) - The VCC power supply controls
the inputs LE, 00-05 and T iR". It can be supplied by any
voltage from 4,5 to VOO. In tYPical usage, VCC is 5 volts for
TTL or microprocessor compatibility of the control Inputs to
the TSAC while VOO and VSS are connected to the Codec
supplies,
OS-DO (Para"el Time Slot Data Inputs) - The six Inputs to
the input-storage latch are the time-slot data. DO is the leastsignificant bit while 05 is the most-significant. The binary
word at this Input represents the number of 8 bit time slots
from FST and FSR where TXE and RXE wi" occur, respectively. These can be 5-volt Input compatible with TTL and are
Internally level shifted to the VOO supply.

FSR (Frame Sync Receive Input) - The FSR input provides the same functions for the RXE output as FST did for
TXE, The FSR and FST inputs can be any number of data
clocks different, or can be the same.
TXE, RXE (Transmit-Enable and Receive-Enable
Outputs) - These outputs are used to control the transmitting and receiving of data words to and from Codecs. Each
output swings from VOO to VSS and is eight data clocks
long. TXE and RXE go high at the beginning of the programmed time slot and low at the end. TXE is derived from
FST and RXE is derived from FSR, provided the T IR bit is
high.

LE (Latch Enable Input with Internal Pull-Up) - This input
allows the data DO through 05 and Tiii bits to be latched in
the input-storage latch. If LE is held high, then the inputs to
the latch are combinational and directly applied to the compare circuits, When LE IS pulled low, the input values applied
at DO through 05 and T IR are latched and held in the storage
latch,
T IF! (TXE/RXE Swap Input with Internal Pull-Up) - This
input allows the TXE and RXE inputs to be swapped. When
T IR is a one, the TXE output is derived from FST and RXE
from FSR, If T/R is a zero, the derivation is reversed. If FST
and FSR are eight data clocks apart, then two TSAC channels programmed to the same DO through 05 and different
T I Rbits wi" create a completed conversation. This feature is
intended for use in simplifying small-key systems,

ST (Strobe Output) - The strobe output is provided to
allow simplified input data storage or off-hook multiplexing
control. ST is the logical AND of an enable signal (NOC) and
the TXE time slot period, Thus, ST can only be high during a
programmed TXE time slot. Since no other TSAC in a bank
can have the same TXE programming, the ST output on any
TSAC can be used to uniquely identify that TSAC by a pulse
input on NOC. In many applications ST is used to control the
LE input.

DC (Data Clock Input) - The data clock input establishes
the bit rate for the TSAC. This is typically 1,544 or
2,048 MHz but can be any frequency up to 2.56 MHz, The
data clock is divide-by-8 for both transmit- and receive-time
slots, The data clock input is a CMOS compatible input between VOO and VSS.

NOC (New Data Clock Input with Internal Pull-Up) - This
input can be used in conjunction with ST to strobe data into
a TSAC bank. NOC can be used to enable the strobe output.
VOO, VSS - The TSAC will operate from any single supply from 4.5 to 16 volts, The TSAC can be used in a S-voltonly system by making both VCC and VDD 5 volts,

2-171

MC14417
FIGURE 2 -

MOTOROLA MONO-CIRCUIT/TSAC COMBINATIONS

+5
Rev Data
Rev Sync

Data Clock

•

1

MC14401
~

RSI

Voo

AnalogGnd

VAG

Analog Out

Rxo

I1xO
Analog In
10 k

r

10 k

MC14417

Vcc

VOO

ROD I - -

FSR

DO

RCE

RXE

D1

RDC

DC

D2

W

Txl

TOC

NDC

D3

-Tx

TOD

ST

D4

MulA

TOE

TXE

D5

"-

I'm

MSI

FST

TiR

-

VSS

VLS

VSS

LE

J
TIme
Slot
Data

Latch

Tx Data
Tx Sync
Gnd

-5V
The MC14417 TSAC offers simple flexible time slot assignment for
the PCM monO-CIrcUit. Assignments are wIred or latched Into
the data porI. The MC14401 offers supply flexibility of ± 5, ± 6, + 12,
or + 10 V with 18 Pin packages and TTL compatibility.

2-172

®

MOTOROLA

Mel4419

2-0F-8 KEYPAD-TO-BINARY ENCODER
The MCl4419 IS designed for phone dialer system applications, but
finds many applications as a keypad-to-blnary encoder. The device contains a 2-01-8 to binary encoder, a strobe generator, and an illegal state
detector. The encoder has four row inputs and four column inputs, and
is designed to accept inputs from 16 keyswitches arranged in a 4 x 4
matrix. For an output on the four data lines, one and only one row along
with one and only one column input line must be activated. All other
combinations are suppressed by the illegal state detector to eliminate
false data output.
The strobe generator produces a strobe pulse when any of the 10
keys corresponding to numerals a through 9 are depressed. The strobe
output can be used to eliminate erroneous data entry due to contact
bounce. For a strobe output to occur, the key row and column Input
lines must remain stable for 80 clock pulses after activation. When the
contact bounce has settled and 80 clock pulses have occurred, the output will be a single strobe pulse equal in width to that of the clock low
state. The strobe generator will output one and only one pulse each
time a numerical key is depressed. After the pulse has occurred, noise
and bounce due to contact break will not cause another strobe pulse.
With a 16 kHz input clock frequency, the pulse occurs 5 ms after the last
bounce.

CMOS
(LOW-POWER COMPLEMENTARY MOS)

2-0F-8 KEYPAD-TO-BINARY
ENCODER

~~
161il0nrU~
u
1~~~ ~ ~
u

1

1

L SUFFIX

P SUFFIX

CERAMIC PACKAGE

PLASTIC PACKAGE

CASE 620

CASE 648

ORDERING INFORMATION

•
•
•
•

Suppressed Output for Illegal Input Codes
On-Chip Pull up Resistors for Rowand Column Inputs
Clock Input Conditioning Circuit
Low Current Drain In Standby Mode
5.0"A Typical @ 5.0 Vdc
• Subsystem Complement to the MCl4408/14409 Phone
Pulse Converter
• Codes for Numbers 0-9 Produce a Strobe Pulse
• One Key Rollover Feature

MC14XXX

-~UffiX

Denotes

L= Ceramic
P= PlastiC

PIN ASSIGNMENT

16

rI'

BLOCK DIAGRAM

15

!

1

Row

Inputs

R2

2

R3

3

R4

4

Inputs

C2
C1

6

C3

7

C4

9

4

15 Clock

BCD

5

Column

14

Detector

--

-1

S"obe

Generator

!

12

I

6

-==:;

14 S"obe

i
Encoder
and
Illegal
Code

Detector
VOO .,.. Pin 16

11
10

-eo(

2-of-8
to
Bmary

13

13

04

12

03

11

02

10

01

VSS .- P,,, 8

2-173

Data
Outputs

This device containS circuitry to protect
the Inputs against damage due to high static
voltages or electriC fields; however, It IS
adVised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to this high
Impedance cirCUit. For proper operation it
is recommended that Vin and V out be
constrained to the range VSS :s;;; (Vin or
Vau,l <; VDD·

•

MC14419

MAXIMUM RATINGS (Voltage. referenced to VSS. Pin 8.1
Rlting

•

Unit

Symbol

Vllue

DC Supply Voltage

VOo

+6.0 to -0.5

Vdc

Input Voltage, All Inputs

Vin

VOO + 0.5
to
VSS -0.5

Vdc

DC Current Drsln per Pin

Operating Temperature Range
Storage Temperature Range

I

10

mAde

TA

-40 to +85
-65 to +150

°c

T stg

C

ELECTRICAL CHARACTERISTICS
Characteristic
Supply Voltage Operating Range
Output Voltage

"0" Level

Symbol
VOO
V out

"1" Level
Noise Immunity
(6V out .. 0.8 Vdc)

Output Drive Current
(VOH = 2.5 Vdc)

=0.4 Vdc)

VNL
VNH
10H

Voo
Vdc

2SoC

-40°C

+8SoC

Min

Max

Min

Typ

Max

Min

Max

Unit

-

3.0

3.0
-

5.0

6.0
0,01

3.0

4.99
1.5
1.4
-0.23

4.99
1.5
1.5
-0.20

5.0
2.25
2.25

-

-

Vdc

-1.7

-

4.95
1.4
1.5
-0.16

6.0
0.05
-

Vdc

5.0
5.0
5.0
5.0
5.0

6.0
0.01
-

-

-

a

-

-

Vdc
Vdc

-

Vdc

-

mAdc

Source

-

-

0.16

-

mAdc

-

-

0.20
-

0.78

IIH

5.0
5.0

0.23

I nput Leakage Current
(Vin = VOO)

10

-

-

-

pAdc

Pull up Resistor Source Current

IlL

5.0

265

460

190

250

330

125

215

"Adc

Cin

-

-

-

-

5.0

-

-

-

pF

100S

3.0
5.0
6.0

-

3.0
15
60

-

1.0
5.0
20

3.0
15
60

-

6.0
30
120

"Adc

(VOL

Sink

10L

(Rowand Column Inputs)
(Vin = VSS)
I "Pu t Capaci tance

(Vin

= VSS)

Standby Supply Current
(fclock = 16 kHz. No Keys

Depressed)
Standby Supply Current as a

100S

-

5.0

-

100S

-

-

=0.09 "A/kHz + 3.0 "A

"Adc

Function of Clock Frequency*

(No Keys Depressed)
·The formula given is for the typical characteristics only.

SWITCHING CHARACTERISTICS (CL = 50 pF TA = 250 C)
Characteristic
Output Rise and Fall Times, 01 thru 04 (Figure 1)

Symbol

VDD

Min

Typ

Max

tr,tf

5.0

-

300

-

ns

Propagation Delay Time, Row or Column Input to
Data Output (Figure 1)

tpLH.
tpHL
PRF

5.0

-

1000

-

ns

3.0 to 6.0

4.0

16

80

kHz

Clock Pulse Frequency Range

2-174

Unit

MC14419

FIGURE 1 - SWITCHING TIME WAVEFORMS

FIGURE 2 - TYPICAL STROBE PULSE OELAY TIMES

PRF
Clock Frequency
kHz
4.0
8.0
16
32
80

VOO

Row or
Column
Input

VSS

On
Output

'ST"
Strobe Pulse Delay Time

ms
~O

10
5.0
2.5
1.0

·tST = (1/PRF). 80, with PRF In kHz, tST in ms.

VOL

FIGURE 3 - STROBE GENERATOR TIMING OIAGRAM

Contact

Contact

Noise
Spike

Make
Bounce

Break
Bounce

Rowor
Column
Input

I.-tsT-lI--PWST""
Strobe Generator
OutPut

n

80 Clock
Pulses

I!

• ·PWST = Strobe Pulse Width == Low State Clock Pulse Width (PWL).

TRUTH TABLE
Inputs

Key**
1
2
3
A

4
5
6
B
7

8
9

c

a
#
0

Row
R4 R3 R2 Rl

Outputs

Column

C4 C3 C2 C1

04030201

Strobe

.n.
.n.
.n.
0
.n.

1
1
1
1

1
1
1
1

1
1
1
1

0
0
0
0

1
1
1
0

1
1
0
1

1
0
1
1

0
1
1
1

0
0
0
1

0
0
0
1

0
1
1
0

1
0
1
0

1
1
1
1

1
1
1
1

0
0
0
0

1
1
1
1

1
1
1
0

1
1
0
1

1
0
1
1

0
1
1
1

0
0
0
1

1
1
1
1

0
0
1
0

0
1
0
1

.n...
.n...

1
1
1
1

0
0

1
1
1
1

1
1
1
1

1
1
1
0

1
1

1

a

0
1
1
1

1

1

1

a

a a a
0 a 1

Il.

1
1
1

1
1
1
1

1
1
1
0

0
0
0
0

a
0
1
1
1
1

t

a
1

1
1

1
1
0
1

1
0
1
1

1
1
1

a

All Other Combinations
.. ·See Figure 4 for keypad designation

2-175

1
1
1

1

1

1

0

a

1
1

0
0
1

1
0
1
1

0
0
1
1

0

0

0

0

a

0

.n.
.n.
0
0

Il.
0
0
0

MC14419

FIGURE 4 - TYPICAL KEYPAD INTERFACE APPLICATION

•

V DD

Keypad with OPST

N,O. SwItches

4

K

4 Keypad

Common

MC14419

Keypad with SPST

D1

10

D2

11

D3

12

D4

13

ST

14

N.O. Switches

:,@
Column

ROW

Common

VSS

FIGURE 5 - PHONE DIALER SYSTEM

MCl4419

MC1440B, MCl4409

2-of-8 Keypad-to-Binary Encoder

Binary-to-Phone Pulse Converter
L=5mH

fClk= 16kHz

14

ST
Row
Inputs

"om {

Keypad

Column
Inputs

Ii
j!

13

11 OutPulsing

D3

D3
11

D2

D2

DRO

10
D1

D1

I
Vss = Pin 8

5P[
D4

12

II
Voo = Pin 16

4

D4

I

MC1440B/409 {

Con"ol Inputs

I

I
-.J
Hold

9

Call Request 13 0 - - - - - - '

I
I
I

12 Dial Rotating
Output-

Re-Dlal 10

In'",d.glt T.me 14
Make Break Ratio 15

0--------'
o----~
0----------'

Voo = Pin 16
VSS = Pin 8
• Between each digit
pulsetraln, MC1440B
ORO stays high.
MCl4409 ORO goes low.

®

MC34010A
MC34011A

MOTOROLA
Advance Information

•

ELECTRONIC
TELEPHONE
CIRCUIT

ELECTRONIC TELEPHONE CIRCUIT
• Provides All Basic Telephone Station Apparatus Functions in a
Single IC, Including DTMF Dialer, Tone Ringer, Speech Network
and Line Voltage Regulator

BIPOLAR lINEARlI2L

• DTMF Generator Uses Low-Cost Ceramic Resonator with Accurate Frequency Synthesis Technique
• Tone Ringer Drives Piezoelectric Transducer and Satisfies EIA
RS-470 Impedance Signature Requirements

~

• Speech Network Provides Two-Four Wire Conversion with Adjustable Sidetone Utilizing an Electret Transmitter
• On-Chip Regulator Insures Stable Operation Over Wide Range
of loop lengths
• 12l Technology Provides low 1.4 Volt Operation and High Static
Discharge Immunity

,

44-PIN
PLCC
CASE7n-01

• MC34010A Provides Microprocessor Interface Port for Automatic Dialing Features

FIGURE 1 -

PSUFAX
PLASnC PACKAGE
CASE 711-113

ELEMENTS OF THE MC34010Al11A ELECTRONIC TELEPHONE

Hook Switch

Pieza
Sound
Element

II'

Ceramic
Resonator

,-

1

2

3 A

4

5

6

7

8

9 C

*

0

#

B

I

------..,
I

I

I

I
I

DTMF

,

~
Tip

I

I

Tone
Ringer

D

Line

Keypad

I......

MPU

I

r----7

,-.--

~
,

MPU

Interface
(MC34010A

Speech
Network

Voltage
Regulator

only)

Receiver

Electret

This document contains Information on a new product. Specifications and information herem
are sublect to change Without nouce.

2.. 177

Ring

MC34010A, MC34011 A

MAXIMUM RATINGS (Voltage References to V - )

PIN CONNECTIONS

Parameter

•

Value

Unit

V+ Terminal Voltage (Pin 34)

+18, -1.0

V

VR Terminal Voltage (Pin 29)

+2.0, -1.0

V

RXO Terminal Voltage (Pin 27)

+2.0, -1.0

V

TRS Terminal Voltage (Pin 37)

+35, -1.0

V

TRO (With Tone Ringer Inactive) Terminal Voltage

+2.0, -1.0

R1-R4 Terminal Current (Pins 1-4)
C1-C4
(Pins 5-8)

a:, TO, DO, 110, A+

V

±100

(MC34010A only)

mA

+12, -1.0

V

Operating Ambient Temperature Range

-20 to +60

°C

Storage Temperature Range

-65to +150

°C

TRF
TRO
TRI
TRS
TRC
FB
V+
BP
LR
LC
VVR
CAL
RXO
RXI
RM
STA
TXO
TXI
TXL

R1
R2
R3
R4
C1
C2
C3
C4
·DP
·TO
·MS
·A+

·110
··ES, ·00
··EV,
CR1
CR2
MM
AGC
MIC

.a:

GI:NERAL CIRCUIT DESCRIPTION
Introduction
The MC34010Al11A Electronic Telephone Circuits
(ETC) provide all the necessary elements of a tone dialing telephone in a single IC. The functional blocks of
the ETC include the DTMF dialer, speech network, tone
ringer, and dc line interface circuit (Figure 1). The
MC34010A also provides a microprocessor interface
port that facilitates automatic dialing features.
low voltage operation is a necessity for telephones
in networks where parallel telephone connections are
common. An electronic speech network operating in
parallel with a conventional telephone may receive line
voltages below 2.5 volts. DTMF dialers operate at similarly low-line voltages when signaling through battery
powered station carrier equipment. These low voltage
requirements have been addressed by realizing the
MC34010Al11A in a bipolar/1 2 l technology with appropriate circuit techniques. The resulting speech and dialer circuits maintain specified performance with instantaneous input voltage as low as 1.4 volts.

·MC34010A only.
··MC34011 A only.
FIGURE 2 -

FIGURE 3 -

0

0

f- R1

0

0

0

~

r-

R2

0

0

0

@]

-

R3

G 0

0
I

@]

-

R4

Line

I
I
I
I

I

I
~

2-178

C3
Keypad

I
C4

Row

Column

Code (B3-BO)

1
2
3

1
1
1
2
2
2
3
3
3
4
1
2
3
4
4
4

1
2
3
1
2
3
1
2
3
2

1111
0111
1011
1101
0101
1001
1110
0110
1010
0100
0011
0001
0010
0000
1100
1000

5
6
7
8
9
0
A
B
C
0

*#

I

L ______________________
ETC I

I
C2

Key

4
iTelephone

LC

0

C1

DC LINE INTERFACE BLOCK DIAGRAM

r---- - - -- - -- -- - -- -.,.--- -

[J

I

Line Voltage Regulator
The de line interface circuit (Figure 3) determines the
dc input characteristic of the telephone. At low input
voltages (less than 3 volts) the ETC draws only the

MPU INTERFACE CODES

4
4

4
4
1
3

MC34010A, MC34011 A

GENERAL CIRCUIT DESCRIPTION (continued)
speech and dialer bias currents through the VR regulator. As input voltage increases, 01 conducts the excess dc line current through resistor R4. The 1.5 volt
level shift prevents saturation of 02 with telephone line
signals up to 2.0 volts peak (+ 5.2 dBm). A constant
current (dummy load) is switched off when the DTMF
dialer is activated to reduce line current transients. Figure 4 illustrates the dc voltage/current characteristic of
an MC34010All1A telephone.
FIGURE 4 -

terminal and driven through an external R-C network to
control the receiver sidetone level. The switched ac resistance at the RM terminal reduces receiver signal
when dialing and suppresses clicks due to hook or keypad switch transitions. When transmitting, audio signal
currents (iTXO and iRXO) flow through the voltage regulator pass transistor (Tl) to drive the telephone line.
This feature has two consequences: 1) In the transmitting mode the receiver sidetone current iRXO contributes to the total signal on the line along with iTXO;
2) The ac impedance of the telephone is determined by
the receiver impedance and the voltage gain from the
line to the receiver amplifier output.

DC V-I CHARACTERISTIC OF THE ETC

7.0
0>

:B~

-5 :!;
w.,

6.0
5.0

)(-

ai'.g 4.0

I1V = R4

111

~.~

~Ill

g ~ 3.0
(lJ

:§

.2

Cl 2.0

1.0

10

20

30
40
Line Current (mAl

50

60

120

DTMF Dialer
Keypad interface comparators activate the DTMF row
and column tone generators (Figure 6) when a row and
column input are connected through a SPST keypad.
The keypad interface is designed to function with contact resistances up to 1.0 kO and leakage resistances as
low as 150 kO. Single tones may be initiated by depressing two keys in the same row or column.

Speech Network
The speech network (Figure 5) provides the two-tofour wire interface between the telephone line and the
instrument's transmitter and receiver. An electret microphone biased from VR drives the transmit amplifier.
For very loud talkers, the peak limiter circuit reduces
the transmit input level to maintain low distortion. The
transmit amplifier output signal is inverted at the STA
FIGURE 5 -

Equalization Circuit (MC34011A Only)
The equalization circuit varies the transmit, receive
and sidetone gains with loop current to compensate for
losses in long lines. The LR terminal voltage varies directly as the dc loop current. The equalization circuit
senses this voltage and switches in external resistors
between V + and V - and across capacitor C6 (Figure
5) when the loop current exceeds a threshold level. The
speech network operates with full transmit, receive and
sidetone gains for long loops. On short loops the LR
voltage exceeds the threshold and these gains are reduced. The threshold detection circuit has a dc hysteresis to prevent distortion of speech signals when the
telephone is operated at the threshold current.

SPEECH NETWORK BLOCK DIAGRAM

--ITXO

R11

r-----,

R12

I Telephone
I Handset
I

C4
R13

C5

C3 +

'-----=--o----l

i

Electret
I Microphone

RXI

I
C10
--IRXO

2-179

MC34010A, MC34011 A

The programmable counters employ a novel design
to produce non-integer frequency ratios. The various
DTMF tones are synthesized with frequency division
errors less than ±0.16% (Table 1). Consequently an inexpensive ceramic resonator can be used instead of a
quartz crystal as the DTMF frequency reference. Total

•

frequency error less than ± 0.8% can be achieved with
±0.3% ceramic resonator. The row and column D/A
converters produce 16-step approximations of sinusoidal waveforms. Feedback through terminal FB reduces the DTMF output impedance to approximately
2.0 kll to satisfy return loss specifications.

FIGURE 6 - DTMF DIALER BLOCK DIAGRAM

r------------------------,I

I

I
r-_ _ _-:C:::l-cl> --i

I

i

Column

I FB
C14

Keypad
Comparators
& Logic
456B

R31

789C

R41

Telephone
Line

• 0 # 0
Keypad

Tone Ringer
The tone ringer (Figure 7) generates a warbling
square wave output drive to a piezo sound element
when the ac line voltage exceeds a predetermined
threshold level. The threshold detector uses a current
mode comparator to prevent onloff chatter when the
output current reduces the voltage available at the
ringer input. When the average current into the tone
ringer exceeds the threshold level, the ringer output
TRO commences driving the piezo transducer. This output current sourced from TRI increases the average current measured by the threshold detector. As a result,
hysteresis is produced beween the tone ringer on and
off thresholds. The output frequency at TRO alternates
between fo/8 and foil 0 at a warble rate of f o /640, where
fo is the ringer oscillator frequency.
Microprocessor Interface (MC34010A Only)
The MPU interface connects the keypad and DTMF
sections of the ETC to a microprocessor for storing and
retrieving numbers to be dialed. Figure 8 shows the
major blocks of the MPU interface section and the interconnections between the keypad interface, DTMF
generator and microprocessor. Each button of a 12 or
16 number keypad is represented by a four-bit code
(Figure 2). This four-bit code is used to load the programmable counters to generate the appropriate row
and column tones. The code is transferred serially to or
from the microprocessor when the shift register is

clocked by the microprocessor. Data is transferred
through the 1/0 terminal, and the direction of data flOw
is determined by the Data Direction (DD) input terminal.
In the manual dialing mode, DD is a logic "0" and the
four-bit code from the keypad is fed to the DTMF generator by the digital multiplexer and also output on the
1/0 terminal through the four-bit shift register. The data
sequence on the 1/0 terminal is B3, B2, Bl, BO and is
transferred on the negative edge of the clock input (Cl).
In this mode the shift register load enable circuit cycles
the register between the load and read modes such that
multiple read cycles may be run for a single-key closure.
Six complete clock cycles are required to output data
from the ETC and reload the register for a second look.
In the automatic dialing mode, DD is a logic "'" and
the four-bit code is serially entered in the sequence B3,
B2, Bl, BO into the four-bit shift register. Thus, only four
clock cycles are required to transfer a number into the
ETC. The keypad is disabled in this mode. A logic "'"
on the Tone Output (TO) will disable tone outputs until
valid data from the microprocessor is in place. Subsequently TO is switched to a logic "0" to enable the
DTMF generator. Figures 9 and '0 show the timing waveforms for the manual and automatic dialing modes
and Table 2 specifies timing limitations.
The keypad decoder's exclusive OR circuit generates
the DP and MS output signals. The DP output indicates
(when at a logic ",") that one, and only one, key is

2-180

MC34010A, MC34011 A

depressed. thereby indicating valid data is available to
the MPU. The OP output can additionally be used to
initiate a data transfer sequence to the microprocessor.
The MS output (when at a Logic "1") indicates the OTMF
generator is enabled and the speech network is muted.
Pin A+ is to be connected to a source of 2.5 to 10
volts (generally from the microprocessor circuit) to enable the pullup circuits on the microprocessor interface
outputs (OP. MS. 110). Additionally. this voltage will
FIGURE 7 -

power the entire circuitry (except Tone Ringer) in the
absence of voltage at V +. This permits use of the transmit and receive amplifiers. keypad interface. and OTMF
generator for non-typical telephone functions.
See Figure 47 for a typical interconnection to an
MC6821 PIA (Peripheral Interface Adapter). Connection
to a port on any other class of microprocessor will be
similar.

TONE RINGER BLOCK DIAGRAM

C17
~Tip
Rl

R2

r--------

1..-_ _ _ _ _ _ _- 0 Ring

TRF

TRI

I

I

I
I

Piezo
Tone
Ringer

I

ETC I
L _____________________~~~-~

FIGURE 8 -

MICROPROCESSOR INTERFACE BLOCK DIAGRAM (MC34010A ONLY)

r-------------------------.,TO
Exclusive -OR

8

~~" -=~" :;"

v

I

o c 0 c
c:::wUw

::;:

1

t

j

DP
MS

DTMF Generator

""-2'3
~~~~

~ -; Ii
9

Keypad

~

:v Comparators Iv'

Keypad
Decoder

'----

,---~

Shift
Register
Load
Enable

4

I-

11"
~

----y

4'rDigital
MUX

11
4-8it

DD

Shift
Register

I/O

MPU

-CL
1.
T
L _________________ ~~------1
ETC

'----T'-:

v-

2-181

•

MC34010A, MC34011 A

FIGURE 9 - OUTPUT DATA CYCLE FROM MC34010A

NOTE: TO may be low (Tone generator enabled) if desired.

DD~'\~~~____~'_K_e_~_D_e_pr_e_ss_e_d_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _K_e_y_'R_e_le_a_se_d_'~I_

•

MS~~~___+--____________________________________~_
I
I

I

L

DP _ _ _ _ _ _----!I tDPCL

1--1

FIGURE 10 -INPUT DATA CYCLE TO MC34010

DD

--.J

Tone Generation Interval

1---1 tTODD
H
roJ~~!--------~lJ~----~U
I

I

I

I

i

I

I

I

I

I

L

I

MS~

DP----+I----------------+I--------------------------------------tDOCL
tCLro

H

H

C[~~~

TABLE 1 -

Ton. Output
Frequency with
500 kHz Oscillator

from Standard

697
770
852
941

696.4
769.2
853.2
939.8

1209
1336
1477
1633

1207.7
1336.9
1479.3
1634.0

(Hz)

Row
Row
Row
Row

1
2
3
4

Column
Column
Column
Column

1
2
3
4

TABLE 2 -

FREQUENCY SYNTHESIZER ERRORS

DTMF
Standard

Symbol
% Devietion

TIMING LIMITATIONS

Parameter

Min Typ Max Unit

Ref

fCL
tH

Clock Frequency
Clock High Time

0
15

-

-0.086
-0.104
+0.141
-0.128

tL

Clock Low Time

15

- -

tr,tf
tDV

-

-

-0.108
+0.067
+0.156
+0.061

tDPCL

Clock Rise, Fall Time
Clock Transition to
Data Valid
Time from DP High
to C[ Low
Time..!!:.om DD High
to CL Low
Data Setup Time
Data Hold Time
Time from C[ Low
to TO Low
Time from TO High
to DD High

30 kHz
- !J-S Figs.
9,10
!J-S Figs.
9,10
2.0 !L s
10 !J-S Fig. 9

20

-

-

!LS

Fig. 9

20

-

-

!J-S

Fig. 10

10
10
10

-

-

- -

-

!J-S
!J-S
!J-S

Fig. 10
Fig. 10
Fig. 10

20

- -

!J-S

Fig. 10

tDDCL
tDS
tDH
tCLTO
tTODD

2-182

20

MC34010A, MC34011 A
PIN DESCRIPTION
(See Figures 47 & 48 for external component identifications.)

PIN

PIN

(PLCCI

(DIPI

Designation

1-4

1-4

Rl-R4

Keypad inputs for Rows 1 through 4. When open, internal S.O kn resistors pull up the row inputs
to a regulated (=1.1 volt) supply. In normal operation, a row and a column input are connected
through a SPST switch by the telephone keypad. Row inputs can also be activated by a Logic
"0" «500 mVI from a microprocessor port.

7-10

5-S

Cl-C4

Keypad inputs for Columns 1 through 4. When open, internal S.O kn resistors pull down the
column inputs to V -. In normal operation, connecting any column input to any row input
produces the respective row and column DTMF tones. In addition to being connected to a row
input, column inputs can be activated by a Logic "I" (>600 mV and <3.0 voltl.

11

9

DP'

Depressed Pushbutton (Outputl- Normally low; A Logic "I" indicates one and only one, button
of the DTMF keypad is depressed.

12

10

TO"

Tone Output (Input) - When a Logic "1," disables the DTMF generator. Keypad is not disabled.

13

11

MS"

Mute/Single Tone (Output) -A Logic "I" indicates a rowand/or column tone is being generated.
A Logic "0" indicates tone generator is disabled.

14

12

A+"

MPU Power Supply (lnputl - Enables pullups on the microprocessor section outputs. Additionally, this voltage will power the entire circuit (except Tone Ringerl in the absence of voltage
atV+.

15

13

I/O"

Input/Output - Serial Input or Output data (determined by DD inputl to or from the microprocessor for storing or retrieving telephone numbers. Guaranteed to be a Logic "I" on powerup
if DD = Logic "0."

16

.14

DD"

Data Direction (Input) - Determines direction of data flow through I/O pin. As a Logic "1," I/O
is an input to the DTMF generator. As a Logic "0," I/O outputs keypad entries to the
microprocessor.

ES**

Sidetone Equalization terminal connects an external resistor between the junction of RS, R9 and
V -. At loop currents greater than the equalization threshold this resistor is switched in to reduce
the sidetone level.

CL*

Clock (Input) - Serially shifts data in or out of I/O pin. Data is transferred on negative edge
typically at 20 kHz.

EV**

Voice Equalization terminal connects an external resistor between V + and V -, for loop length
equalization. At loop currents greater than the equalization threshold this resistor is switched
in by the equalization circuit to reduce the transmit and receive gains.

17

15

Function

lS,19

16,17

CR1, CR2

Ceramic Resonator oscillator input and feedback terminals, respectively. The DTMF dialer is
intended to operate with a 500 kHz ceramic resonator from which row and column tones are
synthesized.

20

IS

MM

Microphone Mute. The MM pin provides a means to mute the microphone and transmit amplifier
in response to a digital control signal. When this pin is connected to a Logic "I" (>2.0 VI the
microphone de return path and the transmit amplifier output are disabled.

21

19

AGC

Automatic Gain Control low-pass filter terminal. Capacitor C3 connected between AGC and VR
sets the attack and decay time of the transmit limiter circuit. This capacitor also aids in reducing
clicks in the receiver due to hook-switch transients and DTMF on/off transients. In conjunction
with internal resistors, C3 (1.0 I"F) forms a timer which mutes the receiver amplifier for approximately 20 'milliseconds after the user goes off-hook or releases a DTMF Key.

22

20

MIC

Microphone negative supply terminal. The dc current from the electret microphone is returned
to V - through the MIC terminal which is connected to the collector of an on-chip NPN transistor.
The base of this transistor is controlled either internally by the mute signal from the DTMF
generator, or externally by the logic input pin MM.

24

21

TXL

Transmit Input Limiter. An internal variable resistance element at the TXL terminal controls the
transmitter input level to prevent clipping with high signal levels. Coupling capacitors C4 and
C5 prevent dc current flow through TXL. The dynamic range of the transmit peak limiter is
controlled by resistors R12 and R13.

25

22

TXI

Transmit amplifier Input. TXI is the input to the transmit amplifier from an electret microphone.
AC coupling capacitors allow the dc offset at TXI to be maintained approximately 0.6 V above
V - by feedback through resistor Rll from TXO.

26

23

TXO

Transmit Amplifier Output. The transmit amplifier output drives ac current through the voltage
regulator pass-transistor Tl via resistor RIO. The dc bias voltage at TXO is typically 0.6 volts
above V -. The transmit amplifier gain is controlled by the Rl1/(R12 + R13) ratio.
(contmuedl

**MC34011A only.

*MC34010A only.

2-183

•

MC34010A, MC34011 A
PIN DESCRIPTION (continued)
PIN
(PlCC)

•

PIN
(DIP)

Designation

Function

27

24

STA

SideTone Amplifier output. STA is the output of the sidetone inverter amplifier whose input is
driven by the transmit signal at TXO. The inverted transmit signal from STA subtracts from the
receiver amplifier input current from V + , thus reducing the receiver sidetone level. Since the
transmitted signal at V + is phase shifted with respect to TXO by the reactive impedance of the
phone line, the signal from STA must be similarly phase-shifted in order to provide adequate
sidetone reduction. This phase relationship between the transmit signal at TXO and the sidetone
cancellation signal from STA is controlled by RB, R9, and C6.

28

25

RM

Receiver Amplifier Mute. A switched resistance at the RM terminal attenuates the receiver
amplifier input signal produced by DTMF dialing tones at V +. RM also mutes clicks at the receiver
which result from keypad or hook switch transitions. The ac resistance at RM is typically 540 n
in the mute mode and 200 kn otherwise. Coupling capacitors C7 and C8 prevent dc current flow
through RM.

29

26

RXI

Receiver Amplifier Input. RXI is the input terminal of the receiver amplifier which· is driven by
ac signals from V + and STA. Input coupling capacitor CB allows RXI to be biased approximately
0.6 volts above the V - via feedback resistor R6.

30

27

RXO

Receiver Amplifier Output. This terminal is connected to the open-collector NPN output transistor
of the receiver amplifier. DC bias current for the output device is sourced through the receiver
from VR. The bias voltage at RXO is typically 0.6 volts above the V -. Capacitor C10 from RXO
to VR provides frequency compensation for the receiver amplifier.

31

2B

CAL

Amplitude CAlibration terminal for DTMF dialer. Resistor R14 from the CAL pin to V - controls
the DTMF output signal level at Tip and Ring.

32

29

VR

Voltage Regulator output terminal. VR is the output of a 1.1 volt voltage regulator which supplies
power to the speech network amplifiers and DTMF generator during signaling. To improve
regulator efficiency at low line current conditions, an external PNP pass-transistor Tl is used in
the regulator circuit. Capacitor C9 frequency compensates the VR regulator to prevent oscillation.

33

30

V-

The dc common (more negative input) connected to Tip and Ring through the polarity guard
bridge.

34

31

LC

DC Load Capacitor. Capacitor Cl1 from LC to V - forms a low-pass filter which prevents the
resistor at LR from loading ac speech and DTMF signals.

35

32

LR

DC Load Resistor. Resistor R4 froll) LR to V - determines the dc input resistance at Tip and Ring.
This resistor is external not only to enable programming the dc resistance but also to avoid
high on-chip power dissipation with short telephone lines. It acts as a shunt load conducting
the excess dc line current. At low line voltages «3.0 Volts), no current flows through LR.

36

33

BP

Base of a PNP Pass-transistor. Under long-loop conditions where low line voltages would cause
VR to fall below 1.1 volts, BP drives the PNP transistor T1 into saturation, thereby minimizing
the voltage drop across the pass transistor. At line voltages which maintain VR above 1.1 volts,
BP biases Tl in the linear region thereby regulating the VR voltage. Transistor T1 also couples
the ac speech signals from the transmit amplifier to Tip and Ring at V + .

37

34

V+

The more positive input to the regulator, speech, and DTMF sections connected to Tip and Ring
through the polarity guard diode bridge.

38

35

FB

FeedBack terminal for DTMF output. Capacitor C14 connected from FB to V + provides ac
feedback to reduce the output impedance to Tip and Ring when tone dialing.

40

36

TRC

Tone Ringer oscillator Capacitor and resistor terminal. The relaxation oscillator frequency fo is
set br resistor R3 and capacitor C13 connected from TRC to V -. Typically, fo = (R3C13 + B.O
!'9)- .

41

37

TRS

Tone Ringer Input Sense. TRS is the most positive input terminal of the tone ringer and the
reference for the threshold detector.

42

38

TRI

Tone Ringer Input terminal. TRI is the positive supply voltage terminal for tone ringer circuitry.
Current is supplied to TRI through resistor R2. When the average voltage across R2 exceeds an
internal reference voltage (typically 1.6 volts) the tone ringer output is enabled.

43

39

TRO

Tone Ringer Output terminal. The frequency of the square wave output signal at TRO alternates
from fo/B to folIO at a warble rate of f0l64O. Typical output frequencies are 1000 Hz and BOO Hz
with a 12.5 Hz warble rate. TRO sources or sinks up to 20 mA to produce an output voltage
swing of 18 volts peak-to-peak across the piezo transducer. Tone ringer volume control can be
implemented by a variable resistor in series with the piezo transducer.

44

40

TRF

Tone Ringer Input Filter capacitor terminal. Capacitor C16 connected from TRF to TRS forms a
low-pass filter. This filter averages the signal across resistor R2 and presents this dc voltage to
the input of the threshold detector. Line voltage transients are rejected if the duration is
insufficient to charge C16 to 1.6 volts.

2-184

MC34010A, MC34011 A

ELECTRICAL CHARACTERISTICS (continued)
TONE RINGER
Characteristic

Test
Method

Symbol

Min

Typ

Max

Unit

14

VTRI

20

21.5

23

Vdc

70
0.4

120
0.8

170
1.5

rnA

TRI Terminal Voltage
TRS Terminal Input Current
VTRS = 24 volts
VTRS = 30 volts

ITRS
15a
15b

!LA

TRF Threshold Voltage

16a

VTRF

1.2

1.6

1.9

Vdc

TRF Threshold Hysteresis

16b

~VTRF

100

200

400

mVdc

TRF Filter Resistance

17

RTRF

30

50

75

kG

High Tone Frequency

18

fH

920

1000

1080

Hz
Hz

Low Tone Frequency

18

fL

736

800

864

Warble Frequency

18

tw

11.5

12.5

13.5

Hz

Tone Ringer Output Voltage

19

Vo(p-p)

18

20

22

Vp-p

FIGURE 11 -

2
3
4

TRI

R4

TRS

C3

V+

13
14
15

100pF

R3

C2

11

r

TRO

TRC

12

*=

R2

FB

10

1

TRF

6

9

100 PF

R1

5 C1

8

MC34010A
Only

GENERAL TEST CIRCUIT

DP

17

19
20

D.U.T.

LR

TO

LC

MS

V-

A+

VR

110

CAL

DO, (ES**)

RXO

CC, (EV**)

RXI

16 CR1

18

BP

C4

40
39
38
37
36
35
34
33
32
31
30
29
+

28

RM

CR2

STA

MM

TXO

AGC

TXI

MIC

TXL

0.047
27

1

20
.

100 k

26

2.0 k

25

510

24
23
22
21

Notes:
,. ·Selected ceramic resonator: 500 kHz ± 2.0 kHz.
2. Capacitances in p,f unless noted,
3. All resistances in ohms.
4. Pin numbers in this Figure and in Test Circuits are for the DIP package.

**MC34011A onlv.

2-185

200 k
TXAC
10 k

1°.D1

•

MC34010A, MC34011 A

FIGURE 12 -

TEST ONE

FIGURE 13 -

34

ISp

34

•

TEST TWO

6000

-"=lvs
General
Test
Circuit

29

lOT

5

-

+

,.., VR

General
Test
Circuit

= 1.7 V
= 1,7 V
Vs = 5.0 V

a. Measure VR with Vs

a. Measure lOT with Vs = 11,5 V .

b. Measure ISp with Vs

b. Measure lOT with Vs = 26 V. Calculate
AIOT = lOT
lOTI
26V
11.5V

c. Measure ISp with

FIGURE 14 -

I-

TEST THREE

FIGURE 15 -

TEST FOUR

S1

r-<'
~OV
-

34
6000

I

I

+

General
Test
Circuit

..I.

General
Test
Circuit

With S1 open measure ITR. Close S1 and again measure
ITR. Calculate:
AITR

=

ITR

1-

S1'

Closed

a. Set Vs = 5.0 V and ILR = 10 rnA. Measure VLR.
Calculate AVLR = Vs - VLR

ITRI

b. Repeat Test 4a with Vs

S1'
Open

2-186

= 18 V and ILR = 110

rnA

MC34010A, MC34011 A

ELECTRICAL CHARACTERISTICS ITA = 25"<:)
KEYPAD INTERFACE CIRCUIT
Tast
Method

Symbol

Min

Typ

Max

Unit

Row Input Pullup Resistance
mth Row Terminal: m = 1,2,3,4

7

RRm

5.0

8.0

11

kfl

Column Input Pulldown Resistance
nth Column Terminal: n = 1,2,3,4

8

RCn

5.0

8.0

11

kfl

7&8

Km,n

0.88

1.0

1.12

-

1100

1200

mVdc

Characteristic

Ratio of Row-to-Column Input Resistances
'!Bro, m = 1,2,3,4
Km,n =
RCn n = 1,2,3,4
Row Terminal Open Circuit Voltage

7a

VROC

950

Row Threshold Voltage for mth
Row Terminal: m = 1,2,3,4

9

VRm

0.70 VROC

-

Column Threshold Voltage for nth
Column Terminal: n = 1,2,3,4

10

VCn

-

-

0.95

-

Vdc

0.30 VROC

Vdc

MICROPROCESSOR INTERFACE IMC34010A only)
Voltage Regulator Output
A+ Regulator

29

VR/A+

1.1

1.3

V

A + Input Current Oft-Hook

28a

IA(oft)

-

50

150

"A

A + Input Current On-Hook

28b

IA(on)

4.0

6.0

9.0

rnA

Input Resistance (00, TO, CL)

30

Rin

50

100

150

kn

Input Current (110)

31

lin

-

80

200

"A

Input High Voltage (00, TO, CL, liD)

-

VIH

2.0

-

A+

V

Input Low Voltage (00, TO, CL, liD)

VIL

-

-

0.8

V

Output High Voltage (MS, OP, liD)

32

VOH

2.4

4.0

-

V

Output Low Voltage (MS, OP, liD)

33

VOL

-

0.1

0.4

V

Volts

LINE VOLTAGE REGULATOR
Voltage Regulator Output

1a

VR

1.0

1.1

1.2

V + Current in OTMF Mode

2a

lOT

8.0

12

14.5

rnA

Change in lOT with Change in V + Voltage

2b

6oIOT

-

0.8

2.0

rnA

V + Cu rrent in Speech Mode
V+ = 1.7 V
V+ = 5.0 V

1b
1c

3.0
8.0

5.0
11

7.0
15

Speech to OTMF Mode Current Oifference

3

-2.0

2.0

3.5

LR Level Shift
V+ = 5.0V,ILR = 10 rnA
V+ = 18V, ILR = 110 rnA

rnA

ISp

60ITR

4a
4b

rnA
Vdc

60VLR
2.4
2.6

2.9
3.3

3.5
4.0

LC Terminal Resistance

5

RLC

30

50

75

kfl

Load Regulation

6

60VR

-20

-6.0

20

mVdc

2-187

MC34010A, MC34011 A
ELECTRICAL CHARACTERISTICS (continued)
SPEECH NETWORK
Charactaristic

Symbol

20

VMIC

Min

Typ

Max

Unh

60

125

mVdc

MIC Terminal Leakage Current

21a

IMIC

-

0.0

5.0

pA

MM Terminal Input Resistance

21b

RMM

50

100

170

kO

TXO Terminal Bias

22a

BTXO

0.48

0.53

0.68

-

TXI Terminal Input Bias Current

22b

ITXI

-

50

400

nA

TXO Terminal Positive Swing

22c

VTXO(+)

60

mVdc

22d

VTXO(-)

-

25

TXO Terminal Negative Swing

130

200

mVdc

Transmit Amplifier Closed-Loop Gain

23a

GTX

16.5

19

20

VN

Sidetone Amplifier Gain

23b

GSTA

0.40

0.45

0.54

VN

24

ISTA

50

100

250

pA

RXO Terminal Bias

25a

BRXO

0.48

0.52

0.68

25b

IRXI

100

400

nA

RXO Terminal Positive Swing

25c

VRXO(+)

1.0

20

mVdc

RXO Terminal Negative Swing

25d

VRXO(-)

-

-

RXI Terminal Input Bias Current

40

100

mVdc

TXL Terminal OFF Resistance

26a

RTXL(OFF)

125

200

300

kG

TXL Terminal ON Resistance

26b

RTXL(ON)

-

20

100

G

RM Terminal OFF Resistance

27a

RRM(OFF)

125

180

300

kG

RM Terminal ON Resistance

27b

RRM(ON)

410

570

770

G

MIC Terminal Saturation Voltage

•

Test
Method

STA Terminal Output Current

DTMF GENERATOR
Row Tone Frequency

Row
Row
Row
Row

1
2
3
4

11a,11b

fRm

692.9
765.3
848.9
935.1

696.4
769.2
853.2
939.8

699.9
773.0
857.5
944.5

Hz

Column
Column
Column
Column

1
2
3
4

11c,11d

fCn

1201.6
1330.2
1471.9
1625.2

1207.7
1336.9
1479.3
1633.4

1213.7
1343.6
1486.7
1641.5

Hz

Row Tone Amplitude

11e

VRow

0.38

0.45

0.55

V rms

Column Tone Amplitude

111

VCol

0.48

0.55

0.67

'V rms

Column Tone Pre-emphasis

11g

dBCR

0.5

1.8

3.0

dB

DTMF Distortion

12

% Dis

-

4.0

6.0

%

DTMF Output Resistance

13

Ro

1.0

2.5

3.0

kG

ES Terminal OFF Resistance

348

RES(OFF)

100

200

325

kO

Equilization Threshold Voltage

34b

VE

1.4

1.6

2.0

Vdc

Column Tone Frequency

EQUIUZATION CONTROL (MC34011A Only)

Equilization Threshold Hysteresis

34c

AVE

75

200

300

mVdc

EV Terminal OFF Resistance

35a

REV(OFF)

100

200

325

kG

EV Terminal ON Resistance

35b

REV(ON)

-

20

50

G

2-188

MC34010A, MC34011 A

FIGURE 16 -

FIGURE 17 -

TEST FIVE

TEST SIX

34

+

33

Circuit

With 5, open measure VLC.
Close 5, and measure 'LC.
Calculate:
5.0 - VLC
RLC = --'L-C-

FIGURE 18 -

(

'Rm

Set ISp = 0.0
Set ISp = 150

FIGURE 19 -

34

5,

+
General
Test
Circuit

VRI

0.0 JJA

2

4

JJA and measure YR.
JJA and measure YR. Calculate:

<1VR = VRI -

TEST SEVEN

3

l1.7V

General
Test

General
Test
Circuit

l5.0V

-

150 JJA

TEST EIGHT

34
5

+

if!

7

~.OV

8

6

l5.0V
General
Test
Circuit

-

-

-

Subscript m corresponds to row number.

a. Set 51 to Terminal 2 and measure voltage at Terminal 1
IVROC)·
b. Set 5, to Terminal' 1m = 1) and measure 'R1. Calculate:

Subscript n corresponds to column number.

a. Set 5, to Terminal 5 In = 1) and measure 'C1. Calculate:
RC, = 1.0V.;. IC1
b,c,d. Repeat Test 8a for n

RR1 = VROC .;. 'R'

c,d,e. Repeat Test 7b for m = 2,3,4.

2-189

=

2,3,4.

•

MC34010A, MC34011 A

FIGURE 20 -

TEST NINE

FIGURE 21 - TEST TEN

34

•

34

+
General
Test
Circuit

+

29

29

General
Test
Circuit

20

20
10 k

10 k

m corresponds to row number.

n corresponds to column number.

a. Set Sl to Terminal 5 (n = 1) with VI = 0 Vdc. Verify
VMIC is low (VMIC < 0.3 Vdc). Increase VI to 0.30 VROC
and verify VMIC switches high, (VMIC > 0.5 Vdc). VROC
is obtained from Test 7a.

a. Set SI to Terminal 1 (m = 1) with VI = 1.0 Vdc. Verify
VMIC is low (VMIC < 0.3 Vdc). Decrease VI to 0.70 VROC
and verify VMIC switches high. (VMIC > 0.5 Vdc). VROC
is obtained from Test 7a.
b,c,d. Repeat Test 9a for rows 2,3, and 4. (m

= 2,3,4)

b,c,d. Repeat Test lOa for columns 2,3, and 4. (n = 2,3,4)

FIGURE ZZ -

TEST ELEVEN

a. With VI = 0.0 V set Sl to Terminal 1 (m
measure frequency of tone at V +.
General
Test
Circuit

=

1) and

b. Repeat Test lla for rows 2,3 and 4. (m = 2,3,4).

V+

c. With VI = 1.0 V set SI to Terminal 5. (n
measure frequency of tone at V +.

=

d. Repeat Test for columns 2,3, and 4. (n

2,3,4).

=

1) and

e. Set SI to Terminal 4 and VI = 0.0 V. Measure row tone
amplitude at V + (VROW).
f. Set Sl to Terminal 8 and VI = 1.0 V. Measure column
tone amplitude at V +. (VcoLl.

m corresponds to row number.
n corresponds to column number.

g. Using results of Tests lIe and Ill, calculate:
VCOl
dBCR = 20 10910 VROW

2-190

MC34010A, MC34011 A

FIGURE 23 -

TEST TWELVE

FIGURE 24 -

600

TEST THIRTEEN

35

n

IS

34

5

~.OV

•

General
Test
Circuit

16

10 kHz Single
Pole lPF

Note: The notch filters must have 50 dB attenuation at their

Measure IS at V,

respective center frequencies.

Measure V+ and V, with a true rms voltmeter. Calculate:
V,(rms)
% DIS = V+(rms) x 100

FIGURE 25 -

= 1.8 V and VI = 2.8 V.

Calculate:
Ro

=

'.0 V

+[151 2.8V
- 151 1.8V ]

FIGURE 26 -

TEST FOURTEEN

...----.....,38

TEST FIFTEEN

...----.....,38

r-----,

f-=-=-........--.VTRI
37
General
Test
Circuit

37

•

a. Measure ITRS with V,
Set I

=

+

General
Test
Circuit

'.0 mA and measure VTRI.

=

24 V.

b. Measure ITRS with V, = 30 V.

2-191

MC34010A, MC34011 A

FIGURE 27 - TEST SIXTEEN

FIGURE 28 - TEST SEVENTEEN

r------,39

r------,40

38

38

~--~DVTRO

•

General
Test
Circuit

1-'-'----.>--0

37

General
Test
Circuit

a. Increase V1 from 21 V until VTRO switches on. Note that
VTRO will be an 16 Vpp square wave. Record this value
of V1' Calculate:

Measure ITRF. Calculate: RTRF = 1.0 + ITRF·

VTRF = V1 - 20 V
b. Decrease V1 from its setting in Test 16a until VTRO
ceases switching. Record this value of V1. Calculate:
dVTRF = V1

1-

Test
16a

V11

Test
16b

FIGURE 29 - TEST EIGHTEEN
VDD
110 k
.------.39

r-------.,

0.Q1 I'F

38
General
Test
Circuit

VDD

37

16
15 I--+-+-'
14 r---+---4~-f
. - - - - - - - t - - I 4 IC2 13
5
12 t---t---,
.-------i 6
11
L -_ _ _....~

~2V

.r

0V

7

8

VDD

5.1 k

5.1 k

Measure the frequencies

1
2
3

39 k

10 k

IC1 - MC14011B
IC2 - MC14538B
VDD = 12 V
T1 -2N3904

two fH. fL.

2-192

101----;----~_4KJJ

9

MC34010A, MC34011 A

FIGURE 30 - TEST NINETEEN

FIGURE 31 - TEST TWENTY

...----'39

1 - - - - - 0 VTRO

34

38
37
General
Test
Circuit

22 V I

•

I5.0V

General
Test
Circuit

Measure VTRO peak-to-peak voltage swing.
Using VTRI from Test '4 Calculate:

Measure VMIC

Vo(p-p) ~ VTRI - 20 V + VTRO

FIGURE 33 - TEST TWENTY-TWO

FIGURE 32 - TEST TWENTY-ONE

r-----.34

F-----.

34

VTXO

23
General
Test
Circuit
IMM

+

IMIC
+

General
Test
Circuit

'8
20

+
15.0V

22
VTXI

-

~"t

I

a. With 5, open, measure VTXO. Using VR obtained in Test
, Calculate: BTXO = VTXO -;- VR
a. Set V,

~

2.0 V and measure IMIC.

b. Set V, ~ 5.0 V and measure IMM.
Calculate: RMM ~ 5.0 V -;- IMM

b. With 5, open, measure VTXO and VTXI. Calculate:
ITXI = (VTXO - VTXI) -;- 200 k!1
c. Close 5, and set I = - 10 !lA. Measure VTXO. Calculate:
VTXO( +) = VR - VTXO where VR is obtained from
Test 1.
d. Close 51 and set I =
VTXO( -) = VTXO·

2-193

+ 10 !lA. Measure VTXO.

MC34010A, MC34011 A

FIGURE 34 - TEST TWENTY-THREE

FIGURE 35 - TEST TWENTY-FOUR
r------,34

34

•

General
Test

~-----.

24

VSTA +

23

VTXi[5.0 V

+
General
Test

.t'F~

Circuit

ISTA

24

Circuit

TXAC 2.0

+

..r.

f = 1.0 kHz

vi

~

L--_......I

"""""

a. Set the generator for vi = 3.0 mVrms . Measure ac
voltage VTXO. Calculate:
GTX =

3V

Measure ISTA.

YIxQ

vi
b. Measure ac voltage VSTA. Using VTXO from Test 23a
calculate:

G

-~

STA - VTXO

FIGURE 36 - TEST TWENTY-FIVE

FIGURE 37 - TEST TWENTY-SIX
....------.34

34

1------. +

+

-I:'OV

~.OV

General
Test
Circuit

27
26

-

ITXL

General
Test
Circuit

VRXO

S1

':.,-fo.

VRXI

4V

~~~~

S1?

~I

1.0 Vrms __
1.0 kHz

a. With S1 open, measure VRXO. Using VR obtained in Test
1, calculate: BRXO = VRXO + YR·
b. With S1 open, measure VRXO and VRXI. Calculate:
IRXI = (VRXO - VRX1) + 100 kG
c. Close S1 and set I = -10 pA. Measure VRXO. Using VR
obtained in Test 1, calculate: VRXO (+) = VR - VRXO.

a. Set S1 to position A with S2 open. Measure ITXL.
Calculate: RTXL (OFF) = 0.4 V + ITXL.
b. Set S1 to position B and close S2. Measure ac voltages vi
and VTXL. Calculate:
RTXL (ON) =

d. Close S1 and set I = + 10 pA and measure VRXO.
VRXO( -) = VRXO·

2-194

vii

..L

~V x 5.1
vi- TXL

kG

MC34010A, MC34011 A

FIGURE 38 -

TEST TWENTY-SEVEN

FIGURE 39 -

TEST TWENTY-EIGHT

r-----,34

1-'------,+

34

~.OV
General
Test

S1

Circuit

General
Test

~.OV

Circuit

l~ofQ.4V

VRM~

~ 2.0~F ~
~ ~Vi
-

1.0 Vrms
1.0 kHz

a. With S2 open and Sl in position
A measure 'RM.

a. Set V + = 1.4 V. Measure 'A(OFF)

Calculate: RRM(OFF) =0.4 V.;. IRM

b. Set V+

= 0.6 V.

Measure 'A(ON)

b. Close S2 and switch Sl to position B. Measure ac
voltages vi and VRM.
Calculate:
V
RRM(ON) = ~V x 10 k!l
vi - RM

FIGURE 40 -

TEST TWENTY-NINE

FIGURE 41 -

TEST THIRTY

12.-----' ~

r-------~

34

10

12

2.4~

General
Test
Circuit

14

~.6V

15

General
Test
Circuit

+
5.0V..I.

Measure VR/A+

l5.0V

Measure lin at each of three inputs. For each. calculate:
Rin = 5.0 Vllin

2-195

MC34010A, MC34011 A

FIGURE 42 -

FIGURE 45 - TEST THIRTY-FOUR

TEST THIRTY-ONE

r-~I-in-----'~2~----~

34

•

+
5.0 V..l

..lis ill:O V

1
+

34
General
Test
Circuit

General
Test
Circuit

+

2.0 V

32

v,
Measure lin.

FIGURE 43 -

a. Set V, = 0 V. Measure IES. Calculate R (OFF) = 0.4 .;IES·
b. Increase V, until YES SWITCHES low «200 mY). Measure V,. VE = V,.

TEST THIRTY-TWO

'2,..----,

,..--------1
9

+ 48 k

c. Decrease V, from the value in Test 34b until YES switches
high (>200 mY). Measure V,. Calculate 6.VE = V, - V,

34

11
'3

General
Test
Circuit

48k48k

+

+

Test 34b

~

Test 34c

5.0V..l

7-=--=--=a. Measure VOH at Pin 13.
b. Close

FIGURE 46 - TEST THIRTY-FIVE

5

34

S f S5')'

s,. measure VOH at Pin ".

c. Close S, and S5. Measure VOH
at Pin 9.

~

+

-::-

7

A

+
FIGURE 44 - TEST THIRTY-THREE

11

General
Test

13

Circuit

+

3.0

14

-::-

s,

B

:~:'F~

i

lV

@ 1.0 kHZ'l

15
J1...

~Jl:V
0.8 V

":"

a. With S, in position A set V,
late REV(OFF) = 0.4 - lEV.

VII0.l

7

'5
0.4 V

..1.5.0 V

-=+

v,

I "fl:.

34

r

General
Test
Circuit

ll.0 V

-::-

(-Itft '" 20 I'S

a. Set VDD to 0.8 V Measure VOL voltages at Pins 9 and ".
b. Close S,. Force VI/O to 0.8 V and VDD to 2.0 V. Apply
4 clock pulses to Pin '5. Open S, and decrease VDD to
0.8 V. Measure VOL at Pin '3.

":"

= 2.0 V.

Measure lEV Calcu-

b. Set V, = 5.0 V and Set S, to position B. Measure Vi and
vEV. Calculate
REV(ON)

= ~ x 600 n
Vi - vEV

APPLICATIONS INFORMATION
Figures 47 & 48 specify typical application circuits
for the MC34010A and MC34011A. Complete listings of
external components are provided at the end of this
section along with nominal component values.
The hook switch and polarity guard bridge configuration is one of several options. If two bridges are used,
one for the tone ringer and the other for speech and
dialer circuits. then the hook switch can be simplified.
Component values should be varied to optimize telephone performance parameters for each application.

2-196

The relationships between the application circuit components and certain telephone parameters are briefly
described in the following:
On-Hook Input Impedance
R1, C17, and Z3 are the significant components for
on-hook impedance. C17 dominates at low frequencies.
R1 at high frequencies and Z3 provides the non-linearity
required for 2.5 V and 10 V impedance signature tests.
C17 must generally be "" 1.0 JLF to satisfy 5.0 Hz impedance specifications. (EIA RS-470)

MC34010A, MC34011 A

Tone Ringer Output Frequencies
R3 and C13 control the frequency (fo) of a relaxation
oscillator. Typically fo = (R3C13 + 8.0 JLs)-l. The output tone frequencies are foil 0 and fo/8. The warble rate
is fo/S40. The tone ringer will operate with fo from 1.0
kHz to 10 kHz. R3 should be limited to values between
150 k and 300 k.

Sidetone Level
Sidetone reduction is achieved by the cancellation of
receiver amplifier input signals from R9 and R5. R8, R15,
and CS determine the phase of the sidetone balance
signal in R9. The ac voltage at the junction of R8 and
R9 should be 1800 out of phase with the voltage at V +.
RS is selected such that the signal current in R9 is
slightly greater than that in R5. This insures that the
sidetone current in the receiver adds to the transmit
amplifier output current.

Tone Ringer Input Threshold
After Rl, C17, and Z3 are chosen to satisfy on-hook
impedance specifications, R2 is chosen for the desired
ring start threshold. Increasing R2 reduces the ac input
voltage required to activate the tone ringer output. R2
should be limited to values between 0.8 k and 2.0 kn.
Off-Hook DC Resistance
R4 conducts the dc line current in excess of the speech
and dialer bias current. Increasing R4 increases the input resistance of the telephone for line currents above
10 mA. R4 should be selected between 30 nand 120 n.

Microprocessor Interface (MC34010A Only)
The six microprocessor interface lines (DP, TO, MS,
DD, I/O, and CL) can be connected directly to a port, as
shown in Figure 47. The DP line (Depressed Pushbutton)
is also connected to an interrupt line to signal the microprocessor to begin a read data sequence when storing a number into memory. The MC34010A clock speed
requirement is slow enough (typically 20 kHz) so that it
is not necessary to divide down the processor's system
clock, but rather a port output can be toggled. This facilitates synchronizing the clock and data transfer, eliminating the need for hardware to generate the clock.
The DD pin must be maintained at a Logic "0" when
the microprocessor section is not in use, so as to permit
normal operation of the keypad.
When the microprocessor interface section is not in
use, the supply voltage at Pin 12 (A +) may be disconnected to conserve power. Normally the speech circuitry is powered by the voltage supplied at the V +
terminal (Pin 34) from the telephone lines. During this
time, A + powers only the active pullups on the three
microprocessor outputs (DP, MS, and I/O). When the
telephone is "on-hook," and V + falls below O.S volts,
power is then supplied to the telephone speech and
dialer circuitry from A +. Powering the circuit from the
A + pin permits communication with a microprocessor,
and/or use of the transmit and receiver amplifiers, while
the telephone is "on-hook."

Off-Hook AC Impedance
The ac input impedance is equal to the receive amplifier load impedance (at RXO) divided by the receive
amplifier gain (voltage gain from V + to RXO). Increasing the impedance of the receiver increases the impedance ofthe telephone. Increasing the gain of the receiver
amplifier decreases the impedance of the telephone.
DTMF Output Amplitude
R14 controls the amplitude of the row and column
DTMFtones. Decreasing R14 increases the level of tones
generated at V +. The ratio of the row and column tone
amplitudes is internally fixed. R14 should be greater
than 20 n to avoid excessive current in the DTMF output
amplifier.
Transmit Output Level
Rl0 controls the maximum signal amplitude produced at V+ by the transmit amplifier. Decreasing Rl0
increases the transmit output signal at V +. Rl0 should
be greater than 220 n to limit current in the transmit
amplifier output.

Equalization of Speech Network (MC34011A Only)
Resistors R17 and R18 are switched into the circuit
when the voltage at the LR terminal exceeds the equalization threshold voltage (typically 1.S5 V). R17 reduces
the transmit and receive gains for loop currents greater
than the threshold (short loops) by attenuating signals
at tip and ring. R18 reduces the sidetone level which
would otherwise increase when R17 is switched into the
circuit. The voltage VLR at LR terminal is given by

Transmit Gain
The gain from the microphone to the telephone line
varies directly with Rll. Increasing Rl1 increases the
signal applied to R10 and the ac current driven through
Rl0 to the telephone line. The closed loop-gain from
the microphone to the TXO terminal should be greater
than 10 to prevent transmit amplifier oscillations.
Note: Adjustments to transmit level and gain are complicated by the addition of receiver sidetone current to the transmit amplifier output current at
V +. Normally the sidetone current from the receiver will increase the transmit signal (if the current in the receiver is in phase with that in Rl0).
Thus the transmit gain and sidetone levels cannot be adjusted independently.

VLR = ilL - IS) x R4.
where IL = loop current
IS = dummy load current (S.O mAl + speech
network current (4.0 mAl.
Thus resistor R4 is selected to activate the equalization circuit at the desired loop current. However, R4
must be selected keeping in mind the fact that it also
controls the dc resistance of the telephone. Capacitors
C18 and C19 prevent dc current flow into the EV and
ES terminals. This reduces clicks and also prevents
changes in the dc characteristic of the telephone when
the EV and ES terminals are switched to low impedance.

Receiver Gain
Feedback resistor RS adjusts the gain at the receiver
amplifier. Increasing RS increases the receiver amplifier
gain.

2-197

•

MC34010A, MC34011 A
FIGURE 47 -

DTMF Pad
Row-Column Switch Closure

•

S" S2 controlled
by hook switch; Illustrated
in "on-hook"
condition.

2

3

4
7

5 6

*

#

8
0

MC34010A ELECTRONIC TELEPHONE APPLICATION CIRCUIT

3

9

4

R1

TRF

R2

TRO

R3

TRI

R4

TRS

C1

TRC

C2

+C16

39
38
37
36

FB
V+

VCC

BP

33

1/0

32
LR
LC 31
30
V29
VR
28
CAL

DO

RXO

a:

RXI

«
0

TO

i

MS

MC6800
System

40

u

:::!!

A+

Z1

TIP

S1r1R1
R5

~

fC17

CR1
CR2

C~C~

19
20

MM

TXO

AGC

TXI

MIC

RING

TXL
Electret
Microphone

C3
+

mike only.
FIGURE 48 -

MC34011A ELECTRONIC TELEPHONE APPLICATION CIRCUIT
1

DTMF Pad
Row-Column Switch Closure

4
7

*

2

3

5

6
9
#

8
0

NC
S1, S21 controlled
by hook switch; Illustrated
in "on·hooklf
condition.

2
3

8
9
10
11
12

R1

TRF

R2

TRO

R3

TRI

R4

TRS

C1

TRC

C2

FB

C3

V+

C4

BP

40

+C16

39
38
37
36

33

13
14
15
R18

S1 rtR1
R5

~ fC17

ES
EV
CR1

R17
C19

TIP

32
MC34011 IA LR
31
LC
30
V29

+

20

CR2

SlA

MM

TXO

AGC

lXI

MIC

RING

TXL
Electret
Microphone

C3
C18

+

+

2-198

MC34010A, MC34011 A

EXTERNAL COMPONENTS
(Component Labels Referenced to Figures 47

Capacitors
Cl, C2
C3

Nominal
Value
100 pF
1.0 JLF, 3.0 V

& 48)

Description
Ceramic Resonator oscillator capaCitors.
Transmit limiter low-pass filter capacitor: controls attack and decay time of transmit peak limiter.

0.1 JLF

Transmit amplifier input capacitors: prevent dc current flow into TXL pin and attenuate low-frequency
noise on microphone lead.

C6

0.05 JLF

Sidetone network capacitor: provides phase-shift in sidetone path to match that caused by telephone
line reactance.

C7,C8

0.05 JLF

Receiver amplifier input capacitors: prevent dc current flow into RM terminal and attenuates low frequency
noise on the telephone line.

C4,C5

C9

2.2 JLF, 3.0 V

VR regulator capacitor: frequency compensates the VR regulator to prevent oscillation.

Cl0

0.01 JLF

Receiver amplifier output capacitor: frequency compensates the receiver amplifier to prevent oscillation.

Cll

0.1 JLF

DC load filter capacitor: prevents the dc load circuit from attenuating ac signals on V + .

C12

0.01 JLF

Telephone line bypass capacitor: terminates telephone line for high frequency signals and prevents
oscillation in the VR regulator.

C13

620 pF

Tone ringer oscillator capacitor: determines clock frequency for tone and warble frequency synthesizers.

C14

0.1 JLF

DTMF output feedback capacitor: ac couples feedback around the DTMF output amplifier which reduces
output impedance.

CIS

4.7 JLF, 25 V

Tone ringer input capacitor: filters the rectified tone ringer input signal to smooth the supply potential
for oscillator and output buffer.

C16

1.0JLF,10V

Tone ringer filter capacitor: integrates the voltage from current sense resistor R2 at the input of the
threshold detector.

C17

1.0 JLF, 250 Vac
Nan-polarized

Tone ringer line capacitor: ac couples the tone ringer to the telephone line; partially controls the anhook input impedance of telephone.

C18

25 pF, 25 V

Speech equalization coupling capacitor. Prevents dc current flow into SPE terminal. (optional)

C19

5.0 JLF, 3.0 V

Sidetone equalization coupling capaCitor. Prevents dc current flow into STE terminal. (optional)

Resistors

Nominal
Value

Description

Rl

6.8 k

Tone ringer input resistor: limits current into the tone ringer from transients on the telephone line and
partially controls the on-hook impedance of the telephone.

R2

1.8 k

Tone ringer current sense resistor: produces a voltage at the input of the threshold detector in proportion

R3

200 k

Tone ringer oscillator resistor: determines the clock frequency for tone and warble frequency synthesizers.

R4

82,1.0W

DC load resistor: conducts all de line current in excess of the current required for speech or dialing
circuits; controls the off-hook dc resistance of the telephone.

R5, R7

150k,56k

Receiver amplifier input resistors: couple ac input Signals from the telephone line to the receiver amplifier;
signal in R5 subtracts from that in R9 to reduce sidetone in receiver.

to the tone ringer input current.

R6
R8,R9
RIO
R11
R12, R13

200 k

Receiver amplifier feedback resistor: controls the gain of the receiver amplifier.

1.5 k, 30 k

Sidetone network resistors: drive receiver amplifier input with the inverted output signal from the transmitter; phase of signal in R9 should be opposite that in R5.

270

Transmit amplifier load resistor: converts output voltage of transmit amplifier into a current that drives
the telephone line; controls the maximum transmit level.

200 k
4.7 k, 4.7 k

Transmit amplifier feedback resistor: controls the gain of the transmit amplifier.
Transmit amplifier input resistors: couple signal from microphone to transmit amplifier; control the dynamic
range of the transmit peak limiter.
DTMF calibration resistor: controls the output amplitude of the DTMF dialer.

R14

36

R15

2.0 k

Sidetone network resistor (optional): reduces phase shift in sidetone network at high frequencies.

R17

600

Speech equalization resistor. Reduces transmit and receive gain when EV terminal switches on. (optional)

R18

5.1 k

Sidetone equalization resistor. Reduces sidetone level when ES terminal switches on. (optional)

RX

3.0 k

Microphone bias resistor: sources current from VR to power a 2-terminal electret microphone; RX is not
used with 3-terminal microphones.

2-199

•

MC34010A, MC34011 A

EXTERNAL COMPONENTS (continued)
Semiconductors

•

Bl = MDA101A, or equivalent,
or 4-1N4005
Tl = 2N4126 or equivalent
Zl = 18 V, 1.5 W, lN5931A
Z2 = 30 V, 1.5 W, lN5936A
Z3 = 4.7 V, 1/2 W, lN750
XR - muRata Erie CSB 500 kHz
Resonator, or equivalent
Piezo - PBl 5030BC Toko Buzzer
or equivalent

Electret Mic

Receiver

2 Terminal, Primo EM-95 (Use RX)
or equivalent
3 Terminal, Primo 07A181P (Remove RX)
or equivalent

Primo Model DH-34 (300 0) or equivalent

2-200

®

MC34012·1
MC34012·2
MC34012·3

MOTOROI.A
Advance Information

TELEPHONE
TONE RINGER

TELEPHONE TONE RINGER
•

Complete Telephone Bell Replacement CirCUit with M,nimum
External Components

•

On-Chip Diode Bridge and Transient Protection

•

Direct Drive for Piezoelectric Transducers

•

Base Frequency Optlons-MC34012-1 10kHz
MC34012-2 20kHz
MC34012-3. 500 Hz

BIPOLAR lINEAR/12l

N SUFFIX

PLASTIC PACKAGE
CASE 626-04

•

Input Impedance Signature Meets Bell and EIA Standards

•

Rejects Rotary Dial Transients

o SUFFIX
PLASTIC PACKAGE
CASE 751-01
SO-8

APPLICATION CIRCUIT

C

180k
...-_ _ _ _1'-1 RG

TIp
47 k
1.0 ~F
r--4'-_~~_~1-_ _+-___~2 AC1

8
RC 1-=--_--<.-_--'
5 O~F

7
RF 1-'--_--,
1 O~F

+ 10V
L-__--------+---~3~AC2

RSf-=-6_ _•

Ring

1.8 k
RI
Plezo Sound

Element

MC34012-1' C =1000 pF
MC34012-2: C = 500 pF
MC34012-3: C = 2000 pF

This document contams information on a new product SpecificatIOns and mformatlon herein
are subject to change Without notice

2-201

5

+ 25V

MC34012-1, MC34012-2, MC34012-3
CIRCUIT DESCRIPTION

•

produces a current through R3 which is input at terminal
RI. The voltage across resistor R3 IS filtered by capacitor
C3 at the Input to the threshold circuit. When the voltage
on capacitor C3 exceeds 1.7 volts, the threshold comparator enables the tone ringer output. Line transients
produced by pulse dialing telephones do not charge
capacitor C3 sufficiently to activate the tone ringer
output.
Capacitors Cl and C4 and resistor Rl determine the
10 volt, 24 Hz signature test Impedance. C4 also provides
filtering for the output stage power supply to prevent
droop In the square wave output signal. Six diodes In
series with the rectifying bridge prOVide the necessary
non-Ilneanty for the 2 5 volt. 24 Hz signature tests.
An internal shunt voltage regulator between the RI
and RG terminals provides dc voltage to power output
stage, OSCillator, and frequency diViders. The dc voltage
at RI is limited to approximately 22 volts in regulation To
protect the IC from telephone line tranSients, an SCR is
tnggered when the regulator current exceeds 50 mAo
The SCR diverts current from the shunt regulator and
reduces the power dissipation within the IC.

The MC34012 Tone Ringer derives its power supply by
rectifYing the ac ringing signal. It uses this power to
activate a tone generator and dnve a plezo-ceramic
transducer. The tone generation circuitry includes a
relaxation oscillator and frequency dividers which
produce high and low frequency tones as well as the
tone warble frequency. The relaxation oscillator frequency fo IS set by resistor R2 and capacitor C2
connected to pin RC. The oscillator will operate with fo
from 1.0 kHz to 10kHz with the proper choice of external
components (See Figure 11.
The frequency of the tone ringer output signal at pin
RO alternates between fo/4 to fo/5. The warble rate at
which the frequency changes is fo/320 for the
MC34012-1, fo/640 for the MC34012-2, or fo/160 for
the MC34012-3. With a 4.0 kHz oscillator frequency, the
MC34012-1 produces 800 Hz and 1000 Hz tones with a
12.5 Hz warble rate. The MC34012-2 generates 1600 Hz
and 2000 Hz tones with a similar 12.5 Hz warble
frequency from an 8.0 Hz oscillator frequency. The
MC34012-3 will produce 400 Hz and 500 Hz tones with
a 12.5 Hz warble rate from a 2.0 kHz oscillator frequency.
The tone ringer output Circuit can source or sink 2.0 mA
with an output voltage sWing of 20 volts peak-to-peak.
Volume control is readily implemented by adding a
vanable resistance in senes with the piezo transducer.
Input signal detection circUitry activates the tone
ringer output when the ac line voltage exceeds
programmed threshold level. Resistor R3 determines the
ringing signal amplitude at which an output signal will
be generated at RO. The ac nnglng signal is rectified by
the internal diode bndge. The rectified Input signal

EXTERNAL COMPONENTS

Al

Line Input resistor. Rl controls the tone
ringer input impedance. It also Influences
ringing threshold voltage and limits current
from line transients.

(Range· 20 kll to 10 kfll.
Cl

FIGURE 1 - OSCILLATOR PERIOD (1/101 versus
OSCILLATOR R2 C2 PRODUCT

Line input capacitor. C1 ae couples the tone
ringer to the telephone line and controls
ringer Input Impedance at low frequencies

(Aange· 04 I'F to 2 OI'FI
R2

Oscillator reSistor.

(Aange· 150 kll to 300 kill
C2
80 0

A3
,/"

1, 600

/'"
C3

/'"

....- /
100

/'"

Input current sense resistor. R3 controls the
ringing threshold voltage. IncreaSing R3
decreases the ring-start voltage.

(Range: 0.8 kll to 2.0 kill.

/1--"

200

Oscillator capacitor.

(Range: 400 pF to 2000 pFI.

150k,;;R2';;300k
_ I---400 pF ,;; C2 ,;; 2000 pF

Ringing threshold filter capacitor C3 filters the
ae voltage across R3 at the Input of the ringing
threshold comparator. It also proVides dialer
transient rejection.

(Aange: 0.5 I'F to 5.0 I'FI.
200

300

400

500

R2C2 (I'sl

C4

Ainger supply capacitor. C4 filters supply
voltage for the tone generating CirCUits. It also
provides an ae current path for the 10 V rms
ringer signature impedance.

(Aange: 1 0 I'F to 10 I'FI.

2-202

MC34012-1, MC34012-2, MC34012-3
FIGURE 2 - TEST ONE

180 k*

C

8
RC

RG
VI

47 k*

7

2

RF

ACl
OUT

3

AC2

0.01 !iF
RS

6
MC34012-1: C = 1000 pF*
MC34012-2: C = 500 pF*
MC34012-3: C = 1000 pF*

1.8 k*

390 II
RO

1.0 !iF
+ 25 V

RI

5

0.047/'F
Yo / S l

VOO

10 k

1

a. Increase VI from +30 volts while monitoring
Va. VStart(+) equals VI when YO commences

~NOrmailY open)

sWItching.

o l/,F

b. Decrease VI from -30 volts while monitoring
VO· VStartH equals VI when Va commences

51 k

sWitching.

c. Oecrease VI from +40 volts while monitoring
YC· VStop equals VI when Va ceases
switching.
d. Set VI to +50 volts. Close 51. Measure
frequencies fH. fL. and

two

200 k

O.OlI'F

L-'-~"""""'11
L -______________________~~lcl)D--~io)fH

IC1-MC14011 B
IC2-MC145388
VOO = 12 V
MC34012-1:
MC34012-2:
MC34012-3:

*Indrcates 1 % tolerance
(5% otherwise)

2-203

R = 110kn*
R = 55 kn*
R = 110 kO*

MC34012-1, MC34012-2, MC34012-3
FIGURE 3 - TEST TWO

180 k'

•

RC

RG
2

"::'

RF

6

AC2

RS

RO

RI

001

~F

I

12 V

I

10V

f--------.---;-\. I ~"::'

"::'

4

2.0 k

Sl~

7

ACl
OUT

3

C

8

5

18k'

~----~~~~~I~

With VRC ~ 3.5 volts. close S 1. Measure the
current at Pm 4 (101) Repeatedly SWitch VRC
between 3.5 volts and 0 volts until Pm 4 current
changes polarity Measure this Opposite polarity
current (102)
Calculate
10 0

1011 +, 102

'0
+

-=- 5.0V

MC34012-1: C ~ 1000 pF'
MC34012-2 C ~ 500 pF'
MC34012-3 C ~ 1000 pF"

I

*Indlcates 1 % tolerance (5% otherWise)

FIGURE 4 - TEST THREE

180k

C

8

VOO
2

3

ACl

RF

AC2

RS

RO

RI

7
Measure voltage at Pin 2

"::'

4
"::'

0.0471'F
MC34012-1: C~l000pP
MC34012-2' C ~ 500 pF"
MC34012-3 C ~ 1000 pF'
-Indicates 1 % tolerance (5% otherWise)

2-204

MC34012-1, MC34012-2, MC34012-3
ELECTRICAL CHARACTERISTICS (TA = 25"C)
Characteristic

Test

Ringing Start Voltage
(VS tart =VI @ Ring Start)
VI>O
VI---vvv-I

I

I

I
I
I

Ring )-----\>-:-=-.....----'
Threshold
Comparator

I
I
I

I
I
RO

I
Piezo
Sound
Element

2-205

•

. MC34012-1, MC34012-2, MC34012-3
APPLICATION CIRCUIT PERFORMANCE
Characteristic
Output Tone Frequencies
MC34012-1
MC34012-2
MC34012-3
Warble Frequency

•

Output Voltage
(VI;;;' 60 Vrms• 20 Hz)

Typical Value

Units

83211040
166412080
416/520
13

Hz

20

V p_p

Output Duty Cycle

50

%

Ringing Start Input Voltage (20 Hz)

36

Vrms
Vrms
Vrms

Ringing Stop Input Voltage (20 Hz)

28

Maximum ac Input Voltage (.;; 68 Hz)

150

Impedance When Ringing
VI = 40V rms• 15Hz
VI = 130 V rms• 23 Hz

20
10

kn

Impedance When NofRinging
VI = 10Vrms. 24 Hz
VI = 2.5 V rms• 24 Hz
VI = 10 Vrms• 5.0 Hz
VI = 3.0 \irm~. 200-320.0 Hz
Maximum Transient Input Voltage
(T';; 2:0 ms)

28
>1.0
55
>1.0

kn
Mn
kn
Mn

1500

V

PIN DESCRIPTIONS
Description

Name

AC1.AC2

The input termjnals to the full-wave diode bridge. T~e ae ringing signal from the telephone hne
energizes the ringer through this bridge.

RS

The positive output of diode bridge to which an external current sense resistor is connected,

RI

The positive supply terminal for the oscillator, frequency divider and output buffer Circuits.

RF

The terminal for the filter capacitor used in detection of ringing input signals.

RO

The tone ringer output terminal through which the sound element is driven.

RG

The negative output of the diode bridge and the negative supply terminal of the tone generating

RC

The oscillator terminal for the external resistor and capacitor which control the tone ringer
frequencies.

circuitry.

2-206

MC34012-1, MC34012-2, MC34012-3
FIGURE 5 - TEST FOUR

c

'80 k
8

v
2

a. Sel1110 30 mA. Measure vollage at Pin 2
(Voff)·
b. Set II to 100 mA. Measure voltage at Pin 2
(Von)·

7

AC,

RF
OUT

0.01

6

3
AC2

RS

RO

RI

~F

1.8 k'

5

MC34012-1: C; 1000 pF'
MC34012-2: C; 500 pF'
MC34012-3: C; 1000 pF'
*Indicates 1 % tolerance (5% otherwise)

FIGURE 6 - TEST FIVE

180 k'

C

8

2

ACl

RF

7

OUT
3

AC2

-;:

390 !l
0.047

4
~F

RO

I

6
+
20V
RS I------<~----+'-f I ~_
1.8 k'
5
+
18V
RI 1----+-'-1I~

Measure current into Pin 7 (IRF).
Calculate:
RRF ; 2 volts + IRF

I

MC34012-1: C; 1000 pF'
MC34012-2: C; 500 pF'
MC34012-3: C; 1000 pF'
*Indicates 1% tolerance (5% otherwise)

2-207

MC34012-1, MC34012-2, MC34012-3
FIGURE 7 - TEST SIX

180 k*

•

RC

RG

-= 4.7 k*
VI

10k

2

RF
ACI

3 AC2

-=

C
2k

8

SI~

7
VRC

OUT
RS 6

om

~F

J

With VRC =3 5 volts. close SI Set VI to 50
volts Measure dc voltage at Pm 4 (VO 11.
Repeatedly change VRC between 3.5 volts and
o volts unt,1 Pin 4 changes state. Measure the
new voltage at Pin 4 (V021.
Calculate the peak-ta-peak output voltage

VO p-p

=I V02 - VOl I

1.8 k*
4

RO

RI

5

Vo

-=- 10V

I

MC34012-1. C =1000 pF*
MC34012-2. C = 500 pP
MC34012-3' C = 1000 pF'

2-208

-Indicates 10;0 tolerance (5% otherwise)

®

MC34013A

MOTOROI.A

TELEPHONE SPEECH NETWORK AND TONE DIALER

SPEECH NETWORK
AND
TONE DIALER

• Linear/1 2 l Technology Provides low 1.4 Volt Operation in Both
Speech and Dialing Modes

BIPOLAR L1NEAR/12l

• Speech Network Provides 2-4 Wire Conversion with Adjustable
Sidetone Utilizing an Electret Microphone
• DTMF Generator Uses low-Cost Ceramic Resonator with Accurate Frequency Synthesis Technique
• On-Chip Regulator Insures Stable Operation Over Wide Range
of loop lengths
• Dialer Mutes Speech Network with Internal Delay for Click
Suppression on DTMF Key Release

,.~
28-PIN
QUAD PACK
CASE 776-01

FIGURE 1 -

1

P SUFFIX
PLASTIC PACKAGE
CASE 710-02

FUNCTIONAL BLOCK DIAGRAM

Ceramic

Resonator

Hook
Switch

4

2

3

A

5

6

B

8

9

C

0

#

D

MC34013A

Line

Keypad

.,:;

Voltage
Regulator
IVREGI

'------0 Ring

~

Speech
Network

=
Electret
Microphone

Receiver

2-209

•

MC34013A
PIN CONNECTIONS

MAXIMUM RATINGS (Voltage References to V-)
Parameter

•

Value

Unit

V + Terminal Voltage (Pin 26)

+18, -1.0

V

VR Terminal Voltage (Pin 22)

+2.0, -1.0

V

RXO Terminal Voltage (Pin 20)

+2.0, -1.0

Rl-R4 Terminal Current (Pins 1-4)
Cl-C4
(Pins 5-8)

Rl
R2
R3
R4
Cl
C2
C3
C4
CR2
CRl
AGC
MM
MIC
TXL

V

±100

rnA

Operating Ambient Temperature Range

-20 to +60

"C

Storage Temperature Range

-65to +150

"C

GENERAL CIRCUIT DESCRIPTION
The MC34013A Electronic Speech Network and Tone
Dialer provides a frequency synthesizer for DTMF dialing, analog amplifiers for speech transmission and a
dc line interface circuit that terminates the telephone
line. When mated with the MC34012 Tone Ringer, a
complete tone dialing telephone can be produced with
just two ICs.
low voltage operation is a necessity for telephones
in networks where parallel telephone connections are
common. An electronic speech network operating in
parallel with a conventional telephone may receive line
voltages below 2.5 volts. DTMF dialers operate at similarly low-line voltages when signaling through battery
powered station carrier equipment. These low voltage
requirements have been addressed by realizing the
MC34013A in a bipolar/1 2 l technology with appropriate
circuit techniques. The resulting speech and dialer circuits maintain specified performance with instantaneous input voltage as low as 1.4 volts.

FB
LC
V+
BP
LR
VVR
CAL
RXO
RXI
RM
STA
TXO
TXI

and dialer bias currents through the VR regulator. As
input voltage increases, 01 conducts the excess dc line
current through resistor R12. The 1.5 volt level shift
prevents saturation of 02 with telephone line signals
up to 2.0 volts peak (+ 5.2 dBm). A constant current
(dummy load) is switched off when the DTMF dialer is
activated to reduce line current transients. Figure 3 illustrates the dc voltage/current characteristic of an
MC34013A telephone.
Speech Network
The speech network (Figure 4) provides the two-tofour wire interface between the telephone line and the
instrument's transmitter and receiver. An electret microphone biased from VR drives the transmit amplifier.
For very loud talkers, the peak limiter circuit reduces
the transmit input level to maintain low distortion. The
transmit amplifier output signal is inverted at the STA
terminal and driven through an external R-C network to
control the receiver sidetone level. The switched ac resistance at the RM terminal reduces receiver signal

line Voltage Regulator
The dc line interface circuit (Figure 2) determines the
dc input characteristic of the telephone. At low input
voltages (less than 3 volts) the IC draws only the speech

FIGURE 3 - DC V-I CHARACTERISTIC
FIGURE 2 - DC LINE INTERFACE BLOCK DIAGRAM
7.0

r---- - - --- -- -- - ------ - -lTelephone
LC

i

Line

0>

SUi

6.0

g

"0 -

~
5.0
x-

w'"
Q)~

I
I
I
I

I

I

.g 4.0

~~

~ ~ 3.0
'" !?

..J

Q

I
IL ______________________ I
~

20

1.0

10

20

30

40

Line Current (mAl

2-210

50

60

120

MC34013A

GENERAL CIRCUIT DESCRIPTION (continued)
FIGURE 4 -

Z1

SPEECH NETWORK BLOCK DIAGRAM

__

rJ~·_~1~ I~_,
:

~

ITxo

I

Transmit

I

I

S,detone

Amplifier

:
STAI

I

I

:

C9

R4

-ITXO
R3

I TXI

r----i

R2

Telephone
Line

C3

I Telephone I
I
Handset I
I
I

I
I
I
I
I

>

'-----"---0----1

I

I

I Electret
I
I Microphone I

I
t-'r-_+--' I
V~

RXO

C10

I
I

--IRXO

L_R~~i.v~.J

I

R9

when dialing and suppresses clicks due to hook or keypad switch transitions. When transmitting, audio signal
currents (iTXO and iRXO) flow through the voltage regulator pass transistor (T1) to drive the telephone line.
This feature has two consequences: 1) In the transmitting mode the receiver sidetone current iRXO contributes to the total signal on the line along with iTXO;
2) The ac impedance of the telephone is determined by
the receiver impedance and the voltage gain from the
line to the receiver amplifier output.

DTMF Dialer
Keypad interface comparators activate the DTMF row
and column tone generators (Figure 5) when a row and
column input are connected through a SPST keypad.

2-211

The keypad interface is designed to function with contact resistances up to 1.0 kn and leakage resistances as
low as 150 kn. Single tones may be initiated by depressing two keys in the same row or column.
The programmable counters employ a novel design
to produce non-integer frequency ratios. The various
DTMF tones are synthesized with frequency division
errors less than :!:0.16% (Table 1). Consequently an inexpensive ceramic resonator can be used instead of a
quartz crystal as the DTMF frequency reference. Total
frequency error less than :!: 0.8% can be achieved with
:!:0.3% ceramic resonator. The row and column D/A
converters produce 16-step approximations of sinusoidal waveforms. Feedback through terminal FB reduces the DTMF output impedance to approximately
2.0 kn to satisfy return loss specifications. (EIA RS-470)

•

MC34013A
FIGURE 5 -

DTMF DIALER BLOCK DIAGRAM

r------------------------,I

I

I

I

C1 I

I

iFB

.-------~C2~1--~
C3 I

•

C13

Keypad
Comparators
& Logic

•

Telephone
Line

5 6 B
R3
8 9 C
R4
0 # D
Keypad

+-_______-+-I~

Mute Signal to
Speech Network

0
L------------------l------~
C1~XR~C2
CR1

CR2

V-

TABLE 1 -

Row
Row
Row
Row

FREQUENCY SYNTHESIZER ERRORS

DTMF
Standard
(Hz)

Tone Output
Frequency with
500 kHz Oscillator

697
770
852
941

696.4
769.2
853.2
939.8

-0.086
-0.104
+0.141
-0.128

1209
1336
1477
1633

1207.7
1336.9
1479.3
1634.0

-0.108
+0.067
+0.156
+0.061

1
2
3
4

Column
Column
Column
Column

ELECTRICAL CHARACTERISTICS ITA
LINE VOLTAGE REGULATOR
Characteristic
Voltage Regulator Output

1
2
3
4

% Deviation
from Standard

= 25"<:)
Test
Method

Symbol

Min

Typ

Max

Unit

1a

VR

1.0

1.1

1.2

Volts

V + Current in DTMF Mode

2a

lOT

8.0

12

14.5

rnA

Change in lOT with Change in V + Voltage

2b

.l.IOT

-

0.8

2.0

rnA

3.0
8.0

5.0
11

7.0
15

-2.0

2.0

3.5

V + Current in Speech Mode
V+ = 1.7V
V+ = 5.0 V

1b
1c

Speech to DTMF Mode Current Difference

3

LR Level Shift
V+ = 5.0V.ILR = 10mA
V+ = 18 V. ILR = 110 rnA

rnA

ISp

.l.ITR

4a
4b

rnA
Vdc

tlVLR
2.4
2.6

2.9
3.3

3.5
4.0

LC Terminal Resistance

5

RLC

30

50

75

kO

Load Regulation

6

t.VR

-20

-6.0

20

mVdc

2-212

MC34013A
ELECTRICAL CHARACTERisTICS (continued)
KEYPAD INTERFACE CIRCUIT
Test
Method

Symbol

Min

Typ

Max

Unit

Row Input Pullup Resistance
mth Row Terminal: m = 1,2,3,4

7

RRm

5.0

8.0

11

kG

Column Input Pulldown Resistance
nth Column Terminal: n = 1,2,3,4

8

RCn

5.0

8.0

11

kG

7&8

Km,n

0.88

1.0

1.12

Row Terminal Open Circuit Voltage

7a

VROC

950

1100

1200

Row Threshold Voltage for mth
Row Terminal: m = 1,2,3,4

9

VRm

0.70 VROC

-

-

Vdc

Column Threshold Voltage for nth
Column Terminal: n = 1,2,3,4

10

VCn

-

-

0.30 VROC

Vdc

l1a,11b

fRm

692.9
765.3
848.9
935.1

696.4
769.2
853.2
939.8

699.9
773.0
857.5
944.5

Hz

1lc, l1d

fCn

1201.6
1330.2
1471_9
1625.2

1207.7
1336.9
1479.3
1633.4

1213.7
1343.6
1486.7
1641.5

Hz

Characteristic

Ratio of Row-to-Column Input Resistances
Bam, m = 1,2,3,4
Km,n =
RCn n = 1,2,3,4

mVdc

DTMF GENERATOR
Row Tone Frequency

Row
Row
Row
Row

1
2
3
4

Column Tone Frequency

Column 1

Column 2
Column 3
Column 4
Row Tone Amplitude

l1e

VRow

0.38

0.45

0.55

Vrms

Column Tone Amplitude

111

VCol

0.48

0.55

0.67

Vrms

Column Tone Pre-emphasis

l1g

dBCR

0.5

1.8

3.0

dB

DTMF Distortion

12

% Dis

-

4.0

6.0

%

DTMF Output Resistance

13

Ro

1.0

2.5

3.0

kG

MIC Terminal Saturation Voltage

14

VMIC

-

60

125

mVdc

MIC Terminal Leakage Current

15a

IMIC

-

0.0

5.0

!lA

MM Terminal Input Resistance

15b

RMM

50

laO

170

kG

TXO Terminal Bias

16a

BTXO

0.48

0.56

0.68

-

TXI Terminal Input Bias Current

16b

ITXI

-

50

400

nA

TXO Terminal Positive Swing

16c

VTXO(+)

60

mVdc

16d

VTXO(-)

-

25

TXO Terminal Negative Swing

130

200

mVdc

SPEECH NETWORK

Transmit Amplifier Closed-Loop Gain

17a

GTX

16.5

19

20

VN

Sidetone Amplifier Gain

17b

GSTA

0.40

0.45

0.54

VN

STA Terminal Output Current

18

ISTA

50

laO

250

!lA

RXO Terminal Bias

19a

BRXO

0.48

0.56

0.68

-

RXI Terminal Input Bias Current

19b

IRXI

-

lOa

400

nA

RXO Terminal Positive Swing

19c

VRXO(+)

20

mVdc

19d

VRXO(-)

-

1.0

RXO Terminal Negative Swing

40

lOa

mVdc

TXL Terminal OFF Resistance

20a

RTXL(OFF)

125

200

300

kG

TXL Terminal ON Resistance

20b

RTXL(ON)

-

20

100

n

RM Terminal OFF Resistance

21a

RRM(OFF)

125

180

300

kn

RM Terminal ON Resistance

21b

RRM(ON)

410

570

770

n

2-213

•

MC34013A
PIN DESCRIPTION
(See Figure 28 for
Pin

•

extern~1

component identifications.)

Designation

Function

1-4

Rl-R4

Keypad inputs for Rows I through 4. When open, internal S.O kn resistors pull up the row inputs to a
regulated (=1.1 volt) supply. In normal operation, a row and a column input are connected through a
SPST switch by the telephone keypad. Row inputs can also be activated by a Logic "0" «500 mV) from
a microprocessor port.

5-8

Cl-C4

Keypad inputs for Columns 1 through 4. When open, internal 8.0 kn resistors pull down the column
inputs to V - .In normal operation, connecting any column inpulto any row input produces the respective
row and column DTMF tones. In addition to being connected to a row input, column inputs can be
activated by a Logic "1" (>500 mV and <3.0 volt).

10,9

CR1, CR2

Ceramic Resonator oscillator input and feedback terminals, respectively. The DTMF dialer is intended to
operate with a 500 kHz ceramic resonator from which row and column tones are synthesized.

II

AGC

Automatic Gain Control low-pass filter terminal. Capacitor C3 connected between AGC and VR sets the
attack and decay time of the transmit limiter circuit. This capaCitor also aids in reducing clicks in the
receiver due to hook-switch transients and DTMF on/off transients. In conjunction with internal resistors.
C3 (1.0 I'F) forms a timer which mutes the receiver amplifier for approximately 20 milliseconds after the
user goes off-hook or releases a DTMF Key.

12

MM

Microphone Mute. The MM pin provides a means to mute the microphone and transmit amplifier in
response to a digital control signal. When this pin is connected to a Logic "1" (>2.0 VI the microphone
dc return path and the transmit amplifier output are disabled.

13

MIC

MICrophone negative supply terminal. The dc current from the electret microphone is returned to Vthrough the MIC terminal which is connected to the collector of an on-chip NPN transistor. The base of
this transistor is controlled either internally by the mute signal from the DTMF generator, or externally
by the logic input pin MM.

14

TXL

Transmit Input Limiter. An internal variable resistance element althe TXL terminal controls the transmitter
input level to prevent clipping with high signal levels. Coupling capacitors C4 and C5 prevent de current
flow through TXL. The dynamic range of the transmit peak limiter is controlled by resistors Rl and R2.

15

TXI

Transmit Amplifier Input. TXI is the input to the transmit amplifier from an electret microphone. AC
coupling capacitors allow the de offset at TXI to be maintained approximately 0.6 V above V - by feedback
through resistor R3 from TXO.

16

TXO

Transmit Amplifier Output. The transmit amplifier output drives ac current through the voltage regulator
pass-transistor Tl via resistor R4. The de bias voltage at TXO is typically 0.6 volts above V -. The transmit
amplifier gain is controlled by the R3/(Rl + R2) ratio.

17

STA

SideTone Amplifier output. STA is the output of the sidetone inverter amplifier whose input is driven
by the transmit signal at TXO. The inverted transmit signal from STA subtracts from the receiver amplifier
input current from V +, thus reducing the receiver sidetone level. Since the transmitted signal at V + is
phase shifted with respect to TXO by the reactive impedance of the phone line, the signal from STA
must be similarly phase-shifted in order to provide adequate sidetone reduction. This phase relationship
between the transmit signal at TXO and the sidetone cancellation signal from STA is controlled by R5,
R6, and C6.

IS

RM

Receiver Amplifier Mute. A switched resistance at the RM terminal attenuates the receiver amplifier
input signal produced by DTMF dialing tones at V +. RM also mutes clicks at the receiver which result
from keypad or hook switch transitions. The ac resistance at RM is typically 540 n in the mute mode
and 200 kn otherwise. Coupling capacitors C7 and CS prevent de current flow through RM.

19

RXI

Receiver Amplifier Input. RXI is the input terminal of the receiver amplifier which is driven by ac signals
from V+ and STA. Input coupling capacitor CS allows RXI to be biased approximately 0.6 volts above
the V - via feedback resistor R9.

20

RXO

Receiver Amplifier Output. This terminal is connected to the open-collector NPN output transistor of the
receiver amplifier. DC bias current for the output device is sourced through the receiver from VR. The
bias voltage at RXO is typically 0.6 volts above the V -. Capacitor Cl0 from RXO to VR provides frequency
compensation for the receiver amplifier.

2-214

MC34013A
PIN DESCRIPTION (continued)
Pin

Designation

21

CAL

22

VR

Function

Amplitude CALibration terminal for DTMF dialer. Resistor Rl1 from the CAL pm to V - controls the DTMF
output signal level at Tip and Ring.
Voltage Regulator output terminal. VR

IS

the output of a 1.1 volt voltage regulator which supplies power

to the speech network amplifiers and DTMF generator during signaling. To Improve regulator efficiency
at low line current conditions, an external PNP pass·transistor T1 is used in the regulator circuit. Capacitor
C9 frequency compensates the VR regulator to prevent oscillation.

23

V-

The dc common (more negative input) connected to Tip and Rmg through the polarity guard bridge.

24

LR

DC Load Resistor. Resistor R12 from LR to V - determines the dc input resistance at Tip and Ring. This
resistor is external not only to enable programming the de resistance but also to avoid high on-chip
power dissipation with short telephone lines. It acts as a shunt load conducting the excess de line current.

At low line voltages «3.0 volts), no current flows through LR.
25

BP

Base of a PNP Pass-transistor. Under long-loop conditions where low line voltages would cause VA to
fali below 1.1 volts, BP drives the PNP transistor Tl into saturation, thereby minimizing the voltage drop
across the pass transistor. At line voltages which maintain VR above 1.1 volts, BP biases Tl in the linear
region thereby regulating the VR voltage. Transistor T1 also couples the ac speech signals from the
transmit amplifier to Tip and Ring at V +.

26

V+

The more positive input to the regulator, speech, and DTMF sections connected to Tip and Ring through
the polarity guard diode bridge.

27

LC

DC Load Capacitor. Capacitor Cl1 from LC to V - forms a low-pass filter which prevents the resistor at
LA from loading ac speech and DTMF signals.

28

FB

FeedBack terminal for DTMF output. Capacitor C13 connected from FB to V+ provides ac feedback to
reduce the output impedance to Tip and Ring when tone dialing.

FIGURE 6 - GENERAL TEST CIRCUIT

~-

4
5

6

Rl

FB

R2

LC

R3

V-

R4

BP

C1

LR

C2

V
OUT

C3
8

100 PF

1 .=

r

100 pF

10
11
12
13
14

27
26
25
24
23

VR

C4

CAL

CR2

RXD

CRl

RXI

AGC

RM

MM

STA

MIC

TXO

TXL

lXI

Notes:

28

18
17
16
15

200 k

~--~--~VV~---,---oTXAC

10 k

1. *Selected ceramic resonator: 500 kHz ± 2.0 kHz.
2. Capacitances in ,uF unless noted.
3. All resistances in ohms.

2-215

I

MC34013A

FIGURE 7 -

FIGURE 8 -

TEST ONE

TEST TWO

•

lOT

26

26

600

n

5
General
Test
Circuit

+

a. Measure VR with Vs

1.7 V

=

a. Measure lOT with Vs = 11.5 V

b. Measure ISp with Vs = 1.7 V
c. Measure ISp with Vs

FIGURE 9 -

=

General
Test
Circuit

b. Measure lOT with Vs = 26 V. Calculate
alOT = lOT
lOTI
26V
11.5V

I-

5.0 V

FIGURE 10 -

TEST THREE

TEST FOUR

S1

r-o
-

~OV
l

26

26
600

I

I

n

+

General
Test
Circuit

General
Test
Circuit

With 51 open measure ITR. Close 51 and again measure
ITR. Calculate:

a. Set Vs = 5.0 V and ILR = 10 mA. Measure VLR·
Calculate aVLR = Vs - VLR

alTR = ITR / - ITR/
51
51
Closed
Open

b. Repeat Test 4a with Vs

2-216

=

18 V and ILR

=

110 mA

MC34013A

FIGURE 11 -

TEST FIVE

FIGURE 12 -

TEST SIX

26
25

5.0 V
General
Test

General
Test

Circuit

Circuit

+

1.7 V

t-2_2_ _ _-U VR

With Sl open measure VLC.
Close Sl and measure ILC.
Calculate:
5.0 - VLC
RLC = --IL-C-

FIGURE 13 -

(

IRm

Set IBP = 0.0 pA and measure VR.
Set IBP = 150 pA and measure VR. Calculate:

~VR

26

General
Test
Circuit

5

~

l5.0V

-

TEST EIGHT

26

Sl

+
3

VRI
0.0 pA 150 pA

FIGURE 14 -

TEST SEVEN

2

4

= VRI -

+
6

~.OV

l5.0V

7

General
Test

8

Circuit

-

Subscript m corresponds to row number.

Subscript n corresponds to column number.

a. Set Sl to Terminal 2 and measure voltage at Terminal 1
IVROC)·
b. Set Sl to Terminal 1 1m = 1) and measure IR1. Calculate:
RRl = VROC -i- IRl
c,d,e. Repeat Test 7b for m

=

2,3,4.

2-217

a. Set Sl to TerminalS In = 1) and measure IC1. Calculate:
RCl

=

1.0 V

-i-

ICl

b,c,d. Repeat Test 8a for n = 2,3,4.

•

MC34013A

FIGURE 15 -

TEST NINE

FIGURE 16 -

TEST TEN

26

•

26

+

22
General
Test

22

General
Test

Circuit

Circuit

13

13

10 k

10 k
m corresponds to row number.

n corresponds to column number.

a. Set Sl to Terminal 1 (m = 11 with VI = 1.0 Vdc. Verify
VMIC is Low (VMIC < 0.3 Vdcl. Decrease Vl to 0.70 VROC
and verify VMIC switches high. (VMIC > 0.5 Vdcl. VROC
is obtained from Test 7a.

a. Set Sl to Terminal 5 (n = 11 with Vl = 0 Vdc, Verify
VMIC is low (VMIC <0.3 Vdcl. Increase VI to 0.30 VROC
and verify VMIC switches high, (VMIC > 0.5 Vdcl. VROC
is obtained from Test 7a.

b,c,d. Repeat Test 9a for rows 2,3, and 4. (m

b,c,d. Repeat Test lOa for columns 2,3, and 4. (n

=

2,3.41

FIGURE 17 -

26

General
Test
Circuit

2,3.41

TEST ELEVEN

600 II
a. With V, = 0.0 V set Sl to Terminal 1 (m
measure frequency of tone at V +.

6
7
8

=

b. Repeat Test lla for rows 2,3 and 4. (m

V+

=

c. With VI = 1.0 V set Sl to Terminal 5. (n
measure frequency of tone at V+.
d. Repeat Test for columns 2,3, and 4. (n

=

=

11 and

2,3.41.

=

11 and

2,3.41.

e. Set 51 to Terminal 4 and VI = 0.0 V. Measure row tone
amplitude at V+ (VROWI.
f. Set S1 to Terminal 8 and VI = 1.0 V. Measure column
tone amplitude at V +. (VCOll.

m corresponds to row number.

g. Using results of Tests lIe and 111, calculate:
VCOl
dBCR = 20 1091O VROW

n corresponds to column number.

2-218

MC34013A

FIGURE 18 -

TEST TWELVE

4,..------,
,..----1

FIGURE 19 -

TEST THIRTEEN

,..-----,28

r----'-i

600 II

IS

26

~OV

..r

General

Test
Circuit

General

0V

Test
Circuit

10

10 kHz Single
Pole LPF

Note: The notch filters must have 50 dB attenuation at their

Measure IS at Vl

respective center frequencies.

Calculate:
Measure V+ and V, with a true rms voltmeter. Calculate:
Vl(rms)
% DIS = - - - x 100
V+(rms)

FIGURE 20 -

=

Ro

TEST FOURTEEN

1.0 V

= 1.8 V and Vl = 2.8 V.

7[lsl -

151

2.8 V

FIGURE 21 -

1.8 V

]

TEST FIFTEEN

26

26

+
General
Test
Circuit

IS,OV

General
Test
Circuit
IMM
IMIC

12
13

+

a. Set VI = 2.0 V and measure IMIC.
b. Set V, = S.O V and measure IMM.
Calculate: RMM = 5.0 V -;- IMM

Measure VMIC

2-219

MC34013A

FIGURE 22 -

FIGURE 23 -

TEST SIXTEEN

TEST SE'JENTEEN

..-----,26

r----,

•

rl",-7_-oV5T~

General
Test

General
Test
Circuit

16

0.1 /LF -

Circuit

~+I~

t

TXAC

.L

-- --

GTX=~

vi
b. Measure ac voltage V5TA. Using VTXO from Test 17a
calculate:

d. Close 51 and set I = + 10 pA. Measure VTXO.
VTXO( -I = VTXO·

G

-~

STA - VTXO

TEST EIGHTEEN

FIGURE 25 -

26

NINETEEN
26

~.OV
General
Test
Circuit

~
.l5.0V
General
Test
Circuit

17

~

--

20

_ VRXO

19

VRXI

~

~.3V

Measure 15TA.

-...

a. 5et the generator for vi = 3.0 mV rms . Measure ac
voltage VTXO. Calculate:

b. With 51 open, measure VTXO a'nd VTXI. Calculate:
ITXI = (VTXO - VTXII .;. 200 kfl
c. Close 51 and set I = -10 pA. Measure VTXO. Calculate:
VTXO( + 1 = VR - VTXO where VR is obtained from
Test 1.

FIGURE 24 -

f = 1.0 kHz

I

vi

'----.......
a. With 51 open, measure VTXO. Using VR obtained in Test
1 Calculate: BTXO = VTXO .;. VR

~T5.0V

V

I-'-_-<~~TX~

'~t

I

a. With 51 open, measure VRXO. Using VR obtained in Test
1, calculate: BRXO = VRXO .;. VR.
b. With 51 open, measure VRXO and VRXI. Calculate:
IRXI = (VRXO - VRXII .;. 100 kfl
c. Close 51 and set I = -10 pA. Measure VRXO. Using VR
obtained in Test 1, calculate: VRXO (+ 1 = VR - VRXO.
d. Close 51 and set I = + 10 pA and measure VRXO.
VRXO( -I = VRXO·

2-220

MC34013A

FIGURE 26 -

FIGURE 27 -

TEST lWENTY

1-------. +

.I:.

I-=:......--~

General
rest

Sl

Circuit

Circuit

~S~~

~ O'l!J.F~~

V,

I
--L

1.0Vrms 1.0 kHz

a. With S2 open and Sl
A measure iRM'

position

b. Close S2 and switch Sl to position B: Measure ac
voltages v, and VRM.
Calculate:
V
RRM(ON) = -~V x 10 kl1
vi - RM

b. Set 81 to position B and close 52. Measure ae voltages vi

and VTXL. Calculate:
vi- TXL

In

-.LVi

Calculate: RRM(OFF)=OA V -;- IRM

a. Set Sl to position A with S2 open. Measure 'TXL.
Calculate: RTXL (OFF) = 0.4 V ~ 'TXL.

~V x 5.1

A l04V

VRM~

':.lf

RTXL (ON) =

Sl
18

t '~O:­

OAV

1.0Vrms 1.0 kHz

+

~.OV

OV

'TXL

General
Test

TEST lWENTY-ONE

.....------.26

r-----,26

kl1

FIGURE 28 -

APPLICATION CIRCUIT

DTMF Pad
Row-Column Switch Closure
Sl

r-R-l-----FB""128
2

4

,.

8 9
0 #

R2

LC

27

C13

~

Tip

V+~2~6~--~C~1~1~----_4~--_.----~----e_--~

3 R3
4 R4

BP 25

L-+-+-~1Cl
~+--,C2

Ring

T1

LR~2~4~~""1
V_r2~3_ _~~

C3 MC34013A VR r2:.::2'--___......:._4~-----<~--......
21
NC
C4
CAL
...---......----...:9CjCR2
RXO
10 CRl

RXI

11 AGC
NC 12 MM

C8

C7

RM
STA

13 MIC

TXO

14 TXL

TXI

17
R6

R4

~C6
RX"
Rl

C3

+

"RX used with 2-terminal mike only.

2-221
._-----------

C5

Switch S1 is controlled
by hook switch.
Illustrated in "off-hook"
condition

•

MC34013A
APPLICATIONS INFORMATION

•

Figure 28 specifies a typical application circuit for the
MC34013A. Complete listings of external components
are provided at the end of this section along with nominal component values. Component values should be
varied to optimize telephone performance parameters
for each application. The relationships between the application circuit components and certain telephone parameters are briefly described in the following:
Off-Hook DC Resistance
R12 conducts the dc line current in excess of the
speech and dialer bias current. Increasing R12 increases
the input resistance of the telephone for line currents
above 10 mAo R12 should be selected between 30 nand
120 n.
Off-Hook AC Impedance
The ac input impedance is equal to the receive amplifier load impedance (at RXO) divided by the receive
amplifier gain (voltage gain from V + to RXO). Increasing the impedance of the receiver incre8/les the impedance of the telephone. Increasing the gain ofthe receiver
amplifier decreases the impedance of the telephone.
DTMF Output Amplitude
Rll controls the amplitude of the row and column
DTMF tones. Decreasing Rll increases the level oftones
generated at V +. The ratio of the row and column tone
amplitudes is internally fixed. Rll should be greater
than 20 n to avoid excessive current in the DTMF output
amplifier.
Transmit Output Level
R4 controls the maximum signal amplitude produced
at V + by the transmit amplifier. Decreasing R4 increases the transmit output signal at V +. R4 should be

greater than 220 n to limit current in the transmit amplifier output.
Transmit Gain
The gain from the microphone to the telephone line
varies directly with R3. Increasing R3 increases the signal applied to R4 and the ac current driven through R4
to the telephone line. The closed loop-gain from the
microphone to the TXO terminal should be greater than
10 to prevent transmit amplifier oscillations.
Note: Adjustments to transmit level and gain are complicated by the addition of receiver sidetone cur·
rent to the transmit amplifier output current at
V +. Normally the sidetone current from the receiver will increase the transmit signal (if the current in the receiver is in phase with that in R4).
Thus the transmit gain and sidetone levels can·
not be adjusted independently.

Receiver Gain
Feedback resistor R9 adjusts the gain at the receiver
amplifier. Increasing R9 increases the receiver amplifier
gain.

Sidetone Level
Sidetone reduction is achieved by the cancellation of
receiver amplifier input signals from R8. R6, R7 and C6
determine the phase of the sidetone balance. The ac
voltage at the junction of R6 and R7 should be 180" out
of phase with the voltage at V +. R7 is selected such
that the signal current in R7 is slightly greater than that
in R8. This insures that the sidetone current in the receiver adds to the transmit amplifier output current.

2-222

MC34013A
EXTERNAL COMPONENTS
(Component Labels Referenced to Figure 28)

--Capacitors

Cl, C2
C3

Nominal
Value

100 pF
1.0 /IF, 3.0 V

C4,C5

O.l/lF

C6

005/lF

Description

Ceramic Resonator oscll(ator capacitors.
Transmit limiter low-pass filter capacitor controls attack and decay time of transmit peak limiter
Transmit amplifier Input capacitors prevent dc current flow Into TXL pin and attenuate low-Irequency
noise on microphone lead.
Sidetone network capacitor. provides phase-shllt In sldetone path to match that caused by telephone
line reactance

C7, C8

0.05/lF
2.2 /IF, 3.0 V

C9

Receiver amplifier Input capacitors: prevent dc current flow Into RM terminal and attenuates low frequency
nOise on the telephone line.
VR regulator capacitor. frequency compensates the VR regulator to prevent OSCillation.

CIO

001/lF

Cll

O.l/lF

DC load filter capacitor' prevents the dc load CirCUit from attenuating ac signals on V + .

C12

O.Ol/lF

Telephone line bypass capacitor: terminates telephone line for high frequency signals and prevents
OSCillation in the VR regulator.

C13

011'F

DTMF output feedback capacitor: ac couples feedback around the DTMF output amplifier which reduces
output impedance.

Resistors

Receiver amplifier output capacitor: frequency compensates the receiver amplifier to prevent OSCillation.

Nominal
Value

Description

R12

82,1.OW

DC load resistor: conducts all dc line current in excess of the current reqUired for speech or dialing
circuits; controls the off-hook dc resistance of the telephone.

R8, RIO

150 k, 56k

Receiver amplifier input resistors: couple ac input signals from the telephone line to the receiver amplifier;
signal in R8 subtracts from that in R7 to reduce sidetone in receiver.

R9

200 k

R6, R7
R4
R3

Sidetone network resistors: drive receiver amplifier input with the inverted output signal from the transmitter; phase of signal In R7 should be opposite that in R8.

270

Transmit amplifier load resistor: converts output voltage of transmit amplifier into a current that drives
the telephone line; controls the maximum transmit level.

200 k

Rl, R2

Receiver amplifier feedback resistor: controls the gain of the receiver amplifier.

1.5 k, 30 k

4.7 k, 4.7 k

Rll

36

RX

3.0 k

Transmit amplifier feedback resistor: controls the gain of the transmit amplifier.
Transmit amplifier input resistors: couple signal from microphone to transmit amplifier; control the dynamic
range of the transmit peak limiter.
DTMF calibration resistor: controls the output amplitude of the DTMF dialer.
Microphone bias resistor: sources current from VR to power a 2-terminal electret microphone; RX is not
used with 3-terminal microphones.

Semiconductors

81

MDA106A, or equivalent,
or 4-1N4005
Tl ~ 2N4126 or equivalent
Zl ~ 18 V, 1.5 W, lN5931A
XR - muRata CS8500
~

Electret Mic

2 Terminal, Primo EM-95 IUse RX)
or equivalent

3 Terminal, Primo 07A181P (Remove RX)
or equivalent

or equivalent

2-223

Receiver

Primo Model DH-34 (300 !l.) or equivalent

®

•

MC34014

MOTOROLA
Specifications and Applications
Information
TELEPHONE SPEECH NETWORK WITH DIALER
INTERFACE

TELEPHONE SPEECH NETWORK
WITH
DIALER INTERFACE
SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC34014 is a Telephone Speech Network integrated circuit
which incorporates adjustable transmit, receive, and sidetone
functions, a dc loop interface circuit, tone dialer interface, and a
regulated output voltage for a pulse/tone dialer. Also included is
an equalization circuit which compensates gains for line length
variations. The conversion from 2-to-4 wire is accomplished with
a supply voltage as low as 1.5 volts. The MC34014 is packaged in
a standard lS-pin (0.3" wide) plastic DIP, and a 20-pin surface
mount PLCC package.

,,I

• Transmit, Receive, and Sidetone Gains Set by
External Resistors

P SUFFIX

PLASTIC PACKAGE
CASE 707-02

• Loop Length Equalization for Transmit, Receive, and
Sidetone Functions
• Operates Down to 1.5 volts (V + ) in Speech Mode
• Provides Regulated Voltage for CMOS Dialer
• Speech Amplifiers Muted During Pulse and Tone Dialing

2 0 . FN SUFFIX

• DTMF Output Level Adjustable with a Single Resistor

PLASTIC PACKAGE

CASE 775-01

• Compatible with 2-Terminal Electret Microphones
• Compatible with Receiver Impedances of 150

PLCC-20

n and Higher

BLOCK DIAGRAM

Tip 0--------,

.-----1 ~~ceiver
Ring 0 - - - - - - - - '

I-t---I~

Input

From
Microphone

2·224

Input

PulsetrOile
Select

To
Dialer
Circuit

MC34014
PIN DESCRIPTION ISee Figure 1)
Pin # Pin #
PlCC DIP Name Description
2

3

4

1

2

3

MIC

TXI

TXO

Pin # Pin #

PlCC

Microphone negative supply. Bias cur~
rent from the electret microphone is
returned to V - through this pin,
through an open collector NPN transis·
tor whose base is controlled by an internal mute signaL During dialing, the
transistor is off, disabling the
microphone.

12

4

STA

5

CC

V-

11

VR

Transmit amplifier input. Input imped-

voltage as low as 1.5 V. Capacitor C8

ance is 10 kfl. Signals from the microphone are input through capacitor C5
to TXI.

stabilizes the regulator.

14

12

LC

9

7

EQ

RXI

Transmit amplifier output. The ac sig-

low pass filter between V + and LR to

nal current from this output flows
through the VR series pass transistor
via R9 to drive the line at V +. Increas-

by the dc load resistor R5. Forcing LC

prevent ae signals from being loaded
to V - will turn off the dc load current
and increase the V + voltage.

15

13

LR

dissipation from the chip. The LR pin
is biased 2.8 volts below the V + voltage (4.5 volts in the tone dialing
model.

Sidetone amplifier output. Input to this
amplifier is TXO. The signal at STA
cancels the sidetone signals in the re-

16

14

V+

Compensation Capacitor. A capacitor

18

15

VDD

voltage of 3.3 V. The nominal output
current is increased from 550 J.LA to

Equalization amplifier output. A portion of the V + signal is present on this
pin to provide negative feedback
around the transmit amplifier. The
feedback decreases with increasing
loop length, causing the ac impedance
of the circuit to increase.

2 mA when dialing. Capacitor C9 stabilizes the regulator and sustains the

VDD voltage during pulse dialing.
19

16

TI

Tone input. The DTMF signal from a
dialer circuit is input at TI through an
external resistor R7. The current at TI

is amplified to drive the line at V +. Increasing R7 will reduce the DTMF output levels. The input impedance at TI
is nominally 1.25 kfl.

Receive amplifier input. Input imped-

20

RXO Receive Amplifier output. RXO is
biased by a 2.5 rnA current source.
Feedback maintains the dc bias voltage at =0.65 V. Increasing R4 (between RXO and RX!) will increase the

17

MS

Mode select. This pin is connected

through an internal 600 kfl resistor to
the base of an NPN transistor. A Logic
"1" (>2.0 VI selects the pulse dialing
mode. A Logic "0" «0.3 VI selects the
tone dialing mode.

receive gain. C4 stabilizes the ampli-

fier. C3 couples the signals to the re-

1

ceiver. The 2.5 rnA current source is

18

MT

Mute input. MT is connected through
an internal 100 kfl resistor to the base
of a PNP transistor, with the emitter at

reduced to 0.4 mA when dialing.
9

VDD regulator. VDD is the output of a
shunt type regulator with a nominal

RXI.

11

Positive supply. V + is the positive line

voltage (from Tip & Ringl through the
polarity guard bridge. All sections of
the MC34014 are powered by V +.

and sidetone amplifier are summed at

8

DC load resistor. Resistor R5 from LR
to V - determines the dc resistance of
the telephone, and removes power

ance is >100 kfl. Signals from the line

10

DC load capacitor. An external capacitor C7 and an internal resistor form a

from CC to ground will compensate

6

Regulated voltage output. The VR voltage is regulated at 1.2 V and biases
the microphone and the speech circuits. An internal series pass PNP transistor allows for regulation with a line

the loop length equalization circuit
when additional stability is required. In
most applications, CC remains open.

8

Negative supply. The most negative inthe polarity guard diode bridge.

13

ceive amplifier. The signal level at STA
increases with loop length.
7

10

put connected to Tip and Ring through

ing R9 will decrease the signal at V +.
The output is biased at =0.65 V to allow for maximum swing of ae signals.
The closed loop gain from TXI to TXO
is internally set at 26 dB.
6

DIP Name Description

VDD. A Logic "0" «1.0 VI will mute

RMT Receiver Mute. The ac receiver current
is returned to V - through an open
collector NPN transistor and a parallel

the network for either pulse or tone di-

aling. A Logic "1" (>VDD - 0.3 VI
puts the MC34014 into the speech
mode.

10 kfl resistor. The base of the NPN is
controlled by an internal mute signal.
During dialing the transistor is off,
leaving the 10 kll resistor in series
with the receiver.

2-225

•

MC34014
FIGURE 1 -

TEST CIRCUIT
Tip

C8
2.0

R8
500

I

R9
200

n

n

~
Ring

VR

18 V

EQ

6
R6
10 k
C5
0.05

-=

V+
14

2

Rl
150 k

R5

10 k

47, V2W

TXI

13 LR
C7
0.2
LC
12

-=

~

5 CC
R2
STA 10 k

R7
22 k

4

C2
0.05

DTMF Input
RXI
7

R4
33 k

VR

0.6 V
3.75 k

1.25 k

50

-=

V+

C3

RXO

Driver

8
C4
lo.05

-=
9 RMT

VDD
Output

VDD
C9
0.1!

15

-=
Mute
PulsefTone
Select

MT

18

MS

17

NOTE: Pin numbers are for 18 pin DIP.

2-226

Receiver
(1500)

MC34014
ABSOLUTE MAXIMUM RATINGS (Voltages referred to V ,TA

=

25"CI(See Note 1.1

Parameter

V+ Voltage
VOO (externally applied, V +

Units
Vdc

-1.0, +6

Vdc

VLR

- 1.0, V + - 3.0

Vdc

MT, MS Inputs

-1.0, VOO + 1.0

Vdc

-65, + 150

°C

=

01

Value
-1.0, +18

Storage Temperature

NOTE 1: Devices should not be operated at these values. The 'Recommended Operating Conditions" provide conditions for actual devIce operation.

RECOMMENDED OPERATING CONDITIONS
Parameter

Value

Units

+ 1.5 to + 15
+3.3 to + 15

Vdc
Vdc

ITXO (Instantaneousl

o to 10

mA

Ambient Temperature

20 to +60

V + Voltage (Speech Model
(Tone Oialing Model

ELECTRICAL CHARACTERISTICS (Refer to Figure 11 (TA

25°CI

=

I

Parameter

°C

Symbol

Min

Typ

Max

2.6
3.0
7.0
4.1
4.6

3.2
3.7
8.2
4.9
5.4

3.8
4.4
9.5
5.7
6.2

4.0
5.5
6.0

6.6
8.4
8.8

8.5
12.5
14.0

-

-

Units

LINE INTERFACE

V+ Voltage
Iloop = 20 mA (Speech/Pulse Model
Iloop = 30 mA (Speech/Pulse Model
Iloop = 120 mA (Speech/Pulse Model
Iloop = 20 mA (Tone Model
11000 = 30 mA (Tone Model

V+

V + Current (Pin 12 Groundedl
V+ = 1.7 V (Speech Model
V+ = 12 V (Speech/Pulse Modesl
V + = 12 V (Tone Mode)

1+

LR Level Shift (V + - VLR)
(Speech/Pulse Mode)
(Tone Mode)

Vdc

mA

Vdc

tNLR

LC Terminal Resistance

-

2.7
4.3

RLC

36

57

94

krl

VR

1.1

-

1.2
20
25

1.3

-

-

Vdc
mV
mV

VOO

3.0

3.3

3.8

Vdc

.lVOOLD
.lVOOLN
IOOSp
IOOOL

375
16

0.25
50
550
2.0

1000
3.6

Vdc
mV
p.A
mA

-

1.5

p.A

VOLTAGE REGULATORS
VR Voltage (V+ = 1.7 V)
Load Regulation (0 mA < IR < 6.0 mAl
Line Regulation (2.0 V < V + < 6.5 V)
VOO Voltage (V + = 4.5 V)
Load Regulation (0 < 100 < 1,6 mAl
(Oialing Mode)
Line Regulation (All Modes) (4.0 V < V + < 9.0 V)
Max. Output Current (Speech Mode)
Max. Output Current (Dialing Mode)
VOO Leakage Current (V +

= 0, VOO =

3.0 V)

~VRLO
~VRLN

IOOLK

SPEECH AMPLIFIERS

Transmit Amplifier
Gain (TXI to TXO)
TXO Bias Voltage (Speech/Pulse Mode)
TXO Bias Voltage (Tone Mode Mode)
TXO High Voltage (Speech/Pulse Mode)
TXO Low Voltage (Speech/Pulse Mode)
TXI Input Resistance

ATXO
VTXOSP
VTXOOL
VTXOH
VTXOL
RTXI

Receive Amplifier
RXO Bias Voltage (All Modes)
RXO Source Current (Speech Mode)
RXO Source Current (PulselTone Mode)
RXO High Voltage (All Modes)
RXO Low Voltage (All Modes)

VRXO
IRXOSP
IRXOOL
VRXOH
VRXOL

2-227

0.45
VR-25
VR-25

-

0.45
1.5
200
VR-l00

-

20
0.52
VR-5.0
VR-5.0
125
10
0.52
2.0
400
VR-50
50

0.60

-

-

250

0.60

150

VN
XVR
mV
mV
mV
krl
xVR
mA
p.A
mV
mV

•

MC34014

ELECTRICAL CHARACTERISTICS -

(continued) ITA = 25'C)

I

Parameter

Min

Symbol

Typ

Max

Units

50

125

mV

MICROPHONE, RECEIVER CONTROLS
MIC Saturation Voltage (Speech Mode, I = 500

ItA)

•

-

VOlMIC

MIC leakage Current (Dialing Mode, Pin 1 = 3.0 V)

IMIClK

RMT Resistance (Speech Mode)
(Dialing Mode)
RMT Delay (Dialing to Speech)

RRMTSp
RRMTDl
tRMT

0

5.0

ItA

5.0

8.0
10

15
18

kG

2.0

4.0

20

ms

100

-

kG

-

Vdc

1.0

Vdc

-

{}

DIALING INTERFACE
RMT

58

MT Input High Voltage

VIHMT

VDD-0.3

MT Input low Voltage

VllMT

-

-

RMS

280

800

-

kG

MS Input High Voltage

VIHMS

2.0

-

Vdc

MS Input low Voltage

VllMS

-

0.3

Vdc

RTI

-

1.25

-

kG

ADTMF

3.2

4.8

6.2

dB

-

-15
-21
-15
-21

-

0.8

0.9

MT Input Resistance

MS Input Resistance

TI Input Resistance
DTMF Gain (See Figure 2) (V+Nin)

SIDETONE AMPLIFIER
Gain (TXO to STA)
(Speech Mode) @ VlR = 0.5 V
(Speech Mode) @ VLR = 2.5 V
(Pulse Mode) @ VlR = 0.2 V
(Pulse Mode) @ VlR = 1.0 V

ASTA

STA Bias Voltage (All Modes)

VSTA

-

0.65

dB

XVR

EQUALIZATION AMPLIFIER
Gain (V + to EO)
(Speech Mode) @ VlR = 0.5 V
(Speech Mode) @ VlR = 2.5 V
(Pulse Mode) @ VlR = 0.2 V
(Pulse Mode) @ VlR = 1.0 V

AEO

EQ Bias Voltage
(Speech Mode) @ VlR = 0.5 V
(Pulse Mode) @ VlR = 0.5 V
(Speech, Pulse) @ VlR = 2.5 V

VEO

-

-

-

-12
-2.5
-12
-2.5
0.66
1.3
3.3

NOTE: TYPical values are not tested or guaranteed.

FIGURE 2 - DTMF DRIVER TEST
22 k

V + 1--....---......---...,

F-~"""----i TI

'V 400 mV rrns
1.0 kHz

MC34014

-=-1.0 V

I

2-228

-

dB

Vdc

MC34014
SYSTEM SPECIFICATIONS (TA

~ 25°CI (See Figures 1-41

Min

Parameter

Tip-Ring Voltage (including polarity guard bridge drop of 1.4 VI
(Speech Model
Iloop ~ 5.0 mA
Iloop ~ 10 mA
Iloop ~ 20 mA
Iloop ~ 40 mA
Iloop ~ 60 mA

Typ

Max

Unit

Vdc

-

2.4
3.9
4.6
5.6
6.6

-

-

-

-

-

Transmit

Gain from Vs to V + (Figure 31 (lioop ~ 20 mAl
Gain change as Iloop is increased to 60 mA

28
-6.0

-

Distortion
Output noise

-

30
-4.5
2.0
11

31
-3.6

-

dB
dB
%

-

dBrnc

-15
-3.0
2.0

-13
-2.0

Receive

- 16
-5.0

VRXONS (f ~ 1.0 kHz, Iloop ~ 20 mAl (See Figure 41
Receive gain change as 'loop is increased to 60 mA
Distortion

-

-

Sidetone Level
VRXON + (Figure 31

dB

-

Iloop ~ 20 mA
Iloop ~ 60 mA
Sidetone Cancellation

[V~~O

(Figure 41] dB

dB
dB
%

-

[V~~O

(Figure 31] dB Iloop

DTMF Driver
V + Nin (Figure 21
AC Impedance
Speech mode (incl. C6, See Figure 41
Zac ~ (6001V + I(VS - V + I
Tone mode (including C61

~

-

-36
-21

-

20

26

-

dB

3.2

4.8

6.2

dB

-

750
300
1650

20 mA

Iloop

~

20 mA

Iloop ~ 20 mA
Iloop ~ 60 mA
20 mA < Iloop < 60 mA

n

-

-

-

NOTE TYPlcals are not tested or guaranteed

FIGURE 3 -

TRANSMIT AND SIDETONE LEVEL TEST

FIGURE 4 -

AC IMPEDANCE, RECEIVE AND SIDETONE
CANCELLATION TEST

150 k
STA
0.05

V f o-..JV',-.".-+--j\-.....- - - i

2-229

+---~RXI

V + 1-.......--..-----,
C610.02

•

MC34014
DESIGN GUIDELINES (Refer to Figure 1)

•

age versus loop current characteristics, and provides the required regulated voltages for internal
and external use.
The dialer interface provides three modes of operation: speech (non-dialing), pulse dialing, and tone
(DTMF) dialing. When switching to either dialing mode
some parameters of the various sections are changed
in order to optimize the circuit operation for that mode.
The following table summarizes those changes:

INTRODUCTION
The MC34014 is a speech network meant for connection to the Tip & Ring lines through a polarity guard
bridge. The circuit incorporates four amplifiers: transmit, receive, sidetone, and equalization. Some parameters of each amplifier are set by external components,
and in addition, the gains of the sidetone and equalization amplifiers vary with loop current.
The line interface portion determines the dc volt-

TABLE 1 - OPERATING PARAMETERS AS A FUNCTION OF OPERATING MODE
Function
LR Level Shift (V + - VLR)

Speech

Pulse

Tone

2.7V

2.7 V

.4.3V

550 f.LA

2.0 mA

2.0mA

Transmit Amplifier

Functional

Functional

Inoperative

MIC Switch (Pin 1)

On

Off

Off

VOO Source Current

Equalization Amplifier

See Transfer Curves - Figure 8

Sidetone Amplifier

See Transfer Curves - Figure 6

Receive Amplifier Output Current
RMT (Pin 9) Impedance
OTMF Amplifier
CC Voltage

2.5 mA

400 p.A

8.00

10 k!l

10 kO

Inoperative

Inoperative

Functional

VLR/3

VLR

VLR

resistance of the circuit, raising the voltage at V + .to
ensure adequate voltage at VDD for the external tone
dialer. See Figure 7 for typical voltage versus loop current characteristics.
Capacitor C7 at Pin 12 provides high frequency rolloff
(above 10Hz) so that R5 does not load down the speech
and DTMF signals.
The voltage at VR is an internally regulated 1.2 volt
supply which provides the bias currents for the microphone and the transmit amplifier output (Pin 3), as well
as internal bias for the various amplifiers. Capacitor C8
stabilizes the regulator. The use of an (internal) PNP
transistor allows VR to be regulated with a V + voltage
as low as 1.5 volts.

DC LINE INTERFACE (Figure 5)
The dc line interface circuit (Pins 10, 12-14) sets the
dc voltage characteristics with respect to the loop current. The loop current enters at Pin 14where the internal
circuitry of the MC34014 draws 5-6 mAo Pin 3 sinks
(typically) 3 mA through RS. The remainder of the loop
current is passed through Q301 and R5. The resulting
voltage across the entire circuit is therefore equal to the
voltage across R5, plus the level shift voltage from Pin
13 (LR) to Pin 14 (V +), nominally 2.7 volts in the speech
and pulse modes. In the tone mode, the level shift increases to 4.3 volts, the internal current changes slightly
(Figure 6), and the current required at Pin 3 decreases
to near zero. These changes increase the equivalent dc

FIGURE 5 - DC LINE INTERFACE

Tip 0 - - - - - - ,

Ring 0 - - - - - - - '
5-6 mA
(Internal
Circuit)
R5
47 n

10
LC

q;

400 p.A

C7
0.2 f.LF

2-230

V-

MC34014
FIGURE 6 -

INTERNAL CURRENT versus VOLTAGE

10

B.O

./'

V

~
/

6.0

V

~

Ill.

/

4.0

o/
o

B.O

TO~E M'ODE

6.0

f:Y
,/./

Vi
!::;

V

o

PULSE. SPEECH MODES

~ 4.0

!/

2.0

VDD ~ 3.0 V
Rl R7. f9 ~l OPE~- r--

/
2.0

4.0

6.0
8.0
V+ (VOLTS I

10

FIGURE 8 -

Tip

./' V

/

/1-""

'"\

SPEECH. PULSE MODES

./'
R5 I~ 47 n
R9 ~ 200n
R7 I~ O~EN

I

1

12

TRANSMIT AMPLIFIER
The transmit amplifier (from TXI to TXO) is inverting,
with a fixed internal gain of 20 VN (26 dB), and a typical
input impedance of 10 kfl (Figure 8). The input bias currents are internally supplied, allowing capacitive coupling of the microphone signals to the amplifier.
In the speech and pulse modes, the dc bias level at
TXO is typically 0.52 x VR (=0.63 V), which permits
the output to swing 0.55 volts in both positive and
negative directions without clipping. The ac voltage
signal at TXO (the amplified speech signal) is converted to an ac current by Rg. The ac current passes

t,....--V

V

VV

I

+

/
2.0

CIRCUIT VOLTAGE versus LOOP CURRENT

10

V
TONE MODE

2:

FIGURE 7 -

20

40

60
80
Iloop (mAl

100

120

through the VR series pass transistor to V +, modulating the loop current. The voltage signal at V + is out
of phase with the signal at TXI.
In the tone dialing mode, the TXO dc bias level is
clamped at approximately VR-10 mV, rendering the amplifier inoperative. This action also reduces the TXO bias
current from 3.0 rnA to less than 125 p.A.
MIC (Pin 1) is connected to an open-collector NPN
transistor, and provides the ground path for the microphone bias current. In either dialing mode, the transistor
is off, disabling the microphone.

TRANSMIT SECTION

0----,

V+

Ring 0 -_ _ _- '
VR

500

- I-- r--

R8

R9
200 n

TXO
STA

R3
R2

Note: All capacitor values in ,...F.

2-231

Cl
JO.05

To
Receive
Circuit

MC34014
SIOETONE AMPLIFIER
The sidetone amplifier provides inversion of the
TXO signal for the reduction of the sidetone signal at
the receive amplifier (Figure 8). Re"stors R2 and R3
determine the amount of sidetone cancellation. Capacitor Cl provides phase shift to "ompensate for the
phase shift created by the complex impedance of the
Tip & Ring lines.
The gain of the sidetone amplifier varies with the voltage at LR (Pin 13), in effect making it a function of the
loop current. The maximum gain is -15 dB (0.17 VN)
at low loop currents, and the minimum gain is -21 dB
(0.09 VN) at high loop current (see Figure 9 for transfer
curves). For example, using 47 !1 for R5, the gain would
begin to decrease at =30 mA. and would stop decreasing at =57 mA (speech mode). The dc bias voltage at
STA (Pin 4) changes slightly (=50 mY) with variations
in loop current. The output is inverted from TXO, which
is the input to this amplifier. Since the transmit amplifier
is inoperative in the tone dialing mode, the sidetone
amplifier is also inoperative in that mode.

•

FIGURE 9 - SIDETONE AMPLIFIER GAIN
\

-15

\
\

.......

-16

r'\

I--

'\ o-pULSE MODE

~-17

1

1\\

6 -18
o
~ -19
z
~ -20
I-

-21

I

:\

\

rg

H

-- -

!
--i
!

SPEECH MODE- ~\

J

-22
0.2

0.6

1.0

1.4
VLR IVOLTS)

loop current, the receive gain will vary by =1.5 dB. If
capacitor Cl is not used, the above equation is simplified by deleting the terms containing XC.
The output at RXO is inverted from V + in the receive
mode. In the transmit mode, the V + -to-RXO phase relationship depends on the amount of sidetone cancellation (determined by R2 and R3 and C1), and can vary
from 0' to lS0'.
In the speech mode, the output current capability (at
RXO) is typically 2.0 mAo In either dialing mode, the
current capability is reduced to 400,.,.A in order to reduce
internal current consumption. This feature is beneficial
when this device is used in conjunction with a line-powered speakerphone circuit, such as the MC3401S, where
the majority of the loop current is needed for the
speakerphone.
RMT (Pin 9) is the return path for the receiver's ac
current. This pin is internally connected to an open collector NPN transistor, paralleled by a 10 k!1 resistor. In
the speech mode, the transistor is on, providing a low
impedance from RMT to ground. In either dialing mode,
the transistor is off, muting the receive signal. This prevents loud "clicks" or loud DTMF tones from being
heard in the receiver during dialing. When switching
from either dialing mode to the speech mode (MT
switches from low to high), the RMT pin switches back
to a low impedance atter a delay of 2-20 ms. The delay
reduces clicks in the receiver associated with switching
from the dialing to speech mode.

1.8

2.2

2.B

I

RECEIVE AMPLIFIER
The gain of the receive amplifier (from V+ to RXO)
is determined according to the following equation (refer
to Figure 10):
VRXO = R4 + (XCIIR2) (AEQ) (ATXO) (ASTA)xRAxR4
V+
Rl
((XCIIR2)+R3)(RA+R6)xR2
Where RA = RSII10 k!1 (10 k!1 = Rin of Tx Amp)
AEO = Gain of Equalization Amp
ATXO = Gain of Transmit Amp (20 VN)
ASTA = Gain of sidetone Amp
Xc = Impedance of Cl at frequency of
interest
The waveform at STA (Pin 4) is in phase with that at
V + (for receive signals). hence the plus sign between
the terms. Due to the variations of AEO and ASTA with

I

EOUlLIZATlON AMPLIFIER
The equalization amplifier gain varies with loop current, and is configured in the circuit so as to cause a
variation of the network ac impedance (when looking in
from the Tip & Ring lines). The gain varies with the
voltage at LR (Pin 13), in effect making it a function of
the loop current. The maximum gain is -2.5 dB (0.75
VN) at high loop current, and the minimum gain is -12
dB (0.25 VN) and low loop current (see Figure 11 for
transfer curve). For example, using 47 n for R5, the gain
would begin to increase at =30 mA, and would stop
increasing at =57 mA (speech mode). The output signal
is in phase with the signal at V +, which is the input to
this amplifier.
The dc bias level at EO (Pin 6) varies with the voltage
at LR (Pin 13) according to the curve of Figure 12. In
most applications, this level shift is of little consequence, and may be ignored. If a particular circuit configuration should be sensitive to the shift, however,
the output signal at EO may be ac coupled to the rest
of the ci rcu it.
The equalization amplifier remains functional in all
three modes, although in the tone mode, its function
has no consequence when the circuit is configured as
shown in Figure 1.

VOO REGULATOR
The VDD regulator is a shunt type regulator which
supplies a nominal 3.3 volts for external dialers, and/or

2-232

MC34014
other circuitry. In the speech mode, the output current
capability at Pin 15 is typically 550 /LA. In either dialing
mode, the current capacity is increased to 2.0 mAo
VOO will be regulated whenever V+ is >300 mV
above the regulated value. As V + is lowered, and the
internal pass transistor becomes saturated, the circuit
steers current away from the external load through an
internal current source, in order that the VOO capacitor
(C9) does not load down speech and OTMF signals at
V +. As V + is lowered below 1 volt, Pin 15 switches
to a high impedance state to prevent discharging of
any storage capacitors, or batteries used for memory
retention.
The VOO voltage is unaffected by the choice of operating mode.

DIALER INTERFACE
The dialer interface consists of the mode control
pins, MT and MS (Pins 18 and 17), and the OTMF current amplifier.
The MT pin, when at a Logic "1" (> VOO - 0.3 V),
sets the circuit into the speech mode, independent of
the state of the MS pin. When the MT pin is at a Logic
"0" « 1.0 V), the dialing mode is determined by the MS
pin. When MS is at a Logic "1" (> 2.0 V), the circuit is
in the pulse dialing mode, and when at a Logic "0" «
0.3 V) the tone (OTMF) mode is in effect.
The input impedance of the MT pin is typically 100
kO, with the input current flowing out of the pin
(from VOO). The input impedance of the MS pin is
typically 600 kO, and the input current flows into the
pin (Figure 1).
The OTMF amplifier (Figure 13) is a current amplifier
which transmits OTMF signals to the V + pin, and consequently onto the Tip & Ring lines. Waveforms from a
OTMF dialer are input at TI (Pin 16) through a current
limiting resistor (R7)' Negative feedback around the amplifier reduces the overall gain so that return loss specifications may be met. The voltage gain is calculated
using the following equation:

V+
Vi

(1

80 RE
+ 0.795R7 + 0.4RER7)

(RE, R7 in kO)
where RE = RLI12 kO (2 kO
impedance)

=

internal dynamic

Using 22 kO for R7, and 6000 for RL, the voltage
gain is a nominal 4.3 dB. The minimum loop current
at which the circuit of Figure 1 will operate without
distortion is 12 mAo
The OTMF amplifier is functional only in the tone
dialing mode, and the waveform at V + is inverted
from that at TI. The TI pin requires a dc bias current
(into the pin) of 20-50 /LA, which may be supplied by
the Tone dialer circuit, or by using the biasing scheme
of Figure 14.

CC (PIN 5)
The CC pin (Compensation Capacitor) has two functions: 1) to provide equalization loop stability where the
normal stabilizing components are ineffective; and 2)
to allow optional control of the equalization functions.
In most applications, the capacitor at LC (Pin 12) provides the required stability, and no further compensation is required. In applications where changes are
forced at Pin 12 andlor 13 (e.g., see Figure 23), the LC
capacitor's effectiveness may be lost. The addition of a
10 /LF capacitor to Pin 5 will provide the required additional compensation.
The CC pin may be used to force the loop length compensation circuits to specific modes. Grounding CC will
set the sidetone and equalization amplifiers at the low
loop current values. Connecting CC to VR wi!, set the
amplifiers at the high loop current values.
Variations in the curves of Figures 9 and 11 may be
obtained by using external resistors from LR to CC, and
from CC to V - .

Tip 0 - - - - - ,

Ring 0 - - - - - '

2-233

•

MC34014

FIGURE 11 -

FIGURE 12 -

EQUALIZATION AMPLIFIER GAIN

-2.0
-3.0

I

-4.0

to -PULSE MODE

-5.0

•

I

4.0

V

/

I
I

~-9.0

SPEECH MODE

/

0.6

V

./

. . . .V

>---::
/
I-

SPEECH MODE

./

1.0

V

V

.1
0.2

./

--J

/

I

'"~ -10

PULSE MODE~

-

/

~-8.0

-12

/

I

@-6.0
~
+ -7.0

-11

EQ (PIN 6) DC VOLTAGE

5.0

.L'r--o

1.0

1.4

2.2

1.8

o

2.6

1.0

VLR (VOLTSI

FIGURE 13 -

2.0
3.0
VLR (VOLTSI

DTMF TONE DIALER

r-----~~~--~

----I

I

RL

I

I

I

I

L ___ ...l

Central
Office
or
PBX

VDD

15

VDD
2

3

4

5

6

7

8

9

* a

#

Vi
Tone
Dialer

+

R7
22 k

Output

~2 k
-4-

TI
16

(Equivalent Dynamic
Impedance of Internal
Circuitry)

MT

Keypad

18

1.25
V- k
10=

3.75 k
1.25 k

RL = Phone Line ac
Impedance

=

FIGURE 14 -

INPUT BIASING

VDD
75 K
DTMF
Input

50

R7

TI

>---1f---'\A'v-<~'--60
0.1

2-234

4.0

5.0

MC34014
APPLICATIONS INFORMATION
AC IMPEDANCE
the characteristic impedance of the phone line, and is
a nominal 600 n. The signal applied to the line (V,) is
therefore a portion of VS. That signal is attenuated by
the distributive impedance of the phone line, with a resulting signal V2 at the telephone. The amplitude of V2
depends on the amount of attenuation, the impedance
of the phone line at the telephone and the ac impedance
of the telephone (Zac), according to:

One of the basic problems with early telephones is
that the performance varied with different line lengths
(distance from the Central Office to the telephone). If a
particular phone were optimized for short loops and
then connected to a long loop, both the transmitted and
receive signals would be difficult to hear. On the other
hand, phones optimized for long loops would then be
annoyingly loud on short loops. The process of equalization is one whereby the performance is forced to vary
with loop length inversly to the expected variations.
Monitoring of loop length is accomplished by monitoring the loop current at the telephone. In the MC340'4,
loop length equalization is provided by varying the ac
impedance of the telephone circuit. In this manner the
MC340'4 mimics a passive network, with varistors providing the equalization.
Figure'5 depicts the situation in the receive mode.
The receive signal coming from the Central Office is Vs
and is independent of the loop length. ZR is the ac
impedance of the Central Office, nominally 900 n. ZL is

V2 =

where vi is the equivalent signal source at the receive end of the phone line, providing the signal V2
through the impedance equal to the characteristic
impedance of the line (ZU. The value of vi depends
on how much V, has been attenuated by the length
of phone line. By increasing Zac on long loops, V2 is
a greater portion of Vi, resulting in a stronger receive
signal at the telephone.

FIGURE 15 -

Figure 16 depicts the situation in the transmit mode.
In this mode, the MC340'4 is an ac current source, with
a finite output impedance, modulating the loop current.
The voltage signal V, is therefore equal to the ac signal
current acting on Zac in parallel with the characteristic
FIGURE 16 -

V;x Zac
Zac + ZL

RECEIVE MODE

impedance of the phone line (ZU. The signal is attenuated by the distributive impedance of the phone line,
and so only a portion of that signal (V2) appears at the
Central Office. By increasing Zac on long loops, V, is
increased, resulting in a higher signal level at V2.
TRANSMIT MODE

Central
Office

Telephone

i---l
I
I

I

I

900 :
I
I

I
I
,

I

I

L ____ J

2-235

MC34014

Z

_

ac -

When calculating or measuring the ac impedance, capacitor C6 (=S.O k!l at 1.0 kHz) and the dynamic impedance of the MC34014 (=10 kO) must be taken into account. If the microphone has an impedance lower than
that of a typical electret, then its dynamic impedance
must be accounted for in the above equation.

(1 + RglR6) (RS)
20 x A x (RS/R6)

where A = the gain of the equalization amplifier
(0.25 to 0.75)

FIGURE 17 - DETERMINING AC IMPEDANCE
From
Tip & Ring V-

VR
VR

EO

RS

R9

R6
10 k

1,TXO

TXI

TXO

Mike
MIC

If a variation in Zac of less than 3:1 is desired, the
circuit configuration of Figure lS may be used. The ac
impedance is the parallel combination of Rx and the

impedance presented by the remainder of the circuit.
With the values shown in Figure lS, the ac impedance
varies from 400 n to SOO n.

FIGURE 18 - REDUCED AC IMPEDANCE VARIATION
10

Rx

,-----}f--'VVIr---.V
:-:-+-< From Tip & Ring
~
____~1.~6~k~~________________~

~

VR

VR

500

R6
27 k

R9
145

0.05

n

10 k
!ITXO

TXI

TXO

__________________________

2-236

~

~

C

Mike
I

RS

EO

M

•

Since the gain of the equalization amplifier varies by
a factor of 3, the ac impedance will vary the same
amount. Using the resistor values indicated in Figure 1,
the ae impedance will vary from 2S0 n (short loop) to
S40 !l (long loop).

The ac impedance of the telephone circuit is determined by the transmit amplifier, equalization amplifier,
and external resistors R6, RS, and RS. In Figure 17, a
portion of the receive signal at V + appears at EO. That
signal is reduced at TXI by the RS-R6 divider (the electret
microphone is a high impedance). The signal at TXI is
then amplified by 20, and that signal (at TXO) is converted to an ac current by RS. The ac impedance of the
circuit is therefore V +/ITXO, and is defined by the following equation:

MC34014

where Zl is the characteristic ac impedance of the
phone line. Capacitor C6 and the =10 kO dynamic
impedance of the MC34014 must also be considered
in the above computation, since they are in parallel
with Zl.
The next step is to select the Rs/RS ratio, according
to the required Zac, using the equation on the previous
page. Then RS is selected to set the microphone sensitivity. RS is typically in the range of 0.5 k to 1.5 kO,
and is dependent on the characteristics of the microphone. R6 is then calculated from the above mentioned ratio.

HANDSET/HANDS-FREE TELEPHONE
Figure 23 indicates a circuit using the MC34014
speech network, MC3401S speakerphone circuit, and the
MC34017 tone ringer to provide a complete telephone/
speakerphone. Switch HS (containing one normally
open and one normally closed contact) is the hook
switch actuated by the handset, shown in the on-hook
position. When the handset is off-hook (HSl open, HS2
closed), power is applied to the MC34014, and consequently the handset, and the CS pin of the MC3401S is
held high so as to disable it. Upon closing the two poles
of switch SS, and placing switch HS in the on-hook position, power is then applied to both the MC34014 and
the MC3401S, and CS is held low, enabling the speakerphone function. Anytime the handset is removed from
switch HS, the circuit reverts to the handset mode. The
diode circuitry sets the MC34014 to the pulse dialing
mode to mute the handset microphone and receiver
when using the speakerphone. To compensate for the
different equalization response of the MC34014 when in

FIGURE 19 - ALTERNATE MICROPHONE BIAS

FIGURE 20 - INTERFACING A DYNAMIC MICROPHONE

TRANSMIT DESIGN PROCEDURE
Referring to Figure 17, first select RS for the desired
maximum output level at Tip & Ring, assuming a signal
level at TXO of 1.0 V p-p. The maximum signal level at
Tip & Ring will be approximately:

(VTXO) (Zl)
RS

VR

V+

1.0 k

10 k

R8

EO
10 k

16 k
MC34014

0.1

TXI
0.05
MIC

R6
20 k

Dynamic
Microphone
(150 0)

MC34014

27 k

MIC

The overall gain from the microphone to V + will vary
with loop current due to the influence of the equalization
amplifier on TXI. The signal at EO is out of phase with
that at TXI, therefore the signal at V + decreases as loop
current (and the EO signal) increases. Variations are typically 2.0 to 5.0 dB and depend largely on the impedance
characteristics of the microphone.

the pulse dialing mode (Figures Sand 11), the 47 0 resistor normally found at Pin 13 of the MC34014 is instead
divided into two resistors (33 0 and 150). This arrangement provides similar equalization response in both the
handset and in the speakerphone modes. Since the LC
capacitor (Pin 12) is ineffective in the speakerphone
mode, a capacitor is added at Pin 5 (CC) to provide compensation for the equalization loop when the speakerphone mode is in effect.

ALTERNATE MICROPHONE BIASING
In the event that the microphone cannot be properly
biased from the 1.2 volt VR supply, a higher voltage can
be obtained by biasing from the V + supply. The configuration shown in Figure lS, provides a higher voltage
to the microphone, and also filters the speech signals
at V + from reaching it, preventing an oscillatory loop
from forming. The maximum voltage limit of the
microphone must be considered when biasing this way.

SWITCHABLE TONE/PULSE TELEPHONE
Figure 21 indicates a switchable tone/pulse telephone
circuit using the MC145412 tone/pulse dialer, MC34014
speech network, and the MC34017 tone ringer. The dialer is programmable, and can store up to 10 phone
numbers. As can be seen, the interface to the MC34014
is straightforward.

If a dynamic microphone is to be used in place of an
electret unit, the circuit in Figure 20 will buffer its low
impedance from the MC34014 circuit, maintaining the
high impedance required at the junction of RS and RS'
The circuit shown provides a gain of =2.6 for the microphone signals, and can be adjusted by varying the
160 II resistor.

PULSE ONLY TELEPHONE
Figure 22 indicates a pulse only telephone circuit using the MC145409 pulse dialer, MC34014 speech network, and the MC34017 tone ringer. The dialer has last
number redial, and provides a pacifier tone to the receiver during dialing.

2-237

MC34014
FIGURE 21 -

COMPLETE TELEPHONE WITH PULSEfTONE DIALING

Tip

Ring

Pieza

~

C6 0.02

RI k
240

,
Keypad

*

I"F

VDD

2

3

R,

5

6

A2

8 9

A3

0

A4

#

(ii'[
DTMF

Me

'"~

C3

Receiver

"'"
U
::<

C2
C,

+

:r:C4
-: 0.05 "F

TSO

100 k
Tone

OSC,

Mode
OSCOVSS

FIGURE 22 -

COMPLETE TELEPHONE WITH PULSE DIALING

Top

Ring

Pieza

~

C6 0.02

RI k
240

I"F

~i4--'M-"

Keypad

,

2

4

5

7

8 9

A3

0

R4

.

VDD

(ii'[

A,

6
#

A2

C3
C2
C,

Me

'"~
'"

..

OH

::E

TSO

U

+
Receiver

:r:

-: 0.05 "F

100 k

2M
390 pF
220 k

AC,

DAS

AC2

MBA

AC3

C4

VSS

2-238

s:::

o

~
o.....
~

FIGURE 23 -

SWITCHABLE HANDSET/HANDSFREE SYSTEM

S

a:.e,

10 k

I

I\)
I

I\)
Co)

CD

Handset

r

y 9 b
rrT

Jack

~:
Phone
Une

~---i----~4~7l~+~:

=>

Pie'00=:
Diodes: 1N4148 except where noted.

II

MC34014
Recommended External Components

Piezo Sounder
Models KSN 1113-1116
Motorola, Inc.
Albuquerque, N.M.
505-822-8801

II

Microhone/Receiver
Microphone model EM-95
Receiver model DH-34
Primo Microphone, Inc.
Elk Grove Village, III.
312-595-1022

TRANSIENT PROTECTION &. RFI SUPPRESSION
Protection from voltage transients is necessary in
most telephone circuits, and may take the form of zener
diodes, RC or LC filters, transient suppressors
(MO'sorb}, or a combination of the above.
Potential radio frequency interference problems
should be addressed early in the electrical and mechanical design of the telephone. RFI may enter the cir-

2-240

Microphone Model KUC2123
Hosiden Electronics
Chicago, III.
312-956-7707

cuitry through the Tip & Ring lines, through the microphone and/or receiver leads in the handset cord, or
through any of the wiring or PC board traces. Ceramic
decoupling capacitors, ferrite beads, and other RFI
suppression techniques may be needed. Good PC board
design techniques, such as the avoidance of loops,
should be used. Long tracks on high impedance nodes
should be avoided.

®

MC34017

MOTOROLA
Advance Information . ~~~~

TELEPHONE
TONE RINGER
TELEPHONE TONE RINGER
BIPOLAR L1NEAR/l 2 L

• Complete Telephone Bell Replacement Circuit with Minimum
External Components
• On-Chip Diode Bridge and Transient Protection
• Direct Drive for Piezoelectric Transducers
• Push Pull Output Stage for Greater Output Power Capability
• Base Frequency Options -

N SUFFIX
PLASTIC PACKAGE
CASE 626-04

MC34017-1: 1.0 kHz
MC34017-2: 2.0 kHz
MC34017-3: 500 Hz

• Input Impedance Signature Meets Bell and EIA Standards
• Rejects Rotary Dial Transients

PLASTIC PACKAGE
CASE 751-01
SO-8

APPLICATION CIRCUIT

160 k
15 k

~!:!
C

~!:!

+

2.21'F
~ 3.0V

7

6

5

~~

RG

RC

RS

AC 1

ROl

R02

1

2

3

8
Ring

MC34017-X

Tip ~,
1.01'F

6.8 k

RI
4

LtjPiezo Sound

Element
MC34017-1: C = 1000 pF
MC34017-2: C = 500 pF
MC34017-3: C = 2000 pF

ThiS document contains ,nformation on a new product SpecifIcations and information herem
are subject to change Without notice

2-241

~
1

o SUFFIX

*

5.01'F

+ 25 V

8~'

MC34017-1, MC34017-2, MC34017-3
APPLICATION CIRCUIT PERFORMANCE (Refer to Circuit on First Page.)
Typical Value

Characteristic

•

Units
Hz

Output Tone Frequencies
MC34017-1
MC34017·2
MC34017·3
Warble Frequency

808/1010
1616/2020
4041505
12.5
Vp _p

Output Voltage
(VI" 60 Vrms • 20 Hz)

37

Output Duty Cycle

50

%

Ringing Start Input Voltage (20 Hz)

36

Vrms

Ringing Stop Input Voltage (20 Hz)

21

V rms

Maximum ac Input Voltage ('" 68 Hz)

150

Vrms

Impedance When Ringing
VI = 40 Vrms • 15 Hz
VI = 130 Vrms • 23 Hz

>16
12

Impedance When Not Ringing
VI = 10 V rms • 24 Hz
VI = 2.5 V rms • 24 Hz
VI = 10 V rms • 5.0 Hz
VI = 3.0 Vrms • 200-3200 Hz

28
>1.0
55
>200

kll
Mll
kll
kll

1500

V

kll

Maximum Transient Input Voltage
(T'" 2.0 ms)
Ringer Equivalence: Class A
Class 8

0.5
0.9

-

PIN DESCRIPTIONS
Description

Name
AC 1• AC 2

The input terminals to the full-wave diode bridge. The ac ringing signal from the telephone line
energizes the ringer through this bridge.

RS

The input of the threshold comparator to which diode bridge current is mirrored and sensed
through an external resistor (R3). Nominal threshold is 1.2 volts. This pin internally clamps at 1.5
volts.

RI

The positive supply terminal for the oscillator. frequency divider and output buffer circuits.

R01. R02

The tone ringer output terminals through which the sound element is driven.

RG

The negative terminal of the diode bridge and the negative supply terminal of the tone
generating circuitry.

RC

The oscillator terminal for the external resistor and capacitor which control the tone ringer
frequencies (R2. C2).

MAXIMUM RATINGS (Voltages Referenced to RG. Pin 7)
. Value

Parameter
Opereting AC Input Current (Pins 1.8)
Transient Input Current (Pins 1. 8) (T<2.0 ms)

Unit

20

mAo RMS

±300

mAo peak

Voltage Applied at RC (Pin 6)

5.0

V

Voltage Applied at RS (Pin 5)

5.0

V

Voltage Applied to Outputs (Pins 2. 3)

-2.0 to VRI

V

1.0

W

Operating Temperature Range

-20 to +60

·C

Storage Temperature Range

-65 to + 150

·C

Power Dissipation (@ 25·C)

2·242

MC34017-1, MC34017-2, MC34017-3
ELECTRICAL CHARACTERISTICS (TA = 25'C)
Test

Symbol

Min

Typ

Max

1a
1b

VStart (+)
VStart (-)

34
-34

37.5
-37.5

41
-41

Ringing Stop Voltage
(VStw = V, @ Ring Stop)
C34017-1
MC34017-2
MC34017-3

1c

VStop

Output Frequencies (V, = 50 V)
MC34017-1 High Tone
Low Tone
Warble Tone
MC34017-2 High Tone
Low Tone
Warble Tone
MC34017-3 High Tone
Low Tone
Warble Tone

1d

Characteristic

Ringing Start Voltage
(V Start = V, @. Ring Start)
V,>O
V,-----1

Jo

II:

2-243
.-

..

- -. .

~----

-----

•

MC34017-1, MC34017-2, MC34017-3
CIRCUIT DESCRIPTION

•

The MC34017 Tone Ringer derives its power supply
by rectifying the ac ringing signal. It uses this power to
activate a tone generator and drive a piezo-ceramic
transducer. The tone generation circuitry includes a relaxation oscillator and frequency dividers which produce high and low frequency tones as well as the tone
warble frequency. The relaxation oscillator frequency fo
is set by resistor R2 and capacitor C2 connected to pin
RC. The oscillator will operate with fo from 1.0 kHz to
10 kHz with the proper choice of external components
(See Figure 1).
The frequency of the tone ringer output signal at ROl
and R02 alternates between fo/4 to fo/5. The warble
rate at which the frequency changes is fo/320 for the
MC34017-1, fo/640 for the MC34017-2, and fo/160 for
the MC34017-3. With a 4.0 kHz oscillator frequency, the
MC34017-1 produces 800 Hz and 1000 Hz tones with a
12.5 Hz warble rate. The MC34017-2 generates 1600 Hz
and 2000 Hz tones with a similar 12.5 Hz warble frequency from an 8.0 kHz oscilla·tor frequency. The
MC34017-3 will produce 400 Hz and 500 Hz tones with
a 12.5 Hz warble rate from a 2.0 kHz oscillator frequency.
The tone ringer output circuit can source or sink 20 mA
with an output voltage swing of 37 volts peak-to-peak.
Volume control is readily implemented by adding a
variable resistance in series with the piezo transducer.
Input signal detection circuitry activates the tone
ringer output when the ac line voltage exceeds programmed threshold level. Resistor R3 determines the
ringing signal amplitude at which an output signal at
ROl and R02 will be generated. The ac ringing signal
is rectified by the internal diode bridge. The rectified
input signal produces a voltage across R3 which is referenced to RG. The voltage across resistor R3 is filtered
by capacitor C3 at the input to the threshold circuit.

When the voltage on capacitor C3 exceeds 1.2 volts, the
threshold comparator enables the tone ringer output.
Line transients produced by pulse dialing telephones
do not charge capacitor C3 sufficiently to activate the
tone ringer output.
Capacitors Cl and C4 and resistor Rl determine the
10 volt, 24 Hz signature test impedance. C4 also provides filtering for the output stage power supply to prevent droop in the square wave output signal. Six diodes
in series with the rectifying bridge provide the necessary non-linearity for the 2.5 volt, 24 Hz signature tests.
An internal shunt voltge regulator between the RI and
RG terminals provides dc voltage to power output stage,
oscillator, and frequency dividers. The dc voltage at RI
is limited to approximately 22 volts in regulation. To
protect the IC from telephone line transients, an SCR is
triggered when the regulator current exceeds 50 mAo
The SCR diverts current from the shunt regulator and
reduces the power dissipation within the IC.

EXTERNAL COMPONENTS

Line input resistor. Rl affects the tone
ringer input impedance. It also influences
ringing threshold voltage and limits cureent
from line transients.
(Range: 2.0 kil to 10 kill.

Cl

Line input capacitor. Cl ac couples the tone
ringer to the telephone line and controls ringer
input impedance at low frequencies.
(Range: 0.4 Io'F to 2.0 Io'FI.

R2

Oscillator resistor.

(Range: 150 kil to 300 kH).

FIGURE 1 - OSCILLATOR PERIOD (11fol versus
OSCILLATOR R2 C2 PRODUCT

800

Rl

......

C2

Oscillator capacitor.
(Range: 400 pF to 3000 pF).

R3

Input current sense resistor. R3 controls the
ringing threshold voltage. Increasing R3
decreases the ring-start voltage.
(Range: 5.0 kH to 18 kHi.

C3

Ringing threshold filter capacitor. C3 filters the
ac voltage across R3 at the input of the ringing
threshold comparator. It also provides dialer
transient rejection.
(Range: 0.5 Io'F to 5.0 Io'F).

C4

Ringer supply capacitor. C4 filters supply
voltage for the tone generating circuits.
It also provides an ac current path for the
10 V rms ringer signature impedance.
(Range: 1.0 Io'F to 10 Io'F).

./

V

-;=0

/

400
200

......

,.,

100

"."

V

"

150k", R2 '" 300k
400 pF '" C2 '" 3000 pF

200

300

400

500

R2C2(!LS1
(Mo = 1.45 R2C2 + 10 !LSI

2-244

MC34017-1, MC34017-2, MC34017-3
FIGURE 2 -

TEST ONE

r----------------------------------------,

6_8 k*
VI

Va

AC,

AC 2

Ral

RG

390 II

DUT

8

6

RC

~--~~VV~.160k*

RS

f - -....-'l.M...... 15 k'

L...-·u-....... C

Ra2

0.047 J.tF

-=

7

4

RI

5

.........U--.. 0.2J.tF
1.0 J.tF

J

MC34017·1: C = 1000 pF*
MC34017·2: C = 500 pF*
MC34017·3: C = 1000 pF*

a. Increase V, from + 33 volts while monitoring

l
INormally open)

Va. Vstartl +) equals VI when Va commences
switching.

b. Decrease VI from - 33 volts while monitoring
Va. Vstartl-) equals VI when Va commences
switching.
c. Decrease VI from + 40 volts while monitoring
Va· VS top equals VI when Va ceases
switching.
d. Set VI to +50 volts. Close Sl. Measure

0.1 J.tF
5.6 k

R

frequencies fH' fl' and fW'
200 k
16

15f-+---r-----,
14 HI--.......
IC2

13
12

11
10~--+---------,

9

IC1-MC14011B

Ql-2N3904

IC2-MC14538B
VDD =12V
*Indicates 1% tolerance

15% otherwise)

~--------~""'~O}fW

2-245

MC34017·1: R = 110 kO*
MC34017·2: R = 55 kO*
MC34017·3: R = 110 kO*

MC34017-1, MC34017-2, MC34017-3
FIGURE 3 - TEST TWO

6.8 k*

1t

AC I

+

•

~v

ROI

5.0 V

ll

RG

7

-=
~

OUT

+
S2

_3

AC r-~~~~--iI60k*
6

A02

IR02

..r ll

C

10 V
AS 5

4 Al

+

SI

.l::.
-=- VRC

J

With VRC = 4.0 volts, close SI' Switch S2 to Pin 2 and measure
current at Pin 2 (101). Repeatedly switch VRC between 4.0 volts
and 0 volts until Pin 2 current changes polarity. Measure the
opposite polarity current (102). Calculate:
IROI = 11011 + 11021
Switch S2 to Pin 3 and repeat.
Calculate:
IR02 = 11011 + 11021

MC34017-1: C = 1000 pF*
MC34017-2: C = 500 pF*
MC34017-3: C = 1000 pF*
*Indicates 1% tolerance (5% otherwise)

FIGURE 4 - TEST THREE

1 AC 1

AC2

8

AG 7

2 ROI

-=
Measure voltage at Pin 1.

OUT

3900

AC I=---....
6
--"M..-... 160 k*

C
4

-=

RI

-=

RS

5

MC34017-1: C = 1000 pF*
MC34017-2: C = 500 pF*
MC34017-3: C = 1000 pF*

*Indicates 1% tolerance (5% otherwise)

2-246

MC34017-1, MC34017-2, MC34017-3

FIGURE 5 -

V

AC 1

AC 2

RDl

RG

DUT
3
4

TEST FOUR

RC

8

=
6

•

160 k*

RD2

C

RI

RS

5

15 k*

=
a. Set II to 30 rnA. Measure voltage at Pin 1
IVott)·
b. Set II to 100 rnA. Measure voltage at Pin 1
IVon )·

MC34017-1: C = 1000 pF*
MC34017-2. C = 500 pF*
MC34017-3: C = 1000 pF*

lEach test < 30 ms)
*Indicates 1% tolerance (S% otherwise)

FIGURE 6 -

6.8 k*

+

-=-

I

50 V

AC 1

AC 2

RDl

RG

DUT
3
4

RC

TEST FIVE

8
7

r -....-"I/IfI..-.... 160 k* Measure voltage at Pin 5 IVclamp)·

RD2
RI

=

6

C
RS \-=--....
5
-"I/IfI..--' 15 k*

MC34017-1: C = 1000 pF*
MC34017-2: C = 500 pF*
MC34017-3: C = 1000 pF*

1-

*Indicates 1% tolerance (5% otherwise)

2-247

Vcl amp

MC34017-1, MC34017-2, MC34017-3
FIGURE 7 -

TEST SIX

6.8 k*
AC l

•

+

':'

ROl
20 k

RG

7

OUT

3 R02

RC 6

160 k*
C

4

RI

MC34017·1: C = 1000 pF*
MC34017·2: C = 500 pF*
MC34017·3: C = 1000 pF*
*Indicates 1% tolerance (5% otherwise)

R5

5

15 k*

~
-=l51

+
VRC

With V RC = 4.0 volts, close 51' Measure dc voltage between
Pins 2 and 3 (Vol). Repeatedly switch VRC between 4.0 volts
and 0 volts until Pins 2 and 3 change state. Measure the new
voltage between Pins 2 and 3 (Vo2).
Calculate:
Va = !Vol! + !Vo2!

2-248

®

MOTOROLA

MC34018

Specifications and Applications
Information

VOICE SWITCHED
SPEAKERPHONE CIRCUIT

VOICE SWITCHED SPEAKERPHONE CIRCUIT
SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC34018 Speakerphone integrated circuit incorporates the
necessary amplifiers, attenuators, and control functions to produce a high quality hands-free speakerphone system. Included
are a microphone amplifier, a power audio amplifier for the
speaker, transmit and receive attenuators, a monitoring system
for background sound level, and an attenuation control system
which responds to the relative transmit and receive levels as well
as the background level. Also included are all necessary regulated
voltages for both internal and external circuitry, allowing linepowered operation (no additional power supplies required). A
Chip Select pin allows the chip to be powered down when not in
use. A volume control function may be implemented with an
external potentiometer. MC34018 applications include speakerphones for household and business use, intercom systems, automotive telephones, and others.

PSUFFIX
PLASTIC PACKAGE
CASE 710·02

• All necessary level detection and attenuation controls for a
hands-free telephone in a single integrated circuit

28

• Background noise level monitoring with long time constant
• Wide operating dynamic range through signal compression
• On-chip supply and reference voltage regulation
• Typical 100 mW output power (into 25 Ohms) with peak limiting
to minimize distortion
• Chip Select pin for active/standby operation

FN SUFFIX
PLCC·28
CASE 776·01

• Linear Volume Control Function
• Standard 2a-pin plastic DIP package (0.600 inch wide) and
PLCC package

ELECTRET~r--------~OC~IAG~M _ _ _ _ _ _ ,
MIC

I

I
I

I

TRANSMIT CHANNel
MIC

AMP

I

I
I

I

I
I
I
I

I
I
I

SPEAKER

~I

~i

R:CEIVE CHANNEL
SPEAKERPHONE IC SYSTEM

L - - ~~'!..-- -

I

-=x:-- - -- -- -1- EN;;;L~

RECEIVE VOLUME CONTROL

2-249

INPUT

DC INPUT

I
\7

TELEPHONE
LINE

MC34018

PIN DESCRIPTION
PIn Name Deecrlptlon

PIn Name Description
1 RR

A resistor to ground provides a reference current
for the transmit and receive attenuators.

2 RTX

A resistor to ground determines the nominal gain
of the transmit attenuator. The transmit channel
gain is inversely proportional to the RTX
resistance.

3 TXI

Input to the transmit attenuator. Input resistance
is nominally 5.0 k ohms.

4 TXO

Output of the transmit attenuator. The TXO output signal drives the input of the transmit level
detector, as well as the external circuit which
drives the telephone line.

5 TLI

Input of the transmit level detector. An external
resistor ac coupled to the TLI pin sets the detection level. Decreasing this resistor increases the
sensitivity to transmit channel signals.

6 TLO

Output ofthe transmit level detector. The external
resistor and capacitor set the time the comparator
will hold the system in the transmit mode after
speech ceases.

7 RLI

Input of the receive level detector. An external
resistor ac coupled to the RLI pin sets the detection level. Decreasing this resistor increases the
sensitivity to receive channel signals.

B RLO

9 MCI

17 AGC A capacitor from this pin to VB stabilizes the
speaker amp gain control loop, and additionally
controls the attack and decay time of this circuit.
The gain cOntrol loop limits the speaker amp input to prevent clipping at SKO. The internal resistance at the AGC pin is nominally 110 k ohms.
18

Output of the receive level detector. The external
resistor and capacitor set the time the comparator
will hold the system in the receive mode after the
receive signal ceases.
Microphone amplifier input. Input impedance is
nominally 10k ohms and the dc bias voltage is
approximately equal to VB.

CPl

12 CP2

14 SKG

High current ground pin for the speaker amp output stage. The SKG voltage should be within 10
mV of the ground voltage at Pin 22.

15 SKO

Speaker amplifier output. The SKO pin will source
and sink up to 100 mA when ac coupled to the
speaker. The speaker amp gain is internally set
at 34 dB (50 VN).

16 V+

Input dc supply Voltage. V + can be powered from
Tip and Ring if an ac decoupling inductor is used
to prevent loading ac line signals. The required
V + voltage is 6.0 to 11 V (7.5 V nominal) at 7.0
mAo

20 VCC

A 5.4 V regulated output which powers all circuits
except the speaker amplifier output stage. VCC
can be used to power external circuitry such as
a microprocessor (3.0 mA max). A filter capacitor
is required. The MC3401B can be powered by a
separate regulated supply by connecting V + and
VCC to a voltage between 4.5 V and 6.5 V while
maintaining CS at a Logic "1".

21

An output voltage equal to approximately VCC/2
which serves as an analog ground for the speakerphone system. Up to 1.5 mA of external load
current may be sourced from VB. Output impedance is 250 ohms. A filter capacitor is required.

VB

24 VLC

A capacitor at this pin peak detects the speech
signals for comparison with the background
noise level held at CPl.
Input to the transmit detector system. The microphone amplifier output is ac coupled to the XDI
pin through an external resistor.

Input to the speaker amplifier. Input impedance
is nominally 20 k ohms.

Ground pin for the IC (except the speaker
amplifier).

23 XDC Transmit detector output. A resistor and capacitor
at this pin hold the system in the transmit mode
during pauses between words or phrases. When
the XDC pin voltage decays to ground, the attenuators switch from the transmit mode to the idle
mode. The internal resistor at XDC is nominally
2.6 k ohms (see Figure 1).

A parallel resistor and capacitor connected between this pin and VCC holds a voltage corresponding to the background noise level. The
transmit detector compares the CPl voltage with
the speech signal from CP2.

13 XDI

Digital chip select input. When at a Logic "0"
«0.7 V) the VCC reguletor is enabled. When at a
Logic "1" (>1.6 V), the chip is in the standby
mode drawing 0.5 mAo An open B pin is a Logic
"0". Input impedance is nominally 140 k ohms.
The input voltage should not exceed 11 V.

19 SKI

22 Gnd

10 MCO Microphone amplifier output. The mic amp gain
is internally set at 34 dB (50 VN).
11

B

25 ACF

Volume control input. Connecting this pin to the
slider of a variable resistor provides receive mode
volume control. The VLC pin voltage should be
less than or equal to VB.
Attenuator control filter. A capacitor connected to
this pin reduces noise transients as the attenuator

control switches levels of attenuation.
26 RXO Output of the receive attenuator. Normally this
pin is ac coupled to the input of the speaker
amplifier.
27

RXI

28 RRX

Input of the receive attenuator. Input resistance
is nominally 5.0 k ohms.
A resistorto ground determines the nominal gain
of the receive attenuator. The receive channel
gain is directly proportional to the RRX
resistance.

Note: Pin numbers are identical for the DIP and PLCC packages.

2·250

MC34018

ABSOLUTE MAXIMUM RATINGS
(Voltages referred to Pin 221 (TA = 25·CI
Value

Unlta

V+ Terminal Voltage (Pin 161

+12, -1.0

V

CS (Pin 181

+12, -1.0

V

Speaker Amp Ground (Pin 141

+3.0, -1.0

V

Parameter

VLC (Pin 241
Storage Temperature

VCC, -1.0

V

-65to +150

·C

"Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The "Electrical Characteristics" tables provide conditions for actual device operation.

RECOMMENDED OPERATING CONDITIONS
Value

Units

+6.0 to +11

V

ICC (Pin 201

o to +11
o to 3.0

mA

VLC (Pin 241

0.55VB to VB

V

o to 250
o to 5.0

mV rms

Speaker Amp Ground (Pin 141

-10to +10

mVdc

Ambient Temperature

-20 to +60

·C

Parameter

V + Terminal Voltage (Pin 161
CS (Pin 181

Receive Signal (Pin 271
Microphone Signal (Pin 91

V

mVrms

ELECTRICAL CHARACTERISTICS (Refer to Figure 11
Parameter

I Symbol

Pin

Min

Typ

Max

Unita

9.0

SUPPLY VOLTAGES
V + Supply Current
V+ = 11 V, Pin 18 = 0.7V
V+ =11V,Pin18=1.6V
VCC Voltage (V + = 7.5 VI
Line Regulation (6.5 V < V + < 11 VI
Output Resistance (ICC = 3.0 mAl
Dropout Voltage (V + = 5.0 VI
VB Voltage (V + = 7.5 VI
Output Resistance (lB = 1.7 mAl

IV+

16

-

VCC
AVCC LN
ROVCC
VCCSAT

20

VB
ROVB

21

4.9
-

2.5

-

-

800

mA
pA

5.4
65
6.0
80

5.9
150
20
300

Vdc
mV
ohms
mV

2.9
250

3.3

Vdc
ohms

10

-

ATTENUATORS
Receive Attenuator Gain (@ 1.0 kHzl
Rx Mode, Pin 24 = VB; Pin 27 = 250 mV rms
Range (Rx to Tx Modesl
Idle Mode, Pin 27 = 250 mV rms

GRX
AGRX
GRXI

RXO Voltage (Rx Model

VRXO

26,
27

2.0
40
-20

44

48

-16

-12

dB
dB
dB

1.8

2.3

3.2

Vdc

-

100

mV

6.0

AVRXO

-

RXO Sink Current (Rx Model

IRXOL

75

-

-

pA

RXO Source Current (Rx Model

IRXOH

1.0

-

3.0

mA

RXI Input Resistance

RRXI

3.5

5.0

8.0

ill

Volume Control Range (Rx Attenuator Gain, Rx Mode,
0.6 VB < Pin 24 < VBI

VCR

24.5

-

32.5

dB

Delta RXO Voltage (Switch from RX to TX Model

2-251

•

MC34018

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Symbol

Pin

Min

Typ

Max

Units

4.0
40
-16.5

6.0
44
-13

8.0
48
-8.5

dB
dB
dB

3.2

Vdc

100

mV

-

pA

ATTENUATORS

•

Transmit Attenuator Gain (75 kO. The VCC and VB regulated voltages go to 0.0
when the chip is deselected. Leaving Pin 18 open is
equivalent to a Logic "0" (chip enabled).

FIGURE 1 - TEST CIRCUIT
TRANSMIT!
OUTPUT

RECEIVE

FIGURE 2 - TRANSMIT ATTENUATOR versus RTX

-

+1 0

0
-1 0 '
-10

..........

.......

.If"'-..
dV,cf = 150 mV

= 30k
-60 r-RR
VLC = VB

+ 10 I-- r-

K

-10
-10
dB -30

:-r--....

1

/'

......

..>

- 50
-60_RR=30k
VLC = VB
-70

r--... "'-

lOOk
RTX (OHMSI

,I

/'

- 40

-70
10K

I

Max Gam
.lVacf = 150 mV

'\
........ r--.

-40 r- Max Att,';;;,,;on
-50

I

Max Gain
.lVacf = 60 mV

r--..

dB -30

FIGURE 3 - RECEIVE ATTENUATOR versus RRX

1M

lK

~
/~

Max Attenuation
dVacf = 6,0 mV

r-Usabl,
10k
RRX(OHMSI

2-256

A

R,ng;±--+4'

lOOK

MC34018

FIGURE 4 -

GAIN AND ATTENUATION
FIGURE 5 -

versus RESISTOR RATIOS

I-- GTX vs. RTXlRR

+10

-...... ........

S.O mV ....
/ K

~Vacf ~

-10

.......- K

-20

dB -30 _

-40

D<:

GRX vs. RRXIRR
~Vacf ~ 150 mV

..Y

-50

ARX vs. RRXIRR

-70

~Iacf rS(rl

0.1

0.5

I--

t---

dB -15

~

5.0

10

0.2

FIGURE 7 -

ATTENUATOR GAIN versus AVacf

.........

......V
~TX

5

t'-..

FIGURE 8 -

.s
::g
:i
:I:

/

150

r-... /

/-

'" A

Minimum

-

>--

t:>

o

60
80
100
:'Vacf IMILLIVOLTS}

'"

120

~

140

r--

' - CU~T
50 IRLI, TLI, XDII

o

FIGURE 9 -

IRLO, TLO, CP21 OUTPUT
VOLTAGE -

VB

o

lS0

LOG AMP TRANSFER CHARACTERISTICS

--

~"M~

U

~

LOG AMP TRANSFER CHARACTERISTICS

...-

/

ii: 100

.......

V
40

:>

............

/'
20

200

V

............

...... V

-30

o

f'....

./

-2 5
-35
-40

GRX

'" ./'

-10 - RR ~ 30K
RTX ~ 91K
dB -1 5 ~RRX ~ 18K
-20

I
I
I

VLCNB

250
+5

"lI

:

-35
-40

VB

GRV

Recommended
1/ II
Liel I I----'"
~1.0
I
O.S
0.8
0.4

RATIO

FIGURE 6 -

I

I

.......

-30
VLC

/

I

V

-25

ATX vs. RTXlRR
150 mV

~Vacf ~

1.0

GTX

'"

..1

ITCUlt In

Receive
Mode

I
I
I

-20

~

/

I f\

-SO

t.

-10 t---'

f"". r-..

r---..

RTX ~ 91K
I-- Rr ~ 3~K

-5

V

'\

r-R~X ~ l~K

+5

ATTENUATOR GAIN versus VLC

-20

-40
DC INPUT CURRENT I/LAI

-60

-80

SPEAKER AMP OUTPUT versus SUPPLY VOLTAGE

10

ii)

8.0

k"

~

o
:>

~ 6.0

./

~

::;;
~ 4.0

'"

V/
/,' V



2.0

4.0
INPUT VOLTAGE ImVp-p}

2-257

5.0

6.0

./

I

NoLoad 25iLoad-

'/

7.0
8.0
V+ IVOLTS}

9.0

10

11

•

MC34018

FIGURE 10 - RESPONSE AT CP2 AND CP1
600

.s: so0

.1 VCP1(Pin 111

.sw

I-~,...-

'" 0
~40

•

w
~

./

300

/

!::i

V

§;

S 20o I
"-

'-'

Il VCP2(Pin 121

I
100 IT 17
7
0r7'
50

100

150

200

250

YMCa ImV·RMSI

FIGURE 11 - TRANSMIT DETECTOR OPERATION

Inp~t ~i~lnal-1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIt----_----lmlIIIIIIIIIIIIHlIIIIIIIIIIIIIIIIIII~1

J1

I
r..,tr----------.\
dV

CP2 (Pin 12)

101lA

L_d_t
_ _=_~_~C:_(=_2_V_/_se_c_)---If.

V1 (= 200 mV)

Ir-r---------, 36 mV

Solid Line = CP1
(Pin 11)
Dotted Line =
Noninverting
Input of Transmit
Detector Compo

12.7 x Il

I

Vl

II

\

I

XDC (Pin 23)

r-----\

\

I

f\'-----------~

I

t

NOTE: Above values are typical based
on components shown in figure 1.
FIGURE 13 - SUPPLY CURRENT
FIGURE 12 - SUPPLY CURRENT versus SUPPLY VOLTAGE
versus SUPPLY VOLTAGE versus SPEAKER POWER
B. 0

6. 0

5

~

7.0

/

I

100mW

cs = 0

/ '"

BOmW

0

~ 5.0

VSKO

I
50mW

5

= OV rms

I
I

-:; 4. 0
~

0

3.0

LA

2.0
5
1.0

0

cs = 1
4.0

5.0

6.0

7.0
B.O
9.0
V+ (VOLTSI

10

0

11

2-258

20mW

10m~-

....

V

4.0

/' 1..-1
5.0

L-

6.0mf
6.0

7.0

B.O
9.0
V+ (VOLTSI

10

11

MC34018

FIGURE 15 FIGURE 14 -

SUPPLY CURRENT

versus SUPPLY VOLTAGE (SEE FIGURE 14)

ALTERNATE POWER SUPPLY CONFIGURATION

25

18

20

MC3401a

~
(Regulated
Supply)

~
«

Vs ,........__::::........_ ....

11-

Allolable
Operating Range

II
~

I

15

::3

~ 10
!£'

5.0

--

o

I
I
I

I

~

./

/

/

/

~

I
I
I
I

5.0

4.0

s.o

7.0

8.0

Vs (VOLTS I

SWITCHING TIME
The switching times of the speakerphone circuit depend not only on the various external components, but
also on the operating condition of the circuit at the time
a change is to take effect. For example, the switching
time from idle to transmit is generally quicker than the
switching time from receive to transmit (or transmit to
receive).
The components which most significantly affect the
timing between the transmit and receive modes are
those at Pins 5 (transmit turn-on), 6 (transmit turn-off),
7 (receive turn-on). and 8 (receive turn-off). These four
timing functions are not independent, but interact since
the Tx-Rx comparator operates on a RELATIVE Tx-Rx
comparison, rather than on absolute values. The components at Pins 11, 12, 13, and 23 affect the timing from
the transmit to the idle mode. Timing from the idle
mode to transmit mode is relatively quick (due to the
quick charging of the various capacitors). and is not
greatly affected by the component values. Pins 5-8 do
not affect the idle-to-transmit timing since the Tx-Rx
comparator must already be in the transmit mode for
this to occur.
The following table provides a summary of the effect
on the switching time of the various components, including the volume control:

Components
RC (a Pin 5
RC (a Pin 6

RC (jl Pin 7
RC (a Pin 8
RC (a Pin 11
C(aPin12
RC@ Pin 13
RC (a Pin 23
V (a. Pin 24
C (a Pin 25

Additionally, the following should be noted:
1) The Res at Pins 5 and 7 have a dual function in
that they affect the sensitivity of the respective log
amplifiers, or in other words, how loud the speech
must be in order to gain control of the speakerphone
circuit.
2) The RC at Pin 13 also has a dual function in that
it determines the sensitivity of the transmit detector
circuit.
3) The volume control affects the switching speed,
and the relative response to transmit signals, in the
following manner: When the circuit is in the receive
mode, reducing the volume control setting increases
the signal at TXO, and consequently the signal to the
Tli pin. Therefore a given signal at TXI will switch the
circuit into the transmit mode quicker at low volume
settings.
The photographs of Figures 16 and 17 indicate experimentally obtained switching response times for the
circuit of Figure 1. In Figure 16, the circuit is provided
a continuous receive signal of 1.1 mVp-p at RXI (trace
#3). A repetitive burst signal of 7.2 mVp-p, lasting 120

Tx to Rx

Rx to Tx

Tx to Idle

Moderate
Significant
Significant
Moderate
No effect
No effect
No effect
No effect
No effect
Moderate

Significant
Moderate
Moderate
Significant
Slight
Slight
Slight
Slight
Moderate
Moderate

No effect
No effect
No effect
No effect
Moderate
Significant
Slight
Significant
No effect
Slight

2-259

MC34018

•

is the output at TXO and is approximately 90 mVp-p at
its maximum, and Trace #4 indicates the output at RXO,
and is approximately 150 mVp-p at its maximum. In this
sequence, the circuit switches between the idle and receive modes. The time required to switch from idle to
receive is approximately 70 ms, as indicated by the first
part of Traces 2 and 4. After the receive signal is shut
off, the time to switch back to the idle mode is approximately 100 ms.
All of the above mentioned times will change significantly by varying the amplitude of the input signals, as
well as by varying the external components.

milliseconds, and repeated every 1 second, is applied
to MCI (Trace #1). Trace #2 is the output at TXO, and
is approximately 650 mVp-p at its maximum. Trace #4
is the output at RXO, and is approximately 2.2 mVp-p
at its maximum. The time to switch from the receive
mode to the transmit mode is approximately 40 ms, as
indicated by the time required for TXO to turn on, and
for RXO to turn off. After the signal at MCI is shut off,
the switching time back to the receive mode is approximately 210 ms.
In Figure 17, a continuous signal of 7.6 mVp-p is applied to MCI (Trace #1), and a repetitive burst signal of
100 mVp-p is applied to RXI (Trace #3), lasting approximately 120 ms, and repeated every 1 second. Trace #2

FIGURE 17 - IDLE-RECEIVE SWITCHING

FIGURe 16 - TRANSMIT-RECEIVE SWITCHING

Burst Input 61 MCI

2

Output (a TXO

3

Input

4

Output (a RXO

«1

RXI

Input (a MCI
Output (a TXO

3

Burst Input (iL RXI

4

Output (a RXO

Time Base = 40 ms/Div

APPLICATIONS INFORMATION
The MC34018 Speakerphone IC is designed to provide
the functions additionally required when a speakerphone is added to a standard telephone. The IC provides
the necessary relative level detection and comparison
of the speech signals provided by the talkers at the
speakerphone (near end speaker) and at the distant telephone (far end speaker).
The MC34018 is designed for use with an electret type
microphone, a 25 ohm speaker, and has an output
power capability of (typically) 100 mW. All external components surrounding this device are passive, however,
this IC does require additional circuitry to interface to
the Tip and Ring telephone lines. Two suggested circuits
are shown in this data sheet.
Figure 18 depicts a circuit using the MC34014 Speech
Network (to provide the line interface), as well as the
circuitry necessary to switch between the handset mode
and the speakerphone mode. Switch HS (containing one
normally open and one normally closed contact) is the
hook switch actuated by the handset, shown in the onhook position. When the handset is off-hook (HSl open,
HS2 closed), power is applied to the MC34014 speech
network, and consequently the handset, and the CS pin
of the MC34018 is held high so as to disable it. Upon
closing the two poles of switch SS, AND placing switch

Time Base

=

30 ms/Div

HS in the on-hook position, power is then applied to
both the MC34014 and the MC34018, and CS is held
low, enabling the speakerphone function. Anytime the
handset is removed from switch HS, the circuit reverts
to the handset mode. The diode circuitry sets the operational mode of the MC34014 so as to optimize the
speakerphone operation (see the MC34014 data sheet
for further details). The tone dialer interface is meant
for connection to a DTMF dialer with an active low
MUTE signal. The VDD supply from the MC34014 is a
nominal 3.3 volts. The MC34017 and piezo sounder provide the ringing function.
Figure 19 depicts a configuration which does not include a handset, dialer, or ringer. The only controls are
Sl (to make the connection to the line), S2 (a "privacy"
switch), and the volume control. It is meant to be used
in parallel with a normal telephone which has the dialing
and ringing functions.
Figure 20 depicts a means of providing logic level
signals that indicate which mode of operation the
MC34018 is in. Comparator A indicates whether the circuit is in the receive or transmit/idle mode, and comparator B indicates (when in the transmit/idle mode)
whether the circuit is in the transmit or idle mode. The
LM393 dual comparator was chosen because of its low
current requirement «1.0 mAl. low voltage requirement (as low as 2.0 volts), and low cost.

2-260

3:

(')

8
-\

CO

FIGURE 18 - SWITCHABLE HANDSET/HANDSFREE SYSTEM

10 k

_jHandset

3.0 k

RRX~

30k 1 RR
RTX
~
.1
3 TXI
1.0

~~

NI
N

....
0)

~

~>--

Privacy
Switch

~>.05

~

ctb
~
~

~-

Speaker

4.7

+

~

RXO 26
25
ACF
24
VLC

TXO

~~
.068 6
TLO

~4.7

~ V-

22+

RLO

iii

21

+1/

20

47

4.7 k

VB
VCC

12
CP2
13
XDI

AGC
V+

.068114 SKG
47

SKO

8~
16
~

gON .

200k

;O>~
24 k

+1/

19.05
SKI
-18
CS

CPl

lL.

.01

"

~ XDC

9 MCI
10
MCO

~

Ir::"'j
+

_,,4.7

51 k
+ 1000
10V

+

"

15

-

1

33

9

.05

200
3.3 k

1 MIC

MTJ

2 TXI

MS 17
T/ 1622 k 200 k

3 TXO
4 STA
5 CC

s:

.05

.05

4.3 k

~

RMT

VDD 15

Q v+ 14

r---2- EO ~
~
51 k
7 RXI
l
B RXO

1.0H
lN4737

1~

10

47
lN4148 =

Jack

I

'

2.2 k

RLI

7

.0688
.1

20 k

I

RXI 27. 05

TLI

4.7,k

+

1

Y 9 b

lr

1~3906

LR

10

.!.L

LC 12
VR ll
V

'~05

Mute!
VOO
To Tone

Dlaler-<>~

Tone

SS2

~::tl~;2
~/

.2
"141
2 lN4004

lN4742

Tip

"

~]

~

1111

I

25~~

240 k

1.0
"F

Ring

6.8 k

.05

PiezQ

~-8

0::~M'~"~
1'--7--4

~

Ja.

5

15 k

+ 2.2

•

Phone

Une

=>

MC34018
FIGURE 19 -

BASIC LINE POWERED SPEAKERPHONE
Sl
~Tip

Hook

I

0.01
47 k

1M

6.8 k

0.01

4.7 k
27 k

68k

220 k

Switch

+-------. Ring

0.1

10k

0.01

Speaker
(25 OHMS)

1. Diodes are lN4001 unless otherwise noted.
2. 4 Transistors are 2N3904.
3. Recommended Transformer: Microtran T2106.

FIGURE 20 -

DIGITAL TRANSMITIlDLEIRECEIVE INDICATION

MC34018

RLO
8

TLO
6

56k

56 k

>--<10--_

r

.>'7___ rTX

Tx/IDLE

~Rx

L-_....:::..j

Comparators A & B = LM393 (Dual)

2-262

:.J Idle

®

MC142100
MC145100

MOTOROLA

4 x 4 CROSSPOINT SWITCH WITH CONTROL MEMORY
The MC142100 and MC145100 consist of 16 crosspoint switches
(analog transmission gatesl organized In 4 rows and 4 columns Both
deVices have 16 latches, each of which controls the state of a particular
sWitch. Any of the 16 sWitches can be selected by applYing ItS address
to the deVice and a pulse to the strobe input. The selected crosspoint
will turn on If dUring strobe, Data In was a one and will turn off if dUring
strobe, Data In was a zero. In addition the MC145100 Will reset all nonselected sWitches In the same row as the selected sWitch Other
sWitches are unaffected In the MC145100, an Internal power-on reset
turns off all sWitches as power IS applied
•
•

Internal Latches Control State of Switches
Power-On Reset (MC145100 Onlyl

•

Low On Resistance -

•
•

Large Analog Range (VDD - VSSI
All Pins Are Diode Protected

CMOS MS.
ILOW-POWER COMPLEMENTARY MOSI

4

X 4 CROSSPOINT SWITCH
WITH CONTROL MEMORY

-

TYPically on 110 Il @ 10 Vdc

1

•

Matched SWitch Characteristics

•
•

High CMOS NOise Immunity
MC142100 Pin-for-Pln Replacement for CD22100

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 620

g

PLASTIC PACKAGE
CASE 648

ORDERING INFORMATION

Strobe

MC14XXXX

Data
In
r-----~----_e----~.---~15

L

R1

Suff,x Denotes
L

Ceramic Package

P

PlastiC Package

A

Extended Operating
Temperature Range

C

limited Operating
Temperature Range

r--r--.--+--~--~~--ro14

R2

PIN ASSIGNMENTS
r---r--'--+--~--~~--rolO
R3

r--+--...--+----..--1f-.....-+-

..:.
0

40

r--.
.....

>

<>:

20

r....

I

r.... :-...
0

-20
10

100

10 k

1k

lOOk

1M

f, Frequency (Hz)

FIGURE

2 - TYPICAL POWER BANDWIDTH

(Large Signal SWing vs. Frequency)
1

10
i
MC 14Jo3
RL=6ool1

9
Ii.

MCl43404

8

RL = 10 kII

cl.

~

1l,
6

~
:;
o

5

>

4

a

\
1\

!!!

g

\

Voltage Follower
THO<5%
VOO=+12V

~

3

1 \

'\

1
1k

10k

lOOk
f, Frequency (Hz)

2-273

1M

MC143403, MC143404

FIGURE 3 - GENERAL PURPOSE DUPLEXER 12-Wlre to 4-Wlre Converterl

10k

•

600

_

10k

Z=6000

-<

Vout ---~...

FIGURE 4 -

HIGH POWER DUPLEXER 12-Wlre to 4-Wlre Converter!

300
Vm - - - - - - - \

50k
20k
1:1
~----~~----~~~~~.
r--------~

Vout ----if--<...~C

-

10k

lOOk

300

-=

-5V

2-274

Z=6000

®

MC145402

MOTOROLA
Product Previe"W'

CMOS LSI
LOW-POWER COMPLEMENTARY MOS

SERIAL 13-BIT LINEAR CODEC

SERIAL 13-BIT LINEAR CODEC
• Provides Both 13-Bit MonotOnic AID and DI A Conversion for
Signal Processing Systems in a Single IC
• 9-Bit Linearity
• On-Chip PrecIsion Voltage Reference
• Senal Data Ports
• 2's Complement Coding
• ± 5 to 6 Volt Supply Operation
• Sample Rates from 100 Hz to 32 kHz
• Input Sample and Hold Provided On-Chip
• 5 Volt CMOS Inputs: Outputs Capable of Dnvlng Two LSTTL
Loads
L SUFFIX
CERAMIC PACKAGE
CASE 620

• Low Power Consumption: 50 mW Typical, 1 mW Power Down

BLOCK DIAGRAM

I
AO

AI

--

-

AOS/H

~~

t
AIS/H

t

~

Bandgap
Voltage Ref

•

L t-

.

DAC

Data
Selector

r----..

L

Rx
Latch

-

Op Amp

i

It

--.r-

.

SAR

MSI

t
CCI

..-

RCE

~~

.

Tx
Latch

Tx
Register

....-

TDF
TDE

~ TDC

t

t

T
Sequence
Controller

04- RDC

t

1

AlCI

~

Rx
Register

•

j
l.Jo.

•

RDD

,I
PDI

I

+ + + +

VDD

VSS

VAG

VDG

ThiS document contains InformatIOn on a product under development Motorola reserves the nght to change or discontinue thrs product without notice

2·275

TDD

•

MC145406

®

MOTOROLA

Advance Information

•

RS-232·C/V.28 Driver/Receiver
The MCl45406 is a silicon-gate CMOS IC that combines 3 drivers and 3 receivers to
fulfill the electrical specifications of EIA Standard RS-232-C and CCITT V.28. The drivers
feature true TTL input compatibility, slew-rate-limited output, 300 ohms power-off source
impedance, and output typically switching to within 25 percent of the supply rails. The
receivers can handle up to ± 25 volts while presenting 3 to 7 kilohms impedance.
Hysteresis in the receivers aids reception of noisy signals. By combining both drivers and
receivers in a single CMOS chip, the MCl45406 provides an efficient, low-power solution
for RS-232-C/V.28 applications.
Drivers
• ±5 to ± 12 V Supply Range
• 300 Ohms Power-Off Source Impedance
• Output Current Limiting
• TTL Compatible
• Slew Rate Maximum of 30 V / I'll
• Selectable Output Voltage Swing

FUNCTION DIAGRAM

,----------------,
I
I
Rx

1

CASE 6ZO
CERAMIC

1

CASE 848
PLASTIC

PIN ASSIGNMENT

Receivers
• ±25 V Input Voltage Range
• 3 to 7 Kilohms Input Impedance
• Hysteresis on Input Switchpoint

VOO

,voo

VCC

Rxl

001

Txl

011

Rx2

002

Tx2

012

Rx3

003

Tx3

013

VSS

GNO

RECEIVER

I
I

I
I
r--f-7 keyboard
inpute into pulse signals that simulate a rotary telephone dialer. All of the features
necessary for implementing a pulse dialer are provided, as well as redial. It uses an
inexpensive RC oscillator, operates directly off telephone line supply, and consumes only
microamperes of current when not outpulsing.
When off hook, the oscillator is enabled when a valid key input is detected. The
MCl46409 senses key depressions, verifies thet a single key is depressed, and stores the
key's code in on-chip memory. Up to 17 digits can be stored in the redial memory. After a
predigital peuse while memory is cleared, outpulsing begins and continues until the last
entered digit is outpulsed. If the receiver has been on-hook for the minimum time, redial
can be initiated by pressing either or #.
When on-hook the oscilletor is disabled, preventing excessive current draw. In this condition, key inpute will not be recognized.

*

•
•
•
•
•
•
•
•
•

Direct Telephone Une Operation
Silicon Gate CMOS Technology for Low-Power Operation
2.5 to 6.0 Volt Supply Range
Selectable Make-Break Ratio (60% or 66%)
Selectable Dialing Rate (10 pps or 20 pps)
Continuous Mute
Tone Signal Output
Memory Redial with or #
Inexpensive RC Oscillator
• Uses Standard 2-of-7 Matrix with Negative Common or the Inexpensive Class-A Type
Keyboard
• Pin Competible with LR-40993

PIN ASSIGNMENTS

"ii'-Ti8 ~ iiP[

YDD
TSO

2

17 ~ OH/T

COli
fli[2

4

15 PiiiiW2

16 ~ li1lWl

COL3

14

iiiiW3

YSS

13

RCI

12

RiiW4
Mii

RC2

11 MBR

RC3

10 DRS

*

BLOCK DIAGRAM
,.----MBR

RCI
RC2
RC3

DPi

OHIT
DRS

TSO

~----------------------~

MO
,-088

This document contains information on a new product. Specifications and information herein are subject to change without notice.

2-282

MC145409
ABSOLUTE MAXIMUM RATINGS

(VSS~O

Parameter

Symbol

Rating

Unit

VOO
TA

-0.3 to +6.0
-30 to +60
-56 to +150

V

DC Supply Voltage
Operating Temperature
Storage Temperature

Power Dissipation

Tstl!
Po

Voltage On Any Pin Relative to VSS

Vinl

On Any Pin Relative to VOO

Vin2

VI

500
0.3
+0.3

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to

"C
"C
mW

avoid application of any voltage higher than

maximum ratad voltages to this high impedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range VSS'" (Vin or
Voutl",VOO·
Unused inputs must always be tiad to an appropriate logic voltage level (e.g., either VSS
orVOOI.

V

ELECTRICAL CHARACTERISTICS
Characteristic

DC Supply Voltage (VSS=O VI
Operating Current (Off Hook, No Load on Outputsl
After Key Depression (During Outpulsingl
During Key Depression
Stand-by Current
(Off-Hook, Oscillator Oisabladl
Memory Retention Current (On-Hookl
Input Voltage
MBR, DRS, OHIT, and Key Inputs (2-of-7 input model
Keyboard Pull-up Resistance, COL 1-3, ROW 1-4
Keyboard Pull-down Resistance, COL 1-3, ROW 1-4
Mute Sink Current, ~
(Vout=2O% ofVOOI
Pulse Output Sink Current, OPt
(Vout=2O% ofVOOI
Tone Output Sink Current, TSO
(Vout = 20% ofVOOI
Tone Output Source Current, TSO
(Vout=2O% ofVOOI
Mute or Pulse Off Leakage Current, MBR, OPL
(Vout",VOOI
Key Contact Resistance
Keyboard Cepacitance

VOO=2.5V
VOO=6.0V
VOO=2.5V
VOO=6.0V
VOO-2.5V
VOO=6.0V

Symbol

Min

Typ

Max

VOO
100

2.5

-

6.0

-

30

ISB

-

"O"level

V,L

"1" level

V,H

VOO=2.5V
VOO=6.0V
VOO=2.5V
VOO=6.0V·
VOO-2.5V
VOO=6.0V
VOO-2.5V
VOO=6.0V
VOO=2.5V
VOO=6.0V

-

-

-

2·283

100

66

-

200
4.5
5.0

6.0
10.0

-

20% ofVOO
80% ofVOO
TBO
TBO

-

-

500

-

TBO

1.0

-

-

TBO

250

-

-

TBO

250

-

-

TBO
TBO
0.001

V
~A

150

-

200

Unit

Z10
~

-

nA
V
kO
kO
~

mA
~
~

-

-

1.0
1

-

30

~

kO
pF

MC145409
AC CHARACTERISTICS ITA = 25"C, VDD = 2.5 to 6.0 V)
Parametar
Clock Frequency
Frequency Stability
Clock Start-Up Time
Tone Frequency*

•

Percent Make-Break Ratio
Outpulsing Rat8*
P..... Oigital Pause*
Inter-Digit Time*

Symbol

Min

Typ

Max

fCl

-

4
±4

-

--

I
1

-

tCl
ORS-VSS
ORS=VOO
MBR=VOO
MBR=VSS
ORS-VSS
ORS=VOO
fOPl -10pps
fOPl =20 pps
fOPl =10pps
fOPl =20 pps

Key Input Debounce Time*
Key Down Time for Valid Entry*
Key Down Tome for Two Key Rollover*
On-Hook Time Required to Clear Memory*
Mute Valid After Last Outpulse*

%MBR
fOPl
tpop
tiD

-

2
66
60
10
20
900

460
900

460

-

-

10
40
5

-

300

-

-

5

tOB

tMO

-

Unit
kHz
%
ms·
kHz
%

-

pps

-

ms

-

m.

-

ms
ms
ms
ms
ms

-

* Directly proportional to oacillator frequency. Parameters for fCl = 4 kHz

PIN DESCRIPTIONS

OPL, OUTPULSING (PIN 18)

Positive power, relative to VSS can be supplied from
regulated line power.

The OPL output is an N-channel transistor in an open drain
configuration designed to drive a bipolar transistor. This output pulls to VSS during break and is open circuited during
make.

Vss, NEGATIVE POWER SUPPLY (PIN 6)

MO, MUTE OUTPUT (PIN 12)

VDD, POSITIVE POWER SUPPLY (PIN 1)

Negative power, relative to VDD
DRS, DIALING RATE SELECT (PIN 101
When Pin 10 is tied to VSS an output pulse rate of 10 pulseper-second is selected. Tying Pin 10 to VDD selects 20 pulseper-second.

The MO output is an N-channel transistor in an open drain
configuration designed to drive a bipolar transistor. This output pulls to VSS at the beginning of the predigital pause and
remains there until the last digit is outpulsed. When not
niuting, this output is an open circuit.
TSO, TONE SIGNAL OUTPUT (PIN 2)

MBR, MAKE-BREAK RATIO (PIN 11)

The make-break ratio input controls the duty cycle of the
digit pulse burets at the OPL output as shown.
Make-Break
Ratio (MBRI

Make

Braak

VSS (Pin 6)

40%

60%

VOO (Pin 1)

34%

66%

A tone signal is generated in response to a key depression
for user feedback. The TSO pin is a CMOS output capable of
driving an external bipolar transistor. The tone frequency is
1 kHz when a 10 pulse-per-second rate is selected and 2 kHz
when 20 pulse-per-second is selected.
OHIT, ON-HOOK/TEST IPIN 17)
Connecting the OH/T pin to VSS sets the MCI45409 in the
normal or off-hook mode. Allowing the pin to float or connecting it to VDD selects the test mode.

2-284

MC145409
KEYBOARD INPUTS (PINS 3, 4, 5, 13, 14, 16, 181
The keyboard inputs allow either a single contact (Class AI
keyboard, or a standard 2-of-7 keyboard with negative com-

mono A valid key antry occurs when either a single row is connected to a single column, or a single row and column are
simultanaously connected to VSS. Figure 1 shows typical
keyboard configurations.

CLASS A ISPSTI

STANDARD 2·0P (OPSTI

.-L0 - - ROW

vss-ct
Vss

COL - - 0

Ct-

COL
ROW

voo ~_CoL

STANOARo 2·0F·7 (oPSTI

Voo

COL

0 - - ROW

VSS

ROW

~-

'-589

Figure 1. Kayboard Configuration

OSCILLATOR (PINS 7, 8, 91
The MCl46409 contains on-chip oscillator circuitry which
will function with a minimum of external components. The

oscillator is disabled when the circuit is idle. The circuit shown
in Figure 2 will cause oscillation at 4 kHz with Rs = 2 MO,
R=220 kO, and C=390 pF.

OSCILLATOR
DISABLE

STRAY
CAPACITANCE

I
EXTERNAl COMPONENTS

NOTE:
Minimizing the stray capacitance on pin 7 will enhance oscillator
stability. The oscillator disable faature is internal to the device.
1-590

Figura 2. Oscillator Configuration

GENERAL DEVICE DESCRIPTION
When the MCl46409 is on-hook, the row and column inputs
are held high and keyboard entry is not accepted. A transition
to off-hook resets the timing and control logic and the
predigital pause counter. When in the off-hook mode, the
keyboard remains static until a keyboard entry is sensed. This
enables the oscillator. The row and column inputs are alternately scanned (by pulling high then lowl to confirm input
validity. The input is accepted only after it remains valid for
10 milliseconds of debounce tima.
Once an input is accepted, the digit is stored in memory and

outpulsing begins. The OPL output sends bursts of pulses
equivalent to the digits of a talephone number stored in
memory. This output drives an extemal bipolar transistor used
to pulse the telephone line by momentarily connecting and
disconnecting the speech network from line power.
During outpulsing, the MO output mutes the receiver,
isolating it from the outpulsing transients.
When off-hook, the MCI46409 accepts key inputs and functions in a normal fashion. After outpulsing the last digit, the
oscillator is disabled and the circuit goes to a standby mode. If
the MCl46409 is switched to on-hook while outpulsing, the remaining digits are outpulsed at 100 times their normal rate,

2·285

•

MC145409
with a make-break ratio of 50/50 to facilitate testing. This is
also an efficient means of resetting the circuit. Outpulsing in
this mode can take up to 300 milliseconds, and when complate, the circuit is deactivated, drawing only enough current
to sustain memory and the power-up-clear detect circuitry.

•

Vss

Returning to off-hook causes a positive transition on the
mute output insuring connection of the speech network to the
line. An initial kay entry of # or * causes the number sequence
stored in on-chip memory to be outpulsed. Pressing any other
valid kay clears memory, and the new number sequence will
be outpulsed.

Voo

VDD
TSO

TP

COLI

KEYBOARD {
INPUTS

Eiir2
CliI3
Vss

2M

RCI
RC2
RC3
220 k
20 PPI ()--+~

10 pps
NOTE:
This circuit demonstrates operation of the device. Outputs can be
observed at testpoints.

'·597

Figure 3. Evaluation Circuit

----.Jroh

ON.HOoK·--,L.;O:.;.;Ff.c..:.H""OO::.:K'--_ _ _ _ _ _---iIIr-_ _ _ _ _ _ _

ROW SCAN
COLUMN SCAN

~~

oFF·HOOK

I~
I

HOOK

- - - - 500 Hz- - - - - -

- - - - - .500 Hz - - - - -

JLJL..Yr--i~Jl-f --- nJ--

~rl--iU

----LItI

TSO

----.J1Ilf ~O~: ~rflJ -- -1JUl~------1uJ1J --- - 111_--=-!I - -

RC2

---uuum. - -- - - -- 4 kHz oSCILLATOR- -

KEY INPUTS

DIGIT "1"

n

- - - - - ~~
OSCILLATOR
OFF

I~ # OR * REDIAL I

DIGIT "2"

~----~~~~

I

----------.nnr-

I

~~

~--~~======~U~====~~~~~

1rI

I

1--

toB

..

lfoP--j
UfoPL

--I

I--- tlo---l

r-

tMO-j

NDRMAL olAUNG

I

I

I+-- REDIAl MooE--./

'TEST
MODE

•
H;92

Figure 4. Timing Diagram

2-286

MC145409

10 M

I.U

-

1N914
330 k

2
N

2M

9
RC 1 RC2 RC3

GRN

•

~

•

Von
68 uF

*

iiiIl:

iii

560 k

18

12

TSO I-C>---+-----j-----j>--l 2N5550

Vss
4

10
COL2

20 k

DRS

COLI

MBR

11

oH/T

TYPICAL
"500" TYI'!:
SPEECH

17

*Low leakage

NETWORK

Figure 5. Telephone Dialer Application Circuit

2·287

1-5113

®

MC145411

MOTOROLA
Advance Information

II

CMOS LSI
ILOW-POWER COMPLEMENTARY MOSI

BIT RATE GENERATOR

BIT RATE GENERATOR

The MC145411 bit rate generator is constructed with complementary
MOS enhancement mode devices. It utilizes a frequency divider network to provide a wide range of output frequencies.
A crystal controlled oscillator is the clock source for the network. A
two-bit address is provided to select one of four multiple output clock
rates.
Applications include a selectable frequency source for equipment in
the data communications market, such as teleprinters, printers, CRT
terminals, and microprocessor systems.

~

lr'f~~nllr 111111

• Single 5.0 Y (±5%1 Power Supply
• Internal Oscillator Crystal Controlled for Stability (to 4 MHz)
•
•
•
•
•
•
•
•
•

1

21 Different Bit Rates
Nine Different Bit Rate Output Pins
Programmable Time Bases for One of Four Multiple Output Rates
50% Output Duty Cycle
Buffered Outputs Compatible with Low Power TTL
Noise Immunity=45% of YDD Typical
Diode Protection on All Inputs
External Clock May be Applied to Pin 13
Internal Pullup Resistor on Reset Input

P SUFFIX
PLASTIC PACKAGE
CASE 848

PIN ASSIGNMENT

F1

rii'JTe ~ Vaa

F3

2

15 ~ RSA

Un~

F5

3

14 ~ RSB

F6

4

13 ~ Xtalin

F7

5

12 ~ Xtalout

MAXIMUM RATINGS IYoltages referenced to VSS Pin 8 I
Rating
ac Supply Voltage Range
Input Voltage, All Inputs

Symbol

Vaa

Value
5.25 to -0.5

Y,n

Vaa+0.5 to

V
V

I

VSS-0.5
10

rnA

Fa

6.

11

F9

TA
Tstg

-40 to +85
-65to +150

'c
'c

Reset

7

10

F2

VSS

8

9

F4

DC Current Drain per Pm
Operating Temperature Range

Storage Temperature Range

BLOCt< DIAGRAM
Rate SelectA ""5"-_ _ _ _ _ _ _ _ _ _ _ _ _ _--.
Rate Selects -".;.4_ _ _ _ _ _ _ _ _ _ _ _ _.".

Xl

.

Crystalin

X
Logic

Crystalout

* See Figure 2 for typical
crystal oscillator circuits

* * When

ThiS deVice contains circuitry to protect the
Inputs against damage due to high static
voltages or electnc fields; however, it IS adVised that normal precautions be taken to

~

______________________

Reset =0, outputs Fl thru F8 =0, output F9 = 1.

~11

~

Vaa=Pin 16
Vss=Pin8

ThiS document containS Information on a new product. Specifications and Information herem
are subject to change without notice.

2-288

aVOid application of any voltage higher than
maximum rated voltages to this high Impedance circuit. For proper operation It IS
recommended that Vln and Vout be constramed to the range VSSslVin or
VoutlsVaa·
Unused Inputs must always be tied to an
appropnate logiC voltage level le.g., either
VSS or Vaal.

MC145411
ELECTRICAL CHARACTERISTICS
Characteristic

Symbol

Supply Voltage
Output Voltage

"0" Level

Voo
V

Q'C
Min

+70'C

25'C
Ma.

Min

Max

Min

Ma.

4.75

5.25

V
V

VOO

-

4.75

5.25

4.75

5.0

5.25

Vout

5.0

-

0.05

-

0

0.05

-

0.05

50

499

-

499

5.0

-

499

-

"1" Level

Unit

TVD

V
V

Input Voltage
IVO=4 5 or 0.5 V)

VIL

5.0

-

1.5

-

225

1.5

-

15

IVO=0.5 or 4.5 Vdcl

VIH

5.0

3.5

-

3.5

2.75

-

3.5

-

Output Drive Current
IVOH=2.5 V) Source

IOH

50

-0.23

-

-0.20

-1.7

-0.16

IOL

5.0

0.23

-

0.20

0.78

-

-

-

-

±0.1

-

±O.OOOOl

±0.1

-

5.0

-

-

-1.5

-

-7.5

-

-

-

5.0

-

pF

0.015

25

-

-

-

15

mW

IVOL=O.4 V)

mA

Sink

Input Current
Pins 13. 14. 15
Pin 7

lin

0.16

~A

±1.0

Input Capacitance IV In = Ol

Cin

-

Quiescent Dissipation

PQ

5.0

-

2.5

Power Olsslpation··t
IOynamlc plus Quiescent)
ICL = 15 pF)

Po
5.0

-

-

Output Rise Time··
Ir = 13.0 nsl pF) CL + 25 ns

tTLH

5.0

-

-

-

70

200

-

-

ns

Output Fall Time"
If= 11.5 ns/pF) CL +47 nS

ITHL

50

-

-

-

70

200

-

-

ns

-

4.0

-

40

MHz

mW
PO=17.5 mW/MHz) f+ PQ

fCL

5.0

-

4.0

-

Clock Pulse W,dlh

IWIC)

-

200

-

200

Reset Pulse Width

tWIR)

-

500

-

500

Input Clock Frequency

ns

200

-

-

500

-

ns

tFor diSSipation at different ext~rnal capacitance (ell refer to corresponding formula'
PTICL = Po + 2.6 x 10- 31CL -15 pF) V002f
where' PT. Po In mW. CL In pF. VOO In V. and f In MHz
• -The formula given 15 for the typical characteristics only.

TABLE lA -

OUTPUT CLOCK RATES

Rate Select

Rate

B

A

0

0

0

1

X8

1

0

X16

1

1

X64

Xl

TABLE lC - 3.6864 MHz
Output Rates

TABLE lB - 1.843 MHz Crystal
Output Rates
Output
Number
Fl
F2
F3
F4
F5
F6
F7
F8
F9'

x64
614.4 k
230.4 k
153 6 k
115.2 k
768 k
36 4 k
19.2 k
9600
1843M

Output Rates I Hz)
x16
x08
153.6 k
576 k
36 4 k
28.8 k
192K
9600
4800
2400
1643 M

* F9 IS buffered oscillator output

76.8
28.8
19.2
14.4

k
k
k
k

9600
4800
2400
1200
1.643 M

Output Rates I Hz)

Output
xOl

Number

x 16

9600
3600
2400
1800
1200
600
300
150
1.843 M

Fl

3072 K

F2
F3
F4
F5
F6
F7
F8
F9'

1152k
76.8 k
576 k
384 k
192 k
9600
4800
36864 M

* F9 IS buffered oscIllator output

2-289

x08

xOl

1536 k

192 k

576 k
384 k
28.8 k
192 k
8600
4800
2400
36864 M

7200
4800
3600
2400
1200
600
300
3.6864 M

•

MC145411

FIGURE 1 - DYNAMIC SIGNAL WAVEFORMS

20 ns

•

20 ns

~
O%

Output

90%

tTLH

FIGURE 2 -

VOH
VOL

tTHL

TYPICAL CRYSTAL OSCILLATOR CIRCUIT

Rate Select

Reset

A

B

-,

..

--'- 5 pF
Rt

CJ

-..

Bit Rate

-,

Clock Outputs

....L .......

_T12pF
Xta10ut

Rt= 15 MII± 10%

Crystal Specifications
Crystal Mode
Frequency
RS

Co
Temperature Range

Test Level
Test Set

Paraliel
1.8432 MHz or 3.6864 MHz
±0.05%@13 pF
540 II max
7.0 pF max
o to 70'C
lmW
TS - 330ITSM or Equivalent

2-290

®

MC145412
MC145413
MOTOROLA

Product Preview
Pulse/Tone Repertory Dialer
The MC145412 and MC145413 are silicon gate, monolithic CMOS integrated circuits
which convert keyboard inputs into either pulse or OTMF outputs for telephone dialing.
All of the features for implementing pulse or DTMF dialing are provided. Additionally, both
parts provide last number redial and repertory memory.
Both parts work with either a 3 x 4 or 4 x 4 keyboard, and have a four second pause input. When used with a 4 x 4 keypad, the MC145413 provides a keypad selectable
pause/ switch function which couples a four second pause with a switch in dialing modes
(DTMF to pulse and vice versa). This dialing mode change is possible in all dialing sequences (normal, redial, and recall). The MC145412 requires manual switching of dialing
modes.
The repertory memory can store nine, 18 digit numbers. Manual and automatic dialing
can be cascaded in any order. During repertory memory programming, dialing outputs are
disabled.
Both parts provide a 500 hertz tone signal output in the pulse dialing mode for user
feedback. The mute output can be used to isolate the receiver from dialing outputs. The
dialer can be controlled by an MCU.
• The MC145412 is Pin Compatible with LR4803 (Except Pin 7), and the MC145413 Adds
Keypad Selectable Switching of Dialing Modes
• Single Pin Switchable Between DTMF, 10 pps and 20 pps
• Memory Storage for 9, 18 Digit Numbers, Plus Last Number Redial
• Uses Standard 2-of-7 or 2-of-8 or Form A Type Keyboards
• Uses 3.579545 MHz Colorburst Crystal
• Telephone Line Powered
• Stand Alone DTMF Dialer/Stand Alone Pulse Dialer
• Silicon Gate CMOS Technology for 2.5 - 6.0 V Low Power Operation

CASE 7111
PLASTIC

PIN ASSIGNMENT

'ii'-'"ii POTMF OUT

VOO
Cal 4

17 ~ OPl

EOrT

16~'ROW1

Cal 2

15~ROW2

Cal 3

14

ROW 3

VSS

13

iiiiW4

TSO

12

OH

OSCin

11

Mii

ose,U!

10

MS

BLOCK DIAGRAM
TSO
f---OOTMF OUT
MS

~

--+--+----,

COl4~~~~~~4-~
Call
Cal 2

COl3
ROW 1
ROW 2
ROW 3
ROW 4
OH

---+-------'
VOO-PIN 1
VSS-PIN 6

OS Cin
OSC,U! - - . . . - _ - - '

This document contains Information on a product under development. Motorola reserves the TIght to change or dIscontinue thiS product Without notIce

2·291

•

MC145412, MC145413
ABSOLUTE MAXIMUM RATINGS (VSS=O V)
Parameter

Symbol

Rating

VDD
TA
Tstg

-0.5 to +8.0

V

-30 to +60

°C

-66 to + 150

°C

I

10

mA

Vinl
vin2

-0.5
+u.5

DC Supply Voltage
Operating Temperature
Storege Temperature
DC Current Drain per Pin

•

Maximum Voltage
On any Pin Relative to VSS
On Any Pin Relative to VDD

Unit

V

ELECTRICAL CHARACTERISTICS (VDD = 2 5 V VSS = 0 V TA = 25°C unless noted)
Characteristics

Symbol

Min

VOO

2.5

100

-

Memory Retention Voltage

V,tby

Memory Retention Current

I,tby

DC Supply Voltage (VSS = 0 V)
Supply Current

Pulse Mode (MS - VOO)
OTMF Mode (MS=VSS)

Typ

Max

Unit

6.0

V

75
1.0

-

I,A
mA

2.0

-

-

1.0

-

I,A
V

V

-

0.2VOO

0.8VOO

Zin

-

100
5

-

kll

Zin

-

100
100

-

kll

-

50

Cin

-

10

-

10L

-

500
1.0
2.0

-

IOH

-

500
-

-

I,A

1.0

I,A

-

400
500

OTMF Output Tone Oistortion (VOO =3.6 V)
(RL = 600 0. 300 to 4.000 Hz)

-

OTMF Output Tone Leakage (VOO - 3.6 V)
IRL = 600 0. 300 to 4.000 Hz)

-

Input Voltage

"O"level
"1" level

VIL
VIH

Row/Column Input Impedance

toVOO
to VSS

Mode Select Input Impedance

toVOO
to VSS

OH Pull-up Resistance
Input Capacitance
Output Sink Current (Vout = 0.5 V)

TSOpin
MOpin
OPL pin

TSO Output Source Current (Vout= 1.5 V)
Output Leakage Current

MO,OPLpins

Ilkg

OTMF Output Level (VOO - 3.6 V)
(RL =600 OtoVOO)

Row Tone
Column Tone

Vout

-

kll
pF
,A
mA

-

mVRMS

5

-

%

-

-80

dBm

Unit

SWITCHING CHARACTERISTICS (TA=25°C, CL =50 pF, VDD=2.5 V unless noted. Osc. Freq. =3.579545 Hz.)
Characteristics
Row/Column Scan Frequency
Key Debounce Time

Symbol

Min

Typ

Max

f

-

250

-

Hz

tDB

-

32

-

ms

-

-

ms

100

ms

tiD

32
-

Minimum DTMF Output Duration

-

100
1.0
0.5

td

-

40
20

-

MBR

-

80

-

-

10
20

-

2

-

4

ms

32

ms

DTMF Output Ouration for Memory Dialing
Inter-Digit Pause Time

OTMF I Memory Dialing)
Pulse IAII Dialing Sequences)

10 pps
20 pps
10 pps
20 pps

Start of Outpulsing Oelay Time
Make-Break Ratio (MS = VOD or Open)
Outpulsing Rate

MS-Open
MS=VDD

fOPL

MO Overlap TIme

tMO

TSO Output Frequency

trso
trso

TSO Output Duration

2-292

-

ms

%
pps

500
20

ms
s

Hz

MC145412, MC145413
PIN DESCRIPTIONS
VDD, VSS - POWER SUPPLY (PIN 1, PIN 6)
OC power is supplied to the part on these two pins, with
VOO being the most positive. Permissible ranges are from 2.5
to 6.0 volts.

common. A valid key entry occurs when either a single row is
tied to a single column or a single row and column are
simultaneously connected to VSS. Typical keyboard configurations are shown in Figure 1. Connecting pin 2, COL 4, to
Voo sets the part for 3 x 4 keyboard interface mode.
Keyboard mode selection is performed at power-up.
CLASS A (SPSTI

MS - MODE SELECT (PIN 10)
The MS pin is a three-state input for switching between
OTMF, 10 pps, and 20 pps dialing modes. The relationship
between pin connection and operating mode is shown in
Table 1 below.

CDL----O

MS

VSS

0 - - ROW

0 - - COL

VSS

Q---RDW

STANDARD 2·DF·7 (DPST}

Table 1. Mode Select Options
VOD
Open

-e=--cn+-

STANDARD 2 Of· 7 IOPSTI

-.L

c l:

Oialing Mode
20 pps Pulse Dialing
10 pps Pulse Dialing
DTMF Tone Dialing

::

Figure 1. Keyboard Configurations
OH - ON-HOOK (PIN 12)
Connecting the OH pin to VOo, or allowing it to float sets
the device in the on-hook mode. Connecting this pin to VSS
selects the off-hook mode. When in the on-hook mode, repertory memory can be programmed without dialing output.

OSCin, OSCout (PIN 8, PIN 9)
A 3.579545 megahertz crystal is required as the frequency
reference for the on chip oscillator. Crystal biasing is accomplished by an internal resistor and capacitors.

GENERAL DEVICE DESCRIPTION

TSO - TONE SIGNAL OUTPUT (PIN 7)
In the pulse dialing mode, a 500 hertz tone signal is output
after a valid key input has been accepted to provide the user
with audio feedback for key depression. This pin also outputs
a tone when on-hook programming is taking place.
DTMF OUT PUT (PIN 18)

DUAL TONE MULTIFREQUENCY OUT-

When the MS pin is set to VSS the oTMF OUT pin outputs
tones corresponding to the row and column of the key
depressed. In the pulse dialing mode (MS = VOO or open), it is
high impedance. For repertory memory programming purposes, this pin will not output OTMF when the OH pin is held
to VOo.
OPL - OUTPULSING (PIN 17)
The OPL pin is a N-channel transistor in an open drain configuration that outputs pulses at 10 pps (MS is open) or 20 pps
(MS = VOol, with a make/break ratio of 40/60. In the oTMF
dialing mode (MS=VSSI, this output is a high impedance.
For repertory memory programming purposes, this pin will not
outpulse when the OH pin is held to Voo.
MO - MUTE OUTPUT (PIN 11)
The Mute Output is an open drain, N-channel output that
pulls to VSS when a key is input during the OTMF dialing
mode, or during outpulsing, or while oTMF is output during
auto redialing.
KEYBOARD INPUTS - (PINS 2, 3, 4, 5, 13, 14. 15, 16)
The keyboard inputs allow either a single contact (Class AI
keyboard, or a standard 2-of-8 (71 keyboard with VSS tied to

On power-up there is a 64 millisecond initialization period
during which the oscillator is enabled and the keyboard inputs
are disabled. A stop code is inserted into the first digit of all
ten RAM locations and the COL 4 input is scanned. If the COL
4' input is high (Vool the dialer is set to the 3 x 4 keypad
mode, otherwise the 4 x 4 keypad mode is selected. Changing
modes is not possible after this power-up period.
NORMAL DIALING
Responses to dialing sequences for 4 x 4 keyboards are
shown in Table 2; 3 x 4 keyboard responses are shown in
Table 3.
For normal dialing, the oscillator starts when a key is
depressed. The key input is debounced for 32 millisecond.
During this debounce period, while the RAM and dialing circuit are disabled, the mode select pin is scanned to determine
the dialing mode (either 10 pps, or 20 pps, or oTMFI. Note
that if the RAM and dialing circuit are active (i.e., during dialing or associated timing), a change at the mode select pin will
not be detected. The MC145413 provides a PAUSE/SWITCH
function, allowing dialing mode changes to be selected from
the keypad during the dialing sequence without waiting_ After
the debounce period, the input is checked for validity, then
latched into last number redial memory. As each digit is
entered, stored in the last number redial memory, and a stop
code is written in the next address. This process continues until 18 digits have been entered. If a 19th digit is entered, it will
be stored in the first address followed by a stop code in the
second address_ When dialing, the device fetches data from
memory until a stop code is encountered or 18 digits have
been dialed.

2-293

•

MC145412, MC145413

•

For a DTMF dialing sequence, the DTMF is output in 32
millisecond intervals as long as the key is depressed after the
debounce period. The DTMF OUT pin is designed to drive an
external bipolar transistor which can be used to modulate Tip
to Ring voltage at the DTMF frequencies. With the exception
of column four, multiple key inputs in anyone column or row
will result in the corresponding column or row frequency to be
output. Multiple key depressions on a diagonal will not cause
any output. When configured for the 3 x 4 keyboard, outputing the tone pairs for Nand * require two depressions of
the desired key.
When pulse dialing, each successive number is stored in last
number redial memory as it is input, then outpulsed in sequence with the appropriate timing. The OPL output can be
connected to an external bipolar transistor, which is used to
pulse the telephone line by momentarily connecting and
disconnecting the speech network from line power.
The duration of the dialing sequences can extend beyond
the time taken to push the keys for both DTMF and pulse dialing modes. Although DTMF is only output as long as the key
is depressed during manual dialing, each key depression
causes the dialing circuit to go through a 200 millisecond cycle
corresponding to the timing for DTMF auto-dialing. These
times accumulate during the dialing process. For pulse dialing,
outpulsing can extend well beyond the time it takes to enter
the digits. Changing the input at the mode select pin will not
be recognized until the accumulation of these timing sequences has elapsed.
FEATURES
For the 4 x 4 keyboard, a last number redial can be accomplished if the REDIP key (COL 4, ROW 1) is the first key
depressed after a transition from on-hook to off-hook. Otherwise, the REDIP key will cause a four second pause. If the
pulse mode is selected, redial can be accomplished if the first
key depressed on a transition to off-hook is N. For the 3 x 4

keyboard, redial occurs if the sequence, *, 0 is entered. Last
number redial memory can also be referred to as memory location O. In the pulse mode, if the first key entered after a transition to off-hook is #, a redial will be initiated.
The MCI45412/13 can be configured with an external battery to provide memory retention power and allow on-hook
programming of the repertory memory. If the part is in the onhook mode, and a key is depressed, the oscillator will start,
and the key's code will be stored in the last number redial
memory, as during off-hook operation. Dialing outputs will
not be activated while the device is in the on-hook condition.
After the number has been entered in the on-hook mode, it
can be stored in repertory memory. For the 4 x 4 keyboard,
pressing the STORE Key (* for 3 x 4 keyboard), followed by a
digit (1 through 9) will store the number in the repertory
memory location specified by the digit.
The RECALL key (COL 4, ROW 4) for the 4x4 keypad is
used to recall and dial numbers stored in the repertory
memory. The digit immediately following the RECALL key
designates the memory location of the number to be autodialed. For the 3 x 4 keyboard, recall is accomplished by
depressing the * key followed by the appropriate digit, only
when the device is in the off-hook mode.
The PAUSE key (COL 4, ROW 2) for the MCI45412 will
cause a four second pause. The PAUSE/S key (COL 4, ROW
2) is a feature offered on the MCl45413. If a pulse dialing
mode is selected (MS = VDD or OPEN), depressing this key
will cause a four second delay, and switch dialing mode to
DTMF. A subsequent PAUSE/S input will cause the dialing
mode to change back to Pulse (which ever pulse mode is
selected on MS). If MS = VSS, pressing the PAUSE/S key
will cause a four second delay but no mode change. These
functions can also be stored in memory for pauses (and mode
switching) during auto-dialing. Just as with manual dialing,
mode changes in auto dialing will only occur if MS*O (VSSI
when auto dialing is initiated.

2-294

MC145412, MC145413
Table 2. 4 x 4 Keyboerd Dialing Sequences
Kay

Dialing
Moda

REDIP

DTMF/PULSE

If first keV after transition to OFF-HOOK. redial the last number. Otherwise.
pause four seconds.

Notes

Function

PAUSE

DTMF/PULSE

Pause four seconds.

MCl45412 on IV

PAUSE/S

DTMF/PULSE

Pause four seconds then switch dialing modes.

MCl45413 onlv

STORE

DTMF/PULSE

Go to STORE mode. Upon input of memory location number. store contents of
Last Number Redial memory into location specified.

RECALL

DTMF/PULSE

Go to RECALL mode. Upon input of memory location number. recall and dial

the number in that memory location.
I

*
0-9

DTMF

Output COL 31 ROW 4 tones.

PULSE

If I is the fi",t keV input upon a transition to OFF-HOOK. Last Number Redial is
initiated; otherwise, it is ignored.

DTMF

Output COL l/ROW 4 tones.

PULSE

Pause four seconds.

DTMF/PULSE

Data input for dialing (unless preceeded bV STORE or RECALl)

See STORE and
RECALL functions

4 x 4 Key Matrix

r:l 0

[J 8

MC145413

L..:J ~ ~W~ _ PAUSEIS KEY TO

0

~ECAL~RoW 4

PAUSE & SWITCH
DIALING MODES

Table 3. 3 x 4 Keyboard Dialing Sequences
Keys

Dialing
Mode

0-9

DTMF/PULSE

Data input for dialing unless preceeded bV

*

DTMF/PULSE

Go to

*.*

Function

DTMF

Output COL l/ROW 4 tones.

PULSE

No response.

DTMF/PULSE

Pause four seconds.

*.0

DTMF/PULSE

OH = VDD or float (ON-HOOKI -

*.0-9

DTMF/PULSE

OH = VSS (OFF-HOOKI specified bV digit.

I

N. I
I. *
1.0-9

DTMF/PULSE

Notes

See

* and I.

* mode and await next input.

*. I

*.1-9

* or I.

stav in * mode.

Recall and dial number from memory location

See *. 0-9

o is last no.

redial; see

*.0

OH = VDD or float (ON-HOOKI - Store number in Last Number Redial
memory into memory location specified by digit.

DTMF

Go to # mode and await next input.

PULSE

Pause four seconds.

DTMF

Output COL 3/ROW 4 tones.

PULSE

Pause eight seconds.

I
No # mode
for PULSE

* mode.

DTMF

Go to

DTMF

Output appropriate DTMF tones.

2-295

MC145412, MC145413

HOOKSWITCH
l!o-;;;.oF;.;.F.H;;;;OO;;.;.K_ _ _ _ _ _ _ _ _ _ _-'1 ON·HOOK

I
KEY INPUTS-n DIGIT "2"

I I

•

I

DIGIT "1"

REDIAL

I

1

I

1

1~1

I

I

I
nnn nnnn

PULSETSO~.I
DTMF TSO

L.I_ _ _ _ _ _ _ _ _ _ _ __

1 1
1

I

50

I
I

+-t<

I

I 1

1

I
1

• •_ _ _ _ _ _ _ _ __

I
1

05CIL~ATION
I

rUUL\I-'UUUIi...-.----~--

I )

,(

I

I

I

I

PUL5EOUT~ I
.J..J.l 1ooms l I -l~ I I

I
I

250 Hz

>-

05CILLATlON

mr

- ---- .illL
i iuu~uj'u"""'ju ---t-.ruuu---mnruuuu------I
I

COL. SCAN-L1llUUU1J1J1JU - -

1 I

I

1

+-~I
I

ROWSCANTInnnnnnnnnnnr

PULSE MODE

1-1 ~IDB I
I -+I I--Id 1

L--LJ

MuTfffiiT I 1
DTMFMODE

II

DTMF OUT

I

I

I

I

'+--tiJ
I

1

I

DTMF

-II--IOB
MUTEOUT---'

I

I

I

~
r~
I 100 ms

'--1:""1-00-m-,":"1~

DTMF

I

I

~I--~I

I

~I-----~~

Figure 2. Timing Diagram

2-296

______~

I

~---II'----

®

MC145414

MOTOROLA

CMOS LSI

DUAL TUNABLE
LOW PASS SAMPLED DATA FILTERS

ILOW-POWER COMPLEMENTARY MOSI

The MC145414 IS sampled data, sWitched capacitor filter IC Intended
to provide band Irmltlng and signal restoration fllterrng It is capable of
operatrng from either a srngle or spirt power supply and can be
powered-down when not in use Included on the IC are two totally uncommitted op amps for use elsewhere rn the system as I to V converters, garn adjust buffers, etc

•

Two General Purpose 5th Order ElliptiC Low Pass Filters

•

Low Operating Power Consumption - 30 mW ITYPlcal!

•

Power Down Capability -

1 mW IMaxlmuml

I!,mnll If
~,'"

,r~~0n,lf II u

• ±5 to ±8 Volt Power Supply Ranges
• TTL or CMOS Compatible Inputs Using VLS Pin
•

DUAL TUNABLE
LOW PASS
SAMPLED DATA FILTERS

1

Two Operational Amplrflers Available to Reduce Component
Count

•

Useful In LPC or CVSD Speech Applications

•

Passband Edges Tunable With Clock Frequency From 1 25 kHz to
10 kHz

f

~~

1

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648

PIN ASSIGNMENT

VAG£['i'i\J"i6~VDD

BLOCK OIAGRAM

A ,n

0-----_----[-::-:--:--,.--_-----4

Aout

::~

13~ Bin

BOl5

12

- B 6

11

+B

10 elK 2

PBOUI
ClK 1

VSS ' -___9... VLS

b L Ceramic Package
P PlastiC Package

1----+--_.-0 Boul
Clock 1

VDD o--_ _ _ _-1..L...--::-....L--J---r:--'-:~_,.._oClock 2
VSS

14pA ouI

AO[4

MC14XXXX

~:~
+B~
o--------t--l

15~Aln

-A[3

ORDERING INFORMATION

AO~

Bin

+A[2

VlS

This deVice contains CircUItry to protect
the inputs against damage due to high
statIc voltages or electrtc fields; however.
it is advised that normal precautions be

taken to avoid application of any voltage
higher than maximum rated voltages to
this high Impedance circuit. For proper
operation It 15 recommended that V In and
Vout be constrained to the range

VSSS(Vin or VoutlsVDD·
Unused Inputs must always be tied to

an approprrate logic voltage level Ie g.,
either VSS or VDDI.

2-297

•

MC145414
MAXIMUM RATINGS IVoltages referenced to VSSI
Rating
DC Supply Voltage

Symbol

Value

VDD-VSS

-0.5to 18

V

Yin
I

- 0.5 to VDD + 0.5

V

10

TA
Tstg

o to 85

mA
·C

65 to 150

·C

Input Voltage, All PinS
DC Current Drain per Pin IExcludlng VDD, VSSI
Operating Temperature Range

•

Storage Temperature Range

Unit

RECOMMENDED OPERATING CONDITIONS
Parameter
DC Supply Voltage
Clock I, 2 Frequency

DIGITAL ELECTRICAL CHARACTERISTICS IVSS -- 0 VI
Symbol

Characteristic
Operating Current
Input Capacitance

VLS TTL Mode
VLS CMOS Mode
VAG Power-Down Mode
VAG Analog-Ground Mode

Input Current Clock I, 2
tlnternal Pull down Reslstorsl
Input Voltage Clock I, 2

"I" Level

Input Current Clock I, 2
tlnternal Pulldown Resistorl
Input Voltage Clock I, 2

10

40

~A

5.0

-

pF

V

12
15

11.5
14.5

11
13

-

-

12
15

4.0
5.0

-

8

-

9

VIL

12
15

-

-

0.8
0.8

VIH

12
15

11.5
14.5

10.5
13.5

-

VIL

12
15

-

-

-

-

7.0
9.0

V

12
12

-

50
-0.00001

100
-0.3

p.A

5.25
6.75
6.75
8.25

3.0
3.5

V

-

V

-

50
-0.00001

100
-0.3
VLS+0.8

VLS+2.0

-

-

VIL
VIH

TTL LOGIC LEVELS IVLS=6 V, VSS=O
"I" Level
lin
"0" Level
"0" Level
VIL
"I" Level
VIH

2·298

Max
4.0

VIH

CMOS LOGIC LEVELS IVLS=VSSI
"I" Level
lin
"0" Level
"0" Level

Unit

Typ
2.0

12

Cin
MODE CONTROL LOGIC LEVELS

VLS Power-Down Mode

25·C
Min

-

IDD
IpD

Power-Down Current IPDI-VSSI

VDD
Vdc
12
12

12
15
12
15

-

9.0
11.5

-

-

mA

V
V
V

VI
12
12
12
12

-

p.A
V

MC145414
-

ANALOG ELECTRICAL CHARACTERISTICS IVDD-12 VI

Symbol

Characteristic

Max
±1.0

±O.OOOOI

±10

2

-

Unit

lin

Am, Bm
A,n , Bin, + A, - A, + B, - B

Zin

-

VICR

2.0

-

10.0

V

liD

±10

-

nA

Input Current

Input Common Mode Voltage Range

Typ
±0.00001

Ain, Bin
VAG

Input Current

AC Input Impedance II kHzl

25'C
Min

Input Offset Current

~A

~A

Mil

+A, -A, +B,-B

liB

-

±0.1O

±1.0

nA

+Ato -A, +Bto-B

VID

-

±1O

±70

mV

1.5
3.0
2.5

-

10.5
8.3
9.0

Zo

-

50
50

-

IOH
IOL

-ZOO

-400

5

7.5
15

-

+ A to - A, + B to

Input Bias Current

Input Offset Voltage

lin

Output Voltage Range
IRL=20kll to VAG, RB= .. I
IRL = 600 Il to VAG, RB = 1.6 kll to VDDI
IRL =900 Il to VAG, RB = 1.8 kll to VDDI
Small Signal Output Impedance 11 kHzl

B

AO, BO, Aout, Bout
VOR

Aout
Bout

Output Current
IVO= 1O.5VI
IVO=I.5VI

Aout, Bout, AO, BO
Aout, Bout, AO, BO
AO, BO

Unity Gain Output NOise

V

Il

~A

mA
I'Vrms

FILTER A SPECIFICATIONS
IVDD- Vss = 12 V, Clock 1, 2= 128 kHz V,n = - 10 dBmO full scale= +3 dBmO, 7 V p-pl
25°C

Characteristic
Gain 11020 Hzl
Passband Ripple 150 Hz to 3000 Hzl
Out of Band Response
3400 Hz
4000 Hz-4600 Hz
4600 Hz-54 kHz

Min

Typ

17.4

18

Max
18.6

-

0.24

1.0

- -0.8 -1.5
-10 -15.5 -25 -33.0 -

Output NOise (A ,n = VAGI

refto9001l

Dynamic Range

76

Differential Group Delay
1150 to 2300 Hz Delay

10
B3

17

-

-

Power Supply RejectIOn Ratio IVDD= 12 V +01 VRMS @ 1 kHzl

-

36

Crosstalk lAin - VAG, B,n-O dBmO Output at Aout at 3 kHzl

-

76

1000 to 2500 Hz Delay
600 to 2700 Hz Delay

Unit
dB
dB

dB

dBrncO
dB

I's

dB
dB

FILTER B SPECIFICATIONS IVDD - VSS = 12 V Clock 1 2 = 128 kHz Vin = - 10 dBmO full scale= + 3 dBmO 7 V p-pl
25°C

Characteristic

Min

Gain (1020 Hzl

Typ

Max

-0.7 ±0.15 +0.7

-

Passband Ripple 1300 Hz to 3000 Hzl

Response
3400 Hz
4000 Hz-4600 Hz
4600 Hz-64 kHz

0.22

1.0

- -0.8 -1.7
-10 -15.5 -28 -33.0 -

Unit
d8
dB

dB

Output NOise 1300 Hz-3400 Hzl

-

8

14

dBrncO

DynamiC Range 17 V pop Maxi

79

87

-

dB

-

-

-

Differential Group Delay
1150 to 2300 Hz Delay
1000 to 2500 Hz Delay
800 to 2700 Hz Delay
Crosstalk IB In = VAG, A,n= OdBmO @ 3 kHz Output at Bout @ 3 kHzl

76

36

Power Supply Rejection RatiO

2-299

~s

dB
dB

MC145414
SWITCHING CHARACTERISTICS IVDD - VSS - 10 V TA -- 25'C)
Symbol

Characteristics

•

Input Rise Time

Clock 1,2

Input Fall Time
Pulse Width
Clock Pulse Frequency
Clock 1, 2 Duty Cycle

Clock 1, 2
Clock 1, 2

tTlH
tTHl
tWH
tCl

-

o to 70'C

Units

Min

Typ

Max

-

-

4

~s

200

-

-

ns
kHz
%

50
40

400
60

FUNCTIONAL DESCRIPTION OF PINS
for the Clock 1, 2 Inputs. If VLS IS within 0.8 V of VSS, the
thresholds will be for CMOS operating between VDD and
VSS. If VLS IS within 1.0 V of VDD, the chip will power
down. If VLS IS between VDD - 2 V and VSS + 2 V, the
thresholds for logiC Inputs at Clock 1, 2 will be between
VLS + 0.8 V and VLS + 2.0 V for TTL compatibility

Pin 1 - VAG (Analog Ground)
This Pin should be held at approximately IVDD-VEE)/2 All
analog Inputs and outputs are referenced to this Pin. If this
pin IS brought to within approximately 1.0 V of VDD, the
chip will be powered down.
Pin2-+A
Non-Inverting Input of op-amp A

Pin 10 - Clock 1
Always tie clock 1 and clock 2 together

Pin3- -A
Inverting Input of op-amp A

Pin 11 - Clock 2
Always tie clock 1 and clock 2 together

Pin4-AO
Pin 12 - Bout (Lowpass Filter B)
ThiS IS the output of 8 low pass filter

Output of uncommitted 'op-amp A.
Pin5-BO
Output of uncommitted op-amp 8.

Pin 13 - Bin (Lowpass Filter B)
ThiS IS the Input to filter B

Pin6--B
Pin 14 - Anut (Low pass Filter A)
ThiS pin IS the output to filter A

Inverting Input of op-amp 8.
Pin7-+B
Non-inverting Input of op-amp 8.

Pin 15 - Ain (Lowpass Filter A)
ThiS IS the Input to filter A

Pin 8 - VSS
This is the most negative supply Pin and digital ground for
the package.

Pin 16 - VDD
Nominally 12 volts

Pin 9 - VLS (Logic Shift Voltage)
The voltage on this Pin determines the logiC compatibility

NOTE. 80th VAG and VLS are high-Impedance Inputs

FILTER DESCRIPTION
FILTER B DESCRIPTION
Filter B In the MC145414 consists of a 5-pole elliptic
tunable lowpass filter operating at a sampled rate determined
by clock 1 and clock 2. Filter 8 IS functionally Similar to filter
A, except filter 8 has unity gain.

FILTER A DESCRIPTION
Filter A of the MC145414 IS a 5-pole elliptic tunable
lowpass filter operating at a sampling rate determined by
clock 1 and clock 2. ThiS filter provides band limiting that IS
a direct function of clock 1 and clock 2. With a 128 kHz
clock, the band limiting frequency IS 3.6 kHz. By diViding the
clock In half to 64 kHz, the band limiting frequency IS cut In
half to 1.8 kHz las Illustrated In Figure. 1). Likewise by doubling the clock, the cutoff pOint will double (as Illustrated In
Figures 3 and 4), The clock frequency can be varied from
50 kHz to 400 kHz. Filter A, unlike filter 8, has a gain of 18
db. Because the MC145414IS a SWitch capacitance filter, the
sampled output signal will have switching nOise present near
multiples of the switching frequency; a single-pole RC filter
may be reqUired to reduce thiS.
To proVide 50/60 Hz and 15 Hz reJection, a 3-pole
Chebychev highpass filter can be externally realized with the
MC145414 by uSing the uncommitted op-amps as an active
filter. This IS shown In Figure 5 and 6.

Clock 1 and 2
LogiC levels of these Signals can be either TTL or CMOS
compatible. ChOice of logiC level can be user determined by
applYing the appropriate voltage to the level shift control pin,
VLS Clock 1, 2 pins should be tied together

Power Down
The MC145414 may be powered down by bringing VAG to
Within 1.7 V of V CC or by bringing VLS to Within 1 7 V of
VDD

2-300

MC145414
FIGURE 1 -

FILTER A AND B LOWPASS CHARACTERISTICS
WITH CLOCK 1 AND 2 AT 64 kHz

FIGURE 2 -

a;

~

~

=>
o

i

B

-5
-10 t--

~
~

--

o

-20

;!!;

-25

o
;=:

-30

~

-35 t--

{

-40

~

-4 5

0.1 k

-5

a -10
i!

-15

~
o

-15

>-

~ -20

-

;!!;

I

C5 -2 5
~ -30
'"a:. _ 35

+

~ -40

1\
1k

~

2k

10 k

100 k

0.1 k

I,n. INPUT FREQUENCY IHzl

FIGURE 3 -

~

>-

a:>o=>
l'l

FILTER A AND B LOWPASS CHARACTERISTICS
WITH CLOCK 1 AND 2 AT 256 kHz

-0

5

i
c3

5

a -10

-1 0

-1 5

-20

:: -1 5

~ -20

C5 -2 5

~
o

~ -30
~

1k

fin, INPUT FREQUENCY IHzl

;!!;

;}

FILTER A AND B LOWPASS CHARACTERISTICS
WITH CLOCK 1 AND 2 AT 12B kHz

,

f\
5 k 10 k 20 k

-25

~ -3 0
c -3 5

=E

is -40

I

>

100 k

1M

1k

flO' INPUT FREQUENCY IHzl

10 k

20 k

100 k

fin, INPUT FREQUENCY 1Hz)

2-301

1M

•

MC145414
FIGURE 5 - FILTER SCHEMATIC FOR MCl46414 WITH 60 Hz REJECT FILTER
Rl

Cl

81n~

•

High lin

b

13
7 V p-p

12
Bout
C4

A Low Pass

R2

R4

VAG

LowZout

VAG

7 V p-p

b

14
Aout

15

Ain

B Low Pass
Cl, C2, C3
C4
Rl
R2
R3
R4

4700 pF

o 2 ~F
112kOY.W
620 kO Y.W
223 kO Y.W
100 kO v.W

±1%
-20% +80%
1%
1%
1%
10%

NOTE: In nOIsy enVIronment, Rl-R4 should be 10 kO or less to minimize pickup.
AD0318

FIGURE 6 - FILTER SCHEMATIC FOR MCl46414 WITH 60 Hz REJECTION AND 900 TERMINATION
Rl

Cl
l,n=9001l

Vtn Max= +3dBm

C4

Q

Bm

12

Bout

A Low Pass

Rl0

R4

VAG

VAG

lout=900 il
Vout Max= + 3 dBm

Q

R9
R7

Aout

15

Am

B Low Pass

R11

Cl, C2, C3
C4
Rl
R2
R3
R4
R5

4700 pF

o 2 ~F
236
294
223
100
200

kO
kO
kO
kO
kO

V.W
V.W
V.W
V.W
Y.W

±1%
-20% +80%
1%
1%
1%
10%
1%

NOTE In nOIsy environment, R1-R4 should be 10 kfl or less to minimiZe pickup

2-302

R6
R7
RS
R9
RlO
~11

169 kO V. W
24 kO V.W
33 kll V.W
lS.kO V.W
9000 V.W
9OO0Y.W

1%
1%
1%
10%
1%
1%
AOO319

i:

o

...&.

FIGURE 7 -

~

DELTAMOD VOICE DIGITIZER USING MC3417 AND MC145414

Con

r

Analog Input

~

...&.

~

12

1

1

16J

VOD~

VAG

~R15

2 +A

~

A

4 AO

~ BO

.
o

6 _B

N

..,.

~

-?
A,n~
Aout

"!I'~ T
12

R4J'

H/--<~ SYL

»
>R3

Co)

r>'
B

+ 12 ~
R 13>

?

Analog
OutPUt

VSS

CLKI
VLS

Encode! Decode

~

CLK 14

:;:

Bit Rate Clock
12 kHz to 32 kHz

01 13

u

......
Rl
vvv

t- ~

VTIN

FIL

r

~

9

11

11

VCC 10
2
9
DO

7 AO

1

Digital Input

OTH 12

5 REI
Clll

.!Q.,

>

R14

A

to)

R5

E,O 15

;:::

~LAAA R2

2l

RS:

R7

!1...-.-C5 T
J

CLK2

4 GC

.A

~


: Co2'!

....

__

Digital Output

~I

-=-

.AAA

R6
128 kHz

?A12
1. Ain has a ga,n of lB dB. Max V,n before clipping 'S 1 Vp-p
2 Clock must be tuff VOD to VSS SWing
3. D'gltal 110 on MC3417/18 ,s TTL compatible.

....

Cl
C2
C3
C4
C5
C6
Rl
R2
A3
R4
R5

0.1 ~F
0.01 p.F
0.1 p.F
033 p.F
0.1 p.F
10 p.F
9.6 kll
400kll
75 kll
15 kll
8.2 kll

20%
20%

A6
R7
RS
A9
Rl0

All
5%
5%
5%
5%
5%

A12
R13
R14
R15

II

47k1l
51 kll
10 kll
20011
1 kll
4.7 kll
22 M

HII
10 kll
2 kll

5%
5%
5%

®

MC145415

MOTOROLA
Advance Information

•

CMOS LSI
ILOW-POWER COMPLEMENTARY MOS)

DUAL TUNABLE LINEAR PHASE LOW-PASS
SAMPLED DATA FILTERS

The MC145415 IS sampled data, sWitched capacitor filter IC Intended
to provide band limiting and signal restoration filtering It IS capable of
operating from either a single or split power supply and can be
powered-down when not In use, Included on the IC are two uncommitted comparators for use elsewhere In the system,

DUAL TUNABLE
LINEAR PHASE LOW-PASS
SAMPLED DATA FILTERS

td
inr

•

Two Linear Phase 5th Order Low-Pass Filters
Low Operating Power Consumption - 20 mW ITYPlca11
• ± 25 to ± 8 Volt Power Supply Ra'nges
• CMOS Compatible Inputs USing VDG Pin
• Two Comparators Available to Reduce Component Count
• Useful In High Speed Data Modem Applications
• Pass-Band Edges Tunable With Clock Frequency from 1 25 kHz to
10 kHz

)f lr IIII I II

t6

•

1

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648

PIN ASSIGNMENT
VAG

~

+A

15

A ,n

-A

14

Aout

AO
BO

VOO

PBin
12 P8 0ut
13

5

- B[ 6

11

loop

+B

10

ClK

Vss

8

VOG

BLOCK DIAGRAM
ORDERING INFORMATION
MC14XXXX
Am

loop
8m
+8
-8
80

1~\J
P
11

T

I

I

FliterA

~~ 1

I

13

Filter 8

14

I

I

10

1

1

I

12

I

~~
6

8

Aout
ClK

b l CeramiC Package
P PlastiC Package

VAG
8 0ut
ThiS deVice contains circuitry to protect

+A
-A
AO

VOG= Pm 9
VOO= Pin 16

ThiS document contains Information on a new product Specifications and Information herein
are subject to change Without notice

2-304

the Inputs against damage due to high
static voltages or electriC fields, however,
It IS adVised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages 10
thiS high Impedance CirCUit For proper
operation It IS recommended that V 1n and
Vout be constrained to the range
V55" IV," or Vout'" VOO
Unused Inputs must always be tied to
an appropriate logiC voltage level (e 9 ,
either V 55 or VOO)

MC145415
ANALOG ELECTRICAL CHARACTERISTICS IVOO= 12 V. VSS=O. VAG= VOO/2. TA= -40 t085'CI

Characteristic

Symbol

Min

Typ

Max

Input Current

Arn. Bin

lin

± 0 CXXI01

±1O

~A

Input Current

VAG
A ln , Bin
A,n , Bin, + A. - A. + B. - B

lin
Zin

-

± 0 CXXI01

±50

~A

2

-

VICR

20

-

100

Mil
V

-

±O 10

±10

nA

±10

± 70

mV

15

-

25

-

AC Input Impedance 11 kHzl
Input Common Mode Voltage Range
Input Offset Current

+Ato

B

110

Input Bias Current

+A. A. + B. B
+ A to - A. + B to - B

liB
VIO

Aout· Bout

VOR

Input Offset Voltage
Output Voltage Range
IRL =20 kll to VAG. RB= 001
IRL =900 II to VAG. RB= 18 kU to VOOI
IRL =600 kG to VAG. R8= 1.6 kG to VOOI

A. + B to

Aout

Zo

Bout

nA

±10

V

30

Small Signal Output Impedance 11 kHzl

Unit

-

-

-

105
90
83

50
50

-

II

Output Current

IVO= 10 5VI
IVO=15VI
Comparator Output Current
IVO=95 VI
IVO=O 5 VI

Aout. Bout
Aout, Bout

IOH
IOL

-200

-400
75

-

~A

5

-

mA

IOH
IOL

- 11
-30

- 2 25
-88

-

mA

AO, BO

FILTER A SPECIFICATIONS IVOO- VSS = 12 V Clock = 1536kHz V,n=O d8mO full scale= + 3 dBmO 0875 V p-p TA = - 40 to B5'CI
Characteristic
Gain 1300 Hzl
Responses I Ref 300 Hzl
2400 Hz
4800 Hz
Idle NOise IA,n = VAG. Ref to 600 !II

Min

Typ

17

18

Max
19

-36
-16

-30
-138

-24
-128

Unit

dB
dB

-

13

24

Oynamlc Range I Full Scale Outputlldle NOisel

76

87

DeViation From Linear Phase de to 2400 Hz

-

25

Power Supply Rejection RatiO IVOO = 12 V + 0 1 VRMS @ 1 kHzl

-

76

-

Crosstalk IAIn - VAG. BIn-O dBrnO. Output at Aout at 3 kHzl

36

d8rnc
dB
deg
dB
dB

FILTER B SPECIFICATIONS IVOO-VSS=12V Clock=1536 kHz V,n=OdBmO full scale = +3dBmO 7Vp-p TA=-40t085'CI
Characteristic
Gain 1300 Hzl
Response I Ref 300 Hzl
2400 Hz
4800 Hz

Min
-07

Typ

Max

Unit

±O 15

+07

dB
dB

-36
-16

-30
-141

-24
-128
24

dBme
d8
deg
d8

Idle NOise 1300 Hz. Ref to 600 !II

-

9

DynamiC Range (Full Scale Output/Idle NOise)

76

91

DeViation From Linear Phase (de to 2400 Hz)

-

25

-

-

36
76

-

Power Supply Rejection Ratio IVOO - 12 V + 0 1 VRMS @ 1 kHzl
Crosstalk IB,n - VAG. A,n - 0 dBrnO @ 2 kHz. Output at Boutl

2-305

dB

MC145415
MAXIMUM RATINGS IVSS=OI
Rating
DC Supply Voltage
Input Voilage, All PinS

Symbol

Value

Unit

VOO-VSS
Vin

-0.5 to 18

V

-0 5to VOO +0.5

V

I

10

mA

TA
Tstg

-40 to B5
-65 to 150

·C

DC Current Drain per Pin IExcluding VOO, VSSI
Operating Temperature Range

•

Storage Temperature Range

·C

RECOMMENDED OPERATING CONDITIONS
Parameter
DC Supply Voltage
Clock Frequency'
• Filter frequency response may degrade slightly as clock frequency IS increased above 200 kHz.

DIGITAL ELECTRICAL CHARACTERISTICS 1VOO= 10 V, VSS=O V, VAG=VOOI2, TA= -40 to B5·CI
Symbol

Min

Max

Unit

-

4

mA

Input Capacitance

100
C,n

-

10

pF

Input Low Voltage IPins 10, 111

VIL

-

VOG + 0.3IVOO - VOGI

Input High Voltage (Pins 10, 111

VIH

0.7x 1VOO-VOGI + VOO

IlL

VOO - 0.3 1VOO - VOGI

VOG

VSS

Characteristic
Operating Current

Input Leakage Current (Pins 10,111
VOG Reference Voltage (Pin 91

2-306

-

~A

2.5
VOO

V
V

4.5

V

MC145415
SWITCHING CHARACTERISTICS (VDD- VSS= 12 V TA= - 40 to 85°Cl
Characteristics
Input Rise Time (Pin 101
Input Fall Time (Pin 101
Pulse Width (Pin 101
Clock Pulse Frequency (Pin 101
Clock Duty Cycle (Pin 101

FUNCTIONAL DESCRIPTION OF PINS
VDD (PIN 16)
Positive supply pin.
VSS (PIN 8)
This is the most negative supply pin.

Symbol
tTlH
tTHl
tWH
fCl

-

Min
-

Typ

50

-

40

-

200

Max
4
4
400
60

Units
I's
I's
ns
kHz
%

Bout. LOW-PASS FILTER B OUTPUT (PIN 12)
This is the output from Filter B.
Bin. LOW-PASS FILTER B INPUT (PIN 13)
This is the input to filter B.
Aout, LOW-PASS FILTER A OUTPUT (PIN 14)
This pin is the output from Filter A.

VAG. ANALOG GROUND (PIN 1)
This pin should be held at approximately (VDD - VSSI/2.
All analog inputs and outputs are referenced to this pin.

Ain, LOW-PASS FILTER A INPUT (PIN 15)
This is the input to Filter A.

+A (PIN 2)
Non-inverting input of comparator A.

NOTE: VAG is a high-impedance input.

-A (PIN 3)
Inverting input of comparator A.
AO (PIN 4)
Output of comparator A. This is a standard 'B' series
CMOS output.
BO (PIN 5)
Output of comparator B. This is a standard 'B' series
CMOS output.
-B (PIN 6)
Inverting input of comparator B.
+B (PIN 7)
Non-inverting input of comparator B.
VDG. DIGITAL GROUND (PIN 9)
This pin is logic ground reference for the ClK and lOOP
pins.
CLK, CLOCK (PIN 10)
This is the clock input that determines the location of the
cutoff frequency of the filters as given below:

FILTER DESCRIPTION
FILTER A DESCRIPTION
Filter A of the MC145415 is a 5-pole tunable linear phase
low-pass filter operation at a sampling rate determined by
the clock. The break frequency, which is a function of the
clock, is calculated by dividing the input clock frequency by
64. With a 128 kHz clock, the band limiting frequency is 2
kHz. By dividing the clock in half to 64 kHz the band limiting
frequency is cut in half to 1 kHz. likewise, by doubling the
clock, the cutoff point with double In frequency. The clock
frequency can be varied from 50 kHz to 400 kHz. Filter A,
unlike filter B, has a gain of 18 dB. Because the MC145415 is
a switch capacitance filter, the sampled output signal will
have switching components present near multiples of the
switching frequency and inputs to these filters should be
band-limited to under -3/4 fClK to prevent aliasing.

-3 dB frequency=fClK +64
LOOP (PIN 11)
When this pin is high, the input to filter A is disconnected
from the pad and shorted to the filter B output pin. With this
pin low, the loop back mode is disabled.

FILTER B DESCRIPTION
Filter B in the MC145415 consists of a 5-pole tunable (inear
phase low-pass filter operating at a sampled rate determined
by the clock. Filter B is functionally similar to filter A, except
filter B has unity gain.

2-307

•

MC145415

FIGURE 1 - FILTER A AND B LOW·PASS CHARACTERISTICS

PHASE .ersu. FREQUENCY
IfCLK-153.6 kHz)

GAIN versus FREOUENCY
IfCLK -153.6 kHz)

•

'" ""-

.......
!is

..
..
z

20

j

~

~

iE

-1

-2

1\

60

-3

\

0.1

0.5

50

10

-4

lOa

a

-... I---

'" '"

"'

fin. INPUT FREQUENCY IkHzI
NOTES:

..........

~

~

40

.-

10

f. FREQUENCY IkHzI

1. Break frequency IS equal to the clock frequency+B4.
2. Figure 1 illustrates Filter B performance.
Filter A would be lB dB higher.

FIGURE 2 - TEST CIRCUIT

+6V

0.1 ~F

VAG

VOD

-=A+

A,n

A-

Aout

Filter A and B Inputs
Filter A Output

90011
AO

Bin

BO

Bout

-=
Filter B Output

90011
B-

Loop

B+

CLK

VSS

VDG

-=-=-=-

O.'~F~

-6 V

CLK Input
153.6 kHz

®

MC145418
MC145419

MOTOROLA

Advance Information

Digital Loop Transceivers (DLT)
The MC145418 and MC145419 DLTs are high-speed data transceivers that provide
80 kbps full duplex data communication Intended primarily for use In digital subscriber
vOice/data telephone systems, these devices can also be used In any digital data transfer
scheme (I e , limited distance modems) where bidirectional data transfer IS needed These
devices utilIZe a 256 kilobaud "squared" modified - DPSK burst modulation technique for
transmISSIOn

These devices are designed for compatibility with eXisting, as well as evolving, telephone
switching hardware and software architectures
The DLT chip set consists of the MC145418 master DLT for use at the telephone sWitch
IInecard and the MC145419 slave DLTfor use at the remote digital telset and/or
data terminal
The devices employ CMOS technology In order to take advantage of Its reliable lowpower operation and proven capability for complex analog/digital LSI functions
•
•
•
•
•
•

Provides Full Duplex Synchronous 64 kbps VOice/ Data Channel and Two 8 kbps
Signalling/Data Channels
Compatible With EXisting and EvolVing Telephone SWitch Architectures and Call
Signalling Schemes
Full Duplex 80 Klloblts Transmission for an 8 kHz Frame Rate
Protocol Independent
Single 5 Volt Power Supply
22 Pin Package

MC145418 Master DLT
•
•
•
•

Pin Controlled Power-Down Feature
Signalling and ControlliO Capable of Sharing Common Bus Wiring With Other DLTs
Variable Data Clock - 64 kHz to 2 56 MHz
Pin Controlled Insertion' Extraction of 8 kbps Channel Into LSB of 64 kbps Channel
for Simultaneous Routing of VOice and Data Through PCM VOice Path
of Telephone SWitch

-- •
~
C ERAMIC
CASE 736

,

PIN ASSIGNMENTS
VSS
01

MEa

NC

REI

VO

Rx

SII

TOC/ROC

SOl

CCI

SI2

Tx

S02

TEl

SE

SIE

PO

MSI

VSS

VOO

01

Compatible With MC 14400 Series PCM Mono-CircuitS
Pin Controlled Loop-Back Feature
Automatic Power-Up Down Feature
On-Chip Data Clock Recovery and Generation
Pin Controlled 500 Hz 03 or CelTT Format PCM Tone Generator for Audible Feedback
ApplicatIOns

SYN

lEi

AEI
Ax
ClK

SOl

X2

SI2

Xl

S02

Tx

and Information herein are subJecI to change wlfhoul notice

2·309

MEO

Sil

PO

Sp~cdlcatlon..,

DO

VO

Mu'A

ThiS document contains Inlormatlon on a new product

VOO
00

SYN

MC145419 Slave DlT
•
•
•
•
•

P SUFFIX
PLASTIC
CASE 708

TEl

TE

MC145418, MC145419
MC145418 MASTER DLT BLOCK DIAGRAM

SII

•

MOOULATION
SI2
10
19

00
RECEIVE
MEO

lB

------

SE
REI
Rx

REGISTER
CCI
MSI

16
11

12
SEQUENCE
ANO
CONTROL

13

>------+-+-=-...

PO

SIE

VO

01
SYN
SOl

S02
15
VOO ~ PIN 22
VSS ~ PIN 1

14

17
REGISTER

* - SE

Controlled Latch

2-310

Ix

TEl
TOC ROC

MC145418, MC145419

MC145419 SLAVE DLT BLOCK DIAGRAM

21

00

MEO

:

20

I

6

l

MODULATOR

I

I

!

MOOULATION

,--- ~

i

LOOP
BACK
CONTROL

BUffER

~~
18

RECEIVE
19

-----

SII
SI2

Rx
REI

r--

4
TE

PO

Xl

XI

01
SYN

REGISTER

TONE
GEN

LB

12

10

'---.--

~
16

15

2
3

POWER·
DOWN
CONTROL

SEQUENCE
AND
CONTROL

I

DEMODULATOR

+

DEMODULATION 1

0

~

PIN 22
PIN I

+
BUffER

TRANSMIT
------

---.
*

CLK

+

5

VD CONTROL

VD

f

I

l
VOD
VSS

L),17

I
I
I
I

I

qJI

I
I

MulA

REGISTER

Signal Bits Output Latcll

2·311

--

1.

7

9

14

1

13

SOl

S02

Ix

TE I

MC145418, MC145419
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSSI
Rating

Symbol

DC Supply Voltage

Unit

Value

VDD - VSS

05 to 90

Voltage. Any P,n to VSS

V

05 to VDD'O 5

V

DC Current. Any Pm (Excludmg VDD VSSI

I

+10

mA

TA

40 10 '85

"C

Tstg

85 to ·150

"C

Operatmg Temperature
Storage Temperature

V

RECOMMENDED OPERATING CONDITIONS (TA 0 to 70"C)
0

Pins

Min

Max

VDD

45

55

V

VDD

-

15

mW

Parameter

DC Supply Voltage
Power D,ss'patlOn (PD

0

VDD. VDD

Power D,ss'pat,on (PD

0

VSS, TE

0

5 VI

0

VSSI

VDD

-

10

mW

MSI

79

81

kHz

-

-

025

%

CCI

-

2.048

MHz

TOC,RDC

64

2560

kHz

DO

-

256

kHz

Frame Rate MC145418
MC145418 - MC145419 Frame Rate Slip (See Note 11
eCI Clock Frequency (MSI

8 kHzl

0

Data Clock Rate MC145418

Unit

ModulatIOn Baud Rate (See Note 21

NOTES
1 The MC145419 crystal frequency divided by 512 must equal the MC145418 MSI frequency ± 0 25% for optimum operation
2 Assumes crystal frequency of 4 096 MHz for the MC145419 and 2048 MHz CCI for the MC145418

DIGITAL CHARACTERISTICS (VDD 5 V TA' 0 to 70"CI
0

Unit

Min

Max

Input High Level

35

-

V

Input Low Level

-

15

V

Input Current

-

±10

IJ-A

Parameter

Input Capacitance

10

pF

Output H'gh Current (Except Tx on MC145418
and Tx and PD on MC1454191

VOH 0 25 V
VOH' 46V

17
-036

-

rnA

Output Low Current (Except Tx on MC145418
and Tx and PD on MC1454191

VOL' 04V
VOL' 08V

036
08

-

mA

-

PD Output H'gh Current (MC1454191
(See Note 51

VOH' 25 V
VOH' 4 6V

90

-

IJ-A

10

PD Output Low Current (MC 1454191
(See Note 51

VOV 04V
VOL' 0.8V

60
100

-

IJ-A

Tx Output High Current

VOH
VOH

25V
46V

-34
07

-

mA

Tx Output Low Current

VOL - 04V
VOL' 08V

17
35

-

mA

VSS. MC1454181

100

-

kll

Crystal Frequency IMC1454191 (See Note 31

40

44

MHz
dBmO

Tx Input Impedance (TEl

PCM Tone (TE

0

0

VDD. MC1454191

22

-18

-

±1

IJ-A

46V

450

-

IJ-A

04 V

450

-

~A

Three-State Current (501. 502. VD, Tx on MC145418. Tx on MC1454191
X2 - Osc,IIator Output H'gh Drive Current (MC1454191
(See Note 41

VOH

X2 - Osc,IIator Output Low Drive Current (MC1454191
(See Note 41

VOL

0

NOTES
3 The MC145419 crystal frequency d,v,ded by 512 must equal the MC145418 MSI frequency ±O 25% for opt,mum performance
4

Output drrve when X 1 IS bellig drrven from an external clock

5 To overdrive PO from a low level to 3 5 V or a hIgh level to 1 5 V requires a minimum of ± 800 IJA drive capabllltv

2-312

MC145418, MC145419

MC14541B SWITCHING CHARACTERISTICS (VOO = 5 V. TA = 25°C. Cl = 50pF)
Fig

Symbol

Min

Max

Unit

Input Rise Time

All Olgltal Inputs

1

tr

4

!,s

Input Fall TI me

All Olgltal Inputs

1

tf

-

4

!,s

TOC/ROC. RE 1. MSI

1

tw(H.L)

90

-

ns

1

tw(H.L)

45

55

%

-

toc

64

2560

kHz

2
3

tplH. tpHl

-

90
90

ns
ns

Parameter

Pulse Width

CCI Outy Cycle
Data Clock Frequency

TOC/ROC

Propagation Delay Time

MSI to 501. 502. VO (PO
TOC to Tx

=VOO)

tsu3
t su 4

90
40

-

4

tsu3
tsu4

90
40

-

ns

4
Rx to TOC/ ROC Setup Time

5

tsu5

60

-

ns

Rx to TOC/ROC Hold Time

5

thl

60

ns

511. 512 to MSI Setup Time

6

tsu6

60

511. 512 to MSI Hold Time

6

th2

60

-

00 Valid to MEO RISing

10

tp7

90

ns

00 Valid to MEO Failing

10

tp8

-

90

ns

01 Valid to SYN RISing

11

t su 7

488

1200

ns

01 Valid to SYN Failing

11

tsu8

-

3900

ns

MSI to TOC/ROC Setup Time
TE1/REl to TOCiROC Setup Time

-

ns
ns

MC145419 SWITCHING CHARACTERISTICS (VOO = 5 V. TA = 25°C. Cl = 50pF)
Fig

Symbol

Min

Max

Unit

Input Rise Trme

All Digital Inputs

1

tr

-

4

!'s

Input Fall Time

All Olgltal Inputs

1

tf

-

4

!'s

ClK

1

tw(H,l)

3.8

40

!'s

-

fXl

4086

41

MHz

7
7
7
8

-50
438

8
9
9

tpl
tpl
tp2
tp3
tp4
tp4
tp5
tp6

50
538
40
40
50
538
90
90

Rx to eLK Setup TIme

5

tsu5

60

-

ns

Rx to elK Hold Time

5

thl

60

-

ns

511. 512 to TE 1 Setup Time

B

tsu6

60

-

ns

511. 512 to TE 1 Hold Time

6

th2

60

-

ns

Parameter

Clock Output Pulse Width
Crystal Frequency
Propagation Delay Times
TE 1 RISing to ClK (TE = VOO)
TEl RISing to elK (TE = VSS)

ns

elK to TEl Failing
elK to RE 1 RISing
RE 1 Failing to elK (TE = Vool
RE 1 Failing to ClK (TE " VSS)
elK to Tx
TEl to 501. 502

8

2-313

-

-50
438

-

•

MC145418, MC145419

TIMING DIAGRAMS

TEl IMCI454191
OR
MSIIMCI454181 _ _ _ _

CLit TOC/RDC.
RE1. cel. MSI

•

+-__..JI

Figure 1

MSl

VD. SOl. S02

y£

SII. SI2

---1:~-;.

Figure 6

70%
30%

Figure 2

~

Figure 7

"£r'~;, ~y30%

TOC/ROC Y ' P L H

70%

Tx

Ip4

70%

CLK

Figure 3

70%

Figure 8
TEl. REI. MSI

70%
30%
~--- ',u3 -----1~

Tx

tsu4

TOC/RoC

r rP6
70%

70%

30%

30%

P5

30%
aK

Figure 4

70%

HI

70%

Figure 9

TOC/RoC. CLK

DO

~
de

O%

30%

VAllO = B q ; 0de%
30%

YP7~SIl8
70%

Rx

MEO

Figure 5

30%

Figure 10

2-314

MC145418, MC145419

~ON'T

01

outputs are hIgh Impedance. This allows these pins to be
bussed With those of other DLTs to a common controller

CARE

y''"'

PO -

70%

SYN

Figure 11

MC145418 MASTER DLT PIN DESCRIPTIONS
Voo -

POSITIVE SUPPLY

MSI -

Normally 5 volts
VSS -

POWER-DOWN INPUT

If held low, the DLT ceases modulatIon In power-down, the
only active circUitry IS that which IS necessary to demodulate
an incoming burst and output the sIgnal and valid data bIts.
Internal data transfers to the transmIt and receIve regIsters
cease When brought hIgh, the DLT powers up, and walts
three positive MSI edges or untIl the end of an mcomlng
transmISSIon from the slave DLT and beginS transmItting
every MSI period to the slave DLT on the next rlsmg edge of
the MSI
MASTER SYNC INPUT

This Pin IS the master 8 kHz Input system sync and Inltitates
modulation MSI should be approxImately leading-edge
aligned WIth TDC/RDC.

NEGATIVE SUPPLY

This Pin IS the most negative supply pin, normally 0 volts
SIE 01 -

DATA INPUT

This Input to the demodulator CirCUit should be a squared
and limited versIOn of the received line Signal (See Figure 15 )
SYN - SYNC INPUT
This Input to the demodulator CirCUit should be a Signal
which IS high when sIgnal energy IS detected on the line (See
F,gure 14 for tYPIcal line Interface CirCUit)
ThIs sIgnal should be the output of a window comparator
WIth a threshold of approximately 40% of the smallest
received line signal (See FIgure 15 )

SIGNAL INSERT ENABLE

This Pin, when held hIgh, Inserts signal bit 2 received from
the slave Into the LSB olthe outgoing PCM word at Tx and WIll
Ignore the SI2 pin and use In ItS place the LSB olthe incoming
PCM word at Rx for transmIssion to the slave. The PCM word
to the slave WIll have its LSB forced low In thIS mode. In thIS
manner, signal bIt 2 to/from the slave DLT is Inserted Into the
PCM words the master sends and receives from the backplane for routing through the PABX for SImultaneous voice/
data communIcation. The state of this pin is internally latched
If the SE pin IS brought and held low.
TE1 - TRANSMIT DATA ENABLE 1 INPUT

NC -

NO CONNECTION

Th,s pin IS not available for use and should be left floating
VD - VALID DATA OUTPUT
A hIgh on th,s Pin ind,cates that a valid line transmISSion
has been demodulated. A valid transmIssIon IS determined by
proper sync and the absence of detected bit errors VD
changes state on the leading edge of MSI when PD IS hIgh
When PD IS low, VD changes state at the end of demodulation
of a line transmIssIon VD IS a standard B-serles CMOS output
and IS hIgh Impedance when SE IS held low
S11, SI2 -

ThIS pin controls the outputting of data on the Tx pin, While
TE 1 IS hIgh, the Tx data is presented on the eIght rising edges
of TDC/RDC. TE1 IS also a hIgh-Impedance control of the Tx
pin. If MSI occurs during thiS period, new data will be
transferred to the Tx output regIster in the ninth hIgh period of
TDC/RDC after TE 1 rises; otherwise, it will transfer on the
rising edge of MSI TE 1 and TDC/RDC should be approximately leading-edge aligned
Tx - TRANSMIT DATA OUTPUT
ThIS three-state output pin presents new vOIce data on the
rising edges of TDC/RDC when TE1 IS high (See TEl)

SIGNALING BIT INPUTS

Data on these pinS IS loaded on the rising edge of MSI for
transmiSSIon to the slave The state of these PinS IS Internally
latched If SE IS held low
S01, S02 -

SIGNALING BIT OUTPUTS

These outputs are receIved slgnalmg b,ts from the slave DLT
and change state on the rising edge of MSllf PD IS hIgh, or at
the completIon of demodulatIon If PD IS low These outputs
have standard B-serles CMOS drive capabil,ty and are hIgh
Impedance If the SE pin IS held low
SE - SIGNAL ENABLE INPUT
If held hIgh, the PD, 511, S12, and SIE Inputs and the 501,
S02, and VD outputs function normally If held low, the states
of these Inputs are latched and held Internally whIle the

CCI - CONVERT CLOCK INPUT
A 2048 MHz clock sIgnal should be applied to th,s pin. ThiS
sIgnal IS used for Internal sequencing and control ThIS sIgnal
should be coherent WIth MSI for optimum performance but
may be asynchronous If Slightly worse error rate performance
can be tolerated.
TDC/ROC - TRANSMIT/RECEIVE DATA CLOCK
ThIS pin IS the transmit and receIve data clock and can be
64 kHz to 2.56 MHz. Data IS output althe Tx pin whIle TEl IS
hIgh on the eIght rising edges of TDC/RDC after the rising
edge of TE 1 Data on the Rx Pin IS loaded mto the receIve
regIster of the DLT on the eIght failing edges of TDC/RDC after
a posItIve transItIon on RE1. ThIS clock should be approxImately leadmg-edge aligned with MSI

2-315

MC145418, MC145419
Rx - RECEIVE DATA
Voice data IS clocked Into the DlTfrom this Pin on the failing
edges of TDC/RDC under the control of RE1.

RE1 - RECEIVE DATA ENABLE 1 INPUT

•

A rising edge on this pin will enable data on the Rx Pin to be
loaded Into the receive data register on the next failing edges
olthe data clock, RDC. RE 1 and RDC should be approximately
leading-edge aligned.

DO - DATA OUTPUT
This B-series output is the square wave Modified - DPSK
modulation waveform to be externally buffered and applied 10
the line. This output is valid only when the MEO output pin IS
high and is undefined while MEO is low. The external line
driver should drive the line in a tri-Ievel manner, controlled by
DO and MEO as shown in Figure 15.

from the Internal OSCillator), VD Will go low Without TE 1 rising
Since TE 1 IS not generated In the absence of received
transmisSions from the master (See TE pin deSCription forthe
one exception to thiS.)

511.512 -

SIGNALING BIT INPUTS

Data on these pinS IS loaded on the rising edge of TE 1 for
transmission to the master. If no transmiSSions from the
master are being received and PD IS high, data on these pinS
Will be loaded into the part on an Internal Signal Therefore,
data on these pins should be steady until synchronous
commUnication With the master has been established, as
indicated by the high on YD.
501, S02 - SIGNALING BIT OUTPUTS
These outputs are received Signaling bits from the master
DlT and change state on the rising edge of TE 1. These outputs
have standard 8-serles CMOS output drive capability

MEO - MODULATION ENABLE OUTPUT
This pin, when high, defines the valid data at the DO pin to
be valid.

MC145419 SLAVE DLT PIN DESCRIPTIONS
VDD - POSITIVE SUPPLY
Normally 5 volts.

VSS - NEGATIVE SUPPLY
This pin is the most negative supply pin, normally 0 volts.

01 - DATA INPUT
This Input to the demodulator circuit should be a squared
and limited version olthe received line signal, (See Figure 15.)

SYN - SYNC INPUT
This input to the demodulator CirCUit should be a Signal
which is high when signal energy is detected on the line. (See
Figure 14 for typical line Interface circuit)
This signal should be the output of a Window comparator
with a threshold of approximately 40% of the smallest
received line signal, (See Figure 15.)

LB - LOOP-BACK CONTROL
When this pin is held low and PD is high (the DlT IS
receiVing transmissions from the master), the DlTwill use the
eight bits of demodulated PCM data in place of the eight bits of
Rx data in the return burst to the master, thereby looping the
part back on itself for system testing. SI1 and SI2 operate
normally In this mode. ClK will be held low dUring loop-back
operation.

VD - VALID DATA OUTPUT
A high on this pin indicates that a valid line transmission
has been demodulated. A valid transmission is determined by
proper sync and the absence of detected bit errors VD
changes state on the leading edge of TE 1 If no transmissions
from the master have been received in the last 250 p'S (derived

PO - POWER-DOWN INPUT/OUTPUT
ThiS IS a bidirectional pin With weak output drivers such that
It can be overdrlven externally. When held low, the DlT IS
powered down and the only active circUitry IS: that which IS
necessary for demodulation, TE 1/RE 1/ClK generation upon
demodulation. the outputting of data received from the master
and updating of VD status. When held high, the DlT IS
powered up and transmits In response to received transmissions from the master. If no received bursts from the
master have occured when powered up, for 2501's (derived
from the Internal OSCillator frequency), the DlTwill generate a
free running 1251's internal clock from the Internal OSCillator
and will burst a transmisSion to the master every other
internal 1251'S clock uSing data on the SI1 and SI2 pinS and
the last data word loaded Into the receive register The weak
output drivers Will try to force PD high when a transmiSSion
from the master IS demodulated and Will try to force It low If
2501's have passed Without a transmiSSion from the master
ThiS allows the slave DlT 10 self power-up and down In
demand powered-loop systems

TE - TONE ENABLE
A high on this pin generates a 500 Hz square wave PCM
tone and Inserts It In place of the demodulated vOice PCM
word from the master for outputting to the Tx pin to the telset
mono-circuit. A high on TE Will generate TE1 and ClK from
the Internal OSCillator when the slave IS not receiving bursts
from the master so that the PCM square wave can be loaded
Into the monO-CirCUit ThiS feature allows the user to proVide
audiO feedback for the tel set keyboard depreSSions except
dUring loop-back DUring loop-back of the slave DlT, ClK IS
defeated so a tone cannot be generated In thiS mode

TE1 - TRANSMIT DATA ENABLE 1 OUTPUT
ThiS IS a standard 8-serles CMOS output which goes high
after the completion of demodulation of an incoming transmission from the master. It remains high for eight ClK periods
and then low until the next burst from the master IS
demodulated While high, the vOice data Just demodulated IS
output on the first eight rising edges of ClK at the Tx pin The
Signaling data Just demodulated IS output on S01 and S02 on
TE 1's rising edge, as IS VD

2-316

MC145418, MC145419

Tx - TRANSMIT DATA OUTPUT

BACKGROUND

This IS a standard B-serles CMOS output VOice data IS
output on this pin on the rising edges of CLK while TE 1 IS high
and IS high-Impedance when TE 1 IS low

X1 - CRYSTAL INPUT
A 4.096 MHz crystal IS tied between thiS pin and X2 A
10 Mn reSistor across X1 and X2 and 25 pF capacitors from
X 1 and X2 to VSS are required for stability and to Insure
start-up X1 may be driven by an external CMOS clock signal If
X2 IS left open

X2 - CRYSTAL OUTPUT
ThiS pin IS capable of driVing one external CMOS Input and
15 pF of additional capacitance (See X1 I

CLK - CLOCK OUTPUT
This IS a standard B-serles CMOS output which provides
the data clock for the tel set monO-Circuit It IS generated by
diViding the OSCillator down to 12B kHz and starts upon the
completion of demodulation of an Incoming burst from the
master. At this time, CLK beginS and TE 1 goes high CLK Will
remain active for 16 periods, althe end of which It Will remain
low until another transmission from the master IS demodulated. In thiS manner, sync from the master IS established In
the slave and any clock slip between the master and the slave
is absorbed each frame ClK IS generated In response to an
incoming burst from the master; however, If TE IS brought
high, then CLK and TE 1/RE 1 are generated from the Internal
oscillator until TE IS brought low or an incoming burst from the
master IS received. ClK IS disabled when lB IS held low

Rx - RECEIVE DATA INPUT
VOice data from the tel set mono-circuit IS Input on thiS pin
on the first eight failing edges of CLK after RE 1 goes high
MulA - TONE DIGITAL FORMAT INPUT
This pin determines If the PCM code of the 500 Hz square
wave tone, generated when TE IS high, IS D3 (Mu / A = 11 or
CCITT (MulA = 01 format

RE1 - RECEIVE DATA ENABLE 1 OUTPUT
This IS a standard B-senes CMOS output which IS the
Inverse of TE1 (see TE11. Data IS clocked Into Rx on the failing
edges of CLK while RE1 IS high

DO - DATA OUTPUT
ThiS B-serles output IS the square wave Modlfled-DPSK
modulation waveform to be externally buffered and applied to
the line ThiS output IS valid only when the MEa output pin IS
high and IS undefined while MEa IS low The external line
driver should dnve the line In a 1rI-level manner, controlled by
DO and MEa as shown In Figure 15

The MC145418 Master and MC145419 Slave DLT transceiver les main application IS to bidirectionally transmit the
digital Signals present at a codec/fllter-dlgltal PABX backplane Interface over transmiSSion mediums such as telephone wire pairs or fiber OptiCS ThiS allows the remotlng of
the monO-Circuit In a digital telephone set and enables each
set to have a high speed data access to the PABX SWitching
facility In effect. the DLT allows each PABX subscnber direct
access to the Inherent 64 kbps data routing capabilities of the
PABX
The DLT prOVides a means for transmitting and receiving 64

kbps of vOice data and 16 kbps of Signaling data The DLT IS
a two chip set consisting of a Master and a Slave The master
DLT replaces the codec/fllter and SLiC on the PABX Ilnecard,
and transmits and receives data over the Intended transmission medium to the telset The DLTappears tothe linecard
and backplane as If It were a PCM codec/fllter and has almost
the same digital Interface features as the MC14400 series
monO-Circuits The slave DLT IS located In the telset and
interfaces the monO-CircUit to the transmiSSion medium By
hooking two DLTs back-to-back, a repeater can also be
formed The master and slave DLTs operate In a frame
synchronous manner, sync being established at the slave by
the timing of the master's transmiSSIOn The master's sync IS
denved from the PABX frame sync
The commUnication between master and slave DlTs reqUire
a Single data link In the transmission medium Eight bits of
vOice data and two bits of Signaling data are transmitted and
received each frame In a half duplex manner, Ie, the slave
walts until the transmission from the master IS completely
received before transmitting back to the master TransmiSSion
occurs at 256 kHz bit rate uSing a "squared·· modified form of
DPSK ThiS ·'plng-pong'· mode will allow transmisSion of data
at distances up to 2 km before turnaround delay becomes a
problem The DlT IS so defined as to allow thiS data to be
handled by the Ilnecard, backplane, and PABX as If It were lust
another vOice conversation ThiS allows eXisting PABX hardware and software to be unchanged and yet prOVides SWitched
64 kbps vOice or data commUnications throughout ItS service
area by Simply replaCing a subSCrIber's Ilnecard and telset A
feature In the master allows one ofthetwo Signaling bits to be
Inserted and extracted from the backplane PCM word to allow
Simultaneous vOice and data transmission through the PABX
The slave DlT has a loop-back feature by which the deVice can
be tested rn the user system
The slave DlT has the additional feature of prOViding a 500
Hz Mu or A law coded square wave to the monO-CircUIt when
the TE Pin IS brought high ThiS can be used to prOVide audiO
feedback In the tel set dUring keyboard depreSSions
Although the DlT was Originally deSigned for a PABX
environment, It can be used In any digital synchronous serial
enVironment, such as, computer to computer communications or rndustrlal control

CIRCUIT DESCRIPTION
GENERAL

MEO -MODULATION ENABLE OUTPUT
ThiS pin, when high, defines the valid data at the DO pin to
be valid.

The DlT consists of a modulator, demodulator. two intermediate data buffers, sequencing and control logiC, and
transmit and receive data registers The data registers rnter-

2-317

•

MC145418, MC145419
face to the linecard or mono-circuit digital interface signals,
the modulator and demodulator provide Modified - DPSK
transmission and reception, while the intermediate data
registers buffer data between these two sections. The DlT IS
intended to operate on a single 5 volt supply and can be driven
by TTL or CMOS logic.

•

MASTER OPERATION
In the master, data is loaded into the receive register each
frame from the Rx pin under the control of the TDC/RDC clock
and the receive data enable, RE1. REl controls loading of
eight serial bits, henceforth referred to as the voice data word
Each MSI, these words are transferred out of the receive
register to the modulation buffer for subsequent modulation
onto the line. The modulation buffer takes the received voice
data word and the two signaling data input bits on Sil and SI2
loaded on the MSI rismg edge and formats the ten bits into a
specific order. This data field is then transmitted in a 256 kHz
"squared" Modified-DPSK burst to the remote slave DlT. An
example of the modulated data field at DO is shown with the
Modulation Enable Output (MEO) in Figure 15. V2-Vl is the
differentially driven waveform onto the line in a twisted pair
application.
The received signal coming into the demodulator should be
a squared digital version of the line signal, shown as DI m
Figure 15. The SYN signal which is the output of a window
comparator IS internally integrated and used by the demodulator's synchronization circuitry along with the first zero
crossing of DI to establish the exact position (in time) of the
incoming burst for demodulation purposes. The SYN pulse or
pulses (output of the window comparator circuitry) must be
present for the first eight baud periods of the incoming burst.
They may persist longer but they must not occur withm one
full baud period before the arrival olthefollowing burst. Upon
demodulating the return burst from the slave, the decoded
data is transferred to the demodulation buffer and the
signaling bits are stripped ready to be output on SOl and S02
at the next MSI. The voice data word is loaded into the
transmit register as described in the TEl pin description for
outputting via the Tx pin althe TDC/RDC data clock rate under
the control of TEl. VD is output on the rising edge of MSI.
Timing diagrams for the master are shown in Figure 12.
SLAVE OPERATION
In the slave, the synchronizing event IS the detection of an
mcoming transmission from the master as indicated by the
completion of demodulation. (The SYN signal and DI function
the same as in the Master.) When an incoming burst from the
master IS demodulated, several events occur. As m the
master, data is transferred from the demodulator to the
demodulation buffer and the signaling bits are stripped for
outputting at SOl and S02. Data m the receive register IS
transferred to the modulation buffer. TEl goes high loadmg In
data at Sil and S12, which will be used in the transmission

burst to the master along with the data In the transmit data
buffer. At the same time SOl, S02, and VD are output.
Modulation of the burst begins four 256 kHz periods after the
completion of demodulation.
While TEl is high, data IS output atTx on the rising edges of
ClK. On the ninth rising edge of ClK, TE 1 goes low, RE 1 goes
high, and data IS Input to the receive register from the Rx pin
on the next eight falling edges of ClK
The ClK pin IS a 128 kHz output that IS formed by dividing
down the 4.096 MHz crystal frequency by 32. Slippage
between the frame rate of the master (as represented by the
completion of demodulation of an Incoming transmiSSion
from the master) and the crystal frequency IS absorbed by
holding the 16th low period of elK until the next completion of
demodulation. This is shown in the slave DlTtimlng diagram
of Figure 13.

POWER-DOWN OPERATION
In the master, when PD IS low, the DlT stops modulating
and only that circUitry necessary to demodulate the Incoming
bursts and output the signaling and VD data bits IS active In
this mode, If the DlT receives a burst from the slave, the SO 1,
S02, and VD pins Will be updated upon completion of the
demodulation Instead of on the rising edge of MSI The state of
these pins will not change until either three rising MSI edges
have occurred without the reception of a burst from the slave
or until another burst IS demodulated, whichever occurs first.
When PD is brought high, the master DLT Will walt either
three riSing MSI edges or until the MSI rising edge follOWing
the demodulation of an incoming burst before transmitting to
the slave. The data for the first transmiSSion to the slave after
power-up IS loaded into the DlTdurlng the REl period prior to
the burst for Rx data, and on the present riSing edge of MSI for
signaling data.
In the slave, PD is a bidirectional Pin With weak output
drivers such that It can be overdriven externally When held
low, the DlT slave IS powered down and only that circUitry
necessary for demodulation, TE 1 /REl /ClK generation upon
demodulation, the outputting of Tx data, signaling bitS, and VD
IS active. When held high, the DlT slave IS powered up and
transmits normally In response to received transmiSSions
from the master. If no bursts have been received from the
master within 250 P.s after power-up (derived from the
internal oscillator frequency), the DlT generates an Internal
125 P.s free-running clock from the Internal oscillator. The
slave DLT then bursts a transmission to the master DLT every
other 125 P.s clock period using data loaded Into the Rx pin
dUring the last RE 1 period and S11, SI2 data loaded In on the
Internal 125 P.s clock edge The weak output drivers Will try to
force PD high when a transmiSSion from the master IS
demodulated and will try to force It low If 250 p'S have passed
Without a transmiSSion from the master ThiS allows the slave
DLT to self power-up and down' In demand powered-loop
systems.

2-318

MC145418, MC145419

~1·'--------------------------125~S--------------------------~·~1
MSI

[\\\

,'"

,~'

,,,',t,'

CCIITDC/RDC

...

[\\\

IN

TEl

T,

IN

~~~,____T_HR_EE_.S_l_AT_E__~'~~'________)1J)~'____________________

c:

REI
I~{

;~{

II'

;~I

R,

n;UDDATA

IN

t"

DON'T CARE

IN

Ii

;'~',
~~---II-----I~--~r---~::'~:-~~
,V
I

;~{

=x---(!------(!-------If'-----/,::I---:
::
_~~
,v
;~(

VD

I""

OUT

I

II

SOl. S02

IN

OUT

//

;~(

OUT

o

DEMODULATION
COMPLETE
IINTERNALI

~

TRANSfER RECEIVE REGISTER TO MODULATION BUffElt LATCH VALID
DATA PIN. LATCH SII. SI2 TWO CCI CLOCKS LATER. TRANSfER
RECEIVE REGISTER TO MODULATION BUffElt START MODULATION

Figure 12. Master DLT TIming

2-319

TRANSfER DEMODULATOR
DATA TO DEMODULATION
BUffER
(DEMODULATION flNISHEDI

MC145418, MC145419

~1·'------------------------125M'------------------------~·~1

n

DEMODULATOR
SYNC (INTERNAL)

,/

I

•

in n n
I

CLK (128 kHz)

II

0

0

,I'

NOTE 1 :

,n 0 Don 110 0 :0 [
~:

II

j)

II
II
II

II

II

INTERNAL 2 048
MHz fROM XI.I

TEl

~...

,~

IV

~I----~;~::--~--~,)~,--~i-I

REI

Tx

I

j

,II

OON'T C A R E : :

Ax

511. SI2

501.502

D
J
J

r

VO

i

:;:

I-VOICE
---+--l
~~~~~-CE-----------------

L
[-

OON'T CARE

VOICE

~:

::
:::
TRANSfER OEMODULATION BUffER TO TRANSMIT REGISTER. GENERATE ENABLES
LATCH 511.512. OUTPUT Tx. 501. S02. OUTPUT VAllO OATA. START 128 kHz
CLOCK. START MOOULATION AfTER fOUR 256 kHz BIT PERIODS

OEMOOULATOR DATA TRANSfER TO
OEMOOULATION BUffER

NOTE
1 Slip between master and slave

Figure 13. Slave DLT Timing

IS

taken up

In thiS

period

MC145418, MC145419
MC54174HCOO

VI

n

~

2

220

MEO
~ .-------~----~~

T1
OT

20
21
MCI4541B/I9

+5 V

2

f-------,
Ik
OR

lM339

50 k

Figure 14. Typical DlT line Interface

2-321

•

MC145418, MC145419

•

MEO

~

DO

~

.,::
V-

-

L

n n

0

,~,

on

n UCb~fl
U
L,,;------J

"See Figure 14 for voltages V2, V1 IV+I must equal IV-I within 5°'0
V2-V1, when MEO IS low, must equal (V+ V-) 2 within 5°/0

VTH+

VTH-

SYN (OUTPUT
OF WINDOW
COMPARATOR)

I
I

I
I

I

I

I

I

I
I

I
I

rl--~I rl--~

I

I

r-~i~1

I

01
I
I
~

I

I

I

1-4--- Tsh **
I

**T sh - SYN should be high a minimum of three 4 096 MHz clock periods before the
first zero crossing as Indicated by 01 state change

Figure 15. Une Driver Waveforms

2-322

p

' - - - - - - l .
•

®

MC145421
MC145425

MOTOROLA

Product Preview

160 kbps ISDN Universal
Digital Loop Transceivers
The MC145421 and MC145425 UDLTs are high speed data transceivers capable of providing 160 kbps full duplex data communication over 26 awg and larger twisted pair cable
up to 1 km in length and up to 2 km with the addition of a simple passive equalizer. These
devices are primarily used in digital subscriber voice and data telephone systems. In addition, the devices meet and can exceed the CCITI's recommendation for data transfer rates
for ISDNs on a single twisted pair. The devices utilize a 512 kilobaud MDPSK burst
modulation technique to supply the 160 kbps full duplex data transfer rates.
The MC145421 and MC145425 UDLTs are designed for upward compatibility with the
existing MC145422 and MC145426 80 kbps UDLTs as well as compatibility with existing
and evolving telephone switching hardware and software architectures.
The MC145421 (Master) UDLT is designed for use at the telephone switch line card
while the MC145425 (Slave) UDLT is designed for use at the remote digital telset or data
terminal.
These devices employ CMOS technology in order to take advantage of its proven
capability for complex analog and digital LSI functions.
• Provides Synchronous Full Duplex 160 kbps Voice and Data Capabilities in a 2B + 2D
Format for ISDN Compatibility
• Provides CCITI Basic Access Data Transfer Rate (2B + D) for ISDNs on a Single
Twisted Wire Pair up to 2 km
• Compatible with Existing and Evolving Telephone Switch Architectures and Call
Signalling Schemes
• Automatic Threshold Adjustment for Optimum Performance Over Varying Signal
Attenuations
• Protocol Independent
• Single 5 V Power Supply

PIN ASSIGNMENTS
MC145421
24 VOO
23 LOI
22 L02
21 IR,

VSS
Vrel
LI
[8
VO
011

REN2
RENI
TOC/ROC
CC/
MSI
TENI
TEN2
T,

021
OCLK
DID
020 10
SE 11

PO

12
MC145425

VSS
Vrel
LI
[8

VOO

LOI

021
OCLK
010
020
~A

PO

L02
R,

4

BCLK
19 4MHz

VO
011

10
11
12

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

2-323

•

L SUFFIX
CERDIP
CASE 623

18
17
16
15
14
13

X2
Xl
TONEI
ENI
EN2
T,

®

MC145422
MC145426

MOTOROLA

Advance Information

•

Universal Digital-Loop
Transceivers (UDLT)
The MCl46422 and MCl45426 UDLTs are high-speed data transceivers that provide 80
kilobits per second full duplex data communication over 26 AWG and larger twisted pair
cable up to two kilometers in distance. Intended primarily for use in digital subscriber
voice/ data telephone systems, these devices can also be used in remote data acquisition
and control systems. These devices utilize a 256 kilobaud modified differential phase shift
keying burst modulation technique for transmission to minimize RFIIEMI and crosstalk.
Simultaneous power distribution and duplex data communication can be obtained using a
single twisted pair wire.
These devices are designed for compatibility with existing, as well as evolving,
telephone switching hardware and software architectures.
The UDLT chip-set consists of the MCl46422 master UDLT for use at the telephone
switch linecard and the MCl45426 slave UDLT for use at the remote digital telset and/or
data terminal.
The devices employ CMOS technology in order to take advantage of its reliable lowpower operation and proven capability for complex analog/digital LSI functions.
'. Provides Full Duplex Synchronous 64 Kilobits-Per-Second Voice/Data Channel and
Two Eight Kilobits-Per-Second Signaling Data Channels Over One 26 AWG Wire Pair
Up to Two Kilometers
• Compatible with Existing and Evolving Telephone Switch Architectures and Call Signaling Schemes
• Automatic Detection Threshold Adjustment for Optimum Performance Over Varying
Signal Attenuations
• Protocol Independent
• Single Five Volt Power Supply
• 22 Pin Package

.L SUFFIX
CERAMIC
CASE 736

PIN ASSIGNMENTS
MCl46422
VSS
vlel

Voo
LOl

II

L02

j]j

REl

vo

Rx

Sil

TOC/ROC

SOl

CCI

SI2

To

S02

TEl

SE

SIE

PO

MSI
MC145426

VSS
VIet

VOO
LOI

MCl45422 Master UDLT

II

L02

•
•
•
•

j]j

REI

Pin Controlled Power-Down and Loop-Back Features
Signaling and Control 110 Capable of Sharing Common Bus Wiring with Other UDLTs
Variable Data Clock-64 kHz to 2.56 MHz
Pin Controlled Insertion/Extraction of Eight Kilobits/Second Channel into LSB of
64 Kilobits/ Second Channel for Simultaneous Routing of Voice and Data Through
PCM Voice Path of Telephone Switch

MC145426 Slave UDLT
•
•
•
•
•

Compatible with MCl4400 Series PCM Mono-Circuits
Pin Controlled Loop-Back Feature
Automatic Power-Up/Down Feature
On-Chip Data Clock Recovery and Generation
Pin Controlled 500 Hz 03 or CCITI Format PCM Tone Generator for Audible Feedback
Applications

This document contains information on a new product, Specifications and information herein are subject to change without notice.

2-324

VO

Rx

Sil

CLK

SOl

X2

SI2

Xl

S02

Tx

MulA

TEl

PO

TE

MC145422, MC145426
MC145422 MASTER UDLT BLOCK DIAGRAM

SI1
LOl
10
19
L02

18

SI2
SE
REl
Rx

[8

11

Po

CCI ..._.:.;16"-+---+-----.1
13
MSI ..._.:..:12"-+---+---......~

SIE

VO

SOl
VOO·PIN 22
VSS·PIN 1
Vref=PIN 2

S02
15
14
17
REGISTER

* - SE controlled latch

2-325

Tx
TEl
TOCIROC

MC145422, MC145426
MC145426 SLAVE UDLT BLOCK DIAGRAM

LOI

r1+--------f----,----...,...,---~SII

21

15
>:3

•

L02

SI2

c=>
c

20

-+__.c:19,+_ REI

:;;

-+__-+_..:.10:....c M~A

14I_ _ _ _
[jj
TE

12

1-_-.4....__t--_1:..:.7_

PO

eLK

X2
Xl

~----r--+-~VO

II

.-+----'... SOI
VOO-PIN 22
VSS·PIN 1
Vref-PIN 2

HI--+----=:.. S02
>1f---,1c.c4_
RESISTER

* - Signal Bits Output Latch

2-326

Tx

,.._ _ _ _ _ _.....~-'-'13'+_ TEl

MC145422, MC145426
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to Vssl
Rating

Symbol

Value

Unit

VDD-VSS

-0.5 to 9.0

V

Voltage, Any Pin to VSS

V

-0.5 to VDD+0.5

V

DC Current, Any Pin (Excluding VDD, VSSI

I

±1O

rnA

TA

-40 to +85

°C

Tstg

-85to +150

°C

DC Supply Voltage

Operating Temperature
Storage Temperature

RECOMMENDED OPERATING CONDITIONS (TA=O to 70°CI
Parameter

Pins

Min

Max

Unit

DC Supply Voltage

VDD

4.5

5.5

V

Power Dissipation (PO = VDD, VDD = 5 VI

VDD

-

80

mW

Power Dissipation (PO = VSS, TE = VSSI

VDD

-

75

mW

Frame Rate MCl45422

MSI

7.9

8.1

kHz

-

-

0.25

%

CCI

-

2.048

MHz

TOC, ROC

54

2560

kHz

L01, L02

-

256

kHz

MC145422-MCl46426 Frame Rate Slip (See Note 1I
CCI Clock Frequency (MSI = 8 kHzI
Data Clock Rate MCl46422
Modulation Baud Rate (See Note 21

NOTES: 1. The MCl46426 crystal frequency divided by 512 must equal the MCl46422 MSI frequency ± 0.25% for optimum operation.
2. Assumes crystal frequency of 4.096 MHz for the MC145426 and 2.048 MHz CCI for the MC145422.

DIGITAL CHARACTERISTICS (VDD =5 V, TA =0 to 70°CI
Min

Parameter

Max

Unit

Input High Level

3.5

Input Low Level

-

1.5

V

Except LI
LI

-1.0
-100

1.0
100

~A

7.5

pF

Output High Current (Except Tx on MC145422
and Tx and PO on MCl464261

VOH=2.5V
VOH=4.6V

-1.7
-0.36

-

rnA

Output Low Current (Except Tx on MCl46422
and Tx and PO on MCl464261

VOL=0.4V
VOL=0.8V

0.36
0.8

-

rnA

PO Output High Current (MC1464261
(See Note 71

VOH=2.5V
VOH=4.6V

-90

-

~A

-10

-

PO Output Low Current (MC1454261
(See Note 71

VOL =O.4V
VOL =0.8V

60
100

-

~A

Tx Output High Current

VOH=2.5V
VOH=4.6V

-3.4
-0.7

-

rnA

Tx Output Low Current

VOL =O.4V
VOL =0.8 V

1.7
3.5

-

rnA

Input Current

-

Input Capacitance

-

V

-

Tx Input Impedance (TEl = VSS, MC1454221

100

-

kll

Crystal Frequency (MC145426, Note 31

4.0

4.4

MHz

PCM Tone (TE=VDD, MCl464261

-22

-18

dBmO

Three-State Current (SOl, S02, VD, Tx on MC146422, Tx on MC1454261

-

±1

~A

Vref Voltage (See Note 61

2

3

V

X2-0scillator Output High Drive Current
(MCl464261 (See Note 51

VOH=4.6V

-450

-

~A

X2 - Oscillator Output Low Drive Current
(MCl464261 (See Note 51

VOL =O.4V

450

-

~A

2-327

II

MC145422, MC145426
ANALOG CHARACTERISTICS (Voo = 5 V, TA = 0 to 70°C)
Parameter

Modulation Oifferential Amplitude (Rl = 440 m

lOl to l02

Modulation Oifferential OC Offset
Demodulator Input Amplitude (See Note 4)

•

Oemodulator Input Impedance

Min

Max

Unit

4.5

6.0

Vp _p

0

300

mV

0_050

2.5

V peak

50

150

kll

NOTES:
3. The MCl45426 crystal frequency divided by 512 must equal the MCl45422 MSI frequency ± 0.25% for optimum performance.
4. The input level into the demodulator to reliably demodulate incoming bursts. Input referenced to Vref.
5. Output drive when X1 is being driven from an external clock.

6. Vref typically (9/20 VOo-VSS)
7. To overdrive

PO from

a low level to 3.5 V or a high level to 1.5 V requires a minimum of ±800 /LA drive capability.

MC146422 SWITCHING CHARACTERISTICS (VOO=5 V, TA = 25°C, Cl =50 pF)
Fig

Symbol

Min

Max

Unit

Input Rise Time

All Oigitallnputs

1

tr

-

4

~s

Input Fall Time

All Oigitallnputs

1

tf

-

4

~s

TOC/ROC, RE1, MSI

1

tw(H,l)

90

-

ns

1

tw(H,L)

45

55

%

-

toc

64

2560

kHz

2
3

tPlH, tpHl

-

90
90

tsu3
tsu4

90
40

-

4

tsu3
tsu4

90
40

Rx to TOC/ ROC Setup Time

5

tsu5

60

Rx to TOC/ROC Hold Time

5

thl

60

-

ns

4

511, 512 to MSI Setup Time

6

tsu6

60

-

ns

511, 512 to MSI Hold Time

6

th2

60

-

ns

Parameter

Pulse Width
CCI Outy Cycle
Oata Clock Frequency

TOC/ROC

Propagation Oelay Time
MSI to 501, 502, VO
TOC toTx

ns

(PO = VOO)

MSI to TOC/ROC Setup Time
TE1/RE1 to TOC/ROC Setup Time

ns

-

ns
ns

MC146426 SWITCHING CHARACTERISTICS (VOO=5V, TA = 25°C, Cl=50 pF)
Fig

Symbol

Min

Max

Unit

Input Rise Time

All Oigitallnputs

1

tr

4

~s

Input Fall Time

All Oigitallnputs

1

tf

-

4

~s

ClK

1

tw(H,L)

3.8

4.0

~s

Crystal Frequency

-

fXl

4.086

4.1

MHz

Propagation Oelay Times
TEl Rising to ClK (TE = VOO)
TEl Rising to ClK (TE=VSS)
ClK to TEl Falling
elK to REl Rising
REl Falling to ClK (TE=VoO)
REl Falling to ClK ITE=VSS)
elK to Tx
TEl to 501,502

7
7
7
8
8
8
9
9

tp1
tp1
tP2
tP3
tp4
tp4
tps
tP6

50
438

-

50
538
40
40
50
538
90
90

Parameter

Clock Output Pulse Width

ns

-50
438

-

Rx to elK Setup Time

5

lsu5

60

-

ns

Rx to ClK Hold Time

5

thl

60

-

ns

S11, SI2 to TEl Setup Time

6

tsu6

60

-

ns

511, SI2 to TEl Hold Time

6

th2

60

-

ns

2-328

MC145422, MC145426
SWITCHING WAVEFORMS

•

CLK. TOC. RDC. RE 1. CCl. MSI

t,

Figure 1

MSI

Figure 2

TDC

Tx

Figure 3

2-329

MC145422, MC145426

TEl, RE1, MSI

tsu4

•

TOC, ROC

Figure 4

O%

TOC, ROC, CLK

~

tsu5

30%

~---------------------

""~f----thll--~~I
70%
Rx

30%

Figure 5

TEl IMC145426) OR MSIIMC145422)

Figure 6

2-330

MC145422, MC145426

TEl

CLK

Figure 7

REl

CLK

Figure 8

Figure 9

2-331

•

MC145422, MC145426
PO-POWER-DOWN INPUT

MC145422 MASTER UDLT PIN DESCRIPTIONS
VOO-POSITIVE SUPPLY
Normally 5 volts.
VSS-NEGATIVE SUPPLY

•

This pin is the most negative supply pin, normally 0 volts.
Vref- REFERENCE OUTPUT
This pin is the output of the internal reference supply and
should be bypassed to VOO and VSS by 0.1 I'F capacitors.
No external dc load should be placed on this pin.
LI-LiNE INPUT
This input to the demodulator circuit has an internal 100 k
resistor tied to the internal reference node so that an external
capacitor and/or line transformer may be used to couple the
input signal to the pal'! with no dc offset.
LB-LOOP-BACK CONTROL
A low on this pin disconnects the LI pin from internal circuitry, drives L01, L02 to Vref and internally ties the
modulator output to the demodulator input which loops the
part on itself for testing in the system. The state of this pin is
internally latched if the SE pin is brought and held low. LoopBack is active only when PO is high ..

If held low, the UOLT ceases modulation. In power-down,
the only active circuitry is that which is necessary to
demodulate an incoming burst and output the signal and valid
data bits. Internal data transfers to the transmit and receive
registers cease. When brought high, the UOLT powers-up,
and waits three positive MSI edges or until the end of an incoming transmission from the slave UOLT and begins
transmitting every MSI period to the slave UOLT on the next
rising edge of the MSI.
MSI-MASTER SYNC INPUT
This pin is the system sync and initiates the modulation on
the twisted pair. MSI should be approximately leading-edge
aligned with TOC/ROC.
SIE-SIGNAL INSERT ENABLE
ihis pin, when held high, inserts signal bit 2 received from
the slave into the LSB of the outgoing PCM word at Tx and
will ignore the SI2 pin and use in place the LSB of the incoming PCM word at Rx for transmission to the slave. The PCM
word to the slave will have LSB forced low in this mode. In
this manner, signal bit 2 to/from the slave UOLT is inserted into the PCM words the master sends and receives from the
backplane for routing through the PABX for simultaneous
voice/data communication. The state of this pin is internally
latched if the SE pin is brought and held low.
TE1- TRANSMIT DATA ENABLE 1 INPUT

VO-VALIO DATA OUTPUT
A high on this pin indicates that a valid line transmission has
been demodulated. A valid transmission is determined by proper sync and the absence of detected bit errors. VO changes
state on the leading edge of MSI when PO is high. When PO is
low, VO changes state at the end of demodulation of a line
transmission. VO is a standard B-series CMOS output and is
high impedance when SE is held low.

This pin controls the outputting of data on the Tx pin. While
TE1 is high, the Tx data is presented on the eight rising edges
of TOC/ROC. TE1 is also a high-impedance control of the Tx
pin. If MSI occurs during this period, new data will be transferred to the Tx output register in the ninth high period of
TOC/ROC after TE1 rises; otherwise, it will transfer on the rising edge of MSI. TE1 and TOC/ROC should be approximately
leading-edge aligned.
Tx- TRANSMIT OATA OUTPUT

SI1, SI2-SIGNALING BIT INPUTS
Oata on these pins is loaded on the rising edge of MSI for
transmission to the slave. The state of these pins is internally
latched if SE is held low.
S01, S02-SIGNALING BIT OUTPUTS
These outputs are received signaling bits from the slave
UDLT and change state on the rising edge of MSI if PO is high,
or at the completion of demodulation if PO is low. These outputs have standard B-series CMOS drive capability and are
high impedance if the SE pin is held low.
SE-SIGNAL ENABLE INPUT
If held high, the PO, LB, SI1, SI2, and SIE inputs and the
S01, S02, and VO outputs function normally. If held low, the
state of these inputs are latched and held internally while the
outputs are high impedance. This allows these pins to be
bussed with those of other UDLTs to a common controller.

This three-state output pin presents new voice data during
the high periods of TOC/ROC when TE1 is high (see TE1).
CCI-CONVERT CLOCK INPUT
A 2.048 MHz clock signal should be applied to this pin. The
signal is used for internal sequencing and control. This signal
should be coherent with MSI for optimum performance but
may be asynchronous if slightly worse error rate performance
can be tolerated.
TOC/RDC- TRANSMIT/RECEIVE DATA CLOCK
This pin is the transmit and receive data clock and can be 64
kHz to 2.56 MHz. Oata is output at the Tx pin while TE1 is high
on the eight rising edges of TOC/ROC after the rising edge of
TE1. Oata on the Rx pin is loaded into the receive register of
the UOLT on the eight falling edges of TOC/ROC after a
positive transition on RE1. This clock should be approximately
leading-edge aligned with MSI.

2-332

MC145422, MC145426
Rx-RECEIVE DATA
Voice data is clocked into the UDlT from this pin on the failing edges of TDC/RDC under the control of RE1.
RE1-RECEIVE DATA ENABLE 1 INPUT
A rising edge on this pin will enable data on the Rx pin to be
loaded into the receive data register on the next eight falling
edges of the data clock, TDC/RDC. REl and TDC/RDC
should be approximately leading-edge aligned.

master are being received and PD is high, data on these pins
will be loaded into the part on an internal signal. Therefore,
data on these pins should be steady until synchronous communication with the master has been established, as indicated
by the high on VD.
S01. S02-SIGNALING BIT OUTPUT5
These outputs are received signaling bits from the master
UDlT and change state on the rising edge of TEl. These outputs have standard B-series CM05 output drive capability.

L01, L02-L1NE DRIVER OUTPUTS
These outputs drive the twisted pair line with 256 kHz
modified DP5K bursts each frame and are push-pull. These
pins are driven to Vref when not modulating the line.

MC145426 SLAVE UDLT PIN DESCRIPTIONS
VDD-POSITIVE SUPPLY
Normally 5 volts.
VSS-NEGATIVE SUPPLY
This pin is the most negative supply pin, normally 0 volts.
V ref- REFERENCE OUTPUT
This pin is the output of the internal reference supply and
should be bypassed to VDD and V55 by O.lI'F capacitors. No
external dc load should be placed on this pin.
L1-L1NE INPUT
This input to the demodulator circuit has an internal 100
kilohm resistor tied to the internal reference node IVref) so
that an external capacitor and/ or line transformer may be used
to couple the signal to this part with no dc offset.

PD- POWER-DOWN INPUT/OUTPUT
This is a bidirectional pin with weak output drivers such that
it can be overdriven externally. When held low, the UDlT is
powered down and the only active circuitry is: that which is
necessary for demodulation, TE1/RE1/ClK generation upon
demodulation the outputting of data received from the master
and updating of VD status. When held high, the UDlT is
powered-up and transmits in response to received transmissions from the master. If no received bursts from the master
have occurred when powered-up, for 250 I's (derived from the
internal oscillator frequency). the UDlT will generate a free
running 1251's internal clock from the internal oscillator and
will burst a transmission to the master every other internal 125
I's clock using data on the 511 and 512 pins and the last data
word loaded into the receive register. The weak output drivers
will try to force PD high when a transmission from the master
is demodulated and will try to force it low if 250 I's have passed
without a transmission from the master. This allows the slave
UDlT to self power-up and down in demand powered loop
systems.
TE- TONE ENABLE

When this pin is held low and PO is high (the UDlT is receiving transmissions from the master), the UDlT will use the
eight bits of demodulated PCM data in place of the eight bits
of Rx data in the return burst to the master, thereby looping
the part back on itself for system testing. 511 and 512 operate
normally in this mode. ClK will be held low during loop-back
operation.

A high on this pin generates a 500 Hz square wave PCM
tone and inserts it in place of the demodulated voice PCM
word from the master for outputting to the Tx pin to the telset
mono-circuit. A high on TE will generate TEl and ClK from
the internal oscillator when the slave is not receiving bursts
from the master so that the PCM square wave can be loaded
into the mono-circuit. This feature allows the user to provide
audio feedback for the telset keyboard depressions except
during loop-Back. During loop-Back of the slave UDlT, ClK
is defeated so a tone cannot be generated in this mode.

VD-VALID DATA OUTPUT

TE1- TRANSMIT DATA ENABLE 1 OUTPUT

A high on this pin indicates that a valid line transmission has
been demodulated. A valid transmission is determined by proper sync and the absence of detected bit errors. VD changes
state on the leading edge of TEl. If no transmissions from the
master have been received in the last 250 i>->>n
Nc.>.&:IoU1--1
e n ---' -I :::::a
en

0')

MC14418
;';;fonoO:l>cP:r:Ji:f
rn rn NCI) ..... 0 0 .....

~C;I~

~-

-II---<

110 4 •

l

J

N-0.5

U

110

N=2

-=

1"0 4 ~

110

T

~

-~ Ii N-4

N-0.5~

IC

5.1 k

O.l.F,1

4~

~21 lOl
VOD
2~

4~

~~.l.fl

~G

r

20 Vret
3 l02
1I
-~8 Sil
7 SI2
SOl
,.----.---1. S02
~ VO
[8

~5.1k4~51k

RING

N

-=

110 4 I' 110

'----'

-~
N-0.5~

2~ lOl

N
~

VREF
3 l02
1I
6 Sil
8 SI2
7 SOl

~S02
"------" VO

~[8

en
en

MSI 12
Tx ~
lB
Rx
17
TIRDC
CCI
Pi} 11
19
REl
14
TEl
13
SIE
10
SE 1
VSSt}

§il

1m

M-Ic;

~

<;;1",1 .. 1""

-»l»C"':I
Nw"C::O'tl"I-I
-I:=IJ
en

cnncncn .....

c n .....

MC14418

.lY

:::::a - t
n
<:
",,..cnCP):Iocr-:::::acn

I'T'II'T'INcn .... C C ..... ::-::NCI)

L..-.J ~Ic;t ~  "'~

L....-,-

3:

0

...a.
01::0

(It
10 V

5V

16 VOO

ROD 15

14 Tx

6 MulA

RCE 14

13 TEl

TOO 11

18 Rx

TOE 10

19 REl

TOC 12

17 CLK

10 k
7pjj"

MONO·
CIRCUIT
MC14403

5 Tx4 Txl
2
RxO

ROC 13

3 Tx+
RCVRI I I

-=

5V
tOOk

S1A CLOSED - ON HOOK

10 M

r

SlB OPEN-ON HOOK

I

(,.)
~

4-

-=

....

3:

TIP

01::0

8 SI2

VO 5

12 TE

LOl 21
L02 20
MulA

~~
iWl

COll

Sil 6

16 X2

VSS

COL3
16 ROWl
15

iiliW2

PULSE
DIALER
MC145409

14 ROW3

I ~ RING

-=

120 PF

20

10 k

18

OHIT 17

COL2

en

10

15 Xl

10 V
VOO

01::0
N

Vret 2

4.096 MHz

OPF

5V

10 V

TSO 2
47 k

IQ

220 k

13 ROW4

rO.l~F

VSS

V
-:::!::-

2M

=

ANALOG GROUND

=

DIGITAL GROUND

0
...a.
(It

UOLT
MC145426

9 S02

VAG

I\)

~

7 SOl

1 VAG

01::0
N

5V

-=

Figure 16. Basic Digital Telset

II

+ 12

0.1 pF

0.1 pF

~h
rN
M
N

3

"-

r

vIs

VSS -5 V

l.q~ RxO

5k
R6
500

o

~

'

I'F

R13

I

10k

R8

T

56k

4

5 RxO
6
+Tx
7' 10 k 7
Txl
8
- Tx
S2·SW3 9
MulA
S2·SW2 10

r
-

,

11
Rl 2

RxG

-

10pF~POI

~C12

VOO

'"c

-5

21
VOOr20
ROO
19
RCE
18
ROC

c

U
:;;

CCI

TOE
MSI

-

Tx3

013

~
9

GN°l

t"
-=

16

VOD

1
NC- T,S
2
TxO
SI·SW5 3
OL
4
NC- BRCLK
5 BC

.


N

:l1;

S~ BRI

-

S~

3!:

o....

VOO
RESET 2!!...V(
18
OCO

-

Sl·SW3 7

C14

(

20

U

:;;

BR2

.j:Io

U'I

.j:Io

N

OOE ..!2....VOD
16
CM

,!')

---:;1.

OC

3!:

15 -

o....

OlE ~VOO
13

.j:Io

~
N
en

DCl

BR3

S~ SB
10
~ VSS

RxS

r!!NC
11

Rxol

v

20 pF

TOC

TOO

:;;

[

8

Rl
10 M

... ffit
N

r---

-

U

VSS

RSI~ Cl~

VAG

VAG

~O pF

22

~ Vr,!

Co)
~

7
8

VOO

f
N

-

Cl0

15

14
011 i - - 13
002
12
012
11
003

.'".

Rx2

~ Tx2
~ Rx3

L!lliP

R5

001

Txl

4

a:
'"

NI

VCC~

-2.. Rxl

~
l

Cll~

-=1

~VOO
2 TxO

•

+5 V

V

=Yl
T4.096 MHz

12
-TE
13
TEl
14 Tx
15
Xl
16 X2

C2
17

CLK
IS Rx

15
14

bJ
12

VlS8

VSS

-

10 S2·SW4
MulA I--S02 9
SI2 8

...'"'"
N

'-'
:;;

19 REI
20
L02
21
LOI
22
VOO

R9
220

HOOK
SWITCH

01 R11
• l Tl

~~.
10 k
02 N=4

~

OIGITAL GROUNO

L,~

jjj~W5
+5 V

2
Vref 1
VSS
RIO
220

Figure 17. Full Featured Digital Telset

5k

VO~NC

1I

~ - ANALOG GROUNO

*-

VOO

R3

SI1 6

3~

V[

VSS
-5 V

-)

Po~W2

SOl 7

PIEZO
PEAKER

-=

.r

1~~
C9
0.1

prs E

VOD
N=2

~

®

MC145428

MOTOROLA

Advance Information

Data Set Interface
Asynchronous-To-Synchronous
Synchronous-To-Asynchronous Converter

1

The MC 145428 Data Set Interface provides asynchronous to synchronous and
synchronous to asynchronous data conversion It IS Ideally SUited for vOice/data digital
telsets supplYing an RS-232 compatible data port Into a synchronous transmission link
Other applications Include, data multiplexers, concentrators, data-only SWitching and
PBX-based local area networks This low power CMOS device directly Interfaces with either
the 64 kbps or 8 kbps channel of Motorola's MC145422 and MC145426 Universal Digital
Loop Transceivers (UDLTs), as well as the MC145418 and MC145419 Digital Loop
Transceivers (DLTs)
• PrOVides the Interface Between Asynchronous Data Ports and Synchronous
TransmiSSion Links
• Up to 128 kbps Asynchronous Data Rate Operation
• Up to 2 1 Mbps Synchronous Data Rate Operation
• On-board Bit Rate Clock Generator with Pin Selectable Bit Rates of 300, 1200, 2400,
4800, 9600, 19200 and 38400 bps or an Externally Supplied 16 Times Bit Rate Clock
• Accepts Asynchronous Data Words of Eight or Nine Bits In Length
• False Start Detection PrOVided
• Automatic Sync Insertion and Checking
• Single 5 Volt Power Supply
• Low Power Consumplion of 5 mW Typical
• Applications Notes AN943 and AN946

DCD

OL

DOE
DIE
DC
CM

-------l~

BC
BRCLK . .

RESET
RxD

_-----1

SB

-------l~

RxS

OCI

~..
f---------------------'

flu., dor,lIrlH'nt COllli'1l11<' 111forrn/I of DIE.DC

The rising edge of an
Internal clock formed by
the logical AND of DOE
and DC

The failing edge of an
the logical AND of DIE
and DC

Ie'" of DOE. DC

I

mternal clock formed by

e

~

of DIE. DC

MC145428
TIMING DIAGRAMS

CM~
~~------------------------------------------------I

r---f,1

DOE

--.-J

DIE

--.-J

I

r----f,1
I

DC

HIGH·Z

DCD

DCI

Figure 3A. Synchronous liD, Continuous Bit Rate, Clock Mode Low

DC

DOE

DCD - - - - - {

DIE

DCI

Figure 3B. Synchronous liD, Eight Bit, Clock Mode High

2-351

MC145428

HIGH·Z
~
DCD ----------~f-------------

DC

•

DOE

DCI

DC

DIE

Figure 3C. Synchronous 1/0. Variable Bit Length. Clock Mode Low

CMoHIGH

SAME AS IN CM 0 D MODE
EXCEPT DOE MUST FAll
BEFORE THE RISE OF DC
TO AVOID THE OUTPUT OF
6 BITS

f

DC

DOE

DCD

DIE

DCI

B4

Figure 3D. Synchronous 1/0. Variable Bit Length. Clock Mode High

2-352

MC145428

'5 V

'5 V

I

1

--

VOO

Vss

Voo
ROD

Tx

TOO

Rx

RCE

TEl

LOI

MCI4402 TOE
PCM
CCI
MONO·CIRCUIT
ROC

REI

L02

CLK

LlI---

~
VSS

J--

-5 V

r------

TO LINE
INTERFACE
CIRCUIT

RINGER
CIRCUIT

SOl

TOC
VLS

r----r-----

Vref

~

N

or

~

I

~

MCI45426
SLAVE UOLT

'"

SII

SI2

+

S02

r---

XI
X2

I

4096 MHz

'5V

~

I
' 5V

-

-C

TxO
RxO - + MC 145406
RS·232
TxS - +
DRIVER/
RxS - + RECEIVER
RESET

OCI
DOE
DIE
DC

~

-

4096 MHz

BAUD
RATE
SElECT
SWITCH

-

VOO
OCO

CM
MCI45428

HOOK SWITCH
AND
DIALER

f--I-----

I----I----f---

TRANSMI T DATA
RECEIVE DATA
CLEAR TO SEND
DATA SET READY/
CARRIER DETECT
DATA TER MINAL
READY

BC

-

BRI

-

BR2

SB

BR3

-

DL-

FORMAT
SELECT
SWITCH

VSS

...L

NOTE Some pm connections on the MC145426 and MC14402 have been omitted Consult MC145426 and MC14402 data sheets
for more details

Figure 4. Digital Telset RS-232 Port Using 8 Kilobits/Second Channel of MC145426

2-353

•

MC145428

-5 V

'5 V

--

I

I

ROD

VSS
T,

TOO

R,

RCE

TEl

LDI

TOE
PCM
CCI
MONO· CIRCUIT
ROC

REI

L02

VDD

MC14402

II

VDD

Ur---

CLK

~
-

-POI

TO UNE
INTERFACE
CIRCUIT

RINGER
CIRCUIT

SOl

TOC
VLS

r-------r--r---

Vref

:E

VSS

00
N

~

~

I

&'

MC145426
SLAVE UOlT

'"

• Sil

-5 V

r------

Xl
SI2

t

S02

X2

+
+5V

HOOK SWITCH
AND
DIALER

1 Dr---4096 MHz

I
VDO
T,O

OCO
~ DCI

R,D

ODE

T,S

DIE

R,S

DC
+ 5 V - CM

_
MC 145406
_
RS·232
DRIVER/ _
RECEIVER _

TRANSMI T DATA
RECEIVED ATA
CLEAR TO SEND
DATASET REAOY/
CARRIER DETECT

BC

+5 V

MC145428

:9

VDlCE

-

r-----.

RESET

4096 MHz

_

--

I--

I

--0

PO

BAUD
RATE
SELECT
SWITCH

r--r---

BRI

f---

BR3

SB

-

BR2
DL-

FORMAT
SELECT
SWITCH

VSS

TO TElSET

-b-

POWER
DOWN
CIRCUIT

NOTE Some pin connections on the MC145426 and MC14402 have been omitted Consult MC145426 and MC14402 data sheets
for more details

Figure 5. Digital Telset RS-232 Port Using 64 Kilobits/Second Channel of MC145426 for Voice or Data

2-354

s:
o....
.,::.

-12 V ·5 V

1

1

VOO

VCC

MCI45406
RS-232
DRIVER' RECEIVER

OSlO
·5 V

MC 145428
VOO
CM

RST

r-I-i------------+-t-

iii

-5,0

0;

!:!:
iii
~

z:

«

"c
~

:;
0

>

-45

-55
300

2.4

2
2,2

2,59
2,58

2,62
2,61

FREQUENCY 1kHz)

2·368

3
2,8

4

MC145432
PIN DESCRIPTIONS

BPO, BAND-PASS OUT (PIN 14)
This pin is the output of the 2600 Hz band-pass filter and
can drive a 20 kll load.

VOO, POSITIVE POWER SUPPLY (PIN 18)
Most positive supply.

B +, OP-AMP NONINVERTING INPUT (PIN 17)
This pin is the noninverting input to the uncommitted opamp provided on the circuit.

VSS, NEGATIVE POWER SUPPLY (PIN 9)
Most negative supply.
VAG, ANALOG GROUND (PIN 1)

B - ,OP-AMP INVERTING INPUT (PIN 15)
This pin is the inverting input of the uncommitted op-amp
provided on the circuit.

This pin is a high impedance input which serves as
analog ground reference. This pin is nominally held at
(VDD- VSS)/2.

BO, OP-AMP OUTPUT (PIN 16)

AO, OP-AMP OUT (PIN 2)
A-, OP-AMP IN (PIN 3)
These pins are for the output buffer amp which is capable
of driving 600 Illoads. A - is the inverting input of this amp
while AO IS its output. This amp buffers either the output of
the notch filter or the input signal at Yin depending on the
state of the NE pin.

This pin is the inverting input of the uncommitted op-amp
provided on the circuit.
CS, CLOCK SELECT (PIN 6)
Cl, C2, CLOCK INPUTS (PINS 7 AND 8)
When held at VOD, CS selects the internal crystal
oscillator clock mode. A 3.579645 MHz crystal is connected
between pins Cl and C2. A 10 Mil resistor should be tied
across C1 and C2 along with 20 pF capacitors to VSS to
insure stable oscillator operation. When tied to V S S, a
2.048 M Hz external clock should be applied to C2. When tied
to VAG. a 1.536 MHz external clock should be applied to C2.
In both external clock modes, C1 should be tied to VSS.

Vin, INPUT (PIN 4)
This pin is the input to the notch filter, band-pass filter,
and notch by-pass switch.
NO, NOTCH OUTPUT (PIN 5)
This pin is the output of the notch filter and can drive
20 kllioads.
NE, NOTCH ENABLE (PIN 12)
When high (see VLS pin) the notch filter output is applied
to the line buffer output amp. When held low (see VLS pin)
the input at Yin is applied to this op amp.

VLS, LOGIC SHIFT VOLTAGE (PIN 10)
This pin determines CMOS or TTL level compatibility for
C1, C2, NE and CO. If tied to VOD, CMOS device levels are
expected; if tied to a voltage less than VOD - 4 V, TTL levels
are expected with VLS equal to logic ground.

TO, TONE OUTPUT (PIN 13)
A 2600 Hz sine wave is output at this pin. This pin can
drive a 20 kll load.

CO, CLOCK OUTPUT (PIN 11)
A 128 kHz square wave is available at this pin. This is the
sample clock of both the notch and band-pass filters.

FIGURE 2A - FREQUENCY SELECTION TABLE

Clock
Select
ICS)

Filter
Switching
Frequency
fs
Clock IHzl
--2-8-

Notchl Bandpass
Center
fc
Clock IHzl

Digital Clock Out
ICO)
Is

Clock 1Hz)

fs

Clock 1Hz)
External
787'7
IC1 =V"S
NOTE: SWitching Frequency Ifsl Range = 10 kHz to 256 kHz

Is

VDD
VAG

Clock
Source
Crystal
IC1. C2)
External

IC1 =VSSI
VSS

Clock IHzl
12
Clock 1Hz)
--1-6-

Frenquency

137ll

---goo-

FIGURE 2B - FREQUENCY SELECTION TABLE
Clock
Select
ICSI
VDD
VAG

Clock
Source
Crystal
IC1, C2)
External

Filter
Switching
3.579 MHz

Clock Out
ICOI
127.8 kHz

Tone
Out ITO)
2601 Hz

1536 MHz

128 KHz

26034 Hz

2048 MHz

128 kHz

2599 Hz

Frequency

IC1 =VSS)
VSS

External

IC1 =VSS)

2-369

MC145432
FIGURE 3 - TEST CIRCUIT

Voo
0.1

MC145432

r-----4~-l VAG

18
VOO

AO

B+

A-

BO

Vin

BBPO ~----------<.--o Band-Pass
Output
TO
20 k
NE

NO
VOO
CS
Cl
C2

rf;"

3.579545
MHz

20 pF

T

VOO

VSS

1..--.....-0 2600 Hz Out

VLS
20 k

VSS

20 pF

~

N.C

CO

10M

T

VOO

VSS

Vss

50
For Single
Supply
Applicallons
(All Loads", 20 k)

VAG

50

VSS

FIGURE 4- TYPICAL RESPONSE CURVES
BAND-PASS FREQUENCY RESPONSE

NOTCH FREQUENCY RESPONSE

10

~
-10

\

!,';;:,-20
~ -30

,

~

J -40

-10

I

~
~

\ /

\

-15

I

.E

"'-

-=

,!'

-25

-50

-3~

-60

-35
-40
2.0

2.2

2.4'
2.6
2.8
t, FREQUENCY (kHz)

/

~ -20

\

1.8

7\
\'
/ '\

-5

v

3.0

3.2

/

/

0.5

3.4

2-370

i'-.

"'" r--...

/

r--

V
1.5

2.0
2.5
3.0
t, fREOUENCY (kHz!

3.5

4.0

4.5

®

MC145433

MOTOROLA
Advance Information

CMOS
(LOW-POWER COMPLEMENTARY MOS)

TUNEABLE NOTCH/
BAND-PASS FILTER

TUNABLE NOTCH/ BAND-PASS FILTERS
This device contains a 6-pole filter and 4-pole band-pass filter which
are frequency programable
±5 to ±8 V Supply Operation
Low Power Consumption, 150 mW Typical
Tuneable Notch and Band-pass Filters
On-board Crystal Oscillator or External Clocks
Clock OutpucPin
An Uncommitted Op-Amp Is ProVided, Capable of Driving em!l
Loads
• Notch Filter Output Gain Adjustable
• TTL or CMOS Compatible Inputs
• 16-Pin Package

•
•
•
•
•
•

L SUFFIX
CERAMIC PACKAGE
CASE 620

t.,

BLOCK DIAGRAM

Notch In
6-Pole
Notch Filter

Clock 1
Clock 2

'--_ _~3 AClock Out

~::B+

VLS

BO

Clock 5
Select
Band-pass 11
In

4-Pole
Band-pass Filter

13 B-

12
Band-pass Out

ThiS document contains Information on a new product Specifications and Information herem
are subject to change without notice

2-371
----_.

__

._._--

VDD=PIn16
VSS=Pln 8
VAG=Pln 1

•

MC145433
MAXIMUM RATINGS (Vss=OVI

PIN ASSIGNMENT

Rating

Symbol

Value

Unit

VOO

-05to 18

V

AO

B+

Vin

-05 to VOO+0.5

V

A-

BO

I

10

mA

OC Supply Voltage
Input Voltage, All PinS
DC Current Dram Per Pin

VAG

INot VOO or VSSI

Operating Temperature Range
Storage Temperature Range

TA

-40 to 85

'C

Tstg

-65 to 150

'C

VOO

NI

B-

CS

BPO

Cl

BPI

C2

Co

VSS

VLS

RECOMMENDED OPERATING CONDITIONS

Parameter
DC Supply Voltage

DIGITAL ELECTRICAL CHARACTERISTICS (VSS=O V, VOO= 10 V, TA= -40 to 85'CI

Characteristic
Operating Current (CMOS Model @ 2048 MHz

Symbol

Min

Typ

Max

Unit

100

-

10

18

mA

15

22

-

5.0

75

pF

(TTL Model @ 2.048 MHz
Cin

Input CapacItance

MODE CONTROL LOGIC LEVELS
VLS ITTL Model
VLS ICMOS Model
Clock Select ICSI, VAG = IVOO - VSSI/2

State 1
State 2
State 3

-

VSS

-

VOO-4

V

VIH

VOO-0.5

-

VOO

V

VIH
VIM
VIL

VOO-0.5
VAG-0.5
VSS

-

VDD
VAG+O 5
VSS +0 5

V

~A

TTL LOGIC LEVELS IVLS=O V VSS=O VI
Input Current IC1, C2, CSI

"1" Level
"0" Level

IIH
IlL

-

-

±03
±03

Input Voltage IC1, C2, CSI

"l"Level
"0" Level

VIH
VIL

VLS + 2 0

-

VLS+0.8

"1" Level
"0" Level

VOH
VOL

2.4

-

08

-

±0.3
±03

Output Voltage ICOIIO= 8 mA
10=25 mA

-

-

V
V

CMOS LOGIC LEVELS IVLS=VOO, VSS=O VI
Input Current IC1, C2, CSI
Input Voltage IC1, C2, CSI
Output Current ICOI

"1" Level
"0" Level

IIH
IlL

-

"1" Level
"0" Level

VIH
VIL

7.5

-

5.6
44

30

VOH=9.5V,
VOL =0.5V

10H

-1.3
11

-2.25
2.25

-

2-372

10L

-

-

~A

V
mA

MC145433
ANALOG ELECTRICAL CHARACTERISTICS

IVDD~ 10 V. VAG ~VDD/2. VSS~O V. TA~O to 85'CI

Characteristic

Symbol

Min

Typ

Max

Unit

DC Input Current IV AGI

II

-

-

± 75

~A

DC Input Current INI and BPII

II

-

-

±10

~A

lin

02

01

-

Mil

V,n

VSS + 1 5

-

VDD-15

V

-

-

mA

Unit

AC Input Impedance 11 kHzl INI and BPII
Input Voltage Range INI and BPII
Output Drive Current
IBPOI

VOH~VDD-12V

VOL~VSS+12V

10H
10L

-04
+09

OP AMP PERFORMANCE IVDD~ 10 V. VAG~ VDD/2. VSS~O V. VLS=VDD. TA=O to 85'CI
Characteristic

Symbol

Min

Typ

Max

VIO

-50

-

+50

MV

AOL

-

45

-

dB

liS

-

+01

-

~A

10
11
18

-

90
89
82

10H
10L

-5
+5

-

-

Output NOise IBOI. 900 II

PN

-

-3

-

dBrnC

Slew Rate IBOI

SR

-

2

-

V/~s

Input Offset Voltage IBOI
lL ~ 600 II + 200 pF to VAG

Open Loop Gain IBOI
Input Bias Current (A -, B - . 8 + )

Output Voltage Range IBOI
IRL~20 k[l to VAGI
IRL~900[l
IRL~6ooll

Vo

to VAGI
to VAG)

Output Current IBOI

VOH~VDD-12V
VOL~VSS+

NOTCH FILTER CHARACTERISTICS IVDD= 10 V.

12 V

mA

-

VAG~VDD/2. CS~ VSS~O V. TA=O to 85'C. BPI=VAGI

Characteristics
Input Overload Voltage
Gain 1+2 dBm Into 900 II @ 1 kHzl
Idle NOise. NI ~ VAG. RL ~ 900 [l
Pass-Band Gain. Ref 1 kHz
300 Hz to 2.2 kHz
22kHz to 24kHz
28kHz to 3 kHz
3 kHz t04 kHz

V

Min

Max

Unit

-

70

Vpp

-10

+1.0

dB

-

28

dBrnC

-1.0
-70
-70
-1.0

+1.0
+ 1.0
+ 1.0
+ 1.0

-45

-

-750

+750

mV

-70

-

dB

INote Figure 11

dB

ReJectIon, Ref 1 kHz
2.58 kHz to 2 62 kHz

dB

Output Offset
Dynamic Range IVFSlldle NOlsel

2-373

•

MC145433

BAND-PASS FILTER ELECTRICAL CHARACTERISTICS (VDD= 10 V NI=VAG VAG=VDD/2 VSS=O V. TA=O to 85°CI
Characteristic·
Symbol
Min
Typ
Max
Unit
Full Scale Input Voltage (+ 3 dbmOl
7
VFS
V~

•

Gain (+ 2 dBm into 900 Il @ 2.6 kHz
Idle NOise. BPI=VAG.RL=9001l
Dynamic Range IVFsildie NOlsel
Total Harmonic DistortIOn (0 dbm Into 900 III

Ar

-1

0.0

+1

dB

PN
DR
THD

63
-

-

35

dBrnC
dB

Output offset
Q (- 3db bandwldth/center frequencyl

Q

-500
28

-

-

-

1.0

%

+500

mV

38

-

DIGITAL SWITCHING CHARACTERISTICS (VDD= 10 V VSS =0. VAG = VDD/2 T A=O to 85°CI
Characteristic

Symbol

Min

Typ

Max

Unit

Input Rise and Fall Times
Input Pulse Width (TTL Model

Cl. C2
Cl. C2

tr.tf
tw

-

-

1.5

~s

Clock Frequency (TTL Model
Clock Frequency (CMOS Model

fc
fc
fx

-

2.048
6

Crystal Frequency

Cl. C2
Cl. C2
Cl. C2

ns
MHz
MHz
MHz

Input Pulse Width (CMOS Model

Cl. C2

tw

125

-

-

ns

fs

10

-

256

kHz

SWItching Frequency (Internal)

200

1

NOTCH RESPONSE PARAMETER
+1.0

-1.0

~

"'g'"
>

-7.0

'"
0::

iIi
~

z

«

'"
~a
c

>

-45

-55
24

300
2.2

2.59
2.62
2.61
2.56

FREQUENCY (kHzI

2-374

2.8

4

6

MC145433
PIN DESCRIPTIONS
VDD (PIN 16)
Most positive supply, nominally

With CS tied to V AG, an external clock frequency must be
applied Into Cl and C2 tied together The sWitching frequency fs for the notch and band-pass filters are equal to the external clock frequency divided by 16. When CS IS tied to
VSS, operation IS Identical to that when tied to VAG, except
that the clock IS divided by 1 Instead of 16.

+ 12 V to + 15 V

VSS (PIN 8)
Most negative supply, nominally 0 V
VAG (PIN 1)
Analog ground This pin IS a high Impedance Input which
serves as analog ground reference ThiS pin IS nominally held
at IVDD- VSSl/2
CS, CLOCK SELECT (PIN 5)
ThiS pin controls the configuration of the digital section of
the CirCUit. Three different clock divide configurations can be
obtained by tYing thiS pin to either Von, VAG or VSS.

NI, NOTCH INPUT (PIN 4)
ThiS pin IS the analog Input to the notch filter
AD, OP-AMP OUT (PIN 2), A-, OP-AMP INOUT (PIN 3)
These pins are for the output buffer amp of the notch
filter. A - IS the inverting Input of thiS amp while AO IS ItS
output. ThiS op-amp IS capable of drIVIng a 600 ohm load.

B +, OP-AMP NONINVERTING INPUT (PIN 15)
VLS, LOGIC SHIFT VOLTAGE (PIN 9)
ThiS determines the logiC levels expected .at the digital Input Cl and C2 If tied to Von, CMOS logiC levels are expected, If tied to a voltage less than VOO-4 V, TTL levels
are expected with VLS equal to logiC ground. ThiS pin also
controls the output sWing at Pin CO In a similar manner, Ie,
TTL or CMOS levels.
CO, CLOCK OUT (PIN 10)
This pin IS the digital clock output pin. It IS equal to the
sWitching frequency, fs of the notch and band-pass filters.

ThiS Pin IS the non inverting Input to the uncommitted
op-amp provided on chip
B - , OP-AMP INVERTING INPUT (PIN 13)
ThiS pin IS the Inverting Input to the uncommitted op-amp.

BO, OP-AMP OUTPUT (PIN 14)
ThiS pin IS the output of thiS uncommitted op-amp. ThiS
op-amp is capable of dnvlng a 600 ohm load.

Cl, C2, CLOCK 1, CLOCK 2 (PINS 6 AND 7)
When CS IS tied to Von, a 1 to 4 MHz crystal IS tied to Cl
and C2. The switching frequency, fs, of both filters IS determined by the crystal frequency and IS given by:
f crystal _ f
28
- s

BPO, BAND-PASS OUT (PIN 12)
This IS the output of the band-pass filter.

FUNCTIONAL TRUTH TABLE
Notch I Bandpass
Filter
Center
Switching

Clock
Select
CS

Clock

VOO

Crystal

VAG

External

VSS

External

-.

BPI, BAND-PASS IN (PIN 11)
ThiS IS the Input to the band-pass filter.

NOTE SWitching Frequency Ifs)

Range~

Frequency

Frequency

f.
Clock 1Hz)
28
Clock IHzl
16

fc
Clock 1Hz)
137844
Clock 1Hz)
78769
Clock 1Hz)
49.23

Clock IHzl
10 kHz to 256 kHz

2-375

Digital Clock Out
CO
Is

fs 01 Notch
fs of Notch

MC145433

+5V
Notch
,-;=======:;-i-j-+AnaIOg Out
600

f--+------=---...:5,V re f
6"lClk Sel

:::r

___

,.--_ __.--...--'-17 C1
A

.....--2 8 VI INote 11

-

-

Output Capacitance
All Except Pm 14
Pm 14 IXoutl
Transmit AudiO Signal LevellP,n 1 RL -10 kO INote21
Total Harmonic Distortion 12nd to 14thl INote 21

Cout

.~~. "

-

-

05
06

500
-

mA

-

-

-

mA

-

-

-

13

-

0428

THO

-

05
-50

0578
-40

~·.t

p.A

-50

pF

Vp-p
dB

I
AC ELECTRICAL CHARACTERISTICS IVDD~5 0 V ±5% VSS~O O'C2.8 VI (Note 11

lin

-

Output High Current (VOH - 2.4 VI
Pins 2,8 (Test Load AI
Pins 10, 21 nest Load BI

10H

Output Low Current (VOL =0.4 VI
PinS 2, 8 ITest Load AI
PinS 10, 21 (Test Load BI

10L

Operating Current

IDD
C,n

Input Capacitance
All Except Pm 13
Pin 13 (X,nl

Min

Typ

Max

2.8
40

-

-

-

-

0.5
0.6

-

-

-50
600

0.75
0.75

-

-

-

1.2
06

-

-

-

25

6

-

-

12

8

-

-

-

12

V

V

~A

mA

mA

All Except Pm 14
Pin 14 IXoutl
Transmit Audio Signal Level IPin 1 AL - 10 kll I Note 21
Total HarmOniC Distortion (2nd to 14thl INote 21

rnA

pF

Cout

Output Capacitance

Unit

pF
13

-

-

0428

THD

-

05
-50

0.578
-40

Vp-p
dB

AC ELECTRICAL CHARACTERISTICS IVDD=5.0 V ±5%, VSS=O, TA=O to 70'CI
Symbol

Min

Typ

Max

Unit

Output Alse Time (Test Load AI IPins 2,81

tr

-

20

100

os

Output A,se Time ITest Load BI IP,ns 10, 14, 211

tr

-

20

100

ns

Output Fall Time ITest Load AI (Pins 2, 81

tf

-

20

100

ns

Output Fall Time ITest Load BI IPins 10, 14,21)

tf

-

20

100

-

1000

Characteristics

Input Alse and Fall Times IExcept Pm 131
Delay From

FITS to CTS

Delay From ATS to CTS

STO= Low

tr tf
ld(lowl

STO= High

td(h,ghl

ns

-

1

-

,,5
,,5

18.3

-

217

ms

NOTES:
1. Active pull-up deVices are used on these mputs to allow Interfacmg to TTL deVices. The lin specified IS a transitional load (not steady state)
which IS drawn when the Input IS brought up to 2.8 V until the Internal pull-up deVice has raised the signal to the VDD level
2. Measured

10

any mode using HP-3555B dB meter (or equlvalentl with 3 kHz flat fllte"ng

2-396

MC145450

PIN DESCRIPTIONS
VDD, POSITIVE POWER SUPPLY (PIN 221
This IS nominally 5.0 V.
VSS, NEGATIVE POWER SUPPLY (PIN 12)
This IS usually a volts.
Tx Car, TRANSMIT CARRIER (PIN 1)
The transmit carner output IS a 16 step digltallysyntheSIZed sine wave with an amplitude of 0.1 VDD Ip-pl
I ± 10%1 and offset by a dc bias of 0.5 VDD I ± 10%1. The
output load should be 10 kllohms or greater
CTS, CLEAR TO SEND (PIN 2)
The clear to send output goes low In response to a highto-low translation of RTS following a selected delay Isee
CTA, CTB, CTC pin descrlplJOni. This output goes high Immediately after loss of RTS. DUring the time follOWing activation of RTS and before the actIVation of CTS, Tx Data
should be held in the mark condition.
CTA, CLEAR TO SEND SELECT A (PIN 5)
CTB, CLEAR TO SEND SELECT B (PIN 4)
CTC, CLEAR TO SEND SELECT C (PIN 3)
For delay times for clear to send delay select Inputs, see
Table 1
RTS, REQUEST TO SEND (PIN 6)
The request to send Input controls data transmission from
the modulator. A low level enables the modulator output and
a high level Will disable the modulator. See Figure 1.
STO, SOFT TURN OFF INPUT (PIN 7)
Activation of STO causes a 900 Hz tone to be transmitted
and CTS to remain active for 20 ms following the loss of
RTS. See Figure 5
Rx Data, RECEIVE DATA (PIN 8)
The receive data output IS the serial data output from the
demodulator. Rx Data is clamped high when CD is not active.
CD, CARRIER DETECT (PIN 9)
When carner detect Input IS high Ill, the Rx Data output
will be clamped to a high state. When carner detect IS low
101, Rx Data output demodulates the Rx carner input signal.
DMO, DEMODULATOR OUTPUT (PIN 10)
The demodulator output IS the output of the differential
delay detector. It is used for production testing of the
demodulator. In normal operation, this Pin should be left
open.
Rx Car, RECEIVER CARRIER (PIN 11)

Xin, OSCILLATIOR INPUT (PIN 13)
Xout, OSCILLATOR OUTPUT (PIN 14)
X,n should be dnven from either an AT-cut crystal or a
digital Signal source at 3.6864 MHz ± 0.01 %. When dnven
by a crystal, a 15 megohm reslsltor should be connected
from X,n to Xout in parallel with the crystal.
MODE (PIN 15)
The mode pin selects the pair of frequencies used dunng
modulation and demodulation A "0" on thiS pin selects forward channel operation, I e. high-speed transmit and lowspeed receive A "1" on thiS Pin selects reverse channel
operation, I.e low-speed transmit and high-speed receive
ST, SELF TEST (PIN 16)
When a high level IS placed on thiS Pin, the demodulator IS
switched to the modulator frequencies and baud rate las
determined by Mode and Type Plnsi. The modulator should
be looped back through the receive filter to the demodulator
for self test lecho backl.
N.C. NO CONNECTION (PIN 17)
ThiS pin IS not bonded Internally and should be left open In
normal operation.
TYPE (PIN 181
This pin IS used to select Bell 202 type operation and
CCITT V 23 operation. When the type Input pin IS a "1", Bell
operation IS selected When the type Input pin IS a "0", the
CCITT standard is selected.
An Bk, ANSWER BACK (PIN 19)
The answer back Input causes the answer back tone to be
transmitted. The answer back tone IS 2025 Hz for the Bell
mode and 2100 Hz for the CCITT modes. When a high level
IS placed on the An Bk Input pin, the Tx Car pin Will output
an answer back tone and CTS will go to a high state, regardless of the state of RTS Isee Figure 11
Tx Data, TRANSMIT DATA (PIN 20)
The transmit data Input is the serial Input to the
modulator. A high level causes a mark frequency to be
transmitted, a low level causes a space frequency to be
transmitted.
Tx Test, TRANSMIT TEST (PIN 21)
The transmit test output is a square wave representation
of the modulator transmit frequency. It is used for test purposes and should be left open in normal operation.

The receiver carner input IS the FSK input to the
demodulator. This signal should be the hard-limited output
of the receive filter, nominally 50%.

2-397

•

MC145450
RTS-CiS TIMING

FIGURE 1 - An Bk AND

An Bk

•

ATS

CTS
No Signal
Tx Car

TABLE 1 - RTS-CTS DELAY TIMES
Delay'

CTC

CTB

CTA

0

0

0

Oms

(')

0

1

26.7 ms

0

1

0

40.0 ms

0

1

1

60.0 ms

1

0

0

133.3 ms

1

0

1

213.3 ms

1

1

0

266 7 ms

1

1

1

426.6 ms

• All delays are ± 1.7 ms

TABLE 2 - OPERATING MODES

Transmit
Type
0

0

1

Mode

Spec

Actual

0

2100

209932

1

1300

1299 86

0

450

450'

0

1
1

390

3905

0

2200

2199 52

0

Answer
Back
Tone

Application

2100

CCITT V 23 75 Baud Receive
1200 Baud Transmit
Forward Channel

2100

CCITT V 23 1200 Baud Aecelve
75 Baud Transmit
Reverse Channel
US.

150 Baud Receive
1200 Baud Transmit I Bell 202)
Forward Channel

U.S

1200 Baud Receive IBell 202)
150 Baud Transmit

2025
1
'0

1

Frequency

Transmit
Data

1200

1200

510

509 73

1

390
1

390

390 5

Reverse Channel

* Crystal Frequency = 3 6864 MHz

Dala=O= Space
= 1 = Mark

2-398

MC145450

FIGURE 2 -

STO TIMING

II

STO

td .-

~

~ tRTS-CTS"
_tSTO

~
Data

Tx Car

No Signal

Data

Data

FIGURE 3 - OUTPUT TEST LOAD A

1-

f

VCC

I
C

I

_I
I

I

MMD6t50
or Equlv

VI

RL
32 kO
±1%

1-

,

I
Rl~31kO

±1%

or Equlv

L:'mulat~r~o~

Vee

C

I

RL
32 kO
±1%

L:'mulat~T~o~

Termmal

Receiver

Tx Data

I
I

Modulator

I

I
I
I
Rx Data I
I

I

MC145450

probe,

-

WIfing,

and load capacitances

I Tx Car

Telephone

Ouplexer

I

t

I
I
I

--

Data Flow

-,

FSK
Format

I
Demodulator

___

i
I
I
I
I
I

.-J

CT == 20 pF == total paraslttc capacitance, which Includes

FIGURE 5 - TYPICAL MEDIUM-SPEED MODEM APPLICATION

Terminal
Transmitter

MMD7000
or EqUlv

I

Transmit Data

----

±1%

_I
I

CT = 20 pF == total parasitic capacitance, which Includes
probe, wiring, and load capacitances

r

Rl~619kO

MMD6150
or Equlv

VI

1

Parallel Format

-l

I

I
I
I

I
_ _ _ .-J

I

----

I

1

MMD7000

No Signal

FIGURE 4 - OUTPUT TEST LOAD B

-- ---l

I

900 Hz

Data

Rx Car

I
I

L - - - --~
Receive Data

Parallel Format

2-399

Bandpass
Filter
and Limiter

Network

II
s::
o....

..
en

FIGURE 6 -

10k

g

TYPICAL 1200 BAUD 4 WIRE MODEM APPLICATION

:>---;lLI_ _ _ _ _ _ _ _ _ _,

Transmit ••----+--------,
VCC

llTx Car

~

CTC

4 CTB
5 CTA

6 RTS
STO
ST16
8 Rx Data MOOG
9 CD
X,n~3
11IRxCar
VssJi2"

Receive

Tx Level
Adjust

Tx Data
An BK Ii9
Typefls

r---------600

I

l"IC

0.1

~

22k

'"TIlle

MCl45450

~
I

"'"

()

()

3k

5 Volts

)0

I

•

------,

VCC

L ______ _

001

10
GrOund,

To Carner
Detect

I OptIOn)
MC54174HC163
1 Reset
VCc116J
_ _+-_1---,2o.jClock
RlppleJi51
3 PO
Carry
4 PI
Out
5 P2

6 P3

VCC

Io2l

7 Enable P Enable T
8 GND
Load ~_ _ _...J

-=

1536kHz Clock Generator I -;- 24)

t":~
MC54174HC04

Line Interface

IInternali

Application Notes and
Technical Articles
Subject

Page

SWITCHING
Understanding Telephone Key Systems IAN8931
Telephone Quality CVSD Codecs USing New Bipolar Llnear/lh IC
Time-Slot Assigner Chip Cuts Multiplexer Parts Count
MCl4402 Mono-CircUit Applications Information IAN-8721
Telecom Ie's Create Low-Cost Phone Links 4 Miles Long

3-3
3-10
3-16
3-17
3-22

VOICE/DATA
CMOS LSI Integration Enhances Voice and Data Networks
UDL T Evaluation Board IAN9431
Interfacing the MC145418 and MC145419 IAN9451

3-24
3-32
3-42

SUBSCRIBER
LSI for Telecommunications: a One Chip Telephone Set
Interfacing the Speakerphone to the MC34010/11113 Speech Networks IAN9571
Transmit Gain Adjustments for the MC34014 Speech Network IAN9581
A Speakerphone with Receive Idle Mode IAN9591
Equalization of DTMF Signals Using the MC34014 IAN9601
The Application of a Telephone Tone Ringer as a Ring Detector IEBl121
The MC145409 Pulse Dialer Application Circuit IEBl131

3-44

3-48
3-60
3-62
3-64
3-66
3-67

MODEM
Low-Speed Modem Fundamentals IAN-7311 .
Low-Speed Modem System Using the MC6860 IAN-7471
Application Performance of the MC6860 Modem IEB-491
MCl4412/MC145440 Chip Set Sets New Standard in 300 Baud Modem DeSigns IAN-8911
2400 bps DPSK Modem System Using the MC6172/6173 IAN-8701
A Four-Wire Full Duplex 1200 Baud Modem Implementation USing the MC145450
and the MC145415 IAN9041
Limited Distance Modem IAN9461
Data MultipleXing IAN9481
The Application of a Duplexer I EB 1111

3-125
3-129
3-139
3-149

FILTER
Adjustable Clock Tunes Notch Filter.
The MC145432 Application Circuit IEB-981
Digitally Control Filer Gain, Cutoff
One IC Conditions Signals
IC Trio Simplifies Speech SyntheSIS
Turn I/O Data Port Into Speech Port

3-151
3-152
3-155
3-156
3-157
3-161

3-1

3-69
3-83
3-98
3-102
3-112

•

•

3-2

®

AN893
Application Note

MOTOROLA

UNDERSTANDING
TELEPHONE
KEY SYSTEMS
Prepared By:
Steve Bramblett
Telecom Applications
Austin, Texas

INTRODUCTION
This application note is intended to give an understanding
of key systems and how they differ. A theoretical architecture based loosely on many of the 16 station key systems now
in existence will be presented. Possible variations and the impact on overall design will also be discussed.

IA2 system, or there must be a way to program the
telephone's "profile" into the CPU so it can control the station accesses. This presents real problems as there must be
some input and display device associated with the CPU plus
some form of non-volatile data storage. This storage can be
anything as simple as several dip switches, or as complicated
as an intelligent controller that hooks into the system with a
CRT terminal and programs several EEPROMs.

WHAT IS A KEY SYSTEM?
A key system is a telephone system that can be used behind
a PBX or central office. Generally, key systems are designed
to support as many as 100 telephones, and provide service to
these phones with up to 50 percent trunking (a trunk may be
either a PBX or central office line connecting the key system
to the rest of the world). The telephone set has several push
buttons that are not generally found on a K500-type desk set.
These push buttons allow direct access to several trunks,
intercom lines and system features such as hold and do-notdisturb. The major difference between a key system and a
PBX is that a key system allows the user full control over individual trunks, while a PBX assigns whatever trunk is
available when requested (usually this is done by dialing a
"9").

WHAT IS A tA2 SYSTEM?
The 1A2 key system is an older system that relied on
electro-mechanical devices to accomplish the tasks now
replaced by modern integrated circuit technology. These
systems generally included several pairs of tip and ring
signals which led to each station, where complicated
mechanical switches selected the desired pair. The connections to the outside world were metallic, and therefore were
of the non-protected variety. The biggest expense was cabling
and installation labor, because the system required a 25-pair
cable for each phone.
WHAT IS MEANT BY "PROTECTION"?
A protected key system is designed in such a way to prevent stressful voltages reaching the trunk under any circumstances. Generally, this is accomplished by transformer
coupling the trunk to the system at the interface and adding
overvoltage protection. This will prevent any accidents from
causing problems with the trunk, such as 110 Vac getting to
the trunk from an improperly installed telephone. When a
key system is not protected, it must be installed by a
registered agent of the manufacturing company. Both
distributor and manufacturer are burdened by expensive
agency agreements if a system is not protected.

HOW DOES "SQUARENESS" AFFECT THE SIZE?
There are two basic architectural types of key systems, one
known as a "square" system, and the other a "non-square"

system. In a square system, every subset has control over
every trunk so there can be no special reserved lines. Some
designs go one step further by forcing a button appearance
for each station. The most obvious size limiting factor in a
square system is the number of buttons on the phone. In a
non-square system, each phone is provided with a subset of
the available trunks. While this makes the non-square system
design appear more attractive, one must understand the complexity involved. In a square system, only one set of tip and
ring wire pair must be routed to the phone, and since each
phone looks identical, bookkeeping by the CPU is held to a
minimum. In a non-square system there must either be a
separate voice pair for each trunk and intercom link, as in

KEY SYSTEM ARCHITECTURE
A l6-station square system with protection is outlined in
Figure I. The trunk interfaces provide the necessary protection to pass the FCC requirements, plus the circuitry to condition the voice and signaling information to make them

3-3

•

AN893

Central
Office

Lines.

•

,r--"

Call
Progress
Tones

Trunk
Interfaces

Station

Subscriber
Apparatus

Apparatus

CPU

Interfaces

FIGURE 1 - Key SyStem Unit

easier for the system to handle. The voice information is
passed to a voice matrix, where the information can be
routed to the proper destinations, and the signaling goes to
the CPU to indicate what is happening at the interface. The
station apparatus interfaces provide the voice and data interfaces to the phones. The progress tones are for internal
supervisory signaling within the switch. The CPU is charged
with the supervisory and monitoring tasks for all other parts
of the system.
A much more detailed look at the voice matrix is provided
in Figure 2. The voice matrix is an analog crosspoint variety
which may be composed of relays or CMOS switches. Relays
are a good voice switch medium for systems with eight or less
stations, but the newer crosspoint lCs, such as the MC142100
and MCI4210l, are much more cost effective. There is some
loss associated with the switches (about 100 ohms) that does
not occur in the relays. In our example we will consider a
4 x 4 x 2 crosspoint and the dotted lines outlining the three
chips needed for the matrix. The music-on-hold (MOH)
music and the tones are separated to help alleviate crosstalk
within the switch structure. The design includes the ability to
handle 3 trunks and I internal conversion. This appears to be
a standard that was implemented through the years. Most
systems allow expansion to either 2 more trunks or a trunk
and an intercom link by adding to the matrix. Bridging more
than one trunk or station can be easily accomplished by setting multiple contact points.
The loss the switch introduces into the system is the major
drawback to using the CMOS crosspoint switch. The FCC requires that the electrical-ta-acousticalloss of the system from
the trunk to the station must not exceed 2.5 dB. A look at
Figure 3A shows that a typical trunk-ta-station loop has loss
in two areas. The two crosspoint switches represent a typical
200 ohm resistance when they are in an on state which creates
about 2.5 dB of loss in a 600 ohm system. Each transformer
also introduces some loss so the electrical-to-electrical loss
exceeds 2.5 dB. Changing the internal resistance of the loop

minimizes the switch resistance but the transformer efficiency is greatly decreased so no advantage is found here. The
loop could be amplified, but this is costly and leads to
unstable circuitry so the phone must be designed to operate
on different levels from a standard phone. The FCC allows
another 2.5 dB of loss for a station-to-station talk path as
shown in Figure 3B so the extra switches in the loop are not
a problem .
. Figure 4A is a block diagram of the trunk circuit. When
the trunk is idle, the tip and ring are bridged by the loop relay
across the ring detect circuit. This circuit signals the CPU
when a call is ringing in from the central office or PBX.
When the trunk is accessed by the system the loop relay connects tip and ring to the transformer. The protect circuit
helps prevent surge and static damage. The battery reversal
detector is an optional circuit that alerts the CPU when the
tip and ring polarity has been reversed. This usually happens
momentarily when a central office toU circuit has been accessed, so this is for toU restriction. The loop detect circuit is
needed to indicate when the connection has been terminated
by the outside caller. This prevents the hold function from
locking up a trunk. If pulse dialing is to be provided a relay
circuit similar to the one in Figure 4B must be added to the
loop. The CPU must read the pulses from the station and
transfer them to the trunk. Another possible optional circuit
is a ground loop detector. This is needed to detect grounds
on a groundstart trunk. These trunks use a ground to start
where loopstart trunks (the most common kind) use loop
continuity to start.
The station interface in Figure 5 is a four-wire design. The
first pair (tip and ring) are used to provide voice communications while the second pair (D + and D - ) provide data communications. The two resistors in the voice circuit provide a
current limiting function to prevent catastrophic system
failures should tip and ring get shorted together. The protect
circuit functions in a manner similar to the trunk protect circuit and the loop detect is used to detect the making and

3-4

AN893

r-----, r-----, r-----, r-----,
COl

I

.1

C02

I

:1

C03 I

.r

Intercom

Stations

,I

I

~

L

-

2

3

4

.1

I•

I

I

f- -

I

,I

-

5

-

I- -

6

7

f...r

8

L

.1

,I

I

:1

,I

I

9

A

.1

- f-J L -

-I-

B

I~I

I.

r.

I

L

-

,I

I

C

D

f- -

- ~

10

MOH

TONE

FIGURE 2 - Voice Matrix

may be uncomfortable, so they must not reach the user,
therefore some feedback must be generated to indicate dialing has taken place.

breaking of the loop to pass pulse dialing signaling to the
trunk. The resistors in the data interface do the same job in
the voice circuit as does the protect circuit. The differential
mode transmitter and receiver provide a serial data stream interface for the data communications. The data is generally in
a half-duplex ping-pong arrangement, where the outgoing
data tells the station which lamps should be on, whether the
ringer is to ring, and whether the call announcer should be
energized. The incoming data gives the status of the phone's
hookswitch and the buttons on the keypad.
Another name for the station apparatus is the keyphone or
the subset. Figure 6 is a block diagram of the subset. Tip and
ring come into the subset through the hookswitch. When the
handset is on-hook, the tip and ring are directed to the
handsfree/call announcer circuit. This circuit is similar to a
speakerphone circuit. When the handset is removed from its
cradle, the tip and ring is routed to the speech network for
normal telephone operation. Each voice network is powered
by the battery voltage on tip and ring. The data circuit is
powered by its own battery feed to help prevent crosstalk between voice and data. The data is brought into the control
logic to activate the lamps, ringer, and in some cases, the
handsfreel call announcer.
There are several variations on the voice and data links to
the subset. Some systems impress the data, which generally
has a rate well above the voice channel, onto the tip and ring
for a single pair run. Extra filtering is needed to separate
voice and data. Another variation connects tip and ring to
the speech network causing the handsfree/call announcer to
receive voice over the same wire pair as the data. This allows
"off-hook call announcing" where the user can be paged via
the call announcer while off-hook talking. Generally the output level of the call announcer is greatly attenuated when the
handset is not in the cradle.
Another interesting variation to the architecture deals with
how the dialing is controlled by the system. In this arrangement all DTMF tones or dial pulses originate at the subset
and are passed through the system as though it is transparent. This is known as end-to-end signaling. An alternative
is to place the pulse or tone dialer on the trunk interface and
read the dial by the control logic so the dialing information is
passed through the CPU to be interpreted at the trunk. The
major drawback here is that there must be extra circuitry in
the subset to produce aural feedback. In a normal phone the
DTMF encoder mutes the speech network. Since the encoder
is not here the mute is lost. The levels needed at the trunk

Adaptation of this system into a non-square system requires several major system modifications. Since a nonsquare system allows only a portion of the trunks and
available features to be represented as buttons on the subset,
some scheme of accessing other non-appearing trunks and
features must be employed. This is usually done by dial access. In a dial access system, every subset must have a dial intercom button. When this button is accessed the system must
provide a dial tone and a dialing register. The dialing register
must be capable of counting dial pulses and decoding DTMF
data. Since DTMF decoders alone are in the $20-$30 price
range the number of registers are generally restricted. This
can cause bottlenecking problems when there is a need for
more dial accesses than the number of registers available.
There is generally a tone associated with this overload (the
overload is called blocking) that indicates to the user that all
circuits are busy. If all intercom links are busy when access is
needed, then blocking also occurs. Now that the buttons
must have some flexible assigrunents a data base of the subset
"profiles" must be retained by the CPU. In addition to this
data base duty, new software overheads are necessary for the
CPU to allow dial and button accesses, as well as the addition of new, extended features such as dial intercom that are
generally included in the non-square system.
There are several alternatives in operation during a power
failure. One solution is called powerfail cutthrough. In this
scheme certain trunks are metalically connected to certain
phones. Our subset design does not support this arrangement
since ringing would be impossible and the call announcer
would be bridged across tip and ring when the subset is
on-hook. The system can be designed so that ringing occurs
in a normal manner, but a ringing generator is necessary. The
ringing generator is a specialized ac power source. An alternative is battery back-up, and since most systems have a
master power supply of 24-48 Vdc, this can be easily accomplished. The major advantage to this that no calls are
lost on the power loss as in cut-through, and unless a
sophisticated cut-through system is employed, calls are lost
on the return to power which again is not a problem in a battery backed-up system. The system must be a low-power
design or the battery back-up system may become prohibitively expensive.

3-5

•

AN893

"'J

~

..,
..L

~

Ring,

.. Tip

::x::
::x::

~ Talk

Battery

~Gnd

.. Ring

FIGURE 3A - Trunk-to-Station Loop

~~---------.~TiP

Tip .....---------,~

•

Talk Battery.............,.....--::x::-r--J-

'-::r::-r---'~ Talk

Gnd~--=r=~~~

F_y-'-_--Jo~Gnd

Battery

'----------~.Ring

Ring'..... - - - - - - - - - ' -

T

T

FIGURE 38 - Station-to-Station Loop

r----l.-Tip
Tip_--+----_......
Loop
Detect

To
Central
Office

To
Matnx

R,ng"--">---+---""'-

1
V ......---'1....,

~'--

:....

To
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.: . CPU

FIGURE 4A - Trunk Interface (Without Pulse Dialing)

To
Hookswitch ..
Relay

~ I-I-+.-------I•.-To Transformer

~
1
V .....1------.:1...,

:~3------_..~TOCPU

FIGURE 48 -

Pulse Dialer

3-6

AN893

TIp

TIp

Talk
Battery

To

Matrix
Ground
Ring

Ring

To
Station

TO{
CPU

0-

..VDD
Ground

0+

FIGURE 5 - Station Interface (Without Ring Generator)

TIp

Hookswltch
Speaker

Ring

Handsfreel Call
Announcer
Microphone

D-~--------------~

D+~~-+--------------~

FIGURE 6 - Subset

3-7

AN893

GLOSSARY OF KEY SYSTEM FEATURES

•

All Call - This is where all of the call announcers are
energized in the system for a general announcement. This is
similar to a page except the call announcers are used instead
of auxiliary amps and speakers.

Do Not Disturb - When this feature is activated at a subset,
no incoming calls will ring the subset, however, the phone
can still be used for outgoing calls. The subset will not
acknowledge the call announcer either.

Background Music - This is a feature that requires an external music source. The music is routed to all of the call announcers so that, if desired, the call announcer can provide
music when the subset is idle.

Direct Station Select - This allows one subset to establish an
intercom call with a second subset by using a dedicated button as opposed to a dial code. This is a very popular feature
in small square systems and is generally referred to as DSS.

Busy Lamp Field - This is an array of lamps or LEOs that
indicate when each station in the system is busy or idle. This
is usually abbreviated as BLF.

Exclusion-Privacy - When active, this feature prevents
other subsets from barging in on your call.

Call Announce - This function is performed instead of ringing. When an individual phone is call announced, the call announce circuitry is energized. A warning tone is then sent to
both parties and then the parties are connected as in a conversation. The called party can talk over the call announcer
as if it were a speakerphone.
Call Forward-Busy - An incoming call is routed to a secondary subset when first subset is busy.
Call Forward-Follow Me - An incoming call to one subset is
routed directly to another subset.

Executive Override-Barge In - Barge in is a feature that
allows one to enter an already active conversation so that a
conference is created. Executive override is the same feature
applied to special phones to overcome an exclusive call (see
Exclusion).
Handsfree - In an apparatus sense, this is known as
speakerphone operation. In essence, a conversation is held
over the subset's speaker and microphone while the handset
is in the cradle. This frees the hands for other uses and
several people can participate in the conversation at the
handsfree end.

Call Forward-No Answer - If a call is not answered in a
specified period of time, the call is rerouted to a second
subset.

Music-On-Hold - This is a feature that requires an outside
music source that mayor may not be the same source used in
background music. When someone is parked or put on hold
they are provided with music instead of silence.

Call Park - This feature is only used in non-square systems.
When a call comes in it can be "parked," then any subset
can pick the call up by accessing the parked call. This allows
the subsets to pick up calls on non-appearing trunks.

Page - This feature is similar to All Call except the general
announcements are made over a user-supplied public address
system instead of call announcers. This is especially useful in
warehouse situations.

Call Progress Monitor - This is a device that allows the
monitoring of the calling function prior to completing' the
connection. All dial tones, dialing tones and ring back tones
are heard over an auxiliary speaker as it would sound over a
handset. This is a simplex device so no conversation can be
held.

Recall - The recall feature is designed to prevent excessively
long holds and call parks. When a call has exceeded the recall
timeout while on hold or parked, it will ring the subset that
either put it there or an attendant station.

Camp On-Auto Call Back - When a called station is busy,
the caller can camp on to that station so that when the subset
becomes idle, it will ring. If the caller hangs up prior to the
subset becoming idle, the caller's subset will ring and after he
answers, the other subset will ring. The second case is known
as auto call back and is an extension of the first case being
camp on.
Conference - A conference is a call that has more than two
parties involved in the call at one time.
Dial Intercom - A dial intercom is an intercom that when
accessed allows the user to access other subsets, trunks and
features with dial codes. This is only found in systems where
there is not an access button for each subset.

Remote Answer - This feature exists only on non-square
systems. When an incoming call rings a subset, it can be
answered at another subset that does not have that particular
line by invoking the remote answer feature.
Repertory Dial - This feature can be associated with either
the subset or the system. This is where several commonly
called phone numbers are internally stored and can be
automatically dialed when accessed. This is also known as
speed or abbreviated dialing.
Secretarial Intercom - This is a special case DSS where the
called subset rings only while the access button is depressed.
This allows private ring codes to be used between subsets to
alert the users to special conditions.

3-8

AN893

Station Hunting - Station huming is an advanced feature
found usually on large, complex system. This feature allows
groups of subsets to be "hunted". When a call is placed to
this group, the first phone rings for a preset period of time,
and if there is no answer, the second phone in the group
rings. This will progress through all the subsets and the call
can be answered at any subset at any time.

Toll Restriction - This feature prevents unauthorized
subsets from making toll calls.
Transfer - This feature is needed only in non-square
systems and it allows a call to be moved to a subset that does
not have a button appearance for that call.

Tie Trunks - A tie trunk is used to link systems together.
Generally the two systems are remotely located and can even
be in different cities. The tie trunk does not rely on central
office intervention.

3-9

®

MOTOROLA

TELEPHONE QUALITY CVSD CODECS
USING NEW BIPOLAR LINEAR/12L I.C.
Stephen H. Kelley
and
John J. Price

•

INTRODUCTION
Principles of continuously variable slope delta modulation
for communications systems are discussed including an
S plane model for a simple delta modulator with adjustable
gain. A new bipolar I2L circuit for implementing CVSD
systems is presented. System performance and design techniques for a basic voice band codec and a telephone quality
codec are included. Double integration and active companding ratio control techniques for improving codec performance is discussed. The emphasis is on a practical, mass
producible telephone codec.
The continuously variable slope delta modulator (CVSD)
is a simple alternative to more complex conversion schemes
in systems requiring digital communication of analog signals.
Voice and audio communications are analog, but digital
transmission of any signal over great distance is more attractive. SIN ratios of the recovered signal do not vary with
distance when using digital transmission; and multiplexing,
switching, and repeating hardware is more economical and
easier to design. However, instrumentation A to D converters do not easily meet the bandwidth constraints of communications requirements. The CVSD A to D is well suited
to the requirements of digital communications and is an
economical, efficient means of digitizing analog inputs for
digital transmission.

THE DELTA MODULATOR
The innermost cOlitrolloop of a CVSD converter is a simple delta modulator. That portion of the CVSD is shown in
Figure I. A delta modulator consists of a comparator in the
forward path and an integrator in the feedback path of a simple control loop. The inputs to the comparator are the input
analog signal and the integrator output. The comparator output reflects the sign of the difference between the input
voltage and the integrator output. That sign bit is the digital
output and controls the direction of ramp in the integrator.
The comparator is clocked so as to produce a synchronous
and band limited digital bit stream.
If the clocked serial bit stream is transmitted to a similar
integrator at a remote point, the remote integrator output is a
copy of the transmitting control loop integrator output. To

the extent that the integrator at the transmitting location
tracks the input signal, the remote receiver reconstructs the
input signal. Low pass filtering at the receiver output will
eliminate most of the quantizing noise if the clock rate of a
the bit stream is an octave or more above the bandwidth of
the input signal. Voice bandwidth is 4 kHz and clock rates of
8 kHz and up are possible. Thus, the delta modulator
digitizes and transmits the analog input to a remote receiver.
The serial, unframed nature of the data is ideal for communications networks. With no input at the transmitter, a
continuous one zero alternation is transmitted. If the two
integrators are made leaky, then during any loss of contact
the receiver output decays to zero and receive restart begins

ANALOG
INPUT

,>-_.-.::DI:::G:;;;:'T41..
.."

f

D'G~TAl
RECONSTRUCTED
ANALOG

----

OUTPUT

INPUT

OUTPUT
DECODER

FIGURE 1 - SIMPLE DELTA MODULATION
An Analog Input Signal Can Ba Digitalized and Transmitted by
Synthesizing a Minimum Error Set of Vo~age Ramps.
The Comparator Clock Establishes the Channal Bandwidth.

without framing when the receiver reacquires. Similarly, a
delta modulator is tolerant of sporatic bit errors.

3-10

The fundamental advantages of the delta modulator are its
simplicity and the serial format of its output. Its limitations
are its ability to accurately convert the input within a limited
digital bit rate. The analog input must be frequency limited
and amplitude limited. The frequency limitations are governed by the Nyquist rate while the amplitude capabilities are
set by the gain of the integrator. For a given signal level, one
specific gain will achieve an optimum noise level. Unfortunately, the basic delta modulator has a small dynamic
range over which the noise level is constant.

stantaneous information about the shape of the input curve.
The purpose of the algorithm is to control the gain of the
integrator and to increase the dynamic range. Thus, a
measure of the average input level is needed. By monitoring
both the coincidence of ones and zeros, the shift register performs a function similar to a full wave bridge rectifier.
The algorithm is repeated in the receiver and thus the level
data is recoverable at the receiver. Because the algorithm
only operates on the past serial data, it changes the nature of
the bit stream without changing the channel bit rate. The bit
stream in the channel is as if it were from a standard delta
modulator with a constant level input.

THE COMPANDING ALGORITHM
The continuously variable slope circuitry provides increased dynamic range by adjusting the gain of the
integrator. For a given clock frequency and input bandwidth,
the additional circuitry increases the delta modulator's
dynamic range. A block diagram of a complete CVSD codec
is shown in Figure 2. A new bipolar /12L integrated circuit
has been built to provide all of the active elements. External
to the basic delta modulator is an algorithm which monitors
the past few outputs of the delta modulator in a simple shift
register. The register is 3 or 4 bits long depending on the application. The CVSD algorithm simply monitors the contents
of shift register and indicates if it contains all ones or zeros.
This condition is called a coincidence. When it occurs, it indicates that the gain of the integrator is too small. The coincidence output drives a low pass filter. The voltage output of
this syllabic filter controls the integrator gain through a V to
I converter and a slope polarity switch whose other input is
the sign bit or the up/down control of the delta modulator.

SYLLABIC AND INTEGRATION FILTER PROPERTIES
The circuit in Figure 3 is the most basic CVSD circuit
possible. For many intelligible voice channel applications, it
is adequate. In this circuit, both the syllabic filter and the
integration filter are composed of single-pole networks.
The integration network is chosen to meet two simple constraints. First, it must be an integrator throughout the voice
band and second, it must be leaky so that bit errors can be
tolerated and loss of receiver contact does not require an external reset for reacquisition. C15.1 JLF and RI = 10 k produce
a 159 Hz break/frequency and a lossy network.
The selection of the syllabic filter components illustrates
an interesting property of the codec. The operation of the
simple delta modulator may be investigated by deriving its S
plane transfer function. The comparator is modeled with a
unit limiter and a summer. The unit limiter has a describing
function in S if the system is analyzed for sinusoidal inputs of
the form e sin wt, that is

Digital Output = ~ e sin wt where A is the peak voltage of
..e
the unit limiter.
It is obviously a non-linear element since the transfer function is dependent on the magnitude of the input signal.
The integration filter has a straightforward transfer function description:

AnalogVout
Digital Vout

Rx

where Rx is connected from the comparator output to the integrator input and sets the gain of the simple delta
modulator.
The closed loop delta modulator model is then
FIGURE 2 - CVSD BLOCK DIAGRAM
A Delta Modulator Is Enclosed in a Digitally Controlled Gain Loop
and Composes a Continuously Variable Slope Delta Modulator.
A Bipolar /l 2 L Integrated Circuit Has Been Designed to Provide
All the Active Circuitry Required.

Analog Vout
e sin wt

1+

4ARx
e CI (S + IIRICil

Note that the response of the codec is a function of the
magnitude of the input level. Closed loop CVSD systems can
be analyzed for steady state inputs by substituting the
syllabic filter voltage which corresponds to an applied e for
A. Thus, the gain of the delta modulator is varied to accommodate the applied input level.

The simplicity of the all ones, all zeros algorithm should
not be taken lightly. Many other control algorithms using the
shift register have been tried. The key to the accepted
algorithm is that it provides a measure of the average power
or level of the input signal. Other schemes provide more in-

3-11

11= ~ + CIdVo
RI
dt

For a CVSD circuit to perform' as an adjusted delta
modulator, the model equation indicates that A oc e must be
nearly constant. The syllabic filter time constant must be
large compared to the input frequency. For a maximum input frequency of 3300 Hz, the time constant must be much
larger than the 0.3 ms. Thus 3 ms is the minimum allowed RC
product for the syllabic filter in voice band applications. The
syllabic nature of voice is responsible for the name "syllabic
filter". A CVSD codec can only effectively transmit signals
whose e varies at a frequency much lower than the fundamental frequency of the signal. Conveniently, voice, modem
signals and DTMF signals have this syllabic property.
In Figure 3, a 6 ms time constant is used. In Figure 5, 3 ms
charge and 9 ms discharge time constants are used to improve
attack time without sacrificing constant A. Voice syllables
tend to have this kind of shewed envelope.

Now a 0 dBmo sine wave has a peak value of 1.0954 volts.
In 1/8 of a cycle of the sine wave centered around the zero
crossing the sine wave changes by approximately its peak
value. The CVSD step should track that change. The required current for a 0 dBm 1 kHz sine wave is

*The maximum voltage across RI when maximum slew is
required is ~ ,
2

CLOCK RATE AND SHIFf REGISTER LENGTH
The prime design constraint of a CVSD channel is the
channel bit rate. Since delta modulator produces a serial unframed bit stream, the bit rate and sample frequency are the
same. Obviously, as the clock rate increases so will the end to
end performance. Clocks from 9600 kHz to 64 kHz can be
used in various applications. 16 kHz, 32 kHz, and 37.7 kHz
have the greatest acceptance in practical voice communication equipment.
After fIXing the system bit rate, the shift register length
selection must be made. The length of the shift register determines the amount of past history which will be taken into account in predicting slope. As the clock rate changes, so does
the amount of signal time recorded by the shift register.
Therefore, at rates below 16 kHz a three bit algorithm produces the best results. From 16 kilobits and up, either 3 or 4
bits may be used. Four bit algorithms provide flatter SIN
performance because they account for a longer average past
history of steady state signals. However, the transient
response to level changes is slightly degraded because of the
slower companding response.
'
The integrated circuit is produced with either 3 or 4 bit
registers and is selected by laser link cutting rather than mask
option. Depending on the results ofthe idle channel trim corrections, the die requiring the smallest step sizes is made into
a 4 bit register.

+SVTO +15V

."'
<>-l'f--,----'t--f.'.-

ANALOG IN

FIGURE 3 - BASIC CVSD ENCODER
Single Pole Integration and a Single Pole Syllabic Filter
Are Sufficient for Many Voice Channel Application•.
Selection of External Components Tailor. the Integrated Circuit
to the Application.

Now the voltage range of the syllabic filter is the power supply voltage, thus

LOOP GAIN CONSIDERATIONS
The feedback gain of the CVSD codec is set by the selection of Rx in Fignre 3. After the clock rate, this gain is the
most critical parameter of codec performance. Since the
CVSD algorithm improves the dynamic range of the delta
modulator for lower level inputs, the selection of loop gain
should be based on the near maximum amplitude and frequency signal which must be transmitted. Experimental data
shows that a CVSD codec produces optimum SIN ratio when
the companding algorithm is active between 5"70 and 25"70 of
the time. Taking this into account, the gain resistor Rx can be
selected by determining the required integrator current which
will produce the needed step size for a specified input signal.
Then the resistor should source the required current when the
syllabic filter output is about 25"70 of its maximum value.
The current required to move the. integrator output a
specific voltage from zero is simply

Rx=0.25(VCc)

0.93~mA

for a 5 volt supply Rx = 1.3 k

MINIMUM STEP SIZE
The final parameter to be determined for the simple encoder in Fignre 3 is the minimum step size. With no input,
the CVSD digital output becomes a one zero alternating pattern and the analog output becomes a small triangle wave.
The peak to peak value of that triangle wave i8 the idle channel step size. Its meaning is analogous to the 1Y, LSB quantization error of a conventional 0 to A converter. The codec

3-12

cannot resolve or transmit signal levels smaller than the
minimum step size. In theory, one would wish to make this
parameter go to zero. However, practical errors such as up
and down ramp matching, comparator hysteresis, and filter
op amp offsets combine to cause the idle channel analog output to drift away from the zero dc reference. The codec then
produces two ones or two zeros in order to restore the level.
To set the idle channel step size, the value of R min must
be selected. With no input signal, the slope control algorithm
is inactive. A long series of ones or zeros never occurs. Thus,
the voltage across the syllabic filter, the voltage divider of RS
and Rmin (see Figure 3) sets the minimum allowed voltage
across the syllabic filter capacitor. That voltage divided by
Rx must produce the desired ramps at the analog output.
Again we write the integrator current equation

one pole, an SIN improvement can be realized. An encoder
using such a network is shown in Figure 5. Adding a second
pole in the transfer function of the integrator simply reduces
the total noise bandwidth of the analog output without affecting the relevant voice energies. From another point of
view, a 11110111 input to a single pole integrator produces a
large ramp reversal at the 0 value since the 0 step will be in the
opposite direction but equal in magnitude to the I ramp
before and after it. Since the analog signal is band limited, it
was obviously continuing to decrease at the 0 step and an error in tracking is encountered. If two pole integration is used,
the 10 1 reversal is filtered and the 0 step is much smaller than
the I step preceding it in the long string of ones. Thus the
total error is less. A two pole filter can improve noise performance by 3 or more dB across the entire input level range.
The first pole is still placed below 300 Hz to provide the
liS voice content curve and a second pole is placed somewhere above the I kHz frequency. For telephone circuits, the
second pole can be placed at 1.8 kHz to exceed the 1633
DTMF frequency. The lower the second pole frequency, the
greater the noise improvement. To ensure the encoder loop
stability, a zero is added to keep the phase shift less than
180 0 • This zero should be placed slightly above the low pass
output filter break frequency so as not to reduce the effectiveness of the second pole. A network of 244 Hz, 1.8 kHz
and 5.3 kHz is used for telephone application in Figure 5
while 160 Hz, 1.2 kHz and 2.8 kHz might be used in voice
only channels. The integration filter in Figure 5 has a transfer
function of

Vo
dVo
Vo
II=-+Cr - . ForsmallVo _-0.
Rr
dt
RI
II=CI AVo where AT is the clock period and AVo is the deAT
sired peak to peak value of the idle output.
Thus if Rx and RS are known, R min may be calculated for
any system. The design of Figure 3 is complete.
Figure 4 describes the performance of the codec in Figure 3
with two sets of curves. The codec was optimized around
o dBm but the SINc ratio falls only 6 dB at - 30 dBm. The
low pass nature of the codec and the change of frequency
response with input level is documented on the left of the
figure.

Vout

40=
R2C2(RQ+Rt>

SIN IMPROVEMENT USING TWO
POLE INTEGRATION
One pole integration filters are not the only possibility. If a
two pole integration network is used instead of the simple

S+ _ __
(RQ+RI)CI

S+

R2C2
The selection of the two pole filter network affects the selection of the loop gain value and the minimum step size

35r--------------------------.
III

"C

:i!!:

.15

en
oz
~

~-10

w30+---------------~------~--~

0

:::;-20

w
>-30

w

~25+-------~----------------~~

z

3 BIT ALGORITHM
37.7 Kilobits
1 kHz TEST TONE
C MESSAGE WEIGHT.

CJ

iii

-'-40

I-

~-50

~-60

o

20~~_r-r~--r-r_,__r_r_.~~

-48

-36

-24

-12

0

3 BIT ALGORITHM
37.7 Kilobits

o

12

INPUT LEVEL IN dBmO

2 kHz 4 kHz 6 kHz 8 kHz 10kHz
INPUT FREQUENCY IN Hz

DELTAMOD SYSTEM PERFORMANCE

FIGURE 4 - SIGNAL TO NOISE PERFORMANCE AND FREQUENCY RESPONSE
Data Resu~ From Testing the Circuit in Figure 3.

3-13

Clock
Input

Volce/Non·Voice
Select

37.7 kHz

Digital
Output
37.7 Kllobits (VCC/2)

+12V
15

Analog
Input 2.6~F

16

14

o----j
01
Non Voic
Input

600

1N914
1~F

(Digital
Input)

•

Analog
Output

1k

Vsyl.
200k

600

R2
0.15~F

6

C2

FIGURE 5 - TELEPHONE QUALITY DELTA MODULATOR CODER
Both Double Integration and Active Companding Control Are Used to Obtain Improved CVSD Performance.
Lsser Trimming of the Integrated Circuit Provides Reliable Idle Channel and Step Size Range Characteristics.

resistor. The required integrator current for a given change in
voltage now becomes

The circuit in Figure 5 provides a 30 dB SINc ratio over 50
dB of dynamic range for a I kHz test tone at a 37.7 kilobit
rate. At 37.7 kilobits, 40 voice channels may be multiplexed
on a standard 1.544 megabit TI facility. This codec has also
been tested for 10-7 error rates with asynchronous and synchronous data up to 2400 baud and for reliable performance
with DTMF signaling. Thus, the design is applicable in
telephone quality subscriber loop carrier systems, subscriber
loop concentrators and small PABX installations.

Vout
R2C 2 RICI
.1.Vout+
Iin=R;+
+R;+C, ~

RO

R2C2CI + RICI R2C 2 .1.Vout 2

Ro
.1.T2
The calculation of desired gain resistor Rx then proceeds
exactly as previously described using this current equation.

THE ACTIVE COMPANDING NETWORK
The unique feature of the codec in Figure 5 is the step size
control circuit which uses a companding ratio reference, the
present step size, and the present syllabic filter output to
establish the optimum companding ratios and step sil:es for
any given input level. The companding ratio of a CVSD
codec is defined as the duty cycle of the coincidence output.
It is the parameter measured by the syllabic filter and is the
voltage across Cs divided by the voltage swing of the coincidence output. In Figure 5, the voltage swing of pin 11 is 6
volts. The operating companding ratio is analoged by the
voltage between pin 10 and 4 by means of the virtual short
across pin 3 and 4 of the V to I op amp within the integrated
circuit. Thus, the instantaneous companding ratio of the
codec is always available at the negative input of AI.

SUBSCRIBER CARRIER TELEPHONE QUALITY
CODEC USING MC3418
Two specifications of the integrated circuit are specifically
intended to meet the performance requirements of commer·
cial telephone systems. First, slope polarity switch current
matching is laser trimmed to guarantee proper idle channel
performance with 5 mV minimum step sil:e and a typical I.,.
current match from 10 p.A TO '" pA. Thus a 300 to I range of
step sil:e variation is possible. Second, the MC3418 provides
the four bit algorithm currently used in subscriber loop
telephone systems.
With these specifications and the circuit of Figure 5, a
telephone quality codec can be mass produced.

3-14

The diode DI and the gain of AI and A2 provide a companding ratio reference for any input level. If the output of
A2 is more than 0.7 volts below VCC/2, then the positive input of AI is (VCCI2-0.7).
The on diode drop at the input of AI represents a 120/.
companding ratio (12"70=0.7 V/6 V).
The present step size of the operating codec is directly
related to the voltage across Rx which established the integrator current. In Figure 5, the voltage across Rx in a direction which reduces the difference between the companding
reference and the operating ratio by changing the step size.
The ratio of R4 and R3 determines how closely the voltage at
pin 4 will be forced to 12%. The selection of R3 and R4 is initially experimental. However, the resulting companding
control is dependent on Rx, R3, R4, and the full diode drop
D I. These values are easy to reproduce from codec to codec.
For small input levels, the companding ratio reference
becomes the output of A2 rather than the diode drop. The
operating companding ratio on pin 4 is then compared to a
companding ratio smaller than 12% which is determined by
the voltage drop across Rx and the gain of A2 and AI. The
gain of A2 is also experimentally determined but once determined, the circuitry is easily repeated.
With no input signal, the companding ratio at pin 4 goes to
zero and the voltage across Rx goes to zero. The voltage at
the output of A2 becomes zero since there is no drop across

Rx. With no signal input, the actively controlled step size
vanished.
The minimum step size is established by the 500 k resistor
between Vee and VCC/2 and is, therefore, independently
selectable.
The signal to noise results of the active companding network are shown in Figure 6. A smooth 2 dB drop is realized
from + 12 dBm to - 24 under the control of AI. At - 24
dbm, A2 begins to degenerate the companding reference and
the resulting step size is reduced so as to extend the dynamic
range of the codec by 20 dBm. The slope overload characteristic is also shown. The active companding network produces
improved performance with frequency. The 0 dBm slope
overload point is raised to 4.8 kHz because of the gain
available in controlling the voltage across Rx. The curves
demonstrate that the level linearity has been maintained or
improved.
The codec in Figure 5 is designed specifically for 37.7
kilobit systems. However, the benefits of the active companding network are not limited to high bit rate systems. By
modifying the crossover region (changing the gain of A2),
the active technique may be used to improve the performance
of lower bit rate systems.
The performance and repeatability of the codec in Figure 5
represents a significant step forward in the art and cost of
CVSD codec designs.

FREQUENCY RESPONSE VS INPUT LEVEL
(SLOPE OVERLOAD CHARACTERISTIC)

SIGNAL TO NOISE PERFORMANCE OF
TELEPHONY QUALITY DELTAMODULATOR
35

E
III
'C

z

0
-10

:::; -20

w

~ -30

..J

~ -40
11.

~

-50
0_ 60

4 BIT ALGORITHM
37.7 Kilobit.

20
-48

-36

-24

-12

0

12

2 kHz 4 kHz 6 kHz 8 kHz 10 kHz
INPUT FREQUENCY IN Hz

INPUT LEVEL IN dBmO

DELTAMOD SYSTEM PERFORMANCE

FIGURE 6 -

SIGNAL TO NOISE PERFORMANCE AND FREQUENCY RESPONSE

Data Document the Improvement Realized with the Circuit in Figure 5.

3-15

Time-slot assigner chip cuts
multiplexer parts count
by Henry Wurzburg
Motorola Inc .. Semiconductor Group, Phoenix, Ariz.

•

In some communications systems, particularly digital
telephony equipment, it is hard to examine the data from
a given source after it has been time-division-multiplexed with other data for serial transmission over a
common data line. Capturing the data from its time slot
and converting it into parallel form for examination
usually requires many integrated circuits, since the slot
must be programmable.
A special-purpose Ie, the MC14417 time-slot assigner
carries out this serial-to-parallel function with the aid of
only a few inverters and one other Ie. What's more, the
cost of implementing the circuit is only a few dollars.
The timing of a simple three-slot TDM system is shown
in (a). In digital telephone systems, a data frame may
consist of anywhere from 24 to 40 time slots, each
containing 8 bits of data transmitted at rates of up to
2.56 megabits per second.

FRAME SYNC

In the all-complementary-Mos capture circuit of (b),
the MCI4094 shift register acts as a serial-to-parallel
converter, while the 14417 computes when the data is to
be captured and converted. Just which time slot it ca,ptures is determined by the binary data present at inputs
0 0-0, of the 14417. The circuit also provides a validdata output signal. As for speed, the circuit works for
clock rates of up to 2.56 MHz with systems having up to
40 time slots.
Implementing a parallel-to-serial converter for multiplexing data onto the TDM data line is equally simple if
the 14417 is used as shown in (c). Here, a three-state
buffer prevents the serial data bus from being loaded
during idle time-slot periods. The frequency limitations
of this second circuit are the same as for the capture
0
circuit.

-.J

DATA CLOCK
DATA BIT

I bo I b, I··· I b

7

I bo Ib,

I ... I b

7

I bo Ib, I·· . I b, I bo Ib,

'---------,v~----' ~----y----~~---__y------"'----~y---

TIME SLOT 0,
OATA SOURCE 0

(ill

TIME SLOT 1.
DATA SOURCE 1

TIME SLOT 2,
DATA SOURCE 2

TIME SLOT 0,
DATASOURCEO

~-----------~y~------------~

DATA FRAME

OATA OUT

DATA IN

~
+12 V

SERIAL
DATA OUT

DATA----I
DATA
CLK

ClK

+12 V
+12 V
DC

FRAME
SYNC

'--y-----J
TIME-SLOT SELECT

TIME-SLOT SELECT
INVERTERS: MC14069

Ibl

TIME-OIVISIO N-MU LTiPLEXED
SERIAL-TO-PARALLE L
CONVERTER

lei

TOM
PARALLEL -TO-SERIAL
CONVERTER

The righl slol. Time-domain multiplexing (a) assigns to data from several sources specific time slots in a serial data stream_ Capturing data
from a specific slot is made easy with the MC14417 time-slot assigner (b), which works with the MC14094 shift register to provide data from
the source dictated by the select inputs of the 14417_ The versatile chip can also provide parallel-to-serial multiplexing (c)_

3-16

AN·872

@ MOTOROLA

Application Note

MC14402 MONO·CIRCUIT
APPLICATIONS INFORMATION
by
Richard L. Hall and Micheal D. Floyd
Telecom Systems Engineering

This application note is intended to ease customer evaluation of the Motorola MCI4402 PCM mono-circuit, particularly when using the Motorola Mono-circuit Evaluation
Board. Schematics and artwork of this board are given as
well as layout guidelines for designing the mono-circuit into a
custom PC board. Analog testing considerations are mentioned to help sidestep some of the troublesome aspects of
codec/ filter evaluations.

These options are selected by solderable wire straps (SI-S6)
as described in the Strapping Information Chart. The straps
can be replaced by DIP switches if desired and can be obtained from:
Grayhill Inc.
561 Hillgrove Avenue
La Grange, Illinois 60525
PIN
78105
78102
78101

EVALUATION BOARD DESCRIPTION
The Motorola Mono-circuit Evaluation Board is a small
PC board that contains all necessary clock circuitry for
operating the MCI4402. Coaxial connectors allow access to
the analog input/output ports and the only other connections required are to the three power terminals-Voo, VSS
and VAG. The schematic for this board is shown in Figure I
while the artwork is given in Figure 2.
The clock circuitry uses a 2.048 Mhz crystal to produce the
2.048 Mhz data clock as well as the 8 kHz sync signal. The
8 kHz sync is an 8-data-clock-wide pulse that is connected to
the RCE, TOE and MSI inputs of the mono-circuit. RCE
and TOE are the receive and transmit enables respectively,
while MSI is the 8 kHz reference input. The 8 kHz sync is
generated by the MCI4417 TSAC (Time Slot Assigner Circuit).
Options are available to help evaluate different channel
parameters. These include:
• 600 or 900 ohm channel impedance
• RSI peak overload voltage of 3.15 or 3.78 volts
• TTL or CMOS logic levels
• Transmit and Receive gain adjustment (RxO gain only)
• A or MU-Iaw coding
• Power-down capability

Name
SI
S2,S3
S4-S6

Qty
1
2

3

Figure 3 shows the physical location of the strap points as
well as the component layout. The solid lines indicate the
normal strap positions as shipped from the factory which
select Mu-law, 900 ohm, CMOS, 3.78 volts peak operation.
The straps EI-EIO allow reprogramming of the clock lines to
provide different clock schemes. Refer to the schematic in
Figure I for changing these straps.
TEST CONSIDERATIONS
Input/Output Levels
Obtaining valid test data is highly dependent upon establishing the proper input/ output voltage levels. However, this
can be a somewhat confusing task since the mono-circuit can
use three different peak overload voltages-2.S, 3.1 and 3.8
volts. The evaluation board permits selection of either 3.1 or
3.8 volts. For 3.1 volts, the proper input/output level for a 0
dBmO test signal is +6 dBml600 ohms (1.5455 volts rms).
For 3.8 volts, 0 dBmO corresponds to + 6 dBml900 ohms
(1.893 volts rms). Usually, measurement levels are referenced

3-17

•

AN872

CMOS
VDD

VSS

37av
o---c

S6

"'~

VDD

VOO

R-leN

VSS

21

Digital

(~-Law)

R8

o

51k

R2
10k

S4

~----~E~9---------------------Q'ffi
R3

Data Clock

10k
ElO
Eo

hi

>--+~----~----~VV~~~-T'
+ T,

•

Vag

MCl4402
MonO-Circuit
VDD

TOE TOO TDC ROC

RO~

RCE

MonO-CIrcuit Asynchronous/32 Channel Synchronous Clock Circuli
RED

)

1Op.F~

VDD

r-------------------,

C7
GRN

8LK

>

(VAG)

,

1

Analog
Ground

I

1

;

I 51

:

: LSB

C. VSS

I
:

11

I

I
1

I

L
2048 MHz

0

Yl

'8

20M
Rl

04

02

03

01

Enable

DO
16
hE

VDD
VCC

VDD

12

MC14069

13
10

RxE 15

Ul

T/R

NC

MCl4417

LE

14

17

DC

NC

11

C1 I30PF

-=
E2

YOut

Yin

VDD

02

NC

128kHz
U2

14

8kHz

...l..

-=

7

~---~~~~---0,

03

13
0,

Digital
Ground

C,

Analog

Ground
C3

01,uF

h
r

8kHz
E3

E4

15

VDD

10

C4
Ol/tF

-=

FIGURE 1 - MCI4402 Switch Programmable Evaluation Board PIN 618-1030

3-18

MSI

MSI

Out

10

AN872
to 0 dBmO to avoid possible confusion over absolute levels.
For example, an absolute idle noise measurement of 21
dBmC becomes 15 dBrnCO when referenced to 0 dBmO
(where 0 dBmO= +6 dBm in our system).

distortion and gain tracking should be avoided since these
parameters involve very low voltage levels that require a
selective voltmeter function for accurate results. Also, attention should be given to correct selection of input/output
parameters on programmable test gear such as the HewlettPackard 3779 PMA and others.

Noise
Special care has been taken in the layout of the evaluation
board to minimize noise corruption. The analog and digital
sections are isolated from each other and bypassing is present
to reduce high frequency noise. The use of shielded cable for
analog test lines is recommended to prevent extraneous environmental noise pickup as well as the use of a power supply
reasonably free of high frequency noise. A 500 pF capacitor
has been put on the RxO output to bypass any radiated asynchronous noise that might be picked up at this node.

LAYOUT GUIDELINES FOR PC BOARDS
• Bypassing of both VOO and VSS to VAG with 0.1
microfarad ceramic capacitors (or any other capacitors
with good high frequency behavior) as close to the part
as possible.
• Isolate analog lines from digital sections. The monocircuit pinout facilitates this by keeping digital and
analog pins on opposite sides of the chip.
• Use gain-setting resistors in the range of 50 kO< R < 5
kO to avoid high impedance nodes in the analog section.

Test Equipment

• If VLS is tied to VAG for TTL level selection, then this
connection should be a short, direct, low inductance
trace.
• In a dual supply environment, VDO and VSS should be
connected before VAG (ground).

There are many different pieces of telecommunications
test gear on the market and most will be more than adequate
for testing codeclfilter parameters. However, the use of
wideband measurement devices for such tests as quantizing

MONOCKT ASYNC I 32 CHAN SYNC
CLOCK CKT
618-1029

•
voo

r
V55

•
V5S

FIGURE 2 - Evaluation Board Artwork

3·19

• • •

•

AN872

S6

S5

1

3. 78

Anal~~ Out

~
~

C9

•
R3.

0

~2

C5C)

11 I7

~1' ~

S2A

Tx

C6C)
2B
S3A

600'MU.

•

•

•
VAG

VSS

@@

--

Digital GND

•

S4

•

Data Clock

Voo

B LJ
1

•

~

R9
--c::J--

Time Slot
10

C3

S3B

•

o

C4

Digital Supply

1~MI~NI'UP
!

TT

AnaIOgl:~

~o:.

I

TTL

Enable
I E6E~--E7
..-----~-........

• --c:::::I-- R6
--c:::::I-- R7

•

~E9

E5

~~r

II

I~ ...---=..::..::...:=~•

U5

~~

o

R8

[]

R4

CMOS

!3.15

• • •

•••
wo,uu,o w

MSIOut

• ~~I~~!~~

~.~
~

0

1:..-;MSB

11"

-LSB

C10

OC2

~M""P (~J5
Y1

Access

NOTE: Solid line indicates normal strapping as shipped from factory; dashed lines indicate optional straps as described below in the
Strapping Information Chart.
Reference Voltage

Reference Impedance

(56)

(S2A)

+6/+6
+6/0
010
010
+6/+6
+6/0
010
010

600n

3.15 V

900n
900n

3.78 V

InputlOutput Levels
(dBm)

600n

R2

16.6 k

R3
-

10 k

-

-

12.5 k

10 k

-

R4
10k
10k
20 k
16.6 k
10k
10 k
20 k
25 k

R5
10 k
10k
10k
10 k
10 k
10 k
10 k
10 k

Rout*
Jumper

600n
600n
Jumper
Jumper

900n
900n
600n

• Rout is located between Rx analog out and RxO output underneath the board.
FIGURE 3 - Component Layout

Strapping Information Cbart
SI

SlA
SlB
S3A
S3B
S4

SS

These straps select via Ul (MCI44l7 TSAq one
of 32 possible time slots in the 8 kHz frame.
When used in conjunction with another board,
performance in different time slots can be
RCE).
evaluated. (that is TDE
Selects 600 or 900 ohm input impedance.
Selects A or Mu-law coding.
Selects either TTL(TT) or CMOS(CM) logic
levels. The TTL levels swing from VDD and
VAG; CMOS levels swing from VDD to VSS.
Powers device up or down. DN = Powered down
and UP = Powered up.
Normally loops RDD to TDD. When R-ICN is
strapped, Mu-law receive idle channel noise can
be measured (RDD= 1 111 1111).

'*

56
Rl,R3
R4,RS
R9

Rout

3-20

Controls digital ground of clock logic. When
CMOS is strapped, digital ground = VSS; when
TTL is strapped, digital ground = VAG. Note
that this strap must agree with the selection on
S3A.
Selects either 3.78 or 3.15 volts peak overload
voltage.
Adjusts RxO output level where gain = - R3/R2
(optional).
Adjusts Tx Analog In level where gain =
-R4/RS.
A 1 kilohm pullup resistor is needed when VAG
output is used by itself to provide ground return
for RxO or RxO. If VAG is tied to system power
ground, this resistor can be deleted.
Determines output impedance.

AN872

APPENDIX

o ~ 10 log 1000 ~ms2)

A DB By Any Other Name •••

100 ~
Yrms2 ~
Yrms ~
Yp-p ~

The following is a brief discussion of decibels and how
they are used in the telephone industry in an attempt to lessen
the notorious confusion this term can create.
Engineers are very familiar with the equation definition of
a decibel which is:
Decibels ~ dB ~ 20 log ~

~

In order to understand the proper level at a certain point in
a system, the term dBmO is used for reference. A dBmO
defines the nominal signal level at a test point node. Absolute
levels can then be referred to in dBmO for comparison to the
nominal level. For example, suppose that at a certain point in
a system 0 dBmO ~ + 6 dBrnl600 ohms. Then a - 20 dBm
signal would be equal to - 20 - ( + 6) = - 26 dBmO. Therefore, a - 20 dBm signal would be 26 dB down from the
nominal level.
Noise measurements require a different decibel unit as they
usually involve some bandwidth or filtering constraint. One
such unit commonly used (especially in North America) is
dBm or decibels above reference noise. The reference noise
level is defined as one picowatt into 600 ohms or - 90 dBm.
Telephone measurements typically refer to dBmC which is
the noise level measured through a C-message weighting filter
(a filter that simulates the response of the human ear). European systems use a related term called dBmp which is the
dBm level noise measured through a psophometric filter.
Both dBmC and dBmp can be referenced to 0 dBmO by adding a zero-dBmCO and dBmOp. Two examples are shown
below to illustrate the use of these units:

(I)

or its corollary:
dB ~ 10 log ~i

.

(2)

The use of the logarithmic function eases the use of the large
range of voltage numbers encountered in the telephone industry. A decibel is only a relative term; it defines the difference between two absolute voltage levels.
Which now brings us to the absolute decibel-the dBm
(decibel milliwatt). A dBm is equivalent to a milliwatt of
power delivered into a reference impedance-usually 600
ohms. An equation commonly used to calculate dBm levels
can be derived from equation (2):

dBm

~

(5/3)Yrms2
0.6
0.7746
2(2)II2Yrms
2.191 volts peak-ta-peak.

10 log (P2!P re f)
10 log (P2IO.OOl W)
10 log 1000 (P2)
1010 1000 (Yrms2)
g 6OO0hm

1) 0 dBmO = +6 dBrnl600 ohms
Noise measurement = 20 dBmC
= 14 dBmCO
2) 0 dBmO = + 9 dBrnl600 ohms
Noise measurement = - 70 dBmp
= -79 dBmOp.

where reference impedance ~ 600 ohms.

Understanding these units should help avoid any possible
correlation problems between measurements and published
specifications.

For example, to calculate the peak-ta-peak voltage of a
() dBm sinusoidal signal:

3-21

•

Telecomm ICs create low-cost
phone links 4 miles long

..

Although the maximum recommended length for
communications links over uncompensated 24 AWG
twisted-pair wires is 4000 ft, a few off-the-shelf
integrated circuits, when configured as a line driver,
will drive a communications link with a maximum
length of over 4 miles. The bandwidth of over 3000
Hz is adequate for remote control, sensing, and even
private-telephone voice communications.
Any subscriber-loop interface circuit (SLIC) can
be used to drive the line. In Fig. 1, a SLIC interfaces
with voltage-to-frequency and frequency-to-voltage
converters and a line terminator. Thus a dc voltage
related to a process at a remote site can be measured
from a central location and a corrective dc voltage
can be sent in the reverse direction to adjust or
control the process.
A variety of ICs can be interfaced with the basic
driver for signaling or for data or voice transmission.
Analog-to-digital and digital-to-analog converterssuch as codecs and CVSDs (continuously variableslope delta modulators used for voice companding)
-perform the front-end data conversion for a lowcost computer link. A variety of dual-tone multifrequency (DTMF) encoders and decoders facilitate

simple signaling over privately owned twisted pairs.
A line-driver card exemplifies the simple hardware
configuration required (Fig. 2). The SLIC uses two
Darlington pairs as pass transistors to handle currents of up to 120 rnA. Changing the value of the
59-kn resistor used in the feedback path of the 741
operational amplifier will adjust the transmission
output gain. The MDA220 rectifier bridge protects
the circuit against lightning damage.
The line-terminator card converts a bidirectional
two-wire line into two pairs of unidirectional lines,
one transmit and one receive, and then amplifies the
received and transmitted signals. A simple
terminator can be made with the hybrid transformer
and two varistors from a telephone handset. Even
if a more sophisticated terminator card were built
using a speech-network IC, the cost of the entire
system would be less than the cost of the modems,
PBX lines, or rf transceivers used for short-range,
private communication links.
.
John Hines, Design Engineer, Motorola Inc.,
Bipolar Integrated Circuits Group, Linear IC
Divi.~ion, .500/j E. McDowell Rd., Phoenix, Ariz.
85008.

Voutput

F-v converter

Linednver
card

Lineterminator

card

Vcontrol

Vcontrol

Remote site

Central monttoring site

1. The maximum range of an RS-232 or RS-422 communications link can be extended to over 4 miles of
uncompensated 24 AWG wires by a line-driver card based on a single-chip subscriber-loop interface circuit.

3-22

GNO

VAG

VAG

427 k

1 pF

A,

V"

T,
TSI
CC

ASI
MJE270

30

BN
EN
V"

P01

Power down

HSO

Hook status

TSO

TIp sense

ASO

Ring sense

HST
Va'
232K

43 k

2. A line-driver card requires a SLIC, two Darlington pairs, a rectifier bridge for lightning protection, and
an operational amplifier. A resistor in the op amp's feedback path adjusts the transmission output gain .

"Reprinted with permission from Electronic Design, Vol. 3D, No. 11; copyright Hayden Publishing Co., Inc., 1982."

3-23

®

MOTOROLA
CMOS LSI INTEGRATION ENHANCES
VOICE AND DATA NETWORKS
AI Mouton
MOS Telecom Planning Manager
Motorola, Inc.
3501 Ed Bluestein Blvd.
Austin, TX 78721

•

INTRODUCTION
Digital Voice and Data PBXs are well accepted today as a
viable communication networking solution. This type of
PBX has proven to be a complete and cost effective interconnect approach toward automating the office environment.
A typical Digital Voice and Data PBX, as shown in
Figure I, can appreciate a variety of interconnect functions.
Besides supporting the standard analog voice service, the
PBX provides an inexpensive means for interconnecting
word processors, CRT terminals, gateways to Local Area
Networks (LAN) and other office equipment. The cost effectiveness of this approach is desirable because of the low connect cost and the use of twisted pair wire in lieu of coaxial or
fiber optic cable.

The feasibility of the Voice and Data PBX is made possible
from the development of cost effective LSI semiconductors
that allow high speed data transmission over twisted pair
wire. These ICs, like Motorola's Universal Digital Loop
Transceivers (UDLT) allow simultaneous transmission of the
64 kbps PCM data, as well as signalling and user data between the digital phone and the PBX. With this capability,
full featured digital phones and workstations, where voice
and user data can simultaneously be transmitted over the
existing twisted telephone wire, are made possible.
This paper will discuss Motorola's Universal Digital Loop
Transceiver (UDLT) family of LSI semiconductors, that
offer a cost effective approach to integrating a Voice and
Data PBX.

OFFICE OF THE FUTURE
DATA PBX
VOICE
DATA
PBX

TELEPHONE
NETWORK

TWISTED WIRE

FIGURE 1

3-24

DESCRIPTION OF A VOICE AND DATA PBX
Most digital PBXs manufactured today offer the option of
analog line cards, for voice services, and digital line cards,
for voice and data services. This type of architecture, as
shown in Figure 2, uses an interchangable back-plane compatible to both types of line cards. The interchangable backplane allows the PBX to be structured for many combinations of analog or digital voice/data line cards.
The analog line card contains the traditional functions.
For example, it includes the Time Slot Assignment Circuit
(TSAC) used for logic supervision, the PCM codec/filter
(mono-circuit) used for voice coding and decoding and the
Subscriber Loop Interface Circuit (SLIC) used to perform
the 2 to 4 wire conversion. Also, battery feed, secondarylighting protection, line fault protection, and signal-

balancing functions are included. The back-plane for the
analog line card interfaces to the PCM highway and the
supervision control lines.
On the digital line card, the PCM mono-circuit and SLIC
have been replaced with the Master VOLT. The analog voice
coding and decoding is now performed by the mono-circuit
in the phone. The 64 kbps PCM data and the user data are
transmitted between the Master and Slave VOLTs at a full
duplex data rate of 80 kbps over the twisted wire. Oue to the
VOLT's unique modulation technique, data can be reliably
transmitted over standard twisted wire up to 2 km with no external filtering or compensation circuitry. The Master VOLT
performs the same back-plane I/O functions as the PCM
mono-circuit. This allows interchanging of the analog and
digital line cards in the PBX.

•

VOICE I DATA PBX
ANALOG
LINE
CARD

I

I
I

I
I

I
I

4-->3km ___

I
- - - - - - - - - -i

ANALOG PHONE

DIGITAL LINE CARD

2 WI RE 80 kbps
TO

H - - ' ' - . - - - - SWITCH
MATRIX
PING PONG

-----------,

DIGITAL PHONE

I
I
I
I
I
I

FIGURE 2

3-25

MOTOROLA'S LSI IC FAMILY
PCM MONO-CIRCUITS

•

•
•
•
•
•
•
•
•
•

Low power CMOS technology
Single or split power supplies
Power supply operation at 6 to 13 volts
On-board selectable voltage reference 2.5,3.1 or 3.8 volts
Data clock from 64 kHz to 3 MHz
CMOS or TTL I/O interface
High output drive capability-12 dBm into 600 ohms
16, 18, and 22 pin package options
A-law CCITT, MU225-law D3 and MU255-law sign
magnitude selectable
• 28 pin leadless chip carrier package
• No external components

Motorola's family of PCM mono-circuits incorporates the
codec, filter and voltage reference functions into a single IC
package. These devices perform the voice digitizing and
recovery, as well as the band limiting and signal restoration
necessary in PCM systems. The mono-circuits are tailored
for a variety of PBX architectures. The family consists of
five different device types. The MCI4400, MCI4403 and
MCI4405 are in a 16 pin package. The MCI4401 is in a 18 pin
package, and the MCI4402 is in a 22 pin package. Figure 3
shows the functional block diagrams that make up all the
mono-circuits. They are the transmit and receive filters, the
DAC decoding/encoding logic, the on board selectable
voltage reference and the transmit and receive digital I/O
logic. Some basic features are:

The PCM mono-circuit family offers options suited for
both line card and digital phone applications.

PCM MONO-CIRCUIT BLOCK DIAGRAM

VAGC>-----------tr=======~==========~----_++_+__+--~

RXOClH--::-t-+__+......----!
RXG
RXO .........._-r_-'

TDC

+ TX ............r---'......,
TXI
- TXL.,.;l-L_ _--I

r

~ ~

Vss

VLS

MSI

MCl4400101/02l03/05
NOTE: 9 = CONTROLLED BY VLS

AA01815-2

FIGURE 3

3-26

TIME SLOT ASSIGNER CIRCUIT (TSAC)

Motorola has three different per-channel TSAC ICs. The
MCI4418 is the full featured TSAC in a 22-pin package. In
addition to performing all the supervision and control functions required in a singie-party telephone line circuit, it performs the variable time slot assignment required in many
digital switching applications.

faces the mono-circuit to the twisted wire pair. The
Master/Slave VOLTs operate in a frame synchronous manner, sync being established at the Slave by the timing of the
Master's transmission each frame over the twisted pairs to
the Slave. The Master's sync is derived from the PBX
frame sync.

MASTER UDLT BLOCK DIAGRAM

The TSAC can be programmed for up to 64 8-bit time slots
through a serial microprocessor port. It also has three additional MPV-programmed control bits that can be used for
ring enable, power down, receive data/tone or other control
and supervision functions. A reset pin is used, in conjunction
with the ring enable, to perform the ring trip function. The
unique addressing capability allows the use of a completely
parallel back-plane for PCM codec/filter-based equipment.
This scheme simplifies back-plane wiring and assembly of the
channel group.

..

The MCI4417 has the same core as the MCI4418 but does
not use the MPV port feature. Time slot data inputs are
directed through an 8-bit parallel port. The data may be
either hard wired on the printed circuit or parallel loaded by
a processor using the Latch Enable function.

~---L~~J=:i'----E33i~f

FIGURE 4

The MCI4416 is also a subset of the MCI4418. It performs
the time slot assignment function using the serial MPV port,
but it lacks the simplified addressing and line circuit control
capabilities of the MCI4418.

SLAVE UDLT BLOCK DIAGRAM

MASTER AND SLAVE VOLT

The MCI45422 Master and MCI45426 Slave VOLTs are
high-speed transceivers intended to provide 80 kbps duplexed
data communication over 26 A WG and larger twisted pair
cable up to 2 kilometers in distance. The VOLTs allow the
remoting of the mono-circuit in a digital telephone set and
enable each set to have high speed data access to the PBX
switching facility. In effect, the VOLTs allow each PBX
subscriber direct access to the inherent 64 kbps data routing
capabilities of the PBX.

FIGURE 5

The VOLT utilizes a •'ping pong" transmission technique,
as shown in Figure 6. Ten bits (eight bits of PCM data and
two bits of signaling data) are sent in a 256 kilobaud burst
from the Master VOLT every frame or 125 p.s. The Slave
VOLT receives this burst and, after a short line settling interval, returns at 256 kilobaud, 10 bit burst of data to the
Master VOLT. With this transmission scheme, the maximum
loop length is determined by the cable delay time, number of
bits in each burst, and the burst baud rate. This results in a
maximum loop length of 2 km.

The VOLT provides a means for transmitting and receiving 64 kbps of voice data and 16 kbps of signaling data. The
Master VOLT replaces the codec/filter and SLIC on the
PBX line card, and it transmits and receives data over the
wire pair to the telset. The Master VOLT, as shown in
Figure 4, appears to the line card and backplane as if it were
a PCM codec/filter and has almost the same digital interface
features as the MCI4400 series mono-circuits. The Slave
VOLT, shown in Figure 5, is located in the telset. It inter-

3-27

•

The UOLT uses a modified OPSK (MOPSK) modulation
technique, resulting in a triangular waveform, as shown in
Figure 6. This waveform results in a lower spectral content,
thus low EMI and RFI radiation. The MOPSK waveform is
very similar to FSK, except that the burst always begins with
a 256 kHz half cycle which identifies the burst boundaries.
Each baud period has no net dc bias. This eliminates any dc
balancing bit requirement. Furthermore, auto equalization
for phase dispersion is not required.

UDLT
2-WIRE PING PONG TRANSMISSION
TECHNIQUE
.
125~sFRAMePERIOD---

•

ideally suited to provide an interface between a RS-232 port
and the UOLT. The OSI IC has an on-board baud rate
generator with 7 selectable baud rates ranging from 300 to
38.4 kbps. An external baud rate generator can be used for a
clock range from dc to 128 kbps. Another feature of the OSI
IC is its ability to optimize the data length by stripping off
the start and stop bits before being transmitted as a synchronous word. Likewise, the OSI will add the start and stop
bits back to the incoming synchronous word.

MOTOROLA VOICE/DATA FAMILY
MC145428
DATA SET INTERFACE

-

MASTER UOLT
BURST

SLAVEUDLT
DECODe

SLAVE UDLT
BURST

MASTER UDLT
DECODE

FIGURE 6

FIGURE 7

A feature of the Master UOLT allows one of two signal
bits to and from the Slave to be inserted and extracted from
the PCM word. This feature allows simultaneous voice and
data transmission through the PBX. All UOLTs have a loopback feature by which the device can be tested in the user
system.

The MCI45428 was designed in Si-gate CMOS technology
and utilized in a 20 pin package. This IC will lend itself to a
variety of data communication applications.

TELSET AUDIO INTERFACE CIRCUIT (TAlC)
The Slave UOLT has the additional feature of providing a
500 Hz MU or A law coded square wave to the mono-circuit
when the TE pin is brought high. This feature is used to provide audio feedback in the telset during keyboard depressions.
The devices employ CMOS technology in order to take advantage of its reliable low-power operation and a proven
capability for complex analog/digital LSI functions.

DATA SET INTERFACE (DSI)
The MCI45428 Oata Set Interface circuit, as shown in
Figure 7, provides the asynchronous to synchronous data
conversion to the UOLT, as well as the synchronous to asynchronous data convertion from the UOLT. The OSI IC is

The MCI45429 Telset Audio Interface Circuit, as illustrated in Figure 8, enhances the digital phone by giving the
microcomputer control of the analog signals between the
PCM mono-circuit and the telset mouthpiece, earpiece,
ringer/speaker, and auxiliary input/output.
The configuration of the device is programmed via a serial
digital data port. Features of the MCI45429 include:
• Independent adjustment of earpiece, speaker, and ringer
volume
• 20 dB mouthpiece signal gain
• Signal routing for loopback test
• Receive low-pass filter for 8 kHz attenuation
• Sixteen possible audio configurations
• Provision for auxiliary speaker phone
• Power-down mode with data retention

DIGITAL PHONE APPLICATION

MOTOROLA VOICE/DATA FAMILY
MC145429
TELSET AUDIO INTERFACE CIRCUIT

In Figure 9, a Oigital Feature Phone is implemented using
the MC145426 Slave VOLT, the MCl4402 mono-circuit and
the MCl46805 CMOS microprocessor. In this application
the Slave VOLT generates the clocks and frame periods for
both the MPV and the mono-circuit. The Slave VOLT also
transmits and receives the 64 kbps PCM voice word from the
mono-circuit and the 16 kbps signaling data for the MPV ..
The VOLT powers down itself and the other logic
automatically in an on hook mode.

EpO

SCI

'------[]

The mono-circuit is used for voice coding and decoding, as
well as the interface to the speaker and microphone in the
handset. The RXO output pin provides the output signal to
the earpiece, while the RXG pin sets the signal gain. The
RXO pin provides the output for the ringing signal to the
piezoelectric transducer or speaker. The TX pins are used for
setting the gain of the incoming signal and side tone.

..,

FIGURES

The MC145429 is designed in Si-gate CMOS technology
and is implemented in a 18 pin package. This device adds
ease of analog signal adjustment with software, in lieu of
hardware.

The MPV provides for the keyboard encoding, speaker
enable and other features desired.

FEATURED DIGITAL TELSET

~
"::"

h; ~~o

.....,."..,......7;T=X-::"I---""'V"'D:-:O""'21

: ......
~ w .......I....._+-8-1 TX -

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L01 21
L02 20
;:::
LI1 2
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ROD 20
13 TX
RCEI-;1.;9_-+_ _ _,.:.12::.jTE1

..

ROC~

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R3

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AN943

S2 - This switch is optional and is hardwired to signaling
channel one for demonstration using LEDs. The footprint for
this switch is included on the board.
This switch can be obtained from:
Cutler-Hammer
PIN B8500W/P281R
S3 - These straps select Mu or A laws and power down on
the MC14403 Mono-circuit and MC145422 master UDLT.
SW1 - (PD) This strap when high, powers both the monocircuit and master UDLT. When low, both parts are
powered down.
SW2 - (Mu/A) Selects Mu or A law coding.
Loopback and Valid Data on the master can be accessed via
pads.

SW5 - ILS) When low, the 64 kilobits-per-second of information coming from the master will loop through the slave
and return to the master. The signaling bits are unaffected.
S3 - Same as the S2 switch on the master.
POWER SUPPLY CONSIDERATIONS/LAYOUT
GUIDELINES
The power supply requirements for these boards are VDD at

+ 5 volts, VSS at - 5 volts and VCC which is the RS-232 driver
positive voltage of + 7 to + 12 volts for the MC1488. VCC may
be as low as + 5 volts with the M C145406 Driver/Receiver
chip. The power supply current required by each of these
voltages is less than 30 milliamperes. This results in a total
slave board power consumption of less than 400 milliwatts.
This amount of power may be supplied by the loop using a
linear supply. To isolate the RS-232 port with respect to earth
ground, a switching regulator powered by the loop or an external power supply will be required. If a switching regulator is
used, it should be synchronized to the eight kilohertz and 128
kilohertz clocks of the slave UDLT to reduce the affects of
aliasing noise into the analog circuitry of either the UDLT or
audio voice channel. This function will be supported by the
MC34129 Digital Telephone Switching Power Supply Controller chip. This device has the capability to power-up and
regulate on its internal oscillator. After regulation is established it can synchronize to an external clock such as the slave's
128 kilohertz clock.

STRAPPING ON THE SLAVE
S1 - Same as S 1 on the master; selects asynchronous data
format and bit rate.
S2 - These straps select Tone Enable, Power Down, Mu/ A,
and Loopback features of the slave (MC145426) as well as
Mu/ A and Power Down on the MC14402 Mono-circuit.
SW1 - (TE) A high enables a 500 hertz tone.
SW2 - (PD) Powers both the slave and mono-circuit up or
down. High = powered up, and Low = powered down.
SW3 - (Mu/ A) Selects Mu or A law coding for the monocircuit.
SW4 - (Mu/A) Selects Mu or A law coding for the slave
UDLT.

3-37

•

•

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II

OB-25
2 TxO

~~
VSS -5 V
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VCC
+12 V
C7

Vec
+12V

C11

C6

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-= -= O.lI'F

O.lI'F

0.1 ~F

MC145406
--U4VOO
Vec
Rx1
001
Dl1
002
Dl2
003
Dl3
GNO

MC1488
U6
VCC
VEE
101
IA
102
OA
IB1
00
IB2
IC1
IC2 9
OB
OC 8
GNO

~O

16
15
14
13
12
11
10

9

L
Cot)
I

Cot)

00

-MIC
(BLACKI
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(WHITEI

Sl

VOO
+5V
MC145428
1
U2
20
NC 2 TxS ~ 19
TxO
RESET
53
Sl·
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NC : BRClk ODE: 7
BC
CMj.J.I!.---,
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DC
Sl·3 7 BR2
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RxS 12 NC
10 VSS
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13
14
15
16
17
18
19

MC145426
T;-m-;:O
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S02
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Rx
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7
6

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PINS 2 & 3TIED TOGETHER
PIN4
TIP

L02

E
N-l

~VOO +5V

~VSS-5V
*These optional resistors provide additional
power supptV noise isolation and are utiliz-

ed by cutting the trace that jumpers across
them.

Figure 6. Slave UDLT Demo Board

220 Rl0
220 R9

PIN 1

RING

~

Co)

AN943

MASTER UDLT DEMO BOARD
PARTS LIST

SLAVE UDLT DEMO BOARD
PARTS LIST

PART

QUANTITY
(PART NUMBER)

PART

QUANTITY
(PART NUMBER)

MCl45422
MC145428
MCl4403
MCl45406
MCl489
MCl488
MCl4069UB
MC74HC74
MC74HC393
LEPCO P-1358A
OB25
RJll
GRAYHILL (SPDT 7BJ05)
CUTLER-HAMMER B8500W/PZ81R
GRAYHILL (SPDT 78J02)
BANANA JACKS
20 pF
O.l/,F
10/,F
10M
5K
3300
1.6 K
3.6 K
56K
10 K
1K
2200
10 K
100
CRYSTAL
JUMPERS
DIODES 1N914
LED (Tl)
2N2907

l-Ul
l-U2
l-U3
l-U4
l-U5
l-U6
l-U7
l-UB
l-U9
l-Tl

MC145426
MCl45428
MCl4402
MC145406
MCl489
MCl488
LEPCO P-1358A
DB25
RJ11
GRAYHILL (SPDT 78J05)
CUTLER-HAMMER B8500W / P281 R
BANANA JACKS
20 pF CAPS
O.l/,F CAPS
10 /,F CAPS
10 M
5K
3300
5K
5000
10 K
56K
2200
10 K
1K
100
JUMPERS
CRYSTAL
LED (Tl)
DIODES lN914
2N2907

l-Ul
l-U2
l-U3
l-U4
l-U5
l-U6
l-T1
1
1
2-S1 & S2
l-S3
6
2-Cl & C2
10-C3-Cll, C14
2-C12, C13
l-Rl
l-R3
l-R4
l-R5
l-R6
l-R7
l-R8
2-R9, Rl0
3-Rll, R13, R2
l-R12
2-R14, R15
12
1-4.096 M
1
2-01, D2
1

1
1
l-Sl
l-S2
l-S3

6
2-Cl & C2
12-C3-C14
2-C15, C16
l-Rl
l-R2
l-R3
l-R5
l-R6
l-R7
l-R8
l-R9
2-Rl0, Rll
2-R12, R4
2-R13, R14
1-4.096 M
10
2-01, D2

SOLDER TAIL SOCKETS

1
1

14
16
20
22

SOLDER TAIL SOCKETS
14
16
20
22

5
2

PIN
PIN
PIN
PIN

3-39
---~-

---

---------

PIN
PIN
PIN
PIN

2
1
1
2

•

AN943

•

3-40

AN943

...
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u

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3-41

II

AN945

®

MOTOROLA

Interfacing the MC145418 and MC145419
Digital-Loop Transceivers to a
Single Twisted-Wire Pair

•

the other feed resistor in a differential drive·type configuration. When MEO is low all of the NAND gate outputs are
forced high, which represents a 0 volt differential potential at
the transformer, so no signal is coupled through the transformer and the line receives no signal, thus fulfilling our
transmission requirements.

The MC145418 master Digital-Loop Transceiver and the
MC145419 slave Digital-Loop Transceiver (DLTs) provide a
highly flexible digital transmission environment which can be
easily adapted for use in voice/data applications over a single
tWisted-pair wire The DLT is designed to promote communication between two digital synchronous serial devices over a
transmission medium which can support the Modified Differential Phase Shift Keyed (MDPSK) protocol utilized between
the master and slave. To further simplify interface requirements, the outputs from and inputs to the DLT. with respectto
the transmission medium, are digital CMOS technology. By
utilizing the inherent features of the DLT an interface can be
designed that supports signaling, data and voice operation
along with battery feed for digital telephone applications. The
purpose of this note IS to Investigate the design of such an
interface.

MEO - - . - - - - -......-1
TIP

T1

II

(
n =1

RING

TRANSMISSION
The typical transmission scheme of the DLT takes eight bits
of information from the transmit register along with two bits of
information on the signaling bit inputs and creates a ten bit
word that is then modulated and presented to the DO output
along with a valid signal indication called MEO. The transmit
register is an eight bit shift register that takes the information
presented at the Rx pin and is loaded by the TDC/RDC clock on
the master or CLK by the slave when REl is high. This information is loaded into the modulation buffer by the leading
edge of MSI on the master, or TEl on the slave. Along with
these eight bits, the information resident at Sil and SI2 are
loaded into the modulation buffer to create a ten bit word. This
word is modulated and transmitted at a 256 kbps data rate.
The DO pin is always presenting changing data at the output
so a signal called MEO is available to define when the DO is
transmitting valid data. MEO will stay high for all ten bit
periods and then go low so it can be used as an enable signal
to enable DO onto the transmission medium, in this case the
tWisted-pair wire.
Since DO can start valid in either a low or a high state, there
must be a way of indicating the start of a transmission that is
data independent. The easiest way to do this is to use a bipolar
scheme where highs and lows are represented by positive
and negative voltages on the line and when no valid transmission exists, no voltage is sent to the line By using a small
pot-core transformer, an interface can be designed that uses
standard HC-series CMOS digital parts for the driver in a
differential drive scheme that performs in this bipolar scheme.
Figure 1 shows a circuit that uses one MC74HCDD quad
two·input NAND gate package. When MEO is high, DO is
inverted by two of the NAND gates and they drive a feed
resistor tothe coupling transformer. This inverted output also
goes to the other two NAND gates which re-invert it and drive

DO

*=MC74HCOO

Figure 1. Transmit Interface
The HC-type devices have a low impedance output which is
used to preserve the proper line impedance tothe twisted-pair
for optimal performance. The twisted-pair is typically a 110
ohm impedance transmission line and for the best power
coupling this condition must be preserved. On the driver side
of the transformer, the 110 ohm impedance IS translated to
440 ohms through the 2 to 1 winding ratio of the coupling
transformer. This means that the drivers see 440 ohms plus
two 220 ohm resistors. Looki ng back into the source from the
line side of the transformer, the two feed resistors are tied to
low impedance sources so the net source impedance is the
series combination of the feed resistors (2x220 ohms) times
the transfer ratio of the transformer (12/22) which gives an
equivalent impedance atthe line of 1100hms. This guarantees
that the power transfer to the line is maximized.

RECEPTION
On the other end from the transmitter, the receiver must
remove the signal from the line without disrupting the line
balance and convert it into a digital MDPSK signal with an
associated valid reception signal. The signal is then demodulated into ten digital bits and loaded into the demodulation
buffer. When demodulation is complete, the eight bitsoriginating from the transmit register are loaded into the receive
register and the SI bits from the transmitter will be put onto
the SO pins on the next MSI for the master, or TEl for the
slave. The receive register can be unloaded via the Tx pin on
the master With the TDC/RDC clock and the TEl enable. The
receive register of the slave is unloaded when TE 1 is high and
by CLK.

3-42

AN945

Figure 2 shows how an LM339 quad comparator chip can
be used to extract the necessary information from the
coupling transformer. In this scheme a step-up winding IS
used to help the overall sensitivity of the receiver. The 51
kilohm and 10 kilohm resistors present an Impedance to the
line of about 3.8 kllohms so that the receiver presents a
minimal Impedance change to the line. These two resistors
provide an over lunder voltage protection network In conjunction with the two clamp diodes Near end coupling of the
transmit along with the voltage boost due to the transformer
windings can create excessive voltage sWings that will
damage the LM339, the network prevents this from happening When In a clamp condition, the 10 kilohm resistor
prevents the receiver from reflecting a low impedance to the
line through the transformer. From this point the signal is now
fed Into the comparator circuits The comparator that outputs
to 01 is strictly a limiter and IS used to square the signal so that
It is easily demodulated. The other three comparators provide
+5 V

01

TIP
T1

II ~
(

n

I

RING

SYN

Window detector Will have drop-outs near the zero crossings
due to the thresholds. The SYN pi n determines If the signal
being input IS valid based on the percentage of time the signal
remains high and the percentage of time in which drop-outs
are present For more detail on the operation of the SYN pin
consult the MC145418/MC145419 data sheet. The thresholds can be adjusted by changing the 50 ohm resistors.
Larger resistors Will help to de-sensitize the detector for nOIsy
environments with some degradation In attenuation performance. Smaller resistors can be used in qUiet environments
where attenuation may be larger (such as extremely small
gauge wire).

TRANSFORMER
Care must be taken in transformer design to guarantee
proper operallon and maximum performance Figure 3 shows
a diagram of the optimized transformer. In using the transformer one Will see that the line Side has split Windings. If
there IS a need for a dc power feed to a remote OLT cirCUli,
battery feed can be Injected at B + and B -. In thiS case a 1 0
microfarad capacitor should be placed between B + and B -to
preserve ac coupling. If battery feed is not used, B + and B may be connected together directly. For best performance the
Tx winding should present no more than 1.75 millihenrys In
Inductance to the transmitter. An opllonal 1000 picofarad
capacitor can be added across the Tx Winding to roll off the
unused harmonics that exist above one megahertz. Care
should also be taken to guarantee that all of the Signal above
40 kilohertz (20 kilohertz IS even better) is preserved so that
the maximum amount of signal energy and information is
available at the receiver. A final note in transformer design is
in remote powering where dc current IS present in the line
loop, the transformer must be deSigned to not saturate. This
means larger currents will probably demand larger cores so
power must be kept to a minimum.

TX~T1ETIP
~ 05
n.

I";; 1 75 mH
n~ 2

Tx

Figure 2. Receive Interface
a Window detector that helps define the burst envelope to
SYN. The four-resistor network provides a midpOint voltage
between the supply voltages to use as a reference for Itie
Window detector and to provide a midpoint voltage for the
transformer The two capacitors are decoupllng capacitors
used to stabilize the reference. Each 1 kilohm and 50 ohm
resistor network set a threshold voltage with respect to the
midpol nt voltage for the Window comparator. One comparator
checks for a valid indication above the midpoint and the
second comparator checks for a valid ind,callon below the
midpoint. The outputs are then wire "ored" into the last
comparator which feeds the results to SYN. Note that the

RX-:l

T1 ~ LEPeO P-1307-A
OR EOUIVALENT

B-

E~05

RX~

B+

RING

Figure 3. OLT Coupling Transformer
OPERATION WITH THE UOLT
While thiS circuit is intended to provide a means of
Implementing a OLT system, the signals presented at the line
by the OLT, with thiS interface, are compatible with the UOLT.
Th'e signals from the UOLT can be demodulated by the OLT.

3-43

LSI for
Telecommunications
a one-chip telephone

w. DAVID PACE
Motorola, Inc.
Tempe, Arizona

•

In recent years, a number of integrated circuits - such as DTMF
dialers, speech networks, and tone
ringers - have been developed for
telephone applications. These products have replaced electromagnetic
elements of the telephone because of
performance and cost improvements
achievable with integrated systems.
In addition, the use of integrated circuits in telephones provides considerable freedom in the external design of telephone sets from both the
practical and aesthetic points of
view.
With these objectives in mind, a
single-chip telephone circuit has
been developed. The MC34010 Electronic Telephone Circuit (ETC) provides all the functions of a standard
tone-dialing telephone. In addition,
a microprocessor interface port facilitates automatic dialing features.
An important characteristic of the
ETC is its ability to operate with instantaneous input voltages as low

as 1.4 V. Low-voltage operation is a
key requirement in North American
telephone networks, where parallel
connections are common.
FUNCTIONAL BLOCKS OF
THE MC34010 ETC
Figure 1 shows the elements of
the ETC:
• Line Voltage Regulator: provides the dc termination of the subscriber loop and a bias voltage for
the DTMF dialer and speech network.
• DTMF Dialer: generates the appropriate dual-tone multi-frequency
(DTMF) signals for dialing.
• MPU Interface: allows the
DTMF generator to be controlled by
a separate microprocessor, which
may be programmed to provide automatic dialing features.
• Speech Network: provides the
two-wire to four-wire interface between the telephone line and the

Fig. 1 Major elements 01 the MC34010 ETC.

3-44

receiver and microphone of the
handset.
• Tone Ringer: converts the ac
ringing signals from the exchange
into a warbled tone emitted through
a piezo sound element.
Line Voltage Regulator
The line voltage regulator provides a regulated bias voltage at the
VR terminal of 1.1 V to other sections ofthe ETC. The low saturation
voltage of an external PNP pass
transistor allows the line input voltage to fall within 300 m V ofVR voltage without clipping signals on the
line. Thus, the DTMF and speech
circuits maintain specified performance with instantaneous line voltages as low as 1.4 V.
The circuit associated with the LR
terminal determines the dc resistance of the telephone. At low line
voltages (corresponding to operation in parallel with nonelectronic
telephones), the ETC draws only 5
rnA of bias current for the speech
network and keypad interface circuits. When the V+ terminal voltage
exceeds 3 V, excess line current
flows through an external resistor
at terminal LR. The 3-kV level shift
from V+ to LR prevents saturation
of the dc termination circuit with
signals up to 2 V peak (+5 dBm) on
the line.
An internal constant current sink
nominally equal to the bias current
of the DTMF dialer also flows
through the dc termination circuit.
When the DTMF dialer is activated,
this current sink is disabled to reduce the line current transient and
dialer clicks.
DTMF Dialer
Inexpensive telephone keypads
have switches of the single pole/
single throw (SPST) type that connect the row and column terminals
corresponding to the selected digit.
A keypad interface circuit within
the ETC, consisting of input resis-

tors, comparators, and decoding
logic, activates the DTMF tone generators whenever two keypad input
terminals are connected.
When the keypad interface activates the DTMF generator, it also produces a mute signal for the speech
network. This mute signal disables
the transmit amplifier and reduces
the DTMF sidetone in the receiver.
Muting the receiver also suppresses
clicks associated with DTMF turnon and turn-off transients.
The row and column tone generators include a programmable counter, an encoder, and a digital-toanalog (DI A) converter. The output
of the 01 A converter is a stair-step
approximation of a sine wave with
16-step intervals per period. Fourier
analysis of such a waveform reveals
that the time intervals corresponding to the positive and negative
peaks (first and ninth intervals) can
be shortened or lengthened with little impact on distortion. By modify-

. ...

Fig. 3 The MPU interlace circuit.

9

..

. mlllIlNTlRVAUI
Fig. 2 The DTMF frequency synthesis technique.

ing the division ratio of the programmable counter during these
peak intervals, output frequency errors are reduced. The periods of the
DTMF tones are adjusted to the desired value within the resolution afforded by the 500-kHz oscillator
frequency.
Figure 2 depicts the implementation of this error reduction technique. The programmable counter
divides the 500-kHz clock frequency
by a number N that is loaded by the
control logic at the beginning of
each step. The output frequency of
the programmable counter is further divided by the 4-bit interval
counter. It is this counter which distinguishes the 16 waveform intervals. The output ofthe 4-bit counter
drives the D/A converter through

an encoder (not shown in Figure 2
for simplicity).
Consider, for example, the generation of the 697-Hz Row 1 tone. For 14
of the 16 waveform intervals the
control logic loads the programmable counter with a divisor of 45.
For the first and the ninth intervals,
however, feedback from the 4-bit interval counter causes the control
logic to program the counter to divide by 44. This combination of divisors reduces the 500-kHz clock frequency to 11.14 kHz at the output of
the programmable counter. The interval counter divides this signal by
16, producing a 696.4-Hz Row 1 tone.
The desired frequency of 697 Hz,
therefore, is synthesized with an error of only 0.09 percent.
Other DTMF tones are generated

3-45

by loading the programmable counters with appropriate pairs of divisors. The worst-case frequency-division error for the eight dialing tones
is 0.16 percen t. Reducing the divider
errors permits an inexpensive 500kHz ceramic resonator to be used for
OTMF clock generation instead of a
more precise quartz crystal. In addition, the lower clock frequency allows the counter to be fabricated in a
linear-compatible integrated injection logic (I 2 L) technology which
enhances the performance of the
analog sections of the ETC.
The outputs of the row and column 01 A converters are summed in
the proper proportion (with a 2-dB
twist) and amplified to drive the
telephone line. The amplitude of the
line's signal is determined by an external resistor. Feedback around the
OTMF output amplifier reduces the
dialing-mode output impedance to 2
kn to satisfy return-loss specifications.

MPU Interface
The MPU interface permits communication between the telephone
keypad, the OTMF dialer, and a microprocessor. Through this port,
telephone numbers may be stored in.
the microprocessor and later retrieved for automatic dialing. Figure 3 shows the major blocks ofthe
MPU interface section and the connections between the keypad, OTMF
dialer, and microprocessor.
Each button of a 12- or IS-number
keypad is represented by a 4-bit
code. This same code controls the
programmable counters to generate

processor is in place. Subsequently,
TO is switched to a logic "0" to generate a DTMF tone pair on the line.
An exclusive OR circuit in the
keypad interface logic determines if
more than one key is depressed.
Single tones may be initiated by depressing two keys in the same row or
column. The exclusive OR circuit
also generates the DP and MLS output signals. DP indicates when one
and only one key is depressed, thereby signaling the microprocessor that
valid data are available. MS indio
cates when the DTMF generator is
enabled and the speech network is
muted.

VA

-~1

TXO

Speech Network

•

Fig. 4 Speech network block diagram.

the appropriate row and column
tones. Binary words corresponding
to keypad digits are transmitted
serially to or from the microproces·
sor via the 4-bit shift register. The
direction of data flow is determined
by the state of the DD terminal
input.
In the manual dialing mode, DD is
a logic "0"; the 4-bit code from the
keypad is fed to the DTMF genera·
tor and also loaded into the shift reg·
ister. The microprocessor-controlled
clock shifts the data through the
1/0 terminal on negative clock
transitions. The shift register load·
enable circuit cycles the register be·

tween the load and shift modes such
that multiple read cycles may be
provided to the microprocessor for a
single key closure. Six complete
clock cycles will output a 4-bit word
from the ETC and reload the shift
register for a second look.
In the automatic dialing mode,
DD is a logic "1" and a 4-bit code is
entered from the microprocessor
into the ETC. The shift register loadenable circuit is disabled in this
mode. Only four clock cycles are required to transfer a digit to be dialed
into the ETC. A logic "1" on the TO
terminal disables the DTMF output
until valid data from the micro·

Fig. 5 Tone ringer block diagram.

3-46

The speech network illustrated in
Figure 4 provides the two· to four·
wire interface between the telephone
line and the transmit and receive
transducers. The key feature of this
circuit is its ability to operate with
instantaneous line voltages as low
as 1.4 V. Satisfactory operation has
been demonstrated in parallel with
a carbon microphone telephone for
loop resistances of up to 2200 Q. This
corresponds to 27,000 ft of 26 AWG
cable between the subscriber terminal and the local exchange.
An electret microphone biased by
the VRregulator drives the transmit
amplifier. The microphone is muted
internally by the dialer during
DTMF signaling and may be muted
by the control signal on the MM
terminal.
For very loud talkers, the peak limiter reduces the transmit amplifier
input level to maintain low harmonic distortion. Transmit gain control
is achieved by varying the satura·
tion resistance of the transistor
which drives the TXL terminal. This
transistor operates as a variable reo
sistance because its collector terminal is unbiased. The peak limiter
circuit determines when the transmit amplifier output approaches the
clipping level and drives the transistor at TXL to attenuate the amplifier input. The peak limiter typically
provides 3D-dB additional dynamic
range with approximately 1 percent
total distortion.
As shown in Figure 4, the transmit amplifier output signal is in·
verted at the STA terminal to pro·
vide sidetone cancellation at the receiver. The signals from the telephone line and the STA terminal are
summed at the input at the receive
amplifier. When transmitting, these
signals are nominally 180 0 out of
phase and the proper choice of ex·
ternal components will nullify the

transmitted signal in the receiver. In
practice, phase shift from the transmit amplifier output to the line due
to reactive line impedances limits
the degree of sidetone cancellation
achieved.
The receive amplifier output produces a signal current in the receive
transducer that also flows through
the VR regulator to the telephone
line. This ac current determines the
impedance of the telephone at the
interface with the line. The input
impedance is set by the proper
choice of receive amplifier gain and
receiver impedance. A 30M receiver driven with a gain of one-half
results in a 600-0 input impedance
and satisfactory receive sensitivity.
Tone Ringer
The tone ringer responds to large
signal ac input voltages with a

warbled two-tone output signal which
may drive a piezo transducer or
speake,: This warbled tone is produced by di viding the tone ringer oscillator frequency alternately by Bor
10 as shown in Figure 5. The warble
rate is the oscillator frequency divided by 640. In a typical application, an 8-kHz oscillator produces
BOO-Hz and lOOO-Hz tones warbling
at 12.5 Hz.
The tone ringer output is enabled
by the threshold detector when a
ringing signal greater than 35 Vrms
is applied at tip and ring. The ringing signal level is measured by monitoring the voltage across the external resistor at the TRI terminal.
When the average voltage across
this resistor exceeds a threshold level, the output buffer commences
driving the piezo element at the
TRO terminal. The'additional cur-

rent drawn from the line to drive the
piezo also flows through the external resistor at TRI. Therefore, the
voltage across this resistor increases
when the output is enabled. Increasing the voltage applied to the threshold detector creates hysteresis between the turn-on and turn-offlevels
that ensures clean on/off transitions.
DESCRIPTION
The MC34010 ETC incorporates
300 bipolar transistors and 520 r"L
gates on a 125x 146mil die. The chip
is fabricated using a two-layer metal, Linear/I2L process and packaged in a 40-pin plastic package.
Combining a dialer, speech network,
and tone ringer on a single chip represents a major step forward in the
modernization and cost reduction of
analog telephones. 0

Reprinted from Telecommunications MagaZine, April 1984, Volume 18, Number 4, with permission from the publisher,
Horizon House-Microwave Inc., Dedham, Mass.

3-47

AN957

®

MOTOROLA

Interfacing The Speakerphone To The
MC34010/11/13 Speech Networks
Prepared by
Dennis Morgan
Bipolar Analog IC Division

•

INTRODUCTION
Interfacing the MC34018 speakerphone circuit to the
MC34010 series of telephone circuits is described in this
application note. The series includes the MC34010,
MC34011, MC34013, and the newer "A" version of each
of those. The interface is applicable to existing designs,
as well as to new designs.

FUNCTIONAL REQUIREMENTS
Figure 1 shows the basic MC3401 0 telephone circuit as
described in the data sheet. It is a completely functional
telephone meant for use with a handset, and provides
the additional function of a microprocessor interface for
the DTMF dialing function. The MC34011 does not have
the microprocessor interface, but otherwise is identical,
including the pin numbers. The MC34013 has the same
speech network, dialer, and line interface circuit as the
MC34010, but does not have the microprocessor interface
or the tone ringer. Except for a minor difference between
the speech networks of the "A" version parts and the
"non-A" parts, the interface to the speakerphone circuit
is virtually the same for all 6 parts.
Figure 2 shows the basic MC34018 speakerphone circuit as described in the data sheet. It is NOT a complete
telephone, but provides only the speakerphone functions.
It requires a speech network, such as the MC34010, to
transfer the speech signals to/from the Tip & Ring lines,
and to provide the required supply voltage. The four external connections - transmit output, receive input, dc
line input, and chip select - are the points which must
be interfaced to the speech network.
In the following text, only the MC34010 interface will
be described. The interface to the other parts is the same
except where noted.
When combining a speech network which operates a
handset, with a speakerphone circuit, certain changes are
required in the circuit operation when switching between
the handset mode and the speakerphone mode, and additionally when the dialing mode is in effect. The four
modes to be considered are: 1) using the handset for
speech, 2) using the speakerphone for speech, 3) dialing
in the handset mode, and 4) dialing in the speakerphone

3-48

mode. The requirements are summarized in the following
table:

Mode

MC34018

Vir

Handset
Mike

Handset·Speech
Spkrphone Speech
Handset-Dialing
Spkrphone Dialing

Unpowered
Powered
Unpowered
Powered

low
High
low
High

live
Dead
Dead
Dead

Speakerphone
Mike

N/A
live
N/A
Dead

Since the entire circuit is to be powered by the phone
line, the speakerphone circuit is powered up only when
it is to be used since it uses a portion ofthe loop current,
(a significant portion on long loops). The MC34010, however, must be powered all the time since it is the interface
to the phone line. The Vir voltage mentioned in the table
is the voltage across the resistor at the LR pin of the
MC3401 0, which sets the dc characteristics of the circuit.
By increasing that resistor, the dc supply voltage (and the
voltage at Tip & Ring) will be increased in the speakerphone modes, where additional power is required.
The handset mike is to be functional only in the handset-speech mode. If it were functional in the speakerphone-speech mode, system oscillations and/or additional echoes could occur. Disabling the microphone is
accomplished by activating the MM (Mike Mute) pin on
the MC34010. On the MC34010A, activating the MM pin
results in disabling the transmit amplifier, so in that case,
a transistor is added to the microphone circuit as the
means to disable it. In both dialing modes, muting is automatic whenever the dialer is activated, so the DTMF
tones are not distorted by sounds entering the
microphone.
The speakerphone mike is listed as N/A in the handset
modes since the MC34018 circuit is unpowered, effectively disabling the mike. In the speakerphone dialing
mode it must be non-functional for the same reason as
mentioned above. That is accomplished by the fact that
the MC3401 0 (and MC3401 OAt transmit amplifier is inoperative when its DTMF dialer is activated.

AN957
TIP
TO
TONE RINGER
CIRCUIT

C7

R5

C8

R7

R6

CIO
RING

RM
RS
SIDETONE
AMP
STA
MT

-=

V+

J

MIKE
Cll

Rl0
Cll

~

lC

TXO

Rll
O.6V

TXI

C5
C4

Rll

TXl

MIC
MT

' - - - - - - - - - Q MM

MT

Rl

#

C3

DIALER
lOGIC
&
DTMF
GENERATOR

MICROPROCESSOR
INTERFACE

..

KEYPAD

\ ••••• I
"p INTERFACE
MC340l0IAIONlY

Figure 1. Basic MC34010 Type Telephone

3-49

V-

MC34010 TYPE
SPEECH NETWORK

II

»

z

CD
(71

.......

TRANSMIT
OUTPUT

VCC

•

VB

RECEIVE
INPUT

VB

'F
0.05

1

2k

01

-1~
0.068
Cot)
I

U1

Q

II

2J

Ok

0.068
0.1

Figure 2. MC34018 Speakerphone Circuit

AN957
CIRCUIT DESCRIPTION
SWITCHING ARRANGEMENT
Figure 3 indicates the switching arrangement for going
off-hook in either the handset mode or speakerphone
mode, and for switching between them. S1 (a two pole
switch) is the normal hook switch activated by lifting the
handset. S2 (a two pole switch) is a manually operated
switch which activates the speakerphone.
Whenever the handset is off-hook, and S2 is in the off
position, power from Tip & Ring is applied to the
MC34010 through the diode bridge and S1A. S1B's position is of no consequence in this mode. Should S2 be
switched on while the handset is off-hook, power is then
applied to the speakerphone IC through S2B. However,

since S1B is open, the MC34018's CS pin (Chip Select) is
taken high through R33, disabling the IC.
Anytime the handset is on-hook, and S2 is on (both
poles closed), power is applied to both the MC34010 and
the MC34018. Since S1B is closed, CS is taken low, enabling the speakerphone circuit. Anytime the handset is
taken off-hook the circuit will revert back to the handset
mode.
The 1.0 Henry inductor isolates the speech signals at
Tip & Ring from the V + pin of the MC34018, preventing
an oscillatory loop from forming. The diode bridge, 82,
is added for the tone ringer circuit of the MC34010(A), or
MC34011(A), to keep the switches S1 and S2 from requiring 3 poles each.

TO
TONE RINGER
CIRCUIT

TIP

R5

0--+-------.

.------'IM,,.-I. TO RECEIVE CIRCUIT

V+
Z1
RING 0--+-------'

MC3401O.A
SERIES
SPEECH NETWORK

V-

S18
Note.
S1 == Hookswltch
(Shown On-Hook)
52 == Speakerphone On/Off

Switch

R33
l---'"........"T"'-4~-.......- - -......-~-,-,.-l SPEAKERPHONE
V+

V-

Figure 6. Microphone Muting -

3-53

MC34010 Series

AN957
In Figure 7, in the handset mode, Sl B is open, T3 is on,
and the microphone bias current flows through the MIC
pin. In the speakerphone mode, Sl B is closed, turning off
T3, disabling the microphone. T3 is required for disabling
the microphone with the "A" series speech networks
since the transmit amplifier is disabled when the MM pin
is taken high.
In both the "non-A" and the "A" version circuits, the
handset microphones are muted during dialing due to
the fact that the MIC pin is opened by the dialer circuit.

-SPEECH SIGNALS
Referring to the complete schematics (Figures 8, 9, 10,

•

and 11) the receive signals coming in on Tip & Ring are
sent to the handset receiver (at RXO) and to the speakerphone circuit's "receive input" path by the MC34010's
hybrid function. It is not necessary to mute the handset
receiver during speakerphone operation.
The transmit signals from the handset microphone are
put onto the Tip & Ring lines through the MC3401 O's hybrid function, with a gain determined by resistors
R27-R30. In the speakerphone mode, the transmit output
signals (at TXO of the MC34018) are attenuated by R35
before being applied to the MC34010's transmit amplifier.
The level of the speakerphone transmit signals at Tip &
Ring can be adjusted by varying R35.

TO
TONE RINGER
CIRCUIT
RS

TIP

TO RECEIVE CIRCUIT
V+

Zl
RING
T1

TO OTHER
CIRCUITRY
PER FIGURE 1

BP
VR
'R

190

3k

MC34010
SERIES
SPEECH
NETWORK

1K

-=

Note:

S 1 = Hookswitch
82

=

(Shown On~Hookl
Speakerphone
On/Off Switch

MIKE
MIC
3K

v-

R36

47 k
'-<~~CT'-4""'_""'

R33

_ _---+-----:v:-+-l

vFigure 7. Microphone Muting -

3-54

MC34010A Series

MC34018
SPEAKERPHONE

AN957

KEYPAD
Rll

.

9
0 #

Rl
R2
R3
R4

DP

'f5
MC34010 ONLY

MS
A+
110

DO

a:

CRI
CR2
MC34010111

C7

MM
MIC
AGC

CS

SKG

TXI

RRX

C9
SKO

•

R32

V+
CP2

GND

R35
MC34010JII and MC34018
COMPONENT VALUES

Rl -30 k
R2 -91 k
R3 -3.3 k
R4 -1 M
RS -4.7k
RS -1 M
R7 -100 k
R8 -4.7 k
R9 -4.3k
Rl0- 200 k
Rll- 24 k
R12-20 k
R13-18 k
R14- 2 k
R1S-l.B k
R1S-200 k
R17-1 k
R1B-l00
R19- 390
R20- 200 k
R21-SSk
R22-1S0 k
R23-S6k
R24-1.S k
R2S-1.S k
R26- 6.8 k
R27- 270
R28-200 k
R29-4.7 k
R30-4.7 k
R31-1.Sk
R32-S1 k
R33-47 k
R34- 36
R3S-33 k

L1 -

Cl -0.1
C2 -0.068
C3 -2.2p.F
C4 - 2.2p.F
CS -0.1
C6 -47p.F
C7 -4.7p.F
C8 - 0.068
C9 -47p.F
Cl0-lp.F
Cll - O.OS
C12 -47p.F
CI3-47p.F
CI4-4.7p.F
C1S-4.7p.F
CI6-0.0S
C17 -

1 Hry, < 100 II

ZI-18V
Z2 - 4.7 V
Z3-30V
Z4-7V
01, 02 - 1 N4001
Tl - 2N4126
T2 - 2N2222A
Bl B2 -

lN4004's
1N4004's

51 -

OPOT (Hookswitch)

52 -

DPST (Speakerphone switch)

0,01

C1B- O.OS
CI9-0.1
C20 -1000 p.F
C21-1p.F
C22 - 4.7 p.F
C23-620 pF
C24-0.01
C2S-0.01p.F
C26 - 2.2p.F
C27 -0.1
C28 - O.OS
C29-0.0S
C30-1p.F, NP
C31-0.1
C32-0.1
C33 -100 pF
C34 -100 pF
C3S-1p.F
C36-0.1

Figure 8. HandsetiHandsfree System Using the MC34010/11 and MC34018

3-55

n

Handset R'cvr - 300
Handset Mike - Electret
Spkr'phone Speaker - 25 H, 0.3 W
Spkr'phone Mike - Electret

1

AN957

KEYPAD
23

Rl

R2

Rll

R3
• 0

(;

OP

TO
MS
A+
VO
DO

a:

500 kHz

RESONATOR

CRI

MC3401S

..

no
Rli

CR2
MC34010AlllA

R5 C19
C16

RXI

RLO
C7

v+

CP2

cs

SKG

RRX

C9
SKO

GND

R35

MC34010Al11A and MC34018

COMPONENT VALUES
Rl - 30 k
R2 - 91 k
R3 -3.3k
R4 - I M
R5 -4.7k
R6 -1 M
R7 - 100 k
R8 -4.7 k
R9 -4.3 k
Rl0- 200 k
Rll -24k
R12-20k
Rl3-18 k
R14- 2 k
R15- 1.8 k
R16- 200 k
R17 - 3 k
R18-100
R19- 390
R20- 200 k
R21 - 56 k
R22- 150 k
R23-56k
R24- 1.5 k
R25 - 1.5 k
R26- 6.8 k
R27 - 270
R28- 200 k
R29-4.7 k
R30 -4.7 k
R31 - I k
R33 -47 k
R34- 36
R35-33k
R36 - 3 k

Cl -0.1
C2 - 0.068
C3 - 2.2 "F
C4 - 2.2 "F
C5 -0.1
C6 -47 "F
C7 -4.7 "F
C8 - 0.068
C9 -47 "F
Cl0-1 "F
Cll -0.05
C12-47 "F
C13-47 "F
C14-4.7 "F
C15-4.7 "F
C16-0.05
C17 -0.01
C18-0.05
CI9-0.1
C20- 1000 "F
C21- I "F
C22 -4.7 "F
C23-620 pF
C24-0.1
C25-2.2 "F
C26-0.01
C27-0.1
C28-0.05
C29-0.05
C30- I "F, NP
C31 -0.1
C32 -0.1
C33 - 100 pF
C34-100 pF
C35- I "F
C36-0.1

11 -

I Hry, < 100 n

Z1-18V
Z2-4.7V
Z3-30V
Z4-7V
01,02 -

lN4001

TI-2N4126
T2, T3 - 2N2222A
Bl B2 -

lN40Q4's
I N4004's

51 52 -

DPOT IHookswitch)
OPST (Speakerphone switch)

Handset R'cvr - 300 n
Handset Mike - Electret
Spkr'phone Speaker - 25 n, 0.3 W
Spkr'phone Mike - Electret

Figure 9. Handset/Handsfree System Using the MC34010Al11A and MC34018

3-56

AN957
TiP

KEYPAD
I 2
4 5
7 8
0 #

.

RI
R2
R3

C3

vMC34013
VR
RXO
500 kHz

RESONATOR:hC33J:
C4

RLI
RXI

RM

CJ

CR2

R5 CI9
Rtl

RXI
CRI

CAL

C34J:

•

CI6
RLO

C)

V+

STA
R32
MM
MIC
AGC

CP2

CS

SKG

TXI

RRX

C9

1

TXO

SKO
GND

R35

MC34013 and MC3401S

COMPONENT VALUES
Rl - 30 k
R2 - 91 k
R3 - 3.3 k
R4 - I M
RS - 4.7 k
R6 - I M
R7 - 100 k
RS -4.7 k
R9 -4.3 k
Rl0- 200 k
R11-24k
R12-20k
R13- IS k
R14- 2 k
R17- I k
R1S- 100
R19- 390
R20-S6k
R21 - 200 k
R22-1S0k
R23-S6k
R24- 1.S k
R2S- 1.S k
R27 - 270
R2S - 200 k
R29-4.7 k
R30-4.7 k
R31 - 1.5 k
R32-S1 k
R33 - 47 k
R34- 36
R3S-33 k

Cl -0.1
C2 - 0.066
C3 - 2.2 "F
C4 - 2.2 "F
CS -0.1
C6 - 47 "F
C7 -4.7 "F
CS - 0.06S
C9 -47 "F
Cl0-l "F
Cll - O.OS
C12-47 "F
C13-47 "F
C14-4.7 "F
C1S-4.7 "F
C16- O.OS
C17 -0.01
C1S-0.0S
C19-0.1
C20 - 1000 "F
C24-0.1
C2S - 2.2 "F
C26 - om
C27 -0.1
C2S - 0.05
C29-0.0S
C31 -0.1
C32-0.1
C33 - 100 pF
C34 - 100 pF
C3S- I "F
C36 - 0.1

L1 -

I Hry. < 100 Il

Z1 -1SV
Z4-7V
01.02 -

lN4001

Tl - 2N4126
T2 - 2N2222A
82 -

I N4004's

51 -

OPOT (Hookswitch)

52

~

DPST (Speakerphone switch)

Figure 10, HandsetlHandsfree System Using the MC34013 and MC34018

3-57

n

Handset R' cvr - 300
Handset Mike - Electret
Spkr'phone Speaker - 25 H, 0.3 W
Spkr'phone Mike - Electret

AN957
TIP
KEYPAD
2
Rll
78
• 0 /I

Rl
R2
R3

MC34()1JA
RXOf----h--I---+----j---,
500kHz

RESONATOR
CRl

CR2

•

MM
C7

V+

CP2
SKG
C9

f SKO

CS
RRX
GND

S2B

R35

MC34013A and MC3401a
COMPONENT VALUES

Rl - 30 k
R2 -91 k
R3 -3.3k
R4 -1 M
R5 - 4.7 k
R6 -1 M
R7 - 100 k
RS - 4.7 k
R9 -4.3 k
Rl0-200 k
R11-24k
R12 - 20 k
R13- 1S k
R14- 2 k
R17 - 3 k
R1S- 100
R19 - 390
R20-56k
R21 -200 k
R22 - 150 k
R23-56k
R24- 1.S k
R25- 1.5 k
R27- 270
R2S-200 k
R29-4.7k
R30-4.7 k
R31 - 1 k
R33 - 4.7 k
R34- 36
R3S-33k
R36-3 k

Ll-l Hry, < lOOn

Cl -0.1
C2 - 0.06S
C3 - 2.2/LF
C4 - 2.2/LF
C5 -0.1
C6 -47/LF
C7 - 4.7 /LF
CS - 0.06S
C9 -47/LF
Cl0- 1 /LF
Cll -O.OS
C12- 47 /LF
C13-47 "F
C14-4.7 "F
C1S-4.7 "F
C1S - 0.05
C17 - 0.01
C1S- 0.05
C19-0.1
C20 - 1000 /LF
C24-0.1
C2S- 2.2/LF
C26-0.01
C27 - 0.1
C28- O.OS
C29-0.0S
C31 -0.1
C32-0.1
C33 - 100 pF
C34 - 100 pF
C3S- 1 "F
C36- 0.1

Z1-1SV
Z4-7V
Dl, D2 -

lN4001

Tl - 2N4126
T2, T3 - 2N2222A
82 -

1N4004's

S1 -

DPDT (Hookswitch)

S2 -

DPST (Speakerphone switch)

Handset R'cvr Handset Mike -

n

300
Electret

Spkr'phone Speaker Spkr'phone Mike -

Figure 11. HandsetiHandsfree System Using the MC34013A and MC34018

3-58

2S n, 0.3 W

Electret

AN957
CONCLUSION

REFERENCES

Interfacing the MC34018 speakerphone circuit to the
MC34010 series of speech networks has been shown to
be simple and straightforward. The interface requires the
addition of 2 diodes, 5 resistors, either 1 or 2 transistors
(depending on the speech network), and one diode bridge
for the tone ringer circuit in the MC34010(A) and the
MC34011 (A). Any existing MC34010 type circuit can be
easily modified to accept the speakerphone circuit.

MC34010 Data Sheet, Dec. 1983, Motorola, Inc.
MC34010A Data Sheet, May, 1985, Motorola, Inc.
MC34013 Data Sheet, Nov. 1983, Motorola, Inc.
MC34013A Data Sheet, Feb. 1985, Motorola, Inc.
MC34018 Data Sheet, Apr. 1985, Motorola, Inc.

i

~

3-59

AN958

®

MOTOROLA

Transmit Gain Adjustments
For The MC34014 Speech Network
By
Scott Bader and Dennis Morgan
Bipolar Analog IC Division

INTRODUCTION

•

The MC34014 telephone speech network provides for
direct connection to an electret microphone and to Tip
and Ring. In between, the circuit provides gain, drive capability, and determination of the ac impedance for compatability with the telephone lines. Since different microphones have different sensitivity levels, different gain
levels are required from the microphone to the Tip and
Ring lines. This application note will discuss how to
change the gain level to suit a particular microphone
while not affecting the other circuit parameters.

CIRCUIT DESCRIPTION
Refer to Figure 1. The microphone is assumed to be an
electret type, characterized by a high dynamic impedance. It is therefore considered to be an ac current source
rather than a voltage source. If the microphone used has
a dynamic impedance which is not high (compared to
RS), then the microphone must be modeled as a current
source paralleled by its dynamic impedance. That impedance value must then be considered to be in parallel with
RS in the following equations. The T x amplifier has a fixed
gain of - 20, and the EO amplifier gain varies from 0.25
to 0.75, depending on the loop current. ZL is the line
impedance. The transmit gain is defined as V + Ilmic and
is equal to:
V+
Imic

R6 x ZL x ATX
(1 + RijlRA)R9 + (ATX) (AEQ) (ZU

where ATX = gain of the transmit amplifier (20 VN)
AEO = gain of the equalization amp. (0.25 to
0.75 VN)
RA = Rall10 kfl (10 kfl = input impedance
of Tx amp.)
The ac impedance of the circuit is defined as:
Zac =

R9 (1 + RijlRA)
(ATX) (AEQ)

The receive gain (see data sheet for the equivalent circuit) is defined as:
Grx =

R4 + (XCIIR2) (AEQ) (ATXO) (ASTA) x R4
R1
((XCIIR2) + R3) (1 + R6/RA) x R2

As can be seen from the above equations, changing R6
whlle maintaining the RijlRA ratio constant will result in
a transmit gain change (proportional to R6) but will not
affect the other parameters. For example, increasing RS
and R6 by a factor of 3 will increase the transmit gain by
=10 dB.
Using the above procedure to increase the transmit
gain results in increasing RS, which supplies the bias current to the microphone. If the higher value of Ra results
in insufficient bias voltage at the microphone, then the
alternate biasing scheme of Figure 2 should be used.

v+

50IL F

J

Figure 2. Alternate Biasing Scheme for
Higher Voltage Microphones

Figure 1. MC34014 Transmit Section

3-60

AN958
TEST RESULTS

CONCLUSION

Tests were conducted with a Primo EM-95A microphone. having a sensitivity of - 53 dB ± 3 dB (0 dB = 1
V/",barl. and a Hosiden KUC2123 microphone which has
a sensitivity of -60 dB ±3 dB. The test circuit is shown
in Figure 3. The tests consisted of applying a constant
sound level to the microphones. and measuring the output at VCO. while Simulating line lengths of 0-21 Kfeet.
The outputs of the two circuits were nearly identical at
all line lengths.

Although the designs of the various parameters (transmit gain. receive gain. ac impedance. etc.) ofthe MC34014
speech network are not mutually exclusive due to the
commonality of various components. it is possible to adjust the transmit gain independently to suit a particular
microphone.
For further information on the MC34014 speech network. refer to the data sheet.

200

47

TXO

MIKE
RS

LR

0.05
LC

RS

MC34014
EO

V+

2.4 k

':'

0.2

TXI

150 k

LOOP
CURRENT

V+

MIC
VR

~

2/LF

2.4 k

VR

STA

~

30 /LF

VDD

RXI

~

RXO

M'f
RMT

V-

MS
TI

}

DIALER
INTERFACE

':'

For Primo EM-95A microphone RS = 500 n. RS = 10 k
For Hosiden KUC2123 microphone RS = 1.5 k. RS = 30 k
Figure 3. Microphone Gain Test Circuit

3-61

•

AN959

@ MOTOROLA
A Speakerphone
With Receive Idle Mode
. By
Dennis Welty and Dennis Morgan
Bipolar Analog IC Division

•

INTRODUCTION

CIRCUIT DESCRIPTION

The MC34018 speakerphone system operates on the
principle of comparing the transmit and receive signals
to determine which is stronger, and then switching the
circuit into that mode. Under conditions where noise
from the telephone line (in the receive path) exceeds
the background noise in the transmit path, the speakerphone will switch easily, or even lock, into the receive
mode. Under these conditions the conversation will
sound "dead" to the party at the far-end. It will also be
more difficult for the near-end party to activate the
transmit channel since the transmit detection is at the
output of the transmit attenuator, which will be at maximum attenuation during this time. The addition of a
receive idle mode can alleviate this problem by ensuring that the transmit and receive gains will be approximately equal when no voice signals are present. This
allows the far-end party to hear ambient noises, and
also increases the sensitivity to transmit signals.

The additional circuitry is shown in Figure 1. The receive signal normally applied to RXI also drives XDI
through a 2.7 kfl resistor and a 0.1 JLF capacitor. XDC is
connected to VLC through the NPN and PNP emitter followers. When voice signals in the receive channel exceed
the background noise by 4.6 dB, XDC switches high and
turns off the PNP transistor (the 4.6 dB threshold is built
into the MC34018). The voltage at VLC is then determined
by the volume control potentiometer. When voice signals
are no longer present, XDC decays to 0.5 VB and turns
on the emitter followers. The voltage at VLC is now determined by the voltage at XDC. By decreasing the VLC
voltage with the emitter followers the transmit and receive gains are adjusted to produce a receive-idle mode.
A peak detector using an external voltage comparator
and diode is required to hold the receive attenuator fully
on (out of the idle mode) when constant level signals,
such as dial tone, are intentionally presented to the re-

MC34018

XDI

MCO
10

XDC

13

VLC

23

VB

0.1;;:
2.7k

~

10 k
2.7k
0.1

1M
~

r:

L--

mum
91k
~

10f

16

20 k

....
...
lN4150

2N2907

24k

-=

DC
SUPPLY

1

1000

51 k
VOLUME

51 k

27

0.1

470 k

"pt
~
~oo

-=""=-=

20

~ ~

J

RXI

V+

VCC

21

24

~

10k

.-.8~
""" +

112
LM393'
OR
EQUIV.

'SEE LM193 DATA SHEET.

Figure 1. Receive-Idle Circuit

3-62

1

4

0.1

2k
3

47k

-=

1-=

0.1

~

RECEIVE
SIGNAL

AN959
ceive channel. When the receive signal at the receive input exceeds the threshold on the comparator (typically
20 mV) the peak detector charges the capacitor at XDC
which prevents the speakerphone from relaxing to the
idle mode. The PNP transistor is turned off and the voltage at VLC is then determined by the volume control
potentiometer. Under these conditions the speakerphone
will be in the receive mode.
The sensitivity threshold of the voice detector circuitry
can be changed by applying a dc current to XDI. The
threshold current (nominally 250 nA) also prevents XDC
from switching sporadically in quiet signal conditions.
The threshold current is determined by the 1 Megohm
resistor between XDI and the 10 k0/91 kfl divider refer-

enced to VB. Whenever receive signal currents exceed
the threshold current by 4.6 dB, the voice detector will
respond and allow XDC to switch high.

CONCLUSION
The receive-idle mode is simple to implement, and improves the performance of the speakerphone system by
allowing noise rejection in both the receive and transmit
channels. The voice-switching function operates only on
valid speech, and ignores background noises.

REFERENCES
MC34018 data sheet, Motorola, 1985
LM193 data sheet, Motorola

•

3-63

®

AN960
MOTOROLA

Equalization of DTMF Signals
Using the MC34014
by
Scott Bader and Dennis Morgan
Bipolar Analog IC Division

INTRODUCTION

•

This application note will describe how to obtain equalization (line length compensation) of the DTMF dialing
tones using the MC34014 speech network. While the
MC34014 does not have an internal dialer, it has the interface for a dialer so as to provide the means for putting
the DTMF tones onto the Tip & Ring lines. The Equalization amplifier, whose gain varies with loop current, was
meant primarily to equalize the speech signals. However,
by adding one resistor, it can be used to equalize the
DTMF signals as well.

CIRCUIT DESCRIPTION
Referring to Figure 1, the gain ofthe equalization amplifier varies with loop current as it is a function of the
voltage at the LR pin (Pin 13). The gain varies from a
minimum of -12 dB at low loop currents (long line), to
- 2.5 dB at high loop currents (short line). The output at
EO (Pin 6) is in phase with the signals going out onto Tip
& Ring, but is out of phase with the DTMF input signals
from the dialer at R7 (see Figure 2). Because of the outof-phase relationship, the signal at EO can be used to
partially cancel the signals at the Tone Input (Pin 16). The
addition of resistor Rl0 provides the path for this function, with the result that the DTMF gain increases as loop
current decreases.
-2.0
-3.0

1

-4.0

I

-s.o
@-s.o

Because the typical telephone line is not purely resistive, there will be a phase shift of other than 1800 from
the DTMF dialer to Tip & Ring in most applications. For
this reason, the values of Rl0 and R7 will have to be
adjusted slightlY from those in the graphs to compensate
for the phase shift.
The MC34014 data sheet mentions that a dc bias current of 20-50 /LA is required into Pin 16 in order to bias
the DTMF amplifier. The addition of R10 will provide the
bias current from the EO output for most applications,
in which case it may be desirable to ac couple the dialer
to R7 with a 0.5 /LF capacitor. Excessive bias current will
result in clipping of the signals at Tip & Ring. If just the
addition of Rl0 results in excessive bias current, then
the EO output should be ac coupled to Rl0 with a 0.5
/LF capacitor, and the bias current supplied either from
the dialer or from an additional resistor as shown in
Figure 5.

J
I

~-8.0

~-9.0

I

'" -10
."
-11
-12

The DTMF gain values indicated in Figures 3 and 4 is
the gain from the tone dialer (input at R7) to the Tip &
Ring lines terminated with a 600 ohm resistor. Figure 3
indicates the gain CHANGE (as the loop current is varied
from 60 to 20 mAl versus different values of Rl0. The
gain change is a function of Rl0, and independent of R7
Figure 4 indicates the DTMF gain versus R7 for different
values of Rl0 at a loop current of 20 mA.

For further information on the MC34014, refer to its'
data sheet.

I

l2
+ -7.0

Because the addition of Rl 0 cancels some of the signal
going into Pin 16, resistor R7 must be decreased in order
to restore the overall gain from the dialer to Tip & Ring.

./
0.2

o.s

1.0

1.4
VLR IVOLTS)

1.8

2.2

2.S

Figure 1, Equalization Amplifier Gain

3-64

AN960
EOUALIZATION
AMPLIFIER

EO

VOU!

r---'-~~---4~.ro

TIP&RING
Rl0
DTMF
INPUT
FROM
TONE DIALER

R7

TI
16

LA
13
3.75 k

1.25 k

47

MT
50

1.25 k
TO V-{

- -

17

':'

':'

MC34014
V- 10

•

Figure 2. DTMF Driver
14

5

4

""'" ""'"

3

-........
.......

r--r--r--

,
.............

2

-

"""- ..........

10

~
~
........

::::s: ~

15

\--

20

30

25

,.=>300

00

r--. r-...

=-- r:::-

I

-2
8

10

12

Rl0-k!!

Figure 3. Gain Change

14

16
R7 - k!l

18

-

Figure 4. DTMF Gain

75 k
DTMF
0.5
R7
INPUT ~r-JVlJ\-t-TI¢

.......

MC34014

Rl0
0.5
EO

Figure 5. Alternate Biasing

3-65

r--

~~

/'"

1--

10

Rl0 =

Rl0 = 12 k/'. ~ ~
...........
=15:/
= 20 k
= 30 k ....
ILOOP = 20mA

-r--

_ ILOOP VARIED FROM
60 TO 20 mA

'-

~

r-r--

1

o

12

r-:::::

20

22

®

EB112

MOTOROLA
THE APPLICATION OF A TELEPHONE TONE RINGER AS A RING DETECTOR
By Tanya Tussing and Glen Zoorner
Telecommunication Applications
Austin, Texas

Telephone ringers are driven by high voltage, low frequency ac signals which are superimposed on the 48 volt dc tipring feed voltage. An electronic ring detector must sense the
presence of an ac signal on the line and produce a dielectrically isolated logic level to the system processor. To isolate
the line from the system, an on-chip piezoelectric driver

drives the LED of an optocoupler. A 1 f.'F capacitor filters
the transistor output of the optocoupler, creating a solid
logic 0 when a ring signal is present. Figure 1 depicts the
schematic of the ring detector. The peripheral components
around the MC34012 set trigger levels and the ringing impedance signature for FCC Part 68 compliance.

•
0.471'F

TIp

4.7k

....----lII--...I\N\r-----2-/

5V

250 V
Non-Polar

Ring

1000 pF

To
Microprocessor
10k

180 k
4N26
Optocoupler
FIGURE 1 -

Ring Detector Schematic

3-66

®

EB113

MOTOROLA
THE MC145409 PULSE DIALER APPLICATION CIRCUIT
by Roger Taylor
Telecommunication Applications
Austin, Texas

cleared during a predigital pause, after which outpulsing
commences. The receiver is muted during outpulsing.
The mute and outpulsing functions are accomplished
through the circuitry contairting transistors Q2 through Q5.
The mute and outpulsing pins (12 and 18 respectively) are in
an open drain configuration, so transistors Q2 and Q3 are
forward biased by connecting their bases to the supply
through pull-up resistors R2 and R3. Muting occurs when pin
12 pulls to VSS. Transistor Q2 turns off, terminating current
flow through R7. Transistor Q5 turns off as the base and
emitter voltages equalize, muting the receiver.
Outpulsing is accomplished in a similar manner. A pulse is
created when pin 18 pulls to VSS. Transistor Q3 turns off,
stopping current flow through R5. The base and emitter
voltages of Q4 equalize through R4, shutting the transistor
off, interrupting current flow through the speech network,
thereby creating a pulse on the phone line.
During a key depression, the MCI45409 outputs a tone
signal at Pin 2. This signal drives the base of 06, which in
turn modulates the voltage at the receiver, creating an audible tone at I kilohertz for 10 pulse per second or 2 kilohertz
for 20 pulse per second. The volume of this tone is controlled
by R8. An increase in R8 corresponds to a decrease in tone
level at the receiver.

The purpose of this document is to describe a circuit for interfacing the MC I 45409 pulse dialer with a telephone system.
The MCI45409 is a monolithic CMOS integrated circuit
which converts 2 of 7 keyboard inputs into pulse signals that
simulate a rotary telephone dialer. It uses an inexpensive RC
oscillator, operates directly off of telephone line supply, and
consumes only microamperes of current when not outpulsing.
When off-hook, power is supplied through a constant current source consisting of QI, RI, 05,06, and R9. To keep
the circuit's power consumption low, 05 and 06 are partially
forward biased. As line voltage increases, voltage applied to
the MCI45409 increases as 05 and 06 become more forward
biased necessitating zener diode, Z2, to provide adequate
regulation. On-hook power for memory retention is supplied
through RIO. Diode, 07, is required to keep the on-hook
current below the Bell specification of five microamperes
maximum.
When off-hook, the oscillator is enabled when a valid key
input is detected. The MC145409 senses key depressions,
verifies that a single key is depressed, and stores the key's
code in on-chip memory. If the first key depressed is a or #,
memory redial is initiated (provided the receiver has been
on-hook for the minimum time). Otherwise, memory is

*

3-67

•

EB113

TELEPHONE DIALER APPLICATION CIRCUIT

Grn

R10

05

0:

06

C'O

a::

0:
01

'"a::

9

'"a::U

0
0

C'O

U

a::

>

C1
18

Z2

'"a::

OPL
12
MO

TSO
6
VSS
4

3

10

CO[2

ORS

COL 1

MBR 11

co

a::

C

OHIT
Typical
"500" Type
Speech

17

Network

S2

R1=1.4k
R2=470 k
R3=330 k
R4= 100 k
R5=3 k
R6= 100 k
R7=3 k
R8= 20 k

R9=560 k
R10= 10 M
R11=2 M
R12=220 k
C1 =68 /,F low leakage
C2=390 pF

01-04= IN4004
05-07= IN914
08=IN4004
Zl=120V,IW
Z2=5 V, 500 mW

3·68

01 =2N5401
02= 2N5550
03= 2N5550
04=2N5401
05=2N5401
06= 2N5550

AN-731

@ MOTOROLA

Application Note

LOW-SPEED MODEM FUNDAMENTALS
Prepared by:
Garth Nash
Computer Systems Engineering

GENERAL
The MC6860 low-speed Modem can be used in many
different configurations. These include full duplex, half
duplex, simplex, automatic answering, automatic disconnect, originate only, answer only, answer/originate,
and others. Figure I illustrates the basic modem configuration used to evaluate the MC6860. An originate only and
an answer only modem design is used for evaluation, and
each section of the interface circuitry is dealt with in
this article.
The originate modem transmits on the low-frequency
channel (Mark 1270 Hz and Space 1070 Hz) and receives
on the high-frequency channel (Mark 2225 Hz and Space
2025 Hz). The answer modem transmits on the upper
channel and receives on the lower.
A buffer and duplexer as shown in Figure I provide
the modem interface to the transmission network while
the bandpas~ filter allows only the desired receive signals
to be seen by the limiter and demodulator.

MODULATOR - BUFFER
Mark/Space information that is presented to the Transmit Data input of the modem is converted to an FSK
signal for transmission. The modulator output is an approximated sinewave derived from a digital-to-analog converter within the MC6860. There are eight amplitude levels
per cycle. Each step has been optimized such that the

composite waveform has a maximum amount of signal
energy at the fundamental. Figure 2 shows the 1270 Hz
transmit carrier and Figure 3 gives its spectral distribution.
A nominal signal has the secant! harmonic attenuated to
-30 dB.
The modulator output impedance is typically 2 k ohms.
Loading this output with an impedance less than 100 k
ohms can produce harmonic distortion. Therefore, a buffer
amplifier is required to match impedances to the duplexer
and the telephone line. This buffer amplifier may be designed to also provide filtering if additional clean-up of
the transmitted signal is required.
The modulation spectrum for 300 bits per second using
an alternate Mark/Space data format is shown in Figure 4.
The amount of modulation or sideband energy that falls
in the adjacent channel is an item of concern in full duplex
operation. Under this condition both channels are operating
Simultaneously and all the adjacent channel energy that is
not balanced out in the duplexer feeds directly through
the bandpass filter and to the limiter. Excessive phase
jitter results if the received signal level is low enough to
approach that of the interference level at the limiter input.
For this reason, additional filtering of the modulator output may be required before it feeds to the duplexer on
those modem designs desiring wide dynamic ranges of
input signal levels.

Transmit

Data

Telephone
Line

Receive
Communications
Terminal

Data

Control

FIGURE 1 - Low-Speed Modem and Interconnections

3-69

AN731

passband of the receive filter and is further attenuated.
In full duplex operation, the second harmonic and the
modulation sidebands have about the same amount of
energy. If this undesired energy must be reduced, the
filter used to reduce the modulation sidebands will also
reduce the second harmonic. Phase jitter and bias distortion
inherent in the modulator is less than 3 MS.

Interference by the second harmonic is of concern in
the originate mode only. In this mode, the transmit signal
is in the low band and its second harmonic falls in or
near the passband of the return channel. In half duplex
operation, the transmit carrier is held at a constant
Mark (1270 Hz) while data is being received. The second
harmonic (2540 Hz), which is typically -30 dB or more
below the fundamental in amplitude, falls just outside the

•

.~

,
.""

g

E

'"ci

G

a.

«

>

0.2 ms/Div.

Time

FIGURE 2 - MOS Synthesized 1270·Hz Sine Wave

161617

Fundamental

Harmonics
Frequency

FIGURE 3 - Frequency Spectrum of MOS Sine Wave

3-70

AN731

27

•
2.0

..oi:'

8.

1.0

~c

w

900

1000

1100

1200

1300

1020

1400

1320
Frequency (Hz)

FIGURE 8 - Answer Bandpass Filter Characteristics

3-71

1500

II
l>
Z
~

Co)

...a.

r

1M

DT

: : } T O Data

1M

I -r

Transmit
Carrier

Voo VSS

T,ansm;t Data
Transmit Break

From
{
Terminal

I

Oat~inal

r :;-;;;----,I
I
____
....J
~I
I
I

Bandpass
Filter

O.01I' F

I
I

Receive
C.rrier

Ready

Break Release

I
I
I
I

Receive Break

Clear.to-Send

Co)
I

.....

N

Receive Data

Thr8s"ilOid

Enable Long Space
Disconnect
Enable-Space
Disconnect

I
I

Dei8ct

TST

I
I

O.01I'F

-=-

-=-

All other pins open.

I
I
I
I
I

MC6S60

To Terminal {

Coupla~

I

95.3k

Answer
Phone

I

+12 V

I

O.01I'F

I
619

Ring
~

SWiiCii
HOOk

-=

DH
DA

~
To CST Data Coupler

FIGURE 9 - Originate Modem

I
L

I

"'=

_____ ...1I

AN731

o

1170
Frequency (500 Hz/DiY.)

FIGURE 4 - Modulation Spectrum for Altarnat. Mark/Space

DUPLEXER
and

The duplexer is used to interface the modem with the
transmission media which is a telephone system in most
cases, through a data coupler. Since signal flow is bidirectional on the telephone line, the duplexer must allow
the received signal to pass on to the bandpass filters,
properly couple the transmitted signal onto the line, minimize the local transmit level at the bandpass filter input,
and properly terminate the transmission line. The diagram
of Figure 5 shows the various components of the duplexer
with A I, i\2, and A3 being the gain expressions of
importance.

The gain from the buffer output to the bandpass
filter

Buffer
Output

A2

=0=- ~; + (I + ~; ) ~

2 R2 = 1 + ~~
RI
Rl
2R2=RI +R2

R3

Rl

R2=RI

Telephone Line

A2~

::u~ ~ ~ +~ + R2) (~)
RI ~ RI
\R3 + R4

It is desired that A2 = 0, thus reducing the intermodulation
effects from the local modulator. With R3 = R4:

~

From

R3 = R4 = 600 ohms
Al = 0.5

r

+
R2

R4

With Rl = R2, the common mode characteristic of the
operational amplifier is used to balance out the local modulator at the bandpass filter input, i.e., A2 = O.
Since all impedances except the line impedance can be
accurately controlled, the degree of nulling A2 becomes a
function of the line impedance. The duplexer gain, A2, is
plotted versus line impedance variation from 200 ohms to
1000 ohms in Figure 6. A well-defined notch exists when
the line appears a purely resistive 600 ohms (the ideal
case). In practice the line impedance can have reactive as
well as resistive component variation, therefore the duo
plexer should be considered as providing approximately
-10 dB even though in many connections greater attenuation will be achieved.
The gain from the telephone line to the bandpass filter
input is given by

Line
Impedance

To Bandpass Filter

FIGURE 5 - Duplexer

The gain from the modulator output to the telephone
line is
R4
Al =R3+R4
where R4 is the line impedance and is considered to be
nominally 600 ohms resistive. Since the line must be
properly terminated, R3 must equal R4. Therefore:

A3 = I + R2 =2
Rl
when Rl = R2.

3-73

AN731
these conditions with bias distortion and excessive phase
jitter at the demodulator output resulting. Intersymbol
interference can be reduced by linearizing the phase
versus frequency transfer function. The slope of this transfer function is termed envelope delay and is determined by:

o
~

-10

~"

-20

r--.

..........

~

./'

V

I--

i\ /
\ II

~

~

:0 -30

"Eo

E -40

1
T _at/>
d -: t:.f 360 degfcycle
where at/> = change of phase in degrees
af = change of frequency in Hz

8
-50
200

300

400

500

600

700

800

Minimizing the distortion of the envelope delay curve
then minimizes the intersyrnbol interference. This is
relatively easy over the center 2/3 of the passband. However, keeping constant delay near the band edges is quite
difficult, if not impossible. For this reason, the optimum
bandwidth is not determined according to the data rate
but rather according to achievable linear phase characteristics. Bias distortion of one tenth of the bit period at
300 bps typically requires a -3 dB bandwidth of 450 Hz
to 500 Hz.
Bandpass filters for evaluating the MC6860 were designed to have approximately a 450 Hz, -3 dB bandwidth
with a Chebyschev response. The schematic for the answer
filter is found in Figure 7 and IS outlined for identification.
The analytical response of this filter using standard valued
components is tabulated in Table I. The -3 dB bandwidth
is calculated as 486 Hz and measured as 448 Hz. There is
approximately 0.7 dB ripple over the center 300 Hz of
the passband, with 0.4 ms envelope delay distortion, as
shown in Figure 8. This filter attenuates the local transmit
carrier of2225 Hz by -35 dB relative to the passband gain.
A similar schematic for the originate bandpass filter is
given in Figure 9. Its response approximates that of the
originate filter as seen in Table 2 and Figure 10. Attenuation of the 1270 Hz local transmit carrier is -43 dB
relative to the passband gain.
The envelope delay distortion for both of these filters
can be reduced by widening the passband, thus flattening
the envelope delay curve.

900 1000

R4, Resistive Line Impedance (Ohms)

FIGURE 6 - Common Mode Gain versus Une Impedance

•

BANDPASS FILTER
The purpose of the bandpass filter is to amplify the
received signal from the remote modem while rejecting
all other signals that may be present in the local modem or
on the telephone line. Interference which must be filtered
out has several possible sources. Each of these must be
considered and dealt with individually. Noise which is
coupled in through the transmission media is either impulsive or band limited (gaussian) white noise. Both of
these must be analyzed on a statistical basis. Discrete
interfering signals may also be coupled in through the
transmission media. However, the interfering signal of
prime importance comes from the local modulator and
will always exist in the half or full duplex modes.
Since the transmission media is lossy, the local transmit
carrier level will exceed the level of the received signal. For
this reason, the bandpass filter must have enough selectivity
to reject the local carrier to an acceptable level. Modems
that are designed for a wide dynamic range of input signal
levels (-15 dBm to -55 dBm) require better than 70 dB
rejection of interfering signals. Most of this rejection must
come from the selectivity in the bandpass filter.
Reducing the effects of band limited white noise is
accomplished by decreasing the bandwidth of the filter.
Determining the minimum bandwidth comes by investigating the received signal characteristics. The transmitted
data can be recovered from binary FSK by properly detecting the carrier and the first sidebands (first Bessel
function)l. With a data rate of 300 bits per second and a
data format of alternate Marks and Spaces, the first Bessel
function occurs at ±150 Hz from the carrier. All other
data formats have sidebands within the ±150 Hz limit.
A minimum bandwidth of 300 Hz is then required in the
bandpass filter.
The bandpass filter output is fed into an amplitude
limiter, therefore the amount of passband ripple is not a
critical parameter. An item of serious concern, however,
is the phase linearity over the passband. All frequency components that pass through the filter must be equally delayed
in time or jumbling and smearing of the data occurs. This
is known as intersymbol or interbit interference. Performance of the communication system is degraded under

UMITER-THRESHOLD DETECTOR
The demodulator in the MC6860 requires symmetrical
limiting of the received signal in order to produce equal
half-cycle periods. Each half-cycle period is measured in
reference to an accurate time base to determine if the
received frequency is a Mark or a Space. Non-symmetrical
limiting produces errors in the demodulation process, thus
degrading the system performance. Accurate limiting must
be achievable over the expected input dynamic range.
Such i.tems as maximum input level and input offset
voltage of the limiting device must be carefully considered.
Figure II shows the schematic for the limiter. The
effect of the input offset is reduced by placing equal
terminating resistors on both the inverting and noninverting outputs. An input coupling capacitor is used to
block any de bias coming from the output of the last
amplifier of the bandpass filter. The desired ae signal is
now properly centered about the input bias level of the

3-74

:J>
Z
.......

Co)

.....

./
1 M

1

:: }

1 M

To Data
Coup'er

-------,
15 k

Voo

VSS

Transmit

Transmit Break
From
{
Terminal

~r,;er

+~

C../
Rec.;ve
../

Data Terminal
Ready
Break Release

MC6860

I

r-

Carrier

T,"nsm;t Data

I

I
Bandp ass
F;lte,

I

I
I

Receive Break

Co)

~

To Terminal {

I
I
1

Clear-ta-Send

1.5 k

Receive Data
Threshold
Detect

Enable Long Space

Disconnect

I

Enable Space

Disconnect

TST

O.OlIJ.F

97.6 k

Answer

All other pins open.

I
I
0.01 I'FI
I

I

I

I

Phone

I
I
1

I
I

+12 V

I

Ring

~

SvVTtch
i=i"O"Ok

-=

I
-....... + f-----,
~ 2550
I
IL _ _ _ _ _ _ _

OH

DA

------~y------------/
To CeT Data Coupler

FIGURE 7 - Answer Modem

~~-----.

I
I
1

1

-----'

AN731
limiter and the maximum input dynamic range can now
be achieved. A 40 dB dynamic range can be achieved with
the limiter of Figure 11. Caution must be exercised in the
amount of loading placed upon the bandpass filter output
for distortion can result with large signal levels. An
isolation resistor placed in series with the limiter input
decreases the loading on the bandpass filter. Under maximum signallevel conditions the limiter should be operating
close to its upper input limit.
The output of the limiter is fed into the demodulator.

•

The threshold detector is used to determine if the input
signal to the limiter is above the maximum detectable
signal level of the modem. This is an amplitude measurement only, thus the period of the output is not critical. A
comparator is used with one side biased to the peak
amplitude of the desired minimum detectable signal level
at the bandpass filter output. When the signal level exceeds
the bias pOint, the comparator output goes low indicating
an acceptable signal level.

TABLE 1 - Answer Filter Tabulated Response
Node

TABLE 2 - Originate Filter Tabulated Response

Phase
Shift

Delay (msl
.11
.13
.18
.26
.45
1.15
2.31
2.81
2.81
2.38
1.94
1.67
1.54
1.50
1.49
1.48
1.46
1.44
1.41
1.41
1.46

Envelope

Frequency

Voltage

dB
Voltage

O.3000E+03
O.4000E+03
0.5000E+03
0.6000E+03
0.7000E+03
0.8000E+03
0.9000E+03
0.9250E+03
0.9500E+03
0.9750E+03
0.1000E+04
0.1025E+04
0.1050E+04
0.1075E+04

0.1175E+04
0.1200E+04
0.1225E+04
0.1250E+04
O.1275E+04

0.202E-Ol
0.576E-Ol
0.145E+00
0.354E+00
0.906E+00
O.267E+Ol
0.10IE+02
0.141 E+02
0.176E+02
0.194E+02
0.196E+02
0.194E+02
0.193E+02
0.195E+02
0.198E+02
0.201E+02
0.203E+02
0.204E+02
0.204E+02
0.204E+02
0.205E+02
0.207E+02

-33.883
-24.796
-16.770
-9.008
-.856
8.523
20.158
22.968
24.927
25.746
25.847
25.761
25.728
25.790
25.914
26.045
26.142
26.190
26.203
26.210
26.246
26.321

80.83
76.99
72.24
65.93
56.62
40.26
-1.03
-21.78
-47.11
-72.41
-93.83
-111.32
-126.37
-140.24
-153.70
-167.08
179.59
166.42
153.50
140.79
128.07
114.90

O.1300E+04

O.209E+02

26.410

100.71

1.58

0.1325E+04 0.209E+02
0.1350E+04 0.203E+02
Q.1375E+04 O.187E+02
O.1400E+04 0.163E+02
0.1425E+04 0.134E+02
0.1450E+04 0.108E+02
0.1500E+04 0.707E+Ol
0.1600E+04 O.340E+Ol
0.1700E+04 0.193E+Ol
0.1800E+04 0.121 E+Ol
0.1900E+04 0.829E+00
0.2000E+04 0.596E+00
0.2100E+04 0.446E+00
0.2200E+04 0.345E+00
0.2300E+04 0.273E+00
0.2400E+04 0.221E+00

26.417
26.166
25.459
24.219
22.568
20.713
16.984
10.635
5.693
1.703
-1.634
-4.501
-7.016
-9.255
-11.275
-13.115
-14.807
-16.372
-17.830
-19.194
-20.476
-21.687

84.93
67.39
48.87
31.05
15.50
2.78
-15.46
-35.62
-46.41
-53.24
-58.02
-61.59
-64.36
-66.60
-68.45
-70.00
-71.34
-72.49
-73.51
-74.41
-75.21
-75.94

1.75
1.95
2.06
1.98

O.1100E+04

0.1125E+04
O.1150E+04

O.2500E+04

O.182E+QO

0.2600E+04
0.2700E+04
0.2800E+04
0.2900E+04
0.3000E+04

0.152E+00
0.128E+00
O.I09E+OO
0.947E-Ol
0.824E-Ol

Frequency

0.3000E+03
0.4000E+03
0.5000E+03
0.6000E+03
0.7000E+03

dB
Voltage

0.1900E+04
0.1925E+04
0.1950E+04

0.467E-03 -66.607
0.116E-02 -58.686
0.242E-02 -52.315
0.454E-02 -46.867
0.794E-02 -42.001
O.133E-Ol -37.505
0.218E-Ol -33.233
0.352E-Ol -29.071
0.567E-Ol -24.925
0.923E-Ol -20.700
O.153E+OD -16.298
O.263E+OO -11.595
O.477E+OO
-6.425
O.941E+OO
-.531
O.212E+Ol
6.534
O.601E+Ol
15.574
0.814E+Ol
18.210
0.110E+02
20.874
O.146E+02
23.268
0.176E+02
24.935
O.192E+02
25.654
O.194E+02
25.738

O.1975E+04
O.2000E+04

O.191E+02
O.189E+02

0.2025E+04

0.189E+02
0.191E+02
0.193E+02

O.SODOE+03

0.9000E+03
0.1000E+04
O.1100E+04

0.1200E+04
0.1300E+04
0.1400E+04
0.1500E+04
0.1600E+04
0.1700E+04
0.1800E+04
0.1825E+04
0.1850E+04
O.1S75E+04

O.2D50E+04

0.2075E+04

1.73

O.2100E+04

1.41
1.01
.56
.30
.19
.13
.10
.08
.06
.05
.04
.04
.03
.03
.03
.02
.02

0.2125E+04
0.2150E+03

O.222SE+04
O.2250E+04
O.2275E+04

O.19SE+02
O.19SE+02
O.195E+02
O.194E+02
O.193E+02
O.193E+02
O.194E+02
O.196E+02

0.2300E+04

0.197E+02

O.2325E+04

O.191E+02
0.176E+02
O.150E+02

O.2175E+04

0.2200E+04

0.2350E+04
O.2375E+04
O.2400E+04
O.2425E+04

0.2450E+04
0.2475E+04
O.2S00E+04

0.2600E+04
0.2700E+04
O.2800E+04
O.2900E+04

0.3000E+04

3-76

Node
Voltage

0.122E+02
0.976E+Ol
O.77SE+01
0.621 E+01
O.S03E+Ol
O.247E+01
O.142E+Ol

0.901E+00
O.61SE+OD
O.443E+OO

Phase
Shift
87.38
86.45
85.47
84.42
83.28

Envelope

Delay (mol

68.37
63.50

.03
.03
.03
.03
.04
.04
.05
.05
.06
.08
.10
.14

56.43

.20

44.84

25.529
25.532
25.609
25.713
25.795
25.824
25.798

-70.39
-90.48
-107.18
-121.58
-134.82
-147.63
-160.44
-173.34
173.77
161.04

.32
.67
1.21
1.63
2.15
2.56
2.57
2.23
1.86
1.60
1.47
1.42
1.42
1.43
1.43
1.41

26.743

148.60

1.38

25.696
25.696
25.756
25.851
25.876
25.634
24.888
23.549
21.768
19.786
17.786
15.858
14.039
7.860
3.031
-.904
-4.218
-7.079

136.37
124.09
111.29
97.31
81.50
63.59
44.47

1.36
1.36
1.42
1.55
1.76
1.99
2.13

26.10

2.04

10.27
-2.47
-12.48
-20.37
-26.70
-42.9Q
-51.95
-57.83
-62.00
-65.14

1.76
1.42
1.11
.88
.70
.45
.25
.16
.12
.09

25.618

82.01

80.59
78.97
77.07
74.79
71.98

20.75

9.86
-4.80
-24.14
-47.21

AN731

300Hz

_
1

_I

-

i

Modulation BW ~

26

0.4 dB Ripple

t

25

iii

24

..

23

~

c

CJ

22

I>
~

o
'o8.
~c

w

1800

1900

2000

2100

2200

2400

2300
1
2275

1975
Frequency (Hz)

FIGURE 10 - Originate Bandpass Filter Characteristics

From

1 ~F

680

Ba;i~:~ss --111--'Wv--<~---"
Output

To Pin 17
(Receive Carrier)

MC6860

1 k

1 k

FIGURE 11 - Limiter Schematic

3-77

2500

AN731
DEMODULATOR
The demodulator utilizes half-cycle detection for determining the presence of Mark or Space frequencies.
Therefore, the Mark/Space information is quantized to
half-cycle increments of the received carrier. Digitizing a
linear signal produces a quantization error. This error
appears in the form of phase jitter and bias distortion at
the demodulator output of the MC6860.
The phase jitter of the demodulator output is shown in
Figure 12. The upper trace is the alternate Mark/Space
transmit data into the originate modulator. The lower
trace shows the recovered data out of the demodulator of
the answer modem. The inherent phase jitter of the demodulation process is apprOximated by

roth:

OTJP

•

eak ""

Total distortion equals percent peak jitter plus percent
bias distortion.
Careful inspection of Figure 12 reveals less than 0.2 ms
marking bias. This is the accumulative bias distortion from
the modulator input through the system to the demodulator output. The majority of this distortion results
from the non-linear envelope delay through the bandpass
filter in the answer modem. It is for tins reason that
special consideration must be given to delay distortion.

DATA COUPLERS
The two data couplers commonly used with low-speed
modems are the CBS and CBT2. Each contains a data
access arrangement (DAA) and the necessary telephone
network control Signaling functions. Figures 13 and 14
show the block diagrams of the CBS and CBT data
couplers respectively. The supervisory control signals from
the CBS comply with the RS-232 interface specifications,
whereas the CBT control signals are contact closures and
relay drive currents.
Table 3 identifies the various data coupler input/
output Signals.

Data Rate
x 100
4 Space Frequency

The receive Space frequency for the answer modem is
1070 Hz and the data rate is 300 bps, giving a peak phase
jitter of 7%. This corresponds to 0.233 ms, as shown in
Figure 12. The output Mark/Space transition will occur
within 0.233 ms of the actual data transitions, neglecting
bias distortion.
The receive Space frequency for the originate modem is
2025 Hz. The peak phase jitter is 3.7% (0.123 ms) at a
data rate of 300 bps.
Bias distortion inherent in the demodulation process
can be found according to:
% Bias Distortion "" 21T

(f. - ~)
f

SYSTEM PERFORMANCE
The MC6860 was evaluated in a typical system configuration. The tests utilized an originate only and an
answer only design as outlined in Figure 15. The relative
gains for both the answer and originate modems are
given. A 600-ohm termination was provided to simulate
the characteristic impedance of the transmission line, and
to provide an input for the gaussian noise generator.
The test equipment was connected according to Figure
16. A word generator producing a 255-bit pseudo-random
pattern at 300 bits per second was used as a transmit data
input to the originate modem. The return channel was
held at a constant Mark condition. The received data from
the answer modem was compared for errors on a bit-bybit basis with the transmitted data.

100

where T =Data bit period in seconds
fs = Space frequency in Hz
fm = Mark frequency in Hz
Thus the originate modem has a bias distortion of 0.67%
and the answer modem has 2.2%. This is a marking bias
(period of a Mark greater than period of a Space) for
both modems.

Transmitted
Data

Mark

>

Space

is

:>
0

.,;

Mark

Received
Space

Data

1.0 ms!Oiv

Time

FIGURE 12 - Bias Distortion and Ph... Jitter .t Demodulator Output

3-78

AN731

T

OH

,....

l
R

.1
Ring

Detector

,.,

---,
CT-

J

Test

Control

1

*+

CT

Automatic
Level

---'

Contact closed
Contact open

OA

FIGURE 13 - Block Diagram of
CBS Data Coupler

1-----oOH

CT

RI

"----r'>CCT

r;::.....
Switch Hook ------iV>------------F 3600/cycle

(7)

t>F = change in frequency in Hz

To maintain less than 0.8 millisecond group delay at a
data rate of 300 bits per second reqUires an overall filter
bandpass of 400 Hz. This results in the low frequency
pair (answer) filter passband being between 970 Hz and
1370 Hz (6-pole. 0.5 dB ripple Chebyshev).

ripple (Amax). and stopband attenuation (Amin).
to determine the order of the prototype lowpass
filter.
From Table 2. determine the location of the prototype low pass filter poles opposite the determined filter order.
From the low pass filter poles. determine their
natural frequency (w) and damping factor (~).
Transform the low pass filter section parameters
to cascaded second order bandpass filter design
section Q and center frequency values.
Determine the active element operational amplifier gain by solving for center frequency loss and
system filter passband gain (AVO).
Use each section Q. frequency. and gain to solve
for the bandpass filter passive component values.

Step (1) - Filter Shape Factor
Figure II shows a design example for a typical 6-pole
answer modem receive filter design. From this data. it is
possible to calculate the filter shape factor (ns) for the
prototype filter.
n

Filter Design Steps
The modem bandpass filter examples will be designed
using the following procedural steps:
(I)

s

TABLE 2 - Pole Locations and Quadratic Factors
(.2 + a,. + 10) for Chebyshev 0.5 dB Ripple Filter
0.5 dB Ripple

TABLE 1 - Complexity Nomogreph for Chebyshe. Filton (Zv_.)
A max

2

A
I
mn

12
11
140
130

10

120
110

20

100
90

10

80
dB

9
8
7

70
60

6

50
5

0.1

~
30 t-20

4

0.001
0.0005

10

I I

8

2
3

7/ 6

1111 /

WI; /

2

'1//

-0.11196
-0.29312
-0.36232
-0.07765
-0.21214
-0.28979

7

1
0

8

9

./

/'

,/

'1// f..-'""

)..

10

~

2

3
fl.

4

5 6 78910

3-88

.,

5

/

V

I()

-0.71281 ± j 1.00404 1.51620 1.42562
-0.31323 ± j 1.02193 1.14245 0.62646
-0.62646
-0.17535 ± j 1.01625 1.06352 0.35071
-0.42334 ± j 0.42095 0.35641 0.84668

6

2

Pole.

4

5

3

0.0001
0.00005

5 6 78910

4

~

1.0

0.01
0.005

Order

Ws V
~:II I II I V V V
/
II I rl/ I
?l fl, V / V
?l11/ / 4j
Ifll.11/ I
1111 V/ ;,-/
1W, 9

40

3

(I)

2110
ns= 400 =5.28

Determine the required prototype low pass filter
shape factor from the passband width and stopband attenuation.
Enter Table 1 with the shape factor. passband

(2)

=F4- F 3 = 2225 -115
F2-FI
1370-970

±j 1.01156 1.03578
± j 0.62518 0.47677
± j 1.00846
± j 0.73824
± j 0.27022

0.22393
0.58625

1.02302 0.15630
0.59001 0.42429
0.15700 0.57959

-0.05700 ± j 1.00641 1.01611 0.11401
-0.15972 ± j 0.80708 0.67688 0.31944
-0.23080 ± j 0.44789 0.25388 0.46160
-0.25617
-0.04362 ± j 1.00500 1.01193 0.08724
-0.12422 ± j 0.85200 0.74133 0.24844
-0.18591 ± j 0.56929 0.35865 0.37182
-0.21929 ± j 0.19991 0.08805 0.43859
-0.03445
-0.09920
-0.15199
-0.18644
-0.1984'1
-0.02790
-0.08097
-0.12611
-0.15891
-0.17615

± j 1.00400 1.00921
± j 0.88291 0.78936
± j 0.65532 0.45254
± j 0.34869 0.15634

0.06891
0.19841
0.30397
0.37288

1.00327
0.90507
0.71826
± 0.46115
± 0.15890

0.06580
0.16193
0.25222
0.31781
0.35230

±
±
±

1.00734
0.82570
0.53181
0.23791
0.05628

AN747

Step (4) - Lowpass Prototype Filter Natural Frequencies and Damping Factors
Using the folloWing relationships, solve for the natural
frequencies (w) and damping factors (n:

~
c

;;

P,* - --

(!l

6

I
I

>



 R2 such that

SQ--o
Rl
S

Solving as in Section I using Equations 23 through 31,
we obtain:

Q--- l / 2
R2

These sensitivities imply that to change section Q, R2
should be adjusted. If R2 were increased, for example
20%, section Q will decrease 10%. Notice that the sensi·
tivity of Q to changes in R2 and RS is equal and opposite
in magnitude. This implies that if R2 and RS are changed
by the same percentage. but in opposite directions, section
Q will not change. Also, as RS is adjusted, it changes the
section center frequency by a ratio of -1/2.

wC2 = 6.12SS x 103 rad/s, 974.9 Hz
QC2 =9.30
AVOC2 =4.43
RS = 303.7S kl:),
RI =34.28 kl:),
R2 =900.S I:),

Filter Tuning Procedure
Section Center Frequency:
(a) Increase/decrease RS for a corresponding decrease/increase in section center frequency wOo
(b) Increase/decrease R2 by the same percentage of
increase/decrease applied to RS in step (a) to
maintain constant sectionQ.

Section 3:
F3 = IIS2.73 Hz
W3 = 7.243 x 103 rad/s
Q3 =4.S96
AV03 =4.41
C3 = C4 = I x 10.8 F
Solving as in section I and 2, we obtain:
wC3 = 7.281 x 103 rad/s, 1158.87 Hz
QC3 = 4.58
AVOC3 =4.41
RS=12S.72kl:),
RI = 14.24 kn
R2 = 1676.9 I:),

Section Q:
(a) Increase/decrease R2 for a corresponding decrease/increase in section Q.

ORIGINATE FILTER DESIGN
Basically, the originate receiving filter design procedures
are identical to the answer filter example. The one major
difference is that the filter center frequency is shifted
to accept 202S - 222S Hz signals. One might also note
that the second harmonics of the local transmit signals in
the originate mode (1070 - 1270 Hz) fall within and just

The complete answer filter is shown in Figure 13a with
the filter response and envelope delay curves shown in
Figure 13b. If the filter is not optimum after construction,
it may be fine tuned by the following method.

3-93

•

AN747

outside of the passband for the originate receive filter, For
this reason, the originate only modem designer may want
to provide a transmit bandpass filter to suppress harmonics
produced by the local transmit carrier (see Figure 15).
The three section design parameters and component
values for the 6-pole originate receive filter are:
Section I:

+20
+15

FI = 2425.81 Hz
QI = 16.56
AVOI =4.48
C3 = C4 = 1 x 1O-8 F
RI = 24.26 kn
R2 = 199.76 n
R5 = 217.258 kn

•

6-pole design example. Therefore, only the component
values for the 8-pole and 4:pole filters are tabulated in
Figure 15 without the individual circuit diagrams.

.

+10

3.oi

~+5.0

2.00

>

iii
"0

0;

,

'iii

0.

(!)

6

0

1.05

0

>

Section2:
F2 = 1985.62Hz
Q2 = 16.67
AV02=4.48
C3 C4 I x 10-8 F
RI 29.85 k
R2 242.36 n
R5 267.23 kn

«-5.0

0

-15L-~~~

= =
=
=
=

__~__U-__~__~-W~~__~~

16001700180019002000210022002300240025002600
f, Frequency (Hz)

FIGURE 14b - Originate Filter Gain and Group Delay

Section 3:

=

F3 2154.oJ Hz
Q3 = 8.32
AV03=4.43
C3 = C4 = I x 1O-8 F
RI 13.88 kn
R2 = 458.85 n
R5 = 122.913 kn

RECEIVE ORIGINATE
Section
R

~IHI

=

1
31.42 k

1111

R5 1111

2
39.54 k

4

3
14.71 k

16.1 k

146.8
181.15
396.29
432.32
288.64 k 363.27 k 132.15 k 144.66 k

RECEIVE ANSWER

The complete 6-pole receive originate filter is shown
in Figure 14a, with the response and envelope delay curves
shown in Figure 14b.

Section

R

1111

~IHI
R5 1111

8-POLE, -SO dB RECEIVE AND 4-POLE, -25 dB
TRANSMIT FILTER DESIGN
A complete full duplex modem system will most likely
require operation with input signals down to -50 dBm at
the line input. This requires a receive filter network having
at least 8 poles to provide the necessary attenuation to
adjacent duplex channel interference and a local transmit
filter having 4 poles to provide 25 dB local transmit signal
harmonic rejection. The construction of an 8-pole or 4-pole
filter takes on the same cascaded form as the illustrated

1

2

3

4

31.08 k

46.34 k

14.51 k

17.1 k

468.48

690.57

1397.94 1643.88

283.33 k 422.31 k 131.38 k

154.8 k

TRANSMIT ANSWER

TRANSMIT ORIGINATE
Section

1

2

Section

1

R 1 111 )

, 5.73 k

20.56 k

Rl Ill)

16.17 k

18.78 k

R2 1111
R5 Ill)

1218.55

1586.55

R21H1

36695

423.79

130.47 k

170.47 k

R5 1Hl

2

133.25 k 154.81 k

Note. All Capacitors = 0.01 IJF

FIGURE 15 - a·polo, -SO dB Receive and 4.pole,

-25 dB Transmit Filter Values

24.3 k

All capacitors are In .uF

FIGURE 148 - Originate Filter Component Values

3-94

:;

t

AN747

The measured response and envelope delay for the switchable 6-pole receive filter design is shown in Figure 17b.
Figure 18 illustrates the complete modem system with
the RS-232 interface to the CBS data coupler, and the
direct interface to a CBT data coupler. Automatic disconnect option inputs are handled by PC board mounted
switches. The complete automatic modem, less the power
supply, may be easily constructed on a single 4 x 5 prin ted
circuit board.

AUTOMATIC ANSWER/ORIGINATE MODEM SYSTEM
The filter design for a fully automatic answer/originate
modem system must have switchable bandpass characteristics. By tabulating the previous component values for
both the answer and originate filters, one can draw some
conclusions on how to best switch the fil ter from one range
to the other. The following example uses the previous
derived values for the 6-pole receive filter. Figure 16 indicates that switching in different values of R2 for all three
sections and a different value for RS in the second section
would provide the required switchable answer/originate
filter. By adjusting the non-switched resistors to the average
value between the answer and originate filter values, the
more accurate the first switchable filter prototype will be.
A semiconductor switch is used to switch values of R2, and
operates in shunt to ground. The best choice for the shunt
switch is to use a low on-resistance bipolar device such as
the 2N3904. For switching RS of section 2, a high off
resistance device is required due to the high series resistance
in the feedback path of the operational amplifier. An
MFE200S N-channel junction FET was selected to do this
job. Figure 17a illustrates the fully automatic answer/
originate switchable filter system. Also shown are the
transmit buffer, duplexer, threshold detector, limiter, and
mode control level translator sections. The level translator,
which provides the correct on/ off voltage levels to the
bipolar FET switches, receives its answer/originate command from the MC6860 modem mode control output pin.

Answer

Originate

Resistor

1070-1270 Hz

2025-2225 Hz

Rl1
R21
RSI
R'2
R22
R52
R'3
R23
R53

23.89 k
632.2
211.7 k

24.26 k
199.76
217.26 k
29.85 k
242.36

34.28 k

900.5
303.75 k
14.24 k
1676.9

267.23 k
13.88 k

125.72 k

122.91 k

458.85

CONCLUSION
A low-speed modem design has been presen ted using
the MC6860 LSI MOS digital Modem integrated circuit.
Included has been a system design example using filter
design tables and equations to develop a comple te modem
system. Also included have been component values for
filter designs which may be used to develop full duplex
modem systems.
The availability of this LSI modem circuit along with
the presented filter deSigns should provide a very useful
building block for the OEM modem and terminal designers
by proViding him precise digital modulation, demodulation,
and superVisory control. The modem designer will find
that a design approach using the MC6860 modem will
also provide an impressive system size reduction as well as
a better price-performance choice for his present and
future low speed modem designs.

Average
or
Value

Ll.

24.08 k
A 432.4
214.48 k
32.07 k
.A 658.2
A 36.5 k
14.06 k

1218.05
124.32 k

Answer

Originate

Switched

Switched

24.1 k
632
214.5 k
32.1 k
900
304 k
14.06 k

24.1 k
200
214.5 k
32.1 k
242
267 k
459

124.3 k

124.3 k

FIGURE 16 - Switchable Modem Filter Values

3·95

14.06 k

1677

•

•

~

Z
....
....

THRESHOLD DETECTOR

~

Tx Car

ro
CBT/CBS
To Line

2k

1 k

-=

-=

+12 V

-12 V

I

*1.0
+5 V

~1

10

'-::!:- ~1.0

:>

1 k

ORx Car

2k

(0)
I

CD

en

L - -_ _ _ _

'-'-----4--j~I~

Mode
30k~2.2k

2N3904

-=

30
1 k

10 k

6.8 k

I

ANSWER

ORIGINATE

-=

i

...
>

All Capac Itors are

In

iii

,u F

E
c
ii

C3n. C4n '" 0.01 ,uF 1 1%.
ReSIstors R 11 thru R53 are ± 1%.

All

=241kn

R21A" 20011
R21B=432H

RSl

=

214.5 kH

R12

"'32.1kH

R22A" 24211
R22B " 658 II
R52A" 267 kll

R52B = 37 kH
A 13
== 14.06 kH

R23A "459 !!
R23B "1218 !!
R53

==

"6

>

<{

':~/ If·

-20

I

2.0

0

~
~

0

".

~

I

124.3 kH

1000

1500

2000

f, Frequency (Hz)

FIGURE 178 - Switchable Filter/Duplexar

FIGURE l1b - Switchable Filter R_nse

•

AN747

I::i: - - - - - - - - - --l

+5 V

~

Data Terminal

10

Break
Release

Transmit
Sreak

Receive
Sreak

Transmit
Carrier
hreshold
Detect

15

Transmit
Data
Data
Terminal
ReadY

I

See F;g 17.

17

r------,

I
I

MC1488

Mode
Receive
Carrier
Line

MC6860

I

Digital 11
No
Carrier
Connection

Receive

Gnd

19
Ring
Inidcator

+V

I

IAn Ph
+5 V I
I
I

DH

2N3903

CBT

Oat.

Coupler

2N3903

I

-=

SH
RI

I

I

SH1

Ai

I
I
I
I

I
I

-V

-=

SH

An Ph

SH
AI

I Line
I
I
I
I

I
I
I

Self

I

DA

-12)

I
I

I
I
I

1--------------1

Switch
21 Hook

+5 V

I

:

DT

I

Clear·toAnswer
4 Phone

DR

+12VI

Data
Send

I

I
I

-= -=

I

,---------,
: MC1488 :
I

:

DT
OH

:

-= I
DR
I
I
I

OA
CBS

Data

Coupler

I

Test

I
I

I
I
I
I
I
I

IAn Ph

I SH
SH
I Ai
RI
I
L _____ .• __ ~
SG
L __________ _ J
~

FIGURE 18 - Modem System

3-97

EB·49

®

MOTOROLA

Application Performance of the MC6860 MODEM

•

MODEM Opemtion

A MODEM fills the need in a data communication network to provide interface between a telephone network,
which carries analog information, and a computer system that operates on digital information. Figure 1
illustrates a typical MODEM application in which both
transmitting (modulation) and receiving (demodulation)
sections are contained within each MODEM system.
Traditionally, these signal conversion operations are performed by analog methods whereas Motorola's recently
introduced MC6860 MODEM modulates and demodulates using digital techniques .

Basically, a MODEM converts logical "I" and "0" levels
into analog frequency tones and back again to ","s and
"O"s. These tones have the specific frequencies listed in
figure 2. Two pairs of tones are listed for each modem,
one set for transmitting and one set for receiving, so that
two-way (full-duplex) operation is possible over a single
transmission line. The computer terminal MODEM that
places a call is referred to as the originate MODEM,
(transmitting tones of 1070 Hz and 1270 Hz) whereas
MODEM

MODEM

Data
Terminal

Data
Terminal
Equipment

Equipment

FIGURE 1. Typical MODEM System Application

Digital

Mode

Answer

Originate

Send

Receive

Send

Receive

Mark

1270 Hz

2225 Hz

2225 Hz

1270 Hz

Space

1070 Hz

2025 Hz

2025 Hz

1070 Hz

FIGURE 2. System Frequency Assignments

3·98

EB·49
the data terminal recelVlng this call is the answer
MODEM, (transmitting tones of 2025 Hz and 2225 Hz).
Modulation
In an analog MODEM, one constructed of linear devices,
modulation is accomplished by shifting the frequency of
a sinewave oscillator. This oscillator is usually con·
structed using tunable cup core inductors resonated with
precision capacitors, a technique that can be expensive
both in terms of components and the tuning necessary
to meet frequency requirements. Temperature compen·
sation of these oscillators is also necessary to maintain
frequency tolerances across the operating temperature of
the MODEM system.
In the MC6860 digital MODEM, a I-MHz frequency is
divided down by digital counters to obtain the desired
modulation transmit frequencies.
Outputs of this
counter chain are used, with a resistor ladder network
and decoder, to generate an eight-level analog output
signal. Each of the eight levels of the digital sinewave
output has been designed to provide the composite
waveform with a maximum amount of signal energy at
the fundamental frequency. This lowers second harmonic content; consequently, less interfering signal is
ger.erated which could cause problems during fullduplex operation. Output frequencies with an accuracy
of 0.1% result from this digital modulation technique.
The onry external component necessary for MC6860
modulator operation is either a I-MHz signal source or a
I-MHz crystal.

For example, the frequencies of 1070 Hz and 1270 Hz
have half-cycle periods of 467 JIS and 393 JIS, respectively. The optimum period for discriminating between
a mark (1270 Hz) or a space (1070 Hz) frequency is the
mean of these two half-cycle periods, or 429 JIS, which
may be easily measured by a counter circuit.
Using this half-cycle measurement technique, a quantization error results as is depicted in figure 3. When
transition is made between a mark and space condition,
the interval for that particular half-cyc1e depends on the
phase of the Iialf-cycle in which the change in frequency
occurs. Thus, if the frequency changes early in the halfcycle period, this measured interval will closely approximate that of the new frequency period. However, if
the frequency changes later in the half-cycle period,
determination of change will be based on the previous
condition. Because counter techniques are used, a
discrimination point exists in the half-cycle interval
such that the new information (i.e" the change from
space to mark or vice versa) will be detected at the end
of the interval if the frequency change occurs prior to
the discrimination point. If the frequency change is
made after the discrimination point, the new information will not be effectively detected until the end of the
next interval, at which time this measured half-cycle
interval will be totally determined by the new frequency
period. The net result of this detection scheme is that
new data is effectively detected within regions either
half an interval prior to the discrimination point or half
an interval after the discrimination point.

Demodulation
Demodulation in an analog MODEM depends on frequency discrimination obtained using narrow-bandwidth
bandpass filters centered about each of the two possible
received frequencies. When the received signal frequency
is centered within one of these bandpass filters, a threshold comparator (slicer) is switched producing either a
logic "I" or "0" output level dependent upon which
frequency within either the originate or answer tone
pairs was received. Analog demodulation deals directly
with the continuously changing analog signal although
periodic frequency changes occur. Recognition of these
frequency changes is normally within 2% of the actual
change in relationship to the total 'received signal time
interval. By adjusting the threshold of the slicer, the
output interval distortion Gitter) can be reduced to
values of 1% or less.
Digital demodulation in the MC6860 takes place in the
following manner. The received analog frequency is first
shaped into a square wave by the use of an external symmetrical limiter. Once shaped, the signal's half-cycle
period is measured and this information is used to determine if a space or a mark frequency is being received.

Point of Change in Incoming
Mark/Space Frequencv

6~~c~~~:~~~~~:nt

'I
I

I
I
I

Demodulator

Output

Mark

I

I >429

I

~ Mark or Space' ~

--.j Half·Cycie I nterval

~s

I Signal was a Space

Space

~

FIGURE 3. Mark/Space Uncertainty Region

The quantization error associated with this half-cycle
technique leads to an output distortion condition called
jitter. As defined in EIA Standard, RS404, "Standard
for Start-Stop Signal Quality Between Data Terminal
Equipment and Non-Synchronous Data Communication
Equipment" and generally accepted in the industry,
jitter is a measure of the time displacement of the
detected transistions between signal states from their
ideal instants. This is normally expressed as a percentage
of the unit bit interval. From previous discussion then,

3-99

I

~

EB·49

the peak jitter associated with the demodulation scheme
used in the MC6860 can be expressed in equation form
as
"'J .. 1/4 Frequency Cycle Interval X 100'11
Bit Period Interval
0

'I'

Since jitter is maximized by using the largest frequency
cycle interval which occurs during a space logic condition, phase jitter can be expressed as

J)

Bit Error Rate Performance

Data Rate
Bits per Sec.

Answer Mode

300

7.0

3.7

200

4.7

2.5

150

3.5

1.8

110

2.6

1.4

~J

Originate Mode
~J

(Peak %)

(Peak %)

Although the demodulation technique used in the
MC6860 leads to a somewhat larger amount of jitter
than that from demodulators using linear devices, the
overall jitter in a system is dependent on other factors
including filter characteristics, transmission line characteristics, and system noise. These generally have about
the same effect whether linear or digital techniques are
used in the demodulation process; however, their contribution to system jitter may well be more significant than
those of the demodulation process itself.

MODEM system performance is best shown by documenting the MODEM'S back-to-back error rate performance when the system is subjected to noise. Backto-back operation is where MODEM A transmits to
MODEM B over a connecting line and both the transmitting and receiving ports are locally available to a test
instrument. The test setup shown in figure 6 uses a
Bowmar 251 A error rate test set to measure the
MODEM system performance. A 51 I-bit pseudo random
data pattern is supplied to MODEM A's modulator for
transmission over the line to MODEM B's demodulator.
The modulator's analog output is combined with noise
at a line mixer unit and a signal of measured signal-tonoise ratio is delivered to the line input of MODEM B.
MODEM B, operating in the originate mode (receiving
2025/2225 Hz tones), demodulates the received analog
data into digital data in the presence of noise and delivers this data stream to the Bowmar test set.

Digital Input - - - ,
.1_____S;..pa_c_e_ _ _---'
L

to Modulator

Mark

~,J.-- Sample Point Tolerance
Digital Output

~

of Demodulator

m

~

~
~
~~------------~LQ
Peak Phase
Jitter

L
I

~
~~-----

Electronic
Device Sample
Point

FIGURE 5. Demodulator Oat. Bit Output

3-100

EB·49

I

Noise Filter

Noise Amplifier
BW 1.0 MHz -3 dB
Av 40 dB
ZOUT 600n

Noise Generator

20 Hz to 5 kHz

Gaussian Noise

24 dB/Octave
Krohn-Hite
Model 3202

EIgenco Inc.
Model602A

J

RX Data

Originate
MODEM
Test Set
for Error

Rate
BOMAR
251A

r--- -----,
TX Data

f---+-----+

r

I
I
I

Answer
MODEM

T~

System Under

200n:
I

Ongmate
MODEM

IL _
200n
200n
____
_ _ JI

TX Data

Mixer Box 600 51

Answer

RX Data

MODEM

Test Set for
Full-Duplex
only

BOWMAR
251A

•

True R.M.S. Voltmeter
H-P Model 3400A
Noise Voltage

Wave Analyzer

H-P Model 302A
Signal Voltage

FIGURE 6. Back-to-Back Full-Duplex MODEM Error Test

The test set will compare the received data bit-for-bit
with the transmitted data and each difference will be
recorded as a bit error. Errors are recorded for a specified number of transmitted bits and the ratio of the
number of bit errors to the number of bits sent is defined as the probability of bit error. This ratio is plotted
against the measured line signal-to-noise ratio, figure 7,
which then represents a MODEM'S system performance.
Figure 7 has included for comparison a plot for a Bell
113A MODEM, an industry standard. Curves are shown
for a MC6860 MODEM system operating in a fullduplex mode. These curves indicate that the MC6860
subjected to system noise provides excellent bit-error
rate performance.

1 X 10- 1

1 X lO-

g

w 1 X lO- 3
iii

3·101

~

~

j
e

1 X 10-4

0-

1 X 10-5

1 X 10-6
-6

,

1\

'0

Summary
Although the jitter resulting from the digital demodulation technique used in the MC6860 MODEM is somewhat larger than that obtained using linear techniques,
performance data shows that the MC6860 provides
excellent performance in data communication systems.
Advantages of small size, low-system expense, and good
performance make the MC6860 MODEM a very costeffective device worthy of serious consideration for your
data communication applications.

,

2~

.""~-~
-4

-2

Motorola MC6860 System

~\

Signal-ta-Noise dB at the Line Input

FIGURE 7. MODEM Bit·Error Rate Originate Mode
Back-ta-Back Full-Duplex Transmission

8

®

AN·891
Application Note

MOTOROLA

MC14412/MC145440 CHIP SET
SETS NEW STANDARD IN
300 BAUD MODEM DESIGNS
Prepared By:
Richard Hall
MOS Telecommunications System

•

The advent of the MCI44I21MCI45440 modem chip set
offers a dramatic reduction in the cost and in the complexity
of 300 baud modem designs. The MCI4412 is a CMOS
device that performs the modulate/demodulate functions of
a basic 300 baud modem. The MC145440 is a CMOS
switched-capacitor filter that provides the necessary upperand lower-band separation for full-duplex operation at 300
baud. By adding a small number of components, a complete
Bell !03-compatible modem can be built.

HOW DOES A 300 BAUD MODEM WORK?
A 300 baud modem is perhaps the most common type of
modem encountered in data communications. Its advantages
are many: low cost and complexity, full-duplex operation
over a two-wire connection, and reliable operation over the
normal dial-up telephone network. It has found a home in
banks, offices, laboratories, and computing centers; and
now with the increasing popularity of personal computers, it
is even in our own homes.
These 300 baud modems (based overwhelmingly on Bell
!O3 operation) employ a modulation scheme called Frequency Shift Keying (FSK), a slightly intimidating term for a simple technique of using different frequencies to encode digital
data for analog transmission over the telephone lines. In
other words, a logic one causes the modem to transmit one
frequency while a logic zero causes another frequency to be
transmitted. Full-duplex transmission over a two-wire
telephone line is achieved by separating the bandwidth of the
lihe (300-3,000 Hz) into a low band and high band, each containing two frequencies for a logic one or zero. These two
frequencies are referred to as mark and space, with mark
representing the higher of the two frequencies. The frequency designations for Bell !O3 operation are shown in Figure I.
To avoid two modems trying to transmit data on the same
band, a simple protocol usually exists. Whenever one modem
calls another modem, the calling or originate modem
transmits on the low band and receives on the high band. The
modem you are calling will operate in the answer mode,
transmitting on the high band and receiving on the low band.

Variations on this theme are answer-only and originate-only
modems that only transmit or receive on one particular band.
Communication theory predicts that the signal bandwidth
of binary (that is, two frequencies in each band) FSK
operating at 300 baud, with mark and space 200 Hz apart, is
approximately 300 Hz) This bandwidth is centered about
the apparent carrier frequency halfway between the mark
and space frequencies. In order to properly demodulate the
FSK signal and attenuate out-of-band noise, the filter should
have a similar bandwidth of 300-400 Hz for each band.
Another concern is that the filter minimize envelope delay
distortion (EDD), which is a measure of the linearity of a
filter's phase response. Excessive EDD can distort the signal
enough such that baud transitions smear and ultimately produce an error (this problem is usually called intersymbol interference). The MC145440 filter meets these requirements,
as is shown in Figure 2.

300 BAUD MODEM EVALUATION BOARD
The schematic for a simple 300 baud modem that we have
designed for an evaluation board is shown in Figure 3. This
board allows the user to evaluate the performance of the
MCI4412/MCI45440 system over a telephone line. An RS232C connector permits testing with a terminal or any other
RS-232C compatible equipment. A TTL compatible interface is also provided through the coaxial connectors TTL
data in and TTL data out. The user can program this board
to accommodate either single or dual power supplies. Switches and solderable straps allow selection of
originate/answer, loop-back, different crystal frequencies,
and other options, as are described in Figure 4.
To set up the board for a particular power supply configuration, it is important to understand the operation of the
single/dual strap and how it relates to the power input
jacks - VDD, VSS, and VAG. When connecting a single
supply of + 5 to + 6 V, the board must be strapped to use the
internal Vref generated by the MCI45440 (E4-E5).
Therefore, the + V would be connected to VDD and ground
to the VSS terminal. The single strap (EI3-EI4) serves to

3-102

AN891
the input level to the tran,mit filter and ;ub,equently ,ets the
output level to the line.
The signal at U2 pin 3 is then filtered and amplified by 10
dB and output at TxO, pin 2.This output will supply ± SmA
at 4 Y peak when the part is running on ± S Y. This signal is
then routed to the input of the active duplexer as well as to
transformer TI and on to the line.' The purpose of the
duplexer is to help reject transmit signal energy while amplifying the receive signal at TPI by 6 dB. Balancing the duplexer is an important procedure that minimizes transmit signal
interference, and is shown in Figure 6. TI is a typical 600:600
ohm telephone coupling transformer whose primary is rated
to handle the 20-80 rnA of dc loop current possible when seizing the telephone line. ZNI is a transient-suppressor device
designed to absorb any voltage spike above a certain clamp
level. R8 provides surge current limiting to help protect the
ZNI.
The receive signal at TPI is routed to the non-inverting terminal of the duplexer op amp (pin 17). After being amplified
by 6 dB, it is input to the receive filter at RxI (pin 13). The
filter output is at RxO (pin 14) and this is fed to the limiter
and carrier detect circuits. Between the actual input to the
limiter and RxO is an optional gain of two stage (U4) which
allows receive sensitivity down to - 45 dBm without having
to trim the offset of the limiter compar"tor (USA). The output of the gain stage is then filtered by a simple RC low pass
that attenuates the high frequency switching noise inherent in
a switched-capacitor filter. The signal at TP4 is ac-coupled
into the limiter which converts the sinusoidal waveform into
a symmetrical square wave which is then input to the
MCI4412 (pin I) for demodulation. Careful layout of the
limiter is important since extraneous high frequency noise
can create jitter in the square wave output, degrading biterror-rate performance. Selection of a low-offset comparator
for the limiter is also critical since a higher offset will produce

define the RS-232C signaling ground and the data in/out
connectors' ground at the + Y ground. To provide a negative
supply below the + Y ground for the RS-232C interface, the
RS-232 YSS jack provides access to the MCI488 drivers'
negative supply input (- YRS). When wanting to run the
board from a ± supply, the Yref strap (E4-E5) would be
open and the single/dual point would be strapped for dual
operation (E13-EIS). + Y would be connected to YOO, - Y
to YSS, and the common or ground of the supply would be
connected to YAG. This procedure is illustrated in Figure S.
An important note for use of the RS-232C port is that the
board must be run at either ±6 Y or at +6 V with - YRS
connected to - 6 Y for proper operation of the MC1488 RS232C drivers.

~
Mark

Data

Low Band

High Band

1270 Hz
1070 Hz

2225 Hz
2025 Hz

Space

Qng = Transmit On Low Band
Receive On High Band
Ans= Transmit On High Band
Receive On Low Band
FIGURE 1 -

Ben 103 Frequency Designations

THEORY OF OPERATION
Asynchronous digital data is input from the RS-232C port
or from the data in coaxial connector (TTL logic levels) by
proper selection of SI. The MCI4412 then transmits
either a mark or space frequency in the form of a digitallystepped waveform (the output of the resistor-string 0/ A).
This waveform is ac-coupled to remove any de offset. R3 sets

*Before actual connection to the telephone line, the FCC requires that either a DAA be placed between the modem and the line or that the entire
modem be certified and registered under the provisions of Part 68.

+10
0

-10

Y"\

f-- ~Jow Ban~

\ /1

c
<0

'"

-30
-40

High

B~n{"" ~

~I :

-20

~

;r---- '-l

-

IA :
.............

-- -- ~-

-50

-60

'j

-\-:
I
I
I

---

V

.-"

Mark-to-Space EDD
Low Band = 484 ~s
High Band = 521 ~s

Start 0.0 Hz
RBW 30 Hz

- -~
r--

Stop 4000.0 Hz
VBW 100 Hz

Start 15.0 Seconds

FIGURE 2 - Frequency Response of
High Band and Low Band of MC145440

3-103

•

AN891

+V

RS·232
01 2N2222

Data
0"

VOO

VAG

Y H'~'~

+V
SIG
GNO

-V

-VRS

SIG
GNO
SIG

TTL

10IIF +V

E14

~1

GNO

10

lO,.F

~
-G----

Data

•

VSS

VSS

TTL

-V
+V
+V

TTL

R23

330

hE

Echo
CR4

15
12

,.

E10

,

Ell !U 5

~

Type

lN914

YE121CClTTI
N

u

RxRate

3

~

RxData

"'
~

NC

-;
"u

"

10

-V

ST

XO

Xl

TxCar

RxCar

-VRS

MODE

TP2

+v

~4) S3

R3
10k
-V

+V

Tos.

SIG
GNO

TP5

R14

2k
+V
+V

+V
CR2
R20
33k

CRl

R17
2k

lN914

14
R21
470

* May

16M
Rl.

be needed for noisy environments. Should be '" 500-1000 pF.

FIGURE 3 - MC14412/MC146440 Modem Evaluation Board Schematic

3-104

+V

I

AN891

TP1

...

~~

Tl

t - - - - - - - -....""I/\~ _-.2..... " -.....--../1.1\.1'---1""""':>
T.p
ZN1

+V

+V

?::
1(1

lEO

VLS

-V

----1--1

e12
01

R15
10 k

1

3-105

f'

!E7 (4 MHz!

f-'-----.J.'-2..:'-;r6 "

-V

136864
MHz)

•

AN891

TTL Data.ln

TTL Data Out

•

G-----o
G-----o
O-{)-4@
E2

El

E3

II)

G
u

~!@

For EIther
1 or4 MHz

C,,,tol,

@ L __ J _.0'.
0-'-:'--0"

U2

E5

E4

E6

"'~E7

~~

0----0

@)'@)D'®D
~

a

TP5

(][]

a am

OTP4

TP3

Strapping and Switch Information
E1. E2. E3

Selects logic input/output levels. E1-E2 for CMOS
swinging VDD to VSS. E1-E3 for TTL swinging
from VAG up.

E4. E5

Provides mid-supply reference voltage for use in
single-supply operation; left open in dual supply.

E6. E7. E8. E9

Selects crystal frequency.
E6-E7 4.0 MHz operation
E6-E8 3.6864 MHz
E6-E9 1.0 MHz

E10. E11. E12

Selects U.S. or CCITT operation.
E10-E11 U.S.
E10-E12 CCITT

E13. E14. E15

Selects signaling ground.
E13-E14 SIG GND = VSS (singly supply)
E13-E15 SIG GND=VAG (dual supply)

E16. E17. E18

Gain strap in.
E18-E17 Gain '"
E18-E16 Gain out

Switches
S1

Selects originate or answer mode of operation.

S2

Selects normal operation or loop test in which the
MC14412 and MC145440 will modulate and
demodulate on the same band. Data input to the
MC14412 will then be looped and available at
MC14412 output.

S3

Selects normal operation or a test mode where lxl
input is connected to VAG. This allows measure~

ment of receive level.
S4

FIGURE 4

3-106

Selects RS-232C data or external TTL data.

AN891
more duty-cycle distortion and perhaps exceed the 50 ± 2"7.
duty-cycle requirement of the MCI4412.
The carrier detect circuit consists of U5B through U5D.
The output of the first comparator (pin 13) goes into a decay
control network formed by RI6 and C13. When carrier is
detected, pin 13 goes low, discharging C13. As the waveform
passes below its peak, CI3 begins to charge through RI6 and
therefore controls the decay response of carrier detect. The
network on the output of U 5C pin 14 controls the attack time
and consists of RI7, RI8, CRI, and C14. When carrier is
present, pin 14 goes low, discharging CI4 through R18.
Therefore, carrier must be present for a certain amount of
time before it is recognized and causes pin 2 to switch low.
The time responses for the attack and decay networks are:
Attack time=Rl8Cl4 In(Y2)= 111 ms
Decay time=Rl6Cl3 In(y2) =52 ms.
Three dB of hysteresis is accomplished by the resistor network of R19-R21. The whole carrier detect circuit will turn
on at a received signal level of - 40 dBm at TP I and turn off
at -43 dBm when operating at ±5 V.
Several features of the MC145440 merit special consideration because of the flexibility they allow the designer. One is
the clock output pin (pin II), which provides a I MHz clock
to the MCI4412 when operating the MC145440 at either I or
4 MHz. The clock select pin (pin (i) controls the selection of
which external crystal to use - 4, I, or 3.6864 MHz. The big

+V

Smgle

advantage here is that a 4 MHz crystal is much cheaper than
a I MHz crystal, although power consumption of the
MC145440 increases slightly. Output levels are defined by the
voltage at the VLS pin (pin 10) for use of either CMOS or
TTL logic. The Vref output (pin 5) generates a mid-supply
voltage between VDD and VSS for use in single-supply applications. As you can see, the design of the MCI45440 was
geared to making the modem designer's task much easier.

RECEIVE SENSITIVITY TESTING
The test set-up for evaluating receive sensitivity in the
originate and answer modes is shown in Figure 7. The procedure for determining the receive level at the line side of Tl
(A and B) is to first adjust the transmit signal level at A and B
to about - 9 dBm (via R3 and with the line side of the
transformer terminated in 600 ohms), which is the maximum
signal level allowed on the line. Then connect the receive
signal and decrease its level until the bit error rate (BER) exceeds I x 10 - 5. Next, close S3 to the test position and
measure the signal level at A and B with a bandlimited
voltmeter, such as the HP 3551 with 3 kHz flat filtering. This
is then the receive sensitivity - the lowest level at which the
demodulator begins to make significant errors on a back-toback set-up. Measured performance on the evaluation board
was - 45 dBm in both the originate and answer modes.

GND

IOptlonal for RS·232C OperallOnl

b

)

0

)

VDD

VAG

VSS

Slipply
Test

-{
-VR5

LSIGGND

RS-232C GND

RS-232C Operation
ReqUires + V of

At Least 6 V and - VRS
of -6 V.
+V Common -V

()

Dual
Supply
Test

VDD

>
VAG

I

)
VSS

6

-V8S

LSIGGND

FIGURE 5 - Power Supply Set-Up

3-107

RS-232C GND

•

AN891

CONCLUSIONS
A simplified method of designing a basic 300 baud modem
with the MCI44l2lMCI45440 has been presented which offers very good performanc.e and ease of implementation. The
attention to detail which is reflected in the options and
features of the MC145440 help the design engineer meet the
variety of modem criteria that might otherwise exclude other

parts. One common design requirement might be for a linepowered modem in which power consumption would be important. Since both the MCI44l2 and MC145440 can work
at 5 V, a very-low-power system can be designed that
operates on only + 5 V. A possible circuit for this application
that stresses minimum cost and power consumption is shown
in Figure 8 with the component layout shown in Figure 9.

Reference
1. K. Sam Shanmugan: Digital and Analog Communication Systems, Wiley, New York, 1979 .

•

MC145440

R5

TxO ",2"-+_ _-,,
3

'Component
R7

+v
120/A

" - Balances
Amplitude
Component

Output of
Duplexer

The purpose of the duplexer is to help reject transmit signal energy from the receive signal.
Theoretically, a duplexer can be "tuned" to achieve infinite rejection - where the phase and
amplitude of the inverting and non-Inverting signals cancel through the duplexer op-amp. In
practice however, telephone line impedances vary enough such that only about 10-15 dB of
rejection can be expected. To attain this rejection, it is recommended that the duplexer components 1R5. R6, R7, and CB m the schematic) be tuned for the impedance and loss
characteristics of the particular type of transformer being used. ThiS will minimize the impedance variation of the line. Once these component values have been determined for a particular transformer type, further trimming is usually unnecessary on a board-to-board basis. A
recommended procedure for balancing the duplexer, which was used in finding the values m
the schematic, IS as follows:
1. First, put the Txl input to VAG. Next, connect a 600 ohm signal source to points A and
B (nominally -10 dBm @ 1170 Hzl. Tweak R5 until the loss at point A and B is eXactly
6 dB. This allows maximum power transfer through the transformer.
2. With R5 at this new value, replace the signal source with a 600 ohm resistor at points A
and B. Now feed the Txl input with the signal source at the same level and frequency.
3. Now tune R7 until the Signal out of TxO reaches a minimum at AO. Then tune CB until a
new, lower mmimum is reached which should be around 30 dB. The phase and
amplitude of the two signal components have now been matched for the best rejection
over the spread of telephone lines.
FIGURE 6 - Duplex., Considerations

3-108

AN891

UUT

TPI

Transmit and Receive
Signal Levels
Measured Here

Modulator

Modulatur

Demodulator

Demodulator

Duplexer

Attenuator
HP 4436A

Receive 300 BPS

Duplexer

Transmit 300 BPS

FIGURE 7 -

Test Set-Up

3-109

•

II
rN';'; 2I
I
I

A21

20 k

m
.....

I
I
I

I

Voo

»
z

------,I
I
I
-.J

A20

10k

MCl4412
VDD
1
16
2 AxCar VDD 15
ST
TO
4 XO U4 Thl*3·+-+-.....;

XI

~-------- Ring

t

EI.-"'U-....L.-

5 R
TxE ",1...
2+-'='=----l
~ AxA TxD>bl"l,--=-_-..
8 AxD
M
VSS TxCar
, 0.1 "F

VDD
Co)

.....
....
o
I

w-.--Tip
R24

Ion

TP2

O.l,.F
A5
10k

U

Rm

~:

300

1'1
VDD
R19
< 10k

~

5to12Voits

VDD _
AnalOg~

GND

C12

t 12k

VDD

Rx

alA

'*

...

VSS~

VDD

t f'G
R13

RS
10k

Carrier Detection 200 k R14
560 of R16

NOTES:
1. Optional Pot PI in lieu of A22 and A23.
2. Optional Ul with R20 and R21 to get add,llonal 6 dB gain. for more receive sensitivity
3. If Ul IS not used, Jumper R20 and R21.
FIGUAE 8 -

Modem 1 Board MCl45440/MCl4412

l>

Co)

.....
I

.....
.....

Rl
R2
R3
R4
R5
R6
R7
R8
R9
RlO
Rll
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24

-

Cl
C2
C3
C4
C5
C6
C7

-

-

C8 C9
ClO
Cll
C12
C13
C14
Ul
U2
U3
U4
Xl
Pl
Dl
Ll
Tl

-

332
10 k
24 k
10 M
10 k
3 k
20 k
10 k
1.6 M
2 k
750 k
2 k
2 k
200 k
33 k
560
N/A
300
10 k
10 k
20 k

Z

o

0

0

"1 i
11

10
0.1
0.068
20 pF
20 pF
0.1
01
N/A
0.01
1 pF
N/A
0.1
0.1
0.1
0.1

R20

•

.!.

OC2

C12

~01ro

stIH,
C8

0

(3

!

R23g22
R19

fCl

o-1FC)
o-n=G Jl

i

C6

FIGURE 9 -

r-



100:

Z
19

Modem 1 Board MCl45440/MCl4412

II

o

CO
CO

.....

AN·870

@ MOTOROLA

Application Note

2400 BPS DPSK MODEM SYSTEM
USING THE MC6172/6173
Prepared by
Richard Hall
MOS Telecommunications Applications

two bits of data in the 2400 bps mode is called a dibit and the
time that modulation begins to encode each new dibit is called dibit clock. The coding scheme of the U.S. and European
options for )200/2400 bps is as follows:

INTRODUCTION

•

The tremendous growth in data communications has spurred the development of many diverse modems for use on the
normal dial-up telephone network and on private leased
lines. One of the more prominent ones is the type 201, 2400
bps (bits per second) system such as the Bell 20 IB/ C data set
or the system described in CCITT specification V.26/V.26
bis. This type of modem uses a technique of modulation called differential phase-shift keying (DPSK) in which a carrier
frequency is phase modulated to represent different information states. The Motorola MC617216173 chip set is an
NMOS LSI subsystem designed to perform the modulate/
demodulate and control functions for implementing a DPSK
modem. Pin-selectable options permit compliance with either
U.S. (Bell) or European (CCITl) requirements and also
allow selection of the standard data rate of 2400 bps or a
secondary rate of 1200 bps. By using the MC6172/6173 chip
set as a core, a complete modem system can be easily built
that offers high performance at a surprisingly reasonable
cost.

1200 bps
Data

a
1

2400 bps

Option C Option D
CCITT
U.S.

+90°
+270°

+45°
+225°

Dibit
Data

00
01
11
10

Option A Option B
CCITI
U.S.

0°
+90°
+180°
+270°

+45°
+135°
+225°
+315°

The term "differential" in DPSK refers to the fact that
each time a phase shift occurs, it is in reference to the
previous phase. This process is shown in Figure I. Differential modulation eliminates the need for a synchronized
reference at the transmitter and receiver. In our system, the
MC6173 demodulator derives its timing synchronization
from the incoming signal, although it does require an external clock for internal sequencing and to provide a reference
input to the internal phase-locked loop (PLL) used to derive
the carrier frequency and the 1200 Hz modulation component (dibit clock).

BACKGROUND
As mentioned, DPSK employs periodic phase shifting to

transmit information through a communication medium.
The primary advantage of this method of modulation is its
efficient use of the narrow bandwidth of a telephone channel
(typically 300-3000 Hz). This efficiency comes about through
the use of multiple phase states which allow higher data rates
within the same channel bandwidth. As a specific example,
let us consider how DPSK is done in the MC6172/6173
system. The basic signal spectra for MC6172 modulator is
from 600 to 3,000 Hz because it modulates an 1800 Hz carrier
at a 1200 Hz rate (fcarrier ± fmod>. In the 1200 bps mode,
only two phase-shift states are used to encode each bit of
data per baud transition (The baud rate is the actual signaling
rate of the carrier). By using four phase states, two bits of
data can be encoded at each baud transition which results in
twice the data rate within the same channel bandwidth. Each

FIGURE 1- DPSK Format

Detection of DPSK signals occurs in one of two ways: differential coherent or differential comparative. Differential
coherent uses a local noise-free reference in phase lock with
the incoming signal for demodulation. This is the method
used in the MC6173. Differential comparative delays the in-

3-112

AN870
coming signal one symbol transition time (or baud time) and
compares this information with the next symbol change.
Although differential coherent detection is more complex, it
offers a significant signal-to-noise-ratio improvement of 2.3
dB over comparative detection for a 4-phase system in the
presence of white noise.
To allow for detection of the 1200 Hz modulation component or dibit clock, an AM envelope is superimposed upon
the output signal of the MC6172 modulator. This envelope

also serves to define the waveform shape during the transition from one phase to another which occurs at the positivegoing edge of dibit clock. As shown in Figure 2, the AM
envelope of bordering dibit intervals are summed together to
provide a smoother waveform with less spectral content than
one with instantaneous phase shifts. The demodulator
system uses a full-wave rectifier and a narrow band-pass
filter to recover this envelope information for internal
synchronization .

>tl"'·f-------

1
.......- - - - - - Dlbit - - - - - - ·..

Dibit - - - - - - ·
.."'1

---------~------~I--------_~------~I.-1800 Carrier

AM

FIGURE 2- DPSK Waveforms

AN870

•

of 6-bit digital words. The 01 A converter then constructs a
PAM waveform from the digital words. A low-pass filter
limits the output frequency spectrum before transmission to
the line. After propagating through the communication
medium, the signal appears at the input to the demodulator
system containing the MC6173 demodulator. The signal is
then amplified, filtered by a band-pass filter and phase
equalized. (The need for equalization would depend upon
the quality of the line.) At this point, the signal splits into
two paths: one through an automatic gain control (AGC) circuit and the other through the carrier detect circuit which
merely indicates to the demodulator that sufficient signal
energy is on the line. The AGC stabilizes the level of the
signal before feeding the 1200 Hz envelope filter and the
AID converter. The 1200 Hz filter recovers the dibit clock
from signal for synchronization with the internal dibit clock
of the MC6173. The AID converter uses successive approximation to transform the analog signal into a digital bit
stream that is input to the demodulator. The MC6173
decodes the digital DPSK data into the original data which is
then transmitted through another RS-232C interface to the
receiving DTE.
The system as shown in the block diagram is only in a
simplex mode of operation in which data flows in only one
direction all the time. For half-duplex operation, where data
flows bidirectionally but not simultaneously, a MC6l72 and
MC6173 would be needed at both ends of a 2-wire connection. In order to realize full-duplex operation where data
flows bidirectionally and simultaneously, a 4-wire connection
would be required.

THE REAL WORLD
After the MC6172 modulator has received the input serial
data, grouped it into dibits (2400 bps operation), and modulated the 1800 Hz carrier accordingly, the output DPSK
signal is thrust into the real world of the switched telephone
network. This environment typically contains such line
impairments as noise, phase jitter, crosstalk, frequency
translation and high voltage spikes. Of these, noise and
phase jitter are the most important to consider in a DPSK
system like the MC6172/6173. General background noise is
usually treated statistically as a guas~ian distribution. In
subsequent performance tests, the noise mentioned will be of
the white guassian type. Phase jitter is a measure of the phase
modulation the communication environment is imposing
upon the line signal and is usually measured in degrees peakto-peak at some frequency of modulation (°p-p/Hz).
To overcome some of the impairments in the normal dialup telephone network, Bell and others can offer the modem
user a variety of private leased lines which do not pass
through any switching apparatus. These lines typically have
special conditioning for higher quality transmission. A very
popular choice is the 3002 voice-grade line which comes in
five different levels of quality; CI, C2, C4, C5 and the basic
unconditioned line. It is characterized by a higher SNR, flatter amplitude response, better phase linearity and less transient interference than dial-up lines. With appropriate
equalization as will be described later, the MC6172/6173
modem can be used on any of the 3002 lines in addition to its
dial-up line capability.
SYSTEM OVERVIEW
A block diagram of the MC6172/6173 modem system is
shown in Figure 3. Serial data is output from the business
machine or DTE (Data Terminal Equipment) as it is usually
referred to, and transferred to the MC6172 modulator via an
RS-232C interface (optional). Under the control of the DTE,
the modulator produces a DPSK signal which is in the form

BUSiness
Machine
IDTEI

;:::..;
R
S
2
3

MC6172
Modulator

2-

Modulator System Design
The modulator design procedure is relatively straightforward and does not affect overall modem performance a great
deal. The complete circuit schematic for the modulator
system is shown in Figure 4. A thorough pinout description
of the MC6172 will not be presented here; therefore the

- -DIA

Low-Pass

-[3>-

Telephone
Line

7-"'"",.
Equalizer

Carner
Detect

~-:H:i
-

Env
Detect

AID

f---.
~

~

MC6173
Demodulator

FIGURE 3- MC6172/6173 Modem Block Diagram

3-114

-

'Ii"
S
2_
3

2

'--

BUSiness
Machine
IDTEI

Tx
Clk "

•

•

D:~a>

"I

SCRAMBLER PARTS
U22
MC14006
U23
MCl4070
U24
MC14069
U25
MCl4011
U26
MCl4013
NOTES
1. All Resistors ± 1%
All Capacitors ± 5%
2 Bypassing of power IS recommended at all chips
3 Tl IS a 600 600 n telephone transformer

+Vref
12.5VI

•
U2
1-L-+5V
MC1403
Rl +Vref
124 k

F
G
S2

II

-=
+5V

111

I

C1I

o

B
"0
0

"

(L

-=

/12

17 ILSBllO A6
VEE

'"

"'5

:>

v

•

OTPI
14 Vp_p Full Scalel

C5
20pF

5:1;

x

N

~

-=

3
R2
2k

22 IMSB) 51. ,
+ Vref
21
6·
20
7
Out l4
19
8
U3
18
9 MCl406

E3~~1

Co)

.....
.....

R12
2.48 k

+5V

"-

10
u

L--J

TP3
TP4

-12

:1;

-

-

TP5
10M

13 110

RlO

R13

Yl

-=

1.8432 MHz

18432 MHz

o

C7 ....L±O oo5%....LC6
15 PF

I

1

R4
261 k
Sl
()---oI(

Ext
Clk

30 PF

[L~~

l1it:

Cl
lOOPF"J

2

-=

+ 12 dBm
to -3 2 dBm
FIGURE 4 - 2400 BPS DPSK Modulator System

___I _____ _

3

:J>
Z

....,

CO

o

AN870

•

reader should consult both a MC6172 and MC6173 data
sheet for full details. The clock source for the MC6172 is a
simple CMOS inverter oscillator using a 1.8432 MHz ±
0.0050/0 crystal as a time base. The MC6172 uses this
reference frequency to derive the 1200/2400 Hz transmit
clock. the 1800 Hz carrier and the dibit clock. The External
Clock input (pin II) can be used to supply the modulator
with an external transmit data clock.
Control of the modulator by the DTE is established
through the R8-232C interface and consists of these signals:
CTS. RTS. Tx Data and Tx Clk. Tx Data is the input line for
the serial digital data and Tx Clk is the clock provided by the
modulator for clocking in the data. RTS stands for RequestTo-Send and essentially is the output enable of the
modulator. A high-to-Iow transition on RTS initiates a training sequence of constant marks (a mark is a logic one; a
space is a logic zero) to be sent for a duration determined by
RTS-to-CTS delay selected by CTSI and CTS2 (pins 3 and 2.
respectively). When this delay has timed out. the CTS (ClearTo-Send) function. pin 4. falls low indicating to the DTE
that normal data transmission can now begin. To terminate
transmission. the DTE would take RTS high. A secondary
output. DRTS (Delayed-Request-To-Send. pin 5) indicates
the exact time the modulator actually ceases transmission.
The small delay from the rising edge of RTS and the rising
edge of DRTS is required to allow the residual data in the
MC6172 to be sent after RTS goes high. An important note is
that signals from R8-232C are inverted from the true logic of
the MC6172; consequently. a mark to the interface is the
most negative voltage level while in the MC6172 it is the most
positive logic level. The Motorola MCI488/89 R8-232C
interface chips provide the necessary inversion and logic
shifting for compatibility between RS-232C and the
MC6172/6173 modem system.
DPSK data is presented at U3. an MCI406 DI A converter.
in the form of a 6-bit digital word. A reference current is supplied by an MCI403 + 2.5 V ref through RI. This current
(about 2 rnA) flows into pin 12 of the 1406 and is used as a
reference to supply an output current at pin 4 proportional to
the input digital word (pins 5 through 10). U4 is a simple
current-to-voltage converter which establishes 4 volt peak-topeak signal at TP I. Because the signal at TP I is a PAM
waveform with excessive high-frequency content. a low-pass
filter is required. A fourth-order 0.01 dB ripple Chebyshev
was chosen and its design equations are given in Appendix I.
This filter provides excellent amplitude response and has a
small envelope delay distortion (EDD) of 61 /LS (referenced to
delay at 1800 Hz). The output of the filter. pin 6 of U6.
passes through an adjustable gain buffer (U7) that establishes a signal level range of + I to - 3 dBml600 ohms at
TP2.
Before actually connecting the output of the modem to a
dial-up switched telephone line. Bell requires that a DAA or
Data Access Arrangement be placed in series between the
modem and the line. The purpose of the DAA is to protect
the line from faulty operation of the modem. such as improper ground isolation or excessive power transmission. A
DAA can be leased from various suppliers or can be built by
the user and then certified by FCC under specification Part
68.
DEMODULATOR SYSTEM DESIGN

The demodulator system is shown in Figure 5. The signal
voltage occurs across Tip (1) and Ring (R) of transformer
T2. The signal is then amplified by 8 dB via U9 and then fed
into the receive band-pass filter (400-3600 Hz pass-band).

This filter is constructed by cascading a 2nd-order Chebyshev
high-pass with the 4th-order low-pass used in the modulator
system. The design equations for the high-pass are also given
in Appendix I.
After filtering. the signal can be equalized if required to
minimize the EDD of a typical 3002 voice-grade line. The
EDD is usually worst about the channel band edges because
that is where band-pass poles begin to accumulate phase. The
schematic for the equalizer and its EDD response is shown in
Figures 6 and 7. respectively.
The conditioned DPSK signal is then output at TP7. From
there it goes to the carrier detect circuit and the AGC. The
carrier detect consists of a 20 dB gain stage (U9D) and a comparator formed by U18 and UI9 (MLM311) that will provide
at least 3 dB of hysteresis. As shown. the circuit will turn on
with an input level of - 43 dBm or greater and will stay on
until the signal falls to - 48 dBm. These trip points can be
adjusted by changing the divider network of R43-R45. The
output of the carrier detect circuit is at U34 pin 6 which is
connected to FCar (pin 2) of the MC6173. A negative transition at this point indicates to the demodulator that sufficient
signal energy has been detected. If there is noise greater than
- 43 dBm on the line. then the trip points must be raised to
prevent false triggering. The AGC consists chiefly of a
Signectics NE571 compandor chip. This is a bipolar device
that combines an integrated rectifier and variable gain
amplifier in one package. The signal at TP7 is ac .coupled
into pins 2 and 6 of the NE571. the rectifier and signal
inputs. respectively. C6 is the rectifier capacitor used to filter
the signal at pin 2 and it directly affects the time constant of
the circuit. After rectification and filtering. a dc level is obtained to control the gain of the signal at pin 6. The output of
the AGC is taken from pin 7 of the NE571 and ac coupled to
TP9. As shown. the AGC will maintain an output level at
TP9 of 0 dBm ± 1.5 dB from - 48 to 0 dBm at the input to
the demodulator system (pins I and 2 of T2).
The signal at TP9 is routed to the 1200 Hz envelope detect
circuit and the AID converter. The envelope detect consists
of a precision full-wave rectifier and a 1200 Hz band-pass
filter. The output of the band-pass is ac coupled into U13.
which is a comparator used to square the waveform before
going into the Env input (pin 10) of the MC6173. The
envelope signal is essentially the dibit clock of the incoming
signal and is used by the MC6173 for synchronization with its
internal dibit clock during the initial training sequence of all
marks.
The AID subsystem consists of an LF398 sample-and-hold
chip (UI2). an MCI4559 successive approximation register
(U17). an MCI408 DIA (UI6). a current-ta-voltage converter (U21) and a comparator (UI4). Operation of this circuit is initiated by a negative transition of UI2 for it to
"hold" a voltage sample of the signal at TP9. U17 begins to
construct a digital word by setting successive bits and comparing the subsequent output voltage at U21 pin 6 with the
held voltage sample at U12 pin 5. If the voltage sample is less
than the output voltage of the DI A. then that particular bit
of U17 is set; otherwise it is reset low. This process continues
at a 460 kHz rate until a 7-bit word has been constructed and
shipped serially to the MC6173 from U17 pin 5. The clocking
for the AID is provided by the MC6173 through the ADS
and ADC outputs (pins 8 and 6).
To summarize the operation of the demodulator system.
assume that there is no data being sent by the modulator and
the demodulator is in an idle condition. FCar is then at a high
state which has effectively disabled the MC6173. The
modulator initiates transmission at some point which. for the

3-116

l>
Z

CO

.....
o

~
R2

R3

10k-

158k-

~-etect]

[~I

+12

+5V

R4O"
lDk

.12

EquahzerStrap-ln

E2

El

,-------«~--- -----;»>--------------~
+12

Co)

•

~
vol'

~

e7.1~

~

.....
~zF;lte~1

ClO
1

TP9

R2B

R29

R30

10k

10k

10k

NOTES

±1 dbm

C19
20pF

BI Oln
U17
MC14559

R34

+12~-'2

SO~A
CK

B

Specifies ± 1% ReSistor
BypaSSing IS recommended at all chips
All capacitors m microfarads unless noted otherv.lse

U9, Ul1
Ul0
U12
U13, 14, 18, 19
U15
U16
U17
U21,37
01·05

MlM4741
NE571N

LF39SN
MLM311
MC14OD7

MC1408
MC14559
MC7415
IN914

10k

FIGURE 5 - 2400 BPS DPSK Demodulator 11 of 2)

II

Quad Op-Amp (14 Plnl-any 741-tvpe cp-amp wdl do
Compandor/Varlable Gain (16 Pint
Sample/Hold (8 Pint
Comparator (8 Pmt
Dual Complementary Pair/Inverter 114 Pm)
D/A (16 Pin)
SAR (16 Pin)
Op-Amp (8 Pint
Diodes

II
l>
Z

Eye Pattern Generator (Optional)

CD

.....

AID Strobe

AID

U33

AID

~

U33 100 pF

U33

~4

9
10

~6

12

A
B
C

U34

~
Rx Clk 20

m;;:

~9

CCor ~

12 D2

"::"

~ Dl
~ DO

4

..5

CD

17 PSS

G

24 DRS
VSS

4

71, 01
,DC

00 Eye 5

J

ReSistors ( ± 1%I
R50= R58=4.64 k
R51 = R59=9.53 k
R52= ROO = 19.1 k
R53= R61 =37 4 k
R64= R62= 75 k
R55= R63= 150 k
R58= R64=301 k
R57= R65=604 k

14
"::'

11

i'PE 15Ci5
18 3

-i=-1

9
'""iT31

P.""g
"

0-

~~-

01

~ DO

(16
(16
(16
114
114

Pinl
Pin)
Pin)
Pinl
Pin)

02

~

-

Pin
Pin
Pin
Pin
Pin

8= GND.
8= GND.
8= GND.
7=GND.
7=GND.

Pin
Pin
Pin
Pin
Pin

16= +5 V
16= + 5 V
1= + 5 V
14= +5 V
14= +5 V

5
'-

--Zj

DC01
91

4

3 10
04
U28

N

"'

<0

a::

a::
U32

13 D3
12

1L-

+5VJ 21
13 12
15 DOl

111

2
04

U28

C
11

FIGURE 5 - 2400 BPS DPSK Demodulator System (2 of 2)

R 14
"::"

,l.L
~
7

00 2
R
1

R
1

"::"

03

~
,......i DO

7

00 2

R 6

'"a::

<0

-.!l.~

03 ~

13 D3
12

~"'-

MCl4015
MC14175
MC14049
MC14013
MC14073

~
a::

iB
fR
a:: a::

+5V

U27. U28
U29-U32
U33. U34
U35
U36

2

2

U27

"-

'"a::

.J.Q....7

+5V

C

"::"

19

U20
MC6173

,....----2 U27
.--.! DO 00

111

fB
a::

TP12
goo
EyeOut

03 .1§......

13 D3
12

Q4

15 D

R6

'"'"a::

~
a::

9
'""iT:tr

R
1
+5V
21
13 12

3 10
04
U27

~ fa
a:: a::

a::

01 7
00 2
R
1

TPll

"'

03~
02~

13 D3

10 Env

F

~a::

~

U36

Co)

....
....

2

+5V

goo Eye 4
I

3

Rx Clk
Rx Data

Rx Data 9
DBC 21

6 ADC
8 ADS
2

~

E

1,4

U34

15

14

5 D R
1 2
U35 0
8
3C
S
6

Clk

23 RDI

U33

12

U33

+tV 1.8432 MHz

VCC

10 k
11

+~r--4--

U33

o

+5V

Cb
a::

~
a:

TP13
0°
Eye Out

~

zco

A104
10k

~1p~t
A101
3.92 k

~

A105
10 k

A103
23.7 k

C101
0.01

~~
A102

~
C102
0.01I

II

"-+--I

---+-- E2

AN870

4

~c:

3

o·

~

1;;

<5
~

~ 2

i

TYPICaI3002
Line Simulator
EDD Response
IWorst-Case Type
Simulatorl

g-

1
w

c:i

ow

..

2000

1000

3000

f. Frequency IHzl
FIGURE 7 - EDD Response

specified training period, consists of all marks. The carrier
detect circuit is turned on, taking FCar low and enabling the
MC6l73 to widen its PLL to lock onto the incoming signal.
The envelope detect presents the recovered dibit clock at Env
for internal synchronization during this time. After the training period times out, normal data transmission occurs and
the Env input is ignored. All subsequent timing for this data
message is derived directly from the DPSK signal. To
lengthen the training period at the MC6173 in which
envelope information is taken from Env, the Cars input (pin
15) should be taken low for the amount of the extended
period.

a resistor-scaling network that produces an equivalent
discrete voltage level. As more data is clocked out, a PAM
staircase waveform is constructed which iIlustrates the 0° and
. 90° carrier shifts. To see the waveform on an oscilloscope,
attach probes from two channels to TPI2 and TPl3 and
overlap the patterns on the scope while triggering on Dibit
Clock (pin 21). The round spaces in the pattern are the eyes
and if they are clearly defined the signal quality is high. As
more noise and jitter perturb the signal, the eyes tend to
become fuzzy and close up. Pictures of actual eye patterns
for both phase options are shown in Figure 8.

Scrambler
A scrambler circuit is shown in the upper-left corner of
Figure 4. This circuit will scramble the serial data with a
511-bit psuedo-random pattern as called for in specification
V.S2. The scrambling of data is done in an attempt to
minimize demodulator sensitivity to long strings of spaces.
When the scrambler is enabled (Scramble Select = 0), the Test
Pattern Enable pin (TPE) should be left high. The MC6l73
demodulator has a built-in descrambler that is enabled by
taking its TPE input (pin 18) low.

PERFORMANCE TESTS
Performance data on modems is usually a nebulous area of
comparison. One modem manufacturer may specify his
modem using C-message weighted noise while another may
use 3 kHz-flat weighting. Test equipment will vary and line
simulators will have different characteristics. To validly compare modems, one must use the same equipment setup and
test procedure. In the following tests, the equipment and
procedure will be clearly stated.
The equipment setup is shown in Figure 9. The Bradley
2A12B disturbence generator is designed to simulate such
line perturbations such as phase jitter, frequency translation,
AM interference and white noise. The Comstrom-S.E.G.
FA-I445 simulates a worst-case 3002 unconditioned line. The
HP 3551 is an ac voltmeter that can measure noise using different weighting schemes. In all cases, noise measurements
were made using the 3 kHz-flat filter while modem signals
were measured in the Receive Tone mode (0-60 kHz bandwidth). The HP 1645A data error analyzer provided the
serial test data and bit error rate (BER) figures. In all cases,
the data pattern was the 511-bit psuedo-random sequence.

Eye Pattern Generator
The MC6173 demodulator has the capability of producing
an "eye" pattern through the use of the 90° Eye and 0° Eye
outputs (pins 4 and 5). An eye pattern is a graphic indication
of the incoming signal quality. The circuit for generating an
oscilloscope picture from the 90° and 0° Eye pins is shown,
surrounding the MC6173, in the second page of Figure 5.
U27 and U28 are serial-to-parallel data registers that allow
the eye information to be clocked out. The AID Strobe output of the MC6173 is used to clock out the eye information to

3-120

AN870

The performance tests, shown in Figures 10 through 13
are:
Figure 10-This is a test of back-to-back performance
with white noise and phase jitter added for
phase option B. Degradation in SNR is about
2.1 dB at 1 x 10- 4 bit error rate.
Figure ll-Same test as in Figure 10 with option A
selected.
Figure 12-Frequency translation effect on option B performance.

Figure 13-Performance when an S.E.O. 3002 Line
Simulator is placed in the signal path. The
equalizer used is the one described in Figure 6.
The curve shows the worst-case performance
that can occur with a worst-case 3002 line and
the equalizer strapped in. On a typical 3002
line, the equalizer will improve performance
considerably.

Phase Option A

Phase Option B
FIGURE 8 -

Eye Patterns

HPl645A
Data Error

Data
Tx Clock

Data
Rx Clock

Analyzer or
Equivalent

'--

'---

Modulator
System

-

Bradley
2A/2B

or EqUIvalent

f---

S E G. FA-1445
(Figure 14 onlyi
or EqUIvalent

IT
HP3551
IBridgedl

or Equlv.

FIGURE 9 -

Equipment Setup

3-121

Demodulator
System

II--

AN870

10- 2

BER

25' p-p/60 Hz Phase Jitter

1 x 10- 3

s

¥J

'"

0:

0:

e

g

UJ 10- 4

~ 1 x 10- 4
iii

iii

0:-

•

25' p-p/60 Hz Phase Jitter

10- 3

W

SS-

III

III

1 x 10- 5

10- 5

7

8

9

10

11

12

13

14

10- 6 L-,--r-,--r-,---ir-,--'-r-.l-6
8
9 10 11 12 13

15

Signal- To-Nols~. Ratlo IdBI
FIGURE 10 -

Signal-To-Noise RatiO IdBI
FIGURE 11 -

B Mod 2400 BPS Back-To-Back 511 Test Pattern

10- 2 .

A Mod 2400 BPS Back-To-Back 511 Test Pattern

10- 2

- 7 Hz Frequency Translation

10- 3

10- 3

;;;
"

0:

e
'E1O- 4

iii

0:W

III

10- 5

10-

10-6
7

8

9

10

11

12

13

14

~-r--~~--'-~r--r--r-~--'---

10

15

I

Signal-To-Noise Ratio IdBI
FIGURE 12 - B Mod 2400 BPS Frequency
Translation 511 Test Pattern

FIGURE 13 -

3-122

11

12

13

14

15

16

17

I
I
Signal-To-NolSe RatiO IdBI

18

19

20

B Mod 2400 BPS 3002 Simulator 511 Test Pattern

AN870

CONCLUSIONS
The MC6172/6173 modem system has been shown to be
very effective over differing line conditions. The general
design procedure for implementing this system has been
presented so that easy modification is possible. The ability of
the MC6172/6173 modem to operate synchronously over the
dial-up telephone network without complex automatic
equalization offers the user an attractive choice for mediumspeed data links.

For this design procedure it is necessary that m:S I.
4Q2
Thereforeml:S _--=~-=-= 0.7573
4(0.5746)2
n=

-

Choosem=O.1

I ± (l-4mQ2)Y,

2mQ2

2mQ2

either value obtained is valid

APPENDIX I
4th-Order Chebyshev Low-Pass Filter Design
This filter was realized by cascading two second-order
Salen and Key filter sections. The design equations were
taken from INTRODUCTION TO THE THEORY AND
DESIGN OF ACTIVE FILTERS by Huelsman and Allen,
pages 157-158. The general circuit realization for a Salen and
Key is shown below.

n = 28.25675 for first stage
RIC2=

I

= 2.63 x 10- 5

2(pi)(fC>(mn) Y2
Let C2=0.01I'F
Then RI = 2.63 kO----------- > 2.61 kO
R3=nRI=74.315 kO---->75 kO
C4=mC2=0.00lI'F

+

The second stage was designed using the same equations and
resulted in the following values for Q2 = 1.7237 and fc =
3600:

C2=0.01I'F
C4= 100 pF
Specifications:
Pass-band ripple = 0.01 dB
Op-amp gain = K = I

fc = 3600 Hz

RI =7.87 kO
R3=249 kO
2nd-Order Chebyshev High-Pass Filter

Pole Locations (normalized):
_a_ _b_
- 0.6762 ± j .3828 first stage
-0.2801 ± j.9241 second stage

Specifications:
Pass-band ripple = 0.01 dB
Op-amp gain=K= I

Q = Quality Factor = (a2 + b2) Y2
--2-a-

The general Salen and Key high· pass realization is shown
below:

fc= 400 Hz

where a= real pole coordinate
b = imaginary pole coordinate
QI = first stage Q = 0.5746

+
Q2 = second stage Q = I. 7237
Let n=R3 and m=C4
RI
C2

3-123

•

AN870

For minimum Q, m should equal 1 which reduces the above
equation to:

Pole Locations (normalized low-pass values) =

a
b
-0.6743 ± j.7075

Q = (n)V2

or

n = 4Q2 = 2.101

2

To transform the low-pass poles into high-pass poles,
= 2.745 x 10- 4

R2CI =
aHP=

a

= -0.7059

bHP=

b

= 0.740654

2(pi)(fcl(n) V2

a2 +h2

a2 +b2

Letting Cl =C2=0.II'F, we obtain
Q=0.7247

..!!!..±...!..
Q = (mn)V2

from page 165 .

R2=2.745 kll----->2.74 kll
R4=5.767 kll----->5.76 kll

•

3.. 124

®

AN904
Application Note

MOTOROLA

A FOUR-WIRE FULL DUPLEX
1200 BAUD MODEM IMPLEMENTATION
USING THE MC145450 AND THE MC145415
Prepared By
Steve Bramblett
Telecom Applications
Austin, Texas

THE APPLICATION
The 1200 baud four-wire modem is intended for dedicatedwire type applications where there is a need for reliable and
economical data transmission. This very design may be used
as a basis for a Bell 202T modem where four dedicated wires
are available from the phone company for long distance
communications. Another possible use for this design is for
transmitting data between computers or between a computer
and a terminal where the distances exceed the ability of normal transmission methods. This is a very common problem
when one computer is required to serve users at a site where
an RS-232 link can only work locally (such as 200 feet from
the computer), and some of the users may be as far away as a
mile or more from the computer. Applications where data is
transferred, but recovery of pure digital signals is impossible
due to line conditions, is a possible candidate for the 1200
baud 4-wire modem link.

modulated and the receive output is the digital representation
of the demodulated data. The transmit carrier output is
typically 490 mV peak-to-peak, and the filter gain is 18 dB,
causing the output of the filter to clip, so a voltage divider is
used to control the level of the modulated signal going to the
filter. The receive carrier input expects a squared-up or
digital representation of the receive modulated data. This is
provided by the limiter.
The limiter section is based on the LM339A comparator.
This particular device was selected for its low offset. The offset determines the minimum signal level detected, so a large
offset will limit the modem's sensitivity. Two passive filters
are used to remove low frequency signals such as 60 Hz noise
and high frequency signals such as the 153.6 kHz clock ripple
on the filter output. This ripple is characteristic of switchedcapacitor filters that do not have on-board real-time
smoothing filters. The extra three devices on the LM339A
chip can be used in the optional carrier detect circuit shown
in Figure 2. The limiter components should be located as
close together as possible to help promote circuit stability.
The filter section utilizes the MCI45415 switchedcapacitor filter. This is actually a pair of low-pass filters
based on a Bessel representation. The" A" filter has an inband gain of 18 dB and the "B" filter has a 0 dB gain. In this
design the "A" filter is used as the transmit filter. This
would be the best choice when there is no specified maximum
output level such as in non-telecom short haul modem
designs. In this case the signal~to-noise ratio is optimized at
the receiver. If the application had a level limitation of
- 12 dBm or less, the "D" filter should be used as the
transmit filter so the "A" filter's gain can be used to extend
the floor of the dynamic range. The 2.2 kilohm resistOl'"network is used to provide a mid-supply reference for the analog
circuitry. If the mid-supply level is not held fairly close to
VCCI2, then the headroom for large signals will be impacted
with the signals clipping at the nearest rail. The filter requires
a 153.6 kHz clock to guarantee a 2.4 kHz break frequency.

THE SYSTEM
The application circuit is comprised of six major functions
which are delineated by the dashed lines in Figure I. The
3.6864 MHz oscillator provides the master clock used
throughout the complete modem circuit. The 153.6 kHz
clock generator derives the 153.6 kHz clock, which is used by
the filter, from the oscillator output. The filter provides all
transmit and receive filtering to provide the optimum signalto-noise ratio for the best possible performance. The limiter
takes the received signal and squares it up into a digital
signal. This is necessary for the mod/demod as it is a digital
circuit that provides the actual conversion between tones and
data.
The heart of the system is the MCI45450 modem chip.
This chip is capable of modulating and demodulating data at
rates of up to 1800 bits per second. A detailed description of
this part, as well as all the other parts, exists in the corresponding data sheet. Since no real features of the MCI45450
are used in this design, only two inputs and two outputs are
needed. The transmit input receives digital data to be

3-125

~
I

AN904

The clock generator circuit used to derive the filter clock is
a very straightforward design. The 3.6864 MHz master clock
is divided by 12 with U3. The resulting output is halved by
U5 to give the 153.6 kHz signal. There is an added bonus in
this direct divide down in that the filter's sample rate will be
synchronous with the modem switching rate causing aliasing
to be mimimized.
The master oscillator is a simple CMOS inverter design.
The oscillator on UI would suffice, but since there are
already some spare inverters available, a buffered oscillator
is created by adding 2 inexpensive capacitors. This is much
more capable in terms of drive characteristics.
The line interface is set up for a 600 ohm balanced line. By
exchanging the resistors, the lines can be used at other impedances, however, if the resistors are less than 300 ohms,
the filter may have problems driving the line. The interface
may also be redesigned with a duplexer to provide the basis
for a two-wire system such as a Bell 202S modem.

•

ALTERNATE CLOCK CIRCUITS
The clock circuit made up of the 3.6864 MHz oscillator
and the 153.6 kHz clock generator may be reconfigured into
a number of different designs. Two other possible configurations are shown in Figure 3. The main criteria in all cases is
that a 3.6864 MHz square wave is available to drive the
MC145450 and a 153.6 kHz square wave is available to drive

the MC145415. Since the 153.6 kHz is 3.6864 MHz divided
by 24, the basic generator need only be a divide-by-24. The
3.6864 MHz clock and the 153.6 kHz clock should be synchronous to help minimize aliasing between the MCI45450
and the MC145415.
CARRIER DETECTION
The optional carrier detect circuit utilizes the three remaining comparators on the LM339A. The output of the first
comparator (Pin 2) goes into a decay control network formed
by R3 and C2. When carrier is detected, Pin 2 goes low,
discharging C2. As the waveform passes below its peak, C2
begins to charge through R3 and therefore controls the decay
response of the carrier detect. The network at the output of
the second comparator (Pin 14) controls the attack time and
consists of R4, R5, C3 and the IN914 diode. When carrier is
present, Pin 14 goes low, discharging C3 through R5.
Therefore, carrier must be present for a certain amount of
time before it is recognized and causes Pin 13 to switch low.
The time responses for the attack and decay network are:
Attack time = RSC3 In(O.S) = III ms
Decay time = R3C2 In(O.5) = 52 ms
Three dB of hysteresis is accomplished by the resistor network R7, R8 and R2. The whole carrier detect circuit will
turn on at a received signal level of - 29 dBm at the filter input and turn off at - 31 dBm.

3-126

)-

zCD
o

~

FIGURE 1 - TYPICAL 1200 BAUD 4 WIRE MODEM APPLICATION

10k
01

----+-------,

Transmit ••

VCC

1ITx Car

Receive

-J

4 CTa
5 CTA
6 CTC
RTS
STO
8 Rx Data
9 CD

Tx Level
Adjust

r --- ----------------,
1 'VAG

600

01

0.1

MODG~

ST 6,

I

I
I
I
I
I

8,VSS

Vssl12

MC145450

MC145415

•

~

I

3k
5Volts.

I

I
I
IL ______ _
I
Line Interface ____ .J

.VCC

0.01

10

To Carner
Detect
IOplionJ

GrOUnd,

~

MC54!74HC163
1 Reset
Vce 16
2 Clock
Ripple
3 PO
Carry
4 P1
Out

4

Oscillator

VCC

8 GND

36864 MHz

1

VCC
MC54!74HC04

6 P3
7 Enable P Enable T~

3.6864 MHz

r

20PF

Loadj,.!!.I>~::.9_ _ _~

0.1
':"

V

~7
GND VCC 14
CC

5 P2

oH

~1JII'C

I
I
I

Co)
~
.....

l'II'C

I

2.2 k

X ,n !131

111Rx Car

I

163.6 kHz Clock Generator 1-<- 241

---

(Internall

AN904

Vcc

Vcc

Vcc
R4
R3

0.1

-------J
Carner' ClI--"--~

2k

750k

R6

IN914

2k

Receive

2

Cl

16m

14

10 k
c2

I
-=

13

R5

o.l

C3
VAG

J

VAG

•

R2

CD

O.l

470

R7

200k

R8

33k

VCC

FIGURE 2 - CARRIER DETECT
74HCOO

0-

2,

14

1

~
4

7

24

t!212

.3..
74HC393

23

VCC

VCC

22

r10

21

4
153.6
kHz

20

153.6
kHz
MCl4411

~

19

CJ

15m

3.6864
MHZ

-=

10

14

nI
13

MC145450

c::::J

12
3.686

4MHz
15m

FIGURE 3 - CLOCK CIRCUITS

3-128

'-~--I~ 3.6864 MHz

AN946

®

MOTOROLA

Limited Distance Modem
Using the
Universal Digital Loop Transceiver Chip Family
OVERVIEW
The introduction of the Universal Digital Loop Transceiver
(UDLT) family of Integrated CirCUits aids the design of a high
speed Limited Distance Modem (LDM) With an external clock,
the LDM will transmit asynchronous data at rates up to SO
kbps As shown here with an Internal clock, the LDM can send
as much as 38 4 kbps of asynchronous full duplex data up to
two kilometers on 26 AWG tWisted pair wire The data
transfer IS controlled by the following RS-232C handshake
Signals Request to Send (RTS), Clear to Send (CTS), Data Set
Ready (DSR) and Carner Detect (CD) If the data link IS
operating, CTS goes active In response to RTS gOing active
DSR IS active If the LDM IS powered up If synchronization IS
lost, the CD Signal goes inactive Figure 1 shows a block
diagram of the LDM Figure 10 IS a photostat of the LDM
Demonstration Board - front, and Figure 11 IS a photostat of
the LDM Demonstration Board - back Table 1 IS a parts list for
the slave and master LDM

Differential Phase Shift Keyed (MDPSK) data burst IS transmllted from the master to the slave Then after a slight delay, a
burst IS transmllted from the slave to the master. Since an
eight kHz clock IS typically applied to the Master Sync Input
(MSI) pin, and ten bits are sent to the master and the slave
every MSI period (every 1251's), the transceiver IS effectively
transmitting SO kbps of full duplex synchronous data
The burst's ten bits of digital data are Input on three
different PinS of the UDLT master. The first eight bits are
serially received from the Receive Data Input (Rx) pin The
ninth bit IS from the Signaling Bit Input (SI1) and the tenth bll
IS from the 512 pin. These ten bits are formatted together and
shipped out from the chip on the L01 and the L02 PinS (Line
Driver Outputs) After being transmitted across the line and
received on the LI Pin of the slave UDLT, eight bits of data are
serially output through the slave's Transmit Data Output (Tx)
Pin, one bit on the 501 and one bit on the S02 (Signaling Bit
Output) Then the slave UDLT sends a Similar burst to the
master UDLT

UNIVERSAL DIGITAL lOOP TRANSCEIVER
The heart of the LDM IS the UDLT master Islave chip set
This chip set transmits data at a 256 kbps burst rate uSing a
"ping pong" approach As shown In Figure 2, a Modified

DlTVS. UDlT
Since the MC14541S/19 Digital Loop Transceiver (DLT)
chip set IS very Similar to the UDLT, It IS not difficult to adapt
VO~

~ 300
L-OSR

oSR
MCI45406

~
~



MC 145422

MCI45426

SII
SOl

R,

T,o
MCI4542B
R,o

oCI

Tx

Tx

RxS
SI21-4------------1

SI2
502

S02

f-----------

Figure 1 Limited Distance Modem Block Diagram

3-129

•

AN946

I~

MASTER
MSI

-'

125/"
RECEIVE

TRANSMIT

·1
r-

@l DlT

@l UDlT

1 -hf--

TURN

SLAVE
@l DlT

•

lD

@l UDlT

TEl

l

RECEIVE

I~

L-

TRANSMIT

·1

125/"
l 0 = LINE DELAY

Figure 2. 80 kbps MDPSK Timing Diagram

AHfllR

ID·BIT TRANSMIT BUFfER

SIGNAL BIT INPUT I
SIGNAL BIT INPUT 2

r--,----,,---r-'.....,.--,--,--,-.........S---1+----'--'---.JL--R...lE-CE-IV-E.J.R-EG-IS-T-'-ER---'----'----'"'--,
TRANSMIT REGISTER

RECEIVE DATA
RECEIVE DATA CLOCK
RECEIVE ENABLE

. - - - - - TRANSMIT ENABLE

r-~--'---r--r--~~---r--~~

f4------

TRANSMIT DATA CLOCK

' - - - -..... TRANSMIT DATA
..

SIGNAL BIT ENABLE

' - - - - - - - - - - _ SIGNAL BIT OUT I

r---l--l----------,_
lO·BIT RECEIVE BUFfER

Figure 3. UDLT Receive and Transmit Registers

3-130

SIGNAL BIT OUT 2

AN946

this LDM to use the DLT There are three main differences
between the UDLT and the DLT chips The most Important
difference between the chips IS that the UDLT automatically
adjusts the thresholds on the receive circuitry ThiS allows the
UDLTto optimize Its reception to a particular Ime'sattenuatron
level The DLTs threshold IS externally set, so typically thiS
receive optImizatIon will not be achieved, unless some rather
complex circuitry IS Implemented Also, the DLT requires
external dnvers and transmits square waves Instead of
triangular waves In conclUSion, the UDLT has on board driver
and threshold adjust circuitry, but the DLTs basIc approach
allows driver and threshold design fleXibility

SIGNALING PINS FOR RTS/CTS HANDSHAKE
ThiS LDM uses the S11, S12, SOl and S02 pinS of the
master and slave for a RTS/CTS handshake To perform thiS
task, the signaling channels are used for transmitting the
RTS' CTS handshake The Input at Sil of the master UDLT 15
the RTS signal ThiS information IS transmitted to the SOl of
the slave UDLT chip At thiS pOint. the signal IS looped around
Into Sil of the slave UDLT. and It IS transmitted to SOl of the
master UDLT ThiS signal at SOl IS the master's CTS Signal A
similar configuratIOn IS used for the slave's RTS/CTS handshake on the SI2/S02 channel ThiS allows the RTS/CTS
handshake to verify that the commUnication link IS operating

DATA SET INTERFACE
Since most data from a terminal IS an asynchronous format,
the Data Set Interface (DSI) IS needed to convert data from an

asynchronous to a synchronous format and vice versa At TxD
of the DSI, the asynchronous Signal should begin with a start
bit (logiC 01 After follOWing with an eight or nine bit data word,
the format ends with one or more stop bits (logiC 11. The rate
that the data IS loaded Into the DSI IS determined by the
Internal bit rate generator, whose rate, If 38.4 kbps or less, IS
selected by BR 1, BR2 and BR3 (Baud Rate Select Plnsl An
external bit rate generator can be used for data rates higher
than 384 kbps
Once In the DSI. the data IS stripped of ItS start and stop bits
and loaded In a register Next. the data IS checked for a break
condition, and one of three types of words IS sent, under the
timing control of the DC, CM and DOE pinS If a break condition
IS recognized, the break flag (11111110115 transmitted If data
IS In the register, It IS dispatched. Finally, if no data IS In the
register, a synchronIZing flag (01111110) IS sent However,
regardless of data being In the transmit register, a synchronIZing flag IS also transmitted on a regular baSIS to verify that
synchronization

IS

Intact Furthermore, the transmit circuitry

Inserts a binary 0 after five continuous 1'5 of data, so neither
pattern, (11111110) or (01111110). can be sent as data.
At DCI, DC, CM and DIE control the synchronous data's
receive loading Into the DSI Once loaded, the DSl's receiver
determines If the data IS break or synchronIZing information If
It IS a break or synchroniZIng flag, the appropriate action IS
taken If It IS not. the data IS loaded Into a receive register.
From thiS register, data words are taken, start and stop bits are
added and the asynchronous word IS output on RxD (Receive
Data) althe baud rate selected by BR1, BR2and BR3 Figure 4
IS a block diagram of the DSI

MC145428
DATA SET INTERFACE
h STATUS

T, DATA

SYNCHRONOUS
DATA OUTPUT

DATA LENGTH

}"'' ''''''

BAUD {
RATE
SELECT

DATA CLOCK
XI6 CLOCK

CONTROL

CLOCK OUT

RESET

STOP BITS
CHANNEL
RECEIVER

Rx DATA

DATA INPUT

Rx STATUS
ASYNCHRONOUS I

SYNCHRONOUS I/O

Figure 4. DSI Block Diagram

3-131

II
~

Z

CD

C12

~
VOO

R5

141

1

7
Ul
Vcc
9 *MC1489
13
12 -NC
NC- 8
11
4
6
NC- 10
1
3
NC- 2
5 -NC

NC -

~±-

VCC

~
Q)

1 I

14 1 U4 4

2048 MHz

5

~

MC74HC74 ~ ~
7
8f--NC
_
9 I-- NC
10 I-- NC
11 I-- NC
NC- 12
13 3
N1C

L

H-

OSR

VCC
C3f

I I

r- 4 8

9

L5

U6
MC14069UB

6
V001T

D825

Tx
RTS

.

CO
CTS
Rx

(,J

.....

(,J
I\)

SG

2
4

8
5
3

1

U2
9
MC145406

Cl;l.l8
VSS
2
4
-6
3
5
7

16
15
13

0

JC14
VCC

12
2
ST- 3
NC- 4 .

:!~
12
10

11
STSTSTST-

711-

3
'----

~

2
U3
*MC1488 :

6
7
8
9
10

---1

-b

NC- 13
7

1:=rll-NC

VSST 1

1 4 1 Voo

I

*MC1489 and MC1488 used when MC145406 nol used
II-

*C8

IS

1 ! - - NC
19 f-- ST
18
17
15
14

when C7

IS

RI

3~

C2

128 kHz
8 kHz

13
16
20

Y

II

YY

11 16
9
B 5 4
lB
19
21
UB
17
20MC145422
14
R2
12
C8**
15 7 6 3 10 22
2
1 13

~ Vec

~5 1~ill
VCC

~~ 01

~~
~TRAP

VCC 0 5 V
GNO 0 0 V
Voo AND VSS ARE DISCUSSED IN THE RS·232 SECTION

optional flltermg

* * lE-TR 1 should be cut

tXli

8

L

I"

R3

H~
9

B

-=?

Ie21-<

7

--<
~

Tl

R4
6

I:;.T _

CIO

2

13

6

4096 MHz

U5
MC145428

~t-

NC- 12

Cl

~ I

I

5

t

-b-

" d

14

12 10 13 11

-=:-

-..

~14

NC NC

13 4 5
14
U7
11
MC74HC393
10
2
7
9
12

used

Figure 5. Master Limited Distance Modem

02

314f5

10

NC

NC

'-

C7***

»z

CII

CD
~

0)

1

7
U1
NC- 9 'MC 1489
13
NC- 8
4
NC- 10
1
NC-7

~
VDD

R5

14

fJ-

VCC

121-- NC
II
6

C4

U4
MC145428

6-

DB 25

T.
RTS

VD~r

1

U2
9
MC 145406

iTI

VSS

8
2
4

16
15
13

C1O
VCC

C~L

2
4

~6

Co)

.....
I

Co)
Co)

CO
CTS
R.
SG

8
5
3

f-I

12
10

6
7
8
9

r-------

~

~

01

3!

13
14

-=-

5-

20

-

02
R2

R3
ST- 11
ST- 4
NC- 5
16

~~C

-

-

17
19

20

10

U3
*MC1488

*

2

r----..
~ f---'

I
7

VCC

2
ST- 3
NC- 4
11

7-=1

3

1

18

16-VCC ~ 12

:~ f--I

3
5
7

STSTSTST-

22
U5
2
10 MC145426
~

C~

1-NC
19-5T
18
17
15
14
13

12
OSR

VCC~

3
51-- NC

21
8
9
15

1
2

R4
6
NC 10
NC- 5
9

::1

'TI3"

* °A~
1

1

C1

Rl

IC2

-=-

NC-12
NC- 13
7

~ VSST

1:0-111--NC
14

1

IT

VOO

C8

ST - STRAP
NC - NO CONNECTION

VOD AND Vss ARE DISCUSSED IN THE RS-232 SECTION

*MC1489 and MC1488 used when MC145406 not used
**C3 IS optional flltermg

***TRl should be cut wtlen C6 IS used

Figure 6_ Slave Limited Distance Modem

~.--

T1

C6***
3
4

8

I

AN946

•

RS-232C DRIVER/RECEIVER

TRANSFORMER INTERFACE

The last Integrated CirCUit discussed IS the RS-232C Interface Either the MC1454060r the MC1488/MC1489 Drlver/
Receiver, which both fulfill the electrical specifications of EIA
Standard RS-232C and CCITI Recommendation V. 28, can be
used. The receivers Invert the signal and convert the RS-232
signals to standard five volt logic levels, and the drivers Invert
the signal and convert five volt logic levels to RS-232 voltage
levels.
The MC145406 is a CMOS RS-232 chip with three drivers
and three receivers. This chip operates with a five volt supply
and ±5 to ±12 volt supplies. Although the MC145406 chip will
work with ±5 volt supplies In most systems, the voltage
supplies should be at least ±7 volts to meet the RS-232 driver
specification. For full RS-232 compliance, the driver's output
must be between 5 volts and 15 volts for a logical 0, and It
must be between -5 volts to -15 volts for a logical 1
The MC1488 IS a quad line driver. For the MC1488 to
comply with the RS-232 driver requirements, a minimum
power supply of ±8 volts must be used. However, the chip Will
operate effectively In most systems with the positive supply
voltage varying from +7to +15volts The MC14891s a five volt
quad line receiver.

The transformer Interface greatly affects the UDLTs capabilities It performs the functions of Impedance matching,
bandwidth limiting, increasing receive voltages to reqUired
threshold levels and Input protection At 256 kHz, 26 AWG
wire's characteristic Impedance IS 110 ohms The source
reSistors from the LOl and L02 PinS are chosen to be 220
ohms With a transformer turns ratio of 2 1, the line Side's
characteristic Impedance IS 110 ohms ThiS configuration
Impedance matches the tWisted pair
The UDLTs minimum output voltage from the LOl and the
L02 pinS IS 2.25 volts peak Half of the voltage IS lost across
the 220 ohm source resistor That voltage of 1 12 volt peak IS
halved again by the 2 1 turns ratiO of the transformer to 0 56
volts peak. At 256 kHz, 26 AWG wire attenuates a signal level
of 18 declbels-per-kllometer After traveling a distance of two
kilometers the signal Will have attenuated 36 decibels At the
line Side of the transformer, the minimum signal level IS 8 9
millivolts peak A turns ratio of 1 4 In the transformer
Windings brings the signal level upto 356 millivolt peak ThiS
voltage IS divided between a resistor from the transformer to
the LI Pin and an Internal resistance At worst case, 29
millivolt peak are at the LI pin - within the 25 millivolts peak
minimum allowed signal
The UDLTs maximum voltage output IS 3.0 volts peak
Because of the voltage being halved by the source resistors
and the transformer Windings, the transmit signal level at the
line Side IS 075 volt peak With a short loop, the signal level
drop IS negligible, so the signal level at the receiving transformer IS about 0 75 volts peak With the 1 4 turns ratio at the
receiving transformer, the signal level at LI will be 30 volts
peak, which exceeds the 2 5volt peak maximum Input at LI A
signal level greater than 2 5 volts peak will Inject current 'nto
the UDLTs substrate ThiS action will distort the modulator's
output, thus creating bl! errors. Consequently, protection
diodes and resistors are needed to clamp the Input at LI The
demonstration board's transformer configuratIOn IS shown In
Figure 8 The LI Pin'S protection Includes a 1 kilohm resistor
between the LI pin and the diodes ThiS reSistor IS not on the

RS-232C CONTROL AND SIGNALS
As seen in Figure 5, the master LDM schematiC, and Figure
6, the slave LDM schematiC, asynchronous control and data
signals enter the LDM at RS-232 voltage levels through a
DB-25connector. Figure 7 shows a DB-25 connector which IS
the standard computer terminal connector. Pins 2,3.4,5,6,7,8
transmit the following information'
Pin
Pin
Pin
Pin
Pin
Pin
Pin

2'
3:
4'
5:
6:
7:
8:

Transmit Data (Tx)
Receive Data (Rx)
Request to Send (RTS)
Clear to Send (CTS)
Data Set Ready (DSR)
Signal Ground (GND)
Carrier Detect (CD)

The Tx and RTS signals are fed Into the receivers, and the Rx,
CTS and CD signals are outputs of the driver For the CD
signal, oneof the receivers Inverts the signal from the RxS pin
of the DSI. When the DSI is In asynchronous status, thiS
inversion gives the CD a logic 0 The output of that receiver IS
then put into a drlverto obtain RS-232 voltage levels The DSR
pin is connected to the RS-232 positive power supply through
a 300 ohm reSistor. Therefore, DSR Will go active whenever
the power supply IS on. The GND pin IS connected to the
system's ground. The remaining pinS used of the DB-25
connector are routed to the RS-232 Driver/Receiver

R1

[01

n:: 2

---"'V'V\r---__._---.

r------TlP

L02 ----'V\/'v---_----'

L::1 75 mH

lk

13

12

11

10

9

8

7

6

5

4

3

2

1

0000000000000
' - - - - - - RING
n:::05

000000000000
25

14 13 11

21

10

19

18

17

16

15

14
Vret - - - - - - - - - - - '

Figure 7. DB-25 Connector

Figure 8. Transformer Configuration Used in
LDM Schematic

3-134

AN946

demonstration board Typically, the external diodes will turn
on before the chip's Internal diodes, so the external diodes will
shunt most of the current However, the 1 kilohm resistor will
further ensure that the external diodes turn on first
The maximum power bandwidth of the UDLT IS 8 to 512
kHz, but to Improve line settling, It IS desirable to use a 20 to
512 kHz bandwidth To make the lower corner of the band- •
Width 20 kHz, the Inductance of the transformer Windings IS
chosen to be 1 75 millihenries To make the upper corner of
the bandwidth 512 kHz, a 0 001 microfarad capacitor IS placed
In parallel With the transmit tap If battery feed IS used, further
Input protectIOn 15 adVised Figure 9 shows a more durable
transformer configuration Transformers fulfilling thesespeclflcatlon can be obtamed from
Leonard ElectriC Products Company
85 Industrial Drive
Brownsville, Texas 78521

LDM BOARD OPTIONS
A picture of the LDM demonstration board IS shown In
Figure 10 and 11 Many of the UDLT and DSI features are
made available on the demonstration board uSing straps
These UDLT features Include

LB

In the master, a low disconnects the LI pin from the
Internal CirCUitry, drives L01, L02 to Vref and Internally ties
the modulator to the demodulator In the slave, a Iowan the
LB Pin makes the incoming demodulated data gOing to Tx
replace the incoming data on Rx

Po

A low powers down the UDLT, except for the receive

circuitry

The DSI features that can be controlled uSing the straps
Include
SB A low selects outputting one stop bit per data word, and
a high selects outputting two stop bits
DL' A low selects operating With eight bit data words, and a
high selects operating With nine bit data words

Part Number PIN P-1358-A

Reset A low clears the Internal FIFO, disables TxD, and
forces TxS and RxS low

+5 V

BR1, BR2, BR3 These pinS select the asynchronous data
rate

110
PIN 21 ~-/\f\r--+~V-J'v-"""-,
[01

, -_ _ _ _..... TWISTED
PAIR

20~'VID'I,-~>-----'VV'v-----'

PIN
[02

1k

For more information, refer to the individual data sheets, The
top of the LDM board shows suggested straps for these
functions These straps select one stop bit, an eight data word,
an inactive Reset, a 9600 baud asynchronous data rate, an
inactive loop-back and an inactive power-down
For battery feed applications, C6 of the slave LDM and C7 of
the master LDM can be Inserted, and the trace between these
pinS should be broken ThiS capacitor allows ac signals to pass
through the transformer, but keeps de power across the
capacitor to be fed Into the system's power supply C3 of the
slave LDM and C8 of master LDM provide filtering for the
upper corner of the bandWidth If thiS filtering IS not deSired,
these capacitors may be omitted, but their insertion IS
recommended

CONNECTORS

PIN 2 _ _ _ _ _ _......_-----'

Vre !

On the demonstration board, VSS and VDD are only used to
power the RS-232 circuitry VSS IS the most negative power
supply, and VDD IS the most POSitive power supply The
RS-232C Driver/Receiver section explainS the appropriate
voltage ranges for uSing either the MC145406 or the
MC1488/MC1489 VCC IS the board's five volt supply, and
GND IS the board's digital ground TIp and Ring are the
connections for the tWisted pair wire The 25 pinS on the left
Side of both the slave and the master board IS for the DB-25
connector

1 75 IIlH
0001 MF

Figure 9, Battery Feed Transformer Configuration

3-135

AN946

vo

vss

OND

~I

ijj

~

~

•

~~

0-

~ e~ ~

'"

~I

=

.,
"'

0'

-

~

~

C8

RING

lJ'

U'

T,O

~~ 92~

C7

Cf>

III

~o ~

~~ 9~
colt
TO

0
lOP

MOTOROLA

Slave

UDLT

Limited

Distance

Modem

Demo

618-1065

Board

·:-,v
vss

vee

VOO

ONO

04

ni3

Ui

0

U6

I

)

",i~~

Col"

-- 0

:U,j

a"

o
MOTOROLA

Master

UDLT

Limited

:;;
~
~

l

C2

~o

-

-

~

RTS

<

~

__
U'

to,~

--"'j~lt

D']

1681\

=
cq

Distance

Modem

RING

Demo

Board

Figure 10. Photostat of LDM Demonstration Board - Front

3-136

618-1088

AN946

•

nstratlon board-back, pin 6 of the MC74HC74 should be connected to pin 16 0 f the MC145422

t' n Board _ Back

'External to the demo

Figure 11, Photostat of LDM Demonstra

3-137

10

AN946

Table 1, Limited Distance Modem Parts List

Master LOM
R4 10 kll
R5 300 Il

Rl 10Mll
R2 220 II
R3 220 II

R4 10 kll
R5 300 II

Cl
C2
C3
C4
C5
C6
C7

C8 loo0pF
C9 01 "F
Cl0 01 "F
Cll 01 "F
C12 01 "F
C13 01 "F
C14 01 "F

Cl
C2
C3
C4
C5
C6

C7 01 pF
C8 01 "F
C9 01 pF
ClO 01 pF
Cll 01 pF

02 lN914

01 lN914

20 pF
20 pF
01 "F
01 "F
01 "F
01 "F
10 "F

01 lN914

•

Slave LOM

Rl 10 Mil
R2 220 II
R3 220 Il

20 pF
20 pF
0 001 "F
01 "F
01 "F
10 "F

Xl 4096 MHz

Xl 4096 MHz

Ul
U2
U3
U4
U5'
U6
U7
U8

Ul
U2
U3
U4
U5

MC1489
MC145406
MC1488
MC74HC74
MC145428
MC14069UB
MC74HC393
MC145422

T1 Lepco PIN P·1358-A

02 1N914

MC1489
MC145406
MC1488
MC145428
MC145426

T1 Lepco P N P·l 358·A

3-138

AN948

®

MOTOROLA

Data Multiplexing
Using the
Universal Digital Loop Transceiver and the Data Set Interface
INTRODUCTION
Data multiplexers find applications where clusters of terminals are connected to a central computer and In systems
where modems are pooled at a common location Combining
the signals from the various terminals onto one muiliplexed
data link simplifies wIring and reduces expenses Sharing the
cost of the multiplexer among the several terminals results In
a lower net cost compared to installing and maintaining
individual cables for each terminal While present day multiplexers are economical. new ICs from Motorola make possible
enhanced performance multiplexers for a fraction of the cost
of eXisting deVIces

This Appllcallon Note Will describe the deSign of a shorthaul multiplexer for asynchronous data at rates up to 9600
baud The mux combines eight full-duplex data channels
along with eight end-to-end RS-232 control signals onto a
Single pair of telephone wire for distances up to 2 km
Motorola's Universal Digital Loop Transceivers IMC1454221
26 UDLTs) master Islave high-speed synchronous data transceivers and Data Set Interface IMC145428 DSI) full-duplex
asynchronous to synchronous converter form the heart of thiS

multiplexer A tew MSI CMOS ICs complete the deSign
F,gu,e 1 Illustrates a tYPical system With the terminals In a
departmental situatIOn multiplexed onto one high-speed data
link RS- 232 control signals are passed transparently through

the multiplexer so the terminals have direct access to the
controls of the modems, ThiS multiplexer system transports
one control signal bldirecllonally for each data channel. As
Will be described below, other configurations may eaSily be
constructed With Simple wIring changes

CHARACTERISTICS OF THE UDLTs
The UDLTs are synchronous data transceivers capable of
transporting 80 kbps of full-duplex data over ordinary tWisted
pair 26to 19 gauge telephone wire at distances of up to 2 km
These devices utilIZe a 256 kilobaud MDPSK ping-pong burst
modulation technique for transmission Three logical data
channels, one of 64 kbps and two of 8 kbps each are
exchanged In bursts of 10 bits every 1251'S frame MDPSK
timing IS shown In Figure 2. The master initiates a pmg~pong
frame by bursting 10 bits of data to the slave beginning on the
rising edge of an externally generated Master Sync Input
IMSI) The modulator'S analog output Signal IL01, L02) is
shown referenced to MSI Upon receiving the last bit from the
master, the slave responds With a 10 bit burst of its own after a
four baud delay The slave's modulator output IL01, L02) IS
shown referenced to its own Transmit Enable 1 ITE1),
Depending on the transmisSion line characteristics and
length, the actual time of amval of the slave's return burst at
the master Will vary due to the propagation time of the signal

TERMINAL

o

MODEM

TERMINAL
MULTIPLEXER

Figure 1, Typical Multiplexer Application

3-139

AN948

I-~---------------------------125Ms--------------------------~·~1

MASTER

MSI

~

TRANSMIT

I

RECEIVE

RECEIVE

r-----

"----_ _---'I

MODULATOR
OUTPUT
IlOl, l021

SLAVE

MODULATOR
OUTPUT
IlOl, l021

•

TEl

TRANSMIT

L

Figure 2, UDLT Timing

between UDlTs, On excessively long lines, propagation time
down the transmission line results In collisions between the
master and slave bursts so maximum line length IS limited to
2 km with 26 gauge wire, The slave's TEl is generated
internally upon completion of demodulation of the burst from
the master, TEl remains high for eight data clock (128 kHzl
periods and returns low until another burst is received, ThiS
process is repeated every 125 !'S. Since both master and slave
devices exchange data every frame in a half-duplex manner at
a 256 kilobaud rate, an effective full-duplex rate of 80kllobaud
IS accessible to the user.
The bursts of data on the transmission line use Modified
DPSK signals to reduce EMI and susceptibility to crosstalk
from other signals in telephone cables. The frequency spectrum consists of peaks at 128 kHz and 256 kHz and their odd
harmonics Only a small amount of energy IS present In the
frequency bands used by analog telephone serVice, so UDlT
signals may be placed on adjacent pairs In cables With
ordinary telephone signals with no degradation of performance, The power spectral denSity at 76 kHz IS approximately
18dBm and at 28 kHz the level IS less than -30dBm, Because
there IS no signal energy at very low frequencies, dc energy
may be transported on the transmission line to power the
remote multiplexer Unit, Details of thiS feature Will be
described later,
The UDlTs have Internal buffers to store and prepare
synchronous data for transmiSSion, Eight bits for the 64 kbps
channel are serially Input and output every 125!,s frame The
two 8 kbps channels each have one bit Input and output every
frame. The master and slave UDlTs synchronous timing IS
shown In Figures 3 and 4 respectively Both figures Illustrate
the transmit and receive timing for the eight bit words on Tx

and Rx, and the timing for the two Signalling bitS, both Inputs
(SI1, SI21 and outputs (Sal, S021
The master UDlT timing shown In Figure 3 reqUires
external timing Signals of 8 kHz for MSI. TEl, RE1, and 64kHz
up to 2 56 MHz may be used for the TDC/RDC pin ThiS
application uses 128 kHz Eight bits of the 64 kbps data
channel received from the slave are output on the Tx pin on
the first eight rising edges of TDC/RDC while TE 1 IS high
Data to be sent to the slave IS Input on the Rx pin on the first
eight failing edges of TDC/RDC while REl IS high In thiS
application TEl and REl are connected together so data IS
Input and output Simultaneously Data on the 8 kHz Signalling
channels are Input on Sil and SI2 pinS and output on SO 1 and
S02 pinS on MSl's rising edge
The slave UDlT timing (shown In Figure 411s Similar to the
master except that the slave synchrOnizes to the master's
bursts and generates ItS own clocks and enables The eight
bits of the 64 kbps data channel received from the master are
presented on the Tx Pin on the (Ising edges of ClK while TE 1 IS
high, Data to be transmitted to the master IS loaded In on the
Rx pin on the failing edges of ClK while REl IS high Signalling
bits on the 8 kbps channels to and from the master are Input at
511, SI2 and output at SO 1, S02 on TE l's rising edge
The master UDlT has pin controlled Power-Down (Pol and
loop-Back ([81 features which can be used for system testing
Also available on the master IS Signal Insert Enable (SIEI
which enables the insertion and extraction of an 8 kbps
channel Into the l5B of the 64 kbps channel In thiS
application SIE IS unused and held low The Signal enable pin
(SEilS a three-state control pin which when held high enables
PD, [8, and the two Signalling bits (Sal and S021 allOWing
these Signals to be bussed to a microprocessor

3-140

AN948

~1~'---------------------------------125pS---------------------------------_;·~1
~J

~

~--------------~I

TDClROC

THREE-STATE

TEl. REI

R.

J

=

Sil SI2

SOl. S01

VAllO

~

______________

~r-

X

OON·TCARE

~----------'

X. . ._______________

OO_N_·T_C_AR_E_ _ _ _ _ _ _ _ _ _ _ _ _

~~

-y
-1'\\.-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _V
""-Figure 3. Master Timing

~1~.---------------------------------125pS--------------------------------_;·~1

TE1J

~--

_ _ _ _ _~I~

CLK

REI

lL.-_________________---'

R.X

=

DON'TCARE

L

~------~

Sil SI2

SOl.S02

VAllO

X. . ._______________

DO_N_·T_C_AR_E_ _ _ _ _ _ _ _ _ _ _ _ _

~~
V-

-y

-"-------------------""-Figure 4. Slave Timing

3·141

•

»z

<0.
0l:Io

+5 V
110n

.1Ion

...

Co)
I

.j:Io

N

~II

5 kll.,.
7
Rx

t
-

-

5kll

+5V

I

L02

III

I

I

f----'-

CHO EN

f-----

lj.

PO r-- +5 V
ill r-- +5 V

BR~~~ I
R,O

OCI
OlE
ODE
.1--- OCO

r-

I~
-

DC
VSS

CH7EN

h

II

+ V

III~~~E

OCO
BC
OC
VSS

I

T1 Lepeo P N P-1358-A

GNO

-12 V
I

+12V

+5V

I~
I

MCI45428

RST

SEQUENCING AND
SIGNALLING
(fiGURE 11

BRCLK
TxD
RxO I
SB

,

"'"

+5 V

Rx DATA

~DTR
DSR

~

I

MCI45406
RS-232
ORIVER/RECEIVER

H-- Tx DATA

'x>-+-

I I I I

OL~
-

BR3
SR2
BRI
TxS
R,S

I I I eX

Yt>+-CTS
VSS

GNO

----=r

-12 V

Figure 5. Master Unit Interconnect

CHANNEl 0

DSR

VSS

OSI7

VDO
CM
+5V

; , o - j - Rx DATA

CTS·

·

.

MCI45406
RS-232
DRIVER/RECEIVER

~OTR

••

CH7 SIG OUT

+5 v---1 SE

VCC'

I

12B kHz
CHO
2048 MHz SIG IN
8 kHz CHO SIG OUT

••
•
CH7 SIG IN

VDD

I I

S
OL B f u
BR3
BR2
+5 V
BRI
TxS
Rl(3E hex),
](3F hex).I(7C hexl, -(7E hex), DEL(7F hex). and Blank(7D hex}}
generate stuffed zeros Fortunately, It IS unlikely that these
characters Will be sent In large enough groups to cause FIFO
overruns In applications where ASCII data IS transported,
eight 9600 baud channels may be multiplexed onto thiS
system's 64 kbps synchronous channel If binary data IS
transported, a 16 kbps synchronous channel must be allocated
for each DS!. resulting In a four channel multiplexer ThiS
guarantees that even With maximum zero inSertIOns, FIFO
overruns will not occur

OCTAL MULTIPLEXER SYSTEM DESCRIPTION
ThiS multiplexer system fully explOits the DSI chips and the
UDLTtranscelver pair The UDLTs 64kbps channel transports
the synchronous data from the DSls One of the UDLTs 8kbps
channels IS used to synchrOnize the multipleXing of the eight
data channels, and the other 8 kbps channel IS used to
transport eight RS-232 control Signals
The multiplexer system conSists of two Units, a master and
a slave. Figure 5 Illustrates the interconnection of the vanous
deVices Within the master Unit The transformer Interface to
the tWisted pair IS shown With the preViously deSCribed
Impedance matching and protection circUitry The master
UDLT IS shown With the Tx, Rx lines along With the 128 kHz
and the 4 096 MHz clocks bussed to the eight DSls The data
channel enables and Signalling lines are shown connecting
the DSls and the RS-232 driver Irecelvers to the sequencing
and Signalling block Each DSlls shown configured for 9600
baud With eight bit character lengths and one stop bit which
may be made SWitch selectable, If deSired
Figure 6 shows the complementing slave unit Protection
circUitry and the transformer Interface are the same as the
master Unit The slave UDLT generates ItS own clocks derived
from an on-chip crystal OSCillator CirCUIt An Inverter IS used to
drive the eight clock Inputs to the DSls Also shown IS the
sequencing and Signalling Interconnect to the DSls and the
RS-232 driver Irecelvers
Circuitry In the sequencing and Signalling blocks IS shown
In FIgures 7 and 8 for the master and slave unIts respectively
All pertinent timing of the multiplexer system IS shown In
Figure 9 Master timing IS shown In the top sectIon, master
and slave bursts on the tWisted pair are shown on the line

3-144

AN948
labeled Transmission Line' Slave timing IS Illustrated on the
bottom half of the figure
Clocks for the master UDLT are created by a 12-stage ripple
counter (MC74HC4040) which IS driven by a 4096 MHz
crystal OSCillator Taps at 01, 05, and 09 create the 2 048
MHz (CCI), 128 kHz (TOC/RDC) and 8 kHz (MSI,TE1,RE1)
clocks respectIvely Inverters are needed on each line so the
rising edges cOincide A pulse which synchronizes the master
and slave data channel sequencmg cIrcUItry IS generated
when a count of 0 IS reached by 010,011, and 012 of the
ripple counter This pulse IS shifted through the enable shift
register (MC 140158) to create eight non-overlapping enables
for the DSls A latch (MC 14013B) IS used to delay the pulse so
that It can be properly Input Into Sil of the UDLT on the next
rising edge of MSI The delayed pulse on Sil and the data
channel enables (CHO-CH7 DOE, DIE) are shown on the
timing diagram RS-232 control data IS routed to a latch by an
addressable data selector (MC14051 B) RS-232 control data
received from the slave unit IS wntten Into an addressable
latch (MC14051 B) Notice that the first OOofthe shift register
IS the enable to the DSI of data channell Since the sync pulse
arrives at the Input of the shift register slightly after the clock,

a one-channel offset IS used to address the proper channel
ThiS offset IS transparent to the system
Data Input on the Rx pin of the UDLT IS buffered until the
next rising edge of MSI, when It IS burst out on the
transmisSion line Data on Sil and SI2 are latched In on the
rising edge of MSI and transmitted In the burst which was
Initiated by that MSI edge The bursts from the master (boxes
with M) and the return bursts from the slave (boxes With S) on
the tWisted pair wire are Illustrated on the Transmission
Line' The numbers indicate which channel's data IS transported In that burst
The system sync pulse arrives at the slave Unit on the SO 1
pin of the UDLT (Figure 8) It IS shifted through a shift register
(MC14015B) which IS clocked by the REl pin The O's from
thiS shift register enable the transmiSSion of data from the
DSls to the UDLT. The sync pulse IS delayed and shifted
through another shift register clocked by TEl The O's from
thiS shift register enable the DSls to accept data from the
UDLT RS-232 control data IS handled In the slave Unit In a
SImIlar manner as the master With a data selector and an
addressable latch Simply offsetting the connections to the
RS-232 driver/receivers realigns the data to the proper

4096 MHz

,----11Jf-o
4096 MHz CLOCK
GEN ERATOR

MCJ4HC4040

I

~I :i>

TOC/ROC
MSI TEl. REI

ENABLES TO OSls

0 0 - DIE
Ol~ DIE
02~ DIE
r-->
03 r--'~ DIE
------00
DIE
r--' 0
01 rDIE
02
DIE
r->
OH- f - DIE

,-- 0

r--r-

--

-=-

CCI

MCI4015B

RST
01

F-

05 09010

all 012

I

2048 MHz

rr-r-

AND
AND
AND
AND
AND
AND
AND
AND

ODE
ODE
ODE
ODE
ODE
ODE
ODE
ODE

CHANNEL
CHANNEL
CHANNEl
CHANNEL
CHANNEl
CHANNEL
CHANNEl
CHANNEL

I
2
3
4
5
6
J
0

128 kHz

ill

8 kHz

1/2MC14013B
OfSII

0


--(

S02

CE

C
B
A
WO

RST r -

04

8

Y

Figure 7. Master Sequencing and Signalling

3-145

XOXIX2X3X4X5X6XJ-

0
I
2
3
4
5
6
J

•

AN948
channels eliminating any superfluous circuitry Offsetting the
connections to the data selector (MC14051 B) Similarly aligns
the channels so that the data arnves at the master In the
correct lime slot FollOWing the channels on the liming
diagram Illustrates the concept.

ThiS multiplexer, because It IS all CMOS, consumes only
about 175 mW per unit. One of the units may be powered by
dc energy transported on the transmission line Itself eliminatIng a power cord The line Interface transformer IS deSigned to
pass dc energy by separating the two line Windings and
installing a 1 /IF capacitor between pinS 2 and 3 Now, dc
current may be passed to the tWisted pair A SWitching power
supply may be Installed In the remote Unit to convert the line
power to voltage levels useable by the digital Circuitry Recall
that the dc resistance of 2 km of 26 AWG wire IS approximately
575 ohms ThiS necessitates a relatively high voltage on the
sending Side to keep the 12R losses In the tWisted pair to a
tolerable level Usually 36 to 40 volts IS' satisfactory to furnish
enough voltage to the remote Unit Since the transmission
Ime IS balanced, there IS no ground reference between master
and slave Units dc power to the tWisted pair must be fed from
an Isolated Winding on the mains transformer, so that a
ground reference may be established at the remote unit

ADDITIONAL CONSIDERATIONS

•

ThiS multiplexer deSign IS qUite modular. If RS-232 control
Signalling IS not desired then the circuitry can be Simplified by
removing the write pulse generator (MC 14022B). addressable
latches (MC14099B) and data selectors (MC14051 B) from
both units The address generator (MC14163B) on the slave
Unit may also be removed In applications where data rates of
less than 9600 baud are used, the Baud Rate select pinS on
the DSls need Simply be reconfigured. A DIP switch can be
conveniently used to set the Baud Rate, Data Length and Stop
Bit pinS on the DSls. Note that the DSls must not be set for
19.2 or 38.4 kilobaud when eight channels are multiplexed If
data rates higher than 9600 baud are deSired, the indiVidual
data channels must be serViced more often by the UDLT
Because the high-speed synchronous channel between
UDLTs IS 64 kbps, the total bandWidth reqUired by all of the
channels must be at or below 64 kbps. The muiliplexer may
also be converted Into a Single channel limited-distance
modem where data rates of up to 56 kbps can be attained

MCI4163B

Connecting the ground references of the two units through

the tWisted pair will result In poor data performance due to
longitudinal currents In the line

References
Motorola Telecommunlcallons DeVice Data 800k DL 136, 1984

'""~'

MCI4015B

PE
TE

TEl

MCI4022B
MCI4099B
f>

~~

CLK --C CE
REI

-<~

RST

I12MCI4013B
S02

0

......
0 - f-

>- - f-

a

A
B
C
WO
y

XO
XI
X2
X3
X4
X5
X6
Xl

IT

CONNECTIONS TO
SLAVE UDlT

00 f - 01 f--02 f--r- 0
- - - - -03
- f--o00 f--f-' - [>C
01 f-- f-02 f-- f0
03 f-- f-~ f>C

RST 02 01 00

+5 V

OlE ENABLES TO OSls

SIGNAL OUT
TO
RS·232
DRIVER
f- CHI
f- CH2
f- CH3
f- CH4
f- CH5
f- CH6
f- CHl
f- CHO

CHANNEl
CHANNEl
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEl

I
2
3
4
5
6
1
0

I12MCI4013B
SOl

0

0

IT

MCI4051B

-A
'-- B
'---- C
y

SI2

XO
XI
X2
X3
X4
X5
X6
Xl

SIGNAL IN
fROM
RS·232
RECEIVER
f- CH4
f- CH5
f- CH6
f- CHl
f- CHO
f- CHI
f- CH2
f- CH3

Figure 8, Slave Sequencing and Signalling

3-146

MCI4015B

-

0

,--- >C

0 DE ENABLES TO OSls

-

03 r02 r- 01 I-- 00 r-+-

-----03 r--*--

-0

-

[>C

02 f--01 f--00 f---

CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEl

2
I
0
1
6
5
4
3

3·147

AN948
MAINS
TRANSFORMER
RECTIFIER/
FILTER

SWITCHING
POWER
SUPPLY

RECTIFIER/
REGULATOR

Tl

•

RS-232
CONNECTIONS

r-:-++-----I

Tl

SLAVE
MULTIPLEXER
CIRCUITRY

MASTER
MULTIPLEXER
CIRCUITRY

TWISTED PAIR
WIRE

Figure 10. Powering Slave Unit From the Twisted Pair

3-148

RS-232
CONNECTIONS

®

EB111

MOTOROLA
THE APPLICATION OF A DUPLEXER
By Vince Deems
Telecommunication Applications
Austin, Texas

The purpose of this document is to explain the application
and operation of a duplexer circuit, to show how to balance a
duplexer, and to discuss the duplexer's operation analysis
when used with two different transformers and with variable
components.
The duplexer circuit shown in Figure I is a fundamental
circuit that is used to help reject the transmit energy from the
receive signal. The circuit in Figure I is set up for a standard
600 ohm system.
This circuit eliminates the transmit signal from the receiving point by sending a combination of both signals into the
inputs of a differential amplifier. This tends to cancel out the
transmit signal leaving only the receive signal. A signal is
transmitted into Pin 3, the noninverting input, while a signal
is being received across Pins 5 and 8 of the transformer, from
the same line. There is a 600 ohm impedance when looking
into Pins 1 and 4 of the transformer. With RI tweaked to approximately 600 ohms, a voltage divider network is established with the 600 ohm impedance of the transformer. Thus,
the signal at the noninverting input, Pin 5, is Rx + (Tx/2).
The signal at the inverting input, Pin 6, is Txl2 due to the
virtual ground concept. When these inputs are added
together, the transmit signal cancels leaving Rx, the receive
signal, at the output Pin 7.
There are several ways of balancing or tuning duplexers
but only one technique will be explained for this application.
The transmit Pin 3 is grounded while a 600 ohm signal source
with a predetermined level and frequency is connected to
Pins 5 and 8 of the transformer. A signal with a level of
- 10 dBm (0.6938 Vp-p) and a frequency of 1700 Hz was
used in this circuit. R I is then tweaked such that the voltage
across Pins 5 and 8 of the transformer is half the signal
voltage or until there is exactly a 6 dB loss across Pins 5 and
8, (i.e., - 16 dBm at Pins 5 and 8). Next, the 600 ohm signal
source set at the same level and frequency is connected to Tx
(Pin 3) across a 10 kilohm resistor. A 600 ohm resistor is connected to Pins 5 and 8 of the transformer. Then, R2 is
tweaked until there is a minimum signal at Rx. Next, several
different values of capacitance are tried for CI until the

3-149

smallest null is found at Rx. Once the best value of
capacitance has been found, the duplexer has been balanced
for that particular input signal and the best possible rejection
of the transmission signal to the receive signal has been
found. This is called the Transhybrid Rejection and is shown
with different values of capacitance in Figure 2.
There are several noisy signals that this duplexer can not
eliminate at the receive Pin 7. For instance, deflection of the
transmit signal off of the transformer returns out of phase
and tends to leak through onto the receive signal. For this
particular circuit, curve I shows the best rejection over the
spectrum.
It is worth noting the difference in performance of this
duplexer with respect to the type of transformer used. The rejection versus frequency plot shown in Figure 2 was the result
obtained when the Midcom 671-0018 was incorporated. This
transformer has winding resistances of 14 ohms on the
primary coil and 18 ohms on the secondary. The same test
was run with a different transformer (Midcom 671-0915) and
the results are shown in Figure 3. This transformer has winding resistances of 178 ohms on the primary coil and 67 ohms
on the secondary coil giving it a much larger insertion loss
than the Midcom 671-0018. This difference is displayed in
Figure 3 as there is not as much rejection with the Midcom
671-0915 over the spectrum as with the Midcom 671-00 18
(Figure 2).
It can be seen from Figures 2 and 3 that changing the
capacitance changes the amount of rejection. This is due to
the fact that the coil (Pins I and 4) not only has a resistance
but also has an inductive reactance. If there is not a proper
sized capacitance in parallel with this inductance, then the
overall impedance of the coil increases. This impedance
changes the voltage divider with RI which in turn allows a
larger Tx at Pin 5 which is slightly out of phase with the
Rx + Txl2 at Pin 6. This allows more leakage of the transmission onto the receive signal thus decreasing the rejection.
This difference between the size of the capacitance and the
type of transformer to use is a tradeoff which is left to the
designer's judgement.

~

!

EB111

Voo
Tx--+--~

Tl

600

5

=W~

~~~II~:

10 k

17003

8

VOO=+5V
VSS=-5V
VAG= GNO IAnalogl
Signal = - 10 dBm
11700 Hzl

20 k

Voo

Ul- MC143403
Tl- Mldcom 671-0018

•

Vss
R<

FIGURE 1 - Duplexer

0
-6

Circu~

....,~=::::

-6

_ -12
en
::::,..

:g -18

_ -12
en

"\

r

g -24

1""- ....

"

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~-42

~-48

R1 =4641l
R2=35.6 kll

t:6-48

f-

Rl =5681l
R2=21 6 kll

-54
-60
100

200

300

400

600

1000

1700

I

3400 J
2600
6000

.=

10,000

f, Frequency, (Hz)

-54
-60
100

I
1k
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FIGURE 3 - Transhybrid Loss with Midcom 671-0915

FIGURE 2 - Transhybrid Loss with Midcom 671-0018

3-150

10 k

Adjustable clock
tunes notch filter
by Steve Bramblett
Motorola Inc., Austin, Texas

Radio transceivers often require notch tilters to suppress
interference from nearby broadcast stations. Unfortunately, most notch Iilters can handle only one frequency.
This design employs a switched-capacitor notch tilter to
form an audio notch tilter whose center frequency is
externally tuned by varying the circuit's clock frequency.
The changing clock frequency alters the tilter's poles and
zeros, resulting in a tunable notch tilter.
A frequency generated by clock U, is used as the
switching frequency for the tunable notch tilter (a) whose
notch frequency is f, = f./49.23 hertz, where f. is the
switching frequency input. In addition, the Iilter's low
and high 3-decibel points can be calculated, respectively, from equations f, = f./58.2 Hz and fh = f./45.71 Hz.
Since tunable filter U, is not capable of driving less than

600 ohms directly, 1,000-0-to-8-0 transformer T, is
used at the output to increase the load impedance.
In order to compensate for the transformer loss and
improve the circuit's signal-to-noise ratio, the tilter uses
an input amplitier that employs transistor Q, to provide
a gain of 20 dB. Because U, can generate switching
frequencies between 5 kilohertz and 128 kHZ, the tilter
may be tuned between 100 Hz and 2.6 kHZ. This circuit
is designed to operate on + 12 volts dc but will function
with voltages between + 10 to + 15 v dc. In addition,
when the circuit is switched off, the input is shunted
directly to the output. The tilter may be used by attaching the input to the receiver's headphone output jack
and connecting the filter's output to the headphones.
Interfering heterodyne frequencies may be suppressed
by adjusting potentiometer R,.
0

12V-i==========================~========~====~====================t-~~~J

12 V
47 kf!

510kf!

2N2222
62 kf!

4.7
kf!

12 V

so kf!

lkf!

lal

Filtering. Motorola's switched-capacitor notch filter MC145433 is switched by adjustable clock U. to provide a tunable audio notch filer (a). This
notch filter has a frequency response of about 100 Hz to 2.6 kHz (b) and can operate with voltages from
proves the circuil's signal-to-noise ratio, while audio transformer T, drives an 8-ohm load.

"Reprinted from ELECTRONICS. February 24. 1983. COPYright © 1983.

3-151

McGraw~HIII

+ 10 to + 15 V dc. Transistor 0, im-

Inc. All Rights Reserved."

EB·98

®

MOTOROLA
THE MC145432 APPLICATION CIRCUIT

•

The purpose of this document is to provide a circuit
capable of detecting 2600 Hz tone pulses on a telephone line
as defined by the Bell System specification for type-F singlefrequency signalling equipment.
The circuit in Figure I is designed to provide a 0 dB gain on
the channel, and the overall circuit is set up for a 600 ohm
system. The signals presented to the channel are driven
through the band-pass filter and out pin 14 of VI (the
MCI45432). The signals are also driven through the notch
filter and output to pin 5. Both outputs are AC coupled to
precision full-wave rectifiers and then averaged by integrators to produce a voltage level that is proportional to inband energies of each filter.
A three-step decision process is used in determining if a
valid 2600 Hz signal is present. The comparator U3A compares the two levels to determine which band has the most
energy. If the band-passed signal has the most energy, the
first step has been met. The second decision criteria requires
the signal level to be at least - 26.5 dBm ± 1.5 dB. This is
measured by the comparator U30 by selecting R23 and R24
so that the voltage drop across R24 equals the peak voltage
level presented at the input by a - 26.5 dBm signal multiplied
by the gain of the averaging circuit, which is 0.64. The circuit
is presently set up for 600 ohms, so a - 26.5 dBm signal is
0.0518 volts peak and the desired voltage drop must be
0.0518 x 0.64, which is 0.0332 volts. If gain is added at the
channel input or the circuit is used in a 900 ohm system, R23
and R24 must be modified to provide the proper comparison
level. The final requirement is the signal must be present for
38 milliseconds. This requirement is measured against the
averager's speed and the two time constants, RI7-CIO and
R2O-CII.
Bell requires that a notch filter be inserted into the channel
if the 2600 Hz tone is present in excess of 13 milliseconds with
a 6 millisecond margin. This requirement is met by the
RI7-CIO time constant. It takes about 7.5 milliseconds for
CIO to charge past the 2.1 volt threshold presented by
06-08. Since the averager takes between 0.5 and 11.5 milliseconds (dependent on input tone level) to provide levels

3-152

usable to make the decision, the overall delay is within 5
milliseconds of 13 milliseconds, which is within specification.
When the threshold is met, the comparator U3B goes high
and drives UI pin 12 high, which inserts the notch filter into
the channel. Should the signal be lost at anytime during the
charge cycle, CIO is discharged through R25, which represents a maximum discharge time of 0.5 milliseconds.
The output signal of U3B represents a delay of about 13
milliseconds and 38 milliseconds are required to meet the Bell
standard, so the R20-CII time-constant provides another 25
millisecond delay. The comparator U3C will go high if the
2600 Hz signal is present in excess of 38 milliseconds, thus the
final decision criteria is met at this point.
There are several other factors that must be taken into account. The circuit must be able to respond to a signal in the
+ 8.5 dBm to - 26.6 dBm range ± 1.5 dB variation in the
presence of no more than 65 dBrnC noise. The circuit will
detect a - 25 dBm signal under these conditions, which is
within the 1.5 dB spec. Another requirement is the ability to
detect a tone that is as much as 15 Hz off frequency;
however, this poses no real problem. There is one more factor known as talk-off. Although the Bell specifications does
not directly address this problem, it can be difficult to deal
with. Talk-off basically is caused by speech energy on an active phone line exceeding the tone energy and thus
prematurely terminating the signal. There presently is
enough protection to avert talk-off when voice signals reach
10 dB higher than the tone levels, but this can be augmented
by varying R25. Increasing the discharge time means the excess energy in the notch band must remain for a longer
period of time and this gives a better margin. However, if too
long of a delay is introduced, another phonemena, know as
talk-on, becomes a problem. This is when the circuit is
energized by the voice energy caused by CIO not bleeding off
fast enough. This is a qualitative trade-off left to the
designer'S judgement. Bell also specifies the detect signal's
pulse length based on the length of the input burst but this is
beyond the purpose of the circuit and can be easily implemented with some simple logic.

m

OJ

cD
CO

10(

.1 0(

Channel with
Filters

.1 0( Integrator. 10(

R "f
ectl ler

+5V

+5V

Analog GND

Co)

R16

NE 12 r~UlL.:1I rrrtit:::rLcrrdure
NO 5
C2 2600 Hz
~~--T;iJ Filter C8

.....
I

U1

+5V
05

-5

Co)

Rl
C3}-1C4

-5V
200 Il

1 kll
2 kll
51 kll
10 kll
20 kll
30 kll

R24
R4
R3, R7
R8, R15, R16, R19, R22
R5, R6, R12, R13, R18, R21
R2, R9, R1O, Rll, R14
R23

39 kll
47 kll
62 kll

10 Mil
20 pF

oO1I'F
0471'F

R17
R20
R25
Rl
C3, C4
Cl, C2, C7, C12
Cl0

11'F
471'F
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Ul
U2
U3
XTAL

2600 Detect
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1

• 0(

C6

R3

Channel Out

Channel Guard
Enable

Cll
C5, C6, C8, C9

01-011
MC145432
MC3403
LM339A
3579 MHz

FIGURE 1 - 2600 Hz Guard and Channel Circuit

~---

R18

+5V

Detect

EB·98

FIGURE 2 -

Mel 46432 Block Diagram

12

NE

2600 Hz
6 Pole Notch
Filter

17

~
+
_

15
_ _ _ _ - 15

•

FIGURE 4 -

Band-Pass Frequency Response

3·154

BNO

Notc h Frequency Response

kHz

kHz

BO

Voo= Pin 18
VAG= Pin 1
VSS= Pin 9

BPO

FIGURE 3 -

B+

16

Digitally control filter gain, cutoff
Earle West and Henry Wurzburg
Motorola Inc, Austin, TX

In addition to its intended application as a PCM
channel filter, you can use the MC14414-2 dual
switched-capacitor filter as a digitally controlled,
10th-order elliptic low-pass filter. Connected as
shown in the figure, this device exhibits a passband
ripple less than 0.6 dB POp, a pass/stopband transition ratio of 1.5:1 and a stopband rejection level of
more than 60 dB.
You set the filter's gain between 0 and 18 dB via
switches So through S;j. This action controls a
divide-by-N counter's output frequency and therefore the switched-capacitor filter's sampling rate by

changing the ratio between the filter's CCI and MSI
inputs. (Note that the MC14522 is a BCD-controlled
counter; if your application requires straight-binary
control, use the MCI4526B.)
The filter's break (cutoff) frequency is also a
function of the input clock's frequency. Set this
characteristic by calculating
fBREAK=fcd41.3.
Thus, for the spec'd 1- to 200-kHz fen span, you
can achieve a break-frequency range of 21 Hz to
4.842 kHz. But keep in mind that because this is a
switching filter, you must band-limit the input's
spectrum to 0.97f('CI to preclude signal aliasing. EDN

6V

FREQUENCY RESPONSE

MC14414·2

dB

~VAG

-::=-

L

A+

C

A-

r

PASSBAND
RIPPLE ,,0.6 dB pop

Ao

-60+=T~RA~N~S~IT~IO~N~---i--------~

Bo

L

B-

~-

r----------------------,

RATIO=1.5

B+

Vss

-6V

L----------f~~------~FREQUENCY

6V

fCCI

fCCI

41.3

27.8

53 52 8 1 So +N GAIN
0

4 INH Voo

V,,

8
10 MR

0 12
MC14522

Do

01

O2

0

0

0

0

1

0

1

0

C 6
03

+ 1'"'1+14-:--T-""'2+~

L - -5

-6V

° °
°

4 x 10k

-o - 6V

....~-f-lr--.NO/,-....

18dB
2

18dB

3

14.5dB

4

12.0dB
10.1 dB

0

1

0

1

0

1

1

0

8.5dB

°

1

1

1

7.18dB

1

1

°°°

1
1

0

6 dB

0

1

9

0

1

0

10

4.1 dB

0

1

11

3.25 dB

1

0

12

2.5dB

1

6V

18dB

1

1

1

1

°

5.0dB

1

13

1.8dB

0

14

116 dB

1

15 0.56 dB

'INVALiD - N INPUT

A switched-capacitor filter provides a gain- and frequency-adjustable 1ath-order elliptic low-pass characteristic when its sampling
and clock rates are varied_ Switches So through S3 set the gain-via a counter-by controlling the sampling rate. The filter's cutoff
frequency is related to the clock's frequency.

"Reprinted from EDN, March 3, 1982, Copyright 1982; Cahners Publishing Company"

3-155

One

Ie conditions signals
You can closely approximate this filter's characteristics by employing the circuit shown in the figure.
The MC14414-a switched-capacitor filter ICprovides the 5-pole elliptic low-pass function that
meets a C Message filter's sharp high-frequencyrolloff requirements. One of the IC's two uncommitted op amps serves as a Sallen Key active filter, the
other as the output filter's (R 3C3) buffer.

Steve Kelley and Henry Wurzburg
Motorola Inc, Austin, TX

When making signal-to-noise-ratio, harmonicdistortion and idle-channel-noise measurements on a
telephone voice channel, you can use a filter to, weigh
the noise spectrum before measuring its value. In
US systems, such an arrangement is commonly
termed a C Message filter.

The filter's output can directly drive a l-kO load.
Output noise equals 11 dBrn,.
EDN

(al

NOISE·SIGNAL INPUT

•

0-----"'"

OUTPUT SIGNAL
TO RMS METER

R,

CLOCK INPUT
134 kHz, TTL

-5

,/
/

-15

I

-20

-25

-30

100

/

/

-10

-35

C,-C 3 =O.0047.2%
A I := 15k
R,= 105k
R,= 7 87k

--------.r\\

v,....

(bl

NOTES:
UNLESS OTHERWISE SHOWN,
ALL CAPACITORS IN"F
ALL RESISTORS 1 %

/

/

V

V

/v
200

400

600

800

1k

2k

3k

4k

5k

Telephony signal conditioning is a snap with this switched-capacitor filter IC (a). Meeting C Message standards, the circuit allows
you to measure a voice channel's signa/-to-noise ratio, harmonic distortion and idle-channel noise. A 5-pole elliptic characteristic (b)
rolls off sharply above 4 kHz:

"Reprinted from EON, April 29, 1981, Copyright 1981; Cahners Publishing Company"

3-156

Ie trio simplifies
speech synthesis
Earle West, Product Engineer
Telecomm Product Engineering
Motorola Inc
MOS Integrated CirCUits Group
3501 Ed Bluestein Blvd.
Austin, Texas 78721

Despite the emergence of special-purpose speech
chips, the details of adding voice output to a system
are still foreign to most designers. However, they
should be happy to learn that highly intelligible
speech is possible using a low-cost microprocessor
and three readily available integrated circuits.
The speech peripheral, which contains an MC3417
continuously variable-slope delta modulator-demodulator, an MC145414 tunable, dual switchedcapacitor, low-pass filter, and an MC14040 counter,
encodes analog signals into a serial bit stream at a
rate of 15,625 bits/s (Fig. 1). The bit stream is then
stored in CPU memory. On demand, the peripheral

will reproduce an analog signal well enough to be
understood easily by an untrained listener.
Such a speech peripheral will enhance the I/O
capability of industrial systems, consumer service
systems, and games tremendously. Although more
CPU memory is required than for linear predictive
coding, stored words are easily changed than with
LPC. Furthermore, no special memories or complicated calculations are required and no specialpurpose synthesizer chips are needed. The encoded
speech signals are simply recorded into and played
out of CPU memory as any other data. Even the
software is simple: words can be packed into ROM
or a disk and need only be selected by the
microprocessor software for output.
Since the three-IC circuit is designed for speech
applications, the bandwidth ranges from 500 Hz to
3.7 kHz (Fig. 2). However, different filter time
constants, data rates, and integrator designs can
change the frequency range and with it the circuit's

I

!
I

I

3-bit
shift
register

I
I

I
I

1 MHz

'- --I

,
Analog
output

MC14Q4Q
counter

Clock
Decode
To
peripheral
Interface
addpter

)

Data

In

Data out

Analog
mput

I

I

Encode I
I

:_____ _ ~~m~~c::0":" ________:
1. At the heart of a three-chip speech peripheral is an MC3417 continuously variable-slope delta modulatordemodulator, which converts an audio waveform into a serial bit stream. The second and newest of the
three is an MC145414duai switched-capacitor low-pass filter with on-board operational amplifiers. An MC14040
12-bit binary counter completes the trio.

3-157

rI""

Gam

20

30

application. The tradeoffs made for this circuit make
it suitable for many industrial applications as well.

'00"'"

About the key chip

Of the three rcs, the key one is the CVSD
modulator-demodulator. On board, a current-controlled integrator generates a ramped voltage to
linearly approximate the encoded analog waveform
in piecewise fashion. Whenever the ramped voltage
becomes greater than the input voltage, an on-board
comparator switches the direction of the ramp.
Digitally, an increasing slope is represented by a 1;
a decreasing slope, by a O. This process is called delta
modulation because the slopes change, or delta, is
detected. However, the MC3417 does more than
simple delta modulation; it performs what is called
continuously variable-slope delta modulation (and
demodulation). Thus the slope of the ramp voltage
-that is, the gain of the chip's integrator-is infinitely variable. This way, in tracking the analog
input voltage, the output slope can change more
quickly when changes in the analog input demand
it. As a result, tracking is more accurate than with
any constant-slope delta modulation scheme.

40

50

\

60

70

500 Hz 1 kHz

•

2 kHz
3 kHz
Frequency

2. The switched-capacitor low-pass filter limits both input and
output frequencies to about 3.7 kHz, as reflected by the
system frequency response curve. Input frequencies are
limited to prevent aliasing; filtering the output smooths it out.
Bandwidth for the circuit ranges from 500 Hz to 3.7 kHz.

-12 V

'12 V

A,s

51 k

t-9:...6:...k'-'v\r,C".'_.. Integrator

400

01,uF
PIeceWise
linear

82k

8-0

22 M J

speaker

I

COinCidence I
output
CPU
interface

Data out

I

I
I

,

Data

In

VA

'-12 V

I

c,

>:

~

:

+12

'-- _J

~-------------I

Microphone

I

I

I

R,

"12 V

:t

R,

) :c:J'c/f

"

156 kHz

If-+--+---,

1 MHz

I

:

R,

I

I

I

400

'12 V

I

I

)!

GND

I

Data clock

v

10

125 kHz

R.

J.

L l'--t----'

Decode

U.

20 V,ms (max)
125 kHz

MC3417 modulator/demodulator

U2:= MC145414 filter

U3

~

MCl4040 counter

3. A continuously variable slope glvesthe MC3417 the accuracy to reproduce analog signals. When necessary,
the syllabic filter changes the rate of integration and with It the slope. The three basic chips, a simple audio
amplifier, and a microprocessor interface complete the speech peripheral circuit.

3-158

The MC145414 contains two filters and two operational amplifiers. One filter provides anti-aliasing by
cutting off input frequencies above 3.7 kHz. It has
a gain of 18 dB. The other filter smooths output noise,
but has no inherent gain. One of the chip's on-board
operational amplifiers augmentR the signal from a
microphone to about 1 V rms to drive the MC3417's
comparator input. At the output, a second op amp
and several discrete components drive an 8-\1
speaker.
The MC1454I4 uses switched-capacitor filters,
which need no precise external components for
accurate, low-pass analog filtering. Both filters are
five-pole, elliptic, low-pass types whose cutoff frequency depends on the sampling clock frequency.
For producing speech, the break frequency (3.7
kHz) requires a I25-kHz clock. The clock is generated
by the third IC, a CMOS MC14040 divider, and
a I-MHz master clock derived from the CPU. The
three rcs interface with a CPU system, in this case,
through an MC6821 peripheral interface adapter
(PIA).
Figure 3 details the entire speech circuit and its
two functions: encoding the analog signal into a serial
bit stream for the CPU to record and decoding the
bit stream into a reconstructed analog waveform.
Switch S, determines which function to perform by
supplying a corresponding level to both the CPU and
the CVSD chip.
When switched to encode, analog signals from the
microphone are amplified and filtered by one of the
op amps and a low-pass filter on board the MC145414.
The filtered audio is then fed to the MC3417, where
the analog-to-digital conversion produces the serial
bit stream. Each high bit means the integrator slope
is positive, and each low signals a negative slope.
Later, the stored bits are used to control the integrator, whose output approximates the audio signal.
In this way, the integrator uses straight lines to
reconstruct the original analog waveform.
Thus, when the circuit is set to decode-that is,
to output speech-the sequence of bits that
translates the serial bit stream into a linear approximation of the original audio is fed to the MC3417,
which sends it to the second low-pass filter and op
amp on board the MC145414 to smooth out the
sequence of linear approximations and provide
enough gain to drive a loud-speaker. As a result, with
the CPU selecting the sequence of bits (representing
words) previously stored in memory, spoken sentences are put out through the peripheral.
Since the speech quality is dramatically affected
by the sampling rate, the feedback loop gain, the
signal level, and the filtering, there is room to tweak
and adjust the sound to suit an application. The
circuit represents several tradeoffs to produce highly

intelligible speech using a reasonable amount of CPU
memory for speech storage, yet requires reasonably
few readily available parts.
For example, the transfer function in this application has two poles-one at 160 Hz and one at 280
Hz-and a zero at 4.0 kHz. The pole at 160 Hz
provides the long time constant necessary for following relatively linear portions of the original analog

•

4. The speech peripheral and the controlling microprocessor
communicate through a peripheral interface adapter. In
addition, clocking and serializing are software tasks, but
since the transfer of data between the program and the
peripheral Is asynchronous, changing the software does not
create a timing problem.

3-159

,,-,

/I:~**i'!;"4-'ilM**/I'lI-i\!

; A ~ TO P.Ejro~IH~t'!C1'(.(A'r·. SER.tAt CNS& Of.'fm:.

_1.

• ENTER ST";;TING ~. LOOIITI"" FUR CArA 5 _
• ' AHoCATlONS _
,~

,;:~J~i'f~i~~~~~~~CATA ~T~

,,,.:l,t,':'

,

,

•

,.

waveform; the pole at 280 Hz prevents instantaneous
reversals of the integrator's output voltage. The
latter action avoids a sawtooth like peak at extreme
values of the audio sine wave, which enables the
output to follow rapid changes in the audio waveform
more closely.
Finally, the zero at 4.0 kHz improves the phase
margin of the MC3417's feedback loop. In a simple
delta modulation-demodulation system, the slope of
the output signal used to approximate the input is
constant. Acceptable speech quality, however, calls
for a continuously variable slope-one that increases
or decreases with the input. The MC3417 performs
continuously variable slope modulation and demodulation so that the slope of the approximating
line segments depends on the last three bits clocked
into the decoder.
To do that, the MC3417's internal3-bit shift register monitors the serial bit stream of the comparator.
If the comparator detects a series of three or more
Is or three or more Os in a row, its coincidence pin
will go active and the slope of the integrator's output
line segments will be made slightly steeper. If three
or more consecutive Is or Os are detected, a capacitor
off the chip will charge up, and the control current
of the integrator will be increased continuously.
When the stream of all Is or all Os ends, the
capacitor is discharged by an external resistor (R 17),
which, with capacitor C9, forms a so-called syllabic
filter. (Incidentally, the values of Rand C are not
critical and in this application, the time constant
provided by the pair is 50 ms.)
Simple software

5. Conspicuous by Its small size, the program for running the
speech peripheral circuit performs both encoding and
decoding functions in 84 lines, including comments. The
routine "reads" the encoding-decoding switch position and
branches to the corresponding routine.

As Fig. 4 indicates, the software to record and play
speech using this peripheral is simple. The assembly
listing for an MC6800 system is given in Fig. 5. In
this case, a switch on the CPU board selects the
encoding or decoding by setting a high or low level,
respectively, at pin 14 of the PIA and pin 15 of the
CVSD chip. The encoding routine reads bits serially
from the peripheral, performs serial-to-parallel conversion, and saves the encoded data in memory. The
program operates asynchronously with the
peripheral, allowing different clock rates without
changing the software. The CPU simply waits for
a data clock edge, then reads the data. The decoding
routine works in the same way. The CPU waits for
a data clock edge, then sends a bit from memory to
the peripheral, which converts it into speech.D

"Reprinted with permission from Electronic Design, Vol, 30, No, 11; copyright Hayden Publishing Co., Inc., 1982,"

3-160

Turn 1/0 data port into speech port
Earle West and AI Mouton
Motorola Inc, Austin, TX

This low-cost, low-power ILP peripheral circuit
(figure) converts an 8-bit liD data port into a
high-quality speech port, using continuously variable slope-delta (CYSD) modulation to encode and
decode waveforms per ILP direction. The ILP can play
back any segment of recorded speech; 1 sec of
intelligible speech requires -1.5k bytes of memory.
You can trade off between voice quality and memorystorage requirements by adjusting the data-clock
rate for the CYSD chip.
'To encode speech, an MC145414 CMOS dual

switched-capacitor filter/dual op amp (U6) buffers
the signal and band-limits the input to -2.9 kHz. U6 ,
an MC3417 linear CYSD modulator/demodulator,
encodes the CYSD word and creates a bit stream at
-12k bps. This serial bit stream loads into U., where
the ILP reads it in parallel.
For decoding and outputting speech, the ILP loads
the MC14014 8-bit shift register (U.) with parallel
data. U. shifts the data to U 5 for CYSD decoding. U 6
performs low-pass filtering and buffers the resultant
voice waveform.
CMOS ICs U h U 2 and U a clock the filter and CYSD
chips, and U 7 drives a loudspeaker. Four control
lines connect with the ILP to control data direction
&DIll
and synchronize data clocking.

90 kHz
0005 pF

12V

15kHz
NOTES:
ENCODE MODE: DATA CAN BE
READ FROM SHIFT REGISTER
AFTER NEGATIVE CLOCK EDGE,
ONLY STABLE FOR 30 ,SEC

9.1k

DECODE MODE. DATA SHOULD BE
LOADED INTO PIA AFTER POSITIVE
CLOCK EDGE AND BE STABLE
BEFORE NEGATIVE CLOCK EDGE

=

U, MC14069
U2 =MC14040
U3 = MC14538
U4 =MC14034

Us = MC3417
Ue = MC145414
RESISTORS

= 1f.W, 5%

12V
CLOCK/SYNC

3.3k

5V
10 11

16
ALL
3.3k
PB,

VDU AE
13

PB,

17 A'I,

PB,

18 A3

PB,

19 A4 U..
20 As

PB.
PBs

21 As

PB,

22 A
23 '
A,
Vss A!S
12

PB,

VDDCL,Clt

16 A,

,.

12

.,.

4.7k
AUX

O.'~

MIC
22M

V..

V LS

8

9

GND

This 8-blt speech circuit encodes and decodes analog waveforms, Adjust the data-clock rate to trade off between voice quality
and memory overhead.

"Reprinted from EDN, May 26, 1982, Copyright 1982; Cahners Publishing Company"

3-161

•

3-162

Glossary.

4-1

Glossary of Terms and Abbreviations
The list reproduced here refers to terms found in this and other Motorola publications concerned with Motorola Semiconductor products for Telecommunications.

A law - An European companding/encoding
law commonly used in PCM systems.

Baud - A unit of Signaling speed equal to the
number of discrete Signal conditions or events
per second. This refers to the physical symbols/second used within a transmission channel.

A/B signaling - A special case of 8th-bit
(LSB) signaling in a wlaw system that allows
four logic states to be multiplexed with voice
on PCM channels.

Bit rate - The speed at which data bits are
transmitted over a communication path, usually expressed in bits per second. A 9600 bps
terminal is a 2400 baud system with 4
bits/baud.

A/D (analog-to-digitail converter (ADC) - A
converter that uniquely represents all analog
input values within a specified total input
range by a limited number of digital output
codes, each of them exclusively representing a
fractional part of the total analog input range.

Blocking - A condition in a switching system
in which no paths or circuits are available to
establish a connection to the called party even
though it is not busy, resulting in a busy tone
to the calling party.

Aliasing noise - A distortion component that
is created when frequencies present in a
sampled signal are greater than one-half the
sample rate.

•

BORS(C)HT - Battery, Overvoltage, Ringing,
Supervision, (Codecl, Hybrid, Test; the functions performed by a subscriber line card in a
telephone exchange.

Answer back - A signal sent by receiving
data-processing device in response to a request from a transmitting device, indicating
that the receiver is ready to accept or has received data.

Broadband - A transmission facility whose
bandwidth is greater than that available on
voice-grade facilities. (Also called wide band.)

Anti-aliasing filter - A filter (normally low
pass) that band limits an input signal before
sampling to prevent aliasing noise.

C message - A frequency weighting that
evaluates the effects of noise based on its annoyance to the "typical" subscriber of standard telephone service or the effects of noise
(background and impulse) on voice-grade data
service.

Asynchronous - A mode of data transmission
in which the time occurrence of the bits within
each character or block of characters relates to
a fixed time frame, but the start of each
character or block of characters is not related
to this fixed time frame.

Carrier - An analog Signal of fixed amplitude
and frequency that combines with an information-bearing signal by modulation to produce
an output signal suitable for transmission.

Attenuation - A decrease in magnitude of a
communication signal.
Bandwidth - The information-carrying frequencies between the limiting frequencies of a
. communication line or channel.

CCITT - Consultative Committee for International Telephone and Telegraph; an international standards group of the European International Telecommunications Union .

Baseband - The frequency band occupied by
information-bearing signals before combining
with a carrier in the modulation process.

Central Office (CO) - A main telephone office, usually within a few miles of a subscriber,
that houses switching gear; commonly
capable of handling about 10,000 subscribers.

4-2

Channel bank - Communication equipment
commonly used for multiplexing voice-grade
channels into a digital transmission signal
(typically 24 channels in the U.S. and 30 channels in Europe).

CTS - Clear to send; a control signal between
a modem and a controller used to initiate data
transmission over a communication line.
CVSD - Continuous Variable Slope Delta
(modulation); a simple technique for converting an analog signal (like voice) into a serial bit
stream.

Circuit, two-wire - A circuit with two conductors providing a "go" and "return" channels.

03 - D3 channel bank; a specific generation
of AT&T 24-channel PCM terminal that
multiplexes 24 voice channels into a 1.544 MHz
digital bit stream. The specifications associated with D3 channel banks are the basis for all
PCM device specifications.

Circuit, four-wire - A circuit with two pairs of
conductors, one pair for the "go" channel and
one pair for the "return" channel.
COOEC - COder-DECoder; the AJ D and DJ A
function on a subscriber line card in a
telephone exchange.

OJ A (digital-to-analog) converter (DAC) - A
converter that represents a limited number of
different digital input codes by a corresponding number of discrete analog output values.

COFIOEC - COder-Fllter-DECoder; the combination of a codec, the associated filtering,
and voltage references required to code and
decode voice in a subscriber line card.

Data compression - A technique that provides for the transmission of fewer data bits
than originally required without information
loss. The receiving location expands the
received data bits into the original bit sequence.

Common mode rejection - The ability of a
device having a balanced input to reject a
voltage applied simultaneously to both differential-input terminals.
Companding - The process in which dynamic
range compression of a Signal is followed by
expansion in accordance with a given transfer
characteristic (companding law) which is
usually logarithmic.

dB (decibel) - A power or voltage-level
measurement unit.

Compandor - A combination of a compressor
at one point in a communication path for
reducing the amplitude range of signals,
followed by an expander at another point for
restoring the original amplitude range, usually
to improve the signal-to-noise ratio.

dBmO - Signal power measured at a point in
a standard test tone level at the same point.
Le., dBmO=dBm-dBr
where dBr is the relative transmission level, or
level relative to the point in the system defined
as the zero transmission level point.

Conference call - A call between three or
more stations, in which each station can carry
on a conversation simultaneously.

dBmOp - Relative power expressed in dBmp.
(See dBmO and dBmp.)

dBm - The decibel signal level level referred
to one milliwatt, i.e., 0 dBm= 1 mW.

dBmp - Indicates dBm measurement made
with a psophometric weighting filter.

Crosspoint - The operating contacts or other
low-impedance-path connection over which
conversations can be routed.

dBrn Relative Signal level expressed
in decibels above reference noise,
where reference noise is 1 pW. Hence,
OdBrn=l pW= -90dBm.

Crosstalk - The undesired transfer of energy
from one signal path to another.

4-3

•

DTMF - Dual Tone Multi Frequency (dialing).

dBrne - Indicates dBrn measurement made
with a C-message weighting filter. (These
units are most commonly used in the U.S.,
where psophometric weighting is rarely used.)

Duplex - A mode of operation permitting the
simultaneous two-way independent transmission of telegraph or data signals.

dBrncO - Noise measured in dBrnc referenced to zero transmission level.

Echo - A signal that has been reflected or
returned as a result of impedance mismatches,
hybrid unbalance, or time delay. Depending
upon the location of impedance irregularities
and the propagation characteristics of a facility, echo may interfere with the speaker/listener or both.

Decoding - A process in which one of a set of
reconstructed analog samples is generated
from the digital character signal representing a
sample.
Delay distortion - Distortion that occurs on
communication lines due to the different
propagation speeds of signals at different frequencies, measured in microseconds of delay
relative to the delay at 1700 Hz. (This type of
distortion does not affect voice communication, but can seriously impair data transmission.)

•

Echo suppressor - A device used to minimize
the effect of echo by blocking the echo return
currents; typically a voice-operated gate that
allows communication one way at a time.
Encoder (PCM) - A device that performs
repeated sampling, compression, and A/D
conversion to change an analog Signal to a
serial stream of PCM samples representing the
analog signal .

Delta modulation - A simple digital coding
technique that produces a serial bit stream corresponding to changes in analog input levels;
usually utilized in devices employing continuously variable-slope delta (CVSD) modulation.

Equalizer - An electrical network in which
phase delay or gain varies with frequency to
compensate for an undesired amplitude or
phase characteristic in a frequency-dependent
transmission line.

Demodulator - A functional section of a
modem that converts received analog line
signals to digital form.

FDM - Frequency-Division Multiplex; a process that permits the transmission of two or
more signals over a common path by using a
different frequency band for each Signal.

Digital telephone - A telephone terminal that
digitizes a voice signal for transmission and
decodes a received digital signal back to a
voice signal. (It will usually multiplex 64 kbps
voice and separate data inputs at multiples of 8
kbps.)

Frame - A set of consecutive digit time slots
in which the position of each digit slot can be
identified by reference to a frame alignment.
The frame alignment signal does not necessarily occur, in whole or in part, in each frame.

Distortion - The failure to reproduce an
original signal's amplitude, phase, delay, etc.
characteristics accurately.

Full duplex - A mode of operation permitting
simultaneous transmission of information between two locations in both directions.

DPSK - Differential Phase Shift Keying; a
modulation technique for transmission where
the frequency remains constant but phase
changes will occur from 90°, 180° and 290° to
define the digital information.

Gain - The increase in signal amplitude realized when a signal passes through an amplifier
or repeater (normally measured in decibels).

4-4

Gain tracking error - The variation of gain
from a constant level (determined at 0 dBm input level) when measuring the dependence of
gain on signal level by comparing tha output
signal to the input signal over a range of input
signals.

Key system - A miniature PABX that accepts
4 to 10 lines and can direct them to as many as
30 telsets.
wlaw - A companding law accepted as the
North American standard for PCM based
systems.

HDLC - High-Level Data Link Control; a
CCITT standard data communication line protocol.

LAN - Local Area Network; a data-only communication network between data terminals
using a standard interface to the network.

Half duplex - A mode of operation permitting
transmission of information between two locations in only one direction at a time.

Line - The portion of a circuit external to an
apparatus that consists of the conductors connecting the apparatus to the exchange or connecting two exchanges.

Handset - A rigid assembly providing both
telephone transmitter and receiver in a form
convenient for holding simultaneously to
mouth and ear.

Longitudinal balance - The common-mode
rejection of a telephone circuit.
I

Hookswitch - The switch on a telephone set
that is operated by the removal or replacement
of the receiver on the hook (defined as offhook and on-hook conditions, and corresponding to busy and idle circuits).

Loopback - Directing signals back toward the
source at some point along a communication
path.
MCU - MicroComputer Unit (also MicroController Unit).

Idle channel noise (lCN) - The total signal
energy measured at the output of a device or
channel under test when the input of the
device or channel is grounded (often a wideband noise measurement using a C-message
weighting filter to band-limit the output noise).

MPU - MicroProcessor Unit.
Mu law - A companding/encoding law commonly used in U.S. (same as wlaw).
MUX - Multiplex or multiplexer.

Intermodulation - The modulation of the
components of a complex wave by each other
(in a nonlinear system).

Modem - MOdulator-DEModulator; a unit
that modulates and demodulates digital information from a terminal or computer port to an
analog carrier signal for passage over an
analog line.

Intermodulation distortion - An analog line
impairment when two frequencies interact to
create an erroneous frequency, in turn distorting the data signal repreentation.

Multiplex - To simultaneously transmit two or
more messages on a single channel.

ISDN - Integrated Services Digital Network;
A future communication network intended to
carry digitized voice and data multiplexed onto
the public network.

Off hook - The circuit condition resulting
when the handset is lifted from the hook
switch of the telephone set; i.e., a low dc impedance is placed across the line causing loop
current flow that is recognized by a relay at the
centfal office as a request for service.

Jitter - A type of analog communication line
distortion caused by abrupt, spurious signal
variation from a reference timing position, and
capable of causing data transmission errors,
particularly at high speeds. (The variation can
be in amplitude, time, frequency or phase.)

On hook - The circuit condition resulting
when the handset of a telephone is replaced
on its cradle (approximately an open circuit).

4-5

I

I

~

PABX - Private Automatic Branch Exchange;
a customer-owned, switchable telephone
system providing internal andlor external
station-to-station dialing.

Repeater - An amplifier and associated
equipment used in a telephone circuit to process a signal and retransmit it.
Repertory dialer - A dialer that stores a repertory of telephone numbers and dials anyone of
them automatically on request.

Pair - The two associated conductors that
form part of a communication channel.
Pass-band filter - A filter used in communications systems that allows only the frequencies
within a communication channel to pass, and
rejects all frequencies outside the channel.

Sampling rate - The frequency at which the
amplitude of an analog signal is gated into a
coder circuit. The Nyquist sampling theorem
states that if a band-limited Signal is sampled
at regular intervals and at a rate equal to or
greater than twice the highest frequency of interest, the sample contains all the information
of the original Signal. The frequency band
of interest in telephony ranges from 300 to
3400 Hz, so a sampling rate of 8 kHz provides
dc to 4000 Hz reproduction.

PBX - Private Branch Exchange; a class of
service in standard Bell System terminology
that typically provides the same service as
PABX.

PCM - Pulse Code Modulation; a method of
transmitting data in which signals are sampled
and converted to digital words that are then
transmitted serially, typically as 8-bit words.

•

SCU - Subscriber Channel Unit; the circuitry
at a telephone exchange associated with an individual subscriber line or channel.

Phase jitter - Abrupt, spurious variations in
an analog line, generally caused by power and
communication equipment along the line that
shifts the signal phase relationship back and
forth.

Signaling - The transmission of control or
status information between switching systems
in the form of dedicated bits or channels of information inserted on trunks with voice data.

Propagation delay - The time interval between specified reference points on the input
and output voltage waveforms.

Signal-to-distortion ratio (SID) - The ratio of
the input Signal level to the level of all components that are present when the input signal
(usually a 1.020 kHz sinusoid) is eliminated
from the output signal (e.g., by filtering).

Psophometric weighting A frequency
weighting similar to C-Message weighting that
is used as the standard for European telephone
system testing.

SLiC - Subscriber Line Interface Circuit; a
device that performs the 2-4 wire conversion,
battery feed and other line interface functions
on a subscriber telephone line.

Pulse dialer - A device that generates pulse
trains corresponding to digits or characters
used in impulse or loop-disconnect dialing.

Speech network - An electric circuit that
connects a transmitter and a receiver to a
telephone line or telephone test loop and to
each other.

Quantizing noise - Signal-correlated noise
generally associated with the quantizing error
introduced by AID and 01 A conversions in
digital transmission systems.

Subscriber line - The permanent connection
between a station and the switching center
that serves it.

RTS - Request to send; an RS-232 control
signal between a modem and user's digital
equipment that initiates the data transmission
sequence on a communication line.

Switch hook - A synonym for hookswitch.

4·6

Syn (Sync) - (1) A bit of character used to
synchronize a time frame in a time-division
multiplexer. (2) A sequence used by a synchronous modem to perform bit synchronization or by a line controller for character synchronization.

Tip (T) and ring (R) - Terms used to identify
the two conductors of a circuit. (These terms
originate from switchboard terminology for
cord circuits, in which a four-wire circuit is
designated T1, T2, and R1 and R2.)
Trunk - A telephone circuit or channel between two central offices or switching entities.

Synchronous modem - A modem that uses a
derived clocking signal to perform bit synchronization with incoming data.

TSAC - Time Slot Assigner Circuit; a circuit
that determines when a CO DEC will put its 8
bits of data on a PCM bit stream.

T1 carrier - A PCM system operating at 1.544
M Hz and carrying 24 individual voicefrequency channels.

TSIC - Time Slot Interchange Circuit; a
device that switches digital highways in PCM
based switching systems; a "digital" crosspoint switch.

Tandem trunk - See trunk.
Telephone exchange - A switching center for
interconnecting the lines that service a specific
area.

Twist - The amplitude ratio of a pair of DTMF
tones. (Because of transmission and equipment variations, a pair of tones that originated
equal in amplitude may arrive with a considerable difference in amplitude.)

TELETEX - A text communication service
between entirely electronic work stations that
will gradually replace TELEX with the introduction of the digital network. (Not to be confused with teletext.)

UDLT - Universal Digital Loop Transceiver; a
Motorola originated name for a voice/data
transceiver circuit.

TELETEXT - The name usually used for
broadcast text (and graphics) for domestic
television reception. (Not to be confused with
teletex.)

Voice frequency - A frequency within that
part of the audio range that is used for the
transmission of speech of commercial quality,
i.e. 300-3400 Hz.

Time-division multiplex - A process that permits the transmission of two or more signals
over a common paty by using a different time
interval for each signal.

Weighting network - A network whose loss
varies with frequency in a predetermined
manner.

4-7

II

I

4-8

Handling and Design
Guidelines

5-1

I

5·2

®

MOTOROLA
HANDLING AND DESIGN GUIDELINES

HANDLING PRECAUTIONS
All MOS devices have an Insulated gate that is subject to
voltage breakdown. The gate oxide for Motorola's devices is
about 800 A thick and breaks down at a gate-source potential of about 100 V. The high-impedance gates on the devices
are protected by resistor-diode networks. However, these
on-chip networks do not make the IC immune to electrostatic damage (ESDI. Laboratory tests show that devices
may fail after one very high voltage discharge. They may also
fail due to the cumulative effect of several discharges of
lower potential.
Static-damaged devices behave in various ways, depending on the severity of the damage. The most severely
damaged are the easiest to detect because the input or output has been completely destroyed and is either shorted to
VDD, shorted to VSS, or open-circuited. The effect is that
the device is no longer functional. Less severe cases are
more difficult to detect because they appear as intermittent
failures or degraded performance. Another effect of static
damage is, often, increased leakage currents.
CMOS and NMOS devices are not immune to large static
voltage discharges that can be generated while handling. For
example, static voltages generated by a person walking
across a waxed floor have been measured in the 4-15 kV
range (depending on humidity, surface conditions, etc.l.
Therefore, the following precautions should be observed.

1. Do not exceed the Maximum Ratings specified by the
data sheet.
2. All unused device inputs should be connected to V DD
or VSS.
3. All low-impedance equipment (pulse generators, etc. I
should be connected to CMOS or NMOS inputs only
after the device is powered up. Similarly, this type of
equipment should be disconnected before power is
turned off.
4. A circuit board containing CMOS or NMOS devices is
merely an extension of the device and the same
handling precautions apply. Contacting edge connectors wired directly to devices can cause damage.
Plastic wrapping should be avoided. When external
connections to a PC board address pins of CMOS or
NMOS integrated circuits, a resistor should be used in
series with the inputs or outputs. The limiting factor
for the series resistor is the added delay caused by the
time constant formed by the series resistor and input
capacitance. This resistor will help limit accidental
damage if the PC board is removed and brought into
contact with static generating materials. For convenience, equations for added propagation delay and
rise time effects due to series resistance size are given
in Figure 1.
5. All CMOS or NMOS devices should be stored or

FIGURE 1 - NETWORKS FOR MINIMIZING ESD AND REDUCING CMOS LATCH UP SUSCEPTIBILITY
VDD

I

To Off-Board
Connection

l
J

Rl

MOS

MOS

Input
or
Output

Input
or
Output

To Off-Board
Connection

D21.-._---I
Advantage: Requires minimal board area
Disadvantage: Rl

Advantage: R2< Rl forthe same
level of protection.

> R2 for the same level of

-= VSS

Impact on ae and de

charactenstics is minimized.

protection, therefore rise and fall

times, propagatIOn delays, and output
Disadvantage:

drives are severely affected.

More board area, higher initial cost

Note: These networks are useful for protecting the following:
A. digital inputs and outputs
B. analog inputs and outputs
C. 3-state outputs
D. bidirectional U/OI ports

EQUATION 1 - PROPAGATION DELAY
vs, SERIES RESISTANCE

EQUATION 2 - RISE TIME
vs. SERIES RESISTANCE

t

t
R---C-k

R_--C.k

where:
R= the maximum allowable series resIstance In ohms
t = the maximum tolerable propagation delay In seconds
C=the board capacitance plus the driven device's
Input capacitance in farads
k=O.33 for the MCl4504011
k = 0.7 for other devices

where:
R= the maximum allowable series resistance in ohms
t = the maximum rise time per data sheet In seconds
C = the board capacitance plus the driven device's
input capacitance In farads
k=O.7 for the MC145040/1
k = 2.3 for other deVices

5-3

•

6.

7.
8.

9.

10.

11.

12.

transported in materials that are antistatic. Devices
must not be inserted into conventional plastic
"snow", styrofoam or plastic trays, but should be left
in their original container until ready for use.
All CMOS or NMOS devices should be placed on a
grounded bench surface and operators should ground
themselves prior to handling devices, since a worker
can be statically charged with respect to the bench
surface. Wrist straps in contact with skin are strongly
recommended. See Figure 2.
Nylon or other static generating materials should not
come in contact with CMOS or NMOS circuits.
If automatic handling is being used, high levels of
static electricity may be generated by the movement
of devices, belts, or boards. Reduce static build-up by
using ionized air blowers or room humidifiers. All parts
of machines which come into contact with the top,
bottom, and sides of IC packages must be grounded
metal or other conductive material.
Cold chambers using C02 for cooling should be
equipped with baffles, and devices must be contained
on or in conductive material.
When lead-straightening or hand-soldering is
necessary, provide ground straps for the apparatus
used and be sure that soldering ties are grounded.
The following steps should be observed during wave
solder operations.
a. The solder pot and conductive conveyor system of
the wave soldering machine must be grounded to
an earth ground.
b. The loading and unloading work benches should
have conductive tops which are grounded to an
earth ground.
c. Operators must comply with precautions previously
explained.
d. Completed assemblies should be placed in antistatic containers prior to being moved to subsequent stations.
The following steps should be observed during board
cleaning operation.
a. Vapor degreasers and baskets must be grounded to

13.
14.

15.

16.

17.

an earth gro.und. Operators must likewise be
grounded.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor
degreaser immediately upon removal from the antistatic contaifler.
d. Cleaned assemblies should be placed in antistatic
containers immediately after removal from the
cleaning basket.
e. High velocity air movement or application of
solvents and coatings should be employed only
when module circuits are grounded and a static
eliminator is directed at the module.
The use of static detection meters for line surveillance
is highly recommended.
Equipment specifications should alert users to the
presence of CMOS or NMOS devices and require
familiarization with this specification prior to performing any kind of maintenance or replacement of devices
or modules.
Do not insert or remove CMOS or NMOS devices
from test sockets with power applied. Check all power
supplies to be used for testing devices to be certain
there are no voltage transients present.
Double check test equipment setup for proper polarity
of voltage before conducting parametric or functional
testing.
Do not recycle shipping rails. Continuous use causes
deterioration of their antistatic coating.

RECOMMENDED FOR READING
"Total Control of the Static in Your Business"
Available by writing to:
Static Control Systems Dlv.
Box ELB-3, 225-4S
3M Center
SI. Paul, MN 55144
Or calling:
1-800-328-1368
1-612-733-9420 (in Minnesotal

FIGURE 2 - TYPICAL MANUFACTURING WORK STATION

•
NOTES: 1. 1/16 inch conductive sheet stock covering bench top
work area.

2. Ground strap.
3. Wrist strap in contact with skin.

4. Static neutralizer. lionized air blower directed at work. I
Primarily for use in areas where dIrect grounding
is impractIcal.
5. Room humidifier. Primarily for use in areas where the

relative humidity is less than 45%. CaullOn: building
heating and cooling systems usually dry the air causing
the relative humidity inside of buildings to be less than
outside humidity.

5-4

CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
prevent it.
Figure 3 shows the layout of a typical CMOS Inverter and
Figure 4 shows the parasitic bipolar devices that are formed.
The circuit formed by the parasitic transistors and resistors is
the basic configuration of a silicon controlled rectifier, or
SCR. In the latch-Up condition, transistors 01 and 02 are
turned on, each providing the base current necessary for the
other to remain in saturation, thereby latching the devices
on. Unlike a conventional SCR, where the deVice IS turned
on by applying a voltage to the base of the NPN transistor,
the parasitic SCR is turned on by applying a voltage to the
emitter of either transistor. The two emitters that trigger the
SCR are the same pOint, the CMOS output. Therefore, to
latch up the CMOS deVice, the output voltage must be
greater than VOO + 0.5 Vdc or less than - 0.5 Vdc and have
suffiCient current to trigger the SCR. The latch-up
mechanism is similar for the inputs.
Once a CMOS device IS latched up, If the supply current is
not limited, the deVice will be destroyed. Ways to prevent
such occurrences are listed below.

2.

3.

4.

5.
6.

1. Insure that inputs and outputs are limited to the maximum rated values, as follows:

FIGURE 3 -

-0.5sVinSVOO+0.5 Vdc referenced to VSS
-0.5sVoutsVOO+0.5 Vdc referenced to VSS
IIinls10 mA
Iioutl s 10 mA when transients or dc levels exceed the
supply Voltages.
If voltage transients of sufficient energy to latch up the
device are expected on the outputs, external protection diodes can be used to clamp the Voltage. Another
method of protection is to use a senes resistor to limit
the expected worst case current to the Maximum
Ratings values. See Figure 1.
If voltage transients are expected on the inputs, protection diodes may be used to clamp the voltage or a
series resistor may be used to limit the current to a
level less than the maximum rating of lin = 10 mAo See
Figure 1.
Sequence power supplies so that the inputs or outputs
of CMOS devices are not powered up first le.g.,
recessed edge connectors may be used In plug-in
board applications and/ or senes resistors).
Power supply lines should be free of excessive noise.
Care in board layout and filtering should be used.
Limit the available power supply current to the devices
that are subject to latch-Up conditions. This can be accomplished with the power supply filte"ng network or
with a current-limiting regulator.

CMOS WAFER CROSS SECTION

P-Channel

N-Channel
Input

Field OXide

FIGURE 4 -

P-Channel Output

::: :1-____

LATCH UP CIRCUIT SCHEMATIC

P_+_N_-_-4~-P----------..:.P-~=s
~

P - Well Resistance

"I/V'vr__

(

N~

Q2

N - Substrate ReSIstance

5-5

¥A

N-ChannelOutput

~=

SS

vV
SS

•

5-6

Quality and Reliability

6-1

II

•
6-2

®

MOTOROLA
Introduction

This chapter IS Intended to demonstrate the quality and
reliability aspects of the semiconductor products supplied by
Motorola.

Quality in Manufacturing
QUALITY IN DESIGN
Motorola's quality activity starts at the product design
stage. It IS ItS philosophy to "design in" reliability. At all
development points of any new design reliability orientated
gUidelines are continuously used to ensure that a thoroughly
reliable part is ultimately produced. This is demonstrated by
the excellent in-house reliability testing results obtained for
all Motorola's semiconductor products and, more importantly, by our numerous customers.

NEW PRODUCT TYPICAL DESIGN FLOW

CIrcuit Design

Package

MATERIAL INCOMING CONTROLS
Each vendor is supplied with a copy of the Motorola Procurement Specification which must be agreed in detail between both parties before any purchasing agreement is made.
This is followed by a vendor appraisal report whereby each
vendor's manufacturing facility is visited by Motorola Quality
Engineers responsible for ensuring that the vendor has a well
organized and adequately controlled manufacturing process
capable of supplying the high quality material reqUIred to
meet the Motorola Incoming Inspection Specification. Large
investments have and are continuously being made and
Quality Improvement programs developed with our main
suppliers concerning:
Masks - Silicon - Piece-parts - Chemical products Industrial gas, etc.
Each batch of material delivered to Motorola IS quarantined at Goods-in until the Incoming Quality Organization has
subjected adequate samples to the Incoming detailed inspection specification. In the case of masks, this will Include
mask inspection for:

Process

II
'I

I~

I

I.

Engineering Sample

1 Defect DenSity
2. Intermask Alignment
3. Mask ReVISion

4. DeVice to Device Alignment
5. Mask Type
Silicon will undergo the following InspecliDns'
1 Type "N" or "P"
2. ReSistivity
3. ReSistivity Gradient
4. Defects
5 Physical DimenSions
6. Dislocation DenSity
Incoming chemicals are also controlled to very rigorous
standards Many are submitted to In-house chemical analYSIS
where the supplier's conformance to specification is

Commercial Sample
This baSIC deSign flow-chart omits
some feedback loops for simplicity

meticulously checked. In many cases, line tests are performed before final acceptance. A major issue and responsibility
for the Incoming Quality Department IS to ensure that the
most disciplined safety factors have been employed With
regard to chemicals. Chemicals can and are often rejected
because safety standards have not been deemed acceptable.

6-3

BIPOLAR WAFER FABRICATION

WAFER FABRICATION
All processing stages of Motorola products are subjected
to demanding manufacturing and quality control standards.
A philosophy of "Do it Right the First Time" is instrumental
in assuring that Motorola has a reliability record second to
none.

The Bipolar and MOS Wafer Fabrication flow charts are
examples which highlight the various in process control
points audited by both Manufacturing and Quality people.
The majority of these inspections are control audit points
with inspection gates at critical points of the process; this is
in line with Motorola policy of all personnel being responsible
for quality at each manufacturing stage.
Diffusion and ion implantation processing is subject to
oxide thickness controls penetration evaluations. Controls
are also performed on resistivity and defect density. Diffusion furnaces, metallization, and passivation equipment are
subjected to daily qualification requirements by using C-V
plotting techniques. C-V techniques are also used to ensure
ongoing stability as they do provide a very sensitive measurement of ionic species concentration.
In addition many other specific controls are used as a
means to ensure built-in reliability and provide statistical
trend data, which include:
•

Environmental monitoring for humidity, temperature
and particles
• Deionized water resistivity, particles and bacteria
checks in water
• Epitaxial material: resistivity - thickness - crystal
defects
• Oxide: thickness - charges - pinhole density
• Metallization: thickness - adherence - metal composition - ohmic contacts
• Doping profiles
• Pre and post etch inspections
• In process SEM analysis for step coverage: metallization - grain size - phosphorous concentration
• Passivation integrity checks

•

• Calibration
• Finai visual inspection gate.
After all processing stages are completed, every wafer lot
is subject to a detailed electrical parameter check.
Parameters such as threshold voltage, junction breakdown
voltages, resistivity, field inversion voltages, etc., are
measured and each batch is sentenced accordingly. The data
generated at this point is treated statistically as a control on
the distribution of each key electrical parameter thus allowing corrective action adjustments to be implemented in a
timely manner.
Every wafer lot is submitted to an electrical probe test during which every individual die is tested to its electrical
specification. Chips which fail are individually inked .

o
6-4

In Process
or Control Process
or Q.A. Inspection

MOS WAFER FABRICATION

In-Process

0

Inspection

ASSEMBLY

The assembly operation is of equal importance to the
wafer fabrication process as a manufacturing activity which
will effect the reliability of the finished product. Motorola
continuously makes major investments In specialized
assembly areas located In Malaysia, the Philippines and
Korea. These assembly plants employ the latest technologies

available to ensure that all Motorola semiconductors are produced to the highest standards of Quality and Reliability. In
addition, each wafer fabrication facility has In-house
assembly capability which allows some production, specific
engineering activity and qualification of piece-parts suppliers. The major production volumes of Motorola's Integrated Circuits are assembled offshore in the Far East.

6-5

•

• Moisture content audit procedures
• Super dry piece-part controls

identical Quality and Reliability philosophies are practiced
in the assemoly areas as within the wafer fabrication
facilities. Quality Assurance Audits for immediate corrective
actions are performed after major process steps as demonstrated in the flow-chart. In addition, screening options are
available. The statistical data obtained from quality audits are
reported to the appropriate business centers either daily,
weekly or monthly for review.
Motorola is particularly aware of the major impact
moisture can have on the reliability performance of either
plastic or ceramic parts. With this in mind several major new
innovations have been introduced to safeguard Motorola
products and thus enhance their overall reliability performance, these include:
• Faraday shield vacuum packed wafer shipping system
• Temperature and humidity controlled wafer inventory
stores
• Inert atmosphere for metal can packages encapsulation
• New design lead frames (plastic assembly)
• New molding compounds
• Low moisture content glass

FINAL TESTING

Each of Motorola's facilties has a complete Final Test
capability for all of the products fabricated and assembled.
The majority of products, after assembly, are tested and
Q.A. released at the facility responsible for that product.
Some product is tested in the offshore assembly site;
however, this is always returned to the facility for Q.A.
release prior to final shipment to customer.
Final Test is a comprehensive series of dc, functional
and speed orientated electrical tests as well as adapted
forced tests. These tests are normally more stringent than
data sheet requirements and are finally sampled by Outgoing
Quality Assurance.
In practice, the test flow philosophies vary according to
product. For instance, most of the Discrete devices are double tested as part of a zero defect quality improvement program. As well, many Integrated Circuits are tested at various
temperatures. There are also many burn-in options available.

TYPICAL INTEGRATED CIRCUITS ASSEMBLY AND FINAL TEST FLOW CHART

•
6-6

OUTGOING OUALITY SAMPLING PLAN
A.O.L.

1979
0.10
040
025
025
0.65
015
010
040
025
015
0.65
0040

1980
010
040
0.25
015
040
015
0.10
0.40
0.25
0.15
0.65
0.40

Functlon/ Parametric
Visuall Mechanical

LTPD

LTPD

15.0)

15.0)

MOS Microprocessors

FunctlOn/ Parametric
Visual! Mechanical

LTPD

LTPD

15.0)

15.0)

NMOS Memories

Functlon/ Parametric
Visual! Mechanical

LTPD

LTPD

15.0)

LS TTL ECL
Bipolar Memory/LSI

Functlon/ Parametric
VIsual/Mechanical

015
065

15.0)
015
0.15

ALS/FAST

Functionl Parametric
Visual! Mechanical

Rectifiers

Electrical Inoperative

Parametric
Visual/Mechanical

linear

Electrical Inoperative
Parametnc
Vlsual/ Mechanical

Power Transistors

Electrrcal Inoperative
Parametric
Visual/Mechanical

Small Signal Transistors

Electrical Inoperative

Parametric
Visuall Mechanical
CMOS

1981
0.065
0.25
015
0.15
040
015
0.10
040
025
0.10
040
0.25
0.15
015
015
0.15
015
0.15
0.065
0.065

1982
0.065
025
015
015
0040
015
010
0.40
015
0.10
040
0.15
0.10
0.15
0.10
0.15
0.10
0.15
0.065
0.065
0.065

1983
0.065
025
010
010
025
0.15
010
025
015
010
0040
0.15
010
0.15
0.10
0.15
0.10
0.15
0.065
0.065
0065

EVOLUTION OF AVERAGE OUTGOING OUALITY - A.O.O.
ITOTAL A.O.O. INCLUDING VISUAL, MECHANICAL AND ELECTRICAL)

Bipolar Linear IIC's

X - X Rectifiers

10

C

0 Transistors

Z - Z Bipolar Digital IIC's

8

x
:;;
0..
0..

4

1976

1977

1978

1979

1980

6-7

1981

1982

1983

In many published cases, stated PPM values refer to Electrical Inoperative failures only.
At Motorola, the Electrical Inoperative, the Electrical
Parametric and the Visual Mechanical failure rates are
calculated separately and then combined to reach an overall
total. In this way Motorola believes that is giving its
customers a true and accurate assessment of the quality of
the product. Unqualified PPM statements can be misleading
and cause the customer to expect quality levels which cannot be achieved. For example, Motorola CMOS A.O.O. is
quoted at , ,250 PPM overall Electrical parameters and including Visual/Mechanical categories. However, the function failure level is less than 200 PPM. Other product families
such as Small Signal Plastic Transistors are already reaching
50 PPM in Electrical Inoperative failure rate.
The Motorola PPM graphs are excellent examples of what
has been achieved over the last years with regard to quality
improvements.
Reductions between 50% and 300% in average outgoing
quality are typical across the broad range of Motorola products.
Throughout the semiconductor industry there have been,
and there still are, examples of manufacturers offering higher
quality standards at a premium. This is not a Motorola
strategy, we believe that our customers should expect high
quality products at no extra cost. This is Motorola's aim and
we will continue to aggressively pursue Ouality and Reliability improvements which will be passed on to our customers
as an obligation on our part.
Also, we actively encourage our customers to provide
their quality results at their Incoming Inspection, during their
manufacturing process and from the field in order to better
correlate and further improve our quality performance.

OUTGOING QUALITY

Although test procedures may vary from product to product within Motorola, the same philosophy applies when
considering quality objectives. Motorola's mission is to be a
Quality and Reliability leader worldwide.
HIGHLIGHTS:
Motorola recognizes that you, our customers, are truly
concerned about improving your own quality image. You
are, therefore, concemed about the quality of the product
Motorola supplies you.
Our customers measure us by the level of defects in the
products we supply at incoming inspection, during assembly
and, most important, field reliability.
During the past years, Motorola has achieved impressive
reductions in defect rates known as A.O.O. or Average
Outgoing Ouality. Instrumental in this success has been the
planned continuous reduction in outgoing A.O.l. to a point
where Motorola believes that over all products it can
demonstrate the most aggressive A.O.L.'s in the industry.
This aggressive program has been designed to help eliminate expensive incoming inspection at our customers.
All of the facilities also practice an extremely demanding
parts per million program program (PPM!.
The PPM performance of all Motorola products is
calculated in each location using the same method; they are,
therefore, directly comparable. Motorola is well aware that
when discussing PPM with existing or potential customers, it
is of paramount importance to explain exactly which failure
categories are included in the stated PPM figures.
Motorola's PPM figures will include:
• Electrical Inoperative Failure
• Electrical Parametric Failures (dc and ac)
• Visual and Mechanical criteria.

MOTOROLA A.O.o. PLAN
History
Avarage
1980
Power Transistors

Rectifiers
Small S.gnal Metal
Small Signal Plastic
Linear I/e's
l. and S.F.
Memory

•

3400
1750
4100
1500
4300

Microprocessor

5000
7000
7000

Bipolar Digital Logic
Bipolar Memory/LSI

1260
1620

Goal
Dec

1981
1400

1982
1100

1100
2200
1200

1000
1400
1030

2800
2370
4350
3860
802
1200

1900
1380
2400
2450
975
1000

A. O. Q. Includes all Defects: Visual. Mechanical,
Electrical Inoperative and Parametric.

6-8

1982

1983

950
950
1100
800
2000
1150
2900
2800
800
151

700
700

800
800
1000
500
1300
1300
500
700

AVERAGE A.O.a. IN P.P.M. FOR MOS PRODUCTS FIGURES
INCLUDE FUNCTIONALIPARAMETRICIVISUALIMECHANICAL

9000

_M,cro

8000

X-X Memory

0---0 CMOS

7000

6000

5000

4000

3000

----...............
---

X_
2000

--~-:.::,

-- -- ---0

1000
500
250
1979

1981

1980

1982

RELIABILITY

Paramount in the mind of every semiconductor user is the
question of device performance versus time. After the applicability of a particular device has been established, its effectiveness depends on the length of troublefree service it
can offer. The reliability of a device is exactly that - an expression of how well it will serve the customer. The folloWing
discussion will attempt to present an overview of Motorola's
reliability efforts.

BASIC CONCEPTS
It is essential to begin with an explanation of the various
parameters of Reliability. These are probably summarized
best in the Bathtub Curve (Figure 1). The reliability performance of a device is charactenzed by three phases: infant

mortality, useful life and wearout. When a device is produced, there is often a small distribution of failure mechanisms
which will exhibit themselves under relatively moderate
stress levels and therefore appear early. This period of early
failures, termed infant mortality, are reduced significantly
through proper manufacturing controls and screening
techniques. The most effective period is that in which only
occasional random failure mechanisms appear; the useful life
typically spans a long period of time with a very low failure
rate. The final period is that in which the devices literally
wear out due to continuous phenomena which existed at the
time of manufacture. Using strictly controlled design techniques and selectivity in applications, this period is shifted well
beyond the lifetime required by the user.

FIGURE 1

FIGURE2

I I I

~~

,

Ilnf~nt ~o~allty
I Such as Early
Burn-In Failuresl

1983

50% CL

~

I I

\

Useful Life

Wearout
Failures

I I
10

100

1000 10,000 100,000

1,000,000

A, Failure Rate

Time (Hoursl

6-9

Both the infant mortality and random failure rate regions
Cdn be described through the same types of calculations.
During this· time the probability of having no failures to a
specific point in time can be expressed by the equation:

where II is the failure rate and t is time. Since II is changing
rapidly during infant mortality, the expression does not
become useful until the random period, where II is relatively
constant. In this equation II is failures per unit of time. It is
usually expressed in percent failures per thousand hours.
Other forms include FIT (Failures In Time= (%/10 3 hrs)
x 10- 4= 10- 9 failures per hour) and MTTF (Mean Time To
Failure) or MTBF (Mean Time Between Failures), both being
equal to 1III and having units of hours.
Since reliability evaluations usually involve only samples of
an entire population of devices, the concepts of the Central
Limit Theorem apply and II is calculated using x2 distribution
through the equation:
x2 (x, 2r+ 2)
II :s
2nt
where x = 100- CL
100
CL = Confidence Limit in percent
Number of rejects
n
Number of devices
t
Duration of test

•

The confidence limit is the degree of conservatism desired
in the calculation. The Central Limit Theorem states that the
values of any sample of units out of a large population will
produce a normal distribution. A 50% confidence limit is
termed the best estimate and is the mean of this distribution.
A 90% confidence limit is a very conservative value and
results in a higherll which represents the point at which 90%
of the area of the distribution is to the left of that value
(Figure 2), The term (2r+ 2) is called the degrees of freedom
and is an expression of the number of rejects in a form
suitable to x2 tables.
The number of rejects is a critical factor since the definition of rejects often differs between manufacturers. While
Motorola uses data sheet limits to determine failures
sometimes rejects are counted only if they are catastroPhic:
Due to the increasing chance of a test not being representative of the entire population as sample size and test time
are decreased, the x2 calculation produces surprisingly high
values of II for short test durations even though the true long
term failure rate may be quite low. For this reason relatively
large amounts of data must be gathered to demonstrate the
real long term failure rate.
Since this would require years of testing on thousands of
devices, methods of accelerated testing have been
developed.
Years of semiconductor device testing has shown that
temperature will accelerate failures and that this behaviour
fits the form of the Arrhenius equation:
R (t) = Ro(t)e- 9/kT

where R(ll = Reaction rate as a function of time and
temperatu re
RO = A constant
t
Time
9
Activation energy in electron volts
k
Boltzman's constant
T
Temperature in degrees Kelvin
To provide time-temperature equivalents this equation is
applied to failure rate calculations in the form:
t =

toe 9/kT

where t = time

to = A constant
The Arrhenius equation essentially states that reaction rate
increases exponentially with temperature. This produces a
straight line when plotted on log-linear paper with a slope expressed by 9. 9 may be physically interpreted as the energy
threshold of a particular reaction or failure mechanism. The
activation energy exhibited by semiconductors varies from
about 0.3 eV. Although the relationships do not prohibit
devices from having poor failure rates and high activation
energies, good performance usually does imply a high 9.
Studies by Bell Telephone Laboratories have indicated that
an overall 9 for semiconductors is 1.0 eV. This value has
been accepted by the Rome Air Development Command for
time-temperature acceleration in powered burn-in as
specified in Method 1015 of MIL-STD-BB3. Data taken by
Motorola on Integrated Circuits have verified this number
and it is therefore applied as our standard time- temperature
regression for extrapolation of high temperature failure rates
to temperatures at which the devices will be used (Figure 3).
For Discrete products, 0.7 eV is generally applied.
To accomplish this, the time in device hours (t1) and
temperature (T1) of the test are plotted as point P1. A vertical line is drawn at the temperature of interest IT2) and a
line with a 1.0 eV slope is drawn through point P1.
Its intersection with the vertical line defines point P2, and
determines the number of equivalent device hours (t21. This
number may then be used with the x2 formula to determine
the failure rate at the temperature of interest. Assuming Tl
of 125°C at t1 of 10,000 hours, a 12 of 7.8 million hours
results at a T2 of 50°C. If one reject results in the 10,000
device hours of testing at 125°C, the failure rate at that
temperature will be 20%/1,000 hours using a 60% confidence level. One reject at the equivalent 7.8 million deVice
hours at 50°C will result in a 0.026%/1,000 hour failure rate,
as illustrated in Figure 4.
Three parameters determine the failure rate quoted by the
manufacturer: the failure rate at the test temperature, the activation energy employed, and the difference between the
test temperature and the temperature of the quoted lI. A
term often used in this manipulation is the" acceleration factor" which is simply the equivalent device hours at the lower
temperature divided by the actual test device hours.
Every device will eventually fail, but with the present
techniques in Semiconductor design and applications, the
wearout phase is extended far beyond the lifetime required.
During wearout, as in infant mortality, the failure rate is
changing rapidly and therefore loses its value. The parameter

6-10

used to describe performance in this area is "Median Life"
and is the point at which 50% of the devices have failed.
There are currently only few significant wearout

mechanisms: electromigration of circuit metallization, electrolytic corrosion in plastic devices alJd metal fatigue for
Power devices.

FIGURE 3
NORMALIZED TIME-TEMPERATURE
REGRESSIONS FOR VARIOUS ACTIVATION
ENERGY VALUES

l000k
1.2

1.6

2.0

2.4

I
1.1

I

3.2

2.8

IJ 1

II
I

'I I 'I
' I I II I

I!. /

I. /H

'1/

I, '/I

I

I

I

I

L

lOOk
1.2
100

,

3.6

I,

I

/I /11/

FIGURE 4
FAILURE RATE

r'1

II '1/1 V/ j

0

.'!l

III. 'I I /
IlIl 'II
I

a;
~

/

.2

,,<

,

1\

I

--

1.1
0.01

\

!

J

.1
T

.-

1\

I
I

I

,

i

\

I

i

\

1
0.001

11\

..
i

0.0001

I

I

I

200

I
0.1

"-

I :
I
500

1

I

'0;

'1/ VI V
'/ ~ / /
"7 rr
/. '!
/ :

3.6

1\

1.0

*.,

./

3.2

....

~

/

2.8

i\

:z:

'2/

2.4

1\

"E:>

/

J

2.0

A2
10

'" /

I

1.6

100

I

0.00001

(0

500

Temperature (OC)

200

100

50

o

Temperature lOCI

For increased flexibility in working with a broad range
of device hours, the time-temperature regression lines
have been normalized to 500°C and the time scale
omitted, permitting the user to define the scale based
on his own requirements.

Reliability
RELIABILITY TESTS:
DEFINITION, PURPOSE AND PROCEDURES
These definitions are intended to give the reader a brief
understanding of the test currently used at Motorola for
reliability checking. They also state which main failure
mechanisms are accelerated by the test.
HIGH TEMPERATURE STORAGE LIFE
An environmental test where only temperature is the
stress. Temperature and test duration must be specified.
Usually temperature is the maximum storage temperature of
the devices under test. Main failure mechanisms are
metallization, bulk silicon, corrosion.
HIGH TEMPERATURE REVERSE BIAS (HTRB)
An environmental stress combined with an electrical stress
whereby devices are subjected to an elevated temperature
and simultaneously reverse biased. To be effective, voltage

must be applied to the devices until they reach room
temperature at the completion of the test. Temperature, time
and voltage levels must be specified. Accelerated failure
mechanisms are inversion, channeling, surface contamination, design.
HIGH HUMIDITY, HIGH TEMPERATURE REVERSE
BIAS (H3-rRB)
A combined environmental! electrical stress whereby
devices are subjected to an elevated ambient temperature
and high humidity, simultaneously reverse biased for a
period of time. Normally performed on a sample basis
(qualification) on non-hermetic devices. The most common
conditions is 85° C and 85% relative humidity. More extreme
conditions generally are very destructive to the chambers
used. Time, temperature, humidity and voltage must be
specified. This accelerated test mainly detects corrosion
risks.

6-11

STEADY STATE OPERATING LIFE
An electrical stress whereby devices are forward I reverse
for zeners) biased at full rated power for prolonged duration.
Test is normally 25°C ambient and power is 100% of full
rated. (For power devices the IIC's maximum operating Ti is
used,) Duration, power and ambient, if other than 25° C,
must be specified. Accelerated failure mechanisms mainly
are metallization, bulk silicon, oxide, inversion and channeling.

for a period of time. During the" on" time the devices are
turned on at a power such that the junction temperature
reaches its maximum rating. During "off" cycle the devices
return to 25°C ambient. Duration, power, pr duty cycle must
be individually specified. Accelerated failures mechanisms
are mainly die bonds, wire bond, metallization, bulk silicon,
and oxide.
THERMAL SHOCK (TEMPERATURE CYCLING)
An environmental stress whereby devices are alternately
subjected to a low and high temperature with or without a
dwell time in between to stabilize the devices to 25° C ambient - the medium is usually air. Temperatures, dwell times
and cycles must be specified. Failure mechanisms are essentially die bonds, wire bonds, and package.

DYNAMIC OPERATING LIFE
An electrical stress whereby devices are alternately subjected to forward bias at full rated power or current and
reverse bias.
Duration, power, duty cycle, reverse voltage ambient and
frequency must be specified. Used normally for rectifiers and
silicon controlled rectifiers. Failure mechanisms are essentially the same as steady state operating life.

THERMAL SHOCK (GLASS STRAIN)

An environmental. stress whereby the devices are subjected to a low temperature, stabilized and immediately
transferred to a high temperature. The medium is usually liquid. Failures mechanisms essentially are the same as
temperature cycling.

INTERMITTENT OPERATING LIFE
(POWER CYCLING)

An electrical stress whereby devices are turned on and off

EXAMPLE OF NEW PROCESS QUALIFICATION TESTS

Condition

Duration

MIL-STD-883
Reference
Test Method

125°C, 5 V or 15 V

1,000 Hours

1005

85°C, 85% R.H.
5 V or 15 V

1,000 Hours

121°C, 100% R.H.
15P.S.I.G.

144 Hours

150°C

1,000 Hours

Thermal Cycle
lAir to Airl

- 65°C to 150°C
5 Min Dwell

1,000 Cycles

1010

Thermal Shock
ILiquid to Liquidl

- 65°C to 150°C
5 Min Dwell

1,000 Cycles

1011

0.5 MS

2002
2007
2001

Test
Operating Life
Temperature Humidity
Bias
Autoclave

High Temperature
Storage

Shock, Vibration, and
Constant Acceleration

Data Retention Bake
INon Volation Memonesl

1,500G, 3 per AXIS
150- 2,000 Hz, 20 g
30 kg

2 Hours

200/2500 C

1,000 Hours

•
6-12

MECHANICAL SHOCK
A mechanical stress whereby the devices are subjected to
high Impact forces normally In two or more of the SIX orientations Xl, Yl, Zl, X2, Y2, Z2 Tests are to verify the physical
Integnty of the deVices G forces, pulse duration, and number of shocks and axes must be speCified

VIBRATION VARIABLE FREQUENCY
Same as Vibration Fatigue except that frequency IS loganthmlcally varied from 100 Hz to 1 kHz and back. Number
of cycles IS normally four. Cycle time, amplitude and total
duration must be specified. Failure mechanisms are mainly
package, wire bond - this test is not applicable to molded
deVices.

EXAMPLE OF NEW PACKAGE QUALIFICATION TESTS

Test
Operating Life

Condition
125'C, 5 V or 15 V

Duration

1,000 Hours

Mll-STO-883
Reference
Test Method
1005

85'C, 85% R.H.
5 V or 15 V

1,000 Hours

121 'C, 100% R H
15 P S.I G.

144 Hours

150'C

1,000 Hours

Thermal Cycle
lAir to Air)

- 65'C to 150'C
5 Min Dwell

1,000 Cycles

1010

Thermal Shock
I LiqUid to LiqUid)

-65'C to 150'C
5 Min Dwell

1,000 Cycles

1011

1,500 G, 3 per AXIS
150 - 2,000 Hz, 20 g
30 kg

0.5ms
2 Hours

2002
2007
2001

Temperature Humidity BrBs

Autoclave

High Temperature Storage

Shock, Vibration, and
Constant Acceleration

Hermetlclty

185,10- 8

1014

8tm cc/sec

Visual Inspection
DimenSions

2008
Outhne Dwg

2016
2015

Markmg Permanency

Solderability
Wire Bond Strength
IPost Seall

230'C
15 Gram

O,e Shear

3 Seconds

2003
2011

2027

6-13

EXAMPLE OF STANDARD RELIABILITY PROGRAM
Reliability
Engineering
Depanment

Motorola Reliability Program For:

Test Group
Reliability Audit

Test

SS

Frequency

Thermal Shock

25

1 Product Line

Test Methodsl Conditions
MIL-STD-883, Method 1011
- 25'C, + 125'C
Dwell Time 5 mn, 100 Cycles

Per Week
High Temperature

40

TA-l50'c' VCB- 8 VCB max 168 hours

Reverse Bias

Life Tests

High Temperature
Reverse Bias

25
1+21

3 Product Lines
Per Month

High Temperature
Storage

25
1+21

TA = 150'C, 1,000 hours

Steady State
Life

25
1+21

MIL-STD-883, Method 1005
TA= 125'C, 1,000 hours

25

High Humidity

TA = 85'C, 85% Humidity
VC8= 8 VCB max 1,000 hours

High Temperature

1+21

Reverse 818S
( + 2) devices for correlation purpose

Test Conditions

Device Hours

No. Of
Failures

Activation

Product Family

Energy

Derated
Temperature

% Per 1,000 Hours
At 60% Confidence

Non Hermetic

Operating
T1= 155'C
Operating
TJ= 125'C

591,552

64

1 eV

70'C

0014

13,082,000

39

1 eV

70'C

00029

798,000

5

7 eV

70'C

0.009

295,000

3

7 eV

70'C

021

520,000

5

7 eV

70'C

0014

Interface I/C's
Consumer I/C's

004/005
Rectifier
PlastiC
Axial Diodes
Button Diodes

TJ-l50'C
VR=.8 BVR
TI -l00'C
VR=.8 BVR
TJ 150'C
VR=.8 BVR

Small Signal
PlastiC
Transistor

TJ-l50'C
VCB= 8 BVCO

579,000

6

7 eV

70'C

0014

Small Signal
Metal
Transistor

TJ-150'C
VCB= 8 BVCBO

3,944,000

12

7 eV

70'C

00039

Case 77
Power Plastic
TranSistor

TJ-l50'C

364,416

2

7 eV

70°C

00097

366,080

0

7 eV

70°C

00028

297,024

3

7 eV

70°C

0016

247,104

3

7 eV

70°C

0019

T0220
Power PlastiC
TranSistor
T03P
Power Plastic
TranSistor

•

TA= 150'C, VC8= 8 VCB max 1,000 hours

T03
Power MetaJ
TranSistor

VBC = .8 BVCBO
TJ -l50'C
VCB = .8 BVCBO
TJ-l50°C
VCB = ,8 BVCBO
TJ-l50°C
VCB= 8 BVCBO

6-14

Product Family
CMOS Ceramic

No. of
Failures

Activation
Energy

Derated
Temperature

% Per 1,000 Hours
At 60% Confidence

6

1 EV

5O'C
75'C
85'C

0.0004
0.003
0014

113x106

4

1 EV

85'C

0.Q18

125'C
Dynamic Bias
5V

2.88x 1()6

47

1 EV

70'C

0039

125'C
DynamIc Bias
5V

434,456

3

1 EV

70'C

0.009

250'C Sake

519,120

3

0.7 EV

70'C

00075

125'C

917,280

25

1 EV

70'C

0.027

Test Conditions
125'C

Device Hours
2.04x 1()6

Static BIas

15 V
CMOS Plastic

125'C
Static Bias

15 V
6800 Senes
Plastic
U V EPROM
life Test

Data Retention
EEPROM
life Tes\

Dynamic Bias

5V
Data Retention

250'C

988,672

19

0.7 EV

70'C

0.020

64K DRAM

125'C
DynamIc Bias
55V

1.05x 1()6

6

0.7 EV

70'C

0.028

Derated

Test Conditions

Device Hours

No. of
Failures

Activation

Product Family

Energy

Temperature

% Per 1,000 Hours
At 90% Confidence

lS·TTl

125'C
Static BasIs
-5.2 V

1.0 eV

70'C

0.0029

ECl

125'C

il':'
I,

I

61.74x 106

7

1.0 eV

85'C

Ii
I;

0.0189

"

Static Bias

5V

Product Family

Test Conditions

Device Hours

No. of
Failures

Activation
Energy

Derated
Temperature

% Per 1,000 Hours
At 60% Confidence

Operational
Amplifier

Operating
T,= 135'C
Operating
Tj= 135'C

437,472

2

1 eV

70'C

0.0026

718,848

4

1 eV

70'C

0.0033

Hermetic
Interface 1/ C' 5

The reliability approach at Motorola Semiconductors is
based on designing in reliability rather than testing for reliability only. This concept is reflected by Motorola's mandatory procedures which require product, process and
packaging qualification on three independently produced
lots before any product is released to volume production.
Reliability engineering approval supported by an officially
documented report is required before any product is released
to manufacturing. Tests at both maximum rated and accelerated stress levels are performed. Acceleration is important to determine how and at what stress level a new design,
product process or package would fail. This information provides an indication of what design changes can be implemented to ensure a wider and safer margin between the
maximum rated stress condition and the devices stress
limitation.
As well as qualifying all new products, processes and
piece-parts, each Motorola manufacturing facility operates

II
II

I
.J

an ongoing reliability monitor which covers all process and
packaging options. This program provides a continuous upto-date data base which is summarized in periodical reports.
Reliability statistics supporting all Motorola Semiconductor devices can be obtained from any of the Motorola Sales
Offices upon request. The present operating life test results
demonstrates Motorola'S reputation for producing semiconductors with reliability second to none.
The Quality organization in each facility is responsible for
preparing and maintaining a Quality Manual which describes
in detail the quality systems and associated Reliability and
Quality Assurance organization, policies, and procedures.
This manual must be appraised and ultimately approved by
the appropriate approval authority.

•

I

6-16

Mechanical Data •
7-1

MECHANICAL DATA
The package availability for each device is indicated on the front
page of the individual data sheets. Dimensions for the packages are
given in this chapter.

- - - - - - - - - S · P l N PACKAGE - - - - - - - - P SUFFIX
PLASTIC PACKAGE
CASE 626-04

NOTES:
1. LEAD POSITIONAL TOLERANCE:
0.13 (0.005) @I T A@ B @i
2. DIMENSION "L" TO CENTER OF
LEADS WHEN FORMED PARALLEL.
3. PACKAGE CONTOUR OPTIONAL
(ROUND OR SQUARE CORNERS).
4. DIMENSIONS A AND B ARE DATUMS.
5. DIMENSIONING AND TDLERANCING
PER ANSI Y14.5, 1973.

1.1.9'

1

1

STYLE 1:
PIN 1. ACIN
2.DC+IN
3. DC-IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC

7·2

MILLIMETERS
DIM MIN
MAX
A 9.40
10.16
B 6.10
6.60
C 3.94
4.45
D 0.38
0.51
F 1.02
1.52
G
2.54 BSC
H 0.76
1.27
J 0.20
0.30
K 2.92
3.43
L
7.62 BSC
M 100
N 0.51
0.76

INCHES
MIN MAX
0.370 D.400
0.240 0.260
0.155 0.175
0.015 0.020
0.040 0.060
0.10 BSC
0.030 0.050
0.008 0.012
0.115 0.135
0.300 BSC
100
0.020 0.030

MECHANICAL DATA (Continued)

- - - - - - - - - 1 4 · P I N PACKAGES--------L SUFFIX
CERAMIC PACKAGE
CASE 632-07

~
4

8~
B P
7~

1

--u-oJ

F

MILLIMETERS
MIN
MAX
19.05 19.94
7.49
6.10
5.08
0.38
0.58
0
F
1.40
1.77
2.548SC
G
H
1.91
2.29
J
0.20
0.38
K
3.18
4.32
7.62 SSC
L
15 0
M
N
0.51
1.02

DIM
A
8
C

NOTES:
1. ALL RULES ANO NOTES ASSOCIATED
WITH MO·OOI AA OUTLINE SHALL APPL Y.
2. DIMENSION "L"TO CENTER OF LEADS
WHEN FORMED PARALLEL.

3. DIMENSION "A" AND "8" (632·07) DO
NOT INCLUDE GLASS RUN·OUT.
4. LEADS WITHIN 0.25 mm (0.010) DIA
OF TRUE POSITION AT SEATING PLANE
AND MAXIMUM MATERIAL CONDITION.

INCHES
MIN
MAX
0.750 0.785
0.240 0.295
0.200
0.015 0.023
0.055 0.070
0.100 SSC
Om5 0.090
0.008 0.015
0.125 0.170
0.300 SSC
15°
0.020 0.040

il
II
i'~

I

I
P SUFFIX
PLASTIC PACKAGE
CASE 646-05

•

MILLIMETERS
DIM MIN
MAX
A
18.16 19.56
6.60
8
6.10
5.08
C
4.06
0.38
0.53
D
F
1.02
1.78
2.548SC
G
2.41
H
1.32
0.38
J
0.20
2.92
K
3.43
7.628SC
L
00
M
100
0.51
N
1.02

NOTES:
1. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.
3. DIMENSION "8" DOES NOT
INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL.

7·3

INCHES
MIN
MAX
0.715 0.770
0.240 0.260
0.160 0.200
0.015 0.021
0.040 0.070
0.1008SC
0.052 0.095
0.008 0.015
0.115 0.135
0.3008se
00
100
0.020 I 0.040

•

MECHANICAL DATA (Continued)

- - - - - - - - - 1 6 · P I N PACKAGES--------L SUFFIX
CERAMIC PACKAGE
CASE 620-08

MILLIMETERS
MIN
MAX
19.05 19.94
7.49
6.10
5.08
0.53
0.38
1.78
1.40
2.54 BSC
G
1.14
0.51
H
0.30
J
0.20
3.18
4.32
K
7.62 BSC
L
150
M
1.02
0.51
N

INCHES
MIN
MAX
0.750 0.785
0.240 0.295
0.200
0.015 0.021
0.055 0.070
0.100 BSC
0.020 0.045
O.OOB 0.012
0.125 0.170
0.300 BSC
15 0
0.020 0.040

MILLIMETERS
MIN MAX
18.80 21.34
6.10
6.60
B
5.08
C 4.06
0.38
0.53
D
1.02
1.78
F
2.54 ase
G
2.41
H
0.38
0.38
0.20
J
K
2.92
3.43
7.628se
L
00
100
M
0.51
N
1.02

INCHES
MAX
MIN
0.740 0.840
0.240 0.260
0.160 0.200
0.015 0.021
0.040 0.070
0.100 ase
0.015 0.095
0.008 0.015
0.115 0.135
0.3008SC
00
10 0
0.020 0.040

DIM
A
8
C
0
F
4. DIM "A" AND "B" DO NOT INCLUDE
GLASS RUN·OUT.
5. DIM "F" MAY NAR ROW TO 0.76 mm
(0.030) WHERE THE LEAD ENTERS
THE CERAMIC BODY.

1. LEADS WITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONDITION.
2. PACKAGE INDEX: NOTCH IN LEAD
NOTCH IN CERAMIC OR INK OOT.
3. DIM "L" TO CENTER OF LEADS WHEN
FOR.MED PARALLEL.

P SUFFIX
PLASTIC PACKAGE
CASE 648-05

OPTIONAL LEAD
\
A -----1
r -_ _ _ _ _ _ _ _

CONFIG. (1,8,9, & 16)

,~TE 5

r.

L

~

~G~jC \3t 1. .1
D

•

NOTES:
1. LEADSWITHINO.13mm
(0.005) RADIUS OF TRUE
POSITION ATSEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.

PLANE

3. DIMENSION "8" DOES NOT
INCLUDE MOLO FLASH.
4. "F" DIMENSION IS FOR FULL
LEADS. "HALF" LEADS ARE
OPTIONAL AT LEAD POSITIONS
1,8,9, and 16).
5. ROUNDED CORNERS OPTIONAL.

7-4

DIM
A

MECHANICAL DATA (Continued)

- - - - - - - - - 1 8 · P I N PACKAGES--------P SUFFIX
PLASTIC PACKAGE
CASE 707-02

MILLIMETERS
DIM MIN MAX
A 22.22 23.24
6.60
6.10
B
3.56
4.57
C
0.56
D
0.36
1.27
1.18
F
2.54 BSC
G
1.52
1.02
H
J
0.20
0.30
3.43
K
2.92
7.6 BSI
15 0
M
00
0.51
1.02
N

NOTES:
1. POSITIONAL TOLERANCE OF LEADS 101,
SHALL BE WITHIN 0.25mm(0.0101 AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.

INCHES
MIN MAX
0.875 0.915
0.240 0.260
0.140 0.180
0.014 0.022
0.05U 0.070
0.100 8SC
0.040 0.060
0.008 0.012
0.115 0.135
0.30 Bse
150
00
0.020 0.040

L SUFFIX
CERAMIC PACKAGE
CASE 726-04

MILLIMETERS
DIM MIN
MAX
A 22.35 23.11
B
6.10
7.49
C
5.08
0
0.38
0.53
F
1.40
1.18
G
2.548SC
H
0.51
1.14
0.20
J
0.30
K
3.18
4.32
7.628SC
l
00
M
150
N
0.51
1.02

NOTES:
1. LEADS, TRUE POSITIONED 2. DIM "L"TD CENTER OF
WITHIN 0.25 mm (0.010) DIA.
LEADS WHEN FORMED
AT SEATING PLANE, AT
PARALLEL.
MAXIMUM MATERIAL
3. DIM "A" & "8" INCLUDES
CONDITION.
MENISCUS.

7·5

INCHES
MIN
MAX
0.880 0.910
0.240 0.295
- 0.200
0.015 0.021
0.055 0'.070
0.1008SC
0.020 0.045
0.008 0.012
0.125 0.170
0.300 BSC
OD
15D
0.020 0.040

MECHANICAL DATA (Continued)

- - - - - - - - 2 0 · P I N PACKAGES--------L SUFFIX
CERAMIC PACKAGE
CASE 732-03

DIM
A
S

C
D
F
G
H
NOTES:
1. lEADS WITHIN 0.25 mm (0.010)
CIA, TRUE POSITION AT
SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.

J
2. DIM l TO CENTER OF lEADS
WHEN FO RMEO PARALLEL.
3. DIM A AND S INCLUDES
MENISCUS.

K
L
M
N

MILLIMETERS
MIN
MAX
23.88 25.15
6.60
7.49
3.S1
5.0S
0.38
0.56
1.40
1.65
2.54 SSC
0.51
1.27
0.20
0.30
3.18
4.06
7.62 SSC
00
15 0
1.02
0.25

INCHES
MIN
MAX
0.940 0.990
0.260 0.295
0.150 0.200
0.015 0.022
0.055 0.065
0.100 SSC
0.020 0.050
O.OoBI 0.012
0.125 0.160
0.300 asc
oo::r 150
0.010 I 0.040

P SUFFIX
PLASTIC PACKAGE
CASE 738-02

MILLIMETERS
MIN
MAX
25.65 27.18
6.10
6.60
a
3.94 4.57
C
0.38
0.56
D
1.27
1.78
F
2.54 asc
G
0.20 0.38
J
3.56
K
2.79
L
7.62 asc
150
M
00
N
0.51 I 1.02

DIM
A

•

NOTES:
1. OIMQD IS DATUM.
2. POSITIONAL TOl FOR lEADS;
Itll'l' 0.25 (O.OlOI@jT I Ael
3. II] IS SEATING PLANE.

4. DIM "S" DOES NOT INCLUDE MOLD FLASH.
5. DIM
TD CENTER DF LEADS WHEN
FORMED PARALLEL .
6. DIMENSIONING AND TDLERANCING
PER ANSI Y14.5, 1973.

rn

7-6

INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.155 0.180
0.015 0.022
0.050 0.070
0.100 asc
0.008 0.015
0.110 0.140
0.300 ase
150
00
0.020 0.040

MECHANICAL DATA (Continued)

- - - - - - - - 22·PIN PACKAGES - - - - - - - _
P SUFFIX
PLASTIC PACKAGE
CASE 708-04

A

HI--

-IGI-NOTES:
1. POSITIONAL TOLERANCE OF LEADS (0).
SHALL BE WITHIN 0.25mm(0.010) AT
MAXIMUM MATERIAL CONDITION. IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEl.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.

MILLIMETERS
MAX
DIM MIN
A 27.56 28.32
8.64
9.14
B
3.94
C
5.08
0.56
0
0.36
F
1.27
1.78
2.54 SSC
G
1.02
H
1.52
0.38
J
0.20
2.92
3.43
K
10.16SSC
L
00
M
15 0
0.51
1.02
N

INCHES
MIN MAX
1.085 1.115
0.340 0.360
0.155 0.200
0.014 0.022
0.050 0.070
0.100 SSC
0.040 0.060
0.008 0.015
0.115 0.135
0.400 SSC
150
00
0.020 0.040

MILLIMETERS
DIM MIN
MAX
A 26.80 27.81
8
9.14 9.91
C
3.81
5.46
0
0.38 0.53
F
1.27 1.65
2.54 SSC
G
H
0.51
1.27
J
0.20 0.30
K
3.18 4.32
9.91 10.41
L
150
M
N
0.25 0.89

INCHES
MIN MAX
1.055 1.095
0.360 0.390
0.150 0.215
0.01.5 0.021
0.050 0.065
0.100 SSC
0.020 0.050
0.008 0.012
0.125 0.170
0.390 0.410
- 150
0.010 0.035

L SUFFIX
CERAMIC PACKAGE
CASE 736-03

I~~~~~~~~~]J
I

A

I ~

r,=l=J

J~JM\
PLANE

NOTES:
1. LEADS TRUE POSITIONED
WITHIN 0.25 mm (0.010) DIA AT
SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (DIM "D").
2. DIM "L" TO CENTER OF LEADS
WHEN FO RMED PARALLEl.

7·7

MECHANICAL DATA (Continued)

--------24·PIN PACKAGES-------L SUFFIX
CERAMIC PACKAGE
CASE 623-05

NOTES:
1. OIM "L" TO CENTER OF
LEADS WHEN FORMED
PARALLEl.

2. LEAOS WITHIN 0.13 mm
(0.0051 RADIUS OF TRUE
POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL
CONOITION. (WHEN FORMEO
PARALLEL).

DIM
A
B
e
0
F
G
J
K
L
M
N

MILLIMETERS
MIN MAX
31.24 32.77
12.70 15.49
4.06 5.59
0.41 0.51
1.27 1.52
2.54 Bse
0.20 0.30
3.18 4.06
15.24 BSC
15"
0°
0.51
1.27

INCHES
MIN MAX
1.230 1.290
0.500 0.610
0.160 0.220
0.016 0.020
0.050 0.060
0.100 BSC
0.008 0.012
0.125 0.160
0.600 Bse
15°
0"
0.020 0.050

MILLIMETERS
MIN
MAX

INCHES
MIN
MAX

31.50 32.13
13.21 13.72
4.70 5.21
0.38 0.51
1.02 1.52
2.54 Bse
1.65 2.16
0.20 0.30
2.92 3.43
14.99 15.49
- 100
0.51 1.02
0.13 0.38
0.51 0.76

1.240 1.265
0.520 0.540
0.185 0.205
0.015 0.020
0.040 0.060
0.100 Bse
0.065 0.085
0.008 0.012
0.115 0.135
0.590 0.610
100
0.020 0.040
0.005 0.015
0.020 0.030

P SUFFIX
PLASTIC PACKAGE
CASE 649-03

DIM
A
8
e

0
F

G
H
J

NOTES:
1. LEAOS WITHIN 0.13 mm (0.005)
RADIUS OF TRUE POSITION AT
SEATING PLANE AT MAXIMUM
MATERIAL CONOITION.
2. DIMENSION "L"TO CENTER OF
LEAOS WHEN FORMED PARALLEL.

K
L

M
N
p
Q

7·8

MECHANICAL DATA (Continued)

- - - - - - - 2 4 · P I N PACKAGES (Continued)------P SUFFIX
PLASTIC PACKAGE
CASE 700-02
24

13

1

B

12

PLANE

NOTES:
1. POSITIONAL TOLERANCE OF LEAOS (01,
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE ANO
EACH OTHER.

2. OIMENSION L TO CENTER OF LEAOS
WHEN FORMEO PARALLEL.
3. OIMENSION B ODES NOT INCLUDE MOLO
FLASH.

7·9

MILLIMETERS
DIM MIN
MAX
A
31.37 32.13
B
13.72 14.22
C
3.94
5.08
0.56
D
0.36
F
1.02
1.52
2.54 BSC
G
H
1.65
2.03
J
0.20
0.38
K
2.92
3.43
l
15.24 BSC
M
150
00
N
0.51.1 1.02

INCHES
MIN
MAX
1.235 1.265
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.080
0.008 0.015
0.115 0.135
0.600 BSC
00
15 0
0.020 I 0.040

MECHANICAL DATA (Continued)

- - - - - - - - 2 8 · P I N PACKAGES - - - - - - - P SUFFIX
PLASTIC PACKAGE
CASE 710-02

2.

15

B

PLANE

NOTES:
I. POSITIONAL TOLERANCE OF LEADS 10),

SHALL BE WITHIN 0.25mm(0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.

2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEl.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.

MI LL IMETE RS
DIM MIN
MAX
A 36.45 37.21
13.72 14.22
8
3.94 5.08
C
0.56
0.36
0
1.02 1.52
F
2.54 BSC
G
H
1.65 2.16
0.38
0.20
J
2.92
3.43
K
15.24 BSC
L
00
15 0
M
N
0.51
1.02

INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 8se
0.065 0.085
O.OOB 0.015
0.115 0.135
0.600 BSC
00
15 0
0.020 0.040

Z SUFFIX
CHIP CARRIER
CASE 763-01

F

I---R--~-1

f----L-

•

MILLIMETERS
DIM MIN
MAX
A 12.01 12.49
B 11.48 11.88
C
1.32
1.72
0.43
0
0.58
G
1.27 BSC
1.19
H 0.83
9.47
9.95
L
N
2.03
1.52
R 8.94
9.34

NOTES:
1. DIMENSIONS A AND L ARE
DATUMS.
2. T IS A GAUGE PLANE.
3. POSITIONAL TOLERANCE FOR
TERMINALS (D): 28 PLACES.
1.10.15(0.006) ~I T
4. DIMENSIONING AND TDLERANCING
PER ANSI Y14.5, 1973.

I A@I L@I

7·10

INCHES
MIN
MAX
0.473 0.492
0.452 0.468
0.052 0.068
0.017 0.023
0.050 BSC
0.033 0.047
0.373 0.392
0.060 0.080
0.352 0.368

MECHANICAL DATA (Continued)

- - - - - - - - - 4 0 · P I N PACKAGES - - - - - - - - P SUFFIX
PLASTIC PACKAGE
CASE 711-03

DIM

A
B
C
0

F

G
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (01.
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION. IN
RELATION TO SEATING PLANE AND
EACH OTHER.

H
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.

7-11

J
K
L
M
N

MILLIMETERS
MIN
MAX
51.69 52.45
13.72 14.22
3.94
5.08
0.56
0.36
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
15°
0°
0.51
1.02

INCHES
MLN
MAX
2.035 2.065
0.540 0.560
0.155 0.200
0.014 0022
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.015
0.115 0.135
0.600 BSC
15°
0°
0.020 0.040

•

•

7·12

•

Selection Guides

•

Data Sheets

•

Application Notes and
Technical Articles

•

Glossary

•

Handling end Design
Guidelines

•

Quality and Reliability

•

Mechanical Data



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