1985_National_EEPROM_Databook 1985 National EEPROM Databook

User Manual: 1985_National_EEPROM_Databook

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EEPROM
DATABOOK

Datasheets
Application Notes
Reliability Information
Physical Dimensions

•III
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Table of Contents
DATASHEETS

NMC9306/COP494 256-Bit Serial Electrically Erasable Programmable Memory ............ 1-3
NMC9306E/COP494E 256-Bit Serial Electrically Erasable Programmable Memory ......... , 1-8
NMC9307E 256-Bit Serial Electrically Erasable Programmable Memory .................... 1-13
NMC9345/COP495 1024-Bit Serial Electrically Erasable Programmable Memory (5V Only) .. 1-18
NMC9346/COP495 1024-Bit Serial Electrically Erasable Programmable Memory (5V Only) .. 1-23
NMC9346E/COP395 1024-Bit Serial Electrically Erasable Programmable Memory (5V Only) .1-28
NMC9802 2048-Bit Parallel (256 x 8) Electrically Erasable Programmable ROM ... '" ....... 1-33
NMC9816A 16,384-Bit (2k x 8) EEPROM .............................................. 1-39
NMC981716,384-Bit(2k x 8) EEPROM ............................................... 1-45
NMC9817A 16,384-Bit (2k x 8) EEPROM .............................................. 1-50
NMC98C64A 8k x 8 CMOS Electrically Erasable PROM ....................... '" ....... 1-56
APPLICATION NOTES

AB-13 Avoiding Problems Caused by Capacitive Coupling Between Input Signal Lines or 21Volt EEPROMs .................................................................. 2-3
AB-15 Protecting Data in the NMC9306/COP494 and NMC9346/COP495 Serial EEPROMs . 2-5
AB-17 Using EEPROMs with ROMless Single Chip Microcontroller . . . . . . . . . . . . . . . . . . . . . . .. 2-7
AN-328 EEPROM Application Note Vpp Generation on Board. . . . . . . . . . . . . . . . . . . .•. . . . . . .. 2-9
AN-338 Designing with the NMC9306/COP494, a Versatile Simple to Use EEPROM ........ 2-15
AN-342 Designing with the NMC9817, a 2nd Generation EEPROM ........................ 2-22
RELIABILITY INFORMATION

The A + Reliability Enhancement Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
Reliability Qualification Procedure for All EEPROM Products ............................. 3-5
PHYSICAL DIMENSIONS

Physical Dimension Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3

vii

Alpha-Numerical Index
AB-13 Avoiding Problems Caused by Capacitive Coupling Between Input Signal Lines on
21-Volt EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
AB-15 Protecting Data in the NMC9306/COP494 and NMC9346/COP495 Serial EEPROMs . 2-5
AB-17 Using EEPROMs with ROM less Single Chip Microcontroller . . . . . . . . . . . . . . . . . . . . . . .. 2-7
AN-328 EEPROM Application Note Vpp Generation on Board. . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-9
AN-338 Designing with the NMC9306/COP494, a Versatile, Simple to Use EEPROM ........ 2-15
AN-342 Designing with the NMC9817, a 2nd Generation EEPROM ........................ 2-22
NMC9306/COP494 256-Bit Serial Electrically Erasable Programmable Memory ............ 1-3
NMC9306E/COP494E 256-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . .. 1-8
NMC9307E 256-Bit Serial Electrically Erasable Programmable Memory .................... 1-13
NMC9345/COP495 1024-Bit Serial Electrically Erasable Programmable Memory (5V Only) .. 1-18
NMC9346/COP495 1024-Bit Serial Electrically Erasable Programmable Memory (5V Only) .. 1-23
NMC9346E/COP395 1024-Bit Serial Electrically Erasable Programmable Memory (5V Only) . 1-28
NMC9802 2048-Bit Parallel (256 x 8) Electrically Erasable Programmable ROM ............. 1-33
NMC9816A 16,384-Bit (2k x 8) EEPROM .............................................. 1-39
NMC9817 16,384-Bit (2k x 8) EEPROM ............................................... 1-45
NMC9817 A 16,384-Bit (2k x 8) EEPROM .............................................. 1-50
NMC98C64A 8k x 8 CMOS Electrically Erasable PROM ................................. 1-56
Reliability Qualification Procedure for All EEPROM Products ............................. 3-5
The A + Reliability Enhancement Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3

viii

Section 1

I
I

Datasheets

,---------------------------------------------------------------------, z

'?A National
~ Semiconductor

o
co

~
.....

NMC9306/COP494 256-Bit Serial Electrically Erasable
Programmable Memory
General Description

Features

The NMC9306/COP494 is a 256-bit non-volatile sequential
access memory fabricated using advanced floating gate
N-channel E2PROM technology. It is a peripheral memory
designed for data storage and/or timing and is accessed via
the simple MICROWIRETM serial interface. The device contains 256 bits of read/write memory divided into 16 registers
of 16 bits each. Each register can be serially read or written
by a COP400 series controller. Written information is stored
in a floating gate cell with at least 10 years data retention
and can be updated by an erase-write cycle. The
NMC9306/COP494 has been designed to meet applications requiring up to 1 x 104 erase/write cycles per register.
A power down mode reduces power consumption by 70 percent.

•
•
•
•
•
•
•
•
•

,.---.

.Iloo

Low cost
Single supply operation (5V ± 10%)
TTL compatible
16 X 16 serial read/write memory
MICROWIRE compatible serial I/O
Compatible with COP400 processors
Low standby power
Non-volatile erase and write
Reliable floating gate technology

Block and Connection Diagrams
VPP
GENERATOR

Dual-In-Line Package

j+-VCC

VCC

GNO

VPP

+
DECODER
1/16

ADDRESS
LATCHES

E'PROM
256 BITS
116x 16)

TLlD/5029-10

Top View

R/WAMPS

so Package

;-+I

DATA
REGISTER
117 BITS)

CLKI.L-

'10-

INSTRUCTION
t
REGISTER ClK
19 BITS)

l..t

INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATORS

CS
SK

Vec

GND

Tl/D/5029-2

Top View
Order Number NMC9306N,
NMC9306
See NS Package NOSE or M14B

.J:
'--

--+

t-t---

Tl/D/5029-1

1-3

Pin Names
CS
Chip Select
SK
Serial Data Clock
01
Serial Data Input
DO
Serial Data Output
Power Supply
Vee
GND
Ground

Q)
~

a..

o
o
......
CD

oC")

o
z

Absolute Maximum Ratings
Voltage Relative to GNO

+6Vto -0.3V

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Ambient Operating Temperature
NMC9306/COP494

O'C to + 70'C

Ambient Storage Temperature
with Data Retention

- 65'C to + 125'C

Lead Temperature (Soldering, 10 seconds)

300'C

Electrical Characteristics O'C ,,;TA,,; 70'C, Vee=5V ± 10% unless otherwise specified
Parameter

Conditions

Min

Operating Voltage (Vee>

Typ

Max

4.5

Units

5.5

Operating Current (lee1)

Vee=5.5V, CS= 1

Standby Current (lee2)

Vee=5.5V, CS=O

0.8
Vee + 1

V
V

0.4

V
V
IJ.A

Input Voltage Levels
-0.1
2.0

VIL
VIH
Output Voltage Levels
IOL =2.1 mA
IOH = - 400 iLA

VOL
VOH

2.4

Input Leakage Current

VIN=5.5V

Output Leakage Current

VOUT= 5.5V, CS=O

IJ.A

250

kHz

SK Frequency
SK HIGH TIME tSKH (Note 2)
SK LOW TIME tSKL (Note 2)

0
1
1

Input Set-Up and Hold Times
CS
tess

0.2
0
0.4
0.4

tesH
to IS
tOIH

01
Output Delay
DO

Erase/Write Pulse Width (tE/W) (Note 1)

10
1

Note 1: tE/W measured to rising edge of SK or

es, whichever occurs

2
2

/ks
IJ.s

ms
IJ.s

last.

Note 2: The SK frequency spec. specifies a minimum SK clock period of 4 p.s, therefore in an SK clock cycle,
=

IJ.s
IJ.s
IJ.s
IJ.s

CL= 100 pF
VOL =0.8V, VOH=2.0V
VIL =0.45V, VIH=2.40V

tp01
tpoo

CS Low Time (tes) (Note 3)

e.g. jf tSKL

IJ.s
IJ.s

tSKH

tsKL must be greater than or equal to 4 /LS.

1 J.l.s then the minimum tSKH = 3 J..A-s in order to meet the SK frequency specification.

Note 3: CS must be brought low for a minimum of 1 f-Ls ('les) between consecutive instruction cycles.

Instruction Set
S8

OpCode

Address

READ

10xx

A3A2A1AO

WRITE

01xx

A3A2A1AO

ERASE

llxx

A3A2A1AO

Erase register A3A2A 1AO

EWEN

0011

xxxx

Erase/write enable

EWOS

0000

xxxx

Erase/write disable

ERAL

0010

xxxx

Erase all registers

WRAL

0001

xxxx

Instruction

Data

Comments
Read register A3A2A 1AO

015-00

Write register A3A2A 1AO

Write all registers

NMC9306/COP494 has 7 instructions as shown, Note that MSB of any given instruction is a "1" and is viewed as a
start bit in the interface sequence, The next 8 bits carry the op code and the 4-bit address for 1 of 16, 16-bit registers,
X is a don't care state,

1-4

z
oCD

:s:::

Functional Description
set to Os). After an ERASE instruction is input, CS is
dropped low. This falling edge of CS determines the start of
programming. The register at the address specified in the
instruction is then set entirely to 1s. When the erase/write
programming time (tE/W) constraint has been satisfied, CS
is brought up for at least one SK period. A new instruction
may then be input, or a low-power standby state may be
achieved by dropping CS low.

The NMC9306/COP494 is a small peripheral memory intended for use with COPSTM controllers and other non-volatile memory applications. Its organization is sixteen registers
and each register is sixteen bits wide. The input and output
pins are controlled by separate serial formats. Seven 9-bit
instructions can be executed. The instruction format has a
logical '1' as a start bit, four bits as an op code, and four bits
of address. SK clock cycle is necessary after CS equals
logical "1" before the instruction can be loaded. The onchip programming-voltage generator allows the user to use
a single power supply (Vecl. Only during the read mode is
the serial output (DO) pin valid. During all other modes the
DO pin is in TRI-STATE®, eliminating bus contention.

Co)

oQ)

o"tJ
.,I>.

.,I>.

WRITE (Note 4)
The WRITE instruction is followed by 16 bits of data which
are written into the specified address. This register must
have been previously erased. Like any programming mode,
erase/write time is determined by the low state of CS following the instruction. The on-chip high voltage section only
generates high voltage during these programming modes,
which prevents spurious programming during other modes.
When CS rises to VIH, the programming cycle ends. All programming modes should be ended with CS high for one SK
period, or followed by another instruction.

READ
The read instruction is the only instruction which outputs
serial data on the DO pin. after a READ instruction is received, the instruction and address are decoded, followed
by data transfer from the memory register into a 16-bit serial-out shift register. A dummy bit (logical '0') precedes the
16-bit data output string. Output data changes are initiated
by a low to high transition of the SK clock.

CHIP ERASE (Note 4)

Entire chip erasing is provided for ease of programming.
Erasing the chip means that all registers in the memory array have each bit set to a 1. Each register is then ready for a
WRITE instruction.

ERASE/WRITE ENABLE AND DISABLE

Programming must be preceded once by a programming
enable (EWEN) instruction. Programming remains enabled
until a programming disable (EWDS) instruction is executed.
The programming disable instruction is provided to protect
against accidental data disturb. Execution of a READ instruction is independent of both EWEN and EWDS instructions.

CHIP WRITE (Note 4)

All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle, except for
the different op code. All registers are simultaneously written with the data pattern specified in the instruction.

ERASE (Note 4)

Note 4: During a programming mode (write, erase, chip erase, chip write),
SK clock is only needed while the actual instruction, i.e., start bit, op code,
address and data, is being input. It can remain deactivated during the Erase/

Like most E2PROMS, the register must first be erased (all
bits set to 1s) before the register can be written (certain bits

Write pulse width (tE/W)'

Timing Diagrams

------1.1
____. . Fts
. ,. Its" ="r----'""'IL-_____
~-4 ".

VOL
TL/D/5029-3

*This is the minimum SK period

Synchronous Data Timing

1-5

NMC9306/COP494
-I

'Lrl..rULI1

5"
ce

READ
DI

.-l

\\0-_ __

CS /

Di"

,..,_______________

~)C?\

til

iffi

TLlD/5029-4

1...f1SU lJ1Sl

WRITE~

J
~

~1Er::::::d

~~::x-;-\

c:x:::x:
TL/D/5029-5

UlSl
K

ERASE { CS

~~:=::I

OI~
TLlD/5029-6

*tEIV.,I measured to rising edge of SK or es, whichever occurs last

Instruction Timing

-t

3"
5"

SK
EWEN
EWDS

(ERASE/WRITE
ENABLE/DISABLE)

f--

\'-___________

DI--.r:\ 0

Ul
~
I»

c
Sir
en

ENABLE = 11
DISABLE=OO
TL/0/5029-7

~::J
5c:
CD

,9,

1...fl.IlJlJlSLfL

CS/

~::d

WRAL
(WRITE ALL)

.!"

DI--.J7\

~JC€\"

x:
TL/0/5029-8

ERAL
(ERASE ALL)

J cs

C:::ElW~

--'

DI~O

0\o~
TL/0/5029-9

*t E/W measured to rising edge of SK

es, whichever occurs last.

Instruction Timing (Continued)

P6PdOO/90£60WN

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en
"!i:I"

r------------------------------------------------------------------------,

~National

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::E

NMC9306E/COP494E 256-Bit Serial Electrically Erasable
Programmable Memory

General Description

Features

The NMC9306E/COP494E is a 256-bit non-volatile sequential access memory fabricated using advanced floating gate
N-channel E2PROM technology. Itis*&-peripheral memory
designed for data storage and/or timing and is accessed via
the simple MICROWIRETM serial interface. The device contains 256 bits of read/write memory divided into 16 registers
of 16 bits each. Each register can be serially read or written
by a COP400 series controiler. Written information is stored
in a floating gate cell with at least 10 years data retention
and can be updated by an erase-write cycle. The
NMC9306E/COP494E has been designed to meet applications requiring up to 1 X 104 erase/write cycles per register.
A power down mode reduces power consumption by 70 percent.

•
•
•
•
•
•
•
•
•

Low cost
Single supply operation (5V ± 10%)
TTL compatible
16 x 16 serial read/write memory
MICROWIRE compatible serial I/O
Compatible with COP400 processors
Low standby power
Non-volatile erase and write
Reliable floating gate technology

Block and Connection Diagrams

Dual-in-Line Package

VCC

vee

GND

TLID/5159-2

Top View

SO Package

01-1-+-+-+---+--....

Vee

GNO

NC
L-------...JTL/O/5159_10

Top View
FiGURE 2
Order Number NMC9306NE, 9306
See NS Package NOSE, M14B
Pin Names

CS~~-------------------.I

INSTRUCTION
DECODE,
CONTROL
ANO
CLOCK
GENERATORS

SK-----------------------..
TL/D/5159-1

1-8

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

VCC

Power Supply

GND

Ground

Absolute Maximum Ratings
Note: Stresses above those listed under "Absolute Maxi·
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicat·
ed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

+6Vto -0.3V

Voltage Relative to GND
Ambient Operating Temperature
NMC9306E/COP494E

-40'Cto + 85'C

Ambient Storage· Temperature
with Data Retention

- 65'C to + 125'C
300'C

Lead Temp. (Soldering, 10 seconds)

Electrical Characteristics. -40'C :s; TA:S;

+B5'C, vcc= 5V ± 10% unless otherwise specified

Conditions

Parameter

Min

Typ

Max

4.5

Operating Voltage (VCC)

Units

5.5

Operating Current (ICC1)

VCC=5.5V, CS= 1

Standby Current (ICC2)

VCC=5.5V, CS=O

0.8
VCC+1

V
V

0.4

V
V

Input Voltage Levels
VIL
VIH

- 0.1
2.0

Output Voltage Levels
VOL
VOH

IOL=2.1 mA
IOH= -400 ",A

Input Leakage Curreht

VIN=5.5V

",A

Output Leakage Current

VOUT=5.5V, CS=O

",A

250

kHz
",5
,,"5

2.4

SK Frequency
SK HIGH TIME tsKH (Note 2)
SK LOW TIME T SKL (Note 2)

0
1
1

Input Set·up and Hold Times
CS
Tess
tesH
DI
tOIS
tOIH

0.2
0
0.4
0.4

Output Delay
DO
tp01
tpoo

,,"5
,,"5

CL = 100pF
VOL = 0.8V, VOH = 2.0V
VIL = 0.45V, VIH = 2.40V

Erase/Write Pulse Width (tE/W) (Note 1)

CS Low Time (tes) (Note 3)

2
2

,,"5
,,"5

ms
,,"5

Note 1: tE/w measured to rising edge of SK or CS, whichever occurs last.
Note 2: The SK frequency spec. specifies a minimum SK clock period of 4 JLs, therefore in an SK clock cycle, tsKH
e.g. if tSKL = 1 /Ls then the minimum tSKH = 3 }ks in order to meet the SK frequency specification.
Note 3: CS must be brought low for a minimum of 1

+ tSKL must be greater than or equal to 4 p.s.

,...8 (tcs) between consecutive instruction cycles.

Instruction Set
58

OpCode

Address

READ

10xx

A3A2A1AO

WRITE

01xx

A3A2A1AO

ERASE

11xx

A3A2A1AO

Erase register A3A2A1AO

Instruction

Data

Comments
Read register A3A2A 1AO

D15·DO

Write register A3A2A 1AO

EWEN

0011

xxxx

Erase/write enable

EWDS

0000

Erase/write disable

ERAL

0010

WRAL

0001

xxxx
xxxx
xxxx

Erase all registers
D15·DO

Write all registers

NMC9306E/eOP494E has 7 instructions as shown. Note that MSB of any given instruction is a "'1"' and is
viewed as a start bit in the interface sequence. The next 8 bits carry the op code and the 4-bit address for 1 of

16, 16·bit registers.
X is a don't care state.

FIGURE 3

1·9

W
~
G)
~

a..

"w
CD

C)
C')
G)

o
z

::!!

r---------------------------------------------------------------------------~

Functional Description
The NMC9306E/COP494E is a small peripheral memory in·
tended for use with COPSTM controllers and other non·vola·
tile memory applications. Its organization is sixteen registers
and each register is sixteen bits wide. The input and output
pins are controlled by separate serial formats. Seven 9·bit
instructions can be executed. The instruction format has a
logical '1 ' as a start bit, four bits as an op code, and four bits
of address. SK clock cycle is necessary after CS equals
logical "1" before the instruction can be loaded. The on·
chip programming·voltage generator allows the user to use
a single power supply (VCC). Only during the read mode is
the serial output (DO) pin valid. During all other modes the
DO pin is in TRI·STATE®, eliminating bus contention.

set to Os). After an ERASE instruction is input, CS is
dropped low. This falling edge of CS determines the start of
programming. The register at the address specified in the
instruction is then set entirely to 1s. When the erase/write
programming time (tE/W) constraint has been satisfied, CS
is brought up for at least one SK period. A new instruction
may then be input, or a low·power standby state may be
achieved by dropping CS low.
WRITE (Note 4)

The WRITE instruction is followed by 16 bits of data which
are written into the specified address. This register must
have been previously erased. Like any programming mode,
erase/write time is determined by the low state of CS fol·
lowing the instruction. The on·chip high voltage section only
generates high voltage during these programming modes,
which prevents spurious programming during other modes.
When CS rises to VIH, the programming cycle ends. All pro·
gramming modes should be elided with CS high for one SK
period, or followed by another instruction.

READ
The read instruction is the only instruction which outputs
serial data on the DO pin. After a READ instruction is reo
ceived, the instruction and address are decoded, followed
by data transfer from the memory register into a 16·bit serio
al·out shift register. A dummy bit (logical '0') precedes the
16·bit data output string. Output data changes are initiated
by a low to high transition of the SK clock.

CHIP ERASE (Note 4)

Entire chip erasing is provided for ease of programming.
Erasing the chip means that all registers in the memory ar·
ray have each bit set to a 1. Each register is then ready for a
WRITE instruction.
.

ERASE/WRITE ENABLE AND DISABLE

Programming must be preceded once by a programming
enable (EWEN) instruction. Programming remains enabled
until a programming disable (EWDS) instruction is executed.
The programming disable instruction is provided to protect'
against accidental data disturb. Execution of a READ in·
struction is independent of both EWEN and EWDS instruc·
tions.

CHIP WRITE (Note 4)

All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle, except for
the different op code. All registers are Simultaneously writ·
ten with the data pattern specified in the instruction.

ERASE (Note 4)

Note 4: During a programming mode (write, erase, chip erase. chip write),
SK clock is only needed while the actual instruction. i.e. start bit. op code,
address and data, is being input. It can remain deactivated during the Erase/
Write pulse width (tEW)'

Like most E2PROMS, the register must first be erased (all
bits set to 1s) before the register can be written (certain bits

Timing Diagrams

I·

4 ~$*

FISK.

-I-

DO
TL/D/5159-3

.. This is the minimum SK period

FIGURE 4. Synchronous Data Timing

1010

::!
3
SK

- --- ---

---- --,

::l
CC

1.SLrLJlJl.
------\'-----

READ
DI

----1

~:::x-:!\

WRITE { CS

CC
~
S»

,>-,_ _ _ _ _ _ _ _ _ _ _ _ __

til

?i
o

---------------I~
0
r;;;:v;;;-v-'

TL/0/5159-4

Ul..fU1JLJl

.:.

c
iii"

.I
~

l~~ _____ "

~IEI:!:::::::I

~~::x:uu-\

c::x::x:
TLlD/5159-5

1JLJl

ERASE { CS

~E::::::::I

DI~
TLI015159-6

*tE/W measured to rising edge of SK or CS, whichever occurs last.

FIGURE 5. Instruction Timing

3\76\7dO~/390E6~WN

iii

NMC9306E/COP494E
-I

s·

CQ
EWfN

EWDS
(ERASE/WRITE
ENABl£IDISABLE)

. - ,__________

iii'

DI~O

D1
3
en

~
ENABLE-11
DlSABLE=OO
TLlD/5159-7

~g.
<:

ULfl...rLrLflSL

SK
WRAL
(WRITE ALL)

esJ

---- - - -- ------

DI~O

J\)

~::.:::::I

0/1~::x-;-\

11\

x:
TLlD/5159-8

ERAL
(ERASE ALL)

'c=..1E~

esl
DI--"",O

o{>\

"tE/W measured to rising edge of SK or CS, whichever occurs last.

FIGURE 5. Instruction Timing (Continued)

z
:s:
oCD

~National

c.l

~ Semiconductor

o
......
m

NMC9307E 256-Bit Serial Electrically Erasable
Programmable Memory
General Description

Features

The NMC9307E is a 256-bit non-volatile sequential access
memory fabricated using advanced floating gate N-channel
E2PROM technology. It is a peripheral memory designed for
data storage and/or timing and is accessed via the simple
MICROWIRETM serial interface. The device contains 256
bits of read/write memory divided into 16 registers of 16 bits
each. Each register can be serially read or written by a
COP400 series controller. Bulk programming instructions
(chip erase, chip write) can be enabled or disabled by the
user for enhanced data protection. Written information is
stored in a floating gate cell with at least 10 years data
retention and can be updated by an erase-write cycle. The
NMC9307E has been designed to meet applications requiring up to 1 x 10 4 erase/write cycles per register. A power
down mode reduces power consumption by 70 percent.

• Low cost
• Single supply operation (5V
•
•
•
•
•
•
•
•

10%)

TTL compatible
16 x 16 serial read/write memory
MICROWIRE compatible serial I/O
Compatible with COP400 processors
Low standby power
Non-volatile erase and write
Reliable floating gate technology
Bulk programming enable/disable for
enhanced data protection

Dual-In-Line Package

Block and Connection Diagrams
CS

vee

BPE

GND

VCC

TL/D/8383-10

Top View
SO Package

01-1-+-++--+--.

Vce

SPE

GNO

Top View

TL/D/8383-2

Order Number NMC9307NE, 9307
See NS Package NOSE, M14B

CS-1!---------+,

INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATORS

Pin Names
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Bulk Program Enable
Vee Power Supply
GND Ground
CS
SK
01
DO
BPE

SK---------_+'

B P E - - - - - - - - - _ . L - -_ _--I
TL/D/8383- ;

1-13

Absolute Maximum Ratings
Voltage Relative to GND

~0.3V

+6Vto

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Ambient Operating Temperature
~40'C

NMC9307E

~ 65'C

Ambient Storage Temperature

to + 85'C

to + 125'C

Lead Temp. (Soldering, 10 seconds)

300'C

Electrical Characteristics

~40'C

:0;

Parameter

:0;

+85'C, Vee

= 5V ± 10% unless otherwise specified

Conditions

Min

Operating Voltage (Vecl

Typ

Max

4.5

Units

5.5

Operating Current (Iee1)

Vee

= 5.5V, Cs = 1

rnA

Standby Current (lee2)

Vee

= 5.5V, Cs = 0

rnA

0.8
Vee + 1

V
V

0.4

V
V

±10
±50

I-'A
I-'A

Input Voltage Levels
~0.1

VIL
VIH

2.0

Output Voltage Levels
IOL
IOH

= 2.1 rnA
= ~400 I-'A

Input Leakage Current
PINS 1, 2, 3
PIN6

VIN

= 0 to 5.5V

Output Leakage Current

VOUT

VOL
VOH

2.4

= 5.5V, CS = 0

SK Frequency
SK HIGH TIME tSKH (Note 2)
SK LOW TIME tSKL (Note 2)

0
1
1

Input Set-Up and Hold Times
CS
tess
01
Output Delay
DO

I-'A

250

kHz
I-'s
/-,S

0.2
0
0.4
0.4

tesH
tOIS
tOIH

/-,s
/-,s
/-,S

I-'s

CL = 100 pF
VOL = 0.8V, VOH = 2.0V
VIL = 0.45V, VIH = 2.40V

tp01
tpoo

Erase/Write Pulse Width (tE/W) (Note 1)

2
2

/-,S

CS Low Time (tes) (Note 3)
Note 1: tE/W measured to rising edge of SK or

es,

/-,S

whichever occurs last.

Note 2: The SK frequency spec. specifies a minimum SK clock period of 4 MS, therefore in an SK clock cycle, tSKH
e.g. if tsKL = 1 /-Ls then the minimum tSKH = 3 J.ts in order to meet the SK frequency specification.

+ tSKL must be greater than or equal to 4 /-Ls,

Note 3: CS must be brought low for a minimum of 1 p,S (tes) between consecutive instruction cycles.

Instruction Set
Instruction

Data

BPE

Comments

Read register A3A2A 1AD

Write register A3A2A 1AD

OpCode

Address

10XX

A3A2A1AO

WRITE

01XX

A3A2A1AO

ERASE

11XX

A3A2A1AO

Erase register A3A2A 1AD

EWEN

0011

XXXX

Erase/write enable
Erase/write disable

READ

/-,s

015-00

EWDS

0000

XXXX

ERAL (Note 5)

0010

XXXX

VIH/OPEN

Erase all registers

WRAL (Note 5)

0001

XXXX

VIH/OPEN

Write all registers

015-00

NMC9307E has 7 instructions as shown. Note that MSB of any given instruction is a "1" and is viewed as a start bit
in the interface sequence. The next 8 bits carry the op code and the 4-bit address of 1 of 16, 16-bit registers.

1-14

The NMC9307E is a small peripheral memory intended for
use with COPSTM controllers and other non-volatile memory
applications. Its organization is sixteen registers and each
register is sixteen bits wide. The input and output pins are
controlled by separate serial formats. Seven 9-bit instructions can be executed. The instruction format has a logical
'1' as a start bit, four bits as an op code, and four bits of
address. SK clock cycle is necessary after CS equals logical
'1' before the instruction can be loaded. The on-chip programming-voltage generator allows the user to use a single
power supply (Vecl. Only during the read mode is the serial
output (DO) pin valid. During all other modes he DO pin is in
TRI-STATE®, eliminating bus contention.

The bulk programming instructions (ERAL, WRAL) are enabled or disabled by the PBE pin. The BPE pin at VIH enables execution of these instructions. The BPE pin at VIL
causes these instructions to be ignored. If the BPE pin is not
connected, it is pulled up to Vee by an on-chip pull-up and
the bulk programming instructions are enabled. Execution of
the EWEN, EWDS, READ and byte programming instructions (ERASE, WRITE) are independent of the state of the
BPE pin.

CHIP ERASE (Note 4)
Entire chip erasing is provided for ease of programming.
Erasing the chip means that all registers in the memory array have each bit set to a 1. Each register is then ready for a
WRITE instruction. The chip erase (ERAL) instruction is ignored if the BPE pin is at VIL, i.e. the array data is not
changed.

READ
The read instruction is the only instruction which outputs
serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed
by data transfer from the memory register into a i6-bit serial-out shift register. A dummy bit (logical '0') precedes the
i6-bit data output string. Output data changes are initiated
by the low to high transition of the SK clock.

CHIP WRITE (Note 4)
All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle except for
the different op code. All registers are simultaneously written with the data pattern specified in the instruction. The
chip write (WRAL) instruction is ignored if the BPE pin is at
VIL, i.e. the array data is not changed.

ERASE/WRITE ENABLE AND DISABLE
Programming must be preceded once by. a programming
enable (EWEN) instruction. Programming remains enabled
until a programming disable (EWDS) instruction is executed.
The programming disable instruction is provided to protect
against accidental data disturb. Execution of a READ instruction is independent of both EWEN and EWDS instructions.

Note 4: During a programming mode (write, erase, chip erase, chip write),
SK clock is only nee dod while the actual instruction, Le. start bit, op
code, address and data, is being input. It can remain deactivated
during the Erase/Writo pulso width (tE/W).

Note 5: The ERAL and WRAl. instructions are ignored if the BPE pin is at
V!L, Le. the array data iti not changed.

ERASE (Note 4)
Like most E2PROMS, the register must first be erased (all
bits set to 1s) before the register can be written (certain bits

Timing Diagrams
Synchronous Data Timing

lfo'~~~~ 4 ",* ------1
SK

-~--..1

_ _ _ _....IFtsKH---t-.I-,_-""!!
.

__________~/VOH
TLlD/8383-3

*This is the minimum SK period

1-15

z
s:::
o<0
Co)

o
......

NMC9307E
-I

Instruction Timing

3'
::l

lJl.Jl...rLf1

CS /
READ

----1

,'------

,,.._______________

~)("7\

CJ)

WRITE

< CS

U-UU~

J
~

'~lE:!:::::::I
1

~)G)G!X.:~"

c:x::x:
TLID/8383-5

ERASE {CS /

~E:=::f

---1
TL/0/8383-6

*tE/W measured to rising edge of SK or CS, whichever occurs last.

aor

J;
TLlD/8383-4

CII

'§
c:

i'
to
Dl
3

::!

Instruction Timing (Continued)

::l

iii'

EWEN

(ERASE/:~~ 1cs /

""I

I»

\\._____________________

3f/)

ENABlE/OISABlE)

01--./7\0

;:!
5"

ENABlE~11
DlSABlE~OO

TL/D/8383-7

ERAl
(ERASE All)
iNOTE 5)

-.j

~E=.:t

00\

1..IUl....rLnJ1JL

WRAl
(WRITE All)
INOTE 5)

c(1)

~::.d

CS/

OI~O

O/1~::x-;-\

/1\

X
TL/D/8383-9

*tE/W measured to rising edge of SK or CS, whichever occurs last.

Note 5: The-ERAL and WRAL instructions are ignored if the BPE pin is at VIL, i.e. the array data is not changed.

3LO£6~I/IIN

iii

Lt)
0)

r----------------------------------------------------------------------------,

"="
a.

o ~National
o
......
Lt)
"="
(f)

~ Semiconductor

o NMC9345/COP495 1024-Bit Serial Electrically Erasable
:::!!!
z Programmable Memory (5V Only)
General Description

Features

The NMC9345/COP495 is a 1024-bit non-volatile, sequential E2PROM, fabricated using advanced N-channel
E2PROM technology. It is an external memory with the 1024
bits of read/write memory divided into 64 registers of 16 bits
each. Each register can be serially read or written by a
COP400 controller, or a standard microprocessor. Written
information is stored in a floating gate cell until updated by
an erase and write cycle. The NMC9345 has been designed
for applications requiring up to 104 erase/write cycles per
register. A power-down mode is provided by CS to reduce
power consumption by 75 percent.

•
•
•
•
•
•
•
•
•
•
•

Low cost
Single supply read/write/erase operations (5V±10%)
TTL compatible
64 x 16 serial read/write memory
MICROWIRETM compatible serial I/O
Simple interfacing
Low standby power
Non-volatile erase and write
Reliable floating gate technology
Self-timed programming cycle
Device status signal during programming
Dual-In-Line Package

Block and Connection Diagrams
Serial E2PROM
Vcc-

Vee

GNO

GND-

TL/D17616-2

Top View
SO Package

Vee

GND

DI-+-+++---+--~

TLlD17616-10

Top View
Order Number NMC9345N,
NMC9345
See NS Package NOSE or M14B
Pin Names

CS-+---------~~

INSTRUCTION
DECODE.
CONTROL,
AND CLOCK
GENERATOR

SK----------~~

TL/D17616-1

1-18

Chip Select
Serial Data Clock

Serial Data Input

Serial Data Output

Vee

Power Supply

GND

Ground

Not Connected

+6Vto -0.3V

Voltage Relative to GND
Ambient Operating Temperature

z
oCD

s::

Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature

O°Cto + 70°C

-65°C to + 125°C

Lead Temp. (Soldering, 10 seconds)

300°C

(,)

,j:Io

DC and AC Electrical Characteristics
Parameter

Symbol

NMC9345: O°C 0;; TA 0;; 70°C, Vee~5V±10% unless specified
Conditions

Vee

Operating Voltage

lee1

Operating Current
Erase/Write Operating Current

Vee~5.5V, CS~

Standby Current

Vee~5.5V,CS~0

lee2

o"tJ

SK~

,j:Io

Min

Max

Units

4.5

5.5

12
12

mA
mA

0.8

V
V

Vee~5.5V

Input Voltage Levels
-0.1
2.0

VIL
VIH

Vee+ 1

Output Voltage Levels
IOL ~2.1 mA
IOH~ -400 JLA

VOL
VOH

0.4

V
V
fJ-A

2.4

III

Input Leakage Current

VIN~5.5V

ILO

Output Leakage Current

VOUT~5.5V, CS~O

JLA

250

kHz

tSKH
tSKL

SK Frequency
SK High Time
SK Low Time

tess

Inputs
CS

tcSH
tOIS
tOIH
tpd 1
tpdO
tE/W

0
2
1
0.2
0
0.4
0.4

DI
Output
DO

CL ~100 pF
VOL ~0.8V, VOH~2.0V
VIL ~ 0.45V, VIH ~ 2.40V

Self-Timed Program
Cycle

tes

Min CS Low Time (Note 3)

tsv

Rising Edge of CS to
Status Valid

tOH,t1H

Falling Edge of CS
to DO TRI-STATE®

JLs
fJ-s
JLS
JLS
JLS
JLS
2
2

JLS
JLS

1
CL ~100pF

JLS
1

JLS

0.4

JLS

Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: The SK frequency spec. specifies a minimum SK clock period of 4 /-Ls, therefore in an SK clock cycle tSKH
e.g. if tSKL = 1 j..LS then the minimum tSKH = 3 j..Ls in order to meet the SK frequency specification.

tSKl must be greater than or equal to 4 MS.

Note 3: CS must be brought low for a minimum of 1MS (tcs) between consecutive instruction cycles.

Functional Description
The NMC9345/COP495 is a small peripheral memory intended for use with COPSTM controllers and other non-volatile memory applications. Its organization is Sixty-four registers and each register is sixteen bits wide. The input and
output pins are controlled by separate serial formats. Seven
9-bit instructions can be executed. The instruction format
has a logical' l' as a start bit, two bits as an op code, and six
bits of address. The programming cycle is self-timed, with
the data out (DO) pin indicating the read/busy status of the
chip.

The on-chip programming voltage generator allows the user
to use a single power supply (Vecl. It only generates high
voltage during the programming modes (write, erase, chip
erase, chip write) to prevent spurious programming during
other modes. The DO pin is valid as data out during the read
mode, and if initiated, as a ready/busy status indicator during a programming cycle. During all other modes the DO pin
is in TRI-STATE, eliminating bus contention.

1-19

STANDBY

ERASE

~-4---I~.--

TRI-STATE

______

5'
c

_____

(I)

It.
TRI-STATE

I\J

nn..ruu-u-t

CHECK STATUS

CS /
ERAL
01
DO

~
TRI-STATE

f7\,-_O..,jI/l///lllllllll~"""""
......"""""""""""WA.",,,,,,~.. _+-_+-____-+_ _
1
I,
, :\..!!~

TL/D/5582-5

~National

PRELIMINARY

:s:

oCD

~ Semiconductor

NMC9802 2048-Bit Parallel (256 x 8)
Electrically Erasable Programmable ROM
General Description
The NMC9802 is a 2048 bit electrically erasable programmable read-only memory (E2PROM) organized as 256
words by eight bits. Fabricated using National's double poly
silicon gate n-channel technology, the device utilizes a novel memory architecture that results in the memory operating
as a non-volatile register file. A single bidirectional eight bit
data port is used for transmitting the address, data and
status information. Both address and input data are latched
into onboard registers elminating the need to hold them valid during the long erase/write operation. In addition, all the
erase/write control logic is incorporated on chip completely
freeing the microprocessor once the erase/write cycle has
been initiated. Both a BUSY signal and status register are
available to facilitate easy interface in a wide variety of microprocessor based systems.
The in-system erase/write capability of the NMC9802 make
it suitable for a wide variety of applications requiring a small
amount of alterable non-volatile storage. Any byte can be
erased and written without affecting the rest of memory.
Alternatively, the entire memory can be erased.

device has an on-chip voltage generator eliminating the
need for any high voltage pulses or power supplies. The
single + 5V power supply is all that is required for any operation. The NMC9802 can be a direct replacement for Synertek's SY2802E.

Features
•
•
•
•
•
•
•
•
iii
•
•

Reliable E2 floating gate technology
Microprocessor compatible architecture
On-chip address/data latches
Single cycle byte erase/write capability
Fully TIL compatible
Endurance 1 x 104 write cycles (Min.)
Single + 5V operation
Erase/write specifications guaranteed 0-70'C
On-chip ERASE/WRITE timing and control
Both BUSY signal and status register
Data retention: 10 years (Min.)

The NMC9802 utilizes fully static circuitry and is completely
TTL compatible in the read and erase/write modes. The

Connection and Block Diagrams

00-07 -----9---.;....----1~--_,

Dual In-Line Package
18

(BUSY)' 07

GNO

BUSY
VCC
NC

R/W

ClR

R/W

BUSY

STRB
RS

STRB

cs
ClR
NC

III

TLIO/8348-1

Top View
'SEE STATUS REGISTER
DATA BUS

See Ordering Information

TLID/8348-2

1-33

ClO

o
:E
z

Absolute Maximum Ratings

Comment

Temperature Under Bias

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied.

-10'C to + 80'
- 65'C to 125'

Storage Temperature
Voltage on Any Pin with

-0.5Vto +7V

Respect to Ground

DC Electrical Characteristics TA =
Symbol

Parameter

0'Ct070'C, Vcc

= +5V ±10% (Note 1)

Conditions

Max

Units

III

Input Leakage Current

VIN

= GND to Vcc

Min

Typ

p.A

ILO

Output Leakage Current

VIN

= GND to Vcc

p.A

Outputs Open

Icc

Vcc Current

rnA

VIL

Input LOW Voltage

-0.3

0.8

VIH

Input HIGH Voltage

2.0

Vcc +1

VOL

Output LOW Voltage

IOL

= 3.2 mA

0.4

. VOH

Output HIGH Voltage

IOH

= -1.0 mA

Capacitance TA =

2.4

= 1.0 MHz

25'C, f

Max

Units

COUT

Output Capacitance

CIN

Input Capacitance

Symbol

Typ

Test

Note: This parameter is periodically sampled and not 100% tested.

AC Electrical Characteristics TA =

O'C to 70'C, Vcc

Parameter

Symbol

Conditions

= + 5V ± 10% (Note 1)
Min

Typ

Max

350

Units
ns

tCYC

Cycle Time

tcs

Chip Select Access Time

120

tSA

Valid Data from Strobe

450

200

tLZ

Select to Output LOW Z

tHZ

Select to Output HIGH Z

tAR

Access Time from RS or R/W

(Note 2)

120

tws

Write Setup Time

tWH

Write Hold Time

tDS

Data Setup Time

tDH

Data Hold Time

tSH

Strobe Pulse Width High

ns
ns

tSL

Strobe Pulse Width Low

120

tSA

BUSY Active From Strobe

tSLW

BUSY Low Pulse Width (WRITE)

tSCY

Busy HIGH to Cycle Start

tSLC

BUSY Low Pulse Width (CLEAR)

2: Current goes through

50%

change

from

10H

(MAX)

rns

12.5

rns

Note 1: A minimum 0.5 ms time delay is required after application of Vee (+ 5V) before proper device operation is achieved.
Note

300

or 10L

(MAX).

Note 3: Pins 11 and 16 must be held below Vee during power up.

1-34

z
oCD

Timing Diagrams
Data Fetch (ClR = HIGH, BUSY = HIGH) (Note 1)

c»
o
N

READ DATA OUT PORT

LOAD ADDRESS REGISTER

TL/D/8348-3

Data Store (ClR

HIGH)(Note 1)

III
LOAD ADDRESS REGISTER

LOAD DATA REGISTER

BYTE ERASE/WRITE OPERATION
TLiO/8348-4

1-35

~
~

Timing Diagram

(Continued)
Read Status Register (CLR = HIGH, BUSY = Don't Care) (Note 1)

tcs-_---J

R/W
1~--~----tAR------~

STATUS
TL/D/8348-5

Clear Cycle (Data = Don't Care) (Note 1)

INITIATE CLEAR OPERATION

CLEAR TO ALL ZEROS
TUD/8348-6

A.C. Testing Load Circuit

A.C. Testing Input, Output Waveform
2.4V

+1.9V

2.0V

TEST POINTS

470Q

O.BV

0.4V
INPUT

OUTPUT

AC TESTING: INPUTS ARE ORIVEN AT 2.4V FOR A LOGIC "1"'
ANO O.4V FOR A LOGIC "0". TIMING MEASUREMENTS ARE
MAOE AT 2.0V FOR A LOGIC "1" ANO O.BV FOR A LOGIC "0".
INPUT PULSE RISE ANO FALL TIMES ARE 5ns.

CL = 100pF

CL INCLUOES SCOPE ANO JIG CAPACITANCE

TL/D/8348-7

TL/D/8348-8

1-36

The NMC9802 has seven modes of operation as listed in
Table I. All the modes of the NMC9802 involve reading or
loading registers. This eliminates any timing problems associated with interfacing to a wide variety of microprocessors
and microcomputers.

Reading the NMC9802 involves two cycles as shown in the
timing diagram. First the address pointer is loaded and then
the data from the selected location can be read. Both the
address and data are transmitted through the same eight bit
port.
DATA STORE
Writing the device requires two cycles as shown in the timing diagram. As with the read operation, first the address
pointer must be loaded. Loading the data input register then
initiates the by1e erase/write operation and the microprocessor is free to do other tasks. The timing interface with the
microprocessor is handled with both a BUSY signal and a
status register. Loading the data in register causes the
open-drain BUSY signal to be set LOW and bit seven (pin 1)
of the status register to be set HIGH for the duration of the
by1e erase/write operation. Once complete, these two signals are reset to their inactive states. Note that it is not
necessary for the microprocessor to erase the location prior
to writing new data. This is automatically done by the memory itself.

To facilitate interfacing the NMC9802 in microprocessor
based systems, a status register has been provided that is
accessible at all times including during the erase/write operation. This allows a polling routine to be used to determine if
the NMC9802 is busy. If bit 7 (pin 1) is a logic "1 ", the
device is in the erase/write operation and if it is a logic "0" it
is available for normal operation.
CLEAR CYCLE
The NMC9802 can be block cleared to all zeros as shown in
the timing diagram. As with the data store operation, this
cycle only needs to be initiated, all the timing is controlled
internally. On initiating the clear cycle, BUSY and bit 7 (pin
1) are set active and remain so until the operation is complete. During the clear cycle, only the status register is accessible.
ENDURANCE CHARACTERISTIC
A characteristic of E2PROMs is that the number of erase/
write cycles is limited. The NMC9802 has been designed to
meet applications where up to 1 x 104 erase/write cycles
per word are required. The erase/write cycling is completely
word independent. Adjacent words are not affected during
the erase/write cycling.

TABLE I. Mode Selection Vee

= +5V (Note 1)

Pin
CS
(12)

R/W
(16)

RS
(15)

STRB
(13)

BUSY
(14)

CLR
(11)

Read Register File

Data
Input!
Outputs

(0-7)
Data Out

Read Status Register

Data Out

Write Address Pointer

Data In

Write Data-In Latch

...r
...r

"l.J

Data In

Deselected

HighZ

Write Inhibited

Block Clear

...r

"l.J

HighZ

READ STATUS REGISTER

DATA FETCH

Mode

z
3:
oco

Once the erase/write operation has been initiated, the
NMC9802 doesn't allow access to address pointer, data input register or data output drivers.

DEVICE OPERATION

DON'T CARE

- " ~ POSITIVE TRANSITION
LJ~

NEGATIVE PULSE

II
I

1-37

o
~

o
::::IE
z

,--------------------------------------------------------------------------------,
Ordering Information
Order
Number

Select
Access
Time

Cycle
Time
(Min)

Supply
Current
(Max)

Package
Type

NMC9802J
NMC9802N

120 ns
120 ns

350
350

70 mA
70mA

Cerdip
Plastic

1-38

PRELIMINARY

~National

oCD

co
.....

~ Semiconductor
NMC9816A 16,384-Bit(2k x 8) E2PROM

General Description
An optional high voltage chip erase feature is provided for
quick erasure of the memory data pattern in a single 9 msec
Chip Erase Cycle.
The density, and level of integrated control, make the
NMC9816A suitable for users requiring minimum hardware
overhead, high systems performance, minimal board space
and design ease. Designing with and using the NMC9816A
is extremely cost effective as the required high voltage and
interfacing hardware required for other E2PROM devices
has been eliminated by 5V-only operation and on-chip latches. See Figures 1, 2, and 3 for the NMC9816A block diagram, pinout, and simple interface requirements.

The NMC9816A is a fast 5V-only E2PROM which offers
many desired features, making it ideally suited for efficiency
and ease in system design. The added features on the
NMC9816A include: 5V-only operation provided by an onchip Vpp generator during erase-write; address and data
latches to reduce part count and to free the microprocessor
while the chip is busy doing erase-write; and automatic
erase before byte-write. It can meet applications requiring
up to 104 write cycles per byte. The NMC9816A is a product
of National's advanced E2PROM stepper technology and
uses the powerful XMOSTM process for reliable, non-volatile
data storage.
The NMC9816A sharply minimizes the interfacing hardware
logic and firmware required to perform data writes. The device has complete self-timing which leaves the processor
free to perform other tasks. With an automatic erase before
write, the user benefits by saving an erase command contributing to efficient usage of system processing time. Onchip address and data latching further enhances system
performance.
The NMC9816A also features DATA Polling, which enables
the E2PROM to signal the processor that a write operation
is complete without requiring the use of any external hardware.
Improved data protection during Vee power up/down transitions is provided by an on-chip Vee sensing circuit which
disables the initiation of all 5V-only programmable modes
when Vee is less than 4 volts.
The NMC9816A's very fast read access times make it compatible with high performance microprocessor applications.
It uses the proven two line control architecture which eliminates bus contention in a system environment.

Features
•
•
•
•
•
•
•
•
•

Single 5V supply
Self-timed byte-write with auto erase
On-chip address and data latches
On-chip power up/down protection
Two iine output control
TRI-STATE® outputs
Data polling verification
High voltage chip erase
Fast byte-writing
Write cycle (2 ms typical)
E/W cycle (4 ms typical)

• Very fast access time
NMC9816A-20-200 ns
NMC9816A-25-250 ns
NMC9816A-35-350 ns
• Direct microprocessor interface capability
• No support components needed
• Reliable E2PROM XMOS stepper technology

Block and Connection Diagrams
~I
OND

GENERATOR

Dual-In-Line Package

DATA INPUTS I OUTPUTS

L-------1,.------...J
IJpp

!JiiT!tt

A7- 1

24-IJCC
23-A8

'6- 2

INPUT LATCHES

CHlP ENABLE/OUTPUT

ENABLE lOGIC

---

AUTOMATIC WRITE TIMING
AUTOMATIC ERASE LOGIC

J
AO~Al0

ADDRESS
INPUTS

....

LATCHES

I
'7
--

v
OECOOER

'-'-

x
DECODER

BUFFERS

r--

r-:-

Y GATING

Addresses
Chip Enable
Output Enable

f-'-

20 -

19 -

AID

Al- 7

18~Ci'
17~ 17/07

0 0 -0 7
10- 17

11/01-10

GNO -

TLIO/84S1-1

A3- 5

12/01 -

16.384·BIT
CELL MATRIX

.,-6
10/00 -

~--------~

FIGURE 1
Pin Names

AO-Al0
CE
OE

22 -

21-WE

AD-8

r:-

~--------~

--.-

INPUT I OUTPUT

'5- 3

A4-'

r- 16/06

lSt--15/05

r12
13 r- 13/03
'-----------'
11

Top View

14/04

TLID/8451-2

FIGURE 2
Data Outputs
Data Inputs
Write Enable

1-39

Order Number NMC9816A-20,
NMC9816A-25 or NMC9816A-35
See NS Package Number J24A or N24A

Absolute Maximum Ratings
Temperature Under Bias
NMC9816A

- 65·C to + 150·C

All Input or Output Voltages with
Respect to Ground

300·C

Operating Conditions
Temperature Range
NMC9816A

5V ±5%

NMC9816AE

5V ±10%

NMC9816AM

5V ±10%

+6Vto -0.3V

Lead Temp. (Soldering, 10 seconds)

- 55"C to + 125"C

NMC9816A

-50"Cto +95"C
-65·C to + 135·C

NMC9816AM
Storage Temperature

- 40"C to + 85"C

NMC9816AM
Vee Power Supply (Notes 2 and 3)

-10"C to + 80"C

NMC9816AE

O"Cto +70"C

DC Electrical Characteristics TA for NMC9816A =
Symbol

Parameter

O"C to + 70"C, Vee = 5V ± 5% (Note 7)

Conditions

typ
(Note 1)

Min

Max

Units

GND to Vee

10
10
10

p,A

GND to Vee

10
10
10

p,A

READ OPERATION

Input Leakage Current

III

NMC9816A
NMC9816AE
NMC9816AM

Output Leakage Current

ILO

NMC9816A
NMC9816AE
NMC9816AM

Vee Current (Active)

leeA

Vee Current (Standby)

Ices

Vil
VIH

NMC9816A
NMC9816AE
NMC9816AM

CE = OE = Vil

40
40
40

80
100
100

CE = VIH

12
12
12

25
30
30

Input Low Voltage

-0.1

0.8

Input High Voltage

2.0
2.2
2.2

Vee + 1
Vee + 1
Vee + 1

0.45

NMC9816A
NMC9816AE
NMC9816AM

Val

Output Low Voltage

IOl =2.1 mA

VOH

Output High Voltage

IOH= -400 /LA

2.4

WRITE OPERATION

Vee Current (Write)

leew

40
40
40

NMC9816A
NMC9816AE
NMC9816AM

Vee Level for Write Lockout

VlKO

80
100
100

mA
V

4.0

HIGH VOLTAGE CHIP ERASE

VER

OE and WE Voltage in Chip Erase Mode

Capacitance TA=.25"C, f= 1 MHz (Note 1)
Symbol

Parameter

Conditions

CIN

Input Capacitance

VIN=OV

Cour

Output Capacitance

Vour=OV

1-40

Min

Typ
(Note 1)

Max

Units

AC Test Conditions
Timing Measurement Reference Level

1 TTL gate and Cl = 100 pF

Output Load

0.45V to 2.4V

Input Pulse Levels

1V and2V

Input

0.8V and 2V

Output

Read Mode AC Electrical Characteristics TA=O'Ct070'C, Vcc=5V ±5% (Notes 2, 3 & 7)
Parameter

Symbol

Conditions

NMC9816A-20

NMC9816A-25

Typ
(Note 1)

Max

Typ
(Note 1)

Max

Min

NMC9816A-35
Min

Typ
(Note 1)

Max

Units

tACC

Address to Output
Delay

CE=OE=Vll

150

200

250

300

350

tCE

CE to Output Delay

OE=Vll

150

200

250

300

350

tOE

Output Enable to
Output Delay

CE=Vll

100

120

tOF

Output Disable
to Output Float

CE or OE=Vll

100

tOH

Output Hold from
Addresses, CE or OE
Whichever Occurred
First

CE,OE=Vll

Write Mode AC Electrical Characteristics TA = O'C to 70'C, VCC = 5V ± 5% (Notes 2, 3 & 7)
Symbol

Conditions

Parameter

Typ
(Note 1)

Min

Max

Units

tAS

Address to Write Set-Up Time

tcs

CE to Write Set-Up Time

twp (Note 6)

Write Pulse Width

150

tAH

Address Hold Time

tos

Data Set-Up Time

OE=VIH

tOH

Data Hold Time

OE=VIH

tcH

CE Hold Time

tOl

Data Latch Time

twc

Byte-Write Cycle Time

tOES

Output Enable Setup Time

toEH

Output Enable Hold Time

ns
4

High Voltage Chip Erase AC Electrical Characteristics (Note 5)
T A = O°C to

+ 70°C, Vcc

Symbol

= 5V ± 5% (Notes 2, 3 & 7)
Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

tcs

CE Set-Up Time

WE = 6V

tos

Output Enable Set-Up Time

WE = 6V

tOH

Output Enable Hold Time

WE = 6V

",s

tWR

Write Recovery Time

WE= 6V

twp

Chip Erase Pulse Width

WE = VER

",s
15

Note 1: This parameter only sampled and not 100% tested.
Note 2: To prevent spurious device erase or write, WE or CE=VIH m~st be applied simultaneously or before'Vcc
simultaneously or after Vee falls before 4V.
Note 3: To prevent damage

4V. WE or CE=VIH must be removed

to the device it must not be inserted into or removed from a board with power applied.

Note 4: tOF is specified from DE or

CE,

whichever occurs first

Note 5: Low voltage Vee sense circuit does not inhibit the high voltage Chip Erase feature.
Note 6:

WE is noise protected.

Nole7:TAforNMC9816AE

Less than a 20 ns write pulse will not activate a write cycle.

-40'Cto +85'C, Vee

5V ±10%,TAforNMC9816AM ~ -55'Cto +125'C,Vee ~ 5V ±10%.

1-41

....

,--------------------------------------------------------------------,
Switching Time Waveforms
Read

:IE
:z;
ADDRESSES

-------'~

-----------------------~ r - - - - ADDRESSES VALID

------n-------JJ '------

-tACC

tOF

(NOTE 4)

VALID
OUTPUT

OUTPUT ---------t~

TL/D/8451-3

Write

ADDRESSES _ _..I

DIN

--------t-C:!~)---~

S-------

OE-----.1
TLlD/8451-4

Chip Erase Cycle

,.-~s

S-S- - - - -

'WR{
1-----§
VERL""-r-----r-__
VIH
OE _ _ _ _....;;,J
'---~
+-'OH ..
+-'OS ..
DATA IN

= OON'T

CARE

S-S- - - - -

SS-----TL/D/8451-6

1-42

3!:

Device Operation
DATA PROTECTION ON Vee POWER UP AND POWER
DOWN

The NMC9816A has 6 modes of user operation which are
detailed in Table I. All modes are designed to enhance the
NMC9816A's functionality to the user and provide total microprocessor compatibility.
TABLE I. Vee
Pin
Mode

10/00-17/07

Read

VIL

VIH

Dour

Standby

VIH

Hi-Z

Write

VIL

VIH

l..f"

DIN

VIH

High-Z

Busy

VIH

Data Polling

VIL

Chip Erase

VIL

VER VER

An eraselwrite of a byte in the NMC9816A is accomplished
with input signals CE, WE = VIL. During system (Vecl power up and power down, this condition may be present as
Vee ramps up to or down from its steady state value of 5V.
To prevent the possibility of an inadvertant byte write during
this power transition period, an on-chip sensing circuit disables the internal programming circuit if Vee falls below 4V
(VLKO).
OPTIONAL HIGH VOLTAGE CHIP ERASE CYCLE
All data can be changed to "1" or erase state in one 10 ms
cycle by raising OE to 12-22V and bringing WE to 12-22V
for twp msec.

High-Z

17107

READ MODE
One aspect of the NMC9816A's high performance is its very
fast read access time-typically less than 200 ns. Its read
cycle is similar to that of EPROMS and static RAMs. It offers
a two line control architecture to eliminate bus contention.
The NMC9816A can be selected using decoded system address lines to CE and then the device can be read, within
the device selection time, using the processor's RD Signal
connected to OE.

DIN

-t~'I~ roo- 5 Vee

FROM DECODER - - :
I

FROM RD

I
I
I

STANDBY MODE

---+
I
I
I

FROt4

ViR

I
I
I
I
I

AD-Al0

...

I
I
I

10/00 -17/°7 '"

I
I
I

~ WE

,..

II.

...,..

The NMC9816A has a standby mode in which power consumption is reduced by 70%. This offers the user power
supply cost benefits when designing a system with
NMC9816A's. This mode occurs when the device is deselected (CE = VIH). The data pins are put into the high impedance state regardless of the signals applied to OE and WE
concurrent with the reading and writing of other devices.

OE
NMC98l6A
E2 PROM

AO-Al0

ID/OD-17/~

SYSTEM IMPLEMENTATION AND APPLICATION

GND

The NMC9816A is compatible with industry standard microprocessors. It requires no interface circuitry and no support
circuitry.

The NMC9816A is ideal for non-volatile memory requirements in applications requiring storage of user defined functions, calibration constants, configuration parameters and
accumulated totals. Soft key configuration in a graphics terminal is an example where user defined functions, such as
protocol, color, margins and character fonts can be keyed in
by the user. Calibration constants could be stored by the
NMC9816A in the smart interface for a robot's axis of movement. Movement constants, compensation algorithms and
learned axis characteristics can be stored. In programmable
controllers and data loggers, configuration parameters for
polling time, sequence and location, could be stored in the
NMC9816A. Accumulated totals for dollars, energy consumption, volume and even the logging of service done on
computer boards or systems can be stored in the
NMC9816A.

S'tSTEt4
I NMC98l6A
REQUIREMENTS • REQUIREt4ENTS
TL/D/8451-5

FIGURE 3. Simple NMC9816A Interface Requirements
WRITE MODE
The NMC9816A is programmed electrically in-circuit, yet it
provides the non:volatility usually obtained by optical erasure in EPROMS and by batteries with CMOS RAM. Writing
to non-volatile memory has never been easier as no high
voltage, external latching, erasing or timing is needed.
When commanded to byte-write, the NMC9816A automatically latches the address, data, and control signals and
starts the write cycle. During the write cycle Vpp is generated on-chip to perform an automatic byte-erase, then write.

The NMC9816A is cost effective for lower density E2PROM
applications and can therefore be used to provide a lower
system cost to the user compared to the 2816 or 2817. The
user will find that tangible cost savings per system include:
board space and component reductions, reduced assembly
costs; savings in inventory costs, handling costs and quality
assurance. The designer will find the NMC9816A reduces
design time by a sizable factor over the 2816 or 2817 due to
the integration of timing, logic, latching and 5V-only operation.

DATA POLLING
The NMC9816A features DATA Polling to signal the completion of a byte write cycle. During a write cycle, an attempted read of the last byte written results in the data complement of that byte at 1107. After completion of the write
cycle, true data is available. DATA Polling allows a simple
readl compare operation to determine the status of the chip
eliminating the need for external hardware.

1-43

o
CD
(1)
.....
en

:J>

Device Operation

(Continued)
The NMC9816A's internal cycle consists of an automatic
2 ms (typical) erase followed by a 2 ms (typical) write. The
total cycle is then typically 4 ms. The NMC9816A maximum
specification is 10 ms.

The NMC9816A will also open up new applications in environments where flexible parameter/data storage could not
be implemented before. For example, applications with
board space constraints are ideal for the NMC9816A. Several NMC9816A's can reside in the same space as one (1)
2816 with its support circuits. This is due to the reduction 01
all components required including the Vpp generator.

WRITE PROTECTION

There are three features that protect the nonvolatile data
from an inadvertant write.

WRITE TIME CHARACTERISTICS

• Noise Protection - A WE pulse of less than 20 ns will not
initiate a write cycle.

The NMC9816A's internal write cycle contains an automatic
erase feature. The 2816 does not have this capability and
must be given an external erase cycle prior to a write. The
2816 has a write time specification of 9 ms. Typically, these
devices will write in times less than 9 ms, but the worst-case
bit defines the minimum specification.

• Vee Sense - When Vee is below approximately 4V all
5V-only write functions are inhibited.
• Write Inhibit - Holding OE low, WE high, or CE high, inhibits a write cycle during power-on and power-off (Ved.

1-44

~National

PRELIMINARY

oCD

........

~ Semiconductor
NMC9817 16,384-Bit (2k x 8) E2PROM
General Description
The NMC9817 is a fast 5V-only E2PROM which offers many
desired features, making it ideally suited for efficiency and
ease in system design. The added features on the
NMC9817 include: 5V-only operation provided by an on-chip
Vpp generator during erase-write; address and data latches
to reduce part count and to free the microprocessor while
the chip is busy during erase-write; 'Ready' line indicator to
indicate status of chip to the microprocessor; and automatic
erase before byte-write. It can meet applications requiring
up to 104 write cycles per byte. The NMC9817 is a product
of National's advanced E2PROM stepper technology and
uses the powerful XMOSTM process for reliable, non-volatile
data storage.
The NMC9817 sharply minimizes the interfaCing hardware
logic and firmware required to perform data writes. The device has complete self-timing which leaves the processor
free to perform other tasks until the NMC9817 signals
'ready'. With an automatic erase before write, the user benefits by saving an erase command contributing to efficient
usage of system processing time. On-chip address and data
latching further enhances system performance.
The NMC9817's very fast read access times make it compatible with high performance microprocessor applications.
It uses the proven two line control architecture which eliminates bus contention in a system environment. Combining
these features with the NMC9817's open-drain 'Ready' signal makes the device an extremely powerful, yet simple to
use, E2PROM memory.

The density, and level of integrated control, make the
NMC9817 suitable for users requiring minimum hardware
overhead, high system performance, minimal board space
and design ease. Designing with and using the NMC9817 is
extremely cost effective as the required high voltage and
interfacing hardware required for other E2PROM devices
has been eliminated by 5V-only operation and on-chip latches. See Figures 1,2 and 3 for the NMC9817 block diagram,
pinout, and simple interface requirements.

Features
•
•
•
•
•
•
•
•

•

•
•
•

Single 5V supply (eliminates an external 21V Vpp)
Self-timed byte-write with auto erase
No external capacitor or pulse shaping circuits
On-chip address and data latches
Two line output control
TRI-STATE® outputs
RDY pin indicator
Fast byte-writing
Write cycle (2 ms typical)
E/W cycle (4 ms typical)
Very fast access times
NMC9817-20-200 ns
NMC9817-25-250 ns
NMC9817-35-350 ns
Direct microprocessor interface capability
No support components needed
Reliable E2PROM XMOS stepper technology

Block and Connection Diagrams
Vpp GENERATOR
~
GND~------------~------------~

Dual·ln·Line Package
DATA INPUTS/OUTPUTS
10/00-17/07

CHIP ENABLE/OUTPUT
ENABLE LOGIC
AUTOMATIC WRITE TIMING

ROV/BUSY

INPUT /DUTPUT
BUFFERS

AUTOMATIC ERASE LOGIC

ROYI

fiITSY

VCC

'WE

lIE

NMt9817

E'PROM

Al0

17/07

10/00

16/06

1,/0,

15/05

1,/0,

A2
AO-A1D
ADDRESS
INPUTS

DECODER

V GATING

Al
AD

LATCHES
X
DECODER

16.384·BIT
CELL MATRIX

TL/D/S04l-l

FIGURE 1

GND

Pin Names

AO-A10 Addresses
10-17
Data Inputs
CE
Chip Enable
RDY /BUSY Device Ready/Busy (Open-Drain Output)
OE
Output Enable NC
No Connect
00-07 Data Outputs

1-45

14-_ _ _ _.--J
15
L
TL/D/S041-2

Top View

FIGURE 2
Order Number NMC9817J·20,
NMC9817J·25 or NMC9817·35
See NS Package Number J28A

......
.....
co
CJ)

o
:::!!E
z

Absolute Maximum Ratings

Operating Conditions

Temperature Under Bias

Temperature Range

-10'Cto +SO'C

Storage Temperature

- 65'C to + 125'C

All Input or Output Voltages with

O'C to +70'C
5V ±5%

Vee Power Supply (Notes 2 and 3)

+6Vto -0.3V

Respect to Ground
Lead Temp. (Soldering, 10 seconds)

300'C

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DC Electrical Characteristics TA=O'Cto 70'C, Vee=5V
Symbol

Parameter

Conditions

±5% (Notes2and3)
Typ
(Note 1)

Min

Max

Units

iJ-A

READ OPERATION
III

Input Leakage Current

VIN=5.25V

ILO

Output Leakage Current

VOUT=5.25V

iJ-A

leeA

Vee Current (Active)

OE=CE=VIL

CE=VIH

Ices

Vee Current (Standby)

VIL

Input Low Voltage

-0.1

O.S

VIH

Input High Voltage

2.0

Vee+ 1

VOL

Output Low Voltage

IOL =2.1 mA

0.45

VOH

Output High Voltage

IOH= -400 iJ-A

2.4

WRITE OPERATION
leew

Vee Current (Write)

RDY/SUSY=VOL

Capacitance TA=25'C, f= 1 MHz (Note 1)
Symbol

Parameter

Conditions

CIN

Input Capacitance

VIN=OV

COUT

Output Capacitance

VOUT=OV

Min

Typ
(Note 1)

Max

Units

AC Test Conditions
Output Load
Input Pulse Levels

Timing Measurement Reference Level

1 TTL gate and CL = 100 pF
0.45V to 2.4V

Input
Output

1-46

1V and 2V
O.SV and 2V

Read Mode AC Electrical Characteristics TA = O'C to 70'C, Vcc= 5V ± 5% (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

NMC9817-20

NMC9817-25

Typ
(Note 1)

Max

Typ
(Note 1)

Max

Min

NMC9817-35
Min

Typ
(Note 1)

Max

Units

tACC

Address to Output
Delay

CE=OE=VIL

150

200

250

300

350

teE

CE to Output Delay

OE=VIL

150

200

250

300

350

tOE

Output Enable to
Output Delay

CE=VIL

100

120

tOF

Output Disable
to Output Float

CEorOE=VIL

100

toH

Output Hold from
Addresses, CE or OE
Whichever Occurred
First

CE,OE=VIL

z
o
CD
CD
......

!!:

.....

Write Mode AC Electrical Characteristics TA=O'Ct070'C, Vcc=5V ±5% (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

tAS

Address to Write Set-Up Time

tes

CE to Write Set-Up Time (Note 5)

\wp

Write Pulse Width

100

tAH

Address Hold Time

tos

Data Set-Up Time

OE=VIH

tOH

Data Hold Time

OE=VIH

teH

CE Hold Time

tos

Time to Device Busy

tWR

Byte-Write Cycle Time

120

Note 1: This parameter only sampled and not 100% tested.
Note 2: To prevent spurious device erase or write,
simultaneously or after Vee.

WE or CE = V,H must be applied simultaneously or before application of Vee. WE or CE = V,H must be removed

Note 3: To prevent damage to the device it must not be inserted into or removed from a board with power applied.
Note 4: tOF is specified from DE or CE, whichever occurs first.
Note 5: Tcs

= 35 ns on

- 25 and - 35 devices.

Switching Time Waveforms
Read
ADDRESSES

)

ADDRESSES VALID

----

tob
OUTPUT

r--

If!Jf!!}
~

II
to,

(NOTE 4)

VALID
OUTPUT
TLlD/5041-3

1-47

Switching Time Waveforms

(Continued)
Write

ADDRESSES

DIN-----------(~~~~--------ROY/BUSY

TLIO/5041-4

Device Operation
The NMC9817 has 4 modes of user operation which are
detailed in Table 1. All modes are designed to enhance the
NMC9817's functionality to the user and provide total microprocessor compatibility.

TABLE I. Vee

WRITE MOOE
The NMC9817 is programmed electrically in-circuit, yet it
provides the non-volatility usually obtained by optical erasure in EPROMS and by batteries with CMOS RAM. Writing
to non-volatile memory has never been easier as no high
voltage, external latching, erasing or timing is needed.
When commanded to by1e-write, the NMC9817 automatically latches the address, data, and control signals and starts
the write cycle. Concurrently, the 'Ready' line goes low, indicating that the NMC9817 is busy and that it can be deselected to allow the processor to perform other tasks. The
Ready IBusy signal is an open-drain output. During the write,
a high Vpp is generated on-chip to perform an automatic
by1e-erase, then write.
As a precaution against spurious Signals which may cause
an inadvertant write cycle, or interfere with a valid signal, it
is recommended that a pullup resistor be used on the WE
pin, pin 27 (see Figure 4).

Pin
Mode

10/00-17/07

ROYIBUSY

Read

VIL

VIH

DOUT

Hi-Z
Hi-Z

Standby

VIH

Hi-Z

Write

VIL

VIH

DIN

VOL

Busy

Hi-Z

VOL

FROM DECODER

•

---+1 IT

FROMRD---+I iiE

Vee

5 Voc

NMC9817
E'PROM

FROM Wii - - - + 1 WE
TO INTERRUPT

+----i ROY IBUSY

AO-A10 _ _ _"AO-A10

10/00-17/07 •

•

10/00-17/07

GNO

-+--

SYSTEM
REQUIREMENTS

NMC9B17
REQUIREMENTS

TL/D/S041-5

FIGURE 3. Simple NMC9817 Interface Requirements

1-48

Device Operation

s::
o

(Continued)

OCI
.....
.....

Vee

R=4K TO 10 K!!

NMC9817

TL/D/5041-6

FIGURE 4. Pullup R on WE

READ MODE
One aspect of the NMC9817's high performance is its very
fast read access time-typically less than 200 ns. Its read
cycle is similar to that of EPROMS and static RAMs. It offers
a two line control architecture to eliminate bus contention.
The NMC9817 can be selected using decoded system address lines to CE and then the device can be read, within
the device selection time, using the processor's AD signal
connected to OE.
STANDBY MODE

The NMC9817 has a standby mode in which power consumption is reduced by 70%. This offers the user power
supply cost benefits when designing a system with
NMC9817s. This mode occurs when the device is deselected (CE = VIH). The data pins are put into the high impedance state regardless of the signals applied to OE and WE
concurrent with the reading and writing of other devices.
SYSTEM IMPLEMENTATION ANP APPLICATION

The NMC9817 is compatible with industry standard microprocessors. It requires no interface circuitry and no support
circuitry.
The NMC9817 is ideal for non-volatile memory requirements in applications requiring storage of user defined functions, calibration constants, configuration parameters and
accumulated tot<\ls. Soft key configuration in a graphics terminal is an eXample where user defined functions, such as
protocol, color, margins and character fonts can be keyed in
by the user. Calipration constants could be stored by the
NMC9817 in the smart interf<\ce for a robot's axis of movement. Movement constants, compensation algorithms and
learned axis characteristics can be stored. In programmable
controllers and data loggers, configuration parameters for

polling time, sequence and location, could be stored in the
NMC9817. Accumulated totals for dollars, energy consumption, volume and even the logging of service done on computer boards or systems can be stored in the NMC9817.
The NMC9817 is cost effective for lower density E2PROM
applications and can therefore be used to provide a lower
system cost to the user compared to the 2816 or 2817. The
user will find that tangible cost savings per system include:
board space and component reductions, reduced assembly
costs, savings in inventory costs, handling costs and quality
assurance. The designer will find the NMC9817 reduces design time by <\ sizable factor over the 2816 or 2817 due to
the integration of timing, logic, latching and 5V-only operation.
The NMC9817 will also open up new applications in environments where flexible parameter/data storage could not
be implemented before. For example, applications with
board space constraints are ideal for the NMC9817. Several
NMC9817s can reside in the same space as one (1) 2816
with its support circuits. This is due to the reduction of all
components required including the Vpp generator.
WRITE TIME CHARACTERISTICS

The NMC9817's internal write cycle contains an automatic
erase feature. The 2816 does not have this capability and
must be given an external erase cycle prior to a write. Typically, these devices will write in times less than 9 ms, but the
worst-case bit defines the minimum specification.
The NMC9817's internal cycle consists of an automatic
2 ms (typical) erase followed by a 2 ms (typical) write. The
total cycle is then typically 4 ms. This cycle is the time that
'Ready' is held low by the device. The NMC9817 maximum
specification is 10 ms.

1-49

--------

RDY /BUSY

TL/D/8370-4

Chip Erase Cycle

·'CS - r-'WP---1 ·'WR-

6V rVER

1-+'05OE

VIN

VER

"' ·'OH'\
TL/D/8370-6

Data In

Don't Care

1-53

Device Operation
The NMC9817A has 6 modes of user operation which are
detailed in Table I. All modes are designed to enhance the
NMC9817A's functionality to the user and provide total microprocessor compatibility.
TABLE I. Vee
Pin
Mode

WRITE MODE

The NMC9817A is programmed electrically in-circuit, yet it
provides the non-volatility usually obtained by optical erasure in EPROMs and by batteries with CMOS RAM. Writing
to non-volatile memory has never been easier as no high
voltage, external latching, erasing or timing is needed.
When commanded to byte-write, the NMC9817A automatically latches the address, data, and control signals and
starts the write cycle. Concurrently, the 'Ready' line goes
low, indicating that the NMC9817A is busy and that it can be
deselected to allow the processor to perform other tasks.
The Ready/Busy signal is an open-drain output. During the
write, cycle Vpp is generated on-chip to perform an automatic byte-erase, then write.

10/00'" 17107

ROYIBUSY

Hi-Z

Read

VIL

VIH

DOUT

Standby

VIH

Hi-Z

Write

VIL

VIH

DIN

VOL

Busy

VIH

Hi-Z

VOL

VIH

Hi-Z

VOL

Data
Polling

VIL

17/07= DIN

VOL

Chip
Erase

VIL

VER

VOL

r----v--

I • IT
Vcc t-- 5 VDC
I
FROM iiii
• OE
NMC9817A
E'PROM
I
FROM Wii
WE
•
I RDYIBmV
TO INTERRUPT
I .... AD-A1D
AO-A1O
I 10 100-17107
10 100-17 107 4
GND
~
I
~
I NMC98l7A
SYSTEM

FROM DECODER

REQUIREMENTS

TLID18370-5

FIGURE 3. Simple NMC9817A Interface Requirements

1-54

,-------------------------------------------------------------------------, z
s::
Device Operation (Continued)
NMC9817As. This mode occurs when the device is deselected (CE = VIH). The data pins are put into the high impedance state regardless of the signals applied to OE and
WE concurrent with the reading and writing of other devices.

DATA POLLING

The NMC9817A also features DATA Polling to signal the
completion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the data
complement of that byte at 1/07' After completion of the
write cycle, true data is available. DATA Polling allows a
simple read/compare operation to determine the status of
the chip eliminating the need for external hardware.

SYSTEM IMPLEMENTATION AND APPLICATION

The NMC9817A is compatible with industry standard microprocessors. It requires no interface circuitry and no support
circuitry.
The NMC9817A is ideal for non-volatile memory requirements in applications requiring storage of user defined functions. calibration constants, configuration parameters and
accumulated totals. Soft key configuration in a graphics terminal is an example where user defined functions, such as
protocol, color, margins and character fonts can be keyed in
by the user. Calibration constants could be stored by the
NMC9817 A in the smart interface for a robot's axis of movement. Movement constants, compensation algorithms and
learned axis characteristics can be stored. In programmable
controllers and data loggers, configuration parameters for
polling time, sequence and location, could be stored in the
NMC9817A. Accumulated totals for dollars, energy consumption, volume and even the logging of service done on
computer boards or systems can be stored in the
NMC9817A.

ON-CHIP DATA PROTECTION ON Vee
POWER UP AND POWER DOWN

An erase/write of a byte in the NMC9817A is accomplished
with input signals CE, WE = VIL. During system (Vecl power up and power down, this condition may be present as
Vee ramps up to or down from its steady state value of 5
volts. To prevent the possibility of an inadvertent by1e write
during this power transition period, an on-Chip sensing circuit disables the internal programming circuit if Vee falls
below 4 volts (VLKO).
WRITE TIME CHARACTERISTICS

The NMC9817A's internal write cycle contains an automatic
erase feature. The 2816 does not have this capability and
must be given an external erase cycle prior to a write. The
2816 has a write time specification of 9 ms. Typically, these
devices will write in times less than 9 ms, but the worst-case
bit defines the minimum specification.

The NMC9817A is cost effective for lower density E2PROM
applications and can therefore be used to provide a lower
system cost to the user compared to the 2816 or 2817. The
user will find that tangible cost savings per systern inClude:
board space and component reductions, reduced assembly
costs, savings in inventory costs, handling costs and quality
assurance. The designer will find the NMC9817A reduces
design time by a Sizable factor over the 2816 or 2817 due to
the integration of timing, logic, latching and 5V-only operation.

The NMC9817A's internal cycle consists of an automatic 2
ms (typical) erase followed by a 2 ms (typical) write. The
total cycle is then typically 4 ms. This cycle is the time that
'Ready' is held low by the device. The NMC9817A maximum specification is 10 ms.
WRITE PROTECTION

There are three features that protect the nonvolatile data
from an inadvertent write.

The NMC9817A will also open up new applications in environments where flexible parameter/data storage could not
be implemented before. For example, applications with
board space constraints are ideal for the NMC9817A. Several NMC9817As can reside in the same space as one (1)
2816 with its support circuits. This is due to the reduction of
all components required including the Vpp generator.

• Noise Protection-A WE pulse of less than 20 ns will not
initiate a write cycle.
• Vee Sense-When Vee is below approximately 4 volts
all 5V-only write functions are inhibited.
• Write Inhibit-Holding OE low, WE high, or CE high, inhibits a write cycle during power-on and power-off (Vecl.

The NMC9817A's very fast read access times make it compatible with high performance microprocessor applications.
It uses proven two line control architecture which eliminates
bus contention in a system environment. Combining these
features with the NMC9817A's open-drain 'Ready' Signal
makes the device an extremely powerful, yet simple to use,
E2PROM memory.

OPTIONAL HIGH VOLTAGE CHIP ERASE CYCLE

All data can be changed to "1" or erase state in one 10 ms
cycle by raising OE to 12-22V and bringing WE to 12-22V for
twp msec.
READ MODE
One aspect of the NMC9817A's high performance is its very
fast read access time-typically less than 200 ns. Its read
cycle is Similar to that of EPROMs and static RAMs. It offers
a two line control architecture to eliminate bus contention.
The NMC9817A can be selected using decoded system address lines to CE and then the device can be read, within
the device selection time, using the processor's RD signal
connected to OE.

The denSity, and level of integrated control, make the
NMC9817A suitable for users requiring minimum hardware
overhead, high system performance, minimal board space
and design ease. An optional high voltage chip erase feature is provided for quick erasure of the memory data pattern in a single 9 msec Chip Erase cycle. Designing with and
using the NMC9817A is extremely cost effective as the required high voltage and interfaCing hardware required for
other E2PROM devices has been eliminated by 5V-only operation and on-chip latches.

STANDBY MODE

The NMC9817A has a standby mode in which power consumption is reduced by 70%. This offers the user power
supply cost benefits when designing a system with

1-55

oCD

CIO
......

......

,------------------------------------------------------------------------------------,

oco
~National
o
0)

:!E

PRELIMINARY

~ Semiconductor

microCMOS

NMC98C64
8k x 8 CMOS Electrically Erasable PROM
General Description

Features

The NMC98C64 is a 5V only CMOS E2PROM with desirable
ease of use features that facilitate in-circuit programming
using a single suppy and TIL level signals. In addition, the
NMC98C64 is compatible with present high density
EPROMs which require high voltage programming and UV
erasing. The NMC98C64 is a state-of-the-art product that
uses the advanced microCMOS stepper based technology.
The process is an enhancement of the proven XMOSTM
process for reliable, non-volatile data storage.
Writing data in NMC98C64 is analagous to writing to a
SRAM. A 200 ns min TTL pulse to the WE pin initiates a
byte write operation which is automatically timed out. Address and data latches free the system bus for the duration
of the write. Ready/Busy facilitates service by providing an
interrupt to the controller; an open drain output facilitates
"wire or" connection in larger systems.
A 32-byte page write allows data to be accepted at an effective rate of 300 Its/ page or 2.6 seconds to write an entire
chip.

• Single 5-V power supply
• Low CMOS power
- Active, 10 mA typical
- Standby, 100 itA typical
- Quiescent, 100 itA typical
• Simple byte write and page write
- On-chip address and data latches
- Self-timed cycle, auto erase before write
- Page write up to 32 bytes per page
- Ready/Busy open drain status output and DATA
polling verification
- Write protection
• Fast write time
- Byte or page write, 10 ms max
- Entire chip write in 2.6 seconds
- Page data load, 300 its typical
• Fast access time: 200 ns/250 ns/350 ns
• CMOS and TIL compatible level inputs/outputs

Block and Connection Diagrams
liD,
GNO 0---+

1100

1103
liD,

liD,
liD,

Vpp GENERATOR

CONTROL LOGIC

Ao
A,
A,
A3
A,

A,
As

A,
As
A,
A,o
A"
An

~
~

COLUMN
ADDRESS
BUFFERS

ROW
ADDRESS
BUFFERS

Y DECODERS

8Kx8
E'PROM
ARRAY

REAOYIBSY

28 Vee

All

27 WE

26 NC

25 As

24 As

23 Au

21 Am

8K x8

20 CE

Ao 10

19 1107

1/00 11

18 110,

liD, 12

17 110,

liD, 13

16 I/o,

Vss 14

15 liD,
TLlD17514-1

Order Number NMC98C64
See NS Package J28A
AO-A4

Column Addresses

A5- A '2

Row Addresses

1100- 1/ 0 7
TL/0/7514-2

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

ROY/BUSY
NC

1-56

22 DE
NMC98CB4

Device Ready/Busy
No Connect

1=;,=--

TABLE I. Operation Modes (Vee = 5V

I:,
I"

s::

10%)

1/00-1/07

RDYIBUSY

Power

Read

VIL

VIH

DOUT

High Z

ActivelQuiescent

00)

Write Single Byte or
1st Byte in a Page

VIL

VIH

DIN

High Z ..... Vol

Write

"'"

Write Subsequent Bytes
in a Page

VIL

DIN

Vol

Write

Busy

VIH
X

X
VIH

X
X

Hi-Z
Hi-Z

Vol
Vol

Write
Write

DATA Polling

VIL

VIH

1/07 = DIN

VoI/Hi-Z

Standby

VIH

High Z

Standby

X
X

VIL
X

X
VIH

HighZ
High Z

Write Inhibit

()C)

!',l'

Device Operation
The NMC98C64 is organized as 256 rows of 32 bytes
(256 x 32 x 8). Address inputs A5 through A 12 are decoded to select one of the 256 rows (pages) of storage locations. AO through A4 are decoded to select one of the 32
bytes within the selected row. The device has various
modes of user operation (detailed in Table I). All input/output levels are TTL compatible. "X" denotes don't care situ ation to TTL levels.

the NMC98C64 has completed writing, and is ready to accept another cycle.
• DATA Polling - The NMC98C64 features DATA Polling
to signal the completion of a byte or page write cycle.
During a write cycle, an attempted read of the last byte
written results in the data complement of that byte at
1/07. After completion of the write cycle, true data is
available. DATA Polling allows a simple read/compare
operation to determine the status of the chip eliminating
the need for external hardware.

READ MODE
The read cycle of the NMC98C64 is similar to that of an
EPROM or a static RAM. A low CE and a low OE enable the
output buffers. The Ready/Busy pin is at high impedance
state during the read cycle.

STANDBY MODE
A device is disabled by bringing CE high. The power dissipation is reduced to Ices if it is disabled between operations.
Writing to the memory in the standby mode is inhibited.

WRITE MODE
Writing data to the NMC98C64 is similar to writing to a static
RAM. There are two ways to load data into data latches of
the device in a write cycle, which once initiated will automatically continue to the completion in 10 ms.

WRITE INHIBIT MODE

A byte write is accomplished by applying to the device a
data load cycle in which a low going pulse to WE with CE
low and OE high is required. The data presented at I/O pins
are written into the location selected by a byte address.
A page write allows a page of data to be written into
E2PROM in a single write cycle. Instead of one data load
cycle, up to 32 (page size) data load cycles can be applied
to the device in 300 ,...s after the first data load cycle. The
address (A5-A 12), which is presented to address pins before the first WE pulse going low, is latched in the device
and used as the page address for the rest of the cycle. The
byte addresses (AO-A4) may be put in any order providing
they are on the same page. Through page writes the entire
memory can be written (or rewritten) in 2.6 seconds.

There are three features that protect the non-volatile data
from an inadvertent write:

Holding OE low or WE high always inhibits a write cycle.
WRITE PROTECTION

• Noise Protection - A WE pulse of less than 20 ns will
not initiate a write cycle.
• Write Inhibit - Holding CE high, OE low or WE high inhibits a write during the time when Vee supply is being
powered up/down,
• Optional Vee Sense - To avoid the initiation of a write
cycle during Vee power up and power down, a write cycle is locked out for Vee less than 3.8 volts. It is the
user's responsibility to insure that the control levels are
logically correct when Vee is above 3.8 volts.
To prevent spurious device erase or write, WE or CE =VIH
must be applied simultaneously or before application of
Vee. WE or CE = VIH must be removed simultaneously or
after Vee.
To prevent damage to the device it must not be inserted into
or removed from a board with power applied.

The data load cycle can be finished by bringing CE or WE
high and keeping that through the rest of the data load time.
The row address (page address) is latched internally aiter
first data load cycle.
The WRITE mode status can be interrogated in two ways:

ENDURANCE
National Semiconductor E2PROM devices are designed for
applications requiring up to 10,000 Erase/Write cycles per
byte.

• Ready/Busy - The Ready/Busy pin (pin 1) goes to a
logic low level indicating that the NMC98C64 is in a write
cycle. When Ready/Busy goes back to high impedance

1-57

-=t
CD

oco
en
o

z==

Absolute Maximum Ratings

Operating Conditions

Temperature Under Bias

Temperature Range

-1Q°C to + 80°C

Storage Temperature

- 65°C to + 125°C

All Input or Output Voltages with

O°Cto +70°C

Vee Power Supply (Notes 2 and 3)

± 10%

+6Vto -0.3V

Respect to Ground
Lead Temp. (Soldering, 10 Seconds)

300°C

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the'
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

DC Electrical Characteristics
Symbol

Parameter

= O°C to 70°C, Vee = 5V ± 10%
Conditions

Typ
(Note 1)

Min

Max

Units

Il-A

20 + 5/MHz

0.2 + 5/MHz

READ OPERATION
III
ILO

VIN

Output Leakage Current

VOUT = Vss to Vee
CE = VIH

TTL
leeA
CMOS

= Vss to Vee

Input Leakage Current

Vee Current Active
(Operating)

Inputs toggling with
VIH & VIL levels, 110's

= Open

Inputs toggling with CMOS levels
(Vee - 0.2V; Vss + 0.2V), 110's

= Open

= VIH

CMOS

;0,

200

Il-A

TTL

OE = CE = VIL, WE = VIH
Ao-A12 = VIL or VIH, 110's = Open

OE = CE :s; Vss + 0.2V, WE ;0, Vee - 0.2V
110's = Open, Ao-A12 = Vss + 0.2V or Vee - 0.2V

200

Il-A

TTL

lees

Vee Current Standby

Vee Current Quiescent

leeQ
CMOS

Vee - 0.2V

100

VIL

Input Low Voltage

-0.1

0.8

VIH

Input High Voltage

2.0

Vee + 1

0.4

0.2

TTL

Output Low Voltage

IOL

= 2.1 mA

CMOS

Output Low Voltage

IOL

= 10 Il-A

TTL

Output High Voltage

IOH

= -400 Il-A

CMOS

Output High Voltage

IOH

= -10 Il-A

VOL

VOH

2.4

Vee - 0.2

WRITE OPERATION
leew

Vee Current (Write)

Capacitance T A =
Symbol
CIN
COUT

RDY/Busy

= VOL

25°C, f = 1 MHz (Note 1)

Parameter
Input Capacitance
Output Capacitance

Conditions
VIN = OV
VOUT

= OV

1-58

Min

Typ
(Note 1)

Max

Units

s:::

oCD
CO
oen

AC Test Conditions
1 TTL gate and CL

Output Load

= 100 pF

O.4V to 2.4V

Input Pulse Levels

"'"

Timing Measurement Reference Level
1V and 2V

Input

0.8Vand 2V

Output

5 ns

Input Rise and Fall

Read Mode AC Electrical CharacteristicsTA = 0'Ct070'C, Vcc = 5V ± 10%
NMC98C64-20
Parameter

Symbol

Conditions

Min

NMC98C64-25

NMC98C64-35

Typ Max Min Typ
Max Min Typ
Max Units
(Note 1)
(Note 1)
(Note 1)

tAA

Address Access Time

= OE = VIL

200

250

350

tCE

Chip Enable Access Time

= VIL

200

250

350

tOE

Output Enable Access Time

= VIL

100

120

tHZ

Output in Hi-Z from CE or OE CEorOE

100

tOH

Output Hold from Address
Change

tTR

Input Rise and Fall Time

tLZ

Output Active from CE or OE CEorOE

= VIL

= OE = VIL 0

= VIL 20

ns
(Notes
1 &2)

Write Mode AC Electrical CharacteristicsTA = 0'Ct070'C, Vcc = 5V ± 10% (Note 3)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

Address to WE Setup Time

tAH

Address to WE Hold Time

200

tcs

Write Setup Time

tCH

Write Hold Time

tOES

OE to WE Setup Time

TOEH

OE to WE Hold Time

200

twp

Write Pulse Time

200

tWPH

Write Pulse High

200

tDS

Data Setup Time

100

tDH

Data Hold Time

tDB

Time to Device Busy

tDLP

Page Data Load Time

twc

Write Cycle Time

tTR

Input Rise and Fall Time

tAS

= VIH

20
120

300

1000

,.,.s (Note 4)

ns (Note 1 & 2)

Note 1: This parameter only sampled and not 100% tested.

Note 2: All input signals must transit from VIL to VIH or from VIH to VIL in a monotonic manner. Transition times are measured between VIL (max) and VIH (min).

wl:

Note 3: Write cycles can be controlled by either
or CE. Timing Diagram on page 5 indicates WE controlled Write Cycle. For CE controlled Write Cycle (Le.
CE goes LOW after WE and goes HIGH before WE) timing specs referenced to WE edges should be referenced to CE edges.
Note 4: Proper DL cycles are guaranteed up to Minimum tOLP time. CE or WE DON'T CARE starts after Maximum tOLP time.

1-59

•

r----------------------------------------------------------------------------,

~ Timing Waveforms
~

ADDRESS

WE~~--------+-----+_----_+--~----------~--------~~--~----------

DOUT-----------t~~~:::::t::)@lmlm~:::t~----_t~~----~----TL/D/7514-4

FIGURE 3. NMC98C64 Read Cycle Switching Time Waveforms

RDY/BUsY ___+-__

-!=I;;;;,,;i~~

TLlD17514-5

FIGURE 4. NMC98C64 Write Cycle Switching Time Waveforms

1·60

Section 2
Application Notes

»
OJ

....

Avoiding Problems Caused
by Capacitive Coupling
Between Input Signal Lines
on 21-Volt EEPROMs

National Semiconductor
Application Brief 13
Elroy Lucero
May 1984

The high input impedance of MOS memories, such as the
NMC 2816, makes such parameters as board layout, signal
shielding, device package, and driver characteristics of
great importance in minimizing the effects of pin to pin coupling between input signal lines.

In standard 5-volt systems the amount of voltage coupled
between input signal lines is small and does not usually
present problems. However, for EEPROMs requiring 21 volt
pulses, the voltage coupled between input signals can be
much larger and may damage other devices on the signal
line whose input characteristics require that Yin does not
exceed Vcc + 1 volt. Moreover, an input signal coupled
above the specified Vih maximum may cause the device to
enter an undesired or non-user test mode (e.g., "read redundancy" or "stress array").

This problem is exaggerated on 21 volt EEPROMs where
the high voltage programming pulse applied to the VPP input (pin 21) can couple sufficient voltage to the OE signal
line (pin 20) as to force the circuit into the chip erase mode
of operation, thereby causing data loss.

The input impedance of an MOS input is typically greater
than 50 megohm for Yin less than 20 volts and Ta = 25"C.
This extremely high input impedance is limited only by the
reverse diode leakage of the pn junction present at the input. This pn junction (part of the input protection circuitry
used to guard against possible ESD damage) is temperature
sensitive causing the effective input impedance to increase
at lower temperatures.

Figure 1 is a simplified schematic diagram showing the possible sources of pin to pin capacitive coupling and the output stages of standard TTL drivers used to drive the address and OE input signal lines.

The voltage coupled to the OE input signal line is

V20=V

+ (

C2120) Il.V21 + (C2019) Il.V19
C2120+C20
C2019+C20

PROGRAM
PULSE
GENERATOR

TTL DRIVER
CLASS·B
OUTPUT STAGE

Vee

VSS

TTL DRIVER
CLASS·B
OUTPUT STAGE

Vee

VSS
TLi0i7084-1
Note: All capacitors are total effective capacitance caused by trace to trace capacitance on PC board, package pin to pin capacitance. device input
capacitance, signal line capacitance, etc.
Note: Resistor R limits voltage overshoot above Vih cause by capacitive coupling.

FIGURE 1. Schematic Diagram Showing Pin to Pin Capacitive Coupling
and the Output Stages of TTL Drivers Used to Drive Signal Lines

2-3

en....
M

impedance of the driver can be lowered for voltages above
Voh. This modification will provide a low impedance path to
Vee (or Vss) for discharging the coupled voltage. This simple technique will ensure that the voltage seen by the MOS
input will not exceed the specified Vih maximum (Vee + 1
volt). In the case of 21-volt EEPROMs this technique used
on the OE driver will prevent inadvertent chip erase cycles
from occurring and therefore enhance the overall system
reliability. In addition, steps taken to reduce the amount of
capacitive coupling between input signal lines and proper
shielding of input signals further reduces the possibility of
data loss.

The output impedance of a standard TTL driver is quite low
and suitable for driving an MOS input signal line for Voh less
than 4.5 volts. However, if the output voltage of the driver is
coupled above this potential the driver enters a high impedance region, with only the reverse diode leakage of the output pn junction to limit the final voltage coupled to this signal
line. Therefore care must be taken to minimize the amount
of signal to signal coupling and insure that the driver output
characteristics remain compatible with the characteristics of
the MOS input being driven.
Fortunately for users of MOS memories the solution is simple and straightforward. By adding a resistor between Vee
(or Vss) and the output of the TTL driver the effective output

2-4

):.

National Semiconductor
Application Brief 15
Asim Bajwa

Protecting Data in the
NMC9306/COP494 and
NMC9346/COP495 Serial
EEPROMs

.....

(II,

May 1984

I'·. ·~:
i~

. The NMC9306/COP494 and NMC9346/COP495 are nonvolatile serial access memories with the following salient
features:

be executed as usual. However, all programming instructions (ERASE, WRITE, ERAL and WRAL) are ignored until
the EWEN instruction is executed to enable programming.
On Vee power up the device is designed to automatically
enter the read-only mode to avoid accidental data loss due
to power up transients. Putting the device in the read-only
mode before powering down Vce avoids spurious programming during power down.

• Low cost
• Single supply read/write/erase operation (5V ± 10%)
• TTL compatible
• MICROWIRETM compatible I/O
• 16 x 16 serial read/write memory (NMC9306/COP494)
64 x 16 serial read/write memory (NMC9346/COP495)

The following guidelines are presented and should be incorporated into the user's designs to achieve the maximum
possible protection of stored data (Figure 2) :

• Self-timed programming cycle (NMC9346/COP495 only)
• Ready/busy status
signal
during
programming
(NMC9346/COP495 only)
• Read-only mode
The read-only mode is provided to prevent accidental data
disturb, especially during Vee power up, power down or excessive noise on the I/O or power supply pins.
Executing the EWDS instruction (Figure 1) activates this
mode by disabling the programming modes and the high
voltage pump. The READ instruction is not affected and can

1) The device powers up in the read-only mode. However,
as a backup, the EWDS instruction should be executed
as soon as possible after VCC to the. EEPROM is powered up to ensure that it is in the read-only mode.
2) Immediately preceding a programming instruction
(ERASE, WRITE, ERAL or WRAL), the EWEN instruction
should be executed to enable the device for programming; the EWDS instruction should be executed immediately following the programming instruction to return

~~___S_~_N_DB_Y______

EWEN
EWDS

DI~"::'O--::.O,r--'t
_ _~""
_
'U.l.l.l.~'U.I.I.I..:A..
_ _ _ _ _ __
ENABLE=l1
DISABLE=OO
TL/D/7085-1

MAIN POWER SUPPLY

4.5V·5.5V

Vee

FIGURE 1. EWEN, EWDS Instruction Timing

1...._____

TL/D/7085-2

*EWDS must be executed before Vee drops below 4.5V to prevent accidental data loss during subsequent power down and/or power up transients.

FIGURE 2. Typical Instruction Flow for Maximum Data Protection

2-5

~r-----------------~,~.'~------------------------------------------'
.,...
the device to the read-only modl\l ar.d protect the stored
must be large enough to maintain Vee between 4.5 and

------1....--- NMC9716/2816

24V

10k
""",.t\,o-5V

CHIP
ERASE
1.2k

"'JVV\o-24V
ERASE/WRITE
(WRITE/RO)

TL/D/51S2-6

FIGURE 6. VPP Switch Design
with Electronic Shutdown for CE
Pulsed Erase/Write for NMC9716

TlID/5152-S

FIGURE 5. OE Chip Erase Control
for NMC2816/NMC9716

24V+--------1~-,----~~----------------------~

3.9k

5V
12k
lM35B
lN914
VPP CONTROL
(WRITE/RO)

. .---t-.. VPP PIN
OF NMC2816

1N914
5k

47k

TL/O/51S2-7

Note 1: 5k is 21 V fine adjust.
Note 2: Resistors are 1/4W.

FIGURE 7. Operational Amplifier VPP Switch Design for NMC2816

2-12

r------------------------------------------------------------------.~

When the capacitor reaches the Zener cut off, the Zener
clamps, charging ceases and the circuit output sits at 21V.

The following r>aragraphs outline a second method of generating a 21 V pulse from a single 5V supply. Figure 8 shows
such a DC-DC converter circuit.

When the signal at node A goes to TTL low, the open collector output of comparator A 1A clamps low, discharging
the .05 capacitor and getting the circuit ready for the next
pulse. Any EEPROM programming requirement can be met
by varying the gain of A 1 B, the time constant at its input
and/or the Zener value across the capacitor. Any TTL detect value can be set by the voltage-divider on the A 1A
comparator in this case set at about 1.5V.

In the circuit, inductor L 1 in conjunction with transistors 01
& 02 form a self driven 5-30V converter. Transitors 03 &
04 are meant to strobe the converter allowing it to draw
power and run only when a TTL high is presented at the
input node A. Trace A. Figure 9 shows the signal to be applied at the input node. This makes the 03-04 transistor
pair conduct biasing 01 & 02. Trace B, Figure 9 shows the
resultant waveform generated at node B, the collector of
02. As the converter runs, its output at node C rises to the
desired high voltage of 30V quickly. The output is lightly
filtered by the .1 F capacitor. Trace C, Figure 9 shows this
waveform.

Transistor 05 is provided to source boosted output current.
Diode D6 is provided to hold the output or Vpp as close to
Vcc as possible when 21V is not desired. A Ge or Schottky
diode must be used to optimize the diode forward drop at
,; .2V. D5 is provided to maximize the reverse breakdown
from node D to base of 05, when 21 volts is at node D.

The voltage at node C is used to charge the 12k, .05fLF
combination at the desired RC of 600fLS, This signal cut off
at 21V by the Zener at the input to A 1 B is presented to the
amplifier A 1B to be outputted to node D as the desired V pp.
The amplitude and pulse shape is controlled by setting the
cut-off Zener voltage in conjunction with the gain of A 1B set
by R2. For example, if 7V Zener voltage is used for cut off a
gain of 3 will have to be set for A 1B to get a 21 V output pulse.

Figure 9 shows the idealized signals generated at various
nodes. When the input at node A is at TTL low level, the
output D sits at 4.8V. As the input A goes to a TTL high level
the output D rises to 21V at RC of 600fLS, The waveform at
node A may be derived from the CE by inverting the CE
signal. The resulting waveform at node D is used for Vpp.

R5
11k

~05f10

SK
DilDO

Common to all 9306's

6CS for 6- 9306's

SK is generated on port pins by bit-set and bit-clear operations in software. A symmetrical duty cycle is not critical.

* CS is set in software. To generate 10-30 rna write/erase the timer/counter is used. During write/erase. SK may be turned off.

FIGURE 3. NSC800™ to NMC93061nterface (also Valid for 8085/8085A and 8156)

2·16

»
z

•
w
w
co

.....

ADD
DECODE

AO-A15

MK3880

.....

DO ,,,,,-

DATA BUS
MI .....
8 BITS
lORa
RD .. PliO CTRL ..

l8D

CPU

DO CE
07

AO ...
A7 ,'III PORTA 110 ,.

lORa

MK3881

iN!

l8DI

PIO

lEI'
INTERRUPT
CONTROL LINES
13)

CID BIA

BO ...
B7 .. PORT B 110 ,.

lEO'

NMC930S
BANK 1
IS)

NMC930S
BANK 2
IS)

TLID15286-4

Z80-P10

9306

AO
A1

~~DO 1 Common to all 9306'5 (Bank 1)

A2-A7

CS1-CS6

.. Only used if priority interrupt daisy chain is desired
* Identical connection for Port B

FIGURE 4. ZSO -

NMC9306 Interface Using ZSO-PIO Chip

DATA
01
NMC930S
DO # 1
CLOCK

P1S

SK CS1

P15
INSBD4B
P14
P13

CS2
74138
B DECODER

P12
P1'

CS9
EN

01
NMC93DS
DO #2

CS2

' - - -......-CS9
TLID15286-5
'" SK and 01 are generated by software. It should be noted that at 2.72 /-Ls/instruction. The minimum SK period achievable will be 10.88 fLs or 92 kHz, well
within the NMC9306 frequency range.

* DO may be brought out on a separate port pin if desired.

FIGURE 5. 4S Series /LP -

2-17

NMC9306 Interface

co
C")

C")

P20~_---1 P20

P21I-01-...-1

LDI

P21
P221-1-1-~ P22
P23 I-I-'I-..c:

a..

MIN

0300-0.320

0.130 ±0.005
(3.302 ±0.127)

(1.651)

90'±4'
_

10.229-0.381)

0.325

0075 ±0.015

.1
~~:~~~

OPTIONS 2,3

0.145 - 0.200
(3.683 - 5.080)

",'' 'r~
~~ ..~" T-J
I.

0.032 ± 0.005
(0.813 ±0.127)
413
RAD
_. P I N ND.lIDENT
1
2

Q (6.350 ±0.127)
1::ffi=Ti'M~~m=;=;;;=l~

~
I
C~"ll'~
0.280
i7112)

====:'2==~11==:'O===9==='~---r
f7\ 0.250 ±0.005

(1'905'0'381)}

~~(0.457±0.076)
0.018 ±0.003

I
_

0.100 ±O 010
(2.540 ±0.254)

0.125 - 0.140
(3.175 - 3.556)

/8255 +1.016)
V' -0.381

N14A (REV D)

NS Package N14A

0.092
(2.336)

NOM

0.843-0.870
(21.41-22.10)

I
(0.762)~2'286)--

0.030

MAX

DEEP (2 PlCS)

0.090·

':!'::f:'i:!:::!::!:::!i';;;:'b::!:';:4!::::!:'3:!:=!;;'2:!:=!::':!'elO;!,j

NOM
PIN NO.1 IDENT

-:-:j
,
0,250 ±0.005
(6,350 ±0,127)

(~:~~:)~

1#;;:;;;=;:;;:;=r;:;=:;:;:;:=;:;;:;:=;:;;=r;:;=?,:?J

MIN

r:
~
0.300-0,320

o
-:'::_

I •

+0.040 .. 1
0.325 -0.015

18255
\ '

+1.016)
-0.381

0,065

0,020
0.025 ±O.O 15
(0.635 ,0,381)

ro-

(0.508)
~~~:;;;' MIN

0.100 ±omo
(2.540 ±0,254)
TYP
N18A (REV E)

NS Package N18A

4-4

"'D

::::J'

'<
1/1

o·
!!!.
c
3·

(~~2.:~~ ~22.~~) ------~._II
13

0.062
11.575)
RAD

r:j::\
V

(1)

::l
1/1

ii'

ii
I'"

0::l
1/1

I 0.540 ·0.005
1(13.716,0.127)

~~rT~r,r~~~~~~FT~~~Fr.~i ~

PIN NO.1 IDENT

(1473)

MIN

o600-0 620

(0762)

I
I

DOTTED OUTliNES
REFLECT ALTERNATE
MOLDED BOD V CONFIGURATION
0030

1 MAX

rr-115.24-15.748)

I.
I

0075
11.905)

L=---++--------'-"--H----r1
0.170-0.210
14.318-5.334)

~ ,,---'--=-~

95"·5"

f--- 0.625 +0.025
-0.015

I
I

10.229-0.381)
0.075'0.015
11.905,0.3811-

(15875+ 0.635 ) .
-0.381

1N24AIREV E)

NS Package N24A

0.580

~114.73IMIN

0.625+ 0.025

(2.540±O.2S4)

-0.015--_

(15.88 ~~:~:~)

N28BIREVEj

NS Package N28B

4-5

s::

(~:~:) RA$l,!MAX

s::
Q)

TYP

iij

.2
~
.s::
Q.
---l 0.290-0.320

H~
1(7.366-8.128)1

0.180

(~~~)

..-'"""

__
95°±5°

0.310-0410
(7.874-10.41)

O.056±O.OD3
(1.422±0.076)'"

GLASS

SEALANT"!f~~R;:d:t;;::::=b
l

0.008-0.012
(0.203-0.305)

Lo.,00±o."o
{2.54D±O.254j TYP

a.Q18±n.Doa

0.150
(3.810)
MIN

~I -.!!!!.
(2.489)
MAX
BOTH ENDS

~TYP--

NS package J18A

11.025
(0.635)
,AO

/1, II
__

0.590-0.620
----

0.030-(1.055
(o.162-1.3!17)
RAQTYP

.~:~ firEm~~~~~tf~

"14986-'5748}--1

1_0:'." :::::
(11.40 -1.'"
+0.635)'

I
---.I

1'\

-1

~I+,::::=::::,-"'"(2~~~ J
.§'

-11-

t1;f;'
'::::1

(0.4571:0.076)::
0.018 ,0.oOJ
TYP

0.125-0.200
- (3.175-5.080)
MIN

---t=-T

0.150
(3.810)
MIN

NS Package J24A
1.490

~'-"'Cl..l!!U!!LJaillLJID..illLll!!Ll!!Ll!!LI:m..illl.r;il' ----L
(37.8461 MAX
22
21 20

fiHi.240)
0.600

MAX GLASS

0.025
(0.635)
'AD

O.514~O.526

' ' 061'' 36'
O,OlO-1I055
(0.162-1391~

RADTYP

0.1/10
(4.S12f

MAX

mm~~~
h

0.D60~O.100

0.100·0.1110
(25411'0.2541

(1.524~2.5401

NS Package J28A

4-6

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(Continued)

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@1985 National SemiCOnductor Corp. W1401

RRD-RR055M75/Printed in U.S.A .

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1985_National_EEPROM_Databook 1985 National EEPROM Databook

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