1985_Rockwell_Data_Book 1985 Rockwell Data Book

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$10.00

1985

DATA BOOK
Rockwell International

Semiconductor Products Division

©Rockwell International Corporation 1985
All Rights Reserved
Printed in U.S.A.

Order NO.1
January, 1985

Rockwell Semiconductor Products Division is headquartered in Newport Beach,
California with Field Sales Offices located throughout the United States, Canada
Europe and the Far East. Their listings, plus those of domestic and international
representatives and distributors, appear on pages A-1 through A-5 of this
publication.

NOTICE

Rockwell International does not assume any liability ariSing out of the application or use
of any products, circuit or software described herein, neither does it convey any license
under its patent rights nor the patent rights of others. Rockwell International further
reserves the right to make changes in any products described herein without notice.
Specifications in the Data Book are subject to change without notice. Preliminary
specifications have tentative parameters which may be subject to change after final
product characterization is completed.

TABLE OF CONTENTS
Rockwell Semiconductor Cross-Reference
Guide ..................................... .
Application Note Index. . . . . . . . . . . . . . . . . . . . . . . . . .

2

Part Number/Data Book Page Index . . . . . . . . . . . . . . .

3

Index by Product Family. . . . . . . . . . . . . . . . . . . . . . . . .

5

R68000 Microprocessor and Peripherals. . . . . . . .
1-1
Product Family Overview . . . . . . . . . . . . . . . . . . . . .
1-1
R68000 16-Bit Microprocessing Unit (MPU). . . . . . .
1-3
R68265 Double-Density Floppy Disk Controller
~~Dq ..................................
1~
R68465 Double-Density Floppy Disk Controller
(DDFDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-60
R68560 Multi-Protocol Communications Controller
(MPCq ................................... 1-86
R68561 Multi-Protocol Communications Controller
(MPCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-86
R68802 Local Network Controller (LNET) ......... 1-118
R68C552 Dual Asynchronous Communications
Interface Adapter (DACIA) . . . . . . . . . . . . . . . . . . . .. 1-138
2

8-Bit Microprocessors and Peripherals. . . . . . . . .
Product Family Overview .. . . . . . . . . . . . . . . . . . . .
R6S00 Family Products
R650X Microprocessors (CPU). . . . . . . . . . . . . . . . .
R651X Microprocessors (CPU). . . . . . . . . . . . . . . . .
R6501Q One-Chip Microprocessor. . . . . . . . . . . . ..
R6511 Q One-Chip Microprocessor. . . . . . . . . . . . ..
R6520 Peripheral Interface Adapter (PIA) . . . . . . . ..
R6522 Versatile Interface Adapter (VIA) . . . . . . . . ..
R6530 ROM-RAM-I/O Timer (RRIOT) . . . . . . . . . . ..
R6531 ROM-RAM-I/O-Counter (RRIOC). . . . . . . . ..
R6532 RAM-I/O:rimer (RIOT) . . . . . . . . . . . . . . . . ..
R6541 Q One-Chip Intelligent Peripheral
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
R6500/41 One-Chip Intelligent Peripheral
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
R6500/42 One-Chip Intelligent Peripheral
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
R6500/43 One-Chip Intelligent Peripheral
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
R6545 CRT Controller (CRTq . . . . . . . . . . . . . . . . .
R6545-1 CRT Controller (CRTq . . . . . . . . . . . . . . . .
R6549 Color Video Display Generator (CVDG) .....
R6551 Asynchronous Communications Interface
Adapter (ACIA) .............................
R6592 Single Chip Printer Controller ............
R65560 Multi-Protocol Communications Controller
(MPCC) ...................................

3

2-1
2-2
2-3
2-3
2-18
2-18
2-24
2-36
2-58
2-69
2-82
2-92
2-92
2-92
2-92
2-100
2-118
2-134
2-165
2-185
2-196

iii

R65C02 CMOS Microprocessor (CPU). . . . . . . . . . .
R65Cl02 CMOS Microprocessor (CPU) ..........
R65Cl12 CMOS Microprocessor (CPU) ..........
R65C21 CMOS Peripheral Interface Adapter (PIA) ..
R65C22 Versatile Interface Adapter (VIA). . . . . . . . .
R65C24 CMOS Peripheral Interface Adapter Timer
(PlAT) .....................................
R65C51 CMOS Asynchronous Communications
Interface Adapter (ACIA) . . . . . . . . . . . . . . . . . . . . ..
R65C52 CMOS Dual Asynchronous
Communications Interface Adapter (DACIA) .......
ZBO/BOBO Bus Compatible Products
R6265 Double-Density Floppy Disk Controller
(DDFDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R6765 Double-Density Floppy Disk Controller
(DDFDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-226
2-226
2-226
2-242
2-254

R6S00/" Microcomputers. . . . . . . . . . . . . . . . . . . .
Product Family Overview .... . . . . . . . . . . . . . . . . .
R65COO/21 Dual CMOS Microcomputer. . . . . . . . . .
R65C29 Dual CMOS Microprocessor. . . . . . . . . . . .
R65Fll FORTH One-Chip Microcomputer. . . . . . ..
R65F12 FORTH One-Chip Microcomputer. . .. .. ..
R65FRX RSC FORTH Development and Kernel
ROMs ....................................
R65FKX RSC FORTH Development and Kernel
ROMs ....................................
R6501 Q One-Chip Microprocessor. . . . . . . . . . . . ..
R6500/1 One-Chip Microcomputer ..............
R6500l1E Emulator Device ....................
R6500/1 EB Backpack Emulator . . . . . . . . . . . . . . . .
R6500/1EAB Backpack Emulator ...............
R6500/11 One-Chip Microcomputer .............
R6500/12 One-Chip Microcomputer .............
R6500/15 One-Chip Microcomputer .............
R6500/16 One-Chip Microcomputer .............
R65/11EB Backpack Emulator .................
R65/11EAB Backpack Emulator ................
R6511Q One-Chip Microprocessor ..............
R6500/13 One-Chip Microcomputer .............
R6500/41 One-Chip Intelligent Peripheral
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
R6500/42 One-Chip Intelligent Peripheral
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R65/41 EB Backpack Emulator . . . . . . . . . . . . . . . . .
R65/41 EAB Backpack Emulator. . . . . . . . . . . . . . . .
R6541Q One-Chip Intelligent Peripheral
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
R6500/43 One-Chip Intelligent Peripheral
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-1
3-2
3-3
3-3
3-36
3-36

2-276
2-296
2-316

2-335
2-335

3-68
3-68
3-76
3-105
3-136
3-143
3-143
3-149
3-149
3-149
3-149
3-184
3-184
3-189
3-189
3-224
3-224
3-253
3-253
3-258
3-258

TABLE OF CONTENTS (Continued)
4

5

6

Memory Products ..........................
Product Family Overview .....................
Masked ROMs
R2332A 32K NMOS Static ROM ................
R2332B 32K NMOS Static ROM ................
R2364A 64K NMOS Static ROM ................
R2364B 64K NMOS Static ROM ................
R23C64 64K CMOS Static ROM ................
R23128 128K NMOS Static ROM ...............
R23C128 128K CMOS ROM ...................
R23256 256K Static ROMs ....................
R23257 256K Static ROMs ....................
UV Erasable PROMs
R87C64 64K CMOS UV EPROM ...............

4-1
4-2

RDC-1024 Rockwell Design Center 8K132K164K
Target RAM Module ..........................
RDC-1030 Multiple Target Development System
PROM Programmer Module ...................
Software Preparation System
SPS-200 Software Preparation System Peripheral
Connector Module ...........................

4-3
4-3
4-7
4-11
4-15
4-19
4-23
4-27
4-27

7

4-31

EPROM Pinouts Guide .......................

4-37

Intelligent Display Controllers .................
Product Family Overview .....................
10937 Alphanumeric Display Controller ..........
10957 Alphanumeric Display Controller ..........
10938 Dot Matrix Display Controller .............
10939 Dot Matrix Display Controller .............
10939 Dot Matrix Display Controller .............
10942 Dot Matrix Display Controller .............
10943 Dot Matrix Display Controller .............
10941 Alphanumeric and Bargraph Display
Controller ..................................
10939 Alphanumeric and Bargraph Display
Controller ..................................
10951 Bargraph and Numeric Display Controller ...
10955 Segmented Display Controller/Driver .......

5-1
5-2
5-3
5-3
5-11
5-11
5-21
5-21
5-21

Microcomputer Development Systems .........
Product Family Overview .....................
RDC-1001/2 Multiple Target Development System
(MTDS) ...................................
RDC-31 01/2 Low Cost Emulator (LCE) ...........
RDC-3XX Rockwell Design Center R6500/'
Personality Set .............................
RDC-502 Rockwell Design Center R6502-R65C02
Personality Set .............................
RDC-504 Rockwell Design Center R6502-R65C02
Personality Set .............................
RDC-509 Rockwell Design Center R6502-R65C02
Personality Set .............................
RDC-2000 R6500 Cross Assembler for Intel
Development System ....... _................
RDC-2005 R6500 Cross Assembler for Intel
Personal Development System .................
RDC-1020 Rockwell Design Center 8K132K164K
Target RAM Module ..........................
RDC-1022 Rockwell Design Center 8K132K164K
Target RAM Module ..........................

6-1
6-2

5-31
5-31
5-41
5-51

6-3
6-9
6-14

Integral Modems ...........................
Product Family Overview .....................
Product Preview-High Speed Modems
R96FT/SEC 9600 BPS Fast Train Modem with
Secondary Channel ..........................
R144 Synchronous 14.4 KBPS Modem ..........
R4875 4800/75 BPS Modem ...................
R208A1B 4800 BPS Modem ...................
High Speed
R96FAX 9600 BPS Facsimile Modem ............
R96DP 9600 BPS Data Pump Modem ...........
R96FT 9600 BPS Fast Train Modem .............
V96P/1 9600 BPS Modem ....................
R48DP 4800 BPS Data Pump Modem ...........
V27P/1 4800 BPS Modem ....................
Product Preview-Low to Medium Speed
Modems
R1212DS Modem Device Set
(212A Compatible) ....................•.....
R2424DS Modem Device Set ..................
R24DP 2400 BPS Modem
(201 C Compatible) ..........................
Low to Medium Speed
R1212 1200 BPS Full Duplex Modem ............
R1212/U 1200 BPS Full Duplex Modem with
Internal USART .............................
R2424 2400 BPS Full Duplex Modem ............
R24DC 2400 BPS Direct Connect Modem ........
R24LL 2400 BPS Leased Line Modem ...........
R24 2400 BPS Integral Modem .................
Modem InterfaCing Products
RDAA Rockwell Data Access Arrangement
Module ...................................

6-26
6-30

6-36
7-1
7-2

7-3
7-4
7-5
7-6
7-7
7-20
7-34
7-47
7-55
7-69

7-76
7-77
7-78
. 7-79
7-94
7-110
7-126
7-134
7-143

7-151

6-18

8
6-18
6-18
6-22
6-24

T·1 and T·lICEPT Pulse Code Modulation
Protocol Devices ...........................
Product Family Overview .....................
R8040 Tri-Port Memory ........................
R8050 T-1 Serial Transmitter ...................
R8060 T-1 Serial Receiver. . . . . . . . . . . . . . . . . . . . .
R8070 T-lICEPT Pulse Code Modulation
Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-1
8-2
8-3
8-9
8-17
8-23

6-26
Sales Offices, Representatives and
Distributors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

6-26

iv

A-1

ROCKWELL SEMICONDUCTORS CROSS·REFERENCE GUIDE

SYNERTEK

ROCKWELL

NCR

SY6502
SY6503
SY6504.
SY6505
SY6506
SY6507
SY6512
SY6513
SY6514
SY6515
SY6520
SY6522
SY6530.
SY6532
SY6545-1
SY6551

R6502
R6503
R6504
R6505
R6506
R6507
R6512
R6513
R6514
R6515
R6520
R6522
R6530
R6532
R6545-1
R6551

NCR6500/1E
NCR6500/1 ...
NCR6500/11 ..
NCR6500/12 ....
NCR6500/13
NCR6500/11 E
NCR6500/41
NCR6500/42
NCR6500/43 .
NCR6500/41E
NCR65C02 .

....

..

.. ..
·

INTEL
8272
MOTOROLA

MC6820
(1)MC6821
(2)MC6845
(2)MC6845M
MC68000

·

MOS TECHNOLOGY

GTE

ROCKWELL

G65SC02.
G65SC21
G6SSC51.

R65C02
... R65C21
.. R6SC51
R23C64

ROCKWELL

R6765
ROCKWELL

R6520
· R6520
R6545-1
R6545-1
R68000

(1) except apphcatlOn of (2) TIL loads
(2) ask customer for evaluatIon

MPS6502.
MPS6503
MPS6504
MPS6505
MPS6506
MPS6507
MPS6512
MPS6513
MPS6514
MPS6515
MPS6520
MPS6522
MPS6530
MPS6532

ROCKWELL
R6500/1EC
· R6500/1
. .... R6500/11
R6500/12
R6500/13
R65110
R6500/41
R6500/42
· R6500/43
R6541 0
R65C02

ROCKWELL

R6502
R6503
R6504
R6505
R6506
R6507
R6512
R6513
R6514
· R6515
R6520
R6522
R6530
R6532

RICOH

ROCKWELL

RD5H64

R87C64

AMI

ROCKWELL

S2333
S2364 ..
S23128
S6551

R2332
.. R2364
R23128
.. R6551

...

FUJITSU

ROCKWELL

MBM27<364

R87C64

AMD

ROCKWELL

AM2764.

· R87C64

ROCKWELL

RCA

CDP65564

...

.. R23C64

NEC

ROCKWELL

765

R6765

APPLICATION NOTE INDEX
Order No.

Title

Order No.

R6500 Mlcroproceaeora and Peripherals
223
296
256

R6S02lR6532 Timer Interrupt Precautions
R6502 Interfacing Higher Speed R6502's to Lower
Speed I/O & Memory
Printer Control with R6522 VIA (Versatile Interface
Adapter)

226

R6531 ROM-RAM-I/O Counter (RRIOC)

227
225

R6531 Address Lines for Contiguous ROM
Generating Non·Standard Baud Rates with the R6551
ACIA (Asynchronous Communication Interface Adapter)

208

Low-Cost Crystal Oscillator for Clock Input Frequency
Generator

231
276

Interfacing R6S00 Microprocessors to a FDC (Floppy
Disk Controller)
Crystal Considerations for R6500 Family Devices

287

USing R65XX Family Peripheral Devices with Z80 CPU

224

237
258
2163

2162
2178
2182

Interfacing R6S00/1 to SIDC (Serial Input Display
Controller)
R6500/1 Microcomputer·Based Printer Controller
A Logical Tester for R6500/1 One-Chip Microcomputer
A Dot Matrix Controller System Design Using the
10938/10939 Display Drivers and R6500/1 EB
Microcomputer
A Low Cost Development Module for the
R65Fl1/R65FI2 FORTH Microcomputer
Design Considerations for Conversion to Rockwell
R6500/11 and R6501Q from Intel 805118031
R6500/41 Based Stepper Motor Controller

Intelligent Display Controllers
2163

A Dot Matrix Controller System Design Using the
10938/10939 Display Drivers and R6500/1EB
Microcomputer

2175

Display Controller Designer Notes

System 65 to AI~ 65 Microcomputer Interface

240

User 65 Emulation with less than 512 Byles of RAM

246

System 65 Bus Interface

2129

OS3.1 Monitor ROM & Macro Assembler/linking Loader

2158

CMOS User 65 System 65 Development System

2166

R6500 Software Preparation System Development
Configurations

Integral Modema

R6500/' Microcomputers
239

Title

Microcomputer Development Systems

2

607

R24 Modem Options

608

Quality of Received Data for R24 Modem

619

R24DC Interface to EIA RS·232·C

622

R24DC Interface to U.S. SWitched Telephone Network

624

R24DC Modem Options

634

R24LL and R24DC Modem Control Signal To LED
Interface

632

R24LL Modem Interface to EIA RS-232-C

635

R24LL Modem Options

617

4800/9600 BPS Modem Interfacing

637

Picture Plotter Data Transmission System

654

R96FAX Modem RAM Write Control

656

R96FAX Modem Recommended Receive Sequence for
Group 2 Facsimile

656

R96FAX Modem Scrambled Ones Work-Around for
R530D-18 and R530D-19

657

R96DP and R48DP Modems RAM Write Control

658

High Speed Modems Filter Characteristics

PART NO.lDATA BOOK PAGE INDEX
10937 Alphanumeric Display Controller ................ 5-3
10938 Dot Matrix Display Controller .................. 5-11
10939 Display Controller ................. 5-11, 5-21,5-31
10941 Alphanumeric and Bargraph Display
Controller ..................................... 5-31
10942 Dot Matrix Display Controller .................. 5-21
10943 Dot Matrix Display Controller .................. 5-21
10951 Bargraph and Numeric Display Controller ........ 5-41
10955 Segmented Display Controller/Driver ........... 5-51
10957 Alphanumeric Display Controller ................ 5-3
R1212 1200 BPS Full Duplex Modem ................. 7-79
R1212DS Modem Device Set (212A Compatible) ........ 7-76
R1212/U 1200 BPS Full Duplex Modem with
Internal USART ................................ 7-94
R144 Synchronous 14.4 KBPS Modem ................ 7-4
R208A/B 4800 BPS Modem ......................... 7-6
R23128 128K NMOS Static ROM .................... 4-19
R23256 256K Static ROMs ......................... 4-27
R23257 256K Static ROMs ......................... 4-27
R2332A 32K NMOS Static ROM ..................... 4-3
R2332B 32K NMOS Static ROM ..................... 4-3
R2364A 64K NMOS Static ROM ..................... 4-7
R2364B 64K NMOS Static ROM .................... 4-11
R23C128 128K CMOS ROM ....................... 4-23
R23C64 64K CMOS Static ROM .................... 4-15
R24 2400 BPS Integral Modem ..................... 7-143
R24DC 2400 BPS Direct Connect Modem ............ 7-126
R24DP 2400 BPS Modem (201 C Compatible) .......... 7-78
R24LL 2400 BPS Leased Line Modem ............... 7-134
R2424 2400 BPS Full Duplex Modem ................ 7-110
R2424DS Modem Device Set ....................... 7-77
R4875 4800/75 BPS Modem ......................... 7-5
R48DP 4800 BPS Data Pump Modem ................ 7-55
R6265 Double-Density Floppy Disk Controller
(DDFDC) .................................... 2-335
R6500/1 One-Chip Microcomputer .................. 3-105
R6500/11 One-Chip Microcomputer. ................ 3-149
R6500/12 One-Chip Microcomputer. ................ 3-149
R6500/13 One-Chip Microcomputer. ................ 3-189
R6500/15 One-Chip Microcomputer. ................ 3-149
R6500/16 One-Chip Microcomputer. ................ 3-149
R6500/1E Emulator Device ........................ 3-136
R6500/1EAB Backpack Emulator ................... 3-143
R6500/1EB Backpack Emulator .................... 3-143
R6500/41 One-Chip Intelligent Peripheral
Controller .................................... 3-224
R6500/42 One-Chip Intelligent Peripheral
Controller ............................... 2-92, 3-224
R6500/43 One-Chip Intelligent Peripheral
Controller ............................... 2-92, 3-258
R6501Q One-Chip Microprocessor ..... , . . . . .. . 2-18,3-76
R650X Microprocessors (CPU) ....................... 2-3

R6502 Microprocessor (CPU) ........................ 2-3
R6503 Microprocessor (CPU) ........................ 2-3
R6504 Microprocessor (CPU) ........................ 2-3
R6505 Microprocessor (CPU) ........................ 2-3
R6506 Microprocessor (CPU) ........................ 2-3
R6507 Microprocessor (CPU) ........................ 2-3
R6511Q One-Chip Microprocessor ............. 2-18, 3-189
R651X Microprocessors (CPU) ....................... 2-3
R6512 Microprocessor (CPU) ........................ 2-3
R6513 Microprocessor (CPU) ........................ 2-3
R6514 Microprocessor (CPU) ........................ 2-3
R6515 Microprocessor (CPU) ........................ 2-3
R6520 Peripheral Interface Adapter (PIA) .............. 2-24
R6522 Versatile Interface Adapter (VIA) ............... 2-36
R6530 ROM-RAM-I/O Timer (RRIOT) ................. 2-58
R6531 ROM-RAM-I/O-Counter (RRIOC) ............... 2-69
R6532 RAM-I/O:rimer (RIOT) ....................... 2-82
R6541Q One-Chip Intelligent Peripheral
Controller ............................... 2-92, 3-258
R6545 CRT Controller (CRTC) ..................... 2-100
R6545-1 CRT Controller (CRTC) .................... 2-118
R6549 Color Video Display Generator
(CVDG) ..................................... 2-134
R6551 Asynchronous Communications Interface
Adapter (ACIA) ................................ 2-165
R65560 Multi-Protocol Communications Controller
(MPCC) ..................................... 2-196
R6592 Single Chip Printer Controller ................ 2-185
R65COO/21 Dual CMOS Microcomputer ............... 3-3
R65C02 CMOS Microprocessor (CPU) ............... 2-226
R65Cl02 CMOS Microprocessor (CPU) .............. 2-226
R65C112 CMOS Microprocessor (CPU) .............. 2-226
R65C21 CMOS Peripheral Interface Adapter
(PIA) ........................................ 2-242
R65C22 Versatile Interface Adapter (VIA) ............. 2-254
R65C24 CMOS Peripheral Interface Adapter
Timer (PlAT) .................................. 2-276
R65C29 Dual CMOS Microprocessor .................. 3-3
R65C51 CMOS Asynchronous Communications
Interface Adapter (ACIA) ........................ 2-296
R65C52 CMOS Dual Asynchronous Communications
Interface Adapter (DACIA) ....................... 2-316
R65Fl1 FORTH One-Chip Microcomputer ............. 3-36
R65F12 FORTH One-Chip Microcomputer ............. 3-36
R65FKX RSC FORTH Development and
Kernel ROMs .................................. 3-68
R65FRX RSC FORTH Development and
Kernel ROMs .................................. 3-68
R65/11EAB Backpack Emulator .................... 3-184
R65/11 EB Backpack Emulator ..................... 3-184
R65/41EAB Backpack Emulator ..... " " , '" , . " " " . " " " " 3-253
R65/41EB Backpack Emulator. " ................... 3-253

3

PART NO./DATA BOOK PAGE INDEX (Continued)
R6765 Double·Density Floppy Disk Controller
(DDFDC) ..................................... 2·335
R68000 16-Bit Microprocessing Unit (MPU) ............. 1-3
R68265 Double·Density Floppy Disk
Controller (DDFDC) ................. , ........•.. 1·60
R68465 Double·Density Floppy Disk
Controller (DDFDC) ............................. 1·60
R68560 Multi·Protocol Communications Controller
(MPCC) .................... : .................. 1-86
R6856l Multi·Protocol Communications Controller
(MPCC) ...................................... 1·86
R68802 Local Network Controller (LNET) ..... '. " ..... 1·118
R68C552 Dual Asynchronous Communications Interlace
Adapter (DACIA) .............................. 1·138
R8040 Tri·Port Memory ............................. 8·3
R6050 T-l Serial Transmitter ....... , ..... , . , ......... 8·9
R8060 T-l Serial Receiver.......................... 8·17
R8070 T-lICEPT Pulse Code Modulation Transceiver .... 8·23
R87C64 64K CMOS UV EPROM .................... 4·31
R960P 9600 BPS Data Pump Modem ................ 7·20
R96FAX 9600 BPS Facsimile Modem .................• 7·7
R96FT 9600 BPS Fast Train Modem . .' ... .' ............ 7·34
R96FT/SEC 9600 BPS Fast Train Modem with
Secondary Channel. ............................. 7·3
RDAA Rockwell Data Access Arrangement Module ..... 7·151
ROC·l001/2 Multiple Target Development
System (MTDS) ................................. 6·3

ROC·l020 Rockwell Design Center 8K/32K/64K Target
RAM Module .................................. 6·26
ROC·l022 Rockwell Design Center 8K/32K/64K Target
RAM Module ...................•.............. 6·26
ROC-l024 Rockwell Design Center 8K/32K/64K Target
RAM Module .............................•.... 6-26
ROC-l030 Multiple Target Development System PROM
Programmer Module ......... '.................. '. 6·30
ROC-2000 R6500 Cross Assembler for Intel
Development System ............................ 6·22
ROC·2005 R6500 Cross Assembler for Intel Personal
Development System ............................ 6-24
ROC-310l/2 Low Cost Emulator (LCE) ................. 6·9
ROC-3XX Rockwell Design Center R6500/'
Personality Set ............. : .................. 6·14
ROC-502 Rockwell Design Center R6502·R65C02
Personality Set ................................ 6·18
ROC·504 Rockwell Design Center R6502·R65C02
Personality Set ................................ 6·18
ROC-509 Rockwell Design Center R6502·R65C02
Personality Set ...........•... '................. 6·18
SPS·200 Software Preparation System Peripheral
Connector Module ................... : .......... 6·36
V27P/l 4800 BPS Modem .................. '....... 7·69
V96P/l 9600 BPS Modem .. ,' .............' ..•...... 7-47

4

PRODUCT INDEX
R68000 Microprocessor and Peripherals

8-Bit Microprocessors and Peripherals

R6500/* Microcomputers

~M_e_m_O_r_y_p_r_O_d_u_ct_s________________________________~
Intelligent Display Controllers

Microcomputer Development Systems

Integral Modems

T-1 and T-1/CEPT Pulse Code Modulation Protocol Devices

5

II

SECTION 1
R68000 MICROPROCESSOR AND PERIPHERALS
Page
Product Family Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2

R68000 16-Bit Microprocessing Unit (MPU) ...................................

1-3

R68265, R68465 Double-Density Floppy Disk Controller (DDFDC) . . . . . . . . . . . . . . . ..

1-60

R68560 and R68561 Multi-Protocol Communications Controller (MPCC) ............. 1-86
R68802 Local Network Controller (LNET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-118
R68C552 Dual Asynchronous Communications Interface Adapter (DACIA) ........... 1-138

1-1

R68000 MICROPROCESSOR AND PERIPHERAL FAMILY
16-bit Speed and Data Capacity, Peripherals to Build Efficient
Systems
Rockwell peripherals give a designer everything the
68000 family promises. They allow you to design' functional
systems utilizing all the speed and data handling potential
of the 16-bit 68000 family.
First of these are the Rockwell designed 16-bit
peripherals-multi-protocol communications controller,
double density floppy disk controller, local area network
controller-each a significant "first" that eliminates the
"glue parts" between a CPU and peripherals.
Not to be ignored, however, is the very wide and
complete family of 8-bit devices-processors, peripherals,
memory, single-chip microcomputers-compatible with the
R68000 family. All of the R6500 family of devices described
in this Data Book are directly compatible with the R68000
bus. They often provide efficient, economical and very
flexible ways of implementing system designs.
The Rockwell R68000 16-bit microprocessor (MPU)
operates at clock speeds of 4, 6, 8, 10 or 12.5 MHz to
match essentially any application.
The R68561 multi-protocol communications controller
(MPCC) is the highest throughput communications device
ever made commercially available. It operates up to

4 Mbits/sec and supports all major communication protocols.
It's available to work with either 16-bit or 8-bit busses and
can be adapted to function with essentially any of today's
more common busses.
The R68465 double density floppy disk controller
(DDFDC) is an intelligent device thaI can run up to four disk
drives without the many support devices previously
required.
The R68802' provides a flexible local area network
(LNET) controller for the R68000. It supports both the
IEEE 802.3 and Ethernet' standards based on the proven
CSMA/CD technique together with network statistics.
The R68C552 provides an easily implemented, program
controlled interface between 16-bit microprocessor-based
systems and serial communication data sets and modems.
This device is the first CMOS.ACIA in the industry.
Rockwell lets you build efficient and economical 16-bit
systems through families of 16-bit and 8-bit peripherals, all
compatible. No other supplier offers you more.
• R68802 is a trademark of the Rockwell International Corp.
• Ethernet is a trademark of the Xerox Corp.

R68000/R6500 Peripheral Migration

1-2

R68000

'1'

R68000
16-BIT MICROPROCESSING UNIT (MPU)

Rockwell

PRELIMINARY
DESCRIPTION

The R68000 offers seventeen 32-bit registers in addition to the
32-bit program counter and a 16-bit status register. The first eight
registers (DO-D7) are used as data registers for by1e (B-bit), word
(16-bit), and long word (32-bit) data operations. The second set
of seven registers (AO-A6) and the system stack pOinter may be
used as software stack pointers and base address registers. In
addition, these registers may be used for word and long word
address operations. All 17 registers may be used as Index
registers.

The R68000 microprocessor is designed for high performance
where operational computation and versatility is required. The
R68000 provides powerful mass-memory handling capability and
architectural features designed to fit the broad range of 16-bit
needs. The Rockwell family of 16-bit products also includes a
wide range of peripherals that will allow complete system design
and manufacture.

FEATURES

31

16 15

87

•
•
•
•
•
•
•
•
•

0

DO
01
02
03 EIGHT
04 DATA
REGISTERS
05
06
07
3'

16 15

fff-

I
I
I
I
I
I

-

I
I

--

0

--

-

--USER-STACKPrnNTER-(USP)--

AO
A1
A2 SEVEN
A3 ADDRESS
A4 REGISTERS
AS
A6

15

87

All 17 Registers Can Be Index Registers
Memory Mapped Peripheral Devices
Vector Generated Exception Processing
Seven Unique Autovectors for Interrupt Service Routines
Trace Mode for Software Debugging
Operations Occur on Five Main Data Types
-Bit
-BCD
- Byte
-Word
- Long Word
• Asynchronous and Synchronous Peripheral Interface
Capability
• Many Peripheral Chips Available
- R68560 Multi-Protocol Communications Controller
- R68465 Double Density Floppy Disk Controller
- R68802 Local Network Controller

POINTERS

o

31

•
•
•
•
•
•

A7 TWO STACK

~U!~'!.V.!.S.9!! !T~£.K-"~I!:!.T.§~ ~'"
~~~AT~

CLK

BUS) 00-015
VAS .....
RIW

FCO
PRO{
CESSOR
STATUS
R6500
{
PERIPHERAL
CONTROL

SYSTEM {
CONTROL

FC1
FC2

UOS
R68000
MPU

LOS

DTAcK

E

BR

VMA

BG

VPA

BUS
} ARBITRATION
BGACK CONTROL

BERR
RESET

IPLO

HALT

IPL2

Figure 1.

ASYNCHRO} NOUS BUS
CONTROL

IPL1

INTERRUPT
} CONTROL

UOS

LOS

High

High

Low

Low

High

Data Strobe Control of Data Bus
R/W

08-015

00-07

No valid data

No valid data

High

Valid data bits
8-15

Valid data bits
0·7

Low

High

No valid data

Valid data bits
0-7

Low

High

High

Valid data bits
~ 8-15

No valid data

Low

Low

Low

Valid data bits
8-15

Valid data bits
0-7

High

Low

Low

Valid data bits
0-7"

Valid data bits
0-7

Low

High

Low

Valid data bits
8-15

Valid data bits
8-15"

-

"These conditions are a result of current Implementation and may not
appear on future deVices.

Input and Output Signals

1-5

16-Bit MPU

R68000
3. data transfer acknowledge (DTACK) is inactive which
indicates that neither memory nor peripherals are using the
bus, and
4. bus grant acknowledge (BGACK) is inactive which
indicates that no other device is still claiming bus mastership.

R6500 PERIPHERAL CONTROL. These control signals are
used to allow the interfacing of synchronous R6500 peripheral
devices with the asynchronous R68000. These signals are
explained in the following paragraphs.
Enable (E). The E output signal is the standard enable signal
(¢2 clock) common to all R6500 type peripheral devices. The
period for this output is ten R68000 clock periods (six clocks
low; four clocks high). Enable is generated by an internal ring
counter which may come up in any state (i.e., at power on, it
is impossible to guarantee phase relationship of E to CLK). E
is a free-running clock and runs regardless of the state of the
bus on the MPU.

INTERRUPT CONTROL (IPLO, IPL 1, IPL2). These input pins
indicate the encoded priority level of the device requesting an
ihterrupt. Level seven is the highest priority while level zero indicates that no interrupts are requested. Level seven cannot be
masked. IPLO is the least significant bit while IPL2 is the most
significant bit. To insure an interrupt is recognized, the interrupt control lines (IPLX) must remain stable until the processor
signals interrupt acknowledge (FCO, FC1, and FC2 all high).

Valid Peripheral Address (VPA). The VPA input indicates that
the device or region addressed is a R6500 family device and
that data transfer should be synchronized with the enable (E)
signal. This input also indicates that the processor should use
automatic vectoring for an interrupt. Refer to INTERFACE; WITH
R6500 PERIPHERALS.

SYSTEM CONTROL. The system control inputs either reset or
halt the processor or indicate to the processor that bui; errors
have occurred. The three system control inputs are explained
in the following paragraphs.
Bus Error (BERR). The BERR input informs the processor that
a problem exists with the cycle currently being executed.
Problems may be a result of:
1. nonresponding devices,
2. interrupt vector number acquisition failure,
3. illegal access request as determined by a memory management unit, or
4. other application dependent errors.

Valid Memory Address (VMA). The VMA output indicates to
R6500 peripheral devices that there is a valid address on the
address bus and that the processor is synchronized to enable.
This signal only responds to a valid peripheral address (VPA)
input which indicates that the peripheral is a R6500 family device.
PROCESSOR STATUS (FCD, FC1, FC2). These function code
outputs indicate the state (user or supervisor) and the cycle type
currently being executed, as shown in Table 2. The information
indicated by the function code outputs is valid whenever address
strobe (AS) is active.

The Bus Error (BERR) signal interacts with the HALT signal to
determine if exception processing should be performed or the
current bus cycle should be retried.

CLOCK (CLK). The clock input is a TTL-compatible signal that
is internally buffered for development of the internal clocks
needed by the processor. The clock input should not be gated
off at any time and the clock signal must conform to minimum
and maximum pulse width times.

Refer to BUS ERROR AND HALT OPERATION paragraph for
additional information about the interaction of the bus error and
halt signals.
Reset (RESET). This bidirectional signalli~e acts to reset (initiate
a system initialization sequence) the processor and system in
response to an external reset signal. An internally generated
reset (result of a RESET instruction) resets all external devices
while not affecting the internal state of the processor. A total
system reset (processor and external devices) is the result of
external HALT and RESET signals applied simultaneously. Refer
to RESET OPERATION paragraph for additional information.

SIGNAL SUMMARY. Table 3 summarizes all the signals discussed in the previous paragraphs.

Table 2.
FC2

Halt (HALT). The bidirectional HALT line, when driven by an
external device, will cause the processor to stop' at the completion of the current bus cycle. Halting the processor using HALT
causes all control signals to gel: inactive and all three-state lines
to go to their high-impedance state. Refer to BUS ERROR AND
HALT OPERATION paragraph for additional information about
the interaction between the HALT and BERR signals.
When the processor has stopped executing instructions, such
as in a double bus fault condition, the HALT line is driven by
the processor to indicate to external devices that the processor
has stopped. Refer to paragaph on Double Bus Faults.

1-6

FCI

Function Code Outputs
FCO

Cycle Type
(Undefined, Reserved)

Low

Low

Low

Low

Low

High

User Data

Low

High

Low

User Program

Low

High

High

(Undefined, Reserved).

High

Low

Low

(Undefined, Reserved)

High

Low

High

Supervisor Data

High

High

Low

Supervisor Program

High

High

High

Interrup't Acknowledge

16-Bit MPU

R68000
Table 3.

Signal Summary

D

Hi-Z
Signal Name

Mnemonic

Address Bus

Input/Output
Output

A1-A23

Active State

On HALT

On BGACK

High

Yes

Yes

Data Bus

DO-D15

Input/Output

High

Yes

Yes

Add ress Strobe

AS

Output

Low

No

Yes

R/W

Output

Read-High
Write-Low

No

Yes

Upper and Lower Data Strobes

UDS, LOS

Output

Low

No

Yes

Data Transfer Acknowledge

DTACK

Input

Low

No

No

Bus Request

BR

Input

Low

No

No

Bus Grant

BG

Output

Low

No

No

Bus Grant Acknowledge

BGACK

Input

Low

No

No

Interrupt Priority Level

IPLO, IPL 1, IPL2

Input

Low

No

No

Bus Error

BERR

Input

Low

No

No

Reset

RESET

Input/Output

Low

No'

No'
No'

Read/Wnte

Halt

HALT

Input/Output

Low

No'

Enable

E

Output

High

No

No

Valid Memory Address

VMA

Output

Low

No

Yes

Valid Peripheral Address

VPA

Input

Low

No

No

Function Code Output

FCO, FC1, FC2

Output

High

No

Yes

Clock

No

No

-

-

CLK

Input

High

Power Input

VCC

Input

-

Ground

GND

Input

-

I

'Open drain.
I

REGISTER DESCRIPTION AND DATA
ORGANIZATION

OPERAND SIZE

STATUS REGISTER. The status register contains the eight level
interrupt mask as well as the condition codes; extend (X),
negative (N), zero (Z), overflow (V), and carry (e). Additional
status bits indicate that the processor is in a trace (T) mode
and/or in a supervisor (8) state.

.

SYSTEM BYTE

15

13

.

DATA ORGANIZATION IN REGISTERS

USER BYTE'
11

10

Operand sizes are defined as follows: a byte equals 8 bits, a
word equals 16 bits, and a long word equals 32 bits. The operand
size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. Implicit
instructions support some subset of all three sizes.

8

4

The eight data registers support data operands of 1, 8, 16, or
32 bits. The seven address registers together with the active
stack pointer support address operands of 32 bits.

0

IT~S~12Hlo_xINlzlvlcl
TRACE LODE

I

SUPERVISOR
STATE

IN~T
MASK

EXTE1NDI

DATA REGISTERS. Each data register is 32 bits wide. 8y1e
operands occupy the low order 8 bits, word operands the low
order 16 bits, and long word operands the entire 32 bits. The
least significant bit is addressed as bit zero; the most significant bit is addressed as bit 31. Wh'en a data register is used
as either a source or destination operand, only the appropriate
low-order portion is changed; the remaining high order portion
is neither used nor changed.

'I

\1 I

NEGATIVE
ZERO

OVERFLOW
CARRY
'CONDITION CODE REGISTER
Status Register

1-7

R68000

16-Bit MPU

15

14

13

12

11

10

9

7

8

6

5

4

3

2

0

WORD ,00000
BYTE 000000

BYTE 000001
WORD tOOO02

BYTE 000002

BYTE 000003

I

i

WORD FFFFFE

I

BYTE FFFFFE

Figure 2.

BYTE FFFFFF

Word Organization In Memory

ADDRESS REGISTERS. Each address register and the stack
pointer is 32 bits wide and holds a full 32-bit address. Address
registers do not support byte sized operands. Therefore, when
an address register is used as a source operand, either the low
order word or the entire long word operand is used depending
upon the operation size. When an address register is used as
the destination operand, the entire register is affected regardless
of the operation size. If the operation size is word, any other
operands are sign extended to 32 bits before the operation is
performed.

The address and data buses are separate parallel buses which
transfer data using an asynchronous bus structure. In all cycles,
the bus master assumes responsibility for deskewing all signals
it issues at both the start and end of a cycle. In addition, the
bus master is responsible for deskewing the acknowledge and
data signals from the slave device.
The following paragraphs explain the read, write, and readmOdify-write cycles. The indivisible read-modify-write cycle is the
method used by the R68000 for interlocked multiprocessor
communications.

DATA ORGANIZATION IN MEMORY

Read Cycle. During a read cycle, the processor receives data
from memory or a peripheral device. The processor reads by1es
of data in all cases, and for a word (or double word) operation,
the processor reads both upper and lower bytes simultaneously
by asserting both upper and lower data strobes. When the
instruction specifies by1e operation, the processor uses an
internal AO bit to determine which byte to read and then issues
the data strobe required for that byte. When the AO bit equals
zero, the upper data strobe is issued, and when the AO bit equals
one, the lower data strobe is issued. The processor correctly
positions the received data internally.

Bytes are individually addressable with the high order byte
having an even address the same as the word, as shown in
Figure 2. The low order byte has an odd address that is one
higher than the word address. Instructions and multi-byte data
are accessed only on word (even by1e) boundaries. If a long word
datum is located at address n (n even), then the second word
of that datum is located at address n + 2.
The data types supported by the R68000 are: bit data, integer
data of 8, 16, or 32 bits, 32-bit addresses and binary coded
decimal data. Each of these data types is put in memory, as
shown in Figure 3. The numbers indicate the order in which data
is accessed from ·the processor.

A word read cycle flow chart is given in Figure 4. A byte read
cycle flow chart is given in Figure 5. Read cycle timing is given
in Figure 6. Figure 7 details word and by1e read cycle operations.

BUS OPERATION

Write Cycle. During a write cycle, the processor sends bytes
of data to memory or a peripheral device, If the instruction
specifies a word operation, the processor writes both bytes.
When the instruction specifies a byte operation, the processor
uses an internal AO [:lit to determine Which by1e to write and then
issues the data strobe required for that byte. When the AO bit
equals zero, the upper data strobe is issued and when the AO
bit equals one, the lower data strobe is issued. A word write cycle
flow chart is given in Figure 8. A byte write cycle flow chart is
given in Figure 9. Write cycle timing is given in Figure 6.
Figure 10 details word and byte write cycle operation.

The following paragraphs explain control signal and bus operation during data transfer operations, bus arbitration, bus error
and halt conditions, and reset operation.
.
DATA TRANSFER OPERATIONS. Transfer of data between
devices involves the following signals:
• Address Bus Al through A23
• , Data Bus DO through D15
• Control Signals

1-8

-

-

LONG WORD 2 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ADDRESSES
1 ADDRESS
32 BITS

=

15
MSB
-

-

14

13

12

11

9

10

8

7

6

o

2

3

4

5

HIGH ORDER
ADDRESS 0- -

-

-

-

-

-

-

-

-

-

-

LOW ORDER
-

-

ADDRESS 1- -

-

-

-

-ADDRESS 2- -

-

MSB
LSB

-

-

-

-

-

-

-

-

-

-

-

-- -

LSB

-

-

-

14

13

BCD 0
BCD 4

MSD
LSD

-

-

-

-

-

-

-

-

-

-

-

-

-

= MOST SIGNIFICANT BIT
= LEAST SIGNIFICANT BIT
DECIMAL DATA
2 BINARY CODED DECIMAL DIGITS

15
MSD

-

-

12

11

I

I

10

9

BCD 1
BCD 5

= MOST SIGNIFICANT DIGIT
= LEAST SIGNIFICANT DIGIT
Figure 3.

8

7

LSDI

I

6

= 1 BYTE
5

4

2

I

BCD 3

BCD 6

I

BCD 7

Data Organization In Memory

1·9

3

BCD 2

0

R68000

16-Bit MPU
BUS MASTER

SLAVE

BUS MASTER

SLAVE

--.~~~

ADDRESS DEVICE
1)
2)
3)
4)
5)

~~

ADDRESS DEVICE

SET RIW TO READ
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSERT ADDRESS STROBE (AS)
ASSERT UPPER DATA STROBE (UDS) AND
LOWER DATA STROBE (LOS)

1)
2)
3)
4)
5)

SET RIW TO READ
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSERT ADDRESS STROBE (AS)_
ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LOS) (BASED ON AO)

I

+

.1

INPUT DATA

INPUT DATA

1) DECODE ADDRESS
2) PLACE DATA ON 00-015
3) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)

,

1) DECODE ADDRESS
2) PLACE DATA ON 00-07 or 08-015 (BASED ON
UDS OR LOS)
3) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)

I

ACQUIRE DATA

ACQUIRE DATA

1) LATCH DATA
2) NEGATE UDS AND LOS
3) NEGATE AS

1) LATCH DATA
2) NEGATE UDS OR!LDS
3) NEGATE AS

•

+

TERMINATE CYCLE

TERMINATE CYCLE

1) REMOVE DATA FROM 00-015
2) NEGATE DlACK

1) REMOVE DATA FROM 00-015 OR 08-015
2) NEGATE DTACK

+

START NEXT CYCLE

Figure 4.

J

.1

START NEtT CYCLE

Figure 5.

Word Read Cycle Flow Chart

Byte Read Cycle Flow Chart

Figure 13 is a flow chart showing the detail involved in a request
from a single device. Figure 14 is a timing diagram for the same
operation. This technique allows processing of bus requests during data transfer cycles.

Read-Modify-Write Cycle. The read-modify-write cycle performs
a read, modifies the data in the arithmetic-logic unit, and writes
the data back to the same address. In the R68000 this cycle
is indivisible in that the address strobe is asserted throughout
the entire cycle. The test and set (TAS) instruction uses this cycle
to provide meaningful communication between processors in a
multiple processor environment. TAS is the only instruction that
uses the read-modify-write cycles. Since the test and set instruction only operates on bytes, all read-modify-write cycles are byte
operations. A read-modify-write cycle flow chart is given in
Figure 11 and a timing diagram is given in Figure 12.

The timing diagram shows that the bus request is negated at
the time that an acknowledge is asserted. This is true for a
system consisting of the processor and one device capable of
bus mastership. However, in systems having a number of
devices capable of bus mastership, the bus request line from
each device is ORed to the processor. In this system, it is easy
to see that there could be more than one bus request being
made. The timing diagram shows that the bus grant signals
negate a few clock cycles after the transition of the acknowledge
(BGACK) signal.

BUS ARBITRATION. Bus arbitration is a technique used by
master-type devices to request, be granted, and knowledge bus
mastership. In its simplest form, it consists of:
1. asserting a bus mastership request,
2. receiving a grant that the bus is available at the end of the
current cycle, and
3. acknowledging that mastership has been assumed.

However, if the bus requests are still pending, the processor will
assert another bus grant within a few clock cycles after negation. This additional assertion of bus grant allows external arbitration circuitry to select the next bus master before the current
bus master has completed its requirements. The following paragraphs provide additional information about the three steps in
the arbitration process.

1-10

R68000

16-Bit MPU

CLK

AS

\

UDS

\
\

LDS

H
H
\
/r----===~--~/
/

I

\I-_-,r---\
r------~\

R/W
DTACK

\

/

D8-D15

(
(

)

DO-D7
FCO-FC2

::x

\~

>-

____________~r-

rr-

r---\

\
r-----.:==~-----'/
\
/r----------\

r

)
)

)

>>-

X~_______~X~____________________~~

I..

I..

.. I..

READ ---~~---WRITE--~.....- - - - - - S L O W READ---.....~I

Figure 6.

Read and Write Cycle Timing Diagram

SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7

I
I
I

>--

H

H
I

I

\

\

I

\

I

;-----\

~
~

\

\

r--

DO-D7~~~~~~~~~~~~~~~~~~~~~~~~~~~~~====
::::x_______ X
X
>-)

(

)

FCO-FC2

)--

)

..J

·INTERNAL SIGNAL ONLY

f.--WORD READ-_*,"I--ODD BYTE READ
... 1 . .

Figure 7.

... 1 . .

EVEN BYTE REAO--..\

Word and Byte Read Cycle Timing Diagram
Receiving the Bus Grant. Normally the processor asserts bus
grant (BG) as soon as possible after internal synchronization. The
only exception occurs when the processor has made an internal decision to execute the next bus cycle but has not progressed
far enough into the cycle to have asserted the address strobe
(AS) signal. In this case, bus grant will not be asserted until one
clock after address strobe is asserted to indicate to external
devices that a bus cycle is being executed.

Requesting the Bus. External devices capable of becoming bus
masters request the bus by asserting the bus request (BR) signal.
This ORed signal (although it need not be constructed from open
collector devices) indicates to the processor that some external
device requires control of the external bus. The processor, at
a lower bus priority level than the external device, will relinquish
the bus after it has completed the last bus cycle it has started.
If no acknowledge is received before the bus request signal goes
inactive, the processor will continue processing when it detects
that the bus request is inactive. This allows ordinary processing
to continue if the arbitration circuitry inadvertently responded
to noise.

The bus grant signal may be routed through a daisy-chained
network or through a specific priority-encoded network. The processor is not affected by the external method of arbitration as
long as the protocol is obeyed.

1-11

II

R6S000

16-Bit MPU
BUS MASTER

Aiju"ES:>
1)
2)
3)
4)
5)
6)

SLAVE

1

ADDRESS DEVICE

UI:VI"'t:

PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSEI!!: ADDRESS STROBE (AS)
Set R/W TO WRITE
PLACE DATA ON DO-D15
ASSERT UPPER DATA STROBE (UDS) AND
LOWER DATA STROBE (LDS)

1)
2)
3)
4)

PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSERT ADDRESS STROBE (AS)
Set R/W TO WRITE
5) PLACE DATA ON DO-D7 or D8-D15 (ACCORDING
TO AO)
6) ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LDS) (BASED ON AO)'

,

--'-

INPUT DATA

INPUT DATA

1) DECODE ADDRESS
2) STORE DATA ON DO-D15
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)

1) DECODE ADDRESS
2) STORE DATA ON DO-D7 If LDS IS ASSERTED
STORE DATA ON D8-D15 IF UDS IS ASSERTED
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DT ACK)

I

t

TERMINATE OUTPUT TRANSFER
1)
2)
3)
4)

TERMINATE OUTPUT TRANSFER
1)
2)
3)
4)

t

NEGATE UDS OR LDS
NEGATE AS
REMOV.! DATA FROM DO-D7 OR D8-D15
SET R/W TO READ

~

TERMINATE CYCLE
1) NEGATE DTACK

TERMINATE CYCLE
1) NEGATE DTACK

I

•

START NEXT CYCLE

Figure 8_

J

i

NEGATE UDS AND LDS
NEGATE AS
REMOVE DATA FROM DO-D15
SET R/W TO READ

•

SLAVE

BUS MASTER
I

START NEXT CYCLE

Figure 9_

Word Write Cycle Flow Chart

Byte Write Cycle Flow Chart

SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO 51 S2 S3 54 S5 S6 57
CLK

AO"

AS=~==~------~(~==~~======~__~==~__~

UDS
LDS

I

\

---~,----!r---~

R/WJ\
DTACK
D8-D15
DO-D7
FCO-FC2

\

===>--<=~~~~~~~~~~~
====>---C
.J(.,.-______--'

"INTERNAL SIGNAL ONLY

~ WORD WRITE
Figure 10.

..

I..

ODD BYTE WRITE

_I"

EVEN BYTE WRITE--!

Word and Byte Write Cycle Timing Diagram

1-12

J

16-Bit MPU

R68000
BUS MASTER

SLAVE

•

ADDRESS DEVICE
1)
2)
3)
4)
5)

SET R/W TO READ
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23
ASSERT ADDRESS STROBE (AS)_
ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LOS)

INPUT DATA
1) DECODE ADDRESS
2) PLACE DATA ON 00-07 OR 08-015
3) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)

I

•

•

ACQUIRE DATA
1) LATCH DATA
2) NEGATE UDS OR LOS
3) START DATA MODIFICATION

TERMINATE CYCLE
1) REMOVE DATA FROM 00-07 OR 08-015
2i NEGATE DTACK

I

•

•

START OUTPUT TRANSFER

INPUT DATA
1) STORE DATA ON 00-07 OR 08-015
2) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)

1) SET RiW TO WRITE
2) PLACE DATA ON 00-07 or 08-015
3) ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LOS)

I

•

~

TERMINATE OUTPUT TRANSFER
1)
2)
3)
41

NEGATE UDS OR LOS
NEGATE AS
REMOVE DATA FROM 00-07 OR 08-015
SET RiW TO READ

TERMINATE CYCLE
1) NEGATE DTACK

,

I

START NEXT CYCLE

Figure 11.

Read-Modify-Write Cycle Flow Chart

""1
.
.
- - - - - - -

Figure 12.

INDIVISIBLE CYCLE

---------I~~I

Read-Modify-Write Cycle Timing Diagram

1-13

II

16-Bit MPU

R68000
PROCESSOR

The bus request from the granted device should be dropped after
bus grant acknowledge is asserted. If a bus request is still
penaing, anotner DUS grant wlil be asserted within a few clocks
of the negation of bus grant. Refer to Bus Arbitration Control
section. The processor does not perform any external bus cycles
before it reasserts bus grant.

REQUESTING DEVICE
REQUEST THE BUS

1) ASSERT BUS REQUEST (BR)

+

I

GRANT BUS ARBITRATION

I

1) ASSERT BUS GRANT (BG)

I

BUS ARBITRATION CONTROL. The bus arbitration control unit
in the R68000 is implemented with a finite state machine. A state
diagram of this machine is shown in Figure 15. All asynchronous
signals to the R68000 are synchronized before being used internally. This synchronization is accomplished in a maximum of
one cycle of the system clock, assuming that the asynchronous
input setup time (#47) has been met (see Figure 16). The input
signal is sampled on the falling edge of the clock and is valid
internally after the next falling edge. If BR and BGACK meet
the asynchronous set-up time tASI (#47), then tBGKBR (#37A)
can be ignored. If BR and BGACK are asserted asynchronously
with respect to the clock, BGACK has to be asserted before BR
is negated.

+

ACKNOWLEDGE BUS MASTERSHIP

1) EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE
3) NEXT BUS MASTER ASSERTS BUS
GRANT ACKNOWLEDGE (BGACK) TO
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR

,

I

I

TERMINATE ARBITRATION.

1) NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)

I

,

As shown in Figure 15, input signals labeled Rand A are internally synchronized on the bus request and bus grant
acknowledge pins respectively. The bus grant output is labeled
G and the internal three-state control signal T. If T is true, the
address, data, and control buses are placed in a high-impedance
state when AS is negated. All signals are shown in positive logic
(active high) regardless of their true active voltage level.

I

OPERATE AS BUS MASTER

1) PERFORM DATA TRANSFER (READ AND
WRITE CYCLEl?) ACCORDING TO THE
SAME RULES THE PROCESSOR USES.

State changes (valid outputs) occur on the next rising clock edge
after the internal signal is valid.

•

RELEASE BUS MASTERSHIP

1) NEGATE BGACK

I

+

RE-ARBITRATE OR RESUME
PROCESSOR OPERATION

Figure 13.

A timing diagram of the bus arbitration sequence during a
processor bus cycle is shown in Figure 17. The bus arbitration
sequence while the bus is inactive (i.e., executing internal operations such as a multiply instruction) is shown in Figure 18.

I

If a bus request (BR) is made at a time when the MPU has
already b~n a bus cycle but AS has not been asserted (bus
state SO), BG will not be asserted on the next rising edge. Instead
BG will be delayed until the second rising edge following its internal assertion. This sequence is shown in Figure 19.

Bus Arbitration Cycle Flow Chart

Acknowledgment of Mastership. Upon receiving a bus grant
(BG), the requesting device waits until address strobe (AS), data
transfer acknowledge (DTACK), and bus grant acknowledge
(BGACK) are negated before issuing its own BGACK. The negation of the address strobe indicates that the previous master has
completed its cycle, while the negation of bus grant acknowledge
indicates that the previous master has released the bus. (If
address strobe is asserted no device is allowed to "break into"
a cycle.) The negation of data transfer acknowledge indicates
the previous slave has terminated its connection to the previous
master. In some applications data transfer acknowledge may
not be required. In this case the devices would use the address
strobe. When bus grant acknowledge is issued the device is bus
master. Only after the bus cycle(s) is (are) completed should bus
grant acknowledge be negated to terminate bus mastership.

BUS ERROR AND HALT OPERATION. In a bus architecture
that requires a handshake from an external device, the possibility
exists that the handshake might not occur. Since different
systems will require a different maximum response time, a bus
error input is provided.
External circuitry must be used to determine the duration
between address strobe and data transfer acknowledge before
issuing a bus error signal. When a bus error signal is received,
the processor has two options: initiate a bus error exception
sequence or try running the bus cycle again.

1-14

16-Bit MPU

R68000

BG
BGACK

I

\
I

\

PROCESSOR~ DMA DEVICE

Figure 14.

I

\
I

\

\
~I·

PROCESSOR

~I·

DMA DEVICE

~

Bus Arbitration Cycle Timing Diagram

Ri\"

INTERNAL SIGNAL VALIDl
EXTERNAL SIGNAL],
SAMPLED
, ,
CLK
I

BGACK------------~

'THIS DELAY TIME IS EQUAL TO PARAMETER #33, ICHGL

Figure 16. Timing Relationship of External
Asynchronous Inputs to Internal Signals

RA

=
=
=
=

R
BUS REQUEST INTERNAL
A
BUS GRANT ACKNOWLEDGE INTERNAL
G = BUS GRANT
THREE·STATE CONTROL TO BUS CONTROL LOGIC2
T
X
DON'T CARE
1. STATE MACHINE WILL NOT CHANGE STATE IF BUS IS
IN SO OR S1. REFER TO BUS ARBITRATION CONTROL
FOR ADDITIONAL INFORMATION.
2. THE ADDRESS BUS WILL BE PLACED IN THE HIGH
IMPEDANCE STATE IF T IS ASSERTED AND AS·
NEGATED.

Figure 15.

Bus Error Operation. When BERR is asserted, the current bus
cycle is terminated. If BERR is asserted before the falling edge
of 52, A5 will be negated in 57 in either a read or write cycle.
As long as BERR remains asserted, the data and address buses
will be in the high-impedance state. When BERR is negated,
the processor Will begin stacking lor exception processing.
Figure 20 is a timing diagram for the exception sequence. The
sequence is composed of the following elements:
1. stacking the program counter and status register,
2. stacking the error information,
3. reading the bus error vector table entry, and
4. executing the bus error handler routine.

State Diagram of R68000 Bus
Arbitration Unit

1-15

16-Bit MPU

R68000

BUS THREE STATED--------,
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED

BUS RELEASED FROM THREE
STATE AND PROCESSOR
STARTS NEXT BUS CYCLE
BGACK NEGATED INTERNAL
BGACK SAMPLED
BGACK NEGATED

CLK

SO 51 52 S3 54 55 56 57 SO 51
BR
BG
BGACK

A1·A23
AS

UDS
LOS

\
PROCESSOR

•

-I-

Figure 17.

ALTERNATE BUS MASTER

-I-

PROCESSOR

•

Bus Arbitration During Processor Bus Cycle

BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE-----,
BGACKNEGATED _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--,
BG
BR
BR
BR

ASSERTED AND BUS THREE STATED----...,
VALID INTERNAL _ _ _ _ _ _ _---,
SAMPLED - - - - - - - - - - ,
ASSERTED---------:t..

CLK

SO 51 52 S3 54

50.51 525354555657
BR ________________

~\======~~I

BG

I

\

BGACK

\

/

'-----~

A1.A23:~:j~~========~~==========~~========================;=~(~~===
~
AS

UDS
LOS
FCO·FC2

\

/

\~----~/,---------~-------------------~

I

~

-:J..============})------------C====
\

~------------------~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ T - - - - - -

'--1

OTACK - - - -____

00·015 --===-::!-(=======)~:::-::=:::::_--_:::::==:_:;:_:::::::;:---_:::=::::::_
I.
I_
I
PROCESSOR

•

BUS INACTIVE _

Figure 18.

ALTERNATE BUS MASTER

Bus Arbitration with Bus Inactive

1·16

•

!ROCESSO~

16-Bit MPU

R6S000

BR ASSERTED
BR SAMPLED
BUS THREE S T A T E D l l
BG ASSERTED
BR VALID INTERNAL

BUS RELEASED FROM THREE
STATE AND PROCESSOR
STARTS NEXT BUS CYCLE - - - ,
BGACK NEGATED INTERNAL
BGACK SAMPLED - - - - - ,
BGACK NEGATED

SO Sl S2 S3 S4 S5 S6 S7 SO Sl

SO Sl S2 S3 S4 S5 S6 S7
BR
BG

II

'--..:========:::::;-______'1

\
1
BGACK------------~======~\======~__~I
A1-A23

\~________'f'------------'~~

f'
\'-______-'f'

FCO-FC2

R/W

-.I

~r____

___--'r____
~'-___--'r____

UDS --.lr---~\
LOS

;;====;>-e
____

==>--<2~:;====2)==-==---=----_:=~(

AS~

~'-

'C...

~
-1~--------------""""\.

__________________F-----------------

DTACK-~~
~~~~~{:=====~--~~~~~~----~\====~===r----=====
I ..
I.
..
..
00-015 -

__

PROCESSOR

Figure 19.

AS
LOS UDS

\~

..

ALTERNATE BUS MASTER

..

PROCESSOR

Bus Arbitration During Processor Bus Cycle Special Case

_____________________- J

\

R/W
DTACK------------------------------------

00-015
FCO-2

J=::::==~(~~~~~~~~;;;;;;;;;;;;;;;;;;;;;;;;C=j ~-~=======

BERR _________________________\~================~
HALT
I JNITIATi-I..
READ

RESPONSE FAILURE -.~j...I----BUS ERROR DETECTION _""'If+--"-IN;;;;..IT;c.IA;.;;.T;;.;;E;;..Bo;..U,,,SO~ "ERROR STACKING

Figure 20.

Bus Error Timing Diagram

1-17

16-Bit MPU

R68000

r!

The single-step mode, derived from correctly timed transitions
on the HALT signal input, forces the processor to execute a
single bus-cycle by entering the "run" mode until the processor
starts a bus cycle then changing to the "halt" mode. Thus, the
single-step mode allows the user to proceed through (and
therefore debug) processor operations one bus cycle at a time.

The stacking of the program counter and the status register is
identical to the interrupt sequence. Several additional items are
stacked when a bus error occurs. These items are used to determine the nature of the error and correct it, if possible. The bus
error vector is vector number two located at address $000008.
The processor loads the new program coumter from this location. A software bus error handler routine is then executed by
the processor. Refer to EXCEPTION PROCESSING for additional information.

Figure 22 details the timing required for correct single-step
operations. Some care must be exercised to avoid harmful interactions between BERR and HALT when using the single cycle
mode as a debugging tool. This is also true of interactions
between the HALT and RESET lines since these can reset the
machine.

Re-Running the Bus Cycle. When, during a bus cycle, the
processor receives a BERR, and HALT is being driven by an
external device, the processor enters the re-run sequence.
Figure 21 is a timing diagram for re-running the bus cycle.

When the processor completes a bus cycle after recognizing
that HALT is active, most three-state signals are put in the highimpedance state. These include:
1. address lines, and
2. data lines.

The processor terminates the bus cycle, then puts the address
and data output lines in the high-impedance state. The processor
remains "halted" and will not run another bus cycle until external logic negates HALT. Then the processor will re-run the
previous bus cycle using the same address, the same function
codes, the same data (for a write operation), and the same controls. BERR should be negated at least one clock cycle before
HALT is negated.

This is required for correct performance of the re-run bus cycle
operation.
Honoring the halt request has no effect on bus arbitration. Only
the bus arbitration function removes the control signals from the
bus.

Note
The processor will not re-run a read-modify-write cycle.
This restriction is made to guarantee that the entire cycle
runs correctly and that the write operation of a Test-andSet operation is performed without ever releasing AS. If
BERR and HALT are asserted during a read-modify-write
bus cycle, a bus error operation results.

Total debugging flexibility is derived from the software debugging
package, the halt function, and the hardware trace capability.
These processor capabilities allow the hardware debugger to
trace single bus cycles or single instructions at a time.
Double Bus Faults. When a bus error exception occurs, the
processor will attempt to stack several words containing information about the state of the machine. If a bus error exception
occurs during the stacking operation, there have been two bus
errors in a row, or a double bus fault. A double bus fault causes
the processor to halt. Once a bus error exception has occurred,
any bus error exception occurring before the execution of the
next instruction constitutes a double bus fault.

Halt Operation with No Bus Error. The HALT input signal to
the R68000 performs a HaltlRun/Single-Step function in a similar
fashion to the R6500 halt functions. When the HALT signal is
constantly active the processor "halts" (does nothing) and when
the HALT signal is constantly inactive the processor "runs"
(does something).

l

\ ....._ _ _..J
~-------------,\

I~--

)
:;===~;;;;~====================j\~.~~~r-­

(~

==~~____~X~======================~~~

~---------;t:>'CU>C""DD:;fk~-------------------------------10(
Figure 21.

H A L T - - - - -...""!o(_--RE-RUN--~.I

Re-Run Bus Cycle Timing Diagram

1-18

R68000

16-Bit MPU

\.....___...J!

'---_____!

/r----------~\

~

!~----

________J!
------~·~I~·~-------HALT--------~·+I·.------READ-----4~~1
Figure 22.

Halt Signal Timing Waveforms

THE RELATIONSHIP OF DTACK, BERR, AND
HALT

Note that a bus cycle which is re-run does not constitute a bus
error exception, and does not contribute to a double bus fault.
This means that as long as the external hardware requests it,
the processor will continue to re-run the same bus cycle.

In order to properly control termination of a bus cycle for are-run
or a bus error condition, DTACK, BERR, and HALT should be
asserted and negated on the rising edge of R68000 clock. This
will assure that when two signals are asserted simultaneously,
the required setup time (#47) for both of them will be met during
the same bus state.

The bus error (BERR) pin also has an effect on processor operation after the processor receives an external reset input. The
processor reads the vector table after a reset to determine the
address to start program execution. If a bus error occurs while
reading the vector table (or at any time before the first instruction is executed), the processor reacts as if a double bus fault
has occurred and it halts. Only an external reset will start a halted
processor.

This, or some equivalent precaution, should be designed external to the R68000. Parameter #48 is intended to ensure thiS
operation in a totally asynchronous system, and may be ignored
if the above conditions are met.

RESET OPERATION. The reset signal is a bidirectional signal
that allows either the processor or an external signal to reset
the system. Figure 23 is a timing diagram for reset operations.
Both HALT and RESET must be applied to ensure total reset
of the processor.

The preferred bus cycle terminations may be summarized as
follows (case numbers refer to Table 4):
Normal Termination: DTACK occurs first (case 1).
Halt Termination: HALT is asserted at same time, or precedes
DTACK (no BERR) cases 2 and 3.

When the RESET and HALT are driven by an external device
the entire system, including the processor, is reset. The
processor responds by reading the reset vector table entry (vector number zero, address $000000) and loads it into the supervisor stack pointer (SSP). Vector table entry number one at
address $000004 is read next and loaded into the program
counter. The processor initializes the status register to an interrupt level of seven, with no other register being affected.

Bus Error Termination: BERR is asserted in lieu of, at same
time, or preceding DTACK (case 4); BERR negated at same
time, or after DTACK.
Re-Run Termination: HALT and BERR asserted in lieu of, at
the same time, or before DTACK (cases 6 and 7); HALT must
be negated at least one cycle after BERR. (Case 5 indicates
BERR may precede HALT which allows fully asynchronous
assertion).

Execution of the RESET instruction drives the reset pin low for
124 clock periods. In this case, the processor is trying to reset
the rest of the system. The internal state of the processor, including the processor's internal registers and the status register, is
unaffected by the execution of a RESET instruction. All external
devices connected to the reset !ine 'Ni!! be reset at the CGrr.p!~>
tion of the RESET instruction.

Table 4 details the resulting bus cycle termination under various
combinations of control signal sequences. The negation of these
same control signals under several conditions is shown in
Table 5. (DTACK is assumed to be negated normally in ali
cases; for best results, both DTACK and BERR should be
negated when address strobe is negated).

Asserting RESET and HALT for 10 clock cycles will cause a
processor reset, except when Vcc is initially applied to the
processor. In this case, an external reset must be applied for
100 milliseconds.

Example A: A system uses a watCh-dog timer to terminate
accesses to unpopulated address space. The timer asserts
DTACK and BERR simultaneously after timeout (case 4).

1-19

II

R68000

16-Bit MPU

CLK
PLUS 5 VOLTS

VCC
RESET
HALT

1'-____________-'
1---11

BUS CYCLES

< 4 CLOCKS

xxxx~~xx¢¢~xr----------~----<_

__)(~:x==~c===x==
2

NOTES:
1) INTERNAL START-UP TIME
2) SSP HIGH READ IN HERE
3) SSP LOW READ IN HERE
4) PC HIGH READ IN HERE

5) PC LOW READ IN HERE
6) FIRST INSTRUCTION FETCHED HERE.

Figure 23.

3

4

5

Y:;<:;J:fX

>----<

6

BUS STATE UNKNOWN (ALL
CONTROL SIGNALS INACTIVE)
DATA BUS IN READ MODE

Reset Operation Timing Diagram

Example B: A system uses error detection on RAM contents.
Designer may (a) delay DTACK until data verified, and return
BERR and HALT simultaneously to re-run error cycle (case 6),
or if valid, return DTACK (case 1); (b) delay DTACK until data
verified and return BERR at same time as DTACK if data in
error (case 4).

The BERR signal is allowed to be asserted after the DTACK
signal is asserted. BERR must be asserted within the time given
as parameter #48 after DTACK is asserted in any asynchronous
system to insure proper operation. If this maximum delay time
is violated, the processor may exhibit erratic behavior.

Synchronous Operation
To allow for those systems which use the system clock as a
signal to generate DTACK and other asynchronous inputs, the
asynchronous inputs setup time is given as parameter #47. If
this setup is met on an input, such as DTACK, the processor is
guaranteed to recognize that signal on the next falling edge of
the system clock. However, the converse is not true-if the input
signal does not meet the setup time it is not guaranteed not to
be recognized. In addition, if DTACK is recognized on a falling
edge, valid data will be latched into the processor (on a read
cycle) on the next falling edge provided that the data meets the
setup time given as parameter #27. Given this, parameter #31
may be ignored. Note that if DTACK is asserted, with the required
setup time, before the falling edge of S4, no wait states will be
incurred and the bus cycle will run at its maximum speed of four
clock periods.

ASYNCHRONOUS VERSUS SYNCHRONOUS
OPERATION
Asynchronous Operation
To achieve clock frequency independence at a system level, the
R68000 can be used in an asynchronous manner. This entails
using only the bus handshake lines (AS, UDS, LDS, DTACK,
BERR, HALT, and VPA) to control the data transfer. Using this
method, AS signals the start of a bus cycle and the data strobes
are used as a condition for valid data on a write cycle. The slave
device (memory or peripheral) then responds by placing the
requested data on the data bus for a read cycle or latching data
on a write cycle and asserting the data transfer acknowledge
signal (DTACK) to terminate the bus cycle. If no slave reponds
or the access is invalid, external control logic asserts the BERR,
or BERR and HALT, signal to abort or rerun the bus cycle.

In order to assure proper operation in a synchronous system
when BERR is asserted after DTACK, the following conditions
must be met. Within one clock cycle after DTACK was recognized, BERR must meet the setup time parameter #27A prior
to the falling edge of the next clock. The setup time is critical
to proper operation, and the R68000 may exhibit erratic behavior
if it is violated.

The DTACK signal is allowed to be asserted before the data from
a slave device is valid on a read cycle. The length of time that
DTACK may precede data is given as parameter #31 (See
Figure 45) and it must be met in any asynchronous system to
insure that valid data is latched into the processor. Notice that
there is no maximum time specified from the assertion of AS
to the .\lssertion of DTACK. ThiS IS because the MPU
will inse"ri wait cycles of one clock period each until DTACK is
recognized.

Note
During an active bus cycle, VPA and BERR are sampled
on every falling edge of the clock starting with SO. DTACK
is sampled on every falling edge of the clock starting with
S4 and data is latched on the falling edge of S6 during
a read. The bus cycle will then be terminated in S7 except
when BERR is asserted in the absence of DTACK, in
which case it will terminate one clock cycle later in S9.

1-20

~6-Bit

R6S000
Table 4.

MPU

DTACK, BERR, HALT Assertion Results

II

Asserted on Rising
Edge of State
Case
No.

Control
Signal

N

1

DTACK
BERR
HALT

A
NA
NA

2

DTACK
BERR
HALT

A
NA
A

8

NA
NA
A

A
NA
8

-DTACK
BERR
HALT

3

N + 2
8

Normal cycle terminate and continue.

8

-Normal cycle terminate and halt Continue when HALT removed.

X

DTACK
BERR
HALT

X

X

A
NA

8
NA

5

DTACK
BERR
HALT

NA
A
NA

8
A

7

Legend.
N A NA X 8 -

-Normal cycle terminate and halt Continue when HALT removed

Terminate and take bus error trap

X

DTACK

X

X

BERR
HALT

A
A

8
8

DTACK
BERR
HALT

NA
NA
A

A
8

Terminate and re-run

-Terminate and re-run when HALT removed

X

--

Terminate and re-run when HALT removed

the number of the current even bus state (e g., 84, 86, etc.)
signal IS asserted In this bus state
signal IS not asserted In this state
don't care
signal was asserted In previous state and remains asserted in this state

Table 5.

Conditions of
Termination in
Table 4-4

•

X
X

4

6

Result

BERR AND HALT Negation Results

Negated on Rising
Edge of State
Control
Signal

Bus Error

BERR
HALT

Re-run

BERR
HALT

Re-run

BERR
HALT

Normal

BERR
HALT

Normal

BERR
HALT

N

•
•
•
•
•
•
•
•

N+2
or
or

•
•

or

•

Results -

Next Cycle

Takes bus error trap.
Illegal sequence; usually traps to vector number 0

•

Re-runs the bus cycle.

or

•

May lengthen next cycle.

or

none

•

= 8ignal is negated in this bus state

1-21

If next cycle is started it will be terminated as a bus error.

16-Bit MPU

R68000

All exception proceSSing is done in the supervisor state,
regardless of the setting of the S-bit. The bus cycles generated
during exception processing are classified as supervisor
references. All stacking operations during exception proceSSing
use the supervisor stack pointer.

PROCESSING STATES
The following paragr~phs describe the actions of the R6S000
which are outside the normal processing associated with the
execution of instructions. The functions of the bits in the supervisor portion of the status register are covered: the supervisor/user bit, the trace enable bit, and the processor interrupt
priority mask. The sequence of memory references and actions
taken by the processor on exception conditions are detailed.

USER STATE. The user state is the lower state of privilege. For
instruction execution, the user state is determined by negating
(low) the S-bit of the status register.

The R6S000 is always in one of three processing states: normal, exception, or halted. The normal processing state
associated with instruction execution; the memory references
are to fetch instructions and operands, and to store results. A
special case of the normal state is the stopped state which the
processor enters when a STOP instruction is executed. In this
state, no further references are made.

Most instructions execute the same in user state as in the supervisor state. However, some instructions which have important
system effects are made privileged. User programs are not permitted to execute the STOP instruction, or the RESET instruction. To ensure that a user program cannot enter the supervisor
state except in a controlled manner, the instructions which
modify the whole state register are priviled. To aid in debugging
programs which are to be used as operating systems, the move
to user stack pointer (MOVE to USP) and move from user stack
pOinter (MOVE from USP) instructions are also privileged.

The exception processing state is associated with interrupts, trap
instructions, tracing and other exceptional conditions. The
exception may be internally generated by an instruction or by
an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, by a bus error, or by a reset. Exception processing is
designed to provide an efficient context IIwitch so that the
processor may handle unusual conditions.

The bus cycles generated by an instruction executed in user
state are classified as user state references. This allows an external memory management device to translate the address and
to control access to protected portions of the address space.
While the processor is in user privilege state, those instructions
which use either the system stack pointer implicitly or address
register seven explicitly, access the user stack pointer.

The halted processing state is an indication of a catastrophic
hardware failure. For example, if during the exception processing
of a bus error another bus error occurs, the processor assumes
that the system is unusable and halts. Only an external reset
can restart a halted processor. Note that a processor in the
stopped state Is not In the halted state, nor vice versa.

PRIVILEGE STATE CHANGES. Once the processor is in the
user state and executing instructions, only exception processing
can change the privilege state. During exception processing,
the current setting of the S-bit of the status register is saved and
the S-bit is asserted, putting the processing in the supervisor
state. Therefore, when instruction execution resumes to process
the exception, the processor is in the supervisor privilege state.

PRIVILEGE STATES
The processor operates in one of two states of privilege: the
"user" state or the "supervisor" state. The privilege state determines legal operations. It is used to choose between the supervisor stack pointer and the user stack pointer in instruction
references, and by the external memory management device
to control and translate accesses.

REFERENCE CLASSIFICATION. When the processor makes
a reference, it classifies the kind of reference being made by
using the encoding on the three function code output lines. This
allows external translation of addresses, control of access, and
differentiation of special processor states, such as interrupt
acknowledge. Table 6 lists the classification of references.

The privilege state is a mechanism for providing security in a
computer system by allowing most programs to execute in user
state. In this state, the accesses are controlled, and the effects
on other parts of the system are limited. Programs should access
only their own code and data areas, and ought to be restricted
from accessing information.

Table 6.

Reference Classification

Function Code Output
FC2

The operating system which executes in the supervisor state,
has access to all resources and performs the overhead tasks
for the user state programs.
SUPERVISOR STATE. The supervisor state is the higher state
of privilege. For instruction execution, the supervisor state is
determined by asserting (high) the S-bit of the status register.
All instructions can be executed in the supervisor state. The bus
cycles' generated by instructions executed in the supervisor state
are classified as supervisor references. While the processor is
in the supervisor privilege state, those instructions which use
either the system stack pointer implicitly or address register
seven explicitly access the supervisor stack pointer.

1-22

FC1

FCD

Reference Class

0

0

0

(Unassigned)

0

0

1

User Data

0

1

0

User Program

0

1

1

(Unassigned)

1

0

0

(Unassigned)

1

0

1

Supervisor Data

1

1

0

Supervisor Program

1

1

1

Interrupt Acknowledge

R6S000

16-Bit MPU

WORD 0

NEW PROGRAM COUNTER (HIGH)

AO=O, Al =0

WORD 1

NEW PROGRAM COUNTER (LOW)

AO=O,Al=l

Figure 24.

Exception Vector Format

D15

D8 D7

DO

IGNORED

WHERE:
v7 IS THE MSB OF THE VECTOR NUMBER
vO IS THE LSB OF THE VECTOR NUMBER

Figure 25.

Peripheral Vector Number Format

A23

Al0 A9 A8 A7 A6

AS

A4 A3

A2 Al

AO

ALL ZEROES

Figure 26.

Address Translated From 8-Bit Vector Number

EXCEPTION PROCESSING

address 1023. This provides 255 unique vectors; some of these
are reserved for TRAPS and other system functions. Of the 255,
there are 192 reserved for user interrupt vectors. However, there
is no protection on the first 64 entries, so user interrupt vectors
may overlap at the discretion of the systems designer.

Before discussing the details of interrupts, traps, and tracing,
a general description of exception processing is in order. The
processing of an exception occurs in four steps, with variations
for different exception causes. During the first step, a temporary
copy of the status register is made, and the status register is
set for exception processing. In the second step the exception
vector is determined, and the third step is the saving of the cur·
rent processor contents. In the fourth step a new context is
obtained, and the processor switches to instruction processing.

KINDS OF EXCEPTIONS. Exceptions can be generated either
internally or externally. Externally generated exceptions include
interrupts (IRQ), bus error (BERR), and reset (RESET) requests.
Interrupts are requests from peripheral devices for processor
action while BERR and RESET inputs are used for access control and processor restart. Internally generated exceptions come
from instructions, from address errors, or from traCing. The trap
(TRAP), trap on overflow (TRAPV), check register against bounds
(CHK) and divide (OIV) instructions can all generate exceptions
as part of their instruction execution. In addition, illegal instructions, word fetches from odd addresses and privilege violations
cause exceptions. TraCing behaves like a very high priority, internally generated interrupt after each instruction execution.

EXCEPTION VECTORS. Exception vectors are memory locations from which the processor fetches the address of a routine
which will handle that exception. All exception vectors are two
words in length (Figure 24), except for the reset vector, which
is four words. All exception vectors lie in the supervisor data
space, except for the reset vector which is in the supervisor program space. A vector number is an eight-bit number which, when
multipled by four, gives the address of an exception vector. Vector numbers are generated internally or externally, depending
on the cause of the exception. In the case of interrupts, during
the interrupt acknowledge bus cycle, a peripheral provides an
8-bit vector number (Figure 25) to the processor on data bus lines
DO through 07. The processor translates the vector number into
a full 24-bit address, as shown in Figure 26. The memory layout
for exception vectors is given in Table 7.

EXCEPTION PROCESSING SEQUENCE. Exception processing
occurs in four identifiable steps. In the first step, an internal copy
is made of the status register. After the copy is made, the S-bit
is asserted, putting the processor into the supervisor privilege
state. Also, the T-bit is negated which will allow the exception
handler to execute unhindered by tracing. For the reset and interrupt exceptions, the interrupt priority mask is also updated.

As shown in Table 7, the memory layout is 512 words long
(1024 bytes). It starts at address 0 and proceeds through

1-23

16·Bit MPU

R6S000
Table 7.

Exception Vector Assignment
Address

Vector
Number(s)
0

2

Assignment

Dec

Hex

Space

a

000

SP

Reset: 1000Iai SSP

4

004

SP

Reset: 1000Iai PC

8

008

SO

Bus Error
Address Error

3

12

DOC

SO

4

16

010

SO

Illegal InstructIon

5

20

014

SO

Zero Oivlde

6

24

018

SO

CHK Instruction

7

28

01C

SO

TRAPV InstructIon

8

32

020

SO

PrivIlege VIolation

9

36

024

SO

Trace

10

40

028

SO

Line 1010 Emulator

11

44

02C

SO

Line 1111 Emulator

12"

48

030

SO

(UnassIgned, reserved)

13"

52

034

SO

(Unassigned, reserved)

14"

56

038

SO

(UnassIgned, reserved)

15

60

03C

SO

Un initIalIzed Interrupt Vector

64

04C

SO

(UnassIgned, reserved)

16-23"

-

95

05F

24

96

060

SO

Spurious Interrupt

25

100

064

SO

Levell Interrupt Autovector

26

104

068

SO

Level 2 Interrupt Autovector

27

108

06C

SO

Level 3 Interrupt Autovector

28

112

070

SO

Level 4 Interrupt Autovector

29

116

074

SO

Level 5 Interrupt Autovector

30

120

078

SO

Level 6 Interrupt Autovector

31

124

07C

SO

Level 7 Interrupt Autovector

32·47

128

080

SO

TRAP Instruction Vectors

191

OBF

192

OCO

SO

(UnassIgned, reserved)

255

OFF

256

100

SO

User Interrupt Vectors

1023

3FF

48-63"

64·255

-

"Vector numbers 12, 13, 14, 16 through 23, and 48 through 63 are reserved for future enhancements. No user peripheral devices should be assIgned
these numbers

1-24

R6S000

SSP...-

16·Bit MPU

STATUS REGISTE':'I
HIGH
I-PROGRAM COUNTER- - - - - -

Table 8.

1

Group

a

HIGHER
ADDRESSES

LOW

Figure 27.

1

Exception Stack Order (Groups 1 and 2)
2

In the second step, the vector number of the exception is deter·
mined. For interrupts, the vector number is obtained by a
processor fetch, classified as an interrupt acknowledge. For all
other exceptions, internal logic provides the vector number. This
vector number is then used to generate the address of the exception vector.

Exception Grouping and Priority

Exception

Processing

Reset
Address Error
Bus Error

Exception processing begins
within two clock cycles.

Trace
Interrupt
Illegal Instruction
Privilege Violation

Exception processing begins
before the next instruction.

TRAP, TRAPV, CHK,
Zero Divide

Exception processing is started
by normal instrucllon execution

The priority relation between two exceptions determines which
is taken first if the conditions for both arise simultaneously.
Therefore, if a bus error occurs during a TRAP instruction, the
bus error takes precedence, and the TRAP instruction processing is aborted. In another example, if an interrupt request
occurs during the execution of an instruction while the T-bit is
asserted, the trace exception has priority, and is processed first.
Before instruction processing resumes, however, the interrupt
exception is also processed, and instruction processing commences finally in the interrupt handler routine. Table 8 gives a
summary of exception grouping and priority.

The third step is to save the current processor status except for
the reset exception. The current program counter value and the
saved copy of the status register are stacked using the supervisor stack pointer as shown in Figure 27. The program counter
value stacked usually points to the next unexecuted instruction;
however, for bus error and address error, the value stacked for
the program counter is unpredictable, and may be incremented
from the address of the instruction which caused the error. Additional information defining the current context is stacked for the
bus error and address error exceptions.
The last step is the same for all exceptions. The new program
counter value is fetched from the exception vector. The
processor then resumes instruction execution. The instruction
at the address given in the exception vector is fetched, and
normal instruction decoding and execution is started.

EXCEPTION PROCESSING DETAILED DISCUSSION
Exceptions have a number of sources, and each exception has
a unique processing sequence. The following paragraphs detail
the sources of exceptions, how each arises, and how each is
processed.

MULTIPLE EXCEPTIONS. These paragraphs describe the processing which occurs when multiple exceptions arise
simultaneously. Exceptions can be grouped according to their
occurrence and priority. The Group 0 exceptions are reset, bus
error, and address error. These exceptions cause the instruction currently being executed to be aborted, and the exception
processing to commence within two clock cycles. The Group 1
exceptions are trace and interrupt, as well as the privilege violations and illegal instructions. These exceptions allow the current instruction to execute to completion, but preempt the execution of the next instruction by forcing exception processing to
occur (privilege violations and illegal instructions are detected
when they are the next instruction to be executed). The Group 2
exceptions occur as part of the normal processing of instructions. The TRAP, TRAPV, CHK, and zero divide exceptions are
In this group. For these exceptions, the normal execution of an
instruction may lead to exception processing.

RESET. The reset input provides the highest exception level.
The processing of the reset signal is designed for system initiation, and recovery from catastrophic failure. Any processing in
progress at the time of the reset is aborted and cannot be
recovered. The processor is forced into the supervisor state and
the trace state is forced off. The processor interrupt priority mask
is set at level seven. The vector number is Internally generated
to reference the reset exception vector at location 0 In the supervisor program space. Because no assumptions can be made
about the validity of register contents, in particular the supervisor stack pOinter, neither the program counter nor the status
register is saved. The address contained in the first two words
of the reset exception vector is fetched as the initial supervisor
stack pointer, and the address in the last two words of the reset
exception vector is fetched as the initial program counter. Finally,
Instruction execution is started at the address in the program
,..nllni"" Thq rowerup/restart code should be pointed to bv the
initial program counter.

Group 0 exceptions have highest priority, 'NI'i1e Group '.? ev<:,~p­
tions have lowest priority. Within Group 0, reset has highest
priority, followed by address error and then bus error. Within
Group 1, trace has priority over external interrupts, which in turn
takes priority over illegal instruction and privilege violation. Since
only one instruction can be executed at a time, there is no priority
relation within Group 2.

The RESET instruction does not cause loading of the reset vector, but does assert the reset line to reset external devices. This
allows the software to reset the system to a known state and
then continue processing with the next Instruction.

1-25

R6S000

16-Bit MPU

INTERRUPTS. Seven levels of interrupt priorities are provided.
Devices may be chained externally within interrupt priority levels,
allowing an unlimited number of peripheral devices to interrupt
the processor. Interrupt priority levels are numbered from one
to seven, level seven being the highest priority. The status
register contains a three·bit mask which indicates the current
processor priority. Interrupts are inhibited for all priority levels
less than or equal to the current processor priority.

INTERRUPTING DEVICE

PROCESSOR

REQUEST INTERRUPT

•

GRANT INTERRUPT
1) COMPARE INTERRUPT LEVEL IN STATUS
REGISTER AND WAIT FOR CURRENT
INSTRUCTION TO COMPLETE
2) PLACE INTERRUPT LEVEL ON A1, A2, A3
3) SET FUNCTION CODE TO INTERRUPT
ACKNOWLEDGE
4) ASSERT ADDRESS STROB~S)
5) ASSERT DATA STROBES (LDS AND UDS*)

An interrupt request is made to the processor by encoding the
interrupt request level on the interrupt request lines; a zero indicates no interrupt request. Interrupt requests arriving at the
processor do not face immediate exception processing, but are
made pending. Pending interrupts are detected between instruction executions. If the priority of the pending interrupt is lower
than or equal to the current processor priority, execution continues with the next instruction and the interrupt exception
processing is postponed. (The recognition of level seven is
slightly different, as explained in a following paragraph.)

•

PROVIDE VECTOR NUMBER
1) PLACE VECTOR NUMBER OF DO·D7
2) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)

,

If the priority of the pending interrupt is greater than the current
processor priority, the exception processing sequence is started.
First a copy of the status register is saved, and the privilege state
is set to supervisor, then traCing is suppressed, and the
processor priority level is set to the level of the interrupt being
acknowledged. The processor fetches the vector number from
the interrupting device, classifying the reference as an interrupt
acknowledge and displaying the level number of the interrupt
being acknowledged on the address bus. If external logic
requests an automatic vectoring, the processor internally
generates a vector number which is determined by the interrupt
level number. If external logic indicates a bus error, the interrupt is taken to be spurious, and the generated vector number
references the spurious interrupt vector. The processor then proceeds with the usual exception processing, saving the program
counter and status register on the supervisor stack. The saved
value of the program counter is the address of the instruction
which would have been executed had the interrupt not been
present. The content of the interrupt vector whose vector number
was previously obtained is fetched and loaded into the program
counter, and normal instruction execution commences in the
interrupt handling routine. A flow chart for the interrupt
acknowledge sequence is given in Figure 28, a timing diagram
is given in Figure 29, and the interrupt exception timing
sequence is shown in Figure 30.

ACQUIRE VECTOR NUMBER
1) LATCH VECTOR NUMBER
2) NEGATE LDS AND UDS
3) NEGATE AS

;
RELEASE
1) NEGATE DTACK

•

START INTERRUPT PROCESSING
* ALTHOUGH A VECTOR NUMBER IS ONE BYTE, BOTH
DATA STROBES ARE ASSERTED DUE TO THE
MICROCODE USED FOR EXCEPTION PROCESSING. THE
PROCESSOR DOES NOT RECOGNIZE ANYTHING ON
DATA LINES D8 THROUGH D15 AT THE TIME.

Figure 28.

Priority level seven is a special case. Level seven interrupts cannot be inhibited by the interrupt priority mask, thus providing
a "non-maskable interrupt" capability. An interrupt is generated
each time the interrupt request level changes from some lower
level to level seven. Note that a level seven interrupt may still
be caused by the level comparison if the request level is a seven
and the processor priority is set to a lower level by an instruction.

Interrupt Acknowledge Sequence Flow Chart

SPURIOUS INTERRUPT. If during the interrupt acknowledge
cycle no device responds by asserting DTACK or VPA, the bus
error line should be asserted to terminate the vector acquisition.
The processor separates the processing of this error from bus
error by fetching the spurious interrupt vector instead of the bus
error vector. The processor then proceeds with the usual exception processing.

UNINITIALIZED INTERRUPT. An interrupting device asserts
VPA or provides an interrupt vector during an interrupt
acknowledge cycle to the R68000. If the vector register has not
been initialized, the responding R68000 Family peripheral will
provide vector 15, the uninitialized interrupt vector. This provides
a uniform way to recover from a programming error.

INSTRUCTION TRAPS. Traps are exceptions caused by instructions. They arise either from processor recognition of abnormal
conditions during instruction execution, or from use of instructions whose normal behavior is trapping.

1-26

\

R6S000

\

16-Bit MPU

CLK

A1·A3

=>-<=~

II

___-;..._~:-~~______--:.

AS

UDS.~~----~

\~_ _ _ _ _ _ _ _~r---\~__~r-

,-_--1\,-_ _""""\

LDS ____;=======~~ r -__~============~
R/W
\

7 "-l
DTACK---~\~~~~~~~
08·015
00·07
FCO·FC2

__ \

~~----J

\~______~/~--~\------

(

---.("(,--=--=--=--=--=--=~

:=x:

IPLO·IPL2

(~

(~

----(--

~r-----------------~X-

I
~.,.·

LAST BUS CYCLE
STACK
OF INSTRUCTION
PCL
lACK CYCLE
STACK AND
(READ OR ..... ...
,.I--...,:(S:-:S;::P:,..)
NUMBER ACQUISITION)+ VECTOR FETCH-.I
WRITE)
-I
·ALTHOUGH A VECTOR NUMBER IS ONE BYTE, BOTH DATA STROBES ARE ASSERTED DUE TO THE MICROCODE USED
FOR EXCEPTION PROCESSING. THE PROCESSOR DOES NOT RECOGNIZE ANYTHING ON DATA LINES DB THROUGH 015
AT THIS TIME.

~

Figure 29.

LAST BUS CYCLE
OF INSTRUCTION
(DURING WHICH
INTERRUPT WAS
RECOGNIZED)

~

STACK
PCL
(AT SSP·2)

~

READ
VECTOR
HIGH
(A16·A23)

-"~--II"'''''(VECTOR

Interrupt Acknowledge Sequence Timing Diagram

1I

lACK

CYCLE
(VECTOR NUMBER ~
ACQUISITION)

---.

Figure 30.

READ
VECTOR
LOW
(AO·A15)

---.

STACK
STATUS
(AT SSP·6)

FETCH FIRST
WORD OF
INSTRUCTION
OF INTERRUPT
ROUTINE

Interrupt Exception Timing Sequence

1·27

---.

STACK
PCH
(AT SSP·4)

r---

NOTE:
SSP REFERS TO THE
VALUE OR THE SUPER·
VISOR STACK POINTER
BEFORE THE INTERRUPT
OCCURS

R68000

16·Bit MPU

Some instructions are used specifically to generate traps. The
TRAP instruction always forces an exception, and is useful for
implementing system calls for user programs. The TRAPV and
CHK instructions force an exception if the user program detects
a runtime error, which may be an arithmetic overflow or a
subscript out of bounds.

is pending on completion, the trace exception is processed
before the interrupt exception. If, during the execution of the
instruction, an exception is forced by that instruction, the forced
exception is processed before the trace exception.

The signed divide (DIVS) and unsigned divide (DIVU) instructions will force an exception if a division operation is attempted
with a divisor of zero.

As an extreme illustration of the above rules, consider the arrival
of an interrupt during the execution of a TRAP instruction while
tracing is enabled. First the trap exception is processed, then
the trace exception, and finally the interrupt exception. Instruction execution resumes in the interrupt handler routine.

ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS. Illegal

BUS ERROR. Bus error exceptions occur when the external logic
requests that a bus error be processed by an exception. The
current bus cycle which the processor is making is then aborted.
Whether the processor was doing instruction or exception
processing, that processing is terminated, and the processor
immediately begins exception processing.

instruction refers to any of the word bit patterns which are not
the bit pattern of the first word of a legal instruction. During
instruction execution, if such an instruction is fetched, an illegal
instruction exception occurs. Rockwell reserves the right to
define instructions whose opcodes may be any of the illegal
instructions. Three bit patterns will always force an illegal instruction trap on all R68000 Family compatible microprocessors. They
are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA
and $4AFB. are reserved for Rockwell system products. The third
pattern, $4AFC, is reserved for customer use.

Exception processing for bus error follows the usual sequence
of steps. The status register is copied, the supervisor state is
entered, and the trace state is turned off. The vector number
is generated to refer to the bus error vector. Since the processor
was not between instructions when the bus error exception
request was made, the context of the processor is more detailed.
To save more of this context, additional information is saved on
the supervisor stack. The program counter and the copy of the
status register are of course saved. The value saved for the program counter is advanced by some amount, two to ten by1es
beyond the address of the first word of the instruction which
made the reference causing the bus error. If the bus error
occurred during the fetch of the next instruction, the saved program counter has a value in the vicinity of the current instruction, even if the current instruction is a branch, a jump, or'a return
instruction. Besides the usual information, the processor saves
its internal copy of the first word of the instruction being
processed, and the address which was being accessed by the
aborted bus cycle. Specific information about the access is also
saved: whether it was a read or a write, whether the processor
was processing an instruction or not, and the classification
displayed on the function code outputs when the bus error
occurred. The processor is processing an instruction if in the
normal state or processing a Group 2 exception; the processor
is not processing an instruction when processing a Group 0 or
a Group 1 exception. Figure 31 illustates how the information
is organized on the supervisor stack. Although this information
is not sufficient to effect full recovery from the bus error, it does
allow software diagnosis. Finally, the processor commences
instruction processing at the address contained in the vector.
It Is the responsibility of the error handler routine to clean up
the stack and determine where to continue execution.

Word patterns with bits 15 through 12 equaling 1010 or 1111
are distinguished as unimpiemented instructions and separate
exception vectors are given to these patterns to permit efficient
emulation. This facility allows the operating system to detect program errors, or to emulate unimplemented instructions in
software.

PRIVILEGE VIOLATIONS. In order to provide system security,
various instructions are privileged. An attempt to execute one
of the privileged instructions while in the user state will cause
an exception. The privileged instructions are:
STOP
AND Immediate to SR
RESET
EOR Immediate to SR
RTE
OR Immediate to SR
MOVE USP
MOVE to SR
TRACING. To aid in program development, the R68000 includes
a facility to allow instruction by instruction tracing. In the trace
state, after each instruction is executed an exeception is forced,
allowing a debugging program to monitor the execution of the
program under test.
The trace facility uses the T-bit in the supervisor portion of the
status register. If the T-blt is negated (off), tracing is disabled,
and instruction execution proceeds from instruction to instruction as normal. If the T-bit is asserted (on) at the beginning of
the execution of an Instruction, a trace exception will be
generated after the execution of that instruction is completed.
If the instruction is not executed, either because an interrupt
is taken, or the instruction is illegal or privileged, the trace exception does not occur. The trace exception also does not occur
if the instruction is aborted by a reset, bus error, or address error
exception. If the instruction is indeed executed and an Interrupt

If a bus error occurs during the exception processing for a bus
error, address error, or reset, the processor is halted, and all
processing ceases. This simplifies the detection of catastrophic
system failure, since the processor removes itself from the
system rather than destroy all memory contents. Only the RESET
pin can restart a halted processor.

1-28

R68000

16-Bit MPU

SSP

15

14

13

12

11

10

7

8

9

6

5

4

I R/WII/N I

- -

-ACCESS ADDRESS

o

2

3

HIGH

-------------------lOW

1

HIGHER
ADDRESS

INSTRUCTION REGISTER
STATUS REGISTER

I-- - PROGRAM COUNTER

II

FUNCTION
CODE

HIGH

-------- -----------

- -

lOW
RIW (READ/WRITE): WRITE

= 0, READ = 1. liN (INSTRUCTION/NOT): INSTRUCTION = 0, NOT =1.
Figure 31.

Supervisor Stack Order (Group 0)

SO S1 S2 53 S4 S5 S6 S7 SO S1 52 S3 54 S5 S6 S7
ClK
A1-A23
AS

\
\
\

UDS
lDS

RlW
DTACK

J

I

I

SO 51 S2 S3 S4 S5

I

\

\
\

\
\

DO-D15

I

(

I"

READ

'--

~----------~'---

I

>---\

"I"

ADDRESS ERROR
WRITE

Figure 32.

)

-I"

Address Error Timing

ADDRESS ERROR. Address error exceptions occur when the
processor attempts to access a word or a long word operand
or an instruction at an odd address. The effect IS much like an
internally generated bus error, so that the bus cycle is aborted,
and the processor ceases whatever processing it is currently
doing and begins exception processing. After exception
processing commences, the sequence IS the same as that for
bus error including the information that is stacked, except that
the vector number refers to the address error vector instead.
Likewise, if an address error occurs during the exception
processing for a bus error, address error, or reset, the processor
is halted. As shown in Figure 32, an address error will execute
a short bus cycle followed by an exception processing.

1-29

"-l

(

APPROX. 8 CLOCKS
IDLE

----1--I- WRITE STACK---l

R6S000

16-Bit MPU

INTERFACE WITH R6500 PERIPHERALS

chip select equation of the peripheral. This ensures that the
R6500 peripherals are selected and deselected at the correct
time. The peripheral now runs its cycle during the high portion
of the E signal. Figures 34 and 35 depict the best and worst case
R6500 cycle timing. This cycle length is dependent strictly upon
when VPA is asserted in relationship the E clock.

Rockwell's line of R6500 peripherals are directly compatible with
the R68000. Some of these devices that are particularly useful
are:
R6520 Peripheral Interface Adapter (PIA)
R6522 Versatile Interface Adapter (VIA)
R6545 CRT Controller (CRTC)
R6551 Asynchronous Communication Interface Adapter
(ACIA)

If we assume that external circuitry asserts VPA as soon as
possible after the assertion of AS, then VPA will be recognized
as being asserted on the falling edge of S4. In this case, no
"extra" wait cycles will be inserted prior to the recognition of
VPA assertion and only the wait cycles inserted to synchronize
with the E clock will determine the total length of the cycle. In
any case, the synchronization delay will be some integral number
of clock cycles within the following two extremes:
1. Best Case-VPA is recognized as being asserted on the
falling edge three clock cycles before E rises (or three clock
cycles after E falls).
2. Worst Case-VPA is recognized as being asserted on the
falling edge two clock cycles before E rises (or four clock
cycles after E falls).

To interface the synchronous R6500 peripherals with the asynchronous R68000, the processor modifies its bus cycle to meet
the R6500 cycle requirements whenever an R6500 device
address is detected. This is possible since both processors use
memory mapped I/O. Figure 33 is a flow chart of the interface
operation between the processor and R6500 devices. 6800
peripherals are also compatible with the R68000 processor.

DATA TRANSFER OPERATION
Three signals on the processor provide the R6500 interface.
They are: enable (E), valid memory address (VMA), and valid
Peripheral address (VPA). Enable corresponds to the E or ~2
signal in existing R6500 systems. The bus frequency is one tenth
of the incoming R68000 clock frequency. The timing of E allows
1 MHz peripherals to be used with an 8 MHz R68000. Enable
has a 60/40 duty cycle; that is, it is low for six input clocks and
high for four input clocks. This duty cycle allows the processor
to do successive VPA accesses on successive E pulses.

Near the end of a read cycle, the processor latches the
peripheral's data in state 6. For all cycles, the processor negates
the address and data strobes one half clock cycle later in state 7,
and the Enable signal goes low at this time. Another half clock
later, the address bus is put in the high-impedance state. Upon
write cycle completion, the data bus is put in the high-impedance
state and the read/write signal is switched high. The peripheral
logic must remove VPA within one clock after address strobe
is negated.

Figures 34 and 35 give a general R6500 to R68000 interface
timing, while Figures 36 and 37 detail the specific timing
parameters involved in the interface. At state zero (SO) in the
cycle, the address bus is in the high-impedance state. A function code is asserted on the function code output lines. Onehalf clock later, in state 1, the address bus is released from the
high-impedance state.

DTACK should not be asserted while VPA is asserted. Note
that the R68000 VMA is active low. This allows the processor
to put its buses in the high-impedance state on DMA requests
without inadvertently selecting peripherals.

During state 2, the address strobe (AS) is asserted to indicate
that there is a valid address on the address bus. If the bus cycle
is a read cycle, the upper and/or lower data strobes are also
asserted in state 2. If the bus cycle is a write cycle, the read/write
(R/ViI) signal is switched to a low (write) during state 2. Qne-half
clock later, in state 3, the write data is placed on the data bus,
and in state 4 the data strobes are issued to indicate valid data
on the data bus. The processor now inserts wait states until it
recognizes the assertion of VPA.

During an interrupt acknowledge cycle while the processor is
fetching the vector, if VPA is asserted, the R68000 will assert
VMA and complete a normal R6500 read cycle as shown in
Figure 38. The processor will then use an internally generated
vector, called an autovector, that is a function of the interrupt
being served. The seven autovectors are vector numbers 25
through 31 (decimal).

The VPA input Signals the processor that the address on the
bus is the address of an R6500 device (or an area reserved for
R6500 devices) and that the bus should conform to the ~2
transfer characteristics of the R6500 bus. Valid peripheral
address (VPA) is derived by decoding the address bus,
conditioned by address strobe (AS). Chip select for the R6500
peripherals should be derived by decoding the address bus conditioned by VMA.

Autovectors operate in the same fashion (but are not restricted
to) the R6500 interrupt sequence. The basic difference is that
there are six normal interrupt vectors and one NMI type vector.
As With both the R6500 and the R68000's normal vectored interrupt, the interrupt service routine can be located anywhere in
the address space. This is due to the fact that while the vector
numbers are fixed, the contents of the vector table entries are
assigned by the user.

After the recognition of VPA, the processor assures that the
Enable (E) is low, by waiting if necessary, and subsequently
asserts VMA. Valid memory address is then used as part of the

Since VMA is asserted during autovectoring, the R6500
peripheral address decoding should prevent unintended
accesses.

INTERRUPT OPERATION

1-30

16·Bit MPU

R68000
S2

SO

S4

w

w

w

w

w

w

S6

S2

SO

CLK

J-<

A1-A23

>---C
~

ASF\
DTACK

>>-

(

DATA OUT
DATA IN

<

::x

FCo-FC2
E

""\

x::=

I

\
~

\

VPA

r-

\

VMA

Figure 34.

R68000 to R6SDD Peripheral Timing-Best Case

~~Mwwwwwwwwwwwwwww~~

CLK
A1-A23
AS

:>-<

K

r

~

DTACK
DATA OUT
DATA IN
FCO-FC2

---<
<

=x

I

E

VPA

I

\

\

VMA

Figure 35.

>->--

)(

'---

\
R68DDD to R6S0D Peripheral Timing-Worst Case

1-31

r

r

i

~

::D
m
Q)

o
o
o

SO
~I

~

S1

S2
~I

S3

S4
r-"\.I

w

~W

w

w

r-"\.

~IW

W
~

w

w

w

w
~

~

elK

S5

S7 _ so
S6
~

A1·A23

AS

......-.I ,--r.t1'I

E

11-

®
@

c:;

I

1=1 ~
,~@

VPA

I\)

VMA

JF~I """

@

DATA OUT - - - - - DATAIN _ _

I
I
~
----------------------------------------

NOTES:
THIS FIGURE REPRESENTS THE BEST CASE R6500 TIMING WHERE VPA FAllS BEFORE THE THIRD SYSTEM CLOCK CYCLE
AFTER THE FALLING EDGE OF E.
THIS TIMING DIAGRAM IS INCLUDED FOR THOSE WHO WISH TO DESIGN THEIR OWN CIRCUIT TO GENERATE VMA IT SHOWS
THE BEST CASE POSSIBLY ATTAINABLE.

....

m
•
m
::;
i!!:

Figure 36.

R6500 Timing-Best Case

'tJ
C

1S-Bit MPU

RSSOOO
PROCESSOR

Included in the register indirect addressing modes is the capability to do postincrementing, predecrementing, offsetting and
indexing. Program counter relative mode can also be modified
via indexing and offsetting.

SLAVE

INITIATE CYCLE
1) THE PROCESSOR STARTS A
NORMAL READ OR WRITE CYCLE

Table 9.

I

+
I

SYNCHRONIZE WITH ENABLE
1) THE PROCESSOR MONITORS ENABLE
(E) UNTIL IT IS LOW (PHASE 1)
2) THE PROCESSOR ASSERTS VALID
MEMORY ADDRESS (VMA)

I

,

TRANSFER DATA
1) THE PERIPHERAL WAITS UNTIL E
IS ACTIVE AND THEN TRANSFERS
THE DATA

,

I

TERMINATE CYCLE
1) THE PROCESSOR WAITS UNTIL E
GOES LOW. (ON A READ CYCLE THE
DATA IS LATCHED AS E GOES LOW
INTERNALLY)
2) THE PROCESSOR NEGATES VMA
3) THE PROCESSOR NEGATES AS, UDS,
and LOS

Register Direct Addressing
Data Register Direct
Address Register Direct

EA
EA

= Dn
= An

Absolute Data Addressing
Absolute Short
Absolute Long

EA
EA

= (Next Word)
= (Next Two Words)

Program Counter Relative
Addressing
Relative with Offset
Relative With Index and Offset

EA
EA

= (PC) + dl6
= (PC) + (Xn) + dB

Register Indirect Addressing
Register Indirect
Postlncrement Register Indirect
Predecrement Register Indirect
Register Indirect With Offset
Indexed Register Indirect With Offset

EA =
EA =
An_
EA =
EA =

Immediate Data Addressing
Immediate
QUick Immediate

DATA = Next Word(s)
Inherent Data

Implied Addressing
Implied Register

EA

NOTES:
EA = Effective Address
An = Address Register
Dn = Data Register
Xn = Address or Data Register
used as Index Register
SR = Status Register
PC = Program Counter
( ) = Contents of
dB = Eight-bit Offset
(displacement)
d 16 = Sixteen-bit Offset
(displacement)

START N!xT CYCLE

Figure 33.

Generation

Mode

DEFINE R6S00 CYCLE
1) EXTERNAL HARDWARE ASSERTS
VALID PERIPHERAL ADDRESS (VPA)

+

Addressing Modes

R6500 Interfacing Flow Chart

DATA TYPES AND ADDRESSING MODES

N

(An)
(An),
An (An)
(An)

An __ An + N
N, EA = (An)
+ dl6
+ (Xnl' + ds

= SR, USP, SP, PC

= 1 for Byte,

..- =

2 for
Words and 4 for
Long Word, If An
IS the stack pOinter
and the operand
size IS byte, N = 2
to keep the stack
pOinter on a word
boundry,
Replaces

Five basic data types are supported. These data types are:
Bits
BCD Digits (4-bits)
Bytes (8-bits)
Word (16-bits)
Long Words (32-bits)

INSTRUCTION SET OVERVIEW
The R68000 instruction set is shown in Table 10. Some additional instructions are variations, or subsets, of these and they
appear in Table 11, Special emphasis has been given to the
instruction set's support of structured high-level languages to
facilitate ease of programming. Each instruction, with few exceptions, operates on bytes, words, and long words and most
instructions can use any of the 14 addressing modes. Combining
instruction types, data types, and addressing modes, over 1000
useful instructions are provided, These instructions include
signed and unsigned multiply and divide, "quick" arithmetic
operations, BCD arithmetic and expanded operations (through
traps),

In addition, operations on other data types such as memory
addresses, status word data, etc., are provided for in the instruction set.
The 14 addressing modes, shown in Table 9, include six basic
types:
Register Direct
Register Indirect
Absolute

Program Counter Relative
Implied
Immediate

1-33

II

16-Bit MPU

R68000
SO Sl S2 S3 S4

w w w w w w w w w w w w w w w w w w w w w w w w w w w w S5 S6 S7 SO

CLK

E

A1·A23
DATA OUT·--DATAIN ___ _

NOTE: THIS TIMING DIAGRAM IS INCLUDED FOR THOSE WHO WISH TO DESIGN THEIR OWN CIRCUIT TO GENERATE VMA.
IT SHOWS THE WORST CASE POSSIBLY ATTAINABLE.

Figure 37.

RC68000 to R6500 Peripheral Timing Diagram - Worst Case

CLK
A1·A3
A4·A23
AS
UDS'
LOS

' - - 1 \~--------------~

R/W
DTACK
08·015
00·07

FCO·FC2
IPLO·IPL2

---<=:)
~

y

'C

______

\
~====~------~r~

X

~

E
VPA
VMA

L-

\~

_ _ _ _--,I

f+ NORMAL -+I~---AUTOVECTOR
.,0(
OPERATION----;~
CYCLE

'ALTHOUGH A VECTOR NUMBER IS ONE BYTE, BOTH DATA STROBES ARE ASSERTED DUE TO THE MICROCODE USED
FOR EXCEPTION PROCESSING. THE PROCESSOR DOES NOT RECOGNIZE ANYTHING ON DATA LINES 08 THROUGH
015 AT THIS TIME.

Figure 38.

Autovector Operation Timing Diagram

1·34

I
---.J

16-Bit MPU

R6S000
Table 10.
Mnemonic

Description

Mnemonic

ADBC
ADD
AND
ASL
ASR

Add Decimal with Extend
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right

BCC
BCHG
BCLR
BRA
BSET
BSR
BTST

Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test

CHK

Check Register Against
Bounds
Clear Operand
Compare

CLR
CMP
DBCC
DIVS
DIVU

Test Condition, Decrement and
Branch
Signed Divide
Unsigned Divide

ADD

AND

Variation

JMP
JSR

Jump
Jump to Subroutine

LEA
LINK
LSL
LSR

Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right

MOVE
MULS
MULU

Move
Signed Multiply
Unsigned Multiply

NBCD
NEG
NOP
NOT

Negate Decimal with Extend
Negate
No Operation
One's Complement

OR

Logical Or

AND
ANDI
ANDI to CCR

Logical And
And Immediate
And Immediate to
Condition Codes
And Immediate to
Status Register

Instruction
Type

CMP
CMPA
CMPM
CMPI

Compare
Compare Address
Compare Memory
Compare Immediate

EOR

EOR
EORI
EORI to CCR

Exclusive Or
Exclusive Or Immediate
Exclusive Or Immediate
(0 Condition Codes
Exclusive Or Immediate
to Status Register

Push Effective Address

RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS

Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine

SBCD
SCC
STOP
SUB
SWAP

Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves

TAS
TRAP
TRAPV
TST

Test and Set Operand
Trap
Trap on Overflow
Test

UNLK

Unlink

1-35

Variation

Description

MOVE
MOVEA
MOVEM
MOVEP
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP

Move
Move
Move
Move
Move
Move
Move
Move
Move

NEG

NEG
NEGX

Negate
Negate with Extend

OR

OR
ORI
ORI to CCR
ORI to SR

Logical Or
Or Immediate
Or Immediate to Condition Codes
Or Immediate to
Status Register

SUB

SUB
SUBA
SUB!
SUBQ
SUBX

Subtract
Subtract
Subtract
Subtract
Subtract

MOVE
Address
Quick
Immediate
with Extend

CMP

Description

PEA

Variations of Instruction Types

Description
Add
Add
Add
Add
Add

EORI to SR

Mnemonic

Exclusive Or
Exchange Registers
Sign Extend

ADD
ADDA
ADDQ
ADDI
ADDX

ANDI to SR

I

I

Description

EOR
EXG
EXT

Table 11.
Instruction
Type

Instruction Set Summary

I

Address
Multiple Registers
Peripheral Data
Quick
from Status Register
to Status Register
to Condition Codes
User Stack Pointer

Address
ImmF.!d;atA

Quick
with Extend

D

16·Bit MPU

R68000

Table 12. Data Movement Operations

The following paragraphs contain an overview of the form and
structure of the R68aaa instruction set. The instructions form
a set of tools that include all the machine functions to perform
the following operations:

Instruction

Data Movement
Integer Arithmetic
Logical
Sh ift and Rotate
Bit Manipulation
Binary Coded Decimal
Program Control
System Control

Operand Size

EXG

32

LEA

32

Operation

EA_ An

An _ -(SP)
SP _An
SP + displacement _SP

LINK

The complete range of instruction capabilities combined with
the flexible addressing modes described previously provide a
very flexible base for program development.

ADDRESSING
Instructions for the R68aaa contain two kinds of information: the
type of function to be performed, and the location of the
operand(s) on which to perform that function. The methods used
to locate (address) the operand(s) are explained in the following paragraphs.

-

Implicit Reference

-

8. 16,32

MOVEM

16,32

(EA) _An, On
An, On --EA

MOVEP

16, 32

(EA) __ On
On ... (EA)

MOVEQ

8

#xxx --On

PEA

32

EA ... -(SP)

SWAP

32

On[31.16J_On[15:0J

An -Sp

UNLK

Instructions specify an operand location in one of three ways:
Register Specification - the number of the register is given
in the register field of the
instruction.
Effective Address

MOVE

I

use of the different effective
address modes.
the definition of certain instructions
implies the use of specific
registers.

NOTES:
s = source
d = destination
[ J = bit number

(SP) + _An

- (

) = indirect With predecrement

( ) + = indirect with postdecrement
#

=

Immediate data

operand sizes. Address operations are limited to legal address
size operands (16 or 32 bits). Data, address, and memory compare operations are also available. The clear and negate instructions may be used on all sizes of dala operands.
The multiply and divide operations are availat'\e for signed and
unsigned operands using word multiply to produce a long word
product, and a long word dividend with word divisor to produce
a word quotient with a word remainder.

DATA MOVEMENT OPERATIONS
The move (MOVE) instruction provides a means for data acquisition (transfer and storage). The move instruction and the effective addressing modes allow both address and data manipulation. Data move instructions allow byte, word, and long word
operands to be transferred from memory to memory, memory
to register, register to memory, and register to register. Address
move instructions allow word and long word operand transfers
and ensure that only legal address manipulations are executed.
In addition to the general move instruction there are several
special data movement instructions: move multiple registers
(MOVEM), move peripheral data (MOVEP), exchange registers
(EXG), load effective address (LEA), push effective address
(PEA), link stack (LINK), unlink stack (UNLK), and move quick
(MOVEQ). Table 12 summarizes the data movement operations.

Multiprecision and mixed size arithmetic can be accomplished
using a set of extended instructions. These instructions are: add
extended (ADDX), subtract extended (SUBX), sign extend (EXT),
and negate binary with extend (NEGX).
A text operand (TST) instruction that sets the condition codes
as a result of a compare of the operand with zero is available.
Test and set (TAS) is a synchronization instruction useful in
multiprocessor systems. Table 13 summrizes the integer
arithmetic operations.

INSTRUCTION FORMAT
Instructions, as shown in Figure 39, vary from one to five words
in length. The first word of the instruction, called the operation
word, specifies the length of the instruction and the operation
to be performed. The remaining words further specify the
operands. These words are either immediate operands or extensions to the effective address mode specified in the operation
word.

INTEGER ARITHMETIC OPERATIONS
The arithmetic operators include the four basic operations of add
(ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well
as arithmetic compare (CMP), clear (CLR), and negate (NEG).
The add and subtract instructions are available for both address
and data operations, and with data operations accepting all

1-36

16-Bit MPU

R6S000
Table 13.
Instruction

Operand Size

CLR

16,32
8,16,32
16,32

Ox + Oy + X -Ox
-(Ax) + -(Ay) + X -(Ax)

8,16,32

o -EA

8,16,32

16,32

On - (EA)
(EA) - #xxx
(Ax) + - (Ay)An - (EA)

32 + 16

On + (EA) _On

EFFECTIVE ADDRESS
Most instructions specify the location of an operand by using
the effective address field in the operation word. For example,
Figure 40 shows the general format of the single effective
address instruction operation word. The effective address is composed of two 3-bit fields: the mode field, and the register field.
The value in the mode field selects the different address modes.
The register field contains the number of a register.

CMP

OIVS

The R68000 separates memory references into two classes: pro·
gram relerences, and data references. Program references
reference that section of memory that contains the program
being executed. Data references refer to that section of memory
that contains data. Operand reads are from the data space,
except in the case of the program counter relative addressing
mode. All operand writes are to the data space.

Operation
On + (EA) _On
(EA) + On -(EA)
(EA) + #xxx -(EA)
An + (EA) _An

8, 16, 32
AOO

AOOX

I

PROGRAMIDATA REFERENCES

Integer Arithmetic Operations

OIVU

32 + 16

On + (EA) -On

EXT

8 _16
16 _32

(On)8 -On16
(Onh6 -On32

MULS

16 x 16 -32

On x (EA) -On

MULU

16 x 16 -32

On x (EA) - On

NEG

8, 16,32

NEGX

8, 16, 32

oo-

8,16,32

REGISTER SPECIFICATION
The register field within an instruction specifies the register to
be used. Other fields within the instruction specify whether the
register selected is an address or data register and how the
register is to be used.

(EA) -(EA)

The effective address field may require additional information
to fully specify the operand. This additional information, called
the effective address extension, is contained in the following
word or words and is considered part of the instruction, as shown
in Figure 39. The effective address modes are grouped into three
categories: register direct, memory addressing, and special.

(EA) - X _(EA)

On - (EA) -On
(EA) - On -- (EA)
(EA) - #xxx -(EA)
An - (EA) _An

SUB
16,32
SUBX

8,16,32

Ox - Oy - X -Ox
- (Ax) - - (Ay) - X _(Ax)

TAS

8

[EA] - 0, 1 _EA[7]

TST

8,16,32

(EA) - 0

REGISTER DIRECT MODES. These effective addressing modes
specify that the operand is in one of the 16 multifunction
registers.
Data Register Direct. The operand is in the data register
specified by the effective address register field.

NOTES:

] = bit number
-( ) = Indirect with predecrement
( ) + = Indirect with postdecrement
l # = Immediate data
[

Address Register Direct. The operand is in the address register
specified by the effective address register field.
MEMORY ADDRESS MODES. These effective addressing
modes specify that the operand is in memory and provide the
specific address of that operand.

15

14

13

12

11

10

9

8

7

6

5

4

OPERATION WORD
(FIRST WORD SPECIFIES OPERATION AND MODES)
IMMEDIATE OPERAND
(IF ANY, ONE OR TWO WORDS)

I

SOURCE EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE OR TWO WORDS)
DESTINATION EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE OR TWO WORDS)

Figure 39.

Instruction Format

1-37

3

2

o

--

16-Bit MPU

R6S000
5

4

3

2

1

0

EFFECTIVE ADDRESS
MODE
REGISTER

Figure 40.

Single-Effeclive-Address Instruction Operation Word General Format
address is the second extension word. The reference classifies
as a data reference with the exception of the jump and jump
to subroutine instructions.

Address Register Indirect. The address of the operand is in
the address register specified by the register field. The reference
is classified as a data reference with the exception of the jump
and jump to subroutine instructions.

Program Counter With Displacement. This address mode
requires one word of extension. The address of the operand
sums the addresses in the program counter and the signextended 16-bit displacement integer in the extension word. The
value in the program counter is the address of the extension
word. The reference classifies as a program reference.

Address Register Indirect With Postincrement. The address
of the operand is in the address register specified by the register
field. After the operand address is used. it is incremented by
one. two or four depending upon whether the size of the operand
is byte, word, or long word. If the address register is the stack
pointer and the operand size is byte, the address is incremented
by two rather than one to keep the stack pointer on a word
boundary. The reference classifies as a data reference.

Program Counter With Index. This address mode requires one
word of extension. This address sums the addresses in the program counter, the sign-extended displacement integer in the
lower eight bits of the extension word, and the contents of the
index register. The value in the program counter is the address
of the extension word. This reference classifies as a program
reference.

Address Register Indirect With Predecrement. The address
of the operand is in the address register specified by the register
field. Before the operand address is used, it is decremented by
one, two, or four depending upon whether the operand size is
byte, word, or long word. If the address register is the stack
pointer and the operand size is byte, the address is decremented
by two rather than one to keep the stack pOinter on a word
boundary. The reference is classified as a data reference.

Immediate Data. This address mode requires either one or two
words of extension depending on the size of the operation.
- operand is low order byte of extenByte Operation
sion word
Word Operation
- operand is extension word
Long Word Operation - operand is in the two extension
words, high-order 16 bits are in the
first extension word, low-order 16
bits are in the second extension
word.

Address Register Indirect with Displacement. This address
mode requires one word of extension. The address of the
operand is the sum of the address in the address register and
the sign-extended 16-bit displacement integer in the extension
word. The reference classifies as a data reference with the
exception of the jump to subroutine instructions.
Address Register Indirect With Index. This address mode
requires one word of extension. The address of the operand
sums the addresses in the address register, the sign-extended
displacement integer in the low order eight bits of the extension
word, and the contents of the index register. The reference is
classified as a data reference with the exception of the jump
and jump to subroutine instructions.

IMPLICIT REFERENCE
Some instructions make implicit reference to the program
counter (PC), the system stack pOinter (SP), the supervisor stack
pointer (SSP), the user stack pointer (USP), or the status register
(SR).
A selected set of instructions may reference the status register
by means of the effective address field. These are:
ANDI to CCR
ANDI to SR
EORI to CCR
EORI to SR
MOVE to CCR
MOVE to SR
MOVE from SR
ORI to CCR
ORI to SR

SPECIAL ADDRESS MODE. The special address modes use
the effective address register field to specify the special addressing mode instead of a register number.
Absolute Short Address. This address mode requires one word
of extension. The address of the operand is the extension word.
The 16-bit address is sign extended before it is used. The
reference classifies as a data reference with the exception of
the jump and jump to subroutine instructions.
Absolute Long Address. This address mode requires two words
of extension. The address of the operand is developed by the
concatenation of the extension words. The high-order part of
the address is the first extension word; the low-order part of the

EFFECTIVE ADDRESS ENCODING SUMMARY
Table 14 summarizes the effective addressing modes discussed
in the previous paragraphs.

1-38

16·Bit MPU

R68000
Table 14.

Effective Address Encoding Summary

Addressing Mode

Mode

Register

Data Register Direct

000

register number

Address Register Direct

001

register number

Address Register Indirect

010

register number

Address Register Indirect with
Postincrement

all

register number

Address Register Indirect with
Predecrement

100

register number

Address Register Indirect with
Displacement

101

register number

Address Register Indirect with
Index

Table 15.

110

register number

Absolute Short

111

000

Absolute Long

111

001

Program Counter with
Displacement

111

010

Program Counter with Index

111

all

Immediate

111

100

Logical Operations

Instruction

Operand Size

AND

8,16,32

DnA(EA) _On
(EA)ADn _(EA)
(EA)A#xxx _(EA)

OR

8,16,32

On. (EA) _On
(EA) • On _(EA)
(EA) • #xxx . . (EA)

EOR

8,16,32

(EA) e Dy _(EA)
(EA) e #xxx . . (EA)

NOT

8, 16, 32

- (EA) . . (EA)

NOTES:
- = Invert
# = immediate data
A = logical AND

Operation

• = logical OR
= logical exclusive OR

ED

Memory shifts and rotates are for word operands only and allow
only single-bit shifts or rotates.
Table 16 summarizes the shift and rotate operations.

BIT MANIPULATION OPERATIONS
The following instructions provide bit manipulation operations:
bit test (BTST), bit test and set (BSET), bit test and clear (BClR),
and bit test and change (BCHG). Table 17 is a summary of the
bit manipulation operations. (Bit 2 of the status register is Z.)

SYSTEM STACK. The system stack is used implicitly by many
instructions; user stacks and queues may be created and maintained through the addressing modes. Address register seven
(A7) is the system stack pointer (SP). The system stack pOinter
is either the supervisor stack pointer (SSP) or the user stack
pointer (USP), depending on the state of the S-bit in the status
register. If the S-bit indicates supervisor state (High), SSP is the
active system stack pointer, and the USP cannot be referenced
as an address register. If the S-bit indicates user state (Low),
the USP is the active system stack pOinter, and the SSP cannot be referenced. Each system stack fills from high memory
to low memory.

Table 16.

Instruction

Operand
Size

8,16,32

~--l"

ASR

8, 16, 32

LSL

8, 16, 32

c:!:;
~ ...

LSR

8,16,32

0-1

ROL

8, 16, 32

~

AOR

e,

ROXL

8, 16, 32

ROXR

8,16,32

SHIFT AND ROTATE OPERATIONS
Shift operations in both directions are provided by arithmetic
instructions ASR and ASl and logical shift instructions lSR and
lSL. The rotate instructions (with and without extend) available
are ROXR, ROXl, ROR, and ROL. All shift and rotate operations can be performed in either registers or memory. Register
shifts and rotates support all operand sizes and allow a shift
count specified in a data register.

1-39

Operation

ASL

LOGICAL OPERATIONS
logical operation instructions AND, OR, EOR, and NOT are
available for all sizes of integer data operands. A similar set of
immediate instructions (ANDI, ORI, and EORI) provide these
logical operations with all sizes of immediate data. Table 15 summarizes the logical operations.

Shift and Rotate Operations

16, 32

.

q
w...Y"
~

1-0

..~

1-+- 0

.. 1-@9
f+J

. P+0
Ri}IJ

.. ~

R68000

16·Bit MPU

Table 17.

Bit Manipulation Operations

Instruction

Operand Size

BTST

8, 32

- bit of (EA) .. Z

BSET

8, 32

- bit of (EA) ..
1 .. bit of EA

BCLR

8, 32

- bit of (EA) ..Z
o .. bit of EA

BCHG

8, 32

- bit of (EA) .. Z
- bit of (EA) .. bit of EA

Table 19.

Operation

Instruction
Conditional
BCC

z

Branch conditionally (14 conditions)
8· and IS·blt displacement
Test condition, decrement, branch
HI·bit displacement

SCC

Set byte conditionally (16 conditions)

Unconditional
BRA

Branch always
8· and 16·blt displacement

BSR

Branch to subroutine
8· and 16·bit displacement

JMP

Jump

JSR

Jump to subroutine

BINARY CODED DECIMAL OPERATIONS
The following instructions accomplish multiprecislon arithmetic
operations on binary coded decimal numbers: add decimal with
extend (ABCD), subtract decimal with extend (SBCD), and
negate decimal with extend (NBCD). Table 1B summarizes the
binary coded decimal operations.

Operstlon

DBCC

NOTE: - = Inven

Returns
RTR
RTS

Return and restore condition codes
Return from subroutine

'----

PROGRAM CONTROL OPERATIONS
Program control operations Implementation requires a series of
conditional and unconditional branch instructions and return
instructions. These instructions are summarized in Table 19.

SYSTEM CONTROL OPERATIONS
System control operations are accomplished by using privileged
instructions, trap generating instructions, and instructions that
use or modify the status register. These instructions are sum·
marized in Table 20.

The conditional instructions provide setting and branching for
the following conditions:
CC - carry clear
CS - carry set
EQ-equal
F - never true
GE - greater or equal
GT - greater than
HI - high
LE - less or equal
LS - low or same
LT - less than
MI - minus
NE - not equal
PL -plus
T - always true
VC - no overflow
VS - overflow

Table 18.

Program Control Operations

INSTRUCTION SET
The following paragraphs provide information about the address·
ing categories and instruction set of the R6BOOO.

ADDRESSING CATEGORIES
Effective address modes may be categorized by the ways in
which they may be used. The following classifications will be
used in the instructions definitions.
Data

If an effective address mode may be used to refer
to data operands, it is considered a data addressing
effective address mode.

Memory

If an effective address mode may be used to refer
to memory operands, it is considered a memory
addressing effective address mode.

Alterable

If an effective address mode may be used to refer
to alterable (writeable) operands, it is considered an
alterable addressing effective address mode.

Control

If an effective address mode may be used to refer
to memory operands without an associated size, it
is considered control addressing effective address
mode.

Binary Coded Decimal Operations

Instruction

Operand Size

Operation

ABCD

8

DX10 + DY10 + X . . Dx
-(Ax)10 + -(Ay)1O + x .. (Ax)

SBCD

8

Dx10 - DY10 - X . . Dx
-(Ax)1O - -(Ay)1O - X _(Ax)

NBeD

8

o - (EA)10 - X . . (EA)

Table 21 shows the various categories to which each of the effective address modes belong. Table 22 is the instruction set
summary.

NOTE: -( ) = indorect With predecrement

1·40

16-Bit MPU

R68000
Table 20.

System Control Operations

Instruction

INSTRUCTION PREFETCH
The R6S000 uses a two-word tightly-coupled instruction prefetch
mechanism to enhance performance. This mechanism is
described in terms of the microcode operations involved. If the
execution of an instruction is defined to begin when the
microroutine for that instruction is entered, some features of the
prefetch mechanism can be described.
1) When execution of an instruction begins, the operation word
and the word following have already been fetched. The operation word is in the instruction decoder.

Operation

Privileged
ANDI to SR
EORI to SR
MOVE EA to SR
MOVE USP
ORI to SR
RESET
RTE
STOP

Logical AND to Status Register
Logical EOR to Status Register
Load New Status Register
Move User Stack Pointer
Logical OR to Status Register
Reset External Devices
Return from Exception
Stop Program Execution

Trap Generating
CHK
TRAP
TRAPV

Check Data Register Against Upper Bounds
Trap
Trap on Overflow

Status Register
ANDI to CCR
EORI to CCR
MOVE EA to CCR
MOVE SR to EA
ORI to CCR

Logical AND to Condition Codes
Logical EOR to Condition Codes
Load New Condition Codes
Store Status Register
Logical OR to Condition Codes

2) In the case of multi-word instructions, as each additional word
of the Instruction is used internally, a fetch is made to the
instruction stream to replace it.
3) The last fetch from the instruction stream is made when the
operation word is discarded and decoding is started on the
next instruction.
4) If the instruction is a single-word instruction causing a branch,
the second word is not used. But because this word is fetched
by the preceding instruction, it is impossible to avoid this
superfluous fetch.
5) In the case of an interrupt or trace exception, both words are
not used.
6) The program counter usually points to the last word fetched
from the instruction stream.

INSTRUCTION EXECUTION TIMES

The status register addressing mode is not permitted unless it
is explicitly mentioned as a legal addressing mode.

The following paragraphs contain listings of the instruction
execution times in terms of external clock (elK) periods. In this
timing data, it is assumed that both memory read and write cycle
times are four clock periods. Any wait states caused by a longer
memory cycle must be added to the total instruction time. The
number of bus read and write cycles for each instruction is
enclosed in parenthesis following the execution periods and is
shown as (r/w) where r is the number of read cycles and w is
the number of write cycles.

These categories may be combined, so that additional, more
restrictive, classifications may be defined. For example, the
instruction descriptions use such classifications as alterable
memory or data alterable. The former refers to those addressing modes which are both alterable and memory addresses, and
the latter refers to addressing modes which are both data and
alterable.

Table 21,
Effective
Address
Modes

Effective Addressing Mode Categories
Addressing Categories

Mode

Register

Data

Memory

Control

On
An
(An)

000
001
010

Register Number
Register Number
Register Number

X

-

-

X

X

X

-

X

X

(An) +
-(An)
d(An)

all
100
101

Register Number
Register Number
Register Number

X
X
X

X
X
X

-

X

X

X

d(An, ix)
xxx.W
xxx.L

110
111
111

Register Number
000
001

X
X
X

X
X
X

X
X
X

X

d(PC)
d(PC, ix)
#xxx

111
111
111

010
all

X
X
X

X

X
X

-

.--~-

-~--

--

X

1-41

X
X

-

-

Alterable
X

X

X
X

16-Bit MPU

R68000
Table 22.

Instruction Set
Condition Codes

Mnemonic

Operation

Description

ABCD

Add Decimal with Extend

(Destination), 0 + (Source), 0 + X .... Destination

ADD

Add Binary

(Destination) + (Source) _Destination

ADDA

Add Address

(Destination) + (Source) _Destination

ADDI

Add Immediate

(Destination) + Immediate Data -Destination

ADDQ

Add Quick

(Destination) + Immediate Data _Destination

ADDX

Add Extended

(Destination) + (Source) + X _ Destination

AND

AND Logical

(Destination) A (Source) .... Destination

ANDI

AND Immediate

(Destination) A Immediate Data _ Destination

ANDI \0 CCR

AND Immediate to Condition Codes

(Source) A CCR _CCR

X

N

Z

V

C

·
····
U

U

- - - - -

ANDI to SR

AND Immediate to Status Register

(Source) A SR _SR

ASL, ASR

Arithmetic Shift

(Destination) Shifted by  _Destination

····
·
···
- ·
·
··· .
· · ·.- -:- r-;--

BCC

Branch Conditionally

If CC then PC + d -PC

- - - -

-

BCHG

Test a Bit and Change

- «bit number» OF Destination -Z
- « bit number» OF Destination < bit number> OF Destination

- -

-

BCLR

Test a Bit and Clear

o _

··-

BRA

Branch Always

PC+d .... PC

BSET

Test a Bit and Set

- « bit number» OF Destination .... Z
1 _ < bit number> OF Destination
PC _(SP); PC + d .... PC

- «bit number» OF Destination _Z
_OF Destination

BSR

Branch to Subroutine

BTST

Test a Bit

- « bit number» OF Destination .... Z

CHK

Check Register Against Bounds

If Dn <0 or Dn> «ea» then TRAP

Clear and Operand

o _Destination

Compare

(Destination)

CMPA

Compare Address

(Destination)

CMPI

Compare Immediate

(Destination)

CMPM

Compare Memory

(Destination) - (Source)

-

-

DBCC

Test Condition, Decrement and Branch

If - CC then Dn - 1 .... Dn; if Dn '" - 1 then PC + d _PC

DIVS

Signed Divide

(Destination)/(Source) _Destination

-

DIVU

Unsigned Divide

(Destination)/(Source) .... Destination

-

EOR

Exclusive OR Logical

(Destination) e (Source) .... Destination

EORI

Exclusive OR Immediate

(Destination) .. Immediate Data .... Destination

-

EORI to CCR

Exclusive OR Immediate
to Condition Codes

(Source) e CCR _ CCR

AND
OR
exclusive OR
complement

.

= affected
- = unaffected
0 = cleared
1 = set
U = undefined

1-42

0

0

- - - - - - - · - - - - - - - · - - · U U U
- 0 1 0 0
.
- ·
- · ·

CLR

1--NOTES:
A = logical
v = logical
.. = logical
- = logical

0

·

CMP

- (Source)
- (Source)
- Immediate Data

0

··
···
·
- - - -·

·
·
· ·

a
a

0

0

a

0

16-Bit MPU

R68000
Table 22.

Instruction Set (Continued)

I
Condition Codes

Description

Mnemonic
EORlto SR

Exchange Register

Rx_Ry

EXT

Sig~

(DestinatIon) Sign-Extended ... Destination

JMP

Jump

Destination ... PC

JSR

Jump to Subroutine

PC ... - (SP); Destination ... PC

Extend

Load Effective Address

 ... An

LINK

Link and Allocate

An ... (SP); SP ... An; SP + Displacement -SP

LSL, LSR

Logical Shift

(Destination) Shifted by < count> .. Destination

MOVE

Move Data from Source to Destination

(Source) _Destination

MOVE to CCR

Move to Condition Code

(Source) -CCR

MOVE to SR

Move to the Status Register

(Source) _ SR
SR - Destination

MOVE USP

Move User Stack POinter

USP _An; An ... USP

MOVEA

Move Address

(Source) .. Destination

MOVEM

Move Multiple Registers

Register .. Destination
(Source) . . Registers

MOVEP

Move Peripheral Data

(Source) .. Destination

MOVEQ

Move Quick

MULS

Signed Multiply

Immediate Data _Destination
-(Destlnation)X(Source) .. Destination

'" _ _ _ _ _ _ ~ ••

MULU

Unsigned Multiply

NBCD

Negate Decimal with Extend

NEG

Negate

NEGX

Negate with Extend

ooo-

NOP

No Operation

-

NOT

Logical Complement

- (Destination) .. Destination

Inclusive OR Logical

(Destination) v (Source) _ Destination

ORI

Inclusive OR Immediate

(Destination) v Immediate Data _Destination

ORlto CCR

Inclusive OR Immediate
to Condition Codes

(Source) v CCR .. CCR

ORI to SR

Inclusive OR Immediate
to Status Register

(Source) v SR _SR

(Destinatlon)X(Source) .. Destination
(Destination)10 - X _Destination
(Destination)" Destination
(Destination) - X .. Destination

PEA

Push Effective Address

 _ - (SP)

RESET

Reset External Device

-

ROL, ROR

Rotate (Without Extend)

(Destination) Rotated by  _Destination

-----

NOTES:
A = logical
v = logical
e = logical
- = logical

AND
OR
exclusive OR
complement

.
0
1
U

=
=
=
=
=

affected
unaffected
cleared
set
undefined

1-43

V

0

C

0

- - - - - - - - -

··· ·
- ··
·····
···
- - - - 0
0

MOVE from SR Move from the Status Register

OR

Z

- - - - - - - - -

LEA

--

N

·····
- - - - - · ·

(Source) e SR ... SR

EXG

--

X

Operation

Exclusive OR Immediate
to Status Register

I

____

0

0

- - ---- I---- - -- - - - - - - - 0 0
-

••

·
·
- ·
·
··

·

·
·
· ·
···
·····
- - - - - · ·
- · ·
- · ·
·····
·····
-

U

0

0

0

0

U

0

0

0

0

0

0

- - - - - - - - 0
-

·· ·

II

16-Bit MPU

R6S000
Table 22.

Instruction Set (Continued)
Condition Codes

Mnemonic

Description

Operation

< count>

~Destination

ROXL,ROXR

Rotate with Extend

(DestrnatlOn) Rotated by

RTE

Return from Exception

(SP) + ~SR; (SP) +

~PC

RTR

Return and Restore Condition Codes

(SP) +

~PC

RTS

Return from Subroutine

(SP) + _PC

SBCD

Subtract Decimal with Extend

(Destination}jo - (Source)1Q - X +-Destination

SCC

Set According to Condition

If CC then 1's +- DestinatIOn else a's -- Destination

~CC;

(SP) +

X

N

.·
·

Z

\I

C

.·
.

0

-

- - - -

-

-

U

·

-

·

U

-

·

-

·

STOP

Load Status Register and Stop

Immediate Data -- SR; STOP

SUB

Subtract Binary

(Destination) - (Source) __ Destination

SUBA

Subtract Address

(Destination) - (Source) __ Destination

SUBI

Subtract Immediate

(Destination) - Immediate Data __ Destination

SUBQ

Subtract Quick

(Destination) - Immediate Data __ Destination

SUBX

Subtract with Extend

(Destination) - (Source) - X _Destination

SWAP

Swap Register Halves

Register [3t :16J_Register [15:0]

TAS

Test and Set an Operand

(Destination) Tested _ CC; 1 __ [7] OF Destination

TRAP

Trap

PC __ - (SSP); SR -- - (SSP); (Vector) -PC

TRAPV

Trap on Overflow

If v then TRAP

0 0
0 a
- - - - - - - - -

TST

Test and Operand

(Destination) Tested - CC

-

UNLK

Unlink

An _SP; (SP) + _An

- - - - -

NOTES:
[ ] = bit number
= logical AND
A
v
= logical OR
= logical exclUSive OR
- = logical complement

'"

-

.

-

-

·
-

·
·
· ·

·

·

·
··
·

-

0

0

= affected
- = unaffected
0 = cleared
1 = set
U = undefined

i

ST ANDARD INSTRUCTION CLOCK PERIODS

Note

The number of clock periods shown in Table 26 delineate the
time required to perform the operations, store the results, and
read the next instruction. The number of bus read and write
cycles is shown in parenthesis as (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.

The number of periods includes instruction fetch and all
applicable operand fetches and stores.

EFFECTIVE ADDRESS OPERAND
CALCULATION TIMING
Table 23 lists the number of clock periods required to compute
an instruction's effective address. It includes fetching of any
extension words, the address computation, and fetching of the
memory operand. The number of bus read and write cycles is
shown in parenthesis as (r/w). Note there are no write cycles
involved in processing the effective address.

In Table 26, the headings have the following meanings:
An = address register operand, Dn = data register operand,
ea = an operand specified by an effective address, and
M = memory effective address operand.

MOVE INSTRUCTION CLOCK PERIODS

IMMEDIATE INSTRUCTION CLOCK PERIODS

Tables 24 and 25 indicate the number of clock periods for the
move instruction. This data includes instruction fetch, operand
reads, and operand writes. The number of bus read and write
cycles is shown in parenthesis as (r/w) ,

The number of clock periods shown in Table 27 includes the
time to fetch immediate operands, perform the operations, store
the results, and read the next operation. The number of bus read
and write cycles is shown in parenthesis as (r/w). The number

1-44

16-Bit MPU

R68000
Table 23.

Effective Address Calculation Timing

Addressing Mode

Byte, Word

Long

On
An

Register
Data Register Direct
Address Register Direct

0(0/0)
0(0/0)

0(0/0)
0(0/0)

(An)
(An) +

Memory
Address Register Indirect
Address Register Indirect with Postincrement

4(1/0)
4(1/0)

8(2/0)
8(2/0)

-(An)
d(An)

Address Register Indirect with Predecrement
Address Register Indirect with Displacement

6(1/0)
8(2/0)

10(2/0)
12(3/0)

d(An, ix)'
xxx.W

Address Register Indirect with Index
Absolute Short

10(2/0)
8(2/0)

14(3/0)
12(3/0)

xxx.L
d(PC)

Absolute Long
Program Counter with Displacement

12(3/0)
8(2/0)

16(4/0)
12(3/0)

d(PC, ix)'
#xxx

Program Counter with Index
Immediate

10(2/0)
4(1/0)

14(3/0)
8(2/0)

'The size of the index register (IX) does not affect execution time.

Table 24.

Move Byte and Word Instruction Clock Periods
Destination

Source
On
An
(An)

On

An

(An)

(An)+

-(An)

d(An)

d(An, ix)'

xxx.W

xxx.L

4(1/0)
4(1/0)
8(2/0)

4(1/0)
4(1/0)
8(2/0)

8(1/1)
8(1/1)
12(2/1)

8(1/1)
8(1/1)
12(2/1)

8(1/1)
8(111)
12(2/1)

12(2/1)
12(2/1)
16(3/1)

14(2/1)
14(2/1)
18(3/1)

12(2/1)
12(2/1)
16(3/1)

16(3/1)
16(3/1)
20(4/1)

(An) +
-(An)
d(An)

8(2/0)
10(2/0)
12(3/0)

8(2/0)
10(2/0)
12(3/0)

12(2/1)
14(2/1)
16(3/1 )

12(2/1)
14(2/1)
16(3/1)

12(2/1)
14(2/1)
16(3/1)

16(3/1)
18(3/1)
20(4/1)

18(3/1)
20(3/1)
22(4/1)

16(3/1)
18(3/1)
20(4/1)

20(4/1)
22(4/1)
24(5/1)

d(An, ix)'
xxx.W
xxx.L

14(3/0)
12(3/0)
16(4/0)

14(3/0)
12(3/0)
16(4/0)

18(3/1)
16(3/1)
20(4/1)

18(3/1)
16(3/1)
20(4/1)

18(3/1)
16(3/1)
20(4/1)

22(4/1)
20(4/1)
24(5/1)

24(4/1)
22(4/1)
26(5/1)

22(4/1)
20(4/1)
24(5/1)

26(5/1)
24(5/1)
28(6/1)

d(PC)
d(PC, IX)'
#xxx

12(3/0)
14(3/0)
8(2/0)

12(3/0)
14(3/0)
8(2/0)

16(3/1)
18(3/1)
12(2/1)

16(3/1)
18(3/1)
12(2/1)

16(3/1)
18(3/1)
12(2/1)

20(4/1)
22(4/1)
16(3/1)

22(4/1)
24(4/1)
18(3/1)

20(4/1)
22(4/1)
16(3/1)

24(5/1)
26(5/1)
20(4/1)

'The size of the index register (ix) does not affect execution time

of clock periods and the number of read and write cycles must
be added respeciiveiy LO ,hose 0: the effective adress calcula·
tion where indicated.

SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Table 28 indicates the number of clock periods for the single
operand instructions. The number of bus read and write cycles
is shown in parenthesis as (r/w). The number of clock periods
and the number of read and write cycles must be added respectively to those of the effective address calculation where
indicated.

In Table 27, the headings have the following meanings:
=immediate operand, Dn = data register operand,
An = address register operand, M = memory operand, and
SR = status register.

#

1-45

II

R68000

16-Bit MPU
Table 25.

Move Long Instruction Clock Periods
Destination

Source

On

An

(An)

(An) +

-(An)

dIAn)

dIAn, Ix)'

xxx.W

xxx.L

Dn
An
(An)

4(1/0)
4(1/0)
12(3/0)

4(1/0)
4(1/0)
12(3/0)

12(1/2)
12(1/2)
20(3/2)

12(1/2)
12(1/2)
20(3/2)

12(1/2)
12(1/2)
20(3/2)

16(2/2)
16(2/2)
24(4/2)

18(2/2)
18(2/2)
26(4/2)

16(212)
16(2/2)
24(4/2)

20(3/2)
20(3/2)
28(5/2)

(An) +
-(An)
dIAn)

12(3/0)
14(3/0)
16(4/0)

12(3/0)
14(3/0)
16(4/0)

20(3/2)
22(3/2)
24(4/2)

20(3/2)
22(3/2)
24(4/2)

20(3/2)
22(3/2)
24(4/2)

24(4/2)
26(4/2)
28(5/2)

26(4/2)
28(4/2)
30(5/2)

24(4/2)
26(4/2)
28(5/2)

28(5/2)
30(5/2)
32(6/2)

dIAn, ix)'
xxx.W
xxx.L

18(4/0)
16(4/0)
20(5/0)

18(4/0)
16(4/0)
20(5/0)

26(4/2)
24(4/2)
28(5/2)

26(4/2)
24(4/2)
28(5/2)

26(4/2)
24(4/2)
28(5/2)

30(5/2)
28(5/2)
32(6/2)

32(5/2)
30(5/2)
34(6/2)

30(5/2)
28(5/2)
32(6/2)

34(6/2)
32(6/2)
36(7/2)

d(PC)
d(PC, ix)*
#xxx

16(4/0)
18(4/0)
12(3/0)

16(4/0)
18(4/0)
12(3/0)

24(4/2)
26(4/2)
20(3/2)

24(4/2)
26(4/2)
20(3/2)

24(4/2)
26(4/2)
20(3/2)

28(5/2)
30(5/2)
24(4/2)

30(5/2)
32(5/2)
26(4/2)

28(5/2)
30(5/2)
24(4/2)

32(5/2)
34(6/2)
28(5/2)

'The size of the index register (ix) does not affect execution time.

Table 26.
Instruction

Standard Instruction Clock Periods

Size

op, Ant

ADD

Byte, Word
Long

8(1/0)+
6(1/0) + * *

4(1/0)+
6(1/0) + **

8(1/1)+
12(1/2)+

AND

Byte, Word
Long

-

4(1/0) +
6(1/0)+ **

8(1/1)+
12(1/2)+

CMP

Byte, Word
Long

6(1/0)+
6(1/0)+

op, On

4(1/0)+
6(1/0)+

op On, 

-

-

158(1/0) + *

-

-

70(1/0) + *

-

70(1/0) + *

-

OR

Byte, Word
Long

-

4(1/0)+
6(1/0) + **

8(1/1)+
12(1/2)+

SUB

Byte, Word
Long

8(1/0)+
6(1/0)+"

4(1/0)+
6(1/0)+ **

8(1/1)+
12(1/2)+

DIVS
DIVU
EOR
MULS
MULU

Byte, Word
Long

140(1/0) + *
4(1/0)***
8(1/0)* * *

-

8(1/1)+
12(1/2)+

NOTES:
+ add effective address calculation time
t word or long only
* indicates maximum value
* * The base time of SIX clock penods is increased to eight if the effective address mode is register direct or immediate (effective address time
should also be added).
* * * Only available effective address mode is data register direct
DIVS, DIVU The divide algonthm used by the R68000 provides less than 10% difference between the best and worst case timings.
MULS, MULU The multiply algorithm requires 38 + 2n clocks where n IS defmed as'
MULU: n = the number of ones in each 
MULU: n = concatanate the  with a zero as the LSB; n IS the resultant number of 10 or 01 patterns 10 the 17·bit source; I.e ,worst
case happens when the source is $5555.

1·46

16-Bit MPU

R68000
Table 27.

Immediate Instruction Clock Periods

Size

op #, On

op #, An

op #, M

ADDI

Byte, Word
Long

8(2/0)
16(3/0)

-

12(2/1) +
20(3/2)+

AD DO

Byte, Word
Long

4(1/0)
8(1/0)

ANDI

Byte, Word
Long

8(2/0)
16(3/0)

CMPI

Byte, Word
Long

8(2/0)
14(3/0)

EORI

Byte, Word
Long

8(2/0)
16(3/0)

-

Instruction

8(1/0)"
8(1/0)

-

8(1/1)+
12(1/2)+
12(2/1)+
20(3/1)+
8(2/0)+
12(J/U) +

12(2/1)+
20(3/2)+

MOVEO

Long

4(1/0)

-

-

ORI

Byte, Word
Long

8(2/0)
16(3/0)

-

12(2/1)+
20(3/2)+

SUBI

Byte, Word
Long

8(2/0)
16(3/0)

-

12(2/1)+
20(3/2)+

SUBO

Byte, Word
Long

4(1/0)
8(1/0)

-

8(1/0)"
8(1/0)

8(1/1)+
12(1/2)+

+ add effective address calculation time
" word only

Table 28.

Single Operand Instruction Clock Periods
Size

Register

Memory

CLR

Byte, Word
Long

4(1/0)
6(1/0)

8(1/1)+
12(1/2)+

NBCD

Byte

6(1/0)

8(1/1)+

NEG

Byte, Word
Long

4(1/0)
6(1/0)

8(1/1) +
12(1/2) +

NEGX

Byte, Word
Long

4(1/0)
6(1/0)

8(1/1)+
12(1/2)+

NOT

Byte, Word
Long

4(1/0)
6(1/0)

8(1/1)+
12(1/2)+

SCC

Byte, False
Byte, True

4(1/0)
6(1/0)

8(1/1)+
8(1/1)+

TAS

Byte

4(1/0)

10(1/1)+

TST

Byte, Word
Long

4(1/0)
4(1/0)

4(1/0)+
4(1/0)+

Instruction

+ add effective address calculation time

1-47

R68000

16·Bit MPU

SHIFT/ROTATE INSTRUCTION CLOCK PERIODS

CONDITIONAL INSTRUCTION CLOCK PERIODS

Table 29 delineates the number of clock periods for the shift
and rotate instructions. The number of bus read and write cycles
is shown in parenthesis as: (r/w). The number of clock periods
and the number of read and write cycles must be added respectively to those of the effective address calculation where
indicated.

Table 31 delineates the number of clock periods required for
the conditional instructions. The number of bus read and write
cycles is indicated in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.

BIT MANIPULATION INSTRUCTION CLOCK PERIODS

JMP, JSR, LEA, PWA, MOVEM INSTRUCTION CLOCK
PERIODS

Table 30 indicates the number of clock periods required for the
bit manipulation instructions. The number of bus read and write
cycles is shown In parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.

Table 29.

Table 32 indicates the number of clock periods required for the
jump, jump to subroutine, load effective address, push effective address, and move multiple registers instructions. The
number of bus read and write cycles is shown in parenthesis
as: (r/w).

Shift/Rotate Instruction Clock Periods
Size

Register

Memory

ASR, ASL

Byte, Word
Long

6 + 2n(1/0)
8 + 2n(1/0)

8(1/1)+

LSR, LSL

Byte, Word
Long

6 + 2n(1I0)
8 + 2n(1/0)

8(1/1)+

ROR, ROL

Byte, Word
Long

6 + 2n(1/0)
8 + 2n(1/0)

8(1/1)+

ROXR,ROXL

Byte, Word
Long

6 + 2n(1I0)
8 + 2n(1/0)

8(1/1)+

Instruction

-

-

-

+ add effective address calculation time
n is shift or rotate count

Table 30.

Bit Manipulation Instruction Clock Periods
Dynamic

Static

Instruction

Size

Register

Memory

Register

Memory

BCHG

Byte
Long

-

8(1/1)+

-

-

12(211) +

12(2/0)*

-

BCLR

Byte
Long

-

8(1/1)+

-

12(2/1) +

10(1/0)'

-

14(2/0)'

-

BSET

Byte
Long

-

8(1/1)+

8(1/0)'

BTST

Byte
Long

8(110)"

-

-

12(2/1)+

12(2/0)'

-

4(1/0)+

-

8(2/0)+

6(1/0)

-

10(2/0)

+ add effective address calculation time
, Indicates maximum value

1-48

-

-

16-Bit MPU

R68000
Table 31.
Instruction

Displacement

10(2/0)

8(110)
12(2/0)

10(2/0)

BRA

Byte
Word

10(2/0)
10(2/0)

BSR

Byte
Word

18(2/2)
18(2/2)

DBCC

CC true
CC false

Size

(An)

-

-

-

12(2/0)

14(3/0)

10(2/0)

JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS

(An)+

-(An)

d(An)

-

8(2/0)

12(2/0)

8(210)

12(3/0)

13(2/0)

12(2/0)

16(2/2)

20(2/2)

16(212)

20(3/2)

16(2/2)

20(2/2)

16 + 4n
(4 + n/O)

18 +4n
(4 + n/O)

16 + 4n
(4 + n/O)

20 + 4n
(5 + n/O)

16 + 4n
(4 + n/O)

18 + 4n
(4 + n/O)

16 + 8n
(4 + 2n/0)

18 + 8n
(4 + 2n/0)

16 + 8n
(4 + 2n/0)

20 + 8n
(5 + 2n/0)

16 + 8n
(4 + 2n/0)

18 + 8n
(4 + 2n/0)

-

-

xxx.W

deAn, Ix)' +

xxx.L

Word

12 + 4n
(3 + n/O)

12 + 4n
(3 + n/O)

-

Long

12 + 8n
(3 + 2n/0)

12 + 8n
(3 + 2n/0)

-

Word

8 + 4n
(2/n)

8 + 4n
(2/n)

12 + 4n
(3/n)

14 + 4n
(3/n)

12 + 4n
(3/n)

16 + 4n
(4/n)

Long

8 + 8n
(2/2n)

-

8 + 8n
(2/2n)

12 + 8n
(3/2n)

14 + 8n
(3/2n)

12 + 8n
(3/2n)

16 + 8n
(4/2n)

-

8(2/0)

JSR

-

16(2/2)

LEA

-

4(1/0)

PEA

-

12(1/2)

MOVEM
R-M

Branch Not Taken

Byte
Word

JMP

MOVEM
M-R

Branch Taken

BCC

Table 32.
Instr

Conditional Instruction Clock Periods

d(PC)

d(PC. Ix)'

10(2/0)

14(3/0)

10(2/0)

12(3/0)

10(2/0)

14(3/0)

18(2/2)

22(2/2)

18(2/2)

20(3/2)

18(2/2)

22(2/2)

n is the number of registers to move
, The size of the index register (ix) does not affect the Instruction's execution time

Table 33.

MULTI-PRECISION INSTRUCTION CLOCK PERIODS
Table 33 delineates the number of clock periods for the multiprecision instructions. The number of ciock pcnodc ~nclucoo the
time to fetch both operands, perform the operations, store the
results, and read the next instructions. The number of read and
write cycles is shown in parenthesis as: (r/w).
In Table 33, the headings have the following meanings: Dn = data
register operand and M =memory operand.

1-49

Multi-Precision Instruction Clock Periods

Instruction

Size

op On, On

op M, M

ADDX

Byte. Word
Long

4(1/0)
8(1/0)

18(3/1)
30(5/2)

GMPM

Byte, Word
Long

-

SUBX

Byte, Word
Long

4(1/0)
8(1/0)

18(3/1)
30(5/2)

ABCD

By1e

6(1/0)

18(3/1)

SBCD

Byte

6(1/0)

18(3/1)

12(3/0)
20l~/0)

R68000

16·Bit MPU

MISCELLANEOUS INSTRUCTION CLOCK PERIODS

EXCEPTION PROCESSING CLOCK PERIODS

Table 34 and 35 indicate the number of clock periods for the
following miscellaneous instructions. The number of bus read
and write cycles is shown in parenthesis as: (r/w). The number
of clock periods plus the number of read and write cycles must
be added to those of the effective address calculation where
indicated.

Table 36 delineates the number of clock periods for exception
processing. The number of clock periods includes the time for
all stacking, the vector fetch, and the fetch of the first instruction of the handler routine. The number of bus read and write
cycles is shown in parenthesis as (r/w)

Table 34.
Instruction

Miscellaneous Instruction Clock Periods
Instruction

Size

Register

Memory

ANDI to CCR

Byte

20(3/0)

-

LINK

ANDI to SR

Word

20(3/0)

-

MOVE from USP

-

CHK

10(110)+

EORI to CCR

Byte

20(3/0)

EORI to SR

Word

20(3/0)

ORI to CCR

Byte

20(310)

ORI to SR

Word

20(3/0)

MOVE from SR
MOVE to CCR
MOVE to SR
EXG

Word
Long

EXT

Size

Regloter

Memory

16(2/2)

-

RTE

-

RTR

-

20(5/0)

RTS

-

16(4/0)
4(010)

MOVE to USP
NOP
RESET

6(110)

8(1/1)+

12(2/0)

12(2/0)+

STOP

-

12(2/0)

12(2/0) +

SWAP

6(1/0)

-

TRAPV

4(1/0)
4(110)

-

UNLK

-

-

4(110)
4(1/0)

4(110)
132(1/0)
20(5/0)

4(1/0)

4(110)
12(3/0)

+ add effective address calculation time

Table 35.

Move Peripheral Instruction Execution Times

Instruction

Size

Register_ Memory

Memory_Register

MOVEP

Word
Long

16(2/2)
24(2/4)

16(4/0)
24(6/0)

Table 36.

Exception Processing Clock Periods

Exception

Periods

Address Error

50(4/7)

Bus Error

50(4/7)

CHK Instruction

44(5/4)+

Divide by Zero

42(5/4)

Illegal Instruction

34(4/3)

Interrupt

44(5/3)"

Privilege Violation

34(4/3)

RESET""

40(6/0)

Trace

34(4/3)

TRAP Instruction

38(4/4)

TRAPV Instruction

34(4/3)

+ add effective address calculation time
" The Interrupt acknowledge cycle IS assumed to take four clock
periods
"" Indicates the time from when RESET and HALT are first sampled
as negated to when Instruction execution starts

1-50

R68000

16-Bit MPU

MAXIMUM RATINGS

Where:

Rating

Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to +7.0

V

Input Voltage

VIN

-0.3 to + 7.0

V

TA

TL to TH
o to 70

°c

TSTG

-56 to 150

°c

Operating Temperature Range
Storage Temperature

TA ., Ambient Temperature, °C
8JA ., Package Thermal Resistance, Junction-toAmbient, °C/W
PD ., PINT + PI/a
PINT" ICC· VCC, Watts-Chip Internal Power
PI/a ., Power Dissipation on Input and Output PinsUser Determined

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
64-Pm Ceramic
64-Pm Plastic Dip

Symbol

Value

Unit

30
55 ±5

°C/W
°C/W

8JA

For most applications PI/a  2.9 kll

910 Il

MM06150
OR EQUIVALENT

MM07000
OR EQUIVALENT

I

1130PF

Figure 41. RESET Test Load

CL=130 pF
(INCLUDES ALL PARASITICS)
RI..::.6.0 kll FO~
AS, A1-A23, BG, 00-015, E
FCO-FC2, LOS, Riw, UOS, VMA
R·=1.22 kll FOR A1-A23, BG,
FCO-FC2

70PF

Figure 43. Test Loads

Figure 42. HALT Test Load

CLOCK TIMING (See Figure 44)
4 MHz
Characteristic

Symbol

Min

6 MHz

Max

Min

8 MHz

Max

Min

10 MHz

Max

12.5 MHz

Min

Max

Min

Max

Unit

F

2.0

4.0

2.0

6,0

2.0

8.0

2.0

lQ,Q

4,0

12.5

MHz

Cycle Time

Icyc

250

500

167

500

125

500

100

500

80

250

ns

Clock Pulse Width

tCl
tCH

115
115

250
250

75
75

250
250

55
55

250
250

45
45

250
250

35
35

125
125

ns

-

10
10

-

10
10

-

10
10

-

10
10

-

5
5

ns

Frequency 01 Operation

Rise and Fall Times

ICr
tel

-

-

-

~-------tcyc - - - - - - . j

tCH

Figure 44. Input Clock Waveform

1-52

c

16-Bit MPU

R68000
AC ELECTRICAL SPECIFICATIONS - READ AND WRITE CYCLES
(V cc = 5 0 Vd c ± 50;'0, Vss = 0 Vd c; TA = T L t0 T H, see FIgures 45 an d 46)
4 MHz
Num.

Characteristic

Symbol

Min

6 MHz

Max

Min

Min

12.5 MHz

10 MHz

8 MHz

Max

Max

Min

Max

Min

Max

Unit

1

Clock Period

tcvc

250

500

167

500

125

500

100

500

80

250

ns

2

Clock Width Low

tCL

115

250

75

250

55

250

45

250

35

125

ns

3

Clock Width High

tCH

115

250

75

250

55

250

125

ns

4

Clock Fall Time

tCI

-

10

-

10

5

ns

10

80

100

-

Clock High to FC Valid

tCHFCV

-

90

-

7

Clock High to Address Data
High Impedance (Maximum)

tCHAZx

-

120

-

8

Clock High to Address/FC
Invalid (Minimum)

tCHAZn

9'

Clock High to AS, DS Low
(Maximum)

tCHSLx

10

Clock High to AS, DS Low
(MInimum)

tCHSLn

112

Address to AS, DS (Read)
Low/AS Write

tAVSL

55

-

35

-

11A2

FC Valid to AS, DS (Read)
Low/AS Write

tFCVSL

80

-

70

-

12'

Clock Low to AS, DS High

tCLSH

-

90

-

132

AS, DS High to Address/FC
Invalid

tSHAZ

60

-

40

142

AS, DS Width Low (Read)/AS
Write

tSL

535

-

tDWPW

285

tSH

285

5

Clock Rise Time

6

Clock Low to Address

tCLAV

6A

14A2

tCr

DS Width Low (Write)

90

0
-

80

0

10

80

-

0

-

70

45

250

35

10

-

10

10

-

10

70

-

60

-

70
80

0

-

60

60
70

0

-

55

0
-

5

ns

55

ns

55

ns

60

ns

-

ns

55

ns

-

0

-

0

-

ns

-

20

-

0

-

ns

60

-

50

-

40

-

ns

80

-

70

-

55

-

50

ns

-

30

-

20

-

10

-

ns

337

-

240

-

195

-

160

-

ns

-

170

-

115

-

80

-

ns

150

-

95

180

105

-

65

-

ns
ns

-

-

0
..-

0
-30

152

AS, DS Width Hlgh

16

Clock High to AS, DS High

tCHSZ

-

120

-

100

-

80

-

70

-

60

t72

AS, DS High to R/W High

tSHRH

60

-

50

-

40

-

20

-

10

-

ns

18'

Clock High to R/W High
(Maximum)

tCHRHx

-

90

-

80

-

70

-

60

-

60

ns

19

Clock High to R/W High
(MInimum)

tCHRHn

20'

Clock High to R/W Low

tCHRL

-

80

tASRV

-

90

AS Low to R/W Valid

20

-

20

tAVRL

45

25

tFCVRL

80

-

70

20A6
212
21A2

Address Valid to R/W Low
FC Valid to R/W Low

a

-

a

-

a

-

ns

-

70

60

ns

20

ns

20

-

-

ns

60

-

50

30

50

-

30

-

ns

140

-

-

a

60

-

a

70

55

-

55

ns

80

-

70

-

60

ns

-

0

-

a

20

20

222

R/W Low to DS Low (Write)

tRLSL

200

23

Clock Low to Data Out Valid

tCLOO

-

90

-

80

24

Clock High to R/W, VMA
High Impedance

tCHRZ

-

120

-

100

-

25 2

DS High to Data Out Invalid

tSHDO

60

-

40

-

30

-

20

-

ns

Data QuI Valid to IJS
(Write)
Data In to Clock Low
(Setup Time)

'COSL

55

-

35

-

30

-

20

-

15

26 2

15

-

ns

tDICL

30

-

25

-

15

-

10

-

10

-

45

-

45

-

45

-

45

275

Lo~]

27A

Late BERR Low to Clock Low
(Setup Time)

tBELCL

45

28 2

AS, DS High to DTACK High

tSHDAH

a

490

a

1-53

325

80

a

245

a

190

0

ns

ns

-

ns

150

ns

•

16-Bit MPU

R6S000
AC ELECTRICAL SPECIFICATIONS -

READ AND WRITE CYCLES (CONTINUED)
4 MHz

Num.

Characteristic

29

DS High to Data Invalid
(Hold Time)

Symbol

tSHDI

30

AS, DS High to BERR High

tSHBEH

31 2

DTACK Low to Data In
(Setup Time)

tDALDI

32

HALT and RESET Input
Transition Time

tRHr,f

Min

0
0

-

6 MHz
Max

-

-

0

180

0

Min

0

-

200

8 MHz

Max

-

0

120

0

Min

0

-

200

90

-

80

90

-

80

10 MHz

Max

-

-

0

90

0

Min

0

-

200

65

0

-

200

33

Clock High to BG Low

tCHGL

34

Clock High to BG High

tCHGH

35

BR Low to BG Low

tBRLGL

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

36

BR High to BG High

tBRHGH

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

37

BGACK Low to BG High

tGALGH

15

3.0

1.5

3.0

15

30

15

3.0

37A

BGACK Low to BR High
(to Prevent Rearbitration)

tBGKBR

30

-

25

-

20

-

20

38

BG Low to Bus High
Impedance (with AS High)

tGLZ

-

120

-

100

-

80

-

tGH

15

-

15

-

15

-

tCLVML

90

80

-

70

100

85

-

25

-

25

-

240

-

39

BG Width High

40

Clock Low to VMA Low

41

Clock Low to E Transition

42

E Output Rise and Fall Time

tEr,f

-

43

VMA Low to E High

tVMLEH

325

44

AS, DS High to VPA High

tSHVPH

0

45

E Low to AddressNMA/FC
Invalid

tELAI

55

-

46

BGACK Width

tBGL

1.5

475

Asynchronous Input
Setup Time

tASI

30

-

f---

48 3

BERR Low to DTACK Low

49

E Low to AS, OS Invalid

50

tCLC

tBELDAL

30

tELSI

-80

E Width High

tEH

900

51

E Width Low

tEL

1400

52

E Extended Rise Time

tCIEHX

53

Data Hold from Clock High

tCHDO

0

54

Data Hold from E Low (Wnte)

tELDOZ

55

RIW to Data Bus Impedance
Change

564

HAL T/RESET Pulse Width

-

240

80

70

12.5 MHz

Max

0
0

0

-

Max

Unit

-

ns

-

ns

50
200

ns
ns

50

ns

50

ns

1.5

3.5

Clk Per.

1.5

3.5

Clk. Per.

15

30

Clk. Per.

-

20

-

ns

70

-

60

ns

15

-

1.5

-

Clk. Per.

-

70

70

ns

70

-

55

45

ns

-

25

-

25

-

25

ns

200

-

150

-

90

-

ns

70

60

Min

60

160

0

120

0

90

0

70

ns

35

-

30

-

10

-

10

-

ns

1.5

-

1.5

-

Clk. Per

20

-

1.5

20

-

1.5

25

ns

0

20

ns

25

-

20

-

20

-

20

-80

-

-80

-

-80

-

-80

-

600

-

450

350

-

280

ns

-

700

550

-

-

900

-

440

-

ns

-

80

-

80

-

80

-

80

ns
ns

Clk. Per.

30

35

-

10

-

60

-

40

tRLDO

55

-

tHRPW

10

-

0

20

30

-

10

-

0

20

-

10

-

10

-

10

-

0

0
15

ns

ns
ns

Notes:
1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the value given In these columns.
2. Actual value depends on clock penod.
3. If #47

IS

satisfied for both DTACK and BERR, #48 may be 0 nanoseconds.

4. For power up, the MPU must be held in RESET state for 100 ms to stabilize all on-chip circUitry. After the system is powered up, #56 refers
to the minimum pulse width required to reset the system.
5 If the asynchronous setup time (#47) requirements are sallsfled the DTACK low-to-data setup time (#31) requirement can be ignored. The data
must only satisfy the data-In clock-low setup time (#27) for the following cycle.
6. When AS and RIW are equally loaded (± 20%). subtract 10 nanoseconds from the value given in these columns.

1-54

R68000

16-Bit MPU

ASYNCHRONOUS-----------------------r--~~--~~------~~----------­

INPUTS
(NOTE 1)
HALTIRESET

BERRIBR --------------------------,
(NOTE 2)

DATA IN -

-

-- -

-

-

-

-

-- - - -

-

-

-

NOTES:
1. SETUP TIME FOR THE ASYNCHRONOUS INPUTS BGACK, IPLD-IPL2, AND VPA GUARANTEES THEIR RECOGNITION AT THE
NEXT FALLING EDGE OF THE CLOCK.
2. BR NEEDS FALL AT THIS TIME ONLY IN ORDER TO INSURE BEING RECOGNIZED AT THE END OF THIS BUS CYCLE.
3. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF
2.0 VOLTS, UNLESS OTHERWISE NOTED.

Figure 45.

Read Cycle Timing

1-55

16-Bit MPU

R68000

S1

SO

CLK
----'

.......;

A1-A23

...
J

LDS/UDS

...I

~ r- .....

*-0

~@
-

@-+

@- ~

-+

-

<-

~@)

0
(A

S7

SO

~

-0

~

~ ~@

DATA OUT

S6

S5

S4

S3

F-\~~~ ~ ~ ~
~ f--0

R/W

FCO-FC2

S2

-...

r- @

@-.

~

0

....

e

r-@.....

~

Ie-

.-@
:---

...

-

I.-

-X -

~

@

.... f-- - @ 1- *-®

-8--

/

~@

®

1l=®

ASYNCHRONOUS
INPUTS

>i'"

~ r--@
@--+ ~
f-®--+

~

@)

r-@-

I---®+-@) ....

/~

\-

@

-

-®

r---@_

J

~

NOTES:
1. BECAUSE OF LOADING VARIATIONS, RiW MAY BE VALID AFTER AS EVEN THOUGH BOTH ARE INITIATED BY THE RISING
EDGE OF S2 (SPECIFICATION 20A).
2. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF
2.0 VOLTS, UNLESS OTHERWISE NOTED.

Figure 46.

Write Cycle Timing

1-56

16·Bit MPU

R68000
AC ELECTRICAL SPECIFICATIONS - BUS ARBITRATION
= 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = 0° to 70 0 e. See Figure 47.)

(Vee

Num.

Characteristic

Symbol

4 MHz
Min

6 MHz

8 MHz

Max

Min

Max

90
90

-

10 MHz

Min

Max

80

-

80

-

12.5 MHz
Unit

Min

Max

Min

Max

70

-

60

-

50

ns

70

-

60

-

50

ns

33

Clock High to

Em Low

ICHGL

34

Clock High to BG High

tCHGH

35

BR Low to BG Low

tBRLGL

1.5

3.5

15

3.5

1.5

35

1.5

35

15

3.5

Clk. Per

36

BR High to BG High

tBRHGH

15

35

1.5

35

1.5

35

15

35

15

3.5

Clk Per

37

BGACK Low 10 BG High

tGALGH

1.5

3.0

15

30

15

3.0

15

30

1.5

30

Clk Per

37A

BGACK Low to BR High
(IO Prevent Rearbllrallon)

tBGKBR

30

-

25

-

20

-

20

-

20

-

ns

38

BG Low to Bus High
Impedance (with AS High)

tGLZ

-

120

-

100

-

80

-

70

-

60

ns

39

Em Width

tGH

15

15

tBGL

15

-

1.5

-

Clk Per

15

-

-

1.5

-

15

BGACK Wldlh

-

1.5

46

High

-

15
----1.5

Clk. Per

THESE WAVEFORMS SHOULD ONLY BE REFERENCED IN REGARD TO THE EDGE-TO-EDGE MEASUREMENT OF THE TIMING
SPECIFICATIONS. THEY ARE NOT INTENDED AS A FUNCTIONAL DESCRIPTION OF THE INPUT AND OUTPUT SIGNALS.
REFER TO OTHER FUNCTIONAL DESCRIPTIONS AND THEIR RELATED DIAGRAMS FOR DEVICE OPERATION.

STROBES
AND R/W - - - - - - - - - '

I+---@--+I

CLK

NOTES:
1. SETUP TIME FOR THE ASYNCHRONOUS INPUTS BERR, BGACK, BR, DTACK, IPLO-IPL2, AND VPA GUARANTEES THEIR
RECOGNITION AT THE NEXT FALLING EDGE OF THE CLOCK.
2. WAVEFORM MEASUREMENTS FOR ALL INPUTS AND OUTPUTS ARE SPECIFIED AT: LOGIC HIGH=2.D VOLTS,
LOGIC LOW = 0.8 VOLTS

Figure 47.

AC ELECTRICAL Waveforms -

1-57

Bus Arbitration

R68000

16-Bit MPU

64-PIN CERAMIC DUAL IN·LINE PACKAGE {DIP}

:i

[
vF

I

I-

DIM
A
B
C
D
F
Cl

]!
-.I-.l

j
A

J
K
L
M
N

j

MILLIMETERS
MIN
MAX
80.52
82.04
22.20
2296
305
432
038
053
076
140
2.54 BSC
0.20
0.33
254
4.19
2281
23.11
10·
102
152

INCHES
MIN
MAX
3.170
3.230
0.878
0904
0120
0170
0015
0021
0055
0030
0.100 BSC
0.008
0.013
0.100
0185
0.890
0910
10·
0.060
0040

MILLIMETERS
MIN
MAX
4110
41.81
17.02
1723
356
4.58
0.48
056
1905 BSC
23.50 BSC
127 BSC
018
033
292
318
483
534

INCHES
MIN
MAX
1818
1838
0.870
0890
0140
0180
0018
0022
0750 BSC
0925 BSC
0050 BSC
0007
0013
0115
0125
0190
0210

W~A

..j.~~,----=1~.

~~D

64·PIN PLASTIC QUAD IN·LINE PACKAGE {QUIP}

DIM
A
B
C
D
El
E2
G

.,nn~nnn~nnnnnnn~nnnnnnnnnnnnn~n~

J

"T

Kl

K2

jj
~:~
)

r,o

~

"

"

~+f,:~~
J-lI-

1-58

TT

16-Bit MPU

R6S000
PACKAGE DIMENSIONS
68-PIN PLASTIC CHIP CARRIER (PCC)

~SEATING

PLANE

1

TOP VIEW

SIDE VIEW

~!~/TT777TTTTT777

"Tlil-t----:T'r-i-'-

114

I-

04----t
05----.,

SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)

CHAM.J x 45°

2121
2096
2223
2248
127
1 143 TYP
0254 TYP

INCHES
MAX
MIN
145
149
072
076
071
075
054
058
091
097
008
012
018 TYP
985
995
945
955
795
805
915
925
825
835
875
885
050 SSC
045 TYP
010 TYP

.2

4° TYP
10° TYP
45° TYP

4° TYP
10° TYP
45° TYP

R
R1

0889 TYP
0254 TYP

035 TYP

DIM
A
A1
A2
A3
A4
AS

b

17 PINS
CHAM.
h x 45° PER SIDE
3 PLCS EQUALLY
SPACES

EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)

BOTTOM VIEW

1-59

0
01
02
03
04
05

.
h
J

.

.1

MILLIMETERS
MAX
MIN
3785
3683
1829
1930

1803

1905

1372
1473
2311
2464
0203
0305
0457 TYP

2502
2400
2019
2324

2527
2426
2045
2350

sse

010 TYP

R68265 • R68465

'1'

Rockwell

R68265, R68465
DOUBLE-DENSITY FLOPPY DISK

CONTROLLER (DDFDC)
PRELIMINARY

DESCRIPTION

FEATURES

The R68465 Double-Density Floppy Disk Controller (DDFDC)
interfaces up to four floppy disk drives to a 68000/68008
microprocessor-based system. The DDFDC simplifies the system
design by minimizing both the number of external hardware components and software steps needed to implement the floppy disk
drive (FDD) interface. Control signals supplied by the DDFDC
reduce the number of components required in external phase
locked loop and write precompensation circuitry. Memorymapped registers containing commands, status and data simplify
the software interface. Built-in functions reduce the software
overhead needed to control the FDD interface. The DDFDC supports both the IBM 3740 Single-Density (FM) and IBM System
34 Double-Density (MFM) formats.

• Address mark detection circuitry
• Software control of
-Track stepping rate
-Head load time
-Head unload time
• Writes in:
-IBM compatible (single- and double-density format (R68465)
-Sony compatible (EMCA) format (R68265)
• Reads
-IBM compatible format (R68265 and R68465)
-Sony compatible format (R68265)
• Programmable data record lengths: 128, 256, 512, 1024,
2048, 4096 or 8192 bytes/sector

The R68265 interfaces to the 3Y2" Sony Micro Floppy disk drive
as well as 5%" and 8" drives. The R68265 writes in the 3'/2"
Sony compatible format and can also read from disks formatted
in IBM compatible format. Any combination of up to four 3'/2",
5%" and 8" drives can be interfaced to and controlled by the
R68265. The R68265 is pin-compatible with, and electrically
identical to, the R68465.

• Multi-sector and multi-track transfer capability
• Controls up to four floppy disk drives
• Data scan capability-will scan a single sector or an entire
track of data fields, comparing on a byte-by-byte basis data
in the processor's memory with data read from the disk

The DDFDC interfaces directly to the 68000/68008 asynchronous
microprocessor bus and operates with 8-bit byte length data
transferred on the bus. The DDFDC will operate in either DMA
or non-DMA mode. In DMA mode, the MPU need only load the
command into the DDFDC and all data transfers occur under
DMA control. The R68265/R68465 is directly compatible with
the MC68440 Dual Direct Memory Access Controller (DDMAC).
In non-DMA mode, the DDFDC generates an interrupt to the
MPU indicating that a byte of data is available.

• Data transfers in DMA or non-DMA mode
• Parallel seek operations on up to four drives
• Directly compatible with 68000 16-bit and 68008 8-bit asynchronous microprocessor bus
• Single phase 8 MHz clock
• Single + 5 volt power supply

Controller commands, command or device status, and data are
transferred between the DDFDC and the MPU via six internal
registers. The Main Status Register (MSR) stores the DDFDC
status information while four additional status registers provide
result information to the MPU following each controller command. The Data Register (DR) stores actual disk data, parameters, controller commands and FDD status information for use
by the MPU.

ORDERING INFORMATION

The DDFDC executes 15 separate multi-byte commands:
Read Data
Write Data
Read Deleted Data
Write Deleted Data
Read a Track
Read ID
Seek
Recalibrate (Restore to Track 0)

Part Number
R68265_
R68465

Specify
Format a Track
Scan Equal
Scan High or Equal
Scan Low or Equal
Sense Interrupt Status
Sense Drive Status

1

Document No. 68650N08
1-60

elK Frequency

Temperature Range

8 MHz

DOC to lDoC

Package: C = Ceramic
P = Plastic

Product Description Order No. 707
Rev. 4, October 1984

R68265, R68465

Double-Density Floppy Disk Controller (DDFDC)

00-07

ROW

..l\

ROD

-vi
PROCESSOR
ASYNCHRONOUS
BUS
INTERFACE

VCO
FOD
SERIAL
DATA
INTERFACE

WCK
WOA
WE

RESET

PSO-PS1

CS

I\.

RS
ROY;>

IRQ

lOX

RIW

OMAC
INTERFACE

{

WPITS

OOFOC

DTACK

FlTITRKO
lCTlDIR

OACK

FR/STP

DONE

RW/SEEK

REQ

HDl

ClK

usa

Vee

US1

HDSEl

GND

FDD
CONTROL/STATUS
INTERFACE

MFM

•

Figure 1. DDFDC Input and Output Signals

PIN DESCRIPTION

RS-Data/Status Register Select. This input selects the Data
or Status Register for reading from or writing to. When
RS = high, the Data Register is selected and the state of RiW
determines whether it is a read (RiW .. high) or a write
(RiW low) operation. when RS low, the Status Register is
selected. This register may only be read (RiW = high); the state
RW· .. low is invalid when the Status Register is selected.

Throughout this document signals are presented using the terms
active and inactive, or asserted and negated, independent of
whether the signal is active in the high-voltage state or lowvoltage state. (The active state of each logic pin is described
below.) Active low signals are denoted by a superscript bar. For
example, RiW indicates read is active high and a write is active
low.

=

=

IRQ-Interrupt Request. This active low output is the interrupt
request generated by the DDFDC to the MPU. IRQ is asserted
upon completion of some DDFDC commands and before a data
byte is transferred between the DDFDC and the data bus (in the
Non-DMA mode).

BUS INTERFACE
DO-D7-Data Lines. The bidirectional data lines transfer data
between the DDFDC and the a-bit data bus.
ClK-ClOCK. The clock is a TTL compatible a MHz square
wave signal.

RtW-ReadlWrite. This input defines the data bus transfer as a
read or write cycle. When high (read), the data transfer is from
the DDFDC to the data bus. When low (write), the data transfer
is from the data bus to the DDFDC.

RESET-RESET. This active low input places the DDFDC in the
idle state and resets the output lines to the floppy disk drives
to the low state. RESETdoes not afiect the Step Rate Time (SRT),
Head Unload Time (HUT) or Head Load Time (HLT) set by a
specify command. If RDY goes high while RESET is low, the
DDFDC will assert IRQ within 1.024 ms. This interrupt can be
cleared by issuing a Sense Interrupt Status command.

DTACK-Data Transfer Acknowledge. This signal is the asynchronous handshake line for information transfer on the 68000
system bus. It is generated by the DDFDC as an acknowledge
to the CS signal in an asynchronous transfer. A low output
indicates that valid data is on the bus (read cycle) or that data
has been written (write cycle). Except when being asserted, this
signal is normally in the high impedance state.

CS-Chip Select. The DDFDC is selected when the CS input
is low.

1-61

R68265, R68465

Double-Density Floppy Disk Controller (DDFDC)

The output characteristics of DTACK are the same as other
'system interface signals with allowances for an external pull·
up resistor such that the output is driven to the high level first
and then to the high impedance state.

FDD CONTROL/STATUS INTERFACE

DIRECT MEMORY ACCESS CONTROLLER
(DMAC) INTERFACE

lOX-Index. An active high input signal from the FDD indicates
the index hole is under the index sensor. Index is used to syn·
chronize DDFDC timing.

ROY-Ready. An active high input signal indicates the FDD is
ready to send data to, or receive data from, the DDFDC.

DACK-DMA Acknowledge. The DMA transfer acknowledge
signal is a TTL compatible input generated by the DMA controller
(DMAC) controlling the DDFDC. The DMA cycle is active when
DACK is low and the DDFDC is performing a DMA transfer.

RW/sEEK-Reed Wrlte/Seek. Mode selection signal to the FDD
which controls the multiplexer from the multiplexed signals.
When RW/SEEK is low, the ReadlWrite mode is commanded;
when RW/SEEK is high, the Seek mode is commanded.

REQ-Data DMA Request. The transfer request signal is a TTL
compatible output generated by the DDFDC to request a data
transfer operation under control of the DMAC (in the DMA mode).
The request is active when REO = low. The signal is reset
inactive when DMA Acknowledge (DACK) is asserted (low).
DONE-DMA Transfer Complete. This input signal is issued to
the DDFDC when the DMA transfer for a channel is complete.
The signal is active low concurrent with the DACK input when
the DMA operation is complete as a result of that transfer.

RWISEEK

Mode

Active FDD Interface Signals

Low

ReadlWrite

High

Seek

Wp, FlT, lCT, FR
TS, TRKO, DIR, STP

WPITS-Wrlte Protect/lWo Side. An active high multiplexed
input signal from the FDD. In the ReadlWrite mode, WP/TS high
indicates the media is write-protected. In the Seek mode, WP/TS
high indicates the media Is two·sided.

FDD SERIAL DATA INTERFACE
FLTITRKO-FaultlTrack Zero. An active high multiplexed input
from the FDD. In the ReadlWrite mode (RWISEEK = low),
FLTITRKO high indicates an FDD fault. In the Seek mode,
FLTITRKO high indicates that the readlwrite head is positioned
over track zero.

RDD-Read Data. Read Data input from the floppy disk drive
(FDD) containing clock and data bits.
ROW-Read Data Window. Data Window input generated by
the Phase Locked Loop (PLL) and used to sample data from
the FDD.
VCO-Voltage Controlled Oscillator Sync. This output signal
inhibits the VCO in the PLL circuit when low and enabies the
VCO in the PLL circuit when high. This inhibits RDD and RDW
from being generated until valid data is detected from the FDD.

RESET
DTACK

Rfii
WCK-Write Clock. This input clock determines the Write Qata
rate to the FDD. The data rate is 500 KHz in the FM mode
(MFM = low) and 1 MHz in the MFM mode (MFM = high). The
pulse width is 250 ns (typical) in both modes.

CS
RS
DO
D1
D2
D3
D4
D5
D6
D7

WDA-Wrlte Data. Serial write data output to the FDD contain·
ing both clock and data bits.
WE-Write Enable. This output Signal enables the Write Data
into the FDD when high.
PSO-PS1-PreshHt. These outputs are encoded to convey write
compensation status during the MFM mode to determine early,
late or normal times as follows:

REQ
DACK
DONE
IDX
IRQ
ClK
GND

Preshlft Outputs
Write Precompensstion Status

PSO

PS1

Normal
Late
Early
Invalid

0
0

0

o=

1
1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

1

a
1

low, 1 = High

Pin Diagram

1·62

vee
RWISEEK
LCT/DIR
FRISTP
HDL
RDY
WP/TS
FlT/TRKO
PSO
PS1
WDA
USO
US1
HDSEl
MFM
WE
VCO
RDD
RDW
WCK

R68265, R68465

Double-Density Floppy Disk Controller (DDFDC)
USO-US1-Unit Select. Output signals for floppy disk drive
selection as follows:

LCT/DIR-Low Current/Direction. A multiplexed output to the
FDD. In the ReadlWrite mode, LCTIDIR is low when the
read/write head is to be positioned over the inner tracks and the
LCT/DIR is high when the head is to be positioned over the outer
tracks. In the Seek mode, LCT/DIR controls the head direction.
When LCT/DIR is high, the head steps to the outside of the disk;
when LCT/DIR is low, the head steps to the inside of the disk.

Unit Select

usa

US1

Floppy Disk
Drive Select

0
0

0

0

1
1

FR/STP-Fault Reset/Step. A multiplexed output to the FDD.
In the ReadlWrite mode, FR/STP high resets the fault indicator
in the FDD. An FR pulse is issued at the beginning of each read
or write command prior to issuing HDL. In the Seek mode,
FRlSTP provides the step pulses to move the read/write head
to another track in the direction indicated by the LCTIDIR signal.

o=

1

1

0

2
3

1

Low, 1 = High

MFM-MFM Mode. Output signal to the FDD to indicate MFM
or FM mode. Selects the MFM mode when MFM = high and
the FM mode when MFM = low.

HDL-Head Load. An active high output to notify the FDD that
the read/write head should be loaded (placed in contact with
the media). A low level indicates the head should be unloaded.

VCC-Power. +5V dc.
GND-Ground (VSS>.

HD-Head Select. An output to the FDD to select the proper
read/write head. Head One is selected when HD = high and
Head Zero is selected when HD = low.

110

00·07

RESET

~

RtW

~

CS
RS

BUFFERS

SERIAL
READ
CONTROL

OPERATION
CONTROL

SERIAL
WRITE
CONTROL

DTACK

----

ROY

oJ

lOX

¢: INPUT

FDC)
Command Phase:
RIW
BYTE

If the OOFOC finds an error in the 10 or Data CRC check bytes,
it continues to read data from the track. The OOFOC compares
the 10 information read from each sector with the value stored
in the lOR, and sets the NO flag in ST1 to a 1 if there is no match.

W·

If the OOFOC does not find an 10 Address Mark on the disk after
it encounters the Index Hole for the second time it terminates
the command, sets the Missing Address Mark (MA) flag in ST1
to a 1, and sets bits 7 and 6 of STO to 0 and 1, respectively.

Command Phase:
BYTE
RIW
W

1

5

4

3

2

1

MF

0

0

1

0

1

0

2

X

X

X

X

X

HD

US!

usa

R

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

7

6

5

4

3

2

1

0

6

Sector Number (R)

0

·MF

SK

0

0

0

1

0

7

Number of Data Bytes per Sector (N)

X

X

X

X

HD

US1

usa

2

X

3

Track Number (T)

4

Head Number (H)

5

Sector Number (R)

6

Number of Data Bytes per Sector (N)

7

End of Track (EOT)

8

Gap length (GPL)

9

Data length (DTl)

1

Status Register 0 (STO)

2

Status Register 1 (ST 1)

3

. Status Register 2 (S1"2)

4

6

0

FORMAT A TRACK
The six-byte Format a Track command formats an entire track.
After the Index Hole is detected, data is written on the disk: Gaps,
Address Marks, 10 fields and Data fields; all are recorded in
either the double-density IBM System 34 format (MF = 1) or
the single-density IBM 3740 format (MF = 0). The particular format written is also controlled by the values of Number of
Bytes/Sector (N), SectorslTrack (ST), Gap Length (GPL) and
Data Pattern (D) which are supplied by the processor during the
command phase. The Data field is filled with the data pattern
stored in O.
The 10 field for each sector is supplied by the processor in
response to four data requests per sector issued by the OOFOC.
The type of data request depends upon the Non-OMA flag (NO)
in the Specify command. In the OMA mode (NO = 0), the
ODFOC asserts the OMA Request (ORQ) output four .times per
sector. In the Non-OMA mode (NO = 1), the OOFOC asserts
Interrupt Request (IRQ) output four times per sector.

Track Number (T)

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector (N)

0

Result Phase:

Result Phase:
R

7

1

The processor must write one data byte in response to each
request, sending (in the consecutive order) the Track Number
(T), Head Number (H), Sector Number (R) and Number of Bytes/
Sector (N). This allows the disk to be formatted with nonsequential sector numbers, if desired.
the processor must send new values for T, H, R, and N to the
OOFOC for each sector on the track. For sequential formatting
R is incremented by one after each sector is formatted, thus,
R contains the total numbers of sectors formatted when it is read
during the result phase. This incrementing and formatting continues for the whole track until the DOFOC, upon encountering
the Index Hole for the second time, terminates the command
and sets bits 7 and 6 in STO to O.

READID
The two-byte Read 10 command returns the present position of
the read/write head. The OPFOC obtains the value from the first
10 field it is able to read, sets bits 7 ana 6 in STO to 0 and terminates the command.
If no proper 10 Address Mark is fQund on the disk before the
Index Hole is encountered for the second time then the Missing
Address Mark (MA) flag in ST1 is set to a 1, and if no data is
found then the NO flag to a 1 is also set in ST1. Bits 7 and 6
in STO are set to 0 and 1, respectively and the command is
terminated.

If the Fault (FLT) signal is high from the FOO at the end of a
write operation, the OOFOC sets the Equipment Check (EC) flag
in STO io a 1, sets bits 7 and 6 of STO 10 0 and 1, respectively,
and terminates the command. Also, a low (ROY) signal at the
beginning of a command execution phase causes bits 7 and 6
of STO to be set to 0 and 1, respectively.
Table 5 shows the relationship between N, ST, and GPL for
various disk and sector sizes.

During this command there is no data transfer between OOFOC
and the data bus except during the result phase.

1-71

o

R68265,R68465

Double-Density Floppy Disk Controller (DDFDC)
Table 5.

Disk
Size

Standard Floppy Disk Sector Size Relationship

Sector Size
Bytes/Sector

No. of Data
Bytes/Sector
(N)

No. of
Sectors/Track
(ST)

FM

128
256
512
1024
2048
4096

00
01
02
03
04
05

MFM3

256
512
1024
2048
4096
8192

Gap Le!'lgth (GPL)4·

lA
OF
08
04
02
01

ReadlWrite
Command 1
07
OE
1B
47
C8
C8

Format
Command 2
lB
2A
.3A
8A
FF·
FF

01
02
03
04
05
06

1A
OF
08
04
02
01

OE
lB
35
99
C8
C8

36
54
74
FF
FF
FF

FM

128
128
256
512
1024
2048

00
00
01
02
03
04

12
10
08
04
02
01

07
10
18
46
C8
C8

09
19
30
87
FF
FF

MFM3

256
256
512
1024
2048
4096

01
01
02
03
04
05

12
10
08
04
02
01

OA
20
2A
80
C8
C8

OC
32
50
FO
FF
FF

128
256
512

00
01
02

OF
09
05

07
OE
1B

lB
2A
3A

256
512
1024

01
02
03

OF
09
05

OE
1B
35

36
54
74

Mode

8"

5%"

FM

3'12"
MFM3

Remarks

Notes:
1. Suggested values of GPL in Read or Write commands to avoid overlapping between Data field and ID field of contiguous sections.
2. Suggested values of GPL in Format a Track command.
3. In MFM mode the DDFDC cannot perform a read/write/format operation with 128 bytes/sector (N = 00).
4. Values of ST and GPL are in hexadecimal.

Command Phase:

Result Phase:

R/W

BYTE

7

6

5

4

3

2

1

0

W

1

0

MF

0

0

1

1

0

1

2

Status Register 1 (ST1)

2

X

X

X

X

X

HD

US1

USO

3

Status Register 2 (ST2)
Track Number (T)'

R

1

Status Register 0 (STO)

3

Number of Bytes per Sector (N)

4

4

Sectors per Track (ST)

5

Head Number (Ht

5

Gap Length (GPL)

6

Sector Number (Rt

6

Data Pattern (D)

7

Number of Data Bytes per Sector (Nt

, The ID information has no meaning in this command.

1·72

Double-Density Floppy Disk Controller (DDFDC)

R68265, R68465
SCAN COMMANDS

mode). If an OR occurs, the DDFDC terminates the command
and sets bits 7 and 6 of STO to 0 and 1, respectively.

The scan commands compare data read from the disk to data
supplied from the data bus. The DDFDC compares the data, and
looks for a sector of data which meets the conditions of
DFDD = Deus, DFDD s Deus, or DFDD ~ Deus (D = the data
pattern in hexadecimal). A magnitude comparison is performed
(FF = largest number, 00 = smallest number). The hexadecimal byte of FF either from the bus or from FDD can be
used as a mask byte because it always meets the condition of
the compare. After a whole sector of data is compared, if the
conditions are not met, the sector number is incremented
(R + STP - R), and the scan operation is continued. The scan
operation continues until one of the following events occur: the
conditions for scan are met (equal, low or equal, or high or equal),
the last sector on the track is reached (EOT), or TC is received.

The following tables specify the command bytes and describe
the result bytes for the three scan commands.

SCAN EQUAL

Command Phase:

If conditions for scan are met, the DDFDC sets the Scan Hit (SH)
flag in ST2 to aI, and terminates the command. If the conditions for scan are not met between the starting sector (as
specified by R) and the last sector on the track (EOT), then the
DDFDC sets the Scan Not Satisfied (SN) flag in ST2 to aI, and
terminates the command. The receipt of TC from the processor
or DMA controller during the scan operation will cause the
DDFDC to complete the comparison of the particular byte which
is in process, and then to terminate the command. Table 6 shows
the status of bits SH and SN under various conditions of scan.
Table 6.
Command

RIW

BYTE

7

6

5

4

3

2

1

w

1

MT

MF

SK

1

a

a

a

1

2

X

X

X

X

X

HD

US1

USa

3

Track Number (T)

R

Bit 2

= SN

Bit 3

= SH

Comments

Scan Equal

a
1

1
a

Scan Low or Equal

a
a
1

1
a
a

DFDo =
DFDo
'"
D FDo =
DFDo <
DFDo >

Scan High or Equal

a
a
1

1
a
a

D FDo = DBus
DFoo > DBus
DFDO < DBus

Head Number (H)

5

Sector Number (R)

6

Number of Data Bytes per Sector (N)

7

End of Track (EDT)

8

Gap Length (GPL)

9

Sector Test Process (STP)

Result Phase:

Scan Status Codes
Status Register 2

4

a

DBus
DBus
DBus
DBus
DBus

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector (N)

SCAN LOW OR EQUAL

Command Phase:

If SK = 0 and the DDFDC encounters a Deleted Data Address
Mark on one of the sectors, it regards that sector as the last sector of the track, sets the Control Mark (CM) bit in ST2 to a 1 and
terminates the command. If SK = 1, the DDFDC skips the sector with the Deleted Data Address Mark, sets the CM flag to a
1 in order to show that a Deleted Sector has been encountered,
and reads the next sector.
When either the STP sectors are read (contiguous sectors = 01,
or alternate sectors = 02) or MT (Multi-Track) is set, the last
sector on the track must be read. For example, if STP = 02,
MT = 0, the sectors are numbered sequentially 1 through 26,
and the scan command starts reading at sector 21. Sectors 21,
23, and 25 are read, then the next sector (26) IS skipped and
the Index Hole is encountered before the EOT value of 26 can
be read. This results in an abnormal termination of the command.
If the EOT had been set at 25 or the scanning started at sector
20, then the scan command would be completed in a normal
manner.

RIW

BYTE

7

6

5

4

3

2

1

W

1

MT

MF

SK

1

1

0

0

1

2

X

X

X

X

X

HD

US1

usa

3

Track Number (T)

4

Head Number (H)

5

Sector Number (R)

6

Number of Data Bytes per Sector (N)

7

End of Track (EDT)

8

Gap Length (GPL)

9

Sector Test Process (STP)

Result Phase:
R

During a scan command data is supplied from the data bus for
comparison against the data read from the disk. In order to avoid
having the Over Run (OR) flag set in ST1, data must be available
from the data bus in less than 27 '"s (FM mode) or 13 '"s (MFM

1-73

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector (N)

0

R68265, R68465

Double-Density Floppy Disk Controller (DDFDC)

SCAN HIGH OR EQUAL

During the command phase of the Seek operation the DDFDC
sets the Controller Busy (CB) flag in the MSR to 1; but duri~g
the execution phase the CB flag is set to 0 to indicate DDFDC
non-busy. While the DDFDC is in the non-busy state, another
Seek command may be issued, and in this manner parallel seek
operations may be performed on all drives at once.

Command Phase:
RIW

BYTE

7

6

5

4

3

2

1

W

1

MT

MF

SK

1

1

1

0

1

2

X

X

X

X

X

HD

US1

usa

3

Track Number (T)

4

Head Number (H)

5

Sector Number (R)

6

Number of Data Bytes per Sector (N)

7

End of Track (EOT)

8

Gap Length (GPL)

9

Sector Test Process (STP)

0

No command other than Seek will be accepted while the DDFDC
is sending step pulses to any FDD. If a different command type
is attempted, the DDFDC will set bits 7 and 6 in STO to a 1 and
0, respectively, to indicate an invalid command.
If the FDD is in a not ready state at the beginning of the command execution phase or during the seek operation, then the
DDFDC sets the Not Ready (NR) flag in STO to a 1, sets STO
bits 7 and 6 to 0 and 1, respectively, and terminates the
command.

Result Phase:
R

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector (N)

If the time to write the three bytes of the Seek command exceeds 150 {ls, the time between the first two step pulses may
be shorter than the Step Rate Time (SRT) defined by the Specify
command by as much as 1 ms.

Command Phase:
R/W

BYTE

7

6

5

4

3

2

1

W

1

0

0

0

0

1

1

1

1

2

X

X

X

X

X

0

US1

usa

3

New Track Number (NTN)

0

SEEK
The three-byte Seek command steps the FDD read/write head
from track to track. The DDFDC has four independent Present
Track Registers for each drive. They are cleared only by the
Recalibrate command. The DDFDC compares the Present Track
Number (PTN) which is the current head position with the New
Track Number (NTN), and if there is a difference, performs the
following operation:

Result Phase: None.
RECALIBRATE
This two-byte command retracts the FDD read/write head to the
Track 0 position. The DDFDC clears the contents of the PTN
counters, and checks the status of the Track 0 signal from the
FDD. As long as the Track 0 signal (TRKO) is low, the direction
signal (LCT/DIR) output remains low and step pulses are issued
on FR/STP. When TRKO goes high the DDFDC sets the Seek
End (SE) flag in STO to a 1 and terminates the command. If the
TRKO is still low after 256 step pulses have been issued, the
DDFDC sets Seek End (SE) and Equipment Check (EC) flags
in STO to 1s, sets bits 7 and 6 of STO to 0 and 1, respectively,
and terminates the command.

If PTN < NTN: Sets the direction output (LCTIDIR) high
and issues step pulses (FR/STP) to the
FDD to cause the read/write head to step
in.
If PTN

> NTN:

Sets the direction output (LCT/DIR) low
and issues step pulses to the FDD to
cause the read/write head to step out.

The rate at which step pulses are issued is controlled by the
Step Rate Time (SRT) in the Specify command. After each step
pulse is issued, NTN is compared against PTN. When
NTN = PTN, then the Seek End (SE) flag in STO is set to a 1,
bits 7 and 6 in STO are set to 0, and the command IS terminated.
At this point DDFDC asserts IRQ.

The ability to do overlap Recalibrate commands to multiple FDDs
and the loss of the RDY signal, as described in the Seek command, also applies to the Recalibrate command.

Command Phase:

The FDD Busy flag (bit 0-3) in the Main Status Register (MSR)
corresponding to the FDD performing the Seek operation is set
to a 1.
After command termination, all FDD Busy bits set are cleared
by the Sense Interrupt Status command.

R/W

BYTE

7

6

5

4

3

2

1

W

1

0

0

0

0

0

1

1

1

2

X

X

X

X

X

0

US1

usa

Result Phase: None.

1-74

0

Double-Density Floppy Disk Controller (DDFDC)

R68265, R68465
SENSE INTERRUPT STATUS

Command Phase:

Interrupt request (IRQ) is asserted by the DDFDC when any of
the following conditions occur:
1. Upon entering the result phase of:
a. Read Data command
b. Read a Track command
c. Read 10 command
d. Read Deleted Data command
e. Write Data command
f. Format a Track command
g. Write Deleted Data command
h. Scan commands

Result Phase:
Status Register 0 (STO)
Present Track Number (PTN)

SPECIFY

2. Ready (ROY) line from the FDD changes state
3. Seek or Recalibrate command termination
4. During execution phase in the Non-DMA mode

The three-byte Specify command sets the initial values for each
of the three internal timers. The Head Unload Time (HUT) defines
the time from the end of the execution phase of one of the
read/write commands to the head unload state. This timer is
programmable from 16 to 240 ms in increments of 16 ms
(1 = 16 ms, 2 = 32 ms, ... F = 240 ms).

IRQ caused by reasons 1 and 4 above occur during normal
command operations and are easily discernible by the processor.
During an execution phase in Non-DMA mode, bit 5 in the MSR
is set to 1. Upon entering result phase this bit is set to O.
Reasons 1 and 4 do not require the Sense Interrupt Status command. The interrupt is cleared by reading or writing data to
DDFDC. Interrupts caused by reasons 2 and 3 are identified with
the aid of the Sense Interrupt Status command. This command
resets IRQ and sets/resets bits 5, 6, and 7 of STO to identify the
cause of the interrupt. Table 7 defines the seek and interrupt
codes.

The Step Rate Time (SRT) defines the time interval between
adjacent step pulses. This timer is programmable from 1 to
16 ms in increments of 1 ms (F = 1 ms, E = 2 ms, 0 = 3 ms, ...
o = 16 ms).

The Head Load Time (HlT) defines the time between the Head
Load (HDl) signal going high and the start of the readlwrite
operation. This timer is programmable from 2 to 254 ms in
increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6 ms, ...
7F = 254 ms).

The Sense Interrupt Status command is used in conjunction with
the Seek and Recalibrate commands which have no result
phase. When the disk drive has reached the desired head position the DDFDC asserts interrupt output. The host CPU must
thenissue a Sense Interrupt Status command to determine the
actual cause of the interrupt, which could be Seek End or a
change in ready status from one of the drives (see example in
Figure 3).

The time intervals are a direct function of the clock (ClK on
pin 19). Times indicated above are for an 8 MHz clock. If the clock
is reduced to 4 MHz (mini-floppy application) then all time intervals are increased by a factor of two.

Issuing a Sense Interrupt Status command without an interrupt
pending is treated as an invalid command.

Table 7.

The choice of DMA or Non-DMA operation is made by the NonDMA mode (NO) bit. When this bit = 1 the Non-DMA mode is
selected, and when NO = 0 the DMA mode is selected.

STO Seek and Interrupt Code Definition for
Sense Interrupt Status

Status Reglater 0
(STO) Bits
Interrupt Code
(IC)

Command Phase:

Seek End
(SE)

Cause

7

6

5

1

1

0

RDY line changed state,
either polarity

0

0

1

Normal termination 01
Seek or Recalibrate
command

0

1

1

Abnormal termination of
Seek or Recalibrate
command

R/W

BYTE

7

W

1

o

SRT HUT HLT ND -

2

SRT

3

HLT

Step Rate Time
Head Unload Time
Head Load Time
Non-DMA mode

Result Phase: None.

1-75

I 6 I 5 I4
I 0 I 0 I0

3

I2 I
0 I

oI

1
1

I
I

0

1

HUT

I ND

R68265, R68465

Double-Density Floppy Disk Controller (DDFDC)

I -Seek (or Recallbrate) Command

r-

INT
CS

I
I
I

I

I

I

II

I

I

1
I

-u-n un U JI1.

Ao

,- Sense Interrupt Status Command-I

Command Phase - / - Execution Phase --I-Command Phase-j- Result Phase.,

1

n. U
...------i

U

.-_;...1_ _ _ _ _ _ _ _---.

1

Il U

fIl,1

I

WR

1

~r------------.

~

DIOU

ROM

U~-----J~L--~J~L--

---1l'----,r--y~-,--

_____.....JnL__r__----.JnL_r_-~

z
wo

)0-

t:~

o
~

z:!!:

....£1.
£1.0

lD

.... 0

~o
zO
........

a:
z~

Figure 3.

Sense Interrupt Status

SENSE DRIVE STATUS

Command Phase:
R/W

This two-byte command obtains and reports the status of the
FDDs. Status Register 3 (ST3) is returned in the result phase
and contains the drive status.

Command Phase:
RIW
BYTE 7
W

6

5

4

3

2

1

0

0

1

0

0

HD

US1

usa

1

0

0

0

0

2

X

X

X

X X

w

Result Phase:
R

PROCESSOR INTERFACE

Result Phase:

I

R

I

Status Register 0 (STO) = 80

During the command or result phases, the Main Status Register
(MSR) must be read by the processor before each byte 0.1 information is transferred to, or from, the DDFDC Data Register. After
each byte of data is written to, or read from, the Data Register,
the processor should wait 12 I'S before reading the MSR. Bits
6 and 7 in the MSR must be a 0 and 1, respectively, before each
command byte can be written to the DDFDC. During the result
phase, bits 6 and 7 of the MSR must both be 1s prior to reading
each byte from the Data Register onto the data bus. Note that
this status reading of bits 6 and 7 of the MSR before each byte
transfer to and from the DDFDC is required in only the command
and result phases and not during the execution phase.

Status Register 3 (ST3)

INVALID COMMAND
If an invalid command (i.e., a command not previously defined)
is received by the DDFDC, then the DDFDC terminates the command after setting bits 7 and 6 of STO to 1 and 0, respectively.
The DDFDC does not generate an interrupt during this condition. Bits 6 and 7 (DIO and ROM) in the MSR are both set to
a 1 indicating to the processor that the DDFDC is in the result
phase and that STO must be read. A hex 80 in STO indicates
an invalid command was received.
A Sense Interrupt Status command must be sent after a Seek
or Recalibrate interrupt, otherwise the DDFDC considers the next
command to be an invalid command.

During the result phase all bytes shown in the result phase must
be read by the processor. The Read Data command, for
example, has seven bytes of data in the result phase. All seven
Bytes must be read to successfully complete the Read Data command. The DDFDC will not accept a new command until all
seven bytes have been read. Other commands may require
fewer bytes to be read during the result phase.

In some applications the user may wish to use this command
as a No-Op command, to place the DDFDC in a standby or no
operation state.

1-76

R68265, R68465

Double-Density Floppy Disk Controller (DDFDC)
DATA IN/OUT
(010)
(MSR BIT 6)

FROM DDFDC TO DATA BUS

FROMDATABUSTO~~
I

REQUEST
FOR MASTER
(RQM)
(MSR BIT 7)

I I

I

I

I

CHIP SELECT (CS)
READIWRITE (RiW)

A

A

A

B

C

0

NOTES

o

DATA REGISTER READY TO BE WRITTEN INTO

o

DATA REGISTER READY FOR NEXT DATA BYTE TO BE READ

[!] DATA REGISTER NOT READY TO BE WRITTEN INTO [EJ DATA REGISTER NOT READY FOR NEXT DATA BYTE TO BE READ
Figure 4.

DDFDC and System Data Transfer Timing

INTERRUPT REQUEST MODE

DONE low or the EaT sector is read), IRQ is asserted to indicate
the beginning of the result phase. When the first byte of data
is read during the result phase, IRQ is reset high.

During the execution phase, the MSR need not be read. The
receipt of each data byte from the FDD is indicated by IRQ low
on pin 18. When the DDFDC is in Non-DMA mode, IRQ is
asserted during the execution phase. When the DDFDC is in
the DMA mode, IRQ is asserted at the result phase. The IRQ
signal is reset by a read (RrW high) or write (RrW low) of data
to the DDFDC. A further explanation of the IRQ signal is
described in the Sense Interrupt Status command on page 16.
If the system cannot handle interrupts fast enough (within 13 I's
for MFM mode or 27 I's for FM mode), it should poll bit 7 (RQM)
in the MSR. In this case, RQM in the MSR functions as an Interrupt Request (IRQ). If the RQM bit is not set, the Over Run (OR)
flag in ST1 will be set to a 1 and bits 7 and 6 of STO will be set
to a 0 and 1, respectively.

During a write command, the DDFDC asserts REQ as each byte
of data is required. The DMA controller responds to this request
with DACK low (DMA Acknowledge) and RrW low (write). When
DACK goes low the DMA Request is reset (REQ high). After the
execution phase has been completed (DONE low or the EaT
sector is written), IRQ is asserted. This signals the beginning of
the result phase. When the first byte of data is read during the
result phase, the IRQ is reset high.

FDD POLLING
After the Specify command has been received by the DDFDC,
the Unit Select lines (USO and US1) begin the pOlling mode.
Between commands (and between step pulses in the Seek Command) the DDFDC polls all the FDD's looking for a change in
the RDY line from any of the drives. If the RDY line changes
state (usually due to the door opening or closing) then the
DDFDC asserts IRQ. When Status Register 0 (STO) is read (after
Sense Interrupt Status command is issued), Not Ready (NR = 1)
will be indicated. The polling of the ROY line by the OOFDC
occurs continuously between commands, thus notifying the processor which drives are on- or off-line. Each drive is polled every
1.024 ms except during read/write commands.

DMA MODE
When the DDFDC is in the DMA mode (ND = 0 in the third command byte of the Specify command), DRQ (DMA Request) is
asserted during the execution phase (rather than IRQ) to request
the transfer of a data byte between the data bus and the DDFDC.
During a read command, the DDFDC asserts REQ as each byte
of data is available to be read. The DMA controller responds
to this request with both DACK low (DMA Acknowledge) and RrW
high (read). When DACK goes low the DMA Request is reset
(REQ high). After the execution phase has been completed

1-n

R68265, R68465

Double~Density

Floppy Disk Controller (DDFDC)

R68465 (FM MODE)
FIELP

GAP . .

SYNC

NO. Of BYTES

40x

Ox

DATA

FF

00

'AM

GAP 1

SYNC

",

Ox

FF

00

FC

lOAM

CYL

HD

SEC

CAC

GAP,

SYNC

11x

Ox

FF

00

FE

I

INDEX.JL

NO

DATA AM

DATA

GAP 3

0

GAP 4b

0

CRC

FB OR Fa

I

REPEAT N TIMES

R68265 (FM MODE)
FIELD

GAP 1

SYNC

NO OF BYTES

lOx

Ox

DATA

FF

00

lOAM

CYL

HD

SEC

NO

CRC

GAP 2

SYNC

11x

Ox

FF

00

FC

INDEX~

DATA AM

DATA

GAP 3

0

GAP 4

0

CRC

FB OR Fa

I

REPEAT N TIMES

R68465 (MFM MODE)
GAP 4a

SYNC

.Ox

lOx

3,

4E

00

C,

'AM

FC

GAP 1

SYNC

50x

lOx

3x

4E

00

"

lOAM

CYL

HD

NO

SEC

FE

I

INDEXfL

CRC

GAP 2

SYNC

22,

lOx

3x

F.

4E

00

"

F.

DATA AM

DATA

GAP 3

0

I

REPEAT N TIMES

R68265 (MFM MODE)

....

,

FIELD

GAP 1

SYNC

NO. OF BYTES

3'x

lOx

3x

DATA

4E

00

"

CYL

HD

NO

SEC

CRC

GAP 2

SYNC

22,

lOx

4E

00

,>

INDEX.JL

FE

I

INDEX
FORMAT

DATA AM

.
3x

,

DATA

GAP 3

0

F.

CRC

I

DDFDC Formats

~~ __________________________~/~

IGAP 4aliAM 1 GAP 111D 1 GAP 21 DATA 1GAP 31

R684S5
VCO SYNC

r------,

WE
INDEX
FORMAT

~~------------------~{~
__ 1110 1 GAP
__21 ____
__ 1GAP 21
__ 41
IGAP
DATA 1______
GAP 31 1D
ID 1( ____ 1GAP
~

-L~~~

~

~

~

L -__

~

____

~/,r

R68265
VCO SYNC

WE

_______\l.--J/ _____~
I

r------,

,

NOTE: _ _ READ
____ WRITE

Figure 6.

DDFDC Formats

1-78

GAP 4

0

F•

REPEAT N TIMES

Figure 5.

GAP 4b

0

CRC

,,------1

~

~

lJ

en
Q)

I\)

en
91
Al·A23

ADDRESS BUS

[)()'D15

DATA BUS

lJ

en
Q)

UDS1

I--

AS

f-

DlACK

.

~

r--

RNi

LOS'

I--

BGACK

en

U1

~K>-

'r"

1'~! •
~.t

I>

~

l-

0

BR

f----I--

BG

~

~s

w

GATED

~I ~I £1

R6SODO
MPU

~I ~I ~ ;.~~
0

BUS

ml
ml ml e
G'l:tl R

~I ~I £1 gl

~

~I

~I

~l ~

,

l'~
~ en

-..j

~

~

~I

c0
ROW
MFM

REO

VCO
ROD

~

68440 DMAC

MEMORY

.

irr"3-

OACK

PSO
PSl
WDA

DONE

WPfTS

lACK

FCl
FC2

~

T

~

R682651
R68485

§i

DDFDC

lS
138

Al

FR/STP

A2

LeTIDlR

A3

l

VPA

IPLO
IPL1
IPL2

FLTiTRKO

-

I

IRQ

WRITE
CLOCK
GEN

lS

WCK

RW/SEEK

2

R--

E
---~
=:
MUX

MUX

14'

HDl

--

8 MHz
OSC
.-

ClK

--

Signal not used in interface to 68008 MPU.
UDS changed to OS when interfaced to 68008 MPU.

--------_._----

RESET

•

USO
USl

C

WRITE DATA
WRITE PROTECT
TWO-SIDE
FAULT
TRACK 0
FAULT RESET
STEP

lOW CURRENT

~f---- DIRECTION
READY

WE

iRa

CD·
I

WRITE ENABLE

lOX

'---

1

tT

- - READ DATA

ROY

HDSEL

L

s:::

~.
RECOVERY

INDEX

~

HEAD LOAD
HEAD SELECT
UNIT SELECT 0

CD
::J
(I)

;::;:
'<

""0'
""'<
C

;"

....

0

-......
0

::J

2CD

C
C

Figure 7.

""

C
0

R68265/R68465 DOFOe Interface to R68000

iii

R68265, R68465

elK

Double-Density Floppy Disk Controller (DDFDC)

~

/
Figure 8.

Clock Timing

RS

R/W

DATA OUT
(00-07)

Figure 9.

DDFDC Read Cycle Timing

RS

7

RIW

DATA IN
(00-07)

Figure 10.

DDFDC Write Cycle Timing

1-80

R68265, R68465

Double-Density Floppy Disk Controller (DDFDC)

TXRQ

~c

-{

DACK

f

DONE

Figure 11.

@

t.

/

{

DMA Operation Timing

WRITE CLOCK
(WCK)~

~

WRITE ENABLE
(WE)@!
PRESHIFT 0 OR 1
(PSO, PS1)

- , r---1.r"::"':"'-'"", ~--~

WRITE DATA
(WDA)

Figure 12.

FDD Write Operation Timing

READ DATA
(ROD)

--------..J.---------J J..--

READ DATA WINDOW
(RDW) _ _ _ _ _ _ _ _J-~------~

[~OTE:

EITHER POLARITY DATA WINDOW IS VALID

Figure 13.

FDD Read Operation Timing

1-81

R6.8265,. R68465

I

Double-Density Floppy Disk Controller (DDFDC)

us.,,,

I

=?j-------......,. -----

SEEK
(RW/sEEK)

DIRECTION
(LCT/DIR)

STEP
(FR/sTP) _ _ _ _ _ _JI

Figure 14. Seek Operation Timing

0

FAULT RESET
(FR)___

_

INDEX
(lOX)

__

@
Figure 16. Index Timing

Figure 15. Fault Reset Timing

-tF
47

RESET
(RST)

Figure 18. Reset Timing

Figure 17. Terminal Count Timing

INPUT/OUT

TEST POINT

..I
2.4V--Y2.0V ;t'iOV
0.45V

---.1\ O.BV

O.BV

CLOCK

V

3.0V----V: 2.4V

1"---

INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND 0.45 V FOR
A LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.0V FOR
A LOGIC "1" AND O.BV FOR A LOGIC "0:'

TEST POINT

.J

72. V 4V

O.3V - A 0 . B 5 V 0 . B 5 V " - CLOCKS ARE DRIVEN AT 3.0V FOR A LOGIC "1" AND 0.3V FOR A
LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.4V FOR A
LOGIC "1" AND 0.B5V FOR A LOGIC "0:'

Figure 19. AC Timing Measurement Conditions

1-82

Double-Density Floppy Disk Controller (DDFDC)

R68265, R68465

i

AC CHARACTERISTICS
(Vee = 5.0 Vdc ±5%, Vss = 0 Vdc, TA = O°C to 70°C)
ReI.
Fig.

5

6
and
7

8

,

No.

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
19a
20
ev

Clock High
Clock Rise Time

tCA
tCLCH

<1>0
<1>,

Clock Fall Time
CS High to RIW High
Address valid to CS Low
CS High to Address Invalid
CS High
DTACK Low to Data Valid
CS High to Output High Z
CS High to DTACK High
Address valid to RIW Low
RIW Low to CS Low
CS Low Pulse Width
Data valid to CS High
CS High to Data Invalid
IRQ Delay from CS High
TXRQ Cycle Period
ACK Low to TXRQ Low
TXRQ High to ACK Low (Delay)
DONE Low Width
WcK cycle Time
(8" or 3-1/2" FOOl

tCHCL
tSHRH
tMlL
tSHAX
tSHSL
tOLOV
tsHoz
t SHoH

t
tSR
tRA
tAH
tSH
tRO
tOF
tDTK

tAVRL
tRLSL
tSLSH
tOVSH
tSHOZ
t lLSH
tTOCY

tws
tWH
tSL
tosu
tOHW
tiRO
tTCY

tAKTH
tOHAL
tNLNH
tKCY

tACK
tMA

I

I

WOA High Width
WE High to WCK High or WE Low to WCK Low
ROW Cycle Time
(8" or 3-1/2" FOO)

I

tKHKL
tKLKH
tKHKL
tKHPV
tOHEN
tpvOH
t OHoL
tEHKH
twev

10
t,

"

lep
!ewE
leo
twoo
tWE
twev

(5-114" 1"00)

ROW Valid to ROD High (Setup)
ROD Low to ROW Invalid (Hold)
ROD High Width

tWVRH
tRUN!
tRHRL

USO, US1 Valid to SEEK High (Setup)
SEEK Low to USO, US1 Invalid (Hold)
SEEK High to OIR Valid (Setup)
OIR Invalid to SEEK Low (Hold)
OIR Valid to STP High (Setup)
STP Low to OIR Invalid (Hold)
STP Low to USO, US1 Invalid (Hold)

tUVSH
tSWI
tSHov
tOXSL
tOVTH
tTLOX
tTWX
tTHTL
ITOY

STP High Width
STP Cycle Time
FR High Width
lOX High Width
DONE Low Width
RESET Low Width

tOONE
tev

(5-1/4" FOO)

WCK High Width
WCK Rise Time
WCK Fall Time
WCK High to PSO, PS1 Valid (Delay)
WCK High to WE High (Delay)
PSO, PS1 valid to WOA High (Delay)

I
10

Symbol
tev

tFHFL
tlHIL
tTHTL
tRHRL

tWRO
tROW
tROD
tus
tsu

Min.
120
40

-

Typ.
125
250

-

-

-

20
20

-

40
0
0
150

20

20
80
250
150
5

13

200
1

80

20
20
20
twcH -50
20

--

15
15

40
12
15
7
30
1
24
5
6

tso
tos
toST
tSTo
tSTU
tSTP
tsc

333

tFR
t lOX
tre
tilST

8
10
1
14

Max.
500

-

90

120

-

500

-

-

200

-

2
1
4
2
250

-

350
20
20
100
100

-

-

-

-

100
100

2
1
4
2

-

-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Us

!IS
;'S
ns
ns
ns
ns
ns
ns
ns
ns

!
~

:l15

r----

'------

ro:I ~I~I
"
'ill

~
~

[l

cl~'
.>

oj

!l?:II

~

BUS

<0

~I~I

~

,
-..I

n

~I

~ ~

;---

A3

C

A2

B
A

A1

L

(Jl

n
r

G2B
G1

t-¥sY6

~

~IT~I ~
~

~

~I

J

lACKS
IACK6

~

~I

C>
~

O[:D
(I)

3:
c

0

~I ~

ihl

,"

;::;

~

l:

'V

TDSR

~

ROSA

~

~
DONE

t-:::-

1K
+5V~

ACKl

YO

~
~

74LSl38 ~
G2A

~I

(")1

ACKO

MC68440
OMAC

~

~~~~

+5V

REaD

MEMORY

m
~,

'.-'

REOl

i:>
<0

j

~\

~

"~

BG

,.-

en
......

.--

r
t-

R!W

en

----.

DACK

R68560
MPCC

~
t-

~

IRQ

3
3

::J

C:;"

a0"

~,

SYSTEM CLOCK

2-

oo
c

IAC~

A

'---

~n

§I

::J

I

CLOCK
QSC

(I)

J

oo

-a...
::J

i"

3:
'V

Figure 11.

o
o

Typical Interface to 68008-Based System

iii

-

R68560, R68561

Multi-Protocol Communications Controller (MPCC)

A1·A4
AO'

CS

LDS/DS
UDS2

RNi

DTACK
4

Do-D15

NOTES:
1. BYTE MODE WHEN CONNECTED TO AO ON 68008 BUS.
2. WORD MODE WHEN CONNECTED TO UDS ON 68000 BUS.
3. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
.
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.

Figure 12. MPCC Read Cycle Timing

A1·A4
AO'

CS

LDS/DS
UDS2

R/W

DTACK
11

00·D15

NOTES:
1. BYTE MODE WHEN CONNECTED TO AO ON 68008 BUS.
2. WORD MODE WHEN CONNECTED TO UDS ON 68000 BUS.
3. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.

Figure 13.

MPCC Write Cycle Timing
1·110

Multi-Protocol Communications Controller (MPCC)

R68560, R68561

II
INTERNAL
RECEIVER
CLOCK
(BAUD RATE)

ROSA

\

I

\

~

@

~

(

DACK

LDS/Os
UDS/A02

DO-D15

R/W

NOTES:
1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS UNLESS OTHERWISE NOTED.
2. WORD MODE ONLY.

Figure 14.

MPCC to Memory DMA Transfer Cycle Timing (Receiver DMA Mode)

1·111

R68560, R68561

Multi-Protocol Communications Controller (MPCC)

I

I
I

INTERNAL
TRANSMITTER
CLOCK
(BAUD RATE)

\ _____1

\_---_1

____~~.-~~~~~@-8~---------~~~------

\____________....1/
LOS/OS
UDS/A02

00-015

R/W

NOTES:
1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS UNLESS OTHERWISE NOTED.
2. WORD MODE ONLY.

Figure 15.

Memory to MPCC DMA Transfer Cycle Timing (Transmitter DMA Mode)

1-112

R68560, R68561

Multi-Protocol Communications Controller (MPCC)

~~----------------------~!

....---{26l---....-l
00-07

INTERRUPT VECTOR

NOTES:
1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH
VOLTAGE OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
2. IRQ IS NEGATED WHEN ALL BITS IN STATUS REGISTERS THAT COULD HAVE CAUSED THE INTERRUPT
ARE CLEARED.

Figure 16.

Interrupt Request Cycle Timing

MDCC1

MPCC2

MPCC 1

TxC

RxC

TxC

TxD

RxD

TxD

Rx DATA (BB)

RxC

TxC

RxC

Tx TIMING (DA)

RxD

TxD

RxD

Tx DATA (BA)

HIGH SPEED INTERFACE

MODEM/DCE

~

Rx TIMING (DO)

LOW SPEED (RS-232) INTERFACE

Figure 17. Serial Interface
1-113

R68560, R68561

Multi-Protocol Communications Controller (MPCC)

HIGH SPEED APPLICATION

LOW SPEED APPLICATION (RS-232 COMPATIBLE)

TxC

TxD

DATA A

Figure 18.

Serial Interface Timing

RxD

TxO

NOTE:
TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.

Figure 19.

Serial Interface Echo Mode Timing
1-114

Multi-Protocol Communications Controller (MPCC)

R68560, R68561
AC CHARACTERISTICS
(Vee = 5.0 Vdc ± 5%, Vss = 0 Vdc, TA

O°C to 70°C)
Max

Unit

1

RIW High to CS, OS Low

tAHSL

0

-

ns

2

Address Valid to CS, OS Low

tAVSL

30

-

ns

3'

CS Low to DTACK Low

tCLDAL

0

60

ns

4'

CS, OS Low to Data Valid

tSLDV

0

140

ns

5

CS, OS High to Data Invalid

tSHDXA

10

150

ns

6

CS, OS High to DTACK High

tSHDAT

0

40

ns

7

CS, OS High to Address Invalid

tSHAI

20

-

ns

8

CS, OS High to RIW Low

tSHAL

20

-

ns

9

RIW Low to CS, OS Low

tALSL

0

-

ns

10

CS High, OS High to RIW High

tSHAH

20

-

ns

11

Data Valid to CS, OS High

tDVSH

60

ns

12

CS, OS High to Data Invalid

tSHDXW

17

DTC Low to DS High

tCLSH

60

-

18

DACK Low to Data Valid, DONE Low

tALDV

0

140

ns

19

OS High to Data Invalid

tSHDXDA

10

150

ns

21

Data Valid to OS High

tDvSH

60

ns

22

OS High to Data Invalid

tSHDXDW

0

-

25

lACK Low to DTACK Low

tlAlAL

0

40

ns

26

lACK, DS Low to Data Valid

tlALDV

0

140

ns

27

OS High to Data Invalid

tlSHDI

10

150

ns

28

lACK High to DTACK High

tlAHDAT

0

40

ns

30

RxC and TxC Period

tcp

-

ns

31

TxC Low to TxD Delay

tTCLTD

0

200

ns

32

RxC Low to RxD Transition (Hold)

tACLAD

0

-

ns

33

RxD Transition to RxC Low (Setup)

tADRCL

30

-

ns

34

RxD to TxD Delay (Echo Mode)

tRDTD

-

200

ns

35

RIW Low to DTACK Low (Setup)

tALAL

0

-

ns

36

DACK High to DONE High

tAHDH

0

-

ns

372. 3

RDSR Pulse Width

t RPw

1

-

clock period

382 • 4

TDSR Pulse Width

t TPW

1

-

clock period

Number

Symbol

Parameter

Min

0

248

ns
ns

ns

Notes:
1. For read cycle timing, the MPCC asserts DTACK within the MPU S4 clock low setup time requirement and establishes
valid data (Data In) within the MPU S6 clock low setup time requirement.
2. For synchronous protocols, this is one full senal clock period of RxC for RDSR and TxC for TDSR.
3. For asynchronous protocols, RDSR is asserted for two system clock penods for a prescale factor of 2 and for three system clock
periods for a prescale factor of 3.
4. For asynchronous protocols, TDSR is asserted for a period of one-half the baud rate.

1-115

II

Multi-Protocol Communications Controller (MPCC)

R68560, R68561
ABSOLUTE MAXIMUM RATINGS*
Parameter

Symbol

Value

Unit

Supply Voltage

Vee

-0.3 to + 7.0

V

Input Voltage

V,N

-0.3 to +7.0

V

Operating Temperature Range

TA

o to +70

°C

Storage Temperature

TSTG

-55 to +150

°C

·NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS
Parameter

Symbol

Thermal Resistance
Ceramic
Plastic

8JA

Value

Rating
°C/w

50
68

DC CHARACTERISTICS
= 5.0 Vdc ± 5%, VSS = 0 Vdc,

(Vee

TA

= ooe to 70 e unless otherwise

Parameter

0

noted)

Symbol

Min

Max

Unit

Input High Voltage
All Inputs

V ,H

2.0

Vee

V

Input low Voltage
All Inputs

V,L

-03

+08

V

Input leakage Current
R/iN, RESET. CS

liN

-

10.0

~A

Y'N = 0 to 5.25V
Vee = 525V

Three-State (Off State) Input Current
IRO, DTACK, DO-DI5

TTSI

-

10.0

~A

V,N = 0.4 to 2.4V
Vee = 525V

Output High Voltage
RDSR, TOSR, IRO, DTACK, DO-DI5, DSR, DTR, RTS,
TxD, TxC

VOH

Vss + 2.4

-

V

Vee = 475V
ILOAD = -400~A
C LOAD = 130 pF

VOH

Vss + 24

-

V

Vee = 475V
ILOAD = 0
C LOAD = 30 pF

VOL

-

0.5

V

Vee = 4.75V
ILOAD = 3.2 mA

BClK

Output low Voltage
RDSA, TOSA, IRO, DTACK DO-DI5, DSR, DTA, ATS,
TxD, TxC, BClK,

Vee = 475V
ILOAD = 8.8 mA

DONE
Internal Power Dissipation
Input Capacitance

Test Conditions

P,NT
C'N

1-116

-

=

1

W

TA

13

pF

V,N = OV
TA = 25°C
f = 1 MHz

25°C

R68560, R68561

Multi-Protocol Communications Controller (MPCC)

PACKAGE DIMENSIONS
48-PIN CERAMIC DIP

~{].
I

-

]J

..!WIIETE".

-~---tl

DIM

MIN

MAX

It.

6035

B 1463

MAX

6157

2376

2~4

1534

0576

0604

0120

0160

C

305

432

D

0381

0533 0015

0021

F

0762

13970030

0055

G

254BSC

0100880

J

0203

0330 0008

0013

K

254

419

0100

0165

L 1499

1565

0590

II
N

rr
1016

HI"

(J'

15240040

MILUMETERS

DIM

MIN

MAX

0516
10'

0606

INCtES

MIN

IIAX

A

5128

5232

2040

2080

8

1372

1422

0540

0560

C

355

508

0140

0200

D

036

051

0014

0020

F

102

152

0040

G

254BSC

0060

0100BSC

H

185

216

J

020

030

0008

0012

K

305

356

0120

0140

L

1-117

INCHES
MIN

1524 esc

II

7"

10"

N

051

102

0066

0600

0085

esc

7"

10"

0020

0040

D

R68802

'1'

Rockwell

R68802
LOCAL NETWORK CONTROLLER (LNET)
PRELIMINARY

DESCRIPTION

FEATURES

The R68802> Local Network Controller (LNET) implements the
IEEE 802.3 CSMAlCD Access Method local network standard.
More generally, it is designed to support a variety of local network designs with varying performance requirements.

• Serial data rates as high as 10M bps
• Compatible With a variety of 8- or 16-bit processors and DMA
controllers
• Meets the IEEE 802.3 (as well as Ethernet» specifications for
local networks
• Interfaces to SEEQ 8002 Manchester Code Converter (MCC)
• Programmable Interframe wait times for smaller topologies
and lower data rates

The basic function of the LNET is to execute the CSMAlCD
algorithm, perform parallel-to-serial and serial-to-parallel conversIOns of the 10M bps packet data stream, and assemble and
disassemble the packet format. In addition, the LNET provides
the necessary asynchronous handshake signals to the 68000
family processors, the reqUired DMA Interfaces, and the proper
interface to the Manchester Interface (MI) component(s) used
to connect the LNET to an IEEE 802.3 defmed Media Attachment Unit (MAU).

• CSMAlCD algorithm:
-Wait before transmit
-Jam on collision
- Binary exponential backoff
• Programmable 2- or 6-byte address recognition

The controller can interface data terminal equipment to local
networks with differing performance reqUirements. At the high
end, the R68802 meets the IEEE 802.3 10M bps specification
and supports the Implementation of ISO layers one and two. For
low cost networks, the controller can be run at greatly reduced
data rates and inexpensiVe system components (drivers, cables,
etc.) may be selected.

• Supports three modes of node self-test
• Programmable disable on reception

The LNET controller implements a protocol known as Carrier
Sense MU~lple Access With Collision Detection (CSMAlCD),
which allows multiple Data Terminal EqUipment to share the
same communication medium without the need for a central
arbiter of medium utilization.

* R68802 IS

Ethernet nodes needing to transmit wait exactly 9.6 jJ.S before
transmitting data to provide recovery time for other controllers
and the cable itself. If a collision WITh another station IS detected,
the transmission is aborted and a jam signal transmitted to alert
other nodes. Following a Jam, the station waits a random amount
of time based on a Binary Exponential Back-off algOrithm before
retransmitting. Repeated collisions result in repeated retries and
an increase in the randomly selected time interval to improve
trafficking.

ORDERING INFORMATION
Part Number

R68802 _

Temperature Range: O°C to 70°C

LpaCkage:
C ~ Ceramic
P ~ Plastic

Document No. 68650N07

• 32-blt CRC generation and reception
• Broadband applications
• TTL compatible 1/0
• 40-pln DIP
• Single 5V power supply
-Ethernet

IS

a trademark of the Rockwell International Corporation
a trademark of the Xerox Corporation

VCC

MAu'REQ

RiW

MAUAVAIL
ISOLATE
TXCLK
TXOATA
TXEN
SIGQUAL
SENSE
RXCLK
RXOATA
MILOOP
TXREQ
RXREQ
OACK
OONE
IRQ

RESET
00
01
02
03
04
05

OS
07
08
09
010
011
012
013
014
015

CS

i5TACK
OS
lACK
GNO

R68802 Pin Assignments

Product Description Order No. 706
Rev. 2 January 1984

IRQ

:D

en

PARALLELTO-SERIAL
REGISTER

INTERRUPT

lAcK _ _~--+lINTERFACE

~TRANSMIT

/\

CRC
GENERATOR

io

I

N

TRANSMIT
MUX

~

I
TXDATA

I

---.l

I

~
3:z..BVTE

TRANSMIT
CONTROL

TRANSMIT

FIFO
(TXFIFO)

Rm

DlACK

.!.

cO

00-015

TXREQ

RxiiEa . - -

PAD
GENERATOR

PREAMBLE &

JAM
GENERATOR

DELIMITER
GENERATOR

INTERFRAME

DELAY
COUNTER

BINARY
EXPONENTIAL
BACK-OFF
COUNTER

CSMA/CD
CONTROL

TXClK

r---+I-+--

r---

TXEN
SIGQUAL
SENSE

i
INTERNAL DATA BUS

<.

!

j

.--

DACK

TRANSMIT
LENGTH
COUNTER

BUS
CONTROL

<::>

DONE

V

/\ r

----+

OS

CS - - - .

I
INTERNAL
TRANSMITTER
CLOCK

/\

/\

EXTERNAL
DMAC
INTERFACE

r

~l
RECEIVE
CONTROL

t
32-BYTE
RECEIVE
FIFO
(RXFIFO)

/)

V

l

ADDRESS
RECOGNITION

V
RECEIVE
LENGTH
COUNTER

g

i

V

INTERRUPT

STATUS

IMODE

{)

REGISTER

~ MAuREa

r---+~

MiU50P
ISOLATE
MAUAVAll

..-

J
SERIAL-TOPARALLEL

COMMAND

e!..

-..
z
:oe

CD

~

INTERNAL
RECEIVER
CLOCK

I+--

RXCLK

oo

-..
:::J

o

RECEIVE
CRC

DELIMITER
RECOGNITION

RXCATA

ii

r

Figure 1.

LNET Block Diagram

Z

m
-t

Local Network Controller (LNET)

R68802
PIN DESCRIPTION

lACK-Interrupt Acknowledge. The active low lACK Input
indicates that the current bus cycle is an interrupt acknowledge
cycle. When lACK is asserted the LNET places an interrupt
vector on the lower byte (00-07) of the data bus.

Throughout the document, signals are presented using the
terms active and inactive or asserted and negated independent
of whether the signal is active in the high-voltage state or lowvoltage state. (The active state of each logic pin is described
below.) Active low signals are denoted by a superscript bar.
RlW indicates a write is active low and a read active high.

DACK-DMA Acknowledge. The OACK low input indicates
that the data bus has been acquired by the DMAC and that the
requested bus cycle is beginning.
DONE-Done. DONE is a bidirectional active low signal. The
DONE signal is asserted by the OMAC when the OMA tr~nsfer
count is exhausted and there IS no more data to be transferred,
or is asserted by the LNET when either the last byte of receive
data IS transferred or a colliSion IS detected dunng a transmission.

{

DATA.
BUS

ASYNCHRONOUS
BUS
CONTROL

{

R68802
LNET

RESET -Reset. The active low, high impedance RESET input
initializes all LNET functions. RESET must be asserted for at
least 500 TXCLKs to initialize the LNET.

MANCHESTER
INTERFACE

OMA
CONTROL

INTERRUPT
CONTROL.

{

TXREQ
RXREQ

{

Figure 2.

DAcK

RXDATA

DONE

Mii:OOP

iRci
lACK

RXREQ-Receive DMA Request. When receive data becomes
available in the RXFIFO, RXREQ output is asserted and held
low for 16 (single address burst mode) OMAC cycles (16
sequential OACK pulses) or until the end of the receive block.
When the last data byte of the receive block is transferred,
DONE is asserted by the LNET with the last OACK strobe and
the negation of RXREQ.

V"
GNO

LNET Input and Output Signals

TXREQ-Transmit DMA Request. When the Transmitter
Enable bit is set in Command Register 1, TXREQ output is
asserted and held low for 16 (single address burst mode) OMAC
cycles (16 sequential OACK pulses) or until the end of the
transmit data block as signaled by the OMAC's assertion of
DONE.

DO-D15-Data Lines. The bidirectional data lines transfer data
between the LNET and the MPU, memory or other peripheral
device. DO-015 are used when connected to the 16-bit 68000
bus and operating in the word mode. 00-07 are used when connected to the 16-bit 68000 bus or the 8-bit 68008 bus and
operating in the byte mode. The data bus is tri-stated when CS
is inactive. (See exceptions in DMA mode.)

MILOOP-MI Loopback. With an active MILOOP output, the
MI shunts its LNET data-in path to its LNET data-out path,
effectively routing the LNET TXOATA output into the LNET
RXOATA input.

CS-Chip Select. CS low selects the LNET for programmed
transfers with the host. The LNET is deselected when the CS
input is inactive in non-DMA mode. CS must be decoded from
the address bus and gated with address strobe (AS).

RXDATA-Receive Data. The LNET receives serial data via
the RXOATA input. The RXOATA input is shiftEl"d into the receiver
on the positive going edge of RXCLK.

R/W-Read/Write. RlW controls the direction of data flow
through the bidirectional data bus by indicating that the current
bus cycle is a read (high) or write (low) cycle.

RXCLK-Receive Clock. The free-running Receive Clock provides the LNET with received data timing information. The positive (Iow-to-high) clock transition enables an RXOATA bit into
the LNET.

DTACK-Data Transfer Acknowledge. OTACK is an active
low output that signals the completion of the bus cycle. During
read or interrupt acknowledge cycles, OTACK is asserted by the
LNET after data has been provided on the data bus; during
write cycles it is asserted after data has been accepted at the
data bus. A pull up resistor is required to maintain DTACK high
between bus cycles.

SENSE-Carrier Sense. The active high SENSE input indicates the presence of data on the RXOATA serial input line.
SIGQUAL-Signal Quality. The assertion of the active high
SIGQUAL input by the MI indicates an error condition on the
medium. During the transmission mode the LNET interprets this
as a collision.

DS-Data Strobe. During a write (RlW low), the OS positive
transition latches data from the external data bus lines into the
LNET. During a read (RlW high), OS low enables data from the
LNET onto data bus lines.

TXEN-Transmit Enable. The active high TXEN output indicates to the MI that data is present on the TXDATA output.

IRQ-Interrupt Request. The active low IRQ output requests
interrupt service by the MPU.

1-120

R68802

Local Network Controller (LNET)
INITIALIZATION REGISTERS

TXDATA-Transmit Data. The LNET transmits serial data on
the TXOATA line. The TXOATA output changes on the positive
going edge of TXCLK.

The initialization registers contain command information to configure the LNET for normal operation. The registers are the onebyte Mode Register (MR), the one-byte Interrupt Vector Number
Register (IVNR) and the two- or six-byte Station Address Register (SAR). These registers must be loaded upon RESET (either
caused by power up or initiated during normal operation) or upon
setting of the RESET bit in Command Register 1. Any of these
conditions reset the LNET by clearing the Mode Register, Station Address Register, Command Registers and Status RegiSters. The Interrupt Vector Number Register IS auto-initialized to
its defau~ value of $OF.

TXCLK-Transmit Clock. The Transmit Clock input is a freerunning clock supplied by the MI that provides both a system
clock and a means of shifting out serial data bit on the TXOATA
output line.
ISOLATE-Isolate MAU. The active low ISOLATE output is
asserted when the Isolate brt in Command Register 1 is set to
1 to isolate the MAU from the medium. As long as ISOLATE is
low, the MAU IS unable to transmit or receive on the medium.

All initialization registers must be written to by the MPU instruction sequence immediately after a reset in the manner decrlbed
below even if no data is changed in a register. The number of
bytes written depends upon the number of bytes in the Station
Address as selected In bit 4 of the Mode Register.

MAUAVAIL-MAU Available. When the active low MAUAVAIL
input is asserted, the transmission algorithm can proceed.
MAUREQ-MAU Request. The active low MAUREQ output is
asserted prior to transmission if MAUAVAIL is not asserted.

After the proper number of write cycles have been completed,
the LNET Initialized bit In Status Register 1 IS set and further
MPU writes to the LNET Will address only Command Register
1 or Command Register 2. All MPU reads of the LNET after
initialization IS complete will access only Status Register 1 or
Status Register 2.

Vee-Power. 5 V ± 5%.
GND-Ground. Ground.

LNET REGISTERS
The LNET contains three groups of registers accessible from
the MPU bus which initialize the LNET, control and monitor
LNET operation, and transfer data between the LNET and the
MPU bus. These register groups, specific registers within each
group, and the size, access and mode of each register are listed
in Table 1.

Initialization Procedure for 16-Bit MPU Bus
Write cycle 1-wrlte the Mode byte on the lower byte of the
data bus 00-07. The upper byte is not used and can contain
any data.
Write cycle 2-write the Interrupt Vector Number on the lower
byte of the data bus 00-07. The upper byte is not used and can
contain any data.

All registers, except the Mode Register, may be accessed either
in the word or byte mode, depending on the MPU data bus
length (S-bit or 16-bit) and the Word/Byte mode selected in bit
4 of the Mode Register during initialization. In the word mode,
two registers are read or written during one cycle with the least
significant byte (00-07) accessed first.

Table 1.
Register Group

Initialization
Registers

LNET MPU Bus Accessible Registers

Register Name

1

Interrupt Vector Number Register (IVNR)

1

Data
Buffers

2 or 6

Command Register 1 (CR1)
Command Register 2 (CR2)

1
1

Status Register 1 (SR1)
Status Register 2 (SR2)

1

Transmit FIFO Register File (TXFIFO)
Receive FIFO Register File (RXFIFO)

Access

Reset
Value

CS = L, RNI/ = L (write one byte ' )

$00

Size
(No. Bytes)

Mode Register (MR)

Station Address Register (SAR)

Operating
Registers

Write cycle 3 or write cycles 3 through 5-write the one- or
three-word Station Address (depending on the Station Address
Size loaded Into the Mode Register), least significant words first.

CS = L, R/W = L (write one byte')

$OF

CS = L, R/W = L (write 1 or 3
sequential words or 2 or 6
sequential bytes)

$00

CS=L,R/W=L

$00

Mode
MPU Write

MPU Write

CS=L,R/W=H

$00

MPU Read

32

TXREQ = L

$XX

DMAWrite

32

RXREQ = L

$XX

DMA Read

1

Notes:
1. Second byte of word ignored.
2. Second byte in word mode ignored.

1-121

1

Local Network Controller (LNET)

R68802
Initialization Procedure for a-Bit MPU Bus

Interrupt Vector Number Register (IVNR)

Write cycle l-write the Mode byte on the data bus.
Write cycle 2-write the Interrupt Vector Number on the data
bus.
Write cycles 3 through 4 or 3 through 8-write the two- or sixbyte Station Address (depending on the Station Address Size
loaded into the Mode Register), least significant bytes first.

Mode Register (MR)
7

If an interrupt condition occurs (as reported by bits in Status
Register 1 and Status Register 2), IRQ is asserted to request
MPU interrupt service. Upon lACK input assertion, the Interrupt
Vector Number (IVN) from the Interrupt Vector Number Register
(IVNR) is placed on the data bus (DO-D7). The IVN must be the
second byte initialized dUring LNET initialization. The IVN is set
to $OF upon RESET or setting the RESET bit to 1 in Command
Register 1.

6
IFWT

Station Address Register (SAR)
7

The Mode Register sets conditions during initialization for use
during normal operations. It must be the first byte written during
initialization. All mode bits are active high, i.e., = 1. All bits are
cleared upon RESET or setting the RESET bit to 1 in Command
Register 1.
MR IFWT
-Interframe Wait Time
7-5
No. of TXCLKs
000
16
001
32
010
48
011
64
80
100
101
96
110
112
111
128
MR

!

o

BYTE -Data Bus Byte Mode
Select word mode (for use with 16-bit MPU bus).
Select byte mode (for use with 8-bit MPU bus).

I

3

2

o

OPERATING REGISTERS
The command or status registers are addressed during an MPU
write or read, respectively, after initialization is complete as
indicated by the LNET Initialized bit in Status Register 1. In word
mode, both command registers are written during one write
cycle. Command Register 1 occupies the lower byte of the word.
Likewise, while reading the status registers in word mode, Status
Register 1 occupies the lower byte of the word.

COMMAND REGISTERS

Assert only DONE on collision.
Assert iRa and DONE on collision.

Command Register 1 (CR1)
Command Register 1 controls the operation of the LNET. All
command bits are active high (i.e., = 1).

MR

o

4

The Station Address Register holds the Station Address for the
Receiver Address Recognition circuitry. The Station Address
bytes must be written to the LNET following the Interrupt Vector
Number during the initialization sequence. Either two or six
bytes must be written, least significant bytes first, depending on
the Station Address Size loaded into the Mode Register.

3 INTCOL -Interrupt on Collision

1.

5

Station Address

MR

'0

6

DISRX -Disable Receiver
Enable receiver after each packet reception.
Disable receiver after each packet reception.

MR
CRl
7 RESET -Reset
'0 Enable LNET operation.
Reset LNET.

1 NOLC

o

-No Length Count
Use length count in packet format.
Do not use length count in packet format.

MR

.Q

o
1

Note: The RESET bit is automatically cleared to 0
upon the completion of the reset sequence. This
bit is unaffected by the RESET pin level.

SAS
-Station Address Size
6-byte station address.
2-byte station address.

1-122

Local Network Controller (LNET)

R68802
CR1
~

A change in any of these status bits causes IRQ to be asserted
(except as noted). Reading of the status registers resets the
individual bit or encoded field that caused the IRQ assertion and
negates IRQ (except as noted). In the byte mode, both status
registers must be read in consecutive read cycles.

ENRX -Enable Receiver after Packet Reception
Disable receiver after packet reception.
Enable receiver after packet reception. This bit must be
set after each packet is received to enable reception of
the next packet only if bit 2 in the Mode Register is set
at initialization. Reception of the packet clears this bit.

o

Note: This bit is not used if bit 2 In the Mode Register is
not set at intitialization.

Status Register 1 (SR1)
7

1

o

o

011

CR1

l.

INLOOP-Internal LNET Loopback Test
Enable LNET normal operation.
1
Enable LNET internal loopback operation.

100
101

o

CR1
1 ODDNO -Odd Number of Bytes
Transmit even number of bytes in a block.
Transmit odd number of bytes in a block.

110

o

CR1

111

Q ENMAU -Enable MAUREQ
Negate MAUREQ.
Assert MAUREQ.

1

6

5

RXSTAT

HRTBT -Heartbeat Absent
Heartbeat present.
Heartbeat absent (part of the transmission algorithm is
to listen for the heartbeat before posting transmit status.
Set concurrent with the transmitter status field.). The
Heartbeat test checks the collision detection circuitry by
listening for a "ping" within seven TXCLKs after the end
of a transmission).

Transmitter idle.
Transmit successful.
Collision (Assertion of SIGQUAL within the first 512 bit
times causes DONE, or DONE and IRQ, to be asserted
depending on the state of MR bit 3).
Signal Quality error (SIGQUAL asserted after the first
512 bit times).
Transmit retry count exceeded.
Transmit buffer underflow during transmission (indicates the TXFIFO emptied between the 16th data byte
delivered for transmission and the assertion of DONE).
Transmit in progress (indicates the real time activity of
the TXDATA pin. This state does not set the IRQ bit in
SR2 nor cause IRQ to be asserted. This bit pattern is
not reset to the transmitter idle pattern upon reading
SR1.
MAUAVAIL changed state during transmission.

SR1

.!

ODD
-Odd Number of Receive Bytes
Even number of bytes in the receive packet.
Odd number of bytes in the receive packet.
1

o

Command Register 2 (CR2)
7

o

2
ODD

6-4 TXSTAT -Transmitter Status

000
001
010

MILOOP-Manchester Interface Loopback Test
Negate MILOOP to command MI normal operation.
Assert MILOOP to command Mlloopback operation.

o

4

SR1

CR1

o

5

TXSTAT

SR1

CR1
4 NOISOL-No Isolate
Assert ISOLATE to the MI to request that the MAU isolate itself from the medium.
Negate ISOLATE to the MI to request that the MAU
connect itself to the medium.

~

6

HRTBT

CR1
.§. RECALL-Receive All Packets
o Receive only addressed packets. The address must
correspond to the Station Address loaded into the Station Address Register upon initialization.
Receive all packets (regardless of address).

4

I

3

2

o

Reserved for future use

SR1

This register not presently in use. When programming, $00
should be written to CR2 to assure future software compatibility.
In byte mode, $00 must be written to this register following the
Command Register 1 write cycle.

000
001
010
011
100
1O~
110

2-0 RXSTAT -Receiver Status

STATUS REGISTERS
The two interrupt driven status registers report the status of the
LNET receiver and transmitter operations. Status registers cannot
be polled, they can only be read upon interrupt service by the
MPU. Status is reported in either discrete or encoded bits. All
discrete (or non-enCOded) status bits are active high (i.e., = 1).

111

1-123

Receiver Idle.
Receive successful.
Minimum packet size error.
Receive buffer overflow.
Frame terminated on a non-byte boundary error.
Frame Check Sequence (FCS) error.
Receive in progress (indicates a valid address has been
recognized and DONE has not been asserted. This
state does not set the IRQ bit in SR2 nor cause IRQ to
be asserted. This bit pattern is not reset to the receiver
idle pattern upon reading SR1.
Reserved

D

Local Network Controller (LNET)

R68802

transmitting half on TXOATA. From the assertion of TXREQ to
the end of the 16th OMAC bus cycle, no more than 128 TXCLKs
can elapse.

Status Register 2 (SR2)
7

5

IRQ

INIT

4

MAUAVAIL 1

2
3

o

COLCNT

RECEIVE DATA BUFFER (RXFIFO)

SR2

J....

o

The Receive data buffer is a 32-byte FIFO register file (RXFIFO)
which can be read only during OMA service. One half of the
RXFIFO is a receiving buffer for the data from the Serial-to-Parallel Register; the other half is a reading buffer for the data ready
to be transferred to the MPU bus. As soon as the receiving
buffer is full, these two halves switched roles. If the receiving
buffer is fully loaded before the reading buffer is empty, IRQ is
asserted and the receive buffer overflow bit pattern (011) IS set
in Status Register 1.

IRQ
-Interrupt Request
An interrupt condition has not occurred and IRQ has not
been asserted.
An interrupt condition has occurred and IRQ has been
asserted.
Note: This bit is cleared when S R2 is read and there is
no pending interrupt condition.

SR2
6

o

The time it takes to unload the reading buffer under OMAC control must be less than the time it takes to load the receiving
buffer from RXOATA. The loading time IS 128 RXCLKs.

-Not used
Always reads zero.

SR2

INPUT/OUTPUT FUNCTIONS

~

INIT
-LNET Initialized
o LNET initialization not complete.
1
LNET initialization complete (set after the last station
address byte has been written).

In addition to being directly compatible with the 68000 and the
68008 MPU's, the LNET supports OMA transfers when used
with the 68440, 68450, AMZ9516, or AMZ8016 OMA controller.
The LNET also provides the necessary synchronous signals for
interfacing to the Manchester Interface device.

Note: This bit is cleared upon RESET or RESET bit set
in Command Register 1.

MPU INTERFACE
SR2

.!

o
1

Transfer of data between the LNET and the system bus Involves
the follOWing signals: Oata Bus 00 through 015 and control singals consisting of R/W, OTACK, CS, lACK, and OS.

MAUAVAIL-MAU Available
MAU is not available.
MAU is available.

16-Bit MPU Interface

Note' This bit is not cleared when SR2 is read.

When connecting the LNET to the 16-bit 68000 MPU data bus,
the LNET OS input is connected to the bus LOS line and the
LNET 00-015 data lines are connected to the bus 00-015 data
lines (see Figure 4).

SR2
3-0 COLCNT -Collision Count
0000 Zero

1111

Bit 4 in the Mode Register, left in its default value of 0 during
initialization, selects the word mode. In the word mode, a read
of both status registers performed with one word read cycle
transfers Status Register 1 on 00-07 and Status Register 2 on
08-015. A write to the command registers is also accomplished
in one cycle which transfers Command Register 1 on 00-07 and
Command Register 2 on 08-015.

Fifteen
Note: Reset to zero when the enable MAUREQ bit is set
in CR1. If Mode Register bit 3 is negated the
changing count does not generate IRQ interrupts.

TRANSMIT DATA BUFFER (TXFIFO)

a-Bit MPU Interface

The Transmit data buffer is a 32-by1e FIFO register file (TXFIFO)
which can be loaded only by OMA service. One half of the
TXFIFO loads data for transmission via the OMAC; the other
half holds data currently being transmitted out serially on
TXOATA. When the transmitting half is empty it becomes the
loading half and the current loading buffer becomes the transmitting half. If the transmitting buffer empties before the loading
buffer is fully loaded, TROis asserted and the transmitter buffer
underflow bit pattern (101) is set in Status Register 1.

When connecting the LNET to the 8-bit 68008 MPU data bus,
the OS input is connected to the bus OS line and the LNET 0007 data lines are connected to the bus 00-07 data lines (see
Figure 5).
Bit 4 of the Mode Register set to 1 during initialization selects
byte mode. In the byte mode, reading of the ,status registers is
performed with two consecutive byte read cycles to enable first
Status Register 1 and then Status Register 2 onto 00-07.
Writing to the command registers also requires two consecutive
byte write cycles with Command Register 1 transferred first followed by Command Register 2.

The time required to load half the transmitter buffer under OMAC
control must be less than the time it takes to serialize out the

1-124

R68802

Local Network Controller (LNET)

Read/Write Operation

MANCHESTER INTERFACE (MI) SIGNALS

The RlW input controls the direction of data flow on the data
bus. CS (Chip Select) enables the LNET for access to the
internal registers and other operations. When CS is asserted
the data I/O buffer acts as an output driver during a read operation, and as an input buffer during a write operation. CS must
be decoded from the address bus and gated with address strobe
(AS).

The abbreviation MI refers to the Manchester Interface component(s) necessary to interface the LNET to an IEEE 802.3
specified Media Access Unit (MAU).

SENSE (Sense Carrier) Input
The MI asserts SENSE when it has detected a change in Carrier
Sense from no carrier present to carrier present. SENSE stays
active as long as carrier is present and is negated when the
carrier disappears.

If the LNET is selected (CS = low) for a read (RlW = high),
data is placed on the data bus from the status register when the
OS Is asserted. The LNET asserts Data Transfer Acknowledge
(DTACK) concurrent wrth the output data.

ISOLATE (Isolate Message Request) Output
The LNET asserts ISOLATE to direct the MI to send an Isolate
message to the MAU. When
is negated, the MI sends
a Normal message to the MAU unless the LNET requires that
the MAU request message be sent to permit data output.

If the LNET is selected (CS = low) for a write (RlW = low), OS
strobes data Into the selected register and the LNET asserts
DTACK immediately after OS is asserted.

iSC5LAi'E

DMA INTERFACE

MAUREQ (MAU Request) Output

During receiving or transmitting data from the MPU bus, the
LNET asserts a receive or transmit request (RXREQ or TXREQ)
to the DMAC. A DMA acknowledge (DACK) signal is asserted
in response to RXREQ or TXREQ when the DMAC is ready to
service the request. Both receive request and transmit request
share the same DACK pin; therefore, in the case of DMAC
devices with a DACK for each channel, they must be ORed
together externally.

The LNET asserts MAUREQ when CR 1 bit 0 is active. MAUREQ
stays active and a MAU request message is sent until the end
of a packet transmission.

MAUAVAIL (MAU Available) Input
The MI asserts MAUAVAIL when an MAU available message
from the MAU is received. MAUAVAIL is negated when an MAU
not available message is received from the MAU.

Transmit DMA Request
SIGQUAL (Signal Quality) Input

In servicing the TXREQ, the DMAC writes to the TXFIFO a byte
or a word at a time. The TXFIFO Input pOinter (TIP) is advanced
and data latches on the rising edge of OS.

SIGQUAL is asserted by MI when a Signal Quality Error Message is received from the MAU.

Receive DMA Request

TXEN (Transmission Enable) Output

In servicing the RXREQ, the DMAC reads from the RXFIFO a
byte or word at a time. Data is enabled out on the falling edge
of DACK and the RXFIFO output pointer (ROP) is advanced on
the rising edge of DACK. The data lines are tri-stated following
the rising edge of DACK.

The LNET starts a transmission by asserting TXEN and outputs
serial data on TXDATA which is Manchester encoded by the MI.
TXEN is active until the end of the transmission.

DONE

RXCLK shifts receive data into the LNET and is free running at
1Q MHz, or slower.

DONE is a bidirectional signal line to or from the DMAC. With
the AMZ8016 and the AMZ9516, DONE auto-Initializes the
DMAC back to the start of the packet when a collision occurs
during transmission. With the 68440, the DONE output is routed
to the 68440's PCL input after gating with TXREQ line. For the
68450 it is necessary for the MPU to reinitialize the DMAC on
collision.

The TXCLK is a free running 10 MHz, or slower, clock used to
clock data into the MI and perform operations in the transmitter.

RXCLK (Receive Clock) Input

TXCLK (Transmitter Clock) Input

MILOOP (MI Loopback) Output
The MILOOP output signals the MI component(s) that the current data is a test frame and it is to be "looped back" to the
LNET instead of being sent to the MAU.

INTERRU,PTS
The IRQ output asserts when there is status information available after the completion of a transmit or receive transaction.
The MPU grants the Interrupt by asserting an Interrupt acknowledge (lACK) signal and reads the interrupt vector when the
LNET asserts data transfer acknowledge (DTACK). The subsequent negation of lACK and IRQ preceed MPU Interrupt
processing.

1-125

II

R68802

Local Network Controller (LNET)

LNET FUNCTIONAL DESCRIPTION
The LNET transmits and receives serial data on an IEEE 802.3
CSMNCD Access Method defined communications medium
and transfers parallel data to and from a host system under program or DMA control according to the IEEE 802.3 data link
specification.

Frame Format
Serial data transfers synchronously between the LNET and the
MI within the frame structure for data communications using
local area network media access control (MAC) procedures.
Each MAC frame, or packet, consists of eight fields: Preamble,
Start Field Delimiter (SFD), Destination Address, Source
Address, Length Count, Data, Pad and Frame Check Sequence
(FSC). Figure 3 illustrates the frame format.
The Preamble consists of seven bytes of alternating l's and D's,
i.e., 1010 ... 1010.
The Start Field Delimiter (SFD) consists of one byte of bit pattern 10101011 immediately following the Preamble pattern which
indicates the start of a valid frame.
The Destination and Source Addresses are either two or six
bytes in length. Addresses may be anyone of the following
three types: Station Address, Logical Group, or Broadcast. Logical Group and Broadcast Addresses are identified by a 1 in the
first bit position received. The first bit of a Station Address is O.
The Length Count field is two bytes in length and specifies the
Data field length (in an Ethernet application this field is the Type
field and the Length Count field in the Mode Register must be
initialized appropriately).
The Data field can have a variable number of bytes. If the Data
field is less than 46 bytes (in a six-byte address mode), or less
than 54 (in a tWO-byte address mode), pad bytes are added to
the frame on transmission to bring the overall packet size up to
the minimum size of 72 bytes. The maximum Data field length
must be programmed into the DMAC operating with the LNET.

The assertion of SENSE defines the beginning of a frame. The
rising edge of RXCLK enables SENSE and concurrently the first
Preamble bit on RXDATA to the LNET. The falling edge of
RXCLK shifts the first bit of the Preamble into the Delimiter Recognition logic and SENSE into the SENSE Detection logic.
Delimiter Recognition is deferred for eight RXCLKS after the
assertion of SENSE, to give the MI unit time to synchrOnize on
the Preamble.
If sequential zeros are detected during the time the LNET is
searching for the double ones delimiter, the packet's reception
is aborted.
The Preamble bits are shifted through the Delimiter Recognition
logic without result. As the last bit of the Delimiter is shifted in,
an internal signal is asserted.
The data is then routed to the Receive CRC and the Serial-toParallel Register. The Byte Alignment and Odd/Even byte monitor is initialized, and a Byte Counter is started.
At the appropriate byte count, the first byte of Destination Address
is converted to parallel data, and compared with the first byte
of Station Address and loaded into the RXFIFO.
The RXFIFO Input Pointer (RIP) is then advanced by one. The
next byte(s) of destination and source addresses are loaded in
the same manner. As the two length count bytes are sent to the
RXFIFO they are also loaded into the Length Counter. If this
field is non-zero it is decremented on each succeeding byte of
the packet.
The remainder of the first 16 bytes of the packet are loaded into
the RXFIFO (unless the Length Counter reaches its terminal
count or the packet terminates).
With 16 bytes buffered, the RXFIFO is half full. RXREQ is now
asserted, the receiving half of the buffer becomes the reading
half, and the first 16 bytes of receive data are unloaded by
advancing the RXFIFO Output Pointer (ROP) as a function of
the DMAC's DACK and OS Signals. Meanwhile the empty,
receiving half, of the RXFIFO continues to fill.

The Frame Check Sequence (FCS) field is four bytes in length.

Frame Reception
The Receiver consists of the following sections: Delimiter Recognition, Receive CRC, Serial-to-Parallel Register, Receive
Length Counter, Address Recognition, and a 32-byte FIFO register file (RXFIFO). These registers are all driven or loaded by
RXCLK or a derivative.
In the absence of serial input data from the network bus, the
SENSE Input from the MilS Inactive. The Receive Clock (RXCLK)
is free running and the Receiver front end is idling.

As the 32nd byte of received data is loaded, RXREQ is asserted
again and RIP proceeds to the just emptied reading buffer while
DMA bus cycles unload the new reading buffer.
The RXFIFO continues to load and unload in this manner
throughout the duration of the packet's Data field.
The position of RIP indicates when to load the Length Counter
from the data stream, when to check for a valid address, when
to assert or negate RXREQ and to flag an overrun of the receive
DMA service.

PREAMBLE

START
FIELD
DELIMITER
(SFD)

DESTINATION
ADDRESS

SOURCE
ADDRESS

LENGTH
COUNT

7
BYTES

1

20R 6
BYTES

2 OR 6
BYTES

2
BYTES

BYTE

DATA

.. ..

----,---------,
PAD

FRAME
CHECK
SEQUENCE

•• •• -----+--------1

...

72 BYTES MINIMUM

Figure 3.

MAC Frame Format
1-126

VARIABLE NO.
0 F BYTES

4
BYTES

Local Network Controller (LNET)

R68802

Upon the assertion of the DONE input by the DMAC (at the time
of the last byte or word transfer), the transmitter finishes serializing the last bytes out, zeros the TXFIFO Input Pointer (TIP)
and serializes the contents of the CRC Register out on TXDATA.

The two-byte Length Counter is located either four or twelve
bytes (depending on the address mode) after Valid Delimiter.
The Length Counter is decremented every eight RXCLKs. When
the Length Counter equals zero, indicating the end of the Data
field, RIP is disabled and RXREQ asserts long enough to unload
the last bytes.
In the case of a normal termination of the packet, after the last
bytes are unloaded, the LNET asserts DONE concurrent with
the last DACK strobe and negates RXREQ. The CRC Register
continues to calculate over the Pad and Frame Check Sequence
fields and the Byte Alignment Checker continues to run until
packet end. The state of the Odd/Even byte checker is latched
at the time of the Length Counter's terminal count.

If SIGQUAL is asserted by the MI during the first 512 TXCLKS,
the LNET assumes there has been a colliSion between its own
transmission and that of another node in the network. The
response of the LNET at its MI interface is to abort the frame
transmiSSion after appending a Jam signal consisting of 48
alternating zeros and ones to it. The Jam signal is sent whenever the LNET has successfully contended for the medium and
then has been interrupted in its transmission during the COllision
window.

The end of the packet is recognized as follows. The last FCS
bit shifts in as RXCLK goes low in the normal manner. Two
RXCLKs later the negated value of SENSE shifts in. At the next
rising edge of RXCLK the CRC syndrom is compared and the
result IS posted to Status Register 1 and IRQ IS asserted.

The response of the LNET at its MPU/DMAC interface to a collision is programmable to one of two modes in the Mode RegIster at initialization.

DMA TRANSFER MODES

ThiS allows for the LNET to be used with DMACs of differing
capabilities. Specifically, some DMACs need to be reinitialized
by the MPU if they are to restart a block transfer that has been
aborted by a peripheral's assertion of a DONE and an IRQ.
Others are capable of automatically re-starting a block by themselves if a DONE is detected during a transfer.

If, during the course of a reception, the Data byte count held
by the system exceeds the maximum number (1500 bytes for
Ethernet), a maximum frame size error is flagged by DONE from
the DMAC. The LNET responds by negating ~ and
clearing the status registers without generating an IRQ.

Frame Transmission

Mode One: Assert IRQ plus DONE On Collision.

The Transmitter consists of the following: Parallel-to-Serial Register, Transmit Length Counter, 32-byte Transmitter FIFO register file (TXFIFO), Transmit CRC Generator, Preamble and
Delimiter Generator, Jam Generator, Interframe Delay Counter,
and the Binary Exponential Back-Off Counter. These sections
are all driven by TXCLK or a derivation.

Assertion of SIGQUAL during the first 512 TXCLKS after transmission begins sets the collision code (010) In the encoded
Transmitter Status field in Status Register 1 and increments the
ColliSion Count field In Status Register 2 by one. Next, IRQ is
asserted, and the Interrupt Vector Number from the Interrupt
Vector Number Register is output on the data bus when lACK
is asserted.

Frame transmission commences with a MPU write to Command
Register 1 setting the Enable MAUREQ bit. The LNET responds
by asserting Transmit DMA Request (TXREQ). Under DMA
control, 16 bytes are loaded from the MPU bus Into the TXFIFO
by advancing the TXFIFO Input Pointer (TIP) as a function of
DACK and DS. The LNET then negates TXREQ until the first
byte of this data has been serialized out.

The MPU processes the interrupt by reading the status registers
to determine the cause of the interrupt and to clear the interrupt.
The MPU then reinitializes the DMAC and reloads the first 16
bytes of the aborted data packet into the TXFIFO. Meanwhile
the LNET is sending the Jam signal fOllowed by a delay interval
determined by the Binary Exponential Back-off Counter. At the
end of this time interval the LNET begins to transmit the preamble
and delimiter again if the TXFIFO has been reloaded with the
first 16 bytes of the packet. If the TXFIFO has not been reloaded
by the time the Jam signal and the back-off delay interval are
over, the LNET will wait for data.

While the first 16 bytes are being loaded into the TXFIFO, the
LNET is monitoring the SENSE input Upon SENSE negation
the Transmitter waits 96 TXCLKS (strict IEEE 802.3 or Ethernet
application, otherwise the delay follows whatever is programmed into Mode Register bits 5-7) and then serializes out
the first byte of data on TXDATA if the TXFIFO is half full (if it
is not half full yet, the LNET retums to monitoring SENSE). If
SENSE is active the LNET waits until it is negated and then
starts the Interframe Delay Counter.

Mode Two: Assert only DONE On Collision_
Upon the assertion of SIGQUAL during the first 512 TXCLKs,
the LNET zeros the TIP, asserts DONE to the DMAC concurrent
with the next DACK signal, increments the retry count and
remains in the transmit mode (TXREQ asserted, etc.), the Jam
is sent, and the Back-off delay IS observed. In the meantime,
16 bytes of data are loaded Into the TXFIFO by the DMAC. The
packet is then transmitted as before.

At the terminal count of the Interframe Delay Counter the first
preamble bits are shifted out under TXCLK control and the
transmitter begins to monitor the SIGQUAL input. At the same
time TXREQ is asserted again and another 16-byte data burst
is transferred into the empty half of the TXFIFO.

If the MI asserts SIGQUAL after the first 512 TXCLKs, IRQ is
asserted and the Transmitter Status field in Status Register 2
is set to 011.

As the TXFIFO Output Pointer (TOP) advances to the first byte
of the most recently filled half of the buffer, TXREQ is again
asserted to reload the half just emptied.
1-127

II

:u
en
(X)
(X)

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A1-A23
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68440
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R6880'
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~
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RXCLK

lACK

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MILOOP

+5V~~

§I
SYSTEM CLOCK

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IACK5
IACK6

----

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Typical Interface to 6800o-Based System

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2-

ii'

r

Z

m

~

Local Network Controller (LNET)

R68802
'1'

,~

i""<

..,I[

RXCLK

~

...,

-0

iRQ

,

'

-0-

NOTE: Timing measurements are referenced to and from a low voltage of
0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

TXCLK

TXOATA

TXEN

SIGQUAl

OS

-t

NOTE: Timing measurements are referenced to and from a low voltage of
0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

*iRQ assertion on collision

not required-Bit 3 of the mode register
(MRl determines whether or not IRQ asserts on collision.

Figure 7.

Manchester Interface Serial Transmitter Timing

1..130

~

j

~

Figure 6. Manchester Interface Serial Receiver Timing

ISOLATE

-~

~k-

...

MILOOP

-®---+

-'

~

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.....

os

.

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RXOATA

SENSE

.

',:::--

R68802

Local Network Controller (LNET)

II
00-07/00-015;-----------------~r

~----......:.,-

NOTE:

Timing meesurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

Figure 8.

LNET Read Cycle Timing

cs
os
Rfii
Di'ACK
19
00-07/00-015
NOTE:
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

Figure 9.

LNET Write Cycle Timing

1-131

R68802

Local Network Controller (LNET)

00-07100-015
~----~34~----~

RiW

NOTES: 1. Timing measurements are referenced to and from a low yoltage of 0.8 Yolts and a high yoltage of 2.0 Yolts, unless otharwlse
noted.
2. Word mode only.

Figure 10. . LNET to Memory DMA Transfer Cycle Timing

1·132

R68802

Local Network Controller (LNET)

MPU
CLOCK

DO-D7/D()'D15

DONE (TO LNET)

00iiiE (FROM LNET)

NOTES: 1. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwlee
notad.
2. Word mode only.

Figure 11. Memory to LNET DMA Transfer Cycle Timing

1·133

R68802

i

l
~

Local Network Controller (LNET)

IRQ

.

I
lACK

OTACK

OS

00-07

NOTE: Timing measurements are referenced to end from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless
otherwise noted.
Figure 12.

Interrupt Request Cycle Timing

1-134

R68802

Local Network Controller (LNET)

SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Vee = 5.0Vdc ± 5%, V s = OVdc, T A = 0 to 70°C)
Number
1

Characteristic
Clock Period

Symbol

Min

Max

Unit

tcp

90

1000

ns

Typ

2

Receive Clock Pulse Width

tCFR

45

-

ns

3

Receive Data/Sense Setup

tRXS

30

-

ns

4

RXDATA, Sense Hold Time

t RXH

20

-

5

IRQ Delay from RXCLK

tRIO

0

6

DS to IRQ Clear (Status Read)

tOlD

50

7

TXDATAlTXEN Delay (C l = 35pF)

trxo

20

8

SIGQUAL Hold Time

tCPH

0

9

IRQ Delay from SIGQUAL Edge (Optional),

t ,SO

0

10

MAU/MI Control Output Delay

t MOO

0

11

R/W High to CS, DS Low

t RHSl

0

12

CS Low to DTACK Low

tCLDAL

20

13

CS,

tSHRl

20

14

CS High to DTACK Tristate

tSHDAT

20

DS High to R/W Low

ns
80

-

ns
ns

60

-

ns
ns
ns

80

ns

80

ns

80

ns

-

ns

40

40

ns

15

CS, DS Low to Data Valid

tSLCV

0

140

ns

16

CS, DS High to Data Invalid

t SHOI

10

150

ns

17

R!W Low to CS,

tRlSl

0

CS, DS High to R/W High

tSHRH

20

-

ns

18
19

Data Valid to CS, DS High

tovsH

100

-

ns

20

CS, DS High to Data Invalid

t SHOI

10

-

21

lACK Low to DTACK Low

t'ALAl

20

40

80

ns

22

lACK High to DTACK Tristate

tlAHDAT

20

40

80

ns

23

lACK Low to Data Valid

t'AlOV

0

140

ns

24

DS High to Data Invalid

t'SHOI

10

50

ns

25

DACK Low to DONE/Data Valid

tOlDV

0

50

ns

26

DTACK High to DONE Invalid/Data

tOHDV

0

40

ns

27

DS Low to DACK High

t OlOH

0

50

ns

28

DS High to Data Invalid

t SHOI

0

40

ns

29

Data Invalid to DS High

t OVSH

65

-

ns

30

Clock Low to DONE (to LNET) Low

t ClOl

0

100

ns

70

250

ns

31

DS Low

External DONE Pulse Width

t EOPW

ns

ns

ns

32

DACK Low to Internal DONE Low Delay

t OLIO

80

33

DACK High to Internal DONE High Delay

t OHIO

80

34

DONE Low to RXREQ High

tOLRXH

2

RXCLK

35

DS High to IRQ High

tOSHIH

2

RXCLK

Note:
'IRQ assertion on collision dependent on bit 3 of mode register (MR).

-

1-135

ns

D

Local Network Controller (LNET)

R68802

THERMAL CHARACTERISTICS

MAXIMUM RATINGS
Characteristics

Characteristics

Symbol

Value

Supply Voltage

Vcc

-0.3 to + 7.0V

Input Voltage

V IN

-0.3 to + 7.0V

Operating Temperatures
Storage Temperatures

Symbol

Thermal Resistance
Ceramic
Plastic

TA

o to 70"C

T STG

-55 to +150"C

Value

Rating

50

"C/W
"C/W

8JA

68

Note:
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
normal precaulions should be taken to avoid application of any
voltage higher than maximum-rated voltages to this high-impedance circuIt. Reliability of operation is enhanced if unused inputs
are tied to an appropriate logic voltage level (e.g., either Vss or
Vccl·

DC ELECTRICAL CHARACTERISTICS (Vee = 5.0Vde ± 5%, Vss = OVde, T A = 0 to 70°C unless otherwise noted)
Characteristics

Symbol

Min

Max

Unit

Input High Voltage

V IH

+2.0

Vcc

V

Input Low Voltage

V IL

-0.3

+0.8

V

Input Leakage Current
R!W, RESET, CS

liN

Input Leakage Current for Three-State (Off)
DTACK, DO-D15

ITSI

Output High Voltage _ _ _
RXREO, TXREO, DTACK,
DO-D15, MILOOP, MAUREO, ISOLATE
TXEN, TXDATA

V OH

Output Low V~
RXREO, TXREO, TXEN, TXDATA, DTACK, DO-D15
MILOOP, MAUREO, ISOLATE
IRQ, DONE

VOL

Power Dissipation

PINT

Input Capacitance

CIN

-

V,N
Vcc

J1-A

V IN .~ 0.4 to 2.4V
Vcc ~ OV

-

1·136

~

0 to 5.25V
OV

-

V
V
V

Vcc ~ 4.75V
I LOAO ~ -400 J1-A, C LOAD ~ 130 pF
I LOAD ~ -400 J1-A, C LOAD ~ 32 pF
I LOAD ~ 0, CLOAD ~ 30 pF

-

0.5

V

Vec ~ 4.75V
I LOAD ~ 3.2 mA

-

0.5

V

I LOAD

-

1.0

W

TA

-

13

pF

Vcc ~ 5.0V
V ,N ~ OV
f ~ 1 MHz
TA ~ 25"C

+2.4
+2.4
+2.4

/

-

~

J1-A

10

10

Test Conditions

~

~

8.8 mA

25"C

R68802

Local Network Controller (LNET)

PACKAGE DIMENSIONS
40-PIN CERAMIC DIP

::In

[: D

I----A-------jl
i

H-I,-II

-ILo

'I

SEATING

en

lij---1
---"'PlAN~t ~
-+-J

1 [I

M

-1

MILLIMETERS
1M MIN MAX
50 29 51 31
A
1486 1562
8
C
254
419
036
053
F
076
140
G
254BSC
H
076
178
J
020
0.33
K
254 419
L
1460 1537
M
IY'
10"
N
051
152

o

INCHES
MIN
MAX
1 960 2.020
0585 0615
0100 0.165
0015 0021
0030 0055
0100BSC
0030 OU70
0006 0013
0100 0165
0575 0605
IY'
10"
0020 0080

40-PIN PLASTIC DIP
MILLIMETERS
INCHES
OIM MIN MAX
MIN
MAX
A
5128 5232 2040 2060

B
C

1·137

1372 1422 0540

0560

355
036

508 0140
051 0014

0200
0020

F

102

152 0040

0060

G
H
J
K
L
M
N

254BSC
165 2.16
020 030
305
356
1524 BSC
10°
051
102

o

r

0100BSC
0065 0085
0006 0012
0120 0140
0600 BSC
7'
10°
0020 0040

II

R68C552

.

:"

'1'

R68C552
DUAL ASYNCHRONOUS, COMMUNICATIONS
INTERFACE ADAPTER (DACIA)

Rockwell

PRELIMINARY
DESCRIPTION

FEATURES

The Rockwell CMOS R68C552 Dual Asynchronous Communications Interface Adapter (DACIA) p'rovides an easily implemented,
program controlled interface between 16-bit microprocessor-based
systems and serial communication data sets and modems.

•

The DACIA has an internal baud rate generator. This feature eliminates the need for multiple component support circuits, a crystal
being the only other part required. The Transmitter baud rate can
be selected under program control to be either 1 of 15 different
rates from 50 to 38,400 baud, or at 1116 times an external clock
rate. The Receiver baud rate mayl;e selected under program control to be either the Transmitter rate, or at 1116 times the external
clock rate. The DACIA is programmable for word lengths of 5, 6,
7 or 8 bits; even, odd, or no parity; and 1 or 2 stop bits.
The DACIA is designed for maximum programmed control from
the microprocessor (MPU) to simplify hardware implementation.
Dual sets of registers allow independent control and monitoring
of each channel. The DACIA also provides a unique, programmable Automatic Address Recognition mode for use in a mUltidrop environment.

•

Data set/modem control functions

•

Internal baud rate generator with 15 programmable baud rates
(50 to 38,400)

•

Program-selectable internally or externally controlled receiver
rate

•

Programmable word lengths, number of stop bits, and parity
bit generation and detection

•

Programmable interrupt control

•

Programmable control of edge detect for DCD, DSR, DTR,
RTS, and CTS

•

Program-selectable serial echo mode for each channel

• Automatic Address Recognition mode for multi-drop operations
• 5.0 Vdc

The Control Register and Status Register permit the MPU to
easily select the R68C552's operating modes and determine
operational status.

±5% supply requirements

• 40-pin plastic or ceramic DiP
•

The Interrupt Enable Registers (IER) and Interrupt Status
Registers (ISR) allow the MPU to control and monitor the interrupt
capabilities of the DACIA.

Full TIL or CMOS input/output compatibility

• Compatible with R68000 microprocessor family

The Control and Format Register (CFR) permits selection of baud
rates, word lengths, parity and stop bits as well as control of DTR
and RTS output signals.

RES
OTACK
XTALI
XTALO
CLKOUT
IACK2
OSR2
OC02
CTS2
RTS2
IRQ2
Rx02
OTR2
Tx02
TxC
07
06
05
04

The Status Register (SR) gives the MPU access to the state of
the modem control lines, framing error, transmitter underrun and
break conditions.
The Compare Data Registers (CDR) hold the data value to be
used in the compare mode.
The IRQ Vector Register (IVR) holds the interrupt vector for use
in the interrupt acknowledge state, or commands a Transmit
Break and provides for parity/address recognition during Automatic Address Recognition mode.

ORDERING INFORMATION
Part Number:
R68C552

L

Low power CMOS N-well silicon gate technology

• Two independent full duplex channels with buffered receivers
and transmitters.

vss

Package:
C .. Ceramic
Plastic
P

YGJ:
RJW

CS

RS2
RS1
RSO
IACK1
OSR1
OC01
CTS1
RTS1
IRQ1
Rx01
OTR1
Tx01
RxC
00
01
02
03

=

Figure 1. R68C552 Pin Configuration

Document No. 68650N09
1-138

Product Description Order No. 708
Rev. 2, October 1984

Dual Asynchronous Communications Interface Adapter (DACIA)

R68C552

INTERFACE SIGNALS

RESET (RES)

Figure 2 shows the DACIA interface signals associated with the
microprocessor and the modem.

During system initialization a low level on the RES input causes a
RESETto occur. Atlhis time the IER's are sello $80, the DTR and
RTS lines go to the high state, the RDR register is cleared,
the IVR is set to $OF, the compare mode is disabled, and tre CTS,
DCD, DSR flags are cleared. No other bits are affected.

DATA BUS (00-07)
The 00-07 pins are eight data lines that transfer data between
the microprocessor (MPU) and the DACIA. These lines are bidirectional and are normally high-impedance except during READ cycle
when the DACIA is selected.

TRANSMIT DATA (TXD1, TXD2)
The TxD outputs transfer serial non-return to zero (NRZ) data to
the data communications equipment (DCE). The data is transferred, LSB first, at a rate determined by the baud rate generator.

REGISTER SELECTS (RSO, RS1, RS2)

RECEIVE DATA (RXD1, RXD2)

The three register select lines are normally connected to the processor address lines to allow the MPU to select the various internal registers. Table 1 shows the internal register select coding
and identifies the abbreviations (ABBR) used throughout the text
for each register. Table 2 summarizes the control and status
registers and shows each bit allocation.

The RxD inputs transfer serial NRZ data into the DACIA from the
DCE, LSB first. The receiver baud rate is determined by the baud
rate generator.

CLEAR TO SEND (CTS1, CTS2)
The CTS control line inputs allow handshaking by the transmitter.
When CTS is low, the data is transmitted continuously. When CTS
is high, the Transmit Data Register empty bit in the ISR is not set.
The word presently in the Transmit Shift Register is sent normally.
Any active transition on the CTS lines sets the CTS bit in the
appropriate ISA. The CTS status bit in the SR reflects the current high or low state of CTS.

READ/WRITE (R/W)
The RiW input, generated by the microprocessor, controls the
direction of data transfer. A high on the RiW line indicates a read
cycle, while a low indicates a write cycle.

CHIP SELECT (CS)

DATA CARRIER DETECT (DCD1, DCD2)

The chip select input is normally connected to the processor
address lines either directly or through decoders. The DACIA
latches address and RiW inputs on the falling edge of CS and
latches the data bus inputs on the riSing edge of CS.

IACKl
LOGIC

IACKl

R/W
CS
RES
DTACK
RSO
RSl
RS2

<...A

l

IRQ2

IACK2

-"
00-07
-y

)

ACIA
CHANNEL 1

)

ACIA
CHANNEL 2

ACIAl BAUD
RATE SELECT

1/0 CONTROL

AND
REGISTER
SELECT
LOGIC

eTSl
DCDl
DSRl
RxDl
TxDl
DTRl
RTSl

ACIAl
REGISTERS
AND
CONTROL
LOGIC

ACIAl
INTERRUPT
LOGIC

IRQl

R68000
BUS

These two lines may be used as general purpose inputs. An active
transition sets the DCD bit in the ISA. The DCD bit in the SR
reflects the current state of the DCD line.

I

DATA
BUS
BUFFERS

DTACK
LOGIC
CLOCK
LOGIC
DATA
1/0
MUX

ACIA2
INTERRUPT
LOGIC

Figure 2.

ACIA2 BAUD
RATE SELECT

ACIA2
REGISTERS
AND
CONTROL
LOGIC

IACK2
LOGIC

DACIA Interface Signals
1-139

..

RxC
XTALI
CLKOUT
XTALO
TxC

RTS2
DTR2
TxD2
RxD2
DSR2
DCD2
CTS2

Dl,Jal Asynchronous Communications Interface Adapter (DACIA)

R68C552

DATA SET READY (DSR1, DSR2)

CRYSTAL (XTALI, XTAlO)

These two lines may be used as general purpose inputs. An active
transition sets the DSR bit in the ISA. The DSR bit in the SR
reflects the current state of the DSR line.

These pins are normally connected to an external 3.6864 MHz
crystal used as the time base for the baud rate generator. As an
alternative, the XTALI pin may be driven with an externally
generated clock in which case the XTAlO pin must float.

REQUEST TO SEND (RTS1,

RT§2)

These two lines may be used as general purpose outputs. They
are set high upon reset. Their state may be programmed by set!!!:!9..the appropriate bits in the CFR high or low. The state of the
RTS line is reflected by the RTS bit in the SA.

RECEIVER CLOCK (RxC)
This pin is the Receiver 16x clock input when the baud rate generator is programmed for External Clock. Figure 15 shows timing considerations for RxC.

DATA TERMINAL READY (DTR1, DTR2)
These two lines may be used as general purpose outputs. They
are set high upon reset. Their'state may be programmed by setting the appropriate bits in the CFR high or low. The state of the
DTR line is reflected by the DTR bit in the SA.

TRANSMITTER CLOCK (TxC)
This pin is the transmitter 16x clock input when the baud rate
generator is programmed for External Clock. Figure 16 shwos timing considerations for TxC.

INTERRUPT REQUEST (IRQ1, IRQ2)
The IRQ lines are open-drain outputs from the interrupt control
logic. IRQ1 is associated with ACIA 1 and IRQ2 is associated with
ACIA2. These lines are normally high but go low when one of the
flags in the ISR is set, provided that its corresponding enable bit
is set in the lEA.

Note
When RxC and TxC are used for external clock input,
XTAll must be tied to ground (Vss) and XTAlO must be
left open (floating).

CLOCK CIRCUIT
The internal clock oscillator supplies the time baSEl for the baud
rate generator. The oscillator can be driven by a crystal or an
external clock, or it can be disabled, in which case the time base
for the baud rate is generated by the Receiver External Clock
(RxC) and Transmitter External Clock (TxC) input pins. Figure 3
shows the three possible clock configurations.

RECEIVER
EXTERNAL
CLOCK
TRANSMITTER
EXTERNAL
CLOCK
OPEN
CIRCUIT

CLOCK OUT (ClK OUT)
This output is a buffered output from the 3.6864 MHz crystal
oscillator. It may be used to drive the XTALI input of another
DACIA. This allows multiple DACIA chips to be used in a system
with only one crystal needed. ClK OUT is in phase with XTALI.

XTALI
RxC

XTALI

EXTERNAL
XTALI
CLOCK

TxC
XTALO

XTALO
EXTERNAL
CLOCK

INTERNAL
CLOCK

Figure 3.

DACIA Clock Generation

1-140

OPEN
CIRCUIT

XTALO
EXTERNAL
CLOCK

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

II
~

DCD1
DSR1
CTB1

IIIl!1

OTR1
RTS1

RxD1

.so

~-r-----.

K:=====~~~

.S1

TxC

rL.~~__~~~~::~~

.S'

RIW

cs

XTALI
CLKOUT

XTALO

.ES

AxD.

ACtA CHANNEL 2

mm

~-----------4

~~~~~~~-+-----CTS'

L~~~J::=~~====:DSR2

DCD2

~-----~

= COMMON LOGIC
........,.......... = CONTROL LINES
~~ = 8·BITDATAUNES

'-.r---( ~

Tx02

MULTI.BIT C8:TROL LINES

Figure 4.

DACIA Block Diagram

1·141

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

FUNCTIONAL DESCRIPTION

Figure 5 shows an example of a single transmitted or received
data word. In this example, the data word is formatted with 8 data
bits, parity, and two stop bits. Figure 5 also shows a single
character transmitted or received in Address Recognition mode.
In this example, the address or data word is 8 bits, there is no
parity bit, and there are two stop bits. The 1Oth bit, (normal parity
bit) is an address/data indicator bit. A 1 means the 8 bits are an
address that will be compared with the address stored in the Compare Data Register. A 0 means the 8 bits are data.

Figure 4 is a block diagram of the DACIA which consists of two
asynchronous communications interface adapters with common
microprocessor interface control logic and data bus buffers. The
individual functional elements of the DACIA are described in the
following paragraphs.
DATA BUS BUFFER
The Data Bus Buffer is a bidirectional interface between the
system data lines and the internal data bus. When RiW is high and
CS is low, the Data Bus Buffer passes data from the internal data
bus to the system data lines. When RiW is high, CS is high, and
either lACK line is low, the IRQ vector is passed to the system
data bus. When RiW is low and CS is low, data is brought into the
DACIA from the system data bus. The following table summarizes
the Data Bus Buffer states.

PARITY MODE

I

[
START
BIT

DATA

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

PARITY STOP
BIT
BITS

ADDRESS/DATA MODE

Data Bus Buffer Summary

I 0 11 12 1 3 14 15

Control Signals
R/W CS IACK1 IACK2

I
I~

I 2 I 3 I 4 I 5 I 6 I 7 I P 11S 12S

0 I

~~------~~------~I

16

17 IYDI1S 12S I

I~

Data Bus Buffer State
ILLEGAL MODE - TRI STATE
ILLEGAL MODE - TRI STATE
ILLEGAL MODE - TRI STATE
WRITE MODE - TRI STATE
ILLEGAL MODE - TRI STATE
ILLEGAL MODE - TRI STATE
ILLEGAL MODE - TRI STATE
TRISTATE
ILLEGAL MODE - OUTPUT $OF
ILLEGAL MODE - OUTPUT $OF
ILLEGAL MODE - OUTPUT $OF
READ MODE - OUTPUT DATA
ILLEGAL MODE - OUTPUT $OF
OUTPUT IRQ VECTOR 1
OUTPUT IRQ VECTOR 2
TRISTATE

START
BIT

ADDRESS
OR
DATA
Figure 5.

o

STOP
BITS

Typical Data Word

INTERRUPT LOGIC
The interrupt logic causes the IRQ lines (IRQ1 or IRQ2) to go low
when conditions are met that require the attention of the MPU.
There are two registers (the Interrupt Enable Register and the
Interrupt Status Register) involved in the control of interrupts in
the DACIA. Corresponding bits in both registers must be set to
cause an IRQ.

INTERRUPT ENABLE REGISTER (IER)
TRANSMIT AND RECEIVE DATA REGISTERS

The Interrupt Enable Register (IER) is a write-only register that
allows each of the possible IRQ sources to be enabled, or disabled, individually without affecting any of the other interrupt
enable bits in the register. IRQ sources are enabled by writing
to the IER with bit 7 set to a 1 and every bit set to a 1 that corresponds to the IRQ source to be enabled. IRQ sources are
disabled by writing to the IER with bit 7 set to a 0 and every bit
set to a 1 that corresponds to the IRQ source to be disabled. Any
bit (except bit 7) to which a 0 is written is unaffected and remains
in its original state. As an example, writing $7F to the IER will
disable all IRQ source bits, but writing $FF to the IER will enable
all IRQ source bits. A hardware reset (RES) clears all IRQ
source bits to the 0 state. Bit assignments for the IER are as
follows:

These registers are used as temporary data storage for the DACIA
Transmit and Receive circuits. The Transmit Data Register is
characterized as follows:
•

Bit 0 is the leading bit to be transmitted.

•

Unused data bits are the high-order bits and are "don't care"
for transmission.

• Write-Only Register.
The Receive Data Register is characterized in a similar fashion
as follows:
•

Bit 0 is the leading bit received.

•

Unused data bits are the high order bits and are "0" for the
receiver.

7

•

Parity bits are not contained in the Receive Data Register, but
are stripped off after being used for external parity checking.
Parity and all unused high-order bits are "0".

CLEAR/
SET
BITS

•

Read-Only Register

1-142

6

TOR
EMPTY
IE

5
CTS
IE

4
DCD
IE

3
DSR
IE

2
PARITY
ERROR
IE

1
FRM
OVR
BRK
CPR
IE

0

RDR
FULL
IE

Dual Asynchronous Communications Interface Adapter (DACIA)

R68C552

Table 1.
HEX

00

L

L

L

01

L

L

H

02

L

H

DACIA Register Selection

CONTROL &FORMAT
REGISTER BITS

REGISTER SELECT
LINES

L

REGISTER ACCESS
REG

WRITE

READ

-

-

IER1
ISR1

INTERRUPT ENABLE
REGISTER 1

INTERRUPT STATUS
REGISTER 1

0

-

CFR1
SR1

CONTROL
REGISTER 1

STATUS
REGISTER 1

1

-

CFR1

FORMAT
REGISTER 1

INVALID

-

0

CDR1

COMPARE
DATA
REGISTER 1

INVALID

-

1

IVR1

IRQ
VECTOR 1

INVALID

03

L

H

H

-

-

TOR1
RDR1

TRANSMIT DATA
REGISTER 1

RECEIVE DATA
REGISTER 1

04

H

L

L

-

-

IER2
ISR2

INTERRUPT ENABLE
REGISTER 2

INTERRUPT STATUS
REGISTER 2

0

-

05

H

L

H

CFR2
SR2

CONTROL
REGISTER 2

STATUS
REGISTER 2

1

-

CFR2

FORMAT
REGISTER 2

INVALID

-

0

CDR2

COMPARE
DATA
REGISTER 2

INVALID

-

1

IVR2

IRQ
VECTOR 2

INVALID

TOR2
RDR2

TRANSMIT DATA
REGISTER 2

RECEIVE DATA
REGISTER 2

06

07

H

H

H

L

H

-

H

Table 2.

-

Control and Status Registers Format Summary

REGISTER BIT NUMBERS

REGISTER

7

6

5

4

3

2

1

0

CLEARISET
BITS

TOR
EMPTY
IE

CTS
IE

DCD
IE

DSR
IE

PARITY
ERROR
IE

FRM,OVR
BRK, CPR
IE

RDR
FULL
IE

INTERRUPT
ENABLE
REGISTERS

ANY
BIT
SET

TOR
EMPTY

CTS
TRANS

DCD
TRANS

DSR
TRANS

PARITY
ERROR

FRM,OVR
BRK, CPR

RDR
FULL

INTERRUPT
STATUS
REGISTERS

FRAMING
ERROR

TRANS
UNDR

CTS
STATUS

DCD
STATUS

DSR
STATUS

REC
BREAK

DTR
STATUS

RTS
STATUS

STATUS
REGISTERS

0

IVR/CDR
REG

NO.
STOP
BITS

ECHO

1

PARITY
SELECTION

NUMBER OF
DATA BITS

CONTROL
REGISTERS

BAUD RATE SELECTION

PARITY
ENABLE

DTR
CONTROL

$80

RTS
CONTROL

AND
FORMAT
REGISTERS
COMPARE
DATA
REGISTER

COMPARE BITS (ADDRESS RECOGNITION)

IAMODE
IRQ VECTOR ADDRESS

IRQ SOURCE

TRANS
BRK

NOT USED

1·143

PARI
ADDR

INTERRUPT
VECTOR
REGISTER
T/RMODE

$OF

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

INTERRUPT STATUS REGISTER (ISR)

INTERRUPT VECTOR REGISTER (IVR)

The Interrupt Status Register (ISR) is a read-only register that
identifies the current status condition for each DACIA internal IRQ
source. Bits 6 through 0 of the ISR are set to a 1 whenever the
corresponding IRQ source condition has occurred in the DACIA.
Bit 7 identifies If any of the IRQ source status bits have been set
in the ISR.

The DACIA has two Interrupt Vector Registers which are write-only
registers. By storing the appropriate vector address number in bits
7 through 2 of the IVR, the DACIA will place the vector on the data
bus when requested by the lACK signal. In this mode, bits 1 and 0
identify the source of the IRQ.

7

6

5

ANY
BIT
SET

TOR
EMPTY

CTS
TRANS

4

3

2

1

FRM
DCD
DSR
PARITY
OVR
TRANS TRANS ERROR
BRK
CPR

0

Any Bit Set
Any bit (6 through 0) has been set to a 1
No bits have been set to a 1

Bit 6

Transmit Data Register Empty (TOR EMPTy)
Transmit Data Register has been transferred to
the shift register
New data has been written to the Transmit Data
Register

Bit 5
1
0

Bit 4
1
0

Bit 3
1
0

Frame Error, Overrun or Break (FRM, OVR,
BRK, CPR)
A framing error, receive overrun, or receive
break has occurred or, in Compare Mode
No error, overrun, break has occurred or RDR
has been read, or not in Compare Mode

6

5

4

2

3

IRQ VECTOR ADDRESS

1

0

IRQ SOURCE
TRANS
BRK

NOT USED

I ADDR
PARI

Interrupt Acknowledge Mode (IA Mode)
Bits 7-2

IRQ Vector Address

Bit 1
1

IRQ Source Channel
ACIA1 selected
ACIA2 selected

Bit 0
1

IRQ Source
Other IRQ (CTS, DCD, DSR, Parity, Break, OV)
Transmit or Receive IRQ

o
o

Transition On DSR Line (DSR TRANS)
A positive or negative transition has occurred on
DSR
No transition has occurred on DSR, or ISR has
been read

Bit 1

0

7

Transition On DCD Line (DCD TRANS)
A positive or negative transition has occurred on
DCD
No transition has occurred on DCD, or ISR has
been read

Parity Error
A parity error has occurred in received data
No parity error has occurred, or the Receive
Data Register (RDR) has been read

Bit 0
1

Writing a 1 to bit 1 of the IVR causes a continuous Break to be
transmitted by the ACIA associated with the register. Writing a 0 to
this bit allows normal transmission to resume. Writing a 1 to bit 0
of the IVR commands the value of the Parity bit to be sent to the
Parity Error bit (bit 2 of the ISR). Writing a 0 to this bit allows normal
Parity Error recognition to be in force. When an RES is received
by the DACIA, both ofthese bits are resetlo O. The bits formatfor
the IVR are as follows:

Transition On CTS Line (CTS TRANS)
A positive or negative transition has occurred on
CTS
No transition has occurred on CTS, or ISR has
been read

Bit 2
1
0

0

During the Transmit Receive mode, bits 7 through 2 are not used
and are treated as "don't care" bits. In this mode, bits 1 and 0
are used for Transmit Break and Parity/Address recognition.

RDR
FULL

Bit 7
1
0

0

Note: In order for the IVR Vector Address to be placed on the bus,
bit 6 of the Control/Format Register (CFR1, CFR2) must be a 1.

Transmit/Receive Mode (T/R Mode)
Bits 7·2

Not used (don't care)

Bit 1
1

Transmit Break (TRANS BRK)
Transmit continuous Break until disabled
Resume normal transmission

Bit 0
1

Parity/Address Recognition (PAR/ADDR)
Send value of parity to ISR bit 2 (Address
Recognition mode)
Return to normal Parity Error recognition mode

o

o

COMPARE DATA REGISTER
The Compare Data Register (CDR) is a write-only register which
can be accessed when CFR bit 6 O. By writing a value into the
CDR, the DACIA is put in the compare mode. In this mode, setting of the RDRF bit is inhibited and the FRM/OVR/BRKlCPR bit
(bit 1) of the ISR is set until a character is received which matches
the value in the CDR. The next character is then received and
the RDRF bit is set. The receiver will now operate normally until
the CDR is again loaded.

=

Receive Data Register Full (RDR FULL)
Shift register data has been transferred to
Receive Data Register
Receive Data Register has been read

1-144

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

STATUS REGISTER (SR)
The Status Register (SR) is a read-only register that provides I/O
status and error condition information. The SR is normally read
after an IRQ has occurred to determine the exact cause of the
interrupt condition.
7

5

6

4

3

2

1

0

FRAMING TRANS CTS
DCD
DSR
REC
DTR
RTS
ERROR UNDR STATUS STATUS STATUS BREAK STATUS STATUS

Bit 7

o
Bit 6
1

D

CTS Status
CTS line high
CTS line low

Bit 4
1

DCD Status
DCD line high
DCD line low

Bit 3
1

DSR Status
DSR line high
DSR line low

o

o
o

Bit 2
1
Bit 1
1

o

0

IVRICDR

Bit 6
1

o

4

NO.
STOP ECHO
BITS

1

Bits 4-3

4 3
o 0

o

Control Register (CFR Addressed with Bit 7 = 0)
5

6

NUMBER
OF DATA
BITS

1
1 0

The Control and Format Register (CFR) is a dual-function, writeonly register which allows control of word length, baud rate, control line outputs, parity, echo mode, and comparellVR access.
When the CFR is written to with bit 7 = 0, the CFR functions as
a Control Register. When the CFR is written to with bit 7 = 1, the
CFR operates as a Formal Register.

6

50
109.2
134.58
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
38400
External TxC and Rxe Clocks

7

o

CONTROL AND FORMAT REGISTER (CFR)

7

()
0 0
0 1
0
1 1
0 0
0 1
0
1
0 0
0 1
0
1 1
0 0
0 1
0

6 5
o 0

RTS Status
RTS line high
RTS line low

Bit 0
1

Baud Rate Selection
Baud Rate

1

Bits 6-5

DTR Status
DTR line high
DTR line low

o

Echo Selection (ECHO)
Echo activated
Echo deactivated

Format Register (CFR Addressed with Bit 7

REC Break
A Receive Break has occurred
No Receive Break occurred, or RDR, was read

o

Bit 4
1
0
Bits 3-0

Transmitter Underrun (TRANS UNDR)
Transmit shift register is empty and TDRE bits
in IER and ISR are set
A write to the TDR has occurred

Bit 5
1

Number of Stop Bits
Two stop bits
One stop bit

~ ~
0 0
0 0
0 0
0 0
0
0
0
0
0
0
0
0

Framing Error
A framing error occurred in receive data
No framing error occurred. or the RDR was
read

1

Bit 5
1
0

3

2

1

1

o

5

4

3

Number of Data Bits Per Channel
No. Bits
5

6
7
8
Parity Mode Selection
Selects
Odd Parity
Even Parity
Mark Parity
Space Parity

Bit 2
1

Parity Enable
Parity as specified by bits 4-3
No Parity

Bit 1
1

DTR Control
DTR high
DTR low

Bit 0
1

RTS Control
RTS high
RTS low

o

o

IVR/CDR
Access the IRQ Vector Register (IVR)
Access the Compare Data Register (CDR)

o

1-145

1

1)
0

-RTS

DTR
PARITY
PARITY
SELECTION ENABLE CONTROL CONTROL

0

BAUD RATE SELECTION

2

=

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

OPERATION

CONTINUOUS DATA TRANSMIT

The ten modes (or conditions) of operation of the DACIA are:

In the normal operating mode, the TDRE bit in the ISR signals
the MPU that the DACIA is ready to accept the next data word.
An IRQ occurs if the corresponding TDRE IRQ enable bit is set
in the lEA. The TDRE bit is set at the beginning of the start bit.
When the MPU writes a word to the TDR the TDRE bit is cleared.
In order to maintain continuous transmission the TDR must be
loaded before the stop bit(s) are ended. Figure 6 shows the relationship between IRQ and TxD for the Continuous Data Transmit
mode.

• Continuous Data Transmit
• Continuous Data Receive
• Transmit Underrun Condition
• Effects of CTS on Transmitter
• Effects of Overrun on Receive
•

Echo Mode Timing

• Framing Error
• Transmit Break Character
• Receive Break Character
• Automatic Address Mode

CHAR #n
/

CHAR #n + 1
I

~/

!

CHAR #n + 2

~/

~/

!

CHAR #n + 3
!

~

TX~ t r:F[~~ t I t ~~~(giJ t I t [BJBJ~~~ t I t [BJBJ~~~ t L
: START

STOP: START

U'

IRilJIJ

STOP: START

STOP: START

ILru

Lru

~ ~:,:~~:,~"

,ROC,.,OR /

,LESSOR

INTERRUPT
(TRANSMIT DATA
REGISTER EMPTY)

READS
ISR, CAUSES
IRQ TO CLEAR

Figure 6.

Continuous Data Transmit

a full data word. This occurs at about the 9/16 point through the
stop bit. The processor must read the RDR before the next stop
bit, or an overrun error occurs. Figure 7 shows the relationship
between IRQ and RxD for the continuous Data Receive mode.

Similar to the continuous data transmit mode, the normal receive
mode sets the RDRF bit in the ISR when the DACIA has received

CHAR #n

~/

I

l

INTERVAL OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED

CONTINUOUS DATA RECEIVE

/

STOP:

CHAR #n + 1

CHAR #n + 2

~/

I

~/

I

CHAR #n + 3
I

"

RX~ t ~~~~! I trorsJ~]g~J/I t [BJBJ~]~Ji]! I t [BJBJ~~~! L
START

STOP: START

STOP:

I

ILJ]

IR~rTT"-----ILJU'
IRQ PROCESSOR
INTERRUPT OCCURS
ABOUT 9/16 INTO
LAST STOP BIT
PARITY OVERRUN,
AND FRAMING ERROR
UPDATED ALSO

START

I

) \ ~
PROCESSOR READS
ISR, CAUSES
IRQ TO CLEAR

Figure 7.

START

Lill
!

PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL, OTHERWISE
OVERRUN OCCURS

Continuous Data Receive

1-146

STOP:

STOP:

L
!

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

TRANSMIT UNDERRUN CONDITION

flag is set. This condition persists until the TOR is loaded with a
new word. Figure 8 shows the relation between IRQ and TxO for
the Transmit Underrun Condition.

If .the MPU is unable to load the TOR before the last stop bit is
sent, the TxO line goes to the MARK condition and the underrun

, - - - - - - - - CHAR #n

IRQ

"
t [BOJBJ ~ ~ ~ t t ro-EI I~~[
1

----...,/

TtlI t [BJBJ ~ ]gij t

J
STOP

STOP START

CHAR #n + 2

I

"

/

TxD

CHAR #n + 1

CONTINUOUS "MARK"

I

J

/

J
STOP START

ISTART

I

1L-____-----,-____---:;l1LJlJ

t

/

PROCESSOR
INTERRUPT
FOR DATA
EMPTY

/

~WHEN PROCESSOR FINALLY LOADS

Figure 8.

Transmit Underrun Condition Relationship

EFFECTS OF CTS ON TRANSMITTER

the TORE bit in the ISR from becoming set. The word currently
in the shift register continues to be sent but any word in the TOR
is held until CTS goes low. At the high·ta-Iow transition the CTS bit
in the ISR~ain set. Figure 9 shows the relationship of IRQ,
TxO, and CTS for the effects of CTS on the transmitter.

The CTS control line controls the transmission of data or the handshaking of data to a "busy" device (such as a printer). When the
CTS line is low, the transmitter operates normally. Any transition
on this line sets the CTS bit in the ISA. A high condition inhibits

CHAR#n

CHAR #n + 1
I

TxD - - - - ' - I---~" /

B

]~EJ

t

J

t

J Bo J B, J

"

CONTINUOUS MARK

NEXT CHARACTER IS SENT IMMEDIATELY
UPON CTS GOING LOW IF PROCESSOR
HAS ALREADY LOADED NEW DATA,
OTHERWISE IT WAITS FOR NEW DATA.

~-'-JB-Jr-P"'J-"tJr.:-'-NE-XT-----.l-+J--,J

STOP START

N

STOP

un
CTS _ _ _ _

NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY

PROCESSOR READS
ISR, CLEARS IRQ

UNDERRUN BIT
SET

LJlJrrr---

CHARACTER
IS NOT SENT
TORE IS NOT SET

t

J Bo J B, J

I~

START
MPU
CLEARS
IRQ AGAIN

WHEN PROCESSOR
FINALLY LOADS
NEW DATA,
TRANSMISSION STARTS

I :-_____--Irl--m~MEDIATELY AND

\

CLEAR-TO-SEND
_______

~~~~~

i"
I iRQ

r-----l.r---------------,
'--CT-S
MPU
CLEARS

I

~

IRQ

Figure 9.

IRQ

Effects of CTS on Transmitter

1-147

CTS

INTERRUPT OCCURS,
INDICATING TRANSMIT
DATA REGISTER EMPTY

II

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

EFFECTS OF OVERRUN ON RECEIVER

RDR contains the last word not read by the MPU and all following data is lost. The receiver will return to normal operation when
the RDR is read. Figure 10 shows the relation of IRQ and RxD for
the effects of overrun on the receiver.

If the processor does not read the RDR before the stop bit of the
next word, an overrun error occurs, the overrun bit is set in the
ISR, and the new data word is not transferred to the RDA. The

CHAR Un + 1

CHAR Un

~/

!

"-../

JIlI S~ART
J [B:JSJ~I~E!
I

RxD
STOP
IRQ

STOP

--un

/

1

CHAR #n + 2

I

"'/

STopi

1

STOP

J1l ~ ra:-rB~[ ]09£] t

mal transmit mode if TORE occurs (indicating end of data) an
underflow flag would be set and continuous Mark transmitted. If
Echo is initiated, the underflow flag will not be set at end of data
and continuous Mark will not be transmitted. Figure 11 shows the
relationship of RxD and TxD for Echo Mode.

START
I

CHAR #n + 2
IRQ.
CHAR #n + 1
IS LOST

+ [S;[~:I ~

STOP

[B;E] t

END OF
DATA

1-1
/ _ _

\ \ \ \ \ \ ~~O:6~N~g~;:~~:
t rs:E==[B;E] t 1t [BOF]-=~ t 1_====

\1 \ \ \

W

MPU READS
ISR
CLEARS IRQ

Effects of Overrun on Receiver

In the Echo Mode, the TxD line re-transmits the data received on
the RxD line, delayed by 1/2 of a bit time. An internal underrun
mode must occur before Echo Mode will start transmitting. In nor-

TxD

n'------;:-___

t'

MPU DOES
NOT READ
RDR.OVERRUN
BIT SET

ECHO MODE TIMING

RxD

I

ISTOP I START

START

!
Figure 10.

START

""/

t [B:JSJ~~~/I t rqeJ~~~/1 t [B~FI~ ~

START

PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL

STOP

CHAR Un + 3

I

STOP START

\ \

STOP~

STOP START

IF ECHO MODE,
NO UNDERFLOW,
THEREFORE NO
CONTINUOUS MARK

Figure 11.

Echo Mode Timing

1-148

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

FRAMING ERROR

quent data words are tested separately, so the status bit always
reflects the last data word received. Figure 12 shows the relationship of IRQ and RxD when a framing error occurs.

Framing error is caused by the absence of stop bites) on received
data. The framing error bit is set when the RDRF bit is set. Subse-

,...--------RxD
(EXPECTED)

RxD
(ACTUAL)

IPROCESSOR

NOTES: 1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.

INTERRUPT,
FRAMING
ERROR
BIT SET

2. IF NEXT DATA WORD IS OK,
FRAMING ERROR IS CLEARED.

Figure 12. Framing Error

TRANSMIT BREAK CHARACTER

$00 is stored in the IER at which time a stop bit is sent and
transmission may resume. At least one full word time of Break
will be sent regardless of the length of time between starting and
st0.Ee!.ng the Break character. Figure 13 shows the relationship
of IRQ and TxD for a Transmit Break character.

A Break may be transmitted by storing a value of $00 in the lEA.
After storing zero in the IER the Break is transmitted immediately.
Care should be exercised so that a character in transmission is
not disturbed inadvertently. The Break level lasts until other than

TxD

t !-4....L.--L--..J==~ t It,

STOP START

STOP

Bo , B, ' __ I BN I P d l

STOP f

START

/

"'-/

I

STOP START

~=]~Ji] t I t CE
I

TOP START

MT---------------+---------------------~

IRQ

I

PERIOD DURING
WHICH PROCESSOR

1 + - - - - - - + 1 - SELECTS
CONTINUOUS
"BREAK" MODE

NORMAL
INTERRUPT

POINTATWH~

PROCESSOR
SELECTS
NORMAL
TRANSMIT
MODE

Figure 13. Transmit Break Character

1-149

PROCESOR
INTERRUPT
TO LOAD
TRANSMIT
DATA

1

Dual Asynchronous Communications Interface Adapter (DACIA)

R68C552

Table 4.

3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

CClntrClI
Register
Bits
2
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
1
1
1

0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Divisor Selected
For The
Internal Counter
73.728
33,538
27,408
24,576
12,288
6,144
3,072
2,048
1,536
1,024
768
512
384
192
96
16

Divisor Selection

Baud Rate Generated
With 3.6864 MHz
Crystal
(3.6864 x 10')/73,728 = 50
(3.6864 x 10')/33,538 = 109.92
(3.6864 x 10')/27.408 = 134.58
(3.6864 x 10')/24,576 = 150
(3.6864 x 10')/12,288 = 300
(3.6864 x 10')/6,144 = 600
(3.6864 x 10')/3,072 = 1,200
(3.6864 x 10')/2,048 = 1,800
(3.6864 x 10')/1,536 = 2,400
(3.6864 x 10')/1,024 = 3,600
(3.6864 x 10')1768 = 4,800
(3.6864 x 10')/512 = 7,200
(3.6864 x 10')/384 = 9,600
(3.6864 x 10')/192 = 19,200
(3.6864 x 10')/96 = 38,400
TxC/16

=

Baud Rate or RxC/16

Baud Rate Generated
With a Crystal
of Frequency (f)
1173.728
1/33.538
1127,408
1/24,576
1112,288
1/6.144
1/3,072
112,048
1/1,536
1/1,024
1/768
1/512
1/384
1/192
1/96

=

Baud Rate

RxC

INTERNAL
+ 18
RxS
LATCH

)~~-D-AT-A------------------~~--------CD

Figure 15.

DACIA External Clock Timing -

TRANSFER DATA TO SHIFT REGISTER

Receive Data

T~~~
~~~RNAL

TxD

----"'\~

)}

Figure 16.

TMN~T

DACIA External Clock Timing -

1-150

~,..----

MTA

Transmit Data

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

RECEIVE BREAK CHARACTER

remains in this state until a stop bit is received. At this time the
next character is to be received normally. Figure 14 shows the
relationship of IRQ and RxD for a Receive Break Character.

In the event thai a Break character is received by the receiver,
the Break bit is sel. The receiver does not set the RDRF bit and

------~"

RxD

IRQ

]~I~~~

CONTINUOUS "BREAK"

It,
U

B o , B'lnI BN , P 1/ 1
STOP I START
STOP I
(

RECEIVER
DATA REGISTER
FULL

I START

I"

PROCESSOR
INTERRUPT

STOP

IBol B,I

I START

rr---

L_-LI

r ~

tI
PROCESSOR
INTERRUPT
FOR

I-'-,----L...~m t ~EI~~;: I t

l

i rrJ
LJJ

----i

,,/~----

STOP /

~

NO MORE
INTERRUPTS

NO INTERRUPT
SINCE RECEIVER.
DISABLED UNTIL
FIRST STOP BIT

NORMAL
RECEIVER
INTERRUPT

WITH BREAK AND FRAMING ERROR BIT SET.
EVEN PARITY CHECK WILL ALSO GIVE A PARITY
ERROR BECAUSE ALL ZEROS (CONTINUOUS
BREAK) REPRESENT EVEN PARITY.

Figure 14.

Receive Break Character

AUTOMATIC ADDRESS RECOGNITION

characters). When all data has been received by the slave, it's
CPU must again write the slave address into the DACIA Compare
Register which automatically puts it back into the Compare Mode,
waiting for another address character.

The DACIA offers a unique solution to the standard problem
associated with multi-drop environment UARTs and communication interface controllers. In the standard configuration used by
other devices, the slave CPU must be constantly interrupted to
analyze incoming characters on the communications net to deter·
mine if an address word is present and if so, does that address
match the address assigned to the slave UART. This CPU inter·
rupt scheme can become intolerable in very large multi-drop net·
works because every slave on the communications net must
"wake-up" it's CPU for every character sent down the network
by the master. The end results is that the CPUs on the communications net are constantly being interrupted for the mundane
task of address recognition.

GENERATION OF NON·STANDARD BAUD RATES

Divisors
The internal counter/divider circuit selects the appropriate divisor
for the crystal frequency by means of bits 0-3 of the CFR Control
Register, as shown in Table 4.

Generating Other Baud Rates
By using a different crystal, other baud rates may be generated.

To avoid this constant CPU interrupt problem, the DACIA has
been designed to do address comparison and recognition internally without the need for CPU intervention. Therefore, the slave
CPU is not interrupted until the DACIA has determined that the
character sent over the communications net by the master was
an address and the address matched the address stored in the
DACIA Compare Register. At this point the DACIA interrupts the
CPU, goes out of Compare Mode, and receives the string of
characters being transmitted by the master, (i.e., the data

These can be determined by:
Baud Rate = Crystal Frequency
Divisor
Furthermore, it is possible to drive the DACIA with an off-chip
oscillator to achieve other baud rates. In this case, XTALI (pin 3)
must be the clock input and XTALO (pin 4) must be a nonconnecl.

1-151

II

R68C552

Dual Asynchronous Communications Interface Adapter (DACIA)

~G}
RSO -RS2

f--0--

X

>-

,w

R

\ r-Gr

S
OA TA

-0

\

--...

/
~

/
\

(DO -07)

If

\

OTACK

G)

/
-..

0

DACIA Read Cycle Timing

G)
RSO-RS2

RiW

cs

-0-

X

K

\

/
\ rG}

-G)---2 (IN).

R6512 FEATURES

VSS

oBE

NMI

N.C.

• 64K addressable bytes of memory (AO-AI5)

SYNC

R/W

• IRQ interrupt

VCC

DO
01
02
03
04
05
06
07

AO
Al
A2
A3
A4
A5
A6
A7
AS
A9
Al0
All

• NMI interrupt
• RDY signal
• 8-bit bidirectional data bus
• SYNC signal
• Two phase clock input
• Data Bus Enable
• 40-pin DIP

A15
A14
A13
A12
VSS

*Pins 37 and 39 are connected internally

2-6

R6500 Microprocessors (CPU)

R650X, R651X

vss

R6513 FEATURES

1/>, (IN)

Il'fQ

• 4K addressable bytes of memory (AO-A11)
• Two phase clock input

NMI

vee
AO
Al
A2
A3
A4
A5
A6
A7
AS

• IRQ interrupt
• NMI interrupt
• 8-bit bidirectional data bus
• 28-pin DIP

vss
1/>, (IN)
IRQ

vee

R6514 FEATURES

AO
Al
A2
A3
A4
A5
A6
A7
AS
A9

• 8K addressable bytes of memory (AO-A12)
• Two phase clock input
• iRa interrupt
• 8-bit bidirectional data bus

vss
ROY
1/>, (IN)

rna

R6515 FEATURES
•
•
•
•
•

vee

4K addressable bytes of memory (AO-A 11 )
Two phase clock input
IRQ interrupt
RDY signal
8-bit bidirectional data bus

AO
Al
A2
A3
A4
A5
A6
A7
AS

2-7

RES
1/>2 (IN)
R/W
DO
01
02
03
04
06
06
07
All
Al0
A9

RES
1/>2 (IN)
Rffl
DO
01
02
03
04
05
06
07
A12
All
Al0

RES
1/>2 (IN)
R/W
DO
01
02
03
04
05
06
07
All

Al0
A9

R6S00 Microprocessors (CPU)

R650X, R651X
FUNCTIONAL DESCRIPTION

ARITHMETIC AND LOGIC UNIT (ALU)

The Internal organization of all R6500 CPUs is identical except
for some variations In clock interface, the number of address
output lines, and some unique Input/output lines between
versions.

All arithmetic and logic operations take place In the AlU including
Incrementing and decrementing Internal registers (except the program counter). The AlU has no Internal memory and Is used only to
perform logical and transient numerical operations.

CLOCK GENERATOR

ACCUMULATOR

The clock generator develops all internal clock signals, and (where
applicable) external clock signals, associated with the device. It is
the clock generator that drives the timing control unit and the external timing for slave mode operations.

The accumulator is a general purpose 8-blt register that stores
the results of most arithmetic and logic operations, and In addition, the accumulator usually contains one of the two data words
used in these operations.

TIMING CONTROL

INDEX REGISTERS

The timing control unit keeps track of the Instruction cycle being
monitored. The unit is set to zero each time an instruction fetch is
executed and is advanced at the beginning of each phase one
clock pulse for as many cycles as Is required to complete the
Instruction. Each data transfer which takes place between the regIsters depends upon deceding the centents of both the instruction
register and the timing control unit.

There are two 8-bit Index registers (X and V), which may be used
to count program steps or to provide an index value to be used In
generating an effective address.
When executing an instruction which specifies indexed addressing,
the CPU fetches the op code and the base address, and modifies
the address by adding the index register to it prior to performing the
desired operation. Pre- or post-Indexing of indirect addresses Is
possible (see addressing modes).

PROGRAM COUNTER
The 16-bit program counter provides the addresses which step
the microprocessor through sequential instructions In a program.

STACK POINTER

Each time the microprocessor fetches an instruction from program memory, the lower byte of the program counter (PCl) is
placed on the low-order bits of the address bus and the higher
byte of the program counter (PCH) Is placed on the high-order 8
bits. The ceunter is incremented each time an instruction or data
Is fetched from program memory.

The stack pointer Is an 8-bit register used to centrol the addressing
of the variable-length stack on page one. The stack pOinter is automatically Incremented and decremented under control of the microprocessor to perform stack manipulations under direction of either
the program or Interrupts (NMI) and IRQ). The stack allows simple
implementation of nested subroutines and multiple level Interrupts.
The stack pOinter should be initialized before any interrupts or stack
operations occur.

INSTRUCTION REGISTER AND DECODE
PROCESSOR STATUS REGISTER

Instructions fetched from memory are gated onto the Internal
data bus. These instructions are latched Into the instuction register, then decoded, along with timing and interrupt signals. to generate control signals for the various registers.

The 8-blt processor status register contains seven status flags.
Some of the flags are controlled by the program, others may be
centrolled both by the program and the CPU.

2-8

R650X, R651X

R6500 Microprocessors (CPU)

. - REGISTER SECTION

AD

A1

A2

A3

A.

Y

INDEX
REGISTER

x

...
...
...
... ... ...
...

AS

A6

A7

ADDRESS

eus2
AB

A.

A10

A11

A12

A13

A1'

A15

....
....
....
....

J;

~

~Ft

C-

z

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DECODE

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REGISTER

t ft.

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LEGEND

03

D.
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= 1 BIT LINE

),."
BUS

07

NOTE
1. CLOCK GENERATOR IS NOT INCLUDED ON R6512, R6513, R6514 AND R6515.
2. ADDRESSING CAPABILITY AND CONTROL OPTIONS VARY WITH EACH OF
THE CPUs.
3. R6502, R6503, R6504, R650S, R6506 AND R6507.
4. R6512, R6513, R6514 AND R6515.
5. R6512 ONLY.
6. R6502 ONLY.

R650X and R651X Internal Architecture

2-9

(ouT)e

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2-13

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SueTRACT

A

ACCUMULATOR

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A"2 (OUT)
XTAL
(1 MHz - 3 MHz)·

·CRYSTAL: CTS KNIGHTS MP SERIES. OR EQUIVALENT

2·16

R650X, R651X

R6500 Microprocessors (CPU)

ABSOLUTE MAXIMUM RATINGS·
Parameter

Symbol

Value

Unit
Vde
Vde

Supply Voltage

Vee

-0.3 to +7.0

Input Voltage

VIN

-0.3 to +7.0

Operating Temperature Range
Commercial
Industrial

TA

Storage Temperature

TSTG

"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

°C
-40 to +85
-55 to + 150

°C

fJ

OPERATING CONDITIONS
Parameter

Symbol

Supply Voltage

Vee

Temperature Range
Commercial
Industrial

TA

DC CHARACTERISTICS
= 5.0V ±5%, Vss = 0, TA =

(Vee

Value
5V ±5%
O°C to + 70°C
- 40°C to + 85°C

TL to T H, unless otherwise noted)

Parameter

Symbol

Input High Voltage
Logic, 1i'l0 (IN)
Ii'lI (IN), 1i'l2 (IN)

VIH

Input Low Voltage
Logic, 160 (IN)
Ii'lI (IN), 1i'l2 (IN)

VIL

Input Leakage Current
Logic (Excl. ROY, S.O.)
Ii'lI (IN), 1i'l2 (IN)
1i'l0 (IN)

liN

Input Leakage Current for Three State Off
00·07

ITSI

Output High Voltage
SYNC, 00·07, AO·AI5, RIW, Ii'lI (OUT), 1i'l2 (OUT)

V OH

Output Low Voltage
SYNC, 00·07, AO·AI5, RIW, Ii'lI (OUT), 1i'l2 (OUT)

VOL

Power Dissipation
1 and 2 MHz
3 MHz

Po

Capacitance
Logic
00-07
AO-AI5, RIW, SYNC
1i'l0 (IN)
Ii'lI (IN)
1i'l2 (IN)

C
CIN

Min.

Typ.S

Max.

Unit'

2.0
Vee -0.3

-

Vee
Vee + 0.25

-0.3
-0.3

-

0.8
0.4

-

V

-

-

-

-

-

2.5
100
10

-

-

10

-

-

+2.4

p.A

VIN = OV to 5.25V
Vee = OV

p.A

VIN = O.4V to 2.4V
Vee = 5.25V

V

ILOAD = -100 p.A
Vee = 4.75V

V

ILOAD = 1.6 mA
Vee = 4.75V

+0.4

COUT
CIi'lO(IN)
CIi'lI
CIi'l2

Test Conditions

v

mW

-

450
500

700
800

-

-

10
15
12
15
50
80

pF

-

-

-

30
50

Notes:
1. All units are direct current (de) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. IRQ and NMI require 3K pull-up resistor.
4. Ii'lI (IN) and 1i'l2 (IN) apply to R6512, 13, 14, and 15; 1i'l0 (IN) applies to R6502, 03, 04, OS, 06 and 07.
5. Typical values shown for Vee = 5.0V and TA = 25°C.

2-17

Vee = 5.0V
VIN = OV
f = 1 MHz
TA = 25°C

R6501Q • R6511Q
R6500 Microcomputer System

'1'

R6501Q AND R6511Q
ONE-CHIP MICROPROCESSOR

Rockwell
INTRODUCTION

• 192-byle static RAM

The Rockwell R6501Q and R6511Q are extended, high performance 8-bit NMOS-3, single chip microprocessors, and are compatible with all members of the R6500 family.

• 32 bidirectional, TIL-compatible I/O lines (four ports)

The devices contain an enhanced R6502 CPU, an internal clock
oscillator, 192 byles of Random Access Memory, and versatile
interface circuitry. The interface circuitry includes two 16-bit programmable timer/counters, 32 bidirectional input/output lines
(including four edge sensitive lines and input latching on one
8-bit port), a full-duplex serial I/O channel, ten interrupts and
bus expandability. A full 16-bit address bus and 8-bit data bus
provide accessing to 65K byles of external memory.

• Two 16-bit programmable counter/timers, with 3 latches

The devices come in a 64-pin Quad Inline package (QUIP).
The devices may be used as a CPU-RAM-I/O counter device
in multlchlp systems or as an emulator for the R6500/11 family
of microcomputers. They provide all R6500/11 interface lines,
plus the address bus, data bus and control lines to interface with
external memory.

• One 8-bit port may be tri-stated under software control
• One 8-bit port may have latched inputs under software control
-Pulse width measurement
-Pulse generation (1 symmetrical, 1 asymmetrical)
-Interval timer
-Event counter
-Retriggerable interval timer
• Serial Port - Full Duplex, Buffered UART
-Receiver Wake Up and Transmitter End of Transmission
Features
-Programmable Standard Asynchronous Baud Rates from
50 to 125K bits/sec at 2 MHz
Satisfies SMPTE 422 Broadcast Standard (8 Data, Parity,
1 Stop) at 38.4K bits/sec
-Programmable 5-8 bit Character Lengths, with or without
parity

SYSTEMS DEVELOPMENT
Rockwell supports development of the devices with the Rockwell
Design Center System and the R65001* Pe~sonality Set: Complete in-circuit emulation with the Personality Set allows total
systems test and evaluation.
This data sheet is for the reader familiar with the R6502 CPU
hardware and programming capabilities. For additional information see the R6501Q Product Description, (Document Order
Number 2145) or the R6511Q Product Description, (Document
Order Number 2133).

-Receiver Error Detection for Framing, Parity, and Overrun
-SynChronous Shift Register alternate mode (250KC at
2 MHz)
• Ten interrupts
-Four edge-sensitive lines; two positive, two negative
-Two counter underflows
-Serial data receiver buffer full
-Serial data transmitter buffer empty
-Non-maskable

ORDERING INFORMATION
Part
Number
R6501Q
R6501AQ
R6511Q
R6511AQ

Package
Type
Plastic
Plastic
Plastic
Plastic

(QUIP)
(QUIP)
(QUIP)
(QUIP)

Frequency
Option
1 MHz
2 MHz
1 MHz
2 MHz

Temp.
Range
O·C
O·C
O·C
O·C

to
to
to
to

70·C
70·C
70·C
70·C

-Reset
• Full data and address pins for 65K byles of external memory
• Flexible clock circuitry
-2 MHz or 1 MHz internal operation
-Internal clock with external XTAL at four times internal frequency (R6501 Q) or two times internal frequency (R6511 Q)
-External clock input divided by one or four (R6501 Q) or one
or two (R6511Q)

FEATURES
• Enhanced R6502 CPU
-Four new bit manipulation instructions
Set Memory Bit (5MB)
Reset Memory Bit (RMB)
Branch on Bit Set (BBS)
Branch on Bit Reset (BBR)
-Decimal and binary arithmetic modes
-13 Addressing modes
-True indexing

• 68% of the instructions have execution times less than 2 ,.s
at 2 MHz
• NMOS-3 silicon gate, depletion load technology
• Single + 5V power supply
• 12 mW stand-by power for 32 byles of the 192-byle RAM
• 64-pin QUIP
• R6501Q has pullup resistors on PA, PB, and PC
R6511 Q has no pullup resistors

Document No. 29000084
2-18

Data Sheet Order No. 084
Rev. 3, March 1984

One-Chip Microprocessor

R6501Q and R6511Q
FUNCTIONAL DESCRIPTION

R65010 has pullup resistors on PA, PB and PC. The R65110
has no pull up resistors. Port D may be used as all inputs or all
outputs. It has active pull-ups.

CENTRAL PROCESSING UNIT (CPU)
The internal CPU of the device is a standard R6502 configuration
with the standard R6502 instructions plus 4 new bit manipulation
instructions. These new bit manipulator instructions form an
enhanced R6502 instruction set and improve memory utilization
efficiency and performance.

Port A (PA) can be programmed as a standard parallel 8-bit I/O
port or under software control as serial I/O lines, counter I/O
lines, positive (2) and negative (2) edge detects, or an input data
strobe for the Port B (PB) input latch.

Set Memory Bit (SMB #,ADDR.)

Port B (PB) can be programmed as an I/O port with latched input
enabled or disabled.

This instruction sets to "1" one bit of the 8-bit data field specified
by the zero page address (memory or I/O port). The first byte
of the instruction specifies the 8MB operation and which one
of 8 bits to be set. The second byte of the instruction designates
the address (0-225) of the byte or I/O port to be operated upon.

Port C (PC) can be programmed as an I/O port, as an abbreviated bus, as a multiplexed bus, or as part of the full address
mode. In the full address mode pins PC6 and PC7 serve as
addresses A 13 and A 14, respectively; PCO-PC5 are I/O pins.
Port 0 (PO) functions as an I/O port, an 8-bit tri-state data bus,
or as a multiplexed address/data bus.

Reset Memory Bit (RMB #,ADDR.)
This instruction is the same operation and format as the 8MB
instruction except a reset to "0" of the bit results.

Serial Input/Output Channel -

Branch on Bit Set Relative (BBS #,ADDR_,DEST)

UART

The devices provide a full duplex serial I/O channel with programmable bit rates covering all standard baud rates from 50 to
125K bits/sec including the 8MPTE 422 standard at 38.4K bits/
sec. Character lengths of 5 to 8 bits, with or without parity are
programmable. A full complement of flags provides for Receiver
Wake Up; Receiver Buffer Full; Receiver Error Conditions detecting Framing, Parity, and Overrun errors; Transmitter End of
Transmission and Transmitter Buffer Empty. In addition, a synchronous shift register mode to 250 KC at 2 MHz is available.

This instruction tests one of 8 bits designated by a 3-bit immediate field within the first byte of the instruction. The second byte
is used to deSignate the location of the byte or I/O port to be
tested within the zero page address range. The third byte of the
instruction is used to specify the 8-bit relative address to which
the instruction branches if the bit tested is a "1". If the bit tested
is not set, the next sequential instruction is executed.

Branch on Bit Reset Relative (BBR #,ADDR.,DEST)
Wake-Up Feature

This instruction is the same operation and format as the BB8
instruction except that a branch takes place if the bit tested is
a "0".

In a multi-distributed microcomputer application, a destination
address is usually included at the beginning of the message.
The Wake-Up Feature allows non-selected CPUs to ignore the
remainder of the message until the beginning of the next
message by setting the Wake-Up bit.

Random Access Memory (RAM)
The RAM consists of 192 by 8 bits of read/write memory with
an assigned page zero address of 0040 through OOFF. The
devices provide a separate power pin (V AA) which may be used
for standby power. In the event of the loss of Vee power, the
lowest 32 bytes of RAM data will be retained if standby power
is supplied to the VAA pin.

Counter/Latch Logic
The devices contain two 16-bit counters (Counter A and
Counter B) and three 16-bit latches associated with the counters.
Counter A has one 16-bit latch and Counter B has two 16-bit
latches. Each counter can be independently programmed to
operate in one of four modes:

Clock Oscillator
The clock oscillator provides the basic timing signals. A reference
frequency can be generated with the on board oscillator (with
external crystal) or an external reference source can be driven
into the XTLI pin. If the XTLO pin is left floating, the reference
frequency is internally divided by four (R6501 0) or two (R6511 0)
to obtain the internal clock. The internal clock is then available
as an output at the 02 pin. The XTLI pin may be used as an
undivided clock input by connecting XTLO to Vs s, in which
case the internal division circuitry is bypassed and the device
operates at the reference frequency.

Counter A

Counter B

• Pulse width
measurement
• Pulse Generation
• Interval Timer
• Event Counter

• Retriggerable Interval
Counter
• Assymmetrical Pulse
Generation
• Interval Timer
• Event Counter

Parallel Input/Output Ports

Mode Control Register (MCR)

The devices have 32 I/O lines grouped into four 8-bit ports (PA,
PB, PC, PD). Ports A through C may be' used either for input
or output individually, or in groups of any combination. The

The Mode Control Register contains control bits for the multifunction 110 ports and mode select bits for Counter A and
Counter B.
2-19

fJ

R6501Q and R6511Q

One-Chip Microprocessor

Ports C and 0 Operation Modes
There are four operating modes available in ports C and D, software programmable via the Mode Control Register. The full
address mode allows access to a full 65K bytes of external
storage. In this mode PCS and PC7 are automaticallyu used for
A13 and A14. In the Input/Output mode the four ports are all
used for I/O. In the abbreviated and multiplexed modes some
port pins set up for addressing 64 or 16,384 bytes of external
memory.

PAO-PA7
(PAD, PAl,
PA2, PA3

EDGE
DETECTS)

DS(PAO
DATA

STROBE)"

Interrupt Flag Register (IFR) and
Interrupt Enable Register (IER)

PCD,PC7J
(A13, A14
Full
address
mode)*

The devices include an Interrupt Flat Register and an Interrupt
Enable Register which flags and controls I/O and counter status.

POQ,PO?!

(DATAJADDR
BUS
A4-A11)

CA (PA')'
CB (PASI'

R6501 Q or R6511 Q
FFFE

IRQ

FFFC

RES

FFFA

NMI

SO (PA6)"
SIIPA?)'

• MULTIPLEXED FUNCTIONS PINS (Software Selectable)

BLOCK DIAGRAM
INTERNAL REGISTERS
READ

I!
I
I
I
I
I
I
I
I
I
I
I
I

USER PROGRAM

I
I

OOFF
INTERNAL
RAM (192)
0040

RESERVED

I
I
I
I
I
I
I
I
I
I

I

WRITE

--

-Upper Latch S* #
Upper Lalch B
Lower Latch B

Lower Cou nter B
Upper Counter B
Lower Counter 8 #

--

--

ADDRESS
001F
001E
0010
001C

Lower Counter A
Upper Counter A
Lower Counter A #

Upper Latch A" #
Upper Latch A
Lower Latch A

001B
001A
0019
0018

S9r Ree Data Reg
Senal Status Reg
Senal Control Reg
Mode Control Reg

Ser Trans Data Reg
Senal Status Reg (1)
Senal Control Reg
Mode Control Reg

0017
0016
0015
0014

--

--

Interrupt Enable Reg
Interrupt Flag Reg
Read FF

Interrupt Enable Reg

--

Clr Inlerrupl Flag (2)

0013
0012
0011
0010
OOOF

USER AVAILABLE
0007

(Reserved for 1/0 ports E, F, & G when
emulating the R6500/12)

0006

0004

001F

0003
110 & REGISTERS

1/0
1/0
1/0
1/0

PORT D
PORTC
PORT B
PORT A
0000

0000

MEMORY MAP

"-LOAD & START COUNTER
# CLEAR FLAG •
(1) BITS 4 & 5 ONLY
(2) BITS 0-3 ONLY

2-20

One-Chip Microprocessor

R6501Q and R6511Q

KEY REGISTER SUMMARY
7

0

I

I ACCUMULATOR

7

0

i

0

I

I

I

"

j

7

0

I

'CH

INDEX REGISTER Y
INDEX REGISTER X

I PROQRAM COUNTER

POL.

7

0

Sp
7

CARRY (0)

PC

o -:learry CI •• r

I STACK POINTER

' - - - - ZERO (ZI

0

INlvl I. I D I l i z Ic I 'ROCUSORSTATU,REG

CD

1:: Carry S.t

,

2
CS1
CS2
RSO RS1
RS2
RS3

BUFFERS
(PA)

I-----+-e------ CBI
L~:!Lj--....---- CB2

TIMER I

BUFFERS
(PB)

Figure 4. R6522 VIA Block Diagram

2-39

PORTB

2

Versatile Interface Adapter (VIA)

R6522
HANDSHAKE CONTROL OF DATA TRANSFERS

data, causing generation of a "Data Taken" signal. The peripheral device responds by making new data available. This process
continues until the data transfer is complete.

The R65?2 !lllows positive control of data transfers between the
,system processor and peripheral devices through the operation
of "handshake" lines. Port A lines (CA1, CA2) handshake data
on both a reEld and a write operation while the Port B lines (CB1,
CB2) handshake on a write operation only.

Read

'.':,'

In the R6522, automatic "Read" 'Handshaking is possible on the
Peripheral A port only. The CA1 interrupt input pin accepts the
"Data Ready" signal and CA2 gen'erates the "Data Taken" signal. The "Data Ready" signal will set an internal flag which may
interrupt the processor or which may be polled under program
control. The "Data Taken" signal can either be a pulse or a level
which is set low by the system processor and is cleared by the
"Data Ready" signal. These options are shown in Figure 9 which
illustrates the normal Read Handshake sequence.

Hand~hake

Positive control of data transfers from peripheral devices into,the
system processor can be accomplished very effectively using
Read Handshaking. In this case, the peripheral device must generate the equivalent of a "Data Ready" signal to the processor
signifying that valid data is present on the peripheral port. This
signal normally interrupts the processor, which then reads the

REG 1-0RAIIRA

REG O-ORB/IRB

1 1'1'1'1'1' '1 1
7

0

~PBa

PAa

PBl

PB'
PB'
PB'
PBS

PAl

OUTPUT REGISTER
"B" (ORB) OR
INPUT REGISTER
"B" (IRB)

'------PA'
' -_ _ _ _ _ PAS

PB6

L--------------PA'

L.._ _ _ _ _ _ _ _ _ PA7

PB'

~N

PIN
DATA DIRECTION

WRITE

DATA DIRECTION
SELI!CTION

READ

SELECTION
DDRB = "1" (DLlTPUn

MPU WRITES OUTPUT lEvel
(ORB)

OORB" "0" (INPUT) •
(INPUT LATCHING DISABLED)

OUTPUT REGISTER
"A" (ORA) OR
INPUT REGISTER
"A" (IRA)

PA'
'-----PA'

MPU WRITES INTO ORB, BUT
NO EFFECT ON PIN LEVEL,
UNTIL OORB CHANGeD

DORa .. "0" (INPUT)
(INPUT LATCHING ENABLED)

DORA .. ''1'' (OUTPUT)
(INPUT LATCHING DISABLED)

MPU READS OUTPUT REGISTER
BIT IN ORB PIN LEVEL HAS NO
A"I!;CT

MPU WRITES OUTPUT LEVEL
(ORA)

DORA '" "1" (OUTPUT)
(INPUT LATCHING ENABLED)

MPU READS INPUT LEVEL ON PB
PIN

DORA .. "0" (INPUT)
(INPUT LATCHING DISABLED)

MPUREADSIRSBIT, WHICH ISTHE
LEVEL OF THE PB PIN AT THE TIM!:
OF THE LAST CS1 ACTIVE
TRANSITION

tl

READ

WRITE

MPU READS LEVEL ON PA PIN
MPU READS IRA SIT WHICH IS THE
LEVELOFTHEPA PINATTHETlME
OF THE LAST CM ACTIVE
TRANsmON

MPU WRITES INTO ORA, BUT
NO EFFECT ON PIN LEVEL,
UNTIL DORA CHANGED

DORA = "0" (lNPUn
(INPUT LATCHING ENABLED)

MPU READS LEVEL ON PA PIN

MPU READS IAABfT WHICH IS THE
LEVELOFTHE PA PIN ATTHE TIME
OF Tl-IE LAST CA1 ACTIVE
TRANSITION

Figure 5. Output Register B (ORB), Input Register B (IRB)
Figure 6. Output Register A (ORA), Input Register A (IRA)
REG 2-DDRB

REG3-DDRA

1,1 1+1+1+1
6

~

CPBa

PAa

PBl

PAl

PB'
PB'

' - - - - - - - PB4/PA4

PA'

DATA DIRECTION
REGISTER "B" (DDRB)

PA'
PA'

' -_ _ _ _ _ _ PBS/PAS

PA'

' - - -_ _ _ _ _ PB6/PAS

PA6

' -_ _ _ _ _ _ _ _ Pa7/PA7

"0"
"1"

DATA DIRECTION
REGISTER "A" (DORA)

PA7

ASSOCIATED PB PIN IS AN INPUT
(HIGH IMPEDANCE)
ASSOCIATED PB PIN IS AN OUTPUT
WHOSE LEVEL IS DETERMINED BY
OAB REGISTER BIT

"0"
"1"

Figure 7. Data Direction Register B (DDRB)

ASSOCIATED PA PIN IS AN INPUT
(HIGH IMPEDANCE)
ASSOCIATED PA PIN IS AN OUTPUT
WHOSE LEVEL IS DHEAMINED BY
ORA REGISTER BIT

Figure 8. Data Direction Register A (DORA)

2-40

R6522

Versatile Interface Adapter (VIA)

~~~~

2 ~1~11JL..rL...JL
READY

~~

\

~

1

IRQ OUTPUT

"DATA TAKEN"
PULSE MODE
(CA2)

I I !I-- - -

.

1/

rl

READ IRA OPERATION

~~~~~:t::~~DE

I I

I

I

~

:

,'-_ __

Ir----

nIl

fJ

I
II
~ -------

---------1.11

Figure 9. Read Handshake Timing (Port A Only)

Write Handshake
The sequence of operations which allows handshaking data from
the system processor to a peripheral device is very similar to that
described for Read Handshaking. However, for Write Handshaking, the R6522 generates the "Data Ready" signal and the
peripheral device must respond with the "Data Taken" signal.
This can be accomplished on both the PA port and the PB port on
the R6522. CA2 or CB2 act as a "Data Ready" output in either
the handshake mode or pulse mode and CA 1 or CB 1 accept the
"Data Taken" signal from the peripheral device, setting the interrupt flag and clearing the "Data Ready" output. This sequence
is shown in Figure 10.

REG l2-PERIPHERAL CONTROL REGISTER

\ '\'\5\'\'\'\ ' \0 I
ca2 CONTROL

~

U C . , ON"RRUPT CONTROL

,,5

OPEAATION

0- NEGATIVE ACTIVE EDGEI

o
o

:~~~;ENNE~EANT~~~T~CAT~~!T~~

1 • POSITIVE ACTIVE EDGE

0 0
0 ,

,,

INPUT NEG EOGe*

o ,
o ,

0 INPUT POSITIVE ACTIVE EDGE
, INDEPENDENT INTERAUPT
INPUT POS EDGE*
, 0 0 HANDSHAKE OUTPUT
, 0 , PULSE OUTPUT
, 0 lOW OUTPUT

,, ,

o
o

0 o INPUT NEGATIVE ACTIVE EDGE
0 , INDEPENDENT INTERRUPT

0'

o ,

1 HIGH OUTPUT

'
,

CSl INTERRUPT CONTROL

Selection of operating modes for CAl, CA2, CB1, and CB2 is
accomplished by the Peripheral Control Register (Figure 11).

,
,

10 - NEGATIVE ACTIVE EDGE I
1· POSITIVE ACTIVE EDGE

CA2 CONTAOl
1 OPERATION

o

,

INPUT NEG EDGE*
INPUT PO:::ITlVE ACTIVE EDGE
INDEPENDENT INTERRUPT

INPUT POS EOGE*
0 o HANDSHAKE OUTPUT
0 1 PULSE OUTPUT
-~

1 0 LOW OUTPUT
1 1 HIGH OUTPUT

• SEE NOTE IN FIGURE 29

Figure 11. Peripheral Control Register (PCR)

"'2~11~11~

~

WRITE ORA, ORB
OPERATION
~
"DATA READY"
HANDSHAKE MODE
(CA2,

g~~~ READY

PULSE MODE
(CA2, CB2)
"DATA TAKEN
(CA1, CB1)
IRQ OUTPUT

1I=t==i=
~

.

11---1

~II

ll~-----',

I

-----J

,..--11

/I

L--..J

»
((

~ll.z::zj
II

L---

I

I
I

'--_ _ _ _ _ 11'_ _ _ _-'·r -

II

Figure 10. Write Handshake Timing

2-41

Versatile Interface Adapter (VIA)

R6522
COUNTER/TIMERS

disables any further interrupts, automatically transers the contents of the latches into the counter and continues to decrement.
In addition, the timer may be programmed to invert the output
signal on peripheral pin PB7 each time it "times-out." Each of
these modes is discussed separaely below.

There are two independent 16-bit counterltimers (called Timer 1
and Timer 2) in the R6522. Each timer is controlled by writing
bits into the Auxiliary Control Register (ACR) to select the mode
of operation (Figure 14.

Note that the processor does not write directly into the low-order
counter (T1C-L). Instead, this half of the counter is loaded
automatically from the low order latch (Tl L-L) when the
processor writes into the high order counter (T1C-H). In fact, it
may not be necessary to write to the low order counter in some
applications since the timing operation is triggered by writing
to the high order latch.

Timer 1 Operation
Interval Timer Tl consists of two S-bit latches (Figure 12) and
a 16-bit counter (Figure 13). The latches store data which is to
be loaded into the counter. After loading, the counter decrements
at 02 clock rate. Upon reaching zero, an interrupt flag is set,
and IRQ goes low if the Tl interrupt is enabled. Timer 1 then

REG 6-TIMER 1 LOW-ORDER LATCH

REG 7-TIMER 1 HIGH-ORDER LATCH

1+1+1+1+1

~§

COUNT
VALUE
L...------32
L--------64

COUNT
VALUE

L--------16384

L---------128

L---------32768

WRITE - 8 BITS LOADED INTO T1 LOW-QRDER
LATCHES. THIS OPERATION IS NO
DIFFERENT THAN A WAITE INTO
REG 4
READ - 8 BITS FROM T1 LOW-ORDER LATCHES
TRANSFERRED TO MPU UNLIKE REG 4
OPERATION, THIS ODES NOT CAUSE
RESET OF T1 INTERRUPT FLAG

WAITE - 8 BITS LOADED INTO T1 HIGH-ORDER
LATCHES UNLIKE REG 4 OPERATION
NO LATCH.TO·COUNTER TRANSFERS
TAKE PLACE
READ - 8 BITS FROM T1 HIGH-QRDER LATCHES
TRANSFERRED TO MPU

Figure 12. Timer 1 (Tl) Latch Registers

REG 4-TIMER 1 LOW-ORDER COUNTER

REG 5-TIMER 1 HIGH-ORDER COUNTER

l716151413121'H

~
COUNT
VALUE

16

COUNT
VALUE

32

'-------8192

64

'--------16384

128

L...--------32768

WRITE - 8 BITS LOADED INTO T1 LOW-ORDER
LATCHES LATCH CONTENTS ARE
TRANSFERRED INTO LOW-ORDER
COUNTER AT THE TIME THE HIGHORDER COUNTER IS LOADED (REG 5)
READ - 8 BITS FROM T1 LOW-ORDER COUNTER
TRANSFERRED TO MPU IN ADDlTlON,
T1 INTERRUPT FLAG IS RESET (BIT 6
IN INTERRUPT FLAG REGISTER)

WAITE - 8 BITS LODED INTO T1 HtGH-ORDEA
LATCHES ALSO. AT THIS TIME BOTH
HIGH· AND LOW-ORDER LATCHES
TRANSFERRED INTO T1 COUNTER
T1 INTERRUPT FLAG ALSO IS RESET
READ - 8 IBTS FROM T1 HIGH-ORDER COUNTER
TRANSFERRED TO MPU

Figure 13. Timer 1 (Tl) Counter Registers

2-42

Versatile Interface Adapter (VIA)

R6522
REG 11-AUXILIARY CONTROL REGISTER

1710151413121,1°1
'

11 TIMER CONTROL

I

'

PB7
70
° ° TIMED INTERRUPT
°,
, ° TIMED INTERRUPT
,,
OPERATION

EACH TIME Tl IS
LOADED
CONTINUOUS
INTERRUPTS

EACH TIME 11 IS
LOADED
CONTINUOUS
INTERRUPTS

DISABLED

ONE SHOT
OUTPUT

saUARE
WAVE
OUTPUT

I

I

I

T2 TIMER CONTROL
5 OPERATION

o

TIMED INTERRUPT

1 COUNT DOWN WIT
PULSES ON PBS

J
Figure 14. AuxiHary Control Register (ACR)

Timer 1 One·Shot Mode

In the one-shot mode, writing into the T1 L-H has no effect on
the operation of Timer 1. However, it will be necessary to assure
that the low order latch contains the proper data before initiating
the count-down with a "write T1C-H" operation. When the
processor writes into the high order counter (T1 C-H), the T1 interrupt flag will be cleared, the contents of the low order latch will
be transferred into the low order counter, and the timer will begin
to decrement at system clock rate. If the PB7 output is enabled,
this signal will go low on the 02 following the write operation.
When the counter reaches zero, the T1 interrupt flag will be set,
the IRQ pin will go low (interrupt enabled), and the signal on
PB7 will go high. At this time the counter will continue to decrement at system clock rate. This allows the system processor to
read the contents of the counter to determine the time since interrupt. However, the T1 interrupt flag cannot be set again unless
it has been cleared as described in this specification.

The Timer 1 one-shor mode generates a single interrupt for each
timer load operation. As with any interval timer, the delay
between the "write T1C-H" operation and generation of the
processor interrupt is a direct function of the data loaded into
the timing counter. In addition to generating a single interrupt,
Timer 1 can be programmed to produce a single negative pulse
on the PB7 peripheral pin. With the output enabled (ACR7 = 1)
a "write T1C-H" operation will cause PB7 to go low. PB7 will
return high when Timer 1 times out. The result is a single
programmable width pulse.

Timing for the R6522 interval timer one-shot modes is shown
in Figure 15.

112
;j'

WRITE T1C-H
IRQ OUTPUT

PB7 OUTPUT

I

N

I

N·1

I

N-2

I

N-3

I

;'/
0

I N I I N·1 I N-2 I N-3 I

I - - - - N + 1.5CYCLES-------.o.Il

Figure 15. Timer 1 One-Shot Mode Timing

2-43

Versatile Interface Adapter (VIA)

R6522
Timer 1 Free-Run Mode

the time-out can be prevented completely if the processor continues to rewrite the timer'before it reaches zero. Timer 1 will
operate in this manner if the processor writes into the high order
counter (T1C-H). However, by loading the latches only, the
processor can access the timer during each down-counting
operation without affecting the time-out in process. Instead, the
data loaded into the latches will determine the length of the next
time-out period. This capability is particularly valuable in the freerunning mode with the output enabled. In this mode, the signal
on PB7 is inverted and the interrupt flag is set with each timeout. By responding to the interrupts with new data for the latches,
the processor can determine the period of the next half cycle
during each half cycle of the output signal on PB7. In this
manner, very complex waveforms can be generated.

The most important advantage associated with the latches in
T1 is the ability to produce a continuous series of evenly spaced
interrupts and the ability toproduce a square wave on PB7 whese
frequency is not affected by variations in the processor interrupt response time This is accomplished in the "free-running"
mode.
In the free-running mode, the interrupt flag is set and the signal
on PB7 is inverted each time the counter reaches zero, at which
time the timer automatically transfers the contents of the latch
into the counter (16 bits) and continues to decrement from there.
The interrupt flag can be cleared by writing T1C-H, by reading
T1C-L, or by writing directly into the flag as described later.
However, it is not necessary to rewrite the timer to enable setting
the interrupt flag on the next lime-out.

A precaution to take in the use of PB7 as the timer output concerns the Data Direction Register contents for PB7. Both DDRB
bit 7 and ACR bit 7 must be 1 for PB7 to function as the timer
output. If one is 1 and the other is 0, then PB7 functions as a
normal output pin, controlled by ORB bit 7.

All interval timers in the R6522 are "re-triggerable." Rewriting.
the counter will always re-initialize the time-out period. In fact,

.2~

rl

WRITE T1C-H
OPERATION - - - '
IRQ OUTPUT
PB7 OUTPUT

!----fl--

I //

/1-'- - - - ,

.......------~f!

~----

---------,'----i,I-'___________.Jr---------------------~,j~'-----------,1.._ _ __
~ N + 1.5 CyCLES.,..-.-t.I-,----N

+ 2 CYCLES----i.!

Figure 16. Timer 1 Free-Run Mode Timing

Timer 2 Operation

decrementing again through zero. The processor must rewrite
T2C-H to enable selling of the interrupt flag. The interrupt flag
is cleared bY'reading T2C-L or by writing T2C-H. Timing for this
operation is shown in Figure 18.

Timer 2 operates as an interval timer (in the "orie-slot" mode
only), or as a counter for counting negative pulses on the PB6
peripheral pin. A single control bit in the Auxiliary Control Register
selects between these two modes. This timer is comprised of a
"write-only" lower-order latch (T2L-L), a "read-only" low-order
counter (T2C-L) and a read/write high order counter (T2C-H).
The counter registers act as a 16-bit counter which decrements
at 02 rate. Figu~e 17 illustrates the T2 Latch/Counter Registers.

Timer 2 Pulse Counting Mode
In the pulse counting mode, T2 counts a predetermined number
of negative-going pulses on PB6. This is accomplished by first
loading a number into T2. Writing into T2C-H clears the interrupt
flag and allows the counter to decrement each time a pulse is
applied to PB6. The interrupt flag is set when T2 counts down
past zero. The counter will then continue to decrement with each
pulse on PB6. However, it is necessary to rewrite T2C-H to allow
the Interrupt flag to set on a subsequent time-out. Timing for
this mode is shown in Figure 19. The pulse must be low on the
leading edge of 1/)2.

Timer 2 One-Shot Mode·
As an interval timer, T2 operates in the "one-shot" mode similar
to Time 1. In this mode, T2 provides a single interrupt for each
"write T2C-H" operation. After timing out, the counter will continue to decrement. However, setting of the interrupt flag is
disabled after initial time-out so that it will not be set by t~e counter

2-44

Versatile Interface Adapter (VIA)

R6522

REG 9-TIMER 2 HIGH·ORDER LATCH/COUNTER

REG 8-TlMER 2 LOW·ORDER LATCH/COUNTER

25.
512

+
L......_ _ _ _

1.

1024

COUNT
VALUE

COUNT
VALUE

2048
4096

l...._ _ _ _ _ 32

fI

8192

l...._ _ _ _ _ _ ••
16384

L......_ _ _ _ _ _ _ 128
32768

WRITE -

8 BITS LOADED INTO 12 lOW·OROER

READ -

8 BITS FROM T2l0W ORDER COUNTER
TRANSFERRED TO MPU T2 INTERRUPT
FLAG IS RESET

WRITE -

LATCH

8 BITS LOADED INTO T'?: tliGH ORDER

COUNTER ALSO. LOW ORDER LATCH
TRANSFERRED TO LOW ORDER
COUNTER IN ADDITION, T21NTERRUPT
FLAG IS RESET
READ -

881TS FROM 12 HIGH ORDER COUNTER
TRANSFERRED TO MPU

Figure 17. Timer 2 (T2) Latch/Counter Registers

WRITE T2C·H

Ij'

/

IRQ OUTPUT

N

N·1

I

N·2

I

N·3

I

I N·1 I N·2 I

o

1 - - - - - - - N + 1.5 CYCLES

------~

Figure 18. Timer 2 One·Shot Mode Timing

WRITE T2C·H
OPERATION

ro1___________________________________________

~

u

u

PB61NPUT

u

u

IRQ OUTPUT
N

N·1

N·2

II

Figure 19. Timer 2 Pulse Counting Mode

2·45

o

-1

N·3

I

R6522

Versatile Interface Adapter (VIA)

SHIFT REGISTER OPERATION

The shifting operation is triggered by the read or write of the SR
if the SR flag is set in the IFA. Otherwise the first shift will occur
at the next time-out of T2 after a read or write of the SA. Data
is shifted first into the low order bit of SR and is then shifted into
the next higher order bit of the shift register on the negative-going
edge of each clock pulse. The input data should change before
the positive-going edge of the CB1 clock pulse. This data is shifted
into the shift register during the 912 clock cycle following the
positive-going edge of the CB1 clock pulse. After 8 CB1 clOCk
pulses, the shift register interrupt flag will set and IRQ will go low.

The Shift Register (SR) performs serial data transfers into and
out of the CB2 pin under control of an internal modul0-8 counter.
Shift pulses can be applied to the CB1 pin from an external
source or, with the proper mode selection, shift pulses generated
Internally will appear on the CB 1. pin for controlling external
devices.
The control bits which select the various shift register operating
modes are located in the Auxiliary Control Register. Figure 20
illustrates the configuration of the SR data bits and Figure 21
shows the SR control bits of the ACR.

SR Mode 2 - Shift In Under $2 Control
SR Mode 0 - Disabled
In mode 2, the shift rate is a direct function of the system clock
frequency (Figure 23). CB1 becomes an output which generates
shift pulses for controlling external devices. Timer 2 operates as
an independent interval timer and has no etiect on SR. The shifting operation is triggered by reading or writing the Shift Register.
Data is shifted, first into bit 0 and is then shifted into the next
higher order bit of the shift register on the trailing edge of each 4>2
clock pulse. After 8 clock pulses, the shift register interrupt flag
will be set, and the output clock pulses on CB 1 will stop.

Mode 0 disables the Shift Register. In this mode the microprocessor can write or read the SR and the SR will shift on each CB1
positive edge shifting in the value on CB2. In this mode the SR
interrupt Flag is disabled (held to a logic 0).

SR Mode 1 -

Shift In Under Control of T2

In mode 1, the shifting rate is controlled by the low order 8 bits of
T2 (Figure 22). Shift pulses are generated on the CB1 pin to control shifting in external devices. The time between transitions of
this output clock is a function of the system clock period and the
contents of the low order T2 latch (N).

REG 11-AUXILIARY CONTROL REGISTER

1+1+1+1,101
~

L

SHIFT
REGISTER
BITS

SHIFT REGISTER
MODE CONTROL

4
0
0
0
0

3
0
0

2

,, ,,
,
, ,
,,
,,,

NOTES
1 WHEN SHIFTING OUT BIT 7!S THE FIRST BIT

0
0

OUT AND SIMUL T"A'N'"EOUSl Y IS ROTATED BACK
INTO BIT 0
2 WHEN SHIFTING IN, BITS INITIALLY ENTER
BtT 0 AND ARE SHiFTED TOWARDS BIT 7

Figure 20. Shift Registers

0

OPERATION
DISABLED

0

SHIFT IN UNDER CONTROL OF T2
SHIFT IN UNDER CONTROL OF 'I'
SHIFT IN UNDER CONTROL OF EXT eLK

0

SHIFT OUT FREE RUNNING AT T2 RATE

0

SHIFT OUT UNDER CONTROL OF T2
SHIFT OUT UNDER CONTROL OF -1'2
SHIFT OUT UNDER CONTROL OF EXT eLK

Figure 21. Shift Register Modes

\12
WRITE OR READ
SHIFT REG

Figure 22. SR Mode 1 -

Shift In Under T2 Control
2-46

Versatile Interface Adapter (VIA)

R6522
SR Mode 3 - Shift In Under CB1 Control

the shifting operation (Figure 25). Since the Shift Register bit
7 (SR7) is recirculated back into bit 0, the 8 bits loaded into the
shift register will be clocked onto CB2 repetitively. In this mode
the shift register counter is disabled.

In mode 3, external pin CB1 becomes an input (Figure 24). This
allows an external device to load the shift register at its own pace.
The shift register counter will interrupt the processor each time
8 bits have been shifted in. The shift register stops after 8 counts
and must be reset to start again. Reading or writing the Shift
Register resets the Interrrupt Flag and initializes the SR counter
to count another 8 pulses.

SR Mode 5 - Shift Out Under T2 Control
In mode 5, the shift rate is controlled by T2 (as in mode 4). The
shifting operation is triggerd by the read or write of the SR if
the SR flag is set in the IFR (Figure 26). Otherwise the first shift
will occur at the next time-out of T2 after a read or write of the
SA. However, with each read or write of the shift register the
SR Counter is reset and 8 bits are shifted onto CB2. At the same
time, 8 shift pulses are generated on CB1 to control shifting in
external devices. After the 8 shift pulses, the shifting is disabled,
the SR Interrupt Flag is set and CB2 remains at the last data
level.

Note that the data is shifted during the first system clock cycle
following the posiive going edge of the CB1 shift pulse. For this
reason, data must be held stable during the first full cycle following CB1 going high.

SR Mode 4 - Shift Out Under T2 Control (Free-Run)
Mode 4 is very similar to mode 5 in which the shifting rate is
set by T2. However, in mode 4 the SR counter does not stop

02

READSR-----fl~__+_~----------------------~~------------------­

CB10UTPUT
SHIFT CLOCK

g:~!NPUT:w////$/////////§$/I~$///////$§1§$$ffi'§$J/'$M
I~

IRQ

Figure 23. SR Mode 2 -

_________________

Shift In Center 02 Control

L
Figure 24. SR Mode 3 -

Shift In Under CB1 Control

.2
WRITE SR

I I
I
I
--1l"--+--f---+.,...,+--f---+--+--I-'
---+-----11----I

!

N + 2 CYCLES t-.~+to~.,

I!

f-1 _ 1---1 _ r-'L.!....J L!..J

CB1 OUTPUT - - - - - - ;

SHIFT CLOCK

g:~!NPUT ~\,_~I...._......:..

__

p.

....JXI...__:..2_~

Figure 25. SR Mode 4 -

8

Shift Our Under T2 Control (Free-Run)

2-47

x:::c

Versatile Interface Adapter (VIA)

R6522
SR Mode 6 -

Shift OUt Under 1/12 Control

Interrupt Flag each time it counts 8 pulses but it does not disable
the shifting function. Each time the microprocessor writes or
reads the shift register, the SR Interrupt Flag is reset and the
SR counter is initialized to begin counting the next 8 shift pulses
on pin CB1. After 8 shift pulses, the Interrupt Flag is set. The
microprocessor can then load the shift register with teh next byte
of data.

In mode 6, the shift rate is controlled by the 02 system clock
(Figure 27).

SR Mode 7 -

Shift Out Under CB1 Control

In mode 7, shifting is controlled by pulses applied to the CBl pin
by an external device (Figure 28). The SR counter sets the SR

I~

1/12

lilill

WRITE SR
CBl OUTPUT
SHIFT CLOCK
CB2 OUTPUT

DATA

~

2 CYCLES

+=.·--+---4
CYC~r-E_s_---.
I
I
I
I

L.J

..._ _....

N+2

1
2
. . . .

l

3

I

s

'
i---

j!

$S\\,~,*,\\,'~\\,~\\,,%~\,~,r---~--~X~--~--~Xr--~~I/i·~I~s-r---___,:,-_.J. '-_--=-2_--J. ,-_...::3:...--.-.1
_,
i

Figure 26. SR Mode 5 -

02
WRITE SR
CB10UTPUT
SHIFT CLOCK
CB2 OUTPUT

DATA

Shift Out Under T2 Control

1nJl.I1..n...rL
_--Il_'<---'---.,+--+-11-+-1-+--+11-+-1-+--11I--+'l-t-,
i

-+---i1.1-

_\'~~\'~~.....,.\_...;;s,--

__

I
Figure 27. SR Mode 6 -

I

WRITESR

~~:F~N6~~CK

Shift Out Under 02 Control

I-L.rLn...ru-L
-~~
I

I

~

lL. 1-S------.'X
~----:-------....

CB2 OUTPUT _ _ _ _

DATA

2

/18

2r=1
==1
j

.I

s '--s

,

L - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Figure 28. SR Mode 7 -

Shift Out Under CB1 Control

2·48

.~

R6522

Versatile Interface Adapter (VIA)

Interrupt Operation

status of the IRQ output. This bit corresponds to the logic function: IRQ = IFR6 x IER6 + IFR5 x IER5 + IFR4 x IER4 +
IFR3 x IER3 + IFR2 x IER2 + IFRl x IERl + IFRO x IERO.

Controlling interrupts within the R6522 involves three principal
operations. These are flagging the interrupts, enabling interrupts
and signaling to the processor that an active interrupt exists
within the chip. Interrupt flags are set in the Interrupt Flag Register (IFR) by conditions detected within the R6522 or on inputs to
the R6522. These flags normally remain set until the interrupt
has been serviced. To determine the source of an interrupt, the
microprocessor must examine these flags in order, from highest
to lowest priority.

Note:

x = logic AND, + = Logic OR.
The IFR bit 7 is not a flag. Therefore, this bit is not directly cleared
by writing a logic 1 into it. It can only be cleared by clearing all the
flags in the register or by disabling all the active interrupts as discussed in the next section.

Interrupt Enable Register (IER)

Associated with each interrupt flag IS an interrupt enable bit In
the Interrupt Enable Register (IER). This can be set or cleared
by the processor to enable interrupting the processor from the
corresponding interrupt flag. If an interrupt flag is set to a logic 1
by an interrupting condition, and the corresponding interrupt
enable bit is set to a 1, the Interrupt Request Output (IRQ) will
go low. IRQ is an "open-collector" output which can be "wireOR'ed" with other devices in the system to interrupt the processor.

For each interrupt flag in IFR, there is a corresponding bit in the
Interrupt Enable Register (IER) (Figure 30). Individual bits in the
IER can be set or cleared to facilitate controlling individual interrupts without affecting others. This is accomplished by writing to
the (IER) after bit 7 set or cleared to, in turn, set or clear selected
enable bits. If bit 7 of the data placed on the system data bus
during this write operation is a 0, each 1 in bits 6 through a clears
the corresponding bit In the Interrupt Enable Register. For each
zero in bits 6 through 0, the corresponding bit is unaffected.

Interrupt Flag Register (IFR)
In the R6522, all the interrupt flags are contained in one register,
i.e., the IFR (Figure 29). In addition, bit 7 of this register will be
read as a logic 1 when an interrupt exists within the chip. This
allows very convenient polling of several devices within a system
to locate the source of an interrupt.

Selected bits in the IER can be set by writing to the IER with bit 7
in the data word set to a 1. In this case, each 1 in bits 6 through a
will set the corresponding bit. For each zero, the corresponding
bit will be unaffected. This individual control of the setting and
clearing operations allows very convenient control of the interrupts du ring system operation.

The Interrupt Flag Register (IRF) may be read directly by the processor. In addition, individual flag bits may be cleared by writing
a "1" into the appropriate bit of the IFA. When the proper chip
select and register signals are appplied to the chip, the contents
of this register are placed on the data bus. Bit 7 indicates the

In addition to setting and clearing IER bits, the contents of this
register can be read at any time. Bit 7 will be read as a logic 1,
however.

REG 13-INTERRUPT FLAG REGISTER
SET BY
CA2

CA2 ACTIVE EDGE

CA 1 ACTIVE EDGE
SHIFT REG
eB2

REG 14-INTERRUPT ENABLE REGISTER
CLEARED BY
READ OR WRITE
REG 1 (ORA)·
READ OR WRITE
REG 1 (ORA

COMPLETE 8 SHIFTS

READ OR WRITE

CB2 ACTIVE EOGE

SHIFT REG
READ OR WRITE ORB·

TIME OUT OF T1

READ T1l0W OR

ANY ENABLED
INTERRUPT

CLEAR ALL
INTERRUPTS

o=

CB'======~~C~B'~A~C~T~IV~EfE~DG~E~~R~E~A~D~O[,R~W~RI~T~O~R~B~
TIME-OUT OF T2
~~~.?E Ti2 L~~HOR

= INTERRUPT

TIMER 2-

IRQ

INTERRUPT
DISABLED
ENABLED

~:ME~R~'~=======l~~~~===i]W~R~IT~E~T'~H~'~GH====j

' - - - - - - - - - TIMER 1
' - - - - - - - - - - SET/CLEAR
NOTES
, IF BIT 7 IS A "0", THEN EACH .. , .. IN BITS 0 - 6 DISABLES THE
CORRESPONDING INTERRUPT
2 IF BIT 7 IS A "''', THEN EACH .. , .. IN BITS 0 -6 ENABLES THE
CORRESPONDING INTERRUPT
3 IF A READ OF THIS REGISTER IS DONE, BIT 7 WILL BE .. , .. AND
ALL OTHER BITS WILL REFLECT THEIR ENABLE/DISABLE STATE

• IF THE CA2/CB2 CONTROL IN THE peR IS SELECTED AS
"INDEPENDENT" INTERRUPT INPUT, THEN READING OR
WRITING THE OUTPUT REGISTER ORA/ORB WILL NOT
CLEAR THE FLAG BIT INSTEAD, THE BIT MUST B E
CLEARED BY WRITING INTO THE IFR, AS DESCRIBED
PREVIOUSL Y

Figure 29. Interrupt Flag Register (IFR)

Figure 30. Interrupt Enable Register (IER)

2-49

R6522

Versatile Interface Adapter (VIA)

PERIPHERAL INTERFACE CHARACTERISTICS
Symbol

:

Characteristic

t" t f

Rise and Fall Time for CAl, CBI, CA2 and CB2 Input Signals

tCA2

Delay Time, Clock Negative Transition to CA2 Negative Transition (read handshake or
pulse mode)

Min.

Max.

Unit

-

10

~s

Figure

1.0

~s

31a, 31b
31a

-

-

1.0

~s

2.0

~s

31b

Delay Time, Clock Positive Transition to CA2 or CB2 Negative Transition
(write handshake)

0.05

1.0

~s

31c,31d

020

31c,31d

tRS1

Delay Time, Clock Negative Transition to CA2 Positive Transition (pulse mode)

t RS2

Delay Time, CAl Active Transition to CA2 Positive Transition (handshake mode)

tWHS
tos

Delay Time, Peripheral Data Valid to CB2 Negative Transillon

1.5

~s

tRS3

Delay Time, Clock PosItive Transition to CA2 or CB2 Positive Transition (pulse mode)

-

1.0

~s

31c

tRS4

Delay Time, CAlor CBI Active Transition to CA2 or CB2 Positive Transillon
(handshake mode)

-

2.0

~s

31d

ns

31d

ns

31e

t21

Delay Time Required from CA2 Output to CA I Active Transillon (handshake mode)

400

tiL

Setup Time, Peripheral Data Valid to CAlor CBI Active Transition (input latching)

300

-

tAL

CA I, CBI Setup Prior to Transition to Arm latch

300

-

ns

31e

tpDH

Peripheral Data Hold After CAl, CBI Transition

ISO

-

ns

31e

tSR1

Shift-Out Delay Time -

-

300

ns

311

tSR2

Shift-In Setup Time -

300

-

ns

31g

tSR3

External Shift Clock (CBI) Setup Time Relative to <1>2 Trailing Edge

100

TCY

ns

31g

tlPW

Pulse Width -

PB6 Input Pulse

2 x TCY

-

31i

tlCW

Pulse Width -

CBI Input Clock

2 x TCY

-

31h

Time from <1>2 Failing Edge to CB2 Data Out
Time from CB2 Data In to <1>2 Rising Edge

tiPS

Pulse Spacing -

PB6 Input Pulse

2 x TCY

-

311

tiCS

Pulse Spacing -

CBI Input Pulse

2 x TCY

-

31h

2-50

Versatile Interface Adapter (VIA)

R6522
PERIPHERAL INTERFACE WAVEFORMS
1/)2

READ IRA
OPERATION

fJ

CA2
"DATA TAKEN"

Figure 31a. CA2 Timing for Read Handshake, Pulse Mode

1/)2

READ IRA
OPERATION

~rf----f'OV

CA2
"DATA TAKEN"

O.8V

~1

"DATA READY"

/

I::

,_

>f

----------------------------------~;~----

Figure 31b. CA2 Timing for Read Handshake, Handshake Mode

1/)2

WRITE ORA, ORB
OPERATION

CA2, CB2
"DATA READY"

1----loS----1
PA,PB
PERIPHERAL
DATA

2.0V

O.8V

Figure 31e. CA2, CB2 Timing for Write Handshake, Pulse Mode
2-51

20~.8VV

L

IRS2

ACTIVE
TRANSITION

Versatile Interface Adapter (VIA) .

R6522

WRITE ORA, ORB
OPERATION

CA2, CB2
"DATA READY"

PERIPHERAL
PA,PB
DATA

~~~~~~~~~~~~~

~~~--------------+-~r----------------t-

CAl, CBl
"DATA TAKEN"

Figure 3111. CA2, CB2· Timing for Write Handshake, Handshake Mode

~;~£~~TCHING

~ : : : .-t-AL- -t-'-L: -~:- ~f~'~:~:~ "

____________...

TRANSITION

Figure 3le. Peripheral Data Input Latching Timing

CBl
SHIFT CLOCK
(INPUT OR
OUTPUT)

DELAY TIME MEASURED FROM THE FIRST 1>2
FALLING EDGE AFTER CBl FALLING EDGE.

Figure 31f. Timing for Shift Out with Internal or External Shift Clocking

2·52

R6522

Versatile Interface Adapter (VIA)

\12
I

tSR2

CB2
SHIFT DATA
(INPUT)

2.0V
O.SV

CBl
SHIFT CLOCK
(INPUT OR
OUTPUT)

l.4V
i

1.41

- - t SR3

SET UP TIME MEASURED TO THE FIRST
~ RISING EDGE AFTER CBl RISING EDGE.

f----

\I2

Figure 31g. Timing for Shift in with Internal or External Shift Clocking

CBl
SHIFT CLOCK
INPUT

l2.0V
2.0V
\O.SV

o.svi
I

I

i

~---- t ,CW -----------j

I

1\. .____

I

I

1-----------

tiCS

-------1

Figure 31 h. External Shift Clock Timing

PBS
PULSE COUNT
INPUT

2.0V\

I

---I
COUNTER T2
DECREMENTS
HERE

Figure 31i.

Pulse Count Input Timing

2-53

'----

fJ

R6522

Versatile Interface Adapter (VIA)

BUS TIMING CHARACTERISTICS
Parameter

Symbol

READ TIMING
Cycle Time

1

10

Address Set-Up Time

TCY
TACR

Address Hold Time

TCAR

0

Peripheral Data Set-Up Time

TpCR

300

Data Bus Delay Time

TCOR

-

Data Bus Hold Time

THR

10

-

1

10

-

180

365

0.5

10

~s

90

-

ns

0

-

ns

150

-

ns

190

ns

10

-

ns

0.50

10

~s

235

-

ns

-

ns

-

WRITE TIMING
Cycle Time

TCY

02 Pulse Width

470

Address Set-Up Time

Tc
TACW

Address Hold Time

TCAW

0

RIW Set-Up Time
RIW Hold Time

Twcw
Tcww

180

Data Bus Set-Up Time

200

Data Bus Hold Time

Tocw
THW

Peripheral Data Delay Time

Tcpw

-

Peripheral Data Delay Time
to CMOS Levels

TCMOS

-

-

180

0
10

Note: tR and tF = 10 to 30 ns.

2-54

90
90

-

0

-

0

ns
ns
ns

10

-

1.0

-

0.5

~s

2.0

-

1.0

~s

90

ns
ns

R6522

Versatile Interface Adapter (VIA)

BUS TIMING WAVEFORMS

.2

CLOCK

-----+-

fI

CHIP SELECTS,
REGISTER SELECTS,

R/W

PERIPHERAL
DATA

DATA BUS - - - - - - - - - - " \

Read Timing Waveforms

.2

CLOCK

CHIP SELECTS,
REGISTER SELECTS

R/W

DATA
BUS

PERIPHERAL
DATA

Write Timing Waveforms

2·55

Versatile Interface Adapter (VIA)

R6522
ABSOLUTE MAXIMUM RATINGS*
Symbol

Value

Unit

Supply Voltage

Paramatar

Vee

-0.3 to + 7.0

Vdc

Input Voltege

VIN

-0.3 to +7.0

Vdc

Operating Temperature
Commercial
Industrial

TA

to +70
-40 to +8S

·C
·C

Storage Temperature .

TSTG

-55 to +150

·C

o

·NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

OPERATING CONDITIONS
Symbol

Parameter
Supply Voltege

Vee

Temperature Range
Commercial

TA

Value
SV ±S%
O·C to 70·C

DC CHARACTERISTICS
(Vee

= 5.0 Vdc

±5%, Vss

= 0, TA = TL to TH, ul)less otherwise noted)
Min.

Typ.3

Input High Voltage

VIH

204

-

Parameter

Symbol

Max.

Unit

Vee

V

Input Low Voltage

VIL

-0.3

0.4

V

Inpu!J.eakage Current
RAN,RES, RSO, RS1, RS2, RS3,CS1,CS2,CA1,'2

liN

-

±1

±2.S

,..A

Input Leakage Current lor Thrae-State Off
00-007
Input High Current
PAO-PA7, CA2, PBO-PB7, CB1, CBS

ITSI

-

±2

±10

,..A

Input Low Current
PAo-PA7, CA2, PBo-PB7, CB1, CB2

IlL

Output High Voltage
All outputs
PSO-PB7, CB2 (Darlington Drive)

VOH

Output Low Voltage"

VOL

..

Output High Current .(So,!rclng)
Logic
PSO-PB7, CB2 (Darlington Drive)

IOH

Output Low Currenl(Sinking)
Output Leakage Current (Off Stete)
IRQ

-200

-

,..A

-

-0.9

-1.8

mA

2.4
1.S

-

-

V
V

-

004

V

-100

IIH

-

-1000
-2.S

10L

1.6

-

-

IOFF

Power Dissipation

Po

Input Capacitance
fIt/W, RES, RSO, RS1, RS2, RS3, CS1, CS2,
00-07, PAo-PA7, CA1, CA2, PBo-PB7
CB1, CB2
,2 Input

CIN

-

,..A
mA

VOH = 2.4V
VOH = 1.SV

-

mA

VOL = 0.4V

±10

,..A

VOH = 2AV
Vee = S.2SV

-

450

700

mW

-

-

7

pF

Vee = S.OV
VIN = OV

10
20

pF
pF

1= 1 MHz
TA = 2S·C

10

pF

Note.:
1. All units are direct current (DC) except lor capacitance.
2. Negative sign indicates outward current flow, positive indicates Inward flow.
3. Typical values shown lor Vee = S.OV and TA = 2S·C.

2-56

-10

4

-

COUT

= OV to S.2SV
= OV
VIN = OAV to 2AV
Vee = S.25V
VIN = 2.4V
Vee = S.2SV
VIL = OAV
Vee = S.2SV
Vee = 4.7SV
ILOAO = -1oo,..A
ILOAO = -1.0 mA
Vee = 4.7SV
VIN
Vee

ILOAD - 1.6 mA

-100
-1.0

. Output Capacitance

-

Test Conditions

Versatile Interface Adapter (VIA)

R6522
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP

MILLIMETERS
"'M MIN MAX
A
5029 5131
1486 1562
B
254
419
C
0
038
053
F
076
140
254 esc
G
H
076
178
020
033
J
254
419
K
L
1460 1537
M
0'
la'
N
051
152

INCHES
MIN
MAX
1980 2020
0585 0615
0100 0165
0015 0021
0030 0055
0100

esc

0030
0008
0100

0070

0575

0605
10'
0060

0'
0020

0013
o t65

40-PIN PLASTIC DIP
MILLIMETERS
DIM MIN MAX
A
5128 5232
B
1372 1422
C
355
50B
0
036
051
F
102
152
254 esc
G
216
H
165
020
030
J
K
356
305
L
1524 esc
10'
M
7'
N
051
102

2-57

INCHES
MAX
MIN
2040 2060
0540 0560
0140 0200
0014 0020
0040 0060

o 100 esc
0065

0085

0008

0012

0120 0140
a 600 esc
10'
r

0020

0040

R6530

'1'

Rockwell

R6530
ROM-RAM-I/O-TIMER (RRIOT)

DESCRIPTION

FEATURES

The R6530 ROM-RAM-I/O-Timer (RRIOT) combines read only
memory, random access memory, parallel I/O data ports, and
timer functions into a single peripheral device which operates
in conjunction with any CPU In the R6500 microprocessor family.
The R6530 allows two chip solutions In a variety of production
applications. It IS comprised of a mask programmable 1024 x
8 ROM, a 64 x 8 static RAM, two software controlled 8-blt
bidirectional data ports allOWing direct Interfacing between the
microprocessor unit and penpheral devices, and a software programmable Interval timer with Interrupt, capable of timing in various intervals from 1 to 262,144 clock periods.

•

1024 x 8 mask programmable ROM

•
•

64 x 8 static RAM
Two 8-bit bidirectional data ports for interface to peripherals

•

Two programmable data direction registers

•

Programmable interval timer

•

Programmable interval timer interrupt

•

TTL & CMOS compatible peripheral lines

•

Peripheral pins with direct transistor dnve capability

•

8-bit directional data bus for direct communication with the
microprocessor

•

High impedance three-state data bus

•

Allows up to 7K contiguous by1es of ROM with no external
decoding

ORDERING INFORMATION
Part Number: R6530_
Lpackage:
C = Ceramic DIP
P = Plastic DIP

vss
PAO
2
RSO
A9
AS
A7
A6
R/iii
A5
A4
A3
A2
A1
AO
RES
I RQ/PB7
CS1/PB6
CS2/PB5

Temperature Range:
O°C to 70°C
Frequency:
1 MHz
Note: A custom part number will be assigned by Rockwell.
ROM codes should be submitted using ROM Code Order
Form, Order No. 2137.

vcc

PA1
PA2
PA3
PA4
PA5
PA6
PA7
00
01
02
03
04
05
06
07
PBO
PB1
PB2
PB3
PB4

R6530 Pin Configuration

Document No. 29000041
2-58

Data Sheet Order No. 041
Rev. 5, August 1983

R6530

ROM-RAM-I/O-Timer (RRIOT)

INTERFACE SIGNALS
RESET (RES)

ADDRESS LINES (AO- A9)

During system initialization, a RES input causes zeroing of all
four 1/0 registers. This in turn causes all 1/0 buses to act as
inputs thus protecting external components from possible
damage and erroneous data while the system is being configured under software control. The Data Bus Buffers are put into
an off state during Reset. Interrupt capability is disabled with
the RES signal. The RES signal must be held low for at least
one clock period when reset is required.

There are 10 address pins (AO-A9). In addition, there is the
ROM Select pin (RSO). Further, pins PB5 and PB6 are mask
programmable, and can be used either individually or together
as chip selects. When used as peripheral data pins they cannot
be used as chip selects.

ROM SELECT (RSO)
RSO serves as an additional address input line. When RSO is
high, Internal ROM is selected; when RSO is low, internal ROM
is not selected.

READ/WRITE (RiW)
The R/W input is supplied by the microprocessor and controls
the transfer of data between the R6530 and the microprocessor
via the data bus. A high on the RlW Pin reads (With proper
addressing) data from the R6530 onto the data bus. A low on
the R/W pin writes (with proper addressing) data from the data
bus into R6530.

PERIPHERAL DATA PORTS
The R6530 has 16 pins available for peripheral I/O operations.
Each pin IS IndiVidually software programmable to act as either
an Input or an output. The 16 pins are diVided into two 8-bit
ports, PAO-PA7 and PBO-PB7. PB5, PB6 and PB7 also have
other uses which are discussed In later sections. The pins are
set up as an Input by writing a "a" Into the corresponding bit of
the Data Direction Register. A "1" into the Data Direction Register causes its corresponding bit to be an output. When In the
Input mode, the Peripheral Data Buffers are in the "1" state and
the internal pull-up device acts as less than one TTL load to
the peripheral data lines. On a Read operation, the microprocessor unit reads the peripheral pin. When the peripheral deVice
gets Information from the R6530 It receives data stored In the
Output Register. The microprocessor will read correct information If the peripheral lines are greater than 2.0 volts (for a
"1") or less than 0.8 volts (for a "a") as the peripheral pins are
all TTL compatible.

PHASE 2 CLOCK (9'2)
The Phase 2 clock (02) Input IS the system clock generated by
the CPU that triggers all data transfers between the data bus
and the R6530.

INTERRUPT REQUEST (IRQ)
The IRQ pin is an Interrupt pin from the interval timer. This same
pin, if not used as an interrupt, can be used as a peripheral
1/0 pin (PB7). When used as an interrupt, the pin should be set
up as an input by the Data Direction Register. The pin will be
normally high with a low Indicating an interrupt from the R6530.
An external pull-up device is not required; however, if collectorOR'd with other devices, the internal pullup may be omitted With
a mask option.

DATA BUS (DO- D7)
CHIP SELECT (CSO, CS1)

The R6530 has eight bidirectional data pins (DO-D7). These
pins connect to the system's data lines and allow transfer of data
to and from the microprocessor The output buffers remain In
the off state except when selected for a Read operation.

<

(8)

"'

(10)

"

A

00-07

AO-A91

Pins 18 and 19 are Individually selectable at mask time as either
chip selects CS1 and CS2, respectively, or port B functions PB6
and PB5, respectively.

,

8)

.

) PAO-PA7

"

R6500
MICROPROCESSOR
BUS

'MASK PROGRAMMABLE
OPTION.

l

~2
Rm
!'ISO
CS1'
CS2'
RES
IRQ ..

R6530
RRIOT

~i

PERIPHERAL
INTERFACE

r
Interface Signals
2-59

(8)

>

1'60-1'67

J

fJ

R6530

ROM-RAM-I/O-Timer (RRIOT)

INTERNAL ORGANIZATION

INTERNAL PERIPHERAL REGISTERS

The R6530 IS divided into four basic sections: RAM, ROM, I/O
and Timer. The RAM and ROM interface directly with the microprocessor through the system data bus and address lines. The
I/O secticn consists of two 8-bit halves. Each half contains a
Data Direction Register (DDR) and an Output Register.

There are four internal registers, two data direction registers and
two output registers. The two data direction registers (A side and
B side) control the direction of the data into and out of the
peripheral pins. A "1" written into the Data Direction Register
sets up the corresponding peripheral buffer pin as an output.
Therefore, anything then written Into the Output Register will
appear on that corresponding peripheral pin. A "0" written into
the DDR inhibits the output buffer from transmitting data from
the Output Register. For example, a" 1" loaded into Data Direction Register A, position 3, sets up peripheral pin PA3 as an
output. If a "0" had been loaded, PA3 would be configured as
an input and remain in the high state. The two Data Output Registers are used to latch data from the Data Bus during a Write
operation until the peripheral device can read the data supplied
by the microprocessor.

ROM-1K BYTE (SK BITS)
The 1K byte ROM is in a 1024 x 8 configuration. Address lines
AO-AS, as well as RSO are needed to address the entire ROM.
With the addition of CS1 and CS2, seven R6530's may be
addressed, giving 7168 x 8 bits of contiguous ROM.

RAM-64 BYTES (512 BITS)
A 64 x 8 static RAM is contained on the R6530. It is addressed
by AO-A5 (Byte Select), RSO, A6, A7, A8, AS and, depending
on the number of chips in the system, CS1 and CS2.

During a Read operation the microprocessor is reading the
peripheral data pins. For the peripheral data pins which are
programmed as outputs the microprocessor will read the corresponding data bits of the Output Register. The only way the
Output Register data can be changed is by a microprocessor
Write operation. The Output Register is not affected by a Read
of the data on the peripheral pins.

PA7

PAO

PBO

1- - --1

11----1
DATA
DIRECTION
REGISTER
A

PERIPHERAL

OUTPUT
REGISTER
A

DATA
BUS
BUFFER

~ DATA BUFFER
A

--- -1 r- --~t
DO

07

AO

A9

INTERVAL
TIMER

CHIP
SELECT
R/W

ADDRESS
DECODER

CS1

64 x 8
RAM

----

PERIPHERAL
DATA BUFFER
B

1K x 8
ROM

f+-

OUTPUT
REGISTER

B

DATA
DIRECTION
REGISTER

B

1rJw
1/>2

PB7

RSO

R6530 Block Diagram

2-60

r--

ROM-RAM-I/O-Timer (RRIOT)

R6530

When the timer has counted down to 0 0 0 0 0 0 0 0 on the
next count time an Interrupt will occur and the counter will read
1 1 1 1 1 1 1 1. After interrupt, the Timer Register decrements at a divide by "1" rate of the system clock. If after interrupt, the timer is read and a value of 1 1 1 0 0 1 0 0 is read
the time since interrupt is 27T. The value read is in one'~
complement.

INTERVAL TIMER
The Timer section of the R6530 contains three basic parts: prescale divide down register, programmable 8-bit register and
interrupt logic.
The interval timer can be programmed to count up to 256 time
intervals. Each time Interval can be either 1T, 8T, 64T or 1024T
increments, where T IS the system clock period. When a full
count is reached, an interrupt flag is set to a logic" 1". After the
Interrupt flag IS set the Internal clock begins counting down to
a maximum of - 225T. Thus, after the interrupt flag is set, a Read
of the timer will tell how long since the flag was set up to a maxImum of 255T.

Value read = 1 1 1 0 0 1 0 0
Complement = 0 0 0 1 1 0 1 1 = 27
Thus, to arrive at the total elapsed time, merely do a one's complement and add to the original time written into the timer.
Again, assume time written as 0 0 1 1 0 1 0 0 (=52). With
a divide by 8, total time to interrupt is (52 x 8) + 1 = 417T. Total
elapsed time would be 417T + 27T = 444T, assuming the value
read after interrupt was 1 1 1 0 0 1 0 O.

The 8 bit system Data Bus IS used to transfer data to and from
the Interval Timer. If a count of 52 time Intervals were to be
counted, the pattern 0 0 1 1 0 1 0 0 would be put on the
Data Bus and written Into the Interval Timer Register.

After the interrupt, whenever the timer IS written or read the
interrupt is reset. However, the reading of the timer at the same
time the interrupt occurs will not reset the Interrupt flag. When
the interrupt flag is read on D7 all other D outputs (DO through
D6) go to "0".

At the same time that data is being written to the Interval Timer,
the counting interval (1, 8, 64, or 1024T) is decoded from
address lines AO and A 1. During a Read or Write operation
address line A3 controls the interrupt capability of PB7, i.e., A3 =
1 enables IRQ on PB7, A3 = 0 disables IRQ on PB7. When
PB7 is to be used as an interrupt flag with the Interval timer It
should be programmed as an input. If PB7 is enabled by A3 and
an interrupt occurs PB7 will go low. When the timer IS read prior
to the interrupt flag being set, the number of time intervals
remaining will be read, i.e., 51, 50, 49, etc.

When reading the timer after an interrupt, A3 should be low so
as to disable the IRQ pin. This is done so as to avoid future
Interrupts until after another Write timer operation.

AO

INTERRUPT
CONTROL

D7

PROGRAMMABLE
REGISTER

D6

D4

D2 DO

Basic Elements of Interval Timer

2-61

DIVIDE
DOWN

<1>2

fJ

R6530

ROM-RAM-I/O-Timer (RRIOT)

ct>21N
WRITET ~~______________________________________________________________________

CD Data written Into Interval timer Is: 0 0

1 1 0 1 0 0

® Data In Interval timer Is: 0 0 0 1 1 0 0 1 = 25, a
52 -!!! - 1 = 52 - 26 - 1 = 25
8
@

Data In Interval timer Is: 0 0 0 0 0 0 0 0
415

52 -

""8 - 1 = 52 -

51 - 1

= 0'0

=0

@

Interl\Jpt has occurred at ~2 pulse #416
Data In Interval timer Is: 1 1 1 1 1 1 1

®

Data In Interval timer IS: 1 0 1 0 1 1 0 0
two's complement IS:
0 1 0 1 0 0 1 1
83 + (52 x 8) + 1 = 500'0

= 83,0

R6S3D Timer Example

2·62

= 52'0

R6530

ROM·RAM·I/O· Timer (RRIOT)

ADDRESSING

SEVEN-CHIP ADDRESSING

Addressing of the R6530 offers many variations to the user for
greater flexibility. The user may configure his system with RAM
in lower memory, ROM in higher memory, and 1/0 registers with
interval timers between the extremes. There are 10 address
lines (AO-A9). In addition, there is the possibility of 3 additional
address lines to be used as chip·selects and to distinguish
between ROM, RAM, 1/0 and interval timer. Two of the addi·
tional lines are chip·selects 1 and 2 (CS1 and CS2). The chip·
select pins can also be PBS and PB6. Whether the pins are
used as chip-selects or peripheralI/O pins is a mask option and
must be specified when ordering the part. Both pins act inde·
pendently of each other in that either or both pins may be des·
ignated as a chip·select. The third additional address line is
RSO. The R6502 and R6530 in a 2-chip system would use RSO
to distinguish between ROM and non·ROM sections of the
R6530. With the addressing pins available, a total of 7K con·
tiguous ROM may be addressed with no external decode. Follow·
ing is an example of a 1·chip and a 7·chip R6530 Addressing
Scheme.

In the seven·chip system, the objective would be to have 7K
bytes of contiguous ROM, with RAM in low order memory. The
7K of ROM could be placed between addresses 65,535 and
1024. For this case, assume A13, A14 and A15 are all 1 when
addressing ROM, and 0 when addressing RAM or I/O. This
would place the 7K ROM between addresses 65,535 and 58,367.
The two pins designated as chip-select, or 110, would be masked
programmed as chip·select pins. Pin RSO would be connected
to address line A10. Pins CS1 and CS2 would be connected to
address lines A11 and A12 respectively. See table 1.
The two examples shown would allow addressing of the ROM
and RAM; however, once the I/O or timer has been addressed,
further decoding is necessary to select which of the I/O registers
are desired, as well as the coding of the interval timer.

I/O REGISTER-TIMER ADDRESSING
Table 2, Addressing Decode for 110 Register and Timer,
illustrates the address decoding for the internal elements and
timer programming. Address lines A2 distinguishes I/O registers
from the timer. When A2 is high and 110 timer select is high,
the 110 registers are addressed. Once the 110 registers are
addressed, address lines A 1 and AO decode the desired register.

ONE-CHIP ADDRESSING
A 1·chip system decode is illustrated in the R6530 One·Chip
Address Encoding Diagram.

When the timer is selected A 1 and AO decode the divide by
matrix. In addition, Address A3 is used to enable the interrupt
flag to PB7.

Table 1. R6530 Seven-Chip Addressing Scheme
Address, Chip Select and Register Select Linea
Device

Function

CS2
A12

A9

A8

A7

AS

R6S30 #1

ROM Select
RAM Select
VO Timer

0
0
0

0
0
0

1
0
0

X

X

X

X

0
1

0
0

0
0

0
0

ROM Select
RAM Select
VO Timer

0
0
0

1
0
0

0
0
0

X

X

X

X

0
1

0
0

0
0

1
1

ROM Select
RAM Select
VO Timer

0
0
0

1
0
0

1
0
0

X

X

X

X

0
1

0
0

1
1

0
0

ROM Select
RAM Select
VO Timer

1
0
0

0
0
0

0
0
0

X

X

X

X

0
1

0
0

1
1

1
1

ROM Select
RAM Select
VO Timer

1
0
0

0
0
0

1
0
0

X

X

X

X

0
1

1
1

0
0

0
0

ROM Select
RAM Select
1/0 Timer

1
0
0

1
0
0

0
0
0

X

X

U

1

X
0

X
i

1

1

0

1

ROM Select
RAM Select
VO Timer

1
0
0

1
0
0

1
0
0

X

X

X

X

0
1

1
1

1
1

0
0

R6S30 #2

R6S30 #3

R6S30 #4

R6S30 #5"

R6S30 #6

R6S30 #7

CS1
All

RSO
A10

Note:" RAM select for R6S30 #5 would read = m.A11.A1O.AS.AS.A'i'.A'6

2-63

ROM-RAM-I/O-Timer (RRIOT)

R6530

r-'

INT TIMER SEl

-A3
INTERVAL

_AI

riMER

AD

I/O TIMER SEL

A X indicates mask programming, I.e..
ROM select ~ CSt. RSO
RAM select ~ CSt.RSO.A9".A7. A6

rLJ

IfOSEL

RAl

110

AD

VO TIMER SELECT = CSt.RSO. A9.A8.A7.A6
B. Notice that AS IS a don't care for RAM select
C. CS2 can be used as PBS in this exampl
e

cs,
C51

RSO
AS

AS

A7
A6

A'

AAMSEL

r-----;" -----~ ---~
I
I

A4

A3

I
I
I
I
I
I
I

:L[)
~4::

:4)
:4::

RAM

A'
Al
AD

AOMSEL

!

AS

I
I

::-c

A'

I
I
I
I

:~

A7
A'

I

:4>

--

A5

I

------

-------

...

A'
A.

A3

A3

A'

A2

Al

Al

AD

AD

R6S30 One-Chip Address Encoding Diagram
Table 2. Addressing Decode for 1/0 Register and Timer
Addressing Decode
Function
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write

ROM
RAM
RAM
DORA
DORA
DORB
DORB
Per Reg.
Per. Reg.
Per. Reg.
Per. Reg.
Timer

A
A
B
B

~IT

-BT
-64T
-1024T
Read Timer
Read Interrupt Flag
Notes: *A3
A3

ROM Select

RAM Select

110 Timer Select

RiW

A3

A2

A1

AO

1

0

1

0
0
0
0
0
0
0
0
0
0

1
1

0
0
0

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0

X
X
X
X
X
X
X
X
X
X
X

X
X
X
0
0
0
0
0
0
0
0

X
X
X
0
0
1
1
0
0
1
1

X
X
X
1
1
1
1
0
0
0
0

0
0
0
0
0

1
1
1
1
1
1

0
0
0
0

··
··
·

1
1
1
1
1
1

0
0

0

1
1
X
X

0

0
0
0
0
0
0

0

= 1 Enables IRQ to PB7
= 0 Disables IRQ to PB7

2-64

0
1
1

0
1

0
1

0
1

1
1

X

1
1

0
1

R6530

ROM-RAM-I/O-Timer (RRIOT)

TIMING CHARACTERISTICS
Read Timing
Characteristic
PJW valid before positive transition of clock
Address valid before positive transrtlon of clock
Peripheral data valid before positive transition of clock
Data Bus valid after positive transition of clock
Data Bus Hold Time
IRQ (Interval Timer Interrupt) valid before positive
transition of clock
Note: Loading =

30 pF

= 130 pF

Symbol
TWCA
TACR
TPCR
TCoA
THA
T,c

Min

Max

Unit

180
180
300

-

10
200

-

ns
ns
ns
ns
ns
ns

Min

Max

Unit

10
25

I"S
ns
ns
ns
ns
ns
ns

395

+ 1 TTL load for PAO-PA7, PBO-PB7
+ 1 TTL load for DO-D7

Write Timing
Characteristic
Clock Period
Rise & Fall Times
Clock Pulse Width
PJW valid before positive transrtlon of clock
Address valid before positive transition of clock
Data Bus valid before negative transij,on of clock
Data Bus Hold Time
Peripheral data valid after negative transition of clock
Peripheral data valid after negative transition of clock
driving CMOS (Level = VCC - 30%)

Symbol
Tcyc
TA, TF
Tc
Twcw
TACW
Tocw
THW
Tcpw
TCMOS

2-65

1
470
180
180
300
10

-

1
2

1"":;
1"":;

fJ

R6530

ROM-RAM-I/O-Timer (RRIOT)

READ TIMING WAVEFORMS

7f

CLOCK INPUT

2AV

~04V

X

24V

20V

R/W

~TWCR

' - - - - - - 1 - - - - - - - - OAV

~~~---------------_t--------~--------------2.4V

ADDRESS

'----_t----------r------_t--------- 04V
r-------~-----_t--------------~---------

PERIPHERAL
DATA

24V

~~-_4------+----------_4---------------------04V

THR

24V

DATA BUS

04V

~

PB7 (IRQ)

TIC

24V

~

_______________________ 04V

WRITE TIMING WAVEFORM~S TCYC~
TR

CLOCK INPUT

LTc:J

I ToI
71'-

-----------

24V

0 4~V

rTF

I

w~

I~

:/

~
24V

R/W

ADDRESS

o 4V
24V

20V

o 8V

04V

24V
DATA BUS

04V
Vcc

T CPW
TDCW-+~__~~--~~

----20V

PERIPHERAL
DATA

o 8V

2-66

-30%

24V
04V

R6530

ROM-RAM-I/O-Timer (RRIOT)

MAXIMUM RATINGS*
Rating

Symbol

Unit

Value

Supply Voltage

Vcc

-0.3 to + 7.0

Input/Output Voltage

V

V ,N

-0.3 to +7.0

V

Operating Temperature

TA

o to 70

Storage Temperature

T STG

-SSto+1S0

'c
'c

'Note: All Inputs contain protection circuitry to prevent damage due to
high static charges. Care should be taken to prevent unnecessary
application of voltage outside the specification range.

fJ

DC CHARACTERISTICS
= 5.aV ± 5%, Vss = av, D·G to 7D·G, unless otherwise noted)

(Vee

Characteristic

Min.

V ,H

+2.4

Vcc

Input Low Voltage

V ,L

-0.3

+0.4

V

2.S

fJ.A

V ,N = 0 to +S.OV
Vcc = 0

±10

fJ.A

V IN = O.4V to 2.4V
Vcc = S.2SV

fJ.A

V ,N = 2.4V

mA

V ,N = O.4V

Typ.

Input Leakage Current
AO-A9, RSO, RiW, RES, 02, PB6(3), PBS(3)

lIN

1.0

Input Leakage Current for Three State Off
00-07

ITS I

±1.0

Input High Current
PAO-PA7, PBO-PB7

I'H

Input Low Current;
PAO-PA7 PBO-PB7

I'L

Output High Voltage
PAO-PA7, PBO-PB7 (TTL drive), 00-07
PBO-PB7, (other drive, e.g., Darlington)

V OH

Output Low Voltage

VOL

Output High Current (Sourcing)
PAO-PA7, PBO-PB7 (TTL drive), 00-07
PBO-PB7 (other drive)

10H

Output Low Current (Sinking)
PAO-PA7, PBO-PB7

10L

Power Dissipation

Po

Input Capacitance
~2
Logic

C 'N

Output Capacitance

-100

Max.

-300
-1.0

-1.6

Unit

Test Conditions

Symbol

Input High Voltage

V

V

Vcc = 4.2SV
ILOAD = -100 fJ.A
I LOAD = 3.0 mA

V

Vcc = 4.2SV
ILOAD = 1.6 mA

+2.4
+1.S
+04

-100
-30

-1000
-S.O

fJ.A
mA
mA

1.6
SOO

CCLK

C OUT

Note: 1. All units are direct current (DC).
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. When programmed as address pins.

2-67

1000

mW

30
10

pF
pF

V OH = 2.4V
V OH = 1 SV
VOL = O.4V

V,N = 0, f = 1 MHz
TA = 2S'C

R6530

ROM-RAM-I/O-Timer (RRIOT)

PACKAGE DIMENSIONS
40-PIN CERAMIC DIP

MILLIMETERS
DIM MIN
MAX
A
5029 5131
1486 1562
B
419
254
C
D
038
053
140
F
076
254
G
H
076
178
033
020
J
254
419
K
1460 1537
L
0'
10
M
051
152
N

sse

0

INCHES
MIN
MAX
2020

1980
0585

0615

0100

0165

0015
0030

0021
0055

o 100 sse
0030

0008
0100
0575
0'
0020

0070
0013
0165

0605
10"

0060

40-PIN PLASTIC DIP
MILLIMETERS
MAX
DIM MIN
A
5128 5232
1372 14 22
B
508
C
355
051
D
036
152
F
102
254
G
165
216
H
020
030
J
K
305
356
1524
L
M
T
10'
102
051
N

sse

sse

2-68

INCHES
MAX

MIN
2040
0540
0140

0014

2060

0560
0200
0020
0060

0040
o 100 sse
0065 0085
0008 0012
0120 0140

0600 sse
10
T
0020 0040

R6531

'1'

R6531
ROM-RAM-I/O COUNTER (RRIOC)

Rockwell
DESCRIPTION

FEATURES

The R6531 ROM-RAM-II0-Counter (RRIOC) integrates readonly memory, random access memory, various I/O data port configurations and timer functions into a single peripheral device
which operates in conjunction with any CPU in the R6500
microprocessor family. The R6531 provides innovative system
designers with a two-chip solution to a wide range of applications. It can also be combined in a variety of multi-chip system
configurations with other R6531 's, ROMs, RAMs and other I/O
devices.

• 2048 x 8 mask programmable ROM
• 128 x 8 static RAM
• 16-bit mUlti-mode counter/latch
-

event counter

-

external trigger

• TIL compatible I/O, drive one TIL load
• 15 bidirectional I/O lines (2 ports -

40-pin package)

• Expansion 8-blt output port and 4·bit input port (52-pin package)
• I/O handshake control
• Four edge sensitive interrupt inputs
• 1 MHz or 2 MHz operation
• ROM-less versions available for prototyping
• Single + 5V power supply

Prototyping circuits are available in both the 40- and 52-pin packages, and in 1- and 2-MHz versions. They are offered as part
numbers R6531-098 and R6531-098A for the 40-pin part, and as
part numbers R6531-099 and R6531-099A for the 52-pin part.

R6S00
MICROPROCESSOR
BUS

PERIPHERAL
INTERFACE

DO-D7

ORDERING INFORMATION

11

pulse generator (one-shot or free-running)

-

• 8-bit serial channel

There are two R6531 versions: a 40-pin dual-in-line package;
another with expanded I/O in a compact 52-pin quad-in-line
package. Both versions contain a 2048 x 8 mask-programmable
ROM, a 128 x 8 static RAM, a software programmable multimode counter, an 8-bit serial data channel, and 15 bidirectional
data lines (two ports) with a handshake control mode and four
interrupt inputs. The 52-pin version has an 8-bit output port and a
4-bit input port for a total of 27 I/O lines. Several mask options are
available to provide a RAM standby power pin and chip selects
for multi-chip systems.

Part Number:
R6S3l

internal timer (one shot or free-running)

-

T~pe,.,",.

PAO-PA7

PBO-PB6

AO-All

- " , (T,-TJ
Blank = 0° to + 70°C
E = -40°C to +85°C

Jl2------l~

RNi---....
Package:
C = 40-Pin DIP, Ceramic
P = 40-Pin DIP, Plastic
Q = 52-Pin QUIP, Plastic

PCO-PC7'

CS1-CS3-----I..
IRQ-----I..
RES-----I..

L -_ _ _

PDO-PD4'

VRR"----'l..

Frequency Range:
No letters = 1 MHz
A = 2 MHz

VCC---+t

NOTE: Contact your local Rockwell representative for
availability.

'S2-PIN VERSION ONLY

"OPTIONAL

Interface Signals
.Document No. 29000052
2-69

Data Sheet Order No. 052
Rev. 5, October 1983

ROM-RAM-I/O Counter (RRIOC)

R6531

PHASE 2 CLOCK (2)

INTERFACE SIGNALS

The Phase 2 Clock (112) input is the system clock that triggers all
data transfers between the data bus and the R6531.

RESET (RES)

PERIPHERAL DATA PORTS (PAO-PA7, PBO"'PB6,
PCO-PC7, PDO-PD3)

This active low signal initializes the R6531. It clears all internal
registers (except the Counter and serial registers) to logic zero.
This action places all bidirectional I/O lines in the input state and
the Port C outputs in the high state. The timer, shift register, and
interrupts are disabled. The RES signal must be low for at least
four clock periods when reset is required.

Both versions of the R6531 have 15 pins available for peripheral
I/O operations. Each pin is software programmable to act as an
input or an output. The pins are grouped into an S-bit port,
PAD-PA7, and a 7-bit port, PBO-PB6. The lines of the PB port
may serve other functions. Ports PA and PB have associated
data direction registers.

ADDRESS BUS (AO-A11) AND CHIP SELECTS
(CS1-CS3)
Memory and register selection is accomplished using the 12
address lines and, in multiple device systems, also using one or
more of the three Chip Select mask options. When PB4, PB5, or
PD2 are chosen as chip selects, they cannot be used as peripheral I/O pins.

The expanded I/O of the 52-pin version provides an S-bit output
only part, peO-PC7, and a 4-bit input only port PDO-PD3. PD2
and PD3 may be assigned other functions as described later.
The outputs are push/pull type drivers capable of driving a single
TIL load. When inputs are selected the drivers float. If PB6 is
programmed as the IRQ request output, the line is driven low and
requires an external pull-up, thus allowing the wire OR-ing of IRQ
from other devices.

OAT A BUS (DO-D7)
The R6531 has eight data bus lines, which allow data to be
transferred to or from the microprocessor. The output buffers
remain in the off-state except when the R6531 is selected for a
read operation.

RAM RETENTION VOLTAGE (VRR)
A separate pin for a power supply for the read/write memory is
available as a mask option. This allows the retention of RAM data
by using a battery back-up for the RAM only. Pin PB6 in the
40-pin version or PD3 in the 52-pin version is mask programmable as the VRR pin. Address line A 10 must be held in the logic
state which deselects RAM (user-defined) in order to protect the
RAM data when VCC falls below the specified level or is turned
off.

READIWRITE (R/W)
The RNi input controls the transfer of data to and from the
microprocessor and the R6531. A high on the RIW pin allows the
processor to read (with proper addressing) the data supplied by
the R6531. A low on the RIW pin allows a write (with proper
addressing) to the R6531.

PA7

PAO

PBS

PC7

PBO

NOTE: '52-PIN VERSION ONLY

R6S31 Block Diagram
2-70

PCO

PD3

PDO

R6531

ROM-RAM-I/O Counter (RRIOC)

VSS
(CS2) PB4/CNTO
(CS1) PB5/CNTl
PB6/IRQ
RES
07
06
05
AS
A7

PB3/S010
R/W
PB2/SCLK
PB1/CA2
PBO/CAl
PA7
PA6
PA5
PA4
A5
A6
PA3
PA2
PAl
PAO
A2
A4
Al
A3
VCC

,p2
04
03
02
01
DO
AO
All
A9
Al0

PB3/S010
RiW
PB2/SCLK
PB1/CA2
PBO/CAl
PA7
PA6
PA5
PA4
A5
A6
PA3
PA2
PAl
PAO
A2
A4
Al
A3
VCC

VSS
(CS2) PB4/CNTO
(CS1) PB5/CNTl
RES
07
06
05
AS
A7

,p2
04
03
02
01
DO
AO
All
A9
Al0
VRR

PB6 OPTION

VRROPTION

R6531 40-Pin DIP Configurations

VSS
(CS2) PB4/CNTO
(CS1) PB5/CNTl
PB6/IRQ
PC7
RES
07
06
05
P03
(CS3) P02
AS
A7

PB3/S010
RiW
PC6
PB2/SCLK
PB1/CA2
PBO/CAl
PC5
PA7
PA6
PA5
PA4
PC4
A5
A6
PC3
PA3
PA2
PAl
PAO
A2
A4
PC2
PCl
Al
A3
VCC

,p2
POl
04
03
POO
02
01
DO
AO
All

peo

A9
Al0

VSS
(CS2) PB4/CNTO
(CS1) PB5/CNT1
PB6/IRQ
PC7
RES
07
06
05
(CS3) P02
AS
A7

PB3/S010
RiW
PC6
PB2/SCLK
PB1/CA2
PBO/CAl
PC5
PA7
PA6
PA5
PA4
PC4
AS
A6
PC3
PA3
PA2
PAl
PAO
A2
A4
PC2
PCl
Al
A3
VCC

,p2
POl
04
03
POO
02
01
DO
AO
All
PCO
A9
Al0
VRR

P03 OPTION

VRR OPTION

R6531 Q 52-Pin QUIP Configurations

2-71

fJ

ROM-RAM-I/O Counter (RRIOC)

R6531

Table 1. R6531 Addressing

INTERNAL ORGANIZATION

Chip
Selects

The R6531 is divided into three basic functions: ROM, RAM, and
I/O. The selection of anyone of these three is accomplished by
issuing the appropriate address information on the address bus
when the chip is selected

RS531
Function

CS3 CS2 CS1

ROM
RAM

ROM-2K BYTES (16K BITS)

Address Inputs (AO·A 11)

1/0

X

X

J

11 10 1 9

X

J

a l71 s

51413

J

211 1 0

2K ROM Decode

X

V V V V VIV IV IV I 128 RAM Decode
Z Z Z Z z IZ IZ IZ IZ IZ IZ 11/0 Decode

The 16K ROM is a 2048 x 8 bit configuration. An address on
lines AO-Al0 uniquely selects one by1e of ROM. Additionally,
address line A 11 and the chip selects are required to select the
ROM function on a given chip. In a system with multiple R6531 's,
the CS1, CS2, and CS3 mask options allow up to seven devices
with 14K bytes of ROM without the need for external decoding.

The chip select pins are also discrete 110 pins PB5, PB4, and
PD2. The pins are independent of each other in that anyone may
be used as a chip select. The user specifies as mask options
which pins are to be used as I/O and which as chip selects.

RAM-128 BYTES (1024 BITS)

40·PIN PROTOTYPING CIRCUIT

The X, Y, and Z bits may be selected as high, low or no effect.

The 128 x 8 static RAM of a given R6531 is addressed by lines
AO-A6. Additionally, address lines A7-All and chip selects CS1,
CS2, and CS3 provide selection of the RAM section of the device
as well as the device itself when additional RAM devices or
R6531's are in the system.

Prototyping circuits R6531-098 (1 MHz) and R6531-098A (2
MHz) are packaged in a 40-pin dual in-line package that has the
same pinouts as the 40-pin R6531 with PB6 option. In this
prototyping circuit, the ROM is disabled and there is no VRR
option. Access codes for this prototyping circuit are shown in
Table 2.

INPUT/OUTPUT

Table 2. R6531·098 Addressing

The input/output section is comprised of the data ports, direction
registers, counter and associated latches, control registers, and
interrupt registers. These I/O functions are all accessible by the
R6502 CPU's instruction set using address bits AO-A3 for the
specific function of the device. Address bits A4-A 11 and CS 1,
CS2, and CS3 additionally may be decoded to select a given
R6531 device in a multichip system.

R6531·09a
Function

Control Registers

N means No Effect, H means High and L means Low.

Chip
Selects

RAM
1/0

Two control registers allow software selection of various I/O functions. The Peripheral Control Register (PCR) is primarily associated with Port B functions and the Auxiliary Control Register
(ACR) is associated with the counter and serial data functions
which also affect Port B.

CS2 CS1
N
N

N
N

Address Inputs (AO . A 11)
11

10

9

7

sJ 5J 4J3J2J 1J 0

L
L

L
H

L N L
H H L

128 RAM Decode
LJ LJ LJ 1/0 Decode

8

52·PIN PROTOTYPING CIRCUIT
Prototyping circuits R6531-099 (1 MHz) amj R6531-099A (2 MHz)
are packaged in the 52-point quad in-line package, with VRR
option. PD2 is used as a chip select (GS3), and PB4 and PB5
are available as I/O lines. Access codes for the prototyping circuit are shown in Table 3.

ADDRESSING

Table 3. R6531·099 Addressing

Addressing of the R6531 offers many variations to the user for
system configuration flexibility. Combination with other R6531
ROMs, RAMs or I/O devices is possible without need for external
address decoding. Each of the three basic functions on the
device has its own decode mask for unique selection.

RS531·099

Function
ROM
RAM

The specific address ranges and chip selects are defined by the
user and are dependent on the number of chips in the system.
The programmed options to be fixed by masking are shown in
Table 1.

1/0

Chip
Selects

Address Inputs (AO·A 11)

CS3 CS2 CS1
H
N
N
L
N
N
L
N
N

11 10 191817161 51413 1211 10
H
2K ROM Decode
L L I Ll N ILl 128 RAM Decode
L Hj HjH j LjLj Lj Ljl/D Decode

The 128 words or RAM have been mapped into the first half of
both Page 0 and Page 1, to accommodate zero page addressing
and stack operations. The full I/O capabilities described for the
R6531 are available in the prototyping circuit, except that 1/0
lines PD2 and PD3 are dedicated to the VRR and GS3 mask
options.

2-72

ROM-RAM-I/O Counter (RRIOC)

R6531
REGISTERS
REGISTER SELECTION
The register selection and/or general operation performed by the
15 R6531 addresses in conjunction with the RtW state is shown
in Table 4.

Table 4. Register Selection
Hex
Addr

A3

0

L

L

L

L

Read Port A Data

Write Port A Data

1

L

L

L

H

Read Port B Data

Write Port B Data

Address Line
A2
A1

Operation
AO

R/W - Low

RIW - High

-

2

L

L

H

L

3

L

L

H

H

4

L

H

L

L

Read Lower Counter

Write Lower Latch

5

L

H

L

H

Read Upper Counter

Write Upper Latch and Download

6

L

H

H

L

7

L

H

H

H

8

H

L

L

L

Read Serial Data Register

Write Serial Data Register

9

H

L

L

H

Read Interrupt Flag Register

Write Interrupt Flag Register

A

H

L

H

L

Read Interrupt Enable Register

Write Interrupt Enable Register

B

H

L

H

H

Read Auxiliary Control Register

Write Auxiliary Control Register

C

H

H

L

L

Read Peripheral Control Register

Write Peripheral Control Register

0

H

H

L

H

E

H

H

H

L

-

Write Port C Data
Write Port 0 Data

-

Write Lower Latch
Write Upper Latch

Write Port A Data Direction Register
Write Port B Data Direction Register

Peripheral Control Register (PCR)

Auxiliary Control Register (ACR)

Some Port B operating options are software selectable by writing
control bits to the Peripheral Control Register (PCR).

Operating Modes for the Timer/Counter, PB2IPB3 Serial
input/output and PB4 pulse output are selected by writing bits
to the Auxiliary Control Register (ACR).

AUXILIARV CONTROL REGISTER (ACR)

I

SERIAL
CONTROL

I7

PERIPHERAL CONTROL REGISTER (PCR)

8

4

Lc-l

17185141'1'1'101
~

I•

I

COUNTER
CONTROL

3

I•I•I 0
~

PBO AND PBl CONTROL

COUNTER SOURCE SELECTION
00 1:1 COUNTER OFF
01 • EXTERNAL EVENT (PBS)

DO
STATIC I/O
01 .. PA HANDSHAKE

10,. PHASE 2
11 = PHASE 2, EXT TRIGGER LOW

=

1X • NEG EDGE DETECT

PULSE GENERATION CONTROL
o = PULSE OUTPUT OFF
1 • PULSE OUTPUT 011 (P84)

' - - - - - PB. AND PB3 CONTROL
o = STATIC 110
1

=

POS EDGE DETECT

FREE RUN CONTROL
O. ONE SHOT

' - - - - - - PBS CONTROL
0= STATIC 110
1 • iRa REQUEST

1 • FREE RUN
SERIAL CLOCK SOURCE
00 • SERIAL OFF

OUTPUT

I

' - - - - - - - - - - SPARE (UNUSED)

=

01

EXTERNAL CLOCK (P82)

'X = PHASE. CLOCK (PB2 OUT)

SERIAL DATA DIRECTION

o•
1

SERIAL IN (P83)

-= SERIAL OUT cPB3)

SPARE (UNUSED)

2-73

fJ

ROM-RAM-I/O Counter (RRIOC)

R6531

PERIPHERAL DATA PORTS

Interrupt Enable and Flag Registers

Each line of the 8-bit data Port A may be individually selected as
an input or output. Associated with the port is Data Direction Register- PortA (DDRA). Each line of the 7-bitdate Port B may be
individually selected as an input or an output. This port also has a
Data Direction Register (DDRB). The two data direction registers
(A and B) control the direction of the data into and out of the
peripheral pins. A "1" written into the Data Direction Register
sets up the corresponding peripheral pin as an outPllt. Therefore,
anything written into the data register will appear on that corresponding peripheral pin. A "0" written into the DDR inhibits the
output buffer from transmitting data from the data register. For
example, a "1" loaded into DDRA, position 3, sets up peripheral
pin PA3 as an output. If a "0" had been loaded, PA3 would be
configured as an input and would be in a float state.

Two registers are provided for interrupt control. Corresponding
bits in the enable and flag registers are logically ANDed to set the
Interrupt Request Pending flag. If the pending flag is set and PB6
is selected as an IRQ Request Output, then PB6 will be set low to
request the R6S02 CPU to service IRQ.
The interrupt enable bits are set or reset by writing into the Interrupt Enable Register. The interrupt flag bits IFRO-IFR6 can be
cleared directly by writing a byte to the flag register which has 1's
in those bit positions to be cleared.
IFR4 and IFRS may also be cleared by reading or writing the Port
A or Serial Data Registers respectively. IFR6 may also be
cleared by reading the lower counter with I/O address hex 4 writing the upper latch with I/O addresses hex S or 7.

Note that when lines in the PB port are used alternately as control
lines for other on-chip functions, Direction Register B must also
be loaded to set up the proper direction - the Control Registers
have no effect on data direction.

These registers and their bit assignments are illustrated.

The 8-bit Port C is an output only port. The 4-bit data Port D is an
input only port.
For those lines being used as outputs, the data registers are
used to latch data from the Data Bus during a Write operation so
the peripheral device can read the data supplied by the
microprocessor.
For the lines being used as inputs, the microprocessor is reading
the peripheral data pins. For the peripheral data pins which are
programmed as outputs the microprocessor will read the corresponding data bits of the Output data.

EDGE DETECT LOGIC
PBO NEGATIVE
EOGE DETECT

Operating in parallel with the I/O operation of PBO-PB3 is edge
detect logic that is enabled by Peripheral Control Register bits 1
and 2. PCR1 enables logic that upon detection of a negative
edge on PBO or PB 1 will set a corresponding flag in the Interrupt
Flag Register. PCR2 enables logic that upon detection of a positive edge on PB2 or PB3 will set corresponding flags in the Interrupt Flag Register. If corresponding bits are set in the Interrupt
Enable Register, then the Interrupt Request Pending flag will be
'
set.

PBl NEGATIVE
EDGE DETECT
PB2 POSITIVE
EDGE DETECT
PB3 POSITIVE
EDGE DETECT
PORT A NEEDS SERVICE
IN HANDSHAKE MODE
SERIAL REGISTER
FULUEMPTY, EXT. CLOCK

HANDSHAKE OPERATIONS

COUNTER OVERFLOW
INTERRUPT
REQUEST PENDING

PBO and PB1 may be used as handshake control lines for date
transmissions over Port PA; see PCR definition. PBO is a control
input, PB1 is a control output. PB1 switches low on a read or write
to Port PA, and switches high in response to a negative transition
on PBO.
IFR4 in the Flag Register is set by a negative transition on PBO,
and cleared by a Read or Write to Port PA; see Handshake Timing Diagram for timing details.

2-74

R6531

ROM-RAM-I/O Counter (RRIOC)

<1>2

ADDR

~

}

~

RiW

I

FR4

~

1

I

0

I

o

0

o

LOAD PA

o

i

0

o

PBO (IN)
PB1 (OUT)

o o

PBO SAMPLED
PA (DATA OUT)
IRQ

--~~==========~~------------~================~~-PB1 CONTROL
SET BY:
RESET,
WRITE PCR, OR
NEGATIVE TRANSITION ON PBO
RESET BY:
WRITE PORT PA
OR READ PORT PA

R6531 Timing for Handshake Mode

<1>2

ADDR
RiW

FRO, 1, 2, 3
IRQ
PBO, PB1

PB2, PB3

PB SAMPLED
(<1>2 LOW)

0

0

I

0

:r:~

NEG TRANSITIONS

POS TRANSITIONS

0 0

INTERRUPT FLAG REG. CONTROL

SET BY INPUT ACTIVE TRANSITIONS
RESET BY RESET OR WRITE "1"
TO CORRESPONDING IFR BIT

R6531 Timing for Interrupt Mode
2-75

R6531

ROM-RAM-I/O Counter (RRIOC)

SERIAL DATA CHANNEL
The R6531 has an s·bit serial channel. PB2 and PB3 are soft·
ware selectable as the serial clock (SClK) and serial data (SOlO)
lines respectively.

Auxiliary Control Register bit 6 sets the serial data direction. Data
are shifted in or out, most significant bit first, under control of the
shift clock.

The software sets Auxiliary Control Register bits 4 and 5 to ena·
ble the serial channel and to specify the source of the shift clock.
Selection of the Internal clock will shift data at one half the system
;2 clock rate. If the external clock is used, data may be shifted at
any rate up to one half the system ~2 clock rate. In the external
clock mode, the counter may be operated In the free .run pulse
generation mode using the CNTO line externally connected to the
SClK line to provide the desired shift rate.

In the external clock mode, the completion of eight shifts of the
serial register will set bit 5 of the interrupt flag register. If the cor·
responding bit of the Interrupt Enable Register is also set an
Interrupt'Request Pending flag will be set.

2

3

4

5

6

13

7

14

15

16

18

-:r:r.

AD DR (WRITE)

WA

RiW (WRITE) !,U.tA-~..u.1.LI.

flb

-0-

DATA BUS
(WRITE)

MSB

1 or 1"

SER DATA
SER elK
INPUT SMPl

17

I..._J

OJ

[]]

ADDR (READ)
RiW (READ)
DATA BUS (READ)

R6531 Serial I/O Timing

2·76

m

m

I

R6531

ROM-RAM-I/O Counter (RRIOC)

COUNTERITIMER
The R6531 contains a multi-mode 16-bit counter/timer with an
associated 16-bit latch whose modes are software selectable by
setting appropriate bits in the Auxiliary Control Register. The
latch holds the counter preset value and all 16 bits download to
the counter simultaneously upon command (I/O address hex 5)
of the software or automatically in free run modes upon overflow
of the counter. The counter is a decrementing counter and
causes the setting of a flag in the Interrupt Flag Register when it
overflows. This interrupt flag, bit 6, is logically ANDed with a corresponding counter overflow interrupt enabled bit to set the Interrupt Request Pending flag. The Auxiliary Control Register is used
to set four basic modes which specify the source of the count
information, and to select two mode modifiers that apply equally
to the three active modes.
Mode 0

-Counter Off

Mode 1

- Event Counter - counts external event
inputs (negative transitions) at PB5

Mode 2

-Interval Timer pulses.

- External Trigger - counts ~ system clock
pulses starting with a negative transition on
PB5.

Mode 3

Mode Modifier A -Pulse Generation Control - causes the
output level on PB4 to switch low each time
the counter is loaded using I/O address
hex. 5. At counter overflow, PB4 switches
high. If in the free run mode, PB4 continues
to toggle at each subsequent counter overflow; otherwise there are no further transitions until the counter is reactivated by the
software.
Mode Modifier B - Free-Run Control- causes the full 16-bit
latch to be downloaded to the counter, continues to count, and sets the counter overflow flag bit every time the counter
overflows. Otherwise the counter is a one
shot mode in which the counter overflow
flag is set one time only until the counter is
reactivated by the software.

counts 02 system clock

ADDR~

=4

lOAD TIMER

RiwL-J
COUNTER: ONE-SHOT
COUNTER: FREE-RUN
FRS: ONE-SHOT
FRS: FREE-RUN
PB4:

--,I

ONE-SHOT~
;,.~ _ _ _ _ _ _ _ _ _ _

PB4: FREE-RUN
IRa

COUNTER EXT STROBE
PBS

--,I

~\:>~ _ _ _ _ _ _ _ _ _ _

'&fj

\

4_1_'2'

_~
___
4 __

2

1

I

0

FF

FE

FD

2 ClK

COUNTEREXTClOCK~
______4_____
4~__I ____I __I__l __l_l
PBS

~

PBS SAMPLES @ 01

R6531 Counter/Timer Timing
2-77

MAX RATE

fI

R6531

ROM-RAM-I/O Counter (RRIOC)

BUS TIMING CHARACTERISTICS
R8531
(1 MHz)

R8531 A
(2 MHz)

Symbol

Min

Max

Min

Max

Unit

Tcyc

1.0

10

0.5

10

.,.s

Clock Pulse Width

Tc

470

-

235

ns

Rise & Fall Times

TR, TF

-

25

-

15

ns

-

120

-

ns

180

ns

10

-

ns

45D

ns

Characteristic
Clock Period

READ TIMING
RIW valid before positive transition of clock

TWCA

180

Address valid before positive transition of clock

TACR

180

Peripheral data valid before positive transition of clock

TPCR

270

Data Bus valid after positive transition of clock

TCDR

-

Data Bus Hold TIme

THR

10

iJiQ valid after negative transition of clock

T,c

-

900

-

120

350

-

120
135

-

ns
ns

WRITE TIMING

RiW valid before positive transition of clock

Twcw

180

Address valid before positive transition of clock

TACW

180

Data Bus valid before negative transition of clock

TDCW

270

Data Bus Hold TIme

THW

10

-

Peripheral data valid after negative transition of clock

Tcpw

-

900

NOTES:
Load

= 100 pF +
= 100 pF +
= 130 pF +

1 TIL for PAO-PA7, PBO-PB6, and PCO-PC7.
1 TIL for 00-07 (R6531A).
1 TTL for 00-07 (R8531).

2-78

120
135
10

-

450

ns
ns
ns
ns
ns

R6531

ROM-RAM-I/O Counter (RRIOC)

READ TIMING WAVEFORMS
TR
2

~ Tevc ~

L :1

-x

Tc

2.0V

rTF

Y1

o.~

2.OV

2.0V

RtW

~

0.4V

2.4V
ADDRESS
0.4V

2.4V

PERIPHERAL
DATA

DATA BUS

P87(IRQ)

0.4V
2.4V

-------<

=1"

--------------

0.4V
TIC

2.4V

~

~----------------

0.4V

WRITE TIMING WAVEFORMS

"2.4V
0.4V

2.4V
0.4V

2.4V
DATA BUS
0.4V
Vcc

----2.0V

PERIPHERAL
DATA

O.BV

2-79

-30%
2.4V
0.4V

fI

ROM-RAM-I/O Counter (RRIOC)

R6531
MAXIMUM RATINGS*
Rating

Symbol

Supply Voltage
Input Vollage
Operating Temperature Range
Commercial
Industrial

TA

Storage Temperature Range

Tstg

Value

Vee

Vdc

V,n

-0.3 to + 7.0

Vdc

DC CHARACTERISTICS
= 5.0V ±5% A,

(Vee 5.0V ±10%, Vee

Vss

o

to + 70
-40 to +85

°C
°C

-55 to + 150

°C

= 0,

TA

'Note: This device contains circuitry to protect the inputs against
damage due 10 high static voltages, however, normal precautions
should be taken to avoid application of any voltage higher than max·
imum rated voltages to this circuit.

Unit

-0.3 to 70

= TL to TH, unless otherwise

noted)

Symbol

Min

Max

Unit<'l

Input High Voltage

V,H

2.0

Vee

V

Input Low Voltage

V,L

-0.3

+0.8

V

Input Leakage Current
AO-A11, CS1-CS3, Rm,

liN

-

2.5

~A

Leakage Current for Three·State Off
(Three State) DO-D7, PAD-PA7, PBO-PB6

ITSI

-

±10

~A

Input High Current
PAO-PA7, PBO-PB6, PDO-PD3

I'H

-100

-

~A

= OV to 5.0V
= OV
V,N = O.4V to 2.4V
Vee = 5.0V
V,N = 2.4V

Input Low Current
PAO-PA7, PBO-PB6, PDO-PD3

I'L

1.6

-

mA

V,N

+2.4

-

Characteristic

RES",

2, PDO-PD3

Output High Voltage
DO-D7, PAO-PA7, PBO-PB6, PCO-PC7

VOH

Output Low Voltage
DO-D7, PAO-PA7, PBO-PB6, PCO-PC7

VOL

Output High Current (Sourcing),
PAO-PA7, PBD-PB6, PCD-PC7

10H

Output Low Current (Sinking)
PAD-PA7, PBD-PB7, PCD-PC7

10L

V

+04

V

V,N
Vee

= O.4V

Vee = 4.75V
ILOAD = - 200 ~A
Vee = 4.75V
ILOAD = 25 mA
VOH = 24V

-200
21

-

mA

VOL = 04V

20
10

pF
pF

Vcc = 5DV,
V,N = OV,
f = 1 MHz,
TA = 25°C

~A

Input Capacitance
2
LogiC

CCIk
C'N

Output Capacitance

COUT

10

pF

PD

10

W

Power DISSipation

Test Conditions

NOTES:
1 All Units are direct current (DC)
2 Negative sign Indicates current flow, positive Indicates Inward flow

2-80

R6531

ROM-RAM-I/O Counter (RRIOC)

PACKAGE DIMENSIONS
40-PIN DIP

q'

DOT OR NOTD
40 C
TO LOCATE

L

PIN NO , .

52-PIN PLASTIC QUIP

-----L-

0600 MAX
"624 M'v11

O~

j

01S5MAX
(393 MM)

2020 MAX
(5130 MM)

~[L .

~~~~~~==~
t
~"'~1 ass±-TT
I t:==.

0010 MIN

~

115 MAX

o 1002
eS1
eS2
RS
R/W

RES
DO
01
02
03
04
05
06
07
IRQ
PBO
PB1
PB2
PB3

R6532 Pin Configuration

= 1 MHz
A = 2 MHz

Data Sheet Order No. 042
Rev. 7, October 1984

Document No. 29000042
2-82

R6532

RAM-I/O-Timer (RIOT)

INTERFACE SIGNALS
RESET (RES)

ADDRESS LINES (AO-A6)

During system initialization, a low RES input causes a zeroing
of all four I/O registers. This In turn causes all I/O buses to act
as inputs thus protecting external components from possible
damage and erroneous data while the system is being configured under software control. The Data Bus Buffers are put into
an OFF-STATE dUring Reset. Interrupt capability is disabled with
the RES signal. The RES signal must be held low for at least
two clock periods when reset is required.

There are seven address pins (AO-A6). In addition, there is the
RAM SELECT (RS) pin. The pins AO-A6 and RS are always used
as addressing pins. There are two additional pins which are used
as CHIP SELECTS. They are pins CS1 and CS2. Tables 1 and 2
identify the functions selected and registers addressed depending
upon the address line and RS inputs in conjunction with the RtW
level.

READ/WRITE (Rm)

1/0 PORTS (PAO- PA7, PBO- PB7)

The Riw signal is supplied by the microprocessor and controls
the transfer of data to and from the R6532. A high on the Riw
pin allows the processor to read (with proper addressing) the
data supplied by the R6532. A low on the R/W pin allows a write
(with proper addressing) to the R6532.

The R6532 has 16 pins available for peripheral I/O operations.
Each pin is indiVidually software programmable to act as either
an input or an output. The 16 pins are divided Into two 8-bit
ports, PAO-PA7 and PBO-PB7. (PA7 also has another use
which IS discussed later.) Each is set up as an input by writing
a "0" Into the corresponding bit of the data direction register. A
"1" written Into the data direction register causes ItS corresponding bit to be an output. When In the input mode, the
peripheral output buffers are in the "1" state and the internal
pull-up device acts as less than one TTL load to the peripheral
data lines. On a Read operation, the microprocessor reads the
peripheral pin. When the peripheral deVice gets Information
from the R6532 It receives data stored in the data register. The
rnicroprocessor reads valid pin information If the peripheral lines
are greater than 2.0 volts for a "1" and less than 0.8 volt for a
"0" as the peripheral pins are all TTL compatible. Pins PBOPB7 are also capable of sourcing 3 ma at 1.5V, thus making
them capable of Darlington drive.

INTERRUPT REQUEST (IRQ)
The IRQ pin is an interrupt pin from the interrupt control logiC.
The pin will be normally high with a low Indicating an Interrupt
from the R6532. An external 3K pull-up resistor is required. The
IRQ pin may be activated by a transition on PA7 or timeout of
the interval timer.

DATA BUS (DO - 07)
The R6532 has eight bidirectional data pins (00-07). These pins
connect to the system's data lines and transfer data between the
R6532 and the microprocessor data bus. The output buffers
remain off, or tri-stated, except when the R6532 is selected for
a Read operation.

00-07

<

(8)
(8)

AO-A6

PAO-PA7

(10)

_2
R6500
MICROPROCESSOR
BUS
INTERFACE

R6532
RIOT

Rm

PERIPHERAL
INTERFACE

CS1
(8)
CS2

AS

RES

l

IRQ 4

I

I

RIOT Interface Signals

2-83

PBO-PB7

PI

R6532

RAM-I/O-Timer (RIOT)

Table 1. Address Decoding
RS

R!W

Write RAM
Read RAM

0
0

0
1

Write Output Reg A
Read Output Reg A

1
1

0
1

WriteDDRA
Read DDRA

1
1

0
1

Write Output Reg B
Read Output Reg B

1
1

0
1

WriteDDRB
Read DDRB

1
1

0
1

1
1
1
1
1
1
1

0
0
0
0
1
1
0

Operation

A4

A3

A2

A1

AO

-

-

-

-

-

0
0

0
0

0
0

0
0

0
0

1
1

-

0
0

1
1

0
0

0
0

1
1

1
1

1
1
1
1
1
1
1

0
0
1
1

0
1
0
1
0
1
(c)

-

-

-

-

-

Write Timer

-1T
-8T
-64T
.1024T
Read Timer
Read Interrupt Flag
Write Edge Detect Control

1
1
1
1

(a)
(a)
(a)
(a)
(a)

-

-

-

0

(b)

Notes:
- ~ Don't Care, "1" ~ High level (;.2.4V), "0" ~ Low level ("'0.4V)
(a) A3 ~ 0 to disable Interrupt from timer to IRQ
A3 ~ 1 to enable Interrupt from timer to IRQ

(c) AO ~ 0 for negative edge-detect
AO = 1 for positive edge-detect

(b) A1 = 0 to dISable Interrupt from PA7 to IRQ
A1 ~ 1 to enable Interrupt from PA7to IRQ

Table 2.
Start
Address
$0
$1
$2
$3
$4
$4
$5
$5
$6

+

Register Addressing
Start
Address

Reglater/Function
DRA ('A' side data register)
DDRA ('A' side data direction register)
DRB ('B' side data register)
DDRB ('B' side data direction register)
Read timer (disable Interrupt)
Write edge-detect control (negative edge-detect,
disable Interrupt)
Read interrupt flag register (bit 7 ~ timer, bit 6 =
PA7 edge-detect) Clear PA7 flag
Write edge-detect control (poSitive edge-detect,
disable interrupt)
Write edge-detect control (negative edge-detect,
enable interrupt)

$7
$C
$14
$15
$16
$17
$lC
$lD
$lE
$lF

2-84

+

Register/Function
Write edge-detect control (positive edge-detece,
enable Interrupt)
Read timer (enable interrupt)
Write timer (divide by 1, disable Interrupt)
Write timer (divide by 8, disable interrupt)
Write timer (divide by 64, disable Interrupt)
Write timer (divide by 1024, disable Interrupt)
Write timer (divide by 1, enable Interrupt)
Write timer (divide by 8, enable interrupt)
Write timer (diVide by 64, enable interrupt)
Write timer (divide by 1024, enable interrupt)

R6532

RAM-I/O-Timer (RIOT)

INTERNAL ORGANIZATION
The R6532 is divided Into four basIc sections, RAM, 110, Timer,
and Interrupt Control. The RAM Interfaces directly with the
microprocessor through the system data bus and address lines.
The I/O section consists of two 8-bit halves Each half contains
a Data Direction Register (DDR) and a Data Register (DR).

Data IS read directly from the data pins during any read operation. For any output pin, the data transferred into the processor
will be the same as that contained in the Data Register if the
voltage on the pin IS allowed to go to 2.4V for a logic one. Note
that for input lines, the processor can write into the corresponding bit of the Data Register. This will not affect the polarity
on the pin until the corresponding bit of DDRA is set to a logic
one to allow the I/O line to act as an output.

RAM-128 BYTES (1024 BITS)
The 128 x 8 Read/Write Memory acts as a conventional static
RAM and can be accessed from the microprocessor by selecting
the chip (CS1 = high, CS2 = low) and by setting RS low.
Address lines AO through A6 then select the desired byte of
storage.

The operation of the Port B IS exactly the same as the normal
110 operation of the Port A. Each of the eight lines can each be
programmed to act as either an input or as an output by placing
a 0 or a 1 Into the Port B Data Direction register (DDRB). In the
output mode, the voltage on a peripheral pin IS controlled by the
Port B Data Register (DRB).

I/O PORTS AND REGISTERS

The primary difference between Port A and the Port B is in the
operation of the output buffers which drive these pins. The Port
8 output buffers are push-pu!1 deVices which are capable of
sourcing 3 ma at 1.5V This allows these pins to directly drive
transistor sWitches. To assure that the microprocessor Will read
proper data on a "Read Port B" operation, logic In the R6532
allows the microprocessor to read the Output Register Instead
of reading the peripheral pin as on Port A.

The 1/0 Ports consist of eight lines which can be individually programmed to act as either an input or an output A logiC zero In
a bit of the Port A Data Direction Register (DDRA) causes the
corresponding line of Port A to act as an input. A logic one
causes the corresponding Port A line to act as an output. The
voltage on any line programmed to be an output IS determined
by the corresponding bit In the Port A Data Register (DRA).

PA7 PBO

PAO

DATA
DIRECTION
REGISTER

DATA
REGISTER

A

A

DATA
BUS
BUFFER

r---.

l---t

l- ---t

PERIPHERAL
DATA BUFFER

PERIPHERAL
DATA BUFFER
B

D7

AO

A

CHIP
SELECT
R/W

ADDRESS
DECODER

t- ---l 1- --t

DO

1
CS2

AS
RS

PB7

128 x 8
RAM

t

~

INTERRUPT
CONTROL

1t

R/W

IRQ RES

CS1

R6532 Block Diagram

2-85

DATA
DIRECTION
REGISTER
B

DATA
REGISTER
B

1--

INTERVAL
TIMER

RAM-I/O-Timer (RIOT)

R6532
EDGE DETECTING WITH PA7
In addition to acting as a peripheral I/O line, the PA7 line can
be used as an edge-detecting input. In this mode, an active transition sets the internal interrupt flag (bit 6 of the Interrupt Flag
register). Setting the interrupt flag causes IRQ output to go low
if the PA7 interrupt has been enabled.

During system initialization, the interrupt flag may inadvertently
be set by an unexpected transition on the PA7. It is therefore
recommended that the interrupt flag be cleared before enabling
interrupting from PA7. To clear PA7 interrupt flag, simply read
the interrupt Flag Register.

Control of the PA7 edge detecting mode is accomplished by
writing to one of four addresses. In this operation, AO controls
the polarity of the active transition and A1 acts to enable or disable interrupting of the processor. The data which is placed on
the Data Bus during this operation is discarded and has no
effect on the control of PA7.

The Timer section of the R6532 contains three basic parts: preliminary divide down register, programmable 8-bit register and
interrupt logic.

INTERVAL TIMER

The Timer can be programmed to count up to 255 time intervals.
Each time interval can be either 1T, 8T, 64T or 1024T increments, where T is the system clock period. When a full count
is reached, an interrupt flag is set to logic" 1". After the interrupt
flag is set the internal clock begins counting down al'lhe system
clock rate to a maximum of -255T. Thus, after the interrupt flag
is set, a Read of the timer will tell how long since the flag was
set up to a maximum of 255T.

The PA7 interrupt flag is set on an active transition, even if the
pin is being used as a normal input or as a peripheral control
output. The flag is also set by an active transition if the PA7
interrupt is disabled. The reset signal (RES) disables the PA7
interrupt and enables negative (high-to-Iow) edge detection on
PA7. The PA7 edge detect logic can be set to detect either a
positive or negative transition and to either enable or disable
interrupt (IRQ) generation upon detection.

A3

R/W

DIVIDE

INTERRUPT
CONTROL

07

06

AO

Al

DOWN

04

02 DO

Basic Elements of Interval Timer

2-86

<1>2

R6532

RAM-I/O-Timer (RIOT)

INTERVAL TIMER EXAMPLE
The 8-bit microprocessor data bus transfers data to and from
the Timer. If a count of 52 time intervals were to be counted,
the pattern 0 0 1 1 0 1 0 0 would be put on the data bus and
written into the divide by 1 Timer register.

Value read = 1 1 1 0 0 1 0 0
Complement = 0 0 0 1 1 0 1 1
ADD 1
= 0 0 0 1 1 1 0 0 =
=0001

SUB 1

At the same time that data is being written to the Timer, the
counting intervals of 1, 8, 64, 1024T are decoded from address
lines AO and A 1. During a Read or Write operation address line
A3 controls the interrupt capability of PB7, I.e., A3 = 1 enables
IRQ, A3 = 0 disables IRQ. When the timer IS read prior to the
interrupt flag being set, the number of time intervals remaining
will be read, i.e., 51, 50, 49, etc.

Thus, to arrive at the total elapsed time, merely do a two's complement add to the original time written into the timer. Again,
assume time written as 0 0 1 1 0 1 0 0 (=52). With a divide
by 8, total time to Interrupt is (52 x 8) + 1 = 417T. Total elapsed
time would be 416T + 27T = 443T, assuming the value read
after interrupt was 1 1 1 0 0 1 0 O.
The interrupt flag will be reset whenever the Timer is accessed
by a read or a write. However, the reading of the timer at the
same time the interrupt occurs will not reset the interrupt flag.
When the Interrupt flags are read (07 for the timer, 06 for the
edge detect) data bus lines 00-05 go to O.

When the Timer has counted through 0 0 0 0 0 0 0 0 on the
next count time an interrupt will occur and the counter will read
1 1 1 1 1 1 1 1. After the interrupt flag is set, the timer register decrements at a divide by "1" rate of the system clock. If
the timer is read after the interrupt flag is set and a value of
1 1 1 0 0 1 0 0 is read, the time since interrupt is 27T. The
value read is in two's complement, but remember that Interrupt
occurred on count number one. Therefore, we must subtract 1.

COUNTER CONTENTS

a

I

r

N·1

v

-I

r;; !"ill 191 1161
L.J ' I< ~ L.J " ..... f.l

IQ1

02 PULSE NUMBER .....J

P Tc
N·2

v

When reading the timer after an interrupt, A3 should be low so
as to disable the m pin. This is done so as to avoid future
interrupts until after another Write timer operation.

I

a

I

255

r4l

PRE-SCALE OUTPUT

254

I

253

r;1

9

WRITE TIMER

I

I

m r;1 I"4l m m n
L.J a I.; rJ ~ L.J a l; t-l ~ L.J; L.J ; L.J 1 l; ~

11

.v ..... '"'

011=

28 Equals two's complement of register
27

8

9

I

I

64

f5l

L.J

6 L.JI ILa

....flL-_____________________________
P Tc· Tc/2

::=fI...__. . n
. . . ____. . nL.
. ___rLJ
NPTC+Tc/2---:j

INTERRUPT FLAG (BIT

7)'---------------------1

READ TIMER _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~nl-

Notes:
Assume 52 Loaded into Timer with a divide by 8.
The Counter Contents and the Clock Pulse Numbers will coincide.
Prescale, P = 8.
Cycle Time, T c = 1 ~sec (for 1 MHz)
Count, N = 52

Interval Time Example Waveforms

2-87

________

fJ

RAM-I/O-Timer (RIOT)

R6532
BUS AND PERIPHERAL TIMING WAVEFORMS
READ TIMING

j112

24 V

ADDRESS
CS, RS, ETC

4V
24 V

O.4V

24V
04V

24 V
DATA
BUS

04V

WRITE TIMING

1'---------'1

0,8 V

ADDRESS,
RS, ETC

es,

Rffl

PERIPHERAL
DATA
~~---------------04V

DATA
BUS

2-88

R6532

RAM-I/O-Timer (RIOT)

AC CHARACTERISTICS

Characteristic
Clock Cycle T,me
Clock Pulse Width
Rise & Fall TImes

Symbol

R6532

R6532A

(1 MHz)

(2 MHz)

Min

Max

1

10

Tcyc
Tc

470

TR• TF

-

25

Max

Unit

10

p,s

240

-

ns

-

15

ns

ns

Min
0.5

READ TIMING

-

90

180

-

90

-

-

395

-

190

ns

-

ns

Address Set Up Time

TACR

180

Address Hold Time

TCAR

0

RIW Set Up TIme

TWCR
TCOR

Data Bus Delay TIme
Data Bus Hold TIme

THR

Penpheral Data Set Up TIme

TPCR

0

10

-

10

300

-

150

ns
ns

ns

WRITE TIMING
1112 Cycle TIme

Tcyc

1112 Pulse Width

Tc

470

Address Set Up Time

TACW
TCAH

Address Hold TIme
R!W Set Up TIme
R!W Hold TIme
Data Bus Set-Up Time
Data Bus Hold TIme

1

10

p,s
ns

90

-

-

0

-

ns

90

ns

10

-

10

240

180
0

Twcw

180

TCWH

0

Tocw

200

-

10

-

THW

0.5

-

0
90

Peripheral Data Delay TIme

TcPN

-

1

Penpheral Data Delay TIme CMOS

TCMOS

-

2

2-89

-

ns

ns
ns
ns

0.5

p,s

1

p,s

PI

R6532

RAM-I/O-Timer (RIOT)

MAXIMUM RATINGS*
Symbol

Value

Unit

Supply Voltage

Vee

-0.3 to +7.0

Vdc

Input Voltage

V ,N

-0.3 to +7.0

Vdc

Operating Temperature
Commercial
Industrial

TA

Storage Temperature

TSTG

Parameter

o

to +70
-40 to +85

"C
"C

-55to+150

"C

"NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

DC CHARACTERISTICS
(Vee

= 5.0

= TL to TH unless otherwise noted)

±5%, TA

Min

Max

Unlt(')

Input High Voltage

V,H

2.4

Vee

V

Input Low Voltage

V,L

0

0.4

V

Input Leakage C.!!!re~
AO-A6, RS, RIW, RES, \lI2, CS1,C82

liN

-

2.5

jJ.A

Y'N = OV to 5.0V
Vee = OV

Input Leakage Current lor Three-State Off
00·07

ITS1

-

±10

jJ.A

Y'N = O.4V to 2.4V

Input High Current
PAO-PA7, PBO-PB7

I'H

jJ.A

V,H = 2.4V

Input Low Current
PAO-PA7, PBO-PB7

I'L

mA

Y'N = O.4V

Output High Voltage
PAO-PA7, PBO-PB7 (TIL drive), 00-07
PBO-PB7 (other than TIL drive, e.g., Darlington)

VOH

Output Low Voltage
00-07

VOL

Parameter

Symbol

Output High Current (Sourcing)
PAO-PA7, PBO-PB7 (TIL drive), 00-07
PBO-PB7 (other drive, e.g., Darlington)

IOH

Output Low Current (Sinking)
PAO-PA7, PBO-PB7

IOL

-100

-

-16

2.4
1.5

-

-

0.4

V

Vee = 4.75V
ILOAD = -100 jJ.A
ILOAD = 3 mA

V

Vee = 4.75V
ILOAD = 1.6 mA

-100
-3.0

-

jJ.A
mA

VOH = 2.4V
V OH = 1.5V

1.6

-

mA

VOL

30
10

pF
pF

Input Capacitance
\lI2
Other

C 'N

-

Other Capacitance

COUT

-

10

pF

Po

-

1000

mW

Power Dissipation

-

COLK

Notes:
1. All units are direct current (~C).
2. Negative sign indicates outward current flow, positive indicates inward flow.

2-90

Test Conditions

= O.4V

Vee = 5.0V
Y'N = OV
1= 1 MHz
TA = 25"C
TA

= O°C

R6532

RAM-I/O-Timer (RIOT)

PACKAGE DIMENSIONS
4()"PIN CERAMIC DIP

[:

It-o--~

iF

[~
_ A

]I]

DIM

A
B
C

INCHES
MIN
MAX

N

50.29 51.31
14.86 15.62
2.54 4.19
038 053
076 140
254 esc
076 178
020 033
254 419
1460 1537
0"
10"
051
152

DIM

MILLIMETERS
INCHES
MIN MAX
MIN
MAX

D
F
G
H
J

.1

MILLIMETERS
MIN MAX

K
L

M

1980
0.585
0100
0.015
0.030
0100
0030
0008
0.100
0575
O·
0020

2020
0.615
0.165
0.021
0055

esc
0070
0013

0165
0605
10·
0060

40·PIN PLASTIC DIP

A
B
C
D
F

G
H
J

K
L
M
N

2-91

5128
1372
355
036
102
254
165
020
305

5232
1422
508
051
152

2040
0540
0140
0014

0040
0100
216 0065
030 0008
356 0120
1524 BSC
0600
10"
051
102 0020

.,.

esc

.,.

2060
0560
0200
0020
0060

esc

0085
0012
0140

esc
10'
0040

R6541 Q • R6500/41 , 142, 143
R6500 Microcomputer System

'1'

Rockwell

R6541Q, R6500/41, R6500/42 & R6500/43
ONE-CHIP INTELLIGENT
PERIPHERAL CONTROLLER

INTRODUCTION

FEATURES

The Rockwell R6541Q, R6500/41, R6500/42 and R6500/43
One-Chip Intelligent Peripheral Controllers (IPC) are general
purpose, programmable interface I/O devices designed for use
with a variety of 8-bit and 16-bit microprocessor systems.

• Directly compatible with 6500, 6800, 8080, and Z80 bus
families
• Asynchronous Host interface that allows independent clock
operation
• Input, Output and Status Registers for CPU/Host data transfers
• Interrupt or polled data interchange with Host
• Enhanced 6502 CPU
-Four new bit manipulation Instructions:
Set Memory Bit (SMB)
Reset Memory Bit (RMB)
Branch on Bit Set (BBS)
Branch on Bit Reset (BBR)
-Decimal and binary arithmetic modes
-13 addressing modes
- True indexing
• 1.5K, 256 or zero bytes mask-programmable ROM

NOTE

This document describes four Intelligent Peripheral Controller devices. In the text, the terms IPC or device Will be
used when describing all parts. The few differences will
be described in the text uSing the terms R6541Q,
R6500/41, R6500/42, or R6500/43.
The one-chip R6500/41 IPC has an enhanced R6502 CPU,
1.5K by 8-bit ROM, 64 by 8-bit RAM, three I/O ports with mUltiplexed special functions, and a multi-function timer all contained within a 40 pin package.
For systems requiring additional I/O ports, the device is also
available in a 64-pin QUIP version, R6500/42, that provides
three additional 8-bit ports.

•
•
•
•

Another 64 pin QUIP version, R6500/43, is functionally equivalent to the R6500/41 except 4K addresses and a data bus are
provided on pins, and the ROM size is optionally 256 or 0 bytes.
The R6541Q, also a 64 pin QUIP version, is functionally identical to the R6500/43 except it has no options. The part has no
ROM and no port pull-up resistors. It can be used as an IPC
microprocessor or as an emulator for the family.

64-byte static RAM
47 TTL-compatible I/O lines (R6500/42)
23 TTL-compatible I/O lines (all others)
A 16-bit programmable counter/timer, with latch
-Pulse width measurement
-Pulse generation
-Interval timer
-Event counter

• Seven interrupts
- Two edge-sensitive lines: one positive, one negative

In all versions, special interface registers allow these IPC deVices
to function as peripheral controllers for the 6500, 6800, Z80,
8080, and other 8-bit or 16-bit host microcomputer systems. The
innovative architecture and the demonstrated high performance
of the R6502 CPU, as well as the instruction simplicity results
in system cost-effectiveness and a wide range of computational
power. These features make the device a leading candidate for
IPC computer applications.

•
•
•
•

-Reset
-Counter
-Host data received
-Output Data Register full
-Input Data Register empty
Multiplexed bus expandable to 4K bytes of external memory
Unmultiplexed bus for Peripheral I/O expansion
68% of the instructions are executed In less than 2/Ls at 2
MHz
NMOS-3 silicon gate, depletion load technology

• Single +5V power supply
• 40-pin DIP (R6500/41)
• 64-pin QUIP (all others)

Document No_ 29000095

Data Sheet Order No. 095
Rev. 1, February 1983
2-92

R6541Q. R6500/41, /42, /43

One-Chip Intelligent Peripheral Controller
MASK OPTIONS

Rockwell supports development of the R6500/41, R6500/42,
and R6500/43 with the System 65 Microcomputer development System and the R6500/* Family of Personality Modules. Complete in-circuit emulation with the R6500/* Family
of Personality Modules allows total system test and evaluation.

The R6500/41 provides for internal pull-up resistors on PA
and PC ports as a mask option. This option is available for
port groups only, not for individual port lines.
The R6500/42 has provision for pull-up resistors on PA, PC,
PF, and PG ports as a mask option. This option is available
for port groups only, not for individual port lines.

This document is for the reader familiar with the R6502 CPU
hardware and programming capabilities. A detailed description of the R6502 CPU hardware is included in the R6500
Microcomputer System Hardware Manual (Order Number
201). A description of the instruction capabilities of the R6502
CPU is contained in the R6500 Microcomputer System Programming Manual (Order Number 202).

The R6500/43 allows for 256 Bytes of ROM or no ROM, the
Reset vector at FFFC or OFFC, and pull-up resistors on PA
and PC ports as independent mask options. The port resistor
options are available for port groups only, not for individual
port lines.

Additional information on the devices can be obtained from
the R6500/41 and R6500/42 Product Description (Order
Number 2135) and the R6500/43 and R6541Q Product
Description (Order Number 2136).

The R6541Q has no options. It is configured with no ROM,
Reset vector at FFFC, and no pull-up resistors.

R6500/41 and R6500/42. The R6500/43 has an oplional256
by1es of ROM at address space OFOO to OFFF. The R6541 Q
has no ROM.

FUNCTIONAL DESCRIPTION
The internal CPU or the device is a standard R6502 configuration with the standard R6502 instructions, plus four new
bit manipulation instructions. These new bit manipulator
instructions form an enhanced R6502 instruction set and
improve memory utilization efficiency and performance.

Random Access Memory (RAM)
The RAM consists of 64 bytes of read/write memory with an
assigned page zero address of 0040 through 007F.

Set Memory Bit (SMB #,ADDR.)

System Clock

This instruction sets to "1" one bit of the 8-bit data field specified by the zero page address (memory or I/O port). The first
byte of the instruction specifies the 5MB operation and which
one of the eight bits to set. The second byte of the instruction
designates the address (0-255) of the byte or the I/O port to
be operated on.

The device functions with an external clock. It is fully asynchronous in reference to the Host computer timing. The
device clock frequency equals the external clock frequency.
It is also made available for any external device synchronization at pin ¢2.

Reset Memory Bit (RMB #,ADDR.)

Parallel Input/Output Ports

This instruction has the same operation and format as the
5MB instruction except that a reset to "0" results.

All of the devices except the R6500/42 have 23 I/O lines
grouped into three ports (PA, PB, PC). Ports A and C may
be used either for input or output individually or in groups of
any combination. Port B may be used as all inputs or all
outputs.

Branch on Bit Set Relative (BBS #,ADDR.,DEST)
This instruction tests one of the eight bits designated by a
3-bit immediate field within the first byte of the instruction.
The second byte designates the location of the byte or I/O
port to be tested within the zero page address range. The
third byte of the instruction specifies the 8-bit relative address
that the instruction will branch to if the tested bit is a "1". If
the bit tested is not set, the next sequential instruction is
executed.

Port A (PA)
Port A can be programmed as a standard parallel 8-bit I/O
port or, under software control, as a counter I/O line or positive and negative edge detects.

Port B (PB)
Port B can be programmed as an I/O port.

Branch on Bit Reset Relative
(BBR #,ADDR.,DEST)

Port C (PC)

This instruction has the same operation and format as the
BBS instruction except that a branch occurs if the bit tested
is a "0".

Port C has seven pins and can be programmed as an I/O
port.

Read Only Memory (ROM)

The R6500/42 has all of the above ports A, B, and C, plus
three extra ports (PE, PF, PG). Port E is outputs only. Ports
F and G are bidirectional in any combination.

Ports E, F, and G (PE, PF, & PG) R6500/42 only

The ROM consists of 1536 bytes of mask programmable
memory with an address space from FAOO to FFFF for the

2-93

2

R6541Q. R6500/41, /42, /43

One-Chip Intelligent Peripheral Controller

Host Computer Interface

Counter/Latch Logic

The device will wOrk with a variety of Host Computers. The
HOST interface consists of a chip select, one address line,
two control lines, and an 8-bit 3-state data bus. Internal logic
(controlled by MCR4) configures the address and two control
lines to either a 6500 or 8080 operational methodology. The
interface is completely asynchronous and will work with a
Host Computer up to a 5 MHz bus transfer rate. The device
clock input frequency need not be the same as the Host's.
A mode control register is set to match the interface to that
of the Host device as follows:

The device contains a l6-bit counter and a l6-bit latch
associated with it. The counter can be independently programmed to operate in one of four modes:
Counter
• Pulse width measurement
• Pulse Generation
• Interval Timer
• Event Counter

Mode Control Register (MCR)

The device has an 8-bit Input Data Register (lOR) and an 8bit Output Data Register (ODR). The lOR serves as a temporary storage for commands and data from the Host to the
device.

The Mode Control Register contains control bits for the multifunction I/O ports, mode select bits for the Counter, and a
selection bit for the type of Host interface.

The ODR serves as a temporary storage for data from the
device to the Host.

Interrupt Flag Register (IFR)
and Interrupt Enable Register (IER)
The device includes an Interrupt Flag Register and an Interrupt Enable Register which flags and controls I/O and counter
status.

A Host Status Flag Register facilitates a software protocol
that permits independent and uninterrupted flow of data
asynchronously between the Host Computer and the device.
The Host Status Flag Register contains eight flag bits that
can be read at any time by either the Host or the device.

R6500{43

elK IN

REs

RES

V,,

v,.

co
AO(RS)
ECAli)

PORTB

V"

PAD-PA7
(PAQ-PED)

PORTA

PAQ·PA7
(PAD-PED)

(PA1-NED)

(PA1-NED)

(PA2-CNTR)

(PA2-CNTR)

<===> ~D~!o~~ TRI.STATE)·

RJW (Viii)

PCo-PC6

PCo-PC6

~A1,A2,A3,

~~~;~,2iN~~

EMS, RIW, INT)*

PEO-PE7

PGo-PG7

Darlington Output Only

PORT F

RJW

~.M"'U'-:LT:::'P-LE"'XE=O-'O"'PT::::'O"'N---......J--

I
.

'----~

SYNC

R6500/42

NM'

* MULTIPLEXED OPTION

2-94

<==> PFo.PF7

I......,..
o

•

MEMORY MAP

I

~.....

R6500/41 AND R6500/42
NORMAL BUS MODE

ABBREVIATED BUS MODE

FFFE I

IRO VECTOR

FFFE

FFFC

RES VECTOR

FFFC

I

MULTIPLEXED BUS MODE

IRO VECTOR

FFFE

RES VECTOR

FFFC
FFFA

FFFA
FAOO

FAOOI

RIII41 a R8500/43

(WID BOOT STRAP ROM)

IRO VECTOR

FFFE

IRO VECTOR -

FFFE

IRO

RES VECTOR

FFFC

(OP RESET VECTOR)

FFFC

RES

FFFA

NMI VECTOR

FFFA

NMI

ROM (1.5KI

ROM (1.5KI

ROM U.5KI

I

R&50O/43

(W/BDOT STRAP ROM)

I

~
~

w

4K
USER
PROGRAM

FAOO
4K
USER PROGRAM
FOOOI

FOOO

INTERNAL REGISTERS
READ
RESERVED

RESERVED

~

I

NOT AVAILABLE

I

RESERVED

f

lOFF
I

o
::;

PERIPHERAL

«
>

ADDRESSES

I~

U6)

iOl00
007F

007F

'"~

& REGISTERS
-

0040

0000

0000

-

Mode Control H80.
Interrupt Enable Reg.

Reed FF

elr Interrupt Flag Reg.

00

,oo

00
00

:::I

110
110

00
OQ
00

::r
ii"

110
110
110

S"

~

.

CD

OIIOF
NOT AVAILABLE

1/0 PORTS E. F. G
(R65II0/42 ONLY)
NOT AVAILABLE
VO POR1 C

va POR1 B
va POR1 A

110 & REGISTERS

0000

UDDe,lmbA

Interrupt Enable Reg.
Interrupt Flag Reg.

RESERVED

110 & REGISTERS

110 & REGISTERS

Upper latthA* #

--

00lF

001F

00lF

--

lower Latch A

Mode Control Reo.

I
I

0040
RESERVED

RESERVED

nUI.u~ Host 8us Buffer 00

I
INTERNAL
RAM (64)

INTERNAL
RAM (64)

InDul Host BIIS 8u"'"

--

I
I

EXTERNAL
MEMORY
4056 -128

0080I
007F

007F
INTERNAL RAM (64)

110 & REGISTERS

0000

BOOT STRAP
ROM (256)

0100

0040

00lF

00lF

OFOO

HBB Status RegISter

--

I

RESET VECTOR

ADDRESS

-HBB salUs Register

Lower Counter A
lower Counter A#
Upper Counter A

I

OFF F

NOT
AVAILABLE

RESERVED

RESERVED

0000

EXTERNAL MEMORY
4096-128

>

LOl00
007F

0040

)/0

.

OFFC
OFFB

o
::;

INTERNAL RAM (64)

INTERNAL RAM (64)

0040

1000
OFFF

WRITE

--

-

*- AND START COUNTER
/I

CLEAR FLAG

0007
0006

0004
0003
02

0000

-

'fit

a

..'I

-6"

i

e.o

o

a

a

•

..

ii'

One-Chip Intelligent Peripheral Controller

R6541Q. R6500/41, /42, /43

KEY REGISTER SUMMARY
CPU Registers

Processor Status Register

---'I

" -_ _--'C_ _ _

[N[V[

ACCUMULATOR

o

'o----'--------!J
'o------"------'J

15

---!J

~I__--'p'-'Cc:"'---_ _'---,O-_ _-'-P;:CL::..-_ _

,O-_ _ _S_p_ _ _---'I

BiOi 'iZ

1

INDEX REGISTER X

PROGRAM COUNTER

1

C1

L:

INDEX REGISTER Y

PC

STACK POINTER

o

IN I V I 18 I 0 I I I z 10 I PROCESSOR STATUS REG

CARRY (el (1)

Carry Set

1
o

Carry Clear

Zero(Z) (1)
1

Zero Result

o

Non-Zero Result

INTERRUPT DISABLE (I) (2)
P

IRQ Interrupt Disabled
IRQ Interrupt Enabled

1
o

DECIMAL MODE (0) (1)
1
o

MCR

I

,J,

I
o

o

0

o

NOT USED

1

o

BUS SELECT

1

Break Command

Non·Break Command

1

Overflow$-el

o

Overflow Clear

NEGATIVE (N) (1)

NOTES
(1) Not ,mtJalized by RES
(2) Set to LogiC 1 by RES

1

COUNTER
SELECT MODE

BUS MODE

1

o

OVERFLOW (V) (1)

AOOR 0014

o

Binary Mode

BREAK COMMAND (B) {1l

Mode Control Register

I

DeCimal Mode

1

Negative Value
Positive Value

o

INTERVAL TIMER
PULSE GENERATOR
EVENT COUNTER
PULSE WIDTH MEASUREMENT

Interrupt Enable and Flag Registers

6500/6800 BUS

1 = ZaO/BOaa BUS

INT SELECT

o~
1

PC6

IER

-TNT

ADOR 0012

PORT B ALL INPUTS

1 PORT B ALL OUTPUTS

o

ABBREVIATED BUS MODE
1 MULTIPLEXED BUS MODE

ADDR 0011

Host Status Flag Register

HSFR

PAO POSITIVE
EDGE DETECT
INTERRUPT ENABLE

ADDR 00lE

PAl NEGATIVE
EDGE DETECT
INTERRUPT ENABLE
INTERNAL INTERRUPT
REQUEST INTERRUPT ENABLE
EXTERNAL INTERRUPTS REQUEST 1,
INT-l ENABLE

INPUT DATA REGISTER
FULL FLAG

EXTERNAL INTERRUPT REQUEST 2,
INT-2 ENABLE
COUNTER UNDERFLOW
INTERRUPT ENABLE

OUTPUT DATA REGISTER
FULL FLAG

COPIES RS ON
WRITE FROM HOST

Host Addressing Matrix
RS (Ao)

READ

1

HOST
STATUS FLAG

COMMAND
INPUT

0

DATA REG
INPUT

DATA REG
OUTPUT

GENERAL PURPOSE
FLAGS STATUS REGISTER

2-96

WRITE

One-Chip Intelligent Peripheral Controller

R6541Q. R6500/41, /42, /43

~<~"'"

(254 MM)

0155 MAX

DOT OR NOTCH
TO LOCATE
PIN NO 1

(393 MM)

-

0010 MIN
(025 MM)

Interface DIagram

I

(4851 MM)
(4800 MM)

PBS
PBS
PB.
PB3
PB2

2050 MAX
(51 30 MM)

19 EQUAL SPACES
NONCUM

o 100 ~ TQl
PBO

(254 MM)

PAl

PAS
PAS
PA'

PA3
PA2

PAl

•t

PAO

20L-_ _ _-.J 21

FIGURE 2-2.

R6500/41 Pin Out Designation
(40 PIN DIP)

~

I

0500 MAX

(152' MM)

L
l~

(165 MM)

TVP
(C 55 MM)

0022

(101 MM)

0040

(045 MM)

0 018

~<:;~~:<--IY'""
40 PIN DIP

2-97

t t~

TVP
0065

A

FIGURE 2-3.

1910

1890

R6500/41 Dimensional Outline

One-Chip Intelligent Peripheral Controller

R6541Q. R6500/41, /42, /43

Interface Diagram
A6
A5
A4
A3
A2
A1
AO

WI

-

SVN.£
R/W
eLKIN

c:=

Cst=.

o! (Ao)
AIW(WA)
AS (AO)
HBO
HB1

HB2 c=-

HB3
H84 ::.._.:...-HB5
HB6
HB7
~2

PC6
PC5
PC4
PC3
PC2
PCI
PCO
V"

-

64
63
62
61
60
59
58
57
56
55
54
53
52

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

51
R6541Q

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

•

R6500/43

FIGURE 2-4.

VDD

PEl

1

64

PE2

A7
A8
A9
A10
A11
A15

PEa
eLKIN

2
3
4
5
6
7
8

63
62
61
60
59
58
57

PE3
PE4
PES
PE6
PE7
Vr:c
RES

HBl
HB2

H~

9
10
11

56
55

P87
PBS

HB4

12

53

PB4

HBS
HBS
HB7
peQ
PCl
pe2

13
14
15
16
17
18
19

52
51
50
49
48
47
46

PB3
PB2
PBl
pea
PG7
PGS
PGS

~

E (AD)
RfW (WR)
RS (AD)
HeD

m
PB7
PB6
PB5
PB4
PB3
PB2
PBI
PBO
DB7
DB6
DB<
DB4
DB3
DB2
OBI
DBO
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO

pea

M_

R6500/42

pes

PC4

20

45

PG4

21

44

PCS

22

43

P2

23

42

PG3
PG2
PGl
PGO
PF7

Vss
PAD

24
25

41
40

PAl

26

39

PF6

PA2
PA3

27
28

38
37

PF5
PF4

PA4

29

36

PF3

PAS
30
35
PF2
PA6
31
34
PF1
PA7 ----'-~32'___ _ _ _ __'3:.:;3.r_- PFO

R6541Q, R6500/42 & R6500/43 Pin Out Designations
(64 PIN QUIP)
150
(381 MM)

---I

It

1-

'0

020 TYP
(508 MM)

-<

l

o
z

>

I
1628
(4135 MM)

o

~

'" C2:

~

~

'------'==-1-----'

_'i._t

925
(23495

1

I·(~··5-~:!~-)--

~

TYP

MM) ------I

1-(19::~M)=l I

-.IT~
200

(508 MM)

L:...

a

68'0------'

. . - - - (17 27 MM)

1--1 =~
'

~ ~

~ ~

64 PIN QUIP

FIGURE 2-5.

64 PIN QUIP Dimensional Outline

2-98

I

I

~

c

32

"
I

~

llUJ

020REJ
TVP

R6541Q. R6500/41, /42, /43

One-Chip Intelligent Peripheral Controller

ELECTRICAL SPECIFICATIONS
Maximum Ratings
RATING

VALUE

SYMBOL

Supply Voltage

03 to
-0310

V"
V"

Input Voltage

o to

Operating Temperature Range,
Commercial

T

Storage Temperature Range

T,,"

65 to

UNIT

7.0

Vdo

~7.0

Vdo
oC

~

-70
150

°C

This device contains CIrcUitry to protect the Inputs against damage due to high static voltages. however It IS advised that normal precaullOns
be taken to aVOid application of any voltage higher than maximum rated voltages to this CIrCUIt

D.C. Characteristics (Vee =

5V ::': 5%, Vss

= 0)

CHARACTERISTIC

SYMBOL

UNITS

MIN

mW

Power DISSipation (Outputs High)
CommerCial 0' C to - 70 C

Input High Voltage (Normal Operating Levels)

, Input Low Voltage (Normal Operating Levels)
Input Leakage Current

f-'_np~u~t~Lo_w_c_u_"e~n~t
-

Vdo
,uAdc

+'--'-,,----f---------f---------~------+_----1

V,n -= 0 to 525 Vdc

(V IL

03
100

mAde

04 Vdc) _______________

Output High Voltage
(Vee -= min, ILood -,

VOH

24

100 J,J-Adc)

Output High Voltage
(Vee'" min)

v"

Vdo

v"

Vdo

04
Output High Current (Sourcing)
(VOH -= 24 Vdc)
Output Low Current (Sinking)
(VOL -= 04 Vdc)

mAde

10

Output Low Current, PE'
(VOL'" 0 4 Vdc)
Input Capacitance
(V,n - 0, TA '" 25 c C, f

mAde

16

Darlington Current Drive, PE"
(VOH = 1 5 Vdc)

mAde

16
10
-=

Vdo

I I-'Adc

100

pF

1 0 MHz)

PA, PB, PC, PF" PG"
Output Capacitance
(V,n - 0, TA -= 25 C, f -= 1 0 MHz)

COUT

10

pF

115

KIl

v

110 Port ReSistance

R,

30

60

I ~~g:~~; ~gg:~g~

-- i

NOTE: Negative sign Indicates outward current flow, positive mdlcates Inward flow Vee = 5V ± 5% 'R6500/42 only

2-99

R6545

'1'

R6545
CRT CONTROLLER (CRTC)

Rockwell
DESCRIPTION

FEATURES

The R6545 CRT Controller (CRTC) interfaces an S-bit microprocessor to CRT raster scan video displays, and adds an
advanced CRT controller to the established and expanding line
of R6500, R6500/* and R65COO microprocessor, microcomputer
and peripheral device products.

• Compatible with S-bit microprocessors
• 3.7 MHz character clock operation
• Refresh RAM may be configured in row/column or straight
binary addressing

The R6545 provides refresh memory addresses and character
generator row addresses which allow up to 16K characters with
32 scan lines per character to be addressed. A major advantage of the R6545 is that the refresh memory may be addressed
in either straight binary or by row/column.
Other functions in the R6545 include an internal cursor register
which generates a cursor output when its contents are equal
to the current refresh address. Programmable cursor start and
end registers allow a cursor of up to the full character scan in
height to be placed on any scan lines of the character. Variable
cursor display blink rates are provided. A light pen strobe input
allows capture of the current refresh address in an internal light
pen register. The refresh address lines are configured to provide direct dynamic memory refresh.
All timing for the video refresh memory signals is derived from
the character clock input. Shift register, latch, and multiplex control signals (when needed) are provided by external high-speed
timing. The mode control register allows noninterlaced video
display modes at 50 or 60 Hz refresh rate. The internal status
register may be used to monitor the R6545 operation. The RES
input allows the CRTC-generated field rate to be dynamicallysynchronized with line frequency jitter.

•
•
•
•
•
•
•
•
•
•

Interlaced or non-interlaced scan
50/60 Hz operation
Fully programmable cursor
Light pen register
Addresses refresh RAM to 16K characters
No external DMA required
Internal status register
40-pin ceramic or plastic DIP
Pin-compatible with MC6!l45R
Single + 5 ± 5% volt power supply

vss

R6545 __ _

[

Alphanumeric and limited graphics capability
Up and down scrolling by page, line, or character
Programmable vertical sync width
Fully programmable display (rows, columns, character matrix)
Video display RAM may be configured as part of microprocessor memory field or independently slaved to R6545
(Transparent Addressing)

VSYNC
HSYNC
RAO
RAl
RA2
RA3
RA4/STB
DO
01
02
03
04
05
06
07

RES
LPEN
CCO/MAO
CC1/MAl
CC2/MA2
CC3/MA3
CC4IMA4
CCS/MAS
CC6/MA6
CC7/MA7
CRO/MA8
CR1/MA9
CR2IMA10
CR3/MAll
CR4IMA12
CRS/MA13
DISPLAY ENABLE
CURSOR
VCC

ORDERING INFORMATION
Part Number:

•
•
•
•
•

Operating Temperature (T L to T H)
No letter = O°C to 70°C
E =, -40°C to 85°C
Package
P = Plastic
C = Ceramic

cs

RS
_2
RNi
CCLK

Operating Frequency
No Letter = t MHz
A

= 2 MHz

R6545 Pin Configuration

Document No. 29001035
2-100

Data Sheet Order No. 0135
October 1984

R6545

CRT Controller (CRTC)

INTERFACE SIGNAL DESCRIPTION

VIDEO INTERFACE

Figure 1 illustrates the interface between the CPU, the R6545,
and the video circuitry. Figure 2 shows typical timing waveforms
at the video interface.

HSYNC (Horizontal Sync)

Vee

The HSYNC active-high output signal determines the start of
the horizontal raster line. It may drive a CRT monitor directly
or may be used for composite video generation. HSYNC time
position and width are fully programmable.

GND

00-07 ~""""'-.....J"""----"'

\12

RNi
CS
RS

___

VIDEO IIF
HSYNC
VSYNC
DISPLAY ENABLE
CURSOR
LPEN
CCLK
RES

VSYNC (Vertical Sync)
The VSYNC active-high output signal determines the start of
the vertical frame. Like HSYNC, VSYNC may drive a CRT
mOnitor or composite Video generation circuits. VSYNC time
position and width are both programmable.

DISPLAY ENABLE (Display Enable)

MAo-MA13 RAO-RA4
REFRESH RAM AND CHARACTER ROM

Figure 1.

The DISPLAY ENABLE active-high output signal indicates when
the R6545 IS generating active display information. The number
of horizontal display characters per row and the number of vertical display rows are both fully programmable and together
generate the DISPLAY ENABLE Signal. DISPLAY ENABLE
delays one character time by setting bit 4 of R8 to a 1.

R6545 Interface Diagram

CPU INTERFACE
02 (Phase 2 Clock)

CURSOR (Cursor Coincidence)

The Phase 2 (02) Input clock triggers all data transfers between
the system processor (CPU) and the R6545. Since there IS no
maximum limit to the allowable 02 clock time, it is not necessary
for It to be a continuous clock. This capability permits the R6545
to be easily interfaced to non-6500 compatible microprocessors.

The CURSOR active-high output signal indicates when the scan
COincides with the programmed cursor positIOn. The cursor POSItion is programmable to any character in the address field.
Furthermore, within the character, the cursor may be programmed to be any block of scan lines, since the start scan line
and the end scan line are both programmable. The cursor position may be delayed by one character time by setting Bit 5 of
R8 to a 1.

R/W (Read/Write)
The RtW input signal generated by the processor controls the
direction of data transfers. A high on the RtW pin allows the
processor to read the data supplied by the R6545, a low on the
RtW pin allows data on data lines DO-D7 to be written into
the R6545.

LPEN (Light Pen Strobe)
The LPEN edge-sensitive Input signal loads the internal Light
Pen Register with the contents of the Refresh Scan Counter at
the time the active edge occurs. The low-to-high transition
activates LPEN.

CS (Chip Select)
The Chip Select input IS normally connected to the processor
address bus either directly or through a decoder. The R6545
is selected when CS IS low.

CCLK (Clock)
The CCLK character timing clock input signal is the time base
for all internal count/control functions.

RS (Register Select)
The Register Select input allows access to internal registers. A
low on this pin permits writing (RtW ; low) Into the Address
Register and reading (RtW ; high) from the Status Register. The
contents of the Address Register is the Identity of the register
accessed when RS IS high.

RES
The RES active-low Input Signal initializes all internal scan
counter cirCUits. When RES IS low, all Internal counters stop and
clGar, at: scan and video outputs go :ovv' and contro! :-egisters
are unaffected. RES must stay low for at least one CCLK period.
All scan timing initiates when RES goes high. In this way, RES
can synchrOnize display frame timing with line frequency. RES
may also synchronize multiple CRTC's in horizontal and/or
vertical split screen operation.

00-07 (Data Bus)
The eight data lines (DO-D7) transfer data between the processor
and the R6545. These lines are bidirectional and are normally
high-Impedance except dUring read cycles when the chip is
selected (CS ; low).

2-101

CRT Controller (CRTC)

R6545
REFRESH RAM AND CHARACTER ROM
INTERFACE

become row addresses CRO-CR5. In this case, the software
manipulates characters in terms of row and column locations,
but additional address compression circuits are needed to convert the CCO-CC7 and CRO-CR5 addresses into a memoryefficient binary address scheme.

MAO-MA13 (Refresh RAM Address Lines)
These, 14 active-high output signals address the refresh RAM
for character storage and display operations. The starting scan
address is fully programmable and the ending scan address is
determined by the total number of characters displayed, which
is also programmable, in terms of characters/line and lines/
frame.

RAO-RA4 (Raster Address Lines)
These five active-high output signals select each raster scan
within an individual character row. The number of raster scan
lines is programmable and determines the character height,
including spaces between character rows.

There are two selectable address modes for MAO-MA 13:
In the straight binary mode (RB, Mode Control, bit 2 = 0),
characters are stored in successive memory locations. Thus,
the software design must translate row and column character
coordinates into sequentially-numbered addresses for Refresh
memory operations.

The high-order line, RA4, is unique in that it can also function
as a strobe output pin when the R6545 is programmed to operate in the "Transparent Address Mode." In this case the strobe
is an active-high output and is true at the time the Refresh RAM
update address gates on to the address lines, MAO-MA13.
In this way, updates and readouts of the Refresh RAM can be
made under control of the R6545 with only a small amount of
external circuitry.

In the row/column mode (RB, Mode Control, bit 2 = 1), MAOMA7 become column addresses CCO-CC7 and MAB-MA13

~_____________________
l_C_O_M_P_L_E_T_E_F_IE_L_D_(~VE
__
R_T_IC_A_L_T_O_T_A_L~)____________________

--l

VERTICAL DISPLAYED

I

DISPLAY
ENABLE
HSYNC

VSYNC

RAG-RA4

1 COMPLETE SCAN liNE (HORIZONTAL TOTAL)
HORIZONTAL DISPLAYED
CCLK
DISPLAY
ENABLE

---------------1

;-1

,

~

r1

'-------!'

HSYNC

RAO-RA4 ____~--------------------------------------------------~1~-

Figure 2.

Vertical and Horizontal Timing

2-102

R6545

CRT Controller (CRTC)

INTERNAL REGISTER DESCRIPTION

SR

7

Table 1 summarizes the internal registers and indicates their
address selection and read/write capabilities.

o

UR
-Update Ready
Register R31 has been either read or written by the
CPU.
An update strobe has occurred.

ADDRESS REGISTER
7

6

5

4

SR
6

o

2

3

o
1

This 5-bit write-only register is used as a "pointer" to direct
CRTC/CPU data transfers within the CRTC. It contains the
number of the desired register (0-31). When RS is low, this
register may be loaded; when RS is high, the selected register
is the one whose identity is stored in this address register.

SR
~

o

STATUS REGISTER (SR)

o

2

3

LRF -LPEN Register Full
Register R16 or R17 has been read by the CPU.
LPEN strobe has been received.

VRF -Vertical Re-Trace
Scan is not currently in the vertical re-trace time.
Scan currently in its vertical re-trace time. Note that
this bit actually goes to a 1 when vertical re-trace
starts, but goes to a 0 five character clock times
before vertical re-trace ends to ensure that critical timings for refresh RAM operations are avoided.

SR
This 3-bit register contains the status of the CRTG.

Table 1.

Addr••• Reg.

Cs

RS

4

1

-

0

0

-

0

0

0
0

3

2

1

0

Reg.
No.

4-0

-Not used.

Internal Register Summary

Register Bit
Register Name

Stored Info.

RO

WR

- - - - -

-

Address Reg

- -

-

-

-

-

Status Reg

1

0

0

0

0

0

AO

Hanz Total

# Charac -1

/

1

0

0

0

0

1

Al

Hartz Displayed

# Charac

/

0

1

0

0

0

1

0

A2

HOflz Sync POSItion

# Charac

/

0

1

0

0

0

1

1

A3

VSYNC, HSYNC Widths

# Scan LII1es and
# Char Times

/

0

1

0

0

1

0

0

A4

Vert Total

'* Charac

/

0

1

0

0

1

0

1

AS

Vert Total Adjust

# Scan lines

/

0

1

0

0

1

1

0

AS

Vert Displayed

# Charac Rows

/

0

1

0

0

1

1

1

A7

Vert Sync PosItion

# Charac Rows

/

0

1

0

1

0

0

0

AS

Mode Control

0

1

0

1

0

0

1

A9

Scan Lines

0

1

0

1

0

1

0

Al0

0

1

0

1

0

1

1

All

0

1

0

1

1

0

0

A12

Display Start Addr (H)

0

1

0

1

1

0

1

A13

Display Start Addr (L)

0

1

0

1

1

1

0

A14

Cursor POSition (H)

/

j

0

1

0

1

1

1

1

A15

Cursor Posrtoo (L)

j

j

0

1

1

0

0

0

0

A1S

Light Pen Reg (H)

/

0

1

1

0

0

0

1

R17

Light Pen Reg (L)

j

0

1

1

0

0

1

0

R1S

Update Address Reg (H)

/

0

1

1

0

0

1

1

A19

Update Address Reg (L)

j

0

1

1

1

1

1

1

A3l

Dummy location

Not•• :

[!]

-

Reg No

Row-1

/
# Scan Lines - 1

/

Cursor Start

Scan Line No

/

Cursor End

Scan LIne No

/
/
/

o. cs =

3

2

1

0

A,

A,

A,

A,

Ao

6

5

U

L

V

V,

V,

Vo

H3

H,

H,

Ho

Uo

C

0

T

AC

I,

10

/
j

4

7

·• ·•• ··• ··• ··· ··• ··• ·••
· ·, ·· ·· ·· ·• ··
• • · · • · ·
·• ···• •
• · • • ·
·· ·• ·· ·• ·•
• • • • •
·
•
•
· ·· · ·• •• ·• ··
• • • • · · • •
• · ·
·
• • ·
• ·
·• ·• ·• •• ·•
·
·• • • • • ·•
•

V3

.,

U,

9,

.;: .

90

.
"

::""

. ':::,;' .::·:·:.::i~

.. .:
~

. ,'

.' :

.....

DeSignates used bit In register
DeSignates unused bit In register Reading thiS bit Is always O. except for R31. which does not dnve the data bus at all, and for
1 which operates hkewlse

2-103

R6545

CRT Controller (CRTC)

RO-HORIZONTAL TOTAL CHARACTERS
7

6

5

4

3

2.

to the line frequency to ensure flicker-free appearance. If the
frame time is adjusted to be longer than the period of the line
frequency, then RES may provide absolute synchronism.

o

NUMBER OF CHARACTERS -1

RS-VERTICAL TOTAL LINE ADJUST
This a-bit write-only register contains the total of displayed and
non-displayed characters, minus one, per hOrizontal line. This
register determines the frequency of HSYNC.

5

6

5

4

3

2

o

6

5

4

3

4

3

2

o

DISPLAYED CHAR. ROWS

R2-HORIZONTAL SYNC POSITION
5

o

R6-VERTICAL DISPLAYED ROWS

This a-bit write-only register contains the number of displayed
characters per horizontal line.

6

2

The 5-bit write-only Vertical Total Line Adjust Register (R5) contains the number of additional scan lines needed to complete
an entire frame scan and is intended as a fine adjustment for
the video frame time.

NUMBER OF CHARACTERS

7

3

SCAN LINES

R1-HORIZONTAL DISPLAYED CHARACTERS
7

4

2

o

This 7-bit write-only register contains the number of displayed
character rows in each frame. This determines the vertical size
of the displayed text

HORIZONTAL SYNC POSITION

This a-bit write-only register contains the position of HSYNC on
the horizontal line, in terms of the character location number
on the line. The position of the HSYNC determines the left to
right location of the displayed text on the video screen. In this
way, the side margins are adjusted.

R7-VERTICAL SYNC POSITION
6

5

4

3

2

o

VERTICAL POSITION

R3-HORIZONTAL AND VERTICAL SYNC WIDTHS

This 7-bit write-only register selects the character row time at
which the vertical SYNC pulse is desired to occur and, thus, positions the displayed text in the vertical direction.

RS-MODE CONTROL (MC)
This a-bit write-only register contains the widths of both HSYNC
and VSYNC, as follows:

o

o
HVSW
7-4 VSYNC Pulse Width
The width of the vertical sync pulse (VSYNC) in the
number of scan lines. When bits 4-7 are all 0, VSYNC
is 16 scan lines wide.

This a-bit write-only register selects the operating modes of the
R6545, as follows:

MC
7

o

HVSW

3-0

HSYNC Pulse Width
The width of the horizontal sync pulse (HSYNC) in
the number of character clock times (CCLK).

MC
6

Control of these parameters allows the R6545 to interface with
a variety of CRT monitors, since the HSYNC and VSNYC timing signals may be accommodated without the use of external
one shot timing.

o
1

UM(T)-Update/Read Mode (Transparent Mode)
Update occurs during horizontal and vertical blanking times with update strobe.
Update interleaves during 02 portion of cycle.
US(T) -Update Strobe (Transparent Mode)
Pin 34 functions as memory address.
Pin 34 functions as update strobe.

MC

R4-VERTICAL TOTAL ROWS
7

6

5

4

5
3

2

o

o

CSK -Cursor Skew
No delay.
Delays Cursor one character time.

NO. OF CHAR. ROWS - 1

MC
4

The 7-bit Vertical Total Register contains the total number of
character rows in a frame, minus one. This register, along with
R5, determines the overall frame rate, which should be close

o

2-104

DES -Display Enable Skew
No delay.
Display Enable delays one character time.

CRT Controller (CRTC)

R6545
MC
3

o
1
MC
2

o
1

RAD -Refresh RAM Addressing Mode
Straight binary addressing
Row/column addressing

MC1-MCO IMC
MC
1

.JL

1

0
1
1

X
o

These registers together form a 14-bit register whose contents
is the memory address of the first character of the displayed scan
(the character on the top left of the video display, as in Figure 1).
Subsequent memory addresses are generated by the R6545 as
a result of CCLK input pulses. Scrolling of the display is accomplished by changing R12 and R13 to the memory address
associated with the first character of the desired line of text to
be displayed first. Entire pages of text may be scrolled or
changed as well via R12 and R13.

RRA -Refresh RAM Access
Shared memory access
Transparent memory access

-Interlace Mode Control

I
~_7 1_6
.
.
.

Operation
Non-interlace
Interlace SYNC raster scan
Interlace SYNC and video raster scan

6

3

2

o

R10-CURSOR START LINE
6

5

I

Bo

4

3

I

2

7

5

6

I

-

o

80

0
0
1
1

0
1
0
1

4

I

3

2

o
The cursor is positioned on the screen by loading the Cursor
Position Address High (R14) and Cursor Position Address Low
(R15) registers with the desired refresh RAM address. The cursor
can be positioned in any of the 16K character pOSitions. Hardware paging and data scrolling is thus allowed without loss of
cursor poSition. Figure 3 is an example of the display cursor scan
line.

END SCAN LINE

Cursor Operating Mode
Display Cursor Continuously
Blank Cursor
Blink cursor at 1/16 Field Rate
Blink Cursor at 1/32 Field Rate

UNDERLINE
CURSOR

A one character wide cursor can be controlled by storing values
into the Cursor Start Line (R10) and Cursor End Line (R11)
registers and into the Cursor Position Address High (R14) and
Cursor Position Low (R15) registers.

5

4

3

2

4

3

2

3

o

B
9

B
9

10

10

"

"

"

CURSOR START
LINE 9

CURSOR START
LINE 1

CURSOR START
LINE 1

CURSOR END
LINE 9

CURSOR END
LINE 1

CURSOR END
LINE 9

=

DISPLAY START ADDRESS LOW

Figure 3.

2-105

4
5
6
7

10

=

o

3

4
5
6
7

B
9

R13-DISPLA Y START ADDRESS LOW
5

CURSOR

0 011111

3

4
5
6
o7

DISPLAY START ADDRESS HIGH

6

BOX

OVER LINE
CURSOR

1
1
1
2 2 2

R12-DISPLAY START ADDRESS HIGH

7

o

2

A cursor of up to 32 characters in height can be displayed on
and between the scan lines as loaded into the Cursor Start Line
(R10) and Cursor End Line (R11) Registers.

These 5-bit write-only registers select the starting and ending
scan lines for the cursor. In addition, bits 5 and 6 of R10 are
used to select the cursor blink mode, as follows:

8,

3

START SCAN LINE

R11-CURSOR END LINE

I- I

4

These registers together form a 14-bIt register whose contents
IS the memory address of the current cursor position. When the
Video display scan counter (MA lines) matches the contents of
this register, and when the scan line counter (RA lines) falls
within the bounds set by R10 and R11, then the CURSOR output becomes active. Bit 5 of the Mode Control Register (RS) may
be used to delay the CURSOR output by a full CCLK time to
accommodate slow access memories.

This 5-bit write-only register contains the number of scan lines,
minus one, per character row, including spacing.

B,

5

CURSOR POSITION LOW

SCAN LINES -1

7

6

7

4

CURSOR POSITION HIGH

R1S-CURSOR POSITION LOW

R9-ROW SCAN LINES

I- I

PO_S~I_T_IO_N~H_I_G_H~
__~__~__~1
5
4
3
2
0
.

LR_14_-_CrU_R_S_O+R__

MC

=

=

=

=

Cursor Display Scan Line Control Examples

2

R6545

CRT Controller (CRTC)

R16-LlGHT PEN HIGH
7

5

3

4

These registers together comprise a 14-bit register whose contents is the memory address at which the next read or update
will occur (for transparent address mode, only). Whenever a
read/update occurs, the update location automatically increments to allow for fast updates or readouts of consecutive
character locations. This is described elsewhere in this document. The section on REFRESH RAM ADDRESSING describes
this more fully.

o

2

LPEN HIGH

R17-LlGHT PEN LOW
7

5

6

3

4

o

2

LPEN LOW

R31-DUMMY LOCATION

4

3

R19-UPDATE ADDRESS LOW
5

6

4

3

(1) Straight binary, if register RB, bit 2 = 0
(2) Row/Column, if register RB, bit 2 = 1. In this case the low
byte is the Character Column and the high byte is the
Character Row.

a

2

UPDATE ADDRESS LOW

NUMBER OF HORIZONTAL TOTAL CHARACTERS (RO)
A

r
NUMBER OF HORIZONTAL DISPLAYED CHARACTERS (Rl)
I

L

,...

NUMBER OF
VERTICAL
TOTAL
ROWS
(R4)

,

,

A

DISPLAY START ADDRESS HIGH (R12)*
DISPLAY START ADDRESS LOW (R13)*

f NUMBER OF
SCAN LINES (R9)

~1\
NUMBER OF
VERTICAL
DISPLAY
ROWS
(RS)

a

Register pairs R12/R13, R14/R15, R16/R17, and R1B/R19 are
formatted in one of two ways:

UPDATE ADDRESS HIGH

7

2

REGISTER FORMATS

a

2

3

This register does not store any data, but is required to detect
when transparent addressing updates occur. This is necessary
to increment the Update Address Register and to set the Update
Ready bit in the status register.

R18-UPDATE ADDRESS HIGH
5

5

6

These registers together form a 14-bit register whose contents
is the light pen strobe position, in terms of the video display
address at which the strobe occurred. When the LPEN input
changes from low to high, then, on the next negative-going edge
of CCLK, the contents of the internal scan counter is stored in
registers R16 and R17.

CURSOR START LINE (Rl0)
~CURSOR END LINE (Rll)

CURSOR POSITION ADDRESS HIGH (R14)
CURSOR POSITION ADDRESS LOW (R1S)

DISPLAY PERIOD

VERTICAL RETRACE PERIOD
(NON-DISPLAY)
VERTICAL
{
TOTAL
ADJUST (RS)

Figure 4.

Video Display Format

2-106

HORIZONTAL
RETRACE
PERIOD
(NON-DISPLAY)

CRT Controller (CRTC)

R6545

= 0)

DESCRIPTION OF OPERATION

Shared Memory Mode (Ra, BIT 3

VIDEO DISPLAY

In this mode, the Refresh RAM address lines (MAO-MA13)
directly reflect the contents of the internal refresh scan character
counter. Multiplex control, to permit addressing and selection
of the RAM by both the CPU and the CRTC, must be provided
external to the CRTC. In the Row/Column address mode, lines
MAO-MA7 become character column addresses (CCO-CC7) and
MA8-MA 13 become character row addresses (CRO-CR5).
Figure 5 illustrates the system configuration.

Figure 4 indicates the relationship of the various program registers in the R6545 and the resulant video display.
Non-displayed areas of the Video Display are for horizontal and
vertical retrace functions of the CRT monitor. The horizontal and
vertical sync signals, HSYNC and VSYNC, are programmed to
occur during these intervals and trigger the retrace in the CRT
monitor. The pulse widths are constrained by the monitor requirements. The time position of the pulses'i'nay be adjusted to vary
the display margins (left, right, top, and bottom).

Transparent Memory Addressing
For this mode, the display RAM is not directly accessible by the
CPU, but is controlled entirely by the R6545. All CPU accesses
are made via the R6545 and a small amount of external circuits. Figure 6 shows the system configuration for this approach.

REFRESH RAM ADDRESSING
There are two modes of addressing for the video display memory:

VSYNC

SYSTEM
BUS

HSYNC
A8545

DISPLAY ENABLE

CRT CONTROLLER

TO
VIDEO
CIRCUITS

CURSOR

RAO-RA4
DISPLAY ADDRESS
CPU
SCAN UNE
COUNT

VIDEO AODRESS

CHARACTER
DATA

Figure 5.

SCAN UNE

L..._ _.J DOT PATTERN

Shared Memory System Configuration

SYSTEM
BUS
R854S

CRT CONTROLLER
RA4

CPU

MAO..... A13

UPDATE
STROBE

RAD-RA3

DISPLAY/UPDATE
ADDRESS

SCAN LINE
COUNT

HARACTE
GENERATO

ROM
CHARACTER
DATA

Figure 6.

CHARACTER
DATA

Transparant Memory Addressing System Configuration
(Data Hold Latch Needed for Horizontal/Vertical Blanking Updates, Only).

2-107

PI

CRT Controller (CRTC)

R6545
ADDRESSING MODES

viable technique, since the Display Enable signal controls the
actual video display blanking. Figure 7 illustrates Refresh RAM
addressing for both row/column and binary addressing for
80 columns and 24 rows with 10 non-displayed columns and 10
non-displayed rows.

Figure 7 illustrates the address sequence for both modes of the
Refresh RAM address.

Row/Column
Note that the straight-binary mode has the advantage that all
display memory addresses are stored in a continuous memory
block, starting with address 0 and ending at 1919. The disadvantage with this method is that, if it is desired to change a
displayed character location, the row and column identity of the
location must be converted to its binary address before the
memory may be written. The row/column mode, on the other
hand, does not need to undergo this conversion. However,
memory is not used as efficiently, since the memory addresses
are not continuous, gaps exist. This requires that the system
be equipped with more memory than actually used and this extra
memory is wasted. Alternatively, address compression logic may
be employed to translate the row/column format into a continuous address block.

In this mode, the CRTC address lines (MAD-MA13) generates
as 8 column (MAD-MA7) and 6 row (MA8-MA13) addresses.
Extra hardware is needed to compress this addressing into a
straight binary sequence in order to conserve memory in the
refresh RAM (register R8, bit 2 is a 1).

Binary
In this mode, the CRTC address lines are straight binary and
no compression circuits are needed. However, software complexity increases since the CRT characters cannot be stored in
terms of their row and column locations, but must be sequential (register R8, bit 2 is a 0).

USE OF DYNAMIC RAM FOR REFRESH MEMORY

The user selects whichever mode is best for the given application. The trade-ofts between the modes are software versus hardware. Straight-binary mode minimizes hardware requirements
and row/column minimizes software requirements.

The R6545 permits use of dynamic RAMS as storage devices
for the Refresh RAM by continuing to increment memory
addresses in the non-display intervals of the scan. This is a

, - - - - - - - TOTAL

rl------

I

rz~

Ir,

~

i

I!

=.. ---------,

,----DlSPlAy

DlSPLAY=80~

,"0:0

'"6"

2
82

--- -.- 77
--- -0- 157

162 --- --- 237

L

~ l5

TOTAL

78
79
158159

80
160

81 - - - B9
161 --- 169

238

240

241 --- 249

239

l.

COLUMN ADDRESS (MAO-MAU)

n

f~

1_Io:1 :o~:
C

:,',:

2 - - - _. 77
258 .-- --- 333

78
78
334

----i

891

79180

a1

79
335

89
81
337 --- 345

80
336

514 --- -.- 589 590 591 59? 593 --- 601
,~~~~_~~__~~~~~~~+-~~

~ ~ :I '---;:-+-!I-+-t-t-+-!--;·+-+-+-~~
r ,

~ ~ C

:

II

1760 17611762 --- __

0

183718381839 1840 1841 - -- 1849

L

~

2000 2001 2002 - - - - - - 2077 20782079 2080 2081 - - - 2089
"
"

264026412642·- - --- 27172718271927202721--- 2729

STRAIGHT BINARY ADDRESSING SEQUENCE

Figure 7.

(I)

~

1920 1921 1922 - - - - - - 1997 1998 1999 2000 2001 - - - 2009

,,

li

f4!!

g~ is

: :

1840 1841 1842 -- - - - - 1917 1918 1919 1920 1921 - -- 1929

[

j-----

= .. - - - - - - - - . "

= 80 ~

I

H'+-!-+-t-!I-+-+--7-t--+-t-+T-l

1::'::±=I=+-+---1I=±::-:-:t~r,.::+:=t-+=I

21
22 563256335634 - - - - -- 5709 5710 5111 57125713 - - - 5721

--E

5888 5889 5890 - - - - - - 5965 5966 5967 5968 5969 - - - 5977

24 6144 6145 6146 - - - - - - 6221 6222 6223 6224 6225 - - - 6233

L: ::: : : : : ~ ~ ~ ~ ~: : : : : : : :: : : :~ ~ : :
ROW/COLUMN ADDRESSING SEQUENCE

Display Address Sequences (with Start Address=O) for 80 )( 24 Example

2-108

R6545

CRT Controller (CRTC)

MEMORY CONTENTION SCHEMES FOR
SHARED MEMORY ADDRESSING

TRANSPARENT MEMORY ADDRESSING
In this mode of operation, the video display memory address
lines are not switched by contention circuits, but are generated
by the R6545. In effect, the contention is handled by the R6545.
As a result, the schemes for accomplishing CPU memory access
are different:

From the diagram of Figure 5, it is clear that both the R6545
and the system CPU must address the video display memory.
The R6545 repetitively fetches character information to generate
the video signals in order to keep the screen display active. The
CPU occasionally accesses the memory to change the displayed
information or to read out current data characters. Three ways
of resolving this dual-contention requirement are apparent:

• 01 and 02 Interleaving
This mode is similar to the Interleave mode used with shared
memory. In this case, however, the 02 address is generated
from the Update Address Register (R1a and R19) in the
R6545. Thus, the CPU must first load the address to be
accessed into R1a/R19 and then this address is always gated
onto the MA lines during 02. Figure 9 shows the timing.

• CPU Priority
In this technique, the address lines to the video display memory are normally driven by the R6545 unless the CPU needs
access, in which case the CPU addresses immediately override those from the R6545 giving the CPU immediate access.
• 01 and 02 Memory Interleaving
This method permits both the R6545 and the CPU access
to the video display memory by time-sharing via the system
01 and 02 clocks. During the 01 portion of each cycle (the
time when 02 is low), the R6545 address outputs are gated
to the video display memory. In the 02 time, the CPU address
lines are switched in. In this way, both the R6545 and the
CPU have unimpeded access to the memory. Figure a illustrates the timings.

O.
CLOCK

MAO-MA13

Figure 9.

01 and 02 Transparent Interleaving

e.
CLOCK

• Horizontal/Vertical Blanking

Vlceo
DISPLAY
MEMORY
ADDRESSES

Figure 8.

In thiS mode, the CPU loads the Update Address, but is only
gated onto the MA lines during horizontal or vertical blank
times, so memory accesses do not interfere with the display
appearance. To signal when the update address is on the
MA lines, an update strobe (STB) is provided as an alternate
function of pin 34. Data hold latches are necessary to temporarily retain the character to be stored until the retrace time
occurs. In this way, the system CPU is not halted waiting for
the blanking time to arrive. Figure 11 illustrates the address
and strobe timing for this mode.

01 and 02 Interleaving

• Vertical Blanking
With this approach, the address circuitry is identical to the
case for CPU Priority updates. The only difference is that the
Vertical Retrace status bit (bit 5 of the Status Register) is used
by the CPU so that access to the video display memory is
only made during vertical blanking time (when bit 5 is a 1).
In this way, no visible screen perturbations result. See
Figure 10 for details.

CURSOR AND DISPLAY ENABLE SKEW CONTROL
Bits 4 and 5 of the Mode Control register (Ra) are used to delay
the Display Enable and Cursor outputs, respectively. Figure 12
illustrates the effect of the delays.

2-109

fI

R6545

CRT Controller (CRTC)

.

FRAME

.

FRAME

VERTICAL DISPLAYED

VERTICAL
BLANKING

DISPLAY
ENABLE

VERTICAL
BLANKING
STATUS
BIT
---,
(STATUS
REGISTER
BIT 5)

I
"0" = DISPLAY ACTIVE
I......--------------l

\1-.-1_ _~

SWITCHES STATE AT
END OF LAST DISPLAYED
SCAN LINE.

Figure 10.

"1" = VERTICAL
BLANKING
ACTIVE

Operation of Vertical Blanking Status Bit

2-110

R6545

CRT Controller (CRTC)

CCLK
1 : - - + - - - + - - _ 1 HORIZONTAWVERTICAL BLANKING - - - DISPLAY
DISPLAY
ENABLE

1

\

1

:

I

I
I

I
I

i:

CRT DISPLAY

ADDR~SSES

I

I

::~ ~ ~~o"R~~S
,
I

UPSTB

I
I
:

I

I

I

I

n1

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- ; :__- J

NON.DISPLAY

IJl-------..J

'lXI'

I~--_r---------------------------------------

Figure 11.

Retrace Update Timing

CCLK

c"~.{
~~,{

(NO DELAY)

(WITH DELAY)

(NO DELAY)

ENABLE
POSITIVE
EDGE

(WITH DELAY)

~,

ENABLE
NEGATiVe
EDGE

{

(NO DELAY)

(WITH DELAY)

Figure 12.

CRT DISPLAY ADDRESSES

Cursor and Display Enable Skew

2·111

fJ

R6545

CRT Controller (CRTC)

WRITE TIMING CHARACTERISTICS

(Vee

=

5.0V ± 5%, TA

=h

to T H, unless otherwise noted)

R6545
Symbol

Characteristic

Min.

R6545A
Max.

Min.

Max.

Unit

tCYC

Cycle Time

1.0

-

05

-

~s

tc

02 Pulse Width

440

200

-

ns

t ACW

Address Set-Up Time

80

40

-

ns

tCAH

Address Hold Time

0

-

0

-

ns

t wcw

R/W Set-Up Time

80

-

40

-

ns

tCWH

R/W Hold Time

0

-

0

-

ns

t DCW

Data Bus Set-Up Time

165

-

60

-

ns

tHW

Data Bus Hold Time

10

-

10

-

ns

(tA and tF

=

10 to 30 ns)

READ TIMING CHARACTERISTICS

(Vee

= 5.0V ±

5%, TA

=h

to T H, unless otherwise noted)

R6545
Symbol

Characteristic

R6545A

Min.

Max.

Min.
05

-

~s

200

-

ns

Max.

Unit

tCYC

Cycle Time

1.0

tc

02 Pulse Width

440

-

tACA

Address Set-Up Time

80

-

40

Address Hold Time

0

-

0

-

ns

tCAA
tWCA

R/W Set-Up Time

80

-

40

-

ns

tCDA

Read Access Time (Valid Data)

-

-

150

ns

tHA

Read Hold Time

10

10

-

ns

tCOA

Data Bus Active Time (Invalid Data)

40

40

-

ns

(tA and tF

=

290

-

10 to 30 ns)

WRITE TIMING WAVEFORMS

READ TIMING WAVEFORMS

<1>2

<1>2

CS,RS

CS, RS

RiW

Rm

DATA BUS

DATA BUS

2-112

ns

R6545

CRT Controller (CRTC)

MEMORY AND VIDEO INTERFACE CHARACTERISTICS
(Vee

= s.ov

± S%, TA

Symbol

= TL to TH,

unless otherwise noted)

Parameter

Min.

tCCH

Minimum Clock Pulse Width, High

130

tccv

Clock Frequency

t A , tF

Rise and Fall Time for Clock Input

tMAD

Memory Address Delay Time

100

160

ns

tRAD

Raster Address Delay Time

100

160

ns

t DTO

Display Timing Delay Time

160

300

ns

t HSD

Horizontal Sync Delay Time

160

300

ns

t VSD

Vertical Sync Delay Time

160

300

ns

tCDD

Cursor Display Timing Delay Time

160

300

ns

MAO-MAI3

RAO-RA4

DISPLAY ENABLE

HSYNC,VSYNC

CURSOR

2-113

Typ.

Max.

Unit

3.7

MHz

20

ns

ns

fJ

CRT Controller (CRTC)

R6545
TRANSPARENT ADDRESSING
WAVEFORMS (1/)1/1/)2 INTERLEAVING)

MAOMA13

LIGHT PEN STROBE TIMING CHARACTERISTICS
R6545
Symbol

Characteristic

R6545A
Max.

Unit

t LPH

LPEN Hold Time

100

-

100

-

ns

t LP1

LPEN Setup Time

120

-

120

ns

t LP2

CCLK to LPEN Delay

0

-

0

-

Min.

Max.

Min.

Note: t A , tF = 20 ns (max)

LIGHT PEN STROBE TIMING WAVEFORMS

MA~MA13 ______n____J)(~_____n+_l____J)(~

____

n_+_2____

J)(~

NOTE: "Safe" time position lor LPEN positive edge to cause
address n+2 to load Into Ligl)t Pen Register.
~P2 and t LP1 are time positions causing uncertain results.

2·114

____

ns

CRT Controller (CRTC)

R6545
CRTC Register Comparison
NON·INTERLACE
REGISTER

SY6545R

MC6845R
HD6845R

SY6845

HD6845S

R6545·1
SY6545·1

R6545
SY6545E

RO HORIZONTAL TOT

TOT·1

TOT·1

TOT-1

TOT-1

TOT-1

TOT-1

R1 HORIZONAL DISP

ACTUAL

ACTUAL

ACTUAL

ACTUAL

ACTUAL

ACTUAL

R2 HORIZONTAL
SYNC

ACTUAL

ACTUAL

ACTUAL

ACTUAL

ACTUAL

ACTUAL

R3 HORIZ AND VERT
SYNC WIDTH

HORIZONTAL

HORIZONTAL

HORIZONTAL

HORIZONTAL
AND VERTICAL

HORIZONTAL
AND VERTICAL

HORIZONTAL
AND VERTICAL

R4 VERTICAL TOT

TOT-1

TOT-1

TOT-1

TOT-1

TOT-1

TOT-1
ANY VALUE

R5 VERTICAL
TOT ADJ

ANY VALUE

ANY VALUE

ANY VALUE

ANY VALUE

ANY VALUE
EXCEPT
R5 = R9H-X

R6 VERTICAL DISP

ANY VALUE
r-~------~1---~HSYNC

VSYNC
DISPLAY ENABLE
CURSOR
LPEN
CCLK
RES

1/12

Rm
CS
RS

VSYNC (Vertical Sync)
The VSYNC active-high output signal determines the start of
the vertical frame. Like HSYNC, VSYNC may drive a CRT
monitor or composite video generation circuits. VSYNC time
position and width are both programmable.

MAD-MA13 RAO-RA4
REFRESH RAM AND CHARACTER ROM

Figure 1.

DISPLAY ENABLE (Display Enable)
The DISPLAY ENABLE active-high output signal indicates when
the R6545-1 IS generating active display information. The number
of hOrizontal display characters per row and the number of vertical display rows are both fUlly programmable and together generate the DISPLAY ENABLE signal. DISPLAY ENABLE delays
one character time by setting bit 4 of R8 to a 1.

R6545-1 Interface Diagram

CPU INTERFACE
92 (Phase 2 Clock)

CURSOR (Cursor Coincidence)

The Phase 2 (02) Input clock triggers all data transfers between
the system processor (CPU) and the R6545-1. Since there is
no maximum limit to the allowable ~2 clock time, it is not necessary for it to be a continuous clock. This capability permits
the R6545-1 to be easily interfaced to non-6500 compatible
microprocessors.

The CURSOR active-high output Signal indicates when the scan
COincides With the programmed cursor pOSition. The cursor
position is programmable to any character in the address field.
Furthermore, within the character, the cursor may be programmed to be any block of scan lines, Since the start scan line
and the end scan line are both programmable. The cursor
position may be delayed by one character time by setting Bit 5
ofR8toa1.

R/W (Read/Write)
The R/IN input signal generated by the processor controls the
direction of data transfers. A high on the RjW pin allows the
processor to read the data supplied by the Re545-1, a low on
the R/IN pin allows data on data lines 00-07 to be written Into
the R6545-1.

LPEN (Light Pen Strobe)
The LPEN edge-sensitive input signal loads the Internal Light
Pen Register with the contents of the Refresh Scan Counter at
the time the active edge oc-::urs. The low-to-high transition
activates LPEN.

CS (Chip Select)
The Chip Select input is normally connected to the processor
address bus either directly or through a decoder. The R6545-1
is selected when CS is low.

CCLK (Clock)

RS (Register Select)

The CCLK character timing clock input signal is the time base
for all internal count/control functions.

The Register Select input allows access to internal registers. A
low on this pin permits writing (RIW = low) into the Address
Register and reading (RIW = high) from the Status Register. The
contents of the Address Register is the identity of the register
accessed when RS is high.

RES
The RES active-low input signal initializes all internal scan
counter circuits. When RES IS low, all internal counters stop and
clear, all scan and video outputs go low and control registers
are unaffected. RES must stay low for at least one CCLK period.
All scan timing initiates when RES goes high. In ,this way, RES
can synchronize display frame timing with line frequency. RES
may also synchronize multiple CRTC's in horizontal and/or
vertical split screen operation.

00-07 (Data Bus)
The eight data lines (00-07) transfer data between the processor
and the R6545-1. These lines are bidirectional and are normally
high-impedance except during read cycles when the chip is
selected (CS = lOW).

2-119

fI

CRT Controller (CRTC)

R6545-1
REFRESH RAM AND CHARACTER ROM
INTERFACE

become row addresses CRO-CR5. In this case, the software
manipulates characters in terms of row and column locations,
but additional address compression circuits are needed to convert the CCO-CC7 and CRO-CR5 addresses into a memoryefficient binary address scheme.

MAO-MA13 (Refresh RAM Address Lines)
These 14 active-high output signals address the refresh RAM
for character storage and display operations. The starting scan
address is fully programmable and the ending scan addr!"ss is
determined by the total number of characters displayed, which
is also programmable, in terms of characters/line and linesl
frame.

RAO-RA4 (Raster Address Lines)
These five active-high output signals select each raster scan
within an indillidual character row. The number of raster scan
lines is programmable and determines the character height,
including spaces between character rows.

There are two selectable address modes for MAO-MA13:

=

The high-order line, RA4, is unique in that it can also function
as a strobe output pin when the R6545-1 is programmed to
operate in the "Transparent Address Mode." In this case the
strobe is an active-high output and is true at the time the Refresh
RAM update address gates on to the address lines, MAO-MA 13.
In this way, updates and readouts of the Refresh RAM can be
made under control of the R6545-1 with only a small amount
of external circuitry.

In the straight binary mode (RS, Mode ContrOl, bit 2
0),
characters are stored in successive memory locations. Thus,
the software design must translate row and column character
coordinates into sequentially-numbered addresses for Refresh
memory operations.

=

In the rowlcolumn mode (RS, Mode Control, bit 2
1), MAOMA7 become column addresses CCO-CC7 and MAS-MA13

1 COMPLETE FIELD (VERTICAL TOTAL)

VERTICAL DISPLAYED

DISPLAY
ENABLE
HSYNC

VSYNC

RAG-RA4

CCLK
DISPLAY
ENABLE

--.-J - - - - - - - - - - - - - - - - 1

1

I

;-1

I

HSYNC

MAO-MA13

X

XXXXXXXXXXXXXX

XXXX XX

RAO-RA4

Figure 2.

Vertical and Horizontal Timing

2-120

LX

CRT Controller (CRTC)

R6545-1
INTERNAL REGISTER DESCRIPTION

SR
7

o

Table 1 summarizes the internal registers and indicates their
address selection and read/write capabilities.

UR
-Update Ready
Register R31 has been either read or written by the
CPU.
An update strobe has occurred.

ADDRESS REGISTER
7

6

5

4

SR

o

2

3

6

o

Ao

1

This 5-bit write-only register is used as a "pointer" to direct
CRTC/CPU data transfers within the CRTC. It contains the
number of the desired register (0-31). When RS is low, this
register may be loaded; when RS is high, the selected register
is the one whose identity is stored in this address register.

SR

5

o
1

STATUS REGISTER (SR)

o

2

3

LRF -LPEN Register Full
Register R16 or R17 has been read by the CPU.
LPEN strobe has been received.

VRF -Vertical Re-Trace
Scan is not currently in the vertical re-trace time.
Scan currently in its vertical re-trace time. Note that
this bit actually goes to a 1 when vertical re-trace
starts, but goes to a 0 five character clock times
before vertical re-trace ends to ensure that critical timings for refresh RAM operations are avoided.

SR

4-0

This 3-bit register contains the status of the CRTC.

Table 1.
AdcIreaa Reg.

-Not used.

Internal Register Summary
Regl_aH

Reg.

Cs

AS

4

1

-

0

0
0

-

-

Address Reg

0

- - - - - - -

0

1

0

0

0

0

0

RO

Honz Total

'1# Charac -1

/

0

1

0

0

0

0

1

Al

HarIZ. Displayed

:# Charac

/

0

1

0

0

0

1

0

R2

HarlZ Sync POSitIOn

# Charac

/

0

1

0

0

0

1

1

A3

VSYNC, HSYNe Widths

# Scan Lines and
:# Char Times

/

0

1

0

0

1

0

0

A4

Vert Total

II Charac Row-1

/

3

2

1

- -

0

No.

Regia. Name

Stored Info.

RD

Reg No

WR

0

1

0

0

1

0

1

AS

Vert Total Adjust

# Scan wnes

/

0

1

0

0

1

1

0

A6

Vert Displayed

II Charac Rows

/

0

1

0

0

1

1

1

A7

Vert Sync POSition

:# Charac Rows

0

1

0

1

0

0

0

AS

Mode Control

0

1

0

1

0

0

1

A9

Scan Lmes

*Scan lines -1

0

1

0

1

0

1

0

Al0

Cursor Start

Scan Line No

/

0

1

0

1

0

1

1

All

Cursor End

Scan Line No

/

0

1

0

1

1

0

0

A12

Display S1art Add. (H)

0

1

0

1

1

0

1

A13

Display Start Addr (L)

0

.1

0

1

1

1

0

R14

Cursor PositIOn (H)

/

/

0

1

0

1

1

1

1

AIS

Cursor POSitIOn (L)

/

/

0

1

1

0

0

0

0

RIS

ugh! Pen Aeg (H)

/
/

/
/
/

/
/

0

1

1

0

0

0

1

A17

ugh! Pen Aeg (L)

0

1

1

0

0

1

0

AIS

Update Address Reg (H)

/

0

1

1

0

0

1

1

A19

Update Address Reg (L)

/

0

1

1

1

1

1

1

A31

Dummy locatIOn

Not. .:

[!]

D

6

5

u

L

V

/

J

Status Reg

7

4

3

2

1

0

A,

A,

A,

A,

Ao

·
·
·
·
····
• •, · · • • •
• • • •
• • ·
• • · • •
• · · · • • •
·· ·• •• •• ·•
•
·• •• ••
• • ·
·
• · • · · • • ·
• • • • •
• · • · · '. • ·
• • ·
•
·
·
·
• • · · · • • •
· ·• •• •• ·· ··
• · ·
• • • • • • •
•
• • • •
• • • •

V,

V,

V,

Vo

H,

H,

U,

Uo

C

D

T

RC

B,

Bo

H,

DeSignates used blt In register
Designates unused bllm register Reading this brt IS always 0, except for R31, which does nol drive the data bus al all, and for
1 which operates Ilkewl58

CS -

2-121

Ho

0

fI

R6545-1

CRT Controller (CRTC)

RO-HORIZONTAL TOTAL CHARACTERS
7

I

6

I

5

I

4

I

3

I

2

to the line frequency to ensure flicker-free appearance. If the
frame time is adjusted to be longer than the period of the line
frequency, then RES may provide absolute synchronism.

o

I

NUMBER OF CHARACTERS -1

RS-VERTICAL TOTAL LINE ADJUST
This S-blt write-only register contains the total of displayed and
non-displayed characters, minus one, per horizontal line. This
register determines the frequency of HSYNC.

I

R1-HORIZONTAL DISPLAYED CHARACTERS

The 5-bit write-only Vertical Total Line Adjust Register (R5) contains the number of additional scan lines needed to complete
an entire frame scan and is intended as a fine adjustment for
the video frame time.

NUMBER OF CHARACTERS

7

16 1

5

14

I

3

I

'2

I

R6-VERTICAL DISPLAYED ROWS

This S-bit write-only register contains the number of displayed
characters per horizontal line.

1

I

6

I

5

I

4

I

3

I

2

I

o

DISPLAYED CHAR. ROWS

R2-HORIZONTAL SYNC POSITION
7

o

1

I

1

I

This 7-bit write-only register contains the number of displayed
character rows in each frame. This determines the vertical size
of the displayed text.

0

HORIZONTAL SYNC POSITION

This S-bit write-only register contains the position of HSYNC on
the horizontal line, in terms of the character location number on
the line. The position of the HSYNC determines the left to right
location of the displayed text on the video screen. In this way,
the side margins are adjusted.

R7-VERTICAL SYNC POSITION
5

I

4

I

3

I

2

I

1

o

VERTICAL POSITION

This 7-bit write-only register selects the character row time at
which the vertical SYNC pulse is desired to occur and, thus,
positions the displayed text in the vertical direction.

R3-HORIZONTAL AND VERTICAL SYNC WIDTHS

RS-MODE CONTROL (MC)

o
o

This S-bit write-only register contains the widths of both HSYNC
and VSYNC, as follows:
HVSW
VSYNC Pulse Width
7-4
The width of the vertical sync pulse (VSYNC) in the
number of scan lines. When bits 4-7 are all 0, VSYNC
is 16 scan lines wide.

This S-bit write-only register selects the operating modes of the
R6545-1, as follows:

MC
7

HVSW

3-0

"0

HSYNC Pulse Width
The width of the horizontal sync pulse (HSYNC) in
the number of character clock times (CCLK).

MC

Control of these parameters allows the R6545-1 to interface with
a variety of CRT monitors, since the HSYNC and VSYNC timing
Signals may be accommodated without the use of external one
shot timing.

6

"0
1
MC
5

R4-VERTICAL TOTAL ROWS

1716151413121
-

UM(T) -Update/Read Mode (Transparent Mode)
Update occurs during horizontal and vertical blanking
times with update strobe.
Update interleaves during 162 portion of cycle.

"0

10

1

NO. OF CHAR. ROWS -1

US(T) -Update Strobe (Transparent Mode)
Pin 34 functions as memory address.
Pin 34 functions as update strobe.

CSK -Cursor Skew
No delay
Delays Cursor one character time.

Me
4

The 7·bit Vertical Total Register contains the total number of
character rows in a frame, minus one. This register, along with
R5, determines the overall frame rate, which should be close

"0

2-122

DES -Display Enable Skew
No delay
Display Enable delays one character time.

CRT Controller (CRTC)

R6545·1
MC
3

These registers together form a 14·bit register whose contents
is the memory address of the first character of the displayed scan
(the character on the top left of the video display, as in Figure 1).
Subsequent memory addresses are generated by the R6545-1
as a result of CCLK input pulses. Scrolling of the display is
accomplished by changing R12 and R13 to the memory address
associated with the first character of the desired line of text to
be displayed first. Entire pages of text may be scrolled or
changed as well via R12 and R13.

RRA -Refresh RAM Access
Shared memory access
Transparent memory access

o
1

MC

2

RAD -Refresh RAM Addressing Mode
Straight binary addressing
Row/column addressing

o
MC
1

-Not Used-don't care

R_14_-_Ct-U_R_S_0-tR_P_O""'SL...IT_IO_N-.L.H_IG_H........L._---'-_ _L..-----i1

MC

.

o

.

.

CURSOR POSITION HIGH

-Not Used-must be a 0,

R15-CURSOR POSITION LOW

R9-ROW SCAN LINES

I~I

4

6

3

2

7

o

6

5

These registers together form a 14-blt register whose contents
is the memory address of the current cursor position. When the
video display scan counter (MA lines) matches the contents of
thiS register, and when the scan line counter (RA lines) falls
within the bounds set by R10 and R11, then the CURSOR output becomes active. Bit 5 of the Mode Control Register (R8) may
be used to delay the CURSOR output by a full CCLK time to
accommodate slow access memories ..

This 5-blt write-only register contains the number of scan lines,
minus one, per character row, including spacing.

R10-CURSOR START LINE
3

2

o

START SCAN LINE

A cursor of up to 32 characters In height can be displayed on
and between the scan lines as loaded Into the Cursor Start Line
(R10) and Cursor End line (R11) Registers.

R11-CURSOR END LINE
4

6

3

2

o

2

CURSOR POSITION LOW

SCAN LINES -1

4

4

o

END SCAN LINE

The cursor IS positioned on the screen by loading the Cursor
Position Address High (R14) and Cursor Position Address Low
(R15) registers with the desired refresh RAM address. The
cursor can be positioned in any of the 16K character positions.
Hardware paging and data scrolling IS thus allowed w~hout loss
of cursor position. Figure 3 IS an example of the display cursor
scan line.

These 5-bit write-only registers select the starting and ending
scan lines for the cursor. In addition, bits 5 and 6 of R10 are
used to select the cursor blink mode, as follows:

B,

Bo

0
0

0

1
1

0

Cursor Operating Mode
Display Cursor Continuously
Blank Cursor
Bilnk Cursor at 1/16 Field Rate
Bilnk Cursor at 1/32 Field Rate

1
1

UNDERLINE
CURSOR

A one character wide cursor can be controlled by storing values
into the Cursor Start Line (R10) and Cursor End Line (R11) registers and into the Cursor Position Address High (R14) and
Cursor Position Low (R15) registers.

BOX

OVERLINE
CURSOR

CURSOR

,II

R12-DISPLAY START ADDRESS HIGH

11

R13-DISPLAY START ADDRESS LOW
7

6

5

4

I

3

2

o

DISPLAY START ADDRESS LOW

CURSOR START
LINE = 9

CURSOR START
LINE = 1

CURSOR START
LINE = 1

CURSOR END
LINE = 9

CURSOR END
LINE = 1

CURSOR END
LINE = 9

Figure 3.

2-123

r:III

o.~

t71_615432
1_

Cursor Display Scan Line Control Examples

R6545-1

CRT Controller (CRTC)

R16-LlGHT PEN HIGH
5

7

3

4

These registers together comprise a 14-bit register whose contents is the memory address at which the next read or update
will occur (for transparent address mode, only). Whenever a
read/update occurs, the update location automatically increments to allow for fast updates or readouts of consecutive character locations. This is described elsewhere in this document.
The section on REFRESH RAM ADDRESSING describes this
more fully.

a

2

LPEN HIGH

R17-LlGHT PEN LOW
7

6

4

5

a

2

3

LPEN LOW

R31-DUMMY LOCATION
These registers together form a 14-bit register whose contents
is the light pen strobe position, in terms of the video display
address at which the strobe occurred. When the LPEN input
changes from low to high, then, on the next negative-going edge
of CCLK, the contents of the internal scan counter is stored in
registers R16 and Rl7.

7

4

5

3

a

2

5

I

3

4

a

Register pairs Rl2/R13, R14/R15, R16/R17, and R18/R19 are
formatted in one of two ways:

R19-UPDATE ADDRESS LOW.
6

2

REGISTER FORMATS

UPDATE ADDRESS HIGH

7

3

This register does not store any data, but is required to detect
when transparent addressing updates occur. This is necessary
to increment the Update Address Register and to set the Update
Ready bit in the status register.

R18-UPDATE ADDRESS HIGH
7

5

(1) Straight binary, if register R8, bit 2 = 0
(2) Row/Column, if register R8, bit 2 = 1. In this case the low
byte IS the Character Column and the high byte IS the Character Row.

a

2

UPDATE ADDRESS LOW

NUMBER OF HORIZONTAL TOTAL CHARACTERS (RO)
r---------____________
______________________
~A~

~

NUMBER OF HORIZONTAL DISPLAYED CHARACTERS (Rl)

rr----------------JA~--------------~
/

~

NUMBER OF
VERTICAL
TOTAL
ROWS
(R4)

DISPLAY START ADDRESS HIGH (R12)*
DISPLAY START ADDRESS LOW (R13)*

OF
} NUMBER
SCAN LINES (R9)

~

CURSOR START LINE (Rl0)

~ CURSOR END LINE (Rll)

CURSOR POSITION ADDRESS HIGH (R14)
CURSOR POSITION ADDRESS LOW (R15)

NUMBER OF
VERTICAL
DISPLAY
ROWS
(R6)

DISPLAY PERIOD

VERTICAL RETRACE PERIOD
(NON-DISPLAY)
VERTICAL
TOTAL
ADJUST (R5)

{
Figure 4.

Video Display Format

2-124

HORIZONTAL
RETRACE
PERIOD
(NON-DISPLAY)

R6545-1

CRT Controller (CRTC)

DESCRIPTION OF OPERATION

Shared Memory Mode (RS, BIT 3 = 0)
In this mode, the Refresh RAM address lines (MAO-MA13)
directly reflect the contents of the internal refresh scan character
counter. Multiplex control, to permit addreSSing and selection of
the RAM by both the CPU and the CRTC, must be provided
external to the CRTC. In the Row/Column address mode, lines
MAO-MA7 become character column addresses (CCO-CC7) and
MA8-MA13 become character row addresses (CRO-CR5). Figure
5 illustrates the system configuration.

VIDEO DISPLAY
Figure 4 indicates the relationship of the various program registers in the R6545-1 and the resultant video display.
Non-displayed areas of the Video Display are for horizontal and
vertical retrace functions of the CRT mon~or. The horizontal and
vertical sync signals, HSYNC and VSYNC, are programmed to
occur dUring these intervals and trigger the retrace in the CRT
monitor. The pulse widths are constrained by the monitor
requirements. The time position of the pulses may be adjusted
to vary the display margins (left, right, top, and bottom).

Transparent Memory Addressing
For this mode, the display RAM is not directly accessible by the
CPU, but IS controlled entirely by the R6545-1. All CPU accesses
are made via the R6545-1 and a small amount of external cirCUitS. Figure 6 shows the system configuration for thiS approach.

REFRESH RAM ADDRESSING
There are two modes of addreSSing for the video display memory.

SYSTEM

VSYNC

BUS
HSVNC

R6545-1
CRT CONTROLLER

DISPLAY ENABLE
RAO-RA4

TO

CURSOR

VIDEO
CIRCUITS

CPU
SCAN LINE
COUNT

SHIFT
REGISTER

~=~=~~CHARACTER
IGENERATOR
CPU
DATA
BUS

Figure 5.

CHARACTER
DATA

ROM

SCAN LINE
DOT PATTERN

Shared Memory System Configuration

SYSTEM

BUS
R6545-1
CRT CONTROLLER

RA4

MAO-MA13

UPDATE
STROBE

CPU

RAO-RA3

DISPLAY/UPDATE
ADDRESS

SCAN LINE
COUNT

CHARACTER
GENERATO
ROM
DATA
BUS

Figure 6.

CHARACTER
OATA

CHARACTER

DATA

Transparent Memory Addressing System Configuration
(Data Hold Latch Needed for HorizontallVertical Blanking Updates, Only).

2-125

fJ

R6545·1

CRT Controller (CRTC)
viable technique, since the Display Enable signal controls the
actual video display blanking. Figure 7 illustrates Refresh RAM
addressing for both row/column and binary addressing for 80
columns and 24 rows wnh 10 non-displayed columns and 10
non-displayed rows.

ADDRESSING MODES
Figure 7 illustrates the address sequence for both modes of the
Refresh RAM address.

Row/Column
Note that the straight-binary mode has the advantage that all
display memory addresses are stored in a continuous memory
block, starting with address 0 and ending at 1919. The disadvantage with this method is that, if it is desired to change a displayed character location, the row and column identity of the
location must be converted to its binary address before the
memory may be written. The row/column mode, on the other
hand, does not need to undergo this conversion. However,
memory is not used as efficiently, since the memory addresses
are not continuous, gaps exist. This requires that the system be
equipped with more memory than actually used and this extra
memory is wasted. Alternatively, address compression logic
may be employed to translate the row/column format into a continuous address block.

In this mode, the CRTC address lines (MAO-MA13) generate as
8 column (MAO-MA7) and 6 row (MA8-MA13) addresses. Extra
hardware is needed to compress this addressing into a straight
binary sequence in order to conserve memory in the refresh
RAM (register R8, bit 2 is a 1).

Binary
In this mode, the CRTC address lines are straight binary and
no compression circuits are needed. However, software complexity increases since the CRT characters cannot be stored in
terms of their row and column locations, but must be sequential
(register R8, bit 2 is a 0).

USE OF DYNAMIC RAM FOR REFRESH MEMORY

The user selects whichever mode is best for the given application. The trade-offs between the modes are software versus
hardware. Straight-binary mode minimizes hardware requirements and row/column minimizes software requirements.

The R6545-1 permits use of dynamic RAMS as storage devices
for the Refresh RAM by continuing to increment memory
addresses in the non-display intervals of the scan. This is a

,
.... - - - - - - TOTAL

I

I

DISPLAY = 80

~
80

81

82

ct

160

161

162 -.- --- 237

"

'2

------

I

--------,

77

157

78

79

80

81

---

160

161 - --

238

240

241 --- 249

239

~
f,,'I ",_10:

89

158 159

169

1

,

II

~ i ~'-r-~~-+-r--r-r7;--+--i--r~1
g °L 17~
18401841 1842

- -

1920 1921 1922 - -

1917 1918191919201921 - -

1929

1997 1998 1999 2000 2001 - -

2009

~

g
....

--- 2717 2718271927202721·-

2729

STRAIGHT BINARY ADDRESSING SEQUENCE

Figure 7.

I

COLUMN ADDRESS (MAO-MA 13)

I

77

18

79

Iso

8'

891

'2
- - - _. 77
258 - - - - - - 333

78
334

79
335

80
336

81
337

345

514 - -- --- 589

590

591

59;"!

593

GO'

0

2,~,:

."

89

:,',:

1-;,+---1---t----t--t--t--I-.--t---t--t---t--;--j
: t--7:+---1--t---t--t--t--I---,·-t---t--t---t--;--j
;

l; 2;

~:-r-li-~-+--~--t----if-;-;--+---t--r-;-;

22 563256335634 - - - - - 57095710571157125713 - - - 5721

LL: : : :::~ : : ~ ~~ -:: : : : : : : : : : --::

"
"

264026412642 -

B;

TOTAL =90
=80 ------"l

C
Q

23 5888 5889 5890 -

~

24 614461456146 - - - - - - 6221 6222622362246225 - - - 6233

- - - - 5965 59665967 5968 5969 - - - 5977

C--~~~~4--4--~~~~~~~+--f~

2000 2001 2002 - - - - - - 2077 20782079 :?OBO 2081 - - - 2089

.,

~

~ ~ ~

17611762--- --- 18371838183918401841--- 1849

....
[

DISPLAY

I

~

I
I

1

=90

ROW/COLUMN ADDRESSING SEQUENCE

Display Address Sequences (with Start Address=O) for 80 x 24 Example

2-126

R6545-1

CRT Controller (CRTC)
TRANSPARENT MEMORY ADDRESSING

MEMORY CONTENTION SCHEMES FOR
SHARED MEMORY ADDRESSING

In this mode of operation, the video display memory address
lines are not switched by contention circuits, but are generated
by the R6545-1. In effect, the contention is handled by the
R6545-1. As a result, the schemes for accomplishing CPU
memory access are different:

From the diagram of Figure 5, it is clear that both the R6545-1
and the system CPU must address the video display memory.
The R6545-1 repetitively fetches character information to generate the video signals in order to keep the screen display
active. The CPU occasionally accesses the memory to change
the displayed information or to read out current data characters.
Three ways of resolving this dual-contention requirement are
apparent:

• 1/11 and $2 Interleaving
This mode is similar to the Interleave mode used with shared
memory. In this case, however, the 02 address is generated
from the Update Address Register (R18 and R19) in the
R6545-1. Thus, the CPU must first load the address to be
accessed into R18/R19 and then this address is always gated
onto the MA lines during 02. Figure 9 shows the timing.

• CPU Priority
In this technique, the address lines to the video display
memory are normally driven by the R6545-1 unless the CPU
needs access, in which case the CPU addresses immediately
override those from the R6545-1 giving the CPU immediate
access.
• $1 and $2 Memory Interleaving
This method permits both the R6545-1 and the CPU access
to the video display memory by time-sharing via the system
01 and 02 clocks. During the 01 portion of each cycle (the
time when 02 is low), the R6545-1 address outputs are gated
to the video display memory. In the 02 time, the CPU address
lines are switched in. In this way, both the R6545-1 and the
CPU have unimpeded access to the memory. Figure 8 illustrates the timings.

'2

CLOCK

MAO .. MA13

Figure 9.

$1 and 1/12 Transparent Interleaving

~2
CLOCK

• HorizontallVertical Blanking

VIDEO

DISPlAY
MEMORY
ADDRESSES

Figure 8.

In this mode, the CPU loads the Update Address, but is only
gated onto the MA lines during horizontal or vertical blank
times, so memory accesses do not interfere with the display
appearance. To signal when the update address is on the
MA lines, an update strobe (STB) is provided as an alternate
function of pin 34. Data hold latches are necessary to temporarily retain the character to be stored until the retrace time
occurs. In this way, the system CPU is not halted waiting for
the blanking time to arrive. Figure 11 illustrates the address
and strobe timing for this mode.

1/11 and 1/12 Interleaving

• Vertical Blanking
With this approach, the address circuitry is identical to the
case for CPU Priority updates. The only difference is that the
Vertical Retrace status bit (bit 5 of the Status Register) is used
by the CPU so that access to the video display memory is
only made during vertical blanking time (when bit 5 is a 1).
In this way, no VISible screen perturbations result. See
Figure 10 for details.

CURSOR AND DISPLAY ENABLE SKEW CONTROL
Bits 4 and 5 of the Mode Control register (R8) are used to delay
Lhe Display Enable ar,d Cursor outputs, respectively. Figure 12
illustrates the effect of the delays.

2-127

fJ

R6545-1

CRT Controller (CRTC)

.

FRAME

.

VERTICAL DISPLAYED

.
FRAME

VERTICAL
BLANKING

DISPLAY
ENABLE

VERTICAL
BLANKING
STATUS
BIT
---,

~;~i~TSER

1
..___"_0_"_~_D_I_SP_L_A_Y_A_C_T_IV_E_ _~

\

BIT 5)

1 . . . - 1_

"1"
SWITCHES STATE AT
END OF LAST DISPLAYED
SCAN LINE

Figure 10;

~

_- - - - - '

VERTICAL
BLANKING
ACTIVE

Operation of Vertical Blanking Status Bit

2-128

CRT Controller (CRTC)

R6545-1

CCLK

DISPLAY
DISPLAY
ENABLE

CRT DISPLAY

I

1

t __;....._..;1I_ _.,-_ _ _NON.DISPLAY
1\._-+
_-111-1_ _ _ _ _ _...J

ADDRESSES
I
I
I
I
I
I
1- - . I
-~-----'------+I
--"I..---Ih-p-D-AT"'E+
1

MAOMA13

~ ~DDRES~

I 1---------n
1

UPSTB

1

I

I

1

I

1

I

------------------~:--~I

• _____________ _______________

~-~-

I

I
I

Retrace Update Timing

CCLK

~~,{

(NO DELAY)

(WITH DELAY)

(NO DELAY)

ENABLE
POSITIVE
EDGE

(WITH DELAY)

.~,

{

(NO DELAY)

ENABLE
NEGATIVE
EDGE

(WITH DELAY)

Figure 12.

I
I

I~-+I------------------------------------

Figure 11.

c"~.{

CRT DISPLAY ADDRESSES

1

Cursor and Display Enable Skew

2·129

fJ

R6545-1

CRT Controller (CRTC)

WRITE TIMING CHARACTERISTICS

(Vee

5.0V ± 5%, TA = TL to T H, unless otherwise noted)
R6545-1

R6545A-1

Min.

Max.

Min.

Max.

tCYC

Cycle Time

1.0

0.5

tc

02 Pulse Width

440
180

-

-

Symbol

Characteristic

t ACW

Address Set-Up Time

tCAH

Address Hold Time

t wcw

R/W Set-Up Time

tCWH

R/W Hold Time

t DCW

Data Bus Set-Up Time

tHW

Data Bus Hold Time

(tR and tF

=

0
180
0
265
10

200
90
0
90
0
100
10

Unit
~s

ns
ns
ns
ns
ns
ns
ns

10 to 30 ns)

READ TIMING CHARACTERISTICS

(Vee

5.0V ± 5%, TAT L to T H, unless otherwise noted)
R6545-1

Characteristic

Symbol

R6545A-1

Min.

Max.

Min.

Max.

05
200

-

Unit

tCYC

Cycle Time

1.0

tc

02 Pulse Width

440

-

t ACR

Address Set-Up Time

180

-

90

-

ns

tCAR

Address Hold Time

0

0

R/W Set-Up Time

180

90

-

ns

t WCR

-

tCDR

Read Access Time (Valid Data)

-

340

-

150

ns

tHR

Read Hold Time

10

-

10

-

ns

tCDA

Data Bus Active Time (Invalid Data)

40

-

40

-

ns

(tR and tF

=

10 to 30 ns)

READ TIMING WAVEFORMS

WRITE TIMING WAVEFORMS

02

02

CS, RS

CS, RS

RiW

RiW

DATA BUS

DATA BUS

2-130

~s

ns

ns

CRT Controller (CRTC)

R6545-1
MEMORY AND VIDEO INTERFACE CHARACTERISTICS
(Vee = 5.0V ± 5%, TA = TL to TH , unless otherwise noted)

R6545A-1

R6545-1
Symbol

Characteristic

Min.

Max.

Min.

Max.

Unit

tCCY

Character Clock Cycle Time

0.40

-

040

-

I's

tCCH

Character Clock Pulse Width

200

-

200

-

ns

(X)tMAD

MAO-MA 13 Propagation Delay

-

300

-

300

ns

(X)tAAD

RAO-RA4 Propagation Delay

-

300

-

300

ns

(X)tDTD

DISPLAY ENABLE Propagallon Delay

-

450

-

450

ns

(X)t HSD

HSYNC Propagation Delay

-

450

-

450

ns

(X)tVSD

VSYNC Propagallon Delay

-

450

-

450

ns

(X)tCDD

CURSOR Propagation Delay

-

450

-

450

ns

MAO-MAI3 SWitching Delay

-

200

-

200

ns

tTAD
Note' t R, tF

=

20 ns (max).

SYSTEM TIMING WAVEFORMS

t- ''" :::j'"

CCLK
OUTPUTS
(SEE TABLE)

~

~

TRANSPARENT ADDRESSING
WAVEFORMS (f/l1/f/l2 INTERLEAVING)

1

~

~ir---~""_ _ __

MAOMA13

LIGHT PEN STROBE TIMING CHARACTERISTICS
R6545-1
Symbol

Characteristic

R6545A-l

Min.

Max.

Min.

Max.

Unit

-

150

-

ns

t LPH

LPEN Hold Time

150

t LP1

LPEN Setup Time

20

t LP2

CCLK to LPEN Delay

0

20
0

Note: t A, tF = 20 ns (max)

LIGHT PEN STROBE TIMING WAVEFORMS

cc,,~

~

LPEN

MAO-MA13 _______
n ____

-J)(~_____n_+_l____J)(~_____n+_2_____J~

NOTE: "Safe" time position for LPEN positive edge to cause
address n+2 to load into Light Pen Register.
~P2 and t LP1 are time positions causing uncertain results.

2-131

ns
ns

fJ

CRT Controller (CRTC)

R6545·1
ABSOLUTE MAXIMUM RATINGS*
Parameter
Supply Voltage

Symbol

Value

Unit

Vee

-0.3 to + 7.0

Vdc

-0.3 to + 7.0

Vdc

Input Voltage

VIN

Operating Temperature Range
Commercial
Industrial

TA

Storage Temperature

TSTG

·NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this document is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

·C
Oto +70
-40 to +85
-55 to + 150

~C

DC CHARACTERISTICS
(Vee = 5.0V

±5%,

TA = T l to T H, unless otherwise noted)
Min.

Max.

Unit

Input High Voltage

Parameter

Symbol
VIH

2.4

Vee

Vdc

Input Low Voltage

VIL

-0.3

0.4

Vdc

Input Leakage (02, RIW, RES, CS, RS, LPEN, CCLK)

liN

-

2.25

"Adc

Three-State Input Leakage (00-07)
(VIN = 0.4 to 2.4V)

ITSI

-

±10.0

~Adc

Output High Voltage
ILOAD = 205 ~Adc (00-07)
ILOAD = 100 ~Adc (all others)

VOH

24

-

Vdc

Output Low Voltage
ILOAD = 1 6 mAdc

VOL

-

0.4

Power Dlssipallon

Po

-

900

mW

-

10.0
125

pF
pF

100

pF

Input Capacitance
02, RAN, RES, CS, RS, LPEN, CCLK
00-07

CIN

Output Capacitance

COUT

-

TEST LOAD
Vcc

2.4K!l
I ...

....

R6545-1 PIN

C1

R

-=

V

~7

~~:..
-=

=llK!l FOR 00-07
=24K!l FOR ALL OTHER OUTPUTS
C =130 pF TOTAL FOR 00-07
=30 pF ALL OTHER OUTPUTS
R

2-132

Vdc

R6545-1

CRT Controller (CRTC)

-

PACKAGE DIMENSIONS

-

4O-PIN CERAMIC DIP

~;
I

MILLfMETEAS

I

I

]l
I

~

~'IIIIIIIIIIIIIIWV~c-'~F1
LD
~
I'

-iG ,-

K

-II- J

1-

L

--=l

INCHES

DIM

MIN

MAX

MIN

MAX

~

5029

5156

1980

2030

B

1473

1549

0500

0610

C

178

305

0070

0120

I-"-F

038

058

0015

0023

102

'.5

0010

0065

G

229

260

0090

0110

J

020

038

0008

0015

•
L

318

381

0125

0150

'499

1651

0590

0650

M

0'

N

058

10'
178

0'

10'

0020

0070

M

4O-PIN PLASTIC DIP

[:::::::::::::::::::I~cC

I

A-

I

~WMETERS

L-]

~~~~

2-133

INCHES

DIM

MIN

MAX

10.

MAX

A

S128

5232

2040

2060

B

0580

1372

1422

0540

C

355

508

0140

0200

D

036

051

0014

0020

F

, 02

15'

0040

0060

G

2!i48SC

0100

esc

H

165

218

008510085

J

020

030

0008

K

305

356

o 12OTol40
0600 esc

L
M

L...!

1524BSC
,.
10'

051

102

0012

,.

10-

002{)

0040

fJ

R6549

'1'

Rockwell

R6549
COLOR VIDEO DISPLAY GENERATOR (CVDG)
PRELIMINARY

DESCRIPTION

FEATURES

The Rockwell R6549 Color Video Display Generator (CVDG)
integrates video raster control; color lookup table (LUT) update
and access; color generation and display refresh; teletext data
DMA addressing, data routing and handshake; dynamic RAM
(DRAM) control and refresh; and MPu/CVDG/DMA access to
DRAM into a single device. Internal horizontal and vertical state
machines generate video synchronization signals and control
access of video color data from DRAM. A 16-entry color lookup
table (LUT) supports 4-bit encoded color levels for red, green
and blue (RGB) colors allowing 4096 color combinations to be
generated. Each color code is converted to a 16-level analog
signal by a dedicated DAC, combined with a blanking signal,
and output in sync with a pixel clock.

• High performance video generator
-2:1 or 1:1 interlace
- Analog red, green, blue (RGB) outputs
- 16 levels per color plus blanking
- 4096 color combinations
- RS-HO sync and color subcarrier generation
-16 entry color look-up table (LUT)
- RS-170 composite sync output with equalization and
serration pulses
- Internal/external video synchronization
- Color subcarrier generation with line, field and pixel phase
lock
- Compatible with MC1377 color encoder

Control registers allow MPU selection of CVDG operating mode
and options while data registers allow MPU update of LUT data,
current drawing pOinter (COP) graphics, Y scroll pointer and
teletext pointer. The data registers can also be monitored by
the MPU as can mode and raster scan status.

• Videotex (VTX)/Teletext (nX) graphics
- 256 x 210 x 4 bit-mapped video image buffer
- Programmable border color
- Transparent video overlay signal
- Fast X COP and Y COP nibble or byte graphics I/O
- NAPLPS X - Y origin with smooth Y vertical scroll
- Fast horizontal drawing support with X auto increment byte
write

The R6549 is the first display generator to be designed exclusively in support of North American Presentation Level Protocol
Syntax (NAPLPS) videotex (VTX) and teletext (TTX).

• Dynamic RAM interface
- Direct 48k-byte DRAM support, with auto inherent refresh
for interfacing to six 16k x 4 DRAMS (4416-150 ns)
- Supports three methods of DRAM access:
- Video refresh 26.9k-byte DRAM-port or address
mapped
- Teletext/program 5.9k-byte DRAM-port or address
mapped
- Optional program 16k-byte DRAM extension-address
mapped
- Interleaving of MPU and CVDG DRAM access for uninterrupted read/write memory access without memory
contention
- On-Chip refresh timing and control

Replacing over 30 conventional MSI/LSI devices, the R6549
simplifies system design and layout, reduces printed circuit size,
and minimizes required support circuits to speed system prototyping and greatly reduce both development and production costs.
Rm
ADO
AD1
AD2
AD3
AD4
AD5
AD8
AD7
DTIME
VCC
CTIME
RTIME
OE1
OE2

Vi
mt
Rmi
CAS1

em

1
2
3
4
5
8
7
8
9
10
11
12
13
14
15
18
17
18
19
20

40
39
38
37
38
35
34
33
32
31
30
29
28
27
28
25
24
23
22
21

A13
A1
AO
ORCS
IOCS
XPAR
RED
GREEN
BLUE
GND
C/HSYNC
VSYNC
PIXCK
TTXOE

• MPU Interface
- Direct timing and cycle stealing for 1.4 MHz 68A09E MPU
- Direct interface to R6512 CPU
• Teletext support
- DMA interface and handshake to external NABTS teletext
prefix processor
- 5.72 Mbps effective data rate
- 8k-byte teletext buffer DRAM interface

l'Ti"imi

ORDERING INFORMATION

SYSCLK
CSUBC
Q

E

CUJS

Part Number

Temperature Range

R6549

O·C to 70·C

1

Package: P _ Plastic

R6549 CVOG Pin Assignments
Document No. 29651N86
2-134

Product Description Order No. 2183
September 1984

Color Video Display Generator (CVDG)

R6549

TELETEXT
PREFIX
PROCESSOR

{

RASL

TTXREQ

RASH

TTXOE

CAS1

MPU
CONTROL &
ADDRESS
LINES &
CHIP
SELECTS

E

CAS2

Q

CASP

R/W

OE1

AD

OE2

A1

W

A13

RTIME

IOCS

CTIME
R6549
CVDG

ORCS

DTIME
SYSCLK

ADDRESSI
DATA
BUS

{

(

AADD-AD7 "
8

PIXCK

"I

CSUBC

..."

DRAM
CONTROL

}

28.636363 MHz
SYSTEM CLOCK

C/HYSYNC
VSYNC
XPAR
R

VIDEOI
COLOR
OUTPUT

G
B

Figure 1. R6549 CVDG Interface Signals

PIN DESCRIPTION

causes the CVDG to stop generating the E and Q clocks for one
AID bus cycle, output a 13·bit address (AO - A 12) to the DRAM
during the processor portion of the AID bus cycle, assert the
TTXOE signal, and assert the W output to enable writing the
data into DRAM.

Throughout this document signals are described logically using
the terms active (or asserted) representing the true state, or inactive (or negated) representing the false state, regardless of
whether the signal is active at a high or low voltage level.

TTXOE-Teletext DMA Output Enable. An active LOW TTL
compatible output pulse asserted within one AID bus cycle after
TTXREQ is asserted to acknowledge TTXREQ receipt and to
enable data transfer from the teletext prefix processor onto the
AID bus (ADO - AD?).

The R6549 CVDG signals can be categorized into several dif·
ferent functional interfaces: MPU control and address bus,
address/data (A/D) bus, DRAM control, color video output,
teletext prefix processor and system clock input. Figure 1 iden·
tifies the signals within each group.

MPU CONTROL AND ADDRESS BUS
DMAC INTERFACE

E-E Clock. A TTL compatible 1.43 MHz output clock that
synchronizes data transfers over the MPU bus. This output drives
the E clock input to the 6809E MPU. The E clock has special
VO H and VOL output levels, Vee - O.5V and Vss + O.3V,
respectively.

TTXREQ-Teletext DMA Request. An asynchronous falling
edge-triggered request for direct memory access (DMA) transfer
of data from a teletext prefix processor connected to the
address/data (A/D) bus to DRAM. This TTL compatible input

2-135

fJ

R6549·

Color Video Display Generator (CVDG)

Q-Q Clock. A TIL compatible 1.43 MHz output clock that leads
the E clock output for use by the 6809E.

DRCS-DRAM Chip Select. ORCS is a TIL compatible, active
LOW, input that enables MPU access to the DRAM. CTIME,
RTIME and DTIME outputs are asserted by the CVDG at the
proper times to enable external buffers which drive the MPU
generated address onto the AID bus and drive data between
the MPU bus data lines and the AID bus In the direction controlled by RiW (HIGH = read from DRAM; LOW = write to DRAM).
Note that DRCS configurations are advanced and optional for
many configurations.

R/iN-ReadIWrlte. The TIL compatible ReadlWrite input
controls the direction of data transfer between the MPU and the
CVDG (HIGH read from the CVDG; LOW write to the CVDG).
The RNi line should be connected to external data bus transceivers to also control the data direction between the MPU bus
and the AID bus.

=

=

ADDRESS/DATA BUS
ADD-AD7-Address/Data Lines. Eight TIL compatible,
bidirectional, multiplexed address/data lines (ADO - AD7) interface the CVDG directly to the video/program DRAM, through
external buffers to the MPU address bus (A 1 - A12), and through
external transceivers to the MPU data bus (DO - D7). These lines
transfer both address and data between the DRAM and the
CVDG and between the MPU bus and the CVDG/DRAM during
one 698 ns AID bus cycle.

AO, Al-MPU Address Line AD and A1 Inputs. When IOCS
is active, the encoded AO and A 1. inputs select the register in
the CVDG to be accessed during a read or write operation (see
Table 1). An exception is when AO and Al are both high during
Mode 0, in which case DRAM is CDP accessed directly by the
MPU at addresses generated by the CVDG.
When DRCS is active and program DRAM is selected (P = 1 in
the DRAM Page Register), AO is passed through the CVDG to
drive the AD6 output during DRAM column address generation
in the processor portion of the AID bus cycle (see MPU DRAM
Access Description).

RASL, RASH-Row Address Strobe Low and High. TIL compatible outputs strobe the upper eight bits of the address on AID
bus lines ADO-AD7 into DRAM (as DRAM addresses A6-A13)
on the falling edge. RASL strobes the address into the
DRAM containing the lower four data bits (DO-D3) and RASH
strobes the address into the DRAM containing the upper four
data bits (D4-D7).

A 13-MPU Address Line A 13 Input. When DRCS is active, A 13
input HIGH causes program DRAM to be accessed (CASP
asserted) during the processor portion of the AID bus cycle
independent of the P bit value in the DRAM Page Register. When
program DRAM is selected in the DRAM Page Register (P = 1)
or when A13= 1, A13 Is passed through the CVDG to drive the
AD5 output during DRAM column address generation in the
processor portion of the AID bus cycle (see MPU DRAM Access
Description).

CAS1, CAS2, CASP-Column Address Strobes 1, 2 and P.
The TIL compatible CAS outputs strobe the six lower bits of
the address on AID bus lines (AD1-AD6) into DRAM (as DRAM
addresses AO-A5) on the falling edge. CASl and CAS2 connect
to the video DRAM containing the LUT addresses. Four 4-bit
LUT addresses packed into two bytes are accessed during the
video portion of each AID bus cycle. CASl strobes the DRAM
containing the LUT addresses for the first two pixel positions
while CAS2 strobes the DRAM devices containing the LUT
addresses for the second two pixel positions. ~ connects
to the program DRAM containing the program instructions/data.

IOCS-I/O Chip Select. The active LOW, TIL compatible,
10CS input selects CVDG I/O port operation. The CVDG internal
registers addressed by the AO and Al inputs are accessed as
enabled by the mode selected in the Mode Register. Data direction is controlled by the RNi input as appropriate for each
register and mode.
Table 1.
A1

AD

L
L
H
H
H
H
H
H
H
H

L
H
L
H
H
H
H
H
L
H

OE1, OE2-DRAM Output Enable. These active LOW, TIL
compatible, outputs enable DRAM device data output lines during a read. OEl connects to the two video DRAM devices
containing byte 1 (LUT addresses for pixels 1 and 2) and is
asserted first during a video refresh cycle. OE2 connects to the
two DRAM devices containing byte 2 (LUT addresses for pixels 3
and 4) and is asserted following 0E1. OE2 is also connected
to the program DRAM devices and enables their data outputs
during the processor portion of the AID bus cycle.

CVDG Register Select Logic (IOCS=LOW)

Model

-

0
0
0
1

2
3
4

5
6

Read (RIW =H)
Status Register
X CDP Register
Y CDP Register
DRAM2

-

LUT3

-

Write (RIW=L)
Mode Register
X CDP Register
Y CDP Register
DRAM2
LUT Address Register
LUT Data Register
Switch Register
Y Scroll Register
Pointer Register
DRAM Page Register

iN-DRAM Write Enable. The TTL compatible, active LOW, Vii
output strobes data from the AID bus into DRAM during a write
in the processor portion of the AID bus cycle. Vii is held HIGH
during a read from DRAM.

TTX Pointer Register nx
-

RTIME-Row Address Time. The active LOW, TIL compatible,
RTIME output enables DRAM row address lines from the MPU
onto the AID bus through external buffers when ORCS is active.
(Required for ORCS configurations only.)

Notes:
1. The mode is selected in Mode Register.
2. DRAM is accessed directly by the MPU at DRAM addresses
determined by the CVDG X CDP and Y CDP register contents
3 The LUT is accessed as enabled and addressed in the LUT
Address Register.

CTIME-Column Address Time. The active LOW, TIL compatible, CTIME output enables DRAM column address lines
from the MPU onto the AID bus through external buffers when
ORCS is active. (Required for ORCS configurations only.)

2-136

R6549

Color Video Display Generator (CVDG)

DTIME-Data Time. The active LOW, TTL compatible, DTIME
output enables data transfer between the MPU data bus and
the AID bus through external transceivers when DRCS or lacs
is active.

PIXCLK-Pixel Clock Output. A 5.7272 MHz pixel output clock
running synchronously with the RGB color outputs.
R, G, B-Red, Green and Blue Color Outputs. Three separate
color analog output voltages. Each output provides a 1.0 Vpp
video signal at high impedance with a 1.8 Vdc offset. Each color
level is controlled by a 4-bit color code accessed from the LUT
for each pixel position. A digital-to-analog converter (DAC)
converts the 4-bit code to one of 16 output voltage levels (black
level = 1.875 Vdc; white level = 2.800 Vdc). The three outputs
allow 4096 color level combinations. A composite blanking signal
(1.800 Vdc) is included in each output.

SYSTEM CLOCK
SYSCLK-System Clock. A clock input with a duty cycle of
40/60 to 50/50. The clock frequency should be 28.63636 MHz
±80 Hz for proper operation of the colorburst frequency. This
input clock may be stopped in either state for up to 1 p,s to allow
for external digital phase lock techniques.

VIDEO/COLOR OUTPUTS

The output signals include high frequency clock components
which may require low pass filtering in some applications. The
outputs can be connected to the R IN, G IN, and B IN inputs
to a MC1377 color encoder through 15 p,F (typical) AC coupling
capacitors.

CSUBC-Color Subcarrier Clock Output. A TTL compatible
3.579545 MHz ± 10% color subcarrier clock. The clock rate complies with the North American Color Burst Clock Output
Standard. The rate is the SYSCLK divided by eight and is phase
keyed to the horizontal sync (HSYNC) output on C/HSYNC (as
either a component of CSYNC or pure HSYNC). Vertical blanking
interval (VBI) color gating by VSYNC must be done externally
(since some modems require an uninterrupted 3.579 MHz cloCk).

The color outputs, through external buffers, can also drive
75 ohm loads, e.g., the inputs to an RGB color monitorlTV.
XPAR-Transparent Output. A TTL compatible, active HIGH,
output controlled by one bit in a 4-bit code (three bits are don't
care) in the LUT. A LUT value of 1XXX in DRAM asserts XPAR
(HIGH); LUT value of OXXX in DRAM negates XPAR (LOW). This
output can be used to indicate which video source to select.
When XPAR output is HIGH, external video signals should be
selected to display background video; when XPAR output is
LOW, CVDG outputs should be selected to display graphics. The
XPAR output is always HIGH during composite blanking to pass
external vertical blanking interval (VBI) Signals, external sync,
color burst, etc.

When the color outputs are connected to an MC1377 color
encoder, the CSUBC output can be connected to the MC1377
CLK input, typically through a 500 pF capacitor/150 p,H inductor
filter network.
C/HSYNC-Composite/Horizontal Sync Output. Either a
composite sync (CSYNC) or a horizontal sync (HSYNC) output
at TTL levels, asserted' 'tips down", is selected by the External
Sync (EXT) bit in the Switch Register.
In internal sync (EXT = 0), an RS-170 composite sync with full
serration and equalization is output in either 2: 1 or 1: 1 interlace
as selected by the 2:1 Interlace Select (S21) bit in the Switch
Register (S21 = 1 for 2:1; S21 = 0 for 1:1).

POWER/GROUND
VCC-Primary Power. 5.0 Vdc.
VSS-Ground. Power and signal ground.

In external sync (EXT = 1), a pure HSYNC is output in either
normal or early timing as selected by the Normal Horizontal Sync
(NHS) bit in the Switch Register. In normal timing (NHS = 1),
a 15.7 kHz signal is output; in advance timing (NHS = 0), a
15.9 kHz stop clock signal is output.

The R6549 CVDG operation is controlled by three free-running
synchronous state machines with the following cycle rates:

When the color outputs are connected to an MC1377 color
encoder, the C/HSYNC output can be connected directly to the
MC1377 SYNC input pin.

Address/Data (A/D) Bus Cycle
Horizontal Raster Line Cycle
Vertical Raster Frame Cycle

VSYNC-Vertical Sync Input/Output. A TTL compatible
vertical sync (VSYNC) input or output signal depending on the
state of the External Sync (EXT) bit in the Switch Register (see
Mode 3). VSYNC is an externally generated input at power up
or when EXT = 1. VSYNC is an internally generated output
when EXT = O.

The CVDG also includes timing shift registers and sample flipflops to generate internal and external timing signals; programmed logic arrays (PLAs) to perform I/O decoding, generate
DRAM control signals and determine state machine outputs;
registers to hold command/status and data; an internal 16-bit
row/column bus in display X-V coordinates; internal input and
output 8-bit data busses; and input/output buffers to isolate
internal circuits from external interfaces and to drive outputs.
Figure 2 illustrates the main CVDG components.

FUNCTIONAL DESCRIPTION

The VSYNC output can be used to disable the color subcarrier
at the chroma modulator during VBI. Videotex decoders can also
use VSYNC to interrupt the MPU at a 60 Hz rate for blink, task
and timekeeping operations.

*A

2-137

698 ns/cycle (1.43 MHz)
63.5 p,s/cycle (15.74 kHz)*
33.3 ms/cycle (30 Hz)

15.9 kHz stop-clock early sync is selectable.

fJ

lJ

INTERNAL
16-BIT
:8~ & COLUMN (RC)

TTX
DMA
CONTROL
& BUFFERS

TTXREQ
TTXOE

2

T
2

8
AID BUS
CONTROL
LINE
BUFFERS
&
LOGIC

Al
"T1

cC
c

iil
!'>
::D

I)J

c;J


= VIDEO REFRESH
ROW ADDRESSES

300

255

PIXEL X LOCATION

NOTES:
1. Vertical State Transition (HS28)
2. Vertical State Transition and HSYNC (HS73)
3. Symbol. definitions:
HBLANK = Horizontal Blanking
IHBLANK = Horizontal Border and Blanking
VBLANK = Vertical Blanking
IVBLANK = Vertical Border and Blanking
CBLANK = HBLANK + VBLANK = Composite Blanking
ICBLANK = = IHBLANK + IVBLANK = Composite Borders and Blanking
4. Shading Legend:

!] Active Pixel Display Region

IZI
I:SI

Top and Bottom Borders

o

Blanking Region

Right and Left Borders

~ Composite SYNC (CSYNC)

Figure 3.

CVDG Video Raster Count Reference

2-140

Color Video Display Generator (CVDG)

R6549
ADDRESS/DATA BUS CONTROL

The E and Q output clocks are suppressed during a teletex1 DMA
transfer. When TTXREQ input goes LOW, the Q and E clock
outputs are held LOW to disable the clocks for one MPU bus
cycle. In addition, the increment TTX address count goes HIGH
to increment the modulo 32 TTX Counter. When TTXREQ goes
HIGH at the completion of the DMA data transfer, the E and
Q output clocks are enabled, the TTXOE output is negated
(reset HIGH), and the increment TTX address count signal is
reset.

The Address/Data Bus state machine controls the operation of
the 698 ns A/D bus cycle. The AID bus cycle contains a 2-byte
video data access cycle and a 1-byte I/O data access cycle
(Figure 4). The addresses and data transferred on the A/D bus
depend on the phase of the AID bus cycle (i.e., the E clock level)
and the type of operation in the I/O data access cycle. Table 2
identifies the source of the addresses for each type of DRAM
access.

Internal reset and initialization signals are generated when both
10CS and DRCS inputs are LOW for test purposes.

Video Data Access Cycle
The video data access cycle (also referred to as the video portion
of the A/D bus cycle) occurs during the first half of the A/D bus
cycle (when the E clock is LOW). Two bytes of video data
(containing four LUT addresses corresponding to four pixellocations on the display) are read each cycle from DRAM at the
DRAM address generated by the CVDG. The DRAM address
is generated corresponding to the first of four pixel column locations in the horizontal raster and the pixel row location in the
vertical raster. The video column (X) address of 0 to 64 is controlled by the horizontal state machine. The video row (Y) address
of 209 to 0 is controlled by the Y Address Counter, which is in
turn controlled by the vertical state machine and the Y Scroll
Register. The two data bytes are loaded into the CVDG Video
Data Register for subsequent serialization and LUT access (see
the Pixel Color Generation description).

A/D Bus Control PLA
The AID Bus Control PLA decodes CVDG and AID Bus operation commands from buffered AID bus control input signals and
encoded mode bits in the Mode Register. Outputs from the PLA
are buffered and routed to other circuits in the CVDG as internal enable signals.

A/D Bus Input/Output Buffers
The AID Bus Input/Output Buffers isolate the internal CVDG data
bus lines from the external AID bus lines (ADO - AD?). Input buffers continuously copy ADO - AD? onto the internal input data
bus. Output buffers drive the states of the internal output data
bus lines onto ADO - AD? when enabled by a CVDG output function and clocked by the 14.3 MHz internal clock. Two of these
output buffers drive AD5 and AD6 during MPU DRAM access
(DRCS = L) with the DRAM page Signals, i.e., VO and
V1, respectively, or A13 and AO inputs, respectively, depending
on the state of the A13 input and the P bit in the DRAM Page
Register.

Up to 48k-bytes of Dynamic RAM (DRAM) can be connected to
the AID bus to store video data (LUT addresses) for video refresh,
program instructions/data and received teletext data. The DRAM
is segmented into six 8k-byte blocks with page selection of one
block at a time during access (Figure 5). Four pages are required
for video refresh (VOO - V11); three pages (VOO, V01 and V10)
hold video data eXClusively, and one page (V11) holds video and
programlteletext data. Two other pages hold program data. During the video data access cycle, and some modes of the I/O data
access cycle, paging is handled automatically by the CVDG. The
A13 and AO input lines and the P, V1 and VO bits in the CVDG
DRAM Page Register select the page for MPU DRAM access
during the I/O data access cycle (see MPU DRAM Access
description).

AID Bus Output Control Logic
Thfl AID Bus Output Control Logic drives data onto the internal
output bus from the internal row and column bus lines, from the
LUT, and from other internal CVDG circuits when enabled by
outputs from the AID Bus Control PLA.

DRAM Control PLA and Buffers
The DRAM Control PLA and Buffers generate and drive control
and timing output signals to the DRAM; the row, column and
data time output control signals for use by external line buffers
and data line transceivers; and internal signals to control
input/output data direction and to enable the internal row and
column bus.

I/O Data Access Cycle
The I/O data access cycle (also referred to as the processor
portion of the AID bus cycle) occurs during the second half of
the AID bus cycle (when E clock is HIGH). AID bus address
source and data source/destination depends upon CVDG chip
select (lOCS and DRCS) and Teletext Request (TTXREQ)
input levels, the selected CVDG mode, and the register select
(AO and A1) input levels. Refer to the description of each I/O
access cycle function for details.

Timing pulses from the Timing Shift Registers; control signals
from the Mode and Page registers, AID Bus Control Buffers and
Logic, and AID Bus Control PLA; and control signals generated
and derived from other sections of the CVDG are input to the
PLA.

A/D Bus Control Line Buffers and Logic

Output control states from the PLA are buffered and routed to
external DRAM control signal pins (RASL, RASH, CAS1, CAS2,
CASP, OE1, OE2, and IN) and to external AID bus control
signal pins (CTIME, RTIME and DTIME). Other output
signals are inverted and routed to internal logic.

The AID Bus Control Line Buffers and Logic condition input and
output AID Bus control signals. Six input signals (RfW, AO, A1,
A13, 10CS and DRCS) are buffered and routed to the DRAM
Control PLA.

2-141

PI

Color Video Display Generator (CVDG)

R6549

1"'1·~--------698ns --------~..~I
a

_ _ _ _....II

E

, ' -_____---JI

\....._ - - - -

""'1,.r---VIDEOTlME--_,,-rI,..
.. --PROCESSOR TIME-----.j

\___
r- RASL AND/OR RASH

RASL AND RASH

~~~----~/~~\~-----------CASl AND CAS2

CASP, CASl OR CAS2

--~;---\~~------~~~------

WRITE

,-READ

-r-

READ

,-wRiTE - ,

w

.

VIDEO DATA ACCESS
ADO-AD7

Figure 4.

DRAM Address/Dsta (A/D) Bus Cycle

2-142

.

I/O DATA ACCESS

Color Video Display Generator (CVDG)

R6549
Table 2.
DRAM Row/Column
CVDG Display Row/Column Bus
AID Bus
Video Cycle'

-

Address/Data Bus Address Sources

-

CAS

CA4

CA3

CA2

CA1

CAO

RA7

RAS

RA5

RA4

RA3

RA2

RAI

C7

CS

C5

C4

C3

C2

Cl

CO

R7

RS

R5

R4

R3

R2

Rl

RAO
RO

AD7

ADS

ADS

AD4

AD3

AD2

ADI

ADO

AD7

ADS

ADS

AD4

AD3

AD2

AD1

ADO

0

V7

VS

V5

V4

V3

V2

0

VI

VO

HS

H5

H4

H3

H2

HI

X1 3

Y7

YS

Y5

Y4

Y3

Y2

X04

Yl

YO

X7

XS

X5

X4

X3

X2

A06

VF

V02

A12

All

Al0

A9

0

A8

A7

A6

A5

A4

A3

A2

AI

0

A09

A13 9

A12

Al1

Al0

A9

0

A8

A7

A6

A5

A4

A3

A2

AI

TO

1"

1"

T12

Tl1

Tl0

T9

0

T8

T7

T6

T5

T4

T3

T2

Tl

Processor Cycle
COP Graphics2
(IOCS = L, Mode 0)

MPU Video DRAM Access5
(ORCS = L, P = 0)

MPU Program DRAM Access8
(ORCS = L, P = 1)

Teletext DMA Access' 0
(TTXREQ = L)
Notes:

1. Video Cycle:
H1 - H6 = HSM Output = 0 to 64 (= 0 to 255 pixel LUT addresses @ 4 addresses per access);
VO - V7 = Y Scroll Counter Output = 209 to 0
2. COP Graphics:
XO - X7 = X COP Register/Counter contents = 0 to 255;
YO - Y7 = Y COP Register contents = 0 to 255 (0 to 209 for displayable data)
3. X1 controls the CAS1 and CAS2 outputs:
o = Assert CASI
1 = Assert CAS2
4. XO controls the RASL and RASH outputs:
o = Assert RASL
1 = Assert RASH
5. MPU Video DRAM Access: AO-A12 = MPU Address = 0 to 4096.
S. AO input controls the CASI and CAS2 outputs:
L = Assert CAS1
H = Assert CAS2
7. VO and V1 bits in the DRAM Page Register control assertion of AD6 and ADS outputs, respectively:
o = Negate output
1 = Assert output
8. MPU Program DRAM Access: AO-AI3 = MPU Address = 0 to 8192
9. AO and A13 inputs control the AD6 and ADS outputs, respectively:
L = Negate output
H = Assert output
10. Teletext Access:
Tl - T4 = Modulo 32 counter incremented by each DMA byte transfer
T5- T12 = Teletext Pointer Register contents incremented by Tl - T4 overflow
11. ADS and ADS asserted to select program DRAM.

I

2·143

fI

Color Video Display Generator (CVDG)

R6549
DRAM Page
Register
A13

P

V1

VO

1

1

X

X

a

a

a

1

a

a

X

1

1

X

1

Addr
(Hex)

Addr
(Dec)

lFFF

8191

{
{

a

a
8191

a

a

lFFF

8191
}
Video 3 (Vll)

0.900
a8FF

2304
2303

a

a

lFFF

8191

a

0

a

a

a,209J. 1,20.9

---

a

Note 2

a
8191

VIDEO'
DATA
Video 1 (Val)

1

a

----

PROGRAMI
TELETEXT

Video 2 (Vla)

a
0

PROGRAM

Program a
(A13 = a)

" lFFF

a

Memory Function

Program 1
(A13 = 1)

lFFF

{

Memory Page

a

a

lFFF

8191

{

Video

---al---254,0.
255,0.

a

0

a (vaa)
Note 2

Notes:
1. 26,880 bytes of video memory are required to support video refresh, i.e" to supply 53,760. 4-bit LUT addresses in support of the
210. x 256 pixel display area. With 32,768 bytes supplied in four 4416 DRAM deVIces, 5888 bytes are available for general
program/TTX message use in the upper part of video memory page 3 (Vll).
2. Nibbles shown correspond to beginning and ending data for 21 a x 256 pixel display area in X(column), Y(row) coordinates.

Figure 5.

DRAM Memory Map

2-144

Color Video Display Generator (CVDG)

R6549
PIXEL COLOR GENERATION

parent state (see Table 3). Each entry holds three 4-bit encoded
color levels (0000 = lowest voltage level, 1111 = highest voltage
level) and a 1-bit transparent state (0 = off, 1 =on). For each pixel
location the three color level codes (R, G and 8) are sampled
from the lUT, latched and routed through three separate digitalto-analog converters. The transparent bit corresponding to each
pixel location is also accessed from the lUT, latched, buffered
and output on the XPAR pin.

LUT Address Generation
The 16-bit Video Data Register latches the four LUT addresses
contained in the two data bytes acquired during the video data
access cycle. Two 4-bit color lookup table (LUT) addresses are
packed into each byte. The Video Shift Register serializes the
four LUT addresses and transfers them one byte at a time to
the LUT Address Generator. The LUT Address Generator latches
the 4-bit coded LUT addresses from the Video Shift Register,
converts the coded address to 16 binary signals and latches the
binary address (0-15) for routing to the LUT.

Digital-To-Analog Conversion (DACs)

a

The 4-bit color code for each color (R, and B) at a pixel position is converted to a corresponding analog voltage through a
16-level digital-to-analog converter (DAC). Four lines from the
four color code lines and their four complements are decoded
to one of 16 levels, sampled and latched. The latched outputs
are in turn connected to the color output pin (R, G and 8) through
a voltage divider ladder network.

LUT Operation
The color look-up table (LUT) is a 16 x 13 bit memory holding
16 entries of R, G and 8 color codes and corresponding trans-

Table 3.

lUT Structure

LUT FORMAT
LUT
AD DR
(HEX)

3

F
E

0
C

0

A

8
7
6
5

4
3
2
1
0

/' /' /'
/ 1/V
1/V /

V V V
/ 1/V

RED2

BLUE2

3

2

1

0

3

2

1

0

3

2

1

0

0

0

0

0

0

1

0

0

0

1

1

1

Example 13

1

0

0

0

1

1

0

0

1

1

1

1

Example 24

1/1/ /

B

9

GREEN2

XPAR'

1

1/ NO
1/ ACTUAL
V DATA

/
/
/

1/1/ /
1/1/ /
1/V V

V V V
1/1/V
1/1/ 1/
1/V V
V V V

Notes:
1. XPAR IS a single bit In the LUT, the format shown corresponds
to the LUT Data Register format:
OXXX = XPAR output LOW
lXXX = XPAR output HIGH
2. Color Data Level:
0000 = lowest output voltage = 1.875 Vdc
1111 = highest output voltage = 2.800 Vdc

3. Example l-LUT Address C Data
XPAR output = LOW
G output = 1.875 + 0 (0.0617) = 1.875 Vdc
B output = 1.875 + 4 (0.0617) = 2.122 Vdc
R output = 1.875 + 7 (0.0617) = 2.307 Vdc

4. Example 2-LUT Address 9 Data'
XPAR output = HIGH
G output = 1 875 + 8 (0.0617) = 2.369 Vdc
B output = 1.875 + 12 (0.0617) = 2.615 Vdc
R output = 1.875 + 15 (0.0617) = 2.800 Vdc

2-145

Color Video Display Generator (CVDG)

R6549
110 DATA ACCESS CYCLE FUNCTIONS

When 10CS is LOW, the register address inputs (AO and A1)
and the mode selected in the CVDG Mode Register define the
specific CVDG 1/0 operation, i.e., ModelStatus Register Access,
CVDG Graphics Access (Mode 0), or one of the six CVDG
Parameter Access modes (Modes 1-6). Table 4 shows the
CVDG registers accessible during the 1/0 access cycle and the
bit assignments. When A1 and AO are both HIGH, the register
bits are defined with reference to a pseudo Data Register (DR).
The actual internal CVDG register accessed depends on the
selected mode (see Table 4). The bits are defined in the following
text.

The 1/0 access cycle operates in one of five ways:
1. CVDG ModelStatus Register Access (enabled by 10CS LOW)

2. CVDG Graphics Access (enabled by 10CS LOW)
3. CVDG Parameter 1/0 Access (enabled by 10CS LOW)
4. MPU DRAM 1/0 Access (enabled by ORCS LOW)
5. Teletext Byte DMA (enabled by TTXREQ LOW)

CVDG Mode/Status Register Access

The basic type of 1/0 access cycle is determined by the chip
select (lOCS or ORCS) and Teletext Request (TTXREQ) inputs.
When neither of the chip select inputs are LOW, nor has a TTX
DMA transfer been initiated by TTXREQ LOW, the 1/0 access
cycle is idle with no data transfer occurring during the processor
portion of the AID bus cycle.

Table 4.

When 10CS is LOW and the register address is zero (AO and
A 1 inputs are both LOW), the Mode Register (MR) or the Status
Register (SR) is accessed depending upon the RiW input level.
When RiW is LOW, the Mode Register is written; when RiW is
HIGH, the Status Register is read.

CVDG Register Summary

Register
Select
Lines
Internal CVDG Register

Register Bit No.

Mode

A1

AO

2

1

0

0

0

W

-

-

-

-

S

M2

M1

MO

OF

Status Register

-

0

0

R

VB

HB

M2

M1

MO

P

V1

VO

--

X COP Register

0

0

1

RIW

X7

X6

X5

X4

X3

X2

X1

XO

00

Y COP Register

0

1

0

R/W

Y7

Y6

Y5

Y4

Y3

Y2

Y1

YO

DRAM'

0

1

1

RIW

P3

P2

P1

PO

03

02

01

00

LUT Address Register

1

1

1

W

XPE

RE

GE

BE

A3

A2

A1

AO

00

LUT2

2

1

1

R

-

-

03

02

01

DO

---

Mode Register

R/W4

7

6

5

4

3

Reset3

00

,--

LUT Data Register

2

1

1

W

-

-

-

03

02

01

DO

Switch Register

3

1

1

W

NHS

S21

EXT

LS

TST

-

-

-

F8

Y Scroll Register

4

1

1

W

Y7

Y6

Y5

Y4

Y3

Y2

Y1

YO

00

TTX Pointer Register

5

1

0

RIW

A12

A11

A10

A9

A8

A7

A6

A5

00

DRAM Page Register

6

1

1

W

-

-

-

-

-

P

V1

VO

07

Notes:
1. The DRAM is directly accessed and not the CVDG.
2. Data is transferred from the LUT onto the AID bus without going through the LUT Data Register.
3. Reset state upon power up.
4. RIW = Read/write (R = read only; W = write only; RIW = read or write).

2-146

R6549

Color Video Display Generator (CVDG)

Mode Register
The write-only Mode Register selects the CVDG mode for next
read from, or write to, the CVDG. In addition, the Mode Register
contains a submode flag applicable only to Mode O. The Mode
Register may be written at any time regardless of the current
CVDG mode. The mode and submode bits are initialized to ones
upon power up.

SR7 Vertical Blanking (VB)

o

Vertical blanking is asserted.
Vertical blanking is not asserted.

SR6 Horizontal Blanking (HB)
Bit Position
Register
Mode

A1 AD RIW

0

0

W

o

716151413121110
-

1-

1-

1-

1

s

1M21 M1 1MO

SR5-SR3 Mode Selected (M2-MO)

MR7-MR4 Not used (no effect)

Reports the current CVDG mode as selected in bits 2-0
of the Mode Register.

MR3 CDP Submode Flag (S) - (Mode 0 only-see Mode 0
description)
o Enable CDP Nibble Submode. Allows readlwrite of a
single 4-bit pixel nibble in a byte.
Enable CDP Byte Submode. Allows readlwrite of two 4-bit
pixel nibbles in a byte with automatic increment of the
X CDP for faster storage of LUT addresses in DRAM.
MR2-MRO

0
0
0
0
1

SR5 SR4
(M2) (M1)
0
0
0
0

CVDG Mode (M2-MO)

Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Not used -

0
1
0
1
0
1
0

0
0
1
0
0

Port CDP Graphics
LUT Address
LUT Data
Switch Register
Y Scroll Offset Register
Teletext DMA Pointer
Set DRAM Page
no effect

Status Register

0

R

IHB IM21 M1 1MO 1 p

SR1
(V1)

o
o
o
o

o
o

Port CDP Graphics
LUT Address
LUT Data
Switch Register
Y Scroll Offset Register
Teletext DMA Pointer
DRAM Page
no effect

SRO
(VO) Selected DRAM Page

o
1

o
1

Mode 0 -

71 6 151413121110
VB

Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Not used -

o

Video Page 0: 8k-byte video RAM
Video Page 1: 8k-byte video RAM
Video Page 2: 8k-byte video RAM
Video Page 3: 2.3k-byte video RAM;
5.9k-byte program RAM
Program Page: 16k-byte optional program
RAM accessed via i5RCS (additionally paged
by A13 and NJ inputs)

Port COP Graphics

When IOCS is LOW and Mode 0 is selected in the Mode
Register, the Port Current Drawing Pointer (CDP) Mode is active.
In this mode display column and row addresses can be written
to the CVDG Current Drawing Pointer (CDP) X and Y registers,
respectively, and pixel data accessed in DRAM. This mode is
primarily used to update LUT addresses (Le., the CDPs) in the
video pages of DRAM. These LUT addresses are the video data
read from the DRAM by the CVDG during the video portion of
the AID bus cycle.

Bit Position

0

SR2
(P)

o

The horizontal blanking (HB) and vertical blanking (VB) signals
report the state of the video raster at the time of access. The
states of these two signals can be used for 15 kHz poll-driven
timing, vertical blanking interval (VBI) identification, LUT loading,
etc. These blanking times reflect the non-pixel display time
including the time actual horizontal and vertical blanking signals
are generated (for inclusion in composite sync output).

Status

1
0
0

0
1
0
1
0
1
0

Reports the current DRAM Page selected in bits 2-0 of
the Page Register (see Mode 6 - Write DRAM Page).
P is the program RAM page indicator. VO and Vl are the
video page indicators.

The read-only Status Register reports the selected CVDG mode,
the selected DRAM page and the status of the horizontal and
vertical raster blanking signals. The Status Register may be read
at anytime regardless of the CVDG mode.

A1 AD RlW

0
0

SR3
(MO)

SR2-SRO DRAM Page Selected (P, V1, VO)

Note that the mode must be written into the Mode Register before
the desired mode can be executed.

Register

Horizontal blanking is asserted.
Horizontal blanking is not asserted.

1 V1 1VO

2-147

PI

Color Video Display Generator (CVDG)

R6549
This mode can be used to write or read data in any of the four
Sk-byte video pages of DRAM defined by the VO and VI bits
in the CVDG DRAM Page Register. The first three pages (VOO,
VOl and Vl0) are used exclusively for video data. 2304 byles
(addresses O-SFF) of the fourth page (VII) are used for video
data while the rest of the DRAM can be used for program or
teletext message storage.

into the DRAM (row address strobed by RASL); if XO = 1, the
P nibble (data bits 7-4) is written into the DRAM (row address
strobed by RASH).
When reading the data, only one nibble is read depending on
the state of XO in the X CDP. If XO = 0, the
nibble is read
(row address strobed by RASL); if XO = 1, the P nibble is read
(row address strobed by RASH).

a

In mode 0, the MPU writes the address of the data in display
coordinates into the CVDG X CDP and Y CDP registers. The
X CDP contains the pixel position in the horizontal axis (i.e., the
display column number) and varies from 0 to 255 (hex FF). Each
pixel data nibble corresponds to a location (0 to 15) in the color
look-up table (LUT) from which the corresponding R, G and B
color levels and transparent bit data are retrieved for color
generation. The Y CDP contains the pixel position in the vertical
axis (i.e., the display row number) and varies from 0 to
255 (hex FF). Only values of 0 to 209 are used by the CVDG
during the video portion of the AID bus cycle to access video
data. Y addresses 210-255 identify DRAM address on video
DRAM page VII that can contain non-displayable data, i.e.,
program or teletext data.

Reading or writing the data in this submode has no effect on
the X CDP or Y CDP register values.

COP Byte Access Submode
The CDP Byte Submode (S = 1) reads or writes two 4-bit LUT
addresses at a time (in one byle) with an automatic increment
of the X CDP value in the X CDP Register during write. Each
write of the DRAM data writes the eight data bits on ADO-AD7
into DRAM and increments the X CDP by two upon the completion of the write cycle. (The new X CDP count can be read from
the X CDP Register at any time.) As writing of the data continues,
the X CDP value eventually wraps around to zero and continues
incrementing. The Y CDP Register value must be incremented
by writing a new Y CDP value. The automatic increment of
X CDP value allows fast horizontal drawing for filling of polygon
and rectangle type shapes (i.e., no intervening X CDP update
is required). Note that the filled boundaries must be addressed
by the horizontal line software since the XO value has no effect
in this submode.

The registers accessible (besides in Mode and Status registers)
in this mode are:
Bit Position
Register

AI AO R/W

4

1

0

0

1 RIW X7

X6 X5 X4 X3 X2 XI

XO

Y CDP

1

0 RIW Y7

Y6 Y5 Y4 Y3 Y2 Yl

YO

DRAM'

1

1 RIW P3

P2

00

X CDP

7

6

5

PI

PO

3

2

03 02 01

This feature is useful for fast non-modulo 210 Y scrolling with
quick reads/writes interleaved by old/new Y address updates.
Note that when S = 1 in the Mode Register, the XO value has
no effect (the P nibble corresponds to XO = 1 and the nibble
corresponds to XO = 0).

'Not CVDG Access

a

The X CDP Register is accessed at register address 1 (AI = 0
and AO = 1) and the Y CDP Register is accessed at register
address 2 (AI = 1 and AO = 0). When register address 3 (AI = 1
and AO = 1) is detected, the CVDG generates DRAM row and
column addresses corresponding to the display coordinates
loaded in the X CDP and Y CDP registers. Data is then written
from the AID bus to the DRAM (RiW = low) or read from the
DRAM to the A/D bus (RiW = high).

Reading of the DRAM data in this submode does not effect the
X CDP count.

cvoa

There are two submodes in Mode 0 that allow accessing of
DRAM data at either the nibble (4-bit) or byte (S-bit) level. The
submode is selected by the S bit (bit '3) in the Mode Register:

S
0
S = 1

PARAMETER I/O ACCESS

Six CVDG Parameter Access modes allow the MPU to load control parameters into CVDG internal registers. Two of the modes
also allow the MPU to read the parameter values from registers.
The exact mode and access is controlled by the selected mode
in the Mode Register and the register select input lines (AI
and AO).

CDP Nibble Submode
CDP Byte Submode

Mode 1 -

LUT Address

In Mode 1, data written to register address 3 (AI = 1 and
AO = 1) is loaded into the LUT Address Register. Four bits
control LUT write and read and the other four bits contain the
actual 'LUT address. Bits 7-4 (XPE, RE, GE and BE) enable
writing into, or reading from, corresponding sections of the LUT
(i.e., XPAR, R, G and 8) during Mode 2 access. Bits 3-0 in the
register contain the LUT address (0-15) accessed during
Mode 2.

COP Nibble Submode
The CDP Nibble Submode (S = 0) reads or writes DRAM data
one nibble at a time. Eight bits of data corresponding to two 4-bit
LUT addresses (P3-PO and 03-00) are on the AID data bus,
but only one nibble is read or written during each access.

a

nibble should contain the same
When writing the data, the
pixel data as the P nibble. Only one of the nibble values is
strobed into DRAM according to the XO value in the X CDP
Register which enables the RASL or RASH Signal to DRAM
during the write. If XO = 0, the nibble (data bits 3-0) is written

Bit Position
Register

a

LUT Address

2-14S

AI AO R/W
1

1

W

716151413121110

I I I I I

XPE RE GE BE A3 A21 AI

I AD

R6549

Color Video Display Generator (CVDG)

OR7

Transparent Enable (XPE)

0

Disable XPAR write or read
Enable XPAR write or read

DRS
0

DRS
0

During a read, data is transferred from the LUT directly to the
AID bus without going through the LUT Data Register. XPAR is
not availabe for readback.
Bit Position

Red Enable (RE)

Register

Disable R write or read
Enable R write or read

LUT Data'

A1 AO RlW 716151413121110
1 1 RfW - 1- 1- 1 - 1 D3iD21 01 J DO

'Durlng a read, data IS transferred directly from LUT to AID bus
without gOing through LUT Data Register.

Green Enable (GE)

OR7-0R4 Not used (no effect)

Disable G write or read
Enable G write or read

OR3-0RO Color Level Code or Transparent Bit State
OR4
0

Blue Enable (BE)
Disable B write or read
Enable B write or read

03

02

01

DO

0
0

0
0

0
0

0

R, G or B Color Output Level
Color output level 0
Color output level 1

OR3-0RO LUT Address (A3-AO)
Color output level 15
OR3 OR2 OR1
(A3) (A2) (A1)

o
o

o
o

o
o

ORO
(AO)

o

LUT address 0
LUT address 1
LUT address 15

01

DO

XPAR Output Level

X
X

X
X

X
X

XPAR output LOW
XPAR output HIGH
(X = no effect)

Switch Register

In Mode 3, switch position data (represented by bit states) written
to register address 3 (A 1 = 1, AO = 1) is loaded into the CVDG
Switch Register. Three bits control video raster operation, one
bit controls the LUT address access source, and one bit enables
the CVDG test mode. All five bits are set to a 1 by power up.

1. Outside the 256 x 210 graphics area, i.e., to generate ihe
border color. Note that programs loading the LUT during the
vertical blanking interval (VBI) must restore the address of the
border color in the LUT into the LUT Address Register prior
to unblanking.

Mode 2 -

02

0

Mode 3 -

The LUT address in the LUT Address Register, rather than the
LUT addresses read from DRAM, is also used to lookup the color
level code in the LUT dUring the active display time (border and/or
pixel) in two circumstances:

2. Within the 256 x 210 graphics area when the LS bit
the Switch Register.

03

Bit Position
Register
Switch

= 0 in

OR7

o
1

LUT Data

In Mode 2, LUT data (i.e., color levels and transparent state)
written to, or read from, register address 3 (A1 = 1, AO = 1)
is loaded into, or read from the LUT at the LUT address contained in the LUT Address Register. Only the section (R, G, B
and/or XPAR codes) of the LUT entry enabled by bits 7-4 in the
LUT Address Register are accessed. Normally only one enable
bit at a time is set to a 1. During a write, data will be written
into each LUT section enabled. During a read, ambiguous data
will be accessed if more than one enable bit is set.

DRS

The transparent state (XPAR) is only one bit (D3). The other three
data bits (D2-DO) are don't care.

OR4

o
DRS

o

o

During a write, the data on the AID bus is written into the CVDG
LUT Data Register. The LUT Address Generator latches the 4-bit
LUT address from the LUT Data Register rather than from the
Video Shift Register. The LUT Address Generator then
generates the 16-bit binary address for routing to the LUT. The
LUT is loaded in a similar manner as described for pixel color
generation.

OR3

o

2-149

A1 AO
1

1

R/W

716151413[21110

W NHslS21jEX~ LSJTS~ - 1 - J -

Normal Horizontal Sync (NHS) Select
Early 15.9 kHz (HSYNC) Output
Normal 15.7 kHz HSYNC Output
2:1 Interlace Select (S21)
1: 1 interlace
2:1 interlace
External Sync Select (EXT)
Internal sync output on VSYNC (C/HSYNC output
enabled.
External sync input on VSYNC (C/HSYNC output
disabled)
LUT Address Select (LS)
Select the LUT Address Register as the LUT address
source
Select Video Shift Register data as LUT address source
Test Mode Select (TST)
Normal mode; Vertical state machine (VSM) and Y
address counter (YAC) run at normal rate
Test mode; VSM and YAC run at 1.413 MHz (used for
factory test only)

fI

Color Video Display Generator (CVDG)

R6549

DR7-DR3 Not Used (no effect)

Mode 4- Y Scroll Register
In Mode 4, Ii Y scroll offset value written to register,address 3
(A 1 = 1, AO = 1) is loaded into the Y Scroll Register. The Y scroll
offset may vary from 0 to 209 (decimal). The value written defines
the first horizontal row to be displayed at the top of the
2S6 x 210 graphics image area.

Register
Y Scroll

Bit Position
A1 AO RIW 716151413121110
1 1 W Y7 I Y6 I YSI Y41 Y31 Y21 Yl I YO

DR7-DRO

Y Sero" Offset

0000000
0000001

Offset = 0
Offset = 1

11010001

Offset = 209 (maximum allowed)

DR2-DRO

Selected DRAM Page

DR2 DR1

ORO

(P)

(V1)

(VO)

o
o
o
o

o
o

o
1

o
1

o

o

Video Page 0: 8k-byte video RAM
Video Page 1: 8k-byte video RAM
Video Page 2: 8k-byte video RAM
Video Page 3: 2.3k-byte video RAM;
5.9k-byte program RAM
Program Page 0: 16k-byte optional program
RAM accessed via ORCS (additionally paged
by A13 and AO inputs)

MPU DRAM 1/0 ACCESS
When ORCS is LOW, the MPU directly accesses the DRAM in
an address map manner. The MPU generates the DRAM row
and column addresses (except for two column address lines
which are driven by the CVDG). The CVDG drives the ADS and
AD6 lines during DRAM column address time and also outputs
control signals (RTIME,CTIME and DTIME) to enable external
AID bus buffers. MPU address line A1-A8 are enabled onto AID
bus lines ADO-AD7, respectively, by RTIME to drive the DRAM
row address. MPU address line A9-A12 are enabled onto AID
bus lines AD1-AD4, respectively, by CTIME to drive the DRAM
column address. The CVDG drives ADS and AD6 with one of
two sets of signals during CTIME. External bidirectional data line
buffers are enabled by DTIME in the direction controlled by the
MPU RIW output to transfer data between the MPU data bus
lines 00-07 and AID bus lines ADO-AD7.

Mode 5 - Teletext DMA Pointer
In Mode 5, an 8-bit Teletext pointer written to register address 2
(A 1 = 1, AO = 0) is loaded into the nx Pointer Register and
Counter. The pointer, consisting of address bits A12-AS
specifies the starting address on a 32-byte boundary for the DMA
transfer of teletext data into video page 3 of DRAM. During a
teletext DMA data transfer, the'Modulo 32 Teletext Counter is
incremented by one upon each DMA byte transfer. The nx
Pointer Register is incremented by one every 32 bytes. The value
of the Teletext Pointer can be read at any time in Mode S.

A13 input high causes program DRAM to be accessed during
the processor portion of the AID bus independent of the P bit
value in the DRAM Page Register. CASP is asserted in response
to the A13 HIGH to strobe the column address lines into program DRAM.

Bit Position
Register
AI AO RIW 716151 4 131 2 1 1 10
Teletext Pointer 1 o RIW A121A111AlOi A91 AsIA71 A61 AS

When A13 input is LOW, the section of DRAM accessed depends
on the P bit value in the DRAM Page Register and the AO input.
If P = 0, video DRAM is accessed; CAS1 is generated when
AO is LOW and CAS2 is generated when AO is HIGH. If P = 1,
program DRAM is accessed since CASP is generated instead
of CAS1 or CAS2 to strobe the DRAM column address.

The status of the P, V1 and VO in the Mode/Status Register are
unchanged during a Teletext DMA data transfer.

Mode 6 - Set DRAM Page
The ADS and AD6 outputs are driven by the CVDG during DRAM
column address generation in the processor portion of the AID
bus cycle as controlled by the P bit in the DRAM Page Register.
If video DRAM is selected (P = 0), the VO and V1 bits in the
DRAM Page Register are output on ADS and AD6, respectively.
If program DRAM is selected (P = 1), the AO and A13 inputs
are output on ADS and AD6, respectively.

In Mode 6, data written to register address 3 (A1 = 1, AO = 1)
is loaded into the DRAM Page Register. The data contains a
3-bit DRAM page select code and five unused bits (don't care).
These DRAM page select bits specify the 8k-byte DRAM page
accessed during a MPU DRAM access (ORCS = low) when A13
input is LOW. The DRAM page bits can be read from the Status
Register at any time.

Note that the DRAM requires assertion of all three control signals
for a valid access (i.e., RAS, CAS and OE for a read and RAS,
CAS and ViI for a write). The CVDG sometimes outputs one or
two of these signals but not all three control signals in "no
access" situations.

Bit Position
Register AI AO RIW 716151413121110
DRAM Page 1 1 W - I - I - I - I - I P I V1 I VO

2-1S0

R6549

Color Video Display Generator (CVDG)

TELETEXT DMA 1/0 ACCESS

the upper count is incremented by one to increment the total
address. The address is reset to zero during horizontal blanking. The upper count may be read from the TTX Pointer Register
at any time in Mode 5.

Teletext data can be DMA transferred from a teletext prefix
processor connected to the AID bus to DRAM locations
addressed by the CVDG. A 13-bit TTX Latch/Counter determines
the DRAM address. The upper a-bits of the TTX Counter is a
latch. The value of the latch is defined by the TTX Pointer
Register which can be loaded in Mode 5 by writing to register
address 2 (A 1 = 1 and AO =0). The TTX Pointer Register value
therefore defines the TTX DMA starting address on a 32-byte
boundary. The lower 5-bits of the TTX Latch/Counter is a
modulo 32 counter. This counter increments by one after each
TTX byte transfer. When the counter overflows (i.e., from 31 to 0)

TTX DMA transfer is initiated by asserting TTXREQ to the
CVDG. The CVDG asserts TTX Output Enable (TTXOE) to
acknowledge TTXREQ receipt, suspends outputting the E and
Q clocks for one cycle, outputs the 13-bit DRAM address and
asserts DRAM Write Enable (IN) to enable writing into DRAM.
Note that DMA must be used only when the horizontal sync is
genlocked to the external teletext raster.

2-151

n
II11II

Color Video Display Generator (CVDG)

R6549

....- - - - - - - - - - - M P U ADDRESS BUS I N P U T - - - - - - - - - . . . .

_

MPU DATA BUS 1 / 0 _

RTIME

CfiME

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ADS
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AD3
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R8S49
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CASP .....(PGM)

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NOTES: 1. CASP allows mamory management of meny program RAM peges In 18K-byte blocks
(TMS4418-t20 RAM devices may be raqulrad for extended AID bus).
2. Page bits may come from sddre.. decoder or static outputs of a parellel port.

Figure 6. CVDG Connection to AID Bus and DRAM

2-152

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Color Video Display Generator (CVDG)

R6549
AC CHARACTERISTICS
(Vee = 5.0V ±5%. vss = 0)

MPU CLOCK AND CONTROL LINE TIMING
Ref. Fig. 8
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Symbol
t ECYC

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tSlEH
tSHEH
tEHQV
tElQZ
tovEl
tElOZ

Parameter

E
E
E
E
E

Cycle Time
and Q Rise and Fall
Low to E High
High to E Low
Low to Q Rising
Q High to E Rising
E High to Q Failing
Q Low to E Falling
Chip Select Low to E Rising (Setup)
Chip Select High to E Rising (Hold)
E High to Data Valid (Read)
E Low to Output High Z (Read)
Data Valid to E Failing (Write)
E Falling to Data Invalid (Write)

Note:
1. Based on 28.636363 MHz SYSCLK input.

2-155

Min.

Typ.

700

698
25
350
350
175
175
175
175
70
0

Max.

240
10
100
30

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

1

Color Video Display Generator (CVDG)

R6549

E

Q

RtW
ADO-AD7 - (READ) (IDeS

=L,R/W = H)

ADO-AD7 - (WRITE) (IDeS = L,R/W = L)
eVDGDATA
VALID-WRITE

Figure 8.

CVDG-MPU AID Bus Timing Waveforms

2-156

Color Video Display Generator (CVDG)

R6549
DRAM TIMING Ref. Fig. 9
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

DRAM TIMING Ref. Fig. 9
No.
30
31
33
36
37
38
39
40
41
42
43
44

VIDEO ACCESS CYCLE
Symbol
tALATL
tATLATH
tALCTL
tCTLCTH
tALOTL
tDTLDTH

t AC
tAP
t AAS
t RCD

t CAS
tCSH
tASH
t CPN
t CAP
t,
tACS

t ASA
tAAH
t ASC
tCAH
tAA
t AAC
t CAC
tRLG1L
tGLGHr

tOEA
tOEZ
tALG2L

Parameter

Min.

RAS Low to RTIME Low (Delay)
RTIME Low to RTIME High
RAS Low to CTIME Low (Delay)
CTIME Low to CTIME High
RAS Low to DTIME Low (Delay)
DTIME Low to DTIME High
RAM ReadlWrite Cycle
RAS High Width
RAS Low Width
RAS Low to CAS Low (Delay)
CAS Low Width
RAS Low to CAS RIsing (Delay)
CAS Low to RAS RIsing (Delay)
CAS High Width
CAS High to RAS Failing (Delay)
RAS and CAS Transition Times
Read Command Setup
Row Address Setup
Row Address Hold
Column Address Setup
Column Address Hold
RAS Low to Column Hold
RAS Low to Data Valid (Setup)
CAS Low to Data Valid (Setup)
RAS Low to OE1 Low (Delay)
OE Low to OE High
OE Low to Data Valid (Setup)
OE High to Output High Z (Hold)
RAS Low to OE2 Low (Delay)

Typ.

Max.

315
70
35
87
122
157
350
105
245
70
245
315
175
105
35
5
105
35
35
35
70
140
150
80
140
70
0
0

40
35
210

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

fJ

MPU DRAM ACCESS CYCLE
Symbol
tAAH
tACH
tGLGH
t DS
twp
tDH
t DHC
tDHA
t WCA
tWCH
t AWL
tCWL

Parameter

Min.

Read Command Hold After RAS High
Read Command Hold After CAS High
OE1, OE2 Low to OE1, OE2 High
Data Setup
W Low to W High
Data Hold After W Low
Data Hold After CAS Low
Data Hold After RAS Low
Write Command Hold After RAS Low
Write Command Hold After CASP Low
Write Command Setup before RAS RIsing
Write Command Setup before CAS RIsing

2-157

Typ.
280
210
140
12
140
70
175
245
315
245
70
140

Max.

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Notes

Color Video Display Generator (CVDG)

R6549

E

~~

________________~

W
(MPU READ)

ADO-AD7
(MPU READ)

W
(MPUWRITE)

ADO-AD7
(MPUWRITE)

Figure 9.

CVDG-DRAM AID Bus Timing Waveforms

2-158

\~-----

R6549

Color Video Display Generator (CVDG)

TELETEXT DMA CYCLE TIMING
Ref. Fig. 10
No.
1
2
3
4

Symbol

Parameter

Min.

TTXREO Low 10 E Low (Selup)
E Low to TTXREO High (Hold)
E Low 10 TTXOE Low
TTXOE Low 10 TTXOE High

IRLEL
tELRH
IELGL
IGLGH

NORMAL CYCLE

Typ.

Max.

Unit

TTX DMA CYCLE

Notes

ns
ns
ns
ns

80
10
595
140

NORMAL CYCLE

E

_________. __0__
~01--~

TTXOE

Figure 10.

Teletext Prefix Processor -

CVDG Timing Waveforms

HORIZONTAL VIDEO TIMING
Ref. Fig. 11
No.
1
2
3
4
5
6
7
8
9
10
11

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

H Sync to Setup
H Front Porch
H Sync 10 XPAR
XPAR Front Porch
H Sync 10 Border 1
H Sync to Graphics
H Sync 10 Border 2
Border Front Porch
H Sync Tip
;-; Period (Nol'ma:)
H Period (Early)

9.3
1.4

9.4
1.5
10.16
2.79
8.38
1257
57.27
2.79
4.81
83556
62.857

9.5
1.6

I'S

-

1"5

1
1
2
2
2
2
2
2
2
2
2

-

-

-

Notes: 1. RS-170A Specifi9atlon (shown for reference only).
2 ± O.II'S, based on 28.636363 MHz SYSCLK Inpul.

2-159

-

-

I'S
I's
I'S

I'S
I's
I's
I'S
!'s
I's

Color Video Display Generator (CVDG)

R6549

~

EXTERNAL ACTIVE VIDEO
REF

EXTERNAL
VIDEO
REFERENCE

XPAR
OUTPUT

RGBVIDEO
OUTPUT

®

@-4-~

G)-+-1-~--~~
..........., ...._ _ _-.-_ _ _.J• ...........,

C/HSYNC OUTPUTS:

_ V YL

- VYB

BORDER COLOR TIME

CSYNC
OUTPUT

@
HSYNC
NORMAL
OUTPUT

-

HSYNC
EARLY
OUTPUT

VOH
VOL

- VOH
- VOL

®

Figure 11.

Horizontal Video Output Timing Waveforms

2·160

Color Video Oisplay Generator (CVOG)

R6549
Vertical Cycle Timing
Ref. Fig. 12
No.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

1
2

Vsu
VH

VSYNC Low Input to First Serration Setup
VSYNC Low Input Pulse Duration
VSYNC Low Output Pulse Duration (Burst Blank)
V Blank Duration
V Unblank to Graphics Duration (Top Border)
Graphics to V Blank Duration (Bottom Border)

20
63.5
19
52
21
31

-

-

ns

3
3
1
1
1
1,2

-

,..s
H
H
H
H

-

-

Notes: 1. H = HSYNC pulse width (63.5 I's)
2. 2 1 Interlace mode
3. Shown for reference only-not an R6549 reqUirement

EXTERNAL
SYNC
REFERENCE
(FROM
EXTERNAL
CIRCUIT)

VSYNCINPUT

fJ

~

-----,

i--r"T1I1'-'-111r-r-r11""-1
. . - .- - - -

a.

Vertical Synchronization

BLACK NEGATIVE
DIRECTION TlME-+

+
CSYNC
OUTPUT

I-H-\-3H

1nrlnnJ

3H--t--3H-+H1
:
EQUALIZING PULSE VERT SYNC
EQUALIZiNG I--- 9 TO 12 H PULSES - I
INTERVAL
PULSE
PULSE
I INTERVAL
INTERVAL
I
:I
I- O.SH
I,JTl + V
LH-j
I

~I~I~I-'r~r~r~#

nr'r'r'r'r'rr--~

I

~

,
I

b.

R8-170A Composite Sync VBI Timing Specifications

Figure 12. Vertical Cycle Waveforms-2:1 Interlace

2-161

R6549

Color Video Display Generator (CVDG)

TELETEXT DMA CYCLE TIMING
Ref. Fig. 13
No.

Symbol

Parameter

1
2
3

I ELPL

E Low 10 PIXCK High
PIXCK High 10 PIXCK Low
PIXCK Low 10 PIXCK High
PIXCK Cycle

4

IpHPL
IpLPH
IpCYC

Min.

Typ.

Max.

,
Figure 13. Video Output Waveforms

2-162

Unit

ns
ns
ns
ns

0
70
105
175

Notes

R6549

Color Video Oisplay Generator (CVOG)

DC CHARACTERISTICS
± 5%, Vss = OV, TA

(Vee = 5.0V

=

ooe to 70°C,

Parameter

unless otherwise noted)

Symbol

Min.

Typ.

Max.

Input High Voltage
SYSCLK
IOCS, DRCS, TTXREO, AO, AI, A13, RiW,
VSYNC, ADO-AD?

VI He
VIH

vee - 0.?5
Vss + 2.0

-

Vee

Input Low Voltage
SYSCLK
IOCS, DRCS, TTXREO, AO, Al,A13, RiW
VSYNC, ADO-AD?

Vile
Vil

Vss - 0.3

-

Vss + 0.4

Input Leakage Current

III

Output High Voltage
E

Unit

Teat Conditions

V
Vee
V
Vss - 0.3

-

Vss + 0.8

tl0

p.A

-

VOH

V

= OV to 5.25V
=0
Vee = 4.?5V
10H = -0.14 rnA

VIN
Vee

Vee - 0.?5

-

-

Vss + 2.4

-

-

10H = -80 p.A
Note 2

Vss + 2.4

-

-

10H = -1?0 p.A
Note 3

-

-

Vss + 0.4

= 4.?5V
IOl = I.? rnA
Note 1

-

-

Vss + 0.4

10l = 1.6 rnA
Note 2

-

-

Vss + 0.4

IOl = 3.0 rnA
Note 3

IOFF

-

-

t20

p.A

VIN

= 0 to 5.25V

Output High Voltage
R,G, B

VVH

-

+2.800

-

V

Cl
Rl
t,lt f

= 30 pF
= 10K Ohms
= 50 ns

Output tow Voltage

VVl

-

+ 1.8?5

-

V

Output Blanking Voltage
R,G, B

VVB

-

+ 1.800

-

V

Input Capacitance4
SYSCLK
IOCS, DRCS, TTXREO, AO, AI, A13, RiW,
VSYNC, ADO-AD?

CIN

Note 1

0, RTIME, CTIME, DTIME,
RASL, RASH, W
CAS1, CAS2, CASP, OE1, OE2, TTXOE,
C/HSYNC, VSYNC, CSUBC, PIXCK, XPAR
ADO-AD?
Output Low Voltage
E

V

VOL

0, RTIME, CTIME, DTIME,
RASL, RASH, W,
CAS1, CAS2, CASP, OE1, OE2, TTXOE,
C/HSYNC, VSYNC, CSUBC, PIXCK, XPAR
ADO-AD?
Output Leakage Current
(OII·State)

Vee

ADO-AD?

R,G, B

pF

-

Notes:
1. Output Load: 1 TTL gate; Cl = 140 pF
2 Output Load: 1 TTL gate; Cc = 100 pF
3. Output Load: 6 DRAM, 2 LS244 buffers and 1 LS245 transceiver; Cl
4. This parameter is periodically sampled and is not 1000/0 tested.

-

= 180 pF

2·163

10
5

Vee = 5.0V, chip
deselected, pi n

Under test at OV,
TA = 25°C,
I = 0.986 MHz
(SYSCLK
= 28.6363 MHz)

fJ

Color Video Display Generator (CVDG)

R6549
ABSOLUTE MAXIMUM RATINGS*
Symbol

Value

Unit

Supply Voltage

Vee

-0.3 to +7.0

V

Parameter

Input Voltages

V IN

-0.3 to +7.0

V

Operating Temperature

TA

o to + 70

°e

Storage Temperature

TSTG

-55 to +150

°e

'NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

PACKAGE DIMENSIONS
40-PIN PLASTIC DIP
DIM

A
B
e
D

F
G

H
J
K
L
M

N

2-164

MILLIMETERS
MIN·
MAX

51.28 52.32
13.72 14.22
3.55
5.08
0.36
051
1.02
152
2.54 BSe
1.65 I 216
0.20 I 0.30
305
3.56
1524 BSe
7° I 10°
0.51 I 1.02

INCHES
MIN
MAX

2.040
0.540
0.140
0.014
0040
0.100
0.065
0.008
0.120
0.600
7°
0.020

2060
0560
0200
0.020
0.060
BSe
0.085
0.012
0.140
BSe
10°
0040

R6551

'1'

Rockwell

R6551
ASYNCHRONOUS COMMUNICATIONS
INTERFACE ADAPTER (ACIA)

DESCRIPTION

FEATURES

The Rockwell R6551 Asynchronous Communications Interface
Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor-based systems
and serial communication data sets and modems.

•
•
•
•

Compatible with 8-bit microprocessors
Full duplex operation with buffered receiver and transmitter
Data set/modem control functions
Internal baud rate generator with 15 programmable baud
rates (50 to 19,200)
• Program-selectable internally or externally controlled receiver
rate
• Programmable word lengths, number of stop bits, and parity
bit generation and detection
• Programmable interrupt control

The ACIA has an Internal baud rate generator. This feature eliminates the need for mU~lple component support circuits, a crystal
being the only other part required. The Transmitter baud rate
can be selected under program control to be either. 1 of 15 different rates from 50 to 19,200 baud, or at '/'6 times an external
clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate, or at '/'6 times
the external clock rate. The ACIA has programmable word
lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1V2, or
2 stop bits.

• Program reset
• Program-selectable senal echo mode
•
•
•
•
•
•

The ACIA is designed for maximum programmed control from
the microprocessor (MPU), to simplify hardware implementation. Three separate registers permit the MPU to easily select
the R6551's operating modes and data checking parameters
and determine operational status.

Two chip selects
2 or 1 MHz operation
5.0 Vdc ± 5% supply reqUirements
28-pin plastic or ceramic DIP
Full TTL compatibility
Compatible with R6500, R6500/* and R65COO microprocessors

The Command Register controls parity, receiver echo mode,
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line.
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.

VSS
CSO

The Status Register indicates the states of the IRQ, DSR, and
DCD lines, Transmitter and Receiver Data Registers, and
Overrun, Framing, and Parity Error conditions.

ffi
RES
RxC

The Transmitter and Receiver Data Registers are used for temporary data storage by the ACIA Transmit and Receiver circuits.

XTLI
XTLO

RTS
CTS
TxO
OTR
RxO
RSO
RS1

ORDERING INFORMATION
Part No.: R6551 __
[

Temperature Range (T l to T H):
Blank = O"C to + 70°C
E = -40°C to +85°C
Package:
C = Ceramic
P = Plastic

'--Frequency Range:
No Letter = 1 MHz
A = 2 MHz

Figure 1.

Document No. 29651N90
2-165

1
2
3
4
5

6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

16
15

RiW
82
iRa
07
D6

05
04
03
02
01
00
OSR
OCO
VCC

R6551 ACIA Pin Configuration

Product Description Order No. 284
Rev. 3, October 1984

Asynchronous Communications Interface Adapter (ACIA)

R6551

T,O

0<>0'

oeD

iFiQ

OSR
RM

R.o

es.

XTLI

CSi

XTLO

RSO

DfII

RSl

"TS

;.
R,O
RES

Figure 2.

ACIA Internal Organization

FUNCTIONAL DESCRIPTION

TIMING AND CONTROL

A block diagram of the ACIA is presented in Figure 2 followed
by a description of each functional element of the device.

The Timing and Control logic controls the timing of data transfers on the internal data bus and the registers, the Data Bus
Buffer, and the microprocessor data bus, and the hardware
reset featu res.

DATA BUS BUFFERS

Timing is controlled by the system ~2 clock input. The chip will
perform data transfers to or from the microcomputer data bus
during the ~2 high period when selected.

The Data Bus Buffer interfaces the system data lines to the internal data bus. The Data Bus Buffer is bi-directional. When the
Rm line is low and the chip is selected, the Data Bus Buffer
writes the data from the system data lines to the ACIA internal
data bus. When the Rm line is high and the chip is selected,
the Data Bus Buffer drives the data from the internal data bus
to the system data bus.

All registers will be initialized by the Timing and Control Logic
when the Reset (RES) line goes low. See the individual reg islet
description for the state of the registers following a hardware
reset.

INTERRUPT LOGIC
The Interrupt LogIC will cause the IRQ line to the microprocessor
to go low when conditions are met that require the attention of
the microprocessor. The conditions which can cause an interrupt will set bit 7 and the appropriate bit of bits 3 through 6 in
the Status Register, if enabled. Bits 5 and 6 correspond to the
Data Carrier Detect (DCD) logic and the Data Set Ready (DSR)
logic. Bits 3 and 4 correspond to the Receiver Data Register full
and the Transmitter Data Register empty conditions. These conditions can cause an interrupt request if enabled by the Command Register.

TRANSMITTER AND RECEIVER DATA REGISTERS
These registers are used as temporary data storage for the
ACIA Transmit and Receive Circuits. Both the Transmitter and
Receiver are selected by a Register Select 0 (RSO) and Register
Select 1 (RS1) low condition. The Read/Write (RlW) line determines which actually uses the internal data bus; the Transmitter
Data Register is write only and the Receiver Data Register is
read only.
Bit 0 is the first bit to be transmitted from the Transmitter Data
Register (least significant bit first). The higher order bits follow
in order. Unused bits in this register are "don't care".

1/0 CONTROL

va

The
Control Logic controls the selection of internal registers
in preparation for a data transfer on the internal data bus and
the direction of the transfer to or from the register.

The Receiver Data Register holds the first received data bit in
bit 0 (least significant bit first). Unused high-order bits are "0".
Parity bits are not contained in the Receiver Data Register. They
are stripped off after being used for parity checking.

The registers are selected by the Receiver Select (RS1, RSO)
and Read/Write (R/W) lines as described later in Table 1.

2-166

R6551

Asynchronous Communications Interface Adapter (ACIA)

STATUS REGISTER

Parity Error (Bit 0), Framing Error (Bit 1), and
Overrun (2)

The Status Register indicates the state of interrupt conditions
and other non-interrupt status lines. The interrupt conditions are
the Data Set Ready, Data Carrier Detect, Transmitter Data Register Empty and Receiver Data Register Full as reported in bits
6 through 3, respectively. If any of these bits are set, the Interrupt (IRQ) indicator (bit 7) is also set. Overrun, Framing Error,
and Purity Error are also reported (bits 2 through 0 respectively).
7

6

5

4

3

2

None of these bits causes a processor interrupt to occur, but
they are normally checked at the time the Receiver Data Register is read so that the validity of the data can be verified. These
bits are self clearing (i.e., they are automatically cleared after
a read of the Receiver Data Register).

o
Receiver Data Register Full (Bit 3)
PE

Bit 7
0
Bit 6
0

This bit goes to a 1 when the ACIA transfers data from the
Receiver Shift Register to the Receiver Data Register, and goes
to a 0 (IS cleared) when the processor reads the Receiver Data
Register.

Interrupt (IRQ)
No interrupt
Interrupt has occurred

Data Set Ready (DSR)
Transmitter Data Register Empty (Bit 4)

DSR low (ready)
DSli high (not ready)

This bit goes to a 1 when the ACIA transfers data from the
Transmitter Data Register to the Transmitter Shift Register, and
goes to a 0 (is cleared) when the processor writes new data
onto the Transmitter Data Register.

Bit 5
0

Data Carrier Detect (DCD)

Bit 4
0
1

Transmitter Data Register Empty
Not empty
Empty

Data Carrier Detect (Bit 5) and Data Set Ready
(Bit 6)

Bit 3
0
1

Receiver Data Register Full

Bit 2
0

Overrun'

These bits reflect the levels of the DCD and DSR inputs to the
ACIA. A 0 indicates a low level (true condition) and a 1 indicates
a high level (false). Whenever either of these inputs change
state, an immediate processor interrupt (IRQ) occurs, unless bit
1 of the Command Register (IRD) is set to a 1 to disable IRQ.
When the interrupt occurs, the status bits indicate the levels of
the inputs immediately after the change of state occurred. Subsequent level changes will not affect the status bits until the
Status Register is interrogated by the processor. At that time,
another interrupt will immediately occur and the status bits
reflect the new input levels. These bits are not automatically
cleared (or reset) by an internal operation.

DCD low (detected)
5CJ) high (not detected)

Not full
Full

No overrun
Overrun has occurred

Bit 1
0
1

Framing Error'

Bit 0
0
1

Parity Error'

No framing error
Framing error detected

No parity error
Parity error detected

Interrupt (Bit 7)
• No interrupt occurs for these conditions

This bit goes to a 1 whenever an interrupt condition occurs and
goes to a 0 (is cleared) when the Status Register is read.

Reset Initialization
76543210

I~I=I=I~I~I ~ I~I~I

Hardware reset
Program reset

2-167

Asynchronous Communications Interface Adapter (ACIA)

R6551
CONTROL REGISTER

Selected Baud Rate (Bits 0, 1, 2, 3)

The Control Register selects the desired baud rate, frequency
source, word length, and the number of stop bits.

These bits select the Transmitter baud rate, which can be at
'/'6 an external clock rate or one of 15 other rates controlled by
the internal baud rate generator
If the Receiver clock uses the same baud rate as the transmitter.
then RxC becomes an output and can be used to slave other
CIrcuits to the ACIA. Figure 3 shows the Transmitter and Receiver
layout.

Bit 7

Stop Bit Number (SBN)
1 Stop bit
2 Stop bits
1Y2 Stop bits
For WL = 5 and no panty
1 Stop bit
For WL = 8 and panty

a

Bits 6-5
~~

a
a

a
1

a

Word Length (WL)
No. Bits
8
7

..,.f----------- RxC

5

Bit 4

Receiver Clock Source (RCS)
External receiver clock
Baud rate

a
1

Bits 3-0

a
a
a
a
a
a
a
a

Rxo

6

1

.l..

i4-.....-

XTLI
XTLO

Selected Baud Rate (SBR)
.Q.. Baud
a a 16x External Clock
a 1 50
1
a 75
1
109.92
a a 134.58
a 1 150
1
a 300
600
a a 1200
a 1 1800
1
a 2400
1
1
3600
a a 4800
a 1 7200
1
a 9600
1
1
19,200

1- ...!...

a
a
a
a

a
a
a
a
1

Figure 3.

Transmitter/Receiver Clock Circuits

Receiver Clock Source (Bit 4)

a

This bit controls the clock source to the Receiver. A causes
the Receiver to operate at a baud rate of '/'6 an external clock.
A 1 causes the Receiver to operate at the same baud rate as
IS selected for the transmitter

Word Length (Bits 5, 6)

Reset Initialization

These bits determine the word length to be used (5, 6, 7 or 8
bits).

7 6 5 432 1 0

I~I~I~I~I~I~I~I~I Program reset

Hardware reset (RES)

Stop Bit Number (Bit 7)

a

This bit determines the number of stop bits used. A always
indicates one stop bit. A 1 Indicates 1V2 stop bits If the word
length is 5 with no panty selected, 1 stop bit If the word length
is 8 with parity selected, or 2 stop bits in all other configurations.

2-168

Asynchronous Communications Interface Adapter (ACIA)

R6551
COMMAND REGISTER

Data Terminal Ready (Bit 0)

The Command Register controls specific modes and functions.

This bit enables all selected interrupts and controls the state of
the Data Terminal Ready (DTR) line. A 0 indicates the microcomputer system is not ready by setting the DTR line high. A
1 indicates the microcomputer system IS ready by setting the
DTR line low. DTR also enables and disables the transmitter
and receiver.

Bits 7-6

2.

.2-

1

0

o
o

0

1

Bit 5

o

Bit 4

o
1

Bits 3·2

3

Receiver Interrupt Control (Bit 1)

Parity Mode Control (PMC)

This bit disables the Receiver from generating an Interrupt when
set to a 1. The Receiver Interrupt IS enabled when this bit IS set
to a 0 and Bit 0 is set to a 1.

Odd parity transmitted/received
Even panty transmitted/received
Mark parity bit transmitted
Parity check disabled
Space panty bit transmitted
Parity check disabled

Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTS) line and
the Transmitter interrupt

Parity Mode Enabled (PME)
Parity mode disabled
No panty bit generated
Parrty check disabled
Panty mode enabled

Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 disables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
O. In the Receiver Echo Mode, the Transmitter returns each
transmission received by the Receiver delayed by one-half bit
time.

Receiver Echo Mode (REM)
Receiver normal mode
Receiver echo mode brts 2 and 3
Must be zero for receiver echo mode, RTS will
be low.

Parity Mode Enable (Bit 5)
This bit enables panty bit generation and checking. A 0 disables
parity bit generation by the Transmitter and panty bit checking
by the Receiver. A 1 brt enables generation and checking of
parrty bits.

Transmitter Interrupt Control (TIC)

2

o

0

o

1

o

RTS
RTS
RTS
RTS

High, transmitter disabled
Low, transmit interrupt enabled
= Low, transmit interrupt disabled
= Low, transmit interrupt disabled
transmit break on TxD
=
=

Bit 1

Receiver Interrupt Request Disabled (IRD)
IRQ enabled (re~eiver)
IRQ disabled (receiver)

Bit 0

Data Terminal Ready (D~
Data terminal not ready (DTR high)*
Data terminal ready (DTR low)

o
o

Parity Mode Control (Bits 6, 7)
These bits determine the type of panty generated by the Transmitter, (even, odd, mark or space) and the type of panty check
done by the Receiver (even, odd, or no check).
Reset Initialization

76543210

I0 I0 I0 I0 10 10 I0 I0 I Hardware reset (RES)
I . . . 0 . 0 . 0 . 0 . O.. Program reset

NOTE
*The transmitter is disabled immediately. The receiver is
disabled but will first complete receiving a byte in process
of being received.

2-169

R6551

Asynchronous Communications Interface Adapter (ACIA)

INTERFACE SIGNALS

Interrupt Request (IRQ)

Figure 4 shows the ACIA Interface signals associated with the
microprocessor and the modem.

The IRQ pin is an interrupt output from the interrupt control logic.
It is an open drain output, permitting several devices to be connected to the common IRQ microprocessor input. Normally a
high level, IRQ goes low when an interrupt occurs.

Data Bus (00-07)

CTS

The eight data line (00-07) pins transfer data between the processor and the ACIA. These lines are bi-directional and are normally high-impedance except during Read cycles when the
ACIA is selected.

TxD
IRQ

DCD
RiW
CSO

DSR

CSI

RxC

RSO

XTLI

RSI

XTLO

Chip Selects (CSO, CS1)
The two chip select inputs are normally connected to the processor address lines either directly or through decoders. The
ACIA is selected when CSO is high and CS1 is low. When the
ACIA is selected, the internal registers are addressed in accordance with the register select lines (RSO, RS1) .

•2
DTR

RES

RTS

Register Selects (RSO, RS1)
The two register select lines are normally connected to the processor address lines to allow the processor to select the various
ACIA internal registers. Table 1 shows the Internal register
select coding.

VCC
RxD
VSS

Figure 4.

ACIA Interface Diagram
Table 1. ACIA Register Selection
Register Operation

MICROPROCESSOR INTERFACE
Reset (RES)
During system initialization a low on the RES Input causes a
hardware reset to occur. Upon reset, the Command Register
and the Control Register are cleared (all bits set to 0). The
Status Register IS cleared with the exception of the indications
of Data Set Ready and Data Carner Detect, which are externally
controlled by the DSR and DCD lines, and the transmitter Empty
bit, which IS set. RES must be held low for one 162 clock cycle
for a reset to occur.

= Low

=

RS1

RSO

L

L

Write Transmit Data
Register

Read Receiver
Data Register

L

H

Programmed Reset
(Data is "Don't
Care")

Read Status
Register

H

L

Write Command
Register

Read Command
Register

H

H

Write Control
Register

Read Control
Register

RfW

RfW

High

I

Input Clock ~2)
The Input clock IS the system J62 clock and clocks all data transfers between the system microprocessor and the ACIA.

Only the Command and Control registers can both be read and
written. The programmed Reset operation does not cause any
data transfer, but is used to clear bits 4 through 0 in the Command register and bit 2 in the Status Register. The Control Register is unchanged by a programmed Reset. It should be noted
that the programmed Reset is slightly different from the hardware Reset (RES); refer to the register description.

Read/Write (RMi)
The R/W Input, generated by the microprocessor controls the
direction of data transfers. A high on the R/W pin allows the
processor to read the data supplied by the ACIA, a low allows
a write to the ACIA.

2-170

Asynchronous Communications Interface Adapter (ACIA)

R6551
ACIA/MODEM INTERFACE

Clear to Send (CTS)

Crystal Pins (XTLI, XTLO)

The CTS input pin controls the transmitter operation. The enable
state IS w~h CTS low. The transmitter IS automatically disabled
if CTS is high.

These pins are normally directly connected to the parallel mode
external crystal (1.8432 MHz) to derive the various baud rates.
Alternatively, an externally generated clock can drive the XTLI
pin. in which case the XTLO pin must float. XTLI is the input
pin for the transmit clock.

Data Terminal Ready (DTR)
ThiS output pin Indicates the status of the ACIA to the modem.
A low on DTR indicates the ACIA is enabled. a high indicates
it IS disabled. The processor controls this pin via bit 0 of the
Command Register.

Transmit Data (TxD)
The TxD output line transfers serial nonreturn-to-zero (NRZ)
data to the modem. The least significant bit (LSB) of the Transmit
Data Register is the first data bit transmitted and the rate of data
transmission IS determined by the baud rate selected or under
control of an external clock. This selection is made by programming the Control Register.

Data Set Ready (t>SR)
The DSR input pin indicates to the ACIA the status of the
modem. A low Indicates the "ready" state and a high. "notready."

Data Carrier Detect (DC D)

Receive Data (RxD)

The DCD input pin Indicates to the ACIA the status of the carrierdetect output of the modem. A low Indicates that the modem
carrier Signal is present and a high. that It IS not.

The RxD input line transfers serial NRZ data into the ACIA from
the modem. LSB first. The receiver data rate IS either the programmed baud rate or under the control of an externally generated receiver clock. The selection is made by programming
the Control Register.

TRANSMITTER AND RECEIVER
OPERATION

Receive Clock (RxC)
The RxC is a bi-directional pin which is either the receiver 16x
clock input or the receiver 16x clock output. The latter mode
results if the internal baud rate generator is selected for receiver
data clocking.

Continuous Data Transmit
In the normal operating mode. the interrupt request output (IRQ)
signals when the ACIA is ready to accept the next data word to
be transmitted. This interrupt occurs at the beginning of the Start
BIt. When the processor reads the Status Register of the ACIA.
the interrupt is cleared.

Request to Send (RTS)
The RTS output pin controls the modem from the processor.
The state of the RTS pin is determined by the contents of the
Command Register.

.

I

iRQLJI]

I

LIlt
PROCESSOR

/

INTERRUPT
(TRANSMIT DATA
REGISTER EMPTY)

The processor must then identify that the Transmit Data RegIster is ready to be loaded and must then load it with the next
data word. This must occur before the end of the Stop Bit. otherwise a continuous "MARK" will be transmitted. Figure 5 shows
the continuous Data Transmit timing relationship.

/LlU

~

L....J\

PROCESSOR READS STATUS
REGISTER, CAUSES IRQ
TO CLEAR

Figure 5.

PROCESSOR MUST

LOAD NEW DATA
IN THIS TIME
INTERVAL. OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED

Continuous Data Transmit

2-171

I

LJI]

fJ

R6551

Asynchronous Communications Interface Adapter (ACIA)

Continuous Data Receive
Similar to the Continuous Data Transmit case, the normal
operation of this mode is to assert IRQ when the ACIA has
received a full data word. This occurs at about 9/'6 point through
the Stop Bit. The processor must read the Status Register and

CHAR#n

CHAR#n+1

/

RxD

read the data word before the next interrupt, otherwise the
Overrun condition occurs. Figure 6 shows the continuous Data
Receive Timing Relationship.

CHAR#n+3

CHAR#n+2

'-./

'-./

'-./

"

lSt"'5El ~ ~ GEl Stopistan5El ~ ~ liE] Stop ISt"t GEl ~ ~ GEJStoplsta,t5El ~ ~ GEJSto{
I

)

PROCESSOR
INTERRUPT OCCURS
ABOUT 9/16 INTO
LAST STOP BIT.
PARITY, OVERRUN.
AND FRAMING eRROR

I

I

I

I

I

I

LJn

L

'u
~

I

Ln]'
'-'\

PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL, OTHERWISE.
OVERRUN OCCURS

PROCESSOR READS~TUS
~~~I~~!=. CAUSES IRQ

ALSO. UPDATED

Figure 6.

Continuous Data Receive

Transmit Data Register Not Loaded by Processor
If the processor IS unable to load the Transmit Data Register in
the allocated time, then the TxD line goes to the "MARK" condition until the data is loaded. IRQ interrupts continue to occur
at the same rate as previously, except no data is transmitted.

CONTINUOUS "MARK"

CHARJfn
I

TxD

When the processor finally loads new data, a Start Bit Immediately occurs, the data word transmission IS started, and another
Interrupt IS initiated, signaling for the next data word. Figure 7
shows the timing relationship for this mode of operation.

CHAR#n+l

~~~-'-.~-------

nS"'t[B:G ~ ~ lSEJ StopI
/

I

I_CHARACTER_I
TIME

LJIJ'
PRoeLoR

l~--

~

\

~

L..J

INTERRUPT
FOR DATA

/

INTERRUPTS
CONTINUE AT
CHARACTER RATE,
EVEN THOUGH
NO DATA IS
TRANSMITTED

REGISTER

EMPTY
PROCESSOR
READS
STATUS
REGISTER

Figure 7.

WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY

Transmit Data Register Not Loaded by Processor

2-172

CHAR#n+2

R6551

Asynchronous Communications Interface Adapter (ACIA)

Effect of CTS or. Transmitter
CTS is the Clear-to-Send Signal generated by the modem. It is
normally low (true state) but may go high in the event of some
modem problems. When this occurs, the TxD line immediately
goes to the "MARK" condition. Interrupts continue at the same
rate, but the Status Register does not indicate that the Transmit
CHAR#n

Data Register is empty. Since there is no status bit for CTS, the
processor must deduce that CTS has gone to the FALSE (high)
state. CTS is a transmit control line only, and has no effect on
the R6551 Receiver Operation. Figure 8 shows the timing relationship for this operation.

CHAR#n+l

CONTINUOUS "MARK"

/r----------~----------

·2

CLEAR-lO-SEND
PROCESSOR READS
NEXT

m

GOES HIGH,
INDICATING MODEM
IS NOT READY TO
RECeiVe DATA. TxD
IMMEDIATELY GOES
TO "MARK" CONDITION

Figure 8.

PROCESSOR
INTERRUPT
AT NORMAL
START BIT
TIME

STATUS REGISTER

SINCE DATA REGISTER
IS NOT EMPTY, PROCESSOR
MUSTDEDUCE THAT
CTS IS SOURCE OF
INTERRUPT (THIS IS
COVERED ELSEWHERE
IN THIS NOTE).

Effect of CTS on Transmitter

Effect of Overrun on Receiver
If the processor does not read the Receiver data Register in the
allocated time, then, when the follOWing Interrupt occurs, the
new data word is not transferred to the Receiver Data Register,

but the Overrun status bit is set. Thus, the Data Register will
contain the last valid data word received and all following data
is lost. Figure 9 shows the timing relationship for this mode.

CHAR#n+l

CHAR#n

~

PROCESSOR

INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL

CHAR#n+2

PROCESSOR
READS
STATUS
REGISTER

RECEIVER DATA REGISTER
NOT UPDATED. BECAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA, OVERRUN
BIT SET IN STATUS
REGISTER

;,. .- ____ __. _ .-m
~

",---.------'/ ~

OVERRUN BIT seT IN
STATUS REGISTER

Figure 9.

Effect of Overrun on Receiver

2-173

CHAR#n+3

Asynchronous. Communications Interface Adapter (ACIA)

A6551
Echo Mode Timing

In Echo Mode,; the TxD line re-transmits the data on the RxD
line, delayed ·by '/2 of .the bit time, as shown in Figure 10.

\\ \ \ \ \ \ \\ \
!--L_.&-.....I=_ 8ao:J I rsnEJ= =8.:JStoPlstart[BOI

TKO

Stop Start

Figure 10.

Echo Mode Timing

Effect of CTS on Echo Mode Operation
In Echo Mode, the Receiver operation is unaffected by CTS,
however, the Transmitter is affected when CTS goes high, Le.,
the TxD line immediately goes to a continuous "MARK" condition. In this case, however, the Status Request indicates that

the Receiver Data Register is full in response to an IRQ, so the
processor has no way of knowing that the Transmitter has
ceased to echo. See Figure 11 for the timing relationship of this
mode.

CHAR#n+1

CHAR#n

CHAR#n+2

CHAR#n+3

NOT -CLEAR·TO-SEND

I
TKO

~:i~~r~IJ I
BN

II

1
Stoplstartl

p

BO

CONTINUOUS "MARK" UNTIL

I I 8211
B,

L_~oo,,)

"FALse" CONDITION

I

.

NORMAL_
RECEIVER DATA
REGISTER FULL
INTERRUPTS

Figure 11.

Effect of CTS on Echo Mode

2-174

ffi

GOES LOW

'\.

R6551

Asynchronous Communications Interface Adapter (ACIA)

Overrun in Echo Mode
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs. the TxD line goes to the

"MARK" condition until the first Start Bit after the Receiver Data
Register is read by the processor. Figure 12 shows the timing
relationship for this mode.

CHAR#n

CHAR#"
~

I

L...-..L..-....1
8, f f-L--L---'

_ _ _-L-_ _ _~"

L-....._-'----'

/~

CHAR:tfx+1
_ _ _--L._ _

~ ~ 8iJ StoplSt"troEl ~ ~

\ ll------.UU

EE

LllJ

TxD

I

PROCESSOR FINALLY
READS RECEIVER
DATA REGISTER,
LAST VALID

PROCESSOR

INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL

TxD DATA
RESUMES

CHARACTEA (#n)
PROCESSOR

PROCESSOR

INTERRUPT
FOR CHAR#x
IN RECEIVER
DATA REGISTER

OVERRUN OCCURS
TxO GOES TO

READS
STATUS
REGISTER

"MARK"
CONDITION

Figure 12.

Overrun In Echo Mode

Framing Error
Framing Error is caused by the absence of Stop Bit(s) on
received data. A Framing Error is indicated by the setting of bit
4 in the Status Register at the same time the Receiver Data
Register Full bit is set, also in the Status Register. In response
to IRQ, generated by RDRF, the Status Register can also be

checked for the Framing Error. Subsequent data words are
tested for Framing Error separately, so the status bit will always
reflect the last data word received. See Figure 13 for Framing
Error timing relationship.

AxD
IEXPECTEDI -'L-....._...1

AxD
(ACTUAL)

NOTES

PROCESSOR

1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.

INTERRUPT,
FRAMING
ERROR

2. IF NEXT DATA WORD IS OK,

BIT seT

FRAMING ERROR IS CLEARED.

Figure 13.

Framing Error

2-175

fI

Asynchronous Communications Interface Adapter (ACIA)

R6551
Effect of DeD on Receiver

DCD is a modem output Indicating the status of the carrier-frequency-detection circuit of the modem. This line goes high for
a loss of carrier. Normally, when this occurs, the modem will
stop transmitting data some time later. The ACIA asserts IRQ
whenever 5GB changes state and indicates this condition via
bit 5 in the Status Register.

Once such a change of state occurs, subsequent transitions will
not cause interrupts or changes In the Status Register until the
first interrupt is serviced. When the Status Register is read by
the processor, the ACIA automatically checks the level of the
DCD line, and If It has changed, another IRQ occurs (see Figure

14).

CONTINUOUS "MARK"

,

t

NORMAL
PROCESSOR
INTERRUPT

PROCESSOR
INTERRUPT
FOR Dc6
GOING HIGH

Figure 14.

/'

AS LONG AS
6Cii IS HIGH.
NO FURTHER
INTERRUPTS
FOR RECEIVER

WILL OCCUR

PROCESSOR
INTERRUPT
FOR oeD
GOING LOW

NO INTERRUPT
WILL OCCUR
HERE, SINCE
RECEIVER IS NOT
ENABLED UNTIL

PROCESSOR /
INTERRUPT
FOR
RECEIVER

DATA

FIRST START BIT
DETECTED

Effect of DeD on Receiver

Timing with 1V:z Stop Bits
It is possible to select 1V2 Stop Bits, but this occurs only for
5-bit data words w~h no parity bit. In this case, the IRQ asserted
for Receiver Data Register Full occurs halfway through the

trailing half-Stop Bit. Figure 15 shows the timing relationship for
this mode.

CHAR#n
I

CHAR#n+1

RxD

LJI]
t
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGHT THE 112
STOP BIT

Figure 15.

Timing with 1112 Stop Bits

2-176

L

R6551

Asynchronous Communications Interface Adapter (ACIA)

Transmit Continuous" BREAK"
This mode is selected via the ACIA Command Register and
causes the Transmitter to send continuous "BREAK" characters, beginning with the next character transmitted. At least one
full "BREAK" character will be transmitted, even if the processor
quickly re-programs the Command Register transmit mode.
Later, when the Command Register IS programmed back to
normal transmit mode, an immediate Stop Bit will be generated
and transmission will resume. Figure 16 shows the timing relationship for this mode.

TxO

"

~/
-I BNIPIStoplstart
-l"'U"c::t...::l....: L..:.J--I _ '
I;::1startr;;r;:1-

I

/

80

B,

BN

,
---

f-------.., -

Note
If, while operating in the Transmit Continuous "BREAK"
mode, the CTS should go to a high, the TxD Will be
overridden by the CTS and will go to continuous "MARK"
at the beginning of the next character transmitted after the
CTS goes high.

I

P

........._

Stop
...'...........,'(

tJ_ft:~~r]iE1StopISI·"rn

t---+----il

I

~,

PERIOD DURING
WHICH PROCESSOR

SELECTS

CONTINUOUS

POINT AT WHICH
PROCESSOR
SELECTS
NORMAL
TRANSMIT
MODE

"BREAK" MODE

NORMAL
INTERRUPT

'Figure 16.

,,/

PROCESSOR
INTERRUPT
TO LOAD
TRANSMIT
OAT A

Transmit Continuous "BREAK"

Receive Continuous "BREAK"
In the event the m.odem transmits continuous "BREAK" characters, the ACIA will terminate receiving. Reception will resume
only after a Stop Bit IS encountered by the ACIA. Figure 17

---------"

RxD

CONTINUOUS

shows the
characters.

"BREAK"

timing

relationship for

/

continuous

"

"BREAK"

/'-----

J::::IJSJ"I+'" ~ ,",_ ," ,~', I ~f.A.I_........~~St.rt~F[JS~Tls'"'tl I
BO

u..-----l§

1

PROCESSOR

1

I

~~~;;

~

INTERRUPTS

INTERRUPT

:=~;~s:~; ~=~;~:~PETR~6~H

FO R
RECEIVER
DATA REGISTER
FULL

BIT seT, EVEN PARITY CHECK
WILL ALSO GIVE A PARITY ERROR
BECAUSE ALL ZEROS (CONTINUOUS
BREAK) REPRESENT EVEN PARITY,

Figure 17.

II

L_..J.J

NO INTERRUPT
SINCE RECEIVER
DISABLED UNTIL
FIRST STOP BIT

Receive Continuous "BREAK"

2-177

NORMAL
RECIEVER
INTERRUPT

B,

I

PI

R6551

Asynchronous Communications Interface Adapter (ACIA)

STATUS REGISTER OPERATION

MISCELLANEOUS

Because of the special functions of the various status bits, there
is a suggested sequence for checking them. When an interrupt
occurs, the ACIA should be interrogated, as follows:

1. If Echo Mode is selected, RTS goes low.
2. If Bit 0 of Command Register(DTR) is 0 (disabled), then:
a) All interrupts are disabled, including those caused by
DCD and DSR transitions.
b) Transmitter is disabled immediately.
c) Receiver is disabled, but a character cUrrently being
received will be completed first.
.

1. Read Status Register
This operation automatically clears Bit 7 (IRQ). Subsequent
transitions on DSR and DCD will cause another interrupt.
2. Check IRQ (Bit 7) in the data read from the Status Register

3. Odd parity occurs when the sum of all the 1 bits in the data
word (Including the parity bit) is odd.

If not set, the interrupt source is not the ACIA.
3. Check

4. In the receive mode, the received parity bit does not go into
the Receiver Data Register, but generates partty error or no
parity error for the Status Register.

BCD and DSR

These must be compared to their previous levels, which must
have been saved by the processor. If they are both 0 (modem
"on-line") and they are unchanged then the remaining bits
must be checked.

5. Transmitter and Receiver may be in full operation simultaneously. This is "full-duplex" mode.
6. If the RxD line Inadvertently goes low and then high right
after a Stop Bit, the ACIA does not interpret this as a Start
Bit, but samples the line again halfway into the bit to determine if it is a true Start Bit or a false one. For false Start Bit
detection, the ACIA does not begin to receive data, instead,
only a true Start Bit initiates receiver operation.

4. Check RDRF (Bit 3)
Check for Receiver Data Register Full.
5. Check Parity, Overrun, and Framing Error (Bits 0-2) if the
Receiver Data Register is full.

7. Precautions to consider with the crystal oscillator circuit:
6. Check TORE (Bit 4)

a) The external crystal should be a "series" mode crystal.
b) The XTALI input may be used as an external clock input.
The unused pin (EXTALO) must be floating and rnay not
be used for any other function.

Check for Transmitter Data Register Empty.
7. If none of the above conditions exist, then CTS must have
gone to the false (high) state.

PROGRAM RESET OPERATION

S. DCD and DSR transitions, although causing immediate processor interrupts, have no affect on transmitter operation.
Data will continue to be sent, unless the processor forces
transmitter to turn off. Since these are high-impedance inputs,
they must not be permitted to float (un-connected). If unused,
they must be terminated either to GND or V cc.

A program reset occurs when the processor performs a write
operation to the ACIA with RSO low and RS1 high. The program
reset operates somewhat different from the hardware reset
(RES pin) and is described as follows:

GENERATION OF NON-STANDARD
BAUD RATES
Divisors

1. Internal registers are not completely cleared. Check register
formats for the effect of a program reset on internal registers.

The internal counter/divider circuit selects the appropriate divisor for the crystal frequency by means of bits 0-3 of the ACIA
Control Register, as shown in Table 2.

2. The DTR line goes high immediately.

Generating Other Baud Rates
3. Receiver and transmitter interrupts are disabled immediately.
If I RQ is low when the reset occurs, it stays low until serviced, unless interrupt was caused by DCD or DSR transnion.

By using a different crystal, other baud rates may be generated.
These can be determined by:
Baud Rate

4. DCD and DSR interrupts are disabled immediately. If IRQ is
low and was caused by DCD or DSR, then it goes high, also
DCD and i5SR status bits subsequently will follow the input
lines, although no interrupt will occur.

Crystal Frequency

= -------

Divisor
Furthermore, it is possible to drive the ACIA with an off-chip
oscillator to achieve other baud rates. In this case, XTALI (pin
6) must be the clock input and XTALO (pin 7) must be a noconnect.

5. Overrun cleared, if set.

2-178

R6551

Asynchronous Communications Interface Adapter (ACIA)
Table 2.

Control
Register
Bits

Divisor Selected
For The
Internal Counter

3

2

1

0

0

0

0

0

No D,v,sor Selected

0

0

0

1

36,864

Divisor Selection
Baud Rate Generated
With 1.8432 MHz
Crtstal

16 x External Clock
at Pin RxC
1.8432

X

0

0

1

0

24,576

1.8432 x 10·

F
-36,864
-

75

F
-24,576
-

109.92

---

134.51

---

150

---

300

---

600

---

1,200

---

1,800

---

2,400

---

3,600

---

4,800

---

7,200

---

9,600

---

19,200

---

24,576
0

0

1

1

16,769

18432 x 10·
16,769

0

1

0

1

0

0

13,704

0

1

12,288

1 8432 x 10·
13,704
1.8432 x 10·

0

1

1

1

1

0

1

6,144

3,072

6,144

3,072
1

0

.

0

1,536

0

0

1

1,024

1

0

1

0

768

1.8432 x 10·
768

1

1

1

0

1

1

1

1

0

0

0

1

512

384

1.8432 x 10·
512
1.8432 x 10·
384

1

1

0

192

1

1

1

1

96

1 8432 x 10·
96

2-179

768

512
F

384
F

1.8432 x 10.
192

1,024

F

256
1

1,536

F

1.8432 x 10"
256

3,072

F

1.8432 x 10"
1,024

6.144

F

1,536
1

12,288

F

18432 x 10.
0

F

13,704

F

18432 x 10·

1.8432 x 10.

F

16,769

F

12,288
0

16 x External Clock
at Pin RxC

50

10·

36,864

Baud Rate Generated
With a Crystal
of Frequency (F)

256
F

192
F

96

Asynchronous Communications Interface Adapter (ACIA)

R6551
DIAGNOSTIC LOOP-BACK
OPERATING MODES

A simplified block diagram for a system incorporating an ACIA
is shown in Figure 1 8 . '

back operation. In this way, the processor can easily perform
local loop-back diagnostic testing.

It may be desirable to include in the system a facility for "Ioopback" testing, of which there are two kinds:

Remote loop-back does not require this circuitry, so LLB must
be set low. However, the processor must select the follOWing:

1. Local Loop-Back
1. Control Register bit 4 must be 1, so that the transmitter clock
equals the receiver clock.

Loop-back from the point of view of the processor. In this
case, the Modem and Data Link must be effectively disconnected and the ACIA transmitter connected back to ItS own
receiver, so that the processor can perform diagnostic checks
on the system, excluding the actual data channel.

2. Command Register bit 4 must be 1 to select Echo Mode.
3. Command Register bits 3 and 2 must be 1 and 0, respectively to disable IRQ interrupt to transmitter.

2. Remote Loop-Back
4. Command Register bit 1 must be 0 to disable IRQ interrupt
for receiver.

Loop-back from the point of view of the Data Link and
Modem. In this case, the processor, itself, is disconnected
and all received data IS immediately retransmitted, so the
system on the other end of the Data Link may operate Independent of the local system.

In this way, the system re-transmits received data without any
effect on the local system.

The ACIA does not contain automatic loop-back operating
modes, but they may be implemented with the addition of a
small amount of external circUitry. Figure 19 mdicates the necessary logic to be used wrth the ACIA. The LLB line IS the posItive-true signal to enable local loop-back operation. Essentially,
LLB = high does the following.
1. Disables outputs TxD, DTR, and RTS (to Modem).
2. Disables Inputs RxD, DCD, CTS, DSR (from Modem).
3. Connects transmitter outputs to respective receiver Inputs
(I.e., TxD to RxD, DTR to DCD, RTS to CTS).
TO DATA LINK

LLB may be tied to a peripheral control pin (from an R6520 or
R6522, for example) to provide processor control of local loop-

I

Figure 18.

Simplified System Diagram

R6551
RTS OTR TxD

R xD

LLB

SEL

-:r-

BCD

eTS DSR

I

1vJ
2V
3V

STB

4V

74157
1B

1A

2B

2A

3B

3A

~4B

4A

Rxo
oeD
eTS
DSR

MODEM

-

SEL

Txo

1V

DTR

2V

~

STB

RTS

3V
4V

-

74157
+5

C
-

1B

1A

2B

2A

3B

3A

4B

4A f-

NOTES

1. HIGH ON lLB SELECTS LOCAL LOOP-BACK MODE

2 HIGH ON 74157 SELECT INPUT GATES "B" INPUTS
TO "Y" OUTPUTS, lOW GATES "A" TO "Y"

Figure 19.

Loop-Back Circuit Schematic
2-180

R6551

Asynchronous Communications Interface Adapter (ACIA)

READ TIMING DIAGRAM
Timing diagrams for transmit with external clock, receive with
external clock, and IRQ generation are shown in Figures 20, 21
and 22, respectively. The corresponding timing characteristics
are listed in Table 3.

Table 3.

XTLI
(TRANSMIT
CLOCK INPUT)
_ _ _..I

Transmit/Receive Characteristics
1 MHz

Characteristic

2 MHz

TxD

Symbol

Min

Max

Min

Max

Unit

Transmit/Receive
Clock Rate

tCCY

400*

-

400*

-

ns

Transmit/Receive
Clock High Time

IcH

175

-

175

-

ns

Transmit/Receive
Clock Low Time

IcL

175

-

175

-

ns

XTLI to TxD
Propagation Delay

too

-

-

500

ns

RTS Propagation
Delay

t OLY

-

500

-

500

ns

IRQ Propagation
Delay (Clear)

tlRQ

-

500

-

500

ns

Load Capacitance
DTR, RTS
TxD

CL

-

130
30

-

130
30

pF
pF

500

NOTE: TxD rate

Figure 20.

----.II

~

(INPUT)

-

I

¥

L

l-tCL~

NOTE: RxD rat. is 1/16 RxC rate

Receive External Clock Timing

~/

ct>2 _ _

Notes:
(tR' tF = 10 to 30 ns)

*The baud rate with external clocking is: Baud Rate =

r- ""i
t CCY -

I

Figure 21.

-

1/16 TxC rate

Transmit Timing with External Clock

I
RxC

IS

1
16 x tcCY

\f-i- -

_----+--.i,·tDLyk=
DTR. RTS

IRQ
(CLEAR)

Figure 22.

2-181

.

.

----------------+---

~.'"Q}--

Interrupt and Output Timing

Asynchronous Communications Interface Adapter (ACIA)

R6551
AC CHARACTERISTICS

(Vee = 5.0V ± 5%, Vss = 0, TA = TL to T H, unless otherwise noted)
2 MHz

1 MHz

Parameter

Symbol

Min

Min

Max

Cycle Time

tCYC

r62 Pulse Width

tc

400

-

Address Set-Up Time

tACW

120

Address Hold Time

tCAH

R/W Set-Up Time

0.5

Max

Unit

40

P.s

200

-

ns

-

70

-

ns

0-

-

0

ns

twcw

120

-

70

R/W Hold Time

tCWH

0

0

Data'Bus Set-Up Time

tocw

150

60

Data Bus Hold Time

tHW

20

-

20

-

Read Access Time (Valid Data)

tCOR

-

200

-

150

ns

Read Hold Time

tHR

20

tCOA

40

-

20

Bus Active Time (Invalid Data)

-

Notes: 1,
2,
3,
4,

40

1.0

40

ns
ns
ns
ns

ns
, ns

Vcc = 5,OV ±5%.
TA = Tc to TH'
tR and tF = 10 to 30 ns,
00-07 load capacitance = 130 pF,

1-----tc----·1

,r-----V,H
02
VII':

,r..--------- V,H
RM
V/L

r-r__

-_~t_HW

tDC_W
____

__

_:tI~ ~

DATABUS_~----------~~

'V
H
'
,L

WRITE TIMING DIAGRAM

RM

~----+----------+------------_ _ _ tWCR

.----tcDR_

DATA BUS ---------+---1(OOG>
?

(
)

-

N
T
T

I
g
h
i
j

F
G
H

,

¢

B
C
D
E

6
7
8
9
:

&

CAN

A

/

X

CAN -Cancel
¥ -Yen
-Pound
t
¢
-Cent
12 -One·Hall
N
- No Tax
T
T
4 Tax

Line Feed

VT - Vertical Tabulation
FF - Form Feed
CR - Carriage Return
DCl - Device Control 1
DC2 - Device Control 2
DC3 - Device Control 3
DC4 - Device Control 4

X

Note: Valid control commands are dependent upon printer model.

2-190

6

x
y

z

I
}

R6592

Single-Chip Printer Controller

PARALLEL DATA INTERFACE

BUSY
BUSY RET

r-11
29

INPUT PRIME
INPUT PRIME RET

31
30

DATA STROBE
DATA STROBE RET

1
19

ACKNOWLEDGE
ACKNOWLEDGE RET

10
28

DATA 1
DATA 1 RET

2
20

DATA 2
DATA 2 RET

3
21

DATA 3
DATA 3 RET

4
22

·NOT REQUIRED IF PARALLEL DATA
IS HELD FOR ",50 ~S AFTER LEADING
EDGE OF DS OR UNTIL ACK IS RECEIVED.

DATA 4
DATA 4 RET

5
23

DATA 5
DATA 5 RET

6
24

DATA 6
DATA 6 RET

7
25

DATA 7
DATA 7 RET

8
26

DATA 8
DATA 8 RET
CENTRONICS PARALLEL INTERFACE

9

-

BUSY/DTR

~
~
~

9

iP/DSR

22

DS

37

ACK

~~

8
R6592

DL1/BR1
29

~

DL2/BR2
28

~

DL3/BR3
27

~

LATCH"

DL4/BR4
26

~

DL5

~

DL6

25
24

R.
R.
f--

27~

DL7
23
R6592 INTERFACE

':

PARALLEL DATA TIMING

- - - - - I f i-----ff---f $1---- -- ------q--- --- . .n---H---f r- - - - - - - - - - - - ( , 1-\

INPUT PRIME (iP)

DATA STROBE (DS)

PARALLEL DATA (DL 1... DL7)

BUSY

-------!IIi-----'~ ~f------4 ~I--·OR UNTIL ACK IS RECEIVED.

2-191

fJ

R6592
SERIAL DATA INTERFACE

RECEIVED SERIAL
DATA (RSD)

3

6~----------------------------------~

DATA SET READY (DSR)

+12V
DATA TERMINAL READY (DTR)

---------0<

20 . .

"---v---'

-12V

RS·232 INTERFACE

SERIAL DATA TIMING
DATA SET READY (DSR)

----------------1$ Hf--iSS---

- - - - - - -

-

-

-

-

-

-

- - -

--{ f- -If- -f f-

-

- --

Ir-(-.----,--,--

i I -r-----t>cl- -----t-;;-tr~:;1

I

DATA

I

START

I

I

I

LBS

I.

I-T-r

I

I

I

I

L..l_L_

STOP

(1, 1'12, OR 2 BITS)

1

.1

5 TO 8 BITS

ISOCHRONOUS FRAME FORMAT
CLK

DATA

I

j--I----t>cl-----l--l--"TI---.,..:-j~I-S-TA-R-T-.l ~;;

1 -

-

~

-rr-- - 5 TO 8 BITS

Figure 4.

t-;s;-1

r~~~Yl ~:2B~s-l-

.1

Asynchronous snd Isochronous Frsme Format

Isochronous ReceIve

BIT ORIENTED PROTOCOLS (BOP)

In the isochronous (ISOC) mode, a 1 times clock on RxC is
reqLlired with the data on RxD and the serial data bit is latched
on the failing edge of each clock pulse. The requirement for the
detection of a valid start bit, or the beginning of a break, is
satisfied by the detection of a hlgh-to-Iow transition on the serial
data Input line. Error detection and status Indication are the same
as the asynchronous mode.

In bit oriented protocols (BOP), messages (data) are transmitted
and received In frames. Each frame contains an opening flag,
address field, control field, frame check sequence, and a closIng flag. A frame may also contain an Information field. (See
Figure 5).
The opening flag Is a special character whose bit pattern Is
01111110. It marks the frame boundaries and Is the Interframe
fill character. The address field of a frame contains the address
of the secondary station which Is receiving or responding to a
command. The address field may be one or more bytes long.
The address field can be extended by setting the ADD EX bit
to a 1 In PSR1. In this case, the address field will be extended
until the occurrence of an address byte with a 1 In bit O. The
first byte of the address field Is automatically checked when the
MPCC Is programmed to be a secondary station In BOP. An
automatic check for global (11111111) or null (00000000)
address Is also made.' The control field of one or two bytes Is
transparent to the MPCC and sent directly to the host without
interpretation.

Asynchronous and Isochronous TransmIt
In asynchronous and IsochronoLls transmit modes, output data
tans mission on TxD begins with the start bit. This is followed
by the data character which is transmlttea'LSB first. If parity
generation is enabled, the parity bit Is transmitted after the MSB
of the character.

SYNCHRONOUS MODeS
In synchronous modes, a one-times clock is provided along with
the data. Serial OLltput data Is shifted out and Input data Is latched
on the failing edge of the clock.

2-212

Multi-Protocol Communications Controller (MPCC)

R65560

The optional information field consists of a-bit characters. Cyclic
redundancy checking is used for error detection and the CRC
remainder resulting from the calculation is transmitted as the
frame check sequence field. For BOP, the polynomial X16 +
X12 + X5 + 1 (CRC-CCITT) should be used, i.e., selected in
the CRC SEL bits in the ECA. The registers representing the
CRC-CCITT polynomial are generally preset to all 1s, and the
1s complement of the resulting remainder is transmitted. (See
X.25 Recommendation.)

at the close of a frame and the C/PERR bit in the RSR is updated.
The FCS and the Flag are not passed on to the RxFIFO.
If the Flag is a closing flag, checks for short frame (no control
field) and CRC error conditions are made and the appropriate
status is updated. When an Abort (seven 1S) is detected, the
remaining frame is discarded and the FAtB bit is set in the RSR.
When a link idle (15 or more consecutive 1s) is detected, the
RIDLE status bit is set in the RSR. The zeros that have been
inserted to distinguish data from special characters are detected
and deleted from the data stream before characters are assembled. The MPCC programmed as a secondary station provides
automatic address matching of the first by1e. If there is no
address match, the receiver (secondary station) ignores the
remainder of the frame by searching for the Flag. If there is a
match, the address by1es are transferred to the RxFIFO as they
are assembled.

Zero insertion/deletion is employed to prevent valid frame data
from being confused with the special characters. A 0 is inserted
by the transmitter after every fifth consecutive 1 in the data
stream. These inserted zeros are removed by the receiver to
restore the data to its original form. The inserted zeros are not
included in the CRC calculation.
The end of the frame is determined by the detection of the
closing Flag special character which is the same is the opening
Flag.

For the control field, one or two by1es are assembled and passed
on to the RxFIFO depending on the state of the extended control
field bit.

With the control options offered by the MPCC, commony used
bit oriented protocols such as SDLC, HDLC and X.25 standards
can be supported. Figure 6 compares the requirements of these
options.

If the CFCRC bit in the ECR is set to 1, an intermediate CRC
check will be made after the address and control field. The Frame
Check Sequence is still calculated over the remainder of the
frame.

BOP Receiver Operation
BOP Transmitter Operation

In BOP, the receiver starts assembling characters and accumulating CRC immediately after the detection of a Flag. The receiver
also continues to search for additional Flag, or Abort, characters
on a bit-by-bit basis. Zero deletion is implemented in the Receiver
Shift Register after the Flag detection logic and before the CRC
circuitry. The receiver recognizes the shared flag (the closing
flag for one frame serves as the opening flag for the next frame)
and the shared zero (the ending 0 of a closing flag serves as
the beginning 0 of an opening flag forming the pattern
"011111101111110."

In BOP, the TxFIFO can be preloaded through the TDR while
the transmitter is disabled (TEN = 0 in the TCR). When the
transmitter is enabled (TEN = 1 in the TCR), the leading FLAG
is automatically sent prior to transmitting data from the TxFIFO.
The TDRA bit is set to 1 in the TSR as long as TxFIFO is not
full. If an underrun occurs, the TUNRN bit in the TSR is set to
a 1 and an ABORT (11111111) is transmitted followed by continuous FLAGSs or marks until a new sequence is initiated.

Character assembly and CRC accumulation are stopped when
a closing Flag or Abort is detected. The CRC accumulation
includes all the characters between the opening Flag and the
closing Flag. The contents of the CRC register are checked

The TLAST bit in the TCR must be set prior to loading the last
character of the message to signal the transmitter to append
the two-byte Frame Check Sequence (FCS) following the last
character. If the transmitter DMA mode is selected (the TDSREN
bit set to 1 in the TCR) the TLAST bit is set by the DONE signal
from the DMAC.

FLAG
01111110

ADDRESS
1 OR N
BYTES

INFORMATION
N BYTES
(OPTIONAL)

CONTROL
10R
2 BYTES

Figure 5.

2 BYTES

FLAG
01111110

FCS

Bit Oriented Protocol (BOP) Frame Format

IBM SOLS FRAME FORMAT
FLAG
01111110

ADDRESS
1 BYTE

CONTROL
1 BYTE

INFORMATION
N BYTES

FCS
2 BYTES

FLAG
01111110

CONTROL
10R
2 BYTES

INFORMATION
N BYTES

FCS
2 BYTES

FLAG
01111110

ADCCP/HDLC FRAME FORMAT
FLAG
01111110

ADDRESS
N BYTES

Figure 6.

Implemented Bit Oriented Protocols
2-213

EI

Multi-Protocol Communications Controller (MPCC)

R65560

A message m~y be terminated at any time by setting the TABT
bit in the TCR to 1 . This causes the transmitter to send an Abort
character followed by the remainder of the current frame data
in the TxFIFO.

A heading is a block of data starting with an SOH and containing one or more characters that are used for message control
(e.g., message identification, routing, and priority). The SOH
initiates the block-check-character (BCC) accumulation, but is
not included in the accumulation. The heading is terminated by
STX when it is part of a block containing both heading and text.
A block containing only a heading is terminated with an ITB or
an ETB followed by the BCC. Only the first SOH or STX in a
transmission block following a line turnaround causes the BCC
to reset. All succeeding STX or SOH characters are included
in the BCC. This permits the entire transmission (excluding the
first SOH or STX) to be block-checked.

The serial data from the Transmitter Shift Register is continuously monitored for five consecutive 1s, and a 0 is inserted in
the data stream each time this condition occurs (excluding Flag
and Abort character~).
CRC accumulation begins with the first non-Flag character and
includes all subsequent characters. The CRC remainder is
transmitted as the FCS following the last data character. If the
CTLCRC bit in the EC,R is set to 1, an intermediate CRC
remainder is appended after the Address and Control field. The
final Frame Check Sequence is calculated over the balance of
the frame.

The text data is transmitted in complete units called messages,
which are initiated by STX and concluded with ETX. A message
can be subdivided into smaller blocks for ease in processing
and more efficient error control. Each block starts with STX and
ends with ETB (except for the last block of a message, which
ends with ETX). A single transmission can contain any number
of blocks (ending with ETB) or messages (ending with ETX). An
EOT following the last ETX block indicates a normal end of
transmission. Message blocking without line turnaround can be
accomplished by using ITB (see the Additional Data Link
Capabilities section, IBM GA 27-3004-2).

BISYNC (BSC)
The structure of messages utilizing the IBM Binary Synchronous
Communications (BSC) protocol, commonly called Bisync, is
shown in Figure 7. The MPCC can process both transparent and
nontransparent messages using either the EBCDIC or the ASCII
codes. The CRC-16 polynomial should be selected by setting
the appropriate CRCSEL bits in the ECR for both transparent
and non-transparent EBCDIC and for transparent ASCII coded
messages. VRC/LRC should be selected for non-transparent
ASCII coded messages. BSC messages are formatted using
defined data-link control characters. Data-link control characters
generated and recognized by the MPCC are listed in Table 4.
Table 4.

Two modes of data transfers are used in BSC. In non-transparent
mode, data link control characters may not appear as text data.
In transparent mode, each control character is preceded by a
data link escape (OLE) character to differentiate it from the text
data. Table 5 indicates which control characters are excluded
in the CRC generation. All characters not shown in the table are
included in the CRC generation. Figure 8 shows various formats
for Control/Response Blocks and Heading and Text Blocks.

BSC Data-Link Control Characters

ASCII
Command Byte 1
SYN
16"
01
SOH
STX
02
ETB
17
ETX
03
ENO
05
DLE
10
ITB
IF
EOT
04
ACKW
10
NAK
15
WACK
10
RVI
10

Byte 2

-

-

-

30-37

-

3B
3C

Command
SYN
SOH
STX
EOB (ETB)
ETX
ENO
DLE
ITB
EOT
ACK 0
ACK 1
NAK
WACK
RVI

EBCDIC
Byte 1
32"
01
02
26
03
2D
10
IF
37
10
10
3D
10
10

Byte 2

-

-

Table 5.

SYN
1 BYTE
(AR2)

Character of Sequence

Yes

No

TSYN
TSOH
TSTX"
TETB
TETX
TDLE

-

DLESYN
DLESOH
DLESTX
DLE
DLE
DLE(DLE)

-

70
61

6B
7C

ETB
ETX
(DLE)DLE

"If not preceded within the same block by transparent heading
information.

SYN
1 BYTE
(AR2)
Figure 7.

Inclusion

Included In CRC Accumulation

-

Note: "Programmable

LEADING PAD
1 BYTE
(AR1)

BSC Control Sequences in CRC Accumulation

BODY

BSC Block Format

2-214

BCC

TRAILING
PAD
11111111

)

:D
0)

U1
U1

CONTROURESPONSE BLOCKS:

0)

o
ADDRESS

s::

c

=
,""'tJ
g

NEGATIVE ACKNOWLEDGEMENT

HEADING AND TEXT BLOCKS:
I\)

~

RESET BCC

'"
SYN

SYN

I

SOH

-!,
I

INCLUDED IN BCC

HEADING

T

-!
I:~B I----=--~~~L~A~-

o

()

2-

oo
3
3
c

HEADING ONLY
RESET BCC

-!'

INCLUDED IN BCC

-j

r-INCLUDED IN B C C - j

"" I "" I '"" I H'~,"G I I IT:' I,,+"I
sn

I- - - - ,-BC - - - - ,-I- - - - -,~ ~L~A~-I

ETx
" : - - - - - ' TI---------T

NONTRANSPARENT HEADING AND TEXT
RESET BCC --iINCLUDED IN BCC1

~---r-----'------'-------'i-S~T~x-;-i--T--i,;'

!'

I DC< "" I :

TRANSPARENT TEXT

-!

INCLUDED IN BCC"

DC'"

En

I Bee

~

5"

!.
0"
~

o

o
o

-

I;~~'~A~I a

"OLE EXCLUDED FROM BCC CALCULATION

~

CD

~

s::

"'tJ

o

Figure 8.

.9

esc Message Format Examples

~

Multi-Protocol Communications Controller (MPCC)

R65560
esc Receiver Operation

The message is terminated by the transmission of the BCC
followed by a closing pad when an ETB, ITB, or ETX is fetched
from the TxFIFO. The closing PAD is generated by the MPCC.

Character length defaults to eight bits in BSC mode. When ASCII
is selected, the eighth bit is used for parity provided that
VRC/LRC polynomial is selected. Character assembly starts after
the receipt of two consecutive SYN characters. Serial data bits
are shifted through the Receiver Shift Register into the Serialto-Parallel Register and transferred to the RxFIFO. The ROA
status bit in the RSR is set to 1 each time data is transferred
to the RxFIFO. The SYN character pairs in non-transparent mode
and OLE-SYN pairs in transparent mode are discarded.

In transparent mode, the BCC accumulation is initiated by
OLE-STX and is terminated by the sequences OLE-ETX,
OLE-ETB, or OLE-ITB. See Table 5 for character sequence and
inclusion in CRC accumulation. If an underrun occurs, OLE-SYN
characters will be transmitted until new characters are available
in the TxFIFO. ETC, ETX, ITB, or ENQ with a TLAST tag is
treated as a control character and the MPCC automatically
inserts a OLE immediately preceding these characters.
OLE-ETB, OLE-ETX, OLE-ITB, or OLE-ENQ terminates a block
of transparent text, and returns the data link to normal mode.
BCC generation is not used for messages beginning with
characters other than SOH, STX, OLE-SOH, or OLE-STX. On
all message types, if the TSYN bit is set to 1 in the TCR, a
SYN-SYN (OLE-SYN sequence on transparent messages)
sequence is transmitted before the next character is fetched from
the TxFIFO.

The receiver starts each block in the non-transparent mode. It
switches to transparent mode if a block begins with a OLE-SOH
or OLE-STX pair. The receiver remains in transparent mode until
a OLE-ITB, OLE-ETB, OLE-ETX or OLE-ENQ pair is received.
BCC accumulation begins after an opening SOH, STX, or
OLE-STX. SYN characters in non-transparent mode or OLE-SYN
pairs in transparent mode are excluded from the BCC
accumulation. The first OLE of a OLE-OLE sequence is not
included in the BCC accumulation and is discarded. The BCC
is checked after receipt of an ITB, ETB, or ETX in
non-transparent mode or OLE-ITB, OLE-ETB, OLE-ETX in
transparent mode. If a CRC error is detected, the C/PERR and
EOF bits in the RSR are set to 1. If no error is detected only
the EOF bit is set. If the closing character was an ITB, BCC
accumulation and character assembly starts again on the first
character following the BCC.

CHARACTER ORIENTED PROTOCOLS
The character oriented protoc'ol (COP) option uses the format
shown in Figure 9. It may be used for various character Oriented
protocols with 5-8 bit character sizes and optional parity
checking. The input data is checked on a bit-by-bit basis for a
pair of consecutive SYN characters to establish character
synchronization. These SYN characters are discarded after
detection. The PAO and SYN characters may be 5-8 bits long
and are user programmable as stored in AR1 and AR2,
respectively.

esc Transmitter Operation
BSC transmission begins with the sending of an opening pad
(PAO) and two sync (SYN) characters. These characters are
programmable and stored in AR1(PAO) and AR2(SYN). SOH or
STX initiates the block-cheek-character (BCC) accumulation. An
initial SOH or STX is not included in the BCC accumulation.
Should an underrun condition occur, the content of AR2
(normally SYN character) is transmitted until new characters
become available.

LEADING PAD
5-8 BITS
(AR1)

SYN

SYN

5-8 BITS

5-8 BITS

(AR2)

(AR2)
Figure 9.

If parity checking is enabled the characters assembled after
character sync are checked for parity errors. If STRSYN is set
in the RCR, all SYN characters detected within the message
will be discarded and will not be passed on to the RxFIFO. If
STRSYN is reset, SYNs detected within the message will be
treated as data.

MESSAGE
BIT CHARACTERS ---------l.~1

I~o(-------- 5-8

Character Oriented Protocol Format

2-216

Multi-Protocol Communications Controller (MPCC)

R65560

:Ii

w
cc

ou
:liC
oa:
.... 0

uc
IcAll!!
Ii: u IG:E~~ fac~C ~I&! ~
r
I/)

I

~il~

fJ

AOoA4

A5-A15

-

V

CS

lu

i~

00.07

ANI
<1>2

.

--'"

I

IRQ

I
s

I
!
..
c:i

All-Aa

i

00.07

ANI
r/>2
1ft

i

w

II

-

~ II , 12

v

i

II

~=
I!~

2-217

'"11-

c

a:

~i
~I

::0

en
en
en
en
o

AD-AI5

DO-D7

r-

RM
MC6800
MPU

-

I--

VMA

f-

.... ilID

fJJ C

~16

...

~~

.

".~

JJ

~

C
0;>
C

...

'---

-

~ ~
-~¥

. ~<

~

t

".

~

..

0>

;.

C

~

.

lJl

I\)

~

TXROO

~

ClK

(X)

R

MEMORY

·"1

<1>2

MC6875
CLOCK
GENERATOR

MC6844
DMAC

BUS ,,2
DMA REQ
DMA GRANT

f2

TXRQl
OC

,,2

IRQ/DEND

DRQT
TXSTB

DGRNT

L__ ... _. _

TXAKA

l;D

JJ

~I

~

6
...

lJl

s::

c

::;

".
0;>
".

..

""tI

S
o

TDSR

()

A

~
.....

-

R65560

MPCC
RDSR

2o
3
3

(')
TO MODEM
ORDCD

c

;:,

DTS
DACK

ri"

<1>2

+

!.

is"
;:,

fA
(')

-a...
o;:,

CD

s::

"tI

(')

Figure 11.

Typical Interface to 6800-Based System

,g

Multi-Protocol Communications Controller (MPCC)

R65560

AG-A4

CS

fI

,2
RJW
DO-D7

NOTES: TIMING MEASUREMENTS ARE REFERENCED 10 AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A
HIGH VOLTAGE OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.

Figure 12. MPCC Read Cycle Timing

AG-A4

CS

DO-D7

NOTES: TIMING MEASUREMENTS ARE REFERENCED 10 AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A
HIGH VOLTAGE OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.

Figure 13. MPCC Write Cycle Timing

2-219

Multi-Protocol Communications Controller (MPCC)

R6556()

INTERNAL
RECEIVER
CLOCK
(BAUD
RATE)
RDSR

EXTERNALLY
LATCHED
RDSR

\

t

/

\

@

i

/

\

I

\

I

\

DACK

'2
DO-D7

\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\

1111111111111111

NOTES: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH
VOLTAGE OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.

Figure 14. MPCC to Memory DMA Transfer Cycle Timing (Receiver DMA Mode).

2-220

Multi-Protocol Communications Controller (MPCC)

R65560

INTERNAL
TRANSMITTER
CLOCK

TDSR

EXTERNALLY
LATCHED
TDSR

\

-t

I

\

@

f

I

\

\

/

\

I

DO-D7

lllllllOOIOOOUlloomlWI

\\\\\\\\\\\\\\\

NOTES: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH
VOLTAGE OF 2.0 VOLTS. UNLESS OTHERWISE NOTED.

Figure 15.

Memory to MPCC DMA 1\'ansfer Cycle Timing (Transmitter DMA Mode).

2-221

r

fJ

Multi-Protocol Communications Controller (MPCC)

R65560

HIGH SPEED APPLICATION

~--------~30r---------~

TxC/RxC

TxD/RxD

LOW SPEED APPLICATION (RS·232 COMPATIBLE)

TxC

TxD

DATA A

RxC (TxC)

Figure 16. Serial Interface Timing

RxD

TxD

NOTE: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH
VOLTAGE OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.

Figure 17. Serial Interface Echo Mode Timing

2·222

Multi-Protocol Communications Controller (MPCC)

R65560

AC CHARACTERISTICS
(Vee = 5.0 Vdc ± 5%, Vss = 0 Vdc, T A = DoC to 70 0 e)
Paramater

Number

Min

Symbol

Max

Unit

1

RIW High to 02 High

tRH2H

0

2

Address Valid to CS Low

tAVSL

30

-

3

CS Low to 02 High

tSL2H

30

-

ns

4

02 High to Data Valid

t2HDV

0

140

ns

5

02 Low to Data Invalid

t2LDXR

10

150

ns

6

02 Low to RIW Low

t2LRL

20

-

ns

7

02 Low to Address Invalid

12LAI

20

8

RIW Low 10 02 High

IRL2H

0

9

Dala Valid 10 02 Low

I DV2L

60

10

02 Low 10 Data Invalid

12LDXW

11

02 Low to RIW High

12LRH

20

15

DACK Low to 02 High

IAL2H

125

16

02 Low 10 DACK High

t2LAH

65

17

DTS Low to 02 Low

ISL2L

60

-

18

DACK Low 10 Dala Valid, DONE Low

tALDV

0

140

ns

19

02 Low 10 Data Invalid

12LDXDR

10

150

ns

20

DACK, DONE Low 10 02 High

IAL2H

125

21

Data Valid 10 02 Low

tDV2L

60

22

02 Low to Data Invalid

t2LDXDW

-

ns

-

ns

23

02 Low 10 DACK, DONE High

t2LDH

30

RxC and TxC Period

Icp

31

TxC Low 10 TxD Delay

tTCLTO

32

RxC Low to RxD Transition (Hold)

33

0

0
65

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns

ns
ns

-

ns

0

200

ns

tRCLRO

0

RxD Transition 10 RxC Low (Setup)

tRORCL

30

34

RxD 10 TxD Delay (Echo Mode)

tRoTO

-

-

35 1• 2

RDSR Pulse Widlh

tRPW

1

361.3

TDSR Pulse Widlh

tTPW

1

246

ns
ns

200

ns

-

clock period

-

clock period

Notes:
1. For synchronous prolocols. Ihis is one full serial clock period of RxC for RDSR and TxC for TDSR.
2. For asynchronous prolocols. RDSR is asserted for two syslem clock periods for a prescale faclor of 2 and for three syslem clock
periods for a prescale faclor of 3.
3 For asynchronous prolocols, TDSR IS asserted of one-half Ihe baud rale.

MDCC1

MPCC2

MPCC1

TxC

RxC

TxC

TxD

RxD

TxD

Rx DATA (BB)

RxC

TxC

RxC

Tx TIMING (DA)

RxD

TxD

I

HIGH SPEED INTERFACE

RxD

MODEM/DCE

~

I~

Rx TIMING (DO)

I

Tx DATA (BA)

LOW SPEED (R8-232) INTERFACE

Figure 18. Serial Interface

2·223

I

Multi-Protocol Communications Controller (MPCC)

R65560
ABSOLUTE MAXIMUM RATINGS·
Parameter

Supply Voltage

Symbol

Value

Unit

V

Vee

-0.3 to +7.0

Input Voltage

Y'N

-0.3 to + 70

Operating Temperature

TA

Storage Temperature

TSTG

o to

+ 70

-NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

V
°C

-55 to + 150

°C

THERMAL CHARACTERISTICS
Parameter

Symbol

Thermal Resistance
Ceramic
Plastic

6JA

Value

Rating

°C/W
50
68

DC CHARACTERISTICS
= 5.0 Vde ± 5%, Vss = 0

(Vee

Vdc, TA

= ooe

to 70°C unless otherwise noted)
Symbol

Min

Max

Unit

Input High Voltage
All Inputs

V,H

+20

Vee

V

Input Low Voltage
All Inputs

V,L

-0.3

+08

V

Input Leakage Current
R/W, RES, CS

liN

-

10.0

~A

Three-State (Off State) Input Current
IRQ, DO·D7

TTSI

-

10.0

~A

Output High Voltage
RDSR, TDSR, IRQ, DO-D7, DSR, DTR, RTS,
TxD, TxC

VOH

Vss + 2.4

-

V

VOH

Vss + 2.4

-

V

VOL

-

0.5

V

Parameter

BCLK

Output Low Voltage
RDSR, TDSR, IRQ, DO-D7, DSR, DTR, RTS,
TxD, TxC, BCLK

Test Conditions

= 0 to 5.25V
= 5.25V
Y'N = 0 4 to 2.4V
Vee = 525V
Vee = 4.75V
ILOAD = -400 ~A,
CLOAD = 130 pF
Vee = 475V
ILOAD = 0
CLOAD = 30 pF
Vee = 4.75V
ILOAD = 3.2 mA
Y'N
Vee

Vee = 4.75V
ILOAD = 8.8 mA

DONE
Internal Power DIssipation

P,NT

Input Capacitance

C 'N

2-224

-

= 25°C

1

W

TA

13

pF

Y,N = OV
TA = 25°C
f = 1 MHz

R65560

Multi-Protocol Communications Controller (MPCC)

PACKAGE DIMENSIONS
40-PIN CERAMIC DIP

b;
I

~

MILLIMETERS

Jl

DIM

I

-0

J-GI

K

II

~~J
1-

\

Y

INCHES
MIN

MAX

A

5029

5156

1980

2030

B

1473

1549

0580

0610

C

178

305

0070

0120

o

038

056

0015

0023

F

102

1650040

0065

G

229

280

0090

0110

J

020

038

0008

0015

0125

0150

K

WiJI '1111111111 i 1IIIRtjJn
rn
I
~

MIN r-;AX

318

381

L

14991651

M

.. 0'

N

058

10'
178

05900650
0"

0020

10'
0070

M

L

40-PIN PLASTIC DIP

[~~~~:::::::::: ]J

MILLIMETERS

MIN

MAX

MIN

MAX

A

5128

5232

2040

2060

B

1372

1422

0540

0560

C

355

508

0140

0200

o

036

051

0014

0020

F

102

152

0040

0060

G
H

254BSC

o 100 BSC

165

216

J

020

03000080012

K

305_1

356

L

2-225

INCHES

DIM

1524BSC

M

7"

10"

N

051

102

0065

0085

012010140
D60Dese

7"

10"

0020

0040

fJ

R65C02. R65C1 02. R65C112

'1'

Rockwell

R65C02, R65C102, AND R65C112
R65COO MICROPROCESSORS (CPU)

DESCRIPTION

FEATURES

The 8-bit R65COO microprocessor family of devices are produced using CMOS silicon gate technology which provides
advanced system archHecture for performance speed and system
cost-effectiveness enhancements over their NMOS counterparts, the R6500 family of microprocessor devices.

• CMOS silicon gate technology
• Low Power (4mA/MHz)
• Software compatible with R6502
• Single 5V +5% power supply requirements
•
•
•
•
•
•
•
•

Three CPU devices are available. All are software-compatible
and provide 64K bytes of addressable memory, interrupt input,
and on-chip clock oscillators and drivers options. All are buscompatible wHh the NMOS R6500 family devices.
The CMOS family includes two microprocessors (R65C02 and
R65C102) with on-board clock oscillators and drivers and one
microprocessor (R65C112) driven by external clocks. The onchip clock versions are aimed at high performance, low-cost
applications where single phase inputs, crystal or RC inputs
provide the time base. The slave processor version is geared
for multiprocessor system applications where maximum timing
control is mandatory. All R65COO microprocessors are available
in ceramic and plastic packaging, operating frequency of 1 MHz,
2 MHz, 3 MHz and 4 MHz, and commercial and industrial
temperature versions. All three devices are housed in 40-pin
packages.

• "Ready" input
• Direct memory access (DMA) capabilHy
•
•
•
•

Memory lock output
1 MHz, 2 MHz, 3 MHz, and 4 MHz versions
Choice of external or on-Chip clocks
On-chip clock options
-External single clock input
-Direct crystal input (+ 4)
• Commercial and industrial temperature versions

ENHANCEMENTS OVER R6502

• Pipeline archHecture
• Slave processor version (R65C112)

The CMOS family of microprocessor devices has been designed
with many enhancements over the R6502 NMOS device while
maintaining software compatibility. Besides the increased speed
and lower power consumption inherent in CMOS technology,
the R65COO family has added the following characteristics.
•
•
•
•
•

Eight bit parallel processing
Decimal and binary arithmetic
True indexing capability
Programmable stack pointer
Interrupt capabilHy
Non-maskable interrupt
Eight-bit bidirectional data bus
Addressable memory range of up to 64K bytes

ORDERING INFORMATION

I Part Number:

r

R65C02 __ _
R65C102 __ _
R65C112

12 new instructions for a total of 68
59 new op codes, for a total of 210
Two new addressing modes
Seven software/operational enhancements
Two hardware enhancements

T~p.
R.,go (T, to T.
Blank = O°C to + 70°C
E

= -40°C to +85°C

Frequency Range
1
1 MHz
2 MHz
2
3 3 MHz
4 4 MHz

=
=
=
=

Package
C = Ceramic
P = Plastic

Document No. 29651N52
2-226

Product Description Order No. 2149
Rev. 3, October 1984

R65COO Microprocessors (CPU)

R65C02,R65C102,andR65C112
FUNCTIONAL DESCRIPTION
With the exception of a crystal oscillator, clock signals, Memory
Latch (ML), and Bus Enable (BE) signals, the internal architecture of the three members of the R65COO CPU of devices is identical. Figure 1 shows the block diagram of the R65COO CPU

+-----

internal architecture for all three devices. This block diagram
supports the following text that describes the function of each
of the device's major elements.

CONTROL SECfION ~

REGISTER SECfION

RES IRQ NMI

ill

INDEX
REGISTER
Y

INDEX
REGISTER
X
..I

~A
..I

~

INTERRUPT
LOGIC

fJ

I

J

h
C

1 - - - - -....

ML(5)

L...-

....- - - - - R D Y
SYNC

L

STACK
~
POINT
I~
REGISTER(S)

1 - - - - -__

t----t~ XTLO(3)

L---

ffi
!E

Z

Qw

bC
;:)8
IZ: w

-~

r

tic

ALU

~ ~

XTLI(3)

i!!:

C

ACCUM~LATORp

I

tj

TIMING
~CONTROLI

rPCL

r--------,

'- ~
~

INPUT DATA
LATCH (DL)

l

r---

~

PCH

~t-

J

HPROCESSOR
STATUS
REGISTER P

CLOCK
GENERATOR

.--------tt---.

I

f

"......
f':"

L-I

~

Lr-r::.':"':;"~_....J

I. dH,

t1
I

INSTRUCTION
REGISTER

•

.1

~

J.III

1J
1

BE(4)
DO
D1

LEGEND:

L------+-~_+_r~-~D2

L------~_+_r~~-~·D3

L-------_r~t-4>----....

D4

L - - - - - - - - - - H.....----~D5
L--------_+~----~D6
L----~---~~----~m

Figure 1.

R65COO Internal Architecture

2-227

'

I ........ 114 ouTf3)
~ 112 OUT(2)
ou,-tI)

1
DATA BUS
BUFFER

110 IN 112 IN(4)

DATA
BUS

11

t

8 BIT LINE
SINGLE LINE

R65C02, R65C102, and R65C112

R65COO Microprocessors (CPU)
and modifies the address by adding the index register to it prior
to performing the desired operation. Pre- or post-indexing of
indirect addresses is possible (see addressing modes).

CRYSTAL OSCILLATOR (R65C102 Only)
The crystal oscillator, driven by a crystal across XTlO and XTAI,
divides the crystal frequency by four to provide the basic 02
clock signal that drives the internal clock generator.

STACK POINTER
The stack pointer is an 8-bit register used to control the
addressing of the variable-length stack on page one. The stack
pointer is automatically incremented and decremented under
control of the microprocessor to perform stack manipulations
under direction of eHher the program or interrupts (NMI and
IRQ). The stack allows Simple implementation of nested subroutines and multiple level interrupts. The stack pointer should
be initialized before any interrupts or stack operations occur.

CLOCK GENERATOR
The clock generator develops all internal clock signals, and
(where applicable) external clock signals, associated with the
device. It is the clock generator that drives the timing control
unit and the external timing for slave mode operations.

TIMING CONTROL
The timing control unH keeps track of the instruction cycle being
monitored. The unH is set to zero each time an instruction fetch
is executed and is advanced at the beginning of each phase
one clock pulse for as many cycles as is required to complete
the instruction. Each data transfer which takes place between
the registers depends upon decoding the contents of both the
Instruction register and the timing control unit.

PROCESSOR STATUS REGISTER
The 8-bit processor status register contains seven status flags.
Some of the flags are controlled by the program, others may be
controlled both by the program and the CPU. The R65COO
instruction set contains a number of conditional branch instructions which are designed to allow testing of these flags.

HARDWARE ENHANCEMENTS

PROGRAM COUNTER

The R65COO family of CPU devices have incorporated hardware
enhancements over their NMOS counterpart, the R6502. These
hardware enhancements are:

The 16-bit program counter provides the addresses which step
the microprocessor through sequential instructions in a program.

• The NMOS device would ignore the assertion of a Ready
(ROY), during a write operation. The CMOS family will stop
the processor during 02 clock if ROY is asserted during a
write operation.
• On the NMOS device, unused input-only pins (IRQ, NMI,
ROY, RES, and SO) must be connected to a low impedance signal to avoid noise problems. These unused pins on
the CMOS devices are internally connected by a high impedance to Vee (approximately 250K ohms).

Each time the microprocessor fetches an instruction from program memory, the lower byte of the program counter (PCl) is
placed on the low-order bits of the address bus and the higher
byte of the program counter (PCH) is placed on the high-order
8 bits. The counter is incremented each time an instruction or
data is fetched from program memory.

INSTRUCTION REGISTER AND DECODE
Instructions fetched from memory are gated onto the internal
data bus. These instructions are latched into the instruction register, then decoded, along with timing and interrupt signals, to
generate control signals for the various registers.

MAJOR FEATURES AND DIFFERENCES
The functional aspects of and differences between the microprocessor configurations are shown in Table 1.

ARITHMETIC AND LOGIC UNIT (ALU)
All arithmetic and logic operations take place in the AlU including
incrementing and decrementing internal registers (except the
program counter). The AlU has no internal memory and is used
only to perform logical and transient numerical operations.

Table 1.

Family Comparison Chart

. .~
N

Feature

ACCUMULATOR

Pin compatible with NMOS R6502
64K addressable bytes of memory
IRQ interrupt
On-chip clock oscillator
External clock only
TTL level single phase clock input
RC time base clock input
Crystal time base cloc~ input
Single phase clock input
Two phase output clock
SYNC and RDY signals
Bus Enable (BE) signal
Memory Lock (MI.) output signal
Direct Memory Access (DMA) capacity
NMI interrupt signal

The accumulator is a general purpose 8-bit register that stores
the results of most arithmetic and logic operations, and in
addition, the accumulator usually contains one of the two data
words used in these operations.

INDEX REGISTERS
There are two 8-bit index registers (X and y), which may be
used to count program steps or to provide an index value to be
used in generating an effective aqdress.
When executing an instruction which specifies indexed
addressing, the CPU fetches the op code and the base address,

2-228

N

i

a::

X
X
X
X

X
X
X

X
X
X

X
X
X

X
X

X
X
X
X
X
X

~

~
a::
X
X
X

X

X

X
X
X
X
X

R65COO Microprocessors (CPU)

R65C02, R65C102, and R65C112
PIN ASSIGNMENTS
Figure 2 shows the pin assignments for the three members of
the R65COO CPU family. All three devices are housed in 4O-pin,
dual-in-line, ceramic or plastic packages.

R65C102

R65C02

VSS
ROY
• 1 (OUT)
IRQ
N.C.
NMI
SYNC
VCC

RES
'2 (OUT)
SO
'0 (IN)
N.C.
N.C.
R/W
DO

ilL

AD
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11

01
02
03
04
05
06
07
A1S
A14
A13
A12

AD
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11

VSS

VSS
ROY
'4 (OUT)
IRQ

R65C112

RES
'2 (OUT)
SO
XTLI
BE
XTLO
R/W
DO

NMI
SYNC
VCC

01
02
03
04
05
06
07
A1S
A14
A13
A12

VSS

VSS
ROY
N.C .
IRQ
ML
NMI
SYNC
VCC

RES
N.C.
SO
'2 (IN)
BE
N.C.
R/W
DO

AD
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11

01
02
03
04
05
06
07
A15
A14
A13
A12

VSS

Note N C means no connection (not used)

Figure 2.

Pin Assianments

SIGNAL DESCRIPTIONS

CLOCK SIGNALS (R65C112)

Reference the timing diagrams (Figures 3, 4 and 5) for the particular device in the following discussion.

All internal clock signals for the R65C112 are generated by the
input clock signal 02 (IN). Since this device is intended to be
operated in the slave mode it does not have internal clock
generation, but rather requires the external clock 02 (IN) from
a host device. Figure 7 shows an example of a clock circuit for
the R65C112 configured for slave mode.

CLOCK SIGNALS (R65C02)
The R65C02 requires an external 00 clock. See Figure 6 for an
example clock circuit. 00 is a TTL level input that is used to
generate the internal clocks of the R65C02. Two full level output clocks are generated by the R65C02. The 02 clock is in
phase with 00. The 01 clock output is 180 0 out of phase with
00. When the input clock is stopped, the CPU is in the standby
mode. See Figure 8 for special standby mode considerations.

ADDRESS BUS (AO-A 15)
AO-A 15 forms a 16-bit address bus for memory and I/O
exchanges on the data bus. The output of each address line is
TTL compatible, capable of driving one standard TTL load and
130pF.

DATA BUS (00-07)

For non-critical timing configurations, a simple RC or crystal
network may be strapped between 00 (IN) and 01 (OUT).

The data lines (DO-D7) constitute an 8-bit bidirectional data bus
used for data exchanges to and from the device and peripherals.
The outputs are tri-state buffers capable of driving one TTL load
and 130pF.

CLOCK SIGNALS (R65C102)
The R65C102 internal clocks may be generated by a TTL level
single phase input, an RC time base input, or a crystal time base
input (~ 4) using the XTLO and XTLI input pins. See Figure 7
for an example of a crystal time base circuit. Two full level output clocks are generated by the R65C102. The 02 clock output
provides timing for external RIW operations. Addresses are
valid after the address setup time (tADS) referenced to the failing edge of 01 (OUT). The 04 output is a quadrature output clock
that is delayed from the falling edge of the 02 clock by delay
time tAVS. Using the 04 clock, addresses are valid at the rising
edge of 04.

BUS ENABLE (BE)
This signal allows external control of the data and the address
output buffers and R/W. For normal operation, BE
is high causing the address buffers and RtW to be active
and the data buffers to be active during a write cycle. For external control, BE is held low to disable the buffers. BE is an asynchronous signal and therefore not related to, or controlled by
the CPU internal clock signals. Figure 5 shows timing relationships of BE to RtW and address output buffers.
2-229

fJ

R65C02, R65C102, and R65C112

R65COO Microprocessors (CPU)
02 in which the ready signal is low. This feature allows microprocessor interfacing with low-speed memory as well as direct
memory access (DMA).

INTERRUPT REQUEST (IRQ)
This TTL compatible input requests that an interrupt sequence
begin within the microprocessor. The IRQ is sampled during 02
operation; if the interrupt flag in the processor status register is
zero, the current instruction is completed and the interrupt
sequence begins during 01 . The program counter and processor
status register are stored in the stack. The microprocessor will
then set the interrupt mask flag high so that no further IRQs may
occur. At the end of this cycle, the program counter low byte will
be loaded from address FFFE, and program counter high byte
from location FFFF, thus transferring program control to the
memory vector located at these addresses. The RDY signal
must be in the high state for any interrupt to be recognized. A
3K ohm external resistor should be used for proper wire OR
operation.

READ/WRITE (Rm)
This signal is normally in the high state indicating that the
microprocessor is reading data from memory or 1/0 bus. In the
low state the data bus has valid data from the microprocessor
to be stored at the addressed memory location.

SET OVERFLOW (SO)
A negative transition on this line sets the overflow bit (V) in the
processor status register. The signal is sampled prior to the
leading edge of 02 by the processor control time (tsos).

RESET (RES)
This input resets the microprocessor. Reset must be held low
for at least two clock cycles after V cc reaches operating voltage
from a power down. A positive transistion on this pin will then
cause an initialization sequence to begin. Likewise, after the
system has been operating, a low on this line of at least two
cycles will cease microprocessing activity, followed by initialization after the positive edge on RES.

MEMORY LOCK (ML)
In a multiprocessor system, the ML output indicates the need
to defer the rearbitration of the next bus cycle to ensure the
integrity of read-modify-write instructions. ML goes low during
ASL, DEC, INC, LSR, ROL, ROR, TRB, TSB memory referencing instructions. This signal is low for the modify and write
cycles.

When a positive edge is detected, there is an initialization
sequence lasting six clock cycles. Then the interrupt mask flag
is set, the decimal mode is cleared, and the program counter
is loaded with the restart vector from locations FFFC (lOW byte)
and FFFD (high by1e). This is the start location for program control. This input should be high in normal operation.

NON-MASKABLE INTERRUPT (NMI)
A negative-going edge on this input requests that a non-maskable interrupt sequence be generated within the microprocessor. The NMI is sampled during 02; the current instruction
is completed and the interrupt sequence begins during 01. The
program counter is loaded with the interrupt vector from locations FFFA (low by1e) and FFFB (high by1e), thereby transferring
program control to the non-maskable interrupt routine.

SYNCHRONIZE (SYNC)
ThiS output line identifies those cycles during which the microprocessor is fetching the instruction operation code (OP CODE).
The SYNC line goes high during 01 of an OP CODE fetch and
stays high for the remainder of that cycle. If the RDY line is
pulled low during the 01 clock pulse in which SYNC went high,
the processor will stop in its current state and will remain in the
state until the RDY line goes high. In this manner, the SYNC
signal can be used to control RDY to cause single instruction
execution.

NOTE
Since this interrupt is non-maskable, another NMI can
occur before the first is finished. Care should be taken
when using NMI to avoid this.

READY (ROY)
This input allows the user to single-cycle the microprocessor on
all cycles including write cycles. A negative transition to the low
state, during or coincident with 01, will halt the microprocessor
with the output address lines reflecting the current address
being fetched. This condition will remain through a subsequent
Table 2.
Function

OPERATIONAL ENHANCEMENTS
Table 2 lists the operational enhancements that have been
added to the CMOS family of CPU devices and compares the
results with their NMOS R6502 counterpart.

CMOS Operational Enhancements
NMOS R6502 Microprocessor

CMOS R65COO Family Microprocessor

Indexed addressing across page boundary.

Extra read of invalid address.

Extra read of last instruction byte.

Execution of invalid op codes.

Some terminate only by reset. Results are
undefined.

All are NOPs (reserved for future use).

Jump indirect, operand = XXFF.

Page address does not increment.

Page address increments and adds one additional cycle.

Read/modify/write instructions at effective
address.

One read and two write cycles.

Two read and one write cycle.

Decimal flag.

Indeterminate after reset.

Initialized to binary mode (0=0) after reset
and interrupts.

Flags after decimal operation.

Invalid N, V and Z flags.

Valid flag adds one additional cycle.

Interrupt after fetch of BRK instruction.

Interrupt vector is loaded, BRK vector is
ignored.

BRK is executed, then interrupt is executed.

2-230

R65C02, R65C102, and R65C112

R65COO Microprocessors (CPU)

ADDRESSING MODES

INDEXED ABSOLUTE INDIRECT [(ABS, X)]'
The contents of the second and third instruction bytes are added
to the X-register. The sixteen-bit result is a memory address containing the effective address. (JMP (ABS, X) only).

The R65COO CPU family has 15 addressing modes (two more
than the NMOS equivalent family). In the following discussion
of these addressing modes, a bracketed expression follows the
title of the mode. This expression is the term used in the Instruction Set Op Code Matrix table (later in this product description)
to make it easier to identify the actual addressing mode used
by the instruction.

IMPLIED ADDRESSING [lmplied]-In the implied addressing
mode, the address containing the operand is implicitly stated in
the operation code of the instruction.
RELATIVE ADDRESSING [Relative]-Relative addressing is
used only with branch instructions and establishes a destination
for the conditional branch.

ACCUMULATOR ADDRESSING [Accum]-This form of addressing is represented with a one byte instruction, implying an
operation on the accumulator.

The second byte of the instruction becomes the operand which
is an "Offset" added to the contents of the lower eight bits of
the program counter when the counter is set at the next instruction. The range of the offset is -128 to +127 bytes from the
next instruction.

IMMEDIATE ADDRESSING [lMM]-ln immediate addressing,
the second byte of the instruction contains the operand, with no
further memory addressing required.
ABSOLUTE ADDRESSING [ABS]-In absolute addressing, the
second byte of the instruction specifies the eight low order bits
of the effective address while the third byte specifies the eight
high order bits. Thus the absolute addressing mode allows
access to the entire 64K bytes of addressable memory.

ZERO PAGE RELATIVE ADDRESSING [ZP REL)'-This mode
bit tests the zero page location specified for bit set/reset per the
mask and performs a conditional relative branch based on the
results of the bit test.
INDEXED INDIRECT ADDRESSING [(IND, X)]-In indexed
indirect addressing (referred to as (Indirect, X)), the second byte
of the instruction is added to the contents of the X index register,
discarding the carry. The result of this addition points to a
memory location on page zero whose contents are the low order
eight bits of the effective address. The next memory location in
page zero contains the high order eight bits of the effective
address. Both memory locations specifying the high and low
order bytes of the effective address must be in page zero.

ZERO PAGE ADDRESSING [ZP]-The zero page instructions
allow for shorter code and execution times by fetching only the
second byte of the instruction and assuming a zero high address
byte. Careful use of the zero page can result in significant
increase in code efficiency.
ZERO PAGE INDEXED ADDRESSING [ZP, X or Y]-(X, Y
indexing)-This form of addressing is used with the index register and is referred to as "Zero Page, X" or "Zero Page, Y".
The effective address is calculated by adding the second byte
to the contents of the index register. Since this is a form of "Zero
Page" addressing, the content of the second byte references
a location in page zero. Additionally, due to the "Zero Page"
addressing nature of this mode, no carry is added to the high
order eight bits of memory and crossing of page boundaries
does not occur.

INDIRECT INDEXED ADDRESSING [(IND), Y]-In indirect
indexed addressing (referred to as (Indirect), V), the second
byte of the instruction points to a memory location in page zero.
The contents of this memory location are added to the contents
of the Y index register, the result being the low order eight bits
of the effective address. The carry from this addition is added
to the contents of the next page zero memory location, the result
being the high order eight bits of the effective address.
ABSOLUTE INDIRECT [(ABS)]-The second byte of the instruction contains the low order eight bits of a memory location. The
high order eight bits of that memory location are contained in
the third byte of the instruction. The contents of the fully specified
memory location are the low order byte of the effective address.
The next memory location contains the high order byte of the
effective address which is loaded into the sixteen bits of the
program counter. (JMP (ABS) only.)

ABSOLUTE INDEXED ADDRESSING [ABS, X or Y]-(X, Y
indexing)-This form of addressing is used in conjunction with
X and Y index register and is referred to as "Absolute, X" and
"Absolute, Y". The effective address is formed by adging the
contents of X or Y to the address contained in the second and
third bytes of the instruction. This mode allows the index register
to contain the index or count value and the instruction to contain
the base address. This type of indexing allows any location referencing and the index to modify multiple fields, resulting in
reduced coding and execution time.

INDIRECT [(IND)]*-The second byte of the instruction contains a zero page address serving as the indirect pointer.
NOTE

"These addressing modes are not available to the NMOS CPU
family (e.g., the R6502).

2-231

R65C02, R65C102, and R65C112

R65COO Microprocessors (CPU)

INSTRUCTION SET
Table 3 lists the instruction set for the CMOS CPU family in
alphabetic order according to mnemonic. Table 4 lists the hexadecimal codes for each of the instructions that are new to the
CMOS family and were not available in thE! NMOS R6502 device

Table 3.
Mnemonic
(2)
(2)

family. Table 5 lists those instructions that were available on the
NMOS family, but have been assigned new addressing modes
in the CMOS CPU family.

Alphabetic Listing of Instruction Set
Mnemonic

Function

ADC
AND
ASL

Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)

BBR
BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRA
BRK
BVC
BVS

Branch on Bit Reset
Branch on Bit Set
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Branch Always
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC
CLD
CLI
CLV
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

(2)

EaR

"Exclusive-OR" Memory with Accumulator

(2)

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Index Y by One

(2)

JMP
JSR

Jump to New Location
Jump to New Location Saving Return Address

(2)

LOA
LOX
LOY
LSR

Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)

(1)
(1)

(2)

(1)

(2)

(2)

(2)

(1)
(1)

(1)
(1)
(1)

(1)
(2)

(1)

(1)
(1)

NOP

No Operation

ORA

"OR" Memory with Accumlator

PHA
PHP
PHX
PHY
PLA
PLP
PLX
PLY

Push Accumulator on Stack
Push Processor Status on Stack
Push X Register on Stack
Push Y Register on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
Pull X Register from Stack
Pull Y Register from Stack

RMB
ROL
ROR
RTI
RTS

Reset Memory Bit
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine

SBC
SEC
SED
SEI
5MB
STA
STX
STY
STZ

Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Store Zero

TAX
TAY
TRB
TSB
TSX
TXA
TXS
TYA

Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Test and Reset Bits
Test and Set Bits
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator

Notes:
(1) Instruction not available on the NMOS family.
(2) R6502 instruction with additional addressing mode(s).

2-232

Function

R65C02, R65C102, and R65C112

Table 4.
Hex

80
3A
1A
OA
SA
FA
7A
9C
9E
64
74
1C
14
OC
04
89
OF·7Ft"
8F·FF'1l
07-"77'''
87·F7'"

R65COO Microprocessors (CPU)

Hexadecimal Codes For New Instructions In The CMOS Family
Mnemonic

Description
Branch relative always [Relative)
Oscrement accumulator [Accum)
Increment accumulator [Accum)
Push X on stack [Implied]
Push Y on stack [Implied)
Pull X from stack [Implied)
Pull Y from stack [Implied]
Store zero [Absolute]
Store zero [ABS, Xl
Store zero [ZP)
Store zero [ZP, Xl
Test and reset memory bits with accumulator [ABS)
Test and reset memory bits with accumulator [ZP)
Test and set memory bits with accumulator [ABS)
Test and set memory bits with accumulator [ZP)
Test Immediate with accumulator [IMM)
Branch on bit reset [Bit Manipulation, Zp, RELJ
Branch on bit set [Bit Manipulation, Zp, REL]
Reset memory bit [Bit Manipulation, ZP)
Set memory bit [Bit Manipulation, ZP)

BRA
DEC
INC
PHX
PHY
PLX
PLY
STZ
STZ
STZ
STZ
TRB
TRB
TSB
TSB
BIT
BBR
BBS
RMB
5MB

Note:
1. Most significant digit change only.

Table 5. Hexadecimal Codes For Instructions With New CMOS Addressing Modes
Hex

Mnemonic

Description

72
32
3C
34
02
52
7C
B2
12
F2
92

AOC
AND
BIT
BIT
CMP
EOR
JMP
LOA
ORA
SBC
STA

Add memory to accumulator with carry [(INO»)
AND memory with accumulator [(I NO»)
Test memory bits with accumulator [ABS, X)
Test memory bits with accumulator [ZP, X)
Compare memory and accumulator [(INO»
Exclusive Or memory with accumulator [(IN D»)
Jump (New addressing mode) [(ABS, X»)
Load accumulator with memory [(INO»
OR memory with accumulator [(INO»
Subtract Memory from accumulator with borrow [(INO»)
Store accumulator in memory [(INO»)

2·233

fJ

R65C02, R65C102, and R65C112

R65COO Microprocessors (CPU)

INSTRUCTION SET OP CODE MATRIX
The following matrix shows the 210 Op Codes associated with
the R65COO family of CPU devices, The matrix identifies the
hexadecimal code, the mnemonic code, the addressing mode,

o

'"

LSD 0

::E

o

C

o

E

F

TSB
ABS
3 6

ORA
ABS
3 4

ASL
ABS
3 6

BBRO
ZP
3 5"

INC
Accum
2

TRB
ABS
3 6

ORA
ABS, X
3 4'

ASL
ABS, X
3 7

3

AND
IMM
2 2

ROL
Accum
2

BIT
ABS
3 4

AND
ABS
3 4

ROL
ABS
3 6

3

SEC
Implied
2

AND
ABS,Y
3 4'

DEC
Aceum
2

BIT
ABS,X
3 4'

AND
ABS,X
3 4'

ROL
ABS,X
3 7

BBR3
ZP
3 5"

RMB4
ZP
2 5

PHA
Implied
3

EOR
IMM
2 2

LSR
Accum
2'

JMP
ABS
3 3

EOR
ABS
3 4

LSR
ABS
3 6

BBR4
ZP

LSR
Zp, X
2 6

RMBS
ZP
2 5

CLI
Implied
2

EOR
ABS, Y
3 4'

PHY
Implied
3

ADC
ZP
2 3t

ROR
ZP
2 5

RMB6
ZP
2 5

PLA
Implied
4

ADC
IMM
2 2t

ROR
Accum
2

JMP
(ABS)
3 6

AOC
ABS
3 4t

ROR
ABS
3 6

STZ
ZP, X
2 4

ADC
ZP, X
2 4t

ROR
Zp, X
2 6

RMB7
ZP

2 5

SEI
Implied
2

AOC
ABS,Y
3 4't

PLY
Implied
1 4

JMP
ABS,X
3 6

AOC
ABS,X
3 4't

ROR
ABS, X
3 7

BBR7
ZP
3 5"

STY
ZP
2 3

STA
ZP
2 3

STX
ZP
2 3

5MBO
ZP
2 5

DEY
Imphed
2

BIT
IMM
2 2

TXA
Imphed
2

STY
ABS
3 4

STA
ABS
3 4

STX
ABS
3 4

BBSO
ZP
3 5"

STA
(INO)
2 5

STY
Zp, X
2 4

STA
Zp, X
2 4

STX
Zp, Y
2 4

5MB'
ZP
2 5

TYA
Implied
2

STA
ABS, Y
3 5

TXS
Implied

STZ
ABS
3 4

LOX
IMM
2 2

LOY
ZP
2 3

LOA
ZP
2 3

LOX
ZP
2 3

5MB2
ZP

TAY
Implied

LOA
IMM

2 2

TAX
Implied
1 2

LOA
(INO)
2 5

LOY
ZP, X
2 4

LOA
ZP, X
2 4

LOX
ZP, Y
2 4

5MB3
ZP

LOA
ABS, Y
3 4'

TSX
Implied
2

CPY
ZP
2 3

CMP
ZP
2 3

DEC
ZP

5MB4
ZP
2 5

INY
Implied

CMP
IMM
2 2

OEX
Implied

CMP
ZP, X
2 4

DEC
Zp, X
2 6

5MB5
ZP

CLD
Implied
2

CMP
ABS,Y
3 4'

PHX
Implied
3

SBC
ZP
3t

INC
ZP
2 5

5MB6
ZP
2 5

INX
Implied

SBC
IMM

2

2 2t

NOP
Implied
1 2

SBC
ZP, X
2 4t

INC
ZP, X
2 6

5MB7
ZP
2 5

SED
Implied
1 2

SBC
ABS, Y
3 4't

PLX
Implied
4

9

A

BRK
ORA
Implied (IND,X)
7
2 6

TSB
ZP
2 5

ORA
ZP
2 3

ASL
ZP
2 5

RMBO
ZP
2 5

PHP
Implied
3

ORA
IMM
2 2

ASL

Accum

BPL
ORA
Relative (IND), Y
2 5'
2 2"

TRB
ZP
2 5

ORA
ZP,
2 4

ASL
ZP,
2 6

RMB'
ZP
2 5

CLC
Implied
2

ORA
ABS, Y
3 4'

BIT
ZP
2 3

AND
ZP
2 3

ROL
ZP
2 5

RMB2
ZP
2 5

PLP
Implied
4

BIT
ZP, X
2 4

AND
ZP, X
2 4

ROL
Zp, X
2 6

RMB3
ZP
2 5

EOR
ZP
2 3

LSR
ZP
2 5

EOR
ZP, X
2 4
STZ
ZP
2 3

6

2

,

JSR
ABS
3 6

ORA
(INO)
2 5

AND
(IND, X)
2 6

BMI
AND
Relative (INO), Y
2 2"
2 5'

AND
(INO)
2 5

x

RTI
EOR
Implied (INO,X)
6
2 6

,

BVC
EOR
Relative (INO), Y
2 2"
2 5'
6

RTS
Implied
6

,

EOR
(INO)
2 5

AOC
(INO, X)
2 6t

BVS

AOC
Relative (INO), Y
2 2"
2 S't

AOC
(INO)
2 St

BRA
STA
Relative (INO, X)
2 3'
2 6
BCC
STA
Relative (INO), Y
2 2"
2 6

A

LOY
IMM

2 2
B

C

o
E

LOA
(IND, X)
2 6

BCS
LOA
Relattve (INO), Y
2 2"
2 5'
CPY
IMM
2 2

CMP
(IND, X)

2 6

CMP
BNE
Relative (INO), Y
2 2"
2 5'
CPX
IMM

2 2
F

the number of instruction bytes, and the number of machine
cycles associated with each Op Code, Also, refer to the instruc·
tion set summary for additional information on these Op Codes,

CMP
(INO)
2 5

SBC
(IND, X)
2 6t

BEQ
SBC
Relative (IND), Y
2 2"
2 5't

CPX
ZP

2 3
SBC
(INO)
2 St

x

2 5

,
,

,
,

,
,
,

,

,

,

,

2 5

2

CLV

,

Implied

5

2 5

2

,

2

2

,
,

2

D-

New Opcode

2

,

,
,
,

o
BRK

Implied
1 7

-op Code
- Addressing Mode
-Instruction Bytes, Machine Cycles

2·234

LSR
EOR
ABS, X ABS, X
3 4'
3 7

,

,
,

,

2

LOY
ABS
3 4

,

STZ
STA
ABS, X ABS,X
3 5
3 5
LOA
ABS
3 4

LOY
LOA
ABS, X ABS, X
3 4'
3 4'

,

CPY
ABS
3 4

2

CMP
ABS
3 4

CPX
ABS
3 4

,

B

tAdd 1 to
'Add , to
"Add' to
Add 2 to

C

BBR'
ZP
5"
BBR2
ZP

5"

4

3 5"
BBRS
ZP
3 5"
BBR6
ZP
3

5"
7

BBS'
ZP
3

5"

LOX
ABS
3 4

BBS2
ZP
3 5"

A

LOX
ABS,Y
3 4'

BBS3
ZP
3 5"

B

DEC
ABS
3 6

BBS4
ZP
3 5"

C

BBS5
ZP
3 5"

o

BBSS
ZP
5"

E

CMP
DEC
ABS, X ABS,X
3 7
3 4'

,

A

4

o

,

B

SBC
ABS
3 4t

INC
ABS
3 6

3

SBC
ABS, X
3 4't

INC
ABS,X
3 7

3

o

E

BBS7
ZP

5"
F

N if In deCimal mode,
N If page boundary IS crossed.
N If branch occurs to same page,
N If branch occurs to different page.

F

PROCESSOR STATUS

ADDRESSING MODES
MNEMONIC

ADC
AND
ASl

C-

BBA ['(M)[

Branch on M, '" ~

BBS ['(~~711
BCC
8CS
BEQ
BIT
BMI
BNE
BPL
BAA
BRK
BVC
BVS
CLC
CLD
CLI
CLV
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
INX
INY
JMP
JSA
LDA
LDX
LDY

~

c.>
C11

OPERATION

I

LSR
NOP
ORA
PHA
PHP
PHX
PHY
PLA
PLP
PLX
PLY

A+M+C-A(1) (5) (7)
(,)

A M-A

OP n

/I

69 2
29 2

2 6D 4
2 2D 4
mE 6

-~

rr=JJ

P "

•

p" • lop

3 65 3
3 25 3
3 ~6 S

lABS, X) I AaS, Y I REIATIV£ I

"J

D 4

C9 2

2

E0 2
2

~ ~~
CE

C~

V

•

0

I

Z

C

z

C

Z

,

Z

C

49 2

:
6

2 40 4

EE 6

N
N

¢~ JI I I I I I I"IT1
,B
DB
5B
BB

3 cs
3 E4
3 C4
3 C6

2
2
2
2

M,

D.
3~

3
l13

A9 2
A2 2
A¢ 2

'8

2 01

5

2 05 4

D6 6

0914

I3

N

0215 12

2 DDIT

N
N

2 DE 7

N
N

3

4'

2

6

51

5

591413

2 55
F6

-C

No OperatIOn
(,)
AVM-A
A-Ms 8-1-8
P-Ms 8-1-8
X-Ms 8-1-8
Y-Ms 8-1-8
5+1-5 Ms-A
5+1-5 Ms-P
5+1-5 Ms-X
8+1-5 Ms-Y

AMB[.(m~7)1

0-M"

AOL
ROA
RTI
ATS
SBC
SEC
SED
SEI

~"'5f;

5MB['(l!~7))

1-Mb

STA
STX
STY
STZ
TAX
TAY
TAB
TS8
TSX
TXA
TXS
TYA

A-M
X-M
Y-M
'-M
A-X
A-Y

~9

2

3 A6
3 A4
3 46

2 ¢D 4

3

Tr

es[

~~
2E 6
6E 6

5

2 85 4

2 ED 4

21' 1m,
4B 3 ,

6

2 11

S

2

5

2

3 26 5

2
2

3 E5 3

BD
BE
BC
9C

4
4
4
4

3
3
3
3

2AI21'

6A 2

1

,C 6
6

......

0

en

,!')

s::
s::
»
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I»
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Q.

::rJ
0)

U'I
(')

6CIGI3
B9
BE

82 5

1914 13

121 5 I 2

2

B61412

2101413

N
N

2

36 6
76 6
E,

6

2 F1

III

5 I 2

B5
B6
B4
64

(Restored)

N
N

I
6
B, 1
'AA
AB

~C

::rJ

0)

U'I
(')

C

15 4

5

2 F5

3B
FB
7B

~~-I

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~B

3 66 5

(4)

,!')

-t

N

B4
56

4m
6.
E9 2

0

......

N
N

2 Bl

4AI 2 I 1 lEA

Rtrn Int
Rtrn Sub

A-M C-A (,) (3) (5)
'-C
,-D
,-I

U'I
(')

......

N
N

521512

DA
5A
6B
2B
FA
7A

(4)

C
C

N

A, 6

3 [2

i:;

::rJ

0)

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c:

c:

7~

7el6 I 3

4C 3
20 6
2 AD
2 AE 4
2 AC 4
4E 6

-t

m
-t

i
6

3AI21,

lAI 2 j 1

M~

B~

,
C,

3 45
3 E6

en

z
en

58

EB
CB

11)

B

N V

~~l ~

CA 2
BB 2

AlJM-A

S-X
X-A
X-S
Y-A

,pi " [ • IoPI " I • IoPI " I. Iopi " I. loPl" I • I N

F~

(2)
(2)

M+1-M or A+l-A
X+1-X
Y+l-Y
Jump to New Lac (8)
Jump 8ub
(,)
M-A
(,)
M-X

lir.f\M-M
AV M-M

1 0

B8
IB91 2 I 2 [2C [ 4 [ 3 [24[ 3 [ 2

~-I

rr::=:1l

2

S

~-C

M-Y
m-

3

liND)

9~

(2)
(2)
(2)
(2)

M-1-M or A-1-A
X-1-X
Y-1-Y

5 •

~I:I

(2)
(2)
(2)

(,)

6

~~l :

~-D

0-V
A-M
X-M
Y-M

Iz, PAGE, YI 7

~I

Branch on M" '" 1
Branch on C "" 11
Branch on C '" 1
Branch on Z", 1
A>M (6)
Branch on N '" 1
Branch on Z '" II!
Branch on N '" ~
Branch Always
Break
Branch on V '" II!
Branch on V '" 1

Z

CODES

IMMEDIATE AISIIlUTE ZERO PAGEl ZP REl

2
1

4

2 3E
2 7E 7

N
N

T

2 FD 4

3

3

F914 13

H I;Ii I:
6121;;

C
C
(Restored)

9915 I 3

N

F2! 5 12

C
,

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0)

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(')

o

o
3:

921512

.
.
8
.

n"

961412

1::1 :

Z

Z
Z

3 '4
3 04

Z
Z

BA
BA
9A
9B

Z

o

"'C

CD
CD

Notes:

LEGEND

1 Add 1 to N 'f page boundary IS crossed
2 Add 1 to N If branch occurs to same page
Add 2 to N If branch occurs to different page
3 Carry not (C) "" Borrow
4 Effects 8·bIt data field of the specified zero page address
5 Add 1 to N If 10 DecImal Mode
6 On the Bit Immediate instructIOn, the results of the M7 and Me bits (N and V flags) are indeterminate and should be considered invalid
7 If In DeCImal Mode. Z flag IS Invalid Accumulator must be checked for zero result
8 JMP (OP Code 6C) IS an Absolute Indirect Addressing Mode (ASS)

X

=

Y

=

A

=
=
=

M

Ms
Mt>
M,

=
~

M,

Index X
Index Y
Accumulator
Memory per effectIVe address
Memory per stack pointer
Selecter zero page memory bit
Memory Brt 7

~

A
V

¥
n
If

~
~

Memory Brt 6
Add

~

Subtract

~ And
~

Or
= ExcluSIVe Of
= Number of cycles
~

Number of Bytes

~

CD

'0
"U

c:

R65COO Microprocessors (CPU)

R65C02, R65C102, and R65C112
AC CHARACTERISTICS
Parameter
CLOCK TIMING
02 Cycle Time

tevc

1000

Note 1

500

Note 1

333

Note 1

250

Note 1

ns

02 Low Pulse Width

tCl

430

5000

210

5000

150

5000

100

5000

ns

02 High Pulse Width

tCH

450

-

220

-

00 Low to 02 Low Skew(2)

t OLY

-

50

-

50

02 Low to 01 High Skew(3)

t OlY1

-20

20

-20

20

XTLI High to 02 Low(4)

tOXI

100

-

XTLO Low to 02 Low(4)

t oxo

-

75

02 Low to 04 High Delay4)

t AVS

250

-

04 Low Pulse Width(4)

t~4l

430

04 High Pulse Width(4)

t~4H

450

Clock Rise and Fall Times

t A, tF

-

25

-

20

-

15

RfW Setup Time

tAWS

-

125

-

100

-

RfW Hold Time

tHAW

15

-

15

-

15

Address Setup Time

tAOS

-

125

-

100

Address Valid to 04 High(4)

tM4

100

25

Address Hold Time

tHA

15

Read Access Time

tACC

775

Read Data Setup Time

tosu

100

Read Data Hold Time

tHA

10

-

-

Write Data Delay Time(2)

twos

Write Data Delay Time(4)

toow

-

200

Write Data Delay Time(6)

tOO12

-

tHW

5000

-

110

-

ns

40

-

30

ns

-20

20

-20

20

ns

100

-

100

100

ns

-

75

-

75

-

75

ns

125

-

65

ns

210
220

5000

160

85
150
160

5000

100
110

-

ns

5000

ns

-

12

ns

75

-

60

ns

-

15

-

ns

-

85

-

70

ns

10

-

0

-

ns

15

ns

160

-

30

-

ns

10

-

ns

55

ns

READIWRITE TIMING

Write Data Hold Time

>

15
340
60
10

215
40
10

ns

85

-

55

ns

235

-

170

-

120

ns

30

-

30

-

30

-

ns

450

-

30

-

200

15

110
110

85

CONTROL LINE TIMING
SYNC Delay

tSYS

-

125

-

100

-

85

-

70

ns

ROY Setup Time

tAOS

200

-

110

80

-

60

tsos

75

-

50

40

-

30

-

ns

SO Setup Time

-

ML Delay Time(5)

t MLS

-

125

-

100

-

75

-

60

ns

ML Hold Time(4)

tMLH

10

ns

15

15

-

-

15

-

10

tMLH

-

10

ML Hold Time(6)

15

-

ns

BE Delay Tlme(5)!9)

tBe

-

40

-

40

IRQ, RES Setup Time

tiS

200

110

NMI Setup Time

tNMI

300

-

-

10

200

40
80
170

-

60
150

ns

40

ns

-

ns
ns

Notes:
1. R65C02 and R65Cl02 minimum operating frequency is limited by 02 low pulse width. All processors can be stopped with 02 held high.
2. R65C02 only.
3. R65C02 and R65Cl02 only.
4. R65Cl02 only.
5. R65C102 and R65Cl12 only.
6. R65Cl12 only.
7. Voltage levels shown are V l "" O.4V and VH 2: 2.4V unless otherwise stated.
8. Measurement points shown are 0.8V (low) and 2.0V (high) for inputs and 1.5V (low and high) for outputs, unless otherwise specified.
9. BE signal IS asynchronous.

2-236

R65COO Microprocessors (CPU)

R65C02, R65C102,and R65C112

J

I_Rj~c : - - - - - - - I F - : : : l - t =_ _ _ __

~IDLY

$0 (IN)1 - - - - ,,_ _ _ _ _ _

$1 (OUT)1

.2.2

(OUT)l
(IN)2

AO-A1S, RJW
SYNC

dlt----\I-- IDLY1

I
I+-IR

--II--~

IcH

lea.

-

I - lADS

1

READ

l

(R/W =

WRITE (R/W

lACe

=

HIGH)
LOW)

IDSU_

DO-D7
(READ)

I-lwDS

DO-D7
(WRITE)

-

~ IyLS

IHRW

)(

1--1_

-- -IHML

("

)l

-

RDY ACTIVE
RDY, IRQ
NMI, RES

r-IttA,

I-- -~R

-

\

10012

.-

IRQ, NMI, RES ACTIVE

-Its

----

1+ INMI

=1tc-----: . - lsos

NOTES:
1. R65C02
2. R65C112
3. ALL TIMING IS REFERENCED FROM A HIGH VOLTAGE OF 2.4 VOLTS AND A LOW OF 0.5 VOLTS

Figure 3. Timing Diagram for the R65C02 and R65C112

2-237

I-~DS

fI

R65C02, R65C102, and R65C112

R65COO Microprocessors (CPU)

XTLI (IN)

-1

-IDXI

XTLO (OUn

-1

!+-Ioxo

• ....

ICl

.2 (OUT)

.4 (OUT)

--

1\1-

I _
R

I--IF
I - - - IAVS

--

DO-D7
(READ)

--

-

1'4H

-

.L

ICH

\

= HIGH)
WRITE (RIW = LOW)

1'-D(

tHAW' tHA - - .

RJW,

SYNC,
AO-A15, ML'

-IA'4

-

READ (RIW

lAce
-IHR

losu - +

-

DO-07
(WRITE)

i--

IHW-

IDOW
Isos_

\

--Ils_

RDY ACTIVE
RDY, IRQ,
NMI, RES

J

IRQ, NMI AND RES ACTIVE

INMIIROS -

++-

NOTE: ALL TIMING IS REFERENCED FROM A HIGH VOLTAGE OF 2.4 VOLTS AND A LOW OF 0.5 VOLTS

Figure 4. Timing Diagram for the R65C102

AO·A15

TRI·STATE

R/Vii

BE

v

\

NOTE: BUS ENABLE APPLIES TO THE R65C102 AND R65C112. BE IS ASYNCHRONOUS AND THEREFORE NOT DIRECTLY
RELATED TO THE 02 CLOCK.

Figure 5.

Timing Diagram for Bus Enable (BE)

2·238

R65C02, R65C102, and R65C112

R65COO Microprocessors (CPU)
Table 6. Typical R65C102/R65C112 Master/Slave
Clock Circuit Component Values

CLOCK/CRYSTAL CONSIDERATIONS
A crystal controlled time base generator circuit should be used
to drive 00 (IN) (R65C02) or the XTU and XTLO (R65C102)
inputs.
Figure 6 shows a time base generation scheme, for a 4 MHz
operation of the R65C02, that has been tested and proven
reliable for normal environments.
Figure 7 shows a possible external clock scheme for a R65C102
and R65C112 master/slave configuration. Table 6 identifies the
typical values for external capacitors at various crystal
frequencies.

C1N
(pF)

COUT
(pF)

,2
FREQ
(MH 3)

16.0

16

16

4

8.0

18

18

2

6.0

20

20

1.5

4.0

24

24

1

Table 7. Nominal Crystal Parameters
KTAL
FREQ
(MHz)

NOTE
As with any clock oscillator circuit, stray capacitance due
to board layout can affect circuit operation requiring "fine
tuning" (e.g., component repositioning or value change)
of the circuits shown in Figures 6 and 7.
Table 6 identifies nominal crystal parameters for five crystal
frequencies.
1.5K

XTAL
FREQ
(MHz)

Rs
(ohms)

Co
(pF)

C1
(pF)

Q
(K)

16.0

10-30

3-5

0.01-0.02

720K

8.0

20-40

4-6

0.01-0.02

720K

6.0

30·50

4-6

001-0.02

720K

4.0

50

65

0025

730K

3.58

60

3.5

0.015

740K

Note: These represent cut crystal parameters only.
Others may be used.

3.0K

STOPPING THE CLOCK-STANDBY MODE

R65C02

Caution must be exercised when configuring the R65C02 or
R65C112 in the standby mode (i.e., 00 IN or 02 IN clock
stopped). The input clock can be held in the high state indefinitely; however, if the input clock is held in the low state longer
than 5 microseconds, internal register and data status can be
lost. Figure 8 shows a circuit that will stop the 00 IN (R65C02)
or 021N R65C112) clock in the high state during standby mode.

00 (IN)'

02 (OUT) 39

Notes: 1. Crystal CTS Knight MP Series.
2. See STOPPING THE CLOCK CAUTION.
Figure 6. Example of R65C02 External Time Base
Generator Circuit.

C1N

~

Vee

R65C102

STOP
L=STANDBY
H=ACTIVE

R65C112

TIME
BASE
(SEE FIG. 6)

37 XTLI

XTALc::J
(F)

MASTER
\12 (OUT) 39

35
.............--!XTLO

SLAVE

CPU
C1 R Q

112(OUT)

+5V

-"""'--37"1112 (IN)
NOTE:
1. R65C02 = 110 (IN)
R65C112 = 112 (IN)

7404

."". COUT

Notes: 1. The oscillator in the R65C102 is series
resonant.
2. R65C102 crystal frequency is divided by 4,
i.e., \&2 (OUT) = F/4.
3. See STOPPING THE CLOCK CAUTION.
4. See Table 6 for component values.

Figure 8. Stopping the Clock (Standby Mode) Circuit

Figure 7. Example of R65C102/R65C112
Master/Slave Clock Circuit
2-239

fJ

R65C02, R65C102, and R65C112

R65COO Microprocessors (CPU)

MAXIMUM RATINGS·
Parameter

°Note

Symbol

Supply Voltage
Input Voltage
Output Voltage

value

Unit

Vcc

-0.3 to +7.0

Vdc

VIN

-0.3 to Vce +0.3

Vdc

VOUT

-0.3 to Vee +0.3

Vdc

Operating Temperature
Commercial
Industrial
Storage Temperature

Stresses above those listed may cause permanent damage to
the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

°C

TA
Old +70
-40 to +85
Tsro

-55 to +150

°C

OPERATING CONDITIONS
Parameter

Symbol

Value

Vee

5V ±5%

Supply Voltage
Temperature Range
Commercial
Industrial

TA
0° to 70°C
-40°C to +85°C

DC CHARACTERISTICS
Parameter

Symbol

Input High Voltage
All Other Input Pins
\110 on R65C02
\112 on R65C112

VIH

Input Low Voltage
All Other Input Pins
\110 on R65C02
\112 on R65C112

V IL

Input Leakage Current
NMI. IRO. BE. ROY. RES. SO
\1I2IN,\!I0IN,XTU

'iN

Min

Typ

Max

2.0
2.4
Vee - 0.4

Vee + 0.3
Vee + 0.3
Vee + 0.3

-03
-0.3
-0.3

+0.8
+0.4
+0.4

-

-50
1.0

V

pA

VIN = OV to 5.25V
Vee = OV

pA

VIN = O.4V to 2.4V
Vee = 5.25V

V

Vee = 4.75V
ILOAD = -100 p.A

+0.4

V

Vee = 4.75V
ILOAD = 1.6 rnA

10
4
7
4

p.A
rnA/MHz
rnA/MHz
rnA/MHz
rnA/MHz
rnA/MHz
rnA/MHz

'

TSI

-

10

Output High Voltage
SYNC, Data, AO-AI5, RiW, 01, \112, \114, ML

VOH

2.4

-

Supply Current
Standby'
Active (R65C02)
Active (R65Cl02)
Active (R65CI12)
Low Power (R65C02)
Low Power (R65Cl02)
Low Power (R65CI12)
Capacitance
NMI, IRO, SO, BE, ROY
Data, 01, 02. 04, ML, XTLO
AO-AI5, RiW, SYNC
\110 (IN), XTU
\112 (IN)

. VOL

-

Icc

-

-C
CIN
COUT
Co
Cz

Test Conditions

V

Three-State (Off State) Input Current
Data Lines

Output Low Voltage
SYNC, Data, AO-AI5, RiW, 01, 02. \114, ML

Unit

2
2.6
5
2
1.1
3
0.7

2
4
1

Vee

ROY
ROY

= 5.0V
=0
=0

pF

-

7
10

-

10
30

Notes:
1. All units are direct current (dc).
2. Negative sign Indicates outward current flow, positive indicates Inward flow.
3. IRO and NMI require external pull-up resistor.
4. Typical values are shown for Vee = 5.0V and TA = 25°C
2-240

Vee = 5.0V
VIN = OV
f = 1 MHz
TA = 25°C

R65C02, R65C102, and R65C112

R65COO Microprocessors (CPU)

PACKAGE DIMENSIONS
40-PIN CERAMIC DIP

[ D ::I]
I·

A

W
H~~LD
F

·1

~n

G~ ~

K

-4~J

MILLIMETERS
INCHES
MAX
MIN
MAX
PIM MIN
A
5029 5131 1980 2020
1486 1562 0585 0615
B
254
419 0100 0165
C
053 0015 0021
D
038
F
076
140 0030 0055
254 SSC
a 100 sse
G
H
178 0030 0070
076
033 0008 0013
J
020
419 0100 0165
K
254
L
1460 1537 0575 0605
10'
0'
10'
M
0'
N
051
152 0020 0060

M-j

40-PIN PLASTIC DIP
MILLIMETERS
DIM MIN
MAX
A
5128 5232
B
1372 1422
508
C
355
D
036
051
F
152
102
G
254
216
H
165
030
J
020
K
356
305
1524B$C
L
10"
M
051
102
N

sse

r

2-241

INCHES
MAX
MIN
2040 2060
0540 0560
0140 0200
0014 0020
0040 0060

a 100 BSC
0065 0085
0008 0012
0120 0140
0600 ssc
r
10'
0020 0040

PI

R65C21

'1'

Rockwell

R65C21
PERIPHERAL INTERFACE ADAPTER (PIA)
PRELIMINARY

DESCRIPTION

FEATURES

The R65C21 Peripheral Interface, Adapter (PIA) is designed to
solve a broad range of peripheral control problems in the implementation of microcomputer systems. This device allows a very
effective trade-off between software and hardware by providing
significant capability and flexibility in a low cost Chip. When coupled with the power and speed of the R6500, R6500/* or R65COO
family of microprocessors, the R65C21 allows Implementation
of very complex systems at a minimum overall cost.

• Low power CMOS N-well silicon gate technology
• Direct replacement for NMOS R6520 or MC6821 PIA
• Two 8-bit bidirectional I/O ports with indiVidual data direction
control

Control of peripheral devices IS handled primarily through two
8-bit bldlrecllonal ports. Each of these lines can be programmed
to act as either an input or an output. In addition, four peripheral
control/interrupt input lines are provided. These lines can be
used to interrupt the processor or to "handshake" data between
the processor and a peripheral device

•
•
•
•
•

Automatic "Handshake" control of data transfers
Two interrupts (one for each port) with program control
1, 2, 3, and 4 MHz versions
Commercial and Industrial temperature range versions
40-pin plastiC and ceramic versions

• 5 volt ±5% supply requirements
• Compatible with the R6500, R6500/* and R65COO family of
microprocessors

ORDERING INFORMATION
VSS
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
CBl
CB2
VCC

The R65C21 is available In both a ceramic and a plastiC 40-pin
package, a commercial or Industnal operating temperature range,
and operating frequencies of 1, 2, 3, or 4 MHz These versions
are coded into the part number as follows:

Part Number:
R65C2L __
Temperature Range (T L to T H):
Blank = O°C to + 70°C
E = -40°C to +85°C

L

Frequency Range'
1 = 1 MHz
2 =2 MHz
3 =3 MHz
4 =4 MHz
Package.
C = Ceramic
P = PlastiC

CAl
CA2
IRQA
IROB
RSO
RSl
RES
DO
01
02
03
D4

05
06
07

02
CSl
CS2
CSO
R/'N

Figure 1. R65C21 Pin Configuration

Document No. 29651 N53
2-242

Product Description Order No. 2150
Rev. 3, October 1984

Peripheral Interface Adapter (PIA)

R65C21
FUNCTIONAL DESCRIPTION
The R65C21 PIA is organized into two independent sections
referred to as the A Side and the B Side. Each section consists
of a Control Register (CRA, CRB), Data Direction Register
(DORA, DDRB), Output Register (ORA, ORB), Interrupt Status
Control (ISCA, ISCB), and the buffers necessary to drive the
Peripheral Interface buses. Data Bus Buffers (DBB) interface

data from the two sections to the data bus, while the Data Input
Register (DIR) interfaces data from the DBB to the PIA registers.
Chip Select and R/W control circuitry interface to the processor
bus control lines. Figure 2 is a block diagram of the R65C21
PIA.

IRQA

INTERRUPT STATUS
CONTROL A (ISCA)

I

CA1
CA2

t

I

DO

01

CONTROL
REGISTER A
(CRA)

.-

02
03

04
05

06
07

-- --

DATA BUS
BUFFER
(DBB)

OUTPUT BUS

k
I

~

I

U

PERIPHERAL
OUTPUT
REGISTER B
(ORB)

CSO

PERIPHERAL
INTERFACE
BUFFER A
(PIBA)

b
~

RSO

RS1

RJW

.2

RES

--

CHIP
SELECT

&Rfii
CONTROL

L--

•

---.J L

-

R65C21 PIA Block Diagram

2-243

PA4

..

-

-=
--

PA5
PA6

PA7
PBO

PB1
PB2

PB3
PB4

PB5
PB6
PB7

DATA DIRECTION
REGISTER B
(DDRB)

IRQB

Figure 2.

PA3

-"'

it

INPUT BUS
CONTROL
REGISTER B
(CRB)

PERIPHERAL
INTERFACE
BUFFER B
(PIBB)

PA1
PA2

~

j",

CS1

CS2

PAO
-"'

PERIPHERALll
OUTPUT
REGISTER A
(ORA)

U
DATA INPUT
REGISTER
(DIR)

r---,r

DATA DIRECTION
REGISTER A
(DORA)

INTERRUPT STATUS
CONTROL B (ISCB)

CB1

CB2

PI

R65C21

Peripheral Interface Adapter (PIA)

DATA INPUT REGISTER (DIR)

PERIPHERAL OUTPUT REGISTERS (ORA, ORB)

When the microprocessor writes data into the PIA, the data
which appears on the data bus during the 02 clock pulse is
latched into the Data Input Register (DIR). The data is then
transferred into one of six internal registers of the PIA after the
trailing edge of the 02 clock. This assures that the data on the
peripheral output lines will make smooth transitions from high
to low (or from low to high) and the voltage will remain stable
except when it is going to the opposite polarity.

The Peripheral Output Registers (ORA, ORB) store the output
data from the Data Bus Buffers (DBB) which appears on the
Peripheral I/O port. If a line on the Peripheral A Port is programmed as an output by the DDRA, writing a 0 into the corresponding bit in the ORA causes that line to go low «0.4 V);
writing a 1 causes the line to go high. The lines of the Peripheral
B port are controlled by ORB in the same manner.

INTERRUPT STATUS CONTROL (ISCA, ISCB)
CONTROL REGISTERS (CRA AND CRB)

The four interrupVperipheral control lines (CAl, CA2, CB1, CB2)
are controlled by the Interrupt Status Control logic (A, B). This
logic interprets the contents of the corresponding Control Register and detects active transitions on the interrupt inputs.

Table 1 Illustrates the bit deSignation and functions In the two
control registers. The control registers allow the microprocessor
to control the operation of the Interrupt Control inputs (CAl,
CA2, CB1, CB2), and Peripheral Control outputs (CA2, CB2).
Bit 2 in each register controls the addressing of the Data Direction Registers (DDRA, DDRB) and the Output Registers (ORA,
ORB). In addition, two bits (bit 6 and 7) in each control register
indicate the status of the Interrupt Input lines (CAl, CA2, CB1,
CB2). These Interrupt Status bits (IRQA1, IRQA2 or IRQB1,
IRQB2) are normally interrogated by the microprocessor during
the IRQ interrupt service routine to determine the source of the
interrupt.

PERIPHERAL I/O PORTS (PAO-PA7, PBO-PB7)
The Peripheral A and Peripheral B VO ports allow the microprocessor to interface to the input lines on the peripheral device
by writing data into the Peripheral Output Register. They also
allow the processor to interface with the peripheral device output
lines by reading the data on the Peripheral Port input lines
directly onto the data bus and into the internal registers of the
processor.

DATA DJRECTION REGISTERS (DDRA, DDRB)

Each of the Peripheral I/O lines can be programmed to act as
an input or an output. This is accomplished by setting a 1 in the
corresponding bit in the Data Direction Register for those lines
which are to act as outputs. A 0 in a bit of the Data Direction
Register causes the corresponding Peripheral I/O lines to act
as an input.

The Data Direction Registers (DDRA, DDRB) allow the processor to program each line in the 8-bit Peripheral I/O port to
be either an input or an output. Each bit in DDRA controls the
corresponding lilie In the Peripheral A port and each bit in DDRB
controls the corresponding line In the Peripheral B port. Writing
a "0" In a bit position In the Data Direction Register causes the
corresponding Peripheral I/O line to act as an input; a "1"
causes It to act as an output.

The buffers which drive the Peripheral A I/O lines contain "passive" pull-up devices. These pull-up devices are resistive in
nature and therefore allow the output voltage to go to VCC for
a logic 1. The switches can sink a full 3.2 mA, making these
buffers capable of driving two standard TTL loads.

Bit 2 (DDRA, DDRB) in each Control Register (CRA and CRB)
controls the accessing to the Data Direction Register or the
Peripheral interface. If bit 2 is a "1," a Peripheral Output register
(ORA, ORB) IS selected, and If bit 2 is a "0," a Data Direction
Register (DDRA, DDRB) is selected. The Data Direction Register Access Control bit, together with the Register Select lines
(RSO, RS1) selects the various internal registers as shown in
Table 2.

In the input mode, the pull-up devices are still connected to the
I/O pin and still supply current to this pin. For this reason, these
lines also represent two standard TTL loads in the input mode.
The Peripheral B I/O port duplicates many of the functions of
the Peripheral A port. The process of programming these lines
to act as an input or an output is similar to the Peripheral A port,
as is the effect of reading or writing this port. However, there
are several characteristics of the buffers driving these lines
which affect their use in peripheral interfacing.

In order to write data into DDRA, ORA, DDRB, or ORB registers,
bit 2 in the proper Control Register must first be set. The desired
register may then be accessed with the address determined by
the address interconnect technique used.

Control Registers Bit Designations

Table 1.

7
CRA

CRB

IRQAl

6

5

IRQA2

7

6

IRQBl

IRQB2

4

3

CA2 Control

5

4
CB2 Control

2-244

2

1

DDRA
Access

3

2
DDRB
Access

0
CAl Control

0

1
CBl Control

Peripheral Interface Adapter (PIA)

R65C21
The Peripheral B I/O port buffers are push-pull devices i.e., the
pull-up devices are switched OFF in the 0 state and ON for a
logic 1. Since these pull-ups are active devices, the logic 1
voltage will not go higher than +2.4V.

Figure 1 (on the front page) shows the pin assignments for these
interface signals and Figure 3 shows the interface relationship
of these Signal as they pertain to the CPU and the peripheral
devices.

Another difference between the PAO-PA7 lines and the PBO
through PB7 lines is that they have three-state capability which
allows them to enter a high Impedance state when programmed
to be used as input lines. In addition, data on these lines will be
read properly, when programmed as output lines, even if the
data signals fall below 2.0 volts for a "high" state or are above
0.8 volts for a "low" state. When programmed as output, each
line can drive at least a two TIL load and may also be used as
a source of up to 3.2 milliamperes at 1.5 volts to directly drive
the base of a transistor switch, such as a Darlington pair.

The PIA IS selected when CSO and CSl are high and CS2 is
low. These three chip select lines are .normally connected to the
processor address lines either directly or through external
decoder circuits. When the PIA is selected, data will be transferred between the data lines and PIA registers, and/or peripheral Interface lines as determined by the R/W, RSO, and RSl
lines and the contents of Control Registers A and B.

Because these outputs are designed to drive transistors directly,
the output data is read directly from the Peripheral Output RegIster for those lines programmed to act as inputs.

The Reset (RES) Input Initializes the R65C21 PIA. A low signal
on the RES Input causes all Internal registers to be cleared.

CHIP SELECT (CSO, CSt, CS2)

RESET SIGNAL (RES)

CLOCK SIGNAL (02)

The final charactenstlc IS the high-Impedance Input state which
is a function of the Penpheral B push-pull buffers. When the
Peripheral B I/O lines are programmed to act as Inputs, the
output buffer enters the high Impedance state.

The Phase 2 Clock Signal ( r/J2) IS the system clock that triggers
all data transfers between the CPU and the PIA. 02 is generated by the CPU and is therefore the synchronizing signal
between the CPU and the PIA.

DATA BUS BUFFERS (DBB)
READ/WRITE SIGNAL (R/W)

The Data Bus Buffers are 8-bit bidirectional buffers used for data
exchange, on the 00-07 Data Bus, between the microprocessor
and the PIA. These buffers are tn-state and are capable of
driving a two TIL load (when operating In an output mode) and
represent a one TTL load to the microprocessor (when operating in an Input mode).

Read/Write (R/W) controls the direction of data transfers between
the PIA and the data lines associated with the CPU and the
peripheral devices. A high on the R/W line permits the peripheral
devices to transfer data to the CPU from the PIA. A low on the
R/W line allows data to be transfered frorn the CPU to the
peripheral devices from the PIA.

INTERFACE SIGNALS
REGISTER SELECT (RSO, RSt)

The PIA Interfaces to the R6500, R6500/' or the R65COO microprocessor family With a reset line, a r/J2 clock line, a read/wnte
line, two interrupt request lines, two register select lines, three
chip select lines, and an 8-blt bidirectional data bus.

The two Register Select lines (RSO, RS1), in conjunction with
the Control Registers (CRA, CRB) Data Direction Register access
bits (see Table 1, bit 2) select the various R65C21 registers to
be accessed by the CPU. RSO and RSl are normally connected
to the rnicroprocessor (CPU) address output lines. Through control of these lines. the CPU can write directly into the Control

The PIA interfaces to the peripheral devices with four interrupV
control lines and two 8-bit bidirectional data buses.

. ,
00-07 ~

(8)

,

Y PAO-PA7 }

(8)

\12
R6S00,
R6S00/'
OR
R6SCOO
MICROPROCESSOR
;:AMILY

R/W
RSO
RSl
CSO
CSl
CS2
RES
IROA
IROB
YSS
YCC

CAl
CA2

PERIPHERAL
DEVICE
A

R6SC2l
PIA

...

..

•
~

~

(8)

Figure 3.

Interface Signals Relationship
2-245

CBl
CB2

/

PBO-PB7

}

PERIPHERAL
DEVICE
B

fI

Peripheral Interface Adapter (PIA)

R65C21

by CRB bit O. Likewise, bit 6 (IROB2) in CRB is set by an active
transition on CB2, and IROB from this flag is controlled by CRB
bit 3.

Registers (CRA, CRB) the Data Direction Registers (DORA,
DDRB) and the Peripheral Output Registers (ORA, ORB). In
addition, the processor may directly read the contents of the
Control Registers and the Data Direction Registers. Accessing
the Peripheral Output Register for the purpose of reading data
back into the processor operates differently on the ORA and the
ORB registers and therefore are shown separately in Table 2.

Also, both bit 6 and bit 7 of CRB are reset by a "Read Peripheral
B Output Register" operation. A summary of IROB control is
shown in Table 3.

Table 3.
Table 2. ORA and ORB Register Addressing
Register
Deta Direction
Select Lines
Control

Register
Address
(Hex)
RSI
0
0
1
2
2

3

L
L
L
H
H
H

RSO

CRA CRB
(Bit 2) (Bit 2)

L
L

1
0

H

-

L
L

H

-

-

-

1
0

-

Register Operetion
R,w=H
Read
Read
Read
Read
Read
Read

PIBA
DORA
CRA
PIBB
DDRB
CRB

R,w=L
Write
Write
Write
Write
Write
Write

IROA and IROB Control Summary

Control Register Bits

Action

CRA-7=1 and CRA-O=1

IROA goes low (Active)

CRA-6=1 and CRA-3=1

IROA goes low (Active)

CRB-7=1 and CRB-O=1

IROB goes low (Active)
IROB goes low (Active)

CRB-6=1 and CRB-3=1

ORA
DDRA
CRA
ORB
DDRB
CRB

Note:
The flags act as the link between the peripheral interrupt signals
and the processor interrupt inputs. The interrupt disable bits allow
the processor to control the interrupt function.

INTERRUPT INPUT/PERIPHERAL CONTROL LINES
(CA1, CA2, CB1, CB2)
INTERRUPT REQUEST LINES (IRQA, IRQB)

The four interrupt input/peripheral control lines provide a number
of special peripheral control functions. These. lines greatly
enhance the power of the two general purpose interface ports
(PAO·PA7, PBO-PB7). Figure 4 summarizes the operation of
these control lines.

The active low Interrupt Request lines (IROA and IROB) act to
interrupt the microprocessor either directly or through external
interrupt priority circuitry. These lines are open drain and are
capable of sinking 1.6 milliamps from an external source. This
permits all interrupt request lines to be tied together in a wiredOR configuration. The A and B in the titles of these lines correspond to the peripheral port A and the peripheral port B so
that each interrupt request line services one peripheral data
port.

CAl is an interrupt input only. An active transition of the signal
on this input will set bit 7 of the Control Register A to a logic 1.
The active transition can be programmed by setting a "0" in bit
1 of the CRA if the interrupt flag (bit 7 of CRA) is to be set on
a negative transition of the CAl signal or a "1" if it is to be set
on a positive transition.

Each Interrupt Request line has two interrupt flag bits which can
cause the Interrupt Request line to go low. These flags are bits
6 and 7 in the two Control Registers (CRA, CRB). These flags
act as the link between the peripheral interrupt signals and the
microprocessor interrupt inputs. Each flag has a corresponding
interrupt disable bit which allows the processor to enable or disable the interrupt from each of the four interrupt inputs (CAl,
CA2, CB1, CB2). The four interrupt flags are set (enabled) by
active transitions of the signal on the interrupt input (CAl, CA2,
CB1, CB2).

NOTE:
A negative transition is defined as a transition from a high
to a low, and a positive transition is defined as a transition
from a low to a high voltage.
CA2 can act as a totally independent interrupt or as a peripheral
control output. As an input (CRA, bit 5 = 0) it acts to set the
interrupt flag, bit 6 of CRA, to a logic 1 on the active transition
selected by bit 4 of CRA.

CRA bit 7 (IROA1) is always set by an active transition of the
CAl interrupt input signal. However, IROA can be disabled by
setting bit 0 in CRA to a o. Likewise, CRA bit 6 (IROA2) can be
set by an active transition of the CA2 interrupt input signal and
IROA can be disabled by setting bit 3 in CRA to a O.

These control register bits and interrupt inputs serve the same
basic function as that described above for CAl. The input signal
sets the interrupt flag which serves as the link between the
peripheral device and the processor interrupt structure. The
interrupt disable bit allows the processor to exercise control over
the system interrupt.

Both bit 6 and bit 7 in CRA are reset by a "Read Peripheral
Output Register A" operation. This is defined as an operation
in which the read/write, proper data direction register and register select signals are provided to allow ~rocessor to read
the Peripheral A I/O port. A summary of IROA control is shown
in Table 3.

In the output mode (CRA, bit 5 = 1), CA2 can operate independently to generate a simple pulse each time the microprocessor reads the data on the Peripheral A I/O port. This mode
is selected by setting CRA, bit 4 to a 0 and CRA, bit 3 to a 1.
This pulse output can be used to control the counters, shift registers, etc., which make sequential data available on the Peripheral input lines.

Control of IROB is performed in exactly the same manner as
that described above for IROA. Bit 7 in CRB (IROB1) is set by
an active transition on CBl and IROB from this flag is controlled

2-246

R65C21

Peripheral Interface Adapter (PIA)

CONTROL REGISTER A (CRA)
CA2 INPUT MODE (BIT 5 = 0)

7

6

5

4

3

2

1

0

IRQAl
FLAG

IRQA2
FLAG

CA2 INPUT
MODE SELECT
(=0)

IRQA2
POSITIVE
TRANSITION

IRQA
ENABLE
FOR IRQA2

ORA
SELECT

IRQAl
POSITIVE
TRANSITION

IRQA
ENABLE
FOR IRQAl

IRQNIRQA2
CONTROL

CA2 OUTPUT MODE (BIT 5

IRQNIRQAI
CONTROL

= 1)

7

6

5

4

3

2

1

0

IRQAl
FLAG

0

CA2 OUTPUT
MODE SELECT
(=1)

CA2
OUTPUT
CONTROL

CA2
RESTORE
CONTROL

ORA
SELECT

IRQAl
POSITIVE
TRANSITION

IRQA
ENABLE
FOR IRQAl

IRQNJRQAl
CONTROL

CA2
CONTROL

CA21NPUT OR OUTPUT MODE (BIT 5 = 0 or 1)
Bit 7
1

o
Bit 2

1

a
Bit 1
1

a
Bit 0
1

a

IRQA1 FLAG
A transition has occurred on CAl that satisfies the bit 1 IRQA1 transition polarity criteria. ThiS bit IS cleared by a read of Output Register
A or by RES.
No transition has occurred on CAl that satisfies the bit 1 IRQA 1 transition polarity criteria.
OUTPUT REGISTER A SELECT
Select Output Register A.
Select Data Direction Register A.
IRQA 1 POSITIVE TRANSITION
Set IRQAl Flag (bit 7) on a positive (Iow-to-high) transition of CAl.
Set IRQAl Flag (bit 7) on a negative (high-to-Iow) transition of CAt.
IRQA ENABLE FOR IRQAl
Enable assertion of IRQA when IRQAl Flag (bit 7) is set.
Disable assertion of IRQA when IRQA 1 Flag (bit 7) is set.

CA2 INPUT MODE (BIT 5
Bit 6
1

a

= 0)

CA2 OUTPUT MODE (BIT 5 = 1)

IRQA2 FLAG
A transition has occurred on CA2 that satisfies the bit 4
IRQA2 transition polarity criteria. This flag is cleared by
a read of Output Register A or by RES.
No transition has occurred on CA2 that satisfies the bit
4 IRQA2 transition polarity criteria.
CA2 MODE SELECT
Select CA2 Input Mode.

Bit 4
1

IRQA2 POSITIVE TRANSITION
Set IRQA2 Flag (bit 6) on a positive (Iow-to-high)
transition of CA2.
Set IRQA2 Flag (bit 6) on a negative (high-to-Iow)
transition of CA2.

a
Bit :3
1

a

NOT USED
Always zero.

Bit 5
1

CA2 MODE SELECT
Select CA2 Output Mode.

Bit 4

CA2 OUTPUT CONTROL
CA2 goes low when a zero is written into CRA bit 3.
CA2 goes high when a one is written into CRA bit 3.
CA2 goes Iowan the first negative (high-to-Iow) 02
clock transition following a read of Output Register A.
CA2 returns high as specified by bit 3.

a

1

Bit 5

a

Bit 6

a
Bit 3

1

o

iRQA ENABLE FOR iRQA2
Enable assertion of IRQA when IRQA2 Flag (bit 6) is
set.
Disable assertion of IRQA when IRQA2 Flag (bit 6) is
set.

Figure 4.

Control Line Operations Summary (1 of 2)

2-247

=

CA2 READ STROBE RESTORE CONTROL (4 0)
CA2 returns high on the· next 02 clock negative
transition following a read of Output Register A.
CA2 returns tllgh on the nexi aCllVe CA1 iranslilon
following a read of Output Register A as specified by
bit 1.

fI

R65C21

Peripheral Interface Adapter (PIA)

CB2 INPUT MODE (BIT 5

CONTROL REGISTER B (CRB)

= 0)

7

6

5

4

3

2

1

0

IROBI
FLAG

IROB2
FLAG

CB21NPUT
MODE SELECT
(=0)

IROB2
POSITIVE
TRANSITION

IROB
ENABLE
FOR IROB2

ORB
SELECT

IROBI
POSITIVE
TRANSITION

IROB
ENABLE
FOR IROBI

IROB/IROB2
CONTROL

CB2 OUTPUT MODE (BIT 5

IROB/IROBI
CONTROL

= 1)

7

6

5

4

3

2

1

0

IROBI
FLAG

0

CB2 OUTPUT
MODE SELECT
(=1)

CB2
OUTPUT
CONTROL

CB2
RESTORE
CONTROL

ORB
SELECT

IROBI
POSITIVE
TRANSITION

IROB
ENABLE
FOR IROBI

IROB/IROBI
CONTROL

CB2
CONTROL

CB21NPUT OR OUTPUT MODE (BIT 5 = 0 or 1)
Bit 7
1

a

IROBI FLAG
A transition has occurred on CBl that satisfies the bit 1 IROBI transition polarity criteria. This bit is cleared by a read of Output Register
B or by RES.
No transition has occurred on CBl that satisfies the bit 1 IROBI transition polarity criteria.

Bit 2
1
o

OUTPUT REGISTER B SELECT
Select Output Register B.
Select Data Direction Register B.

Bit 1
1

IROB1 POSITIVE TRANSITION
Set IROBI Flag (bit 7) on a posrtive (Iow-to-high) transition of CB1.
Set IROBI Flag (bit 7) on a negative (high-to-Iow) transition of CB1.

Bit 0
1
o

IROB ENABLE FOR IROBI
Enable assertion of IROB when IROBI Flag (bit 7) is set.
Disable assertion of IROB when IROBI Flag (bit 7) is set.

a

CB2 INPUT MODE (BIT 5
Bit 6
1

a

BH 5

a
Bit 4
1

o
Bit 3
1
o

= 0)

CB2 OUTPUT MODE (BIT 5 = 1)

IROB2 FLAG
A transition has occurred on CB2 that satisfies the bit 4
IROB2 transition polarity criteria. This flag is cleared by
a read of Output Register B or by RES.
No transition has occurred on CB2 that satisfies the bit
4 IRQB2 transition polarity criteria.
CB2 MODE SELECT
Select CB2 Input Mode.

Bit 6
o

NOT USED
Always zero.

Bit 5

CB2 MODE SELECT
Select CB2 Output Mode.

Bit 4
1

CB2 OUTPUT CONTROL
CB2 goes low when a zero IS written into CRB bit 3.
CB2 goes high when a one IS written Into CRB bit 3.
CB2 goes low on the first negative (high-to-Iow) \\2
clock transition follOWing a write to Output Register B.
CB2 returns high as specified by bit 3.

o

IROB2 POSITIVE TRANSITION
Set IROB2 Flag (bit 6) on a positive (Iow-to-high)
transition of CB2.
Set IROB2 Flag (bit 6) on a negative (high-to-Iow)
transition of CB2.

Bit 3

IROB ENABLE FOR IRQB2
Enable assertion of iRciB when IROB2 Flag (bit 6) is
set.
Disable assertion of IROB when IROB2 Flag (bit 6) is
set.

Figure 4.

o

CB2 WRITE STROBE RESTORE CONTROL
(BIT 4 0)
CB2 returns high on the next 02 clOCk negative
transition follOWing a write to Output Register B.
CB2 returns high on the next active CBl transition
following a write to Output Register B as specified by
bit 1.

=

Control Line Operations Summary (2 of 2)

2·248

R65C21

Peripheral Interface Adapter (PIA)

A second output mode allows CA2 to be used in conjunction
with CA 1 to "handshake" between the processor and the
peripheral device. On the A side, this technique allows posrtive
control of data transfers from the peripheral deVice into the
microprocessor. The CA1 Input signals the processor that data
is available by interrupting the processor. The processor reads
the data and sets CA2 low. This signals the peripheral deVice
that it can make new data available.

transfers the data on the Peripheral A 1/0 lines to the data bus.
In this situation, the data bus will contain both the input and output data. The processor must be programmed to recognize and
interpret only those bits which are important to the particular
peripheral operation being performed.
Since the processor always reads the Peripheral A 1/0 port pins
instead of the actual Peripheral Output Register (ORA), it is
possible for the data read by the processor to differ from the
contents of the Peripheral Output Register for an output line.
This is true when the 1/0 pin is not allowed to go to a full
+ 2.4V DC when the Peripheral Output register contains a
logiC 1. In thiS case, the processor will read a 0 from the
Peripheral A pin, even though the corresponding bit in the
Peripheral Output register is a 1.

The final-output mode can be selected by setting bit 4 of CRA
to a 1. In this mode, CA2 is a simple peripheral control output
which can be set high or low by setting bit 3 of CRA to a 1 or
a 0 respectively.
CB1 operates as an interrupt input only in the same manner as
CA1. Bit 7 of CRB IS set by the active transition selected by bit
o of CRB. Likewise, the CB2 Input mode operates exactly the
same as the CA2 Input modes. The CB2 output modes, CRB
bit 5 = 1, differ somewhat from those of CA2. The pulse output
occurs when the processor writes data Into the Peripheral B
Output Register. Also, the "handshaking" operates on data
transfers from the processor Into the peripheral device.

READING THE PERIPHERAL B 1/0 PORT
Reading the Peripheral B 1/0 port yields a combination of input
and output data in a manner similar to the Peripheral A port.
However, data IS read directly from the Peripheral B Output
Register (ORB) for those lines programmed to act as outputs.
It is therefore possible to load down the Peripheral B Output lines
without causing incorrect data to be transferred back to the
processor on a Read operation.

READING THE PERIPHERAL A 1/0 PORT
Performing a Read operation with RS1 = 0, RSO = 0 and the
Data Direction Register Access Control bit (CRA-2) = 1, directly

'2 ______________

~

RSO, RS1,
CSO,CS1,CS2
PAO-PA7

~~~~

.Ie-----+-------f--------------I---------------------

PBO-PB7

00-07
DATA OUT

CA2
(PULSE OUT)

CA1

CA2
(HAND SHAKE)

Figure 5.

Read Timing Waveforms
2-249

2

Peripheral Interface Adapter (PIA)

R65C21

112

RSO, RS1,
CSO, CS1, CS2

RIW

00·07
DATA IN

PAO.PA7 -,eo~~~!r'l!"""~~JtIL-I------~-----------­
PBO·PB7 .........................,,"""''''''''';.lUI.J1JI1E----:I------~-----------CB2
(PULSE OUT)

CBl

CB2
(HAND SHAKE)

Figure 6.

Write Timing Waveforms

2·250

R65C21

Peripheral Interface Adapter (PIA)

BUS TIMING CHARACTERISTICS
2 MHz

1 MHz
Parameter
!/l2 Cycle
!/l2 Pulse Width
!/l2 Rise and Fall Time

4 MHz

3 MHz

Symbol

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

tevc
te

1.0
450

-

0.5
220

-

0.33
160

-

0.25
110

-

Ire. Ire

-

25

-

15

-

12

Unit
p.S

10

ns
ns

20

80
-

ns
ns
ns
ns
ns

35
0
45
0
45
10

-

ns
ns
ns
ns
ns
ns

-

READ TIMING
Address Set-Up TIme
Address Hold Time
Peripheral Data Set·Up Time
Data Bus Delay Time
Data Bus Hold Time

tACR

leAR
tPCR
teDR
tHR

140
0
300

-

-

-

335

20

-

tACw
!cAw
twow
teww
tDOW
tHW
tepw
teMOS

140
0
180
0
180
10

-

tPCR
teA2
tRS1
tRS2
teB2
toe
IRS1
tRS2
t,.1t

300

70
0
150

-20

-

145
-

53
0
110

-

-

-20

105

53
0
67
0
67
10

-

-

35
0
75

-

WRITE TIMING
Address Set·Up Time
Address Hold Time
RiW Set-Up Time
RiW Hold Time
Data Bus Set·Up Time
Data Bus Hold Time
Perlpheral Data Delay Time
Peripheral Data Delay Time
to CMOS Level

-

70
0
90
0

90
10

1.0
2.0

-

-

150

-

0.5
1.0

-

-

110

0.33
0.7

-

0.25
0.5

p.S
p.S

PERIPHERAL INTERFACE TIMING
Peripheral Data Set-Up
!/l2 Low to CA2 Low Delay
!/l2 Low to CA2 High Delay
CAl Active to CA2 High Delay
!/l2 High to CB2 Low Delay
Peripheral Data Valid to CB2 Low Delay
!/l2 High to CB2 High Delay
CBl Active to CB2 High Delay
CAl. CA2. CBl and CB2
Input Rise and Fall TIme

0
-

1.0
1.0
2.0
1.0
1.5
1.0
2.0
1.0

2-251

-0
-

0.5
0.5
1.0
0.5
0.75
0.5
1.0
1.0

0
-

-

0.33
0.33
0.67
0.33
0.5
0.33
0.67
1.0

75

0
-

-

0.25
0.25
0.5
0.25
0.37
0.25
0.5
1.0

ns
jlS
jlS
jlS
jlS
jlS
jlS
jlS
jlS

R65C21

Peripheral Interface Adapter (PIA)

ABSOLUTE MAXIMUM RATINGS*
Symbol

Value

Unit

Supply Voltage

Parameter

Vee

-0.3 to +7.0

Vde

Input Voltage

Y'N
VOUT

Output Voltage
Operating Temperature Range
Commercial
Industrial

TA

Storage Temperature

TSTG

·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

- 0.3 to Vee + 0.3 Vdc
-0.3 to Vee +0.3 Vdc
°C

o to

+70
-40 to +65
-55 to +150

°C

OPERATING CONDITIONS
Symbol

Value

Supply Voltage

Parameter

Vcc

5V ±5%

Temperature Range
Commercial
Industrial

TA
O°C to 70°C
- 40°C to + 65°C

DC CHARACTERISTICS
(Vee

= 5.0V ± 5%,

Vss

= 0,

TA

=h

to T H, unless otherwise noted)

Parameter

Symbol

Input High Voltage
All except PBO-PB7, RES
PBO-PB7, RES

V'H

Min.

Typ.3

Max.

Unit2

+2.0
+2.4

-

-

Vee
Vee

V
V

Test Conditions

Input Low Voltage

V,l

-

+0.8

V

Inpu0-e~e

liN

-

±1

±2.5

~

Y'N = OV to Vee
Vee = 5.25V

Input Leakage Current for Three-State Off
DO-D7, PBO-PB7, CB2

ITSI

-

±2

±10

~A

Y'N = O.4V to 2.4V
Vee = 5.25V

Input High Current
PAO-PA7, CA2

I'H

-200

-300

~A

V,H = 2.4V

Input Low Current
PAO-PA7, CA2

I'l

-

-2

rnA

V,l = O.4V

Output High Voltage
Logic
PBO-PB7, CB2 (Darlington Drive)

VOH
2.4
1.5

Output Low Voltage
PAO-PA7, CA2, PBO-PB7, CB2
DO-D7, IROA, IROB

VOL

-

-

Output High Current (Sourcing
Logic
PBO-PB7, CB2 (Darlington Drive)

10H
-200
-3.2

-1500
-6

Output Low Current (Sinking)
PAO-PA7, PBO-PB7,CB2, CA2
DO-D7, IROA, IROB

IOl
3.2
1.6

-

Output Leakage Current (011 State)
IROA,IROB

IOFF

Current
RIW, RES, RSO, RS1, CSO, CS1, CS2, CA1,
CB1,02'

Power Dissipation

Po

Input Capacitance
D~D7, PAO-PA7, PBO-PB7, CA2,CB2
RIW, RES, RSO, RS1,CSO, CS1,CS2
CA1, CB1, 02

C'N

-0.3

-

Output Capacitance
COUT
Notes:
1. All units are direct current (dc) except capacitance.
2. Negative sign indicates outward current Ilow, positive indicates inward flow.
3. Typical values are shown for Vee = 5.0V and TA = 25°C.

2-252

-3.2

Vee = 4.75V
IlOAD = - 200~A
IlOAD = - 3.2mA

+0.4

-

V

~A

rnA

Vee = 4.75V
IlOAD = 3.2 rnA
IlOAD = 1.6 rnA
VOH = 2.4V
VOH = 1.5V
VOL = O.4V

rnA
rnA

1

±10

7

10

-

10
7
20

pF
pF
pF

10

pF

~

VOH = 2.4V
Vee = 5.25V
mW/MHz
Vee = 5.0V
Y'N = OV
1= 2 MHz
TA = 25°C

R65C21

Peripheral Interface Adapter (PIA)

PACKAGE DIMENSIONS
40·PIN CERAMIC DIP

[: D ::III

1M

A
B

C

~---===----,,.:.;JI

- - - - - A _ _ _ _-I.

ti

,

SEATING PLANE

j

j~ FlJ"

G-~

D
F
G
H
J
K
L
M
N

MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
5131
1980
50 29
2020
1466 1562 0585 0615

254 419
038 053
076
140
254 Bse
076
178
020 033
254 419
1460 1537
0'
la'
051
152

0100

0165

0015

0021

0030

0055

a 100 sse
0030

0070

0008

0013
0165

0100
0575

a'
0020

0605
10'
0060

M-ji""

-11-

40·PIN PLASTIC DIP

DIM

A
B
C

D
F
G
H
J
K
L
M
N

2-253

MILLIMETERS
INCHES
MIN
MIN
MAX
MAX
5128 5232 2040 2060
1372 1422 0540 0560
355 5 08 0140 0200

036
102
254
165
020
305
1524
T

051

051 0014
152 0040
0100
216 0065
030 0008
356 0120
SSC
0600
7
10
102 0020

ssc

0020
0060

ssc
0085
0012
0140
SSC

10
0040

R65C22

'1'

Rockwell

R65C22
VERSATILE INTERFACE
ADAPTER (VIA)
PRELIMINARY

DESCRIPTION

FEATURES

The R65C22 Versatile Interface Adapter (VIA) is a very flexible
I/O control device. In addition, this device contains a pair of very
powerful 16-bit interval timers, a serial-to-parallel/parallel-to serial
shift register and input data latching on the peripheral ports.
Expanded handshaking capability allows control of bidirectional
data transfers between VIA's in multiple processor systems.

• Low power CMOS N-well silicon gate technology

The R65C22 includes functions for programmed control of up
to two peripheral devices (Ports A and B). These two program
controlled B-bit bidirectional peripheralI/O ports allow direct interfacing between the microprocessor and selected peripheral
units. Each port has input data latching capability. Two programmable Data Direction Registers (A and B) allow selection of data
direction (input or output) on an individual line basis. The R65C22
also has two programmable 16-bit Interval Timer/Counters with
latches. Timer 1 may be operated in a One-Shot Interrupt Mode
with interrupts on each count-to-zero, or in a Free-Run Mode
with a continuous series of evenly spaced interrupts. Timer 2
functions as both an interval and pulse counter. Serial data
transfers are provided by a serial-to-parallel/parallel-to-serial shift
register. Application versatility is further increased by various
control registers, including-the Interrupt Flag Register, the Interrupt Enable Register, the Auxiliary Control Register and the
Peripheral Control Register.

• TTL compatible peripheral control lines

• Fully compatible with NMOS 6522 devices
• Two B-bit bidirectional I/O ports
• Two 16-bit programmable timer/counters
• Serial bidirectional peripheral I/O
• Expanded "handshake" capability allows positive control of
data transfers between processor and peripheral devices.
• Latched output and input registers on both I/O ports
• 1, 2, 3, and 4 MHz operation
• Single + 5V power supply
• 40-pin ceramic or plastic DIP

Vss

PAD
PAl
PA2

ORDERING INFORMATION

PA3

PA4

PAS
PAS

Part Number:

R65C22

L
'----

PA7
PBO
PBl
PB2
PB3
PB4
PB5
PB6

Temperature Range (T L to TH):
Blank = D·C to + 7D·C
E = -4D·C to + 85·C

PB7
CBl

Frequency
1 = 1 MHz
2 = 2 MHz
3 = 3 MHz
4 = 4 MHz

CAl
CA2
RSO
RSl
RS2
RS3
RES
DO
01

02
03

04
05
06
07
1/)2

CSl
CS2

CB2

RiW

VCC

IRQ

R65C22 Pin Configuration

Package
C = Ceramic
P = Plastic

Document No. 29651 N87
2-254

Product Description Order No. 2184
October 1984

Versatile Interface Adapter (VIA)

R65C22
INTERFACE SIGNALS

CHIP SELECTS (CS1, CS2)

Figure 1 shows the relationship of R65C22 interface signals to
the microprocessor and peripheral devices.

Normally, the two Chip Select lines are connected to the
microprocessor address lines. This connection may be direct
or through decoding. To access a selected R65C22 register, CSl
must be high (Logic 1) and CS2 must be low (Logic 0).

RESET (RES)

REGISTER SELECTS (RSO-RS3)

Reset (RES) clears all internal registers (except Tl and T2
counters and latches, and the Shift Register (SR) ). In the RES
condition, all peripheral interface lines (PA and PB) are placed
in the input state. Also, the Timers (Tl and T2), SR and interrupt logic are disabled from operation.

The Register Select inputs allow the microprocessor to select
one of 16 internal registers within the R65C22. Refer to Table 1
for Register Select coding and a functional description.

INTERRUPT REQUEST (IRQ)

INPUT CLOCK (PHASE 2)

The Interrupt Request (IRQ) output signal is generated whenever
an internal Interrupt Flag bit is set and the corresponding Interrupt Enable bit is a Logic 1. The Interrupt Request output is an
open-drain configuration, thus allowing the IRQ signal to be
wire-ORed to a common microprocessor IRQ input line.

The system Phase 2 (02) Input Clock controls all data transfers
between the R65C22 and the microprocessor.

READ/WRITE (R/W)

PERIPHERAL PORT A (PAO-PA7)

The direction of the data transfers between the R65C22 and the
system processor is controlled by the RiW line in conjunction
with the CSl and CS2 inputs. When RiW is low, (write operation) and the R65C22 is selected, data is transferred from the
processor bus into the selected R65C22 register. When RiW is
high, (read operation) and the R65C22 is selected, data is
transferred from the selected R65C22 register to the processor
bus.

Peripheral Data Port A is an 8-line, bidirectional bus for the
transfer of data, control and status information between the
R65C22 and a peripheral device. Each Peripheral Data Port bus
line may be individually programmed as either an input or output
under control of a Data Direction Register. Data flow direction
may be selected on a line-by-line basis with intermixed input and
output lines within the same port. When a "0" is written to any
bit position of the Data Direction Register, the corresponding
line will be programmed as an input. When a "1" is written into
any bit position of the register, the corresponding data line will
serve as an output. Polarity of the data output is determined by
the Output Register, while input data may be latched into the
Input Register under control of the CA 1 line. All modes are program controlled by the microprocessor by way of the R65C22's
internal control registers. Each Peripheral Data Port line represents one TTL load in the input mode and will drive one standard
TTL load in the output mode. A typical output circuit for
Peripheral Data Port A is shown in Figure 2.

DATA BUS (00-07)
The eight bidirectional Data Bus lines transfer data between the
R65C22 and the microprocessor. During a read operation, the
contents of the selected R65C22 internal register are transferred
to the microprocessor via the Data Bus lines. DUring a write
operation, the Data Bus lines serve as high impedance inputs
over which data is transferred from the microprocessor to a
selected R65C22 register. The Data Bus lines are in the high
impedance state when the R65C22 is unselected.

00-07

PAO-PA7

0 2 - - - - - t..
MICROPROCESSOR
BUS
INTERFACE

..-----CAl

R i W - - - - - t..
CS1, CS2 _ _.......,,t.....;;2~-t~

R65C22

. . - - - -.... CA2

VIA

1 4 - - - -... CBl

RSO-RS3 ---7':......:..4-+1

. .- - - -.... CB2

--'P

RES-----+I

A~_~.""

IRQ - - - - - l.........
, ____

Figure 1.

R65C22 VIA Interface Signals

2-255

PBO-PB7

PERIPHERAL
INTERFACE

fJ

A65C22

Versatile Interface Adapter (VIA)

PORT A CONTROL LINES (CA1, CA2)

pulses on the PS61ine. Port S lines represent one standard TTL
load in the input mode and will drive one TTL load in the output
mode. Port S lines are also capable of sourcing 3.0 mA at
t.5 Vdc in the output mode. This allows the outputs to directly
drive Darlington transistor circuits. A typical output circuit for
Port S is shown in Figure 3.

Control lines CAt and CA2 serve as interrupt inputs or handshake outputs for Peripheral Data Port A. Each line controls an
internal Interrupt Flag with a corresponding Interrupt Enable bit.
CAt also controls the latching of Input Data on Port A. CAt is
a high impedance input, while CA2 represents one standard TTL
load in the input mode. In the output mode, CA2 will drive one
standard TTL load.

PORT B CONTROL LINES (CB1, CB2)
Control lines CSt and CS2 serve as interrupt inputs or handshake outputs for Peripheral Data Port S. Like Port A, these two
control lines control an internal Interrupt Flag with a corresponding Interrupt Enable bit. These lines also serve as a serial data
port under control of the Shift Register (SR). Each control line
represents one standard TTL load in the input mode and can
drive one TTL load in the output mode. Note that CSt and CS2
cannot drive Darlington transistor circuits.

PORT B (PBO-PB7)
Peripheral Data Port S is an 8-line, bidirectional bus which is
controlled by an Output Register, Input Register and Data Direction Register in a manner much the same as Data Port A. With
respect to Port S, the output signal on line PS7 may be controlled by Timer t while Timer 2 may be programmed to count

Register
Number

Rs3

0

0

0

0

RSCodlng
Rs2
Rs1

Table 1.

R65C22 Register Addressing

RsO

Register
Osslg.

0

ORB/IRB

Write (RiW - L)
Output Register B
Output Register A

R~8ter/Descrlptlon

I

I
I

Read(RIW
Input Register B

H)

1

0

0

0

1

ORA/IRA

2

0

0

1

0

DDRB

3
4

0

0
1

1

1

0

0

DORA
T1C-L

5

0

1

0

0
1

6
7
8
9

0

1

1

0

T1C-H
T1L-L

0

1

1

1

T1L-H

T1 High-Order Latches

1

0

0

T2C-L

0
0

0
1

T2 Low-Order Latches
1 T2 Low-Order Counter
T2 High-Order Counter

10

1
1

0
1
0

SR

11

1

0

1

1

ACR

Auxiliary Control Register

T2C-H

Input Register A

Data Direction Register B
Data Direction Register A
Tl Low-Order Latches
I Tl Low-Order Counter
Tl High-Order Counter
Tl Low-Order Latches

I
Shift Register

12

1

1

0

0

PCR

Peripheral Control Register

13

1

1

0

1

IFR

14

1

1

1

0

IER

Interrupt Flag Register
Interrupt Enable Register

15

1

1

1

1

ORA/IRA

Output Register B'

1

Input Register B'

NOTE: 'Same as Register 1 except no handshake.

+5V

':t
~

I/O
CONTROL

P

PAO-PA7,
CA2

OUTPUT
DATA

I/O
CONTROL

0

oN

DATA
INPUT
(OUTPUT MODE)
INPUT

Figure 2_

_-----I

'::L

-=-

INPUT (INPUT MODE)

Port A Output Circuit

Figure 3.

2-256

Port B Output Circuit

PBO-PB7,
CS1, CS2

R65C22

Versatile Interface Adapter (VIA)

FUNCTIONAL

PORT A AND
The R65C22 VIA ~_
Port B) and eachEach a-bit periphe,··
DDRB) for specify,
inputs or outputs. ,
causes the corresp
causes the pin to

Reading a peripheral port causes the contents of the Input
Register (IRA, IRB) to be transferred onto the Data Bus. With
input latching disabled, IRA will always reflect the levels on the
PA pins. With input latching enabled, IRA will reflect the levels
on the PA pins at the time the latching occurred (via CAl).

VIA is illustrated in

The internal org.
Figure 4.

.

,

,~"

,"

.~~

.,1.

• l' ' (-,

. ,I/O ports (Port A and
·d control lines.

The IRB register operates similar to the IRA register. However,
for pins programmed as outputs there is a difference. When
reading IRA, the level on the pin determines whether a "0" or
a "1" is sensed. When reading IRB, however, the bit stored in
the output register, ORB, IS the bit sensed. Thus, for outputs
which have large loading effects and which pull an output "1"
down or which pull an output "0" up, reading IRA may result
in reading a "0" when a "1" was actually programmed, and
reading a "1" when a "0" was programmed. Reading IRB, on
the other hand, will read the" 1" or "0" level actually programmed, no matter what the loading on the pin.

',." lction Register (DORA,
' i eral pins are to act as
3ta Direction Register
, J act as an input. A "1"

Each peripheral pc
:Jy a bit in the Output
Register (ORA, OP
,gister (IRA, IRB). When
the pin is prograF
,:; " .:
the voltage on the pin is
controlled by the cor
the Output Register. A "1"
in the Output Regist!j,
.:Ie output to go high, and a "0"
causes the output to go lOW. Data may be written into Output
Register bits corresponding to pins which are programmed as
inputs. In this case, however, the output signal is unaffected.

Figures 5 through a illustrate the formats of the port registers.
In addition, the input latching modes selected by the Auxiliary
Control Register are shown in Figure 14.

r-------------------------------- IRQ

INTERRUPT
CONTROL
FLAGS
(IFR)

INPUT LATCH
(IRA)
OUTPUT
(ORA)

---------

-EN-ABLe(IER)
DATA
BUS

PORT A

-DATA-off:!-

DATA
BUS
BUFFERS

(DORA)

PORT A

1-----------------CA1
CA2

-------- 1------,
PORT B
LATCH
(Tt L-H)

RES

LATCH
(Tt L-L)

COUN'TERTCC)UNTER

RtW

02

CS1
CS2
RSO RS1
RS2
RS3

:
:

(TtC-H)
CHIP
ACCESS
CONTROL

HANDSHAKE
CONTROL

rsS~H~IFryT~RUE~Gll-----J-L------

__ CB1
L...:(~S!:!1R)~j---~---- CB2

: (TtC-L)

TIMER 1

OUTPUT
(ORB)

-oATA-i)iFI
(DDRB)

Figure 4.

R65C22 VIA Block Diagram

2-257

BUFFERS
(PB)

PORT B

fI

Versatile Interface Adapter (VIA)

R65C22
HANDSHAKE CONTROL OF DATA TRANSFERS

port. This signal normally interrupts the processor, which then
reads the data, causing generatl'on of a "Data Taken" signal.
The peripheral device responds by making new data available.
This process continues until the data transfer is complete.

The R65C22 allows positive control of data transfers between
the system processor and peripheral devices through the operation of "handshake" lines. Port A lines (CAt, CA2) handshake
data on both a read and a write operation while the Port B lines
(CB1, CB2) handshake on a write operation only.

In the R65C22, automatic "Read" Handshaking is possible on
the Peripheral A port only. The CA 1 interrupt input pin accepts
the "Data Ready" signal and CA2 generates the "Data Taken"
signal. The "Data Ready" signal will set an internal flag which
may interrupt the processor or which may be polled under program control. The "Data Taken" signal can either be a pulse
or a level which is set low by the system processor and is cleared
by the "Data Ready" signal. These options are shown in Figure 9
which illustrates the normal Read Handshake sequence.

Read Handshake
Positive control of data transfers from peripheral devices into
the system processor can be accomplished very effectively using
Read Handshaking. In this case, the peripheral device must
generate the equivalent of a "Data Ready" signal to the
processor signifying that valid data is present on the peripheral

REG O-ORB/IRB

REG I-ORA/IRA

PBO

PAO

PB,
PA'
PB'
'-----PB'
' - - - - - - PB'
' -_ _ _ _ _ PB5

OUTPUT REGISTER
"B" (ORB) OR
INPUT REGISTER
"B" (IRB)

,.,
'-----PA'
' - - - - - - PA.
'-------PA.

L--_ _ _ _ _ _ PB_

L-_____________

' -_ _ _ _ _ _ _ PB]

PlN
DATA DIRECTION

P.,

OUTPUT REGISTER
"A" (ORA) OR
INPUT REGISTER
"A" (IRA)

L-___________ PA'

PlN

READ

WAITE

DATA DIRECTION
SELECTION

SELECTION
DORS = "1" (OUTPUT)

MPU WRITES OUTPUT lEVEL

OORB .. "0" (INPUT)
(INPUT LATCHING DISABLED)

MPU WRITES INTO ORB, BUT

(ORB)

MPU READS OUTPUT REGISTER
BIT IN-ORB PIN LEVEL HAS NO
AFFECT

NO EFFECT ON PIN lEVEL,
UNTil DORB CHANGED

DDRB = "0" (INPUT)
(INPUT LATCHING ENABLED)

"All

WAITE

DOFIA.. "1"(O~UT)
(INPUT LATCHING DISABLED)

MPU WAITES OUTPUT LEVEL
(OAA)

DOFIA. • "1" (OUTPUT)
(INPUT LATCHING ENABLED)

MPU READS INPUT LEVEL ON P8
PlN

MPU READS IRBBIT, WHICH IS THE
LEVEL OF THE PB PIN AT THE TIME
OF THE LAST cel ACTIVE
TRANSITION

DDAA • "0" (INPUT)
(INPUT LATCHING DISABLED)

MPU AEADS IAA BIT WHICH IS THE
LEVEL OFTHE PA PIN AT THE TIME
OF THE LAST CAl ACTIVE
TAANSITION
MPU WAITES INTO OAA, BUT
NO EFFECT ON PIN LEVEL,
UNTIL DDAA CHANGED

Output Register B (ORB), Input Register B (IRB)
Figure 6.

MPU AE.A.DS LEVEL ON PA PIN

MPU AE ....DS IAA BIT, WHICH IS THE
LEVELOFTHE FlA PIN AT THE TIME
OF THE LAST CAl ACTIVE
TR ....NSITION

DORA· "0" (INPUT)
(INPUT LATCHING ENA.BLED)

Figure 5.

MPU AEADS LEVEL ON PA PIN

Output Register A (ORA), Input Register A (IRA)

REG 2-DDRB

REG3-DDRA

1,1_1+ 1,1,1,1 1

E
0

PAO

l==PBO
PBl

PAl

PB'

PA'

PB3

I

L . . . l-

-

-

-

-

PB4",PA4

DATA DIRECTION
REGISTER "B" (DDRB)

PA'
PA.

PBS'PA5

PA5

' -_ _ _ _ _ _ _ PB6,PA6

PA'

L . . . ._ _ _ _ _ _

' -_ _ _ _ _ _ _ _ PB7,'PA7

"0"
"1"

PAl
"0"

ASSOCIATED PB PIN IS AN INPUT
(HIGH IMPEDANCE)
ASSOCIATED PB PIN IS AN OUTPUT
WHOSE LEVEL IS DETERMINED BY
ORB REGISTER BIT

Figure 7.

DATA DIRECTION
REGISTER "A" (DORA)

"1"

ASSOCIATED PA PIN IS AN INPUT
(HIGH IMPEDANCE)
ASSOCIATED PA PIN IS AN OUTPUT
WHOSE LEVEL IS DETERMINED BY
ORA REGISTER BIT

Figure 8.

Data Direction Register B (DDRB)

2-258

Data Direction Register A (DORA)

Versatile Interface Adapter (VIA)

R65C22

02 .JL..J'"'LJl...1~...JL..SL....JL

~~~ ..'"'

\ ~ I I •

~I---

I

II

II

~"
RII
!--+---

I

IRQ OUTPUT

I

IF

READ IRA OPERATION
"DATA TAKEN"
HANDSHAKE MODE
(CA2)
"DATA TAKEN"
PULSE MODE
(CA2)

I

~

~

II

I

II

~

Figure 9.

....- - -

PI

1_ _ _- - '

1/ _ _ _ _ _ __

Read Handshake Timing (Port A Only)

Write Handshake
REG l2-PERIPHERAL CONTROL REGISTER

The sequence of operations which allows handshaking data from
the system processor to a peripheral device is very similar to
that described for Read Handshaking. However, for Write Handshaking, the R65C22 generates the "Data Ready" signal and
the peripheral device must respond with the "Data Taken"
signal. This can be accomplished on both the PA port and the
PB port on the R65C22. CA2 or CB2 act as a "Data Ready"
output in either the handshake mode or pulse mode and CA 1
or CB1 accept the "Data Taken" signal from the peripheral
device, setting the interrupt flag and clearing the "Data Ready"
output. This sequence is shown in Figure 10.

I' j6J'J '1'1' , 10 1
, 6,
o
o

CB2CONTROL

~ ~CA' ,"TERRUPT

OPERATION
0 0 INPUT NEGATIVE ACTIVE EDGE
0 , INDEPENDENT INTERRUPT
INPUT NEGATIVE EDGE'

o ,
o ,

0 INPUT POSITIVE ACTIVE EDGE
INDEPENDENT INTERRUPT

,

INPUT POSITIVE EDGE·

, 0 0
, 0 , ~~:"s~S~~~:U~UTPU!~
, 0 LOW OUTPUT

,, ,

I

0 • NEGA liVE ACTIVe EDGE
l ' POSITIVE ACTIVE E~GE

Selection of operating modes for CA1, CA2, CB1, and CB2
is accomplished by the Peripheral Control Register
(Figure 11).

,,

1 OPERATION

o
o

0
0

~ r+~~~!ENNE;E~T;~!T~~T~~:TEDGE

o ,
o ,

~ :~~~!;~~~T~~~N;~

INPUT POSITIVE EDGe'
1 0 0 HANDSHAK E OUTPUT

I

, 0 1 PULSE OUTPUT

,
,

1 0

LOW OUTPUT

1 1 tHiGH OUTPUT

'SEE NOTE IN FIGURE 29

Figure 11.

Peripheral Control Register (PCR)

I/--l
I/=+=i=

02~1I~1I~

~

WRITE ORA, ORB
OPERATION
--I

~

~II

l..---

"DATA READY"
HANDSHAKE
MODE
I
II____~
(CA2, CB2)
DATA READY - - - - ,
,.....-11-1----+------11
PULSE MODE
"---'
~~~~
1/
1/
"DATA TAKEN
(CA1, CB1)
«
IRQ OUTPUT - - - - - - - - - , 1 ' 1 - 1
II _ _ _ _

I

fZ"Z/Z/Z"Z"Z2Z2l

----""L______

Figure 10.

Write Handshake Timing

2-259

I

CA2CONTROl

INPUT NEGATIVE EDGe·

1 HIGH OUTPUT

CSI INTERRUPT CONTROL

CON7ROL

0 0 NEGATIVE ACTIVE EDGE
1 - POSIT(VE ACTIVE EDGE

I
I

I

---Jr-

--

Versatile Interface Adapter (VIA)

R65C22
COUNTER/TIMERS

disables any further interrupts and automatically transfers the
contents of the latches into the counter and continues to decrement. In addition, the timer may be programmed to invert the
output signal on peripheral pin PB7 each time it "times-out".
Each of these modes is discussed separately below.

There are two independent 16-bit counter/timers (called Timer 1
and Timer 2) in the R65C22. Each timer is controlled by writing
bits into the Auxiliary Control Register (ACR) to select the mode
of operation (Figure 14).

Note that the processor does not write directly into the low-order
counter (Tl Col). Instead, this half of the counter is loaded
automatically from the low order latch (Tl L-L) when the
processor writes into the high order counter (Tl C-H). In fact, It
may not be necessary to write to the low order counter in some
applications since the timing operation is triggered by writing
to the high order latch.

Timer 1 Operation
Interval Timer Tl consists of two S-bit latches (Figure 12) and
a 16-bit counter (Figure 13). The latches store data which is to
be loaded into the counter. After loading, the counter decrements
at 02 clock rate. Upon reaching zero, an interrupt flag is set,
and IRQ goes low if the T1 interrupt is enabled. Timer 1 then

REG 7-TIMER 1 HIGH-ORDER LATCH

REG 6-TIMER 1 LOW-ORDER LATCH

1'16JsJ<]3J'l,J oj

]7]+]+1'1'1 1
0

~:.

~!~~

COUNT
VALUE

3'64

COUNT
VALUE

16384

32768

'28

WAITE - 8 BITS LOADED INTO T1 HIGH·OADER
LATCHES UNLIKE REG 4 OPERATION
NO LATCH·TO-COUNTER TRANSFERS
TAKE PL.ACE
READ _ 8 BITS FROM T1 HIGH·ORDER LATCHES
TRANSFERRED TO MPU

WAITE - 8 BITS LOADED INTO T1 LOW-ORDER
LATCHES THIS OPeRATION IS NO
DIFFERENT THAN A WRITE INTO
REG 4
READ - 8 BITS FROM T1 LOW·ORDER LATCHES
TRANSFERRED TO MPU UNLIKE REG 4
OPERATION, THIS DOES NOT CAUSE
RESET OF T1 INTERRUPT FLAG

Figure 12.

Timer 1 (T1) Latch Registers

REG 4-TIMER 1 LOW-ORDER COUNTER

REG 5-TIMER 1 HIGH-ORDER COUNTER

1'16\s\41 3I'\' \01

\,\61+1 311'1 1
2

~t

0

I
~:

1024

COUNT
VALUE

2U48
4096

64

8192

'28

3276B

16384

WAITE - 8 BITS LOADED INTO T1 LOW·ORDER
LATCHES LATCH CONTENTS ARE
TRANSFERRED INTO LOW-ORDER
COUNTER AT THE TIME THE HIGHORDER COUNTER IS LOADED (REG 5)
READ - 8 BITS FROM T1 LOW-ORDER COUNTER
TRANSFERRED TO MPU IN ADDITION,
T1 INTERRUPT FLAG IS RESET (BIT 6
IN INTERRUPT FLAG REGISTER)

Figure 13.

WRITE - 8 BITS LOADED INTO T1 HIGH-ORDER
LATCHES ALSO, AT THIS TIME BOTH
HIGH- AND LOW-ORDER LATCHES ARE
TRANSFERRED INTO T1 COUNTER
T1 INTERRUPT FLAG ALSO IS RESET
READ - 8 BITS FROM T1 HIGH-ORDER COUNTER
TRANSFERRED TO MPU

Timer 1 (T1) Counter Registers

2-260

COUNT
VALUE

Versatile Interface Adapter (VIA)

R65C22
REG II-AUXILIARY CONTROL REGISTER

I'1
T1 TIMER CONTROL

o'

OPERATION

6
0 TIMED INTERRUPT

6J

T
PB'

EACH TIME T1 IS

L

5J

'-.l'l'J ~

0

'"2

SHIFT OUT UNDER CONTROL Of EXT elK

Auxiliary Control Register (ACR)

Timer 1 One-Shot Mode

In the one-shot mode, writing into the Tl L-H has no effect on
the operation of Timer I. However, it will be necessary to assure
that the low order latch contains the proper data before initiating
the count-down with a "write Tl C-H" operation. When the processor writes into the high order counter (Tl C-H), the T1 interrupt flag will be cleared, the contents of the low order latch will
be transferred into the low order counter, and the timer will begin
to decrement at system clock rate. If the PB7 output is enabled,
this signal will go low on the 02 following the write operation.
When the counter reaches zero, the Tl interrupt flag will be set,
the IRQ pin will go low (interrupt enabled), and the signal on
PB7 will go high. At this time the counter will continue to decrement at system clock rate. This allows the system processor to
read the contents of the counter to determine the time since
interrupt. However, the Tl interrupt flag cannot be set again
unless it has been cleared as described in this specification.

The Timer lone-shot mode generates a single interrupt for each
timer load operation. As with any interval timer, the delay
between the "write T1 C-H" operation and generation of the processor interrupt is a direct function of the data loaded into the
timing counter. In addition to generating a single interrupt,
Timer 1 can be programmed to produce a Single negative pulse
on the PB7 peripheral pin. With the output enabled (ACR7 1)
a "write T1C-H" operation will cause PB7 to go low. PB7 will
return high when Timer 1 times out. The result is a single programmable width pulse.

=

Timing for the R65C22 interval timer one-shot modes IS shown
in Figure 15.

1/)2

I

WRITE TtC-H

I

--rI

;/

}I'

IRQ OUTPUT

PB7 OUTPUT
Tl COUNTER

I

I

l" .~~'

N-3

I

,'I'
0

I

N + 1.5 CYCLES

FFFF

N

N-l

I

N-2

I

.1

L -_ _ _ _ . _ _ _ _ . _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Figure 15.

Timer 1 One-Shot Mode Timing

2-261

~

Versatile Interface Adapter (VIA)

R65C22
Timer 1 Free-Run Mode

the time-out can be prevented completely if the processor continues to rewrite the timer before it reaches zero. Timer 1 will
operate in this manner if the processor writes into the high order
counter (T1C-H). However, by loading the latches only, the
processor can access the timer during each down-counting
operation without affecting the time-out in process. Instead, the
data loaded into the latches will determine the length of the next
time-out period. This capability is particularly valuable in the freerunning mode with the output enabled. In this mode, the signal
on PB7 is inverted and the interrupt flag is set with each timeout. By responding to the interrupts with new data for the latches,
the processor can determine the period of the next half cycle
during each half cycle of the output signal on PB7. In this manner,
very complex waveforms can be generated.

The most important advantage associated with the latches in T1
is the ability to produce a continuous series of evenly spaced
interrupts and the ability to produce a square wave on PB7 whose
frequency is not affected by variations in the processor interrupt
response time. This is accomplished in the "free-running" mode.
In the free·running mode, the interrupt flag is set and the signal
on PB7 is inverted each time the counter reaches zero at which
time the timer automatically transfers the contents of the latch
into the counter (16 bits) and continues to decrement from there.
The interrupt flag can be cleared by writing T1C-H, by reading
T1C-L, or by writing directly into the flag as described later.
However, it is not necessary to rewrite the timer to enable setting the interrupt flag on the next time-out.

A precaution to take in the use of PB7 as the timer output concerns the Data Direction Register contents for PB7. Both DDRB
bit 7 and ACR bit 7 must be 1 for PB7 to function as the timer
output. If one is 1 and other is 0, then PB7 functions as a normal outpin pin, controlled by ORB bit 7.

All interval timers in the R65C22 are "re-triggerable". Rewriting
the counter will always re-initialize the time-out period. In fact,

\12

.J"L.Sl--IL..r

~

~:~~~~I~~H ~
({
I
'00 0""'",
I ,,':-~(
----i._____-li;f-,'----i...___
PB7 OUTPUT

- - - - - - ,'---i!~( _ _ _ _ _..,Jr-------r'/I~(- - - - - . ,L._ _ __

I---

N + 1.5 CYCLES

-~.+I~.--- N

+ 2 CYCLES

-----1.1

Figure 16. Timer 1 Free-Run Mode Timing

Timer 2 Operation

decrementing again through zero. The processor must rewrite
T2C-H to enable setting of the interrupt flag. The interrupt flag
is cleared by reading T2C-L or by writing T2C-H. Timing for this
operation is shown in Figure 18.

Timer 2 operates as an interval timer in the "one-slot" mode only),
or as a counter for counting negative pulses on the PB6
peripheral pin. A single control bit in the Auxiliary Control Register
selects between these two modes. This timer is comprised of
a "write-only" lower-order latch (T2L-L), a "read-only" low-order
counter (T2C-L) and a read/write high order counter (T2C-H). The
counter registers act as a 16-bit counter which decrements at
02 rate. Figure 17 illustrates the T2 Latch/Counter Registers.

Timer 2 Pulse Counting Mode
In the pulse counting mode, T2 counts a predetermined number
of negative-going pulses on PB6. This is accomplished by first
loading a number into T2. Writing into T2C-H clears the interrupt flag and allows the counter to decrement each time a pulse
is applied to PB6. The interrupt flag is set when T2 counts down
past zero. The counter will then continue to decrement with each
pulse on PB6. However, it is necessary to rewrite T2C-H to allow
the interrupt flag to set on a subsequent time-out. Timing for this
mode is shown in Figure 19. The pulse must be low on the leading
edge of 02.

Timer 2 One-Shot Mode
As an interval timer, T2 operates in the "one-shot" mode similar
to Timer 1. In this mode, T2 provides a single interrupt for each
"write T2C-H" operation. After timing out, the counter will continue to decrement. However, setting of the interrupt flag is disabled after initial time-out so that it will not be set by the counter

2-262

Versatile Interface Adapter (VIA)

R65C22

REG 9-TIMER 2 HIGH·ORDER LATCH/COUNTER

REG 8-TIMER 2 LOW·ORDER LATCH/COUNTER

,..
512

+

1024

COUNT
VALUE

' -_ _ _ _ 16

COUNT
VALUE

2048
4096

' -_ _ _ _ _ 32
8192

' -_ _ _ _ _ _ 6.
16384

'--------128

32768

WRITE _

8 BITS LOADED INTO T2 LOW ORDER
LATCH

READ _

8 BITS FROM T2 LOW ORDER COUNTER

WRITE -

8 BITS LOADED INTO T"!: HIGH ORDER

COUNTER ALSO,lOW ORDER LATCH
TAANSFERRED TO LOW ORDER

COUNTER IN ADDITION, 12 INTERRUPT
FLAG IS AESET

TRANSFERRED TO MPU T2INTERRUPT
FLAG IS RESET
READ -

8 BITS FROM T2 HIGH ORDEA COUNTER
TRANSFERRED TO MPU

Figure 17.

Timer 2 (T2) Latch/Counter Registers

WRITE T2C·H

/

IRQ OUTPUT

T2 COUNTER

N

I

N·l

N·2

I

N·3

o

I

1 - - - - - - - N + 1.5 CYCLES

Figure 18.

FFFF

I

FFFE

I

FFFD

I

FFFC

------.~I

Timer 2 One·Shot Mode Timing

WRITE T2C·H
r:
OPERATiON ----I
I'-_ _ _ _ _ _ _ _ _ _ _ _ _~/'I-'-------------

U'----,U,---I/,I-'--'U'------

PB6 INPUT - - - - - -....

IRQ OUTPUT -------------------~;',;..I--------:
T2 COUNTER

N

Figure 19.

N·1

N·2

Timer 2 Pulse Counting Mode

2·263

o

_____
FFFF

I

Versatile Interface Adapter (VIA)

R65C22
SHIFT REGISTER OPERATION

of this output clock is a function of the system clock period and
the contents of the low order 1"2 latch (N).

The Shift Register (SR) performs serial data transfers into and
out of the CB2 pin under control of an internal modul0-8 counter.
Shift pulses can be applied to the CB1 pin from an external
source or, with the proper mode selection, shift pulses generated
internally will appear on the CB1 pin for controlling external
devices.

The shifting operation is triggered by the read or write of the SR
if the SR flag is set in the IFR. Otherwise the first shift will occur
at the next time-out of 1"2 after a read or write of the SA. Data
is shifted first Into the low order bit of SR and is then shifted into
the next higher order bit of the shift register on the negative.going
edge of each clock pulse. The input data should change before
the positive-going edge of CB1 clock pulse. This data is shifted
into the shift register during the 02 clock cycle following the
positive-going edge of the CB1 clock pulse. After 8 CB1 clock
pulses, the shift register interrupt flag will set and IRQ will go low.

The control bits which select the various shift register operating
modes are located in the Auxiliary Control Register. Figure 20
illustrates the configuration of the SR data bits and Figure 21
shows the SR control bits of the ACA.

SR Mode 0 - Disabled

SR Mode 2 - Shift In Under 02 Control

Mode 0 disables the Shift Register. In this mode the microprocessor can write or read the SR and the SR will shift on each
CB1 positive edge shifting in the value on CB2. In this mode
the SR interrupt Flag is disabled (held to a logic 0).

In mode 2, the shift rate is a direct function of the system clock
frequency (Figure 23). CB1 becomes an output which generates
shift pulses for controlling external devices. Timer 2 operates
as an independent interval timer and has no effect on SA. The
shifting operation is triggered by reading or writing the Shift
Register. Data is shifted, first into bit 0 and is then shifted into
the next higher order bit of the shift register on the trailng edge
of each 02 clock pulse. After 8 clock pulses, the shift register
interrupt flag will be set, and the output clock pulses on CB1
will stop.

SR Mode 1 - Shift In Under Control of T2
In mode 1, the shifting rate is controlled by the low order 8 bits
of 1"2 (Figure 22). Shift pulses are generated on the CB1 pin to
control shifting in external devices. The time between transitions

REG 11-AUXILIARY CONTROL REGISTER

1'1_1 1_1+1+1
5

l.LL

SHIFT
REGISTER
BITS

L

SHIFT REGISTER
MODE CONTROL

_
3
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

NOTES
1 WHEN SHIFTING OUT, BIT 718 THE FIRST BIT

OUT AND SIMULTANEOUSLY IS ROTATED BACK
INTO BITO
2 WHEN SHIFTING IN. BITS INITIALLY ENTER
BIT 0 AND ARE SHIFTED TOWARDS BIT 7

2
0
1
0
1
0
1
0
1

OPERATION
DISABLED
SHIFT IN UNDER CONTROL OF T2
SHIFT IN UNDER CONTROL OF 02

SHIFT IN UNDER CONTROL OF EXT elK
SHIFT OUT FREE RUNNING AT T2 RATE
SHIFT OUT UNDER CONTROL OF T2
SHIFT OUT UNDER CONTROL OF 02

SHIFT OUT UNDER CONTROL OF EXT eLK

Figure 21. Shift Register Modes

Figure 20. Shift Registers

WRITE OR READ
SHIFT REG

Figure 22. SR Mode 1 - Shift In Under 1"2 Control

2-264

Versatile Interface Adapter (VIA)

R65C22

set by T2. However, in mode 4 the SR Counter does not stop
the shifting operation (Figure 25). Since the Shift Register bit 7
(SR7) is recirculated back into bit 0, the 8 bits loaded into the
shift register will be clocked onto CB2 repetitively. In this mode
the shift register counter is disabled.

SR Mode 3 - Shift In Under CB1 Control
In mode 3, external pin CB1 becomes an input (Figure 24). This
allows an external device to load the shift register at its own pace.
The shift register counter will Interrupt the processor each time
8 bits have been shifted in. The shift register stops after 8 counts
and must be reset to start again. Reading or writing the Shift
Register resets the Interrupt Flag and initializes the SR counter
to count another 8 pulses.

SR Mode 5 -

Note that the data is shifted during the first system clock cycle
following the positive-going edge of the CB1 shift pulse. For this
reason, data must be held stable during the first full cycle following CB1 going high.

SR Mode 4 - Shift Out Under 12 Control (Free-Run)
Mode 4 Is very similar to mode 5 in which the shifting rate is

READSR--1l
CB10UTPUT
SHIFT CLOCK

Shift Out Under 12 Control

In mode 5, the shift rate is controlled by T2 (as in mode 4). The
shifting operation Is triggered by the read or write of the SR If
the SR flag Is set in the IFR (Figure 28). Otherwise the first shift
will occur at the next time-out of T2 after a read or write of the
SR. However, with each read or write of the shift register the SR
Counter Is reset and 8 bits are shifted onto CB2. At the same
time, 8 shift pulses are generated on CB1 to control shifting in
external devices. After the 8 shift pulses, the shifting Is disabled,
the SR Interrupt Flag is set and CB2 remains at the last data level.

~

I

~----------

C B 2
2I3N
4
5
P
6
7
8U T .
1
1 DATA
IRQ
~I

Figure 23.

_________________

SR Mode 2 - Shift In Under .2 Control

CB2INPUT~~~~CJ~~~~J2~~~~J3~~~~J4[J~/~ ~
DATA

:

~

I

L
Figure 24.

I I
WRITESR~

SR Mode 3 - Shift In Under CB1 Control

I

-+-....j....-+-+-----

N + 2 CyC...
LE-S...Ij.I-.:::;:::j':':"'"-::I---+-.......

CB1 OUTPUT
SHIFT CLOCK

------I

XXXXXXXXXXXXXX.....____ X

CB2
DATAINPUT _

J. .

2

X

3

Figure 25. SR Mode 4 - Shift Our Under T2 Control (Free-Run)

2-265

8

x::::r::

2

Versatile Interface Adapter (VIA)

R65C22
SR Mode 6 - Shift Out Under 02 Control

Interrupt Flag each time it counts 8 pulses but it does not disable
the shifting function. Each time the microprocessor, writes or
reads the shift register, the SR Interrupt Flag is reset and the
SR counter is initialized to begin counting the next 8 shift pulses
on pin CBt After 8 shift pulses, the Interrupt Flag is set. The
microprocessor can then load the shift register with the next byte
of data.

In mode 6, the shift rate is controlled by the 1/12 system clock
(Figure 27).

SR Mode 7 - Shift Out Under CB1 Control
In mode 7, shifting is controlled by pulses applied to the CBl
pin by an external device (Figure 28). The SR counter sets the SR

WRITE SR

*==+ =*

N + 2 CYCLES

CBl OUTPUT
SHIFT CLOCK

I ..I

I

--r-l.......L
I
I
I

+ 2 CYC~ES
1-1- - - i
i----i

I
•

_

1

2

I

I

, ( l f U U l J l - ,

J

3'

1

(--i
M
_.

8

....
' ---

~:~~UTPUT XXXXXXXXXXXXXXX...__....;..._...JXI..._.......::2:......_...IX..._~3_-I1 P........;8~t--_ _

Figure 26.

SR Mode 5 - Shift Out Under 12 Control

~

~IIIII

WRITESR
CB10UTPUT
SHIFT CLOCK
CB2 OUTPUT
DATA

-------LJ--i.J--LJ---L~

mxxxxxxxxxxxxx=too=x I

8

I
Figure 27.

SR Mode 6 - Shift Out Under .2 Control

J-u-u-Lru-L

WRITESR
CBl INPUT
SHIFT CLOCK
CB2 OUTPUT
DATA

~~--------------------~r--~-----1
2

..._ _...

OOOOOOOOOOOOOOO,.---......,----""'X

Figure 28.

2

SR Mode 7 - Shift Out Under CBl Control

2-266

Versatile Interface Adapter (VIA)

R65C22

function: IRQ = IFR6 x IER6 + IFR5 x IER5 + IFR4 x IER4
+ IFR3 x IER3 + IFR2 x IER2 + IFR1 x iER1 + IFRO x
IERO.

Interrupt Operation
Controlling interrupts within the R65C22 involves three principal
operations. These are flagging the interrupts, enabling interrupts
and signaling to the processor that an active interrupts exists
within the Chip. Interrupt flags are set in the Interrupt Flag
Register (IFR) by conditions detected within the R65C22 or on
inputs to the R65C22. These flags normally remain set until the
interrupt has been serviced. To determine the source of an interrupt, the microprocessor must examine these flags in order, from
highest to lowest priority.

Note:

x = logic AND, + = Logic OR.
The IFR bit 7 is not a flag. Therefore, this bit is not directly cleared
by writing a logiC 1 into it. It can only be cleared by clearing all
the flags in the register or by disabling all the active interrupts
as discussed in the next section.

Associated with each interrupt flag is an interrupt enable bit in
the Interrupt Enable Register (IER). This can be set or cleared
by the processor to enable interrupting the processor from the
corresponding interrupt flag. If an interrupt flag is set to a logic 1
by an interrupting condition, and the corresponding inte~t
enable bit is set to a 1, the Interrupt Request Output (IRQ)
will go low. IRQ is an "open-collector" output which can be
"wire-OR'ed" with other devices in the system to interrupt the
processor.

Interrupt Enable Register (IER)
For each interrupt flag in IFR, there is a corresponding bit in the
Interrupt Enable Register (IER) (Figure 30). Individual bits in the
IER can be set or cleared to facilitate controlling individual interrupts without affecting others. This is accomplished by writing
to the (IER) after bit 7 set or cleared to, in turn, set or clear
selected enable bits. If bit 7 of the data placed on the system
data bus during this write operation is a 0, each 1 in bits 6 through
o clears the corresponding bit in the Interrupt Enable Register.
For each zero in bits 6 through 0, the corresponding bit is
unaffected.

Interrupt Flag Register (IRF)
In the R65C22, all the interrupt flags are contained in one register,
i.e., the IFR (Figure 29). In addition, bit 7 of this register will be
read as a logic 1 when an interrupt exists within'the chip. This
allows very convenient polling of several devices within a system
to locate the source of an interrupt.

Selected bits in the IER can be set by writing to the IER with
bit 7 in the data word set to a 1. In this case, each 1 in bits 6
through 0 will set the corresponding bit. For each zero, the corresponding bit will be unaffected. This individual control of the
setting and clearing operations allows very convenient control
of the interrupts during system operation.

The Interrupt Flag Register (IRF) may be read directly by the processor. In addition, individual flag bits may be cleared by writing
a "1" into the appropriate bit of the IFR. When the proper chip
select and register signals are applied to the chip, the contents
of this register are placed on the data bus. Bit 7 indicates the
status of the IRQ output. This bit corresponds to the logic

In addition to setting and clearing IER bits, the contents of this
register can be read at any time. Bit 7 will be read as a logic 1,
however.

REG 13-INTERRUPT FLAG REGISTER

REG 14-INTERRUPT ENABLE REGISTER

1716151<13121'101

l, l

SET BY

CLEARED BY

CA2 CA2 ACTIVEEDGE

READ OR WRITE
REG 1 (ORAl·

CA1- CAt ACTIVE EOGE

READ OR WRITE
REG 1 (ORA

SHIFT REG

CB2
CB'
TIMER 2
TIMER 1

IRO

COMPLETE 8 SHIFTS

READ OR WRITE

CB2 ACTIVE EDGE

SHIFT REG
READ OR WRITE ORB·

81 ACTIVE EDGE

TIME DUT OF T2

REA OR

ITE

TIME OUT OF T1

READ T2 LOW OR
WRITE T2 HIGH
READ T1 LOW OR

ANV ENABLED
INTERRUPT

WRITE T1 HIGH
CLEAR ALL
INTERRUPTS

o = INTERRUPT
DISABLED

B

= INTERRUPT
ENABLED
'---------TlMER'

'----------SETfCLEAR
NOTES
, IF BIT 7 IS A "0", THEN EACH "'" IN BITS 0 - 6 DISABLES THE
CORRESPONDING INTERRUPT
2 IF BIT 7 IS A ",", THEN EACH "'" IN BITS 0 - 6 ENABLES THE
CORRESPONDING INTERRUPT
3 IF A READ OF THIS REGISTER IS DONE, BIT 7 Will BE "1" AND
ALL OTHER BITS WILL REFLECT THEIR ENABLE/DISABLE STATE

• IF THE CA2/CB2 CONTROL IN THE PCR IS SElECTED AS
"INDEPENDENT" INTERRUPT INPUT, THEN READING OR

WAITING THE OUTPUT REGISTER ORA/ORB Will NOT
CLEAR THE FLAG BIT INSTEAD, THE BIT MUST BE
CLEARED BY WRITING INTO THE IFR, AS DESCRIBED
PREVIOUSLY

Figure 29.

Figure 30.

Interrupt Flag Register (IFR)

2-267

Interrupt Enable Register (IER)

fI

Versatile Interface Adapter (VIA)

R65C22
PERIPHERAL INTERFACE CHARACTERISTICS
Symbol

Characteristic

t" t f

Rise and Fall Time for CA1, CB1, CA2 and CB2 Input Signals

tCA2

Delay Time, Clock Negative Transition to CA2 Negative Transition (read handshake
or pulse mode)

t RSt

Delay Time, Clock Negative Transition to CA2 Positive Transition (pulse mode)

tRS2

Delay Time, CA1 Active Transition to CA2 Positive Transition (handshake mode)

tWHs

Min.

Max.

Unit

-

1.0

!,s

Figure

-

1.0

!,s

31a,31b
31a

-

1.0

!,s

2.0

!'s

31b

Delay Time, Clock Positive Transition to CA2 or CB2 Negative Transition (write
handshake)

0.05

1.0

!,S

31c,31d

0.20

1.5

!,S

31c, 31d

-

1.0

!'s

310

2.0

!'s

31d

-

ns

31d

ns

31e

tDs

Delay Time, Periphral Data Valid to CB2 Negative Transition

t RS3

Delay Time, Clock Positive Transition to CA2 or CB2 Positive Transition (pulse mode)

t RS4

Delay Time, CA1 or CB1 Active Transition to CA2 or CB2 Positive Transition
(handshake mode)

t2t

Delay Time Required from CA2 Output to CA1 Active Transition (handshake mode)

400

tiL

Setup Time, Peripheral Data Valid to CA1 or CB1 Active Transition (input latching)

300

tAL

CA 1, CB 1 Setup Prior to Transition to Arm Latch

300

31e

Peripheral Data Hold After CA 1, CB1 Transition

150

-

ns

tpDH

ns

31e

tSRt

Shift·Out Delay Time -

-

300

ns

311

300

-

ns

31g

ns

31g

Time from

O2 Falling

Edge to CB2 Data Out

Time from CB2 Data In to O2 Rising Edge

tSR2

Shift·ln Setup Time -

tSR3

External Shift Clock (CB1) Setup Time Relative to O2 Trailing Edge

100

TCY

t lPW

Pulse Width -

PBS Input Pulse

2 x TCY

-

31i

t lCW

Pulse Width -

CB1 Input Clock

2 x TCY

-

31h

tiPS

Pulse Spacing -

PBS Input Pulse

2 x TCY

tiCS

Pulse Spacing -

CB1 Input Pulse

2 x TCY

-

31h

Notes:
1. Vcc = 5.0Vdc ±5%
2. TA = TL to T H

2-268

31i

R65C22

Versatile Interface Adapter (VIA)

PERIPHERAL INTERFACE WAVEFORMS
1/)2

READ IRA
OPERATION

CA2
"DATA TAKEN"

Figure 31a.

CA2 Timing for Read Handshake, Pulse Mode

1/)2

READ IRA
OPERATION

t

CA2
"DATA TAKEN"

ICA2

j~o.sv

r'OV

--------~~'--------------

>f'RS2

CA 1
",::
"DATA R E A D Y " . !

----------------------------------------~i~-----

Figure 31b.

20·.OSVv

L

ACTIVE
TRANSITION

CA2 Timing for Read Handshake, Handshake Mode

1/)2

WRITE ORA, ORB
OPERATION

CA2, CB2
"DATA READY"

O.SV
•- - - I D S - - - - I

PA, PB
.
PERIPHERAL
DATA

.

Figure 31c.

2.0V

.

O.SV

F-----------------------------------------CA2, CB2 Timing for Write Handshake, Pulse Mode

2-269

R65C22

Versatile Interface Adapter (VIA)

WRITE ORA, ORB
OPERATION

PA, PB

J

!:":

CA2,CB2
"DATA READY"

\

~ 12.0V

O.8V

2.0V

tDS----..j.~

PERIPHERAL~
DATA
~O~.8~V---------------+~~t-21-___
---_
-----,tR-S-4-___
____
--+CAl, CBI
"DATA TAKEN"

.x.

---------------------------------------------~I4--~~J~~~------i
2.0V

---------------------------------------A-C-T-IV-E~I~'~=:J~~~O~.8~V--------TRANSITION

Figure 31d.

CA2, CB2 Timing for Write Handshake, Handshake Mode

PA,PB
_2.0V
PERIPHERAL
INPUT DATA
FO~.8~V_____________

r::=

tiL

----+~

~_ ____________- "

CAl, CBI
INPUT LATCHING ____________
CONTROL
.

_
1-----tAL - - - + I

Figure 31e.

ACTIVE
TRANSITION

Peripheral Data Input Latching Timing

CBI
SHIFT CLOCK
(INPUT OR
OUTPUT)

Figure 31f.

Timing for Shift Out with Internal or External Shift Clocking

2-270

Versatile Interface Adapter (VIA)

R65C22

SHIFT DATA
CB2
(INPUT)

~~~~~~~~

~;.;;.;..+-

____!-_+______________

CB1
SHIFT CLOCK
(INPUT OR
OUTPUT)
SET UP TIME MEASURED TO THE FIRST 02
RISING EDGE AFTER CB1 RISING EDGE.

Figure 31g.

Timing for Shift In with Internal or External Shift Clocking

,,,A~;·"

CB1
SHIFT CLOCK
INPUT

I,CW
Figure 31 h.

PB6
PULSE COUNT
INPUT

1''

------IJ l

-I,CS

External Shift Clock Timing

,.v~'"
I,PW ----+i~1lt------IIPS

I

COUNTER T2
DECREMENTS
HERE

Figure 311.

Pulse Count Input Timing

2-271

"}-

fJ

Versatile Interface Adapter (VIA)

R65C22
BUS TIMING CHARACTERISTICS

3 MHz

2 MHz

1 MHz
Parameter

4 MHz

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

tCY

1000

-

500

-

330

-

250

ns

Phase 2 Pulse Width High

tpWH

470

240

-

-

160

-

120

-

ns

Phase 2 Pulse Width Low

tpWL

470

240

-

160

-

120

-

ns

Phase 2 Transition

tR,F

-

30

-

30

-

30

ns

Select, RIW Setup

t ACR

160

-

45

-

ns

tCAR

0

-

65

Select, RIW Hold

0

-

0

-

ns

Data Bus Delay

tCOR

190

-

90

ns

Data Bus Hold

tHR

10

ns

Peripheral Data Setup

tpCR

300

-

Select RIW Setup

t ACW
tCAW

Data Bus Setup

tocw

195

Data Bus Hold

tHW

10

-

ns

Select, RIW Hold

Peripheral Dala Delay

tcpw

250

ns

Cycle Time

30

-

Unit

READ TIMING

-

-

90

320

-

0

-

150

160

-

0

-

130

-

110

90

-

65

0

-

0

10

10

-

10
75

ns

WRITE TIMING

-

1000

90
10

-

Notes:
1, VCC ~ 5.0 Vdc ±5%
2. TA ~ TL to TH

2-272

500

65
10

-

330

45
0
45
10

-

ns
ns
ns

Versatile Interface Adapter (VIA)

R65C22
BUS TIMING WAVEFORMS
Read Timing Waveforms

.2CLOCK
REGISTER
SELECTS,
CHIP
SELECTS,

R/W

~~i~~~

-+__-+_=~~~~i~II~I[

~__~_ _

PERIPHERAL
DATA

DATA BUS

----------0{

Write Timing Waveforms

-=!

ICY

- tPWH

112

I- tAcw

.J

CHIP SELECTS,
REGISTER SELECTS

2.0V

2.0V

/

CLOCK

--

-

2.0V

DATA
BUS

\

tCAw

I--

2.0V
O.BV

O.BV

R/W

2.0V

O.BV

tocw 2.0V

O.BV

~l

-

!--tHW

2.0V

O.BV

f.

t cpw 2.0V

PERIPHERAL
DATA

O.BV

2-273

Versatile Interface Adapter (VIA)

R65C22
ABSOWTE MAXIMUM RATINGS·
Symbol

Value

Unit

Supply Voltage

Parameter

Vee

-0.3 to -7.0

Vdc

Input Voltage

VIN

-0.3 to + 7.0

Vdc

Operating Temperature
Commercial
Industrial

TA

o to +70
-40 to +85

°C
°C

Storage Temperature

Tsm

-55to+150

°C

-NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

OPERATING CONDITIONS
Parameter

Value

Symbol

Supply Voltage

Vee

5V ±5%

Temperature Range
Commercial

TA

TL to TH
O°C to 70°C

DC CHARACTERISTICS
(Vee = 5.0 Vdc ±5%, VSS = 0, TA = TL to TH , unless otherwise noted)
Min.

Typ.3

Max.

Unit'

Input High Voltage

VIH

+2.0

-

Vee

V

Input Low Voltage

VIL

-0.3

-

+0.8

V

Input Leakage Current
RAN, RES, RSO, RS1, RS2, RS3,CS1, CS2,CA1, 02

liN

-

±1

±2.5

~A

VIN = OV to Vee
Vee = 5.25V

Input Leakage Current lor Three-State Off
00-007
Input High Current
PAO-PA7,CA2, PBO-PB7,CB1, CBS

ITSI

-

±2

±10

~A

VIN = O.4V to 2.4V
Vee = 5.25V

~A

VIN = 2.4V

Input Low Current
PAO-PA7, CA2, PBO-PB7, CB1,CB2

IlL

VIL = O.4V

Output High Voltage
All outputs
PBO-PB7, CB2 (Darlington Drive)

VOH

Output Low Voltage

VOL

Output High Current (Sourcing)
Logic
PBO-PB7, CB2 (Darlington Drive)

IOH

Output Low Current (Sinking)

IOL

3.2

-

Output Leakage Current (Off State)
IRQ

IOFF

-

1

±10

-

7

10

mW/MHz

-

10
7
20

pF
pF
pF

10

pF

Parameter

Symbol

IIH

-200

Power Dissipation

PD
CIN

Output Capacitance

COUT

-

-

-2

-3.2

mA

2.4
1.5

-

-

V
V

-

-

+0.4

V

-200
-3.2

Input Capacitance
RAN, RES, RSO, RS1, RS2, RS3, CS1, CS2,
DO-D7,PAO-PA7,CA1, CA2, PBO-PB7
CB1, CB2, 02

-400

-

-

Notes:
1. All units are direct current (DC) except lor capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values shown lor Vee = 5.0V and TA = 25°C.

2-274

-

-1500
-6

-

Test Conditions

Vee = 4.75V
iLOAD = 200 ~
ILOAD2 = - 3.2 mA
Vee = 4.75V
ILOAD = 3.2 mA
ILOAD = 1.6 mA

-

~
mA

VOH = 2.4V
VOH = 1.5V

-

mA

VOL = 0.4

~A

VOH = 2.4V
Vee = 5.25V

Vee = 5.0V
VIN = OV
1= 2 MHz
TA = 25/C

Versatile Interface Adapter (VIA)

R65C22
PACKAGE DIMENSIONS
4o-PIN CERAMIC DIP

MILLIMETERS
1M MIN MAX
A
5029 5131
1486 1562
B
254 419
C
038 053
D
F
076
140
G
254 esc
H
076
178
J
020 033
K
254 419
L
1460 1537
M
0
10'
051
N
152

INCHES
MAX
MIN
2020

'980
0585
0100
0015

0030
0100
0030
0008
0100
0575
0
0020

0615
0165
0021

0055

esc

0070
0013
0165

0.605
10

o oeo

40-PIN PLASTIC DIP

:;: : : : : ~::::::: ::p

,'i

~ffF=3+1_
.IGI----lf-F~D
tiM J_,

2-275

MILLIMETERS
INCHES
MAX
DIM MIN MAX
MIN
A
5128 5232 2040 2060
1372 1422 0540 0560
B
355 508 0140 0200
C
051 0014 0020
D
036
102
152 0040 0060
F
0100
254 sse
G
216 0065 0085
H
16\
020 030 0008 0012
J
K
305
356 0120 0140
1524 esc
0600
L
10
M
T
10'
7'
051
102 0020 0040
N

esc
esc

fJ

R65C24

'1'

Rockwell

R65C24
PERIPHERAL INTERFACE
ADAPTER/TIMER (PlAT)
PRELIMINARY

DESCRIPTION

FEATURES

The R65C24 Peripheral Interface Adapter/Timer (PlAT) is
designed to solve a broad range of peripheral control problems
in the implementation of microcomputer systems. This device
allows a very effective trade-off between software and hardware
by providing significant capabilny and flexibility in a low cost
chip. When coupled with the power and speed of the R6500,
R6500/* or R65COO family of microprocessors, the R65C24
allows implementation of very complex systems at a minimum
overall cost.

• Low power CMOS N-well silicon gate technology
• Two S-bit bidirectional VO ports with individual data direction
control
• Programmable 16-bit Counter/Timer with eight modes of
operation
• Three S-bit latches associated with the Counter/Timer
• Selectable divide-by-sixteen prescaler for all modes
• Automatic "Handshake" control of data transfers
• Two interrupts (one for each port) wnh program control
• 1, 2, 3, and 4 MHz versions
• Commercial and industrial temperature range versions
• 40-pin plastic and ceramic versions
• Single 5V ± 5% supply requirements
• Compatible with the R6500, R6500r and R65COO family of
microprocessors

Control of peripheral devices is handled primarily through two
S-bit bidirectional ports. Each of these lines can be programmed
to act as enher an input or an output. In addition, four peripheral
controVinterrupt input lines are provided. These lines can be
used to interrupt the processor or to "handshake" data between
the processor and a peripheral device.
The PlAT also contains one 16-bit Counter/Timer comprised of
a 16-bit counter, two S-bit latches associated with the counter,
and an S-bit snapshot latch for the upper half of the counter. A
counter mode control register, under software direction, selects
anyone of eight counter modes of operation, and the status
register contains an underflow flag to report counter time-out.
A maskable Interrupt request allows immediate CPU notification
upon counter time-out.

VSS

PAO
PA1
PA2
PA3
PA4
PAS
PAS
PA7
PBO
PB1
PB2
PB3
PB4
PBS
PBS
PB7
CB1
CB2

ORDERING INFORMATION
The R65C24 Is available in both a ceramic and a plastic 40-pin
package, a commercial or industrial temperature range, and
operating frequencies of 1, 2, 3, or 4 MHz. These versions are
coded Into the part number as follows:

Part Number:
R65C24 __ _
Temperature Range:
Blank = O°C to + 70°C
[
E = -40°C to +S5°C
Frequency Range:
1 = 1 MHz
2 = 2 MHz
3 = 3 MHz
4 = 4 MHz

VCC

CA1
CA2
IRQ
CNTR
RSO
RS1

REI
00
01

02
03

04
05

OS
07

162

RS2
CS2

CSO

RJW

Figure 1. R65C24 Pin Configuration

Package:
C = Ceramic
P = Plastic

Document No. 29651N54
2-276

Product Description Order No. 2151
Rev. 3, October 1984

R65C24

Peripheral Interface Adapterrrimer (PlAT)

FUNCTIONAL DESCRIPTION
from the DBB to the PlAT registers. Chip Select and R/Vii control
circuitry interface to the processor bus control lines. The Counter/
Timer consists of a 16-bit counter; i.e., an 8-bit Upper Counter
(UC) and 8-bit Lower Counter (LC), an 8-bit Upper Latch (UL),
an 8-bit Lower Latch (LL), an 8-bit Snapshot Latch (SL), and a
Status Register (SR). A Counter Mode Control Register (CMCR)
selects the Counter/Timer mode of operation. Figure 2 is a block
diagram of the R65C24 PlAT.

The R65C24 PlAT is organized into three independent sections
referred to as the A Side, the B Side, and a Counter/Timer. The
A Side and B Side each consist of a Control Register (CRA,
CRB), Data Direction Register (DORA, DDRB), Output Register
(ORA. ORB), Interrupt Status Control (ISCA, ISCB), and the
buffers necessary to drive the Peripheral Interface buses. Data
Bus Buffers (DBB) interface data from the two sections to the
data bus, while the Data Input Register (DIR) interfaces data

,---------------,fI
CNTR

r:>

IRQT

16-BIT
COUNTERrTlMER

~

DO

01

-

r

.

02
DATA BUS
BUFFERS
(DBB)

03

04
05

06

-

t

.
Tl~

I

OUTPUT BUS

b

--'"

07

U
DATA INPUT
REGISTER
(DIR)

CONTROL
REGISTER A
(CRA)

~

I

PERIPHERAL
OUTPUT
REGISTER A
(ORA)
COUNTER MODE
CONTROL
IREGISTER
(CMCR)

b

DATA DIRECTION
REGISTER A
(DORA)

U
PERIPHERAL
INTERFACE
BUFFER A
(PIBA)

=::>

PERIPHERAL
OUTPUT
REGISTER B
(ORB)

RS1
RiW

¢2
RES

..
.

CHIP
SELECT
&RiW
CONTROL

- .

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

PB1

b

PERIPHERAL
INTERFACE
BUFFER B
(PIBB)

CS2

RSO

CA2

PBO

~

CSO

RS2

CA1

INTERRUPT STATUS
CONTROL A (ISCA)

IRQA

PB2
PB3

- -

PB4
PBS

PB6
PB7

if
INPUT BUS

S

CONTROL
REGISTER B
(CRB)

---IL

•

IROB

Figure 2. R65C24 PlAT Block Diagram

2-277

DATA DIRECTION
REGISTER B
(DDRB)

INTERRUPT STATUS
CONTROL B (ISCB)

cal
CB2

Peripheral Interface Adapterrrimer (PlAT)

R65C24
DATA INPUT REGISTER (DIR)

PERIPHERAL OUTPUT REGISTERS (ORA, ORB)

When the microprocessor writes data into the PlAT, the d!ita
which appears on the data bus during the \112 clock pulse is
latched into the Data Input Register (DIR). The data is then
transferred into one of six internal registers of the PlAT after the
trailing edge of the \212 clock. This assures that the ,data on the
peripheral output lines will make smooth transHions from high
to low (or from low to high) and the voltage will remain stable
except when it is going to the opposite polarHy.

The Peripheral Output Registers (ORA, ORB) store the output
data from the Data Bus Buffers (DBB) which appears on the
Peripheral VO port. If a, line on the Peripheral A Port is programmed as an output by the DORA, writing a 0 into the corresponding bit in the ORA causes that line to go low «0.4 V);
writing a 1 causes the line to go high. The lines of the Peripheral
B port are controlled by ORB in the same manner.

INTERRUPT STATUS CONTROL (ISCA, ISCB)
CONTROL REGISTERS (CRA AND CRB)

The four interrupt/peripheral control lines (CAl, CA2, CB1, CB2)
are controlled by the Interrupt Status Control logic (A, B). This
logic interprets the contents of the corresponding Control Register and detects active transitions on the interrupt inputs.

Table 1 illustrates the bH designation and functions in the two
control registers. The control registers allow the microprocessor
to control the operation of the Interrupt Control inputs (CAl,
CA2, CB1, CB2), and Peripheral Control outputs (CA2, CB2).
Bit 2 in each register controls the addressing of the Data Direction Registers (DORA, DDRB) and the Output Registers (ORA,
ORB). In addition, two bHs (bit 6 and 7) in each control register
indicate the status of the Interrupt Input lines (CAl, CA2, CB 1,
CB2). These Interrupt Status bits (lRQA1, IRQA2 or IRQB1,
IRQB2) are normally interrogated by the microprocessor during
the IRQ interrupt service routine to determine the source of the
interrupt.

PERIPHERAL 1/0 PORTS (PAO-PA7, PBO-PB7)
The Peripheral A and Peripheral B VO ports allow the microprocessor to interface to the input lines on the peripheral device
by writing data into the Peripheral Output Register. They also
allow the processor to interface with the peripheral device output
lines by reading the data on the Peripheral Port input lines
directly dIlto the data bus and into the internal registers of the
processor.

DATA DIRECTION REGISTERS (DDRA, DDRB)

Each of the Peripheral VO lines can be programmed to act as
an input or an output. This is accomplished by setting a 1 in the
corresponding bit in the Data Direction Register for those lines
which are to act as outputs. A 0 in a bit of the Data Direction
Register causes the corresponding Peripheral VO lines to act
as an input.

The Data Direction Registers (DORA, DDRB) allow the processor to program each line in the B-bit Peripheral 1/0 port to
be eHher an input or an output. Each bit in DORA controls the
corresponding line in the Peripheral A port and each bit in DDRB
controls the corresponding line in the Peripheral B port. Writing
a "0" in a bH position in the Data Direction Register causes the
corresponding Peripheral VO line to act as an input; a "1"
causes it to act as an output.

The buffers which drive the Peripheral A VO lines contain "passive" pull-up devices. These pull-up devices are resistive in
nature and therefore allow the output vo~age to go to VCC for
a logic 1. The swHches can sink a full 3.2 mA, making these
buffers capable of driving two standard TTL loads.

Bit 2 (DORA, DDRB) in each Control Register (CRA and CRB)
controls the accessing to the Data Direction Register or the
Peripheral interface. If bit 2 is a "1," a Peripheral Output register
(ORA, ORB) is selected, and if bit 2 is a "0," a Data Direction
Register (DORA, DDRB) is selected. The Data Direction Register Access Control bit, together with the Register Select lines
(RSO, RSI and RS2) selects the various internal registers as
shown in Table 2.

In the input mode, the pull-up devices are still connected to the

VO pin and still supply current to this pin. For this reason, these
lines also represent two standard TTL loads in the input mode.
The Peripheral B VO port duplicates many of the functions of
the Peripheral A port. The process of programming these lines
to act as an input or an output is similar to the Peripheral A port,
as is the effect of reading or writing this port. However, there
are several characteristics of the buffers driving these lines
which affect their use in peripheral interfacing.

In order to write data into DORA, ORA, DDRB, or ORB registers,
bit 2 in the proper Control Register must first be set. The desired
register may then be accessed wRh the address determined by
the address interconnect technique used.

Table 1.

7

eRA

eRB

6

IRQAl

IRQA2

7

8

IRQBl

IRQB2

5

Control Registers Bit Designations
4

3

CA2 Control

5

4
CB2 Control

2-278

2

1

DORA

CAl Control

Access
3

2
DDRB

Access

0

1

0
CBl Control

Peripheral Interface Adapter/Timer (PlAT)

R65C24

Peripheral B I/O lines are programmed to act as inputs, the
output buffer enters the high impedance state.

The Peripheral B I/O port buffers are push-pull devices i.e., the
pull-up devices are switched OFF in the 0 state and ON for a
logic 1. Since these pull-ups are active devices, the logic 1
voltage will not go higher than +2.4V.

DATA BUS BUFFERS (DBB)

Unlike the PAO-PA7 lines (which have pull-up devices), the PBO
through PB71ines have three-state capability which allows them
to enter a high impedance state when programmed to be used
as input lines. In addition, data on these lines Will be read properly, when programmed as output lines, even if the data signals
fall below 2.0 volts for a "high" state or are above 0.8 volts for
a "low" state. When programmed as output, each line can drive
at least a two TTL load and may also be used as a source of
up to 3.2 milliamperes at 1.5 volts to directly drive the base of
a transistor switch, such as a Darlington pair.

The Data Bus Buffers are 8-bit bidirectional buffers used for data
exchange, on the 00-07 Data Bus, between the microprocessor
and the PlAT. These buffers are tri-state and are capable of
driving a two TTL load (when operating in an output mode) and
represent a one TTL load to the microprocessor (when operating in an Input mode).

cOUNTERITIMER
The Counter/Timer Includes a 16-bit counter and three 8-bit data
latches. It also includes an 8-bit Counter Mode Control Register
(CMCR) to select the Counter/Timer operating mode and options
and an 8-bit Status Register to report time-out condition as well
as peripheral data port interrupt conditions. Figure 3 Illustrates
the Timer/Counter.

Because these outputs are designed to drive transistors directly,
the output data is read directly from the Peripheral Output Register for those lines programmed to act as inputs.
The final characteristic is the high-impedance input state which
is a function of the Peripheral B push-pull buffers. When the

00-07

L-.._--r--.._....I iRQT ENABLED
COUNTERiT'IMER
PRESCALER
OPERATING
MODE
ENABLED

14---+-PRESCALER

CNTR

L-________~--1--¢2

00-07

Figure 3. Counter/Timer

2-279

Peripheral Interface Adapter/Timer (PlAT)

R65C24
Counter/Latches-The Upper Counter (UC) and Lower Counter
(LC) form a 16-bit down-counter that counts either ¢2 clock
pulses from the processor bus or external events from input line
CNTR, depending on the mode selected. The Upper Latch (UL)
and Lower Latch (LL) hold the initial higher- and lower-order
count values to be loaded into the counter. The Sn1l.pshot Latch
(SL) is loaded with the value of the UC when the LC is read or
the LL is written into by the PlAT. After a read of the LC, the
Snapshot Latch is read to provide the current 16-bit value of the
counter. The Underflow Flag (UF) in the Status Register (SR)
is set to a 1 whenever the counter (UC, LC) decrements past
$0000. A Prescaler can be program activated to divide-bysixteen rather than divide-by-one for any of the Counter/Timer
modes.

Status Register-Bit 7 of the Status Register (SR) reports the
Counter Underflow Status. This underflow (UF) bit is set to 1
when the counter decrements past $0000. When this bit is set,
the IRO output will be asserted if the Interrupt Enable bit in the
CMCR is set to a 1. The status of the Port A Interrupt Flag
(IROA) and Port B Interrupt Flag (IROB) are reported in bits 6
and 5, respectively, in addition to being reported in the ISCA
and ISCB registers.

Counter Mode Control Register-The Counter Mode Control
Register (CMCR) allows program selection of any of eight
Counter/Timer modes of operation, for the enabling or disabling
of the Prescaler, and the enabling or disabling of the IROT
interrupt line. Bits 2, 1, a of the CMCR selects one of the following Counter/Timer operating modes:

The PlAT interfaces to the peripheral devices with four interrupV
control lines and two 8-bit bidirectional data buses. A Counter/
Timer input/output line (CNTR) also interfaces to a peripheral
device.

INTERFACE SIGNALS
The PlAT interfaces to the R6500, R6500/' or the R65COO
microprocessor family with a reset line, a ¢2 clock line, a read/
write line, an interrupt request line, three register select lines,
two chip select lines, and an 8-bit bidirectional data bus.

Figure 1 (on the front page) shows the pin assignments for these
interface signals and Figure 4 shows the interface relationship
of these signal as they pertain to the CPU and the peripheral
devices.

Disable Counter/Timer
One-Shot Interval Timer
Free-Run Interval Timer
Pulse Width Measurement
Event Counter
One-Shot Pulse Width Generation
Free-Run Pulse Generation
Retriggerable Interval Timer

CHIP SELECT (CSO, CS2)
The PlAT is selected when CSO is high and CS2 is low. These
two chip select lines are normally connected to the processor
address lines either directly or through external decoder cirCUits.
When the PlAT is selected, data will be transferred between the
data lines and PlAT registers, and/or peripheral interface lines
as determined by the R/W, RSO, RSl and RS2 lines and the
contents of Control Registers A and B.

Bit 7 of the CMCR determines whether the IROT line is enabled
or disabled for generating an interrupt request on the IRO output
to the processor. When bit 7 is set to a 1, IROT is enabled so
that an Underflow Flag (UF bit in the Status Register set to a
1) will cause IRO to be asserted. When bit 7 is set to a 0, the
IROT is disabled.

Note:
An R65C24 PlAT may be installed in a circuit in place of
an R65C21 PIA subject to chip select conSiderations.
Since the R65C21 has a CSl input and the R65C24 does
not have a CSl input, the PlAT Will be selected in the
same addresses as the PIA and maybe more depending
upon external address decoding cirCUitry.

Bit 4 of the CMCR enables or disables the Prescaler. A 1 in bit
4 causes the Prescaler to be enabled so that the Counter/Timer
IS operating In a dlvlde-by-slxteen mode. When this bit is a 0,
the Prescaler IS disabled so that the Counter/Timer is operating
in a normal (divlde-by-one) mode.

....
00-07 ~

(8)

> PAO-PA7

8)

02

R6S00,
R6S00r
OR
R6SCOO
MICROPROCESSOR
FAMILY

CAl
CA2

RNi
RSO
RSl
RS2
CSO
CS2
RES
IRQ
VSS
VCC

R6SC24
PlAT

PERIPHERAL
DEVICE
A

CNTR

.

CBl
CB2

....
(8)

Figure 4. Interface Signals Relationship

2-280

J

> PBO-PB7

}

PERIPHERAL
DEVICE
B

Peripheral Interface AdapterfTimer (PlAT)

R65C24

Register Select line RS2 determines whether the addressed
registers are part of the Counter/Timer or the peripheral Port A
and Port B sections of the PlAT. When RS2 is high, the Port N
Port B registers shown in Table 2 are selected. When the RS2
is low, the Counter/Timer registers are selected and operated
upon as shown in Table 3.

RESET SIGNAL (RES)
The Reset (RES) input initializes the R65C24 PlAT. A low signal
on the RES input causes all internal registers to be cleared.

CLOCK SIGNAL (~2)
The Phase 2 Clock Signal (rp2) is the system clock that triggers
all data transfers between the CPU and the PlAT. rp2 is generated by the CPU and is therefore the synchrOnizing signal
between the CPU and the PlAT.

Table 3.

Counter/Timer Register Addressing

Register
Select Lines

Register
Address
(Hex) RS2 RS1 RSO

READIWRITE ~IGNAL (RJW)

0

L

L

Read/Write (R/W) controls the direction of data transfers between
the PlAT and the data lines associated with the CPU and the
peripheral devices. A high on the R!W line permits the peripheral
devices to transfer data to the CPU from the PlAT. A low on the
R/W line allows data to be transfered from the CPU to the
peripheral devices from the PlAT.

Counter/Timer Operation
(R/W = H)

L Read Snapshot

Latch (SL)
SL -+ 00-07
0-+ UF

REGISTER SELECT (RSO, RS1, RS2)
Two of the Register Select lines (RSO, RS1), in conjunction w~h
the Control Registers (CRA, CRB) Data Direction Register access
bits select various R65C24 registers to be accessed by the
CPU. RSO and RSl are normally connected to the microprocessor (CPU) address output lines. Through control of these
lines, the CPU can write directly into the Control Registers
(CRA, CRB) the Data Direction Registers (DORA, DDRB) and
the Peripheral Output Registers (ORA, ORB). In addition, the
processor may directly read the contents of the Control Registers and the Data Direction Registers. Accessing the Peripheral
Output Register for the purpose of reading data back into the
processor operates differently on the ORA and the ORB registers and therefore are shown separately in Table 2.

(R/W = L)
Wnte Upper Latch
(UL)
00-07 -+ UL
0-+ UF
Load and Enable
Counter
UL-+ UC,
LL -+ LC

1

L

L

H Read Upper
Counter (UC)
UC -+ 00-07

Write Upper Latch
(UL)
00-07 -+ UL

2

L

H

L Read Lower
Counter (LC)
LC -+ 00·07
UC-+ SL

Write Lower Latch
(LL)
00-07-+ LL
UC -+ SL

3

L

H

H Read Status
Register (SR)
SR -+ 00-07
0-+ UF,

Write Counter Control
Mode Register
(CMCR)
00-07 -+ CMCR

INTERRUPT REQUEST LINE (IRQ)
Note:

Three internal active low Interrupt Request lines (I ROA, IROB,
and IR~ act to interrupt the microprocessor through the
externallRO output. TRC:i is an open drain output and is capable
of sinking 1.6 milliamps from an external source. This permits
ali interrupt request lines to be tied together in a wired-OR configuration. The A and B in the titles of these internal lines correspond to the peripheral port A and the peripheral port B so
that each interrupt request line services one peripheral data
port. The T corresponds to the Counter/Timer generated interrupt request.

In order to address the ORA and ORB Registers in the
PlAT, Register Select line RS2must be high. When RS2
is low, the Counter/Timer registers are selected (as shown
in Table 3).

Table 2.

Peripheral Register Addressing
Data
Direction
Register
Control

Register
Select
Lines

Regleter
Address
CRA CRB
(Hex) RS2 RSl RSO (BII2) (Bit 2)
4

H

L

L

1

4

H

L

L

0

5

H

L

H

6

H

H

L

6

H

H

L

-

7

H

H

H

-

IRQA and IRQB Lines-These two internal Interrupt Request
lines are associated with the Port A and Port B sections of the
PlAT and are controlled by Control Registers CRA and CRB,
and the Peripheral Control lines CAl, CA2, CB1, and CB2.

Register Operstlon
RNi

=H

RIW

=L

-

Read CRA

Wrije CRA
WrileORB

Read PIBA

Write ORA
These Interrupt Request lines have three interrupt flag bits
which can cause the Interrupt Request line to go low. These
flags are bits 6 and 7 in the two Control Registers (CRA, CRB).
These flags act as the link between the peripheral interrupt signals and the microprocessor interrupt inputs. Each flag has a
corresponding interrupt disable bit which allows the processor
to enable or disable the interrupt from each of the four interrupt

Read DORA Wrije DORA

1

Read PIBB

0

Read OORB Write DORA

-

Read CRB

Wrije CRB

2-281

Peripheral Interface AdapterfTimer (PlAT)

R65C24
inputs (CAl, CA2, CB1, CB2). The four interrupt flags are set
(enabled) by active transitions of the signal on the interrupt input
(CAl, CA2, CB1, CB2).

CA1 is an interrupt input only. An active transition of the signal
on this input will set bit 7 of the Control Register A to a logic 1.
The active transition can be programmed by setting a "0" in bit
1 of the CRA if the Interrupt flag (bit 7 of CRA) is to be set on
a negative transition of the CAl signal or a "1" if it is to be set
on a positive transition.

CRA bit 7 (IROA1) is always set by an active transition of the
CAl interrupt input signal. However, IROA can be disabled by
setting bit 0 in CRA to a O. Likewise, CRA bit 6 (IROA2) can be
set by an active transition of the CA2 interrupt input signal and
IROA can.be disabled by setting bit 3 in CRA to a O.

Note:
A negative transition is defined as a transition from a high
to a low, and a positive transition is defined as a transition
from a low to a high voltage.

Both bit 6 and bit 7 in CRA are reset by a "Read Peripheral
Output Register A" operation. This is defined as an operation
in which the read/write, proper data direction register and register select signals are provided to allow the processor to read
the Peripheral A VO port. A summary of IRQA control is shown
in Table 3.

CA2 can act as a totally independent interrupt or as a peripheral
control output. As an input (CRA, bit 5 = 0) it acts to set the
interrupt flag, bit 6 of CRA, to a logic 1 on the active transition
selected by bit 4 of CRA.

Control of IROB Is performed in exactly the same manner as
that described above for IRQA. Bit 7 in CRB (IROB1) is set by
an active transition on CB1 and IROB from this flag is controlled
by CRB bit O. Likewise, bit 6 (IROB2) in CRB is set by an active
transition on CB2, and
from this flag is controlled by CRB
bit 3.

These control register bits and interrupt inputs serve the same
basic function as that described above for CA1. The input signal
sets the interrupt flag which serves as the link between the
peripheral device and the processor interrupt structure. The
interrupt disable bit allows the processor to exercise control over
the system interrupt.

mae

Also, both bit 6 and bit 7 of CRB are reset by a "Read Peripheral
B Output Register" operation. A summary of 'IROB control is
shown in Table 4.
Table 4_

In the output mode (CRA, bit 5 = 1), CA2 can operate independently to generate a simple pulse each time the microprocessor reads the data on the Peripheral A VO port. This mode
is selected by setting CRA, bit 4 to a 0 and CRA, bit 3 to a 1.
This pulse output can be used to control the counters, shift registers, etc. which make sequential data available on the Peripheral input lines.

IROA and IROB Control Summary

Control Register Bits

Action

CRA-7=1 and CRA-O=1

IROA goes low (Active)

CRA-6=1 and CRA-3=1

IROA goes low (Active)

CRB-7=1 and CRB-O=1

IROB goes low (Active)

CRB-6=1 and CRB-3=1

A second output mode allows CA2 to be used in conjunction
with CAl to "handshake" between the processor and the
peripheral device. On the A side, this technique allows positive
control of data transfers from the peripheral device into the
microprocessor. The CA1 input signals the processor that data
is available by interrupting the processor. The processor reads
the data and sets CA2 low. This signals the peripheral device
that it can make new data available.

IROB goes low (Active)
Note:

The flags act as the link between the peripheral interrupt signals
and the processor interrupt Inputs. The interrupt disable bits allow
the. processor to control the interrupt function.

The final output mode can be selected by setting bit 4 of CRA
to a 1. In this mode, CA2 is a simple peripheral control output
which can be set high or low by setting bit 3 of CRA to a 1 or
a 0 respectively.

IROT Line-The internal IROT line is associated with the
Counter/Timer and is controlled by the IROT Enable bit in the
Counter Mode Control Register and the Underflow Flag in the
Status Register. A thorough discussion of the functions and
operation of the IROT line is given in the Counter/Timer Operation section of this product description.

CBl operates as an interrupt input only in the same manner as
CAl. Bit 7 of CRB is set by the active transition selected by bit
o of CRB. Likewise, the CB2 input mode operates exactly the
same as the CA2 input modeS. The CB2 output modes, CRB
bit 5 = 1, differ somewhat from those of CA2. The pulse output
occurs when the processor writes data into the Peripheral B
Output Register. Also, the "handshaking" operates on data
transfers from the processor into the peripheral device.

INTERRUPT INPUT/PERIPHERAL CONTROL LINES
(CA1, CA2, CB1, CB2)
The four interrupt input/peripheral control lines provide a number
of special peripheral control functions. These lines greatly
enhance the power of the two general purpose interface ports
(PAO-PA7, PBO-PB7). Figure 5 summarizes the operation of
these control lines.

2-282

Peripheral Interface Adapter/Timer (PlAT)

R65C24

CONTROL REGISTER A (CRA)

CA21NPUT MODE (BIT 5 = 0)
7

6

5

4

3

2

1

0

IRQAl
FLAG

IRQA2
FLAG

CA21NPUT
MODE SELECT
(=0)

IRQA2
POSITIVE
TRANSITION

IRQA
ENABLE
FOR IRQA2

ORA
SELECT

IRQA1
POSITIVE
TRANSITION

IRQA
ENABLE
FOR IRQA1

IRQNIRQA1
CONTROL

IRQNlRQA2
CONTROL

CA2 OUTPUT MODE (BIT 5

= 1)

7

6

5

4

3

2

1

0

IRQA1
FLAG

0

CA2 OUTPUT
MODE SELECT
(=1)

CA2
OUTPUT
CONTROL

CA2
RESTORE
CONTROL

ORA
SELECT

IRQA1
POSITIVE
TRANSITION

IROA
ENABLE
FOR IRQA1

CA2
CONTROL

IRQNIRQA1
CONTROL

CA21NPUT OR OUTPUT MODE (BIT 5 = 0 or 1)
Bit 7
1

o

IRQA 1 FLAG
A transition has occurred on CA 1 that satisfies the bit 1 IRQA 1 transition pola"ty criteria This bit IS cleared by a read of Output Register
A or by RES
No transition has occurred on CA 1 that satisfies the bit 1 IRQA 1 transition pola"ty criteria

Bit 2
1
o

OUTPUT REGISTER A SELECT
Select Output Register A
Select Data Direction Register A

Bit 1
1

IRQA 1 POSITIVE TRANSITION
Set IRQA1 Flag (bit 7) on a positive (Iow-to-high) transttlon of CAL
Set IRQA1 Flag (bit 7) on a negative (hlgh-to-Iow) transition of CAL

Bit 0
1

IRQA ENABLE FOR IRQA 1
Enable assertion of IROA when IRQA1 Flag (bit 7) IS set
Disable assertion of IRQA when IRQA 1 Flag (bit 7) IS set.

o
o

CA2 INPUT MODE (BIT 5
Bit 6
1

o

=0)

IRQA2 FLAG
A transition has occurred on CA2 that satisfies the bit 4 IRQA2 transition pola"ty criteria. ThiS flag IS cleared by a read of Output
Register A or by RES.
No transition has occurred on CA2 that satisfies the bit 4 IROA2 tranSition pola"ty criteria

Bit 5

CA2 MODE SELECT
Select CA2 Input Mode

Bit 4
1
o

IRQA2 POSITIVE TRANSITION
Set IRQA2 Flag (bit 6) on a positive (Iow-to-hlgh) transition of CA2
Set IRQA2 Flag (bit 6) on a negative (hlgh-to-Iow) tranSition of CA2

Bit 3
1

IRQA ENABLE FOR IRQA2
Enable assertion of IRQA when IRQA2 Flag (bit 6) IS set
Disable assertion of IRQA when IRQA2 Flag (bit 6) IS set

o

o

CA2 OUTPUT MODE (BIT 5
Bit 6

o

=1)

NOT USED
Always zero.

Bit 5
1

CA2 MODE SELECT
Select CA2 Output Mode

Bit 4
1

CA2 OUTPUT CONTROL
CA2 goes low when a zero IS written Into CRA bit 3 CA2 goes high when a one IS written Into CRA bit 3
CA2 goes low on the first negative (hlgh-to-Iow) ¢2 clock transition follOWing a read of Output Register A. CA2 returns high as specified
by bit 3

o
Bit 3
1

o

CA2 READ STROBE RESTORE CONTROL (BIT 4 = 0)
CA2 returns high on the next ¢2 clock negative transition follOWing a read of Output Register A
CA2 returns high on the next active CA 1 transition follOWing a read of Output Register A as specified by bit 1

Figure 5_

Summary of Control Lines Operation (1 of 2)
2-283

fJ

Peripheral Interface Adapter/Timer (PIAn

R65C24

CONTROL REGISTER B (CRB)

CB2 INPUT MODE (BIT 5 = 0)
7

6

5

4

3

2

1

0

IROBl
FLAG

IROB2
FLAG

CB21NPUT
MODE SELECT
(=0)

IROB2
POSITIVE
TRANSITION

IROB
ENABLE
FOR IROB2

ORB
SELECT

IROBl
POSITIVE
TRANSITION

IROB
ENABLE
FOR IROBl

IROB/IROBl
CONTROL

IROB/IROB2
CONTROL

CB2 OUTPUT MODE (BIT 5

= 1)

7

6

5

4

3

2

1

0

IRQBl
FLAG

a

CB2 OUTPUT
MODE SELECT

CB2
OUTPUT
CONTROL

CB2
RESTORE
CONTROL

ORB
SELECT

IROBl
POSITIVE
TRANSITION

IROB
ENABLE
FOR IROBl

(=1)

CB2
CONTROL

IROB/IROBl
CONTROL

CB21NPUT OR OUTPUT MODE (BIT 5 = 0 or 1)
Bit 7
1
a

IRQBl FLAG
A transition has occurred on CBl that satisfies the bit 1 IROBl transition polarity criteria This bit IS cleared by a read of Output Register
B or by RES
No transition has occurred on CBl that satisfies the bit 1 IROBl transition polarity crltena

Bit 2
1
a

OUTPUT REGISTER B SELECT
Select Output Register B
Select Data Direction Register B

Bit 1
1
a

IRQBl POSITIVE TRANSITION
Set IROBl Flag (bit 7) on a poSItive (low-to-hlgh) trans~lon of CB1.
Set IROBl Flag (btt 7) on a negative (hlgh-to-Iow) transition of CBl

Bit 0
1
a

IRQB ENABLE FOR IRQBl
Enable assertion of IROB when IROBl Flag (bit 7) IS set
Disable assertion of IROB when IROBl Flag (bit 7) IS set

CB21NPUT MODE (BIT 5 = 0)
Bit 6
1

a

IRQB2 FLAG
A transition has occurred on CB2 that satisfies the bit 4 IROB2 transition polarity criteria ThiS flag IS cleared by a read of Output
Register B or by RES
No trans~lon has occurred on CB2 that satisfies the bit 4 IROB2 transition polarity criteria

Bit 5

CB2 MODE SELECT
Select CB2 Input Mode

Bit 4
1

IRQB2 POSITIVE TRANSITION
Set IROB2 Flag (bit 6) on a positive (Iow-to-hlgh) transition of CB2
Set IROB2 Flag (bit 6) on a negative (hlgh-to-Iow) transition of CB2

Bit 3
1

IRQB ENABLE FOR IRQB2
Enable assertion of IROB when IROB2 Flag (bit 6) IS set
Disable assertion of IROB when IROB2 Flag (bit 6) IS set

a
a
a

CB2 OUTPUT MODE (BIT 5 = 1)
Bit 6

NOT USED
Always zero

Bit 5
1

CB2 MODE SELECT
Select CB2 Output Mode.

Bit 4
1

CB2 OUTPUT CONTROL
CB2 goes low when a zero IS written Into CRB bit 3. CB2 goes high when a one IS written Into CRB b~ 3
CB2 goes Iowan the first negative (hlgh-to-Iow) ¢2 clock transition follOWing a wnte to Output Register B CB2 returns high as speCified
by bit 3

Bit 3
1

CB2 WRITE STROBE RESTORE CONTROL (BIT 4 = 0)
CB2 returns high on the next ¢2 clock negative transition follOWing a write to Output Register B
CB2 returns high on the next active CBl transition follOWing a write to Output Register B as speCified by bit 1

o

a

a

Figure 5.

Summary of Control Lines Operation (2 of 2)
2-284

Peripheral Interface Adapterrrimer (PlAT)

R65C24
COUNTERfTlMER REGISTERS

Bit 7

o
1

COUNTER MODE CONTROL REGISTER (CMCR)
The 8-bit Counter Mode Control Register (CMCR) selects the
Counter/Timer mode of operation and enables or disables both
the internal IROT and the Prescaler. The format of the CMCR
IS:
7

IROT
Enabled
Bit 7

6

5

0

0

4

Prescaler
Enabled

1

2

3

Bit 6

o
Bit 5-0

0

1
Bits 6-5
Bit 4
1

Bit 3

Not used, don't care value during write.

Not used, don't care value during write.

Bits 2-0
000
001
0·1 0
011
1 0 0
1 0 1

1

1

0

1

1

1

LOWER LATCH (LL)

Counter/Timer Mode
Mode O-Dlsable Counter/Timer
Mode 1-0ne-Shot Interval Timer
Mode 2-Free-Run Interval Timer
Mode 3-Pulse Width Measurement
Mode 4-Event Counter
Mode 5-0ne-Shot Pulse Width Generation
Mode 6-Free-Run Pulse Generation
Mode 7-Retriggerable Interval Timer

The Lower Latch (LL) holds the least significant 8-bits of the
16-bit latch value. The LL IS written from the data bus (DO-D7)
when the register address is 2 and R/W is low. When the LL IS
loaded, the contents of the UC are copied Into the Snapshot
Latch (SL) without affecting the counting operation of the UC.

UPPER LATCH (UL)
The Upper Latch (UL) holds the most significant 8-bits of the
16-bit latch value. The UL is written from the data bus (DO-D7)
when R/W is low and the register address is either 0 or 1. The
difference in the two register address functions are:

The CMCR can be written into at any time w~hout disabling or
stopping the Counter/Timer. This allows the Counter/Timer mode
of operation to be changed while it IS still in operation. However,
selecting Mode 0 disables the Counter/Timer and stops its
operation. The Prescaler and the IROT interrupt can also be
enabled or disabled at any time. The CMCR is written to when
the register address is 3 and R/W is low.

Register Address 0
1. The UL is loaded from DO-D7.
2. The contents of the Latch (UL and LL) are transferred to the
Counter (UC and LC, respectively).
3. The UF bit IS cleared in the SA.
4. The Counter is enabled, i.e., the count in UC and LC is decremented by one upon detection of a rising edge on either
1252 or CNTR (depending upon mode selection) as scaled by
the Prescaler.

STATUS REGISTER (SR)
The 8-blt Status Register (SR) reports the status of two interrupt
conditions: Counter underflow (I ROT) and Port A Interrupt
(IROA). The format of the Status Register is:
7

Not used, always read as shown In register
figure.

The Counter underflow (UF), bit 7, is updated," the same clock
cycle that an underflow condition occurs on the Counter/Timer.
The IROA interrupt flag (bit 6) is updated at the rising edge of
the next 02 clock immediately following the setting of corresponding interrupt bits (IROA1, IROA2) in the CRA register.
IROA is set whenever IROA1 or IROA2 is set. The underflow
bit is cleared whenever the Status Register is read, the Snapshot Latch is read, the UL IS written to at register address 0,
Mode 0 is selected In the CMCR, or a RES occurs. Reading the
Status Register also clears the IROA interrupt flag. The Status
Register is read when the register address is 3 and R/W is high.

Prescaler Enabled
Prescaler Disabled (-1)
Prescaler Enabled (-16)

o

IRQA Interrupt Flag
Port A Interrupt has not occurred.
Port A interrupt has not occurred.

Counter/Timer Mode

0

IRQT Enabled
IROT Disabled
IROT Enabled

o

Counter Underflow (UF) Interrupt Flag
Counter underflow has not occurred.
Counter underflow has occurred.

5

6

UF (IROT) IROA
Interrupt Interrupt
Flag
Flag

4

3

2

1

0

1

1

1

1

1

Register Address 1
0

1. The UL is loaded from DO-D7.
2. All other elements of the Counter/Timer are unaffected.

2-285

fJ

R65C24

Peripheral Interface Adapter/Timer (PlAT)

LOWER COUNTER (LC)

UL and LL values are loaded into the UC and LC, respectively,
and the counter is enabled. The counter then decrements one
count for every posnive edge (low to high) transition detected
on the ¢2 or CNTR input (depending on the selected mode) as
scaled by the Prescaler. In most modes, each time the counter
underflows below $0000, the underflow bit is set in the SR, the
counter reloads to the latch value and the down-counting continues. If the UF bit is set when the IRaT is enabled in the
CMCR, the IRa output will be asserted to the processor.

The Lower Counter (LC) holds the least significant 8-bits of the
16-bit counter.
When the LC decrements below $00, 1 is borrowed from the
UC to load $FF into the LC.
The LC is read to the data bus (00-07) when the register
address is 2 and R/W is high. When LC is read, the 8-bit contents of the UC is transferred to the Snapshot Latch without
affecting the operation of the counter (Le., the count-down continues without .interruption).

MODE O-DISABLE COUNTER/TIMER
The Counter/Timer is disabled (all counting stops), the IRaT
interrupt (bit 7 in the CMCR) is disabled, and the counter underflow (bit 7 in the SR) is cleared. Mode 0 may be selected at any
time by selecting Mode 0 in the CMCR or upon RES which
initializes the CMCR to $00. Selecting Mode 0 in the CMCR
does not affect any data in the LL or UL, any count in the LC
or UC, or any data in the SL.

UPPER COUNTER
The Upper Counter (UC) holds the most significant 8-bits of the
16-bit counter. The UC is read to the data bus (00-07) when
the register address is 1 and R/W is high. When the UC is read,
there is no other effect on the Counter/Timer operation. Counter
underflow occurs when the LC borrows a 1 from the UC value
of $00.

MODE 1-0NE SHOT INTERVAL TIMER
The counter counts down once from the latch value at the 02
clock rate (as scaled by the Prescaler) and sets the UF bit in
the SR upon underflow. The counter starts when data is written
to the UL at register address 0, which causes the UL and LL
values to be loaded into the UC and LC, respectively. When the
counter decrements below $0000, the UF bit in the SR is set.
The set UF bit causes IRa to be asserted if the IRaT Enable
bit is set in the CMCR. Upon decrementing below $0000, the
UC and LC are automatically reset to a value of $FFFF and the
counter continues down-counting. However, the UF bit in the
SR will not be set again (due to the counter again decrementing
through $0000) until the UL is again written at register address
O. The CNTR line is not used in this mode. Figure 6 shows the
timing relationship for Mode 1 operation.

Note:
When reading the UC directly, the value read can be one
count too high if the LC value is just above $0000 at the
start of the read since an underflow in the LC will result
in decrementing the UC by one count. The Snapshot
Latch should be read to obtain the UC value corresponding to the LC value.

SNAPSHOT LATCH (SL)
The Snapshot Latch holds the value of the UC corresponding
to the LC value. The SL is loaded with the value of the UC when
the LL is written to, or when the LC is read. The SL is read to
the data bus (00-07) when the register address is 0 and R/W
is high, without affecting the counting operation. When the SL
is read, the UF in the SR is cleared. Since the SL is loaded with
the value of the UC whenever the LC is read, an accurate count
of the total 16-bit counter can be made without the need for
further calculations to account for delays between the reading
of the LC and the UC.

Typical Application: Can be used for an accurate time delay
such as would be required to control the duration of time to have
a thermal printer element activated.

MODE 2-FREE·RUN INTERVAL TIMER

COUNTER/TIMER OPERATION
The Counter/Timer has eight modes of operation. The Counter/
Timer is always either disabled (mode 0) or operating in one of
the other seven modes as selected in the Counter Mode Control
Register (CMCR).
To operate the Counter/Timer, first issue Mode 0 to stop any
counting in progress due to a previously selected mode, to clear
the counter underflow bit in the SR and to disable the IRaT
interrupt. The order of mode selection and latch loading depends
upon the desired mode. Generally, if a timer mode based on the
5152 clock rate is to be selected, first select the mode then write
the timer initialization value to the latch. Write the LL first then
the UL value (to register address 0). When the UL is written, the

2-286

The counter repetitively counts down at the ¢2 clock rate, as
scaled by the Prescaler, and sets the UF bit in the SR each time
the counter underflows. The counter is initialized to the UL and
LL values and starts down counting at the clock rate when the
UL value is written to register address O. Each time the counter
decrements below $0000, the UF bit in the SR is set, the counter
is reloaded with the UL and LL value, and the count-down cycle
continues. If the IRaT Enable bit is set in the CMCR, IRQ will
thus be asserted upon each time-out. The CNTR line is not used
in this mode. Figure 7 shows the timing relationship for Mode
2 operation.
Typical Application: Can be used for a timed interrupt structure when a hardware location needs updating at specific intervals, such as would be required to update a multiplexed display.

Peripheral Interface Adapter/Timer (PlAT)

R65C24

2

WRITE
UPPER LATCH _ __
(ADDR 0)
IRQ-----4-------_r,L-----4
N + 2

(I------JI

I-----CYCLES-----l
READ
STATUS _ _ _ _ _ _ _ _ _ _ _ _~l~l------_(), r---\ ____________
REGISTER
""~
,
READ
~

SNAPSHOT------------~,~v~-----_r~,L---~

~-------

LATCH

Figure 6. Mode 1-0ne-Shot Interval Timer Timing

",,'" :-:.~~~: f
(ADDR 0)

' "

IRQ

.

READ
STATUS

-

N + 2

;

/

'_..
i'

()~

~--------

CYCLES

N + 1 CYCLES - - - - - - - - \
. /""\.
REGISTER ----~(»,>-()----_(tV-J
'-f''>-()- - - - - - T ( > C ( l . . l- - - - - - - - - - - READ
r---\

SNAPSHOT-----~J~)-----,~r~--~()~

~\~l------------­

LATCH

Figure 7. Mode 2-Free-Run Interval Timer Timing

2-287

fJ

Peripheral Interface Adapter/Timer (PlAT)

R65C24
MODE 3-PULSE WIDTH MEASUREMENT

MODE 4-EVENT COUNTER

The counter counts down from the latch value at the ¢2 clock
rate (scaled by the Prescaler) from the time the CNTR input
goes low until CNTR goes high to provide a measurement of
the CNTR low pulse duration. The counter is loaded with the
value of the UL and LL upon writing UL to register address o.
The counter starts decrementing at the scaled
clock rate
when the CNTR line goes low and stops decrementing when
the CNTR line returns high. If the counter decrements below
$0000 before the CNTR line goes low, the UF bit in the SR is
set, the counter is reloaded with the UL and LL value, and the
cycle continues down until CNTR goes high. Once the CNTR
line has cycled from high to low and back to high, the Counter/
Timer will ignore any additional high to low transitions on the
CNTR line. To relnitiate Mode 3, it is necessary to reload the
UL by writing to register address o. Figure 8 shows the timing
relationships for a Mode 3 operation.

CNTR is an input and the Counter/Timer counts the number of
positive transitions on CNTR. The counter is initially loaded with
the UL and LL value when the UL is written to register address
o. The counter then decrements one count on the rising edge
of the
clock after a riSing edge (lOW to high transition) is
detected on the CNTR input (as scaled by the Prescaler). The
maximum rate at which this rising edge can be detected is onehalf the
clock rate. When the counter decrements below
$0000, the UF bit in the SR is set, the counter is reloaded with
the UL and LL value and the operation repeats. Figure 9 shows
the timing relationship of a Mode 4 operation.

912

02

912

Typical Application: Can be used with a timed software loop
to count external events (i.e., a frequency counter).

Typical Application: Can be used to measure the duration of
an event from an external device. Allows an accurate measurement of the duration of a logical low pulse on the CNTR line.

j
L
I
I
I
I
_: _: _; _: J1~=ECR.."".\'----.L---JI

TIMER DOES NOT DECREMENT

Figure 8. Mode 3-Pulse Width Measurement Timing

1/>2

CNTR~'-

________

J/r~!~Ir----~\~______-J/r~l~lr-----~\~________-JI
COUNTER
DECREMENTED

COUNTER
DECREMENTED
PAST $0000, UF BIT SET
AND UC, LC RELOADED FROM UL, LL

iI

""-

COUNTER
DECREMENTED

\1-_____-11

READ
~
SNAPSHOT----------------------------I{
,'------LATCH

Figure 9. Mode 4-Event Counter Timing

2-288

Peripheral Interface Adapter/Timer (PlAT)

R65C24
MODE 5-0NE·SHOT PULSE WIDTH GENERATION

(if low upon mode selection) when data is written to the UL at
register address 0 which also starts the counter. The counter
decrements at the 02 clock rate as scaled by the Prescaler.
When the counter decrements below $0000, CNTR toggles from
low to high (or high to low depending upon its initial state), the
counter is reloaded wHh the UL and LL value and the counter
continues down-counting. The UF bH in the SR is set the first
time the counter decrements past $0000 and is cleared only if
a new wrrte to UL at register address 0 occurs. Figure 11 shows
the timing relationship of a Mode 6 operation.

CNTR is an output which can be pulsed low for a programmed
time interval. When this mode is selected in the CMCR, the
CNTR output goes high (if the UF bit is set) or goes low (if the
UF bit is cleared). The CNTR line then goes low when data IS
written to the UL at register address 0, which also starts the
counter. The counter decrements from the UL and LL value at
the 02 clock rate as scaled by the Prescaler. When the counter
decrements below $0000, the CNTR output goes high, the UF
bit is set in the SR, the counter is reloaded with $FFFF and the
count-down continues. Figure 10 shows the timing relationship
of Mode 5 operation.

This mode can be used to generate an asymmetncal waveform
by toggling the UL and LL With the CNTR high and low times.
Immediately after starting the counter wHh the first CNTR low
time, load the LL and UL (by Writing to register address 1, which
does not restart the counter) with the CNTR high time. When
the first counter underflow occurs, the counter loads the new
latch value (i.e., the CNTR high time) Into the counter and continues counting. DUring the IRQ Interrupt processing resulting
from the first counter time-out, load the LL and UL (at register
address 1) With the onglnal CNTR low time. Continue to alternate loading of the high and low time latch values during the
Interrupt processing for the duration of the mode.

Note that clearing the UF bit after it is set upon the first timeout
causes CNTR to go low, in which case CNTR will again go high
upon the next counter timeout.
Typical Application: Can be used to hold-off (delay) an extemal
hardware event on an asynchronous basis such as disallOWing
a motor startup until certain parameters are met.

MODE 6-FREE·RUN PULSE GENERATION
CNTR is an output and the Counter/Timer can be programmed
to generate a symmetrical waveform, an asymmetrical waveform, or a string of varying width pulses on CNTR. The CNTR
line IS forced low (If high upon mode selection) or remains low

CNTR

Typical Application: Can be used to supply external circuitry
wrth a software variable clock based upon the system ¢2 clock
(e.g., a tone generator for audiO feedback).

~~~~~ C_~C-T~CI-;S_-_-_-_-_ -_....J,Jr------------___

-_

UNDERFLOW
FLAG
SET

Figure 10. Mode 5-0ne-8hot Pulse Width Generation Timing

<1>2

_+0_- N + 1 _ _oj._ _ N + 1
CYCLES

CYCLES

Figure 11. Mode 6-Free-Run Pulse Generation Timing

2-289

2

R65C24

Peripheral Interface Adapter/Timer (PlAT)

MODE 7-RETRIGGERABLE INTERVAL TIMER

LDA
STA
LDA
STA

The Counter/Timer operates as a timer which is retriggered, i.e.,
reinitialized to its starting value, upon detection of a negative
transition on the CNTR input. The counter is initially loaded with
the UL and LL value when the UL is written to register address
O. The counter starts decrementing at the ¢2 clock rate (as
scaled by the Prescaler) when a falling edge (high to low transition) is detected on CNTR. The counter is reinitialized to the
UL and LL value whenever a falling edge is subsequently
detected on CNTR. If the counter decrements past $0000 before
the falling edge is detected, the UF bit is set in the SR, the
counter is initialized to the UL and LL value and the count-down
continues.

#$Iovalue
LL
#$hivalue
ULEC

;Iower latch value
;write to lower latch
;upper latch value
;write to upper latch
;clear underflow flag, and enable
counter

The following instructions is a way to change modes while the
Counter/Timer is in operation:
LDA

#$mode

STA

CMCR

;select desired mode, except
mode 0
;write to mode register

The change of mode operation will take effect immediately.
Thus, the Free-Run Internal Timer mode (Mode 2) could be systematically stopped by changing to the One-Shot Interval Timer
mode (Mode 1). The Counter/Timer will then halt operation
when the underflow condition occurs. This technique can also
be used to enable or disable IRQ during program execution.

Typical Application: Can be used to monitor signals that should
be periodic and can interrupt the processor if the signal being
monitored does not occur within a specified time frame; such
as a synchronous motor that has fallen out of synchronization.

PRESCALER

READING THE COUNTER/TIMER

The Counter/Timer operates in either the divide by one or divide
by sixteen mode. In the divide by one mode, the counter holds
from 1 to 65,535 counts. The counter capacity is therefore 1 I1-S
to 65,535 I1-S at 1 MHz ¢2 clock rate or 0.25 I1-S to 16,383 I1-S
at a 4 MHz ¢2 clock rate. Timer intervals greater than the maximum counter value can be easily measured by counting underflow flags or IRQ interrupt requests.

To service an interrupt request, the following sequence can be
used:
BIT
BNE
LDA
LDX

The divide by sixteen prescaler can be enabled to extend the
timing interval by 16. This provides timing from 1048.56 ms (1
MHz) to 260.21 ms (4 MHz). The prescaler clocks the Counter/
Timer at the 02 clock rate divided by sixteen, except for Mode
4. In Mode 4, sixteen positive CNTR edges must occur to decrement the Counter/Timer by one count.

$status
error
$LC
$SL

;getunderflow flag
;check if flag is set
;get low counter value for overflow
;get high counter value for overflow
;underflow flag is cleared

By reading the LC and SL, it is possible to determine the amount
of time between the interrupt request and servicing the interrupt.
To read a timer value at any time, the suggested technique is
as follows:
LDA

$LC

LDA

$SL

INITIALIZING THE COUNTER/TIMER
The following program segment IS one suggested technique for
Initializing the Counter/Timer:

;get low counter value
;upper counter transferred to
snapshot
;any miscellaneous code to store
value if desired
;get high counter value

;Data Definition
SL
UC
LC
SR
ULEC
UL
LL
CMCR

=
=
=
=
=
=
=
=

$XXXO
$XXX1
$XXX2
$XXX3
$XXXO
$XXX1
$XXX2
$XXX3

;Snapshot Latch
;Upper Counter
;Lower Counter
;Status Register
;Upper Latch and Enable Counter
;Upper Latch
;Lower Latch
;Counter Mode Control Register

READ/WRITE TIMING
CHARACTERISTICS OF PlAT
Figure 12 is a timing diagram for the R65C24 PlAT during a
Read operation (input mode). Figure 13 is a timing diagram for
the PlAT during a Write operation (output mode). Table 5 shows
the characteristics of the times shown in Figures 12 and 13.

; Program
LDA
STA
LDA

#$modeO
CMCR
#$mode

STA

CMCR

;disable Counter/Timer
;write to mode register
;select mode and Prescaler and
IRQT enable/disable
;write to mode register

2-290

R65C24

Peripheral Interface Adapter/Timer (PlAT)

CNTR---""""
COUNTER
STARTS
DECREMENTING

UNDERFLOW MUST
OCCUR BY THIS TIME TO
SET UNDERFLOW FLAG

f - - - - - - TIME DECREMENTS, POSSIBLE TO--t---TIMER STILL DECREMENTS
SET UNDERFLOW FLAG

IF NO UNDERFLOW HAS
OCCURRED

Figure 12. Mode 7-Retrlggerable Interval Timer Timing

q,2 _ _ _ _ _ _ _......,

PBO·PB7

.e----+---t-------+----------i:>i:>,QQ,~~ -----+---+---------t-----------

00.07

~~~~~~S8:S8:~~-........'\lI>------_+_----------_

PAO.PA7 50<50<::~~

DATA OUT =~~"""~~~~~ ~_~

CA2
(PULSE OUT)

CAl

CA2
(HAND SHAKE)

Figure 13. Read Timing Diagram

2·291

PI

Peripheral Interface Adapter/Timer (PlAT)

R65C24

RSO, RS1, RS2
CSO, CS2

RIW

00-07
DATA IN

Vcc -30%
PAO-PA7 ,",",;;o:;?"<"'X'i~~""",.Jt.5.--If-------f-----------­
PBO-PB7

.lI..Q.A.Q'::"::'~=='-lU"""" 1 t - - - I f - - - - - - - f - - - - - - - - - - - -

CB2
(PULSE OUT)

CBl

CB2
(HAND SHAKE)

Figure 14. Write Timing Diagram

READING THE PERIPHERAL A 1/0 PORT

when the Peripheral Output register contains a logic 1. In this
case, the processor will read a 0 from the Peripheral A pin, even
though the corresponding bit in the Peripheral Output register
is a 1.

Performing a Read operation with RS1 = 0, RSO = 0 and the
Data Direction Register Access Control bit (CRA-2) = 1, directly
transfers the data on the Peripheral A I/O lines to the data bus.
In this situafion, the data bus Will contain both the input and
output data. The processor must be programmed to recognize
and interpret only those bits which are important to the particular
peripheral operation being performed.

READING THE PERIPHERAL B 1/0 PORT
Reading the Peripheral B I/O port yields a combination of input
and output data in a manner similar to the Peripheral A port.
However, data is read directly from the Peripheral B Output
Register (ORB) for those lines programmed to act as outputs.
It is therefore possible to load down the Peripheral B Output
lines without causing incorrect data to be transferred back to the
processor on a Read operation.

Since the processor always reads the Peripheral A I/O port pins
instead of the actual Peripheral Output Register (ORA), it is posSible for the data read by the processor to differ from the contents of the Peripheral Output Register for an output line. This
is true when the I/O pin is not allowed to go to a full +2.4V DC

2-292

R65C24

Peripheral Interface Adapter/Timer (PlAT)

BUS TIMING CHARACTERISTICS
2MHz

1MHz
Symbol

Min

q,2 Cycle

TCYC

1.0

q,2 Pulse Width

tc

q,2 Rise and Fall Time

Parameter

Max

3MHz

4MHz

Min

Max

Min

Max

Min

Max

Unit

0.5

-

0.33

-

0.25

-

1'5

450

-

220

-

160

110

-

ns

trc • tfc

-

25

-

15

-

12

-

10

ns

READ TIMING
Address Set-Up Time

t ACR

140

-

70

-

53

-

35

-

ns

Address Hold Time

tCAR

0

0

-

0

-

0

-

ns

Peripheral Data Set-Up Time

t pCR

300

-

150

110

ns

tCOR

325

145

-

80

ns

Data Bus Hold Time

tHR

20

-

20

-

20

-

-

-

Data Bus Delay Time

-

-

75

-

-

20

-

ns

-

70

53

-

ns

0
45

-

ns

67

-

53

90

-

0

-

0

-

0

-

ns

67

-

45

-

ns

105

WRITE TIMING
Address Set-Up Time

t ACW

140

Address Hold Time

tCAW

0

RIW Set-Up Time

twcw

180

RIW Hold Time

tcww

0

Data Bus Set-Up Time

tocw

180

0

0

Data Bus Hold Time

tHW

10

-

Peripheral Data Delay Time

tcpw

-

1.0

-

0.5

Peripheral Data Delay Time
to CMOS Level

tCMOS

-

2.0

-

1.0

-

10

90

-

10

10

ns

ns

0.33

-

0.25

I's

0.7

-

0.5

p's

PERIPHERAL INTERFACE TIMING
1MHz
Parameter

Symbol

2MHz

3MHz

4MHz

Min

Max

Min

Max

Min

Max

Min

-

150

-

110

-

75

1.0

-

0.5

0.33

-

0.25

1.0

-

0.5

0.33

-

0.25

p.S

2.0

1.0

0.67

0.5

p's

Peripheral Data Setup

tpCR

300

q,2 Low to CA2 Low Delay

tCA2

q,2 Low to CA2 High Delay

t RS1

CA 1 Active to CA2 High Delay

tRS2

Max

-

Unit

ns

q,2 High to CB2 Low Delay

tCB2

-

1.0

-

0.5

-

0.33

-

0.25

P.s

Peripheral Data Valid to CB2 Low Delay

toc

0

1.5

0

0.75

0

0.5

0

0.37

p's

q,2 High to CB2 Hgh Delay

tRS1

-

0.25

p's

0.67

-

0.5

I'S

CAl, CA2, CBl and CB2
Input Rise and Fall Time

t" t f

1.0

-

10

-

0.33

2.0

-

0.5

tRS2

-

1.0

CB 1 Active to CB2 High Delay

1.0

-

1.0

P.s

2-293

1.0

P.s

Peripheral Interface Adapter/Timer (PlAT)

R65C24
ABSOLUTE MAXIMUM RATINGS·
Symbol

Value

Unit

Supply Voltage

Parameter

Vee

-0.3 to +7.0

Vdc

Input Voltage

VIN

- 0.3 to Vee + 0.3

Vdc

Output Voltage

VOUT

-0.3 to Vee +0.3

Vdc

Operating Temperature
Commercial
Industrial

TA

. Storage Temperature

• Note: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

°C

o to

+70
-40 to +85
TSTG

-55 to +150

°C

OPERATING CONDITIONS
Symbol

Value

Supply Voltage

Parameter

Vee

5V ±5%

Temperature Range
Commercial
Industrial

TA
0° to 70°C
- 40° to + 65°C

DC CHARACTERISTICS
Vee = 5.0V ±5%, Vss = 0, TA = TL to TH, (unless otherwise noted)
Max

Unltl

Vee

V

Min

Typ3

V,"

+2.0

Vil

-0.3

-

+0.8

V

Input Leakage Current:
Rm, RES, RSO, RS1, RS2, CSO, CS2, CA1,
CB1, <1>2

I'N

-

±1

±2.5

~A

V'N = OV to Vee
Vee = 5.25V

Input Leakage Current for Three-State Off
00-07, PBO-PB7, CB2

ITSI

-

±2

±10

~A

VIN = OAV to 2AV
Vee = 5.25V

Input High Current
PAD-PA7, CA2

IIH

~

V IH = 2AV

Input Low Current
PAO-PA7, CA2

IlL

rnA

VIL = OAV

Output High Voltage
Logic
PBO-PB7, CB2 (Darlington Drive)

VOH

Output Low Voltage
PAD-PA7, CA2, PBO-PB7, CB2
00-07, IRQ, CNTR

VOL

Output High Current (Sourcing)
Logic
PBO-PB7, CB2 (Darlington Drive)

10H

Output Low Current (Sinking)
PAO-PA7, PBO-PB7, CB2, CA2
00-07, IRQ, CNTR

IOL

Output Leakage Current (Off State):
IRQ

Parameter
Input High Voltage
Input Low Voltage

Symbol

-200

-400

-

-2

2.4
1.5

-

-

-200
-3.2

-1500
-6

-3.2

-

-

V
V

+004

V

-

~
rnA

-

-

IOFF

-

1

±10

~

-

7

10

mW/MHz

-

-

10
7
20

pF
pF
pF

10

pF

Power Dissipation

Po
CIN

Output Capacitance

COUT

-

Notes:
1. All units are direct current (dc) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values are shown for Vee = 5.0V and TA = 25°C.
2-294

Vee = 4.75V
ILOAD = 200~A
ILOAD, = - 3.2 mA
Vee = 4.75V
ILOAD = 3.2 rnA
ILOAD = 1.6 rnA
VOH = 2.4V
VOH = 1.5V
VOL = OAV

-

3.2
1.6

Input Capacitance
00-07, PAO-PA7, PBO-PB7, CA2,CB2,CNTR
Rm, RES, RSO, RS1, RS2,CSO, CS2
CA1, CB1, <1>2

Test Conditions

-

rnA
rnA
VOH = 2AV
Vee = 5.25V

Vee = 5.0V
VIN = OV
f = 2 MHz
TA = 25°C

Peripheral Interface Adapter/Timer (PlAT)

R65C24
PACKAGE DIMENSIONS
4G-PIN CERAMIC DIP

[ D ::I]
I~
~F

H~~LD

A

111M

?n;in
·1

G

_~ ~

K..j~J

A
B
C
0
F

G
H

J
K
L
M
N

MIWMETERS
INCHES
MIN MAX
MAX
MIN

5029 5131
1486 1562
254 419
038 053
076 140
254 esc
076 178
020 033
254 419
1460 1537
10'
0'
152
051

1980
0585
0100
0015
0030
0100
0030
0006
0100
0575
O·
0020

2020
0615
0165
0021
0055

esc
0070
0013
0165
0605
10'
0060

M-j

40-PIN PLASTIC DIP
MILLIMETERS

DIM MIN MAX
A 5128 5232
B 1372 1422
C
355 508
0
036 051
F
102 152
254 esc
G
H
165 216
020 030
J
K
305 358
1524 esc
L
10'
M
7'
102
N
051

2-295

INCHES
MAX
MIN

2040
0540
0140
0014
0040

2060
0560
0200
0020
0060

0100 esc
0065 OOBS
0008 0012
0120 0140
0600 esc
7'
10'
0020 0040

R65C51

'1'

R65C51
ASYNCHRONOUS COMMUNICATIONS
INTERFACE ADAPTER (ACIA)

Rockwell
DESCRIPTION

FEATURES

The Rockwell CMOS R65C51 Asynchronous Communications
Interface Adapter (ACIA) provides an easily implemented, program controlled interface between B-bit microprocessor-based
systems and serial communication data sets and modems.

•
•
•
•
•

Low power CMOS N-well silicon gate technology
Direct replacement for NMOS R6551 ACIA
Full duplex operation wijh buffered receiver and transmitter
Data set/modem control functions
Internal baud rate generator with 15 programmable baud
rates (50 to 19,200)
• Program-selectable internally or externally controlled receiver
rate
• Programmable word lengths, number of stop bits, and parity
bit generation and detection
• Programmable Interrupt control

The ACIA has an internal baud rate generator. This feature eliminates the need for muHiple component support circuits, a crystal
being the only other part required. The Transmitter baud rate
can be selected under program control to be either 1 of 15 different rates from 50 to 19,200 baud, or at '/'6 times an external
clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate, or at '/'6 times
the external clock rate. The ACIA has programmable word
lengths of 5, 6, 7, or B bits; even, odd, or no parity; 1, 1V2, or
2 stop bits.

• Program reset
• Program-selectable serial echo mode
•
•
•
•
•
•

The ACIA is designed for maximum programmed control from
the microprocessor (MPU), to simplify hardware implementation. Three separate registers permit the MPU to easily select
the R65C51's operating modes and data checking parameters
and determine operational status.
The Command Register controls parity, receiver echo mode,
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the ffi'R line.

Two chip selects
1 or 2 MHz operation
5.0 Vdc ± 5% supply requirements
2B-pin plastic or ceramic DIP
Full TTL compatibility
Compatible with R6500, R6500/* and R65COO microprocessors

The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
VSS

The Status Register indicates the states of the IRQ, DSR, and
DCD lines, Transmitter and Receiver Data Registers, and
Overrun, Framing, and Parity Error conditions.
The Transmitter and Receiver Data Registers are used for temporary data storage by the ACIA Transmit and Receiver circuits.

r

ORDERING INFORMATION
Part No.: R65C51

,m"""",
R,"" CO, ., T",'
Blank = DoC to + 70°C

T

E = -40°C to +85°e
Frequency Range:
1 = 1 MHz
2 = 2 MHz

28

ffi

3

26

R/W
_2
IRQ

RES

4

25

07

RxC

5

24

06

XTLI
XTLO

6

23

05

7

22

04

RTS

8

21

03

CTS

9

20

02

CSO

2

27

TxO

10

19

01

OTR

11

18

DO

RxO

12

17

OSR

RSO

13

16

OCO

RS1

14

15

VCC

-Package:
= Ceramic
P = Plastic

e

Figure 1. R65C51 ACIA Pin Configuration

Document No. 29651 N6D
2-296

Product Description Order No. 2157
Rev. 3, October 1984

R65C51

Asynchronous Communications Interface Adapter (ACIA)

l
DO-D7

<-

-:::>I

IRQ

DATA
BUS
BUFFER

r-L

I
N
T
E
R
N
A
L
D
A
T
A
B
U
S

-

INTERRUPT

I LOGIC

>----

RiW
CSO
CSt
RSO

1/0
CONTROL
~

RSt

j2
RES

TIMING

& CONTROL

I

TRANSMIT
DATA
REGISTER
STATUS
REGISTER

.........

I

~

CONTROL
REGISTER

L

r
l
I

I

.... 1 COMMAND I
REGISTER

JI

-

RECEIVE
DATA
REGISTER

TRANSMIT
CONTROL

CTS

.1 TRANSMIT
SHIFT
1 REGISTER

TxD

DCD

I

DSR
BAUD
RATE
GENERATOR

1

~RxC

f4---

XTLI

r---- XTLO
DTR

I

J

I

1

I
Figure 2.

•

r-r• r-

RECEIVE
SHIFT
REGISTER

RTS

RxD

RECEIVE
CONTROL

ACIA Internal Organization

FUNCTIONAL DESCRIPTION

TIMING AND CONTROL

A block diagram of the ACIA is presented in Figure 2 followed
by a description of each functional element of the device.

The Timing and Control logiC controls the timing of data transfers on the Internal data bus and the registers, the Data Bus
Buffer, and the microprocessor data bus, and the hardware
reset features.

DATA BUS BUFFERS
The Data Bus Buffer interfaces the system data lines to the internal data bus. The Data Bus Buffer is bi-directional. When the
RiW line is low and the chip is selected, the Data Bus Buffer
writes the data from the system data lines to the ACIA internal
data bus. When the RiW line is high and the chip is selected,
the Data Bus Buffer drives the data from the internal data bus
to the system data bus.

Timing is controlled by the system ~2 clock input. The chip will
perform data transfers to or from the microcomputer data bus
during the %2 high period when selected.
All registers will be initialized by the Timing and Control LogiC
when the Reset (RES) line goes low. See the individual register
description for the state of the registers following a hardware
reset.

INTERRUPT LOGIC
The Interrupt Logic Will cause the IRQ line to the microprocessor
to go low when conditions are met that require the attention of
the microprocessor. The conditions which can cause an Interrupt will set bit 7 and the appropriate bit of bits 3 through 6 in
the Status Register, if enabled. Bits 5 and 6 correspond to the
Data Carrier Detect (DCD) logic and the Data Set Ready (DSR)
logic. Bits 3 and 4 correspond to the Receiver Data Register full
and the Transmitter Data Register empty conditions. These conditions can cause an Interrupt request if enabled by the Command Register.

TRANSMITTER AND RECEIVER DATA REGISTERS
These registers are used as temporary data storage for the
ACIA Transmit and Receive Circuits. Both the Transmitter and
Receiver are selected by a Register Select 0 (RSO) and Register
Select 1 (RS1) low condition. The Read/Write (Fl/W) line determines which actually uses the internal data bus; the Transmitter
Data Register is write only and the Receiver Data Register is
read only.
Bit 0 is the first bit to be transmitted from the Transmitter Data
Register (least significant bit first). The higher order bits follow
in order. Unused bits In this register are "don't care".

I/O CONTROL
The I/O Control Logic controls the selection of Internal registers
in preparation for a data transfer on the internal data bus and
the direction of the transfer to or from the register.

The Receiver Data Register holds the first received data bit in
bit 0 (least Significant bit first). Unused high-order bits are "0".
Parity bits are not contained in the Receiver Data Register. They
are stripped off after being used for parity checking.

The registers are selected by the Receiver Select (RS1, RSO)
and Reacl/Write (Fl/W) lines as described later in Table 1.

2-297

R65C51

Asynchronous Communications Interface Adapter (ACIA)
Parity Error (Bit 0). Framing Error (Bit 1). and
Overrun (2)

STATUS REGISTER
The Status Register indicates the state of interrupt conditions
and other non-interrupt status lines. The interrupt conditions are
the Data Set Ready, Data Carrier Detect, Transmitter Data Register Empty and Receiver Data Register Full as reported in bits
6 through 3, respectively. If any of these bils are sel, the Interrupt (IRQ) indicator (bit 7) is also set. Overrun, Framing Error,
and Parity Error are also reporled (bits 2 through 0 respectively).
7

6

5

4

3

2

None of these bits causes a processor interrupt to occur, but
they are normally checked at the time the Receiver Data Register is read so that the validity of the data can be verified. These
bits are self clearing (Le., they are automatically cleared after
a read of the Receiver Data Register).

o
Receiver Data Register Full (Bit 3)
PE

Bit 7

0
1
Bit 6

0
Bit 5

0
Bit 4

0
1

Interrupt (IRQ)
No interrupt
Interrupt has occurred
Data Set Ready (DSR)
DSR low (ready)
DSR high (not ready)

Bit 2

Overrun'
No overrun
Overrun has occurred

0
1
Bit 0

0

This bit goes to a 1 when the AC IA transfers data from the
Transmitter Data Register to the Transmitter Shift Register, and
goes to a 0 (is cleared) when the processor writes new data
onto the Transmitter Data Register.

Transmitter Data Register Empty
Not empty
Empty
Receiver Data Register Full
Not full
Full

Bit 1

Transmitter Data Register Empty (Bit 4)

Data Carrier Detect (DCD)
DCD low (detected)
DCD high (not detected)

Bit 3
0
1

0

This bit goes to a 1 when the ACIA transfers data from the
Receiver Shift Register to the Receiver Data Register, and goes
to a 0 (is cleared) when the processor reads the Receiver Data
Register.

Data Carrier Detect (Bit 5) and Data Set Ready
(Bit 6)
These bits reflect the levels of the DCD and DSR inputs to the
ACIA. A 0 indicates a low level (true condition) and a 1 indicates
a high level (false). Whenever either of these inputs change
state, an immediate processor interrupt (IRQ) occurs, unless bit
1 of the Command Register (IRD) is set to a 1 to disable IRQ.
When the interrupt occurs, the status bits indicate the levels of
the inputs immediately after the change of state occurred. Subsequent level changes will not affect the status bits until the
Status Register is interrogated by the processor. At that time,
another interrupt will immediately occur and the status bits
reflect the new input levels. These bits are not automatically
cleared (or reset) by an internal operation.

Framing Error'
No framing error
Framing error detected
Parity Error'
No parity error
Parity error detected

Interrupt (Bit 7)
* No interrupt occurs for these conditions

This bit goes to a 1 whenever an interrupt condition occurs and
goes to a 0 (is cleared) when the Status Register is read.

Reset Initialization

Hardware reset
Program reset

2-298

R65C51

Asynchronous Communications Interface Adapter (ACIA)

CONTROL REGISTER

Selected Baud Rate (Bits 0, 1,2, 3)

The Control Register selects the desired baud rate, frequency
source, word length, and the number of stop bits.

These bits select the Transmitter baud rate, which can be at
'/,6 an external clock rate or one of 15 other rates controlled by
the internal baud rate generator.
If the Receiver clock uses the same baud rate as the transmitter,
then RxC becomes an output and can be used to slave other
circuits to the ACIA. Figure 3 shows the Transmitter and Receiver
layout.

Bit 7
0
1
1

Stop Bit Number (SBN)
1 Stop bit
2 Stop bits
1V2 Stop bits
For WL = 5 and no parity
1 Stop bit
For WL = 8 and parity

Bits 6-5

..!.
0
0
1
1

..§..
0
1
0
1

Bit 4
0
1

0
0
0
0
0
0
0
0
1

i4-.--RxD

Word Length (WL)
No. Bits
8
7
6
5

.....1====-----

Receiver Clock Source (RCS)
External receiver clock
Baud rate

Bits 3-0

.1..

fI

.£.
0
0
0
0
1
1
1
1
0
0
0
0
1

XTLI
XTLO

Selected Baud Rate (SBR)
..L ..Q... Baud
0
0
16x
0
1
50
1
0
75
109.92
1
1
134.58
0
0
0
1
150
1
0
300
1
1
600
0
1200
0
1
1800
0
2400
1
0
1
3600
1
4800
0
0
1
0
7200
0
9600
19,200
1

Figure 3.

Transmitter/Receiver Clock Circuits

Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a baud rate of '/,6 an external clock.
A 1 causes the Receiver to operate at the same baud rate as
is selected for the transmitter.

Word Length (Bits 5, 6)

Reset Initialization

These bits determine the word length to be used (5, 6, 7 or 8
bits).

765 4 3 2 1 0

I~I~I~I~I~I~I~I~I

RxC

Hardware reset (RES)

Stop Bit Number (Bit 7)

Program reset

This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1V2 stop bits if the word
length IS 5 with no parity selected. 1 stop bit if the word length
is 8 with parity selected. and 2 stop bits in all other configurations.

2-299

Asynchronous Communications Interface Adapter (ACIA)

R65C51
COMMAND REGISTER

Data Terminal Ready (Bit 0)

The Command Register controls specific modes and functions.

This bit enables all selected interrupts and controls the state of
the Data Terminal Ready (DTR) line. A 0 indicates the microcomputer system is not ready by setting the DTR line high. A
1 indicates the microcomputer system is ready by setting the
DTR line low. OTR line low. D'rR also enables and disables'
the transmitter and receiver.

Bits 7-6

1.

~

1

1
0

o
o

0

Bit 5

o

Bit 4

o

Bits 3-2

3

Receiver Interrupt Control (Bit 1)

Parity Mode Control (PMC)

This bit disables the Receiver from generating an interrupt when
set to a 1. The Receiver interrupt is enabled when this bit is set
to a 0 and Bit 0 is set to a 1.

Odd parity transmitted/received
Even parity transmitted/received
Mark parity bit transmitted
Parity check disabled
Space parity bit transmitted
Parity check disabled

Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTS) line and
the Transmitter interrupt.

Parity Mode Enabled (PME)
Parity 11)0de disabled
No par~y'blt generated
Parity check disabled
Parity mode enabled

Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 disables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
O. In the Receiver Echo Mode, the Transmitter returns each
transmission received by the Receiver delayed by one-half bit
time.

Receiver Echo Mode (REM)
Receiver normal mode
Receiver echo mode bits 2 and 3
Must be zero for receiver echo mode, RTS will
be low.

Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0 disables
parity bit generation by the Transmitter and parity bit checking
by the Receiver. A 1 bn enables generation and checking of
parrty bits.

Transmitter Interrupt Control (TIC)

2

o

0

o

1

o
1

Bit 1

o
1

RTS = High, transmitter disabled
RTS = low, transmit interrupt enabled
RTS = low, transmit interrupt disabled
RTS = low, transmit interrupt disabled
transmit break on TxD

Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the Transmitter, (even, odd, mark or space) and the type of parity check
done by the Receiver (even, odd, or no check).

Receiver Interrupt Request Disabled (IRD)
IRQ enabled (receiver)
IRQ disabled (receiver)

Reset Initialization
Bit 0

o

Data Terminal Ready (DTR)
Data terminal not ready (DTR high)*
Data terminal ready (OTR low)

76543 2 1

°

1010 10 I~ I~ I~ I~ I~I :~~~:~er=~t (RES)

NOTE
'The transmitter is disabled immediately. The receiver is
disabled but will first complete receiving a byte in process
of being received.

2-300

Asynchronous Communications Interface Adapter (ACIA)

R65C51
INTERFACE SIGNALS

Interrupt Request (IRQ)

Figure 4 shows the ACIA interface signals associated with the
microprocessor and the modem.

The iRQ pin is an interrupt output from the interrupt control logic.
It is an open drain output, permitting several devices to be connected to the common fRO' microprocessor input. Normally a
high level, IRQ goes low when an interrupt occurs.

Data Bus (00-07)

CTS

00-D7

The eight data line (00-07) pins transfer data between the processor and the ACIA. These lines are bi-directional and are normally high-impedance except during Read cycles when the
ACIA is selected.

TxD

IRQ

OCD

RJW

OSR

CSD

Chip Selects (CSo,~)

RxC

CS1
RSD

XTLI

RS1

XTLO

'2

The two chip select inputs are normally connected to the processor address lines either directly or through decoders. The
ACIA is selected when CSO is high and CS1 is low. When the
ACIA is selected, the internal registers are addressed in accordance with the register select lines (RSO, RS1).

DTR

RES

Register Selects (RSO, RS1)

RTS

The two register select lines are normally connected to the processor address lines to allow the processor to select the various
ACIA internal registers. Table 1 shows the internal register
select coding.

vee
RxD
VSS

Figure 4.

ACIA Interface Diagram
Table 1.

ACIA Register Selection
Register Operation

MICROPROCESSOR INTERFACE
Reset (RES)
During system in~ialization a low on the RES input causes a
hardware reset to occur. Upon reset, the Command Register
and the Control Register are cleared (all bits set to 0). The
Status Register is cleared with the exception of the indications
of Data Set Ready and Data Carrier Detect, which are externally
controlled by the DSR and DCD lines, and the transmitter Empty
bit, which is set. RES must be held low for one ¢2 clock cycle
for a reset to occur.

RS1

RSD

R/W =L_

RiW =

L

L

Write Transmit Data
Register

Read Receiver
Data Register

L

H

Programmed Reset
(Data is "Don't
Care")

Read Status
Register

H

L

Write Command
Register

Read Command
Register

H

H

Write Control
Register

Read Control
Register

High

Input Clock ~2)
The input clock is the system ¢2 clock and clocks all data transfers between the system microprocessor and the ACIA.

Only the Command and Control registers can both be read and
written. The programmed Reset operation does not cause any
data transfer, but is used to clear bits 4 through 0 in the Command register and bit 2 in the Status Register. The Control Register is unchanged by a programmed Reset. It should be noted
that the programmed Reset is slightly different from the hardware Reset (~); refer to the register description.

Read/Write (R/W)
The R/W input, generated by the microprocessor controls the
direction of data transfers. A high on the R/W pin allows the
processor to read the data supplied by the ACIA, a low allows
a write to the ACIA.

2-301

2

Asynchronous Communications Interface Adapter (ACIA)

R65C51·
ACIAIMODEM INTERFACE

Clear to Send (CTS)

Crystal Pins (XTLI, XTLO)

The CTS input pin controls the transmitter operation. The enable
state is wfth C'fS low. The transmitter is automatically disabled
if ffi is high.

These pins are normally directly connected to the parallel mode
external crystal (1.6432 MHz) to derive the various baud rates.
Alternatively, an externally generated clock can drive the XTLI
pin, in which case the XTLO pin must float. XTLI is the input
pin for the transmit clock.

Data Terminal Ready (DTR)
This output pin indicates the status of the ACIA to the modem.
A low on DTR indicates the ACIA is enabled, a high indicates
it is disabled. The processor controls this pin via bit 0 of the
Command Register.

Transmit Data '(TxD)
The TxD output line transfers serial nonreturn-to-zero (NRZ)
data to the modem. The least significant bit (LSB) of the Transmit
Data Register is the first data bit transmitted and the rate of data
transmission is determined by the baud rate selected or under
control of an external clock. This selection is made by programming the Control Register.

Data Set Ready ('D'S'R)
The DSR input pin indicates to the ACIA the status of the
modem. A low indicates the "ready" state and a high, "notready."

Data Carrier Detect (DCD)

Receive Data (RxD)

The DCD input pin indicates to the ACIA the status of the carnerdetect output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is not.

The RxD input line transfers serial NRZ data into the ACIA from
the modem, LSB first. The receiver data rate is either the programmed baud rate or under the control of an externally generated receiver clock. The selection is made by programming
the Control Register.

TRANSMITTER AND RECEIVER OPERATION
Continuous Data Transmit

Receive Clock (RxC)

In the normal operating mode, the interrupt request output (IRQ)
signals when the ACIA is ready to accept the next data word to
be transmitted. This interrupt occurs at the beginning of the Start
Bit. When the processor reads the Status Register of the ACIA,
the interrupt is cleared.

The RxC is a pI-directional pin which is either the receiver 16x
clock input o'r the receiver 16x clock output. The latter mode
results if the internal baud rate generator is selected for receiver
data clocking.

The processor must then identify that the Transmit Data Register is ready to be loaded and must then load it with the next
data word. This must occur before the end of the Stop Bit, otherwise a continuous "MARK" will be transmitted. Figure 5 shows
the continuous Data Transmit timing relationship.

Request to Send (RTS)
The RTS output pin controls the modem from the processor.
The state of the RTS pin is determined by the contents of the
Command Register.

CHAR#n+1

CHAR#n

/

TxD

CHAA#n+3

'J

,

'J

I
J

I

I

I

I

,

I

Lm

l

ls""5"R ~ ~ hl:js,.p\S'·"ffi ~ ~ hl:j s..p\s'""5"R ~ ~ hl:js··+·,·ffi ~ ~ ffis,·pL
I

J

iRa

CHAR#n+2

'J

iJIJ

iJIl

UU'

'"~-")
INTERRUPT
ITRANSMIT DATA
REGISTER EMPTY)

~._._~u .~".~,

'-'\

__
PROCESSOR READS STATUS
REGISTER CAUSES'iiiQ

LDADNEWDATA
IN THIS TIME
INTERVAL. OTHERWISE,

~O::!~~~~:;~~ARK"

TO CLEAR'

Figure 5.

Continuous Data Transmit

2-302

Asynchronous Communications Interface Adapter (ACIA)

R65C51
Continuous Data Receive

read the data word before the next interrupt, otherwise the
Overrun condition occurs. Figure 6 shows the continuous Data
Receive Timing Relationship.

Similar to the Continuous Data Transmit case, the normal
operation of this mode is to assert IRQ when the ACIA has
received a full data word. This occurs at about 9/,6 point through
the Stop Bit. The processor must read the Status Register and

CHAR#n

RxD

rna

CHAR#n+3

CHAR#n+2

CHAR#n+1

/

'-/

"\.

'-/

'-/

I

I

I

I

I

I

I

I

LJn

L

lStart5"EI ]~;oEJ s.o·IStlrtG"EJ ~ ~ c:;r:] StopISt.rtG"EJ ~ ~ rnSto·ls. ,.GF] ~ ~ rns.o·L

Ur

-1IJ
PROCESSOR

)

INTERRUPT OCCURS

~:~~:6:.8~1~~O

PARITY. OVERRUN.
AND FRAMING ERROR

L..J\

i~

~

PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL; OTHERWISE,
OVERRUN OCCURS

PROCESSOR READS ~TUS
~~~I~!:. CAUSES IRQ

ALSO. UPDATED

Figure 6.

Continuous Data Receive

Transmit Data Register Not Loaded by Processor
When the processor finally loads new data, a Start Bit immediately occurs, the data word transmission is started, and another
interrupt is initiated, signaling for the next data word. Figure 7
shows the timing relationship for this mode of operation.

If the processor is unable to load the Transmit Data Register in
the allocated time, then the TxD line goes to the "MARK" condition until the data is loaded. IRQ interrupts continue to occur
at the same rate as previously, except no data is transmitted.

CONTINUOUS "MARK"

CHAR#n
I

CHAR#n+l

TxO

INTERRUPTS
CONTINUE AT
CHARACTER RATE,
EVEN THOUGH
NO DATA IS
TRANSMITTED

EMPTY

PROCESSOR
READS
STATUS
REGISTER

Figure 7.

\

WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY

Transmit Data Register Not Loaded by Processor

2-303

CHAR#n+2

Asynchronous Communications Interface Adapter (ACIA)

R65C51
Effect of CTS on Transmitter

CTS is the Clear-to-Send signal generated by the modem. It is
normally low (true state) but may go high in the event. of some
modem problems. When this occurs, the TxD line goes to the
"MARK" condition after the entire last character (including parity
and stop bit) have been transmitted. Bit 4 in the Status Register
CHAR#n

indicates that the Transmitter Data Register is not empty and
IRQ is not asserted. CTS is a transmit control line only, and has
no effect on the ACIA Receiver Operation, Figure 8 shows the
timing relationship for this mode of operation.

CHAR#n+1

CONTINUOUS "MARK"

TxD

iRa
1i'!Q
NOT CLEAR~TO.SEND

I'

IS NOT ASSERTED

AGAIN UNTIL
GOES LOW

m

CLEAR-TO·SEND

CTs GOES

HIGH,
INDICATING MODEM
IS NOT READY TO
RECEIVE DATA TxD
GOES TO "MARK" CONDITION
AFTER COMPLETE CHARACTER
IS TRANSMITTeD

Figure 8.

Effect of CTS on Transmitter

Effect of Overrun on Receiver
but the Overrun status bit is set. Thus, the Data Register will
contain the last valid data word received and all following data
IS lost. Figure 9 shows the timing relationship for this mode.

If the processor does not read the Receiver data Register in the
allocated time, then, when the following interrupt occurs, the
new data word is not transferred to the Receiver Data Register,
CHAR#n

~/

I

RxD ]:jSt"tG""EI

CHAR#n+1
"-/

I

CHAR#n+2
"-/

I~Stop\s""G"EJ ~ ~ EEJSto+."

I

I
PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL

I

[BOEr ~

~

PROCESSOR
READS

I

STATUS
REGISTER

liEjSto p\st"t[B:8

RECEIVER DATA REGISTER

OVERRUN BIT seT IN
STATUS REGISTER

Effect of Overrun on Receiver
2-304

I

NOT UPDATED, BECAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA, OVERRUN
BIT SET IN STATUS
REGISTER

"-'------.---/ ~

Figure 9.

CHAR#n+3
"-/

I.

~~ ~

R65C51

Asynchronous Communications Interface Adapter (ACIA)

Echo Mode Timing
In Echo Mode, the TxD line re-transmits the data on the RxD
line, delayed by '12 of the bit time, as shown in Figure 10.

RxO

]=lStortrqs:]==liEJs,opls,artru==liEJs,opls,."GI

\\\ \

\\

\ \\ \\ \\ \

Figure 1O.

fJ

Echo Mode Timing

Effect of CTS on Echo Mode Operation
In Echo Mode, the Receiver operation is unaffected by CTS,
however, the Transmitter is affected when CTS goes high, i.e.,
the TxD line immediately goes to a continuous "MARK" condition. In this case, however, the Status Request indicates that

the Receiver Data Register is full in response to an IRQ, so the
processor has no way of knowing that the Transmitter has
ceased to echo. See Figure 11 for the timing relationship of this
mode.

CHAR#n+1

CHAR#n

CHAR#n+2

CHAR#n+3

NOT·CLEAR·TO·SEND

TxO

~~J8Nlp

I
II

CONTINUOUS "MARK" UNTIL.ffi GOES lOW

s,opIS""1 I I II
80

8,

82

~,o~)

"FALse" CONDITION

NORMAL
RECEIVER DATA
REGISTER FUll
INTERRUPTS

I

Figure 11.

Effect of CTS on Echo Mode

2-305

"-

R65C51

Asynchronous Communications Interface Adapter (ACIA)

Overrun in Echo Mode
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as a normal overrun in Receive Mode. For the reo
transmitted data, when overrun occurs, the TxD line goes to the

"MARK" condition until the first Start Bit after the Receiver Data
Register is read by the processor. Figure 12 shows the timing
relationship for this mode.
CHAR1tx+1

CHAR#n

~/

!

RxD } : l S t . , , [ % E ]

~_ _ _L...._ _~"

"'-

~ ~ [~~E}o+."1 BO I8,

I

"'1-1'
TxD

_~--'~~ EEJStopISt·"ffi~~ EE

L-.......

-""""'un

IiI-

UD

80

If)-L--'---'

/r----'---

LllJ

8,

!--L_-'---'

I
PRDCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER

!

PROCESSOR FINALLY

TxD DATA

READS RECEIVER

RESUMES

==~

DATA REGISTER,

LAST VALID
CHARACTER I#nl

FULL
PROCESSOR
REGISTER

PROCESSOR
INTERRUPT

OVERRUN OCCURS
TxD GOES TO
"MARK"

READS

STATUS

FOR CHAR#x
IN RECEIVER
DATA REGISTER

CONDITION

Figure 12.

Overrun in Echo Mode

Framing Error
Framing Error is caused by the absence of Stop Sitts) on
received data. A Framing Error is indicated by the setting of bit
4 in the Status Register at the same time the Receiver Data
Re~er Full bit is set, also in the Status Register. In response
to IRQ, generated by RDRF, the Status Register can also be

RxD
IEXPECTEDI

--'_-'---I

RxD
IACTUALI

--'_-'---I

NOTES:

checked for the Framing Error. Subsequent data words are
tested for Framing Error separately, so the status bit will always
reflect the last data word received. See Figure 13 for Framing
Error timing relationship.

PROCESSOR

1. FRAMING ERROR DOES NOT

INTERRUPT,
FRAMING

INHIBIT RECEIVER OPERATION.

ERROR

2. IF NEXT DATA WORD IS OK.
FRAMING ERROR IS CLEARED.

BIT seT

Figure 13.

Framing Error

2·306

Asynchronous Communications Interface Adapter (ACIA)

R65C51
Effect of DCD on Receiver

DCD is a modem output indicating the status of the carrier-frequency-detection circuit of the modem. This line goes high for
a loss of carrier. Normally, when this occurs, the modem will
stop transmitting data some time later. The ACIA asserts IRQ
whenever DCD changes state and indicates this condition via
bit 5 in the Status Register.

Once such a change of state occurs, subsequent transitions will
not cause interrupts or changes in the Status Register until the
first interrupt is serviced. When the Status Register is read by
the processor, the ACIA automatically checks the level of the
DCD line, and if it has changed, another IRQ occurs (see Figure
14).

fJ

CONTINUOUS ''MARK''

f

NORMAL
PROCESSOR
INTERRUPT PROCESSOR

AS LONG AS
IS HIGH,

NO INTERRUPT

0C0

INTERRUPT

NO FURTHER
INTERRUPTS

FOR i5Ci5
GOING HIGH

FOR RECEIVER
WILL OCCUR

PROCESSOR
INTERRUPT
FOR DCD
GOING LOW

WILL OCCUR
HERE. SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT

PROCESSOR /
INTERRUPT

FOR
RECEIVER
DATA

DETECTED

Figure 14.

Effect of OeD on Receiver

Timing with 11f2 Stop Bits
It is possible to select 1V2 Stop Bits, but this occurs only for
5-bit data words with no parity bit. In this case, the IRQ asserted
for Receiver Data Register Full occurs halfway through the

trailing half-Stop Bit. Figure 15 shows the timing relationship for
this mode.

CHAR#n
I

CHAR#n+1

RxD

LJ]]
t
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGHT THE 112

STOP BIT

Figure 15. Timing with 1112 Stop Bits

2-307

L

Asynchronous Communications Interface A~apter (ACIA)

R65C51
Transmit Continuous "BREAK"

Note

This mode is selected via the ACIA Command Register and
causes the Transmitter to send continuous "BREAK" characters, beginning with the next character transmitted. At least one
full "BREAK" character will be transmitted, even if the processor
quickly re-programs the Command Register transmit mode.
Later, when the Command Register is programmed back to
normal transmit mode, an immediate Stop Bit will be generated
and transmission will resume. Figure 16 shows the timing relationship for this mode.

~/

T"O

"

~Start~--I BNIPIStoplstart
-.J"U"~
t....:.l---1 _ I

I

If, while operating in the Transmit Continuous "BREAK"
mode, the CTS should go to a high, the TxD will be
overridden by the CTS and will go to continuous "MARK"
at the beginning of the next character transmitted after the
CTS goes high.

,,/

/

- - - - -..L. . . .J'L-.. .&'. ii
80

B1

I

BN

I

P

Stop

1,.1

~_f~:f~[]iEJS'OP,s

~---II

I

~

PERIOD DURING

f o - - - - - - - + j - ~EH~~~::OCESSOA
CONTINUOUS
"BREAK" MODE

POINT AT WHICH
PROCESSOR

NORMAL

SELECTS

INTERRUPT

. ,.5Fl

PROCESSOR
INTERRUPT

TO LOAD

NORMAL

TRANSMIT

TRANSMIT

DATA

MODE

Figure 16. Transmit Continuous "BREAK"

Receive Continuous "BREAK"
In the event the modem transmits continuous "BREAK" characters, the ACIA will terminate receiving. Reception will resume
only after a Stop Bit is encountered by the ACIA. Figure 17

RxD

,...--r--r-",

shows the
characters.

timing

relationship

CONTINUOUS "BREAK"

. /
]::;Lffiil",,",...'I_B_O_I_B_'___IB_N__P_I.....,·lrf-(..L1_..L..""""'rrS.artrq:]-

)u
PROCESSOR
INTERRUPT

FOA
RECEIVER
DATA AEGISTER
FULL

for

1

~ ~

PROCESSOR INTERRUPT WITH
BREAK AND FRAMING ERAOR SET.
EVEN PARITY CHECK WILL ALSO
GIVE A PARITY ERROR BECAUSE
ALL ZEROS (CONTINUOUS BREAK)
REPRESENT EVEN PARITY.

Figure 17.

NMOO'-E
A

NO INTERRUPT

INTERRUPTS

SINCE RECEIVER
DISABLED UNTil
FIRST STOP BIT

Receive Continuous "BREAK"

2-308

=l±J

continuous

"/
TiS'"''

NORMAL
RECEIVER
INTERRUPT

Bo

"BREAK"

I I
B,

R65C51

Asynchronous Communications Interface Adapter (ACIA)

STATUS REGISTER OPERATION

MISCELLANEOUS

Because of the special functions of the vanous status btts, there
is a suggested sequence for checking them. When an interrupt
occurs, the ACIA should be interrogated, as follows:

1. If Echo Mode is selected, RTS goes low.
2. If Bit 0 of Command Register (DTR) is 0 (disabled), then:
a) All Interrupts are disabled, Including those caused by
DCD and DSR transttions.
b) Transmitter is disabled immediately.
c) Receiver IS disabled, but a character currently being
received Will be completed first.

1. Read Status Register
This operation automatically clears Bit 7 (IRQ). Subsequent
transitions on DSR and DCD will cause another Interrupt

3. Odd panty occurs when the sum of all the 1 btts In the data
word (including the panty bit) IS odd.

2. Check IRQ (Bit 7) in the data read from the Status Register
If not set, the Interrupt source IS not the ACIA.

4. In the receive mode, the received parity bit does not go into
the Receiver Data Register, but generates partty error or no
parity error for the Status Register.

3. Check DCD and DSR
These must be compared to their prevIous levels, which must
have been saved by the processor. If they are both 0 (modem
"on-line") and they are unchanged then the remaining bits
must be checked

5. Transmitter and Receiver may be in full operation simultaneously. This is "full-duplex" mode.
6. If the RxD line Inadvertently goes low and then high nght
after a Stop Bit, the ACIA does not interpret this as a Start
Bit, but samples the line again halfway Into the bit to determine if it IS a true Start Bit or a false one. For false Start Bit
detection, the ACIA does not begin to receive data, Instead,
only a true Start Bit inrtlates receiver operation.

4. Check RDRF (Bit 3)
Check for Receiver Data Register Full.
5. Check Parity, Overrun, and Framing Error (Bits 0-2) If the
Receiver Data Register IS full

7. Precautions to conSider wtth the crystal oscillator circuit:
6. Check TORE (Bit 4)

a) The external crystal should be a "series" mode crystal.
b) The XTALI input may be used as an external clock input.
The unused pin (EXTALO) must be floating and may not
be used for any other function.

Check for Transmitter Data Register Empty.
7. If none of the above conditions exist, then CTS must have
gone to the false (high) state.

8. DCD and DSR transttions, although causing immediate processor interrupts, have no affect on transmitter operation.
Data will continue to be sent, unless the processor forces
transmitter to turn off. Since these are high-impedance inputs,
they must not be permitted to float (un-connected}. If unused,
they must be terminated either to GND or Vcc.

PROGRAM RESET OPERATION
A program reset occurs when the processor performs a write
operation to the ACIA with RSO low and RS1 high. The program
reset operates somewhat different from the hardware reset
(RES pin) and is described as follows:

GENERATION OF NON-STANDARD BAUD RATES
Divisors
The Internal counter/divider circUit selects the appropriate diVIsor for the crystal frequency by means of bits 0-3 of the ACIA
Control Register, as shown in Table 2.

1. Internal registers are not completely cleared. Check register
formats for the effect of a program reset on internal registers.
2. The DTR line goes high Immediately.

Generating Other Baud Rates
By using a different crystal, other baud rates may be generated.
These can be determined by:

3. Receiver and transmitter Interrupts are disabled Immediately.
If IRQ is low when the reset occurs, it stays low until serViced, unless Interrupt was caused by DCD or DSR transrtion.

Baud Rate =

Crystal Frequency

-..:....--...:....--=--Divisor

4. DCD and DSR Interrupts are disabled Immediately. If IRQ IS
low and was caused by DCD or DSR, then It goes high, also
DCD and DSR status bits subsequently will follow the input
lines, although no interrupt will occur.

Furthermore, it is possible to drive the ACIA with an off-chip
oscillator to achieve other baud rates. In this case, XTALI (pin
6) must be the clock input and XTALO (pin 7) must be a noconnect.

5. Overrun cleared, If set.

2-309

fJ

R65C51

Asynchronous Communications Interface Adapter (ACIA)

Table 2.
Control
Register
Bits

Divisor Selected
For The
Internal Counter

3

2

1

0

0

0

0

0

No Divisor Selected

0

0

0

1

36.864

0

0

1

0

24,576

0

0

1

1

16,769

0

1

0

0

13,704

0

1

0

1

12,288

0

1

1

0

6,144

0

1

1

1

3,072

1

0

0

0

1,536

1

0

0

1

1,024

1

0

1

0

768

1

0

1

1

512

1

1

0

0

384

1

1

0

1

256

1

1

1

0

192

1

96

1

1

1

Divisor Selection
Baud Rate Generated
With 1.8432 MHz
Crtstal

16 x External Clock
at Pin RxC
1.8432 x 10·
36.864
1.8432 x 10·
24,576
1.8432 x 10·
16,769
1.8432 x 10.
13,704
1.8432 x 10·
12,288
1.8432 x 10"
6,144
1.8432 x 10·
3,072
1.8432 x 10·
1,536
1.8432 x 10"
1,024
1.8432 x 10·
768
1.8432 x 10"
512
1.8432 x 10·
384
1.8432 x 10·
256
1.8432 x 10·
192
1.8432 x 10·
96

2-310

Baud Rate Generated
With a Crystal
of Frequency (F)

16 x External Clock
at Pin RxC
F

50

---

75

---

109.92

---

134.51

---

150

F
-12,288
-

300

-6,144
--

600

---

1,200

-1,536
--

1,800

---

2,400

---

3,600

-512
--

4,800

-384
--

7,200

-256
--

9,600

---

19,200

---

36.864
F

24,576
F

16,769
F

13,704

F

F

3,072
F

F

1,024
F

768
F

F

F

F

192
F

96

R65C51

Asynchronous Communications Interface Adapter (ACIA)

DIAGNOSTIC LOOP-BACK OPERATING MODES
A simplified block diagram for a system incorporating an ACIA
is shown in Figure 18.

loop-back operation. In this way, the processor can easily perform local loop-back diagnostic testing.

It may be desirable to include in the system a facility for "Ioopback" testing, of which there are two kinds:

Remote loop-back does not require this circuitry, so LLB must
be set low. However, the processor must select the following:

1. Local Loop-Back

1. Control Register bit 4 must be 1, so that the transmitter clock
equals the receiver clock.

Loop-back from the point of view of the processor. In this
case, the Modem and Data Link must be effectively disconnected and the ACIA transmitter connected back to Its own
receiver, so that the processor can perform diagnostic checks
on the system, excluding the actual data channel.

2. Command Register bit 4 must be 1 to select Echo Mode.
3. Command Register bits 3 and 2 must be 1 and 0, respectively to disable IRQ interrupt to transmitter.

2. Remote Loop-Back

4. Command Register bit 1 must be 0 to disable IRQ Interrupt
for receiver.

Loop-back from the point of view of the Data Link and
Modem. In this case, the processor, Itself, is disconnected
and all received data is immediately retransmitted, so the
system on the other end of the Data Link may operate independent of the local system.

In this way, the system re-transmits received data without any
effect on the local system.

The ACIA does not contain automatic loop-back operating
modes, but they may be implemented with the addition of a
small amount of external circuitry. Figure 19 indicates the necessary logic to be used with the ACIA. The LLB line is the positive-true signal to enable local loop-back operation. Essentially,
LLB = high does the following:

MICROPROCESSOR

1. Disables outputs TxD, DTR, and RTS (to Modem).
2. Disables inputs RxD, DCD, CTS, DSR (from Modem).
3. Connects transmitter outputs to respective receiver inputs
(Le., TxD to RxD, DTR to DCD, RTS to CTS).
TO DATA LINK

LLB may be tied to a peripheral control pin (from an R65C21
or R65C24, for example) to provide processor control of local

I

Figure 18.
R6551

RxD DCD CTS DSR

RTS DTR TxD

LLB

SEL

-r-

STB

1VW
2V
3V
4V

+5

SEl

±

STB

C-

RxD
DCD
CTS
DSR

TxD
DTR
RTS

1V
2V
3V

74157 4V
1B
1A
2B
2A
3B
3A
4B
4A

I

I

74157
1B
1A
2B
2A
3B
3A
4A
~4B

'----

Simplified System Diagram

-

l·oo~
J

NOTES: 1. HIGH ON LLB SELECTS LOCAL LOOP-BACK MODE.
2. HIGH ON 74157 SELECT INPUT GATES "B" INPUTS
TO "V" OUTPUTS; LOW GATES "A" TO "V".

Figure 19.

Loop-Back Circuit Schematic
2-311

R65C51

Asynchronous Communications Interface Adapter (ACIA)

READ TIMING DIAGRAM

1--------tCCY------~

Timing diagrams for transmit with external clock, receive with
external clock, and iFiQ generation are shown in Figures 20, 21
and 22, respectively. The corresponding timing characteristics
are listed in Table 3.

XTLI
(TRANSMIT
CLOCK INPUT";")_ _J

Table 3. Transmlt/Aecelve Characteristics
1 MHz

2 MHz

TxD

Symbol

Min

Max

Min

Max

Unit

TransmiVReceive
Clock Rate

tccv

400'

-

400'

-

ns

Transmit/Receive
Clock High Time

tCH

175

-

175

-

ns

TransmiVRecelve
Clock Low Time

tCl

175

-

175

-

ns

XTLI to TxD
Propagation Delay

tDD

-

500

-

500

ns

RTS Propagation
Delay

tOlV

-

500

-

500

ns

IRQ Propagation
Delay (Clear)

t'RQ

-

500

-

500

ns

Characteristic

NOTE: TxD RATE IS 1/16 TxC RATE

Figure 20.

NOTE: RxD RATE IS 1116 RxC RATE

Figure 21.

Notes:
(t R, tF = 10 to 30 ns)
'The baud rate with external clocking is: Baud Rate

Transmit Timing with External Clock

=

Receive External Clock Timing

1
16 x tCCY

• tDLY

Q

IRQ
_________________tl_RJ) (CLEAR) _

Figure 22.

2-312

Interrupt and Output Timing

R65C51

Asynchronous Communications Interface Adapter (ACIA)

AC CHARACTERISTICS
1 MHz

2 MHz

Symbol

Min

Max

Min

Max

Unit

02 Cycle Time

teye

1000

500

te

400

200

-

ns

02 Pulse Width
Address Set-Up Time

t ACW

120

-

60

-

ns

Address Hold Time

tCAH

0

-

0

RfW Set-Up Time

t wcw

120

Parameter

R/W Hold Time

tCWH

0

Data Bus Set-Up Time

tocw

120

Data Bus Hold Time

tHW

20

-

ns

-

ns

60

-

ns

0

-

ns

60
10

-

ns

ns

Read Access Time (Valid Data)

tCoR

-

200

-

100

ns

Read Hold Time

tHR

20

10

tCoA

40

-

ns

Bus Active Time (Invalid Data)

-

20

ns

Notes:
I. Vcc = 50V ±5%
2. TA = TLtoT H
3 tR and tF = 10 to 30 ns

tR

2

-I:

tc

tCYC
j--tF

·1

VIH

"\

-

VIL
I-tCAH.

-tACW-

VIH
CSo, CS " RS o, RS,
VIL
I--twcw-

R/W

I--tcWH-1

!

\

VIH
VIL

i'CW-I-. '"W~v,"
DATABUS-==
VIL

Figure 23.

R/W

DATA BUS

Write Timing Diagram

1-'W~J-tCDR_1

VIH

~tHR-1

l-tCDA-a:

Figure 24.

Read Timing Characteristics

2·313

}

VIL

--

R65C51

Asynchronous Communications Interface Adapter (ACIA)

ABSOLUTE MAXIMUM RATINGS·
Parameter

Symbol

Supply Voltage

Value

Unit

Vee

-0.3 to +7.0

Vdc

Input Voltage

VIN

-0.3 to Vee +0.3

Vdc

Output Voltage

VOUT

-0.3 to Vee +0.3

Vdc

Operating Temperature
Commercial
Industrial

TA

Storage Temperature

TSTG

• NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document Is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

·C

o to

+70
-40 to +85
-55 to +150

·C

OPERATING CONDITIONS
Parameter

Symbol

Value

Supply Voltage

Vee

5V ±5%

Temperature Range
Commercial
Industrial

TA
O· to 70·C
- 40·C to + 85·C

DC CHARACTERISTICS
(Vee = 5.0V

±5%,

= 0, TA = TL to TH, unless otherwise noted)

Vss

Parameter

Symbol

Min

Typ

Max

Unit
V

Test Conditions

Input High Voltage

VIH

2.0

-

Vee

Input Low Voltage

Vil

-0.3

-

+0.8

V

Input Leakage Current:
~2. ANY. REB.CSO. CSl.RSO. RS1,CTS, RxO,~, OSR

liN

-

±1

±2.5

,.A

VIN = OV to Vee
Vee = 5.25V

Input Leakage Current (Three State Off)
00-07

ITSI

-

±2

±10

,.A

VIN = O.4V to 2.4V
Vee = 5.25V

Output High Voltage:
00-07, TxO, RxC, RTS, OTR

VOH

2.4

-

-

V

Vee = 4.75V
ILOAD = -100,.A

Output Low Voltage:
00-07, TxO, RxC.

VOL

-

-

0.4

V

Vee = 4.75V
ILOAD = 1.6 rnA

IOH

-200

-

p.A

VOH = 2.4V

Output Low Current (Sinking):
00-07, TxO. RxC, RTS, OTR, IRQ

IOL

1.6

-

rnA

VOL = O.4V

Output Leakage Current (all state): IRQ

IOFF

-

10

,.A

Your = 5.0V

Power DiSSipation

Po

-

10

mW/MHz

20
10

pF
pF

10

pF

RTS,

OTR, IRQ

Output High Current (Sourcing):
00-07, TxO, RxC, RTS,OTR

Input Capacitance
All except ~2
~2

Output Capacitance

-

CeLK
CIN

-

Cour

-

Notes:
1. All units are direct current (de) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates Inward flow.
3. Typical values are shown for Vee = 5.0V and TA = 25·C.

2·314

-400

7

Vee = 5.0V
VIN = OV
f = 2 MHz
TA = 25·C

R65C51

Asynchronous Communications Interface Adapter (ACIA)

PACKAGE DIMENSIONS

2S·PIN CERAMIC DIP

2S·PIN PLASTIC DIP

I

(.550)
(.530)

'p ,.,

::::~:---'~I

r-

r-+(.OOl}

1

I-

rii=1

fJ

LM-n-rTTTTM"T"TTTT"1rTTTTT"~~

I

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R65C52

'1'

Rockwell

R65C52
DUAL ASYNCHRONOUS COMMUNICATIONS
INTERFACE ADAPTER (DACIA)
PRELIMINARY

DESCRIPTION

FEATURES

The Rockwell CMOS R65C52 Dual Asynchronous Communications Interface Adapter (DACIA) provides an easily implemented,
program controlled interface between 8-bit microprocessor-based
systems and serial communication data sets and modems,

•

Low power CMOS N-well silicon gate technology

• Two independent full duplex channels with buffered receivers
and transmitters.

The DACIA has an internal baud rate generator. This feature elimInates the need for multiple component support circuits, a crystal
being the only other part required. The Transmitter baud rate can
be selected under program control to be either 1 of 15 different
rates from 50 to 38,400 baud, or at 1/16 times an external clock
rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate, or at 1/16 times the external
clock rate. The DACIA is programmable for word lengths of 5,6,
7 or 8 bits; even, odd, or no parity; and 1 or 2 stop bits.
The DACIA IS designed for maximum programmed control from
the microprocessor (MPU) to simplify hardware implementation.
Dual sets of registers allow independent control and monitoring
of each channel. The DACIA also provides a unique, programmable Automatic Address Recognition Mode for use in a multidrop environment.

•

Data set/modem control functions

•

Internal baud rate generator with 15 programmable baud
rates (50 to 38,400)

•

Program-selectable internally or externally controlled receiver
rate

•

Programmable word lengths, number of stop bits, and panty
bit generation and detection

•

Programmable interrupt control

•

Programmable control of edge detect for DCD, DSR, DTR,
RTS, and CTS

•

Program-selectable serial echo mode for each channel

• Automatic Address Recognition Mode for multi-drop operation.
• Up to 4 MHz host bus operation
• 5.0 Vdc ± 5% supply requirements
• 40-pin plastic or ceramic DIP

The Control Register and Status Register permit the MPU to
easily select the R65C52's operating modes and determine
operational status.

• Compatible with R6500 and R65COO microprocessors and
R6500/* microcomputers.

The Interrupt Enable Registers (IER) and Interrupt Status
Registers (ISR) allow the MPU to control and monitor the interrupt
capabililieS of the DACIA.

ORDERING INFORMATION

• Full TTL or CMOS input/output compatibility

The Control and Format Register (CFR) permits selection of baud
rates, word lengths, parity and stop bits as well as control of DTR
and RTS output signals.

Part Number:
R65C52

L

The Status Register (SR) gives the MPU access to the state of
the modem control lines, framing error, transmitter underrun and
break conditions.
The Compare Data Registers (CDR) hold the data value to be used
in the compare mode and the Transmit Break Register (TBR)
commands a Transmit Break and provides for parity/address
recognition, for Automatic Address Mode.

~

L....~~~

The Transmitter Data Register and Receiver Data Register are
used for temporary data storage of input and output data.

Document No. 29651N68

2-316

~, ~

"m,,,"'"'"
e"""
'.1
Blank =
DOC to + 7DoC
E

= - 4DoC

to + 85°C

Frequency Range
2 = 2 MHz
4 = 4 MHz
Package
C = Ceramic
P = PlastiC

Product Description Order No. 2165
Rev. 2, October 1984

Dual Asynchronous Communications Interface Adapter (DACIA)

R65C52

REGISTER SELECTS (RSO, RS" RS2)
RES

Vcc

N/C

CS

The three register select lines are normally connected to the processor address lines to allow the MPU to select the various internal registers. Table 1 shows the internal register select coding and
identifies the abbreviations (ABBR) used throughout the text for
each register.

RJW

XTALI
XTALO
CLKOUT
N/C
OSR2
OC02
CTS2
RTS2
IRQ2
Rx02
OTR2
Tx02
TxC
07
06
05

RS2
RS1
RSO

N/C

READ/WRITE (R/W)

OSR1
OC01
CTS1
RTS1
IRQ1
Rx01
OTR1
Tx01
RxC
DO
01
02

04

The RiW input, generated by the microprocessor, controls the
direction of data transfer. A high on the RiW line indicates a read
cycle, while a low indicates a write cycle.

CHIP SELECT (CS)
The chip select input is normally connected to the processor
address lines either directly or through decoders. The DACIA
latches address and RiW inputs on the falling edge of CS and
latches the data bus inputs on the rising edge of CS.

RESET (RES)

03

Vss

During system initialization a low level on the RES input causes a
RESET to occur. At this time the IER's are set to $80, the DTR and
RTS lines go to the high state, Ihe RDR register is cleared,
the TBR is set to $OF, the compare mode is disabled, and the CTS,
DCD, DSR flags are cleared. No other bits are affected.

Note: N/C indicates no connection

Figure 1.

R65C52 Pin Configuration

INTERFACE SIGNALS

TRANSMIT DATA (TXD1, TXD2)

Figure 2 shows the DACIA interface signals associated with the
microprocessor and the modem.

The TxD outputs transfer serial non-return to zero (NRZ) data to
the data communications equipment (DCE). The data is transferred, LSB first, at a rate determined by the baud rate generator.

DATA BUS (00-07)

RECEIVE DATA (RXD1, RXD2)

The 00-07 pins are eight data lines that transfer data between
the microprocessor (MPU) and the DACIA. These lines are bidirectional and are normally high-impedance except during READ cycle
when the DACIA is selected.

R/W
CS
RES

or
R6500/*

.A

.A

<...00-07

DATA
BUS
BUFFERS

CLOCK
LOGIC

l

ACIA
CHANNEL 1

RxC
XTALI
CLKOUT
XTALO
TxC

DATA

110
MUX

ACIA2
INTERRUPT
LOGIC

Figure 2.

CTS1
OC01
OSR1
RxD1
Tx01
OTR1
RTS1

ACIA1 BAUD
RATE SELECT

110 CONTROL
AND
REGISTER
SELECT
LOGIC

RSO
RS1
RS2

,RQ2

ACIA1
REGISTERS
AND
CONTROL
LOGIC

ACIA1
INTERRUPT
LOGIC

iRQ1

R6500,
R65COO,

The RxD inputs transfer serial NRZ data into the DACIA from the
DCE, LSB first. The receiver baud rate is determined by the baud
rate generator.

ACIA2 BAUD
RATE SELECT

ACIA2
REGISTERS
AND
CONTROL
LOGIC

DACIA Interface Signals

2-317

RTS2
DTR2
TxD2
RxD2
DSR2
OCD2
CTS2

1

J

ACIA
CHANNEL 2

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

CLEAR TO SEND (CTS1, CTS2)

REQUEST TO SEND (RTS1, RTS2)

The CTS control line inputs allow handshaking by the transmitter.
When CTS is low, the data is transmitted continuously. When CTS
is high, the Transmit Data Register empty bit in the ISR is not set.
The word presently in the Transmit Shift Register is sent normally.
Any active transition on the CTS lines sets the CTS bit in the
appropriate ISA. The CTS status bit in the CSR reflects the current high or low state of CTS.

These two lines may be used as general purpose outputs. They
are set high upon reset. Their state may be programmed by setting the appropriate bits in the CFR high or low. The state of the
RTS line is reflected by the RTS bit in the CSA.

DATA TERMINAL READY (DTR1, DTR2)
These two lines may be used as general purpose outputs. They
are set high upon reset. Their state may be programmed by setting the appropriate bits in the CFR high or low. The state of the
DTR line is reflected by the DTR bit in the CSA.

DATA CARRIER DETECT (DCD1, DCD2)
These two lines may be used as general purpose inputs. An active
transition sets the DCD bit in the,ISA. The DCD bit in the CSR
reflects the current state of the DCD line.

INTERRUPT REQUEST (IRQ1, IRQ2)
The IRQ lines are open-drain outputs from the interrupt control
logic. IRQ1 is associated with ACIA 1 and IRQ2 is associated with
ACIA2. These lines are normally high but go low when one of the
flags in the ISR is set, provided that its corresponding enable bit
is set in the lEA.

DATA SET READY (DSR1, DSR2)
These two lines may be used as general purpose inputs. An active
transition sets the DSR bit in the ISR. The DSR bit in the CSR
reflects the current· state of the DSR line.

Table 1.

HEX
ADDR
00

01

02

REGISTER SELECT
LINES
RS2
L

L

L

RSl
L

L

H

DACIA Register Selection

CONTROL AND FORMAT
REGISTER BITS

RSO
L

REG
ABBR

WRITE

READ

-

-

IERl
ISRl

INTERRUPT ENABLE
REGISTER 1

INTERRUPT STATUS
REGISTER 1

0

-

CFRl
SRl

CONTROL
REGISTER 1

STATUS
REGISTER 1

1

-

CFRl

FORMAT
REGISTER 1

INVALID
INVALID

H

L

REGISTER ACCESS

CFR-6

CFR-7

-

0

CDRl

COMPARE DATA
REGISTER 1

-

1

TBRl

TRANSMIT BREAK
REGISTER 1

INVALID

03

L

H

H

-

-

TORl
RDRl

TRANSMIT DATA
REGISTER 1

RECEIVE DATA
REGISTER 1

04

H

L

L

-

-

IER2
ISR2

INTERRUPT ENABLE
REGISTER 2

INTERRUPT STATUS
REGISTER 2

0

-

CFR2
SR2

CONTROL
REGISTER 2

STATUS
REGISTER 2

1

-

CFR2

FORMAT
REGISTER 2

INVALID

-

0

CDR2

COMPARE DATA
REGISTER 2

INVALID

-

1

TBR2

TRANSMIT BREAK
REGISTER 2

INVALID

TOR2
RDR2

TRANSMIT DATA
REGISTER 2

RECEIVE DATA
REGISTER 2

05

06

07

H

H

H

L

H

H

H

L

H

-

-

2-318

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

FUNCTIONAL DESCRIPTION

INTERRUPT LOGIC

Figure 3 is a block diagram of the DACIA which consists of two
asynchronous communications interface adapters with common
microprocessor interface control logic and data bus buffers. The
individual functional elements of the DACIA are described in the
following paragraphs.

The interrupt logic causes the IRQ lines (IRQ1 or IRQ2) to go low
when conditions are met that require the attention of the MPU.
There are two registers (the Interrupt Enable Register and the
Interrupt Status Register) involved in the control of interrupts in
the DACIA. Corresponding bits in both registers must be set to
cause an IRQ.

fJ
IAQ1

4--------1

RxD1
DATA

TxC
XTALI
CLKOUT

XTAL.O
AxC

RxD2

ACIA CHANNEL 2

~~~~1--------~

RTS2

--------1

IRQ2 ...

LEGEND
- - - -

0-;

COMMON LOGIC
TxD2

.........,........... == CONTROL LINES

~t=::>:: 8-8ITDATALINES

'-r-{

MUL11·BIT C8:TROl LINES

Figure 3.

DACIA Block Diagram

2-319

Dual Asynchronous Communications Interface Adapter (DACIA)

R65C52

parity bit, and there are two stop bits. The 10th bit (normal parity
bit) is an address/data indicator. A 1 means the 8 bits are an
address and a 0 means the 8 bits are data.

DATA BUS BUFFER
The Data Bus Buffer is a bidirectional interface between the
system data lines and the internal data bus. When RtW is low
and CS is low, the Data Bus Buffer writes data from the internal
data bus to the system data lines. When RtW is high and CS is
low, data is driven into the DACIA from the system data bus.
Table 2 summarizes the Data Bus Buffer states.

Table 2.

CLOCK CIRCUIT
The internal clock oscillator supplies the time base for the baud
rate generator. The oscillator can be driven by a crystal or an
external clock, or it can be disabled, in which case the time base
for the baud rate is generated by the Receiver External Clock
(RxC) and Transmitter External Clock (TxC) input pins. Figure 5
shows the three possible clock configurations.

Data Bus Buffer Summary

Control Signals
R/W
CS

Data Bus Buffer State

L

L

Write Mode -

H

L

Read Mode - Output Data

Crystal (XTAU, XTAlO)

Tn-State

These pins are normally connected to an external 3.6864 MHz
crystal used as the time base for the baud rate generator. As an
alternative, the XTLI pin may be driven with an externally
generated clock in which case the XTAlO pin must float.

TRANSMIT AND RECEIVE DATA REGISTERS

Receiver Clock (RxC)

These registers are used as temporary data storage for the DACIA
Transmit and Receive circuits. The Transmit Data Register is
characterized as follows:

This pin is the Receiver 16x clock input when the baud rate generator is programmed for external clock. Figure 15 shows timing
considerations for RxC.

• Bit 0 is the leading bit to be transmitted.

Transmitter Clock (TxC)

• Unused data bits are the high-order bits and are "don't care"
for transmission.

This pin is the transmitter 16x clock input when the baud rate
generator is programmed for external clcck. Figure 16 shows timing considerations for TxC.

• Write-only register.
The Receive Data Register is characterized in a similar fashion
as follows:

Note
When RxC and TxC are used for external clock input,
XTALI must be tied to ground (Vss) and XTAlO must
be left open (floating).

• Bit 0 is the leading bit received.
• Unused data bits are the high order bits and are "0" for the
receiver.

Clock Out (ClK OUT)

• Parity bits are nol contained in the Receive Data Register,
but are stripped off after being used for external parity checking. Parity and all unused high-order bits are "0".

This output is a buffered output from the 3.6864 MHz crystal
oscillator. It may be used to drive the XTALI input of another
DACIA. This allows multiple DACIA chips to be used in a system
with only one crystal needed. ClK OUT is in phase with XTALI.

• Read-only register
Figure 4 shows an example of a Parity Mode single transmitted
or received data word. In this example, the data word is formatted with 8 data bits, parity, and two stop bits. Figure 4 also shows
a single character transmitted or received in Address/Data Mode.
In this example, the address or data word is 8 bits, there is no

'I

XTALI

0--

XTALI

0--

XTALO

PARITY MODE

f 0 I 12 13 14 Is 16 17 I P lIS 12S I
~~.----~------~JI ~

START
BIT

DATA

XTALO

I I

PARITY STOP
BIT
BITS

0

12 13 14

Is 1

6

17]A DllS 12S I

' - -_ _...,.--_ _

START
BIT

ADDRESS
OR
DATA

Figure 4_

~J

OPEN
CIRCUIT

INTERNAL
CLOCK

ADDRESS/DATA MODE

,

EXTERNAL
CLOCK

I '--r--I
STOP
BITS

EXTERNAL
CLOCK

RECEIVER
EXTERNAL
CLOCK

XTALI
RxC

TRANSMITTER
EXTERNAL
CLOCK
OPEN
CIRCUIT

TxC
XTALO
EXTERNAL
CLOCK

o

Typical Character

Figure 5.
2-320

DACIA Clock Generation

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

CONTROL AND FORMAT REGISTER (CFR)

Format Register (CFR Addressed with Bit 7

The Control and Format Register (CFR) is a dual-function, writeonly register which allows control of word length, baud rate, controlline outputs, parity, echo mode, and compare/TBR access.
When the CFR is written to with bit 7 = 0, the CFR functions as
a Control Register. When the CFR is written to with bit 7 = 1, the
CFR operates as a Formal Register.
Control Register (CFR Addressed with Bit 7
6

7

0

5

NO.
TBR/CDR STOP
BITS

4
ECHO

3

2

6

1

NUMBER
OF DATA
BITS

o
o

BAUD RATE SELECTION

3

0

1

2

PARITY
PARITY
DTR
RTS
SELECTION ENABLE CONTROL CONTROL

Control or Format Register
Format Register

PI

Number of Data Bits Per Character
No. Bits

Bits 6-5
6 5

0

4

5

Bit 7
1

= 0)

1

7

= 1)

0

5
6
7

1

o

8
Bit 7
0

Control or Format Register
Control Register

Bit 6
1
0

TBR/CDR
Access the Transmit Break Register (TBR)
Access the Compare Data Register (CDR)

Bit 5
1
0

Number of Stop Bits Per Character
Two stop bits
One stop bit

Bit 4
1
0

Echo Selection (ECHO)
Echo activated
Echo deactivated

Bits
3 2
0 0
0 0
0 0
0 0
0 1
0
0 1
0 1
0
0
0
0

3-0
1
0
0
1
1
0
0

0
0

0
1
0
1
0

1
0 0
0 1
1 0
1 1
0 0
0 1
0

Bits 4-3
4 3

o
o

Parity Mode Selection
Selects
Odd Parity
Even Parity
Mark Parity
Space Parity

0
1

o

Bit 2
1

Parity Enable
Parity as specified by bits 4-3
No Parity

o
Bit 1

DTR Control
DTR high
DTR low

1

o

Baud Rate Selection
Baud Rate
50
109.2
134.58
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
38400
External TxC and RxC Clocks

RTS Control
RTS high
RTS low

Bit 0
1

o

INTERRUPT ENABLE REGISTER (IER)
The Interrupt Enable Register (IER) is a write-only register that
allows each of the possible IRO sources to be enabled, or disabled, individually without affecting any of the other Interrupt
enable bits in the register. IRO sources are enabled by writing
to the IER with bit 7 set to a 1 and every bit set to a 1 that corresponds to the IRO source to be enabled. IRO sources are
disabled by writing to the IER with bit 7 set to a 0 and every bit
setto a 1 that corresponds to the IRO source to be disabled. Any
bit (except bit 7) to which a 0 is written is unaffected and remains
in its original state. As an example, writing $7F to the IER will
disable alilRO source bits, but writing $FF to the IER will enable
all IRO source bits. A hardware reset (RES) clears all IRO
source bits to the 0 state. Bit assignments for the IER are as
follows:
7
CLEAR/
SET
BITS

2-321

6
TDR
EMPTY
IE

5

CTS
IE

4

DCD
IE

3

DSR
IE

2

1

0

PARITY
ERROR
IE

FRM
OVR
BRK
CPR
IE

RDR
FULL
IE

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

INTERRUPT STATUS REGISTER (ISR)

CONTROL STATUS REGISTER (CSR)

The Interrupt Status Register (ISR) is a read-only register that
identifies the current status condition for each DACIA internal IRQ
source. Bits 6 through 0 of the ISR are set to a 1 whenever the
corresponding IRQ source condition has occurred in the DACIA.
Bit 7 identifies if any of the IRQ source status bits have been set
in the ISA.

The Control Status Register (CSR) is a read-only register that provides 110 status and error condition information. The CSR is normally read after an IRQ has occurred to determine the exact
cause of the interrupt condition.

7

6

7

5

4

3

2

1

6

0

FRM
ANY TDR
DCD
CTS
DSR PARITY OVR RDR
BIT EMPTY TRANS
TRANS TRANS ERROR BRK FULL
SET
CPR

o
Bit 6

o
Bit 5
1

o
Bit 4
1

4

3

2

1

0

Bit 7
1

Framing Error
A framing error occurred in receive data
No framing error occurred, or the RDR was
Read

Bit 6
1

Transmitter Underrun (TRANS UNDR)
Transmit shift register is empty and TORE bits
in IER and ISR are set
A write to the TOR has occurred

o

Bit 7
1

5

FRAMING TRANS CTS
DCD
DSR REC DTR_ RTS
ERROR UNDR STATUS STATUS STATUS BREAK STATUS STATUS

Any Bit Set
Any bit (6 through 0) has been set to a 1
No bits have been set to a 1

o

Transmit Data Register Empty (TOR EMPTY)
Transmit Data Register has been transferred to
the shift register
New data has been written to the Transmit Data
Register

Bit 5
1

o

Transition On CTS Line (CTS TRANS)
A positive or negative transition has occurred on
CTS
No transition has occurred on CTS, or ISR has
been Read

Bit 4
1

Transition On DCD Line (DCD TRANS)
A positive or negative transition has occurred on
DCD
No transition has occurred on DCD, or ISR has
been Read

o

o
Bit 3
1

CTS Status
A low-to-high transition occurred on CTS line
A high-to-Iow transition occurred on CTS line
DCD Status
A low-to-high transition occurred on DCD line
A high-to-Iow transition occurred on DCD line
DSR Status
A low-to-high transition occurred on DSR line
A high-to-Iow transition occurred on DSR line

Bit 2
1

REC Break
A Receive Break has occurred
No Receive Break occurred, or RDR, was read

Transition On DSR Line (DSR TRANS)
A positive or negative transition has occurred on
DSR
No transition has occurred on DSR, or ISR has
been Read

Bit 1
1

DTR Status
A low-to-high transition occurred on DTR line
A high-to-Iow transition occurred on DTR line

Bit 0
1

Bit 2
1

Parity Error
A parity error has occurred in received data
No parity error has occurred, or the Receive
Data Register (RDR) has been Read

o

RTS Status
A low-to-high transition occurred on RTS line
A high-to-Iow transition occurred on RTS line

Bit 1

Frame Error, Overrun or Break (FRM, OVR,
BRK, CPR)
A framing error, receive overrun, or receive
break has occured, or, in Compare Mode
No error, overrun, break has occured, RDR has
been Read, or not in Compare Mode

o
Bit 3
1

o

o

o
Bit 0
1

o

o
o

Receive Data Register Full (RDR FULL)
Shift register data has been transferred to
Receive Data Register
Receive Data Register has been Read

2-322

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

TRANSMIT BREAK REGISTER (TBR)

COMPARE DATA REGISTER

The DACIA has two Transmit Break Registers which are writeonly registers. Only two bits of these registers are used; one during the Receive mode to command a Transmit Break and the
other to provide for Parity/Address recognition. Writing a 1 to bit 1
of the TBR causes a continuous Break to be transmitted by the
ACIA associated with the register. Writing a 0 to this bit allows
normal transmission to resume. Writing a 1 to bit 0 of the TBR
commands the value of the Parity bit to be sent to the Parity Error
bit (bit 2 of the ISR). Writing a 0 to this bit allows normal Parity
Error recognition to be in force. When an RES is received by the
DACIA. both of these bits are reset to O. The bits format for the
TBR are as follows:

The Compare Data Register (CDR) is a write-only register which
can be accessed when CFR bit 6 = O. By writing a value into
the CDR, the DACIA is put in the compare mode. In this mode,
setting of the RDRF bit is inhibited and the FRM/OVR/BRKlCPR
bit (bit 1) on the ISR is set until a character is received which
matches the value in the CDR. The next character is then
received and the RDRF bit is set. The receiver will now operate
normally until the CDR is again loaded.

7

6

5

4

2

3

NOT USED

Bits 7-2

1

0

TRANS
BRK

PARI
ADDR

SUMMARY OF REGISTERS
Table 3 shows the control and status registers associated with
the DACIA in a single summary table. Each of the ACIA's has its
own set of these seven registers.

OPERATION
The following paragraphs describe len modes (or conditions) of
operation of the DACIA. The modes described are:
•

Not used (don't care)

Continuous Data Transmit

• Continuous Data Receive
Bit 1
1

o
Bit 0
1

o

Transmit Break (TRANS BRK)
Transmit continuous Break until disabled
Resume normal transmission

• Transmit Underrun Condition
•
•

Parity/Address Recognition (PAR ADDR)
Send value of parity to ISR bit 2
Return to normal Parity Error recognition mode

Effects of CTS on Transmitter
Effects of Overrun on Receiver

•

Echo Mode Timing

•

Framing Error

• Transmit Break Character
•

Receive Break Character

• Automatic Address Recognition

Table 3.

Control and Status Registers Format Summary

REGISTER BIT NUMBERS

REGISTER

7

6

5

4

3

2

1

0

CLEARISET
BITS

TDR
EMPTY
IE

CTS
IE

DCD
IE

DSR
IE

PARITY
ERROR
IE

FRM,OVR
BRK, CPR
IE

RDR
FULL
IE

INTERRUPT
ENABLE
REGISTERS

ANY
BIT
SET

lOR
EMPTY

CTS
TRANS

DCD
TRANS

DSR
TRANS

PARITY
ERROR

FRM,OVR
BRK, CPR

RDR
FULL

INTERRUPT
STATUS
REGISTERS

FRAMING
ERROR

TRANS
UNDR

CTS
STATUS

DCD
STATUS

DSR
STATUS

REC
BREAK

DTR
STATUS

RTS
STATUS

STATUS
REGISTERS

0

TBRI
CDR

NO.
STOP
BITS

ECHO

DTR
CONTROL

RTS
CONTROL

CONTROL
REGISTERS
AND
FORMAT
REGISTERS

TRANS
BRK

PARI
ADDR

1

NUMBER OF
DATA BITS

PARITY
SELECTION

BAUD RATE SELECTION
PARITY
ENABLE

NOT USED

COMPARE BITS (ADDRESS RECOGNITION)

2-323

I

TRANSMII
BREAK
REGISTERS
COMPARE
DATA
REGISTERS

$80

fI

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

CONTINUOUS DATA TRANSMIT

When the MPU writes a word to the TOR the TORE bit is cleared.
In order to maintain continuous transmission the TOR must be
loaded before the stop bit(s) are ended. Figure 6 shows the relationship between IRQ and TxO for the Continuous Data Transmit
mode.

In the normal operating mode, the TORE bit in the ISR signals
the MPU that the DACIA is ready to accept the next data word.
An IRQ occurs if the corresponding TORE IRQ enable bit is set
in the IER. The TORE bit is set at the beginning of the start bit.

CHAR #n + 1

CHAR #n
I

CHAR #n + 2

I

~/

/

CHAR #n + 3

1

~/

~/

I

~

TX~ t [BOF]~]~~EJ t I t [BOF] ~ ~ GEJ t I t ["B:TB0 ~ ~ GEJ t I t ["B:TB0 ~ ]~EJ t L
: START

STOP:START

UU'

STOP: START

STOP: START

/Lw

Lw

.

,Los•• ~ =~,~

IRiluJ

'ROC,"SO' /
INTERRUPT
(TRANSMIT DATA
REGISTER EMPTY)

READS
ISR, CAUSES
IRQ TO CLEAR

Figure 6.

STOP:

l

INTERVAL OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED

Continuous Data Transmit

CONTINUOUS DATA RECEIVE
stop bit. The processor must read the RDR before the next stop
bit, or an overrun error occurs. Figure 7 shows the relationship
between IRQ and RxD for the continuous Data Receive mode.

Similar to the continuous data transmit mode, the normal receive
mode sets the RDRF bit in the ISR when the DACIA has received
a full data word. This occurs at about the 9/16 point through the

CHAR #n + 1

CHAR #n
/

I

,,/

I

CHAR #n + 2
,,/

CHAR #n + 3

I

,,/

I

"

RX~ t [BOF]~~GEJ/I t [BOF]~=GEJ/I t r:-r;~I~GEJ/I t rs:FI~~1 L
START

STOP: START

STOP:

START

IR~
IRQ PROCESSOR
INTERRUPT OCCURS
ABOUT 9/16 INTO
LAST STOP BIT
PARITY OVERRUN,
AND FRAMING ERROR
UPDATED ALSO

STOP:

START

LlU
PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL, OTHERWISE
OVERRUN OCCURS

PROCESSOR READS
ISR, CAUSES
IRQ TO CLEAR

Figure 7.

Continuous Data Receive

2-324

STOP:

L

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

TRANSMIT UNDERRUN CONDITION

flag is set. This condition persists until the TOR is loaded with a
new word. Figure 8 shows the relation between IRQ and TxO for
the Transmit Underrun Condition.

If the MPU is unable to load the TOR before the last stop bit is
sent, the TxO line goes to the MARK condition and the underrun

CHAR#n
I

/

TxD

CONTINUOUS "MARK"

/

TtlI t ~~~~ t
I

I
STOP

I

" /

t [gBJ~~~ t I t [BJBJ~~~
I
STOP START

I START

U . . . .- -

rLJIJ

t!---------j-.-------/----7

PROCESSOR
INTERRUPT
FOR DATA
EMPTY

CHAR #n + 2
I

r--r---r--.-.:"T-----

STOP START

IRQ

CHAR #n + 1

~WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY

PROCESSOR READS
ISR, CLEARS IRQ

UNDERRUN BIT
SET

Figure 8.

Transmit Underrun Condition Relationship

EFFECTS OF CTS ON TRANSMITTER
in the shift register continues to be sent but any word in the TOR
is held until CTS goes low. At the high-to-Iow transition the CTS bit
in the ISR is again set. Figure 9 shows the relationship of IRQ,
TxO, and CTS for the effects of CTS on the transmitter.

The CTS control line controls the transmission of data or the handshaking of data to a "busy" device (such as a printer). When the
CTS line is low, the transmitter operates normally. Any transition
on this line sets the CTS bit in the ISA. A high condition inhibits
the TORE bit in the ISR from becoming set. The word currently

CHAR #n
TxD

CHAR #n + 1
I

" /

B_-_b00 t

I t \ Bo I B,I

"

CONTINUOUS MARK

NEXT CHARACTER IS SENT IMMEDIATELY
UPON CTS GOING LOW IF PROCESSOR
HAS ALREADY LOADED NEW DATA,
OTHERWISE IT WAITS FOR NEW DATA.

~-r-IB-rI-'"pI---'tfr::--N~EX~T~--"""""~Jr--,_J

STOP START

N

STOP

un

CHARACTER
IS NOT SENT
TORE IS NOT SET

MPU
CLEARS
IRQ AGAIN

I Bo \ B,\

J:=

WHEN PROCESSOR
FINALLY LOADS
NEW DATA,
TRANSMISSION STARTS

11,-_____...JI.----,m~MEDIATELY AND
\

' "
CTS
MPU
IRQ
CLEARS
IRQ

r-.....:.,,-------i---,I

CLEAR-TO-SEND
CTS _ _ _ _ _ _~~~~~=-

t

START

______...JI

\~
CTS
IRQ

Figure 9.

Effects of CTS on Transmitter

2-325

INTERRUPT OCCURS,
INDICATING TRANSMIT
DATA REGISTER EMPTY

PI

Dual Asynchronous Communications Interface Adapter (DACIA)

R65C52

EFFECTS OF OVERRUN ON RECEIVER
If the processor does not read the RDR before the stop bit of the
next word, an overrun error occurs, the overrun bit is set in the
ISR, and the new data word is not transferred to the RDR. The
RDR contains the last word not read by the MPU and all follow-

CHAR #n

~

/

ing data is lost. The receiver will return to normal operation when
the RDR is read. Figure 10 shows the relation of IRO and RxD for
the effects of overrun on the receiver.

CHAR #n + 1

I

"

/

CHAR #n + 2

I

"

/

CHAR #n + 3

I

"

/~_ _ _--'-I_ __

J!l t [B:JBJ~~GEJ)I 1t [B:JBJ~~GEJ/II t [BOFJ~~GEJ/I
t [B:JBJ~~ ~
I
I
iRaLJIJ
!
tn ~-;::'-C-H-A-R-#-n-+-2-RxD
STOP I START

STOP

START

STOP

START

STOP

START

1

PROCESSOR /

INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL

MPU DOES
NOT READ
RDR. OVERRUN
BIT SET

Figure 10.

MPU READS
ISR
CLEARS IRQ

IRQ.
CHAR #n + 1
IS LOST

Effects of Overrun on Receiver

ECHO MODE TIMING
underflow flag would be set and continuous Mark transmitted. If
Echo is initiated, the underflow flag will not be set at end of data
and continuous Mark will not be transmitted. Figure 11 shows the
relationship of RxD and TxD for Echo Mode.

In the Echo Mode, the TxD line re-transmits the data received on
the RxD line, delayed by 112 of a bit time. An internal underrun
mode must occur before Echo Mode will start transmitting. In normal transmit mode if TDRE occurs (indicating end of data) an

STOP
RxD

TxD

START

STOP

START

STOP

END OF
DATA

~~~~ ~ 1+ [BOTBtI~~ t 11..-/
___
\1 \ \ \ \ \ \ \ \ \ \ \ ~:;'O:6~N~gHU;~~~:

W t [BOJBtJ==~ t 1t ~==~ t 1_====
STOP START

STOP~

STOP START

IF ECHO MODE,
NO UNDERFLOW,
THEREFORE NO
CONTINUOUS MARK

Figure 11.

Echo Mode Timing

2-326

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

FRAMING ERROR
Framing error is caused by the absence of stop bit(s) on received
data. The framing error bit is set when the RDRF bit is set. Subsequent data words are tested separately, so the status bit always

reflects the last data word received. Figure 12 shows the relationship of IRQ and RxD when a framing error occurs.

RxD
(EXPECTED)
STOP
1

STOP START

1121 I I

RxD
(ACTUAL)

Bo

B,

B21 B31 B41 Bsl B61

NOTES: 1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.

I

PROCESSOR
INTERRUPT,
FRAMING
ERROR
BIT SET

2. IF NEXT DATA WORD IS OK,
FRAMING ERROR IS CLEARED.

Figure 12. Framing Error

TRANSMIT BREAK CHARACTER
transmission may resume. At least one full word time of Break
will be sent regardless of the length of time between starting and
stopping the Break character. Figure 13 shows the relationship
of IRQ and TxD for a Transmit Break character.

A Break may be transmitted by storing a value of $00 in the IER.
After storing zero in the IER the Break is transmitted immediately.
Care should be exercised so that a character in transmission is
not disturbed inadvertently. The Break level lasts until other than
$00 is stored in the IER at which time a stop bit is sent and

"
.Jtl.tm~=~ t It,
~/

TxD

STOP 1START

STOP

"-../

==~tlt~
I

t

Bo I B, ' __ I BN I P ,
I
START
STOp!

STOP START

I'TT"-----i
IRQ
I+------~-

PERIOD DURING
WHICH PROCESSOR
SELECTS
CONTINUOUS
"BREAK" MODE

NORMAL
INTERRUPT

POINTATWH~

PROCESSOR
SELECTS
NORMAL
TRANSMIT
MODE

Figure 13. Transmit Break Character

2-327

/
PROCESSOR
INTERRUPT
TO LOAD
TRANSMIT
DATA

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

RECEIVE BREAK CHARACTER
In the event that a Break character is received by the receiver,
the Break bit is set. The receiver does not set the RDRF bit and
remains in this state until a stop bit is received. At this time the

-------~"

RxD

CONTINUOUS "BREAK"

E~~l±J~ I t I Bo, B'I __ ,B
STOP I START

N

I P 1)1' I

1---I.....~f1l t ~-~l±JJi I t I Bol B,I

LJr

U
r

,,/~----

STOP /

(1--'-\

STOP I

-----i

PROCESSOR
INTERRUPT
FOR
RECEIVER
DATA REGISTER
FULL

next character is to be received normally. Figure 14 shows the
relationship of IRQ and RxD for a Receive Break Character.

r ~

START
I

rr---

II

L_...J..I

~

NO MORE
INTERRUPTS

NO INTERRUPT
SINCE RECEIVER.
DISABLED UNTIL

PROCESSOR
INTERRUPT
FIRST STOP BIT
WITH BREAK AND FRAMING ERROR BIT SET.
EVEN PARITY CHECK WILL ALSO GIVE A PARITY
ERROR BECAUSE ALL ZEROS (CONTINUOUS
BREAK) REPRESENT EVEN PARITY.

Figure 14.

STOP I START

NORMAL
RECEIVER
INTERRUPT

Receive Break Character

AUTOMATIC ADDRESS RECOGNITION
The DACIA offers a unique solution to the standard problem
associated with multi-drop environment UARTs and communication interface controllers. In the standard configuration used by
other devices, the slave CPU must be constantly interrupted to
analyze incoming characters on the communications net to determine If an address word is present and if so, does that address
match the address assigned to the slave UART. This CPU interrupt scheme can become intolerable in very large multi-drop networks because every slave on the communications net must
"wake-up" it's CPU for every character sent down the network
by the master. The end result is that the CPUs on the communications net are constantly being interrupted for the mundane task
of address recognition.

To avoid this constant CPU interrupt problem, the DACIA has
been designed to do address comparison and recognition internally without the need for CPU intervention. Therefore, the slave
CPU is not interrupted until the DACIA has determined that the
character sent over the communications net by the master was
an address and the address matched the address stored in the
DACIA Compare Register. At this point the DACIA interrupts the
CPU, goes out of Compare Mode, and receives the string of
characters being transmitted by the master, (Le., the data
characters). When all data has been received by the slave, it's
CPU must again write the slave address into the DACIA Compare
Register which automatically puts it back into the Compare Mode,
waiting for another address character.

2-328

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

GENERATION OF NON-STANDARD BAUD RATES

These can be determined by:

Divisors

B
au

The internal counter/divider circuit selects the appropriate divisor
for the crystal frequency by means of bits 0-3 of the CFR Control
Register, as shown in Table 4.

d R t _ Crystal Frequency
ae Divisor

Furthermore, it is possible to drive the DACIA with an off-chip
oscillator to achieve other baud rates. In this case, XTALI (pin 3)
must be the clock input and XTALO (pin 4) must be a nonconnect.

Generating Other Baud Rates
By using a different crystal, other baud rates may be generated.

Table 4.
Control
Register
Bits

Divisor Selection

3

2

1

0

Divisor Selected
For The
Internal Counter

Baud Rate Generated
With 3.6864 MHz
Crystal

0

0

0

0

73,728

(3 6864 x 10')173,728

0

0

0

1

33,538
27,408

(3 6864 x 10')/33,538 = 109 92

Baud Rate Generated
With a Crystal
of Frequency (f)

= 50

fl73,728
1/33,538

0

0

1

1/27,408

0

1

0
1

(36864 x 10')/27,408 = 13458

0

24,576

(3.6864 x 10')/24,576 = 150

fl24,576

(3 6864 x 10')/12,288 = 300

1/12,288

0

1

0

0

12,288

0

1

1

0

1

0
1

0

6,144
3,072

(3 6864 x 10')/6,144 = 600
(3.6864 x 10')/3,072 = 1,200

1/6,144
1/3,072

0

1

1

1

2,048

(3 6864 x 10')/2,048 = 1,800

fl2,048

1

0

0

0

1,536

(3 6864 x 10')/1,536 = 2,400

fll,536

1

0

0

1

1,024

(36864 x 10')/1,024

= 3,600

f/l,024

1

0

1

0

768

(3 6864 x 10')/768

= 4,800

1/768

1

1
0

1
0

512
384

(36864 x 10')/512

= 7,200

1/512

1

0
1

(3.6864 x 10')/384

= 9,600

1/384

1

1

0

1

192

(3 6864 x 10')/192

1/192

1

1

1

0

96

(3.6864 x 10')/96

= 19,200
= 38,400

1

1

1

1

16

TxC/16

2-329

=

Baud Rate or RxC/16

1/96

=

Baud Rate

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

RxC

INTERNAL

+ 18
RxS

LATCH

)}~_DA_T_A

~~

____________________

CD

_______

TRANSFER DATA TO SHIFT REGISTER

Figure 15. DACIA External Clock Timing - Receive Data

=~~

~~~RNAL

TxD

--~~

) } _ _ rr QUA

Figure 16. DACIA External Clock Timing - Transmit Data

2-330

~r----

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

AC CHARACTERISTICS
= 5.0V ±5%, vss =
READIWRITE TIMING

(Vcc

OV, TA

= TL to TH)
2 MHz

Charactarlstlc

Symbol

Rm, RSO-RS2 Valid to CS Low
(Satup Time)
CS Low to Am, RSO-RS2
(HOld Time)

Min

Iwc

0

4 MHz
Max

Min

Max

Unit

-

0

-

ns

-

ns

IcwH

65

-

65

CS Low to Data Valid
CS High 10 Dala Invalid

!cov

-

100

-

100

ns

(Hold Time)

!coz

-

10

-

10

ns

IOVCH

20

Data Valid to

CS High

20

ns

Note:
1. All limes are In nanoseconds.

RSO-RS2

00-07
DATA OUT

DACIA Read Cycle Waveforms

RSO-RS2

~I,---Jm~~

RtW

'k'C_
1cwH

_

}--

Icov

OATAIN

1. .

{O!' .....

00·D7 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----<.

:1
~

f------'I
DACIA Write Cycle Waveforms

2·331

fJ

R65C52

Dual· Asynchronous Communications Interface Adapter (DACIA)

TRANSMIT/RECEIVE TIMING
Characteristic

,:'

Symbol

Min

Max

Unit

TransmiUReceive Clock Rate

!cCY

250

ns

TransmiUReceive Clock High Time

tCH

100

TransmiUReceive Clock Low Time

teL

100

-

XTALIto TxD Propagation Delay

too

-

250

ns

XTALIto IRQ Propagation Delay

tOI

-

250

ns

CTS, DCD,DSRtoIRQ

tCTI

150

ns

150

ns

150

ns

IRQ Propagation Delay (Clear)

tlRQ

-

RTS, DTR Propagation Delay

t OLY

-

ns
ns

Note:
1. All times are in nanoseconds.

XTALI

/ f.--

tCH----O

~~tCL-V
I

tCCY

I

~

TxD

f.

too •

I+-

tDi

tCTI

-

--..

X
I---

I---

/

t IRQ - -

t OLY

I--

~

RTS, DTR

DACIA Transmit/Receive Timing

2-332

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

ABSOLUTE MAXIMUM RATINGS*
Parameter

Symbol

Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Commercial
Industrial
Storage Temperature

* NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Unit

Value

Vee

-0.3 to + 7.0

Vde

VIN

- 0.3 to Vee + 0.3

Vdc

VOUT

- 0.3 to Vee + 0.3

Vdc
°C

TA
o to + 70
-40 to +85
TSTG

-55 to + 150

fI

°C

OPERATING CONDITIONS
Parameter

Supply Voltage
Temperature Range
Commercial
Industrial

Symbol

Value

Vee

5V±5%

TA
0° to 70°C
- 40°C to + 85°C

DC CHARACTERISTICS
(Vee

= 5.0 V ± 5%, Vss = OV, TA = T L to T H, unless otherwise noted)
Characteristic

Symbol

Input High Voltage
ExceptXTALI and XTALO
XTALI and XTALO

V IH

Input Low Voltage
Except XTALI and XTALO
XTALI and XTALO

VIL

Input Leakage Current
RtW, RES, RSO, RS1, RS2, RxD, CTS, DCD, OSR, RxC,
TxC,CS

liN

Input Leakage Current for Three-State Off
DO-D7

ITSI

Output High Voltage
DO-D7, TxD, CLK OUT, RTS, DTR

VOH

Output Low Voltage
DO-D7, TxD, CLK OUT, RTS, DTR

VOL

Output Leakage Current (Off State)
IRQ

10FF

Typ

+2.0
+2.4

-

Vee + 0.3
Vee + 0.3

-0.3
-0.3

-

+0.8
+0.4

PD
CIN

Unit

Test Conditions

V

!LA

10

-

Power Dissipation

Max

V

-

Input Capacitance
Except XTALI and XTALO
XTALI and XTALO
Output Capacitance

Min

+2,4
1.5

50

10

!LA

-

-

V

Vee = 4.75V
ILOAD = -100 !LA
Vee = 4.75V
ILOAD = 1.6 mA

-

+0.4

V

-

±2

±10

~A

10

mW/MHz

-

COUT

-

-

5
10

pF
pF

-

-

10

pF

1. All units are direct current (dc) except for capacitance.
2 Negative sign indicates outward current flow, positive Indicates inward flow.
3. Typical values are shown for Vee = 5.0V and TA = 25°C.

2-333

VIN = O.4V to 2,4V
Vee = 5.25V

±2

-

Notes:

VIN = OV to Vee
Vee = 5.25V

Vee = 5.25V
VOUT = 0 to 2.4V

Vee'" 5.0V
VIN = OV
f = 2 MHz
TA = 25°C

R65C52

Dual Asynchronous Communications Interface Adapter (DACIA)

PACKAGE DIMENSIONS
40-PIN CERAMIC DIP

[: [J ]]]
I·

A

.[

~;:::::::: ::: :: :~

H~dLD

ir====l

G~ ~ ~J

M--1

40-PIN 'PLASTIC DIP

MILLIMETERS
DIM MIN
MAX
A 50 29 5131
B 1486 1562
254
419
C
D
038
053
076
140
F
G
254 esc
076
178
H
J
020
033
K
254
419
L
1460 1537
1QO
O·
M
051
152
N

MILLIMETERS
MAX
DIM MIN
A 5128 5232
V 1372 1422
355
5 08
C
D
036
051
F
102
152
254
esc
G
165
216
H
J
020
030
K
3 as
356
1524 esc
L
7·
10·
M
N
051
102

2-334

INCHES
MIN MAX

1980
0585
0100
0015
0030

2 020
0615
0165
0021
a 055

0100 SSC

0030 0070
0008 0013
0100 0165
0575 0605
O·
10·
0020 0060

INCHES
MIN MAX
2040 2060

0540 0560
0140 0200
0014 0020
0040 0060
0100 Bse
0065 0085
00080012

a 120

0140

0600 BSC
7·
10·

a 020

0040

R6265 • R6765

'1'

Rockwell

R6265, R6765
DOUBLE-DENSITY FLOPPY DISK

CONTROLLER (DDFDC)
PRELIMINARY

DESCRIPTION

FEATURES

The R6765 Double-Density Floppy Disk Controller (DDFDC)
interfaces up to four floppy disk drives to an S-bit or 16-bit
microprocessor-based system including Z SO, SOSOA, SOS5A,
SOS6, and SOSS. The DDFDC simplifies the system design by
minimizing both the number of external hardware components
and software steps needed to implement the floppy disk drive
(FDD) interface. Control signals supplied by the DDFDC reduce
the number of components required in external phase locked
loop and write precompensation circuitry. Memory-mapped
registers containing commands, status and data simplify the software interface. Built-in functions reduce the software overhead
needed to control the FDD interface. The DDFDC supports both
the IBM 3740 Single-Density (FM) and IBM System 34 DoubleDensity (MFM) formats.

• Address mark detection circuitry

The R6265 interfaces to the 3V2" Sony Micro Floppy disk drive
as well as 5%" and S" disk drives. The R6265 writes and reads
in the Sony compatible format and can also read from disks
formatted in IBM compatible format. A combination of up to four
3'12",5%" and S" drives can be interfaced to and controlled by
the R6265. The R6265 is pin-compatible with, and electrically
identical to, the R6765.

• Multi-sector and multi-track transfer capability

• Software control of
-Track stepping rate
-Head load time
-Head unload time
• Writes in:
-IBM compatible (single- and double-density format (R6765)
-Sony compatible (EMCA) format (R6265)
• Reads data written in:
-IBM compatible format (R6265 and R6765)
-Sony compatible format (R6265)
• Programmable data record lengths: 12S, 256, 512,1024,2048,
4096 or S192 bytes/sector
• Controls up to four floppy disk drives
• Data scan capability-will scan a single sector or an entire
track of data fields, comparing on a byte-by-byte basis data
in the processor's memory with data read from the disk
• Data transfers in DMA or non-DMA mode
• Parallel seek operations on up to four drives

The DDFDC interfaces directly to the synchronous microprocessor bus and operates with S-bit byte length data transferred on
the bus in either DMA or non-DMA mode. In DMA mode, the CPU
need only load the command into the DDFDC and all data
transfers occur under DMA control. The R6265/R6765 is directly
compatible with the ZS41 0/,..PDS257 Direct Memory Access Controller (DMAC). In non-DMA mode, the DDFDC generates an interrupt to the CPU indicating that a byte of data is available.

• Directly compatible with an B-bit or 16-bit synchronous
microprocessor bus including Z-SO/SOSOA/SOS5A, SOS6,
and SOSS
• The R6765 replaces the NEC "PD765A and Intel S272
• The R6265 replaces the NEC "PD7265
• Single phase 4 or S MHz clock (R6765) or S MHz clock (R6265)
• Single + 5 volt power supply

Controller commands, command or device status, and data are
transferred between the DDFDC and the CPU via six internal
registers. The Main Status Register (MSR) stores the DDFDC
status information while four additional status registers provide
result information to the CPU following each controller command.
The Data Register (DR) stores actual disk data, parameters, controller commands and FDD status information for use by the CPU.

ORDERING INFORMATION
Part Number
R6265
R6765

The DDFDC executes 15 separate multi-byte commands:
Read Data
Write Data
Read Deleted Data
Write Deleted Data
Read a Track
Read ID
Seek
Recalibrate (Restore to Track 0)

Document No. 29651 N71

O·C to 70·C

-

TI L

Specify
Format a Track
Scan Equal
Scan High or Equal
Scan Low or Equal
Sense Interrupt Status
Sense Drive Status

Temperature Range

L

ClK Frequency:
5
= 4 MHz (R6765 only)
Blank = 8 MHz
Package:
P = Plastic
C = Ceramic

2-335

Product Description Order No. 2168
Rev. 2, October 1984

R6265, R6765

Double-Density Floppy Disk Controller (DDFDC)
ROW

0O-O7~

ROD

vi

WCK

VCO
WOA

PROCESSOR
BUS
INTERFACE

WE

RST

FOO
SERIAL
DATA
INTERFACE

PSO-PS1

CS
AO

ROY

INT

lOX

RO
OOFOC

WR

WP/TS
FlT/TRKO
lCTlOIR

OMAC
INTERFACE

{

OACK

FRISTP

TC

RW/SEEK

ORQ

HOl

ClK

usa

Vee

US1

FOO
CONTROl/ST ATUS
INTERFACE

HO

GNO

..

Figure 1.

MFM

DDFDC Input and Output Signals
operation. When AO = low, the Status Register is selected. This
register may only be read (RD = low); the state WR = low is
invalid when the Status Register is selected.

PIN DESCRIPTION
Throughout this document signals are presented using the terms
active and inactive, or asserted and negated, independent of
whether the signal is active in the high-voltage state or lowvoltage state. (The active state of each logic pin is described
below.) Active low signals are denoted by a superscript bar.

INT-Interrupt Request. This active high output is the interrupt
request generated by the DDFDC to the CPU. I NT is asserted
upon completion of some DDFDC commands and before a data
byte is transferred between the DDFDC and the data bus (in the
Non-DMA mode).

BUS INTERFACE
DO-D7-Data lines. The bidirectional data lines transfer data
between the DDFDC and the a-bit data bus.

RD-Read. This active low input defines the data bus transfer
as a read cycle. When low, the data transfer is from the DDFDC
to the data bus.

ClK-ClOCK. The clock is a TTL compatible 4 or a MHz square
wave signal.

WR-Write. This active low input defines the data bus transfer
as a write cycle. When low, the data transfer is from the data bus
to the DDFDC.

RST-RESET. This active high input places the DDFDC in the
idle state and resets the output lines to the floppy disk drive
(FDD) to the low state. RST does not affect the Step Rate Time
(SRT), Head Unload Time (HUT) or Head load Time (HlT) set
by a Specify command. If RDY goes high while RST is high,
the DDFDC will assert INT within 1.024 ms. This interrupt can
be cleared by issuing a Sense Interrupt Status command.

DIRECT MEMORY ACCESS CONTROllER
(DMAC) INTERFACE
DACK-DMA Acknowledge. The DMA transfer acknowledge
signal is a TTL compatible input generated by the DMA controller
(DMAC) controlling the DDFDC. The DMA cycle is active when
DACK is low and the DDFDC is performing a DMA transfer.

CS-Chlp Select. The DDFDC is selected when the CS input
is low.

DRQ-Data DMA Request. The transfer request signal is a TTL
compatible output generated by the DDFDC to request a data
transfer operation under control of the DMAC (in the DMA mode).
The request is active when DRQ = high. The signal is reset
inactive when DMA Acknowledge (DACK) is asserted (low).

AO-Data/Status Register Select. This input selects the Data
or Status Register for reading from or writing to. When AO =
high, the Data Register is selected and the state of RD or WR
determines whether it is a read (Flo = low) or a write (WR = low)

2-336

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765

TC-Termlnel Count. This input signal is issued to the DDFDC
when the DMA transfer for a channel is complete. The signal
is active high concurrent with the DACK input when the DMA
operation is complete as a result of that transfer.

WP/TS-WrIte Protect/l\Yo Side. An active high multiplexed input
signal from the FDD. In the Read/Write mode, WP/TS high indicates the media is write-protected. In the Seek mode, WP/TS high
indicates the media is two-sided.

FDD SERIAL DATA INTERFACE

FLTITRKO-FaultlTrack Zero. An active high multiplexed input
from the FDD. In the Read/Write mode (RWISEEK = low),
FLTITRKO high indicates an FDD fault. In the Seek mode,
FLTITRKO high indicates that the readlwrite head is positioned over
track zero.

ROD-Read Data. Read Data input from the floppy disk drive
(FDD) containing clock and data bits.
ROW-Read Data Window. Data Window input generated by the
Phase L.ocked Loop (PLL) and used to sample data from the FDD.

LCT/DIR-Law Current/Direction. A multiplexed output to the
FDD. In the Read/Write mode, LCTIDIR is low when the read/write
head is to be positioned over the inner tracks and the LCT/DIR
is high when the head is to be positioned over the outer tracks.
In the Seek mode, LCT/DIR controls the head direction. When
LCT/DIR is high, the head steps to the outside of the disk; when
LCT/DIR is low, the head steps to the inside of the disk.

VCO-Voltage Controlled Oscillator Sync. This output signal
inhibits the VCO in the PLL circuit when low and enables the
VCO in the PLL circuit when high. This inhibits ROD and ROW
from being generated until valid data is detected from the FDD.
WCK-Wrlte Clock. This input clock determines the Write Data
rate to the FDD. The data rate is 500 KHz in the FM mode (MFM
= low) and 1 MHz in the MFM mode (MFM high). The pulse
width is 250 ns (typical) in both modes.

FR/STP-Fault ResetlStep. A multiplexed output to the FDD. In
the Read/Write mode, FRlSTP high resets the fault indicator in
the FDD. An FR pulse is issued at the beginning of each read
or write command prior to issuing HDL. In the Seek mode, FRlSTP
provides the step pulses to move the read/write head to another
track in the direction indicated by the LCT/DIR signal.

=

WDA-Wrlte Data. Serial write data output to the FDD contain·
ing both clock and data bits.
WE-Write Enable. This output signal enables the Write Data
into the FDD when high.

HDL-Head Load. An active high output to notify the FDD that
the read/write head should be loaded (placed in contact with the
media). A low level indicates the head should be unloaded.

PSO-PS1-Preshlft. These outputs are encoded to convey write
compensation status during the MFM mode to determine early,
late or normal times as follows:
Preshift Outputs
Write Precompensstlon Status

PSO

PSI

Normal
Late
Early
Invalid

0
0
1
1

0
1
0
1

o=

RST
RO
WR
CS
AO

low, 1 = High

00
01
02
03
04
05

FDD STATUS INTERFACE
RDY-Ready. An active high input signal indicates the FDD is
ready to send data to, or receive data from, the DDFDC.
IDX-Index. An active high input signal from the FDD indicates
the index hole is under the index sensor. Index is used to synchronize DDFDC timing.

06
07
ORQ
OACK
TC
lOX
INT

RW/sEEK-Read WritelSeek. Mode selection signal to the FDD
which controls the multiplexer from the multiplexed signals.
When RW/SEEK is low, the Read/Write mode is commanded;
when RW/SEEK is high, the Seek mode is commanded.

RW/sEEK

Mode

Low

ReadlWrite

High

Seek

ClK
GNO

1

40

vee

2
3
4

RW/sEEK
LCT/OIR
FRlSTP

5

39
38
37
36

6
7

35
34

8
9
10
11
12

33
32
31

FlTITRKO
PSO
PSI

30
29
28

WOA
USO
USI
HO
MFM

13
14
15
16
17
18
19
20

27
26

WE

23

ROO

22
21

WCK

Wp, FlT, LCT, FR

DDFDC Pin Diagram

2-337

WPITS

25
24

Active FOO Interface Signals

TS, TRKO, DIR, STP

HOl
ROY

VCO
ROW

fJ

R6265, R6765

Double-Density Floppy Disk Controller (DDFDC)
DDFDC REGISTERS

HD-Head Select. An output to the FDD to select the proper
readlwrite head,. Head One is selected when HD = high and Head
Zero is selected when HD = low.

The DDFDC contains six registers which may be accessed by
the processor or DMA controller via the system (i.e., micro·
processor) bus: a Main Status Register, a Data Register, and four
Result Status Registers. The B·bit Main Status Register (MSR)
contains the status information of the DDFDC, and may be
accessed at any time. The 8-bit Data Register, consisting of
several registers in a stack with only one register presented to
the data bus at a time, stores data, commands, parameters and
FDD status information. Bytes of data are read out of, or written
into, the Data Register in order to initiate a command or to obtain
the results of a command execution.

USO-US1-Unit Select. Output signals for floppy disk drive selec·
tion as follows:
Unit Select

usa

US1

Floppy Disk
Drive Select

0
0

0

0

1

1

1
1

0

2
3

1

O=Low,l = High

The read-only Main Status Register facilitates the transfer of data
between the system and the DDFDC. The other Status Registers
(STO, ST1, ST2 and ST3) are only available during the result
phase, and may be read only after completing a command. The
particular command which has been executed determines how
many of the Status Registers will be read.

MFM-MFM Mode. Output signal to the FDD to indicate MFM
or FM mode. Selects the MFM mode when MFM = high and the
FM mode MFM = Low.
VCC-Power. +5 Vdc.
GND-Ground (V• .).

I/O
BUFFERS

DO·D7

RST
RD

...

WR

CS

SERIAL
WRITE
CONTROL

«
z
DMA
CONTROL

TC

w

~r

DRQ

INPUT
PORT

<:=

a:

DACK

WCK
WDA
WE

~

PSO, PS1

~

IDX

RDY

CD

....I

VCC

r-r--

III
:::l

INT

GND

RDD
VCO

~

OPERATION
CONTROL

AD

CLK

RDW

SERIAL
READ
CONTROL

';

DRIVE
INTERFACE
CONTROL

FLT/TRKO

~

..
....

WP/TS

OUTPUT
PORT

r-r--

LCT/DIR
FRISTP
RW/SEEK
HDL
HD

~

usa
US1
MFM

.....

Figure 2.

DDFDC Block Diagram

2-338

R6265, R6765

Double-Density Floppy Disk Controller (DDFDC)
MSR
3
D3B
-Floppy Disk Drive (FDD) 3 Busy.
0
FDO 3 is not busy, DDFDC will accept read or write
command.
FOO 3 is busy, DDFOC will not accept read or write
command.

The relationship between the status/data registers and the WR,
RD and AO signals is shown below.

AO

RD

WR

Function

0
0
0
1
1
1

0
0
1
0
0
1

0
1

Illegal
Read Main Status Register
Illegal
Illegal
Read from Data Register
Write into Data Register

o=

0

0
1
0

MSR
2 D2B
-FDD 2 Busy.
0
FDO 2 is not busy, ODFOC will accept read or write
command.
FDO 2 is busy, DDFOC will not accept read or write
command.

Low, 1 = High

Table 1 shows each of the status registers used by the DDFDC
and each bit assignment within the individual registers. Table 2
defines the symbols used throughout the command definitions.
Each register bit symbol is defined in the register descriptions
that follow Table 2.

MSR
D1B
-FDD 1 Busy.
FDD 1 is not busy, DDFDC will accept read or write
command.
FDD 1 is busy, DDFDC will not accept read or write
command.

.!
0

REGISTER DEFINITIONS

MSR
0 DOB
-FDD 0 Busy.
0
FDD 0 is not busy, DDFDC will accept read or write
command.
FDD 0 is busy, DDFDC will not accept read or write
command.

Main Status Register (MSR)

o

2
D2B

D1B

DOB

The Main Status Register (MSR) contains the status information
of the DDFDC, and must be read by the processor before each
byte is written to, or read from, the Data Register during the command or result phase. MSR reads are not required during the
execution phase. The Data Input/Output (010) and Request for
Master (ROM) bits in the MSR indicate when data is ready and
in which direction data will be transferred on the data bus. The
maximum time between the last RD or WR during command
or result phases and the 010 and ROM getting set or reset is
12 p.s. For this reason, every time the MSR is read the processor
should wait 12,.s. The maximum time from the trailing edge of
the last RO in the result phase to when bit 4 (DDFDC Busy)
goes low is also 12 p.s.

Status Register 0 (STO)
7

I

6

IC

5

SE

4

EC

3
NR

2

1

I 0
I USO

US

HD
US1

The Status Register 0 (STO) as well as the other status registers
(8Tl-ST3), are available only during the result phase, and may
be read only after completing a command. The particular command executed determines which status registers are used and
may be read.
STO

7 6 IC

The 010 and ROM timing chart is shown in Figure 3.

o

MSR

7
0

0

o

-Request for Master.
RQM
Data Register is not ready.
Data Register is ready.

o

MSR

6
0
·1

010

-Data Input/Output.
Data transfer is from system to the Data Register.
Data transfer is from Data Register to the system.

STO
~

o

MSR

5

o

-Execution Mode. (Non-DMA mode only).
EXM
Execution phase ended, result phase begun.
Execution phase started.

4

SE
-Seek End.
Seek command is not completed.
8eek command completed by OOFDC.

STO
4 EC
-Equipment Check.
o
No error.
Either a fault signal is received from the FOD or the track
signal failed to occur after 256 step pulses (Recalibrate
command).

MSR

o

-Interrupt Code.
Normal Termination (NT). Command was properly executed and completed.
Abnormal Termination (AT). Command execution was
started, but was not successfully completed.
Invalid Command (IC). Received command was invalid.
Abnormal Termination (AT). The Ready (RDY) signal
from the FOD changed state during command
execution.

-Controller (DDFDC) Busy.
CB
DDFDC is not busy, will accept a command.
DOFOC is busy, will not accept a command.

o

2-339

fJ

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765
Table 1.

DDFDC Status Register Bit Assignments
Bit Number

Main Status Register (MSR)

7

6

5

4

3

2

1

0

ROM

DIO

EXM

CB

D3B

D2B

D1B

DOB

SE

EC

NR

HD

Status Register 0 (STO)

IC

US
US1

USO
MA

Status Register 1 (ST1)

EN

0

DE

OR

0

ND

NW

Status Register 2 (ST2)

0

CM

DD

WT

SH

SN

BT

MD

Status Register 3 (ST3)

FLT

WP

RDY

TRKO

TS

HD

US1

USO

Table 2.
Symbol

Command Symbol Description

Name

Description

AO

Address Line AO

Controls selection of Main Status Register (AO = low) or Data Register (AO = high).

D

Data

The data pattern which is going to be written into a sector

Do-D7

Data Bus

8-bit data bus, where DO

DTL

Data Length

When N is defined as 00, DTL is the number of data bytes to read from or write into the sector

EOT

End of Track

The final sector number on a track. During read or write operation, the DDFDC stops data transfer
after reading from or writing to the sector equal to EOT.

GPL

Gap Length

The length of Gap 3. During read/write commands this value determines the number of bytes that the
VCO will stay low after two CRC bytes. During the Format a Track command it determines the size of
Gap 3.

H

Head Address

Head number 0 or 1, as specified in ID field.

HD (H)

Head

A selected head number 0 or 1 which controls the polarity of pin 27. (H = HD in all command words).
The head load time in the FDD (2 to 254 ms in 2 ms increments).

IS

the least significant data line and D7 is the most significant data line.

HLT

Head Load Time

HUT

Head Unload Time

The head unload time after a read or write operation has occurred (16 to 240 ms in 16 ms Increments)

MF

FM or MFM Mode

When MF = 0, FM mode is selected; and when MF = 1, MFM mode is selected.

MT

Multi-Track

When MT = 1, a multi-track operation is to be performed. After finishing a read/write operation on side
0, the DDFDC will automatically start searching for sector 1 on side 1.

N

Bytes/Sector

The number of data bytes written in a sector.

ND

Non-DMA Mode

When ND = 1, operation is in the Non-DMA mode; when ND = 0, operation is In the DMA mode.

NTN

New Track Number

A new track number, which will be reached as a result of the Seek command. Desired head position.

PTN

Present Track Number

The track number at the completion of Sense Interrupt Status command. Present head position.
The sector number to be read or written.

R

Record (Sector)

RIW

ReadIWrite

Either read (R) or write (W) signal.

ST

Sectors/Track

The number of sectors per track.

SK

Skip

Skip Deleted Data Address Mark.

SRT

Step Rate Time

The stepping rate for the FDD (1 to 16 ms in 1 ms increments). Stepping rate applies to all drives
(F = 1 ms, E = 2 ms, etc.)

STO
ST1
ST2
ST3

Status
Status
Status
Status

Four registers which store the status information after a command has been executed. This information
is available during the result phase after command execution. These registers should not be confused
with the Main Status Register (selected by AO = law). STO-ST3 may be read only after a command has
been executed and contain information relevant to that particular command.

STP

Sector Test Process

During a Scan command, if STP = 01, the data in contiguous sectors is compared byte by byte with data
sent from the processor (or DMA controller); and if STP = 02, then alternate sectors are read and
compared:

T

Track Number

The currenUselected track number of the medium (0-255).

USO,US1

Unit Select

A selected drive number (0-3).

0
1
2
3

2-340

Double-Density Floppy Disk Controller (DDFDC)

R626S, R676S

STO
-Not Ready.
3 NR
FDD is ready.
0
FDD is not ready at issue of read or write command. If
a read or write command is issued to side 1 of a singlesided drive, this bit is also set.

sn

STO
-Head Address. (At Interrupt).
2 HD
Head Select o.
0
Head Select 1.

STI

o
o

US
FDD
0
FDD
1
o FDD
FDD

2. DDFDC cannot detect the Data Address Mark or
Deleted Data Address Mark. The MD (Missing Address
Mark in Data field) of Status Register 2 is also set.

Status Register 2 (ST2)

6

3

2

o

o

ND

NW

o

7

6

5

4

3

2

MA

o

eM

DD

WT

SH

SN

sn
o

ST2
7

EN
-End of Track.
No error.
DDFDC attempted to access a sector beyond the last
sector of a track.
-Not Used. Always Zero.

STI
-Data Error.
5 DE
o No error.
DDFDC detected a CRC error in ID field or the Data field.

-Not Used. Always Zero.

sn
2

-Not Used. Always Zero.

ST2
4 WT
-Wrong Track.
a No error.
Contents of T on the disk is different from that stored in
IDR. Bit is related to ND (Bit 2) of Status Register 1.

sn

o

MD

ST2
-Data Error in Data Field.
§. DD
a No error.
DDFDC detected a CRC error in the Data field.

STI
4 OR
-Overrun.
o No error.
DDFDC was not serviced by the system during data
transfers, within a predetermined time interval.

3

o
BT

ST2
-Control Mark.
6 CM
a No error.
DDFDC encountered a sector which contained a Deleted
Data Address Mark during execution of a Read Data,
Read a Track, or Scan command, or which contained a
Data Address Mark during execution of a Read Deleted
Data command.

STI
6

MA
-Missing Address Mark.
No error.
2 possible errors.
encountering the index hole twice.

-Unit Selected. (At Interrupt).
0 selected.
1 selected.
2 selected.
3 selected.

Status Register 1 (S11)

7

NW
-Not Writable.
No error.
DDFDC detected a write protect signal from FDD during
execution of Write Data, Write Deleted Data or Format
a Track commands.

1. DDFDC cannot detect the ID Address Mark after

STO
1 0

o
o

1

o

NO
-No Data.
No error.
3 possible errors.

ST2
3 SH
-Scan Equal Hit.
a No "equal" condition during a scan command.
"Equal" condition satisfied during a scan command.

1. DDFDC cannot find sector specified in the Internal Data
Register (IDR) during execution of Read Data, Write
Deleted Data or Scan commands.

ST2

2. DDFDC cannot read ID field without an error during
Read ID command.

2

a

3. DDFDC cannot find starting sector during execution
of Read a Track command.

2-341

SN
-Scan Not Satisfied.
No error.
DDFDC cannot find a sector on the track which meets
the scan command condition.

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765

COMMAND SEQUENCE

ST2
1 BT
-Bad Track.
o No error.
1
Contents of T on the disk is different from that stored in
the lOR and T - FF. Bit is related to NO (Bit 2) of Status
Register 1.

The DDFDC is capable of performing 15 different commands.
Each command is initiated by a multi-byte transfer of data from
the system. After command execution, the result of the command
may be a multi-byte transfer of data back to the system. Because
of this multi-byte transfer of information between the DDFDC and
the system, each command consists of three phases:

ST2

o

a

MD
-Missing Address Mark In Data Field.
No error.
DDFDC cannot find a Data Address Mark or Deleted Data
Address Mark during a data read from the disk.

Command Phasa-The DDFDC receives all information
required to perform a particular operation from the system.
Execution Phase-The DDFDC performs the instructed
operation.

Status Register 3 (ST3)

o

2
HD

Result Phasa_After completion of the· operation, status and
other housekeeping information are made available to the system.

USl

The bytes of data sent to the DDFDC to form a command, and
read out of the DDFDC in the result phase, must occur in the
order shown for each command sequence. That is, the command
code byte must be sent first followed by the other bytes in the
specified sequence. All command bytes must be written and all
result bytes must be read in each phase. After the last byte of
data in the command phase is received by the DDFDC, the
execution phase starts. Similarly, when the last byte of data is
read out in the result phase, the command is ended and the
DDFDC is ready to accept a new command. A command can
be terminated by asserting the Terminal Count (TC) signal to
the DDFDC. This ensures that the processor can always get the
DDFDC's attention even if the command in process hangs up
in an abnormal manner.

USO

Status Register 3 (STa) holds the results of the Sense Drive Status
command.
ST3
7 FLT
-Fault.
Fault (FL signal from the FDD is low.
1
Fault (FL signal from the FDD is high.

a

n
n

ST3
6 WP
-Write Protect.
Write Protect (WP) signal from the FDD is low.
Write Protect (WP) signal from the FDD is high.

a

ST3
5 ROY
-Ready.
Ready (ROY) signal from the FDD is low.
1
Ready (ROY) signal from the FDD is high.

COMMAND DESCRIPTION

a

READ DATA
A command set of nine bytes places the DDFDC into the Read
Data mode. After the Read Data command has been received
the DDFDC loads the head (if it is unloaded), waits the specified
Head Settling Time (defined in the Specify command), then begins
reading 10 Address Marks and 10 fields from the disk. When the
current sector number (R) stored in the 10 Register (lOR) matches
the sector number read from the disk, the DDFDC transfers data
from the disk Data field to the data bus.

ST3
4 TRKO -Track O.
Track 0 (TRKO) signal from the FDD is low.
Track 0 (TRKO) signal is from the FDD is high.

a

ST3
3 TS
-Two Side.
Two Side (TS) signal from the FDD is low.
1
Two Side (TS) signal from the FDD is high.

a

After completion of the read operation from the current sector,
the DDFDC increments the Sector Number (R) by one, and the
data from the next sector is read and output to the data bus. This
continuous read function is called a "Multi-Sector Read Operation." The Read Command terminates after reading the last data
byte from sector R when R - EOT. STO bits 7 and 6 are set to
o and 1, respectively, and ST1 bit 7 (EN) is set to a 1.

ST3
2 HD
-Head Select.
Head Select (HD) signal to the FDD is low.
Head Select (HD) signal to the FDD is high.

a

ST3
1 US1
":"Unlt Select 1.
Unit Select 1 (US1) signal to the FDD is low.
1
Unit Select 1 (US1) signal to the FDD is high.

a

The Read Data command can also be terminated by a high
Terminal Co~C) signal. TC should be issued at the same
time that the DACK for the last byte of data is sent. Upon receipt
of TC, the DDFDC stops outputting data to the data bus, but continues to read data from the current sector, checks CRC (Cyclic
Redundancy Count) bytes, and then at the end of that sector terminates the Read Data command and sets bits 7 and 6 in STO

ST3
o USO
-Unit Select O.
Unit Select 0 (USO) signal to the FDD is low.
Unit Select 0 (US1) signal to the FDD is high.

a

2-342

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765

If the DDFDC reads a Deleted Data Address Mark from the disk,
and the Skip Deleted Data Address Mark bit in the first command
byte is not set (SK = 0), then the DDFDC reads all the data in
the sector, sets the Control Mark (CM) flag in ST2 to a 1, and
terminates the command. If SK = 1, the DDFDC skips the sector with the Deleted Data Address Mark and reads the next' sector. The'CRC bits in the deleted data field are not checked when
SK = 1.

to O. The amount of data which can be handled with a single command to the DDFDC depends upon MT (Multi-Track), MF
(MFM/FM), and N (Number of Bytes/Sector) values. Table 3 shows
the transfer capacity.

The multi-track function (Ml) allows the DDFOC to read data from
both sides of the disk. For a particular track, data is transferred
starting at sector 1, side 0 and completed at sector L, side 1
(sector L last sector on the side). This function pertains to only
one track (the same track) on each side of the disk.

=

During disk data transfers from the DDFDC to the system, the
DDFDC must be serviced by the system within 27 pS in the FM
mode, and within 13 pS in the MFM mode, otherwise the DDFDC
sets the Over Run (OR) flag in ST1 to a 1, sets bits 7 and 6 in
STO to 0 and 1, respectively, and terminates the command.

When N = 0 in command byte 6 (FM mode), the Data Length
(DTL) in command byte 9 defines the data length that the DDFDC
must treat as a sector. If DTL is smaller than the actual data
length in a sector, the data beyond the DTL is not sent to the
data bus. The DDFDC reads (internally) the complete sector, performs the CRC check, and depending upon the manner of command termination, may perform a multi-sector Read operation.
When N is non-zero (MFM mode), DTL has no meaning and
should be set to FF.

If the processor terminates a read (or write) operation in the
DDFDC, then the 10 information in the result phase is dependent
upon the state of the MT bit in the first command byte and the
End of Track (EOl) byte. Table 4 shows the values for Track
Number (1), Head Number (H), Sector Number (R), and Number
of Data Bytes/Sector (N), when the processor terminates the
command.

At the completion of the Read Data command, the head is not
unloaded until the Head Unload Time (HUl) interval defined in
the Specify command has elapsed. The head settling time may
be avoided between subsequent reads if the processor issues
another command before the head unloads. This time savings
is considerable when disk contents are copied from one drive to
another.

Command Phase:

If the DDFDC detects the Index Hole twice in succession without
finding the right sector (indicated in R), then the DDFDC sets the
No Data (NO) flag in Status Register 1 (ST1) to a 1, sets Status
Register 0 (STO) bits 7 and 6 to 0 and 1, respectively, and terminates the Read Data command.

RIW

BYTE

7

6

5

4

3

2

1

W

1

MT

MF

SK

0

0

1

1

0

2

X

X

X

X

X

HD

US1

USO

3

Track Number (i)

4

Head Number (H)

5

Sector Number (R)

After reading the 10 and Data fields in each sector, the DDFDC
checks the CRC bytes. If a read error is detected (incorrect CRC
in 10 field), the DDFDC sets the Data Error (DE) flag in ST1 to
a 1, sets the Data Error in Data Field (DO) flag in ST2 to a 1 if
a CRC error occurs in the Data field, sets bits 7 and 6 in STO
to 0 and 1, respectively, and terminates the command.

Table 3.

6

Number of Data Bytes per Sector (N)

7

End of Track (EOT)

8

Gap Length (GPL)

9

Data Length (DTL)

DDFDC Transfer Capacity

Multi-Track
(MT)

MFM/FM

0
0

0
1

00

1
1

0
1

00
01

6,656
(128) (52) (256) (52) = 13,312

26 at Side 1

0
0

0
1

01
02

(256) (15) =
(51~ (15) =

15 at Side 0
or 15 at Side 1

1
1

0
1

01
02

(256) (30) = 7,680
(512) (30) ;. 15,360

0
0

0
1

02
03

(512) (8)
(1024) (8)

1
1

0
1

02
03

(512) (16) = 8,192
(1024) (16) - 16,384

(MF)

ByteslSector
(N)

Maximum Transfer Capacity
(ByteS/Sector) (Number of Sectors)
(128) (26) =
(256) (26) -

01

2-343

=
=

Final Sector Read

from DI$k

3,328
6,656

26 at Side 0
or 26 at Side 1

3,840

7,680

4,096
8,192

..

15 at Side 1
8 at Side 0
or 8 at Side 1
8 at Side 1

0

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765
Table 4.

DDFDC Command Termination Values
Result Phase 10

Command Phase 10
MultiTrack
(!'liT)

0

Head
Number
(tiD)

Final Sector Transferred
tolfrom Data Bus

Head
Number
. (H)

Sector
Number
(R)

No. of
Data Bytes
(N)

0

Less than EOT

NC

NC

R + 1

NC

0

Equal to EOT

T + 1

NC

01

NC

1

Less than EOT

NC

NC

R + 1

NC

T + 1

NC

01

NC
NC

Equal to EOT .

1

1

Track
Number
(T)

0

Less than EOT

NC

NC

R + 1

0

Equal to EOT

NC

LSB

01

NC

1

Less than EOT

NC

NC

R +.1

NC

1

Equal to EOT

T + 1

LSB

01

NC

Notes:
1. NC (No Change): The same value as the one at the beginning of command execution.
2. LSB (Least Significant Bit): The least significant bit of H is complemented.

Result Phase:
R

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

IS

Sector Number (R)

7

Number of Data Bytes per Sector (N)

in one of the.ID fields, it terminates the Write Data command,
sets the DE flag in ST1 to a 1, and sets bits 7 and 6 in STO to
o and 1, respectively.
The Write Data command operates in much the same manner
as the Read Data command. Refer to the Read Data command
for the handling of the following items:
• Transfer Capacity
• End of Track (EN) flag
• No Data (ND) flag
• Head Unload Time (HUT) interval
• ID information when 'the processor terminates command
(see Table 4)
• Definition of Data Length (DTL) when N = 0 and when N*,O

WRITE DATA
A command set of nine bytes places the DDFDC in the Write Data
mode. After the Write Data command has been received the
DDFDC loads the head (if it is unloaded), waits the specified Head
Settling Time (defined in the Specify command), then begins
reading ID fields from the disk. When the four bytes (T, H, R, N)
loaded during the command match the four bytes of the ID field
from the disk, the DDFDC transfers data from the data bus to
the disk Data field.

In the Write Data mode, data transfers from the data bus to the
DDFDC must occur within 27 pS In the FM mode, and within 13 pS
in the MFM mode. If the time interval between data transfers is
longer than this, then the DDFDC terminates the Write Data command, sets the Over Run (OR) flag in ST1 to a 1, and sets bits
.7 and 6 in STO to 0 and 1, respectively.

Command Phase:

After writing data into the current sector, the DDFDC increments
the sector number (R)by one, and writes into the Data field in
the next sector. The DDFDC continues this multi-sector write
operation until the last byte is written to sector R when R = EOT.
STO bits 7 and 6 are set to 0 and 1, respectively, and ST1 bit
7 (EN) is set to a 1.
The command can also be terminated by a high on Terminal
Count (TC). If TC is sent to the DDFDC while writing into the
current sector, then the remainder of the Data field is filled with
00 (zeros). In this case, STO bits 7 and 6 are set to 0 and the
command is terminated.
The DDFDC reads the ID field of each sector and checks the
CRC bytes. If the DDFDC detects a read error (incorrect CRC)

2-344

RIW

BYTE

7

6

5

4

3

2

1

W

1

MT

MF

0

0

0

1

0

1

2

X

X

X

X

X

HD

US1

usa

3

Track Number (T)

4

Head Number (H)

5

Sector Number (R)

-

6

Number of Data Bytes per Sector (N)

7

End of Track (EOT)

8

Gap Length (GPL)

9

Data Length (DTL)

0

R6265, R6765

Double-Density Floppy Disk Controller (DDFDC)

Result Phase:
R

Command Phase:

1

Status Register 0 (STO)

RIW

BYTE

7

6

5

4

3

2

1

2

Status Register 1 (ST1)

W

1

MT

MF

SK

0

1

1

0

0

3

Status Register 2 (ST2)

2

X

X

X

X

X

HD

US1

USO

4

Track Number (T)

3

Track Number (T)

5

Head Number (H)

4

Head Number (H)

6

Sector Number (R)

5

Sector Number (R)

7

Number of Data Bytes per Sector (N)

6

Number of Data Bytes per Sector (N)

WRITE DELETED DATA

7

End of Track (EOT)

8

Gap Length (GPL)

9

Data Length (DTL)

0

The Write Deleted Data command is the same as the Write Data
command except a Deleted Data Address Mark is written at the
beginning of the Data field instead of the normal Data Address
Mark.

Result Phase:
R

Command Phase:
RIW

BYTE

7

6

5

4

3

2

1

0

W

1

MT

MF

0

0

1

0

0

1

X

X

X

X

HD

US1

USO

2

X

3

Track Number (T)

4

Head Number (H)

5

Sector Number (R)

6

Number of Data Bytes per Sector (N)

7

End of Track (EOT)

8

Gap Length (GPL)

9

Data Length (DTL)

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector (N)

READ A TRACK
The Read a Track command is similar to the Read Data command except that this is a continuous read operation where all
Data fields from each of the sectors on a track are read and
transferred to the data bus. Immediately after encountering the
Index Hole, the DDFDC starts reading the Data fields as continuous blocks of data. This command terminates when the
number of sectors read is equal to EOT. Multi-track operations
are not allowed with this command.

Result Phase:
R

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector(N)

If the DDFDC finds an error in the ID or Data CRC check bytes,
it continues to read data from the track. The DDFDC compares·
the ID information read from each sector with the value stored
in the IDR, and sets the ND flag in ST1 to a 1 if there is no match.
If the DDFDC does not find an ID Address Mark on the disk after
it encounters the Index Hole for the second time it terminates the
command, sets the Missing Address Mark (MA) flag in ST1 to
a 1, and sets bits 7 and 6 of STO to 0 and 1, respectively.

READ DELETED DATA
The Read Deleted Data command is the same as the Read Data
command except that if SK = 0 when the DDFDC detects a Data
Address Mark at the beginning of a Data field, it reads all the
data in the sector and sets the CM flag in ST2 to a 1, and then
terminates the command. If SK = 1, then the DDFDC skips the
sector with the Data Address Mark and reads the next sector.

2-345

PI

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765
Command Phase'
RIW
W

BYTE

FORMAT A TRACK
7

6

5

4

3

2

1

1

a

MF

SK

a a a

2

x

X

x

x

3

Track Number (T)

4

Head Number (H)

5

Sector Number (R)

6

Number of Data Bytes per Sector (N)

X

HD

0

1

a

US1

usa

The six-byte Format a Track command formats an entire track.
After the Index Hole is detected, data is written on the disk: Gaps,
Address Marks, 10 fields and Data fields; all are recorded in either
the double-density IBM System 34 format (MF = 1) or the singledensity IBM 3740 format (MF
0). The particular format written
is also controlled by the values of Number of Bytes/Sector (N),
Sectors/Track (ST), Gap Length (GPL) and Data Pattem (D) which
are supplied by the processor during the command phase. The
Data field is filled with the data pattern stored in D.

=

7

End of Track (EOT)

8

Gap Length (GPl)

9

Data Length (DTL)

The 10 field for each sector is supplied by the processor in
response to four data requests per sector issued by the DDFDC.
The type of data request depends upon the Non-DMA flag (NO)
in the Specify command. In the DMA mode (NO
0), the DDFDC
asserts the DMA Request (ORO) output four times per sector.
In the Non-DMA mode (NO
1), the DDFDC asserts Interrupt
Request (INT) output four times per sector.

=

=

Result Phase:
R

1

Status Register a (STa)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

The processor must write one data byte in response to each
request, sending (in the consecutive order) the Track Number (T),
Head Number (H), Sector Number (R) and Number of Bytes/
Sector (N). This allows the disk to be formatted with nonsequential sector numbers, if desired.

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector (N)

The processor must send new values for T, H, R, and N to the
DDFDC for each sector on the track. For sequential formatting
R is incremented by one after each sector is formatted, thus, R
contains the total numbers of sectors formatted when it is read
during the result phase. This incrementing and formatting continues for the whole track until the DDFDC, upon encountering
the Index Hole for the second time, terminates the command and
sets bits 7 and 6 in STO to O.

READID
The two·byte Read 10 command returns the present position of
the read/write head. The DDFDC obtains the value from the first
10 field it is able to read, sets bits 7 and 6 in STO to 0 and terminates the command.
If no proper 10 Address Mark is found on the disk before the Index
Hole is encountered for the second time then the Missing Address
Mark (MA) flag in STI is set to ai, and if no data is found then
the NO flag in STI is also set to a 1. Bits 7 and 6 in STO are set
to 0 and 1, respectively and the command is terminated.

If the Fault (FLT) signal is high from the FDD at the end of a write
operation, the DDFDC sets the Equipment Check (EC) flag in STO
to ai, sets bits 7 and 6 of STO to 0 and 1, respectively, and terminates the command. Also, a low (ROY) signal at the beginning
of a command execution phase causes bits 7 and 6 of STO to
be set to 0 and 1, respectively.

During this command there is no data transfer between DDFDC
and the data bus except during the result phase.

Table 5 shows the relationship between N, ST, and GPL for
various disk and sector sizes.

Command Phase:
RIW

BYTE

7

6

W

1

a

MF

2

x

X

4

3

2

1

a a

1

a

1

a

x

X

HD

US1

usa

5

x

0

Command Phase:

Result Phase:
R

a (STa)

1

Status Register

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector (N)

2-346

RIW

BYTE

7

6

W

1

a

MF

2

X

X

3

Number of Bytes per Sector (N)

5

4

3

2

1

a a

1

1

a

1

X

X

HD

US1

usa

X

4

Sectors per Track (ST)

5

Gap Length (GPL)

6

Data Pattern (D)

0

R6265, R6765

Double-Density Floppy Disk Controller (DDFDC)
Table 5. Standard Floppy Disk Sector Size Relationship

Disk
Size

Mode

FM

Sector Size
BytealSector
128
256
512
1024

MFM3

FM

SV4"
MFM3

FM
31/2"
MFM3

No. of
SectorslTrack
(ST)

Read/wrlte
Command 1

Format
Command 2

00

1A
OF
08
04
02
01

07
OE
1B
47
C8
C8

1B
2A
3A
8A
FFFF

OE
1B
35
99
C8
C8

36
54
74
FF
FF
FF

07
10
18
46
C8
C8

09
19
30
87
FF
FF

OA
20

OC
32
50
FO
FF
FF

4096

01
02
03
04
05

256
512
1024
2048
4096
8192

01
02
03
04
05
06

1A
OF
08

128
128
256
512
1024
2048

00
00

12
10
08

256
256
512
1024
2048
4096

01
01
02

128
256
512

00

256
512
1024

2048
8"

Gap Length (GPL)4

No. of Data
BytealSector
(N)

01
02
03
04

04
02
01

04
02
01
12
10
08
04
02
01

80
C8
C8

01
02

OF
09
05

07
OE
1B

01
02
03

OF
09
05

OE
1B
35

03
04
05

2A

Remarks

1B

2A
3A

36
54
74

Notes:
1. Suggested values of GPL in Read or Write commands to avoid overlapping between Data field and ID field of contiguous sections.
2. Suggested values of GPL in Format a Track command.
3. In MFM mode the DDFDC cannot perform a read/write/format operation with 128 bytes/sector (N = 00).
4. Values of ST and GPL are in hexadecimal.

Result Phase:
R

SCAN COMMANDS

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T).

5

Head Number (H)·

6

Sector Number (R)·

7

Number of Data Bytes per Sector (N)·

The scan commands compare data read from the disk to data
supplied from the data bus. The DDFDC compares the data, and
looks for a sector of data which meets the conditions of DFDD =
Deus, DFDD s Deus, Dr DFDD 2: Deus (D = the data pattern in
hexadecimal). A magnitude comparison is performed (FF =
largest number, 00 = smallest number). The hexadecimal byte
of FF either from the bus or from FDD can be used as a mask
byte because it always meets the condition of the compare. After
a whole sector of data is compared, if the conditions are not met,
the sector number is incremented (R + STP - R), and the scan
operation is continued. The scan operation continues until one
of the following events occur: the conditions for scan are met
(equal, low or equal, or high or equal), the last sector on the track
is reached (EOT), or TC is received.

• The 10 information has no meaning in this command.

2-347

fJ

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765

SCAN EQUAL

If conditions for scan are met, the DDFDC sets the Scan Hit (SH)
flag in ST2 to a 1, and terminates the command. If the conditions for scan are not met between the starting sector (as specified
by R) and the last sector on the track (EOT), then the DDFDC
sets the Scan Not Satisfied (SN) flag in ST2 to a 1, and terminates
the command. The receipt of TC from the processor or DMA controller during the scan operation will cause the DDFDC to complete the comparison of the particular byte which is in process,
and then to terminate the command. Table 6 shows the status
of bits SH and SN under various conditions of scan.
Table 6.
Command
Scan Equal

Scan Low or Equal

RIW

BYTE

7

6

5

4

3

2

1

W

1

MT

MF

SK

1

0

0

0

1

2

X

X

X

X

X

HD

USl

usa

3

Track Number (T)

Scan Status Codes
Status Register 2

Comments

Bit2=SN

Bit 3 = SH

0

1

DFOO

1

0

0
0

1

DFOO
D FDO = Dsus
DFDO < Dsus
DFDO > Dsus

1
Scan High or Equal

Command Phase:

0
0
1

0
0
1

0
0

=

*

Dsus
Dsus

4

Head Number (H)

5

Sector Number (R)

6

Number of Data Bytes per Sector (N)

7

End of Track (EOT)

8

Gap Length (GPL)

9

Sector Test Process (STP)

0

Result Phase:
R

DFDO = Dsus
DFOO > Dsus
DFOO < Dsus

If SK = 0 and the DDFDC encounters a Deleted Data Address
Mark on one of the sectors, it regards that sector as the last sector of the track, sets the Control Mark (CM) bit in ST2 to a 1 and
terminates the command. If SK = 1, the DDFDC skips the sector with the Deleted Data Address Mark, sets the CM flag to a
1 in order to show that a Deleted Sector has been encountered,
and reads the next sector.

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector (N)

SCAN LOW OR EQUAL
When either the STP sectors are read (contiguous sectors = 01,
or alternate sectors = 02) or MT (Multi-Track) is set, the last sector on the track must be read. For example, if STP = 02, MT
= 0, the sectors are numbered sequentially 1 through 26, and
the scan command starts reading at sector 21. Sectors 21, 23,
and 25 are read, then the next sector (26) is skipped and the Index
Hole is encountered before the EOT value of 26 can be read.
This results in an abnormal termination of the command. If the
EOT had been set at 25 or the scanning started at sector 20, then
the scan command would be completed in a normal manner.

Command Phase:
RIW

BYTE

7

6

5

4

3

2

1

W

1

MT

MF

SK

1

1

1

0

1

2

X

X

X

X

X

HD

USl

usa

During a scan command data is supplied from the data bus for
comparison against the data read from the disk. In order to avoid
having the Over Run (OR) flag set in ST1 , data must be available
from the data bus in less than 27 p's (FM mode) or 13 p.S (MFM
mode). If an OR occurs, the DDFDC terminates the command
and sets bits 7 and 6 of STO to 0 and 1, respectively.

3

Track Number (T)

4

Head Number (H)

5

Sector Number (R)

6

Number of Data Bytes per Sector (N)

7

End of Track (EOT)

8

Gap Length (GPL)

9

Sector Test Process (STP)

Result Phase:
R

The following tables specify the command bytes and describe
the result bytes for the three scan commands.

2-348

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Head Number (H)

6

Sector Number (R)

7

Number of Data Bytes per Sector (N)

0

R6265, R6765

Double-Density Floppy Disk Controller (DDFDC)
During the command phase of the Seek operation the DDFDC
sets the Controller Busy (CB) flag in the MSR to 1; but during
the execution phase the CB flag is set to 0 to indicate DDFDC
non-busy. While the DDFDC is in the non-busy state, another
Seek command may be iSSUed, and in this manner parallel seek
operations may be performed on all drives at once.

SCAN HIGH OR EQUAL
Command Phase:
RIW

BYTE

7

6

5

4

3

2

1

W

1

MT

MF

SK

1

1

1

0

1

2

X

X

X

HD

USl

USO

3

Track Number (T)

4

Head Number (H)

X X

5

Sector Number (R)

6

Number of Data Bytes per Sector (N)

7

End of Track (EOT)

8

Gap Length (GPL)

9

Sector Test Process (STP)

0

No command other than Seek will be accepted while the DDFDC
is sending step pulses to any FDD. If a different command type
is attempted, the DDFDC will set bits 7 and 6 in STO to a 1 and
0, respectively, to indicate an invalid command.
If the FDD is in a not ready state at the beginning of the command execution phase or during the seek operation, then the
DDFDC sets the Not Ready (NR) flag in STO to a 1, sets STO
bits 7 and 6 to 0 and 1, respectively, and terminates the command.
If the time to write the three bytes of the Seek command exceeds
150 pS, the time between the first two step pulses may be shorter
than the Step Rate Time (SRl) defined by the Specify command
by as much as 1 ms.

Result Phase:
R

1

Status Register 0 (STO)

2

Status Register 1 (ST1)

3

Status Register 2 (ST2)

4

Track Number (T)

5

Command Phase:
RIW

BYTE

7

6

5

4

3

2

1

W

1

0

0

0

0

1

1

1

1

Head Number (H)

2

X

X

X

X X

0

US1

USO

8

Sector Number (R)

3

New Track Number (NTN)

7

Number of Data Bytes per Sector (N)

0

Result Phase: None.
SEEK
The three-byte Seek command steps the FDD readlwrite head
from track to track. The DDFDC has four independent Present
Track Registers for each drive. They are cleared only by the
Recalibrate command. The DDFDC compares the Present Track
Number (PTN) which is the current head position with the New
Track Number (NTN), and if there is a difference, performs the
following operation:
If PTN

RECALIBRATE
This two-byte command retracts the FDD readlwrite head to the
Track 0 position. The DDFDC clears the contents of the PTN
counters, and checks the status of the Track 0 signal from the
FDD. As long as the Track 0 signal (TRKO) is low, the direction
signal (LCT/DIR) output remains low and step pulses are issued
on FRISTP. When TRKO goes high the DDFDC sets the Seek
End (SE) flag in STO to a 1 and terminates the command. If the
TRKO is still low after 256 step pulses have been issued, the
DDFDC sets Seek End (SE) and Equipment Check (EC) flags in
STO to 1s, sets bits 7 and 6 of STO to 0 and 1, respectively, and
terminates the command.

< NTN: Sets the direction output (LCT/DIR) high
and issues step pulses (FRISTP) to the FDD
to cause the readlwrite head to step in.

If PTN

> NTN: Sets the direction output (LCT/DIR) low and
issues step pulses to the FDD to cause the
readlwrite head to step out.

The ability to do overlap Recalibrate commands to multiple FDDs
and the loss of the RDY signal, as described in the Seek command, also applies to the Recalibrate command.

The rate at which step pulses ara issued is controlled by the Step
Rate Time (SRl) in the Specify command. After each step pulse
is issued, NTN is compared against PTN. When NTN = PTN,
then the Seek End (SE) flag in STO is set to a 1, bits 7 and 6
in STO are set to 0, and the command is terminated. At this point
DDFDC asserts INT.

Command Phase:

The FDD Busy flag (bit 0-3) in the Main Status Register (MSR)
corresponding to the FDD performing the Seek operation is set
to a 1.
After command termination, all FDD Busy bits set are cleared by
the Sense Interrupt Status command.

RIW

BYTE

7

6

5

4

3

2

1

W

1

0

0

0

0

0

1

1

1

2

X

X

X

X

X

0

USl

USO

Result Phase: None.

2-349

0

fJ

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765
SENSE INTERRUPT STATUS

Command Phase:

Interrupt Request (INT) is asserted by the DDFDC when any of
the following conditions occur:
1. Upon entering the result phase of:
a. Read Data command
b. Read a Track command
c. Read ID command
d. Read Deleted Data command
e. Write Data command
f. Format a Track command
g. Write Deleted Data command
h. Scan commands

Result Phase:
Status Register 0 (STO)
Present Track Number (PTN)

SPECIFY

2. Ready (RDY) line from the FDD changes state

The three-byte Specify command sets the initial values for each
of the three internal timers. The Head Unload Time (HUT) defines
the time from the end of the execution phase of one of the
readlwrite commands to the head unload state. This timer is
programmable from 16 to 240 ms in increments of 16 ms
(1 .. 16 ms, 2 '"' 32 ms, ... F '"' 240 ms).

3. Seek or Recalibrate command termination
4. During execution phase in the Non-DMA mode
INT caused by reasons 1 and 4 above occur during normal
command operations and are easily discernible by the processor.
During an execution phase in Non-DMA mode, bit 5 in the MSR
is set to 1. Upon entering result phase this bit is set to O. Reasons
1 and 4 do not require the Sense Interrupt Status command. The
interrupt is cleared by reading or writing data to DDFDC. Interrupts caused by reasons 2 and 3 are identified witil the aid of
the Sense Interrupt Status command. This command resets INT
and sets/resets bits 5, 6, and 7 of STO to identify the- cause of
the interrupt. Table 7 defines the seek and interrupt codes.

The Step Rate Time (SAT) defines the time interval between
adjacent step pulses. This timer is programmable from 1 to
16 ms In increments of 1 ms (F = 1 ms, E = 2 ms,
D 3 ms, ... O 16 ms.)

=

=

The Head Load Time (HlT) defines the time between the Head
Load (HDl) signal going high and the start of the readlwrite
operation. This timer is programmable from 2 to 254 ms in
increments of 2 ms (01 .. 2 ms, 02 = 4 ms, 03 = 6 ms, ...
7F = 254 ms).

The Sense Interrupt Status command is used in conjunction with
the Seek and Recalibrate commands which have no result phase.
When the disk drive has reached the desired head position the
DDFDC asserts interrupt output. The host CPU must then issue
a Sense Interrupt Status command to determine the actual cause
of the interrupt, which could be Seek End or a change in ready
status from one of the drives (see example in Figure 3).

The time intervals are a direct function of the clock (ClK on pin 19).
Times indicated above are for an 8 MHz clock. If the clock is
reduced to 4 MHz (mini-floppy application) then all time intervals
are increased by a factor of two.
The choice of DMA or Non-DMA operation is made by the NonDMA mode (ND) bit. When this bit = 1 the Non-DMA mode is
selected, and when ND = 0 the DMA mode is selected.

Issuing a Sense Interrupt Status command without an interrupt
pending is treated as an invalid command.

Command Phase:

Table 7.

STO Seek and Interrupt Code Definition for
Sense Interrupt Status

Status Register 0
(STO) Bits
Intsrrupt Code
(Ie)

Seek End
(SE)

6

5

1

1

0

ROY line changed
state, either polarity

0

0

1

Normal tsrmination of
Seek or Recalibrste
command

0

1

1

Abnormal termination of
Seek or Recalibrate
command

BYTE

7

W

1

o

SAT HUT HLT NO -

Cause

7

RIW

6

I

2

SAT

3

HLT

Step Rate Time
Head Unload Time
Head Load Time
Non-OMA mode

Result Phase: None.

2-350

I

5

I4

I 0 I 0 I0

3

I

oI

2
0

I

I

1
1

I

I

0
1

HUT

T NO

R6265, R6765

Double-Density Floppy Disk Controller (DDFDC)
I - Seek (or Reeallbrate) Command

r

INT
CS

Ao

Command Phase

Sanse Interrupt Statua Command -j

• ,

-t-- Execution Phase -!,-Command Phase~- Result Phase-l

I
I
I

I

I

I

II

I

I

I ,--------...;....,

I

I

I

1J rL
.-~I---------------,r-------,
u n.

-'iSTl un u .fil

U ffi,

I

fJ

I

WR~
. DID
ROM

u--ur------------.u

---u

J---,_y

][

][

n.......,;--_---'n'--.------'~
z

WU

~Q
ii:1!i
~Q

z~

z
z_

I-

Figure 3.

Sense Interrupt Status

Command Phase:

SENSE DRIVE STATUS

w

Command Phase:
RIW

BYTE

7

6

5

4

3

2

1

0

W

1

0

0

0

0

0

1

a

a

2

x

X

x x

X

HD

USl

usa

Invalid Codes

Result Phase:

I

R

I

Status Register a (STO) = 80

PROCESSOR INTERFACE

Result Phase:
R

o

RIW

This two-byte command obtains and reports the status of the FDDs.
Status Register 3 (813) is returned in the result phase and contains the drive status.

Status Register 3 (ST3)

During the command or result phases, the Main Status Register
(MSR) must be read by the processor before each byte of information is transferred to, or from, the DDFDC Data Register. After
each byte of data is written to, or read from, the Data Register,
the processor should wait 12 pS before reading the MSA. Bits 6
and 7 in the MSR must be a 0 and 1, respectively, before each
command byte can be written to the DDFDC. During the result
phase, bits 6 and 7 of the MSR must both be 1s prior to reading
each byte from the Data Register onto the data bus. Note that
this status reading of bits 6 and 7 of the MSR before each byte
transfer to and from the DDFDC is required in only the command
and result phases and not during the execution phase.

INVALID COMMAND
If an invalid command (i.e., a command not previously defined)
is received by the DDFDC, then the DDFDC terminates the command after setting bits 7 and 6 of STO to 1 and 0, respectively. The
DDFDC does not generate an interrupt during this condition. Bits
6 and 7 (010 and ROM) in the MSR are both set to a 1 indicating
to the processor that the DDFDC is in the result phase and that
STO must be read. A hex 80 in STO indicates that an invalid command was received.

During the result phase all bytes shown in the result phase must
be read by the processor. The Read Data command, for example,
has seven bytes of data in the result phase. All seven bytes must
be read to successfully complete the Read Data command. The
DDFDC will not accept a new command until all seven bytes have
been read. Other commands may require fewer bytes to be read
during the result phase.

A Sense Interrupt Status command must be sent after a Seek or
Recalibrate interrupt, otherwise the DDFDC considers the next
command to be an invalid command.
In some applications the user may wish to use this command as
a No-Op command, to place the DDFDC in a standby or no operation state.

2-351

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765
DATAIN/OUT
(010)
(MSR BIT 6)
REQUEST
FOR MASTER
(RQM)
(MSR BIT 7)

FROM DDFDe TO DATA BUS
FROM DATA BUS TO DDFDC

I
I
I

WRITE (WR)
READ (RD)

I I
I I
I

I READy!
,

iJr--1---1LJ
I

L

II

I

I

I
I

I

I

I
I
A

I

I
I
I

I
I

I

L.J

I

I I I I0
B

A

C

I

I

i
I
I

I
I
I

I

U
C

I

I I

10

IBI A

NOTES

o

DATA REGISTER READY TO BE WRITTEN INTO

[!] DATA REGISTER NOT READY TO BE WRITTEN INTO
Figure 4,

[£] DATA REGISTER READY FOR NEXT DATA BYTE TO BE READ

o

DATA REGISTER NOT READY FOR NEXT DATA BYTE TO BE READ

DDFDC and System Data Transfer Timing

the EOT sector is read), INT is asserted to indicate the beginning of the result phase. When the first byte of data is read during the result phase, INT is reset low.

INTERRUPT REQUEST MODE
During the execution phase, the MSR need not be read. The
receipt of each data byte from the FDD is indicated by INT high
on pin 18. When the DDFDC is in Non-DMA mode, INT is asserted
during the execution phase. When the DDFDC is in the DMA
mode, INT is asserted at the result phase. The INT signal is reset
by a read (RD low) or write (WR low) of data to the DDFDC.
A further explanation of the INT signal is described in the Sense
Interrupt Status command on page 16. If the system cannot
handle interrupts fast enough (within 13 pS for MFM mode or 27 pS
for FM mode), it should poll bit 7 (ROM) in the MSR. In this case,
ROM in the MSR functions as an Interrupt Request (INT). If the
ROM bit is not set, the Over Run (OR) flag in ST1 will be set to
a 1 and bits 7 and 6 of STO will be set to a 0 and 1, respectively.

During a write command, the DDFDC asserts DRO as each byte
of data is required. The DMA controller responds to this request
with DACK (DMA Acknowledge) and WR low (write).
When DACK goes low the DMA Request is reset (DRO low). After
the execution phase has been completed (TC high or the EOT
sector is written), INT is asserted. This signals the beginning of
the result phase. When the first byte of data is read during the
result phase, the INT is reset low.

FDD POLLING

DMA MODE

After the Specify command has been received by the DDFDC,
the Unit Select lines (USO and US1) begin the polling mode.
Between commands (and between step pulses in the Seek Command) the DDFDC polls all the FDD's looking for a change in
the RDY line from any of the drives. If the RDY line changes state
(usually due to the door opening or closing) then the DDFDC
asserts INT. When Status Register 0 (STO) is read (after Sense
Interrupt Status command is issued), Not Ready (NR = 1) will
be indicated. The polling of the RDY line by the DDFDC occurs
continuously between commands, thus notifying the processor
which drives are on- or off-line. Each drive is polled every 1.024 ms
except during read/write commands.

When the DDFDC is in the DMA mode (ND = 0 in the third command byte of the Specify command), DRO (DMA Request) is
asserted during the execution phase (rather than INT) to request
the transfer of a data byte between the data bus and the DDFDC.

During a read command, the DDFDC asserts DRO as each byte
of data is available to be read. The DMA controller responds to
this request with DACK low (DMA Acknowledge) and RD low
(read). When DACK goes low the DMA Request is reset (DRO
low). After the execution phase has been completed (TC high or

2-352

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765
R6765 (FM MODE)
FIELD

GAP 4.

SYNC

NO. OF BYTES

CO.

0.

DATA

FF

DO

lAM

GAP1

SYNC

,0.

0.

FF

DO

Fe

lOAM

HO

CYL

CRC

SYNC

GAP'

,,.

DATA AM

DATA

00

GAP 3

0

0.

FF

FE

I

INDEXJL

NO

SEC

CRO

GAPC.

0

FlORPI

I

REPEAT N TIMES

R6265 (FM MODE)
FIELD

GAP 1

SYNC

NO OF .YTES

".

0.

DATA

FF

00

lOAM

HO

eYL

SEC

NO

eRC

Fe

.

GAP,

SYNC

,,.
FF

00

DATA AM

DATA

GAP 3

0

CRe

F8 OR Fa

I

REPEAT N TIMES

INDEXf\J:..

GAP C

0

R8785 (MFM MODE)

...

GAP . .

CE

SYNC

,,.
DO

..

lAM

C2

Fe

GAP 1

SYNC

so •

,,.

CE

00

INDEX~

..,

lOAM

HO

CYL

SEC

NO

eRe

FE

I

GAP'

SYNC

22,

12,

CE

00

...,

DATA AM

DATA

GAP 3

0

F8

CRC

GAP4b

0

Fa

I

REPEAT N TIMES

R6265 (MFM MODE)
FIELD

GAP 1

SYNC

NO OF BYTES

32,

12,

DATA

c.

..,

00

INDEX~

lOAM

HO

CYL

SEC

NO

eRO

FE

SYNC

'"

12,

4E

I

..,

DATA AM

DO

DATA
CRe

I

--.f\

.

~

~------------------~f~

~

FORMAT
R6765
VCOSYNC

r------,

VCO SYNC

WE

_ _ _----'\"---'1 _____~

,,------,,

NOTE: _ _ READ
____ WRITE

Figure 6.

DDFDC Formats
2·353

,r------r

____
IGAP41
~

__

~

I

;

~

__L -__
____
IDIGAP21
IDfr
~

~

~

~

~

~

__ 11 __
____
____
I GAP
IDIGAP21
DATAl ______
GAP 3

R8285

~

--.f\'-------------------jf~
~

INDEX
FORMAT

I

0

FI

DDFDC Formats

WE

GAPC

GAP 3

0

FB

REPEAT N TIMES

Figure 5.
INDEX

GAP 2

fJ

:D

m
m
Y'

I\)

:D

atc.n
A1-A15

A

K... DO-D7

~

~

RST

~>

~

lID
RD
WR

c
0

r-

~-

-

11~'

~I jgI ~ I!!
III

~

~ tll
RDW
....!!!!!:l!II.

yeo
RDD

'~

zao

~

I

~~I I~

~

PSO
PS1

CPU

WDA

--

DATA
jRECOVERY

.-

...

FlTITRKO

R62651
R6765
DDFDC

...

0
ClK

.J

L

'"

OSC

L

J

J

WRITE

I

LCLOCK
J
GEN

WCK

RWISEEK
RDY

WE
CLK ....

INT

FRlSTP
LCT/oIR

INT

ILDX
HDl
HD
USO

MUX

....

__

WRITE DATA

~
~

MUX

c

oC

0"

JPRE.coMP

WPITS

MEMORY

READ DATA

t-----t
1----1

t---4

WRITE PROTECT
TWO-SIDE
FAULT

TRACK 0
FAULT RESET
STEP
LDWCURRENT
DIRECTION

~

CD

c•

CD
:::J

(I)

~
"11

0'

'a
:EADY
WRITE ENABLE
NDEX
EADLOAD
EADSElECT
INIT SELECT 0
INIT SELECT 1

~

c

iii'
~

~
:::J

-...
a
CD

C
C

"11

C

Figure 7.

R6265/R6765 DDFDC Interface to Z 80

,g

R6265, R6765

CLK

Double-Density Floppy Disk Controller (DDFDC)

~

I

Figure 8. Clock Timing

All,

ca, DACK

DATA OUT

DO-D7

INT

Figure 9.

Read Cycle Timing

All, CS, DACK

DATA IN

DO-07
INT

Figure 10. Write Cycle Timing

2-355

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765

~------~17J--------~

DRQ

WRORRD

Figure 11. DMA Operation Timing

WRITE CLOCK
(WCK)r.;;;-,

®
WRITE ENABLE
(WE)@
-'\.r--""":i..k-~~.....

PRESHIFT 0 OR 1
(PSO. PS1)

r----...

WRITE DATA
(WDA)

Figure 12. FDD Write Operation Timing

READ DATA (RDD)

READ DATA WINDOW (RDW) _ _ _ _ _ _....J

NOTE:
EITHER POLARITY DATA WINDOW IS VALID

Figure 13. FDD Read Operation Timing

2-356

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765

"~"" ~;.....---------~ ,,----SEEK
(RW/SEEK)

DIRECTION
(LCT/DIR)

STEP
(FR/STP) _ _ _ _ _ _..11

Figure 14.

(FR) _____"
FAULT RESET

Seek Operation Timing

INDEX
(IDX)

" -_ __

@
Figure 15.

Fault Reset Timing

I
TERMINAL COUNT
(TC)

RESET

:LI

---.1.I

-l

~@

Terminal Count Timing

INPUT/OUT

CLOCK

TEST POINT

t-@

TEST POINT

.I
3 . 0 V - - y 2.4Vj' 2.4V V -

2.4V-V2.0V;t'i0VY

O.BV'''---

0.3V --./\0.65V 0 . 6 5 V " - - -

INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND 0.45 V FOR
A LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.0V FOR
A LOGIC "1" AND O.BV FOR A LOGIC "0:'

Figure 19.

~
I

Figure 18. Reset Timing

.,/
0.45V --.-.I\O.BV

I

~

(RST)~
I

I

I

Index Timing

I

I

~ .

--t
Figure 17.

Figure 16.

CLOCKS ARE DRIVEN AT 3.0V FOR A LOGIC "1" AND 0.3V FOR A
LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.4V FOR A
LOGIC "1" AND 0.65V FOR A LOGIC "0:'

AC Timing Measurement Conditions

2-357

Double-Density Floppy Disk Controller (DDFDC)

R6265, R6765
AC CHARACTERISTICS

(Vcc = 5.0 Vdc ±5%, Vss = 0 Vdc, TA = O°C to 70°C)
Ref.
Fig.

No.
1

5

6

7

8

2

Clock Period

Characteristic
8" or 3·1/2" FDD
5·1/4" FDD

CPo
CPr

-

CPI

-

ISLRL
IRHSH
IRLRH
I RLOV
I RHOZ

IAR
IRA
IRR
I RO
IOF

0
0
250

IRI
lAW

-

16
17
18
19
19a

WR High 10 INT High
DRO Cycle Time
DRO High 10 RD, WR High (Response)
DACK Low 10 DRO Low (Delay)
DRO High 10 DACK Low (Delay)
DRO High 10 RD Low (Delay)
DRO High 10 WR Low (Delay)
WCK Cycle Time
(8" or 3-1/2" FDD)

I

22
23
24
25
25a
26
27
28

31
32
33
35
36
37
38
39
40
41
42
43
44
45
46
47

tWHIH
locy
IOHXH
IALQL
IOHAL
IOHRL
IOHWL
I KCY

lAM
IMA
IMR
I MW
ICY

(5-1/4" FDD)

WCK High Widlh
WCK Rise Time
WCK Fall Time
WCK High 10 PSO, PS1 Valid (Delay)
WCK High 10 WE High (Delay)
PSO, PS1 Valid 10 WDA High (Delay)
WDA High Widlh
WE High 10 WCK High or WE Low 10 WCK Low
RDW vycle Time
(8" or 3-1/2" FDD)

I

l

10vwH
IWHOX

IWA
Iww
low
Iwo
IWI
tMCY
I MRW

IKHKL
IKLKH
IKHKL
IKHPV
IOHEN
I pvOH
IOHOL
IEHKH
IwCY

10
Ir
tl
Icp
ICWE
Ico
Iwoo
IWE
IwCY

(5-1/4" FDD)

RDW Valid 10 RDD High (Selup)
RDD Low 10 RDW Invalid (Hold)
RDD High Widlh
USO, US1 Valid to SEEK High (Selup)
SEEK Low 10 USO, US1 Invalid (Hold)
SEEK High 10 DIR Valid (Setup)

IRHRL
IUVSH
I SLUI
I SHOV

DIR Invalid to SEEK Low (Hold)
DIR Valid 10 STP High (Selup)
STP Low to DIR Invalid (Hold)
STP Low to USO, US1 Invalid (Hold)

IOXSL
IOVTH
I TLOX
I TLUX

STP High Widlh
STP Cycle Time
FR High Widlh
IDX High Widlh
TC High Width
RST High Widlh

ITHTL
I TCY
IFHFL

IWVRH
tRLW1

tlHIL

ITHTL
IRHRL

IWRO
tROW
I ROO
Ius
Isu
Iso
los
lOST
tSTD
ISTU
1ST?
Isc
IFR
IIOX
tTC
I RST

125

Max.
5

~5

ICA

IRHIH
I SLWL
I WHSH
I WLWH

Typ.

4C

ICLCH
ICHCL

;jU

12
13
14
15

CPCY

Clock Rise Time
Clock Fall Time
AD, CS, DACK Valid 10 RD Low (Selup)
RD High 10 AO, CS, DACK Invalid (Hold)
RD Low Width
RD Low 10 Dala Valid (Access)
RD High 10 Oulput High Z
RD High 10 INT High
AO, CS, DACK Valid 10 WR Low (Selup)
WR High 10 AD, CS, DACK Invalid (Hold)
WR LowWidlh
Data Valid 10 WR High (Selup)
WR High 10 Dala Invalid (Hold)

I

11

Icy

Min.
12C

Clock High

~1

10

All. Sym.

3
4
5
6
7
8
9
10
11
12
13
14
15

20

9

Symbol

4

20

tl~.5

-

20
20

-

-

-

-

200
100
500

0
0
250
150
5

-

-

-

-

500

13

-

-

-

-

200
800
250

80

20
20
20
IWCH-50
20

15
15
40
12
15
7
30
1
24
5
6
333
8
10
1
14

-

-

2
1
4
2
250

-

-

-

-

-

-

ns
ns

~~~ = ¥
~~~: ¥

~~~ = ~
~~~ ;; ¥

uS
~s

fiS
ns
ns
ns
~s

p.s
P.s
P.s
~s

-

~s

-

CLK = 8 MHz

~s

-

-

ICY = 125 ns

uS

ns
ns
ns
ns

8
note 1
10

CLK = 8 MHz

~s

100
100

-

CL = 100 pF
CLK = 8 MHz

1<8

ns
ns
ns
ns

-

Test
Conditions
:';LK = B MHZ
vLK - 4 M~ Z
:';LK - 8 MHZ
vL.K
8MHz

~s

350
20
20
100

-

7

-

ns
ns

-

-

-

200

-

-

-

~s

100

2
I
4
2

~s

12

-

-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ClK = 8 MHz

~s

P.s
P.s
P.s
ICY
ICY
ICY

1. Isc = 33 ~s min. is for differenl drive unils. In Ihe case of Ihe same unil, Isc can range from 1 ms 1016 ms wilh 8 MHz clock
period, and 2 ms to 32 ms wilh 4 MHz clock, under software conlrol.

2-358

R6265, R6765

Double-Density Floppy Disk Controller (DDFDC)

ABSOLUTE MAXIMUM RATINGS·
Parameter

Symbol

Value

Unit

Vee

-0.3 to + 7.0

V

I nput Voltage

VIN

-0.3to +7.0

V

Output Voltage

VOUT

-0.3 to + 7.0

V

Oto +70

C'

-55to +150

C'

Supply Voltage

Operating Temperature Range

TA

Storage Temperature Range

TSTG

"NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

OPERATING CONDITIONS
Parameter

Range

Vee Power Supply

5.0V ±5%

Operating Temperature

O'C to 70'C

DC CHARACTERISTICS
01cc = 5.0 Vdc ±5%, Vss = 0 Vdc,
Parameter

TA = COC to 7OOC, unless otherwise noted)
Symbol

I nput Low Voltage
logic
CLK and WCK

Vil

Input High Voltage
Logic
CLK and WCK

VIH

Output Low Voltage

VOL

Output High Voltage

VOH

Vee Supply Current

Icc

Input Load Current

III

Min

Max

Unit

Test Conditions

V
-0.5
-0.5

0.8
0.65

2.0
2.4

Vee + 0.5
Vee + 0.5

V

2.4

All Inputs

0.45

V

Vee = 4.75V, 10l = 2.0 rnA

Vee

V

Vee = 4.75V, 10H = -200 pA

150

rnA

Vee = 4.75V

10

pA

VIN = Vee

-10

pA

VIN = OV

pA

Vee = OV to 5.25V, Vss = OV
VOUT = Vee

High Level Output Leakage Current

ILOH

10

Low Level Output Leakage Current

ILOl

-10

pA

Vee = OV to 5.25V, Vss = OV
V OUT = +0.45V

Internal Power DiSSipation

PINT

1.0

W

TA = 25'C

-

CAPACITANCE
(TA = 25°C; fe = 1 MHz; Vee = OV)
Parameter

Symbol

Max Limit

Unit

Clock Input

CIN(II)

20

pF

Input

CIN

10

pF

Output

COUT

20

pF

Note: All pins except pin under test tied to ground .

._---<-

2-359

R6265, R6765

Double-Density Floppy Disk Controller (DDFDC)

PACKAGE DIMENSIONS
40·PIN CERAMIC DIP

[: 0 :=]]

DIM
A

B
e
0

1---- ------.,1
A

~F 11I111

H

J'

I-

SEATiNG PLANE

o

tNJU

iY'~
ILK

111II1 [ 1-1

:JLi Iii iii iii iii i

F

I

G-J

-1

j

c

I

-+-J

M

-1

G
H
J
K
L
M
N

MILLIMETERS
MIN
MAX
60.29 51.31
14.86 15.62
2.54
4.19
0.36 -0.53
0.76
1.40
2.54 Bse
0.76
1.78
0.20
0.33
2.54
4.19
14.60 15.37
10·
o·
0.51
152

INCHES
MIN
MAX
1.980 2.020
0.565 0.615
0.100 0.165
0.015 0.021
0.030 0.055
0.100 Bse
0.030 0.070
0.008 0.013
0.100 0.165
0.575 0.605
10·
o·
0.020 0060

MILLIMETERS
MIN
MAX
51.28 52.32
13.72 14.22
3.55
508
0.36
0.51
1.02
1.52
2.54 Bse
1.65
216
0.20
030
305
3.56
1524 Bse
7·
10·
1.02
0.51

INCHES
MIN
MAX
2.040 2.060
0.540 0.560
0.140 0.200
0.014 0020
0.040 0060
0.100 Bse
0.065 0.085
0008 0012
0.120 0.140
0.600 Bse
7·
10·
0.020 0.040

40·PIN PLASTIC DIP

DIM
A

B
e
D

F

G
H

J
K
L
M
N

2-360

SECTION 3
R6500/* MICROCOMPUTERS
Page

Product Family Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2

R65COO/21 and R65C29 Dual CMOS Microcomputer

and Dual CMOS Microprocessor ....................... . . . . . . . . . . . . . . . . . . .

3-3

R65F11 and R65F12 FORTH One-Chip Microcomputers. . . . . . . . . . . . . . . . . . . . . . . ..

3-36

R65FRX and R65FKX RSC FORTH Development and Kernel ROMs. . . . . . . . . . . . . ..

3-68

R6501Q One-Chip Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-76

R6500/1 One-Chip Microcomputer ........................................... 3-105
R6500/1 E Emulator Device ................................................. 3-136
R6500/1 EB and R6500/1 EAB Backpack Emulator .............................. 3-143
R6500/11, R6500/12, R6500/15 and R6500/16 One-Chip Microcomputers ........... 3-149
R65/11 EB and R65/11 EAB Backpack Emulator ................................ 3-184

R6511Q and R6500/13 One-Chip Microprocessor and One-Chip Microcomputer ..... 3-189
R6500/41 and R6500/42 One-Chip Intelligent Peripheral Controllers ............... 3-224
R65/41 EB and R65/41 EAB Backpack Emulator ................................ 3-253

R6541 Q and R6500/43 One-Chip Intelligent Peripheral Controllers ................ 3-258

3-1

R6500/* SINGLE-CHIP MICROCOMPUTER FAMILY
Higher Performance, Broader Applications, Software Compatibility

The R6500/' single-chip microcomputers are completely
software compatible with the 8-bit multi-chip family. They let
you move easily from a multi-chip to a single-chip system
solution when the application warrants it. They also function
as intelligent peripheral controliers. The family continues to
expand to include dual processors and CMOS versions. The
R6500/' devices have faster execution speeds for most
applications, based on our competitors own figures, even
though some others use higher frequency crystals.
Features include 1.5 to 4K bytes of ROM, 64 to 192 bytes
of RAM, 23 to 56 I/O ports, multiple use counter/timers,
serial communication channels, new bit manipulation
instructions, expansion bus, multiple bus interfaces, directly
executable RAM with low power standby, multiple interrupts,
all from a single 5V power supply.
Three intelligent peripheral controllers offer design
effective upgrading potentials for existing 6800, 8080, Z80
and 6500 systems. They're also available in ROM-less
versions, for large memory system applications and for

developing and simulating products in prototype, with
external memory.
And, two versions even have all system software on chip,
including an operating system and high level FORTH
language. It's an extremely versatile single-chipper, and
available in three configurations to accommodate application
programs to 48K.
Three different sets of development ROM permit systems
from 16 to 40 I/O and 8K to 48K of application program
memory.
As the highest performance single-chip family, the
R6500/* devices are in use now in applications such as
printers, telephone answering equipment, fixed disk drives,
stereos, industrial controllers, telecom, cash registers,
sewing machines, test equipment and more.
Check for yourself and see how a Rockwell R6500/* can
solve your system problem. There are no higher performing
8-bit single chippers, regardless of clock speeds.

ROCKWELL NMOS MICROCOMPUTERS-THE TOP PERFORMERS IN INDUSTRY
Features/Models

R6500/1

R6500/11

R6500/15

R6500/12

R6500/16

R6501Q/11Q

R6500/41

R6500/42

R6541Q

• ROM (xB)

2048

3072

4096

3072

4096

-

1536

1536

256

• RAM (x8)

64

192

192

192

192

192

64

64

64

• I/O Lines
• Serial Comm.

32

32

32

56

32

23

47

USART

-

USART

USART

USART

56
USART

• 16-Bit Counters

ONE

TWO

TWO

TWO

TWO

TWO

• Host/Slave Bus

-

-

-

-

-

-

4K

4K

• Expansion Bus
• Interrupts
- External
- Internal
- Host
• Standby RAM (mW)

16K

16K

16K

16K

65K

6
4

6
4

6
4

6
4

6
4

4
1

-

35

• Package

40 DIP

Alternatives for

8048/49

12
40 DIP

-

-

12

12

40 DIP

64 QUIP
8051

64 QUIP

12
64 QUIP

23

-

-

ONE

ONE

80/65

80/65

ONE
80/65
8K14K

4
1
2

12

8031

3-2

-

40 DIP

4
1
2

5
1
2

-

-

64 QUIP

64 QUIP

8041

R65COO/21 • R65C29

'1'

Rockwell

R65COO/21 DUAL CMOS MICROCOMPUTER
AND R65C29 DUAL CMOS
MICROPROCESSOR
PRELIMINARY

INTRODUCTION
FEATURES
• Nine interrupts
- Positive and negative edge detect
-Low level detect (external IRQ)
-CounterlTImer A and B underflow
-Inter-processor communication
- Host computer data transfer
-Non-maskable
-Reset
• Flexible system operation
-Memory mapped I/O for easy programming
-Page zero location for memory effiCient access
• Low power at normal frequency (40 mw at 2 MHz)
• Reduced power at low frequency (2.0 mw at 2 MHz/128)
• System clock rates from 10 KHz to 4 MHz
• 5V ± 10% power supply
• 64-pin QUIP

• Two enhanced CMOS R6502 CPU's in one device
-Common memory and I/O
-Shared data and subroutines
-Independent CPU registers and interrupt vectors
-Independent reset operation and programs
-R6502 software and timing compatible
• 10 new instructions for faster and smaller programs
-Unsigned Mu~iply (MUL)
-Set and Reset Memory Bn (SMB and RMB)
-Branch on Bn Set and Reset (BBS and BBR)
-Uncondnional Branch (BRA)
-Push and Pull Index Registers (PHX, PHY, PLX, PLY)
• Microcomputer/microprocessor/peripheral controller operation
-Stand-alone microcomputer
2048 x 8 mask programmable ROM
128 x 8 random access memory (RAM)
-Enhanced microprocessor
Built-in RAM, ROM and I/O with expand ability
8-, 12- or 16-bit extension address bus
-Programmable peripheral controller
Host data bus interface (Z80/8080 or 6500/6800 option)
Self-contained or expandable
• 16-bit Counter/Timer A wnh eight modes, and prescaler
-Timer Off
-Free-Run Event Counter
-Free-Run Pulse Width Measurement
-One-Shot Retriggerable Timer
-One-Shot Interval Timer
-Free-Run Interval Timer
-One-Shot Pulse Generator
-Free-Run Pulse Generator
• 16-bit Counter/Timer B wnh four modes
-Free-Run Interval Timer
-Free-Run Pulse Generator
-Event Counter
-Pulse Width Measurement
• Up to 52 general purpose input/output lines
-Five bidirectional 8-bit ports (PA, PB, PC, PO and PF)
-One 8-bit output port (PE)
-One 4-bn input port (PG)
-Multi-purpose operation for selected ports

SUMMARY
The Rockwell R65COO/21 is a complete, high performance
8-bit, CMOS dual microcomputer in a single chip and is compatible wnh all R6500 microprocessors except that it has
additional instructions including a 1O-clock time multiply.
The R65COO/21 consists of two enhanced instruction set 6502
CPU's in one device. The device also has 2048 bytes of ReadOnly Memory (ROM), 128 bytes of Random Access Memory
(RAM) and versatile interface circuitry. The interface circuitry
ConSists of two multlmode programmable 16-bit counter/timers
and 52 general purpose input/output lines. Some of these input/
output lines may be used as address, data and control lines
for expanded systems or as data and control lines when the
R65COO/21 is used as a programmable peripheral controller.
The two CPU's in the R65COO/21 are functionally independent.
Each has its own set of registers, its own reset and interrupt
vectors and operates under control of its own program. The two
CPU's do, however, share the same memory and system VO
resources. ThiS allows direct commUnication between the two
CPU's and allows sharing of subroutines and common data
areas where desired. Programming and system design for
applications which require simultaneous colotrol of two or more
independent asynchronous processes is thus simplified because
one CPU may control one process while the other controls

Document No. 29651 N64
3-3

Product Description Order No. 2161
Rev. 2, October 1984

R65COO/21. R65C29

Dual CMOS Microcomputer/Microprocessor
DEVELOPMENT SYSTEM SUPPORT

another one. Consequently, complex programming usually
needed to interleave the control functions or to implement an
interrupt driven system, is not required.

Prototype circuit and software development support are available using the Rockwell Design Center (ROC) and R65COO/21
Personality Module. Program development and debugging aids
such as text editing, symbolic assembly with conditionals and
macros at the absolute and relocatable/linking level, and single/
multiple step execution with instruction/data tracing are provided. Real-time in-circuit emulation in the target environment
is also supported.

In a multiple computer approach, both processors may need the
same subroutines so that some portions of memory must be
duplicated In both systems. The dual CPU's share the same
program memory, therefore only one set of subroutines is
required and both CPU's may even be using them at the same
time without interference.
In addition to the dual CPU's, the R65COO/21 also has the
innovative architecture and the demonstrated high performance
of the well established R6502 CPU, flexible input/output which
provides improvements over the R6522 Versatile Interface
Adapter (VIA) device, and production efficient on-chip ROM and
RAM. These features make the R65COO/21 a leading candidate
for most imbedded microcomputer applications.

NOTE

All descriptions of R65COO/21 operation in this document
also apply to the R65C29 except for internal ROM, and
as otherwise noted.

A system using the R65COO/21 Dual CMOS Microcomputer Will
be simpler in design, use less program memory, require fewer
components, reduce circuit board sizes, simplify test requirements, and minimize field maintenance-all contributing to lower
production and support costs. In addition, simpler designs shorten
development effort and time-leading to reduced development
costs and faster product to market.

ORDERING INFORMATION
The R65COO/21 Dual CMOS Microcomputer can be ordered in
volume quantities with the following speed capability and mask
option indicated in the R65COO/21 ROM Code Order Form (Document Order No. 2134)
• 1, 2, 3, or 4 MHz system clock (¢2)
• Crystal/master clock or slaved clock input mask option

The R65C29 Dual CMOS Microprocessor, a ROM-less version
of the R65COO/21 with permanently extended data and address
bus, is also available. The R65C29 is ideal for dual CPU applications requiring changeable ROM and/or extended RAM, ROM
or 110, and can also be used for R65COO/21 prototype circuit
development. The R65COO/21 can also operate in an emulation
mode, like the R65C29, with its internal ROM disabled.

The R65C29 Dual CMOS Microprocessor has the following
characteristics:
• Crystallmaster clock input
• 8-blt data bus and 16-bit address bus extension
• No internal ROM

3-4

Dual CMOS Microcomputer/Microprocessor

R65COO/21 • R65C29

INTERFACE
The interface signals for the R65COO/21 and R65C29 are
described in Table 2. The descriptions of the selectable bus
expansion pins (16·bit address mode) for the R65COO/21 apply
to permanent bus expansion pins for the R65C29.

The interfaces for the R65COO/21 and R65C29 are illustrated
in Figure 1.
The pin assignments for the R65COO/21 and the R65C29 are
shown in Figure 2. The R65C29 pin assignments are the same
as the R65COO/21 except that bus expansion functions are per·
manently assigned instead of general purpose ports D and E.

VDD
CPU A

CPUB

OSCILLATOR
CLOCK
GENERATOR

2D48x8
ROM
R85COD121 ONLY

RtW

128x8
RAM

EMS
CONTROL
REGISTERS

I
II
I

PORTA

PAo-PA7

PORTB

PBDIPB7

PORTC

PCO·PC7
OPTIONAL USE:
HOST DATA BUS

PORTD

PDO-PD7
OPTIONAL USE:
EXP. BUS
DATA/LOWER ADDR. (ADDR. LOW)

PORT E

PED-PE7
OPTIONAL USE:
EXP. BUS
UPPER ADDR. (ADDR. HIGH)

PORT F

PFD-PF7
OPTIONAL USE:
PFD POS. EDGE
DETECT
PFI NEG. EDGE
DETECT
PF2 EXT. IRQ INPUT
PF3 TIMA 1/0
PF4 TIMB 110
PF5 --PF6 --PF7 HINT

PORTG

PGO-PG3
OPTIONAL USE:
PGD H'2IHRD
PGl HRrN/HWR
PG2 HRS
PG3 CS

TIMER A

TIMER B

Figure 1.

8

R65COO/21 and R65C29 Interface Diagram

3·5

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor

XTALO

Vee

~2

NMIA

EMS

PGO

Rm

PG2

PE6

POO

PE4

P02

XTALI

M
SYNC
PE7
PES
PE3
PE1
PF7
PFS
PF3

PE2

R6SCOO/21

PEO

P06

PF6

PCO

PF4

PC2

PF2

PC4

PFO

PC6

PA6

PBO

PF4

PB2

PA2

PB4

PAO

PB6

PF1
PA7
PAS
PA3
PA1

P04

~A

SYNC
A1S
A13
A11

XTALO

Vee

~2

NMIA

EMS

PGO

Rm

PG2

A9

PFS
PF3

AO/OO

A12

A2/02
R6SC29

PAS
PA3
PA1

A4/04

AS

A6/06

PF6

PCO

PF4

PC2

PF2

PC4

PFO

PC6

PA6

PBO

PA4

PB2

PA2

PB4

PAO

PB6

PF1
PA7

PG3
P01
P03
POS
P07
PC1
PC3
PCS
PC7
PB1
PB3
PBS

RES
NMIB
PG1

A14

A10
PF7

NMIB
PG1

PB7

Vss

XTALI

RES

PG3
A1/D1
A3/03
AS/OS
A7/D7
PC1
PC3
PCS
PC7
PB1
PB3
PBS
PB7

Vss

Figure 2.

R65COO/21 and R65C29 Pin Assignments

3-6

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor
Table 1.

R65COO/21 Pin Description

Pin No.

1/0

31-24

VO

PBO-PB7

40-33

I/O

Port B. General purpose 8-bit I/O Port B.

PCO-PC?

48-41

VO

Port C. General purpose 8-bit I/O Port C. Host Data Bus in Host Mode.

POO-P07

56-49

I/O

Port D. General purpose 8-bit I/O Port O. Multiplexed lower address (AO to A7) and Data
Bus (00-07) when Bus Extension Mode is selected.

PEO-PE7

15-8

0

Port E. General purpose 8-bit output Port E. Upper address (A8 to Allor A8 to A 15) when
Bus Expansion Mode is selected.

PFO-PF7

23-16

I/O

Port F. General purpose 8-bit I/O Port F. Under software control, each line has alternate
functions as follows:

PFONEG (PFO)

23

I

PFO Positive Edge Detect. Maskable CPU interrupt on PFO

PF1POS (PF)

22

I

PF1 Negative Edge Detect. Maskable CPU Interrupt on PFI Negative Trans~lon.

Signal Name
PAO-PA7

Description
Port A. General purpose 8-bit I/O Port A.

Pos~ive

Transition.

PF2LOW (PF2)

21

I

TIMA (PF3)

20

I/O

Timer A External Input/Output.

TIMB (PF4)

19

I/O

Timer B External Input/Output.

HINT (PF?)

16

0

Host Interrupt. Active-low maskable interrupt request to Host.

60-57

I

Port G. General purpose 4-bit input Port G. Under software control, Port G serves as the
Host Control Bus as follows:

H0'2/HRO (PGO)

60

I

Host Bus Clock/Read Strobe Input. Ji2 for 6500/6800 bus; Read Strobe for Z80/8080
bus.

HFVWiHWR (PG1)

59

I

Host Bus Read-Wrlte/Wrlte Strobe Input. FVW for 6500/6800 bus; Write Strobe for
Z80/8080 bus.

PGO-PG3

PF2 Low Level Detect. Maskable CPU interrupt on PF2 Low (external IRQ).

HRS (PG2)

58

I

Host Blls Register Select Input. Low selects Data Buffer; high selects Status Flags.

CS (PG3)

57

I

RES

63

I

Host Bus Active-Low Chip Select Input. Low selects Host Bus operation depending on
HRS and HFVW/HWR coding and Host Control and Status Register contents; high
disables Host Bus interface.
Reset. Active-low Reset input initializes R65COO/21 to initial conditions-resets all registers
and I/O lines.

NMIA

62

I

CPU A Non-Maskable Interrupt. Non-maskable negative edge sensitive Interrupt input to
CPUA.

NMIB

61

I

CPU B Non-Maskable Interrupt. Non-maskable negative edge sens~ive interrupt input to
CPU B.

EMS

5

Ji2

3

FVW

7

SYNC

6

0'A

4

0
0
0
0
0

XTALO

1

0

XTALI

2

I

VCC

64

Power. 5.0 Vdc.

VSS

32

GND. Signal and power ground.

External Memory Strobe. Active-low.
System Phase 2 Clock Output. Maskable as system clock input for slave operation.
Read/Write. Read/write control output. High during read, low during write.
Sync. Instruction sync output. High When Op Code fetched
Phase A. Phase A clock output. High during CPU A bus cycle, low during CPU B bus
cycle.
Crystal/Master Clock Return. Output connection to crystal (or no connection if external
master clock connected to XTALI). Input frequency is two times system clock (0'2) rate.
Crystal/Master Clock Input. Input connection from crystal (or external master clock).

3-7

Dual CMOS Microcomputer/Microprocessor

R65COO/21 • R65C29

FUNCTIONAL DESCRIPTION
The R65COO/21 consists of two central processor units (CPU's),
a 2048 x 8 read-only memory (ROM), a 128 x 8 random access
memory (RAM), five 8-bH parallel I/O ports, one 8-bit output
port, one 4-bit input port, two 16-bit counter/timer systems, a
variety of I/O control registers, and an independent interrupt
control system for each CPU. All of the ROM, RAM, VO, internal
buses, and the arithmetic logic unit (ALU) are shared by the two
CPU's. A memory map of the system is shown in Figure 3. An
overall block diagram of the R65COO/21 is shown in Figure 4.

INDEX REGISTERS
Each CPU has two index registers, X and Y. Each index register
may be used as a modifier to a base address supplied as a part
of the instruction being processed. The resulting effective address
is usually the sum of the base address plus the contents of the
indicated index register. The index registers are used in a
number of the addressing modes including zero page indexed,
absolute indexed, post-indexed indirect and pre-indexed indirect. Each index register also has a family of instructions which
allow loading, storing, incrementing, decrementing, and comparing the contents of the register. These are discussed thoroughly in the R6500 Programming Manual (Order No. 202).

NOTE
Throughout this document, unless specified otherwise, all
memory or register address locations are specified in
hexadecimal notation.

ADDRESS (HEXI

INTERNAL MEMORY

0000
001F
0020

INTERNAL READ-ONLY-MEMORY (ROM)

003F
0040
007F
0080

The ROM in the R65COO/21 consists of 2048 (2K) bytes of mask
programmable memory with an address space from F800 to
FFFF. ROM locations FFF2 through FFFF are assigned to interrupt and reset vectors for the two CPU's.

I/O AND CONTROL REGISTERS
EXTERNAL 1/0 EXPANSION2
NOT ACCESSIBLE
INTERNAL RAM (128 BYTES)'
(SHARED WITH 0180-01FF)

OOFF
0100

EXTERNAL RAM EXPANSION2

017F
0180

INTERNAL RANDOM ACCESS MEMORY (RAM)
The internal RAM consists of 128 bytes of read/write memory
with assigned page zero addresses of 0080 through OOFF.

INTERNAL RAM (128 BYTES),
(SHARED WITH 0080-00FF)

01FF
0200

EXTERNAL MEMORY AND
1/0 EXPANSION2

EFFF
FOOO
F7FF
F800

EXTERNAL MEMORY
External memory can be addressed by selecting the Bus
Expansion Mode In the Bus Control Register. Address space
from 0200 through EFFF may be accessed for either RAM,
ROM, or VO purposes as the particular application requires It.
In addition, there are 32 bytes from 0020 through 003F which
may be used for VO expansion and 256 bytes from 0100 through
01 FF which may be external RAM.

NOT ACCESSIBLE
INTERNAL ROM (2048 BYTES)

FFFl
FFF2
FFF3

CPU LOGIC
Each CPU in the R65COO/21 is effectively a standard R6502 CPU
with 10 extra instructions utilizing 40 operation codes which are
unused in the R6502. Therefore, each CPU has an 8-bit accumulator, two 8-bit index registers (X and y), an 8-bit Stack Pointer
Register, an 8-bit Status Register, a 16-bit Program Counter,
independent interrupt circuitry, and an instruction register with
state counter. The internal buses, memory, instruction decoding
circuitry, and ALU are shared by the two CPU's on alternate
clock cycles.

NMIB VECTOR

FFF4
FFF5

RESB VECTOR

FFF6
FFF7

IRQBVECTOR

FFF8
FFF9

NOT USED

FFFA
FFFB

NMIA VECTOR

FFFC
FFFD

RESA VECTOR

FFFE
FFFF

IRQAVECTOR

Notes:
1. When bit 4 of the Bus Control Register (BCR) is a 0 (default value),
the 12B bytes of Internal RAM are redundantly mapped mto both
page zero and page one and are addressable as either OOBO-OOFF
or 0IBO-OIFF. When BCR bit 4 is a I, all of page one RAM
(256 bytes) is mapped externally (0100-01 FF) and the 12B bytes
of internal RAM are dedicated to page zero (OOBO-OOFF).
2 AcceSSible In bus expansion mode.

ACCUMULATORS
The accumulator in each CPU IS a general purpose 8-bit register
that stores the resu~s of most arithmetic and logiC operations.
Additionally, the accumulator contains one of the two data words
used in these operations.

Figure 3.

3-8

R65COO/21 Memory Map

Dual CMOS Microcomputer/Microprocessor

R65COO/21 • R65C29

INTERRUPT
FLAG
BITS

I'NTERRUPT
CONTROL
AND STATUS
REGISTER

•

'NTERRUPT

LATCH

ENABLE

J.
NMIA~

NMii~

'NTERRUPT
L.OGIC

I

I

CLEAR
INTERRUPT
FLAG

F

I

(-12B)

F
P

I
.I
I

INSTRUCTION

INSTRUCTION

OeCODE

REGISTERS

~
CLOCK
SELECT

II.

•I

~

I -,

I

I

I

INDEX

REGISTER

J

POWER

02

REGISTER

I

J

I
I

.1I Z6~~:~l

SELECT

I
I

UPPER LATCH

LOWER LATCH

UPPER COUNTER

L.OWER COUNTER

+----PF3

SNAPSHOT REG

I

REGISTER

COUNTERfTlMER B

I

l

.II C6'."T~Ol

LOWER LATCH

UPPER LATCH

LOWER COUNTER

UPPER COUNTER

J
I

I

PORT G

INPUT

I 14--1'
I f4----

PF4

I

I (Ho:.rG~6;ROl)

I

AND STATUS

I

REGISTER

I
I

I
I

DATA

DIRECTION
F

I

I

I

PORT F

I/O

I

I

ACCUMULATOR

I

STACK
POINTER

I
I

I
l

PCl
PROGRAM
COUNTER

DATA
DIRECTION

0

OATA

DIRE~TION

I
I

I
J

I
I
RAM

I
I

128>:8

BUS
CONTROL
REGISTER

DATA

DIRE~TION

l
Figure 4.

I

.I
I

I

I

PORT 0

I/O

I
I

PD(),PD7
(A().A7

AND

PORTC

110

I

I
I (HOS~C~:r~7

I
I

DATA
DIRECTION

I

u

I
I

R65COO/21 and R65C29 Block Diagram

3·9

PEo-PE7
(A8-A11

00-07)

I
A

I
I

OR

I

ROM
2048 X 8
(R65COO/21
ONLY)

PORT E
OUTPUT

PFO-PF7
(SPECIAL
FUNCTIONS)

A8-A15)

I

PCH

indicates dual registers - one
for CPU A and one for CPU B

I
J :='1'

AND STATUS

I
I

Note:~

r-

TIMER A
CLOCK

I

I

I

GEN

COUNTERfTlMER A

X

AlU

0'

CLOCK

I

y

INDEX
REGISTER

XTALO

J

l

PROCESSOR
STATUS

XTALI

CLOCK
OSCILLATOR

CONTROL.

I ;6~~:;L
I A~~G~~~~S

REGISTER

RES-----tI':

PRESCALER

PORT B

110

PORTA
I/O

I
J

PB().PB7

I
I

PA().PA7

BUS)

R65COO/21. R65C29

Dual CMOS Microcomputer/Microprocessor

STACK POINTERS

FFFC) and in CPU B (RESB at FFF4) when power is applied
to the R65COO/21. Each time a processor fetches an instruction
from memory, the lower (least significant) byte of its program
counter (PCl) is placed on the low-order eight bits of the address
bus and the higher (most significant) byte of the program counter
(PCH) is placed on the high-order eight bits of the address bus.
The counter is incremented each time an instruction or operand
is fetched from memory.

Each CPU in the R65COO/21 has its own independent a-bit Stack
Pointer Register located in RAM on page zer%ne and is pOinted
to by a Stack Pointer. Each Stack Register is automatically incremented and decremented under control of the appropriate CPU
to perform proper stack manipulations in response to user
instructions, an IRQ interrupt or an external NMI interrupt of the
appropriate CPU. The Stack Pointers must be initialized by the
user program.

The contents of the program counter are replaced with a new
value when a JMP, JSR, RTS, RTI, BRK, or any of the branch
instructions are executed. Also, the program counter value is
replaced when an external non-maskable interrupt NMIA or
NMIB, an internal interrupt request, an external interrupt request
via PF2 (see Port F description) or reset (RES) occurs.

These stacks allow simple implementation of multiple level
independent interrupts in each CPU, subroutine nesting, and
simplification of many types of data manipulation without
the programmer continually being aware of specific memory
addresses. The JSR, BRK, RTI, RTS, PHA, PlA, PHP, PlP,
PHX, PlX, PHY and PLY instructions all make use of the stack
and the appropriate CPU's Stack Pointer.

INSTRUCTION REGISTERS AND
INSTRUCTION DECODE

Each stack may be visualized as a deck of cards which may only
be accessed from the bottom of the deck. The value to be stored
is written on a card and then that card is placed on the bottom
of the deck (pushed onto the stack). When the data are to be
read, the bottom card is removed from the deck and the value
on it transferred to the appropriate register (pulled from the stack
to the specific register). Each time data are to be used as an
address, the value is stored in the addressed memory cell, and
the Stack Pointer is decremented by 1. When the data are read
(or "pulled") from the stack, the Stack Pointer is incremented
by 1 and the resulting value can be used to address the data.
The data are read from the addressed memory cell and then
transferred to the appropriate register in the CPU.

Instructions selected by the program counter are fetched from
ROM or RAM (or Port D if in Expanded Bus Mode) and gated
onto the internal data bus. These instructions are latched into
the proper instruction register and then decoded using common
decoding circuits for both CPU's. Timing, status bits, and interrupt controls are interpreted together with the instruction code
to generate control signals for the various registers in the
appropriate CPU.

INTERRUPT LOGIC
Each CPU has Its own logic which controls the sequencing of
three types of interrupts: RES, NMI, and IRQ. The same RESET
(RES) pin is used for both CPU's; consequently, reset occurs
on both CPU's at the same time. A different reset vector (RESA
and RESB) exists for each CPU to allow initialization of the separate and independent programs.

Each CPU must have an independent starting location for its
stack. It is the programmer's responsibility to see that the RAM
utilized for each CPU stack does not conflict. It is recommended
that the CPU requiring less depth in its stack be assigned the
OXFF location and the other stack be started a safe distance
below it. The two stacks are physically located either on page
zero (although addressed as page one) for single-chip operation, or externally on page one when extended addressing is
selected. (See Note 1 in Figure 3). The default areas for the
stacks are on page zero. In either case, both stacks are on the
same page.

Separate pins are used for the two processors' non-maskable
interrupts (NMIA and NMIB). Each processor has its own NMI
vector; CPU A uses NMIA Vector at FFFA and CPU Buses
NMIB Vector at FFF2.
Three different types of external interrupt conditions can be
detected by connecting the external signal to one of three Port
F input pins. A positive-going edge, a negative-going edge, and
an external interrupt request (IRQ), i.e., a low level, can be
detected on PFO, PF1 and PF2, respectively. Internally, IRQ
conditions can be generated by time-out of either of the two 16bit counter/timers, upon interprocessor-communication request
by the other CPU, or by the Host Interface Port.

ARITHMETIC AND LOGIC UNIT (ALU)
All arithmetic and logic operations for both CPU's take place in
a shared AlU. Incrementing and decrementing of the index registers and memory also take place here. The AlU stores data
for only one cycle. Consequently, data placed on the inputs at
the beginning of a cycle are processed and gated to one of the
registers, or to memory, during the next cycle.

In each case, the interrupt condition is reported as an interrupt
flag in a controVstatus register associated with the functional
area. Each CPU can either enable or disable IRQ generation by
setting or resetting a corresponding interrupt enable bit in the
same or associated controVstatus register.

Each bit of the AlU has two inputs. These inputs may be tied
to various internal buses or to a logic zero; the AlU then generates the function (AND, OR, SUM, etc.) using the data on the
two inputs.

PROGRAM COUNTERS

Furthermore, each CPU can control whether or not its proceSSing is interrupted when an interrupt request (IRQ) is generated. Each CPU has its own Processor Status Register (PSRA
and PSRB) with the capability of disabling IRQ interrupts when
its own "I flag" bit is a 1.

The 16-bit program counters for each CPU provide addresses
that step each processor through sequential instructions in a
stored program. The program counter for each CPU is initially
set to the value stored as the reset vector in CPU A (RESA at

3-10

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor
instruction branches if the bit tested is a 1. If the bit tested is not
set to a 1, the next sequential instruction is executed. This
instruction requires five cycles if the branch is not executed, six
cycles if the branch executes to the same page, or seven cycles
if it branches to a different page.

NEW AND MODIFIED INSTRUCTIONS
In addition to the standard R6502 instruction set, ten new
instructions have been added and minor timing and other
changes have been made to a few other instructions. All of these
additions and changes are discussed in this section. Refer to
the Instruction Set Op Code Matrix for the operation codes and
addressing modes of all instructions. The times indicated for
each instruction are given in terms of CPU clock-times.

BRANCH ON BIT RESET RELATIVE
(BBR m, ADDRESS, DESTINATION)
This instruction is similar to the BBS instruction except that the
branch takes place If the bit tested IS a O.

UNSIGNED MULTIPLY (MUL)
The 10 clock-time hardware multiply instruction multiplies the 8bit contents of the Y register by the 8-bit contents of the A register to give a 16-bit product. At the completion of the multiply
operation, the most significant half of the product resides in the
A register and the least significant half in the Y register. This
operation uses unsigned numbers only. This instruction uses the
implied addressing mode and, consequently, requires one byte
for the op code.

INDEX REGISTER STACK OPERATIONS
(PHX, PLX, PHY, AND PLY)
These instructions are similar to the PHA and PLA instructions
In the conventional R6502 except that they push or pull the X
or Y registers to and from the stack, respectively. The push
instructions require three instruction cycles and the pull instructions reqUire four cycles.

SET MEMORY BIT (SMB m, ADDRESS.)

UNCONDITIONAL BRANCH (BRA)

This instruction uses zero page addressing only and requires
five cycle times. It sets the designated bit in the addressed
memory cell or I/O port to a 1. The first byte of the two-byte
instruction identifies the operation and the bit to be set while the
second byte designates the address of the word in which the bit
is to be set. Eight op codes are used for the eight bit locations
in a by1e.

This unconditional branch is a branch always Instruction. It operates similar to the conditional branches of the R6502 except that
the relative branch always occurs. It executes In three cycles if
the branch is to the same page or four cycles if it is not. Two bytes
are required, one for the op code and the other for the relative
address.

INSTRUCTION DIFFERENCES FROM R6502
RESET MEMORY BIT (RMB

m, ADDRESS.)

DeCimal add and decimal subtract instructions on the R65COO/
21 require one cycle time longer than their binary equivalents.
The add and subtract times are the same for both decimal and
binary operation on the R6502.

This instruction operates in the same way as the 5MB instruction except that the bit is set to O.

BRANCH ON BIT SET RELATIVE
(BBS m, ADDRESS, DESTINATION)

The decimal mode flag (D) In the processor status registers
default to binary (D=O) operation when the R65COO/21 is RESET,
whereas thiS bit is umnillalized on the R6502.

This instruction tests one of eight bits designated by a three-bit
immediate field within the first byte of the Instruction. The second
byte designates the address of the byte to be tested within the
zero page address range (memory or I/O ports). The third byte
of the instruction specifies the 8-blt relative address to which the

The indirect jump instruction increments the page address when
the indirect pOinter crosses a page boundary, whereas on the
R6502 it does not.

3-11

R65COO/21. R65C29

Dual CMOS Microcomputer/Microprocessor

PROCESSOR STATUS REGISTERS

DECIMAL MODE BIT (D)

Each CPU has its own 8-bit Processor Status Register. Each
register contains seven status flags. Some of these flags
are controlled by the user program; others may be controlled
both by the user's program and the appropriate CPU. The
R65COO/21 instruction set contains a number of conditional
branch instructions which are designed to allow testing of these
flags.

The decimal mode bit (D) controls the arithmetic mode of its
CPU. When this bit is set to a 1, the adder operates as a decimal
adder for the Add with Carry (ADC) and the Subtract With Carry
(SBC) instructions. These instructions, in the decimal mode,
require one additional CPU cycle time compared with binary
mode or the decimal mode in the conventional R6500. (In the
conventional R6500, the decimal and binary arithmetic operations are the same speed.) When the bit is a 0, the arithmetic
is performed in straight binary. The decimal mode is controlled
only by the programmer for each of the CPU's. The Set Decimal
Mode (SED) instruction causes decimal arithmetic to be performed and the Clear Decimal Mode (CLD) instruction causes
binary arithmetic to be performed by that CPU. The PLP and
RTI instructions also affect the decimal mode bit.

CARRY BIT (C)
The carry bit (C) can be considered the ninth bit of an arithmetic
operation. It is set to a 1 if a carry from the eighth bit has
occurred, or it is cleared to 0 if no carry has occurred, as a result
of arithmetic or shift operations.
The carry bit may be set or cleared under program control by
use of the Set Carry (SEC) or Clear Carry (CLC) instructions,
respectively. Other operations which affect the carry bit are
ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, ROR, RTI, and
SBC.

The D bit for each CPU is automatically set to the zero state
(binary mode) when the R65COO/21 is reset by RES.

BREAK BIT (B)
The break bit (B) determines the type of condition which caused
the IRQ service routine to be entered. If the IRQ service routine
was entered because a BRK instruction was executed by its
CPU, the B bit is set to a 1. If the service routine was entered
because of an IRQ signal being generated, the B IS set to a O.
There are no instructions which directly set or clear thiS bit.

ZERO BIT (Z)
The zero bit (Z) is set to a 1 by the CPU during any data movements, or calculations, which sets all eight bits of the result to
zero for that CPU. This bit is cleared to a 0 when all eight bits
of a data movement, or calculation, operations are not all zero
for that CPU. The R6500 instruction set contains no instruction
to specifically set or clear the Z flag bit. The Z flag bit is, however, affected by the following instructions: ADC, AND, ASL,
BIT, CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY,
LDA, LDX, LSR, ORA, PLA, PLP, PLX, PLY, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TVA.

OVE RFLOW BIT (V)
The overflow bit (V) indicates that the result of a signed binary
addition or subtraction operation is a value which cannot be contained in seven bits (outSide the range of -128 to +127). This
indicator only has meaning when signed arithmetic IS performed. In this case, the arithmetic operations are being performed on the sign and seven magnitude bits for one byte, or
the most significant byte of a longer signed number. When the
ADC or SBC instruction is executed, the overflow bit is set to
a 1 if the polarity of the sign bit is changed because the result
exceeds +127 or -128 in absolute magnitude. Otherwise, the
V bit is cleared to a O. The V bit may be cleared by the programmer by executing a Clear Overflow (CLV) instruction in the
appropriate CPU.

INTERRUPT DISABLE BIT (I)
The interrupt disable bit (I) controls the servicing of an interrupt
request (IRQ). If the I bit is set to a 0 in the Processor Status
Register of one, or both, of the CPU's, the IRQ signal will be
serviced by that particular CPU. If the bit is set to a 1 for one
or both of the CPU's, the IRQ Signal will be ignored by that CPU.
Each CPU will set its interrupt disable bit to a 1 if a RES, an
IRQ, or its non-maskable interrupt (NMI) signal is detected.
Interrupting one processor does not affect the other one unless
It IS programmed to respond to the same Interrupt.

The overflow bit is also affected by the BIT instruction. The BIT
instruction samples specific bits in memory or I/O interrupt
status words. Most of the I/O devices used in the R6500 family
and most of the interrupt flags in the R65COO/21 have interrupt
flags in the upper two bits of the register. The BIT command
copies these two most significant bits of the addressed word into
the N and V flags. The V flag is set to the same state as bit 6
of the addressed words and the N flag copies bit 7.

The I bit is cleared for each CPU when that CPU executes a
Clear Interrupt Disable (CLI) instruction and is set under software control by a Set Interrupt Disable (SEI) instruction. This bit
IS also set by the Break (BRK) instruction. The Return From
Interrupt (RTI) and Pull Processor Status (PLP) instructions also
affect the I bit by setting it to the value which was stored on the
stack.

The instructions which affect the
RTI and SBC.

3-12

V flag are ADC,

BIT, CLV, PLP,

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor

NEGATIVE BIT (N)
The negative bit (N) indicates that the sign bit (bit 7) in the
resulting value of a data movement or arithmetic operation is
a 1. If the value represents a signed number, the most significant bit being a 1 indicates a negative number. If the sign bit is
a 0, the resu~ is interpreted as a positive value. The BIT instruction copies the most significant bit of the addressed memory cell
or I/O register Into the N flag bit.
There are no instructions that set or clear the N bit directly since
the N bit represents only the status of a result. The instructions
which produce a resu It that affects the state of the N bit are
AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EaR, INC,
INX, INY, LDA, LOX, LDY, LSR, ORA, PLA, PLP, PLX, PLY,
ROL, ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TYA.

Processor Status Registers (PSRA and PSRB)
7

6

5

4

3

2

1

a

NEG
(N)

OVFL
(V)

NOT
USED

BRK
(B)

DEC
(D)

IRQ
ENBL
(I)

ZERO
(Z)

CARRY
(C)

Bit 7
-1

a
~
1

a

Negative (N)'
Negative Value
Positive Value
Overflow (0)'
Overflow Set
Overflow Clear

BitS

Not Used (Don't care value)

Bit 4
-1

Break Command (B)1
Break Command
Non-break Command

a
Bit 3
-1

a

Decimal Mode (OJ'
Decimal Mode
Binary Mode

Bit 2
1

Interrupt Enable (1)2
IRQ Interrupt Disable
IRQ Interrupt Enable

Bit 1
-1-

Zero (Z)1
Zero Result
Non-Zero Resufi

a
a

Bit a
-1-

a

Carry (C)'
Carry Set
Carry Clear

Notes:
1. Not Initialized by RES.
2. Set logic 1 by RES.
3. Cleared to logiC a by RES
4. There are two Processor Status Registers, one for each CPU.

3-13

Dual CMOS Microcomputer/Microprocessor

R65COO/21 • R65C29

INPUT/OUTPUT AND CONTROL/STATUS REGISTERS
REGISTER ADDRESSES
Seven control/status registers control and monitor the basic
operation of the R65COO/21. The registers and their primary
functions are as follows:

Table 2 shows the input/output, control/status and timer/counter
registers which are addressed on page zero from locations 00
through 1D. Some of the registers combine other functions when
they are read or written. The table lists both the primary and
secondary types of functions. Table 3 summarizes the register
formats.

BCR

Bus Control Register-defines expansion bus
modes
Host Control and Status Register-defines host
HCSR
bus and interrupts
Interrupt Control and Status Register-enables
ICSR
and reports interrupt conditions
Clear Interrupt Flags Register
CIFR
Power Control Register--selects low power
PCR
mode
TACSR Timer A Control and Status Register-controls
and monitors Timer A operation
TBCSR Timer B Control and Status Register-controls
and monitors Timer B operation

All controVstatus registers and data direction registers are cleared
to zero by a RES. Thus, the zero state of each bit defines the
default operating modes. Each register is associated with a
functional area in the microcomputer, e.g., parallel input/output,
timer/counter, bus control, etc. The detail operation of each register is defined in the appropriate sections.
Thirteen registers are used for input/output functions and nine
registers used for timer/counter functions. The use of these registers is discussed in later sections.
Table 2.
Address
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
1,7
18
19

110, Control/Status and Timer Registers
Write

Read
PA Data
PB Data
PC Data, Cl-+IBF3
PC Data, Cl-+IBF3
PD Data'

PF Data
PG Data

-

-

-

BCR
HCSR
ICSR

-

PCR
TACSR
LCA, UCA.... SLA
SLA
SLA, Cl-+UFA2

lA
lB
lC
lD

TBCSR
LCB
UCB
UCB, Cl-+UFB2

IE
IF

-

-

Register Names/Notes

PA Data
PB Data
PC Data. 1.... 0BE, Cl-+RS03
PC Data, 1.... 0BE, I .... RS03
PD Data'
PE Data'
PF Data

PA
PB
PC
PC
PD

Direction
Direction
Direction
Direction
Direction'

PF Direction
-

Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port

A Data I/O
B Data I/O
C Data I/O
C Data I/O
D Data I/O
E Data Output Only
F Data I/O
G Data Input Only
A Di rection
B Direction
C Direction
C Di rection
D Direction

Port F Direction

BCR
HCSR
ICSR
CIFR
IPCIR
PCR
TACSR
LLA
ULA
ULA, ULA.... UCA,
LLA.... LCA, Cl-+UFA 2
TBCSR
LLB
ULB
ULB, ULB-->UCB, LLB-->LCB, 0.... UFB2

Bus Control Register
Host Control and Status Register
Interrupt Control and Status Register
Clear Interrupt Flags Register
Inter-Processor Communication Interrupt Register
Power Control Register
Timer A Control and Status Register
Timer A Lower Counter (LCA)/Lower Latch (LLA)
Timer A Snapshot Latch (SLA)/Upper Latch (ULA)
Timer A Snapshot Latch (SLA)/Upper Latch,
Download and Start Timer
Timer B Control and Status Register
Timer B Lower Counter (LCB)/Lower Latch (LLB)
Timer B Upper Counter (UCB)/Upper Latch (ULB)
Timer B Upper Counter (UCB)/Upper Latch (ULB),
Download and Start Timer

-

Notes:
1. Addressed externally when in expanded bus mode.
2. Counter/Timer underflow flags:
UFA = Timer A Underflow Flag bit in TACSR
UFB = Timer B Underflow Flag bit in TBCSR

3. R65COO/21 to/from Host data transfer bits in HCSR:
IBF = Input Buffer Full flag bit
OBE = Output Buffer Empty flag bit
RSI = Register Select Input bit
RSO = Register Select Output bit
4. = Not used-indeterminate data when read

3-14

Dual CMOS Microcomputer/Microprocessor

R65COO/21 • R65C29
Table 3.

Control/Status Registers Formats Summary

Address
(Hex)

BII Number
7

10

CPUA
ACTIVE

11

O/P
BUFF
FULL
INT
FLAG
(OBF)

12

13

IPCA
INT
FLAG
IPCB
INT
FLAG
CLR
IPeA
INT
FLAG
CLR
IPCB
INT
FLAG

6

5

4
PAGE
ONE
EXT

NOT USED

VP
BUFF
FULL
INT
FLAG
(IBF)

VO
REG
SEL
(RSI)
(RSO)

NOT
USED

PF2
LOW
INT
FLAG

PF1
NEG
EDGE
INT
FLAG

PFO
POS
EDGE
INT
FLAG

NOT
USED

CLR
PF1
NEG
INT
FLAG

CLR
PFO
POS
INT
FLAG

14

2

3

1
BUS
EXTENSION
MODE

PORTA
NIBBLE
MODE
VOA
INT
ENBL

0

HOST
INT
ENBL

HOST
BUS
ENBL

HOST
BUS
TYPE

IPCA
INT
ENBL

PF2A
INT
ENBL

PF1A
INT
ENBL

PFOA
INT
ENBL

IPCB
INT
ENBL

IPCB
INT
ENBL

PF1B
INT
ENBL

PFOB
INT
ENBL

VOB
INT
ENBL

NOT USED

16

TMRA
UNFL
FLAG
(UFA)

PF3
LEVEL
IND

NOT
USED

TMRA
INT
ENBL

1A

TMR B
UNFL
FLAG
(UFB)

PF4
LEVEL
IND

NOT
USED

TMRB
INT
ENBL

TMRA
CLK
PRESC
SEL

LOW
PWR
CPUA
(LPA)

TIMER A
MODE
SELECT

NOT USED

INTERRUPT
CONTROL AND
STATUS
REGISTER
(ICSR)

INTERPROCESSOR
COMMUNICATION
INTERRUPT
REGISTER (IPCIR)
LOW
PWR
CPU B
(LPB)

NOT USED

HOST
CONTROL AND
STATUS
REGISTER
(HCSR)

CLEAR
INTERRUPT
FLAGS
REGISTER
(CIFR)

WRITE ONLY REGISTER-NO SPECIFIC BIT (IPCIR)

15

BUS
CONTROL
REGISTER
(BCR)

TIMER B
MODE
SELECT

POWER
CONTROL
REGISTER
(PCR)
TIMER A
CONTROL AND
STATUS
REGISTER
(TACSR)
TIMER B
CONTROL AND
STATUS
REGISTER
(TBCSR)

Note: All control and status registers are cleared to zero by RES

INTERRUPT CONTROL AND STATUS
Unlike other R6500 family devices, the R65COO/21 does not
concentrate the interrupt flags into a Single register. The
R65COO/21, in general, places the interrupt flags in registers
which also have to do with the control of the particular function
which can cause the interrupt.

TACSR
TBCSR

Portions of each of these registers relating to interrupt enables
are duplicated for each of the two CPU's. However, only one
memory address has been allocated so that each CPU uses the
same address to select its own interrupt enables. The specific
details of the usage of the interrupt control bits are discussed
in the corresponding functional area.

Interrupt enable control is located in the following registers:
HCSR
ICSR

Timer A Control and Status Register
Timer B Control and Status Register

Host Control and Status Register
Interrupt Control and Status Register
3-15

R65COO/21. R65C29

Dual CMOS Microcomputer/Microprocessor

CLOCK CIRCUITS
CLOCK OSCILLATOR

POWER CONTROL REGISTER (PCR)

The internal clock oscillator generates the system clock (0'2)
which clocks all R65COO/21 operations. The system clock frequency ranges from 10KHz to 4 MHz (the upper limit determined by the R65COO/21 part number) which is one-half the
external crystal (or master clock) frequency. Each CPU in turn
operates at one-half the system clock frequency (alternate
cycles). All operations to memory or 1/0 take place at the system
clock frequency. Since each CPU shares the common segments
of the system on alternate system clock cycles, all internal
operations occur at the system clock rate but, for CPU timing
purposes, a CPU cycle rate of half the system rate is used. Thus
with a 4 MHz crystal frequency, the system clock rate is 2 MHz
and each CPU operates at an effective 1 MHz rate. Every two
system clock periods sees one cycle devoted to CPU A and one
cycle devoted to CPU B.

Two bits in the Power Control Register (PCR) determine operation of the clock prescaler. Each CPU can set its own power
control bit and read both of them. When both power control bits
are a 1, the system switches to the low power operation at a
clock rate of 0'2/128 (02PS). The system reverts to normal
power and speed when either power control bit is a 0 or when
an enabled interrupt occurs. In the latter case, the system continues to operate at the low rate until the current instruction IS
completed, then it switches to the normal rate.

NOTE

An enabled interrupt automatically clears the PCR bit for
the affected CPU. It must be set again by software to
resume low power mode.

The \ll2 clock is normally routed externally to clock external
memory operations in the extended bus mode. A mask option
allows the \ll2 clock to be configured as an input so the
R65COO/21 can operate in a slaved clock mode. In this case,
the crystal input (XTALI) is grounded and crystal output (XTALO)
is left open as shown in Figure 5.

Power Control Register (PCR)
7

I

6

I

5

I

4

I

3

T

NOT USED

LOW POWER OPERATION
The divide-by-128 clock prescaler operates in one of three ways
(see Figure 6). One is the prescaler switched completely out
which gives a system clock rate (02) at one-half of the crystal
frequency. Another way is to select the low power operation for
both CPUs which switches in the clock prescaler. The clock
prescaler divides the system clock frequency by 128 to generate
the prescaled system clock rate (0'2PS). This reduces the device
power requirements and also reduces the counting rate of both
counter/timers by a factor of 128. The third operating mode for
the prescaler is to use it for prescaling Timer A only. This mode is
discussed under the CounterlTimer Operation.

2

1

LOW
PWR
CPU· B
(LPB)

Bits 7-2

Not Used (Don't care)

Bit 1
1

Low Power Mode Select for CPU B (LPB)
Low power mode requested by CPU B
Normal power mode requested by CPU B

Bit 0
1

Low Power Mode Select for CPU A (LPA)
Low power mode requested by CPU A
Normal power mode requested by CPU A

o

o

Notes'
1. Both CPU's can read both bits.
2. Each CPU can only write its power control bit.
3. Both bits must be set to enable low power mode.

3-16

0
LOW
PWR
CPUA
(LPA)

R65COO/21 • R65C29

XTLI

9

XTLO

Dual CMOS Microcomputer/Microprocessor

OUTPUT CLOCK

r-

INPUT CLOCK

XTALO

p-

r---l

L...
MASTER
MICROCOMPUTER

r-

I

--,

I

r

IL ____ J,
I

---'

~

82

I

L.

SLAVE
MICROCOMPUTER

L...-

INVERTER USED WHEN SLAVE
IS TO OPERATE OUT OF PHASE
WITH MASTER

Figure 5.

'h CRYSTAL/MASTER CLOCK ..;:CD::;1- - -.......-i

n
XTALI

'2

Vss

Master/Slave Cock Connection

PRESCALER

(+ 128)

--

LOWFREQ
SELECTION

-

CLK
GEN

_ SYSTEM CLOCK
(8'2 OR '2PS)

r
POWER
CONTROL
REGISTER

Notes.
1. Crystal or Master clock frequency is divided by two internally.
2 System clock is 02 or 02PS (02 - 128) if low frequency operation for both CPU's is selected in the Power Control Register.
3. When a deVice IS strapped for slave clock mode, the Input fl/2 by-passes the prescaler (I.e, PCR brts Will have no affect on the Internal 82 clock
rate of the slave processor.

Figure 6.

System Clock Operation

3-17

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor

PARALLEL INPUT/OUTPUT PORTS
assigned to write to both halves, write to neither half (only
read-the other CPU writes to the whole register), write to top
half, or write to bottom half. When a mode has been selected
for writing to only one-half of the port, the other half is unaffected.

The R65COO/21 parallel input/output interface consists of five
8-bit, bidirection input/output ports, one 8-bit output only port,
and one 4-bit input only port.

BIDIRECTIONAL PORTS A, B, C, D AND F

ALTERNATIVE MODES OF OPERATION

The five 8-bit bidirectional ports (Ports A, B, C, D and F) each
have an associated data direction register which configures
individual data ports for either input or output. Port E is output
only and port G is input only, therefore, no data direction registers are required for these two ports.

Bidirectional Ports C, D, and F all have alternative modes of
operation which may be selected in lieu of the bidirectional port
capabilities.
Port C is a data bus for a host computer when the R65COO/21
is being used as a programmable peripheral device. This is discussed in more detail under Bus Extension and Host Interface.

OUTPUT MODE
If the data direction register for a particular bit position in a
bidirectional port is a 1, that bit is defined as an output pin. The
Information written into each bit position of the data word is
loaded into a latch. The information will remain in that latch until
new data is transmitted to the data word or the power is shut
off. The output latches are individually connected to output
drivers for each bit position for which a corresponding bit in the
data direction register is a 1. The output drivers are doubleended, push:pull type. The drivers force the output pins high
(;;.2.4V) if the output data bit is a 1, or low (;;'O.4V) if the output
data bit is a O. The output drivers are TTL compatible.

Port D is a multiplexed data bus (DO through D7) and address
bus (AO through A7) when the R65COO/21 is used as a microcomputer with external memory and I/O devices. This is also
detailed under Bus Extension and Host Interface.
Port F also has the capability of operating in conjunction with
other segments of the R65COO/21 architecture as described
below.

PORT F CONTROL AND STATUS
The Interrupt Control and Status Register (ICSR) and the Clear
Interrupt Flags Register (CIFR) control and monitor the operation of the Port F external interrupts (bits 2, 1, 0) as well as interprocessor communication interrupts.

INPlIT MODE
If the data direction register for a particular bit position in a
bidirectional port is 0, that bit position is defined as an input pin.
When the input/output port is read via an LDA, LDX, LDY, ADC,
SBC, ORA, AND, EOR, or a BIT instruction, all of the information
on that port's pins are read into the corresponding register and
processed as directed by the instruction. Since the input signal
lines are at a "float" state, the logic level on them will be read
as either a 1 or a 0 for that pin poSition. A low (;;'0.8V) input
causes a logic 0 to be read and a high (;;.21.0V) input causes a
logic 1 to be read. The output values can also be read (if the
direction bit = 1) since the outputs are also on the pins. The input
receivers are TTL compatible, are not latched, and are sampled
near the end of each clock cycle ~2 and gated onto the internal
bus when selected.

When the PFO edge-sensitive circuit detects a positive transition, bit 4 of the ICSR is set to a 1. An internal interrupt request
(IRQ) is generated to a CPU whenever this bit is set and the
corresponding PFO Interrupt Enable Flag (ICSR bit 0) is set to
a 1 for that CPU. Similarly, a negative going transition on PF1
sets the edge detect flag in ICR bit 5. ICSR bit 1 is the corresponding PF1 Interrupt Enable bit. As in all cases of the interrupt
enable bits, each CPU has its own set, addressed at the same
location, but held separately.
Port F signal PF2 has an external interrupt request (IRQ) capability. When this signal goes low, bit 6 of the Interrupt Control
and Status Register is set and remains set as long as the signal
is low. If the corresponding PF2 Interrupt Enable bit (bit 2) in its
segment of the Interrupt Control and Status Register is a 1 while
the PF2 Low Interrupt bit (bit 6) is a 1, an interrupt request is
generated.

PORT A NIBBLE ADDRESSING
Whenever a port is shared as an output, care must be exercised
that one CPU does not destroy the other CPU's output data. In
general, this can be avoided by allocating complete output ports
to each CPU so that there is no possibility of conflict. However,
there may be some situations where at least one port must be
shared for outputs to get the proper mix for the required application. Port A is slightly different from the other bidirectional
ports to allow port A to be safely shared as an output port by
both CPU's.

Each CPU may thus control the external interrupt independently
of the internal interrupts. If the I flag in the Processor Status
Register of a particular CPU is a 1, no IRQ's will be honored.
If the I flag is a 0 and that CPU's interrupt enable in bit 2 of the
Interrupt Control and Status Register is a 0, only internal interrupts will interrupt that CPU. If bit 2 is a 1, any IRQ will be
honored.

Port A is divided into two 4-bit "nibble ports". Each half (nibble)
of Port A may be Independently addressed by each CPU as
defined by two bits in the Bus Control Register (BCR2 and
BCR3) as described in Bus Extension and Host Interface section. Depending upon the control bits, either CPU may be

The Port F signals PF3 and PF4 can be used as external interfaces for Counter/Timers A and B, respectively (refer to the
Counter/Timers description). Finally, PF7 can be used as an
active-low interrupt to a host processor. The operation of the
R65COO/21 with a host processor is discussed under Bus Extension mode.
3-18

Dual CMOS Microcomputer/Microprocessor

R65COO/21 • R65C29

CLEAR INTERRUPT FLAGS REGISTER (CIFR)

The Inter-Processor Communication Interrupt (IPCA and IPCB)
bit in the ICSR allows each CPU to interrupt the other CPU if
all of the other normal IRQ conditions are correct. CPU A sets
the IPCB Interrupt Flag in CPU B's Interrupt Control and Status
Register and CPU B sets the IPCA Interrupt Flag in CPU A by
any write to location 0014, the Inter-Processor communications
Interrupt Register. This IS not an actual register, but writing any
value here sets the other CPU IPCI flag. This inter-processor
communications is illustrated in Figure 7.

The Clear Interrupt Flags Register (CIFR) is similar to the ICSR
in that only one address is used but the bit pattern operates only
on the status bits for its own processor. Thus only CPU A may
clear IPCA but either may clear the edge detection flag bits. Bit
6 will only be cleared when the signal on PF2 goes high.
Actually, the Clear Interrupt Flags Register is not a register at
all, but addressing a bit pattern to this location performs the
function. Any bit to which a zero is written will clear the corresponding interrupt flag. A read of this word returns logic one's
so that the new Reset Memory Bit instructions may be used to
clear these flags.

Interrupt Control And Status Register (ICSR)
7

6

IPCA
INT
FLAG

IPCi3
INT
FLAG

Bit 7

o
~
1

o
Bit 5
-1-

o
Bit 4
-1

o
Bit 3
1

o
Bit 2
1

o
Bit 1

-1

o
Bit 0
1

o

PF2
LOW
INT
FLAG

4

5

PF1
NEG
EDGE
INT
FLAG

PFO
POS
EDGE
INT
FLAG

3

2

1

0

IPCA
INT
ENBL

PF2A
INT
ENBL

PF1A
INT
ENBL

PFOA
INT
ENBL

IPCB
INT
ENBL

PF2B
INT
ENBL

PF1B
INT
ENBL

PFOB
INT
ENBL

Clear Interrupt Flags Register (CIFR)
7

6

CLR
IPCA
INT
FLAG

NOT
I - - USED
CLR
IPCB
INT
FLAG

Inter-Processor Communication (IPC) Interrupt Flag
(A or B)
An inter-processor Interrupt IS requested by the other
CPU
No internal Interrupt is requested
PF2 Low Interrupt Flag (A and B)
PF2 is low
PF2 is high

Bit 7
-1-

o

PF1 Negative Edge Detect Interrupt Flag
A positive-to-negative transition on PF1 occurred
No posltive-to-negative transition on PF1 occurred
Bit 5
-1

o

Inter-Processor Communication Interrupt Enable
(A or B)
Enables inter-processor communication interrupt (bit 7)
Disables inter-processor communication interrupt (bit 7)

Bit 4
1

o

PF1 Interrupt Enable (A or B)
Enables PF1 interrupt (bit 5)
Disables PF1 interrupt (bit 5)

FLAG

FLAG

SET
FLAG
WRITE
TO IPCIR
(0014)

IPeA
INT
FLAG

FLAG
WRITE
TO IPCIR
(0014)

1

I

0

NOT USED

Clear Inter-Processing Communication Interrupt Flag
Has no effect on the IPC Flag
Clears the IPC Interrupt Flag (specific CPU, A or B)

Clear PF1 Interrupt Flag
Has no effect on the PF1 Interrupt Flag
Clears the PFI Interrupt Flag (either CPU)
Clear PFO Interrupt Flag
Has no effect on the PFO Interrupt Flag
Clears the PFO Interrupt Flag (either CPU)

Port E is a dual function port WhiCh, In addition to being an
output port, can also serve as address bits A 15 through A8
when the R65COO/21 is addressing external mernory and I/O
devices This is diswsse<:l in mf)re rlptC'iI "r<:ler Bus Extension
and Host Interface.

IPeA
INT
~
IPCB

INT

P.Et'.O

FLAG

CPU B

ICSR
BIT 7
(0012)

FLAG

CLR
IPCB

INT

FLAG

INPUT ONLY PORT G

CLEAR

FLAG
WRllETO
CIFR

The input characteristics of the 4-bit Port G are the same as a
bidirectional port in an input mode. The difference is that only
four bits are input into the least significant bits of the data register and the most slgmficant bits are loaded as zeros.

BIT 7
(0013)

Figure 7.

I

OUTPUT ONLY PORT E

CLR

WRITE
TO CIFR
BIT 7
(0013)

2

SET

READ

CLEAR

CLR
PFO
POS
INT
FLAG

I

The output characteristics of Port E are identical to that of the
bidirectional ports. The main difference is that there is no data
direction register and also no capability of reading the information being output. Attempting to read Port E loads indeterminate data onto the internal bus.

PFO Interrupt Enable (A or B)
Enables PFO Interrupt (bit 4)
Disables PFO interrupt (bit 4)

CPU A

CLR
PFI
NEG
INT
FLAG

3

Bit 3-0 Not Used

PF2 Interrupt Enable (A or B)
Enables PF2 interrupt (bit 6)
Disables PF2 interrupt (bit 6)

(0012)

4

Not Used

PFO Positive Edge Detect Interrupt Flag
A positive-to-negative transition on PFO occurred
No positive-to-negative transition on PFO occurred

ICSR
81T7

5

Inter Processor Communication
3-19

Dual CMOS Microcomputer/Microprocessor

R65COO/21 • R65C29

COUNTE R/TIMERS
Counter (LCA and LCB, where A and B refer to Counter/Timer
A and B) and Upper Counter (UCA and UCB). Both counter/
timers also have a 16-bit latch section consisting of two 8-bit
segments: Lower Latch (LLA and LLB) and Upper Latch (ULA
and ULB). In addition, only Timer A has an 8-bit Snapshot Latch
(SLA) register.

There are two separate 16-bit counter/timer systems in the
R65COO/21: Counter/Timer A and Counter/Timer B. The block
diagram of the counter/timers (also referred to as the timers, the
counters, Timer A, or Timer B) is shown in Figure 8. Timer A
has eight operating modes and five registers while Timer B has
four operating modes and four registers. Both counter/timers
have a 16-bit counter comprised of two 8-bit segments: Lower

TAC3

TIMER A

+ 128
~--------+---r-r-~

PRESCALER
PF3

DATA BUS

ULB

LLB

UCB

LCB

TIMER B

Figure 8. Counter/Timer Block Diagram
3-20

PF4/1l'2

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor
Timer A Mode Control

Data are written to the latches which act as holding registers for
loading or reloading the initial counter/timer values upon mode
initiation or counter/timer restart.

The operation of Timer A is controlled and monttored by the
Timer A Control and Status Register (TACRS).

Both timers count down from the pre-set latch value and set an
appropriate underflow flag when the counter counts through
zero. The counter actually never counts below zero. At the time
the counter would go negative, the contents of the latches
replace the count value with no time delay.

Bits 0-2 select the Timer A mode of operation.
Bit 3, when set to a 1, causes the clock prescaler to be swttched
into the circuit so that the timer may count longer intervals in
modes which allow it.

Each counter/timer has three addresses for accessing the five
(Counter/Timer A) or four (Counter/Timer B) 8-bit registers in
its system. Consequently, the R/W line also aids in addreSSing
the registers. Reading or writing to specific registers may also
have other effects such as clearing an interrupt flag or transferring latch data to the counter. Consu~ the input/output and
control register memory map in Table 2 for the effects of reading
or writing to specific registers in the two counter/timer systems.

Timer A Interrupt Enable, TACSR bit 4, if set to a 1 by a CPU,
enables generation of an internal IRQ to that CPU when the UFA
flag is set.
Bit 6 copies bit 3 of Port F (PF3).
Bit 7 is the UFA bit which indicates that Timer A has counted
down through zero. This may be detected by reading the bit or
may be used to cause an IRQ interrupt if bit 4 of the TACSR is
sello a 1. The UFA flag is reset to a 0 by reading SLA or writing
ULA at address 0019.

Each counter/timer has operallng modes which are clocked
either at the system clock rate (02) or an external event clock
rate. In addition, Timer A can operate with a prescaled %2/128
clock rate.

Timer A Control And Status Register (TACSR)
7

COUNTER/TIMER A (TA)

6

5

TMRA
PF3
UNFl
NOT
lEVEL
FLAG
USED
IND
(UFA)

Counter/Timer A, with its four additional modes and Snapshot
Latch, is generally more flexible than Counter/Timer B.
The Snapshot Latch (SLA) solves a problem which sometimes
occurs when a timer IS read. The problem is that between the
time when the low byte of the 16-bit counter is read and the time
when the high byte is read it is possible for the high byte to have
been decremented. The resu~ing 16-bit value would, in this
case be incorrect. In many modes of timer, the values are not
actually read but the zero count transition is Important. These
types of applications do not require the use of the Snapshot
Latch register. If the timer count value is to be used directly from
a running timer, however, the Timer A Snapshot Latch should
be used.

Bit 7
1

o
Bit 6
1

o

3

1

I

0

TIMER A
MODE
SELECT

Port F Bit 3 (PF3) Level
PF3 High
PF3 low
Not Used (Don't care)
Timer A Interrupt Enable
Enable Timer A Interrupt
Disable Timer A Interrupt

o

I

Timer A Underflow Flag (UFA)
Underflow condition occurred
No underflow

Bit 4
-1

Bit 3
-1

2

TMRA
TMRA
ClK
INT
PRESC
ENBl
SEl

Bit 5

o

Timer A overcomes the problem stated above by sampling the
value of the upper counter byte into the Snapshot Latch every
time the lower counter by1e is read. The value of the Upper Counter can be obtained by first reading the Lower Counter at address
0017, then reading the Snapshot Latch at address 0018 or 0019.
Note that reading address 0019 also resets the Timer A Underflow (UFA) flag.

4

Timer A Clock Prescaier Enable'
Enable Clock Prescaler (02/128)
Disable Clock Prescaler (/32)

Bits 2 to 0 Timer A Mode Select (TAMS)
2 1 0
Timer A Off
Free-Run Event Counter Mode'
0 0 1
Free-Run Pulse Width Measurement Mode'
0 1 0
Retrlggerable One-Shot Timer Mode'
0 1 1
One-Shot Interval Timer Mode
1 0 0
Free-Run Interval Timer Mode
1 0 1
One-Shot Pulse Generation Mode
1 0
1
Free-Run Pulse Generation Mode
Note:
1. Prescaler must be disabled (bit 3=0) for Free-Run Event Counter
Mode, Free-Run Pulse Width Measurement Mode, and Retriggerable One-Shot Timer Mode. These three modes do not allow
prescaling.

a a a

A second architectural difference between the two timers is that
Timer A can have its clock input scaled down by a factor of 128
during normal power operation. This allows Timer A to measure
longer periods of time internally while the microcomputer in
operating at the 02 system clock rate. With a 4 MHz system
clock, more than two second time Intervals (up to 2.097 seconds) can be measured directly without any software intervention. Without the prescaler, 16.384 ms is the longest time interval
at 4 MHz.

3-21

9

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor

Timer A Operating Modes

Timer A One-Shot Pulse Generation, Mode 6

The Timer A mode of operation is selected by setting bits 0-2
of the Timer A Control and Status Register (TACSR) to the
appropriate code.

The PF3 data direction register bit must be set to a 1 before
starting this mode to in ~ially force a high output. Writing ULA
at 0019 starts the timer and clears the PF3 data output bit to
a 0 causing a low output. The PF3 output remains low until the
timer counts through zero. At this time, the PF3 output goes high
until the mode is restarted or a new mode is selected. The UFA
flag is also set at this time and the counter is stopped. The timer
counts at either the 02, or the scaled rt2 (021128), rate.

Timer A Off, Mode 0
Timer A is turned off in this mode. The Timer A Underflow Flag
(UFA) stays at its current state. The counter holds its current
value and may be read. Writing to the registers performs the
usual functions associated with that address but the counter
remains stopped. This is'the default condition.

Timer A Free-Run Pulse Generation, Mode 7
The data direction register for PF3 must be set to a 1 to select
the PF3 output before starting this mode. Writing to ULA at
0019 sets PF3 to 0 forcing a low output and starts the timer.
Each time the timer counts through zero, the PF3 output changes
state to generate a square wave at a rate dependent upon the
latch value. The timer counts at either 02, or the scaled 02 (021
128), rate. Each time the counter counts through zero, the latch
contents are automatically transferred to the timer registers and
the UFA flag is set.

Timer A Free-Run Event Counter, Mode 1
The Timer A Upper Counter (UCA) and Lower Counter (LCA)
is loaded with the Timer A Upper Latch (ULA) and Lower Latch
(LLA) value when the data is written to the Timer A Upper Latch
at address 0019. Timer A then decrements by 1 at each negative transition of the signal on Input Port PF3. (The Port F data
direction register must have a 0 in bit 3.) The Timer A Underflow
Flag (UFA) is set to 1 when the counter decrements below zero.
At this same time, the latch value is reloaded into UCA and LCA.
The maximum rate of the signal on PF3 which may be detected
is one-half of the 02 system clock rate.

COUNTER/TIMER B (TB)
Timer B is a simpler timer than Timer A but it still retains great
flexibility. Unlike Timer A, there is no "off" mode (the default
mode is the Free-Run Interval Timer Mode) and there is no separate selectable clock prescaler. All counting (except for counting
external events) is done either at the 02 clock rate or rt2l128
rate (when low power mode is selected). Another difference is
that Timer B does not have the snapshot latch register for
freezing the upper timer byte for reading. However, in its normal
modes the counter counts through zero to set the Underflow
Flag B (UFB) so that a snapshot latch register is not required.

Timer A Free-Run Pulse Width Measurement,
Mode 2
Writing to ULA at 0019 transfers the 16-bit latch to the counter
which operates as a timer in this mode. The initial value in the
timer is decremented at the 02 rate when the PF3 signal is low.
Otherwise, the counter holds its value. Counting stops when the
PF3 signal goes high and will resume if the signal goes low
again. If the counter counts below zero, the counter initial value
is reloaded from the latches and the UFA flag is set.

Timer B Mode Control
The operation of Timer B is controlled and monitored by the
Timer B Control and Status Register (TBCSR).

Timer A One-Shot Retriggerable Timer, Mode 3
This mode is similar to Mode 4 except that the timer restarts
each time PF3 goes through a high-to-Iow transition and counts
down until the counter goes through zero. A second difference
is that the clock prescaler may not be used with this mode. The
data direction register bit 3 (PF3) must be zero to select input.

Bits 0-1 select the Timer B operating mode.
Timer B Interrupt Enable, bit 4, when set to a 1 by a CPU,
enables generation of an internal interrupt request (IRQ) to that
CPU when the UFB flag is set.

Timer A One-Shot Interval Timer, Mode 4

Bit 6 of the TBCSR copies bit 4 of Port F (PF4).

Writing to ULA at 0019 transfers the initial value from the latches
and starts the timer. The timer counts at either the 162, or scaled
(12 (.0'2/128), rate. When the counter counts through zero, the
latch value is transferred to the counter, the UFA flag is set and
the counter stops counting.

Bit 7 in the TBCSR is the UFB bit which indicates that Timer B
has counted down through zero. This may be detected by
reading the bit or may be used to cause an fRO interrupt if bit
4 of the TBCSR is set to a 1. The UFB bit is reset by either
reading UCB or writing to U LB at address 001 D.
Timer B Control and Status Register (TBCSR)

Timer A Free-Run Interval Timer, Mode 5
7

Writing ULA at 0019 transfers the 16-bit latch value to the timer
and starts it running. The counter counts down at either the 02,
or the scaled 02 (021128), rate. When the counter counts through
zero the UFA flag is set, the value in the latches is transferred
to the counter, and the counter continues to count down.

6

5

TMR B
PF4
NOT
UNFL
LEVEL
FLAG
USED
IND
(UFB)

3-22

4
TMR B
INT
ENBL

3

1

2

NOT USED

1

1

TIMER B
MODE
SELECT

0

R65COO/21 • R65C29
Bit 7
1

Timer B Underflow Flag (UFB)
Underflow condition occurred
No underflow

Bit 6
-1

Port F Bit 4 (PF4) Level Indicator
PF4 High
PF4 Low

o
o

~

Not Used (Don't care)

Bit 4

Bits 3-2

Timer B Interrupt Enable
Enable Timer B Interrupt
Disable Timer B Interrupt
Not Used (Don't care)

Bits 1-0

Timer B Mode Select (TMS)

1

o
1

Dual CMOS Microcomputer/Microprocessor
Timer B Free-Run Pulse Generation, Mode 1
The data direction register for PF4 must be set to a 1 to select
PF4 output before starting this mode. Writing to ULB at 001 D
sets PF4 to 0 to force the PF4 output low and starts the timer.
Each time the timer counts through zero, the PF4 output changes
state to generate a square wave at a rate dependent upon the
initial value loaded into the latches. The timer counts at the (;12
rate. Each time the counter counts through zero, the latch values
are automatically transferred to the timer registers and the UFB
flag is set to a 1.

Timer B Event Counter, Mode 2

0

0" '0
o 1
1

0

1

1

The data direction register bit for PF4 must be set to a 0 to select
PF4 input prior to selecting this mode. The counter is loaded
with the latch value when the ULB data is written to address
001 D. Timer B then decrements by 1 at each negative transition
on input Port PF4. The Timer B Underflow Flag (UFB) is set to
a 1, when Counter B counts through zero. At this same time,
the latch value is reloaded into Timer B. The maximum rate of
the signal on PF4 which may be detected is one-half of the 112
clock rate.

Free-Run Interval Timer Mode
Free-Run Pulse Generator Mode
Event Counter Mode
Pulse Width Measurement Mode

Timer B Operating Modes
The Timer B operating mode is selected by setting bits 0 and
1 in the TBCSR to the appropriate code.

Timer B Pulse Width Measurement, Mode 3

Timer B Free-Run Interval Timer, Mode 0

Writing to ULB at 001 D transfers the 16-bit latch value to the
counter. The initial value in the timer is decremented at the (;12
rate when the PF4 signal is low. Each time the PF4 signal goes
high, the counter stops and then continues when the signal is
low again. If the counter counts through zero, the UFB flag is
set to 1 and the latch value transfers to reinitialize the counter
and the countdown continues as long as PF4 is low.

Writing to Timer B Upper Latch (ULB) at 001 D transfers the
16-bit latch value to the timer and starts it running. The counter
counts down at the ~2 rate. When the counter counts through
zero, the Timer B Underflow Flag (UFB) is set to a 1, the value
in the latches is transferred to the counter and the counter continues to count down.

3-23

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor

BUS EXTENSION
Figure 9 is an overall block diagram of a system using the
R65COO/21 in the bus extension rnode.

In addition to its application as a single-chip microcomputer, the
bus extension mode allows the R65COO/21 to operate as a microprocessor with external memory and 1/0.

The CPU A Active signal (bit 7 of the BCR) is high when CPU
A is controlling the system bus, and low when CPU B is active.
This bit copies the state of the filA output signal. Consequently,
the bit may be sampled in common subroutines to determine
the calling CPU, or for bank selection purposes. Thus, CPU A
and CPU B may have some external memory or I/O dedicated
to their exclusive use. Each may separately address as much
as 59.5K bytes of external memory map, or external memory
may be shared.

BUS EXTENSION MODE
When the R65COO/21 is used as a single-chip microcomputer,
all of the output ports may be used as input or output ports.
However, to use the R65COO/21 with external ROM, RAM, or
I/O, a number of the ports act as extensions of the internal
address and data buses. Specifically, Port D becomes dedicated as a multiplexed 8-bit data and address bus. Port D provides both the data bus (DO through D7) and the low bits of the
address (AO through A7) on pins PDO through PD7. When a bus
extension mode is selected, the Port D Data Direction Register
must be cleared to zero (its default condition) to configure Port
D as all inputs. The R65COO/21 then controls Port D as an
extension of the Internal bus structure and provides an activelow External Memory Select (EMS) strobe signal at the time the
address bits are available. The EMS signal is present even
when Port D is being used as a normal input/output register.

Bus Control Register (BCR)
7

6

CPUA
ACTIVE

PAGE
ONE
EXT

3

I

Bits 6-5

Not Used (Don't Care)

Bit 4
1

Page One External/Internal Mapping

o

.£.
0

o

o
Bits 1-0

1. JL

o
o
1

0

0

1
0

Port A Write Nibble Control'
CPU A writes to both halves (PAO-PA7).
CPU A writes to upper half (PA4-PA7); CPU B
writes to lower half (PAO-PA3).
CPU A writes to lower half (PAO-PA3); CPU B writes
to upper half (PA04-PA7).
CPU B writes to both halves (PAO-PA7).
Bus Extension Mode
Bus ExtenSion Mode not selected.
S-bit Address Extension Mode. Range equals 256.
12-bit Address Extension Mode. Range equals 4096.
16-bit Address Extension Mode. Range equals
65,536.

Note:
-Either CPU may read the full port at any time.

3-24

I

Page One External
Page One Internal

Bits 3-2

1.

1

BUS
EXTENSION
MODE

CPU A active
CPU B active

o

In a one-chip configuration, the 128 bytes of internal page one
RAM (address 0180 through 01 FF), is logically combined with
page (0080-00FF). However, when an extended bus is used,
the stack page may be addressed in its normal range in external
memory (0100-01 FF). When bit 4 of the Bus Control Register
is a 0, page one is internal and shared with page zero; when it
is aI, page one is external allowing full 256 bytes available to
the two stacks.

2

PORTA
NIBBLE
MODE

CPU A Active

o

Since Port D is mu~iplexed, it is necessary that external latches
be supplied to hold the lower eight bits of the address bus. The
EMS output is low when the address is being supplied from Port
D. All of the other necessary control bus signals are also provided; these include 132 and R/W. The SYNC and filA signals are
also brought out for use by development systems and bus analyzers for system debugging.

4

5

NOT USED

Bit 7
1

The R65COO/21 has the option of using 8-, 12- or 16-bit address
bus extensions. Selection of the bus extension mode is controlled by bits 0 and 1 of the Bus Control Register (BCR). When
the 8-bit mode is selected, only the Port D multiplexed address!
data bus function is required. However, if either the 12- or 16bit address bus extension is selected, either one half or all of
output Port E also becomes dedicated to the bus extension
function. If a 16-bit bus extension is selected, then all of Port E
becomes the upper address bits A8 through A15 on pins PEO
through PE7, respectively. If the 12-bit bus extension is selected,
then the address lines A8 through All appear on PEO through
PE3. In this case, PE4 through PE7 have their usual output
function.

I

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor

PORT A

VDD
Vss

PORT B

RES
PORT C
XTALO

XTALI

NMIA

R65CDD/21
DUAL
MICROCOMPUTER

PORT F

PORTG
NMIB

PORT E UPPER ADDR 0, 4, 8"
SYNC
LOWER
ADDR
LATCH

8

8
LOWER
A-__~A~DDR~______~,

PORT D

DATA

8

02
R/W

NOTE:
"UPPER ADDRESS EXTENSION MAY BE 0, 4 OR 8 LINES.

Figure 9.

Bus Extension Mode Block Diagram

3-25

UP TO
59.5K BYTES
EXTERNAL
MEMORY
AND
PERIPHERALS

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor
Table 4.

PROGRAMMABLE PERIPHERAL
TO A HOST MODE
An overall block diagram of a system using an R65COO/21 as
an intelligent controller is shown in Figure 10.
In this configuration, three of the R65COO/21 input/output ports
have special significance. Port C becomes the interface wHh the
host data bus (Port C's Data Direction Register must specify as
the input; i.e., all zeros). Pin PF7 becomes an active-low Host
Interrupt (HINT) line, and the 4-bit input Port G becomes the
control pins interface to the Host computer.
The R65COO/21 is configured to operate as a peripheral for
either the R6500 or 6800 families, or the Z80 or 8080 families.
When operating in the 6500/6800 mode, PGO is an input for the
host (12 (HIl2) and PG1 is the input for the host R/W (HRW)
control lines.
When operating in the Z8018080 mode, PGO accepts the host
RD (HRD) control and PG1 provides the host WR (HWR) control.
In both cases, PG2 serves as a register select (HRS) and PG3
acts as an active-low chip select (CS) from the host. HRS is
used in conjunction with the CS and HWR to control reading or
writing of data or status information as shown in Table 4.

HRW
(PG1)

Register Select Control
HfJ2
(PGO)

Host Function
(6500/6800 Mode)

-

Host Interface Deselected
Write Input 8uffer,
HCSR5 RSI cleared, set IBF
Read Output Buffer, Clear OBF
Write Input Buffer,
HCSR5 RS1 set, set IBF
Read upper 3 bits of HCSR;
OBF, IBF & RSO

CS
(PG3)

fiRS
(PG2)

H
L

-

-

L

L

L
L

L
H

H
L

H
H

L

H

H

H

CS
(PG3)

HRS
(PG2)

HWR
(PG1)

HRD
(PGO)

Host Function
(8080/Z80 Mode)

H
L

-

-

-

L
L

L
H

H
L

L
H

L

H

H

L

Deselected
Write Input Buffer,
HCSR5 RSI cleared, set IBF
Read Output Buffer, Clear OBF
Write Input Buffer,
HCSR5 RS1 set, set IBF
Read upper 3 bits of HCSR;
OBF, IBF & RSO

L

L

H

H

Host Control and Status Register (HCSR)
6

7
O/P
BUFF
FULL
INT
FLAG
(OBE)

Control of the host mode options is provided by the Host Control
and Status Register (HCSR).
When the host writes a byte into the Input Buffer (Port C), the
Input Buffer Full (IBF) flag is set to a 1. Similarly, when a byte
is read from the Output Buffer (Port C) by the host, the Output
Buffer Full (OBF) flag is cleared to a O. Setting bit 3 of the HCSR
enables generation of an internal interrupt request (IRQ) when
either the IBF flag is a 1 or the OBF flag is a O. This logic is
duplicated for both CPU's.

5

VO
BUFF
FULL
INT
FLAG
(IBF)

3

4

VOA
INT
ENBL

VO
REG
SEL
(RSI)
(RSO)

NOT
USED

VoB
INT
ENBL

1

2

HOST
INT
ENBL

HOST
BUS
ENBL

0

HOST
BUS
TYPE

Output Buffer Empty (OBE) Flag
Output Buffer Full
Output Buffer Empty

o

Setting bit 2 of the HCSR to a 1 enables generation of any
interrupt signal to the host computer. In this case, bit 7 of Port
F is pulled low by either a write to Port C (Output Buffer) or a
read from Port C (Input Buffer), by either of the R65COO/21
CPU's.

Bit 6
1

Input Buffer Full (IBF) Flag
Input Buffer Full
Input Buffer Empty

BitS

Register Select
Distinguishes commands from data. Host reads
RSO and R65C00l21 reads RSI. Selection of 1 or 0
to represent commands or data is user defined.

o

Bit 5 of the HCSR is actually two different bits representing Register Select Input (RSI) and Register Select Output (RSO). The
R65COO/21 writes bit RSO and reads bH RSI, while the host
writes RSI and reads RSO. The R65COO/21 wrHes a 0 to this
bit when Port C is addressed at 0002 and a 1 when Port C is
addressed at 0003. When the host writes to the R65COO/21
through Port C, the level of the HRS input is copied into the RSI
bit. This bit allows the communications between the host system
and the R65COO/21 to flag the type of data being transferred
so that command information may be distinguished from data.

Brt4

Not Used. (Don't care)

Bit 3

Input/Output Buffer Interrupt Enable
Enable IRQ IBF = 1)
Disable IRQ

-1-

o
Bit 2
1

Host Interrupt (HINT) Output Enable
Disable RTiii'f Output to Host
Enable HINT Output to Host (OBF = 1)

Bit 1
1

Hoet Bus Enable
Disable Host Bus
Enable Host Bus

Bit 0
1

Host Bus Type
Host Bus is Z80/8080
Host Bus Is 6500/6800

o

o

o

Note:
Register

3-26

IS

cleared to all zeros by RES.

Dual CMOS Microcomputer/Microprocessor

R65COO/21 • R65C29

~
8

-

Vss

XTALO

XTALI

SYNC

--

-

PORTA

..

V

8

PORTB

...

.
R65COO/21
DUAL
MICROCOMPUTER
USED
AS AN
INTELLIGENT
CONTROLLER

8

..

PORT D

8

PORT E

8

PORT F

HINT

PORT C HOST DATA BUS 8)
H,2/HRD

PGO

HRIWIHWR

PG1

HRS

PG2

CS

PG3

Figure 10.

HOST
SYSTEM

Host Mode Block Diagam

EMULATION MODE
The R65COO/21 can operate in an emulation mode under external signal control.

To further aid program development in emulation mode, all bus
cycles which perform a memory or I/O write operation, whether
the true destination is internal or external, will assert the External
Memory Strobe (EMS) signal. This allows a copy of internal register and memory values to be kept in external memory.

Emulation mode deselects the internal ROM and enables the
16-bit Expanded Bus mode, independent of the bus mode programmed in the Bus Control Register. Since the Expanded Bus
mode uses peripheral Ports D and E, provision is made for
these to be emulated in external hardware. This is accomplished by forcing all memory references to Ports D and E to
be External Bus cycles. Accesses to the Data Direction Register
for Port D are also forced external.

Emulation mode is selected by applying the %2 output clock
signal to the RES input pin.

3-27

Dual CMOS Microcomputer/Microprocessor

R65COO/21. R65C29

INSTRUCTION SET IN ALPHABETIC SEQUENCE
The instructions notated with a ' are added instructions for the
R65COO/21 and R65C29 which are not part of the standard
6502 instruction set.

The following table contains a summary of the R65COO/21 and
R65C29 CPU instruction set. For detailed information, consult
the R6502 Microcomputer System Programming Manual, Order
No. 202.

Instruction Set in Alphabetic Sequence
Mnemonic
ADC
AND
ASL
'BRA
'BBR
'BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS

Description

Mnemonic

Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)

LDA
LOX
LDY
LSR

Branch Always
Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC
CLD
CLI
CLV
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable
Clear Overflow Flag
Compare Memory and
Compare Memory and
Compare Memory and

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

EOR

"Exclusive-Or" Memory with Accumulator

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Index Y by One

JMP
JSR

Jump to New Location
Jump to New Location Saving Return Address

'MUL

Bit
Accumulator
Index X
Index Y

Multiply

NOP

No Operation

ORA

"OR" Memory with Accumulator

PHA
PHP
'PHX
'PHY
PLA
PLP
'PLX
'PLY

Push Accumulator or Stack
Push Processor Status on Stack
Push Index X
Push Index Y
Pull Accumulator from Stack
Pull Processor Status from Stack
Pull Index X
Pull Index Y

'RMB
ROL
ROR
RTI
RTS

Reset Memory Bit
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine

SBC
SEC
SED
SEI
'SMB
STA
STX
STY

Subtract Memory from Accumulator With Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X In Memory
Store Index Y in Memory

TAX
TAY
TSX
TXA
TXS
TYA

3-28

Description
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)

Transfer
Transfer
Transfer
Transfer
Transfer
Transfer

Accumulator to Index X
Accumulator to Index Y
Stack POinter to Index X
Index X to Accumulator
Index X to Stack Register
Index Y to Accumulator

:tI

IINEMOMC

OPERATION

IIIIIElMATEIABSOLUTE\ZEROPAGEI ACCUII.

I

IIIPUED I (INO,X)

I (IND},Y

Iz PAGE, Xl

I

ABS,X

ABS,Y

IREUnVEllNDIRECTlz PAGE,Y

OPlnlIlIOPlnl#tOPln 1#-IOPln11l1OPln I#-IOPI nl#-IOPI nl#-IOPI nllllOPlnllllOPln IIIIOPlnllllOpl nllllOPI nlll
AOC
AND

ASL

A+M+e-.A
A M--A

6.

14} II)
(I)

C~cr::==::1!J

_____

601'1'165

20 4 3 25
_ ES3_SI5

29

21

6

2

31
71

5

2

35

4

2

16

6

2

30
IE

4

3

7

3

39

4

BIT

A

BVC
BVS
ClC

B~C
,,~O

08

Cli
ClV
CMP

jf~1

58
B8

BRI<

on N 1 (2)
on Z=~ (2)
on N -:J (2)
Ahways (I)

on V ~ (2)
on V I (2)

(,--+V
A M

CPX

X M

CPY
DEC
OEX
DEY
EOR
INC
INX
INY
JMP
JSR
LOA
LOX

Y M
M '~M
X l--+X
Y '~Y
A'fM--+A (1)
M+ '~M
X - 1-~X
JumptoNewloc
Jump Sub
M--A (1)
M--X (1)

I'DY
LSR
NOP

~-. rr==:lO
NoOpefallon

M--oY

MUL
ORA
PHA
PHP
PHX
PHY
PLA
PLP
PLX

~ T
2 IT
2 O
EC
G
qJ 2 2 CC
GE

,, ,,
,
,

G5
E'

cli 6 I 2 I 01 I 5 I 2

ATI
RTS
SBC

SEC
SED
SEI
SM8{#(J-711
STA
STX

G6

TAY
TSX
TXA

"S
TVA

2 100

061 sl 2

I 4 I 3 I 09 I

4

I DE I 71

"

AD
AE
AG
'E

A9

,.,
A2

-

G

~.

2

2 '0

Rtm Int
RIm Sub
A-M C-A II) (5)

O.

2

80
'.

2312

M,M. -

AS
A6

, ,

..
..

•

2 G

Z G
2 C
Z

591413

Z

2

'TITTI'

~I

3

EA
0:2

121'

3

I:~ I :

· z

en

0

·2

s:
»
:0

n"
.,

2

:1; I~~

I2

2
2
2 G

B'

101

2

(,11 61 21 111 5121151 412110

I 41

3 119

I4

N

13

•

48

-t

08
OA 13

: I':I~
SA

FA
7A

4
4

1
1

N
N

•
•

(Res10red)
- - - -

•

~71 171 27 I 37 1471 57 I 67 177

~~I:I~I=I;I;I~I~I:

:: I: I~

E9 I 2 I 2 I EO I 4 I 31 E5] 3 I 2

l .....C
1..... 0
I ..... T

~I
Ell

:1; I;~ 1~

Z
Z

•

Z G
2 G
(Restored)

2

sl 21 Fll 5 I 2 I F51 4 I 2 I FO I 4 I 3 I F9 I 4 I 3

i5

381'1'
F8

2

1

'"

2

,

801'1'185

61 21 911 61 21 951 41 2 I 90 I 51 3 I 991 5 I 3

aE4386

S--X
X-A
X-S
Y_A

Notes:
1 Add 1 to N If page boundary IS crossed
2 Add 1 to N If branch occurs to same page
Add 2 to N If branch occurs to different page
3 Carry not (C) :: Borrow
4 If In deCImal mode Z nag IS Invahd
accumulator must be checked 00 zero result
5 Effects 8-blt data fIeld of the specIfied zero page address

M/21'
SA
,
AS

2

8A
9A

21'

98

2
,

!!.
0

:s::

0

()

0

3

'0
C

-n":s::
Ci
.,

941 41 2

aC4384

A--X
A_Y

cc

c: en
s: :s::

-<

87 I 97 I A7 187 IC7 I D7 I E7 IF7
all

~
c:
~

:0

6
z
en
m

f 613
B61 4

I\)

,CD

Z

Z

A4

_5

~

U1

2

All 6 I 2 I 81 I 5 I 2 I Bsl 4 I 2 I Bo I 4

......

•

· 2

~

6C

,
,

I\)

0

I3

'G

.e

!~I ~~I ;~I ~~ I~~I ~~I ~~ I;~

3

~~ I ~

F6

0

0

Z G

2
2

~ I; 1~

~

STV

TAX

I

411 61 21 511 512155

'5
E6

EE

A*Y-A ,s a Y7-o
AVM--A (I)
A--+Ms 5 1--5
P~Ms 5 1 ~S
X--+Ms 5 - 1--5
Y~Ms 5 1 .5
5-1--+5 Ms-·A
S'l~S Ms--->P
S·l~S Ms·X

X~M

4

ZC

C4

~I; I~
491212140

(1)

I ..... M. (5)
A--+M

I 051

1 •

I

2 •

'.

1
,
,

"121'

~~~II(._7)II;~~:S (5~S-~Y

I~~

2
2
2

2

U1

2 G

5.

00 1 7 11

90

N V

B'F,
"12 12

2C] 4 I 31 24 I 3 12

ClD

BNE
BPl
BRA

~
CD

M

5 4 3

N

98

Branch
Branch
Branch
Branch
Break
Branch
Branch

a

I7

51alllNV.

3

BBRI#{Jf-7)] Branch on Mo=O (5)
BBS(lIfJJ-7l] Branch on Mo·, (5)
BCC
Branch on C=~ (2)
BCS
Branch on C = I (2l
BEQ
Branch on Z -, (2)
8MI

Bn ADDRESSING (OP BY BIT II)
.111213141

6'1 6121 I 51'1'51'1 21'0 1'1'1"1' I'

_AI 2 11

Q)

PROCESSOR STATUS
CODeS

ADDRESSING MODE

N

•

N

•

1

,

LEGEND
X
= Index X
Y
= Index Y
A
= Accumulator
M
= Memory per effectIVe address
Ms = Memory per stack pOinter
Mb = Selecter zero page memory btt
M1 = Memory BIt 7

a

M~

~

1\

=
~

V
V-

=
=

m
/I

=
=

•

Z

BIt 6
Add
Subtract
And
Or
ExcluSIve or
Number of cycles
Number of Bytes

= Memory

(3

'0

(3

()

CD
til
til

0.,

R65COO/21. R65C29

Dual CMOS Microcomputer/Microprocessor

INSTRUCTION SET OPERATION CODE MATRIX
The following matrix shows the op codes associated with the
R65COO/21 and R65C29 CPUs. The matrix identifies the
hexadecimal code, the mnemonic code, the addressing mode,

3

o

BRK
ORA
Implied (IND. X)
1 7
2 6

7

8

9

A

ORA
ZP
2 3

ASL
ZP
2 5

RMBO
ZP
2 5

PHP
Implied
1 3

ORA
IMM
2 2

ASL
Accum
1 2

ORA
ZP, x
2 4

ASL
ZP, X
2 6

RMBI
ZP
2 5

CLC
Implied
1 2

ORA
ABS,Y
3 4-

AND
ZP
2 3

ROL
ZP
2 5

RMB2
ZP
2 5

PLP
Implied
1 4

AND
IMM
2 2

4

MUL
Implied

1 10

BPL
ORA
Relative (INO). Y
2 2-2 5-

5

B

2

3

BMI
AND
Relative (INO, Y)
2 2-2 5-

AND
ZP, X
2 4

ROL
Zp,X
2 6

RMB3
ZP
2 5

SEC
Implied
1 2

AND
ABS,Y
3 4-

4

RTI
EOR
Implied (INO,X)
1 6
2 6

EOR
ZP
2 3

LSR
ZP
2 5

RMB4
ZP
2 5

PHA
Implied
1 3

EOR
IMM
2 2

BVC
EOR
Relative (INO). Y
2 2-2 5-

EOR
ZP. X
2 4

LSR
ZP,X
2 6

RMBS
ZP
2 5

CLI
Implied
1 2

EOR
ABS,Y
3 4-

PHY
Implied

6

RTS
AOC
Implied (IND. X)
1 6
2 6

AOC
ZP
2 3

ROR
ZP
2 5

RMB6
ZP
2 5

PLA
Implied
1 4

AOC
IMM
2 2

ROR
Accum
1 2

7

BVS
AOC
RelatIVe (INO, Y)
2 2-2 5-

AOC
ZP,X
2 4

ROR
ZP. X
2 6

RMB7
ZP
2 5

SEI
Implied
1 2

AOC
ABS,Y
3 4-

PLY
Implied

8

BRA
STA
Relative (IND. X)
2 6
2 3-

ZP
2 3

STA
ZP
2 3

STX
ZP
2 3

5MBO
ZP
2 5

DEY
Implied
1 2

BCC
STA
Relative (IND. Y)
2 2-2 6

ZP. X
2 4

STA
ZP,X
2 4

STX
ZP, Y
2 4

5MB1
ZP
2 5

TYA
Implied
1 2

STA
ABS,Y
3 5

TXS
Implied
1 2

LOY
ZP
2 3

LOA
ZP
2 3

LOX
ZP
2 3

5MB2
ZP
2 5

TAY
Implied
1 2

LOA
IMM
2 2

TAX
Implied
1 2

LOY.
ZP, X
2 4

LOA
ZP, X
2 4

LOX
ZP, Y
2 4

5MB3
ZP
2 5

CLV
Implied

1 2

LOA
ABS,Y
3 4-

TSX
Implied
1 2

CPY
ZP
2 3

CMP
ZP
2 3

DEC
ZP
2 5

5MB4
ZP
2 5

INY
Implied
1 2

CMP
IMM
2 2

OEX
Implied
1 2

CMP
ZP. X
2 4

DEC
ZP, X
2 6

5MBS
ZP
2 5

CLO
Implied
1 2

CMP
ABS,Y
3 4-

PHX
Implied
1 3

sac

INC
ZP
2 5

5MB6
ZP
2 5

INX
Imploed
1 2

sec
IMM
2 2

NOP
Implied
1 2

INC
ZP,X
2 6

5MB7
ZP
2 5

SED
Implied
1 2

SBC
ABS,Y
3 4-

PLX
Implied

8

9

A

B

C

o
E

F

LOY
IMM
2 2

LOA
(INO, X)
2 6

BIT
ZP
2 3

STY

STY

LOX
IMM
2 2

BCS
LOA
Relative (INO), Y
2-2
2 5CPY
IMM
2 2

CMP
(INO,X)
2 6

BNE

CMP

Relative (INO). Y
2 2--

2 5-

CPX
IMM
2 2

SBC
(INO,'X)
2 6

CPX
ZP
2 3

BEQ
sec
Relative (INO),Y
2 2-2 5-

o

ZP
2 3

sec
ZP. X
2 4

2

3

4

o
BRK
Implied

1 7

-op Code
-Addressing Mode
-Instruction Bytes; Machine Cycles

6

D

3-30

ROL
Accum
1 2

BIT
ABS
3 4

LSR

JMP
ABS
3 3

Accum
1 2

o

E

F

ORA
ABS
3 4

ASL
ABS
3 6

BBRO
ZP
3 5--

JMP
Indirect
3 5

1 4
STY
ABS
3 4

BBR2
ZP
3 5--

AND
ABS.X
3 4-

ROL
ABS, X
3 7

BBR3
ZP
3 5--

EOR
ABS
3 4

LSR
ABS
3 6

3 5--

CPX
ABS
3 4

B

C

4

5--

BBR6
ZP
3 5--

AOC
ABS,X
3 4-

ROR
ABS,X
3 7

BBR7
ZP
3 5--

STA
ABS
3 4

STX
ABS
3 4

BBSO
ZP
3 5--

LOA
ABS
3 4

2

BBRS
ZP
3

ROR
ABS
3 6

BBSI
ZP

3 5-LOX
ABS
3 4

BBS2
ZP
3

A

5--

LOX
ABS.Y
3 4-

BBS3
ZP
3 5--

B

CMP
ABS
3 4

DEC
ABS
3 6

BBS4
ZP
3 5--

C

CMP
ABS.X
3 4-

DEC
ABS, X
3 7

BBSS
ZP
3 5--

o

SBC
ABS
3 4

INC
ABS
3 6

INC
sec
ABS, X ABS,X
3 7
3 4-

1 4

BBR4
ZP

AOC
ABS
3 4

LOY
LOA
ABS, X ABS,X
43
3 4CPY
ABS
3 4

5--

ROL
ABS
3 6

STA
ABS.X
3 5
LOY
ABS
3 4

BBRI
ZP
3

AND
ABS
3 4

EOR
LSR
ABS, X ABS, X
3 7
3 4-

1 3

TXA
Implied
1 2

-New Opcode

C

ORA
ASL
ABS.X ABS, X
3 43 7

JSR
AND
Absolute (INO,X)
3 6
2 6

A

o

the number of instruction bytes, and the number of machine
cycles associated with each op code. Also, refer to the instruction set summary for additional information on these op codes.

o

E

BBSS
ZP
3

BBS7
ZP
3

E

5--

F

5-F

-Add 1 to N If page boundary is crossed.
--Add 1 to N if branch occurs to same page;
Add 2 to N if branch occurs to different page.

Dual CMOS Microcomputer/Microprocessor

R65COO/21. R65C29
1/0 PORT WAVEFORMS-ALL PORTS

\
PO RTINPUT

X

x

xx
x

.xx xxx
xx .xx

N"
x y
tps

tpH

)

PO RT OUTPUT
- tpD -

1/0 PORT TIMING-ALL PORTS
2 MHz

4 MHz

SymbDI

Min

Max

Min

Max

Input Data Setup Time

tps

50

-

35

-

Input Data Hold Time (Port D)

tpH

10

10

-

25

-

25

-

-

120

-

100

Parameter

Input Data Hold Time
(All ports except D)
Output Data Delay Time

tpo

3-31

R65COO/21 • R65C29

Dual CMOS Microcomputer/Microprocessor

EXPANSION BUS TIMING
(Vee = s.ov

± 10%, TA = OOC to 70°C
4 "11Hz

2 "11Hz
Parameter

Unit

Symbol

"IIln.

"IIax.

"IIln.

"IIax.

02 Cycle Time

leyc

500

See Nole 1

250

See Nole 1

ns

Pulse Width 02 Low

tpWL

235

265

115

135

ns

Pulse Width 02 High

IpWH

235

265

115

135

ns

0A Delay Time -

12AO

0

60

0

50

ns

EMS Delay Time - Address Valid 10 EMS Low

lEMA

10

-

10

-

ns

EMS Delay Time - 02 to EMS Low

tEMO

-

150

-

115

ns

EMS Hold Time

tEMH

10

-

10

-

ns

RW Delay Time

t Awo

20

100

10

80

ns

PE Address Delay Time

t AEo

20

100

10

80

ns

PO Address Delay Time

t AOO

20

120

10

100

ns

Data Delay Time - Write

toow

-

120

-

100

ns

Data Hold Time - Write

tOHW

20

-

20

-

ns

60

ns

-

ns

Clock/Control Timing

02 10 02A

Write Timing

Read Timing
PO Address Hold Time Data Setup Time Data Hold Time Note:

Read
Read

Read

t AoH

0

tOSA

50

tOHA

10

80

-

0
35
10

ns

1. The 02 clock should never be held static at a dc level. The maximum cycle time (tCyel that guarantees no data loss to internal
registers IS 20 microseconds.

3-32

Dual CMOS Microcomputer/Microprocessor

R65COO/21 • R65C29

EXPANSION BUS WRITE CYCLE WAVE FORMS

1\2

"\

--

.

.

leye
IPWL

IpWH

"\

/
12AO

I--

/

--

t RWD

I--

'\

R/W

....

I EMO

-r

tEMH~

'\
---IAEO-

ADDR~SS HIGH VALID

I

PE

I.

I--IEMA

_ IAOO -

PD

loow

.
~

ADDRESS LOW VALID

-

~

IOHW

DATA OUT
VALID

I--

r

EXPANSION BUS READ CYCLE WAVE FORMS
leye
IpWH

IPWL

r/l2

/f-

'\

M

R/W

--

EMS

12AO

'\

"I<-

-

I RWO

-

/~

--

I--IEMH

k(

IEMH

r-

V-

- IAEO -

PE

~

~

~IADD

PD

I

ADDRESS HIGH VALID
I

I

---j

tAOH

ADDRESS LOW
VALID

3·33

I-=-

-

.•

tDSR~

DATA IN VALID

k!OHN

r

R65COO/21. R65C29

Dual CMOS Microcomputer/Microprocessor

MAXIMUM RATINGS*
Parameter

Symbol

Value

Unit

Vec

-0.3 to +7.0

Vdc

Supply Voltage
Input Voltage

V,N

-0.3 to Vec +0.3

Vdc

Operating Temperature

TA

o to +70

°C

Storage Temperature

T STG

-55 to + 150

°C

DC CHARACTERISTICS
= +5.0V ± 10%, TA = O°C to

Vcc

Parameter

·NOTE: This device contains circuitry to protect the inputs
against damage due to high static voltages, however, it is
advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this circuit.

70°C (unless otherwise specified)
Symbol

Input High Voltage

V'H

Min
+2.0

-

Max

-

Unit

Test Condition

V

+0.8

V

-

V

Vee = 4.5V
ILOAD = -100."A

±10

."A

V'N = OVor Vee
Vee = OV

-

+0.4

V

Vee = 4.5V
ILOAD = 1.6 mA

louT

-

-1.6

mA

C'N

-

25
5

pF
pF

Input Low Voltage

V'L

Output High Voltage

VOH

Input Leakage Current

I'N

-

Output Low Voltage

VOL

Output Low Current
(All ports except Port G)
Input Capacitance
(XTALO, XTALI)
(All Others)

+2.4

-

Output Capacitance

C OUT

-

10

pF

Operating Frequency
Crystal or Master Clock
.02 Clock

-

.02
.01

8.0
4.0

MHz
MHz

Power Dissipation

PD

-

40

mW

Note: Negative sign indicates outward current flow, positive sign indicates inward current flow.

3-34

=

VOL

Vee

1=
TA

O.4V

= 5V
2 MHz
25'C

=

Vee = 5V
f = 2 MHz
TA = 25°C

Dual CMOS Microcomputer/Microprocessor

R65COO/21. R65C29
PACKAGE DIMENSIONS
64 PIN PLASTIC QUIP (QUAD IN-LINE PACKAGE)

I

MILLIMETERS

F~ ~ ~GIn ~GrInn t ~ nlln nn nnll~n nil nn n~n ~nnnnnnJl
64
33

!

MIN

MAX

MIN

MAX

A

41.15

41.66

1.620

1640

B

17.02

17.53

0.670

0.690

3.05

4.57

0.120

0.180

0.38

0.51

0.024

0.020

D
F
C

B

G

11
u ~u

J

H

32

~u~ u~u ~u ~u~urr~u ~u ~u~u~u ~u~

K

I'
-~H

A

'j l
~

-I~D

C

KT

-t

IT

1.27 BSC

0.050 BSC

2.54 BSC
1.02

2.79

0.100 BSC
1.14

0.040

7°

-

7°

4.32

0.110

0.170

0.045

L

18.92

19.81

0.745

0.755

M

23.37

2362

0.920

0930

TI

1'-~-jJLJ

3-35

INCHES

DIM

R65F11 • R65F12

'1'

Rockwell

R65F11 AND R65F12
FORTH BASED MICROCOMPUTERS

SECTION 1
INTRODUCTION
1.1 FEATURES

• Flexible clock circuitry
-2-MHz or I-MHz internal operation
-Internal clock wHh external XTAL at 'two times internal
frequency
-External clock input divided by one or two

• FORTH kernel in ROM
• Enhanced 6502 CPU
-Four new bH manipulation instructions:
Set Memory Bit (SMB)
Reset Memory Bit (RMB)
Branch on Bit Set (BBS)
Branch on Bit Reset (BBR)
-Decimal and binary arithmetic modes
-13 addressing modes
-True indexing

•
•
•
•
•
•

• 192-byte static RAM
• 16 bidirectional, TIL-compatible I/O lines (two ports, R65Fll)
or 40 bidirectional, TIL-compatible I/O lines (five ports,
R65F(2)

1 JLS minimum instruction execution time @ 2 MHz
NMOS silicon gate, depletion load technology
Single +5V power supply
12 mW standby power for 32 bytes of the 192-byte RAM
4O-pin DIP (R65Fll)
64-pin QUIP (R65FI2) has three additional8-bit I/O ports to
provide a total of 40 I/O lines.

1.2 SUMMARY
The Rockwell R65Fll and R65F12 are complete, high-performance, B-bit NMOS single chip microcomputers, and are compatible wHh all members of the R6500 family.

• One 8-bit port with programmable latched input
• Two 16-bit programmable counter/timers, with latches
-Pulse width measurement
-Asymmetrical pulse generation
-Pulse generation
-Interval timer
-Event counter
-Retriggerable interval timer

The kernel of the high level Rockwell Single Chip RSC-FORTH
language is contained in the preprogrammed ROM of the R65Fll
and R65F12. RSC-FORTH is based on the popular fig-FORTH
model wHh extensions. All of the run time functions of RSCFORTH are contained in the ROM, including 16- and 32-bit
mathematical, logical and stack manipulation, plus memory and
inpuVoutput operators. The RSC-FORTH Operating System
allows an external user program written in RSC-FORTH or
Assembly Language to be executed from external EPROM, or
development of such a program under the control of the R65FRI
RSC-FORTH Development ROM. Other development ROM's
can also be accommodated.

• Serial port
-Full-duplex asynchronous operation mode
-Selectable 5- to 8-bit characters
-Wake-up feature
-Synchronous shift register mode
-Standard programmable bit rates, programmable up to
62.5K bits/sec
• Ten interrupts
-Four edge-sensitive lines; two positive, two negative
-Reset
-Non-maskable
-Two counter
-Serial data received
-Serial data transmitted

The R65Fll and R65F12 consist of an enhanced 6502 CPU,
an internal clock oscillator, 192 bytes of Random Access Memory
(RAM) and versatile interface circuitry. The interface Circuitry
includes two 16-bit programmable timer/counters, 16 bidirectional inpuVoutput lines (including four edge-sensitive lines and
input latching on one B-bit port), a full-duplex serial I/O channel,
ten interrupts and bus expandability.

• Expandable to 16K bytes of external memory
The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction simplicity,
results in system cost-effectiveness and a wide range of

Document No. 29651N49
3-36

Product Description Order No. 2146
Rev. 3, October 1984

R65F11 • R65F12

FORTH Based Microcomputers

computational power These features In combinatIOn with the
FORTH high level operating system make the R65F11 and
R65F12 ideal for microcomputer applications.

(Order Number 201). A description of the instruction capabilites
of the R6502 CPU is contained in the R6500 Microcomputer
System Programming Manual (Order Number 202).

For systems requiring additional 1/0 ports, the 64-pln QUIP
version, the R65F12, provides three additional 8-blt ports.

1.3 ORDERING INFORMATION

A complete RSC-FORTH development system can be created with three MOS parts: the R65F11, one RAM chip and
the R65FR1 Development ROM.
This product description is for the reader familiar with the
R6502 CPU hardware and programming capabilities. A
detailed description of the R6502 CPU hardware is Included
in the R6500 Microcomputer System Hardware Manual

Part No.

Description

R65F11P
R65F11AP
R65F120
R65F12AO
R65FR1P
R65FR2P
R65FK2P

4O-Pin FORTH Based Microcomputer at 1 MHz
40-Pin FORTH Based Microcomputer at 2 MHz
64-Pin FORTH Based Microcomputer at 1 MHz
64-Pin FORTH Based Microcomputer at 2 MHz
FORTH Development ROM for R65F11 or R65F12
FORTH Development ROM for expanded capacity
FORTH Kernel ROM for expanded capacity
development
FORTH Development ROM for R65010
FORTH Kernel ROM for R65010

R65FR3P
R65FK3P
Order No.
2148

Description
FORTH Based Microcomputer User's Manual'

Note:
'Included with R65FR1.

3-37

R65F11 • R65F12

FORTH Based Microcomputers

SECTION 2
INTERFACE REQUIREMENTS
This section describes the interface requirements for the
R65F11 and R65F12 single chip microcomputers. Figure
2-1 is the Interface Diagram for the R65F11 and R65F12,
Figure. 2-2 shows the pin out configuration and Table 2-1
describes the function of each pin of the R65F11 and R65F12.
Figure 3-1 is a detailed block diagram.

......
v.

Table 2-1_
Signal
Name

R65F11 and R65F12 Pin Descriptions

Pin No.
R65F11

Pin No.
R65F12

Vee

21

50

Main power supply +5V

V RR

39

12

Separate power pin lor RAM.
In the event that Vee power
Is lost, this power retains
RAM data.

Vss

40

11

Signal and power ground (OV)

XTLI

2

10

Crystal or clock input for internal clock oscillator. Also
allows input of Xl clock signal If XTLO is connected to
Vss. or X2 or X4 clock H
XTLO Is floated •

XTLO

1

9

Crystal output from internal
clock oscillator.

20

41

The Reset input Is used to
in~lallze the R65Fll. This
signal must not transition from
low to high lor at least eight
cycles after Vee reaches operating range and the internal oscillator has stabilized.

3

13

Clock signal output at internal frequency.

22

51

A negative going edge on the
Non-Maskable Interrupt signal requests that a nonmaskable Interrupt be generated wkhln the CPU .

30-23
311-31

64-57
8-1

Two II-bit ports used for ekher
Input/output. Each line of
Ports A and B consist of an
active transistor to V 5S and
a passive pull-up to V ce.

PCO-PC7
AO-A3
A12, R/N
A13, EMS

4-11

25-32

PDO-PD7
A4-All
00-07

19-12

40-33

Port C has an active pull-up
transistor. Port D has active
pull-up and pull-down translstors. Ports C and D lines
form the external muHlp1exed
address and data bus to ailow externel mamory addressing.

cco,,,
OSCt.LATOA

v.
v.

PNJ4"A7(PAO PAl
POSITIVE PAi PAl
NEGATIVE EDGE DETECTS)
PlI(I..P87 (LATCHED INPUTS)

DSiPAO) (INPUT DATASTFIOBE)'

RES

1.0-1.3""2.
R/'IIA'3 tQ!J(PCOPC7)

,0\4-11.11 AD[)AIOO 07 OAT" BUS
(POO-P07)

_2

so (PAS)'
SI(PA7}'

NMI

• MUlTPLEXEO FUNCTION PINS

PAO-PA7
PBO-PB7

Figure 2-1. R65F11 and R65F12 Interface Diagram

PEO-PE7
PFO-PF7
PGO-PG4
PG5-PG7

3-38

Dascrlptlon

49-42
24-17
52-56,
14-16

On the R65F12, Port E may
be used lor output only. Polls
F and G are similar to Ports
A and B In construction and
may be used for Inputs or
outputs.

R65F11 • R65F12

FORTH Based Microcomputers

0155MA)(
(3
_____

OOT OR NOTCH

,~._"_,

TO LOCATE

,

«(125 ....)

T

L

(4151 MM)

(4lIOO MM)

2050 MAX
(SI30MM)

11 EQUAL SPACES

o 100 ~ TOl NONCUM
(254MM)

~

R65F11 Pin Out Designation

0500MAX

•,

L

TV>

I'''''··'
,-----,.I

40 PIN DIP

R65F11 Dimensional Outline

PI7
PIS

'AO
pA'

PBS

, ... 2

PI"

PI3

::~

P80

no

In
Vss

V~II

•

PA7
PQ"

PG3
PG2
POI
PGO

PGS
P06
PO?

Niii

PF3

PES

PF'1
PFI
PFS
PF4

:~~

'FO

~!

",3

~

r t'

PA3

PA4

:~:

Vec
PEO

'0

Q20TYP

(501 Mill)

...

,

I

(4131 . .)

PEl
PE2
PE3

Pl4

=~

iiiiii'

i!
.?,eII

=:

~--~~--------~--~
R65F12 Pin Out Designation

R65F12 Dimensional Outline
Figure 2-2.

Pin Out Configuration
3-39

+

J.

1180

r

(115MM)

0065

(055 Mill) 0022

(101 MY)

0040

(045MM)

0011

FORTH Based Microcomputers

R65F11 • R65F12

SECTION 3
SYSTEM ARCHITECTURE
This sectIOn provides a functional description of the R65F11
and R65F12. Functionally the R65F11 consists of a CPU,
RAM memory, two 8-bit parallel I/O ports (five in the 64-pin
R65F12), a serial I/O port, dual counter/latch circuits, a mode
control register, an interrupt fla9"enable dual register circuit,
and an internal Operating System. The kernel of FORTH in
ROM complements the system hardware. A block diagram
of the system is shown in Figure 3-1.

The stack can be envisioned as a deck of cards which may
only be accessed from the top. The address of a memory
location is stored (or "pushed") onto the stack. Each time
data are to be pushed onto the stack, the Stack Pointer is
placed on the Address Bus, data are written into the memory
location addressed by the Stack Pointer, and the Stack
POinter IS decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented by
1. The Stack Pointer is then placed on the Address Bus, and
data are read from the memory location addressed by the
Pointer.

NOTE

Throughout this document, unless specified
otherwise, all memory or register address locations are specified in hexadecimal notation.

The stack is located on zero page, i.e., memory locations
00FF-0040. After reset, which leaves the Stack POinter
indeterminate, normal usage calls for its initialization at OOFF.

3.1 CPU LOGIC

3.1.4 Processor Status Register

The R65F11 internal CPU is a standard 6502 configuration
wnh an 8-bit Accumulator register, two 8-bit Index Registers
(X and V); an 8-bit Stack POinter register, and AlU, a 16-bit
Program Counter, and standard instruction register/decode
and internal timing control logic.

The 8-bit Processor Status Register contains seven status
flags. Some of these flags are controlled by the user program; others may be controlled both by the user's program
and the CPU. The R6500 instruction set contains a number
of conditional branch instructions which are designed to allow
testing of these flags. See Appendix B for details.

3.1.1 Accumulator

3.1.5 Program Counter

The accumulator IS a general purpose 8-bit register that
stores the results of most arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used In these operations.

The 16-bit Program Counter prOVides the addresses that are
used to step the processor through sequential instructions
in a program. Each time the processor fetches an instruction
from program memory, the lower (least significant) byte of
the Program Counter (PCl) is placed on the low-order bits
of the Address Bus and the higher (most significant) byte of
the Program Counter (PCH) IS placed on the high-order 8
bits of the Address Bus. The Counter IS incremented each
time an instruction or data is fetched from program memory.

3.1.2 Index Registers
There are two 8-blt Index registers, X and Y. Each Index register can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the index register contents.
When executing an Instruction which specifies indirect
addreSSing, the CPU fetches the op code and the address,
and modifies the address from memory by adding the Index
register to it prior to loading or storing the value of memory.

3.1.6 Arithmetic And LogiC Unit (ALU)
Each bit of the AlU has two inputs. These Inputs can be tied
to various internal buses or to a loqic zero; the AlU then
generates the function (AND, OR, SUM, and so on) using
the data on the two inputs.

Indexing greatly simplifies many types of programs, especially those using data tables.

3.1.7 Instruction Register and Instruction Decode

3.1.3 Stack Pointer

Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These Instructions are latched into the
Instruction Register then decoded along with timing and
interrupt signals to generate control Signals for the various
registers.

The Stack Pointer is an 8-bit register. It is automatically
Incremented and decremented under control of the microprocessor to perform stack manipulation in response to either
user instructions, an internal IRQ interrupt, or the external
interrupt line NMI. The Stack Pointer must be initialized by
the user program.
The stack allows simple implementation of multiple level
interrupts, subroutine nesting and simplffication of many types
of data manipulation. The JSR, BRK, RTI and RTS instructions use the stack and Stack Pointer.

3-40

:::D

m
....
....

."

•

m
....N

."

'"~

."

o

~

''0
'MO

J:
aJ

ij

I»

CB(PA5)

CA

1
(P"'~l

l

SI(PA1)

~

C.

s:
n"

a

n

Figure 3-1. Detailed Block Diagram

o
3

"0
C

m

~
""'l
Ul

FORTH Based Microcomputers

R65F11 • R65F12
3.1.8 Timing Control

For the RAM to retain data upon loss of V cc , V RR must be
supplied within operating range and RES must be driven low
at least~t ~2 clock pulses before V cc falls out of operating
range. RES must then be held low while Vce is out of operating range and until at least eight ~2 clock cycles after Vec
is again wijhin operating range and the internal ~2 OSCillator
is stabilized. V RR must remain within Vec operating range
during normal operation. When Vec is out of operating range,
V RR must remain within the V RR retention range in order to
retain data. Figure 3-2 shows typical waveforms.

The Timing Control Logic keeps track of the specific instruc·
tion cycle being executed. This logic is set to TO each time
an instruction fetch is executed and is advanced at the
beginning of each Phase One clock pulse for as many cycles
as are required to complete the instruction. Each data transfer
which takes place between the registers is caused by
decoding the contents of both the instruction register and
timing control unit.

3.1.9 Interrupt Logic
RAM OPERATING MODE

Interrupt logic controls the sequencing of three interrupts;
RES, NMI and IRQ. IRQ is generated by anyone of eight
condijions: 2 Counter Overflows, 2 Positive Edge Detects,
2 Negative Edge Detects, and 2 Serial Port Conditions.

RAM RETENTION MODE

J: ~t~;~

:: 11°

3.2 CPU INSTRUCTION SET
The machine code instruction set of the R65F11 and R65F12
microcomputers are based on the popular R6500 microprocessor set. They contain all the instructions in the standard
R6502 sel, with the addition of the four new bit instructions
added to the R6511 processor family. Refer to Appendix A
for the Op Code mnemonics addressing matrix for details on
these instructions.

1
2
3
4
5

INITIAL APPLICATION OF Vcc AND VRR •
LOSS OF Vee. RAM ON STANDBY POWER.
REAPPLICATION OF Vee.
>8112 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
>8 \12 CLOCK PULSES.

Figure 3-2. Data Retention Timing

3.3 READ-ONLY-MEMORY (ROM)

3.5 CLOCK OSCILLATOR

The ROM consists of pre programmed memory with an
address space from F400 to FFFF. It contains the run time
kernel of the high level language Rockwell Single Chip
FORTH. There are 133 included functions stored in the
ROM. Codes are in the format of a two byte code field, which
identifies the interpreter assigned to execute that word, followed by a variable length Parameter Field, which contains
the instructions and data used by that interpreter according
to the programmed intention of that definition. See Appendix
o for a complete list of the names of all included words. All
words needed for support of the run time operation of dedicated applications programs are included. The RSC-FORTH
Operating System is also part of the ROM code and is
entered upon Reset. This Operating System allow the R65F11
and R65F12 to auto start a user program written in either
RSC-FORTH or Assembly language or enter a Development ROM if one is present. If no auto start program is found,
an attempt will be made to boot an operating program from
floppy disk.

A reference frequency can be generated with the on-chip
oscillator using an external crystal. The OSCillator reference
frequency passes through an internal countdown network
(divide by 2) to obtain the internal operating frequency (see
Figure 3-3a).
Internal timing can also be controlled by driving the XTLI pin
with an external frequency source. Figure 3-3b shows typical
connections. If XTLO is left floating. the external source is
divided by the internal countdown network. However, if XTLO
is tied to V ss, the internal coundown network is bypassed
causing the chip to operate at the frequency of the external
source.
The R65F11 and R65F12 operate in the CLOCK MASTER
mode. In this mode a frequence source (crystal or external
source) must be applied to the XTLI and XTLO pins.
NOTE: When operating at a 1 MHz internal frequency place
a 15-22 pF capaCitor between XTLO and GND.

3.4 RANDOM ACCESS MEMORY (RAM)
The RAM consists of 192 bytes of read/write memory with
an assigned page zero address of 0040 through OOFF. The
R65F11 and R65F12 provide a separate power pin (V RR )
which may be used for standby power for 32 bytes located
at 0040-005F. In the event of the loss of Vcc power, the
lowest 32 bytes of RAM data will be retained if standby power
is supplied to the V RR pin. If the RAM data retention is not
required then V RR must be connected to Vcc. During operation V RR must be at the Vee level.

02 is a buffered output signaLwhich closely approximates the
internal timing. When a common external source is used to
drive multiple devices the internal timing between devices as
well as their 02 outputs will be skewed in time. If skewing
represents a system problem it can be avoided by the
Master/Slave connection and options shown in Figure 3-4.
The R65F11 ~nd R65F12 is operated in the CLOCK MASTER
MODE. A second processor could be operated in the CLOCK

3-42

FORTH Based Microcomputers

R65F11 • R65F12

3.6 MODE CONTROL REGISTER (MCR)

SLAVE MODE. Mask options in the SLAVE unit convert the
~2 signal into a clock input pin which is tightly coupled to the

The Mode Control Register contains control bits for the mUltifunction VO ports and mode select bits for Counter A and
Counter B. Its setting, along w~h the setting of the Serial
Communications Control Register (SCCR), determines the
basic configuration of the R65F11 and R65F12 in any application. The Mode Control Register bit assignment is shown
in Figure 3-5. MCR Bits 7, 6, 5 must remain 1's in order for
ex1ernal memory referencing to be enabled.

internal timing generator. As a result the internal liming of the
MASTER and SLAVE units are synchronized with minimum
skew. If the 1112 signal to the SLAVE unit is inverted, the
MASTER and SLAVE UNITS WILL OPERATE OUT. OF
PHASE. This approach allows the two devices to share
external memory using cycle stealing techniques.

a

2-4 MHZ c::::J

TLI
R65F11

"NT

= 1 OR 2 MHZ

= 2X t'NT
XTLO
T
- 10-22 pF when using crystal :s 4MHz
a. Crystal Input
'EXT

MCR

Addr 0014

Vcc

CounterB
Mode Select

I I

300n
2-4 MHZ

XTLI
R65F11
NC

XTLO

"NT

= 1 OR 2 MHZ

'EXT

= 2X

BUI Mode Select

oo1_
1_

"NT

0- - 0 Interval Timer
0 - 1 Pulse Generation
10 Event Counter

1_
1 Pulse Width Meas
0 Interva' Timer
1 AsymmetriC Pulse Generation
0 Event Counter

1 R.tri..... bI. l"terY" Timer

Port B Latch
(1 = Enabled)
PortDT~'"

(0

o-

1-2 MHZ

X Norma'

=Trl .... H.... IrnpedInce Mode) not .......
t

1 ""NonMI
no!: allowed

1 - 0 Abbr. Busf
1_
1 Mux'd Bus

......_<1"'1 XTLI
"NT

= 1 OR 2 MHZ

R65F11
XTLO

'EXT

=

"NT

Figure 3-5. Mode Control Register

b. Clock Inputs

The use of Counter A Mode Select is shown in Section 6.1.
The use of Counter B Mode Select is shown in Section 6.2.

Figure 3-3. Clock Oscillator Input Options

The use of Port B Latch Enable is shown in Section 4.4.
R65F11 OR R65F12
XTLI
MASTER

112

(OUTPUT CLOCK)

XTLO

INVERTER USED
r-- --, WHEN SLAVE IS

~ 10-22 pF for using crystal
:s4MHz
6500/11, ETC.

I

,
I

L__

XTLI
SLAVE

I TO OPERATE

lOUT
OF PHASE WITH
MASTER

__ oJ

112
(INPUT CLOCK)

XTI..O

Figure 3-4. Master/Slave Connections

3-43

9

FORTH Based Microcomputers

R65F11 • R65F12
3.7 INTERRUPT FLAG REGISTER (IFR)
AND INTERRUPT ENABLE
REGISTER (IER)
An iRQ interrupt request can be initiated by any or all of eight
possible sources. These sources are all capable of being
enabled or disabled by the use of the appropriate interrupt
enabled bits in the Interrupt Enable Re~er (lER). Multiple
simultaneous interrupts will cause the IRO interrupt request
to remain active until all interrupting conditions have been
serviced and cleared.

IER

_'0012

IFR

Addr 0011

PAl PooIll..

Edge DeIect
PAl POIIa".

Edge_
PAZ ..........

Edge DeIect

The Interrupt Flag Register contains the information that
indicates which VO or counter needs attention. The contents
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge detect IFR bits may be
cleared in low level code by executing a RMB instruction at
address location 0010. The RMB X, (0010) instruction reads
FF, modifies bit X to a "0", and wr~es the modified value at
address location 0011. In this way IFR bits set to a "I" after
the read cycle of a Read-Modify-Write instruction (such as
RMB) are protected from being cleared. A logic "I" is ignored
when writing to edge detect IFR bits.

u_. .

PA3 NepII".

Edge_

Cool..... A

--

~ow .....

Cool......

FlIIg

XMTR
FIIIg

Figure 3-6. Interrupt Enable and Flag Registers

Each IFR bit has a corresponding bit in the Interrupt Enable
Register which can be set to a "I" by writing a "I" in the
respective bit position at location 0012. Individual IER bits
may be cleared by writing a "0" in the respective bit pos~ion,
or by RES. If set to a "1", an IRO will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag Register and Interrupt Enable Register bit assignments are shown
in Figure 3-6 and the functions of each bit are explained in
Table 3-1.

Table 3-1. Interrupt Flag Register Bit Codes
Bit
Code

Function

IFR 0:

PAO Positive Edge Detect Flag-Set to a "I" when a positive going edge is detected on PAO.
Cleared by RMB 0 (0010) Instruction or by RES.

IFR 1:

PAl PosibVe Edge Detect Flag-Set to a 1 when a poSItive going edge is detected on PAl.
Cleared by RMB 1 (0010) Instruction or by RES.

IFR 2:

PA2 Negative Edge Detect Flag-Set to a 1 when a negative going edge is detected on PA2.
Cleared by RMB 2 (0010) instruction or by RES.

IFR 3:

PA3 NegatIVe Edge Detect Flag-Set to 1 when a negative going edge is detected on PA3.
Cleared by RMB 3 (0010) Instruction or by RES.

IFR 4:

Counter A Underflow Flag-Set to a 1 when Counter A underflow occurs. Cleared by reading
the Lower Counter A at location 0018, by writing to address location 001A, or by RES.

IFR5:

Counter B Underflow Aag-Set to a 1 when Counter B underftow occurs. Cleared by reading
the Lower Counter B at location 001 C, by writing to address location 001 E, or by RES.

IFR 6:

Receiver Interrupt Flag-Set to a 1 when any of the Serial Communication Status Register bits
o through 3 IS set to a 1. Cleared when the Receiver Status bits (SCSR 0-3) are cleared or by
RES.

IFR 7:

Transmitter Interrupt Flag-Set to a 1 when SCSR 6 IS SlSt to a 1 while SCSR 5 IS a 0 or SCSR
7 is set to a 1. Cleared when the Transmitter Status bits (SCSR 6 & 7) are cleared or by RES.

3-44

R65F11 • R65F12

FORTH Based Microcomputers

3.8 OPERATING SYSTEM

Whether a warm or cold reset, the memory map is then
searched at every 1K byte boundary starting at location 0400
Hex. The first two bytes at each boundary are checked
against an A55A Hex bit pattern. This pattern indicates that
an auto start program is installed. The next two bytes are
assumed to point to the Parameter Field of the high level
RSC-FORTH word to be executed upon reset. This may be
the main function of a user defined program or the start up
routine of a Development ROM. Figure 3-7 details proper
alignment.

The system startup function, COLD, is executed upon Reset.
COLD, a high level FORTH word, forms the basis of the RSC
Operating System. Upon reset this function in~ializes the
R65Fli or R65F12 registers to establish the external 16K
byte memory map and disable all interrupt sources. It also
sets up the serial channel for 1200 baud (assuming a 1 MHz
internal clock) asynchronous transmission (seven bits, parity
disabled). The internal FORTH structure "W" is prepared for
use and the low level input/output vectors are forced to point
to the system serial channel routines. The FORTH User Area
Pointer, UP, is assigned the value 0300 Hex.

If no auto start ROM IS found, the Operating System turns
control over to a program that issues a "NO ROM" message
to the systems terminal via the serial channel and attempts
to boot a program from disk. A floppy disk controller, compatible with the WD1793 type, IS assumed to be present at
address 0100 Hex. The first half of Track 0 Sector 1 is loaded
from a double dens~ boot diskette Into RAM starting at
address 005F. When successfully loaded execution will be
turned over to this boot program.

A test is made of the variable CLD/WRM in memory location
030E. If this contains a value other than A55A Hex a cold
reset is assumed. In this case, the low level IRQ vector,
IRQVEC; the low level NMI Vector, NMIVEC, and the high
level interrupt vector, INTVEC, are all forced to point to the
system reset routine. ThiS prevents an unintentionally generated interrupt from crashing the system. System variables
TIB, RO, SO, UC/L, UPAD, UR/W and BASE are also initialized to their default values.

XX03
XX02
XXOI
XXOD

I~ I{..."="".
::

XX07
XX06
XX05
XX04
XX03
XX02
XX01
XXOO

0' WORD """".""

{AUTO START ROM PATTERN
lK BOUNDARY
AUTO START FORTH PROGRAM

TA
Te
fCC
To

AABB = ENTRY POINT ROUTINE
CCDD = XX06

~
TL

HHLL = XX04

f-A5{

AUTO START PATTERN

I-'=-

~

1K BOUNDARY
AUTO START MACHINE CODE PROGRAM

Figure 3-7. Auto Start ROM

3-45

DI

R65F11. R65F12

FORTH Based Microcomputers

SECTION 4
PARALLEL INPUT/OUTPUT PORTS
4.2 OUTPUTS

The R65F11 has 16 VO lines grouped into two a-bit ports
(PA, PB) and 16 lines programmed as an Address/Data bus
(PC & PO). Ports A and B may be used either for input or
output individually or in groups of any combination. The
R65F12 has 24 additional port lines grouped into three a-bit
ports (PE, PF, PG).

Outputs for Ports A and B are controlled by writing the
desired I/O line output states into the corresponding I/O port
register bit positions. A logic 1 will force a high (>2.4V)
output while a logic 0 will force a low «O.4V) output.

Multifunction VO's such as Port A are protected from normal
port 110 instructions when they are programmed to perform
a multiplexed function.

4.3 PORT A (PA)
Port A can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard parallel a-bit, bit independent, I/O port
or as serial channel 110 lines, counter VO lines, or an input
data strobe for the Port B input latch option. Table 4-3 tabulates the control and usage of Port A.

Internal pull-up resistors (FET's with an impedance range of
3K,s; Rpu ,s; 12K ohm) are provided on all port pins.
The direction of the VO lines are controlled by a-bit port registers located in page zero. This arrangement provides quick
programming access using simple twO-byte zero page
address instructions. There are no direction registers associated with the 110 ports, which simplifies I/O handling. The
I/O addresses are shown in Table 4-1.

Table 4-1.

In addition to their normal 110 functions, PAO and PAl can
detect positive going edges, and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate ah
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rate at which an edge can be detectb oj is onehalf the ~2 clock rate. Edge detection timing is shown in
Appendix F.4.

1/0 Port Addresses

Port

Address

A
B

0000
0001
0004
0005
0006

E
F
G

4.4 PORT B (PB)
Port B can be programmed as an a bit, bit independent I/O
port. It has a latched input capability which may be enabled
or disabled via the Mode Control Register (MCR). Table
4-2 tabulates the control and usage of Port B. An Input Data
Strobe signal must be provided thru PAO when Port B is programmed to be used with latched input option. Input data
latch timing for Port B is shown in Appendix F.4.

Appendix F.4 shows the I/O Port Timing.

4.1 INPUTS
Table 4-2.

Inputs for Ports A and B are enabled by loading logic 1 into
all I/O port register bit positions that are to correspond to
I/O input lines. A low «o.aV) input signal will cause a logic
o to be read when a read instruction is issued to the port
register. A high (>2.0V) input will cause a logic 1 to be read.
An RES signal forces all I/O port registers to logic 1 thus
initially treating all I/O lines as inputs.

Port B Control & Usage
Latch
Mode

110 Mode
MCR4

The status of the input lines can be interrogated at any time
by reading the I/O port addresses. Note that this will return
the actual status of the input lines, not the data written into
the I/O port registers.
Read/Modify/Write instructions can be used to modify the
operation of PA and PB. During the Read cycle of a Read!
Modify/Write instruction the Port I/O register is read. For all
other read instructions the port input lines are read. Read!
Modify/Write instructions are: ASL, DEC, INC, LSR, RMB,
ROL, ROR, and 5MB.

Pin
No.
R65Fll

Pin
No.
R65F12

38
37
36
35
34
33
32
31

8
7
6

5
4
3
2
1

=a

MCR4
(2)

Signal

Signal
Name

Type (1)

Name

Type

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

(1) Resistive pull-up, active buffer pull down
(2) Input data is stored in port B latch by PAD pulse

3-46

=1

R65F11 • R65F12

FORTH Based Microcomputers

Table 4-3.

Port A Control and Usage

PAO I/O

R65Fll/RS5F12
PORT!S)

~

MCR4

PORT B LATCH MODE

0

MCR4

SIGNAL

PAO( 2 )

1

~

SIGNAL

NAME

TYPE

NAME

TYPE

PAO

I/O

PORT B
LATCH STROBE

INPUTI')

PA1-PA31/0
PAl 12)
PA2 13 )
PA3 (3 )

SIGNAL
NAME

TYPE

PAl
PA2
PA3

1/0
I/O
I/O
COUNTER A 1/0

PA41/0

PA4

MCRO = 0
MCRI = 0
SCCR7 = 0
RCVR SIR MODE

MCRO = 1
MSRI = 0
SCCR7 = 0
RCVR SIR MODE

= 0 (4 )

SCCR7 ~ 0
seCR6 ~ 0
MCRI ~ 1

= 0 (4 )

(6)

SIGNAL

SIGNAL

SIGNAL

NAME

TYPE

NAME

TYPE

NAME

PA4

1/0

CNTA

OUTPUT

CNTA

I
I

TYPE
INPUT (1)

SERIAL 1/0 SHIFT REGISTER CLOCK
seCR7
SCCRS

=
~

1
1

RCVR SIR MODE

SIGNAL

SIGNAL

I

NAME

I

XMTR CLOCK

TYPE

NAME

OUTPUT

RCVR CLOCK

PAS

~
~

I
I

0
0

MCR3
MCR2

SIGNAL

~

0

=

1

MCR3
MCR2

TYPE

NAME

TYPE

NAME

PAS

1/0

CNTB

OUTPUT

CNTB

SERIAL 1/0
XMTR OUTPUT

PAS I/O
seCR7

=0

SCCR7

=

1

SIGNAL

SIGNAL
NAME

TYPE

NAME

TYPE

PA6

I/O

XMTR

OUTPUT
SERIAL I/O
RCVRINPUT

PA71/0
SCCR6

PA7

=0

SCCR6

SIGNAL

=

1

SIGNAL

NAME

TYPE

NAME

TYPE

PA7

I/O

RCVR

INPUT (1)

3-47

~

~

1
X

SIGNAL

SIGNAL

NAME

PA6

TYPE
INPUT (1)

COUNTER B 1/0

PAS I/O
MCR3
MCR2

= 1 (4)

(1)
(2)
(3)
(4)

I
I

TYPE
INPUT (1)

HARDWARE BUFFER FLOAT
POSITIVE EDGE DETECT
NEGATIVE EDGE DETECT
RCVR SIR MODE = 1 WHEN
SCCR6 • SCCRS • SCCR4 = 1
(5) APPLIES TO EITHER R65Fll
OR R65F12 PORT (SEE PIN
DIAGRAM)
(6) FOR THE FOLLOWING MODE
COMBINATIONS PA4 IS
AVAILABLE AS MJ INPUT
ONLY PIN.
SCCR7·SCCR6·SCCRS·
MCRI + S'CCR7 • SCCR6 •
SCCR4 • MCRI + SCCR? •
SCCR6 • SCCRS + SCCR?·
SCCR5 • SCCR4·

R65F11 • R65F12

FORTH Based Microcomputers

4.5 PORT C (PC)

4.6 PORT D (PD)

Port C is preprogrammed as part of the Address/Data bus.
PCO-PC7 function as AO-A3, A12, RIW, A13, and EMS,
respectively, as shown in Table 4-4. EMS (External Memory
Select) is asserted (low) whenever the internal processor
accesses memory area between 0100 and 3FFF. (See
Memory Map, Appendix C). The leading edge of EMS may
be used to strobe the eight address lines multiplexed on Port
D. See Appendix F.3-for Port C timing.

Port [j is also preprogrammed as part of the Address/Data
bus. Data bits DO through 07 are time mu~iplexed with
address bits A4 through A 11, respectively. Refer to the
Memory Maps (Appendix C) for Multiplexed memory assignments. See Appendix F.3 for Port 0 timing.

4.7 PORT E (PE~ PORT F (PF),
PORT G (PG)
Ports E, F and G are available on the R65F12 only. Port E
can only be used as outputs. Port F and Port G can be used
for Inputs or outputs and are similar to Port A and Port B in
operation.

Table 4-4.

Port C Control and Usage
Multiplexed
Mode
MCR7 = 1
MCR6 = 1

R65Fll1
R65F12
Port

Signal

peo
pel
PC2
PC3
PC4
PCS
pe6
PC7

Name

Type (1)

AO
Al
A2
A3
A12

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

RIW
A13
EMS

Table 4-5.

Port 0 Control and Usage
Multiplexed
Mode
MCR7
MCR6
MCR5

R65Fll1
R65F12
Port

Name

PD~

A4

POI
PD2
PD3
PD4
PD5
PD6
PD7

AS
A6
A7
AS
A9
AIO
All

=1
=1
=1

Signal

Signal

Phase 1

Phase 2
Type (2)

Name

Type (3)

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

DATAO
DATAl
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

(1) Active Buffer Pull·up and Pull-Down
(2) Tri·State Buffer is in Active Mode
(3) Tri·State Buffer is in Active Mode only during the Phase 2 Portion of a Wnte Cycle

3-48

FORTH Based Microcomputers

R65F11 • R65F12

SECTION 5
SERIAL INPUT/OUTPUT CHANNEL
The RS5Fll and RS5F12 Microcomputers provide a full
duplex Senal 1/0 channel with programmable bit rates and
operating modes. The serial I/O functions are controlled by
the Serial Communication Control Register (SCCR). The
SCCR bit assignment IS shown In Figure 5-1. The senal bit
rate IS determined by Counter A for all modes except the
Receiver Shift Register (RCVR SIR) mode for which an
external shift clock must be provided. The maximum data
rate uSing the Internal clock is S2.5K bits per second (@ {62
= 1 MHZ). The transmitter (XMTR) and receiver (RCVR) can
be independently programmed to operate In different modes
and can be independently enabled or disabled.

SCCR

ASYNCHRONOUS MODE WITHOUT PARITY

i PA~IH I

Addr 0015

!PA~ITY
a-Odd Parity
I_Even Parity
Parity Disable
1 Parity Enable
8 Bits/Char
1 - 7 Bits/Char
6 Bits/Char
1 _ 5 Bits/Char

a

a

a

a

o

I

2 STOP

;

2 STOP

2 $TOP

SHIFT REGISTER '-lODE 8 BIT OATA

WOAOM+ 1

aa-

SHIFT

~EGISTE~

ClOCk IP441

a XMTR & RCVR ASYN Mode
1 XMTR ASYN, RCVR SIR
X XMTR SIR, RCVR ASYN

Figure 5-2. Bit Allocations

In the SIR mode. eight data bits are always shifted out. Bltsl
character and panty control bits are Ignored The senal data
IS shifted out via the SO output (PAS) and the shift clock IS
available at the CA (PA4) pin. When the transmitter underruns In the SIR mode the SO output and shift clock are held
In a high state.
'

o

RCVR Disable
1 RCVR Enable

a xMTR Disable
1 XMTR Enable

Figure 5-1_ Serial Communication Control Register

The XMTR Interrupt Flag bit (IFR7) IS controlled by Senal
Communication Status Register bits.' SCCR5, SCCRS and
SCCR7.

Except for the Receiver Shift Register Mode (RCVR SIR), all
XMTR and RCVR bit rates will occur at one sixteenth of the
Counter A Interval timer rate. Counter A IS forced Into an
Interval timer mode whenever the senal 1/0 IS enabled In a
mode requiring an Internal clock.

IFR7

Whenever Counter A IS reqUired as a timing source It must
be loaded with the hexadeCimal code that selects the data
rate for the senal 1/0 Port Refer to Counter A (paragraph
S.l) for a table of hexadeCimal values to represent the deSired
data rate.

=

SCSRS (SCCRS + SCCR7)

5.2 RECEIVER OPERATION (RCVR)
The receiver and its selected control and status functions are
enabled when SCCR-S is set to a "1." In the ASYN mode,
data format must have a start bit, appropriate number of data
bits, a panty bit (If enabled) and one stop bit. Refer to Figure
5-2 for a diagram of bit allocations. The receiver bit period
IS divided into 8 sub-intervals for Internal synchronization.
The receiver bit stream is synchronized by the start bit and
a strobe signal IS generated at the approximate center of
each Incoming bit. Refer to Figure 5-3 for ASYN Receive
Data Timing. The character assembly process does not start
if the start bit signal IS less than one-half the bit time after a
low level is detected on the Receive Data Input. Framing
error, over-run, and parity error conditions or a RCVR Data
Register Full will set the appropriate status bits, and any of
the above conditions will cause an Interrupt Request if the
Receiver Interrupt Enable bit is set to logic 1.

5.1 TRANSMITTER OPERATION (XTMR)
The XTMR operation and the transmitter related control!
status functions are enabled by bit 7 of the Senal Communications Control Register (SCCR). The transmitter, when In
the Asynchronous (ASYN) mode, automatically adds a start
bit, one or two stop bits, and, when enabled, a parity bit to
the transmitted data. A word of transmitted data (In asynchronous parity mode) can have 5, S, 7, or 8 bits of data.
The nine data modes are shown below. When panty is diSabled, the 5, 6, 7 or 8 bits of data are terminated with two
stop bits.
3-49

R65F11 • R65F12

FORTH Based Microcomputers
received data has a panty error ThiS bit IS cleared
by reading the Receiver Data Register or by RES.

Serial
Input -'1:,.--..".,..c:~c::::::::=r=:JIC-:::=r=1
Shirt BII

LSB

=-:::rl

SCSR 3: Frammg Error-Set to a logiC 1 when the received
data contains a zero bit after the last data or panty
bit In the stop bit slot. Cleared by reading the
Receiver Data Register or by RES. (ASYN Mode
only).
SCSR 4: Wake-Up-Set to a logiC 1 by wntlng a "1" In bit
4 of address: 0016. The Wake-Up bit IS cleared by
RES or when the receiver detects a stnng of ten
consecutive 1'so When the Wake-Up bit IS set
SCSRO through SCSR3 are Inhibited.

Stop BII Stap Bit

• Serlal Input Data Shifted In

Figure 5-3. ASVN Receive Data Timing

SCSR 5: End of Transmission-Set to a logiC 1 by wnllng
a "1" in bit position 5 of address: 0016. The End
of Transmission bit IS cleared by RES or upon
writing a new data word Into the Transmitter Data
Register. When the End-of-Transmisslon bit IS true
the Transmitter Register Empty bit is disabled until
a Transmitter Under-Run occurs.

In the SIR mode, an external shift clock must be provided at
CA (PA4) pin along with 8 bits of serial data (LSB first) at the
SI input (PA7). The maximum data rate using an external
shift clock is one'elghth the internal clock rate. Refer to
Figure 5-4 for SIR Mode Timing.

SCSR 6. Transmitter Data Register Empty-Set to a logiC
1 when the contents of the Transmitter Data RegIster IS transferred to the Transmitter Shift RegIster. Cleared upon wntlng new data Into the
Transmit Data Register. ThiS bit IS Initialized to a
logiC 1 by RES.
SCSR 7. Transmitter Under-Run-Set to a logiC 1 when the
last data bit IS transmitted If the transmitter IS In a
SIR Mode or when the last stop bit IS transmitted
If the XMTR IS In the ASYN Mode while the Transmitter Data Register Empty Bit IS set. Cleared by
a transfer of new data Into the Transmitter Shift
Register, or by RES.

~~~'::, .....I--,---r--< ..- -....-:--,--"T"---"
Oa18 Out

• Senal Input Data Shifted In
•• Serial Output Data Makes TransItion

Figure 5-4. SIR Mode Timing
A RCVR interrupt (IFR6) IS generated whenever any of
SCSRO-3 are true.

SCSRI

7

I

6

I

5

I

5.3 SERIAL COMMUNICATION STATUS
REGISTER (SCSR)

4

I I I' 1 J
l

l

2

3

0

Addr 0016

RCVR Oa'a
Rag Full

RCVR Over·Run

The Serial Communication Status Register (SCSR) holds
Information on vanous communication error conditions, status
of the transmitter and receiver data registers, a transmitter
end-of-transmlsslon condition, and a receiver Idle line condition (Wake-Up Feature). The SCSR bit aSSignment is shown
in Figure 5-5. Bit assignments and functions of the SCSR are
as follows:

Parity Error
Frame Error

Wake-Up
End of Transmi'sion

XMTR Oa,a Reg Empty

SCSR 0: Receiver Data Register Full-Set to a logic 1 when
a character IS transferred from the Receiver Shift
Register to the Receiver Data Register. ThiS bit IS
cleared by reading the Receiver Data Register, or
by RES and IS disabled If SCCR 6 = O. The SCSR
bit will not be set to a logiC 1 If the received data
contains an error condition, however, a corresponding error bit Will be set to a logiC 1 Instead.

XMTR Under-Run

Figure 5-5.

SCSR Bit Allocations

5.4 WAKE-UP FEATURE

o

In a multl-dlstnbuted microprocessor or microcomputer applications, a destonatlon address IS usually Included at the
beginning of the message. The Wake-Up Feature allows
non-selected CPU's to Ignore the remainder of the message
until the beginning of the next message by setting the WakeUp bit. As long as the Wake-Up flag IS true, the Receiver
Data Register Full Flag remains false. The Wake-Up bit IS
automatically cleared when the receiver detects a stnng of
ten consecutive l's which Indicates an Idle transmit line.
When the next byte IS received, the Receiver Data Register
Full Flag Signals the CPU to wake-up and read the received
data.

SCSR 1: Over-Run Error-Set to a logiC 1 when a new character IS transferred from the Receiver Shift RegIster, With the last character still In the Receiver
Data Register. ThiS bit IS cleared by reading the
Receiver Data Register, or by RES
SCSR 2. Panty Error-Set to logiC 1 when the RCVR IS In
the ASYN Mode, Panty Enable bit IS set, and the
3-50

R65F11 • R65F12

FORTH Based Microcomputers

SECTION 6
COUNTER/TIMERS
The R65Fll and R65F12 Microcomputers contain two 16-bit
counters (Counter A and Counter B) and three 16-bit latches
associated wjth the counters. Counter A has one 16-bit latch
and Counter B has two 16-bit latches. Each counter can be
independently programmed to operate in one of four modes:

Counter A

Upper Latch A before the contents of the 16-bit latch are
transferred to Counter A. Counter A is set to the latch value
whenever Counter A underflows. When Counter A decrements from 0000 the next counter value WII! be the latch
value, not FFFF, and the Counter A Underflow Flag (IFR 4)
Will be set to "1". ThiS bit may be cleared by reading the
Lower Counter A at 10callOn 0018, by writing to address
location 001 A, or by RES.

Counter B
• Retnggerable Interval Counter
• Asymmetncal Pulse
Generation
• Interval Timer
• Event Counter

• Pulse width
measurement
• Pulse Generation
• Interval Timer
• Event Counter

Counter A operates in any of four modes. These modes are
selected by the Counter A Mode Control bits in the Control
Register. See Table 6-1.

Table 6·1. Counter A Control Bits
Operating modes of Counter A and Counter B are controlled
by the Mode Control Register. All counting begins at the
Initialization value and decrements. When modes are selected
reqUiring a counter Input'output line, PA4 IS automatically
selected for Counter A and PAS IS automatically selected for
Counter B (see Table 4.2).

Counter A consists of a 16-blt counter and a 16-blt latch
organized as follows: Lower Counter A (LCA), Upper Counter
A (UCA), Lower Latch A (LLA), and Upper Latch A (ULA).
The counter contains the count of either \12 clock pulses or
external events, depending on the counter mode selected.
The contents of Counter A may be read any time by execuhng a read at location 0019 for the Upper Counter A and
at location 001A or location 0018 for the Lower Counter A.
A read at location 0018 also clears the Counter A Underflow
Flag (IFR4).

0

1
1

1. When the Counter IS decremented from 0000, the next
Counter value IS the Latch value (not FFFF).
2. When a write operallOn IS performed to the Load Upper
Latch and Transfer Latch to Counter address 001 A,
the Counter IS loaded With the Latch value. Note that
the contents of the Accumulator are loaded Into the
Upper Latch before the Latch value IS transferred to
the Counter.
The Counter value is decremented by one count at the !62
clock rate. The 16-blt Counter can hold from 1 to 65535
counts The Counter Timer capacity IS therefore 11-'s to 65 535
ms at the 1 MHz \12 clock rate or 0.5 !'-s to 32.767 ms at the
2 MHz \12 clock rate. Time Intervals greater than the maxImum Counter value can be eaSily measured by counting
IRQ Interrupt requests In the counter IRQ Interrupt routine.

I

COUNTER UNDERFLOW

I

COUNTER'--'----'_....:....--'_-'---''---'----'II-',=.;UL;:...L=C),_IL...!.::,U",L.",,",,-I'..:.'LI_

COUNTER UNDERFLOW FLAG

1
1

Mode
Interval Timer
Pulse Generation
Event Counter
Pulse Width Measurement

In the Interval Timer mode the Counter IS 1000lalized to the
Latch value by either of two conditions:.

.2

)ET ANY nME BEFORE
COUNTER UNDEAFLOW

0

6.1.1 Interval Timer

Counter A can be started at any time by writing to address:
001 A. The contents of the accumulator Will be copied Into the

I

0
0

The Counter IS set to the Interval Timer Mode (00) when a
RES Signal IS generated.

The 16-blt latch contains the counter Initialization value, and
can be loaded at any time by executing a write to the Upper
Latch A at location 0019 and the Lower Latch A at location
0018. In either case, the contents of the accumulator are
copied Into the applicable latch register.

COUNTER INTERRUPT ENABLED

MCRO
(bit 0)

The Interval Timer, Pulse GenerallOn, and Pulse Width Measurement Modes are ~2 clock counter modes. The Event
Counter Mode counts the occurrences of an external event
on the CNTR line.

6.1 COUNTER A

I

MCRl
(bit 1)

I
I
1

10---:-------

When Counter A decrements from 0000, the Counter A
UnderflOW (IFR4) IS set to logiC 1. If the Counter A Interrupt
Enable Bit (IER4) is also set, an IRQ interrupt request will be
generated. The Counter A Underflow bit in the Interrupt Flag
Register can be examined in the IRQ interrupt routine to
determine that the IRQ was generated by the Counter A
Underflow.

I
Figure 6·1. Interval Timer Timing Diagram
3-51

R65F11 • R65F12

FORTH Based Microcomputers

While the timer IS operating In the Interval Timer Mode, PA4
operates as a PA I/O bit.

The Counter A underflow flag will be set only when the count
In the timer reaches zero. Upon reaching zero the timer Will
be loaded with the latch value and continue counting down
as long as the CA pin IS held low. After the counter is stopped
by a high level on CA, the count will hold as long as CA
remains high. Any further low levels on CA will again cause
the counter to count down from its present value. The state
of the CA line can be determined by testing the state of PM.

A timing diagram of the Interval Timer Mode IS shown In
Figure 6-1.

6.1.2 Pulse Generation Mode
In tile Pulse Generation mode, the CA line operates as a
Counter Output. The line toggles from low to high or from
high to low whenever a Counter A Underflow occurs. or a
write IS performed to address 00IA.

A timing diagram for the Pulse Width Measurement Mode is
shown in Figure 6-3.

The normal output waveform IS a symmetrical square·wave.
The CA output IS Inillalized high when entering the mode and
transitions low when writing to 001 A.

112

I-- T
-1 2.0V

PDSU

CNTR

Asymmetric waveforms can be generated If the value of the
latch IS changed after each counter underflow.

COUNT

A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one
occurrence of the output toggle condition.

N

I

N-1

N-3

N·2

Figure 6·3. Pulse Width Measurement

6.1.3 Event Counter Mode
In thiS mode the CA is used as an Event Input line, and the
Counter will decrement with each rising edge detected on
thiS line. The maximum rate at which thiS edge can be
detected IS one-half the ~2 clock rate.

6.1.5 Serial I/O Data Rate Generation
Counter A also provides clock timing for the Serial I/O which
establishes the data rate for the Serial I/O port. When the
Serial I/O is enabled, Counter A is forced to operate at the
Internal clock rate. Counter A IS not required for the RCVR
SIR mode. The Counter I/O (PA4) may also be reqUired to
support the Serial I/O (see Table 4-2).

The Counter can count up to 65,535 occurrences before
underflowlng. As In the other modes, the Counter A Underflow bit (IER4) IS set to logiC 1 If the underflow occurs.
Figure 62 IS a timing diagram of the Event Counter Mode.

Table 6-2 identifies the values to be loaded in Counter A for
selecting standard data rates with a ~2 clock rate of 1 MHz
and 2 MHz. Although Table 6-2 identifies only the more
common data rates, any data rate from 1 to 62.5K bps can
be selected by using the formula:

N =

16

x bps

-1

where
N
Figure 6·2. Event Counter Mode

~2
bps

6_1.4 Pulse Width Measurement Mode

deCimal value to be loaded Into Counter A uSing
its hexadecimal equivalent.
the clock frequency (1 MHz or 2 MHz)
the desl red data rate.
NOTE

ThiS mode allows the accurate measurement of a low pulse
duration on the CA line. The Counter decrements by one
count at the ~2 clock rate as long as the CA line is held In
the low state. The Counter IS stopped when CA IS In the high
state

In Table 6-2 you Will notice that the standard data rate
and the actual data rate may be slightly different.
Transmitter and receiver errors of 1.5% or less are
acceptable. A revised clock rate is included in Table
6-2 for those baud rates which fall outside this limit.

3-52

R65F11 • R65F12

FORTH Based Microcomputers
occurs on the CB pin (PA5). The Counter B Interrupt flag Will
be set If the counter underflows before a positive edge occurs
on the CB line. Figure 6-4 Illustrates the operation.

Table 6-2. Counter A Values for Baud Rate Selection

I
Standard
Baud
Rate
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600

Hexadecimal
Value

Actual
Baud
Rate At

Clock Rate
Needed
To Get
Standard
Baud Rate

1 MHz 2 MHz

1 MHz

2 MHz

1 MHz 2 MHz

04E1
0340
0237
01AO
OOCF
0067
0033
0019
0010
OOOC
0008
0006

50.00
7503
110.04
149.88
30048
600.96
120192
2403.85
367647
480769
6944.44
8928.57

50.00
74.99
110.04
150.06
299.76
600.96
1201.92
2403.85
3676.47
480769
735294
961538

10000
1.0000
1.0000
10000
1.0000
10000
1.0000
10000
09792
10000
10368
10752

09C3
0682
046F
0340
01AO
OOCF
0067
0033
0021
0019
0010
OOOC

20000
20000
2.0000
2.0000
20000
2.0000
20000
2.0000
1.9584
20000
1.9584
20000

CB LINE
COUNTER
UNDERFLOWS

RESET BY
4 / SOFTWARE

COUNTERB----------~~L-------­
FLAG

Figure 6-4. Counter B. Retriggerable Interval Timer Mode
6.2.2 Asymmetrical Pulse Generation Mode

6.2 COUNTER B

Counter B has a special Asymmetrical Pulse Generation
Mode whereby a pulse train with programmable pulse Width
and period can be generated without the processor IntervenlIOn once the latch values are Initialized.

Counler B con~lsts of a 16-blt counter and two 16-bIt latches
organized as follows Lower Counter B (LCB), Upper Counter
B (UCB), Lower Latch B (LLB), Upper Latch B (ULB), Lower
Latch C (LLC), and Upper Latch C (ULC). Latch C IS used
only In the asymmetrical pulse generallOn mode. The counter
contains the count of either ~2 clock pulses or external
events depending on the counter mode selected. The contents of Counter B may be read any time by executing a read
at location 0010 for the Upper Counter B and at location
001 E or 001 C for the Lower Counter B. A read at location
001 C also clears the Counter B Underflow Flag.

In thiS mode, the 16-blt Latch B IS Initialized with a value
which corresponds to the duration between pulses (referred
to as 0 In the follOWing descriptIOns). The 16-bit Latch C IS
Initialized with a value which corresponds to the desired
pulse width (referred to as P In the follOWing descrlpllOns)
The initialization sequence for Latch Band C and the starting
of a counting sequence are as follows.
1. The lower 8 bits of P are loaded Into LLB by writing to
address 001 C, and the upper 8 bits of P are loaded
Into ULB and the full 16 bits are transferred to Latch
C by writing to address location 001 D. At thiS pOint
both Latch B and Latch C contain the value of P.

Latch B contains the counter InitlalizallOn value, and can be
loaded at any time by executing a write to the Upper Latch
B at location 0010 and the Lower Latch B at location 001 C
In each case, the contents of the accumulator are copied Into
the applicable latch register

2. The lower 8 bits of 0 are loaded Into LLB by writing to
address 001 C, and the upper 8 bits of 0 are loaded
Into ULB by writing to address location oo1E. Writing
to address locallOn 00 1E also causes the contents of
the 16-blt Latch B to be downloaded Into the Counter
B and causes the CB output to go low as shown In
Figure 6-5.

Counter B can be Initialized at any time by writing to address.
001 E The contents of the accumulator IS COPied Into the
Upper Latch B before the value In the 16-bIt Latch B IS transferred to Counter B. Counter B Will also be set to the latch
value and the Counter B Underflow Flag bit (IFR5) Will be set
to a "1" whenever Counter B underflows by decrementing
from 0000.

3. When the Counter B underflow occurs the contents of
the Latch C IS loaded Into the Counter B, and the CB
output toggles to a high level and stays high until
another underflow occurs. Latch B IS then down-loaded
and the CB output toggles to a low level repeating the
whole process.

IFR 5 may be cleared by reading the Lower Counter B at
location 001 C, by writing to address location 001 E, or by
RES.
Counter B operates In the same manner as Counter A In the
Interval Timer and Event Counter modes. The Pulse Width
Measurement Mode IS replaced by the Retriggerable Interval
Timer mode and the Pulse Generation mode is replaced by
the Asymmetrical Pulse Generation Mode.

6.2.1 Retriggerable Interval Timer Mode

1 AND 3. COUNTER B -

LATCH B (D)

When operating In the Retnggerable Interval Timer mode,
Counter B IS Initialized to the latch value by wntlng to address
001 E, by a Counter B underflow, or whenever a positive edge

2 AND 4. COUNTER B _

LATCH C (P)

Figure 6-5.
3-53

Counter B Pulse Generation

FORTH Based Microcomputers

R65F11 • R65F12

SECTION 7
POWER ON/INITIALIZATION CONSIDERATIONS
7.1 POWER-ON-RESET

·5------

_--------~~----

Vcco~
-"'POWER ON

The occurrence of RES going from low to high will cause the
R65F11 or R65F12 to reset and enter the RSC-FORTH
Operating System. As was described in Section 3.8, upon
reset certain system variables will be initialized. See Appendix
C.4 for a list of these variables names, locations and contents. The ex1ernal memory map will be searched for an auto
start ROM.

XTLO~lJUU1IU1J1JUlMIlJUl.J1
I-CLOCK
--l
STABILIZATION
TIME

.2~JUl.JLJl.JlJlJ1

I;UL~C~

CYC~

RES

A bit pattern of A55A at a 1K byte page boundary indicates
that an auto start program follows. The next two bytes are
assumed to be a pointer to the high level RSC-FORTH word
that is the entry point to that program. Auto start programs
is written in assembly language, rather than RSC-FORTH,
a series of indirect pointers as shown in 3-7 can be used to
initiate program execution.

Figure 7·1.

Power Turn·On Timing Detail

7.3 RESET (RES) CONDITIONING
When RES is driven from low to high the R65F11 or R65F12
is put in a reset state. The registers and 1/0 ports are configured as shown in Table 7-1 when the external ROM is
autostarted.

Table 7·1. RES Initialization of I/O Ports and Registers

7.2 POWER ON TIMING
After application of Vcc and V RR power to the R65F11 or
R65F12, RES must be held low for at least eight ~2 clock
cycles after Vee reaches operating range and the internal
oscillator has stabilized. This stabilization time is dependent
upon the input Vee voltage and performance of the internal
oscillator. The clock can be monitored at ~2 (pin 3). Figure
7-1 illustrates the power turn-on waveforms. Clock stabilization time is typically 20 ms.

REGISTERS
Mode Control (MCR)
Int. Enable (IER)
Int. Flag (I FR)
Ser. Com. Control (SCCR)
Ser. Com. Status (SCSR)
PORTS
PA Latch
PB Latch

3-54

5

4

3

2

1

0

1

1

0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0

0
0
0
0
0

0
0
0
0
0

1
1

1
1

1
1

1
1

1
1

7

6

1
0
0

0

1
1

0
0
0
0

1
1

1
1

1
1

1

1

FORTH Based Microcomputers

R65F11 • R65F12

APPENDIX A
R65F11 AND R65F12 INSTRUCTION SET
This appendix contains a summary of the R6500 Instruction
set. For detailed information, consult the R6500 Microcomputer System Programming Manual, Document 29650 N30.
The four instructions notated with a " are added instructions
for the R65F11 and R65F12 which are not part of the standard 6502 instruction set.

A.1 INSTRUCTION SET IN ALPHABETIC SEQUENCE
Mnemonic

Instruction

Mnemonic

ADC
AND
ASL

Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)

LDA
LDX
LDY
LSR

Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or
Accumulator)

Nap

No Operation

ORA

"OR" Memory with Accumulator

PHA
PHP
PLA
PLP

Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack

"RMB
ROL

Reset Memory Bit
Rotate One Bit Left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine

"BBR
"BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS

Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits In Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Ovelilow Clear
Branch on Ovelilow Set

CLC
CLD
CLI
CLV
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable
Clear Ovelilow Flag
Compare Memory and
Compare Memory and
Compare Memory and

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

EaR

"Exclusive-Or" Memory with
Accumulator

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Index Y by One

JMP
JSR

Jump to New Location
Jump to New Location Saving Return
Address

Instruction

ROR
Bit
RTI
RTS

Accumulator
Index X
Index Y

Subtract Memory from Accumulator with
Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator In Memory
Store Index X in Memory
Store Index Y in Memory

SBC
SEC
SED
SEI
"SMB
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA

Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator

I

I

3-55

I

A.2 R65F11 AND R65F12 INSTRUCTION SET SUMMARY TABLE

m
....

."

INSTRUCTIONS
IIMMEDlATEIABsoLuTE!zERO PAGEl ACCUM
MNEMONIC

ADC
AND
AS'-

OPERATION
A M C---A

l4)i1)

A M-A

("
C-~~-(J

I

IMPLIED

op I n 1/1 lop I n I /; I op! n I /; lop In! /; I op I n III IOP\ n 1 /; lop! n I /; lop I n I /; lop \ n
60 I 4
69
6'
4
"1 55 1'I'51
65
25 3 2
31
2 35 4 1'I'DI4
2 3D
'9
'0
06 5 2 lOA I 2 I 1
16 6 2 lE
DE

BBS{#{O-71)

Branch on M. ' 1

Branch on C- 0
Branch on C - 1

ClI

CLV
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
INX

~

'"

I'NY
JMP
JSR
LDA
LDX
LDY
LSR
NOP

ORA
PHA
PHP
PLA
PLP

(2)
(2)
(2)

Branch on 1/- 0

(2)

Branch on 1/ - I

'"

....,

ROL
ROR
RTI
RTS

sse

SEC
SED
SEI

00
30
10
50
70

0--·1

A M (1)

XM
YM

EO 2 2 EC
CTITD
C022CC

CE

'~M

csl
E4
C4
C6

X I-X

I_Y
(1)

A'No-I-.

49

I 2 I 2 I 40

M 1-M

EE

X 1 -~X
Y l_Y
Jump to New Loc

4C

'0
2 I AD 14

4,1
E6

Cll 6

3

."

~~I

,,

, I'

T
2
2

I

09

I 2 12 100 J 4 I 31 051 3 12

rr:==9J -

O-~
No OperatIon
AVM-A(l)

411 61 2

AS
A6

All 6

I

51

I

5

4

1 2 I DO I 4 I

I 2 I 55
F6

I

2

3 109

2

2
2

2

~1 ~ I;

56
EA 12 11

011 61 2 I 11 I 5 I 2 I 151 4 I 2 110 I 4 I 3 I 19 I 4
08
48
68
28

Ms-P

3
3

4

..111

'E I 6 13 1 ' 6 I T n l l

RIm Sub

A M C-A

(1) (4)

E9 I 2 I

J I

ED I 4 I 3! E5

3

2

:~

38
Fa
78

'-C

'-0
,_T
(5)

~~I:I~IEI~I~IIII

NOTES
Add 1 to N If page boundary IS crossed
Add 1 to N II branch occurs to same page
Add 2 to N II branch occurs to different page
3 Carry not == Borrow
4 It In decimal mode Z flag IS invalid
accumulator must be checked on zero resull
5 Effects a-blt data field of the specified zero page address

~

C
C
C

z
z
z
z C

N •

13

• Z

1
1

N •

: I EL I
1
1
1

J,I, J~ ~ ~ I:~: ~
I

18'161'1"161'1 :

l
2
2
2

.....

o .
• 0

I

I

I:I: I

I

37 1471 57

I

iRestoredl

Z

67 \77\ .

("""o,ed) .

1 31 F91 4 13

19D 51 31

I~
.1 ~
:::r:
'1
-

N v

Z i31

m

<

15 1 3

96

1 4 I, 18'1"1 A'I B'

r'l

I»

:I p=Co

D'I E'I"I

AA ,
A8 ,
8A
BA
9A
98

en

• Z

1

14 1'1

2
2
2

en

I\)

I 1 1 1 1 1 1 I~

071 17! 27
6E6366S26A21

1 0

N
N
N
N
N

(5)

~
Rtrn Int

•

o .
N •
N
N
N

~~!~1;1591413

BE 14 13

2

2

I 4 13

I B1 1 5 1 z I 851 4 I 2 I BO I 4 I 3 189 1 4 13

4A I 2 I ,

A-Ms S 1-5
P-Ms S 1-5
S 1-5 Ms-A
S 1--5

I 051

B4

:~1:1;1:~15

C

2

3

MM••

6C 1513\

10.0

2

1 01 I 5 I

5 4

2

~: 1 ~ !~

M-Y

(1)

2

~: I~ I~

,I,

A9
A2

AE

I

6

;;1 !~I~: I~~I ~~I·:: I;;

06161zl[lE1713

Jump Sub
M-A (t)
M-X (1)

A-M
X-M
Y-M
A-X
A-Y
$-oX
X_A
X-S
Y-A

Z C
Z
Z C

08
2 1
'81'1'
58 2 1
88 2 1

0--0

5MB[#(O-7Jj t-M.

STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA

BO
FO

O-V

Rt.1B[#(O-711 O-Mo

loPI n 1 II I 0

N

0017 11

O-C

7INV-BDIZC

I7

BIT ADDRESSING (OP BY BIT #)

N V

2C14l3/241312

Branch on N = 1
Branch on Z- 0
Branch on N ~ 0

II

PAGE, Y I

...a.

•:::D

CODes

;~ I: I;
90

AAM

y

lop! n III lop I n III \ OP I n I

(5)(2)
(2)
(2)
(2)

Branch on Z - 1

M

\11

"

1 1'

BBR[#(O-?ll BranCh on M. =0 (S)(2)

BCC
BCS
BEO
B'T
BMI
BNE
BPL
BRK
BVC
BVS
CLC
CLD

R65Fll AND R65F12 ADDRESS MODES
I (IND. X) I (INO), Y Iz PAGE, X I ASS, X
A8S, Y I RELATIVE I INOtRECT I Z

PROCESSOR STATUS

3:

N •
1
1
1

LEGEND
Index X
X
Index Y
Y
Accumulator
A
Memory per effective address
M
Memory per stack pOinter
M,
Selecter zero page memory bit
M.
Memory Bit 7
M,

M.

N

•

N

•

~ I ...0

(1;"

• Z

Memory 81t 6
Add
Subtract
And

V

0<

#

ExcluSIve Or
Number of cycles
Number of Bytes

(')

0

3

"0
I:

...

CD
(I)

FORTH Based Microcomputers

R65F11 • R65F12

A.3 INSTRUCTION CODE MATRIX

9

A

BRK
ORA
Implied (IND, X)
1 7
2 6

ORA
ZP
2 3

ASL
ZP
2 5

RMBO
ZP
2 5

PHP
Impll8d
1 3

ORA
IMM
2 2

ASL
Accum
1 2

BPL
ORA
Relative (IND). Y
2 5'
2 2"

ORA
Zp, X
2 4

ASL
Zp, X
2 6

RMBl
ZP
2 5

CLC
Implied

1 2

ORA
ABS, Y
3 4'

AND
ZP
2 3

ROL
ZP
2 5

RMB2
ZP
2 5

PLP
Imphed
1 4

AND
IMM
2 2

Relative (IND, Y)
2 5'
2 2"

AND
Zp, X
2 4

ROL
ZP, X
2 6

RMBJ
ZP
2 5

SEC
Imphed
1 2

AND
ABS,Y
3 4'

RTI
EOR
Imphed (IND, X)
1 6
2 6

EOR
ZP
2 3

LSR
ZP
2 5

RMB4
ZP
2 5

PHA
Impll8d
1 3

EOR
IMM
2 2

EOR
ZP, X
2 4

LSR
ZP, X
2 6

RMB5
ZP
2 5

CLI
Imphed
1 2

EOR
ABS,Y
3 4'

RTS
ADC
Imphed (IND,X)
1 6
2 6

ADC
ZP
2 3

ROR
ZP
2 5

RMB6
ZP
2 5

PLA
Imphed
1 4

ADC
IMM
2 2

BVS
ADC
RelatIVe (IND, Y)
2 2"
2 5'

ADC
Zp, X
2 4

ROR
ZP, X
2 6

RMB7
ZP
2 5

SEI
Implied
1 2

ADC
ABS, Y
3 4'

2

JSR
AND
Absolute (IND, X)
3 6
2 6
BMI

BVC

3

4

BIT
ZP
2 3

AND

EOR

Relative (IND), Y
2

2'·

BCC

2

5'

A

B

C

o
E

F

2"

ROL
Accum
1 2

BIT
ABS
3 4

JMP
ABS
3 3

LSR
Accum
1 2

ROR
Accum
1 2

JMP
Indirect
3 5

STA

STY
ZP, X
2 4

STA
ZP, X
2 4

STX
ZP, Y
2 4

5MBl
ZP
2 5

TYA
Imphed
1 2

STA
ABS, Y
3 5

TXS
Imphed
1 2

LOY
ZP
2 3

LOA
ZP
2 3

LOX
ZP
2 3

5MB2
ZP
2 5

TAY
Implied
1 2

LOA
IMM
2 2

TAX
Imphed
1 2

LOY
ABS
3 4

LOY.
ZP, X
2 4

LOA
ZP, X
2 4

LOX
ZP, Y
2 4

5MBJ
ZP
2 5

CLV
Imphed
1 2

LOA
ABS,Y
3 4'

TSX
Imphed
1 2

LOY
ABS, X
3 4'

CPY
ZP
2 3

CMP
ZP
2 3

DEC
ZP
2 5

5MB4
ZP
2 5

INY
Imphed
1 2

CMP
IMM
2 2

DEX
Imphed
1 2

CPY
ABS
3 4

CMP
ZP, X
2 4

DEC
ZP, X
2 6

5MB5
ZP
2 5

CLD
Implied
1 2

CMP
ABS, Y
3 4'

SBC
ZP
2 3

INC
ZP
2 5

5MB6
ZP
2 5

INX
Imphed
1 2

SBC
IMM
2 2

sec

INC
ZP, X
2 6

5MB7
ZP
2 5

SED
Imphed
1 2

SBC
ABS, Y
3 4"

ecs

LOA

Relative (IND), Y
2 2"
2 5'
CMP
(IND,X)
2 6

BNE
CMP
Relabve (IND), Y
2 2"
2 5"

sec

CPX
ZP
2 3

(IND, X)
2 6

BEQ
JBC
Relative (IND), Y
2 5'
2 2"

ZP, X
2 4

2

AND
ABS
3 4

ROL
ABS
3 6

EOR
ABS
3 4

LSR
ABS
3 6

ADC
ABS
3 4

ROR
ABS
3 6

ADC
ROR
ABS, X ABS, X
3 4'
3 7

DEY
Imphed
1 2

LOX
IMM
2 2

F
BBRO
ZP
3 5"

EOR
LSR
ABS, X ABS, X
3 4'
3 7

5MBO
ZP
2 5

6

E
ASL
ABS
3 6

AND
ROL
ABS, X ABS, X
3 7
3 4'

STX
ZP
2 3

2

o
ORA
ABS
3 4

ORA
ASL
ABS, X ABS, X
4'
3
7
3

STA
ZP
2 3

LOA
(IND, X)
2 6

CPX
IMM
2 2

C

STY
ZP
2 3

LOY
IMM
2 2

CPY
IMM
2 2

B

STA
(IND, X)
2 6

Relative (IND, Y)
2

5

TXA
Imphed
1 2

STY
ABS

STA
ABS

STX
ABS

3 4

3 4

3 4

STA
ABS, X
3 5
LOA
ABS
3 4

LOX
ABS
3 4

DEC
ABS

3 6

BBR3
ZP
3 5"
BBR4
ZP

3 5"
BBRS
ZP
S"

3

BBR6
ZP
3 5"
BBR7
ZP
3 5"
BBSO
ZP
S"

BBS2
ZP
3 5"

A

BBS3
ZP
3 5"

B

BBS4
ZP
3 S"

C

BBSS
ZP

SBC
ABS

INC
ABS

BBSS
ZP

3 4

3 6

3 5"

D

o

3 5"

CPX
ABS

c

8

3

3 4

INC
sec
ABS, X ABS, X
3 7
3 4'

B

2

BBSl
ZP

CMP
DEC
ABS, X ABS, X
3 7
3 4'
NOP
Imphed
1 2

BBR2
ZP
3 5"

3 5"

LOA
LOX
ABS, X ABS,Y
3 4'
3 4'
CMP
ABS
3 4

BBRl
ZP
5"

3

BBS7
ZP

E

F

3 5"
F

o
o

BRK
Implied
1 7

-OPCode
-Addressing Mode
-Instruction Bytes; Machine Cycles

"Add 1 to N If page boundary IS crossed.
.. Add 1 to N If branch occurs to same page;
add 2 to N if branch occurs to different page,

3-57

R65F11. R65F12

FORTH Based Microcomputers

APPENDIX B
KEY REGISTER SUMMARY
7

0

MCR

L,I_ _ _" -_ _ _-;}I ACCUMULATOR
7

15

Addr 0014

0

~17===~===~ol

INDEX REGISTER Y

'=17---"------='01

INDEX REGISTER X

.......i17,......._ _:..:PC:::L'----_ _~OI

L._--'P..::C:.:H_ _ _

PROGRAM COUNTER

CDYnter B
Mode Select

PC

l

-'5::.P_ _ _--:" STACK POINTER

7

II I 0 II I z Ic I PROCESSOR STATUS REG

P

00-

0 Iniervill Timer
1 Pulse Generation

1_

0

e.... nl Counter

1 - 1 Pulse Width Meas
0 - 0 Inlerval Timer

Bus Mode Select

,=1_ _

IN I v I

I I

o _
1 AsymmetriC Pulse Generation
10 Event Counter
1_
1 Retrlggerablelnterval TImer
Port B Latch

(I ~ Enable)
Port 0 Tn-Stale

(0 - Trl-$Ial. High Impedance Mode)

CPU Registers

_

1 Muxd Bus

Mode Control Register

l

CARR V (e)



.. "l -ll
~

FORTH Based Microcomputers

R65F11. R65F12

APPENDIX E
ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS*
Symbol

Value

Unit

Vee & VRR

-0.3 to + 7.0

Vdc

Input Voltage

VIN

-0.3 to + 7.0

Vdc

Operating Temperature Range,
Commercial

TA

TL to T H
o to +70

°C

T STG

-55 to + 150

°C

Parameter
Supply Voltage

Storage Temperature

"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

DC CHARACTERISTICS
(Vce = 5.0V ±5%, VRR = Vee; Vss = OV; TA = 0° to 70°, unless otherwise specified)
Parameter
RAM Standby Voltage (Retention Mode)

Symbol

Min

VRR

3.0

-

RAM Standby Current (Retention Mode)

IRR

Input High Voltage
All Except XTLI
XTLI

VIH
+2.0
+4.0

Typl

-

4

-

Input Low Voltage

VIL

-0.3

Input Leakage Current
RES, NMI

liN

-

Input Low Current
PA, PB, PC, PO, PF3, PG3

IlL

-

Output High Voltage (Except XTLO)

VOH

Output Low Voltage

VOL

-

-

I/O Port Pull-Up Resistance
PAO-PA7, PBO-PB7, PCO-PC7, PFO-PF73,
PGO-PG73

RL

3.0

Output Leakage Current (Three-State 011)

lOUT

-

Darlington Current Drive
PE3

+2.4

-1.0

IOH

Input Capacitance
XTLI, XTLO
All Others

CIN

Output Capacitance (Th ree-State Off)

COUT

-

Power Dissipation (Outputs High)

PD

-

Notes:
1. Typical values measured at TA = 25°C and Vee = 5.0V.
2. Negative sign indicates outward current Ilow, positive indicates inward Ilow.
3. R65F12 only.

3-62

Max
Vcc

Unit

Test Conditions

V
mA

TA = 25°C

V
Vcc
Vee
+0.8

V

±10.0

,.A

VIN = 0 to 5.0V

-1.6

mA

VIL = O.4V

Vee

V

ILOAD = -100,.A

+0.4

V

ILOAD = 1.6 mA

6.0

11.5

Kohm

-

±10

,.A

-

-

mA

VOUT = 1.5V

pF

TA = 25°C
VIN = OV
I = 1.0 MHz

10

pF

TA = 25°C
VIN = OV
I = 1.0 MHz

1000

mW

TA = 25°C

-1.0

-

50
10

R65F11 • R65F12

FORTH Based Microcomputers

APPENDIX F
TIMING REQUIREMENTS AND CHARACTERISTICS
F.2 CLOCK TIMING

F.1 GENERAL NOTES
1. Vcc = 5V ± 5%, O"C .. TA .. 70"C

SYMBOL
2. A valid V cc - RES sequence is required before proper
operation is achieved.

PARAMETER

1 MHz

MAX

MIN

MAX

1Ol£S

500

10l£s

250
± 10

-

TCyc

Cycle Time

1000

T PWX1

XTLI Input Clock
Pulse Width
XTLO = VSS

500
±25

4. All time units are nanoseconds, unless otherwise specified.

T PW02

5. All capacitive loading is 130pf maximum, except as noted
below:

Output Clock Pulse T PWX1 T PWX1
Width at MInimum
± 25
Tcyc

TRo TF

Output Clock Rise,
Fall TIme

-

TiRo TIF

Input Clock Rise,
Fall TIme

-

3. All timing reference levels are O.BV and 2.0V, unless
otherwise specified.

PA, PB, PE,PF, PG

-

50pf maximum

2 MHz

MIN

-

T PWX1

T PWX1
± 20

25

-

15

10

-

10

Tcyc

To.
XTU

1.5V

..

Tpw02

02

_ _ T.

3·63

T.

FORTH Based Microcomputer,s

R65F11. R65F12
F.3 MULTIPLEXED MODE TIMING-PC AND PO
(MeR 5

= 1, MeR 6 = 1, MeR 7 = 1)

SYMBOL

1 MHz

PARAMETER

MIN

2 MHz
MIN

MAX

225

-

225

-

MAX

T pcRS

(PC5) R/W Setup Time

T PcAS

(PCo-PC4.

T pBAS

(PO) Address Setup Time

-

T pBSU

(PO) Data Setup Time

50

T pBHR

(PO) Data Read Hold Time

10

T pBHW

(PO) Data Wnte Hold Time

30

'-

30

-

T pBOO

(PO) Data Output Delay

-

175

-

150

-

PC6) Address Setup Time

225

-

10

TPCHA

(PCO-PC4. PC6) Address

30

-

30

(PO) Address Hold Time

10

100

10

TPCHR

(pe5) R/W Hold Time

30

-

30

Time

T pcHV

(PC7) EMS Hold Time

10

-

10

T pcvo lll

(PC7) Address to EMS Delay Time

30

-

30

T pcvp

(PC7) EMS Stabilization Time

30

30

EMS Set Up Time

-

-

T Esu

NOTE 1 Values assume PCo-PC4.

-

350

140
140

35

T pSHA

HolD

140

-

80

210

pce and PC7 have the same capaCl~ve load

F.3.1 Multiplex Mode Timing Diagram
READr-____________~

WRITE

_ _ TPCHR

R/W
(pes)
• TPCRS
-TPCHV
EMS
(PC-7)

TESU

TPCVP
TPCHAPCO-PC4,
PCS
TPCAS

PDDPD7

TPBAS

-

TPBDD

_TPBHA

TPCVP

- TPBHR

3-64

TPBHW

R65F11 • R65F12

FORTH Based Microcomputers

F.4 I/O, EDGE DETECT, COUNTERS, AND SERIAL I/O TIMING
2 MHz

1 MHz
SYMBOL

PARAMETER
MIN

MAX

MIN

MAX

Internal Write to Penpheral Data Valid
T

(1)
pow
TCMOS(1)

PA, PBTIL
PA, PB CMOS

-

500
1000

-

500
1000

Penpheral Data Setup Time
T PDSU

PA, PB

200

-

200

-

Penpheral Data Hold Time
T PHR
TEPW

PA, PB
PAO-PA3 Edge Detect Pulse Width

75

-

75

-

Tcyc

-

Tcyc

-

TCYC

-

Tcyc

-

Counters A and B
Tcpw
T (1)
co

PA4, PA5 Input Pulse Width
PA4, PAS Output Delay

-

500

-

500

Port B Latch Mode
T PSLW
T PLSU
T PBlH

PAO Strobe Pulse Width
PB Data Setup Time
PB Data Hold Time

Tcyc
175
30

-

Tcyc
150
30

-

-

Senail/O

T
(1)
pow
T CMOS")
Tcpw
Tpow 111
T CMOS")

PA6XMTRTIL
500
PA6 XMTR CMOS
1000
PA4 RCVR SIR Clock Width
4 Tcyc
4 TCYC
PA4 XMTR Clock-SIR Mode (TIL)
500
PA4 XMTR Clock-SIR Mode (CMOS)
1000

-

-

-

NOTE 1. Maximum Load Capacrtance' 50pF Passive Pull-Up ReqUired

3-65

500
1000

500
1000

R65F11 • R65F12

FORTH Based Microcomputers

F.4.1 I/O Edge Detect, Counter, and Serial I/O Timing

1.SV

1.SV\

/

,'"
A

PAO·PA7
PBO·PB7
PCO·PC7
PDO·PD7

EDGE DET ECTS
(pAO·PA3)

..

TCyc

.1"
TPDSU

I

..

I~

I

"

~

K

).
TEPW

CNTR
PA4, P AS

.

.

1.SVj

\1.SV
TCPW

TCD

1,SVI
TCPW
2.4V

CNTR
(PA4, P AS)

O.4V
TCMOS
PAO·PA7

TPDW

2.4V

VDD-30%1

I

PBO·PB 7
O.4V
PB
(LATCH MODE)

>~

__________________-J,K~_
1.SV

PAO STROBE

~T

PLSU

1.SV

PBLW------~I

-.11 ....1 - - - - - - T

3·66

..

_ T pBLH

FORTH Based Microcomputers

R65F11 • R65F12

APPENDIX G
INCLUDED FORTH FUNCTIONS IN ROM
BANKEXECUTE
EEC!
?
DoR
#>
IN IT
DISK
MOD
MI

DABS
S->D
BLANKS
EXPECT
COUNT
SPACE
<
2PAD
IN
UPAD
TIB
2
+'
SWAP
DNEGATE
0<
>R
RP!
OR
CMOVE
EMIT
(DO)
BRANCH

BANKEEC!
#S
<#
DWRITE
M/MOD
I

M*
ABS
COLD
ERASE
(0")

DECIMAL
PICK
U<
1C/L

CLD/WRM
UC/L
BL
1
C@
BOUNDS
2DROP
NEGATE
0=
LEAVE
SP!
AND
CR
ENCLOSE
(+LOOP)
EXECUTE

BANKC@
oR
.#
SPACES
DREAD
*1
IMOD

BANKC!
Do
SIGN
SEEK
SELECT
*/MOD

MAX
0+(NUMBER)
FILL
-TRAILING
HEX
ROT

*
MIN
+HOLD
QUERY
TYPE
-DUP
>

2+
HLD
BASE
RO

1+
DPL
UR/W
SO

4

3

0
@
2DUP
DROP
0+
R
;S
SP@

C!
TOGGLE
DUP
OVER
+
R>
RP@
XOR
U*
KEY
DIGIT
OBRANCH
LIT

UI

?TERMINAL
(FIND)
(LOOP)
CLiT

3-67

R65FRx • R65FKx

'1'

R65FRx AND R65FKx
RSC FORTH
DEVELOPMENT AND KERNEL ROMS

Rockwell
INTRODUCTION

FEATURES

The Rockwell Single Chip (RSC) FORTH System can be configured using the R65F11, R65F12 microcomputers or the
R6501Q ROM-less microcomputer. One of these microcomputers, when used in conjunction with a development ROM and
a FORTH kernel ROM, provide the designer with maximum flexibility when developing FORTH applications.

• R65FR1 FORTH Development ROM
-SK ROM
-Addressable from $2000 through $3FFF in FORTH development configuration memory map
-R65F11 and R65F12 compatible
-Operates in the R65F11/F12 FORTH development
configuration

RSC-FORTH is based on the popular fig-FORTH model with
extensions. The R65F11 and R65F12 both have the kernel of
the high level Rockwell Single Chip RSC-FORTH language contained in the preprogrammed ROM. The R65FK2 and R65FK3
Kernel ROMs are preprogrammed ROMs for use with the
R6501Q when developing larger applications requiring more
memory and I/O line support. All of the run time functions of the
RSC-FORTH are contained in these ROMs, including 16- and
32-bit mathematical, logical and stack manipulation, plus
memory and input/output operators. The RSC-FORTH Operating
System allows an external user program written in RSC-FORTH
or Assembly Language to be executed from external EPROM,
or development of such a program under the control of the
R65FR1, R65FR2 or R65FR3 RSC-FORTH Development ROMs.

• R65FR2 FORTH Development ROM
-SK ROM
-Addressable from $4000 through $5FFF in the FORTH
development configuration memory map
-R6501 Q compatible for use in emulation of the R65F11/F12
FORTH development configuration
• R65FR3 FORTH Development ROM
-SK ROM
-Addressable from $COOO through $DFFF in the FORTH
development configuration memory map
-Operates in the R6501 Q FORTH development
configuration
• R65FK2 FORTH Kernel ROM
-4K ROM
-Addressable from $F400 through $FFFF in the FORTH
development configuration memory map
-R6501Q compatible for use in the emulation of the
R65F11/F12 FORTH development configuration
-Replaces the FORTH kernel contained in the R65F11 and
R65F12 microcomputers during development

This document describes five different RSC-FORTH system configurations using the development and kernel ROMs.

ORDERING INFORMATION
Part No.
R65FR1P
R65FR2P
R65FR3P
R65FK2P
R65FK3P
R65F11P
R65F11AP
R65F120
R65F12AO
R65010
R6501AO

Description
FORTH Development ROM for R65F11 or R65F12
FORTH Development ROM for R65010
FORTH Development ROM for R65010
FORTH Kernel ROM for R65010
FORTH Kernel ROM for R65010
40-Pin FORTH Based Microcomputer at 1 MHz
40-PIn FORTH Based Microcomputer at 2 MHz
64-PIn FORTH Based Microcomputer at 1 MHz
64-Pin FORTH Based Microcomputer at 2 MHz
64-PIn One-Chip Microprocessor at 1 MHz
64-Pin One-Chip Microprocessor at 2 MHz

Order No.
2145
2146
2148
2162

• R65FK3 FORTH Kernel ROM
-4K ROM
-Addressable from $F400 through $FFFF in the FORTH
development and production configuration memory maps
-R6501Q compatible
-Operates in the R6501 Q FORTH development and production configurations

RSC-FORTH SYSTEM CONFIGURATIONS
The three configurations of the RSC-FORTH System are identified by the CPU-Development ROM combinations listed below:

Description
R65010 One-Chip Microprocessor Product
Description
R65F11 and R65F12 FORTH Based Microcomputer
Product Description
RSC-FORTH User's Manual
Application Note: A Low-Cost Development Module
for the R65F11 FORTH Microcomputer

RSC-FORTH System Configurations

Document No_ 29651N80
3-6S

CPU

Kernel
ROM

R65F11
R65F12
R65010
R65010

none
none
R65FK2
R65FK3

Development
ROM

RSC
Configuration

R65FR1
R65FR1
R65FR2
R65FR3

1
1
2
3

Product Description Order No. 2177
February 1984

R65FR1

RSC FORTH ROMs

RSC-FORTH CONFIGURATION 1 (R65FR1)
R65F11/R65F12 DEVELOPMENT AND PRODUCTION
Although programs may reside in the upper 8K bytes of memory
area, normally filled by the R65FR1 Development ROM, it is difficult to develop code for that area using this configuration of
the RSC-FORTH System.

The RSC-FORTH Configuration 1 provides the designer with a
FORTH development and application environment at a minimal
cost. The application program is developed using an R65F11
or R65F12 microcomputer, an R65FR1 Development ROM and
external RAM. Up to 8K bytes of RAM space is available using
this configuration. However, Configuration 1 is limited to 5K or
less bytes of RAM during development. This is the result of
allocating 2K: bytes of RAM for disk buffers and at least 1K bytes
of RAM for the "Program heads". The program heads are contained in a dictionary containing the Name (NFA), Link Field
Address (LFA) and the Parameter Field Address Pointer (PFA).
This dictionary is a list of FORTH word words and user-defined
FORTH words used in the development of a FORTH program
and is not present during the execution of the FORTH program.

The difference in using the R65F11 or the R65F12 is in the
number of 1/0 lines available to the user. The R65F11 supports
16 1/0 lines, the R65F12 supports 40 1/0 lines.
Figure 1 shows the development and production configurations
for the R65F11/F12. Configurations 1A and 18 list the features,
memory maps, and the relationship of the R65F11 and R65F12
to the R65FR1 Development ROM in the development and production environment.

APPLICATION
DEVELOPMENT
RAM
,,;8K BYTES

APPLICATION
'EPROM
,,;8K BYTES
R65F11!
R65F12
MICROCOMPUTER

R65F11!
R65F12
MICROCOMPUTER
R65FR1
DEVELOPMENT
ROM
8K BYTES

APPLICATION
RAM
(OPTIONAL)

DEVELOPMENT

Figure 1.

PRODUCTION

R65FR1 Configuration 1 Block Diagram

3-69

R65FR1

RSC FORTH ROMs

CONFIGURATION 1A CONSIDERATIONS

CONFIGURATION 1B CONSIDERATIONS

Features
• ·.8K Bytes of Uller Memory
• 16 110 Lines

Features
• 8K Bytes of User Memory
• 40 110 Lines

Device Configuration

Device Configuration
DEVELOPMENT PRODUCTION

DEVELOPMENT PRODUCTION
R65F11 Microcomputer

R65F12 Microcomputer

R65FR1 Development ROM

R65FR1 Development ROM

User Memory-I/O Resource Matrix

User Memory-IIO Resource Matrix

User memory may be a mix of ROM, EEROM, UVPROM or
RAM.

User memory may be a mix of ROM, EEROM, UVPROM or
RAM.

1

48Kl

1

48KI

MEMORY

MEMORY
16K

16K

8K

8K

0
0

16

32

40

1/0 LINES

Memory Map

~F9

Memory Map

32

16

40

1/0 LINES

~F9

FOOO

FOOO

'r

4000

MUX BUS

{

4000
R65FR1
MUX BUS

2000
USER MEMORY

0000

3-70

{

R65FR1
2000
USER MEMORY
0000

RSC FORTH ROMs

R65FR2 • R65FK2
RSC-FORTH CONFIGURATION 2
(R65FR2, R65FK2)
R6501Q DEVELOPMENT AND R65F11/F12
PRODUCTION

Using this configuration, the application program can be
developed using the R6501Q and then later installed in an
R65F11 or R65F12 microcomputer without modification.

The RSC·FORTH Configuration 2 provides the designer with the
capability of using the full 16K bytes of external address space
of the R65F11 and R65F12.

Figure 2 shows the development and production configuration
for the R6501 Q. Configurations 2A and 2B list the features,
memory maps, and the relationship of the R6501 Q to the
R65FR2 Development ROM and R65FK2 Kernel ROM in the
development and production environment. Figure 3 is a
schematic of the R6501 Q, R65FR2, R65FK2 development setup.

The R6501Q ROM·less microprocessor, when used with the
R65FK2 Kernel ROM and the R65FR2 Development ROM,
emulates the operation of the R65F111F12. Because of the
greater address space of the R6501 Q, the R65FR2 Development
ROM can be relocated to address $4000 and the disk buffers
and HEADS program to $6000. This expands the available user
memory space to 16K bytes, $0000 through $3FFF.

DISK AND
HEADS RAM
,;8K BYTES

R65FR2
DEVELOPMENT
ROM
8K BYTES

APPLICATION
EPROM

,;16K

R65FK2
KERNEL
ROM
3K BYTES

R6501Q
MICROPROCESSOR

R65F111
R65F12
MICRO·
PROCESSOR

APPLICATION
DEVELOPMENT
RAM
,;16K BYTES

APPLICATION
RAM
16K BYTES

PRODUCTION

DEVELOPMENT

Figure 2.

R65FR2 and R65FK2 Configuration 2 Block Diagrams

3-71

Rse FORTH ROMs

R65FR2 • R65FK2
CONFIGURATION 2A CONSIDERATIONS

CONFIGURATION 28 CONSIDERATIONS

Features
• 16K Bytes of User "Headerless" Memory
• 16 1/0 Lines

Features
• 16K Bytes of User "Headerless" Memory
• 40 I/O Lines

Device Configuration

Device Configuration
DEVELOPMENT PRODUCTION

DEVELOPMENT PRODUCTION

1/

R65F11 Microcomputer

1/

R65F12 Microcomputer

R6501 Q Microprocessor

1/

R6501Q Microprocessor

1/

R65FR2 Development ROM

1/

R65FR2 Development ROM

1/

R65FK2 Kernel ROM

1/

R65FK2 Kernel ROM

1/

Memory-I/O Matrix

Memory-I/O Matrix

If floppy disk is used in the application, space for the disk buffers must be allocated in memory from $0500 through $3FFF
or $6000 through $7FFF. User memory can be a mix of ROM,
EEROM, UVROM or RAM.

If floppy disk is used in the application, space for the disk buffers must be allocated in memory $0000 through $3FFF. User
memory can be a mix of ROM, EEROM, UVROM or RAM.

1

1

1

48K

MEMORY

MEMORY

16K
8K

16
32
1/0 LINES

16

40

32

40

1/0 LINES

Memory Maps

Memory Maps
PRODUCTION

DEVELOPMENT
FFF
Fn
R,65FK2
F4DO

1
8000
6000

DEVELOPMENT

1

FFFF~

1

F400

KERNEL

FFFF~

1

8000

8K USER RAM
(HEADS)

6000

R65FR2
4000

4000

0000

USER
MEMORY
(CODES ONLY)

R65FK2

1

""n
PRODUCTION

8K USER RAM
(HEADS)
R65FR2

t-------i

4000

USER
MEMORY
0000 (CODES ONLY)

0000

3-72

USER
MEMORY
(CODES ONLY)

4000 1 - - - - - - 1
USER
MEMORY
0000 (CODES ONLY)

:IJ

en

CIt

+5V

c

en

m
~

o

"'II

Z
c

=u
c...

c

i!:
"'II

-

-I

PDe
RES
Vee
NMI
PA7
PA6
PAS
"
PA4
~ PA3
~ PA2
PAl
PAl
PB7
PB6
PBS
PB4
PB3
PB2
PB1
PBe
VRR
V"

:D

"'II

r

c

C>

Z

-I

o

:D

en
]

U1

en

oo

"~

1
2
3
4
5
6
7
8
9
10
11
12

~
"'IIPD1~

Z

2
"'II
en
o
o

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

62
6
21
23
32
33
34
35
36
37
38
39
24
25
26
27
28
29
30
31
43
44

:IJ
N

8KRAM

41
42
45
54
55
56
57
58
59
60
61
5

8!-------4
14
3
15
2"
PD3~
PD2 fff------¥.

m

o

'"~
'"

XTLO
XTLI
02
pce
PCl
PC2
PC3
PC4
PC5
PC6
PC7
PD7
PD6
c... PD5
.... PD4

"T1

.r.:\. WE

J21

•

:IJ

en
CIt

"T1

~

....c
:D

en
o
....
U1

o

Oi
~

"'II

D7
D6
05
D4
D3
D2
D1
De

ADDRESS BUS

Z

DATA BUS

o

c
j

12

~

3

4
6

RIW 40

5

U7

~4
US
U6

74LS04
74LS10

U7

74LSOO

+5V

GND

14
14
14

7

:IJ

NOTES

Pin 22 on R6501Q-Sync Signal not connected.
When emulating a R65F12 system Ports E, F or G
must be constructed externally using TTL circuits
(contact Rockwell).

en

o

"T1

o

:IJ

-4

::::t
:IJ

o

Figure 3.

R6501Q, R65FR2 and R65K2 Application Configuration Schematic

a

s::

o

RSC FORTH ROMs

R65FR3 • R65FK3
RSC-FORTH CONFIGURATION 3
(R65FR3, R65FK3)

CONFIGURATION 3 CONSIDERATIONS
Features
• R6501Q w/FORTH
• 48K Bytes of User Memory
• 30 110 Lines

R6501Q BASED SYSTEM DEVELOPMENT
AND PRODUCTION
The RSC-FORTH Configuration 3 is designed for those applications which require a larger amount of ROM or RAM space than
the R65Fll or R65F12 can provide.

Device Configuration
DEVELOPMENT PRODUCTION

In the development configuration, the user is provided with up
to 48K bytes of memory. The user memory is located from $0000
through $BFFF. The program heads will use some of this area
but the user will still have considerably more memory space
available then in the previous configurations.
The production configuration provides up to 56K bytes of user
memory. This is due to the fact that the R65FR3 Development
ROM, used in the development configuration, is not required
in the production configuration and releases the 8K bytes of
memory space. This memory is located at $COOO through
$DFFF.

R6501Q
MICROPROCESSOR

/'-

'v-

~

rV

V'

R65FK3 Development ROM

V'

R65FR3 Kernel ROM

V'

V'

V'

User Memory-I/O Resource Matrix
All ports act as 110 ports. Memory is on the bus. PC6 & PC7
(110 lines) are assigned to memory. User memory can be a mix

Figure 4 shows the development and production configurations
for the R6501 Q. Configuration 3 lists the features, memory maps,
and the relationship of the R6501 Q to the R65FR3 Development
ROM and the R65FK3 Kernel ROM in the development and production environment.

r;>

R6501Q Microcomputer

of ROM. EEROM, UVPROM or RAM.

R65FR3
DEVELOPMENT
ROM
8K BYTES

MEMORY

R65FK3
KERNEL
ROM
4K BYTES

1/0 LINES

--"
L-,/

APPLICATION
DEVELOPMENT
RAM
,,48K BYTES

Memory Maps
DEVELOPMENT

DEVELOPMENT

FFFF
FOOO

R65FK3
KERNEL
ROM

PRODUCTION
FFFF

R65FK3

FOOO

AVAILABLE

AVAILABLE

E006

E006
FLOPPY CONTROL

R6501Q
MICROPROCESSOR

R65FK3

EOOO

EOOO

FLOPPY CONTROL

R65FR3
COOO
APPLICATION
RAM
"56K BYTES

USER
MEMORY

1

PRODUCTION

0000
Figure 4_ R65FR3 and R65FK3
Configuration 3 Block Diagrams
3-74

USER
MEMORY

J

1 1

0000

RSC FORTH ROMs

R65FRx • R65FKx

NC
A12
A7
A6
AS
A4
A3
A2
A1
AO
DO

01
02
GNO

2
3
4
5
6 R65FR1
OR
7
R65FR2
8
OR
9 R65FR3
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A7
A6
AS
A4
A3
A2
A1
AO
00
01
02
GNO

VCC
NC
NC
A8
A9
A11
OE
A10
CS
07
DB
05

1
24
2
23
3
22
4
21
5
20
6
R65FK2 19
OR
7
18
8 R65FK3 17
16
9
10
15
11
13
12
14

D4

03

RSC-FORTH ROM Pin Assignments

3-75

VCC
A8
A9
A11
OE
A10
CS

07
06
05
04
03

R6501Q
R6500 Microcomputer System

'1'

Rockwell

R6501Q
ONE-CHIP MICROPROCESSOR

SECTION 1
INTRODUCTION

1.1 FEATURES OF THE R6501Q
• Enhanced 6502 CPU
-Four new bit manipulation instructions
• Set Memory Bit (5MB)
• Reset Memory Bit (RMS)
• Branch on Bit Set (BBS)
• Branch on Bit Reset (BBR)
- Decimal and binary arithmetic modes
-13 addressing modes
- True indexing
• 192-byte static RAM
• 32 bidirectional, TTL-compatible I/O lines (four ports)
• One a-bit port may be tn-stated under software control
• One a-bit port may have latched inputs under software
control
• Two 16-blt programmable counter/timers, with latches
-Pulse width measurement
-Asymmetrical pulse generation
- Pulse generation
-Interval timer
-Event counter
-Retriggerable interval timer
• Senal port
- Full-duplex asynchronous operation mode
-Selectable 5- to a-bit characters
-Wake-up feature
-Synchronous shift register mode
-Standard programmable bit rates programmable
up to 62.5K bits/sec @ 1 MHz
• Ten Interrupts
-Four edge-sensitive lines; two positive, two negative
-Reset
- Non-maskable
- Two counter underflows
-Serial data received
-Serial data transmitted

• Bus expandable to 64K bytes of external memory
• Flexible clock circuitry
-2-MHz or 1-MHz internal operation
-4 MHz Crystal used to generate internal clocks
• 1 I-'S minimum instruction execution time at 2 MHz
• NMOS-3 silicon gate, depletion load technology
• Single +5V power supply
• 12 mW stand-by power for 32 bytes 01 the 192-byte RAM
• 64-pin QUIP

1.2 SUMMARY
The Rockwell R6501 Q is a complete, high-performance a-bit
NMOS-3 microcomputer on a single chip and is compatible
with all members of the R6500 family.
The R6501 Q consists of an enhanced 6502 CPU, an internal
clock oscillator, 192 bytes of Random Access Memory (RAM),
and versatile interface circuitry. The interface circuitry includes two 16-bit programmable timer/counters, 32 bidirectional input/output lines (including four edge-sensitive lines
and input latching on one a-bit port), a full-duplex serial I/O
channel, ten interrupts, and bus expandability.
The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction Simplicity,
results in system cost-effectiveness and a wide range of
computational power. These features make the R6501Q a
leading candidate for microcomputer applications.

Document No. 29651N48
3-76

Product Description Order No. 2145
Rev. 3, October 1984

One-Chip Microprocessor

R6501Q
Rockwell supports development of the R6501 Q
System 65 Microcomputer Development System
R6500/* Family of Personality Modules. Complete
emulation with the R6500r Family of Personality
allows total system test and evaluation.

1.3 CUSTOMER OPTIONS

with the
and the
in-circuit
Modules

The R6501 Q has no customer specified mask options. It has
the following characteristics.
•
•
•
•
•

This product description assumes that the reader is familiar
with the R6502 CPU hardware and programming capabilities.
A detailed description of the R6502 CPU hardware is included
in the R6500 Microcomputer System Hardware Manual (Document Order No. 201). A description of the instruction
capabilities of the R6502 CPU is contained In the R6500
Microcomputer System Programming Manual (Document
Order No. 202).

PO,
PD4
PD.

PDO
PC7
PC,
PC.
PC.
PC,
PC,

PD7

RES
A12
A11
A10
A9
A.
A7
AS
A'
A.

A1

AO
V"
SYNC

NMi
PB7
PB'
PB,
PB'
PB'
PB'
PB'
PBO
PA7

R6S01Q

PC'
PCO
DBO
DB'
DB'
DB'
DB.

Crystal Oscillator
Clock Divide by 4
Clock MASTER Mode
Reset Vector at FFFC
Internal pull-up resistors on Ports PA, PB, and PC

1.4 ORDERING INFORMATION
R6501Q - 4 MHz Xtal, 1 MHz Operation-Commercial
R6501AQ-4 MHz Xtal, 2 MHz Operation-Commercial
R6501EQ-4 MHz Xtal, 1 MHz Operation-Industrial
R6501AEQ-4 MHz Xtal, 2 MHz Operation-Industrial

L
-t
020TVP
(50BMM)

1628
(413SMM)

DB'
DB7

"

V"
Vee
XTLI
XTL.O

'"d
z

0

_~_t I
J

PA5

-~---

PA'

~--:cr-:O'50 REF

(127MM)
TYP

64 PIN QUIP

Figure 2-1.

~

•~ m

R/W
PAO
PA'
PA'
PA3
PA'

Mechanical Outline & Pin Out Configuration

3-77

>020 REF

TYP

J

One-Chip Microprocessor

R6501Q

SECTION 2
INTERFACE REQUIREMENTS
TABLE 2-1. R6501Q Pin Descriptions

This section describes the interface requirements for the
R6501 Q. Figure 2-1 and 2-2 show the Interface Diagram and
the pin out configuration for both devices. Table 2-1 describes
the function of each pin. Figure 3-1 has a detailed block diagram of the R6501 Q ports which illustrates the internal function of the device.

SIGNAL NAME

Vee
VRR

PIN NO.

DESCRIPTION

21

Main power supply +5V
Separate power pin for RAM.
In the event thai Vee power
is off, this power retains RAM
'
data.

43

XTLI

44
42

XTLO

41

V••

6
XTLO
XTLI

PAO-PA7 (PAO, PAl,
P42, PA3

45

EDGE DETECTS)
PSO-PS7 (LATCHED INPUTS)

23

DS (PAO)
(DATA STROBE,"

Peo-PC7

PAO-PA7
PBO-PB7
PCO-PC7
PDO-PD7

39-32
31-24
54-61
62-64,
1-5

AO-A12, A15

20-7

DBO-DB7

53-46

CA (PA4),

CB (PA5),

so (PA6)"
51 (PA7)

MULTIPLEXED FUNcnONS PINS

(Software Selectable,

Figure 2-2.

Interface Diagram

3-78

SYNC

22

R/W

40

Signal and power ground (OV)
Crystal or clock input for internal clock oscillator. Allows
input of Xl clock signal if
XTLO is connected to Vss or
of X4 clock if XTLO is floated.
Crystal output from internal
clock oscillator.
The Reset input is used to
initialize the device. This signal must not transition from
low to high for at least eight
cycles after Vee reaches operating range and the internal oscillator has stabilized.
Clock signal output at Internal frequency.
A negative goi ng edge on the
Non-Maskable Interrupt signal requests that a nonmaskable interrupt be generated with the CPU.
Four 8-bIt ports used for
either input/output. Each line
of Ports A, Band C consists
of an active transistor to V ss
and a passive pull-up to Vee.
Port 0 functions as either an
8-bit input or 8-bit output port.
It has active pull-up and pu'lIdown transistors.
Fourteen address lines used
to address a complete
65K external address space.
Note: A13 & A14 are sourced
through PC6 & PC7 when in
the Full Address Mode.
Eight bidirectional data bus
lines used to transmit data to
and from external memory.
SYNC is a positive going signal for the full clock cycle
whenever the CPU is performing an OP CODE felch.
Controls the direction of data
transfer between the CPU
and the extemal 65K address space. The signal is
high when reading and low
when writing.

One-Chip Microprocessor

R6501Q

SECTION 3
SYSTEM ARCHITECTURE
This section provides a functional description of the R6501 Q.
Functionally the R6501Q consists of a CPU, RAM, four 8-blt
parallel I/O ports, a serial I/O port, dual counter/latch circuits,
a mode control register, and an interrupt flag/enable dual
register circuit. A block diagram of the system is shown in
Figure 3-1.

location is stored (or "pushed'1 onto the stack. Each time
data are to be pushed onto the stack, the Stack Pointer is
placed on the Address Bu,s, data are written into the memory
location addressed by the Stack Pointer, and the Stack
Pointer is decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented by
1. The Stack Pointer is then placed on the Address Bus and
data are read from the memory location addressed by the
Pointer.

NOTE

Throughout this document, unless specified otherwise,
all memory or register address locations are specified
in hexadecimal notation.

The stack IS located on zero page, I.e., memory locations
00FF-0040. After reset, which leaves the Stack POinter
indeterminate, normal usage calls for ItS InLtlalizatlon at OOFF.

3.1 CPU LOGIC

3.1.4 Arithmetic And Logic Unit (ALU)

The R6501 Q internal CPU is a standard 6502 configuration
with an 8-bit Accumulator register, two 8-bit Index Registers
(X and V); an 8-b~ Stack Pointer register, an AlU, a 16-bit
Program Counter, and standard instruction register/decode
and internal timing control logic.

All arithmetiC and logiC operalions take place In the AlU,
Including Incremenling and decrementing Internal registers
(except the Program Counter). The AlU cannot store data
for more than one cycle. If data are placed on the Inputs to
the AlU at the beginning of a cycle, the result IS always gated
Into one of the storage registers or to external memory dUring
the next cycle.

3.1.1 Accumulator
The accumulator IS a general purpose 8-bIt register that
stores the results of most arithmetiC and logiC operations. In
addition, the accumulator usually contains one of the two
data words used In these operatIOns.

Each bit of the AlU has two Inputs. These Inputs can be tied
to various Internal buses or to a logiC zero; the AlU then
generates the function (AND, OR, SUM, and so on) uSing
the data on the two Inputs

3.1.2 Index Registers
3.1.5 Program Counter

There are two 8-blt Index registers, X and Y. Each Index reg·
Ister can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the Index register contents.

The 16-blt Program Counter prOVides the addresses that are
used to step the processor through sequential Instructions
In a program Each lime the processor fetches an Instruction
from program memory, the lower (least Significant) byte of
the Program Counter (PCl) IS placed on the low-order bits
of the Address Bus and the higher (most Significant) byte of
the Program Counter (PCH) IS placed on the high-order 8
bits of the Address Bus. The Counter IS Incremented each
time an Instruction or data IS fetched from program memory.

When executing an instruction which specifies indirect
addressing, the CPU fetches the op code and the address
and modifies the address from memory by adding the index
register to it prior to loading or storing the value of memory.
Indexing greatly Simplifies many types of programs, espeCially those uSing data tables.

3.1.6 Instruction Register and Instruction Decode
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These instructions are latched into the
Instruction Register, then decoded along with timing and
interrupt signals to generate control signals for the various
registers.

3.1.3 Stack Pointer
The Stack Pointer is an 8-bit register. It is automatically
incremented and decremented under control of the microprocessor to perform stack manipulation In response to either
user Instructions, an Internal IRQ interrupt, or the external
interrupt line NMI. The Stack POinter must be inilialized by
the user program.

3.1.7 Timing Control
The Timing Control logiC keeps track of the speCifiC Instruclion cycle being executed. ThiS logiC IS set to TO each lime
an InstructIOn fetch IS executed and IS advanced at the
beginning of each Phase One clock pulse for as many cycles
as are required to complete the Instruction. Each data transfer
which takes place between the registers IS caused by
decoding the contents of both the instruction register and
timing control Unit.

The stack allows Simple Implementation of multiple level
interrupts, subroutine nesting and simplification of many types
of data manipulation. The JSR, BRK, RTI and RTS instructions use the stack and Stack Pointer.
The stack can be envisioned as a deck of cards which may
be accessed only from the top. The address of a memory

3-79

R6501Q

One-Chip Microprocessor

3-80

One-Chip Microprocessor

R6501Q
3.1.8 Interrupt Logic

3.4 RANDOM ACCESS MEMORY (RAM)

Interrupt logic controls the sequencing of three Intertupts;
RES, NMI and IRQ. IRQ IS generated by anyone of eight
conditions: 2 Counter Overflows, 2 Positive Edge Detects,
2 Negative Edge Detects, and 2 Senal Port ConditIOns.

The RAM consists of 192 bytes of read/write memory with
an assigned page zero address of 0040 through OOFF. The
R6501Q provides a separate power pin (V RR ) which may be
used for standby power for 32 bytes located at 0040-005F.
In the event of the loss of Vee power, the lowest 32 bytes of
RAM data will be retained If standby power IS supplied to the
VRR pin. If the RAM data retention is not required then V RR
must be connected to Vee. Dunng operation VRR must be at
the Vee level.

3.2 NEW INSTRUCTIONS
In addition to the standard R6502 instruction set, four new
bit manipulation instructions have been added to the R6501 Q.
The added instructions and their format are explained in the
following paragraphs. Refer to Appendix A for the Op Code
mnemonic addreSSing matrix for these added instructions.
The four added instructions do not impact the CPU processor
status register.

For the RAM to retain data upon loss of Vee, VRR must be
supplied Within operating range and RES must be dnven low
at least eight (Il2 clock pulses before Vee falls out of operating
range. RES must then be held low while Vee is out of operating range and until at least eight (Il2 clock cycles after Vee
IS again Within operating range and the Internal (Il2 OSCillator
IS stabilized. VRR must remain Within Vee operating range
during normal operatIOn. When Vee IS out of operating range,
\l.RR must remain Within the VRR retention range in order to
retain data. Figure 3.2 shows typical waveforms.

3.2.1 Set Memory Bit (SMB m, Addr.)
This instruction sets to "1" one of the 8-bIt data field specified
by the zero page address (memory or I/O port). The first byte
of the instruction specifies the 5MB operation and one of eight
bits to be set. The second byte of the instruction designates
address (0-255) of the byte to be operated upon.

RAM OPERATING MODE

RAM RETENTION MODE

I

I

~~=i=

3.2.2 Reset Memory Bit (RMB m, Addr.)
This instructIOn is the same operation and format as 5MB
instruction except a reset to "0" of the bit results.

/--0

3.2.3 Branch On Bit Set Relative (BBS m, Addr,
DEST)

~~Ir--l
--j I[--0

TRL0

INITIAL APPLICATION OF Vee ANO VFIR
LOSS OF V,,, RAM ON STANDBY POWER

This instruction tests one of eight bits designated by a 3-bit
immediate field within the first byte of the Instruction. The
second byte is used to deSignate the address of the byte to
be tested within the zero page address range (memory or
I/O ports). The third byte of the instruction IS used to specify
the 8-bit relative address to which the instruction branches
if the bit tested is a "1". If the bit tested IS not set, the next
sequential instruction IS executed.

v".

REAPPLICATION OF
>8;2 CLOCK PULSES AFTER OSCILLATOR STABILIZATION
>8 .2 CLOCK PULSES

Figure 3-2. Data Retention Timing

3.5 CLOCK OSCILLATOR
The R6501 Q has been configured for a crystal oscillator,
a countdown network, and for Master Mode Operation.

3.2.4 Branch On Bit Reset Relative (BBR m,
Addr, DEST)

A reference frequency can be generated with the on-Chip
oscillator using either an external crystal or an external
oscillator. The oscillator reference frequency passes
through an internal countdown network to obtain the
internal operating frequency (see Figures 3-3a and 3-3b).
The external crystal generated reference frequency is a
preferred method since the resistor method can have tolerances approaching 50%.

This instruction is the same operation and format as the BBS
Instruction except that a branch takes place If the bit tested
IS a "0".

3.3 READ-ONLV-MEMORY (ROM)
The R6501 Q has no ROM and its Reset vector is at FFFC.

Note:
When operating at 1 MHz interval frequency
(R6501 Q) place a 15-22 pt capaCitor between
XTLO and ground.

3-81

One-Chip Microprocessor

R6501Q
Internal timing can also be controlled by driving the XTLI pin
with an external frequency source. Figure 3-3c shows typical
connections. If XTLO is left floating. the external source is
divided by the internal countdown network. However. if XTLO
is tied to Vss • the internal countdown network is bypassed
causing the chip to operate at the frequency of the external
source.

r---.[]XTLI
2_4MHz

c::::J

I, .. , - "" 2 MHz

A6S01Q

....---DXTLO

8. Crystal Input

I

10-22 pF WHEN CRYSTAL ,.,;4 MHz

'":"

simultaneous interrupts cause the IRQ interrupt request to
remain active until all interrupting conditions have been
serviced and cleared.

The Interrupt Flag Register contains the Information that
indicates which I/O or counter needs attention. The contents
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge detect IFR bits may be
cleared by executing a RM B Instruction at address location
0010. The RMB X, (0010) instruction reads FF. modifies bit
X to a "0", and writes the modified value at address location
0011. In this way IFR bits set to a "1" after the read cycle of
a Read-Modify-Write Instruction (such as RMB) are protected
from being cleared. A logiC "1" IS Ignored when wntlng to
edge detect IFR bits.
Each IFR bit has a corresponding bit in the Interrupt Enable
Register which can be set to a "1" by writing a "1" in the
respective bit position at location 0012. Individual IER bits
may be cleared by writing a "0" In the respective bit position,
or by RES. If set to a "1", an IRQ will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag Register and Interrupt Enable Register bit aSSignments are shown
in Figure 3-6 and the functions of each bit are explained in
Table 3-1.

..oil
2-8 MHz

"N! =

"" 2 MHz

R6501Q

Ne

1·2MHz

XTLO

vJ;1;'OO2.4V)
output while a logiC 0 will force a low «O.4V) output.

4.3 Port A (PA)
Port A can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard parallel 8-blt, bit Independent, I/O port
or as serial channel I/O lines, coumer I/O lines, or an input
data strobe for the Port B Input latch option. Table 4-2 tabulates the control and usage of Port A.

4.1 INPUTS

In addition to their normal I/O functions, PAO and PAl can
detect positive going edges and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate an
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rate at which an edge can be detected is oneclock rate. Edge detection timing is shown in Aphalf the
pendix E.3.

Inputs for Ports A, B, and C are enabled by loading logic 1
into all I/O port register bit positions that are to correspond
to I/O input lines. A low «O.8V) Input signal will cause a logic
o to be read when a read instruction is issued to the port
register. A high (>2.0V) input will cause a logic 1 to be read.
An RES signal forces all I/O port registers to logic 1 thus
initially treating all I/O lines as Inputs.

P2

3-85

R6501Q

One-Chip Microprocessor
Table 4-2.

Port A Control and Usage

PAD I/O

PORT B LATCH MODE

MCR4: D

MCR4: 1

SIGNAL

PAD (2)
PIN 39

SIGNAL

NAME

TYPE

NAME

TYPE

PAD

I/O

PORT B
LATCH STROBE

INPUT (1)

PA1-PA3110
PA1 (2)
PIN 38
PA2 (3)
PIN 37
PA3 (3)
PIN 3S

SIGNAL
NAME

TYPE

PAl
PA2
PA3

110
110
I/O

COUNTER A 110

PA41/0

PA4
PIN 3S

MCRD: D
MCRI : D
SCCR7: D
RCVR SIR MODE = 0
(4) (5)

SCCR7: 0
SCCR6: 0
MCRI : 1

MCRO: 1
MCRI : 0
SCCR7: 0
RCVR SIR MODE : 0
(4)

SIGNAL

SIGNAL

SIGNAL

NAME

TYPE

PA4

110

TYPE

NAME

OUTPUT

CNTA

NAME
CNTA

I
I

TYPE
INPUT (1)

SERIAL 110 SHIFT REGISTER CLOCK
SCCR7: 1
SCCR5: 1

RCVR SIR MODE : 1
(4)
SIGNAL

SIGNAL
NAME
XMTR CLOCK

I

TYPE

NAME

I

OUTPUT

RCVR CLOCK

PA5110

TYPE
INPUT (1)

COUNTER B 110
MCR3: 1
MCR2 = X

MCR3: 0
MCR2: 1

MCR3: D
MCR2: D

PAS
PIN 34

I
I

SIGNAL

SIGNAL

SIGNAL

NAME

TYPE

NAME

TYPE

NAME

I

TYPE

PAS

110

CNTB

OUTPUT

CNTB

I

INPUT (1)

PAS
PIN 33

PA6110

SERIAL 110
XMTR OUTPUT

SCCR7 = 0

SCCR7: 1

SIGNAL

SIGNAL

NAME

TYPE

NAME

TYPE

PA6

I/O

XMTR

OUTPUT

PA7
PIN 32

PA7110

SERIAL 110
RCVRINPUT

SCCR6: 0

SCCR6 = 1
SIGNAL

SIGNAL
NAME

TYPE

NAME

TYPE

PA7

I/O

RCVR

INPUT (1)

3-86

(1)
(2)
(3)
(4)

HARDWARE BUFFER FLOAT
POSITIVE EDGE DETECT
NEGATIVE EDGE DETECT
RCVR SIR MODE: 1 WHEN
SCCR6 . SCCRS . SCCR4 = 1
(5) For the following mode combi·
nations PA4 IS available as an
Input Only pin:
SCCR7'SCCR6'SCCR5-MCRI
+ SCCR7·SCCR60SCCR40MCRI
+ SCCR7·SCCR60SCCR5
+ SCCR7·SCCR5-SCCR40

One-Chip Microprocessor

R6501Q
4.4 PORT B (PB)

4.5 PORT C (PC)

Port B can be programmed as an S-bit, bit-independent I/O
port. It has a latched input capability which may be enabled
or disabled via the Mode Control Register (MCR). Table
4-3 tabulates the control and usage of Port B. An Input Data
Strobe signal must be provided thru PAO when Port B is programmed to be used with latched input option. Input data
latch timing for Port B is shown in Appendix E.3.

Port C can be programmed as an I/O port, or as part of the
full address bus. When operating in the Full Address Mode
PC6 and PC7 serve as A 13 and A 14 with PCO-PC5 operating
as normal I/O pins.

Table 4-3.

MCR4

LATCH
MODE
MCR4 = 1
(2)

=0

SIGNAL

#
31
30

29
28
27
26
25
24

Port 0 can be programmed as an I/O Port. Mode selection
for Port 0 is made by the Mode Control Register (MCR). The
Port 0 output drivers can be selected as tri-state drivers by
setting bit 5 of the MCR to 1 (one). Table 4-5 shows the necessary settings for the MCR to achieve the various modes
for Port D.

Port B Control & Usage

I/O MODE

PIN

4.6 PORT 0 (PO)

4.7 BUS MODES

SIGNAL

PIN
NAME

NAME

TYPE
(1)

NAME

TYPE

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

PBO
PBl
PB2
PB3
PB4
PB5
PBS
PB7

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

In the Full Address Mode, the separate address and data bus
are used in conjunction with PC6 and PC7, which automatically provide A13 and A14. The remaining ports perform the
normal I/O function.
In the I/O Bus Mode all ports serve as I/O. The address and
data bus are still functional but without A13 and A14. Since
the internal RAM and registers are in the OOXX location, A 15
can be used for Chip select and AO-A12 used for selecting
SK of external memory.

(1) RESISTIVE PULL-UP, ACTIVE BUFFER PULL DOWN
(2) INPUT DATA IS STORED IN PORT B LATCH BY PAO PULSE

HITS

)

."'"

Y.

Y.

...-

PORTA

...

)

PORTD

PORT •

..lITe

....

..

..

A'4(PC1)

"""'

.

"'"

[~~Rj

DATA BUS
DB;'D87

)

SYNC

UPTOI4K-244
OFEXTERNAt..

",..

me

.............

._

UP TO'IK.J44

.IOORIIIEMORY

a0101).F1'f'F

DATA BUS

_D87

( VECTORS AT )
FFFA-fFFF

[ACnY"IIOM]
.....
~ooo".

O1QO.lfFF

(VEC'fOftSAT

ADDAESS8US

Figure 4-1a.

/

..llnI

AI3IPCI,

....,2, ...

HITS

Oii

..lITe

RUl1Q OR AIIDO/13

••mI

PORTA

Y•

1IM11QORRSIOO/13

...-

)

Y.

'."TO

...,.

...,.

ADORI!.SauS

'5

A;-A'Z,A15

Figure 4-1b.

Full Address Mode

3-87

Normal Bus Mode

",....".,

R6501Q

One-Chip Microprocessor
Table 4·4.

Port C Control and Usage
FULL ADDRESS
MODE

liD MODE

MCR7 ~ a
MCR6 = a

MCR7'= a
MCR6 = 1

SIGNAL

PIN

PIN
NAME

#
54
55
56
57
58
59

Pca
PCl
PC2
PC3
PC4
PC5
PC6
PC7

60
61

NAME

PCO
PC1
PC2

SIGNAL
TYPE

NAME

PCO
PC1
PC2
PC3
PC4
PCS
PC6
PC7

1/0(1)
1/0(1)
1/0(1)

pea

1/0(1)
1/0(1)
1/0(1)

PC4
PCS
A13
A14

TYPE
(1)

OUTPUT (2)
OUTPUT (2)

I/O

1/0
I/O
I/O

1/0
I/O
I/O
I/O

NOTES:
1. Resistive Pull·Up, Active Buffer Pull-Down
2. Active Buffer Pull-Up and Pull-Down

Table 4·5.

Port 0 Control and Usage

1/0 MODES

PIN

MCR7 = 0
MCR6 = X
MCR5 = 0

MCR7 = 0
MCR6 = X
MCR5 = 1

SIGNAL

SIGNAL

#

PIN
NAME

62
63
64
1
2
3
4
5

PD~

PD~

PDl
PD2
PD3
PD4
PD5
PD6
PD7

PDl
PD2
PD3
PD4
PD5
PD6
PD7

NAME

TYPE
(1)

NAME

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

PDl
PD2
PD3
PD4
PD5
PD6
PD7

PD~

NOTES:
1. Tn-State Buffer IS In High Impedance Mode
2 Tri-State Buffer is in Active Mode

3-88

TYPE
(2)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

One-Chip Microprocessor

R6501Q

SECTION 5
SERIAL INPUT/OUTPUT CHANNEL
ASYNCHRONOUS MODE WITHOUT PAlmv

The device provides a full duplex Serial I/O channel with programmable bit rates and operating modes. The senal I/O
functions are controlled by the Senal Communication Control
Register (SCCR). The SCCR bit. assignment IS shown in
Figure 5-1. The serial bit rate is determined by Counter A for
all modes except the Receiver Shift Register (RCVR SIR)
mode for which an external shift clock must be provided. The
maximum data rate using the Internal clock IS 62.5K bits per
second (at ¢2 = 1 MHZ). The transmitter (XMTR) and receiver
(RCVR) can be independently programmed to operate in
different modes and can be Independently enabled or
disabled.

_____8~"~IT~DA_TA__________________~~~'S~TD~P~
~~lll______
"_IT_D_AT_A______________~__'_ST~DP__~

~~,,~I

&-BIT CATA

25TO"

5·81T OATA

2·5TOP

ASYNCHRONOUS MODE WITH PARtTY
a·81T DATA

IPA~ITY I
IPA~ITY I

SCCR

o Parity Disable
o
o
1
1

o
o
o
1
o XMTR
1 XMTR

Figure 5-1.

2 STOP

2 STOP

SHIFT REGISTER MODE 8-BIT DATA

1 Parity Enable
O~8 Bits/Char
1 ~ 7 Bits/Char
O~ 6 Bits/Char
1 ~ 5 Bits/Char

M·,

I

WOROM+l

SHIFT REGISTER CLOCK (PA4)

-11.

o XMTR & RCVR ASYN Mode

Figure 5-2.

1 XMTR ASYN, RCVR SIR
X XMTR SIR, RCVR ASYN

n

SIO Data Modes

In the SIR mode, eight data bits are always shifted out. Blts/
character and parity control bits are ignored. The serial data
is shifted out via the SO output (PA6) and the shift clock IS
available at the CA (PA4) pin. When the transmitter underruns in the SIR mode the SO output and shift clock are held
in a high state.

RCVR Disable
RCVR Enable
Disable
Enable

Serial Communication Control Register

Except for the Receiver Shift Register Mode (RCVR SIR), all
XMTR and RCVR bit rates will occur at one sixteenth of the
Counter A interval timer rate. Counter A IS forced into an
interval timer mode whenever the serial I/O is enabled In a
mode requiring an internal clock.

The XMTR Interrupt Flag bit (IFR7) is controlled by Serial
Communication Status Register bits SCSR5, SCSR6 and
SCSR7.
IFR7

Whenever Counter A is required as a timing source It must
be loaded with the hexadecimal code that selects the data
rate for the serial I/O Port. Refer to Counter A (paragraph
6.1) for a table of hexadecimal values to represent the desired
data rate.

= SCSR6 (SCSR5 + SCSR7)

5.2 RECEIVER OPERATION (RCVR)
The receiver and its selected control and status functions are
enabled when SCCR-6 is set to a "1." In the ASYN mode,
data format must have a start bit, the appropriate number of
data bits, a parity bit (if enabled), and one stop bit. Refer to
paragraph 5.1 for a diagram of bit allocations. The receiver
bit period IS divided into 8 sub-intervals for internal synchronization. The receiver bit stream is synchronized by the start
bit and a strobe Signal is generated at the approximate center
of each incoming bit. Refer 10 Figure 5-3 for ASYN Receive
Data Timing. The character assembly process does not start
if the start bit signal is less than one-half the bit time after a
low level is detected on the Receive Data Input. Framing
error, over-run, and parity error conditions or a RCVR Data
Register Full will set the appropriate status bits. Any of the
above conditions will cause an Interrupt Request if the
Receiver Interrupt Enable bit is set to logic 1.

5.1 TRANSMITTER OPERATION (XTMR)
The XTMR operation and the transmitter related control/
status functions are enabled by bit 7 of the Serial Communications Control Register (SCCR). The transmitter, when in
the Asynchronous (ASYN) mode, automatically adds a start
bit, one or two stop bits, and, when enabled, a parity bit to
the transmitted data. A word of transmitted data (in asynchronous parity mode) can have 5, 6, 7, or 8 bits of data.
The nine data modes are shown in Figure 5-2. When parity is
disabled, the 5, 6, 7 or 8 bits of data are terminated with two
stop bits.

3-89

_I

One-Chip Microprocessor

R6501Q

::

I

Input!
SlIrt Bn

LSB

I

I

received data has a parity error. This bit is cleared
by reading the Receiver Data Register or by RES.
SCSR 3: Framing Error-Set to a logic 1 when the received
data contains a zero bit after the last data or parity
bit in the stop bit slot. Cleared by readi ng the
Receiver Data Register or by RES (ASYN Mode
only).
SCSR 4: Wake-Up-Set to a logic 1 by writing a "1" in bit
4 of address: 0016. The Wake-Up bit is cleared by
RES or when the receiver detects a string of ten
consecutive 1'so When the Wake-Up bit is set
SCSRO through SCSR3 are inhibited.
SCSR 5: End of Transmission-Set to a logic 1 by writing
a "1" in bit pOsitIOn 5 of address: 0016. The End
of Transmission bit is cleared by RES or upon
writing a new data word into the Transmitter Data
Register. When the End-of-Transmission bit is true
the Transmitter Register Empty bit is disabled until
a Transmitter Under-Run occurs.

I

Stop Bit Stop Bit

• Serlellnput Dell Sh_ In

Figure 5-3.

ASYN Receive Data Timing

In the SIR mode, an external shift clock must be provided at
CA (PM) pin along with 8 bits of serial data (LSB first) at the
SI input (PA7). The maximum data rate using an external
shift clock is one-eighth the internal clock rate. Refer to
Figure 5-4 for SIR Mode Timing.

;:':,':1
External

==:r:=::r==r:::=:r:

I Data In

:::

SCSR 6: Transmitter Data Register Empty-Set to a logic
1 when the contents of the Transmitter Data Register are transferred to the Transmitter Shift Register. Cleared upon writing new data into the
Transmit Data Register. This bit is initialized to a
logic 1 by RES.
SCSR 7: Transmitter Under-Run-Set to a logic 1 when the
last data bit is transmitted if the transmitter is in a
SIR Mode or when the last stop bit is transmitted
if the XMTR is in the ASYN Mode while the Transmitter Data Register Empty Bit is set. Cleared by
a transfer of new data into the Transmitter Shift
Register or by RES.

Shlll~~

Clock

Serial
Output
Shill

I

I

: "--r--'T""--r---,..__..L..._-'-_ _......_"'"'-

OataOut

CIOCk~~

. Serlllinput Data Shifted In
•. Se,II' Output Data Makes Transition

Figure 5-4.

SIR Mode Timing

A RCVR Interrupt (IFR6) IS generated whenever any of
SCSRO-3 are true.

SCSR

5.3 SERIAL COMMUNICATION STATUS
REGISTER (SCSR)
The Serial Communication Status Register (SCSR) holds
information on various comrnunication error conditions, status
of the transmitter and receiver data registers, a transmitter
end-of-transmisslon condition, and a receiver Idle line condition (Wake-Up Feature). The SCSR bit assignment is shown
in Figure 5-5. Bit assignments and functions of the SCSR are
as follOWS:

Parity Error

Frame Error
Wake-Up

End of Transmission
XMTR Data Reg Empty

SCSR 0: Receiver Data Register Full-Set to a logic 1 when
a character is transferred from the Receiver Shift
Register to the Receiver Data Register. This bit is
cleared by reading the Receiver Data Register, or
by RES and is disabled if SCCR 6 = O. The SCSR
o bit will not be set to a logic 1 if the received data
contains an error condition; instead, a corresponding error bit will be set to a logic 1.

XMTR Under-Run

Figure 5-5. SCSR Bit Allocations

5.4 WAKE-UP FEATURE
In a multi-distributed microprocessor or microcomputer appliations, a destination address is usually included at the beginning of the message. The Wake-Up Feature allows non-selected
CPU's to ignore the remainder of the message until the beginning of the next message by setting the Wake-Up bit. As long
as the Wake-Up flag is true, the Receiver Data Register Full Flag
remains false. The Wake-Up bit is automatically cleared when
the receiver detects a string of eleven consecutive 1's which indicates an idle transmit line. When the next byte is received, the
Receiver Data Register Full Flag signals the CPU to wake-up
and read the received data.

SCSR 1: Over-Run Error-Set to a logic 1 when a new character is transferred from the Receiver Shift Register with the last character still in the Receiver
Data Register. This bit is cleared by reading the
Receiver Data Register or by RES.
SCSR 2: Parity Error-Set to logic 1 when the RCVR is in
the ASYN Mode, Parity Enable bit is set, and the
3-90

R6501Q

One-Chip Microprocessor

SECTION 6
COUNTER/TIMERS
The device contains two 16-bit counters (Counter A and
Counter B) and three 16-bit latches asSOCiated with the
counters. Counter A has one 16-bit latch and Counter B has
two 16-bit latches. Each counter can be independently programmed to operate in one of four modes:

Upper Latch A before the contents of the 16-bit latch are
transferred to Counter A. Counter A is set to the latch value
whenever Counter A underflows. When Counter A decrements from 0000 the next counter value will be the latch
value-not FFFF-and the Counter A Underflow Flag (IFR
4) will be set to "1". This bit may be cleared by reading the
Lower Counter A at location 0018, by writing to address location 001 A, or by RES.

Counter B

Counter A

• Retriggerable Interval Counter
• Asymmetrical Pulse
Generation
• Interval Timer
• Event Counter

• Pulse width
measurement
• Pulse Generation
• Interval Timer
• Event Counter

Counter A operates in any of four modes. These modes are
selected by the Counter A Mode Control bits in the Control
Register.

Operating modes of Counter A and Counter B are controlled
by the Mode Control Register. All counting begins at the
initialization value and decrements. When modes are selected
requiring a counter input/output line, PA4 is automatically
selected for Counter A and PAS is automatically selected for
Counter B (see Table 4.2).

MCRO
(bit 0)

0
0

0
1
0

Made

Interval Timer
Pulse Generation
Event Counter
Pulse Width Measurement

The Interval Timer, Pulse Generation, and Pulse Width Measurement Modes are
clock counter modes. The Event
Counter Mode counts the occurrences of an extemal event
on the CNTR line.

6.1 COUNTER A

!62

Counter A consists of a 16-bit counter and a 16-bit latch
organized as follows: Lower Counter A (LCA), Upper Counter
A (UCA), Lower Latch A (LLA), and Upper Latch A (ULA).
The counter contains the count of either !Y.! clock pu lses or
external events, depending on the counter mode selected.
The contents of Counter A may be read any time by executing a read at location 0019 for the Upper Counter A and
at location 001A or location 0018 for the Lower Counter A.
A read at location 0018 also clears the Counter A Underflow
Flag (IFR4).

The Counter is set to the Interval Timer Mode (00) when a
RES signal is generated.

6.1.1 Interval Timer
In the Interval Timer mode the Counter is initialized to the
Latch value by either of two conditions:
1. When the Counter is decremented from 0000, the next
Counter value is the Latch value (not FFFF).

The 16-bit latch contains the counter initialization value and
can be loaded at any time by executing a write to the Upper
Latch A at location 0019 and the Lower Latch A at location
0018. In either case, the contents of the accumulator are
copied into the applicable latch register.

2. When a write operation is performed to the Load Upper
Latch and Transfer Latch to Counter address 001 A,
the Counter is loaded with the Latch value. Note that
the contents of the Accumulator are loaded into the
Upper Latch before the Latch value is transferred to
the Counter.

Counter A can be started at any time by writing to address:
001 A. The contents of the accumulator will be copied into the

.

The Counter value is decremented by one count at the 02
clock rate. The 16-bit Counter can hold from 1 to 65535
counts. The Counter Timer capacity is therefore lJLS to 65.535
ms at the 1 MHz ~2 clock rate or 0.5 ,.,.s to 32.767 ms at the
2 MHz ~2 clock rate. Time intervals greater than the maximum Counter value can be easily measured by counting
IRQ interrupt requests in the counter IRQ interrupt routine.

COUN11!R U.....,.l.LOW

I

I

COON11!R.-~-.r-~-.--~-r--~-rI~(~UL~.~~I~(~U~~L~L~I'~ll---

awNnR~nNN"~MWm

MeRl
(bit 1)

I

rc-------------+,----------BET ANY nME BEFORE

COUNTER UNDERFLOW FLAG

COUNTER UNDER.LOW rl---:-----------

When Counter A decrements from 0000, the Counter A
Underflow (IFR4) is set to logic 1. If the Counter A Interrupt
Enable Bit (IER4) is also set, an IRQ interrupt request Will be
generated. The Counter A Underflow bit in the Interrupt Flag
Register can be examined in the IRQ interrupt routine to
determine that the IRQ was generated by the Counter A
Underflow.

I
Figure 6·1.

Interval Timer Timing Diagram

3-91

D

One-Chip Microprocessor

R6501Q
While the timer is operating in the Interval Timer Mode, PA4
operates as a PA I/O bit.

The Counter A underflow flag will be set only when the count
in the timer reaches zero. Upon reaching zero the timer will
be loaded with the latch value and continue counting down
as long as the CA pin is held low. After the counter is stopped
by a high level on CA, the count will hold as long as CA
remains high. Any further low levels on CA will again cause
the counter to count down from its present value. The state
of the CA line can be determined by testing the state of PA4.

A timing diagram of the Interval Timer Mode IS shown in
Figure 6-1.

6.1.2 Pulse Generation Mode
In the Pulse Generation mode, the CA line operates as a
Counter Output. The line toggles from low to high or from
high to low whenever a Counter A Underflow occurs or a
write is performed to address 001A.

A timing diagram for the Pulse Width Measurement Mode is
shown in Figure 6.3.

The normal output waveform is a symmetrical square-wave.
The CA output is Initialized high when entering the mode and
transitions low when writing to 001A.
Asymmetric waveforms can be generated if the value of the
latch is changed after each counter underflow.

COUNT

A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one
occurrence of the output toggle condition.

N

N-1

N-2

N-3

Figure 6-3. Pulse Width Measurement

6.1.3 Event Counter Mode
In thiS mode the CA is used as an Event Input line, and the
Counter will decrement With each rising edge detected on
thiS line. The maximum rate at which this edge can be
detected is one-half the ~2 clock rate.

6.1.5 Serial 1/0 Data Rate Generation
Counter A also provides clock timing for the Serial I/O which
establishes the data rate for the Serial I/O port. When the
Serial I/O is enabled, Counter A is forced to operate at the
internal clock rate. Counter A is not required for the RCVR
SIR mode. The Counter I/O (PA4) may also be required 10
support the Serial I/O (see Table 4-2).

The Counter can count up to 65,535 occurrences before
underflowing. As in the other modes, the Counter A Underflow bit (IER4) IS set to logic 1 if the underflow occurs.
Figure 6.2 is a timing diagram of the Event Counter Mode.
;2

PDSU}-20V

CNTR

COUNT

Table 6-1 identifies the values to be loaded in Counter A for
selecting standard data rates with a ~2 clock rate of 1 MHz
and 2 MHz. Although Table 6-1 identifies only the more
common data rates, any data rate from 1 to 62.5K bps can
be selected by using the formula:

120V I Day

o,v

~Tpw ~Tpw~
N

I

N-1

Figure 6-2.

N
N-2

=

~2
16 x bps

-1

where
N

Event Counter Mode

¢2
bps

6.1.4 Pulse Width Measurement Mode

decimal value to be loaded into Counter A using
ItS hexadeCimal eqUivalent.
the clock frequency (1 MHz or 2 MHz)
the desired data rate.
NOTE

This mode allows the accurate measurement of a low pulse
duration on the CA line. The Counter decrements by one
count at the ~2 clock rate as long as the CA line is held in
the low state. The Counter IS stopped when CA is in the high
state.

In Table 6-1 you will notice that the standard data rate
and the actual data rate may be slightly different.
Transmitter and receiver errors of 1 .5% or less are
acceptable. A revised clock rate is included in Table
6-1 for those baud rates which fall outside this limit.

3-92

One-Chip Microprocessor

R6501Q
Table 6·1.

Counter A Values for Baud Rate Selection
03

HEXADECIMAL
STANDARD
VALUE
BAUD
RATE
1 MHz 2 MHz

50
75
110
150
300
600
1200
2400
3600
4800
7200
9600

04E1
0340
0237
01AO
OOCF
0067
0033
0019
0010
OOOC
0008
0006

09C3
0682
046F
0340
01AO
OOCF
0067
0033
0021
0019
0010
OOOC

ACTUAL
BAUD
RATE AT

6.2.1 Retriggerable Interval Timer Mode
When operating in the Retriggerable Interval Timer mode,
Counter B is initialized to the latch value by writing to address
001 E, by a Counter B underflow, or whenever a positive edge
occurs on the CB pin (PAS). The Counter B interrupt flag will
be set if the counter underflows before a positive edge occurs
on the CB line. Figure 6-4 illustrates the operation.

CLOCK RATE
NEEDED
TO GET
STANDARD
BAUD RATE

1 MHz

2 MHz

1 MHz 2 MHz

50.00
75.03
110.04
149.88
300.48
60096
1201.92
2403.85
3676.47
4807.69
6944.44
8928.57

50.00
74.99
110.04
150.06
299.76
600.96
1201.92
2403.85
3676.47
480769
7352.94
9615.38

1.0000
1.0000
1.0000
1.0000
1.0000
10000
1.0000
1.0000
0.9792
10000
1.0368
1.0752

2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
1.9584
2.0000
1.9584
2.0000

Counter
Underflows

/ l / Reset by Software

-IIIL_____

Counter B _ _ _ _ _ _ _

Flag

Figure 6·4.

6.2 COUNTER B
Counter B consists of a 16-bit counter and two 16-bit latches
organized as follows: Lower Counter B (LCB), Upper Counter
B (UCB), Lower Latch B (LLB), Upper Latch B (ULB), Lower
Latch C (LLC), and Upper Latch C (ULC). Latch C is used
only in the asymmetrical pulse generation mode. The counter
contains the count of either ~2 clock pulses or external
events depending on the counter mode selected. The contents of Counter B may be read any time by executing a Read
at location 0010 for the Upper Counter B and at location
001E or 001C for the Lower Counter B. A Read at location
001C also clears the Counter B Underflow Flag.

Counter B Retriggerable Interval Timer Mode

6.2.2 Asymmetrical Pulse Generation Mode
Counter B has a special Asymmetrical Pulse Generation
Mode whereby a pulse train with programmable pulse width
and period can be generated without the processor intervention once the latch values are initialized.
In this mode, the 16-bit Latch B is initialized with a value
which corresponds to the duration between pulses (referred
to as 0 in the following descriptions). The 16-bit Latch C is
initialized with a value corresponding to the desired pulse
width (referred to as P in the following descriptions). The
initialization sequence for Latch Band C and the starting of
a counting sequence are as follows:

Latch B contains the counter initialization value and can be
loaded at any time by executing a Write to the Upper Latch
B at location 0010 and the Lower Latch B at location 001C.
In each case, the contents of the accumulator are copied into
the applicable latch register.

1. The lower 8 bits of P are loaded into LLB by writing to
address 001C; the upper 8 bits of P are loaded into
ULB and the full 16 bits are transferred to Latch C by
writing to address location 0010. At this point both
Latch B and Latch C contain the value of P.

Counter B can be initialized at any time by writing to address:
001 E. The contents of the accumulator is copied into the
Upper Latch B before the value in the 16-bit Latch B is transferred to Counter B. Counter B will also be set to the latch
value and the Counter B Underflow Flag bit (IFR5) will be set
to a "1" whenever Counter B underflows by decrementing
from 0000.

2. The lower 8 bits of 0 are loaded into LLB by writing to
address 001C; the upper 8 bits of 0 are loaded into
ULB by writing to address location 001 E. Writing to
address location 001 E also causes the contents of the
16-bit Latch B to be downloaded into the Counter B
and the CB output to go low as shown in Figure 6-5.

IFR 5 may be cleared by reading the Lower Counter B at
location 001 C, by writing to address location 001 E, or by
RES.

3. When Counter B underflow occurs the contents of the
Latch C are loaded into the Counter B and the CB output toggles to a high level, staying high until another
underflow occurs. Latch B is then down-loaded and the
CB output toggles to a low level repeating the whole
process.

Counter B operates In the same manner as Counter A In the
Interval Timer and Event Counter modes. The Pulse Width
Measurement Mode is replaced by the Retriggerable Interval
Timer mode and the Pulse Generation mode IS replaced by
the Asymmetrical Pulse Generation Mode. Mode Control
Register bits MCR2 and MCR3 select the four Counter B
modes in a Similar manner and coding as MCRD and MCR1
select the modes of Counter A.

3-93

One-Chip Microprocessor

R6501Q

SECTION 7
POWER ON/INITIALIZATION CONSIDERATIONS
7.1 POWER ON TIMING

7.3 RESET (RES) CONDITIONING

After application of Vee and V RR power to the device, RES
must be held low for at least eight pJ2 clock cycles after Vee
reaches operating range and the internal oscillator has stabilized. This stabilization time is dependent upon the input
Vee voltage and performance of the Internal oscillator. The
clock can be monitored at ~2 (pin 3). Figure 7-1 illustrates
the power turn-on waveforms. Clock stabilization time is typically 20 ms.

When RES is driven from low to high the device is put in a
reset state causing the registers and 1/0 ports to be configured as shown in Table 7-1.

Table 7-1.

REGISTERS
Processor Status
Mode Control (MCR)
Int. Enable (IER)
Int. Flag (IFR)
Ser. Com. Control (SCCR)
Ser. Com. Status (SCSR)

y,;.~--=<:

_0.

---------------------~

Figure 7·1.

Power Turn-On Timing Detail

5

4

3

2

0
0
0
0
0

0
0
0
0
1

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

1
0
0
0
0
0

0

0
0
0
0
0

0
0
0
0
0

Any initialization process for the device should include a
RES, as indicated in the preceeding paragraphs. After stabilization of the internal, clock (if a power on situation) an
initialization routine should be executed to perform (as a
minimum) the following functions:

1.
2.
3.
4.
5.

The Stack Pointer should be set
Clear or Set Decimal Mode
Set or Clear Carry Flag
Set up Mode Controls as required
Clear Interrupts

A typical initialization subroutine could be as follows:

3

LDX
TXS
CLD
SEC

1.3. Counter B .....- Latch B (D)
2&4. Cou..... B _

6

7.4 INITIALIZATION

the device sets the Interrupt Mask Bit-bit 2 of the Processor Status Registerand initiates a reset vector fetch at address FFFC and FFFD
to begin user program execution. All ofthe 1/0 ports (PA, PB,
PC, PD) will be forced to the high (logic 1) state. All bits of
the Control Register will be cleared to logic 0 causing the
Interval Timers counter mode (mode 00) to be selected and
allJnterrupt enabled bits to be reset.

2

7

All RAM and other CPU registers will initialize in a random,
non-repeatable data pattern.

7.2 POWER-ON RESET
When RES goes from low to high,

CB Oulput

of 1/0 Ports and Registers

PORTS
PA Latch
PB Latch
PC Latch
PO Latch

12 _-""..JllfWIj'MIWV\J

...

RES 1~ltlalizatlon

Latch C (p)

CLI

Figure 6-5. Counter B Pulse Generation

3-94

Load stack pOinter sta.rting address into

X Register
Transfer X Register value to Stack Pointer
Clear Decimal Mode
Set Carry Flag
Set-up Mode Control and
special function registers
and clear RAM as required
Clear Interrupts

One-Chip Microprocessor

R6501Q

APPENDIX A
ENHANCED R6502 INSTRUCTION SET
This appendix contains a summary of the Enhanced R6502
instruction set. For detailed information, consult the R6502
Microcomputer System Programming Manual, Document
29650 N30. The four instructions notated with a ' are added
instructions to enhance the standard 6502 instruction set.

A.1 INSTRUCTION SET IN ALPHABETIC
SEQUENCE
ADC
AND
ASL
'BBR
'BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS

Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC
CLD
CLI
CLV
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

EOR

"Exclusive-Or" Memory with
Accumulator

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Index Y by One

JMP
JSR

Jump to New Location
Jump to New Location Saving Return
Address

LDA
LDX
LDY
LSR

Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or
Accumulator)

NOP

No Operation

ORA

"OR" Memory with Accumulator

PHA
PHP
PLA
PLP

Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Proces~or Status from Stack

'RMB
ROL

Reset Memory Bit
Rotate One Bit Left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine

ROR
RTI
RTS
SBC
SEC
SED
SEI
'SMB
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA

3-95

Subtract Memory from Accumulator with
Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer

Accumulator to Index X
Accumulator to Index Y
Stack Pointer to Index X
Index X to Accumulator
Index X to Stack Register
Index Y to Accumulator

A.2 INSTRUCTION SET SUMMARY TABLE

:u
en

ENHANCED R6502 INSTRUCTION SET

PROCESSOR STATUS
COOES

INSTRUCTIONS
IMMEDIATEIABSOLUTElzERO PAGel ACCUM

OPERATION

MNEMONIC

ADC
AND

A-M-C----A
A M--->A

ASl

C~~<-{I

BBR[#(O-7)]

BranchonM.=O
Branch on M,=l
Branch on C~O

88S[#(0-7)]

BCC
BCS
BEQ

BIT
BMI
BNE

BPl

cO

'"

I # loP I

O~V

29222043253
OE 6 3 06 5

#

(INO). Y

lopt

n

31

5

IZ PAGE, X

I # lop I

n

I

I

ABS, X

ASS, Y

I RELATIVE I

INDIRECT

1# lop I n I # lop I n I # lop I n I # I OP I

21

6

2

2

35

n

IZ

BIT ADDRESSING (OP BY BIT #)

PAGE, Y

I # I opt

n

I

#

I 0

I 1

B8

~~

4912 12 140
EE

0

N V

z

C

Z

•

Z C

2 12

· z

;I ~~

1

411 61 21 51

3 12

• 0

I

512

I

•

0

N
N
N

•

N

•

· z

N •
N
N

Z
Z
Z

N

•••••

Z

N •••••
(RestOred)

Z

N

Z C

z

C
C
C

21 DE 1 7 I 3

~gl;I;1591413

55
F6

~~ I; I~
6C

All 6 I 2 1 B1 I 5 1 2 I 851 4 1 2 I BO 1 4 1 3 I ~~
4A

!2

1

5 13

I: I;

861 412

~;I~I;I~~I;I;

1 2 11

~~ I~ I; I ~~ I ~ I; I~: I ; I~

E91 2121 Eol 41 3[ E51 3

I; I;

210014131091413

061 6

4C 1313
A9I'I'I!~ : A6
46

(1)

1

~;I ~;I !~I ~~1~~16~1 ~~I;~

2 11

~: I; I~

X ·l---+X
Yel ~y

Atm Int
Atm Sub
A-M-C--+A
l--->C
1---->0
l--->T
l--+M" (5)
A--+M
X--+M
Y--->M
A--+X
A--+Y

2

• 0
• 0
Cli 61 21011 5 I 2 [ 051 4

l-~X

Y l---+Y

~

3

N •
N •

M,M••

C91'I'ICOl4131 C5

(1)

4

0010

EO 2 2 EC 4 3 E4
C022CC43C4
CE 6 3 C6

M'l---+M

5

30 12 12

08181', 11
58 ,

M l---+M

6

SI617INV.BDIZC

30433943
1E 7 3

FO

Jump to New lee
Jump 5ub
AS
M--+A (1)
M--+X (1)
A222AE4 3
AO 2 2 AC
A4
M--+Y (1)
4E
O--+~--+C
No Operation
AVM--+A(1)
09 I 2 I 2 100 j 4 j 3[ 05 j 3 12
A--+Ms 5 1--+5
P--+Ms S 1--+S
S ·1--+S Ms~A
S· 1--+5 Ms--+P
O--+M" (5)
~

5MB[#(0~7)1

I

90BO [',

INX
INY

STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA

n

61 I 61 'I 71 I 51'175 I 4 '1 70 [4[31"1 413
16

DA j 2 11

JMP
J5R
LDA
LOX
LOY
l5R
NOP
ORA
PHA
PHP
PLA
PLP
RMB[#(O~7)1

I

(IND, X)

(2)
(2)

Y M

AVM~A

I

(2)
(2)
(2)

A M (1)

X

IMPLIED

691'1'160 [4[3[65[3 I'

O~I

X M

I

I # I OP I n 1# lopl

O~D

CMP
CPX
CPY

ROL
ROR
ATt
RTS
SBC
SEC
SED
SEI

n

O~C

ClV

EOA

n

00 I 7 11

Break

!NC

I # I OP I

2CI4131241312

Branch on V=O
Brancn on V=l

DEC
OEX
DEY

Co>

8ral'lchonZ=1

n

(5}(2)
(5){2)
(2)
(2)
(2)

AAM
Branch on N=l
Branch onZ=O
Branch on N~O

BVS

ClC
ClD
CLI

(1)

BranchonC~l

BRK

8VC

(4)(1)

OP I n I # loP I

g....
o

o •

z c

EA I 2 11

4813
0868 43 I 1
28

011 61 2 I

11

I 5

I

2

I

151 4 I 2

110 I

4

I

3 I 19 I 4 13

411

•

071 17 I 27 I 37 1471 57 1 67 [77

~I~I;I;~I;

~~ I ~ I~

38[' 11
78 ,
FB

•

N •

Z C
(Restored)

Ell 61 2 1 Fl I 5

I

2 I F51 4

I

2 I FD

I

N V ••••

4 I 3 I F9 I 4 I 3

Z (3)
1

,

·1
·1

CD

o•
::r

87i971A71B71c71D71E71F7

80[4[3[85[3['

811

8E438632
8C438432

s-.x
X--+A
X--+S
Y--+A

NOTES
1 Add 1 to N If page boundary IS crossed
2 Add 1 to N If branch occurs to same page
Add 2 to N If branch occurs to different page
Carry not = Borrow
If In decimal mode Z flag IS Invalid
accumulator must be checked on zero result
5 Effects 8·blt data field of the specified zero page address

6[ 21 91

I 6 I 2 I 951 4 I 2 1 901 5 1 3 Ie, I 5 I 3
961 412

A8
BA
.AA
BA

I'l'
2

1

2
,

1

941 41 2

9A ,
98

211

M.

LEGEND

x
y
A
M

M,
M.

M,

Index X
Index Y
Accumulator
Memory per effective address
Memory per stack pomter
Selecter zero page memory bit
Memory Bit 7

A

V
~

"

"C

•

Z

N •
N •••••

Z

N

z .

•••••

o::::J

•

Memory BIt 6
Add
Subtract
And
0<
ExcluSive Or
Number of cycles
Number of Bytes

s:

n
-.:

o
-.:
on

"C
CD

(I).
(I)

o-.:

R6501Q

One-Chip Microprocessor

A.3 INSTRUCTION CODE MATRIX
D

BRK
D Implied
1 7

LSD 0

5l

::;;

A

ORA
ZP
2 3

ASL
ZP
2 5

RMBO
ZP
2 5

PHP
Implied
I 3

ORA
IMM
2 2

ASL

BPL
ORA
Relative (IND), Y
2 2"
2 5'

ORA
Zp, X
2 4

ASL
ZP, X
2 6

RMB,
ZP
2 5

CLC
Implied
2

ORA
ABS,Y
3 4'

JSR
AND
Absolute (IND, X)
3 6
2 6

BIT
ZP

AND
ZP

ROL
ZP

2 3

2 5

RMB2
ZP
2 5

PLP
Implied
4

AND
IMM
2 2

BMI
AND
Relative (IND, Y)
2 2"
2 5'

AND
ZP, X
2 4

ROL
Zp, X
2 6

RMB3
ZP
2 5

SEC
Implied
2

AND
ABS, Y
3 4'

RTI
EOR
Implied (IND, X)
I 6
2 6

EOR
ZP
2 3

LSR
ZP
2 5

RMB4
ZP
2 5

PHA
Implied
3

EOR
IMM
2 2

EOR
ZP, X
2 4

LSR
Zp, X
2 6

RMB5
ZP
2 5

CLI
Implied
2

EOR
ABS,Y
3 4'

RTS
ADC
Implied (IND, X)
I 6
2 6

ADC
ZP
2 3

ROR
ZP
2 5

RMB6
ZP
2 5

PLA
Implied
I 4

ADC
IMM
2 2

BVS
ADC
Relative (IND, Y)
2 2"
2 5'

ADC
ZP, X

ROR
Zp, X
2 a

RMB7
ZP
2 5

SEI
Implied
2

ADC
ABS,Y
3 4'

STX
ZP

DEY
Implied
2

BVC
2

2"

EOR
2

5'

2 4

,

2

BIT
ABS
3 4

ROL

,

Accum
2

JMP
ABS
3 3

LSR

,

Accum
2

ROR

JMP
Indirect
3 5

,

Accum
2

F
BBRO
ZP
3 5"

ORA
ABS, X
3 4'

ASL
ABS, X
3 7

3

AND
ABS

3 4

ROL
ABS
3 6

3

AND
ABS, X
3 4'

ROL
ABS,X
3 7

BBR3
ZP
3 5"

3

EOR
ABS
3 4

LSR
ABS
3 6

BBR4
ZP
3 5"

4

EOR
ABS,X
3 4'

LSR
ABS, X
3 7

ADC
ABS

ROR
ABS
3 6

3 5"

3 4'

ROR
ABS, X
3 ?

BBR?
ZP
3 5"

STA
ABS

STX
ABS

3 4

3 4

BBSO
ZP
3 5"

3 4
ADC
ABS, X

o

BBR'
ZP
5"

BBR2
ZP
5"

BBR5
ZP
5"

3

BBRa
ZP

2 3

STA
Relative (IND, Y)
2 2"
2 6

STY
ZP, X
2 4

STA
Zp, X
2 4

STX
ZP, Y
2 4

5MBI
ZP
2 5

TYA
Implied
2

STA
ABS,Y
3 5

TXS
Implied
I 2

LOY
ZP
2 3

LOA
ZP
2 3

LOX
ZP
2 3

5MB2
ZP
2 5

TAY
Implied
I 2

LOA
IMM
2 2

TAX
Implied
I 2

LOY
ABS
3 4

3 4

LOX
ABS
3 4

3 5"

LOY
ZP, X
2 4

LOA
ZP, X
2 4

LOX
ZP, Y
2 4

5MB3
ZP
2 5

CLV
Implied

LOA
ABS, Y
3 4'

TSX
Implied
I 2

LOY
ABS, X
3 4'

LOA
ABS, X
3 4'

LOX
ABS,Y
3 4'

BBS3
ZP
3 5"

B

CPY
ZP

CMP
ZP
2 3

DEC
ZP
2 5

5MB4
ZP
2 5

INY
Implied
2

CMP
IMM
2 2

DEX
Implied
2

CPY
ABS
3 4

CMP
ABS

DEC
ABS
3 6

BBS4
ZP
3 5"

C

CMP
ZP, X
2 4

DEC
ZP, X
2 6

5MB5
ZP
2 5

CLD
Implied
2

CMP
ABS,Y

CMP
ABS,X

3 4'

3 4'

DEC
ABS, X
3 7

3 5"

SBC
ZP
2 3

INC
ZP

5MB6
ZP

2 5

2 5

INX
Implied
2

INC

5MB?

ZP, x
2 6

Zp

LOY
IMM
2 2

LOA
(IND, X)
2 6

BCS

LOA

Relative (IND), Y
2"

CPY
IMM
2 2
BNE

"

,

I

E
ASL
ABS
3 6

5MBO
ZP
2 5

2

5'

CMP
(IND, X)
2 6

LOX
IMM
2 2

2 3

CMP

Relative (IND), Y
2

E

,

Accum

o
ORA
ABS
3 4

STA
ZP
2 3

2

o

,

C

STY
ZP
2 3

BCC

C

,

-Addressing Mode
-Instruction Bytes; Machine Cycles

STA
(IND, X)
2 6

8

B

,

2 3

Relative (IND), Y

A

B

9

BRK
ORA
Implied (INO, X)
I 7
2 6

-op Code

2"

2

5'

CPX
IMM
2 2

SBC
(IND,X)
2 6

BEQ

SBC

Relath/s ([ND), v
2

2"

o

2

5'

CPX
ZP
2 3

SBC

ZP,

x

2

4

8

2

5

TXA
Implied
I 2

,
,

,

2

,
,

,

SED

,,,,p'
, ,ed
2

7

SBC
IMM

2

2

STY
ABS
3 4

,

NOP
Implied
2

,

BBSI
ZP

3 5

3 5"

LOA
ABS

3 4

SBC
ABS

INC
ABS

BBS6
ZP

3 4

3 a

3 5"

3 4'

B

BBS5
ZP

CPX
ABS

SBC
INC
ABS, X IIBS, X
3 4'
3 ?

A

BBS2
ZP

3 4

SBC
.1I8S, Y

9

STA
ABS,X

C

o

E

BBS7
ZP
3 5"

A

o
E

F

F

• Add 1 to N if page boundary is crossed,
"Add 1 to N if branch occurs to same page;
add 2 to N if branch occurs to different page,

3-97

One-Chip Microprocessor

R6501Q

APPENDIX B
KEY REGISTER SUMMARY
7

•

I':-__--"___-,JI

§
I7

(

15

ACCUMULATOR

I NI

~.I INDEX REGISTER Y
°1

7

v

I

1·1

DI' I ZI Cl

INDEX REGISTER X

CARRY (e)

0

1...--...:PC.=H-----l'7.--_.!:.PC1.""-_ _ _;;lo' PROGRAM COUNTER
'=-__....:::SP_ _ _-,JI STACK POINTER
7

' - - - - - - ZERO ,ZI

•

~IN:.JI-,v.l.I--,-1::.
• ...II..:D"I,,''-I.:1z:..L1c:..J1 PROCESSOR STATUS REO

CD

1: Carry Set
o ;:::: Carry Clear

PC

v-----

'>

~

1SY

15Y

STROH

j.- TpLSU ~.

TpBLW

3·103

~I

~TpBLH

R6501Q

One-Chip Microprocessor

E.4 MICROPROCESSOR TIMING (00-07,
AQ-A 12, A15, SYNC, R/W)
SYMBOL

PARAMETER

1 MHz

2 MHz

MIN MAX

MIN MAX

225

-

140

150

-

75

35

30

-

00-07 Write Output
Delay

-

TSYN

SYNC Setup

THA

AO-A12, A15 Hold Time

THRW
TACC

-

TRws

RIW Setup Time

TAos

AO-A12, A15 Setup
Time

Tosu

00-07 Data Setup Time

50

THR

00-07 Read Hold Time

10

THw

00-07 Write Hold Time

T Mos

-

10

-

30

-

175

-

130

-

225

-

175

30

-

30

-

RIW Hold Time

30

-

30

External Memory Access

-

TACC

-

30

-:-

30

TlmeTACC

::::

TACC

Tcyc-T F -

TADS-Tosu

TSYH

SYNC Hold Time

-

E.4.1 Microprocessor Timing Diagram

WRITE

READ

...-THAW

R/W

AO-A12,
015

TOSU - - - .

TMOS

DATA~

DATA 7

-cr---THR
. . - TSYH

SYNC

3-104

R6500/1
R6500 Microcomputer System

'1'

Rockwell

R6500/1
ONE-CHIP MICROCOMPUTER

SECTION 1
INTRODUCTION

The Rockwell R6500/1 microcomputer is a complete 8-bit
computer fabricated on a single chip using an N-channel silicon gate MOS process. The R6500/1 complements an
established and growing line of R6S00 products and has a
wide range of microcomputer applications.

FEATURES
•
•
•
•
•
•
•
•

The R6500/1 consists of an R6502 Central Processing Unit
(CPU), 2048 bytes of Read Only Memory (ROM), 64 bytes of
Random Access Memory (RAM) and Interlace circuitry for peripheral devices.

•
•
•

The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction simplicity, results in system cost-effectiveness and a wide range of
computational power. These features make the R6500/1 a
leading candidate for microcomputer applications.

•
•
•
•
•
•

To facilitate system and program development for the
R6500/1, Rockwell has developed an R6500/1 E Emulator
part. A description of the R6500/1 E is contained in Appendix D.

•
•
•
This product description is for the reader familiar with the
R6502 CPU hardware and programming capabilities. A
detailed description of the R6502 CPU hardware is included
in the R6500 Microcomputer System Hardware Manual
(Document Number 29650N31). A description of the instruction capabilities of the R6502 CPU is contained in the
R6500 Microcomputer System Programming Manual (Document
Order No. 202).

o

•

Document No. 29650N48
3-105

Single-chip microcomputer
R6502 software compatible
Eight-bit parallel processing
Decimal or binary arithmetic
Vanable length stack
True indexing capability
Thirteen addressing modes
1 or 2 MHz clock operation, with the following options:
- External single clock input
- RC time base input
- Crystal time base input
Single + 5V power supply
500 mw operating power
Separate power pin for RAM with standby power only 10% of
operating power
2K x 8 ROM on chip
64 x 8 RAM on chip
40-pin dual in-line package
64-pin Emulator part available, with 40 signals identical to
production part
Pipeline architecture
32 bidirectional TTL compatible I/O lines
- 1 positive edge sensitive I/O line
- 1 negative edge sensitive I/O line
1 bidirectional TTL compatible counter I/O line
16-bit timer/counter
Four timer/counter modes
- Internal timer
- Pulse generator
- Event counter
- Pulse width measurement
Three maskable interrupts
- 1 counter overllow
- 2 I/O edge detect
NMI and Reset interrupts

Product Description Order No. 212
Rev. 1, October 1984

R6500/1

One-Chip Microcomputer

SECTION 2
INTERFACE REQUIREMENTS
configuration and Table 2-1 describes the function of each
pin of the R6500/1.

.This section describes the interface requirements for the
R6500/1 single chip microcomputer. Figure 2-1 is the Interface Diagram for the R6500/1. Figure 2-2 shows the pin out
XTLI

VRR
PD7
PD6
PD5
PD4
PD3
PD2
PDl

XTLO
8::> PAO·PA7

8:> P80·P87

VCC

PD~

XTLI
XTLQ
VSS
PC7
PC6
PC5
PC4
PC3
PC2
PCl
PCO

VSS

8>

VRR

PCO.PC7

8:::> POO·P07
14-+CNTR

Figure 2-1. R6500/1 Interlace Diagram

10
11
12
13
14
15
16
17
18
19
20

NMI
RES
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
VCC
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
CNTR

Figure 2-2. R6500/1 Pin Out Designation

Table 2-1. R6500/1 Pin Description
Signal Name

VCC

Pin No.

30

VRR

Separate power pin for RAM. In the event that VCC power is lost, this power retains
RAM data.
12

XTLI

10

Crystal, clock or RC network input for internal clock oscillator.

XTLO

1

Crystal or RC network output from internal clock oscillator.

-

39

!

-

NMI

!

PAO-PA7
PBO-PB7
PCO-PC7
PDO-PD7
CNTR

i
I

Main power supply + 5V

VSS

RES

,

Description

Signal and power ground (OV)

The Reset input is used to Initialize the R6500/1. The signal must not transition from low
to high for at least eight cycles after VCC reaches operating range and the internal oscillator has stabilized (see section 5).

+ 10V input enables the test mode.
40

A negative going edge on the Non-Maskable Interrupt signal requests that a nonmaskable interrupt be generated within the CPU.

38-31
29·22
20-13
9-2

Four 8-bit ports used for either input/output. Each line consists of an active transistor to
VSS and an optional passive pull-up to VCC. The two lower bits of the PA port
(PAO-PA1) also serve as edge detect inputs with maskable interrupts.

21

This line is used as a Counter input/output line. CNTR is an input in the Event Counter
and Pulse Width Measurement modes and is an output in the Interval Timer and Pulse
Generator modes. It consists of an active transistor to VSS and an optional passive
pull-up to VCC.

3-106

R6500/1

One-Chip Microcomputer

SECTION 3
SYSTEM ARCHITECTURE
This section provides a functional description of the R6500/1.
A block diagram of the R6500/1 is presented in Figure 3·1.

either user instructions or the interrupt lines NMI and IRQ.
The Stack Pointer must be initialized by the user program.

3.1 INDEX REGISTERS

The stack allows simple implementation of multiple level
interrupts, subroutine nesting and simplification of many
types of data manipulation. The JSR, BRK, RTI and RTS
instructions use the stack and Stack Pointer.

There are two S·bit index registers, X and Y. Each index
register can be used as a base to modify the address data
program counter and thus obtain a new address - the sum
of the program counter contents and the and the index reg·
Ister contents.

The stack can be envisioned as a deck of cards which may
only be accessed from the top. The address of a memory
location is stored (or "pushed") onto the stack. Each time
data are to be pushed onto the stack, the Stack Pointer is
placed on the Address Bus, data are written into the memo
ory location addressed by the Stack Pointer, and the Stack
Pointer is decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented
by 1. The Stack Pointer is then placed on the Address Bus,
and data are read from the memory location addressed by
the Pointer.

When executing an instruction which specifies indirect
addressing, the CPU fetches the op code and the address,
and modifies the address from memory by adding the index
register to it prior to loading or storing the value of memory.
Indexing greatly simplifies many types of programs, espe·
cially those using data tables.

3.2 STACK POINTER
3.3 ARITHMETIC AND LOGIC UNIT (ALU)
The Stack Pointer is an S·bit register. It is automatically
Incremented and decremented under control of the microprocessor to perform stack manipulation in response to

All arithmetic and logic operations take place in the ALU,
including incrementing and decrementing internal registers

Figure 3·1. R6500/1 Block Diagram

3·107

3

One-Chip Microcomputer

R6500/1
(except the Program Counter). The AlU cannot store data
for more than one cycle. If data are placed on the inputs to
the AlU at the beginning of a cycle, the result is always
gated into one of the storage registers or to external memory during the next cycle.

3.9 CLOCK OSCILLATOR
The Clock Oscillator provides the basic timing signals used
by the R6500/1 CPU. The reference frequency is provided
by an external source, and can be from a crystal, clock or
RC network input. The RC network mode is a mask option.
The external frequency can vary from 200 kHz to 4 MHz.
The internal Phase 2 (02) frequency is one-half the external
reference frequency. Figure 3-2 shows typical connections.

Each bit of the AlU has two inputs. These inputs can be
tied to various internal buses or to a logic zero; the AlU
then generates the function (AND, OR, SUM, and so on)
using the data on the two inputs.

3.4 ACCUMULATOR
The accumulator is a general purpose 8-bit register that
stores the results of most arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used in these operations.

3.5 PROGRAM COUNTER

a.

The 12-bit Program Counter provides the addresses that
are used to step the processor through sequential instructions in a program. Each time the processor fetches an
instruction from program memory, the lower (least significant) byte of the Program Counter (PCl) is placed on the
low-order bits of the Address Bus and the higher (most significant) byte of the Program Counter (PCH) is placed on
the high-order 4 bits of the Address Bus. The Counter is
incremented each time an instruction or data is fetched
from program memory.

Crysta I Input
VCC

2-4MHz

3.6 INSTRUCTION REGISTER AND
INSTRUCTION DECODE
b.
Instructions are fetched from ROM or RAM and gated onto the
Internal Data Bus. These instructions are latched into the Instruction Register then decoded along with timing and interrupt signals
to generate control signals for the various registers.

Clock Input

R=4.7K!1
(NOMINAL)
(2MHz EXCITATION
FREQUENCY)

3.7 TIMING CONTROLS
The Timing Control logic keeps track of the specific instruction cycle being executed. This logic is set to TO each time
an instruction fetch is executed and is advanced at the
beginning of each Phase One clock pulse for as many
cycles as are required to complete the instruction. Each
data transfer which takes place between the registers is
caused by decoding the contents of both the instruction register and timing control unit.

c.
NOTE

RC Network Input (Mask Option)

(1)
(2)

C IS PROVIDED INTERNALLY BY THE R650011.
THE RC OPTION IS AVAILABLE ONLY ON THE
1 MHz R6500/1.

Figure 3-2. Clock Oscillator Input Options

3.8 INTERRUPT. LOGIC

3.10 PROCESSOR STATUS REGISTER

Interrupt logic controls the sequencing of three interrupts;
RES, NMI and IRQ. IRQ is generated by anyone of three
conditions: Counter Overflow, PAO Positive Edge Detected,
and PAl Negative Edge Detected.

The 8-bit Processor Status Register, shown in Figure 3-3,
contains seven status flags. Some of these flags are controlled by the user program; others may be controlled both
by the user's program and the CPU. The R6500 instruction

3-108

R6500/1

One-Chip Microcomputer
not all zero. The R6500 instruction set contains no instruction to specifically set or clear the Zero Bit. The Zero Bit is,
however, affected by the following instructions: ADC, AND,
ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC,
INX, INY, LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL,
ROR, RTI, SBC, TAX, TAY, TXA, TSX, and TVA.

set contains a number of conditional branch instructions
which are designed to allow testing of these flags. Each of
the eight processor status flags is described in the following
sections.

3.10.1 CARRY BIT (C)

3.10.3 INTERRUPT DISABLE BIT (I)

The Carry Bit (C) can be considered as the ninth bit of an
arithmetic operation. It is set to logic 1 if a carry from the
eighth bit has occurred or cleared to logic 0 if no carry
occurred as the result of arithmetic operations.

The Interrupt Disable Bit (I) is used to control the servicing
of an interrupt request (IRQ). If the I Bit is reset to logic 0,
the IRQ signal will be serviced. If the bit is set to logic 1,
the IRQ signal will be ignored. The CPU will set the Interrupt Disable Bit to logic 1 if a RESET (RES) or NonMaskable Interrupt (NMI) signal is detected.

The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Clear Carry (CLC)
instruction, respectively. Other operations which affect the
Carry Bit are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL,
ROR, RTI, and SBC.

The I bit is cleared by the Clear Interrupt (CLI) instruction,
the Pull Processor Status from Stack (PLP) instruction, or
as the result of executing a Return from Interrupt (RTI)
instruction (providing the Interrupt Disable Bit was cleared
prior to the interrupt). The Interrupt Disable Bit may be set
or cleared under program control using a Set Interrupt Disable (SEI) or a Clear Interrupt Disable (CLI) instruction,
respectively.

3.10.2 ZERO BIT (Z)
The Zero Bit (Z) IS set to logic 1 by the CPU during any
data movement or calculation which sets all 8 bits of the
result to zero. This bit is cleared to logic 0 when the resultant 8 bits of a data movement or calculation operation are
7

6

5

4

3

o

2

CARRY (C) (1)

1

o

=

Carry Set

=

Carry Clear

L..._ _ _ _ ZERO (Z) (1)

1

o

=
=

Zero Result
Non-Zero Result

L - - - - - - - - I N T E R R U P T DISABLE (I) (2)

1

o

=

=

I RO Interrupt Disabled
I RQ Interrupt Enabled

L-_ _ _ _ _ _ _ _ _ DECIMAL MODE (D) (1)

1 = Decimal Mode

o

=

Binary Mode

L-_ _ _ _ _ _ _ _ _ _ _ BREAK COMMAND (B) (1)

1

o

=

Break Command

=

Not Break Command

L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OVERFLOW (0) (1)

,

=

f)

=

Overflow Set
Overflow Clear

L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ NEGATIVE (N) (1)

NOTES
(1) Not initialized by RES

o =

(2) Set to Logic 1 by RES

Figure 3-3. Processor Status Register

3-109

Negative Value
Positive Value

9

One-Chip Microcomputer

R6500/1

arithmetic operation is negative; if the sign bit is cleared,
the result of the data movement or arithmetic operation s
positive. There are no instructions that set or clear the Negative Bit since the Negative Bit represents only the status of
a result. The instructions that effect the state of the Negative Bit are: ADC, AND, ASL, BIT, CMP, CPX, CPY, DEC,
DEX, DEY, EOR, INC, INX, INY, LOA, LOX, LOY, LSR,
ORA, PLA, PLP, ROL, ROR, RTI, SBC, TAX, TAY, TSX,
TXA, and TVA.

3.10.4 DECIMAL MODE BIT (D)
The Decimal Mode Bit (D), is used to control the arithmetic
mode of the CPU. When this bit is set to logic 1, the adder
operates as a decimal adder. When this bit is cleared to
logic 0, the adder operates as a straight binary adder. The
adder mode is controlled only by the programmer. The Set
Decimal Mode (SED) instruction will set the 0 bit; the Clear
Decimal Mode (CLD) instruction will clear it. The PLP and
RTI instructions also effect the Decimal Mode Bit.

3.11 2K X 8 ROM
The R6500/1 2048 byte x 8-bit Read Only Memory (ROM)
usually contains the user's program instructions and other
fixed constants. These program instructions and constants
are mask-programmed into the ROM during fabrication of
the R6500/1 device. The R6500/1 ROM is memory mapped
from 800 to FFF.

The Decimal Mode Bit will either set or clear in an
unpredictable manner upon power application to
R6500/1. This bit must be initialized to the desired
state by the user program or erroneous results may
occur.

3.1264

3.10.5 BREAK BIT (B)

X

8 RAM

The 64 by1e x 8-bit Random Access Memory (RAM) contains the user program stack and is used for scratch pad
memory during system operation. This RAM is completely
static in operation and requires no clock or dynamic refresh.
The data contained in RAM is read out non destructively
with the same polarity as the input data. A standby power
pin, VRR allows RAM memory to be maintained on 10% of
the operating power. In the event that VCC power is lost
and execution stops, this standby power retains RAM data
until execution resumes.

The Break Bit (B) is used to determine the condition which
caused the IRQ service routine to be entered. If the IRQ
service routine was entered because the CPU executed a
BRK command, the Break Bit will be set to logic 1. If the
IRQ routine was entered as the result of an IRQ signal
being generated, the B bit will be cleared to logic O. There
are no instructions which can set or clear this bit.

3.10.6 OVERFLOW BIT (V)
The Overflow Bit (V) is used to indicate that the result of a
signed, binary addition, or subtraction, operation is a value
that cannot be contained in seven bits (-128 "" n ""
127). This indicator only has meaning when signed arithmetic (sign and seven magnitude bits) is performed. When the
'ADC or SSC instruction is performed, the Overflow Bit is
set to logic 1 if the polarity of the sign bit (bit 7) is
changed because the result exceeds +127 or -128; otherwise the bit is cleared to logic O. The V bit may also be
cleared by the programmer using a Clear Overflow (CLV)
instruction.

In order to take advantage of zero page addressing capabilities, the R6500/1 RAM is assigned page zero memory
address 0 to 03F.

3.13 CONTROL REGISTER
The Control Register (CR), shown in Figure 3-4, is located
at address 08F. The CR contains five control signals and
three status signals.
The control signals are summarized in Table 3-1. The control signals are set to logic 1 by writing logic 1 into the
respective bit positions and cleared to logic 0 either by writing logic 0 into the respective bit position or by the occurrence-of a RES signal.

The Overflow Bit may also be used with the BIT instruction.
The BIT instruction which may be used to sample interface
devices, allows the overflow flag to reflect the condition of
bit 6 in the sampled field. Duriing a BIT instruction the
Overflow Bit is set equal to the content of the bit 6 on the
data tested with BIT instruction. When used in this mode,
the overflow has nothing to do with signed arithmetic, but is
just another sense bit for the microprocessor. Instructions
which affect the V flag are ADC, BIT, CLV, PLP, RTI and
SBC.

Table 3-1. CR Control Signals
Control Signal Name

Bit
Number

Counter Mode Control 0 (CMCO)

3.10.7 NEGATIVE BIT (N)
The Negative Bit (N) is used to indicate that the sign bit
(bit 7), in the resulting value of a data movement or data
arithmetic operation, is set to logic 1. If the sign bit is set
to logic 1, the resulting value of the data movement or

1

PA1 Interrupt Enabled (A1IE)

2

PAO Interrupt Enabled (AOIE)

3

Counter Interrupt Enabled (CIE)

4

The three status signals are summarized in Table 3-2.

3-110

0

Counter Mode Control 1 (CMC1)

R6500/1

One-Chip Microcomputer
7

6

S

4

3

o

2

ICR7)1
CR6, I A1ED
CRS, I CR41
CR3ICR2ICR11ICRO,1
CTRO AOED
CIE
AOIE
AllE CMCl CMCO

I

I

COUNTER MODE CONTROL (CMCl & CMCO)

o

0
1
1 0
1 1

Interval Timer
Pulse Generator
Event Counter
Pulse Width Measurement

o

PAl INTERRUPT ENABLE (AlIE)
1 = Enable PA 1 Interrupt
0= Disable PAl Interrupt
PAO INTERRUPT ENABLE (AOIE)
1 = Enable PAO Interrupt
0= Disable PAO Interrupt
COUNTER INTERRUPT ENABLE (CIE)
1 = Enable Counter Intenupt
Disable Counter Interrupt

o=

PAl NEGATIVE EDGE DETECTED (A1ED)
1

=

o =

PAl Negative Edge Detected
PAl Negative Edge Not Detected

PAO POSITIVE EDGE DETECTED (AOED)
1

=

o =

PAD Positive Edge Detected
PAO Positive Edge Not, Detected

COUNTER OVERFLOW (CTRO)
1

=

Counter Overflow Occurred

o

=

No Counter Overflow

Figure 3-4. Control Register (CR)
Table 3-3. Counter Mode Control Selection

Table 3-2. CR Status Signals
Bit
Number

CMCl
(Bit 1)

CMCO
(Bit 0)

PAl Negative Edge Detected (A1ED)

5

0

0

Interval Timer

PAD Positive Edge Detected (ADED)

6

0

1

Pulse Generator

Counter Overflow (CTRO)

7

1

0

Event Counter

1

1

Pulse Width Measurement

Status Signsl Name

The status signals are read-only information. The status bits
are set to logic 1 by hardware monitoring logic and cleared
to logic 0 by the occurrence of RES signal or by specific
address commands. Each of these signals is described in
the following sections.

Mode

The Counter is set to the Interval Timer Mode (00) when a
RES signal is generated or if the user program stores logic
o into Bits 0 and 1 of the Control Register'. A complete
description of each of the Counter modes is given in Section 3.14,1,
'

3.13.1 COUNTER MODE CONTROL 0 AND 1
Counter Mode Control signals CMCO and CMC1 (bits 0 and
1) control the Counter operating modes, The modes of
operation and the corresponding configuration of CMCO and
CMC1 are summarized in Table 3-3.

3.13.2 PA1 INTERRUPT ENABLE BIT (A1IE)'
If the PA1 Interrupt Enable Bit (CR2) is set to logic 1, an
IRQ interrupt request Signal will be generated when the
PA1 Negative Edge Detected Bit (CR5) is set.

These modes are controlled by writing the appropriate bit
values into the Counter Mode Control bits.

3-'"

One-Chip Microcomputer

R650Q/1

the values contained in the Upper Latch (UL) in address 084 and
in the Lower Latch (LL) in address 085, respectively. Therefore, it
is important to load the Lower Latch value prior to executing the
Write to Upper Latch and Transfer Latch to Counter (address
088) in order to prevent an unpredicted reoccurrence of Counter
Overflow and, if enabled, an IRQ interrupt request.

3.13.3 PAO INTERRUPT ENABLE BIT (AOIE)
If the PAO Interrupt Enable Bit (CR3) is set to logic 1, the
IRQ interrupt request signal will be .generated when the
PAO Positive Edge Detected Bit (CRS) is set.

3.13.4 COUNTER INTERRUPT ENABLE BIT (CIE)

3.14 COUNTER/LATCH

If the Counter Interrupt Enable Bit (CR4) is set to logic 1,
the IRQ interrupt request signal will be generated when
Counter Overflow (CR7) is set.

The Counter/Latch consists of a 16-bit Counter and a 16-bit
Latch. The Counter resides in two 8-bit registers: address
086 contains the Upper Count value (bits 8-15 of the Counter) and address 087 contains the Lower Count value (bits
0-7 of the Counter). The Counter contains the count of
either f/l2 clock periods or external events depending on
which counter mode is selected in the Control Register
(Section 3.13.1).

3.13.5 PA1 NEGATIVE EDGE DETECTED BIT
(A1ED)
The PA1 Negative Edge Detected Bit (CR5) is set to logic
1 whenever a negative (falling) edge is detected on PA1.
This bit is cleared to logic 0 by RES or by writing to
address 08A.

The Latch contains the Counter initialization value, The
Latch resides in two 8-bit registers: address 084 contains
the Upper Latch value (bits 8-15 of the Latch) and address
085 contains the Lower Latch value (bits 0-7 of the Latch).
The 16-bit Latch can hold values from 0 to 65535.

The edge detecting circuitry is active when PA1 is used
either as an input or as an output. When PA1 is used as
an output, A1 ED will be set when the negative edge is
detected during a logical 1 to 0 transition.

The Latch registers can be loaded at any time by executing
a write to the Upper Latch Address (084) and the Lower
Latch Address (085). In each case, the contents of the
Accumulator are copied into the applicable Latch register.
The Upper Latch and Lower Latch can be loaded independently; it is not required to load both registers at the same
time or sequentially. The Upper Latch can also be loaded
by writing to address 088.

When PA1 is used as an input and the negative edge
detecting circuitry is used, A1ED should be cleared by the
user program upon initialization and when the PA1 Negative
Edge Detected IRQ processing is completed.

3.13.6 PAO POSTIIVE EDGE DETECTED BIT (AOED)
The PAO Positive Edge Detected Bit (CR6) is set to logic 1
whenever a positive (rising) edge is detected on PAO. The
bit is cleared to logic 0 by RES or by writing to address
089.

The Counter can be initialized at any time by writing to
address 088. The contents of the Accumulator will be copied into the Upper Latch before the value in the Upper
Latch is transferred to the Upper Counter.

The edge detecting circuitry is active when PAO is used
either as an input or as an output. When PAO is used as
an output, AOED will be set when the positive edge is
detected during a logical Oto 1 transition.

The Counter will also be initialized to the Latch value whenever the Counter overflows. When the Counter decrements
from 0000, the next Counter value will be the Latch value,
not FFFF.

When PAO is used as an input and the positive edge
detecting circuitry is used, AOED should be cleared by the
user program upon initialization and upon completion of
PAO Positive Edge Detected IRQ processing.

Whenever the Counter overflows, the Counter Overflow Bit
(CR7) is set to logic 1. ThiS bit is cleared whenever the
lower eight bits of the counter are read from address 087
or by writing to address 088.

3.13.7 COUNTER OVERFLOW BIT (CTRO)

3.14.1 COUNTER MODES

The. Counter Oyerflow Bit (CR7) is set to logic 1 whenever
a counter overflow occurs in any of the four counter operating modes. Overflow occurs when the counter is decremented one count from 0000. This bit is cleared to logic 0
by REs or by reading froniaddress 087 or writing to
address 088.

The Counter operates in any of four modes. These modes
are selected by the Counter Mode Control bits in the Control Register.
Mode

This bit should be cleared by the user program upon
initialization' and upon completion of Counter Overflow IRQ
interrupt processing.

Interval Timer

When a Counter Overflow occurs. the Upper Count (UC) in address 086 and the Lower Count (LC) in address 087 are reset to

Event Counter

Pulse Generator

Pulse Width Measurement

3-112

CMC1

CMCO

o
o

o
o

One-Chip Microcomputer

R6500/1

Counter Timer capacity IS therefore 1/-,s to 65.535ms at the 1
MHz 02 clock rate or 0.5/-,s to 32.?68ms at the 2 MHz ¢2 clock
rate. Time intervals greater than the maximum Counter value can
be eaSily measured by counting IRQ interrupt requests In the
counter IRQ Interrupt routine.

The Interval Timer, Pulse Generator, and Pulse Width
Measurement Modes are ~2 clock counter modes. The
Event Counter Mode counts the occurrences of an external
event on the CNTR line.

Interval Timer (Mode 0)
In the Interval Timer mode the Counter is initialized to the
Latch value by either of two conditions:

When the Counter decrements from 0000, the Counter
Overflow (CR?) is set to logic 1 at the next 02 clock pulse.
If the Counter Interrupt enable bit (CR4) is also set, an IRQ
interrupt request will be generated. The Counter Overflow
bit in the Control Register can be examined in the IRQ
interrupt routine to determine that the IRQ was generated
by the Counter Overflow.

1. When the Counter is decremented from 0000, the next
Counter value IS the Latch value (not FFFF).
2

When a write operation is performed to the Load
Upper Latch and Transfer Latch to counter address
(088), the Counter is loaded with the Latch value. Note
that the contents of the Accumulator are loaded into
the Upper Latch before the Latch value is transferred
to the Counter.

While the timer is operating in the Interval Timer Mode, the
Counter OuVEvent line is held in the high (output disabled)
state.

The Counter value IS decremented by one count at the ~2 clock
rate. The 16-blt Counter can hold from 1 to 65535 counts The

A timing diagram of the Interval Timer Mode is shown in
Figure 3-5.

(])2

I

COUNTER OVERFLOW

,

COUNTER

3

o

2

I

I

(UL, LL)

(UL, LL)-1

COUNTER INTERRUPT ENABLED

\

SET ANY TIME BEFORE
COUNTER OVERFLOW

COUNTER OVERFLOW

IRQ

CNTR _ \ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
HELD HIGH IN MODE 00

Figure 3-5. Interval Timer (Mode 0) Timing Diagram

Pulse Generator Mode (Mode 1)
output on the CNTR line in thiS mode. The CNTR output IS
initialized high by a RES since the Interval Timer mode is
established by RES.

In the Pulse Generator mode, the Counter Out/Event In line
(CNTR) operates as a Counter Out. The CNTR line toggles
from low to high or from high to low whenever a Counter
Overflow occurs, or a write is performed to address 088.

A one-shot waveform can be easily generated by changing
from Mode 1 Pulse Generator to Mode 0 (Interval Timer)
aiter only one occurrence of the output toggle condition.

Either a symmetric or asymmetric output waveform can be

3-113

One-Chip Microcomputer

R6500/1

count at the ~2 clock rate as long as the CNTR line is held
in the low state. The Counter is stopped when CNTR is in
the high state.

Event Counter Mode (Mode 2)
In this mode the CNTR line is used as an Event Counter. The
Counter will decrement with each rising edge detected on this
line. The maximum rate at which this edge can be detected is
one-half the (il2 clock rate.

If the CNTR pin is left disconnected, this mode may be
selected to stop the Counter since the internal pull-up
device will cause the CNTR input to be in the high (>2.0V)
state.

The Counter can count up to 65,535 occurrences before
overflowing. As in the other modes, the Counter Overflow
bit (CR7) is set to logic 1 if the overflow occurs.

A timing diagram for the Pulse Width Measurement Mode is
shown in Figure 3-7.

Figure 3-6 is a timing diagram of the Event Counter Mode.

3.15INPUT/OUTPUT PORTS

Pulse Width Measurement Mode (Mode 3)

The R6500/1 provides four a-bit Input/Output (1/0) ports
(PA, PB, PC, PO). These 32 1/0 lines are completely
bidirectional. All lines may be used either for input or output
in any combination; that is, there are no line grouping or
port association restrictions.

This mode allows the accurate measurement of a low pulse
duration on the CNTR line. In this mode, CNTR is used in
the Event In capacity. The Counter decrements by one

-IT,f ,.u ~ 1!-

CNTR

~~

I

I

1i2

2.0V

2.0V

--f

O.BV

f-k~~T""~

COUNT

O.BV

\

ff

N·2

N-'

READ

N-'

N·2

Figure 3-6. Event Counter Mode (Mode 2)

:i
CNTR

~2.0V

COUNT
N

READ

r

j

T".U

f.---

_

I I I I I I
N-'

N

N·2

N-'

N·2

2.0V

I

N-3 1

N-3

Figure 3-7. Pulse Width Measurement (Mode 3)

3-114

TPDSU

I I

N41

N4

N4

N4

One-Chip Microcomputer

R6500/1
The direction of the 32 I/O lines are controlled by four 8-bit port
registers located in page zero. This arrangement provides quick
programming access using simple two-byte zero page address
instructions. There are no direction registers associated with the
I/O ports, which simplifies I/O handling. The I/O addresses are
shown in Table 3-4.

The status of the input lines can be interrogated at any
time by reading the I/O port addresses. Note that this will
return the actual status of the input lines, not the data written into the I/O port registers.

Table 3-4. I/O Port Addresses

Outputs are controlled by writing the desired I/O line output
states into the corresponding I/O port register bit positions.
A logic 1 will force a high (>2.4V) output while a logic 0
will force a low «0.4V) output.

Port

Address

A

080

B

081

C

082

D

083

3.15.2 OUTPUTS

3.15.3 EDGE DETECTION CAPABILITY
Ports PAD and PAl have an edge detection capability. Figure 3-9 shows the edge detection timing.

Figure 3-8 shows the I/O Port Timings.

PAO Positive Edge Detecting Capability
In addition to its normal I/O function, PAD will detect an
asynchronous positive (rising) edge signal and set the PAD
Positive Edge Detected signal (CR6) to logic 1. The maximum rate at which this positive edge can be detected is
one-half the 162 clock rate.

3.15.1 INPUTS
Inputs are enabled by loading logic 1 Into all I/O port register bit
positions that are to correspond to I/O Input lines. A low «0 8V)
Input signal will cause a logiC 0 to be read when a read instruction
IS issued to the port register A high (>2.0V) Input will cause a
logic 1 to be read. An RES signal forces all I/O port registers to
logic 1 thus Initially trealing all I/O lines as inputs.

I! the PAD Interrupt Enable Bit (CR3) is set, an IRQ interrupt request will also be generated. The PAD Positive Edge
Detected signal can be cleared by writing to address 089.

I/O PORT OUTPUT TIMING

L~

I

I

~_ _ _ _~I~_~==~T~CM~OS~==.~~

INTERNAL RiW

______________________________________~___________
po_w___

1_

T

PA, PB, PC, PO OUTPUT

~ 0.7 Vee
2.4V
O.4V
I'---

I/O PORT INPUT TIMING

INTERNAL RiW _ _

\

~

TpOSU--J

2.0V

PA,PB,PC, PO INPUT

O.BV

----------------------------~

Figure 3-8. I/O Port Timing

3-115

--------------------

One-Chip Microcomputer

R6500/1

(j>2

I

'---_--'I

_-------I

1.-1

~~~"" ~ .:~:_:_:_P_D~S~U~ ~ ~:~: ~i. ;t<:~
________
T_PW
______

________________________________________
"SEE NOTE

"NOTE: IRQ WILL STAY LOW UNTIL IT IS SERVICED

Figure 3-9. PAO and PA1 Edge Detection Timing

PA1 Negative Edge Detecting Capability

3.16 MASK OPTIONS

In addition to its normal 1/0 function, PA1 will detect an
asynchronous negative (falling) edge signal and set the PA1
Negative Edge Detected signal (CRS) to logic 1. The maximum rate at which this negative edge can be detected is
one-half the ~2 clock rate.

An option is provided to delete the Internal pull-up resistance from
PA, PB, PC and/or PD ports at mask time. ThiS option is available
for B-bit port groups only, not for individual port lines. This option
may by used to aid interface With CMOS drivers, or in order to
Interface with external pull-up devices.

" the PA 1 Interrupt Enable signal (CR2) is set, an fRO
interrupt request will also be generated. The PA 1 Negative
Edge Detected signal may be cleared by writing to address
OBA.

An option is also provided to delete the internal pull-up
resistance on the CNTR line.

3-116

R6500/1

One-Chip Microcomputer

SECTION 4
IRQ INTERRUPT REQUEST GENERATION
An IRQ interrupt request can be initiated by any or all of
three possible sources. These sources are all capable of
being enabled or disabled by the use of the appropriate
interrupt enabled bits in the Control Register.

Multiple simultaneous interrupts will cause the IRQ interrupt
request to remain active until all interrupting conditions have
been serviced and cleared.

The first source of IRQ is Counter Overflow. The IRQ interrupt
request will be driven low whenever both the Counter Interrupt
Enable (CR4) and the Counter Overflow (CR7) are logic 1.
If the same data, I.e., the same RAM, counter/latch or I/O
addresses, are operated on asynchronously by a normal
processing routine and by an Interrupt service routine, care
must be taken to prevent loss of data due to the interrupt
routine altering the data during update of the data by the
normal processing routine. This situation can be prevented
by disabling the IRQ Interrupt with the SEI instruction before starting the data update in the normal processing and
then enabling the interrupt with the CLI instruction upon
completion of data update.

The second source of IRQ is detection of a positive edge
on PAO. The IRQ inerrupt request will be driven low whenever both the PAO Interrupt Enable (CR3) and the PAO
Positive Edge Detected (CR6) are logic 1.
The third source of IRQ is detection of a negative edge on
PA1. The IRQ interrupt request will be driven low whenever
both the PA1 Interrupt Enable (CR2) and the PA1 Negative
Edge Detected (CR5) are logic 1.

3-117

R6500/1

One-Chip Microcomputer

SECTION 5
POWER ON/OFF CONSIDERATIONS
low at least eight ~2 clock pulses before vee falls out of
operating range. RES must then be held low while vee is
out of operating range and until at least eight 1Il2 clock
cycles after vee is again within operating range and the
internal' 162 oscillator is stabilzed. VRR must remain within
vee operation range during normal R6500/1 operation.
When vee is out of operating range, VRR must remain
within the VRR retention range in order to retain data. Figure 5-2 shows typical waveforms.

5.1 POWER-ON RESET
The occurrence of RES going from low to high will cause
the R6500/1 to set the Interrupt Mask Bit - bit 2 of the
Processor Status Register - and initiate a reset vector fetch
at address FFE and FFF to begin user program execution.
All of the I/O ports (PA, PB, PC, and PO) and eNTR will
be forced to the high (logic 1) state. All bits of the Control
Register will be cleared to logic 0 causing the Interval
Timer counter mode (mode 00) to be selected and causing
all interrupt enabled bits to be reset.

5.4 RAM DATA RETENTION OPERATION
The requirement for R6500/1 RAM data retention and restart operation is application dependent. If R6500/1 RAM
data retention is not required during loss of vee, then VRR
can be connected to the same power source as vee.
With this configuration a complete initialization of R6500/1
program variables in RAM is required upon vee and VRR
power application.

5.2 POWER ON/OFF TIMING
After application of vee power to the R6500/1, RES must
be held low for at least eight 02 clock cycles after vee
reaches operating range and the internal clock oscillator has
stabilized. This stabilization time is dependent upon the
input vee voltage and performance of the crystal, clock, or
Re network input circuit. The clock oscillator output can be
monitored on XTLO (pin 11).

If the R6500/1 RAM is to retain data during loss of vee,
the following is required:
1. Connection of vee and VRR to separate power supplies
or to the same primary power supply with isolation
diodes and battery or other backup power for VRR.

Figure 5-1 illustrates the power turn-on waveforms.

5.3 RAM DATA RETENTION - VRR

2. vee power monitor hardware with power loss and
cold/warm start indications to the R6500/1.

REQUIREMENTS

3 Power loss detection as well as cold and warm start

For the RAM to retain data upon loss of vee, VRR must
be supplied within operating range and RES must be driven

Vee +5 - -

-

initialization in the R6500/1 program.

-~_--------------......fJJ

O~POWERON
XTLO

I-- eLoe~

STABILIZATION TIME--I

t--

s

IS
Figure 5·1. Power Turn·On Timing Detail

3·118

R6500/1

One-Chip Microcomputer
RAM OPERATING MODE

RAM RETENTION MODE

~

VRR

vee

- - - -n - - - -;;,

~

o

®

o

I~------~H~----~~I

--u--®

G)

INITIAL APPLICATION OF VCC AND VRR.

®
®

REAPPLICATION OF

~ ~TRL 0

LOSS OF VCC. RAM ON STANDBY POWER.

o
®

vee.

;;'8 1/>2 CLOCK PULSES AFTER~2 OSCILLATOR STABILIZATION.
;;.8 1/>2 CLOCK PULSES.

Figure 5-2. RAM Retention Mode Timing

The power monitor hardware must sense the loss of VCC
power In sufficient time to allow the R6500/1 to save required CPU register data in RAM. The power loss indication
line can be connected to the NMI interrupt input in order to
cause an immediate R6500/1 interrupt upon power loss
detection.

depending upon cold/warm start condition.

Upon power loss detection, the R6500/1 should save all reqUired
CPU register data in either the stack or dedicated RAM. The stack
may be preferred if dedicated RAM IS not available. If the program
IS to restart at the interrupted address, then all CPU registers
must be saved, i.e., S, P, PC, A, X, and Y. The stack pointer must
be saved in a dedicated RAM address. Note that processor status
P and the program counter, PC, are already saved on the stack by
the NMI interrupt R6500/1 hardware processing. lithe warm start
can be performed at a speCifiC address, then the saving of the
register data at power loss detection may not be reqUired. Figure
5-3 shows top level flowcharts of typical power down and
power-up processing.

The power monitor hardware should also provide an indication of cold start (initial VCC and VRR power application) or
warm start (VCC power re-application while VRR is retained
on backup power) provided as input on a data I/O pin.
A level indication is sufficient. The R6500/1 program can
then initialize all, or partial, program variables upon initialization then jump to any other starting address as required

3-119

R6500/1

One-Chip Microcomputer

ACQUIRE/COMPUTE
AND SAVE DATA
AS REQUIRED

COMMON INITIALIZATION

SAVE A, X, 8< Y IN STACK
SAVE S IN DEDICATED RAM
NO

YES

COLD
START
ADDRESS
INITIALIZE COLD START
UNIQUE VARIABLES

*HANG UP IN SHORT
LOOP UNTIL EXECUTION
TERMINATES

a.

WARM
START
ADDRESS
INITIALIZE WARM START
UNIQUE VARIABLES

Program Recovery at
Address of Interruption

ACQUIRE/COMPUTE 8<
SAVE DATA AS
REQUIRED

COMMON INITIALIZATION

YES

*HANG UP IN SHORT
LOOP UNTIL EXECUTION
TERMINATES

NO

WARM
START
ADDRESS
INITIALIZE WARM START
UNIQUE VARIABLES

b.

Program Recovery at
Specific Restart Address
Figure 5-3. Typical R6500/1 Power Loss Recovery Flowcharts

3-120

R6500/1

One-Chip Microcomputer

SECTION 6
TEST
application program into RAM. It can easily be adapted to
specific requirements by re-assigning I/O as required. The
loader uses positive handshake between the R65OO/1 and
the interfacing host equipment. One I/O line is dedicated to
the test mode selection. The other pins assigned to loader
interface signals may be assigned to normal application I/O
interface signals when the test mode is not selected.

6.1 TEST MODE
The R6500/1 test function is multiplexed on the
pin. The three Input states for this pin are:

RES

input

1. <0.8V

Reset state. All R6500/1 outputs are
forced to the high state.

2. >2.0Vand
<5.5V

Normal run state. The low to high transItion on the RES Pin initiates fetch of the
reset vector from address FFC and FFD
and starts user program execution at the
vectored address.

3. >10.0Vand
<10.5V

I/O is assigned for the RAM Program Loader as follows:

Test state. The only internal action that
takes place is switching of the data
source for instruction memory from internal ROM to I/O port "C". Bit 0 of port
"C" is the data least significant bit (LSB).

PAO

Data Ready (DR) - Positive edge indicates data is ready for sampling by the
R6500/1.

PA1

End of Data (EOD) - Negative edge
indicates that all the data has been
transferred to the R6500/1.

PA2

Data Taken (DT) -

o = Data Not Taken
1 = Data Taken

PA7

The test mode allows instructions and data to be input externally
through I/O port "C". This capability is used at Rockwell to test all
of the R6500/1 logiC, registers and internal data RAM A ROM
dump may be accomplished by using the test feature to load into
the internal RAM a small program to fetch each byte of ROM and
output it to an I/O port. After this program is loaded the CPU is
directed to begin execution out of RAM, e.g., JMP to 00. After the
Jump is executed, the RES line is returned to the normal run state.
The normal run state allows data fetches to occur out of the
Internal ROM and returns port "C" to its normal function.

Normal Mode Select (NMS) -

o = Test Mode
1 = Normal Mode
PB7-PBO

Data input, i.e., instruction or data (PB7
= MSB, PBO = LSB)

The flowchart in Figure 6-1 shows the loader operation. The
handshake waveforms between the R6500/1 and the host
are illustrated in Figure 6-2. The following description corresponds to the handshake events identified in Figure 6-2:
1) Host sees PA2 high, which indicates previous data, if
any, has been taken by the R6500/1. The host then
drops PAO low to indicate new data is not ready. This
signal should be initialized low by the host.

The detail support hardware and software required to use
the R6500/1 test mode is fairly complex and time critical.
For normal application testing, it is recommended that a test
program be loaded into RAM and executed as explained in
Section 6.2.

2) R6500/1 detects PAO low then drops PA2 low to indicate that data has not been taken.
3) Host sees PA2 low then sets up new data.

6.2 PROGRAM LOADING INTO RAM

4) Host sets PAO high to indicate new data is ready.
5) Upon detecting positive edge of PAO, R6500/1 reads
data on PB7-PBO. R65OOl1 then sets PA2 high to indicate that the data has been taken.

A test or application program can easily be loaded into the
R6500/1 RAM and executed without forcing the R6500/1
into the test mode. To do this, a short program loader function must be permanently included in the application program
stored in ROM. Upon test mode selection during R6500/1
initialization, the loader reads instructions or data from an
I/O port and stores them into RAM. At the first completion
of the load, the loader then jumps to the first instruction in
RAM to start program execution.

6 When no more data is available, the host drops
low to indicate end of data (EOD). The R65OO/1
jumps to address $000 to start program execution.
RAM is loaded without EOO detected, the R6500/1
jumps to address $000.

PA1
then
If all
also

An assembly listing of the RAM Program Loader is shown
in Table 6-1.

A program is described which may be used to load test or

3-121

One-Chip Microcomputer

R6500/1

INITIALIZE STACK POINTER

.

$3F+S

CLEAR DECIMAL MODE
INITIALIZE RAM INDEX TO 0

CRS

I = PAl NEG EDGE
DETECTED = YES

PAl NEG EDGE
DETECTED = YES

Figure 6-1. RAM Program Loader Flowchart

3-122

R6500/1

One-Chip Microcomputer
t----DATA STABLE----I

DATA (PB7·'PBD)

DATA READY (DR) (PAD)

~f

DATA TAKEN (DT) (PA2)

ENDOF DATA (EOD) (PA1)

--------------------------1\

Figure 6-2. R6500/1 RAM Program Load Handshake

3-123

\

~

9

One-Chip Microcomputer

R6500/1

Table 6-1. RAM Program Loader Assembly Listing
R6500/1 RAM LOADER ..... PAGE 001
LINE #
0002
0003
0004
0005
0008

LOC
0000
0000
0000
0000
0000

0008
0009
0010
0011
0012
0013
0014

0000
0800
0802
0803
0804
0808
0808

A23F
9A
08
A200
A580
3020

Reset

0016
0017
0018

080A
080C
0800

A580
4A
BO 1C

PAZCK

0020
0021

O8OF
0811

A9 FB
B580

0023
0024
0025

0813
0815
0817

A920
248F
501A

0027
0028
0029
0030
0031
0032
0033
0034

0819
081B
00810
081F
0821
0823
0824
0826

8589
A581
9500
A9 FF
8580
E8
EO 40
DO E2

0038

08l!8

4C 00 00

0038
0039
0040
0041

082B
0820
082F
0831

0043
0044

0833
0835

0046

0837

0048
0049
0050

0837
OFFC
OFFE

CODE

LINE
PORTB $81
PORTA = $80
CLRPAO = $89
CTLREG= $8F
BEGIN =$000

RDYCK

;Port B Aaoress
;Port A Address
;CLR PAO Edge Detect
;Control Register
;RAM First Address

'=$0800
LOX #$3F
TXS
CLD
LOX #$00
LOA PORTA
BMIINIT

;Initlallze Stack Pointer
;Set Binary Add Mode
;Initialize RAM Index
;Test Mode Selected (PA7=0)?
;Yes

LOA PORTA
LSRA
BCS EODCK1

;Data Ready High (PAO = 1)?

LOA #$FB
STAPORTA

;No, Reset Data Taken
;O->PA2

LOA #$20
BITCTLREG
BVC EODCK2

;Data Ready (PAO Pos Edge Detected)?

STACLRPAO
LOA PORTB
STA BEGIN,X
LOA #$FF
STA PORTA
INX
CPX #$40
BNE PAZCK

;Yes, Clear PAO Pos Edge Detected
;Load Data From Port B
;Store in RAM

JMPBEG

JMP BEGIN

;Yes, Go To RAM Program Execution

A920
258F
FO 09
DO F5

EODCK1

LOA #$20
AND CTLREG
BEQ PAZCK
BNEJMPBEG

;End of Data (PA1 Neg Edge Detected)?
;Yes, Go To RAM Program Execution

FODE
DO F1

EODCK2

BEQ RDYCK
BNE JMPBEG

;End of Data (PA1 Neg Edge Detected)?
;Yes, Go To Ram Program Execution

RES

;Is RAM Full?

;First Address of Normal Program

INIT
00 08

;Set Data Taken (1·>PA2)
;Increment RAM Index

'=$FFC
.WOR RESET
.END

Errors = 0000 <0000>
End of Assembly

3-124

;Reset Vector

R6500/1

One-Chip Microcomputer

APPENDIX A -

SYSTEM MEMORY MAP

HEX
IRQ Vector High

FFF

IRQ Vector Low

FFE

RES Vector High

FFD

RES Vector Low

FFC

NMI Vector High

FFB

NMI Vector Low

FFA

ROM

FF9
User Program
800
7FF
R6500/1 E User Program
400

..

..

Unassigned
Control Register

3FF
900
08F
08E

.. >

:>

Unassigned

08B

Clear PA1 Neg Edge Detected (Write Only)

(1)

DBA

Clear PAD Pos Edge Detected (Write Only)

(1)

089

Upper Latch and Transfer Latch to Counter (Write Only)

(2)

088

Lower Count (Read Only)

(2)

Upper Count (Read Only)

..

087

Input/Output

086

Lower Latch (Write Only)

085

Upper Latch (Write Only)

084

PORT D

083

PORTC

082

PORT B

081

PORT A

080

 DO

4

1 D9

4

3

N '

I
06

6

2 DE

7

3

Z C

eM P

zC
z c

c
c

z.

0 E C

DE>

z.

z.
A'" M ~ A

, N C

M + 1 -M

111

J M P

JUMPTONEWLOC

J S R

JUMP SUB

LOA
L D ,

LOY
L S R

NO P

o-C~=:::-.D-·c

2

2

I
11)

~ ~:

49

:::

A9

A2

I

2

2

~ I:

40

4

EE

6

3

3

20

6

3

AD

4

3

AC





SO

4

3 89 4

3
86

6

1 Be

4

3

2

7

3

5E

4

;>

I I

0,

l'

lOA
LOX

Z'

LOY

Z C

2

15



I

I

I
2 I 2

6

N '

I _1
II:

461s124A12!1

NOQPERATION

L ,

CLV

31,

0' Y
'DR

vS

C L C

e

C L V

e

BIT
B M ,

C L ,

e

AND

Z CAS l

BRANCH ON C '" 1 (2)

BRANCH ON V

n

z·
,

I""""

INDIRECT
QP

N V

,

BVe
L

ACCIJM
OP n

90

BRK

e
e

;I

\21

=0

B , T

vS

lEAD PAGE

• OP

OE630652QA21

Bee
Be S

B

ABSOLUTE

OP

MFMOR'r

3-127

PFRC;~ArK

MEMORY BIT 7
MEMORY BIT 6

NO CYCLES

MEMORY PER EFFECTIVE


SBIT
PORT 0
PDO-PD7

SINGLE CHIP
MICROCOMPUTER
EMULATOR

CNTR
B DATA
LINES <;
EMULATOR
CONTROL

NMI

<
4>2

RES

ROY
SYNC

.

I

::> PORT A

VSS

"nm{

BBIT

RiW

Figure 0-1. R6500/1 Emulator Interface Diagram
3-130

...

TO
INTERFACE
DEVICES

R6500/1

One-Chip Microcomputer
Table 0-1. R6500/1 E Emulator Pin Description

Signal
Name

Pin
No.

Description

RIW

62

ReadlWrite allows the CPU to control the direction of data transfers between the R6500/1 E Emulator CPU and
external memory. This line is high when reading data from memory and is low when writing data to memory.

ROY

3

The Ready input delays execution of any cycle dUring which the ROY line IS low ThiS allows the user to halt
or single step the CPU on all cycles except write cycles. A negative transition to the low state during the ~2
clock low pulse will halt the CPU with the address lines containing the current address being fetched. If ROY is
low during a write cycle, it is ignored until the following read operation. This condition will remain through a subsequent 912 clock pulse in which the ROY line is low. This feature allows the CPU to interface with memories
having slow access times, such as EPROMS used with the R6500/1 Emulator part during prototype system
development.

SYNC

6

The Sync signal is provided to identify cycles in which the CPU
during the 162 clock low pulse of an OP CODE fetch and stays
line is pulled low during the f,J2 clock low pulse in which SYNC
and will remain in that state until the ROY line goes high. Using
control ROY to cause single instruction execution.

P2

1

is performing OP CODE fetch. SYNC goes high
high for the remainder of that cycle. If the ROY
went high, the CPU will halt in its current state
this technique, the SYNC signal can be used to

Phase 2 (~2) clock pulse. Data transfer takes place only during ~2 clock pulse high.

AO·A11

25-37

Address Bus lines. The address bus buffers on the R6500/1 E are pushlpull type drivers capable of driving at
least 130 pf and one standard TIL load. The address bus always contains known data. The addressing technique Involves putting an address on the address bus which IS known to be either in program sequence, on the
same page in program memory, or at a known pOint in memory. The 1/0 address commands are also placed on
these lines.

00-07

53-46

Data Bus lines. All transfers of instructions and data between the CPU and memory, 1/0, and other interfacing
circuitry take place on the data bus lines. The buffers driving the data bus lines have full three-state capability,
which IS necessitated by the fact that the lines are bidirectional Each data bus pin IS connected to an input and output
buffer, With the output buffer remaining In the floating condition

0.3 SYSTEM ARCHITECTURE

-8:::::> PAO-PA7

Figure 0-3 is a block diagram of the R6S00/1 E Emulator.
The function of each block is identical to its counterpart in
the R6S00/1 microcomputer. The main differences between
the two products are in the ROM, the clock oscillator, the
input/output ports and write-only monitoring.

_8:::> PBO-PB 7
R6500/1 E
EMULATOR

0.3.1 ROM

_8

:::> PCO-PC7

AO-A11 <:;:12

To facilitate debugging, the R6S00/1 ROM has been removed from the R6S00/1 E Emulator, and has been replaced
by external memory. Also, an additional 1024 bytes of
memory (400-7FF) are addressable.

00·07 < : 8

ROY---~

0.3.2 CLOCK OSCILLATOR

8::::> POO-P07

I+--I~CNTR

SYNC.---f

RiW

The external frequency reference for the R6S00/1 E Emulator
may be either a crystal or a clock. The RC option is not
available for this device.

.---1

Figure 0-3. R6500/1 E Emulator Block Diagram

0.3.3 INPUT/OUTPUT PORTS

0.3.4 WRITE-ONLY MONITORING

The R6S00/1 E has the internal 1/0 and CNTR port pull-up
resistance only. The option to delete the pull-up resistance
is not included in this device.

The R6S00/1 E allows the user to monitor write operations
to the internal RAM and 1/0 by routing those operations
externally as well as internally. Read operations are not
routed externally.

3-131

One-Chip Microcomputer

R6500/1
0.4 R6500/1 E I/O PORT INITIALIZATION

than in the R6500/1. It is still required, however, that the
RES line to the R6500/1 E be held low for at least eight /62
clock cycles after vee reaches operating range and the ~2
clock oscillator has stabilized.

Ports A, B, e and D and the eNTR line in R6500/1 E are
initialized to the logic high state two f/l2 clock cycles earlier

S ¢2 clock eycl.. minimum after r/l2 clock stabilization

I

~~~~~----------------------------~0---

R6500/1E

1/0
PORTS

~~~~~~~~~~~n---------------------------------------~At-----

R6500/1~

~

RES transitIon window

~ Don't car. state
this case, type 2716 and 2708 PROMs). Example 1 shows a
connection to a 2K 2716 PROM. Since the R6500/1 has a
2K ROM capacity, the contents of the PROM could be
masked directly into the production R6500/1 ROM.

0.5 TYPICAL R6500/1 E PROGRAM MEMORY INTERCONNECTIONS
Shown below and on the following page are two typical
connections between the R6500/1 E and program memory (in

Example 1. R6500/1E Connected to One 2716 PROM (2K Bytes)
• SEE R6500/1 DETAILED MEMORY MAP

Connection Diagram

R6500/1E

DO
01
02
03
04
05
06
07

00
01
02
03
04
05
06
07

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0

AO
Al
A2
A3
A4
A5
A6
A7
AS
A9
Al0

All~

I

Memory Map
FFF

2716
PROM

800
7FF

2716

NOT USED

090
oaF

RAM & I/O'

OE
EE

000

3-132

R6500/1

One-Chip Microcomputer
program, however, must be reduced to 2K maximum (between addresses 800 and FFF) before committing to
R6500/1 ROM.

Example 2 shows a connection to 3K of 2708 PROMs. The
extra 1K PROM allows expanded or additional programs be
used during R6500/1 firmware development. The production

Example 2. R6500/1 E Connected to Three PROMs (3K Bytes)

Connection Diagram
00
01
02
03
04
05
06
07

00
01
02
03
04
05
06
07

AO
Al
A2
R6500/1 E A3
A4
A5
A6
A7
A8
A9

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9

Al0
All

00
01
02
03
04
05
06
07

00
01
02
03
04
05
06
07
2708
NO.1

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9

~

l~cs

J}

FFF

2708 NO.3
PROM

coo

r------

SFF

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9

2708
NO.2

cs

2708
NO.3

.---

II

J p

-

CS

1
J

Program Memory

2708 NO.2
PROM

------

800
7FF

2708 NO.1
PROM

} Extended Program
Memory

400
3FF
NOT USEO

RAM & 1/0

.

090
08F
000

'See R6500/1 E Oetailed Memory Map

Truth Table
Address

PROM Select
2708 No.1

Al~

!'..1C

0

0

1

0

1

0

C'=

I

2808 No.3
CE

Selected
Address Range

1

1

0OO-3FF

1

1

400-7FF
800-BFF
COO-FFF

2708 No.2

t::F

1

0

1

0

1

1

1

1

1

0

3-133

One-Chip Microcomputer

R6500/1
0.6 R6500/1 E TIMING

2 MHz

1 MHz
Signal

Max.

Unit

TRws

300

200

ns

TAos

300

200

ns

525

225

ns

Min.

Symbol

RNi setup time from CPU
Address setup time from CPU

Max.

Min.

Memory read access time

TAco

Data stabilization time

Tosu

150

75

ns

Data hold time -

Read

THR

10

10

ns

Data hold time -

Write

THw

30

30

Data delay time from CPU

T MDS

ROY setup time

T AOY

175

350

TSYNC

Address hold time

THA

Rm hold time

THRw

30

Cycle Time

Tcyc

1.0

/>2

ns

30
10.0

ns
ns

30

30

ns
ns

50

100

SYNC delay time from CPU

PHASE 2 (1/>2) TIMING REFERENCE

ns
150

200

10.0

0.5

floS

O,4V

TIMING FOR READING DATA FROM
EXTERNAL MEMORY

RM

-2.0V
____ O.8V

ADDRESS FROM
CPU

DATA FROM
MEMORY

ROY

SYNC

TIMING FOR WRITING DATA TO
EXTERNAL MEMORY

--

-

RiW

ADDRESS FROM
CPU

DATA FROM
CPU
T MDS

3-134

- - T HRW

One-Chip Microcomputer

R6500/1
0.7 R6500/1E DC CHARACTERISTICS
= 5.0V ±5%, Vss = OV; TA = 0° to 70°C, unless

01cc

otherwise specified)
Min

Typl

Max

Input High Voltage
00-07, ROY

V,H

Vss +2.4

-

-

V

Input Low Voltage
00-07, ROY

V,L

-

-

Vss +0.8

V

Input Leakage Current (Three-State 011)
00-07

liN

-

-

±10.0

p.A

Y,N = 0 to 5.0V
Vee = 5.25V

Output High Voltage
00-07, SYNC, AO-A11, RiW,02

VOH

Vss +2.4

-

-

V

ILOAD = - 100 p.A
Vee = 4.75V

Output Low Voltage
00-07, SYNC, AO-A11, RiW, 02

VOL

-

-

Vss +0.6

V

ILOAD = 1.6 rnA
Vee = 4.75V

I/O Port Pull-Up Resistance

RL

3.0

6.0

11.5

Input Capacitance
ROY
00-07

C'N

-

-

-

10
15

Output Capacitance
AO-A11 , RiW, SYNC
02

COUT

-

50

12
80

Power Oissipation (Outputs High)

Po

-

750

1200

Parameter

Symbol

Notes:
1. Typical values measured at TA = 25°C and Vee = 5.0V.
2. Negative sign indicates outward current Ilow, positive indicates inward Ilow.

3-135

Unit

Test Conditions

Kohrn
pF

TA = 25°C
Y'N = OV
1= 1.0 MHz

pF

TA = 25°C
Y,N = OV
1= 1.0 MHz

mW

TA = O°C

R6500/1E
R6500/* Microcomputers

'1'

Rockwell

R6500/1E
MICROPROCESSOR EMULATOR DEVICE

INTRODUCTION

of R6500/1 and R6500/1 common interface signals and
functions.

The R6500/1 EC and R6500/1 EQ devices provide all the features
of the R6500/1 Microcomputer in a ROMless form suitable for
use as an advanced microprocessor complete with 16 bit counter
and 321/0 lines, and an address and data bus for 4K of external
memory.

The device is available in both 64-pln DIP ceramic (R6500/1 EC)
and 64-pin QUIP PlastiC (R6500/1EQ).

To aid in designing R6500/1 microcomputer systems, it may also
be used as an Emulator device. Device architecture is basically
the same as the R6500/1 except that the address, data, and
associated control lines are routed off the chip for connection
to an external memory.

ORDERING INFORMATION

The functions and operation of the devices are identical to the
R6500/1 except for minor differences. The R6500/1 Data Sheet
Order No. 051 (Document No. 2900051) contains a description

'2

Part
Number

Package
Type

R6S00/1EC
R6S00/1EAC
R6S00/1EO
R6S00/1EAO

Ceramic
Ceramic
PlastiC
PlastiC

SYNC
PB7
PB6
PB5

PB4
PB3
PB2
PBl
PBD

PB7
PB6
PB5

PB4
PB3
PB2
PB1
PBD

02

03
04

PA7

PA6
PA5
PA4
PA3
PA2
PAl
PAD
VRR
CNTR
AD
A1

A2
A3
A4
A5
A6
A7

DO
01

02
03

06
07

PA6
PA5
PA4
PA3

P07

PA2

05
06
07
P07

P06
P05
P04
P03
P02
P01
POD
A11
A1D

PA1
PAD
VRR
CNTR
AD
A1
A2
A3
A4

P06
P05
P04
P03
P02
P01
POD
A11
A1D

A5
A6
A7

AS
VCC

A9
AS

VCC
R65DD/1E

70°C
70°C
70°C
70°C

PC7

PA7

05

to
to
to
to

PCD
PCl
PC2
PC3
PC4
PC5
PC6

SYNC

01

O°C
O°C
O°C
O°C

RtW

NMI

DO

MHz
MHz
MHz
MHz

Temperature
Range

XTLO
XTLI

VSS
ROY
RES

Rfii
PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7

NMt

1
2
1
2

'2

XTLO
XTLI

VSS
ROY
RES

Frequency
Option

04

A9

R65DD/1EQ
Pin Configuration

Document No. 29000D51S
3-136

Data Sheet Order No. D51S
Rev. 2, February 1984

R6500/1E

Microprocessor Emulator Device

SIGNAL DESCRIPTIONS

Signal
Name

All R6500/1 interface signals are provided in the device. While
the pin assignments are different from the R6500/1 in order to
accommodate the 64-pin package, the interface electncal
characteristics are identical. The device provides 24 additional
signals to route the address bus (12 lines), the data bus (8 lines),
and control signals (4 lines) off the chip for connection to external
memory.

Pin
No.

<1>2

Phase 2 (<1>2) clock pulse. Data transfer can
take place only dunng <1>2 clock pulse.

AO-A11

25-32
34-37

Address Bus Lines. The address bus buffers on the device are push/pull type
drivers capable of driving at least 130 pf
and one standard TTL load. The address
bus always contains known data. The
addressing technique involves putting an
address on the address bus which is
known to be either in program sequence,
on the same page in program memory, or
at a known pOint in memory. The I/O
addresses are also placed on these lines.

00-07

53-46

Data bus Lines. All transfers of instructions
and data between the CPU and external
memory take place on the data bus lines.
The buffers driVing the data bus lines have
full three-state capability. Each data bus
Pin IS connected to an input and an output
buffer, with the output buffer remaining in
the floating conditIOn.

MEMORY MAP
An additional 1024 bytes of memory (400-7FF) are addressable
in the device.

EXTERNAL FREQUENCY REFERENCE
The external frequency reference may be a crystal or a clock
- the RC option is not available in the device.

1/0 PORT PULLUPS
The device has internal I/O port pullup resistance only.

DEVICE ADDITIONAL SIGNALS
Signal
Name

Pin
No.

RMi

62

ReadlWrite. The ReadlWrite output controls the direction of data transfer between
the CPU and external memory. This line
is high when reading data from memory
and low when writing data to memory.

ROY

3

Ready. The Ready input delays execution
of any cycle during which the ROY line is
low. This allows the user to halt or single
step the CPU on any cycle except a write
cycle. A negative transition to the low state
during the <1>2 clock low pulse will halt the
CPU with the address lines containing the
current address being fetched. If ROY is
low during a write cycle, It is ignored until
the following read operation. This condition
will remain through a subsequent <1>2 clock
pulse In which the ROY line is low.

SYNC

6

Description

Description

110 PORT INITIALIZATION
Ports A, B, C and 0 and the CNTR line in the device are initialized to the logiC high state two <1>2 clock cycles earlier than in
the R6500/1. It is still required, however, that the RES line be
held low for at least eight <1>2 clock cycles after VCC reaches
operating range (Figure 1).

TYPICAL PROGRAM
MEMORY INTERCONNECTIONS

Sync. The Sync signal is provided to identify those cycles in which the CPU is performing an OP CODE fetch. SYNC goes
high during <1>2 clock-low pulse during an
OP CODE fetch and stay high for the
remainder of that cycle. If the ROY line is
pulled low during the <1>2 clock low pulse
In which SYNC went high, the CPU Will halt
in its current state and will remain in that
state until the ROY line goes high. Using
this technique, the SYNC signal can be
used to control ROY to cause single
instruction execution.

Illustrated are two typical connections between the R6500/1 E
and program memory (in this case, type 2716 and 2708 PROMS).
Figure 2 shows a connection to a 2K 2716 PROM. Since the
R6500/1 has a 2K ROM capacity, the contents of the PROM
could be masked directly into the production R6500/1 ROM.

Fig\lre 3 shows a connection to 3K of 2708 PROMS. The extra
1K PROM allows expanded or additional programs be used during R6500/1 firmware development. The production program,
however, must be reduced to 2K maximum (between addresses
800 and FFF) before committing to R6500/1 ROM.

3-137

R6500/1E

Microprocessor Emulator Device

~ RES TRANSITION
~WINDOW

4>2

RES ~Q,.,...._ _ _ _ _ _8...;4>_2_C_L_0_C_K_C_Y_CL_E_S_M_I_N_IM_U_M_'_ _ _ _ _~
R6S0011E
I/O
PORTS

{

~

DON'T CARE STATE

~~~~~-------------------I.~
~~~~~~~~_ _ _ _ _ _ _ _ _ _ _ _ _ _---..~

R6S00/1

~
Figure 1. I/O Port Initialization

CONNECTION DIAGRAM

R6500/1E

DO
Dl
D2
D3
D4
DS
D6
D7

00
01
02
03
04
05
06
07

AO
Al

AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
Al0

A2
A3
A4
AS
A6
A7
A8
A9
A10
A11

H>-J:

MEMORY MAP

FFF
2716
PROM
800
7FF
NOT USED

2716

090
08F
RAM & I/O·

000

OE
,eE

Figure 2.

Device Connected to One 2716 PROM (2K Bytes)

3-138

Microprocessor Emulator Device

R6500/1E

MEMORY MAP

CONNECTION DIAGRAM
DO
01
02
03
04
05
06
07
AO
A1
A2
R6S00l1E A3
A4
AS
A6
A7
A8
A9

A10
A11

00
01
02
03
04
05
08
07

00
01
02
03
04
05
06
07

AO 2708
A1 No.1
A2
A3
A4
AS
A6
A7
A8
A9

AO
A1
A2
A3
A4
AS
A6
A7
A8

~CE

Figure 3.

00
01
02
03
04
05
06
07
AO
A1

2708
No.2

FFF
2708 No.3
PROM
~-----

2708
No.3

A2

~::

1-----

PROGRAM
MEMORY

800
7FF} EXTENDED
MEMORY
400
PROGRAM

2708 NO.1
PROM

A3
A4
AS
A6
A7
A8
A9

coo
BFF

2708 NO.2
PROM

3FF
NOT USED
RAM & 1/0

090
• 08F

000
frDCE

'SEE DETAILED
MEMORY MAP

Device Connected to Three PROMS (3K Bytes)

TRUTH TABLE
Address

PROM Select

A11

A10

2708 No.3
CE

0
0
1
1

0
1
0
1

1
1
1
0

2708 No.2
CE

2808 No.1
CE

Selected
Address Range

1
1
0
1

1
0
1

OQO-3FF
400-7FF
800-BFF
COO-FFF

3-139

1

Microprocessor Emulator Device

R6500/1E
DEVICE TIMING
1 MHz
Signal

Symbol

Min.

2 MHz
Min.

Max.

Max.

Unit

Rm setup time from CPU

TRWS

300

200

ns

Address setup time from CPU

TAOS

300

200

ns

Memory read access time

TACC

525

225

Data stabilization time

TOSU

Data hold time -

Read

THR

Data hold time -

Write

THW

150

Data delay time from CPU

TMOS

ROY setup time

TROY

SYNC delay time from CPU

TSYNC

ns

75

ns

10

10

ns

30

30

ns

200
100

150

ns

175

ns

50

ns

350

Address hold time

THA

30

30

Rm hold time

THRW

30

30

Cycle Time

TCYC

1.0

ns
ns

0.5

10.0

10.0

~s

ELECTRICAL CHARACTERISTICS
= 5.0 ± 5%, VSS = 0, TA = 25°C)

(Vcc

Symbol

Characteristic

I
I
I

Input High Threshold Voltage
00-07, ROY,

VIHT

Input Low Threshold Voltage
00-07, ROY,

VILT

Three-State (Off State) Input Current
(V = 04 to 2 4V, VCC = 5.25V)
00-07

ITSI

Output High Voltage
(lLOAO = 100~Adc, VCC = 4.75V)
00-07, SYNC, AO-Al1 , R/W, <1>2

VOH

Output Low Voltage
(lLOAD = 1.6 mAde, VCC = 4.75V)
00-07, SYNC, AO-Al1 , Rm, <1>2

VOL

Power DIssipation
Capacitance
(V,n = 0, TA = 25°C, f
ROY
00-07
AO-A", R/W, SYNC
<1>2

I/O Port Pull-up Resistance

Max

Unit

Min

Typ

VSS + 24

-

-

-

VSS + 0.8

-

-

10

-

-

Vdc

-

-

VSS + 06

Vdc

-

0.75

120

-

Vdc
Vdc
~A

VSS + 2.4

Po

W
pF

C

= 1 MHz)
Cout
C2

-

50

10
15
12
80

RL

3.0

60

11.5

Cm

3·140

-

-

kohm

Microprocessor Emulator Device

R6500/1E
DETAILED MEMORY MAP
HEX
FFF
FFE
FFD
FFC
FFB
FFA
FF9
BOO
7FF
400

IRQ VECT R HIGH
IRQ VECTOR LOW
RES VECTOR HIGH
RES VECTOR LOW
NMI VECTOR HIGH
NMI VECTOR LOW
R6500/1 USER PROGRAM
R6500/1E EXTENDED PROGRAM AREA (1)
I

UNASSIGNED

~

~

..

CONTROL REGISTER

I)

UNASSIGNED

CLEAR PAl NEG EDGE DETECTED
CLEAR PAD POS EDGE DETECTED
UPPER LATCH AND TRANSFER LATCH TO COUNTER
LOWER COUNT
UPPER COUNT
LOWER LATCH
UPPER LATCH
PORT 0
PORT C
PORT B
PORT A

JOBF
OBE
OBB
DBA
(2)
OB9
(2
(3) OBB
(3) OB7
OB6
OB5
OB4
OB3
OB2
OBl
OBO

ROM

NOTES:
( 1) Additional 1024 bytes are decoded for external
memory addressing. This area can be used during
debut, but cannot be used in a masked ROM
R6S0011.
(2) 1/0 command only; i.e., no stored data.
(3) Clears Counter Overflow - Bit 7 in Control Register
(4) CAUTION: The device allows RAM mapping into
040-07F, 100-13F, 140-17F, 200-23F, 240-27F,
300-33F, and 340-37F; as well as 000-03F. The
production R6S0011 , however allows RAM mapping
only at 000-03F.

INPUT/OUTPUT

UNASSIGNED
03F }RAM(4)
000

USER RAM

TIMING DIAGRAMS
PHASE 2 (
"V

33

.680
I
I-(17.27
MM)--I

=)H
~ ~

ti~
64 PIN QUIP

)0

~ ~

L-~==~3=2__~

1 .. 1

~

VCC,VSS

PDO-PD7
~

_ _ lI _ _--, ___

PROM/
ROM
CNTR

OE
CE

40 R6500/1
COMPATIBLE PINS

24 PROM/ROM
PINS

R6500/1EB Interface Diagram

3-144

Backpack Emulator

R6500/1EB and R6500/1EAB

DETAILED MEMORY MAP

PROM

BACKPACK MEMORY SIGNAL
DESCRIPTION

IRQ VECTOR HIGH
IRQ VECTOR LOW
RES VECTOR HIGH
RES VECTOR LOW
NMI VECTOR HIGH
NMI VECTOR LOW
R6500/1 USER PROGRAM

PROM

R6500/1EB EXTENDED PROGRAM AREA (1)

Signal
Name

Pin No.

Description

00-07

98-118,
138·175

Data Bus Lines All instrucllon and data
transfers take place on the data bus lines. The
buffers driving the data bus lines have full threestate capability. Each data bus pin IS connected
to an Input and an output buffer, with the output buffer remaining in the floating condition.

AO-A9

18·88,
Address Bus Lines. The address bus lines are
238, 248 buffered by push/pull type drivers that can drive
one standard TTL load.

A10

198

Address Bus Line 10. ThiS address hne has the
same characteristics and functions as Lines
AO-A9

CE

188

CE IS active when the address IS 400-FFF
ThiS line can drive one TTL load

OE

208

Memory Enable Line ThiS signal provides the
output enable for the memory to place Informalion on the data bus hnes ThiS signal IS driven
by the RiW signal from the CPU and then
Inverted by a standard TTL inverter, to form OE.

Vee

248

Main Power 8upply $5V. ThiS pin is !led directly
to pin 30 (Vcd.

A11

218

Address Bus line II. ThiS pin IS tied to A11. Our·
ing backup power, power IS supplied only to the
RAM memory, and not to the PROMs.

Vss

125

81gnal and Power Ground (zero volts). This pin
is tied directly to pin 12 (Vss).

400

NOT
USED

UNASSIGNED
CONTROL REGISTER

(21

08F
08E
08B
08A
089

(3)

088

(:it

087
086
085
084
083
082
081
080

UNASSIGNED

1/0

HEX
FFF
FFE
FFD
FFC
FFB
FFA
FF9
400
3FF

CLEAR PAl NEG EDGE DETECTED
CLEAR PAO POS EDGE DETECTED
UPPER LATCH AND TRANSFER
LATCH TO COUNTER
LOWER COUNT
UPPER COUNT
LOWER LATCH
UPPER LATCH
PORT D
PORT C
PORT B
PORT A

NOT
USED

UNASSIGNED

RAM

USER RAM

@.

03F
000

NOTES
(1) Additional 1024 bytes are decoded for external memory
addressing by the Backpack Emulator Device. This area can
be used during debug, but cannot be used in a masked
ROM R650011.
(2) 1/0 command only; i.e., no stored data.
(3) Clears Counter Overflow-Bit 7 in Control Register
(4) CAUTION: The device allows RAM mapping into 040-07F,
100-13F, 140-17F, 200-23F, 240-27F, 300-33F, and 340-37F;
as well as 000-03F. The production R650011, however
allows RAM mapping only at 000-03F.

VRR
P07
PD6
PD5
PD4
PD3
PD2
PD1
PDO
XTLl
XTLO

RAM MAPPING
The Backpack Emulator allows RAM mapping into 040-07F,
100-13F, 140-17F, 200-23F, 240-27F, 300-33F and 340-37F, as
well as 000-03F. The production R6500/1, however, allows RAM
mapping only at 000-03F. This means that a write to location
40, for example, will write to location 0 in the Backpack Emulator,
and to invalid RAM in the R6500/1 production part.

NMI
RES
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
Vcc
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
CNTR

Vss
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PCO

110 PORT INITIALIZATION
Ports A, S, C, and D and the CNTR line in the Backpack
Emulator are initialized to the logic hi~tate two 02 clock
cycles earlier than in the R6500/1. The RES line to the device
must, however, still be held low for at least eight 02 clock
cycles after Vce reaches operating range. See timing diagram.

Pin Configuration

3-145

Backpack Emulator

R6500/1 EBand R6500/1 EAB
READ TIMING CHARACTERISTICS
1 MHz
Signal

Symbol

OE setup time from CPU
Address setup time from CPU
Memory read access time
Data stabilization time
Data hold time-Read
Address hold time
OE hold time
Cycle Time

Min.

TOEs

-

TAos

-

TACC
Tosu

THR
THA
T HOE
Tcyc

150
10
30
30
1.0

2 MHz
Max.

Min.

300
300
525

-

-

100
10
30
30
0.5

-

10.0

-

Max.

Unit

150
150
250

-

ns
ns
ns
ns
ns
ns
ns

10.0

fLs

READ TIMING WAVEFORMS
I-_ _ _ _ T CYC -------Io-l
1>2'

ADDRESS FROM
CPU
DATA FROM -+--+--+-......:s~
MEMORY
~--'-_-I'1rTosu

*q,2 IS SHOWN FOR REFERENCE ONLY AND IS NOT AVAILABLE EXTERNAL TO THE DEVICE.

I/O PORT INITIALIZATION TIMING

R6500/1EB
,1/0

PORTS

[
R6500/1

~

~

_____________________

~

~

~

~

~~~_ _ _ _ _8~q,_2_C_L_0_C_K_CY_C_LE_S_M_IN_IM_U_M_________~
~

RES

"'""""'''''''''''''''''''''''''''a-------------------Irv--~

3-146

~

RES TRANSITION WINDOW

~

DON'T CARE STATE

R6500/1EB and R6500/1EAB

Backpack Emulator

MAXIMUM RATINGS·
Parameter

Symbol

Value

Unit

Supply Voltage

Vee

-0.3 to + 7.0

Vdc

Input Voltage

VIN

-0.3 to + 7.0

Vdc

Operating Temperature
Commercial

TA

TL to TH
o to +70

°C

TSTG

-55 to + 150

°C

Storage Temperature

·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

DC CHARACTERISTICS
(Vee

= 5.0V

±5%, Vss

= OV;

TA

0° to 70°, unless otherwise specified)
Min

Typl

Max

Input High Voltage
00-07

VIH

Vss +24

-

-

V

Input Low Voltage
00-07

VIL

-

-

Vss +O.B

V

Input Leakage Current (Three-State 011)
00-07

liN

-

-

± 10.0

~A

VIN = 0.4 to 2.4V
Vee = 5.25V

Output High Voltage (Except XTLO)
00-07, AO-All, OE

VOH

Vss +2.4

-

-

V

ILOAD = -100
Vss = 4.75V

Output Low Voltage
00-07, AO-Al1 , OE

VOL

-

-

Vss +0.6

V

ILOAD = 1.6 mA
Vss = 4.75V

I/O Port Pull-Up ReSistance

RL

3.0

6.0

115

Kohm

Input Capacitance
00-07

CIN

-

-

15

pF

TA = 25°C
VIN = OV
I = 1.0 MHz

Output CapaCitance (Three-State Off)
AO-All

COUT

-

-

12

pF

TA = 25°C
VIN = OV
I = 1.0 MHz

Power Dissipallon (Loss EPROM)

PD

-

BOO

1300

mW

TA = O°C

Parameter

Symbol

Notes:
1. Typical values measured at TA = 25°C and Vcc = 5.0V.
2. Negative sign indicates outward current flow, positive indicates inward Ilow.

3-147

Unit

Test Conditions

~A

Backpack Emulator

R6500/1EB and R6500/1EAB
PACKAGE DIMENSIONS
40·PIN BACKPACK

. 1-- 0.050 ± .020

I

- - - 1 . 2 2 0 MAX - - - -

~

-,- - [
0.300
_

I

1_0.530

SO'_I

0.185
MAX

MAX

o.o:t~

±±~::o

0050
BOTH ENDS

_

IIJ I.
.11._°,018
1-------1R~~
0.100 ±.010 TYP

3·148

II

0.040

±.003 _ _ +.0(!7 TYP
TYP
-.002

I

0.125
MIN

R6S00/11-/12-/1S-/16

'1'

Rockwell

R6500/11, R6500/12,
R6500/15 AND R6500/16
ONE·CHIP MICROCOMPUTERS
SECTION 1
INTRODUCTION

1.1 FEATURES

-Internal clock With external 2 MHz to 4 MHz series
resonant XTAL at two or four times internal frequency
-External clock Input divided by one, two or four
• 11-'s rninimum instruction execution time @ 2 MHz
• NMOS-3 silicon gate, depletion load technology

• Enhanced 6502 CPU
-Four new bit manipulation instructions:
Set Memory Bit (SMB)
Reset Memory Bit (RMB)
Branch on Bit Set (BBS)
Branch on Bit Reset (BBR)
-Decimal and binary arithmetic modes
-13 addreSSing modes
- True indeXing
•
•
•
•
•
•
•
•

•
•
•
•

3K-byte mask-programmable ROM (R6500/11, R6500/12)
4K-byte mask-programmable ROM (R6500/15, R6500/16)
192-byte static RAM
32 TTL-compatible I/O lines (R6500/11, R6500/15)
56 TTL-compatible I/O lines (R6500/12, R6500/16)
One 8-bit port may be tri-stated under software control
One 8-bit port with programmable latched input
Two 16-blt programmable counter/timers, with latches
-Pulse width measurement
-Asymmetrical pulse generation
-Pulse generation
-Interval timer
-Event counter
-Retriggerable interval timer

Single +5V power supply
12 rnW stand-by power for 32 bytes of the 192-byte RAM
40-pin DIP (R6500/11 and R6500/15)
64-pin QUIP (R6500/12 and R6500/16)

1.2 SUMMARY
These Rockwell microcomputers are complete, high-performance a-bit NMOS-3 microcomputers on a single chip, and are
compatible with all members of the R6500 family.
The R6500/11 consists of an enhanced 6502 CPU, an internal
clock oscillator, 3072 bytes of Read-Only Memory, 192 bytes
of Random Access Memory (RAM) and versatile interface cirCUitry. The interface circuitry includes two 16-blt programmable
timer/counters, 32 bidirectional input/output lines (including four
edge-sensitive lines and Input latching on one 8-bit port), a fullduplex serial I/O channel, ten interrupts and bus expandability.
The R6500/15 is identical to the R6500/11 except it has 4K of
ROM.

• Serial port
-Full-duplex asynchronous operation mode
-Selectable 5- to 8-blt characters
-Wake-up feature
-Synchronous shift register mode
-Standard programmable bit rates, programmable up to
62.5K bitS/sec @ 1 MHz
• Ten Interrupts
-Four edge-sensitive lines; two positive, two negative
-Reset
-Non-maskable
- Two counter underflows
-Serial data received
-Serial data transmitted
• Bus expandable to 16K bytes of external memory
• Flexible clock circuitry
-2-MHz or 1-MHz internal operation

The R6500/12 consists of all the features of the R6500/11 plus
three additional 1/0 ports. It is packaged in a 64 pin QUIP.
The R6500/16 is identical to the R6500/12 except it has 4K of
ROM.
The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction simplicity,
results in system cost-effectiveness and a wide range of computational power. These features make either device a leading
candidate for microcomputer applications.
To allow prototype circuit development, Rockwell offers a PROMcompatible 64-pin extended microprocessor device. This device.
the R6511 Q, provides all R6500/11 or R6500/15 interface lines,
plus the address bus, data bus and control lines to interface with
external memory. With the addition of external circuits it can also
be used to emulate the R6500/12 or R6500/16 (contact Rockwell
sales offices listed on the back page for details).

Document No. 29651N23
3-149

Product Description Order No. 2119
Rev_ 5, October 1984

3

One-Chip Microcomputers

R6500/11·/12·/15·/16
A backpack emulator, the R65/11 EB, is available for developing R6500/11 applications. No backpack part is available
for the R6500/12.

1.3 CUSTOMER OPTIONS
The R6500/11 microcomputer is available with the following
customer specified mask options:

The R6511Q may also be used as a CPU-RAM-I/O counter

• Option
• Option
., Option
• Option
• Option
• Option

device in multichip systems.

Rockwell supports development of the devices
System 65 Microcomputer Development System
R6500/* Family of Personality Modules. Complete
emulation with the R6500/ .. Family of Personality
allows total system test and evaluation.

with the
and the
in-circuit
Modules

1 Crystal or RC oSf:;illator
2 Clock divide by 2 or 4
3 Clock MASTER Mode or SLAVE Mode
4 Port A with or without internal pull-up resistors
5 Port B with or without internal pull-up resistors
6 Port C with or without internal pull-up resistors

All options should be specified on an R6500/11 or 115 order
form.

This product description is for the reader familiar with the
R6502 CPU hardware and programming capabiltties. A
detailed description of the R6502 CPU hardware is included
in the R6500 Microcomputer System Hardware Manual (Order
Number 201). A description of the instruction capabilities of
the R6502 CPU is contained in the R6500 Microcomputer
System Programming Manual (Order Number 202).

The R6500/12 or 116 is available with all of the above options
plus:
• Option 7
• Option 8

3-150

Port F with or without internal pull-up resistors
Port G with or without internal pull-up resistors

R6S00/11-/12-/1S-/16

One-Chip Microcomputers

SECTION 2
INTERFACE REQUIREMENTS
This section describes the interface requirements for the
single chip microcomputer devices. Figure 2-1 is the Interface Diagram for the devices, Figure 2-2 and Figure 2-3 show
the mechanical outline and pin out configurations and

Table 2-1 describes the function of each pin. Figure 3-1 has
a detailed block diagram of the device which illustrates its
internal functions.

XTLO~----~----------~R~65S.0~0~/'~1(0"R~R66!5~0~0/~,55----------~

. . - '------1--'1

XTLI

CLOCK
OSCILLATOR

RES----I~

EDGE DETECT

INTERRUPT
LOGIC

NMI----I~

.e~A

1

PAO-PA7 (PAD, PAl,
POSITIVE: PA2, PA3
NEGATIVE EDGE DETECTS)

1

Vcc----I~
Vss---~

I'----~~_______,'II'----

PBO-PB7 (LATCHED INPUTS)

I

rom------,B

~_ _ _

1,----:'_______,"

DS(PAD) (INPUT DATA STROBE)'
PCO-PC7/(AO-A3, A12,
RIW, A13, EMS)

II,----PORT------,CI

3072 x
4096 x

a (111 OR 112)
a (115 OR 116)
ROM

PGO-PG7

OaC)

I

rome

CONTROL
REGISTERS

16 BIT
COUNTER/LATCH
A

16 BIT
COUNTER/LATCHES
B

SERIAL RECEIVE,
TRANSMIT
REGISTERS

I

~--------------------------------.

1--' '--I
L PORT~~ L PORT~~

!

PDO-PD71
(DATAIADDR BUS (A4-All»

pORT~1

_--t..

1......
~CA (PA4)'
1....
__---1•• CB (PAS)'

t-----.

SO (PA6)'
SI (PA7)'

paC)

PEO-PE7

\4_ _ _

PFO-PF7

L _ _ -------1
R6500112 OR R6500116

'MULTIPLEXED FUNCTION PINS

Figure 2.1

Interface Diagram
3-151

One-Chip Microcomputers

R6500111-/12 -/15 -/16

DOT OR NOTCH
TO LOCATE
PIN NO 1

0155 MAX
(393 MM)

L-------i~

(025 MM)

I

T

L

(4851 MM)
(48 00 MM)

2050 MAX
(5130MM)

19 EQUAL SPACES
0100 c
sndLoglc
Un,\(ALU)

'"

en

~eglstllr

~"9'0I8f

Q

~
....

•
:::t

I

INTERNAL ADDRESS BUS

I

INSTRUCTION CONTROL LINES

I

~
INTERNAL DATA BUS -

,--

,--

n

,
op

REGISTER/PORT CONTROL (Cl TIME)

-

,--,--r--,--

~

m

Proces,,,,

Enabl!

~
!

~
Commun,cat.on
Con\I

[S:
~ ~ j

',0
P""C

~~"

I :~IA §I :::~,

I~
B(161

~

CounterS
(16)

!

rt~~)

'--

:r f"'l~[§:]
latch
AII6)

000"," A
!l61

XtJITR
Bult.rlBI

;.:,~':

Reg"'er

l!

·R6500/110~lv

Rev.
Buffer!81

:',".:.: ~

SUlIU.

RISter

::::',
Reg",e'

1

II

"

CirCUit

~:;:'~,

Lpg,c

is"

s:::

c;"

Clock

O.. ,II.,or

an
o

3

"D
Figure 3-1.

C

System Block Diagram

Ci

m

til

R6500/11·/12·/15·/16

One-Chip Microcomputers

3.1.8 Interrupt Logic

3.3 READ-ONL Y-MEMORY (ROM)

Interrupt logic controls the sequencing of three interrupts;
RES, NMI and IRQ. IRQ is generated by anyone of eight
conditions: 2 Counter Overflows, 2 Positive Edge Detects,
2 Negative Edge Detects, and 2 Serial Port Conditions.

In the R6500/11 or R6500/12 the ROM consists of 3072 by1es
(3K) of mask programmable memory with an address space
from F400 to FFFF. ROM locations FFFA through FFFF are
assigned for interrupt and reset vectors.

3.2 NEW INSTRUCTIONS

In the R6500/15 or R6500/16 the ROM consists of 4096 by1es
(41<) of mask programmable memory with an address space
from FOOO to FFFF. ROM locations FFFA through FFFF are
assigned for interrupt and reset vectors.

In addition to the standard 6502 instruction set, four instructions have been added to the devices to simplify operations
that previously required a read/modify/write operation. In
order for these instructions to be equally applicable to any
I/O ports, with or without mixed input and output functions,
the I/O ports have been designed to read the contents of the
specified port data register during the Read cycle of the read/
modify/write operation, rather than I/O pins as in normal read
cycles. The added instructions and their format are explained
in the following subparagraphs. Refer to Appendix A for the
Op Code mnemonic addressing matrix for these added
instructions.

3.4 RANDOM ACCESS MEMORY (RAM)
The RAM consists of 192 bytes of read/write memory with
an assigned page zero address of 0040 through OOFF. The
R6500/11 provides a separate power pin (VAA ) which may be
used for standby power for 32 bytes located at 0040-005F.
In the event of the loss of Vee power, the lowest 32 by1es of
RAM data will be retained if standby power is supplied to the
VAA pin. If the RAM data retention is not required then VAR
must be connected to Vee. During operation VRR must be at
the Vee level.

3.2.1 Set Memory Bit (SMB m, Addr.)
For the RAM to retain data upon loss of Vee, VRR must be
supplied within operating range and RES must be driven low
at least eight P2 clock pulses before Vee falls out of operating
range. RES must then be held low while Vee is out of operating range and until at least eight P2 clock cycles after Vee
is again within operating range and the internal ~2 oscillator
IS stabilized. VRR must remain within Vee operating range
during normal operation. When Vee IS out of operating range,
VRR must remain within the VRR retention range In order to
retain data. Figure 3.2 shows tYPical waveforms.

This instruction sets to "1" one of the a-bit data field specified
by the zero page address (memory or I/O port). The first byte
of the instruction specifies the 5MB operation and 1 of a bits
to be set. The second byte of the instruction designates
address (OO-FF) of the byte or I/O port to be operated upon.

3.2.2 Reset Memory Bit (RMB m, Addr.)
This instruction is the same operation and format as 5MB
instruction except a reset to "0" of the bit results.

3.2.3 Branch On Bit Set Relative (BBS m, Addr,
DEST)

RAM OPERATING MODE

~
__ l

This Instruction tests one of a bits designated by a three bit
Immediate field within the first by1e of the instruction. The
second by1e IS used to deSignate the address of the byte to
be tested within the zero page address range (memory or
I/O ports). The third by1e of the instruction is used to specify
the a bit relative address to which the Instruction branches
if the bit tested is a "1 ". If the bit tested is not set, the next
sequential instruction IS executed.

VRRO
Vee

RES
1
2
3
4
5

3.2.4 Branch On Bit Reset Relative (BBR m,
Addr,DEST)
ThiS instruction is the same operation and format as the BBS
instruction except that a branch takes place if the bit tested
IS a "0".

~--

CD

~~

~®---~~er---,I~~I r-

r--@ r-1!--®

II

-1

[::®

INITIAL APPLICATION OF vee AND V RR •
LOSS OF Vee, RAM ON STANDBY POWER.
REAPPLICATION OF Vee.
> 8112 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
> 8 1»2 CLOCK PULSES.

Figure 3-2.

3-156

RAM RETENTION MODE

Data Retention Timing

R6500111-/12-/15-116

One-Chip Microcomputers

3.5 CLOCK OSCILLATOR
Internal timing can also be controlled by driving the XTU pin
with an external frequency source. Figure 3-3c shows typical
connections. If XTLO is left floating, the external source is
divided by the internal countdown network. However, if XTLO
IS tied to Vss , the Internal countdown network IS bypassed
causing the chip to operate at the frequency of the external
source.

Three customer selectable mask options are available for
controlling the device timing. It can be ordered with a crystal
or RC oscillator, a divide by 2 or divide by 4 countdown network and for clock master mode or clock slave mode
operation.
For 2 MHz internal operations the divide by two option must
be specified.

The operation described above assumed a CLOCK MASTER
MODE mask option. In thiS mode a frequence source (crystal,
RC network or external source) must be applied to the XTU
and XTLO pins. ~2 is a buffered output signal which closely
approximates the internal timing. When a common external
source IS used to drive multiple devices the internal timing
between devices as well as their ~2 outputs will be skewed
In time. If skeWing represents a system problem it can be
aVOided by'the Master/Slave connection and options shown
In Figure 3-4.

A reference frequency can be generated with the on-chip
oscillator using either an external crystal or an external resistor
depending on the mask option selected. The oscillator reference frequency passes through an internal countdown network (divide by 2 or divide by 4 option) to obtain the Internal
operating frequency (see Figure 3-3a and 3-3b). The external
crystal generated reference frequency IS a preferred method
since the resistor method can have tolerances approaching

50%.
One device IS operated In the CLOCK MASTER MODE and
a second In the CLOCK SLAVE MODE. Mask options In the
SLAVE unit convert the 02 signal Into a clock input pin which
is tightly coupled to the internal timing generator. As a result
the Internal timing of the MASTER and SLAVE units are synchrOnized with minimum skew. If the (32 signal to the SLAVE
Unit IS Inverted, the MASTER and SLAVE UNITS WILL
OPERATE OUT OF PHASE. ThiS approach allows the two
devices to share external memory using cycle stealing
techniques.

Note:
When operating at a 1 MHz internal frequency place
a 15-22 pf capacitor between XTLO and ground.

R = 2.4K
tor 2 MHz

d

Li

tiNT

= 1 MHz

R6500/11

XTLO

tEXT

= 2X

tiNT

a. Resistor Input

LI

~

2-6 MHz c::::::J

6500/11 OR /12

R6500/11 tiNT'" 2 MHz

XTLO

XTLI

I EXT = 2X or 4X liNT

=
b. Crystal Input

MASTER

02

(OUTPUT CLOCK)

XTLO

Vcc

r--

300n
2-4 MHz

XTLI

tiNT'"

6500111 OR 112

2 MHz

R6500/11

NC

XTLO

I EXT

I
I
I __
L

= 2X or 4X

INVERTER USED

--1 WHEN SLAVE IS
i TO OPERATE
__ ..J

OUT OF PHASE
WITH MASTER

XTLI

tiNT

SLAVE

02
(INPUT CLOCK)

VCF

1-2 MHz

XTLO

~~LI
I

tiNT

= 1 or 2

MHz

Figure 3-4.

R6500/11

v __

~LO

tEXT

=

tiNT

c. Clock Inputs

Figure 3-3.

Clo.:k Oscillator Input Options

3-157

Master/Slave Connections

One-Chip Microcomputers

R6500/11·112·/15·/16

3.7 INTERRUPT FLAG REGISTER (IFR)
AND INTERRUPT ENABLE
REGISTER (IER)

3.6 MODE CONTROL REGISTER (MCR)
The Mode Control Register contains control bits for the multifunction I/O ports and mode select bits for Counter A and
Counter B. Its setting, along with the setting of the Serial
Communications Control Register (SCCR), determines the
basic configuration of the device in any application. Initializing this register is one of the first actions of any software
program. The Mode Control Register bit assignment is shown
in Figure 3-5.

MeR

An IRQ interrupt request can be initiated by any or all of eight
possible sources. These sources are all capable of being
enabled or disabled by the use of the appropriate interrupt
enabled bits in the Interrupt Enable Register (IER). Multiple
simultaneous interrupts will cause the IRQ interrupt request
to remain active until all interrupting conditions have been
serviced and cleared.
The Interrupt Flag Register contains the information that
indicates which I/O or counter needs attention. The contents
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge detect IFR bits may be
cleared by executing a RMB instruction at address location
0010. The RMB X, (0010) instruction reads FF, modifies bit
X to a "0", and writes the modified value at address location
0011. In this way IFR bits set to a "1" after the read cycle of
a Read-Modify-Write instruction (such as RMB) are protected
from being cleared. A logic "1" is ignored when writing to
edge detect IFR bits.

Addr 0014

Counter B
Mode Select

I I

Bus Mode Select

6- - 0 Interval Timer
0 - - 1 Pulse Generation
1 - - 0 Event Counter
1 - - 1 Pulse Width Meas.

0 - 0 Interval Timer

0 - 1 Asymmetric Pulse Generation
10 Event Counter
1_
1 Retrlggerable Interval Timer
Port B latch
(1 = Enabled)
Port 0 Tn-State
(0= Trl State High Impedance Mode)

Each IFR bit has a corresponding bit in the Interrupt Enable
Register which can be set to a "1" by writing a "1" in the
respective bit position at location 0012. Individual IER bits
may be cleared by writing a "0" in the respective bit position,
or by RES. If set to a "1", an IRQ will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag Register and Interrupt Enable Register bit assignments are shown
in Figure 3-6 and the functions of each bit are explained in
Table 3-1.

O-XNormal
10 Abbr. Bus

1_

1 Mux'd Bus

Figure 3-5.

Mode Control Register

The use of Counter A Mode Select is shown in Section 6.1.
The use of Counter B Mode Select is shown in Section 6.2.
The use of Port B Latch Enable is shown in Section 4.4.
The use of Port D in Tri-State Enable is shown in Section
4.6.
The use of Bus Mode Select is shown in Section 4.5 and 4.6.

3-158

R6S00/11-112-/1S-116

One-Chip Microcomputers

IER

IFR

PA2 Negative

Edge Detect
PA3 Negative
Edge Detect
Counter A
Underflow Flag
Counter B

Underflow Flag

Receiver

Flag
XMTR

Flag

Figure 3-6.

Interrupt Enable and Flag Registers

Table 3-1
BIT
CODE

Interrupt Flag Register Bit Codes
FUNCTION

IFR 0:

PAO Positive Edge Detect Flag-Set to a "1" when a positive going edge IS detected on PAO.
Cleared by RMB 0 (0010) instruction or by RES.

IFR 1:

PAl Positive Edge Detect Flag-Set to a ~en a pOSitive going edge is detected on PAl.
Cleared by RMB 1 (0010) instruction or by RES.

IFR 2:

PA2 Negative Edge Detect Flag-Set to a 1 when a negative going edge is detected on PA2.
Cleared by RMB 2 (0010) Instruction or by RES.

IFR 3:

PA3 Negative Edge Detect Flag-Set to 1 when a negative going edge is detected on PA3.
Cleared by RMB 3 (0010) instruction or by RES.

IFR 4:

Counter A Underflow Flag-Set to a 1 when Counter A underflow occurs. Cleared by reading
the Lower Counter A at location 0018, by writing to address location 001A, or by RES.

IFR 5:

Counter B Underflow Flag-Set to a 1 when Counter B underflow occurs. Cleared by reading
the Lower Counter B at location 001C, by writing to address location 001E, or by RES.

IFR 6:

Receiver Interrupt Flag-Set to a 1 when any of the Serial Communication Status Register bits
othrough 3 is set to a 1. Cleared when the Receiver Status bits (SCSR 0-3) are cleared or by
RES

IFR 7:

Transmitter Interrupt Flag-Set to a 1 when SCSR 6 is set to a 1 while SCSR 5 is a 0 or SCSR
7 is set to a 1. Cleared when the Transmitter Status bits (SCSR 6 & 7) are cleared or by RES.

3-159

R6S00/11-/12-/1S-/16

One-Chip Microcomputers
zero. This bit is cleared to logic 0 when the resultant a bits
of a data movement or calculation operation are not all zero.
The R6500 instruction set contains no instruction to specifically set or clear the Zero Bit. The Zero Bit is, however,
affected by the following instructions; ADC, AND, ASL, BIT,
CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY,
LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TVA.

3.8 PROCESSOR STATUS REGISTER
The a-bit Processor Status Register, shown in Figure 3-7,
contains seven status flags. Some of these flags are controlled by the user program; others may be controlled both
by the user's program and the CPU. The R6502 instruction
set contains a number of conditional branch instructions
which are designed to allow testing of these flags. Each of
the eight processor status flags IS described in the following
sections.

3.8.3 Interrupt Disable Bit (I)

The Carry Bit (C) can be considered as the ninth bit of an
arithmetic operation. It is set to logic 1 if a carry from the
eighth bit has occurred or cleared to logic 0 if no carry
occurred as the result of arithmetic operations.

The Interrupt Disable Bit (I) is used to control the servicing
of an interrupt request (IRQ). If the I Bit is reset to logic 0,
the IRQ signal will be serviced. If the bit is set to logic 1, the
IRQ Signal will be ignored. The CPU will set the Interrupt
Disable Bit to logic 1 if a RESET (RES), IRQ, or Non-Maskable Interrupt (NMI) signal is detected.

The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Clear Carry (CLC) instruction, respectively. Other operations which affect the Carry Bit
are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, ROR, RTI,
and SBC.

The I bit IS cleared by the Clear Interrupt Mask InstructIOn
(CLI) and is set by the Set Interrupt Mask Instruction (SEI).
This bit IS set by the BRK Instruction. The Return from Interrupt (RTI) and Pull Processor Status (PLP) instructions will
also affect the I bit.

3.8.1 Carry Bit (C)

3.8.2 Zero Bit (Z)
The Zero Bit (Z) is set to logiC 1 by the CPU during any data
movement or calculation which sets all a bits of the result to

[NIVIIBIDlllzJcJ

~,

CARRY(C)0)

=

Carry Set

o = Carry Clear
ZERO (Z)0)
1

=Zero Result

o = Non-Zero Result
INTERRUPT DISABLE (I) ~
1

= IRQ Interrupt Olsabled

o = IRQ Interrupt Enabled
DECIMAL MODE (0)0

1

= DeCimal Mode

o = Bmary Mode

BREAK COMMAND (B)0)
1 _ Break Command

o -= Non Break Command
OVERFLOW (0)0)

1

= Overflow Set

o = Overflow Clear
NEGATIVE (N)0)

NOTES

CD Not Initialized by RES
® Set to LogiC 1 by RES

Figure 3-7.

1

= Negative Value

0= Postlve Value

Processor Status Register

3-160

R6500/11·/12·/15·116

One-Chip Microcomputers
This indicator only has meaning when signed arithmetic (sign
and seven magnitude bits) is performed. When the ADC or
SBC instruction is performed, the Overflow Bit is set to logic
1 if the polarity of the sign bit (bit 7) is changed because the
result exceeds +127 or -128; otherwise the bit is cleared
to logic O. The V bit may also be cleared by the programmer
uSing a Clear Overflow (CLV) Instrucllon.

3.8.4 Decimal Mode Bit (D)
The Decimal Mode Bit (D), is used to control the arithmetic
mode of the CPU. When this bit is set to logic 1, the adder
operates as a decimal adder. When this bit is cleared to logic
0, the adder operates as a straight binary adder. The adder
mode is controlled only by the programmer. The Set Decimal
Mode (SED) instruction will set the 0 bit; the Clear Decimal
Mode (CLD) Instruction will clear it. The PLP and RTI instructions also effect the Decimal Mode Bit.

The Overflow Bit may also be used with the BIT instruction.
The BIT instruction which may be used to sample interface
devices, allows the overflow flag to reflect the condition of bit
6 in the sampled field. During a BIT instruction the Overflow
Bit is set equal to the content of the bit 6 on the data tested
with BIT instruction. When used in this mode, the overflow
has nothing to do with signed arithmetic, but is just another
sense bit for the microprocessor. Instructions which affect the
V flag are ADC, BIT, CLV, PLP, RTI and SBC.

CAUTION
The Decimal Mode Bit will either set or clear in an
unpredictable manner upon power application. This bit
must be initialized to the desired state by the user program or erroneous results may occur.

3.8.7 Negative Bit (N)
3.8.5 Break Bit (B)

The Negative Bit (N) is used to indicate that the sign bit (bit
7), in the resulting value of a data movement or data anthmetic operation, IS set to logic 1. If the sign bit IS set to logic
1, the resulting value of the data movement or arithmetic
operation is negative; If the sign bit is cleared, the result of
the data movement or arithmetiC operation is positive. There
are no instructions that set or clear the Negative Bit since the
Negative Bit represents only the status of a result. The
instructions that effect the state of the Negative Bit are: ADC,
AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EaR,
INC, INX, INY, LOA, LOX, LOY, LSR, ORA, PLA, PLP, ROL,
ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TVA.

The Break Bit (B) IS used to determine the condition which
caused the IRQ service routine to be entered. If the IRQ service routine was entered because the CPU executed a BRK
command, the Break Bit will be set to logic 1. If the IRQ routine was entered as the result of an IRQ signal being generated, the B bit will be cleared to logic O. There are no
instructions which can set or clear this bit.

3.8.6 Overflow Bit (V)
The Overflow Bit (V) is used to indicate that the result of a
signed, binary addition, or subtraction, operation IS a value
that cannot be contained in seven bits (-128 '" n '" 127).

3-161

One-Chip Microcomputers

R6S00111-/12-/1S-/16

SECTION 4
PARALLEL INPUT/OUTPUT PORTS

The R6S00/11 or R6S00/1S has 32 I/O lines grouped into four
8-bit ports (PA, PB, PC, and PD). Ports A through C may be
used either for input or output individually or in groups of any
combination. Port D may be used as all inputs or all outputs.

Port D may only be all inputs or all outputs. All inputs is
selected by setting bit S of the Mode Control Register (MCRS)
to a "0".
The status of the input lines can be interrogated at any time
by reading the 1/0 port addresses. Note that this will return
the actual status of the input lines, not the data written into
the 110 port registers.

The R6S00/12 or R6S00/16, a 64 pin QUIP device, has three
additional ports: PE, PF and PG. PE is outputs only; PF and
PG are bidirectional.
Multifunction 110's such as Port A and Port C are protected
from normal port 1/0 instructions when they are programmed
to perform a multiplexed function.
Internal pull-up resistors (FET's with an impedance range of
3K ~ Rpu ~ 12K ohm) may be provided on all port pins
except Port D and E as a mask option.

ReadlModifylWrite instructions can be used to modify the
operation of PA, PB, PC, & PD and also ports PF and PG
of the R6S00/12. During the Read cycle of a Read/Modifyl
Write instruction the Port 110 register is read. For all other
read instructions the port input lines are read. ReadlModifyl
Write instructions are: ASL, DEC, INC, LSR, RMB, ROL,
ROR, and 5MB.

The direction of the 1/0 lines are controlled by four 8-bit port
registers located in page zero. This arrangement provides
quick programming access using simple two-by1e zero page
address instructions. There are no direction registers associated with the 1/0 ports, which simplifies 1/0 handling. The
VO addresses are shown in Table 4-1. Section E.6 shows
the 1/0 Pcrt Timing.

Outputs for Ports A thru D and Ports E thru G of the R6S00112
or R6S00/16 are controlled by writing the desired 1/0 line output states into the corresponding I/O port register bit positions. A logic 1 will force a high (>2.4V) output while a logic
o will force a low « 0.4V) output.

Table 4-1.

I/O Port Addresses

Port

Address

A

0000
0001
0002
0003
0004
0005
0006

B
C
D
E
F
G

4.2 OUTPUTS

Port D all outputs is selected by setting MCRS to a "1".
Port E is always all outputs.

4.3 PORT A (PA)
Port A can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard parallel 8-bit, bit independent, 110 port
or as serial channel 1/0 lines, counter 1/0 lines, or an input
data strobe for the Port B input latch option. Table 4-2 tabulates the control and usage of Port A.

4.1 INPUTS
In addition to their normal 1/0 functions, PAO and PAl can
detect positive going edges, and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate an
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rate at which an edge can be detected is onehalf the 02 clock rate. Edge detection timing is shown in Section E.S.

Inputs for Ports A, B, and C and also Ports F and G of the
R6S00/12 or R6S00/16 are enabled by loading logic 1 into
all I/O port register bit positions that are to correspond to I/O
input lines. A low «0.8V) input signal will cause a logic 0
to be read when a read instruction is issued to the port register. A high (>2.0V) input will cause a logic 1 to be read.
An RES signal forces all 1/0 port registers to logic 1 thus initially treating all I/O lines as inputs.

3-162

R6S00/11·/12·/1S·116

One-Chip Microcomputers
Table 4-2.

Port A Control & Usage

PAO 1/0

PORT B LATCH MODE

=0

MCR4

MCR4

SIGNAL

PAO(2)

=

1

SIGNAL

NAME

TYPE

NAME

TYPE

PAO

1/0

PORT B
LATCH STROBE

INPUT (1)

PA1-PA3110

PAl (2)

SIGNAL

PA2(3)

NAME

TYPE

PA3 (3)

PAl
PA2
PA3

1/0
1/0
1/0

COUNTER A 1/0

PA41/0

PA4

MCRO = 0
MCRI = 0
SCCR? = 0
RCVR SIR MODE = 0
(4) (5)

MCRO = 1
MCRI = 0
SCCR? = 0
RCVR SIR MODE = 0
(4)

SIGNAL

SCCR? = 0
SCCR6 = 0
MCRI = 1

SIGNAL

SIGNAL

NAME

TYPE

NAME

TYPE

NAME

PA4

110

CNTA

OUTPUT

CNTA

I
I

TYPE
INPUT (1)

SERIAL 1/0 SHIFT REGISTER CLOCK
seCR?
SCCR5

=1
=1

RCVR SIR MODE
(4)

SIGNAL
NAME
XMTR CLOCK

PAS

I

I

NAME

I

OUTPUT

RCVR CLOCK

MCR3
MCR2

SIGNAL

=0
=1

MCR3
MCR2

NAME

TYPE

NAME

PA5

1/0

CNTB

OUTPUT

CNTB

SERIAL 1/0
XMTR OUTPUT

PA61/0

=0

SCCR?

SIGNAL

PM

I

SCCR6

1

SIGNAL
TYPE

NAME

TYPE

1/0

XMTR

OUTPUT

SERIAL 110
RCVRINPUT

PA?IIO

PA7

=

=0

SCCR6

SIGNAL

=1

SIGNAL

NAME

TYPE

NAME

TYPE

PA7

1/0

RCVR

INPUT (1)

3-163

=1
=X

SIGNAL

SIGNAL
TYPE

NAME

INPUT (1)

COUNTER B 1/0

=0
=0

SCCR?

TYPE

l

NAME

PA6

1

SIGNAL
TYPE

PA51/0
MCR3
MCR2

=

I
I

TYPE
INPUT (1)

Notes:
(1) Hardware Buffer Float
(2) Posttlve Edge Detect
(3) Negative Edge Detect
(4) RCVR SIR Mode = 1 when
SCCR6 • SCCR5 • SCCR4 = 1
(5) For the following mode combina·
lions PA4 is availab!e as an input
only pin:
SCCR?·SCCR&SCCR5.MCRI
+ SCCR?·SCCR&SCCR4·MCRI
+ SCCR?·SCCR&SCCR5
+ SCCR?·SCCR50SCCR4·

One-Chip Microcomputers

R6500/11·112·115·/16
4.4 PORT B (PB)

4.5 PORT C (PC)

Port B can be programmed as an a bit, bit independent I/O
port. It has a latched input capability which may be enabled
or disabled via the Mode Control Register (MCR). Table
4-3 tabulates the control and usage of Port B. An Input Data
Strobe signal must be provided thru PAO when Port B is programmed to be used with latched input option. Input data
latch timing for Port B is shown in Section E.S.

Port C can be programmed as an I/O port and in conjunction
with Port D, as an abbreviated bus, or as a multiplexed bus.
When used in the abbreviated or multiplexed bus modes,
PCO-PC7 function as AO-A3, A12, R/W, A13, and EMS,
respectively, as shown in Table 4-4. EMS (External Memory
Select) is asserted (low) whenever the internal processor
accesses memory area between 0100 and 3FFF. (See
Memory Map, Appendix B). The leading edge of EMS may
be used to strobe the eight address lines multiplexed on Port
D in the Multiplexed Bus Mode. See Appendix E.3 through
E.S for Port C timing.

Table 4-3.

Port B Control & Usage

Latch
Mode

1/0 Mode

MCR4

=0

MCR4
(2)

=1
4.6 PORT 0 (PO)

Signal

Signal

Pin
Name

Name

Type (1)

Name

Type

PBO
PBt
PB2
PB3
PB4
PBS
PBS
PB7

PBO
PBt
PB2
PB3
PB4
PBS
PBS
PB7

I/O
1/0
1/0
1/0
1/0
1/0
1/0
1/0

PBO
PBt
PB2
PB3
PB4
PBS
PBS
PB7

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

Port D can be programmed as an I/O Port, an a-bit tri-state
data bus, or as a multiplexed bus. Mode selection for Port
D is made by the Mode Control Register (MCR). The Port D
output drivers can be selected as tri-state drivers by setting
bit S of the MCR to 0 (zero). Table 4-S shows the necessary
settings for the MCR to achieve the various modes for Port
D. When Port D is selected to operate in the Abbreviated
Mode PDO-PD7 serves as data register bits DO-D7. When
Port D is selected to operate In the Multiplexed Mode data
bits DO through D7 are time multiplexed with address bits A4
through A 11, respectively. Refer to the Memory Maps
(Appendix C) for Abbreviated and Multiplexed memory
assignments. See Appendix E.3 through E.S for Port D timing.

(1) Resistive pull-up, active buffer pull down

(2) Input data is stored in por.t B latch by PAO pulse

4.7 PORT E, PORT F AND PORT G (PE,
PF & PG) R6500/12 OR 116 ONLY
Port E only operates in the Output mode. It provides a Darlington output that can source current at the high (1) level.
Port F and Port G operate identically and can be programmed as bidirectional VO ports. They have standard
output capability. See Appendix E.5 for Port E, F & Port G
timing.

3-164

R6S00/11-112-/1S-116

One-Chip Microcomputers

Table 4-4.

Port C Control and Usage
Abbreviated
Mode

1/0 Mode

MCR7
MCR6

=0
=X

MCR7
MCR6

Signal
Pin
Name
PCO
PC1
PC2
PC3
PC4
PCS
PCS
PC?

Multiplexed
Mode

=1
=0

MCR7
MCR6

Signal

Name

Type
(1)

PCO
PC1
PC2
PC3
PC4
PCS
PCS
PC?

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

=1
=1

Signal

Name

Type
(2)

Name

Type
(2).

AO
A1
A2
A3
A12
RW
A13
EMS

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

AO
A1
A2
A3
A12
RW
A13
EMS

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

(1) Resistive Pull-Up, Active Buffer Pull-Down
(2) Active Buffer Pull-Up and Pull-Down

Table 4-5.

Abbreviated
Mode

1/0 Modes
MCR7
MCR6
MCR5

=0
=X
=0

Port 0 Control and Usage

MCR7
MCR6
MCR5

Signal

=0
=X
=1

MCR7
MCR6
MCR5

Signal

Multiplexed Mode

=1
=0
=1

MCR7
MCR5
MCR5

Signal

=1
=1
=1

Signal

Signal

Phase 1

Phase 2

Pin
Name

Name

Type (1)

Name

Type (2)

Name

Type (3)

Name

Type (2)

Name

Type (3)

PD~

PD~

PD~

PD1
PD2
PD3
PD4
PD5
PD6
PD?

PD1
PD2
PD3
PD4
PD5
PD6
PD7

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

DATAO
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA?

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

A4
AS
A6
A?
AS
A9
A10
A11

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

DATAO
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA?

1/0
1/0
1/0
1/0

(1) Tri-State Buffer
(2) Tri-State Buffer
(3) Tri-State Buffer

PD1
PD2
PD3
PD4
PD5
PD6
PD?

High Impedance Mode
Active Mode
Active Mode Only During the Phase 2 Portion of a Write Cycle

3-165

110
110
1/0
1/0

One-Chip Microcomputers

R6S00/11·/12·/1S·/16

SECTION 5
SERIAL INPUT/OUTPUT CHANNEL
The device provides a full duplex Serial I/O channel with programmable bit rates and operating modes. The serial I/O
functions are controlled by the Serial Communication Con,trol
Register (SCCR) . .The SCCR bit assignment is shown in
Figure 5-1. The serial bit rate is determined by Counter A
for all modes except the Receiver Shift Register (RCVR
SIR) mode for which an external shift clock must be provided.
The maximum data rate using the internal clock is 62.5K bits
per second (@ ¢2 =1 MHz). The transmitter (XMTR) and
receiver (RCVR) can be independently programmed to
operate in different modes and can be independently enabled or disabled.

ASYNCHRONOUS MODE WITHOUT PARITY
8-BIT DATA

~RTul

- L_ _ _ _

5-81T DATA

1
1

a
a

ASYNCHRONOUS MODE WITH PARITY
8·BIT DATA

IPA~ITY I
I PA~lTY 1

6-BIT DATA

a-Odd Parity
1_Even Parity
o Parity Disable
1 Parity Enable
a- 8 Bits/Char
1 _7 Bits/Char
a- 6 Bits/Char
1 _ 5 Bits/Char

2 STOP

2 STOP

2 STOP

SHIFT REGISTER MODe 8-81T DATA

M';-=C

WORD M

WOROM+1

SHIFT REGISTER CLOCK (PA4)

a XMTR & RCVR ASYN Mode

Figure 5-2.

1 XMTR ASYN, RCVR SIR
X XMTR SIR, RCVR ASYN

Transmitted Data Modes

In the SIR mode, eight data bits are always shifted out. Bits/
character and parity control bits are ignored. The senal data
is shifted out via ihe SO output (PA6) and the shift clock is
available at the CA (PA4) pin. When the transmitter underruns in the SIR mode the SO output and shift clock are held
in a high state.

o RCVR Disable
1 RCVR Enable
a XMTR Disable
1 XMTR Enable

Figure 5-1.

I

2·STOP

IPA~ITY I

a
o

~

2 STOP

Addr 0015

SCCR

________________________

Serial Communication Control Register

The XMTR Interrupt Flag bit (IFR7) is controlled by Serial
Communication Status Register bits SCSR5, SCSR6 and
SCSR7.

Except for the Receiver Shift Register Mode (RCVR SIR), all
XMTR and RCVR bit rates will occur at one sixteenth of the
Counter A interval timer rate. Counter A is forced into an
interval timer mode whenever the serial I/O is enabled in a
mode reqUiring an internal clock.

IFR7 = SCSR6 (SCSR5 + SCSR7)

Whenever Counter A is required as a timing source it must
be loaded with the hexadeCimal code that selects the data
rate for the serial I/O Port. Refer to Counter A (paragraph
6.1) for a table of hexadecimal values to represent the desired
data rate.

5.2 RECEIVER OPERATION (RCVR)
The receiver and its selected control and status functions are
enabled when SCCR-6 is set to a "1." In the ASYN mode,
data format must have a start bit, appropriate number of data
bits, a parity bit (if enabled) and one stop bit. Refer to paragraph 5.1 for a diagram of bit allocations. The receiver bit
period is divided into 8 sub-intervals for internal synchronization. The receiver bit stream is synchronized by the start
bit and a strobe signal is generated at the approximate center
of each incoming bit. Refer to Figure 5-3 for ASYN Receive
Data Timing. The character assembly process does not start
if the start bit signal is less than one-naif the bit time after a
low level is detected on the Receive Data Input. Framing
error, over-run, and parity error conditions or a RCVR Data
Register Full will set the appropriate status bits, and any of
the above conditions will cause an Interrupt Request if the
Receiver Interrupt Enable bit is set to logic 1.

5.1 TRANSMITTER OPERATION (XTMR)
The XTMR operation and the transmitter related control/
status functions are enabled by bit 7 of the Serial Communications Control Register (SCCR). The transmitter, when in
the Asynchronous (ASYN) mode, automatically adds a start
bit, one or two stop bits, and, when enabled, a parity bit to
the transmitted data. A word of transmitted data (in asynchronous panty mode) can have 5, 6, 7, 9r 8 bits of data.
The nine data modes are in Figure 5-2. When parity is disabled, the 5, 6, 7 or 8 bits of data are terminated with two
stop bits.
3-166

One-Chip Microcomputers

R6S00/11-/12-I1S-/16
Serial
Input

Start Bit

received data has a parity error. This bit is cleared
by reading the Receiver Data Register or by RES.
SCSR 3: Framing Error-Set to a logic 1 when the received
data contains a zero bit-after the last data or parity
bit In the stop bit slot. Cleared by reading the
Receiver Data Register or by RES. (ASYN Mode
only).
SCSR 4: Wake-Up-Set to a logic 1 by writing a "1" In bit
4 of address: 0016. The Wake-Up bit is cleared by
RES or when the receiver detects a strrng of ten
consecutive 1's. When the Wake-Up bit is set
SCSRO through SCSR3 are Inhibited.
SCSR 5: End of Transmission-Set to a logic 1 by writing
a "1" in bit position 5 of address: 0016. The End
of Transmission bit is cleared by RES or upon
writing a new data word into the Transmitter Data
Register. When the End-of-Transmisslon bit is true
the Transmitter Register Empty bit is disabled until
a Transmitter Under-Run occurs.

=:r:=:::C-:-:::JI=-::::rl

I':,---:,,-I-==--L...._: :::
LSB

Stop Bit Stop Bit

• Sertallnput Data Shifted In

Figure 5-3.

ASYN Receive Data Timing

In the SIR mode, an external shift clock must be provided at
CA (PA4) pin along with 8 bits of serial data (LSB first) at the
SI input (PA7). The maximum data rate using an external
shift clock is one-eighth the internal clock rate. Refer to
Figure 5-4 for SIR Mode Timing.

-.-_-;..-_-r__..-

Serlal...,._ _- r_ _-r--i ..._ _
Input

=r Data In
External

::. . _-''--_-'--_-'-_-'-

SCSR 6: Transmitter Data Register Empty-Set to a logic
1 when the contents of the Transmitter Data RegIster IS transferred to the Transmitter Shift RegIster. Cleared upon wrrting new data into the
Transmit Data Register. This bit is Initialized to a
logic 1 by RES.
SCSR 7: Transmitter Under-Run-Set to a logic 1 when the
last data bit IS transmitted if the transmitter is in a
SIR Mode or when the last stop bit is transmitted
If the XMTR is in the ASYN Mode while the Transmitter Data Register Empty Bit is set. Cleared by
a transfer of new data into the Transmitter Shift
Register, or by RES.

Shill~~
Clock
Serial

Output .....1,---,..-'-_ _-'-........_ _-'-_--''--_-'-_ _.LData Out

Shill

CIOCk~~

*

Senallnput Data Shifted In

** Serial Output Data Makes Transition

Figure 5-4.

SIR Mode Timing

A RCVR interrupt (IFR6) is generated whenever any of
SCSRO-3 are true.

SCSRI

7

I

6

I

5

I

4

I

3

I

5.3 SERIAL COMMUNICATION STATUS
REGISTER (SCSR)

1 1

ll

2

t

0 JAddroo16

l,,~Reg Full

RCVR Over-Run

The Serial Communication Status Register (SCSR) holds
information on various communication error conditions, status
of the transmitter and receiver data registers, a transmitter
end-of-transmission condition, and a receiver Idle line condition (Wake-Up Feature). The SCSR bit assignment IS shown
in Figure 5-5. Bit aSSignments and functions of the SCSR are
as follows:

Parity Error
Frame Error

Wok... Up
End of Transmission

XMTR Oato Rog Empty

SCSRO: Receiver Data Register Full-Set to a logic 1 when
a character is transferred from the Receiver Shift
Register to the Receiver Data Register. This bit is
cleared by reading the Receiver Data Register, or
by Fi'ES and is disabled if SCCR6 = O. The SCSR
o bit will not be set to a logic 1 if the received data
contains an error condition, instead, a corresponding error bit will be set to a logic 1.

XMTR Under-Run

Figure 5-5.

SCSR Bit Allocation

5.4 WAKE-UP FEATURE
In a multi-distributed microprocessor or microcomputer
applications, a destination addrees is USU'lliy included at the
beginning of the message. The Wake-Up Feature allows
non-seiected CPU's to Ignore the remainder of the message
until the beginning of the next mesbage by setting the WakeUp bit. As long as the Wake-Up flag is true, the Receiver
Data Register Full Flag remains false. The Wake-Up bit IS
automatically cleared when the receiver detects a string of
eleven consecutive 1's which indicates an idle transmit line.
When the next byte is received, the Receiver Data Register
Full Flag signals the CPU to wake-up and read the received
data.

SCSR 1: Over-Run Error-Set to a logic 1 when a new character IS transferred from the Receiver Shift RegIster, with the last character still in the Receiver
Data Register. This bit is cleared by reading the
Receiver Data Register, or by RES.
SCSR 2: Parity Error-Set to logic 1 when the RCVR is in
the ASYN Mode, Parity Enable bit is set, and the
3-167

R6500/11-/12-/15-/16

One-Chip Microcomputers

SECTION 6
COUNTER/TIMERS
The device contains two 16-bit counters (Counter A and
Counter B) and three 16-bit latches associated with the
counters. Counter A has one 16-bit latch and Counter B has
two 16-bit latches. Each counter can be independently programmed to operate in one of four modes:

Counter A

Upper Latch A before the contents of the 16-blt latch are
transferred to Counter A. Counter A IS set to the latch value
whenever Counter A underflows. When Counter A decrements from 0000 the next counter value Will be the latch
value, not FFFF, and the Counter A Underflow Flag (IFR 4)
Will be set to "1". ThiS bit may be cleared by reading the
Lower Counter A at localion 0018, by writing to address
location 001A, or by RES.

Counter B
• Retnggerable Interval Counter
• Asymmetrical Pulse
Generation
• Interval Timer
• Event Counter

• Pulse width
measurement
• Pulse GeneratJon
• Interval Timer
• Event Counter

Counter A operates In any of four modes. These modes are
selected by the Counter A Mode Control bits in the Control
Register.

Operating modes of Counter A and Counter B are controlled
by the Mode Control Register. All counting begins at the
initialization value and decrements. When modes are selected
requiring a counter input/output line, PA4 IS automatically
selected for Counter A and PA5 is automatically selected for
Counter B (see Table 4.2).

Counter A consists of a 16-bit counter and a 16-blt latch
organized as follows: Lower Counter A (LCA), Upper Counter
A (UCA), Lower Latch A (LLA), and Upper Latch A (ULA).
The counter contains the count of either ~2 clock pulses or
external events, depending on the counter mode selected.
The contents of Counter A may be read any time by executing a read at location 0019 for the Upper Counter A and
at location 001A or location 0018 for the Lower Counter A.
A read at location 0018 also clears the Counter A Underflow
Flag (IFR4).

I~ET ANY nME BEFORE

Figure 6-1.

COUNTER UNDERFLOW

0

1
1

1. When the Counter is decremented from 0000, the next
Counter value is the Latch value (not FFFF).
2. When a write operation is performed to the Load Upper
Latch and Transfer Latch to Counter address 001 A,
the Counter IS loaded with the Latch value. Note that
the contents of the Accumulator are loaded into the
Upper Latch before the Latch value IS transferred to
the Counter.
The Counter value IS decremented by one count at the 1/l2
clock rate. The 16-bit Counter can hold from 1 to 65535
counts. The Counter Timer capacity '5 therefore 1/LS to 65.535
ms at the 1 MHz ~2 clock rate or 0.5 /Ls to 32.767 ms at the
2 MHz ~2 clock rate. Time intervals greater than the maximum Counter value can be easily measured by counting
IRQ interrupt requests in the counter IRQ interrupt rouline.

I

COUNTER UNDERFLOW FLAG

1
1

Mode
Interval Timer
Pulse Generation
Event Counter
Pulse Width Measurement

In the Interval Timer mode the Counter IS I",liailzed to the
Latch value by either of two conditions:

COUNTER UNDERFLOW

COUNTER INTERRUPT ENABLED

0

6.1.1 Interval Timer

Counter A can be started at any lime by writing to address.
001 A. The contents of the accumulator Will be copied into the

I

0
0

The Counter IS set to the Interval Timer Mode (00) when a
RES signal IS generated.

The 16-bit latch contains the counter InJlialization value, and
can be loaded at any time by executing a write to the Upper
Latch A at location 0019 and the Lower Latch A at localion
0018. In either case, the contents of the accumulator are
copied Into the applicable latch register.

I

MCRO
(bit 0)

The Interval Timer, Pulse Generation, and Pulse Width Measurement Modes are ~2 clock counter modes. The Event
Counter Mode counts the occurrences of an external event
on the CNTR line.

6.1 COUNTER A

COUNTER"--..:.....-"'_..:....-'-_'---"-_=--..JI~(UL, LL)

MCRI
(bit 1)

I (UL, LL) ·1 I

I
I
1..---;------

When Counter A decrements from 0000, the Counter A
Underflow (IFR4) IS set to logic 1. If the Counter A Interrupt
Enable Bit (IER4) is also set, an IRQ Interrupt request Will be
generated. The Counter A Underflow bit in the Interrupt Flag
Register can be examined in the IRQ interrupt routine to
determine that the IRQ was generated by the Counter A
Underflow.

I
Interval Timer Timing Diagram
3-168

R6500/11·/12·115·/16

One-Chip Microcomputers

While the timer is operating in the Interval Timer Mode, PA4
operates as a PA I/O bit.

The Counter A underflow flag will be set only when the count
in the timer reaches zero. Upon reaching zero the timer will
be loaded with the latch value and continue counting down
as long as the CA pin is held low. After the counter is stopped
by a high level on CA, the count will hold as long as CA
remains high. Any further low levels on CA will again cause
the counter to count down from its present value. The state
of the CA line can be determined by testing the state of PA4.

A timing diagram of the Interval Timer Mode is shown in
Figure 6-1.

6.1.2 Pulse Generation Mode
In the Pulse Generation mode, the CA line operates as a
Counter Output. The line toggles from low to high or from
high to low whenever a Counter A Underflow occurs, or a
write is performed to address 001 A.

A timing diagram for the Pulse Width Measurement Mode is
shown in Figure 6.3.

The normal output waveform is a symmetncal square-wave.
The CA output is initialized high when entering the mode and
transitions low when writing to 001 A.
Asymmetric waveforms can be generated if the value of the
latch is changed after each counter underflow.
A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one
occurrence of the output toggle condition.

Figure 6·3.

Pulse Width Measurement

6.1.3 Event Counter Mode
In this mode the CA is used as an Event Input line, and the
Counter will decrement with each rising edge detected on
this line. The maximum rate at which this edge can be
detected is one-half the ~2 clock rate.

6.1.5 Serial I/O Data Rate Generation
Counter A also provides clock timing for the Serial I/O which
establishes the data rate for the Senal I/O port. When the
Serial I/O is enabled, Counter A is forced to operate at the
internal clock rate. Counter A is not required for the RCVR
SIR mode. The Counter I/O (PA4) may also be required to
support the Serial I/O (see Table 4-2).

The Counter can count up to 65,535 occurrences before
underflowing. As in the other modes, the Counter A Underflow bit (IER4) is set to logic 1 if the underflow occurs.
Figure 6.2 is a timing diagram of the Event Counter Mode.

Table 6-1 identifies the values to be loaded in Counter A for
selecting standard data rates with a ~2 clock rate of 1 MHz
and 2 MHz. Although Table 6-1 identifies only the more
common data rates, any data rate from 1 to 62.5K ~ps can
be selected by using the formula:

N

=

_~~2-,--_

-1

16 x bps

where

N
Figure 6-2.

~2

Event Counter Mode

bps

6.1.4 Pulse Width Measurement Mode

deCimal value to be loaded into Counter A using
Its hexadeCimal eqUivalent.
the clock frequency (1 MHz or 2 MHz)
the desired data rate.

NOTE

This mode allows the accurate measurement of a low pulse
durahon on the CA line. The Counter decrements by one
count at the ~2 clock rate as long as the CA line IS held in
the low state. The Counter is stopped when CA is in the high
state.

In Table 6-1 you Will notice that the standard data rate
and the actual data rate may be slightly different.
Transmitter and receiver errors of 1.5% or less are
acceptable A reVised clock rate IS included in Table
6-1 for those baud rates which fall outside this limit.

3-169

One-Chip Microcomputers

R6500/11-/12 -/15 -/16

6.2.1 .Retriggerable Interval Timer Mode

Table 6-1. Counter A Values for Baud Rate Selection

Standard
Baud
Rate
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600

Hexadecimal
Value

Actuel
Baud
Rate
At

1 MHz 2 MHz

1 MHz

2 MHz 1 MHz 2 MHz

O4E1
0340
0237
01AO
OOCF
0067
0033
0019
0010

50.00
75.03
110.04
149.88
300.48
600.96
1201 .92
2403.85
3676.47
4807.69
6944.44
8928.57

50.00
74.99
110·114
150.06
299.76
800.96
1201.92
2403.85
3676.47
4807.69
7352.94
9615.38

OOOC
0008
0006

09C3
0682
046F
0340
01AO
OOCF
0067
0033
0021
0019
0010

OOOC

When operating in the Retriggerable Interval Timer mode,
Counter B is initialized to the latch value by writing to address
001 E, by a Counter B underflow, or whenever a positive edge
occurs on the CB pin (PA5). The Counter B interrupt flag will
be set if the counter underflows before a positive edge occurs
on the CB line. Figure 6-4 illustrates the operation.

Clock Rate
Needed
To Get
Standard
Baud Rate
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
0.9792
1.0000
1.0368
1.0752

2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
1.9584
2.0000
1.9584
2.0000

LATCH VALUE

oOOO----------------~--------~---------1

RESET BY
COUNTER B
FLAG

6.2 COUNTER B

Figure 6-4.

Counter B consists of a 16-bit counter and two 16-bit latches
organized as follows: Lower Counter B (LCB) , Upper Counter
B (UCB), Lower Latch B (LLB), Upper Latch B (ULB), Lower
Latch C (LLC), and Upper Latch C (ULC). Latch C is used
only in the asymmetrical pulse generation mode. The counter
contains the count of either ~2 clock pulses or external
events depending on the counter mode selected. The contents of Counter B may be read any time by executing a read
at location 001 D for the Upper Counter B and at location
001 E or 001 C for the Lower Counter B. A read at location
001 C also clears the Counter B Underflow Flag.

_ ________~r__I~SOFnNARE

!

!

Counter B Retrlggerable Interval Timer Mode

6.2.2 Asymmetrical Pulse Generation Mode
Counter B has a special Asymmetrical Pulse Generation
Mode whereby a pulse train with programmable pulse width
and period can be generated without the processor intervention once the latch values are initialized.
In this mode, the 16-bit Latch B is initialized with a value
which corresponds to the duration between pulses (referred
to as D in the following descriptions). The 16-bit Latch C is
initialized with a value which corresponds to the desired
pulse width (referred to as P in the following descriptions).
The initialization sequence for Latch Band C and the starting
of a counting sequence are as follows:

Latch B contains the counter initialization value, and can be
loaded at any time by executing a write to the Upper Latch
B at location 001D and the Lower Latch B at location 001C.
In each case, the contents of the aocumulator are copied into
the applicable latch register.

1. The lower 8 bits of P are loaded into LLB by writing to
address 001 C, and the upper 8 bits of P are loaded
into ULB and the full 16 bits are transferred to Latch
C by writing to address location 0010. At this point
both Latch B and Latch C contain the value of P.

Counter B can be initialized at any time by writing to address:
001E. The contents of the accumulator is copied into the
Upper Latch B before the value in the 16-bit Latch B is transferred to Counter B. Counter B will also be set to the latch
value and the Counter B Underflow Flag bit (IFR5) will be set
to a "1" whenever Counter B underflows by decrementing
from 0000.

2. The lower 8 bits of D are loaded into LLB by writing to
address 001C, and the upper 8 bits of D are loaded
into ULB by writing to address location 00IE. Writing
to address location.001E also causes the contents of
the 16-bit Latch B to be downloaded into the Counter
B and causes the CB output to go low as shown in
Figure 6-5.

IFR 5 may be cleared by reading the Lower Counter B at
location 001C, by writing to address location 00IE, or by
RES.

3. When the Counter B underflow occurs the contents of
the Latch C is loaded into the Counter B, and the CB
output toggles to a high level and stays high until
another underflow oocurs. Latch B is ·then down-loaded
and the CB output toggles to a low level repeating the
whole process.

Counter B operates in the same manner as Counter A in the
Interval Timer and Event Counter modes. The Pulse Width
Measurement Mode is replaced by the Retriggerable Interval
Timer mode and the Pulse Generation mode is replaced by
the Asymmetrical Pulse Generation Mode.

3-170

One-Chip Microcomputers

R6500/11-/12-/15 -/16

SECTION 7
POWER ON/INITIALIZATION CONSIDERATIONS

7.1 POWER-ON TIMING

7.3 RESET (RES) CONDITIONING

After applications of Vcc and V RR power to the device, RES
must be held low for at least eight 02 clock cycles after Vcc
reaches operating range and the interal oscillator has stabilized. This stabilization time is dependent upon the input Vcc
voltage and performance of the internal oscillator. The clock
can be monitored at 02 (pin 3). Figure 7-1 illustrates the
power turn-on waveforms. Clock stabilization time is typically

When RES is driven from low to high the device is put in a
reset state causing the registers and 1/0 ports to be configured as shown in Table 7-1.

Table 7-1.

RES Initialization of 1/0 Ports and Registers
7

6

5

4

3

2

-

-

-

-

0
0
0
0
1

0
0
0
0
I)

0
0
0
0
0

0
0
0
0
0

1
0
0
0
0
0

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1

0

-

-

0
0
0
0
0

0
0
0
0
0

1
1
1
1

1
1
1
1

Reglaters

20 ms.

Processor Status
Mode Control (MeR)
0
In!. Enable (IER)
0
Int Flag (IFR)
0
Ser. Com. Control (SCCR) 0
Ser. Com. Status (SCSR)
0

,0-------

+5______
vcco~

'.~~~~.~ ~~N~ d n nC~~CnKn~TABILIZATION TIME

XTLO~ u u u u U u Lru1SU1SUl.SlSl

.2

Ports
PA
PB
PC
PO

r.;CLOCKSj

RES.________~C~y~C~
Figure 7-1.

Power Turn-on Timing Detail

Latch
Latch
Latch
Latch

1
1
1
1

All RAM and other CPU registers will initialize In a random,
non-repeatable data pattern.

7.2 POWER-ON RESET

7.4 INITIALIZATION

The occurrence of RES going from low to high will cause the
device to set the Interrupt Mask Bit - bit 2 of the Processor
Status Register - and initiate a reset vector fetch at address
FFFC and FFFD to begin user program execution. All of the
1/0 ports (PA, PB, PC, PD) will be forced to the high (logic 1)
state. All bits of the Control Register will be cleared to logic
o causing the Interval Timers counter mode (mode 00) to be
selected and causing all interrupt enabled bits to be reset.

Any initialization process for the device should include a
RES, as indicated in the preceding paragraphs. After stabilization of the internal clock (if a power on situation) an initialization subroutine should be executed to perform (as a minimum)
the following functions:

CB
OUTPUT

A tYPical Initialization subroutine could be as follows:

2 3

The Stack POinter should be set
Clear or Set Decimal Mode
Set or Clear Carry Flag
Set up Mode Controls as reqUired
5. Clear Interrupts

1.
2.
3.
4.

4

I-D-Ipl-

LDX
TXS
CLD
SEC

1&3. Counter B _ _ Latch B (D)
2&4.

Counter B - - Latch C (P)

Figure 6-5.

CLI

Counter B Pulse Generation

3-171

Load stack pOinter starting address Into X
Register
Transfer X Register value to Stack Pointer
Clear DeCimal Mode
Set Carry Flag
Set-up Mode Control and
speci al fu nction
registers as reqUired
Clear Interrupts

One-Chip Microcomputers

R6S00/11·112·/1S·/16

APPENDIX. A
ENHANCED R6502 INSTRUCTION SET
This appendix contains a summary of the R6502 instruction
set. For detailed information, consult the R6502 Microcomputer
System Programming Manual, Order No. 202. The four instructions notated with a ' are added instructions to enhance the
standard 6502 instruction set.

A.1 INSTRUCTION SET IN ALPHABETIC
SEQUENCE
ADC
AND
ASL
'BBR
'BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS

Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits In Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC
CLD
CLI
CLV
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

EaR

"Exclusive·Or' Memory with
Accumulator

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Index Y by One

JMP
JSR

Jump to New Location
Jump to New Location Saving Return
Address

LDA
LDX
LDY
LSR

Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or
Accumulator)

Nap

No Operation

ORA

"OR" Memory with Accumulator

PHA
PHP
PLA
PLP

Push Accu,mulator on Stack
Push Processor Status 011 Stack
Pull Accumulator from Stack
Pull Processor Status from Stack

*RMB
ROL

Reset Memory Bit
Rotate One Bit Left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine

ROR
RTI
RTS
SBC
SEC
SED
SEI
'SMB
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA

3-172

Subtract Memory from Accumulator with
Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer Stack Pointer tv Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator

::u
0')

A.2 INSTRUCTION SET SUMMARY TABLE

en
o

R6500111 OR R6500115 INSTRUCTION SET

PROCESSOR STATUS
CODES

INSTRUCTIONS

76543210
MNEMONIC
ADC

AND
ASl

(4){1)
(1)

c-- c:z=:=]] --A

(1)

M l-M
X I-X

49121214D
EE

451 3 12
E6

4C
20

3
6

A222AE
A
TITD
AO 2 2 AC
4E

4
4
6

~u.:~ S~lb)
(1)
(1)

No Operation
AVM-A (1)
A-Ms S 1-8
P-Ms S T-8
S 1-5 M5--->A
S 1-5 Ms-P
O-Mh (5)

ROl

~

O-~-C

09

1

41! 6

I 21 51 I 5 I 2 1 ~~

I: I~ I~~ I~ I; I

59

I4 I3

6C I 5 13

3
3
3

All 61 2

A6
A4
46

liAS

4A 1 2 11

EA 12 11 1

01

I Bl

1 5 1 2 1 B514121 BD 14131
8442BC4
56625E7

I 1I I I I
6

2

11

5

2

15

4

2

10

~~

I! I;

o .
N •

4131,914 13

OB
N •••••
(Restored)

~: I: I~
071 17

2E
6E

6
6

3
3

5

N •
N •

~~I~I~I~~

26

66

T
2 A
6A
40
6
.!..

OPERATION
A· M C--A
A M~A

~
.....

·1

1

(5)

,.

B71971A71871c71071E71F7

BD
BE
BC

4

B5
B6
B4

NOTES
Add 1 to N If page boundary IS crossed
Add 1 to N If branch occurs to same page
Add 2 to N If branch occurs 10 different page
Carry nol = Borrow
If In decimal mode Z flag IS Invahd
accumulator must be checked on zero result
5 Effects a·bli data field of the specified zero page address

3
3
3

2

611 61 21 91

I 6 I 2 I 951 4 I 2 I 90 I 51 3 I ( ,I 5 1 3

BA 12
9A 2
96 211

N •••••

•

~

CD

o::r•

-6.

96 I 4 12

941 41 2

LEGEND
X
Index X
Y
Index Y
A
Accumulator
M
Memory per effective address
Ms
Memory per slack pOlnler
Mb
Selecter zero page memory bll
M7
Memory BII 7

o

M&

V

#

C:;"

z

Memory 81t 6
Add
Subtract
= And
= Or
= Exclusive Or
Number of cycles
= Number of Bytes

=

~

1\

s::

an
o
3

."
C

CD
iii

One-Chip Microcomputers

R6500/11-/12-/15 -/16
A.3 INSTRUCTION CODE MATRIX

o
-op Code
-Addressing Mode
-Instruction Bytes; Machine Cycles

BRK
o

LSD 0

!1l

::;;

o

2

4

6

ORA
ZP
2 3

ASL
ZP
2 5

RMBO
ZP
2 5

PHP
Implied
1 3

ORA
IMM
2 2

BPL
ORA
Relative (IND), Y
2 2"
2 5'

ORA
ZP, X
2 4

ASL
ZP, X
2 6

RMB1
ZP
2 5

CLC
Implied
1 2

ORA
ABS,Y
3 4'

AND
ZP
2 3

ROL
ZP
2 5

RMB2
ZP
2 5

PLP
Implied
1 4

AND
IMM
2 2

BMI
AND
Relative (IND, Y)
2 2"
2 5'

AND
ZP, X
2 4

ROL
ZP, X
2 6

RMB3
ZP
2 5

SEC
Implied
1 2

AND
ABS, Y
3 4'

RTI
EOR
Implied (IND, X)
1 6
2 6

EOR
ZP
2 3

LSR
ZP
2 5

RMB4
ZP
2 5

PHA
Implied
1 3

EOR
IMM
2 2

BVC
EOR
Relative (IND), Y
2 2"
2 5'

EOR
Zp, X
2 4

LSR
Zp, X
2 6

RMB5
ZP
2 5

CLI
Implied
1 2

EOR
ABS, Y
3 4'

RTS
ADC
Implied (IND, X)
1 6
2 6

ADC
ZP
2 3

ROR
ZP
2 5

RMB6
ZP
2 5

PLA
Implied
1 4

ADC
IMM
2 2

BVS
ADC
Relative (IND, Y)
2 2"
2 5'

ADC
Zp, X
2 4

ROR
Zp, X
2 6

RMB7
ZP
2 5

SEI
Implied
1 2

ADC
ABS,Y
3 4'

JSR
AND
Absolute (IND, X)
3 6
2 6

BCC

BIT
ZP
2 ,3

2
A

B

C

2"

LDY
IMM
2 2

2 2
D

E

F

3

JMP
ABS
3 3

LSR
Accum
1 2

JMP
Indirect
3 5

ROR
Accum
1 2

DEY
Implied
1 2

STA

STY
Zp, X
2 4

STA
ZP, X
2 4

STX
ZP, Y
2 4

5MB1
ZP
2 5

TYA
Implied
1 2

STA
ABS, Y
3 5

TXS
Implied
1 2

LDY
ZP
2 3

LDA
ZP
2 3

LDX
ZP
2 3

5MB2
ZP
2 5

TAY
Implied
1 2

LDA
IMM
2 2

TAX
Implied
1 2

LOY
ZP, X
2 4

LDA
ZP, X
2 4

LOX
ZP, Y
2 4

5MB3
ZP
2 5

CLV
Implied
1 2

LOA
ABS, Y
3 4'

TSX
Implied
1 2

CPY
ZP

CMP
ZP

2 3

2 3

DEC
ZP
2 5

5MB4
ZP
2 5

INY
Implied
1 2

CMP
IMM
2 2

DEX
Implied
1 2

CMP
ZP, X
2 4

DEC
ZP, X
2 6

5MB5
ZP
2 5

CLD
Implied
1 2

CMP
ABS,Y
3 4'

SBC
ZP
2 3

INC
ZP
2 5

5MB6
ZP
2 5

INX
Implied
1 2

SBC
IMM
2 2

SBC
ZP, X
2 4

INC
ZP, X
2 6

5MB7
ZP
2 5

SED
Implied
1 2

SBC
ABS,Y
3 4'

5

6

7

8

LOX
IMM
2 2

CMP
(IND, X)
2 6

SBC
(IND, X)
2 6

CPX
ZP
2 3

BEQ
SBC
Relative (IND), Y
2 2"
2 5'

3

4

AND
ABS
3 4

ROL
ABS
6

3

EOR
ABS
3 4

LSR
ABS
3 6

LSR
EOR
ABS, X ABS,X
3 4'
3 7

5MBO
ZP
2 5

LDA
(IND, X)
2 6

F
BBRO
ZP
3 5"

AND
ROL
ABS, X ABS,X
3 7
3 4'

STX
ZP
2 3

BNE
CMP
Relative (IND), Y
2 2"
2 5'
CPX
IMM
2 2

BIT
ABS
4

ROL
Accum
1 2

STA
ZP
2 3

2 6

E
ASL
ABS
3 6

ORA
ASL
ABS, X ABS,X
3 7
3 4'

STY
ZP
2 3

BCS
LDA
Relative (IND), Y
2 2"
2 5'
CPY
IMM

ASL
Accum
1 2

STA
(IND, X)
2 6
Relative (IND, Y)

o
ORA
ABS
3 4

C

B

A

8

4

BRK
ORA
Implied (IND, X)
1 7
2 6

Implied
1 7

STY
ABS
3 4

TXA
Implied
1 2

CPX
ABS
,3 4

NOP
Implied
1 2

A

B

C

BBR3
ZP
3 5"
BBR4
ZP
3 5"
BBR5
ZP
3 5"
BBR6
ZP
5"

ROR
ABS
3 6

ADC
ABS, X
3 4'

ROR
ABS,X
3 7

BBR7
ZP
3 5"

STA
ABS
3 4

STX
ABS
3 4

BBSO
ZP
3 5"

LOA
ABS
4

3

LDA
LOY
ABS, X ABS, X
3 4'
3 4'
CPY
ABS
3 4

BBR2
ZP
5"

3

ADC
ABS
3 4

3

BBSt
ZP
3 5"

STA
ABS, X
3 5
LDY
ABS
3 4

BSR1
ZP
3 5"

LOX
ABS
3 4

3

BBS2
ZP
5"

A

LDX
ABS,Y
3 4'

3

BBS3
ZP
5"

B

CMP
ABS
3 4

DEC
ABS
3 6

BBS4
ZP
3 5"

C

CMf'
ABS, X
3 4'

DEC
ABS, X
3 7

BBS5
ZP
3 5"

D

BBS6
ZP
5"

E

SBC
ABS
3 4

INC
ABS

3

6

3

SBC
ABS, X
3 4'

INC
ABS, X
3 7

o

E

I

BBS7
ZP
5"

3

F

•Add 1 to N If page boundary IS crossed
.. Add 1 to N If branch occurs to same page,
add 2 to N If branch occurs to different page,

3·174

One-Chip Microcomputers

R6500/11-/12-/15-116

APPENDIX B
KEY REGISTER SUMMARY
0

7

J

I

0
7

0

I7
I7

15
PC"

ACCUMULATOR

I

INDEX REGISTER Y

I

INDEX REGISTER X

INlvllBlol'lzlcJ

~

0

I PROGRAM COUNTER

PCL

0
Sp

7

PC

I STACK POINTER

0

INI vi I BID I' I z I C I PROCESSOR STATUS REG

P

I

CPU Registers

CARRY (C)

CD

1 :::::Carry Set
o -=Carry Clear
ZERO (Z)

CD

=

1 Zero Resull
0:::: Non-Zero Result
INTERRUPT DISABLE (I)

®

1 - IRa Interrupt Disabled

o - IRa Interrupt Enabled
OECIMAL MODE (0)

CD

1 --:: DeCimal Mode
o Binary Mode

=

BREAK COMMAND (B)
1

CD

= Break Command

0= Non Break Command
OVERFLOW (O)G>

MCR

t -= Overflow Set
0= Overflow Clear

Addr 0014

NEGATIVE (N)

I
Counter B

NOTES
t Not Initialized by RES
Set to LogiC 1 by"'REs

Mode Select

00 Interval Timer
0 - 1 Pulse Generation
1 - 0 Event Counter
1 - 1 Pulse Width Meas
0 - 0 Interval Timer

I

Bus Mode Select

.

II

o 1_
1_

1 AsymmetriC Pulse Generation
0 Event Counter
1 Retn9gerable Interval Timer

CD

1 .:::;:: Negative Vatue

,®

0= Postlve Value

Processor Status Register

IFR

Addr 0011

IER

Addr 0012

Port B latch
(1 - Enable)

Port 0 Tn-State
(0

Tn-State High Impedance Mode)

O-XNormal
1 - o Abbr Bus
1 _ 1 Muxd Bus

Mode Control Register

Edge Detect
PA2 Negative
Edge Detect
PA3 Negative
Edge Detect

Counter A
Underflow Flag
Counter B
Underflow Flag
RCVR
Flag
XMTR
Flag

Interrupt Enable and Flag Registers
Addr 0015

SCCR

Addr 0016

SCSR

I

I

1

l

1 "" 7 Bits/Char
0-- 6 Bits/Char
1 ...... 5 Bits/Char

l

Reg Fuji
RCVR Over·Run

Panty Error

Frame Error

0 - 0 XMTR & RCVR ASYN Mode
0 - 1 XMTR ASYN, RCVR SIR
1 - x XMTR SIR, RCVR ASYN

l

Wake-Up

End of TransmisSion

o RCVR Disable
1 RCVR Enable

XMTR Data Reg Empty

o XMTR Disable

XMTR Under·Run

1 XMTR Enable

Serial Communications Control Register

l

3-175

Serial Communications Status Register

R6S0Q/11-/12-/1S-/16

One-Chip Microcomputers

APPENDIX C
ADDRESS ASSIGNMENTS/MEMORY
MAPS/PIN FUNCTIONS
C.1 I/O AND INTERNAL REGISTER ADDRESSES
ADDRESS
(HEX)

,,:.

READ

WRITE

--

--

001F
1E
10
1C

Lower Counter B
Upper Counter B
Lower Counter B, CLR Flag

1B
1A
19
18

Lower Counter A
Upper Counter A
Lower Counter A, CLR Flag

Upper Latch A, Cntr A<-Latch A, CLR Flag
Upper Latch A
Lower Latch A

17
16
15
14

Senal Receiver Data Register
Senal Comm. Status Register
Senal Comm. Control Register
Mode Control Register

Senal
Senal
Senal
Mode

13
12
11
0010
OF
DE
DO
DC
DB
OA
09
08
07
06
05
04
03
02
01
0000

Upper Latch B, Cntr B<-Latch B, CLR Flag
Upper Latch B, Latch C<-latch B
Lower Latch B

--

--

--

Transmitter Data Register
Comm Status Reg Bits 4 & 5 only
Comm. Control Register
Control Register

--

Interrupt Enable Register
Interrupt Flag Register
Read FF

Interrupt Enable Register

--

Clear Int Flag (Bits 0-3 only, Wnte D's only)

----------

-----

----

--

--

Port G*
Port F*
Port E*

PortG*
Port F*
Port E'

Port 0
PortC
Port B
PortA

Port D
PortC
Port B
PortA

NOTE' *R6500/120 or 1160 only.

3-176

One-Chip Microcomputers

R6S00/11-112-/1S-116
C.2 ABBREVIATED MODE
MEMORY MAP
FFFE
FFFC
FFFA

C.3 MULTIPLEXED MODE
MEMORY MAP
FFFE

IRQ vector
RES Vector
NMI Vector

IRQ Vector
RES Vector
NMI Vector

FFFC
FFFA

ROM (3K)

ROM (3K)
F400
FOOO

F400
ROM (4K)

ROM(4K)

FOOO

Reserved

001F

Reserved

00IF
I

I

I
I
,-3FFF

",e

I

Peripheral DeVices
(64)
Abbr Addr Mode

r:1...1

w~

Internal Ram (192)
Reserved

001F
0000

110 & RegIsters

-r

r",e
:1...1

I

I
I

...L-OOFF
0040

I

Internal
Registers

I

I

I

I

I

I

Reserved

1/0 Ports E, F, G
(A6500112Q and 160)

110 Ports A, B, C, 0

3FFF

w~

0010
OOOF

t
--OOFF

0007
0006
0004
0003

I

I

External Memory
(16384 - 256)
Mux'd Addr Mode

I
I

I

Reserved

I

Internal Ram (192)

I

I/O Porta E, F, G

I

0040
Reserved

(R65001120 and 160)

I

00IF

0000

Internal
Registers

I

0000

110 Ports A, B, C, 0

110 & RegIsters

I/O PORT
FUNCTION

ABBREVIATED PORT
FUNCTION

MULTIPLEXED PORT
FUNCTION

4
5
6
7

PCO
PCl
PC2
PC3

AO
Al
A2
A3

AO
Al
A2
A3

8
9
10
11

PC4
pe5
PC6
PC7

A12
R/W
A13
EMS

A12
R/W
A13

EMS

19
18
16

POO
POl
P02
P03

00
OJ
02
03

A4/00
A5/01
A6/02
A7/03

15
14
13
12

P04
P05
P06
P07

04
05
06
07

A8/04
A9/05
Al0/06
All/07

17

3-1n

0004
0003
0000

C.4 MULTIPLE FUNCTION PIN ASSIGNMENTS-PORT C AND PORT D
PIN
NUMBER

0010
OOOF
0007
0006

9

One-Chip Microcomputers

R6S00111-/12-I1S-/16

APPENDIX D
ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS*
Parameter

Symbol

Value

Unit

Vee & VRR

-0.3 to + 7.0

Vdc

Input Voltage

VIN

-0.3 to + 7.0

Vdc

Operating Temperature
Commercial

TA

TL to TH
Oto+70

°C

T STO

-55 to +150

°C

Supply Voltage

Storage Temperature

'NOTE: Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

DC CHARACTERISTICS
Ct'ce = 5.0V ±5%, VRR = Vee; Vss = OV; TA = 0° to 70°, unless otherwise specified)
Parametar
RAM Standby Voltage (Retention Mode)

Symbol
V RR

Min

-

RAM Standby Current (Retention Mode)

IRR

Input High Voltage
All Except XTLI and 02 in Slave Option
XTLI and 02 in Slave Option

V IH

Input Low Voltage

V IL

-0.3

In~eakage

liN

-

IlL

-

Current

Input Low Current
PA, PB, PC, PO, PF3, PG3

Max
Vee

-

4

Unit

Test Conditions

V
mA

TA = 25°C

V
+2.0
+4.0

RES, NMI

Typl

3.0

-

-

Vee
Vee

-

+0.8

V

±10.0

,.A

V IN = 0 to 5.0V

-1.6

mA

VIL = O.4V

Vee

V

ILOAD = -100,.A

+0.4

V

ILOAD = 1.6 rnA

-1.0

Output High Voltage (Except XTLO)

VOH

+2.4

Output Low Voltage

VOL

-

-

I/O Port Pull-Up Resistance
PAO-PA7, PBO-PB7, PCO-PC7,
PFO-PF73, PGO-PG73

RL

3.0

6.0

11.5

Kohm

-

-

±10

,.A

-

50
10

-

Output Leakage Current (Three-State 011)

lOUT

Input Capacitance
XTLI, XTLO
PA, PB, PC, PO, PF3, PG3

C IN

Output Capacitance (Three-State 011)

COUT

-

Power DiSSipation (Outputs High)

PD

-

Notes:
1. Typical values measured at TA = 25°C and Vee = 5.0V.
2. Negative sign indicates outward current Ilow, positive indicates inward Ilow.
3. R65001120 and R6500/l60 only.

3-178

pF

TA = 25°C
VIN = OV
1= 1.0 MHz

10

pF

TA = 25°C
V IN = OV
1= 1.0 MHz

1200

mW

TA = 25°C

One-Chip Microcomputers

R6S00111-/12-/1S-/16

APPENDIX E
TIMING REQUIREMENTS AND CHARACTERISTICS

E.1 GENERAL NOTES
2. A valid Vee - RES sequence
operation is achieved.

E.2 CLOCK TIMING
IS

SYMBOL

required before proper

Cycle Time

Tcyc

3. All timing reference levels are O.BV and 2.0V, unless
otherwise specified.

T pWX1

4. All time Units are nanoseconds, unless otherwise specified.

T pW02

5. All capacitive loading
below:

IS

PARAMETER

XTLI Input Clock
Pulse Width
. XTLO ~ VSS
Output Clock Pulse
Width at Minimum

50pf maximum
50pf maximum
130pf maximum
130pf maximum

,(XTLO

500
± 25

TpWX1

MAX

10 JLS

500

10 JLS

-

2 MHz

250
± 10

T pWX1
± 25

T pWX1

-

T pWX1

± 20

Output Clock Rise,
Fall Time

-

25

-

15

T 1R •

Input Clock Rise,
Fall Time

-

10

-

10

TIF

Tcyc

"

-'

1.SV
~

MIN

T R , TF

TIR
XTLI

1000

MHz
MAX

Tcyc

130pf maximum, except as noted

PA,PB
PC (I/O Modes Only)
PC (ABB and Mux Mode)
PC6, PC7 (Full Address Mode)

1

MIN

vss)

TpWX1

-

T pW02

112
__ T
R

3-179

.

One-Chip Microcomputers
E.3 ABBREVIATED MODE TIMING-PC ANI:) PO
(MCR 5

= 1,MCR6 = 0, MCR7 = 1)
1 MHz

2 MHz

.---

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

- r------

T PeAS

(PC5) R/w Setup Time

-

225

-

T peAS

(PCO-PC4, PC6) Address Setup Time

-

200

-

(PO) Data Setup Time

50

35

(PO) Data Read Hold Time

10

T pBHW

(PO) Data Write Hold Time

30

-

T PSDO

(PO) Data Output Delay

-

1?5

T PCHA

(PCO-PC4, PC6) Address Hold Time

30

-

30

-

T pCHR

(PC5) R/W Hold Time

30

30

-

T pCHV

10

10

-

TPCVO(1)

(PC?) EMS t:lold TIme
-(PC?) Address to EMS Delay Time

-

30

220

30

130

T pcvp

(PC?) EMS Stabilization Time

30

30

-

T PBSU
1-T PBHR

r-------" -

"r-10

-

140
140

-

1--

-

30

-

-

130

NOTE 1 Values assume PCO-PC4, PCS and PC? have the same capacitive load.

E.3.1 Abbreviated Mode Timing Diagram
WRITE

READ

r-------------~I

_TPCHR

RIW
1"--'---"", TPCRS

_TPCHV

TPCVD
TPCVP

TPCHA

TPBDD
TPBSU
PDD-PD7

TPBHR

3-180

TPBHW

One-Chip Microcomputers

R6S00/11-112-/1S-/16
E.4 MULTIPLEXED MODE TIMING-PC AND PO
(MCR 5

= 1,

MCR 6

= 1,

MCR 7

= 1)
1 MHz

SYMBOL

2 MHz

PARAMETER
MIN

MAX

MIN

MAX

T pCAS

(PC5) R/W Selup Time

-

225

-

140

T pCAS

(PCO-PC4, PC6) Address Setup Time

-

200

-

140

T pBAS

(PO) Address Setup Time

-

220

-

120

T pBSU

(PO) Data Setup Time

50

-

35

T pBHA

(PO) Data Read Hold Time

10

-

10

-

T pBHW

(PO) Data Write Hold Time

30

-

30

-

T pBOD

(PO) Data Output Delay

-

1?5

-

140

TpCHA

(PCO-PC4, PC6) Address Hold Time

30

-

30

-

T pBHA

(PO) Address Hold Time

40

100

40

80

T pCHA

(PC5) RIW Hold Time

30

30

-

-

T PCHV

(PC?) EMS Hold Time

10

-

10

T pevo(1)

(PC?) Address to EMS Delay Time

30

200

30

150

T pCVP

(PC?) EMS Stabilization Time

30

-

30

-

NOTE 1. Values assume PDQ-POl and PC7 have the same capactlve load.

E.4.1 Multiplex Mode Timing Diagram
READ

r-------------__

WRITE

I r-----------------..

4>2

_TPCHR
R/W
(PC5)

1_------_.1 TPCRS
_TPCHV

EMS
(PC7)
TPCVP

TPCHA
PCO-PC4,
PC6

PDOPD7
TPBAS

_ _ TPCVD

TPBHR

3-181

TPBHW

One-Chip Microcomputers

R6S00/11·/12·/1S·/16
E.S I/O, EDGE DETECT, COUNTERS, AND SERIAL I/O TIMING
2 MHz

1 MHz
SYMBOL

PARAMETER
MIN

MAX

MIN

MAX

Internal Write to Peripheral Data Valid

TpOW(11
TcMos(1)

Tpoow

PA, PB, PC, PE, PF, PG, TTL
PA,PB, PC, PE, PF, PG,CMOS
PD

-

-

-

500
1000
175

-

-

500
1000
150

Peripheral Data Setup Time
Tposu
Tposu

PA, PB, PC, PF, PG
PD

200
50

-

200
50

-

Peripheral Data Hold Time

TpHA
T PHR

TEPW

PA, PB, PC, PF, PG
PD
PAO-PA3 Edge Detect Pulse Width

Tcye

-

Tcye

-

Tcye

-

Tcve

-

75
10

75
10

-

Counters A and B

Tcpw
Tco(ll

PA4, PA5 Input Pulse Width
PA4, PA5 Output Delay

-

500

-

500

Port B Latch Mode

TpBLW
T PLSU

TpBLH

PAD Strobe Pulse Width
PB Data Setup Time
PB Data Hold Time

Tcve
175
30

-

Tcve

150
30

-

-

Serial 110
T pDW{1}
TCMOS(1)

Tcpw
T pDW (1)
TCMOS(1)

PA6
PA6
PA4
PA4
PA4

XMTRTTL
XMTR CMOS
RCVR SIR Clock Width
4 Tcve
XMTR Clock-SIR Mode (TTL)
XMTR Clock-SIR Mode (CMOS) -

-

500
1000

500
1000

-

4 Tcyc

-

NOTE 1: MaXimum Load CapaCItance: 50pF Passive Pull· Up ReqUIred

3·182

500
1000

500
1000

R6500/11-/12 -/15 -/16

One-Chip Microcomputers

E.S.1 I/O, Edge Detect, Counter, and Serial I/O Timing

EDGE DETECTS
(PAO-PA3)

~

1.SV\

/
PAO-PA7
PBO-PB7
PCO-PC7
PDO-PD7
PFO-PF7
PGO-PG7

•

TCYC

,I"
I'

TPDSU

•

I."

)!

.I

T~

I

)

x:

TEPW
CNTR
PA4, PAS

1.SV.!

\l.SV

1.SV]

..

TCPW
TCD
CNTR
(PA4, PAS)

•

TCPW
2.4V
O.4V

TpDDW

>t

PDO- PD7

-

1

PAO-PA7
PCO-PC7
PBO-PB7
PEO-PE7
PFO-PF7
PGO-PG7

TCMOS
TPDW

VDD-3D%

2.4V

I
I

O.4V

-----------\;r

PB
(LATCH MODE)

f

1.SV
PAD

1.SV

STROBE

-4- TPLSU __

j......I - - - - - - - - TPBLW --------c~~l

3-183

_

TpBLH

R65/11 EB .R65/11 EAB
R6500 Microcomputer System

'1'

R65/11EB AND R65/11EAB
BACKPACK EMULATORS

Rockwell
INTRODUCTION

FEATURES

The Rockwell R65/11 EB and R65/11 EAB Backpack Emulator
is the PROM prototyping version of the 8-bit, masked-ROM
R6500/11 one-chip microcomputer. Like the R6500/11, the
backpack device is totally upward/downward compatible with all
members of the R6500/11 family. It is designed to accept standard 5-volt, 24-pin EPROMs or ROMs directly, in a socket on
top of the Emulator. This packaging concept allows a standard
EPROM to be easily removed, re-programmed, then reinserted
as often as desired.

• PROM version of the R6500/11
• Completely pin compatible with R6500/11 single-chip microcomputers
• Profile approaches 40-pin DIP of R6500/11
• Accepts 5 volt, 24-pin Industry-standard EPROMs
-4K memories-2732, 2732A (4K bytes addressable)
• Use as prototYPlng tool or for low volume productIOn
• 4K bytes of memory capacity
• 192 x 8 static RAM
• Separate power pin for 32 bytes of RAM
• Software compatibility with the R6500 family
• 32 bi-directional TTL compatible I/O lines (4 ports)
• Two 16 bit programmable counter/latches with SIX modes
(interval timer, pulse generator, event counter, pulse width
measurement, asymmetrical pulse generator, and retriggerable interval timer)
• 10 interrupts (reset, non-maskable, four external edge sensitive, 2 counters, serial data received, serial data transmitted).
• Crystal or external time base
• Single +5V power supply

The backpack devices have the same pinouts as the maskedROM R6500/11 microcomputer. These 40 pins are functionally
and operationally identical to the pins on the R6500/11. The
R6500/11 Microcomputer Product Description (Rockwell Document No. 29651 N23, Order No. 2119) includes a description of
the interface signals and their functions. Whereas the maskedROM R6500/11 provides 3K bytes of read-only memory, the
R65/11 EB will address 4K bytes of external program rnemory.
This extra memory accommodates program patches, test programs or optional programs dUring breadboard and prototype
development states.

ORDERING INFORMATION
Backpack Emulator
Part
Number

Memory
Capacity

Compatible
Memories

Temperature
Range and Speed

R65/IIEB

4K x 8

2732

O°C to 70°C
IMHz

R65/IIEAB

4K x 8

2732A

O°C to 70°C
2 MHz

Support Products
Part
Number

Description

S65-101

SYSTEM 65 Microcomputer
Development System

M65-040
M65-131

PROM Programmer Module
I-MHz R6500/11 Personality Module
2-MHz R6500/11 Personality Module

M65-132
ROC-IOOI
ROC-IOI
ROC-I 02

Rockwell DeSign Center
I MHz R6500/11 P Personality Module (ROC)
2 MHz R6500/IIAP Personality Module (ROC)

Document No. 29001013

R65/11EB Backpack Emulator

3-184

Data Sheet Order No. 0113
February 1983

R65/11EB. R65/11EAB

Backpack Emulators

CONFIGURATIONS

PRODUCT SUPPORT

The Backpack Emulator is available in two different versions,
to accommodate 1 MHz and 2 MHz speeds. Both versions
provide 192 bytes of RAM and
as well as 24 signals to
support the external memory "backpack" socket.

The Backpack Emulator is just one of the products that Rockwell offers to facilitate system and program development
for the R6500/11.

va,

The SYSTEM 65 Microcomputer Development System with
R6500/11 Personality Module supports both hardware and
software development. Complete in-circuit user emulation
with the R6500/11 Personality Module allows total system
test and evaluation. With the optional PROM Programmer,
SYSTEM 65 can also be used to program EPROMs for the
development activity. When PROM programs have been finalized, the PROM device can be sent to Rockwell for masking
into the 3K ROM of the R6500/11.

The emulator will relocate the EPROM address space to
FXXX (see Memory Map). EPROM addresses FFA through
FFF must contain the interrupt vectors.

EXTERNAL FREQUENCY REFERENCE
The external frequency reference may be a crystal or a
clock-the RC option of the R6500/11 is not available in the
emulator device. The R65/11 EB and R65/11 EAB divide the
input clock by two regardless of the source.

In addition to support products, Rockwell offers regularly. scheduled designer courses at regional centers.

I/O PORT PULLUPS
The devices have internal I/O port pullup resistors on ports
A, B, & C. Port D has push-pull drivers.

XTLI
XTLO

VCC,VRR,VSS

vee,

VSS

PROM!
ROM

40 R6500/11
COMPATIBLE PINS

24 PROM/ROM
PINS

R6S/11 EB Interface Diagram

3-185

Backpack Emulators

R65/11EB. R65/11EAB
XTLO
XTLI

BACKPACK MEMORY SIGNAL
DESCRIPTION

Vss
VRR
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
NMI
Vee

P2

PCO
PCl
PC2
PC3
PC4
PCS
PC6
PC7
P07
P06
POS
P04
P03
P02
POl
POO
RES

Signal
Name

Pin No.

Description

DO-D7

9S-11S,
13S-17S

Data Bus Lines. All instruction and data
transfers take place on the data bus lines.
The buffers driving the data bus lines have
full three-state capability. Each data bus
pin is connected to an Input and an output
buffer, with the output buffer remaining in
the floating condition.

AO-A7
A8,A9
AID
All

lS-8S,
23S,24S
19S
21S

Address Bus Lines. The address bus lines
are buffered by push/pull type drivers that
can drive one standard TTL load.

CE

18S

BE

20S

Chip Enable. CE is active when the address
is 8000-FFFF. This line can drive one TTL
load.
Memory Enable Line. This signal prOVides
the output enable for the memory to place
information on the data bus lines. ThiS
signal is driven by an inverted R1W signal
from the CPU. It can drive 1 TTL load.

Vcc

24S

Vss

12S

Pin Configuration

Main Power Supply +5V. This pin is tied
directly to pin 21 (Vcel.
Signal and Power Ground (zero vo~s). This
pin is tied directly to pin 40 (Vss).

I/O AND INTERNAL REGISTER ADDRESSES
Address
(Hex)

Write

Read

--

--

001F
IE
lD
lC

Lower Counter B
Upper Counter 8
Lower Cbunter 8, CL'R Flag

18
lA
19
18

Lower Counter A
Upper Counter A
Lower Counter A, CLR Flag

Upper Latch A, Cntr A<-Latch A, CLR Flag
Upper Latch A
Lower Latch A

17
16
15
14

Serial
Serial
Serial
Mode

Serial
Serial
Serial
Mode

13
12
11
DOlO

--

--

Receiver Data Register
Comm. Status Register
Comm. Control Register
Control Register

Transmitter Data Register
Comm. Status Reg. Bits 4 & 5 only
Comm. Control Register
Control Register

--

--

Interrupt 'Enable Register
Interrupt Flag Register
Read FF

Interrupt Enable Register

--

Clear Int Flag (Bits 0-3 only, Write D's only)

--

--

04 thru OF
03
02
01
0000

Upper Latch B, Cntr B<-Latch 8, CLR Flag
Upper Latch 8, Latch C<-Latch 8
Lower Latch B

Port D
PortC
Port 8
PortA

Port D
PortC
Port B
PortA

3-186

.Backpack Emulators

R65/11EB. R65/11EAB
READ TIMING CHARACTERISTICS
1 MHz
Signal

Symbol

DE and CE setup time from CPU
Address setup time from CPU
Memory read access time
Data set up time
Data hold time-Read
Address hold time
DE and CE hold time
Cycle Time

TOES
TAOS
T ACC
Tosu
THR
T H.
T HOE
Tcyc

2 MHz

Min.

Max.

Min.

Max.

Unit

-

225
225
700

-

140
140
315

-

35
10
30
30
0.5

-

ns
ns
ns
ns
ns
ns
ns

10.0

f.Ls

-

50
10
30
30
1.0

10.0

-

READ TIMING WAVEFORMS
I------TCYC----.-j

ADDRESS FROM
CPU
DATAFROM-~--~---~---<~
~~----~

MEMORY

ABBREVIATED MODE
MEMORY MAP

MULTIPLEXED MODE
MEMORY MAP

FFFE

IRQ VECTOR

FFFE

FFFC

RES VECTOR

FFFC

RES VECTOR

FFFA

NMIVECTOR

FFFA

NMI VECTOR
ROM (3K)

ROM (3K)

F400
FOOO

IRQ VECTOR

F400

EXTENDED ROM (1 K)·

FOOO

EXTENDED ROM (1 K)*

001F

001F

RESERVED

T

.

T

REGISTERS

PERIPHERAL DEVICES
(64)

~

ABBR ADDR MODE

0010
OOOF

RESERVED
INTERNAL RAM (192)

110 PORTS E, F, G

0040

(R6500/12Q ONLY)

RESERVED
001F

0000

I/O & REGISTERS

INTERNAL
3FFF

..,.ud!

-

0007
0006

(163 ...i56)

~

-*-

0004
0003

1/0 PORTS A, B, C, 0

0000

*NOT AVAILABLE FOR MASKED ROM R65OO/11.

3-187

REGISTERS

EXTERNAL MEMORY

...

DOFF

I

RESERVED

INTERNAL
3FFF

~§

L

I

MUX'O ADDR MODE
RESERVED

OOFF
INTERNAL RAM (192)

I}O PORTS E, F, G

0040

(R6500/12O ONLY)

RESERVED
I

OOlF

0000

110 & REGISTERS

-

-

0010
OOOF
0007
0006
0004
0 003

I/O PORTS A, S, C, 0

0000

R65/11EB. R65/11EAB

Backpack Emulators

ELECTRICAL CHARACTERISTICS
(Vee = 5.0 ± 5%, Vss = 0, TI>. = 25°C)
Characteristic

Symbol

Input High Threshold Voltage
00-07

V ,HT

Input Low Threshold Voltage
00-07

V ,LT

Three-State (Off State) Input Current
(V = 0.4 to 2.4V, Vcc = 5.25V)
00-07

ITSI

Output High Voltage
(I LOAD = 100", Adc, Vee
00-07, AO-A11 , OE, CE

V OH

Output Low Voltage
(lLOAD = 1.6 mAdc, Vcc
00-07, AO-A11, OE, CE

Min

+ 2.0

-

-

-

Vss

Max

Typ

Vss

Unit
Vdc

+ 0.8

Vdc
",A

-

-

+ 2.4

-

= 4.75V)
Vss

± to

-

Vdc

VOL

= 4.75V)
-

-

-

Power Dissipation (less EPROM)

Po

Capacitance
(V,n = 0, TA = 25°C, f = 1 MHz)
00-07 (High Impedance State)
Input Capacitance

C

-

Coo

-

-

I/O Port Pull-up ReSistance

RL

3.0

6.0

Cout

)

1

Vss

+ 0.4

1.20

0.80

Vdc

W
pF

10
10
11.5

21

40DDDDDDDDDDDD

ii.c~cc,".

1--

20

1--------2020 MAXI-------_1

0185
MAX

·II~ ~~~3

1-'-~i'~--I

_ _ _ _ _ _ _ _ ~~o~-----~~-

40-Pin Backpack Package

3-188

0125
MIN

kohm

R6511Q •

R6500113

R6500 Microcomputer System

'1'

Rockwell

R6511Q and R6500/13
ONE·CHIP MICROPROCESSOR
and ONE·CHIP MICROCOMPUTER

SECTION 1
INTRODUCTION
1.1 FEATURES
• Enhanced 6502 CPU
-Four new bit manipulation instructions
• Set Memory Bit (SMB)
• Reset Memory Bit (RMB)
• Branch on Bit Set (BBS)
• Branch on Bit Reset (BBR)
-Decimal and binary arithmetiC modes
-13 addressing modes
- True indexing
• 256-byte mask-programmable ROM or no ROM"
• 192-byte static RAM
• 32 bidirectional, TTL-compatible I/O lines (four ports)
• One 8-blt port may be tn-stated under software control
• One 8-bit port may have latched inputs under software
control
• Two 16-blt programmable counter/timers, with latches
-Pulse width measurement
-Asymmetrical pulse generation
-Pulse generation
-Interval timer
-Event counter
-Retriggerable interval timer
• Senal port
-Full-duplex asynchronous operation mode
-Selectable 5- to 8-bit characters
-Wake-up feature
-SynChronous shift register mode
-Standard programmable bit rates programmable
up to 62.5K bHs/sec @ 1 MHz
• Ten interrupts
-Four edge-sensitive lines; two positive, two negative
-Reset
-Non-maskable
- Two counter underflows
-Serial data received
-Serial data transmitted
• Bus expandable to 64K bytes of external memory

• Flexible clock circuitry
-2-MHz or l-MHz internal operation
-Internal clock with external XTAL at two or four times
internal frequency
-External clock input divided by one, two or four
• 11-'s minimum InstructIOn executIOn time @ 2 MHz
• NMOS-3 Silicon gate, depletion load technology
• Single +5V power supply
• 12 mW stand-by power for 32 bytes of the 192-byte RAM
• 64-pln QUIP
NOTE

This document uses the term R6500/13 to descnbe
both parts. See section 1.3 for a deSCription of the options available when uSing the R6500/13 and the fixed
features of the R6511Q.

1.2 SUMMARY
The Rockwell R6500/13 is a complete, high-performance
8-bH NMOS-3 microcomputer on a single chip and is compatible with all members of the R6500 family.
The R6500/13 consists of an enhanced 6502 CPU, an internal clock OSCillator, an optional 256 bytes of Read-Only
Memory, 192 bytes of Random Access Memory (RAM) and
versatile Interface cirCUitry. The Interface circuitry Includes
two 16-bIt programmable timer/counters. 32 bidirectional input/output lines (Including four edge-sensitive lines and input
latching on one 8-blt port). a full-duplex senal I/O channel.
ten Interrupts and bus expand ability.
The Innovative architecture and the demonstrated high performance of the R6502 CPU. as well as instruction simplicity,
results in system cost-effectiveness and a wide range of
computational power. These features make the R6500/13 a
leading candidate for microcomputer applications.
The R6511 Q contains all the features of the R6500/13 except
it has no ROM and IS thus Intended as a high feature microprocessor With full 65K address bus.

*R6511Q has no ROM.

Document No. 29651 N36
3-189

Product Description Order No. 2133
Rev. 4, October 1984

R6511 Q Microprocessor and R6500/13 Microcomputer
1.3 CUSTOMER OPTIONS

To allow prototype circuit development, Rockwell offers a
PROM-compatible 64-pin extended microprocessor device.
This device, the R6511 Q, provides all R6500/11 Interface
lines, plus the address bus, data bus and OO!1trollines to interface with external memory. The R6511 Q also can be used
to emulate the R6500/13. With the addition of ellterrial cir.
cuits it can also emulate the R6500/12.
Rockwell supports development of the R6500/13
System 65 Microcomputer Development System
R6500/* Family of Personality Modules. Complete
emulation with the R6500/* Family of Personality
allows total system test and evaluation.

The R6500/13 microcomputer Is available with the following
customer specified mask options.
.
• . Option 1 Crystal or RC oscillator
•
•
•
•
•
•
•

with the
and the
in-circuit
Modules

This product description assumes that the reader is familiar
with the R6502 CPU hardware and programming capabilities. A detailed description of the R6502 CPU hardware is
included in the R6500 Microcomputer System Hardware
Manual (Document Number 29650N31). A description of the
instruction capabilities of the R6502 CPU is contalne~ in the
R6500 Microcomputer System Programming Manual (Document Number 29650N30).

Option
Option
Option
Option
Option
Option
Option

2
3
4
5
6
7
8

Clock divide by 2 or 4
Clock MASTER Mode or SLAVE Mode
with or without a 256 byte ROM
Reset Vector at FFFC or 7FFF
Port A with or without internal pull-up resistors
Port B with or without intemal pull-up resistors
Port C with or without internal pull-up resistors

All options should be specified on an R6500/13 order form.
The R6511Q has no customer specified mask options. It has
the following characteristics.
•
•
•
•
•
•

Crystal Oscillator
Clock Divide by 2
Clock MASTER Mode
Without ROM
Reset Vector at FFFC
No internal pull-up resistors or any Port (PA, PB, or PC)
1.00
--.'3.81 MM)..-

I I

Po.
PD4

PD'
PD1
PDO

PC7

PCS
PC'

..L

T

pc.

PC.

pc.

,020TYP

(.80BMM)

PC1

pco
DBO
DB1
DB.
DB3
DB.
D..
DB.
DB7

R8511Q

•

R6500113

"28

(41.35MM)

..

§

Vn

V..
XTLI

-a

mo

II

AIW

--,,=--_____--=:::r--

~

i

PAO
PA1
PA.
PA'
PA'
PA,
PA.

-~~I
j

-~--

~----'::r---;:050 REF

(127MM)
TVP

84 PIN QUIP

Figure 2-1. Mechanical Outline & Pin Out Configuration
3-190

020 REF
TVP

J

R6511Q Microprocessor and R6500/13 Microcomputer

SECTION 2
INTERFACE REQUIREMENTS
Table 2-1. R6500/13 Pin Descriptions
Pin No.
Description
Signal Name

This section describes the interface requirements for the
R6511Q and R6500/13. Figure 2-1 and 2-2 show the Interface Diagram and the pin out configuration for both devices.
Table 2-1 describes the function of each pin. Figure 3-1 has
a detailed block diagram of the R6500/13 ports which illustrates the internal function of the device.

VRR

21
43

Vss
XTLI

44
42

XTLO

41

Vee

RES

6

XTLO
XTLI

PAG-PA7 (PAD. PA1,
PA2, PA3:
EDGE DETECTS)

45

PBO-PB7 (LATCHED INPUTS)

os (PAD)
(DATA STROBE)'

23

PCo-PC7/(A13, A14

(Full address mode)"

PO()"PD7/

(OATAJADOR BUS (A4-A11))

SYNC

RrW

PAC-PAl
PBO-PBl
PCO-PCl
PDO-PDl

39-32
31-24
54-61
62-64,
1-5

AO-AI2, A15

20-1

DBO-DBl

53-46

so

(PA6),
51 (PA7)

• MULTIPLEXED FUNCTIONS PINS (Software Selectable)

Figure 2-2. Interface Diagram

SYNC

22

40

3-191

Main power supply +5V
Separate power pin for RAM.
In the event that Vee power
is off, this power retains RAM
data.
Signal and power ground (OV)
Crystal or clock input for internal clock oscillator. Also
allows input of XI clock signal If XTLO is connected to
V 55, or X2 or X4 clock if XTLO
is floated.
Crystal output from internal
clock oscillator.
The Reset input is used to
initialize the device. This signal must not transition from
low to high for at least eight
cycles after Vee reaches operating range and the internal oscillator has stabilized.
Clock signal output at internal frequency.
A negative going edge on the
Non-Maskable Interrupt signal requests that a nonmaskable interrupt be generated with the CPU.
Four 8-bit ports used for
either input/output. Each line
of Ports A, Band C consists
of an active transistor to V 55
and an optional passive pullup to Vee. In the abbreviated
or multiplexed modes of operation Port C has an active
pull-up transistor. Port 0
functions as either an 8-bit
input or 8-bit output port. It
has active pull-up and pulldown transistors.
Fourteen address lines used
to address a complete
65K external address space.
Note: A13 & A14 are sourced
through PC6 & PCl when in
the Full Address Mode.
Eight bidirectional data bus
lines used to transmit data to
and from external memory.
SYNC is a positive going signal for the full clock cycle
whenever the CPU is per·
forming an OP CODE fetch.
Controls the direction of data
transfer between the CPU
and the external 65K address space. The signal is
high when reading and low
when writing.

R6511Q Microprocessor and R6500/13 Microcomputer

SECTION 3
SYSTEM ARCHITECTURE
location is stored (or "pushed") onto the stack. Each time
data are to be pushed onto the stack, the Stack Pointer is
placed on the Address Bus, data are written into the memory
location addressed by the Stack Pointer, and the Stack
Pointer is decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented by
1. The Stack Pointer is then placed on the Address Bus and
data are read from the memory location addressed by the
Pointer.

This section provides a functional description of the R6500/
13. Functionally the R6500/13 consists of a CPU, both RAM
and optional ROM memories, four a-bit parallel I/O ports, a
serial I/O port, dual counter/latch circuits, a mode control register, and an interrupt flag/enable dual register circuit. A block
diagram of the system is shown in Figure 3-1.

NOTE
Throughout this document, unless specified otherwise,
all memory or register address locations are specified
in hexadecimal notation.

The stack is located on zero page, I.e., memory locations
OOFF-0040. After reset, which leaves the Stack Pointer
indeterminate, normal usage calls for ItS Initialization at OOFF.

3.1 CPU LOGIC

3.1.4 Arithmetic And Logic Unit (ALU)

The R6500/13 internal CPU is a standard 6502 configuration
with an a-bit Accumulator register, two a-bit Index Registers
(X and Y); an a-bit Stack POinter register, an AlU, a 16-bit
Program Counter, and standard instruction register/decode
and Internal timing control logic.

All arithmetiC and logiC operations take place In the AlU,
Including incrementing and decrementing Internal registers
(except the Program Counter) The AlU cannot store data
for more than one cycle. " data are placed on the Inputs to
the AlU at the beginning of a cycle, the result IS always gated
Into one of the storage registers or to external memory during
the next cycle

3.1.1 Accumulator
The accumulator IS a general purpose B-bIt register that
stores the results of most arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used In these operations.

Each bit of the AlU has two Inputs. These Inputs can be tied
to vanous Internal buses or to a logiC zero, the AlU then
generates the function (AND, OR, SUM, and so on) uSing
the data on the two Inputs.

3.1.2 Index Registers
3.1.5 Program Counter

There are two B-blt Index registers, X and Y. Each Index regIster can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the Index register contents

The 16-bIt Program Counter prOVides the addresses that are
used to step the processor through sequential instructIOns
In a program Each time the processor fetches an instruction
from program memory, the lower (least Significant) byte of
the Program Counter (PCl) IS placed on the low-order bits
of the Address Bus and the higher (most Significant) byte of
the Program Counter (PCH) IS placed on the high-order 8
bits of the Address Bus The Counter IS Incremented each
time an Instruction or data IS fetched from program memory.

When executing an instruction which specifies indirect
addressing, the CPU fetches the op code and the address
and modifies the address from memory by adding the index
register to it prior to loading or storing the value of memory.
Indexing greatly Simplifies many types of programs, espeCially those uSing data tables

3.1.6 Instruction Register and Instruction Decode
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These instructions are latched into the
Instruction Register, then decoded along with timing and
interrupt signals to generate control signals for the various
registers.

3.1.3 Stack Pointer
The'Stack POinter IS an' B-blt register. It IS automatically
Incremented and decremented under control of the microprocessor to perform stack mampulallon In response to either
user Instructions, an Internal IRQ Interrupt, or the external
interrupt line NMI. The Stack POinter must be Initialized by
the user program.

3.1.7 Timing Control
The Timing Control logiC keeps track of the speCifiC Instruction cycle being executed. ThiS logiC IS set to TO each time
an Instrucllon fetch IS executed and IS advanced at the
beginning of each Phase One clock pulse for as many cycles
as are reqUIred to complete the instruction. Each data transfer
which takes place between the registers IS caused by
decoding the contents of both the instruction register and
timing control Unit.

The stack allows simple Implementation of multiple level
Interrupts, subroutine nesting and Simplification of many types
of data manipulation. The JSR, BRK, RTI and RTS instructions use the stack and Stack Pointer.
The stack can be envisioned as a deck of cards which may
be accessed only from the top. The address of a memory

3-192

lJ

en

....
....
o
s::
U1

c:;-

o
"C

o

n

CD

~

o...
D)

::l

a.
lJ

en

U1
Q

g
Co)

s::

c.>

~

0'

o
n

c.>

o
3

-...

"C
C
CD

AD-A12,A15

~

ij
PCO:PCl

PBO:PB7

~t
C8{PASI

Figure 3-1.

t

CA(P.l.41

so (PA6)

Detailed Block Diagram

1m

R6511 Q Microprocessor and R6500/13 Microcomputer
3.1.8 Interrupt Logic

3.3 READ-ONL Y-MEMORY (ROM)

Interrupt logic controls the sequencing of three interrupts;
RES, NMI and IRQ. IRQ is generated by anyone of eight
conditions: 2 Counter Overflows, 2 Positive Edge Detects,
2 Negative Edge Detects, and 2 Serial Port Conditions.

The optional ROM consists of 256 bytes mask programmable
memory with an address space from 7FOO to 7FFF. ROM
locations FFFA to FFFF are assigned for interrupt vectors.
The reset vector can be optionally at 7FFE or FFFC.
The R6511Q has no ROM and its Reset vector is at FFFC.

3.2 NEW INSTRUCTIONS
3.4 RANDOM ACCESS MEMORY (RAM)

In addition to the standard R6502 instruction set, four new
bit manipulation instructions have been added to the R6500/
13. The added instructions and their format are explained in
the following paragraphs. Refer to Appendix A for the Op
Code mnemonic addressing matrix for these added instructions. The four added instructions do not impact the 'CPU
processor status register.

The RAM consists of 192 bytes of read/write memory with
an assigned page zero address of 0040 through OOFF. The
R6500/13 provides a separate power pin (V RR) which may be
used for standby power for 32 bytes located at 0040-005F.
In the event of the loss of Vee power, the lowest 32 bytes of
RAM data will be retained if standby power is supplied to the
VRR pin. If the RAM data retention is not required then VRR
must be connected to Vee. During operation VRR must be at
the Vee level.

3.2.1 Set Memory Bit (SMB m, Addr.) .
This Instruction sets to "1" one of the 8-bit data field specified
by the zero page address (memory or I/O port). The first byte
of the instruction specifies the 5MB operation and one of eight
bits to be set. The second byte of the instruction designates
address (0-255) of the byte to be operated upon.

For the RAM to retain data upon loss of Vee, VRR must be
supplied within operating range and RES must be driven low
at least eight ~2 clock pulses before Vee falls out of operating
range. RES must then be held low while Vee is out of operating range and until at least eight ~2 clock cycles after Vee
is again within operating range and the internal ~2 oscillator
is stabilized. VRR must remain within Vee operating range
during normal operation. When Vee is out of operating range,
VRR must remain within the VRR retention range in order to
retain data. Figure 3.2 shows typical waveforms.

3.2.2 Reset Memory Bit (RMB m, Addr.)
This instruction is the same operation and format as 5MB
instructIOn except a reset to "0" of the bit results~

3.2.3 Branch On Bit Set Relative (BBS m, Addr,
OEST)

RAM OPERATING MODE

This instruction tests one of eight bits designated by a 3-bit
immediate field within the first byte of the Instruction. The
second byte is used to deSignate the address of the byte to
be tested within the zero page address range (memory or
I/O ports). The third byte of the Instruction is used to specify
the 8-bit relative address to which the instruction branches
if the bit tested IS a "1 ". If the bit tested is not set. the next
sequential Instruction IS executed.

I

:

RAM RETENTION MODE

I

I

::~~r,I--@ f~::~~
I-I-

~
~
TRL
1 INITIAL APPLICATION OF vee AND VRR •
@
2 LOSS OF Vee. RAM ON STANDBY POWER.
3 REAPPLICATION OF Vee.
4 >8,2 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
5 >8 112 CLOCK PULSES.

3.2.4 Branch On Bit Reset Relative (BBR m,
Addr,OEST)
This instruction IS the same operation and format as the BBS
instruction except that a branch takes place if the bit tested
is a "0".

Figure 3-2.

3-194

®

Data Retention Timing

R6511 Q Microprocessor and R6500/13 Microcomputer
3.5 CLOCK OSCILLATOR

IS tied to Vss , the Internal countdown network IS bypassed
causing the Chip to operate at the frequency of the external
source.

The R6511 Q has been configured for a crystal oscillator, a
divide by 2 countdown network, and for Master Mode
Operation.

The operation escribed above assumed a CLOCK MASTER
MODE mask option. In this mode a frequence source (crystal,
RC network, or !;lxternal source) must be applied to the XTLI
and XTLO pins.

Three customer selectable mask options are available for
controlling the R6500/13 timing. The R6500/13 can be ordered
with a crystal or RC oscillator, a divide by 2 or divide by 4
countdown network and for clock master mode or clock
slave mode operation.

Note:
When operating at a 1 MHz internal frequency place a
15-22 pt capacitor between XTLO and GND.

For 2MHz interval operation the divide-by-2 options must be
specified.

02 is a buffered output signal which closely approximates the
internal timing. When a common external source is used to
drive multiple devices the internal timing between devices as
well as their ~2 outputs will be skewed in time. If skewing represents a system problem it can be avoided by the
Master/Slave connection and options shown in Figure 3-4.

A reference frequency can be generated with the on-chip
OSCillator uSing either an external crystal or an external resistor
depending on the mask option selected. The oscillator reference frequency passes through an Internal countdown network (divide by 2 or diVide by 4 option) to obtain the Internal
operating frequency (see Figures 3-3a and 3-3b). The external
crystal generated reference frequency IS a preferred method
since the resistor method can have tolerances approaching
50%.

One R6500/13 IS operated In the CLOCK MASTER MODE
and a second in the CLOCK SLAVE MODE. Mask options
in the SLAVE Unit convert to ~2 signal into a clock Input pin
which IS tightly coupled to the internal timing generator. As
a result the Internal timing of the MASTER and SLAVE units
are synchrOnized With minimum skew. If the ~2 signal to the
SLAVE Unit IS inverted, the MASTER and SLAVE UNITS
WILL OPERATE OUT OF PHASE. ThiS approach allows the
two devices to share external memory using cycle stealing
techniques.

Internal timing can also be controlled by driving the XTLI Pin
With an external frequency source. Figure 3-3c shows tYPical
connections. If XTLO IS left floating, the external source IS
diVided by the internal countdown network However, If XTLO

d

R = 2.4K

tiNT

R6500/13
TLI
XTLO

= 1 MHz

(USE + 4)
tEXT

R6500/13

= 4 MHz
XTLI

A. RESISTOR INPUT

,-. M" '

f'

~~w"
XTLO

=
tiNT
tEXT

MASTER
XTLO

= :s 2 MHz
= 2X or 4X

r-- __ -, INVERTER USED
I
I WHEN SLAVE IS

~

tiNT

I
I

~

Vcc

SLAVE

tEXT

= 2X or 4X

tiNT

Figure 3-4.
VCF

~30~

.....

XTLI

IR6500113

~

~O

Vss ...

C. CLOCK INPUTS

Figure 3·3.

112

XTLO

R6500/13 liNT = :s 2 MHz

I~

OUT OF PHASE
WITH MASTER

(INPUT CLOCK)

""-"",-,,,-r'l7rLI
NC [ XTLO
'--

l TO OPERATE

__.J

XTLI

~ 300!l

1-2 MHz

L __

6500113

B.-CRYSTAL INPUT

2-4 MHz

112 (OUTPUT CLOCK)

Clock Oscillator Input Options

3-195

Master/Slave Connections

R6511Q Microprocessor and R6500/1·3.M'icrOcomputer
3.6 MODE CONTROL REGISTER (MCR)

3.7 INTERRUPT FLAG REGISTER (IFR)
AND INTERRUPT ENABLE
REGISTER (IER)

The Mode Control Register contains control bits for the multifunction I/O ports and mode select bits for Counter A and
Counter B. Its setting, along with the setting of the Senal
Communications Control Register (SCCR). determines the
basic cOnfiguration of the' R6500/13 in any application. Initializing this register IS one of the first actions Of any software
program. The Mode Control Register bit assignment is shown
in Figure 3-5.

MCR

An IRQ Interrupt request can be Initiated by any or all of eight
possible sources. These sources are all capable of being
enabled or disabled by the use of the appropnate Interrupt
enabled bits in the Interrupt Enable Register (IER). Multiple
simultaneous interrupts cause the IRQ interrupt request to
remain active until all interrupting conditions have been
serviced and cleared.
The Interrupt Flag Register contains the Information that
indicates which I/O or counter needs attention. The contents
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge detect IFR bits may be
cleared by executing a RMB Instruction at address location
0010. The RMB X, (0010) Instruclion reads FF, modifies bit
X to a "0", and wntes the modified value at address location
0011. In this way IFR bits set to a "1" after the read cycle of
a Read-Modlfy-Wnte Instruclion (such as RMB) are protected
from being cleared. A logiC "1" IS Ignored when wntlng to
edge detect IFR bits.

Addr 0014

Counter B
Mode Select

Bus Mode Select

I I

0- - 0 Interval Timer
0 - ' - 1 Pulse Generation
1 - - 0 Event Counter

11 Pulse Width Meas.
0 - 0 Interval Timer
1 Asymmetric Pulse Generation
1_
0 Event Counter
1_
1 Retnggerable Interval Timer
Port B Latch
(1 = Enabled)
Port 0 Tn-State
(0= Tn State High Impedance Mode)

o-

Each IFR bit has a corresponding bit In the Interrupt Enable
Register which can be set to a "1" by wntlng a "1" In the
respective bit position at location 0012, IndiVidual IER bits
may be cleared by wntlng a "0" In the respective bit pOSition,
or by RES. If set to a "1", an IRQ will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag RegIster and Interrupt Enable Register bit assignments are shown
In Figure 3-6 and the functions of each bit are explained In
Table 3·1.

0 - - 0 Full Address
0 - - '1 Normal
1 - - 0 Abbr Bus
1 - - 1 MUll d Bus

Figure 3-5.

Mode Control Register

The use of Counter A Mode Select IS shown In Section 6.1,
The use of Counter B Mode Select is shown in Section 6.2.
The use of Port B Latch'Enable IS shown

In

Section 4.4.

The use of Port 0 In Tn-State Enable IS shown In Section
4.6.
The use of Bus Mode Select IS shown In Section 4.5 and 4.6

3-196

R6511 Q Microprocessor and 'R6500/13 Microcomputer
Addr 0012

IER

IFR

Addr 0011

PAO Positive

Edge Detect
PAl Positive
Edge Detect
PA2 NegatIve
Edge Detect
PA3 Negative
Edge Detect

Counter A
Underflow Flag
Cou .... S
Underflow Flag

Receiver
Flag

XMTR
Flag

Figure 3-6.

Interrupt Enable and Flag Registers

Table 3-1.

Interrupt Flag Register Bit Codes

Bit
Code

Function

IFRO

PAO POSItive Edge Detect Flag-Set to a "1" when a positive gOing edge IS detected on PAO.
Cleared by RMB 0 (0010) instruction or by RES

IFR 1

PAl PosItIve Edge Detect Flag-Set to a 1 when a posItive going edge IS detected on PAl
Cleared by RMB 1 (0010) Instruction or by RES

IFR2

PA2 Negative Edge Detect Flag-Set to a 1 when a negative gOing edge IS detected on PA2
Cleared by RMB 2 (0010) instruction or by RES

IFR 3'

PA3 Negative Edge Detect Flag-Set to 1 when a negatIve gOing edge IS detected on PA3.
Cleared by RMB 3 (0010) Instruction or by RES

IFR 4'

Counter A Underflow Flag-Set to a 1 when Counter A underflow occurs. Cleared by readIng
the Lower Counter A at locatIon 001 S, by wntlng to address locatIon 001 A, or by RES.

IFR 5:

Counter B Underflow Flag-Set to a 1 when Counter B underflow occurs. Cleared~readlng
the Lower Counter B at location 001 C, by wntlng to address location 001 E, or by RES.

IFR6

Receiver Interrupt Flag-Set to a 1 when any of the Senal Communication Status Register bIts

othrough 3 IS set to a 1. Cleared when the Receiver Status bits (SCSR 0-3) are cleared or by
RES.

IFR 7.

Transmitter Interrupt Flag-Set to a 1 when SCSR 6 IS set to a 1 while SCSR 5 IS a 0 or SCSR
7 IS set to a 1. Cleared when the Transmitter Status bits (SCSR 6 & 7) are cleared or by RES

3-197

R6511 Q Microprocessor and R6500/13 Microcomputer
zero. This bit is cleared to logic 0 when the resultant 8 bits
of a data movement or calculation operation are not all zero.
The R6500 Instruction set contains no instruction to specifically set or clear the Zero Bit. The Zero Bit is, however,
affected by the following instructions; ADC, AND, ASL, BIT,
CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, IN X, INY,
LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TVA.

3.8 PROCESSOR STATUS REGISTER
The 8-blt Processor Status Register, shown in Figure 3-7,
contains seven status flags. Some of these flags are
controlled by the user program; others may be controlled both
by the user's program and the CPU. The R6502 instruction set
contains a number of conditional branch instructions which are
designed to allow testing of these flags. Each of the eight processor status flags is described in the following sections.

3.8.3 Interrupt Disable Bit (I)

The Carry Bit (C) can be considered as the ninth bit of an
anthmetic operation. It is set to logic 1 if a carry from the
eighth bit has occurred or cleared to logiC 0 if no carry
occurred as the result of arithmetic operations.

The Interrupt Disable Bit (I) is used to control the servicing
of an interrupt request (IRQ). If the I Bit is reset to logic 0,
the IRQ signal will be serviced. If the bit IS set to logic 1, the
IRQ signal will be Ignored. The CPU Will set the Interrupt
Disable Bit to logiC 1 If a RESET (RES), IRQ, or Non-Maskable Interrupt (NMI) Signal is detected.

The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Clear Carry (CLC) instruction, respectively. Other operations which affect the Carry Bit
are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, ROR, RTI,
and SBC.

The I bit is cleared by the Clear Interrupt Mask Instruction
(CLI) and is set by the Set Interrupt Mask Instruction (SEI).
This bit IS set by the BRK Instruction. The Return from Interrupt (RTI) and Pull Processor Status (PLP) instructions will
also affect the I bit.

3.8.1 Carry Bit(C)

3.8.2 Zero Bit (Z)
The Zero Bit (Z) is set to logic 1 by the CPU during any data
movement or calculation which sets all 8 bits of the result to

IN1Vl1B1Dlll

z

ici

CARRY (c)Q)
1 = Carry Set

= Carry Clear

o

ZERO (Z)Q)
1
o

=Zero Result

=Non-Zero Result

INTERRUPT DISABLE
1
o

(I)®

= IRQ Interrupt Disabled

=IRQ Interrupt Enabled

DECIMAL MODE (D)Q)
1
o

= DeCimal Mode
= Binary Mode

BREAK COMMAND (B)Q)
1 _ Break Command
o
Non Break Command

=

OVERFLOW (0)0
1
o

= Overflow Set
= Overflow Clear

NEGATIVE (N)
NOTES

=

CD Not Initialized by RES
® Set to LogiC 1 by RES
Figure 3-7.

0

1 Negative Value
0= Postlve Value

Processor Status Register

3-198

R6511Q Microprocessor and R6500/13 Microcomputer
This indicator only has meaning when signed arithmetic (sign
and seven magnitude bits) is performed. When the ADC or
SBC instruction is performed, the Overflow Bit is set to logic
1 if the polarity of the sign bit (bit 7) is changed because the
result exceeds +127 or -128; otherwise the bit is cleared
to logic O. The V bit may also be cleared by the programmer
using a Clear Overflow (CLV) Instruction.

3.8.4 Decimal Mode Bit (0)
The Decimal Mode Bit (D) is used to control the arithmetic
mode of the CPU. When this bit' Is set to logic 1, the adder
operates as a decimal adder. When this bit is cleared to logic
0, the adder operates as a straight binary adder. The adder
mode Is controlled only by the programmer. The Set Decimal
Mode (SED) instruction will set the D bit; the Clear Decimal
Mode (CLD) instruction clears it. The PLP and RTI instructions also affect the Decimal Mode Bit.

The Overflow Bit may also be used with the BIT instruction.
The BIT instruction-which may be used to sample interface
devices-allows the overflow flag to reflect the condition of
bit 6 in the sampled field. During a BIT instruction the Overflow Bit is set equal to the content of the bit 6 on the data
tested with BIT instruction. When used in this mode, the
overflow has nothing to do with signed arithmetic, but is just
another sense bit for the microprocessor. Instructions affecting
the V flag are ADC, BIT, CLV, PLP, RTI and SBC.

CAUTION
The Decimal Mode Bit will either set or clear in an
unpredictable manner upon power application. This bit
must be initialized to the desired state by the user program or erroneous results may occur.

3.8.7 Negative Bit (N)
3.8.5 Break Bit (B)

The Negative Bit (N) is used to indicate that the sign bit (bit
7) in the resulting value of a data movement or data arithmetic operation is set to logiC 1. If the sign bit is set to logic
1, the resulting value of the data movement or arithmetic
operation is negative; if the sign bit is cleared, the result of
the data movement or arithmetic operation is positive. There
are no instructions that set or clear the Negative Bit since the
Negative Bit represents only the status of a result. The
instructions that effect the state of the Negative Bit are: ADC,
AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EOR,
INC, INX, INY, LOA, LOX, LDY, LSR, ORA, PLA, PLP, ROL,
ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TVA.

The Break Bit (B) is used to determine the condition which
caused the IRQ service routine to be entered. If the IRQ service routine was entered because the CPU executed a BRK
command, the Break Bit will be set to logic 1. If the IRQ routine was entered as the result of an IRQ signal being generated, the B bit Will be cleared to logiC O. There are no
instructions which can set or clear this bit.

3.8.6 Overflow Bit (V)
The Overflow Bit (V) IS used to indicate that the result of a
Signed, binary addition, or subtraction, operation is a value
that cannot be contained in seven bits (-128 '" n '" 127).

3-199

R6511 Q Microprocessor and R6500/13 Microcomputer·

SECTION 4
PARALLEL INPUT/OUTPUT PORTS
& BUS MODES

Port D may only be all inputs or all outputs. All inputs is
selected by setting bit 5 of the Mode Control Register (MCR5)
to a "0".

The devices have 32 I/O lines grouped into four S-bit ports
(PA, PB, PC, and PD). Ports A through C may be used either
for input or output individually or in groups of any combination.
Port D may be used as all inputs or all outputs.

The status of the input lines can be interrogated at any time
by reading the I/O port addresses. Note that this will return
the actual status of the input lines, not the data written into
the I/O port registers.

Multifunction I/O's such as Port A and Port C are protected
from normal port I/O instructions when they are programmed
to perform a multiplexed function.

Read/Modify/Write Instructions can be used to mOdify the
operation of PA, PB, PC, & PD. During the Read cycle of a
Read/Modify/Write instrucllon the Port I/O register is read.
For all other read instructions the port input lines are read.
Read/Modify/Write instructions are: ASL, DEC, INC, LSR,
RMB, ROL, ROR, and 5MB.

Internal pull-up resistors (FET's with an impedance range of
3K os; RL os; 12K ohm) are provided on all port pins except
Port D. A mask option to delete the internal pull-ups in S-bit
port groups is available.
The direction of the 32 I/O lines are controlled by four S-bit
port registers located· in page zero. This arrangement provides quick programming access using simple two-byte zero
page address instructions. There are no direction registers
associated with the I/O ports, thus simplifying I/O handling.
The I/O addresses are shown in Table 4-1. Appendix E.6
shows the I/O Port Timing.

4.2 OUTPUTS
Outputs for Ports A thru D are controlled by writing the
desired I/O line output states Into the corresponding I/O port
register bit pOSitions. A logiC 1 will force a high (>2AV)
output while a logic 0 will force a low «OAV) output.
Port D all outputs is selected by setting MCR5 to a "1".

Table 4·1.

1/0 Port Addresses

Port

Address

A
B
C
D

0000
0001
0002
0003

4.3 Port A (PA)
Port A can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard parallelS-bit, bit independent, I/O port
or as senal channel I/O lines, counter I/O lines, or an input
data strobe for the Port B input latch option. Table 4-2 tabulates the control and usage of Port A.

4.1 INPUTS

In addition to their normal I/O functions. PAO and PA1 can
detect positive going edges and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate an
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rate at which an edge can be detected is onehalf the ~2 clock rate. Edge detection timing is shown in Appendix E.5.

Inputs for Ports A, B, and C are enabled by loading logic 1
into all I/O port register bit positions that are to correspond
to I/O Input lines. A low «O.SV) input signal will cause a logic
o to be read when a read instruction is issued to the port
register. A high (>2.0V) Input will cause a logic 1 to be read.
An RES signal forces all I/O port registers to logic 1 thus
Initially treating all I/O lines as inputs.

3·200

R6511Q Microprocessor and ,R6500t13 Microcomputer
Table 4-2.

Port A Control & Usage

PAO I/O
MCR4

PORT B LATCH MODE

0

~

MCR4

SIGNAL

PAO(2)
PIN 39

=,

1

SIGNAL

NAME

tYPE

NAME

tYPE

PAO

1/0

PORT B
LATCH STROBE

INPUT (1)

PA1-PA3 I/O
PAl (2)
PIN 38
PA2(3)
PIN 37
PA3(3)
PIN 36

SIGNAL
NAME

tYPE

PAl
PA2
PA3

1/0
1/0
1/0

PA41(0

PA4
PIN 35

MCRO ~ 0
MCRl ~ 0
SCCR7 ~ 0
RCVR SIR MODE

COUNTER A I/O
MCRO ~ 1
MCRl ~ 0
SCCR? = 0
RCVR SIR MODE ~ 0
(4)

~ 0
(4) (5)

SIGNAL

SCCR7 = 0
SCCR6 ~ 0
MCRl ~ 1

SIGNAL

SIGNAL

NAME

TYPE

NAME

TYPE

NAME

PA4

I/O

CNTA

OUTPUT

CNTA

I
I

TYPE
INPUT (1)

SERIAL I/O SHIFT REGISTER CLOCK
SCCR? = 1
SCCR5 = 1

">,

RCVR SIR MODE
(4)

, SIGNAL

I
I

NAME
XMTR CLOCK

PAS
PIN 34

~
~

I

NAME

OUTPUT

RCVR CLOCK

SIGNAL

~
~

"

NAME

TYPE

NAME

PAS

I/O

CNTB

OUTPUT

,CNTB

SERIAL 110
XMTR OUTPUT

PA6
PIN 33

SCCR?

0

SIGNAL

~

1

SIGNAL

NAME

TYPE

NAME

TYPE

PA6

1/0

XMTR

OUTPUT

SERIAL 1/0
RCVRINPUT

PA?IIO
SCCR6

PA7
PIN 32

~

SCCR6

0

SIGNAL

~

1

SIGNAL

NAME

TYPE

NAME

tYPE

PA7

1/0

RCVR

INPUT (1)

3-201

~

1

=X

SIGNAL

SIGNAL
TYPE

~

INPUT(l}

MCR3
MCR2

0
1

NAME

SCCR?

tYPE

I

COUNTER B I/O
MCR3
MCR2

0
0

PA61/0

1

SIGNAL
TYPE

PAS I/O
MCR3
MCR2

~

(1)
(2)
(3)
(4)

I
I

Type
INPUT (1)

Hardware Buffer Float
Positive Edge Detect
Negative Edge Detect
RCVR SIR Mode = 1 when SCCR6
: SCCRS • SCCR4 = 1
(5) For the following mode' combinations PA4 is available as an input
only pin:
SCCR7·SCCR6·SCCRS·MCRl
+ SCCR7·SCCR6·?SCCR4·MCRl
+ SCCR?·SCCR6·SCCRS
+ SCCR?·SCCRSC·SCCR4,

R6511 Q Microprocessor and,'R6S00/13 Microcomputer
bit 5 of the MCR to 1 (one). Table 4-5 shows the necessary
settings for the MCR' to achieve the various modes for Port
D. When Port D is selected to operate in the Abbreviated
.ModELPDO-PD7 serves as data register bits DO-D7. When
Port D is selected to operate in the Multiplexed Mode dllta
bits DO through D7 are time multiplexed with address bits A4
through All, respectively. Refer to the Memory Maps
(Appendix C) for Abbreviated and Multiplexed memory asSignments. See Appen(lices E.3 through E.5 for Port D timing.

4.4 PORT B (PB)
Port B can be programmed as an 8-bit, bit-independent I/O
port. It has a latched input capability which may be enabled
or disabled via the Mode Control Register (MCR). Table
4-3 tabulates the control and usage of Port B. An Input Data
Strobe signal must be provided thru PAO when Port'B is programmed to be used with latched input' option. Input data
latch timing for Port B is shown in Appen.dix E.5 ..,
Port B Control & Usage

Table 4-3.

1/0 Mode

MCR4
MCR4

= 0

#
31
30
29
28 i

21
26
25
24

Pin
Name

Name

PBO
PBI
PB2
PB3
PB4
PBS
PB6
PBl

PBO
PBI
PB2
PB3
PB4
PB5
PB6,
PBl

A special attribute of Port C and Port D is their capability to
be configured via the Mode Control Register (see Section
3.6) into four different modes.

= 1

(2)

In the Full Address Mode, the separate address and data bus
are used in conjunction with PC6 and PC7, which automatically provide A13 and A14. The remaining ports perform the
normal I/O function.

Signal

Signal
Pin

4.7 BUS MODES

Latch
Mode

Type
(1)

1/0

110
110
110
110
110
110
110

Name

Type

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PBl

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

In the I/O Bus Mode all ports serve as I/O. The address and
data bus are still functional but without A13 and A14. Since
the internal RAM and registers are in the OOXX location, A 15
can be used for chip select and AO-AI2 used for selecting
8K of external memory. Thus, the device can be used to
emulate the R6500/11 in the Normal Bus Mode.

(I) Resistive Pull-Up. Active Buffer Pull-Down
(2) Input elata is stored in Port B latch by PAO Pulse

In the Abbreviated Bus Mode, the address and data lines can
be used as in the I/O Bus Mode to emulate the R6500/11.
Port C and Port D are automatically transformed into an
abbreviated address bus and control signals (Port C) and a
bidirectional data'bus (Port D). 64 Peripheral addresses can
be selected. In general usage, these 64 addresses would be
distributed to several external I/O devices such as R6522
and R6520, etc., each of which may contain more than one
unique address.

4.5 PORT C (PC)

C

Port can be programmed as an I/O port, as part of the full
address bus, and, in conjunction with Port D, as an abbreviated bus, or as a multiplexed bus. When operating in the
Full Address Mode PC6 and PC7 serve as A13 and A14 with
PCO-PC5 operating as normal I/O pins. When used in the
abbreviated or multiplexed bus modes, PCO-PC7 function as
AO-A3, A12, RlW, A13, and EMS, respectively, as shown in
Table 4-4. EMS (Exte.rnal Memory Select) is asserted (low)
whenever the internal processor accesses memory area
between 0100 and 3FFF. (See Memory Map, Appendix B),
The leading edge of EMS may be used to strobe the eight
address' lines multiplexed on Port D in the Multiplexed Bus
Mode. See Appendices E.3 through E.5 for Port C timing.

In the Multiplexed Bus Mode, the operation is similar to the
Abbreviated Mode except that a full 16K of external addresses
are provided. Port C provides the lower addresses and control signals. Port D multiplexes functions. During the first half
of the cycle it contains the remaining necessary 8 address
bits for 16K; during the second half of the cycle it contains
a bidirectional data bus. The address bits appearing on Port
D must be latched into an external holding register. The
leading edge of EMS, which indicates that the bus function
is active, may be used for this purpose.

4.6 PORT 0 (PO)

Figures 4-1 a thru 4-1 d show the possible configurations of the
four bus modes. Figure 4-2 shows a memory map of the port
as a function of the Bus Mode and further shows which
addresses are active or inactive on each of the three possible
buses.

Port P can be programmed as im I/O Port, an 8-bit tri-state
data bus, or as a multiplexed bus. Mode selection for Port
D is made by the Mode Control Register (MCR). The Port D
output drivers can be selected as .tri-state drivers by setting

3-202

R6511 Q Microprocessor and R6500113 Microcomputer
Port C Control & Usage

Table 4-4.
Full Address
Mode
MCR7
MCR6

=0
=0

MCR7
MCR6

Signal
Pin

#

Pin
Name

Name

54
55
56
5?
58
59
60
61

PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC?

PCO
PC1
PC2
PC3
PC4
PC5
A13
A14

Abbreviated
Mode

1/0 Mode

=0
=1

MCR7
MCR6

Signal
Type

Name
PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC?

1/0(1)

110(1)
1/0(1)
1/0(1)
1/0(1)
1/0(1)

OUTPUT (2)
OUTPUT (2)

Multiplexed
Mode

=1
=0

MCR7
MCR6

Signal

Signal
Type
(1)

Type
(2)

Name

1/0
1/0
1/0
1/0
1/0
1/0

AO
A1
A2
A3
A12

110

A13
EMS

RVV

1/0

=1
=1
Type
(2)

Name

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

AO
A1
A2
A3
A12

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

RVV

A13
EMS

(1) Resistive Pull·Up, Active Buffer Pull-Down
(2) Active Buffer Pull-Up and Pull-Down

Table 4-5.

Port 0 Control & Usage
Abbreviated
Mode

1/0 Modes

MCR7
MCR6
MCR5

=0
=X
=0

MCR7
MCR6
MCR5

Signal
Pin
#

Pin
Name

62
63
64
1
2
3
4
5

PDO
PD1
P02
PD3
PD4
PD5
P06
PO?

Name
PD~

PD1
P02
P03
P04
PD5
P06
PO?

=0
=X
=1

MCR?
MCR6
MCR5

Signal
Type
(1)

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

Multiplexed Mode

=1
=0
=1

MCR?
MCR6
MCR5

Signal

Name

Type
(2)

PDO
P01
PD2
PD3
P04
P05
P06
PO?

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

Signal

Signal

112 Low

112 High

Name

Type
(3)

Name

Type (2)

Name

Type (3)

DATAO
OATA1
OATA2
OATA3
OATA4
OATA5
OATA6
DATA?

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

A4
A5
A6
A?
A8
A9
A10
A11

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

DATAO
OATA1
DATA2
DATA3
DATA4
OATA5
OATA6
DATA?

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

(1) Tn-State Buffer IS In High Impedance Mode
(2) Tri-State Buffer is in Active Mode
(3) Tn-State Buffer is in Active Mode only during the phase 2 portton of a Wnte Cycle

3-203

=1
=1
=1

R6511 Q Microprocessor and R6500/'13 MicrocOmputer
,.; ,

I,"

XTLO ----_l~

""'-----+\
,~-----l~

.-------!~
...,.

.......----+\

iiiii _ _ _ _

JiEi _ _ _ _

, .. ----_l~

PORTa

•• - - -_

...

1"-_ _-./) """' •

_l~

... _----+1

---;~

---;~

.,.BITS

)

PORTe

-,------;~
Rllil1QORR8&O0f13

R8511Q(mRe5OOJ13

1"-_ _-./)

PORTO

PORTO

'

A13(PCIS)

--

A14(PC7)
UP TO MK

--,

'I--W

f'i' •

,\

UPT018k·244
OF EXTERNAL

OF EXT.I!ANAL

[ ~:'·='l'

~~·F~':"']
[ OD04-IlDOF,

6011JO.FFFF

DATA BUS

(

ADDRESS BUS

...

(VECTORSAT
9FFA-8FFF)

~12,AlI

."12,1<15

iii.

A. FULL ADDRESS MODE '

)

..alTS

PORTA

'IW_
UP TO 54 BYTD OF
DATA

EXT£IIHAL

sus (PDO-PD7)

110 OR MEMORY

["_OF,]

......

J>.
M(pe7)

lr

~
lli
EiH

R8511QDR AB6OOI1~

[~C~:::FROM ]

:s

(PC

RiW

SYNC

8'INC

UPT032K

UP TO 32K

D...tABUS

OF EXTatNAL

08/-'"

ACmlEFRDM

ADDFIESSBUS

DATA BUS

.....'"

I/O OR MEMOAY

[::::]

ADDRESS BUS
~A12,A115

"t1-AU.A15

1-tFC6l

UP TO 11k-2H
OF EXTERNAL

I!O OR MEMORY

j2

t...:;

"..

""",a

A"'A3,A12,A'3(P~,11

,......"

",

)

RJW(PC6)

1QOO.100F,
......",

A!fA:t,A12,A13(~,8)

RlllllfQORAIIOO/13

:I.
&oBITS

' ..
' ..

)"""'

...m'.

PORTA

::::

.... ..... .

' ..

NORMAL BUS MODE

"

.....

:,

--0100.1FFF

O-.DB7

\lECTORS AT )

" '"

An

C'::::f~n

r(PC8)

C. ABBREVIATED BUS MODE

A"

D. MULTIPLEXED BUS MODE

Figure 4·1. Bus Mode Configurations

3·204

EXTERNAL I/O OR
MEMORY

ACTIV£FROM

[=::J
(=~AT)

R6511 Q Microprocessor and R6500/13 Microcomputer

ABBREVIATED
MODE

NORMAL
MODE

MULTIPLEXED
MODE

FULL ADDRESS
MODE

--y--------, FFFF

8000
7FFF
INTERNAL BOOT
STRAP ROM
(R6500/13 ONLY
7FOO
7EFF

4000
3FFF
EMS VALID
(WHEN ABBR OR
MUX MODE
SELECTED)

1FFF

0100
OOFF
RAM AND
INTERNAL
REGISTERS
0010
OOOF

0003
I/O PORTS
0000
UI
:;:)

III

a:

III
III

~

:;:)

:=;

UI
:;:)

UI

:;:)

UI

:;:)

UI
:;:)

UI

:;:)

UI
:;:)

III

III

III

III

III

III

Z



A· M· e---.A
A M~A

(4)(1)
(1)

cc=:QJ.",

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Branch
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Branch

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PAGE,

lOP] n I

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#

BIT ADDRESSING (OP BY BIT #)

I 0

17 6

6

2

lE

7

3

90
FO

(2)
(2)
(2)

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30
10
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140

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l-~D

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STA
STX

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l--->Mo
A--+M
X--+M
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TAX

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TSX

s--.x

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TXS
TVA

X-A
X---->S
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51

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I 5 I 3

961412
94

3

NOTES
1 Add 1 to N If page boundary IS crossed
2 Add 1 to N If branch occurs to same page
Add 2 to N If branch occurs to different page
3 Carry not = Borrow
4 If In decimal mode Z flag IS Invalid
accumulator must be checked on zero result
5 Effects 8-blt data field of the speCIfied zero page address

6 j 2 [ 91 I 6 [ 2 [ 951 4 I 2 I 90 I 5 1 3 1 (

A8
SA
8A
AA
9A
98

2
2
2
2
2

N •
N •
N
N

1
1
1
1
1

1'1'

N •

M,

LEGEND

Y
A
M
M,
M~

M,

a

Index X
Index Y
Accumulator
Memory per effective address
Memory per stack pomter
Selecter zero page memory bit
Memory Bit 7

A

V

"
#

l:J

en
o

e.....

6C 1513
20 6 3
4C
A922A
D41A5

Q.
(II

591413

(5)

i;;~"m'-,;lo;C''''S~:'~FC:'9~1)~

SED

z c
z C

061s1210EI713

Ms--+P

~

0

C

X·l~X

Y 1 ~Y
Jump to New Loc
Jump Sub (See Fig 2)
M~A (11
M----.X (I)
M--->Y (1)
0 •
oj ~ C
No Operation

.

1

~

I»
:::J

·0
·0
cll 6 I 2 [ 01 I 5 I 2 [ 05 I 4 I 2 [DO [ 4 [ 3 [ D9 I 4 I 3

g: I; I~

4
6

o
~

E4

EE

M·l~M

2

C5

"n's:
g

. z

M.M, •

181',
58 '1'

C9
EO

.....
.....

"C

08

Y M
M l~M
X l~X
Y l~Y

RMB[#(O-7)] O--+Mh

C

Z

;6 I; j;

(2)
(2)

X M

1--+5

0

~~I ;~I !~ I ~~ I~~I ~~I ~~ I;~

1'1'
1'1'
2

1

z

N V
N
N •

31

16

5 4

7INV·BDIZC

3
79
5 2 175I'I'17D
35 4 2 30 1'13
4 3 139 I'
4 13
71 I 51'

~~ I ~

BO

0-0

PHP
PLA

STY

lOP] n I

ASS, X

• 0

A--->Ms S 1--->$
P-Ms S 1-5
S· 1-5 Ms-A

SEC

#

\2 PAGE, X I

o~e

O-V
A M (1)

sse

I OP I n I # lop I n I # I OP 1 n 1# [OPI n I

(INO), Y

2cI4131241312

Branch on N=l
Branch on Z=O
Branch on N- 0
Break (See Fig 1)
Branch on V - 0
Branch on V=l

ClV
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
INX
INY
JMP
JSR
LOA
LOX
LDY
LSR
NOP
ORA
PHA

RTS

#

~~ I~ I~ I g~ I 5 I 2 I QA I 2 1 1

AAM

O~I

=i~

lop I n I

601 41 31 651 3 12

69
29

I

IMPLIED I (lND, X)

on M,-O (5)(2)
on M.=l (5)(2)
onC=O
(2)
onC-1
(2)
on2=1
(2)

eLi

ROL

[ #

I

z .

z .
Memory BIt 6
Add
Subtract
Aod
Or
Exc1u5lVeOr
Number of cycles
Number of Bytes

s:

n'

o
()

o
3

"C
C

CD
~

R6511 Q Microprocessor and R6500/13 Microcomputer
A.3 INSTRUCTION CODE MATRIX
o

LSD 0

~

3

2

ORA

4

A

B

C

o
E

F

E

F

ASL
ABS
3 6

BBRO
ZP
3 5"

ORA
ABS,Y

ORA
ABS, X

3 4'

3 4'

ASL
ABS, X
3 7

3 5"

Zf'
3

ASL
ZP
2 5

RMBO
ZP
2 5

PHP
Implied
1 3

ORA
IMM
2 2

BPL
ORA
Relative (INO), Y
2 2"
2 5'

ORA
ZP, X
2 4

ASL
ZP, X
2 6

RMBI
ZP
2 5

CLC
Implied
1 2

AND
ZP
2 3

ROL
ZP
2 5

RMB2
ZP
2 5

PLP
Implied
1 4

AND
IMM
2 2

BMI
AND
Relative (INO, Y)
2 2"
2 5'

AND
ZP, X
2 4

ROL
ZP,X
2 6

RMB3
ZP
2 5

SEC
Implied
1 2

AND
ABS,Y
3 4'

RTI
EOR
Implied (INO,X)
1 a
2 a

EOR
ZP
2 3

LSR
ZP
2 5

RMB4
ZP
2 5

PHA
Implied
1 3

EOR
IMM
2 2

BVC
EOR
Relative (INO), Y
2 2"
2 5'

EOR
Zp, X
2 4

LSR
Zp, X
2 a

RMB5
ZP
2 5

CLI
Implied
1 2

EOR
ABS,Y
3 4'

RTS
AOC
Implied (INO,X)
1 6
2 6

AOC
ZP
2 3

ROR
ZP
2 5

RMB6
ZP
2 5

PLA
Implied
1 4

AOC
IMM
2 2

BVS
AOC
Relative (INO, Y)
2 2"
2 5'

AOC
Zp, X
2 4

ROR
ZP, X
2 6

RMB7
ZP
2 5

SEI
Implied
1 2

AOC
ABS,Y
3 4'

2

JSR
AND
Absolute (INO, X)
3 6
2 6

3

o
ORA
ABS
3 4

A

4

BRK
ORA
Implied (IND, X)
1 7
2 6

BIT
ZP
2 3

B

Accum
1

2

ROL

Accum
1

2

LSR
1

STA
ZP
2 3

STX
ZP
2 3

5MBO
ZP
2 5

DEY
Implied
1 2

BCC
STA
Relative (INO, Y)
2 2"
2 6

STY
ZP, X
2 4

STA
ZP, X
2 4

STX
ZP, Y
2 4

5MBI
ZP
2 5

7YA
Implied
1 2

STA
ABS, Y

3 5

TX5
Implied
1 2

LOY
ZP
2 3

LOA
ZP
2 3

LOX
ZP
2 3

5MB2
ZP
2 5

TAY
Implied
1 2

LOA
IMM
2 2

TAX
Implied
1 2

LOY
ZP, X
2 4

LOA
ZP, X
2 4

lOX
ZP, Y
2 4

5MB3
ZP
2 5

ClV
Implied
1 2

lOA
ABS,Y

CPY
ZP
2 3

CMP
ZP
2 3

DEC
ZP
2 5

5MB4
ZP
2 5

CMP
ZP, X
2 4

DEC
Zp, X
2 6

SBC
ZP
2 3
SSC
ZP, X
2 4

LOX
IMM
2 2

LOA
BCS
Relative (IN D), Y
2 2"
2 5'
CPY
IMM
2 2

CMP
(INO, X)
2 6

CMP
BNE
Relative (INO), Y
2 2"
2 5'
CPX
IMM
2 2

SBC
(INO,X)
2 6

CPX
ZP
2 3

BEQ
SBC
Relative (INO), Y
2 2"
2 5'

o

3

o

Implied
1 7

BBR2
ZP

3 5"

AND
ABS, X

BBR3
ZP
3 5"

3

3 4'

ROL
ABS,X
3 7

EOR
ABS
3 4

LSR
ABS
3 a

BBR4
ZP
3 5"

4

EOR
ABS, X

3 4'

LSR
ABS, X
3 7

3 5"

AOC
ABS

ROR
ABS

BBR6
ZP

3 4

3 6

3 5"

AOC
ABS, X

ROR
ABS,X
3 7

BBR7
ZP

TXA
Implied
1 2

BBR5
ZP

7

3 5"

STY
ABS

STA
ABS

STX
ABS

BBSO
ZP

3 4

3 4

3 4

3 5"

STA
ABS, X
3 5

2

BBSI
ZP
3

8

9

5"

LOY
ABS

LOA
ABS

LOX
ABS

BBS2
ZP

3 4

3 4

3 4

3 5"

lOY
ABS, X

lOA
ABS, X

3 4'

3 4'

lOX
ABS, Y
3 4'

BBS3
ZP
3 5"

8

3 4'

TSX
Implied
1 2

INY
Implied
1 2

CMP
IMM
2 2

OEX
Implied
1 2

CPY
ABS

CMP
ABS

3 4

BBS4
ZP
3 5"

C

3 4

DEC
ABS
3 a

5MB5
ZP
2 5

ClO
Implied
1 2

CMP
ABS,Y

CMP
ABS, X

3 4'

BBS5
ZP
5"

o

3 4'

INC
ZP
2 5

5MB6
ZP
2 5

INX
Implied
1 2

SBC
IMM
2 2

INC
Zp, X
2 6

5MB7
ZP
2 5

SED
Implied
1 2

SSC
ABS,Y

SBC
ABS, X

3 4'

4

8

o
BRK

ROL
ABS

3 6

3 4'

STY
ZP
2 3

LOA
(INO, X)
2 a

AND
ABS

3 4

JMP
Indirect
3 5

ROR
Accum
1 2

BBRI
ZP

BIT
ABS

3 3

2

o

3 4

JMP
ABS

Accum

STA
(INO, X)
2 6

LOY
IMM
2 2

C

ASL

CPX
ABS
3 4

NOP
Implied
1 2

A

B

C

DEC
ABS, X
3 7

3

BBsa
ZP

INC
ASS
3 6

3 5"

3 4'

INC
ABS, X
3 7

BBS7
ZP
3 5"

o

E

F

SSC
ABS

3 4

A

E

F

'Add 1 to N if page boundary is crossed,
•• Add 1 to N if branch occurs to same page;
add 2 to N if branch occurs to different page,

-op Code
-Addressing Mode
-Instruction Bytes; Machine Cycles

3-214

R6511 Q Microprocessor and R6500/13 Microcomputer

APPENDIX B
KEY REGISTER SUMMARY
7

0

I7

I ACCUMULATOR
0

I7

0

I7

15

I

7

I

I INDEX REGISTER X

PCl
I PROGRAM COUNTER
I7
'=-___S=p_ _ _----'I STACK POINTER

PC"

INlvll·lol'lzlcl

INDEX REGISTER Y
CARRY (C)

L

PC

O--::oCarryClear

ZERO (Zl

0

IN Iv I IB I 0 I' I z IC I PROCESSOR STATUS REG

CD

l=Carry Set

CD

l-=Zero Result
0= Non-Zero Result

P

,NTERRUPT DISABLE (I) ®

CPU Registers

1 -IRQ Interrupt Disabled

o -IRQ Interrupt Enabled
DECIMAL MODE (D)

CD

1 ---:: DeCimal Mode
0= Binary Mode
BREAK COMMAND (B)

CD

1 = Break Command
0= Non Break Command
OVERFLOW (0)

,

G2B

Y7

380G-3FFF

G2A

YB

300o-37FF

Y5

28OG-2FFF

74LS138 Y4

2OOG-27FF

Y3

lSOG-1FFF

Gl

5. All capacitive loading IS l30pt maximum, except as noted
below:
PA,PB
PC (I/O Modes Only)
PC (ABB and Mux Mode)
PCS, PC? (Full Address Mode)

sopt maximum
sopt maximum
130pt maximum
l30pt maximum

PARAMETER

1 MHz
MAX

MIN

MAX

lOI-'S

500

10 I-'S

Cycle Time

1000

TPWX1

XTLI Input Clock
Pulse Width
XTLO = VSS

± 25

Output Clock Pulse
Width at Minimum

Y2

10OG-17FF

A12

B

Yl

O8OG-OFFF

All

A

YO

010G-07FF

2 MHz

MIN

Tcyc

TpW02

C

Note that both EMS and Phase 2 (<1>,) must be used to correctly
enable the chip selects," the multiplexed or abbreViated bus modes.

E.2 CLOCK TIMING
SYMBOL

A13

500

TPWX1

-

250

-

± 10

TpWX1

TpWX1

TpWX1
± 20

± 25

Tcyc

TRI TF

Output Clock Rise,
Fall Time

-

25

-

15

TIR • TtF

Input Clock Rise,
Fall Time

-

10

-

10

Tcyc

T'R

1.5V

XTLI
(XTLO

= Vo s)

T pwx,
TpW02

__ T
R

3-219

TF

R6511 Q Microprocessor and R6500/13 .Microcomputer
E.3 ABBREVIATED MODE TIMING-PC AND PD
(MCR 5

= 1, MCR 6

,;, 0, MCR 7

= 1)
2 MHz

1 MHz
PARAMETER

SYMBOL

f---

MIN

MAX

MIN

T peAS

(PC5) RIW Setup Time

-

225

-

T pc. .

(PCO-PC4, PCS) Address Setup Time

-

200

-

TpBSU

(PO) Data Setup Time

TpBHR

(PO) Data Read Hold Time

50
-10

TpBHW

(PO) Data Write Hold Time

30

TpBDD

(PO) Data Output Delay

-

T PCHA

(PCO-PC4, PCS) Address Hold Time

30

TPCHA

(PC5) R!W Hold Time

30

TpCHIJ

(PC7) EMS Hold Time

10

T pcVP

(PC7) EMS Stabilization Time

30

TEsu

EMS Setup Time

-

-

-

-

35
10
_
.

MAX
140
100

r-----

r-----

30
- - - I--175
130

-

-

30

_ . 1---10
30
'----- - - - 210
350
30

E.3.1 Abbreviated Mode Timing Diagram

WRITE

READ

-TPCHR

RIW
I_-'--_......,~ TPCRS

_TPCHV

TPCVP

TPBDD
TPBSU
PDO-PD7

TPBHR

3-220

TPBHW

R6511 Q Microprocessor and R6500/13 Microcomputer
E.4 MULTIPLEXED MODE TIMING-PC AND PD
(MCR S

= 1, MCR 6 = 1, MCR 7 = 1)
1 MHz

SYMBOL

2 MHz

PARAMETER
MIN

MAX

-

225

MIN

MAX

220

-

50

-

35

(PO) Oata Read Hold Time

10

-

10

TpBHW

(PO) Oata Wnte Hold Time

30

-

30

-

Tpsoo

(PO) Oala Output Oelay

-

175

-

140

TPCHA

(PCO-PC4, PC6) Address Hold Time

30

-

30

-

T PaHA

(PO) Address Hold Time

10

100

TPCHR

T pCRS

(PC5) R/W Setup Time

T pCAS

(PCo-PC4, PC6) Address Setup Time

T pBAS

(PO) Address Setup Time

-

TpBSU

(PO) Oata Selup Time

T P9HR
I---

200

-

140
100
120

-

10
80
1- -30
-

(PC5) RIW Hold Time

30

T PCHV
T pcvo (1)

(PC7) EMS Hold Time

10

(PC7) Address to EMS Delay Time

30

T pcVP

(PC7) EMS Stabilization Time

30

-

30

-

Tesu

EMS Setup Time

-I

350

-

210

10

-

30

NOTE 1 Values assume PCo-PC4, PCS and PC? have the same capaCItive load

E.4.1 Multiplex Mode Timing Diagram
READ

WRITE r-------------"""'\

r-------------~I

_TPCHR

RIW
(PCS)

1--------..

TPCRS
_TPCHV

EMS
(PC7)
-

TESU

- ---

TPCVP

TPCHA

PCO-PC4,
PC6

_ _ TPBHA

PDOPD7

I
TPBAS

TPCVD

TPBHR

3·221

TPBHW

R6511 Q Microprocessor and R6500/13 Microcomputer
E.S I/O, EDGE DETECT, COUNTERS, AND SERIAL I/O TIMING
2 MHz

1 MHz
PARAMETER

SYMBOL

~-

MIN

MAX

1----

MIN

MAX

Internal Write to Penpheral Data Vahd

TpDW(1)
TCMOS(ll

Tpoow

-

PA, PB, PC TTL
PA, PB, PC CMOS
PO

-

500
1000

-

I---

500
1000
150

-

175

Penpheral Data Setup Time
Tposu

~TpHR
TpHA
1---TEPW

50

-

75
10

-

200

PA, PB, PC
PO

1----

50

-

75
10

-

200

Peripheral Data Hold Time
PA, PB, PC
PO

-- -

PAO-PA3 Edge Detect Pulse Width

Tcyc

-- - -

--

--

Tcyc

-

--

Counters A and B

Tcpw
Till
co

----

PA4, PAS Input Pulse Width
PA4, PAS Output Delay

-

Tcyc

-

-

-

Tcyc

500
---

-

500

-- - -

Port B Latch Mode

TpBLW
TpLSU
TpBLH

--

PAO Strobe Pulse Width
PB Data Setup Time
PB Data Hold Time

Tcyc
150
30
-- --

Tcyc

175
30
- -

-

I----

SenailiO
TpDWm

TCMosOl

Tcpw

TpDW lll
TCMOS(1)

----

PAS
PAS
P A4
PA4
PA4

XMTRTTL
XMTR CMOS
RCVR SIR Clock Width
4 Tcyc
XMTR Clock-SIR Mode (TTL)
XMTR Clock-SIR Mode (CMOS) -

500
tODD

-

-

500
1000

-

4 Tcyc

500

-

500

1000
1000
----- - - - -

NOTE 1 MaXimum Load Capacitance. 50pF
Passive Pull-Up ReqUired

E.S.1 I/O, Edge Detect, Counter, and Serial I/O Timing
TCYC

J"

/

..

PAO·PA7
PBO·PB7
PCO·PC7
PDO·PD7
EDGE DETECTS
(PAO·PA3)

TPDSU

*

...

I

T~

I

TEPW

~.SV

1.SV]

..

1.SVJ

..

1.SV

X

>t
I

CNTR
PA4,PAS

""

1,SV

..

TCPW
TCD

CNTR
(PA4, PAS)

TCPW
2.4VI
O.4VI

T pDDW
PDO·PD7

XTCMOS

PAO·PA7~PDW
PCO·PC7
PBO·PB7

2.4V

VDD-30%l
I

O.4V

.

PB
(LATCH M_O_D_E..:..l_ _ _ _-1 l ' - - - - - - - - - - - - - - - - - " T
1.SV

1.SV

PAO STROBE

__TPLSU -!I ....o------TP B L W - - - - - - - l...~1

3·222

- TpBLH

R6511 Q Microprocessor and R6500/13 Microcomputer
E.6 MICROPROCESSOR TIMING (00-07,
AO-A 12, A15, SYNC, R/W)
PARAMETER

SYMBOL

1 MHz

2 MHz

MAX

TAws

R/W Setup Time

-

225

-

140

TADS

AO-A12, A15 Setup
Time

-

225

-

140

T DSU

00-07 Data Setup Time

50

-

35

-

THR

00-07 Read Hold Time

10

-

10

THw

00-07 Write Hold Time

30

-

30

-

T MOS

00-07 Write Output
Delay

-

175

-

150

T SYN

SYNC Setup

-

225

-

175

THA

AO-A12, A15 Hold Time

30

30

-

T HRw

RIW Hold Time

30

-

T Ace

External Memory Access

-

rAce

MIN

MAX

MIN

30

-

T Ace

Time TAce = Tcyc-T FTADS - T DSU

T SYH

SYNC Hold Time

30

-

30

-

E.6.1 Microprocessor Timing Diagram

WRITE

READ

02

-THRW

RIW

AO-A12,
A15

TDSU_

TMDS

1-----,

DATA 0DATA 7
-THR

Y@<
~-S-Y-N-------------

THW~

nY"

I

''"C,

______________

3-223

~~

R6500/41. R6500/42

'1'

Rockwell

R6500/41 AND R6500/42
ONE-CHIP INTELLIGENT
PERIPHERAL CONTROLLERS
SECTION 1
INTRODUCTION

1.1 FEATURES

•
•
•
•

• Directly compatible with 6500, 6800, 8080, and Z80 bus
families
• Asynchronous Host interface that allows independent clock
operation
'
• Input, Output and Status Registers for CPU/Host data transfer
• Status register for CPU/Host data transfer operations
• Interrupt or polled data interchange with Host
• Enhanced 6502 CPU
-Four new bit manipulation instructions:
Set Memory Bit (SMB)
Reset Memory Bit (RMB)
Branch on Bit Set (BBS)
Branch on Bit Reset (BBR)
-Decimal and binary arithmetic modes
-13 addressing modes
- True indexing
• 1536-byte mask-programmable ROM
• 64-byte static RAM
• 23 TTL-compatible I/O lines (R6500/41 only)
• 47 TTL-compatible I/O lines (R6500/42 only)
• A 16-bit programmable counter/timer, with latch
-Pulse width measurement
-Pulse generation
-Interval timer
-Event counter

NMOS-3 silicon gate, depletion load technology
Single +5V power supply
40-pin DIP (R6500/41 only)
64-pin QUIP (R6500/42 only)
NOTE
This document describes both the R6500/41 and
R6500/42. In the text, the terms IPC or device will be used
when describing both parts. The few differences will be
described in the text using the terms R6500/41 or R6500/
42.

1.2 SUMMARY
The Rockwell R6500/41 and R6500/42 One-Chip Intelligent
Peripheral Controllers (IPC) are general purpose, programmable interface VO devices designed for use with a variety
of 8-bit and 16-bit microprocessor systems. The one-chip
R6500/41 IPC has an enhanced R6502 CPU, 1.5K by 8-bit
ROM, 64 by 8-bit RAM, three I/O ports with multiplexed special
functions, and a multi-function timer all contained within a 40pin package.
For systems requiring additional VO ports, the device is also
available in a 64-pin QUIP version, R6500/42, that provides
three additional 8-bit ports. In both versions, special interface
registers allow these IPC devices to function as peripheral controllers for the 6500, 6800, Z80, 8080, and other 8-bit or 16-bit
host microcomputer systems.

• Seven interrupts
- Two edge-sensitive lines; one positive, one negative
-Reset
-Counter Underflow
- Host data received
-Output Data Register full
-Input Data Register empty
• Multiplexed bus expandable to 4K bytes of external memory
• Unmultiplexed bus for Peripheral I/O expansion
• 68% of the instructions are executed in less than 2JLs @
2 MHz

The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction simplicity,
results in system cost-effectiveness and a wide range of computational power. These features make the device a leading
candidate for IPC computer applications.

To facilitate system and program development for the device
Rockwell has developed the R6541 Q which can be used as an
Emulator. A description of the R6541Q is contained in the
R6541Q Product Description (Document Order No. 2136).

Document No_ 29651N38
3-224

Product Description Order No_ 2135
Rev. 4, October 1984

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers
1.3 MASK OPTIONS

Rockwell supports development of the R6500/41 and R65001
42 with the System 65 Microcomputer Development System
and the R65001 Family of Personality Modules. Complete
in-circuit emulation With the R65001 Family of Personality
Modules allows total system test and evaluation.

*

The R6500/41 has prOVision for Internal pull-up resistors on
PA and PC ports as a mask option. This option IS available
for port groups only, not for Individual port lines.

*

The R6500/42 has provision for pull-up resistors on PA, PC,
PF, and PG ports as a mask option. This opllon IS available
for port groups only, not for IndiVidual port lines.

This product description is for the reader familiar wRh the
R6502 CPU hardware and programming capabilities. A
detailed description of the R6502 CPU hardware is included
in the R6500 Microcomputer System Hardware Manual
(Order Number 201). A description of the instruction capabilities of the R6502 CPU is contained in the R6500 Microcomputer System Programming Manual (Order Number 202).

3-225

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

SECTION 2
INTERFACE REQUIREMENTS
pin of the devices. Figures 2-3 and 2-5 show the mechanical
dimensions of the devices. Section 5 describes the Host
computer interface protocol and timing reqUirements.

This sectIOn describes the Interface requirements for the Intelligent Peripheral Controller. Figure 2-1 IS the Interface Diagram for the devices. Figures 2-2 and 2-4 show the pin out
configurations and Table 2-1 describes the function of each

R6500/41
ClKIN

I

I

ClK CIRCUIT

EDGE DETECT
PAD-PA7
(PAD-PED)
(PAl-NED)
(PA2-CNTR)

~

~

Vee

V"

CS

. I

INT lOGIC

I

6502 CPU

I

64 BYTES RAM

..

RS(AO)

~

E(RD)

I

STATUS REG.

I

PORTA

I

PORT B

PBD-PB7
(00-07, TRI·STATE)"

RJW(WR)

I
HBD-HB7 (

PGD-PG7

<

1.5K ROM

II

I

PORTC

I

CONTROL REG

II

16 BIT
COUNTER/lATCH

I

INPUT DATA
REG

II

OUTPUT DATA
REG

I

PORTG

I

I
I

Figure 2·1.

I

I

PORTF

I

R6500/42

Interface Diagram

3-226

I

PORTE

"MULTIFUNCTION PINS

PCo-PC6
(AO, Al, A2, A3,
EMS, RiW, INT)"

PED-PE7
DarlIngton Output Only

PFD-PF7

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

C=~;~I
~~

::~ : : ;

0

-

" " .,"
~2

015SMAX
(393 MM)

DOT OR NOTCH

TO LOCATE
PIN NO 1

S4 101M)

_

r.--

L-......-__

0010 MIN
(025 MM)

..,1-

InterfilceClilgram

I

L

(4851 MM)

1-

(4800 101M)

2050MAX
(51 JOMM)

19 EQUAL SPACES
TOL NONCUM

o 100 ~

(2~MM)

-1

Figure 2.2

R6500/41 Pin Out Designation
(40 PIN DIP)

OSOOMAX
(1524MII/I)

•t

r-

Figure 2-3.

(165MM)
(101 MM)

!

t

t

'" '"

IOSSYM)
(045MM)

R6500/41 Dimensional Outline

'"

(381 MM)

-I

Interface Diagram
PEl
PEO

63

62

PE4

CS
E (RD~

61
60

PES
PES

"

'"

RS~~~
~g~

~:!

HBS

~:~
:~~

~
~

~:~

~

::~
:~~

52

~g

:~

PC4

45
44
43
42

pes
pes
.2

v,

i I

I

I

1628

~---=

~

I
,__

-

---

:)2

I

~

~~

=i'"

~
33
-~
~--

..- -

680
(17 27 MM) _

poo

PFJ

'

(4135MM)

PG4
PG3
P02
pal

PA4

m

I

I

;g!

:~~

PA3

7:

020

1

( 506MM)

PBl

':.:1
:~~

IT;

I

~~s
;:~

~

::

"

PE3

elKIN

"'WI"'"

Irr~

'f"

&4

1-

j

~\.~

-£.--

""" I

I (127MM)~

--.j

j

02~y~EFJ

TYP

;~!

~~;

_~~_ _ _ _~_'"

64 PIN QUIP

Figure 2-4.

R6500/42 Pin Out Designation
(64 PIN QUIP)

Figure 2-5.
3-227

R6500/42 Dimensional Outline

R6,500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers
Table 2-1.

PIN NO.
SIGNAL NAME R6500/41 R6500/42

PIN NO.
SIGNAL NAME R6500/41 R6500/42

DESCRIPTION

ClKIN

39

3

Symmetrical square wave
100 KHz to 2 MHZ. TTL compatible Input

~2

20

23

Output timing signal-This IS
an Internally synchronized
1 x clock output sUitable for
external memory or peripheral interfacing

38

57

The reset Input IS used to Initialize the device Section 7
describes the process and
conditions of the RES
procedure

VCC

40

58

Power supply Input ( + 5V)

VSS

21

24

Signal and power ground
(OV)

CS

1

4

Chip select pin

RS (AO)

4

7

Register select Input pin used
by the Host processor to indicate that Information being
written Into the IPC IS a data
or command by1e or to indicate that Information being
read from the IPC IS a status
or data byte

R/W(WR)

2

5

3

6

Pin Description

PAO-PA7

22-29

25-32

8 bit I/O port used for either
Input or output Each line
consists of an active tranSIStor to V55 and an optional
passive pull-up to Vcc. The
two lower bits PAO and PAl
also serve as edge detect inputs. PA2 IS time shared with
the 16 bit Counter Input or
output pin, CNTR, and IS
mode selected

PBO-PB7

30-37

49-56

8 bit I/O port used for either
Input or output Each line
consists of an active transIstor to V55 and an active pullup to Vcc This port becomes
a trl-state data bus, 00-07,
In the Abbreviated or Multiplexed Bus Mode. 00-07 are
multiplexed with address lines
A4-A 11 In the Multiplexed
Bus Mode

PCO-PC6

13-19

16-22

7 bit I/O port used for either
Input or output Each line
consists of an active transIstor to V55 and an opllonal
passive pull-up to Vcc The
pins PCO to PC5 are multiplexed with address and
control signals for use In
abbreviated and multiplex
modes. PC6 IS multiplexed
with INT and IS program selectable. In these two modes
PCO-PC5 have active pullups

PEO-PE7
PFO-PF7
PGO-PG7

N/A
N/A
N/A

Host timing control signal for
data register write and read
Host timing control signal for

data register write and read.
HBO-HB7

5-12

8-15

Data bus between Host and
IPC data Input and output
registers

3-228

DESCRIPTION

1,2,64-59 For the R6500/42, the 64 pin
33-40
QUIP verSion, three addi41-48
tional ports (24 lines) are
proVided. Each line consists
of an active transistor to V55
PFO-PF7 and PGO-PG7 are
bldlrecllonal, and an opllonal
passive pull-up to Vcc IS provided. PEO-PE7 IS outputs
only with an active pullup. All
ports will source 100 /-Lamps.
at 2.4v except port E (PEOPE7) which will source 1 ma
at 1 5v

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

SECTION 3
SYSTEM ARCHITECTURE
This section provides a functional description of the IPC device. Functionally, the device consists of a CPU, both
ROM and RAM memories, three parallel I/O ports (six in the
64-pin R6500/42), counter/latch circuit, a mode control register, and an interrupt flag/enable dual register circuit. A block
diagram of the system is shown in Figure 3-1.

NOTE

data are to be pushed onto the stack, the Stack Pointer IS
placed on the Address Bus, data are written Into the memory
location addressed by the Stack POinter, and the Stack
POinter IS decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack POinter IS Incremented by
1. The Stack POinter IS then placed on the Address Bus, and
data are read from the memory localton addressed by the
POinter.

Throughout this document, unless specified otherwise,
all memory or register address locations are specified
in hexadecimal notation.

The stack IS located on zero page, I e., memory locations
007F-0040. Normal usage calls for the Initialization of the
Stack POinter at 007F.

3.1 CPU LOGIC

3.1.4 Arithmetic and Logic Unit (ALU)

The internal CPU of the device is an enhanced R6502 configuration with an S-bit Accumulator register, two S-bit Index
Registers (X and V); an S-bit Stack Pointer register, an AlU,
a 16-bit Program Counter, and standard instruction register/
decode and internal timing control logic.

All arithmetic and logiC operaltons take place In the AlU, Including Incrementing and decrementing Internal registers
(except the Program Counter). The AlU cannot store data
for more than one cycle. If data are placed on the Inputs to
the AlU at the beginning of a cycle, the result IS always gated
Into one of the storage registers or to external memory dUring
the next cycle.

3.1.1 Accumulator
The accumulator is a general purpose S-bit register that
stores the results of most arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used in these operations.

Each bit of the AlU has two Inputs. These Inputs can be !led
to various Internal buses or to a logiC zero; the AlU then
generates the function (AND, OR, SUM, and so on) uSing
the data on the two inputs.

3.1.2 Index Registers

3.1.5 Program Counter

There are two S-bit index registers, X and Y. Each index register can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the index register contents.

The 16-blt Program Counter prOVides the addresses that are
used to step the processor through sequenttal Instructions
In a program. Each time the processor fetches an Instruction
from program memory, the lower (least slgnlftcant) byte of
the Program Counter (PCl) IS placed on the low-order bits
of the Address Bus and the higher (most significant) byte of
the Program Counter (PCH) IS placed on the high-order S
bits of the Address Bus. The Counter IS Incremented each
time an Instruction or data IS fetched from program memory.

When executing an instruction which specifies indirect addressing, the CPU fetches the op code and the address, and
modifies the address from memory by adding the index register to it prior to loading or storing the value of memory.
Indexing greatly simplifies many types of programs, especially those using data tables.

3.1.6 Instruction Register and Instruction Decode
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These instructions are latched Into the
Instruction Register then decoded along with timing and Interrupt Signals to generate control Signals for the various
registers.

3.1.3 Stack Pointer
The Stack Pointer is an S-bit register. It is automatically incremented and decremented under control of the microprocessor to perform stack manipulation in response to either
user instructions, or an internal IRQ interrupt. The Stack
Pointer must be initialized by the user program.

3.1.7 Timing Control
The Timing Control logiC keeps track of the speCifiC Instruction cycle being executed. ThiS logic IS initialized each time
an instruction fetch IS executed and IS advanced at the beginning oi each low level oi the Clock In pulse for as many
cycles as are reqUIred to complete the Instruclton. Each data
transfer which takes place between the registers IS caused
by decoding the contents of both the instruction register and
timing control Unit.

The stack allows simple implementation of multiple level interrupts, subroutine nesting and simplification of many types
of data manipulation. The JSR, BRK, RTI and RTS instructions use the stack and Stack Pointer.
The stack can be envisioned as a deck of cards which may
only be accessed from the top. The address of a memory
location is stored (or "pushed") onto the stack. Each time

3-229

~

c.n
o

.e
....
~

CS
RS (AD)

CPUi1iOST
CONTROL

_+____

m

6502 CPU
WITH BIT MANIPULATION
INSTRUCTIONS ADDED

.....J

5.

::D

m

R/W(\YR)
E (RD)

--t--------

~

CPUi1iOST
STATUS
REGISTER

HBD-HB7

~
I\)

INTERRUPT
ENABLE

64 X 8
RAM

OUTPUT
DATA
REGISTER

1536

X

8

ROM

~

o

::s

(,)

a

cp

o

:::r

ClKIN

-So
::s

_2
RES

-...
!!.

Vee

PORTA

PORTB

PORTS E, F, & G
(R6500/42 only)

Vss

cQ'
CD

::s

~
-So

:::r

PCD-PC6
(AD-A3, EMS, Rm,

PAD-PA7

iNTI'

PAD-POS EDGE)"
( PAl-NEG EDGE
PA2-CNTR

PBD-PB7

( 00.07) "
A4-All

"MULTIFUNCTION SIGNALS

Figure 3-1.

R6500/41 & R6500/42 Block Diagram

PED-PE7
PFD-PF7
PGD-PG7

...

CD

!.

o

-o
o

::s

CD
....
til

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

3.1.8 Interrupt Logic

3.5 SYSTEM CLOCK

Interrupt logic controls the sequencing of two interrupts: RES
and IRQ. IRQ is generated by anyone of four conditions:
Counter Overflow, Positive Edge Detect, Negative Edge Detect, and Input Data Register FUll.

The deVice functions with an external clock. It is fully asynchronous in reference to the Host computer timing. The device clock frequency equals the external clock frequency. It
IS also made available for any external deVice synchronization at pin ~2.

3.2 NEW INSTRUCTIONS

3.6 MODE CONTROL REGISTER (MCR)

In addition to the standard 6502 Instruction set, four instructions have been added to the devices to simplify operations
that previously required a read/modify/write operation. In order for these Instructions to be equally applicable to any I/O
ports, with or without mixed input and output functions, the
I/O ports have been deSigned to read the contents of the
specified port data register dUring the Read cycle of the read/
modify/write operation, rather than I/O pinS as in normal read
cycles. The added Instructions and their format are explained
In the following subparagraphs. Refer to Appendix A for the
Op Code mnemonic addressing matrix for these added
InstrucllOns.

The Mode Control Register contains control bits for the mUltifunction I/O ports and mode select bits for the Counter, the
6500 or 8080 Bus Select, and the Interrupt (INT). Its setting
determines the basic configuration of the device In any application. Initializing this register IS one of the first actions of
any software program. The Mode Control Register bit assignment is shown in Figure 3-2.
The use of Counter A Mode Select IS shown In Section 6.
The use of the 6500/8080 Host Bus Select IS shown In Section 6.

3.2.1 Set Memory Bit (5MB m, Addr.)
The use of Interrupt Select IS shown In Section 4.5.

This instruction sets to "1" one of the 8-blt data field specified
by the zero page address (memory or I/O port). The first byte
of the Instruction speCifies the 5MB operation and 1 of 8 bits
to be set. The second byte of the Instruction designates address (OO-FF) of the byte or I/O port to be operated upon.

The use of Bus Mode Select IS shown In Sections 4.4 and
4.5.

3.2.2 Reset Memory Bit (RMB m, Addr.)
ThiS Instruction IS the same operation and format as 5MB
Instruction except a reset to "0" of the bit results.

ADDR 0014

lIeR

3.2.3 Branch on Bit Set Relative (BBS m, Addr,
DEST)
COUNTER
SELECT MODE

ThiS instruction tests one of 8 bits designated by a three bit
immediate field within the first byte of the Instruction. The
second byte IS used to designate the address of the byte to
be tested within the zero page address range (memory or
I/O ports). The third byte of the instruction IS used to speCify
the 8 bit relative address to which the Instruction branches
If the bit tested IS a "1 ". If the bit tested IS not set, the next
sequential Instruction IS executed.

BUS MODE
SELECT
NOT USED

1

BUS SELECT

~o

INTERVAL TIMER

1 PULSE GENERATOR

o

c=

6500t6800 BUS

o EVENT COUNTER

1

-eo

ZSOI8080 BUS

1 PULSE WIDTH
MEASUREMENT

INT SELECT

0- pe6
1 = iiif

3.2.4 Branch On Bit Reset Relative (BBR m,
Addr,DEST)

o

PORT B ALL INPUTS
PORT B ALL OUTPUTS
ABBREVIATED 8US MODE

1 MULTIPLEXED BUS MODE

ThiS Instruction IS the same operation and format as the BBS
instruction except that a branch takes place If the bit tested
is a "0".

Figure 3-2.

3.3 READ-ONLY-MEMORY (ROM)
The ROM consists of 1536 bytes (1.5K) mask programmable
memory with an address space from FAOO to FFFF. ROM
locations FFFC through FFFF are aSSigned for Interrupt and
reset vectors.

3.4 RANDOM ACCESS MEMORY (RAM)
The RAM consists of 64 bytes of read/write memory with an
aSSigned page zero address of 0040 through 007F.

3-231

Mode Control Register Bit Allocations

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

3.7
IER

AODR 0011
PAO POSITIVE
EDGE DETECT
INTERRUPT ENABLE
PAl NEGATIVE
EDGE DETECT
INTERRUPT ENABLE
INTERNAL INTERRUPT
REQUEST. IRQ ENABLE
EXTERNAL INTERRUPTS REQUEST 1,
INT-l ENABLE
EXTERNAL INTERRUPT REQUEST 2,
INT-2 ENABLE
COUNTER UNDERFLOW
INTERRUPT ENABLE

Figure 3-3.

Interrupt Enable Signals

Control Signal

Description

IER 0

Posilive Edge Detect. Interrupt Enablewhen this bit IS true. a positive gOing signal on PAO will generate an IRO and set
the corresponding flag bit

IER 1

Negative Edge Detect Interrupt Enablewhen this bit IS set to a "1" a negative
gOing signal on PA 1 Will generate an IRO
and set the corresponding flag bit.

IER 2

Input Data Register Full Interrupt Ena·
ble-settlng this bit to a "1" allows an
IRO to be generated each time the Host
fills the lOR setting the IDFR bit

IER 3

Output Data Register Full Interrupt Enable-when tnls bit IS an Interrupt request
to the Host IS generated each time the
ODRF flag IS set to a "1 ". (See External
Interrupts, Paragraph 3 7 1) Reading the
ODR clears INT-1 and ODRF flags

IER4

Input Data Register Empty Interrupt Enable-when thiS IS set to a "1" an Interrupt IS generated to the Host each time
the lOR IS read by the CPU The Interrupt
occurs when the IDRF flag IS cleared
INT·2 IS cleared when the Host reads the
status flag register (See External Inter·
rupts, Paragraph 3 7 1)

IER 5

(IFR)

An IRQ interrupt request can be initiated by any or all of four
possible sources. These sources are all capable of being
enabled or disabled by the use of the appropriate interrupt
enabled bits In the Interrupt Enable Register (IER). Multiple
simultaneous Interrupts Will cause the IRQ Interrupt request
to remain active until all Interrupting conditions have been
serviced and cleared.
The Interrupt Flag Register contains the Information that indicates which I/O or counter needs attention. The contents
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge detect IFR bits may be
cleared by executing a RMB Instruction at address location
0010, The RMB X, (0010) Instruction reads FF, modifies bit
X to a "0", and writes the modified value at address location
0011. In thiS way IFR bits set to a "1" aiter the read cycle of
a Read-Modlfy-Wrlte instruction (such as RMB) are protected
from being cleared. IFR bits 6 and 7 are Indeterminate on a
Read.
Each IFR bit has a corresponding bit In the Interrupt Enable
Register which can be set to a "1" by writing a "1" In the respective bit position at location 0012. IndlviduallER bits may
be cleared by writing a "0" In the respective bit poSition, or
by RES. If set to a "1", an IRQ Will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag RegIster and Interrupt Enable Register bit assignments are shown
In Figure 3-3 and the functions of each bit are explained In
Table 3-1

Interrupt Enable and Flag Registers

Table 3-1.

INTERRUPT FLAG REGISTER

AND INTERRUPT ENABLE
REGISTER (IER)

ADDR 0012

3.7.1 External Interrupts (INT)
An external Interrupt INT to the Host computer may be selected In two modes. (See Section 5 for information on the
Host/Device Interface).

OUTPUT DATA REGISTER (ODR) FULL
When IER 3 of the Interrupt Enable Register IS set to a "1",
the deVice will assert the INT (PC6) line each time it loads
the ODR. The ODRF flag of the Status Flag Register and the
IFR 3 of the IFR will be set to a "1" Indicating the ODR IS full.
The ODRF and IFR 3 flags are cleared and INT is negated
when the Host processor reads the ODA.

INPUT DATA REGISTER (lOR) EMPTY
When IER 4 of the Interrupt Enable Register IS set to a "1",
the device Will assert the INT (PC6) line each time It reads
the lOR. The IDRF flag of the Host Status Flag Register Will
be cleared and the IFR 4 flag of the IFR Will be set to a "1"
Indicating the lOR has just been read by the device. The IFR
4 flag IS cleared and INT IS negated when the Host processor
reads the Host Status Flag Register. RES ctears the IDR and
sets the IFR4 flag to indicate the register IS empty.

Counter Interrupt Enable-If enabled, an
IRO IS generated whenever the Counter
overflows

3-232

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers
zero. This bit IS cleared to logic 0 when the resultant a bits
of a data movement or calculation operation are not all zero.
The R6502 Instruction set contains no instruction to specifically set or clear the Zero BIt. The Zero Bit IS, however, affected by the following instructions; ADC, AND, ASL, BIT,
CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY,
LDA, LDX, LOY, LSR, ORA, PLA, PLP, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TYA.

3.8 PROCESSOR STATUS REGISTER
The a-bit Processor Status Register, shown in Figure 3-4,
contains seven status flags. Some of these flags are controlled by the user program; others may be controlled both
by the user's program and the CPU. The R6502 Instruction
set contains a number of conditional branch Instrucllons
which are designed to allow testing of these flags. Each of
the eight processor status flags IS described In the following
sections.

3.8.3 Interrupt Disable Bit (I)

The Carry Bit (C) can be considered as the ninth bit of an
arithmetiC operation. It IS set to logic 1 If a carry from the
eighth bit has occurred or cleared to logic 0 If no carry occurred as the result of arithmetiC operations.

The Interrupt Disable Bit (I) IS used to control the servicing
of an Interrupt request (IRQ). If the I Bit IS reset to logic 0,
the IRQ signal Will be serviced. If the bit IS set to logic 1, the
IRQ signal Will be Ignored. The CPU Will set the Interrupt
Disable Bit to logic 1 If a RESET (RES) or Non-Maskable
Interrupt (NMI) signal IS detected.

The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Clear Carry (CLC) instruction, respectively Other operations which affect the Carry Bit
are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, ROR, RTI,
and SBC.

The I bit IS cleared by the Clear Interrupt Mask Instruction
(CLI) and IS set by the Set Interrupt Mask Instruction (SEI).
This bit may also be set by the BRK Instruction. The Return
from Interrupt (RTI) and Pull Processor Status (PLP) InstruclIOns Will also affect the I bit.

3.8.1 Carry Bit (C)

3.8.2 Zero Bit (Z)
The Zero Bit (Z) IS set to logic 1 by the CPU dUring any data
movement or calculation which sets all a bits of the result to
7

6

5

4

3

o

2

I I vi I BID 111 1 J
N

Z

C

'-CARRY (C) (1)
1

~

o~

Carry Set
Carry Clear

' - - - - - Z e r o (2) (1)
1

~

o~

Zero Result
Non-Zero Result

' - - - - - - - - INTERRUPT DISABLE (I) (2)
1

~

o~

IRQ Interrupt Disabled
IRQ Interrupt Enabled

' - - - - - - - - - DECIMAL MODE (D) (1)
1

~

o~

Decimal Mode
Binary Mode

' - - - - - - - - - - - BREAK COMMAND (B) (1)
1

~

o~
L-_ _ _ _ _ _ _ _ _ _ _ _ _

Break Command
Non-Break Command

OVERFLOW (0) (1)
1

~

o~

Overflow Set
Overflow Clear

' - - - - - - - - - - - - - - - - - NEGATIVE (N) (1)
NOTES
(1) Not initialized by RES
1 ~ Negative Value
(2) Set to Logic 1 by RES
0 ~ Positive Value

Figure 3-4_

Processor Status Register

3-233

R6500/41 and 86500/42

One-Chip Intelligent Peripheral Controllers
This indicator only has meaning when signed arithmetic (sign
and seven magnitude bits) is performed. When the ADC or
SBC Instruction IS performed, the Overflow Bit IS set to logiC
1 if the polarity of the sign bit (bit 7) IS changed because the
result exceeds + 127 or -128, otherwise the bit IS cleared
to logiC O. The V bit may also be cleared by the programmer
uSing a Clear Overflow (CLV) Instruction.

3 ..8.4 Decimal .Mode Bit (D)
The Decimal Mode Bit (D), IS used to control the arithmetic
mode of the CPU. When this bit IS set to logic 1, the adder
operates as a deCimal adder. When this bit IS cleared to logiC
0, the adder operates as a straight binary adder. The adder
mode IS controlled only by the programmer. The Set DeCimal
Mode (SED) lnS1ructlon will set the 0 bit; the Clear DeCimal
Mode (CLD) Instruction will clear It. The PLP and RTI Instruc·
tlons also effect the DeCimal Mode BIt.

The Overflow Bit may also be used with the BIT Instruction.
The BIT Instruction which may be used to sample Interface
deVices, allows the overflow flag to reflect the condition of bit
6 In the sampled field. DUring a BIT instruction the Overflow
Bit IS set equal to the content of the bit 6 on the data tested
with BIT Instrctlon. When used In this mode, the overflow has
nothing to do with Signed arithmetic, but IS Just another sense
bit for the microprocessor. Instructions which affect the V flag
are ADC, BIT, CLV, PLP, RTI and SBC.

CAUTION
The DeCimal Mode Bit will either set or clear In an unpredictable manner upon power application to the device. This bit must be Initialized to the deSired state by
the user program or erroneous results may occur

3.8.5 Break Bit (B)

3.8.7 Negative Bit (N)

The Break Bit (B) IS used to determine the condition which
caused the IRQ service routine to be entered If the IRQ service routine was entered because the CPU executed a BRK
command, the Break Bit will be set to logiC 1 If the IRQ routine was entered as the result of an IRQ signal being generated, the B bit will be cleared to logiC O. There are no instructions which can set or clear this bit

The Negative Bit (N) IS used to Indicate that the sign bit (bit
7), In the resulting value of a data movement or data arithmetic operation, IS set to logiC 1. If the sign bit IS set to logic
1, the resulting value of the data movement or arithmetic
operation IS negative, If the sign bit IS cleared, the result of
the data movement or arithmetic operation IS positive. There
are no Instructions that set or clear the NegatlveSlt since the
Negative Bit represents only the status of a result. The Instructions that effect the state of the Negative Bit are. ADC,
AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EaR,
INC, INX, INY, LOA, LOX, LOY, LSR, ORA, PLA, PLP, ROL,
ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TYA.

3.8.6 Overflow Bit (V)
The Overflow Bit (V) IS used to indicate that the result of a
signed, binary addition, or subtraction, operation IS a value
that cannot be contained In seven bits (-128 ." n <; 127).

3-234

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

SECTION 4
PARALLEL INPUT/OUTPUT PORTS
low «0.8V) Input Signal Will cause a logiC 0 to be read when
a read Instruction IS ISSUed to the port register. A high ('>2.0V)
Input will cause a logiC 1 to be read. An RES 'SIgnal forces
all I/O port registers to logiC 1 thus Initially treating all I/O
lines as Inputs.

INPUT/OUTPUT PORTS
The IPC device provides three ports (PA, PB, and PC). The
15 lines of PA and PC are completely bidirectional, that IS,
there are no line grouping or port assoclallon restnctlons.
The eight lines of Port B may be programmed as all Inputs
or all outputs. Port PC, however, may be multiplexed under
program control with seven other signals. SIX of these signals
form an address and control bus for extended addressing.
The seventh signal is multiplexed with an external Interrupt
output, INT. All eight Port B lines are tn-state to permit their
use as a data bus dUring extended addressing modes.

Port B may be all Inputs or all outputs. All Inputs IS selected
by setting bits MCRS and MCR7 of the Mode Control RegIster to a "0".
The status of the Input lines can be Interrogated at any lime
by reading the I/O port addresses. Note that thiS will return
the actual status of the Input lines, not the data written Into
the I/O port registers.

The R6500/42, a 64 pin QUIP deVice, has three additional
ports: PE, PF, and PG. PE IS outputs only. PF and PG are
bidirectional.

Read/Modify/Write Instructions can be used to modify the
operation of PA, PB, PC, and also PF, & PG of the RS500/
42. During the Read cycle of a Read/Modify/Write instruction
the Port I/O register is read. For all other read instructions
the port input lines are read. Read/Modify/Write instructions
are: ASL, BBS, BBR, DEC, INC, LSR, RMB, ROL, ROR, and
5MB.

Internal pull-up resistors (FET's with an Impedance range of
3K", Rpu '" 12K ohm) may be provided on ports PA and
PC and ports PF & PG (R6500/42 only), as a mask option.
The direction of the I/O lines are controlled by 8-bit port regIsters located In page zero. This arrangement provides qUick
programming access uSing simple two-byte zero page address Instructions. There are no direction registers assocIated with the I/O ports, which Simplifies I/O handling. The
I/O addresses are shown In Table 4-1. Section E.6 shows
the I/O Port Timing.

Table 4-1.

4.2 OUTPUTS
Outputs for Ports A thru C, and Ports E thru G of the RS500/
42, are controlled by writing the deSired I/O line output states
Into the corresponding I/O port register bit posilions. A logiC
1 Will force a high ('>2.4V) output while a logiC 0 Will force
a low «0.4V) output. Port B also requires that MCRS be set
to a "I" and MCR7 be set to a "0".

I/O Port Addresses

PORT

ADDRESS

A
B
C
E
F
G

0000
0001
0002
0004
0005
0006

} R6500/42 only.

4.3 PORT A (PA)
Port A can be programmed via the Mode Control Register
(MCR) as a standard parallel 8-bit, bit Independent, I/O port,
or a counter I/O line. Table 4-2 tabulates the control and
usage of Port A.
In addition to their normal I/O functions, PAO can detect posItive gOing edges, and PAl can detect negative gOing edges.
An edge tranSItion on these pins will set a corresponding
status bit In the IFR and generate an Interrupt request if the
respective Interrupt Enable Bit is set. The maximum rate at
which an edge can be detected IS one-half the ~2 clock rate.
Edge detection timing is shown In Secllon E.5.

4.1 INPUTS
Inputs for Ports A and C, and also Ports F and G of the
RS500/42, are enabled by loading logiC 1 into all I/O port regIster bit pOSItions that are to correspond to I/O Input lines. A

Table 4-2.

Port A Control & Usage

PA21/0

PAG-PA1I!O

MCRO
MCR1
SIGNAL

PA3-PA71/0

PA2 COUNTER

=0
=D

SIGNAL

-

MCRD
MCR1

=1
=D

SIGNAL

MCRD
MCR1

=X
=1

SIGNAL

SIGNAL

NAME

TYPE

NAME

TYPE

NAME

TYPE

NAME

TYPE

NAME

TYPE

PAO (1)
PA1(2)

I/O
I/O

PA2

I/O

CNTR

OUTPUT

CNTR

INPUT (3)

PA3-PA7

I/O

(1) POSITIVE EDGE DETECT (2) NEGATIVE EDGE DETECT

(3) HARDWARE BUFFER FLOAT

3-235

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

4.4 PORT B (PB)

When used In the abbreViated or multiplexed bus modes,
PCO-PC5 function as AO-A3, R/W, and EMs, respectively,
as shown In Table 4-4. EMS. (External Memory Select) IS
asserted (low) whenever the Internal processor accesses
memory area between 0080 and OFFF. (See Memory Map,
Appendix C). The leading edge of EMS may be used to
strobe the eight address lines multiplexed on Port B in the
Multiplexed Bus Mode. See Appendix E.3 through E.5 for
Port C timing.

Port B can be programmed as an I/O ,Port, an 8-blt tn-state
data bus, or as a multiplexed bus. Mode selection for Port
B IS made by the Mode Control Register (MCR). The Port B
output drivers can be selected as tn-state output drivers by
setting bit 7 of the MCR to 0 (zero) and bit 6 of the MCR to
1. An all Inputs condition IS created by setting both MCR6
and MCR7 to 0 (zero) Table 4-3 shows the necessary settings for the MCR to achieve the vanous modes for Port B.
When Port B IS selected to operate In the Abbreviated Mode
PBO-PB7 serves as data register bits 00-07. When Port B
IS selected to operate In the Multiplexed Mode data bits DO
through 07 are time multiplexed with address bits A4 through
All, respectively Refer to the Memory Maps (Appendix B)
for AbbreViated and Multiplexed memory assignments. See
Appendix E.3 through E.5 for Port B timing.

4.6 PORT E, PORT F AND PORT G (PE,
PF & PG) R6500/42 ONLY
Port E only operates In the Output mode. It provides a Darlington output that can source current at the high (1) level.
Port F and Port G operate Identically and can be programmed as bidirectional I/O ports. They have standard output capability. See Appendix E.3 through E 5 for Port E, F
& Port G timing

4.5 PORT C (PC)
Port C can be programmed as an I/O port and in conjunction
with Port B, as an abbreViated bus, or as a multiplexed bus.

Table 4-3.

1/
l/fQ

Port B Control & Usage
ABBREVIATED
MODE

1/0 MODES
MCR?
MCR6

~

0
0

~

~

MCR?
MCR6

SIGNAL

~

0
1

MCR?
MCR6

SIGNAL

MULTIPLEXED MODE

=1
~

MCR?
MCR6

0

SIGNAL

PIN
#

PIN
#

NAME

TYPE
(1)

NAME

TYPE
(2)

NAME

30
31
32
33
34
35
36
37

49
50
51
52
53
54
55
56

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

DO
D1
D2
D3
D4
DS
D6
D7

~

1

=1

PHASE 1

PHASE 2
SIGNAL

SIGNAL

TYPE
(3)

1/0
1/0
1/0
1/0
1/0
1/0
I/O
I/O

NAME

TYPE (2)

NAME

TYPE (3)

A4
. A5
A6
A?
A8
A9
A10
A11

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

DO
D1
D2
D3
D4
D5
D6
D7

1/0
I/O

1/0
1/0
1/0
1/0
I/O

1/0

(1) TRI-STATE BUFFER IS IN HIGH IMPEDANCE MODE (2) TRI-STATE BUFFER IS IN ACTIVE MODE
(3) TRI-STATE BUFFER IS IN ACTIVE MODE ONLY DURING THE PHASE 2 PORTION OF A WRITE CYCLE

Table 4-4.

VI/I
t1

Port C Control & Usage

MCR?
MCR6

~

~

~

0
X

PIN
#

NAME

13
14
15
16
17
18
19

16
17
18
19
20
21
22

PCO
PC1
PC2
PC3
PC4
PC5
PCS'

MCR?'~

MCR? '" 1
MCR6 ~ 0

SIGNAL

PIN
#

MULTIPLEXED
MODE

ABBREVIATED
MODE

I/O MODE

MCR6

SIGNAL
TYPE
(1)

NAME

I/O
I/O
I/O
I/O
I/O

AO
A1
A2
A3
EMS

1/0

R/W

I/O

INT"

(1) RESISTIVE PULL-UP, ACTIVE BUFFER PULL-DOWN
(2) ACTIVE BUFFER PULL-UP AND PULL-DOWN

• PCS If MCRS

3-236

1

=1

SIGNAL
TYPE
(2)

NAME

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
~

0, INT If MCR5

AO
A1
A2
A3
EMS

RtW
INT"
~

1

TYPE
(2)
.OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

SECTION 5
HOST INTERFACE BUS
host write data exchange. The device can write to the F1 flag
at any time.

Two way data transfers are performed between the IPC and
the Host microprocessor by means of the Output Data RegIster and the Input Data Register. The Host can also write a
command to the lOR and read from the Host Status Flag
Register. Table 5-1 shows the Host addressing matrix. A
hardware Interrupt procedure and a software polling procedure IS available to control data traffiC between the CPU and
Host.

Table 5-1.

The ODRF (Output Data Register Full) flag IS set each time
the device writes to the Output Data Register. The setting of
the ODRF sets the device Interrupt Status Register IFR3 flag.
An Output Interrupt (INT) may be generated under program
control by setting IER3 In the Interrupt enable register The
ODRF flag IS reset only by a hardware reset or by the host
performing a read on the output data register The ODRF flag
IS reset follOWing the conclUSion of any host output data regIster read The resetting of the ODRF causes the reset of the
IFR3 flag and thus the reset of the external Interrupt (INT).

Host Addressing Matrix

RS (Ao)

READ

1

HOST
STATUS FLAG

COMMAND
INPUT

0

DATA REG
OUTPUT

DATA REG
INPUT

WRITE

The IDRF (Input Data Register Full) flag IS set follOWing the
conclUSion of any host write data exchange The setting of
the IDRF causes IFR2 of the device status register to be set
An Internal Interrupt may be generated under program control by setting IER2 In the Interrupt Enable Register The setting of IDRF also causes IFR4 to be reset The IDRF resets
dUring deVice read of the Input data register IFR2 sets and
IFR4 resets follOWing the reset of IDRF IFR4 may generate
an external output Interrupt (INT, Input buffer empty), under
program control by setting IER4 In the Interrupt enable
register

5.1 DATA REGISTERS
The device has an 8-blt Input Data Register (lOR) and an
8-bit Output Data Register (ODR). The lOR serves as a temporary storage for commands and data from the Host to the
device. When transfernng data from the Host to the device,
the follOWing conditions are In effect:

The Host Status Flag Register IS cleared by the RES Input

• CS IS asserted
• RS (AO) indicates command Input or data Input.
• The contents of the host data bus (HBO-HB7) are copied
into the lOR when the appropnate Host bus write signals
are asserted.

ADDR 00lE

INPUT DATA
REGISTER
FULL FLAG

The ODR serves as a temporary storage for data from the
device to the Host When the Host IS reading data from the
device, the follOWing condllions are In effect.

OUTPUT DATA
REGISTER
FULL FLAG

• CS IS asserted
• RS (AO) Input selects ODR or HSFR
• The contents of ODR or the Flag Register are placed on
the host data bus (HBO-HB7) when the appropriate Host
read signals are asserted.

GENERAL PURPOSE
FLAGS STATUS REGISTER

Figure 5-1.

5.2 HOST STATUS FLAG REGISTER
A Host Status Flag Register faCilitates a software protocol
that permits Independent and uninterrupted flow of data
asynchronously between the host computer and the device.

COPIES RS ON
WRITE FROM HOST

Host Status Flag Register Bit Allocation

5.3 HOST COMPUTER INTERFACE
The deVice Will work With a variety of Host Computers The
HOST Interface consists of a chip select, one address line,
2 control linE'S and an 8 bit three state data bus. Internal logic
of the deVice, controlled by MCR4, configures, the address
and two control lines to either a 6500 or 8080 operational
methodology. The Interface IS completely asynchronous and
Will work With a Host Computer up to a 5 MHz bus transfer
rate The deVice clock Input frequency need not be the same
as the Host's. A mode control register IS set to match the
Interface to that of the Host device as follows:

The Host Status Flag Register contains 8 flag bits that can
be read at any1lme by either the Host or the device See Figure 5-1. General purpose flags F2 through F6 are serviced
by the device In either read or write modes and mOnitored
by the Host (Read Only).
Flag F1 can be read at anytime by either the host or the device. The F1 flag caples the AO (RS) Input signal dUring any
3-237

One-Chip Intelligent Peripheral Controllers

R6500/41 and R6500/42

=

MCR4 = 0 When MCR4 is set to a logic zero, the IPC is configured to operate on a 650216800 type host bus. In this mode,
the E input is connected to the host transfer strobe (VMA or
02 for 6800, 02 for 6500) and the RIW input is connected to
the host microprocessor RIW output line. Figure 5-3 and
Table 5-2, together, specify the relevant timing for read and
write cycles on this type of host bus.

MCR4
1 When MCR4 is set to a logic one, the IPC is configured for operation on an 8080/Z80 type bus. In this mode,
the RD input is used as a read strobe and the WR input is
connected to the write strobe of the host microprocessor bus.
Figure 5-4 and Table 5-3 show the relevant timing characteristics for th is mode of operation.

Table 5-2. Host Interface Timing Characteristics
BSEL = 0 (6500)

Table 5·3. Host Interface Timing Characteristics
BSEL = 1 (8080)

Characteristics
1 and 2 MHz

Symbol-

Min

Max

CS, RfIN, RS Setup Time

tes

10

-

Access Time

tOA

-

90·

Data Hold Time

tOHR

10

-

Control Hold Time

tHe

10

-

Write Data Setup Time

twos

75

-

Write Data Hold Time

tOHW

10

Write Stroke Width

tWR

75'

-

Characteristics
1 and 2 MHz

Note:
90 ns when loading = 130 pF + 1 TTL LOAD and
75 ns when loading = 90 pF + 1 TIL LOAD.

Symbol

Min

tes

10

-

Data Access Time on Read

tOA

-

90·

Data Hold Time

tOHR

10

-

Control Hold Time

tHe

10

-

Write Data Setup Time

twos

75

-

Write Data Hold Time

tOHW

10

Write Stroke Width

tWR

75

-

Note:
90 ns when loading = 130 pF + 1 TTL LOAD and
75 ns when loading = 90 pF + 1 TIL LOAD.
WRITE

Figure 5·3.

Timing Diagram-Host Interface (MCR4=0) (6500 Version)

Figure 5·4.

Timing Diagram-Host Interface (MCR4 = 1) (8080 Version)
3-238

Max

CS, AO Setup Time

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

SECTION 6
COUNTER/TIMERS
The Counter operates In any of four modes. These modes
are selected by the Counter Mode Control bits In the Control
Register

The device contains a 16-blt counter and a 16-bit latch associated with It The counter can be Independently programmed to operate In one of four modes'

Counter
•
•
•
•

Pulse width measurement
Pulse Generation
Interval Timer
Event Counter

Operating modes of the Counter are controlled by the Mode
Control Register. All counting begins at the Initialization value
and decrements. When modes are selected requiring a
counter Input/output line, PA2 IS selected for Counter I/O.

MCR1
(bit 1)

MCRO
(bit 0)

0
0

0

1
1

0

1
1

Mode

Interval Timer
Pulse Generation
Event Counter
Pulse Width Measurement

The Interval Timer, Pulse Generation, and Pulse Width Measurement Modes are ¢2 clock counter modes The Event
Counter Mode counts the occurrences of an external event
on the CNTR line (PA2)
The Counter IS set to the Interval Timer Mode (00) when a
RES signal IS generated

6.1 COUNTER

6.1.1 Interval Timer Mode

The Counter consists of a 16-blt counter and a 16-blt latch
organized as follows: Lower Counter (LC), Upper Counter
(UC), Lower Latch (LL), and Upper Latch (UL). The counter
contains the count of either ~2 clock pulses or external
events, depending on the counter mode selected The contents of the Counter may be read any time by executing a
read at location 0018 for the Upper Counter and at location
001A or location 0019 for the Lower Counter. A read at location 0019 also clears the Counter Underflow Flag (IFR5)

In the Interval Timer mode the Counter IS initialized to the
Latch value by either of two conditions
1. When the Counter IS decremented from 0000, the next
Counter value IS the Latch value (not FFFF)
2. When a write operatIOn IS performed to the Load Upper
Latch and Transfer Latch to Counter address 0019, the
Counter IS loaded With the Latch value. Note that the
contents of the Accumulator are loaded Into the Upper
Latch before the Latch value IS transferred to the
Counter.

The 16-blt latch contains the counter initialization value, and
can be loaded at any time by executing a write to the Upper
Latch at location 0018 and the Lower Latch at locatIOn 001 A.
In either case, the contents of the accumulator are copied
Into the applicable latch register.

The Counter value IS decremented by one count at the fl2
clock rate. The 16-bIt Counter can hold from 1 to 65535
counts The Counter Timer capacity IS therefore 1j.LS to 65.535
ms at the 1 MHz ¢2 clock rate or 0.5j.Ls to 32 767 ms at the
2 MHz ¢2 clock rate Time Intervals greater than the maxImum Counter value can be eaSily measured by counting IRQ
Interrupt requests In the counter IRQ Interrupt routine

The Counter can be started at any time by writing to address
0019. The contents of the accumulator will be copied Into the
Upper Latch before the contents of the 16-blt latch are transferred to the Counter. The counter IS set to the latch value
whenever the Counter underflows. When the Counter decrements from 0000 the next counter value will be the latch
value, not FFFF, and the Counter Underflow Flag (IFR 5) will
be set to "1". This bit may be cleared by reading the Lower
Counter at locatIOn 0019, by writing to address locatIOn 0019,
or by RES.

When the Counter decrements from 0000, the Counter Underflow (IFR5) IS set to logiC 1 If the Counter Interrupt Enable
Bit (IER5) IS also set, an IRQ Interrupt request will be generated. The Counter Underflow bit In the Interrupt Flag RegIster can be examined In the IRQ Interrupt routine to determine that the IRQ was generated by the Counter Underflow.

3-239

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers
6.1.4 Pulse Width Measurement Mode

While the timer IS operating In the Interval Timer Mode, PA2
operates as a PA 1/0.

ThiS mode allows the accurate measurement of a low pulse
duration on the 'PA2 line. The Counter decrements by one
count at the ¢2 clock rate as long as the PA2 line IS held In
the low state. The Counter IS stopped when PA2 IS in the
high state

A timing diagram of the Interval Timer Mode IS shown In Figure 6-1.

The Counter underflow flag Will be set only when the count
In the timer reaches zero. Upon reaching zero the tlmer Will
be loaded with the latch value and continue counting down
as long as the PA2 pin IS held low. After the counter IS
stopped by a high level on PA2, the count Will hold as long
as PA2 remains high. Any further low levels on PA2 Will again
cause the counter to count down from ItS present value. The
state of the PA2 line can be determined by testing the state
of PA2.

COUNTER UNDERFLOW

t I

I IUL. LLI IIUL. LLl -, I

COUNTER

COUNTER INTERRUPT ENABlED

I
~
c~~~::: ~~~~::~g=Er-1

-'----------

COUNTER UNDERFLOW FLAG

IRQ

Figure 6·1.

-,

Interval Timer Timing Diagram

COUNT

6.1.2 Pulse Generation Mode
In the Pulse Generation mode, the PA2 line operates as a
Counter Output The line toggles from low to high or from
high to low whenever a Counter Underflow occurs, or a write
IS performed to address 0019
The normal output waveform IS a symmetrical square-wave
The PA2 output IS Initialized high when entering the mode
and transitions low when wriling to 0019
Asymmetric waveforms can be generated If the value of the
latch IS changed after each counter underflow
A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one occurrence of the output toggle condition

6.1.3 Event Counter Mode
In thiS mode PA2 IS used as an Event Input line, and the
Counter Will decrement with each rising edge detected on
thiS line The maximum rate at which thiS edge can be detected IS one-half the 112 clock rate.
The Counter can count up to 65,535 occurrences before underflowlng. As In the other modes, the Counter Underflow bit
(IER5) IS set to logiC 1 If the underflow occurs
Figure 6 2 IS a timing diagram of the Event Counter Mode

Figure 6·2.

.....1 I- T.,,,!I

CNTR~20V

Event Counter Mode
3·240

N

I

N-,

I

I
N-'

N-3

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

SECTION 7
POWER ON/INITIALIZATION CONSIDERATIONS
Table 7-1. RES Initialization of 1/0 Ports and Registers

7.1 POWER ON TIMING

BIT N O . -

After application of VCC power to the device, RES must be
held low for at least eight stable ¢2 clock cycles after Vee
reaches operating range

REGISTERS
Processor Status
Mode Control (MCR)
Int Enable (lER)
Int Flag (IFR)
Host Status Flag
Input Data
Output Data

Figure 7-1 Illustrates the power turn-on waveforms External
clock stabilization time IS tYPically 20ms

PORTS
PA Latch
PB Latch
PC Latch

PE Latch} R6500/42
PF Latch
only
PG Latch
RH ________________________

7

6

5

4

3

2

0
0
0
0
0
0

-

-

-

-

0
0
0
0
0
0

0
0
0
0
0
0

0
0
1
0
0

0

0
0
0
0
0
0

1
0
0
0
0
0
0

1
1
1
1
1
1

1
1
1
1
1
1

1
1
1
1
1
1

1
1
1
1
1
1

1
1
1
1
1
1

1
1
1
1
1
1

1

0

-

-

0
0
0
0
0
0

0
0
0
0

1
1
1
1
1
1

1
1
1
1
1
1

0
0

All RAM and other CPU registers Will Inltlahze In a random, nonrepeatable data pattern

~

7.4 INITIALIZATION
Figure 7-1,

Any initialization process for the device should Include a RES
as Indicated In the preceding paragraphs. After stabilization
of the external clock (If a power on situation) an Initialization
routine should be executed to perform (as a minimum) the
follOWing functions

Power Turn-On Timing Detail

7.2 POWER-ON RESET
The occurrence of RES gOing from low to high Will cause the
device to set the Interrupt Mask Bit-bit 2 of the Processor
Status Register-and Initiate a reset vector fetch at address
FFFC and FFFD to begin user program execution All of the
I/O ports Will be Initialized to the high (logiC 1) state All bits
of the Control Register Will be cleared causing the Interval
Timer counter mode to be selected and causing all Interrupt
enabled bits to be reset

1. The Stack POinter should be set
2 Clear or Set Decimal Mode
3 Set or Clear Carry Flag
4 Set up Mode Controls and Counter as reqUired
5 Clear Interrupts.
A tYPical Initialization routine could be as follows
LDX

Load stack pOinter starting address Into

X Register
TXS
CLD
SEC

7.3 RESET (RES) CONDITIONS
When RES IS dnven from low to high the device IS put In a
reset slate causing the registers and I/O ports to be set as
shown In Table 7-1

CLI

3-241

Transfer X Register value to Stack POinter
Clear DeCimal Mode
Set Carry Flag
Set-up Mode Control,
Counter, speCial functIOn
registers and Clear RAM as reqUIred
Clear Interrupts

R6500/41 and R6500/42

One;.Chip Intelligent Peripheral Controlle.rs

APPENDIX A
EXPANDED R6502 INSTRUCTION SET
This appendix contains a summary of the R6502 instruction
set. For detailed information, consult the R6502 Microcomputer
System Programming Manual, Document 29650 N30.

r

A.1 INSTRUCTION SET IN ALPHABETIC
SEQUENCE
i
MNEMONIC

ADC
AND
ASL

'BBR
'BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS

,

The four instructions notated with a • are added instructions for
the IPC devices which enhance the standard 6502 instruction
set.

,

INSTRUCTION

Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)

Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits In Memory With Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC
CLD
CLI
CLV
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable
Clear Overflow Flag
Compare Memory and
Compare Memory and
Compare Memory and

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

EaR

"Exclusive-Or" Memory with
Accumulator

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Index Y by One

JMP
JSR

Jump to New Location
Jump to New Location Saving Return
Address

,

INSTRUCTION

MNEMONIC

LDA
LDX
LDY
LSR

Load Accumulator with Memory
Load Index X with Memory
Load Index Y With Memory
Shift One Bit Right (Memory or
Accumulator)

Nap

No Operation

ORA

"OR" Memory With Accumulator

PHA
PHP
PLA
PLP

Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack

'RMB
ROL

Reset Memory Bit
Rotate One Bit Left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine

Bit
ROR
Accumulator
Index X
Index Y

RTI
RTS

Subtract Memory from Accumulator With
Borrow
Set Carry Flag
Set DeCimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X In Memory
Store Index Y in Memory

SBC
SEC
SED
SEI
'SMB
STA
STX
STY

TAX
TAY
TSX
TXA
TXS
TVA

...
3-242

Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
i

Accumulator to Index X
Accumulator to Index Y
Stack Pointer to Index X
Index X to Accumulator
Index X to Stack Register
Index Y to Accumulator
.l

:::rJ

A.2 R6500/41 AND R6500/42 INSTRUCTION SET SUMMARY TABLE

en

(II
PAOCESSOA STATUS

ADDRESSING MODE
MNEMONICi

'i'

~

~~

:+~~A (4)i~!

ASL
BBR(#(0-7lJ
88S(#(0-7)]
BCe
BGS
BEO
BIT
8MI
BNE
BPl
BRK
BVe
8VS

Branch on M~="
Branch on M.= 1
Branch on C=0
Branch on C = ,
Branch on Z", 1
A M
Branch on N,..,
Branch on Z
Branch on N=0
Break
Branch on V = I}
Branch on V 1

="

ClC

0-C
0-0
0-1
0--V
A-M
X-M
Y,"M
M-1<..,.M
X-l_X

DEY

Y--l-Y

EOA
INC
tNX

AVM--+A (1)
M+l_M
X+l-X

;1:gl:I;I~~I;I;
"E 6 3 06 5 2(1lA(211

0No OperallOn
AVM--oA
A_Ms S-I-S
P-Ms S-I-S
S"'_5 Ms--A
S+ l-S Ms--P
0-Mb (5)

l-C

SEO
SEI

1-0
I _____ T

4

6

I2

3D
7D
IE

I'
•

7

I3

I n III

CD •
EC •
CC
CE
2

2

40

4

EE

6

,.

3
3

'5
E6

5

2

2

C

•
•

'E

01

I

5

I

2 I 051 4 I 2

I 00

I 4

I

3

I 09 I

A5
A6
A,
'6

5

214A 12 I 1

3

05

3

,

All 6 \ 2

2

EO

4

I Bl I

5 J 2

I B5 J

en

E5

011 61 21 111

TT
,
2

3

A-M
X...... M

STY

Y-M

TAX
TAY
TSX
TXA

A-X
A-Y
S-X
X-A

TXS
TVA

o
o

Z

:&;i;

N
. 0

o •
• 0
Z C

N •

4 I3

N

4

I 2 I BO I 4

J 3

I:~

I:

I

5I

2

I

151 4 I 2 110 14 I 3 119

SA

2

•

o::l

5 13
N •

B61 4

o .
I

z C

N •

4 13

N

CDI

Z
Z
Z

I2

•

•

: :l

CD

:: I: 1~
361'1'
F8
78

2
2

C

;:I:I~I;~I;I;

C
(Restored)
Z (3)
1

N V

E116121F115121F5i4121FDI4131F91413

1
1

•

65

811

66
64

96

A8
AA
SA

X-S
Y--A

98

211

3 Carry not "" Borrow
4 If In dectmal mode Z flag IS Invalid
accumulator must be checked on zero result
Effects 8-brt data field of the specified zero page address

LEGEND
X
Index X
Y
Index Y
A
Accumulator
M
Memory per effective address
M.
Memory per stack pOinter
Mb
Selecter zero page memory bit
M,
Memory 81t 7

m

CD

a
~.

I2

2 1
121'
2 1

,
,

Add 1 to N If page boundary IS crossed
Add 1 to N If branch occurs to same page
Add 2 to N If branch occurs to different page

r4

941 41 2

6A
9A

NOTES

61 21 91 I 61 2 I 95 J 4 I 2 I 90 J 5 J 3 I ( ,I 5 J 3

cS'
~

87 I 9"7 I A7 187 IC7 I 07 1 E7 IF7

6D
6E
6C

:::T

-

• Z

071 171 271 37 1471 571 67 177

I '1

n

"0

Z

(Restored)

1

5MB(I("-7)) l-Mb (5)
STA
STX

•

2
2

08 3 1
'
'61
66 • 11
28

3

::l

Q.

(II

2
2
2
2

...a.

D)

:::rJ
M, M••

~:I:I~I~~

EA I 2 11

4

,

Z C
Z
Z C

o

:&;i;

C
C

,I,

'6
66

I Z C

N V
N
N

oslsl21DEi713

3
3
3
3

2E
6E

B 0

V

o .
I

2

"lITD'

E9

IN

2
2

6C

AC

•

7

~;I ~;I !~I ~~ I~~I ~~I ~~ I;:

T
T
2
2

76543218

BIT ADDRESSING (OP BY BIT II)

2 11

'C

A0

Opl n I II

;: I:

11

Cll 6 I 2

~13

I III

PAGE, Y

2

C5
E'
C6

OP I n

lOP

50
70

~

SEC

751'
35

lop

30
DO
10

Tninr.
(1)

31

I n I 11

00 I 7 J 1

cc=:=:!J -

Rlrn Sub
A-M-G-oA

71

21

lOP

(2)
(2)

(1)

AeL
AeA
RT!
RTS
SBC

61

III

90

A222AE
A
TITD

LSR
NOR

I OP I n I II

CaDEt

I A~S,:

(2)
(2)
(2)

M--->A (ll
M--+X (l)
M--->Y

lOP I n

/I

X

60
FO

49

lOY

10PI n I

P~G~,

I RELATIVE I INDIRECT Il

2C!4!31241312

C9
Ee
ce

Y+l-+Y

IZ

16

18122

Jump to New Loc
Jump Sub

I (I~D,~) I (I~D). ,V

(5)
(5)
(2)
(2)
(2)

56
B8

INY

PHA
PHP
PLA
PLP
RMB(#(O-7)J

I::

D6

JMP

ORA

I

IMPLIED
U,", I n r" , VI" I n I " I UI'" I n III I ut", n I II I ut" I n 1/1

C<-~---{l

CLD
ell
elV
eMP
CPX
CPY
DEC
DEX

JSA
LOA
lOX

1;I~M~DI~TEIABSIOl~T~ZER? P~GEI ~A~CU~

OPERATIOt,l

ASS, Y

n
o

",
,

z .

N
N
N
N

•
•
•
•

N

•••••

Z

Memory BIt 6
Add
Subtract

And

V

Or

Y

ExclUSive Or
Number of cycles
Number of Bytes

#

"0

:::T
CD

;;
n
o

::l

a
ti'

Ul

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

A.3 INSTRUCTION CODE MATRIX
o

o

LSD

o

8

9

A

BRK
ORA
Implied (IND,X)
1 7
2 6

ORA
ZP
2 3

ASL
ZP
2 5

RMBO
ZP
2 5

PHP
Implied
1 3

ORA
IMM
2 2

ASL
Accum
1 2

BPL
ORA
Relative (IND), Y
2 2"
2 5'

ORA
ZP, X
2 4

ASL
ZP, X
2 6

RMBI
ZP
2 5

CLC
Implied
1 2

ORA
ABS,Y
3 4'

AND
ZP
2 3

ROL
ZP
2 5

RMB2
ZP
2 5

PLP
Implied
1 4

AND
IMM
2 2

BMI
AND
Relative (IND, Y)
2 2"
2 5'

AND
ZP, X
2 4

ROL
Zp, X
2 6

RMB3
ZP
2 5

SEC
Implied
1 2

AND
ABS,Y
3 4'

RTI
EOR
Implied (IND,X)
1 6
2 6

EOR
ZP
2 3

LSR
ZP
2 5

RMB4
ZP
2 5

PHA
Implied
1 3

EOR
IMM
2 2

BVC
EOR
RelatIVe (IND), Y
2 2"
2 5'

EOR
ZP, X
2 4

LSR
Zp, X
2 6

RMB5
ZP
2 5

CLI
Implied
1 2

EOR
ABS,Y
3 4'

RTS
ADC
Implied (IND, X)
1 6
2 6

ADC
ZP
2 3

ROR
ZP
2 5

RMB6
ZP
2 5

PLA
Implied
1 4

ADC
IMM
2 2

BVS
ADC
Relative (IND, Y)
2 2"
2 5'

ADC
ZP, X
2 4

ROR
ZP, X
2 6

RMB7
ZP
2 5

SEI
Implied
1 2

ADC
ABS,Y
3 4'

2

en

::;

2

9

A

B

C

o
E

AND
JSR
Absolule (IND, X)
3 6
2 6

BIT
ZP
2 3

Implied

-op Code

1 7

-Addressing Mode
-Instruction Bytes; Machine Cycles

B

C

ROL
Accum
1 2

BIT
ABS
3 4

LSR
Accum
1 2

JMP
ABS
3 3

JMP
Indirect
3 5

ROR
Accurn
1 2

F

3 6

BBRO
ZP
3 5"

ORA
ABS, X
3 4'

ASL
ABS, X
3 7

BBRI
ZP
3 5"

AND
ABS
3 4

ROL
ABS
3 6

BBR2
ZP
3 5"

AND
ABS, X
3 4'

ROL
ABS, X
3 7

BBR3
ZP
3 5"

EOR
ABS
3 4

LSR
ABS

BBR4
ZP

3 6

3 5"

EOR
ABS, X
3 4'

LSR
ABS, X
3 7

BBR5
ZP
3 5"

ADC
ABS
3 4

ROR
ABS
3 6

BBR6
ZP
3 5"

ADC
ABS,X
3 4'

ROR
ABS, X
3 7

3 5"

STA
ABS
3 4

STX
ABS

BBSO
ZP

3 4

3 5"

STX
ZP
2 3

5MBO
ZP
2 5

DEY
Implied
1 2

BCC
STA
Relative (IND, Y)
2 2"
2 6

STY
ZP, X
2 4

STA
ZP, X
2 4

STX
ZP, Y
2 4

5MBI
ZP
2 5

TVA
Implied
1 2

STA
ABS, Y
3 5

TXS
Implied
1 2

LOY
ZP
2 3

LOA
ZP
2 3

LOX
ZP
2 3

5MB2
ZP
2 5

TAY
Implied
1 2

LOA
IMM
2 2

TAX
Implied
1 2

LOY
ABS
3 4

LOA
ABS
3 4

LOX
ABS
3 4

BBS2
ZP
3 5"

LOY
Zp, X
2 4

LOA
ZP, X
2 4

LOX
ZP,Y
2 4

5MB3
ZP
2 5

CLV
Implied
1 2

LOA
ABS,Y
3 4'

TSX
Implied
1 2

LOY
ABS, X
3 4'

LOA
ABS, X
3 4'

LOX
ABS, Y
3 4'

BBS3
ZP

3 5"

CPY
ZP
2 3

CMP
ZP
2 3

DEC
ZP
2 5

5MB4
ZP
2 5

INY
Implied
1 2

CMP
IMM
2 2

DEX
Implied
1 2

CPY
ABS

3 4

CMP
ABS
3 4

DEC
ABS
3 6

3 5"

CMP
ZP, X
2 4

DEC
ZP, X
2 6

5MBS
ZP
2 5

CLD
Implied
1 2

CMP
ABS, Y
3 4'

CMP
ABS, X
3 4'

DEC
ABS, X
3 7

SBC
ZP

INC
ZP
2 5

5MB6
ZP
2 5

INX
Implied
1 2

SBC
IMM
2 2

SBC
ABS
3 4

INC
ABS
3 6

3 5"

INC
ZP, X
2 6

5MB?
ZP
2 5

SED
Implied
1 2

SBC
ABS,Y
3 4'

sse
ABS, X
3 4'

INC
ABS, X
3 7

BBS7
ZP
3 5"

o

E

F

BCS
LOA
RelatIVe (IND), Y
2 2"
2 5'
CPY
IMM
2 2

CMP
(IND,X)
2 6

BNE

CMP

LOX
IMM
2 2

Relative (IND), Y
2 2"
2 5'
CPX
IMM

SBC
(IND,X)
2 6

BEO
sse
Relative (IND), Y
2 2"
2 5'

CPX
ZP
2 3

2 3

sse
ZP, X
2 4

9

3 4

A

BBSI
ZP
3 5"

STA
ABS, X
3 5

NOP
Implied
1 2

CPX
ABS
3 4

B

C

o

BBR7
ZP

STA
ZP
2 3

LOA
(IND, X)
2 6

STY
ABS

E
ASL
ABS

STY
ZP
2 3

LOY
IMM
2 2

TXA
Implied
1 2

o
ORA
ABS
3 4

STA
(IND,X)
2 6

2 2
F

6

3

BRK

BBS4
ZP

BBSS
ZP

A

B

C

o

3 5"
BBS6
ZP

E

F

•Add 1 to N If page boundary IS crossed,
.. Add 1 to N if branch occurs to same page;
add 2 to N if branch occurs to different page,

3-244

One-Chip Intelligent Peripheral Controllers

R6500/41 and R6500/42

APPENDIX B
KEY REGISTER SUMMARY
Processor Status Register

CPU Registers
7

0

I':-___-"-___~I
7

~l===~===~J

r15'--_--;;;;:;--_ _ _

\"\ v\

ACCUMULATOR

0

-,':-(:....-_-_-_-_-_-~=-~-----------.:--:._;J

lL__--'P"'C:o.H_ _ _- - ' ; -_ _.:.PC"'L'--_ _-;;J

\. \ 0\ 1\ Z\ C j

L:

INDEX REGISTER Y

INDEX REGISTER X

PC

PROGRAM COUNTER

' : : - - - - s ' - - P - - - - : J STACK POINTER

CARRY (e) (1) ,

Carry Set
Cerry Clnr

1

o

ZItfO(2) (1)

1
o

Zero Rnull
Non-Zero Result

INTERRUPT DISABLE (I) (2)

I BID II I z 10 I PROCESSOR STATUS REG

1
o

P

~

IRO IntelTupt Di••bled
IRQ Interrupt Enabt.d

DECIMAL MODE (0) (1)
1 - Decima' Mode
o
BiNiry MoM

BREAK COMMAND (8) (1)

Mode Control Register

1
a,...k Command
o - Non-Bruk Command
OVERFLOW (0) (1)

Me.

ADOR 0014

1 - Overflow Set
o - OverflowelNr
NEGAnVE (N) (1)

NOTES

I

COUNTER
SELECT MODE

I

o

INTERVAL TIMER
PULSE GENERATOR
EVENT COUNTER
1 PULSE WIDnt MEASUREMENT

NOT USED

o

o

o-

,l,

BUS MODE

I

1 - NegatIVe Velue
POsitive V.lue

(1) Not InitiaUHd by RES
(2) Set to logiC 1 by RES

aus SELECT

o1

Interrupt Enable and Flag Registers

850016800 BUS
Z80(8080 BUS

IH'f SELECT

'E.

o pea
1

IN'f

ADDR 0012

PORT B ALL INPUTS
PORT B ALL OUTPUTS
ABBREVIATED aus MODE
1 MULTIPLEXED BUS MODE

0

ADDR 0011

Host Status Flag Register
PAO POSITIVE
EDGE DETECT
INTERRUPT ENABLE

ADDR 001E

HSFR

PAl NEGATIVE
EDGE DETECT
INTERRUPT ENABLE
INTERNAL INTERRUPT
REQUEST, IRQ ENABLE
EXTERNAL INTERRUPTS REQUEST 1,
INT-1 ENABLE
INPUT DATA REGISTER
FULL FLAG

EXTERNAL INTERRUPT REQUEST 2,
INT-2 ENABLE
COUNTER UNDERFLOW
INTERRUPT ENABLE

OUTPUT DATA RE~STER

rc:ULl

~1...AG

Host Addressing Matrix

GENERAL PURPOSE
FLAGS STATUS REGISTER

3-245

WRITE

RS(A,)

READ

1

HOST
STATUS FLAG

COMMAND
INPUT

0

DATA REG
OUTPUT

DATA REG
INPUT

COPIES AS ON
WRITE FROM HOST

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

APPENDIX C
MEMORY MAPS AND ADDRESS AND PIN ASSIGNMENTS
C.1 ABBREVIATED BUS MODE MEMORY MAP

FFFE

IRQ VECTOR

FFFC

fl:S VECTOR

* R6500142 ONI.. Y
#DELETED FOR NORMAL MODE

FFFB

I

ROM 1 SK

FADO

I

OFFf

/

ZONE FOR 16

SIS (ACTIVe LOW)

~~O

007F

I

PERIPHERAL
DEVICE

I

I

001F

I

I

0010

I

ADDRESSES#

/

INTERNAL RAM
(64 BYTES)

0040

I

UNASSIGNED

I

I

I

I

I

I

I

0006

I

0000

I

INTERNAL
110 PORTS E, F & G*

0004

-

/

00IF

!

INTERNAL
REGISTERS

000'

INTERNAL

INTERNAL

110 PORTS A, e, C

110 AND REGISTERS

I

0000

C.2 MULTIPLEXED BUS MODE MEMORY MAP

FFFE

IRQ VECTOR

FFFC

RES VECTOR

., R6500/42 ONI.. Y

FFFB

I

ROM 15K

FADO

----,lr---

00IF

OFFF

I
EXTERNAL

I~o

007F

I

MEMORY
4()96.128 BYTES
MULTIPLEXED
DATA AND ADDRESS

I

0010

I

I

INTERNAL RAM
(64 BYTES)

I

UNASSIGNED

I

I

I

I

I

I
INTERNAL

110 PORTS E, F & G*

,

0006
I

0004

/

00IF

I

/

INTERNAL
REGISTERS

/

"US

0040

0000

I

I

000'

INTERNAL

INTERNAL

110 AND REGISTERS

-------

110 PORTS A,

e,

C

3-246

I

0000

'R6500/42 ONLY

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

C.3 I/O AND INTERNAL REGISTER ADDRESSES
ADDRESS
001F
1E

READ

--

Host Status Flag Register

--

1C

Input Oata Register (lOR)

1B
1A
19
18

Lower Counter
Lower Counter & Clear Flag (IFR5)
Upper Counter

13
12
11
10

Host Status Flag Register

--

10

17
16
15
14

WRITE

--

Output Oata Register (OOR)

--

-Lower Latch
Upper Latch/Transfer Latch to Counter & Clear Flag (IFR5)
Upper Latch

--

--

--

--

--

--

Mode Control Register

Mode Control Register

--

-Interrupt Enable Register

Interrupt Enable Register
Interrupt Flag Register
Read "FF"

OF
OE
00
OC

--

OB
OA
09
08

--

-Clear Int Flag Bit

--

-----

---

---

---

----

---

07
06
05
04

Port G (R6500/42 only)
Port F (R6500/42 only)
Port E (R6500/42 only)

03
02
01
00

Port C
Port B
Port A

Port G (R6500/42 only)
Port F (R6500/42 only)
Port E (R6500/42 only)

--

-PortC
Port B
Port A

C.4 MULTIPLE FUNCTION PIN ASSIGNMENTS

PIN NUMBER
R6500/41
R6500/42

FUNCTION

ABBREVIATED PORT
FUNCTION

MULTIPLEXED PORT
FUNCTION

I/O

13
14
15
16

16
17
18
19

PCO
PC1
PC2
PC3

AO
A1
A2
A3

AO
A1
A2
A3

17
18
19

20
21
22

PC4
PC5
PC6/INT

R/W
EMS
PC6/INT

R/W
EMS
PC6/INT

30
31
32
33

49
50
51
52

PBO
PB1
PB2
PB3

00
01
D2
03

A4/00
A5/01
A6iD2
A7/03

34
35
36
37

53
54
55
56

PB4
PBS
PB6
PB7

04
05
06
07

A8/04
A9/05
A10/06
A11I07

3-247

One-Chip Intelligent Peripheral Controllers

R6500/41 and R6500/42
MAXIMUM RATINGS*
Parameter

Symbol

Value

Unit

Vee

-0.3 to + 7.0

Vdc

Supply Voltage
Input Voltage

VIN

-0.3 to +7.0

Vdc

Operating Temperature
Commercial

TA

TL to TH
Oto +70

·C

Storage Temperature

TSTG

-55 to +150

·C

"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

DC CHARACTERISTICS
01cc

= 5.0V

±5%, Vss

= OV;

TA

= 0° to 70·e,

Parameter

unless otherwise specified)
Symbol

Min

Typl

Input High Voltage

VIH

+2.0

Input Low Voltage

VIL

-0.3

Input Leakage Current
RES, NMI

liN

-

-

-

-1.0

Input Low Current

IlL

Output High Voltage

VOH

+2.4

-

VCMOS

Vee-30%

-

Output High

Vo~age

(CMOS)

Output Low Voltage

VOL

1/0 Port Pull-Up Resistance

RL

3.0

6.0

Max
Vcc

Unit

Teet Conditione

V

+0.8

V

±10.0

,.A

VIN

= 0 to 5.0V
= 0.4V

-1.6

mA

VIL

Vee

V

ILOAO = -100,.A
Vcc = 4.75V

Vcc

V

Vce

+0.4

V

ILOAD = 1.6 mA
Vec = 4.75V

11.5

Kohm

= 4.75V

PAO-PA7, PCO-PC7, PFO-PF73, PGO-PG73

-

= 2.4V

Output High Current (Sourcing)

IOH

-100

-

Output Low Current (Sinking, PE3)

IOL

1.6

mA

VOH

10

pF

TA = 25·C
VIN = OV
f = 1.0 MHz

10

pF

TA = 25·C
VIN = OV
f = 1.0 MHz

1050

mW

TA = 25·C

Darlington Current Drive (PE3)

IOH

-1.0

Input Capacitance
PA, PB, PC, PF3, PG3

CIN

-

-

Output Capacitance (Three-State Off)

COUT

-

-

Power DiSSipation (Outputs High)

Po

-

550

Notes:
1. Typical values measured at TA = 25·C and Vce = 5.0V.
2. Negative sign indicates outward current flow, poSItive indicates Inward flow.
3. R6500/42 only.

3-248

,.A

VOH

mA

VOL = 0.4V

= 1.5V

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

APPENDIX E
TIMING REQUIREMENTS AND CHARACTERISTICS

E.1 GENERAL NOTES
1 Vee

5V ± 5°,,0 C

,s;

TA

,s;

E.2 CLOCK TIMING
70 C

2 A valid Vee - RES sequence
operation IS achieved

IS

SYMBOL

required before proper

3 All timing reference levels are 0 BV and 2 OV. unless
otherwise specified

S All capacitive loading
below

IS

~

eLKIN

500

lOl"s

ClKIN Input Clock
Pulse W,dth

475

Tpw/O
+25

Tpw/O

Tpw~

+20

-

25

-

15

TIR TIF

Input Clock R,se
Fall T,me

-

10

-

-10

1-"
1.SV

Tpw_o

.

.

T pW02

.., 7

_T,

•
.....l

I'-

3-249

-

Output Clock Rise.
Fall T,me

..

-

240

TR , TF

It

;2

-

I
Output Cloek Pulse I T pw/O
W,dth at Minimum
TCYC

SOpf maximum
SOpf maximum
130pf maximum

T"

MAX

lOl"s

Tpw.o

T",c

1.SV

MIN

1000

130pf maximum. except as noted

PA,PB
PB, PC (I/O Modes Only)
PB, PC (ABB and Mux Mode)

MAX

Cycle Time

pW02

2 MHz

MIN

Tcvc

r----'
T

4 All time Units are nanoseconds. unless otherwise specified

1 MHz

PARAMETER

-

~

~.-

~

_T,

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

E.3 ABBREVIATED MODE TIMING-PB AND PC
(MeR s = 1, MeR 6 = 0, MeR 7 = 1)
1 MHz
SYMBOL

PARAMETER

MIN

2 MHz

MAX

MIN

(PC5) R/W Setup Time

TpCAS

(PCO-Pe3) Address Setup Time

-

TpBSU

(PB) Data Setup Time

50

TpBHR

(PB) Data Read Hold Time

10

TPSHW

(PB) Data Write Hold Time

30

-

TpBOD

(PB) Data Output Delay

-

175

TpCHA

(PCO-PC3) Address Hold Time

30

-

30

TPCHR

(PC5) R/W Hold Time

30

-

30

TpcHV

(PC4) EMS Hold Time

10

-

10

-

Tf'CVP

(PC4) EMS Stabilization Time

30

-

30

-

Tesv

EMS Setup Time

NOTE 1. Values assume

-

MAX

TpcRS

225
225

140

35

-

10

-

30

-

-

150

-

350
pco-pes have the same capacitive load

140

210

E.3.1 Abbreviated Mode Timing Diagram

WRITE

READ

r-------------~I

__ TpCHR

RIW
(pes)
TpcRS

_

TpCHY

Tp9Su

PBO-PB7

TpBHR

3-250

TpBHW

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

E.4 MULTIPLEXED MODE TIMING-PB AND PC
(MCR 5

~

1, MCR 6

~

1, MCR 7

~

1)

2 MHz

1 MHz
SYMBOL

PARAMETER

MIN

TpcRS

(PCS) R/W Setup Time

TpcAS

(PCO-PC3) Address Setup Time

-

TPBAS

(PS) Address Setup Time

-

MAX

MIN

MAX

225

-

140

225

-

140

225

-

140

-

TPBsu

(PS) Data Setup Time

50

-

35

TPSHR

(PS) Data Read Hold Time

10

-

10

-

TpBHW

(PS) Data Write Hold Time

30

-

30

-

TPSOD

(PS) Data Output Delay

-

175

-

150

TPCHA

(PCO-PC3) Address Hold Time

30

-

30

TPBHA

(PS) Address Hold Time

TPCHR

(PCS) R/W Hold Time

0

100

30

-

0

80

10

-

30

-

30

TpcHV

(PC4) EMS Hold Time

10

TpcVO (1)

(PC4) Address to EMS Delay Time

30

Tpcvp

(PC4) EMS Stabilization Time

30

-

30

TESU

EMS Setup Time

-

350

-

210

NOTE 1: Values assume FCO-PeS haw the same capaCitive load.

E.4.1 Multiplex Mode Timing Diagram
READ

WRITE I~------,

,--._--------

-

TPCHR

RIW
(PC5)

1 - - - -..
• TPCRS
EMS

_

(PC4)

TPCHV

TESU

TPCYD

Tpcvp

_ _ TPCHA4-

PCO-PC3

- - ..-- TPBHA

PBO-PB7
I
T pBAS

TPCVD

TPBHR

3-251

TpBHW

R6500/41 and R6500/42

One-Chip Intelligent Peripheral Controllers

E.S I/O, EDGE DETECT AND COUNTER TIMING
1 MHz

2 MHz

PARAMETER

SYMBOL

MAX

MIN

MAX

-

500
1000
175

-

500
1000
150

200
50

-

75
10

MIN
Internal Wnte to Peripheral Data Valid

Tpow 0)

-

PA, PC TIL
PA, PC CMOS
PB

TCMOS(1)

TpDOW

Penpheral Data Setup Time
PA,PC
PB

Tposu

Tpos u

-

-

200
50

-

-

75
10

-

Tcyc

-

Tc't'c

-

Tcyc

-

Tcyc

-

Peripheral Data Hold Time
T pHR
T"",

PA,PC
PB

TEPW

PAO·PAl Edge Detect Pulse Width

-

Counter
PA2 Input Pulse W,dth
PA2 Output Delay

Tcpw

Tco In

-

-

500

500

NOTE 1 Maximum load Capacitance 50pF Passive Pull·Up Required

E.S.1 1/0, Edge Detect, Counter

.
2

\

·k

Tcyc

.

1,5V

.J

I

Tposu
~

I'"

PAO-PA1
PBO-PB1
PCO-PC1

~

1.5V

.1

.-

'---,
TpHR

K

\

EDGE DET ECTS
(PAO-PA1)

./
T EPW

..

1.5V

1.5VJ

ll.5V

CNTR
PA2

Tcpw
TCD
CNTR
PA2

J
~

Tcpw
2.4V
O.4V

Tpoow

)t

PBO-PB1

I:

~I
I
~~_~~_+._-------------1--~

.-----=

PAO-PA1 ____________ Tpow'
PBO-PB1

PCO-PC6 - - - - - - - - - - -

2.4V

TCMOS

O.4V

3·252

VDD-30

R65/41EB. R65/41EAB
R6500 Microcomputer System

'1'

R65/41EB AND R65/41EAB
BACKPACK EMULATORS

Rockwell
INTRODUCTION

FEATURES

The Rockwell R65/41EB and R65/41EAB Backpack Emulator
is the PROM prototyping version of the 8-bit, masked-ROM
R6500/41 one-chip microcomputer. Like the R6500/41, the
backpack device is totally upward/downward compatible with all
members of the R6500/41 family. It is designed to accept standard 5-volt, 24-pin EPROMs or ROMs directly, in a socket on
top of the Emulator. This packaging concept allows a standard
EPROM to be easily removed, re-programmed, then reinserted
as often as desired.

• PROM version of the R6500/41
• All Host bus features of R6500/41
• Completely pin compatible with R6500/41 single-chip microcomputers
• Profile approaches 40-pln DIP of R6500/41
• Accepts 5 volt, 24-pin Industry-standard EPROMs
-4K memories-2732, 2732A
• Use as prototyplng tool or for low volume production
• 4K bytes of memory capacity

The backpack devices have the same pinouts as the maskedROM R6500/41 microcomputer. These 40 pins are functionally
and operationally Identical to the pins on the R6500/41. The
R6500/41 Microcomputer Product Description (Rockwell Document No. 29651N38, Order No. 2135) includes a description of
the interface signals and their functions. Whereas the maskedROM R6500/41 provides 1.5K bytes of read-only memory, the
R65/41 EB will address 4.0K bytes of external program memory.
This extra memory accommodates program patches, test programs or optional programs during breadboard and prototype
development states.

•
•
•
•

64 x 8 static RAM
Software compatibility with the R6500 family
23 bi-dlrectlonal TTL compatible I/O lines
16 bit programmable counter/latch With four modes (interval timer, pulse generator, event counter, pulse width
measurement)

• 7 interrupts (reset, two external edge sensitive, counter
underflow, Host data received, Output data register full, Input
data register empty).
• External time base
• Single +5V power supply

ORDERING INFORMATION
Backpack Emulator
Part
Number

Memory
Capacity

R65/41EB

4K x B

2732

O°C to 70°C
1MHz

R65/41EAB

4K x B

2732A

O°C to 70"C
2 MHz

Compatible
Memories

Temperature
Range and Speed

Support Products
Part
Number

S65-101
M65-Q40
M65-131
M65-132

RDC-1001
RDC-131
RDC-132

Description

SYSTEM 65 Microcomputer
Development System
PROM Programmer Module
1-M Hz R6500/41 Personality Module
2-MHz R6500/41 Personality Module
Rockwell Development Center
1 MHz R6500/41 Personality Set (RDC)
2 MHz R6500/41 Personality Set (RDC)

R65/41EB-R65/41EAP Backpack Emulator

Document No. 29001014
3-253

Data Sheet Order No. 0114
February 1983

Backpack Emulators

R65/41EB. R65/41EAB
CONFIGURATIONS

PRODUCT SUPPORT

The Backpack Emulator is available in two different versions,
to accommodate 1 MHz and 2 MHz speeds. Both versions
provide 192 bytes of RAM and VO, as well as 24 signals to
support the external memory "backpack" socket.

The Backpack Emulator is just one of the products that Rockwell offers to facilitate system and program development
for the R6500/41.
The SYSTEM 65 Microcomputer Development System with
R6500/41 PersonalHy Module supports both hardware and
software development. Complete in-circuH user emulation
with the R6500/41 Personality Module allows total system
test and evaluation. With the optional PROM Programmer,
SYSTEM 65 can also be used to program EPROMs for the
development activity. When PROM programs have been finalized, the PROM device can be sent to Rockwell for masking
into the 1.5K ROM of the R6500/41.

External 4K memories with addresses of 000 to FFF, are
upward translated to addresses FOOD to FFFF when assembled to form the Backpack Emulator.

EXTERNAL FREQUENCY REFERENCE
The external frequency reference is an output timing signal
~2. This is an internally synchronized 1 x clock output suitable for external memory or peripheral interfacing.

In addition to support products, Rockwell offers regularlyscheduled designer courses at regional centers.

1/0 PORT PULLUPS
The emulator devices have internal I/O port pullup resistors
on ports A and C. Port B has tri-state drivers.

CLKIN

VCC,VSS

PROM/

1-_ _ 8 _ _-,./

ROM

40 R6500/41
24 PROM/ROM
PINS

COMPATIBLE PINS

R65/41EB Interface Diagram

3-254

Backpack Emulators

R65/41EB. R65/41EAB
CS

Vcc
ClKIN
RES
PB7
PB6
PBS
PB4
PB3
PB2
PBl
PBO
PA7
PA6
PAS
PA4
PA3
PA2
PAl
PAO
Vss

E (RD)
RiW (WR)
RS (AO)
HDO
HDl
HD2
HD3
HD4
HDS
HD6
HD7

PCO
PCl

PC2
PC3
PC4
PCS
PC6
_2

BACKPACK MEMORY SIGNAL
DESCRIPTION
Signal
Name

Pin No.

00-07

98-118,
138-178

AO-A9
Al0,
All
CE
OE

18-88,
228,238
198,218
188
208

Vee

248

Vss

128

Description
Data Bus Lines. All instruction and data
transfers take place on the data bus lines.
The buffers driving the data bus lines have
full three-state capability. Each data bus
pin is connected to an input and an output
buffer, with the output buffer remaining in
the floating condition.
Address Bus Lines. The address bus lines
are buffered by push/pull type drivers that
can drive one standard TTL load.
Chip Enable.
Memory Enable Line. This signal provides
the output enable for the memory to place
Information on the data bus lines. This
signal IS driven by the Riw signal from the
CPU and then Inverted to form OE. This
signal is driven by the Inverted address line
All. The OE signal Will be low for
addresses greater than OFFF
Main Power 8upply +5V. This pin IS tied
directly to pin 40 (V cd.
81gnal and Power Ground (zero volts). ThiS
pin is tied directly to pin 21 (V ssl.

Pi n Configuration

(1) PIN 21 is Vcc for R6S/41EB or All for R6S/41EB

I/O AND INTERNAL REGISTER ADDRESSES
Address

I

Write

Read

--

001F
lE
10
lC

-Host 8tatus Flag Register

Host 8tatus Flag Register

--

--

Input Data Register (lOR)

Output Data Register (ODR)

--

--

lB
lA
19

Lower Counter
Lower Counter & Clear Flag (IFR5)

Lower Latch
Upper Latch/Transfer Latch to Counter & Clear Flag (lFR5)

18

Upper Counter

Upper Latch

17
16
15
14

---

Mode Control Register

Mode Control Register

--

--

13
12
11
10
03 thru OF
02
01
0000

----

--

Interrupt Enable Register
Interrupt Flag Register
Read "FF"

Interrupt Enable Register

-Clear Int Flag Bit

--

I

PortC
Port B
PortA

--

I

3-255

PortC
Port B
PortA

I

R65/41EB. R65/41EAB

Backpack Emulators

READ TIMING CHARACTERISTICS
1 MHz
Signal

Symbol

OE and CE setup time from CPU
Address setup time from CPU
Memory read access time

TOES
TAOS
T ACC

Data set up time

T DSU

Max.

Min.

Max.

Unit

-

225
225

-

-

140
140

us

700

-

315

-

Data hold time-Read

T HR

50
10

Address hold time

THA

30

OE and CE hold time

T HOE
Tcyc

30
10

Cycle Time

2 MHz

Min.

10.0

ns
ns

-

ns

35
10

-

ns

30

-

ns

30
0.5

10.(}

ns
p.s

READ TIMING WAVEFORMS
~

__________ TCYC ________~~

ADDRESS FROM
CPU
DATA FROM --+---+---+-_~
MEMORY
::-:C-""T-o _ _r-

ABBREVIATED BUS
MODE MEMORY MAP
FFFE

IRQ VECTOR

FF"

IRQ VECTOR

FFFC

RES VECTOR

FFe

RES VECTOR

FFr B
FAOO
FOO'

T

EMS (ACnVE LOW)

1

MULTIPLEXED BUS
MODE MEMORY MAP

FFB

ROM1.5K

,
INTERNAL
REGISTERS

ZONE FOR 16

PERIPHERAL
OEVtcE

r 1T
0010

ADDRESSES

INTERNAL RAM

110 AND REGISTERS

,
MEMORY
4096-128 BYTES

MULTIPLEXED

g;,~

INTERNAL RAM
(64 BYTES)

-

UNASSIGNED

-

INTERNAL

0002

I/O PORTS A, B, C

..100

'Not available for masked ROM R65oo/41.

°tF
,,

,

INTERNAL
I/O AND REGISTERS

'Not available for masked ROM R6500/41

3-256

'r
0010

DATA AND ADDRESS
BUS

..I..

,

INTERNAL
REGISTERS

EXTERNAL

EMs (ACTIVE LOW)

(64 BYTES)

UNASSIGNED

EXTENDED
ROM (25K)*

OFFF

OFFF

INTERNAL

AiDM 15K

I

AOO

EXTENDED
ROM (25K)*

-

INTERNAL
I/O PORTS A, B. C

R65oo/42 ONL V

'r

'000

Backpack Emulators

R65/41EB. R65/41EAB
ELECTRICAL CHARACTERISTICS
= 5.0 ± 5%, Vss = 0, T A = 25°C)

(Vee

Characteristic

Symbol

Min

Input High Threshold Vo~age
DO-D7

V ,HT

Input Low Threshold Voltage
DO-D7

V ,LT

Three-State (Off State) Input Current
(V = 0.4 to 2.4V, Vcc = 5.25V)
DO-D7

I TSI

Output High Voltage
(I LOAD = 1001" Adc,.;!s.c = 4.75V)
DO-D7, AO-A11 , OE, CE

VOH

Output Low Vo~age
(ILOAD = 1.6 mAdc, Vcc = 4.75V)
DO-D7, AO-A11, 'O'E, CE

VOL

Power Dissipation (less EPROM)

Po

Capacitance
(V,n = 0, TA = 25°C, f = 1 MHz)
DO-D7 (High Impedance State)
Input Capacitance

C

Cout
Con

-

VO Port Pull-up Resistance

RL

3.0

Vss

+ 2.0

-

Typ

Max

Unit

-

-

Vdc

-

Vss

-

-

+ 2.4

-

-

-

-

0.50

± 10

Vss

n
I
,

-

Vdc

+ 0.4
-

W

Vdc

10
10

6.0

11.5

i

I

~

000000000000

20

1---------2020MAX--------I

I

DOSO:!: 020

----1220MAX----1

~t~ ~~ l_o~~a_1

1.~:

,~~ ~~II--l-____11--10
-

-

pF

21

1__

Vdc
I"A

Vss

~-

+ 0.8

I...

OSO:!: 015 BOTH ENDS

-01OO:!: 010 TYP

..

jl__ ~O:3
1 ~yp

REF

40-Pin Backpack Package
3-257

...

-- 0 0..0 ~

gg~ TYP

I

0125

MIN

kohm

R6541 Q • R6500/43

'1'

Rockwell

R6541Q AND R6500/43
INTELLIGENT PERIPHERAL CONTROLLERS

SECTION 1
INTRODUCTION
1.1 FEATURES
• Directly compatible with 6500, 6800, 8080, and Z80 bus
families
• Asynchronous Host interlace that allows independent clock
operation

• Unmultiplexed Address and Data buses for 4K of Peripheral I/O expansion
• 68% of the instructions are executed In less than 2,",s @
2 MHz
• NMOS-3 silicon gate, depletion load technology

• Input, Output and Status Registers for CPU/Host data
transfer

• Single +5V power supply

• Status register for CPU/Host data transfer operations

• 64-pin QUIP

• Interrupt or polled data Interchange with Host
• Enhanced 6502 CPU
• Four new bit manipulation instructions

NOTE
This document describes both the R6541Q and
R6500/43. In the text, the terms IPC or device will be
used when describing both parts. See Section 1.3 for
a description of the options available for the R6500/43
and the fixed features of the R6541Q.

• Set Memory Bit (SMB)
• Reset Memory Bit (RMB)
• Branch on Bit Set (BBS)
• Branch on Bit Reset (BBR)
• Decimal and binary arithmetic modes
• 13 addressing modes
• True indexing
• 256-byte mask-programmable ROM*

1.2 SUMMARY

• 64-byte static RAM
• 23 TTL-compatible I/O lines
• A 16-bit programmable counter/timer, with latch
• Pulse width measurement

The Rockwell R6541Q and R6500/43 One-Chip Intelligent
Peripheral Controllers (IPC) are general purpose, programmable interlace I/O devices designed for use with a variety
of 8-bit and 16-bit microprocessor systems. They have an
enhanced R6502 CPU, an optional 256 by 8-bit ROM, 64 by
8-bit RAM, three 1(0 ports with multiplexed special functions,
a multi-function timer, and a full 4K address and data buses
all contained within a 64-pin Quad-in-line package.

• Pulse generation
• Interval timer
• Event counter
• Eight interrupts
• Two edge-sensitive lines; one positive, one negative
•
•
•
•
•

In both versions, special interface registers allow these IPC
devices to function as peripheral controllers for the 6500,
6800, Z80, 8080, and other 8-bit or 16-bit host microcomputer systems.

Reset
Counter Underllow
Host data received
Output Data Register full
Input Data Register empty

The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction simplicity,
results in system cost-effectiveness and a wide range of
computational power. These features make the device a
leading candidate for IPC computer applications.

• Non-maskable
• Multiplexed bus expandable to 4K bytes of ex1ernal memory
* R6541 Q has no ROM.

Document No. 29651 N39
3-258

Product Description Order No. 2136
Rev. 2, October 1984

Intelligent Peripheral Controllers

R6541 Q and R6500/43

• Without ROM

Rockwell supports development of the R6541 Q and R6500/43
with the System 65 Microcomputer Development System and
the R65001* Family of Personality Modules. Complete
in-circuit emulation with the R6500/" Family of Personality
Modules allows total system test and evaluation.

• Reset Vector at FFFC
• No internal pull-up resistors on any Port (PA or PC)

elK CIRCUIT

This product description assumes that the reader is familiar
with the R6502 CPU hardware and programming capabilities.
A detailed description of the R6502 CPU hardware is included
in the R6500 Microcomputer System Hardware Manual
(Document Order Number 201). A descrption of the instruction capabilities of the R6502 CPU is contained in the R6500
Microcomputer System Programming Manual (Document
Order Number 202).

INT LOGIC

I I

STATUS REG

6502 CPU

I I

PORT A

64 BYTES RAM

I I

PORT B

256 BYTES ROM

I I

PSG-PS7
{DO-07,

I

CONTROL

(11.0, At 11.2, 11.3,
EMS, A/W, INT)'

A~G_J

INPUT DATA

I I

REG

OUTPUT DATA
REG

1 with or without a 256 byte ROM
2 Reset Vector at FFFC or OFFC
3 Port A with or without Internal pull-up resistors
4 Port C with or without internal pull-up resistors

Figure 2-1.

Interface Diagram

,,.

/381 MM)

A4

A3
A'
A'
AO

59~A11
A15
57
RES
58

NMi

SYNC

56

RNi

55
54

cs

12

RS(AO)
HBO

15
16

R6541Q

HBt

17

HB2
HB3
HB4
HBS

16
19
20
21
22

R6500143

.1~~::
HB~

.

~PB7

51

PB2

~~~::b

48 t:J

OB7
47 ~DB6
46
085
45
DB4
44p
OB3
43
DB2

: Lt: g::

27

38

PAS

37
36
35
34
33

PA4
PA3
PA'
PA,
PAo

25
28

"

30
31

32

I

PBS
PBS

53~PB4
52
P~3

26

H_~d~~
PCS
PCS
PC4
PC3
PC'
PC'
PCO
V"

-£-1

Voo
A7
A8

;6 ~ ~~o

elKIN

40

PA7

39

PAS

-I

Ii

'"

<3

g

i

. ill
g ~

-£--

_cr.J..1
(~sg7~=1 J
TVP

R6541Q & R6500/43 Pin Out Designation (64 PIN QUIP)

Figure 2-3.

R6541Q & R6500/43 Dimensional Outline
3-259

I'-

IIT1

I
I

1628
(4135 MM)

1-4-(17 ::~M) ~
Figure 2-2.

R/W
AO-Al', A1S

.... Sy~C

The R6541 Q has no customer specified mask options. It has
the following characteristics.

64

..

DBO-OB7

• MULTIFUNCTION PINS

63
62

-..,2
==>

All options should be specified on an R6500/43 order form.

A6
A'

(PAo-PED)
(PAt-NED)
(PAa-eNTRI

pea-pee

1_3 CUSTOMER OPTIONS

Option
Option
Option
Option

EDGE DETECT
PAD-PA7

The R6500/43 microcomputer is available with the following
customer specified mask options.
•
•
•
•

I I

I
I
!

i

:

I

_.1.

020 RE;f
TVP

0

Intelligent Peripheral Controllers

R6541 Q and R6500/43

SECTION 2
INTERFACE REQUIREMENTS
This section describes the interface requirements for the Intelligent Peripheral Controller. Figure 2-1 is the Interface Diagram for the devices. Figure 2-2 shows the pin out configuration and Table 2-1 describes the function of each pin of the
Table 2-1.
PIN NO.
SIGNAL NAME R6541Q & R6500/43
ClKIN

devices. Figure 2-3 shows the mechanical dimensions of the
devices. Section 5 describes the Host computer interface
protocol and timing requirements.
Pin Description
PIN NO.
R6541Q & R6500/43

DESCRIPTION

SIGNAL NAME

11

Symmetrical square wave
100 KHz to 2 MHZ, TTL compatible input.

PBO-PB7

49-56

24

Output timing signal-This is
an internally synchronized
1 x clock output suitable for
external memory or peripheral interfacing.

57

The reset input is used to initialize the device. Section 7
deSCribes the process and
conditions of the RES procedure.

8 bit I/O port used for either
input or output. Each line
consists of an active transistor to Vss and an active pullup to Vee. This port becomes
a tri-state data bus, 00-07,
in the Abbreviated or Multiplexed Bus Mode. 00-07 are
multiplexed with address lines
A4-A11 in the Multiplexed
Bus Mode.

PCO-PC6

31-25

7 bit I/O port used for either
Input or output. Each line
consists of an active transistor to V 55 and an optional
passive pull-up to Vee. The
PinS PCO to PC5 are multiplexed with address and
control signals for use in
abbreViated and multiplex
modes. PC6 is multiplexed
with INT and is program selectable. In these two modes
PCO-PC5 have active pullups.

AO-A11 , A15

7-1
63-58

Thirteen address lines used
to address a complete 8K
external address space.

DBO-DB7

41-48

Eight bidirectional data bus
lines used to transmit data to
and from external memory.

VCC

64

VSS

32

Power supply input (+5V)
Signal and power ground
(OV).

RS (AD)

HBO-HB7

PAO-PA7

12

Chip select pin for host Interface.

15

Register select Input pin used
by the Host processor to indicate that information being
written Into the IPC IS a data
or command byte or to indicate that Information being
read from the IPC IS a status
or data byte.

13

Host timing control signal for
data register write and read.

14

Host timing control Signal for
data register write and read.

16-23

Data bus between Host and
IPC data Input and output
registers.

8

A negative going edge on the
Non-Maskable Interrupt signal requests that a nonmaskable Interrupt be generated With the CPU.

33-40

8 bit I/O port used for either
Input or output. Each line
consists of an active transIstor to V 55 and an optional
passive pull-up to Vee. The
two lower bits PAD and PA1
also serve as edge detect inputs. PA2 is time shared With
the 16 bit Counter Input or
output pin, CNTR, and is
mode selected.

SYNC

3-260

DESCRIPTION

9

SYNC is a positive going signal for the full clock cycle
whenever the CPU is performing an OP CODE fetch.

10

Controls the direction of data
transfer between the CPU
and the external 65K address space. The signal is
high when reading and low
when Writing.

Intelligent Peripheral Controllers

R6541 Q and R6500/43

SECTION 3
SYSTEM ARCHITECTURE
This section provides a functional description of the IPC device. Functionally, the device consists of a CPU, RAM and
optional ROM memories, three parallel I/O ports (actually 23
I/O lines), counter/latch circuit, a mode control register, and
an interrupt flag/enable dual register circuit. A block diagram
of the system is shown in Figure 3-1.

data are to be pushed onto the stack, the Stack Pointer IS
placed on the Address Bus, data are written Into the memory
location addressed by the Stack POinter, and the Stack
POinter IS decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack POinter IS incremented by
1. The Stack POinter IS then placed on the Address Bus, and
data are read from the memory location addressed by the
POinter.

NOTE

Throughout this document, unless specified otherwise,
all memory or register address locations are specified
In hexadecimal notation.

The stack IS located on zero page, I.e., memory locabons
007F-0040. Normal usage calls for the Initialization of the
Stack POinter at 007F

3.1 CPU LOGIC

3.1.4 Arithmetic and Logic Unit (ALU)

The Internal CPU of the device IS an enhanced R6502 configuration with an 8-blt Accumulator register, two 8-blt Index
Registers (X and Y), an 8-blt Stack POinter register, an AlU,
a 16-blt Program Counter, and standard instruction reglster/
decode and internal timing control logic.

All arithmetiC and logic operations take place In the AlU, including incrementing and decrementing Internal registers
(except the Program Counter) The AlU cannot store data
for more than one cycle If data are placed on the Inputs to
the AlU at the beginning of a cycle, the result IS always gated
Into one of the storage registers or to external memory dUring
the next cycle.

3.1.1 Accumulator
The accumulator IS a general purpose 8-blt register that
stores the results of most arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used In these operations.

Each bit of the AlU has two Inputs. These Inputs can be lied
to variOus Internal buses or to a logic zero; the AlU then
generates the function (AND, OR, SUM, and so on) uSing
the data on the two inputs

3.1.2 Index Registers

3.1.5 Program Counter

There are two 8-blt index registers, X and Y. Each Index register can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the index register contents.

The 16-blt Program Counter provides the addresses that are
used to step the processor through sequential InstrucllOns
In a program. Each time the processor fetches an instruction
from program memory, the lower (least significant) byte of
the Program Counter (PCl) IS placed on the low-order bits
of the Address Bus and the higher (most significant) byte of
the Program Counter (PCH) IS placed on the high-order 8
bits of the Address Bus. The Counter IS Incremented each
time an Instruction or data IS fetched from program memory.

When executing an Instruction which specifies Indirect addressing, the CPU fetches the op code and the address, and
modifies the address from memory by adding the Index regi!ller to It prior to loading or storing the value of memory.
Indexing greatly simplifies many types of programs, especially those uSing data tables.

3.1.6 Instruction Register and Instruction Decode
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These Instructions are latched into the
Instruction Register then decoded along With timing and interrupt signals to generate control signals for the various
registers.

3.1.3 Stack Pointer
The Stack POinter IS an 8-bit register. It is automatically Incremented and decremented under control of the microprocessor to perform stack manipulation In response to either
user instructions, or an Internal IRQ Interrupt. The Stack
POinter must be initialized by the user program.

3.1.7 Timing Control
The Timing Control logic keeps track of the specific instruction cycle being executed. This logic IS Initialized each time
an instruction letch is executed and's advanced at the beginning of each low level of the Clock In pulse for as many
cycles as are required to complete the instruction. Each data
transfer which takes place between the registers IS caused
by decoding the contents of both the instruction register and
timing control Unit.

The stack allows simple Implementation of multiple level Interrupts, subroutine nesting and simplification 01 many types
of data manipulation. The JSR, BRK, RTI and RTS instructions use the stack and Stack Pointer.
The stack can be envIsioned as a deck of cards which may
only be accessed from the top. The address of a memory
location IS stored (or "pushed") onto the stack. Each time
3-261

::D

en
en

..

C
CPU,I-IOST
CONTROL
LOGIC

RS(A

RrW(W
E

(1'1
.t:.

A

y'-HBO-HB7

'"

'"
0>

I\)

RiW

r-

r-

SYNC

l-

NMI

-+
-+

CLKIN

P2

f--

RES

......

k

~

r--v rv-

CPU,I-IOST
STATUS
REGISTER

OUTPUT
DATA
REGISTER

l;t- I-

~

Vt--r\
j\r-v'

-+

Vss

......

~j,

t

INTERUPT
FLAG
REGISTER

MODE
CONTROL
REGISTER

II:

I--

~
V

INPUT
DATA
REGISTER

f-

ft\

--.--J

f-~

I+-

C)

INT
PORTC

j

z

U
;1--1\lA- J\
v--v

I'c

~

l;Lt\ ~

rv-v r-r-

t---

~
[\rlI'--

"\t
~'~PCO-PC6
(AO-A3, EMS, R/W, INT)'

w

Q.

::D

f--

en
en
Q

~
Co)

64 X
RAM

s

256 X S
ROM

()

I

INTERNAL DATA BUS

w

0

Vee

16 BIT
COUNTER/
LATCH

INTERUPT
ENABLE
REGISTER

I»
::::J

6502 CPU
WITH BIT MANIPULATION
INSTRUCTION ADDED

~

Vi- ~ VU\
~ rv i'rV
I-

~
.....

D

~t
PORTA

~:c

~~

::::J

DATA

cE"

CD

PORT B

1st

i,1

PAO-PA7

PBO-PB7

PAO-POS EDGE)"
( PAl-NEG EDGE
PA2-CNTR

~

( 00-07) "
A4-All

"MULTIPLEXED SIGNALS

lsr
DBD-DB7

CD
::::J

I/O

."

l3f--

'"

AD-All, A15

CD

'"'I

-6"

::T
CD
'"'I

!!.

o

o

::::J
' "'I

Figure 3-1.

R6541Q & R6500/43 Block Diagram

2CD
'"'I

til

Intelligent Peripheral Controllers

R6541 Q and R6500/43
3.1.8 Interrupt Logic

3.4 RANDOM ACCESS MEMORY (RAM)

Interrupt logic controls the sequencing of three interrupts:
RES, NMI, and IRQ. IRQ is generated by anyone of four
conditions: Counter Overflow, Positive Edge Detect, Negative Edge Detect, and Input Data Register Full.

The RAM consists of 64 bytes of read/wnte memory With an
assigned page zero address of 0040 through 007F.

3.5 SYSTEM CLOCK
The deVice functions With an external clock. It IS fully asynchronous in reference to the Host computer timing. The device clock frequency equals the external clock frequency. It
is also made available for any external deVice synchrOnization at pin ~2.

3.2 NEW INSTRUCTIONS
In addition to the standard 6502 instruction set, four instructions have been added to the devices to simplify operations
that previously required a read/modify/write operation. In order for these Instructions to be equally applicable to any I/O
ports, with or Without mixed Input and output functions, the
I/O ports have been designed to read the contents of the
specified port data register dUring the Read cycle of the read/
modify/write operation, rather than I/O pins as In normal read
cycles. The added Instructions and their format are explained
In the follOWing subparagraphs. Refer to Appendix A for the
Op Code mnemonic addressing matnx for these added
instructions.

3.6 MODE CONTROL REGISTER (MCR)
The Mode Control Register contains control bits for the multifunction I/O ports and mode select bits for the Counter, the
6500 or 8080 Bus Select, and the Interrupt (INT). Its setting
determines the basic configuration of the deVice In any application. InitialiZing thiS register IS one of the first actions of
any software program. The Mode Control Register bit assignment IS shown In Figure 3-2.

3.2.1 Set Memory Bit (SMB m, Addr.)

The use of Counter A Mode Select IS shown In Section 6

This Instruction sets to "1" one of the 8-blt data field speCified
by the zero page address (memory or I/O port). The first byte
of the instruction speCifies the 5MB operation and 1 of 8 bits
to be set. The second byte of the instruction designates address (OO-FF) of the byte or I/O port to be operated upon.

The use of the 6500/8080 Host Bus Select IS shown
tion 6

In

Sec-

The use of Interrupt Select IS shown In SecliOn 4.5.

3.2.2 Reset Memory Bit (RMB m, Addr.)

The use of Bus Mode Select IS shown
4.5.

ThiS Instruction IS the same operation and format as 5MB
Instruction except a reset to "0" of the bit results.

In

Sections 4 4 and

3.2.3 Branch on Bit Set Relative (BBS m, Addr,
DEST)
ThiS instruction tests one of 8 bits designated by a three bit
immediate field Within the first byte of the instruction. The
second byte IS used to designate the address of the byte to
be tested within the zero page address range (memory or
I/O ports). The third byte of the instruction IS used to speCify
the 8 bit relative address to which the Instruction branches
If the bit tested IS a "1 ". If the bit tested IS not set, th8 next
sequential Instruction IS executed.

~CR

,...--,...--r--r--r--r--r--r----.

AODR 0014

COUNTER

3.2.4 Branch On Bit Reset Relative (BBR m,

SELECT MOOE
BUS MODE
SELECT

Addr, DEST)

NOT USED

This instruction IS the same operation and format as the BBS
instruction except that a branch takes place if the bit tested
is a "0".

1

BUS SELECT
= 6500/6800 BUS

o

1 "" Z80/8080 BUS

~
INTERVAL TIMER
PULSE GENERATOR
EVENT COUNTER
PULSE WIDTH
MEASUREMENT

INT SELECT

0= PC6

3.3 READ-ONL Y-MEMORY (ROM)

1

The optional ROM consists of 256 bytes mask programmable
memory with an address space from OFOO to OFFF. ROM
locations FFFA through FFFF are assigned for Interrupt vectors. The Reset vector can be optionally at OFFC or FFFC.

o

1
1

The R6541 Q has no ROM and its reset vector is at FFFC.

iNT

PORT B ALL INPUTS

1 PORT B ALL OUTPUTS
0 ABBREVIATED BUS MODE
1 MULTIPLEXED 8US MODE

Figure 3-2.

3-263

=

Mode Control Register Bit Allocations

9

Intelligent Peripheral Controllers

R6541 Q and R6500/43

3.7 INTERRUPT FLAG REGISTER (IFR)
AND INTERRUPT ENABLE
REGISTER (IER)

ADDR 0012

An IRQ Interrupt request can be Initiated by any or all of four
possible sources, These sources are all capable of being
enabled or disabled by the use of the appropnate interrupt
enabled bits In the Interrupt Enable Register (IER). Multiple
Simultaneous Interrupts will cause the IRQ Interrupt request
to remain active until all interrupting conditions have been
serViced and cleared,

ADDR 0011

PAO POSITIVE
EDGE DETECT
INTERRUPT ENABLE
PAl NEGATIVE
EDGE DETECT
INTERRUPT ENABLE

The Interrupt Flag Register contains the Information that Indicates which I/O or counter needs attention, The contents
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011, Edge detect IFR bits may be
cleared by executing a RMB Instruction at address location
0010, The RMB X, (0010) instruction reads FF, modifies bit
X to a "0", and wntes the modified value at address location
0011, In thiS way IFR bits set to a "1" after the read cycle of
a Read-Modlfy-Wnte instruction (such as RMB) are protected
from being cleared, IFR bits 6 and 7 are Indeterminate on a
Read.

INTERNAL INTERRUPT
REQUEST. IRQ ENABLE
EXTERNAL INTERRUPTS REQUEST 1,
INT-l ENABLE
EXTERNAL INTERRUPT REQUEST 2,
INT-2 ENABLE
COUNTER UNDERFLOW
INTERRUPT ENABLE

Figure 3-3.

Interrupt Enable and Flat Registers

Table 3-1.

Interrupt Enable Signals

Control Signal

Description

IER 0

Positive Edge Detect, Interrupt Enablewhen this bit IS true, a positive gOing sig·
nal on PAO Will generate an IRQ and set
the corresponding flag bit.

IER 1

Negative Edge Detect Interrupt Enablewhen this bit IS set to a "1" a negative
gOing signal on PAl Will generate an IRQ
and set the corresponding flag bit.

IER 2

3.7.1 External Interrupts (INT)
An external Interrupt INT to the Host computer may be selected in two modes. (See Section 5 for Information on the
Host/DeVice Interface),

Input Data Register Full Interrupt Ena·
ble-settlng this bit to a "1" allows an
IRQ to be generated each time the Host
fills the lOR setting the IDFR bit.

IER 3

Output Data Register Full Interrupt Enable-when this bit IS an Interrupt request
to the Host IS generated each time the
ODRF flag IS set to a "1". (See External
Interrupts, Paragraph 3,7,1) Reading the
ODR clears INT-l and ODRF flags,

IER 4

Input Data Register Empty Interrupt Enable-when thiS IS set to a "1" an Interrupt IS generated to the Host each time
the lOR IS read by the CPU, The Interrupt
occurs when the IDRF flag IS cleared,
INT-2 IS cleared when the Host reads the
status flag register. (See External Interrupts, Paragraph 3,7,1),

IER 5

Each IFR bit has a corresponding bit In the Interrupt Enable
Register which can be set to a "1" by wntlng a "1" in the respective bit pOSItion at location 0012, IndiVidual IER bits may
be cleared by writing a "0" In the respective bit POSition, or
by RES, If set to a "1", an IRQ Will be generated when the
corresponding IFR bit becomes true, The Interrupt Flag RegIster and Interrupt Enable Register bit assignments are shown
In Figure 3-3 and the functions of each bit are explained In
Table 3-1,

OUTPUT DATA REGISTER (ODR) FULL
When IER 3 of the Interrupt Enable Register is set to a "1",
the deVice Will assert the INT (PC6) line each time It loads
the ODR. The ODRF flag of the Status Flag Register and the
IFR 3 of the IFR Will be set to a 'T indicating the ODR IS full,
The ODRF and IFR 3 flags are cleared and INT is negated
when the Host processor reads the ODR.

INPUT DATA REGISTER (lOR) EMPTY
When IER 4 of the Interrupt Enable Register IS set to a "1",
the device Will assert the INT (PC6) line each time it reads
the lOR. The IDRF flag of the Host Status Flag Register Will
be cleared and the IFR 4 flag of the IFR Will be set to a "1"
indicating the lOR has just been read by the deVice. The IFR
4 flag is cleared and INT is negated when the Host processor
reads the Host Status Flag Register, RES clears the lOR and
sets the IFR4 flag to Indicate the register IS empty,

Counter Interrupt Enable-If enabled, an
IRQ IS generated whenever the Counter
overilows.
3-264

R6541 Q and R6500/43

Intelligent Peripheral Controllers

3.8 PROCESSOR STATUS REGISTER

zero. This bit is cleared to logic 0 when the resultant a bits
of a data movement or calculation operation are not all zero.
The R6502 instruction set contains no instruction to specifically set or clear the Zero Bit. The Zero Bit is, however, affected by the following instructions; ADC, AND, ASL, BIT,
CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY,
LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TYA.

The a-bit Processor Status Register, shown in Figure 3-4,
contains seven status flags. Some of these flags are controlled by the user program; others may be controlled both
by the user's program and the CPU. The R6502 instruction
set contains a number of conditional branch instructions
which are designed to allow testing of these flags. Each of
the eight processor status flags is described in the following
sections.

3.8.3 Interrupt Disable Bit (I)

3.8.1 Carry Bit (C)

The Interrupt Disable Bit (I) is used to control the servicing
of a!!..!!!terrupt request (IRQ). If the I Bit is reset to logic 0,
the IRQ signal will be serviced. If the bit is set to logic 1, the
IRQ signal Will be ignored. The CP~ill set the Interrupt
Disable B!!J2 logic 1 if a RESET (RES) or Non-Maskable
Interrupt (NMI) signal is detected.

The Carry Bit (C) can be considered as the ninth bit of an
arithmetic operation. It is set to logic 1 if a carry from the
eighth bit has occurred or cleared to logic 0 if no carry occurred as the result of arithmetic operations.
The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Clear Carry (CLC) instruction, respectively. Other operations which affect the Carry Bit
are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, ROR, RTI,
and SBC.

The I bit is cleared by the Clear Interrupt Mask Instruction
(CLI) and IS set by the Set Interrupt Mask Instruction (SEI).
This bit may also be set by the BRK Instruction. The Return
from Interrupt (RTI) and Pull Processor Status (PLP) instructions Will also affect the I bit.

3.8.2 Zero Bit (Z)
The Zero Bit (Z) is set to logic 1 by the CPU during any data
movement or calculation which sets all a bits of the result to
7

6

5

4

3

o

2

INIVllBIDlllZTCl

~ CARRY (C) (1)
1

~

o~

Carry Set
Carry Clear

Zero (2) (1)
1
o

~
~

Zero Result
Non-Zero Result

INTERRUPT DISABLE (I) (2)
1

~

o~

IRQ Interrupt Disabled
IRQ Interrupt Enabled

DECIMAL MODE (D) (1)
1

~

o~

Decimal Mode
Binary Mode

BREAK COMMAND (B) (1)
1
o

~
~

Break Command
Non-Break Command

OVERFLOW (0) (1)
1
o

~
~

Overflow Set
Overflow Clear

NEGATIVE (N) (1)
NOTES
(1) Not initialized by RES
(2) Set to Logic 1 by RES

Figure 3-4.

1

~

o~

Negative Value
Positive Value

Processor Status Register
3-265

9

Intelligent Peripheral Controllers

R6541 Q and R6500/43
3.8.4 Decimal Mode Bit (D)

ThiS indicator only has meaning when signed arithmetiC (sign
and seven magnitude bits) IS performed. When the ADC or
SBC instruction is performed, the Overflow Bit is set to logic
1 if the polarity of the sign bit (bit 7) is changed because the
result exceeds + 127 or -128; otherwise the bit is cleared
to logiC 0. The V bit may also be cleared by the programmer
using a Clear Overflow (CLV) instruction.

The Decimal Mode Bit (D), is used to control the arithmetic
mode of the CPU. When this bit is set to logic 1, the adder
operates as a decimal adder. When this bit is cleared to logic
0, the adder operates as a straight binary adder. The adder
mode is controlled only by the programmer. The Set Decimal
Mode (SED) Instruction Will set the 0 bit; the Clear DeCimal
Mode (CLD) instruction Will clear It. The PLP and RTI instructions also effect the Decimal Mode Bit.

The Overflow Bit may also be used with the BIT instruction.
The BIT instruction which may be used to sample Interface
devices, allows the overflow flag to reflect the condition of bit
6 In the sampled field. During a BIT Instruction the Overflow
Bit is set equal to the content of the bit 6 on the data tested
with BIT instrction. When used In thiS mode, the overflow has
nothing to do with signed arithmetic, but is just another sense
bit for the microprocessor. Instructions which affect the V flag
are ADC, BIT, CLV, PLP, RTI and SBC.

CAUTION
The Decimal Mode Bit will either set or clear in an unpredictable manner upon power application to the device. ThiS bit must be initialized to the desired state by
the user program or erroneous results may occur.

3.8.5 Break Bit (B)

3.8.7 Negative Bit (N)

The Break Bit (B) IS used to determine the condition which
caused the IRQ service routine to be entered. If the IRQ service routine was entered because the CPU executed a BRK
command, the Break Bit Will be set to logiC 1. If the IRQ routine was entered as. the result of an IRQ signal being generated, the B bit will be cleared to logiC 0. There are no instructions which can set or clear this bit.

The Negative Bit (N) IS used to indicate that the sign bit (bit
7), In the resulting value of a data movement or data arithmetic operation, IS set to logic 1. If the sign bit is set to logiC
1, the resulting value of the data movement or arithmetic
operation is negative; If the sign bit IS cleared, the result of
the data movement or arithmetiC operation IS positive. There
are no instructions that set or clear the Negative Bit since the
Negative Bit represents only the status of a result. The instructions that effect the state of the Negative Bit are: ADC,
AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EOR,
INC, INX, INY, LOA, LOX, LOY, LSR, ORA, PLA, PLP, ROL,
ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TYA.

3.8.6 Overflow Bit (V)
The Overflow Bit (V) IS used to Indicate that the result of a
signed, binary addition, or subtraction, operation IS a value
that cannot be contained In seven bits (-128 ~ n ~ 127).

3-266

Intelligent Peripheral Controllers

R6541 Q and R6500/43

SECTION 4
PARALLEL INPUT/OUTPUT PORTS
(>2.0V) input will cause a logic 1 to be read. An RES signal
forces all 1/0 port registers to logic 1 thus initially treating all
1/0 lines as inputs.

INPUT/OUTPUT PORTS
The IPC device provides three ports (PA, PB, and PC). The
15 lines of PA and PC are completely bidirectional, that is,
there is no line grouping or port association restnctions.
The eight lines of Port B may be programmed as all inputs
or all outputs. Port PC, however, may be multiplexed under
program control with seven other signals. SIX of these signals
form an address and control bus for extended addressing.
The seventh signal is multiplexed with an external interrupt
output, INT. All eight Port B lines are tri-state to permit their
use as a data bus dunng extended addressing modes.

Port B may be all inputs or all outputs. All inputs is selected
by setting bits MCR6 and MCR? of the Mode Control Register to a "0".
The status of the Input hnes can be Interrogated at any time
by reading the 1/0 port addresses. Note that this will return
the actual status of the input lines, not the data written into
the 1/0 port registers.

Internal pull-up resistors (FET's with an impedance range of
3K", Rpu '" 12K ohm) may be provided on ports PA andlor
PC. The R6541Q does not have these resistors.

Read/ModifyIWrite instructions can be used to modify the operation of PA, PB, PC, and also PF, & PG of an emulated
R6500/42. During the Read cycle of a ReadlModifylWrite
instruction the Port I/O register is read. For all other read Instructions the port input lines are read. Read/ModifyIWrite Instructions are: ASL, BBS, BBR, DEC, INC, LSR, RMB, ROL, ROR,
and 5MB.

The direction of the 1/0 lines are controlled by 8-bit port regIsters located In page zero. This arrangement provides quick
programming access using simple two-byte zero page address Instructions. There are no direction registers associated with the 1/0 ports, which simplifies 1/0 handling. The
1/0 addresses are shown in Table 4-1. If a part is being
used to emulate a R6500/42 the ports must be provided in
external circuitry and addressed through locations 00040006.

4.2 OUTPUTS
Outputs for Ports A thru C, and emulated Ports E thru G of
the R6500/42, are controlled by writing the desired 1/0 line
output states into the corresponding 1/0 port register bit positions. A logic 1 will force a high (>2.4V) output while a logic
will force a low «0.4V) output. Port B also requires that
MCR6 be set to a "1" and MCR? be set to a "0".

o

Table 4-1. 1/0 Port Addresses
PORT

ADDRESS

A

0000
0001
0002
0004
0005
OOOS

B

C
E
F
G

}RS500/42 only

4.3 PORT A (PA)
Port A can be programmed via the Mode Control Register
(MCR) as a standard parallel 8-bit, bit independent, 1/0 port,
or a counter 1/0 line. Table 4-2 tabulates the control and
usage of Port A.
In addition to their normal I/O functions, PAO can detect positive going edges, and PA1 can detect negative going edges.
An edge transition on these pins will set a corresponding
status bit in the IFR and generate an interrupt request if the
respective Interrupt Enable Bit is set. The maximum rate at
which an edge can be detected is one-half the ~2 clock rate.
Edge detection timing is shown in Section E.5.

4.1 INPUTS
Inputs for Ports A and C, and also Ports F and G if emulating
the R6500/42, are enabled by loading logic 1 Into all 1/0 port
register bit positions that are to correspond to I/O input lines.
A low «0.8V) input signal will cause a logic 0 to be read
when a read instruction is issued to the port register. A high

Table 4-2.
PA~PA11/0

Port A Control & Usage
MCRO = 1
MCR1 = 0

MCRO = 0
MCR1 = 0
SIGNAL

PA3-PA71/0

PA2 COUNTER

PA21/0

SIGNAL

SIGNAL

MCRD - X
MCR1 = 1
SIGNAL

SIGNAL

NAME

TYPE

NAME

TYPE

NAME

TYPE

NAME

TYPE

NAME

TYPE

PAO(l)
PAl (2)

liD

PA2

I/O

CNTR

OUTPUT

CNTR

INPUT (3)

PA3-PA7

liD

I/O

(1) POSITIVE EDGE DETECT

(2) NEGATIVE EDGE DETECT (3) HARDWARE BUFFER FLOAT
3-267

Intelligent Peripheral Controllers

R6541 Q and R6500/43
4.4 PORT B (PB)

4.5 PORT C (PC)

Port B can be programmed as an I/O Port, an 8-bit tri-state
data bus, or as a multiplexed bus. Mode selection for Port
B is made by the Mode Control Register (MCR). The Port B
output drivers can be selected as tri-state output drivers by
setting bit 7 of the MCR to 0 (zero) and bit 6 of the MCR to
1. An all inputs condition is created by setting both MCR6
and MCR7 to 0 (zero). Table 4-3 shows the necessary settings for the MCR to achieve the various modes for Port B.
When Port B IS selected to operate in the Abbreviated Mode
PSO-PB7 serves as data register bits 00-07. When Port B
is selected to operate in the Multiplexed Mode data bits 00
through 07 are time multiplexed with address bits A4 through
A11, respectively. Refer to the Memory Maps (Appendix B)
for Abbreviated and Multiplexed memory assignments. See
Appendix E.3 through E.5 for Port B timing.

Port C can be programmed as an I/O port and in conjunction
with Port B, as an abbreviated bus, or as a multiplexed bus.
When used in the abbreviated or multiplexed bus modes,
PCO-PC5 function as AO-A3, R/W, and EMS, respectively,
as shown in Table 4-4. EMS (External Memory Select) is
asserted (low) whenever the internal processor accesses
memory area between 0080 and OFFF. (See Memory Map,
Appendix C). The leading edge of EMS may be used to
strobe the eight address lines multiplexed on Port B in the
Multiplexed Bus Mode. See Appendix E.3 through E.5 for
Port C timing.

Table 4-3.

Port B Control & Usage
ABBREVIATED
MODE

I/O MODES
R6541Q &
R6500/43

MeR?
MeR6

=0
=0

=0
=1

MeR?
MeR6

SIGNAL

MeR?
MeR6

SIGNAL

MULTIPLEXED MODE

=1
=0

MeR?
MeR6

NAME

TYPE
(1)

NAME

TYPE
(2)

NAME

49
50
51
52
53
54
55
56

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

DO
D1
D2
D3
D4
D5
D6
D7

1
1

PHASE 1

SIGNAL

PIN #

=
=

PHASE 2
SIGNAL

SIGNAL

TYPE
(3)

NAME

I/O
I/O
I/O
I/O

TYPE (2)

NAME

TYPE (3)

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

DO
D1
D2
D3
D4
D5
D6
D7

I/O
I/O

A4

A5
A6
A7
A8
A9
A10
A11

1/0
I/O
I/O

1/0

1/0
I/O

1/0
I/O
I/O

1/0

(1) TRI-STATE BUFFER IS IN HIGH IMPEDANCE MODE (2) TRI-STATE BUFFER IS IN ACTIVE MODE
(3) TRI-STATE BUFFER IS IN ACTIVE MODE ONLY DURING THE PHASE 2 PORTION OF A WRITE CYCLE

Table 4-4.

Port C Control & Usage

R6541Q &

MeR7
MeR6

R6500/43

=0
=X

MeR7
MeR6

SIGNAL
PIN #

NAME

31
30
29
28
27
26
25

PCO
PC1
PC2
PC3
PC4
PC5
PC6'

MULTIPLEXED
MODE

ABBREVIATED
MODE

1/0 MODE

=1
=0

MeR7
MeR6

SIGNAL

SIGNAL
TYPE
(1)

TYPE
(2)

NAME

I/O
I/O

AD
A1
A2
A3
EMS

1/0
I/O
I/O
I/O
I/O

Fl/W
iNT'

(1) RESISTIVE PULL-UP, ACTIVE BUFFER PULL-DOWN
(2) ACTIVE BUFFER PULL-UP AND PULL-DOWN

'PC6 If MCR5

3-268

=1
=1

NAME

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

= 0;

INT If MCR5

AD
A1
A2
A3
EMS

R/W
INT'

=

1

TYPE
(2)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

Intelligent Peripheral Controllers

R6541 Q and R6500/43
4.7 BUS MODES
A special attribute of Port B and Port C is their capability to
be configured via the Mode Control Register (see Section
3.6) Into four different modes

In the Multiplexed Bus Mode, the operation is similar to the
Abbreviated Mode except that a full4K of external addresses
are provided. Port C provides the lower addresses and control signals. Port B multiplexes functions. During the first half
of the cycle It contains the remaining necessary 8 address
bits for 4K; dUring the second half of the cycle it contains a
bidirectional data bus The address bits appearing on Port
B must be latched into an external holding register. The leading edge of EMS, which Indicates that the bus function is
active, may be used for thiS purpose.

In the Port B All Inputs and Port B All Outputs modes the
separate address and data bus are used. The difference lies
in the direction of Port B-all Inputs or all outputs. The receiving ports perform the normal 1/0 function. A 15 IS usually
used as a chip select for external memory.
In the Abbreviated Bus Mode, the address and data lines can
be used as above to emulate the R6500/41. Port B and Port
C are automatically transformed Into an abbreviated address
bus and control signals (Port C) and a bidirectional data bus
(Port B). 16 Peripheral addresses can be selected. In general
usage, these 16 addresses would be distributed to several
external 1/0 devices such as R6522 and R6520, etc., each
of which may contain more than one unique address.

Figures 4-1a thru 4-1d show the possible configurations of
the four bus modes. Appendix C1 shows a memory map of
the port as a function of the Bus Mode and further shows
which addresses are active or inactive on each of the three
possible buses.

3-269

Intelligent Peripheral Controllers

R6541 Q and R6500/43
PORT B
All OUTPUTS
BUS MODE

ABBREVIATED
BUS MODE

ClKIN - .

8 BITS ) PORT A

RES - .
8 BITS

AO(RS)-.

PORT B

A

R!W (RD)-+

7 BITS

PORTC

CS-.

R/W (PORT C)
}12

Vss --+
HBOHB7

---'SYNC

,+-

8 BITS /
.:L
INT #

+-NMi
12 BITS /
A15 "
R/W
DB1-DB7

r.
A

12 BITS
A15

4K
EXTERNAL
MEMORY
@FXXX

8 BITS

"

Figure 4-1 c.

PORT B
All INPUTS
BUS MODE

MULTIPLEXED
BUS MODE
PORTA

"
8 BITS

AO(RS)-.
RiW(RD)-+

v

E(WR)-+

PORTC

Vcc

"

8 BITS

PORT A

~

19-;T

m

EMS'

---+

(PORT C)
(PORT C)

R/W
1'12

Vss

r---.

HBO-~
HB7..::L
-v
INT#+-

SYNC

~NMi

AO-A3 PORT C)

-:+ SYNC
+- NMI

AD-All
12 BITS

12 BITS "\
A15

R/W
DB1-DB7 ~

4K
EXTERNAL
MEMORY
@FXXX

A15
R/W
DB1-DB7

8 BITS

8 BITS

v

v

Figure 4-1 b.

Figure 4-1 d.

# OPTIONAL pe6
## NOT AVAilABLE WITH BOOTSTRAP ROM OPTION
• EMS VALID @ 0100 THRU OFFF

3-270

UP TO 4K
EXTERNAL
MEMORY
ANDIOR
PERIPHERALS
##
@OXXX

LATCH I A4-All
l

cs~
\12

Vss - .

+-

AO(RS)~

Riw(Ro)-+
E(WFi)--.

CS-.
V cc - '

"'s

ClKIN-+
RES-.

PORT B

7 BITS

4K
EXTERNAL
MEMORY
@FXXX

ADB1-DB~

Figure 4-18.

8 BITS

"

R/W

"

RES - .

SYNC

~NMI

8 BITS

ClKIN - .

16
PERIPHERAL
ADDRESSES
##

EMS (PORT cy

",AO-All".

H BDBITs"
HB7.:::!:
""V
INT #

AD-A3 (PORT C)

Vcc --+

\12

PORT A

DATA BUS PORT B)

"

E (Wii)--+

Vss - .

(a

"

R!W(RD)---.

CS-.
Vcc - '

HBDBITs"
HB7..::!.
"
INT # + -

8 BITS )

RES - - .
AO(RS)--.

"

E(WR)-+

ClK
IN - .

4K
EXTERNAL
MEMORY
@FXXX

v

R6541 Q and R6500/43

Intelligent Peripheral Controllers

SECTION 5
HOST INTERFACE BUS
Two way data transfers are performed between the IPC and
the Host microprocessor by means of the Output Data Register and the Input Data Register. The Host can also write a
command to the lOR and read from the Host Status Flag
Register. Figure 5-1 shows the Host addressing matrix. A
hardware interrupt procedure and a software polling procedure IS available to control data traffic between the CPU and
Host.
RS(Aol

READ

1

HOST
STATUS FLAG

COMMAND
INPUT

0

DATA REG
OUTPUT

DATA REG
INPUT

Figure 5-1.

host write data exchange. The device can write to the Fl flag
at any time.
The OORF (Output Data Register Full) flag IS set each time
the deVice writes to the Output Data Register. The setting of
the OORF sets the device Interrupt Status Register IFR3 flag.
An Output Interrupt (INT) may be generated under program
control by setting IER3 In the interrupt enable register. The
OORF flag IS reset only by a hardware reset or by the host
performing a read on the output data register. The OORF flag
IS reset follOWing the conclusion of any host output data regIster read. The resetting of the OORF causes the reset of the
IFR3 flag and thus the reset of the external Interrupt (INT).

WRITE

The IORF (Input Data Register Full) flag IS set follOWing the
conclUSion of any host write data exchange. The setting of
the IORF causes IFR2 of the device status register to be set.
An Internal Interrupt may be generated under program control by setting IER2 In the Interrupt Enable Register. The setting of IORF also causes IFR4 to be reset. The IORF resets
dUring deVice read of the Input data register. IFR2 sets and
IFR4 resets follOWing the reset of IORF. IFR4 may generate
an external output Interrupt (INT, Input buffer empty), under
program control by setting IER4 in the Interrupt enable
register.

Host Addressing Matrix

5_1 DATA REGISTERS
The device has an 8-bit Input Data Register (lOR) and an
8-bit Output Data Register (OOR). The lOR serves as a temporary storage for commands and data from the Host to the
device. When transferring data from the Host to the deVice,
the follOWing conditions are In effect:
• CS IS asserted
• RS (AO) Indicates command Input or data input.
• The contents of the host data bus (HBO-HB7) are copied
Into the lOR when the appropriate Host bus write signals
are asserted.

INPUT DATA
REGISTER
FULL FLAG

The OOR serves as a temporary storage for data from the
device to the Host. When the Host is reading data from the
device, the follOWing conditions are In effect·

OUTPUT DATA
REGISTER
FULL FLAG

• CS IS asserted
• RS (AO) input selects OOR or HSFR
• The contents of OOR or the Flag Register are placed on
the host data bus (HBO-HB7) when the appropriate Host
read signals are asserted.

GENERAL PURPOSE
FLAGS STATUS REGISTER

5.2 HOST STATUS FLAG REGISTER

Figure 5-2.

A Host Status Flag Register facilitates a software protocol
that permits Independent and uninterrupted flow of data
asynchronously between the host computer and the device.

COPIES RS ON
WRITE FROM HOST

Host Status Flag Register Bit Allocation

5.3 HOST COMPUTER INTERFACE
The device Will work with a variety of Host Computers. The
HOST interface consists of a chip select, one address line,
2 control lines and an 8 bit three state data bus. Internal logic
of the deVice, controlled by MCR4, configures, the address
and two control lines to either a 6500 or 8080 operational
methodology. The interface IS completely asynchronous and
will work with a Host Computer up to a 5 MHz bus transfer
rate. The device clock input frequency need not be the same
as the Host's. A mode control register is set to match the
interface to that of the Host device as follows:

The Host Status Flag Register contains 8 flag bits that can
be read at anytime by either the Host or the deVice. See Figure 5-2. General purpose flags F2 through F6 are serviced
by the device In either read or write modes and monitored
by the Host (Read Only).
Flag Fl can be read at anytime by either the host or the device. The Fl flag copies the AO (RS) input signal during any

3-271

Intelligent Peripheral Controllers

R6541 Q and R6500/43
MCR4

=

0 When MCR4 is set to a logic zero, the IPC is
configured to operate on a 6502/6aOO type host
bus. In this mode, the E Input IS connected to
the host transfer strobe (VMA or ¢2 for 6aOO,
02 for 6500) and the R/W Input IS connected to
the host microprocessor Rm output line. Figure 5-3 and Table 5-1, together, specify the relevant timing for read and write cycles on this
type of host bus.

MCR4 = 1 When MCR4 IS set to a logic one, the IPC is
configured for operation on an aoao/zao type
bus. In this mode, the RD input is used as a
read strobe and the WR input is connected to
the write strobe of the host microprocessor bus.
Figure 5-4 and Table 5-2 show the relevant timing characteristics for this mode of operation.

Table 5-1. Host Interface
Timing Characteristics BSEL = 0 (6500)
CHARACTERISTICS
1 AND 2 MHz

Table 5-2. Host Interface
Timing Characteristics BSEL:;: 1 (8080)
CHARACTERISTICS
1 AND 2 MH

SYMBOL

MIN

SYMBOL

MIN

CS, R/W, RS Setup Time

tes

10

-

CS, AO Setup Time

tes

10

-

Access Time

tOA

-

90'

Data Access Time on Read

tOA

-

90'

tOHR

10

Data Hold Time

tHe

10

-

tWDS

75

tOHW

10

tWR

75

Data Hold Time
Control Hold Time
Write Data Setup Time
Write Data Hold Time
Wnte Stroke Width
'NOTE.
90 ns when loading
75 ns when loading

= 130 pI + 1 TTL LOAD
= 90 pI + 1 TIL LOAD.

MAX

tOHR

10

-

tHe

10

-

Wnte Data Setup Time

tWDS

75

Write Data Hold Time

tOHW

10

Wnte Strobe Width

,tWR

75

-

Control Hold Time

-

'NOTE
90 ns when loadmg = 130 pI + 1 TIL LOAD and
75 ns when loadmg = 90 pI + 1 TIL LOAD.

and

READ

Figure 5-3.

WRITE

Timing Diagram-Host Interface (MCR4

=0) (6500 Version)

WRITE

READ

~ ~44~e --"'1-f;/,Itd
• wJP&f f@ll!ffffff!lIffJW1~r
WFi

-~-

i.-

THe

-~~~r~•••

RD
TDA

TWOS

.)c-I~

HBO-HB7

-----:~l.__

Figure 5-4.

+_'
TDHR

I

Timing Diagram-Host Interface (MCR4 = 1) (8080 Version)
3-272

MAX

Intelligent Peripheral Controllers

R6541 Q and R6500/43

SECTION 6
COUNTER/TIMERS
The Counter operates In any of four modes. These modes
are selected by the Counter Mode Control bits in the Control
Register.

The device contains a 16-blt counter and a 16-bit latch associated with It. The counter can be independently programmed to operate in one of four modes:
Counter

•
•
•
•

Pulse width measurement
Pulse Generation
Interval Timer
Event Counter

Operallng modes of the Counter are controlled by the Mode
Control Register. All counting begins at the Initialization value
and decrements When modes are selected requiring a
counter input'output line, PA2 IS selected for Counter I/O

MCRI

MCRO

(bit 1)

(bit 0)

0
0
1
1

0
1
0
1

Mode

Interval Timer
Pulse Generation
Event Counter
Pulse Width Measurement

The Interval Timer, Pulse Generation, and Pulse Width Measurement Modes are ~2 clock counter modes. The Event
Counter Mode counts the occurrences of an extemal event
on the CNTR line (PA2).
The Counter IS set to the Interval Timer Mode (00) when a
RES signal 15 generated.

6.1 COUNTER

6.1.1 Interval Timer Mode

The Counter consists of a 16-M counter and a 16-M latch
organized as follows: Lower Counter (LC), Upper Counter
(UC), Lower Latch (LL), and Upper Latch (UL). The counter
contains the count of either ~2 clock pulses or external
events, depending on the counter mode selected. The contents of the Counter may be read any time by execullng a
read at location 0018 for the Upper Counter and at location
001A or location 0019 for the Lower Counter. A read at location 0019 also clears the Counter Underflow Flag (IFR5).

In the Interval Timer mode the Counter
Latch value by either of two conditions:

15

Initialized to the

1. When the Counter IS decremented from 0000, the next
Counter value IS the Latch value (not FFFF).
2. When a write operation 15 performed to the Load Upper
Latch and Transfer Latch to Counter address 0019, the
Counter 15 loaded With the Latch value. Note that the
contents of the "Accumulator are loaded into the Upper
Latch before the Latch value IS transferred to the
Counter.

The 16-blt latch contains the counter Initialization value, and
can be loaded at any lime by executing a write to the Upper
Latch at location 0018 and the Lower Latch at location 001A.
In either case, the contents of the accumulator are copied
into the applicable latch register.

J32

The Counter value is decremented by one count at the
clock rate. The 16-M Counter can hold from 1 to 65535
counts. The Counter Timer capacity IS therefore 1/Ls to 65.535
ms at the 1 MHz ~2 clock rate or 0.5/Ls to 32.767 ms at the
2 MHz (12 clock rate. Time intervals greater than the maximum Counter value can be easily measured by counting IRQ
Interrupt requests In the counter IRQ Interrupt routine.

The Counter can be started at any time by writing to address
0019. The contents of the accumulator will be COPied Into the
Upper Latch before the contents of the 16-bit latch are transferred to the Counter. The counter is set to the latch value
whenever the Counter underflows. When the Counter decrements from 0000 the next counter value will be the latch
value, not FFFF, and the Counter Underflow Flag (IFR 5) will
be set to "1". ThiS bit may be cleared by reading the Lower
Counter at location 0019, by writing to address location 0019,
or by RES.

When the Counter decrements from 0000, the Counter Underflow (IFR5) IS set to logic 1. If the Counter Interrupt Enable
Bit (IER5) IS also set, an IRQ interrupt request Will be generated. The Counter Underflow bit in the Interrupt Flag Register can be examined In the IRQ Interrupt routine to determine that the IRQ was generated by the Counter Underflow.

3-273

9

R6541 Q

an~

Intelligent Peripheral Controllers

R6500/43

6.1.4 Pulse Width Measurement Mode

While the timer is operating In the Interval Timer Mode, PA2
operates as a PA 1/0.

ThiS mode allows the accurate measurement of a low pulse
duration on the PA2 line. The Counter decrements by one
count at the 162 clock rate as long as the PA2 line is held in
the low state. The Counter IS stopped when PA2 is In the
high state.

A timing diagram of the Interval Timer Mode is shown in Figure 6-1.

,..

The Counter underflow flag will be set only when the count
in the timer reaches zero. Upon reaching zero the timer will
be loaded with the latch value and continue counting down
as long as the PA2 pin IS held low. After the counter is
stopped by a high level on PA2, the count will hold as long
as PA2 remains high. Any further low levels on PA2 will again
cause the counter to count down from ItS present value. The
state of the PA2 line can be determined by testing the state
of PA2.

COUNTER UNDERFLOW

COUNTER

• I
_-=--....J._.::....-L_.:..-....L--=~...IIc..;(~UL:;..=LL):....l.I.:;:(u::::L.-=LL):..-..:..'
I

.1..1

COUNTER INTERRUPT ENABLED

I
COUNTER UNDERFLOW FLAG

I

---'1-----

'SET ANY TIME BEFORE
COUNTER UNDERFLOWr--1

I
Figure 6-1.

Interval Timer Timing Diagram

6.1.2 Pulse Generation Mode
In the Pulse Generation mode, the PA2 line operates as a
Counter Output. The line toggles from low to high or from
high to low whenever a Counter Underflow occurs, or a write
is performed to address 0019.
The normal output waveform is a symmetrical square-wave.
The PA2 output IS Initialized high when entering the mode
and tranSitions low when writing to 0019.
Asymmetric waveforms can be generated if the value of the
latch is changed after each counter underflow.
A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one occurrence of the output toggle condition.

6.1.3 Event Counter Mode
In thiS mode PA2 IS used as an Event Input line, and the
Counter will decrement with each rising edge detected on
this line. The maximum rate at which this edge can be detected is one-half the ~2 clock rate.
The Counter can count up to 65,535 occurrences before underflowing. As in the other modes, the Counter Underflow bit
(IER5) is set to logiC 1 if the underflow occurs.
Figure 6.2 is a timing diagram of the Event Counter Mode.

Figure 6·2. Event Counter Mode

3-274

Intelligent Peripheral Controllers

R6541 Q and R6500/43

SECTION 7
POWER ON/INITIALIZATION CONSIDERATIONS
7.1 POWER ON TIMING

7.3 RESET (RES) CONDITIONS

After application of VCC power to the device, RES must be
held low for at least eight stable ~2 clock cycles after Vee
reaches operating range.

When RES IS driven from low to high the deVice IS put In a
reset state causing the registers and I/O ports to be set as
shown In Table 7-1.

Figure 7-1 Illustrates the power turn-on waveforms. External
clock stabilization time IS tYPically 20ms.

Table 7·1. RES Initialization of ilO Ports and Registers

REGISTERS
Processor Status
Mode Control (MCR)
In!. Enable (IER)
In!. Flag (IFR)
Host Status Flag
Input Data
Output Data

7

6

5

4

3

-

-

-

0
0
0
0
0
0

0
0
0
0
0
0

1
1
1

1
1
1

2

1

0

-

-

1

-

-

0
0
0
0
0
0

0
0
1
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

1
1
1

1
1
1

1
1
1

1
1
1

1
1
1

1
1
1

"_"""fIAN--'WW\IVV

Figure 7·1.

PORTS
PA Latch
PB Latch
PC Latch

~

mm _ _ _ _ _ _ _ _ _ _ _ _

All RAM and other CPU registers Will Initialize In a random, nonrepeatable data pattern

Power Turn-On Timing Detail

7.4 INITIALIZATION
Any initialization process for the device should include a RES
as indicated In the preceding paragraphs. After stabilization
of the external clock (If a power on situation) an inillalization
routine should be executed to perform (as a minimum) the
follOWing functions:

7.2 POWER-ON RESET
The occurrence of RES gOing from low to high will cause the
deVice to set the Interrupt Mask Bit-bit 2 of the Processor
Status Register-and Initiate a reset vector fetch at address
FFFC and FFFD to begin user program execution. All of the
I/O ports Will be initialized to the high (logic 1) state. All bits
of the Control Register will be cleared causing the Interval
Timer counter mode to be selected and causing all Interrupt
enabled bits to be reset.

1.
2.
3.
4.
5.

The Stack Pointer should be set
Clear or Set Decimal Mode
Set or Clear Carry Flag
Set up Mode Controls and Counter as required
Clear Interrupts.

A tYPical Initialization routine could be as follows:
LDX
TXS
CLD
SEC

CLI

3-275

Load stack pOinter starting address Into
X Register
Transfer X Register value to Stack Pointer
Clear DeCimal Mode
Set Carry Flag
Set-up Mode Control,
Counter, speCial funcllon
registers and Clear RAM as required
Clear Interrupts

R6541 Q and R6500/43

Intelligent Peripheral Controllers

APPENDIX A
EXPANDED R6502 INSTRUCTION SET
The four instructions notated with a * are added instructions
for the IPC devices which are not part of the standard 6502
instruction set.

This appendix contains a summary of the R6502 instruction
set. For detailed information, consult the R6502 Microcomputer System Programming Manual, Document 29650 N30.

A.1 INSTRUCTION SET IN ALPHABETIC
SEQUENCE
MNEMONIC
ADC
AND
ASL

*BBR
*BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS

INSTRUCTION
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)

MNEMONIC
LOA
LOX
LOY
LSR

Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC
CLD
CLI
CLV
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable
Clear Overflow Flag
Compare Memory and
Compare Memory and
Compare Memory and

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

EOR

"Exclusive-Or" Memory with
Accumulator

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Index Y by One

JMP
JSR

Jump to New Location
Jump to New Location Saving Return
Address

NOP

No Operation

ORA

"OR" Memory with Accumulator

PHA
PHP
PLA
PLP

Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack

*RMB
ROL

Reset Memory Bit
Rotate One Bit Lett (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine

Bit
ROR
Accumulator
Index X
Index Y

RTI
RTS

SBC
SEC
SED
SEI
*SMB
STA
STX
STY

TAX
TAY
TSX
TXA
TXS
TYA

3-276

INSTRUCTION
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or
Accumulator)

Subtract Memory from Accumulator with
Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory

Transfer
Transfer
Transfer
Transfer
Transfer
Transfer

Accumulator to Index X
Accumulator to Index Y
Stack Pointer to Index X
Index X to Accumulator
Index X to Stack Register
Index Y to Accumulator

:D

A.2 R6500/1-11 INSTRUCTION SET SUMMARY TABLE

0)

en

MNEMONIC'

OPERATION

IIMMEDIATEIABSOLUTElZEAO PAGEl ACCUM

Op 1 n
ADC
AND
ASL

A-.-M+C ... A

I #- lOP I

n

I #- I OP I

n

I #- lOP I

n

I

IMPLIED

(1)

C·'~-il

I

(INo, X)

n

(INO), Y

I #- IOPI

6 92220432532
2
1 TITT
' ! '5I '2 lOA I 2 I 1
OE I
6'!
3 "06

Iz

PAGE, X I ABS, X

n I # lop I n

~~ I ~ I ~ I ~~

(4)(1)

A M-A

I

I #- I OP I n I#- lopi

CODES

I

ASS, Y

cp
I\)

:::I

BCS

Branch on

C~l

(2)

Branch on Z - 1

(2)

BIT
BMI
BNE
BPl
BRK
BVe
BVS
ClC
ClD
CLI
ClV
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
INX

A M

I'NY
JMP
JSR
lOA
lOX
lOY
lSR
NOP
ORA
PHA
PHP
PLA
PlP
AMB!#(0-7)]
ROl
ReR
ATI
RTS
SBC
SEC
SED
SEI
5MB[#(0-7)J
STA
STX
STV
TAX
TAY
TSX
TXA
TXS
TVA

Branch
Branch
Branch
Break
Branch
Branch

I7 6 5 4 3 2 1 e

BIT ADDRESSING tOP BY BIT #)

PAGE, Y

I # 1OPI

nI # 1 e

DB
58 121'
B8 2 1

ell 61 2 I 01 I 5 I 2 I 051 4 I 2 1OD! 4 I 3 109 I 4 13

E 022 2 E C 4 3 E 4

X--l--->X

Y-l---c>Y
AVM---+A

50

'0

18

CO

(1)

M+l_M
Xll-.X

2 1
2T
g~:;
g:1;1~
TIT5

14912 121 ~~ I: I~ I ~! I 3

o

•••

•

~

Z

212
2

,

Co)

..
..
..
..

'"
,

2

N

z

•

C
Z C

Z C
06161210EI713

~: I~ I~
I2

41

I

6

I

2

I

51

I

5

I 2 I 55

~~1;1~1591413

F6

N

•••••

Z

EB
CB

Y+l----Y

4C
20

Jump to New Loc
Jump Sub
M-A (1)

A9

2

A0

0- cz:==]J - C
No Operallon

AVM--->A
A___ Ms S-1---5
P---->Ms 5-1---->5
S+1---S Ms---A
S+1---S Ms---P
.0--+Mb (5)

09

~I
Rtrnlnt

6C 15131

2

A2

(1)
(1)

Rlrn SUb
A-M C--A (1)
hC
1_0
l-T
l-->Mb (5)
A-M
X_M
Y_M
A_X
A-Y

:D

en

·1·1

(2)
(2)

n

Z

2 C

0)

M,M6

30
00
10

0-

C

2

00 17 It
on V-0
on V - 1

z

~~l ~~l !~I ~~ I~~16~1 ~~ I;~

, 12
2

I'CI4131241312

I

Q)

::s

7INV·BDlze

3 1'9 14 1 3
'514121'0
14413
3
54230
3943
16 6 2 1E

(2)
(2)
(2)

0-C
0-0
0-1
0-V
A-M
X-M
Y M
M-l---c>M

M---+X
M---+Y

n

N V
N
N •

90
BO
FO
I

on N-l
on Z=0
on N~"

I RELATIVE I INDIRECT I Z

I # lop 1 n 1# loP I n I # lop I n I # I OP I

BBR[#(0-7)] Branch on M.. =0 (5)
88S[#(0-7)] BranchonM.~l (5)
Bee
Branch on C=0 (2)
BEQ

.1=10
.....
o

PROCESSOR STATUS

ADDRESSING MODES

2

2

I

A11 6

AE43A6
ATIT51312
AC 4 3 M

4E

6

3

46151214A'211

00

4

3

05

3

EA 12 11

2

I~~I~I;I ~~I;I;I~~I;I~

I E912121EDI4131 E51312

133

68

4

28

4

Bl j 5

I 2 I 851

4

I 2 I so I 4 I 3 I :~

I: I~

B6

4

,

~~I:I~I~~I;

:: I~ I!

I'l'
2
2

Z
Z
Z C

O·

-"

N •

::s

Z •

N •

1

CD

(Reslvred)
07 t 171 27 1 37 ! 471 57 1 67 1771 •
N
N •

~~I:I;I~~

cC·

C
Z C

Z

CD

(Restored)

Ell 61 21 Ft I 5 I 2 1 Fsi 4 I 2 1 FO I 4 I 3 I F9 I 4 I 3

N V
1

81 j 61 21 91 1 6 j 2 I 951 4 1 2 I 90 I 5 1 3 1 ( ,I 5 1 3

::s

Z (3)

1
1

B
5 3
8E4386
l I T 1 1'
8C43a4

NOlES
1 Add 1 to N If page boundary IS crossed
2. Add 1 to N 'f branch occurs to same page
Add 2 to N If branch occurs to !:llfferent page
3 Carry not = Borrow
4 If In decimal mode Z flag IS ,"valid
accumulator must be checked on zero resu"
5. Effects 8-bIt data freld of the spectfted zero page address

I

11

I II

X-A
X_S
Y_A

2

011 61 21 11 I s I 2 I lsi 4 I 2 ItO I 4 I 3 I 19 I 4 13
4B
OB

F8
3B
78

s-.x

I

,.
•

CD

::::!.
-C

9£[4121''1"'1''1"' n D T ' I F ' I :

941 41 2
AA
A8
BA
BA

Z

N •

1211
2 t

J
CD

•

~

2
2

N •

:: ~ I ~

Z :

N •
LEGEND

X
y
A
M
M.
M,
M,

eJ

M,
Index X
Index Y
Accumulator
Memory per effective address
Memory per stack pointer
Selecter zero page memory bit
Memory elt 7

~

Memory Bit 6

=

A

Add
Subtract
And

V

0,

"
"

ExcluSIve Or
Number of cycles
Number of Bytes

I

!!.
0
0
::s

~

!2.
CD
~

tn

R6541 Q and R6500/43

Intelligent Peripheral Controllers

A.3 INSTRUCTION CODE MATRIX
LSD

o

:q

3

0

4

BRK
ORA
Implied (IND, X)
7
2 6

RMBO
ZP
2 5

PHP
Implied
3

ORA
IMM
2 2

ORA
ZP, X
2 4

ASL
Zp, X
2 6

RMB'
ZP
2 5

CLC
Implied
2

ORA
ABS,Y
3 4-

AND
Zp
2 3

ROL
Zp
2 5

RMB2
ZP
2 5

PLP
Implied

AND
IMM
2 2

BMI
AND
Relative (IND, Y)
2 2-'
2 5'

AND
ZP, X
2 4

ROL
ZP, X
2 6

RMB3
ZP
2 5

SEC
Implied
2

AND
ABS, Y
3 4-

RTI
EOR
Implied (IND, X)
6
2 6

EOR
ZP
2 3

LSR
ZP
2 5

RMB4
ZP
2 5

PHA
Implied

EOR
IMM

EOR
Zp, X
2 4

LSR
ZP, X
2 6

RMB5
ZP
2 5

CLI
Implied
2

EOR
ABS,Y

RTS
ADC
Implied (IND,X)
2 6
6

ADC
ZP
2 3

ROR
ZP
2 5

RMB6
ZP
2 5

PLA
Implied

AOC
IMM
2 2

BVS
ADC
Relative (IND, Y)
2 2-2 5-

AOC
Zp, X
2 4

ROR
ZP, X
2 6

RMB7
ZP
2 5

SEI
Implied
2

BPL

ORA

Relative (IND), Y
2--

2

2 5-

JSR
AND
Absolute (IND, X)
3 6
2 6

BIT
Zp
2 3

,

BVC

EOR

Relative (IND), Y
2--

2

2 5-

,

BCC

A

B

C

o

E

F

,

4

,

,

3

,

,

4

,

2 2

2

ROL
Accum
2

BIT
ABS
3 4

,
,

2

,

2

DEY
Implied
2

STA

STY
ZP, X

STA
ZP, X
2 4

STX
ZP, Y
2 4

5MB'
ZP
2 5

TYA
Implied
2

STA
ABS,Y
3 5

TXS
Implied
2

2 3

LOA
ZP
2 3

LOX
ZP
2 3

5MB2
ZP
2 5

TAY
Implied
2

LOA
IMM
2 2

TAX
Implied
2

LOY
ZP, X
2 4

LOA
Zp, X
2 4

LOX
ZP, Y
2 4

5MB3
ZP
2 5

CLV
Implied
2

LOA
ABS,Y
3 4-

TSX
Implied
2

CPY
ZP
2 3

CMP
ZP

DEC
ZP
2 5

5MB4
ZP
2 5

INY
Implied
2

CMP
IMM
2 2

OEX
Implied
2

DEC
ZP, X
2 6

5MB5
ZP
2 5

CLO
Implied

CMP
ABS,Y

2 4
SBC
ZP
2 3

INC
ZP
2 5

5MB6
ZP
2 5

INX
Implied
2

SBC
IMM
2 2

SBC
ZP, X
2 4

INC
ZP, X
2 6

5MB7
ZP
2 5

SED
Implied
2

SBC
ABS,Y
3 4-

6

7

8

2 4
LOX
IMM
2 2

CMP
(IND, X)
2 6

LOY
ZP

CMP
ZP, X

SBC
(IND, X)
2 6

CPX
ZP
2 3

BEQ
SBC
Relative (IND), Y
2 2-2 5-

o

2 3

4

2

,
,

,
,

2

,
,

o
o

BRK
Implied
1 7

3 4-

ASL
ABS, X
3 7

BBR'
ZP
3 5'-

AND
ABS
3 4

ROL
ABS
3 6

BBR2
ZP
3 5--

AND
ABS, X

ROL
ABS, X
3 7

BBR3
ZP
3 5--

EOR
ABS

LSR
ABS

BBR4
ZP

3 4

3 6

3 5--

EOR
ABS,X
3 4-

LSR
ABS, X
3 7

BBR5
ZP
3 5--

AOC
ABS
3 4

ROR
ABS

3 6

BBR6
ZP
3 5--

ADC
ABS,X
3 4-

ROR
ABS,X
3 7

BBR7
ZP
3 5"

ADC
ABS,Y
3 4-

5MBO
ZP
2 5

LOA
(IND, X)
2 6

ORA
ABS,X

TXA
Implied
2

,

STY
ABS

STA
ABS

STX
ABS

3 4

3 4

3 4

LOY
ABS
3 4

LOY
LOA
ABS, X ABS, X

,
,

NOP
Implied
2

,

B

BBSO
ZP
5--

LOX
ABS

3 4

BBS2
ZP
3 5'-

A

BBS3
ZP
5-'

B

BBS4
ZP
5--

C

BBS5
ZP
5--

o

E

3 4-

LOX
ABS, Y
3 4-

CPY
ABS
3 4

CMP
ABS
3 4

3 6

3

CMP
ABS, X
3 4-

DEC
ABS, X
3 7

3

CPX
ABS

SBC
ABS

3 4

3 4

INC
ABS
3 6

BBS6
ZP
3 5--

SBC
ABS,X
3 4'

INC
ABS, X
3 7

3 5--

o

E

F

C

6

3

3 4-

3 4-

A

LOA
ABS
3 4

o

BBS,
ZP
3 5--

STA
ABS, X
3 5

,
,

BBRO
ZP
5"

3

3 3

JMP
Indirect
3 5

ROR

Accum

STX
ZP
2 3

,

E
ASL
ABS
3 6

JMP
ABS

3 4'

,

o
ORA
ABS
3 4

3 4LSR
Accum

STA
ZP
2 3

BNE
CMP
Relative (IND), Y
2 2-2 5CPX
IMM
2 2

,

,

Accum

STY
ZP
2 3

BCS
LOA
Relative (IND), Y
2 2'2 5CPY
IMM
2 2

,

C

ASL

STA
(IND, X)
2 6

Relative (IND, Y)
2 2-'
2 6
LOY
IMM
2 2

B

A

ASL
ZP
2 5

,

4

6
ORA
ZP
2 3

DEC
ABS

3

BBS7
ZP

F

'Add 1 to N if page boundary is crossed.
"Add 1 to N If branch occurs to same page;
add 2 to N if branch occurs to different page.

-op Code
-Addressing Mode
-Instruction Bytes; Machine Cycles

3-278

R6541 Q and R6500/43

Intelligent Peripheral Controllers

APPENDIX B
KEY REGISTER SUMMARY
CPU Registers

Processor Status Register
0

15

I

1"1 vi 1 "101'1 zl cJ

I ACCUMULATOR

I
7
I
7
I7

0

I

0

I

INDEX REGISTER X

0

PCH

I PROGRAM COUNTER

PCl

CARRY (C) (1)

L

INDEX REGISTER Y

PC

1
o

1
o

0

I STACK POINTER

5P
7

eo

Carry Set

=

Carry Clear

Zero (2) (1)
=
=

Zero R.sult
Non-Zero Result

INTERRUPT DISABLE (I) (2)

0

I-Ivl I" 10 1' I z I a I PROCESSOR STATUS REG

P

1 '" IRQ Interrupt Dlaabled
o eo IRQ Interrupt Enabled
DECIMAL MODE (O) (1)
1 '" Decimal Mode

o '" Binary Mode
BREAK COMMAND (B) (1)

Mode Control Register

1 '" Break Command
o = Non·B ....k Command
OVERFLOW (0) (1)

MCR

ADOR 0014

1

=

everllow Set

o '" Overflow Clear
NEGATIVE (N) (1)

NOTES
(1) Not Initialized by RES
(2) Sat to Logic 1 by RES

I

,L,

sus MOCE

o

NOT USED

I
o
o

1 '" Negatlva Value
o '" Poallive Value

0 INTERVAL TIMER
PULSE GENERATOR
EVENT COUNTER

1 PULSE WIDTH MEASUREMENT

BUS SELECT
= 6500/6800 BUS
1 '" Z80/8080 BUS

Interrupt Enable and Flag Registers

o

INT SELECT

0= PC6
1 = l"iii'f

0

PORT B ALL INPUTS
PORT B ALL OUTPUTS

1

MULTIPLEXED BUS MODE

AODR 0012

'ER

ABBREVIATED BUS MODE

AODR 0011

Host Status Flag Register
PAO POSITIVE
EDGE DETECT
INTERRUPT ENABLE

ADOR 001E

HSFR

PA1 NEGATIVE
EDGE DETECT
INTERRUPT ENABLE
INTERNAL INTERRUPT
REQUEST, IRQ ENABLE
EXTERNAL INTERRUPTS REQUEST 1,
INT-1 ENABLE
INPUT DATA REGISTER
FULL FLAG

EXTERNAL INTERRUPT REQUEST 2,
INT-2 ENABLE
COUNTER UNDERFLOW
INTERRUPT ENABLE

,
OUTPUT DATA REGISTER
FULL FLAG

COPIESRS ON
WRITE FROM HOST

Host Addressing Matrix
RS (Ao)

READ

1

HOST
STATUS FLAG

COMMAND
INPUT

DATA REG
OUTPUT

DATA REG
INPUT

GENERAL. PURPOSE
FLAGS STATUS REGISTER

0

3-279

WRITE

:D

APPENDIX C
C.1 MEMORY MAPS AND ADDRESS AND PIN ASSIGNMENTS

0')

en

.....a:::.

"
II)

::l

a.

:D

Q)

PORT B ALL INPUTS
&
PORT B ALL OUTPUTS

ABBREVIATED BUS MODE

MULTIPLEXED BUS MODE

FFFE

FFFE

FFFE

FFFC

FFFC

FFFC

FFFA

FFFA

NMI VECTOR

,

FFFA

NMI VECTOR

FFFE

NMI VECTOR

FFFA

4K USER
PROGRAM

4K :.JSEA
PROGRAM

4K USER
PROGRAM

R6500/43
(W/BOOT STRAP ROM)

NMI VECTOR

FFFE

IRO VECTOR

,

FFFC

RES VECTOR

I

FFFA

NMI VECTOR

!

4K
USER
PROGRAM

4K

USER PROGRAM

FOOD

FOOO

FOOOI

FOOD

FOOO

en
o

R6541 & R6500/43
(W/O BOOT STRAP ROM)

~
(,.)

I
I

INTERNAL REGISTERS

WRITE

READ

RESERVED

RESERVED

I
I

NOT AVAILABLE

Cf
0>
'"
o

RESERVED

TOFFF

TOFFF

o

o

OFFF
OFFC

Oil

PERIPHERAL
ADDRESSES
(16)

>

w
::i'
w

I

10100

007F

w
::i'
w

I

EXTERNAL
MEMORY
4056--128

OFOO

Output Host Bus Buffer

Lower Counter A
Lower Counter A#
Upper Counter A

Lower Latch A
Upper Latch A * #
Upper latch A

Mode Control Reg

Interrupt Enable Reg
Interrupt Flag Reg
Read FF

Interrupt Enable Reg

I
I
I

elr Interrupt Flag Reg

ADDRESS

001F
00lE
0010
001C
001B
001A
0019
0018
0017
0016

0015
0014
0013
0012
0011
0010
OOOF

I

I/O & REGISTERS

I/O & REGISTERS
0000I

I/O & REGISTERS
0000

lIO PORTC
I/O PORT B
I/O PORT A

D01F

00lF

00lF

RESERVED

RESERVED

RESERVED

I/O & REGISTERS
0000
'~AND

#

START COUNTER
CLEAR FLAG

I!.
CO
CD

-"
::l

NOT AVAILABLE

I

0040

~~

~~

I

INTERNAL
RAM (64)

~~

~~

Mode Control Reg

I

G07F

0040

Input Host Bus Buffer

I

0080
INTERNAL
RAM (64)

INTERNAL RAM (64)
0040

00lF
0000

I
I

NOT
AVAILABLE

RESERVED

I/O & REGISTERS

BOOT STRAP
ROM (256)

~~

~~

I

RESET VECTOR

0100
OOlF

)

007F

0040
RESERVED

0000

;;

EXTERNAL MEMORY
4096-126

INTERNAL RAM (64)

INTERNAL RAM (64)

00lF

OFFB

::;

10101

007F

0040

I

1000

HBS Status Register

HBS Status Register

0003
0002
0000

CD

I~
CD
~

!!.
0

0

::l
~

2-

CD
~

(I)

Intelligent Peripheral Controllers

R6541 Q and R6500/43
C.2 1/0 AND INTERNAL REGISTER ADDRESSES
ADDRESS

READ

WRITE

--

001F
1E
10
1C

--

Host Status Flag Register

Host Status Flag Register

--

-Input Data Register (IDR)

Output Data Register (ODR)

--

1B
1A
19
18

--

Lower Counter
Lower Counter & Clear Flag (IFR5)
Upper Counter

Lower Latch
Upper Latch/Transfer Latch to Counter & Clear Flag (IFR5)
Upper Latch

----

17
16
15
14

---

--

Mode Control Register

Mode Control Register

--

13
12
11
10

-Interrupt Enable Register
-Clear Int Flag Bit

Interrupt Enable Register
Interrupt Flag Register
Read "FF"

------

OF
OE
aD
OC
OB
OA
09
08

---

-----

----

---

------

07
06
OS
04
03
02
01
00

--

---

---

Port C
Port B
PortA

Port C
Port B
Port A

C.3 MULTIPLE FUNCTION PIN ASSIGNMENTS

PIN NUMBER
R6500/43
R6541Q

FUNCTION

ABBREVIATED PORT
FUNCTION

MULTIPLEXED PORT
FUNCTION

31
30
29
28

pea
PC1
PC2
PC3

AO
A1
A2
A3

AO
A1
A2
A3

27
26
25

PC4
PC5
PC6/1NT

R/W
EMS
PC6/INT

R/W
EMS
PC6/INT

49
50
51
52

PBO

DO

PB1
PB2
PB3

D1
D2
D3

A4/DO
A5/D1
A6/D2
A7/D3

53
54
55
56

PB4
PBS
PB6
PB7

D4
D5
D6
D7

A8/D4
A9/D5
A10/D6
A11/D7

I/O

3-281

R6541 Q and R6500/43

Intelligent Peripheral Controllers

APPENDIX D
ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS·
Parameter

Symbol

Value

Unit

Supply Voltage

Vee

-0.3 to + 7.0

Vdc

Input Voltage

VIN

-0.3 to +7.0

Vdc

Operating Temperature
Commercial

TA

TLtoT H
o to + 70

'C

TSTG

-SSto+1S0

'C

Storage Temperature

°NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

DC CHARACTERISTICS
(Vee = 5.0V ±50f0, Vss = OV; TA = 0° to 70°, unless otherwise specified)
Parameter

Symbol

Min

Input High Voltage

VIH

+2.0
-0.3

Input Low Voltage

VIL

Input Leakage Current

lIN

Input Low Current

IlL

Output High Voltage

VOH

+2.4

Output High Voltage (CMOS)

VeMos

Vee -30%

Output Low Voltage

VOL

1/0 Port Pull-Up Resistance
PAO-PA7, PCO-PC7,
PFO-PF73, PGO, PG73

RL

3.0

Output High Current (Sourcing)

10H

-100

Output Low Current (SInking, PE3)

10L

1.6
-1.0

Darlington Current Drive (PE3)

IOH

Input Capacitance
XTLI, XTLO
All Others

CIN

Output Capacitance (Three-State Off)

Power Dissipation (Outputs High)

-

-1.0

-

Max

V

+0.8

V
~

VIN = 0 to S.2SV

-1.6

rnA

VIL = O.4V

Vce

V

ILOAo = -100 I'A
Vee
4.7SV

Vee

V

Vee

+0.4

V

I1.S

Kohm

-

-

-

SO
10

Cour

-

-

10

Po

-

750

3-282

Test Conditions

±10.0

-

=

Unit

Vcc

=
= 4.7SV
ILOAo = 1.6 rnA

Vee
6.0

Notes:
1. Typical values measured at TA
2S'C and Vee
S.OV.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. R6500/43 only.

=

Typl

1100

~

Your

rnA

Your

=

4.7SV

= 2.4V
= O.4V
= I.SV

rnA

Your

pF

TA
2Soc
VIN
OV
f
1.0 MHz

pF

TA = 2S'C
VIN = OV
f = 1.0 MHz

mW

TA = 2S'C

=
=
=

R6541 Q and R6500/43

Intelligent Peripheral Controllers

APPENDIX E
TIMING REQUIREMENTS AND CHARACTERISTICS

E.1 GENERAL NOTES
5V ± 5°0, O°C :S TA :S

1. Vee

E.2 CLOCK TIMING
70°C
1 MHz

2. A valid Vee - RES sequence is required before proper
operation is achieved.

Symbol

Parameter

2 MHz

Min

Max

Min

Max

TCYC

Cycle Time

1000

10 "s

500

10 "s

3. All timing reference levels are 0.8V and 2.0V, unless otherwise specified.

Tpw~

ClKIN Input Clock
Pulse Width

475

-

240

-

4. All time units are nanoseconds, unless otherwise specified.

TpW02

T pw00

T pw00
+25

T pw00

T pw00
+20

5. All capacitive loading is 130 pF maximum, except as noted
below:

Output Clock
Pulse Width at
Minimum TCYC

T R,

Output Clock
Rise, Fall Time

-

25

-

15

Input Clock Rise,
Fall Time

-

10

-

10

PA, PB
50 pF maximum
PB, PC (1/0 Modes Only)
50 pF maximum
PB, PC (ABB and Mux Mode) - 130 pF maximum

14

CLKIN~1.5V

TF

T IR , TIF

Tcve

'·lE

1r"
1.5V

Tpw• o

4

..
I'-

02

-

7
-,

3-283

_ TA

•

TpW02

.-'

-

.-

~<"" - - - TF

R6541 Q and R6500/43

Intelligent Peripheral Controllers

E.3 ABBREVIATED MODE TIMING-PB AND PC
~

(MeR 5

1, MeR 6

~

D, MeR 7

~

1)
1 MHz

SYMBOL

2 MHz

PARAMETER
MIN

MAX

MIN

MAX

T pCRS

(PC5) R/W Setup Time

-

225

-

140

T pCAS

(PCO-PC3) Address Setup Time

-

225

-

140

TpBSU

(PB) Data Setup Time

50

-

35

T pBHR

(PB) Data Read Hold Time

10

-

10

-

T PBHW

(PB) Data Write Hold Time

30

-

30

-

T pBDD

(PB) Data Output Delay

-

175

-

150

T PCHA

(PCO-PC3) Address Hold Time

30

-

(PC5) R/W Hold Time

30

30

T pCHV

(PC4) EMS Hold Time

10

-

30

T pCHR

-

T pcvp

(PC4) EMS Stabilization Time

30

-

30

-

TEsu

EMS Setup Time

- ...

350

-

210

NOTE 1 Values assume

PCO~PC5

10

have the same capaCItIve load

E.3.1 Abbreviated Mode Timing Diagram
WRITE

READ

"
_ _ TPCHR

A/Vi
(pe5)

____ TPCHV

TPCVP

TPeOD
TPBSU

peO-P87

TPBHR

3-284

TPBHW

Intelligent Peripheral Controllers

R6541 Q and R6500/43
E.4 MULTIPLEXED MODE TIMING-PB AND PC
(MeR 5

~

1, MeR 6

~

SYMBOL

1, MeR 7

~

1)
1 MHz

PARAMETER

MIN

2 MHz

MAX

MIN

MAX

T pCR5

(PCS) R/W Setup Time

-

225

-

140

TPCAS

(PCO-PC3) Address Setup Time

225

-

140

T pBAS

(PB) Address Setup Time

-

225

-

140

T pssu

(PB) Data Setup Time

50

35

TI"BHR

(PB) Data Read Hold Time

10

-

T"PBHW

(PB) Data Write Hold Time

30

-

30

-

T pBDO

(PB) Data Output Delay

-

175

-

150

TpCHA

(PCO-PC3) Address Hold Time

30

-

30

TpBHA

(PB) Address Hold Time

TpCHf.!

(PCS) R/W Hold Time

T pOiV

TpCVD I1'

0

10

100

0

80

-

30

-

30

(PC4) EMS Hold Time

10

-

30

-

10

(PC4) Address to EMS Delay Time

30

-

T pcvp

(PC4) EMS Stabilization Time

30

-

30

-

T ESU

~SetupTime

-

350

-

210

NOTE 1 Values assume PCOMPC5 have the same capacitive load.

E.4.1 Multiplex Mode Timing Diagram
READ

WRITE

1,-_ _ _ _ _ _ _""""'

~TPCHR

RW
(pe5)

I

11

EMS

.!

(PC4)

--~
TPCHA

ESU-...

I

~

PCO-PC3

I _ _--~I

I"

TPCAS
TPRHA

TPBDD

-'

PSO-P87

__
TPBAS

TPBHR

...-TPCvD

3-285

,I
TPBHW

R6541 Q and R6500/43

Intelligent Peripheral Controllers

E.S I/O, EDGE DETECT AND COUNTER TIMING
1 MHz

PARAMETER

SYMBOL

MIN

MAX

2 MHz
MIN

MAX

-

500
1000
150

Internal Wnte to Penpheral Data Valid
Til)

pow

TCMos(1)

Tpoow

-

PA, PC TTL
PA, PC CMOS
PB

500
1000
175

-

-

-

Peripheral Data Setup Time
Tposu
TPDSU

PA,PC
PB

200
50

-

200
50

-

75
10

-

75
10

-

Tcyc

-

Tcyc

-

Tcyc

-

Tcyc

-

Penpheral Data Hold Time

T pHR
TpHA
T EPW

PA,PC
PB
PAO-PA1 Edge Detect Pulse Width

-

Counter
Tcpw
Tco(1)

PA2 Input Pulse Width
PA2 Output Delay

-

-

500

500

NOTE 1 Maximum Load Capacitance 50pF Passive Pull-Up ReqUired

E.S.1 I/O, Edge Detect, Counter.
T C.05- T DSu

SYNC Hold Time

TSVH

30

-

E.6.1 Microprocessor Timing Diagram
WRITE

READ

RW

,---------------n-----;

TMOS

DATAO-=PDATA 7

~------'I

.,.

__________ THA

THW~

_

..~ ;;:l-I XZ2<
~___________~
______________>2?
3-287

SECTION 4
MEMORY PRODUCTS
Page
Product Family Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-2

Masked ROMs
R2332A and R2332B 32K NMOS Static ROM ..................................

4-3

R2364A 64K NMOS Static ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-7

R2364B 64K NMOS Static ROM ............................................. 4-11
R23C64 64K CMOS Static ROM ............................................. 4-15
R23128 128K NMOS Static ROM ............................................. 4-19
R23C128 128K CMOS ROM ................................................. 4-23
R23256 and R23257 256K Static ROMs ....................................... 4-27
UV Erasable PROMs
R87C64 64K CMOS UV EPROM ............................................. 4-31
EPROM Pinouts Guide ..................................................... 4-37

4-1

MEMORY PRODUCTS
High Density NMOS ROMs and Low Power CMOS ROMs/EPROM
active and standby modes, reduce power supply
requirements and extend operating time between battery
replacement/recharge. Latched address (and optional
latched chip select) features enhance design-in for both
multiplexed and non-multiplexed address/data bus
structures. The latched address scheme is compatible with
systems using a clocked chip enable, a good engineering
practice to eliminate contention and reduce noise. In
addition, the ROM output drivers are not enabled until valid
data is available. This eliminates noise and excess power
consumption due to unneeded output data line transitions.
For many permanent memory applications, or ROM code
prototyping, the Rockwell R87C64 is ideal. With low-power
dissipation in both active and standby modes, the R87C64
will meet your most demanding power sensitive
requirements and allow in-line cost-reduction upgrade to
Rockwell CMOS ROMs for larger production runs.

Rockwell NMOS and CMOS masked ROMs support a
broad range of high volume permanent memory applications.
A wide selection of different size ROMs with various speed,
power and temperature range options-backed by Rockwell
dependability and service-will meet your production needson schedule and at the right price. Industry standard
pin-outs allow easy prototyping with popular EPROMS.
Covering a wide spectrum of sizes-32K through 256K bits,
Rockwell NMOS ROMs can efficiently implement such
applications as single 4K-byte ROM-based controllers to
multiple 32K-byte ROM-based personal computers and
graphics work stations. Low-power standby mode is a
standard feature on larger density ROMs and a mask option
on lower density ROMs.
For low power applications, such as battery powered
portable computers and terminals, Rockwell CMOS ROMs
are unsurpassed. Extremely low power dissipation in both

Rockwell Has The Right ROM For Your System
NMOS ROMS

Density
32K

64K

Active Power
(mW)

Standby Power
(mW)

Organization

Part No.

Max. Access
Time (ns)

4096x8

R2332A
R2332AS

200/250/300/450
250/300/450

125
125

275
275

37.5

R2332B
R2332BS

200/250/300/450
250/300/450

125
125

275
275

37.5

R2364A
R2364AS

200/2501300
200/250/300

125
125

275
275

37.5

R2364B
R2364BS

200/250/300
200/2501300

125
125

275
275

37.5

8192x8

Package

Compatible
PROM

24-pin DIP
24-pln DIP

2532
2532

-

24-pin DIP
24-pin DIP

2732
2732

-

24-pin DIP
24-pin DIP

MCM68764
MCM68764

80

28-pin DIP
28-pln DIP

2764
2764

Typ.

Max.

Typ.

Max.

-

-

-

-

128K

16384x8

R23128

250/300

125

275

37.5

256K

32768x8

R23256
R23257

200/250/450
200/250/450

125
125

400
400

40
40

64K

8192x8

R23C64

150/250/300

51

101

128K

16384x8

R23C128

150/250/300

81

151

80
80
80

80

28-pin DIP

2764

100
100

28-pin DIP
28-pin DIP

2764
2564

0.03

0.05

28-pin DIP

27642

0.03

0.05

28-pin DIP

27642

CMOS ROMS

Notes:
1. @ 1 pS cycle time.
2. The R23C64 and R23C128 latch the address inputs on the falling edge of

4-2

E.

R2332A and R2332B
Memory Products

'1'

R2332A AND R2332B
32K (4K x 8) STATIC ROM

Rockwell
DESCRIPTION

G/G/N

The R2332A and R2332B ROMs are 32,768-blt static Read-Only
Memories (ROMs), organized as 4,096 eight-bit bytes, that offer
maximum access times of 200 to 450 nanoseconds, respectively,
These ROMs are In Industry-standard 24-pln, dual in-line packages,
and are available In ceramiC or low-cost plastic These fully-static
32K-blt ROMs are compatible with Industry standard
microprocessors,

E/E/N

All R2332A and R2332B ROMs operate totally asynchronously
and require no clock Input These deVices prOVide tn-state output buffers for memory expansion These ROMs offer TTL Input
and output levels With a minimum nOise Immunity of 0 4 volts

AO

QO

A1

Q1

A3

Ore

The mask-programmable chip enable Input (EiE) may be programmed to function as a chip select Without power down
standby mode or as a chip enable With power down standby
mode The active level of the enable Input IS also programmable

A4

w"Co

A5

3:~

A2

A6

II:

w

C~

o~

Q2
32, 768-61T
ROM
CELL ARRAY

Q3
Q4
Q5
Q6

0

II:

Q7

FEATURES
• 4,096 x 8 organization
• Access time' 200 ns, 250 ns, 300 ns, and 450 ns (max,)
• Low power diSSipation IS 125 mW active, 37.5 mW standby
• Dnves two TTL loads and 100 pF

A7 AS A9 A10 A11

• Single +5V :'= 10% power supply
• Totally static operation, no Input clock required
• Completely TTL compatible

R2332A and R2332B Block Diagram

• Mask-programmable chip enable and chip select
• Tn-state outputs for memory expansion

R2332A

R2332B

ORDERING INFORMATION
Part Number:

R2332_='::"_~-LL pa~k:g~eramlc
P

~

PlastiC

Temperature Range
No letter ~ O°C to + 70'C
E ~ -40'C to +85'C
Power Down Standby Mode
S ~ Yes
No letter ~ No

L

Access Time (Max)

Note Submit ROM
codes uSing Rockwell
ROM Code Order
Form, Order No
2137

A7

vcc

A7

vee

A6
A5

AS

A6

AS

AS

A5

A4

GIGIW

A4

A9
All

A3

eiElw

A3

GIGIW

A2

Al0

Al0

Al

All

A2
Al

AO

07

AO

07

00
01

06

00
01

06
05

02

04

GND

03

02

05
04

GND

03

eiEIW

2;:~~~~:

3 ~ 300 ns
No number(s) ~ 450 ns

"Mask-programmable option
"N = No effect on selection/enable logic, however, no voltage
other than logic levels shall be applied,

Model
A ~ R2332A
B ~ R2332B

R2332A and R2332B Pin Configuration

Document No. 29000089

Data Sheet Order No. 089
Rev. 3, October 1984
4-3

9

32K (4K x 8) Static ROM

R2332A and R2332B
ABSOLUTE MAXIMUM RATINGS*
Parameter

Symbol

Value

Vcc

-0.5 to +7.0

V IN

-0.5 to +7.0

Vdc

VOUT

-0.5 to +7.0

Vdc

Supply Voltage
Input

Vo~age

Output

Vo~age

Temperature Under Bias
Commercial
Industrial

TA

Storage Temperature

TSTG

Power Dissipation

P

'C
-10 to +BO
-50 to +95

DC CHARACTERISTICS
Symbol

"NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this document is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

Unit
Vdc

-65 to +150

W

Vcc = 5 OV -+ 10%, T A = O'C to 70'C (unless otherwise specified)

Parameter

V OH

Output High Voltage

VOL

Output I..ow Voltage

'C

1.0

Min

Typ3

2.4

Max

Test Conditions

Units

10H

Vcc

= 4.5V,
= 4.5V,

= 5.5\1,

OV "" VIN "" 5.5V

Vcc

V

Vcc

0.4

V
V

=

-400 /LA

10L = 3.3 mA

V IH

Input High Voltage

2.0

Vcc

V IL

Input Low Voltage

-0.5

O.B

V

ILl

Input Load Current

10

/LA

Vcc

ILO

Output Leakage Current

±10

/LA

Vcc = 5.5V, chip deselected,
VOUT = +OAV to Vcc

Icc

Power Supply Current, Active

25

55

mA

ISB

Power Supply Current, Standby'

7.5

16

mA

CI

Input Capacitance 2

Co

Output Capacrtance2

Notes:
1 Applies only to chip enable with power down standby mode
2. ThiS parameter IS periodically sampled and is not 100% tested

AC CHARACTE RISTICS

V cc

= 5.0V

± 10%, T A

Parameter

7

pF

10

pF

Vcc = 5.0V, chip deselected, pin
under test at OV, T A = 25'C,
1=1 MHz

3. TYPical values are for TA=25°C and Vcc =5.0V

= O°C to 70°C (unless otherwise
R2332-2

Symbol

Min

= 5.5V

Vcc

Max

R2332-25
Min

Max

specified)
R2332-3

Min

Max

R2332-45
Min

tAVAl<

Address Valid to Address Don·t Care

200

250

300

450

tELEH

Chip Enable Low to Chip Enable High2

200

250

300

450

tAVQV

Address Valid to Output Valid (tAcd (Access)

t ELav

Chip Enable Low

tAVQX

Address Valid to Output (t OH) Invalid

10

10

10

10

tELax

Chip Enable Low to Output (teo) Invalid

10

10

10

10

tEHQZ

Chip Enable High to Output High Z (t OF)

10

teu

Chip Selection to Power Up Tlme2

tpo

Chip Deselection to Power Down Time2

t AVEL

Address Valid to Chip Enable Low

0

t GLaV

Chip Select Low to Output Valld3

10

tGHaZ

Chip Select High

to Output Valid (Access)2

to Output High Z3

Unit
ns
ns

200

250

300

450

ns

200

250

300

450

ns

70'

10

70'

100'

100'

70'

10
10

70'

90'
70'

10

10

ns
70'

ns
ns

0
90'

10

90'

ns

70'

10

70'

ns

Notes:
1. Test Conditions:
Output Load: 2 TTL Loads and 100 pF, Input Transnion Time: 20 ns; Timing Reference Levels: Input: 1.5V; Output: O.BV, 2.0V.
2. Mask-programmed for chip enable wnh power down standby mode.
3. Mask-programmed lor chip enable wrthout power down standby mode.
4. Add 20 ns for extended temperature devices (-40'C to +B5'C).

4-4

ns
ns

100'

100'

10

ns

0

0

0
90'

10
0

0

0

10

Max

32K (4K x 8) Static ROM

R2332A and R2332B
TIMING DIAGRAMS
READ CYCLE TIMING 1

(E HELD LOW)

1 - - - - - - - - IAVAX -----------1

AI~~~~~S ~~~~~'i1':x:'L'i1'o'ic"1':x:""1f.oc,&"1f.'&OQJ~*:-=--=--=--=--=--=--=--=--=--=--=-~A~D~D~R~E~S:;;-S:..-; . :VA~L~I~D:.-.:_-.:_-_-_-_-_-.:_-_-_i~':._=__=__=__=__=__=__=_= ~::
1 - - - - - IAVQV

----I

_IAVQX-j

Q (DATA OUT)

--~~~~~~~~-~~~~-----~~7,;~----VOH
PREVIOUS DATA VALID
DATA VALID
VOL

=l

READ CYCLE TIMING 2

I AVEL

ADDRESS
Ir-~---------A-D-D-R-E-S-S-V-A-L-ID---------- VIH
_ _ _ _ _ _ _ _ _ VIL
INPUTS .....CJU'-"-'u'-_+-_ _ _ _ _ _ _ _
..:.c::.::..;.=~.;.,:.:;;;::....

I _ - - - - - - -__ IELEH - - - - - - - f
i r - - - - - VIH

E (CHIP ENABLE)

Q (DATA OUT)

VIL

-----1--

DATA VALID

Vee SUPPLY lec - - - - - - - CURRENT I S B - - - - - - - - J

G (CHIP SELECT)
(SHOWN ACTIVE LOW)

TYPICAL CHARACTERISTICS
SUPPLY CURRENT VS AMBIENT TEMPERATURE
0

~

0

1

0

I

40

I

.2

3o

o

i
-WI

!

i

60

~Cfl/le
i

!

.1

60

,

50

j

~

"

.2

..,.

i

Y,o/Cq )

i

f---

1

t-l-

60

90

120

0

~

VS
10

AMBIENT TEMPERATURE
700

0

-

I

400

I
1
1

1

30 0

I _;125'C

200
100

--

-55'
0
·60

·30

.....-

"'\~
30

:""---1

60

I

Vee" 50V
2 TTL LOADS
CL " 100 pF
90

120

150"

TA-Amblent Temperature-OC

4·5

_I,

db)'~~\--

TA " 25'C
i

45

50

55

Vee-Volts

1

500

.

f----'Stsn
I

35 40

600

I

~~

150'

TA-Ambient Temperature-OC

I~

30

p..,c\\-.J 0

ACCESS TIME

I
/,-,_,+1;25 0
Standby TYPical
Vee == 5 OV

30

-

40

1

i
30

i

i

I

i

10 -

o

70

~
i

SUPPLY CURRENT VS SUPPLY VOLTAGE

60

6.5

70

32K (4K x 8) Static ROM

R2332A and R2332B
PACKAGE DIMENSIONS

24-PIN PLASTIC DIP

24-PIN CERAMIC DIP

0.530

t-- Q.4sij - - j

0 070

~.~~~

0.050
0.020

0.530

o.~ t-- Q.4sij--J

~~'IF'IFiI~f~:~~:

- r , - - - - - - - - - - . , 1~·160

)~

M~~pOtri

~
0.150
0.125

0.065

-1111-

0040 --u- 0.023
0.015

4-6

-I

1-0.110

0 032 REF

0.090

I

=

~h

+-

0.008
11---0.700----1
O.SOO

R2364A
Memory Products

'1'

R2364A
64K (8K x 8) STATIC ROM

Rockwell
DESCRIPTION

The R2364A2, R2364A25 and R2364A3 are 65,536-bit static
Read-Only Memories (ROMs), organized as 8,192 eight-bit bytes,
that offer maximum access times of 200, 250 and 300 nanoseconds, respectively. These ROMs are in industry-standard
24-pin, dual in-line packages, and are available in ceramic or
low-cost plastic. These fully-static 64K-bit ROMs are compatible
with industry standard microprocessors.

AO

All three R2364A ROMs operate totally asynchronously, and
require no clock input. These devices provide tri-state output
buffers for memory expansion. The R2364A ROMs offer TTL
input and output levels wnh a minimum noise immunity of 0.4
volts.

AI

The mask-programmable chip enable input (E/E) may be programmed to function as a chip select without power down
standby mode or as a chip enable with power down standby
mode. The active level of the enable input is also programmable.

A6

A2
A3
A4
AS

III
II:

~

II:

w

8i

~

65,536 BIT
ROM
CELL ARRAY

w~

00
~0
-

:)

III

!5
Q.

!:;
0

II:

QO
Q1
Q2
Q3
Q4
Q5
Q6
Q7

A7

FEATURES
• 8,192 x 8 organization
• Access time: 200 ns, 250 ns, and 300 ns (max.)
• Low power dissipation: 125 mW active, 37.5 mW standby
•
•
•
•
•
•

A8 A9 A10 A11 A12
R2364A Block Diagram

Drives two TTL loads and 100 pf
Single +5V ± 10% power supply
Totally static operation, no input clock required
Completely TTL compatible
Mask-programmable chip enable
Tri-state outputs for memory expansion

ORDERING INFORMATION
Part Number: R2364A-- - - [

Package:
C = Ceramic
P = Plastic
Temperature Range:
No letter = O'C to + 70°C
E = -40°C to +85'C

I

Power Down Standby Mode:
S = Yes
No letter = No

~ Access Time (Max):
Note: Submit ROM codes using
Rockwell ROM Code Order Form,
Order No. 2137.

A7

VCC

A6

A8

AS

A9

A4

A12

A3

EiE*

A2

A10

AI

All

AO

Q7

00

06

Ql
Q2'

Q5

GND

Q3

Q4

*Maak-programmable option

2 = 200 ns
25 = 250 ns
3 = 300 ns

R2364A Pin Configuration

Document No. 29000063
4-7

Data Sheet Order No. 063
Rev. 4, October 1984

II

R2364A

64K (SK x 8) Static ROM

ABSOLUTE MAXIMUM RATINGS'
Parameter

Symbol

Value

Supply Voltage

Vcc

-0.5 to +7.0

Input Voltage

V IN

-0.5 to +7.0

Vdc

Output Voltage

Vour

-0.5 to +7.0

Vdc

Temperature Under Bias
Commercial
Industrial

TA

Storage Temperature

TSTG

Power Dissipation

P

"NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this document is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

UnIt
Vdc

'C
-10 to +80
-50 to +95
-65 to +150

'C

W

1.0

DC CHARACTERISTICS
Vee = 5.0V ± 10%, T A =
Symbol

ooe to 70 e (unless otherwise specified)
0

Parameter

V OH

Output High Voltage

VOL

Output Low Voltage

Min

Typ3

204

Test Conditions

Max

Units

Vcc

V

Vcc

004

V

V cc

V

= 4.5V,
= 4.5V,

10H

=

-400 !LA

10L" 3.3 mA

V IH

Input High Voltage

2.0

Vcc

V IL

Input Low Voltage

-0.5

0.8

V

III

Input Load Current

10

!LA

Vcc = 5.5V. OV :s VIN :s 5.5V

I LO

Output Leakage Current

±10

!LA

Vce = 5.5V. chip deselected,
Vour = + OAV to Vcc

Icc

Power Supply Current, Active

25

55

mA

Vce

ISB

Power Supply Current, Standby'

7.5

16

mA

CI

Input Capacitance'

Co

Output Capacitance'

Notes:
1. Applies only to chip enable with power down standby mode.
2. This parameter is periodically sampled and is not 100% tested.

= 5.5V

7

pF

Vee = 5.0V, chip deselected, pin
under test at OV, T A = 25'C

10

pF

f

= 1 MHz

3. Typical values are for TA = 25°C and Vcc = 5.0V.

AC CHARACTERISTICS
= 5.0V ± 10%, T A = OOG to 70 e (unless otherwise specified)

Vec

0

R2364A2
Symbol

Parameter

Min.

Max.

R2364A25
Min.

Max.

R2364A3
Min.

tAVAX

Address Valid to Address Don't Care

200

250

300

tELEH

Chip Enable Low to Chip Enable High'

200

250

300

tAVQV

Address Valid to Output Valid (tACe) (Access)

200

250

200

Unit
ns
ns

300

ns

300

ns

tELQV

Chip Enable Low to Output Valid (Access)'

t AVQX

Address Valid to Output (t OH ) Invalid

10

10

10

tELQX

Chip Enable Low to Output (tco) Invalid

10

10

10

tEHQZ

Chip Enable High to Output High Z (tDF)

10

tpu

Chip Selection to Power Up Time'

t pD

Chip Deselection to Power Down Time'

tAVEL

Address Valid to Chip Enable Low

0

tGLQX

Chip Select Low to Output Invalid 3

10

90'

10

90'

10

90'

ns

tGHQZ

Chip Select High to Output High Z

10

70'

10

70'

10

70'

ns

70'

0

250

Max.

10

70'

ns
70'

100'

100'

Notes:
1. Test Conditions:
Output Load: 2 TTL Loads and 100 pF; Input Transition Time: 20 ns; Timing Reference Levels: Input: 1.5V, Output: O.BV, 2.0V.
2. Mask-programmed for chip enable with power down standby mode.
3. Mask-programmed for chip enable without power down standby mode.
4. Add 20 ns for extended temperature devices (-40'C to +85'C).

4-8

--

ns
ns

0

0

ns
ns

0

0
100'

10

ns

R2364A

64K (8K

8) Static ROM

X

TIMING DIAGRAMS
READ CYCLE TIMING 1 (e HELD LOW)
1_------_tAVAX - - - - - - - - - 1

~~m~~~======~~~~~~======t====
VI~
ADDRESS VALID
VIL

ADDRESS
INPUTS Q(

1 - - - - tAVQV - - - - I
_tAvax--j
PREVIOUS DATA VALID
DATA VALID
VOL
-===~~~~~~~~~~~~~t===========~~~~=========Vo~

Q (DATA OUT) _

-l

READ CYCLE TIMING 2

~~-~~I=t========~~~~~~===========
VI~
ADDRESS VALID
VIL

ADDRESS
INPUTS ~

1---------- tELE~ - - - - - - - 1

1-

Ir-----VI~

E (CHIP

ENABLE)

- - tGLQX

-l

;-~v

-J

-

_tELQ~

~~Ol>i>~

Q (DATA OUT) - - - - - , - , - HI z

tG~QZ
te~QZ

-

VIL

-

-.J)- HI Z ~::

C-

____
D_A_T_A_V_A_L_ID_ _ _ _

-1

_
t pu_ _ , - -

t pD
Vee SUPPLY lee - - - - - - - ,-------------------CURRENT Isa - - - - - - - - - '

' - - - - - - - - - TYPICAL CHARACTERISTICS
SUPPLY CURRENT VS AMBIENT TEMPERATURE

SUPPLY CURRENT VS SUPPLY VOLTAGE

0

70

60

60

50

50

-55'

"

-

~

I
I

~

40

i

~

30

I

I

~~l

J:l..c\\"oIe

YPlcat

20
10

.I 1

o-60

..1--

Standby TVPlcai

~

-30

0

30

60

20

+125'
V e~ ~ 50V

01--

-1-

90"

\

120

0

35

ISO"

-Jdb)'1?~\---

r:--sr-

40

TA-Ambient Temperature-OC

50

55

60

Vee-Volts

ACCESS TIME VS AMBIENT TEMPERATURE
700

600
500

[,CO'._or--t--S\.od~-ii1 ~

ACCESS TIME VS
AMBIENT TEMPERATURE

O35

700

150'

TA-Amblent Temperature-OC

40

45

50

55

60

Vee-Volts

600
600

l!!

L 400
" 300

~

200
100
-55'
0

-60

~

.-

-3~

;'1125'C
.,,~ V
30

60

~

Vee = 50V
2 TTL lOADS
CL = 100 pF
90

120

150'

TA-Ambient Temperature-°C
4·13

TA =j25'C
65

70

R2364B

64K (8K

X

8) Static ROM

PACKAGE DIMENSIONS
28-PlN PLASTIC DIP

[I~I~~]l
,

I

(1.420)
(1 380)

I'

(.115)
(.080)

~
(1.440)

$L~J-= ~~~~-'
_

I

(.160)

- - , (.140)L-(.810)

~~~('580)

!

~\ ~

(.015)

(.580)

(.155) (.085)
(.125) (.015)

4-14

h

(.085)

(.OiO)

(.150) (.080)
(.125) (.020)

(.015)

R23C64
Memory Products

'1'

R23C64
64K (8K x 8) CMOS ROM

Rockwell

PRELIMINARY
DESCRIPTION
The Rockwell R23C64 is an BK x B (65,536 bits) CMOS readon-memory (ROM) housed in a 2B-pin JEDEC standard package.
It is fabricated in CMOS technology to achieve high performance
with extremely low power dissipation. This device is available with
maximum access times of 150, 250, or 300 nanoseconds, latched
or non-latched chip selects, optional extended temperature range,
and packaged in ceramic or low-cost plastic.

til til
tIIW

w:z:

a:(J

AO-A12

The R23C64 is controlled via the chip enable (E) and the mask
programmable output enable (G/G/N) and chip selects (S1/S1/N
and S2/S2N). The address is latched on the falling edge of E,
allowing the R23C64 to operate on a multiplexed bus as well
as a non-multiplexed bus. The output enable and chip selects
control the output buffers, however, these buffers do not become
active until valid data is present from the internal data latches.
This prevents spurious, invalid outputs that increase power
dissipation. When E is high, the output buffers are in the high
impedance state and the address, output enable and chip select
pins are ignored (standby). E may also be held low indefinitely,
keeping the address latched and the output buffers under output enable and chip select control. The R23C64 is in a low-power
quiescient active mode when E is low and the other control
inputs (G, S1 and S2) are steady state.

o~
00(
0(-1

II:

~i!l

00
a:t..l
w

65,536 BIT
MEMORY
ARRAY

o

GIG

52/82

00·07

FEATURES
R23C64 Block Diagram

• B,192 x B organization
• JEDEC standard pinout
• Extremely low power
- Active 10 mW/MHz (max.)
- Active quiescent 50 p.W (max.)
- Standby 50 p.W (max.)
• Fast access times: 150 ns, 250 ns and 300 ns (max.)
• Mask programmable chip selects and output enable
• Latched addresses and (optional) latched chip selects
• Drives two TTL loads and 100 pF
• Single 5V ± 10% power supply
• Pin compatible with Mostek MK37000

NC
A12
A7
A6
A5
A4
A3
A2
A1
AO
00
01
02
GND

ORDERING INFORMATION
Part Number: R23C64 ___ _

---I
I

L Package:
C = Ceramic
P = PlastiC

1

Note: Submit ROM
codes using Rockwell
ROM Code Order Form,
Order No. 2137.

Temperature Range:
No letter = O°C to + 70°C
E = -40°C to +85°C
Access
15 =
25 =
3 =

2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

16
15

VCC
S2/S2/N"

51 1S'f/N ,
A8
A9
A11
G/G/N'
A10
E
07
06
05
04
03

• Mask-programmable option.
N = No effect on selection logic, however, voltage greater than
logic level shall not be applied.

Time (Max):
150 ns
250 ns

300 ns

R23C64 Pin Configuration

Document No. 29000M05
4-15

Data Sheet Order No. MM05
Rev. 2, October 1984

64K (8K x 8) CMOS ROM

R23C64
ABSOLUTE MAXIMUM RATINGS*
Parameter

Symbol

Value

Supply Voltage

Vee

-0.3 to + 7.0

Vdc

Input Voltage

VIN

-0.3 to Vee +0.3

Vdc

Outpul Voltage

VOUT

-0.3 to Vee +0.3

Vdc

Temperature Under Bias
Commercial
Industrial

TA

Storage Temperature

TSTG

Power Dissipation

P

°C
-IOto +80
-50 to +95
-55 to + 150
1.0

DC CHARACTERISTICS
= S.OV ± 10%, TA = OOC to

Vee

Symbol

'NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this document is not implied. Exposure
to absolute maximum rating conditions for extended periods may
affect device reliability.

Unit

Output High Voltage

VOL

Output Low Voltage

W

70 0 C (unless otherwise specified)

Parameter

VOH

°C

Min

Typ'

2.4

Max

Units

Vee

V

Vee

0.4

V

Vee

= 4.5V,
= 4.5V.

Test Conditions

V

= 5.5V, OV <

IOH

=

-200

~A

IOl = 3.2 mA

VIH

Input High Voltage

2.0

Vee

V il

Input Low Voltage

-0.3

0.8

V

III

Input Load Current

il

p.A

Vee

ILO

Output Leakage Current

±10

~A

Vee = 5.5V, chip deselected,
VOUT = +O.4V to Vee

lee1

Power Supply Current, Active

2

mA

lee2

Power Supply Current, Standby

10

~A

lee3

Power Supply Current, Active Quiescent

10

~A

CI

Input Capacitance (all but E)2

(E)

7
10

pF
pF

= 150 ns 1, Vee = 5.5V
= Vee - 0.5V; all other pins active
E = Vil
G = 51 = 52 = Steady State (Vll or VIH)
Vee = 5.0V, chip deselected, pin under
test at OV, TA = 25°C, I = 1 MHZ

Output Capacitance 2

10

pF

Co

Notes:
1. tElEH = 150 ns, all pins active, no loads, 1 ~ cycle time (tElEl = 1~).
2. This parameter is periodically sampled and is not 100% tested.
3. Typical values are lor TA = 25"C and Vee = 5.0V.

4-16

tElQV
E

VIN

< 5.5V

R23C64

64K (8K x 8) CMOS ROM

AC CHARACTERISTICS
Vee

= 5.0V

± 10%, TA

= OOG to 70

0

G (unless otherwise specified)
R23C64-15

Parameter

Symbol

Min

R23C64-25

Max

R23C64-3

Max

Min

Min

Max

Unit

IELEL

Cycle Time

220

365

465

ns

IELEH

Chip Enable Low 10 Chip Enable High

150

250

300

ns

60

100

150

IEHEL

Chip Enable High 10 Chip Enable Low

I ELOV

Chip Enable Low to Output Valid (Access)

t AVEL

Address Setup Time

I ELAX

ns
300

250

150

ns

0

0

0

ns

Address Hold Time

50

65

80

ns

t GVQV

Output Enable Valid to Output Valid

75

100

150

ns

I EHQX

Chip Enable High to Output Invalid

10

10

10

ns

t GXQX

Output Enable Invalid 10 Oulput Invalid

10

tEHQZ'

Chip Enable High to Output High Z

50

65

70

tGXQz'

Output Enable Invalid to Output High Z

60

75

90

ns

t F , tR

Rise and Fall Tlmes2

10

15

20

ns

10

ns

10

ns

Notes:
1 Test Conditions Output Load: 2 TTL Loads and 100 pF: Input Transition Time. 20 ns: Timing Reference Levels: Input 1 5V, Output 0 8V, 2 OV
2. Rise and Fall times stated are required for these high performance parameters only and may be relaxed for slower operation, e g , 100 kHz operalion.
3. G may be delayed up 10 t AVQV - tGLQV after Ihe falling edge of E wllhout Impact on I AVQV ' Data IS available at the Q outputs after a delay of tGLQV
from the falling edge of G, provided that E has been low (V,J and addresses have been valid for at least t AVQV - t GLQV '
4. t EHQZ , tGHQZ are specified from G or E, whichever occurs first.

,-----_ _ _ _ _ 9
TIMING DIAGRAM
READ CYCLE TIMING

tELEL

- E (CHIP

-

7

IF .

f-

IR

ENABLE)
VEL_

AD - A 13 (ADDRESS) Tl'T'X'n
Sl (CHIP SELECT)' ~

'--

I - IEHEL -

tELEH

.NlllX

VALID

Ullll'

~

IELAX
G (OUTPUT ENABLE)
Sl (CHIP SELECT)2

VALID'

f - - I GVQV - -

HIZ

Q (DATA OUT )

I•

--

l>ATA
VALID

-I

~LQV

NOTES:
1. CHIP SELECTS (Sl/51 AND S2/S2) LATCHED.
2. CHIP SELECTS (Sl/51 AND S2/S2) NOT LATCHED.

4-17

-j

___ t EHQX ' t Gxax

HIZ
r--IEHOZ
I Gxaz

64K (8K x 8) CMOS ROM

R23C64

PACKAGE DIMENSIONS
28·PIN CERAMIC DIP

28·PIN PLASTIC DIP

I

(.550)

(530)

,

I

(1.420)
(1.380)

\nT1:nm"TTTTTl"TTTT"'~....J~
I'

(.115)

'I

(1.470)
(1.440)

(.08oj

,~jtt~
~I!l ,~Jt:
(.010)

(.022)
(.015)

~

\ "\
(
(155) (.065)
(i2sj" (.015)

-

(160)
. , (.140)L-(.610)

~~t-W=;!

1t:- jft::ijt~"t 1~7t:::
(.065)

)

4·18

(.015)

_.(.090)

(.150) (.060)
(.125) (.020)

R23128
Memory Products

'1'

R23128
128K (16K x 8) STATIC ROM

Rockwell
DESCRIPTION

G/G/N-------------,
S1/S1/N------------,

The R23128-25 and R23128-3 are 131 ,072-bit static Read-Only
Memories (ROMs), organized as 16,384 eight-bit bytes, that offer
maximum access times of 250 and 300 nanoseconds, respectively. These ROMs are in industry-standard 28-pin, dual in-line
pacKages, and are available in ceramic or low-cost plastic. These
fully-static 128K-bit ROMs are compatible with industry standard
microprocessors.

E----------.-----.

AO

The R23128 ROMs operate totally asynchronously, and require
no clock input. The mask-programmable chip select (81/81)
input allows two 128K ROMs to be OR-tied without external
decoding. These devices provides tri-state output buffers for
memory expansion. The R23128 ROMs offer TIL input and output levels with a minimum noise immunity of 0.4 volts.

A1
A2
A3
A4
AS
A6
A7

The chip enable Input (E) functions as a chip enable wtth power
down standby mode. When this line is high the chip is disabled
and enters a low power standby state.

V>

a:

a:

W

W

0o~

131,072 BIT
ROM
~
CELL ARRAY

U'"
Wu-

00
'!:~

uu-

:::>

III

>-

:::>
0..

0-

>:::>
0

a:

00
01
02
03
04
05
06
07

AS

FEATURES
• 16,384 x 8 organization bytes
• Access time: 250 ns and 300 ns (max.)
• Low typical power dissipation IS 100 mW active, 20 mW
standby
• Drives two TTL loads and 100 pF
• 81ngle +5V :<:: 10% power supply
• Totally static operation, no Input clock required
• Completely TIL compatible
• Three mask-programmable chip select inputs
• Tri-state outputs for memory expansion

R23128 Block Diagram

NC
A12

ORDERING INFORMATION
Part Number: R23128 ___ _

L

PaCkage:
C = Ceramic
P = PlastiC

Note' Submit ROM
codes uSing Rockwell
ROM Code Order Form,
Order No 2137

L

Temperature Range'
No letter = O°C to + 70°C
E = -40°C to -'-85°C

vcc
SllS1lN"

A7

A13

A6

A8

A5

A9

A4

All

A3

GIGIN"

A2

Al0

Al

E

AD

07

00
Ql

06

Q2

04

GND

Q3

Q5

"Mask-programmable option.
N = no effect on selectlonienable logic, however, voltage
greater than logiC levels shall not be applied

Access Time (Max)'
25 = 250 ns
3=300ns

R23128 Pin Configuration

Document No. 29000M03
4-19

Data Sheet Order No. MM03
Rev. 3, October 1984

II

R23128

128K (16K

x 8) Static ROM

ABSOLUTE MAXIMUM RATINGS·
Parameter
Supply Vollage
Input Voltage
Output Voltage

Symbol

Value

Unit

Vee

-0.5 to +7.0

Vde

VIN

-0.5 to +7.0

Vdc

VOUT

-0.5 to +7.0

Temperature under Bias
Commercial
Industrial

TA

Storage Temperature

T STG

Power Dissipation

P

·NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device .• This is
a stress rating only and functional operation of the device. at
theSe or any other conditions above those indicated in the operational sections of this document is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

Vde

'c
-10to +80
-;50 to +95
-65 to +150
1.0

'c
W

DC CHARACTERISTICS
Vce = 5.0V ± 10".... , TA = O°C to 70°C (unless otherwise specified)
Symbol

Parameter

Typ2

Min

VOH
VO'l

Output HIGH Voltage

V IH

Input HIGH Voltage

2.0

V il

Input LOW I'/ollage

-0.5

III

2.4

Output LOW Voltage

Max

Test Conditions

Units

Vec

V

V cc

0.4

V

Vcc

Vec

V

= 4.5V,
= 4.5V,

10H
10l

= -400 /LA
= 3.3 mA

0.8

V

Input Load Current

10

/LA

Vee = 5.5V, OV SV IN s55V

ILO

Output Leakage Current

±10

/LA

Vec = 5 5V, chip deselected
VOUT = +OAVtoVee

Icc

Power Supply Current, Active

20

55

mA

Vcc = 5.5V

158

Power Supply Current, Standby

7.5

16

mA

7

pF

10

pF

CI

Input Capacttance'

Co

Output Capacitance'

Note:
1. This parameter is periodically sampled and is not 100% tested.

V cc = 5.0V, chip deselected, pin
under test at OV, T A = 25°C
f = 1 MHz

2. Typical values are for TA = 25°C and Vce = 5.0V

AC CHARACTERISTICS
Vee = 5.0V ± 10%, T A. = O°C to 70°C (unless otherwise specified)

R23128-3

R23128-25
Symbol

Parameter

Max

Min

Min

Max

Units

tAVAl(

Address Valid to Address Don't Care

250

300

n~

tElEH

Chip Enable Low to Chip Enable High

250

300

ns

t AvOV

Address Valid to Output Valid (tACe! (Access)

250

300

ns

250

300

ns

tELQV

Chip Enable Low to Output Valid (Access)

tAvox

Address Valid to Output (to H) Invalid

10

10

tELQX

Chip Enable Low to Output (teo) Invalid

10

10

tEHOZ

Chip Enable High to Output High Z (tOF)

10

t pu

Chip Selection to Power Up Time

tpo

Chip Deselection to Power Down Time

t AVEl

Address Valid to Chip Enable Low

0

tGlov

Chip Select Low to Output Valid

10

90 2

10

go>

ns

t GHOZ

Chip Select High to Output Hig/i Z

10

702

10

702

ns

Notes:
1. Test CondiliOns:
Output load 2 TIL loads and 100 pF
Input transition time: 20 ns
Timing reference. levels: Input· 1.5V; Output: 0.8V, 2,OV
Add
20 ns for extended temperature deVices (- 40°C to + 85°C)
·2

70

10

ns
ns
70

100

100

ns
ns

0

be delayed up to tAVQV-tGLQV after the failing edge of E
Without Impact on tAVOV ' Data 15 avall~le at the Q oute.uts after a
delay of tGlOV from the falling edge of G, provided that E has been
low (Vld and addresses have been ~alld lor at least tAVQV-tGlQV
4 tGHQZ and tEHQZ are specified from G or E, whichever occurs first.

3.

4-20

G may

ns
ns

0

0

R23128

TIMING

DIAGR{AM~DDRESS

READ CYCLE
TIMING 1

INPUTS

(EHELDLOW)

---f-----

128K (16K

t

AVAX

x 8) Static ROM

~----

------.Ji_--- V,H

- - _.... :

~

Q (DATA OUT)

t AVQV _ _ _ _ I

=~~~~_~~tA~V~QX~==~~~~========~~~~========

'li~C=t========~~~~~~!:=========
--------f

ADDRESS
INPUTS

iI!i

1_ _ _ _ _ _ _ _ _ _

VOH
VOL

V,H
V ,L

tElEH

I , . . . - - - - V,H

E (CHIP ENABLE)
READ CYCLE
TIMING 2

tEHQZ

V,L

1_
HI

Q (DATA OUT)

Vee SUPPLY Icc
CURRENT Isa

V
IL

z-

V OH
VOL

________,1- tOLQY
~

G/Si CHIP SELECTS

(ACTIVE) _ _ _--'

(SHOWN ACTIVE LOW)

TYPICAL CHARACTERISTICS
SUPPLY CURRENT VS AMBIENT TEMPERATURE

SUPPLY CURRENT VS SUPPLY VOLTAGE

70

70

0

60

0

50

~

0
0
20

~

-55"
.... -'r--,Active 7'YPlCBI

J tr-- -_I

40

30

-

20

+125'

o --=I--StandbY TYPlca;'-0
- 60' - 30'

0'

30'

60'

~'_~.l-5 OV

90'

120'

10

ACCESS TIME VS AMBIENT TEMPERATURE

150'

700

TA-Amblent T8mperature-'C

o

--

3 5 4.0

""\IV.1~\_-

J.- T'T'C

Standby TY!!~,! _

45

50

55

Vee-Volta
600

500

L400

J

300

;'1125'C

200

~

100

o

~Yee = 50Y
l

-55' . -

·60

~~

·30

30

4-21

60

2 TTL LOADS
CL ~ 100 pF
90

120

150'

6.0

65

70

128K (16K x 8) Static ROM

R23128
PACKAGE DIMENSIONS

28-PIN PLASTIC DIP

[~f~j~~~~]i

I'

(1.420)
(1.380)

I'

(.115)
(.080)

'I

(.010)

jt

('070)
(.040)

(.022)
(.015)

I I

--j

(.110)

~

f--- (.620) ----I

(.160)

-

---1I -(.140)L-(.610)

~~~
1~-+-(·015)
~lt::::jt~,F~ :=" ,~,

JifflHN~~~R,. " i
(.055)

(1.470)
(1440
. )

(.008)

(.590)

(.155) (.065)
(.125) (.015)

4·22

_

(.065)

)

(.015)

~
. 90)

(.150) (.060)
(.125) (.020)

R23C128
Memory Products

'1'

R23C128
128K (16K x 8) CMOS ROM

Rockwell

PRELIMINARY
DESCRIPTION
The Rockwell R23C128 is a 16K x 8 (131,072 bits) CMOS readonly-memory (ROM) housed in a 28-pin JEDEC standard
package. It is fabricated in CMOS technology to achieve high
performance with extremely low power dissipation. This device
is available with maximum access times of 150, 250, or 300 nanoseconds, latched or non-latched chip select, optional extended
temperature range, and packaged in ceramic or low-cost plastic.

VI VI
Vlw

w:z:

II:(J

AO-A13

01-

OC(
c(....I

The R23C128 is controlled via the chip enable (E) and the mask
programmable output enable (G/G/N) and chip select (S1/S1/N).
The address is latched on the falling edge of E, allowing the
R23C128 to operate on a multiplexed bus as well as a nonmultiplexed bus. The output enable and chip select control the
output buffers, however, these buffers do not become active until
valid data is present from the internal data latches. This prevents
spurious, invalid outputs that increase power dissipation. When
E is high, the output buffers are in the high impedance state
and the address, output enable and chip select pins are ignored
(standby). E may also be held low indefinitely, keeping the
address latched and the output buffers under output enable and
chip select control. The R23C128 is in a low-power quiescent
active mode when E is low and the other control inputs (G and
S 1) are steady state.

II:

~~

00

II:(J

w

o

131,072 BIT
MEMORY
ARRAY

GIG

QO-Q7

FEATURES

R23C128 Block Diagram

• 16,384 x 8 organization
• JEDEC standard pinout
• Extremely low power
- Active 15 mW/MHz (max.)
- Active quiescent 50 p.W (max.)
- Standby 50 p.W (max.)
• Fast access times: 150 ns, 250 ns and 300 ns (max.)
• Mask programmable chip select and output enable
• Latched addresses and (optional) latched chip select
• Drives two TTL loads and 100 pF
• Single 5V ± 10% power supply

NC
A12
A7
A6
AS
A4
A3
A2
A1
AD
QO
Q1
Q2
GND

ORDERING INFORMATION
Part Number: R23C128 ___ _

-'-1
I
I

L Package
C = Ceramic
P = PlastiC

L.....

Note' Submit ROM
codes using Rockwell
ROM Code Order Form,
Order No. 2137

Temperature Range
No letter = O°C to + 70°C
E = -40°C to +85°C

1
2
3
4
5
6

7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

16
15

VCC
S1/Sf/W
A13
A8
A9
A11
G/GIW

A10

E
Q7
Q6
QS
Q4
Q3

'Mask-programmable option.
N = No effect on selection logic, however, voltage greater than
logic level shall not be applied.

Access Time (Max).
15 = 150 ns
25 = 250 ns
3=300ns

R23C128 Pin Configuration

Document No_ 29000M19
4-23

Data Sheet Order No_ MM19
October 1984

128K (16K x 8) CMOS ROM

R23C128
ABSOLUTE MAXIMUM RATINGS·
Parameter
Supply Voltage
Input Voltage
Output Voltage

Symbol

Temperature Under Bias
Commercial
Industrial

Value

·NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This Is
a stress rating only and functional operation of the device at
these or any other conditions above those Indicated In the
operational sections of this document Is not Implied. Exposure
to absolute maximum rating conditions for extended periods may
affect device reliability.

Unit

Vee

-0.3 to +7.0

Vdc

VIN

-0.3 to Veo +0.3

Vde

VOUT
TA

- 0.3 to Voo + 0.3

Vdc
'C

-10 to +80
-so to +95

Storage Temperature

TSTG
P

Power Dissipation

-SSto +150
1.0

'C

W

DC CHARACTERISTICS
Vee - 5.0V ± 10%, TA
Symbol

•

ooe to 70°C (unless otherwise specified)
Parameter

Max

Units

Vec
0.4

V

Voo - 4.SV, 10H • - 200 p.A

V

Vco = 4.SV, 10L = 3.2 mA

Input High Voltage

2.0

V

VIL

Input Low Voltage

-0.3

Vcc
0.8

ILl
ILO

Input Load Current

tl

p.A

Vee • S.SV. OV

Output Leakage Current

tl0

p.A

Vee - S.5V. chip deselected,
VOUT • +0.4V to Vce

Output High Voltage

VOL
VIH

Output Low Voltage

Min

Typ3

2.4

VOH

Tilt Conditione

V

< VIN < S.5V

1001

Power Supply Current. Active

3

mA

tELQV • 150 nsl, Voe • 5.SV

1002

Power Supply Current, Standby

10

p.A

'E

1003

Power Supply Current, Active Quiescent

10

p.A

CI

Input Capacitance (all but 'E)2
('E)
Output Capacitance2

7
10

pF
pF

10

pF

Co
Note.:
1. tELEH • ISO ns, all pins active, no loads, 1 P.s cycle time (tELEL • 1 p.a).
2. This parameter Is periodically sampled and Is not 100% tested.
3. Typical values are lor TA • 2S'C and Veo = 5.0V.

4·24

= Voo - 0.5V; all other pins active
~
~. 1· Steady State (VIL or VIH)

'E -

Vee - 5.0V, chip deselected, pin under
test at OV, TA • 2S'C, I . 1 MHZ

128K (16K x 8) CMOS ROM

R23C128
AC CHARACTERISTICS
vcc = 5.0V ± 100Al, TA = O°C to 70°C (unless otherwise specified)
R23C128-15
Parameter

Symbol

Min

R23C128-25

Max

Min

Max

R23C128-3
Min

Max

Unit

tELEL

Cycle Time

220

365

465

ns

tELEH

Chip Enable Low to Chip Enable High

150

250

300

ns

tEHEL

Chip Enable High to Chip Enable Low

60

100

150

tELOV

Chip Enable Low to Output Valid (Access)

t AVEL

Address Setu'p Time

tElA)(

150

ns

250

300

ns

0

0

0

ns

Address Hold Time

50

65

80

ns

tovov

Output Enable Valid to Output Valid

75

100

150

ns

tEHOX

Chip Enable High to Output Invalid

10

10

10

ns

toxox

Output Enable Invalid to Output Invalid

10

10

10

tEHOZ4

Chip Enable High to Output High Z

50

60

70

ns

toxoz4

Output Enable Invalid to Output High Z

60

75

90

ns

t F, tR

Rise and Fall Tlmes2

10

15

20

ns

ns

Notes:
1. Test Conditions' Output Load. 2 TTL Loads and 100 pF, Input Transition Time' 20 ns, Timing Reference Levels. Input: 1 5V; Output: O.BV, 2.0V.
2. Rise and Fall times stated are required for these high performance parameters only and may be relaxed for slower operation, e.g., 100 kHz operation.
3. G may be delayed up to tAVOV -tOLOV after the failing edge of E Without impact on tAVO V' Data IS avaliable at the Q outputs after a delay of IaLOV
from the failing edge of G, provided that E has been low (VIJ and addresses have been valid for at leasttAvav -toLay'
4. tEHOZ' tOHOZ are specified from G or E, whichever occurs first.

,..----------0
TIMING DIAGRAM
READ CYCLE TIMING

tELEL

E (CHIP

-

t;

~

ENABLE)
_ I EHEL _
VEL_

AO - A 13 (ADDRESS)
SI (CHIP SELECT)'

~
-

~

IELEH

nww

VALID

IDm'

tElAX

G (OUTPUT ENABLE)
SI (CHIP SELECT)2

VALID

-

- tGVQV - Q (DATA OUT)

HIZ

DATA
VALID

IeLQV
I

NOTES:
1. CHIP SELECT (51/51) LATCHED.
2. CHIP SELECT (51151) NOT LATCHED.

4-25

-

__ I EHQX ' I GXQX
HI Z

I-~EHQZ
I GXQZ

128K (16K x 8) CMOS. ROM

R23C128

PACKAGE DIMENSIONS
28-PIN CERAMIC DIP

28-PIN PLASTIC DIP

[I~]~]l
(1.420)

1 - - - - - (1.380)

I

(.550)

(.530)

'TnTTnTTTTTTI"TTTnITTTT'rTTTT"'-.-l

(.115)

---'I

(.080)

I"

::.::
.

(.180)

-1

r-:+(.008)"" ~~~=~
~~LJ

I 1 (.110)
--l ~

(.140)1.-(.810)
1,--(·590

I-L

~ (.590)--1

(.085)

(.155) (.085)
(.125) (.015)

4-26

(.015)

(.090)

(.125) (.020)

(.015)
(.008)

R23256 and R23257
Memory Products

'1'

R23256 AND R23257
256K (32K x 8) STATIC ROMS

Rockwell

PRELIMINARY
DESCRIPTION
The R23256 and R23257 are 262,144-bit static Read-Only
Memories (ROMs), organized as 32,768 eight-bit bytes, that offer
maximum access times of 200 nanoseconds. These ROMs are
in industry-standard 28-pin, dual in-line packages, and are
available in ceramic or low-cost plastic. These fully-static 256K-bit
ROMs are compatible with industry standard microprocessors
and are designed for installation in systems requiring highperformance large-capacity storage and simple interfacing.

SlISlIN'

A12
A7
A6
A5
A4
A3
A2
Al
AO
QO
Ql
Q2

The R23256 and R23257 ROMs operate totally asynchronously,
and require no clock input. These ROMs offer TTL input and
output levels with a minimum noise immunity of 0.4 volts. The
R23256 has a Chip Select (51151) input which allows two of
these ROMs to be wire-ORed without external decoding. The
R23256 also has an Output Enable (GIG) input to eliminate bus
contention in multiple-bus systems. The R23256 has two Chip
Select (51151 and 52/52) inputs which allow up to four of these
ROMs to be wire-ORed without external decoding.
The chip enable input (E) functions as a chip enable with power
down standby mode. When this line is high the chip Is disabled
and enters a low power standby state.

GND

26
27
26
25
24
23
22
21
20
19
18
17
16
15

vee
A14
A13
A8
A9
All

GIG'
Al0

E
Q7
Q6
Q5
Q4
Q3

R23256

The R23256 is pin compatible with the 2764 EPROM and the
R23257 is pin compatible with the 2564 EPROM, which
eliminates the need to redesign printed circuit boards for volume
mask programmable ROMs after prototyping with EPROMs.
S2/tiIN'

FEATURES

A13
A7
A6
A5
A4
A3
A2
Al
AO
QO
Ql
Q2

• 32,768 x 8 organization
• Access times: 200 ns, 250 ns, and 450 ns (max)
• Low max. power dissipation: 400 mW (active), 100 mW
(standby)
• Drives two TTL loads and 100 pF
• Single + 5V ± 10% power supply
• Totally static operation, no input clock required
• Completely TTL compatible
• Mask-programmable chip select/output enable lines
• Tri-state outputs for memory expansion
• R23256 pin compatible with 2764 EPROM
• R23257 pin compatible with 2564 EPROM

-t

1
2
3
4
5
6
7
8
9
10
11
12
13
14

ORDERING INFORMATION

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

16
15

vee
A14
Sl/S1/N'

A8
A9
A12

E
Al0
All
Q7
Q6
Q5
Q4
Q3

Part Number: R23256 ___ _

R23257 ___ _

R23257

Lpa~k!g~eramic
L

NOle: Submit ROM
codes using Rockwell
ROM Code Order Form,
Order No. 2137.

P = Plastic

'Mask-programmable option.
N = No effect on selection logic, however, voltage greater
than logiC level shall not be applied.

Temperature Range:
No letter = O°C to + 70°C
E = -40°C to +85°C
Access
20 =
25 =
45 =

Time (Max):
200 ns
250 ns
450 ns

R23256 and R23257 Pin Configurations-

Document No. 29000M10
4-27

Data Sheet Order No. MM10
September 1984

II

R23256 and R23257

256K (32K x 8) Static ROM
J

ABSOLUTE MAXIMUM RATINGS*
Parameter

Symbql

Supply Voltage

Vcc
,,'

Input Voltage
. Output Voltage

'Value

Unit

-0.5 to + 7.0

Vdc

,-

-VIN

-0.510 +7.0

Vdc

VOUT

-0.5 to + 7.0

Vdc

'l'emperature'under Bias
Commercial
Industrial

TA

Storage Temperature

TSTG

Power Dissipation

P

·NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damllge to the d~yice. 'This is
a stress rating only and functional opera,ion pf t~e device at
these or any other conditions aboye those indicated in the
operational sections of this docl\ment is not implied. Exposurei
to absolute maximum rating conditions for extended periods may
affect device reliability.

·C
-10to+80
-50 to +95
-65 to +150

·C

1.0

W

DC CHARACTERISTICS
Vee = 5.0V ±10%, TA = o·e to 70·e (unless otherwise specified)
Symbol

Parameter·

VOH

Output HIGH Voltage

Min.

Max

Units

2.4

Typ

Vcc

V

Vcc '= 4.5V, 10H = -1.0 mA

Test Conditions

Vee = 
?

Nole: X means this bit (bit 7) is a "don't care" bit except lor PNT and TAIL on 10957 only. The hex codes shown assume bit 7 is a zero.

5-7

Alphanumeric Display Controller

10937 • 10957
POWER·ON RESET (POR)

SEGMENT DRIVERS (SGA-SGP)

The Power-On Reset (PaR) initializes the internal circuits of the
10937 or 10957 ADC when power (Voo is applied. The following conditions are established after a Power-On Reset:

Sixteen (16) Segment Drivers are provided (SGA-SGP), plus
the decimal point (PNT) and comma tail (TAIL). The segment
outputs are internally decoded from the 8-bit characters in the
Display Data Buffer by means of a 64 x 16-bit PLA. The Segment Driver Allocations are shown in Figure 2. Data codes and
their corresponding segment patterns are shown in Figure 3.
Timing characteristics for the segment outputs are shown in
Figure 1. See paR for the Power-On Reset state of these drivers.

a. The Digit Drivers (ADl - AD16) are in the off state (floating).
b. The Segment Drivers (SGA - SGP) are in the off state
(floating). This includes PNT and Tail.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 16 (a bit code value of 0).
e. The Buffer Pointer points to the character controlled by AD1.

DIGIT DRIVERS (AD1-AD16)

NOTE

The sixteen Digit Drivers (ADl - AD16) are used to select each
of the display digits sequentially during a refresh scan. Display
segments will be illuminated when both the Digit Drivers and
Segment Drivers for a particular character are energized
simultaneously. The timing characteristics of both the digits and
segments are shown in Figure 1. See paR for the Power-On
Reset state of these drivers.

For 14-segment displays, SGA is used for the top segment
and SGF is used for the bottom segment. SGB and SGE
can be floated.

TYPICAL SYSTEM HOOK-UP

Table 4. Additional Codes for PNT and Tail On 10957
DATA WORD
BINARY

HEX

01101100
01101110

6C
6E

Figure 4 shows the 10937 or 10957 as it would be connected
to a V-F display when driven by a host system. EK is determined by the V-F display specifications and Rc is selected to
provide proper biasing current for zeners. Pull down resistors
RA and RG are determined by the interconnection capacitance
between the device and the display.

CHARACTER
, (Tail only)
Blank

o

j)

o

PNT } SEE
TAIL TABLE 4

PNT }SEE
) } TAIL TABLE 4

16-SEGMENT

14-SEGMENT

Figure 2. Segment Driver Allocations

5-8

Alphanumeric Display Controller

10937 • 10957

00

01

I 08 I I
I-I I 1- -I
I
1-

I
-I 09

--

I
I- -

OB

1
I-

OD

I
I-

OE

--

06

11

I
I

I 19 \1
I
I lA I

fJ71

I- --I

OF

I

lB

lC

I
I-

I 16 I I

I

IE

II

\1

I I 17 I 1IF
I- - I 1/\1

23

\

24

\

-

26

I II 38 I I
-I
II I 1--

31

2A

\11
11\

32 1-- 3A

1 I 2B

1

29

I I
-1-1

1I
-1-1

125 1 II
I II-I
-

1\

30

\
I

\1

22

I
\

28

--

1\/1 I 1
I I 15 I- - 1 10
1\

21

\1

I
I

14

20

1\

I 12 I
1-\
I
-I I 13 I
--I
1-\

I 10C I
I- -I- I

04

05

I 18 \1

I I OA
I-I I

02

03

I
I
--

I

10 1--

39

--

--

-

-1-

33

I
--I 3B I

----

34

I I 3C I
--I
I
--

--

35

1
--I

6C'

1

2E
\1
---36
11-\1 6E' Blank

-I

3D

3E

--

I

27

2F

--

I I
--I

I

2C

2D

I
I

I
I

--\

\
--

I 3F
1

37

-

I

I

16-Segment Display
00

01

I 08 I I
I I I 1- -I
I 09
1- -I

02

03

06

07

11
I-I OA I

-

I
I-

OB

I
I-

OD

1
I-

OE

I -I

OF

1

-

.

1-\

13

I
--I

lB

14

I
I

lC

1-\

Noles: Bit 7 of the data byte
= 10957 only.

IS

1\/1
1\

I
I
I-

I

15

20

i

1/\1

21

\1

I 1

I
1-

23

\

\

24

I 25 I II
I II-I
1\

IF

26

27

-

I II
II
- I

38

2A

\11
11\

32 1-- 3A

I

-1-

39

I-I

-

33

---- 34

35

I
--I 3B I
1 I 3C I
--I
I
I
--I

3D

--

-

1

2E
\1
---- 36
3E
1-\1 6E' Blank
1=-=1

I

I
-I

=-=1

-

6C'

--

1-

I

2C

2D

I
1

I
-

31

-1-1

-1-1

30

29

I I 2B

11

\

\
I

22

I

28

-

IE

II

I 17 I
1

I

I I
I- I lD

116 I I
\1

\1
1\

I I 19 \1
I- \1
I
1 I lA I

I 12
I

II

I

I

11

I loc 1
1 I I-

04

05

1
I

I

10 1_-' 18

2F

I
I

37

1

I

3F

\

-

\
-

1

I

14-Segment Display
a "don't care" bit except for PNT and TAIL on 10957. Data byte hex codes shown assume bit 7 is a zero.

Figure 3.

Display Segment Driver Character Patterns

5·9

Alphanumeric Display Controller

10937 • 10957

+5

15V

Vss

DATA~----------------~

10937 OR 10957

SCLK~----------------~

VDD ADX

SGX

POR

16

16

TYPICAL

1'"'"'::=:::-:-:-If-JVo./\r--t ANODE
Rc

TYPICAL
GRID
(DIGIT)
DRIVER
CIRCUIT

RA

(SEGMENT)
DRIVER
C RCUIT

Ra

VDD

VACUUM FLUORESCENT
DISPLAY

-V D1SP

Figure 4.

Partial System Schematic

5-10

HOST
SYSTEM

10938 • 10939

'1'

10938 AND 10939
DOT MATRIX DISPLAY CONTROLLER

Rockwell
DESCRIPTION

FEATURES

The Rockwell 10938 and 10939 Dot Matrix Display Controller
is a two-chip MOS/LSI general purpose display controller system
designed to interface to dot matrix displays (vacuum-fluorescent
or LED).

• 20-character display driver cascadable to 80
• Standard 5 x 7 character font. Custom fonts available by
special order
• Separate cursor driver output

The two-chip set will drive displays with up to 35 anodes (dots)
and up to 20 grids (characters) plus a cursor. The chips can be
cascaded to drive larger displays of as many as 80 characters.
An internal PLA-type decoder provides character decoding and
dot pattern generation for the full 96-character ASCII set and
an additional 32 special characters.

• Direct drive capability for vacuum-fluorescent displays
• 128 x 35 PLA provides segment decoding for full 96-character ASCII set, plus 32 special characters
• Serial or parallel data input for 8-bit display and control
characters
• Brightness, refresh rate, and display mode controls

ORDERING INFORMATION
Part
Number

Package
Type

10938P
10938PE
10939P
10939PE

Plastic
Plastic
Plastic
Plastic

• 40-pin DIP
Temperature
Range (OC)

o to
-40 to
o to
-4010

I

+70
+85
+ 70
+85

20-CHARACTER 5 x 7 DOT MATRIX DISPLAY
SG01-SG35

STROO-STR19

CURSOR

10938

10939
IANODE DRIVERS AND LATCHES ~
. I INVE:SION
I LOGIC

I t

t
1128 x 35 PLAI

LEVEL
DETECT
LOGIC

+~~
LEVEL

8-BIT SHIFT
REGISTER

GRID DRIVERS

f
DATA-LOAD
CONTROL
LOGIC
SCLK-DIS

~5~~8T

-

,.....-20 x 8
RAM
~

t
I
HOST

Block Diagram of 10938 and 10939

Document No. 29000096
5-11

Data Sheet Order No. 096
Rev. 3 October 1984

Dot Matrix Display Controller

'10938 • 10939
INTERFACE DESCRIPTION
10938 Pin Functions
Signal Name

Pin No.

Vss
SG01-SG35
SCLK-DIS
DATA-LOAD
Vee
VGG

2
3-25,27-38
39
40
1
26

10939 Pin Functions

Function
Power and signal reference
Anode driver outputs
Serial data shift clock
Serial data output/latch control
DC Power
Display voltage

DATA-LOAD
SCLK-DIS
SG01
SG02
SG03
SG04
SG05
SG06
SG07
SG08
SG09
SG10
SG11
SG12
VGG
SG13
SG14
SG15
SG16
SG17

Voo

V••
SG35
SG34
SG33
SG32
SG31
SG30
SG29
SG28
SG27
SG26
SG25
SG24
SG23
SG22
SG21
SG20
SG19
SG18

Signal Name

Pin No.

,; Function

Vss
Vee
CLOCK
CURSOR
MASTER
SIP
SOP
00-07
'LD
POR
SCLK-DIS
DATA-LOAD
STROO-STR19
VGG

36
37
38
14
39
3
2
6-13
5
4
1
40
15-34
35

Power and signal reference
DC Power
Synchronization Clock
Cursor drive output
Master/Slave Mode control
Sync Input
Sync Output
Serial or parallel data input
Input data strobe
Power-on reset
Serial data shift clock
Serial data output/latch control
Grid Driver Outputs
Display voltage

SCLK-DIS
SOP
SIP
POR
LD
DO
01
02
03
04
05
06
07
CURSOR
STR19
STR18
STR17
STR16
STR15
STR14

10938 Pin Configuration

DATA-LOAD
MASTER
CLOCK
Voo

V••
VGG

STROO
STROl
STR02
STR03
STR04
STR05
STR06
STR07
STR08
STR09
STR10
STRll
STR12
STR13

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS·
10939 Pin Configuration

Voltages are referenced to Vss
Parameter
Operating Temperature
Commercial
Industrial
Storage Temperature

Symbol

Value

o to

Unit

Tc
Ti

+70
-40 to +85
-55 to +125

·C
·C
·C

Operating Voltage

Vee

-22to-18

Vdc

Operating Display Voltage

VG",

-50

Vdc

-

'NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

5-12

Dot Matrix Display Controller

10938 • 10939
DC CHARACTERISTICS
All voltages referenced to Vss
Parameter

Notes

Input DO-D7, LD, SIP
Logic "I"
Logic "0"

2

Input POR
Logic "I"
Logic "0"

2

Output SOP
Logic "I"
Logic "0"

2

Output Grids, Cursor, and Anodes
Logic "I" (I,oad = 10 mA 10939, 2 mA 10938)
Logic "0" (I,oad = 0 mA)

1

Symbol

Min

Typ

Max

Unit

V,H
V ,l

-1.2
Voo

+0.3
-4.2

V
V

V,HPO
V,lPO

-3.0
Voo

+0.3
-10.0

V
V

VOHSY
VOlSY

-12
Voo

Vss
-4.2

V
V

V OH
VOL

-1.5
VGG

0.95

V
V

Vss
X

VGG

Notes: 1. Designates characteristics for both 10938 and 10939
2. Designates characterlslics for 10939

OPERATING CURRENTS
Maximum

Parameter

Industrial
TA = -40°C
Voo = -22 Vdc
VGG = -50 Vdc

Typical
Commercial
TA = O°C
Voo = -22 Vdc
VGG = -50 Vdc

Unit

TA = 25°C
Voo = -20 Vdc
VGG = -50 Vdc

10938'
100

IGG

4.5
11.2

3.6
9.0

3.2
8.0

mA
mA

13.6
1.0

10.9
0.8

6.0
0.5

mA
mA

9.1
1.0

7.3
0.8

4.0
0.5

mA
mA

10939 (master)2
100

IGG
10939 (slave)2
100

IGG

Notes.
1. The 10938 has 35 internal drivers which are brow;ht out IGG IS proportional to the number of drivers on. The values given are for
all 35 drivers on. D,v,de IGG shown by 35 to determine IGG for one driver
2. The 10939 will never have more than two drivers on at anyone time; one grid driver and the cursor. The values shown are for two
drivers on with 100% duty cycle.

5·13

Dot Matrix Display Controller

10938 -10939
AC CHARACTERISTICS
Parameter

Min

Symbol

Typ

Max

Unit

GENERAL INTERFACE TIMING
Data Load (LD)
On Time
Off time
Commercial
Industrial
Cycle Time
Commerical
Industrial

T1don
T 'dOIf

,,8
,,8

1.0
40.0
44.5

"s

Tldcyc

60.0
66.7

"s
"s

SERIAL INTERFACE TIMING
Serial Clock (Dl)
On Time
Off Time
Cycle Time

1.0
1.0
2.0

Tscon
Tscoff
Tsccyc

Serial Clock (DO)
Set-up Time
Hold Time

TShold

Serial Clock to LD Time
LD to Senal Clock

20.0

"s
"s
"s

400
400

ns
ns

TSI

1.0

"s

Tis

1.0

"s

0
200

ns
ns

Tssetup

PARALLEL INTERFACE TIMING
Parallel Data (DO-D7)
Set-up Time
Hold Time

T psetup
T phold

TIMING WAVEFORMS

Tscoff

01
(SERIAL CLOCK)

·1

---~
-I

LD

DO
(DATA)

Serial Interface Timing Waveforms

1.-------T,dCyC-----l·1
..
~1+-~T~ld~o:!:n~.~I~.o---_TldOff -----...J
LD

----'r--

! - I_ _ _

pselupL ~

phOld

DO-07

Parallel Interface Timing Waveforms
5-14

Dot Matrix Display Controller

10938 • 10939
FUNCTIONAL DESCRIPTION

Table 1 Control Word Assignments

Once the display buffer has been loaded from the host processor, the 10938/10939 system generates all timing signals
required to control the display.
Input data is loaded into the Display Data Buffer as a series of
8-blt words via the Serial or Parallel Data Input channel on the
10939. Internal timing and control logic synchronize the digit output signals with the Serial Data and Load signals to the 10938
to provide the proper timing for the multiplexing operation. A
128 x 35 bit PLA is provided for decoding the full 96 character
ASCII set, plus 32 special characters.

Hex Value

Function

00
01
02
03
04
05
06
07
08

Not used
Load 01 Into Data Buffer
Not used
Not used
Not used
Set digit time to 16 cycles per grid
Set digit time to 32 cycles per grid
Set digit time to 64 cycles per grid
Enable Normal Display Mode (MSB in data words
is used for cursor control only)
Enable Blank Mode (data words with MSB _ 1 will
be blanked and cursor will be on)
Enable Inverse Mode (data words with MSB - 1
will be "inversed" and cursor will be on)
Not used
Not used
Not used
Start Display Refresh Cycle (use only once after
reset)
Not used
Not used
Load Duty Cycle Register with lower 6 bits (0-63)
Load Digit Counter (80 - 32, 81 -1, 82.2, etc.)
Not used
Load Buffer Pointer Register with lower 5 bits
Not used

OS
OA

The parallel data input mode is implemented by toggling any
of data lines 02-07 after POR has gone low. Once the parallel
data load mode has been implemented, a power-on reset procedure must be performed to return to serial data load mode.
Parallel data transfer is accomplished by putting the command
or display data on the data lines, then pulsing the LD line. The
load cycle time must be at least 60 P.s with the LD line set high
for at least one P.s and held low for at least 40 p.s.

OB
OC
00
OE
OF
10-3F
40-4F
80-SF
AO-BF
CO-D3
EO-FF

The serial data input mode is implemented during the poweron reset procedure. In those systems using serial mode, ports
02-07 should be tied low to prevent the inadvertent implementation of the parallel load mode. Serial data by1es are shifted
into a data buffer MSB first on line DO using line 01 as the serial
clock. The last eight bits clocked in are latched into the display
controller by a pulse on the LD line. The cycle time for each data
bit is 2 P.s and the load time for each by1e is 60 p.S.

Table 2. Buffer Pointer Control Codes

Input data may be Control or Display data. The following
paragraphs describe the format and functions of these control
and display data words.

CONTROL DATA WORDS
Control data words are used to select the operating parameters
of the display controller. They must be preceded by a Control
Prefix word (0000 0001, hexadecimal 01) to be distinguished
from Display Data words.

Buffer Pointer Control
The Buffer Pointer Control code sets the Display Data Buffer
pointer. The lower 5 bits of the code are loaded into the buffer
pOinter (see Table 2).

Code
Value

Pointer
Value

Character
POlltlon

CO
Cl
C2
C3
C4
C5
C6
C7
C8
CS
CA
CB
CC
CD
CE
CF
DO
01
02
03

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Note:
DO NOT USE CHARACTER POSITIONS 20-31
(CODES D4-DF)

5-15

10938. 1.0939

Dot Matrix Display Controller

Digit Counter Control

Table 4. Duty Cycle Control Codes
Digit Tlme=16

The Digit Counter Control code defines the number of character
positions (grids) to be controlled. This code is normally used only
during initialization routines, but it may also be used in conjunction with the Duty Cycle Control code to extend the range of
brightness control (see Table 3).

Duty Cycle Control
The Duty Cycle Control code turns the display on and off, adjusts
display brightness, and modifies display timing. The time slot
for each character is 16, 32, or 64 cycles as selected by the Digit
Time Control codes (see Table 3). The anode and grid drivers
for each character are on for a maximum of 13, 29, or 61 cycles
with a 3 cycle inter-digit off-time. The lower 6 bits of the Duty
Cycle Control code are loaded into the Duty Cycle Register.
Resultant duty cycles are shown in Table 4.
Table 3. Digit Counter Control Codes
Code
80
81
82
83
84
85
86
87
88
89
8A
88
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
98
9C
9D
9E
9F

Digit
Counter Value

No. of Grids
Controlled

00
01
02
03
04
05
06
07
08
09
OA
08
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C

32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

Code

On

Off .

40
41
42
43
44
45
46
47
48
49
4A
48
4C
4D
4E
4F
50
51
52
53

-

1
2
3
4
5
6
7
8
9
10
11
12
13
13
13
13
13

16
16
16
15
14
13
12
11
10
9
8
7
6
5
4
3
3
3
3
3

58
5C
5D
5E
5F
60
61
62

13
13
13
13
13
13
13
13

7C
7D
7E
7F

13
13
13
13

-

Dlgl.l Time = 32

Digit Time = 64

On

Off

On

Off

-

-

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

32
32
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

64
64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47

3
3
3
3
3
3
3
3

25
26
27
28
29
29
29
29

7
6
5
4
3
3
3
3

25
26
27
28
29
30
31
32

39
38
37
36
35
34
33
32

3
3
3
3

29
29
29
29

3
3
3
3

58
59
60
61

6
5
4
3

-

Display Mode Select

Digit Time Select

Each ASCII character is represented by the lower seven bits of
the 8-bit value loaded into the 10939. The eighth (most significant) bit controls the cursor (see Cursor Control). This bit is
known as the data byte control bit. If either Blank or Inverse mode
is selected, a "0" in this bit causes a normal character display,
while "1" selects either Blank or Inverse mode, depending on
which mode is enabled. Three control codes are provided (see
Table 1) to Enable Blank Mode, Enable Inverse Mode, or Enable
Normal Display Mode.

The Digit Time Select code sets the total time for each character
during the refresh cycle. Three values can be set using the three
codes shown in Table 1. The default value set at power-on is
64 cycles per grid. For displays with 40 or more characters, or
under conditions where the display can be subjected to quick
movements during viewing (e.g. portable or vehicle-mounted
applications), it may be necessary to increase the refresh rate
by selecting 16 or 32 cycles per grid with the appropriate control code.

In the Blank mode, any character with the MSB ="1" will be
blanked. In the Inverse mode, it will be displayed with all segment driver outputs inverted. On video displays, this is referred
to as "Inverse Video" format. These controls allow individual
characters or groups of characters to be blinked or blanked by
simply changing the mode without changing the data in the
Display Buffer.

10
IE
IF

5-16

Dot Matrix Display Controller

10938 • 10939
Cursor Control

b. The Anode Drivers (SG01-SG35) on the 10938 are in the off
state.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 32.
e. The Buffer Pointer is set to O.
1. The Digit time is set to 64.
g. The Normal display mode is set.
h. DATA-LOAD is set to high impedance state.
i. SCLK-DIS is set to VOL to disable the anode drivers in the
10938.
j. SOP is set to VOL to disable the sync pulse.

The data byte control bit (MSB 8), besides selecting Blank,
Inverse, or Normal mode, also controls the cursor output which
Is enabled on all characters with the MSB equal to one.
Therefore, when the Normal mode is enabled and the MSB of
the data byte Is set to a one, the normal character is displayed
with the cursor on. When the Blank mode is enabled and the
MSB is set to a one, the character is blanked but the cursor is
on. If Inverse mode is enabled and the MSB is set to a one, the
inverse character is displayed and the cursor is on but not
inversed.

Start Refresh

NOTE:
1. When the POR signal is removed, SCLK-DIS is set to the high
impedance state.
2. During the initial rise time of Voo at power turn-on, the
magnitude of VGG should not exceed the magnitude of Voo.

At power on, the 10939 is held in an internal halt mode. The
normal display refresh sequence starts upon receipt of a Start
Refresh control code. This Is particularly useful for synchronizing systems using more than one 10939. Only the Master 10939
In a multi-chip system will recognize the Start Refresh code. The
Master starts the Slave(s) at the appropriate time, using the SOP
Signal.

GRID (DIGIT) DRIVERS (STROO-STR19) PLUS CURSOR
The 20 Digit Drivers select each of the display character positions sequentially during a refresh scan. Display dots will be illuminated when both the Digit Drivers and Dot Drivers for a
particular character are energized simultaneously. The cursor
se9ment is generated by the 10939, but its timing characteristics
are identical to the anode timing generated by the 10938.

INPUT DISPLAY DATA WORDS
Display data words are loaded as 8-bit codes. The eighth (most
significant) bit specifies normal (0) or blank/inverse (1) display
mode, depending on the blanklinverse mode selection (see Control data words 09 and OA in Table 1). This bit also controls the
cursor.

ANODE (DOT) DRIVERS (SG01-SG35)

Twenty display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer automatically increments after each data word is stored in the buffer. To select a
character position to be loaded out of sequence, use the Buffer
Pointer control code. The Buffer Pointer will automatically reset
to character position 0 when its value is equal to the programmed
Digit Count.

35 Dot Drivers are provided in the 10938. The output states for
each character pattern are internally decoded from the 8-bit
characters received from the 10939 by means of a 128 x 35-bit
PLA. Data codes and the corresponding patterns are shown in
Figure 1. Figure 2 shows the Dot Drivers (SG01-SG35) assignments as they relate to the 5 x 7 dot matrix patterns.

POWER-ON RESET

TYPICAL SYSTEM HOOKUPS

The Power-On Reset (POR) initializes the internal circuits of the
10939. This is normally accomplished when power (Voo) is
applied. The following conditions are established by application
of POR:

Figure 3 shows a 10938 and 10939 in a parallel interface with
the host system driving a 20 character display. Figure 4 shows
a 10938 and a 10939 in a serial interface with the host system
driving a 20 character display. Figure 5 shows a 10938 and two
10939's in a parallel interface with the host system driving a
40 character display.

a. The Grid Drivers (STROO-STR19) on the 10939 are in the
off state.

5-17

Dot Matrix Display Controller

10938 • 10939

00

~:~-:- -:-::-~r- -:~.

0'

:-:-: 02

.:-:- 03

H~-+-+-:-:++:;:::
oe i :::::

~.

i.. )

09

i".i

OA

::.

'2

19:

08

I....

lA:

'3

1

~

2';

2s1

29

~-.-

::::: ,.

--:.

: 181

",

II· ... • 1'1.:. 321')
I'

30 ("! 3'

I ".
~8! ; ••• ;

39

3A

I ".

.40

48

50

".'

I.·.•.·.. :.

..
:

41

• •

49

"

.

42

=.i.:

!".:

-:::!

'5

•••• OE

' ..

-:::!

-. --:

lC

:

:

10

:

'6

-:::! t8:::!
--f--.
. : .
'7

0'

lE

I"

•••••

..

IF I'"

:

" ' - f - ' --:~:

25

"

~6 ~}

2E

2D

-~---f- --- -- - '
:::L. 35 ..
::::; 36 !""
'.'

33L' ":;: 3.

OF

27

.:

i

2F'"

'-j
37 ';::;'

I":"

r-, -~ - -~~~'-- c- " - r-:-:~:

i

3sl:

3C'

43

=
.....

44

'I:. :.

3Fi

45

41:

:..

46 :..

:",,:

1":- - -.~--:: 4A

48

"
:

.52

-53

H---+-+-++-+: :
"

•

•

4C I

i

40

i.i

4E

i

56

0'

..

3D ::::: 3E

:,,:-,-i-~-;-:: j-;:~~'- ,;::::- --:::;; -h~
=: .........

".
51

00

:

2A :-!-:2B "!" 2C

":

.. ::

-;--f--" -- -

f-+-'.:.:.. -:~ +-1

-:;"

:::-

'~~~r:1 L~ :/

22

-, -~~-~

i
---I--t---------::. ::: :.: I.:.

:::.' OC

:

}-~::----:~

:::- 05 .:.:. 06 :".: 07

i---:-

-':~ - : : --t--~.~

I
20

:

O'

:':H1-:::

I.::

18! ::::

:1':"

-- - c----- --

~ "i ::::: 1I::::
f-- --- -1--- -t:;;;;'0 :::::

:

:,,:: J

:~:-i- :::;~.

i "!

4F

=. .:

57

~

~!

-~~ -- ::~~ - ~----; - -;---; f- -/::-;~
•••• :

i

54

55

~

L:J:

~:~'--~--I-- ~~:...-- -..:-~-r-:

--'..1

i
.....
:~.. :_+-+--'-_t-t-'-'-:":':"'f5_B+_t~:~
~:'::: 5i;15~t·t
:~~:l
~ I ~ ~..
."
.•••
59

eo

SA

1

6S

69

". .... :
....
62

6'

".

63

64

:''': 65 : ••• :

66

""

--

""
6B

SA

!....

6e

"

Figure 1.

".

6D

,i"

-:-

6E

5 x 7 Dot Matrix PLA Patterns

seese

8888e

89888
88888
8888e

88888

Sge8e
Figure 2.

Anode (Dot) Driver Assignments

5-18

67 : ... :

-~:.:
6F

".
".

10938·. 10939

Dot Matrix Display Controller

FILAMENT 1

2D-CHARACTER VACUUM TUBE
FLUORESCENT DISPLAY

FILAMENT 2

20

35
CURSOR
Voo
Vss
VGG

SG01-SG35

10938

STROO-STR19
SOP
SIP
10939
MASTER

DATA-LOAD
SCLK-DIS

CLOCK
POR

LD

-15V (Voo)
N.C.

HOST SYSTEM

Figure 3.

Typical Display System with Parallel Interface to Host System

FILAMENT 1

20-CHARACTER VACUUM TUBE
FLUORESCENT DISPLAY

FILAMENT 2

20
35
SG01-SG35

10938

CURSOR STROO-STR19
VDD

Voo
Vss
VGG

SOP
SIP

Vss
VGG

10939

MASTER

DATA-LOAD
SCLK-DIS

Figure 4.

CLOCK
LD

D1

DO POR D2-D7

Typical Display System with Serial Interface to Host System

5-19

-15V (Voo)
N.C.
-15V (Voo)

II

Dot Matrix Display Controller

10938 • 10939

-

f--FIL AMENT 1

40 CHARACTER VACUUM TUBE
FLUORESCENT DISPLAY

35
20

SG01-SG35

10938

It

STROO-STR19
Voo
Vss
VGG

~
+5V
-45V
DATA-LOAD
SCLK-DIS

~

•

:~

20,

CURSOR
CURSQI'I STROO-STR19
VGG
SIP
SOP
SOP
SIP
MASTER
MASTER !--15V (Voo)
10939
10939
CLOCK (SLAVE)
(MASTER) CLOCK

Voo
Vss
VGG

I

1I

I---FILAMENT 2

LD

II

00-07 POR

If

LD

00-07 POR

J r

-

---

)'8

RES
CONTROL
HOST SYSTEM
1/0

Figure 5.

DATA

Typical Display System with Parallel Interface to Host and Two 10939 Devices

5-20

+5V (Vss)
Voo
Vss
VGG

10939 • 10942 • 1094'3

'1'

10939, 10942, AND 10943
DOT MATRIX DISPLAY CONTROLLER

Rockwell
DESCRIPTION

FEATURES

The Rockwell 10939, 10942, and 10943 Dot Matrix Display Controller is a three-chip MaS/LSI general purpose display controller
system designed to interface to dot matrix displays (vacuumfluorescent or LED).

• 20-character display driver cascadable to 80 characters
• Standard 5 x 12 character font. Custom fonts available by
special order
• Separate cursor driver output
• Two 128 x 23 PLAs provide decoding for full 96-character
ASCII set plus 32 special characters
• Serial or parallel data input for 8-bit display and control
characters
• Brightness, refresh rate, and display mode controls

The three-chip set will drive displays with up to 46 anodes (dots)
and up to 20 grids (characters) plus a cursor. The chips can be
cascaded to drive larger displays of up to 80 characters. An
internal PLA-type decoder provides character decoding and dot
pattern generation for the full 96-character ASCII set and an
additional 32 special characters.

•
•

ORDERING INFORMATION
Part
Number

Package
Type

10939P
10939PE
10942P
10942PE
10943P
10943PE

Plastic
Plastic
Plastic
Plastic
Plastic
Plastic

10939 provided in 40-pin DIP
10942 and 10943 provided in 28-pin DIP

Temperature
Range (OC)

o to
-40 to
o to
-40 to
o to
-40 to

+70
+85
+70
+85
+70
+85

t=-

20-CHARACTER 5 x 12 DOT MATRIX DISPLAY
23

.t-

SG01-SG23

23

I ANODE DRIVERS AND LATCHES I-

-I

t
INVERSION
LOGIC

I

t

+j

t

LEVEL
DETECT

DATA-LOAD

10943

LEVEL
DETECT

1128 x 23 PLA 1
--{

t

SG01-SG23

ANODE DRIVERS AND LATCHES'

t

10942

J..

I

t
INVERSION
LOGIC

I-

t
1128 x 23 PLA 1

r~
DET

8-BIT SHIFT REGISTER

rL~
'-;
t
8-BIT SHIFT REGISTER

SCLK-DIS

20 x 8
RAM

.LDET

CONTROL
LOGIC

t

10939

I

r

GRID
DRIVERS

r-

CURSOR

I

STROO-STRI9
20

HOST

I

Block Diagram of 10939, 10942, 10943

Document No_ 29000099
5-21

Data Sheet Order No. 099
Rev. 2, October 1984

.

""

Dot Matrix Display Controller

10939 • 10942 • 10943
INTERFACE DESCRIPTION

10939 Pin Functions
Signal Name

10942 and 10943 Pin Functions
Signal Nama

Pin No.

Function

Voo
Vss
SG01-SG23
VGG
SCLK-DIS
DATA-LOAD

1
2
3-17, 19-26
18
27
28

DC Power
Power and signal reference
Anode (Dol) driver outputs
Display voltage
Serial data shift clock
Serial data output/latch control

Voo
Vss
SG23
SG22
SG21
SG20
SG19
SG18
SG17
SG16
SG15
SG14
SG13
SG12

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Vss
Voo
CLOCK
CURSOR
MASTER
SIP
SOP
00-07
LD
POR
SCLK-DIS
DATA-LOAD
STROO-STR19
VGG

DATA-LOAD
SCLK-DIS
SGOl
SG02
SG03
SG04
SG05
SG06
SG07
SG08

SCLK-OIS
SOP
SIP
POR
LO
DO
01
02
03
04
05
06
07
CURSOR
STR19
STR18
STR17
STR16
STR15
STR14

Vaa
SG09
SG10
SGll

10942 and 10943
Pin Configurations

:"':'

Pin No.
36
37
38
14
39
3
2
6-13
5
4
1
40
15-34
35

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Fun<:tlon
Power and signal reference'

DC·Pow~r

'\.

"

Synchronization Clock,
Cursor driver output
Master/Slave Mode control
Sync Input
Sync Output
Serial or parallel data input
Input data strobe
Power-on reset
Serial data shift clock
Serial data output/latch control
Digit (grid) driver outputs
Display voltage

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

DATA-LOAD
M~STER

CLOCK
Voo
Vss
VGG
STROO
STROl
STR02
STR03
STR04
STR05
STR06
STR07
STR08
STR09
STR10
STR11
STR12
STR13

10939 Pin Configurations

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS·
Voltages are referenced to Vss, where Vss
Parameter

Symbol

= +5 Vdc

Value

Unit

Oto+70
-40 to +85
-55 to +125

'C
'C

Operating Temperature
Commercial
Industrial
Storage Temperature

Ts

Operating Voltage

Voo

-22to-18
-20 typical

Vdc

Operllting Display Voltage

VGG

-50

ydc

·NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
Th.is is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
other sections of this document IS not Implied. Exposure to
absolute maximum rating conditions for extended periods may
attect device ~eliability.

TA

·C

5-22

Dot Matrix Display Controller

10939 • 10942 • 10943
DC CHARACTERISTICS
(Voo

= -18.0 to

-22 Vdc, Vss

Parameter
10942 and 10943
Output Anodes (Dots)
Logic "I" (ILOAO = 2 mAl
Logic "0" (l lOAO = 0 mAl
10939
Input 00-07, LD, SIP
Logic "I"
Logic "0"
Input POR
Logic "I"
Logic "0"
Output SOP
Logic "I"
Logic "0"
Output Digits, Cursor
Logic "I" (ILOAO = 10 mAl
Logic "0" (lLOAO = 0 mAl
Note: TA

= O·C to

0 Vdc, unless otherwise noted. All voltages referenced to Vss.)
Symbol

Min.

Typical

Max.

Unit

Vss
0.95 X VGG

V
V

VOH
VOL

-1.5
VGG

V IH
Vil

-1.2
Voo

+0.3
-4.2

V
V

VIHPO
VllPO

-3.0
Voo

+0.3
-10.0

V
V

VOHSY
VOlSY

-1.2
Voo

Vss
-42

V
V

VOH
VOL

-1.5
VGG

Vss
0.95 X VGG

V
V

+ 70·C (commercial) or - 4O·C to + 8S·C (industrial), unless otherwise noted.

OPERATING CURRENTS
Maximum

Parameter

Typical

Industrial
TA
-40°C
-22 Vdc
VDD
VGG
-50 Vdc

Commercial
TA
O°C
-22 Vdc
VDD
VGG
-50 Vdc

4.5
7.4

3.6
5.9

3.2
5.3

mA
mA

13.6
10

10.9
0.8

6.0
05

mA
mA

9.1
10

7.3
0.8

40
0.5

mA
mA

=
=
=

=
=
=

= 25°C
= -20 Vdc
= -50 Vdc

TA
VDD
VGG

Unit

10942 or 10943
100

IGG 1
10939 (master)
100

IGG2
10939 (slave)
100

IGG 2

Notes:
1 The 10942 and 10943 each have 23 driver outputs. IGG IS proportional to the number of drivers on. The values given are for all 23 drivers
on. Divide IGG shown by 23 to determine IGG for one driver. Multiply IGG by 2 to find total current requirements for all drivers on for both
devices.
2 The 10939 will never have more than two drivers on at anyone time; one grid driver and the cursor. The values shown are for two drivers
on with 100% duty cycle

5·23

iii

Dot Matrix Display Controller

109a9 • 10942 • 10943
AC CHARACTERISTICS
Parameter

Symbol

Data Load (LD)
On Time
Off Time
Commercial
Industrial
Cycle Time
Commercial
Industrial

Min.

Tldon
Tldo"

Typical

Unit

Max.

1.0

pIS

40.0

pIS
pIS
pIS
pIS
pIS

44.5

Tldcyc
60.0
66.7

SERIAL INTERFACE TIMING
Serial Clock (01)
On Time
Off Time
Cycle Time
Serial Data (DO)
Set-up time
Hold Time
Serial Clock to LD Time
LD to Serial Clock

1.0
1.0
2.0

Tacon
Tscoff
Tsceyc

",8

pIS
pIS

TShOld
TSI
Tis

400
400
1.0
1.0

ns
ns
",s

Tpsetup
TPhoid

0
200

ns
ns

Tssetup

PARALLEL INTERFACE TIMING
Parallel Data (00-07)
Set-up Time
Hold Time

20.0

pIS

TIMING WAVEFORMS

Dl
(SERIAL CLOCK)

·1

LD

s----------------~_t~1---~~~==~.1

DO
(DATA)

Serial Interface Timing Waveforms

1. .

>--_ _ _ TIdcyc

-----1.1

LD

DO-D7

Parallel Interface Timing Waveforms
5-24

Dot Matrix Display Controller

10939 • 10942 • 10943
FUNCTIONAL DESCRIPTION

time slot for each character is 16, 32, or 64 cycles as selected
by the Digit Time Control codes (see Table 1). The segment and
digit drivers for each character are on for a maximum of 13, 29,
or 61 cycles with a 3 cycle inter-digit off-time. The lower 6 bits
of the Duty Cycle Control code are loaded into the Duty Cycle
Register. Resultant duty cycles are shown in Table 4.

Once the display buffer has been loaded from the host
processor, the 10939, 10942, and 10943 system generates all
timing signals required to control the display.
Input data is loaded into the Display Data Buffer as a series of
8-bit words via the Serial or Parallel Data Input channel on the
10939. Internal timing and control logic synchronize the digit output signals with the Serial Data and Load signals to the
10942/10943 to provide the proper timing for the multiplexing
operation. Two 128 x 23 bit PLAs, one in the 10942 and the
other in the 10943, decode the full 96-character ASCII set plus
32 special characters.

Table 1.

The parallel data input mode is implemented by toggling any
of data lines 02-07 after POR has gone low. Once the parallel
data load mode has been implemented, a power-on reset procedure must be performed to return to serial data load mode.
Parallel data transfer is accomplished by putting the command
or display data on the data lines, then pulsing the LD line. The
load cycle time must be at least 60 /lS with the LD line set high
for at least one /lS and held low for at least 40 /ls.

Function

00
01
02
03
04
05
06
07
08

Not Used
Load 01 into Data Buffer
Not used
Not used
Not used
Set Digit Time to 16 cycles per grid
Set Digit Time to 32 cycles per grid
Set Digit Time to 64 cycles per grid
Enable Normal Display Mode (MSB in data words
is ignored
Enable Blank Mode (data words with MSB = 1 Will
be blanked)
Enable Inverse Mode (data words with MSB = 1 will
be "lnversed")
Not used
Not used
Not used
Start Display Refresh Cycle (use only once after
reset)
Not used
Not used
Load Duty Cycle Register
Load Digit Counter (80 = 32, 81 = 1, 82 = 2, etc.)
Not used
Load Buffer Pointer Register with lower 5 bits
Not used

09
OA

The serial data input mode is implemented during the poweron reset procedure. In those systems using serial mode, ports
02-07 should be tied low to prevent the inadvertent implementation of the parallel load mode. Serial data bytes are shifted into
a data buffer MSB first on line DO using line 01 as the serial
clock. The last eight bits clocked in are latched into the display
controller by a pulse on the LD line. The cycle time for each data
bit is 2 /lS and the load time for each byte is 60 /ls.

OB
OC
OD
OE
OF
10-3F
40-7F
80-9F
AO-SF
CO-DF
EO-FF

Input data may be Control or Display data. The following
paragraphs describe the format and functions of these control
and display data words.

Table 2.

CONTROL DATA WORDS
Control data words are used to select the operating parameters
of the display controller. They must be preceded by a control
prefix word (0000 0001, hexadecimal 01) to be distinguished from
display data words.

Buffer Pointer Control
The Buffer Pointer Control code sets the Display Data Buffer
pointer. The lower 5 bits of the code are loaded into the buffer
pointer (see Table 2).

Digit Counter Control
The Digit Counter Control code defines the number of character
positions (grids) to be controlled. This code is normally used only
during initialization routines, but it may also be used in conjunction with the Duty Cycle Control code to extend the range of
brightness control (see Table 3).

Duty Cycle Control
The Duty Cycle Control code is used to turn the display on and
off, to adjust display brightness, or to modify display timing. The

Control Word Assignments

Hex Value

Buffer Pointer Control Codes

Code
Value

Pointer
Value

Character
Position

CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
Dl
D2
D3

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Note: Do not use character positions 20-31 (Codes D4-DF)

5-25

Dot Matrix Display Controller

10939 • 10942 • 10943 '
Table 3.
Code

DIgIt Counter Control Codes
Digit
Counter Value

No. 01 Grids
Controlled

00

32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

80
81 '
82
83
84
85
86
87
88
89
8A
88
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
98
9C
90
9E
9F

01
02
03
04
05
06
07
08
09
OA
08
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C
10
1E
1F

Table 4.
Digit Time
Code

Digit Time Select
The Digit Time Select code sets the total time for each character
during the refresh cycle. Three values can be set using the three
codes shOwn in Table 1. The default value set at power·on is
64 cycles per grid. For displays with 40 or more characters,or
under conditions where the display can be subjected to quick
movements during viewing (e.g. portable or vehicle·mounted
applications), it may be necessary to increase the refresh rate
by selecting 16 or 32 cycles per grid with the appropriate con·
trol code.

Duty Cycle Control Codes

= 16

Digit Time

= 32

On

Oil

On

Oil

-

--

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

32
32
32
31
30
29
28
27
26
26
24
23
22
21
20
19
18
17
16
15

Digit Time

=64

On

Oil

-

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

64
64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47

40
41
42
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53

1
2
3
4
5
6
7
8
9
10
11
12
13
13
13
13
13

16
16
16
15
14
13
12
11
10
9
8
7
6
5
4
3
3
3
3
3

58
5C
50
5E
5F
60
61
62

13
13
13
13
13
13
13
13

3
3
3
3
3
3
3
3

25
26
27
28
29
29
29
29

7
6
5
4
3
3
3
3

25
26
27
28
29
30
31
32

39
38
37
36
35
34
33
32

7C
70
7E
7F

13
13
13
13

3
3
3
3

29
29
29
29

3
3
3
3

58
59
60
61

6
5
4
3

-

characters or groups of characters to be blinked or blanked by
simply changing the mode without changing the data in the
Display Buffer.

Cursor Control
The data byte control (MSB 8), besides selecting Blank, Inverse,
or Normal mode, also controls the cursor output which is enabled
on all characters with the MSB equal to one. Therefore, when
the Normal mode is enabled and the MSB of the data byte is
set to a one, the normal character is displayed with the cursor
on. When the Blank mode is enabled and the MSB is set to a
one, the character is blanked but the cursor is on. If Inverse mode
is enabled and the MSB is set to a one, the inverse character
is displayed, and the cursor is on but not inversed.

Display Mode Select
Each ASCII character is represented by the lower seven bits of
the 8-bit value loaded into the 10939. The eighth (most significant) bit is used to turn the cursor (see Cursor Control) on in
Normal display mode. If either Blank or Inverse mode is selected,
a "0" in this bit causes a normal character display mode, while
a "1" selects either Blank or Inverse mode, depending on which
mode is enabled. Three control codes are provided (see Table 1)
to Enable Blank mode, Enable Inverse mode, or Enable Normal
display mode.

Start Refresh
At power on, the 10939 is held in an internal halt mode. The
normal display refresh sequence starts upon receipt of a Start
Refresh control code. This is particularly useful for synchronizing
systems using more than one 10939. Only the Master 10939 in
a multi-chip system will recognize the Start Refresh code. The
Master starts the Slave(s) at the appropriate time, using the SOP
signal.

In the Blank mode, any character with the MSB = "1" will be
blanked. In the Inverse mode, it will be displayed with all segment driver outputs inverted. On video displays, this is referred
to as "Inverse Video" format. These controls allow individual

5-26

Dot Matrix Display Controller

10939 - 10942- 10943
INPUT DISPLAY DATA WORDS

POWER-ON RESET

Display data words are loaded as 8-bit codes. The eighth (most
significant) bit is a dual purpose bit. This bit specifies normal
(0) or blank/inverse (1) display mode, depending on the
blank/inverse mode selection (see control data words 09 and
OA in Table 1). It also controls the cursor output from the 10939;
on (1) or off (0). Note, that this bit always controls the cursor
no matter what display mode is selected.

The Power-On Reset (PaR) initializes the internal circuits of the
10939. This is normally accomplished when power (Voo) is
applied. The following conditions are established by the application of paR:
a. The Grid Drivers (STROO-STR19) on the 10939 are in the off
state.
b. The Anode Drivers, SG01-SG23 on the 10942 and
SG01-SG23 on the 10943, are in the off state.

Twenty display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer automatically increments after each data word is stored in the buffer. To select a
character position to be loaded out of sequence, use the Buffer
Pointer Control code command. The Buffer Pointer will automatically reset to character position 0 when its value is equal
to the programmed Digit Counter.

c. The Duty Cycle is set to O.
d. The Digit Counter is set to 32.
e. The Buffer Pointer is set to O.
f. The Digit time is set to 64.
g. The Normal display mode is set.
h. DATA-LOAD is set to high impedance state.

DIGIT GRID DRIVERS (STROO-STR19) PLUS CURSOR

SCLK-DIS is set to VOL to disable the anode drivers in the
10942 and 10943.

The 20 Digit Drivers select each of the display character positions sequentially during a refresh scan. Display dots are
illuminated when both the Digit Drivers and Anode (Dot) Drivers
for a particular character are energized simultaneously. The
Cursor output is generated by the 10939, but its timing
characteristics are identical to the 46 segment outputs generated
by the 10942 and the 10943.

j. SOP is set to VOL to disable the sync pulse.
NOTE:
1. When th paR signal is removed, SCLK-DIS is set to the high
impedance state.
2. During the initial rise time of Voo at power turn-on, the
magnitude of VGG should not exceed the magnitude of Voo.

ANODE (DOT) DRIVERS (SG01-SG23)

TYPICAL SYSTEM HOOKUPS

A total of 46 Dot Drivers are provided by the 10942 and the
10943. The output states for each ASCII charcter pattern are
internally decoded from the 8-bit characters received from the
10939 by means of two 128 x 23-bit PLAs, one in the 10942
and the other in the 10943. Figure 1 shows the dot matrix drivers
(SG01-SG23) as they relate to the 10942 and 10943. Data codes
and the corresponding character patterns are also shown in
Figure 1.

Figure 2 shows a 10939, 10942, and a 10943 in a parallel interface with the host system driving a 20-character display. Figure 3
shows a 10939, 10942, and a 10943 in a serial interface with
the host system driving a 20-character display. Figure 4 shows
two 10939s, a 10942, and a 10943 in a parallel interface with
the host system driving a 40-character display.

5-27

~

Ii:I

10939.'" 1094~ • 10943

00

01

08

09

...

10

•••••

11

18

•

19

•

20

28

· ..
•••

.

~

I

.Q

u

02

• •• 03

OA

..E"'E.

08

12

••••

13

·.... .

18

1A.

•

22

21

2A • • •

...

:.,' 05

04

...

E::'

OC

. .
.::::

14.

...

1C

23

·..

29

Dot Matrix Display Controller

.....
....
..••••

00

...
.....•

24

2C

28

•••

15

.....
•••

10

•

.. · .
·....
...
:::E.
•

06

...

25

••

16

·· . .
· ..

20

•

38

31

32 _.. , ••

33

39

3A

38 .

....
40

!:~~E

48

41

·. ..

••

34

:E

26
•

I

59

•

...
17

•••• :

.. ..

IF • :.:

·.

•• :.:

27

~

2E

••

2F

42

••••

43

.....

3C

44

52

53

SA

58

.1'..1

.... •

35

36.

37

3D

3E

3F

46

45

·

5C

'.

47

4F

55

•••

56.

57

.50

•••

5E

5F

54

•••

Segmen1s Driven 8y 10942

8e8S8
888S8
S8888
S8S
SG19

r3IIE-3IIE-

4C •••••

•

OF

.....

49

58

•

lE

. ..
30 •

• 07

OE

..

••••

•

! J

60

61

62

63

....•
64.

68

69

6A

68

6C

70

71

72

73

74

888S8
80088
S008S
seese
00000
00000

Segments Oroven 8y 10943

10942 and 10943 Driver Assignments

65

60

· ..

66

67

6E

6F

76

n ...

.....
• • 75

...
...
78

.'

79

7A

78

7C

70

7E

7F :::::

Figure 1. 5 x 12 Dot Matrix PLA Patterns and Driver Assignments

5·28

Dot Matrix Display Controller

10939 • 10942 • 10943

Ir

20·CHARACTER 5 x 12 DOT MATRIX VACUUM FLUORESCENT DISPLAY

~3

,
,

23

SG01-SG23

Vss

-45V

VGG

VGG

DATA-LOAD

T

SG01-SG23

Voo

+5V

Vss
10942

FILAMENT 1
FILAMENT 2

I

-15V

Voo

1==

10943

SCLK·DIS

I 1
Vss

VGG

Voo sOP

P
r-

SIP
MASTER
10939

-15V (Voo)

r- N.C.

CLOCK
CURSOR

,

STROO-STR19
LD

t

110

00-07

POR

t

1
RES

DATA

20

CONTROL
HOST SYSTEM

Figure 2. Typical Display System with Parallel Interface to Host System

Ir

FILAMENT 1
20·CHARACTER 5 x 12 VACUUM FLUORESCENT DISPLAY
23
I

I

I

23

SG01-SG23

-15V

Voo

+5V

Vss
10942

Voo
Vss

-45V

VGG

10943

VGG

DATA-LOAD

J

SG01-SG23

SCLK·DIS

I 1

VGG

Vss

Voo

SOP
SIP

MASTER
10939

-15V(Voo)- 02-07

CLOCK

P
r-

-15V (Voo)

t-- N.C.

CURSOR
STROO-STR19
LD

t

D1

DO

t

LATCH SERIAL DATA
CLOCK
HOST SYSTEM

POR

L

2~

t
RES

Figure 3. Typical Display System with Serial Interface to Host System

5·29

FILAMENT 2

Dot Matrix Display Controller

10939 • 1.0942 • 10943

Irt

FILAMENT 1
4G-CHARACTER 5 x 12 DOT MATRIX VACUUM FLUORESCENT DISPLAY
FILAMENT 2

1

t

23

SG01-SG23

VDD
Vss
VGG

10942

-15V
+5V
-45V

23

S001-S023

VDD
Vss
,VGG

20
10943

20

DATA·LOAD
SCLK·DIS

I
~OP

SIP

+5V (Vss)- MASTER 10939 (SLAVE)

CURSOR -+ISTROO-STR19 LD
DO-07

\110
CONTROL
(LOAD)

VGG

DATA-LOAD SCLK·
DIS

SIP

10939 (MASTER) MASTER -15V (VDD)

POR

1

I

I

SCLK·DIS DATA-LOAD SOP

CURSOR
STROO-STR19
DO-D7

-..-

POR

DATA
, RESCONTJ6~ \
HOST SYSTEM
(LOAD)

Figure 4. Typical Display System with Parallel Interface to Host and Two 10939 Devices

5·30

10941 • 10939

'1'

10941 AND 10939
ALPHANUMERIC AND BARGRAPH
DISPLAY CONTROLLER

Rockwell
DESCRIPTION

FEATURES

The Rockwell 10939 and 10941 Alphanumeric and Bargraph
Display Controller is a two-chip MOS/LSI general purpose display
controller system designed to interface with bargraph and
segmented displays (vacuum-fluorescent or LED).

• 20-character display driver cascadable to 80 characters

The two-chip set will drive displays with up to 16 segments (plus
decimal point and comma tail) and up to 20 grids (characters)
plus a cursor. The chips can be cascaded to drive larger displays
of 80 characters. Segment decoding for ASCII characters and
bargraph patterns is accomplished through an internal PLA.

• Serial or parallel data input for 8-bit display and control
characters

• Direct drive capability for vacuum-fluorescent displays
• 128 x 18 PLA provides segment decoding for ASCII
characters (all caps only) and bargraph patterns

• Brightness, refresh rate, and display mode controls
• Separate cursor driver output
• 10939-40-pin DIP package
• 10941-24-pin DIP package

ORDERING INFORMATION
Part
Number

Package
Type

10941P
10941PE
10939P
10939PE

Plastic
Plastic
Plastic
Plastic

~

Temperature
Range (OC)

o to
-40 to
o to
-40 to

+ 70
+85
+70
+85

20-CHARACTER 16-SEGMENT ALPHANUMERIC OR BARGRAPH DISPLAY

TAIL

SG01-SG16

PNT

CURSOR

STROO- STR19

10941

10939

~SEGMENT

DRIVERS AND LATCHES

•

INVERSION
LOGIC

1

~

t.

GRID DRIVERS

I 1

128 x 18 PLA]
8-BIT SHIFT
REGISTER

rf

LEVEL
DETECT
LOGIC

LEVEL
DETECT
LOGIC

r:--

I

,.---

SCLK-DIS
CONTROL
LOGIC
DATA-LOAD

--

20 x 8
RAM

t

I

I

I

I--=:J
Block Diagram of 10941 and 10939

Document No. 29000097
5-31

Data Sheet Order No. 097
Rev. 2, October 1984

Alphanumeric and Bargraph Display Controller

10941 • 10939
INTERFACE DESCRIPTION

10939 Pin Functions

10941 Pin Functions
Signal Name

Pin No.

Vss
SG01-SG16
SCLK-DIS
DATA-LOAD
PNT
TAIL
Voo
VGG

2
6-15, 17-22
23
24
4
5
1
16

Function,
Power and signal reference
Segment driver outputs
Serial data shift
Serial data output/latch control
Decimal Point driver output
Comma Tail driver output
DC Power
Display voltage

Voo

Vss
PNT
TAIL
NOT USED
SG16
SG15
SG14
SG13
SG12
SGll
SG10

'-1-_ _ _ _....r"

DATA-LOAD
SCLK-DIS
SGOI
SG02
SG03
SG04
SG05
SG06
VGG
SG07
SG08
SG09

Signal Name

Pin No.

Vss
Voo
CLOCK
CURSOR
MASTER
SIP
SOP
DO-D7
LD
POR
SCLK-DIS
DATA-LOAD
STROO-STR19
VGG

36
37
38
14
39
3

2
6-13
5
4
1
40
15-34
35

SCLK-DIS
SOP
SIP
POR
LD
DO
01
02
03
04
05
06
07
CURSOR
STR19
STR18
STRt?
STR16
STR15
STR14

10941 Pin Configuration

Function

;

ppwer and signal reference
DC Power
Synchronization Clock,
Cursor driver output
Master/Slave Mode control
Sync Input
Sync Output
Serial or parallel data input
Input data strobe
Power-on reset
Serial data shift clock
Serial data output/latch control
Grid Driver Outputs
Display voltage

DATA-LOAD
MASTER
CLOCK
Voo
Vss
VGG
STRDD
STRDI
STR02
STR03
STR04
STROS
STR06
STR07
STR08
STRD9
STR10
STRll
STR12
STR13

SPECIFICATIONS
10939 Pin Configuration

ABSOLUTE MAXIMUM RATINGS,"
Voltages are referenced to Vss
Symbol

Value

Unit

Operating Temperature
Commercial
Industrial
Storage Temperature

Parameter

Tc
TI

o to + 70
-40 to +85
-55 to + 125

°C
°C
°C

Operaling Voltage

Voo

-22 to -18
- 20 (tYPical)

Vdc

Operating Display Voltage

VGG

-50

Vdc

"NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device,
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections 01 this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability,

5-32

Alphanumeric and Bargraph Display Controller

10941 • 10939
DC CHARACTERISTICS
All voltages referenced to V 66

Symbol

Min

10941
Output Segments
Logic "1" (iload
Logic "1" (ILOAO

Parameter

Max

Unit

VOH
VOL

-1.5
VGG

Vss
0.95 x VGG

V
V

10939
Input 00-07, LD, SIP
Logic "1"
Logic "0"

V IH
Vil

-1.2
Voo

+03
-4.2

V
V

Input POR
Logic "1"
Logic "0"

VIHPO
VllPO

-3.0
Voo

+0.3
-10.0

V
V

Output SOP
Logic "1"
Logic "0"

VOHSY
VOlSY

-1.2
Voo

Vss
-4.2

V
V

VOH
VOL

-1.5
VGG

Vss
0.95 x VGG

V
V

= 2 rnA)
= 0 rnA)

Output Digits, Cursor
Logic "1" (iload
10 rnA)
Logic "0" (iload
0 rnA)

=
=

Typ

OPERATING CURRENTS
Typical

Maximum

Parameter

Notes

Commercial
TA
O°C
Voo
-22 Vdc
VGG
-50Vdc

Industrial
TA
-40°C
Voo
-22 Vdc
VGG
-50 Vdc

=
=
=

=
=
=

= 25°C
= -20Vdc
= -50 Vdc

TA
Voo
VGG

Unit

10941
100

1

4.5
5.7

3.6
4.6

32
29

rnA
rnA

2

136
1.0

10.9
0.8

60
05

rnA
rnA

2

9.1
1.0

7.3
0.8

40
0.5

rnA
rnA

IGG
10939 (master)
100

IGG
10939 (slave)
100

IGG

Notes:
1. The 10941 has 18 internal drivers which are brought out IGG IS proportional to the number of drivers on. The values given are for
all 18 drivers on. Divide IGG shown by 18 to determine IGG for one driver.
2. The 10939 will never have more than two drivers on at anyone time; one grid driver and the cursor. The values shown are for Iwo
drivers on with 100% duty cycle.

5-33

iii

Alphan.umeric and Bargraph DisplayControlle.r

10941 • 10939
AC CHARACTERISTICS

Min

Symbol

Parameter
Ge:NERAL INTERFACE TIMING
Data Load (LD)
On Time
0111ime
Commercial
Industrial
Cycle Time
Commerical
Industrial
SERIAL INTERFACE TIMING
Serial Clock (D1)
On Time
Off Time
Cycle Time
Serial Data (DO)
Set-up Time
Hold Time
Serial Clock to LD Time
LD to Serial Clock

Unit

..

1.0

T 1don
Tldott

~s

40.0
44.5

~s

60.0
66.7

~s

~s

TldCYC
~s

10

Tscon

20.0

~s

1.0
20

~s

ns
ns

Tsl
Tis

400
400
10
1.0

Tpsetup
Tphold

0
200

Tscoff

Tsccyc
Tssetup
TshOld

PARALLEL INTERFACE TIMING
Parallel Data (DO-D7)
Set-up Time
Hold Time

Max

Typ

~s

~s
~s

ns
ns

TIMING WAVEFORMS

01
. (SERIAL CLOCK)

-I

'------~

LD

- - - - - T tdcyc

DO
{DATA)

Serial Interface Timing Waveforms

1.....------TldcyC ------·~I

J..-T
LD

00-07

1don

.1..

I

Tldoff

t-

_I

1-....

~T_.L -J.
at
~"-__
Parallel Interface Timing Waveforms
5-34

I

10941 • 10939

Alphanumeric and

FUNCTIONAL DESCRIPTION

Barg~aph

Display Controller

Table 1. Control Word AGsignments

Once the display buffer has been loaded from the host processor, the 10941/10939 system generates all timing signals
required to control the display.
Input data is loaded into the Display Data Buffer as a series of
8-bit words via the Serial or Parallel Data Input channel on the
10939. Internal timing and control logic synchronize the digit output signals with the Serial Data and Load signals to the 10941
to provide the proper timing for the multiplexing operation. A
128 x 18 bit PLA is provided for decoding the character set and
bargraph codes.

Hex Value

Function

00
01
02
03
04
05
06
07
08

Not used
Load 01 into Data Buffer
Not used
Not used
Not used
Set digit time to 16 cycles per grid ,
Set digit time to 32 cycles per grid
Set digit time to 64 cycles per grid
Enable Normal Display Mode (MSB in data words
is cursor control only)
Enable Blank Mode (dat~ words with MSB = 1 will
be blanked and cursor will be on)
Enable Inverse Mode (data words with MSB ;. 1
will be "inversed" and cursor will be on)
Not used
Not used
Not used
Start Display Refresh Cycle (use only once after
reset)
Not used
Not used
Load Duty Cycle Register with lower 6 bits (0-63)
Load Digit Counter (80 = 32, 81 = I, 82 = 2, etc,)
Not used
Load Buffer Pointer Register with lower 5 bits
Not used

09
OA

The parallel data input mode is implemented by toggling any
of data lines 02-07 after POR has gone low. Once the parallel
data load mode has been implemented, a power-on reset procedure must be performed to return to serial data load mode.
Parallel data transfer is accomplished by putting the command
or display data on the data lines, then pulsing the LD line. The
load cycle time must be at least 60 itS with the LD line set high
for at least one its and held low for at least 40 its.

OB
OC
00
OE
OF
10-3F
40-7F
80-9F
AO-BF
CO-OF
EO-FF

The serial data input mode is implemented during the poweron reset procedure. In those systems using serial mode, ports
02-07 should be tied low to prevent the inadvertent implementation of the parallel load mode. Serial data bytes are shifted
into a data buffer MSB first on line DO using line 01 as the serial
clock. The last eight bits clocked in are latched into the display
controller by a pulse on the LD line. The cycle time for each data
bit is 2 itS and the load time for each byte is 60 its.

Table 2. Buffer Pointer Control Codes

Input data may be Control or Display data. The following
paragraphs describe the format and functions of these control
and display data words.

CONTROL DATA WORDS
Control data words are used to select the operating parameters
of the display controller. They must be preceded by a Control
Prefix word (0000 0001, hexadecimal 01) to be distinguished
from Display Data words. Table 1. shows the Control Word code
aSSignments and functions.

Buffer Pointer Control
The Buffer Pointer Control code sets the Display Data Buffer
pointer. The lower 5 bits of the code are loaded into the buffer
pointer (see Table 2).

Code
Value

Pointer
Value

Character
Position

CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Note:
DO NOT USE CHARACTER POSITIONS 20-31 (Codes D4-DF),

5-35

Alphanumeric and Bargraph Display Controller

10941-,10939
Digit Counter Gontrol , .

Table 4. Duty Cycle Control Codes
Digit Time

The Digit Counter Control code defines the number of character
positions (grids) to be controlled. This code is normally used only
during initialization routines, but it may also be used in conjunction with the Load Duty Cycle control code to extend the range
of brightness control (see Table 3).

'Duty Cycle Control
The Duty Cycle Coptrol code turns the display on and off, adJusts display brightness, or modifies display timing. The time slot
for each character is 16, 32, or 64 cycles as selected by the Digit
Time Control codes (see Table 3). The segrnent and digit drivers
for each character are on for a maximum of 13, 29, or 61 cycles
:with a 3 'cycle inter:,digit tiff-time. The Iqwer 6 bits of the Duty
Cycle Control code' are loaded into the Duty Cycle Register.
Resultant duty cycles are shown in Table 4.

Digit Time Select
The Digit Time Select code sets the total time for each character
during the refresh cycle. Three values caribe set using the three
codes shown in Table 1. The default value set at power-on is
'64 cycles per grid. For displays with 40.,or mqre character, or
under conditions where the display can be subjected to quick
movements during viewing (e.g. portable or vehicle-mounted
'applications), it may be necessary to increase the refresh rate
by selecting 16 or 32 cycles per grid with the appropriate control
code.
Table 3. Digit Counter Control Codes
Code

Digit
Counter Value

No. of Grids
Controlled

80
81
82
83
84
85
86
87
88
89
8A
88
8C
80
810
8F
90
91
92
93
94
95
96
97
98
99
9A
98
9C
90
910
9F

00
01
02
03
04
05
06
07
08
09
OA
08
OC
00
010
OF
10
11
12
13
14
15
..16
17
18
19
1A
18
1C
10
110
1F

32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

=16

Code

On

Off

40
41
42
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53

-

16
16
16
15
14
13
12
11
10
9'
8
7
6
5
4
3
3
3
3
3

1
2
3
4
5
6
7
8
9
10
11
12
13
13
13
13
13

=

Digit Time 32

=

Digit Time 64

On

Off

On

Off

-

32
32
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15

-

8
9
10
11
12
13
14
15
16
17

64
64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47

-

-1

2
3
4
5
6
7
8
9
10
11'
12
13
14
15
16
17

1
2
3
4
5
6

7

,

58
5C
50
510
SF
60
61
62

13
13
13
13
13
13
13
13

3
,3
3
3
3
3
3
3

25
26
27
28
29
29
29
29

7
6
5
4
3
3
3
3

25
26
27
28
29
30
31
32

39
38
37
36
35
34
33
32

7C
70
7E
7F

13
13
13
13

3
3
3
3

29
29

3
3
3
3

58
59
60
61

6
5
4
3

29
29

significant) bit controls the cursor (see Cursor Control). This bit
is known as the data byte control bit. If either Blank or Inverse
mode is selected, a "0" in this bit causes a normal character
display, while a "1" selects either Blank or Inverse mode,
depending on which mode is enabled. Three control codes are
provided (see Table 1) to Enable Blank mode, Enable Inverse
mode, or Enable Normal Display mode.
In the Blank mode, any character with the MSB = "1" will be
blanked. In the Inverse mode, it will be displayed with all segment driver outputs inverted. On video displays, this is referred
to as "Inverse Video" format. These controls allow individual
characters or groups of characters to be blinked or blanked by
simply ,changing the mode without changing the data in the
Display Buffer.

Cursor Control
The data byte control bit (MSB 8), besides selecting Blank,
Inverse, or Normal mode, also controls the cursor output which
is enabled on all characters with the MSB equal to one.
Therefore, when the Normal mode is enabled and the MSB of
the data byte is set to a one, the normal character is displayed
with the cursor on. When the Blank mode is enabled and the
MSB is set to a one, the character is blanked but the cursor is
on. If Inverse mode is enabled and the MSB is set to a one, the
inverse character is displayed and the cursor is on but not
inversed.

Display Mode Select
Each ASCII character is represented by the lower seven bits
of the 8-bit value loaded into the 10939. The eighth (most
5-36

10941 • 10939

Alphanumeric and Bargraph Display;.controller

Start Refresh

SEGMENT (ANODE) DRIVERS (SG01-SGI6, PNT, TAIL)

At power on, the 10939 is held in an internal halt mode. The
normal display refresh sequence starts upon receipt of a Start
Refresh control code. This is particularly useful for synchronizing systems using more than one 10939. Only the Master 10939
in a multi-chip system will recognize the Start Refresh code. The
Master starts the Slave(s) at the appropriate time, using the SOP
signal.

Eighteen Segment (Anode) Drivers are provided in the 10941.
The output states for each character pattern and each bargraph
pattern are internally decoded from the 8-bit characters received from the 10939 by means of a 128 x 18-bit PLA. Data codes
and the corresponding segment patterns are shown in Figure 1.
Data codes and the corresponding bargraph patterns are shown
in Figure 2.

~

INPUT DISPLAY DATA WORDS

i

Display data words are loaded as 8-bit codes. The eighth (most
significant) bit specifies normal (0) or blank/inverse (1) display
mode, depending on the blank/inverse mode selection (see Control data words 09 and OA in Table 1). This bit also controls the
cursor.

~

I

Q

i

!

"

00
08

01
1- -

1_-',

10 1_-'

Twenty display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer automatically increments after each data word is stored in the buffer. To select a
character position to be loaded out of sequence, use the Buffer
Pointer control code. The Buffer Pointer will automatically reset
to character position 0 when its value is equal to the programmed
Digit Count.

09

11

I·

18

- - ' 19
1__
;

20

21

I
\

2.

29

I II

POWER-ON RESET

30 I:::: -' 31

The Power-On Reset (PaR) initializes the internal circuits of the
10939. This is normally accomplished when power (Voo) is
applied. The following conditions are established by application
of paR:

~

~

~

Q

5i Ji
I II
I~ -" 03

I

I

1A 1_-' ,. 1__

,I

22

\
1

--,.

I;

2A
I
I

I I

23 =:=:

1C

24

I

\1/

2. -1- 2C

/I~

32 1- -' 33

\1
/\

59
61

68

I 69

70

~

Ii

3C

I I

I
4A I
-I-

43

\1

SA

I

26

2D

2E

I

I

62

I

SA

/
/

72

I
I

I

2F

35

1= =1

3':==1"

3D

--

3E

I I 45 1_
I I I

44

58 I

5C

I-

63

,

- ,8

\

I

I
I

\ 3F

-

I --

I
I

I 5E

50

\

-

I

1\

,.

65

64

,

-

6E -

60

I
-

I
I
I

I I I \ I 4~
I I I
57 I I
"I - - I " II
1/\ I

\

I 74
I

I

I

47 I

4' :-

40 1\ I I 4E I \ I
I
I

6C

I 73

I
27

--

\

71

--

,I
C::,I
-

I 48 I / 40 1
I
I 1-\

I

I I
i; lE 1= =i 1F 1_-'I'

I

u_ 2511~:=1
-'-'

I 34 1__ :

/

,
60

li

Ji

~ i

10

I--,I'

==1

38

U

1- -

50 1_ -' 51 1I I 52 1_-' 53 1= =1 54
I
_'c.1 I \
58

~

1_ _

--'

--';

I I
40 I-I I 41 I ~ 142
I

a. The Grid Drivers (STROO-STRI9) on the 10939 are in the
off stale.
b. The Segment Drivers (SG01-SGI6) on the t0941 are in the
off state.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 32.
e. The Buffer Pointer is set to O.
f. The Digit time is set to 64.
g. The Normal display mode is set.
h. DATA-LOAD is set to high impedance state.
SCLK-DIS is set to VOL to disable the anode drivers in the
10941.
j. SOP is set to VOL to disable the sync pulse.

Q

i

6

s

~

Ii

Q

I 04
I 06 1_ -' 07
1
I ,I C =1,05 ==1
I - -I
I '; I
I OE - -' OF - - I
lOA I I 0. 1_ -'
1- _.,
I, 1==1
I oc I/_foo I
~
I I I
I
II
I
1_- 12 1- - 13
114 1--1. 15 I--l " I~ -'; 17 I ;
I. I I.

02

3.-=: 39 1--',.
I

4. 1--'49

~

i

I

Q

5F
-

-

67'
6F

\

I

I
I 75

I
I 76 I

I '
I 77 I

I
I

7C I III I III I III 1\1/1
78 1 I I 79 I III 7A I 1,11 78 I I~I
I I I I I I I ,I ! 1\1 70 1/1\1 7E 171'\1 7F 171\1
-

Note:

CHARACTER

1. When the paR signal is removed, SCLK-DIS is set to the high
impedance state.
2. During the initial rise time of Voo at power turn-on, the
magnitude of VGG should not exceed the magnitude of Voo.

( SG01)

( SG02)

ill~rn~rn
(SG1S)

DIGIT (GRID) DRIVERS (STROO-STR19) PLUS CURSOR

(SG11)

rn~rn ~rn

The 20 Digit (Grid) Drivers select each of the display character
positions sequentially during a refresh scan. Display segments'
are illuminated when both the Digit Drivers and Segment Drivers
for a particular character are energized simultaneously. The Cursor segment is generated by the 10939, but its timing characteristics are identical to the 16 segments generated by the 1094t.

7

3

(SG06)

4

(SGOS)

•

PNT
~ TAIL

SEGMENT DRIVER ASSIGNMENTS

Figure 1.

5-37

16-Segment PLA Character Codes

10941 • :118~39'

't

01'

00

\ ,,' Alphanumeric and Bargraph Display Control'ler

02

==
=

03

OA

=
=

08

04

-==

05

=

(Jl

06

-

,'~

09

08

=
10

18

11

=

19

20

-

,=

=

1A

13

18

21

23

22

29,

28

12

2A

oc
=

=

14

1C

=

24

-

28

'='

5
;;;;;;;

-

2C

00

OE

16

15

10

25

--

20

=
17

=
1E

-

OF

-

-

1F

=
26

=

27

(jglD
(jgJi)

2F

2E

~

agjD
30:

31

38

39

40

41

32

=
=

--

3A

33

34

=

35

==
38

3C

-

36

-

3E

30

:r1

~

-

~
~

3F

42

=

43

-

44

45

=

-

46

47

( SG09 )

=

-

( SGoa )
( SG07 )

~
:~

.'

48

49

4A

50

51

52

"

,

48

4C

53

40

4E

4F

54

55

56

57

5C

50

5E

5F

66

67

6E

6F

-

( SG05 )
( SG04 )

=
58

SA

59

58

==

-

Segment Assignments

50,

61

68

69

SA

70

71

72

63

62

64

65

}

1 of 16

78

=
=

79

==

7A

-

68

6C

73

==
=
=
=

74

=
78

60

EE

'-

76

75

5
7C

7D

7E

==
=

77

=

-

{'.:'

Figure 2.

16-Segment BarGraph Codes

5-38

}

Nof 16

7F

Alphanumeric and Bargraph Disptay ·Controller

10941- 10939
TYPICAL SYSTEM HOOKUPS

Figure 3 shows a 10941 and 10939 in a parallel interface with
the host system driving a 20 character display. Figure 4 shows
a 10941 and a 10939 in a serial interface with the host system

driving a 20 character display. Figure 5 shows a 10941 and two
10939's in a parallel interface with the host system driving a
40 character display.

• ILAMENT 1
20·CHARACTER VACUUM TUBE FLUORESCENT DISPLAY

FILAMENT 2

20
16
CURSOR STROO-STR19
Vee
Vss
VGG
10939

SG01-SG16

PNT TAIL
Vee
Vss
VGG
10941

SOP
SIP
MASTER

DATA·LOAD

CLOCK

SCLK·DIS

Figure 3.

-15V (Vel1l
N.C.

Typical Display System with Parallel Interface to Host System

FILAMENT 1
20·CHARACTER VACUUM TUBE FLUORESCENT DISPLAY

FILAMENT 2

20
16
SG01-SG16

10941

CURSOR
Veo
Vss
VGG

PNT TAIL
Voo
Vss
VGG

STROO-STR19
SOP
SIP
10939
MASTER

DATA·LOAD
SCLK·DIS

Figure 4.

Typical Display System with Serial Interface to Host System

5·39

CLOCK
02-07

-15V (V eo )
N.C.
-15V (Voo)

Alphanumeric and Bargraph Display Controller

109.41 • 10939

-

r---- FILAMENT 1
r---- FILAMENT 2

40 CHARACTER VACUUM TUBE FLUORESCENT DISPLAY

16,

20

SG01-SG16 PNT TAIL
Voo
Vss
VGG
10941

a

+5V
-45V
DATA-LOAD

STROO-STR19
Voo
Vss
VGG

10939
(MASTER)

I

DO-D7 POR

/1

II

I/O
DATA
CONTROL
HOST
SYSTEM

Figure 5.

p-

.....
'''0

CURSOR
VGG
SOP
SIP
MASTER --15V (Voo)
CLOCK

SCLK-DISI
LD

..

If

I

20 I'

CURSOR STROO-STR19
SIP
SOP
MASTER
10939
CLOCK
(SLAVE)
LD

DO-07 POR

1 1

-

---

RES

Typical Display System with Parallel Interface to Host and Two 10939 Devices

5-40

+5V (Vss)
Voo
Vss
VGG

10951

'1'

10951
BARGRAPH AND NUMERIC
DISPLAY CONTROLLER

Rockwell

PRELIMINARY
DESCRIPTION

FEATURES

The Rockwell 10951 Bargraph and Numeric Display Controller
is an LSI general purpose display controller designed to interface
to bargraph and numeric displays (vacuum fluorescent or LED).

•

16 segment drivers plus decimal point and comma tail drivers

•

16 digit drivers

• Up to 66 kHz data rate

The 10951 will drive 16-segment bargraph or seven-segment
plus comma and decimal numeric displays with up to 16 display
positions. The controller accepts command and data input words
on a clocked serial input line. Commands control the on/off duty
cycle, starting character position and number of characters to
display. Encoded data words display bargraph position (single
segment or increasing bar length), numbers, comma, decimal
and selected upper and lower case letters. No external drive
circuitry is required for displays that operate on 20 mA of drive
current up to 50 volts. A 64 x 16-bit segment decoder provides
character set decoding for the display.

• TTL compatible
•

• Serial data input for 8-bit display and control data words
• 64 x 16-bit PLA provides data decoding driving
- Any 1 of 16 bargraph segments
- 1 to 16 bargraph segments
- Ten seven-segment numeric characters (0-9)
- Comma and decimal

ORDERING INFORMATION
Part
Number
10951P-40
10951P-50
10951PE-40
10951PE-50

Direct digit drive of 20 mA for up to 50 volt displays

• Supports vacuum fluorescent or LED displays

-

Package
Type

Drive
Voltage

Plastic
Plastic
Plastic
Plastic

40V
50V
40V
50V

Temperature
Range (OC)

Eight upper and lower case seven-segment characters

• Command functions
- On/off duty cycle
- Character position

o to

+70
010 -1;70
-40 to +85
-40 to +85

•

Number of characters

40-Pin DIP package

,.-----------DATA

r------.
SCLK

TIMING
AND
CONTROL

r------.

POR

VSS ------------VDD
-------

6 x 16
DISPLAY
DATA
BUFFER

----+

64 x 16
PLA

r------+

2 x 16
DECIMAL PT.
COMMA TAIL

+
DIGIT DRIVERS
(GRID)

A 4--

SEGMENT
DECODER

r-----+
SEGMENT
DRIVERS
(ANODE)

SGA
SGB
SGC
SGD
SGE
SGF
SGG
SGH
SGI
SGJ
SGK
SGL
SGM
SGN
SGO
SGP
PNT
TAIL

++++++++++++++++
10951 Block Diagram

Document No. 29000094
5-41

Data Sheet Order No. 094
Rev. 2, October 1984

l:I

Bargraph and Numeric Display Controller

10951
INTERFACE DESCRIPTION

Vss
ADI6-ADI
Voo
A
POR
DATA
SCLK
SGA-SGP
TAIL
PNT

Pin No.
1
2-17
18

19
20
21
22
23-38
39
40

PNT

VSS

10951 Pin Functions
Signal Name

TAIL

AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
ADS
AD7
AD6
ADS
AD4
AD3
AD2
AD1
VDD
A

Function
Power and signal reference
Digits 16 through 1 driver outputs
DC power connection
A clock output used for testing
Power-on resel input
Serial data Input
Serial data clock input
Segments A through P driver outputs
Comma tail driver output
Decimal poinldriver output

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS·
All voltages are specified relative to Vss.

SGP
SGO
SGN
SGM
SGL
SGK
SGJ
SGI
SGH
SGG
SGF
SGE
SGD
SGC

SGa
SGA
SCLK

DATA

POR
Parameter

Symbol

Value

Unit

Supply Voltage
Operating Current
Input Voltage
Output Voltage
Operating Temperature
Commetcial
Industrial
Storage Temperature
Input Capacitance
Output Capacitance

Voo
VIN
VOUT

+0.3 to -20
7
+0,3 to -20
+0,3 to -50

V
mA
V
V

To
TI
T STG
CIN
COUT

o to +70
-40 to +85
-55 to + 125
5
10

·C
·C
·C
pF
pF

100

10951 Pin Configuration

"NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause perma!,)ent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
other sections of this document is not implied, Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

DC CHARACTERISTICS

=tI)

Limits (Vss

Limits (Vss

= +5V)

Parameter

Min

Typ

Max

Min

Typ

Max

Supply Voltage (Voo)
Input DATA,SClK,
Logic "1"
Logic "0"
Input POR
Logic "1"
Logic "0"
Output Digit and
Segment Strobes
Driver On
Commercial
Industrial

-16,5

-15,0

-13,5

-11,5

-10,0

-8,5

V

-1.0
Voo

+0,3
-4,2

+4,0
Voo

+5,3
+0,8

V

-3,0
Voo

+0.3
-10,0

+2,0
Voo

+5,3
-5,0

Driver ,Off 10951-40
Driver Off 10951-50

-1,5
-1,7
-40
-50

-35
-45

Output Leakage
Input Leakage

Conditions

Unit

+3,5
+3,3

}

At 10 mA

V
V

-30
-40

}

Actual value
determined by
external circuit

V
V

10
10

}

Per driver at
driver off

~A
~A

-35
-45

10
10

Note: All outputs require Pulldown Resistors,

AC CHARACTERISTICS
Parameter
SCLK Clock
On Time
On Time
Data Input Sample Time
Before SCLK Clock Off
After SCLK Clock Off

Symbol

Min
1,0
1,0

Ton
TOfl
Tbofl
Taoff

200
100

5-42

Typ

Max

Unit

20,0

~s
~s

ns
ns

Bargraph and Numeric Display Controller

10951

SCLK

DATA INPUT
'DATA MUST BE STABLE DURING THIS TIME.

SCLK and Serial Data Timing

+5V
SCLK
OV
DATA

DATA

~ ~ ~ ~
I
0
0
'----,
I
~ ~ ~ t§J ~ f§il t§1 ~
1

I

oI

0

~ ~ ~ ~
I
1

CONTROL
BIT

0

I

I

0

I

I

DATA

~ DUTY CYCLE

~

0

COMMAND
BITS

1

I
I

~ BUFFER POINTER

I
I

~ DIGIT COUNT

=

15
(1 CONTROL BIT, 3 COMMAND BITS)

1

I
I
I

DATA
BITS

=

11
(1 CONTROL BIT, 3 COMMAND BITS)

1

~ ~ ~

~

=

11
(1 CONTROL BIT, 2 COMMAND BITS)

NOTE: CROSSHATCH

= DON'T CARE

~

SCLK and Serial Data (Control Word) Examples

.-----------y
NEXT
DATA WORD

END OF
DATA WORD------i
MSB

LSB

LSB

SCLK
MIN 40 I'SEC
MIN 120 I'SEC

Data Word LSB/MSB Timing

VDD

~

I

VDD STABILIZED

~"",...-~---+--t

_100 1'5-f-100 1'5(MIN)
(MIN)

POR

I'--_+-t ~I- J

OATAlCOMMAND

Power-On Reset
5-43

~I!-I--

DATA VALID

Bargraph and Numeric Display Controller

10951
FUNCTIONAL DESCRIPTION

Buffer Pointer Control
The Buffer Pointer Control code allows the Display Data Buffer
pointer to be set to any digit position so that individual characters
. may be modified. The Buffer Pointer is loaded with a decimal
equivalent value 2 less than the desired value (i.e., to pOint to
the digit controlled by AD6 of the display, a value of 4 is entered).
See Table 2 for a complete list of the Buffer Pointer values.

The 10951 receives commands and data on a serial input line
clocked externally by a separate clock input line. The controller
decodes the commands from control data words, decodes the
data words in accordance with an internal 64 x 16-bit programmable logic array (PLA) and turns on and off segment and digit
output drivers. The segment output patterns are controlled by
the decoded data words while the digit output and segment output timing are controlled by the decoded control words. All timing
signals required to control the display are generated in the 10951
device without any refresh input from the host processor.

Digit Counter Control
The Digit Counter Control code is normally used only during initialization routines to define the number of character positions
to be controlled. This code maximizes the duty cycle for any
display. If 16 characters are to be controlled, enter a value of 0
(zero). Otherwise, enter the value desired.

Input data is loaded into the Display Data Buffer via the Serial
Data Input (Data) channel. Internal timing and control blocks synchronize the segment and digit output signals to provide the
proper timing for the multiplexing operation. The 16 x 64 PLA
decodes a-bit data words to drive the 16 segment, comma and
decimal point drivers. The decoded data words will drive 16 segments to display bargaph patterns (Single segment and multiple segment for increasing length displays) or seven-segment
patterns to display numbers, selected upper and lower case
letters, comma and decimal point.

Duty Cycle
The Duty Cycle Control code is used to turn the display on and
off, and to adjust display brightness. As shown in the block
diagram, the time slot for each character is 32 clock cycles. The
Segment and digit drivers for each character are on for a maximum of 31 cycles with a 1 cycle inter-digit off-time. The Duty
Cycle Control code contains a 5-bit numeric field which modifies
the on-time for the driver outputs from 0 to 31 cycles. A duty
cycle of 0 puts both the segment and digit drivers into the off
state. Figure 1 shows the timing characteristics for the segment
outputs.

Input data is loaded. into the 10951 as a series of a-bit words with
the most significant bit (MS8)., bit 7 first..!f the MSB is a logic 1
(this bit is referred to as the control bit C), the loaded word is a
control data word. If the C bit of any word is a logic 0, the loaded
word is a display data word. The following paragraphs describe
the format and functions of these control and display data words.

INPUT CONTROL DATA WORDS
When the C-Bit (bit 7) of the a-bit input word is a logic 1, bits 5
and 6 are decoded into one of four control commands while data
associated with the command are extracted from bits 0-4. There
are four control codes which perform the following display
functions:
• Load the Display Data Buffer pointer,
• Load the Digit Counter,
• Load the Duty Cycle register,
• Enter Test Mode.
Table 1 lists the control codes and their functions.

Table 1.

Test Mode Enable
The Test Mode Enable code is a device test function only. If
executed, it will lock the device in the Test Mode. This mode
can be disabled only by performing a power-on reset.

If this mode is activated, the digit time is reduced from 32 to
4 clock cycles to speed up the output driver sequencing time
for ease in testing.

Control Data Words

8-Blt Control Word
C-Bit

7-lm Code

Function

1
1
1
1

010NNNN'
100NNNN'
l1NNNNN2
OONNNNN3

Load Buffer Pointer (Position of character to be changed)
Load Digit Counter (Number of characters to be output)
Load Duty Cycle (On/off and brightness control)
Enter Test Mode (Not a user function)

Note:
1. NNNN is a 4-bit binary value representing the digit number to be loaded.
2. NNNNN is a 5-bit binary value representing the number of ck>ck cycles each digit is on.
3. This code is a device test function only. If executed it will lock the device in the Test Mode. Test Mode can be
disabled only by performing a power-on reset.

5-44

Bargraph and Numeric Display Controller

10951
Table 2.

Buffer POinter Control Codes

Hex Code

Pointer Value

Character Controlled By

AO
A1
A2
A3
A4
A5
A6
A7
AS
A9

16
1
2
3
4
5
6
7
S
9
10
11
12
13
14
15

AD2
AD3
AD4
AD5
AD6
AD7
ADS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD1

AA

AS
AC
AD
AE
AF

Sixteen display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer is automatically
incremented before each data word is stored in the Display
Buffer except for decimal point and comma words. The decimal
point and comma words do not cause the Buffer Pointer to
increment and thus are always associated with the previous
character entered. To enter a character position out of the normal
sequence, use the Buffer Pointer control command before entering the display data word. It is not necessary to use the Buffer
Pointer control command to cycle back to position 1 when less
0).
than 16 character positions are being used (Digit Counter

*'

DIGIT DRIVERS (AD1-AD16)
The sixteen Digit Drivers (AD1 - AD16) are used to select each
of the display digits sequentially during a refresh scan. Display
segments will be illuminated when both the Digit Drivers and
Segment Drivers for a particular character are energized
simultaneously. The timing characteristics of both the digits and
segments are shown in Figure 1. See paR for the Power-On
Reset state of these drivers.

INPUT DISPLAY DATA WORDS
Display data words are loaded as S-bit format codes. There are
64 codes available (with the C-bit set to 0 to indicate a display
data word).

V
ss
AD1
AD2

- V

~

II

I

ADS

II

n

I I

AD7

I I

ADS

rl

n

1

I I

AD6

n

r-L-

n

I I
I I

AD9
AD10

n
II

n

I I

AD11

11

I I

AD12

II

I I
I I
I I

AD13
AD14
AD15

I

AD16

11
11

n

I

.1 I'"

n
31 BIT TIMES

Vs~

SGX -V

I
I

II
.1 I'" 1 BIT TIME
II

n

II

I I

AD4

-I

f"l1 BIT TIME

I I

AD3

1 DISPLAY CYCLE
512 BIT TIMES

I.. i 31 BIT TIMES

n
NOTE:
TiMING SHOWN

!Lf"I
is

FOR i6 CHARACTERS WiTH A DUTY CYCLE 0;-: :J~.

Figure 1. Display Scan Timing Diagram (Duty Cycle)

5-45

II

10951

Bargraph and Numeric Display Controller

POWER-ON RESET (POR)

decimal point are shown in Figure 2. The input codes associated
with seven-segment alphanumeric, comma and decimal point
display are also shown in Figure 2. The complete set of a-bit
codes for the bargraph and alphanumeric display is shown in
Table 3. Note that only segment drivers SGA-SGG are used to
drive the seven-segment characters. Segment drivers SGH-SGP
may be used for other purposes as decoded in accordance with
Table 3. Figure 3 shows the total allocation of the 16-segment
drivers as they would appear on a 7-segment display or a
16-segment bargraph display. Timing characteristics for the
segment outputs are shown in Figure 1. See paR for the
Power-On Reset state of these drivers.

The Power-On Reset (POR) initializes the internal circuits of the
10951 when power (Voo) is applied. The following conditions
are established after a Power-On Reset:
a. The Digit Drivers (AD1-AD16) are in the off state (floating).
b. The Segment Drivers (SGA-SGP) are in the off state (floating).
This includes PNT and TAIL.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 16 (a bit code value of 0).
e. The Buffer Pointer points to the character controlled by AD1.

SEGMENT DRIVERS (SGA-SGP)

TYPICAL SYSTEM HOOK-UP

Sixteen (16) Segment Drivers are provided (SGA-SGP), plus the
decimal pOint (PNT) and comma tail (TAIL). The segment, PNT
and TAIL outputs are internally decoded from the a-bit characters
in the Display Data Buffer by means of a 64 x 16-bit PLA. The
driver allocations for the 16-segment bargraph display and
the seven-segment alphanumeric character plus comma and

Figure 4 shows the 10951 as it would be connected to a V-F
display when driven by a host system. EK is determined by the
V-F display specifications and Rc is selected to provide proper
biasing current for zeners. Pull down resistors RA and RG are
determined by the interconnection capacitance between the
10951 and the display.

5-46

10951

Bargraph and Numeric Display Controller
Table 3.

Input Code
7 6

5 4 3 2 1 0

0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X 0 0
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X

O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1

0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0 0 0 0
0 0 0 1
0 0 1 0

0
0
0
0
0

0

1
1
1
1
1
1
1
1

0 0 0

1

1

1 0 0
1 0 1
1 1 0
1 1 1

0 0

1

0 1 0
0

1 1

1
1
1
1

0 0
0 1
1 0

0 0
0 0
0 0
0 0

0 0

0
0

0
0
1
1
1
1
1
1
1
1

1

1

0 1
1 0
1

1

1
1
1
1

0 0
0 1
1 0

0
0
0
0

0 0

1 1

0

1
1
1 0
1 0
1 1
1 1

0
0
0
0
0
0
0

1

0
1

0
1

0
1

0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 0 1
0 1 0

0 0

0

0

1 0

0 0
0 1
1 0
1 1

0 0
0 1
1 0
1 1
1

0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0

1

1 0

1

0 1 1 1 0
0 1 1 1 1

0 X 1 1 0 0 0 0
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X

1
1
1
1
1
1
1
1
1
1
1
1
1
0 X 1
0 X 1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0 0 0 1
0 0 1 0

0 0 1
0 1 0
0 1 0
0 1 1
0
1
1
1
1
1
1
1
1

1

1

0
1

0

1 1

0 0 0
0 0

1

0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1

1

10951 Data Codes
Segment Driver Output Patterns (1

Function

-:4~

= On)

SGA SGB SGC SGD SGE SGF SGG SGH SGI SGJ SGK SGL SGM SGN SGO SGP PNT TAIL

Segment AOn
Segment BOn
Segment C On
Segment DOn
Segment E On
Segment F On
Segment G On
Segment H On
Segment I On
SegmentJ On
Segment K On
Segment L On
Segment M On
Segment N On
Segment 0 On
Segment P On

1

Segment A On
Segments MB On
Segment A·C On
Segment A·D On
Segment A·E On
Segment A·F On
Segment A·G On
Segment A-H On
Segment A-IOn
Segment A.J On
Segment A·K On
Segment A·L On
Segment A·M On
Segment A·N On
Segment A·O On
Segment A·P On

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Number 0
Number 1
Number 2
Number 3
Number 4
Number 5
Number 6
Number 7
Number 8
Number 9
Letter P
letter L
Comma
Blank
DeCImal
Blank

1

Number
Number
Number
Number

0
1
2
3
Number 4
Number 5
Number 6
Number 7
Number 8
Number 9
Letter A
Letter b
Letter C
Letter d
Letter E
Letter F

1

1
1
1
1
1

Any 1 of
16 Segments

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1

1

1

1

1
1

1

1
1

1

1
1

1
1
1

1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1

1
1
1
1
1
1
1

I

1
1
1

1 to 16
Segments

1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
i
1
1

1
1
1
1
1
1

1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1

1
1

1
1
1
1
1
1
1
1
1
1

1
1

1
1

I
1
1
1
1
1
1
1
1
1

1
1
1
1
1

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

1

1

1

1
1

1

1
1

1

1
1
1
1
1
1

1

1

I

1
1
1
1
1
1

1
1
1
1
1
1
1
1

I
1
1
1
1
1

I

1
1
1
1
1

1
1

I

1

Notes:
Sets comma and decimal outputs for last character entered,
.. Sets decimal output for last character entered.

5-47

I

Bargraph
Codes

I

1
1
1
1

1
1
1

1
1
1

r

1

-E-

j

I

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1 '

I'

; I

; I

I'

AI phanumerlc
and
Special
Codes

1"

,

1-'-

Bargraph and Numeric Display Controller

10951

00

I

01

02

I

03

08

10

09

11

I

19

OA

12

I

1A

OB

13

04

05

06

07

I
I
-

18

II

OC

14

00

15

OE

16

OF

17

II
IIIII-

I
I
I
I
I
I
I
I
I
I

1B

1C

10

I- I
I- I
I- I
I- I
I- I
I- I
I- I
I- I
I- I
I- I
I I
I-I

20

I I
I- I

21

22

23

24

25

-

-

I
I
I

II
I
I- I
I
-

I-

I

I- I
I- I

28

I- I
- I
I- I
I
I
I-

29

2A

2B

,
•

2C

30

31

32

33

34

20

35

1E

I- I
I- I

26

II- I

2E

• 36

1F

I- I
I- I

27

I
I

2F

37

SGPSGOSGNSGMSGLSGKSGJ SGI
SGHSGGSGFSGESGDSGCSGBSGA-

-

HI-SEGMENT
BARGRAPH

I I
I- I
I
I
- I
I- I
- I
I- I
I
I- I
II- I
I
I

38

39

3A

3B

3C

3D

3E

3F

SGA

SGF

SGB
SGG

SGE

SGC
SGD

• PNT
,TAIL

7-SEGMENT
ALPHANUMERIC

Figure 2. Segment Allocation and 7-Segment Alphanumeric Codes

5-48

I- I
I- I
I- I
- I
I- I
I I
II- I
I
I- I
I- I
II-

II

Bargraph and Numeric Display Controller

10951

00

01

02

03

04

05

06

07

08

09

OA

OB

OC

OD

OE

OF

SEE FIGURE 2

1

1

7·SEGMENT
CHARACTERS

SGP_
SGO_
SGN_
SGM_
SGL_
SGK_
SGJ_
SGI_
SGH_
SGG_
SGF_
SGE_
SGD_
SGC_
SGB_
SGA_

BARGRAPH
CODES

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

7·SEGMENT
CHARACTERS

SEE FIGURE 2
SGP_
SGO_
SGN_
SGM_
SGL_
SGK_
SGJ_
SGI_
SGH_
SGG_
SGF_
SGE_
SGD_
SGC_
SGB_
SGA_

BARGRAPH
CODES

20

21

10

22

23

24

25

26

27

28

29

2

3

4

5

6

7

8

9

2A
P

2B

.

2C

2D

2E

2F

L

1

7·SEGMENT
CHARACTERS

SGP_
SGO_
SGN_
SGM_
SGL_
SGK_
SGJ_
SGI_
SGH_
SGG_
SGF_
SGE_
SGD_
SGC_
SGB_
SGA_

•=PNT and TAIL both set
•• =PNT only set
SPECIAL
BARGRAPH
CODES

30
10

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

2

3

4

5

6

7

8

9

A

B

C

D

E

FI

SGP_
SGO_
SGN_
SGM_
SGL_
SGK_
SGJ_
SGI_
SGH_
SGG_
SGF_
SGE_
SGD_
SGC_
SGB_
SGA_

7·SEGMENT
CHARACTERS

1
-

J

Figure 3. Total Character Allocation for Bargraph or 7·Segment Displays

5·49

SPECIAL
BARGRAPH

CODES

Bargraph and Numeric Display Controller

" .

10951

+5
DATA

Vss

101'1
10951

+5

VDD
ADX

SGX

16

TYPICAL
GRID
(DIGIT)
DRIVER
CIRCUIT

POR

16

TYPICAL
ANODE
(SEGMENT)
DRIVER

aocurr

VACUUM
FLUORESCENT
DISPLAY

~

___ !~

-VD1SP

Figure 4. Partial System Schematic

5-50

HOST
SYSTEM

10955

'1'

Rockwell

10955
SEGMENTED DISPLAY CONTROLLER/DRIVER
PRELIMINARY

DESCRIPTION

FEATURES

The 10955 Segmented Display/Driver is a MOS/LSI device
capable of directly driving both the grids and anodes of multiplexed vacuum-fluorescent segmented displays. All timing
circuits (including a clock generator) required to control the
display drivers are contained within the device. The 10955 can
drive segmented displays with 8 or 16 grids (characters) and
8, 16, or 24 anodes (segments). A serial interface allows for a
host microprocessor to transmit commands and display data to
the 10955 directly.

•
•
•
•
•
•
•
•
•
•

A 128 x 16 bit PLA provides coding for both 16-segment and
14-segment alphanumeric ASCII code character sets (all caps
only). The PLA is divided into lower 64 and upper 64 code sets.
Only one set can be selected at a time. In lower set mode the
16-segment display characters are selected. In upper set mode
the 14-segment display characters are selected. The PLA can
also be bypassed so that data words from the host microprocessor are loaded directly into segment drivers without
decoding by the PLA. This mode is especially useful for creating
special display patterns such as bar graph displays. Bypass
mode is limited to eight drivers per data word.

DATA IN
SCLK
LD
POR
VDD
VSS

8- or 16-character display driver
8-, 16-, or 24-segment drivers
Average data rate 66 kHz
Single character burst rate 500 kHz
Direct digit drive of 20 ma for up to 40 or 50 volt vacuumfluorescent serial displays
128 x 16-bit PLA provides 16- or 14-segment alpha-numeric
character set
Internal clock generator circuit
Serial host interface
PLA bypass mode
40-pin DIP

ORDERING INFORMATION

DISPLAY
DATA
BUFFER
(16x6)

8

Part
Number

Package
Type

Drive
Voltage

Temperature
Range (OC)

10955P-40
10955P-50
10955PE-40
10955PE'50

Plastic
Plastic
Plastic
Plastic

40V
50V
40V
50V

o to +70
o to +70
-40 to +85
-40 to +85

SEGMENT
DECODER
PLA
144x16

16

SEGMENT
DRIVERS

C12P

VGG

SGA
SGB
SGC
SGD
SGE
SGF
SGG
SGH
SGI
SGJ
SGK
SGL
SGM
SGN
SGO
SGP

10955 Block Diagram

Document No. 29001036
5-51

Data Sheet Order No. 0136
October 1984

EI

Segmented Display Controller/Driver

10955
INTERFACE DESCRIPTION
Signal Name

Pin No.

Function

1
2
3
4
5-20

Power and signal reference
Test clock-factory test
Serial input data clock
Serial data input
Segments A through P driver
outputs
Direct segment outputs or
strobe outputs
Strobe outputs
Display voltage
Logic supply voltage
Power on reset
Data Load Strobe

Vss
C12P
SCLK
DATAIN
SEGA-SEGP
D7/STRI5-DO/STR08
STR07-STAOO
VGG
Voo
POR
LD

21-28
29-35,37
36
38
39
40

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS'
Ali voltages are specified relative to Vss.
Parameter

Symbol

Value

Unit

Supply Voltage
Operating Current
Input Voltage
Display Voltage
Operating Temperature
Commercial
Industrial
Storage Temperature
Input Capacitance
Output Capacitance

Voo
VIN
VGG

+03to-25
8
+0.3 to -25
+0.3 to -50

V
rnA
V
V

Tc
TI
TSTG
CIN
COUT

o to +70
-40 to +85
-55 to + 125
5
10

°C
°C
°C
pF
pF

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Vss
C12P
SCLK
DATAIN
SEGA
SEGB
SEGC
SEGD
SEGE
SEGF
SEGG
SEGH
SEGI
SEGJ
SEGK
SEGL
SEGM
SEGN
SEGO
SEGP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

LD
POR
Vee
STROO
VGG
STROI
STR02
STR03
STR04
STR05
STR06
STR07
DO/STR08
Dl/STR09
D2/STR10
D3/STRll
D4/STRI2
D5/STRI3
D6/STRI4
D7/STRI5

10955 Pin Configuration
"Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is astress rating only and functional operation of the device
at these or any other conditions above those indicated in the
other sections of this document is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

DC CHARACTERISTICS
(VDD = - 18.0 to - 22.0 Vdc, VS5
All voltages referenced to V 55.)

= 0 Vdc, TA = oDe to

Parameter
Operating Current, Logic
Commercial
Industrial
Operating Current Display
(1 strobe plus 24 segment)
Commercial
Industrial
(1 strobe plus 16 segment)
Commercial
Industrial
(All display drivers)
VGG and 85°C
Display voltage
10955·40
10955·50
Input Leakage (at - 20V)
Input (DATAIN, LD, SCLK)
Logic "1"
Logic "0"
Input POR
Logic "1"
Logic "0"
Output (C 12P)
Logic "1"
Logic "0"1
Output (Strobe STROO-07, DO-D7, SGA-SGP)
Logic "1" (I Load = 10 rnA)
Logic "1" (ILoad = 20 mA)2
Logic "0" (I Load = 0 rnA)

+ 70 0 e (commercial) or - 40 0 e to + 85°e (industrial), unless otherwise noted.

Symbol
100

Min.

Typical 3

Max.

Unit
rnA

-

3.2
4.0

6.4
8.0

-

-

6.5
8.0

rnA
rnA

4.3
5.3

rnA
rnA

320

p.A
V

IGG

VGG

-40.0
-50.0

-

IlL

-

10

uA
V

VIH
VIL

-1.2
Voo

-05
-6.0

+0.3
-4.2

VIHPO
VILPO

-3.0
Voo

-12.0

+0.3
-10.0

VOHSY
VOLSY

-0.7
Voo

-

+0.3

VOH
VOH
VOL

-1.5

-1.0
-2.0
0.5+ VGG

Vss
Vss
0.95 x VGG

V

V

-

V

-

VGG

Notes:
1. Open drain' driver. Requires external pull-down resistor for testing only.
2. STROO-STR07 only (also for DO-D7 when used as character drivers)

5-52

3. Typical measured at Voo

= 20.0V and

YA

= 25°C.

10955

Segmented Display Controller/Driver

AC CHARACTERISTICS
Characteristic

Clock Timing Cycle Time
Commercial
Industrial

Symbol

Min.

Typical

Max.

Unit

6.66
5.88

20.0
22.2

usec
usec

usec
usec
usee

tCYC

HOST INTERFACE TIMING
Serial Clock (SCLK)
On Time
Off Time
Cycle Time

tSCON
tSCOFF
tsccyc

1.0
10
2.0

40.0

Serial Data (DATAIN)
Set-up Time
Hold Time

tSSETUP
tSHOLD

400
400

nsec
nsec

Serial Clock to LD Time

tSL

600

LD to Serial Clock

t LS

400

-

Data Load (LO)
On Time
Off Time (Commercial
Off Time (Industrial)
Cycle Time (Commercial)
Cycle Time (Industrial)

t LOON
t LOOFF
t LOOFF
t LDcyC
tLOCYC

-

usec
usec
usee
usec
usec

-

1.0
40.0
44.5
60.0
66.7

nsec
nsec

-

-

Note:
Ir and If = rise and fall lime of clocking signals which are 10 10 30 nsec.

~-----------tsc~c------------~~

tSCOFF
tr

SCLK

- tLDOFF
LD

~

f+---------

Serial Interface Timing Waveforms

5-53

tLD~C ~

r-==- -

----DATAIN~r DATAVALID
_DATAVALID~

----;jc-

Segmented Display Controller/Driver

10955

GND

1
r· !

' - ; - - - - - - - - - 1 DISPLAY CYCLE _ _ _ _ _ _ _ _ _ _~I
61 BIT TIMES
1024 BIT TIMES
•

sm ~3BITTIMES
~h~~~~----------------------------~r;~----------n

I
'"-------S~ ~1-+-~rJ~------------------------------------------~rI~------­

ST1

S~ ~I-+----n~--------------------~
II
n
r-t....
________________________________________
___
I
_________________________________________

ST4
ST5

rJ~

S~

ST7

rI~

~1-+--------~r1~-------------------------------------

_________________________________
I
___________________________
~I~--------------------------rl~-----------------------------

~~ ~I~--------------------~n rJ~
03
02

04
05
06

~

rI~

~1_+-------------------~r1~----------------

nl----------

I

~I_+------------------------------------~~~-----------------I
rl'"-_____________
I .. 61 BIT TIMES
____
~

SGX GND

~

~rI~

_____________

r_urJ~

______

-VI II
1--11- 3 BIT TIMES
I

II

Notes:
1. tCYC = 2 bit times.
2. Timing shown is for 16 characters with a duty cycle of 61.

Display Scan Timing Diagram

FUNCTIONAL DESCRIPTION

loaded directly from the Data Buffer (RAM). In other modes these
drivers are used as extra character (grid) drivers (STR8-STR15).
See Display Modes for further discussion of these driver
functions.

All timing signals required to control the display are generated
by the 10955 device after the display buffer and control registers
have been loaded from the host processor. In the fOllowing functional description, refer to the 10955 block diagram.

SEGMENT DRIVERS (SGA-SGP)

Input data is loaded into the Display Data Buffer via the serial
data input channel. Internal timing and control logic synchronize
the digit output signals with the segment output signals to provide the proper timing for the multiplexing operation. The segment decoding is performed in a 128 x 16 PLA character code
set.

SYSTEM CLOCK

CHARACTER DRIVERS (STROO·STR07)

Each 10955 device has its own on-board oscillator and clock
generator.

Depending on the display mode, the sixteen segment drivers
are loaded through an 8 x 16 PLA decoder or directly from the
Data Buffer RAM.

The eight character (grid) drivers are used to select the display
character positions sequentially during a refresh scan. Display
characters are illuminated when both the character driver for
a particular character position and the segment (anode) drivers
are energized simultaneously.

POWER·ON RESET
The Power-On Reset (POR) input initializes the internal circuits
of the 10955. This is normally performed when power (VDD) is
applied. The following conditions are established by application
of POR:

DISCRETE DRIVERS (00·07)
The function of these eight drivers depends on the display mode.
In some modes these drivers act as segment (anode) drivers

a. The grid and anode drivers (STROO·STR07, 00-07, and SGASGP) are in the off state.

5-54

Segmented Display Controller/Driver

10955
b.
c.
d.
e.
f.

The following sections describe the format and functions of the
input words which may contain either control data or display
data.

Duty Cycle register is set to zero.
The Digit Counter is set to 32 digits.
The Buffer Pointer is set to zero.
The Digit Time is set to 64.
The PLA Bypass/Sixteen Digit display mode is set.

Input Display Data Words
Display data words are loaded as nine bit codes. The lower eight
bits (7-0) are data. The ninth bit (the most significant) is always
a zero (0).

At power on, the 10955 is held in an internal halt mode. This
allows the host system to load the control registers and the data
buffer without flashing invalid data on the display.

Sixteen display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer is automatically
incremented after each data word is stored in the buffer. To
select the next character pOSition to be loaded out of the normal
sequence, use the Load Buffer Pointer command. The Buffer
Pointer will automatically reset to character position 0 when its
value is equal to the Digit Counter programmed value.

During the initial rise time of VDD at power turn-on, the
magnitude of VGG should not exceed the magnitude of VDD.

HOST SYSTEM INTERFACE
Input data is loaded into the 10955 via a serial data input channel as a series of nine-bit words.

Control Data Words

After nine bits of data (with the most significant bit first) have
been shifted into the data buffer, a pulse on the LD signal loads
the data into an internal buffer and informs the 10955 that a new
data word is available. After the LD pulse, a new data word may
be shifted in while the 10955 is processing the first word.

8

7

I

6

I

I1

I

5

LOAD

I

X

0

I

4

I

3

I

2

D~TA

I

I

I

I

1

Control data words are distinguished from display words by the
fact that the most significant bit is always a one. Control words
and their functions are defined below. The most Significant bit
is implied as always being a 1 for these functions.

I

0

I

I

BIT

I

PLA MODE I CONFIG·I DIGIT TIME I

X

X

X

X

X

DUTY CYCLE, DIGIT COUNTER, BUFFER POINTER
...-- CONTROL REGISTER
LOAD DUTY CYCLE REGISTER
(with lower 6 bits)

0

0

0

0

X

X

X

X

X

LOAD DIGIT COUNTER
(with lower 5 bits)

0

0

X

X

X

X

LOAD BUFFER POINTER
(with lower 4 bits)

0

X

X

X

X

X

LOAD CONTROL REGISTER
(5 bits coded as shown below)

0
0

X
X
X
X
X
X

X
X
X
X
X
X

0

0

0

0

0
0

0
0

0
0

0

0

0

0

0

0

0

0
0
0

0
0
0

0
0
0

0

0
0

0
0

X
X
X
X

0
0

0
1
0

0

64 cycles per grid
16
32
8
16

cycles per grid
cycles per grid
cycles per grid
digit configuration

8 digit and two output

0

PLA bypass
Reserved for upgrade
Lower 64 PLA (64U)

1

Lower 64 PLA (64L)

5-55

Segmented Display Controller/Driver

10955
Load Buffer Pointer

data is not affected although the duty cycle is decreased as each
phantom strobe is added. The code, digit counter value, and
number of grids controlled by the Digit Counter are shown in
Table 2.

The Load Buffer Pointer code sets the Display Data Buffer
Pointer. The three most significant bits of the loaded code value
are dropped and the five least significant bits are loaded into
the Control Data Word to provide the character position data
shown in Table 1.

Table 1.

Table 2.

Load Buffer Pointer Codes

Load Code
Value

Pointer
Value

Character Position
Selected

CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CO
CE
CF

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Code

80
81 .
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F

Note: ~O-OF (Not Used)

Load Digit Counter
The Load Digit Counter command defines the number of character positions (grids) to be controlled. This code is normally used
only during initialization routines, but it may also be used in conjunction with the Load Duty Cycle control code to extend the
range of brightness control. The display should be set up with
digit 0 on the left and digit 15 on the right. The number of positions to be controlled starts at position 0 and increases to position 15. If 17 through 32 grids are specified, extra time slots are
generated for these phantom strobes. When the phantom
strobes are active, strobes 0 through 15 are off so the displayed

5-56

Load Digit Counter Control Codes
Digit
COII.nter Value

00
·01
02
03
04
05
06
07
08
09
OA
OB
·OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
lB
1C
10
IE
1F

.'

~o.

of Grids
Controlled

32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

Segmented Display Controller/Driver

10955
Load Duty Cycle

codes. The segment and digit drivers for each character are on
for a maximum of 13, 29, or 61 cycles with'a 3 cycle inter-digit
off time. The lower six bits of the Load Duty Cycle code are
loaded into the Duty Cycle Register. Resultant duty cycles,
on-times, and off-times are shown in Table 3.

The Load Duty Cycle code is used to turn on and off the display,
to adjust display brightness, or to modify display timing. The time
slot for each character is 8, 16, 32, or 64 internal cycles (an
internal cycle .. 1/2 tCYC as selected by the Set Digit Time

Table 3. Load Duty Cycle Control Codes
Digit Time
Code

On

40
41
42
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53

-

1
2
3
4
5
5
5
5
5
5
5
5
5
5
5
5

5

=8
Off
8
8
8
7
6
5
4
3
3
3
3
3
3
3
3
3
3
3
3
3

Digit Time

On

--

1
2
3
4
5
6
7
8
9
10
11
12
13
13
13
13
13

= 16

Dlilit Time .. 32

Dlilit Time .. 64

Off

On

Off

On

Off

16
16
16
15
14
13
12
11
10
9
8
7
6
5
4
3
3
3
3
3

-

32
32

-

64
64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

32

31
30
29

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

"

58
5C
50
5E
SF
60
61
62

5
5
5
5
5
5
5
5

3
3
3
3
3
3
3
3

13
13
13
13
13
13
13
13

3
3
3
3
3
3
3
3

7C
70
7E
7F

5
5
5
5

3
3
3
3

13
13
13
13

3
3
3
3

5-57

25
26
27
28
29
29
29
29

29
29

29
29

7
6
5
4
3
3
3
3

25
26
27
28
30
31
32

39
38
37
36
35
34
33
32

3
3
3
3

58
59
60
61

6
5
4
3

29

Segmented Display Controller/Driver

10955
Loaa Control Register

adjacent drivers which can be connected externally to provide
twice the current drive of an individual driver. The data
bits/segments selection allocation is as folloWs:

There is a Ej-bit control register, which can be loaded by the
control word, OOOXXXXX. The lower 5 bits of the control word
is loaded into the control register.
The least significant two bits of the control register set the total
Digit Time for each character during the refresh cycle. Four
values can be set using the codes, 8, 16, 32, or 64 cycles per
grid. The default value set at power-on is .64 cycles per grid.
Under conditions where the display can be subjected to quick
movements during viewing (e.g. portable or vehicle mounted
applications) it may be necessary to increase the refresh rate
by selecting 8, 16 or 32 cycles per grid with the appropriate
control codes.

Data bit

7

6

5

4

3

2

. Segments

O,P

M,N

K,L

I,J

G,H

E,F'

o
C,D

A,B

Upper 64 PLA Mode (64U)
In this mode (bit 5 = 1, bit 4 = 0) the Upper 64 out of the 128 codes
are used, (Le., 64 to 127). Since 64 codes can be specified by
a 6-bit word, the most significant two bits of the 8-bit word from
the RAM are not used. Another feature of this 64U-PLA mode
is that the most significant two bits of the data can be brought
out directly to SEGO and SEGP outputs.' Therefore, the 64 codes
can be decoded to the 16-segment outputs, or only 14-segment
outputs leaving two for direct output from the RAM ..

The middle bit of the 5 bit determin~s the sixteen digit or eight
digit configurations. The last 2 bits select one of the four PLA
Modes.

Lower 64 PLA Mode (64L)
This mode (bit 5 = 1, bit 4 = 1) is similar to the Upper 64 PLA
Mode, but only the lower 64 codes (0-63) out of the 128 codes
are used. The 64L and 64U PLA modes allow two independent
sets of 64 codes to be programmed into one chip. In running
the display, only one set can be selected at a time.

ENABLE DISPLAY MODE
The 10955 can operate In one of eight display modes which
control the maximum number of active strobes and segments
and the manner in which the RAM Data Buffer is decoded onto
the segment drivers.

Fourth PLA Mode
A fourth PLA mode is reserved for future expansion of the 10955.
This code (bit 5 = 0, bit 4 = 1) should not be used. Selecting this
PLA mode may result in non-defined characters appearing on
the display.

16-Digit Configuration
If the third bit of the control register is zero or is reset by the
POR signal, the 16-digit configuration is selected, in which case,
a maximum of 16 segments and 16 strobes are provided. The
16 words in the RAM Data Buffer correspond to the 16 strobes.
The 8 data bits of each word are sent to the PLA for decode.

PLA CHARACTER SET CODES
Figure 1 shows the 16-segment and 14-segment driver assignments for the corresponding segmented displays. Figure 2
shows the 16-segment and 14-segment PLA character set
patterns coded into the 10955.

8 Digit Configuration
If the third bit of the control register is set, the 10955 is configured into 8-digit mode, in which case, a maximum of 8 strobes
and 24 segments are allowed. The 8-bit words in the RAM Data
Buffer are grouped into 8 word pairs which correspond to strobes
STRO-STR7: 0-1,2-3,4-5,6-7,8-9,10-11,12-13, and 14-15. The
data in the even-numbered word of each pair is loaded into the
direct-output segment drivers (DO-D7), but the data in the oddnumbered word of each pair is decoded in the segment PLA
decoder before being loaded into the 16-segment output drivers
(SGA-SGP).

PLA Bypass Mode
If both of the most significant bits of the control register are zero,
the PLA Bypass Mode is selected. In this mode, the PLA is
bypassed. Each data word is loaded directly into the segment
drivers without being decoded by the PLA. Since there are only
8 data bits but 16 drivers, each data bit is loaded into two

l6-Segment
Figure 1.

5-58

l4-Segment

Segment Driver ASSignments

Segmented Display Controller/Driver

10955

00

08

10

18

- -I
I I 03
I 01 I
02
I- I I I I - I- I
I I 09 I OA
I 08
1- -I
I- - I
-II I 11 I I 12 I I 13
I \
I
I \1
\1 19 \1 1A I 18
1\
I
I
--

20

21

\1

22

I I

23

/

29

30

\

I II
II
- -

I
I

31

1

38

2A

I

\

32

\11
11\

OC

I
I

- -

I
I-

- -

I
I

-

15

\

10

\

I I
-1-1

25

- -

20

I
I 35
I

1

I

3C

/
-

16

07

I I
II

I 1E
1\
I
I II 26 \1
II - I I \1
- -

17

30

I

-

I
I

I I
1/\1

-/

27

/
/

I
I

37

- -

-- -

-

36

I
1--1

-

1F

2F

2E

I
- -I

I
I-

1\ I OF I
I \1 I-

-

I 34 I

I

I I
I- - I

I
I

-

2C

- 38

I
I

1C

33

-

I I 05 I
06
I- -I- I
1\/1 OE
I
00
I I
I- -

14

I I
-1-1 24

28

!

I-

I I I I
1--1 39 - -I 3A
--

04

- -

28

I
I- I I
1-\

3E

\

\

3F

-

I

I

- -

-

16·Segment PLA Patterns
40

I 41 I
I-I I I

48

I I 49
1- -I

50

58

60

-

I 42
I
I
I

4A

I I 43 I
I I II I
I I 48 1-\
I

I
I

I 51 I I 52
I- \1
\1 59 \1 5A
1\
I
\1 62
61
I

69

\
70

78

I II 71
II I

\

6A

I
I

4C

-

I 53 I

I
I

\

I

I

58

-

I I

63

72

1

\11
11\

68

I 73

I-

I

-

L.::
68

44

1\
I- \

78

I
II
I

54

5C

40

\
\

I I I I
-1-1 64 -1-1
I
I

6C

I
- -I

74

-" ..

I I I I 1\
1- -I 79 --I 7A II
-

I I 45 I
- I I I-

55

50

46

I
I

I 56 I /
I 1/

I
I-

II
~I

5E

1\

65

1\ I
/\1

66

I- -I

60

--

6E

\/

57

II

\1

I I 75 I
--I
- -I
'"-

/

7C

70

/
-

76

..

--

\

7E

-

\

I
I
I

I I
1/\1
/

67

6F

/

/

I
n
I--- I

16· and 14·Segment PLA Character Sets

5·59

-

5F

/\

~

I
I-

1\/1 4E 1\ I 4F I
I I I \1 I-

14·Segment PLA Patterns
Figure 2.

47

7F

I
I
-

I

I

Segmented Display Controller

10955
PACKAGE DIMENSIONS
40·PIN PLASTIC DIP

DIM

A

e

C
0
F

G
H

J
K

L

M
N

5-60

MILLIMETERS
MAX
MIN

5128
1372

5232
1422
508
051
152

355
036
102
254 esc
165
216
020
030
305
356
1524 esc
7·
10·
051
102

INCHES
MAX
MIN

2040
0540
0140

0014
0040
0100
0065
0008
0120
0600
7·
0020

2080
0560
0200
0020
0060

esc

0085
0012
0140

esc
10·
0040

SECTION 6
MICROCOMPUTER DEVELOPMENT SYSTEMS
Page
Product Family Overview ...................................................

6-2

RDC-1001/2 Multiple Target Development System (MTDS) . . . . . . . . . . . . . . . . . . . . . . ..

6-3

RDC-3101/2 Low Cost Emulator (LCE) ........................................

6-9

RDC-3XX Rockwell Design Center R6500/* Personality Set ....................... 6-14
RDC-502. RDC-504 and RDC-509 Rockwell Design Center
R6502-R65C02 Personality Set. ............................................ 6-18
RDC-2000 R6500 Cross Assembler for Intel Development System .................. 6-22
RDC-2005 R6500 Cross Assembler for Intel Personal Development System .......... Q-24
RDC-1020. RDC-1022 and RDC-1024 Rockwell Design Center
8K132K164K Target RAM Module ........................................... 6-26
RDC-1030 Multiple Target Development System PROM Programmer Module ......... 6-30

Software Preparation System
SPS-200 Software Preparation System Peripheral Connector Module ............... 6-36

6-1

MICROCOMPUTER DEVELOPMENT SYSTEMS
Low Cost, Flexible Systems Work With Multiple j.tCs

To support product development, Rockwell offers a range
of microcomputer development systems, each extremely
economical when compared on a cost/performance basis
with competitive development systems.
The new Low Cost Emulator (LCE) system links popular
personal computers (PCs) to your application. Code is
developed on the PC, downloaded to LCE, and it runs
in-circuit emulation in your application. LCE also accepts
downloads from other manufacturers development systems
via cross assemblers.
The AIM 65 microcomputer functions as an extremely low
cost, expandable, development system when used with the
Rockwell Software Preparation System kit. The Rockwell
Design Center (RDC) is an excellent, low cost, disk based
development system, allowing concurrent development of up
to four target R6500 and R65001* systems.
The RDC is an easy to use, powerful development system
for multi-chip and one-Chip R6500 systems. A full line of
support modules, macro assembler, link editor and high
level PLl65 language are also available. R6500/' personality

modules, additional RAM and a PROM programmer help
add versatility.
The RDC supports the growing trend to using single-chip
microcomputers as slaves with multi- or single-chip
microprocessor systems. The advantages of slaves include
both cost and technical saVings, such as eliminating some
complex timing relationships. With the RDC, up to four
different microprocessor personality modules can be
performing in-circuit-emulation under control of the system.
The RDC mainframe is constructed modularly, using the
proven RM Eurocard design, so it can be expanded readily,
as needed. The terminal unit includes CRT, disk drives, and
keyboard. Up to 1.28 Mbytes can be addressed on the two
96 TPI, double sided, double density, 5 V4-inch disk drives.
The RDC allows designers to economically and efficiently
develop multiple microcomputer systems, regardless of the
microcomputer device involved. Personality sets and target
RAM modules are available for all R6500 and R6500/'
configurations.

Rockwell Design Center Development System

Low Cost Emulator System

6-2

RDC-1001/2
Microcomputer Development Systems

'1'

Rockwell

RDC-1001/2
MULTIPLE TARGET DEVELOPMENT
SYSTEM (MTDS)

INTRODUCTION

, For users who already have an Intel Development System (IDS)
with mass storage program management, an R6500 crossassembler Is available. This allows the MTDS to function as a
satellite, providing a powerful debug system. The MTDS'is also
capable of receiving files from the Rockwell System 65
Microcomputer.

The Multiple Target Development System (MTDS) is a development system vertically integrated to support the entire R6500
family of microprocessors and .microcomputers. The MTDS
allows emulation, development, and software debugging of up
to four separate microprocessors and microcomputers concurrently, even if the four devices are different members of the
R6500 family. The MTDS is a disk-based system with two 96 TPI,
doubled-sided, double-density 5V4-inch floppy disk drives that
provide a storage capacity of up to 1.3M bytes of data
(formatted).

When used with the R65001* Microcomputer or R6502-R65C02
Microprocessor Personality Sets, the MTDS is a powerful emulat~n system for the complete family of Rockwell R65001* one-Chip
microcomputers or NMOS R6502 and CMOS R65C02 families
of microprocessors. The multiple target bus structure of the
MTDS allows the user to emulate four devices concurrently, and
at different speeds.

A unique bus structure provides a separate system bus and four
target busses which can operate at different speeds (up to
4 MHz) for the target bus which supports the emulator device.
Construction of the MTDS is modular based on the proven
RM 65 design using both single- and double-sized eurocards
and highly reliable DIN 41612 pin and socket connectors. The
double eurocards allow use of both the system bus and a target
bus which can operate at different speeds.
Featuring Softkey function keys, the MTDS eliminates the need
for an operator to learn extra key strokes and command structures. A command line of operating modes is displayed across
the bottom of the CRT screen so that the user need only push
the corresponding function key to command the MTDS to enter
the mode of operation desired.

SYSTEM FEATURES
Multiple Target Development System (MTDS)

• Modular construction based on proven RM 65 architecture
• Non-glare 12-inch CRT, green phosphor
•
•
•
•

• Detachable full ASCII intelligent keyboard
• Dual 96 TPI, double-sided, double-density 5V.-inch floppy disk
drives
.
.'
• Separate system bus and four independent target busses
• Separate system and target mer,nory map

•
•
•
•
•

• Two serial port~one for MTDS terminal interface-one for
host system download
'
• Two parallel ports-one for MTDS terminal interface-one
for external printer
• 64K byte RAM system memory
• Internal self-test panel for system troubleshooting

Self-contained, disk-based operating syStem
Softkey function access to menu-driven operational modes
Disk based Text Edit~r
Disk based R6500 Macro Assembler with all instruction
subsets
SYSGEN configurable to uset ehvironment
Automatic power-up initialization of system and configurations
Separate system and target memory map
Allows Real-time in-circuit emulation, up to 4 MHz
Five hardware breakpoints per target, 32-bits (16 addr, 8 data
and 8 control) wide with "don't care" bits

• External trigger input allows TTL level to cause a user
breakpoint
• Configurable as a satellite for an IDS host system or Rockwell
System 65

• Three separate CPUs for keyboard, CRT, and system control
• Designed for built-in PROM programmer option
• Requires only Personality Set for complete in-circuit
debugging

Document No. 29655N04
6-3

Data Sheet Order No. RDC04
Rev 3, October 1984

Multiple Target Development System

RDC-1001/2
PRODUCT OVERVIEW

FUNCTION DESCRIPTION'

The MTDS consists of three assemblies; the mainframe, a CRT
terminal with floppy disk drives and a full ASCII keyboard. The
mainframe contains the following components:

Major Components and Int'erfaces
The block diagram shows the architecture of the MTDSsystem
and identifies the relationship between the system bus and the
target busses. Although the block diagram shows only one
Target Interface, it represents the architecture of eactiof the
four target busses. The terminal keyboard interfaces with the
MTDS system through one of the RS-232C ports (J3 connected
to the ACIA module). The CRT interfaces with the MTDS system
through a parallel port (J3 connected to the MPI module). The
disk drives interface to the MTDS system through a separate
port (J2 connected to the FDC module). All other control functions of the MTDS system interface directly through the MTDS
system bus. Note that the Personality Set PMC module interfaces the MTDS system bus to the target bus.

•
•
•
•
•
•

The system bus and target/user busses
Power supply and system cooling fans
Two 32K Dynamic RAM modules for system memory
Single Soard Computer (SSC) module
Floppy Disk Controller (FDC) module
Asynchronous Commu(lications Interface Adapter (ACIA) module
with 2 channels for keyboard interface and user RS-232C
• Multi-function Peripheral Interface (MPI) module with two ports
for interface to the CRT terminal and to a printer
• 24-pin and 28-pin PROM sockets for optional PROM Programmer module

Bus Structure

The terminal assembly consists of a non-glare 12-inch, green
phosphor CRT, a video display controller module, and two
5%-inch floppy disk drives. The keyboard is intelligent for full
ASCII operation.

OPTIONAL R6500t" or R8502·R8SC02
PERSONALITY SET

r--- --- - - - - - ,
I
I
I
i

I
I '-----,--' L - - r - - - I
L ______ _

I

The MTDS system operates through a multiple bus structure-a
system bus and four target busses. The system bus contains
21 card slots to accommodate singe Eurocard modules or

r----,

II
I

EXTERNAL
PRINTER

II
I

L_,_.J
I

(TYPICAL 1 OF 4)
TARGET BUS

SY4"
FLOPPY
DISK
DRIVES

CRT/FOD·L---..J

ROC TERMINAL
PROM

SOCKETS '(2)

MTDS System Block Diagram

6-4

Multiple Target Development System

RDC·1001/2
double Eurocard modules. Double Eurocard modules plugged
into the system bus are common to the system bus and the target
bus. Double Eurocard modules (such as the R6500'" Personality
Set PMC module) are used for microcomputer emulation support. Single Eurocard module connectors on the system bus are
used to interface with MTDS microcomputer system modules
such as the 32K RAM(2), SBC, FDC, ACIA, and MPI.

(8K x 8, 32K x 8 or 64K x 8 depending upon the microcomputer to be emulated). These three target busses are color coded
(blue, red, and yellow) on the MTDS card cage for easy identification of the division of the target bus segments. The fourth
target bus consists of nine Euroconnectors, four of which will
accept double Eurocard modules and five of which will accept
single Eurocard modules.

The four target busses are segmented so that four separate
emulations can be controlled by the system concurrently. Three
of the target busses have four card slots each. Three of these
slots will accept double Eurocard modules, and the fourth will
accept a single Eurocard module. The double card slots are
intended for a Personality Module Controller (PMC) module and
future growth up to two Analyzer modules. The single card slot
is intended for plugging in a target (emulation) RAM module

A typical single target emulation configuration will consist of an
R6500'" or R6502-R65C02 Personality Set (comprising a PMC
module, Personality Pod, and Emulator Interface) and a target
RAM module, as a minimum. Since up to four fully configured
emulation systems can be supported concurrently, the MTDS
could be configured with any combination of four R6500'" or
R6502-R65C02 Personality Sets, and four target RAM modules
in addition to the ROC system control modules.

POWER SUPPLY ---~
- - - - TARGET BUSSES
_ _ _ _ SYSTEM BUS

J4
PRINTER

_ _ _ _ CARD CAGE

PORT

J3
PROM PROGRAMMER
SOCKETS

VIDEO-KEYBOARD
PORT

J1
RS232C

POWER SWITCH

PORT

MTDS MAINFRAME BACK VIEW

MTDS MAINFRAME FRONT VIEW

I

BLUE

TARGET
BUS 1

II

REO

TARGET
BUS 2

I

YELLOW
TARGET
BUS 3

I

WHITE

TARGET
BUS 4

I

~~"M~~ ~~~ ~ -~~~ ~~ ~~~

TARGET
}

~ m~ ~I~ ~ ~ ~ ~ ~I~ ~I~ ~ ~ ~I~ ~ ~ ~ I
}

MTOS CHASSIS CARD CAGE

MTDS Internal Layout and Card Cage Bus Structure

6-5

BUSSES

SYSTEM
BUS

RDC~t001/2

Multiple Target Development System

Operating Modes

Each Softkey prompt, when selected by the function key, invokes
a new set of Softkey prompts which further define the tasks to
be performed by the mode. As an example, if the LOCAL prompt
is selected, a new Softkey prompt menu displays:

The MTDS bootstrap ROM is initiated whenever the system is
powered-up. The bootstrap'program then loads the SYSGEN
data and system program from the system disk drive. When the
bootstrap is completed the CRT displays a Softkey menu for the
function keys on the keyboard. It is this menu that prompts the
user to select the mode of operation required. The Soft key
prompts displayed at this time are:
SATELLITE

LOCAL

SYSGEN

UTILITY,

DISK

HELP

COPY

HELP

-This mode displays information which briefly
describes the operational mode options available
in SATELLITE, LOCAL and SYSGEN modes. All
Softkey menus include a HELP which is always
located on the CRT screen directly over the far
right hand function key on the keyboard.

EXEC

HELP

BACKUP

FORMAT

DIR

INIT

HELP

This hierarchy continues until all parameters of the tasks of the
mode selected have been established. At any time during the
mode selection process the user has the option of calling back
the previous set of Softkey menu prompts by simply pushing
the - (minus) key.

-This mode provides the menus available to the
user from within the MTDS without requiring host
resources.
-This mode allows the user to modify the diskettestored system parameters on either a permanent
(until another power-up condition) or a temporary
basis.

FILE

Selecting DISK invokes a new menu which asks:

SATELLITE-This mode provides the menus available for
interfacing the MTDS as a satellite to the host
system (Intel ISIS II)

SYSGEN

HELP

If UTILITY is selected from this prompt, a new menu displays:

These Softkey prompts represent the primary modes of operation for the MTDS system. When the function key corresponding
to the CRT prompt location is pressed, one of the following
modes is selected:

LOCAL

DEBUG

The illustration shows the depth to which the command line
prompts guide the user thrqugh selecting the desired mode of
operation.

Software Command Overview
SYSGEN FUNCTIONS
BAUD
Select baud rate for host interface
WORD LEN
Select word length for host Interface
PARITY
Select parity for host interface
STOP BITS
Select stop bits for host interface
TARGET
Select the processor type emulating for each of the targets
PROTOTYPE Select areas to be mapped external for each target
PRINTER
Set up paging parameters for parallel printer
BEEPER
Turn on or off the BELL to indicate errors
DISPLAY
Show the current sysgen setup parameters
KEEP
Save the current sysgen parameters onto system disk
UTILITY FUNCTIONS
COPY
Copy diskettes
BACKUP
Copies disk files
FORMAT
Format new diskette
INITIALIZE
Initialize diskette directory
DIRECTORY List or Print diskette directory
LIST
List fole to printer, screen or disk file
DELETE
Remove disk file
RECOVER
Recover deleted disk file
RENAME
Rename disk file
EXEC
Executive a disk-based utility (Le. Text Editor. Macro
Assembler. etc.)
DOWNLOAD Transfer object file from host computer (System 65 or Intel ISIS)

6-6

DEBUG FUNCTIONS
DUMP
Show an image of user memory
(Hex and ASCII)
MODIFY
Allow changes to user memory
(Hex and ASCII)
DISASSM
Disassemble selected area of user
memory
LOAD
Load selected area of user memory with
object code file
SAVE
Save selected area of user memory to
disk file
VERIFY
Verify contents of user memory with
data in disk file
PROTECT
Set and clear areas to be write
protected
RUN
Execute at normal speed until any
breakpoint condition occurs
STEP
Execute user program displaYing every
instruction and register
RESET
Reset all debut parameters and
hardware
REGISTER
Show and accept changes to, load or
save emulator registers
BREAKPOINT Show and accept changes to the
breakpOint conditions

RDC-1001/2

Multiple Target Development System

INTERFACE

for proper installation. The MTDS Cable Interface figure shows
how these cables are routed in the system. The Self·Test Panel
interface ribbon cable is attached to the test panel and has a
connector on the other end that mates to the sec module 1/0
connector. The optional PROM programmer module connects
to the two PROM sockets through a single ribbon cable.

Interface between the MTDS system control modules and the
port connectors on the back panel are made through ribbon
cables. The ribbon cables are permanently attached to the port
connectors. The terminal interfaces to the MTDS system through
two cables with mating connectors on each end that are keyed

,----

1

I
I
I

-- ---_._-- .....

1 .... - - - - - - - - - - - - - ,

'---

MTDS MAINFRAME

NOTE:

PROM

SOCKETS

CD FRAME
RIBBON CABLES ARE PHYSICALLY ATTACHED TO MTDS MAIN·
CONNECTORS J1 THROUGH J4 AND HAVE CONNECTORS
ON THE OTHER END THAT MATE TO THE MODULES.

MTDS Mainframe Internal/External Ribbon Cable Connections

SPECIFICATIONS
MTDS Terminal
Parameter

MTDS Mainframe

CRT/FDD

Keyboard
3 in. (7.62 cm)
20 in. (50.60 cm)
8 in. (20.32 cm)

Dimensions
Height
Width
Depth

11 in. (27 94 cm)
20 in. (50.60 cm)
18 in. (45.72 em)

14 in. (35.56 em)
20 in. (SO.80 cm)
16 in. (40.64 em)

Weight

40 Ibs. (18 Kg)

42 Ibs. (19 Kg)

Electrical
AC Input Voltage
AC Frequency
Fuse Requirement
Environmelltal
Temperature
With/Disk Media
Humidity

105 to 125 (RDC·1001)
210 to 250 (RDC·1002)
47 to 63 Hz
3 A sic-blo (RDC·1001)
1.5 A slc-blo (RDC·1002)

105 to 125 (RDC·1001)
210 to 250 (RDC'1002)
47 to 63 Hz
3 A slo·bio (RDC·1001)
1.5 A slc-blo (RDC·1002)

59°F to 104°F (15°C to 40°C) operating
_4°F to 140°F (-20°C to 60°C) shipping
- 4°F to 122°F (- 20°C to 50°C) storage
20% to 80010 non·condensing operating'
1% to 95% non·condenslng shipping
1% to 95% non·condensing storage
NOTE: 'Disk media maximum wet bulb temperature 84.9°F (29.4°C)

6·7

6 Ibs. (2.7 Kg)

RDC-1001/2

Multiple Target Development System

ORDERING INFORMATION
Part Number
RDC·tOOl
RDC·t002
RDC·l020
RDC·t022
RDC·l024
RDC·l030
RDC-2000

Order Number(2)
RDC06
RDC09
RDCll
RDC12

PERSONALITY SETS
Personality Sets are available for the MTDS that allow emula·
tion, development, and software debugging of the complete
family of R6500/* Microcomputers and R6502·R65C02 Micro·
processors. The microcomputers and microprocessors
supported by these Personality Sets are:

Description
MTDS System (100 Vac)(')
MTDS System (220 Vac)(')
64K Target RAM Module
32K Target RAM Module
8K Target RAM Module
PROM Programmer Module
R6S00 Cross Assembler for Intel IDS

•
•
•
•
•
•
•

Document Title
ROC R6S00/' Personality Set Data Sheet
R6500 Cross Assembler for IDS Data
Sheet
ROC R6502·R65C02 Personality Set
Data Sheet
MTDS PROM Programmer Data Sheet

R6500/11P
R6500/12P
R65410
R65Cl02
R6504
R6512
R6500/13P

•
•
•
•
•
•
•

R6500/41P
R65010
R65C112
R6505
R6513
R6500/42P
R6500/43P

•
•
•
•
•
•
•

R6502
R6506
R6514
R6500/1P
R65110
R65C02
R6503

• R6507
• R6515
• R6500/15P

• R6500/160

For complete information on ordering any particular Personality
Set or groups of Personality Sets, refer to the RDC R6500/'
Personality Set Data Sheet, Order Number RDC06, or RDC
R6502·R65C02 Personality Set Data Sheet, Order Number
RDCll.

Notes:
(1) Both system configurations are shipped with the following
components:
• MTDS Mainframe
• MTDS Terminal with 12" CRT and Dual 5%" Floppy Disk
Drives and detached Keyboard
• Six System Control modules-ACIA, FDC, SBC, MPI,
and two 32K DRAM
• All Required Interface Cables
• Software Package (Utilities, Text Editor, Macro
Assembler)
• Documentation Package
(2) Documents proVide further Information about the MTDS system.

I.

6-8

RDC·3101/2
Microcomputer Development Systems

'1'

Rockwell

RDC-3101/2
LOW COST EMULATOR (LCE)

INTRODUCTION

FEATURES

The Low Cost Emulator (LCE) is a development system vertically
integrated to support the entire R6500 family of microprocessors
and microcomputers. The LCE allows emulation, development,
and software debugging of microprocessors and microcomputers of the R6500 family.

• Compact desktop modular design construction allows future
options
• SYSGEN configurable to user environment
• Front panel reset switch with 'warm' option to maintain
SYSGEN parameters

A unique bus structure provides a separate system bus and
target bus which can operate at different speeds (up to 4 MHz)
for the target bus which supports the emulator device. Construction of the LCE is modular based on the proven RM 65 design
using both single- and double-sized Eurocards and highly reliable
DIN 41612 pin and socket connectors. Additional slots allow
expansion.

• Two serial ports-one for terminal interface-one for host
system download or other peripheral devices
• Serial port options for eight baud rates 110 to 19.2K with
choice of 7- or a-bit word length
• Software allows choice of any baud rate, word length or parity
options with full handshake signal support from the R6551
ACIA device

Featuring Softkey function keys, the LCE eliminates the need
for an operator to learn extra key strokes and com mand structures. A command line of operating modes is displayed across
the bottom of the CRT screen so that the user need only push
the corresponding function key to command the LCE to enter
the mode of operation desired.

• Target emulation of any R6500 multichip or single-chip
MPU device
• 24K-byte ROM includes system, debug and self-test firmware

For users who already have an Intel development system with
mass storage program management, an R6500 cross-assembler
is available. This allows the LCE to function as a satellite, providing a powerful debug system. The LCE is also capable of
receiving files from the Rockwell System 65 Microcomputer.

• 10K-byte RAM with aK bytes for symbol table generation
• Internal default switchlLED panel with software for system
troubleshooting
• Self-contained, ROM-based operating system

When used with the R65001' Microcomputer or R6502-R65C02
Microprocessor Personality Sets, the LCE is a powerful emulation system for the complete family of Rockwell R65001' oneChip microcomputers or NMOS R6502 and CMOS R65C02
families of microprocessors.

• Softkey function ac-:ess to menu-driven operational modes
• R6500 Assembler with all instruction subsets
• Separate system bus and target bus with independent
processor
• Allows real-time in-circuit emulation, up to 4 MHz
• Five hardware breakpoints, 32-bits wide (16 address, a data
a control) with "don't care" mask for each bit
• Two hardware match pOints allow execution to continue with
external TTL level trigger signals
• External trigger input allows TTL trigger to cause a user
breakpoint
• Configurable as a satellite for any host system including the
Rockwell System 65
• Designed for add-on PROM programmer option
• Requires only Personality Set and user supplied terminal for
full operation

Low Cost Emulator (LCE)

Document No. 29655N17
6-9

Data Sheet Order No. RDC17
October 1984

Low Cost Emulator

RDC-3101/2
PRODUCT OVERVIEW

Bus Structure
The LCE system operates through a multiple bus structure-a
system bus and target bus. The system bus contain~ 4 card slots
to accommodate single eurocard modules' and 2 card slots for
double eurocard modules. Double eurocard modules plugged
into the system bus are common to the system bus and the target
bus. Double eurocard modules (such. as the R6500/' Personality
Set PMC module) are used for microcomputer emulation support. Single eurocard module connectors on the system bus are
used to interface with LCE microcomputer system modules such
as the universal RAM, SBC, and ACIA.

The LCE mainframe contains the following components:
• The card cage/backplane ,:",ith system bus and target bus
•

Power supply and system cooling fan

• Single Board Computer (SBG) module (2K RAM, 8K ROM)
• Universal memory module for system memory (8K RAM, 16K
ROM)
• Asynchronous Communications Interface Adapter (ACIA)
module with 2 channels preconfigured for terminal and host
interfaces

MAJOR COMPONENTS AND INTERFACES

The target bus contains two single card slots and two double
slots shared with the system bus. The double card slots are
intended for a Personality Module Controller (PM C) module and
future growth up to an Analyzer module. The single card slot
is intended for plugging in a target emulation RAM module (8K
x 8, 32K x 8, or 64K x 8 depending upon the microcomputer
to be emulated). The target bus is color coded red on the LCE
card cage for easy identification of the division of the target bus
segment.

The block diagram shows the architecture of the LCE system
and identifies the relationship between the system bus and the
target busses,

A typical LCE configuration consists of an R6500/' or
R6502-R65C02 Personality Set, Personality Pod, and Emulator
Interface) and a target RAM module.

• 28-pin PROM socket for optional PROM Programmer module
•

Personality Set Module Controller (PMC) with cables to connect a R6500/' or R6502-R65C02 Personality Set

FUNCTIONAL DESCRIPTION

r-------------~==============================================~========~==~~RESET
UNIVERSAL MEMORY MODULE

SBC MODULE
R6502
CPU

ROM 1
8K BYTES
RAM
2K BYTES

PORT 1
TERMINAL
RS-232C

SYSTEM
RAM
8K BYTES

SYSTEM
ROM
16K BYTES

PORT 2
HOST
RS-232C

PERSONALITY
MODULE
. CONTROllER

DEFAULT
SWITCHES
& lEDS

!OPTIONAL . ,
18K, 32K, 64K :
I TARGET
I

!B~

__ -'

r-

-..,

FUTURE
I

OP~ON

I
I

L_'_ _ -'

lCE ENCLOSURE

LeE System Block Diagram

6-10

rFUTURE OPTION
I PROM
I PROGRAMMER I
I MODULE
I

PROM
SOCKET

Low Cost Emulator

RDC·3101/2
Operating Modes

TERMINAL - This mode echoes each character entered from
the console device to the host system.

The LCE bootstrap ROM is initiated whenever the system is
powered-up. The program then loads the SYSGEN data and
system program from the system ROM. When the initialization
is completed the console device displays a Softkey menu. It is
this menu that prompts the user to select the mode of op~a­
tion required. The Softkey prompts displayed at this time are:
1:SYSGEN
5:TERMINAL

2:MEMORY
6:PROM

3:EMULATE
7:TRACE

4:SYMBOL
8:SPEED

These Softkey prompts represent the primary modes of operation for the LCE system. When the function key corresponding
to the prompt location is pressed, one of the following modes
is selected:
SYSGEN

- This mode selects the command options for the
optional PROM Programmer module.

TRACE

- This mode selects the command options for the
optional TRACE module.

SPEED

- This mode selects the speed of dump and disassemble data being displayed to the console.

Each Softkey prompt, when selected by the number key, invokes
a new set of Softkey prompts which further define the tasks to
be performed by the mode. As an example, if the SYSGEN
prompt is selected, a new Softkey prompt menu displays:

- This mode allows the user to modify the ROMstored system parameters on either a permanent
(until another power-up condition) or a temporary
basis.

1:PORT1
2:PORT2
4:PROTECT 5:BEEPER

MEMORY - This mode allows the user to display or modify
the contents of Target as well as Prototype
memory.

3:TARGET
6:DISPLAY

1:PROTECT 2:UNPROTECT 3:CLEARALL 4:DISPLAY
This hierarchy continued until all parameters of the tasks of the
mode selected have been established. At any time during the
mode selection process the user has the option of calling back
the previous set of Softkey menu prompts by simply pushing
the 0 or - (minus) key.

- This mode contains the functions which control
the generation and use of symbol tables as it
relates to MEMORY functions.

POWER SUPPLY

CARD CAGE

TARGET
BUS

.. : ........

:.:'

7:EXIT

If PROTECT is selected from this prompt, a new menu displays:

EMULATE - This mode provides all the functions for con'
trolling run-time characteristics and emulation.
SYMBOL

PROM

....... .

t . ::::~ .:.:.';:.;:<;~::;\'. >.;'~
LCE CHASIS CARD CAGE

LCE Internal Layout and Card Cage Bus Structure

6-11

SYSTEM
BUS

Low Cost Ernulator

RDC-3101/2
Software Command Overview
SYSGEN FUNCTIONS

BAUD
WORD LEN
DELAY
FORMAT
START CHAR
STOP CHAR
SYSTEM
TARGET
PROTOTYPE
PROTECT
BEEPER
DISPLAY
EXIT

Select baud rate arid parity options
Select serial word length
Set delay after linefeed between 0 to !;l9 mS
Set record format for data files (;,:, or Block)
Set start of file marker character
Set end of file marker character
Select the system console port
Select the processor type for emulation
Select areas to mapped external of LCE target memory
Set and clear areas to be write protecteq
Turn on or off the BELL to indicate errors
Show the current sysgen setup parameters
Accept the current sysgen parameters and exit to primary menu

DEBUG 'FUNCTIONS

DUMP
MODIFY
ASSEMBLER
DISASSM
LOAD
SAVE
VERIFY
STEP
RUN
SNAPSHOT
MATCH
RESET
BREAK

Show a screen image at user memory (Hex and ASCII)
Show user memory and allow changes (Hex or ASCII)
Assemble op code text into user memory
Dissassemble op code image of user memory
Load a file image into user memory
Save a file image of user memory
Verify a file image with user memory
Execute user program displaying every instruction <
LJ6- -

U==_--Ll

=-

><

-~2~-11-

~~
I

......,rl-..,..,I-+-+-I-------!
1:1111

PMC BOARD
J6
PMC MODULE CONNECTS

40 PIN RIBBON
CABLE

J5

___

--,
I
I

g~NNECTOR

I

PROTOTYPE

I

OR

:

CONNECT
TO 28 PIN
DEVICE
CONNECTOR

I

I

~_ !~!?T~T~~_J

6-WIRE
POWER
CABLE

28 PIN
RIBBON
CABLE

EMULATION POD
BOARD 2

L---,__ TO SYSTEM BUS
AND A TARGET BUS

MTDS OR LCE
MAINFRAME

System Interconnection
Execution Functions

EXECUTION COMMAND SUMMARY

Step through a user program displaying instructions and
registers
Run through a program at full execullOn speed stopping at
at breakpOints
Run at full speed With breakpoint signals on Sync
connectors (LCE)
Reset the debugger
Examine or alter the registers
Set or modify hardware breakpOints

The R6502-R65C02 Personality Set is designed to allow R650X,
R651X or R65XXX devices to execute independent of the MTDS
or LCE. Thus, while the emulator is executing code, the CPU
is still in operation. This allows certain functions to be performed
by the MTDS or LCE CPU without disturbing the execution of
the emulator device.
The R65C02 Personality Set hardware supports the LCE and
MTDS debug software in the following commands:
Memory Functions
Dump memory In Hex and ACSII format
Modify or alter selected memory locations In Hex or ASCII
Examine/modify RAM and I/O one byte at a time (LCE)
Assemble or code text into text memory (LCE)
Disassemble or code Image of user memory
Load an object code file Into user memory
Save an object file from user memory
Verify an object file with memory
Write protect memory blocks
Select memory areas to be prototype or target enVIronment

6-19

ROC R6S02-R6SC02 Personality Set

ROC-SOX
CONFIGURATIONS

R6502-R65C02 Personality Sets and Memory

The RDC Personality Sets for the R6502-R65C02 Microprocessors, shown in the chart below, include one Personality Module
Controller (PM C), two Personality Emulator Pod Modules, one
Emulator Device set, an interconnect cable set, and the required
software and support documentatio"n. In the LCE configuration,
the PMC and interconnect cables are already installed in the
LCE as part of the system package.

Part Number

Description

RDC-502
ROC-509

R6502-R65C02 Personality Set, 1-2 MHz
R6502-R65C02 Personality Set, 1-2 MHz
(LCE only)
64K RAM Target Memory, 1-3 MHz
32K RAM Target Memory 1-3 MHz
8K RAM Target Memory, 1-3 MHz only

ROC-1020
ROC-1022
RDC-1024

PMC TO EPM2
INTERCONNECT' •
CABLE
(50 PIN)
(MTDS

PMC TO EPM1
INTERCONNECT
CABLE
(60 PIN)
(MTDS ONLY)

EPM1 TO EPM2
60-PIN
INTERCONNECT
CABLE

28-PIN
PROTOTYPE-TO-POD
INTERFACE CABLE

40-PIN/
PROTOTYPE-TO-POD
INTERFACE CABLE

ONE INCLUDED
WITH EACH SET

Typical R6502-R65C02 Personality Set Hardware Components

6-20

ROC-50X

ROC R6502-R65C02 Personality Set
R6502-R65C02 Personality Set Component List

QUANTITY

ITEM

DESCRIPTION

1

PMC Module

Controller module that plugs into the MTDS and LCE Mainframe. (MTDS only,
PMC is installed in LCE when system IS shipped.)

1

Emulator Pod
Module Assembly

Pod that contains EPM-1 and EPM-2, a short ribbon cable, a six-wire power cable,
and the R6502 Emulator Device.

1

Emulator Package

Package contains the R6512, R65C02, R65C102 and R65C112 Emulator devices
and 5 jumper headers for the 28-pin processors.

2

PMC to Pod
Interiace Ribbon Cables
(Long Length)

One cable with 60-pm connector on each end with one cable with a SO-pin connector on each end. (MTDS only, cables installed m LeE prior to shipment).

2

Prototype-to-Pod
Interiace Cables
(Medium Length)

One of two pOSSible configurations:
a. One ribbon cable with 40-pin connectors on each end. Used for emulating the
R6502, R6512, R65C02, R65C102 or R65C112.·
b. One cable with a 28-pin connector on each end. Used for emulating the R6503,
R6504, R6505, R6506, R6507, R6513, R6514 or R6515.

6-21

RDC·2000
Microcomputer Delle/opment Systems

'1'

Rockwell

RDC-2000
R6S00 CROSS ASSEMBLER
FOR INTEL DEVELOPMENT SYSTEM

CROSS ASSEMBLY

FEATURES

The R6500 Cross Assembler provides the user with the capability
of developing assembly language programs on the Intel Development System and downloading these programs to the Multiple
Target Development System (MTDS) or Target Emulator
Workstation (lEW) for debugging and in-circuit operation.

• Intel Development System Host
• Supports Rockwell's a-bit CPU devices:
-R6500 NMOS microprocessor family
-R6500/' NMOS microcomputer family
-R65COO CMOS microprocessor family
• Symbolic notation-operands and labels
• Interactive assembler operation
• Operator selected object code output devices
-Display/printer
-Printer
-Floppy Disk
-Download to MTDS or TEW
• Operator selected assembly/error listing output
-Display/Printer
-Printer
-Floppy Disk

The process of translating microprocessor instructions for a computer program written in symbolic form to executable machine
instructions is called an assembly, and the computer program
that performs this translation is called an assembler. Assemblers
that run on a host computer different from the target computer
that the generated machine code is to operate in are called cross
assemblers. One assembly language statement usually translates into a single processor instruction. Each statement consists of a label (if required), an arithmetic operator (if required)
and an optional comment. Constants are comprising one or more
bytes of memory are generated from data statements while one
or more bytes of memory are assigned to variables. This cross
assembler is a symbolic assembler that allows the programmer
to represent memory locations and numeric values with names
or symbols.

• Assembler directives
• Symbolic cross-reference
• Communications support-downloading of object code

PRODUCT OVERVIEW
The R6500 Cross Assembler for the Intel Development System
allows users who have access to such a system and are
accustomed to its text editor (ISIS CREDIT) to enter and edit
source code, assemble the program and save both the source
and object code on floppy disk. The object code can then be
loaded into a MTDS or TEW for program debugging and in-circuit
validation using an R6500, R65001* or R65COO Personality Set.
Up to four personality sets can be installed in one MTDS or TEW
main frame to maximize the utility of one Intel Development
System and MTDS or TEW. The object code can also be programmed into PROM/ROM for execution by an R6500 NMOS
or R65COO CMOS microprocessor or masked in R6500/' NMOS
one-Chip microcomputer ROM for execution.

ORDERING INFORMATION
Part No.
RDC-2000
Order No.
RDC02

Description
R6500 Cross Assembler for Intel Development
System Disk (8" ISIS II compatible disk)
Description
R6500 Cross Assembler for Intel Development
System User's Manual (included with RDC-2000)

SYSTEM REQUIREMENTS
The Intel Development System must provide 64K bytes of
memory and the Dual-Density Drive option to support the R6500
Cross Assembler. 32K bytes are then available for application
source code. The other 32K bytes contain the ISIS system (14K)
and the cross assembler (18K).

The disk-based R6500 cross assembler is a two-pass symbolic
assembler which produces absolute 6500 object code. It performs symbol (1 - 6 characters) definition, syntax checking,
assembly/symbol table listings and cross reference generation
for effective program development. Assembler operation is
automatic once started.
The assembler outputs to the console the pass it is currently
performing and a dot for every 161ines of source code assembled.
This enables viewing of the assembly process and observation
of detected errors. List (.LST), object (.OBJ), and symbol (.SYM)
files are automatically generated with the source name assigned
as the header and the particular extension added.

Document No. 29655N09
6-22

Data Sheet Order No. RDC09
Rev. 1, August 1984

R6S00 Cross Assembler for Intel Development System

RDC·2000
Assembler Directives
Assembly Listing Control
.TTL
Title
.PAGE
Page
.L1NE
Page Length

.WIDTH
.SKIP

Data Storage
.BYTE
.wORD
.DBYTE
.SBYlE

Line Length
Skip

Equate

Source F"e Control
End of Assembly
.END
.MOD
Assembly Type

Assign value to symbol

Error Codes
Pass 1
1 OPERAND VALUE IS INVALID OR GT HEX FFF
2 OPERAND VALUE IS GREATER THAN HEX FFFF
3 INCORRECT ADDRESSING MODE
4 SYMBOL NOT PREVIOUSLY DEFINED
5 NO OPERAND
6 ASCII STRING NOT PROPERLY ENCLOSED
7 MISSING .END STATEMENT
8 UNDEFINED ASSEMBLER DIRECTIVE
9 IMPROPER EQUATE FORMAT
10 UNRECOGNIZABLE ASTERISK DEFINITION
11 INDIRECT ADDRESSING OFF OF ZERO PAGE
12 INCORRECT FORM OF INDIRECT ADDRESSING, MISSING Y
13 INCORRECT FORM OF INDEX ADDRESSING, MISSING X
14 OPERAND MUST BE ON ZERO PAGE (OO-$FF)
15 ILLEGAL INSTRUCTION FOR THIS ASSEMBLER

Pass 2
1 .MOD DIRECTIVE MUST BE FIRST LINE ON LISTING
2 INCORRECT FORMAT OF INDEX ADDRESSING, MISSING X
OR Y
3 MISSING RIGHT PARENTHESIS
4 LABEL LONGER THAN 6 CHARACTERS
5 LABEL IS DEFINED MORE THAN ONCE
6 RELATIVE BRANCH IS OUT OF RANGE
7 ILLEGAL OR MISSING OPCODE
8 OPERAND LABEL IS DEFINED MORE THAN ONCE
9 SYMBOL TABLE FULL
10 MISSING LABEL FOR EQUATE
11 OPERAND LABEL GREATER THAN 6 CHARACTERS LONG
12 .MOD VALUE IS INCORRECT FOR THIS ASSEMBLER
13 OPERAND NOT BETWEEN 0-7
14 SYMBOL HAS ILLEGAL CHARACTER OR IS GREATER THAN
ZIJFF

Operators
Prefix Character
(none)
$
@

%

Initialize byte memory location
Generate 16-bit address
Generate 16-bit data word
Initialize ACSII string

Constants (Prefix)
10
16
8
2

Operator

Base
(Decimal)
(Hexadecimal)
(Octal)
(Binary)

+
>
<

6·23

Operation
Addition
Subtraction
High-Byte Selection
Low-Byte Selection

RDC-2005
Microcomputer Development Systems

'1'

Rockwell

RDC-2005
R6500 CROSS ASSEMBLER FOR
INTEL PERSONAL DEVELOPMENT SYSTEM

CROSS ASSEMBLY

FEATURES

The R6500 Cross Assembler provides the user with the capability
of developing assembly language programs on the Intel Personal
Development System (PDS) and downloading these programs
to the Low Cost Emulator (LCE) for debugging and in-circuit
operation.

• Intel Personal Development System Host
• Supports Rockwell's 8-bit CPU devices:
-R6500 NMOS microprocessor family
-R6500/' NMOS microcomputer family
-R65COO CMOS microprocessor family
• Symbolic notation-operands and labels
• Interactive assembler operation
• Operator selected object code output devices
-Display/printer
-Printer
-Floppy Disk
-Download to LCE
• Operator selected assembly/error listing output
-Display/Printer
-Floppy Disk

The process of translating microprocessor instructions for a computer program written in symbolic form to executable machine
instructions is called an assembly, and the computer program
that performs this translation is called an assembler. Assemblers
that run on a host computer different from the target computer
that the generated machine code is to operate in are called cross
assemblers. One assembly language statement usually translates into a single processor instruction. Each statement consists of a label (if required), an arithmetic operator (if required)
and an optional comment. Constants are comprising one or more
bytes of memory are generated from data statements while one
or more bytes of memory are assigned to variables. This cross
assembler is a symbolic assembler that allows the programmer
to represent memory locations and numeric values With names
or symbols.

• Assembler directives
• Symbolic cross-reference
• Communications support-downloading of object code

PRODUCT OVERVIEW
ORDERING INFORMATION

The R6500 Cross Assembler for the Intel Personal Development
System allows users who have access to such a system and
are accustomed to its text editor (ISIS CREDIT) to enter and edit
source code, assemble the program and save both the source
and object code on floppy disk. The object code can then be
loaded into a LCE for program debugging and in-circuit validation using an R6500, R65001' or R65COO Personality Set. The
object code can also be programmed into PROM/ROM for
execution by an R6500 NMOS or R65COO CMOS microprocessor or masked in R6500/' NMOS one-chip microcomputer
ROM for execution.

Part No.
RDC-2005

Order No.
RDC02

Description
R6500 Cross Assembler for Intel Personal
Development System Disk
(5-1/4" ISIS II compatible disk)
Description
R6500 Cross Assembler for Intel Personal
Development System User's Manual
(Included With RDC-2005)

The disk-based R6500 cross assembler IS a two-pass symbolic
assembler which produces absolute 6500 object code. It performs symbol (1-6 characters) definition, syntax checking,
assembly/symbol table listings and cross reference generation
for effective program development. Assembler operation is
automatic once started.
The assembler outputs to the console the pass It IS currently
performing and a dotfor every 16 lines of source code assembled.
This enables viewing of the assembly process and observation
of detected errors. List (.LST), object (.OBJ), and symbol (.SYM)
files are automatically generated with the source name assigned
as the header and the particular extension added.

Document No. 29655N23
6-24

Data Sheet Order No. RDC23
Rev. 1, October, 1984

R6500 Cross Assembler for Intel Personal Development System

RDC·2005

Assembler Directives
Assembly Listing Control
.TIL
Title
.PAGE
Page
LI NE
Page Length

WIDTH
.sKIP

Data Storage
.BYTE
.WORD
DBYTE
SBYTE

Line Length
Skip

Equate

Source File Control
END
End of Assembly
.MOD
Assembly Type

Assign value to symbol

Error Codes
Pass 1
1 OPERAND VALUE IS INVALID OR GT HEX FFF
2 OPERAND VALUE IS GREATER THAN HEX FFFF
3 INCORRECT ADDRESSING MODE
4 SYMBOL NOT PREVIOUSLY DEFINED
5 NO OPERAND
6 ASCII STRING NOT PROPERLY ENCLOSED
7 MISSING END STATEMENT
8 UNDEFINED ASSEMBLER DIRECTIVE
9 IMPROPER EQUATE FORMAT
10 UNRECOGNIZABLE ASTERISK DEFINITION
11 INDIRECT ADDRESSING OFF OF ZERO PAGE
12 INCORRECT FORM OF INDIRECT ADDRESSING, MISSING Y
13 INCORRECT FORM OF INDEX ADDRESSING, MISSING X
14 OPERAND MUST BE ON ZERO PAGE (OO-$FF)
15 ILLEGAL INSTRUCTION FOR THIS ASSEMBLER

Pass 2
1 MOD DIRECTIVE MUST BE FIRST LINE ON LISTING
2 INCORRECT FORMAT OF INDEX ADDRESSING, MISSING X
OR Y
3 MISSING RIGHT PARENTHESIS
4 LABEL LONGER THAN 6 CHARACTERS
5 LABEL IS DEFINED MORE THAN ONCE
6 RELATIVE BRANCH IS OUT OF RANGE
7 ILLEGAL OR MISSING OPCODE
8 OPERAND LABEL IS DEFINED MORE THAN ONCE
9 SYMBOL TABLE FULL
10 MISSING LABEL FOR EQUATE
11 OPERAND LABEL GREATER THAN 6 CHARACTERS LONG
12 MOD VALUE IS INCORRECT FOR THIS ASSEMBLER
13 OPERAND NOT BETWEEN 0-7
14 SYMBOL HAS ILLEGAL CHARACTER OR IS GREATER THAN
ZIJFF

Constants (Prefix)

Operators
Prefix Character
(none)

$
@

%

Imtialize byte memory location
Generate 16-bit address
Generate 16-bit data word
Initialize ACSII string

10
16
8
2

Base
(Decimal)
(Hexadecimal)
(Octal)
(Binary)

Operator

+

>
<

6-25

Operation
Addition
Subtraction
High-Byte Selection
Low-Byte Selection

RDC·102X
Microcomputer Development Systems

'1'

. Rockwell

RDC·1020, RDC-1022 AND RDC·1024
ROCKWELL DESIGN CENTER (ROC)
8K132K164K TARGET RAM MODULE

INTRODUCTION

FEATURES

The 8K/32K/64K Target RAM Module is one of the hardware
options available for the Rockwell Design Center Family of
development systems.

• In the high speed mode, supports Multiple Target Development (MTDS) and Low Cost Emulator (LCE) 3 MHz RAM
operations
• In the universal memory mode, supports 2K, 4K, 8K, and 16K
byte-wide memory devices for up to 128K bytes of memory

The Target RAM Module supports memory operations In conjunction with the R65001" and R6502-R65C02 Personality Sets
used on both the Multiple Target Development System (MTDS)
and Low Cost Emulator (LCE). The module In its 8K byte configuration also supports the ROM and RAM area for the TEW
operating system.

• In the high speed mode, supports 8K devices for up to
64K bytes of memory (refer to Devices Supported for
part numbers)
• On-board header and shunt configure the module into a 2K
to 128K memory space
• Each half (four device sockets) Independently conflgurable
In the universal memory mode
• On-board memory bank select switches assign each half of
the module to either one or both of two 64K memory banks
• On-board ROM select switches serve as write-protect
switches for each half of the memory in universal memory
mode
• Compact size-100 mm x 160 mm (approximately 3.9 in.
x 6.3 in.)
• Operates from a single + 5V power source
• Fully assembled (except for user-supplied memory devices),
tested and warranted

OVERVIEW
Two major capabilities are provided in the Target RAM Module:
the flexibility of using 2K, 4K, 8K, or 16K memory devices on
the module, and use of the memory in either a high-speed mode
or a universal memory mode. Typical data-transfer rates are up
to 3 MHz (to support the MTDS and LCE) in the high speed mode
and 1- to 2-MHz in the universal memory mode. Rates are
dependent both on memory devices used and system configuration. Memory devices that can be used with the module are
RAMs, ROMs, EPROMs, and EEPROMs.

ORDERING INFORMATION

8K/32K/64K Target RAM Module

Document No. 29655N18
6-26

Part No.

Description

RDC-1020
RDC-1022
RDC-1024

64K RAM Module (1 to 3 MHz)
32K RAM Module (1 to 3 MHz)
8K RAM Module (1 to 3 MHz)

Data Sheet Order No. RDC18
Rev _ 1 October 1984

Target RAM Module

RDC·102X
FUNCTIONAL DESCRIPTION

Device Select A consists of jumpers E3, E4, and E7 through El 0
determine the particular type memory device (2K, 4K, 8K, or 16K)
installed in the Memory A sockets. Similarly, Device Select B
jumpers E5, E6, and Ell through E14 determine memory device
types in Memory B.

Data Bus Transceivers buffer and invert data signals BDOI
through BD7/. Data signals from the RM 65 Bus pass through
the bidirectional transceivers into the module during a write
operation and out from the module through the transceivers to
the RM 65 Bus during a read operation. Data in is inverted for
use in the module, and data out (from the module) is inverted
for use on the RM 65 Bu~. Transfers occur when any of the chipselect signals and the 02 clock pulse are in the active states
concurrently. Direction of data flow either into or out of the
module is controlled by the Rm signal state.

Memory A Decoder is a programmable array logic (PAL) device
internally configured to decode a combination of input signals
and generate one output (chip-select) signal. Memory
Decoders A and B are used only when the module is being
operated in the universal memory mode. Both decoders operate
in the same manner, but only one is used at a time. Thus, when
Memory A is addressed, Memory Decoder A is used, and
Memory Decoder B when Memory B is addressed.

Address and Control Buffer logic consists of inverters that buffer
address signals BAOI through BA131 and the read/write signal
BRIWI. These signals are converted to positive signals BAO
through BA13 and BRIW for use within the module.

DEVICES SUPPORTED
In the universal memory mode, the following is a partial list of
devices supported:

Bank Address Select logic is controlled by the state of the
BADRlsignal, which functions as a seventeenth address bit. The
state of the BADRlsignal indicates which of the two 65K memory
banks is addressed. In the high speed memory mode, the
module can be configured to operate in either one or both 65K
memory banks. In the universal memory mode, each half of the
memory is configurable to either one or both 65K memory banks.

16K of the following 2K devices:
R2316
2716
2516
2016
5516
6116
R5213/2816
X2816

Module Active logic is enabled when any chip-select signal is
enabled. Thus, when any memory device in either Memory A
or Memory B is enabled by a chip-select signal, the BACT!, or
Module Active, signal is in the ,active state.
Address signals BA13/, BA14/, and BA15/, in conjunction with
BO, are decoded by a 3:8 decoder to enable one of eight possible
outputs. Each output signal in a low state indicates an 8K
address boundary signal. Thus, the 8K address boundaries are
$0000, $2000, $4000, ... $EOOO. Each of these signals is used
as a memory chip-select signal during operation of the memory
in the high-speed mode and as a 2K, 4K, 8K, and 16K decoder
enabling signal in the universal memory mode.

ROM-Rockwell
EPROM-Intel
EPROM-TI
RAM-Toshiba
RAM-Toshiba
RAM-Hitachi
EEPROM-Rockwell
EEROM-XICOR

32K of the following 4K devices:
R2332
2732A
2532 (350 ns)

ROM-Rockwell
ROM-Intel
ROM-TI

64K of the following 8K devices:

By connecting a pin on the Address Header to a specific output
(chip select) pin from the 8K Decoder, that 8K address boundary
signal is connected to one specific memory device (in one of
the eight memory device sockets) only in high speed mode.

R2364A, R2364B
68A764
68766
2764
5564
6264
8464

The module can be used either as a high speed memory or as
a universal memory. The removable 16-pin, 8-position shunt is
placed either in the High Speed Option Shunt socket for high
speed memory operation, or in the Universal Memory Option
Shunt socket for universal memory operation. In the high speed
mode, Memory A Decoder and Memory B Decoder are not used,
and the address (chip-select) signal from the Address Header
is applied directly to the applicable Memory A or Memory B
devices. As a result, decoding time is saved.

ROM-Rockwell
EPROM-Motorola
EPROM-Motorola
EPROM-Intel
RAM-Toshiba
RAM-Hitachi
RAM-Fujitsu

128K of the following 16K devices:
R23128
27128

ROM-Rockwell
EPROM-Intel

In the high speed mode, the following is a partial list of devices
supported:

Memory A consists of 2K, 4K, 8K, or 16K memory devices
installed in the four sockets assigned as Memory A. Memory B
also consists of memory devices located in four sockets
designated as Memory B. Thus, the capacity of Memory A or
Memory B is dependent on the capacity of the memory devices
installed in each socket. Each of the two groups of four sockets
can be configured with jumpers to accept one of the four types
(2K, 4K, 8K, or 16K) of memory devices. Each memory device
in the memory sockets in Memory A or Memory B must have
the same capacity.

64K of the following 8K devices:
R2364A, R2364B
68A764
68766
2764
5564
6264
8464

6-27

ROM-Rockwell
EPROM-Motorola
EPROM-Motorola
EPROM-Intel (TEW)
RAM-Toshiba
RAM-Hitachi (MTDS and TEW)
RAM-Fujitsu

Target RAM Module

RDC-102X
RM 65 Bus Pin Assignments
Bottom (Solder Side)
Signal
Mnemonic

Pin

la
2a
3a
4a
5a
6a
7a
8a
9a
lOa
Ila
12a
13a
14a
15a
16a
17a
18a
19a
20a
21a
22a
23a
24a
25a
26a
27a
28a
29a
30a
31a
32a

GND
BADRI
GND
BAI3/
BAli/
BA1O/
BA8/
GND
BA5/
BA3/
BA2/
BAO/
GND
BSO
BRDY
+12V/+V
GND
BDMT/
BRiWi
GND
BIRO/
B~2/
B~2

BD7/
GND
BD4/
BD2/
BDI/
+5V

Top (Component Side)

Signal Name

Pin

Ground
Buffered Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit,8
Ground
Buffered Address Bit 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
"Buffered Set Overflow
"Buffered Ready
"User Spare 1
'+12 Vdc/+V
Ground Line
"Buffered DMA Terminate
'User Spare 3
Buffered Read/Write "Not"
'System Spare
Ground
'Buffered Interrupt Request
Buffered Phase 2 "Not" Clock
Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Bufferea Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+5 Vdc

Ic
2c
3c
4c
5c
6c
7c
8c
9c
10c
Ilc
12c
13c
14c
15c
t6c
17c
18c
19c
20c
21c
22c
23c
24c
25c
28c
27c
28c
29c
30c
31c
32c

Signal
Mnemonic

+5V
BAI5/
BAI4/
BAI21
GND
BA9/
BA7/
BA6/
BA4/
GND
BAI/
B~1

BSYNC
BDROI/
GND
' -12V/-V
BFLT/
B~O
GND
BDR021
BRlW
BACT/
BNMI/
GND
BRES/
BD6/
BD5/
BD3I
GND
BDO/
GND

Signal Name

+5 Vdc
Buffered ,Address Bit 15
Buffered Address Bit, 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffered Address Bit 4
Ground
'Buffered Address Bit 1
"Buffered Phase 1 Clock
"Buffered Sync
' 'Buffered DMA Request 1
Grouhd
"-12Vdc/-V
"User Spare 2
"Buffered Bus Float
"Buffered External Phase 0 Clock
Ground
"Buffered DMA Request 2
"Buffered Read/Write
Buffered Bus Active
"Buffered Non-Maskable Interrupt
Ground
'Buffered Reset
Buffered Data Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit 0
Ground

Note: 'Not used on this module

~

80.-' TO
B071

•

•
DATA BUS
TRANSCEIVERS

I

I

I

BACT/

3

BA13! 81\141 8A1S/

B'2J

MODULE

.~

~

HEADER

I •

MEMORY
A

4

ACTIVE

HIGH
SPEED

•

OPTION

SHUNT

r-

P-i

*I

DEVICE
SELECT A

8A,1 TO
BA13!

~

14
ADDRESS
AND

16

4

CONTROL
BRm,'

MEMORY A

DECODER

r-- t-r-

BUFFER

*-

-----+BADAl

BANK
ADDRESS
SELECT

I-I-----

~
4

MEMORY B

DECODER

UNIVERSAL
MEMORY
OPTION
SHUNT

~

Target RAM Module Block Diagram
6-28

~
4

MEMORY

B

I

~

DEVICE
SELECT B

J

RDC-102X

Target RAM Module

SPECIFICATIONS
Parameter

Value

Dimenslons(1,2,3)
Width
Length
Height

100 mm (3.94 In.)
160 mm (6.3 in.)
14 mm (0.55 in.)

Weight

156 g (5.5 oz.)

E nv ironment
Operating Temperature
Storage Temperature
Relative Humidity

O'C to 70'C
- 40'C to 85'C
0% to 85% (without condensation)

Power Requirements

5 OV (420 mao typical, 640 mao maximum with no memory devices Installed)

Connector
RM 65 Bus Connector PI

64-pln plug (0.100 In centers) per DIN 41612 (Row b not installed)-mates
With Burndy PI96B32ROOAOOL-9 or eqUivalent

Notes
t Height Includes the maximum values for component height above the board surface (04 In. for populated modules), printed CIrCUit board
thickness (0.062 In.), and pin extension through the bottom of the module (Olin.)
2. Length does not Include the added extension due to the module elector
3 Dimensions conform to DIN 41612

1--

rJ?

LENGTH

L

.j

HEIGHT

f

WIDTH

L

EUROCONNECTOR
EXTENSION

---II.... __
Module Dimensions

6-29

EUROCARD CONNECTOR
COMPONENT AREA

o::--~- - -=

~

RDC-1030
Microcomputer Development Systems

'1'

Rockwell

RDC-1030
MULTIPLE TARGET
DEVELOPMENT SYSTEM (MTDS)
PROM PROGRAMMER MODULE

INTRODUCTION

FEATURES

The Multiple Target Development System (MTDS) is a development system vertically integrated to support the entire R6500
family of microprocessors and microcomputers. The MTDS allows
emulation, development, and software debugging of up to four
separate microprocessors and microcomputers concurrently,
even ifthe four devices are different members of the R6500 family.
The MTDS is a disk-based system with two 96 TPI, double-sided,
double-density 5%-inch floppy disk drives that provide a storage
capacity of up to 1.3M bytes of data (formatted).

•

Programs 2K-byte to 8K-byte UV EPROMs
-2K-byte: 2516, 2716
-4K-byte: 2532, 2732, 2732A
-8K-byte: 2564, 2764, 68764

• Erases and programs 2K-byte EEROMs
-2K-byte: R5213/2816, 5213, 2816, 48016
• Connects to PROM socket module installed in the MTDS with

A unique bus structure provides a separate system bus and four
target busses which can operate at different speeds (up to 4 MHz).
Construction of the MTDS is modular based on the proven RM
65 microcomputer module design using both single- and doublesized Eurocards and highly reliable DIN 41612 pin and socket connectors. The double Eurocards allow use of both the system bus
and a target bus which can operate at different speeds.

-28-pin and 24-pin Zero Insertion Force (ZIF) sockets
-Connecting 24-inch cable to RM 65 module
• Easy-to-use interactive softkey commands
-PROM interface (check, program, read, verify)
-RAM preparation (alter and invert)
-Utility functions (PROM type selection, toggle verify mode,
etc.)

PRODUCT OVERVIEW
The RDC-1030 PROM Programmer Module, in conjunction with
the MTDS, programs industry standard 2K-, 4K- and 8K-byte
EPROMs (ultra-violet light erasable programmable read-only
memories) and 2K-byte EEROMs (electrically erasable programmable read-only memories). The module consists of an RM 65
module and a 24-inch ribbon cable. A 28-pin and a 24-pin Zero
Insertion Force (ZIF) socket are mounted on the MTDS mainframe to allow installation of a 28-pin or 24-pin PROM.

• Verify during or after programming
• Compact size RM 65 module-about 100 mm x 160 mm
(4 in. x 6% in.)

•

+ 5V only operation (on-board DC/DC converter)

• Fully assembled and tested with one year warranty

RDC-1030 PROM Programmer Module

Document No. 29655N13
6-30

Data Sheet Order No. RDC13
September 1984

RDC-1030

MTDS PROM Programmer Module

ORDERING INFORMATION
Part No.
RDC·t030

Description
MTDS PROM Programmer Module

Order No.
RDCt2

The R6522 VIA transfers a-bit data between the RM 65 data bus
and the PROM data lines and controls programming voltage
levels. During PROM programming, the VIA transfers data from
the Data Transceivers for writing into the PROM and during a
PROM read, verify or check function, the VIA reads data from
the PROM. During PROM programming, the VIA issues control
signals to the Power Multiplexer, the Misplaced PROM Detector,
and the Vpp Rise/Fall Time Controller.

D,.crlptlon
MTDS PROM Programmer Module User's Manual'

Note:
'Included with RDC-t030.

The Programmable Voltage Regulator, consisting of the a-bit
DAC, a Vpp Rise/Fall Time Controller, a DC/DC Converter and
an Analog Buffer, generates the Vpp programming voltage. The
DAC outputs a voltage proportional to Vpp for the selected
PROM type as controlled by a-bit data received from the RM 65
data bus. The DAC output voltage is amplified to the full Vpp
level, mixed with the rise or fall time control signal, clamped to
minimum Vpp level, and output to the Analog Buffer. The + 5
to + 32V DC/DC Converter provides the high voltage used in
the second stage of amplification. The Analog Buffer amplifies
the Vpp current for use by the Power Multiplexer.

FUNCTIONAL DESCRIPTION
PROM PROGRAMMER MODULE
The Data Transceivers invert and transfer a-bits of parallel data
between the PROM Programmer module and the RM 65 data
bus when enabled by the Chip Select Decoder. The read/write
line from the RM 65 bus determines the direction of data flow.
During a write operation, data is transferred from the bus to the
module; during a read operation, data is transferred from the
module to the RM 65 bus.

The Power Multiplexer selects the proper voltage level to output to the PROM during a programming or read operation as
controlled by signals from the VIA and Octal Latch A. The output voltage is selected from TTL high, TTL low, Vcc and the Vpp
output from the Analog Buffer. The correct voltage is selected
by VIA output control lines.

The Control Signal Buffers invert and transfer the phase 2,
read/write, bank address and reset signals from the RM 65 bus
to the module. The bus active signal is also driven to the RM 65
bus when data is being transferred between the RM 65 bus and
the module.
Address Signal Buffers invert and transfer signals from 13
address lines from the RM 65 bus to the module.

The Misplaced PROM Detector determines if a 24-pin PROM
has been installed in the 2a-pin ZIF socket on the PROM module.
The detected state is input to the VIA and sampled by the
programming firmware to prevent application of programming
voltage to a misplaced PROM.

The Chip Select Decoder, in conjunction with Base Address
Select, Bank Select and Bank Select Enable switches and the
ROM Range Select jumper decodes the address from the RM 65
bus and generates enable signals to other major on-board
circuits. When the address matches the I/O Base Address switch
positions, one of two Octal Latches, the on-board R6522
Versatile Interface Adapter (VIA), the Digital-to-Analog Converter
(DAC) and/or the Data Bus Transceivers are enabled. When the
address matches the ROM Base Address switch positions and
ROM Range Selection jumper position, the on-board program
ROM is enabled along with the Data Bus Transceivers.

The two Octal Latches, A and B, transfer addresses from the
Address Buffers to the PROM during PROM access operations.
The levels of three programming voltages output by the Power
Multiplexer to the PROM are also controlled by Octal Latch A.

PROM SOCKETS AND INTERFACE CABLE

Bank Select and Bank Select Enables switches assign the
module to one or two 65K-byte memory banks. The Bank Select
Enable switch assigns the module to be active in common
memory (both Bank 0 and 1).

Both 2a-pin and 24-pin Zero Insertion Force (ZIF) sockets are
mounted on the front panel of the MTDS mainframe and connected to the PROM Programmer module by a 24-inch ribbon
cable.

6-31

RDC-1030

MTDS PROM Programmer Module

PROM PROGRAMMER COMMANDS

PROM PROGRAMMER FUNCTIONS

Computer program routines to operate the PROM Programmer
module are provided on a diskette to be installed in the MTDS
system. Easy-to-use interactive commands perform PROM
interface functions (check, program, read and verify), RAM
preparation functions (fill and invert) and utility functions (e.g.,
command and PROM type menus, toggle verification mode, and
change PROM type).

PROM Programmer commands are invoked from a command
soft key software mode the same as used in the standard MTDS
software. The commands listed can then be selected by single
keystrokes. Subprompts displayed upon command selection
request entry of information pertinent to the specific function.
Once initiated, each function operates automatically until
successful completion or upon termination due to a detected
error.

Command

Function

CHECK
PROGRAM
READ
VERIFY
MODIFY
ALTER
INVERT
SAVE
ERASE
SELECT
TOG.VER
CHEKSUM
LOAD
DUMP
DIR
RENAME
DELETE
RECOVER

Check PROM
Program PROM
Read PROM
Verify PROM
Modify Memory
Alter Memory
Invert Memory
Save Memory
Erase EEROM
Select PROM Type
Toggle Verify Mode
Checksum Memory
Load
Dump
Display Disk Directory
Rename File
Delete File
Recover Deleted File

RM 65 BUS

I/O BUS
CONNECTOR

CONNECTOR

DATA

PROM
ADDRESS

PROM
ADDRESS
AND CONTROL
CONTROL
AND
TIMING

PROM
DATA
PROM
ADDRESS
AND DATA

ADDRESS
PROM
ADDRESS
CONTROL
BANK ADDRESS

Vee, Vpp

BANK
AODRESS.
ENABLE AND
SELECT
SWITCHES

FIRMWARE
AND 110 BASE
ADDRESS
SELECTION
SWITCHES

PROM Programmer Module Block Diagram

6-32

RDC-1030

MTDS PROM Programmer Module
PROM Socket Pin Assignment

Connector 24-pin PROM 28-pin PROM
Jl (P2)
Socket Pin
Socket Pin Signal
Pin No.
Number (1)
Number
Symbol
3.5.10,
15,24,26,
2S, 30, 32
35,37,39
1,40
2
4
6
7
8
9
11
12
13
14

Connector 24-pin PROM 28-pin PROM
Jl (P2)
Socket Pin
Socket Pin
Pin No.
Number (1)
Number

Signal Name

12

14

GND

Ground

-

28
1
2
3
4
5
6
7
S
9
10

VCC
VPP
A12
A7
A6
AS
A4
A3
A2
AI
AO

PROM Supply Voltage
Programming Voltage
Address Bit 12
Address Bit 7
Address Bit 6
Address Bit 5
Address Bit 4
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit a

-

1
2
3
4
5
6
7
S

16
17
18
19
20
21
22
23
25
27
29
31
33
34
36
3S

9
10
11
13
14
15
16
17
18
19
20
21
22
23
24

11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27

-

Signal
Symbol

Signal Name

00
01
02
03
04
05
06
07
CE
Ala
OE
All
A9
AS

Data Bit a
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Chip Enable
Address Bit 10
Output Enable
Address Bit 11
Address !'lit 9
Address Bit S
Al~(2) Address Bit 13
PGM
Program

Note: (1) Nomenclature applies to the recommended JEDEC Bytewide pin-out.
(2) Applies to 24-pin devices

RM 65 Bus Pin Assignments
Bottom (Solder Side)
Pin
la
2a
3a
4a
Sa
6a
7a
Sa
9a
IDa
lla
12a
13a
14a
15a
16a
17a
ISa
19a
20a
21a
22a
23a
24a
25a
26a
27a
2S8
29a
30a
31a
32a

Signal
Mnemonic

Signal Name

GND
BADRI
GND
BA131
BA111
BA101
BASI
GND
BASI
BA31
BA21
BAOI
GND
BSO
BRDY
+12V/+V
GND
BDMTI
BRml
GND
BIROI
Ba21
BIJ2
BD71
GND
BD41
8D21
BOIl
+5V

Top (Component Side)

I

Pin

Ground
Buffered Bank Address
Ground
Buffered Address Bit 13
Buffered Address Bit 11
Buffered Address Bit 10
Buffered Address Bit S
Ground
Buffered Address Bit 5
Buffered Address Bit 3
Buffered Address Bit 2
Buffered Address Bit 0
Ground
"Buffered Set Overflow
"Buffered Ready
"User Spare 1
"+12 Vdc
Ground
"Buffered DMA Terminate
"User Spare 3
Buffered ReadlWrite "Not"
"System Spare
Ground
"Buffered Interrupt Request
Buffered Phase 2 "Not" Clock
"Buffered Phase 2 Clock
Buffered Data Bit 7
Ground
Buffered Data Bit 4
Buffered Data Bit 2
Buffered Data Bit 1
+5 Vdc

lc
2c
3c
4C
5c
6c
7c
Sc
9c
10c
llc
12c
13c
14c
15c
16c
17c
18c
19c
20c
21c
22c
23c
24c
25c
26c
27c
28c
29c
30c
31c
32c

Note:
"Not used on this module

6-33

Signal
Mnemonic
+5V
VA151
BAI41
BA121
GND
BA91
BA71
BA61
BA41
GND
BA1I
Bal
BSYNC
BDR01/
GND
-12V/-V
BFLTI
BaO
GND
BDR021
BRm
BACTI
BNMII
GND
BRESI
BD61
BD51
BD31
GND
BDOI
GND

Signal Name
+5 Vdc
Buffered Address Bit 15
Buffered Address Bit 14
Buffered Address Bit 12
Ground
Buffered Address Bit 9
Buffered Address Bit 7
Buffered Address Bit 6
Buffered Address Bit 4
Ground
Buffered Address Bit 1
"Buffered Phase 1 Clock
"Buffered Sync
"Buffered DMA Request 1
Ground
" -12Vdc/-V
"User Spare 2
"Buffered Bus Float
"Buffered External Phase 0 Clock
Ground
"Buffered DMA Request 2
"Buffered ReadlWrite
Buffered Bus Active
"Buffered Non-Maskable Interrupt
Ground
Buffered Reset
Buffered Data Bit 6
Buffered Data Bit 5
Buffered Data Bit 3
Ground
Buffered Data Bit a
Ground

MTDS PROM Programmer Module

RDC-1030
SPECIFICATIONS
Parameter

Value

.- r--'

Dlmenalons
PROM Programmer Module
Width
Length
Helght(1)
PROM Programmer Cable
Length

100 mm (3.94 in.)
167 mm (6.58 in.)
14 mm (0.56 in.)
610 mm (24 In.)

Weight

184 g

Environment
Operating Temperature
Storage Temperature
Relative Humidity

o· to 70·C
- 40·C to 85·C
0% to 85% (without condensation)

Power Requirements

(6.5 oz.)

+5V ±5% at 1.1 A typical
2.0 A maximum (average)
2.9 A maximum (peak)

Connectore/Sockets
AM 65 Bus Connector (PI)

64-pln plug per DIN 41612 (Rows a and b with c not Installed)
40-pln plug (0.100 In. centers) per DIN 41612, mates with
3417-7040 (3M) or equivalent
28-pl nand 24-pl n

Socket Module Cable Connector (J 1)
PROM Sockets

Note:
1. Height value includes the maximum values for component height above the board surface (0.4 in.), printed circuit board thickness
(0.062 in.), and pin extension through the bottom of the module (0.1 in.).

.

,

CABLE

f

 -43
> -33
> -26
> -16

0
1
2
3

7·29

dBm
dBm
dBm
dBm

RLSD Off

< -48
< -38
< -31
< -21

dBm
dBm
dBm
dBm

9600 bps Data Pump Modem

R96DP

R96DP Interface Memory Definitions (Continued)
Mnemonic

Name

Memory
Location

Description

RTS

Request-to-Send

0:7:7

When control bit RTS goes to a one, the modem begins a transmit sequence. It
continues to transmit until RTS is reset to zero, and the turn-off sequence has been
completed. This input bit parallels the operation of the hardware RTS control input.
These inputs are ORed by the modem.

SOlS

Scrambler Disable

0:7:5

When control bit SOlS is a one, the transmitter scrambler cirCUit IS removed from the
data path.

SEPT

Short Echo
Protector Tone

0:7:0

When control bit SEPT IS a one, the echo protector tone is 30 ms long rather than
185 ms.

TBA

Transmitter Buffer
Available

O:E'O

This status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register O' 0, this bit sets to a one.

TIA

Transmitter
Interrupt Active

0:E:7

This status bit is a one whenever the transmitter IS driving IRO to a zero.

TIE

Transmitter
Interrupt Enable

0:E'2

When the host processor wntes a one in control bit TIE, the IRO line of the hardware
interface is dnven to zero when status bit TBA IS at a one.

TLVL

Transmitter Level
Field

0:4'2-4

The transmitter analog output level is determined by eight TLVL codes, as follows
TLVL
0
1
2
3
4
5
6
7

Transmitter Analog Output"
-1
-3
-5
-7
-9
-11
-13
-15

dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm

±1 dB
±1 dB
± 1 dB
±1 dB
±1 dB
± 1 dB
±1 dB
±1 dB

'Each step above is a 2 dB change ± 0.2 dB.
TOO

Train-on Data

1 :6:6

When control bit TOO is a one, it enables the train-an-data algorithm to converge the
equalizer if the signal quality degrades suffiCiently. When TOO IS a one, the modem st"l
recognizes a training sequence and enters the force train state. A BER of approximately
10. 3 for 0.5 seconds initiates traln-on-date.

TPOM

Transmitter Parallel
Data Mode

0:7:2

When control bit TPOM is a one, the transmitter accepts data for transmiSSion from the
transmitter data register (0: 0) rather than the serial hardware data input.

(None)

Transmitter
Configuration

0:6:0-7

The host processor configures the transmitter by writing a control byte Into the
transmitter configuration register in its interface memory space. (See TSB).
Transmitter Configuration Control Codes

Control codes for the modem transmitter configurations are:
Configuration

Configuration Code (Hex)

V.299600
V.297200
V.294800
V.27 4800 Long
V.27 2400 Long
V.27 4800 Short
V.27 2400 Short
Tone Transmit

14
12
11
22
21
02
01
80

7-30

R96DP

9600 bps Data Pump Modem
R96DP Interface Memory Definitions (Continued)

Mnemonic
(None)

Name
Transmitter Data

Memory
Location
0:0:0-7

Description
The host processor conveys output data to the transmitter in the parallel mode by
writing a data byte to the transmitter data register. The data is divided on baud
boundaries, as follows:
NOTE
Data

IS

transmitted bit zero first.
Bits

Configuration

7

I

V.29 9600 bps

I

5

6

Not Used

V.29 4800 bps

Baud 3

V.27 4800 bps

Not Used

V.27 2400 bps

Baud 3

I

I

Baud 1

V.29 7200 bps

4

Baud 1
Baud 2

I

Baud 1
Baud 2

I

3

I

2

I

I

1

0

Baud 0

i
Baud 1

Baud 0

I

I
Baud 1

Baud 0

Baud 0

J

Baud 0

TSB

Transmitter Setup
Bit

0:E:3

When the host processor changes the transmitter configuration, the host must write a
one in this control bit. TSB goes to a zero when the change becomes effective.

TTDIS

Transmitter Train
Disable

0:7:6

When control bit TTDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay is less than two
baud times.

T2

T/2 Equalizer
Select

1 :7:1

When control bit T2 IS a one, an adaptive equalizer with two taps per baud IS used.
When T2 is a zero, the equalizer has one tap per baud. The total number of taps
remains the same for both cases.

XCEN

External Clock
Enable

0:7: 1

When control bit XCEN is a zero, the transmitter timing is established by the external
clock supplied at the hardware input XTCLK, pin 22A.

POWER-ON INITIALIZATION

BIT ERROR RATES

When power is applied to the R96DP, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms atter
the low to high transition of POR, the modem is ready to be configured, and RTS may be activated. If the 5 Vdc power supply
drops below 3.5 Vdc for more than 30 msec, the POR cycle is
generated.

The Bit Error Rate (BER) performance of the modem is specified
for a test configuratio conforming to that specified in CCITT
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of - 20 dBm as
illustrated.

PHASE JITTER

At POR time the modem defaults to the following configuration:
V.29, 9600 bps, T/2, standard echo protector tone, serial data
mode, internal clock, cable equalizers disabled, link amplitude
equalizer disabled, link delay equalizer disabled, transmitter
output level set to - 1 dBm ± 1 dB, interrupts disabled, receiver
threshold set to - 43 dBm, eye pattern selectable, and traln-ondata disabled.

At 2400 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
At 4800 bps (V.27 bislter), the modem exhibits a bit error rate
of 10- 6 or less with a signal-to-noise ratio of 10 dB in the
presence of 15° peak-to-peak phase jitter at 60 Hz.

P(,)R r:~n I)~ rnnnl?t:'terl tn

;::t 1)5Ar ~L'rrlierl rnwl?r-on-reset sigl1F.1I
in a wire-or configuration. A low active pulse of 3 ",sec or more
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec atter POR is removed

At 9600 bps, the modem exhibits a bit error rateof 10- 6 or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peakto-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10- 5 or less with a signal-to-noise ratio of 23 dB in the
presence of 20° peak-to-peak phase jitter at 30 Hz.

PERFORMANCE
Whether functioning as a V.27 ter or V.29 type modem, the
R96DP provides the user with unexcelled high performance.
7-31

II

R96DP

9600 bps Data Pump Modem

An example of the SER performance capabilities is given in the
following diagram:

GENERAL SPECIFICATIONS
Power

10- 3

4800 BPS
V 27
AND
7200 BPS 9600 BPS
V.29 ' / V.29

2400 BPS 4800 BPS
V.29
V.27

\

Voltage

Tolerance

Current (Max)

+5 Vdc
+ 12 Vdc
-12 Vdc

±5%
±5%
±5%

<700 rnA
<20 rnA
<80 rnA

V

/V

Environmental
Parameter
Temperature
Operating
Storage

10-'

i

Relative Humidity:

iIii
10- 5

Specification
OOC to +60°C (32 to 140°F)
-40°C to +80 0 C (-40 to 176°F)
Stored in heat sealed antistatic bag
and shipping container
Up to 90% noncondenslng, or a wet
bulb temperature up to 35°C,
whichever is less.

Mechanical
Parameter

\

\

10- 8

8

:s 0.1 volts peak-ta-peak.

Note: All voltages must have ripple

8

10 12

14 16

18

20 22

24 28

LINE

f--- SIMULATOR f---

Dimensions

Wldth-3.94 In. (100 mm)
length-4.72 in. (120 mm)
Helght-0.4 in. (10.2 mm)

Weight

less than 3.6 oz. (100g)

The SER performance test set-up Is shown in the following
diagram:

Woret Caae BER Performance
(Back-to-Back)

MODEM
TRANSMtTTER

Single PC board with single right
angle header with 64 pins, Burndy
(P196B32ROOAOOZ1) or equivalent
mating connector.

28 30

SIGNAL-TD-NOISE RATIO dB

Specification

Board Structure

NOISE
SOURCE
GR1381
50 KHZ BW

r--

ATTENUATOR
HP 3500

IMPAIRMENT
SOURCE
BRADLEY 2A

~

ATTENUATOR
HP 3500

-

L

r--

LEVEL
METER
HP 3552A

r-'--

MODEM
RECEIVER

I

I

ENGINEERING
MODEM
CONSOLE

ENGINEERING
MODEM
CONSOLE

NOTE
SI GNAl AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING,

BER Performance Teat Set-up

7-32

R96DP

9600 bps Data Pump Modem

.156 ± .003
DIAMETER
6 PLACES
MALE 64·PIN

~ DIN CONNECTOR

R96DP

Inches

MM

.119
.156
.483
3.275
3.700
3.937
4.100
4.725

3
4
12
83
94
100
104
120

R96DP Circuit Board Dimensions

II
7·33

R96FT
Integral Modems

'1'

Rockwell

R96FT
9600 BPS FAST TRAIN MODEM
PRELIMINARY

INTRODUCTION

FEATURES

The Rockwell R96FT is a synchronous serial 9600 bps modem
designed for multipoint and networking applications. The R96FT
allows full-duplex operation over either four-wire dedicated
unconditioned lines or half-duplex operation over the general
switched telephone network.

• User Compatibility:
- Proprietary Fast Train
-CCITTV.29
• Train on Data
• Full-Duplex (4-Wire)
• Half-Duplex (2-Wire)
• Programmable Tone Generation
• Dynamic Range -43 dBm to 0 dBm
• Diagnostic Capability
• Equalization:
- Automatic Adaptive
- Compromise Cable (Selectable)
- Compromise Link (Selectable)
• DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Loopbacks
- Local Analog (V.54 Loop 3)
- Remote Analog (Locally Activated)
- Remote Digital (Locally Activated V.54 Loop 2)
• Small Size
-100 mm x 120mm (4.0 in. x 4.8 in.)
• Low Power Consumption
- 4 watts, typical
• Programmable Transmit Output Level
• TTL and CMOS Compatible

Proprietary fast train configurations provide communication at
9600, 7200 and 4800 bps with the ability to train in thirty milliseconds. For applications requiring operation with international
standards, fallback configurations compatible with CCITT recommendation V.29 at 9600,7200 and 4800 bps are available. These
configurations require 253 milliseconds to train.
The small size and low power consumption of the R96FT offer
the user flexibility in formulating a 9600 bps modem design customized for specific packaging and functional requirements.

R96FT Modem

Document No. 29200N09
7-34

Data Sheet Order No. MD09
Rev. 1 June 1984

R96FT

9600 bps Fast Train Modem

TECHNICAL SPECIFICATIONS

RECEIVE LEVEL

TRANSMITTER CARRIER FREQUENCY

The receiver circuit of the modem satisfies all specified performance requirements for received line signal levelS from 0 dBm
to -43 dBm. The received line signal level is measured at the
receiver analog input (RXA).

The transmitter carrier frequency is 1700 Hz ± 0.01 % for all
configurations.

TONE GENERATION

RECEIVE TIMING

Under control of the host processor, the R96FT can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.

The R96FT provides a data derived Receive Data Clock (RDClK)
output in the form of a squarewave. The low to high transitions
of this output coincide with the centers of received data bits.
The timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source.

SIGNALING AND DATA RATES
Signaling/Data Rates
Parameter
Signaling Rate'
Data Rate:

TRANSMIT LEVEL

Specification
(to.Ol%)

The transmitter output level is accurate to ± 1.0 dB and is programmable from - 1.0 dBm to - 15.0 dBm in 2 dB steps.

2400 Baud:
9600 bps,
7200 bps,
4800 bps

TRANSMIT TIMING
The R96FT provides a Transmit Data Clock (TDClK) output with
the following characteristics:
1. Frequency. Selected data rate of 9600, 7200, or 4800 Hz
(±0.01%).
2. Duty Cycle. 50% ± 1%

DATA ENCODING
The data stream is encoded per CCITT V.29. At 9600 bps, the
data stream is divided in groups of four-bits (quad-bits) forming
a 16-point structure. At 7200 bps, the data stream is divided into
three bits (tribits) forming an 8-point structure. At 4800 bps, the
data stream is divided into two bits (dibits) forming a 4-point structure. Signal structure, scrambler, and encoding are compatible
with CCITT V.29.

Input data presented on TXD is sampled by the R96FT at the
low to high transition of TDClK. Data on TXD must be stable
for at least one microsecond prior to the riSing edge of TDClK
and remain stable for at least one microsecond after the rising
edge of TDClK.

EXTERNAL TRANSMIT CLOCK

EQUALIZERS

The transmitter data clock (TDClK) can be phase locked to a
signal on input XTClK. This input signal must equal the desired
data rate (or a submultiple of the data rate) ± 0.01 % with a duty
cycle of 50% ± 20%.

The R96FT provides equilization functions that improve performance when operating over low quality lines.
Cable Equalizers - Selectable compromise cable equalizers
in the receiver and transmitter are provided to optimize performance over different lengths of non-loaded cable of 0.4 mm
diameter.

TRAIN ON DATA
When train on data is enabled (by setting a bit in the interface
memory), the modem monitors the EOM signal. If EOM indicates
a loss of equilization (I.e., BER approximately 10- 3 for
0.5 seconds) the modem attempts to retrain on the data stream.
Retrain is accomplished in three to fifteen seconds depending
on line conditions.

Link Equalizers - Selectable compromise link equalizers in the
receiver optimize performance over channels exhibiting severe
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.
Automatic Adaptive Equalizer - An automatic adaptive T
equalizer is provided in the receiver circuit.

TURN-ON SEQUENCE
Nine selectable turn-on sequences can be generated as follows:

TRANSMITTED DATA SPECTRUM

Turn-On Sequences
No. Configuration CTS Response Time
Comments
1
FT/9600
30
2
FT/7200
30
Proprietary Fast Train
FT/4800
3
30
4
V.29/9600
253
CCITT Recommenda·
5
V.29/7200
253
tion V.29
V.29/4800
253
6
7
V.29/9600
V.29 preceded by
458
echo protector tO~8
V 29/7200
8
458
V.29/4800
for lines uSing echo
9
458
suppressors'
• For short echo protector tone, subtract 155 msec. from values of CTS
response time.

If the cable equalizer is not enabled, the transmitter spectrum
is shaped by a square root of 20 percent raised cosine filter.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's rules.

SCRAMBLER/DESCRAMBLER
The R96FT incorporates a self-synchronizing scramblerl
descrambler. This facility is in accordance with V.29.

RECEiVED SIGNAL
FREQUENCY TOLERANCE
The receiver circuit of the R96FT can adapt to received frequency error of up to t 10Hz with less than 0.2 dB degradation in BER performance.

TURN-OFF SEQUENCE

During fast train polling, frequency offset must be less than
± 2 Hz for successful training.

The turn-off sequence consists of approximately 5 ms of remaining data and scrambled 1'So
7-35

9600 bps Fast Train Modem

R96FT
CLAMPING

3. Greater than - 26 dBm (RLSO on) .
Less than - 31 dBm (RLSO off)
4. Greater than -16 dBm (RLSO on)
Less than - 21 dBm (RLSO off)

Received Oata (RXO) is clamped to a constant mark (one) when
the Received Line Signal Oetector (RLSO) is off.

RESPONSE TIMES OF CLEAR·TO·SEND (CTS)

NOTE
Performance may be at a reduced level when the received
signal is less than - 43 dBm.

The time between the off-to-on transition of Request-To-Send
(RTS) and the off-to-on transition of eTS is dictated by the length
of the training sequence if used. These times are given in the
Turn-On Sequences table. If training is not enabled, RTS/CTS
delay is less than 2 baud times.

A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on -ta-off transition levels. The threshold levels and
hysteresis action are measured with a modulated carrier signal
applied to the receiver's audio input (RXA).

The time between the on-to-off transition of RTS and the on-tooff transition of eTS in the data state is a maximum of 2 baud
times for all configurations.

MODES OF OPERATION

RECEIVED LINE SIGNAL DETECTOR (RLSD)

The R96FT is capable of being operated in either a serial or a
parallel mode of operation.

For the fast train configurations, RLSO is activated by an
increase of approximately 15 dB or greater in line power. The
RLSO signal turns on at the end of the training sequence. If
training is not detected at the receiver, the RLSO off-to-on
response time is 32 ± 5 ms. The RLSO signal is deactivated by
a decrease of approximately 15 dB in line power. RLSO on-tooff response time is 10 ± 3 ms.

SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the Functional Interconnect Oiagram) illustrates this capability.

For V.29 configurations RLSO is activated by line power above
a preset threshold. The RLSO signal turns on at the end of the
training sequence. If training is not detected at the receiver, the
RLSO off-to-on response time is 15 ± 10 ms. The RLSO on-ta-off
response time for V.29 is 30 ±9 ms. Response times are
measured with a signal at least 3 dB above the actual RLSO
on threshold or at least 5 dB below the actual RLSO off threshold.

The R96FT has the capability of transferring channel data 8 bits
at a time via the microprocessor bus in 9600 or 4800 bps
configurations, 6 bits at a time in 7200 bps configuration.

Four threshold options are provided:
1. Greater than - 43 dBm (RLSO on)
Less than - 48 dBm (RLSO off)
2. Greater than - 33 dBm (RLSO on)
Less than - 38 dBm (RLSO off)

Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the R96FT is configured
by the host processor via the microprocessor bus.

r-----.,
I
I
I
I
I
I
I
I
I

MODE SELECTION

RTS

[

0SCOPE

CTS
rXD
TDCLK
XTCLK
RLSD
RXD
RDCLK
TBCLK

A-,
"','
USART
(OPTIONAL)

A

L---f'A

PARALLEL MODE

'1
I

EVEV

t

EVE
PATTERN
GENERATOR

EVSVNC
EVECLK

RBCLK
MODEM

+12V
+5V

POWER
SUPPLY

GND

.J

-12V

READ

HOST
PROCESSOR
(DTE)

xt tv

EVEX

WRITE
DATA BUS (8)

TXA

ADDRESS BUS (41.

RXA

-

IDECODER

CS (3)

LINE
INTERFACE

AUXIN

POR

IRQ

+5~
R96FT Functional Interconnect Diagram
7-36

:}

TELEPHONE
LINE

R96FT

9600 bps Fast Train Modem

INTERFACE CRITERIA

R96FT Hardware Circuits (Continued)
Name

The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
64-pin DIN connector. Software circuits are assigned to specific
bits in a 48-byte interface memory.

EYEX
EYEY
EYECLK
EYESYNC

HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R96FT Hardware
Circuits table. In the table, the column titled 'Type' refers to
designations found in the Hardware Circuit Characteristics. The
microprocessor interface is designed to be directly compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, it can be made compatible with 6500, 6800, or 68000
microprocessors.

Type

Pin No.

Description

OC
OC
OA
OA

15C
14A
14C
13A

Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal

Data-X Axis
Data-Y Axis
Clock
Synchronizing

EYE PATTERN GENERATION

Description

A. OVERHEAD:
Ground (A)
Ground (D)
+5 volts
+ 12 volts
-12 volts
POR

Pin No.

The four hardware diagnostic circuits, identified in the preceding
table, allow the user to generate and display an eye pattern.
Circuits EYEX and EYEY serially present eye pattern data for
the horizontal and vertical display inputs respectively. The 8-bit
data words are shifted out most significant bit first, clocked by
the rising edge of the EYECLK output. The EYESYNC output is
provided for word synchronization. The falling edge of EYESYNC
may be used to transfer the 8-bit word from the shift register
to a holding register. Digital to analog conversion can then be
performed for driving the X and Y inputs of an oscilloscope.

R96FT Hardware Circuits
Name

Type

F. DIAGNOSTIC:

AGND
31C,32C
Analog Ground Return
DGND 3C,8C,5A,10A Digital Ground Return
PWR 19C,23C,26C,30C + 5 volt supply
PWR
15A
+ 12 volt supply
PWR
12A
-12 volt supply
IIOA
13C
Power-an-reset

MICROPROCESSOR TIMING

READ

WRITE

B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
D1
DO

IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA

1C
1A
2C
2A
3A
4C
4A
5C

RS3
RS2
RS1
RSO

IA
IA
IA
IA

6C
6A
7C
7A

CSO

IA

10C

CS1

IA

9C

CS2

IA

9A

READ
WRITE
IRQ

IA
IA
OB

12C
11A
11C

CSI
(I = 0-2)
Data Bus (8 Bits)
RSi
(I = 0-4)
Register Select (4 Bits)

Chip Select
Transmitter Device
Chip Select Receiver
Sample Rate Device
Chip Select Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request

READ

DI

C. V.24 INTERFACE:
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD

OC
OC
IB
IB
OC
IB
OC
OC

(I
21A
23A
22A
25A
25C
24C
22C
24A

Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request-to-Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal
Detector

Microprocessor Interfsce Timing Diagram
Critical Timing Requirements
Characteristic
CSi, RSi setu~e prior
to Read or Write
Data access ti me after Read
Data hold time after Read
CSi, RSi hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse width

D. ANCILLARY CIRCUITS:
RBCLK
TBCLK

OC
OC

26A
27C
29A
18C

Receiver Baud Clock
Transmitter Baud Clock
(Future Use)
(Future Use)

E. ANALOG SIGNALS:
TXA
RXA
AUXIN

AA
AB
AC

31A
32A
30A

=0-7) - - - . . ,

Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input

7-37

Symbol

Min

Max

Units

TCS
TDA
TDH

30

-

10

140
50

nsec
nsec
nsec

TCH
TWOS
TWDH
TWR

10
75
10
75

-

nsec
nsec
nsec
nsec

-

II

R96FT

9600 bps Fast Train Modem

HARDWARE CIRCUIT CHARACTERISTICS
Digital Interface Characteristics
Ol'lltal Interface Characteristics
Input/Output Type
Symbol

Parameter

Units

IA

IB

IC

V

2.0 Min.

2.0 Min.

2.0 Min.

0.8 Max.

0.8 Max.

0.8 Max.

VIH

Input Voltage, High

VIL
VOH

Input Voltage, Low

V

Output Voltage, High

V

VOL

Output Voltage, Low

liN

Input Current, Leakage

OA

0.4 Max. 2

0.4 Max. 2

110 A

110 B

2.0 Min.

5.25 Max.
2.0 Min.

0.8 Max.

0.8 Max.

2.4 Min.'

2.4 Min.3

0.4 Max. 2

0.4 Max. 2

±2.5 Max.'

Output Current, High

mA

-0.1 Max.

10L

Output Clirrent, Low

mA

1.6 Max.

IL

Output Current, Leakage

~

Ipu

Pull-up Current
(Short Circuit)

~A

CL

Capacitive Load

pF

Co

Capacitive Drive

pF

1.6 Max.

1.6 Max.

± 10 Max.

5

-240 Max.
...,10 Min.

-240 Max.
-10 Min.

5

20

-240 Max.
-10 Min.
100

TIL

1. I Load
2. I Load

0.4 Max. 2

±2.S Max.

10H

Circuit Type

OC

2.4 Min.'

V
~A

OB

TIL
w/Pull-up

= -100 ~A
= 1.6 mA

TIL
w/Pull-up

Type

AA

The transmitter output is a low impedance
operational amplifier output. In order to match to
600 ohms, an external series resistor is required.

RXA

AB

The receiver input impedance is 63.4K ohms
±5%.

AUXIN

AC

The auxiliary analog input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this is a
sampled data input, any signal above 4800 Hz
will cause aliasing errors. The input impedance
is 1K ohms, and the ga.in to transmitter output is
-1 dB ± 1 dB.

10

40

100

100

Open-Drain Open-Drain
3-State
Open-Drain
w/Pull-up Transceiver w/Pull-up

=

Status Control Bits
The operation of the R96FT is affected by a number of software
control inputs. These inputs are written into registers within the
interface memory via the host microprocessor bus. Bits
designated by an 'X' are "Don't Care" inputs that can be set
to either j or O. Modem operation is monitored by various
software flags that are read from interface memory via the host
microprocessor bus. All status and control bits are defined in the
Interface Memory table. Bits designated by an 'R' are reserved
for modem use only and must not be changed by the host.

Analog Interface Characteristics
Name

100

Notes
3. I Load = -40 ~A
4. VIN
0.4 to 2.4 Vdc, Vee = 5.25 Vdc

Analog Interface Characteristics

TXA

TIL

100

-280 Max.
-100 Min.

Characteristics

RAM Data Access
The R96FT provides the user with access to much of the data
stored in the modem's memories. This data is useful for performing certain diagnostic functions.
Two RAM access registers in chip 1 allow user access to RAM
locations via the X word registers (1:3 and 1:2) and the Y word
registers (1:1 and 1:0). Comparable registers in chip 2 provide
access to chip 2 RAM locations. The access code stored in RAM
ACCESS XS (1 :5) selects the source of data for RAM DATA XSM
and RAM DATA XSL (1:3 and 1:2). Similarly, the access code
stored in RAM ACCESS YS (1 :4) selects the source of data for
RAM DATA YSM and RAM DATA YSL (1:1 and 1:0). Chip 2
registers are aSSOCiated in the same way.

SOFTWARE CIRCUITS
The R96FT comprises three signal processor chips. Each of
these chips contains 16 registers to which an external (host)
microprocessor has access. Although these registers are within
the modem, they may be addressed as part of the host
processor's memory space. The host may read data out of or
write data into these registers. The registers are referred to as
interface memory. Registers in chip 1 update at half the modem
sample rate (4800 bps). Registers in chip 0 and 2 update at the
selected baud rate.

Reading of RAM data is performed by storing the necessary
access codes in 1:5 and 1:4 (or 2:5 and 2:4), reading 1:0 (or 2:0)
to reset the associated data available bit (1 :E:O or 2:E:0), then
waiting for the data available bit to return to a one. Data is now
valid and may be read from 1:3 through 1:0 (or 2:3 through 2:0).
The contents of registers 2:3 and 2:1 are also available serially
on outputs EYEX and EYEY, respectively, unless the IFIX bit
(1 :6:7) is set to a one. When IFIX is a one, EYEX and EYEY
remain fixed on the rotated equalizer output.

When information in these registers is being discussed, the
format Y:Z:O is used. The chip is specified by Y(O - 2), the
register by Z(O - F), and the bit by 0(0 - 7, 0 = LSB).
7-38

9600 bps Fast Train Modem

R96FT
RAM Access Codes

Receiver Interface Memory Chip 1 (CS1)

The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.

~

6

7

5

4

2

3

1

0

Register

RAM Access Codes
No.
1
2
3
4
5

Function

Chip X Access Y Access Register

Received Signal Samples
Demodulator Output
Low Pass Filter Output
Average Energy
AGC Gain Word

6 Equalizer Input
7 Equalizer Tap Coefficients
8 Unrotated Equalizer
Output
9 Rotated Equalizer Output
(Received POints)
10 Decision Points
(Ideal Data Points)
11 Error
12 Rotation Angle
13 Fr81 uency Correction
14 EQM
15 Dual POint

1
1
1
1
1

El
Not Used
2,3
CO
40
0,1,2,3
F2
62
0,1,2,3
Not Used
25
0,1
AI
Not Used
2,3

2
2
2

CO
80-9F
El

40
00-IF
61

0,1,2,3
0,1,2,3
0,1,2,3

2

E2

62

0,1,2,3

2

E8

68

0,1,2,3

2
2
2
2
2

E4
A7
A5
BC
E9

F

R

R

R

R

R

R

R

R

E

RSIA

R

R

R

RSB

RSIE

R

RSDA
R

0

R

R

R

R

R

R

R

C

R

R

R

R

R

R

R

R

B

R

PNDET

R

R

R

R

R

CDET

A

R

R

R

R

R

R

R

R

9

R

R

R

R

R

R

R

R

8

R

R

R

7

6

64
0,1,2,3
Not Used
2,3
Not Used
2,3
Not Used
2,3
0,1,2,3
69

R

DDIS RPDM

RTH
IFIX

TOO

R

R

R

R

R

R

R

R

RECEIVER CONFIGURATION

5

RAM ACCESS XS

4

RAM ACCESS YS

3

RAM DATA XSM

2

RAM DATA XSL

1

RAM DATA YSM

0

RAM DATA YSL; RECEIVER DATA

/:

7

6

5

4

2

3

1

0

Bit

NOTE
(X) indicates user available.
(R) indicates reserved for modem use only.

Transmitter Interface Memory Chip 0 (CSO)

~

7

6

5

4

3

2

1

Receiver Interface Memory Chip 2 (CS2)

~

0

Register

7

6

5

4

2

3

1

0

Register

F

R

R

R

R

R

R

R

R

F

R

R

R

R

R

R

R

R

E

TIA

R

R

R

TSB

TIE

R

TBA

E

RBIA

R

R

R

R

RBIE

R

RBDA

0

R

R

R

R

R

R

R

R

0

R

R

R

R

R

R

R

R

C

R

R

R

R

R

R

R

R

C

R

R

R

R

R

R

R

R

B

R

R

R

R

R

R

R

R

B

R

R

R

R

R

R

R

R

A

R

R

R

R

R

R

R

R

A

R

R

R

R

R

R

R

R

9

R

R

R

R

R

R

R

R

9

R

R

R

R

R

R

R

R

8

R

R

R

R

R

R

R

R

8

R

R

R

R

R

R

R

R

7

RTS

7

R

R

R

R

R

R

R

R

6

R

R

R

R

R

R

R

R

2

1

0

TTDIS SDIS MHLD

6

EPT TPDM XCEN SEPT

TRANSMITTER CONFIGURATION

5

X

4

X

LAEN LDEN

CEQ

L3ACT L4ACT L4HG

A3L

D3L

L2ACT LCEN

TLVL

5

RAM ACCESS XB

4

RAM ACCESS YB
RAM DATA XBM

3

FREQM

3

2

FREQL

2

RAM DATA XBL

1

RAM DATA YBM

0

RAM DATA YBL

1

R

R

0

R

R

R

R

R

R

TRANSMITTER DATA

~

7

6

5

4

3

2

1

.:;:

0

Bit

7

6

5

4

3

Bit

NOTE
(X) indicates user available.
(R) indicates reserved for modem use only.

NOTE
(X) indicates user available.
(R) indicates reserved for modem use only.

7-39

9600 bps Fast Train Modem

R96FT
R96FT Interface Memory Definitions
Mnemonic

Name

Memory
Location

Description

A3L

Amplitude 3-lmk
Select

0:5:1

See LAEN.

CEO

Cable Equalizer
Field

0:5:(4,5)

The CEO Control field simultaneously controls amplitude compromise eq!Jalizers m both
the transmit and receive paths. The following table lists the possible cable equalizer
selection codes:
CEQ

Cable Length (0.4 mm diameter)

o

0.0
1.8 km
3.6 km
7.2 km

1
2

3
Carrier Detector

1: B :0

When zero, status bit CDET Indicates that passband energy IS being detected, and
that a training sequence is not in process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal

DDIS

Descramble Disable

1 :7:5

When control bit DDIS is a one, the receiver descrambler CirCUit IS removed from the
data path.
'

D3l

Delay 3-Link Select

0: 5: 0

See LDEN.

,EPT

Echo Protector
Tone

0 : 7: 3

When control bit EPT is a one, an unmodulated carner IS transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of
transmission. This opllOn IS available in the V,27 and V,29 Configurations, although It IS
not specified in the CCITT V.29 recommendation,

(None)

FREOl/FREOM

0:2:0-7,
0:3:0-7

The host processor conveys tone generation data to the transmitter by writing a 16-bit
data word to the FREOl and FREOM registers in the Interface memory space, as
shown below:

FREQM Register (0:3)
I

Bit: I

IData Word: I

7

I

6

215

I

214

I

I

5
2 13

I
j

4
212

I
I

3
211

I
I

2

I

1

I

o

I

2

I

1

I

o

I

20

I
I

FREQL Register (0:2)
I

Bit: I

7

I

IData Word: I

21

I

6
26

I
I

The frequency number (N) determines the frequency (F) as follows:
F = (0,146486) (N) Hz ±0,01%
Hexadecimal frequency numbers (FREOl, FREOM) for commonly generated tones are
given below:

IFIX

Eye Fix

1 :6:7

Frequency (Hz)

FREQM

FREQL

462
1100
1650
1850
2100

OC

52
55
00
55
00

10
2C
31
38

When control bit IFIX is a one, the serial data on EYEX and EYEY reflect the rotated
equalizer output and do not follow the data selected by RAM ACCESS XB and RAM
ACCESS VB.

7-40

R96FT

9600 bps Fast Train Modem
R96FT Interface Memory Definitions (Continued)

Mnemonic

LAEN

Name

Link Amplitude
Equalizer Enable

Memory
Location

0:5:3

Description

The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer in the receive path according to the following table:
LAEN

A3L

Curve Matched

0
1
1

X
0
1

No Equalizer
U.S. Survey Long
Japanese 3-Link

LCEN

Loop Clock Enable

0:4:0

When control bit LCEN is a one, the transmitter clock tracks the receiver clock.

LDEN

Link Delay
Equalizer Enable

0:5:2

The link delay equalizer enable and select bits control a delay compromise equalizer In
the receive path according to the following table:
LDEN

D3L

Curve Matched

0
1
1

X
0
1

No Equalizer
U.S. Survey Long
Japanese 3-Llnk

L2ACT

Remote Digital
Loopback Activate

0:4:1

When control bit L2ACT is a one, the receiver digital output is connected to the
transmitter digital Input In accordance with CCITT recommendation V.54 loop 2

L3ACT

Local Analog Loopback Activate

0'4:7

When control bit L3ACT is a one, the transmitter analog output is coupled to the
receiver analog input through an attenuator in accordance with CCITT recommendation
V.54 loop 3.

L4ACT

Remote Analog
Loopback Activate

0:4:6

When control bit L4ACT is a one, the receiver analog input is connected to the transmitter analog output through a van able gain amplifier In a manner similar to recommendation V.54 loop 4.

L4HG

Loop 4 High Gain

0:4:5

When control bit L4HG is a one, the loop 4 variable gain amplifier is set for + 16 dB,
and when at zero the gain IS zero dB.

MHLD

Mark Hold

0:7:4

When control bit MHLD is a one, the transmitter Input data stream is forced to all marks
(ones).

PNDET

Penod N Detector

1 :B:6

When status bit PNDET IS a zero, It indicates a PN sequence has been detected. ThiS
bit sets to a one at the end of the PN sequence

(None)

RAM Access XB

2:5:0-7

Contains the RAM access code used in reading chip 2 RAM locallons via word X (2: 3
and 2:2)

(None)

RAM Access XS

1 :5:0-7

Contains the RAM access code used in reading chip 1 RAM locations via word X (1 : 3
and 1 :2).

(None)

RAM Access YB

2:4:0-7

Contains the RAM access code used In reading chip 2 RAM locations via word Y (2: 1
and 2'0).

(None)

RAM Access YS

1 :4:0-7

Contains the RAM access code used In reading chip 1 RAM locations via word Y (1 : 1
and 1 :0).

(None)

RAM Data XBL

2:2:0-7

Least significant byte of 16-bit word X used in reading RAM locations in chip 2.

(None)

RAM Data XBM

2:3:0-7

Most significant byte of 16-bit word X used In reading RAM locations In chip 2.

(None)

RAM Data XSL

1 :2:0-7

Least significant byte of 16-blt word X used In reading RAM locations in chip 1

(None)

RAM Data XSM

1 :3:0-7

Most significant byte of 16-bIt word X used In reading RAM locations in chip 1.

7-41

9600 bps Fast Train Modem

R96FT

R96FT Interface Memory Definitions (Continued)
Mnemonic

Name

Memory
Location

Description

(None)

RAM Data YBl

2:0:0-7

least significant byte of 16-bit word Y used in reading RAM locations in chip 2.

(None)

RAM Data YBM

2: 1 :0-7

Most significant byte of 16-bit word Y used in reading RAM locations in chip 2.

(None)

RAM Data YSl

1 :0:0-7

least significant byte of 16-bit word Y used in reading RAM locations in chip 1. Shared
by parallel data mode for presenting channel data to the host microprocessor bus. See
'Receiver Data.'

(None)

RAM Data YSM

1: 1 :0-7

Most significant byte of 16-bit word Y used in reading RAM locations in chip 1.

RBDA

Receiver Baud
Data Available

2:E:0

Status bit RBDA goes to a one when the receiver writes data into register 2: O. The bit
goes to a zero when the host processor reads data from register 2: O.

RBIA

Receiver Baud
Interrupt Active

2:E:7

This status bit is a one whenever the receiver baud rate device is driving IRO low.

RBIE

Receiver Baud
Interrupt Enable

2:E:2

When the host processor writes a one in the RBIE control bit, the IRO line of the
hardware interface is driven to zero when status bit RBDA is a one.

(None)

Receiver
Configuration

1 :6:0-5

The host processor configures the receiver by writing a control code into the receiver
configuration field in the interface memory space (see RSS).
Receiver Configuration Control Codes

Control codes for the modem receiver configuration are:
Configuration

Configuration Code (Hex)

FTI9600
FTI7200
FTI4800
V.2919600
V.2917200
V.2914800

lC
lA
19
14
12
11

(None)

Receiver Data

1 :0:0-7

The·host processor obtains input data from the receiver in the parallel data mode by
reading a data byte from the receiver data register. The data is divided on baud
boundaries as is the transmitter data. When using receiver parallel data mode, the
registers 1 : 3 through 1 : 0 can not be used for reading the chip 1 RAM.

RPDM

Receiver Parallel
Data Mode

1 :7:4

When control bit RPDM is a one, the receiver supplies data .to the receiver data register
(1 : 0) as well as to the hardware serial data output.

RSB

Receiver Setup Bit

1 :E:3

When the host processor changes the receiver configuration (or the RTH field), the host
processor must write a one in the RSB control bit. RSB goes to zero when the changes
become effective.

RSDA

Receiver Sample
Data Available

I:E:O

Status bit RSDA goes to a one when the receiver writes data to register 1: O. RSDA
goes to a zero when the host processor reads data from register 1 : O.

RSIA

Receiver Sample
Interrupt Active

1 :E:7

This status bit is a one whenever the receiver sample rate device is driving IRO to zero.

RSIE

Receiver Sample
Interrupt Enable

1 :E:2

When the host processor writes a one in the RSIE control bit, the IRO line of the
hardware interface is driven to zero when status bit RSDA is at a one.

RTH

Receiver Threshold
Field

1 :7:6,7

The receiver energy detector threshold is set by the RTH field according to the following
codes (see RSB):
RTH

RLSD On

RLSD Off

0
1
2
3

> -43 dBm
> -33 dBm
> -26 dBm
>-16dBm

< -48 dBm
< -38 dBm
< -31 dBm
< -21 dBm

7-42

9600 bps Fast Train Modem

R96FT

R96FT Interface Memory Definitions (Continued)
Mnemonic

Name

Memory
Location

Description

RTS

Request-ta-Send

0:7:7

When control bit RTS goes to a one, the modem begins a transmit sequence. It
continues to transmit until RTS is reset to zero, and the turn-off sequence has been
completed. This input bit parallels the operation of the hardware RTS control input.
These inputs are ORed by the modem.

SOlS

Scrambler Disable

0:7:5

When control bit SOlS is a one, the transmitter scrambler circuit is removed from the
data path.

SEPT

Short Echo
Protector Tone

0:7:0

When control bit SEPT
than 185 ms.

TBA

Transmitter Buffer
Available

O:E:O

This status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, this bit sets to a one.

TIA

Transmitter
Interrupt Active

0:E:7

This status bit is a one whenever the transmitter is driving IRQ to a zero.

TIE

Transmitter
Interrupt Enable

0:E:2

When the host processor writes a one in control bit TIE, the IRQ line of the hardware
interface IS driven to zero when status bit TBA is at a one.

TLVL

Transmitter Level
Field

0:4:2-4

The transmitter analog output level is determined by eight TLVL codes, as follows'

IS

a one, the echo protector disable tone

TLVL
0
1
2
3
4
5
6
7

IS

30 ms long rather

Transmitter Analog Output'
-1
-3
-5
-7
-9
-11
-13
-15

dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm

±1
±1
±1
±1
±1
±1
±1
±1

dB
dB
dB
dB
dB
dB
dB
dB

'Each step above is a 2 dB change ±0.2 dB.
TOO

Train-on Data

1 :6:6

When control bit TOO is a one, it enables the train-on-data algorithm to converge the
equalizer if the signal quality degrades sufficiently. When TOO is a one, the modem still
recognizes a training sequence and enters the force train state. A BER of approximately
10- 3 for 0.5 seconds initiates train-on-data.

TPDM

Transmitter Parallel
Data Mode

0:7:2

When control bit TPDM is a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0) rather than the serial hardware data input.

(None)

Transmitter
Configuration

0:6:0-7

The host processor configures the transmitter by writing a control byte into the
transmitter configuration register in its interface memory space.
Transmitter Configuration Control Codes

Control codes for the modem transmitter configurations are:
Configuration
FT/9600
FT/7200
FT/4800
V.29/9600
V.2917200
V.29/4800
Tone Transmit

7-43

Configuration Code (Hex)
lC
lA
"i9
14
12
11
80

R96FT

9600 bps Fast Train Modem
R96FT Interface Memory Definitions (Continued)

Mnemonic
(None)

Name
Transmitter Data

Memory
Location
0:0:0-7

Description
The host processor conveys output data to the transmitter in the parallel mode by
writing a data byte to the transmitter data register. The data is divided on baud
boundaries, as follows:
NOTE
Data is transmitted bit zero first.
Bits
Configuration

7

I

6

9600 bps

I

I4 I
I

5

Baud 1

7200 bps

Not Used

4800 bps

Baud 3

I
I

Baud 1
Baud 2

I

3

I

2

I

I

1

0

Baud 0

I
Baud 1

Baud 0

I

Baud 0

TSB

Transmitter Setup
Bit

0:E:3

When the host processor changes the transmitter configuration, the host must write a
one in this control bit. TSB goes to a zero when the change becomes effective.

TTDIS

Transmitter Train
Disable

0:7:6

When control bit TTDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS and CTS delay is less than two
baud times.

XCEN

External Clock
Enable

0:7:1

When control bit XCEN is a zero, the transmitter timing is established by the external
clock supplied at the hardware input XTCLK, pin 22A.

POWER-ON INITIALIZATION

PERFORMANCE

When power is applied to the R96FT, a period of 50 to 350 ms
is required for power supply settling. The power-an-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be configured, and RTS may be activated. If the 5 Vdc power supply
drops below 3.5 Vdc for more than 30 msec, the POR cycle is
generated.

Whether functioning in V.29 or the proprietary fast train configurations, the R96FT provides the user with unexcelled high
performance.

POLLING SUCCESS
In fast train configuration the modem achieves a 98% success
rate over unconditioned 3002 lines for a signal-to-noise ratio of
26dB.

BIT ERROR RATES

At POR time the modem defaults to the following configuration:
fast train, 9600 bps, no echo protect tone, serial data mode,
internal clock, cable equalizers disabled, link amplitude equalizer
disabled, link delay equalizer disabled, transmitter output level
set to - 1 dBm ± 1 dB, interrupts disabled, receiver threshold
set to -26 dBm, eye pattern selectable, and train-an-data
disabled.

The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of - 20 dBm as
illustrated.

POR can be connected to a user supplied power-an-reset
signal in a wire-or configuration. A low active pulse of 3 !

...C"i t"i...C>

R96FT

I

1

I

~-

~

1

Inches

MM

.119
156
483
3.275
3.700
3.937
4100
4.725

3

~

+

:-r

bl-3'2~5
4.100
4.725

.483

•

R96FT Circuit Board Dimensions

7·46

4

12
83
94
100
104
120

V96P/1
Integral Modems

'1'

Rockwell

V96P/1
HIGH SPEED 9600 BPS MODEM

INTRODUCTION

FEATURES

The Rockwell V96P/1 IS a versatile, high performance, 9600 bps
modem on a single printed circuit board. Being CCID V.29 and
V.27 compatible, the V96P/1 (with minimal interface circuitry)
can operate on dedicated 2-wire or 4-wire half-duplex or 4-wire
full-duplex lines. The V96P/1 can also operate in half-duplex on
the general switched network.

•
•
•
•

Single printed circuit card
9600/7200/4800/2400 bps modes
Full-duplex or half-duplex
Dedicated or general switched network lines operation

• Ultimate user flexibility:
-CCID V.29, V.27 ter, V.27 bis compatible
-Also 300 bps binary signalling per CCID T.30

Measuring approximately 9.2 inches (23.3 cm) by 6.3 inches
(16.0 cm), the V96P/1 is the smallest full-feature 9600 bps
modem that approaches data communication theoretical performance limits.

DL compatibility
Automatic adaptive equalizer
Analog loop back test circuitry
0 to -45 dBm dynamic AGC
LSI signal processing
High reliability
Low power consumption:
-Typically 3.5 watts
• Automatic training sequence for receiver

•
•
•
•
•
•
•

The V96P/1 meets the tolerances specified in the CCID V.29,
V.27 bis (alternate A), V.27 ter and FSK T.30 speCifications. In
addition, the V96P/1 can be configured to be functionally compatible with those enhanced specifications available in the
Rockwell V96P, M96P, and V29P modem series.

EI
Document No. 29220N30
7-47

Data Sheet Order No. 630
March 1983

V96P/1

High Speed 9600 BPS Modem

FUNCTIONAL SPECIFICATIONS
TRANSMIT CONTROLS

HIGH SPEED DATA INPUT

-----+1

XMIT

~=:~~~~nER

LINE
SIGNAL

DEVICE

FSK DATA INPUT _ _ _ _ _ _ _ _ _ _ _ _

FSK DATA OUTPUT

~

------------"'1

LOOPBACK

EYE QUALITY _ - - - - - - - ,
RECEIVER

DEVICE
BANDPASS
FILTER,
SQUELCH,

HIGH SPEED
DATA OUTPUT

AGe,

RCV

LINE
SIGNAL

THRESHOLD

SELECT

RECEIVE CONTROLS _ _....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '

V96P/1 Functional Block Diagram

Transmit Carrier and Signalling Frequencies

Transmitted Data Spectrum

Carrier Frequency Codex
Compatible QAM:
Carrier Frequency V.29:
Carrier Frequency V.27:
Echo Suppression Frequencies:

At 2400 and 1600 baud the transmitted spectrum is shaped
by approximately a square root of 50 percent raised cosine
filter function. At 1200 baud the spectrum IS shaped by
approximately a square root of 90 percent raised cosine filter
function.

Signalling Frequencies of T.30:

1706.667 Hz
1700 Hz
1800 Hz
2100 Hz
2025 Hz
1850 Hz
1650 Hz
1300 Hz
1100 Hz

± 0.01 %
± 0.Q1%

± 0.01%
± 0.01%
± 0.Q1 %
± 0.01%

The 2400 baud configurations require a line with typical
3002-C2 or M1020 characteristics over the frequency range
from 450 Hz to 2950 Hz. The 1600 and 1200 baud rate configurations require a usable bandwidth from 950 Hz to 2650
Hz and 1150 Hz to 2450 Hz respectively.

± 0.01%
± 0.01%
± 0.Q1%

Received Signal Frequency Tolerance

Data Encoding

The receiver can receive frequency errors of up to ± 10
Hz with less than a 0.2 dB degradation in Bit Error Rate
performance.

At 2400 baud the data stream is divided into groups of four
bits (quadbits), three bits (tribits), or two bits (dibits). The data
rate of 9600 bps, 7200 bps, or 4800 bps is selected by a 16point, 8-point, or 4-point data structure, respectively. For
2400 baud operation, when V.29 configuration is selected,
encoding of the quadbits, tribits, and dibits are per CCITT
Recommendation V.29.

Data Signalling and Modulation Rate
At 2400 baud:
Signalling RateData Rate-

At 1600 baud:
Signalling RateData RateAt 1200 baud:
Signalling RateData Rate-

2400 baud ± 0.01 %
9600 bps ± 0.01 %
7200 bps ± 0.01 %
4800 bps ± 0.01%
1600 baud ± 0.01 %
4800 bps ± 0.01 %

At 1600 baud the data stream is divided into groups of three
bits (tribits). The data rate of 4800 bps may use either an 8point QAM structure or 8-phase structure. Encoding of the
tribits in the 8-phase structure are per CCITT Recommendation V.27 ter.

1200 baud ± 0.01 %
2400 bps ± 0.01 %

At 1200 baud the data stream is divided into groups of two
bits (dibits). The data rate of 2400 bps uses a 4-phase data
7-48

V96P/1

High Speed 9600 BPS Modem
Received Line Signal Detector (0109)

structure. Encoding of the dibits may be per the fallback rate
of CCITT Recommendation V.27 bis and ter (same as V.26A)
or V26B depending on the selected configuration.

The time response of the Received Line Signal detector circuit (0109) is a function of the length of the received turn-on
sequence. Circuit 0109 turns on after synchronizing is completed and prior to user data appearing on the received
output line. 0109 turns on for approximately 2 milliseconds
after the echo protect tone disappears in the V27EP configurations (Nos. 16, 18,21,23,25,29 and 32 in Table 1).

Turn-on, Turn-off Sequences
The V96P/1 turn-on sequences are compatible with CCITT
Recommendations V.29, V.27 bis (alternate i), V.27 and
Rockwell M96P modem specifications.
The turn-off sequences for all V.27 modes (except the 1600
baud rate manual V.27 mode) consists of 5 to 10 milliseconds of remaining data followed by continuous scrambled 1's
followed by no transmission energy. The period of no transmission energy is provided by turning off the transmitter key
signal for a recommended duration of 20 milliseconds.

For non-CCITT configurations (Nos. 7, 8 and 9 in the table
on page 4), 0109 momentarily goes on at the beginning of
the synchronizing sequence.
When no synchronizing signal is detected at the receiver,
0109 turns on in 5 to 15 milliseconds for an applied signal
greater than 3 dB above the turn-on threshold. If training is
not enabled at the receiver, 0109 turns on in 5 to 15
milliseconds.

The turn-off sequences for all non-V.27 modes consists of
4 to 7 milliseconds of remaining data followed by a period of
no transmission energy.

Three threshold options are provided:

Ready For Sending Response Times
The Ready For Sending response time to a Request To Send
is determined by the configuration selected and its corresponding training time. In the following chart of configurations, the Training Times are shown in milliseconds. Note,
however, that the 1600 baud manual CCITT configurations
actually specify the synchronizing sequence timing per CCITT
V.27 rather than the training time. Also note the following
abbreviations.
ITC (1 P-5P):

Receiver Configuration Inputs 1 through 5.
These five bits establish the octal code
shown where P1 and P2 are the most significant octal digit and P3 through P5
establish the least significant octal digit
shown in the chart.

IRSS (1 P-2P),
ITSS (1 P-2P):

Receiver Signal Structure and Transmitter
Signal Structure. Where P1 and P2 establish an octal code of 0, 1, 2, or 3. They
define the Signal structures as follows:
o selects 16-point QAM
1 selects 8-point QAM
2 selects 4-point QAM
3 selects OPSK as:
8-phase at 1600 baud
4-phase at 1200 baud

0109 ON
0109 OFF

2) Greater than -26 dBm:
Less than - 31 dBm:

0109 ON
0109 OFF

3) Greater than -16 dBm:
Less than -21 dBm:

0109 ON
0109 OFF

The three threshold options are controlled by the condition
of the THRESH1 and THRESH2 control lines as indicated
below.

Transmitter Configuration Inputs 1 through
5. These five bits establish the octal code
shown where P1 and P2 are the most significant octal digit and P3 through P5
establish the least significant octal digit
shown in the chart.

IRC (1 P-5P):

1) Greater than -43 dBm:
Less than -48 dBm:

dB Level

THRESH1

THRESH2

-43 dBm ON
-26dBm ON
-16 dBm ON

Open Circuit
Open Circuit
o to -O.5V

Open Circuit
o to -0.5V
Open Circuit

When the received signal drops 5 dB below the 0109 turn
off threshold, 0109 will turn off in 5 to 15 milliseconds. The
condition of 0109 between the selected turn-on and turn-off
thresholds is not specified except that a hysteresis action of
greater than 2 dB exists between the off-to-on and on-to-off
transition levels.
Recommended circuits to control THRESH1 and THRESH2
input interface lines are shown in the diagrams on page 5
(A, B and C).

Bit Error Rates
The V96P/1 is thoroughly tested to guarantee Bit Error Rate
(BER) performance under test conditions equivalent to CCITT
Recommendation V.26. The test set-up used by Rockwell is
shown in the BER Performance Test Set-up diagram.
The results of these BER performance tests are shown in the
Typical Bit Error Rate Performance diagram.

7-49

V96P/1 Configurations

No.
1.
2.
3.
4.
5.
6.
7.

Configuration

2400.
240.0.
240.0.
240.0.
2400.
2400

Baud
Baud
Baud
Baud
Baud
Baud
Baud
Baud
Baud
Baud
Baud
Baud
Baud

DIAL
DIAL - T/2
pop
pop - T/2
V29
V29 - T/2
DIAL, CCITI DIAL
DIAL - T/2
DIAL Slow
Pop
pop - T/2
Echo
Manual CCITI

Transmitter
ITC (1P-5P)
(Octal Code)

Receiver
IRC (1P-5P)
(Octal Code)

0.2
0.2
DO.
DO.
0.1

DO.
0.1
DO.
0.1
0.2
0.3

01
22
22
36
20
20
34
32

22
36
22
20
32
34

Signal
Structura
IRSS (1 P-2P)
ITSS (1 P-2P)
(Octal Code)

Data
Rate
(bps)

Training
Time
(msec)

Carrier
Fraquency
(Hz)

320.
320.
280.
280.

1706 2/3

960.0.
720.0.
480.0.

0.,1,2
0.,1,2

0..1,2
0..1,2
0.,1,2
0..1,2

480.0.
480.0.
480.0.

3D

1,3
1,3
1,3
1,3
1,3
1,3
3

10..

1600.
1600.
1600.
1600.

11.
12.
13.

1600
1600
1600

14.

1600 Baud Manual CCITI

3D

3D

3

4800

15.
16.
17.
18.
19.

1600 Baud V27 D IAL1 P- p
1600 Baud V27 DIAL1P-P EP
1600 Baud V27 DIAL1P-P - T/2
1600 Baud V27 DIAL1P-P - T/2 EP
1600 Baud V27 Multipoint - T/2
1600 Baud V27 Resync (use with
configuration 15)
1600 Baud V27 Resync EP (use
with configuration 16)
1600. Baud V27 Resync - T/2 (use
with configuration 17)
1600. Baud V27 Resync - T/2 EP
(use with configuration 18)
1600 Baud V27 Echo
1600 Baud V27 Echo EP
1200. Baud DIAL
1200. Baud P- P
1200. Baud V27 DIAL1P-P
1200. Baud V27 DIAL1P-P EP
1200. Baud V27 Multipoint
1200. Baud V27 Resync (use with
configuration 28)
1200 Baud V27 Resync EP (use
wfth configuration 29)

23
27
23
27
21
21

23
23
33
33
27
25

3
3
3
3
3
3

4800.
480.0.
480.0.
4800.
480.0
480.0

25

25

3

21

35

25

S.
9.

20..
21.
22.
23.
24.
25.
26.
27.
28.
29.
30..
31.
32.

4800

480.0.
480.0.
480.0.

233
233
181
181
221
141
141

480.
20 (V.27 Sync
Sequence)
50. (V.27 Sync
Sequence)
708
923
708
923

170.62/3
170.62/3
170.62/3
170.0.
170.0.
NOTE
NOTE
NOTE
NOTE
NOTE
NOTE
1800

1800.
1800

50.
50.

1800.
1800.
180.0.
180.0.
1800.

4800.

265

1800

3

480.0.

50.

180.0.

35

3

480.0.

265

180.0.

23
27
14
10
13
17
11
11

37
37
10

4800.
480.0.
240.0.
2400.
240.0.
240.0.
240.0.

708
923

180.0

11
11
15
13

3
3
3
3
3
3
3
3

15

13

3

10.

180.0.

240.0.

117
943
1158
66
66

180.0.
180.0.
180.0.
180.0.
180.0
1800.

240.0.

281

180.0.

170.

NOTE: Carrier frequency is 1706 2/3 Hz when IRSS (1 P-2P) is a 1 (8-point).
Carrier frequency is 180.0. Hz when IRSS (1 P-2P) is a 3 (8-phase DPSK).

Data Scrambler Selection

• CCITT period 127 self-synchronizing (compatible with
CCITT Recommendations V.27 bis and ter)

The V96P/1 makes available to the user one CCITT V.29
compatible scrambler, five different period 127 scramblers
(and descramblers), and a no-scramble option. These
scramblers provide data transmitted by the V96P/1 with the
degree of randomness necessary to ensure the continued
convergence of all adaptive proceSSeS at the receiver. The
seven possible scrambler configurations that are user software selectable are:

• No scrambler
All scramblers can be used with all modem configurations
listed in the above table except for the cryptographic scrambler which cannot be used in the CCITT V.29 configuration.

MODES OF OPERATION
The V96P/1 has two modes of operation; a training mode
and a data mode. In order for the receiver to correctly decode
the transmitted data, the V96P/1 must detect the presence
of a line signal, adjust the AGC, detect the presence of a
training sequence, recover the baud timing of the transmitter,
phase and frequency lock to the carrier associated with the
received signal, and adapt the equalizer to the amplitude and
delay characteristics of the channel. This learning process
is accomplished most efficiently when the transmitter initiates
a training sequence whenever a new transmitter-receiver

• Period 127 cryptographic
• Period 127 synchronizing
• CCITT period 127 self-sy'nchronizing (compatible with
CCITT Recommendation V.29)
• Period 8,388,60.7 self-synchronizing (compatible with
CCITT Recommendation V.29)
• Period 127 self-synchronizing with 8-bit protection
7-50.

V96P/1

High Speed 9600 BPS Modem

A.

+'V

\"00,I......"iB.S v2.

4800 BPS V27 TER
2400 BPS V27 TER

----------,

15K

\aOOB.\V2.

00 BPS

I
I

VH'/1

\

\

I

10K

I

\

\\

I
I

I

THRESH1
or THRESH2

I
I

-12V

I
I

10-4

L _______ -.J

\

.
w

+5V

\

"a:a:
0

a:

..ffi

\

I

i\

iI
I

10.5

+5V

q

C.

I

20K

>---<>--_

\1

THRESH1 or 2

\

-t2V

10

12

14

16

18

20

22

24

SIGNAL TO NOISE RATIO

Suggested Interface Circuits for Controlling
THRESH1 and THRESH2 Input Lines

MODEM
TRANS.
MinER

I
ENGINEERING
MODEM
CONSOLE

I---

LINE
SIMULATOR

f----

Typical Bit Error Rate Performance

NOISE
SOURCE
GR1381
50 KHZ BW

-

AnENUATOR
HP 3500

IMPAIRMENT
SOURCE
BRADLEY 2A

-

AnENUATOR
HP 3500

f----

NOTE
THE V.568 CONFIGURATION INCLUDES A PERFECTO.3TO 3.4 KHz FILTER
ON THE NOISE SOURCE TO ACHIEVE THE SAME EFFECT IN THIS
CONFIGURATION, THE LEVEL METER USES 15 KHz FLAT WEIGHTING AND
685 dB IS ADDED TO THE MEASURED SIN RATIO

BER Performance Test Set-up

7-51

z=

.---

LEVEL
METER
HP 3555B

1--'--

MODEM
RECEIVER

I
ENGINEERING
MODEM
CONSOLE

High Speed 9600 BPS Modem

V96P/1
connection is made. It is possible to set up the receiver
without a training sequence, but it is a manual mode requiring
considerable user effort. In a training mode, an internal generated pattern is transmitted to the receiver to facilitate synchronization. Ouring the training mode, the data input line to
the receiver is ignored and the output line does not reflect
the state of the data input.

The resync configurations are used for reacquiring synchronization in turnaround operation without having to go through
the normal long training sequence. The resync training
sequences are relatively short and are used for recovering
carrier phase, symbol timing and achieving equalizer convergence without resetting carrier frequency and equalizer
taps.

In the data mode of operation, information o'n the data input
is strobed by the transmitter signal element clock and transmitted to the receiver. The receiver demodulates and decodes
the passband signal and outputs the recovered data on the
output where it is then ready to be strobed by the receiver
signal element clock.

Training Mode-Multipoint
In the V96P/1 modem, two multipoint configurations are provided for 4-wire circuits conforming to M1020 which permit
short training sequences. In these configurations, the first
train Signal must be high to process the short training
sequences; otherwise the receiver will ignore the training
sequence and enter directly into the data mode. The receiver
will enter into the training mode if the first train signal is high
and there is sufficient signal energy.

Request To Send-Ready For Sending
To inttiate transmitter operation in the data or training mode,
the Request to Send input is brought high. If a training mode
is not initiated, the Ready for Sending indicator goes high
within one baud interval and data transmission commences.

For 4-wire circuits which are worse than
2-wire circuits, a long training sequence
rather than the multipoint configuration.
sequences require that the receiver be in
point-to-point configuration.

The mode of the receiver is indicated by the data channel
received line signal detector (0109). For data mode, 0109
is high and the receiver training mode indicator is low.

M1020 and for
should be used
These training
the proper dial/

Training Mode-Manual
If the receiver enters the training mode, the receiver training
mode indicator goes high until the training mode is completed. When training is completed the receiver training mode
Indicator goes low and, if sufficient sigl}al energy is present
on the input line, 0109 goes high, enabling the data mode.

The V96P/1 modem includes two manual configurations in
which the remote modem need not transmit a special training
sequence to the local receiver. In these configurations, the
equalizer tap coefficients for the local receiver must be initialized from an external source. The tap coefficients may be
initialized by controlling three input terms-ICR, ICI and
ICLCP-in synchronization with the Baud Rate Clock.

Training Mode-Dial and Point-To-Point
For dial and point-to-point configurations, the V96P/1 receiver
training is automatically initiated whenever a training sequence
is detected in the received line signal. The training sequence
consists of two phases: Phase 1 causes the training detector
to turn on and also makes a course adjustment of the carrier
frequency variable, which compensates for any frequency
translation due to the channel; Phase 2 is used to converge
the adaptive equalizer, which is part of the V96P/1 structure.

In order to operate the modem in the manual configurations,
both the transmitter and receiver must be set according to
the code shown in Table 1 Modem Configuration. Manual
configuration code octal 30 has a longer synchronizing
sequence than configuration code octal 32, but both synchronizing sequences conform to the CCITT Recommendation V.27. However, neither sequence IS of sufficient
duration to aid in training the receiver.

A short scrambler synchronization sequence follows Phase
2 and is used to generate the success indicator. In order for
training to be successful, the incoming training sequence
must have been generated by a similarly configured transmitter using a compatible training sequence.

Receiver Operation During Loss of Line Signal
When there is no line signal present, all receiver update
relating to the equalizer, carner frequency variable and baud
timing are inhibited and the current values of the equalizer
taps and the carrier frequency variable are retained.

At the receiver, detection of a training sequence requires that
there be sufficient signal energy and that the receiver's carrier frequency variable be within 30 Hz of nominal.

I

Training Resync (V.27 bislter Turnaround)
In a 2-wire half-duplex data communication system, data can
be transmitted in only one direction at any given instant.
Therefore, the modems at the local and remote sites are
required to interchange their roles as the receiver and the
transmitter, respectively. This turnaround operation requires
constant resynchronization to meet CCITT Recommendations for V.27 bis/ter.

DATA QUALITY
The receiver generates an Eye Quality Monitor (EQM) signal
that can be used to determine the equivalent Gaussian signal
to noise ratio of the overall system wtth in approximately ±

7-52

High Speed 9600 BPS Modem

V96PI1

ADDITIONAL CAPABILITIES

2 db. Eye quality is determined by calculating the difference
between the received signal point after equalization and the
transmitted or expected signal point. The receiver output
DEQ2P is a filtered version of this error signal. It is a serial
word clocked by the system bit clock (345.6 kHz or 230.4
kHz, depending on baud rate). Output signal DQGTP is a
gating signal which delineates the eight MSB's of DEQ2P.
The use and interpretation of these binary signals are quite
complex and are dependent on the application and the signal
structure. The user can derive a meaningful interpretation of
the EQM readings by monitoring them while testing the
modem against his performance criteria.

The V96P/1 provides many additional capabilities germane
to data communication system design and implementation.
Capabilnies such as local loopback, tone generation and
detection, external clock facilities, and 300 bps FSK operation are briefly described in the following paragraphs.

Local Loopback Capability
A local loopback option is available for all half duplex and full
duplex modem configurations. The Local Loopback Command (ILB) connects the transmitter's output through a buffer
amplifier to the receiver input, thereby allowing a check of
the local modem. The ILB command squelches the input to
the receiver and loops the analog signal from the transmitter
to the receiver input.

Visual Display of Eye Pattern
A visual indication of the modem's performance can be
obtained by displaying the received baseband signal structure after equalization. This is done by converting the eight
MSB's of the real and imaginary equalized signal points
available on DRERP and DIERP to analog voltages which
are then used to drive the horizontal and vertical sweeps of
an oscilloscope. The resultant display will be a symmetrical
dot pattern of 16 points, 8 points, or 4 points which is a time
representation of the received baseband signal. Any uncompensated distortion over the transmission path will cause
each dot in the pattem to enlarge or otherwise show distorlIOn. A tYPical visual eye pattern of a 4-point display IS shown
in the following diagram.

An internal pattern generator is also incorporated in the
modem which can be used when no modem test set is
available.

Tone Generation And Detection
The transmitter can be used to transmit single frequency
tones for disabling echo suppressors or for system signaling.
Tones that can be transmitted (selected through software
control) are: 1100 Hz, 1300 Hz, 1650 Hz, 1850 Hz, 2025 Hz,
and 2100 Hz. Other tones are also possible and the carner
frequency can be altered by selection of values for a binary
bit stream.

External Data Clock
DISPERSION

The data input to the transmitter can be clocked from an
external source when the external clock is used as a reference input to the data clock's phase locked loop. By applying
an external clock the reference input will cause the transmitter data clock to track the frequency and phase of the reference. The frequency of the reference clock must be wnhin
100 ppm of nominal in order for the receiver's baud timing
to properly track that of the transmitter. The reference clock
can be equal to the nominal data clock frequency or be a
subharmonic of it as long as the frequency tolerance IS
adhered to.

DUE TO GAIN
ERRORS

DISPERSION DUE
TO PHASE ERRORS

DISPERSION AROUND

PROPER posmON DUE
TO COMBINATION OF
RANDOM NOISE, PHASE

CIRCLE REPRESENTS
PROPER POSITION OF
HIGH QUAUTY SIGNAL

ERROR, ANDIOR GAIN
ERROR

Typical Eye Pattern

300 bps FSK Modem Operation
A CCITT T 30 compatible 300 bps FSK modem having characteristics of the
V.21 channel 2 modulation system
can also be configured. The FSK modem is capable of generating the 1100, 1300, 1650 and 1850 Hz tones.

ccm

Success Indicator
A second data qualny indicator is provided for in all configurations except the 1200 baud non-V.27 modes. This signal
provides a rough indication that the training has been successful and that data will be properly received. This "success" output (DSUCP) will go high during the last one to
twenty milliseconds of receiver training, provided training has
been successful. During the data mode (DRTMP low and
0109 high), DSUCP will go high whenever 15 consecutive
data marks or spaces are decoded at the receiver data
output.

D
7-53

V96P/1

High Speed 9600 BPS Modem

SPECIFICATIONS
V96P/1 Specifications
DC Voltages
Voltage
+ Svolt
+12 vo~
-12 vo~

Tolarance

Current (Typical)

Current (Max)

±5%
±S%
±5%

13Sma
40ma
175 ma

<200 ma
< 70ma
<230ma

NOTE: All voltages must have ripple ..0.1

vo~s peak-to-peak.

Envlronmant
Temperature:

Relative Humidity:

Operating: O°C to +6O"C (32 to 14O"F)
Storage: -4O"C to +80"C (-40 to 178°F)
(Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.

Mechanical
Board Structure:
Mating Connector:
Dimensions:

Single PC board with edge connector
100 pin, edge connector, two sided, w~h 0.1 in (2.S4 cm) centers. Recommended Viking 3VHSOIIJNDS or equivalent mating connector.
Width-9.1BB in (23.338 cm) Depth-B.288 in (IS.972 cm)

Weight:

Less than 0.45 Ibs (0.20 kg)

7-54

R48DP
Integral Modems

'1'

Rockwell

R48DP
4800 BPS DATA PUMP MODEM

INTRODUCTION

FEATURES

The Rockwell R48DP is a synchronous serial 4800 bps modem
designed for full-duplex operation over either four-wire dedicated
unconditioned lines or half-duplex operation over the general
switched telephone network.

• User Compatibility:
- CCITT V.27 bislter
• Full-Duplex (4-Wire)
• Half-Duplex
• Programmable Tone Generation
• Dynamic Range -43 dBm to 0 dBm
• Diagnostic Capability
• Equalization:
- Automatic Adaptive
- Compromise Cable (Selectable)
- Compromise Link (Selectable)
• DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Loopbacks
- Local Analog (V.54 Loop 3)
- Remote Analog (Locally Activated)
- Remote Digital (Locally Activated V.54 Loop 2)
• Small Size - 100 mm x 120mm (4.0 x 4.8 inches)
• Low Power Consumption (3 watts, typical)
• Programmable Transmit Output Level
• TTL and CMOS Compatible

The modem satisfies telecommunications requirements specified
in CCITT Recommendations V.27 bislter.
The small size and low power consumption of the modem offer
the user flexibility in creating a 4800 bps modem design customized for specific packaging and functional requirements.
The modem is capable of operating at 4800 and 2400 bps.

R48DP Modem

Document No_ 29200N08
7-55

Data Sheet Order No. MD08
Rev. 1 June 1984

4800 bps Data Pump Modem

R48DP
TECHNICAL SPECIFICATIONS

TRANSMITTED DATA SPECTRUM
If the cable equalizer is not enabled, the transmitter spectrum
is shaped by the following raised cosine filter functions:
1. 1200 Baud. Square root of 90 percent
2. 1600 Baud. Square root of 50 percent
The out-of-band transmitter power limitations meet those
specified by Part 68 of the FCC's rules, and typically exceed
the requirements of foreign telephone regulatory bodies.

TRANSMITTER CARRIER FREQUENCIES
Transmitter Carrier Frequencies
Function
V.27 bis/ter Carrier

Frequency
(Hz ±0.01%)
1800

TONE GENERATION

SCRAMBLERIDESCRAMBLER

Under control of the host processor, the R48DP can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.

The R48DP incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with V.27 bis/ter.

RECEIVED SIGNAL
FREQUENCY TOLERANCE

SIGNALING AND DATA RATES

The receiver Circuit of the R48DP can adapt to received
frequency error of up to ± 10 Hz with less than 0.2 dB degradation in BER performance.

Signaling/Data Rates
Parameter

Specification
(± 0.01 0/0)

Signaling Rate:
Data Rate:

1600 Baud
4800 bps

Signaling Rate:
Data Rate:

1200 Baud
2400 bps

RECEIVE LEVEL
The receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from 0 dBm
to -43 dBm. The received line signal level is measured at the
receiver analog input (RXA).

DATA ENCODING
At 1600 baud, the 4800 bps data stream is encoded into tribits
per CCITT V.27 bis/ter.

RECEIVE TIMING

EQUALIZERS

The R48DP provides a data derived Receive Data Clock
(RDCLK) output in the form of a squarewave. The low to high
tranSitions of this output coincide with the centers of received
data bits. The timing recovery circuit is capable of tracking a
± 0.01 % frequency error in the associated transmit timing
source.

The R48DP provides equalization functions that improve performance when operating over low quality lines.

TRANSMIT LEVEL

At 1200 baud, the 2400 bps data stream is encoded into dibits
per CCITT V.27 bis/ter.

The transmitter output level is accurate to ± 1.0 dB and is
programmable from -1.0 dBm to -15.0 dBm in 2 dB steps.

Cable Equalizers - Selectable compromise cable equalizers
in the receiver and transmitter are provided to optimize performance over different lengths of non-loaded cable of 0.4 mm
diameter.

TRANSMIT TIMING
The R48DP provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
1. Frequency. Selected data rate of 4800 or 2400 Hz (± 0.01 %).
2. Duty Cyc/e.50% ± 1 %

Link Equalizers - Selectable compromise link equalizers in the
receiver optimize performance over channels exhibiting severe
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.

Input data presented on TXD is sampled by the R48DP at the
low to high transition of TDCLK. Data on TXD must be stable
for at least one microsecond prior to the rising edge of TDCLK
and remain stable for at least one microsecond after the rising
edge of TDCLK.

Automatic Adaptive Equalizer - An automatic adaptive
equalizer is provided in the receiver circuit. The equalizer can
be configured as either a T or a Tl2 equalizer.

7-56

4800 bps Data Pump Modem

R48DP
EXTERNAL TRANSMIT CLOCK

RECEIVED LINE SIGNAL DETECTOR (RLSD)

The transmitter data clock (TDCLK) can be phase locked to a
signal on input XTCLK. This input signal must equal the desired
data rate ± 0.01 % with a duty cycle of 50% ± 20%.

For V.27 bislter, RLSD turns on at the end of the training
sequence. If training is not detected at the receiver, the RLSD
oft-to-on response time is 15 ± 10 ms. The RLSD on-to-off
response time for V.27 is 10 ± 5 ms. Response times are
measured with a signal at least 3 dB above the actual RLSD
on threshold or at least 5 dB below the actual RLSD oft threshold.

TRAIN ON DATA
When train on data is enabled, the receiver trains on data in
less than 3.5 seconds.

The RLSD on-to-off response time ensures that all valid data
bits have appeared on RXD.

TURN-ON SEQUENCE

Four threshold options are provided:
1. Greater than -43 dBm (RLSDon)
Less than - 48 dBm (RLSD off)
2. Greater than - 33 dBm (RLSD on)
Less than - 38 dBm (RLSD off)
3. Greater than - 26 dBm (RLSD on)
Less than - 31 dBm (RLSD oft)
4. Greater than -16 dBm (RLSD on)
Less than - 21 dBm (RLSD off)

A total of 8 selectable turn-on sequences can be generated as
defined in the following table:
Turn-On Sequences
CTS
Response Time
(milliseconds)

No.

V.27 bls/ter

1
2
3
4

4800 bps long
2400 bps long
4800 bps short
2400 bps short

708
943
50
67

5
6
7
8

4800 bps long
2400 bps long
4800 bps short
2400 bps short

913
1148
255
272

Comments

NOTE
Performance may be at a reduced level when the received
signal is less than - 43 dBm.

Preceded by
Echo Protector
Tone for lines
using echo
supressors*

A minimum hysteresis action of 2 dB exists between the actual
oft-to-on and on-to-oft transition levels. The threshold levels and
hysteresis action are measured with an unmodulated carrier
signal applied to the receiver's audio input (RXA).

'For short echo protector tone, subtract 155 ms from values
of eTS response time.

MODES OF OPERATION
The R48DP is capable of being operated in either a serial or
a parallel mode of operation.

TURN-OFF SEQUENCE
For V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy.

SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible)
signals to transfer channel data. An optional USRT device
(shown in the Functional Interconnect Diagram) illustrates this
capability.

CLAMPING
Received Data (RXD) is clamped to a constant mark (one)
whenever the Received Line Signal Detector (RLSD) is off.

PARALLEL MODE
The R48DP has the capability of transferring channel data up
to eight bits at a time via the microprocessor bus.

RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
The time between the off-to-on transition of Request-To-Send
(RTS) and the oft-to-on transition of CTS is dictated by the length
of the training sequence and the echo suppressor disable tone,
if used. These times are listed in the Turn-On Sequences table.
If training is not enabled RTS/CTS delay is less than 2 baud
times.

MODE SELECTION
Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the R48DP is configured
by the host processor via the microprocessor bus.

The time between the on-to-oft transition of RTS and the on-tooft transition of CTS in the data state is a maximum of 2 baud
times for all configurations.

7-57

II

R48DP

4800 bps Data Pump Modem
r

I
I

_....
USRT
(OPTIONAL)

I
I
I
I
I
I
I
L __ -.

I....

RTS

h
I~ -

CTS
TXD

SCOPE

TDCLK
;- -XTCLK

RXD

<

EVEX

RLSD

h.

~

,....

RDCLK

EVESVNC
EVECLK

xt

tv

EVE
PATTERN
GENERATOR

TBCLK ;::

I

+12V

MODEM

RBCLK;:::

J

+5V

.

ADDRESS BUS (4) ..

t

I DECODER~CS

(3) ..

POR
IRQ

JV'A

POWER
SUPPLY

,...

DATA BUS (8)

?h..-

GND
-12V

.

READ
WRITE

+5

'.

','

~

 -43 dBm
> -33 dBm
> -26 dBm
>-16dBm

7-64

RlSD Off

< -48
< -38
< -31
< -21

dBm
dBm
dBm
dBm

R48DP

4800 bps Data Pump Modem
R48DP Interface Memory Definitions (Continued)

Mnemonic

Name

Memory
Location

Description

RTS

Request-to-Send

0:7:7

When control bit RTS goes to a one, the modem begins a transmit sequence. It
continues to transmit until RTS is reset to zero, and the turn-off sequence has been
completed. This input bit parallels the operation of the hardware RTS control input.
These inputs are ORed by the modem.

SOlS

Scrambler Disable

0:7:5

When control bit SDIS IS a one, the transmitter scrambler circUit is removed from the
data path.

SEPT

Short Echo
Protector Tone

0:7:0

When control bit SEPT is a one, the echo protector tone is 30 ms long rather than
185 ms.

TBA

Transmitter Buffer
Available

O:E:O

This status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, this bit sets to a one.

TIA

Transmitter
Interrupt Active

0:E:7

This status bit is a one whenever the transmitter is driving IRQ to a zero.

TIE

Transmitter
Interrupt Enable

0:E:2

When the host processor writes a one in control bit TIE, the IRQ line of the hardware
interface is driven to zero when status bit TBA is at a one.

TLVL

Transmitter Level
Field

0:4:2-4

The transmitter analog output level is determined by eight TLVL codes, as follows.
TLVL
0
1
2
3
4
5
6
7

Transmitter Analog Output'
-1
-3
-5
-7
-9
-11
-13
-15

dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm

±1 dB
±1 dB
±1 dB
±1 dB
± 1 dB
± 1 dB
± 1 dB
± 1 dB

• Each step above IS a 2 dB change ±O 2 dB.
TOD

Train-on Data

1 :6:6

When control bit TOD is a one, It enables the traln-on-data algorithm to converge the
equalizer if the signal quality degrades sufficiently. When TOD is a one, the modem still
recognizes a training sequence and enters the force train state. A BER of approximately
10- 3 for 0 5 seconds Initiates train-on data

TPDM

Transmitter Parallel
Data Mode

0:7:2

When control bit TPDM is a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0) rather than the serial hardware data input.

(None)

Transmitter
Configurallon

0:6:0-7

The host processor configures the transmitter by writing a control byte Into the
transmitter configuration register In ItS Interface memory space.
Transmitter Configuration Control Codes

Control codes for the modem transmitter configurations are:
Configuration

Configuration Code (Hex)

V.27 4800 Long
V.27 2400 Long
V.27 4800 Short
V.27 2400 Short
Tone Transmit

22
21
02
01
80

7-65

II

4800 bps Data Pump Modem

R48DP

R48DP Interface Memory Definitions (Continued)
Mnemonic
(None)

Name
Transmitter Data

Memory
Location
0:0:0-7

Description
The host processor conveys output data to the transmitter in the parallel mode by
writing a data byte to the transmitter data register. The data is divided on baud
boundaries, as follows:
NOTE
Data is transmitted bit zero first.

Bits

I

Configuration

7

V.27 4800 bps

Not Used

V.27 2400 bps

Baud 3

6

I4 I

5

Baud 1
Baud 2

I

3

I
I
Baud 1

2

I

I

1

0

Baud 0

I

Baud 0

TSB

Transmitter Setup
Bit

0:E:3

When the host processor changes the transmitter configuration, the host must write a
one in this control bit. TSB goes to a zero when the change becomes effective.

TIDIS

Transmitter Train
Disable

0:7:6

When control bit TIDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay is less than two
baud times.

T2

T/2 Equalizer
Select

1 :7:1

When control bit T2 is a one, an adaptive equalizer with two taps per baud is used.
When T2 is a zero, the equalizer has one tap per baud. The total number of taps
remains the same for both cases.

0:7: 1

When control bit XCEN is a zero, the transmitter timing is established by the external
clock supplied at the hardware input XTCLK, pin 22A.

XCEN

External Clock
Enable

POWER·ON INITIALIZATION

PERFORMANCE

When power is applied to the R48DP, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be configured, and RTS may be activated. If the 5 Vdc power supply
drops below 3.5 Vdc for more than 30 msec, the POR cycle is
generated.

Functioning as a V.27 bislter type modem, the R48DP provides
the user with unexcelled high performance.

BIT ERROR RATES
The Bit Error Rate (BER) performance of the modem is speCified
for a test configuration conforming to that specified in CCITT
recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of -20 dBm as
illustrated.

At POR time the modem defaults to the following configuration:
V.27 4800 bps, short train, T/2, no echo protector tone, serial
data mode, internal' clock, cable equalizers disabled, link
amplitude equalizer disabled, link delay equalizer disabled,
transmitter output level set to -1 dBm ± 1 dB, interrupts disabled, receiver threshold set to - 43 dBm, eye pattern selectable, and train-on-data disabled.

PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz or with a signal-te-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).

POR can be connected to a user supplied power-on-reset signal
in a wire-or configuration. A low active pulse of 3 /Lsec or more
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after POR is removed.

At 4800 bps (V.27 bis/ter), the modem exhibits a bit error rate
of 10-6 or less with a signal-to-noise ratio of 19 dB in the
presence of 15° peak-to-peak phase jitter at 60 Hz.

7-66

R48DP

4800 bps Data Pump Modem
GENERAL SPECIFICATIONS

An example of the BER performance capabilities is given in the
following diagram:

Power

4800 BPS
1127

L'

2400 BPS
V.27
10- 3

Voltage

Tolerance

Current (Max)

+5 Vdc
+12Vdc
-12 Vdc

±5'10
±5'10
±5'10

<700 mA
<20 mA
<80 mA

Note: All voltages must have ripple

:5 0.1

volts peak-to-peak.

Environmental
Parameter
Temperature
Operating
Storage

10-'

Relative Humidity

IIJ

~

Specification
OOC to +60·C (32 to 140·F)
-40·C to +80·C (-40 to 176°F)
Stored in heat sealed antistatic bag
and shipping container
Up to 90% noncondenslng. or a wet
bulb temperature up to 35·C.
whichever is less

a:
~
a:
IIJ
Mechanical

I-

m

Parameter

10-'

10-'
6

8

10

12

14

16

18

20

22

24

26

28

30

Specification

Board Structure

Single PC board With single right
angle header with 64 pins. Burndy
(PI96B32ROOAOOZ1) or equivalent
mating connector.

Dimensions

Wldth-3.94 in. (100 mm)
Length-4.72 in. (120 mm)
Height-OA In. (10.2 mm)

Weight

Less than 3.6 oz. (100g)

SIGNAL-TO NOISE RATIO dB

The BER performance test set-up is shown in the following
diagram:
Worst Case BER Performance
(Back-to-Back)

NOISE
SOURCE
GR1381
50 KHZ BW

MODEM
TRANSMITTER

-

LINE
SIMULATOR

-

IMPAIRMENT
SOURCE
BRADLEY 2A

r--

ATTENUATOR
HP 3500

-

ATTENUATOR
HP 3500

-

L

r--

LEVEL
METER
HP 3552A

-'"'"-

MODEM
RECEIVER

!

I

ENGINEERING
MODEM
CONSOLE

ENGINEERING
MODEM
CONSOLE

NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING

BER Performance Test Set-up

7-07

II

4800 bps Data Pump Modem

R48DP

.156 ± .003

IT,
~~
11~ -=-=: :f:i
I

DIAMETER
6 PLACES

~

R48DP

--1~~~~
-lJ

==-=.=.

II

MALE 64·PIN
DIN CONNECTOR

T

~ .483
~4.725~
:'100 3.275

R48DP Circuit Board Dimensions

7-68

Inches

MM

.119
.156
.483
3.275
3.700
3.937
4.100
4.725

3
4
12
83
94
100
104
120

V27P/1
Integral Modems

'1'

Rockwell

V27P/1
HIGH SPEED 4800 BPS MODEM

INTRODUCTION

FEATURES

The Rockwell V27P/1 is a versatile, high performance, 4800 bps
modem on a single printed circuit board. Being CCITT V.27
compatible, the V27P/1 (with minimal interface circuitry) can
operate on dedicated 2-wlre or 4-wire half-duplex or 4-wire fullduplex lines. The V27P/1 can also operate in half-duplex on the
general switched network.

• Single printed circuit card

• 4800/2400 bps modes
• Full-duplex or half-duplex
• Dedicated or general SWitched network lines operation
• Ultimate user flexibility:
-CCITT V.27 ter, V 27 bis compatible
-Also 300 bps binary signalling per CCITT T.30

Measunng approximately 9.2 inches (23.3 cm) by 6.3 inches
(16.0 cm), the V27P/1 is the smallest full-feature 4800 bps
modem that approaches data communication theoretical performance limits.

•
•
•
•
•
•
•

TTL compatibility
Automatic adaptive equalizer
Analog loopback test cirCUitry
0 to -45 dBm dynamic AGC
LSI signal processing
High reliability
Low power consumption:
- Typically 3.5 watts
• Automatic training sequence for receiver

The V27P/1 meets the tolerances specified in the CCITT V.27
bis (alternate A), V.27 ter and FSK T.30 specifications. In addition,
the V27P/1 can be configured to be functionally compatible with
those enhanced specifications available in the Rockwell V27P
and M48P modem series.

II
Document No. 29220N31
7-69

Data Sheet Order No. 631
March 1983

High Speed 4800 BPS Modem

V27P/1
FUNCTIONAL SPECIFICATIONS
TRANSMIT CONTROLS

HIGH SPEED DATA INPUT

-----I

XMIT

i=:~~~~nER

LINE
SIGNAL

DEVICE

FSK DATA INPUT

------------1

FSK DATA OUTPUT

_-----------1

LOOPBACK

EYE Q U A L l T Y _ - - - - - - ,
RECEIVER
DEVICE

BANDPASS

FILTER.

HIGH SPEED

SQUELCH.

DATA OUTPUT

AGe,

RCV

LINE
SIGNAL

THRESHOLD
SELECT

AECEIVECONTROLS

--4--------------------------------'
V27P/1 Functional Block Diagram

Transmit Carrier and Signalling Frequencies
Carrier Frequency Codex
Compatible QAM:
Carrier Frequency V.27:
Echo Suppression Frequencies:
Signalling Frequencies of T.30:

1706.667 Hz
1800 Hz
2100 Hz
2025 Hz
1850 Hz
1650 Hz
1300 Hz
1100 Hz

tion. At 1200 baud the spectrum is shaped by approximately
a square root of 90 percent raised cosine filter function.

± 0.01 %
± 0.01%

The 1600 and 1200 baud configurations require a usable
bandwidth from 950 Hz to 2650 Hz and 1150 Hz to 2450 Hz
respectively.

± 0.01%
0.01%
0.01%
0.01%
0.01%
± 0.01%

±
±
±
±

Data Encoding
At 1600 baud the data stream is divided into groups of three
bits (tribits). The data rate of 4800 bps may use either an Spoint QAM structure or 8-phase structure. Encoding of the
tribits in the 8-phase structure are per CCITT Recommendation V.27 ter.

Received Signal Frequency Tolerance
The receiver can receive frequency errors of up to ± 10
Hz with less than a 0.2 dB degradation in Bit Error Rate
performance.

At 1200 baud the data stream is divided into groups of two
bits (dibits). The data rate of 2400 bps uses a 4-phase data
structure. Encoding of the dibits may be per the fallback rate
of CCITT Recommendation V.27 bis and ter (same as V.26A)
or V26B depending on the selected configuration.

Data Signalling and Modulation Rate
At 1600 baud:
Signalling RateData RateAt 1200 baud:
Signalling RateData Rate-

1600 baud ± 0.01%
4800 bps ± 0.01 %

Turn-on, Turn-off Sequences

1200 baud ± 0.01 %
2400 bps ± 0.01 %

The V27P/l turn-on sequences are compatible with CCITT
Recommendations V.27 bis (alternate i), V.27, and Rockwell
M48P modem specifications.

At 1600 baud the transmitted spectrum is shaped by approxi(11ately a square root of 50 percent raised cosine filter func-

The turn-off sequences for all V.27 modes (except the 1600
baud rate manual V.27 mode) consists of 5 to 10 millisec-

Transmitted Data Spectrum

7-70

High Speed 4800 BPS Modem

V27P/1
onds of remaining data followed by continuous scrambled 1's
followed by no transmission energy. The period of no transmission energy is provided by turning off the transmitter key
signal for a recommended duration of 20 milliseconds.

shown where P1 and P2 are the most significant octal digit and P3 through P5
establish the least significant octal digit
shown in the chart.

The turn-off sequences for all non-V.27 modes consists of
4 to 7 milliseconds of remaining data followed by a period of
no transmission energy.

IRC (1 P-5P):

Receiver Configuration Inputs 1 through 5.
These five bits establish the octal code
shown where P1 and P2 are the most significant octal digit and P3 through P5
establish the least significant octal digit
shown in the chart.

IRSS (1 P-2P),
ITSS (1 P-2P):

Receiver Signal Structure and Transmitter
Signal Structure. Where P1 and P2 establish an octal code of 0, 1, 2, or 3. They
define the signal structures as follows:
1 selects 8 point QAM
3 selects DPSK as:
a-phase at 1600 baud
4-phase at 1200 baud

Ready For Sending Response Times
The Ready For Sending response time to a Request To Send
is determined by the configuration selected and its corresponding training time. In Table 1 the Training Times are
shown in milliseconds. Note, however, that the 1600 baud
manual CCID configurations actually specify the synchronizing sequence timing per CCID V.27 rather than the training
time. Also note the following abbreviations.

ITC (1P-5P):

Transmitter Configuration Inputs 1 through
5. These five bits establish the octal code

V27P/1 Configurations

No.

Configuration

Transmitter
ITC (IP-5P)
(Octal Code)

Receiver
IRC (IP-5P)
(Octal Code)

22
22
36
20
20
32

22
36
22
20
32
30

Signal
Structure
IRSS (1 P-2P)
ITSS (1 P-2P)
(Octal Code)

Data
Rate
(bps)

Training
Time
(maec)

Carrier
Frequency
(hz)

1,3
1,3
1,3
1,3
1,3
3

4800
4800
4800
4800
4800
4800

NOTE
NOTE
NOTE
NOTE
NOTE
1800

1.
2.
3.
4.
5.
6.

1600
1600
1600
1600
1600
1600

7.

1600 Baud Manual CCID

30

30

3

4800

1600 Baud V27 DIAUP-P
1600 Baud V27 DIAUP-P EP
1600 Baud V27 DIAUP-P - T/2
1600 Baud V27 DIAUP-P - T/2 EP
1600 Baud V27 Multipoint - T/2
1600 Baud V27 Resync (use with
configuration 8)
1600 Baud V27 Resync EP (use
with configuration 9)
1600 Baud V27 Resync - T/2 (use
with configuration 10)
1600 Baud V27 Resync - T/2 EP
(use with configuration 11)
1200 Baud DIAL
1200 Baud P-P
1200 Baud V27 DIAUP-P
1200 Baud V27 DIAUP-P EP
1200 Baud V27 Multipoint
1200 Baud V27 Resync (use with
configuration 19)
1200 Baud V27 Resync EP (use
with configuration 20)

23
27
23
27
21
21

23
23
33
33
27
25

3
3
3
3
3
3

4800
4800
4800
4800
4800
4800

181
181
221
141
141
20 (Sync
Sequence)
50 (Sync
Sequence)
708
923
708
923
50
50

25

25

3

4800

265

1800

21

35

3

4800

50

1800

25

35

3

4800

265

1800

14
10
13
17
11
11

10
10
11
11
15
13

3
3
3
3
3
3

2400
2400
2400
2400
2400
2400

170
117
943
1158
66
66

1800
1800
1800
1800
1800
1800

15

13

3

2400

281

1800

8.
9.
10.
11.
12.
13.
14.
15.
16
17
18.
19.
20.
21.
22.
23.
Note:

Baud
Baud
Baud
Baud
Baud
Baud

DIAL, CCID DIAL
DIAL - T/2
DIAL Slow
P- P
P-P - T/2
Manual CCID

Carrier frequency is 1706 213 Hz when IRSS (1 P-2P) is a 1 (8-point).
Carner frequency IS 1800 Hz when IRSS (1 P-2P) is a 3 (8-phase DPSK).

7-71

1800
1800
1800
1800
1800
1800
1800

V27P/1

High Speed 4800 BPS Modem

Received Line Signal Detector (0109)

.IV

A.

The time response of the Received Line Signal detector circuit (0109) is a function of the length of the received turn-on
sequence. Circuit 0109 tums on after synchronizing is completed and prior to user data appearing on the received
output line. 0109 turns on for approximately 2 milliseconds
after the echo protect tone disappears in the V27EP configurations (No.9, 11, 14, 16, 20 and 23 of the V27P/l Configuration Chart).

1----- -

11K

I
I

---j

I
I

VI7P/l

I
I

10K

I
I

I

I

I

I

I

THAISH,

I

or THREBHI

For non-CCITT configurations (No.1, 2 and 3 in the table on
page 3), 0109 momentarily goes on at the beginning of the
synchronizing sequence.

II
I _______ ..JI
L
-1.V

When no synchronizing signal is detected at the receiver,
0109 turns on in 5 to 15 milliseconds for an applied signal
greater than 3 dB above the turn on threshold. If training Is
not enabled at the receiver, 0109 turns on in 5 to 15
milliseconds.

+IV

B.
.IV

.OK

"--_"AA ___

THAEIH1 or"

Three threshold options are provided:
1) Greater than -43 dBm:
Less than -48 dBm:

0109 ON
0109 OFF

2) Greater than -26 dBm:
Less than - 31 dBm:

0109 ON
0109 OFF

3) Greater than -16 dBm:
Less than -21 dBm:

0109 ON
0109 OFF

c.

.IV

.OK

'>--~-. THAE'HI

Of'

-1'V

The three threshold options are controlled by the condition
of the THRESHl and THRESH2 control lines as Indicated
below.

dB
-43
-26
-16

LEVEL
dBm ON
dBm ON
dBm ON

THRESHl
Open Circuit
Open Circuit
o to -0.5V

Suggeeted Interface Circuits for ContrOlling
THRESH1 and THRESH2 Input Lines

THRESH2
Open Circuit
Oto -0.5V
Open Circuit

Data Scrambler Selection

When the received signal drops 5 dB below the 0109 turn
off threshold, 0109 will turn off In 5 to 15 milliseconds. The
condition of 0109 between the selected turn on and turn off
thresholds Is not specified except that a hysteresis action of
greater than 2 dB exists between the off-to-on and on-to-off
transition levels.

The V27P/l makes available to the user one CCITT V.29
compatible scrambler, five different period 127 scramblers
(and descramblers), and a no scramble option. These scramblers provide data transmitted by the V27P/l with the degree
of randomness necessary to ensure the continued convergence of all adaptive processes at the receiver. The seven
possible scrambler configurations that are user software
selectable are:

Recommended circuits to control THRESHl and THRESH2
Input Interface lines are shown In diagrams (A, B and C).

The V27P/l Is thoroughly tested to guarantee Bit Error Rate
(BER) performance under test conditions equivalent to CCITT
Recommendation V.28. The test set-up used by Rockwell is
shown In the BER Performance Test Set-up diagram.

• Period 127 cryptographic
• Period 127 synchronizing
• CCITT period 127 self synchronizing (compatible with
CCITT Recommendation V.27)
• Period 8,388,807 self synchronizing (compatible with
CCITT Recommendation V.29)
• Period 127 self synchronizing with 8-blt protection
• CCITT period 127 self synchronizing (compatible with
CCITT Recommendations V.27 bls and ter)
• No scrambler

The resutts of these BER performance tests are shown In the
Typical Bit Error Rate Performance diagram.

All scramblers can be used with all modem configurations
listed In the table on page 3.

Bit Error Rat••

7-72

High Speed 4800 BPS Modem

V27P/1

NOISE
SOURCE
GR1381
50 KHZ BW

MODEM
TRANSMinER

LINE
SIMULATOR

r-

I

r-

IMPAIRMENT
SOURCE
BRADLEY 2A

-

AnENUATOR
HP 3500

r-

AnENUATOR
HP 3500

~

r--

2:

r-'--

LEVEL
METER
HP 3555B

MODEM
RECEIVER

I

NOTE
THE V.5IB CONFIGURATION INCLUOESA PERFECTO 3 TO 3.4 KHz FILTER
ON THE NOISE SOURCE TO ACHIEVE THE SAME EFFECT IN THIS
CONFIGURATION. THE LEVEL METER USES 16 KHz FLATWEIGHTING ANO
I B6 dB IS ADDED TO THE MEASURED SIN RATIO

ENGINEERING
MODEM
CONSOLE

ENGINEERING
MODEM
CONSOLE

BER Perfonnance Test Set-up

,

.

30DBPS

/

2400 BPS V27 TER

without a training sequence, but it is a manual mode requiring
considerable user effort. In a training mode, an internally
generated pattern is transmitted to the receiver to facilitate
synchronization. During the training mode, the data input line
to the receiver is Ignored and the output line does not reflect
the state of the data input.

4800 BPS V27 TEll

I

\

1\

In the data mode of operation, information on the data input
is strobed by the transmitter signal element clock and transmitted to the receiver. The receiver demodulates and decodes
the passband signal and outputs the recovered data on the
output where it is then ready to be strobed by the receiver
signal element clock.

\

,

\

., , .

6

B

10

Request To Send-Ready For Sending

12

14

16

18

To initiate transmitter operation in the data or training mode,
the Request to Send input is brought high. If a training mode
is not initiated the Ready for Sending indicator goes high
within one baud interval and data transmission commences.

20

The mode of the receiver is indicated by the data channel
received line signal detector (D109). For data mode, D109
is high and the receiver training mode indicator is low.

Typical Bit Error Rate Performance

MODES OF OPERATION

If the receiver enters the training mode, the receiver training
mode indicator goes high until the training mode is completed. When training is completed the receiver training mode
indicator goes low and, if sufficient signal energy is present
on the Input line, D109 goes high, enabling the data mode.

The V27P/1 has two modes of operation; a training mode
and a data mode. In order for the receiver to correctly decode
the transmitted data the V27P/1 must detect the presence
of a line signal, adjust the AGe, detect the presence of a
training sequence, recover the baud timing of the transmitter,
phase and frequency lock to the carrier associated with the
received Signal, and adapt the equalizer to the amplitude and
delay characteristics of the channel. This learning process
is accomplished most efficiently when the transmitter initiates
a training sequence whenever a new transmitter-receiver
connection is made. It is possible to set up the receiver

Training Mode-Dial and Point-To-Polnt
For dial and point-to-point configurations, the V27P/1 receiver
training is automatically initiated whenever a training sequence
is detected in the received line signal. The training sequence
consists of two phases: Phase 1 causes the training detector
to turn on and also makes a course adjustment of the carrier

7-73

V27P/1

High Speed 4800 BPS Modem

frequency variable which compensates for any frequency
translation due to the channel; Phase 2 is used to converge
the adaptive equalizer which is part of the V27P/1 structure.

the code shown in Table 1. Manual configuration code octal
30 has a longer synchronizing sequence than configuration
code octal 32, but both synchronizing sequences conform
to the CCITT Recommendation V.27. However, neither sequence is of sufficient duration to aid in training the receiver.

.A short scrambler synchronization sequence follows Phase
2 and is used to generate the success indicator. In order for
training to be successful, the incoming training sequence
must have been generated by a similarly configured transmitter using a compatible training sequence.

Receiver Operation During Loss of Line Signal
When there is no line signal present, all receiver update
relating to the equalizer, carrier frequency variable and baud
timing are inhibited and the current values of the equalizer
taps and the carrier frequency variable are retained.

At the receiver, detection of a traimng sequence requires that
there be sufficient signal energy and that the receiver's carrier frequency variable be wnhin 30 Hz of nominal.

Training Resync (V.27 bis/ter Turnaround)

DATA QUALITY

In a 2-wire half duplex data communication system, data can
be transmitted in only one direction at any given instant.
Therefore, the modems at the local and remote sites are
required to interchange their roles as the receiver and the
transmitter respectively. This turnaround operation requires
constant resynchronization to meet CCITT Recommendations for V.27 bis/ter.

The receiver generates an Eye Quality Monitor (EQM) signal
that can be used to determine the equivalent Gaussian signal
to noise ratio of the overall system within approximately ±
2 db. Eye quality is determined by calculating the difference
between the received signal point aiter equalization and the
transmitted or expected signal point. The receiver output
DEQ2P is a filtered version of this error signal. It is a serial
word clocked by the system bit clock (345.6 KHz or 230.4
KHz, depending on baud rate). Output signal DQGTP is a
gating signal which delineates the eight MSB's of DEQ2P.
The use and interpretation of these binary signals are quite
complex and are dependent on the application and the signal
structure. The user can derive a meaningful interpretation of
the EQM readings by monitoring them while testing the
modem against his pe.rformance criteria.

The resync configurations are used for reacquiring synchronization in turnaround operation without having to go through
the normal long tralmng sequence. The resync training
sequences are relatively short and are used for recovering
carrier phase, symbol timing and achieving equalizer convergence without resetting carrier frequency and equalizer
taps.

Training Mode-Multipoint

Visual Display of Eye Pattern

In the V27P/1 modem, two multipoint configurations are provided for 4-wlre circuits conforming to M1020 which permit
short training sequences. In these configurations, the first
train signal must be high to process the short training
sequences; otherwise the receiver will ignore the training
sequence and enter directly into the data mode. The receiver
will enter into the training mode if the first train signal is high
and there is sufficient signal energy.

A visual indication of the modem's performance can be
obtained by displaying the received baseband signal structure aiter equalization. This is done by converting the eight
MSB's of the real and imaginary equalized signal points
available on DRERP and DIERP to analog voltages which
are then used to drive the horizontal and vertical sweeps of
an oscilloscope. The resultant display will be a symmetrical
dot pattern of 16 points, 8 points, or 4 points which is a time
representation of the received baseband signal. Any uncompensated distortion over the transmission path will cause
each dot in the pattern to enlarge or otherwise show distortion. A typical visual eye pattern of a 4 point display is shown
in the following diagram.

For 4-wire circuits which are worse than M1020 and for
2-wire circuits, a long training sequence should be used
rather than the' multipoint configuration,' These training
sequences require that the receiver be in the proper diaV
point-to-point configuration.

DISPERSION

Training Mode-Manual

DUE TO GAIN
ERRORS

The V27P/1 modem includes two manual configurations in
which the remote modem need not transmit a special training
sequence to the local receiver. In these configurations, the
equalizer tap coefficients for the local receiver must be initialized from an external source. The tap coefficients may be
initialized by controlling three input terms-ICR, ICI and
ICLCP-in synchronization with the' Baud Rate Clock.

DISPERSION DUE
TO PHASE ERRORS

DISPERSION AROUND

PROPER POSITION DUE
PROPER POSITION OF

TO COMBINATION OF
RANDOM NOISE, PHASE
ERROR, ANDIOR GAIN

HIGH QUALITY SIGNAL

ERROR

CIRCLE REPRESENTS

In order to operate the modem in the manual configurations,
both the transmitter and receiver must be set according to

Typical Eye Pattern

7-74

High Speed 4800 BPS Modem

V27P/1
,
Success IndICator

Tone Generation And Detection
The transmitter can be used to transmit Single frequency
tones for disabling echo suppressors or for system signaling.
Tone that can be transmitted (selected through software control) are: 1100 Hz, 1300 Hz, 1650 Hz, 1850 Hz, 2025 Hz, and
2100 Hz. Other tones are also possible. The carrier frequency can be altered by selection of values for a binary bit
stream.

A second. data quality indicator is provided for in all configurations except the 1200 baud non-V.27 modes. This signal
provid~s a rough indication that the training has been successful and that data will be properly received. This "success" output (DSUCP) will go high during the last one to
twenty milliseconds of receiver training, provided training has
been successful. During the data mode (DRTMP low and
0109 high), DSUCP will go high whenever 15 consecutive
data marks or spaces are decoded at the receiver data
output.

External Data Clock
The data input to the transmitter can be clocked from an
external source when the external clock is used as a reference input to the data clock's phase locked loop. By applying
an external clock the reference input will cause the transmitter data clock to track the frequency and phase of the relerence. The frequency of the reference clock must be within
100 ppm of nominal in order for the receiver's baud timing
to properly track that of the transmitter. The reference clock
can be equal to the nominal data clock frequency or be a
subharmonic of it as long as the frequency tolerance is
adhered to.

ADDITIONAL CAPABILITIES
The V27P/1 provides many additional capabilities germane
to data communication system design and implementation.
Capabilities such as local loopback, tone generation and
detection, external clock facilities, and 300 bps FSK operation are briefly described in the following paragraphs.

300 bps FSK Modem Operation

Local Loopback Capability

A CCITT T.30 compatible 300 bps FSK modem having characteristics of the CCITT V.21 channel 2 modulation system
can also be configured. The FSK modem is capable of generating the 1100, 1300, 1650 and 1850 Hz tones.

A localloopback option is available for all half duplex and full
duplex modem configurations. The Local Loopback Command (ILB) connects the transmitter's output through a buffer
amplifier to the receiver input, thereby allowing a check of
the local modem. The ·ILB command squelches the input to
the receiver and loops the analog signal from the transmitter
to the receiver input.
An internal pattern generator is also incorporated in the
modem which can be used when no modem test set is
available.

SPECIFICATIONS
V27P/1 Specifications
DC Voltages
Voltsge
+ 5 volt
+12 voH
-12 voH

Tolerance

Current (Typlcsl)

Current (Max)

±5%
±5%

135ma
40 ma
175ma

<200 ma
< 70ma
<230 ma

±5%

Note: All voltages must have ripple ... 0.1 volts peak-to-peak.
Environment
Temperature:

Relative Humidity:

Operating: O'C to +60'C (32 to 14O'F)
Storage: -4O'C to +8O"C (-40 to 176"F)
(Stored in heat sealed antistatic bag and shipPing container)
Up to 90% noncondenslng, or a wet bulb temperature up to 35'C, whichever is less.
Mechanical

Boerd Structure:
Mating Connector:
Dimensions:
Weight:

Single PC board with edge connector
100 pin, edge connector, two sided, wtth 0.1 in (2.54 cm) centers Recommended Viking 3VH501IJND5 or equivalent mating connector.
Width-9.188 in (23.338 cm) Depth-6.288 in (15.972 cm)
Less than 0.45 Ibs (0.20 kg)

7-75

II

R1212DS
Integral Modems

'1'

Rockwell

R1212DS
MODEM DEVICE SET
(212A COMPATIBLE)
PRODUCT PREVIEW

INTRODUCTION

FEATURES

The R1212DS is a high performance 1200/300 bps, full duplex
modem device set. Utilizing state-of-the-art LSI and signal processing technology, the R1212DS provides the user with
enhanced performance and reliability.

•
•
•
•
•
•

The R1212DS is ideal for designing products for data transmission over the 2-wire dial-up telephone network. cCln V.22 A,
B, Bell 212A and 103 compatible, the R1212DS can handle virtuallyall applications for full duplex 1200 bps (synchronous or
asynchronous) and 0 to 300 bps asynchronous data transmission over the switched network.

•
•
•

Test features such as local analog loopback, remote digital loopback, and a self test configuration offer the user flexibility in
creating a 1200 bps modem design customized for specific
packaging and functional requirements.

•
•

For detail information, reference R1212 Modem Device Set
Manual Order No. 652.

•
•
•
•

Product is available NOW.
•

Bell 212A and 103 Compatible
cCln V.22 A, B Compatible
Operation-2-Wire Full-Duplex
Adaptive and Fixed Compromise Equalization
Outstanding Performance Over Unconditioned Lines
Test Configurations
-Local Analog Loopback
-Remote Digital Loopback
-Self Test
Busy Out Option
Auto/Manual Answer
Auto/Manual Dial
-Tone or Pulse Dial
Synchronous-1200 bps, 600 bps Fallback
Asynchronous-1200 bps, 600 bps ± .01 %, 0-300 bps
-Character length 8, 9, 10, or 11 bits
Eye Pattern Generation Capability
Power Consumption-3 Watts typical
Power Requirements: + 5 Vdc, ± 12 Vdc
Guard Tone Generation (CCln Configurations)
-Selectable 1800 Hz and 550 Hz
3 Integrated Circuits Provide Total Modem Functions

I·

Document No. 29220N59
7-76

Product Preview Order No. 659
October 1984

R2424DS
Integral Modems

'1'

Rockwell

R2424DS
MODEM DEVICE SET
2400 BPS FULL DUPLEX MODEM
PRODUCT PREVIEW

INTRODUCTION

FEATURES

The Rockwell R2424DS is a high performance 2400/12001
300 bps lull duplex modem device set. Utilizing state-ol-the-art
VLSI and signal processing technology, the R2424DS provides
the user with enhanced performance and reliability.

•
•
•
•
•
•
•

The R2424DS is ideal for data transmission over the 2-wire
dial-up telephone network. cCln V.22 bis, V.22 A, B, Bell 212A
and 103 compatible, the R2424DS can handle virtually all applications for full-duplex 2400 and 1200 bps fallback (synchronous
and asynchronous) and 0 to 300 bps asynchronous data
transmission over the switched network.

•
•

Test features such as local analog loopback, remote digital loopback, and a self test configuration offer the user flexibility in
creating a 2400/1200 bps modem design customized for specific
packaging and functional requirements.

•
•

For detail information, reference R2424 Modem Device Set
Manual Order No. 651.

•
•
•

Product Is available NOW.
•

Document No. 29220N60
7-77

cCln V.22 bis Compatible
CCITT V.22 A, B Compatible
Bell 212A and 103 Compatible
Operation-2-Wire Full-duplex
Adaptive and Fixed Compromise Equalization
Outstanding Performance Over Unconditioned Lines
Test Configurations
-Local Analog Loopback
-Remote Digital Loopback
-Self Test
Auto/Manual Answer
Auto/Manual Dial
-Tone or Pulse Dial
Synchronous-2400 bps, 1200 bps, 600 bps ± .01%
Asynchronous-2400 bps, 1200 bps, 600 bps + 1%, - 2.5%
0-300 bps
-Character length 8, 9, 10, or 11 bits
Eye Pattern Generation Capability
Power Consumptlon-3 Watts typical
Guard Tone Generation (CCITT Configurations)
-Selectable 1800 Hz and 550 Hz
3 Integrated circuits provide total modem functions

Product Preview Order No. 660
October 1984

R24DP
Integral Modems

'1'

Rockwell

R24DP
2400 BPS MODEM
(201C COMPATIBLE)
PRODUCT PREVIEW

INTRODUCTION

FEATURES

The R24 Data Pump is a synchronous, serial, 2400 bps modem
designed for operation over dedicated unconditioned lines or
with the general switched telephone network with appropriate
line terminations, such as a Data Access Arrangement or
transformer, provided externally.

• Configurations
-Bell 201C
-CCITI V.26
• Half-Duplex (2-Wire), Full-Duplex (4-Wire)
• Ideal for Point-to-Point Applications
• Plug Compatible with Rockwell R96DP, R48DP, R96FT
Modems
• Programmable Tone Generation
• Dynamic Range: - 43 dBm to 0 dBm
• Equalization
-Automatic Adaptive
-Compromise Cable (Selectable)
-Compromise Link (Selectable)
• DTE Interface: Two Alternate Ports
-Microprocessor Bus
-CCITI V.24 (RS-232-C Compatible)
• Diagnostics
-Provides Telephone Line Quality Monitoring Statistics
• Programmable Transmit Output Level
• Loopbacks
-Local Analog
-Remote Analog
-Remote Digital
• Power Consumption-2.5 Watts typical
• TTL and CMOS Compatible

The R24DP satisfies the telecommunications requirements
specified in CCITT V.27 bis/ter and Bell 208 AlB for 4800 bps
modems.
The R24DP is optimized for point-to-point applications and
suitable for network applications where the optimum in data
transfer is needed. Its small size (100 mm by 120 mm) and low
power consumption (2.5W typical) offer the user flexibility in
creating a 2400 bps modem customized for specific packaging
and functional requirements.
Data can be transferred to and from the modem either serially
over the CCITT V.24 interface or in parallel over the microprocessor bus interface.
The R24DP is a member of Rockwell's family of plug compatible modems.
Product availability is APRIL, 1985.

SPECIFICATIONS
POWER REQUIREMENTS
+5 Vdc ±5% <500ma
+12 Vdc ±5% <20ma
-12 Vdc ±5% <80ma
ENVIRONMENTAL
Temperature: Operating 0 to 60°C
Storage - 40 to 90°C
Relative Humidity: Up to 90%, noncondensing, or a wet bulb
temperature up to 35°C, whichever is less.

Document No. 29220N61
7-78

Product Preview Order No. 661
October 1984

R1212
Integral Modems

'1'

Rockwell

R1212
1200 BPS FULL-DUPLEX MODEM

INTRODUCTION

FEATURES

The Rockwell R1212 is a high performance full-duplex 1200 bps
modem. Using state-of-the-art VLSI and signal processing
technology, the R1212 provides the user with enhanced performance and reliability on a single printed circuit board of less than
22 square-inches-overall size.

•
•
•
•
•

The R1212 modem is ideal for data transmission over the 2-wire
dial-up telephone network. The direct-connect, auto dial/answer
features are specifically designed for remote and central site
computer applications. The bus interface allows easy integration into a personal computer, box modem, microcomputer,
terminal or any other communications product that demands the
utmost in reliability and performance.

•
•
•

The added test features, such as local analog loopback, remote
digital loopback, and a self-test function, offer the user flexibility in creating a 1200 bps modem design customized for specific
packaging and functional requirements.

•
•

Being CCITT V.22 A, B compatible, as well as Bell 212A and
103 compatible, this modem fits any-application for full-duplex
1200 bps (synchronous and asynchronous) and 0 to 300 bps
asynchronous data transmission over the general switched
telephone network.

•
•
•
•

CCITT V.22 A, B Compatible
Bell 212A and 103 Compatible
Synchronous: 1200 bps, 600 bps ±0.01%
Asynchronous: 1200 bps, 600 bps + 1%, - 2.5%, 0-300 bps
-Character length 8, 9, 10, or 11 bits
DTE Interface
-Functionally: Microprocessor Bus (Configuration/Control)
and RS-232-C Interface (Data/Control)
-Electrically: TTL Compatible
Operation: 2-wire full-duplex
Adaptive and Fixed Compromise Equalization
Test Configurations:
-Local Analog Loopback
-Remote Digital Loopback
-Self Test
Auto/Manual Answer
Auto/Manual Dial:
-Tone or Pulse Dial
Power Consumption: 3 Watts Typical
Power Requirements: + 5 Vdc, ± 12 Vdc
Plug-compatible member of new Rockwell modem line
Two Versions: R1212DC (Direct Connect) with FCC approved
DAA Part 68 Interface and R1212M (Module) without DAA

R1212 Full-Duplex Modem

Document No. 29200N10
7-79

Data Sheet Order No. MD10
Rev. 2 July 1984

R1212

1200 bps Full-Duplex Modem

TECHNICAL SPECIFICATIONS

3. DTMF Tones: The R1212 generates dual tone'multifrequency tones. When the transmission of DTMF tones are
required, the CRQ and DTMF bits must be set to a 1. (see
Interface Memory). When in this mode, the specific DTMF
tones generated are decided by loading the dial digit register
with the appropriate digit as shown in the following table:

TRANSMITTER CARRIER AND SIGNALING
FREQUENCIES
Transmitter Carrier and Signaling
Frequencies Specifications
Specification
(Hz ±O.OI%)
Frequency
1200
V.22 low channel, Originate Mode
2400
V.22 high channel, Answer Mode
Bell 212A high channel Answer Mode
2400
Bell 212A low channel Originate Mode
1200
Bell 103/113 Originating Mark
1270
Bell 103/113 Originating Space
1070
Bell 103/113 Answer Mark
2225
Bell 103/113 Answer Space
2025

BCD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

TONE GENERATION
The specifications for tone generation are as follows:
1. Answer Backtones: The R1212 generates echo disabling
tones both of the CCITT and Bell versions, as follows:
a. CCITT: 2100 Hz ± 15 Hz.
b. Bell: 2225 Hz ± 10 Hz.
2. Guard Tones: If GTS is low, an 1800 Hz guard tone frequency
Is selected; if GTS if high, a 553.846 Hz tone Is employed.
In accordance with the CCITT V.22 Recommendation, the
level of transmitted power for the 1800 Hz guard tone Is
6 ± 1 dB below the level of the data power in the main
channel. The total power transmitted to the line is the same
whether or not a guard tone is enabled. If a 553.846 Hz guard
is used, its transmitted power is 3 ± 1 dB below the level of
the main channel power, and again the overall power transmitted to the line will remain constant whether or not a guard
tone is enabled. The device accomplishes this by reducing
the main channel transmit path gain by .97 dB and 1.76 dB
for the cases of the 1800 Hz and 553.846 Hz guard tones
respectively.

Operating Mode
V.22:
(Alternative A)
Mode i
Mode iii
(Alternative B)
Mode i
Mode iii
Mode Ii

a
a

1
1
1
1

0
0
1
1
0
0
1
1
0

a

1
1
0

a

1
1

0
1
0
1
0
1
0
1
0
1

a

1

a
1

a

1

0
1
2
3
4

5
6
7
8
9

* (B)
Spare
Spare (C)
Spare (0)
#
Spare (F)

Tone
941
697
697
697
770
770
770
852
852
852
941
697
770
852
941
941

Pairs
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1633
1633
1633
1477
1633

TONE DETECTION
The R1212 can detect tones in the 340 ±5 Hz to 640 ±5 Hz
band.
Detection Level: 0 to - 45 dBm
Response Time: 17 ± 2 ms

SIGNALING AND DATA RATES
The signaling and data rates for the R1212 are defined in the
table below:

Signaling and Data Rates
Signaling Rate (Baud)

Data Rate

600

1200 bps ±0.01% Synchronous

600

600 bps ±0.01 % Synchronous

600
600

1200 bps ±0.01 % Synchronous
600 bps ±0.01 % Synchronous

600

1200 bps Asynchronous
8, 9, 10, or 11 Bits Per Character
600 bps Asynchronous
8, 9, 10, or 11 Bits Per Character

Mode iv

Bell 212A

0
0
0
0
1
1
1
1
0
0

Dial Digits/Tone Pairs
Dial Digits

1200 bps ±0.01%
SynchronouslAsychronous
o to 300 Bps Asynchronous

600

o to 300

7-80

1200 bps Full-Duplex Modem

R1212
DATA ENCODING

The R1212DC transmit level is strapped in the permissive mode
so that the maximum output level is -10 dBm ± 1.0 dBm.

The specifications for data encoding are as follows:
1. 1200 bps (V. 22 and 8eI/212A). The transmitted data is divided
into groups of two consecutive bits (dibits) forming a four-point
signal structure.
2. 600 bps (V.22). Each bit is encoded as a phase change
relative to the phase preceding signal elements.

TRANSMIT TIMING
The R1212 provides a Transmit Data Clock (TDCll<) output with
the following characteristics:
1. Frequency. Selected data rate of 1200 or 600 Hz (± 0.01 %).
2. Duty Cycle. 50 ± 1%.

EQUALIZERS
The R1212 provides equalization functions that improve performance when operating over low quality lines.

Transmit Data (TXD) must be stable during the one microsecond
periods immediately preceding and following the rising edge of
TDClK.

Automatic Adaptive Equalizer-An automatic adaptive
equalizer is provided in the receiver circuit for V.22 and Be1l212A
configurations.

CLAMPING
The following clamp is provided with the R1212:

Fixed Compromise Equalizer-Compromise equalization is
provided in the transmitter.

1. Receive Data (RXD). RXD is clamped to a constant mark (1)

TRANSMITTED OAT A SPECTRUM

whenever RlSD is off.

After making allowance for the nominal specified compromise
equalizer characteristic, the transmitted line signal has a frequency spectrum shaped by the square root of a 75 percent
raised cosine filter. Similarly, the group delay of the transmitter
output is within ± 100 microseconds over the frequency range
900 to 1500 Hz (lOW channel) and 2100 to 2700 Hz (high
channel).

RECEIVED LINE SIGNAL DETECTOR
The high and low channel thresholds are greater than - 45 dBm
(RlSD on) and less than - 48 dBm (RlSD off) for V.22 and Bell
2\12A configurations.

DATA SET READY
The on condition of the R1212 output Data Set Ready (DSR)
indicates that the modem is in the data transfer state. The off
condition of DSR is an indication that the DTE is to disregard
all signals appearing on the interchange circuits-except the calling indicator and the test signal. DSR will switch to the off state
when in test state. The on condition of DSR indicates the
following:

SCRAMBLER/DESCRAMBLER
The R1212 incorporates a self-synchronizing scrambler!
descrambler. In accordance with the CCITT V.22 and the Bell
212A recommendations. This function cannot be disabled.

RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R1212 can adapt to received frequency
errors of up to ± 7 Hz with less than a 0.2 dBm degradation in
BER performance.

1. The modem is not in the talk state, i.e., an aSSOCiated
telephone handset is not in control of the line.
2. The modem is not in the process of automatically establishing
a call via pulse or DTMF dialing.
3. The modem is generating an answer tone or detecting answer
tone.
4. After ring indicate goes on, DSR waits at least two seconds
before turning on to allow the telephone company equipment
to be engaged.

RECEIVE LEVEL
The receiver circuit of the R1212 satisfies all specified performance requirements for the received line signals from 0 dBm to
- 45 dBm. The received line signal is measured at the receiver
analog input RXA.

RECEIVE TIMING
DSR will go off 50 msec after DTR goes off or 50 msec plus a
maximum of 4 sec when SSD is enabled. (Note: All time
measurements without a tolerance have a ± 0.5 ms tolerance.)

The R1212 provides a Receive Data Clock (RDCll<) output in
the form of a (50 ± 1% duty cycle) squarewave. The low to high
transitions of this output coincide with the center of received data
bits. The timing recovery circuit is capable of tracking a
± 0.035% (relative) frequency error in the associated transmit
timing source.

DATA TERMINAL READY
An on condition of DTR prepares the modem to be connected
to the communications channel, and maintains the connection
established by the DTE (manual answering) or internal
(automatic answering) means. The off conditior! places the
modem in the disconnect state.

TRANSMIT LEVEL
The R1212M output control circuitry contains a variable gain
buffer which reduces the modem output level. The R1212M can
be strapped via the host interface memory to accomplish this.

PERMISSIVE/PROGRAMMABLE CONFIGURATIONS

AUTOMATIC RECONFIGURA TION

The R1212M transmit level is + 6 dBm to allow a DM to be
used. The DM then determines the permissive or programmable
configuration.

The R1212 is capable of automatically configuring itself to the
compatibility of a remote modem. The R1212 can be in either
the answer or originate mode for this to occur. The compatibilities

7-81

R1212

1200 bps Full-Duplex Modem
RECEIVE/TRANSMIT CIRCUITS

that the R1212 is limited to adapt to are V.22A1B, Bell 212, and
Bell 103. If the R1212 is to originate in a specific configuration,
the MODE bits must be set.

The receiver and transmitter circuits are defined in the following block diagrams:

TONE

&
FSK
DETECTOR

r--------

RX SP

l

IA
,

CARRIER
DETECTOR

I

TRAINING
DETECTOR

RECEIVER
CONFIGURATION

TIMING
RECOVERY

STATUS

,I

, COS~-----'

I
I

,(WT + <1»
DATA
OUTPUT

AGC
CONTROL

I

L -

-

-

-

LINE
INTERFACE
(DAA)

l

L--..,..-----'

I
DESCRAMBLER

RECEIVED
LINE
SIGNAL

SYNC
TO
ASYNC
CONVERTER

JITTER
TRACKER

R1212 Receiver/Equalizer Block Diagram

,--_ _ _--, COS (wi)

TX SP
ASYNC
TO
SYNC
CONVERTER

r------,
I

INPUT
DATA

SCRAMBLER

BAND
SPLIT
FILTER

DATA
ENCODER

L ____

SELF TEST
PATTERN
GENERATOR

~===~~GENERATOR

L_~=======;

~A.J

LPF
FSK

DATA
CI.iK

LINE
INTERFACE
(DAA)

______.,

SIN (WI)

DTMF
GENERATOR

R1212 Transmitter Block Diagram
7-82

PASSBAND
LINE
SIGNAL

1200 bps Full-Duplex Modem

R1212
MODES OF OPERATION

set to a one. The modem automatically defaults to the serial
mode at power-on. In either mode the R1212 is configured by
the host processor via the microprocessor bus.

The R1212 is capable of being operated in either a serial or a
parallel mode of operation.

SERIAL MODE

INTERFACE CRITERIA

The serial mode uses standard V.24 (RS-232-C compatible)
signals to transfer channel data. An optional USART device
(shown in the Functional Interconnect Diagram) illustrates this
capability.

The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
64-pin DIN connector. Software circuits are assigned to specific
bits in a 32-byte interface memory.

PARALLEL MODE

HARDWARE CIRCUITS

The R1212 has the capability of modem control via the
microprocessor bus. Data transfer is maintained over the serial
V.24 channel.

Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R1212 Hardware
Circuits table. In the table, the column titled 'Type' refers to
designations found in the Hardware Circuit Characteristics. The
microprocessor interface is designed to be directly compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, it can be made compatible with 6500, 6800, or 68000
microprocessors.

MODE SELECTION
Selection of either the serial (DTR, RTS, TLK, ORG) or parallel
(DTR, RTS, DATA, ORG) control is by means of the BUS bits
([0,1]:0:7). To enable the parallel control, the BUS bits must be

r------ ........

RTS

I
I

CTS
TXD

I
I
I
I
I

1,.,. ...

""'
USART
(OPTIONAL)

I
I


--

.156 ±.003
DIAMETER
6 PLACES

Ii

I
I

I

~

r--

I

J

Ir--I
t
~.~

4.100

.483

Inches

MM

.119
.156
.483
2.725
3.228
3.700
3.937
4.100
4.725

3
4
12
69
82
94
100
104
120

R1212/U Printed Circuit Board Dimensions

INSTALLATION

4. You should disconnect the modem from the telephone line
if it appears to be malfunctioning. Reconnect it only when
it can be determined that the telephone line is the source of
trouble. If the modem needs repair, return it to Rockwell Inter·
national. This applies to equipment both in and out of war·
ranty. Do not attempt to repair the unit as this will violate FCC
rules.
5. The modem contains protective circuitry to prevent harmful
voltages from being transmitted to the telephone network.
If however such harmful voltages do occur, then the telephone
company shall:
• Promptly notify you of the discontinuance.
• Afford you the opportunity to correct the situation which
caused the discontinuance.
The FCC requires that the following label be prominently
displayed on an outside surface of the OEM's end product.
• Unit contains Registered Protective Circuitry which
complies with Part 68 of FCC Rules.
• FCC Registration Number: Applied For
• Ringer Equivalence: 0.5
Size of the label should be such that all the required information is legible without magnification.

IMPORTANT NOTICE TO USER
The R1212DC/U contains protective circuitry registered with the
Federal Communications Commission (FCC) Part 68 to allow
direct connection to the switched telephone network. To comply
with the FCC regulations the following is required:
1. All direct connections to the telephone lines shall be made
through standard plugs and telephone company provided
jacks.
2. It is prohibited to connect the modem to pay telephones or
party lines.
3. You are required to notify the local telephone company prior
to the connection and upon final disconnection of the modem.
You must supply to the telephone company the make, model
number, FCC registration number, ringer equivalence and
particular line to which the connection is to be made. If the
proper jacks are not available, you must order the type of
jacks to be used from the telephone company.

7·109

R2424
Integral Modems

'1'

Rockwell

R2424
2400 BPS FULL-DUPLEX MODEM

INTRODUCTION

FEATURES

The Rockwell R2424 is a high performance full-duplex 2400 bps
modem. Using state-of-the-art VLSI and signal processing
technology, the R2424 provides the user with enhanced performance and reliability on a single printed circuit board of less than
22 square-inches-overall size.

•
•
•
•

The R2424 modem is ideal for data transmission over the 2-wire
dial-up telephone network. The direct-connect, auto dial/answer
features are specifically designed for remote and central site
computer applications. The bus interface allows easy integration into a personal computer, box modem, microcomputer,
terminal or any other communications product that demands the
utmost in reliability and performance.

•

•
•
•

The added test features, such as local analog loopback, remote
digital loopback, and a self-test function, offer the user flexibility in creating a 2400 bps modem design customized for specific
packaging and functional requirements.

•
•

Being CCITTV.22 bis, V.22 A, B compatible, as well as Bell 212A
and 103 compatible, this modem fits most applications for fullduplex 2400 and 1200 bps fallback (synchronous and asynchronous) and 0 to 300 bps asynchronous data transmission over
the general switched telephone network.

•
•
•
•

CCITT V.22 bis, V.22 A, B Compatible
Bell 212A and 103 Compatible
Synchronous: 2400 bps, 1200 bps, 600 bps ±0.01%
Asynchronous: 2400 bps, 1200 bps, 600 bps + 1%, - 2.5%,
0-300 bps
-Character length 8, 9, 10, or 11 bits
DTE Interface
-Functionally: Microprocessor Bus (Configuration/Control)
and RS-232-C Interface (Data/Control)
-Electrically: TTL Compatible
Operation: 2-wire full-duplex
Adaptive and Fixed Compromize Equalization
Test Configurations:
-Local Analog Loopback
-Remote Digital Loopback
-Self Test
Auto/Manual Answer
Auto/Manual Dial:
-Tone or Pulse Dial
Power Consumption: 3 Watts Typical
Power Requirements: + 5 Vdc, ± 12 Vdc
Plug-compatible member of new Rockwell modem line
Two Versions: R2424DC (Direct Connect) with FCC approved
DAA Part 68 Interface and R2424M (Module) without DAA

R2424 Full-Duplex Modem

Document No. 29200N11
7-110

Data Sheet Order No. MD11
Rev. 2 July 1984

R2424

2400 bps Full-Duplex Modem

TECHNICAL SPECIFICATIONS

reducing the main channel transmit path gain by .97 dB and
1.76 dB for the cases of the 1800 Hz and 553.846 Hz guard
tones respectively.
3. DTMF Tones: The R2424 generates dual tone multifrequency tones. When the transmission of DTMF tones are
required, the CRO and DTMF bits must be set to a 1. (see
Interface Memory). When in this mode, the specific DTMF
tones generated are decided by loading the dial digit register
with the appropriate digit as shown in the following table:

TRANSMITTER CARRIER AND SIGNALING
FREQUENCIES
Transmitter Carrier and Signaling
Frequencies Specifications
Frequency

Specification
(Hz ±0.01%)

V.22 bis low channel, Origmate Mode
V.22 low channel, Originate Mode
V.22 high bis channel, Answer Mode
V.22 high channel, Answer Mode
Bell 212A high channel Answer Mode
Bell 212A low channel Originate Mode
Bell 1031113 Originating Mark
Bell 103/113 Originating Space
Bell 103/113 Answer Mark
Bell 1031113 Answer Space

1200
1200
2400
2400
2400
1200
1270
1070
2225
2025

Dial Dlgits/Tone Pairs
Dial
Digits

BCD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

TONE GENERATION
The specifications for tone generation are as follows:
1. Answer Backtones: The R2424 generates echo disabling
tones both of the CCITT and Bell versions, as follows:
a. CCITT: 2100 Hz ± 15 Hz.
b. Bell: 2225 Hz ± 10 Hz.
2. Guard Tones: If GTS is low, an 1800 Hz guard tone frequency is selected; if GTS is high, a 553.846 Hz tone is
employed. In accordance with the CCITT V.22 Recommendation, the level of transmitted power for the 1800 Hz guard
tone is 6 ± 1 dB below the level of the data power in the main
channel. The total power transmitted to the line is the same
whether or not a guard tone is enabled. If a 553.846 Hz guard
is used, its transmitted power is 3 ± 1 dB below the level of
the main channel power, and again the overall power
transmitted to the line will remain constant whether or not
a guard tone is enabled. The device accomplishes this by

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
2
3
4
5

6
7
8
9

*

Spare (B)
Spare (C)
Spare (D)

#
Spare (F)

Tone Pairs
941
697
697
697
770
770
770
852
852
852
941
697
770
852
941
941

1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1633
1633
1633
1477
1633

TONE DETECTION
The R2424 detects tones in the 340 ± 5 Hz to 640 ± 5 Hz band.
Detection Level: 0 to - 45dBm
Response Time: 17 ± 2ms

SIGNALING AND DATA RATES
The Signaling and data rates for the R2424 are defined in the
table below:

Signaling and Data Rates
Operating Mode

Signaling Rate (Baud)

Data Rate

V.22 bis:

600

Synchronous/Asynchronous
2400 bps ±0.01%

V.22 bis:

600

Synchronous/Asynchronous
1200 bps ±0.01%

V.22:
(Alternative A)
Mode i

600

1200 bps ± 0.01 % Synchronous

600

600 bps ± 0.01 % Synchronous

600
600

1200 bps ± 0.01 % Synchronous
600 bps ±0.01% Synchronous

Mode iii
(Alternative B)
Mode i
Mode iii
Mode ii

1200 bps Asynchronous
8, 9, 10, or 11 Bits Per Character

Mode iv

600 bps Asynchronous
8, 9, 10, or 11 Bits Per Character

Bell 212A:

1200 bps ±0.01%
Synchronous/Asynchronous
o to 300 bps Asynchronous

600

o to 300
7-111

fJ

R2424

2400 bps Full-Duplex Modem

DATA ENCODING

The R2424DC transmit level is strapped in the permissive mode
so that the maximum output level is - 10 dBm ± 1.0 dBm.

The specifications for data encoding are as follows:
1. 2400 bps (V.22 bis). The transmitted data is divided into
groups of four consecutive bits (quad bits) forming a 16-point
signal structure.
2. 1200 bps (V. 22 and 8eI/212A). The transmitted data is divided
into groups of two consecutive bits (dibits) forming a four-point
signal structure.
3. 600 bps (V.22). Each bit is encoded as a phase change
relative to the phase preceding signal elements.

TRANSMIT TIMING
The R2424 provides a Transmit Data Clock (TDCLK) output with
the following characteristics:

1. Frequency. Selected data rate of 2400, 1200 or 600 Hz
(±0.D1%).
2. Duty Cycle. 50 ± 1%.
Transmit Data (TXD) must be stable during the one microsecond
periods immediately preceding and following the rising edge of
TDCLK.

EQUALIZERS
The R2424 provides equalization functions that improve performance when operating over low quality lines.

CLAMPING

Automatic Adaptive Equalizer-An automatic adaptive
equalizer is provided in the receiver circuit for V.22 bis, V.22
and Bell 212A configurations.

The following clamp is provided with the R2424:
1. Receive Data (RXD). RXD is clamped to a constant mark (1)
whenever RLSD is off.

Fixed Compromise Equalizer-Compromise equalizers are provided in the transmitter and receiver.

RECEIVED LINE SIGNAL DETECTOR

TRANSMITTED DATA SPECTRUM

The high and low channel thresholds are greater than - 45 dBm
(RLSD on) and less than -48 dBm (RLSD off) for V.22 bis, V.22
and Bell 212A configurations.

After making allowance for the nominal specified compromise
equalizer characteristic, the transmitted line signal has a frequency
spectrum shaped by the square root of a 75 percent raised cosine
filter. Similarly, the group delay of the transmitter output is within
± 100 microseconds over the frequency range 900 to 1500 Hz
(low channel) and 2100 to 2700 Hz (high channel).

DATA SET READY

The R2424 incorporates a self-synchronizing scramblerl
descrambler. In accordance with the CCITT V.22 bis, V.22 and
the Bell 212A recommendations.

The on condition of the R2424 output Data Set Ready (DSR) indicates that the modem is in the data transfer state. The off condition of DSR is an indication that the DTE is to disregard all signals
appearing on the interchange circuits-except the calling indicator
and the test signal. DSR will switch to the off state when in test
state. The on condition of DSR indicates the following:

RECEIVED SIGNAL FREQUENCY TOLERANCE

1. The modem is not in the talk state, I.e., an associated
telephone handset is not in control of the line.

The receiver circuit of the R2424 can adapt to received frequency
errors of up to ± 7 Hz with less than a 0.2 dBm degradation in
BER performance.

2. The modem is not in the process of automatically establishing
a call via pulse or DTMF dialing.

SCRAMBLER/DESCRAMBLER

3. The modem is generating an answer tone or detecting answer
tone.

RECEIVE LEVEL

4. After ring indicate goes on, DSR waits at least two seconds
before turning on to allow the telephone company equipment
to be engaged.

The receiver circuit of the R2424 satisfies all specified performance requirements for the received line signals from 0 dBm to
- 45 dBm. The received line signal is measured at the receiver
analog input RXA.

DSR will go off 50 msec after DTR goes off or 50 msec plus a
maximum of 4 sec when SSD is enabled. (Note: All time
measurements without a tolerance have a ±0.5 ms tolerance.)

RECEIVE TIMING
The R2424 provides a Receive Data Clock (RDCLK) output in the
form of a (50 ± 1% duty cycle) squarewave. The low to high transitions of this output coincide with the center of received data bits.
The timing recovery circuit is capable of tracking a ± .035% (relative) frequency error in the associated transmit timing source.

DATA TERMINAL READY
An on condition of DTR prepares the modem to be connected
to the communications channel, and maintains the connection
established by the DTE (manual answering) or internal (automatic
answering) means. The off condition places the modem in the
disconnect state.

TRANSMIT LEVEL
The R2424M output control circuitry contains a variable gain buffer
which reduces the modem output level. The R2424M can be
strapped via the host interface memory to accomplish this.

AUTOMATIC RECONFIGURATION
The R2424 is capable of automatically configuring itself to the
compatibility of a remote modem. The R2424 can be in either
the answer or originate mode for this to occur. The compatibilities
that the R2424 are limited to adapt to are V.22 bis, V.22 AlB
(1200 bps), Bell 212, and Bell 103. If the R2424 is to originate
in a specific configuration, the MODE bits must be set.

PERMISSIVE/PROGRAMMABLE CONFIGURATIONS
The R2424M transmit level is + 6 dBm to allow a DAA to be used.
The DAA then determines the permissive or programmable
configuration.
7-112

R2424

2400 bps Full-Duplex Modem

RECEIVE/TRANSMIT CIRCUITS
The receiver and transmitter circuits are defined in the following block diagrams:

-

TONE
&
FSK
DETECTOR

r-------I

IA

...

I

RX SP

TO CLOCK

l

DR.VE

I

RECEIVER

TRAINING
DETECTOR

CARRIER
DETECTOR

I

I

TRAINING
CONTROL

TIMING
RECOVERY

t

I
I

I

AGC
CONTROL

I

-

kttE
r
L----

U",
INTERFACE
(DAA)

l

I

I

& BPF
& BSF

ADC

I COS
I(WT +

J

r-- CONFIGURATION

r-- STATUS

I


-0.1 max.
1.6 max.

mA
mA
~A
~A

pF
pF

-240 max.
-10 min.
5

5

08

TTL
w/Pull-up

0.4 max. 2

1.6 max.
± 10 max.

1.6 max.

-240 max.
-10 min.
20

TTL
w/Pull-up

1/0 A

I/O 8

2.0 min.

5.25 max.
2.0 min.
0.8 max.
2.4 min.3
0.4 max. 2

,

0.4 max,>

0.8 max.
2.4 min.
0.4 max. 2
±2.5 max'

-240 max.
-10 min.
100

TTL

OC

TTL

100

10
100

100

-260 max.
-100 min.
40
100

Open-Drain Open Drain
3 State
Open-Drain
w/Pull-up Transceiver w/Pull-up

= -100 ~A
= 1.6 mA
= -40 ~A
0.4 10 2.4 Vdc, Vcc = 5.25 Vdc

Ring Indicator-The R2424 provides a ring indicator (Ai)
output; its low state indicates the presence of a ring signal on
the line. The low condition appears approximately coincident
with the on segment of the ring cycle (during rings) on the communication channel. (The ring signal cycle is typically two
seconds on, four seconds off.) The high condition of the indicator
output is maintained during the off segment of the ring cycle
(between rings) and at all other times when ringing is being
received. The operation of RT is not disabled by an off condition
on Data Terminal Ready.

Analog Interface Characteristics
TXA-The (Type OC) transmitter output is a low impedance
operational amplifier output in series with a 604 ohm resistor.
In order to have a 0 dBm output, an external 600 ohm resistor
to ground is required.
RXA-The (Type IB) receiver input impedance is 63.4K ohms
±5 percent.

Transmission Line Interface Characteristics
The R2424DC interface to the telephone line is the Tip and Ring
leads. Lightning induced surge voltages and other hazardous
voltages which may appear on the telephone line are limited to
approximately 7V peak between the secondary leads of the line
coupling transformer.

Ri will respond to ring signals in the frequency range of 15.3 Hz
to 68 Hz with voltage amplitude levels of 40 to 150 Vrms (applied
across Tip and Ring), with the response times given in the following table:
RI Response Time

The DAA (R2424DC only) is bi-directional as required by 2-wire
full-duplex circuits.
Connection to the telephone line interface pins of the R2424DC
to the network are made via two RJ 11 jacks. The pin designations are shown in the table below:

Telco

Mnemonic

2
3

R

Jack

4

T

170 ±50 ms
110 ±50 ms

Function
OH-The R2424M provides an output OH (Off-Hook) which
indicates the state of the OH relay. A low condition on OH implies
the OH relay is closed and the modem is connected to the
telephone line. A high condition on OH implies the OH relay is
open (I.e., the modem is on-hook). The delay between the lowto-high or high-to-Iow transition of OH and the subsequent closeto-open or open-to-close transition of the OH relay is 8 ms
maximum.

1

VSOC
RJll

Response Time

Off-Io-On
On-Io-Off

This off-to-on (on-to-off) response time is defined as the time
interval between the sudden connection (removal) of the ring
signal across Tip and Ring and the subsequent on (off) transition Ri.

R2424DC Network Interface
Connection Type

RI Transition

Ring-one side of
lelepone line
Tip-one side of
telephone line

5
6

7-116

R2424

2400 bps Full-Duplex Modem

RD-AD indicates to the A2424M by an on (low) condition that
a ringing signal is present. The RD signal should not respond to
momentary bursts of ringing less than 125 ms in duration, or to
less than 40V rms, 15 to 68 Hz appearing across Tip and Ring
with respect to ground.

Two RAM access registers are provided in the interface memory
to allow user access to various RAM locations within chip 0 and
chip 1. The access code stored in O:F selects the source of data
for the RAM data registers in chip 0 (0:5 through 0:2). Similarly,
the access code stored in 1:F selects the source of data for
registers 1:5 through 1:2. Reading is performed by first storing
the desired access code in register O:F (or 1:F). The data may
then be read from 0:5 through 0:2 (or 1:5 through 1:2).

RCCT-RCCT is used to request that a data transmission path
through the DAA be connected to the telephone line. When RCCT
goes off (low), the cut-through buffers are disabled and CCT
should go off (high) within 1 msec. RCCT should be off during
dialing but on for tone address signalling.

RAM Access Codes
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.

ccr-An on (low) signal to the CCT lead indicates to the R2424M
that the data transmission path through the DAA is connected.

RAM Access Codes (Chip 0)

AUDIO INTERFACE INPUT IMPEDANCE
CHARACTERISTICS

Function

Audio Interface Input Impedance Characteristics
OnlOff Hook

Measurement

On-Hook (DC)

The DC resistance between Tip and
Ring, and between either TIp or Rmg
and signal ground is greater than
10 megohms for DC \/Oltages up to 100 \/OIls.

On-Hook (AC)

The on-hook AC Impedance measured
between TIp and Ring IS less than
40K ohms (153 Hz minimum).

Off-Hook (DC)

Less than 200 ohms.

Off-Hook (AC)

600 ohms nominal when measured
between TIp and Ring.

Self Test Error Counter
Equalizer Tap CoeffiCients
Phase Error
Rotated Equalizer Output
(Received Pomt Eye Pattern)
Rotated Angle
Low Pass Filter Output
Input Signal to Equalizer Tap CoeffiCients
DeciSion Pomts (Ideal Eye Pattern)
Rotated Error
Equalizer Output
Demodulator Output

Access
Code

Register
No.

00

2,3
2,3,4,5
2,3
2,3,4,5

01-00
10
11
12
40

41-40
51
52
53
56

4,5
2,3,4,5
2,3,4,5
2,3,4,5
2,3,4,5
2,3.4,5
2,3,4,5
_.

Auto Dial Sequence
SOFTWARE CIRCUITS

The following flow chart defines the auto dial sequence via the
microprocessor interface memory.

The R2424 comprises two signal processor chips. Each of these
chips contains 16 registers to which an external (host) microprocessor has access. Although these registers are within the
modem, they may be addressed as part of the host processor's
memory space. The host may read data out of or write date into
these registers. The registers are referred to as interface
memory. Registers in chip 0 update at the modem baud rate
(600 bps) (except RAM access and RAM Data Update where
operation is at sample rate). Registers in chip 1 update at the
sample rate (7200 bps).
When information in these registers is being discussed, the
format V:Z:Q is used. The chip is specified by V(O or 1), the
register by Z(O-F), and the bit by Q (0-7, 0= LSB).

STATUS/CONTROL BITS
The operation of the R2424 is affected by a number of software
control inputs. These inputs are written into registers within the
interface memory via the host microprocessor bus. Bits designated by an 'X' are "Don't Care" inputs that can be set to either
1 or O. Modem operation is monitored by various software flags
that are read from interface memory via the host microprocessor
bus. All status and control bits are defined in the Interface
Memory table. Bits deSignated by an 'R' are reserved for modem
use only and must not be changed by the host.

II

RAM Data Access
Auto Dial Sequence Flow Diagram

The R2424 provides the user with access to much of the data
stored in the modem's memories. This data is useful for performing certain diagnostic functions.

Note: The modem timing for the auto dialer accounts for interdigit delay for pulses and tones.

7-117

2400 bps Full-Duplex Modem

R2424
The timing for the pulses and tones are as follows:

Output Level
1.5 ±1 dBm

Tones - Tone duration
71 ms
Interdigit delay
71 ms

Pulses - Relay open 64 ms
Relay closed 36 ms
Interdigit delay
750 ms

R2424 Transmitter Interface Memory Chip 1 (CS1)

R2424 Receiver Interface Memory Chip 0 (CSO)

~

7

E

IRQ

0

BUS CRO

6

3

4

5

2

1

0

RAM Access B

F

ENSI NEWS

7

6

4

5

2

3

1

0

X

ENSI NEWS

R

NEWC

R

R

R

E

IRO

X

X

LCD

RSD

X

D

BUS CRO DATA AAE

X

X

X

C

X

X

X

AL

B

CHAR

X

X

X

B

X

X

X

X

DL

ST

ERDL RDL

RAM Access S

F

R

C

A

I~
Register

Register

MODE

DSRA

TXCLK

ERDL RDL

DTR

CHAR

TX LEVEL

A

NEWC DDEI

GTE

DL

R

DDRE

X

X

SSD

X

X

GTS

3DB DTMF

X
AL

MODE

ST

9

X

X

SPEED

X

X

X

X

9

BRK RTRN ORG

LL

RTS

CC

X

X

8

TONE

X

X

X

X

TM

RLSD

8

DLO

CTS

DSR

RI

X

X

X

X

7

R

R

R

R

R

R

R

R

7

R

R

R

R

R

R

R

R

6

R

R

R

R

R

R

R

R

6

R

R

R

R

R

R

R

R

R

R

R

2

1

0

X

RAM Data YBM

5

5

RAM Data YSM
RAM Data YSL

4

RAM Data YBL

4

3

RAM Data XBM

3

RAM Data XSM

2

RAM Data XBL

2

RAM Data XSL

1

R

R

R

R

R

R

R

R

1

0

R

R

R

R

R

R

R

R

0

7

6

5

4

3

2

1

0

~

~
Bit

R

R

R

R

R

Dial Digit Register

7

6

5

4

3

Bit

Note
(X) indicates user available.
(R) Indicates reserved for modem use only.

Note
(X) indicates user available.
(R) indicates reserved for modem use only.

R2424 Interface Memory Definitions
Mnemonic

Name

AAE

Auto Answer Enable

AL

Analog Loopback

BRK

Break

BUS

Bus Select

Memory
Location
I:D:4

(O,I):B:O

1:9:7

(0,1):D:7

Description
When control bit AAE goes to a one, the modem will automatically
answer when a ringing signal is present on the line.
When control bit AL is a one, the modem IS placed In (V.54 Loop 3) local
analog loopback. In this loop, the transmitter's analog output is coupled
to the receiver's analog input at a point near the modem's telephone line
Interface. An attenuator is Introduced into the loop such that the signal
level coupled into the receive path is attenuated 14 ±1 dBm.
When control bit BRK goes to a one, the modem transmits 2M + 3 bits
of start polarity. (M is equal to the number of bits per character in the
selected format.) BRK will reset to zero after the sequence IS sent.
When control bit BUS goes to a one, the modem is placed In the parallel
control mode, and when zero the modem is configured for the senal control mode. BUS can be in either state to configure the modem.

7·118

R2424

2400 bps Full-Duplex Modem
R2424 Interface Memory Definitions (Continued)

Mnemonic

Name

CC

Controlled Carrier

CHAR

Character Length Select

Memory
Location
1:9:2

(0,1):C:(3,4)

Delcrlptlon
When control bit CC goes to a one, the modem Is placed In controlled
carrier operation; and when zero, the modem Is configured for constant
carrier operation.
These character length bits select either 8, 9, 10, or 11 bit characters, as
shown below:
Conllgurltlon
8 bits
9 bits
10 bits
11 bits

Configuration Word

o
o
1
1

0
1
0
1

CRO

Call Request

(0,1):0:6

When control bit CRO goes to a one, it places the transmitter In auto
dial and the receiver in tone detect mode. The data placed In the dial
digit register is then treated as digits to be dialed. After the last digit has
been dialed, FF (HEX) should be loaded Into the dial digit register to tell
the modem to go to the data state. CRO in the transmitter (chip 1) when
turned off causes the modem to go on-hook. Therefore, It should be on
for the duration of the call and not turned 011 until it Is desired to go
on-hOOk. CRO In the receiver (chip 0) must be turned off Immediately
after rlngback Is detected to put the modem In the data mode, otherwise
no answerback tone will be detected.

CTS

Clear-to-Send

1:8:6

When status bit CTS is a one, it indicates to the terminal equipment that
the modem will transmit any data which are present at TXo.
CTS response times from an on or off condition of RTS are shown
below:
CTS Tranaltlona
011 to On
On to 011

Conatant Carrier
<2 ms
<2 ms

Controlled Cerrler
275 ms
<2 ms

DATA

Talkloata

1:0:5

When control bit DATA goes to a one, It places the modem in data state
and when zero In Ihe talk state.

ooEI

Dial Digit Empty Interrupt

1:E:2

When control bit ODE I goes to a one, It causes an Interrupt to occur
when the dial digit register (1:0) Is empty (ooRE - 1).

ooR

Dial Digit Register

1:0:(0-7)

ooR is used to load the digits to be dialed. Example: If a 4 is to be
dialed, a 04 (HEX) should be loaded. This action also causes the
Interrupt to be cleared. ooR Is a write only register.

ooRE

Dial Digit Register Empty

l:E:O

When status bit oDRE Is a one, it indicates that the dial digit register is
empty and can be loaded with a new digit to be dialed. After the register
is loaded, ooRE goes to a zero.

oL

Digital Loopback (Manual)

(0,1):A:5

When control bit DL is a one, the modem is manually placed in ramote
digital loopback. oL should be set during the data mode. oSR and CTS
will be at zero. The local modem can then be tested from the far-end by
using the terminal equipment at the far-end to transmit a test pattern and
examine the looped data. At the far-end modem, all interiace circuits
behave normally as In the data mode. At the conclusion of the test, oL
must be resel to zero. The local modem will then return to the normal
data mode with control reverting the oTEs, DTR.

oLO

Data Line Occupied

1:8:7

When status bit oLO Is a one, it indicates that the modem is in the auto
dial state, i.e, CRO Is at a one and the modem is off-hook and ready to
dial.

oSR

Data Set Ready

1:8:5

When status bit oSR is a one, it indicates that the answerback tone has
been detected, the modem handshake has begun and that the data state
will follow. DSR alone should not be used to indicate that the
communication channel has been completely established. oSR in
conjunction with CTS and RLSo will determine this. oSR will be at zero
in all test states (except optionally for analog loopback) and when the
channel is being used for voice communication (talk).

7-119

II

R2424

2400 bps Full-Duplex Modem
R2424 Interrace Memory Deflnltlonl (ContInued)
Memory
Location

De.crlptlon

Mnemonic

Name

OSRA

Data Set Ready In Analog
Loopback

1:C:7

When control bit OSRA goes to a one, It causes OSR to be set to a one
during analog loopback.

OTMF

Touch Tones!
Pulse Dialing

1:8:1

When control bit OTMF goes to a one, It tells the modem to auto dial
using tones, and when zero the modem will dial using pulses.

OTR

Data Terminal Ready

1:0:3

Control bit OTR must be a one, before the modem will enter the data
state, either manually or automtlcally. OTR must also be at a one In
order for the modem to automatically answer an Incoming call.

ENSI

Enable New Status
Interrupt

(0,1):E:6

When control bit ENSI goes to a one, It causes an Interrupt to occur
when the status bits In registers (0:[8,9]) and (1 :8) are updated.
(NEWS - 1)

EROL

Enable Response to
Remote Digital Loopback

(0,1):A:7

When control bit EROL goes to a one, It enables the modem to respond
to another modem's remote digital loopback request, thus going into
loopback.

GTE

Guard Tone Enable

1:8:4

When control bit GTE goes to a one, It causes the specified guard tone
to be transmitted (CCITT Configurations only).

GTS

Guard Tone Select

1:8:3

When control bit GTS goes to zero, it selects the 1800 Hz tone and
when a one it selects the 550 Hz tone.

IRQ

Interrupt

(0,1):E:7

When status bit IRQ is a one, it Indicates that an interrupt has been
generated.

LCD

Loss of Carrier
Disconnect

0:0:2

When control bit LCD goes to a one, the modem terminates a call when
a loss of received carrier energy is detected after 400 msec. After the
first 40 ms of loss of carrier, RLSO goes off. 360 ms later if no carrier is
detected, CTS goes off.

LL

Leased Line

1:9:4

When control bit LL goes to a one, it places the modem in leased line
operation; and when zero, switched line operation.

MODE

Mode Select

(0,1):A:(0,3)

LCD is not disabled In leased line operation.

These bits select the compatibility at which the modem is to operate, as
shown below:
Configuration
Bell 212A
12aO
Bell 212A
1200
Bell 212A
300
V.22A
1200
1200
V.228
600
V.22A
V.22B
600
2400
V.22 bis
V.22 bis
2400
V.22 bis
1200
1200
V.22 bis

Sync.
Async.
Async.
Sync.
Async.
Sync.
Async.
Sync.
Async.
Sync.
Async.

Configuration Word
a
1
a
a
0
0
1
1
1
0
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
1
0
0
1
1
1
1
0
1
1
1
0
1
1
1
1

NEWC

New Configuration

(0.1):E:3

When status bit NEWC is a one, it tells the modem that a new
configuration has been written into the configuration registers. The
modem will then read the configuration registers and then reset NEWC.
NEWC must be set after a new configuration has been written into the
following registers: (O:[A-D]) and (1 :[9-0]). The remaining registers do
not require the use of NEWC to tell the modem that new data was
written Into them.

NEWS

New Status

(0,1):E:5

When status bit NEWS is a one, it tells the user that there has been a
change of status in the status registers. The user must write a zero into
NEWS to reset it. This aclion also causes Ihe Interrupt 10 be cleared.

7·120

2400 bps Full-Duplex Modem

R2424

R2424 Interface Memory Definitions (Continued)
Mnemonic

Name

Memory
Locetlon
1:9:5

Description

ORG

Originate/Answer

When status bit ORG is a one, it tells the modem that it is originating a
call and when a zero answering a call. (This is only valid In manual
originate/answer and analog loopback.)

(None)

RAM Access B

0:F:0-7

Contains the RAM access code used in reading RAM locations
(baud rate device).

(None)

RAM Access S

1:F:0-7

Contains the RAM access code used in reading RAM locations in chip 1
(sample rate device).

(None)

RAM DataXBL

0:2:0-7

Least significant byte of 16-bit word X used in reading RAM locations in
chip o.

(None)

RAM DataXBM

0:3:0-7

Most significant byte of 16-blt word X used in reading RAM locations in
chipO.

(None)

RAM Data XSL

1:2:0-7

Least significant byte of 16-bit word X used in reading RAM locations in
chip 1.

(None)

RAM DataXSM

1:3:0-7

Most significant byte of 16-bit word X used in reading RAM locations in
chip 1.

(None)

RAM Data YBL

0:4:0-7

Least significant byte of 16-bit word Y used In reading RAM locations in
chipO.

(None)

RAM DataYBM

0:5:0-7

Most significant byte of 16-bIt word Y used in reading RAM locations in
chip o.

(None)

RAM Data YSL

1:4:0-7

Least significant byte of 16-bit word Y used in reading RAM locations In
chip 1.

(None)

RAM Data YSM

1:5:0-7

Most significant byte of 16-bit word Y used in reading RAM locations in
chip 1.

RDL

Remote Digital Loopback

(O,1):A:6

When control bit RDL goes to a one, It causes the modem to Initiate a
request for the remote modem to go Into digital loopback.

RI

Ring Indicator

1:8:4

When status bit RI is a one, It indicates that a ringing Signal is being
detected.

RLSD

Received Line Signal
Detector

0:8:0

When status bit RLSO is a one, it indicates that the carrier has
successfully been received. RLSD will not respond to the 550, 1800,
2100, or 2225 Hz tones. RLSD response times are given below:
RLSO Transltlona'
Off to On
On to Off

Conatant Carrier
40 to 65 ms
40 to 85 ms

In

chip 0

Controllad Carrier
40 to 65 ms
40 to 65 ms

Note:
1. After handshake has occurred.
RSD

Receive Space
Disconnect

0:0:1

When control bit RSD goes to a one, It causes the modem to go on-hook
after receiving approximately 1.6 seconds of continuous spaces.

RTRN

Retrain (V.22 bis only)

1:9:6

When control bit RTRN goes to a one, it sends the training sequence. It
resets when the sequence is completed.

7-121

2400 bps Full-Duplex Modem

R2424

R2424 Interface Memory Definitions (Continued)
Mnemonic

RTS

Name

Request-to-Send

Memory
Location

1:9:3

Description

When control bit RTS goes to a one, It allows the modem to transmit
data when CTS becomes active. Responses to RTS are shown below:
Assume DTR is on, Talk/Data is set to Data (CRO or AAE IS set for a
dial line) and the modem IS connected to the line (off-hook).
Leased or Dial Line 1
Controlled Carrier

RTS Off
CTS Off
Carrier Off

RTS On
Carrier On
275 ms Scrambled l's
Transmitted
CTS On

Constant Carrier

CTS Off
Carrier On
Scrambled l's
Transmitted

CTS On
Carrier On
Data Transmitted

Note:
1. After handshake IS complete.

For ease of use in constant carrier mode, RTS should be turned on the
same time as DTR.
SPEED

Speed Indication

SSD

Send Space Disconnect

ST

Self Test

0:9:(4,5)

00
01

= 300 bps
= 600 bps

10
11

= 1200 bps
= 2400 bps

I:D:O

When control bit SSD goes to a one, it causes the modem to transmit
approximately 4 seconds of spaces before disconnecting, when DTR is
at zero.

(0,1):A:4

When control bit ST IS a one, self test is activated. ST must be at zero
to end the test. It is possible to perform test with or without DTE
connected. During any self test, TXD and RTS are ignored. Self test do
not test asynchronous-to-synchronous converter circuits in either the
transmitter or receiver.
Error detection is accomplished by monitoring the self test error counter
in the RAM. If the counter increments during the self test, an error was
made. The counter contents are available in the diagnostic register when
the RAM access code 00 is loaded in the diagnostic control register
(O:F).
Self Test End-to-End
Upon activation of self-test an internally generated data pattern of
alternate binary ones and zeros (reversals) at the selected bit rate are
applied to the sC'rambler. An error' detector, capable of identifying errors
in a stream of reversals are connected to the output of the descrambler.
Self Test with Loop 3
Loop 3 is applied to the modem as defined In recommendation V.54
Self-test IS activated and DCE operation is as In the end-lo-end lest. In
this test DTR is ignored.
Self Test with Loop 2
The modem is conditioned to instigate a loop 2 at the remote modem as
specified in recommendation V 54. Self-test IS activated and DCE
operation is as in the end-to-end test.

3DB

3 dB Loss to Receive
Signal

I:B:2

When control of bit 3DB is a one, It attenuates the received Signal 3 dB.
This IS only used If the R2424M will see 0 dBm or greater line Signal at
the receiver input. Insertion of the 3 dB loss will then prevent saturation.
This bit is not needed With the R2424DC.

TM

Test Mode

0:8:1

When status bit TM is a one, It indicates that the modem has completed
the handshake and is In one of the follOWing test modes: AL, RDL, or DL.

TONE

Tone Detect

0:8:7

TONE follows the energy detected In the 340 to 640 Hz frequency band.
The user must determine which tone is present on the line by
determining the duty cycle of the TONE bit. TONE is active only when
CRO in chip 0 is a one.

7-122

R2424

2400 bps Full-Duplex Modem
R2424 Interface Memory Definitions (Continued)

Mnemonic

Name

Memory
Location

Description

TXCLK

Transmit Clock Select

1:C:(5,6)

TXCLK allows the user to designate the origin of the transmitter data
clock, as shown below:
Transmit Clock
Configuration Word
Internal
a a
Not Used
a 1
External
1
a
Slave
1
1

TX LEVEL

Transmit Level

1:B.(5-7)

TX LEVEL allows the User to change the R2424M transmitter output
level, assuming the modem is transmitting Into a 600 ohm load.
Transmit Level
(±t.O dBm)
a dBm
-2 dBm
-4 dBm
-6 dBm
-8 dBm
-10 dBm
-12 dBm
-14 dBm

POWER-ON INITIALIZATION

Configuration Word

a
a
a
a
1
1
1
1

1
1

a

a
a

1

a
1
1

BIT ERROR RATES
The Bit Error Rate (BER) performance of the R2424 is specified
for a test configuration conforming to that specified in CCIIT
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of -43 dBm.

NOISE
SOURCE
ATTENUATOR
I-GR1381
HP 350D
50 KHZ BW

IMPAIRMENT
ATTENUATOR
10SOURCE
I-HP 350D
BRADLEY 2A

I:

I
ENGINEERING
MODEM
CONSOLE

a

PERFORMANCE

POR can be connected to a user supplied power-on-reset signal
in a wire or configuration. A low active pulse of 3 !,sec or more
applied to the POR pin causes the modem to reset. The modem

LINE

1

1
1

Whether functioning as a V.22 bis, V.22, or Bell 212A type
modem, and regardless of simulated line condition or introduced
line impairment, the R2424 provides unexcelled high performance to the user.

At POR time the modem automatically defaults to V.22 bis
2400 bps, answer state using serial start-stop data, 10 bits per
character, constant carrier, dial line.

\ - - - SIMULATOR 1 0 -

a

is ready to be configured 10 msec after the low active pulse is
removed from POR.

When power is applied to the R2424, a period of 50 to 300 ms
is required for power supply settling. The power-on reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below 3.5 Vdc for more than 30 msec, the POR cycle is
repeated.

MODEM
TRANSMITTER

a
a

NOTE:
IN THE V.56B SET-UP NO NOISE FILTER IS USED, BUT THE NOISE POWER IS
CALCULATED AS IF A PERFECT 0.3 TO 3.4 kHz NOISE FILTER WAS USED. TO ACHIEVE
THIS EFFECT, THE LEVEL METER USES 15 kHz FLAT WEIGHTING AND 6.85 dB IS
ADDED TO THE MEASURED SIN RATIO.

BER Performance Test Setup
7-123

r-

LEVEL
METER
HP 3552A

1"-'---

MODEM
RECEIVER

J
ENGINEERING
MODEM
CONSOLE

fI

2400 bps Full-Duplex Modem

R2424
GENERAL SPECIFICATIONS

Mechanical

Power
Voltag.·

Tolerance

Current (Max)

+5 Vdc
+ 12 Vdc
-12 Vdc

±5%
±5%
±5%

<500 ma
< 10 ma
< 50 ma

• All voltages must have ripple

Board Structure

Single PC board with right angle
male DIN connector.

Mating Connector

Female 3 row 64 pin Euroconnector
(DIN) with rows A and C populated.
Recommended mating connector:
Winchester 968-6043-0531-1 or
equivalent.

:s 0.1 volts peak-to-peak.
PCB Dimensions
R2424DC Version

Environmental

Width 3.94 In. (100 mm) x Length
4.725 in. (120 mm) x Height 0.75 in.
(19mm)
Width 3.94 in. (100 mm) x Length
3.23 in. (82 mm) x Height 0.40 In.
(10mm)

Specification

Parametar

R2424M Version

Temperature
Operating
Storage·

OOC to + 60°C (32 to 140°F)
-40°C to +80°C (-40 to 176°F)

Relative Humidity

Up to 90% noncondensing, or a wet
bulb temperature up to 35°C,
whichever is less.

Altitude

Weight

Less than 0.45 Ibs. (0.20 kg.)

Lead Extrusion

0.100 In. (2.54 mm) max.

- 200 to + 10,000 feet

·PCB's are stored in heat sealed antistatic bags and shipping
containers.

IT
II
t;

ell

....--- ----< ~r-'-

MALE 64·PIN

I--" DIN CONNECTOR
I

I

g

....

.156 i.003
DIAMETER
4 PLACES

I

R2424M

~ ~

I
I

I

-]

T

~.U'~.~
3.228

MALE 54·PIN
..-- DIN CONNECTOR
I

I

I

nlbt
I
I

ell

~

IT

.156 ±.003
DIAMETER
5 PLACES

R2424DC

I

..

.-1r'T

1--

4.100

'.~AU

4.725

R2424 Printed Circuit Board Dimensions

7·124

I

ell

Inche.

MM

.119
.156
.463
2.725
3.228
3.700
3.937
4.100
4.725

3
4
12
69
82
94
100
104
120

R2424

2400 bps Full-Duplex Modem

INSTALLATION

4. You should disconnect the modem from the telephone line
If It appears to be malfunctioning. Reconnect It only when
It can be determined that the telephone line Is the source of
trouble. If the modem needs repair, return It to Rockwell International. This applies to equipment both In and out of warranty. Do not attempt to repair the unit as this w"l violate FCC
rules.
5. The modem contains protective circuitry to prevent harmful
voltages from being transmitted to the telephone network.
If however such harmful voltages do occur, then the telephone
company shall:
• Promptly notify you of the discontinuance.
• Afford you the opportunity to correct the situation which
caused the discontinuance.
The FCC requires that the following label be prominently
displayed on an outside surface of the OEM's end product.
• Unit contains Registered Protective Circuitry which
complies with Part 68 of FCC Rules.
• FCC Registration Number: Applied For
• Ringer Equivalence: 0.5
Size of the label should be such that all the required information is legible without magnification.

IMPORTANT NOTICE TO USER
The R2424DC contains protective circuitry registered with the
Federal Communications Commission (FCC) Part 68 to allow
direct connection to the switched telephone network. To comply
with the FCC regulations the following Is required:
1. All direct connections to the telephone lines shall be made
through standard plugs and telephone company provided
jacks.
2. It is prohibited to connect the modem to pay telephones or
party Ii nes.
.
3. You are required to notify the local telephone company prior
to the connection and upon final disconnection of the modem.
You must supply to the telephone company the make, model
number, FCC registration number, ringer equivalence and
particular line to which the connection is to be made. If the
proper jacks are not available, you must order the type of
jacks to be used from the telephone company.

II
7-125

R24DC
Integral Modems

'1'

Rockwell

R24DC
2400 BPS DIRECT CONNECT MODEM

INTRODUCTION

FEATURES

The Rockwell R24DC Is a high performance synchronous serial
2400 bps DPSK modem. Extensively utilizing MOS/LSI technology with registered protective circuitry, the R24DC Is Ideally
suitable for direct connection to the domestic switched network
or two-wire private lines. Performance and versatility are enhanced
while cost and size are reduced by the on·board Rockwell
PPS-4/1 One Chip Microcomputer

• High Performance; Low Cost
• LSI High Density; Low Power
• Microcomputer Controlled Line Connect/Disconnect Sequence;
Low Component Count
• Bell 201 C, cCln V.26 bis Compatible
• Half Duplex (2-Wlre) Operating Mode
• 2400 BPS Data Rate
• Auto or Manual Answer
• Auto or Manual Dial Through (Pulse Dialing)
• Automatic Answer Back Tone Generation upon Auto Answer
• Direct Connect to Switched Network
• Programmable or Permissive Connection Arrangement
• Local Analog Loopback Test Mode
• Compromise Equalizer (Strap Selectable)
• Scrambler/Descrambler Facility (Selectable)
• Line Current Sensing (Selectable)
• DTE Interface LSTTLICMOS Compatible Levels. RS-232-C
Functions
• External Transmit Data Clock Tracking
• Power Requirements, ± 12V, +5V
• Typical Power Consumption 3 Watts
• Diagnostic Outputs Available for Eye Pattern and Data Quality
Monitor
• 15 Second Abort Timer (Selectable)

Having Bell201C and cCln V.26 bls compatibility, the R24DC
offers the user a high performance 2400 bps modem that Is FCC
registered for direct connection to the dial-up network. No
re·registration of OEM equipment is required when the simple
installation instructions, supplied with the R24DC, are followed.
OEM's can easily Incorporate this Single (5" x 8") card Into their
computer terminals, communication networks, PABX equipment,
data concentrators, stand-alone box modems or almost any
application where reliable data communication Is required.

R24DC Modem

Document No. 29200N02
7-126

Data Sheet Order No. MD02
Rev. 1, August 1983

R24DC

2400 bps Direct Connect Modem

FUNCTIONAL SPECIFICATIONS

1-'-0.+-_ _'.

T

E

,
•
L

H

°

~~~===]l

N
T

E

"
F

A

o
E

o

°

DECISION

N
N

DEVICE

DIAGNOSTICS
A

MOS/LSI

E

o

IVO
FlCVDS

Ul0441

T

00'
PE

PPS4/1
MICROPFlOCeSSOR

°"

DEVICE
IA75521

OTE INTERFACE CONNECTOR

R24DC Functional Block Diagram
Transmitter Carrier Frequency -

1800 Hz ±0.01%

divided into pairs of consecutive bits (dibits). Each dlblt Is
encoded as a phase change relative to the phase of the Immediately preceding signal element. Two alternative arrangements
of coding are possible (in accordance with CCITI Recommendations V.26 and V.26 bis) as shown in the following chart.

Echo Suppression and Answering Tone Frequencies
2100 Hz ±0.01% or 2025 Hz ±0.01%.
Received Signal Frequency Tolerance - The receiver can
adapt to received frequency errors up to ± 10Hz with less than
a 0.5 dB degradation in bit error rate.

ALTERNATIVE A

00

+90 0

+2700

+1S00

ALTERNATIVE B

+450

+1350

+2250

+3150

rvVVv~

Data Signaling and Modulation Rate - The normal signaling
rate is 1200 baud ± 0.01 %, and a data rate of 2400 bps ± 0.01 %.
The fallback signaling rate is 1200 baud ±0.01%, and a data
rate of 1200 bps ± 0.01 %.

f\

Transmitted Data Spectrum - The transmitted spectrum's
bandwidth extends from 800 Hz to 2800 Hz. Phase distortion
characteristics are within the limits specified in CCITT Recommendation V.26 bis. The out of band signal power limitations
meet those specified by Part 68 or Tariff 261 of the FCC's regulations, and typically exceed the requirements of international
regulatory bodies as well.

AI!\ J!\ J!\,h!\

V lTVVWV\.J

Reference Line Signal Diagram (V.26 A&B)
At 1200 bps, differential2-phase modulation is employed. Each
bit to be transmitted is encoded as a phase change relative to
the phase of the immediately preceding signal element. The
encoding is in accordance with CelTT Recommendation V.26
bis as shown in the following chart.

Data Encoding (DPSK) - At 2400 bps, differential 4-phase
modulation is employed. The data stream to be transmitted is

1200 BPS
2400 BPS

eiT

PHASE CHANGE

0
1

+90°
+270°

PHASE CHANGE
OIBIT

V.26A

00
01
11
10

00
+90 0
+180°
+270°

V.26B/Boll 201
+45 0
+135°
+225°
+315°

Turn On Sequences - A total of six selectable turn on
sequences can be generated by the transmitter of the R24DC,
as shown in the following chart.

7-127

D

R24DC

2400 bps Direct Connect Modem

TYPEDI'
LINE
.SIGNAL

SEGMENT'

SEGMENT 2

TURN'()N
SEQUENCE
NUMBER

CONTINUOUS
UNSCRAMBLED
ONES

CONTINUOUS
SCRAMBLED'
ONES

1
2
3
4
6
8

SOml
8.33ml
148.3 ml
8.33 ms
220ml
8.33 ma

Oml
81.87 ml
Oml
140ms
Oml
211.7 ms

"

TOTAL OF
SEGMENTS
'.2
NOMINAL
TOTAL
TURN ON
SEQUENCE
TIME2

COMMENTS

SOml
90ml
148.3 ml
148.3 ml
220m.
220ml

V.28. V.28 bls
(scrambler Innrted)
8ell 201C
(scrambler Innrted)
V.2B bll
(scrambler Inserted)

As II evident from the Ibove for thon turn·on sequence. for which tha Icrembler II Innrted. the tran.mitted line signal corresponds to a
contlnuou ... on .... unscrambled. for 8.33 m.·t.n b.ud (symbol) Interval. - follow.d by the transmission of a continuous "one". scrambled.
for the remainder of the turn-on sequence.

Turn Oft Sequence - When the R240C transmitter has been
sending data and Request·to·Send Is turned off, any remaining
data bit Information Is transmitted within 6 milliseconds.

Clamping - The following clamps are provided:
1. Received Data. The Received Data output is clamped to
a mark when Carrier Detect Is off. This action prevents
disturbances on the line from getting through the receiver
circuit to the data output.
2. Carrier DeteCt Clamp. The Carrier Detect outpulls clamped
off (squelched) during the time when Aequest·to-Send Is on.
An option extends this clamp for 146 ms beyond transltlonlng
off; thus providing echo protection.
3. Receive Clock Clamp. The Receive Clock output is clamped
off when Carrier Detect Is off. This action prevents any disturb·
ances from propagating through the receiver circuit to the
receive clock output.

Re.pon.e Tim.. of Cle.r-to-Send - The Clear-to-Send
response times are determined by the selected configuration
of the R240C and Its associated turn·on sequence, as shown
In the following chart.
CLEAR·TO.aEND
RESPONSE TIMESI

TURN·ON
SEQUENCE
NUMBER

Ol'I'·TO'()N

ON·TO'()FF

COMMeNTS

1
2
3
4
6
B

90ml
90m.
148.3 ml
148.3 ms
220 ml
220 ml

oml

V.28 bls
V.28 bll w/lcrambl.r
8ell201C
Bell 201 C w/scrambler
V.28 bll
V.26 bll w/lcrambl.r

Oml
Oml
ml
Oml
Om.

o

Equalizer - The R240C contains a fixed compromise delay
equalizer, which can be used to Improve performance over the
domestic switched network. The equalizer may optionally be
positioned In the receiver, or removed enllrely, by means of a
Jumper plug. The equalizer has a nominally flat 0.0 dB amplitude
response,

The tolerence on each Off·to·On .nd On-to.()ff relponse tim. II
(+3.4. -0.1) mi.

Te.t Pattern Generation - The scrambler/descrambler func·
tlon can be used to Implement a 127·blt test pattern feature, For
example, a constant mark input could be scrambled and trans·
mltted as a pseudo-random signal to be descrambled at the
receiver back to the constant mark. A transmission error would
be represented as a space for the duration of an Incorrect bit.

Scrambler/Deacrambler - The R240C Incorporates a self·
synchronizing scrambler/descrambler. This feature Is enabled
by a discrete digital Input.
Carrier Detection - The receiver circuit of the R240C contains
a received line signal detector which Indicates the presence of
energy at the receiver input above a certain threshold for a mini·
mum amount of time.

Receive Level - The R240C receives line Signals from 0 to
-43 dBm.

Carrier Detect Thresholds
Racllvad Laval

Carrllr Datact

Greater than -43 dBm
Lesl than -48 dBm

On (Line signal prellnt)
Off (Line Ilgnal not present)

Tranamlt Timing - The R240C generates a Transmit Clock
having the following characteristics: Frequency - 2400 Hz
± 0.01 % (1200 Hz ± 0.01 % In fallback mode), duty cycle - 50
± 1%. The R240C is also optionally capable of tracking an
External Transmit Clock supplied by the user. Both have similar
characteristics.

Carrier Detect Response Time
Carrier Oeteat Tranlltlon
Off·to·On
On-lo·Off

Receive Timing - The modem provides a data derived Receive
Clock output In the form of a nominal squarewave (50 ± 1% duty
cycle). The modem timing recovery function Is capable of track·
ing a ± 0.01 % frequency error In the associated transmit timing
source,

RuponnTlma
14±.1 ml
8±'3 ml

7·128

R24DC

2400 bps Direct Connect Modem
Data Structure

Transmit Level - The R24DC transmitted output line signal
level may be regulated in either the permissive or programmable
modes. In the permissive mode, the transmitted line signal level
is -9 dBm maximum. In the programmable mode, the transmitted
line signal level is set by an external resistor installed by the
telephone company in the wall Jack. Using this method, the transmitted line signal level can be controlled in increments of 1 dBm
from 0.0 to -12 dBm, depending on the value of resistance
installed.

INPUT
DATA
SIGNALLING
RATE
SELECTOR
(P1·1S)

Answering Tone Generation - When in the automatic answering mode, the R24DC generates a selectable answering tone
of 2100 Hz ± 0.01 % or 2025 Hz ± 0.01 %. It is also capable of
optionally providing this tone when in the manual answer mode.

V.2SA/B
(P1·l4)

DATA STRUCTURE

Low

Low

2400 bps Alternate A

Low

High

2400 bps V.26 Alternat. B
(Bell 201C)

High

Low or High

1200 bps

Abort Timer- The R24DC contains a 15 ± 1 second abort timer,
which may be enabled via the Abort Enable input.

Answering Tone Frequency
INPUT
SELECT 1
(P1·34)

ANSWERING TONE
FREQUENCY

High
Low

2100 Hz
2025 Hz

Line Current Interrupt Disconnect - The R24DC contains a
475 ± 125 ms line current interrupt abort timer, which may be
enabled via the LCIS Enable input.
The digital interchange circuits provide control, status indicators,
data clocks and data interface. Traditional RS232-type control
functions and additional signals allow the user to access the
inherent flexibility and monitoring capabilities of the R24DC.

Satellite Option and DSR Selection

Satellite
Option

DSR (Pl-30)
During Analog
Loopback

AL-DSR Enable
(Pl-12)

Yes
No
Yes
No

OFF (High)
ON (Low)
ON Low)
OFF (High)

High
Low
Wired to Analog Loopback
Wired to Analog Loopback 1.

Carrier Detect Squelch
INPUTS

1. Inverse of Signal applied to Analog Loopback Input.

Baud Clocks - Symbol or baud timing is available for both the
transmitter and receiver functions. These signals have characteristics similar to the data clocks except that their frequency is
equal to the signalling rate of 1200 Hz ± 0.01 %.
Analog Loopback - The R24DC can be locally commanded
into local analog loopback (CCITT Loop 3) via digital input Analog
Loopback, when in the wait mode.

ANALOG
LOOPBACK
(P1·33)

SELECT 2
(P1·3S)

Low

Low or High

Low or High

No Squelch

High

Low or High

Low

Squelch

High

High

Low~>High

Extended Squelch 2

High

Low

Low->High

No Extended Squelch

REQUEST·
TO-SEND
(PH 1)

SQUELCH STATUS 1

"Squelch" means that Carrier Detect is clamped off (high) regardless,of the level of received line signal. When "extended squelch"
is enabled, squelch occurs both during the time when Request-

to·Send is on (low) and for 148.3 ms (+3.4, -0.1 ms) following
the On-ta-Off transition of Request-ta-Send.

Selection Of Clear-To-Send Response Times
INPUTS

CLEAR-TO-SEND
RESPONSE TlME1

TURN-ON
SEQUENCE

SELECT 1
(P1·34)

SCRAMBLER
ENABLE
(PHS)

SELECT 2
IP1·3S)

OFF-TO'()N

ON-TO-OFF

1
2

High
High
Low
Low
High
High

Low
High
Low
High
Low
High

Low
Low
Low or High
Low or High
High
High

90
90
148.3
148.3
220
220

0
0
0
0
0
0

3

4
5
6

1mB)

The tolerance on each Off-to.()n and On·to·Off response is (-3.4, -0,1 msl.

7-129

II

2400 bps Direct Connect Modem

R24DC

± 1.5

OPERATING MODES

be on. Then DP (normally off) is pulsed at a rate of 9.5
pulses per second.

Line connect and disconnect sequences are controlled automatically by the R24DC which is at all times in one of the following
modes:

The pulse requirement is a uniform train with break intervals at
58% to 64%.
The interdigit time (i.e., the time between the end of the last pulse
of a given digit and the beginning of the first pulse of a subsequent digit) should be between 700 ms and 3 seconds.

Wait Mode - This is a hot-standby mode. The R24DC enters
this mode upon a power-up, Reset, or whenever an operational
mode is exited. The following diagrams illustrate the sequence
of events for the Wait mode.

C.O.P. is turned off after the called modem answers. Signal
sequence for this mode is shown in the following diagram.

INlTlAUlE
OH" HIGH
DATA SET READY., HIGH
SQUELCH = ACTIVATEO

RESET ABORT TIMER
DISABLE REQUEST TO SEND

Automatic Call Mode Sequence
Manual Answer Mode - This mode provides the capability of
manually answering calls with a telephone ·set. Signal sequence
for this mode is shown in the following diagram.
DATA SET

;;;;I:A~------;;;;;-----

--=~------~ION (

Analog Loopback Mode - This mode provides the capability
of diagnosing a problem in the communications link. In this
mode, the transmitter's analog output is connected to the
receiver's analog input through an attenuator.

IiFENA8lEO
BY AST

ENABLEI

Manual Answer Mode Sequence
Automatic Answer Mode - This mode provides the capability
of automatically answering calls. Signal sequence for this mode
is shown in the following diagram.

DATA
TERMINAL
READV

~L_O'_ _ _ _ _ _ _ _ _ _ _ _ _ _---;"-'~

(

MODEM

""I
ANSWERING

6~~~RATION

; ' F .lST ENABLE

(

""'1"

=_-,
OFF,
L:-"''-_ _ _ _ _ _ _ _ _..." ~

__

r--~----~'l
.... :.._::~s LOW

ANSWERINc"
TONE

_ _ _....:::.'-_ _ _- ' ; -_ _ _ _ _ _ _- ' , ; -_ __

O,A'A"O,~ET ----:::-:-----""\,:::1
.

~i~~~NAL

~

OFF HOOK

V

\ \

~L_ _ _ _~~~_+-__~

ANSWERING
TONE
GENERATION

Manual Originate Mode - This mode provides the capability
of manual call origination. Calls may be originated in the usual
manner by a telephone set. Signal sequence for this mode is
shown in the following diagram.

(~

((

I

Wait Mode Flow Diagram

--------',n~1

\.

~

\

-',
..,

~!~
\.'--;;;:;oQ"K

/oFF HOOK:

I

I

ONHOOK

,.. -lr- \ . -ll-,.. ~

Manual Originate Mode Sequence

----------i~~-----:

T

Automatic Call Mode - This mode provides the capability
of automatically originating calls by using the pulse dialing
technique.

['

.

ON

OFF

I

IS· = 275 ms If satellite option IS selected
"" 65 ms If satellite option IS not selected

The R24DC allows the user to auto dial by controlling inputs
DTR, C.O.P. and DP. To originate a call, DTR and C.O.P. must

Automatic Answer Mode Sequence

7-130

2400 bps Direct Connect Modem

R24DC
INTERFACE CRITERIA

Analog Interface Circuits - The analog interface circuits
defined in the following charts provide power and switched network connections and a means for the user to monitor the incoming line signals.

The R24DC interface signals are classified as digital interchange
signals and analog signals. These signals interface to the user
through the board edge connector.

Analog Interface Circuits

Digital Interchange Circuits - The characteristics of the
R24DC digital inputs and outputs are given in the following
charts.

TERM

PIN
NUMBER

DESCRIPTION

Digital Input Characteristics
Input Logic State
Low
High

Allowed Input Voltage Levels
O.OV to O.BV sinking <10 IJ.A
+4.0V (VSS - IV) to +5.0V (VSS)
sourcing <10 u.A

The
The digital inputs are directly CMOS compatible.
capacitive loading on each input is 25 pF (maximum!.

+12V

Pl·40

-12V

Pl·38

-12V Power Supply

+5V

Pl-l

+5V Power Supply

COMMON

PI-2,
PI-4

Ground (signal and power return)

Receiver
Analog

PI-32

Low impedance output of R24DC
receive filter. Gain from Tip and
Ring to Receiver Analog is nominally 12.7 dB

+12V Power Supply

Digital Output Characteristics
Ouput Logic State
Low
High

TELEPHONE INTERFACE
LEADS

Allowed Output Voltage Levels
O.OV to OAV sinking 0.36 mA
4.0V (VSS - IV) to 5.0V (VSS)
sourcing 100 IJ.A

The digital outputs are directly CMOS or low-power Schottky
TTL compatible.

TIP
RING

P2·9
P2-10

PR
PC

P2-2
P24

for programmable mode

MI
MIC

P2-3
P2·1

Leads routed to contact on exclusian key of associated telephone

Telephone Line Leads

Leads to external wall jac k resistor

set

DIGITAL OUTPUT CHARACTERISTICS
(EXCEPTIONS)
The exceptions to the above are outputs OH, RI, SH and A. Outputs OH, RI and SH have the following characteristics:

R240C

Output Logic State

Allowed Output Voltage Levels

Low
High

O.OV to OAV sinking 0.36 mA
2AV to 5.0V (VSS) sourcing 100 p,A

RECEIVED ANALOG
DIAL PULSE

COP

CF
DB

cc
BS
DO

Output A, useful in the generation of eye pattern and diagnostic
information, switches from +S.OV to -12.0V.

CE

li~~~CTS

CARRIER OET

TX DATA elK
QSA
RX DATA
RX DATA elK
SH

RI·

OH

DATA SIGNALLING

Audio Interface Input Impedance
Parameter
On·Hook DC

CA
CH
SA
DA

Specification

CO

DC resistance between Tip and Ring, and

~~~~~

RTS
RATE SET
TX DATA
EXT TX CLOCK

TELEPHONE
INTERFACE LEAOS

OTR

between either Tip or Ring and signal
ground is greater than 10 megohms for
DC voltages up to 100 volts.
ABT

On-Hook AC

SCRAMBLER
ENABLE
ABORT
ENABLE

between Tip and Ring is less than 40 K
ohms (15.3 Hz minimum)
Off-Hook DC
aff~Hocl<

AC

Longitudinal
Balance

CONFIGURATION

ENABLE

On-hook AC impedance measured

)

CONTROLS MAY
BE STRAPPED HIGH

OR lOW AS DESIRED

LeSI
ENABLE

Less than 200 ohms
600 ohms riOminai when mea&Llfecl
between Tip and Ring

NOTES

Meets requirements of FCC Rules,
Part 68

.. ReQUIRED IF AUTO ANSWER IS IMPLEMENTED
** AUTOMATIC CALLING CAPABILITY CAN BE EASILY IMPLEMENTED WITHIN THE OTE

FCC Registration Number" AMQ9SQ-68813-DM-R
Ringer Equivalence. 098

Typical R24DC to OEM Interconnections
for Half-Duplex Applications

7-131

R24DC

2400 bps Direct Connect Modem

r -----

MI

(111

-,

I

I
131

MI
MIC

MIC

(1l1

PR

121.

PC

"'I

TO OTE

I

I

STANDARD
MINIATURE
PLUG

----

L

141

~RD

,

I

~E~M~

NOT USED

EX

2

3

NETWORK
TN

RM

,J

4

XI

~IJI~

I

5

I
I

6
7

,),

+

EX

8
RN

:

t'

}TONETWOR K

RN

BRIDGING
TRANSFORMER
(HI·Z)

TElEPHONE HANDSET
TYPE RTC
OPTIONED FOR DATA SET
CONTROL OF THE LINE

MIC

NOTES

3
4

MI AND MIC ARE REQUIRED ONL Y IF HANDSET IS EMPLOVED.
PR AND PC ARE REQUIRED FOR PROGRAMMABLE MODE ONLY
STANDARD TELEPHONE
PROVIDED JACK RJ16X, RJ45S OR RJ415
RJ36X OR CONNECTING BLOCK IS REOUIRED ONLY IF TELEPHONE HANDSET IS EMPLOYED WHEN THE R24DC IS IN THE
PERMISSIVE MODE, THE RJA2X ADAPTER AND RJ11C JACK MAY BE EMPLOYED WITH THE ASSOCIATED TELEPHONE SET

co

Typical R24DC to Network Interconnection
Telephone Line and OEM Connections - Connection of the
R24DC telephone interface pins to the network is made via
standard jacks and plugs. A typical installation, including an
optional telephone set, is illustrated.

Timing Jitter - The maximum steady state timing jitter of
Received Clock with respect to Transmit Clock is less than 10%
pop for an input signal-to-noise ratio of 12 dB.
Bit Error Rate - The following graph represents typical R24DC
performance.

Telephone Set - If it is desirable to have manual call origination or alternate voice capability, an exclusion key telephone set
(configured as Modem Controls the Line) may be ordered from
your local telephone company.

0-

=
-+- r:\ t,o .......
=®~

Mounting and Signal Routing - The R24DC may be physically
incorporated into your OEM end product by using either the four
corner (0.156 inch) diameter mounting holes or by using board
guides. The electrical interface is via edge connector(s).

"

.~

r-

\® fj ~®

CD,

.\--

~- ---1-- -

. =\= -

Interface Mating Connectors
Typel
Manufacturer
Type:

Winchester:
T&B Ansley:
Spectra-Strip:

P1 (DTEI Connector
40pin
0.100 in. spacing
20 pins per side
53-40-0
609-4015M
807-4005-001

P2 (Telephone Linel
Connector

!\ .

,," ,
1

PERFORMANCE DATA
The R24DC is a high performance synchronous 2400 bps DPSK
modem, utilizing a coherent demOdulation technique to achieve
reliable operation over the switched network or unconditioned
lines.

,\ .
I

\

1\

i

0

.

53·10-0
609·1015M
807·1005-001

!

I

\

,,',

10 pin
0.100 in. spacing
20 pins per side

I

\

1\

:j~ -1\

7

8

9

10

11

12

13

14

1200 BPS, BACK.TO BACK, SCRAMBLER, NO EQUALIZER

2

2400 BPS, V 26A OR S, BACK TO.BACK, SCRAf..tSLER,
NO EQUALIZER

3

2400 BPS, V 26A OR S, 150.150 HZ PHASl! JITTER, NO
SCRAMBLER, NO EQUALIZER

4

2400 BP~, ~ ,26A OR B. 30° 120 HZ PHASE JITtER, NO
SCRAMBLER, NO EQUALIZER

5

2400 BPS, V .28A OR S, 3002 UNCONDITIONED LINE,
NO SCRAMBLER, EQUALIZER

Typical Bit Rate Performance

7-132

15

SIONAL TO NOISE RATIO fDBj

2400 bps Direct Connect Modem

R24DC

Phase error and eye pattern can be extremely useful for modem
acceptance testing, product evaluation, and observation of line
signal quality under actual operation.

Phaae Error - Phase error can be measured by using the
modem's output signals PE, SYC, and A. With an external test
circuit, a numerical value can be derived to Indicate the quality
of received data. This numerical value can be directly correlated
to bit error rate performance. The required test circuit can be
Implemented with discrete circuitry or In software within a
microcomputer.

POWER REQUIREMENTS

Eye Pattern - By using the modems digital output signals
RCVDS, SYC, and A along with an added test circuit, the user
can generate an oscilloscope quadrature eye pattern. This pat·
tern displays the received signal as a group of dots In the base·
band signal plane; hence, It is a graphic representation of
modem performance.

+6 VDC.±.6%
+12 VDC±6%
-12 VDC.±.6%

100 mil p.p
60 mV p.p
60 mV p.p

110mA
70mA
140mA

Operating Temperature: O·C to 60·C
Storage Temperature: -40·C to + 90·C
Relative Humidity: to 95% (non·condensing)
Altitude: -200 to 10,000 feet (-61 meters to 3,049 meters)
Burn·ln: 96 hours at 70·C

DISPERSION DUE
TO PHASE ERRORS

RE RESENTS
PROPER POSITION OF
HIGH QUALITY SIGNAL

Maximum
Curr.nt

ENVIRONMENTAL SPECIFICATIONS

DISPERSION
DUE TO GAIN
ERRORS

CIRc~e

Rlppl.

Voltag.

DISPERSION AROUNO
PROPER POSITION DUE
TO COMBINATION OF
RANDOM NOISE. PHASE
ERROR. ANDIOR GAIN
ERROR.

MAXIMUM DIMENSIONS
Width: 4.988 In. (12.669 cm)
L.ength: 7,900 In. (20.066 cm)
Height: 0.500 In. (1.270 cm)

Typical Eye Pattern: 4 Phaae·2400 BPS·1200 Baud (V2SA)

7·133

R24LL
Integral Modems

'1'

Rockwell

R24LL
2400 BPS MODEM

INTRODUCTION

FEATURES

The Rockwell R24LL is a high-performance serial synchronous
2400 bps DPSK modem. By utilizing state-of-the-art MOS/LSI
technology, the R24LL provides the user with enhanced performance and reliability In a small package. Implemented on a
single printed circuit board, the R24LL is less than 26 square
inches.

• High Performance-Low Cost
• LSI High Density-Low Power
• Bell 201 BIC, CCITI V.26 AlB Compatibility and V.26 bis
AlB Compatibility
• DTE Interface LSTTLICMOS Compatibility
• External Transmit Data Clock Tracking
• Diagnostic Outputs Available for Eye Pattern Generation and
Data Quality Monitoring
• Fixed Compromise Equalizer (Strap Selectable)
• 2400/1200 bps Modes
• Transmitter-Differential Phase Modulation
• Receiver-Coherent Phase Detection
• Operating Modes:
-Half-Duplex (2-wlre)
-Full-Duplex (4-wire)
• Outstanding Performance Over Unconditioned Lines
• V.27 ScramblerlDescrambler Compatibility
• Answer-Back Tone Generation
• Clear-to-Send Delay Options
• NSYNC Option for Rapid Resynchronization in Multi-Point
Applications
• Small Size-Less than 26 sq. in.
• Typical Power Consumption-3 watts
• Power Requirements, +5 Vdc and ± 12 Vdc

The R24LL operates in either the full-duplex (4-wire lelephone
connection) or half-duplex (2-wlre telephone connection) mode.
The R24LL is designed for easy Integration into a user's system,
e.g., a simple box or rack-mount modem, statistical multiplexor,
error controlier, terminal, PBX, or any other communications
product that requires the utmost in reliability and performance
for data transmission over voice-grade telephone lines.
The R24LL Is ideal for data transmission applications over either
2-wire or 4-wire leased (dedicated) telephone lines or the dialup telephone network. Beli 201 BIC, CCITI V.26 AlB and V.26
bis AlB compatible, the R24LL modem offers the user flexibility
in creating a 2400 bps modem design customized for specific
packaging and functional requirements.

Document No_ 29200N05
7-134

Data Sheet Order No_ M005
Rev. 1, March 1983

R24LL

2400 BPS Modem

COMPROMISE
EQUALIZER

REC IN

VOLTAGE
REF
EQIN
REF

CARRIER
DETECT
CIRCUITRY

RECEIVER
DEVICE
SAMPLE
AND
HOLD/DAC

MOS/LSI
TRANSMITTER
OSC
DIVIDER

T1

REF

TRANSMIT
DAC

REC
OSC
DIVIDER

(11043)

TRANSMITTER
DEVICE

MOS/LSI
(11044)

MOS/LSI
(11042)
DIGITAL
INTERCHANGE
CIRCUITS

DIAGNOSTICS
A

SYC
RCVDS
PE

R24LL Functional Block Diagram

FUNCTIONAL SPECIFICATIONS
Transmitter Carrier Frequency-1800 Hz:!: 0.01%

Data Encoding (DPSK)-At 2400 bps, differential 4-phase
modulation is employed. The data stream to be transmitted
divides into pairs of consecutive bits (dibits). Each dibit is encoded
as a phase change relative to the phase of the immediately preceding signal element. Two alternative arrangements of coding
are possible (in accordance with CCITT Recommendations V.26
and V.26 bis) as shown in the following chart.

Echo Suppression end Answering Tone Frequencles-2100
Hz :!: 0.01 % or 2025 Hz :!: 0.01 %
Received Signal Frequency Tolerance-The receiver can
adapt to received frequency errors up to :!: 10Hz with less than
a 0.5 dB degradation in bit error rate.
Data Signaling and Modulation Rate-The normal signaling
rate is 1200 baud :!: 0.01 % and a data rate of 2400 bps :!:
0.01%. The fallback signaling rate is 1200 baud:!: 0.01% and
a data rate of 1200 bps:!: 0.01 %.

II

Data Encoding
2400 BPS
i

Transmitted Data Spectrum-"I he transmitted spectrums
bandwidth extends from 800 Hz to 2800 Hz. Phase distortion
characteristics fall within the limits specified in CCITT Recommendation V.26 bis. The out-of-band signal power limitations
meet those specified by Part 68 of Tariff 261 of the FCC's regulations and typically exceed the requirements of international
regulatory bodies as well.

7-135

Phase Changa

Dlblt

V.26A

V.26B/Bell 201

00
01
11
10

0'
+90'
+180'
+270'

+45'
+135'
+225'
+315'

R24LL

2400 BPS Modem
0'

ALTIRNAn;;

~ f\

+110'

+270'

Turn Off Sequence-When the transmitter has been sending
data and "Request-to-Send" is turned off, any remaining data
bit Information transmits within 6 milliseconds.

+180'

h~

vvvvv
ALTERNATIVE B

+45'

+135'

+225'

Reeponee Tlm.e of Clea ....to-S.nd-The selected configuration of the R24LL and Its associated turn-on sequence determine the Clear-to-Send response times, as shown In the following
chart.

+315'

¥~¥

Scrambl.r/Deecrambler-The R24LL Incorporates a selfsynchronizing scrambler/descrambler enabled by a discrete digital input.

Reference Line Signal Diagram (V.26 AlB)

Carrier Detection-The R24LL contains a received line signal
detector. This detector indicates the presence of energy at the
receiver input above a certain threshold for a minimum amount
of time.

At 1200 bps. dlfferential2-phase modulation Is employed. Each
bit to be transmitted Is encoded as a phase change relative to
the phase of the Immediately preceding signal element. The
encoding Is In accordance with cCln Recommendation V.26
bls as shown in the following chart.

Carrier Detect Threeholde

Data Encoding

Received Levil

1200 BPS

Greater than -43 dBm
Less than -4B dBm

Bit

Ph... Change

0

+90'
+270'

1

Carrllr Oltect
On (line signal present)
Off (line signal not present)

Carrier Detect Reepon.. Time

Turn On Sequences-The transmitter of the R24LL can generate a total of 13 selectable turn-on sequences, as shown in
the following chart.

Carrlar Dataet Tranaltlon

R,apon.. Tlma

Off·to-On
On-to-Off

14 ± 1 ms
8:!: 3 ms

Turn-On S.quences
Type 01
Line Signal

Sagman! 1

Sigmant 2

Total 01
Segments 1, 2

Turn·On
Sequence
Number

Continuous
Un8crambled
On..

Continuous
Scrambled1
Ona.

Nominal Total
Turn On Sequence
Tlme a

1

2
3
4

5
6
7
8
9
10
11
12
13

Oms
6.67 ms
8.33 me
30 ms
6.33ms
90 ms
B.33 me
148.3 ms
8.33 ms
220 ms
B.33 ms
800 ms
8.33 ms

Oms

o ma
Oms
Oms
21.67 ms
Oms
81.67 ms
Oms
140 ms
Oms
211.7 ms
Oms
791.7ms

Oms
6.67 ms
8.33 ms
30 ms
30 ms
90 ms
90 ms
148.3 ms
148.3 ms
220 ms
220 ms
800 ms
BOO ms

Comments

V.26
(scrambler Inserted)
V.26, V.26 bls
(scrambler Inserted)
(scrambler inserted)
V.26 bis
(scrambler Inserted)
V.26 bls
(scrambler Inserted)

Notes:
1. See paragraph titled Scrambler/Oescrambler for a description of scrambler/descrambler facility.
2. For those turn-on sequences in which the scrambler Is Inserted, the transmitted line signal corresponds to a continuous "one", unsorambled,
for 8.33 ms-ten baud (symbol) Intervals, followed by the transmission of a continuous "one", scrambled, lor the remainder of the turn-on
sequence.

7-136

2400 BPS Modem

R24LL
Clear-To-Send Response Times
Turn-On
Sequence
Number

CI.....Ta-Send
Response Time.·
Off-ta-On

On-to-Off

Equalizer-The R24LL contains a fixed compromise delay
equalizer which improves performance over the domestic
switched network. The equalizer may optionally be positioned
in the receiver or removed entirely by means of a jumper plug.
It has a nominally flat 0.0 dB ampl~ude response.

Comments

1

Oms

Oms

2

6.67 ms

Oms

switched carrier
4-wire (BELL 201)

3

B.33 ms

Oms

switched carrier
4-wire

4

30ms

Oms

CCITT 4-wire

5

30ms

Oms

CCITT 4-wire with
scrambler

6

90ms

Oms

CCITT 2-wire

7

90ms

Oms

CCITT 2-wire with
scrambler

B

1433 ms

Oms

switched carrier
2-wire

9

143.3 ms

Oms

switched carner
2-wire with
scrambler

10

220ms

Oms

CCm2-Wlre
echo protection

11

220ms

Oms

Switched 2-wlre
echo protection with
scrambler

12

BOOms

Oms

CCITT 2-wire auto
call

13

BOO ms

Oms

CCITT 2-wlre auto
call with scrambler

Test Pattern Generation-The scrambler/descrambler function can be used to implement a 127-bit test pattern feature. For
example, a constant mark input could be scrambled and transmitted as a pseudo-random signal to be descrambled at the
receiver back to the constant mark. A transmission error would
be represented as a space for the duration of an incorrect bit.
Receive Level-The R24LL receives line signals from 0 to -43
dBm.
Transmit Timing-The R24LL generates a Transmit Clock with
the following characteristics: Frequency-2400 Hz ± 0.01 %
(1200 Hz ± 0.01% in fall back mode), duty cycle-50 ± 1%.
The R24LL can also optionally track an External Transmit Clock
supplied by the user. Both have similar characteristics.
Receive Timing-The R24LL provides a data derived Receive
Clock output in the form of a nominal squarewave (50 ± 1%
duty cycle). The timing recovery function can track a ± 0.01%
frequency error in the associated transmit timing source.
Secondary Channel-The R24LL provides the user sufficient
flexibility to add an external secondary channel if desired. (A
secondary channel is a data transmission channel having a
lower Signalling rate and occupying a different portion of the telephone line bandwidth than the primary channel. The primary
and secondary channels share the same transmission facility,
the telephone line.) Additional receive filtering to allow simultaneous operation of the secondary channel must be provided
external to the R24LL.

Note:
• The tolerance on 'each Off-to-On and On-to-Off response
time is (+.9, -.1) ms.

TransmH Level-The transmitted output line signal level of the
modem is -1.0 dBm ± 1.0 dBm when the transmitter output is
terminated with a 600 ohm resistor in series. This applies to all
possible transmitted data patterns both at 2400 bps and 1200
bps, as well as to answering tone generation.

Clamping Options-The following clamps are provided with
the R24LL:

1. Received Data. The Received Data output is clamped to a
mark when Carrier Detect is off. This action prevents disturbances on the line from getting through the receiver circuit
to the data output.

Answering Tone Generation-The R24LL can generate an
answering tone at 2100 Hz ± 0.01% or 2025 Hz ± 0.01%
(selectable) for 3.4 ± 0.2 seconds under the control of an input
logic signal (CAUTO). The R24LL also provides a digital output
(TONA) indicating the conclusion of answering tone generation.

2. Carrier Detect Clamp. The Carrier Detect output is clamped
off (squelched) when Request-to-Send is on. An option
extends this clamp for 148 milliseconds beyond trans~ioning­
off, thus providing echo protection.

New Sync-Pulsing the New Sync (NSYNC) dig~al input forces
Carrier Detect Off and causes the R24LL to resynchronize rapidly on sequences of incoming messages. This feature is necessary in some polling applications because the receiver
maintains the timing information of the previous message for
some time after it has ended-this may interfere with resynchronization on receipt of the next message from a different
remote transmitter.

3. Receive Clock Clamp. The Receive Clock output is clamped
off when Carrier Detect is off. This action prevents any disturbances from propagating through the receiver circuit to the
receive clock output.

7-137

R24LL

2400 BPS Modem

Fast Energy Detector-A received line signal detector, the fast
energy detector~s output (RLSD) has the same threshold and
hysteresis characteristics as the Carrier Detect. For RLSD the
maximum turn-on time is 1.6 ms and the maximum turn-off time
is 6.6 ms (both times for Equalizer not inserted). Furthermore,
the RLSD output will respond to transient line conditions (no
momentary dropout or momentary-on glitch protection).

CP15, RW/4W, TH09, FSYC; TCOS, and PBS. If answerback
or echo suppression tone generation capability is required, the
input CAUTO (which should be strapped low if not used) and
the output TONA are available. Implementation of the New Sync
function requires any new sync pulses to be inputted to NSYNC.
The outputs SYC, RCVDS, DCP, A, and PE can be used to generate eye pattern and phase error diagnostic information.

Baud Clocks-Symbol or baud timing is available for both the
transmitter and receiver functions. These signals have characteristics similar to the data clocks' except that their frequency
is equal to the signalling rate (1200 Hz ± 0.01%). Transitions
on Transmitter Baud Clock and Receiver Baud Clock coincide
with Off-to-On transitions of Transmit Clock and Receive Clock,
respectively. For 2400 bps operation both baud clocks are low
for the first data bit in a baud and high for the second data bit.

Analog interface connections. The GAIN-G1-G2 jumper (for
threshold set selection) should be in the proper location as
described in the table at the top of page 9. Note that input
impedance at REC IN is a resistive 15.8K ohms. If a 600 ohm
receiver input impedance is desired, an external resistor to
signal ground must be added. Take care when routing to REC
IN (for low level receive signal) from any telephone interface
circuitry. Also note that ~ is possible to insert the equalizer into
the receiver or not to insert it by use of the jumper on the board.
Implementation of a local analog loopback scheme could be
achieved in many ways, If the line interface connection as
shown in the diagram below is employed, the user can create
a local analog loopback simply by deactivating squelch. To isolate the telephone line during this loopback (no transmitted
line signal). additional cirCUitry must be added.

Analog Loopback-The R24LL provides the flexibility to implement a variety of analog loopback schemes using a minimum
amount of external circuitry.
Eye Pattern/Data Quality Detector-The R24LL outputs digital signals (RCVDS, SYC. A) which the user can decode to
generate a quadrature eye pattern. The eye pattern is a visual
(oscilloscope) display showing the received signal as groupings
of dots in the baseband signal plane. It is useful as an incoming
modem test and product evaluation tool and as an indication of
a line condition in actual operation (useful for some network
control applications).

Full-Duplex-In a full-duplex application, the user needs both
transmit and receive capabilities simultaneously. A 4-wire line
connection is required.
The only differences with half-duplex are that REC IN is no
longer connected to T1 (the transmitter and receiver have independent transmission paths) and the squelch function would be
deactivated (except during New Sync) by use of the input T2W/
4W.

The modem also outputs digital signals (PE, SYC, A) which the
user can decode to generate a data signal quality detector. This
indicates if a reasonable probability of errors is received on the
data channel.

Digital interface connection is the same as for the half-duplex.

CONFIGURATIONS

Analog interface connections. With the exception of the 4-wire
line interface, analog interface connections are the same as
half-duplex. Implementation of a variety of local or remote analog
or digital loopback schemes requires the addition of a minimal
amount of external 'circuitry.

The R24LL modem provides the user with a wide range of
modem functional configurations. Some of the possibilities are
described below.
Half-Duplex (2-Wlre)-ln a half-duplex application, the user
needs both transmit and' receive capabilities (although not
simultaneously) on a 2-wire connection.
If a hybrid (4-wire -> 2-wire) transformer is not employed as a
line interface device, REC IN would be strapped to T1 through
an external resistor, the user perhaps selecting this resistor to
produce a specific output impedance or to compensate for
losses in any line interf!ICe circuitry.

RECEIVER

Digital interface connections. In a typical application, the user
controls basic modem operation through the digital signals T103,
T105, T106, T114, T104, T115, T109, and perhaps RBCK,
T113, or TBC. (T113 is used if transmit timing is to be, locked
to t,he customer's clock; TBC may be employed to minimize certain timing delays and is useful in some multiplexing operations).
A number of digital inputs can either be fixed (tied directly and
permanently to the +5V supply [high] or to signal ground or the
-12V supply [low] in accordance with the specific requirements)
or, if the user desires programmable flexibility, these signals can
be interfaced with his equipment. Signals of this type include
T111, V26A, 1, SSGR, K, Y, TC06, 800MS, E, T2W/4W, CP04,

n

RECIN

TRANSMITIER

R

EXTE~~AL
REGISTER

TO LINE INTERFACE
CIRCUITRY

R24LL Half-Duplex Mode

7-138

T1

2400 BPS Modem

R24LL
INTERFACE CRITERIA

DCP

Pl-A21

The R24LL interface Signals are classified as digital interchange
signals and analog signals. The signals interface to the modem
user through the board edge connector.

Digital output enabling user to
generate eye pattern and phase
error diagnostic information.

R2W/4W

Pl-A22

Input affecting state of THRH
output.

Digital Interchange Circuits-The characteristics of the R24LL

Receiver Baud Clock
(RBCK)

Pl-A23

For 2400 bps operation.

digital inputs and outputs are given in the following charts:

PBS

Pl-A24

Input determining Tf09 On-to-Off
response time.

TH09

Pl-A25

Transmitted Data
(Tl03)

Pl-A29

Input affecting state of THRH
output.
Input for dlgttal data to be
transmitted.

Clear-to-Send or
Ready-for-Sending
(Tl06)

Pl-A30

Output indicating readiness to accept data for transmission.

Data Signalling Rate
Selector (TIll)

Pl-A32

Receive Clock
(T115)

Pl-A33

Input determining whether transmitted data rate is 2400 bps or
1200 bps.
Output providing received signal
element timing information.

E
T2W/4W

Pl-B6 }
Pl-B7
Pl-BB

Digital Input Characteristics
Input logic State
Low
High

Allowed Input Voltage Levels
-12V (Voo) to O.BV sinking <10 p.A
+4.0V (V ss - W) to +5.0V (V ss> sourcing
<10 p.A

The digttal inputs are directly CMOS compatible. The capacitive
loading on each input is 25 pF (maximum).

Digital Output Characteristics
Output logic Stata
Low

Allowed Output Voltage Levels
O.OV to 0.4V (-0.4V to +0.4V for RLSD)
sinking 0.36 mA
+4.0V (V ss - 1V) to +5.0V (V ss) sourcing
100 p.A

High

Y

The digital outputs are directly CMOS or low-power Schottky TTL
compatible.

Pin
Number

Pl-Bl0

A

Pl-Bll

Digital output enabling user to
generate eye pattern and phase
error diagnostic Information.

Pl-BI5

Input determining whether scrambler IS to be Inserted.

THRH

Pl-Bl B

Output used in conjunction with
carrier detect circuitry to Implement Tl09 threshold set select
function.

V26A/B

Pl-BI9

Input selecting dibit encoding at
2400 bps operation as per V.26
Mernate A or V.26 Atternate B.

CP15

Pl-B20

Input selecting optional clamping
of Receive Clock (T115).

RCVDS
SYC
PE

Pl-B21 } Digrtal outputs enabling user to
Pl-B22 generate eye pattern and phase
Pl-B23 error diagnostic information.

TC09

Pl-B24

Input determining Tl09 Off-to-On
response time.

CP04
Extemal Transmit
Clock (T113)

Pl-B25

Input determining Tf 04 damping.

Pl-B29

Input providing modem with transmitted signal element timing
information.

Request-to-Send
(Tl05)
Received Data
(Tl04)

Pl-B30

Input to transmitter.

Pl-B31

Transmit Clock
(T114)

Pl-B33

Carrier Detect
(Tl09)

Pl-B24

Digital data output from modem
receiver.
Output providing user wtth transmitted Signal element timing
information.
Output indicating presence of signal energy on receiver line.

Description

TONA

Pl-A5

Output indicating completion of
$I1swering tone.

BOOMS

Pl-A6

Input affecting Clear-to-Send response time.

TC06

Pl-A7

K

Pl-AB

Input affecting Clear-to-Send response time.
Input affecting Ready-for-Sending
response time.

X

Pl-A9

Input affecting Tl09 Squelch.

CAUTO

Pl-Al0

New Sync (NSYNC)

Pl-AI3

Input initiation transmission of answering tone.
Input affecting Tl09 Squelch.

CLAMP

Pl-AI5

Input forcing squelch of Tl09.

Fast Energy
Detector (RLSD)
Fast Sync (RSYC)

Pl-AI7

Input generating Tl09.

PI-AlB

Input determining whether fast
sync feature (fast resynchronization upon recovery of received line
signal following momentary dropout) is enabled.

SBGR

Pl-A19

Input determining whether the
modulo B pattern guard will be Incorporated Into the scrambler
faCility.
Note:

The following PI connector pin locations should be left open and unconnected:
A4, All, A12, A14, A16, A20, A35, Bl, B12, B13, B14, B17, B32, and 835.

7-139

Input affecting Ready-for-Sending
response time and answering tone
frequency.
Output baud clock (1200 Hz).

Transmitter Baud
Clock (TBC)

Digital Interchange Circuits
Term

Inputs affecting Clear-to-Send response time and Tl09 Squelch.

II

R24LL·

2400 BPS Modem
Tone Generation

Data Structure
Inputs

Input
Data Signalling
Rate Selector
(P1-A32)

Data Structure
V26 AlB
(P1-B19)

Low
Low

Low
High

High

Don't
Care

2400 bps Alternate A
2400 bps V.26 Alternate B
(Bell 201 C)
1200 bps

CAUTO
(P1-Al0)

Low
High
High
High

Outputs

Y
(P1-BB)

TONA
(P1-A5)

Transmitted Signal

Don't Care
High
Low
Don't Care

High
High
High
Low

Normal Operation
2100 Hz Answering Tone
2025 Hz Answering Tone
Normal Operation

Selection of Clear-To-Send Response Times
Clea....To-Send
Response Times
(ms)

Inputs
Turn-On
Sequence

1
2

3
4
S
S
6

6
7

8
9
9
9
10
10
10
11
12

Y
(P1-BB)

Low
High
High
High
High
High
High
High
Low
Low
High
High
High
High
High
High
High
High

BOOMS
(P1-A6)

High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
Low
Low

K
(P1-AB)

TC06
(P1-A7)

T2W/4W
(P1-B7j

Don't Care
Low
Low
Low
Don't Care
High
Don't Care
High
Don't Care
Don't Care
High
Don't Care
Don't Care
High
Don't Care
Don't Care
Don't Care
Don't Care

Don't Care
High
Low
Don't Care
High
High
High
High
Den't Care
Don't Care
Low
Don't Care
Low
Low
Don't Care
Low
Don't Care
Don't Care

High
High
High
High
Low
High
Low
High
Low
Don't Care
Don't Care
Low
Low
Don't Care
Low
Low
Don't Care
Don't Care

I
(P1-B15)

Low
Low
Low
High
Low
Low
High
High
Low
High
Low
Low
Low
High
High
High
Low
High

E
(P1-B6)
Don't Care
Don't Care
Don't Care
Don't Care
Low
Don't Care
Low
Den't Care
Don't Care
Don't Care
Don't Care
High
Don't Care
Don't Care
- High
Don't Care
Den'tCare
Don't Care

Otf-to-On

On-to-Otf

6.67
B.33
30
30
90
90
90
90
148.3
148.3
220
220
220
220
220
220
220
800

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

N·ote: The tolerance on each Oll-to-On and On-to-Oll response time is (+0.9, -0.1 ms).

Carrier Detect Squelch
Inputs

X
(P1-A9)

T2W/4W
(P1-B7)

E
(P1-B6)

T105
(P1-B30)

Don't Care
Don't Care
Low
High
High
High

Don't Care
High
Low
Low
Low
Low

Don't Care
Don't Care
Don't Care
Don't Care
High
Low

Don't Care
Don't Care
Don't Care
High
High-+Low
High-+Low

NSYNC
(P1-A13)

Squelch Status

Low
High
High
High
High
High

Squelch
No Squelch
No Squelch
Squelch
Extended Squelch
No Extended Squelch

Notes:
"Squelch" means that Carrier Detect (Tl09) IS clamped off regardless of the level of received line signal. During squelch, CLAMP
(T-13) is a low impedance to ground. For normal operation (no squelch) CLAMP (T-13) is in a high impedance ("open drain")
state.
When "extended squelch" is enabled, squelch occurs both when Request-to-Send (Tl0S) is On (High) and for 148.3 ms (+0.9,
-0.1 ms) following the On-to-Oll (High to Low) tranSItion of Tl0S.

7-140

R24LL

2400 BPS Modem
Carrier Detect Threehold Selection
Olin
Strip

Sellctld
Threlhold Sit

Gl
G2
Gl or G2

-43 dBm, -48 dBm
-33 dBm, -38 dBm
-28 dBm, -31 dBm

THRH
High Impedance
High Impedance
Low Impedance
to ground

The receiver and transmitter line Interfaces are single-ended
(non-transformer coupled) signals with the following characteristics:

Tranamltter Voice Frequency Output T1
1. Output Impedance: Impedance of Op-Amp
2. Maximum Output Level: ... 0.0 dBm as measured per the following diagram using a true RMS
meter.

Gain must be shorted to either Gl or G2.
THRH Operation
Input
THOS

THRH

R2W/4W

Low
High
Low
High

Low
Low
High
High

I

High Impedance
High Impedance
High Impedance
Low Impedance

I

I

OO",.,,'...
>-_.--_...:T.:..'1t-6-.
' %-r+~~+~~E RMS
600 •.

THRH Is an open-drain driver reprasentlng either a low Impedance to ground «500 ohms) or a very high Impedance state.

,%

Scrambler/Deecrambler
Input
I
(P1·B15)

SIOR
(P1·A1S)

Low
High

Don't Care
Low

High

High

Scrambllr/Dlscrlmbllr
Configuration
No Scrambler
Scrambler V.27 bls, ter
(modulo 8 pattern guard)
(no modulo 8 pattern guard)

Receiver Voice Frequency Input REC IN
1. Input Impedance: 1S.BK ohms ± 1% resistive
2. Maximum Input Level: .. 0.0 dBm

Analog Intertace Clrculta-The analog Interface circuits of the
R24LL defined in the following chart provide the power, the
switched network connections, and a means for the user to
monitor the incoming line signals.

The output level at the R24LL line Interface is less than -60
dBm In the frequency band of 1 Hz to 12 Hz when the modem
is not transmitting. A period of ioo milliseconds Is required for
the line Interfaces to stablize following power turn-on.

Analog Interface Clrculte

Low Impedance voice frequency output T1 satisfies applications
Interfacing with lossy transformers or hybrids. The characteristics of T1 output are:

Term

Pin
Number

+12V
-12V
+5V
COMMON

Pl-B5, B9
PI-AI
Pl-A2, B2
PI-AS, A3!, BS

Tl

Pl-A34

SECONDARY IN

Pl-B4

RECIN

Pl-BS6

Description
+ 12V Power Supply
-12V Power Supply
+5V Power Supply
Ground (signal and power
return)
Tl Is the low Impedance
transmitter analog output (line
signal). The Tl allows the
user the flexibility needed to
customize his output Impedance (to compensate for
transformer losses, for instance).
Secondary channel Input
from the DTt:.
Receive filter Input. Input
Impedance Is a resistive 15.8
K ohms:t 1%.

a. Output Impedance: Essentially zero ohms when loaded to
ground with greater than 400 ohms
(resistive). This Is a direct output from an
operational amplifier.
b. Minimum Load: ;.400 ohms (resistive) as measured between
T1 and signal ground.

PERFORMANCE DATA
The R24LL Is a high performance synchronous 2400 bps DPSK
modem. It utilizes a coherent demodulation technique to achieve
reliable operation over the switched network or unconditioned
lines.
Timing Jitter-The maximum steady state timing jitter of
Received Clock with respect to Transmit Clock is less than 10%
pop for an input signal-to-noise ratio of 12 dB.
Bit Error Rate-The following graph represents typical R24LL
performance.

Audio Intertace-The audio interface includes the R24LL's
interface with the transmission network.

7-141

R24LL

2400 BPS Modem

t-@

I--'- 2)::::'
I--

C

10- 4

~

....... @f

IA.

IT\ \

r--

- \'

\

\

\

\

typical Eye Pattern: 4 Phase-2400 BPS·1200 Baud (V26A)

\

\\

\
1\

10-6
5

REPRESENTS
PROPER POSITION OF
HIQH QUA~ITY SIQNAL

\

\ \

4

CIRC~E

-,. ~'r-

\

10-&

DISPERSION AROUND
PROPER POSITION DUE
TO COMBINATION OF
RANDOM NOISE, PHASE
ERROR, ANDIOR QAIN
ERROR.

@

ia:
III

DISPERSION DUE
TO PHASE ERRORS

---

\\

au

a:
a:
au
t:

~

\\ ~ ~ 0

.... CD

0

DISPERSION
DUETOQAIN
ERRORS

6

\

9

10

11

The R24LL connector mating contacts are not gold covered;
therefore, a high quality gas-tight card edge connector should
always be used to maintain reliable operation. Rockwell rec·
ommends the following in order of preference:

\
\\

1\ \
8

RECOMMENDED MATING CONNECTORS

\ \

\
7

Phase error and eye pattern can be extremely useful for modem
accGlPtance testing, product evaluation, and observation of line
signal quality under actual operation.

12 13

14

15

1. Burndy GTBH Series
2. Continental 6100-200 Series
3. Elco 00·6307 Series

SIGNAL TO NOISE RATIO (DB)

POWER REQUIREMENTS
1. 1200 BPS, BACK-TO-BACK, SCRAMB~ER, NO EQUA~IZER
2. 2400 BPS, V.26A OR B, BACK-TO-BACK, SCRAMB~ER
NO EQUALIZER'
3. 2400 BPS, V.26A OR B, 15'-150 HZ PHASE JllTER, NO
SCRAMB~ER, NO EQUALIZER
4. 2400 BPS, V.26A OR B, 30'-120 HZ PHASE JllTER, NO
SCRAMBLER, NO EQUALIZER
5. 2400 BPS, V.26A OR B, 3002 UNCONDITIONED LINE,
NO SCRAMB~ER, EQUALIZER

Voltage

+5 VDC ± 5%
+12 VDC ± 5%
-12 VDC ± 5%

Ripple
100 mV
50 mV
50 mV

pop
pop
pop

Maximum
Current
102 mA
64 mA
142 mA

ENVIRONMENTAL SPECIFICATIONS
Operating Temperature: O'C to 60'C
Storage Temperature: -40'C to +80'C
Relative Humidity: to 90% (non-condensing) or a wet bulb temperature up to 35'C, whichever is less.
Altitude: -200 to 10,000 feet (-61 meters to 3,049 meters)

Typical Bit Error Flate Performance

Phase Error-Phase error can be measured with the modem's
output signals PE, SYC, and A. With an external test circuit, a
numerical value can be derived to indicate the quality of received
data and then directly correlated to bit error rate performance.
The required test circuit can be implemented with discrete circuitry or in software within a microcomputer.
Eye Pattern-By using the modem's digital output signals
RCVDS, SYC, and A along with an added test circuit, the user
can generate an oscilloscope quadrature eye pattern. This pattern displays the received Signal as a group of dots in the baseband Signal plane: it is a graphic representation 0/ modem
performance.

7-142

R24.
Integral Modems

'1'

R24
2400 BPS INTEGRAL MODEM

Rockwell
INTRODUCTION

FEATURES:

The Rockwell R24 is a high performance synchronous serial
2400 bps DPSK modem, Utilizing extensive MOSILSI
technology, the R24 is implemented in three modular building
blocks, It is innovatively designed to enable its economic integration by system designers in a broad range of communication,
computer, and control equipment.

•
•
•
•
•
•
•

Having Bell 201 B/C and CCITT V,26 compatibility, the modular
R24 offers the user sufficient flexibility to customize a 2400 bps
modem to his specific packaging and functional requirements,
With a minimum amount of interface circuitry, the modem can
be configured for operation on leased lines or on the general
switched network.

•
•
•
•
•
•
•
•
•
•

MODULE VERSATILITY
The versatility of the R24 design is achieved by dividing the
modem's functions into three modules:
Transmitter - Module T
Receiver - Modules R1 and R2

LSI high density; low power
2400/1200 bps modes
Transmitter-Differential phase shift keying
Receiver-Coherent phase detection
Bell 201 B/C, CCITT V.26 compatible
CCITT AlB encoding options
Operating modes:
Half duplex (2 wire)
Full duplex (4 wire)
Simplex (Transmit or Receive only)
Outstanding performance over unconditioned lines
LSTTL/CMOS compatible digital interface
Fixed compromise equalizer
V,27 compatible scramblerldescrambler
Answer-back tone generation
Clear-to-send delay options
New sync option provides rapid resynchronization
Typical power consumption 2 watts
Total module area 25 sq, in,
R24 Modem Evaluation Board facilitates evaluation and
design-in tasks,

Each module can be plugged into standard connectors or can
be wave soldered on one or more printed circuit boards, The
pin spacing is on 100 mil centers, Modem modules are functionally independent.

MODEM OPERATION MODES
In general, the modules can be configured to operate in the
following modes:
Simplex -

Transmit only:

Only the transmitter module (T) is
used,

Simplex -

Receive only:

R1 and R2 modules are used to
implement a complete receiver
function.

Half Duplex (2-Wire):

Requires both transmit and receive
functions (although not simultaneously), therefore, all three
modules are used.

Full Duplex (4-Wire):

Requires both transmit and receive
functions simultaneously, again all
three modules are used.

Document No. 29200N01

R24 Integral Modem

7-143

Data Sheet Order No. MD01
Rev. 3, August 1983

2400 bps Integral Modem

R24

------

INTERCONNECT

~-----------Q

RECEIVER

-1 '"""' I+---Ir----....,

DATA

I CONTROL

TRANSMITTER

L"-----::-.::~~
CONTROL

INTERCONNECT

__

R24 Functional Diagram

TECHNICAL DESCRIPTION
Transmitter carrier frequency -

1800 Hz ± 0.01 %

Echo suppression and answer tone frequencies - 2100 Hz
±0.01% or 2025 Hz ±0.01%
Received signal frequency tolerance - The receiver can
adapt to received frequency errors up to ± 10Hz with less than
a 0.5 dB degradation in bit error rate.

Signaling Rate - 1200
Data Rate - 2400 bps
2) Fallback: Signaling Rate - 1200
Data Rate - 1200 bps

2400 BPS
PHASE CHANGE
V.26A
V.26B/Boll 201

00
01
11
10

0°
+90°
+180°
+270°

ALTERNATIVE A

00

+900

+45°
+135°
+225°
+315°

+2700

+1800

f\~f\hnl/\l/\

Data signaling and modulation rate:
1) Normal:

.oIBIT

vv vv \J\T\J\.TV
f\cJnA/\I/\hn
v lTV v\JlT\./V

ALTERNATIVE B

baud ±0.01%.
±0.01%.
baud ±0.01%.
± 0.01 %.

+45°

+135°

+225°

+315°

Line Signal Diagram (V.26 A & B)

Transmitted Data Spectrum - The transmitted spectrum's
bandwidth extends from 80Q Hz to 2800 Hz. Phase distortion
characteristics are within the limits specified in CCITT Recommendation V.26 bis. The out··of. band signal power limitations
meet those specified by Part 68 or Tariff 261 of the FCC's regulations, and typically exceed the requirements of international
regulatory bodies as well.

At 1200 bps, differential two-phase modulation is used. Each
bit is transmitted at a relative phase change to preceding signal
element in acordance with CCITT V.26 bis.
12.00 BPS

Data Encoding (DPSK) - At 2400 Bps, differential four-phase
modulation is used. The data stream is transmitted in pairs of
consecutive bits (dibits). Each dibit is encoded as a phase
cllange relative to the phase of the preceding signal element.

BIT

PHASE CHANGE

0
1

+90 0
+270°

Turn On Sequences - A total of twelve selectable turn on
sequences can be generated by the transmitter module.

The R24 implements the phase A and B recommendations of
CCITT V.26. The modulation coding in Bell 201 modems is the
same as V.26B. Definition of these coding arrangements is
shown in the following table:

Turn Off Sequence - When the transmitter has been sending
data and "Request to Send" is turned off, any remaining data
bit information is transmitted within 6 milliseconds.
7-144

R24

2400 bps Integral Modem
Transmit Timing - The modem generates a Transmit Clock
(T114) having the following characteristics: Frequency 2400 Hz ± 0.1 % (1200 Hz ± .01 % in fallback mode), duty cycle
- 50 ± 1%. The modem is also optionally capable of tracking
an External Transmit Clock (T113) supplied by the modem user.
T113 has similar characteristics to T114.

Ready for Sending (Tl 06) Response Times - These response
times are determined by the modem configuration selected and
its associated turn on sequence.
Turn On

Ready for Sending

Sequence
Number

Response

1

~onfiguration

and
Carrier Type

Time

667 msec

SWitched Carner

~

Receive Timing (Tl15) - The modem provides a data derived
"Receive Clock" output in the form of a nominal squarewave
(50 ± 1% duty cycle). The modem timing recovery function is
capable of tracking a ± 0.D1 % frequency error in the associated
transmit timing source.

4-Wlre

(Bell 201)
2

833 msec

SWitched Carner - 4-Wlre

3

30 msec

CCITT - 4-Wlre

4

30 msec

CCITT - 4-Wlre with Scrambler

5

90 msec

CCITT - 2-Wlre

6

90 msec

CCITT - 2-Wlre with Scrambler

7

1483msec

SWitched Carner - 2-Wlre

8

1483 msec

SWitched Carner - 2-Wlre with
Scrambler

!;!

220 msec

CCITT - 2-Wlre Echo Protection

10

220 msec

SWitched 2-Wlre Echo Protection

11

800 msec

CCITT - 2-Wlre Auto Call

12

800 msec

CCITT - 2-WIr'e Auto Call with
Scrambler

Transmitter Output Levels - This output can be strap controlled in 2 ± 0.2 dB steps from -1 dBm ± 1 dB to -15 dBm
± 1 dB.
Answer Tone Generation - The modem generates a selectable answering tone of 2100 Hz ±O.01% or 2025 Hz ±0.D1%.
The 2100 Hz tone meets CCITT Recommendations G.161 and
V.25, and the 2025 Hz tone meets Bell System requirements
for both answering tone and echo suppressor disabling tone.

with Scrambler

Equalizer - As a strap option, the modem contains a fixed compromise delay equalizer which can be used to improve performance over unconditioned schedule 3002 lines. This option is
normally positioned in the receiver, but it can be repositioned
in the transmitter or bypassed entirely. It is designed to compensate for the mean of the range of group delay distortions
generally encountered in the United States. Its amplitude
response is nominally flat at 0.0 dB.

Response Time tolerance (+ 09, -0,1) msec

Scrambler/Descrambler - As a selectable option, the scrambler/
descrambler may be inserted into the transmitter/receiver path.
The purpose of this scrambler is to ensure that the line signal
will evenly span the allocated bandwidth. This minimizes pattern sensitivity problems arising from simple fixed and periodic
data sequences. The scrambler is V.27 or V.27 bis/ter compatible.

Test Pattern Generation - The scrambler/descrambler function can be used to implement a 127-bit test pattern feature. For
example, a constant mark input could be scrambled and
transmitted as a pseudo-random signal to be descrambled at
the receiver back to the constant mark. A transmission error
would be represented as a space for the duration of an incorrect bit.

Carrier Detect (Tl 09) - The modem receiver incorporates a
line signal energy detector whose output responds to three selectable threshold levels.
Set 1 (V.26 bis, switched
network)

Greater than -43 dBm = ON
Less than -48 dBm
OFF

Set 2 (V.26 bis, switched
network)

Greater than -33 dBm = ON
Less than -38 dBm
OFF

Set 3 (V.26, leased line)

Greater than -26 dBm = ON
Less than -31 dBm
= OFF

Multipoll Synchronization - The "new sync" (NSYNC) digital
input can be pulsed to cause rapid resynchronization of the
receiver for sequences of incoming messages. This feature is
necessary in some polling applications. However, if the user's
hardware/software does not support the use of "new sync"
(NSYNC), then the optional "fast sync" (FSYNC) can be utilized
to enable a fast resynchronization procedure.

Selectable Tl09 Response Times - This time is defined as
the interval between the sudden connection or removal of the
received line signal to the modems receive filter, and the subsequent transition of Carrier Detect (T1 09) from one state to the
other.

Selectable Clamping Options 1) Received Data (T104) - This output is clamped to a selectable constant (space or mark) when "Carrier Detect" is off,
to prevent disturbances on the line from getting through the
receiver to the data output.

Carrier Detect
Transition

OFF tn ON

Response Time

6 +1

m!';

(connectIOn)

t Selectable

ON to OFF
(removal)

22 ±3 ms

8 ±3 ms

f Selectable

Receive Level -43 dBm.

2) Carrier Detect (T1 09) Clamp - This output may be clamped
OFF (squelched) in a 2-wire applications during the time When
"Request to Send" (T105) is on. An additional option extends
this clamp for 148 msec beyond T105 transitioning off, providing echo protection.

I

14; 1 ms

3) Receive Clock (T115) - This clock output can be clamped
OFF when "Carrier Detect" is off, thereby preventing any
disturbances from propagating through the receiver to the
receive clock output.

The modem receives line signals from 0 to

7-145

II

R24

2400 bps Integral Modem
As shown, a transformer is sufficient to connect directly to a
leased line in the U.S. For the switched network, registered protective circuitry or a data access arrangement (OAA) is generally
required. Rockwell offers an FCC registered protective circuitry
product to support this application. Requirements for line interface and protective circuitry vary internationally.

SYSTEM DESIGN
The R24 modem modules provide the user with sufficient flexibility
to implement a wide range of modem functional configurations.
This flexibility is achieved by digital control at the module interfaces. For a given application, such as a lease network V.26
Alternative B modem (Bell 201 B), the complexity of the user interface can be significantly reduced by strapping those data interface inputs which do not change. The modem interface can also
be under software control.

DIAGNOSTICS

TO LEASED

LlNEOR
TO SWITCHED

NETWORK
PROTECTIVE

Figures 1 and 2 show the basic interface connections for the
transmitter module (T) and the receiver modules (R1 ,R2). These
diagrams are applicable for any operation mode of the modemsimplex, half-duplex, or full-duplex.

)11

RECEIVER
CONTROL

CIRCUITRY

TRANSMITTER
CONTAOL
COMMON MODEM DIGITAL

DATA (T103)

~
V26A

I
SaGR

Figure 3.

NSYNC
CLAMP

Transmitter-Receiver Interconnection (Half
Duplex)

CAUTO

rONA
TBC
Z

~

X

INTERCHANGE
TIN

-1dBm
-$dBm
-SdBm
-7d8m
-9dBm
-11dBm

Secondary Channel - The modem modules provide the user
with all the interface connections needed to add an external
secondary channel if required. This data transmission channel
would operate at a lower rate, and in a different portion of the
available bandwidth than the primary. Additional external receive
filtering would also have to be added to allow simultaneous
operation of the primary and secondary channels.

T2W/4W
K

Y
TC06
BOOMS
E

T103

T105
Tl06
T111
T113
T114

-13dBm
- 15dBm

Figure 1.

'>

g~~~~~LS
RECEIVER

Analog and Digital Loopback - To check out or djagnose the
communication link, loopback testing is often performed. A test
word is transmitted and "looped" back to the originating OTE.
Typical types of loopback tests are:

Transmitter Interfaces

DIGITAL
INTERCHANGE

r -~1l---.J~L==-~.J-:.+--h_1I

R2W/4W

~~~~

T104

CD

LOCAL DIGITAL

®

REMOTE ANALOG

®

LOCAL ANALOG

8)

REMOTE DIGITAL

COMMON MODEM

~~':

DIGITAL CONTAOLS

CPQ4

V26A

CP15
FSye

I
SaGA

..

NSYNe
CLAMP

COMMUNICATION
CHANNEL

Figure 2.

Receiver Interconnection

MODEM OPERATION HALF OR FULL-DUPLEX

DTE - Data Terminal Equipment
The modem modules provide the user with all the necessary interfaces connections to implement almost any loopback scheme
desired. With a minimum amount of external circuitry, loopback
testing can be controlled via a communications adapter/software
approach or manually. For local analog, remote analog and
remote digitalloopback, the V.27 scrambler within the modem
can be used to generate a 127-bit word.

Figure 3 indicates the module interconnections necessary for
half-duplex operation. For full-duplex operation, the transmitter/
receiver interconnections are similar to the half-duplex case with
the exception that ','REC IN" is not connected to T2 or T1. In
full-duplex operations, the transmission and receiver paths are
independent. .

7·146

R24

2400 bps Integral Modem

INTERFACE DESCRIPTION

TRANSMITTER ANALOG CONTROLS

STANDARD DIGITAL INTERCHANGE
Term
(CellT V 24 EtA RS232C
Equivalent) Equivalent

T103

BA

T104

BB

T105

CA

T106

CB

DACOUT

Module Interface

input
T·9

Term

Output
R2·5

TFIL

T·23

TIN
-1dBm
-3dBm
-5dBm
-7dBm
-9dBm
-11dBm
-13dBm
-15dBm

T·31

Description

T·6

Ready for Sending
(Clear to Send)

CF

R1·4

T111

CH

T·12,
R2·9

Data Signalling Rate Selector
Selects 2400 bps or 1200 bps
Mode

T113

DA

T·7

External Transmit Clock
(Transmitted Signal Element
Timing)

T114

DB

T·10

Transmit Clock (Transmitted
Signal Element Timing)

T115

DO

R2·6

Receive Clock (Receive Signal
Element Timing)

R2·22

Data Channel Received Line
Signal Detector(Camer Detect)

ANALOG LINE INTERFACES

RECIN

Output

Description

Analog Line Signal Input (Receive Filter
Input)

T1

T·1

Low Impedance Transmitter Output

T2

T·2

Standard Transmitter Output 600 ohms
Impedance

V26A

Module Interface
Input
output

T·16
R2·13

NSYNC
CLAMP

Description
Receiver Baud Clock

R1·1

R2·25

RLSD
THRH
R2W/4W
TH09

R2·24
R1·3
R2·8
R2·18

R1·2 } Control Signals toGenerate Carner Detect
R2·23 (T109) and Implement T109 Threshold Set
Select Function

TC09

R2·15

Determines Carrier Detect (T109) Off-to·On
Response

PBS

R2·16

Determines Carner Detect (T109) On·to·Off
Response

CP04

R2·17

Clamps Received Data (T104) to a mark
or space when Carner Detect (T1 09) IS Off

CP15

R2·19

Optional Clamping of Received Clock (T115)

FSYC

R2·20

Fast Sync Optional Fast Resynchronlzatlon
Procedure

Descrip.lton

Controls for Scramble Operation

{ T·17

RECEIVER DIGITAL DIAGNOSTICS

R2·14
Controls n09 to Force Rapid
Resynchronlzatlon of the Receiver

T·14
R2·11
R2·10

Module Interface
output
Input

Selects V 26A or V 26B Diblt Encoding

{:i 1152}
SBGR

These Nine Signals Implement the
Transmitter Output Level Attenuator One of
the Signals -1dBm,
, -15dBm IS
Strapped to TI N to Set the DeSIred Output
Level

RBCK

COMMON MODEM DIGITAL CONTROLS
Term

T·39
T·3B
T·37
T·36
T·35
T·34
T·33
T·32

RECEIVER DIGITAL CONTROLS
Term

Module Interface

Description
Output of Digital to Analog Converter
Input to Low Pass Fliter DAC OUT IS
Normally Connected to TFIL Unless
Additional Filtering or an Equalizer IS to be
Inserted

Received Data
Request to Send

T·B

Input
R1·12

T·22

Transmitted Data

T109

Term

Module Interface
output
Input

T·13

Implements Squelch for Carner Detect
(T109)

Term

Module Interface
Input
Output

PE

R2·1
R2·2
A2-4
R2·3
R2·7

Term

Module Interface
output
Input

SYC
RCVDS
DCP

A

Description
Digital Outputs which Enable User to
Generate Eye Pattern and Phase Error
Information

TRANSMITTER DIGITAL CONTROLS
Term
CAUTO
TONA

Module Interface
output
Input
T·3

TBC

Description

T·5

Initiates Answer Tone
Indicates Completion of Transmission
of Answer Tone

T·4

Transmitter Baud Clock

Z

T·28

Input Forcing Transmit Clock (T114) to
Phase and Frequency Lock to External
Transmit Clock (T113)

T2W/4W

T·11
T24
T·25
T·26
T·27
T·29
T·30

Inputs Affecting Ready for Sending
Response Times, Answer Tone Frequency
and Carner Detect (n09) Squelch

X
K
Y
TC06
800MS
E

RECEIVER ANALOG CONTROLS
Description

RECOUT

R1·7

Receive Filter Ouput

EOIN
EOOUT

R1·B
R1·6

Equalizer Input
Equalizer Output

RLSDIN
AGCIN
AGCOU7

R1·5
R2·21
R2-26

GAIN
G1
G2

R1·11
R1·9

IANALOG

R2·27

7-147

Carner Detect Circuitry Input
Automatic Gam Control Circuitry Input
Automatic Gam Control Circuitry OUtput

R1.1Q} Optional Carner Detect (T109) Threshold
Selection Controls
Sample and Hold Circuitry Input

R24

2400 bps Integral Modem

MODEM PERFORMANCE
The R24 is a high performance synchronous 2400 bps DPSK
modem, utilizing a coherent demodulation technique to achieve
reliable operation over the switched network or unconditioned
lines. This section contains a quantitative discussion of the R24's
typical performance under varying test conditions.

DISPERSION

A.""'::=""--- ~~~6~SGAIN

DISPERSION DUE
TO PHASE ERRORS

Timing Jitter - The maximum steady state timing jitter of
"receive clock" with respect to "transmit clock" is less than 10%
pop for an input signal-to-noise ratio of 12 dB.
Bit Error Rate performance:

DISPERSION AROUND
PROPER POSITION DUE
TO COMBINATION OF
RANDOM NOISE, PHASE
ERROR, ANDIOR GAIN
ERROR

CIRCLE REPRESENTS
PROPER POSITION OF
HIGH QUALITY SIGNAL

The following graph represents typical R24

Typical Eye Pattern: 4 Phase-2400 bps-1200 Baud (V26A)

'~m'~

Phase error and eye pattern can be extremely useful for modem
acceptance testing, product evaluation, and observation of line
signal quality under actual operation.

~,

I

I

I

i
~.1p i
i 't r
i

10-4

~~

'\

I

ELECTRICAL CHARACTERISTICS

I

POWER REQUIREMENTS
Maximum

\ :

1

..

"

\
\1
7

I

:

..

\ \

\.
I

10

Voltage

Ripple

Current

T

+5 Vdc±5%
+12 Vdc ±5%
·12Vdc±5%

100 mV p.p
50mV p.p
50mV p.p

3BmA
16mA
4BmA

Rl

+12 Vdc ±5%
·12 Vdc±5%

50 mV p.p
50 mV Pi>

23mA
16mA

R2

+5 Vdc±5%
+12 Vdc ±5%
-12 Vdc±5%

100mVp·p
50mV p.p
50 mV p.p

64mA
25mA
7!1mA

Module

\\

\

I!

1\,

I

~\

:

" " "

Maximum total power consumption approximately 3 watts.
Typical total power consumption approximately 2 watts.

IIONAL TO NOl81i "ATK) ID81

, 1200 ..... BACK To.aACK,lCflAMBLER. NO EQUALIZI ..
2 :MIlD lIN, v 2IA OR., BACK TO BACK,ICRAMBLiR. NO IQUALIZIR

3 2400 BPS. II 280\. OR 8, 1Po11O HZ f'HAU JITTER, NO ICMMBUf!. NO lQUAlIZ'tI
4 :MOIl BPI. II ztA OR., 30 D t20 HZ PHASE JITTER, NO SCRAMBLER, NO eOUALIZER
I MOD PU, V,ZIA OR', 3001 UNCONDITIONI!D LINe, NO ICRAMa!.E .., EQUALIZER

DIGITAL INTERFACE
The R24 provides LS TIL or CMOS compatible logic levels that
are functionally equivalent to EIA RS232/449 and CCITI V.24.

~1."RaIo"_

Phase Error - Phase error can be measured by using the
modem's output signals PE, SYC, and A. With an external test
Circuit, a numerical value can be derived to indicate the quality
of received data. This numerical value can be directly correlated
to bit error rate performance, The required test circuit can be
implemented with discrete circuitry or in software within a
microcomputer.

Input
Logic

Allowed Input Voltage Laval.

Low
High

·12.0V to +0.8V Sonkong <10 jJ.A
+4.0V to +5.0V Sourcong < 10 pA

Digital inputs are directly CMOS compatible. Interfacing with
standard TIL or low-power Schottky TIL requires an external
pull-up resistor.
Output
Logic

Eye Pattern - By using the modems digital output signals
RCVDC, SYC, and A along with an added test circuit, the user
can generate an OSCilloscope quadrature eye pattern. This pattern
displays the received signal as a group of dots in the baseband
signal plane; hence, it is a graphic representation of modem
performance.

Low
High

Allowed Output Voltage Level.
O.OV to + 0.4V Sinking 0.36 mA
+ 4.0V to + 5.0V Sourcing 100 ~A

Digital outputs are directly CMOS or low-power Schottky TIL
compatible.

7-148

R24

2400 bps Integral Modem

TRANSMISSION LINE INTERFACE

~

The R24 provides an analog interface that must generally be
transformer coupled to ensure normal telephone line Isolation.
Through appropriate selection of transformers and other Interface circuitry, the R24 can be configured to operate on leased
or dial-up telephone lines, or on other special private networks.
For the dial-up interface, Rockwell offers an FCC registered
module that allows direct connection to this network. For the
leased line interface, only transformers with characteristics
similar to those utilized on the R24 modem evaluation board are
required for this connection.

.326
18.26 1

'12V (19)

COM 120)

(16) I

DAC OUT (22)
TFIL (23)

(13) CLAMP

(12) Tl11

(
(
(
(

L

X (24)

T2W/4W
T114
T103
T105

K (25)
Y (26)

TCDS (27)
Z (28)
800MS (29)
E (30)

7) T113
6) Tl06
6) TONA
4)TBC

TIN (31)
15dBm (32)
, 3dam (33)
1 'dBm (34)

( 3) CAUTO
I 2) T2
I 1) T1

-.

\

.100
12641
TYP,

The receiver and transmitter line interfaces are single-ended
(non-transformer coupled) signals with the following
characteristics:

18.281

'5V (21)

(14) NSYNC
(11)
(10)
I 9)
( 8)

-~
.326

·'2V (18)

(17) SaGR

(16) V26A

-9dem
·7dBm
5dBm
3dBm
-ldBm

(35)
(36)
(37)
(38)
(39)

\ .026 1.641 sa. P 1N
39 PLACES

Transmitter Module Package
Transmitter Output (Normal)

-L

~~----------,-----------~

Output Impedance: 600 ohms ± 2%
Maximum output level: :s0.0 dBm

I~~~~I

Transmitter Output (Alternate) Low Impedance:

R:~~!:~i ~ '1(8'26)

~

1
·12Vi13i '

(8)EQIN

m REC OUT
i~~ ~PS~UI~

Output Impedance: 0 ohms (op amp output)
Maximum output level :s + 6.0 dB

1.900
(48.26)

(4) n09

L_ !~l~t~~

RBCK
~- \i1I

Note: This output for transformer loss compensation.
Receiver Input:

.325

Input Impedance: 15.8K ohms ± 1%
Maximum Input Level: 0.0 dBm

. 12V n4)
COM (15)

\ 025 I 641 SQ. p, N
15 PLACES

Receiver - R1 Module Package

MECHANICAL SPECIFICATIONS

TI

.800
(20.32)

L_

I
I
leaksl!r -----------l!t- 1
300 MAX

2400'

~(j~

062

I
1-----

,

1

2 75 ± 03

344 ± .005

!if' I~~
I--r
-I

~~~

100

± .007

(LEAD PROTECTION)

(20) FSYC
(19) CP15
(18) TH09
(17) CP04
(16) PBS
(15) TC09
(14)S8GR
113) V26A
(12) I
(11) NSYNC
110) CLAMP
( 9) T111
( 8) R2W!4W
( 7) PE
( 6) T1 15
( 5) Tl04
( 410CP
( 3) A
( 2) RCVOS

AGC IN
T1 09
THRH
RLSD
RBCK
AGC OUT
IANALOG

.325
18.261

1]""::::
2500

L
.'\YC

5V
COM
·12V
·12v

.100
12541

TVP
\025 (.64) sa PIN
'31 PLACF.:S

Receiver -

(21)
(22)
(23)
(24)
(25,
(26)
(27)

(28)
(29)
(30)
(31)

~~

R2 Module Package

NOTES: 1) Dimensions in inches (millimeters),
2) Component side shown

NOTE: This cross-section is common to all modules.

7-149

R24

2400 bps Integral Modem
R24 MODEM EVALUATION BOARD

PRINTED CIRCUIT BOARD MOUNTING
OPTIONS FOR THE R24 MODULES

To facilitate evaluation and design-In of the R24 modem for new
and existing equipment designs, an R24. Modem Evaluation
Board (R24MEB) is available. The R24MEB can be easily combined with terminal systems for real-time performance
evaluation.

Three methods of mounting are commonly used. Each configuration has certain distinct advantages.
Mounting
Method

TVpe of Connection
or Connector Used

Basic
Advantage

Standard Flush
PCB Component
Mount

Wave Soldered Into Standard
PCB Eyelets

Lowest Height
Profile

Above Board
Low Profile
Sockat

Connectors (SAE Series
3000 or Methode Series 1000)
These Sockets are Wave
Soldered Into Standard
PCB Eyelets

Plug-in Capebilitv at Low
Cost

PCB Plug-in
Sockets (Bullets)

Connectors (AMP Miniature
Spring Sockets.)
Pin Sockets are Individually
Soldered Into PCB Eyelets

Lowest Profile for Plug-In
Capebllity

RECEIVER

ENVIRONMENTAL SPECIFICATIONS:
Operating temperature: O°C to 60°C
Storage temperature: -40°C to + eo°c
Relative humidity: to 95% (non-condensing)
Altitude: -200 to 10,000 feet (-6.1 meters to 3,049 meters)
Burn-In: 96 hours at 70°C

R24- Modem Evaluation Board (R24MEB)
The Modem Evaluation Board Is equipped with a standard 31
pin edge connector, control switches, output level jumper, and
Interface transformers. These features allow full control of the
interface Circuitry. In addition, this unit can be used directly in
a U.S. leased line configuration. The R24MEB is recommended
for all first-time users to assist in their evaluation. Complete
documentation Is supplied with each initial R24MEB.

Ordering Information
When ordering, specify products as follows:
R24 - Set of 3 modules (T, R1, R2)
R24MEB - Modem Evaluation Board

7-150

RDAA
Integral Modems

'1'

Rockwell

RDAA
ROCKWELL DATA ACCESS
ARRANGEMENT MODULE
PRELIMINARY

SECTION 1 -

INTRODUCTION

FEATURES

This document is an aide to customers installing, operating and
troubleshooting the Rockwell Data Access Arrangement (RDAA)
Module designed and manufactured by Rockwell International.

• Pre·registered (under FCC Rules, Part 68) for direct connec·
tion to dial telephone network
•
•
•
•
•
•
•
•
•

Integral Data Access Arrangement (DAA)
Automatic dialing-pulse or tone
Establishes data transmission path
Automatic answering function
Surge and hazardous voltage protection
Switch hook status indication
Ringing indication
Automatic line signal output limiting
Programmable or Permissive (strap selectable) connection
arrangements
• Small size (approximately 3.95" by 3.94") (100 mm. by
100 mm.)

THE RDAA MODULE
The RDAA Module enables the modem user to make direct con·
nections of their modems to the domestic switched telephone
network. The RDAA is completely registered with the Federal
Communications Commission under Rules Part 68. Therefore,
no user re·registration of OEM data communication equipment
is necessary when used with the RDAA. This means a definite
cost·savings for the OEM equipment designer.
In addition to establishing your desired data transmission path,
the RDAA also features an automatic answering function, line
surge and hazardous voltage protection, switch hook status
indication, ringing indication and automatic signal level control.
Automatic dialing can be performed by pulsing the OH relay or
by transmitting tone pairs.

RDAA Module
Document No. 29220N49

7·151

Product Description Order No. 649
August 1983

RDAA

Rockwell Data Access Arrangement Module
When the Permissive connection arrangement is employed, the
maximum signal output level across T and R is fixed at -9 dBm.
The Permissive jacks (RJ11 C) used for line connections are the
same jacks used for standard voiCe installations. Therefore, this
arrangement provides for greater mobility of user equipment.

The RDAA is easily incorporated into the users end product by
either using the provided mounting holes, and/or using the card·
guides without card·edge connector. The small size of the RDAA
makes it ideal for piggyback type mounting.
The Rockwell RDAA printed circuit board is 3.94 inches (100
mm.) in width and 3.94 inches (100 mm.) in depth.

RDAA DIMENSIONS
The dimensions for the RDAA Module are given in Figure 2.

SELECTABLE CONFIGURATIONS
As a prerequisite, telephone companies require that the signal
level received at their local central office not exceed -12 dBm.
Several different connection arrangements have been estab·
lished (as documented in the FCC Rules, Part 68) to meet this
requirement.

MATING CONNECTORS
The mating connectors of the RDAA are as follows:
1. Two row (14 pins) ribbon type connectors .1" spacing between
pins.

By jumper selection (Figure 1) the RDAA can be configured to
operate in either the Programmable (pG) or Permissive (PM)
connection arrangement. This is accomplished by placing the
jumper in either the W2 or W1 locations for the desired mode.
W1 jumper in, W2 jumper out for the permissive mode. W2
jumper in, W1 jumper out for the programmable mode.

I·~_:·::-~
-- I I

.,25-1 -

,------r+--------------------------~

3.94

1

- - e---------------

------------------1

3,275

I

3943275

1

°000000

e ____~·~O~o~o~o~o~o~o~__________~~~
Figure 1.

RDAA Module Jumper Selection Location
Figure 2.

When using the Programmable connection arrangement, the
maximum signal level allowed to be transmitted across T and
R is set by a resistor installed by the telephone company in their
wall jack (RJ45S or RJ41 S) at the customer location. The resistor
interacts with the RDAA through the leads PR and PC to pro·
gram the maximum output level in one dB steps between -12
dBm and 0 dBm. Selection of the resistor from thirteen possible
values is based on loop loss measurements performed by the
telephone jack installer. The Programmable arrangement pro·
vides for the transmission of the maximum allowable amount of
power. Therefore, this arrangement offers optimum perfor'
mance over long loops.

7·152

RDAA Module Dimensions

RDAA

Rockwell Data Access Arrangement Module

SECTION 2 -

INTERFACE DESCRIPTION

INTERFACE CIRCUIT DESCRIPTION
The following paragraphs describe in detail the RDAA interface
circuits shown in the block diagram (Figure 3) and the interface
circUits listing (Table 2-1).

PR)-----------~------------------------------------------__,

pc)----------------------------------------------------,
TXA

.. RXA

r-~--------------~

~------------------------~------4_------------~~OH

L-______________________

~--~--+_--------------~RDI

r:~~::~-----------------MI)---------~~_1;>----~--------------------------------------~

Figure 3_

SH

RDAA Functional Block Diagram

Table 2-1.

RDAA Interface Circuits

Signal Direction To:
Lead Designation

User

RDAA

Both

R, T
MI, MIC
PR, PC

+5V, +12V, -12V
SG
RDI
RCCT
OH
SH
CCT!
TXA
RXA

Function

X
X
X

Transmission leads for data signals.
Leads to telephone set switch hook
Leads to programming resistor.

X

Signal ground required.
Ringing slgm,1 present Indication.
To request data transmission path cut through.
To control Off-Hook relay
Status of telephone set swrtch hook.
Transmission path cut through indication.
Lead to modem output.
Lead to modem Input.

DC power required.

X
X
X
X
X
X
X
X

7-153

II

RDAA

Rockwell Data Access Arrangement Module

SG

NOTE
WARNING. If OH Is asserted to a logic high before the
incoming call ring signal is completed, the OH reed relay
switch contacts may suffer degradation.

The SG (Signal Ground) is the common reference for all modem
interface Signals.

RDI
ROt (Ring Detect) indicates to the user by an ON (Low) condition that a ringing signal is present. The ROt signal will not
respond to momentary bursts of ringing less than 125 ms in duration, or to less than 40V rms, 15 to 68 Hz appearing across Tip
and Ring with respect to ground. ROt is also used to disable
the transmission path. The electrical characteristics of the ROt
signal are shown in Table 2-2.

SH
An ON (High) signal on the SH lead indicates to the user that
the associated telephone (if used) is in the talk mode i.e., a contact closure exists between MI and MIC. The characteristics of
the SH signal are shown in Table 2-2.

CCTI

Table 2·2. Output Signals ROt
SH and CCTI Characteristics
Output
Logic State

CCTI is the Coupler Cut Through. An ON (Low) signal to the
CCTtlead indicates to the user that the data transmission path
through the RDAA is connected. The ON (Low) state does not
indicate the status of the telephone line or connection. The
characteristics of the CCTI signal are shown in Table 2-2.

Output Levels
0.0 to 0 4V while sinking < 1.6 ma
2.4 to 5.0V while sourcing < 40 I'-A

LOW
HIGH

TXA
TXA (Transmit Analog) is the lead from modem transmitter output. This lead should be tied to GND when the modem is in the
receive only mode.

RCCT
RCCT (Request Coupler Cut-Through) is used to request that
a data transmission path through the RDAA be connected to
the telephone line. When RCCT goes OFF (Low), the cut-through
buffers are disabled and CCT will go OFF (High) within 1 millisecond. RCCT must be OFF (Low) during dial pulsing but ON (High)
.for tone address signaling. The electrical characteristics of the
RCCT signal are shown in Table 2-3.

RXA
RXA (Receive Analog) is the lead to modem receiver input. This
lead may be left open when the modem is in the transmit-only
mode .

POWER REQUIREMENTS
The following power must be provided at the RDAA interface.

Table 2·3. Input Signals RCCT and OH Characteristics
Input
Logic Stste
OFF or I.!)W
ON or HIGH

A. + 12 VDC ± 5% @ 15 ma with a maximum ripple of 50 mv
peak-to-peak

Input Levels
0.0 to O.BV, load current .. 0.36 ma
RCCT
OH

= 2.0 to 5.0V, load current, .. 20 I'-a
= 2,OV, load current .. 100 I'-a

B. + 5 VDC ± 5% @ 20 ma with a maximum ripple of 100 mv
peak-to-peak

5,OV, load current .. 250 I'-a

C. -12 VDC ± 5% @ '15 ma with a maximum ripple of 50 mv
peak-to-peak.

OH

,"

P"

OH controls the OFF-HOOK relay, Applying an ON (High) signal
to OH closes the OH relay and establishes a DC path between
,T and R. Maximum delay between the ON signal to OH and the
close of the OH relay is 10 ms. When originating a call, an ON
(High) signal is used to request dial tone. After detecting dial
tone, OH can be pulsed to generate the dial pulses corresponding to the number of the called station (see Section 4.2).
On incoming calls, an ON (High) signal to the OH lead initiates
the answering sequence (see Section 4.1). The characteristics
of the OH signal is shown in Table 2-3.

HAZARDOUS VOLTAGE PROTECTION
Ughtning induced surge voltages and other hazardous voltages
are limited to 10.0 volts peak between the secondary leads of
the coupling transformer T1. The isolation between the relay
contacts and coils provides the protection of the telephone line
!rom hazardous voltages appearing on any control lead.

7-154

RDAA

Rockwell Data Access Arrangement Module

RING DETECTOR AND TIMER

The output control circuitry contains a variable gain buffer which
reduces the RDAA output to the maximum allowed level across
T and R. When the RDAA IS jumpered to operate in the Programmable mode, the resistor in the telephone company wall
jack sets the output level to one of thirteen possible values. If
the RDAA is jumpered to operate in the Permissive mode, then
an internal resistor will set the output to a fixed value. The relationship between the RDAA input amplitude (In dBm) across
TXA and GND and the nominal RDAA output level across T and
R is given below:

When the Ring Detector detects the presence of a ringing signal
ranging from 15.3 to 68 Hz with voltage levels of 40 to 150 VRMS
across Tip and Ring (T and R) leads, after a delay of 125 ms
to 500 ms, it will send an RD! (Ring Detect) signal to the user's
data terminal equipment (DTE). If the DTE is conditioned for
answering, the DTE will return an ON signal on OH and RCCT.
The OH signal closes the OH relay and starts a timer. The timer
is used to provide a quiet interval of more than two seconds
between the closing of OH relay and the connection of data
transmission path. This allows the telephone company to properly engage their billing equipment. After this delay the CCT!
interface lead goes ON (Low) and data transmission may begin.

A. For Programmable mode: output level across T and R
(input amplitude at TXA - 7 dB + (Programmed level set by
wall jack resistor).

RD! will go OFF (High) in less than 400 MSEC after the ringing
signal is stopped. The ring detector is disabled when OH is ON
(High) or SH is ON (High).

B. For Permissive mode: output level across T and R
amplitude at TXA) -16 dB.

SIGNAL LEVEL LIMITER AND GAIN
CONTROL CIRCUITRY

IMPEDANCE SPECIFICATIONS

= (input

On-Hook DC:

The DC resistance between T and R,
and between either T or R and signal
ground are greater than 10 megohms
for DC voltages up to 100 volts.

On-Hook AC:

The on-hook AC impedance
measured between T and R is less
than 40K ohms (15.3 Hz minimum).

NOTE

Off-Hook DC:

Less than 100 ohms.

The off-hook relay is not affected by the limiting function,
therefore, so triggering the limiting function need not result
in call termination.

Off-Hook AC:

600 ohms nominal when measured
between T and R.

TXA and GND:

2 megohms typical (operational
amplifier voltage follower input
impedance).

RXA and GND:

75 ohms typical (operational amplifier
voltage follower output impedance).

The limiter monitors the signal level applied to the RDAA input
lead TXA and is unaffected by the level of receive signal. When
the applied signal amplitude becomes greater than + 7 dBm for
a period of 1.3 to 3 seconds, the transmission path is disconnected via the transmit and receive buffers, and the output signal
CCT! will go OFF (High).

Reducing the input signal amplitude to less than + 7 dBm will
reset the limiter in less than 4 milliseconds, restore the data
transmission path, and cause the signal CCT to go ON (Low).
In order not to activate the limiter during normal operation, care
must be taken to ensure that the maximum signal amplitude into
the RDAA input TXA never exceeds +6 dBm. If the modem
output has a tolerance of ± 1 dB, then it is recommended to set
the modem output to +5 dBm (± 1 dB), so that the maximum
signal amplitude into TXA is 6 dBm.

INSERTION LOSS
There is no insertion loss for the RDAA. The RDAA contains a
receive buffer which compensates for transformer insertion loss.
For this reason, additional receive buffering is not necessary.

fI
7-155

RDAA

Rockwell Data Access Arrangement Module

SECTION 3 -

INSTALLATION/CHECKOUT
TELEPHONE SET AND JACK
ORDERING INFORMATION

RDAA CONNECTION TO TELEPHONE LINE
Connection of the telephone line interface pins of the RDAA to
the network shall be made via standard jacks and plugs as
shown in Figure 4. Cable color codes are also shown in Figure
4. A number of telephone line cord manufacturers produce the
standard plugs and cables (Meyer Wire Co., Hamden, CT; Virginia Plastics, Roanoke, VA, etc.)

If it is desirable to have manual call origination or alternate voice
capability, an exclusion key telephone set may be ordered from
a local telephone company. The telephone line may be transferred to the telephone set by lifting both the handset and the
exclusion key, if the telephone is configured as Data Set Controls Line. This operation is for manual origination or alternate
voice transfer (refer to paragraph 4.4 for manual origination procedure). A call may be terminated by replacing the handset in
its cradle and taking OH low if OH is not already low .

..-

~L'

.
4

r

RED

MI

FIGURE 3 2.

VELL.OW

1

BROWN

T

SILVER

'--'
STANDARD
CABLE

~:g:ITION

PC
RDAA PROGRAMMABLE
MODE

:t~i'~~ORNE

..BLACK

,

REO

4

GREEN

5

VELLOW

"

---

r l-

MINIATURE

PR

SrA-NOARD

2

R'
T1

MIC

PLUG

~

MIC

ADAA

GREEN

~

TO JACK
SUCH AS
{
RJ36X
SHOWN ON

R

0

0

USQe
RJ45S
JACK

MI

BLACK

1
I :A 2 , "L

5

4

r

-1--'
6

__ J

I JACK

RJ16X

---,

LT~T~T~T~T~TJ
MI

MI

R

T

MIC

'--v--'
TO RDAA

R
ADA'"

T

MIC

TO MINIATURE 6 POSITION JACK

~

~
123456

~

STANDARD
CABLE

STANDARD
PLUG

1'1

RDA" PERMISSive

MODE

I

,-

l'
I
I

ADAPTER

RJA2X

I

,

RJ41S IS A UNIVERSAL JACK WHICH

CAN BE UTILIZED WITH EITHER
THE PROGRAMMABLE MOOE OR
FIXED LOSS L.OOP

~FlL)

2

34

J~

MODE

r----:l

LTJ.:TJJ.::J

RJ41S
JACK

6 POSITION

MINIATURE PLUG

Figure 4.

Standard Jacks, Plugs and Cable Color Codes

7-156

I
I

I

,

2

."

,

I I
;.\ {~

1;- - - -1'--'
~ :JJ.1:1.:: J
6 POSITION
M1N1ATURE PLUG

RDAA

Rockwell Data Access Arrangement Module

The ringer of the telephone set may be disconnected by the
telephone company to prevent the bell from ringing.

When ordering this telephone, specify the USOC number RTC
and the following options:

The telephone company provides an exclusion key telephone
under the Universal Service Order Code (USOC) RTC. This telephone set has the following customer options:

A. A2 - Data set controls line
8. 83 - Aural monitoring not provided
or
84 - Aural monitoring provided

A. A1 - Telephone set controls line
C. 83 - Aural monitoring not provided

C. C5 - Touch tone dial telephone (503C)
or
C6 - Rotary dial telephone (2503C)

D. 84 - Aural monitoring provided (See Note 1)

D. 08 - Voice mode indication only

8. A2 - Data set controls line

E. C5 - Touch tone dial

Another telephone set provided by the telephone company is
the Model 502 with exclusion key. To order this telephone set.
specify the following:

F. C6 - Rotary dial

G. 07 - Switch hook indication
H. 08 - Voice mode indication only (See Note 2)

A. Modem 502 with exclusion key
8. Data set controls line

NOTES

A summary of the information for ordering telephone and jacks
is given in Table 3-1. Examples of typical installation are given
in Figure 3-2.

1. The aural monitoring feature allows the telephone
handset to be used for listening to line signals without
interfering with data transmission.
2. In thiS option the make contact of the exclusion key and
a make contact on the switchhook are connected in
series and to the mode indication leads MI and MIC of
the data jack. Therefore, the SH signal of the RDAA
goes ON only when the exclusion key is lifted.

Table 3-1.
Output
Configuration

Optional
Telephone Set

Programmable

With
Telephone Set
Without
Telephone Set

Permissive

With
Telephone Set
Without
Telephone Set

Telephones and Jacks Ordering Information
FCC
Reg. No.

Ringer
Equivalent

AM09S0
67943
DP-E
AM09S0
67943
DP-E
AM09S0
67943
DP-E
AM09S0
67943
DP-E

.8B

'RJ36X and
2.3RJ45S

.8B

2.3RJ45S

.8B

'RJ36X and RJ16X
or
4RJA2X and RJ11C
RJ11C

.8B

Telephone Jack
USOC No.

Telephone Set
USOC No.
RTC or 502
with exclusion key
N.A.

RTC or 502
with exclusion key
N.A.

Notes:
1. RJ36X is an 8 position miniature jack into which the telephone plugs. Rather than using an RJ36X jack, the telephone company may use a
connecting block to connect the telephone set and data jack to the telephone line.
2. RJ41S is a universal data jack. It may be used for either Programmable or Fixed·Loss Loop mode. The RJ45S jack is preferred. because it
costs less.
3. For mu~iple connections, the RJ45M jack should be ordered. The letter M indicates mu~iple single line jack for up to 8 lines. Specify the number
of lines required when ordering.
~. RJA2X is the adapter shown in Figure 3·1. The use of the RJ36X and RJ16X jacks is recommended.

7·157

II

RDAA

Rockwell Data Access Arrangement Module
TO OTE

OH RCCT RDI SH CCTI

TX
OUTPUT

R

R

T

T

TODTE

RDAA

MI

RXA

MIC

RX
INPUT

STANDARD
MINIATURE
PLUG

RJ36X 4
JACK

~RD
"

1
2

I

EX

3
4

I

5

J

--

6

7

8

""
:

}TO NETWOR K

,

SH

'kEX

1

NETWORK

~

)II~

EX

+

:],

/,\ BRIDGING
TRANSFORMER

RTC
OPTIONED FOR DATA SET
CONTROL OF THE LINE

NOTES:
1
2.
3.
4.

MI AND MIC ARE REQUIRED ONLY IF HANDSET IS USED.
PR AND PC ARE REQUIRED FOR PROGRAMMABLE MODE ONLY.
STANDARD TELEPHONE CO. PROVIDED JACK RJ16X, RJ45S OR RJ41S.
RJ36X OR CONNECTING BLOCK IS REQUIRED ONLY IF TELEPHONE HANDSET IS USED. WHEN THE RDAA
IS IN THE PERMISSIVE MODE, THE RJA2X ADAPTER AND RJ11C OF FIGURE 4 MAY BE USED WITH THE
ASSOCIATED TELEPHONE SET.

Figure 5. Transmit and Receive (Half Duplex) and (Full Duplex)

MODEM INTERFACE
There are 4 possible two-wire modes of operation configurations: receive-only, transmit-only, and receive and transmit (half
duplex) and full-duplex (using two different frequencies simultaneously) as described below:

C For the transmit-only configuration, the RDAA lead RXA is
leit open rather than connected to the modem receiver as
shown in Figure 5.

A. For the half-duplex and full-duplex configurations, the inter-

For a 4-wire full-duplex configuration, 2 RDAA modules and 2
telephone lines are required. The connection circuitry consists
of one 2-wire receive-only connection, and one 2-wire transmitonly connection.

face connection circuitry could be as shown in Figure 5.
B. For the receive-only configuration, the connection circuitry is
the same as that shown in Figure 5, except that the RDAA
input lead TXA is grounded rather than connected to the
modem transmitter output.

7-158

RDAA

Rockwell Data Access Arrangement Module

MODULE MOUNTING AND SECURING

Care must be taken in routing the telephone interface pins to
the telephone jack. The FCC (Rules, Part 68) requires that the
telephone interface leads shall be separated from the leads or
metallic paths connecting to power connections.

The RDAA may be physically incorporated into the OEM's end
product by using the four corner (0.156 inch diameter) mounting
holes and self-locking plastic standoffs, or by bolting the RDAA
module to a rigid structure. The RDAA module may also be
mounted using card guides without card edge connector.

NOTE
Power connections are those connections between commercial power and any transformer, power supply rectifier,
converter, or other circuitry associated with the RDAA.
The connection of the interface pins (including the ±12V
and +5V) shown in Figure 2 are not power connections.

A number of manufacturers such as Richlock Corporation, Chicago, IL., produce plastic standoffs (Part Number CBS-3N).

ELECTRICAL INTERFACE
Electrical connection to the RDAA module is made through
ribbon type connectors. The connector(s) interface pins (Figure
2) are contained on the component side of the board. There are
two test points brought out to the interface connector of the
board. Therefore care must be taken to prevent shorting test
points with any of the other interface signals.

The telephone interface leads shall not be routed in the same
cable (or use the same connector) as leads or metallic paths
connecting to commercial power.
FCC (Rules, Part 68) also requires that the telephone leads T
and R be separated from metallic paths to leads connecting to
non-registered equipment, when specification details provided
to FCC do not show that the interface voltages are less than
non-hazardous vo~age source lim~s in Part 68. T and R shall
not be routed in the same cable (or use adjacent pins on the
same connector) as metallic paths to leads which are not considered non-hazardOUS. All DTE interface connector Signals
shown in Table 3-2 have been established as non-hazardous.

The RDAA telephone line interface connector pins are physically
separated from the RDAA DTE interface connector pins, as
shown in Figure 2 and described in Table 3-2.

Therefore, in routing the telephone interface leads from the
RDAA P1 connector to the telephone jack, the following precautions must be strictly adhered to. The telephone jack interface routing path should be as direct as possible. Any cable
used in establishing this path should contain n6 signal leads
other than possibly the (prevIously established as non-hazardous) DTE interface signals shown in Table 3-2. Any connector used in establishing this path shou Id contain no
commercial power source signal leads, and adjacent pins to the
T and R (Tip and Ring) pins in any such connector should not
be utilized by any signals other than possibly those shown in
Table 3-2. Also the DTE interface routing path should be made
as short as possible.

Table 3-2. RDAA Telephone and
Modem Interface
Type
Interface
Circuit

DTE
Interface
Connections

RDAA
Connectors!
Pin No.
P2-1
P2-2
P2-3
P2-4
P2-5
P2-6
P2-7
P2-8
P2-9
P2-10
P2-11
P2-12
P2-13
P2-14

Telephone
Line
Interface
Connections

PI-4
PI-3
PH
PI-2
Pl-(5-8) & (11-12)
PI-9,10
PI-13,14

Interface
Circuit/Signal
CCTI
RXA
TXA
OH
RCCT
RDI
-12V
SH
GND
TP2 EXCESSIVE
POWER DETECT
+12V
+5V
N!U
TPI BILLING
DELAY TIME

INSTALLATION PROCEDURE
A. Check the telephone line interface cable(s) plug(s) and jack(s)
(Figure 4). If the USOC RJ41 S jack is used for the Programmable mode, ensure that the Jumper W2 IS installed and WI
jumper is removed for the programmable mode of operation.
B. Make sure the telephone company installer has measured
the loop loss correctly and has selected the proper programming resistor in the RJ45S or RJ41S jack.

PC
PR
MIC
MI
(Not Used)
R
T

NOTE
You have the right to know the method used by the
installer for measuring loop loss and selecting the programming resistor.

7-159

RDAA

Rockwell Data Access Arrangement Module

C. Check the power supplies to see if they meet the proper
'requirements specified in paragraph 2.2.

A. All direct connections to the telephone lines shall be made
through standard plugs and jacks as specified in Figure 4
and Table 3-1.

D. Insert the telephone cable plug into the jack, and make the
DTE interface connection. Then sWitch on the power supplit's.

B. It is prohibited to connect the RDAA to pay telephones or
party lines.

OPERATIONAL CHECKOUT PROCEDURE

C. You are required to notify the local telephone company of
the connection or disconnection of the RDAA, the make, the
modem number, the FCC registration number, the ringer
equivalence number (refer to Table 3-1) and the particular
line to which the connection is made. If the proper jacks are
not available, you must order·the type of jacks to be used
from the telephone company (Refer to Table 3-1 for the
proper jacks and telephones.)

The following procedures check out the RDAAin association
with a modem, a data terminal, a telephone set and an automatic dialer. The telephone set IS required only in the manual
origination mode (refer to paragraph 4.4) or if alternate voi':e
communication is desired. The automatic dialer is required Drily
in the automatic dial mode (refer to paragraph 4.3).

D. You should disconnect the RDAA from the telephone line if
it appears to be malfunctioning. If the RDAA needs repair,
return it to Rockwell International. This applies to equipment
both in and out of warranty. Do not attempt to repair the Unit
as this will violate the FCC rules.

AUTOMATIC ANSWER MODE
A. Set the modem transmitted output level to +5 dBm.
B. Call the local modem from a remote station.

C. Follow the instructions given in Figure 6.

E. The RDAA contains protective circuitry to prevent harmful
voltages being transmitted to the telephone network. If however, such harmful voltages do occur, then the telephone
company has the right to temporarily discontinue your service. In this case, the telephone company shall:

D. Transmit data from the local terminal to the remote terminal
and monitor the CCT/ signal, It should stay low.
E. Terminate the call sequence and verify the received data.

AUTOMATIC ORIGINATE MODE

1. Promptly notify you of the discontinuance.

A. Set the modem transmitted output level to +5 dBm.

2. Afford you the opportunity to correct the situation that
caused the discontinuance.

B. Follow the procedure of Figure 8 for touch tone origination
or Figure 7 for pulse dial origination.

3. Inform you of your right to bring a complaint to the FCC
concerning the discontinuance.

C. Transmit data from the local terminal and monitor the CCT/
signal. It should stay low.

F. The telephone company also has'the right to make changes
in their facilities and services which may affect the operation
of your equipment. However, you shall be given notice In
writing by the telephone company adequate to allow you to
maintain 'uninterrupted service.

D. Terminate the call sequence and verify the received data.

MANUAL OPERATION MODE
A. Set the modem transmitted output level to +5 dBm.

G. Labeling ReqUirements:

B. Follow the instructions given in paragraph 4.4.
C. Transmit data from the local terminal. CCT should stay low.

1. The FCC requires that the follOWing label be prominently
displayed on an outside surface of the OEM's end product.

D. Terminate the call sequence and verijy the received data.

Unit contains Registered Protective Circuitry
which complies with Part 68 FCC Rules

SPECIAL INSTRUCTIONS TO USER

'FCC Registration Number:

Your Rockwell Data Access Arrangement has been registered
with the Federal Communications CommiSSion (FCC). To comply
with the FCC regulations you are requested to observe the
following:

Ringer Equivalence: .8B
2. The size of the label should be such that all the requ'lred
information is legible without magnification.

7-160

RDAA

Rockwell Data Access Arrangement Module

SECTION 4

OPERATING INSTRUCTIONS
IDLE

AUTOMATIC ANSWER

t

r----

The connection of the data transmission path for automatic
answer is as described In paragraph 2.4. To disconnect the data
transmission path, just turn off OH and/or DA, as shown in
Figure 6.

I
CCT/· ON

I
I

DETECT DIAL TONE 1

IDLE

+

r----

RD/ON

-

RCCT·OFF2

I

I

CCT/· OFF3

'OH • RCCT • ON

I

2.§ECOND MINIMUM DELAY

I

R

I

D

I
RCCT· ON

T

I

E

I

E

DETECT ANSWER TONE 4

DATA TRANSMISSION

I

I

DATA TRANSMISSION

I

OH • RCCT • OFF

'OH & RCCT· OFF

I

CCT/· OFF

-

t

IDLE

D

CCT/.ON3

A

T

I

A

OH PULSES FOR NO.

D

ANSWER TONE
A

I

R

A

CCT/· ON

D

-

OH. RCCT· ON

I

-

CCT/· OFF

+

"---

"---

IDLE

-DA MAY BE ON PERMANENTLY FOR AUTOMATIC ANSWER.

Figure 6.

NOTES.
1. DIAL TONE DETECTION IS NOT PROVIDED WITHIN THE ROAA.
ALTERNATIVELY, DTE MAY START FROM..IDLE. TURN ON OH,
THEN TIME FOR 3 SECONDS TO ENSURE DIAL TONE PRESENT
AND PULSE OH FOR NUMBER.
2. DA MUST BE OFF DURING DIAL PULSING. DA MAY BE ON AT
ALL OTHER TIMES.
3. THE DA TO CCT RESPONSE TIME IS LESS THAN 1 MS.
4. ANSWER TONE DETECTION CIRCUITRY IS NOT PROVIDED
wrrHIN THE RDAA.

Automatic Answering Sequence

AUTOMATIC DIAL

Figure 7.

DIAL PULSE ORIGINATION
The DTE must provide the logic to turn ON the OH and DA
leads, detect dial tone (or time for 3 seconds to ensure dial tone
present), then turn OFF the DA lead and generate the dial
pulses corresponding to the called number (Figure 7). The
2-second delay period between OH and DA going ON and the
response of CCT going ON will not be invoked in the origination
mode. The DTE should monitor for call progress Indication (dial
tone, busy tone, answer tone, and call intercept).

Dial Pulse Origination Sequence

face with Voiceband Ancillary and Data Equipment"
(PUB 47001).
The following is an example for pulse dialing the digit #2 through
the OH lead.

Requirements for proper call establishment exist on the pulse
repetition rate (8 to 11 pulses per second), off duty cycle
(60 percent nominal), interdigital delay timing (600 ms to
2 seconds) and chatter and spurious makes and breaks. The
RDAA off-hook relay is a Reed relay designed to long life. Bell
System requirements for pulse and touch-tone dialing are
described in their Communications reference "Electrical
Characteristics of Bell System Network Facilities at the Inter-

+!iV/MAKE

OV!BREAK

7-161

ON HOOK

OFF HOOK

...
I~

100....

"'"

I
----t----

~
INTERDIGITAL

100ms

INTERVAL
BOOms TO 2 SEC

RDAA

Rockwell Data Access Arrangement Module
Bell System requirements exist on minimum and maximum tone
pair transmit power for proper call address signaling. When the
RDAA is in the programmable mode, the gain of the RDAA
transmit leg is set by a programming resistor in the telephone
jack (over thirteen possible values). This makes establishment
of the tone pair signal level to be input to the RDAA (at TXA)
which meets the Bell System requirements difficult. It is therefore necessary to operate the RDAA in the Permissive mode for
touch-tone origination. In this event the proper input power level
(per frequency pair) to the RDAA (at TXA) would be + 15 dBM
(nominal). This level is well above the RDAA automatic
limiter threshold. But the RDAA limiter activates (cuts off transmission path) only if threshold power level is continuously
exceeded for about one second minimum, ~nd quickly resets
itself if the power level drops below threshofd. If the tone pair
duration time is restricted to significantly under one second (the
minimum duration requirement is only 50 milliseconds) and the
minimum interdigital time requirement (45 milliseconds) is
observed, the limiter will not be activated. These requirements
are easily met if the tone pair generation is under logic control.
If the generation is controlled via keyboard input, the limiter will
be activated if a key is depressed and held for more than a
second, but will recover during the interval between key closures. However, the possibility exists that transients occurring
at limiter activation and resetting may endanger proper call
origination.

The OH lead can be pulsed directly via microprocessor port, or
a commercially available "binary to dial pulse" LSI device such
as the Rockwell CRC 8000, the General Instrument AY-5-9151
series, or the Motorola MC 14408. These devices can accept
4-bit binary digital inputs, buffer these digits, and output the OH
dial pulses upon command. Also available from numerous
semiconductor manufacturers (National, Mostek, General
Instrument, Motorola, etc.) are LSI devices capable of interfacing directly to a key board and producing suitable dial pulses.

TOUCH·TONE ORIGINATION
The user's terminal must provide the logic to turn ON the OH
and RCCT signals, detect the dial tone (or time for 3 seconds
to ensure dial tone present) and transmit the tone-address
signals via the TXA lead (Figure 8). The 2-second delay period
between OH and RCCT going ON and CCT! going ON is not
invoked in the origination mode. The DTE should monitor for
call progress indications (dial tone, busy tone, answer tone, and
call intercept).
It should be noted that tone address signaling method is significantly more complicated in terms of hardware requirements
than simple pulse dialing. The necessary tone pair generators
must be added by the user. A number of semiconductor manufacturers produce monolithic LSI tone generators (AMI, Mostek,
Motorola, National, General Instrument, Intersil, etc.). These
tone pair generators are designed to interface wrth keyboards
or digital ports and may require varying degrees of additional
low pass filtering to reduce harmonic distortion. Touch-tone
dialing is significantly faster than pulse dialing, but it may not be
available in some locations.

•

AUTOMATIC CALLING UNIT
Automatic dialing capability may also be added to a data transmission system simply by purchasing or leasing a separate box
termed an "Automatic Calling Unit" (ACU). Such units are available from a variety of manufacturers. ACU's are available utilizing pulse or tone dialing. Connections of ACU to the data
transmission system may be different for different ACUs. The
standard protocol involved in interfacing between the user's
data terminal equipment and an ACU is documented in CCITT
Recommendation V.25 and also in EIA Standard RS-366.
"Interface Between Data Terminal Equipment and Automatic
Calling Equipment for Data Communication." It should be reemphasized that a separate ACU is not necessarily required for
automatic dial capability. The RDAA and some external hardware and/or software (as previously described) can suffice.

IDLE

-

~

·OH &: OA -ON

I

CCT·DN

I

··OETECT DIAL TONE

I

TRANSMIT TONE
ADDRESS SIGNALS

R

D

• ... DETECT ANSWER TONE

D

T

DATA TRANSMISSION
A

E

I

A

MANUAL ORIGINATION

I

For manual origination a telephone set with an exclusion key
must be ordered from the local telephone company (refer to
Table 3-1). After lifting both the handset and the exclusion key,
a call may be originated or answered in the same manner as
normal telephone service. When the handset and the exclusion
key are lifted (MI is shorted to MIC), the signal SH is turned ON.
If the user's data terminal is ready, it may respond with OH and
RCCT. The RDAA will then turn ON the CCT! signal. When
answer tone is heard, the operator replaces the handset in its
cradle. the SH signal will go Low and the data transmission path
is connected. When data transmission is completed, the terminal
turns OFF the OH signal and returns to the idle state.

·OH & OA·QFF

I

CCT· OFF

+

'---

'---

IDLE

*OA MAY BE PERMANENTLY ON,
-*ALTERNATIVELY, USER MAY TIME FOR 3 SECONDS TO
ENSURE DIAL TONE PRESENT.
·-·ANSWER TONE DETECTION CIRCUITRY IS NOT PROVIDED
WITHIN THE RDAA

Figure 8.

Touch·Tone Origination Sequence

7-162

RDAA

Rockwell Data Access Arrangement Module

SECTION 5 -

FAULT ISOLATION

CUSTOMER REPAIR LIMITATIONS

FAULT ISOLATION

Under the FCC Rules, no customer is authorized to repair an
RDAA module. In the event of an RDAA malfunction, return the
faulty RDAA to Rockwell International. It is recommended that
the following fault isolation instructions provided in this section
be performed prior to returning a suspected RDAA module. A
periodic check of the DC power supplies is also recommended.

The fault isolation flow chart (Figure 9) has been prepared specifically as an aid to the user for locating possible network and/
or RDAA module malfunctions.

II
Figure 9.

RDAA Fault Isolation Flow Chart
7-163

SECTION 8
T-1 AND T-1/CEPT PULSE CODE
MODULATION PROTOCOL DEVICES
Page

Product Family Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8-2

R8040 Tri-Port Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8-3

R8050 T-1 Serial Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8-9

R8060 T-1 Serial Receiver .................................................. 8-17
R8070 T-1/CEPT Pulse Code Modulation Transceiver ............................ 8-23

8-1

T-1 AND T-1/CEPT PCM
(PULSE CODE MODULATION) PROTOCOL DEVICES
Meet AT&T and CCITT Standards
with signaling information outputted and the 24 or 32
channels uniquely identifiable.
Transmission in digital format instead of analog has
inherent ability to perfectly regenerate the signal even after
noise in the phone network. The TTL compatible devices
operate from a single 5V power supply.
For specialized memory for digital PBX and other
telecommunication applications, tri-port memory devices
are also available. These allow random read and sequential
read Simultaneously, and, allow addressing sequentially
or randomly. They support either time or space division
switching as well as elastic storage applications when
transmission and write speeds differ.

Rockwell International is the first company producing LSI
devices for supporting the commercial digital switched
network. The 24 or 32 digitized channels meet AT&T and
CCITT standards.
This means it is now possible to design T-1/CEPT
systems using LSI instead of discrete devices. This results
in a much lower parts count, lower power requirements,
smaller size and significant cost reductions. It also means
an increase in reliability.
Using our LSI devices, the 24 or 32 channels of 64K bps
information and signaling are multiplexed over a single pair
of wires. All data are transmitted serially, along with framing
bits, at 1.544 to 2.048M bps. At the receiving end frame,
superframe, and channel synchronization is accomplished,

Rockwell LSI Devices Provide• Parts Count Reduction
• Cabling Reduction
• Cost Reduction
• Increased Reliability
• Increased Performance

8-2

R8040
T-1 PCM Devices

'1'

Rockwell

R8040
T-1 TRI-PORT MEMORY

OVERVIEW

R04
R16
R32
WSEL
WE
RH
RG

VOO
N.C.*
SH
SG

GNO

FEATURES
•
•
•
•
•
•
•
•
•

R02
R01
RST
SCLK
N.C.

ROB

The Tri-Port Memory circuit is designed to function as an
assembly point and temporary storage area for 8-bit T-1 data.
It provides 64 8-bit locations of on-chip random access memory
which can be accessed via external addresses or internal
sequential addressing.

64 x 8 bit static memory
Single + 5V supply
Two totally independent read ports
Multiple Read access time < 430 ns (worst case)
Selectable random- or sequential-address Write operation
On-chip sequential address counter
Tri-state drivers, for chip-selectable bus operation
40-pin plastic dual in-line package
LSTTL Schottky-compatible (12KO pullup, to drive CMOS)

RF

SF

RE
RO
RC

SE
SO
SC
SB
SA
SRE
B

RB
RA
RRE

A

o

C
E

F
H

G

*NOTE: PIN 34 HAS AN OUTPUT SIGNAL APPLICABLE
ONLY TO ROCKWELL TESTING, MAKE NO CONNECTION
TO THIS PIN.

APPLICATIONS
Time-Division Multiplex (TOM) digitar switching data and control stores
• TDM sequential machines
• Elastic stores
• Hardware/Software control interfaces
• 110 Buffers

Pin Configuration
next positive transition on SCLK will clear it to binary 000000.
The Counter will also be cleared unconditionally if Reset signal
RST has been set to logic 0 when the positive transition of SCLK
occurs.

TRI-PORT MEMORY OPERATION

The Sequential Read Enable signal, SRE, enables sequentiallyaddressed read operations. If SRE is logic 0, the sequential
accessed data outputs (SA through SH) will become valid within
430 ns after the next positive transition on SCLK. If SRE is logic
1, and 350 ns have elapsed since the positive transition of SCLK,
the sequential accessed data outputs will become valid 80 ns
after the negative transition of SRE. The sequential read data
will cease to be valid 100 ns after the negative transition of SRE
or 20 ns after the next positive transition of SCLK, becoming
valid with the content of the next sequential location within
430 ns of that SCLK transition.

The Tri-Port Memory device accepts 8-bit parallel input data on
lines A through H. This data is stored in an internal memory location that is selected by either random address lines R01 through
R32 or by the device's Sequential Address Counter. Write Select
signal WSEL determines the source of the address; in the logic
ostate, WSEL selects the random address, in the logic 1 state,
WSEL selects the internal sequential address.
The state of Write Enable signal WE determines whether or not
the data on lines A through H will be written into memory. Data
will only be written into memory when WE goes low (to a logic
o state) and the address inputs have stabilized.

The Random Read Enable Signal, RRE, enables randomaccessed read operations. If RRE is logic 0, the random
accessed data outputs (RA through RH) will become valid within
380 ns after the random address lines have stabilized. If RRE
is logic 1, and 300 ns have elapsed since the random address
lines have stabilized, the random accessed data outputs will

The on-chip, six-bit Sequential Address Counter is a binary
counter that increments on each positive transition of Sequential Clock (SCLK). When the Counter attains binary 111111, the

Document No_ R8040D

Data Sheet Order No. 306
Rev. 4, June 1984
8-3

[I
I

R8040

T-1 Tri-Port Memory

become valid 80 ns after the negative transition of RRE. The
random accessed data outputs will cease to be valid 100 ns after
a positive transition of RRE or 20 ns after the random address
input lines change, becoming valid with the contents of the
newly-addressed location within 380 ns after the random address
Inputs have stabilized.

In the case of a same location read/write cycle, the .sequential
and/or random data outputs will cease to be valid after a negative
transition of WE, and will become valid with the newly-written
contents within 340 ns of that transition. Control of this parameter
minimizes external circuitry required for resolution of read-write
contention.

RECOMMENDED OPERATING CONDITIONS
Minimum Setup/Hold Time.
Hold

Setup
Signal

Measure to

ns

Measure to

ns

SCLK t
WSEL

WEI
WEI
WEI
WEt
SCLK I

300
280
250
150
180

WEt
WE t
WEt
WEt
SCLK t

0
0
0
100
0

R01-R32
A-H
RST

Minimum Pulse Widths

~~~T SEQUENTIAL
CLOCK
(SCLK)

-

Signal

Minimum Pulle Width

WE (=0)
SCLK

170 ns
220 ns

-

xxx----------

-XXX

f-

SETUP > 180 NS

--l

---j

f--

, , \ 1 ,I

HOLD > 0

~--------I

Sequential Counter Reset Setup and Hold Timing

NEW DATA -

NOTE: RANDOM WRITE AL.WAYS AFFECTS RANDOM READ OUTPUTS; SEQUENTIAL WRITE AL.WAYS AFFECTS SEQUENTIAL
READ OUTPUTS. EITHER WRITE WIL.L. AFFECT THE OPPOSITE READ OUTPUT, IF, AND ONLY IF, THE RANDOM
ADDRESS AND SEQUENTIAL ADDRESS ARE EQUAL.

Read Outputs at Same Location as Write (All Other Inputs Stable)

8-4

T-1 Trj-Port Memory

R8040

~~~SEL =

1)

m

~

WIDTH> 220 NS

~

..

WIDTH> 220 NS

-I

SETUP> 300 NS

--j

~!~~~r-m

I---

l--

HOLD> 0

'i\fV\l

WRITE

R01-R32
(IF WSEL

---XZZOZll///o
Wvs"---------n
--l f--

I
SETUP> 280 NS

--I

HOLD> 0

I'fV'v'

\NV

= O) _ _ _...J.NV'I\~.lC..!.1:I.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _"'iIAV\l\..¥-"'-'-~-_-_-_-_-_-_-_-_-_-_

--l f--

I-----I
- - - -- - - - - -- -----'fIX
SETUP> 250 NS

WRITE DATE
(A-H)

I SETUP ~
I-- > 150 NS
1

I

WE

-------------,~ WIDTH

HOLD> 0

xxx- ------

HOLD
> 100 NS

I

I--

_{'--------

I--- > 170 NS --I
Write Setup and Hold Timing

V
/i\

V

~~~
ADDRESS
fo..
(R01-R32) - - . . t + l l - - - - - - - - - - - - - - - - - - - - - - Z - O - N - S - - . . . . . L . + - ' RANDOM
OUTPUT DATA _ _
(RA-RH)

==
__ ~(:A~3~
'IJX

--'-...lL..~'-

:

::L:

:A:. _ _ _

~~~~~NTIAL

MIN. HOLD

~~~~~~T~~~A

-1

\\\-----

-\~\

20 NS
MIN. HOLD

\

READ ENABLE
(RRE OR SRE)
.. NS MAX.

...../1 l-.

--i

I

XX)(--

-

HI-Z

__

j

1

xxx- -------------"!XX

-

Sequential Read (SRE

DATA OUTPUT
(RA-RH OR SA-SH)

1 ·

= 0, WE = 1)

f-....- - - - - (TSA) 430 NS M A X . - j

(SA-SH)

~ ww.

~ _ _ _ _ _ _ _ _ _ _L..l/.:......¥....l...._
I\IV\
_ _ _ _ _ _ _ _ _...J.....iIl_ll...l_
Random Read (RRE

(SCLK)

Il-.----

= 0, WE = 1)

j

:1
"""_:
t--'"
Ef"TTT««'T"T""1-7~-------'-'»"""""""~»""""""~)'ftf-

--1 ~..,~

Read Port Enable/Disable (Address Stable, WE
8-5

= 1)

NS MAX

HI-Z

T-1 Trj-Port Memory

R8040
Propagation Delays
Parameter

Symbol

Min

Max

Unit

Random Read Access Time
Sequential Read Access Time
Read Port Disable (to HI-Z)
Read Port Enable
Same-Location Read After Write

tRA
tSA
tpD
tpE
tSL

0
0
0
0
0

380

ns
ns
ns
ns
ns

430
100
80
340

A -WRITE DATAB
C

o
F
G

R32 RANDOM ADDRESS INPUTS

R'.
ROB

1 OF 64
READ

R04

RANDOM

RO
RO'

DECODER

ADDRESS

RANDOM
READ PORT

WRITE
ADDRESS

WSEl
"0"" RANDOM

SELECTOR

SEQUENTIAL
ADDRESS COUNTER

=
ttr::=~~1~[2~~~~~~~~~~~~~~:-1
:~
~~g~~~

SCLK
)-'="----bClK

816

~~!;4

SEQUENTIAL

~+5

. ) GND
-

0

o!R(

Tri-Port Memory Block Diagram

8-6

SEQUENTIAL
READ PORT

R8040

T -1 Tri-Port Memory

MAXIMUM RATINGS*
Symbol

Value

Unit

Supply Voltage

Voo

+4.75 to +5.25

Operating Temperature

Top

o to + 70

V
DC

Storage Temperature

TSTG

-55 to +150

DC

Parameter

"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(Voo = +5V ±5%, Vss = OV TA = 25 D C)
Parameter

Symbol

Min

Max

Unit

Input Logic "1" Voltage

V'H

Input Logic "0" Voltage

V'l

Input Logic" 1" Voltage

VOL

Output Logic "0" Voltage

VOL

Output Source Current

IOH

-100

Output Sink Current

IOl

400

Input Capacitance

C,

5

pF

Output Capacitance

Co

25

pF

Power Dissipation (at 25 DC)

POSS

300

mW

2.0

V
0.8

2.4
0.4

8-7

V
V
V
p.A
p.A

R8040

T-1 Tri-Port Memory

PACKAGE DIMENSIONS

I

.550

T30

""""""'"T"TT'TTTTT'T"M'"TTT'T'T'T'"I"'T'T"MrTT"M'T'T'"I"'T'T"M..,.r~
1_

~
.065

"I

2.02 MAX
(51.3 MM)

.160

I-- ~ -I
IrI

"T4O
-1

.590 --""\

J~~~n~
~
:~~~
-l ~ ~ ~
~ jUIII~

I

~
.015

-

.045'

032 REF

.

UIJI
~
~U

I
I

I~

.020

f--

.125

r--

..J.!Q...
.090

NOTE: PIN NO.1 IS IN LOWER LEFT CORNER WHEN SYMBOLIZATION IS IN NORMAL ORIENTATION

8-8

R8050
T-1 PCM Devices

'1'

R8050
T-1 SERIAL TRANSMITTER

Rockwell
DESCRIPTION

The Rockwell T-1 Senal Transmitter formats data to be
sen ally transmitted according to T-1 02 or T-1 03 specifications, inserting framing and signalling bits along with 24
channels of 8-bIt channel data. The T-1 Senal Transmitter
also provides for alarm reporling via the Bit 2 inhibit method
or, with minimal external logic, via the multlframe alignment
signal (Fsl modificatIOn method.

B70PTN
TEST
FRSYNC
SBIT
CCIS
SSTB
UNPLRA
UNPLRB
GND
BINOUT
SYNOUT
LOOP
SYNCIN
BCH

Figure 1 IS a functional block diagram of the T-1 Senal Transmltter. The Mod 193 counter IS dnven by the clock at 1.544
MHz and IS either synchrOnized to the dnvlng system by Input
signal SYNCIN or provides synchronlzalion via output signal
SYNOUT. Input signal FRSYNC applies synchrOnization to
a Mod 12 counter, which Identifies the frame of the 12-frame
multlframe being processed.
The Input data register latches data dunng each bit penod,
when the 8th bit of a channel sample IS being transmitted.
The data selector outputs the proper sequence of bitS, as
controlled by a bit count and frame count.

1.
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

INH
BIT3
CHCLK
BIT4
BIT2
BITS
BIT1
BIT6
BIT7
VDD
CLOCK
ALARM
BIT8
ACH

Pin Configuration

The zero channel mOnitor function causes Bit 8 or Bit 7 to
be transmitted as a "one" if the channel data sample IS all
"zeros." Input INH provides a means to inhibit the zero
channel mOnitor function. Input B70PTN controls the particulars of the insertion method.

FEATURES
• Single 5V supply, low power Schottky TTL compatible.
• Accepts 8 bits of parallel data as input.
• Generates output as 193 bit serial data stream in T-1, 02, 03
or 04 Mode 3 data format.
• Provides a channel and frame timing Signal.
• Provides alternate control for alarm reporting and signalling.
• Provides automatic bit insertion for all-zero channel samples.

Two types of transmit formats are provided, a binary output
and a paired Unipolar output. The unipolar pair provides a
means to externally create a Single bipolar output with mlnImallogic.
FRS"""

.----~---t__-----~CHClKF
SVNCIN

>--11--~;;;-;:;:;;'

>--ji---;:=.:.::..J

CLOCK
5VOC>-+-

GNO}-+-

.--+-+-t-4--+t+t-----~SYNOUT
t-----~

SSTB

BIT 1
BIT 2
BIT 3

BIT 4
BlTO

BIT.

I

BlT7
BIT 8
ALARM

L .... BINOUT
UNPI..RA
UNPLRB

AC"
BCH

SBrr>CCIS>-====~

Figure 1. T-1 Serial Transmitter

Document No_ R80S0D

Data Sheet Order No. 307
Rev. 4, June 1984
8-9

T·1 Serial Transmitter

R8050
T·1 TRANSMITTER INPUTS

=

BCH: "8" CHANNEL HIGHWAY SIGNALLING

=

BCH allows the user to transmit one bit of signalling per channel
as Bit 8 of each channel data sample in Frame 12 only. BCH
is clocked into the input register by the falling edge of CHCLKF.
Refer to Table 1 and Figure 4.
.

Any input sO.8V
logic 0, low. Any input 2:2.0V
logic 1,
high. The transition from a low level to a high level is called a
rising edge, while the converse is defined as a falling edge.

FRSYNC: FRAME SYNCHRONIZATION

S·BIT: MUL TIFRAME SIGNALLING BIT

Frame sync allows external synchronization of the transmitter's
internal frame counter. When FRSYNC becomes high, the frame
counter is directly set to frame 1, the first of the twelve frames.
If FRYSYNC is held high and does not return to zero before a
rising edge of CLOCK, the subsequent states of BINOUT,
UNPLRA and UNPLRB are high, high and low, respectively,
regardless of the states of any other inputs. The latter
mechanism is useful for device and/or board testing only and
will cause bit errors and/or bipolar violations if used during field
operations. See Figures 6 and 7.

SBIT, in conjunction with CCIS, provides an alternate way to
control the multiframe signalling bit (Fs) transmission. The S-Bit
input is transmitted as the multiframe signalling bit (Fs) if CCIS
is held high. Refer to Table 2.

ALARM: LOCAL ALARM
Used for reporting alarm conditions. If the ALARM signal is high,
Bit 2 (the most-significant bit) of every channel data sample of
every frame is transmitting as a zero. This is commonly called
remote alarm signalling. ALARM is clocked into the input register
at the falling edge of CHCLKF. Refer to Table 1 and Figure 4.

SYNCIN: SYNCHRONIZATION INPUT

LOOP: LOOP STRAP

SYNCIN allows external synchronization of the internal Modulo
193 bit/channel counter. When SYNCIN becomes high, the
Modulo 193 counter is directly set to the state corresponding
to the output of the framing (FT or Fs) bit. The first bit of channel one will be output on BINOUT (and UNPLRA or UNPLRB)
as a result of the first rising edge of CLOCK following the return
of SYNCIN to logic O. See Figures 5 and 7.

Provided to aid testing of user applications. When enabled to
a high level, LOOP forces the unipolar outputs to transmit alternating ones and zeros, regardless of input conditions, while
BINOUT continues to provide normal data outputs. Refer to
Figure 3.

CCIS: COMMON CHANNEL INTEROFFICE
SIGNALLING STRAP

TEST: ROCKWELL DEVICE TEST INPUT

Provides optional control for replacing the automatic Fs pattern
with a 4-kilobit common channel signalling path. When CCIS
is high, the SBIT input replaces the Fs pattern and the insertion of ACH and BCH is suspended. The CCIS input may also
be used to provide the alternate method of alarm reporting. See
Figure 4.

Used only for Rockwell device testing. Keep this input
grounded.

CLOCK: T·1 CLOCK
Maximum frequency = 1.6 MHz
Minimum pulse width = 275 ns
The T-1 bit period is bounded by the rising edges of this input.

B70PTN: BIT 7 OPTION
Provides Bit 7 as an alternate bit position for "one" stuffing, as
programmed by the zero channel monitor function. Refer to
Table 1.

INH: INHIBIT ZERO CHANNEL MONITOR
If INH is high, the zero channel monitor function is disabled, and
Bits 7 and 8 are transmitted per corresponding inputs received.
See Table 1.

VSS, VDD: GROUND AND POWER
Voo = +5 ±0.25 Vdc
Vss = Ground, 0 Vdc

For channels in signalling frames (6 or 12) in which the first six
data bits and the signalling highway are all "zero," BIT 7 will
be forced to one if INH is low. For any frame except a signalling
frame Bit 8 or Bit 7 as selected by B70PTN will be transmitted
as a "one" if the channel input data is "zero" and INH is low.

Low power TTL Schottky compatible. "1" 2: 2.4 Vdc, "0" s
0.4 Vdc, CMOS - 12KO pullup to Voo required.

BITS 1-8: PARALLEL CHANNEL DATA INPUTS

SSTB: 4 kHz SIGNALLING CHANNEL STROBE

T-1 TRANSMITTER OUTPUTS

SSTB is the least-significant bit of the frame counter. Unless
it is directly set by FRSYNC, SSTB will go high as each framing
bit (FT) is serially transmitted, and will return low as each
multiframe alignment signal (Fs) is transmitted. Refer to
Figure 2.

Bit 1, the sign bit, will be serially transmitted first, followed by
Bits 2 through 8. The falling edge of CHCLKF indicates input
channel data has been clocked into the input register and always
occurs during the transmission of the final bit (Bit 8) of each channel data sample.

SYNOUT: CHANNEL SYNC OUTPUT

ACH: "A" CHANNEL HIGHWAY SIGNALLING

SYNOUT provides a means to synchronize to the internal bit
counter (Mod 193). SYNOUT is high for one bit time, beginning
just prior to the first data bit of a frame being serially transmitted.
Refer to Figure 7. SYNOUT is the only output determined by
the falling edge of CLOCK.

ACH allows the user to transmit one bit of signalling per channel as Bit 8 of each channel data sample in Frame 6 only. ACH
is clocked into the input register by the falling edge of CHCLKF.
Refer to Table 1 and Figure 4.

8-10

T·1 Serial Transmitter

R8050

UNPLRA, UNPLRB: T-1 SERIAL DATA UNIPOLAR
OUTPUTS

CHCLKF: CHANNEL CLOCK FALSE
The falling edge of CHCLKF, occurring as Bit 8 of any channel
is being serially transmitted, indicates input data has been
clocked into the input register. With the exception of an extra
bit period extending the low level duration at frame bit time,
CHCLKF is a divide-by-eight of CLOCK. Refer to Figure 2.

Two paired unipolar outputs are provided for the purpose of
creating a single serial data output transmission in bipolar format. The unipolar output register toggles for each "one" bit to
be serially transmitted. UNPLRA and UNPLRB are transmitted
as complements for "one" data bits and as low levels for "zero"
data bits. See Figure 3.

BINOUT: SERIAL DATA OUTPUT, BINARY
FORMATTED

The input signal LOOP, if high, forces the unipolar outputs to
toggle every bit time, regardless of input data.

BINOUT is the binary formatted serial conversion of the parallel
input data. The programmed format of BINOUT follows Tables 1
and 2.

FRSYNC perturbs the current bits being transmitted by UNPLRA
and UNPLRB. If FRSYNC remains high during the rising edge
of CLOCK, UNPLRA will be transmitted as a high level and
UNPLRB will be low. Refer to Figures 6 and 7.

BINOUT is synchronously transmitted as a high level if FRSYNC
remains high during the rising edge of CLOCK. Refer to
Figures 6 and 7.

Table 1. Serial Channel Sample Output Data Truth Table
Inputs X

0(

~

...
III

Iii '"

Z

::I!

ti:

a:

~

l:

0

l-

iii

M

I-

iii

= don't care

...
l-

iii

II>

co

I-

t::

iii

III

...

l-

iii

CD

l:

l:

iii

u
0(

u

I-

Binout
Serial Output

Current
Frame
Number

III

Notes

Channel
Bit Position
1

2

3

4

5

6

7

8

1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

X

X

X

X

X

X

X

X

X

X

0

X

X

X

X

X

X

X

X

X

X

0

X

X

X

X

X

X

1

0

X

X

P

Q

R

S

T

U

V

X

A

X

6

P

Q

R

S

T

U

V

A

2

0

X

X

P

Q

R

S

T

U

V

X

X

B

12

P

Q

R

S

T

U

V

B

2

0

X

X

P

Q

R

S

T

U

V

W

X

X

Y

P

Q

R

S

T

U

V

W

2,3

0

1

X

0

0

0

0

0

0

0

X

A

X

6

0

0

0

0

0

0

0

A

0

1

X

0

0

0

0

0

0

0

X

X

B

12

0

0

0

0

0

0

0

B

0

1

X

0

0

0

0

0

0

0

W

X

X

y

0

0

0

0

0

0

0

W

0

0

X

0

0

0

0

0

0

0

X

0

X

6

0

0

0

0

0

0

1

0

1

3

0

0

X

0

0

0

0

0

0

0

X

X

0

12

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

0

0

0

X

X

Y

0

0

0

0

0

0

1

0

3

0

0

0

0

0

0

0

0

0

0

0

X

X

Y

0

0

0

0

0

0

0

1

3

NOTES (1) ALARM = 1 has the same effect as BIT 2 = 0
(2) P, Q, R, S, T, U and V may not SImultaneously be zero, unles A, B or W IS 1
(3) Y IS any frame f 6 and f 12 WIth eels = 0, or all frames WIth eeiS = 1

i

~

I

8-11

i

R8050

T-1 Serial Transmitter
Table 2. Framing Bit (FT & Fs) Output Data
Frame
Number

Blnout

Processed
Bit

1

eels = 1

eels = 0

FT

1

1
S81T

2

Fs

0

3

FT

0

0

4

Fs

0

S81T

5

FT

1

1

6

Fs

1

S81T

7

FT

0

0

8

Fs

1

S81T

9

FT

1

1
S81T

10

Fs

1

11

FT

0

12

F.

o (NOTE 1)

0
S81T

Notes: (1) Alternate remote alarm reporting may be accomplished by holding S81T and eels both high just prior
to initiation of Frame 12.
(2) FT bit insertion 15 automatic and no optional control is provided.

CLOCK
(1.544 MHz)

I

B~~~6~ ~-8~X~F~~1~~2~~3~X~~~~~-"X~7~~8-"~-X~2~X~3~u-~X~5~~6~~~~8~X
CHCLKF

~SAMPLE CH. 1

-I

- - CH. 24

FT
OR

(n7~------,,\!:::SAMPLE CH. 2

f-ol>llt-----

_1>11

CHANNEL 1

/n7~------\'L"

--I

CHANNEL 2

,F_S~~~~
____- - - - - - - - - - I
1_
(horizontal scale change)
ACH Replaces BIT 8 in Frame No.6
BCH Replaces BIT 8 on Frame No. /
(

o
FRAME NUMBER
FT

=

1

1

0

/

1

~--~--+---~--4---~--~---L--~---L---+--~---+--~-~

1

SSTB
SYNOUT
FRSYNC'

~

________________________________________________________

SYNCIN"
'POSSIBLE POSITIONS TO RE-INFORCE INTERNAL SYNCHRONIZATION.

Figure 2. Transmitter Input-Output Signal Relationships
8-12

-+~

_________

R8050

T-1 Serial Transmitter

CLOCK

LOOP

BIN OUT

UNPLRA

UNPLRB

d

Figure 3. Transmitter Binary, Unipolar Outputs

CLOCK

~

1 '" 1 '"

\

I

CHCLKF

:~~~~I~:,
ALARM

~7~PTN

I\'--'-\\--'>-\-Lo\:>......J\'--'-\
r--

---------------------x~
I
I
X

~:~~~:
_

xt

X

6th

t3S

i

t,s

\,-----,r

.-L.-.t----.~ t'H

2)C- - - - - - - - -

x
x
~fX- t: _________________ _
X

7th

----l

F or 1st

8th

Figure 4 (a). Channel Input Timing

CLOCK

LOOP

xxx

xxx
Figure 4 (b). LOOP Input Timing

CLOCK

SSTB

SBIT

BINOUT

~

\

/

\~-\

-l \\\\\\\\

\

r

------------x:f '" r:'- ----------------X

CH 24, BIT 7

X

CH 24, BIT 8

J
I

CCIS

/

X

Fs

X

CH 1, BIT 1

X

I

,*:\SEE NOTE)

NOTE: CCIS WAVEFORM SHOWN FOR ALTERNATE ALARM REPORTING METHOD. eCls SHOULD BE
ACTIVE JUST PRIOR TO FRAME 12. UNDER THESE CONDITIONS, SBIT HIGH WOULD REPORT
THE REMOTE ALARM.

Figure 4 (e). Control Input Timing

8·13

•

I'

i'

R80S0

T-1 Serial Transmitter

\'--~/

":(~fl

CLOCK

SYNCIN

X

BINOUT

X

ANY BIT

CH 1, BIT 1

\'-----'/

x

CH 1, BIT 2

x

Figure 5. SYNCIN Timing Relationship

CLOCK

FRSYNC

07

SSTB

xxx

07

\\\
\\\

\\\

OZ

xxx

BINOUT

xxx

OJ

UNPLRA

XXX

UNPLRB

XXX

Figure 6. Non-return-to-zero FRSYNC Timing

CLOCK
FRSYNC
(Return to zero)
SYNCIN

(1 PULSE PER 2316 CLOCKS)

_____.un
~Hp~~N~!:T~

DATA
IN

..
BINOUT

SSTB

CHCLKF

SYNOUT

(1 PULSE PER 193 CLOCKS, MAX)

11111-1----_______________--'l.~
I

CH 23
FRAME 12

CHANNEL 1

may change

FRAME 1

78a8F818283848s86

/////
~\\\
~ffi~m'l ~~*~~

///II

______________

Figure 7. Transmitter External Synchronization (Return-to-zero FRSYNCj
8-14

~

R8050

T-1 Serial Transmitter
Table 3. Input Timing

Symbol

Parameter

Min

Max

Unit

- 0

t ,S

Buffered Data Setup Time

t'H
t2S

Buffered Data Hold Time

0

ns
ns

Control Input Setup Time

400

ns

t2H

Control Input Hold Time

20

ns

tas

Asynchronous Control Input Setup Time

350

ns

t3H

Asynchronous Control Input Hold Time

20

ns

t4S

SYNCIN Setup Time

200

ns

t4H

SYNCIN Hold Time

450

20

ns

SYNCIN Pulse Width

100

ns

tss

Frame Sync Setup Time (Return to Zero)

250

ns

tSH

Frame Sync Hold Time (Return to Zero)

20

ns

Frame Sync Pulse Width

200

ns

tss

Frame Sync Setup Time (Non·Return to Zero)

525

ns

tSH

Frame Sync Hold Time (Non-Return to Zero)

20

ns

Table 4. Output Propagation Delay, Worst Case
(Measured from Rising Edge of Clock Unless Stated Otherwise)
Output

Max Delay

Unit

SSTB
SYNOUT
Ref from Falling
Edge of Clock
CHCLKF
BINOUT
UNPLRA
UNPLRB

500
500

ns
ns

500

ns
ns
ns
ns

500
500
500

MAXIMUM RATINGS*
Parameter

Symbol

Value

Unit
Vdc

Supply Voltage

Voo

+4.75 to +5.25

Operating Temperature

Top

o to 70

°C

Storage Temperature

TSTG

-55 to +150

°C

-NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
= 5.0 ±5%)

(Vaa

Parameter

Symbol

Min

Max

Unit

Logical" 1" Input Voltage

VOH

20

Voo + 03

V

Logicical "0" Input Voltage

VIL

-03

0.8

V

Logicical "1" Output Voltage

VOH

24

-

V

LOgiC "0" Output Voltage

VOL

-

04

V

Output Source Current

10H

-100

-

/LA

Output Sink Current

10L

400

-

/LA

Capacitance Load (any output)

C

Input Capacitance (any Input)

CIN

-

Clock Frequency
Power Dissipation

Po

8-15

25

pF

5

pF

1.6

MHz

250

mW

R8050

T-1 Serial Transmitter

PACKAGE DIMENSIONS

I

(.650)
(.630)

~~~~~~~

"1
\1J~,
~

g::~~l -----1"1

J..!lli.

\"t- t~~~l -1

~

(.125)

8-16

(.060)
(.020)

R8060
T-1 PCM Devices

'1'

Rockwell

R8060
T-1 SERIAL RECEIVER

DESCRIPTION

TCLK
VOO (+5)
W1HBT
B2ALRM
TESTI
FRALRM
CHCLK
MAXCNT
CHSYNC
SYNCEN
MR
GNO
CALRM
SBALRM

The Rockwell T-l Receiver processes serial unipolar data of a
T-l ,02 or T-l ,03 line from which data and a 1.544 MHz clock
have been extracted.
Frame synchronization is accomplished by locating the frame
bit (FT) alternating every 386 bits. loss of frame sync IS indicated
if a frame bit error occurs within two to four F-Bit frames since
the previous frame bit error.
A loss of carner is indicated if 31 consecutive bit times yield
"zeros" ~t the input. Carrier loss is reset and frame sync search
begins when a "one" reappears at the TDATA input.

SIGFR
SBCLK
TOATA
COBS }
COB7
COB6
CHANNEL
COB5
OATA
COB4
BITS
COB3
COB2
COBl
COINH
SBIT
TESTO

Signaling bits, which occur 193 bit positions after a framing bit,
are monitored to detect signaling frames. The Signaling frame
output, SIGFR, identifies the present frame as a signaling frame,
and the S-Bit output at that time identifies which signaling frame
is being processed.

Pin Configuration

Remote alarm reporting is detected by mOnitoring the second
received bit of every channel sample of every frame. An alarm
is indicated if 255 consecutive Bit 2 zeros are received.
Channel data bits are output by an eight-bit parallel register. The
rising edge of the signal called channel clock (CHCll<) indicates
the extraction of new output channel data.

VD0>---C:> +5V
VSS

Several signals developed from a MOD 386 counter are provided
to aid in the external processing and storage of channel data.
Signals are provided to increment counters, synchronize
counters, strobe data into memories, etc.

>---<=>

P2

(GNDI P12

~p!:

~

: jeHANN"
~: ~~~A

64

±
CDINH

~P!!"_ _ _ _ _ _--f---L~~:pi.L...L-l

The Rockwell T-l Receiver chip operates on a single 5 volt supply
and directly interfaces to the low power TTL Schottky logic family.
The Receiver is packaged in a 28 pin dual In-line (DIP).
Timing relationships are given in figures 3 through 5.

TCLK

FEATURES
•

Synchronizes serial T-l ,02 or T-l ,03 sjgnals In less than 5 ms.

• Extracts 8-bit parallel channel data

MR
SYNCEN~~P1I:0
===Tff=~~~~~~~i....:.
11

•

Provides timing signals to capture and synchronize channel
and frame information

CHClK
WIHBT

CHsVNC

Monitors and detects
-

MAXCNT

Errors In signaling bit pattern
lOss of frame sync
lOSS of carrier
Remote alarm reporting

I

TESTl~

SBIT

Si'Gf'ii

(lEAVEOPENJ

SBALRM

B2ALRM

• Single 5V supply
• lSTTl Schottky compatible

Figure 1.

Document No. R8060D

R8060 Block Diagram

Data Sheet Order No. 308
Rev. 4, June 1984
8-17

•

T-1 Serial Receiver

R8060
T-1 RECEIVER INPUTS

COB (1-8): CHANNEL DATA BIT 1 THROUGH 8

Any input "0.8V = LOGIC 0, LOW, ZERO. Any input ;o:2.0V =
LOGIC 1, HIGH, ONE. A transition from a low level to a high
level is called a rising edge, while the converse is true for the
falling edge.

Bit 1 is the sign bit, Bit 2 is the most significant bit and Bit 8
is the least significant bit. If CDINH is low,new parallel channel
data becomes valid within 200 ns after the rising edge of CHCLK
and remains valid until the next rising edge of CHCLK. If CDINH
is high, channel data Bits 1 through 7 are forced to a high level.
Bit 8, the least significant bit, is not controlled by CDINH. Channel data Bits 1 through 7 are enabled or disabled within 300 ns
(R8060) or 150 ns (R8060A) by CDINH. Refer to Figures 3
through 5.

TDATA: UNIPOLAR T-1-D2, T-1-D3 SERIAL DATA INPUT
Unipolar T-1 Data is clocked in on the falling edge of TCLK.
Thereafter, TDATA is processed on the rising edge of TCLK.
TDATA must be stable 100 ns before and remain stable 100 ns
after the falling edge of TCLK.

CHCLK -

CHANNEL CLOCK

The rising edge of CHCLK indicates a change of parallel output
channel data. CHCLK is four TCLKS high then four TCLKS low
except for when an "F" or "S" bit is received. Then CHCLK
stretches to five TCLKS high and four TCLKS low. Refer to
Figures 3 and 4.

TCLK: T-1 CLOCK
Typical clock frequency is 1.544 MHz. Maximum clock frequency
is 1.85 MHz. The T-1 bit period is bounded by the rising edges
of TCLK. Input levels must be >2.4 volts for LOGIC 1 and
:5. 0.8 volts for LOGIC O.
SYNCEN: FRAME SYNCHRONIZATION ENABLE

CHSYNC:CHANNELSYNC

Provides a means to disable the automatic resync search initiated by a FRAME ALARM condition. If the SYNCEN signal is
low, with synchronization function is inhibited and remains inhibited until SYNCEN transitions high. SYNCEN must be stable
200 ns before the rising edge of FRALRM, In order to inhibit the
synchronization function.

Channel Sync occurs one time in a 24 channel period, making
it suitable for synchronizing external counters to the T-1 Frame
rate. CHSYNC goes low one TCLK period before the falling edge
of CHCLK at channel 24 date sample time. CHSYNC returns
high 1 TCLK period after the next rising edge of CHCLK. Refer
to Figures 3 through 5.

MR: MASTER RESET

TESTO: ROCKWELL DEVICE TEST OUTPUT

Master Reset, when low performs an initialization clear of the
T-1 Receiver; SBALRM and CALRM are reset to low levels while
FRALRM, CHCLK, WIHBT and CHSYNC are set to high levels.
Frame synchronization search begins on the rising edge of MR
provided that SYNCEN signal has been high for 200 ns.
Minimum pulse width is one T-1 clock penod.

Designed to aid in Rockwell device testing. No connection
required for normal operation.
WIHBT: WRITE INHIBIT
WIHBT covers the parallel channel data transition period. WIHBT
is suitable for clocking or strobing channel data into external
memories. WIHBT is high for two TCLK periods, beginning one
TCLK period before the rising edge of CHCLK. Refer to Figures
3 and 4.

CDINH: CHANNEL DATA INHIBIT
Provides a means to disable channel data bit outputs. When at
a high level, CDINH forces channel data Bits 1 through 7 high.
Bit 8, the least significant channel data bit, is not controlled by
CDINH.

MAXCNT: MAXIMUM COUNT OF 386 MODULUS

TESTI: ROCKWELL DEVICE TEST INPUT

MAXCNT is low for one TCLK period, marking the completion
of a two-frame period corresponding to the expected receipt of
an F-bit at the TDATA input. Refer to Figures 4 and 5.

Used only for Rockwell device testing, no connection to TESTI
is required for normal operation.

SBCLK: S-BIT CLOCK
SBCLK will be high during the S-Bit frame and low during the
F-bit frame. The transitions will occur within 300 ns after the rising edge of TCLK as channel 24 data is being transferred to the
parallel channel outputs. Refer to Figures 3 through 5.

VSS, VDD: GROUND AND POWER
VDD
VSS

= + 5.0 ± 0.25 VDC
= Ground, 0 VDC

S-BIT: SIGNALING BIT OUTPUT

T-1 RECEIVER OUTPUTS
The S-Bit output will have the same digital level as the previous
S-Bit received which occurred two frames before the receipt of
the current S-Bit. An S-Bit output transition occurs one TCLK
period after the rising edge of SBCLK.

Low Power TTL Schottky - compatible
"1" ;0: 2.4 Vdc; "0" " 0.4 Vdc
CMOS - 12 K n pullup to VDD required.
8-18

R8060

T-1 Serial Receiver

During a signaling frame (SIGFR is low), frame 6 or "A" highway
signaling is identified by S-Bit output being low. If S-Bit is high
during a signaling frame, frame 12 or "B" highway signaling
is identified. Refer to Figures 3 through 5.

FRALRM is set high and frame sync search begins when the
first TDATA high level is received.

SIGFR: SIGNALING FRAME

FRALRM detects an out-of-frame condition. FRALRM goes high
if:

FRALRM: FRAME ERROR ALARM

SIGFR identifies frame 6 or 12 when low. If the sequence of five
consecutive received S-Bits is either 0111 X or 1X001 (left to right,
as received), SIGFR shall go low after the rising edge, but at
least 375 ns before the falling edge of WIHBT corresponding
to channel 1 data sample time. SIGFR returns high one frame
later (193 bits). Refer to Figures 3 through 5.

A)
B)
C)

D)
SBALRM: S-BIT ALARM

The framing synchronization function is in progress.
Within 250 ns after the falling edge of MR.
An F-Bit is received which is not the inverse of the last
F-Blt and the same conditIOn also occurred two or three
or four F-Bit frames earlier.
Within 250 ns after the falling edge of CALRM, (CALRM
being reset by high level TDATA bit).

FRALRM goes low upon completion of the synchronization function or within 250 ns after the rising edge of CALRM. (Carrier
loss condition during frame synchronization function).

SBALRM goes high if the sequence of the five S-Bits received
contains four consecutive ones (01111), and remains high until
three consecutive "zero" bits are preceded and followed by a
"one" S-Bit (10001). The actual transition of SBALRM output
occurs after the rising edge, but at least 375 ns before the failing edge of WIHBT corresponding to channel 1 data sample
time.

OUTPUT CLOCK SIGNALS DURING FRAME
SYNCHRONIZATION FUNCTION
Following the Declaration of Frame Sync loss (FRALRM goes
high), output signals will continue normally for a two-frame period
with the exception of CHSYNC, which has the above mentioned
second frame sync pulse inhibited. Following the two-frame
period CHCLK, CHSYNC, and WIHBT are held high until frame
sync has been located, as indicated by the falling edge of
FRALRM. With typical data patterns, frame synchronization
takes less than five milliseconds. See Figure 2.

B2ALRM: BIT 2 ALARM
B2ALRM goes high, detecting a remote alarm condition, if 255
consecutive channel data samples are received with Bit 2 low.
B2ALRM returns low upon the receipt of any channel sample
with Bit 2 high.
CALRM: CARRIER LOSS ALARM
A carrier loss is detected and CALRM is set high if 31 consecutive low level TDATA bits are received. CALRM is reset low,

/FRAMESYNC
_________________

FRALRM-----.Jr--------------------------------------------yl~

-----2 FRAME

1-1
......

PERIOD------.l_~1

WIHBT

Figure 2.

Signal Relationship During Frame Alarm and Search for Resynchronization

8-19

R8060

T -1 Serial Receiver
.

_ F BIT FRAME

CH24
, - -_ _
A.A_ _....

I

S BIT FRAME_
CH1
A'-_ _.....

~~~~~ATA l' f± 1.. 1 H · 14121 : IB~Tf ± 1"1 32 H .1_1 21' I H 32
CLOCKED DATA l' I 1.. 1 1.1 ·1·_ 12 l' IB~TI H 32 H • I_ 12 l' I 1.. 1
32

±

±

32

1

±

±

TCLK (1.54 MHZ)
CHCLK

~

WIHBT

'--__---'I
SBCLK
SBIT

_______

~x~

X

CHANNEL DATA~ CH23 OUTPUT DATA
PARALLEL
--"
..

Figure 3.

______________

CH24 OUTPUT DATA

v--cti1"
~

Signal Relationships at Beginning of FS Frame (S-BIT)

I

- - S BIT FRAME F BIT FRAME-CH1
A

CH24
r -_ _ _
AA_ _

:~~~~~ATA l' f

±

CLOCKED DATA

~

IB~Tr I.. 132 H .1 I 2I ,'1 ± H
121 IB~TI lui 32 H .1_1 1' I H

1.. 132 H · 14 I 2I:

1'1 ± 1.. 132 \>01 .1 4

4

±

1

±

32

2

±

TCLK (1.544 MHZ)
CHCLK

'--__r--

~

WIHBT

'---__---'I
SBCLK
SBIT

NO CHANGE

u
CHANNEL DATA ~ CH23 OUTPUT DATA
PARALLEL
--"

Figure 4.

X

CH24 OUTPUT DATA

v--cti1

I'L.!::!!!...

Signal Relationship at Beginning of FT Frame (F-BIT)
8-20

R8060

T·1 Serial Receiver
FRAME SYNCHRONIZATION
BIT (F BIT) PATTERN

SBCLK

SBIT ~\.._ _ _ _ _ _ _ _ _ _ _~
(OUTPUT)
SIGFR

u

u

u

=

u
=

u

=

FRAME
24 TIME SLOTS
193 BITS
1251'S
TIME SLOT = 5.181'S ONE BIT = 648 NS
MULTIFRAME = 12 FRAMES
1.5 MS.

=

F BIT (FT) ALIGNMENT SIGNAL
(ODD-NUMBERED FRAMES)

S BIT (Fs) MUL TIFRAME ALIGNMENT SIGNAL
(EVEN-NUMBERED FRAMES)

FIRST BIT

FRAME

FIRST BIT

1

1

3
5
7

0

2
4

0
0

1

6

0

9
11

1

8
10
12

FRAME

0

Figure 5.

1
1

0

Multiframe Signal Relationships

Table 1. Output Propagation Delay
Worst Case. From Rising Edge of TCLK
OUTPUT

MAX DELAY (NS)

CHCLK
CHSYNC
WIHBT

300
300
300

~vjAXCNT

300

SBCLK
SBIT
SIGFR
SBALRM
B2ALRM
CALRM
FRALRM
COB (1-8)

400
400
475
475
450
300
900
400

:Lit-

I

( 5501
( 5301

Lirn-T1"'1'"T'TTTnTT'!"'!Tn'T'n~~
:~~~:-i-'jl-f~nl

(0651

( 160i

Lf
itf

~

j~~ j~~"t-~_ :::H ,~,
(0151

------

(0901

(1251 i020l

Packaging Diagram
8-21

II

R8060

T-1 Serial Receiver

MAXIMUM RATINGS*
Parameter
Supply Voltage

Symbol

Value

Unit

Voo

+ 4.75 to + 5.25

V

Operating Temperature Range

Top

Storage Temperature Range

TSTG

o to +70
-55 to + 150

·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

°C
°C

ELECTRICAL CHARACTERISTICS
= +5V ±5%, TA = 25°C)

(Voo

Parameter

Symbol

Min

Input Logic "1" Voltage

VIH

2.0

Input Logic "0" Voltage

Vil

-0.3

Output Logic "1" Voltage

VOH

Output Logic "0" Voltage

Val

Output Source Current

IOH

-100
400

Output Sink Current

IOl

Clock Frequency

TClK

Max

Unit

VDD + 0.3

V

0.8

V

2.4

V
0.4

V

p.A
~A

1.85

MHz

Input Capacitance

CI

5

pF

Output Capacitance

Co

25

pF

Power Dissipation

PDSS

550

mW

8-22

R8070
T-l PCM Devices

'1'

R8070
T -1/CEPT PCM TRANSCEIVER

Rockwell
INTRODUCTION

FEATURES

The R8070 is a monolithic silicon gate CMOS device designed
to implement PCM transmitter and receiver functions applied
in primary-rate digital carrier systems worldwide. Both the
transmitter and receiver contain appropriate circuitry for synchronization, channel monitoring and signalling extraction.

• Autonomous Transmit and Receive Sections in a single chip
• Low Power CMOS 100mw (Operating)
• 5 Volts Single Supply Voltage
• 64-pin QUIP
• Meets CCITI G.732, G 733, and applicable sections of G.703
Specifications and AT&T Advisories

The R8070 supports CCITI recommendations G 732, G.733 and
applicable sections of G.703, as well as Bell System technical
advisories on clear channel capability and extended framing
format. This device provides the interfaces between the multiplexed digital signals of the subscriber loop and the PCM highway in a digital telephone switching system. The device operates
from a single power supply of 5 volts and a sampling clock of
1.544 to 2.048 MHz, depending on the mode of operation.

• Operates with EXTENDED FRAMING, CLEAR CHANNEL,
and/or CEPT formats
• Supports MultiplexlDemultiplex T-1 C, Mode 1 (Synchronous)
Operations
• Uses a clock of 1.544 (T-l), 1.576 (1/2 T-1C) or
2.048 (CEPT) MHz, depending on operatIOn mode
• Selectable Serial or Parallel Digital Data Interface

Packaged in a 64-pin QUIP (quad in-line package), the R8070
requires less real-estate and provides flexibility in system integration and manufacturing. Specific support of both types of operation modes (parallel/serial) allows the application of the R8070
in virtually every type of voice/data system using either T-l, T-1 C,
or CEPT specification.

PSll---!~I~-::...--

TFSVNC - - TMSVNC------IA--IB - - - - - - 10 - - -

TVEL------TCLK - - TMAX------Ml--M2-----M3- - M4-----TIOLE - - TLOOP--- - - TNEG - - TPOS-----TNRZ--OJ - - - - - OH--OE - - - - - PS09- - PS010-----PSOll- - PS012 - - - - - PS013 - - -

L___ _ _ _ _
I

• Reframe Time 10 ms (Mode Dependent)
• TIL/CMOS Compatible Inputs and Outputs

~

~~

3

62

4

61

5
6

60
59

7

58

8

57

9

56

10
11

55

54

12
13

53
52

14
15
16

51
50
49

17
18
19

48
47
46

20
21

45
44

22
23
24

43
42

25

41
40

26

39

27

38

O_D_-_-_~- _~_~

oc - - - - -

---=-~~---PSI3

PSI4
------PSI5
---PSI6
- - - - - - PSI7
- - - PSIS
------IC
- - - RCLK
------RPOS
---RNEG
------RIOLE
- - -RMW
-----RVEL
- - -RSER
- - - - - PSOl
- - - PS02
-----PS03
- --PS04
- - - - - - PS05
---PS06
- - - - - PS07
- - -PSOS
-----RSRCH
- - - RMRST
- - - - - PUP
- - -RREO
- - -

~_~_~-_._-_-_-_-_O_G_-_-

30

35

_
OB--·
31
34
R_V_L_L_-___--_. L3_2________________
_______________33...J
PIS - __
- -__
- - -

- -

- -

-

-

---OA
-

-

OF

_- __
-RSVNC
-Vss

R8070 Pin Configuration

Data Sheet Order No. 314
October 1984

Document No. 29300N14
8-23

T·1/CEPT PCM Transceiver

R8070
FUNCTIONAL CHARACTERISTICS

receiving terminal, this signal is referred to as digital milliwatt.
A multiplexed framing pattern generator signal, which is the
result of the composite of an externally supplied S BIT and an
internally generated data link CRC check bit, is provided at
TFGEN. TI1S, TN1S, and TX1S are provisions for inputs that
are dedicated for use in the 256 modes and are typically applied
in handshaking applications between the transmit and receive
terminals. Many other signals are used on different assignments,
depending on the selected operating mode, and are described
in detail in this document. These input and output signals are
used to provide the hooks and handles that are associated with
each mode.

TRANSMIT SECTION
The transmit section of the R8070 (refer to the R8070 Functional
Block Diagram) formats data to be serially transmitted according to CCITT G.732, G.733, applicable sections of G.703, and
Bell technical advisories on clear channel capability and extended
framing format. The 8-bit PCM data is clocked out by the transmit
clock, which can vary between 1.544 and 2.049 MHz, depending on the selected mode of operation. Input signals TSSYNC
and TMSYNC provide external synchronization to the R8070
frame counters.

RECEIVE SECTION

Depending on the mode of operation when a yellow alarm is
received, the R8070 is capable of sending idle messages in all
message channels by activating the TIDLE input. A TLOOP is
provided to aid testing user's applications by connecting internally TNEG and TPOS to RNEG and RPOS. Yellow alarm
signalling to remote equipment is conveyed by stuffing or
manipulating the appropriate bits in the various data channels,
depending on the mode of operation.

In the receive section (refer to R8070 Functional Block Diagram),
the received unipolar data is processed serially by the rising edge
of RCLK at a rate of 1.544 to 2.048 MHz, depending on the mode
of operation (Bell or CCITT). Synchronization is accomplished
by locating the Ft bit (framing bit) through a five-stage process,
thus eliminating erroneous bit candidates that could cause false
synchronization. In the 193N and S modes, synchronization is
achieved in less than 5ms, while in the other modes, it is
achieved in less than 10ms.

Transmit output signals (i.e., TCHCLK, TCHSYNC and TMAX)
are provided as a means to synchronize external equipment to
the internal bit counters. Two types of data output formats are
provided by virtue of pins TNRZ, TPOS and TNEG. TPOS and
TNEG can be configured with minimal external circuitry to create
a bipolar output. When configured in a parallel mode, the
transmit channel data bits T1-T8 are sampled by the rising
edges of TCLK. When used in a serial transmit mode, input
control signal TSA allows advancement by one bit time of the
transitions on TSQ and TSIGSQ. TSIGMD identifies the input
source for transmit signalling information. Transmit output
signals, designated by TSQ1 through TSQ5, are provided and
can be used in decoding schemes to address indiVidual channel cards residing in channel banks, according to D1 D or D2
sequential code format.

Output signals such as RSYNC, RSRCH, RRED, and RMAX are
dependent on the synchronizer receive master state and may
be used for status reporting or external processing of the
received data. Remote alarm monitoring (yellow alarm) is
reported by RYEL in a format appropriate to the transmission
mode.
Similar to the transmitter, a provision that allows insertion of idle
channel data in the received bit stream is invoked by activating
the RIDLE input. RMW Input is provided for trunk alignment,
causing a 1 kHz milliwatt generator to be substituted for all
received message channels.

Various mode dependent signals are used to provide control and
signalling to the transmitted data stream. Transmit link input
signal, TLlNK, is used to input link information at various bit
rates, depending on the mode of operation. Provision for insertion of error patterns in the F position is made possible through
input TFSIG. In the 193E and S modes, robbed bit signalling
information is provided and controlled through inputs TA(C) and
TB(D). In the 256S mode, the serial bit stream containing the
transmit signalling information is provided at TABCD and sampled at an 8 kHz rate. Repetitive transmission of a certain code
sequence in a given channel on TNRZ or TPOS and TNEG provides a 0 dBm 1 KHz signal. When decoded in a properly aligned

Receive output signals (I.e., RCHSYNC, RCHCLK, and
RWIHBT) are provided for synchronization of external counters
to the PCM frame rate and strobing the received data into
external memory if necessary. Additional output signals are
provided to indicate the status of the received data, the type of
alarm received and a bipolar violation indication when it is
manifested In the data pattern. Serial mode receive outputs (i.e.,
RSQ1-RSQ5) are used in a decoding scheme to select channel units residing in channel banks. Receive framing mode
dependent signals OA through OJ are used for monitoring of
signalling Information, error reporting, synchronization reporting
and many useful alarm reporting signals.

8-24

T-1/CEPT PCM Transceiver

R8070

PIS MODE
SELECT
FR AME MODE
SE LECT

•
•
•
•

DISPATCHING
CIRCUIT

SIGNALLING
IDLE CODE
ALARM
BIT CONTROL
GENERATOR

L-.

TRANSMIT
COUNTER
LOGIC

TIMING
SELECT

~

TIMING
TRANSMIT
OUTPUTS

TRANSMIT CLOCK

t
PARALLE L
INPUT
DATA

~

8-BIT
LATCH

I
I

~~~T~A~~T ..!.N~~ __

~

~

OUTPUT
REGISTER

SINGLE AND

PAIRED UNIPOLAR
~ OUTPUTS

I
I
I

_ _ _ _ _ --.JI

CHANNEL
TRANSLATOR
Transmit Section

H--.

SEQUENCE CODE

I
I

r-------- -------------------~
I RCV CLOCK

I
RECE IVEDl
DATA

t

~~

RECEIVED
DATA
INPUT
REGISTER

RIDLE

SIP
CONVERTER

RMW
• MIF SYNC
• SIGNALLING
• DATA LINK
• ALARM
EXTRACTION
CIRCUIT

.-

--.
~

FRAME FORMAT
MODE SELECT

RECEIVED
PARALLEL
DATA

RECEIVE
SERIAL DATA

~

PIS MODE SELECT

f-----

RECEIVE
COUNTER
CONTROL
LOGIC

t
~~~.~~~~

RECEIVE
DISPATCHING
CIRCUITRY
Receive Section

RECEIVER
STATUS
SIGNALS

SYNCHRONIZER
~ SYNC STATUS
LOGIC

.
010/02
CHANNEL
TRANSLATOR

EXTERNAL
SYNC SIGNALS

f---- SEQUENCE
CODE
FRAMING MODE
OUTPUT SIGNALS

~-----------------------R8070 Functional Block Diagram

8-25

[I

I

R8070

T·1/CEPT PCM Transceiver

OPERATIONAL MODES

PARALLEL/SERIAL MODE-DEPENDENT OUTPUTS

The R8070 is configurable in a parallel or serial operation. The
R8070 is mode selectable. By strapping input lines M1-M4,
eleven data formats are provided to meet the user's
requirements.

Parallel Mode-Dependent Outputs
Pin

PSOI
PS02
PS03
PS04
PSOS
PS06
PS07
PS08
PS09
PS010
PSOll
PS012
PS013

The PIS (ParalieI/Serial) mode straps are as follows:
1. Parallel PIS = 1
2. Serial PIS = 0
The permissible modes that may be selected are illustrated.

r --

r
I

M2

I

,=

,

1

I

L

,...
I

I

M2 ,= 0
I
L

= 1-

Ml

- - -, r- - - - Ml

=0 -

- --,

197N
Transp

193N
B8ZS

193N
B7

2S6N
HDB3

DEVICE
TEST A

193E
B8ZS

193E
B7

DEVICE
TEST D

DEVICE
TEST B

193F
B8ZS

DEVICE
TEST C

DEVICE
TEST E

1975
Transp

1935
B8ZS

1935
B7

2S6S
HDB3

M3

=

L.. ___

0

M3 = 1 ___

J

M4

=

0

M4

I
=
I

I
I

I

M4 = 0

M3 = 0

PARALLEL/SERIAL MODE-DEPENDENT INPUTS
Parallel Mode-Dependent Inputs
PSII
PSI2
PSI3
PSI4
PSIS
PSI6
PSI7
PSI8

Tl
T2
T3
T4
TS
T6
T7
T8

Name

PSII
PSI2
PSI3
PSI4
PSI5
PSI6
PSI7
PSI8

TSER
TSIGMD
TABCD
TSA
RSHIFT
D1D
D2
RSR

Transmit Channel Clock
Transmit Channel Sync
Receive Channel Clock
Receive Channel Sync
Receive Write Inhibit

Pin

Name

PSOI
PS02
PS03
PS04
PSOS
PS06
PS07
RS08
PS09
PS010
PSOll
PS012
PS013

RSOI
RS02
RS03
RS04
RSOS
TSIGSO/TNSYNC'
RSIGSO/RIBITS'
R8/RABCD
TSOI
TS02
TS03
TS04
TS05

Description

Receive Sequence Code Bits I-S

Transmit Sequence Code Bits I-S

Notes

Description

Transmit Channel
Data Bits 1-8

Serial Mode-Dependent Inputs
Pin

Receive Channel Data Bits 1-8

Serial Mode-Dependent Outputs

1

INTERFACE CRITERIA

Name

Description

I
I

Mode Selection

Pin

Name

Rl
R2
R3
R4
RS
R6
R7
R8
TCHCLK
TCHSYNC
RCHCLK
RCHSYNC
RWIHBT

Description

Transmit Serial Input
Transmit Signalling Mode
Transmit Signalling Input
Transmit Sequence Advance
Receive Shift
Dl D Sequence
D2 Sequence
Receiver Sequence Retard

8-26

• Mode ~ Transmit Signalling Square Wave
193 or Receive Signalling Square Wave
197
Receive Channel Data Bit 8

(PS06)
(PS07)
(PS08)

• Mode ~ TN SYNC Transmit National Sync
2S6
RIBITS
Receive International
RABCD
Receive Signalling

(PS06)
(PS08)
(PS08)

R8070

T-1/CEPT PCM Transceiver

INPUT/OUTPUT SIGNAL CHARACTERISTICS
R8070 Input/Output Signal Characteristics
Mnemonic

Definition

Function

SERIAL MODE COMMON INPUTS:
DID, D2

Code Select Modes

These signals, Dl D and D2, permit the generation of transmit and receive serial codes,
according to CCITI or the Dl D and D2 channel assignment format:
DID = 0,
DlO = 1,
DlO = 0,

D2 = 0 CCITT
D2 = 0 Dl D
D2 = 1 D2

COMMON RECEIVE INPUT SIGNALS:
PUP

Power-Up

This signal initializes the RB070. It can also be used as a "hands off' restart.
After power is applied and RCLK and TCLK are active, PUP must be held low for at least
16 clock cycles to el'lSure output predictability (refer to Power-Up Timing Requirement
Diagram).

RCLK

Receive Clock

An external timing source is input via the RCLK pin to provide the master timing for the
receive function

RIDLE

Receive Idle Control

When RIDLE IS high and RMW is low, Idle codes are substituted for all received
message channels; this Signal is sampled channel-by-channel

RMRST

Receive Master Reset

When RMRST is high, it forces the master state controller to go Into a "WAIT" state, if
a continuous level is maintained, and holds off entry to "IN IT" ("WAIT" = the inilial
step of the synchrOnization process).

RMW

Receive Milliwatt

When RMW is high and RIDLE is low, RMW causes the internal 1 kHz milliwatt
generator to be substituted for all received message channels. This signal is sampled
channel-by-channel.

RPOS, RNEG

Receive Unipolar
Positive and Negative

Input data to the receiver which may be of RZ or NRZ nature. When RPOS is strapped
to RNEG it causes:
1. BBZS or HDBS modes to become transparent for transmit functions and receive functions.
2. Disabling of the bipolar violation detector.

RSRCH

Receive Search
Control

When low, RSRCH holds off entry to "INIT", the second step of the initializaliOn
process. When RRED and RSRCH are active low dUring the first time slot of the first
frame of the multiframe, bit 5 is skipped.

COMMON RECEIVE OUTPUT SIGNALS:
RRED

Receive Red Alarm

RRED is high when the receiver IS not synchronized.
RRED when low indicates that the receiver is frame synchronized. It mayor may not
be multiframe synchrOnized.

RSER

Receive Serial Data

RSER represents the received serial data bit stream, including any BBZS or HDBS
corrections.

RSYNC

Receive
Synchronization State
Indicator

RSYNC provides a SYNC output that is dependent upon the receive master state.
1. SYNC (North American): Single pulse coinciding with the first 'F' bit for each new
multiframe, as shown in the North American Mode Receive Synchronization Timing
Diagram.
2. SYNC (European): Single pulse coinciding with bit one of each new multiframe, as
shown in the European Receive Synchronization Timing Diagram.

RVLL

Bipolar Violation, Loss
of Carner

RVLL reports bipolar violations as a high-level coinclden! with the emergence of thA
accused bit at RSER. Also, RVLL reports failure to receive carrier.

RYEL

Receive Yellow Alarm

RYEL conveys yellow alarm information appropriate to mode. RYEL transitions occur
one bit time after the bit that triggered the alarm merges out RSER.

[I
I

8-27

T-1/CEPT PCM Transceiver

R8070

R8070 Input/Output Signal Characteristics (Continued)
Mnemonic

Definition

Function

PARALLEL MODE RECEIVE OUTPUT SIGNALS:
RCHCLK

Receive Channel
Clock

RCHCLK is high during the output of bits I through 4 of the channel data on RSER.
RCHCLK is low elsewhere.

RCHSYNC

Receive Channel
Synchronization

RCHSYNC is suitable for synchronizing external counters to the T-I or CEPT frame
rate. Transittons on RCHSYNC are mode dependent.

RI-R8

Receive Channel
Data Bits 1-8

RI-R8 are valid with the current channel data nominally for 8 bit times and extend to 9
or 10 bit times in cases where an 'F' and/or link bit occur Transitions cOincide with the
output of Bit I on RSER. Refer to the Parallel Mode Receive Signals Timing Diagram.

RWIHBT

Receive Wnte Inhibit

RWIHBT covers the parallel channel data transition period. It goes high-active before,
during, and after the transitions on RI-R8.

SERIAL MODE RECEIVE INPUT SIGNALS:
RSHIFT

Receive Shift

When RSHIFT IS high, it causes the RSQ codes to be shifted.

RSR

Receive Sequence
Retard

When RSR is high, the RSQ codes and RSIGSQ transitions are delayed by one bit
time from their nominal posittons.

SERIAL MODE RECEIVE OUTPUT SIGNALS:
RSIGSQ

Receive Signalling
Square Wave

RSIGQ exhibits a high-to-Iow transition during the output of the F-bit at RSER for
frames carrying "B" (D) Signalling and low-to-high transition dunng the output of the
F-bit at RSER for frames carrying "A" (C) signalling. It is affected by RSR In the same
manner as the RSQ leads.

RSQI, RSQ2, RSQ3,
RSQ4 and RSQ5

Receive Sequence
Code Bits I through 5

RSQI through RSQ5 encode the current channel number according to CCITT
convention. During the occurrence of framing, link and CRC bits, speCial codes are
observed.
Refer to the 197 Mode Receive Sequence Code Timing Diagram.

MODE DEPENDENT RECEIVE OUTPUT SIGNALS:
RABCD

Receive ABCD

RABCD represents a serial bit stream containing the most recently received signalling
bits for each of the 30 channels. RABCD is channel-aligned With RSER.

RIBITS (OB)

Receive International
Bits

RIBITS goes high to indicate that the international bit is present at senal output RSER,
as shown in the National and International Bits Timing Diagram.

RNBITS (OE)

Receive National Bits

RNBITS is active-high coincident with the emergence of bits 4 through 8 of TSO not
containing the frame alignment signal.

RTSI6 (OC)

Receive Time Slot 16

RTSI6 is high for the duration of TSI6 bits I through 8 emerging from output RSER

RXBITS (DG)

Receive Extra Bits

RXBITS IS active-high when RSER contains bits 5, 7 and 8 of TSI6 containing the
multlframe alignment Signal

MODE DEPENDENT RECEIVE ERROR
OUTPUT SIGNALS:
CKERR (DC)

CycliC Redundancy
Check Bit Error

CKERR pulses high with the emergence of the "F" CRC bit at RSER if a cycliC bit
error is detected.

ERR (OD)

Error Signal

ERR pulses high for one bit time upon detection of a framing error or check sum error.

FERR (OD)

Framing Error

This signal pulses high for one bit time, upon detection of a framing or check sum
error. Response varies according to mode. Applicable to 193A, S & N, 1975 & N, &
256N modes.

8-28

R8070

T·1/CEPT PCM Transceiver
RS070 Input/Output Signal Characteristics (Continued)

Mnemonic

Definition

Function

MODE DEPENDENT RECEIVE ERROR
OUTPUT SIGNALS (Continued):
FMERR (OD)

Receive Frame
Multiframe Error

FMERR pulses high for one bit time to indicate detection of either frame or
multiframe errors. Applicable to 256S mode.

RMRED (OC)

Receive Multiframe Red

RMRED is active-high when two consecutive multiframe alignment errors have
occurred or if all TS16 data bits are low for a complete multiframe. When RMRED
is high, the transmitter transmits a multiframe yellow alarm in bit 6 of TSI6,
containing the multiframe alignment signal.

RMYEL (OF)

Receive Multiframe
Yellow

RMYEL contains the extracted bit 6 of TS16 that represents the multiframe
alignment signal.

SERR (OE)

S-Bit Errors

SERR pulses high for one bit time each time an error IS observed in the received
S-bit pattern.

MODE DEPENDENT RECEIVE SIGNALLING
OUTPUT SIGNALS:
MS1, MS2 (OF, OG)

Master State
Sequence Code

The two least Significant bits MSI and MS2 are of the master state sequence code.

RLCLK (OG)

Receive link Clock

RLCLK represents a square clock at the data rate of RLiNK.

RLiNK (OF)

Receive Data Link

RLiNK reports data extracted from the "Received Link Data," occurnng at the rates
corresponding to the vanous transmission modes (refer to 256N mode Receive Link
Data Timing Diagram).

RLlNKl (OC)

Receive link 1

An active-high level Indicates the reception of 255 consecutive ones In time slot 16.

RMFA (OA)-193F mode
RMFA (OB)-256S mode

Receive Multlframe
Alignment

RMFA IS high for the durallon of frame 24. TranSitions coincide with the emergence
of the "F" bits at RSER.
In the 256S mode, RMFA is active-high for the duration of the frame which contains
the multlframe alignment signal.

RSBCLK (OC)

Receive S-Bit Clock

RSBCLK is a 4 kHz square clock whose low to high transition occurs 1 bit after the
emergence of RSBIT (Fs) at RSER.

RSIG (OA)

Receive Signalling
Frame

RSIG IS active-high during the receipt of Signalling frames. Activity IS suspended If
recent errors have been observed in the F-bit or S-bit.mode dependent signal.

RSIGBD (OB)

Receive Signalling B
or D

RSIGBD represents a 2 kHz square wave With low-to-hlgh transilions occurnng
during frames containing the A or C Signalling, and hlgh-to-Iow transitions occurnng
during frames containing B or D signalling.

RSIGCD (OC)

Receive Signalling C
or D

RSIGCD represents a 1/3 kHz square clock with transitions COinCiding With the
emerging F-bit at RSER.

RSBIT (OB)

Receive SignallingFraming Bit

RSBIT IS the most current received S-bit COincident With the emergence of the S-bit
at RSER and is mode dependent.

COMMON TRANSMIT INPl T SIGNALS:
TCLK

Transmit Clock

All inputs of the transmit secllon are sampled on the riSing edge of TCLK.

TFSYNC

Transmit Frame Sync

TFSYNC synchronously restarts the transmitter to the beginning of a frame
TFSYNC reinforces the Internal count cycle when pulsed once per frame.

I

8-29

T-1/CEPT PCM Transceiver

R8070

R8070 Input/Output Signal Characteristics (Continued)
Mnemonic

Function

Definition

COMMON TRANSMIT INPUT SIGNALS (Continued):
TIDLE

Transmit Idle

When high, TIDLE causes the transmitter to output idle code in all message channels
via TNRZ, TPOS and TNEG.

TLOOP

Transmit Loop

When high, TLOOP causes the transmitter to alternately transmit ones on TPOS and
TNEG, and the transmitter Internal TPOS and TNEG signals to be routed to the receive
function in place of RPOS and RNEG. TLOOP does not affect TNRZ.

TMSYNC

Transmit Multiframe
Sync

When active-high, it synchronously sets the internal frame counter to the first frame of
a multiframe.

TYEL

Transmit Yellow Alarm

High level on TYEL activates the transmission of a yellow alarm and is mode dependent.

COMMON TRANSMIT OUTPUTS:
TMAX

Transmit Maximum

TMAX pulses high for one bit time coincident with the sampling of the last serial bit of
a multiframe.

TNRZ

Transmit Non-Return
to Zero

This output contains the non-return-to-zero bit stream of the transmitter. TNRZ is not
affected by TLOOP, HDB3 or B8ZS functions.

TPOS, TNEG

Transmit Positive,
Negative

TPOS and TNEG contain the transmit output bit stream conditioned for alternate mark
inversion. This sequence of steering alternate ones for each of these outputs is
deliberately broken when a B8ZS or HDB3 substitution takes place.

PARALLEL MODE TRANSMIT OUTPUT:
TCHCLK

Transmit Channel
Clock

TCHSYNC

Transmit Channel
Sync

TCHCLK Indicates times when parallel data has been sampled.

TCHSYNC IS an 8-bit signal active pnor to the sampling of parallel data for the first
message channel.

SERIAL MODE RECEIVE INPUT SIGNALS:
TSA

Transmit Sequence
Advance

When TSA IS high, transitions on TS01-TS05 and TSIGSO are advanced one bit time
Refer to the Transmit Seqence Code Timing Diagram.

TSIGMD

Transmit Signalling
Mode

TSIGMD indicates that signalling is Included within the senally Input bit stream or
through dedicated signalling Inputs. The effect of TSIGMD varies for different modes.

TABCD

Transmit Signalling
ABCD

TASCD consists of a senal bit stream containing transmit signalling sampled at an
8 kHz rate for each of the 30 channels, applicable to the 256S mode

TSER

Transmit Serial

TSER IS a serial bit stream containing the message data

SERIAL MODE RECEIVE OUTPUT SIGNALS·
TSIGSO

Transmit Signalling
Square

TSIGSO is a 2/3 kHz square wave aligned to cause certain per-channel codecs to
insert A and B signalling into TSER.

TS01-TS05

Transmit Sequence
Code Bits 1-5

TS01-TS05 represent the transmit sequence codes with coding identical to RSO
When TSA is high, these transitions occur an additional bit time earlier

PARALLEL MODE TRANSMIT INPUTS:
Tl-T8

Transmit Channel Data
Bits 1-8

Tl-T8 are sampled by the nsing edge of the TCLK These Inputs should be applied
when TCHCLK IS low

8-30

R8070

T-1/CEPT PCM Transceiver
R8070 Input/Output Signal Characteristics (Continued)

Mnemonic

Definition

Function

FRAMING MODE DEPENDENT TRANSMIT
INPUT SIGNALS:
TDATIS (IC)

Transmit Data Ones

A high level on TDATIS triggers the transmission of all ones In time slot 16.

TLNKMD (10)

Transmit Link Mode

A one or zero level on TLNKMD selects between data or Link information to be
transmitted in TS16 (applicable to 256N mode).

TA(C), TB(D), lA, IB

Transmit TA(C) and
TB(D) Signalling

These signals provide A(C) and B(D) robbed-bit signalling
A and B are selected when TSIGSEL
C and 0 are selected when TSIGSEL

= O.
= 1.

These conditions are applicable to the 193E.
TA, TB, IA and IB

Transmit A and B
Signalling

TA and TB are sampled at the beginning of a channel time to provide A and B robbedbit signalling (applicable to the 1935 and 1975 modes).

TIBITS, TNBITS,
TXBITS

Transmit international,
national and extra bits

These signals allow the transmission of the international, national and extra bits
Applicable to modes 256 S&N.

TFSIG (10)

Framing-Bit Signal

TFSIG input provides the Fr and Fs bits (mode dependent) The Input IS sampled
COincident with the sampling of channel one parallel data.

TLiNK (IC)

Transmit Link

Provides a serial data link input at either 4, 32, or 64 Kbps, depending on mode
(eqUivalent to the rates on RLINK).

YELMD (IC)

Yellow Alarm

YELMD input selects method for Transmission and detection of yellow Alarm If low,
yellow Alarm will be transmitted as the inhibit of bit 2 If high, yellow Alarm is Identified
as the Fs bit for frame 12

TSBIT (IA)

Transmit S-bit

In modes 193N and 197N, this Input IS sampled to proVide the transmitted S-bit to
control the S-bit transmiSSion

FRAMING MODE DEPENDENT TRANSMIT
OUTPUT SIGNALS:
TTS16 (OJ)

Transmit Time Slot 16

Active for 8 bit times prior to the sampling of TS16 data at TSER.

TMFA (OH)

Transmit Multlframe
Alignment

TMFA is active during sampling of data for frames containing the multlframe alignment signal

TN SYNC

Transmit National
Bit-Sync

TN SYNC is active-high during sampling of the national bits (bits 4 through 8) of TSO for
frames not containing frame alignment

TFGEN (OJ)

Framing-Bit Generator

ThiS signal is the composite framing pattern generator. It IS the result of multipleXing
externally-supplied S-blt data with the internally-generated framing pattern, the data link
and the CRC check bits appropriate to the operating mode

TFR24 (OE)

Transmit Frame 24

A high level on TFR24 Indicates that frame 24 IS being processed.

TLCLK (OH)

Transmit Link Clock

TLCLK represents a square clock at the data rate of TLiNK.

TSBCLK (OE)

Framing-Bit Generator

TSBCLK IS a 4 kHz square wave whose rising edge occurs two bit times after the
TSBIT Input has been sampled.

TSIGSEL (0 E)

Transmit Signalling
Select

When low, it Indicates that A and B channels are being sampled When high, it
Indicates that C and 0 channels are being sampled Transitions COincide With the
<:Bmpnl')g time of the "~" bits

i

I

8-31

T-1/CEPT PCM Transceiver

R8070

POWER - - - - - - - - - - " "

CLOCK

SEE TIMING REQUIREMENTS
PUP - - - - - - - - " " ' \

TRISTATE " 1 " - - - - - - - - - - - .
OUTPUTS "0"
DATA

)>---------------« . . ______D_AT_A_ _ _ _ __

Power Up Timing Requirement

RCLK

RSER
RRED ______________-+~--'~

__- - - - - - - - - -____--__----------------

RSYNC _ _ _ _ _ _ _ _ _ _ _ _J
SEE TIMING REQUIREMENTS

L -_____________________________________________________________________ _

North American 193 Mode Receive Synchronization Timing

8·32

T-1/CEPT PCM Transceiver

R8070

RCLK

RSER

RRED __________________~,~----------------------------------------------RSYNC __________________--1'

European Receive Synchronization Timing

RCHCLKJ

\ ...._ _-J!

\~

Rl-R8:J<____~C~H~A~N~NE~L~2~3~___JX~

___-J!

______C~H~A~N_N~E~L~2_4

____--JX~

\\.... _ _-Jr-

______

C_HA_N_N_E_L_l____~>e:::::

RSER --1 ' L J 'L,.J
SEE TIMING REQUIREMENTS
RWIHBT

J,c

\~------------

RCHSYNC ______________________

NOTE: ABOVE TIMING IS APPLICABLE
TO ALL 193 MODES.

Parallel Mode Receive Signals Timing

8-33

R8070 '

T-1/CEPT PCM Transceiver

:.

RCLK

RSQS
RSQ4

---H--------------~

SEE TIMING REQUIREMENTS

RSQ3
RSQ2
RSQ1

=

NOTE: 010 & 02
0
RSHIFT
0
RSR
0

=

=

197 Mode Receive Sequence Code Timing

RCLK

RSER
RIBITS

RNBITS

------------~

------------~r-------~

National and International Bit Timing

,

',

.....

8-34

T-1/CEPT PCM Transceiver

R8070

RCLK
TIME SLOT 15
RSER

RLINK

BIT 8 FRAME N-1

RLCLK

________

RTS16

~-----------------J

f

_ _ _ _- J

256N Mode Receive Link Data Timing

TCLK

TSER

TSQ1TSQS
I-----ISQS

----.J

SEE TIMING
REQUIREMENTS

TSA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J
ISQA

TSQ1TSQ5

Transmit Sequence Code Timing

8-35

SEE TIMING
REQUIREMENTS

T-1/CEPT PCM Transceiver

R8070'
FRAMING MODE SUMMARY
The framing mode dependent signals are summarized in the
table below. Inputs IA-ID and output OA-OJ are functionally
related to the various modes of operation as previously
discussed.

Framing Mode-Dependent Signals
Inputs

Modes
193N

PIN
IA
IB
IC
ID

TSBIT

,
,

TFSIG

197N

1935
TA
TB
YELMD
TFSIG

TSBIT

1975

TLiNK
TFSIG

TA
TB
TLiNK
TFSIG

RSIG
RSBIT
RSBCLK
FERR
TSBCLK
RLiNK
RLCLK
TLCLK
TFGEN

RSIG
RSBIT
RSBCLK
FERR
SERR
RLiNK
RLCLK
TLCLK
TFGEN

Outputs
OA
OB
OC
OD
OE
OF
OG
OH
OJ

193E
TA(C)
TB(D)
TLiNK
TFSIG

193F

,

,
TLiNK
TFSIG

256N

256S

TIBITS
TNBITS
TLiNK
TLNKMD

TIBITS
TNBITS
TDAIS
TXBITS

RTS16
RIBITS
RLlNK1
FERR
RNBITS
RLiNK
RLCLK
TLCLK
TTS16

RTS16
RMFA
RMRED
FMERR
RNBITS
RMYEL
RXBITS
TMFA
TTS16

Modes
RSIG
RSBIT
RSBCLK
FERR
TSBCLK
MS1
MS2
',

RSIG
RSBIT
RSBCLK
FERR
SERR
MS1
MS2

TFGEN

TFGEN

,,

RSIG
RSIGBD
RSIGCD
ERR
TSIGSEL
RLiNK
RLCLK
TLCLK
TFGEN

RMFA

"
CKERR
FERR
TFR24
RLiNK
RLCLK
TLCLK
TFGEN

Notes
'Test Inputs. preferably lied to a high level
"Test outputs, leave unloaded

INPUT/OUTPUT SETUP/HOLD TIMES
Input/Output Setup/Hold Times

Timing Requirements

Output
(Transmitter/Receiver)

Maximum
Delay

Unit

(Measured from rising edge
of clock unless stated
otherwise)

100

ns

Input (Transmitter/Receiver)

Minimum
Setup
Time

Unit

Input Setup and Hold Times

60

ns

tUPH (power up hold time) '" 16 clock periods minimum
tSQS (TSO setup time) = 1 clock period or 2 depending on
TSA
tOST (transmit data setup time) = 60 ns minimum
tRo (receive data ouput delay) = 100 ns maximum
tSNW (RSYNC pulse width) = 1 clock period
tRW (write inhibit pulse width) = 2 clock periods typical
tSNW (RSYNC pulse width) = 1 clock period typical
tSQA (TSO advance time) = 1 clock period
tooo (transmit data output delay) = 100 ns maximum
tRST (receive input setup time) = 60 ns minimum
tRHT (receive input hold time) = 60 ns minimum

8-36

T·1/CEPT PCM Transceiver

R8070
MAXIMUM RATINGS*
Symbol

Value

Unit

Supply Voltage

Parameter

Vcc

+ 4.75 to 5.25

Vdc

Operating Temperature
Commercial
Industrial

Topc
TOPI

to +70
-40 to + 85

·C

Storage Temperature

TSTG

-55 to +150

·C

o

'NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Parameter

Symbol

Input Logic "1" Voltage

VIH

Min

Max

Unit

2.0

Vcc + 0.3

V

Test Condition

Input Logic "0" Voltage

VIL

-

08

V

Output Logic "1" Voltage

T2L
VOH CMOS

24
35

-

V

ILOAD
ILOAD

Output Logic "0" Voltage

VOL

-

04

V

ILOAD

Output Source Current

IOH

Output Sink Current

IOL

Clock Frequency

TCLK

pA

V OH = 2.4V

+ I.S

mA

VOL = 04V

2.049

MHz
pF

-100

100 kHz

Input CapaCitance

GIN

5

Output CapaCitance

COUT

50

pF

Power DissipallOn

PWD

100

mw

REFERENCE DATA
For detail information refer to the R8D7D T-l/CEPT PCM
Transceiver Designer's Guide. Order Number 313.

8-37

= - 1 SmA
= - !DOILA
= + I.S mA

T·1/CEPT PCM Transceiver

R8070
PACKAGE DIMENSIONS

64 PIN PLASTIC QUIP

DIM
A
B

C
D
F
G

H

J
K
L
M

1-

"I~

A

I~~
K ,

--U--

H

-If--

0

-,

8-38

MILLIMETERS
MIN
MAX
4115 4166
1702 1753
305
456
036
051
127 esc
254 esc
102
114
7'
279
432
1692 1961
2337 2362

INCHES
MIN
MAX
1620 1640
0870 0890
0120 0160
0024 0020
0050 esc
0100 esc
0040 0045
7'
0110 0170
0745 0755
0920 0930

SEMICONDUCTOR PRODUCTS DIVISION REGIONAL ROCKWELL SALES OFFICES
HOME OFFICE
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Rockwell International
4311 Jamboree Rd
P.O Box C, MS 501-300
Newport Beach, CA 92658-8902
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UNITED STATES
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Semiconductor Products DiYision
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Ci.lrr!~, Pe3!< £..

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MI. Airy
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(800) 336-3747 (MO, DE)
(703) 591-1300

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NEW JERSEY
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CUrrie, Peak and FraZier, Inc
(404) 449-7662

PAF ASSOCiates, Inc
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Naudam Assoc , Inc
(609) 983-5300

Note Refer to Rockwell Document RD-1 for detailed address mformatlOn

A-1

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Tulsa
Norcom, Inc

(g-;3) O:J2-7747

SALES REPRESENTATIVES (Continued)
PENNSYLVANIA
Naudaln Assoc., Inc.
(See Marlton, New Jersey)
Pittsburgh
Robert O. Whitesell & Associates
(412) 963-6161
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(See Burlington, Massachusetts)
SOUTH CAROLINA
Columbia
Currie, Peak and Frazier, Inc.
(803) 254·1971
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TENNESSEE
Knoxville
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Austin
Norcom, Inc.
(512) 451-2757

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WEST VIRGINIA
Robert O. Whitesell & Associates
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VIRGINIA
Fairfax
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(703) 591·1300
(800) 336·3747 (MD, DEL)

WISCONSIN
Wauwatosa

Dallas

Forest

Norcom, Inc.

Beacon North, Inc.

(214) 386-4888

(804) 239·8486

Houston
Norcom, Inc,
(713) 778-0392

WASHINGTON, D.C.
Beacon North, Inc.
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Larsen Associates Inc.
(414) 258·0529
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Wlllowdale, Ontario
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A-2

INDUSTRIAL DISTRIBUTORS
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Fairfield

Advent Electronrcs
(319) 363-0221

Hamllton/Avnet ElectroniCs
(201) 575-3390

Fairfield
Semlspeclahsts of Amenca Inc
(201) 227-7444

A-3

Columbus
Graham Electronrcs
(614) 895-1590

Voyager Electronrcs Corporation
(612) 571-7766

MISSOURI
Earth City

Indianapolis

Cleveland
CAM/A PC

Livonia
(313) 525-2700

Hamllton/Avnet
(317) 844-9333

Santee
Mouser Electronrcs
(619) 449-2229

Image ElectrOnics
(714) 730-0303

Greensboro
Hammond Electronics
(919) 275-6391

Norcross
Hammond ElectroniCS
(404) 449-1996

(408) 743-3355

Tustin

NORTH CAROLINA

Cincinnati
Graham Electronrcs
(513) n2-1661

Rosemont
Advent Electronrcs
(312) 298-4210

Torrance
Hamllton/Avnet Electronrcs
(213) 615-3931

Grand Rapids

Rochester

Hamllton/Avnet ElectronIcs
(616) 243-8805

(312) 982-9210

Sunnyvale
Hamllton/Avnet ElectrOniCs

Advent ElectroniCS
(313) 477-1650

Rochester

CAM/RPC

Norcross
Hamllton/Avnet Electronics
(404) 447-7500

Hamllton/Avnet Electronics
(619) 571-7510

Sunnyvale

MICHIGAN
Farmington Hills

GEORGIA

San Diego

Bell Industnes
(408) 734-8570

Liverpool
Future ElectrOniCs
(315) 451-2371

Westboro

Winter Park

Western Micro Technology Inc
(408) 725-1660

MASSACHUSETTS
Canton
Alma ElectroniCS
(617) 821-1450

Hamllton/Avnet Electronics
(305) 628-3888

Hamllton/Avnet ElectroniCs
(213) 558-2441

Farmingdale
SemlspeCiahsts of Amenca Inc
(516) 293-2710

Largo

Culver City

Culver City

Rockville
Alma ElectrOniCs Corp
(301) 792-9197

Hamllton/Avnet ElectrOnics
(305) 971-2900

(714) 641-4100

Hamilton Electro Sales
(213) 558-2121

NEW YORK
East Syracuse

East Haven
J V ElectrOniCs

Hamden

Hamilton Electro Sales
(818) 700-2600

Albuquerque
Bell Indust"es
(505) 292-2700

Hamllton/Avnet Electronics
(315) 437-2641

Alma Electronics
(203) 288-6556

Hamllton/Avnet Electronics
(818) 700-6500

(505) 765-1500

Hamllton/Avnet ElectroniCs
(301) 995-3550

Tempe
Bell Industnes
(602) 966-7800

MARYLAND
ColumbIa

NEW MEXICO
Albuquerque
Hamllton/Avnet ElectroniCS

Hamllton/Avnet Electronics
(203) 797-2800

Hamllton/Avnet Electronics
(602) 231-5100

CALIFORNIA
Chatsworth

KANSAS
Cedar Rapids

(513) 434-8231

Westerville
Hamilton/Avnet Electronics
(614) 436-4158

OKLAHOMA
Tulsa
Quality Components, Inc
(918) 664-8812

INDUSTRIAL DISTRIBUTORS (Continued)
OREGON

TEXAS

WASHINGTON

CANADA

Beaverton

Addison

Bellevue

Calgary, Alberta

Western Micro Technology Inc
(503) 629-2082

Quality Components, Inc.
(214) 733-4300

Bell Industries
(206) 747-1515

Card mal Industrial Electronics. Ltd
(403) 259-6817

Lake Oswego

Austin

Bellevue

Calgary, Alberta

Bell Industries
(503) 241-4115

Quality Components, Inc.
(512) 835-0220

Hamilton/Avnet Electronics
(206) 643-3950

Hamllton/Avnet Electronics
(403) 230-3586

Lake Oswego

Austin

Redmond

Hamllton/Avnet Electronics
(503) 635-8157

Hamilton/Avnet ElectroniCS
(512) 837-8911

Western MIcro Technology Inc
(206) 881-6737

Downsvlew, Ontario
Future Electronics Inc.
(416) 663-5563

PENNSYLVANIA
Philadelphia
Alma Electronics
(215) 698-4000
Pittsburgh
Alma Electronics
(412) 931-5990

Pittsburgh
CAM/RPC
(412) 782-3770

York
E C.I
(717) 843-8971

Irvine (Dallas)
Hamllton/Avnet Electronics
(214) 659-4111

WISCONSIN
Milwaukee
Industrial Electronics Corp
(414) 276-1212

Houston
Hamllton/Avnet Electronics
(713) 780-1771

New Berlin
Hamilton/Avnet ElectroniCS
(414) 784-4510

Sugarland
Quality Components, Inc
(713) 491-2255

Waukesha
Bell Industries
(414) 784-0235

UTAH
Salt Lake City
Hamllton/Avnet Electronics
(801) 972-2800

Edmonton, Alberta
Cardinal Industnal Electronics Ltd.
(403) 483-6266
Mississauga, Ontario
Hamllton/Avnet Electronics
(416) 677-7432
Montreal, Quebec
Future Electronics Inc
(514) 694-7710
Nepean, Ontario
Hamllton/Avnet Electronics
(613) 226-1700
Ottawa, Ontario
Future Electronics Inc
(613) 820-8313

TENNESSEE
Nashville
Graham Electronics
(615) 242-2682

St. laurent, Montreal, Quebec
Hamllton/Avnet Electronics Ltd.
(514) 335-1000
Toronto, Ontario
Canadian General Electnc
(416) 530-2921
Vancouver, B.C.
Future ElectrOnics, Inc
(604) 438-5545

A-4
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