1985_Siemens_Industrial_IC_Data_Book 1985 Siemens Industrial IC Data Book
User Manual: 1985_Siemens_Industrial_IC_Data_Book
Open the PDF directly: View PDF 
.
Page Count: 1000
| Download | |
| Open PDF In Browser | View PDF |
-m
SIEMENS
~
m
Z
tit
:::J
c..
c
...Cir
!!L
IlidustriallC Data Book
1985
Microprocessors _ Microcontrollers _ Peripherals _ Support
Memory _ Telecom _ Data Converters _ SM PS Controllers
Table of Contents
General Information
Summary of Types
Microcontroller and Microprocessor Components
Peripheral and Support Components
Memory Components
Telecom Components
Data Conversion Components
Switched Mode Power Supply (SMPS) Components
Integrated Circuits for Consumer Applications
SIEMENS
Industrial Ie
Data Book 1985
Table of Contents
Table of Contents
Page
1.
General Information
1.1
1.2
1.3
Type designation code for ICs ........................................
Mounting instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Processing guidelines for ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Identification
Scope
Handling of devices
Storage
Transport
Incoming inspection
Material and mounting
Electrical tests
Packaging of assembled PC boards or flat pack units
Ultrasonic cleaning of ICs
Electrical and environmental ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Maximum ratings
Electrical characteristics
Operating data
Mechanical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Package dimensions
Shipping tube dimensions
Quality and reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Quality assurance system
Quality specifications
Quality conformance
Reliability
Thermal coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4
1.5
1.6
1.7
15
15
16
19
20
33
40
2.
Summary of Types
2.1
Component selection guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43
3.
Microcontroller and Microprocessor Components
SAB 8031/8051
SAB 8031/8051-EXT
8-bit single chip microcomputer ................... 49
8-bit single chip microcomputer with extended
temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65
SAB 8031A/8051A
8-bit single chip microcomputer ................... 81
SAB 8031A/8051A-EXT 8-bit single chip microcomputer with extended
temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 99
SAB 8032A/8052A
8-bit single chip microcomputer ................... 117
SAB 80C482
8-bit single chip CMOS microcomputer .... '......... 133
SAB 8086
16-bit microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . .. 161
SAB 8088
16-bit microprocessor with 8-bit data bus interface. .. 199
SAB 80186
High integration 16-bit microprocessor. . . . . . . . . . . .. 229
High integration 16-bit microprocessor with 8-bit data
SAB 80188
bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 231
High performance 16-bit microprocessor with memory
SAB 80286
management and protection . . . . . . . . . . . . . . . . . . . .. 233
7
Table of Contents
4.
Peripheral and Support Components
SAB
SAB
SAB
SAB
SAB
SAB
SAB
SAB
SAB
1791/93/95/97
2793A/97A
8237A
8256A
8259A
8275
8276
8282A/8283A
8284B
SAB
SAB
SAB
SAB
SAB
8286A/8287A
8288A
8289
82258
82284
SAB 82288
SAB 82289
SAB 82731
5.
SAB 81C52
HYB 4164
HYB 41256
HYB 41257
8
Floppy disk formatter/controller ................... 299
Floppy disk formatter/controller .................... 325
High performance programmable DMA controller ..... 353
Programmable multifunction UART (MUART) ........ 369
Programmable interrupt controller ................. 395
Programmable CRT controller ..................... 405
Small system CRT controller ...................... 433
Octal latch .................................... 459
Clock generator and driver for SAB 8086
family processors ............................... 465
Octal bus transceiver ............................ 479
Bus controller for SAB 8086 family processors ....... 485
Bus arbiter for SAB 8086 family processors ......... 495
Advanced DMA controller for 8 or 16-bit systems ..... 507
Clock generator and ready interface for SAB 80286
family processors ............................... 555
Bus controller for SAB 80286 family processors ...... 567
Bus arbiter for SAB 80286 family processors ........ 593
Dot rate generator .............................. 595
Memory Components
SAB 81C50/81C51
6.
Page
CMOS static ram; 256 X 8-bit with multiplex bus
interface ...................................... 625
CMOS static ram; 256 X 8-bit with multiplex bus
interface ...................................... 631
DynamiC ram; 65, 536 X 1-bit ..................... 639
Dynamic ram; 262, 144 X 1-bit .................... 653
Dynamic ram; 262, 144 X 1-bit with nibble mode ..... 669
Telecom Components
PEB
PEB
PEB
PEB
PEB
2030
2040
2050
2051
2060
PSB
PSB
PSB
PSB
PSB
PSB
SAB
SAB
6520
6521
6620
8590
8591
8592
80C482
81 C50/81 C51
Frame alignment circuit .......................... 689
Memory time switch ............................. 697
Peripheral board controller .......................713
Peripheral board controller ....................... 733
Programmable digital signal processing
CODEC-FIL TER ................................ 751
Tone ringer ...............................•.... 769
Tone ringer .................................... 781
Ring detector .................................. 795
DTMF generator/dialer ........................... 801
DTMF generator/dialer ........................... 819
DTM F generator/dialer ........................... 843
8-bit single chip CMOS microcomputer ............. 133
CMOS static ram; 256 X 8-bit with multiplex bus
interface ...................................... 625
Table of Contents
Page
SAB 81C52
PSB 7510
7.
Data Conversion Components
SDA
SDA
SDA
SDA
SDA
8.
CMOS static ram; 256 X 8-bit with multiplex bus
interface ...................................... 631
CMOS LCD controller ........................... 853
5200N
5200S
6020
8005
8010
6-bit
6-bit
6-bit
8-bit
8-bit
flash AID converter ......................... 875
flash A/D converter ......................... 881
flash A/D converter ......................... 887
high speed D/A converter .................... 893
flash A/D converter ......................... 905
Switched Mode Power Supply (SMPS) Components
TDA
TDA
TDA
TDA
TDA
TDA
4600-2/4600-20
4601/46010
4700/4700A
4714A/4714B
4716A/4716B
4718/4718A
Control
Control
Control
Control
Control
Control
IC
IC
IC
IC
IC
IC
for
for
for
for
for
for
switched
switched
switched
switched
switched
switched
mode
mode
mode
mode
mode
mode
power
power
power
power
power
power
supplies
supplies
supplies
supplies
supplies
supplies
........ 919
........ 929
........ 943
........ 957
........ 969
........ 981
9.
Integrated Circuits for Consumer Applications
9.1
VHF/UHF Video Modulator IC ...........................................•
TDA 5660P
9.2
Video IF ICs . . . . . . . . . . . . . . . . . . . .
. ............................ .
TBA 1440G, TBA 1441, TDA 5510, TDA 2440, TDA 2441, TDA 5400, TDA 5410,
TDA 5430, TDA 6000
9.3
Video Single Pole Double Throw Switch IC ............................. .
TDA 5850
9.4
Quasiparallel Sound (Split Sound) Amplifier
TDA 4282T
9.5
Video IF/Quasi parallel Sound (Split Sound) Combo ICs ................... .
TDA 5830-2, TDA 5835
9.6
TV Stereo/Dual Sound (German Standard) and Matrix IC
TDA 6600
9.7
ICs for Switched Mode Power Supplies .............................. .
TDA 4600-2, TDA 4600-2D, TDA 4601, TDA 46010
9.8
IC for Pin Cushion Correction in CRT Applications ....................... .
TDA 4610
'See Consumer Data Book or contact your local Siemens Representative.
9
I
Table of Contents
Page
9.9
Programmable Multistandard Sync Pulse Generator ...................... .
S 178A
9.10
High Frequency Prescalers .......................................... .
SDA 2211, SDA 2311, SDA 4042, S 89, SDA 4211
9.11
Phase Locked Loop (PLL) Devices .................................... .
SDA 2112-2, SDA 3002, SDA 3112, SDA 3202, SDA 3203
9.12
Application Oriented Single Chip Microcomputers ....................... .
SDA 2010, SDA 2011, SDA 2030, SDA 2110, SDA 3010, SDA 3110, SAB 80215,
SAB 80315
9.13
IR Transmitter ICs, Preamplifiers, Receivers ............................ .
SDA 2008, SDA 2208, TDA 4050B, SAB 4209,
9.14
Non Volatile Memories .............................................. .
SDA 2116, SDA 2216
9.15
Display Drivers and Controllers ....................................... .
SDA 2131, SDA 2005, UAA 170, UAA 180, SDA 2014
9.16
Audio Control ICs .................................................. .
TDA 4290-2S, TDA 4292, TDA 6200
9.17
AF Power Amplifiers ............................................... .
S 1531G, TDA 1037, TDA 1037D, TDA 4930, TDA 4926, TDA 4935
9.18
Tuner/Mixer ICs/FM Receivers ....................................... .
TUA 2000-4, S 042P, TBB 469, TBB 1469, TBB 2469
9.19
FM IF Amplifiers with Demodulator ................................... .
S 041P, TBA 120S, TBA 120T, TBA 120U, TBA 129, TBA 130, TBA 229,
TDA 1047, TDA 4200-3, TDA 4210-3
9.20
AM IF Amplifiers with Demodulator ................................... .
TCA 440, TDA 1046, TDA 4001, TDA 1048G, TDA 2048
9.21
AM/FM-IF Combination IC ........................................... .
TDA 4100, TDA 4110X
9.22
PLL for AM/FM Receivers ........................................... .
SDA 2120, S 187B
9.23
FM Stereo Decoders ............................................... .
TCA 4500A, TCA 4511
'See Consumer Data Book or contact your local Siemens Representative.
10
Table of Contents
Page
9.24
Photoelectric Devices ............................................. .
TFA 1001W
9.25
Timer ICs ................................................... .
SAB 0529, SAB 0529G
9.26
Phase Control ICs ................................................. .
TLE 3101, TLE 3102, TLE 3103, TLE 3104, S 576A, S 576B, S 576C, S 5760,
TCA 785
9.27
DC Motor Control ................................................ .
TCA 955, TCA 2365, TLE 4201A/S
9.28
Window Discriminator ICs ..... .
TCA 965
9.29
Threshold Switches ................................................ .
TCA 105, TCA 105G, TCA 345A
9.30
Programmable Diode Matrix ......................................... .
S 353, S 1353, S 2353
9.31
Audible Signal Devices ............................................. .
SAB 0600, SAB 0601, SAB 0602, SAB 0700
9.32
Sensor ICs, Proximity Switches, Hall Effect Devices ..................... .
TCA 305A/G, TCA 355B/G, HKZ 101, HKZ 101S, TLE 4903, SAS 231W
'See Consumer Data Book or contact your local Siemens Representative.
11
I
General Information
I
General Information
1.1
Type Designation Code For ICs
The IC type designations are based on the European code system of Pro Electron.'
The code system is explained in the Pro Electron brochure D 15, 1982 edition, which
can be obtained from:
Pro Electron
Boulevard de Waterloo 103
1000 Brussels, Belgium
'Some exceptions exist.
1.2
Mounting Instructions
Plastic Package With 8, 14, 16, 18, 20, 22, 24, 28, or 40 Pins
The pins are bent downwards in a 90° angle and fit into holes with a diameter of between
0.7 and 0.9 mm spaced 2.54 mm apart. The dimension x(see figure below) is given
in the mechanical dimension drawings for the various packages.
The bottom of the package will not touch the PC board after insertion because the
pins have shoulders just below the package (see figure below).
After the package is inserted into the PC board, it is advisable to bend the ends of
two pins at an angle of approx. 30° to the board so that the package does not have
to be pressed down during soldering. Plastic packages are soldered on that side of
the PCB facing away from the package.
The maximum permissable soldering temperature is 265°C (max. 10 s) for manual
soldering and 240°C (max 4 s) for dip soldering.
-
Tin solder
Dimensions in mm
Figure 1
Power Package With 9 Pins
Power packages generally have wider pins than standard plastic packages; meaning
the hole diameter on the PCB must be between 1.1 and 1.8 mm. If the pins are bent,
there should be no stress between the pins and the package. The minimum distance
between the package and the bending point is 2 mm.
The soldering temperatures for power packages are the same as for plastic packages.
Micropack Packages
Mounting instructions for components available in a micropack are found within the
Data Sheet.
15
General Information
Precautions
Ensure that no current is able to flow between the solder bath or soldering iron and
the PCB. It is advisable to ground the pins that are to be soldered as well as the solder
bath or soldering iron.
When they are being prepared and inserted in a PCB, integrated circuits should be
protected against static charging. Under no circumstances may the components be
removed or inserted while the operating voltage is switched on.
The increase in chip temperature during the soldering process results in a temporary
increase in electrostatic sensitivity of integrated circuits. Special precautions should
therefore be taken against line transients, e.g. through the switching of inductive loads.
1.3
Processing Guidelines For ICs
Integrated circuits (ICs) are electrostatic-sensitive (ESS) devices. The requirement for
greater packing density has led to increasingly small structures on semiconductor chips,
with the result that today every IC, whether bipolar, MOS, or CMOS, has to be protected against electrostatics.
MOS and CMOS devices generally have integrated protective circuits and it is hardly
possible any more for them to be destroyed by purely static electricity. On the other
h~lnd, there is acute danger from electrostatic discharges (ESD).
Of the multitude of possible sources of discharge, charged devices should be mentioned in addition to charged persons. With low-resistance discharges, it is possible
for peak power amounting to kilowatts to be produced.
For the protection of devices, the following principles should be observed:
a) Reduction of charging voltage, below 200 V if possible. Means which are effective
here are an increase in relative humidty to ;::: 60% and the replacement of highly
charging plastiCS by antistatic materials.
b) With every kind of contact with the device pins a charge equalization is to be
expected. This should always be highly resistive (ideally R : 106 to 108 ohms).
All in all this means that ICs call for special handling, because uncontrolled charges,
voltages from ungrounded equipment or persons, surge voltage spikes and similar
influences, can destroy a device. Even if devices have protective circuits (e.g. protective diodes) on their inputs, the following guidelines for their handling should nevertheless be observed.
Identification
The packing of ESS devices is provided with the following label by the manufacturer.
k
Scope
The guidelines apply to the storage, transport, testing, and processing of all kinds of
ICs, as well as equipment and soldered circuit boards that contain such components.
16
General Information
Handling of Devices
1.
ICs must be left in their containers until they are processed.
2.
ICs may only be handled at specially equipped work stations. These stations must
have work surfaces covered with a conductive material of the order of 106 to 10 9
ohms to ground.
3.
With humidity of > 50% pure cotton clothing is sufficient. In the case of chargeable
synthetic fibers, the clothing should be worn close-fitting. A wrist strap grounded
across a resistor of 5 x 104 to 105 ohms must be worn snugly on the skin.
4.
If conductive floors, R = 5 x 10 4 to 10 7 ohms are provided, further protection can
be achieved by using so-called MOS chairs and shoes with a conductive sole (R
= 10 5 to 10 7 ohms).
5.
All transport containers for ESS devices and assembled circuit boards must first
be brought to the same potential by being placed on the work surface or touched
by the operator before the individual devices may be handled. The potential equalization should be accross a resistor of 106 to 108 ohms.
6.
When loading machines and production devices, it should be noted that the devices
come out of the transport magazine charged and can be damaged if they touch
metal, e.g. machine parts.
Example 1)
conductive (black) tubes.
The devices may be destroyed in the tube by charged persons or
come out of the tube charged if this is emptied by a charged person.
Conductive tubes may only be handled at ESS work stations (highresistance work-station and person grounded).
Example 2)
anti-static (transparent) tubes.
The devices cannot be destroyed by charged persons in the tube
(there may be a rare exception in the case of custom ICs with
unprotected gate pins). The devices can be endangered as in 1) when
the tube is emptied if the tube, especially at low humidity, is no longer
sufficiently anti-static after a long period of storage (> 1 year).
In both cases, damage can be avoided by discharging the devices across a grounded adapter of high-resistance material (= 10' to 10' ohms) between the tube and
the machine.
The use of metal tubes - especially of anodized aluminum because of the danger of low-resistance device discharge.
is not advisable
Storage
ESS devices should only be stored in identified locations provided for the purpose.
During storage, the devices should remain in the packing in which they are supplied.
The storage temperature should not exceed 60°C.
Transport
ESS devices in approved packing tubes should only be transported in suitable containers of conductive or longterm anti-static-treated plastic or possibly unvarnished wood.
Containers of high-charging plastic or very low-resistance materials are in like manner
unsuitable.
17
I
General Information
Transfer cars and their rollers should exhibit adequate electrical resistance (R < 106
ohms). Sliding contacts and grounding chains will not reliably eliminate charges.
Incoming Inspection
At incoming inspection, the above guidelines should be observed. Otherwise any right
to refund or replacement if devices fail inspection may be lost.
Material and Mounting
1. The drive belts of machines used for the processing of the devices (e.g. bending
and cutting machines, conveyor belts), should be treated with anti-static spray (e.g.
anti-static spray 100 from Kontaktchemie).
2.
If ESS devices have to. be soldered or desoldered manually, solder.ing irons with
thyristor control should not be used. Siemens EMI-suppression capacitors of the
type B 81711-B31 ... -B36 are recommended to protect against line transients.
3.
Circuit boards fitted and soldered with ESS devices are always to be considered
electrostatically sensitive.
Electrical Tests
1.
2.
The devices should be processed with observation of these guidelines. Before
assembled and soldered circuit boards are tested, remove any shorting rings.
Test receptacles must not have voltage applied when individual devices or assembled circuit boards are inserted or withdrawn, unless specifications state otherwise. Ensure that the testers do not produce any voltage spikes, either when being
turned on and off in normal operation or if the power fuse blows or other fuses
respond.
3.
Signal voltages may only be applied to the inputs of ICs when or after the supply
voltage is turned on. They must be disconnected before or when the supply voltage
is turned off.
4.
Observe any notes and instructions in the respective data books.
Packing Of Assembled PC Boards or Flatpack Units
The packing material should exhibit low volume conductivity: 105 ohm-cm <
ohm-cm.
p
< 10 10
In most cases - especially with humidity of > 40% - this requirement is fulfilled by
simple corrugated board. Better protection is obtained with bags of conductive
polyethylene foam (e.g. RCAS 1200 from Richmond of Redlands, CAl.
One should always ensure that boards cannot touch.
In SPecial cases, it may be necessary to provide protection against strong electric fields,
such as. can be generated by conveyor belts for example. For this purpose, a sheath
of aluminum foil is recommended, although direct contact betWeen the foil and the
PCB must be avoided. Cardboard boxes with an aluminum-foil lining, such as those
used for shipping Siemens devices, are available from Laber of Munich.
18
General Information
Ultrasonic Cleaning Of ICs
The following recommendation applies to plastic packages. For cavity packages (metal
and also ceramic), separate regulations have to be observed.
Freon and isopropyl alcohol (trade name: propanol) can be used as solvents. These
solvents can also be used for plastic packages because they do not eat into the plastic
material.
An ultrasonic bath in double halfwave operation is advisable because of the low component stress.
The ultrasonic limits are as follows:
sound frequency
f > 40 KHz
exposure
t < 2 min.
alternating sound pressure p < 0.29 bar
N < W/cm 211iter
sound power
1.4
Electrical And Environmental Ratings
Maximum Ratings
The maximum ratings are absolute limits. The IC may be destroyed if only a single
one of these values is exceeded.
Electrical Characteristics
The electrical characteristics include the guaranteed tolerances of the values main·
tained by an IC for the specified operating range.
The typical characteristics are mean values that can be expected on the basis of the
production. Unless otherwise specified, the typical characteristics apply to Tamb = 25°C
and the given supply voltage.
Operating Data
The functions stated in the circuit description are fulfilled within the range of the operating
.
data.
19
I
General Information
1.5
Mechanical Dimensions
Package Dimensions
Piggyback
>-------51.3-1---------1
""
.
'1
.
40
21
tt+-
+++
20
Plastic plug-in package 20 A 8 DIN 41866
8 pins. DIP
1.5 max
0.45. 0.11
~
~
~bx
Approx. weight 0.7 9
20
General Information
Plastic plug-in package 20 A 14 DIN 41866
14 pins, DIP
': :
8
0,4 max
17.6-03-----
Approx. weight 1.1 g
Plastic power package,
with cooling fin and 9 pins, SIP (TDA 4601)
L
3.2-0,2
Approx. weight 1.9 g
21
General Information
Plastic plug-in package 20 A 16 DIN 41866,
16 pins, DIP
20L o.3
8 0.4max
Approx. weight 1.2 g
Ceramic package, 16 pins, DIC
-"Ed:
~762'06
o 25- 0 '
16
to]
1
8
-20.5-01---·
Approx. weight 1.4 g
22
General Information
Plastic plug-in package 20 A 18 DIN 41866,
18 pins, DIP
~
~.-J,~
7.6'01
r-
..s'
-~
--.110.45'0.1 2.54
1.5mnx
--1
'"
.1.2
18
10
16
[::~"'"
22.7.03
Approx. weight 1.3 g
Ceramic package, 18 pins, DIC
2.54
1.5max
18
10
~
1
9
1
23·0.1
Approx. weight 2.7 g
23
General Information
Plastic plug-in package 20 A 20 DIN 41866,
20 pins, DIP
0.4S'O.1
20
2.54
l.SmQ)(
~1.2
11
10
1
0.4mox
f--~~-2S. 3-03 ~~--If---
Approx. weight 1.5 g
Plastic plug-in package 20 D 22 DIN 41866,
22 pins, DIP
_g~j 10.16'°2
I
m'"CE4~
~-1 ~
~
!
I I
-1
0.4S'O.1 1,Smax
2.S4
22
0.2S'01.
=1,2
11_ 9-02 jl
12
C10.16'1.2:j
11
t--~~-27.8_ 0.3 -----<~
Approx. weight 2.1 g
24
0.4max
General Information
Plastic plug-in package 20 B 24 DIN 41866,
24 pins, DIP
~.!:-.lx
1:=15.24,0.2
=:1
~O
J0l010Jtl f"
f
2.54
1.5mnx
0.45'0.1
24
.2
13
r-----31.9_0.4
12 0.4mnx
----,,14--
Approx. weight 2.5 g
Ceramic package; 24 pins, DIC
~~'
~~ ~ AL
~
0.25. 0.1
=1.3
1.5r<
2.540.45. 0.1
15.24,0.6
13
24
)
0
1
--.
12
31.5 _1S --
----
Approx. weight 3 g
25
General Information
Plastic plug-in package 20 8 28 DIN 41866,
28 pins, DIP
f-----
14 0.4 max
35. 9_0.---___oo-1\---
Approx. weight 3 g
Plastic plug-in package 208 40 DIN 41866,
40 pins, DIP
Approx. weight 5.9 g
26
General Information
Ceramic package, 40 pins, DIC (SAB 8086)
20
1
51,5.1,1
Approx. weight 6.8 g
Ceramic package, 40 pins, DIC
Approx. weight 5.9 g
27
General Information
Ceramic package, 68 pins, LCC
Pin No.1 Mark
MICROPACK, 64 connections
I--------i-r-
16 ..
O.6max
7.
l
7
I
O.03min
I
---L--
r-
I
I
I
~8B
~491
_~~~~~-114 --~
28
f+-----------------------if--~-~-~-~4-~+:~-~4-~-+-~-1
..
S28·2
3±0
11~
CJl
C)
-6'
"C
:i"
.,CD
::r
Packagmg rail
t- ~.::..=-~E~~S
±O.S
C
::s
o·
=-(t== ..-
'J'-
__ ~ _ _ _-
-
CD
IJI
/
ANTISTATIC -
c'
C"
3'
CD
2)
/\
®=f~
CD
--
::s
-
-::Et±:!-~ £I:1-±=i~
[2£J
3BO±O.1
~~14'
13
X~(=130)
-
b
IJI
Il
is:
rCo>
0
0
c(')
~
10
cross-secllOn, rotated by 90°
"IT
~...,.S~j-;-
_
_~
~
"!
t
1) Labeling: Height: 4mm, color: blue
2) ESD - symbol according to SN68410
seam 0,03 max_
Hard PVC, transparent,
impact resistant
,?-'1-- ~'---J::J
6·0,2
15
I\)
CD
......
.Rl
......
S
CD
~
!!!.
-o·
:;
.,
0
3
DI
~
w
(J)
o
Packaging rail
,
'''''~''''''"
f+--------.---------------it--~-+-~-~-e.:;:;+:r-r~-~-+-r-l
..
+1.
$~1
3
±0"
/
::J
<0
!!!.
~
0-
lD
C
'"o·
'"
::J
~. ~_=_-=-~~E!:S_ _ _A~~~l~_=__=_ ___ ~---~~~
~
_ _ _ =-----., t---±O,5
CD
::l
CD
ID
::J
3)
/~
:::T
3'
5282
.::Et±3'~ -EI3-:E-!'
@]
380+0,1
j.---~14'
13
-
x[i£] (=130)
~
IL
:s:
r
w
0
0
'0
"!l
.l>o
.m
.CD
cross-section, rotated by 90 0
1)
Labeling: Height: 4mm, color: red
2) measurement
3) ESD -
symbol according to SN68410
.~
....
....
so
.m
I\)
.8
seam 0,03 max.
Hard PVC, transparent,
impact resistant
I..
15+0,3
)t~
G
G')
-0'
"S!.
~
::l
.....
0
~
-o·
3
III
::l
!J)
:::T
~
Packa9m9 rad
I
I
I
I
I
I
'~
I
I
I
I
I
I
ri----------------~~---~-+-1-i--r-~-t-i-~~r-+-i-i--r-1
,..-I.-.,
•
u-rJ==t!
CD
:::J
CD
...,.
IC
!!!.
:i"
ct
tT
11)
C
•
•
3±O.1
1)
3'
11)
::J
rn
o·
2)
::J
rn
s:
rC>
1~14X
0
0
13
x
c
@] c'= 156)
0
I\)
.~
I\)
59
cross-section, rotated by 90°
~
.9
o
~
,S
f?SSSSSi
I
_
hSSSSS\:,\
~l~
N
~~
-,."
20±O,2
~
7
.I.~
o
1) Labeling: Height: 4mm, color; blue
2) ESD - symbol according to SN68410
seam 0,03 max,
+
~
o
Hard PVC, transparent,
impact resistant
Q
-6'
-c
-o·
:::J
0
...,.
3
III
:::J
w
'"
~
.Packag,ng m,'
'III'I'~IIIII
I
I
[i---------------------~-+-i-~--r-~-t-i-~:r-+-i-~--rl ~l
.
..
528_2
3±Ol
1)
2)
(J)
::T
CD
2tT
-
CD
0
3'
CD
::I
en
o·
::I
en
485±01
:s:
"'I@] 1-
r
~14'
'"
Ol
0
0
13 X@](=156)
'§
"1J
I\)
-~
I\)
cross-section, rotated by 90 0
~ssssS! I
13 t021
ISSSSS\:\--+l
.P?
"'"
.s
A
I
1) Labeling: Height: 4mm, color: red
2) ESD - symbol according to SN68410
ft
o
0
+
u
o
"
~
§.
seam 0,03 max.
dJ
Hard. PVC, transparent,
impact resistant
G)
-5'
"'C
:i"
co
::s
CD
....
~
::s
0
....
3
-o·
QI
::s
General Information
1.6
Quality And Reliability
Quality Assurance System
The high quality and reliability of integrated circuits from Siemens is the result of a
carefully arranged production which is systematically checked and controlled at each
production stage.
The procedures are subject to a quality assurance system; full details are given in the
brochure "Siemens Ouality Assurance System-Integrated Circuits" (SOS-IC).
Figure 1 shows the most important stages of the "SOS-IC". A quality assurance (OA)
department which is independent of production and development, is responsible for
the selected control measures, acceptance procedures, and information feedback loops.
This department has state-of-the-art test and measuring equipment at its disposal, works
according to approved methods of statistical quality control, and is provided with facilities
for accelerated life and environmental tests used for both qualification and routine
monitoring tests.
Figure 1
Qualification stoges
Incoming inspectIOn
parts
lJIat.riats
In - proctss control
ph)'SICo.I para.rllriers
ctilllensions
IIlsuc.I inspection
1 st lot
ClC.c.¢IlfK.I
tlst
In ~ prouss centro!
bending
dlMnStor'ls
2 nd tot acceptunn tlSt
3 rd lot O,(tlptnnc.t test
ConfomMlnc.1 Inspection
{llttributHI
The iatest methods and equipment for preparation and analysis are employed to achieve
a continuous development of quality and reliability.
33
General Information
Quality Specifications
The delivery quality of integrated circuits is specified as follows:
1.
2.
Maximum ratings and tolerance limits of the characteristics.
Sampling inspection, AQL values (acceptable quality level)
Inspection by attributes 1) is based on the identical sampling inspection plans DIN
40080, (or) MIL-STD-105, inspection level II, normal inspection, or lEG 410.
A delivery lot for which the defect percentage for a certain characteristic is equal
or less than the specified AOL value, will most probably (more than 95%) be
accepted in the appropriate sampling inspection.
The average defect percentage of delivered products lies, in general, clearly below
the AOL value and is known as the average outgoing quality (AOO). Only the number
of defective units is evaluated in the sampling inspection.
3.
Defects
A defect exists if a component characteristic does not correspond to the specifications in the data sheet.
The defects are classified as total defects, defects in the electrical features, and
defects in the mechanical features. Unless otherwise agreed upon., the AOL values
in section 5 apply to the various defect types.
4.
Classification of defects
Total defect:
Defects in the
electrical features:
Defects in the
mechanical features:
. open contact or short circuit within a specified
temperature range
- no marking, or wrong type and/or direction of
marking
- wrong marking of pin 1
- mixed with wrong versions/types
- components not aligned within one rail/tube
- broken package and/or pins
- exceeding electrical specification limits
-
defects on the package surface
type marking hard to identify
bent pins
wrong dimensions
1) Inspection for a characteristic for which only two mutually exclusive properties are specified
(good/bad).
34
General Information
5.
AQL table
Defect type
Total defect (mechanical and electrical)
Defect in the electrical features
Defect in the mechanical features
AQL values
MOS IC
Bipolar IC
0.1
0.25
0.4
0.4
0.4
0.4
AQL value 1.5 applies to switching times
6.
Incoming inspection
The tests carries out by the manufacturer are intended to render expensive incoming
inspection by the user unnecessary. If the user, however, wants to carry out such
inspections, we recommend the use of a sampling inspection plan as described
in section 7. The test method used must be agreed upon between customer and
supplier.
The following information is required to adjust a possible claim:
test circuit, sample size, number of defective items found, sample of evidence,
packing list.
35
I
General Information
7.
Sampling inspection plan for normal inspection
in accordance with DIN 40080 or MIL-Std-105 D, inspection level II, or IEC410
AQL value
Sample
size
Lot size
0.0651 0.10
0.15
0.25
0.40
0.65
1.0
1.5
2.5
4.0
6.5
AR AR AR AR AR AR AR AR AR AR AR
2 to
8
2
9 to
15
3
16 to
25
5
26 to
50
8
51 to
90
13
~
o1
Jl
o1
1i 1
o
1
+-
91 to
150
o1
1 2
2 3
1 2
2 3
3 4
1 2
2 3
3 4
5 6
1 2
2 3
3 4
5 6
7 8
1 2
2 3
3 4
5 6
7 8 1011
1 2
2 3
3 4
5 6
7 8 1011 1415
1 2
2 3
3 4
5 6
7 8 10 11 1415 2122
1 2
2 3
3 4
5 6
7 8 10 11 1415 2122
7 8 1011 1415 2122
20
~
151 to
280
o1
32
~
281 to
500
50
501 to 1200
80
1201 to 3200
125
o1
o1
o1
1
3201 to 10000
200
10001 to 35000
315
35001-150000
500
150001-500000
500001 and more
A
=
B
=
o1
i
o1
1 2
1
i
t
i
II'
o1
I
r1
l
1 2
2 3
3 4
5 6
800
t
1 2
2 3
3 4
5 6
7 8 10 11 1415 2122
1250
2 3
3 4
5 6
7 8 10 11 1415 2122
t
r1
Acceptance number, i.e. the maximum number of defective sample units up
to which the lot is accepted.
Rejection number, i.e. the number of defective sample units which must at
least be found for the lot to be rejected.
Additional requirement
As the combination Acceptance 0 and Rejection 1 has a low degree of significance,
the next larger size should be sampled.
36
General Information
Quality Conformance
Each integrated circuit is subject to a final test at the end of the production process.
Those tests are carried out by computer-controlled, automatic test systems because
hundred of thousands of operating conditions as well as many static and dynamic
parameters are to be considered. Moreover, the test systems are extremely reliable
and reproducible. The quality assurance department carries out a final check in the
form of a lot-by-Iot sampling inspection to additionally ensure this minimum failure rate
as well as the acceptable quality level (AOL). Sampling inspection is performed in accordance with the inspection plans of DIN 40080, as well as of the identical MIL-STD-105
or IEC 410.
The table below shows the results of such sampling inspections performed with hundred of thousands of ICs in 1984. Those results correspond to the average outgoing
quality (AOO), and are specified as defectives per million.
Total
defects
AOO
(dpm)
Sum of
electrical
defects
AOO
(dpm)
Sum of
mechanical
defects
AOO
(dpm)
SSI/MSI
5 1000 gate functions
60
300
500
LSIIVLSI
~ 1000 gate functions
400
800
600
Due to the low failure rate, the user generally need not perform an incoming inspection.
Reliability
Measures tal(en during development
The reliability of ICs is already considerably influenced at the development stage.
Siemens has, therefore, fixed certain design standards for the development of circuit
and layout, specifying e.g. minimum width and spacing of conductive layers on a chip,
dimensions and electrical parameters of protective circuits for electrostatic charge, etc.
An examination with the aid of carefully arranged programs operated on large-scale
computers, guarantees the immediate identification and elimination of unintentional
offenses against those design standards.
In-process control during production
The manufacturing of integrated circuits comprises several hundred production steps.
As each step is to be executed with utmost accuracy, the in-process control is of outstanding importance. Some processes require more than a hundred different test
measures. The tests have been arranged such that the individual process steps can
be reproduced continuously.
The decreasing failure rates reflect the never ending effort in this direction; in the course
of years they have been reduced considerably despite an immense rise in the IC's
complexity.
37
I
General Information
Figure 2
Random failure rate
Fit
Complexity
Gate/chip
5000
5000
500
500
50
50
1970
1975
1980
1983
Figure 2 shows the general course of the failure rate for digital MOS ICs in fit for the
years 1970 to 1983. The increasing complexity as regards gate functions/chip is also
specified.
Reliability monitoring
The general course of the IC's failure rate versus time is shown by a so-called "bathtub"
curve (figure 3). The failure rate has its peak during the first few operating hOllrs (early
failure period). After the early failure period has decayed, the "constant" failure rate
period starts during which the failures may occur at an approximately uniform rate.
This period ends with a repeated rise of the curve during the wear-out failure period.
For IC's, however, the latter period lies usually far beyond the service life specified
for the individual equipment.
38
General Information
Figure 3
Failure rate
I
X
Early
failure
period
Constant failure rate period
,/
\Wear -out
failure
period
Operating hours-
Reliability tests for ICs are usually destructive examinations. They are, therefore, carried out with samples. Most failure mechanisms can be accelerated by means of higher
temperatures. Due to the temperature dependence of the failure mechanisms, it is possible to simulate a future operational behavior within a short time by applying high
temperatures; this is called life test.
The acceleration factor B for the life test can be obtained from the Arrhenius Equation
B = exp [(
-¥- )( ~~-~12)]
where T2 is the temperature at which the life test is performed, T1 is the assumed
operating temperature, and k is the Boltzmann constant.
Important for factor B is the activation energy EA' It lies between 0.3 and 1.3 eV and
differs considerably for individual failure mechanisms.
For all Siemens ICs, the reliability data from life tests is converted to an operating
temperature of Tamb = 40°C, assuming an average activation energy of 0.4 eV. The
acceleration factor for life tests is thus 24, compared with operational behavior. This
method considers also failure mechanisms with low activation energy, i.e. which are
only slightly accelerated by the temperature effect.
Various reliability tests are periodically performed with IC types that are representative
of a certain production line-this is described in the brochure "SOS-IC". Such tests are
e.g. humidity test at 85°C and 85% relative humidity, pressure cooker test, as well
as life tests up to 1 000 hours and more. Test results are available in the form of summary reports.
39
General Information
1.7
Thermal Coefficients
Plastic Packages
Typel
Mounting Area
Chip Size
R'hSA
Pins
mm x mm
mm2
°K/W
OIL
8
14
16
18
20
22
24
28
40
2.0
2.0
3.5
2.0
3.5
3.5
3.7
2.8
3.5
3.8
4.0
4.5
4.2
6.2
4.2
6.0
6.0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3.0
3.6 N
4.2 N
3.6
5.0
6.5
10.2
3.6
5.5
5.5 N
7.8
5.5
5.2
7.2
5.2
7.5
7.5
108
4
415
4/7/15
79/77
72167/62
77/75
71165/59
8
25
63
60
4/7
4/7/15
7/17
70/65
66160/55
65/60
4/7/12
4/5
18
7/21
7/18
56
56/47
55/52
49/45/44
51/48
45/41/40
43/39/38
7/30140
7/18
7/30140
7/30/40
N = new package, S = special package according to package catalogue
Ceramic multi-layer packages
Typel
Mounting Area
Chip Size
R'hSA
Pins
mm x mm
mm 2
°K/W
OIC 16
18
24
40
3.9
5.6
3.9
6.5
7.8
9.0
x
x
x
x
x
x
6.1 S
10 N
5.6 S
6.5 S
7.8 S
9.0 N
4/7/15
78171/65
30
55
4/7/13
75168/63
54/46
49/42/37
45/38/36
7/30
7/30/46
7/30/46
N = new package, S = special package according to package catalogue.
Plastic power package
Typel
Mounting Area
Chip Size
Pins
mm x mm
mm2
SIL
40
9
2.5 x 3.4
3.4 x 4.3
4.7
7
R'hSA
R'hSC
°K/W
°K/W
60
60
2.2
2.2
N = new package, S = special package according to package catalogue.
Summary of Types
Summary of Types
Siemens Part No.
2.1
Function
Page
Component Selection Guide
Microcontroller and Microprocessor Components
SAB 8031-P
8-bit single chip microcomputer without internal
ROM, 12 MHz, '
" " " " " " " "
" " "
SAB 8031-10-P
8-bit single chip microcomputer without internal
ROM, 10 MHz, , . , , , . , , , , , , , , , , , , , , ' , , , . , ,
SAB 8031-T40/85-P
8-bit single chip microcomputer without internal
ROM, 10 MHz, -40°C to +85°C temp. range"."
SAB 8031-T 40/11 O-P 8-bit single chip microcomputer without internal
ROM, 8 MHz, -40°C to + 110°C
temp. range, , , , , , . , , , . , , , , , , , , , , , , , , , , , , , , ,
SAB 8031A-P
8-bit single chip microcomputer without internal
ROM, 12 MHz, , , , , , , , , , , , , , , . , , , , , ,
,,.,,,"
SAB 8031A-15-P
8-bit single chip microcomputer without internal
ROM, 15 MHz. , , ' , ' , ' , , , ' , , , ' , , , , , , ' , , ' , ' , ' , "
SAB 8031A-T40/85-P 8-bit single chip microcomputer without internal
ROM, 12 MHz, -40°C to + 85°C temp, range, , , . , "
SAB 8031A-T40/110-P 8-bit single chip microcomputer without internal
ROM, 10 MHz, -40°C to +110oC temp, range"""
SAB 8032A-P
8-bit single chip microcomputer without internal
ROM, 12 MHz, (enhanced SAB 8031A-P) , , , , , , , , , , ,
SAB 8051-P
8-bit single chip microcomputer with internal mask
programmed ROM, 12 MHz, , , , , , , , , , , , , , , , , , , , "
SAB 8051-10-P
8-bit single chip microcomputer with internal mask
programmed ROM, 10 MHz, , ' , ' , ' , '
SAB 8051-T40/85-P
8-bit single chip microcomputer with internal mask
programmed ROM, 10 MHz, -40°C to + 85°C
temp, range, . , ' , ' . ' ......... , .. , ... , . , .. ' . ' . ,.
SAB 8051-T-40/110-P a-bit single chip microcomputer with internal mask
programmed ROM, 8 MHz, -40°C to + 11 DoC
lemp. range .. , ,
, . , ... , . , ......... , . , .... , ,.
SAB 8051A-P
8-bit single chip microcomputer with internal mask
programmed ROM, 12 MHz .. ' ..... ' .. , ..........
SAB 8051A-15-P
8-bit single chip microcomputer with internal mask
programmed ROM, 15 MHz .. , .. , . , . . . . . . . . . . . .
SAB 8051A-T40/85-P 8-bit single chip microcomputer with internal mask
programmed ROM, 12 MHz, -40°C to +85°C
temp. range ... ' , , .. , , , , .. , .. , , . , , . , . , .... , ... ,
SAB 8051A-T40/110-P 8-bit single chip microcomputer with internal mask
programmed ROM, 10 MHz, -40°C to + 110°C
, , .. , . , .............. , , ..
temp, range. , . , . .
SAB 8052A-P
8-bit single chip microcomputer with internal mask
programmed ROM, 12 MHz, (enhanced SAB 8051A-P)
SAB 8086-P
16-bit microprocessor, 5 MHz
SAB 8086-C
16-bit microprocessor, 5 MHz. , , . , .. , ... , . , , . , , ..
49
49 ,
65
65
81
81
99
99
117
49
49
65
65
81
81
99
99
117
161
161
43
I
Summary of Types
Siemens Part No.
Function
Page
16·bit microprocessor, 10 MHz .................... 161
16·bit microprocessor, 10 MHz .................... 161
16·bit microprocessor, 8 MHz ..................... 161
16-bit microprocessor, 8 MHz ..................... 161
16-bit microprocessor with 8-bit data bus
interface, 5 MHz ................................ 199
16-bit microprocessor, with 8-bit data bus
SAS 8088-2-P
interface, 8 MHz ................................ 199
SAS 80186-C
High integration 16-bit microprocessor, 8 MHz ....... 229
High integration 16-bit microprocessor with 8-bit
SAS 80188·C
data bus interface, 8 MHz ........................ 231
High performance 16·bit microprocessor, 8 MHz, LCC. 233
SAS 80286-C
High performance 16·bit microprocessor, 6 MHz, LCC. 233
SAS 80286-6-C
High performance 16·bit microprocessor, 8 MHz, PGA.233
SAS 80286·CG
High performance 16·bit microprocessor, 6 MHz, PGA. 233
SAS 80286·6·CG
SAS 80C482-P
8-bit single chip CMOS microcomputer with internal
mask programmed ROM, 3 MHz (80C48 with special
features). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 133
Peripheral and Support Components
SAS 1791-02-P
Floppy disk controller with inverted data bus ........ 299
SAS 1793-02-P
Floppy disk controller with non-inverted data bus ... , 299
SAS 1795-02-P
Floppy disk controller with inverted data bus and
side select output . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 299
SAS 1797-02-P
Floppy disk controller with non-inverted data bus
and side select output ..... . . . . . . . . . . . . . . . . . . . .. 299
SAS 2793A-02-P
Floppy disk controller with non-inve1ted data bus,
built in data separator and write precompensation logic .................................... 325
SAS 2797A-02-P
Floppy disk controller with non-inverted data bus,
side select output, and built in data separator and
write precompensation logic ....................... 325
SAS 8237A-P
8-bit high performance programmable DMA
controller, 3 MHz ............................... 353
SAS 8237 A-5-P
8-bit high performance programmable DMA
controller, 5 MHz ............................... 353
SAS 8256A-P
Programmable multi-function component with
timers/counters, an interrupt controller, baud rate
generator, serial and parallel ports ................. 369
SAS 8256A-2-P
Programmable multi-function component with
timers/counters, an interrupt controller, baud rate,
generator, serial and parallel ports (faster
version of the SAS 8256A) ........................ 369
SAS 8259A
Programmable interrupt controller, 5 MHz ........... 395
SAS 8259A-2-P
Programmable interrupt controller, 8 MHz ........... 395
SAS 8275-P
Programmable CRT controller, 2 MHz .............. 405
SAS 8275-2-P
Programmable CRT controller, 3 MHz .............. 405
SAS
SAS
SAS
SAS
SAS
44
8086-1-P
8086-1-C
8086-2-P
8086-2-C
8088-P
Summary of Types
Siemens Part No.
SAB
SAB
SAB
SAB
8276-P
8282A
8283A
8284B-P
SAB 8284B-1-P
SAB 8286A-P
SAB 8287A-P
SAB 8288A-P
SAB 8289-P
SAB 8289-1-P
SAB 82258-C
SAB 82258-6-C
SAB 82258-CG
SAB 82258-6-CG
SAB 82284-P
SAB 82284-6-P
Function
Page
Small system CRT controller ...................... 433
8-bit non-inverting octal latch ..................... .459
8-bit inverting octal latch ......................... 459
Clock generator and driver for SAB 8086 family
processors, 8 MHz .............................. 465
Clock generator and driver for SAB 8086 family
processors, 10M Hz ............................. 465
8-bit non-inverting octal bus transceiver ............. 479
8-bit inverting octal bus transceiver ................. 479
Bus controller for SAB 8086 family processors ....... 485
Bus arbiter for SAB 8086 family processors, 8 MHz ... 495
Bus arbiter for SAB 8086 family processors, 10 MHz .. 495
Advanced DMA controller for 8 or 16-bit systems,
8 MHz, LCC .................................. 507
Advanced DMA controller for 8 or 16-bit systems,
6 MHz, LCC .................................. 507
Advanced DMA controller for 8 or 16-bit systems,
8 MHz, PGA .................................. 507
Advanced DMA controller for 8 or 16-bit systems,
6 MHz, PGA ...... _........................... 507
Clock generator and driver for SAB 80286 family
processors, 8 MHz .............................. 555
Clock generator and driver for SAB 80286 family
processors, 6 MHz .............................. 555
Bus controller for SAB 8086 family processors ....... 567
Bus controller for SAB 8086 family processors, 6 MHz. 567
Bus arbiter for SAB 80286 family processors ......... 593
Bus arbiter for SAB 80286 family processors, 6 MHz .. 593
Dot rate generator, 50 MHz ....................... 595
Dot rate generator, 80 MHz ....................... 595
SAB 82288·P
SAB 82288-6-P
SAB 82289-P
SAB 82289-6-P
SAB 82731-P
SAB 82731-2-P
Memory Components
SAB 81 C50-P
CMOS 256 x 8-bit static RAM with multiplex bus
interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS 256 x 8-bit static RAM with multiplex bus
SAB 81C51-P
interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS 256 x 8-bit static RAM with multiplex bus
SAB 81C52-P
interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dynamic RAM; 65, 536 xl, access time 120 ns . . . ..
HYB 4164-P1
Dynamic RAM; 65, 536 xl, access time 150 ns . . . ..
HYB 4164-P2
Dynamic RAM; 65, 536 xl, access time 200 ns . . . ..
HYB 4164-P3
Dynamic RAM; 262,144 x 1, access time 120 ns ....
HYB 41256-P12
Dynamic RAM; 262, 144 xl, access time 150 ns . . ..
HYB 41256-P15
Dynamic RAM; 262,144 x 1, access time 200 ns ....
HYB 41256-P20
Dynamic RAM; 262, 144 x 1 with nibble mode,
HYB 41257-P12
access time 120 ns . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
Dynamic RAM; 262, 144 x 1 with nibble mode,
HYB 41257-P15
access time 150 ns ........................... "
625
625
631
639
639
639
653
653
653
669
669
45
Summary of Types
Page
Siemens Part No.
Function
HYB 41257-P20
Dynamic RAM; 262, 144 x 1 with nibble mode,
access time 200 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 669
Telecom Components
PEB 2030-C
46
Frame alignment circuit for synchronization of
2.048 MHz PCM systems ......................... 689
PEB 2040-C
Memory time switch for 2.048 MHz and 8.192
MHz PCM systems .............................. 697
PEB 2050-C
Peripheral board controller, line card controller
for 1.536 MHz, 1.544 MHz, 2.048 MHz, 3.072 MHz,
and 4.096 MHz PCM systems ..................... 713
PEB 2051-C
Peripheral board controller, variation of PEB 2050 .... 733
PEB 2060-P
Programmable digital signal processing CODECFILTER, CMOS ................................. 751
PSB 6520-P
Tone ringer, replaces mechanical bell in telephone .... 769
PSB 6521-P
Tone ringer, replaces mechanical bell in telephone .... 781
PSB 6620-P
Ring detector, senses ringing signal in telephone ..... 795
PSB 8590-P
Dual-tone multi-frequency generator/dialer ........... 801
PSB 8591-P
Dual-tone multi-frequency generator/dialer ........... 819
PSB 8592-P
Dual-tone multi-frequency generator/dialer, CMOS .... 843
SAB 80C482-P
8-bit single chip CMOS microcomputer with internal
mask programmed ROM, 3 MHz (80C48 with special
features). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 133
SAB 81 C50-P
CMOS 256 X 8-bit static RAM with multiplex bus
interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
SAB 81C51-P
CMOS 256 x 8-bit static RAM with multiplex bus
interface ....................................... 625
SAB 81C52-P
CMOS 256 x 8-bit static RAM with multiplex bus
interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 631
PSB 7510
Numeric LCD controller, 64-pin micropack, CMOS .... 853
Data Conversion Components
SDA 5200N-C
6-bit, 100 MHz, monolithic AID flash converter ....... 875
SDA 5200S-C
6-bit, 100 MHz, monolithic AID flash converter ....... 881
SDA 6020-C
6-bit, 50 MHz, monolithic A/D flash converter ...... " 887
SDA 8005-C
8-bit high speed monolithic D/A flash converter. . . . . .. 893
SDA 8010-C
8-bit, 100 MHz, monolithic AID flash converter
905
Switched Mode Power Supply Components
TDA 4600-2
Control IC for switched mode power supplies,
9 pin SIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 919
TDA 4600-2D-P
Control IC for switched mode power supplies ........ 919
TDA 4601
Control IC for switched mode power supplies,
9 pin SIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 929
TDA 4601 D-P
Control IC for switched mode power supplies ........ 929
TDA 4700-C
Control IC for switched mode power supplies ........ 943
TDA 4700A-P
Control IC for switched mode power supplies ........ 943
TDA 4714A-P
Control IC for switched mode power supplies ........ 957
TDA 4716A-P
Control IC for switched mode power supplies ........ 969
TDA 4718-C
Control IC for switched mode power supplies ...... " 981
TDA 4718A-P
Control IC for switched mode power supplies ........ 981
Microcontroller and Microprocessor Components
SAB 8031/8051
8-Bit Single Chip Microcomputer
SAB 8031/8031-10 Control Oriented CPU With RAM and 1/0
SAB 8051/8051-10 An SAB 8031 With Factory Mask-Programmable ROM
.4Kx8ROM
.128 x 8 RAM
• Four 8-Bit Ports, 32 1/0 Lines
• Two 16-Bit TimerlEvent Counters
• High-Performance Full-Duplex
Serial Channel
• External Memory Expandable to 128K
• Compatible with SAB 808018085
Peripherals
• SAB 8031/8051 12 MHz Operation
Pin Configuration
• SAB 8031-10/8051-1010 MHz Operation
• Boolean Processor
• SAB 8048 Architecture Enhanced with:
Non-Paged Jumps
Direct Addressing
Four 8-Register Banks
Stack Depth Up to 128-Bytes
Multiply, Divide, Subtract, Compare
• Most Instructions Execute in 1 lis
• 4 ~s Multiply and Divide
I
logic Symbol
S'6
~"
.,,,
The SAB 8031/8051 is a stand-alone, high-performance single-chip computer fabri~ated in +5V advanced N-channel, silicon gate Siemens MYMOS
technology and packaged in a 40-pin DIP. It provides
the hardware features, architectural enhancements and new instructions that are necessary to
make it a powerful and cost effective controller for
applications requiring up to 64K bytes of program
memory andlor up to 64K bytes of data storage.
The SAB 8051 contains a non-volatile 4K x 8 readonly program memory; a volatile 128 x 8 readlwrite
data memory; 32 1/0 lines; two 16-bit timerl
counters; a five-source, two-priority-Ievel, nested
interrupt structure; a serial 1/0 port for either multiprocessor communications, 1/0 expansion, or full
duplex UART; and on-chip oscillator and clock
circuits. The SAB 8031 is identical, exceptthat it lacks
the program memory. For systems that require extra
capability, the SAB 8051 can be expanded using
standard TIL compatible memories and the byte
oriented SAB 8080 and SAB 8085 peripherals.
The SAB 8051 microcomputer, like the SAB 8048,
is efficient both as a controller and as an arithmetic
processor. The SAB 8051 has extensive facilities for
binary and BCD arithmetic and excels in bit-handling
capabilities. Efficient use of program memory
results from an instruction set consisting of 44%
one-byte. 41 % two-byte, and 15% three-byte
instructions. With a 12 MHz crystal, 58% of the
instructions execute in 1.0 ~s, 40% in 2.0 ~IS and
multiply and divide require only 4.0 ~IS. Among the
many instructions added to the standard SAB 8048
instruction set are multiply, divide, subtract and
compare.
AG 11/83
49
SAB 8031/8051
Pin Definitions and Functions
Symbol
Number
Input (I)
Output (0)
P1.0-P1.7
1-8
1/0
Port 1 is an 8-bit quasi-bidirectional 1/0 port. It is used for
the low-order address byte during program verification.
Port 1 can sinklsource three LS TTL loads.
RSTIVPD
9
I
A high level on this pin resets the SAB 8051. A small
internal pulldown resistor permits power-on reset using
only a capacitor connected to vce. If VPD is held within its
spec while VCC drops below spec, VPD will provide
standby power to the RAM. When VPD is low, the RAM's
current is drawn from VCC.
P3.0-P3.7
10-17
1/0
Port 3 is an 8-bit quasi-bidirectional 1/0 port. It also
rontains the interrupt, timer, serial port and RD and WR
pins that are used by various options. The output latch
corresponding to a secondary function must be programmed to a one (1) for that function to operate. Port 3
can sinklsource three LS TIL loads. The secondary
functions are assigned to the pins of Port 3, as follows:
- RXD/data (P3.0). Serial port's receiver data input
(asynchronous) or datil inputloutput (synchronous).
- TXD/ciock (P3.1). Serial port's transmitter data output
(asynchronous) or clock output (synchronous).
- INTO (P3.2). Interrupt 0 input or gate control input for
counter O.
- INTl (P3.3). Interrupt 1 input or gate control input for
counter 1.
- TO (P3.4). Input to counter O.
- Tl (P3.5). Input to counter 1.
- WR (P3.6). The write control signal latches the data
byte from Port 0 into the External Data Memory.
- RD (P3.7). The read control signal enables External
Data Memory to Port O.
XTAL1
XTAL2
19
18
I
XTAL 1 Input to the oscillator's high gain amplifier.
Required when a crystal is used. Connect to VSS when
external source is used on XTAL2.
XTAL2 Output from the oscillator's amplifier. Input to the
internal timing circuitry. A crystal or external source can
be used.
P2.0-P2.7
21-28
1/0
Port 2 is an 8-bit quasi-bidirectional 1/0 port. It also emits
the high-order address byte when accessing external
memory. It is used for the high-order address and the
control signals during program verification. Port 2 can
sinklsource three LS TIL loads.
PSEN
29
0
The Program Store Enable output is a control signal that
enables the external Program Memory to the bus during
external fetch operations. It is activated every six oscillator
periods, except during external data memory accesses.
Remains high during internal program execution.
ALE
30
0
Provides Address Latch Enable output used for latching
the address into external memory during normal
operation. It is activated every six oscillator periods
except during an external data memory access .
._----_.
50
Functions
.---
SAB 8031/8051
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (01
EA
31
I
When held at a TIL high level, the SAB 8051 executes
instructions from the internal ROM when the PC is
less than 4096. When held at a TIL low level, the SAB 8051
fetches all instructions from external Program Memory.
P0.0--PO.7
39-32
I/O
Port 0 is an B-bit open drain bidirectional I/O port. It is
also the mUltiplexed low-order address and data bus
when using external memory. It is used for data output
during program verification. Port 0 can sink/source
eight LS TIL loads.
VCC
40
+5V power supply during operation and program
verification.
VSS
20
Circuit ground potential.
Functions
Block Diagram
Frequency
Reference
I
I
I
I
I
I
-t---~--------------- ----------- -~--~--&
Timing
I
I
I
I
I
128 Bytes
Data Memory
Two 16-Blt
Timer/Event
Counters
t
t
64k-Byte Bus
Expansion
Control
I
I
L
=:>
Programmable 1/0
Interrupts
- --------Interrupts
-----
Control
-- -- -Parallel Ports
Adress Data Bus
and I/O Pins
I
I
I
I
Programmable
serial port
. full duplex UART
• synchronous
shifter
--+---Serial
IN
I
I
I
I
I
~
I
I
I
I
I
)
I
I
8051
CPU
I
l
I
4096 Bytes
Program
Memory
(8051 only)
Oscillator
I
Counters
I
I
I
I
I
I
~
Serial
OUT
51
SAB 8031/8051
Instruction Set Description
IDescription
Mnemonic
IByte ICycle
Arithmetic operations
ADD
A,Rn
Add register to Accumulator
ADD
A, direct
ADD
A,@Ri
ADD
A,#data
ADDC
A,Rn
1
1
Add direct byte to Accumulator
2
1
Add indirect RAM to Accumulator
1
1
Add immediate data to Accumulator
2
1
Add register to Accumulator with Carry flag
1
1
ADDC
A,direct
Add direct byte to A with Carry flag
2
1
ADDC
A,@Ri
Add indirect RAM to A with Carry flag
1
1
ADDC
A,#data
Add immediate data to A with Carry flag
2
1
SUBB
A,Rn
Subtract register from A with Borrow
1
1
SUBB
A,direct
Subtract direct byte from A with Borrow
2
SUBB
A,@Ri
Subtract indirect RAM from A w/Borrow
1
SUBB
A,#data
Subtract immediate data from A wi Borrow
INC
A
Increment Accumulator
INC
Rn
Increment register
1
1
INC
direct
Increment direct byte
2
1
INC
@Ri
Increment indirect RAM
1
DEC
A
Decrement Accumulator
1
DEC
Rn
Decrement register
1
DEC
direct
Decrement direct byte
2
.------
-------- ----------------
--
1
i-----------
1
..
_--
1
2
._-.- .__._- --_ .._.
1
1
- - - - e-------
1
1----1
-- - - - 1
._- r----1
DEC
@Ri
Decrement indirect RAM
1
1
INC
DPTR
Increment Data Pointer
1
2
MUL
AB
MUltiply A & B
1
4
DIV
AB
Divide A & B
1
4
DA
A
Decimal Adjust Accumulator
1
1
ANL
A,Rn
AND register to Accumulator
1
1
ANL
A,direct
AND direct byte to Accumulator
2
1
ANL
A,@Ri
AND indirect RAM to Accumulator
1
1
ANL
A,#data
AND immediate data to Accumulator
2
1
ANL
direct,A
AND Accumulator to direct byte
2
1
Logical operations
52
-
- -'---
i----- - - - -
SAB 8031/8051
Instruction Set Description (continued)
Mnenlonic
ANL
direct,#data
Description
Byte
Cycle
AND immediate data to direct byte
3
2
- - ----
ORL
A,Rn
OR register to Accumulator
1
1
ORL
A,direct
OR direct byte to Accumulator
2
1
ORL
A,@Ri
OR indirect RAM to Accumulator
1
1
ORL
A, itdata
OR immediate data to Accumulator
2
1
ORL
direct,A
OR Accumulator to direct byte
2
1
ORL
direct,#data
OR immediate data to direct byte
3
2
XRL
A,Rn
Exclusive-OR register to Accumulator
1
1
XRL
A,direct
Exclusive-OR direct byte to Accumulator
2
1
XRL
A,@Ri
Exclusive-OR indirect RAM to A
1
1
XRL
A,*data
Exclusive-OR immediate data to A
2
1
XRL
directA
Exclusive-OR Accumulator to direct byte
2
1
-
XRL
direct,*data
Exclusive-OR immediate data to direct
3
2
CLR
A
Clear Accumulator
1
1
CPL
A
Complement Accumulator
1
1
flL
A
Rotate Accumulator Left
1
RLC
A
Rotate A Left through the Carry flag
1
1
RR
A
Rotate Accumulator Right
1
1
RRC
A
Rotate A Right through Carry flag
1
1
SWAP
A
Swap nibbles within the Accumulator
1
1
MOV
A,Rn
Move register to Accumulator
1
1
MOV
A,direct
Move direct byte to Accumulator
2
1
MOV
A,@Ri
Move indirect RAM to Accumulator
1
1
MOV
A,*data
Move immediate data to Accumulator
2
1
MOV
RnA
Move Accumulator to register
1
1
MOV
Rn,direct
Move direct byte to register
2
2
MOV
Rn,iFdata
Move immediate data to register
2
1
MOV
direct,A
Move Accumulator to direct byte
2
1
MOV
direct,Rn
Move register to direct byte
2
2
MOV
direct,direct
Move direct byte to direct
3
2
---------_.
--------------_._-------_._-_.
----.---
-r--
- - --.
-
1
Data transfer
53
SAB 8031/8051
Instruction Set Description (continued)
Mnemonic
Description
Byte
Cycle
MOV
direct,@Ri
Move indirect RAM to direct byte
2
2
MOV
direct,*data
Move immediate data to direct byte
3
2
MOV
@Ri.A
Move Accumulator to indirect RAM
1
1
MOV
@Ri,direct
Move direct byte to indirect RAM
2
2
MOV
@Ri,*data
Move immediate data to indirect RAM
2
1
MOV
DPTR,*data 16
Load Data Pointer with a 16-bit constant
3
2
MOVC
A.@A+DPTR
Move Code byte relative to DPTR to A
1
2
Data transfer (cont.)
MOVC
A.@A+PC
Move Code byte relative to PC to A
1
2
MOVX
A,@Ri
Move External RAM IS-bit addr) to A
1
2
MOVX
A,@DPTR
Move External RAM 116-bit addr) to A
1
2
MOVX
@Ri.A
Move A to External RAM 18-bit addr)
1
2
MOVX
@DPTR.A
Move A to External RAM I 16-bit sddr)
1
2
PUSH
direct
Push direct byte onto stack
2
2
POP
direct
Pop direct byte from stack
2
2
XCH
A.Rn
Exchange register with Accumulator
1
1
XCH
A,direct
Exchange direct byte with Accumulator
2
1
XCH
A,@Ri
Exchange indirect RAM with A
1
1
XCHD
A.@Ri
Exchange low-order Digit indo RAM w/A
1
1
C
Clear Carry flag
1
1
CLR
bit
Clear direct bit
2
1
SETB
C
Set Carry flag
1
1
SETB
bit
Set direct Bit
2
1
CPL
C
Complement Carry flag
1
1
CPL
bit
Complement direct bit
2
1
ANL
C,bit
AND direct bit to Carry flag
2
2
ANL
C,/bit
AND complement of direct bit to Carry
2
2
ORL
C,bit
OR direct bit to Carry flag
2
2
ORL
C.fbit
OR complement of direct bit to Carry
2
2
MOV
C,bit
Move direct bit to Carry flag
2
1
MOV
bit,C
Move Carry flag to direct bit
2
2
Boolean variable manipulation
CLR
54
SAB 8031/8051
Instruction Set Description (continued)
IDescription
Mnemonic
IByte ICycle
Program and machine control
ACALL
addr 11
LCALL
addr16
RET
RETI
AJMP
addr 11
Absolute Subroutine Call
2
2
Long Subroutine Call
3
2
Return from subroutine
1
2
Return from interrupt
1
2
Absolute Jump
2
2
LJMP
addr16
Long Jump
3
2
SJMP
rei
Short Jump Irelative addr)
2
2
JMP
@A+DPTR
Jump indirect relative to the DPTR
1
2
JZ
rei
Jump if Accumulator is Zero
2
2
JNZ
rei
Jump if Accumulator is Not Zero
2
2
JC
rei
Jump if Carry flag is set
2
2
JNC
rei
Jump if Carry flag is not set
2
2
JB
bit,rel'
Jump if direct Bit set
3
2
JNB
bit,rel
Jump if direct Bit Not set
3
2
JBC
bit, rei
Jump if direct Bit is set & Clear bit
3
2
CJNE
A.direct,rel
Compare direct to A & Jump if Not Equal
3
2
CJNE
A.#data,rel
Camp. immed. to A & Jump if Not Equal
3
2
CJNE
Rn,#data,rel
Camp. immed. to reg. & Jump if Not Equal
3
2
CJNE
@Ri,#data,rel
Comp.immed. to indo & Jump if Not Equal
3
2
DJNZ
Rn,rel
Decrement register & Jump if Not Zero
2
2
DJNZ
direct,rel
Decrement direct & Jump if Not Zero
3
2
No operation
1
1
NOP
Notes on data addressing modes:
Rn
- Working register RD-R7
direct
- 128 internal RAM locations, any 1/0 port,
control or status register
@Ri
·-Indirect internal RAM location addressed
by register RD or R1
#data
- 8-bit constant included in instruction
#data 16 -16-bitconstantincludedasbytes2&30f
instruction
bit
- 128 software flags, any 1/0 pin, control
or status bit
All mnemonics copyrighted
@
Notes on program addressing modes:
addr 16 - Destination address for LCALL & LJMP
may be anywhere within the 64-Kilobyte
program memory address space.
addr 11 - Destination address for ACALL & AJMP
will be within the same 2-Kilobyte page
of program memory as the first byte of
the following instruction.
rei
- SJMP and all conditional jumps include
an 8-bit offset byte. Range is + 127/-128
bytes relative to first byte olthe followi ng
instruction.
Intel Corporation 1979
55
SAB 8031/8051
Instruction Opcodes in Hexadecimal Order
Hex
Code
Number
of Bytes
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
1
2
3
1
1
2
1
1
1
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
56
i
1
1
1
1
1
1
3
:'>
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
Mnemonic Operands
Hex
Code
Number
of Bytes
NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
JBC
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
JB
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JNB
ACALL
RETI
RLC
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
codeaddr
codeaddr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr code addr
codeaddr
codeaddr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr code addr
codeaddr
A
A,*data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bit addr, code addr
codeaddr
A
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
Mnemonic Operands
AD DC
AD DC
ADDC
ADDC
ADDC
AD DC
ADDC
AD DC
AD DC
ADDC
ADDC
AD DC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
XRL
XRL
A,*data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R7
A,R7
codeaddr
codeaddr
data addr,A
data addr, *data
A,*data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,*data
A,*data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
code addr
data addr,A
data addr, *data
A,*data
A,data addr
A,@RO
A,@R1
SAB 8031/8051
Instruction Opcodes in Hexadecimal Order (continued)
Hex
Code
Number
of Bytes
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
1
1
1
Mnemonic Operands
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
.IMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
DIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
C,bitaddr
@A+DPTR
A,ifdata
data addr, ifdata
@RO,ifdata
@R1,ifdata
RO,ifdata
R1,ifdata
R2,ifdata
R3,ifdata
R4,ifdata
R5,ifdata
R6,ifdata
R7,ifdata
codeaddr
codeaddr
C,bitaddr
A,@A+PC
AS
data addr,data addr
data addr,@RO
data addr,@R1
data addr, RO
data addr, R1
data addr, R2
data addr, R3
data addr, R4
data addr, R5
data addr, R6
data addr, R7
DPTR,ifdata
code addr
bit addr,C
A,@A+DPTR
A,ifdata
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
Hex
Code
Number
of Bytes
9C
90
9E
9F
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
1
1
1
1
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
1
1
1
1
Mnemonic Operands
SUBB
SUBB
SUBB
SUBB
ORL
AJMP
MOV
INC
MUL
reserved
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
A,R4
A,R5
A,R6
A,R7
C,fbit addr
code addr
C,bit addr
DPTR
AB
@RO,data addr
@Rl,dataaddr
RO,data addr
R1,data addr
R2,data addr
R3,data addr
R4,data addr
R5,data addr
R6,data addr
R7,data addr
C,fbit addr
codeaddr
bit addr
C
A,ifdata,code addr
A,data addr,codeaddr
@RO,ifdata,codeaddr
@Rl,*data,codeaddr
RO, *data, code addr
Rl,*data,code addr
R2,ifdata,code addr
R3,ifdata,code addr
R4,*data,code addr
R5,ifdata,code addr
R6,*data,code addr
R7,*data,code addr
data addr
code addr
bitaddr
C
A
A,data addr
A,@RO
A,@R1
A,RO
A,Rl
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
57
SAB 8031/8051
Instruction Opcodes in Hexadecimal Order (continued)
Hex
Code
Number
of Bytes
Mnemonic Operands
DO
01
02
03
D4
D5
D6
D7
D8
09
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
EO
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
POP
ACALL
SETB
SETB
DA
DJNZ
XCHO
XCHD
DJNZ
OJNZ
DJNZ
OJNZ
OJNZ
DJNZ
DJNZ
OJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
FD
FE
FF
58
data addr
codeaddr
bitaddr
C
A
data addr,code addr
A,@RO
A,@R1
RO,code addr
R1,codeaddr
R2,code addr
R3,code addr
R4,code addr
R5,code addr
R6,code addr
R7,code addr
A,@DPTR
codeaddr
A,@RO
A,@R1
A
A,dataaddr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
@DPTR,A
codeaddr
@RO,A
@R1,A
A
data addr,A
@RO,A
@Rl,A
RO,A
Rl,A
R2,A
R3,A
R4,A
R5,A
R6,A
R1,A
SAB 803118051
Absolute Maximum Ratings 1)
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (VSS)
Power Dissipation
oto 70'C
-65 to + 150'C
-0.5to + 7 V
2W
D.C. Characteristics
TA
= Oto 70'C;
vcc = 5V ± 5%; VSS
= OV
Symbol
Parameter
Limit Values
VIL
Input Low Voltage
VIH
Input High Voltage
2.0
(Except RSTIVPD and XTAL2)
VCC+0.5
VIHl
Input High Voltage to
RST IVPD for Reset, XTAL2
2.5
-
XTAL 1 to VSS
VPD
Power Down Voltage
To RSTIVPD
4.5
5.5
VCC = OV
VOL
Output Low Voltage
Ports 1,2,3
-
0.45
VOLl
Output Low Voltage
Port 0, ALE, IPSEN
Min.
VOH
Output High Voltage
Ports 1,2,3
Typ.
-0.5
Unit
Test Condition
Max.
0.8
-
V
10L
= 1.6 mA
10L
= 3.2 mA
10H = -60
~tA
-
2.4
10H = -400
~tA
VOH1
Output High Voltage
Port 0, ALE, IPSEN
IlL
Logical 0 Input Current
Ports 1,2,3
-800
ItA
IIL2
Logical 0 Input Current
XTAL2
-2.0
mA
XTAL 1 = VSS
VIL = 0.45 V
IIH1
Input High Current to
RST IVPD for Reset
500
ItA
VIN
III
Input Leakage Current
To Port O,lEA
VIL
~
0.45 V
= VCC-1.5V
-
±10
ICC
Power Supply Current
125
160
IPD
Power Down Current
10
20
CIO
Capacitance of 1/0 Buffer
-
10
0< VIN < VCC
mA
-
pF
fe
= 1 MHz
1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
59
SAB 8031/8051
A.C. Characteristics for SAB 8031/8051
TA O'Cto 70'C; VCC = 5V ±5%; VSS = OV
(CL for Port 0, ALE and PSEN Outputs = 100 pF; CL for All Other Outputs = 80 pF)
Program Memory Characteristics
Symbol
Limit Values
Parameter
Variable Clock
1/TCLCL = 1.2 MHz to 12 MHz
12 MHz Clock
Min
Max
Min
Max
TLHLL
ALE Pulse Width
TAVLL
Address Setup to ALE
53
TLLAX1
Address Hold After ALE
48
TLLlV
ALE to Valid Instr In
-
TLLPL
ALE to PSEN
58
TPLPH
PSEN Pulse Width
215
TPLIV
PSEN to Valid Instr In
-
150
-
3TCLCL-100
TPXIX
Input Instr Hold After PSEN
0
-
0
-
TPXIZ*)
Input Instr Float After PSEN
-
63
-
TPXAV*)
Address Valid After PSEN
75
--
TCLCL-8
TAVIV
Address to Valid Instr In
-
302
-
5TCLCL-115
TAZPL
Address Float to PSEN
0
-
0
-
----
127
Unit
2TCLCL·40
-
-
TCLCL-30
TCLCL-35
233
-
-
4TCLCL-100
TCLCL-25
ns
-
3TCLCL-35
TCLCL-20
--1---------
---
.._'---._-
External Data Memory Characteristics
Symbol
Parameter
Limit Values
12 MHz Clock
Min
Max
Unit
Va'riable Clock
1/TCLCL = 1.2 MHz to 12 MHz
Min
Max
-
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TLLAX2
Address Hold After ALE
132
TRLDV
RD to Valid Data In
-
250
-
5TCLCL-165
TRHDX
Data Hold After RD
0
-
0
-
-
8TCLCL-150
400
6TCLCL-100
-
6TCLCL-100
-
2TCLCL-35
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data In
2TCLCL-70
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
200
300
3TCLCL-50
3TCLCL+50
TAVWL
Address to WR or RD
203
-
4TCLCL-130
-
TWHLH
WR or RD High to ALE High
43
123
TCLCL-40
TCLCL+40
TDVWX
Data Valid to WR Transition
33
97
-
f------
517
Data Setup Before WR
433
TWHOX
Data Hold After WR
33
TRLAZ
Address Float After RD
-
ns
9TCLCL-165
585
TOVWH
-- ---
TCLCL-50
-
7TCLCL-150
-
TCLCL-50
0
-
0
*) Interfacing the SAB 8051 to devices with float times up to 75ns is permissible. This limited bus contention
will not caused any damage to Port 0 drivers.
60
SAB 8031/8051
A.C. Characteristics for SAB 8031-10/8051-10
TA O"C to 70 C C; vcc = 5V ±5%; VSS = OV
(CL for Port 0, ALE and PSEN Outputs = 100 pF; CL for All Other Outputs
= 80 pF)
Program Memory Characteristics
Symbol
Parameter
Limit Values
Variable Clock
l/TCLCL = 1,2 MHz to 10 MHz
10 MHz Clock
Min
Max
Unit
Min
Max
TLHLL
ALE Pulse Width
160
TAVLL
Add ress Setu p to ALE
70
TLLAXl
Address Hold After ALE
65
TLLlV
ALE to Valid Instr In
-
TLLPL
ALE to PSEN
75
TPLPH
PSEN Pulse Width
265
TPLIV
PSEN to Valid Instr In
-
200
-
3TCLCL-l00
TPXIX
Input Instr Hold After PSEN
0
-
0
-
TPXIZ' )
Input Instr Float After PSEN
-
80
-
TCLCL-20
TPXAV*)
Address Valid After PSEN
92
-
TCLCL-8
-
TAVIV
Address to Valid Instr In
-
385
-
5TCLCL·115
TAZPL
Address Float to PSEN
0
-
0
-
2TCLCL-40
-
TCLCL-30
-
TCLCL-35
300
-
-
4TCLCL-l00
TCLCL-25
3TCLCL-35
-
ns
External Data Memory Characteristics
Symbol
Parameter
Unit
Limit Values
Variable Clock
lITCLCL = 1.2 MHz to 10 MHz
10 MHz Clock
Min
Max
Min
Max
TRLRH
RD Pulse Width
TWLWH
VVR Pulse Width
TLLAX2
Address Hold After ALE
165
TRLDV
RD to Valid Data In
-
335
-
5TCLCL-165
TRHDX
Data Hold After RD
0
-
0
-
-
650
-
8TCLCL-150
500
6TCLCL-l00
-
6TCLCL-l00
-
2TCLCL-35
2TCLCL-70
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data In
130
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
250
350
3TCLCL-50
3TCLCL+50
TAVWL
Address to WR or RD
270
-
4TCLCL-130
-
TWHLH
WR or RD High to ALE High
60
140
TCLCL-40
TCLCL+40
TDVWX
Data Valid to WR Transition
50
TOVWH
Data Setup Before WR
550
TWHOX
Data Hold After WR
50
TRLAZ
Address Float After RD
-
ns
9TCLCL-165
735
TCLCL-50
-
7TCLCL-150
-
TCLCL-50
0
-
0
*) Interfacing the SAB 8051 to devices with floal times up to 92ns is permissible. This limited bus contention
will not caused any damage to Port 0 drivers.
61
SAB 8031/8051
External Clock Drive XTAL2
Symbol
Limit Values
Parameter
Unit
Variable Clock
Freq = 1.2 MHzto 12 MHz (8031/8051)
Freq = 1.2 MHz to 10 MHz (8031-10/8051-10)
Min
Max
TCLCL
Oscillator Period 8031/8051
83.3
Oscillator Period 8031-10/8051-10 100
833.3
TCHCX
High Time
TCLCL-TCLCX
TCLCX
Low Time
TCLCH
Rise Time
TCHCL
Fall Time
20
TCLCL-TCHCX
ns
20
-
External Clock Cycle
08
08
- - TClCX-
1 - - - - - - - T C L C L - - - - - -..-I
A.C, Testing Input, Output, Float Waveforms
2.4
045
2.4
045
X::
~::
Test POints
Float
::X
::~
24
0.45
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Timing measurements are made at 2.0V for a logic "1" and 0.8V for a logic "0".
For timing purposes, the float state is defined as the point at which a PO pin sinks 3.2mA or sources
400 ~A at the voltage test levels.
62
SAB 8031/8051
Waveforms
Program Memory Read Cycle
I-~~~-~~~~~~-
TCY
---~----
TLLIV ~-
TLHLL-
-TLLPL
ALE
-~TPLPH--
-
LLAX11.J.rTPLIV -
--TAVLL -
-TAZPL
A7 - AD
PORT 0
---TAVIV
PORT 2
I
ADDRESS
OR SFR-P2
~~~
ADDRESS A 15 - A B
Data Memory Read Cycle
~
__~I-~--- TLLDV ~-
TWHLH-
ALE
--TLLWL
-I-~~~-
TRLRH
-~~--~
- - --TAVWL--TRLDV--
Port 0
Port 2
ADDRESS
-OR SFR-P2
ADDRESS A15-AB OR SFR-P2
63
SAB 8031/8051
Data Memory Write Cycle
TWHLH ALE
--TLLWL-I------·TWLWH--- - - - WR
TAVWL
I
--TDVWX
TClVWH
-TWHQX
DATA OUT
Port 0
ADDRESS A15 - A8 OR SFR-P2
Port 2
Recommended Oscillator Circuits
C
:t--_-.._--'1c.;9 XTAL 1
, - - - j .
I
l --i.,
I
1
+ SV
~'Jk
~1.2-12 MHz
~-
18
~il----*----"'-lXTAL2
~I
~---~XTAL2
7404
74LS04
CdO pH 10pF
Crystal Os[illator Mode
64
~XTAL1
Driving from .External Source
SAB 8031/8051
8-Bit Single Chip Microcomputer
Extended Temperature Range: -40 to + 85°C
-40 to +110 C
SAB 8051-P-T40/85
Mask Programmable ROM
SAB 8051-P-T40/110
C
o4K x 8 ROM
SAB 8031-P-T40/85
SAB 8031-P-T40/110
External ROM
• Boolean Processor
• SAB 8048 Architecture Enhanced with:
.128 x 8 RAM
• Four S-Bit Ports, 32 I/O Lines
o Two 16-Bit Timer/Event Counters
• Non-Paged Jumps
• High-Performance Full-Duplex
Serial Channel
• Four 8-Register Banks
• Stack Depth Up to 128-Bytes
• Direct Addressing
• External Memory Expandable to 12SK
• Multiply, Divide, Subtract, Compare
• Compatible with SAB 8080/S085
Peripherals
• Single +5V Power Supply with ±10%
Voltage Margins
Logic Symbol
Pin Configuration
VSSYU
RSTlVPO
."
The SAB 8031/8051 for the two extended
temperature ranges (industrial temperature range:
-40 to T85 C, Automative temperature range:
--40to +110C) isfullycompatiblewiththestandard
SAB 8031/8051 with respect to architecture,
instruction set, and software portability.
The SAB 8031/8051 is a stand-alone, high-performance single-chip computer fabricated in +5V advanced N-channel, silicon gate Siemens MYMOS
technology and packaged in a 40-pin DIP.
The SAB 8031 is identical to the SAB 8051, except
that it lacks the program memory.
The SAB 8051 microcomputer, like the SAB 8048,
is efficient both as a controller and as an arithmetic
processor. The SAB 8051 has extensive facilities for
binary and BCD arithmetic and excels in bit-handling
capabilities. Among the many instructions added
to the standard SAB 8048 instruction set are
multiply, divide, subtract and compare.
AG 2184
65
SAB 8031/8051 Ext. Temp.
Pin Description
Symbol
Number
Input (I)
Output (0)
P1.0-P1.7
1-8
1/0
Port 1 is an 8-bit quasi-bidirectional 1/0 port. Ii is used for
the low-order address byte during program verification.
RSTIVPD
9
I
A high level on this pin resets the SAB 8051. A small
internal pulldown resistor permits power-on reset using
only a capacitor connected to vee. IfVPD is held within its
spec while vee drops below spec, VPD will provide
standby power to the RAM. When VPD is low, the RAM's
current is drawn from vee.
P3.0-P3.7
10-17
1/0
Port 3 is an 8-bit quasi-bidirectional 1/0 port. It also
contains the interrupt, timer, serial port and RD and WR
pins that are used by various options. The output latch
corresponding to a secondary function must be programmed to a one (1) for that function to operate.
The secondary functions are assigned to the pins of Port 3,
as follows:
- RXD/data (P3.0). Serial port's receiver data input
(asynchronous) or data input/output (synchronous).
- TXD/clock (P3.1). Serial port's transmitter data output
(asynchronous) or clock output (synchronous).
- INTO (P3.2). Interrupt 0 input or gate control input for
counter O.
- INT1 (P3.3). Interrupt 1 input or gate control input for
counter 1.
- TO (P3.4). Input to counter O.
- T1 (p3.5). Input to counter 1.
- WR (P3.6). The write control signal latches the data
byte from Port 0 into the External Data Memory.
- RD (P3.7). The read control signal enables External
Data Memory to Port O.
XTAL1
XTAL2
19
18
I
XTAL 1 Input to the oscillator's high gain amplifier.
Required when a crystal is used. Connect to VSS when
external source is used on XTAL2.
XTAL2 Output from the oscillator's amplifier. Input to the
internal timing circuitry. A crystal or external source can
be used.
P2.0-P2.7
21-28
1/0
Port 2 is an 8-bit quasi-bidirectional 1/0 port. It also emits
the high-order address byte when accessing external
memory. It is used for the high-order address and the
control signals during program verification.
PSEN
29
0
The Program Store Enable output is a control signal that
enables the external Program Memory to the bus during
external fetch operations. It is activated every six oscillator
periods, except during external data memory accesses.
Remains high during internal program execution.
ALE
30
0
Provides Address Latch Enable output used for latching
the address into external memory during normal
operation. It is activated every six oscillator periods
except during an external data memory access.
66
Function
SAB 8031/8051 Ext. Temp.
Symbol
Number
Input (II
Output 101
EA
31
I
When held at a high level, the SAB 8051 executes
instructions from the internal ROM when the PC is
less than 4096. When held at a low level, the SAB 8051
fetches all instructions from external Program Memory.
PO.O- PO.7
39-32
1/0
Port 0 is an 8-bit open drain bidirectional 1/0 port. It is
also the multiplexed low-order address and data bus
when using external memory. It is used for data output
during program verification.
VCC
40
+ 5 V power supply during operation and program
verification.
VSS
20
Circuit ground potential.
Function
Block Diagram
Frequency
Reference
r
I
I
I
- t---~---------------------------l--~--Oscillator
I
I
&
Timing
I
I
I
I
I
I
Counters
1
4096 Bytes
Program
Memory
180510nlyi
Two 16-Blt
Timer I Event
Counters
128 Bytes
Data Memory
1
f
8051
CPU
~
I
I
I
64k-Byte Bus
Ex panslon
Control
I
I
I
I
I
L
:)
Programmable 110
Programmable
serial port
• full duplex UART
• shnchronous
sliter
Interrupts
-
---------
-----
'v
Interrupts
Control
--
--
--
V
Parallel Ports
Adress Data Bus
and 110 Pins
----
---- -
Serial
IN
Serial
OUT
67
SAB 8031/8051 Ext.Temp.
Instruction Set Description
I Description
Mnemonic
I Byte I Cycle
Arithmetic operations
ADD
A,Rn
ADD
ADD
Add register to Accumulator
1
1
A, direct
Add direct byte to Accumulator
2
1
A,@Ri
Add indirect RAM to Accumulator
1
1
ADD
A,#data
Add immediate data to Accumulator
2
1
ADDC
A,Rn
Add register to Accumulator with Carry flag
1
1
AD DC
A,direct
Add direct byte to A with Carry flag
2
1
ADDC
A,@Ri
Add indirect RAM to A with Carry flag
1
1
ADDC
A,#data
Add immediate data to A with Carry flag
2
1
SUBB
A,Rn
Subtract register from A with Borrow
1
1
SUBB
A,direct
Subtract direct byte from A with Borrow
2
1
SUBB
A,@Ri
Subtract indirect RAM from A w/Borrow
1
1
SUBB
A,#data
Subtract immediate data from A w/Borrow
2
1
INC
A
Increment Accumulator
1
1
INC
Rn
Increment register
1
1
INC
direct
Increment direct byte
2
1
INC
@Ri
Increment indirect RAM
1
1
DEC
A
Decrement Accumulator
1
1
DEC
Rn
Decrement register
1
1
DEC
direct
Decrement direct byte
2
1
DEC
@Ri
Decrement indirect RAM
1
1
INC
DPTR
Increment Data Pointer
1
2
MUL
AB
Multiply A & B
1
4
DIV
AB
Divide A & B
1
4
DA
A
Decimal Adjust Accumulator
1
1
ANL
A,Rn
AND register to Accumulator
1
1
ANL
A;direct
AND direct byte to Accumulator
2
1
ANL
A,@Ri
AND indirect RAM to Accumulator
1
1
ANL
A,#data
AND immediate data to Accumulator
2
1
ANL
direct,A
AND Accumulator to direct byte
2
1
- ..
Logical operations
68
SAB 8031/8051 Ext. Temp.
Mnemonic
Description
Byte
Cycle
ANL
direct, jedata
AND immediate data to direct byte
3
2
ORL
A,Rn
OR register to Accumulator
1
1
ORL
A,direct
OR direct byte to Accumul3tor
2
1
ORL
A,@Ri
OR indirect RAM to Accumulator
1
1
ORL
A,4rdata
OR immediate data to Accumulator
2
1
ORL
direct,A
OR Accumulator to direct byte
2
1
ORL
direct,#data
OR immediate data to direct byte
3
2
XRL
A,Rn
Exclusive-OR register to Accumulator
1
1
XRL
A,direct
Exclusive-OR direct byte to Accumulator
2
1
XRL
A,(a:Ri
Exclusive-OR indirect RAM to A
1
1
XRL
A,#data
Exclusive-OR immediate data to A
2
1
XRL
direct,A
Exclusive-OR Accumulator to direct byte
2
1
XRL
direct,#data
Exclusive-OR immediate data to direct
3
2
CLR
A
Clear Accumulator
1
1
CPL
A
Complement Accumulator
1
1
RL
A
Rotate Accumulator Left
1
1
RLC
A
Rotate A Left through the Carry flag
1
1
RR
A
Rotate Accumulator Right
1
1
RRC
A
Rotate A Right through Carry flag
1
1
SWAP
A
Swap nibbles within the Accumulator
1
1
MOV
A,Rn
Move register to Accumulator
1
1
Data transfer
MOV
A,direct
Move direct byte to Accumulator
2
1
MOV
A,@Ri
Move indirect RAM to Accumulator
1
1
MOV
A,#data
Move immediate data to Accumulator
2
1
MOV
Rn,A
Move Accumulator to register
1
1
MOV
Rn,direct
Move direct byte to register
2
2
MOV
Rn,#data
Move immediate data to register
2
1
MOV
direct,A
Move Accumulator to direct byte
2
1
MOV
direct,Rn
Move register to direct byte
2
2
MOV
direct,direct
Move direct byte to direct
3
2
69
SAB 8031/8051 Ext. Temp.
Mnemonic
Description
Byte
Cycle
direct.@Ri
Move indirect RAM to direct byte
2
2
MOV
direct,*data
Move immediate data to direct byte
3
2
MOV
@Ri,A
Move Accumulator to indirect RAM
1
1
MOV
@Ri,direct
Move direct byte to indirect RAM
2
2
MOV
@Ri,#data
Move immediate data to indirect RAM
2
1
MOV
DPTR,*data 16
Load Data Pointer with a 16-bit constant
3
2
A,@A+DPTR
Move Code byte relative to DPTR to A
1
2
MOVC
A,@A+PC
Move Code byte relative to PC to A
1
2
MOVX
A,@Ri
Move External RAM (S-bit addr) to A
1
2
MOVX
A,@DPTR
Move External RAM 116-bit addr) to A
1
2
MOVX
@Ri,A
Move A to External RAM IS-bit addr)
1
2
MOVX
@DPTR,A
Move A to External RAM 116-bit addr)
1
2
PUSH
direct
Push direct byte onto stack
2
2
MOV
Data transfer Icont.)
MOVC
POP
direct
Pop direct byte from stack
2
2
XCH
A,Rn
Exchange register with Accumulator
1
1
XCH
A,direct
Exchange direct byte with Accumulator
2
1
XCH
A,@Ri
Exchange indirect RAM with A
1
1
XCHD
A,@Ri
Exchange low-order Digit indo RAM w/A
1
1
C
Clear Carry flag
1
1
Boolean variable manipulation
CLR
CLR
bit
Clear direct bit
2
1
SETB
C
Set Carry flag
1
1
SETB
bit
Set direct Bit
2
1
CPL
C
Complement Carry flag
1
1
CPL
bit
Complement direct bit
2
1
ANL
C,bit
AND direct bit to Carry flag
2
2
ANL
C,/bit
AND complement of direct bit to Carry
2
2
ORL
C,bit
OR direct bit to Carry flag
2
2
ORL
C,/bit
OR complement of direct bit to Carry
2
2
MOV
C,bit
Move direct bit to Carry flag
2
1
MOV
bit,C
Move Carry flag to direct bit
2
2
70
SAB 8031/8051 Ext. Temp.
I Byte I Cycle
I Description
Mnemonic
Program and machine control
ACALL
addr 11
LCALL
addr16
RET
RETI
AJMP
addr 11
Absolute Subroutine Call
2
2
Long Subroutine Call
3
2
Return from subroutine
1
2
Return from interrupt
1
2
Absolute Jump
2
2
LJMP
addr 16
Long Jump
3
2
SJMP
rei
Short Jump (relative addr)
2
2
JMP
@A+DPTR
Jump indirect relative to the DPTR
1
2
JZ
rei
Jump if Accumulator is Zero
2
2
JNZ
rei
Jump if Accumulator is Not Zero
2
2
JC
rei
Jump if Carry flag is set
2
2
JNC
rei
Jump if Carry flag not set
2
2
JB
bit,rel
Jump if direct Bit set
3
2
JNB
bit,rel
Jump if direct Bit not set
3
2
JBC
bit,rel
Jump if direct Bit is set & Clear bit
3
2
CJNE
A,direct,rel
Compare direct to A & Jump if Not Equal
3
2
CJNE
A,#data,rel
Camp. immed. to A & Jump if Not Equal
3
2
CJNE
Rn,#data,rel
Compo immed. to reg. & Jump if Not Equal
3
2
CJNE
@Ri,#data,rel
Comp.immed. to indo & Jump if Not Equal
3
2
DJNZ
Rn,rel
Decrement register & Jump if Not Zero
2
2
direct.rel
Decrement direct & Jump if Not Zero
3
2
No operation
1
1
DJNZ
NOP
-
Notes on data addressing modes:
Rn
- Working register RO- R7
direct
- 128 internal RAM locations, any 1/0 port,
control or siatus register
@Ri
- Indirect internal RAM location addressed
by register RO or R1
*data
- 8-bit constant included in instruction
#data 16 - 16-bit constant included as bytes 2 & 3
of instruction
bit
- 128 software flags, any 1/0 pin, control
or status bit
Notes on program addressing modes:
addr 16 - Destination address for LCALL & LJMP
may be anywhere within the 64-Kilobyte
program memory address space.
addr 11 - Destination address for ACALL & AJMP
will be within the same 2-Kilobyte page
of program memory as the first byte of
the following instruction.
rei
-SJMP and all conditional jumps include
an 8-bit offset byte. Range is + 127 1-128
bytes relative to first byte of the following
instruction.
All mnemonics copyrighted 9 Intel Corporation 1979
71
SAB 8031/8051 Ext. Temp.
Instruction Opcodes in Hexadecimal Order
Hex
Code
Number
of Bytes
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1
2
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
72
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
Mnemonic Operands
Hex
Code
Number
of Bytes
NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
JBC
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
JB
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JNB
ACALL
RETI
RLC
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
58
5C
5D
5E
5F
60
61
62
53
64
65
66
67
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
code addr'
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr code addr
code addr
code addr
A
A
data addr
@RO
@R1
RO
Rl
R2
R3
R4
R5
R6
R7
bit addr code addr
code addr
A
A,*data
A,data addr
A.@RO
A.@R1
A,RO
A.R1
A,R2
A,R3
A,R4
A.R5
A,R6
A,R7
bit addr, code addr
code addr
A
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
Mnemonic Operands
AD DC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
AD DC
AD DC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
XRL
XRL
A,*data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R7
A,R7
code addr
code addr
data addr,A
data addr, #data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr, #data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R5
A,R7
code addr
code addr
data addr,A
data addr, #data
A.#data
A,data addr
A,@RO
A,@R1
SAB 8031/8051 Ext. Temp.
Instruction Opcodes in Hexadecimal Order (Continued)
Hex
Code
Number
of Bytes
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
1
1
1
1
1
1
1
1
2
2
2
1
2
77
78
79
7A
7B
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
1
1
1
Mnemonic Operands
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
OIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
C,bit addr
@A+OPTR
A,*data
data addr, "data
@RO,*data
@R1,*data
RO,*data
R1,*data
R2,*data
R3,*data
R4,*data
R5,*data
R6,*data
R7,"data
code addr
code addr
C,bitaddr
A,@A+PC
AB
data
data
data
data
data
data
data
data
data
data
data
addr,data addr
addr,@RO
addr,@R1
addr, RO
addr, R 1
addr, R2
addr, R3
addr,R4
addr, R5
addr,R6
addr, R7
OPTR,"data
code addr
bitaddr,C
A,@A+OPTR
A,*data
A,data addr
A,@RO
A,@R1
A,RP
A,R1
A,R2
A,R3
Hex
Code
Number
of Bytes
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AO
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CO
CE
CF
1
1
1
1
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
1
1
1
1
Mnemonic Operands
SUBB
SUBB
SUBB
SUBB
ORL
AJMP
MOV
INC
MUL
reserved
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
A,R4
A,R5
A,R6
A,R7
C,fbit addr
code addr
C,bitaddr
OPTR
AB
@RO,data addr
@R1,data addr
RO,data addr
R 1,data addr
R2,data addr
R3,data addr
R4,data addr
R5,data addr
R6,data addr
R7,data addr
C,fbit addr
code addr
bit addr
I
C
A,*data,code addr
A,data addr,code addr
@RO,*data,codeaddr
@R1,"data,codeaddr
RO,*data,code addr
R1,"data,code addr
R2,"data,code addr
R3,*data,code addr
R4,*data,code addr
R5,*data,code addr
R6,*data,code addr
R7,*data,code addr
data addr
code addr
bit addr
C
A
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
73
SAB 8031/8051 Ext. Temp.
Instruction Opcodes in Hexadecimal Order (Continued)
Hex
Code
Number
of Bytes
Mnemonic Operands
00
01
02
03
04
05
06
07
OB
09
OA
OB
OC
00
OE
OF
EO
,El
E2
E3
E4
E5
E6
E7
EB
E9
EA
EB
EC
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
POP
ACALL
SETB
SETB
OA
OJNZ
XCHO
XCHO
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
OJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ED
EE
EF
FO
Fl
F2
F3
F4
F5
F6
F7
FB
F9
FA
FB
FC
FO
FE
FF
74
data addr
code addr
bltaddr
C
A
data addr,code addr
A,@RO
A.@R1
RO,code addr
R 1,code addr
R2,code addr
R3,code addr
R4,code addr
R5,code addr
R6,code addr
R7,code addr
A,@OPTR
code addr
A,@RO
A,@Rl
A
A,data addr
A,@RO
A,@Rl
A,fW
A.Rl
A,R2
A.R3
A,R4
A,R5
A,R6
A,R7
@OPTR,A
code addr
@RO,A
@Rl,A
A
data addr,A
@RO,A
@Rl,A
RO,A
Rl,A
R2,A
R3,A
R4,A
R5,A
R6,A
R7,A
SAB 8031/8051 Ext. Temp.
Absolute Maximum Ratings 1)
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (VSS)
Power Dissipation
-40 to + 85°C for T40/85
-40 to + 110°C for T40/110
-65 to + 150'C
-0.5to + 7 V
2W
D.C. Characteristics
vcc = 5V ±10%; VSS = OV;
Symbol
TA
TA
= -40to +
=
85'CforT40/85;
-40to +110'CforT40/110
Parameter
Limit Values
Min.
Typ.
Units
Test Conditions
Max.
VIL
Input Low Voltage
T40/85
T40/110
-0.5
0.8
0.7
VIH
Input High Voltage
except RST IVPD and
XTAL2
T40/85
T40/110
2.0
2.1
VCC+0.5
VIHl
Input High Voltage
to RST IVPD for
Reset, XTAL2
T40/85
T40/110
2.5
2.8
-
XTAL1 toVSS
VPD
Power Down Voltage
To RSTIVPD
4.5
5.5
VCC
Val
Output low Voltage
Ports 1,2,3
-
0.45
Vall
Output Low Voltage
Port 0, ALE, IPSEN
-
V
I
= OV
IOl
= 1.2 mA
IOL
= 2.4 mA
-
VOH
Output High Voltage
Ports 1,2,3
T40/85
T40/110
VOH1
Output High Voltage
Port 0, ALE, IPSEN
T40/85
T40/110
ilL
Logical 0 Input Current
Ports 1,2,3
-800
ftA
IIL2
Logical 0 Input Current
XTAL2
-2.0
mA
IIHl
Input High Current to
RSTIVPD for Reset
500
III
Input Leakage Cu rrent
to Port O.lEA
ICC
Power Su pply Cu rrent
IPD
Power Down Current
20
CIO
Capacitance of I/O Buffer
10
-
2.4
-
= -60 ftA
= -50 f1A
10H = -400 ftA
10H = -360 ftA
VIL = 0.45 V
IOH
IOH
XTAL1 = VSS
VIL = 0.45V
VIN =VCC-l.5V
~A
±10
-
175
0< VIN < VCC
mA
-
pF
fc
= 1 MHz
1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
75
SAB 8031/8051 Ext. Temp.
A.C. Characteristics for T40/85
vcc = 5V ±10%; VSS = OV; TA = -40to +S5"C
(CL for Port 0, ALE and PSEN Outputs = 100 pF; CL for All Other Outputs = SO pF)
Program Memory Characteristics
Symbol
Parameter
Limit Values
10 MHz Clock
Min
TLHLL
Max
Unit
Variable Clock
1/TCLCL = 1.2 MHz to 10 MHz
Min
Max
2TCLCL-40
ALE Pulse Width
160
TAVLL
Address Setup to ALE
70
TLLAX
Address Hold After ALE
65
TLLlV
ALE To Valid Instr In
-
TLLPL
ALE To PSEN
75
TPLPH
PSEN Pulse Width
265
TPLIV
PSEN To Valid Instr In
-
200
-
3TCLCL-100
TPXIX
Input Instr Hold After PSEN
0
-
0
-
-
TCLCL-30
-
TCLCL-35
300
-
TCLCL-25
3TCLCL-35
4TCLCL-100
-
TPXIZ*)
Input Instr Float After PSEN
-
80
-
TCLCL-20
TPXAV*)
Address Valid After PSEN
92
-
TCLCL·8
-
TAVIV
Address To Valid Instr In
-
3S5
-
5TCLCL-115
TAZPL
Address Float To PSEN
0
-
0
-
ns
External Data Memory Characteristics
Symbol
Parameter
Limit Values
10 MHz Clock
Min
Max
Unit
Variable Clock
1/TCLCL = 1.2 MHzto 10 MHz
Min
Max
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TLLAX
Address Hold After ALE
65
TRLDV
RD To Valid Data In
-
335
-
5TCLCL·165
TRHDX
Data Hold After RD
0
-
0
-
-
650
-
8TCLCL-150
TRHDZ
Data Float After RD
TLLDV
ALE To Valid Data In
TAVDV
Address To Valid Data In
TLLWL
ALE To WR or RD
500
6TCLCL-100
-
6TCLCL·100
-
TCLCL-35
130
2TCLCL-70
735
250
350
9TCLCL-165
3TCLCL-50
3TCLCL+50
TAVWL
Address To WR or RD
270
-
4TCLCL·130
-
TWHLH
WR or RD High To ALE High
60
140
TCLCL·40
TCLCL+40
TDVWX
Data Valid To WR Transition
50
TOVWH
Data Setup Before WR
550
TWHOX
Data Hold After WR
50
TRLAZ
Address Float After RD
-
ns
.
TCLCL·50
-
lTCLCL·150
-
TCLCL·50
0
-
0
*) Interfacing the SAB S051 to devices with float times up to 92ns is permissible. This limited bus contention
will not cause any damage to Port 0 drivers.
76
SAB 803118051 Ext. Temp.
A.C. Characteristics for T40/110
vcc = 5V ±10%; VSS = OV; TA = -40to +110°C
(CL for Port 0, ALE and PSEN Outputs = 100 pF; CL for All Other Outputs = 80 pF)
Program Memory Characteristics
Symbol
Parameter
Unit
Limit Values
Variable Clock
l/TCLCL = 1.2 MHz to 8 MHz
8 MHz Clock
Min
Max
Min
Max
TLHLL
ALE Pulse Width
210
TAVLL
Address Setup to ALE
90
TLLAX
Address Hold After ALE
85
TLLlV
ALE To Valid Instr In
-
TLLPL
ALE To PSEN
100
TCLCL-25
TPLPH
PSEN Pulse Width
340
3TCLCL-35
TPLIV
PSEN To Valid Instr In
-
250
-
3TCLCL-125
TPXIX
Input Instr Hold After PSEN
0
-
0
-
TPXIZ*)
Input Instr Float After PSEN
-
105
-
TCLCL-20
TPXAV*)
Address Valid After PSEN
112
-
TCLCL-13
-
TAVIV
Address To Valid Instr In
-
485
-
5TCLCL-140
TAZPL
Address Float To PSEN
0
-
0
-
2TCLCL-40
-
TCLCL-35
-
TCLCL-40
375
-
4TCLCL-125
-
I
ns
External Data Memory Characteristics
Symbol
Parameter
Unit
Limit Values
Variable Clock
l/TCLCL = 1.2 MHz to 8 MHz
8 MHz Clock
Min
Max
Min
Max
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TLLAX
Address Hold After ALE
85
TRLDV
RD To Valid Data In
-
460
-
5TCLCL-165
TRHDX
Data Hold After RD
0
-
0
-
-
850
-
8TCLCL-150
650
6TCLCL-l00
-
6TCLCL-l00
-
TCLCL-40
2TCLCL-70
TRHDZ
Data Float After RD
TLLDV
ALE To Valid Data In
180
TAVDV
Address To Valid Data In
TLLWL
ALE To WR or RD
325
425
3TCLCL-50
3TCLCL+50
TAVWL
Address To WR or RD
370
-
4TCLCL-130
-
TWHLH
WR or RD High To ALE High
85
165
TCLCL-40
TCLCL+40
TDVWX
Data Valid To WR Transition
75
TOVWH
Data Setup Before WR
725
TWHOX
Data Hold After WR
75
TRLAZ
Address Float After RD
-
ns
9TCLCL-165
960
TCLCL-50
-
7TCLCL-150
-
TCLCL-50
0
-
0
*) Interfacing the SAB 8051 to devices with float times upto 112ns is permissible. This limited bus contention
will not cause any damage to Port 0 drivers.
77
SAB 8031/8051 Ext. Temp.
External Clock Drive XTAL2
Symbol
Parameter
Limit Values
Unit
Variable Clock
Freq = 1.2 MHz to 10 MHz (T40/85)
Freq = 1.2 MHzto 8 MHz (T40/110)
TCLCL
Oscillator Period
TCHCX
High Time
TCLCX
Low Time
TCLCH
RiseTime
TCHCL
Fall Time
T40/85
T40/110
Min
Max
100
125
833.3
TCLCL·TCLCX
20
TCLCL·TCHCX
-
ns
20
External Clock Cycle
0.8
TClCX Test Points for T40/110: 0.7V and 2.8V
1 - - - - - - - TClCl------.~1
A.C. Testing Input, Output, Float Waveforms
2.4
0.45
2.4
0.45
X:':
]
Tosl Points
FloQI
::X
~
2.0
2.0
2.4
0.8
0.8
0.45
AC testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Timing measurements are made at 2.0V for a logic "1" and 0.8V for a logic "0".
For timing purposes, the float state is defined as the point at which a PO pin sinks 3.2 mA or sources
400 ~A at the voltage test levels.
78
SAB 8031/8051 Ext. Temp.
Waveforms
Program Memory Read Cycle
1----------------------TCy
TLLIV -
ALE
I
-TAVLL
PORT 0
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A15-AB
ADDRESS A15 - A8
Data Memory Read Cycle
, -_ _-, I-~----- TLLDV - - - - - - I
TWHLH-
ALE
--TLLWL ~I------ TRLRH -----------1
TRHDZ
~-TAVWLTRLDV~
DATA IN
Port 0
Port 2
TRHDX-
ADDRESS
-OR SFR-P2
ADDRESS A15-A8 OR SFR-P2
79
SAB 8031/8051 Ext. Temp.
Data Memory Write Cycle
TWHLH
ALE
--TLLWL-I-'~---~TWLWH-----
TAVWL
TDVWX
• -TWHQ)(
TQVWH
DATA OUT
Port 0
ADDRESS A15-A8 OR SFR-P2
Port 2
Recommended Oscillator Circuits
19 XTAL 1
_-----Il---<>-------'-1.:..j9 XTAL 1
+5V
=
4.7k
1.2-12 MHz
L--~~-~>-------'-18~XTAL2
1 : > - - - - - - - 18 XTAL2
7404
74LS04
C=30pH10pF
Crystal Oscillator Mode
80
Driving from External Source
SAB 8031A18051A
SAB 8031A-15/8051A-15
8-Bit Single Chip Microcomputer
SAB 8031A/8031A-15 Control Oriented CPU with RAM and I/O
SAB 8051A18051A-15 A SAB 8031A with Factory Mask-Programmable ROM
• SAB 8031A/8051A, 12 MHz Operation
SAB 8031A-15/8051A-15, 15 MHz Operation
• 4K x 8 ROM
.128 x 8 RAM
• Four 8-Bit Ports, 32 I/O Lines
• Two 16-Bit Timer/Event Counters
• High-Performance Full-Duplex
Serial Channel
• External Memory Expandable to 128K
Pin Configuration
• Compatible with SAB 8080/8085
Peripherals
• Boolean Processor
• 218 User Bit-Addressable Locations
• Most Instruction Execute in:
1 Ils (SAB 8031 A/8051 A)
800 ns (SAB 8031A-15/8051A-15)
• 4 Ils (3.2 [lS) Multiply and Divide
Logic Symbol
r
I
XTAL'___
TI
I
~"''':C''TOD
I ----
-_
- ~, --___
__
Programmable 110
Interrupts
-
---------
Interrupts
-----
Control
--
--
--
Parallel Ports
Address Data Bus
and 110 Pins
Programmable
serial port
. lull duplex UART
• shnchronous
siller
----1----Serial
IN
Serial
OUT
101
SAB S031A/S051A Ext. Temp.
Instruction Set Description
I Description
Mnemonic
I Byte I Cycle
Arithmetic operations
A,Rn
Add register to Accumulator
1
1
ADD
A, direct
Add direct byte to Accumulator
2
1
ADD
A.@Ri
Add indirect RAM to Accumulator
1
1
ADD
A,*data
Add immediate data to Accumulator
2
1
AD DC
A,Rn
Add register to Accumulator with Carry flag
1
1
ADD
AD DC
A,direct
Add direct byte to A with Carry flag
2
1
AD DC
A,@Ri
Add indirect RAM to A with Carry flag
1
1
AD DC
A,*data
Add immediate data to A with Carry flag
2
1
SUBB
A,Rn
Subtract register from A with Borrow
1
1
SUBB
A,direct
Subtract direct byte from A with Borrow
2
1
SUBB
A,@Ri
Subtract indirect RAM from A w/Borrow
1
1
SUBB
A,*data
Subtract immediate data from A w/Borrow
2
1
INC
A
Increment Accumulator
1
1
INC
Rn
Increment register
1
1
INC
direct
Increment direct byte
2
1
INC
@Ri
Increment indirect RAM
1
1
DEC
A
Decrement Accumulator
1
1
DEC
Rn
Decrement register
1
1
DEC
direct
Decrement direct byte
2
1
DEC
@Ri
Decrement indirect RAM
1
1
INC
DPTR
Increment Data Pointer
1
2
MUL
AB
Multiply A & B
1
4
DIV
AB
Divide A& B
1
4
DA
A
Decimal Adjust Accumulator
1
1
ANL
A,Rn
AND register to Accumulator
1
1
ANL
A,direct
AND direct byte to Accumulator
2
1
ANL
A,@Ri
AND indirect RAM to Accumulator
1
1
ANL
A,*data
AND immediate data to Accumulator
2
1
ANL
directA
AND Accumulator to direct byte
2
1
Logical operations
102
SAB S031A/S051A Ext. Temp.
Instruction Set Description (continued)
Description
Byte
Cycle
ANL
direct,*data
AND immediate data to direct byte
3
2
ORL
A,Rn
OR register to Accumulator
1
1
ORL
A,direct
OR direct byte to Accumulator
2
1
ORL
A,@Ri
OR indirect RAM to Accumulator
1
1
ORL
A,*data
OR immediate data to Accumulator
2
1
ORL
direct,A
OR Accumulator to direct byte
2
1
ORL
direct,*data
OR immediate data to direct byte
3
2
XRL
A,Rn
Exclusive-OR register to Accumulator
1
1
XRL
A,direct
Exclusive-OR direct byte to Accumulator
2
1
XRL
Mnemonic
A,@Ri
Exclusive-OR indirect RAM to A
1
1
XRL
A,*data
Exclusive-OR immediate data to A
2
1
XRL
direct,A
Exclusive-OR Accumulator to direct byte
2
1
XRL
direct,*data
Exclusive-OR immediate data to direct
3
2
CLR
A
Clear Accumulator
1
1
CPL
A
Complement Accumulator
1
1
RL
A
Rotate Accumulator Left
1
1
RLC
A
Rotate A Left through the Carry flag
1
1
RR
A
Rotate Accumulator Right
1
1
RRC
A
Rotate A Right through Carry flag
1
1
SWAP
A
Swap nibble's within the Accumulator
1
1
MOV
A,Rn
Move register to Accumulator
1
1
MOV
A,direct
Move direct byte to Accumulator
2
1
MOV
A,@Ri
Move indirect RAM to Accumulator
1
1
MOV
A,*data
Move immediate data to Accumulator
2
1
MOV
Rn,A
Move Accumulator to register
1
1
MOV
Rn,direct
Move direct byte to register
2
2
MOV
Rn,*data
Move immediate data to register
2
1
MOV
direct,A
Move Accumulator to direct byte
2
1
MOV
direct,Rn
Move register to direct byte
2
2
Mbv
direct,direct
Move direct byte to direct
3
2
I
Data transfer
*)
*) MOV A,ACC is not a vaiid instruction
103
SAB S031A/S051AExt. Temp.
Instruction Set Description (continued)
Mnemonic
Description
Byte
Cycle
MOV
direct,@Ri
Move indirect RAM to direct byte
2
2
MOV
d i rect,#d ata
Move immediate data to direct byte
3
2
MOV
@Ri,A
Move Accumulator to indirect RAM
1
1
MOV
@Ri,direct
Move direct byte to indirect RAM
2
2
MOV
@Ri,#data
Move immediate data to indirect RAM
2
1
MOV
DPTR,#data 16 .
Load Data Pointer with a 16-bit constant
3
2
MOVC
A,@A+DPTR
Move Code byte relative to DPTR to A
1
2
MOVC
A,@A+PC
Move Code byte relative to PC to A
1
2
MOVX
A,@Ri
Move External RAM (8-bit addr) to A
1
2
MOVX
A,@DPTR
Move External RAM (16-bit addr) to A
1
2
MOVX
@Ri,A
Move A to External RAM (8-bit addrl
1
2
MOVX
@DPTR,A
Move A to External RAM (16-bit addr)
1
2
PLJSH
direct
Push direct byte onto stack
2
2
POP
direct
Pop direct byte from stack
2
2
XCH
A,Rn
Exchange register with Accumulator
1
1
XCH
A,direct
Exchange direct byte with Accuniulator
2
1
XCH
A,@Ri
Exchange indirect RAM with A
1
1
XCHD
A,@Ri
Exchange low-order Digit ihd. RAM w/A
1
1
Data transfer (cant.)
Boolean variable manipulation
CLR
C
Clear Carry flag
1
1
CLR
bit
Clear direct bit
2
1
SETB
C
Set Carry flag
1
1
SETB
bit
Set direct Bit
2
1
CPL
C
Complement Carry flag
1
1
CPL
bit
Complement direct bit
2
1
ANL
C,bit
AND direct bit to Carry flag
2
2
ANL
C,/bit
AND complement of direct bit to Carry
2
2
ORL
C,bit
OR direct bit to Carry flag
2
2
ORL
C,/bit
OR complement of direct bit to Carry
2
2
MOV
C,bit
Move direct bit to Carry flag
2
1
MOV
bit,C
Move Carry flag to direct bit
2
2
104
SAB S031A/S051A Ext. Temp.
Instruction Set Description (continued)
IDescription
Mnemonic
I Byte I Cycle
Program and machine control
ACALL
addr 11
Absolute Subroutine Call
2
2
LCALL
addr 16
Long Subroutine Call
3
2
RET
Return from subroutine
1
2
RETI
Return from interrupt
1
2
AJMP
addr 11
Absolute Jump
2
2
LJMP
addr16
Long Jump
3
2
SJMP
rei
Short Jump Irelative addr)
2
2
JMP
@A+DPTR
Jump indirect relative to the DPTR
1
2
JZ
rei
Jump if Accumulator is Zero
2
2
JNZ
rei
Jump if Accumulator is Not Zero
2
2
JC
rei
Jump if Carry flag is set
2
2
JNC
rei
Jump if Carry flag not set
2
2
JB
bit, rei
Jump if direct Bit set
3
2
JNB
bit,rel
Jump if direct Bit not set
3
2
JBC
bit,rel
Jump if direct Bit is set & Clear bit
3
2
CJNE
A,direct,rel
Compare direct to A & Jump if Not Equal
3
2
CJNE
A,#data,rel
Compo immed. to A & Jump if Not Equal
3
2
CJNE
Rn,#data,rel
Compo immed. to reg. & Jump if Not Equal
3
2
CJNE
@Ri,#data,rel
Comp.immed. to indo & Jump if Not Equal
3
2
DJNZ
Rn,rel
Decrement register & Jump if Not Zero
2
2
DJNZ
direct, rei
Decrement direct & Jump if Not Zero
3
2
No operation
1
1
NOP
Notes on data addressing modes:
Rn
- Working register RO- R7
direct
- 128 internal RAM locations, any I/O port,
control or status register
@Ri
-Indirect internal RAM location addressed
by register RO or Rl
#data
- 8-bit constant included in instruction
#data 16 - 16-bit constant included as bytes 2 & 3
of instruction
bit
- 128 software flags, any I/O pin, control
or statu s bit
Notes on program addressing modes:
addr 16 - Destination address for LCALL & LJMP
may be anywhere within the 64-Kilobyte
program memory address space.
addr 11 - Destination address for ACALL & AJMP
will be within the same 2-Kilobyte page
of program memory as the first byte of
the following instruction.
rei
- SJMP and all conditional jumps include
an 8-bit offset byte. Range is + 127/-128
bytes relative to first byte ofthe following
instruction.
All mnemonics copyrighted © Intel Corporation 1979
105
SAB 8031A/8051A Ext. Temp.
Instruction Opcodes in Hexadecimal Order
Hex
Code
Number
of Bytes
Mnemonic Operands
Hex
Code
Number
of Bytes
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
JBC
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
JB
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JNB
ACALL
RETI
RLC
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
58
5C
5D
5E
5F
60
61
62
63
64
65
66
67
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
106
code addr
codeaddr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr code addr
codeaddr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr code addr
code addr
A
A,#data
A,dataaddr
A,@RO
A,@R1
A,RO
A,R1
AR2
A,R3
A,R4
A,R5
AR6
A,R7
bit addr, code addr
code addr
A
1
1
1
1
1
1
2
2
2
3
2
2
1
1
Mnemonic Operands
AD DC
AD DC
ADDC
ADDC
ADDC
AD DC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
XRL
XRL
A,#data
A,dataaddr
A,@RO
A,@R1
ARO
A,R1
A,R2
A,R3
A,R4
A,R5
AR7
A,R7
code addr
code addr
data addr, A
data addr, #data
A,#data
Adata addr
A,@RO
A,@R1
ARO
AR1
A,R2
AR3
AR4
AR5
AR6
A,R7
codeaddr
code addr
data addr, A
data addr,#data
A,#data
Adata addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
AR3
A,R4
AR5
A,R6
A,R7
code addr
code addr
data addr, A
data addr, #data
A#data
A,dataaddr
A@RO
A,@R1
SAB S031A/S051A Ext. Temp.
Instruction Opcodes in He)(adecimal Order (continued)
Hex
Code
Number
of 8ytes
68
69
6A
68
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
78
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
88
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
98
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
1
1
1
Hex
Code
Number
of 8ytes
A.RO
A.R1
A,R2
A.R3
A.R4
A,R5
A,R6
A,R7
9C
9D
9E
9F
AO
A1
A2
A3
1
1
1
1
code addr
code addr
C,bitaddr
A4
@A+DPTR
A7
A8
A9
AA
A8
AC
AD
AE
AF
80
81
82
83
84
85
86
87
88
89
8A
88
8C
8D
8E
8F
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
C8
CC
CD
CE
CF
Mnemonic Operands
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
DIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SU88
SU88
SUS8
SUSS
SU8S
SU88
SU88
SU88
A,#data
data addr,#data
@RO,#data
@R1,#data
RO,#data
R1,#data
R2,*data
R3,#data
R4,#data
R5,#data
R6,#data
R7,#data
code addr
code addr
C,bitaddr
A,@A+PC
A8
data addr,data addr
data addr,@RO
data addr,@R1
data addr, RO
data addr, R1
data addr, R2
data addr, R3
data addr, R4
data addr, R5
data addr, R6
data addr,R7
DPTR,*data
code addr
bitaddr,C
A,@A+DPTR
A.#data
A,data addr
A.@RO
A.@R1
A.RO
A,R1
A.R2
A.R3
2
2
2
1
1
A5
A6
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
1
1
1
1
Mnemonic Operands
SU88
SU88
SU88
SU88
ORL
AJMP
MOV
INC
MUL
reserved
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
A,R4
A.R5
A,R6
A,R7
C,fbit addr
code addr
C,bitaddr
DPTR
A8
@RO,data addr
@R1,data addr
RO,data addr
R 1 ,data addr
R2,data addr
R3,data addr
R4,data addr
R5,data addr
R6,data addr
R7,data addr
C,fbit addr
code addr
bit addr
C
A,#data,code addr
A.data addr,code addr
@RO,#data,codeaddr
@R1,#data,codeaddr
RO,#data,code addr
R 1,#data,code addr
R2,#data,code addr
R3,#data,code addr
R4,#data,code addr
R5,#data,code addr
R6,#data,code addr
R7,#data,code addr
data addr
code addr
bit addr
C
A
A.data addr
A,@RO
A.@R1
A,RO
A.R1
A,R2
A,R3
A,R4
A,R5
A.R6
A.R7
107
SAB 8031A/8051A Ext. Temp.
Instruction Opcodes in Hexadecimal Order (continued)
Hex
Code
Number
of Bytes
Mnemonic Operands
00
01
02
03
04
05
06
07
08
09
DA
DB
DC
DO
DE
DF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
Fl
F8
F9
FA
FB
FC
FD
FE
FF
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
POP
ACALL
SETB
SETB
OA
OJNZ
XCHO
XCHO
OJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
data addr
codeaddr
bitaddr
C
A
data addr,code addr
A,@RO
A,@R1
RO,code addr
R1,code addr
R2,code addr
R3,code addr
R4,code addr
R5,code addr
R6,code addr
R7,code addr
A,@DPTR
codeaddr
A,@RO
A,@R1
A
A,data addr *)
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
@DPTR,A
codeaddr
@RO,A
@R1,A
A
data addr,A
@RO,A
@R1,A
RO,A
R1,A
R2,A
R3,A
R4,A
R5,A
R6,A
Rl,A
*) MOV A,ACC is not a valid instruction
108
SAB S031A/S051A Ext. Temp.
Absolute Maximum Ratings 1)
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (VSS)
Power Dissipation
D.C. Characteristics
vcc = 5V ± 10%; VSS = OV
Symbol
-40 to
-40to
-65 to
-0.5to
+ 85'C for T40/85
+110'CforT40/110
+ 150'C
+ 7V
2W
TA = -40 to + 85'C for T40/85;
TA = -40 to + 110'C for T40/110
Parameter
Limit Values
Min.
Max.
0.8
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
except RST IVPD and
XTAL2
2.0
VIH1
Input High Voltage
to RST IVPD for
Reset, XTAL2
2.5
VPD
Power Down Voltage
To RSTIVPD
4.5
VOL
Output Low Voltage
Ports 1,2,3
VOL1
Output Low Voltage
Port 0, ALE, IPSEN
VOH
Output High Voltage
Ports 1,2,3
Units
Test Conditions
VCC+0.5
XTAL 1 to VSS
5.5
VCC
= OV
V
-
2.4
10L
= 1.6mA
10L
= 3.2 mA
10H
= -80 rIA
10H
= -400 rIA
= 0.45V
0.45
-
VOH1
Output High Voltage
Port 0, ALE, IPSEN
ilL
Logical 0 Input Current
Ports 1,2,3
-800
~IA
VIL
IIL2
Logical 0 Input Current
XTAL2
-2.5
mA
XTAL1 = VSS
VIL = 0.45 V
IIH1
Input High Current to
RST IVPD for Reset
500
III
Input Leakage Current
to Port O,lEA
±10
ICC
Power Supply Current
150
IPD
Power Down Current
15
CIO
Capacitance of 1/0 Buffer
10
-
VIN
= VCC-l.5 V
~IA
0< VIN < VCC
mA
-
pF
fc
= 1 MHz
1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
109
SAB S031A/S051A Ext. Temp.
A.C. Characteristics for T40/S5
vcc = 5V ± 10%; VSS = OV; TA = -40 to +85'C
(CL for Port 0, ALE and PSEN Outputs = 100 pF; CL for All Other Outputs = 80 pF)
Program Memory Characteristics
Symbol
Limit Values
Parameter
12 MHz Clock
Min
TLHLL
ALE Pulse Width
Max
127
Unit
Variable Clock
1/TCLCL = 1.2 MHz to 12 MHz
Min
Max
2TCLCL-40
-
TCLCL-30
-
TAVLL
Address Setup to ALE
53
TLLAXl
Address Hold After ALE
48
TLLlV
ALE To Valid Instr In
-
TLLPL
ALETa PSEN
58
TPLPH
PSEN Pulse Width
215
TPLIV
PSEN To Valid Instr In
-
150
-
3TCLCL-100
TPXIX
Input Instr Hold After PSEN
0
-
0
-
TCLCL-35
233
-
-
4TCLCL-l00
TCLCL-25
3TCLCL-35
-
TPXIZ*)
Input Instr Float After PSEN
-
63
-
TCLCL-20
TPXAV*)
Address Valid After PSEN
75
-
TCLCL-8
-
TAVIV
Address To Valid Instr In
-
302
-
5TCLCL-115
TAZPL
Address Float To PSEN
0
-
0
-
ns
External Data Memory Characteristics
Symbol
Parameter
Limit Values
12 MHz Clock
Min
Max
Unit
Variable Clock
1/TCLCL = 1.2 MHz to 12 MHz
Min
Max
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TLLAX2
Address Hold After ALE
132
TRLDV
RD To Valid Data In
-
250
-
5TCLCL-165
TRHDX
Data Hold After RD
0
-
0
-
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data ln
TAVDV
Address To Valid Data In
400
6TCLCL-l00
-
6TCLCL-l00
97
-
-
2TCLCL-35
517
2TCLCL-70
-
585
8TCLCL-150
ns
9TCLCL-165
TLLWL
ALE To WR or RD
200
300
3TCLCL-50
3TCLCL+50
TAVWL
Address To WR or RD
203
-
4TCLCL-130
-
TWHLH
WR or RD High To ALE High
43
123
TCLCL-40
TCLCL+40
TDVWX
Data Valid To WR Transition
33
TOVWH
Data Setup Before WR
433
TWHOX
Data Hold After WR
33
TRLAZ
Address Float After 'AD
-
TCLCL-50
-
7TCLCL-150
-
TCLCL-50
0
-
0
*) Interfacing the SAB 8051 A to devices with float times upto 75ns is permissible. This limited bus contention
will not cause any damage to Port 0 drivers.
110
SAB S031A/S051A Ext. Temp.
A.C. Characteristics for T40/110
vcc = 5V ±10%; VSS = OV; TA = -40to
(CL for Port 0, ALE and PSEN Outputs
=
+110°C
100 pF; CL for All Other Outputs
=
80 pF)
Program Memory Characteristics
Symbol
Parameter
Limit Values
10 MHz Clock
Min
Max
Unit
Variable Clock
lITCLCL = 1.2 MHz to 10 MHz
Min
Max
TLHLL
ALE Pulse Width
160
TAVLL
Address Setup to ALE
70
TLLAX1
Address Hold After ALE
65
TLLlV
ALE To Valid Instr In
-
TLLPL
ALE To PSEN
75
TPLPH
PSEN Pulse Width
265
TPLIV
PSEN To Valid Instr In
-
200
-
3TCLCL-100
TPXIX
Input Instr Hold After PSEN
0
-
0
-
2TCLCL-40
-
TCLCL-30
-
TCLCL-35
300
-
-
4TCLCL-100
TCLCL-25
ns
3TCLCL-35
TPXIZ*)
Input Instr Float After PSEN
-
80
-
TCLCL-20
TPXAV*)
Address Valid After PSEN
92
-
TCLCL-8
-
TAVIV
Address To Valid Instr In
-
385
-
5TCLCL-115
TAZPL
Address Float To PSEN
0
-
0
-
External Data Memory Characteristics
Symbol
Parameter
Limit Values
10 MHz Clock
Min
Max
Unit
Variable Clock
1/TCLCL = 1.2 MHz to 10 MHz
Min
Max
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TLLAX2
Address Hold After ALE
165
TRLDV
RD To Valid Data In
-
335
-
5TCLCL-165
TRHDX
Data Hold After RD
0
-
0
-
-
650
-
8TCLCL-150
500
6TCLCL-100
-
6TCLCL-100
-
2TCLCL-35
TRHDZ
Data Float After RD
TLLDV
ALE To Valid Data In
130
2TCLCL-70
TAVDV
Address To Valid Data In
TLLWL
ALE To WR or RD
250
350
3TCLCL-50
3TCLCL+50
TAVWL
Address To WR or RD
270
-
4TCLCL-130
-
TWHLH
WR or RD High To ALE High
60
140
TCLCL-40
TCLCL+40
TDVWX
Data Valid To WR Transition
50
735
TOVWH
Data Setup Before WR
550
TWHOX
Data Hold After WR
50
TRLAZ
Address Float After RD
-
ns
9TCLCL-165
TCLCL-50
-
7TCLCL-150
-
TCLCL-50
0
-
0
*) Interfacing the SAB 8051A to devices with float times up to 92ns is permissible. This limited bus contention
will not cause any damage to Port 0 drivers.
111
SAB 8031A/8051A Ext. Temp.
External Clock Drive XTAL2
Symbol
Limit Values
Parameter
Unit
Variable Clock
Freq = 1.2 MHz to 12 MHz (T40/85)
Freq = 1.2 MHz to 10 MHz IT40/110)
TClCl
Oscillator Period T40/85
T40/110
TCHCX
High Time
TClCX
low Time
TClCH
RiseTime
TCHCl
Fall Time
Min
Max
83.3
100
833.3
TClCl-TClCX
20
TCLCL-TCHCX
-
ns
20
External Clock Cycle
O.B
O.B
----- TCLCX i-------TCLCL----------o..-I
A.C. Testing Input, Output, Float Waveforms
2.4
~.45
2.4
0.45
X::
~::
Test Points
Float
::X
::~
2.4
0.45
AC testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Timing measurements are made at 2.0V for a logic "1" and 0.8V for a logic "0".
For timing purposes, the float state is defined as the point at which a PO pin sinks 3.2 mA or sources
400 ItA at the voltage test levels.
112
SAB S031A/S051A Ext. Temp.
ROM Verification Characteristics
TA=25'C±5'C; VCC=5V±10%; vss=ov
Symbol
Parameter
Limit Values
Min
TAVQV
Address to Valid Data
TELQV
Enable to Valid Data
Unit
Max
-
TEHQZ
Data Float after Enable
0
1/TCLCL
Oscillator Frequency
4
48 TCLCL
ns
6
MHz
I
ROM Verification
P1.0- P1.7
P2.0- P2,3
---i
--I
Address:
P1.0-P1.7 = AO-A7
P2.0-P2.3 = A8-A11
Data:
Port 0
= DO-D7
C
~Vo.V
Port 0
P2.7
ENABLE
)
Address
Data out
'1
-
~Ho.Z
J
Inputs: P2.4-P2.6, PSEN = VSS
ALE, EA
= TTL high level
RSTIVPD = VIH1
113
SAB S031A/S051A Ext. Temp.
Waveforms
Program Memory Read Cycle
1 - - - - - - - - - . - - - TCY
TLLIV - -
TLHLL -
TLLPL
ALE
~-TPLPH--
/--_ _f-_~-ITPXAV
TLLAXl tTPLIV -
TPXIZ
-TAVLL
-
\0----.....
-TAZPL
~---.-ln
)----,
PORT 0
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A15-AB
ADDRESS A15-AB
Data Memory Read Cycle
r---,",I-~--- TLLDV - - - -
TWHLH-
ALE
--TLLWL ~I-----ITRLRH - - - - - - 1
I
------~----~
I~- -TAVWl-~
TRLDV~
Port 0
Port 2
114
ADDRESS
OR SFR-P2
ADDRESS A15-AB OR SFR-P2
SAB 8031A/S051A Ext. Temp.
Data Memory Write Cycle
TWHLH ,----
\
I
ALE
I
~-TLLWL-I------TWLWH-----,
:
Port 0
I
I
I-b:~_,-,,,,, m,,"
==>-1 Jxt
A7-AO
[
DATA OUT
)
I
I
Port 2
d
AOORESS
ADDRESS A15-AB OR SFR-P2
OR SFR-P2~\-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
Recommended Oscillator Circuits
_--I1-----4~--'-19'_l XT AL 1
19 XTAL 1
+ 5V
=
4.7k
1.2-12MHz
1-_------_---+_ _ _ _1"'-j8 XTAL2
7404
74LS04
C=30pF±10pF
Crystal
Oscillator Mode
Driving from External Source
115
SAB 8032A18052A
8-Bit Single Chip Microcomputer
SAB 8032A Control-oriented CPU with RAM and 110
SAB B052A A SAB 8032A with factory mask-programmable ROM
• 8K x 8 ROM (SAB 8052A only)
.256 x 8 RAM
• Timer 2 capture capability
• Variable transmit/receive baud rate capability
Four 8-bit ports, 32 110 lines
Three 16-bit timerlevent counters
High-performance full-duplex serial channel
External memory expandable to 128 Kbytes
III Compatible with SAB 8080/8085 peripherals
• Boolean processor
• Most instructions execute in 1 ~s
•
•
•
•
Pin Configuration
• 4 ~s multiply and divide
• Upward compatible with SAB 8031A/8051A
Logic Symbol
Y5SII(C
!!sTII/PO
"',.
'"
11032,.,
'"
IIOS2 ...
~32"
"'-
If['i_-I-
The SAB 8032A/8052A is a stand-alone, high-performance single-chip microcomputer fabricated in
+5V advanced N-channel, silicon gate Siemens
MYMOS technology, packaged in a 40-pin DIP.
It is upward compatible with the SAB 8031A/8051A.
It provides the hardware features, architectural
enhancements, and instructions that are
necessary to make it a powerful and cost effective
controller for"applications requ iring up to 64 Kbytes
of program memory andlor up to 64 Kbytes of data
memory.
The SAB 8052A contains a non-volatile 8 K x 8 read-
only program memory; a volatile 256 x 8 readlwrite
data memory; 32 110 lines; three 16-bit timerl
counters; a six-source, two-priority-Ievel, nested
interrupt structure; a serial 110 port for either
multiprocessor communications, 110 expansion,
or full duplex UART; as well as on-chip oscillator
and clock circuits. The SAB 8032A is identical, except
that it lacks the program memory ..
For systems that require extra capability, the
SAB 8052A can be expanded using standard TTL
compatible memories and the byte oriented
SAB 8080 and SAB 8085 peripherals.
AG3/85
117
SAB 8032A/8052A
Pin Definitions and Functions
Symbol
Number
Input (I)
Output (0)
Pl.0~P1.7
1~8
1/0
Port 1 is an 8-bit quaoi-bidirectionall/O port. It is used for
the low-order address byte during program verification.
Port 1 can sink/source four LS TIL loads. Pins Pl.0 and
Pl.l also correspond to the special functions T2, external
input to Timer 2, and T2EX, Timer 2 trigger input. The
output latch on these two special function pins must be
programmed to a one (1) for that function to operate.
RSTIVPD
9
I
A high level on this pin resets the SAB 8052A. A small
internal pulldown resistor permits power-on reset using
onlya capacitor connected to vee. If VPD is held within its
spec while vee drops below spec, VPD will provide
standby power to the RAM. When VPD is low, the RAM's
current is drawn from vee.
P3.0~P3.7
10--17
I/O
Port 3 is an 8-bit quasi-bidirectional I/O port. It also
contains the interrupt, timer, serial port and RD and WR
pins that are used by various options. The output latch
corresponding to a secondary function must be programmed to a one (1) for that function to operate. Port 3
can sink/source four LS TIL loads. The secondary
functions are assigned to the pins of Port 3, as follows:
~ RXD/data (P3.0). Serial port's receiver data input
(asynchronous) or data input/output (synchronous).
~ TXD/clock (P3.1). Serial port's transmitter data output
(asynchronous) or clock output (synchronous).
~ INTO (P3.2). Interrupt 0 input or gate control input for
counter O.
~ TNTl (P3.3). Interrupt 1 input or gate control input for
counter 1.
~ TO (P3.4). Input to counter O.
~ Tl (P3.5). Input to counter 1.
~ WR (P3.6). The write control signal latches the data
byte from port 0 into the external data memory.
~ RD (P3.7). The read control signal enables external
data memory to port O.
XTALl
XTAL2
19
18
I
XTAL 1 input to the oscillator's high gain amplifier.
Required when a crystal is used. Connect to VSS when
external sou rce is used on XTAL 2.
XTAL 2 output from the oscillator's amplifier. Input to the
internal timing circuitry. A crystal or external source can
be used.
P2.0--P2.7
21~28
I/O
Port 2 is an 8-bit quasi-bidirectional I/O port. It also emits
the high-order address byte "'hen accessing external
memory. It is used for the high-order address and the
control signals during program verification. Port 2 can
sinklsource four LS TIL loads.
PSEN
29
0
The program store enable output is a control signal that
enables the external program memory to the bus during
external fetch operations. It is activated every six oscillator
periods, except during external data memory accesses.
Remains high during internal program execution.
118
Function
SAB S032A/S052A
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
ALE
30
0
Provides address latch enable output used for latching
the address into external memory during normal
operation. It is activated every six oscillator periods
except during an external data memory access.
EA
31
I
When held at a TIL high level, the SAB 8052A executes
instructions from the internal ROM when the PC is
less than 8192. When held ata TTL low level, the SAB 8052A
fetches all instructions from external program memory.
For the SAB 8032A this pin must be tied low.
PO.O-PO.7
39-32
1/0
Port 0 is an S-bit open drain bidirectional 1/0 port. It is
also the multiplexed low-order address and data bus
when using external memory. It is used for data output
during program verification. Port 0 can sinklsource
eight LS TIL loads.
VCC
40
+5V power supply during operation and program
verification.
VSS
20
Circuit ground potential.
Function
Block Diagram
Frequency
Reference
r
I
-t---r----------------------
I
I
8192 bytes
Program
Memory
(SAB B052A only)
Oscillator
I
I
&
Timing
I
64 Kbyte Bus
I
I
I
ExpanSion
Control
=>
Interrupts
-
---------
Interrupts
I
I
U
t
I
I
I
L
I
SAB B052A
CPU
I
I
Three 16 bit
Timer IEvent
C()Jnters
256 bytes
Data Memory
~
I
I
I
I
I
Counters
----~--~---l
-----
Control
Programmable I/O
fr
--u--
--
Parallel Ports
Address Data Bus
and 110 Pins
I
I
I
Programmable
senal port
. full duplex UART
. synchronous
shilter
I
I
I
I
I
I
- - - - - - - - -.~
Senal
IN
Seflal
OUT
119
SAB S032A/S052A
Instruction Set Description
Mnemonic
[ Description
[ Byte
[ Cycle
Arithmetic operations
ADD
A Rn
Add register to Accumulator
1
ADD
A direct
Add direct byte to Accumulator
2
1
ADD
A,@Ri
Add indirect RAM to Accumulator
1
1
ADD
A#data
Add immediate data to Accumulator
2
1
ADDC
ARn
Add register to Accumulator with Carry flag
1
1
ADDC
Adirect
Add direct byte to Accu with Carry flag
2
1
ADDC
A(dRi
Arlrl
~
~
ADDC
A,#data
Add immediate data to Accu with Carry flag
2
1
SUBB
ARn
Subtract register from Accu with borrow
1
1
SUBB
Adirect
Subtract direct byte from Accu with borrow
2
1
SUBB
A@Ri
Subtrac! indirect RAM from A with borrow
1
1
inriirprt
RAM
tn A t:'t:' I_I I/Ilith C?rr~1
f!22
1
SUBB
A,#data
Subtract immediate data from A with borrow
2
1
INC
A
Increment Accumulator
1
1
INC
Rn
Increment register
1
1
INC
direct
Increment direct byte
2
1
INC
@RI
Increment indirect RAM
1
1
DEC
A
Decrement Accumulator
1
1
DEC
Rn
Decrement register
1
1
DEC
direct
Decrement direct byte
2
1
DEC
@Ri
Decrement indirect RAM
1
1
INC
DPTR
Increment data pointer
1
2
MUL
AB
Multiply A & B
1
4
DIV
AB
Divide A & B
1
4
DA
A
Decimal adjust Accumulator
1
1
ANL
A,Rn
AND register to Accumulator
1
1
ANL
Adirect
AND direct byte to Accumulator
2
1
ANL
A@Ri
AND indirect RAM to Accumulator
1
1
ANL
A*data
AND immediate data toAccumulator
2
1
ANL
direct,A
AND Accumulator to direct byte
2
1
Logical operations
120
SAB 8032A/8052A
Instruction Set Description (continued)
Mnemonic
Description
Byte
Cycle
ANL
direct,l'data
AND immediate data to direct byte
3
2
ORL
A,Rn
OR register to Accumulator
1
1
ORL
A,direct
OR direct byte to Accumulator
2
1
ORL
A,@Ri
OR indirect RAM to Accumulator
1
1
ORL
A,*data
OR immediate data to Accumulator
2
1
ORL
direct,A
OR Accumulator to direct byte
2
1
ORL
direct,*data
OR immediate data to direct byte
3
2
XRL
ARn
Exclusive-OR register to Accumulator
1
1
XRL
Adirect
Exclusive-OR, direct byte to Accumulator
2
1
XRL
A,@Ri
Exclusive-OR indirect RAM to Accumulator
1
1
XRL
A*data
Exclusive-OR immediate data to Accumulator
2
1
XRL
direct,A
Exclusive-OR Accumulator to direct byte
2
1
XRL
direct,*data
Exclusive-OR immediate data to direct
3
2
CLR
A
Clear Accumulator
1
1
CPL
A
Complement Accumulator
1
1
RL
A
Rotate Accumulator left
1
1
RLC
A
Rotate A left through the Carry flag
1
1
RR
A
Rotate Accumulator right
1
1
RRC
A
Rotate A right through Carry flag
1
1
SWAP
A
Swap nibbles within the Accumulator
1
1
MOV
ARn
Move register to Accumulator
1
1
MOV
Adirect *
Move direct byte to Accumulator
2
1
MOV
A,@Ri
Move indirect RAM to Accumulator
1
1
MOV
A,*data
Move immediate data to Accumulator
2
1
MOV
Rn,A
Move Accumulator to register
1
1
MOV
Rn,direct
Move direct byte to register
2
2
MOV
Rn,#data
Moire immediate data to register
2
1
MOV
direct,A
Move Accumulator to direct byte
2
1
MOV
direct,Rn
Move register to direct byte
2
2
MOV
direct,direct
Move direct byte to direct
3
2
Data transfer
'Note: MOV A, ACC is not a valid instruction
121
SAB S032A/S052A
Instruction Set Description (continued)
Description
Byte
Cycle
direct,@Ri
Move indirect RAM to direct byte
2
2
MOV
direct,*data
Move immediate data to direct byte
3
2
MOV
@Ri,A
Move Accumulator to indirect RAM
1
1
MOV
@Ri,direct
Move direct byte to indirect RAM
2
2
MOV
@Ri,*data
Move immediate data to indirect RAM
2
1
MOV
DPTR,*data 16
Load data pointer with a 16-bit constant
3
2
Mnemonic
MOV
Data transfer (cont.)
MOVC
A,@A+DPTR
Move code byte relative to DPTR to Accumulator 1
2
MOVC
A.@A+PC
Move code byte relative to PC to Accumulator
1
2
MOVX
A,@Ri
Move external RAM (8-bit addrl to Accumulator
1
2
MOVX
A,@DPTR
Move external RAM (16-bit addrl to Accumulator 1
2
MOVX
@Ri,A
Move A to external RAM (8-bit addr)
1
2
MOVX
@DPTR,A
Move A to external RAM (16-bit addrl
1
2
PUSH
direct
Push direct byte onto stack
2
2
POP
direct
Pop direct byte from stack
2
2
XCH
A.Rn
Exchange register with Accu,nulator
1
1
XCH
A,direct
Exchange direct byte with Accumulator
2
1
XCH
A,@Ri
Exchange indirect RAM with Accumulator
1
1
XCHD
A,@Ri
Exchange low-order digit indo RAM with Accu
1
1
Boolean variable manipulation
CLR
C
Clear Carry flag
1
1
CLR
bit
Clear direct bit
2
1
SETB
C
Set Carry flag
1
1
SETB
bit
Set direct bit
2
1
CPL
C
Complement Carry flag
1
1
CPL
bit
Complement direct bit
2
1
ANL
C,bit
AND direct bit to Carry flag
2
2
ANL
C,fbit
AND complement of direct bit to Carry
2
2
ORL
C,bit
OR direct bit to Carry flag
2
2
ORL
C,fbit
OR complement of direct bit to Carry
2
2
MOV
C,bit
Move direct bit to Carry flag
2
1
MOV
bit,C
Move Carry flag to direct bit
2
2
122
SAB S032A/S052A
Instruction Set Description (continued)
IDescription
Mnemonic
I Byte I Cycle
Program and machine control
ACALL
addr 11
Absolute subroutine call
2
2
LCALL
addr16
Long subroutine call
3
2
RET
Return from subroutine
1
2
RETI
Retu rn from interrupt
1
2
AJMP
addr 11
Absolute jump
2
2
LJMP
addr16
Longjump
3
2
SJMP
rei
Short jump (relative addr)
2
2
JMP
@A+DPTR
Jump indirect relative to the DPTR
1
2
JZ
rei
Jump if Accumulator is zero
2
2
JNZ
rei
Jump if Accumulator is not zero
2
2
JC
rei
Jump if Carry flag is set
2
2
JNC
rei
Jump if Carry flag is not set
2
2
JB
bit,rel
Jump if direct bit set
3
2
JNB
bit,rel
Jump if direct bit not set
3
2
JBC
bit,rel
Jump if direct bit is set and clear bit
3
2
CJNE
A.directrel
Compare direct to Accu and jump if not equal
3
2
CJNE
A.*data,rel
Comp, immed, to Accu and jump if not equal
3
2
CJNE
Rn,*data,rel
Comp, immed, to reg, and jump if not equal
3
2
CJNE
@Ri,*data,rel
Comp,immed, to ind, and jump if not equal
3
2
DJNZ
Rn,rel
Decrement register and jump if not zero
2
2
DJNZ
direct,rel
Decrement direct and jump if not zero
3
2
No operation
1
1
NOP
Notes on data addressing modes:
Rn
- Working register RO- R7
direct
- 128 internal RAM locations, anY.I/O port,
control or status register
@Ri
_. Indirect internal RAM location addressed
by register RO or R1
*data
- 8-bit constant included in instruction
*data 16- 16-bit constant included as bytes 2 & 3 of
instruction
bit
_. 128 software flags, any 1/0 pin, control
or status bit
A
- Accumulator
All mnemonics copyrighted
(C)
Notes on program addressing modes:
addr 16 - Destination address for LCALL & LJMP
may be anywhere within the 64-Kbyte
program memory address space,
addr 11 - Destination address for ACALL & AJ MP
will be within the same 2-Kbyte page
of program memory as the first byte of
the following instruction,
rei
- SJMP and all conditional jumps include
an 8-bit offset byte, Range is + 127/--128
bytes relative to first byte of the following
instruction,
Intel Corporation 1979
123
SAB S032A/S052A
Instruction Opcodes in Hexadecimal Order
Hex
Code
Number
of Bytes
00
01
02
03
04
05
06
07
08
09
OA
OB
0C
OD
OE
OF
10
11
12
13
14
15
16
'17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
1
2
124
3
1
1
2
1
1
1
1
1
1
Mnemonic Operands
Hex
Code
Number
of Bytes
Mnemonic Operands
NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
2
2
1
1
1
1
1
1
1
1
1
1
AD DC
AD DC
ADDC
ADDC
AD DC
AD DC
AD DC
AD DC
ADDC
ADDC
AD DC
ADDC
~v
2
...
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
XRL
XRL
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
1
!~~C
~4
1
1
1
INC
INC
INC
JBC
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
JB
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JNB
ACALL
RETI
RLC
R5
R6
R7
bit addr code addr
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr code addr
code addr
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
A
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bit addr, code addr
code addr
A
"
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R7
A,R7
L;UU'~
dulir
code addr
data addr,A
data addr, #data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr,#data
A,#data
A,data addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
data addr,A
data addr, #data
A,#data
A,data addr
A,@RO
A,@R1
SAB S032A/S052A
Instruction Opcodes in Hexadecimal Order (continued)
Hex
Code
Number
of Sytes
58
59
5A
5S
5C
50
5E
5F
70
71
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
72
73
74
75
75
77
78
79
7A
7S
7C
70
7E
7F
80
81
82
83
84
85
85
87
88
89
8A
8S
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
1
1
1
1
1
1
Mnemonic Operands
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
OIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUSS
SUSS
SUBS
SUBS
SUBS
SUSS
SUSS
SUBS
A,RO
A,R1
A,R2
A,R3
AR4
A,R5
A,R5
A,R7
code addr
code addr
C,bitaddr
@A+OPTR
A,#data
data addr, #data
@RO,#data
@R1,#data
RO,#data
R1,#data
R2,#data
R3,#data
R4,#data
R5,#data
R6,#data
R7,#data
code addr
code addr
C,bitaddr
A@A+PC
AS
data addr,data addr
data addr,@RO
data addr,@R1
data addr, RO
data addr, R1
data addr, R2
data addr, R3
data addr, R4
data addr, R5
data addr, R5
data addr, R7
OPTR,#data
code addr
bit addr,C
A,@A+OPTR
A#data
A,qata addr
A,@RO
A,@R1
A,RO
A,R1
A,R2
AR3
Hex
Code
Number
of Sytes
9C
90
9E
9F
AO
A1
A2
A3
1
1
1
1
2
2
2
1
1
A4
A5
A6
A7
A8
A9
AA
AB
AC
AO
AE
AF
BO
S1
S2
S3
S4
B5
B5
S7
S8
B9
SA
BS
SC
SO
BE
BF
CO
C1
C2
C3
C4
C5
C5
C7
C8
C9
CA
CB
CC
CO
CE
CF
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
1
1
1
1
Mnemonic Operands
SUSS
SUSS
SUSS
SUSS
ORL
AJMP
MOV
INC
MUL
reserved
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
AR4
AR5
A,R5
AR7
C,fbit addr
code addr
C,bitaddr
OPTR
AB
@RO,data addr
@R1,dataaddr
RO,data addr
R1,data addr
R2,data addr
R3,data addr
R4,data addr
R5,data addr
R5,data addr
R7,data addr
C,fbit addr
code addr
bitaddr
C
A,#data,code addr
A,data addr,code addr
@RO,#data,codeaddr
@R 1,#data, code addr
RO,#data,code addr
R1,#data,code addr
R2,#data,code addr
R3,#data,code addr
R4,#data,code addr
R5,#data,code addr
R6,#data,code addr
R7,#data,code addr
data addr
code addr
bitaddr
C
A
Adataaddr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
AR6
AR7
125
SAB S032A/S052A
Instruction Opcodes in Hexadecimal Order (continued)
Hex
Code
Number
of Bytes
Mnemonic Operands
DO
Dl
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
2
2
2
1
1
3
1
1
2
2
2
2
POP
ACALL
SETB
SETB
DA
DJNZ
XCHD
XCHD
DJNZ
DJNZ
DJNZ
DJNZ
data addr
code addr
bitaddr
C
A
data addr,code addr
A,@RO
A,@Rl
RO,code addr
R1,code addr
R2,code addr
R3,code addr
auu,
~~
~v
~
,....IRoI..,
LJ..J I 'ilL.
il~,cuU'tt
DD
DE
DF
EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
2
2
2
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
DJNZ
DJNZ
DJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5,code addr
R6,code addr
R7,code addr
A,@DPTR
code addr
A,@RO
A.@Rl
A
A,dataaddr *
A,@RO
A,@Rl
A.RO
A.Rl
A,R2
A.R3
A.R4
A.R5
A,R6
A,R7
@DPTR,A
codeaddr
@RO,A
@Rl,A
A
data addr,A
@RO,A
@Rl,A
RO,A
Rl,A
R2,A
R3,A
R4,A
R5,A
R6,A
R7,A
-Note: MOV A, ACC is not a valid Instruction
126
SAB 8032A/8052A
Absolute Maximum Ratings 1)
o to 70'C
-65 to + 150'C
-0.5to + 7 V
Ambient Temperature under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (VSS)
Power Dissipation
2W
D.C. Characteristics
TA
= 0 to 70'C; vcc = 5 V ± 10%; VSS = 0 V
Symbol
Parameter
Limit Values
Min.
Max.
0.8
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
(Except RSTIVPD and XTAL21
2.0
VIH1
Input High Voltage to
RSTIVPD for Reset, XTAL2
2.5
VPD
Power Down Voltage
to RSTIVPD
4.5
VOL
Output Low Voltage
Ports 1,2,3
VOL 1
Unit
Test Condition
-
VCC+0.5
XTAL1 to VSS
5.5
VCC
= OV
10L
= 1.6 mA
Output Low Voltage
Port 0, ALE, PSEN
10L
= 3.2 mA
VOH
Output High Voltage
Ports 1,2,3
10H
= -80 ilA
VOH1
Output High Voltage
Port 0, ALE, PSEN
10H
= -400 flA
ilL
Logical 0 Input Current
Ports 1,2,3
-800
rlA
VIL
= 0.45 V
IIL2
Logical 0 Input Current
XTAL2
-2.0
mA
XTAl1 = VSS
VIL = 0.45V
IIH1
Input High Current to
RST IVPD for Reset
500
III
Input Leakage Current
to Port 0, EA
±10
ICC
Power Supply Current
175
V
-
2.4
0.45
-
-
VIN
flA
mA
IPD
Power Down Current
15
CIO
Capacitance of 1/0 Buffer
10
OV < VIN < VCC
All outputs
disconnected
VCC
pF
= VCC-1.5 V
f,
= OV
= 1 MHz
1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
127
SAB S032A/S052A
A.C. Characteristics
TA = O"C to 70 C; VCC = 5V ±10%; VSS = OV
(CL for Port 0, ALE and PSEN Outputs = 100 pF; CL for All Other Outputs
C
= 80 pF)
Program Memory Characteristics
Symbol
Parameter
Limit Values
Variable Clock
l/TCLCL = 1.2 MHz to 12 MHz
12 MHz Clock
Min
Max
127
Unit
Min
Max
TLHLL
ALE Pulse Width
2TCLCL·40
TAVLL
Address Setup to ALE
53
TLLAXl
Address Hold after ALE
48
TLLlV
ALE to Valid Instr In
-
TLLPL
ALE to PSEN
58
TPLPH
PSEN Pulse Width
215
TPLIV
PSEN to Valid Instr In
-
150
-
3TCLCL-l00
TPXIX
Input Instr Hold after PSEN
0
-
0
-
-
TCLCL·30
-
TCLCL-35
233
-
4TCLCL-l00
TCLCL-25
-
3TCLCL-35
-
TPXIZ*)
Input Instr Float after PSEN
-
63
-
TCLCL-20
TPXAV*)
Address Valid after PSEN
75
-
TCLCL-8
-
TAVIV
Address to Valid Instr In
-
302
-
5TCLCL-115
TAZPL
Address Float to PSEN
0
-
0
-
ns
External Data Memory Characteristics
Symbol
Parameter
Limit Values
12 MHz Clock
Min
Max
Unit
Variable Clock
l/TCLCL = 1.2 MHz to 12 MHz
Min
Max
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TLLAX2
Address Hold after ALE
132
TRLDV
RD to Valid Data In
-
250
-
5TCLCL-165
TRHDX
Data Hold after RD
0
-
0
-
400
-
6TCLCL-l00
-
2TCLCL-35
2TCLCL-70
TRHDZ
Data Float after RD
TLLDV
ALE to Valid Data In
97
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
200
300
3TCLCL-50
3TCLCL+50
TAVWL
Address to WR or RD
203
-
4TCLCL-130
-
TWHLH
WR or RD High to ALE High
43
123
TCLCL-l\O
TCLCL+40
TDVWX
Data Valid to WR Transition
33
TOVWH
Data Setup before WR
433
TWHOX
Data Hold after WR
33
TRLAZ
Address Float after RD
-
-
517
-
585
8TCLCL-150
ns
9tCLCL-165
TCLCL-50
-
7TCLCL-150
-
TCLCL-50
0
-
0
.*) Interfacing the SAB 8052A to devices with float times up to 75ns is permissible. This limited bus
contention will not cause any damage to Port 0 drivers.
128
SAB S032A/S052A
External Clock Drive XTAL2
Symbol
Parameter
Limit Values
Unit
Variable Clock
Freq = 1.2 MHz to 12 MHz
TCLCL
Oscillator Period
TCHCX
High Time
TCLCX
Low Time
TCLCH
Rise Time
TCHCL
Fall Time
Min
Max
83.3
833.3
TCLCL-TCLCX
20
TCLCL-TCHCX
-
ns
20
External Clock Cycle
08
TeLCX - - -
1 - - - - - - - - TCLCL - - - - - - - - - < - J
A.C. Testing Input, Output, Float Waveforms
::5 ______
~:><::~:~:~__
T_e_st_p_o_ln_t_s____
-t:---------------<::
Float
2.4
~:~:~~
045 _ _ _
0
...
_____
..
~
2.4
0.45
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Timing measurements are made at 2.0V for a logic "1" and 0.8V for a logic "0".
For timing purposes, the float state is defined as the point at which a PO pin sinks 3.2mA or sources
400 !IA at the voltage test levels.
129
SAB S032A/S052A
Waveforms
Program Memory Read Cycle
~--------------------T[Y
TLLIV - - !r---,L--1TLLPL
ALE
TPLPH-
PORT 0
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A15 - A 8
Data Memory Read Cycle
~
_ _"'\ t-~----- TLLDV
-------I
TWHLH
ALE
--TLLWL --I----------ITRLRH ----------1
TRHDZ
---TAVWLTRLDV-
DATA IN
Port 0
Port 2
130
TRHDX-
ADDRESS
OR SFR-P2
ADDRESS A15-A8 OR SFR-P2
SAB S032A/S052A
Data Memory Write Cycle
ALE
PSEN
TLLWL- •
TWLWH
WR
TAVWL
TDVWX
TIlVWH
TWHIlX
DATA OUT
Port 0
ADDRESS A15· AS OR SFR-P2
Port 2
Recommended Oscillator Circuits
~_--JII--_ _ _---,-19~
XTAL 1
19 XTAL 1
+ 5V
=
4.7k
1.2-12MHz
L-_--JII--_......_--'18"-1 XTAL 2
k>-_....... ____1"'l8 XTAL 2
7404
74LS04
(=30pF !10pF
(rystal Oscillator Mod.
Driving from Ext.rnal SOU".
131
SAB S032A/S052A
ROM Verification Characteristics
TA=25'C±5'C; VCC=5V±10%; vss=ov
Symbol
Parameter
TAVQV
Address to Valid Data
TELOV
Enable to Valid Data
TEHQZ
Data Float after Enable
0
llTCLCL
Oscillator Frequency
4
Limit Values
Min
Max
48 TCLCL
ns
6
MHz
ROM Verification
P10 - P17
P2.0- P2.4
J
PortO
Address
Data out
T1 -1
Address:
P1.0-P1.7 = AO-A7
P2.0-P2.4 = A8-A12
Data:
Port 0
Inputs:
P2.5-P2.6, PSEN = VSS
ALE, EA
= TTL high level
RSTIVPD = VIHl
132
)
~VUV
f---
P2.7
ENABLE
Unit
= DO- D7
r-!IHUZ
C
SAB 80C482 (8M 850)
SD:lBnt
SOrrllg~e
Chip Microcomputer
Preliminary data
CMOS circuit
The SAB 80C482 is a low-power, advanced CMOS member of the popular SAB 8048 family. The SAB
80C482 contains double-sized program memory and 4 additional 110 lines. For systems that require
extra capability, the SAB 80C482 can easily be expanded using CMOS external memories. The onchip mask-programmable keyboard wake-up offers a convenient solution for a power-saving keyboard
scanner. The SAB 80C482 has the same cycle time at about half the SAB 8048 clock frequency. The
100% static operation provides the possibility to optimize between power consumption and program speed.
The CMOS design of the SAB 80C482 opens new application areas that require battery operation,
low power standby, wide voltage range, and the ability to maintain operation during AC power line
interruptions. These applications include telecommunications, automotive, consumer, portable, and
hand-held instruments.
o 2K x 8 ROM
064 x 8 RAM
o 31 I/O lines
o 2.66 I-Is cycle time
(with 3 MHz crystal)
o Automatic power-on reset
o Keyboard wake-up
o
Very low power consumption
Normal: 1.2 mA@5 V@8 I-IS cycle
o Halt 0.4 mA@5 V@8 I-Is cycle
o Standby: 2 I-IA@5 V
o 100% static operation
@ Supply voltage: 2.5 to 6 V
Q
AG 11/84
133
134
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
SAB 80C482
(SM 850)
Pin description
Pin No.
Symbol
Description
2
XTALl
Oscillator input; one side of crystal input
3
XTAL2
Oscillator output; other side of crystal input
40
OSCEN
Oscillator enable input
(Schmitt-Trigger input)
A high signal enables oscillator to run
A low signal stops oscillator and initializes standby mode
4
6
RESET
Input used to initialize processor (active low).
INT
Interrupt input with internal pull-up resistor. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after reset.
HALT mode is terminated by interrupt (active low).
8
RD/EA
Output strobe activated during a bus read. Can be used to
enable transfer of data on the bus from an external device.
Used as a read strobe to external data memory (active low).
External access input which forces all program memory fetches
to reference external memory. Active only during the initialization time (RESET at low)! (active low).
9
TO/PSEN
Input pin testable using the instructions .:.ITO and JNTO until
disabled through an execution of instructions SEL·MBO or SEL
MB1.
Program store enable. This output is enabled through the first
execution of instructions SEL MBO or SEL MB 1. It can be
disabled only through a new RESET initialization.
It occurs only during a fetch to external program memory
(active low).
10
WRNER
Output strobe during a bus write. Used as vyrite strobe to
external data memory (active low).
ROM verification input is low during the initialization time
(RESET at low). The contents of the internal ROM can be read
without program execution.
135
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
SAB 80C482
(SM 850)
Pin No.
Symbol
Description
11
ALE
Address latch enable. This signal occurs once during each
cycle and is useful as clock output. Negative edge of ALE
strobes address into external data and program memory.
12... 19
080 ... 087
True bidirectional port which can be written or read synchronously using WR, RO strobes.
Contains the 8 low-order program counter bits during an
external program memory fetch, and .receives the addressed
instruction under the control of PSEN. Also contains the
address and data during an external RAM data store instruction, under control of ALE, RO, and. WR.
21 ... 24
P40 ... P43
4-bit quasi-bidirectional port. Internal puli-up resistors. This
port contains the four high order prOQram-counter bits during
an external program memory fetch.
5,7,
P60 .. P63
4-bit quasi-bidirectional port. Internal puli-up resistors.
Keyboard wake-up capability mask-programmable.
27 ... 34
P10 ... P17
8-bit quasi-bidirectional port. Internal puli-up resistors. Keyboard wake-up capability mask-programmable.
35 ... 38
P50 ... P53
4-bit quasi-bidirectional port. Internal puli-up resistors. Keyboard wake-up capability mask-programmable.
39
T1
1
VOO
Input pin testable using JT1, and JNT1 instructions. Can be
designated as timer/counter input using the STRT CNT instruction.
Power supply
20
VSS
Circuit GNO potential (0 VI
25, 26
136
UI
0'
n
~
a.
Internal ROM
2K K 8
i"
iil
3
eniD'
3"m
-:r
CQ"C
CPo
O:J
:rCD
-S"O
caO
":J
tD;::;:a
0=
s:~
oCJ)
3:
(=)"
ao
R
A
M 01
o
3
-
"'C
RAM
c:
CD
..;:!..
E
A (
g gI Register bonk 1
R
R
E
RI
Stock
~I I Register bonk 0
w
.....
t;J
Reset
logic
~
_tD
CJ)ca
-
3:0
OSCEN
m~
.91\)
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Oscillator
The on-board oscillator is a high-gain resonant circuit with a frequency range between
o and 3 MHz. The clock frequency is determined by the resonator (e.g. crystal) connected
between the pins XTAL 1 and XTAL2.
22pF
100pF
vss ~1--~--~--IXTALl
1--------<~__tXTAL2
vss r-i1--~--~---jXTAL 1
Vss r - i t - -.......- -.......- - - i XTAL2
100pF
b)
a)
p----IXTAl 1
----iXTAl2
c)
8-bit timer/counter
The SAB 80 C 842 contains a timer/counter to aid the user in counting and generating
accurate time delays without placing a burden on the processor for these functions.
Timer
Execution of a START T instruction connects an internal clock to the counter input. The
XTAL frequency divided by 256 is the timer input frequency.
Counter
Execution of a START CNT instruction connects the T1 pin to the counter input and enables
the counter. Subsequent high-to-Iow transition on T 1 pin must be held low for at least one
machine cycle to ensure it is not missed. The counter may be incremented only once
throughout three instruction cycles. There is no minimum frequency limit.
138
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
SAB 80C482
(SM 850)
Program memory
The resident program memory consists of 204a bytes. There are three particulary important locations in program memory:
1. Location 0:
Executing the initialization reset causes the first instruction to be fetched from location O.
2. Location 3:
Execution starts at location 3 after the interrupt input (pin 6) of the processor has gone
low (if interrupt is enabled).
3. Location 7:
A timer/counter interrupt resulting from timer/counter overflow (if enabled).
I
Program memory configurations
1. Internal 2 Kbyte ROM
- pin 9 is available as TO input
- port 4 serves only as I/O port
2. Internal 2 Kbyte ROM and additional, e"ternal 2 Kbyte ROM
- with external access, instruction words are read in via bus (data bus, DB).
- an SEL MBO or an SEL MB 1 instruction must be executed· before using the data bus
for external program store access.
- execution of SEL MB 1 instruction followed by CALL or JMP enables exceeding internal 2 Kbyte limits and accessing of external ROM.
- external program memory access causes loading of program counter bits pca
through PC 11 at port lines 40 to 43. pca through PC7 appear on bus during the failing edge of ALE.
- execution of MOVP3 A@A instruction causes internal ROM (bank 0) to be selected.
- internal ROM is automatically selected during every execution of an interrupt service routine.
- in second cycle of MOVX instruction no PSEN signal appears and RD or WR signal is
active. Port 4 is not affected.
3. External 4 Kbyte ROM, internal ROM disabled
- sole access to external 4 Kbyte ROM is initiated by logic 0 at pin a (RD/EA) during initialization time (RESET at low). Atthe machine cycle TS test logic calls up status from
pin S.
- pin 9 serves as PSEN output.
- program counter bits PCO through PC7 appear at DBO through DB7 and pca through
PC11 appear at port lines P40 through P43.
- execution of MOVP3 A.@ A instruction or interrupt routine selects automatically
lower 2 Kbytes of external ROM.
139
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
SAB 80C482
(SM 850)
4. Internal ROM verification without program execution
- pin 10 (WRNER) is tested at the machine cycle TS during the initialization time
(RESET at low). The low level at this pin forces the SAB SO C 482 to the verification
mode.
- contents of internal ROM appear on lines DBa through DB7
- program-counter bits pca through PC7 appear at DBa through DB7 and PCS
through PC11 at port lines P40 through P43.
- ALE and PSEN are enabled.
Reset
The reset signal sets the microcomputer to a defined initial state. There are two oossibiliii65 to reacn tnis state.
1. by an external signal at pin 4 (RESET)
2. by an internal signal generated through the built-in power-on-reset circuit.
If the oscillator is enabled (OSCEN at high), reset performs the following functions:
1. sets program counter to zero (PC = aOOH)
2. sets stack pointer to zero (SP = OOH)
3. selects register bank
4. selects memory bank a (internal ROM)
5. sets bus to high impedance state
(except when RD/EA or WRIVER is at low)
6. sets ports 1,4, 5, 6 to input mode
7. stops counter/timer
S. enables pin 9 as test input TO
9. disables interrupts
10. clears timer flag
11. releases HALT mode
12. does not affect internal RAM contents
Timing diagrams for power-on and external reset are shown in fig. a) and b).
a
140
SAB80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Figure a) Internal power-on reset
~OSCEN
+----Voo ....!.
SAB 80(482
......- - - Vss
I
..1Q.
Cycle
XTAL 2
OSC EN
RESET
pin
Internal
RESET
............nlU __ _
~'
~-----~------------------
~.
----I.L--.:.'WW~~~
iii
L
-OSC,,"lotor bUilt-up perlod--1
I
~
Supply voltage
rISe time
I-
.1
Initialization r@set
.,
Max. clock generator
neframlng time
141
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Figure b) External reset
.....---Voo
40 OSC EN
SAB 80 (482
T
~
Vss
41.______. .
Cyell
Res.t
Reset
i linstruction i l.instructlon
.
I
:
pc: 001
/1
~•
I
~-:------~--~--~--------------
RESET
pin
~*I-
---Oscillator Ouilt-up PtriOd1
: - - - . -.....-j
Supply voltage
nse time
*1 During this time-slot the Signal
at Reset-pin can change to Voo
without lengthening the Reset execulton
142
PC : 000
.......nnnnnn. __ _
XTAL 2
OSCEN
Sync.
-lniltalization res.t-...,
l-- --_.. --__
Max. clock generator
reframing time
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
SAB 80C482
(SM 850)
Interrupt
The SAB 80 C482 has the same interrupt logic as the SAB 8048. The interrupt can be initialized through two possible sources:
1. external low active signal at pin INT
2. overflow of the internal counter/timer.
Keyboard wake-up
The SAB 80 C 482 has a special on-chip circuitry for a convenient keyboard-scanning
named "Keyboard wake-up". Four NAND gates can be connected to the ports Pl 0-13,
P14-17, P50-53 and P60-63 by mask programming. The outputs of these gates are
interconnected in the NOR manner. The resulting output controls the release from the
HALT mode.
This means, the SAB 80 C 482 can be "waked up" on any keystroke without the necessity
of using a double contact keyboard.
HALT mode
After execution of the HALT instruction the processor enters the HALT mode where the
internal clocks and internal logic are disabled. The oscillator is running. In the HALT mode,
power consumption is about 1/3 of normal SAB 80 C482 operation.
HALT mode can be released in three different ways:
1. by low pulse on the RESET pin
(program starts at address location 0)
2. via keyboard wake-up
(program continues at address location PC+1)
3. by low pulse on the INT pin
(if interrupt is enabled the interrupt subroutine starting at the address location 3 is
executed. After its execution, or if interrupt is disabled, program continues at address
location PC+l.)
143
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
SAB 80C482
(SM 850)
Standby
Standby provides additional, drastic power consumption savings over the HALT mode.
Standby is initiated by forcing the OSCEN pin to low state. Oscillator operation is
discontinued. While in standby, the following data is maintained:
1. internal RAM
2. stack pointer
3. program counter
4. memory bank status
5. TO/PSEN status
6. 110 status on all ports
7. all internal logic states
It is possible, but not recommended, to put tne SAB 80 C482 on standby without regard
to the running program. Stopping at any time in the instruction cycle can result in an undef!~e~ ~'t~t~e. C~~eeq~:::":t~" :!;~ yd"w";SCiti:iJ tv ciitc,f 5 i.i2fnJuy uniy TrOm ine HALT state or It an
external reset signal is applied. The RES pin must be forced at least 2.5 cycles earlierto the
low level than the OSCEN pin.
If the SAB 80 C 482 has entered the standby from the HALT mode, it is still in the HALT
mode after the OSCEN pin has been forced high. In the second case, the RES pin has to be
held at least for the oscillator built-up period plus one cycle at low level after the OSCEN
pin has been forced high.
144
·Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
SAB 80C482
(SM 850)
Instruction set
There are five new instructions in addition to the SAB 8048 instruction set:
@RO
instruction code
DEC
CO
@ R1
instruction code
C1
DEC
@ RO, addr
OJNZ
EO
instruction code
@ R1, addr
OJNZ
instruction code
E1
HALT
instru~tion code
F3
The following
IN
MOVO
OUTL
MOVO
ENTO
JF1
CLR
ORL
ORLO
CPL
ANL
ANLO
CLR
CPL
JFO
MOV
MOV
SAB 8048 instructions are not available:
A, P2
instruction code
instruction code
A. P7
P2,A
instruction code
P7, A
instruction code
instruction code
CLK
addr
instruction code
FO
instruction code
P2, # data
instruction code
instruction code
P7.A
FO
instruction code
instruction code
P2. # data
instruction code
P7.A
F1
instruction code
instruction code
F1
addr
instruction code
instruction code
A. PSW
PSW, A
instruction code
OA
OF
3A
3F
75
76
85
8A
8F
95
I
~A
9F
AS
B5
B6
C7
07
The opcode of the following instruction has been changed:
JNI
addr
instruction code
66 (8048 = 86)
145
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Symbols and abbreviations
A
Accumulator
AC
Auxiliary carry
addr
An
Bb
Program memory address
Accumulator bit n
Bit designator b =. a to 7
BS
Bank switch
BUS
CY
Bus port
Carry
Clock
ClK
CNT
E'!~~t ~I)~r!te!'
data
a-Bit number or expression
OBF
Memory bank flipflop
Interrupt
PC
Program counter
Pp
Port designator p = 4 to 6
P1
PSW
Port 1
Program status word
Ri
Register designator i = O. 1
Register designator r = a to 7
Rr
SP
T
TF
Stack pointer
Timer
TO/T1
Test 0, test 1
X
Mnemonic for external RAM
Immedi'ate data prefix
*
TImer/counter flag
@
Indirect address prefix
(X)
((X))
Contents of X
Contents of location
addressed by (Xl
Is replaced by
....
+-
AND
OR
XOR
146
Is exchanged with
Logical AND operation
Logical OR operation
Logical EXOR operation
SAB 80C482
(SM 850)
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Mnemonic
Function
Description
Cycles
Accumulator and register move instructions
MOV A, Rr
(A) - (Rr)
Move register to
accumulator
F8-FF
1
1
MOV A. @ Ri
(A) - ((Ri))
Move data memory to
accumulator
FO-Fl
1
1
MOV A,
(A) - data
Move data to
accumulator
23
2
2
MOV Rr, A
(Rr) - (A)
Move accumulator to
register
A8-AF
1
1
MOV@ Ri, A
((Ri)) - (A)
Move accumulator to
data memory
AO-Al
1
1
(Rr) - data
Move data to register
BB-BF
2
2
((Ri)) - data
Move data to data
memory
BO-Bl
2
2
MOVX A, @ Ri
(A) - ((Ri))
Move external data to
accumulator
80-81
1
2
MOVX @ Ri, A
((Ri)) - (A)
Move accumulator to
external data memory
90-91
1
2
XCH A, Rr
(A)- (R)
Exchange register and
accumulator
28-2F
1
1
XCH A. @ Ri
(A) - ((Ri))
Exchange data
memory and
accumulator
20-21
1
1
XCHD A. @ RI
(AO-3) ((RiO-3))
Exchange nibble of
data memory and
accumulator
30-31
1
1
MOVP3 A. @A
save (PC)
(PCO-7) - (A)
(PC8-11) 011 B
(A) -((PC))
restore PC
Move data from
page 3 of program
memory to
accumulator
E3
1
2
MOVP A,.@A
save (PC)
(PCO-7) - (A)
(A) - ((PC))
restore PC
Move data from
current page of
program to
accumulator
A3
1
2
SWAP A
(A4-7) (AO-3)
Exchange accumulator 47
nibbles
1
1
MOV Rr,
I;
data
I;
MOV @ Ri,
data
I;
data
I
147
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Mnemonic
Function
Description
Cycles
Timer/counter move instructions
MOVA. T
(A)- (T)
Read counter/timer
into accumulator
42
1
1
T. A
(T) - (A)
load counter/timer
from accumulator
62
1
1
Move data at port 1 to
accumulator
09
1
2
Out~ut ar..r.umIlIAtt:'r 0~
39
1
~
MOV
Port move instructions
IN A. P1
(A) - (P1)
OUTl P1. A
(P11- (AI
*data
ORl P1. * data
...
port 1
(P1) (P1) AND data
Logical AND port 1
with data
99
2
2
(P1) (P1) OR data
logical OR port 1 with
data
89
2
2
IN A. BUS
(A) - (BUS)
Move data on bus to
accumulator
08
1
2
OUTl BUS. A
(BUS) - A
Output accumulator
on bus
02
1
2
ANl BUS.
data
(BUS) (BUS) AND
data
logical AND bus with
data
98
2
2
ORl BUS.
data
MOVD A. Pp
logical OR bus with
88
(BUS) (BUS) OR data data
(AO-3) - (Pp) Move data at port
OC-OE
(A4-7) - 0
4 - 6 to accumulator
·3C-3E
(Pp) - (AO-3) Output accumulator
on port 4 - 6
(Pp) - (AO-3) logical AND
9C-9E
AND (Pp)
accumulator with port
4-6
8C-8E
(Pp) - (AO-3) Logical OR
OR (Pp)
accumulator with port
4-6
2
2
1
2
1
2
1
2
1
2
ANl P1.
*
*
MOVD pp. A
ANlD Pp. A
ORlD pp. A
148
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Mnemonic
Function
SAB 80C482
(SM 850)
Description
Cycles
Arithmetic accumulator instructions
ADD A. Rr
(AI - (AI + IRrl Add register to
accumulator
S8-SF
AC
CY
1
1
(AI(AI+((Ril
Add data memory to
accumulator
SO-S1
1
1
(AI(AI+data
(A)(A)+(Rr)+
ICY)
Add data to
accumulator
03
AC
CY
AC
CY
2
2
Add register and carry
to accumulator
78-7F
AC
1
1
(A) (A) + IIRi)! +
(CY)
Add data memory and
carry to accumulator
70-71
AD
CY
1
1
ADDC A. # data
(AI- (AI+
data+ICY)
Add data and carry to
accumulator
13
AC
CY
2
2
INC A
(A) - (AI+ 1
Increment accumu·
lator by 1
17
1
1
DEC A
(AI- (AI-1
Decrement
accumulator by 1
07
1
1
Decimal adjust
accumulator
57
1
1
ADD A.
@
Ri
ADD A. # data
AD DC A. Rr
AD DC A.
@
Ri
DA A
CY
AC
CY
INC Rr
(Rr) - (Rr) + 1
Increment register
by 1
18-1F
,
DEC Rr
IRr) - (Rr)-1
Decrement register
by 1
C8-CF
1
,
,
DEC @ Ri
IIRi))((Ri)! + 1 .
Decrement dat:J
memory by 1
CO-C1
1
1
INC@ Ri
((Ri)) (IRi)! + 1
Increment data
memory by 1
10-11
1
1
DJNZ Rr. addr
IRr) - IRr) - 1
if (Rr)
0
IPCO-7)-addr
Decrement register
by 1 and jump if
register not zero
E8-EF
2
2
DJNZ @ Ri. addr
I(Ri)) (IRi)) - 1
if ((Ri)!
0
(PCO-7)-addr
EO-E1
Decrement data
memory by 1 and jump
if data memory is not
zero
2
2
Arithmetic register instructions
*
*
I
149
SAB80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Mnemonic
Function
Description
Logical accumulator and register instructions
(A)Logical AND
(A) AND (Rr)
accumulator with
register
(A)Logical AND
ANLA, @ Ri
(A) AND ((Ri)) accumulator with data
memory
(A)Logical AND
ANL A. data
(A) AND data
accumulator with data
(A)Logical OR
ORL A, Rr
(A) OR (Rr)
accumulator with
register
(A)ORL A, @ Ri
Logical OR
(A) OR ((Ri))
accumulator with
data memory
(A)Logical OR
ORL A, data
(A) OR data
accumulator with data
(A)Logical XOR
XRL A. Rr
(A) )(OR (Rr)
accumulator with
register
(A)Logical XOR
XRL A, @ Ri
(M XOR ((Ri)) accumulator with data
memory
(A)Logical XOR
XRL A, data
(A) XOR data
accumulator with data
(A) -0
Clear accumulator
CLR A
(A}-(A)
CPL A
Complement
accumulator
ANL A, Rr
*
*
*
150
58-SF
1
1
50-51
1
1
53
2
2
48-4F
1
1
40-41
1
1
43
2
2
DB-OF
1
1
00-D1
1
1
D3
2
2
27
1
1
37
1
1
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Mnemonic
Function
Description
Cycles
RL A
(An + 1) - (An)
Shift accumulator 1 bit
to left
E7
RLC A
(An + 1) - (An)
(CY) - (A7)
(AD) - (CY)
Shift accumulator 1 bit
to left through carry
F7
RRA
(An) - (An+1)
Shift accumulator 1 bit
to right
77
RRC A
(An) - (An + 1)
(CY) - (AD)
(A7) - (CY)
Shift accumulator 1 bit
to right through carry
67
CLR C
(CY) - 0
Clear carry bit
CPL C
(CY) - ('CY)
Complement carry bit
Rotate instructions
CY
CY
1
1
1
1
1
1
1
1
I
Flag instructions
151
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Mnemonic
Function
Branch instructions
(PCO,..7) addr 0-7
(PCS-l0) addr S-10
(PCll) - OaF
JMP addr
Description
Jump to address.
page 0
1
2
3
4
5
6
7
JMPP@ A
04
24
44·
64
84
A4
C4
E4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
B3
1
2
(PCO-7) tlAll
Jump to address
JC addr
if (CY) = 1
(PCO-7) - addr
Jump to address if
carry = 1
F6
2
2
JNC addr
if (CY)=O
(PCO-7) - addr
if (A) =0
(PCO- 7) - addr
Jump to address if
carry = 0
E6
2
2
Jump to address if
accumulator = 0
C6
2
2
JNZ addr
if (A) >0
(PCO-7) - addr
Jump to address if
accumulator> 0
96
2
2
JTO addr
ifTO = 1
(PCO-7) - addr
Jump to address if
TO is High
36
2
2
JNTO addr
ifTO=O
(PCO-7) - addr
if T1 = 1
(PCO-7) - addr
Jump to address if
TO is Low
26
2
2
Jump to address if
T1 is High
56
2
2
JNTl addr
if T1 = 0
(PCO- 7) - addr
Jump to address if
Tl is Low
46
2
2
JTF addr
if TF = 1
(PCO-7) - adar
(TF) - 0
if lNT = 0
(PCO-7) - addr
if (An) = 1
(PCO-7) - addr
Jump to address if
counter/timer
flag = 1
16
2
2
Jump to address if
interrupt input Low
66
2
2
Jump to address. n=O
if bit n of
1
2
accumulator = 1
3
4
12
32
2
2
2
2
2
5
6
82
7
F2
nAfinAn in
prl)~!,,~!,!,!
I
memory
JZ addr
JT1 addr
JNI addr
Jab addr
152
52
72
92
D2
TF
2
2
2
2
2
2
2
2
2
2
2
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Mnemonic
Function
Description
Subroutine instructions
CALL addr
Jump to
page 0
((SP)) (PCO-ll,
subroutine
1
PSW4-7)
2
(SP) - (SP) + 1
3
4
(PCO-l0) addr 0-10
5
(PCll) - OBF
6
7
14
34
54
74
94
B4
04
F4
2
2
2
2
2
2
2
2
RET
(SP) - (SP)-l
(PC) - ((SP))
Return without PSW
Restore
83
1
2
2
2
2
2
2
2
2
2
RETR
(SP) - (SP)-l
(PC) - ((SP))
(PSW4-7) ((SP))
Return with
PSW Restore
93
1
2
CY
AC
OBF
153
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Mnemonic
Function
Description
Cycles
Control instructions
STRTT
Start timer
55
1
1
STRT
CNT
Start counter
45
1
1
STOP
TCNT
Stop timer/counter
65
1
1
EN
TCNTI
Enable timer/
counter interrupt
25
1
1
DIS
TCNT!
Disable timer/
counter interrupt
35
1
1
I:naale external
interrupt
05
1
1
DIS I
Disable external
interrupt
15
1
1
SEL RBO
Seleet register bank 0
C5
BS
1
1
SEL RBl
Sel eet reg i ster ba n k 1
05
BS
1
1
SEL MBO
Select programmemory bank 0
E5
OBF
1
1
SEL MBl
Seleet programmemory bank 1
F5
OBF
1
1
NOP
No operation
00
1
1
HALT
HALT instruction
F3
1
1
cN
154
i
Telephone Controller
(Single-Chip 8-Bit CMOS Microcomputer)
SAB 80C482
(SM 850)
Maximum ratings
Ambient temperature under bias
Tomb
o to
70
°C
Storage temperature
Tstg
-55 to 125
°C
Supply voltage ref. to GND (Vss)
Voo
o to
V
Total power dissipation
P tat
1
W
-0.3 to Voo
V
All input and output voltages
DC characteristics
Tamb
=0
to 70°C; Voo
= 2.5 to
6 V; Vss
=0
V
Test conditions
L input voltage
(all except XTAll. XTAl2. ~)
l input voltage
(XTAL 1. XTAl2. ~)
H input voltage
(all except XTAL 1. XTAL2. ~
H input voltage
(XTAll. XTAl2. lrrSn
L output voltage
V'L
V,LI
V,LI
V,H
7
Voo
< 4.5
Min.
Typ.
0.75
V
-0.1
0.75
0.25
0.7x Voo
Voo
V
V
V
0.7x Voo
Voo
V
V
V,H ,
Max.
-0.1
VOL
IOL
= 1.0 mA
0.45
V
Vall
IOL
= 1.0 mA
0.45
V
VOH
IOH
= 1.0 rnA
0.75x Voo
V
H output voltage; low impedance
(all other outputs). high impedance
Input leakage current (Portl. 4. 5. 6)
Input leakage current (lfEID. T1)
Input leakage current
(TNT; pullup)
Input current XTAL
Output leakage current
(For bus and TO in
high-impedance states)
VOH '
VOH '
I'LP
I'LC
IOH
= 1 mA
= 1 IJA
0.75x Voo
0.75x Voo
V
V
IJA
IJA
IJA
IJA
IJA
IJA
Total supply current
100
(BUS. l1ri.
WR. J5"SEN. AU)
L output voltage
(all other outputs)
H output voltage
(BUS.
tID. WR. "P"SEN. AU)
IOH
IXT
V,N :5 V'L
Vss:5 V'N :5 Voo
V'N = Voo
V'N :5 V'L
Vss :5 V'N :5 Voo
IOL
V'N :5 V'L
I'L
-5
±1
+1
-5
±10
±1
1 MHz; 5 V
1.2
4.2
0.9
3 MHz; 5 V
HALT supply current
Power-down mode
Operation supply voltage
100
100
VOD
500 kHz;
1 MHz; 5
3 MHz; 5
500 kHz;
5V
5V
V
V
5V
550
250
1
2.5
1.4
mA
mA
mA
400
IJA
IJA
IJA
IJA
V
2
6
155
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
AC characteristics
T. mb = 0 to 70°C; Voo
CL = 40 pF
= 5 V;
Vss
= 0 V; 'osc =
3 MHz
Test conditions
ALE pulse width
Address set-up before ALE
Address hold from ALE
Control pulse width
lSS"EN
1W.WR
tLL
tAL
tLA
tcc
tcc
Data set-up before WR
Data hold after WR
tow
Cycle time
Data hold after tfI5
Instr. hold after "F'Srn
m5 to data in
lSS"EN to data in
Address set-up before WR
Address set-up to data
atm5
at lSS"EN
Address float to
m5
tcv
lSS"EN
WF{ to ALE
~toALE
ALE to m5
ADDRESS Time Port 4
156
two
tev = 2.66 I.I~
CL = 40 pF
Min.
Typ.
800
120
0
833
166
300
1300
1300
333
1333
1333
333
Max.
160
ns
ns
ns
ns
ns
ns
ns
300
1 2.66
tAW
2000
us
ns
ns
ns
ns
ns
tAD
tAD
3500
500
ns
ns
t Mc
"tAFC
166
140
tCA
tCA
tCA
0
ton
ton
t no
0
0
300
300
1200
300
t no
t AOO
333
166
333
1333
50
666
ns
ns
ns
ns
ns
ns
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
SAB 80C482
(SM 850)
Time parameters versus fesc
Symbol
Parameter
1/fesc
~s
tCY
8 t
~s
Read from external data memory
2.5 t
~s
~s
1.0 t
4.0 t
~s
~s
~s
3.5
t
10.5 t
~s
~s
Write into external data memory
tCA
tcc
two
tow
tAW
1.0
4.0
1.0
4.0
6.0
t
t
t
t
t
~s
~s
~s
~s
~s
Instruction fetch from external program memory
tAL
tCA
tLA
tcc
tOR
t RO
tAD
t AOD
t AFC
0.5 t
4.0 t
-
~s
~s
1.0 t
-
0.5
• 1.5
2.0
0.5
~s
~s
~s
t
t
t
t
~s
~s
~s
~s
157
SAB 80C482
(SM 850)
Telephone Controller
(Single·Chip 8·Bit CMOS Microcomputer)
Application example "Intelligent Telephone Set"
Line
interface
"-
SAB
80(482
I
~
Keyboard
Data
memory
SAB 81(50
1
LCD
controller
PSB 7510
Features of this telephone set
-
direct and indirect radialing
short dialing (10 memories)
auto dialing by special keys
babysitter function
LC-display control
electronic keylock
clock function
rate signaling
158
1 st cycle
[T5
I
T6 -
LnTYSTY9 fT2rnTT4TT!q
I.-r-l
ALE
Read
from
external
data
memory
,t..-------- -----
------1l I'LL+-,i I
---, I'm
--;X
----+,
ALE
tev - - - - -
1--------
Bus
I"
·1
.1
I
!
'
"u--l
4
I
tow
Data
X
Address
L
I
tRo - - - j ltoR
,
'[§).-----F+lp-at-in-g- - -
------------~~I
TI
Dr
ca
tel. \--
-----------.1
fAD - - _ .. _----
~
iii
II
Co
Floating
r--- tcc -
WR
I T7 I T8 I T9 I T 2 I n I
1--- tcc ---4
TIr-----A-d-dr-es-s--+,
I..
T6
1 st cycle
-,
RD
Bus
Write into
external
data
memory
2 nd cycle
cncs4
S"iD
CC"C
-::::J'
CPo
0::::1
iii
3
-S"O
CD
::0:(3
0=
en
~
0
(')
~
N
::::J'CD
coO
'::::I
tD-
s:~
0
en
s:
c:r
(3
n
0
3
two
-
r-
"C
Xr---FI+qa-ti-ng---
~
C
CD
.1
tAW
ALE
Instruction
fetch from
external
program
memory
PSEN
tOR
BusPort 4
U;
co
Floating
==x
Floating
-1
tAoo
r-
X'--I/-O----X A X
I.- H impedance --4.-- Llmpedance .1.
-Imation
if 110 intor-!is changed
1/0
110
L
!
Xr--I-/O-'¥'--A--X!/O
H impedance .....\.-L impedance - - -
--I
if 110 info~mation is changed
if 1/0 information isn't changed
~
_tD
en CO
s:o
coO
c.n'"
oco
-I\)
SAB 8086
16-Bit Microprocessor
SAB 8086·2
SAB 8086·1
SAB 8086
8 MHz
10 MHz
• Bit, Byte, Word, and Block Operations
.24 Operand Addressing Modes
• Clock Rate upto
10 MHz (SAB 8086·1)
.Compatible with Industry Standard 8086
• Direct Addressing Capability to
1 MByte of Memory
• Assembly Language Compatible with
SAB 8080 I SAB 8085
.14 Word, By 16·Bil Register Set with
Symrnetrica I Operations
.8· and 16·Bit Signed and Unsigned
Arithmetic in Binary or Decimal
Including Multiply and Divide
Figure 1.
Pin Diagram
"In plastic and ceramic package
Figure 2.
Pin Names
AD o- 15
Address/Data
Status
Interrupt Request
Clock
Oueue Status
Test for Busy
Ready
Chip Reset
Minimum/Maximum
Mode
Read
Request/Grant
Bus Lock
Memory/lO
50 - 2
INTR
CLK
OS'_l
TEST
READY
RESET
MN/MX
RD
RO/GTo_1
LOCK
M/TO
5 MHz
A'6-19
S 3-7
BHE
HOLD
HLDA
WR
DTIR
DEN
ALE
INTA
NMI
GND
Vee
SAB 8086 is a new generation, high performance
16·bit Microprocessor implemented in +5 Volts,
depletion load, N channel, silicon gate Siemens
MYMOS technology packaged in a 40 pin package.
It is 100 percent compatible with the industry
Address
Status
Bus High Enable
Hold
Hold Acknowledge
Write
Bus Driver Transmitl
Receive
Bus Driver Enable
Address Latch Enable
Interrupt Acknowledg e
Non·maskable
Interrupt
Ground
+5 Volts
standard 8086. With features like string handling,
16·bit arithmetic with multiply and divide it significantly increases system performance. It is highly
suited for multiprocessor applications in various
configu rations.
AG 8183
161
SAB 8086
Functional Pin Definition
The following pin function descriptions are for
SAB 8086 systems in either minimum or maximum
mode. The "Local Bus" in these descriptions is
Number
Symbol
Input (II
Output (01
2-16
39
AD o-AD'5
I/O
31S--3!3
A
Ie:
A;;/S~
C
the direct multiplexed bus interface connection
to the SAB 8086 (without regard to additional
bus buffersl.
Function
These lines constitute the time multiplexed memory I/O
address (T,I and data (T" T3, T41 bus. Ao is analogous to
BHE for the lower byte of the data bus, pins 0 7-0 •. It is
LOW during T, when a byte is to be transferred on the
lower portion of the bus in memory or I/O operations.
Eight-bit oriented devices tied to the lower half would
normally use A. to condition chip select functions. These
lines are active HIGH and float to 3-state OFF during
interrupt acknowledge and local bus "hold acknowledge".
UUI il'~ 11 Lile::te are {ne Tour most slgnltlcant address lines
for memory operations. During I/O operations these lines
are LOW. During memory and I/O operations, status
information is available on these lines during T" T 3, Twand
T4. The status of the interrupt enable FLAG bit (S 51 is
updated at the beginning of each CLK cycle.
A'7/S4 and A'6/S3 are encoded as follows:
A'8/ S 5
A'9/S6
A'7/ S 4
A'6/S 3
Characteristics
o (LOWI
0
1
0
1
Alternate Data
Stack
Code or None
Data
0
1 (HIGHI
1
S6 is 0
(LOWI
This information indicates which relocation register is
presently being used for data accessing.
These lines float to 3-state OFF during local bus "hold
acknowledge".
34
BHE/S 7
a
During T, the bus high enable signal (BHEI should be used
to enable data onto the most significant half of the data
bus, pins 0'5-08' Eight-bit oriented devices tied to the
upper half of the bus would normally use BHE to
condition chip select functions. BHE is LOW during T, for
read, write, and interrupt acknowledge cycles when a byte
is to be transferred bn the high portion of the bus.
The S 7 status information is available during T" T3, and T4.
The signal is active LOW, and floats to 3-state OFF in
"hold". It is LOW during T, for the first interrupt
acknowledge cycle.
32
RD
a
Read strobe indicates that the processor is performing a
memory or 1/0 read cycle, depending on the state of the
S, pin. This signal is used to read devices which reside on
the SAB 8086 local bus. RD is active LOW during T" T3 and
Tw of any read cycle, and is guaranteed to remain HIGH in
T, until the SAB 8086 local bus has floated.
This signal floats to 3-state OFF in "hold acknowledge".
162
SAB 8086
Number
Symbol
Input (I)
Output (0)
22
READY
I
READY is the acknowledgement from the addressed
memory or 1/0 device that it will complete the data
transfer. The RDY signal from memory 1/0 is synchronized
by the SAB 8284A Clock Generator to form READY. This
signal is active HIGH. The SAB 8086 READY input is not
synchronized.
Correct operation is not guaranteed if the setup and hold
times are not met.
18
INTR
I
Interrupt request is a level triggered input which is sampled
du ring the last clock cycle of each instruction to determine
if the processor should enter into an interrupt acknowledge
operation. A subroutine is vectored to via an interrupt
vector lookup table located in system memory. It can be
internally masked by software reseting the interrupt
enable bit. INTR is internally synchronized. This signal is
active HIGH.
23
ITSi
I
The TtST input is examined by the "Wait" instruction.
If the TtST input is lOW execution continues, otherwise
the processor waits in an "Idle" state. This input is
synchronized internally during each clock cycle on the
leading edge of ClK.
17
NMI
I
Non-maskable interrupt is an edge triggered input which
causes a type 2 interrupt. A subroutine is vectored to via
interrupt vector lookup table located in system memory.
NMI is not maskable internally by software. A transition
from a lOW to HIGH initiates the interrupt at the end of the
current instruction. This input is internally synchronized.
21
RESET
I
RESET causes the processor to immediately terminate its
present activity. The signal must be active HIGH for at least
four clock cycles. It restarts execution, as described in the
Instruction Set description, when RESET returns lOW.
RESET is internally synchronized.
19
ClK
I
The clock provides the basic timing for the processor and
bus controller. It is asymmetric with a 33% duty cycle to
provide optimized internal timing.
33
MN/"IViX
I
Minimum/Maximum: indicates what mode the processor
is to operate in. The two modes are discussed in the
following sections.
40
Vee
+5V (power supply)
1,20
GND
GND (ground)
Function
163
I
SAB 8086
The following pin function descriptions are for the
SAB 8086/8288 system in maximum mode (i. e.
MN/MX = GND). Only the pin functions which are
Number
Symbol
Input (I)
Output (0)
26-28
s"S;,S;
0
unique to maximum mode are described; all other
pin functions are as already described.
Function
These status lines are encoded as follows:
S,
S,
So
Characteristics
o (lOW)
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
0
0
0
1 (HIGH)
1
1
1
Status is active during T4, T" and T, and is returned to the
passive state (1,1,1) during T3 or during Tw when READY is
HIGH. This status is used by the SAB 8288 Bus Controller
to generate all memory and I/O access control signals.
Any change by S" S" or So during T4 is used to indicate
the beginning of a bus cycle, and the return to the passive
state in T3 or Tw is used to indicate the end of a bus cycle.
These signals float to 3-state OFF in "hold acknowledge".
30-31
RO/GTo, RO/GT,
I/O
The request/grant pins are used by other local bus
masters to force the processor to release the local bus at
the end of the processQi'.s current bus cycle. Each pin is
bidirectional with RO/GTo having higher priority than
RO/GT, . RO/GT has an internal pull-up resistor so may be
left unconnected. The request/grant sequence is as
follows (see Figure 14):
1. A pulse of 1 ClK wide from another local bus master
indicates a local bus request ("hold") to the SAB 8086
(pulse1).
2. During the CPU's next T4 or T, a pulse 1 ClK wide from
the SAB 8086 to the requesting master (pulse 2)
indicates that the SAB 8086 has allowed the local bus
to float and that it will enter the "hold acknowledge"
state at the next ClK. The CPU's bus interface unit is
disconnected logically from the local bus during "hold
acknowledge" .
3. A pulse 1 ClK wide from the requesting master indicates
to the SAB 8086 (pulse 3) that the "hold" request is
about to end and that the SAB 8086 can reclaim
the local bus at the next ClK.
Each master-master exchange of the local bus is a
sequence of 3 pulses. There must be one dead ClK cycle
after each bus exchange. Pulses are active lOW.
If the request is made while the CPU is performing a
memory cycle, it will release the local bus during T4 of the
cycle when all the following conditions are met:
1. Request occurs on or before T,.
2. Current cycle is not the low byte of a word (on an odd
address).
3. Current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
4. A locked instruction is not currently executing.
164
SAB 8086
Number
Symbol
Input (I)
Output (0)
29
lOCK
0
The lOCK output indicates that other system bus masters
are not to gain control of the system bus while LITCR: is
active lOW. The lOCK signal is activated by the "lOCK"
prefix instruction and remains active until the completion
of the next instruction. This signal is active lOW, and
floats to 3-state OFF in "hold acknowledge".
24-25
OS"OSo
0
OS, and OSo provide status to allow external tracking of
the internal SAB 8086 instruction queue.
Function
OS,
QS o
Characteristics
o (lOW)
0
1 (HIGH)
0
1
0
1
1
No Operation
First Byte of Op Code from Queu
Empty the Queue
Subsequent Byte from Oueue
The queue status is valid during the elK cycle after
which the queue operation is performed.
165
SAB 8086
The following pin function descriptions are for
the SAB 8086 minimum mode (i. e. MN/MX = Ved.
Only the pin functions which are unique to
minimum mode are described; all other pin
functions are as described before.
Number
Symbol
Input (I)
Output (0)
28
M/TO
0
This status line is logically equivalent to S, in the
maximum mode. It is used to <:!i§tinguish a memory
access from an 1/0 access. MilO becomes valid in the T4
preceding a bus cycle and remains valid-'!ntil the final
T4 of the cycle (M = HIGH, 10 = LOW). MilO floats to 3-state
OFF in local bus "hold acknowledge".
29
WR
0
Write strobe indicates that the processor is performing a
write m~mory or write 1/0 cycle, depending on the state of
the MilO signal. WR is active for T" T3 and Tw of any write
cycle. It is active LOW, and floats to 3-state OFF in local bus
"hold acknowlf>rI<]f>"
24
INTA
0
INTA is used as a read strobe for interrupt acknowledge
cycles. It is active LOW during T" T3 and Tw of each
interrupt acknowledge cycle.
25
ALE
0
Address latch enable is provided by the processor to
latch the address into the SAB 8282/SAB 8283 address
latch. It is a HIGH pulse active during T, of any bus cycle.
Note that ALE is never floated.
27
DT/R
0
Data transmitlreceive is needed in minimum system that
desires to use a SAB 8286/SAB 8287 data bus transceiver.
It is used to control the dir:§lction of data flow through the
transceiver. Logically DTIR is equivalent to S, in the
maximum mode, and its timing is the same as for MilO.
(T=HIGH, R=LOW). This signal floats to 3-state OFF in
local bus "hold acknowledge".
26
DEN
0
Data enable is provided as an output enable for the
SAB 8286/SAB 8287 in a minimum system which uses
the transceiver. DEN is active LOW during each memory
and 1/0 access and for INTA cycles. For a read or INTA
cycle it is active from the middle ofT, until the middle ofT4,
while for a write cycle.l!..l.§..active from the beginning of T,
until the middle of T4. DEN floats to 3-state OFF in local
bus "hold acknowledge".
30-31
HOLD
HLDA
I
0
HOLD indicates that another master is requesting a local
bus "hold". To be acknowledged, HOLD must be active
HIGH. The processor receiving the "hold" request will
issue HLDA (HIGH) as an acknowledgement in the middle
of T4 or T,. Simultaneous with the issuance of HLDA the
processor will float the local bus and control lines. After
HOl.D is detected as being LOW, the processor will lower
HLDA, and when the processor needs to run another cycle,
it will again drive the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system cannot otherwise
guarantee the setup time. The same rules as for RQIGT
apply regarding when the local bus will be released.
_.
166
Function
SAB 8086
Figure 3. Functional Block Diagram
Memory Interface
,-------
,----------------------------C-Bus
I
I BIU
I
I
I
I
I
I
I - - - - - i Instruction
I
I - - - - - i Stream
Byte
I - - - - - i Queue
I
I
I
I
I
I
I
IP
I
I
A-Bus_ __ _ _- L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
___
I
'-----~o:-------------.
AH
BH
BL
I
CH
Cl
I
I
I
I
I
I
~
----
EU
I
I
I
I
I
I
I
----------~
\--------
I
I
I
--------1
Control
System
I
I
I
1----------I
I
ss
os
I
I
I
I
I
CS
I
I
I
I
ES
I
I
I
AL
OH
OL
5P
BP
51
[01
Flags
L _____________________________________
I
~
167
SAB 8086
Figure 4. Memory Organization
1-r-----,1- FFFFFH
1
} Cod.
' ' "cO
I
XXXXOH
I
1
r
Stack Segment
+Of fset
1
1
I
Segment Register
File
CS
,>--
Data Segment
SS
OS
ES
1>-
1>---
- -
--
-
Functional Description
The internal functions ofthe SAB 8086 processor are
partitioned logically into two processing units. The
first is the Bus Interface Unit (BIU) and the second
is the Execution Unit (EU) as shown in the block
diagram of Figure 3.
The bus interface unit provides the functions related
to instruction fetching and queuing, operand fetch
and store, and address relocation. The overlap of
instruction pre-fetching provided by this unit serves
to increase processor performance through
improved bus bandwidth utilization. Up to 6 bytes
of the instruction stream can be queued while
waiting for decoding and execution.
The instruction stream queuing mechanism allows
the BIU to keep the memory utilized very efficiently.
Whenever there is space for at least 2 bytes in the
168
queue, the BIU will attempt a word fetch memory
cycle. This greatly reduces "dead time" on the
memory bus.
The execution unit receives pre-fetched instructions
from the BIU queue and provides un-relocated
operand addresses to the BIU. Memory operands
are passed through the BIU for processing by the EU,
which passes results to the BIU for storage.
The processor provides a 20-bit address to memory
which locates the byte being referenced. The
memory is logically organized as a linear array of
1 million bytes, addressed as OOOOO(H) to FFFFF(HI.
The memory can be further logically divided into
code, data, alternate data, and stack segments of
up to 64 Kbytes each, with each segment falling
on 16-byte boundaries. (See Figure 41
SAB 8086
Minimum and Maximum Modes
The requirements for supporting minimum and
maximum SAB 8086 systems are sufficiently
different that they cannot be done efficiently with
40 uniquely defined pins. Consequently, the
SAB 8086 is equipped with a strap pin (MN/MX)
which defines the system configuration.
The definition of a certain subset of the pins changes
dependent on the condition of the strap pin.
When MN/MX pin is strapped to GND, the SAB 8086
treats pins 24 through 31 in maximum mode. An
SAB 8288 bus controller interprets status information coded into So, s" S, to generate bus timing
and control signals.
When the MN/MX pin is strapped to Vee, the
SAB 8086 generates bus control signals itself on
pins 24 through 31, as shown in parentheses in
Figure 1.
Bus Operation
The SAB 8086 has a combined address and data bus
commonly referred to as a time multiplexed bus.
Each processor bus cycle consists of at least four
ClK cycles. These are referred to as T" T" T3 and T4
(see Figure 5). The address is emitted from the
processor during T, and data transfer occurs on the
bus during T3 and T 4 • T, is used primarily for changing
the direction of the bus during read operations.
In the event that a "NOT READY" indication is given
by the addressed device, "Wait" states (T w) are
inserted between T3 and T 4 • Each inserted "Wait"
state is of the same duration as a ClK cycle. Periods
can occur between SAB 8086 bus cycles. These are
referred to as "Idle" states (T;) or inactive ClK cycles.
The processor uses these cycles for internal
housekeeping.
Status bits 50, 5" and S; are used, in maximum
mode, by the bus controller to identify the type of
bus transaction according to the following table:
S,
S,
So
Characteristics
o (lOW)
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read 1/0
Write 1/0
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)
0
0
0
1 (HIGH)
1
1
1
Status bits S 3through S, are multiplexed with highorder address bits and the BHE signal, and are
therefore valid during T, through T 4 • S 3 and S 4
indicate which segment register (see Instruction
Set description) was used for this bus cycle in
forming the address, according to the following
table:
S4
S3
Characteristics
o (lOW)
0
0
1 (HIGH)
0
1
1
Alternate Data
(extra segment)
Stack
Code or None
Data
S 5 is a reflection of the PSW interrupt enable bit.
S 6 = 0 and S, is a spare status bit.
During T, of any bus cycle the ALE (Address latch
Enable) signal is emitted (by either the processor
or the SAB 8288 bus controller, depending on the
MN/MX strap). At the trailing edge of this pulse,
a valid address and certain status information for
the cycle may be latched.
169
SAB 8086
Figure 5. Basic System Timing
f----(4+NwAIT)= TCY - - - . . f - - - - - (4+N wA1T)= TCY - - - - - I
T1
I
T2
I
T3
I
TWAIT
I
T4
I
T1
T2
I
T3
I
TWAIT
I T4
elK
ALE
J\'--_______ n
-I.
-------~
---------
Goes Inactive In the State
. . _~" 'us. . .:t"'_p"': rI_or_t_o_T_4_ _ _
~
READY
READY
READY
WAIT
DT/R
170
~
WAIT
__'1L
\'----
SAB 8086
liD Addressing
System Components
In the SAB 8086, 1/0 operations can address up to
a maximum of 64 KilO byte registers or 32 KilO
word registers.
The 1/0 address appears in the same format as the
memory address on -bus lines A,s-A c. The address
lines A 19 -A'6 are zero in 1/0 operations.
The variable 1/0 instructions which use register OX
as a pointer have full address capability while the
direct 1/0 instructions directly address one or two
of the 256 1/0 byte locations in page 0 of the 1/0
address space.
Processors
SAB 8088 -100% Compatible CPU with SAB 8086
with 8-bit bus
SAB 8087
SAB 8089
- Numeric Data Processor. Coprocessor
to SAB 8086 and SAB 8088.
- Input I Output Processor.
Support Circuits
SAB
SAB
SAB
SAB
8282
8283
8284A
8286
Octal Latch
Octal Latch (Invertingl
Clock Generator and Driver
Octal Bus Transceiver
SAB
SAB
SAB
SAB
8287
8288
8289
8259A
Octal Bus Transceiver (Invertingl
Bus Controller
Bus Arbiter
Programmable Interrupt Controller
Typical Applications
SAB 8086 is a general purpose 16-bit microprocessor
which can be used for applications ranging from
process control to data processing. Figures 6 and 7
show typical system configurations for SAB 8086
familiy components.
171
SAB 8086
Figure 6. Minimum Mode SAB 8086 Typical System Configuration
o
CLK MN/MX
READY M / i O l - - - - - - - - - - RESET I N T A \ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . . ,
Ri5
-------------~----~---_r--;
WR\------------------~+_----__+------_+~
DT/R
SAE DEN
8086
--,
--l 1
11
CPU ALE 1--_-+1-+1_---1
AD0·AD15I/'--=~=c-~1
---:-1
I
I
I
~----LL-~c_--~.-------LL,
A'6- A19
SHE
SAB 2142
RAM (41
(2)
1Kx8
SAB 2716·2
PROM (21
12)
1Kx8
2Kx8
Peripheral
2Kx8
Figure 7. Maximum Mode SAB 8086 Typical System Configuration
vee
rD
SAB 2716·2
PROM (21
SAS 2142
RAM 14)
121
1Kx8
172
12)
1Kx8
2Kx8
2Kx8
Peripheral
SAB 8086
Instruction Set Summary
DATA TRANSFER
MOV = Move
76543210
76543210
76543210
76543210
data
data ifw=1
Register / memory to / from register
11 000 1 0 d w
1
Immediate to register/memory
11 1 0001 1 w
1 mod
Immediate to register
11 0 1 1 w reg
1
data
data if w= 1
Memory to accumulator
11 0 1 0 0 0 0 w
1
addr-Iow
addr-high
Accumulator to memory
[1 0 1000 1 w 1
addr-Iow
addr-high
Register/memory to segment register
11 000 1 1 1 0 Imod 0 reg rim
Segment register to register/memory
11 000 1 1 00 Imod 0 reg rim
PUSH
mod reg rim
0 0 0 rim
1
I
= Push:
Register/memory
11 1 1 1 1 1 1 1 Imod 1 1 0 rim
Register
101 01 0 reg
Segment register
1
a a a reg
11a
1
1
POP = Pop:
Register/memory
11 000 1 1 1 1 Imod 000 rim
Register
10 1 0 1 1 reg
1
Segment register
10 0 a reg 1 1 1
1
1
XCHG = Exchange:
Register/memory with register
11 0000 1 1 w Imod reg rim
Register with accumulator
11
a 01
0 reg
IN = Input from:
Fixed port
11110010wl
Variable port
11110110wl
port
173
SAB 8086
76543210
76543210
Fixed port
11110011wl
port
Variable port
11110111wl
XLAT = Translate byte to AL
111010111
LEA = Load EA to register
11 000 1 1 0 1 Imod reg rim
LOS = Load pointer to DS
11 10001 01 Imod reg rim
LES = Load pointer to ES
11 1 000 1 00 Imod reg rim
LAHF = Load AH with flags
110011111
SAHF = Store AH into flags
110 011110
PUSHF = Push flags
110011100
POPF =Pop flags
11001 1 101
OUT = Output to:
76543210
76543210
ARITHMETIC
ADD = Add:
Reg.!memory with register to either
I 000000 d wlmod reg rim
Immediate to registerlmemory
11 00000 s w Imod 000 rim
Immediate to accumulator
I 0 0 000 lOw I
I
data
data
Idata ifS:W=Oll
data ifw:2J
ADC = Add with carry:
Reg.!memory with register to either
10001 OOdw I mod reg rim
Immediate to registerlmemory
11 000005 W mod 0 1 0 rim I
Immediate to accumulator
I
000 1 0 lOw
I
I
data
INC = Increment:
Registerlmemory
11 1 1 1 1 1 1 w I mod 0 0 0 rim I
Register
101000reg
AAA = ASCII adjust for add
100110111
DAA = Decimal adjust for add
100100111
174
data
data if W= 1
Idata if s:w=Ol I
SAB 8086
SUB = Subtract:
76543210
76543210
Reg.lmemory and register to either
1001010 d wi mod reg rim I
Immediate from registerlmemory
1100000swl mod 1 a 1 r/ml
Immediate from accumulator
10010110wl
data
76543210
76543210
data
I data if s:w=Oll
data if W= 1
SBB = Subtract with borrow
Reg.lmemory and register to either
1000110dWI mod reg rim I
Immediate from registerlmemory
1100000swl mod 0 1 1 r/ml
Immediate from accumulator
10001110wl
data
data if W= 1
76543210
76543210
76543210
76543210
data
I data if s:w=Oll
DEC = Decrement:
Registerlmemory
11111111Wl mod 0 01 r/ml
Register
I 01001 reg
data
I data if s:w=Oll
I
1111011Wl mod all r/ml
NEG = Change sign
CMP = Compare:
Registerlmemory and register
001110dWI mod reg rim
Immediate with registerlmemory
100000swi mod 1 1 1 r/ml
Immediate with accumulator
001 1110 wi
AAS = ASCII adjust for subtract
001 1 1 1 1 1
DAS = Decimal adjust for subtract
I
data
data if W= 1
00101 1 1 1
MUL = Multiply lunsigned)
11 1 101 1 wi mod 1 00 r/ml
IMUL = Integer multiply ISigned)
1111011 wi mod 1 01 r/ml
AAM = ASCII adjust for multiply
110101001000010101
DIV = Divide lunsigned)
1111011 wi mod 1 1 0 r/ml
IDIV = Integer divide Isigned)
1 1 1 1 0 1 1 w I mod 1 1 1 r/ml
AAD = ASCII adjust for divide
1110101011000010101
CBW = Convert byte to word
1100110001
CWO = Convert word to double word
1100110011
175
SAB 8086
LOGIC
76543210
76543210
NOT = Invert
11 1 1 1 0 1 1 wi mod 0 1 0 rim
SHLISAL = Shift logicallarithmetic left
11 1 0 1 0 0 v W mod 1 0
76543210
76543210
I
SHR = Shift logical right
I
MffiJ
11 1 01 00 v W I mod 101 rim I
SAR = Shift arithmetic right
1110100VW
mod111r/ml
ROL = Rotate left
1110100VW
mOdooor/ml
ROR = Rotate rig ht
11 10100 v W mod 0 01 rim 1
RCL = Rotate through carry flag left
11 1 01 00 v W mod 0 1 0 rim 1
RCR = Rotate through carry right
11 10 l' 0 0 v W mod 01 1 rim 1
AND = And:
Reglmemory and register to either
1001000 d W 1 mod reg rim
Immediate to registerlmemory
11 OOOOOOw
Immediate to accumu lator
1 0 0 1 00 1 0 W 1
I mod
1 oor/ml
data
data
data if W= 1
1 data if W= 1
TEST = And function to flags, no result:
Registerlmemory and register
Immediate data and registerlmemory
Immediate data and accumulator
I
11 1 1 1 01 1 W I mod 000 rim I
data
11 01 0 1 00 w I
data
I data if W= 1
11 0000 1 0 W mod reg rim
data if w=1
OR = Or:
Reglmemory and register to either
1000010 d w 1 mod reg rim
Immediate to registerlmemory
11 OOOOOOw 1 modOO 1 rlml
data
Immediate to accumulator
10000 1 1 0 w
I
data if W= 1
data
data ifw=1
XOR = Exclusive or:
Reg.lmemory and register to either
1001 1 00 d w 1 mod reg rim
Immediate to registerlmemory
11 000000 w
Immediate to accumulator
176
I mod 1 10 rim 1 data
100 1 1 0 1 0 w I
data
data if W= 1
data if W= 1
SAB 8086
STRING MANIPULATION
REP
= Repeat
76543210
76543210
76543210
disp-Iow
disp-high
11 1 1 1001 z
MOVS
= Move b'fte/word
11010010wl
CMPS
= Compare byte/word
11010011 w I
SCAS
= Scan byte/word
11010111 w I
LODS
= Load byte/word to AL/ AX
11010110wl
STDS
= Store byte/word from ALIA
11010101wl
CQNTROL TRANSFER
CALL = Call:
Direct within segment
11 1 101000
Indirect within segment
11 1 1 1 1 1 1 1 Imod 0 1 0 rim I
Direct intersegment
110011010
Indirect intersegment
JMP
offset-low
offset-high
seg-Iow
seg-high
I
111111111 Imod 0 1 1 rim I
= Unconditional Jump:
Direct within segment
11 1101001
disp-Iow
Direct within segment short
111101011
disp
Indirect within segment
111111111 Imod 1 0 a rim
Direct intersegment
111 101010
Indirect intersegment
disp-high
offset-low
offset-high
seg-Iow
seg-high
111111111 Imod 1 01 rim
177
SAB 8086
RET = Return from CALL:
76543210
76543210
76543210
data-low
data-high
data-high
Within segment
1'1000011
Within seg. adding immed to SP
1"000010
Intersegment
11 100101 ,
Intersegment adding immediable to SP
11 1001010
data-low
JE/JZ = Jump on equal/zero
101110100
disp
101111100
disp
101111110
disp
101110010
disp
101110110
disp
JP/JPE = Jump on parity/parity even
101111010
disp
JO = Jump on overflow
101110000
disp
101 1 1 1000
disp
101 1 10101
disp
10 1 1 1 1 1 0 1
disp
10 1 1 1 1 1 1 1
disp
1011 1001 1
disp
101 1 101 1 1
disp
10 1 1 1 1 0 1 1
disp
101110001
dlsp
101 1 1 1001
disp
111100010
disp
111100001
disp
111100000
disp
111100011
disp
JLlJNGE
= Jump on less/not greater
JLE/JNG
= Jump on less or equal/not
JB/JNAE
= Jump on below/not above
or equal
greater
or equal
JBE/JNA = Jump on below or equal/
not above
JS
= Jump on sign
JNLlJGE
= Jump on not equal/not zero
= Jump on not less/greater
JNLE/JG
= Jump on not less or equal/
JNE/JNZ
or equal
greater
JNB/JAE
= Jump on not below/above
JNBE/JA
= Jump on not below or
or equal
equal/above
JNP/JPO
= Jump on not par/par odd
JNO = Jump on not overflow
JNS
= Jump on
LOOP
not sign
= Loop ex times
LOOPZ/LOOPE = Loop while zero/equal
LOOPNZ/LOOPNE
= Loop while not
zero/equal
JCXZ = Jump on
178
ex zero
l
I
I
SAB 8086
= Interrupt
76543210
76543210
Type specified
111001101
type
Type 3
111001100
INT
INTO
= Interrupt on overflow
11 1001 1 10
IRET
= Interrupt return
11 1001 1 1 1
PROCESSOR CONTROL
= Clear carry
CLC
= Complement carry
CMC
11 1 1 1 1 000
11 1 1'10101
STC
= Set Carry
11 1 1 1 1 001
CLD
= Clear direction
11 1 1 1 1 100
STO
= Set direction
11 1 1 1 1 1 0 1
CLI
= Clear interrupt
11 1 1 1 1010
STI
= Set interrupt
11 1 1 1 101 1
HLT
= Halt
WAIT
ESC
= Wait
= Escape (to external device)
LOCK
= Bus lock prefix
11 1 1 10100
11001 101 1
111011xxx Imod x x x rim
111110000
179
SAB 8086
Footnotes:
AL = 8-bit accumulator
AX = 16-bit accumulator
CX = Count register
DS = Data segment
ES = Extra segment
Above/below refers to unsigned value.
Greater = more positive;
Less = less positive (more negativel signed values
if d = 1 then "to" reg; if d = a then "from" reg
ifw = 1 then word instruction; ifw = a then byte
instruction
I a 0 1 reg 1 1 0 I
if mod = 11 then rim is treated as a REG field
if mod = 00 then DISP = 0*, disp-Iow and disp-high
REG is assigned according to the following table
~r~ eb~e~!
if mod
= 01
then DISP = disp-Iow sign-extended to
16-bits, disp high is absent
10 then DISP = disp-high: disp low
if mod
=
if rim = 000 then
if rim = 001 then
if rim = 010 then
if rim = all then
if rim = 100 then
if rim = 101 then
if rim = 110 then
if rim = 111 then
DISP follows 2nd
requiredl
EA = (BXI + (SII + DISP
EA = (BXI + (DII + DISP
EA = (BPI + (SII + DISP
EA = (BPI + (DII +DISP
EA = (SII + DISP
EA = (DII + DISP
EA = (BPI + DISP'
EA = (BXI + DISP
byte of instruction (before data if
'except if mod = 00 and rim = 110 then EA =
disp-high:disp-Iow.
180
if s:w = 01 then 16-bits of immediate data from
the operand
it s:w = 11 then an immediate data byte is sign
extended to form the 16-bit operand
if v = 0 then "count" = 1; if v = 1 then "count" in
(CLI
x = don't care
z is used far string primitives for comparsion with
ZF FLAG
SEGMENT OVERRIDE PREFIX
16-Bit (w= 1)
8-Bit (w=O)
Segment
000
001
010
all
100
101
110
111
000
001
010
all
100
101
110
111
00
01
10
11
AX
CX
DX
BX
SP
BP
SI
DI
AL
CL
DL
BL
AH
CH
DH
BH
E8
CS
88
DS
Instruction which reference the flag register file
as a 16-bit object use the symbol FLAGS to
represent the file:
FLAGS = X:X:X:X:(OF):(DFI:(IFI:(TFI:(SFI:(ZF):
X:(AFI:X:(PF) :X:(CFI
SAB 8086
Absolute maximum ratings
*)
Ambient Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground
Power Dissipation
o to 70°C
-65 to +150°C
-1.0 to + 7V
2.5 Watt
D.C. Characteristics
SAB 8086: TA = 0 to 70°C, Vee = 5 V ± 10%
SAB 8086-1/8086-2: TA = 0 to 70'C, Vee = 5V ± 5%
Limit Values
Symbol
Parameter
V"
Input Low Voltage
-0.5
+0.8
V'H
Input High Voltage
2.0
Vee+ 0.5
Val
Output Low Voltage
-
0.45
10l = 2.0 mA
VOH
Output High Voltage
2.4
-
10H = -400 f.lA
Icc
Power Supply Current
SAB 8086
SAB 8086-2
SAB 8086-1
III
Input Leakage Current
fco
Output Leakage Current
Min.
-
Max.
Units
Test Conditions
V
340
350
360
mA
±10
f.lA
TA = 25°C
OV,,; V,N :s Vee
0.45 V,,; VOUT ,,; Vee
Vel
Clock Input Low Voltage
-0.5
+0.6
VeH
Clock Input High Voltage
3.9
Vee +1.0
G'N
Capacitance of Input Buffer
(All input e~6J;t
ADo-AD", R /CIT)
-
15
G,O
Capacitance of I/O Buffer
(AD o-AD'5,OO/GT)
V
-
pF
Ic = 1 MHz
*) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
181
SAB 8086
A.C. Characteristics for SAB 8086/8086-2
SAB 8086: TA = 0 to 70'C, Vee = 5V ± 10%
SAB 8086-2: TA = 0 to 70'C, Vee = 5V ± 5%
Minimum Complexity System (Figures 8, 9, 12, 15)
Timing Requirements
Limit Values
Symbol
Parameter
Min.
Max.
Min.
Max.
TClCl
ClK Cycle Period
SAB 8086
200
500
125
500
TClCH
ClK low Time
118
TCHCl
ClK High Time
69
TCH1CH2 ClK Rise Time
SAB 8086
-
-
SAB 8086-2
Test
Units Conditions
-
68
44
10
-
TCl2Cl1
ClK Fall Time
TDVCl
Data in Setup Time
30
20
TClDX
Data in Hold Time
10
10
TR1VCl
RDY Setup Time into
SAB 8284A ') ')
35
35
TClR1X
RDY Hold Time into
SAB 8284A ') ')
0
TRYHCH
READY Setup Time into
SAB 8086
118
68
TCHRYX
READY Hold Time into
SAB 8086
30
20
TRYlCl
READY Inactive to ClK 3)
-8
-8
From 1.0 to 3.5V
10
From 3.5 to 1.OV
-
0
THVCH
HOLD Setup Time
35
20
TINVCH
INTR, NMI, TEST
Setup Time ')
30
15
TILIH
Input Rise Time
(Except ClK)
TIHll
Input Fall Time
(Except ClK)
20
-
ns
-
-
20
From 0.8 to 2.0V
12
From 2.0 to 0.8V
12
') Signal at SAB 8284A shown for reference only.
') Setup requirement for asynchronous signal only to guarantee recognition at next ClK.
3) Applies only to T, state. (8 ns into T3 )
182
SAB 8086
Timing Responses
Limit Values
SAB 8086-2
Symbol
Parameter
SAB 8086
TCLAV
Address Valid Delay
TCLAX
Address Hold Time
TCLAZ
Address Float Delay
TCLAX
80
TCLAX
50
TLHLL
ALE Width
TCLCH-20
-
TCLCH-l0
-
TCLLH
ALE Active Delay
Min.
10
Max.
110
-
Min.
10
Max.
60
r--
-
80
-85
50
r---
TCHLL
ALE Inactive Delay
TLLAX
Address Hold Time to
ALE Inactive
TCLDV
Data Valid Delay
TCHDX
Data Hold Time
TWHDX
Data Hold Time After WR
TCVCTV
Control Active Delay 1
TCHCTV
Control Active Delay 2
TCVCTX
Control Inactive Delay
TAZRL
Address Float to
READ Active
TCLRL
RD Active Delay
TCLRH
RD Inactive Delay
TRHAV
RD Inactive to Next
Address Active
TCLCL-45
-
TCLCL-40
-
TCLHAV
HLDA Valid Delay
10
160
10
100
TCHCL-l0
-
10
-
110
Test
Units Conditions
55
TCHCL-l0
-
10
r--
60
ns
TCLCH-30
TCLCH-30
CL = 20-100 pF
for all SAB 8086
Outputs
(In addition to
SAB 8086
self-load)
70
10
110
10
r-60
r--70
0
-
10
-
165
0
10
150
TRLRH
RD Width
2TCLCL-75
TWLWH
WR Width
2TCLCL-60
TAVAL
Address Valid to ALE Low TCLCH-60
TOLOH
Output Rise Time
TOHOL
Output Fall Time
-
100
r--80
2TCLCL-50
-
2TCLCL-40
-
TCLCH-40
20
-12
20
From 0.8 to 2.0V
12
From 2.0 to 0.8V
-
183
SAB 8086
Max Mode System (Using SAB 8288 Bus Controller) (Figures 10-14)
Timing Requirements
Limit Values
Symbol
Parameter
Min.
Max.
Min.
Max.
TClCl
ClK Cycle Period
SAB 8086
200
500
125
500
TClCH
ClK low Time
118
68
TCHCl
ClK High Time
69
44
TCH1CH2 ClK Rise Time
SAB 8086
-
10
SAB 8086-2
-
TCL2Cll
ClK Fall Time
TDVCl
Data In Setup Time
30
20
TCLDX
Data In Hold Time
10
10
TR1VCl
RDY Setup Time into
SAB 8284A ') ')
35
35
TClR1X
RDY Hold Time into
SAB 8284A ') ')
0
TRYHCH
READY Setup Time into
SAB8086
118
68
TCHRYX
READY Hold Time into
SAB 8086
30
20
TRYlCl
READY Inactive to ClK 4)
-8
-8
TINVCH
Setup Time for
Recognition
(lNTR, NMI, TEST) ')
30
15
40
30
TGVCH
RO/GT Setup Time
TCHGX
RO Hold Time into
SAB 8086
TILIH
Input Rise Time
(Except ClK)
TIHll
Input Fall Time
(Except ClK)
Test
Units Conditions
-
From 1.0 to 3.5V
10
From 3.5 to 1.OV
ns
0
-
20
-
-
-
20
From 0.8 to 2.0V
12
From 2.0 to 0.8V
-
12
') Signal at SAB 8284A or SAB 8288 shown for reference only.
') Setup requirement for asynchronous signal only to guarantee recognition at next elK.
') Applies only to T, and wait states.
4) Applies only to T, state (8 ns into T,).
184
SAB 8086
Timing Responses
Limit Values
Symbol
Parameter
TClMl
Command Active Delay')
TClMH
Command Inactive Delay')
TRYHSH
READY Active to
Status Passive 3)
TCHSV
Status Active Delay
TClSH
Status Inactive Delay
TClAV
Address Valid Delay
TClAX
Address Hold Time
TClAZ
Address Float Delay
TSVlH
Status Valid to ALE High ')
TSVMCH
Status Valid to
MCE High')
TCllH
ClK low to ALE Valid ')
SAB8086
Min.
Max.
Min.
Max.
10
35
10
35
-
65
-
110
60
10
-
I---
130
10
110
-
70
r-60
r--
TClAX
80
TClAX
50
-
20
-
20
4
15
4
~5
TClMCH
ClK low to MCE High ')
TCHll
ALE Inactive Delay ')
TCLDV
Data Valid Delay
TCHDX
Data Hold Time
TCVNV
Control Active Delay ')
5
TCVNX
Control Inactive Delay')
10
')
')
3)
4)
Test
Units Conditions
SAB 8086-2
10
-
110
10
-
45
ns
Cl = 20-100 pF
for all SAB 8086
Outputs
(In addition to
SAB 8086
self-load)
60
I---
-
5
45
10
Signal at SAB 8284A or SAB 8288 shown for reference only.
Setup requirement for asynchronous signal only to guarantee recognition at next ClK.
Applies only to T3 and wait states.
Applies only to T, state (8 ns into T3)'
185
SAB 8086
Limit Values
Symboi
Parameter
TAZRL
Address Float to
READ Active
TCLRL
RD Active Delay
TCLRH
RD Inactive Delay
TRHAV
RD Inactive to Next
Address Active
TCHDTL
Direction Control
Active Delay ')
Min.
Max.
Min.
Max.
0
-
0
-
10
TCLCL-45
-
100
f80
TCLCL-40
-
50
r--- 30
ns
f30
TCLGL
GT Active Delay
GT Inactive Delay
TRLRH
RDWidth
TOLOH
Output Rise Time
TOHOL
Output Fall Time
0
85
0
50
2TCLCL-75
-
2TCLCL-50
-
20
r--- 12
20
From 0.8 to 2.0V
12
From 2.0 to 0.8V
r---
Signal at SAB 8284A or SAB 8288 shown for reference only.
Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
Applies only to T3 and wait states.
Applies only to T, state (8 ns into T3)'
186
CL = 20-100 pF
for all SAB 8086
Outputs
(In addition to
SAB 8086
self-load)
uetdY I
TCLGH
')
')
3)
4)
10
50
~ire~ti0r:.. C~Jnt\?1
IIld\,;lIve
165
r--150
-
TCHDTH
Test
Units Conditions
SAB 8086-2
SAB 8086
SAB 8086
A.C. Characteristics for SAB 8086-1
TA
= a to 70"C, Vee =
5V
± 5%
Minimum Complexity System (Figures 8, 9, 12, 15)
Timing Requirements (Preliminary)
Limit Values
Symbol
Parameter
Units
Min.
Max.
500
TClCl
ClK Cycle Period
100
TClCH
ClK low Time
53
TCHCl
ClK High Time
39
TCH1CH2
ClK Rise Time
TCl1Cl2
ClK Fall Time
TDVCl
Data in Setup Time
TClDX
Data in Hold Time
10
TR1VCl
ROY Setup Time into SAB 8284A')')
35
From 3.5 to 1.0V
ROY Hold Time into SAB 8284A')')
0
READY Setup Time into SAB 8086
53
TCHRYX
READY Hold Time into SAB 8086
20
TRYlCl
READY Inactive to ClK')
-10
THVCH
HOLD Setup Time
20
TINVCH
INTR, NMI, TEST Setup Time ')
15
Input Rise Time (Except ClK)
Input Fall Time (Except ClK)
From 1.0 to 3.5V
5
TClR1X
TILIH
-
10
TRYHCH
TllHll
Test
Conditions
-
ns
-
-
20
From 0.8 to 2.0V
12
From 2.0 to 0.8V
') Signal at SAB 8284A shown for reference only.
') Setup requirement for asynchronous signal only to guarantee recognition at next ClK.
') Applies only to T, state. (8 ns into T,)
187
SAB8086
Timing Responses SAB 8086-1 (Preliminary)
Limit Values
Symbol
Parameter
Units
Min.
TCLAV
Address Valid Delay
TCLAX
Address Hold Time
TCLAZ
Address Float Delay
TLHLL
ALE Width
TCLLH
ALE Active Delay
TCHLL
ALE Inactive Delay
TLLAX
Address Hold Time to ALE Inactive
iCLU'V'
Dena Vaiici u81ay
TCHDX
Data Hold Time
TWHDX
Data Hold Time After WR
TCVCTX
Control Active Delay 1
TCHCTV
Control Active Delay 2
TCVCTX
Control Inactive Delay
TAZRL
Address Float to READ Active
TCLRL
RD Active Delay
Max.
10
-
50
40
TCLCH-10
-
40
r---45
TCHCL-10
10
50
f----
TCLCH-25
50
i - ns
10
45
i-
TCLRH
RD Inactive Delay
TRHAV
RD Inactive to Next Address Active
50
0
10
-
Cl = 20 - 100 PF
for all SAB BOB6
Outputs
lin addition to
SAB BOB6
self-load)
70
I----
60
TCLCL-35
60
TCLHAV
HLDA Valid Delay
10
TRLRH
RDWidth
2TCLCL-40
TWLWH
WRWidth
2TCLCL-35
TAVAL
Address Valid to ALE Low
TCLCH-35
TOLOH
Output Rise Time
TOHOL
Output Fall Time
188
Test
Conditions
-
-
-
20
From O.B to 2.0V
12
From 2.0 to O.BV
SAB 8086
Max Mode System (Using SAB 8288 Bus Controller) (Figures 10-14)
Timing Requirements SAB 8086-1 (Preliminary)
Limit Values
Symbol
Parameter
Units
Min,
Max,
100
500
TClCl
ClK Cycle Period
TClCH
ClK low Time
53
TCHCl
ClK High Time
39
TCH1CH2
ClK Rise Time
TCl2Cl1
ClK Fall Time
TDVCl
Data In Setup Time
5
TClDX
Data In Hold Time
10
TR1VCl
ROY Setup Time into SAB 8284A')')
35
TClR1X
ROY Hold Time into SAB 8284A')')
0
TRYHCH
READY Setup Time into SAB 8086
53
TCHRYX
READY Hold Time into SAB 8086
20
TRYlCl
READY Inactive to ClK')
-10
TINVCH
Setup Time for Recognition
(INTR, NMI, TEST)')
15
-
Test
Conditions
-
-
From 1.0 to 3.5V
10
From 3.5 to 1,OV
TGVCH
RO/GT Setup Time
12
TCHGX
RO Hold Time into SAB 8086
20
TILIH
Input Rise Time (Except ClK)
TIHll
Input Fall Time (Except ClK)
-
ns
-
20
From 0,8 to 2.0V
12
From 2.0 to 0.8V
') Signal at SAB 8284A or SAB 8288 shown for reference only.
') Setup requirement for asynchronous signal only to guarantee recognition at next ClK,
') Applies only to T, state (8 ns into T,).
189
SAB 8086
Timing Responses SAB 8086-1 (Preliminary)
Limit Values
Symbol
Parameter
TCLML
Command Active Delay')
TCLMH
Command Inactive Delay')
TRYHSH
READY Active to Status Passive')
TCHSV
Status Active Delay
TCLSH
Status Inactive Delay
Units
Min.
Max.
10
35
-
45
55
TCLAV
Address Valid Delay
TCLAX
Address Hold Time
-
ILLAL
Address Hoat Delay
40
TSVLH
Status Valid to ALE High')
TSVMCH
Status Valid to MCE High')
TCLLH
CLK Low to ALE Valid')
TCLMCH
CLK Low to MCE High')
TCHLL
ALE Inactive Delay')
10
50
ns
-
20
4
15
TCLDV
Data Valid Delay
TCHDX
Data Hold Time
TCVNV
Control Active Delay')
5
TCVNX
Control Inactive Delay')
10
10
50
-
') Signal at SAB 8284A or SAB8288 shown for reference only.
') Applies only to T, and wait states.
190
Test
Conditions
45
CL = 20-100 pF
for all SAB 8086
Outputs
(In addition to
SAB 8086
self-load)
SAB 8086
Timing Responses SAB 8086-1 (continued)
(Preliminary)
Limit Values
Symbol
Parameter
TAZRL
Address Float to READ Active
TCLRL
RD Active Delay
TCLRH
RD Inactive Delay
TRHAV
RD Inactive to Next Address Active
TCHDTL
Direction Control Active Delay')
TCHDTH
Direction Control Inactive Delay')
TCLGL
GT Active Delay
tCLGH
GT Inactive Delay
TRLRH
RDWidth
TOLOH
Output Rise Time
TOHOL
Output Fall Time
Min.
Max.
0
-
10
Units
Test
Conditions
ns
CL = 20-100 pF
for all SAB 8086
Outputs
(In addition to
SAB 8086
self-load)
70
r-60
TCLCL-35
-
-
50
r-30
0
45
2TCLCL-40
-
-
20
From 0.8 to 2.0V
12
From 2.0 to 0.8V
r----
') Signal at SAB 8284A or SAB 8288 shown for reference only.
') Applies only to T3 and wait states.
191
SAB 8086
Figure 8. Bus Timing - Minimum Mode System
T,
T,
tCH1CH2
eLK
(SAB 8284A QUlpUI)
Itl
MliO
;::;;-;r:-",
UIIL'U7
A,9IS6·A,6IS3
ALE
I
ROY 4)
(SAB 8284A Inpul )
>l{
0-
;1]28
~g
m
""
. en
r
AD ' 5 -AD,
~
I
~:;-O
RD
~~
~I~
DTIR
DEN
192
AD,5-AD!
,-
SAB 8086
Figure 9. SAB 8086 Bus Timing - Minimum Mode System (cont'd)
T,
eLK
(SAB B1B4 Output)
MliO
BHEIS 7
A19IS6'A,6IS3 -.,---t----'
'-+--t-J '--+--------t---j-J ' - - - I-
I
ALE
(even:
I
§'
~ 1~.
il~
~
{AD15
-AO~ ___
+-fl~
Invalid
Address
__
__
_ _ ____ Software HALT
10"
ll~·
~~
') All signals switch between VOH and VOl unless otherwise specified.
') RDY is sampled near the end of T,. T 3 , Tw to determine if Tw machines states are to be· inserted.
3) Two INTA cycles run back to back. The SAB 8086 local ADDR/DATA Bus is floating during both INTA
cycles. Control signals shown for second INTA cycle.
4) Signals at SAB 8284A are shown for reference only.
5) All timing measurements are made at 1.5 V unless otherwise noted.
193
SAB8086
Figure 10. SAB 8086 Bus Timing - Maximum Mode System (Using SAB 8288)
OS,.QS,
-+_-+..J
5,:S, :s, ---It---t--+---+--+-+77T7;>lnnr+--+~---
(Except HAlTi
SHE,S,
A19 JSG -A'6 /S 3
---'1-'.'--;----+---' '-j--+----i---r---+---+___'
READY
(SAS 8OB6 Inpul I
READ CYCLE
~"~ IIOO~C
r":: ________----.
Oulp,ts
l
194
'--j----f---.,,--t-J
DEN _ _ _ _ _ _ _ _ _ _ _J
SAB 8086
Figure 11. SAB 8086 Bus Timing - Maximum Mode System (Using SAB 8288) (cant.)
TJ
T,
WRITE CYCLE
52.5, :S0 ------...,_--.---11
INTA
I
.... tkL~':
I'
r----.
/-
_"'~
OEN _ _ _ _ _~I
__
\';,---1_..t~~_"2.
Software HALT -
("Om, vo,' R5 MRDC,IORC.MWTC wwC.iOW;::,A"iQWC,INTA OT/R 'Vo" I
ADtS-A00
~
Invalid Address
---'t(~A"f--
S,S;:s,~
1
';----'-----
') All Signals switch between VOH and VOL unless otherwise specified.
') RDY is sampled near the end of T" T 3 , Tw to determine if Tw machines states are to be inserted.
3) Cascade address is valid between first and second INTA cycle.
4) Two INTA cycles run back-to-back. The SAB 8086 local ADDR/DATA Bus is floating during both INTA
cycles. Control for pointer address is shown for second INTA cycle.
5) Signals at SAB 8284A or SAB 8288 are shown for reference only.
6) The issuance of the SAB 8288 command and control signals (MRDC, MWTC, AMWC, IORC,
IOWC, AIOWC, INTA and DEN) lags the active HIGH SAB 8288 DEN.
7) All timing measurements are made at 1.5V unless otherwise noted.
B) Status inactive in state just prior to T4 •
195
SAB 8086
Figure 12. Asynchronous Signal Recognition
ClK
I:~~ }Si9
nal,....:_ - - - '
TEST
') Setup requirements for asynchronous signals only to guarantee recognition at next eLK
Figure 13. Bus Lock Signal Timing (Maximum Mode Only)
P
nY ClK Cycle----j
elK
LOCK
196
~
f-Any ClK Cycle----j
---~
-
' 'T---''"'
SAB 8086
Figure 14. Request/Grant Sequence Timing (Maximum Mode Only)
Any CLK Cycle ~0·CLK Cycle
ClK
AD15 -AD0
A19/S6-AI6/S3
52 :5 1 :5 0
PrevIous grant
~('_ _ _ _ _ _- - - - T
Coprocessor 1)'
SAB 8086
RD,lOCK
SHE,S?
') The coprocessor may not drive the buses outside the region shown without risking contention
Figure 15. Hold/Hold Acknowledge Timing (Minimum Mode Only)
~1
ClK Cycle
10r 2 Cycles
197
SAB 8088
8-Bit Microprocessor
SAB 8088
5 MHz
SAB 8088-2
8 MHz
.8 Bit Data Bus Interface
.24 Operand Addressing Modes
.16 Bit Internal Architecture
• Direct Addressing Capability to
1 MByte of Memory
.8-Bit and 16-Bit Signed and Unsigned Arithmetic
in Binary or Decimal, Including Multiply
and Divide
• Software Compatible with SAB 8086
• 14-Word by 16-Bit Register Set with
Symetrical Operations
• Two Clock Rates:
5 MHz for SAB 8088
8 MHz for SAB 8088-2
• Byte, Word, and Block Operations
• Compatible with Industry Standard 8088
,-----------------------------------------------------Pin Configuration
Pin Names
HI ~j
MOO[
'MAx
'1
, f',ODE
r
vee
A15
A16153
A17IS4
A~8iSS
A191Sfi
sso
(HIGH)
Rii
HOLD
(RQIGTOl
HLDA
ifilllGr1)
WR
(LOCK)
101M
[52)
OTIR
151)
DEN
(SOl
ALE
laso)
INTA
(OSl)
TEST
READY
RESEl
SAB 8088 is a high-performance 8-bit microprocessor implemented in + 5 volts, advanced
Siemens MYMOS technology, packaged in a 40-pin
package. It is 100 percent compatible with the
industry standard 8088. With features like string
ADO-7
50-2
INTR
ClK
QSO-l
TEST
READY
RESET
MN/MX
RD
RQ/GTO-1
lOCK
IO/M
A8-19
S3-6
SSO
HOLD
HlDA
WR
DTIR
DEN
ALE
INTA
NMI
VCC
GND
Address/Data
Status
Interrupt Request
Clock
Queue Status
Test for Busy
Ready
Chip Reset
Minimum/Maximum Mode
Read
Request/Grant
Bus lock
IO/Memory
Address
Status
Status (= SO)
Hold
Hold Acknowledge
Write
Bus Driver Transmit/Receive
Bus Driver Enable
Address latch Enable
Interrupt Acknowledge
Non-maskable Interrupt
+ 5 Volt
Ground
handling, 16-bit arithmetic with multiply and divide
it significantly increases system performance.
It is highly suited for multiprocessor applications in
various configurations.
AG 12/84
199
SAB 8088
Pin Definitions and Functions
The following pin function descriptions are for
SAB 8088 systems in either minimum or maximum
mode. The "local bus" in these descriptions is
the direct mUltiplexed bus interface connection
to the SAB 8088 (without regard to additional
bus buffers).
Symbol
Number
Input (I)
Output (0)
AD7-ADO
9-16
1/0
ADDRESS DATA BUS: These lines constitute the time multiplexed memory 1/0 address (Tl) and data (T2, n, Tw, and T4)
bus. These lines are active HIGH and float to 3-state OFF during
interrupt acknowledge and local bus "hold acknowledge".
A15-A8
39,2-8
0
ADDRESS BUS: These lines provide address bits 8 through 15
for the entire bus cycle (T1- T4). These lines do not have to be
latched by ALE to remain valid. A15-·A8 are active HIGH and
float to 3-state OFF during interrupt acknowledge and local bus
"hold acknowledqe".
0
ADRESS/STATUS: During T1, these are the four most significant address lines for memory operations. During 1/0
operations, these lines are LOW. During memory and 1/0
operations, status information is available on these lines
during T2, T3, Tw and T4. S6 is always low. The status of the
interrupt enable flag bit (S5) is updated at the beginning of
each clock cycle. S4 and S3 are encoded as shown.
A 19/56, A 18/S5, 34-38
A 17 IS4, A 16/S3
Function
S4
S3
Characteristics
a
a
a
Alternate Data
Stack
Code or None
Data
1
1
1
0
1
This information indicates which segment register is presently
being used for data accessing.
These lines float to 3-state OFF during local bus "hold
acknowledge" .
RD
32
0
READ: Read strobe indicates that the processor is performing
a m~mory or 1/0 read cycle, depending on the state of the
101M pin or S2. This signal i~sed to read devices which reside
on the SAB 8088 local bus. RD IS active LOW during T2, T3 and
Tw of any read cycle, and is guaranteed to remain HIGH in T2
until the SAB 8088 local bus has floated.
This signal floats to 3-state OFF in "hold acknowledge".
READY
22
I
READY: is the acknowledgement from the addressed memory
or 1/0 device that it will complete the data transfer. The RDY
signal from memory or 1/0 is synchronized by the SAB 8284AI
8284B clock generator to form READY. This signal is active
HIGH. The SAB 8088 READY input is not synchronized. Correct
operation is not guaranteed if the set up and hold times are not
met.
INTR
18
I
INTERRUPT REQUEST: is a level triggered input which is
sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt
acknowledge operation. A subroutine is vectored to via an
interrupt vector lookup table located in system memory. It can
be internally masked by software resetting the interrupt enable
bit. INTR is internally synchronized. This signal is active HIGH.
200
SAB 8088
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
TEST
23
I
TEST: input is examined by the "wait lor test" instruction. lithe
TEST input is lOW, execution continues, otherwise the
processor waits in an "idle" state. This input is synchronized
internally during each clock cycle on the leading edge 01 ClK.
NMI
17
I
NON-MASKABlE INTERRUPT: is an edge triggered input
which causes a type 2 interrupt. A subroutine is vectored to via
interrupt vector lookup table located in system memory.
NMI is not maskable internally by software. A transition
Irom a lOW to HIGH initiates the interrupt at the end 01 the
current instruction. This input is internally synchronized.
RESET
21
I
RESET: causes the processor to immediately terminate its
present activity. The signal must be active HIGH lor at least
four clock cycles. It restarts execution, as described in the
instruction set description, when RESET returns lOW.
RESET is internally synchronized.
ClK
19
I
CLOCK: provides the basic timing for the processor and bus
controller. It is asymmetric with a 33% duty cycle to provide
optimized internal timing.
VCC
40
-
POWERSUPPlY(+5V)
GND
1,20
-
GROUND (OV)
MNIMX
33
I
MINIMUM/MAXIMUM: indicates what mode the processor
is to operate in. The two modes are discussed in the following
sections.
Function
The following pin function descriptions are for the
SAB 8088 minimum mode (i.e. MN/MX =. VCC).
Only the pin functions which are unique to
-
minimum mode are described; all other pin
functions are as described above.
28
0
STATUS LINE: is an inverted maximum mode S;f. It is used to
distinguish a memory access from an 1/0 access. 101M
becomes valid in the T4 preceding a bus cycle and remains
vali.cJ. until the final T4 of the cycle (1/0 = HIGH, M = lOW).
101M floats to 3-state OFF in local bus "hold acknowledge"
WR
29
0
WRITE: strobe indicates that the processor is performing
a w!ite memDl'Lorwrite 1/0 cycle depending on the state of the
101M signal. WR IS active for T2, T3, and Tw of any write cycle.
It is active LOW, and floats to 3-state OFF in local bus "hold
acknowledge".
INTA
24
0
INTA: is used as a read strobe for interrupt acknowledge
cycles. It is active lOW during T2, T3, and Tw of each interrupt
acknowledge cycle.
101M
-
201
I
SAB 8088
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
ALE
25
0
ADDRESS ~ATCH ENABLE: is provided by the processor to
latch the address into the SAB 8282 /8282A/8283/8283A
address latch. It is a HIGH pulse active dUring clock low of
T1 of any bus cycle. Note that ALE IS Ilever floated.
DT/R
27
0
DATA TRANSMIT/RECEIVE: is needed in a minimum system
that desires to use an SAB 8286/8286A18287 /8287 A data bus
transceiver. It is used to control the direction of data flow
through the transceiver. Logically, DT;R is equivalent to S 1
in thf! mr\x;mllm mnr\p, ~nrl it~ ~ir::!~g is t~~ s:::!~c:::!~ fc:- ~C/~:~
(T = HIGH, R O~ LOW). This signal tloats to 3·state OFF in
local "hold acknowledge".
DEN
26
0
DATA ENABLE: is provided as an output enable for the
SAB 8286/8286A/ 82!lZ1.8.287A in a minimum system which
uses the transceiver. Dt.N~;'; active LOW during eilfh Illemory
and I/O access, and for INTA cycles. For a read or INTA cycle, it
is active from the middle of T2 until the middle of T4, while
for a write cyckj! is active from the beginning of T2 until the
middle of T4. DEN floats to 3·state OFF during local bus
"hold acknowledge".
HOLD, HLDA
31,30
I/O
HOLD: indicates that another master is requesting a local bus
"hold". To be acknowledged, HOLD must be active HIGH.
The processor receiving the "hold" request will issue HLDA
(HIGH) as an acknowledgement, in the middle of a T4 or T1
clock cycle. Simultaneous with the issuance of HLDA the
processor will float the local bus and control lines. After HOLD
is detected as being LOW, the processor lowers HLDA, and
when the processor needs to run another cycle, it will again
drive the local bus and control lines.
Hold IS not an asynchronous input. External synchronIZation
should be provided if the system cannot otherwise guarantee
the set up time.
SSO
34
0
STATUS LINE: is logically egtJiyalent,to SO in tlJe maximum
mode. The combination of SSO, 101M and DT/R allows the
system to completely decode the current bus cycle status.
Function
-
202
-
--
101M
DTIR
SSO
Cha racteristics
1
1
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
Interrupt Acknowledge
Read 1/0 Port
Write 1/0 Port
Halt
Code access
Read memory
Write memory
Passive
1
1
0
0
SAB 8088
Pin Definitions and Functions (continued)
The folloWlI1(J pill fllnction ciescriptions are for the
SAB 8088/8288 system in maxilllulll'mode (i.e.
MN/MX
GNDI. Only the pin functions which
Input (II
O,ltPUt (01
are unique to maximum mode are described.
All other pin functions are as described above.
Function
--.-.-.-.-+------f----+----------------------S2, S 1, SO
28
26
o
STATUS: is active during clock high ofT4, Tl, and T2, and is
returned to the passive state (1,1,1) during T3 or during Tw
when READY is HIGH. This status is used by the
SAB 8288/8288A bus controller to generate all memory and
110 access control signals. Any change by 52, S'l, or SO during
T4 is used to indicate the beginning of a bus cycle, and the
return to the passive state in T3 or Tw is used to indicate the
end of a bus cycle.
These signals float to 3-state OFF during "hold acknowledge".
During the first clock cycle after RESET becomes active,
these signals are active HIGH. After this first clock, they float
to 3-state OFF.
S2
51
SO
Ch aracteristics
a
a
0
a
a
a
a
1
0
1
1
1
1
1
0
0
0
1
1
0
Interrupt Acknowledge
Read 110 Port
Write I/O Port
Halt
Code access
Read memory
Write memory
Passive
1
1
1
1
--------------.~---+=============================~--R-O/GTO
31
REQUESTIGRANT: pins are lIsed by other local bus masters
I/O
RQ/tTl
30
I/O
to force the processor to release the local bus at the end of the
fJi()c_e~~or's current bus cycle. Each ~i,,-bidirectional with
RQ/GTO having higher priority than RQIGTl. RQIGT has an
internal pull-up resistor so may be left unconnected. The
requestlgrant sequence is as follows (See page 28):
1. A pulse of one ClK wide from another local bus master
indicates a local bus request ("hold") to the SAB 8088
(pulse 1).
2. During a T4 or T1 clock cycle, a pulse one clock wide from
the SAB 8088 to the requesting master (pulse 2), indicates
that the SAB 8088 has allowed the local bus to float and that
it will enter the "hold acknowledge" state at the next elK.
The CPU's bus interface unit is disconnected logically from
the local bus during "hold acknowledge", The same rules
as for HOLD/HOLDA apply as for when the bus is released.
3. A pulse one ClK wide from the requesting master indicates
to the SAB 8088 (pulse 3) that the "hold" request is
about to end and that the SAB 8088 can reclaim the local
bus at the next ClK. The CPU then enters T4.
Each master-master exchange of the local bus is a sequence of
three pulses. There must be one idle ClK cycle after each bus
exchange. Pulses are active lOW.
203
I
SAB 8088
Pin Definitions and Functions (continued)
Symbol
Number
Input II)
Output 10)
Function
If the request is made while the CPU is performing a memory
cycle, it will release the local bus during T4 of the cycle when all
the following conditions are met:
1. Request occurs on or before T2.
2. Current cycle is not the low byte of a word.
3. Current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the reouest is made the twn
possible events will follow:
1. local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four
rules for a currently active memory cycle apply with
condition number 1 already satisfied.
[ocR
29
0
lOCK: indicates that other systeQ1_bus masters are not to gain
control of the system bus while lOCK is active (lOW). The
lOCK signal is activated by the "lOCK" prefix instruction and
remains active until the completion of the next instruction.
This signal is active lOW, and floats to 3-state off in "hold
acknowledge".
OSl, QSO
24,25
a
QUEUE STATUS: provide status to allow external tracking of
the internal SAB 8088 instruction queue.
The queue status is valid during the ClK cycle after which the
queue operation is performed.
-
204
34
a
QSl
OSO
Characteristics
0
0
1
1
0
1
0
No operation
First Byte of opcade from queue
Empty the queue
Subsequent byte from queue
1
Pin 34 is always high in the maximum mode.
SAB 8088
Block Diagram
Memory Interlace
I
----~~s-----------------l
I
I BIU
I
I
I
I
.--------~
.
I
I
I
I
I
I
J
I
I
I
1
4
i
3
2
I
1
I
I
ES
I
I
instruction
Stream
Byte
Queue
I
I
I
I
I
I
I
I
cs
ss
---J-------lI
I
!
r---~~l
OS
Control
System
IP
I
I
______ -.J
f--------
I
I
I
I EU
I
I
I
A-Bus
--D
~
I
I
I
I
I
I
AH
AL
BH
BL
I
CH
CL
DH
OL
I
I
I
I
I
I
'
I
i
SP
BP
I
SI
I
01
I
I
IL ______________ _
205
I
SAB 8088
Functional Description
Memory Organization
The processor provides a 20-bit address to memory
which locates the byte being referenced. The
memory is organized as a linear array of up to
1 million bytes, addressed as OOOOO(H) to FFFFFIH).
The memory is logically divided into code, data,
extra data, and stack segments of up to 64 Kbytes
each, with each segment falling on 16-byte
boundaries.
All memory references are made relative to base
addresses contained in high speed segment
registers. The segment types were chosen based
on the addressing needs of programs. The segment
register to be selected is automatically chosen
~_c,~~~~~~g_ lothe rules of the following table. All
" "UIIIIClllUI, II' Ullt: ~t:Y"Jt:HIl lype snare tne same
logical attributes le.g. code or data). By structuring
memory into relocatable areas of similar characteristics and by automatically selecting segment
registers, programs are shorter, faster, and more
structured.
Word 116-bit) operands can be located on even or
odd address boundaries. For address and data
operands, the least significant byte of the word is
stored in the lower valued address location and the
most significant byte in the next higher address
location. The BIU will automatically execute two
fetch or write cycles for 16-bit operands.
Certain locations in memory are reserved for
specific CPU operations. Locations from addresses
FFFFOH trough FFFFFH are reserved for operations
including a jump to the initial system initialization
routine. Following RESET, the CPU will always
begin execution at location FFFFOH where the
jump must be located. Locations OOOOOH through
~?~!:~.~:~r_eserv~d.for i~te~r_uPt operations. Fourlo.Iy I~ tJUIII~t;;I;) .... vll;)r~Llrl~ UI d lo·un segment adaress
and a 16-bit offset address direct program flow to
one of the 256 possible interrupt service routines.
The pointer elements are assumed to have been
stored at their respective places in reserved
memory prior to the occurrence of interrupts.
1 FFFFFH
Memory Organization
I
t
CD
..,.
""
J
Segment
COde
j
XXXXOH
I
I
( Stack Segment
I
+Oftt
Segment Register
CS
File
Data Segment
r>-
SS
DS
ES
J
~.-
.·lD , " S~
Do<.
'(
206
f 0000flH
.."'
SAB 8088
Minimum and Maximum Modes
Bus Operation
The requirements for supporting minimum and
The SAB 8088 address/data bus IS broken Into three
parts - the lower eight address/data bits (ADO-AD7!.
the mldle eight address bits (AS-A 15), and the
upper four address bits (A 16-A 19). The addressl
data bits and the highest four address bits are
time multiplexed. ThiS technique prOVides the most
effiCient use of pins on the processor, permitting
the use of a standard 40 lead package. The middle
eight address bits are not multiplexed, I.e. they
remain vallrl through hout each bus cycle, In addition,
the bus can be demultlplexed at the processor With
a Single address latch if a standard, non-multiplexed
bus is deSired for the system.
maximum SAB 8088 systems are sufficiently
different that they cannot be done efficiently with
40 uniquely defined pins. Consequently, the
SAB 8088 IS equipped with a strap pill IMNIMX}
which defines the system configuration
The definition of a certain subset of the pins changes,
dependent on the condition of the strap pin.
When the MN/Mx pin is strapped to GND, the
SAB 8088 defines pins 24 through 31 and 34 ,n
maximum mode. When the MN/MX pin IS strapped
to VCC, the SAB 8088 generates bus control signals
itself on pins 24 through 31 and 34.
The minimum mode SAB 8088 can be used with
either a multiplexed or demultiplexed bus. The
multiplexed bus configuration is compatible with
the SAB 8085A multiplexed bus peripherals
(e.g. SAB 8155) and provides the user with a
minimum chip count system. ThiS architecture
provides the 8088 processing power in a highly
i nteg rated form.
The demultlplexed mode requires one latch (for
64K addressability) or two latches (for a full
megabyte of addressing). A third latch can be used
for buffering if the address bus loading requires It
An SAB 8286/8286A or SAB 8287!8287A transceiver can also be used if data bus buffering is
reqUired. The SAB 8088 prOVides DEN and DT/R
to control the transceiver, and ALE to latch the
addresses. This configuration of the minimum
mode provides the standard demultiplexed bus
structure with heavy bus buffering and relaxed bus
timing requirements.
The maximum mode employs the SAB 828818288A
bus controller. The SAB 8288/8288A decodes status
lines SO, :>1, and S2, and provides the system with
all bus control signals, Moving the bus control
to the SAB 8288/8288A provides better source and
sink current capability to the control lines, and
frees the SAB 8088 pins for extended large system
features. Hardware lock, queue status, and two
request/grant interfaces are provided by the
SAB 8088 in maximum mode, These features allow
co-processors in local bus and remote bus
configurations,
Each processor bus cycle consists of at least four
ClK cycles. These are referred to as T1, T2, T3 anei T4,
The address is emitted from the
processor dUring T1 and data transfer occurs on the
bus dUring T3 and T4. T2 IS used primarily for
changing the direction of the bus during rearl
operations, In the event that a "NOT READY"
indication IS given by the addressed device, "wait"
states (Tw) are Inserted between T3 and T4. Each
inserted "wait" state is of the same duration as a
elK cycle. Periods can occur between SAB 8088
driven bus cycles, These are referred to as
"idle" states (Ti), or inactive ClK cycles, The
processor uses these cycles for internal
housekeeping,
During T1 of any bus cycle, the ALE (address latch
enable) signal is emitted (by either the processor
or the SAB 8288/828SA bus controller, depending
on the MNIMX strap). At the trailing edge of this
pulse, a valid address and certain status information
for the cycle may be latched.
207
I
SAB 8088
Basic System Timing
---(4+N WAITHCY -----1
(4+N WAIT)'TCY--
I
T2 I
T3 ITWAIT I T4
T1
I T2 I T3
IT WAIT I
ClK
ALE
n
J\
'-----------------'
$2-S0
\I---_-=/0=W//$
IL
\'---_
Goes Inactive in the State
Prior to T4
~-----:>~~-----'
~just
Imll
\
ADDRI
STATUS
ADDR
ADDR.
DATA
I
i
READyi
READY
f
READY
-t;LJ---
(>-1--1
WAIT
DT/R
\I....-----J/
208
SAB 8088
Status bits SO, Sl, and S2 are used by the bus
controller, in maximum mode, to identify the type
of bus transaction according to the following table:
52
51
SO
Cha racteristics
OILOW)
a
a
a
1IHIGH)
1
1
1
0
a
1
1
a
0
1
1
0
1
a
1
a
1
a
1
Interrupt Acknowledge
Read I/O
Write I/O
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive Ino bus cycle)
Status bits S3 through S6 are multiplexed with highorder address bits and are therefore valid during
T2 through T4. S3 and S4 indicate which segment
register was used for this bus cycle in forming the
address according to the following table:
1/0 Addressing
In the SAB 8088, I/O operations can address up to
a maximum of 64 K I/O registers. The I/O address
appears in the same format as the memory address
on bus lines A15--AO. The address lines A 19-A16
are zero in I/O operations. The variable I/O
instructions, which use register DX as a pointer
have full address capability, while the direct I/O
instructions directly address one or two of the
256 I/O byte locations in page a of the I/O address
space. I/O ports are addressed in the same manner
as memory locations.
Designers familiar with the SAB 8085 or upgrading
an SAB 8085 design should note that the SAB 8085
addresses I/O with an 8-bit address on both halves
of the 16-bit address bus. The SAB 8088 uses a
full 16-bit address on its lower 16 address lines.
System Components
Support Circuits
S4
S3
Cha racteristics
alLOW)
a
a
1IHIGH)
1
0
Alternate Data
lextra segment)
Stack
Code or None
Data
SAB 8282/8282A Octa I Latch
SAB 8283/8283A Octal Latch Iinverting)
SAB 8284A/8284B Clock Generator and Driver
SAB 8286/8286A Octal Bus Transceiver
SAB 8287/8287 A Octal Bus Transceiver (Inverting)
SAB 8288/8288A Bus Controller
SAB 8289
Bus Arbiter
SAB 8259A
Programmable Interrupt Controller
S5 is a reflection of the PSW interrupt enable bit.
S6 is always equal to O.
Typical Applications
The SAB 8088 is a general purpose 8-bit microprocessor which can be used for applications
ranging from process control to data processing.
On page 12 are shown typical system
configurations for SAB 8088 familiy components.
209
I
SAB 8088
Minimum Mode SAB 8088 Typical System Configuration
CLK
MN/Mx -----oVC(
READY
,.-_ .... _-,
r
r
I
Walt
I
I
Stole
I
IO"H"
iW
RESET
we
-1"'
iNfA
- - - - --- ---t-+-~
SAS
!lCeB
l~::~o~J
CPU DT/R
BEN
!
---,
-----,
1
1
1
S18
ALE
BE
ADO-AD7
A8-A19
SA6
8282A
I
~--j - -
I--P--+---T;
Latch
I! ' i :
lUor31
INTR
I I
SAB
82S'JA
Interrupt
Control
- ----
INT
Maximum Mode SAB 8088 Typical System Configuration
..
CLK
MNIMx
Rf ADY
so
REET
51
Sl
-oGNO
CLK _
HRO(
MWTC
'-'
--~
--I
AMW(
lORe
,
;-t --
r-----'
r
[
WOII
I
Stote
r
I
I
l~::~o~J
I
SAS
806e
CPU
INT
SAB
8259A
Interrupt
Control
--- INT
210
I
I
~
:;
~
DATA TRANSFER
MOV = Move
76543210
76543210
76543210
I
Register / memory to / from register
~~~d~l~od
Immediate to register/memory
11100011wlm~dooor/ml
Immediate to register
11 0 1 1
W
reg
I
I
I
reg rIm
data If W=" 1
addr-Iow
addr-hlgh
Accumulator to memory
Register/memory to segment register
1100
Segment register to register/memory
11000 1 1 00 Imod 0 reg rIm
01 0
w
0 1w
addr-Iow
addr-hlgh
°1 110 ImOd 0 reg rIm I
I
PUSH == Push:
Register/memory
1'- 1 ~1 "
-;-i-Imod , ,
I
Register
10,010 reg
Segment register
1000reg 11 01
POP
=
°rim 1
~!!lmodOOorlm
Register
101011 leg
Segment register
1000reg 111
dalalfw='
OUT -:: Output to:
7654321D
76543210
76543210
Fixed port
11110011 w r--p~rt--l
Variable port
!
XLAT '" Translate byte to AL
t11010111
LEA
111 01 11
Ul
~
I:
LES ." Load pomter to ES
1'1000100 ImOdregrlm
LAHF
= Load
~
1010
-<
I
1'00111101
flags
I' 00 "
PUSHF "" Push flags
POPF =
3AI
~0111~11
AH wIth flags
Store AH
3
I
I~
ImOdre~
LOS == Load pOInter to DS
SAHF
o·~
Ul
1
I' 1000101
I:
:>
wi
~oo-~~egr/m
Load EA to register
=
76543210
, 00
!
POD f1aqs
1 00 11' 0 1
I
I
ARITHMETIC
ADD '-' Add.
Pop:
Register/memory
I
I
data
data
I, 0 1 0000
I," a
Memory to accumulator
76543210
!
Reg Imemorv wllh register TO eltt1er
LOOO.JOOd wlmOd reg
Immediate to reglster/rnemPTV
I, OOOOO~w
Immediate to aCcurnuldtor
lo-~oool~wl
r/~
ImodOOOrlm j
data
data
Idatalfs w-Ol
dalallw 1
ADC = Add with carrv
XCHG
~
Exchange:
Register/memory with register
Register with accumulator
IN
= Input from:
Fixed port
Variable port
~
r,
0000 11 w
110010 reg
I ~dr-e~~l
•
1
Reg Imemory with register to eltt>er
1000 '
Im~dr~~~J
Immediate to reglstpr,'memory
I~ OOOOOsw i';odO -,---o-;/mT
I
Immediate to accumulator
OOdw
i
000 1 0 lOw
I
data
Idata
data
data
I' W
L'C;
Wall
1
INC '---- Increment.
I - p~rt -- -I
1"10"0wl
1'11001 Ow
l111W{~OdOOO--;J~1
Register/memory
f11'
Register
!OlOOOreg
AAA :.- ASCII adJust for add
100 "01'1
DAA
100100, "
=
DeCimal adjust for add
-
en
l>
OJ
00
o
00
00
~
SUB - Subtract:
'"
Reg /mernory and rCfllster to either
Immediate from register/memory
Immedlilte from accumulator
SSB
76543210
76543210
76543210
I0010 1 0 d wI mod reg rim I
1'00000 S w I mod 0 rim I
data
I
data If W= 1
1
tOOl 0 1 10 w
1
data
76543210
Idata if S:W-,Oll
odwr~-:d---;~--;-/~l
Reg Imcmory and register to either
1000 11
Immediate from register/memory
[1oocioos~1 ~~-dOl-~;ffiJ- -da~a -ld~;aif-s:w=Oll
I
[0001110wl
data
76543210
76543210
DEC - Decrement:
76543210
76543210
1 1 0 1 00 v w
t
1 10100 v w
Imod 1 °1 rim!
SAR '--- Shift arithmetic Tight
l' 1 0 1 00 vw
j mod 1 1 1 rIm
ROl ---' Rotate left
1'101oovwlmOdOOOr/ml
ROR
datalfw-l I
76543210
-0
--=
ShIft logIcal Tight
Rotate right
(J)
76543210
»
OJ
t 1 1 1 101 1 w t mod 010 rim!
!
!
SHlISAl = ShIft logIcal/arIthmetic leh
SHR
Subtract with borrow
Immediate from accumulator
76543210
lOGIC
NOT'-' Invert
CO
mod 1 00 rim \
o
CO
CO
I
1,10l00vw!mOd001 r/m!
RCl -=- Rotate through carry flag left
1'10100vwlmod010r/ml
RCR = Rotate through carry nght
F
OOvw! modO 11 r/ml
76543210
AND = And:
Reglster/mernory
1'111111WI mOdOOlr/ml
Register
I 0. 1 001 reg I
NEG
eMP
ChClngc sign
F01~I~~
~~wl~Odre~r~~
~oooooo±~
Immediate to accumulator
I0 0 1 00 1 0 w !
00
1
rim!
I
data
data If w
data
,
~;ta:' w
,
I
1
!
I
Compare:
Register/memory and register
Immediate with register/memory
100111 Odwl
0!
AAS
ASCII adjust for subtract
DAS
Decimal adjust for subtract
100101 \ ' 1 t
MUl
Multiply (unsigned)
l'
IMUL
Integer multiply (signed)
AAM
ASCII adjust for multIply
00 1 1 1 1 0 w
00 1 1 1 1 1 1
I
!
data
<1
1011 wi mod 1 0' r/mj
,,010100 (00001010
, , , , 0 11 wi mod "
11,,01' wi mod 111 rim
Convert word to double word
11010101100001010
10011000
I
10011001 I
data
[data If S:W-01[
I
~~ ~dreq-r/~ 1
Immediate data and regIster/memory
~l~W]~dOOO~~T--da;;
-
[da;alfw
ImmedIate data and accumulator
I' 0 1 0 1 00 w !
1
I
-eo
data
I data
If w
Or:
J
Reg/memory and register to either
I000010dwlmOdr;~!~
Immediate to reglster/memory
!'00oooowlmOdOOlr/ml
data
Immediate to accumulator
(00001 lOw
I
data If w ,1
data
datalfw----:~-l
a r/ml
DIV -- DIVide (unsigned)
CBW _ Convert byte to word
And function to flags. no result
data If w= 1
IDIV - Integer diVide (signed)
AAD -= ASCI, adjust for diVide
=
Register/memory and regIster
OR
1 1 , 0 11 wi mod 1 a a
I" ,
TEST
mOd~~;~
0 000 s w[ mod 111 r/ml
I
!
Immediate with accumulator
cwo -
Reg/memory and register to either
Immediate to register/memory
I
I
XOR - Exclusive or"
Reg Imemory and register to either
F'
Immediate to register/memory
Uoooooow[m~dl-'0r/ml
Immediate to accumulator
!0011010wl
OOdwl
mOdregr/~
data
data
datalfw=l
dataifw=l
I
STRING MANIPULATION
REP
Repeat
76543210
j 11
1 100 I
1
MOVS
Move byte/word
['OI0010 W
CMPS
Compare byte/word
[1010011
seAS
Scan byte/word
[1010111 w
LODS
Load byte/word to ALIAX
STQS
Store byte/word from AL/ A
76543210
76543210
Foo~
Within seg adding Immed to SP
§o-o 010!
wi
l' 0 1 0 11 Ow 1
10 I 0 10 1w I
Direct Within segment
Indirect Within segment
1111"_1~~ l~o~~~r~J
JMP
J-d~;hl9hJ
1 1 0 I 0 [offset-law
El'l1 I
offset-high
seg-Iaw
se.9-h,gh
[mad 0 1 1 rim [
Unconditional Jump.
Direct wlthm segment
!
1 1 I 0 I 00 I
dlsp-Iaw
Direct wlthm segment short
[, , 1 0 1 0 1 1
dlsp
Indlre'-t Within segment
[I I 1 1 1 1 1 1 [mad 1 0
Direct Intersegment
[1 , 10 10 10
Indirect Intersegment
I,
dIS-P-~
~ ~~m-'
offset-low
offset-high
seg-Iow
seg-hlgh
I 1 I I 1 1 1 Imod 1 0 1 r/~
1
76543210
76543210
data-low
data high
°° I
1
11
Intersegment adding rmmedlable to SP
11F===~----~--~
100 1 °1 0 I data-low
data high
JE/JZ
101 1 10100
I
dlsp
10 1 1 1 1 1 0 0
I
dlsp
Jump on equal/zero
JL/JNGE
J -dl·;p-~o';
[
[, 1 0
Intersegment
I
f~ ,·10,000
Indirect Intersegmenl
76543210
[
!
rrn
Return from CALL.
I
CONTROL TRANSFER
CALL Call
Direct Intersegment
RET
Within segment
Jump on less/not greater
or equal
JLE/JNG ; Jump on less or equallnot
greater
El110!
dlsp
J8/JNAE
!
dlsp
0-
Jump on below/nol above
or equal
0 1 1 I 00 1
o!
I
JBEJJNA - Jump on below or equal!
not above
101110110
dlsp
JP/JPE -= Jump on parrty/pauty even
10 1 1 1 1 0 1 0
dlsp
JQ ,... Jump on overflow
101110000
dlsP
JS - Jump on sign
I0 1 1 1 1 000
dlsp
JNE/JNZ - Jump on nOI equal/not zero
101'.'°101
dlsp
JNL/JGE == Jump on not less/greater
Of eQual
tal 1 1 1 10'
dlsp
JNLE/JG -= Jump on nOT less or equal!
greater
tOIl 1 1 1 11
dlsp
JNB/JAE -= Jump on not below/above
or equal
10111001'
dlsp
JNBE/JA -= Jump on not below or
eQual/above
to 1 1 1 0 1 1 1
drsp
I
JNP/JPO -= Jump on nOT par/par odd
I
0 1 1 1 10 1 1
drsp
I
JNO "'- Jump on not overflow
10 1 1 1 000 I
dlsp
JNS =- Jump on not Sign
10 1 1 1 1 0 0 I
dlsp
111100010
dlsp
lOOP", Loop
ex times
LOOPZ/LOQPE '" Loop while zero/equal
111100001
dlsp
LOOPNZlLOOPNE '" Loop While not
zero/equal
111100000
dlsp
[11100011
drsp
JCXZ -= Jump on
ex zero
-----:l
I
I
I
I
J
I
I
I
I
I
en
l>
ttl
00
I\)
~
o
00
00
'"~
INT
16543210
Interrupt
INTO
IRET
----;y;;~
Lii~
Type 3
Interrupt on overfluw
interrupt return
en
Footnotes:
76543210
~Ol
Type specified
§01110!
AL
AX
ex
8·b!l accumulator
16-blt accumulator
Count register
OS
ES
Data segment
Extra segment
II s w
01 then 16-blts 01 Immediate data from
the operand
It sow
11 then an lfnmed,ate data byle IS sign
extended 10 form the 16-blt operand
If v
0 then "count"
1, If v
1 then "count" In
Above/below refers to unSigned value
~lOOl~iiJ
Greater
more positive,
Less
less positive (more negative) Signed va ues
If d
1 then "10" reg, Ii d
0 then "/rom" reg
Ifw
1 then word instruction, Ifw 0 then byll'
CMe
STC
Carry
ScI Carry
['11 10101
I
Clear direction
~;o-J
STO
Set direction
E~
Clear Interrupt
11
511
5e! Interrunl
F~
WAIT
ESC
LOCK
Walt
Escape (10 exle'fla: deVice)
Bus lock prt!!,,,
1 1 1 1010
II mud
If rllod
!
eLi
Halt
If mod
II mod
G~
ClO
HL T
don't care
IS used for stnng prImItIves for comparSlon WIth
ZF FLAG
SEGMENT OVERRIDE PREFIX
~oT1
Clear carry
ComplemenT
x
1
1001
~
l
~I~ 1{
~ I~' ~
~ 3. -c
~ I~ E
1--)
TCVCTX
- - - + - - - - - - - , . '-_ _ _ _
DEN
AD1-ADO
Invalid Address
---~~
1111''-----
-----J
Software HALT
'-::c:-:7,--------TeLAV
:::Iz-Ies
ow ....
VlOO
') All signals switch between VOH and VOL unless otherwise specified.
') RDY is sampled near the end of T2, T3, Tw to determine if Tw machines states are to be inserted.
3) Two INTA cycles run back to back. The SAB BOB810cai ADDR/DATA Bus is floating during both
INTA cycles. Control signals shown for second INTA cycle.
4) Signals at SAB 8284A/8284B are shown for reference only.
5) All timing measurements are made at 1.5V unless otherwise noted.
219
SAB 8088
Max Mode System (Using SAB 8288/8288A Bus Controller)
Timing Requirements
Limit Values
Symbol
Parameter
Min.
Max.
500
TClCl
ClK Cycle Period
200
TClCH
ClK low Time
118
TCHCl
ClK High Time
69
TCH1CH2 ClK Rise Time
TCl2Cl1
ClK Fall Time
TDVCl
Data In Setup Time
SAB 8088-2
SAB 8088
-
-
Min.
Max.
125
500
44
10
-
From 3.5to 1.0V
Data In Hold Time
10
10
RDY Setup Time into
SAB 8284A/8284B ') 2)
35
35
TClR1X
RDY Hold Time into
SAB 8284A/8284B ') ')
0
TRYHCH
READY Setup Time into
SAB 8088
118
68
TCHRYX
READY Hold Time into
SAB 8088
30
20
TRYlCl
READY Inactive to ClK 3)
-8
-8
TINVCH
Setup Time for
Recognition
(INTR, NMI, TEST) ')
30
15
40
30
RQ/GT Setup Time
RQ Hold Time into
SAB 8088
TILIH
Input Rise Time
(Except ClK)
TIHll
Input Fall Time
(Except ClK)
From1.0t03.5V
10
?n
30
TR1VCl
TGVCH
-
0
ns
-
-
20
20
From 0.8 to 2.0V
12
12
From 2.0 to 0.8V
-
') Signal at SAB 8284A/8284B or SAB 8288/8288A shown for reference only.
'I Setup requirement for asynchronous signal only to guarantee recognition at next ClK.
3) Applies only to T2 state (8 ns into T31.
220
Test
Condition
-
68
TClDX
TCHGX
Unit
SAB 8088
Timing Responses
------
limit Values
Symbol
Parameter
TClMl
Command Active Delay I I
TClMH
Command Inactive Delay· I
TRYHSH
READY Active to
Status Passive 'I
SAB 8088-2
SAB 8088
Min.
Max.
Min.
Max.
10
35
10
35
-
65
-
Test
Condit lOll
110
TCHSV
Status Active Delay
TClSH
Status Inactive Delay
TClAV
Address Valid Delay
60
f---
--_.
Unit
10
f---
130
f - - 10
70
f--
110
60
)---
TClAX
Address Hold Time
TClAZ
Address Float Delay
TSVlH
Status Valid to ALE High'l
TSVMCH
Status Valid to
MCE High 'I
TClAX
TCllH
ClK low to ALE Valid 'I
TClMCH
ClK low to MCE High "
TCHll
ALE Inactive Delay'l
TClDV
Data Valid Delay
TCHDX
Data Hold Time
TCVNV
Control Active Delay' I
TCVNX
Control Inactive Delay 'I
_.-
f--
-
-
80
TClAX
50
-
20
-
20
4
15
4
15
10
-- -_.
5
----10
-
110
10
-
45
ns
Cl 20 100 pF
for all SAB 8088
Outputs in
addition to the
internal loads
60
f---
5
45
10
'I Signal at SAB 8284A/8284B or SAB 8288/8288A shown for reference only.
21 Applies only to T2 state (8 ns into T31.
221
SAB 8088
Limit Values
Symbol
TAZRL
Parameter
SAB 8088
Address Float to
READ Active
TCLRL
AD Active Delay
TCLRH
_.
RD Inactive Delay
-
--
Direction Control
Active Delay ')
TCHDTH
Directi0r:...C?nt~?1
Min.
Max.
Min.
Max.
0
_.
0
.-
10
TCLCL-45
165
I--- 10
-
GT Active Delay
50
30
30
TRLRH
RDWldth
Output Rise Time
--_._"- -
------
--
-
-
85
50
Output ~all Time
2TCLCL· 75
-
--
20
2TCLCL - 50
f---- -
-
-
12
-----
'} Signal at SAB 8284Ai8284B or SAB 8288/8288A shown for reference only.
222
CL= 20- 100 pF
for all SAB 8088
Outputs In
addition to the
internal loads
Gf Inactive Delay
TOLOH
TOHOL
-
TCLCL - 40
I--TCLGL
-- TCLGH
100
80
I--
I
Test
Condition
---
50
--
HldLLlV~ U~ldy
Unit
150
TRHAV
AD Inactive to Next
Add ress Active
--rCHDTL
SAB 8088-2
20
I From 0.8 to 2.0V
12
From 2.0 to 0.8V
SAB 8088
Bus Timing - Maximum Mode System (Using SAB 8288/8288A)
VCH
CLK
VCL;
aso,aSl
-----1---'
52,51 ,so
----M---~-+---~-+__h~~~+_--~------
(Except HALTI
'------
\
A15-AB
A15-A8
TCHOX
A19/S6- A16/Sl
1c.illW '
I
51~
ALE
ISAB 8IB8/BI88A, _ _ _ _+-J
GLitput)
ROY
8184A/8284B,
l' ISAB
Input)
READY
{SAB B08B Inputl
I
READ CYCLE
rCLAV
AD )-AOO
~
I
_ _ _J
ICHOTL
OTiR
5,61
SAB 828818288A
Qutpu ts
MROC ---------------------..
or
IQRC
DEN
Notes see next page,
223
SAB 8088
Bus Timing - Maximum Mode System (Using SAB S2SS/S2SBA)
WRITE CYCLE
11
T1
14
13
INTACYCLE
Float
TCLOX
TDVCl,
POinter
AOI-ADO
I
: Float
I
r-
~-+f---------+-t--'I~C~HO~T'H-
I
5.SI
SAB
B1BB/B1SBA
Outputs
OTiR
INTA
19MfL
DEN
---i------~
Software HALT (DE N ,VOl i RQ,MRDC, IORC.MWT(, A"MW5, 1(jjj2,iJfJWC.INTA.DTIR 'VOH)
j
A07-ADO
A15 -AB
~
..
S2,S1,SO ~
V
Iova II d Address
Jj\
f-K1\clC'"L-;;~Y"---------/~-----------"\,- ___ _
') All Signals switch uetweeh VOH and VOL unless otherwise specified.
2) RDY is sampled near the end of T2, T3, Tw to determine if Tw machines states are to be inserted.
3) Cascade address is valid between first and second INTA cycle.
4) Two INTA cycles run back-to-back. The SAB 8088 local ADDR/DATA Bus is floating during both INTA
cycles. Control for pointer address is shown for second INTA cycle.
5) Signals at SAB 8284A/8284B or SAB 8288/8288A are shown for reference only.
6) The issuance of the SAB 8288/8288A command and control signals (MRDC, MWTC, AMWC, TORC,
IOWC, AIOWC, INTA and DEN) lags the active HIGH SAB 8288/8288A DEN.
') All timing measurements are made at 1.5 V unless otherwise noted.
8) Status inactive in state just prior to T4.
224
SAB 8088
Asynchronous Signal Recognition
I
'I
Setup requirements for asynchronous signals only to guarantee recognition at next elK
Bus Lock Signal Timing (Maximum Mode Onlyl
_IAny
ClK
CYC~~ _ _ h
ClK'~·
LOCKq:
rAny
ClK
CYCI~
L--I
-~
F
225
SAB 8088
Request/Grant Sequence Timing (Maximum Mode Only)
r- r--:
Any '::';LK Cycle >-:~-CU:'. Cycle
CLK~1Jb.
f-
---'>--TCLCL----,-jTCHGX
I
I
i- - _.
I
I
I
ROiGT
AD? -AD0
i
----I
r--;C;~!JI
i
Pulse 2
1
[
I
SAB 8088
I
I
lIT
I
I
I
_---j i- TCL~
' I
C
~,'- - - - - - - - - 1
SI,Sl S0
R15. LUCK
SAB 8088
Pulse I
~C~~~O~\~sr- __--.:
' -_ _---J
PrevlUUS grant
AI9iS5A16iS3
A1'l- A8
--j
-------1
~-----
U
'_,O~l, 0cessO f
\'§AB
r
8~}88
,~---------'
'1 The coprocessor may not drive the buses outside the region shovlin without risking contention
- - - ----------------
-------------1
Hold/Hold Acknowledge Timing (Minimum Mode Only)
I
I
A07 - ADO
A15- AS
A19156 -A 161S3
RD,IDIM.
DTlR, WR. DEN
226
I------.Jr,-
"
-\ !SAB'
' -_ _S_A_B_80_8_8--\,r--A--_ _ _C_o_p---'ro~~----.r'\~
SAB 8088
Input/Output Waveforms for A.C.-Tests
I
A.C. Testing: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0" The clock i's driven
at 4,3V and 0.25V. Timing measurements are made at 1.5V for both a logic
"1" and "0".
Load Circuit for A.C.-Tests
Device
under
Test
1
CL =100 PF
CL includes Jig Capacitance
227
§ffi\rB5 [8(Q)i ~(6)
~~~~ ~[(1)~®grra~~on
i ©~[E~~
~ij ~CG[/(Q)~trocessor
• Integrated Feature Set
-Enhanced SAB 8086-2 CPU
-Clock Generator
-2 Independent, High-Speed DMA Channels
-Programmable Interrupt Controller
-3 Programmable 16-bit Timers
-Programmable Memory and Peripheral
Chip-Select Logic
- Programmable Wait State Generator
-Local Bus Controller
• Direct Addressing Capability to
1 MByte of Memory
• Completely Object Code Compatible with
All Existing SAB 8086/8088 Software
-10 New Instruction Types
• Complete System Development Support
I
• Fully Compatible with Industry Standard 80186
• High Performance Processor
-2 Times the Performance of the
Standard SAB 8086
-4 MByte/Sec Bus Bandwidth Interface
SAB 80186 Block Diagram
INT31TNTAi
INT2IINTAO
CLKour
Vee
GND
TMR OUT 1
TMR OUT 0
-------,I
EXECUTION UNIT
16-B11
ALU
CLOCK
GENERATOR
I
I
I
I
I
I
I
I
PROGRAMMABLE
INTERRUPT
CONTROLLER
MAX COUNT
REGISTER 8
MAX COUNT
REGISTER A
CONTROL REGISTERS
I
I
_.J
. - - - - - f - DRQD
DRat
So-52
20·8iT
SOURCE POINTERS
ARDY
TEST
HOLD
HLDA
RES
RESET
20-B11
DESTINATION
POINTERS
16 BIT
TRANSFER COUNT
CONTROL
REGISTERS
AG 1/85
229
SAB 80188
High Integration
a-Bit Microprocessor
• Integrated Feature Set
-Enhanced SAB 8088·2 CPU
-Clock Generator
-2 Independent, High·Speed DMA Channels
-Programmable Interrupt Controller
-3 Programmable 16-bit Timers
-Programmable Memory and Peripheral
Chip·Select Logic
-Programmable Wait State Generator
-Local Bus Controller
• Completely Object Code Compatible with
All Existing SAB 8086/8088 Software
-10 New Instruction Types
• Direct Addressing Capability to 1 MByte
of Memory
• Complete System Development Support
• Fully Compatible with Industry Standard 80188
• 8·Bit Data Bus Interface; 16-Bit Internal
architecture
• High Performance 8 MHz Processor
-2 Times the Performance of the
Standard SAB 8088
-2 MByte/Sec Bus Bandwidth Interface
SAB 80188 Block Diagram
INT3/INTAl
INT2IINTAO
Cl KOUT
Vee
GND
-------,I
EXECUTION UNIT
I
16-81T
ALU
CLOCK
GENERATOR
I
I
I
I
I
PROGRAMMABLE
INTERRUPT
CONTROLLER
MAX COUNT
REGISTER A
I
I
CONTROL REGISTERS
I
I
_oJ
,--------11-- DRCO
SRDY
TEST
HOLD
REs
RESET
CONTROL
REGISTERS
PCS0-4
AG 1/85
231
I
SAB80286
High Performance
Microprocessor with Memory
Management and Protection
e High-Performance Processor
(up to Six Times the SAB 8086)
e Large Address Space:
- 16 Megabytes Physical
- 1 Gigabyte Virtual per Task
elntegrated Memory Management, Four-Level
Memory Protection and Support
for Virtual Memory and Operating Systems
Logic Symbol
RESET
READY
A23-AO
D15-DO
INTR NHI
)""
A23-AO
} Interrupt
Requests
015-00
Arbitration
B"
Interface
PEREa
PEACK
BUSY~
SHE
Address Bus
Data Bus
Bus Cycle Status
Bus High Enable
HOLD
HLDA
INTR
NMI
MIlO
MemoryllO Select
PEREO
51,So
from 5AB 82284
HlDA
e Full Hardware and Software Support
Pin Names
CLK
HOLD
eTwo SAB 8086 Upward-Compatible
Operating Modes:
- SAB 8086 Real Address Mode
- Protected Virtual Address Mode
e High Bandwidth Bus Interface
(8 Megabyte/s)
-SHE
M/iO
51
} Extension
p""""
--SO
Interface
(ODlrN'iA
ERROR
-- LOCK
VCC
Processor Extension
Operand Request
CODIINTA Codellnterrupt
Acknowledge
lOCK
Bus lock
ClK
RESET
READY
CAP
System Clock
System Reset
Bus Ready
Substrate Filter
Capacitor
vss
Bus Hold Request
Bus Hold Acknowledge
Interrupt Request
Non-Maskable Interrupt
Request
PEACK
Processor Extension
Operand Acknowledge
BUSY
ERROR
VCC
VSS
Processor Extension Busy
Processor Extension Error
Power supply (+5V)
Ground (OV)
CAP
The SAB 80286 is an advanced, high-performance
microprocessor with specially optimized capabilities for multiple user and multitasking systems.
The SAB 80286 has built-in memory protection that
supports operating system and task isolation as
well as program and data privacy within tasks. An
8 MHz SAB 80286 provides up to six times greater
throughput than the standard 5 MHz SAB 8086. The
SAB 80286 includes memory management capabilities that map up to 230 lone gigabyte) of virtual
address space per task into 224 bytes 116 megabytes)
of physical memory.
TheSAB 80286 is upward-compatible with SAB 80861
8088 software. Using SAB 8086 real address mode,
the SAB 80286 is object codecompatible with
existing SAB 8086/8088 software. In protected
virtual address mode, the SAB 80286 is source codecompatible with SAB 8086/8088 software and may
require upgrading to use virtual addresses supported
by SAB 80286's integrated memory management and protection mechanism. Both modes
operate at full SAB 80286 performance and execute
a superset of the SAB 8086/8088 instructions.
The SAB 80286 provides special operations to
support the efficient implementation and execution
of operating systems. For example, one instruction
can end execution of one task, save its state, switch
to a new task, load its state, and start execution of
the new task. The SAB 80286 also supports virtual
memory systems by providing a segment-notpresent exception and restartable instructions.
AG 3/85
233
SAB 80286
Pin Configuration
LCC package
Component pad view - as viewed from underside
of component when mounted on the board.
PC board view - as viewed from the component
side of the pc board.
U:..Jl..JLJ~JUUU:"JLJLJ:"JLJULJ:".L
n
CAP
ERROR
BUSY
N C
N (
_J
INTR
_J
N. (
NMI
.J
_J
V55
II
II
Pin No 1 Hark
Note: N.C. Pads must not be connected.
Pin grid array package
Bottom view
35
17
37
39
1S
13
~
"
43
9
45
7
U
5
Top view
~
3
S1
1
Pin No.1 Mark
234
SAB 80286
Pin Definitions and Functions
Symbol
Number
Input (II
Output (01
BHE
1
0
Function
BUS HIGH ENABLE indicates transfer of data on the upper byte of
the data bus D15-8. Eight-bit oriented devices assigned to the upper
byte of the data bus would normally use BHE to condition chip
select functions. BHE is active LOW and floats to Tri-state OFF
during bus hold acknowledge.
BHE and AO encodings
BHE value AO value Function
a
a
1
1
S1, SO
4,5
0
0
1
0
1
Word transfer
Byte transfer on upper half of data bus (D15-81
Byte transfer on lower half of data bus (D7-01
Reserved
BUS CYCLE STATUS indicates initiation of a bus cycle and, along
with MIlO and COD/INTA, defines the type of bus cycle. The bus
is in a Ts state whenever one or both are LOW, Sf and SO are
active LOWand floatto Tri-state OFF during bus hold acknowledge.
Bus cycle status definition
COD/INTA
MIlO
Sf
a (LOWI
a
a
a
a
a
0
a
0
0
a
1 (HIGHI
1
1
1
1
1
1
1
PEREO
PEACK
6
I
0
0
0
1
1
1
1
a
a
a
0
1
1
1
1
0
1
1
0
a
1
1
a
0
1
1
0
a
1
1
SO Bus cycle initiated
0
1
0
1
0
1
0
1
Interrupt acknowledge
Reserved
Reserved
None; not a status cycle
IF A 1 = 1 then halt; else shutdown
Memory data read
Memory data write
None; not a status cycle
a Reserved
1 1/0 read
0 1/0 write
1 None; not a status cycle
0 Reserved
1 Memory instruction read
0 Reserved
1 None; not a status cycle
PROCESSOR EXTENSION OPERAND REQUEST AND ACKNOWLEDGE extend the memory management and protection
capabilities of the SAB 80286 to processor extensions. The PEREQ
input requests the SAB 80286 to perform a data operand transfer
for a processor extension. The PEACK output signals the processor
extension when the requested operand is being transferred.
PEREQ is active HIGH and floats to Tri-state OFF during bus hold
acknowledge. PEACK may be asynchronous to the system clock.
PEACK is active LOW.
235
I
SAB 80286
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
A23-AO
7-34
0
ADDRESS BUS outputs physical memory and 1/0 port addresses.
AO is LOW when data is to be transferred on pins 07-0. A23-A 10
are LOW during 1/0 transfers. The address bus is active HIGH and
floats to Tri-state OFF during bus hold acknowledge.
RESET
29
I
SYSTEM RESET clears the internal logic of the SAB 80286 and is
active HIGH. The SAB 80286 may be reinitialized at anytime a lOW
to HIGH transition on RESET which remains active for more than
16 system clock cycles. During RESET active, the output pins of the
SAB 80286 enter the state shown below:
Function
I
Pin state during reset
I
Pin value
Pin names
1 (HIGH)
SO, 51, PEACK, A23-AO, BHE, LOCK
MIlO, COD/INTA, HLDA
015- DO
o (lOW)
Tri-state OFF
I
Operation of the SAB 80286 begins after a HIGH to LOW transition
on RESET. The HIGH to LOW transition of RESET must be
synchronous to the system clock. Approximately 50 system clock
cycles are required by the SAB 80286 for internal initializations
before performing the first bus cycle to fetch code from the poweron execution address.
A LOW to HIGH transition 'of RESET synchronous to the system
clock will end a processor cycle at the second HIGH to LOW transition of the system clock. The LOW to HIGH transition of RESET
may be asynchronous to the system clock; however, in this case it
cannot be predetermined which phase of the processor clock will
occur during the next system clock period. Synchronous LOW to
HIGH transitions of RESET are required only for systems where the
processor clock must be phase-synchronous to another clock.
CLK
31
I
SYSTEM CLOCK provides the fundamental timing for SAB 80286
systems. It is divided by two (inside the SAB 80286) to generate the
processor clock. The internal divide-by-two circuitry can be
synchronized to an external clock generator by a LOW to HIGH
transition on the RESET input.
015-00
36-51
I
0
DATA BUS inputs data during memory, 1/0, and interrupt acknowledge read cycles: outputs data during memory and 1/0 write
cycles. The data bus is active HIGH and floats to Tri-state OFF
during bus hold acknowledge.
BUSY
ERROR
53,54
I
I
PROCESSOR EXTENSION BUSY AND ERROR indicate the operating
condition of a processor extension to the SAB 80286. An active
BUSY input stops theSAB 80286 program execution on WAIT and
some ESC instructions until BUSY becomes inactive (HIGH). The
SAB 80286 may be interrupt while waiting for BUSY to become inactive. An active ERROR input causes the SAB 80286 to perform a
processor extension interrupted when executing WAIT or some
ESC instructions. These inputs are active LOW and may be
asynchronous to the system clock.
236
SAB 80286
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
INTR
57
I
INTERRUPT REQUEST requests the SAB 80286 to suspend its
current program execution and service a pending external request.
Interrupt requests are masked whenever the interrupt enable bit in
the flag word is cleared. When the SAB 80286 responds to an
interrupt request, it performs two interrupt acknowledge bus
cycles to read an 8-bit interrupt vector that identifies the source of
the interrupt. To assure program interruption, INTR must remain
active until the first interrupt acknowledge cycle is completed.INTR
is sampled at the beginning of each processor cycle and must be
active HIGH at least two processor cycles before the current
instruction ends in order to interrupt before the next instruction.
INTR is level sensitive, active HIGH, and may be asynchronous to
the system clock.
NMI
59
I
NON-MASKABLE INTERRUPT REQUEST interrupts the SAB 80286
with an internally supplied vector value of 2. No interrupt acknowledge cycles are performed. The interrupt enable bit in the
SAB 80286 flag word does not affect this input. The NMI input is
active HIGH, may be asynchronous to the system clock, and is
edge-triggered after internal synchronization. For proper
recognition, the input must have been previously LOW for at least
four system clock cycles and remain HIGH for at least four system
clock cycles.
READY
63
I
BUS READY terminates a bus cycle. Bus cycles are extended without limit until terminated by READY LOW. READY is an active LOW
synchronous input requiring setup and hold times relative to the
system clock be met for correct operation. READY is ignored during
bus hold acknowledge.
HOLD
HLDA
64
65
I
BUS HOLD REQUEST AND HOLD ACKNOWLEDGE control ownership of the SAB 80286 local bus. The HOLD input allows another
local bus master to request control of the local bus. When control
is granted, the SAB 80286 will float its bus drivers to Tri-state OFF
and then activate HLDA, thus entering the bus hold acknowledge
condition. The local bus will remain granted to the requesting
master until HOLD becomes inactive which results in the
SAB 80286 deactivating HLDA and regaining control ofthe local
bus. This terminates the bus hold acknowledge condition, HOLD
may be asynchronous to the system clock. These signals are
active HIGH.
COD/INTA
66
0
CODE/INTERRUPT ACKNOWLEDGE distinguishes instruction
fetch cycles from memory data read cycles.
Also distinguishes interrupt acknowledge cycles from I/O cycles.
COD/INTA floats to Tri-state OFF during bus hold aCknowledge.
M/JO
67
0
MEMORY I/O SELECT distinguishes memory access from I/O
access. If HIGH during Ts, a memory cycle or a halt/shutdown
cycle is in progress. If LOW, an I/O cycle or an interrupt acknowledge cycle is in progress M/ID floats to Tri-state OFF during bus
hold acknowledge.
0
Function
I
237
SAB 80286
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
lOCK
68
a
BUS lOCK indicates that other system bus masters are not to
gain control of the system bus following the current bus cycle.
The lOCK signal may be activated explicitly by the "lOCK"
instruction prefix or automatically by SAB 80286 hardware during
memory XCHG instructions, interrupt acknowledge, or descriptor
table access. lOCK is active lOW and floats to Tri-state OFF
during bus hold acknowledge.
VCC
30,62
-
POWER SUPPLY (+5V)
VSS
9,35,60
-
GROUND (OVI
CAP
52
I
SUBSTRATE FilTER CAPACITOR: a 0,047 lIf ±20% 12V canar.itnr
must be connected between this pin and ground. This capacitor
filters the output of the internal substrate bias generator.
A maximum dc leakage current of 1 I'a is allowed through the
capacitor.
For correct operation of the SAB 80286 the substrate bias
generator must charge this capacitor to its operating voltage.
The capacitor's charging time is 5 milliseconds (max.) after VCC
and ClK reach their specified ac and dc parameters. RESET may
be applied to prevent spurious activity by the CPU during this time.
After this time, the SAB 80286 processor clock can be phasesynchronized to another clock by pulsing RESET lOW synchronous
to the system clock.
238
Function
[
~
:::J
~
to
1-------------------I Address Unit IAUI
------1
I
I
I
I
I
I
I
Address
1-: : >~~t~/~O
5egment
Size
Bus Control
Ie ~ REAOY,HOLO
,
~
I
I
51,50,COO INTA,
LOCK,HLDA
015-00
I
I
I
I
I
I
0>
3
-:------t-- PER E
I
1
Qi'
~
Q
","-~I-
L
o
I
I
Prefetcher
Bases
C~;;~er
,..
1.--------------,
I Bus Unit IBUI
I
1--1---\-- PEACK
5egment
5e.9 ment
0n
-----
----I
------,
-------j
ALU
~/
I
Registers
r Control
I
I
i Execution Unit lEU)
12
TI--r-l
L ______________ ~~+-
NHII
INTR
I I I BU5Y
ERROR
~
I
I
I
I
I
---------~
L
RE5ET
ClK
VSS
I
IL Instruction
_____
Unit
__
IIU)
____________
VCC
~
CAP
en
~
IX!
CO
o
'"
CD
'"
N
CO
0)
SAB 80286
instructions, and addressing modes. Therefore, the
SAB 80286 processor is upward-compatible with
the SAB 8086, 8088 and 80186 CPUs.
Functional Description
Introduction
The SAB 80286 is an advanced, high-performance
microprocessor with specially optimized capabilities
for mUltiple user and multitasking systems.
Depending on the application, the SAB 80286's
performance is up to six times faster than that of the
standard 5 MHz SAB 8086, while providing complete
upward software compatibility with the Siemens
16-bit CPU family ISAB 8086/88, SAB 80186/88),
The SAB 80286 operates in two modes: real address
mode 18086 mode) and protected virtual address
mode. Both modes execute a superset of the
SAB 8086188 instruction set. In real address mode
programs use real addresses with up to one megabyte of address space. Programs use virtual
~dd;-c~:;c;; iii pi-Vlt-Ctt:;J VillUdl aUuress moae, also
called protected mode. In protected mode, the
SAB 80286 CPU automatically maps 1 gigabyte of
virtual addresses per task into a 16 megabyte real
address space. This mode also provides memory
protection to isolate the operating system and
ensure privacy of each task's programs and data.
Both modes provide the same basic instruction set,
registers, and addressing modes.
The following functional description describes first
the basic SAB 80286 architecture common to both
modes, second the real address mode, and thirdly
the protected mode.
Basic Architecture
Register Set
The SAB 80286 basic architecture has fifteen
registers as shown below. These registers are
grouped into the following four categories:
General registers: Eight 16-bit general purpose
registers used to contain arithmetic and logical
operands. Four of these lAX, BX, CX, and DX) can
be used either in their entirety as 16-bit words or
split into pairs of separate 8-bit registers.
Segment registers: Four 16-bit special purpose
registers select, at any given time, the segments of
memory that are immediately addressable for
r.nrlA, c:t~rk. ?~tj
02!2 !~(:~ :..!:::g:::;, ;-CfCi~0 ~V~Cl-IIUIY
Organization).
Base and index registers: Four of the general
purpose registers may also be used to determine
offset addresses of operands in memory. These
registers may contain base addresses or indexes to
particular locations within a segment. The
addressing mode determines the specific registers
used for operand address calculations.
Status and control registers: The three 16-bit
special purpose registers in the figure below record
or control certain aspects of the SAB 80286
processor state including the instruction pointer
which contains the offset address of the next
sequential instruction to be executed.
The processors of the IntellSiemens 16-bit CPU
family all contain the same basic set of registers,
Register Set
Special
Register
Fundions
16-Bit
Register
Name
§
15
07
~~~eressable {~:
IS'Bit
Register
Names
Shown I
AH
AL
OH
OL
}
CX
CH
CL
8X
BH
BL
MultiplylDivide
I/O Instructions
) Loop/Shift/Repeat Count
} Base Registers
BP
(5
OS
Stack Segment Selector
ES
Extra Segment Seledor
Segment Registers
15
Index Registers
)
Stack Pointer
01
SP
o
15
General
Registers
240
Code Segment Selector
Dala Segment Selector
55
51
}
0
0
F§Flags
IP
Instruction Pointer
MSW
Machine Status Word
Status and (antral
Registers
SAB 80286
Status and Control Register Bit Functions
5 tatus
Flag~:
Carry - - - - - - - - - - - - - - - - - - - - - - - - " - ]
Parity - - - - - - - - - - - - - - - - - - - - - - - - - ,
Auxiliary Carry - - - - - - - - - - - - - - - - - - ,
Zero - - - - - - - - - - - - - ,
Sign - - - - - - - - - - - ,
Flags:
L---_ _ _ _ _ _
Control Flag~:
Trap Flag
I
" - - - - - - - - - - Interrupt Enable
Direction Flag
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _
~pecial
Fields:
L - - - - - - - - - - - - - - - - - - - I / O Privilege Level
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Nested Task Flag
15
_Reserved
Processor Extension Emulated _ _ _ _-..J
Monitor Processor Extension _ _ _ _ _ _--.1
Protection Enable
Flags Word Description
The flags word (flags) records specific characteristics of the result of logical and arithmetic
instructions (bits 0, 2, 4, 7, and 11) and controls the
operation of the SAB 80286 within a given operating
mode (bits 8 and 9). Flags is a 16-bit register. The
function of the flag bits is given in table 1.
Instruction Set
The instruction set is divided into seven categories:
data transfer, arithmetic, shift/rotate/logical, string
manipulation, control transfer, high level instructions, and processor control.
An SAB 80286 instruction can reference zero, one,
or two operands; where an operand resides in a
register, in the instruction itself, or in memory.
Zero-operand instructions (e.g. Nap and HLT) are
---------~
usually one byte long. One-operand instructions
(e.g. INC and DEC) are usually two bytes long but
some are encoded in only one byte. One-operand
instructions may reference a register or memory
location. Tow-operand instructions permit the
following six types of instruction operations:
- register to register
- memory to register
- immediate data to register
- memory to memory
- register to memory
- immediate data to memory
Two-operand instructions (e.g. MOV and ADD) are
usually three to six bytes long. Memory to memory
operations are provided by a special class of string
instructions requiring one to three bytes. For
detailed instruction formats and encodings refer to
the instruction set summary.
241
SAB 80286
Table 1
Flags Word Bit Functions
Bit
position
Name
Functions
0
CF
Carry Flag - Set on high-order bit carry or borrow; cleared otherwise
2
PF
Parity Flag - Set if low-order 8 bits of result contain an even number of 1-bits;
cleared otherwise
4
AF
Set on carry from or borrow to the low-order 4 bits of AL;
cleared otherwise
6
ZF
Zero Flag - Set if result is zero; cleared otherwise
7
SF
Sign Flag - Set equal to high-order bit of result (0 if positive, 1 if negative)
"
v.
vv,,, fiuw ;:iag - 5e! if result IS a positive number too large or a negative number
too small (excluding sign bit) to fit in destination operand; cleared otherwise
8
TF
Single Step Flag - Once set, a single step interrupt occurs after the next
instruction has been executed. TF is cleared by the single step interrupt
9
IF
Interrupt Enable Flag - When set, maskable interrupts will cause the CPU to
transfer control to an interrupt vector specified location
10
DF
Direction Flag - Causes string instructions to autodecrement the appropriate
index registers when set. Clearing DF causes autoincrement
Memory Organization
(a pointer) that consists of a 16-bit segment selector,
and a 16-bit offset. The segment selector indicates
the desired segment in memory. The offset
component indicates the desired byte address
within the segment.
Memory is organized as sets of variable length
segments. Each segment is a linear contiguous
sequence of up to 64 K (2 16 ) 8-bit bytes. Memory is
addressed using a two-component address
Two Component Address
32-Bit Pointer
I
31
,
A
/
Segment
I
Offset
1615
I
0
--.J
I
Operand
Selected
Memory
242
Selected
Segment
SAB 80286
Table 2
Segment Register Selection Rules
Memory
reference needed
Segment register
used
Implicit segment
selection rule
Instructions
Code (CS)
Automatic with instruction prefetch
Stack
Stack (55)
All stack pushes and pops. Any memory reference which uses
BP as a base register
Local data
Data (OS)
All data references except when relative to stack or string
destination
Externed (global) data Extra (ES)
Alternate data segment and destination of string operation
All instructions that address operands in memory
must specify the segment and the offset. For
speed and compact instruction encoding, segment
selectors are usually stored in the high-speed
segment registers. An instruction need specify only
the desired segment register and an offset in order
to address a memory operand.
Most instructions need not explicitly specify which
segment register is used. The correct segment
register is automatically chosen according to the
rules of table 2.
These rules follow the way programs are written as
independent modules that require areas for code
and data, a stack, and access to external data areas.
Special segment override instruction prefixes allow
the implicit segment register selection rules to be
overridden for special cases. The stack, data, and
extra segments may coincide for simple programs.
To access operands not residing in one of the four
immediately available segments, a full 32-bit pointer
or a new segment selector must be loaded.
Addressing Modes
The SAB 80286 provides a total of eight adressing
modes for instructions to specify operands. Two
addressing modes are provided for instructions that
operate on register or immediate operands:
Register operand mode: The operand is located in
one of the 8 or 16-bit general registers.
Immediate operand mode: The operand is included
in the instruction.
Direct mode: The operand's offset is contained in
the instruction as an 8 or 16-bit displacement
element.
Register indirect mode: The operand's offset is in
one ofthe registers 51, 01, BX, or BP.
Based mode: The operand's offset is the sum of an
8 or 16-bit displacement and the contents of a base
register (BX or BP).
Indexed mode: The operand's offset is the sum of
an 8 or 16-bit displacement and the contents of an
index register (51 or 01).
Based indexed mode: The operand's offset is the
sum of the contents of a base register and an index
register.
Based indexed mode with displacement: The
operand's offset is the sum of a base register's
contents, an index register's contents, and an 8 or
16-bit displacement.
Data Types
The SAB 80286 directly supports the following data
types:
Integer:
A signed binary numeric value contained in an 8-bit
byte or a 16-bit word. All operations assume a 2's
complement representation. Signed 32 and 64-bit
integers are supported using the numeric data
processor extension.
Ordinal:
An unsigned binary numeric value contained in an
8-bit byte or 16-bit word.
Pointer:
A 32-bit quantity, composed of a segment selector
component and an offset component. Each component is a 16-bit word.
String:
A contiguous sequence of bytes or words. A string
may contain between 1 byte and 64 Kbytes.
ASCII:
A byte representation of alphanumeric and control
characters using the ASCII standard of character
representation.
BCD:
A byte (unpacked) representation of the decimal
digits 0 to 9.
243
SAB 80286
Packed BCD:
A byte (packed) representation of two decimal digits
oto 9 storing one digit in each nibble of the byte.
Floating Point:
A signed 32, 64, or80-bit real number representation
(Floating point operands are supported using the
extended processor configuration with SAB 80287).
1/0 Space
The 1/0 space consists of 64 K 8-bit or 32 K 16-bit
ports. 1/0 instructions address the 1/0 space with
either an 8-bit port address, specified in the
instruction, or a 16-bit port address in the DX register,
8-bit port addresses are zero extended such that
A15-A8 are LOW. 1/0 port addresses 00F8(H)
through OOFF(H) are reserved.
Table 3
Interrupt Vector Assignments
Function
Interrupt
Number
Related
instructions
Divide error exception
0
DIV,IDIV
Yes
Single step interrupt
1
All
-
NMI interrupt
2
All
-
Breakpoint interrupt
3
INT
-
INTO detected overflow exception
4
INTO
No
BOUND range exceeded exception
5
BOUND
Yes
Invalid opcode exception
6
any undefined opcode Yes
Processor extension not available exception
7
ESC orWAIT
Reserved
8-15
Processor extension error interrupt
16
Return address
before instruction
causing exception?
Yes
ESC or WAIT
-
Reserved
17-31
-
User defined
32-255
-
Interrupts
An interrupt transfers execution to a new program
lecation. The old program address (CS:IP) and
machine state (flags) are saved on the stack to allow
resumption of the interrupted program. Interrupts
fall into three classes: hardware initiated, INT
instructions, and instruction exceptions. Hardwareinitiated interrupts occur in response to an external
input and are classified as non-maskable or
maskable. Programs may cause an interrupt with an
INT instruction. Instruction exceptions occur when
an unusual condition, which prevents further
instruction processing, is detected while attempting
to execute an instruction. The return address from
an exception will always point at the instruction
causing the exception and include any leading
instruction prefixes.
A table containing up to 256 pointers defines the
proper interrupt service routine for each interrupt.
Interrupts 0 to 31, some of which are used for
instruction exceptions, are reserved. For each inter-
244
rupt, an 8-bit vector must be supplied to the
SAB 80286 which identifies the appropriate table
entry. Exceptions supply the interrupt vector internally. INT instructions contain or imply the vector
and allow access to all 256 interrupts. Maskable
hardware initiated interrupts supply the 8-bit vector
to the CPU during an interrupt acknowledge bus
sequence. Non-maskable hardware interrupts use a
predefined internally supplied vector.
Single step interrupt
The SAB 80286 has an internal interrupt that allows
programs to execute one instruction at a time. It is
called the single step interrupt and is controlled by
the single step flag bit (TF) in the flag word. Once
this bit is set, an internal single step interrupt will
occur after the next instruction has been executed.
The interrupt clears the TF bit and uses an internally
supplied vector of 1. The IRET instruction is used to
set the TF bit and transfer .control to the next
instruction to be single-stepped.
SAB 80286
Interrupt Priorities
When simultaneous interrupt requests occur, they
are processed in a fixed order as shown in table 4.
Interrupt processing involves saving the flags,
return address, and setting CS:IP to point atthe first
instruction of the interrupt handler. If other inter-
rupts remain enabled they are processed before the
first instruction of the current interrupt handler is
executed. The last interrupt processed is therefore
the first one serviced.
Table4
Interrupt Processing Order
Order
Interrupt
Instruction exception
2
Single step
3
NMI
4
Processor extension segment overrun
5
IINTR
6
Initialization and processor reset
Machine Status Word Description
Processor initialization or start up is accomplished
by driving the RESET input pin HIGH. RESET forces
the SAB 80286 to terminate all execution and local
bus activity. No instruction or bus activity will occur
as long as RESET is active. After RESET became
inactive and an internal processing interval has
elapsed, the SAB 80286 begins execution in real
address mode with the instruction at physical
location FFFFFO(H). RESET also sets some registers
to predefined values as shown in table 5.
A23 to A20 will be HIGH when the SAB 80286
performs memory references relative to the CS
register until CS is changed. A23 to A20 will be zero
for references to the OS, ES, or SS segments.
Changing CS in real address mode will force A23 to
A20 LOW whenever CS is used again. The initial
CS:IP value of FOOO:FFFO provides 64 Kbytes of code
space for initialization code without changing CS.
The machine status word (MSW) records when a
task switch takes place and controls the operating
mode of the SAB 80286. It is a 16-bit register of
which the lower four bits are used. One bit places
the CPU·into protected mode, while the other three
bits, as shown in table 6, control the processor
extension interface. After RESET, this register
contains FFFO(H) which places the SAB 80286 in real
address mode.
Table 5
SAB 80286 Initial Register State after RESET
Flag word
Mach ine status word
Instruction pointer
Code segment
Data segment
Extra segment
Stack segment
0002(H)
FFFO(H)
FFFO(H)
FOOO(H)
OOOO(H)
OOOO(H)
OOOO(H)
245
SAB 80286
Table 6
MSW Bit Functions
Bit
position
Name
Function
0
PE
Protected mode enable places the SAB 80286 into protected mode and cannot
be cleared except by RESET
1
MP
Monitor processor extension allows WAIT instructions to cause a processor
extension not present exception (number 7)
2
EM
Emulate processor extension causes a processor extension not present
exception (number 7) on ESC instructions to allow emulating a processor
extension
3
TS
Task switched indicates that the next instruction using a processor extension
will cause exception 7, allowina software to tP.~t whp.th~r the ~1_1::e~! p~~~:::::::~:extension context belongs to the current task
I
The LMSW and SMSW instructions can load and
store the MSW in real addre~s mode. The
recommended use of TS, EM, and MP is shown in
table 7.
Table 7
Recommended MSW Encodings For Processor Extension Control
Instructions
causing
exception 7
TS
MP
EM
Recommended use
0
0
0
Initial encoding after RESET. SAB 20286 operation
is identical with SAB 8086/88 operation
none
0
0
1
No processor extension is available. Software will
emulate its function
ESC
1
0
1
No processor extension is available. Software will
emulate its function. The current processor extension
context may belong to another task
ESC
0
1
0
A processor extension exists
none
1
1
0
A processor extension exists. The current processor
extension context may belong to another task. The
exception on WAIT allows software to test for an error
pending from a previous processor extension
operation
ESC orWAIT
Halt
The HL T instruction stops program execution and
prevents the CPU from using the local bus until
restarted. Either NMI, INTR with IF = 1, or RESET
246
will force the SAB 80286 out of halt. If interrupted
the saved CS:IP will point to the next instruction
after the HLT.
SAB 80286
Real Address Mode
The SAB 80286 executes a fully upward-compatible
superset of the SAB 8086's instruction set in real
address mode. In real address mode, the SAB 80286
is object code compatible with SAB 8086 and
SAB 8088 software. The real address mode architecture Iregisters and addressing modes) is exactly
as described in the SAB 80286 basic architecture
section of this functional description.
Memory Size
Physical memory is a contiguous array of up to
1,048,576 bytes lone megabyte) addressed by pins
AO through A 19 and BHE. A20 through A23 may
be ignored.
Memory Addressing
In real address mode the processor generates 20-bit
physical addresses directly from a 20-bit-segment
base address and a 16-bit offset.
The selector portion of a pointer is interpreted as
the upper 16 bits of a 20-bit segment address. The
lower four bits of the 20-bit segment addresses are
always zero. Segment addresses, therefore, begin
on multiples of 16 bytes. See figure on address
calculation for a graphic representation of address
formation.
All segments in real address mode are 64 Kbytes in
size and may be read, written, or executed. An
exception or interrupt can occur if data operands or
instructions attempt to wrap around the end of a
segment le.g. a word with its low-order byte at
offset FFFF(H) and its high-order byte at offset
OOOOIH). If, in real address mode, the information
contained in a segment does not use the full
64 Kbytes, the unused end of the segment may be
overlayed by another segment to reduce physical
memory requirements.
Real Address Mode, Address Calculation
15
0000
I
Offset
I
L..._ _..1_ _ _ _ _ _ _ _ _ _ _---.J
15
'--I
Offset
Address
r-~--
19
20-Bit Physical
Memory Address
247
SAB 80286
Table 8
Real Address Mode, Addressing Interrupts
Interrupt
number
Related
instructions
Return address
before instruction?
Interrupt table limit too small
exception
8
INT vector is not within table limit
Yes
Processor extension segment
ove rru n i nte rru pt
9
ESC with memory operand
extending beyond offset FFFF(H)
No
Segment overrun exception
13
Word memory reference with
offset = FFFF(H) or an attempt to
execute past the end of a segment
Yes
Function
Interrupts
I~uie
a snows tne interrupt vectors reserved tor
exceptions and interrupts which indicate an
addressing error. The exceptions leave the CPU in
the state existing before attempting to execute the
failing instruction (except for PUSH, POP, PUSHA,
or paPA).
~:I_re9,ist7~s, .i,nst~~c~i~~.:_a_nd addressing modes
U'Ci.:,.,•• I IUI,'::U III lilt:: 0J-\C OULOO UC:!::ilC arcnllecture
section of the functional description remain the
same. Programs for the SAB 8086, SAB 8088,
SAB 80186 and real address mode SAB 80286 can
be run in protected mode: however, embedded
constants for segment selectors are different.
Shutdown
Memory Size
Shutdown occurs when a severe error is detected
that prevents further instruction processing by the
CPU. Shutdown and halt are externally signalled
via a halt bus operation. They can be distinguished
by A 1 HIGH for halt and AlLOW for shutdown. In
real address mode, shutdown can occur under two
conditions:
The protected mode SAB 80286 provides a 1
gigabyte virtual address space per task mapped into
a 16 megabyte physical address space defined by
the address pins A23-AO and BHE. The virtual
address space may be larger than the physical
address space since any use of an address that does
not map to a physical memory location will cause
a restartable exception .
• Exceptions 8 or 13 happen and the IDT limit does
not include the interrupt vector.
• A CALL, INT or POP instruction attempts to wrap
around the stack segment when SP is not even.
An NMI input can bring the CPU out of shutdown if
the IDT limit is at least OOOF(H) and SP is greater than
0005(H). otherwise shutdown can only be exited via
the RESET input.
Protected Virtual Address Mode
The SAB 80286 executes a fully upward-compatible
superset ofthe SAB 8086 instruction set in protected
virtual address mode (protected mode). Protected
mode also provides memory management and
protection mechanisms and associated instructions.
The SAB 80286 enters protected virtual address
mode from real address mode by setting the PE
(Protection Enable) bit of the machine status word
with the Load Machine Status Word (LMSW)
instruction. Protected mode offers extended physical
and virtual memory address space, memory protection mechanisms, and new operations to support
operating system and virtual memory.
248
Memory Addressing
As in real address mode, protected mode uses 32-bit
pointers, consisting of 16-bit selector and offset
components. The selector, however, specifies an
index into a memory resident table rather than the
upper 16-bits of a real memory address. The 24-bit
base address of the desired segment is obtained
from the tables in memory. The 16-bit offset is added
to the segment base address to form the physical
address as shown in the figure below. The tables
are automatically referenced by the CPU whenever
a segment register is loaded with a selector. All
SAB 80286 instructions which load a segment
register will reference the memory-based tables
without additional software. The memory-based
tables contain 8 byte values called descriptors.
SAB 80286
Protected Mode, Memory Addressing
CPU
31
Pointer
a
16 15
Selector
I
Offset
I
I
I
Physical
Address
Adder
I23
Segment Base
Address
I
r
a
~
Physical Memory
Memory
Operand
Segment
Descriptor
~
Segment
Segment
Descriptor
Table
1
= 1)
Descriptors
Code and data segment descriptors (S
Descriptors define the use of memory. Special types
of descriptors also define new functions for transfer
of control and task switching. The SAB 80286 has
segment descriptors for code, stack and data
segments, as well as system control descriptors for
special system data segments and control transfer
operations. Descriptor accesses are performed as
locked bus operations to assure descriptor integrity
in mu Itiprocessor systems.
Besides segment base addresses, code and data
descriptors contain other segment attributes
including segment size (1 to 64 Kbytes), access rig hts
(read only, read/write, execute only, and execute/
read). and presence in memory (for virtual memory
systems; figure and table next page). Any segment
usage violating a segment attribute indicated by the
segment descriptor will prevent the memory cycle
and cause an exception or interrupt.
249
SAB 80286
Code or Data Segment Descriptor
7
o
07
Reserved*)
Access
Rights Byte
+5
P
I Is I
OPL
II
Type
A
+6
Base 23 -Base 16
+4
Base15-BaseO
+2
Limit 15-LimitO
+1
87
15
o
*) Must be set to 0 for compatibility with SAB 80386
Access Rights Byte Definition
Bit
Position
Name
7
Present (P)
6-5
Descriptor privilege
level (DPL)
Segment descriptor (5)
Function
P= 1
p=o
Segment is mapped into physical memory
No mapping to physical memory exists, base and limit are not
used
Segment privilege attribute used in privilege tests
5 = 1
5=0
Code or data (includes stacks) segment descriptor
System segment descriptor or gate descriptor
1
Executable (E)
Expansion direction (ED)
Writeable (W)
E=O
ED = 0
ED = 1
W=O
W=1
Data segment descriptor type is:
Expand up segment, offsets must be :5 limit
Expand down segment, offsets must be > limit
Data segment may not be written into
Data segment may be written into
3
2
Executable (E)
Conforming (C)
E= 1
C= 1
~ 1
Readable (R)
R=O
R= 1
Code segment descriptor type is:
Code segment may only be executed when
CPL 2:: DPL and CPL remains unchanged
Code segment may not be read
Code segment may be read
0
Accessed (A)
A=O
A=1
4
3
c 2
:~c
't
1J
1J
Qj
<,::
OJ
0-
I
I
If
code
segment
(5 = 1,
E = 1)
Segment has not be accessed
Segment selector has been loaded into segment register or
used by selector test instructions
Code and data (including stack data) are stored in
two types of segments: code segments and data
segments. Both types are identified and defined by
segment descriptors (5 = 1). Code segments are
identified by the executable (E) bit set to 1 in the
descriptor access rights byte, whereas the data
segments have the E bit set to O.
250
If
data
segment
(5 = 1,
E = 0)
System segment descriptors (S = 0, type = '-3)
In addition to code and data segment descriptors,
the protected mode SAB 80286 defines system
segment descriptors. These descriptors define
special system data segments which contain a table
of descriptors (local descriptor table descriptor)
or segments which contain the execution state of a
task (task state segment descriptor).
The figure and table on next page show the formats
for the special system data segment descriptors.
SAB 80286
System Segment Descriptor
a7
o
Reserved*l
.7
I
I
.5 P DPL
I0 I
Type
Base 23 -Base 16
I
.3
Base1S-BaseO
.1
Limit1S-LimitO
15
.4
o
87
*) Must be set to 0 for compatibility with SAB 80386
System Segment Descriptor Fields
Name
Value
Description
TYPE
1
2
3
Available task state segment
Local descriptor table descriptor
Busy task state segment
P
0
1
Descriptor contents are not valid
Descriptor contents are valid
DPL
0-3
Descriptor privilege level
BASE
24-bit number
Base address of special system data segment in real memory
LIMIT
16-bit number
Offset of last byte in segment
Gate Descriptors (S
= 0, Type = 4-7)
Gates are used to control access to entry points
within the target code segment. The gate descriptors are call gates, task gates, interrupt gates and
trap gates. Gates provide a level of indirection
between the source and destination of the control
transfer. This indirection allows the CPU to automatically perform protection checks and control
entry point of the destination. Call gates are used to
change privilege levels (see privilege), task gates
are used to perform a task switch, and interrupt and
trap gates are used to specify interrupt service
routines. The interrupt gate disables interrupts
(resets IF) while the trap gate does not.
The figure and table below show the format of thEi
gate descriptors. The descriptor contains a
destination pointer that points to the descriptor of
the target segment and the entry point offset. The
destination selector in an interrupt gate, trap gate,
and call gate must refer to a code segment
descriptor. Exception 13 is generated when the gate
is used if a destination selector does not refer to the
correct descriptor type.
251
SAB 80286
Gate Descriptor
07
Reserved *)
p
I DPL I 0 I
Type
Ix
X
+6
xl
Word Count
4-0
Destination Selector 15 - 2
I
+1
Ix
+4
X +2
Destination Offset 15-0
I
15
87
*) Must be set to 0 for compatibility with SAB 80386 IX is don't care)
Gate Descriptor Fields
Value
Description
4
5
7
-
P
0
1
- Descriptor contents are not valid
- Descriptor contents are valid
DPL
0-3
Descriptor Privilege level
WORD
COUNT
0-31
Number of words to copy from callers stack to called
procedures stack. Only used with call gate
DESTINATION
SELECTOR
16-bit
selector
Selector to the target code segment (call, interrupt or trap gate)
DESTINATION
OFFSET
16-bit
offset
Entry point within the target code segment
Name
TYPE
6
Call gate
Task gate
Interrupt gate
Trap gate
Segment Descriptor Cache Registers
Selector Fields
A segment descriptor cache register is assigned
to each of the four segment registers (CS, SS, DS,
ES). Segment descriptors are automatically loaded
(cached) into a segment descriptor cache register
(see figure) whenever the associated segment
register is loaded with a selector. Only segment
descriptors may be loaded into segment descriptor
cache registers. Once loaded, all references to that
segment of memory use the cached descriptor
information instead of reaccessing memory. The
descriptor cache registers are not visible to
programs. No instructions exist to store their
contents. They only change when a segment
register is loaded.
A protected mode selector has three fields: descriptor entry index, local or global descriptor table
indicator (TI), and selector privilege (RPL) as shown
in the figure on selector fields. These fields select
one of two memory-based tables of descriptors,
select the appropriate table entry and allow
highspeed testing of the selector's privilege
attribute (refer to privilege discussion below).
252
SAB 80286
Descriptor Cache Registers
Program Visible
Access
Rights
Segment Selectors
~;~
1S
Segment Base Address
Segment Size
11-----+-1- - I - - - - - l
o
47
16 15
4039
I
I
I
I
Segment Registers
I Loaded by Program}
:
Segment Discriptor Cache Registers
~~~~~~~~
L ___________
I
___________ ~
Selector Fields
Selector
Index
I I I
15
I
HR~LI
3 210
Bits
Name
1-0
Function
Requested
Privilege
Level
(RPl)
Indicates Selector Privilege
Level Des ired
2
Table
Indicator
(TI)
TI = 0 Use Global Descriptor Table
(GOT)
TI = 1 Use Local Descriptor Table
(LOT)
15-3
Index
Select Descriptor Entry in Table
Local and Global Descriptor Tables (LOT, GOT)
Two tables of descriptors, called descriptor tables,
contain all descriptors accessible by a task at any
given time. A descriptor table is a linear array of up
to 8192 descriptors. The upper 13 bits of the
selector value are an index into a descriptor table.
Each table has a 24-bit base register to locate the
descriptor table in physical memory and a 16-bit
limit register that confine descriptor access to the
defined limits of the table as shown in the figure
below. A restartable exception (13) will occur if an
attempt is made to reference a descriptor outside
the table limits.
253
SAB 80286
Local and Global Descriptor Table Definition
Memory
CPU
(
r
23
I
··
0
15
GOT Limit
Globol
} Descriptor
TClbie
(GOT)
GOT Base
15
I
0
LOT
Selector
LOT1
+s{
··
,----------1
)
0 I
15
I
I LOT
i 23
iI I
LOT Base
Limit
~---
+J
I
I
I
Program
Invisible
IL __________ --lI
LOTn
···
Global Descriptor Table and Interrupt Descriptor Table Data Type
7
07
I
Reserved*")
+5
Base 23 -Base 16
+3
Base15-BaseO
+1
Limit 15 -LimitO
15
+4
87
*) Must be set to 0 for compatibility with SAB 80386
Interrupt Descriptor Table
The protected mode SAB 80286 has a third
descriptor table, called the interrupt descriptor
table (OT) (see figure below). used to define up to
256 interrupts. It may contain only task gates,
interrupt gates and trap gates. The lOT (interrupt
254
descriptor table) has a 24-bit base and 16-bit limit
register in the CPU. References to lOT entries are
made via INT instructions, external interrupt
vectors, or exceptions. The lOT must be at least
256 bytes in size to allocate space for all reserved
interrupts.
SAB 80286
Interrupt Descriptor Table Definition
Memory
r
Gate for
Interrupt # n
I
Gate for
Interrupt #n-1
···
·
CPU
15
1
I
Gate for
Interrupt # 1
0
lOT Limit
lOT Base
~
--
Interrupt
Oes( riptor
Table
( lOT)
l
Gate for
Interrupt # 0
21:-3- - - - - - - - !
Privilege
The SAB 80286 has a four-level hierarchical
privilege system which controls the use of
privileged instructions and access to descriptors
(and their associated segments) within a task
(figure below). The privilege levels are numbered 0
through 3. Level 0 is the most privileged level.
Hierarchical Privilege Levels
Applications
CPU
Enforced
Software
High Speed
Operating
System
Interface
255
SAB 80286
Protection
The SAB 80286 includes mechanisms to protect
critical instructions that affect the CPU execution
state (e.g. HLTI and code or data segments from
improper usage. These mechanisms are grouped
under the term "protection" and have three forms:
Restricted usage of segments (e.g. no write allowed
to read-only data segmentsl. The only segments
available for use are defined by descriptors in the
local descriptor table (LDTI and global descriptor
table (GDTI.
Restricted access to segments via the rules of
privilege and descriptor usage.
Privileged instructions or operations that may only
be executed at certain privilege levels as
determined by the CPL and I/O privilege level (IOPLI.
Th ..... 1("101 ; ..... ....J .... +: .......... ..-J h .. h: ........ 1.1 .... _..J 1") ..... +-1-1..._ £1 __
I " v , .......
'- , ................. , ................ 1 ..... ,~ ..... '""T .... , , ..... , .... V I ~I''''' IIU~
Table 10
Operand Reference Checks
Error description
Write into code segment
Read from execute-only code
segment
Write to read-only data segment
Segment limit exceeded 1)
1)
Exception
number
13
13
13
12 or 13
Carry out in offset calculations is ignored.
Table 11
Privileged Instruction Checks
Error description
IException
numoer
word.
These checks are performed for all instructions and
can be split into three categories: segment load
checks (table 91, operand reference checks (table 101,
and privileged instruction checks (table 111. Any
violation of the rules shown will result in an
exception. A not-present exception related to the
stack segment causes exception 12.
The IRET and POPF instructions do not perform
some of their defined functions if CPL is not of
sufficient privilege (numerically small enoughl.
No exceptions or other indication are given when
these conditions occur:
The IF bit is not changed if CPL > 10PL.
The 10PL field of the flag word is not changed
ifCPL> O.
Table 9
Segment Register Load Checks
Error description
Exception
number
Descriptor table limit exceeded
13
Segment descriptor not present
11 or 12
Privilege rules violated
13
Invalid descriptor/segment type
segment register load:
- read only data segment load to
SS
- special control descriptor load to
DS, ES, SS
- execute only segment load to
OS, ES, SS
- data segment load to CS
- read/execute code segment
load to SS
13
256
CPL> 0 when executing the
following instructions
LlOT, LLOT, LGOT, LTR, LMSW,
CTS,HLT
13
CPL> 10PL when executing the
following instructions
INS, IN, OUTS, OUT, STI, CLI,
LOCK
13
Exceptions
The SAB 80286 detects several types of exceptions
and interrupts in protected mode (see table 121.
Most of then are restartable after the exceptional
condition is removed. Interrupt handlers for most
exceptions receive an error code, pushed on the
stack after the return address, that identifies the
selector involved (0 if nonel. The return address
normally points to the failing instruction, including
all leading prefixes. For a processor extension
segment overrun exception, the return address will
not point at the ESC instruction that caused the
exception; however, the processor extension
registers may contain the address of the failing
instruction.
SAB 80286
Table 12
Protected Mode Exceptions
Interrupt
vector
Function
Return
address
at failing
instruction?
Always
restartable?
Error
code
on stack?
8
9
10
11
12
13
Double exception detected
Processor extension segment overrun
Invalid task state segment
Segment not present
Stack segment overrun or segment not present
General protection
yes
no
yes
yes
yes
yes
no
no
yes
yes
yes1)
no
yes
no
yes
yes
yes
yes
11 When a PUSHA instruction attempts to wrap around the stack segment, the machine state after the
exception will not be restartable. This condition is identified by the value of the saved SP being either
OOOO(H), 0001(H), FFFE(H), or FFFF(H).
Special Operations
Task Switch Operation
Processor Extension Context Switching
The SAB 80286 provides a built-in task switch
operation which saves the entire SAB 80286
execution state (registers, address space, and a
link to the previous task)' loads a new execution
state, and commences execution in the new task.
Like gates, the task switch operation is invoked by
executing an inter-segmentJMP or CALL instruction
which refers to a task state segment (TSS) or task
gate descriptor in the GDT or LDT. An INT instruction,
exception, or external interrupt may also invoke the
task switch operation by selecting a task gate
descriptor in the associated IDT descriptor entry.
The context of a processor extension (such as the
SAB 80287 numerics processor) is not changed by
the task switch operation. A processor extension
context need only be changed when a different task
attempts to use the processor extension (which
still contains the context of a previous task).
The TSS descriptor points at a segment (see figure
on next page) containing the entire SAB 80286
execution state while a task gate descriptor
contains a TSS selector. The limit field must be
> 002B(H).
The task state segment is marked busy by Changing
the descriptor type field from type 1 to type 3. Use of
a selector that references a busy task state segment
causes exception 13.
Whenever the SAB 80286 switches tasks, it sets the
task switched (TS) bit of the MSW. TS indicates that
a processor extension context may belong to a
different task than the current one. The processor
extension not present exception (7) will occurwhen
attempting to execute an ESC or WAIT instruction
if TS = 1 and a processor extension is present
(MP = 1 in MSW).
Double Fault and Shutdown
If two seperate exceptions are detected during a
single instruction execution, the SAB 80286
performs the double fault exception (8). If an
exception occurs during processing of the double
fault exception, the SAB 80286 will enter shutdown.
During shutdown no further instructions or
exceptions are processed. Either NMI (CPU remains
in protected mode) or RESET (CPU exits protected
mode) can force the SAB 80286 out of shutdown.
Shutdown is externally signalled via a HALT bus
operation with A 1 HIGH.
257
SAB 80286
Task State Segment and TSS Registers
Type Description
Reserved
CPU
1
Task Register
System
Segment
Descriptor
TRc=J--15
0
ip;g--;;';;;-;;;~sible
I
15
0
l
I
i JL;;;t"]- U
II
J J:
Base
I 23
0
Base1S-BaseO
An available task
state segment. May
be used as the destination of a task
switch operation.
]l
A busy task state
segment. Cannot be
used as the dest;-
I
,
,
------i-----------Limit 15: limitO
I ~~;;~~ of
l~
~o:~:
_J
I
L ________ .J
Byte
15
Task LOT Selector
Task
State
Segment
o Offset
42
OS Selector
40
55 Selector
38
C5 Selector
36
ES Selector
34
01
32
51
30
BP
28
SP
26
BX
24
OX
22
CX
20
AX
18
Flag Word
16
IP (Entry Point)
14
P
Description
Base and limit fields
are valid
Segment is not present in memory.
Base and limit are
not defined.
Current
Task
State
55 for CPL2
SP for CPL 2
SS for CPL 1
SP for CPL 1
55 for CPL 0
SPfor CPLO
Back Link Selector to TSS
258
0
10
8
"I
~
0
Initial
Stacks
for CPL 0,1,2
SAB 80286
System Interface
The SAB 80286 system interface appears in two
forms: a local bus and a system bus. The local bus
consists of address, data, status, and control
signals at the pins of the CPU, A system bus is any
buffered version of the local bus. A system bus may
also differ from the local bus in terms of coding of
status and control lines and/or timing and loading
of signals. The SAB 80286 family includes several
devices to generate standard system buses such
as the IEEE 796 standard Multibus 8
Bus Interface Signals and Timing
The SAB 80286 local bus interfaces the SAB 80286
to local memory and I/O components. The interface
has 24 address lines, 16 data lines, and 8 status and
control signals.
The SAB 80286 CPU, SAB 82284 clock generator,
SAB 82288 bus controller, SAB 82289 bus arbiter,
SAB 8286A/8287A transceivers, and SAB 8282A/
8283A latches provide a buffered and decoded
system bus interface. The SAB 82284 generates the
system clock and synchronizes READY and RESET.
The SAB 82288 converts bus operation status
encoded by the SAB 80286 into command and bus
control signals.
The SAB 82289 bus arbiter generates Multibus bus
arbitration signals. These components can provide
the timing and electrical power drive levels required
for most system bus interfaces including the
Multibus.
Physical Memory and liD Interface
A maximum of 16 megabytes of physical memory
can be addressed in protected mode. One
megabyte can be addressed in real address mode.
Memory is accessible as bytes or words. Words
consist of a ny two consecutive bytes addressed
with the least significant byte stored in the lowest
address.
The I/O address space contains 64 K addresses in
both modes. The I/O space is accessible as either
bytes or words, as is memory. Byte-wide peripheral
devices may be attached to either the upper or lower
byte of the data bus. An interrupt controller such
as the SAB 8259A must be connected to the lower
byte of the data bus (D7-DO) for proper return of the
interrupt vector.
Bus Operation
The SAB 80286 uses a double frequency system
clock (ClK input) to control bus timing. All signals
on the local bus are measured relative to the system
ClK input. The CPU divides the system clock by 2 to
produce the internal processor clock, which
determines bus state. Each processor clock is
composed of two system clock cycles named
phase 1 and phase 2. The SAB 82284 clock generator
output (PClK) identifies the next phase of the
processor clock (see figure on system and processor
clock relationship),
System and Processor Clock Relationship
One Processor Clock Cycle
f-----
One Bus T State
---~..,
CLK
J
One System---j
_ CLK Cycle
I
PCLK
r
\ ' -_ _ _ _ _
259
SAB 80286
Six types of bus operations are supported: memory
read, memory write, I/O read, I/O write, interrupt
acknowledge, and halt/shutdown. Data can be
transferred at a maximum rate of one word per two
processor clock cycles.
The SAB 80286 bus has three basic states: idle (TI).
send status (TSI, and perform command (TCI. The
SAB 80286 CPU also has a fourth local bus state
called hold (THI. TH indicates that the SAB 80286
has surrendered control of the local bus to another
bus master in response to a HOLD request.
Each bus state is one processor clock long. The
figure below shows the four SAB 80286 local bus
states and allowed transitions.
Pipelined Addressing
The SAB 80286 uses a local bus interface with
j.JijJc;,:;I-'C~ Lilll;ll'd LU dllUW a~ rnucn lime as posSIble
for data access. Pipelined timing allows bus
operations to be performed in two processor cycles,
while allowing each individual bus operation to
last for three processor cycles.
The timing of the address outputs is pipelined such
that the address of the next bus operation becomes
available during the current bus operation. Or in
other words, the first clock of the next bus operation
is overlapped with the last clock of the current bus
operation. Therefore, address decoder and routing
logic can operate in advance of the next bus
operation. External address latches may hold the
address stable for the entire bus operation, and
provide additional ae and de buffering.
The SAB 80286 does not maintain the address of the
current bus operation during all TC states. Instead,
the address for the next bus operation may be
emitted during phase 2 of any TC. The address
remains valid during phase 1 olthe first TC to
quarantee hold timA. rp.IRtivp tn AI J=, fnrthl? eddress
latch inputs.
SAB 80286 Bus States
RESET
HLDA
HLDA
NEW CYCLE· HLDA
HLDA' NEW CYCLE
HLDA· NEW
CYCLE~
"
NEW CYCLE
ALWAYS
READY· NEW CYCLE
260
READY· NEW CYCLE
SAB 80286
Basic Bus Cycle
Read Cycle N
Read Cycle N+ 1
CLK
PROC CLK
A23-AO
50·51
J
READY
015-00---------------------0------------0
Valid Read
Data IN)
Valid Read
Data IN+lI
Bus Cycle Termination
Synchronous Ready
At maximum transfer rates, the SAB 80286 bus
alternates between the status and command states.
The bus status signals become inactive after TS so
that they may correctly signal the start of the next
bus operation after the completion of the current
cycle. No external indication of TC exists on the
SAB 80286 local bus. The bus master and bus
controller enter TC directly after TS, and continue
executing TC cycles until terminated by READY.
The SAB 82284 clock generator provides READY
synchronization from both synchronous and
asynchronous sources (see figure on next page).
The synchronous ready input (SRDY) of the clock
generator is sampled with the falling edge of ClK at
the end of phase 1 of each TC. The state of SRDY is
then transferred to the bus master and bus
controller via the READY output line.
Asynchronous Ready
READY Operation
The current bus master and SAB 82288 bus
controller terminate each bus operation
simultaneously to achieve maximum bus bandwidth. Both are informed in advance by READY
active which identifies the last TC cycle of the
current bus operation. The bus master and bus
controller must see the same sense of the READY
signal, there by requiring READY be synchronous
to the system clock.
Many systems have devices of subsystems that are
asynchronous to the system clock. As a result, their
ready outputs cannot be guaranteed to meet the
SAB 82284 SRDY setup and hold time requirements.
But the SAB 82284 asynchronous ready input
(ARDY) is designed to accept such signals. The
ARDY input is sampled at the beginning of each TC
cycle by SAB 82/.84 synchronization logic. This
provides one system CLK cycle time to resolve its
value before transferring it to the bus master and
bus controller.
261
SAB 80286
Synchronous and Asynchronous Ready
Memory Cycle N-1
Memory Cycle N
--T5-~+---
ClK
PROC elK
A23 - AO
50·51
5RDY
READY
ARDY
3)
1) 5RDYEN is active low
2) If 5RDYEN is high, the state of SRDY will not effect READY
3) ARDYEN is active low
ARDY or ARDYEN must be HIGH at the end of TS.
ARDY cannot be used to terminate a bus cycle with
no wait states.
Each ready inputofthe SAB 82284 has an enable pin
(SRDYEN and ARDYEN) to select whether the
current bus operation will be terminated by the
synchronous or asynchronous ready. Either of the
ready inputs may terminate a bus operation. These
enable inputs are active low and have the same
timing as their respective ready inputs. An address
decode logic usually selects whether the current
bus operation should be terminated by ARDY or
SRDY.
262
Hold and HLDA
HOLD and HLDA allow another bus master to gain
control of the local bus by placing the SAB 80286
bus into the Th state. The sequence of events
required to pass control between the SAB 80286
and another local bus master is shown in the
next figu reo
SAB 80286
Multibus Write Terminated by Asynchronous Ready with Bus Hold
Bus Hold
Bus Cycle Type
CLK
110LO
HLOA
SAB
60286
A23-AO
MliO
-------------\-(
COOIINTA
'--+---"
BHE,LOCK - - - - - - - - - - -
015-00--------------
Valid
SAB
82284
CMOLY
SAB
82288
71
OTiR - - - - - - - - - - - - - - - - - . . : . . : . - - - - - - I H i g h l
\\.---
DEN
1\
ALE
1
_ _ _ _ _....J
,'---------
TS=Slalus Cycle
TC =Command Cycle
263
SAB 80286
1) Status lines are not driven by SAB 80286 yet
remain high due to pullup resistors in SAB 80288
and SAB 82289 during HOLD state.
2) Address, M/TO and COD/INTA may start floating
during any TC depending on when jnternal
SAB 80286 bus arbiter decides to release bus to
external HOLD. The float starts in 02 of TC.
3) BHE and LOCK may start floating after the end of
any TC depending on when internal SAB 80286
bus arbiter decides to release bus to external
HOLD. The float starts in 01 of TC.
4) The minimum HOLD to HLDA time in shown.
Maximum is one TH longer.
5) The earliest HOLD time is shown. It will always
allow a subsequent memory cycle if pending as
shown.
oj Tne minimum HULU In HLUA time is shown.
Maximum is a function of the instruction, type of
bus cycle and other machine status (i.e., interrupts, waits, lock, etc.)
7) Asynchronous ready allows termination of the
cycle. Synchronous ready does not signal ready
in this example. Synchronous ready state in
ignored after ready is signalled via the asynchronous input.
Processor Extension Transfers
The processor extension interface uses I/O port
addresses 00F8(H), OOFA(H), and OOFC(H) which are
part of the I/O port address range reserved. An ESC
instruction with EM = 0 and TS = 0 will perform I/O
bus operations to one or more of these I/O port
addresses independent of the value of 10PL
and CPL.
ESC instructions with memory references enable
the CPU to accept PEREO inputs for processor
extension operand transfers. The CPU will
determine the operand starting address and read/
write status of the instruction. For each operand
transfer, two orthree bus operations are performed,
one word transfer with I/O port address OOFA(H) and
one or two bus operations with memory. Three bus
operations are required for each word operand
aligned on an odd byte address.
Interrupt Acknowledge Sequence
The figure Interrupt Acknowledge Sequence
illustrates a sequence performed by the SAB 80286
in response to an INTR input. An interrupt acknowledge sequence consists of two INTA bus operations.
The first allows a master SAB 8259A programmable
interrupt controller (PIC) to determine which if any
of its slaves should return the interrupt vector. An
eight-bit vector is read by the SAB 80286 during the
264
second INTA bus operation to select an interrupt
handler routine from the interrupt table.
The master cascade enable (MCE) signal of the
SAB 82288 is used to enable the cascade address
drivers, during INTA bus operations (see interrupt
acknowledge sequence figure), onto the local
address bus for distribution to slave interrupt
controllers via the system address bus. The
SAB 80286 emits the LOCK signal (active LOW)
during TS of both INTA bus operations. A local bus
"hold" request will not be honored until the end of
the second INTA bus operation.
Three idle processor clocks are provided by the
SAB 80286 between INTA bus operations to allow
for the minimum INTA to INTA time and CAS
(cascade address) out delay of the SAB 8259A. The
second INTA bus operation must always have at
least one extra TC state added via logic controlling
READY. A23-AO are in Tri-state OFF until the first
TC state ofthe second INTA bus operation. This
prevents bus contention between the cascade
address drivers and CPU address drivers. The extra
TC state provides time for the SAB 80286 to resume
driving the address lines for subsequent bus
operations.
Local Bus Usage Priorities
The SAB 80286 local bus is shared among several
internal units and external HOLD requests. In caSe of
simultaneous requests, their relative priorities are:
(Highest)
Any transfers which assert LOCK either explicitly
(via the LOCK instruction prefix) or implicitly (I.e.
segment descriptor access, interrupt acknowledge
sequence, or an XCHG with memory).
The second ofthe two byte bus operations required
for an odd-aligned word operand.'
The second or third cycle of a processor extension
data transfer.
Local bus request via HOLD input.
Processor extension data operand transfer via
PEREO input.
Data transfer performed by EU as part of an
instruction.
(Lowest)
An instruction prefetch request from BU. The EU wil
inhibit prefetching two processor clocks in advance
of any data transfer to minimize waiting by EU for a
prefetch to finish.
SAB 80286
Interrupt Acknowledge Sequence
Bus Cycle Type
elK
51· SO
MilO
COO INTA
I
lOCK
SAB
80286
A23-AO.---~-----{,--_o_o_n'_t_ca_re_--,}----~----C
BHE _ _
015-00
Previous
W"te Cycle
--------IOPL.
15. The IF field of the flag word is not updated if
CPL>IOPL. The IOPL field is updated only if
CPL = O.
5. Processor extension segment overrun interrupt
(9) will occur if the operand exceeds the segment
limit.
16. Any violation of privilege rules as applied to the
selector operand does not cause a protection
exception; rather, the instruction does not
return a result and the zero flag is cleared.
Either mode
17. If the starting address of the memory operand
violates a segment limit, or an invalid access is
attempted, a general protection exception (13)
will occur before the ESC instruction is executed.
A stack segment overrun exception (12) will
occur if the stack limit is violated by the
operand's starting address. If a segment limit is
violated during an attempted data transfer
then a processor extension segment overrun
exception (9) occurs.
6. An exception may occur, depending on the value
of the operand.
7. LOCK is automatically asserted regardless of the
presence or absence of the LOCK instruction
prefix.
8. LOCK does not remain active between all
operand transfers.
Protected virtual address mode only
9. A general protection exception (13) will occur if
the memory operand can not be used due to
either a segment limit or access rights violation.
If a stacksegment limit is violated, a stack
segment overrun exception (12) occurs.
18. The destination of an INT, JMP, CALL, RET or
IRET instruction must be in the defined limit of
a code segment or a general protection
exception (13) will occur.
10. For segment load operations, the CPL, RPL and
DPL must agree with privilege rules to avoid an
exception. The segment must be present to
avoid a not-present exception (11). If the SS
register is the destination and a segment notpresent violation occurs, a stack exception (12)
occurs.
281
CX>
'"
'"
en
Instruction Set Summary
»
OJ
00
Function
0
Format
virtual
address
address
mode
mode
Data Transfer
MOV= Move:
Register to registerlmemory
1 000 1 00 w 1 mod reg rim 1
2,3*
2,3*
2
9
Registerlmemory to register
11 000 1 0 1 wi mod reg rim 1
2,5*
2,5*
2
9
Immediate to registerlmemory
11 1 000 1 1 wi mod 000 rim 1
2,3*
2,3*
2
9
Immediate to register
1 101 1 w reg 1
data
2
2
Memory to accumulator
11010000wl
addr-Iow
Accumulator to memory
11010001wl
addr-Iow
data
1 data ifw = 1
1
1
data ifw = 1 ]
addr-high
5
5
2
9
addr-high
3
3
2
9
Registerlmemory to segment register 110001 1 10 Imod 0 reg r/ml
2,5*
17,19 *
2
9, 10, 11
Segment register to registerlmemory 110001 100 Imod 0 reg r/ml
2,3*
2,3*
2
9
PUSH = Push:
Memory
11 1 1 1 1 1 1 1 1mod 1 1 0 rim 1
5*
5*
2
9
Register
1 0 1 0 1 0 reg
3
3
2
9
3
3
2
9
11 000 1 1 1 1 1mod 000 rim 1
5*
5*
2
9
Register
1 0 1 0 1 1 reg
5
5
2
9
Segment register
I 0 0 0 reg 1 1 1 I
5
20
2
9,10,11
POP = Pop:
Memory
1
(reg*01)
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
N
00
en
Clock Count
Function
Real
address
Format
mode
Protected
virtual
address
Comments
Real
address
mode
mode
Protected
virtual
address
mode
Data Transfer (Continued)
POPA
XCHG
Pop AI!
~
1011000011
19
19
2
9
3,5'
3,5*
2, 7
7,9
3
3
5
5
14
5
5
14
Exchange:
Registerlmemory with register
11 0000 1 1 wi mod reg rim
Register with accumulator
11001 0 reg
I
I
IN = Input from:
Fixed port
11110010wl
Variable port
11110110 w
I
port
I
OUT = Output to:
Fixed port
11110011 w
Variable port
11110111W
XLAT = Translate byte to AL
I
port
11 1 0 1 0 1 1 1
I
rim I
rim I
LEA
= Load
EA to reg ister
110001101
mod reg rim
LDS
= Load
pointer to DS
111000101
mod reg
LES
= Load
pointer to ES
LAHF = Load AH with flags
SAHF
~
PUSHF
Store AH into flags
=
Push flags
POPF = Pop flags
111000100
mod reg
3
3
14
3
3
14
5
5
9
3 '
3'
(mod i l l )
7*
21 '
2
9,10,11
(mod"" 11)
7•
21 *
2
9,10,11
2
2
11001 1 1 1 1
11001 1 1 10
2
2
110011100
3
3
2
9
[1001 1 101
5
5
2,4
2,4
en
»
llJ
CO
o
'"w
00
N
CO
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
en
....~
Function
Clock Count
Real
Protected
Format
address
mode
virtual
address
Comments
Real
Protected
address
virtual
mode
address
mode
Arithmetic
ADD = Add:
mode
en
l=tD
CO
o
N
CO
0)
Reglmemory with register to either
100000dw I mod reg. rim
I
Immediate to register memory
11 00000 s w I mod 000 rim I
Immediate to accumulator
10000010wl
data
data
Idata if s w =
(~
I data if w = 1 I
2,7*
2,7*
2
9
3,7*
3,7*
2
9
3
3
ADC = Add with carry:,
Reg memory with register to either
Immediate to registerlmemory
Immediate to accumulator
I 000 1 00 d w I mod reg rim I
_11 00000 s w I mod 0 1 0 rim I
10001010wl
data
Idata if s w = C~
data
I dataifw=1 I
2,7*
2,7*
2
9
2
9
2
9
3,7*
3,7*
3
3
INC = Increment
Register memory
11 1 1 1 1 1 1 w I mod 000 rim I
2,7*
2,7*
Register
101000reg
2
2
I
SUB = Subtract
Reg memory and register to either
I 00 1 0 1 0 d w I mod reg rim I
Immediate from register memory
11 00000 s w I mod 1 0 1 rim I
Immediate from accumulator
10010110wl
data
data
Idata if s w =
O~
I data if w = 1 I
2,7*
2,7*
2
9
3,7*
3,7*
2
9
3
3
,
SSB = Subtract with borrow:
Reglmemory and register to either
1000110dwimodreg rim I
Immediate from registerlmemory
11 00000 s w I mod 01 1 rim I
Immediate from accumulator
10001110wl
-
----------
--
data
data
Idata
I data if w = 1 I
-
--
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
-
ifsw=O~
2,7*
2,7*
2
9
3,7*
3,7*
2
9
3
3
Clock Count
Function
Comments
Real
Protected
Protected
Format
Real
address
mode
virtual
address
mode
address
mode
virtual
address
mode
11111111wlmodOOl r/ml
2,7*
2,7*
2
9
101001 reg 1
2
2
Arithmetic (Continued):
DEC = Decrement:
Register memory
Register
CMP = Compare:
g:
Register memory with register
a a 1 1 1 a 1 wi mod reg rIm 1
2,6*
2,6*
2
9
Register with registerlmemory
a 01 1 10 Owl mod reg rIm 1
2,7*
2,7*
2
9
3,6*
3,6*
2
9
3
3
2
7
Immediate with register memory
1 a a a a a s w 1mod 1 1 1 rIm 1
Immediate with accumulator
001111w
NEG = Change sign
11110 11 w mod a 11 r/ml
2
7*
AAA = ASCII adjust for add
a a 11 a 111
3
3
DAA = Decimal adjust for add
00100111
3
3
1
data
data
1data if s w=Ol 1
1 data if w = 1 1
AAS = ASCII adjust for subtract
a all 1 1 1 1
3
3
DAS = Decimal adjust for substract
00 10 1111
3
3
13
21
16 *
24*
13
21
16 *
24*
2
2
9
9
13
21
16 *
24 *
13
21
16 *
24*
2
2
9
9
MUL = Multiply (unsigned):
register-byte
register-word
memory-byte
menory-word
11 1 1 1 a 1 1 w 1mod 1 a a rIm 1
IMUL = Integer multiply (signed):
register-byte
register-word
memory-byte
memory-word
11 1 1 1 a 1 1 w 1mod 1 a 1 rIm 1
--
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
~
Cl
CO
o
N
CO
C)
en
'"a>
(»
Protected
Function
Format
virtual
l>
IX!
CO
0
N
CO
0)
DIV = Divide unsigned):
register-byte
register-word
memory-byte
memory-word
14
22
17*
25 *
14
22
17*
25 *
6
6
2,6
2,6
6
6
6,9
6,9
17
25
20 *
28 *
17
25
20 *
28 *
6
6
2,6
2,6
6
6
6,9
6,9
16
16
IOIV = Integer divide (signed):
register-byte
register-word
memory-byte
memory-word
11 1 1 1 0 1 1 w 1mod 1 1 1 rim 1
AMM = ASCII adjust for multiply
111010100 100001010 1
AAO = ASCII adjust for divide
111010101 100001010 1
14
14
1100110001
2
2
2
2
CBW = Convert byte to word
CWO = Convert word to double word 11 00 1 1 00 1
!
logic
Shift/Rotate Instructions:
Register/memory by 1
11 101000 w 1 mod ITT rim 1
Register/memory by Cl
11 101001 wi mod ITT rim 1
ITT Instruction
000
ROl
001
ROR
010
RCl
011
RCR
100 SHlISAl
101
SHR
111
SAR
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
I
2,7*
I
2,7*
I
2
I
9
Clock Count
Function
Real
address
mode
Format
Protected
virtual
address
mode
Comments
Real
address
mode
Protected
virtual
address
mode
Arithmetic (Continued):
AND = And:
Reg/memory and register to either
1001 OOOdwl mod reg rim
Immediate to register/memory
11 OOOOOOwlmod 1 00 r/ml
Immediate to accumulator
10010010wl
Reg/memory and register to either
I
11000000 w mod 001
Immediate to accumulator
10000110wl
data
9
3
3
2
9
2
9
3
3
I
data
rim I
I data if w = 1 I
I data if w = 1 I
2,7*
2,7*
2
9
3,7*
3,7*
2
9
3
3
2,7*
2,7*
2
9
3,7*
3,7*
2
9
3
3
2,7*
2,7*
2
9
I
Reg/memory and register to either
10011 OOdwl mod reg rim
Immediate to register/memory
11 OOOOOOwlmod 11 0 r/ml
Immediate to accumulator
10011010wl
NOT = Invert registerlmemory
11 1 1 1 0 1 1 w mod 0 1 0
I
9
2
2,6*
XOR = Exclusive or:
data
2
3,6*
100001 Odwl mod reg rim
Immediate to registerlmemory
2,7*
3,7*
2,6*
data
OR = Or:
2,7*
3,7*
3,6*
I
11010100wl
I data if w = 1 I
I
I
I data I data if w = 1 I
I data if w = 1 I
1100001 owl mod reg rim
Immediate data and register/memory 11 1 1 1 0 1 1 w mod 000 rim
Immediate data and accumulator
data
I data f w = 1
data
TEST = And function to flags, no result:
Register/memory and register
I
data
I data if w = 1 I
I data if w = 1 I
rim I
en
»
D:I
CO
o
~
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
N
CO
O'l
""
Comments
0:>
0:>
Function
Protected
virtual
address
mode
Format
Real
address
mode
Protected
virtual
address
mode
»
!XI
00
0
N
00
en
String Manipulation:
MOVS
= Move byte word
1010010wl
5
5
2
9
CMPS
= Compare byte/word
1010011wl
8
8
2
9
SCAS
= Scan byte/word
1010111wl
7
7
2
9
LODS
= Load byte/wd to ALI AX
10101 10 w
5
5
2
9
1010101wl
3.
3
2
MOVS = Move string
11110010 11010010wl
5
CMPS = Compare string
1111001z 11010011wl
SCAS= Scan string
1111001z 11010111wl
LODS = Load string
11110010 11010110wl
5
STOS = Store string
11110010 i1010101wi
4
STOS = Store byte/wd from ALIA
(J)
I
Repeated by count in CX
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
+ 4n
5
+ 4n
2
9
5
+ 9n
5
+ 8n
5
+ 9n
2,8
8,9
5
+ 8n
2,8
8,9
+ 4n
5
+ 4n
2,8
8,9
+ 3n
4
+ 3n
2,8
Clock Count
Function
Real
address
Format
mode
Protected
virtual
address
mode
Comments
Real
address
mode
Protected
virtual
address
mode
Control transfer
CAll = Call:
disp-Iow
Direct within segment
1111010001
Registerlmemory
indirect within segment
11 1 1 1 1 1 1 1 1mod 0 1 0 rim 1
Direct intersegment
1100110101
1
1
disp-high
1
7+ m
7+m,11+m* 7+m,11+m*
segment offset
1
segment selector
13+ m
11 1 1 1 1 1 1 1 1mod 0 1 1 rim 1 (mod
26 + m
2
18
2,8
8,9,18
2
11,12,18
1
Protected mode only (direct intersegment):
Via cali gate to same privilege level
Via call gate to different privilege level, no parameters
Via call gate to different privilege level, x parameters
Via TSS
Via task gate
Indirect intersegment
7+ m
41 +m
82+m
* 11)
16+n
8,11.12,18
8,11,12,18
86+4x+m
8,11,12,18
177+m
182+m
8,11,12,18
29+n*
8,11,12,18
2
8,9,11,12,18
Protected mode only (indirect intersegment):
Via call gate to same privileg level
Via call gate different privilege level, no parameters
Via call gate to different privilege level, x parameters
ViaTSS
Via task gate
44+m*
83+m*
8,9,11,12,18
90+4x+m¥
8,9,11,12,18
180+m*
185+m*
8,9,11,12,18
8,9,11,12,13
8,9,11,12,18
(J)
l>
CD
CO
o
'"
CD
CD
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems,
N
CO
0)
'"o
Clock Count
CD
Function
Real
address
mode
Format
Protected
virtual
address
Comments
Real
address
mode
mode
Protected
virtual
address
mode
JMP = Unconditional jump:
I
I
11 1 1 0 1 0 1 0 Imod 0 1 0 rim I
Short/long
1111010111
disp-Iow
Direct within segment
1111010011
disp-Iow
1111010101
Protected mode only (direct intersegment):
I
disp-high
I
7+m
7+m
18
7+m
7+m
18
7+m,11+m"" 7+m,11+m*
segment offset
segment selector
I
I
11+m
Via call gate to same privilege level
Via TSS
Via task gate
Indirect intersegment
I
11 1 1 1 1 1 1 1 mod 1 0 1 rim
I
(mod
* 11)
15+m*
Protected mode only (indirect intersegment):
Via call gate to same privilege level
Via TSS
Via task gate
2
9,18
23+m
11,12,18
38+m
175+m
180+m
8,11,12,18
8,11.12,18
8,11,12,18
26+m*
2
41+m*
178+m*
183+m*
8,9,11,12,18
8,9,11,12,18
8,9,11,12,18
8,9,11,12,18
RET = Return from CALL:
Within segment
1110000111
W1thin seg adding immediate to SP
1110000101
I
Intersegment adding immediate to SP ~1 00 1 0 1 0 I
Intersegment
l>
.IX'
CO
c
N
CO
en
Control transfer (Continued):
Register/memory indirect within
segment
Direct intersegment
en
11+m
data-low
I
data-high
I
11100101 1
data-low
I
data-high
I
11+m
2
11+m
l1+m
2
8,9,18
15+m
25+m
2
8,9,11,12,18
2
8,9,11,12,18
15+m
8,9,18
Protected mode only (RET):
To different privilege level
---
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
55+m
9,11,12,18
Clock Count
Format
Function
Real
Protected
address
mode
virtual
address
mode
Comments
Real
Protected
address
mode
virtual
address
mode
Control transfer (Continued):
JE/JZ
= Jump on equal/zero
101110100
disp
7+m or3 7+mor3
18
01111100
disp
7+m or3 7+m or3
18
JLlJNGE = Jump on less/not greater equal
JLE/JNG = Jump on less or equal/not greater
01111110
disp
7+m or3 7+m or3
18
JB/JNAE = Jump on below/not above or equal
01110010
disp
7+m or3 7+m or3
18
JBE/JNA = Jump on below or equal/not above
01110110
disp
7+m or3 7+mor3
18
JP/JPE = Jump on parity/parity even
01111010
disp
7+mor3 7+mor3
18
JO = Jump on overflow
01110000
disp
7+mor3 7+m or3
18
JS = Jump on sign
01111000
disp
7+mor3 7+m or3
18
JNE/JNZ = Jump on not equal/not zero
01110101
disp
7+mor3 7+mor3
18
JNL/JGE = Jump on not less/greater or equal
01111101
disp
7+mor3 7+mor3
18
JNLE/JG = Jump on not less or equal/greater
01111111
disp
7+mor3 7+mor3
18
JNB/JAE = Jump on not below/above or equal
101110011
disp
7+m or3 7+mor3
18
JNBE/JA = Jump on not below or equal/above
101110111
disp
7+mor3 7+m or3
18
JNP/JPO
I
01 1 1 101 1
disp
7+mor3 7+m or3
18
JNO = Jump on not overflow
101110001
disp
7+m or3 7+m or3
18
JNS = Jump on not sign
101111001
disp
7+m or3 7+m or3
18
LOOP = Loop CX times
111100010
disp
8+m or4 8+m or4
18
LOOPZlLOOPE = Loop while zero/equal
111100001
disp
8+m or4 8+m or4
18
LOOPNZ/LOOPNE = Loop while not zero/equal
111100000
disp
8+m or4 8+m or4
18
111100011
disp
8+m or4 8+m or4
18
=
Jump on not par/par odd
JCXZ = Jump on
I\l
ex zero
5'
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
-
en
l>
OJ
CO
oi'.)
CO
0')
U)
I\J
»
O:J
~
Function
Format
CO
o
N
CO
en
Control transfer (Continued):
INT
= Interrupt:
J
Type specified
§01101
Type 3
1110011001
INTO = Interrupt on overflow
1110011101
2,7;S
type
2,7,S
2,6,S
(3 if no
Protected mode only:
Via interrupt or trap gate to same privilege level
Via interrupt or trap gate to fit different privilege level
Via Task Gate
IRET
= Interrupt return
Ul
001111
J
Protected mode only:
To different privilege level
To different task (NT = 1)
Shaded areas indicate instructions not available in SAB SOS6, SOSS microsystems,
interrupt)
I interrupt)
40+m
7S+m
167+m
17+m
131+m
55+m
169+m
7,8,11,12,18
7,8,11,12,18
7,8,11,12,18
2,4
8,9,11.12,15,18
18.9.11.12.15.18
8,9,11,12,18
Clock Count
Format
Function
Comments
Real
Protected
address
virtuaf
address
mode
mode
Real
address
mode
Protected
virtual
address
mode
Processor Control
~
CLC
Clear carry
~
CMC
Complement carry
11111000
2
2
11110101
2
2
STC
~
Set carry
11111001
2
2
CLD
~
Clear direction
11111100
2
2
STD
~
Set direction
11111101
2
2
CLI
~
Clear interrupt
1 1 1 1 10 10
3
3
14
STI
~
Set interrupt
11111011
2
2
14
11110100
2
2
13
WAIT~Wait
10011011
3
3
LOCK
11110000
0
0
HLT
~
Halt
~
Bus lock prefix
E!~m~flea~t'l~~~s~i~~he~~~>J" ~.= JOO 0 01 1 r 1 .1 00 0,0 01
1 0 [""
ESC
~
Processor extension escape
11 1 0 1 1 T T T 1 mod LLL rim 1
SEG
~
Segment override prefix
I 001 reg 110 I
2
, .•.-
.,
'
·1·..
. "
..
_
...
14
:3' ....
..
I"':'-"'~ I-
9-20 *
9-20 *
0
0
5,8
,
. I'
13
8,17
{Tn LLL are opcode to processor extension)
en
l>
ttl
'"
CD
W
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
-
CO
o
N
CO
en
en
If
l>
O:J
CO
o
N
CO
en
Shaded areas indicate instructions not available in SAB 8086, 8088 microsystems.
SAB 80286
Notes:
REG is assigned according to the following table:
The effective address (EA) of the memory operand is
computed according to the mod and rim fields:
if mod = 11 then rim is treated as a REG field
if mod = 00 then OISP = 0*, disp-Iow and disp-high
are absent
if mod = 01 then OISP = disp-Iow sign-extended to
16-bits, disp-high is absent
if mod = 10 then OISP = disp-high: disp-Iow
if rim = 000 then EA = (BX) + (SI) + OISP
if rim = 001 then EA = IBX) + 101) + OISP
if rim = 010 then EA = IBP) + lSI) + OISP
if rim = all then EA = IBP) + (01) + OISP
if rim = 100 then EA = lSI) + OISP
if rim = 101 then EA = 101) + OISP
if rim = 110 then EA = IBP) + OISP*
if rim = 111 then EA = IBX) + OISP
16-bit (w = 1)
000 AX
001 CX
010 OX
011BX
100SP
101 BP
11OS1
111 01
8-bit (w = 0)
000 AL
001 CL
0100L
011BL
100AH
101 CH
1100H
111 01
The physical addresses of all operands addressed
by the BP register are computed using the SS
segment register. The physical addresses of the
destination operands of the string primitive
operations Ithose addressed by the 01 register)
are computed using the ES segment, which may not
be overridden.
OISP follows 2nd byte of instruction (Before data if
required)
* except if mod
=
00 and rim
=
110 then EA
=
disp-high: disp-Iow.
segment override prefix
[ 0 0 1 reg 1 1 0 [
reg is assigned according to the following:
reg
00
01
10
11
Segment
register
ES
CS
SS
OS
295
I
Peripheral and Support Components
SAB 179X
Floppy Disk Formatter!
Controller Family
FEATURES
SAB SAB SAB SAB
1791 1793 1795 1797
Single Density IFM)
X
X
X
X
Double Density (MFM)
X
X
X
X
X
X
True Data Bus
Inverted Data Bus
X
Write Precomp
X
Side Selection Output
X
X
X
X
X
X
•
•
•
•
Two VFO Control Signals-RG & VFOE
Soft Sector Format Compatibility
Automatic Track Seek with Verification
Accomodates Single and Double Density Formats
IBM 3740 Single Density IFM)
IBM System 34 Double Density IMFMI
• Read Mode
Single/Multiple Sector Read with Automatic
Search or Entire Track Read
Selectable 128 Byte or Variable length Sector
• Write Mode
Single/Multiple Sector Write with Automatic
Sector Search
Entire Track Write for Diskette Formatting
• System Compatibility
Double BuHering of Data 8 Bit Bi-Directional
Bus for Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
On-Chip Track and Sector Registers/Comprehensive Status Information
• Programmable Controls
Selectable Track to Track Stepping Time
Side Select Compare
o Write Precompensation
o Window Extension
• Incorprorates Encoding/Decoding
and -Address Mark Circuitry
• For 8" and 5' ,"
Floppy Disks
• Compatible with Industry Standard 179X
Pin Connections
Logic Diagram
floppy Drsk
Interface
Microcomputer
Int~rfa[e
II!
rs
ORO
liE
OOEN
- RClK - -- RG/SSO
- LATE
A'
AI
- EARLY
~WD
lAD
Wf/VFOE
Jill
READY
Om
WD
SAB
OAL4
WG
1?9X
DAlS
TG43
5AI6
HID
OAl7
RAW READ
STEP
RCLK
-w
--- TRO~
--- READY
- - - TG43
--ORa -
INTRa -
OIR(
EARLY
·_-'-WG
- - WPfH
--- WFJVFOE
--
----~SHP
----~DIR(
eLK
eLK
LATE
FiR
VSS
vee
1~ SAB 1791/1793: RG, 5AB 179517 =550
2) SAB 17931SAB 1797= True Bus
SAB 179X is a floppy disk controller family of
N-channel MOS LSI components designed to
interface with SAB 8080/8085/8086/8051 family
- - } Onl' Silo!
-Ilf used)
processors. Its flexibility and ease of use makes It
an ideal floppy disk interface between conventional
floppy disks and all computer systems.
AG 9/84
299
SAB 179X
Pin Definitions and Functions
Symbol
Number
Input II)
Output (0)
NO CONNECTION - Pin 1 is internally connected to a back bias
generator and must be left open by the user.
NC
MR
19
MASTER RESET - A logic low (50I-'S min.) on this input resets
the device and loads HEX 03 into the command register. The Not
Ready (Status Bit 7) is reset during MR ACTIVE. When MR is
brought to a logic high a RESTORE Command is executed,
regardless of the state of the Ready signal from the drive. Also,
HEX I'll is loaded into sector register.
WE
CS
Function
WRITE ENABLE -A logic Iowan this input gates data on the DAL
into the selected register when CS is low.
3
CHIP SELECT
::::r:::;~~c::;
A logic Iowan this input selects the chip and
':::vi-'-'PUlC'1
\...UII II IIUlrici:::IllOn
with the device.
RE
4
READ ENABLE - A logic Iowan this input controls the placement of data from a selected register on the DAL when CS is low.
A0, A1
5,6
REGISTER SELECT LINES - These inputs select the register to
receive/transfer data on the DAL lines under RE andWE control:
ES A 1 AQl
RE
WE
o Ql 0 Status Reg
Command Reg
o 0 1 Track Reg
Track Reg
o 1 0 Sector Reg
Sector Reg
Ql
1
1
Data Reg
Data Reg
DAL0
to
DAL7
7
to
14
ClK
24
DRQ
38
o
DATA REQUEST - This open drain output indicates that the DR
contains assembled data in Read operations, or the DR is empty
In Write operations. This signal is reset when serviced by the
computer through reading or loading the DR In Read or Write
operations, respectively. Use 10K pull-up resistor to + 5V.
INTRQ
39
o
INTERRUPT REQUEST - This open drain output IS set at the
completion of any command and IS reset when the STA rus
register IS read or the command register IS written to. Use 10K
pull-up resistor to i oV,
STEP
15
16
o
o
STEP - The step output contains a pulse for each step.
DIRC
EARLY
17
o
EARLY -Indicates that the WRITE DATA pulse occurrrng
while Early is active (high) should be shifted early for write
precompensation.
LATE
18
o
LATE - Indicates that the write data pulse occurrng while
Late is active (high) should be shifted late for write precompensatian.
300
I/O
DATA ACCESS LINES· Eight bit Inverted (SAB 1791/5) or true
(SAB 1793/7) bidirectional bus used for transfer of data, control,
and status. This bus is receiver enabled by WE or transmitter
enabled by RE. Drive capability IS 1 TTL Load
CLOCK - This input requires a free-running square wave clock
for internal timing reference. 2 MHz ± 1% with 50%
duty cycle. 1 MHz ± 1% for mini-floppies.
DIRECTION - Direction Output is active high when stepping in,
active low when stepping out.
SAB 179X
SYlTIbol
Number
Input (I)
Output (0)
F-unctlon
TEST
n
I
TEST ._. This input IS used for testing purposes only and shoUld
be tied to + 5V or left open by the user unless interfacing to
voice coli actuated motors.
HLT
23
I
RG
25
0
READ GATE (SAB 1791/3) -A high level on this output indicates
to the data separator circuitry that 2 bytes of zeros in single
density, or4 bytes of either zeros or ones in double density have
been encountered, and is used for synchronization.
SSO
25
0
SIDE SELECT OUTPUT (SAB 1795/1797) - The logic level of the
Side Select Output is directly controlled by the ,S' flag in Type II
or III commands. When U ~ 1, SSO is set to a logic 1. When U = 0,
SSO is setto a logic(} The SSO is compared with side information
in the sector ID field. If they do not compare, status bit41RNF) is
set. The Side Select Output is only updated at the beginning of a
Type II or III command. It is forced to a logic 0 upon a MASTER
RESET conditIOn.
RCLK
26
I
RAW READ
27
I
HLD
28
TG43
29
a
WG
30
a
WD
31
a
WRITE DATA - A 200 ns (MFM) or 500 ns IFMI output pulse pe
flux transition. WD contains the unique Address marks as well
as data and clock In both FM and MFM formats.
READY
32
I
READY - This Input indicates disk readiness and is sampled
for a logic high before Read or Write commands are performed.
It Ready is low the Read or Write operation is not performed
and an interrupt is generated. Type I operations are performed
regardless of the state of Ready. The Ready input appears in
inverted format as Status Register bit 7.
------
.
----
-
-
-- r-6
+---
HEAD LOAD TIMING -- When a logic high is found on the HLT
input the head is assumed to be engaged.
-- f--
READ CLOCK - A nominal square-wave clock signal derived
from the data stream must be provided to this input. PhaSing
Ii. e. RCLK transitions) relative to RAW READ is important but
polarity (RCLK high or low) is not .
RAW READ - The data input signal directly from the drive.
This input shall be a negative pulse for each recorded flux
transition.
HEAD LOAD - The HLD output controls the loading of the
Read-Write head against the media.
TRACK GREATER THAN 43 - This output informs the drive that
the Read/Write head is positioned between tracks 44-76. This
output is valid only during Read and Write Commands.
f--
-
WRITE: GATE -- This output IS made valid before writing is to
be performed on the diskette.
U'c
I
SAB179X
Pin Definitions and Functions (continued)
-S-y-m-b-O-------T-N-u-m--b-e-r--r--~~t-(-I)--'I--FL-Jn-c-t-io-n----------------------------------------
.
WFIVFOE
Output (0)
33
I ~A
-
I
1/0
WRITE FAULT VFO ENABLE - This is a bidirectional signal used
to signify writing faults at the drive, and to enable the external
PLO data separator. When WGc 1, Pin 33 functions as a WF input. If WF = 0, any write command will immediately be terminated. When WG = 0, Pin 33 functions as a VFOE output. VFOE
will go low during a read operation after the head has loaded and
settled (HLT - 1). On the SAB 179517, it will remain low until the
last bit of the second CRC byte in the 10 field. VFOE will then go
high until8 bytes (MFM) or4 bytes (FM) pefore the Address Mark.
It will then go active until the last bit ofthe second CRC byte of the
Data Field. Onthe SAB1791/3, VFOEwili lemain low until the end
ofthe Data Field. This pin has an internal 100 kOhm pull-up resistor.
I
"",,-,,,vu
"II':> 11't-'UlIII'VI 'LI~ lilt:: 3Ao iI'S;":
Write head is positioned over Track 00.
lil(H lfl8
KeaaJ
IP
35
I
INDEX PULSE - This input informs the SAB 179X when the
index hole is encountered on the diskette
WPRT
36
I
WRITE PROTECT - This input is sampled whenever a Write
Command is received. A logic low terminates the command
and sets the Write Protect Status bit.
DDEN
37
I
DOUBLE DENSITY - This pin selects either single or double
density operation. When DDEN = 0, double density is selected.
When DDEN = 1, single density is selected.
VCC
21
-
POWER SUPPLY (+5 V).
VDD
40
-
POWER SUPPLY (+ 12 V).
VSS
20
-
GROUND (OV)
-
SAB 179X
~+---~~------+--+-+-----------44---< RAW READ
Write Oata
Ito OlSk)
L----------------
C1J
~
'"
c;S
""-I
CD
X
SAB 179X
IBM System 34 Format 256 Bytes/Sector (S",
Recommended - 128 Bytes/Sector (Mini-Diskette)
Shown below is the IBM dual-density format with
256 bytes/sector. In order io format a diskette the
user must issue the Write Track command and load
the data register with the followll1g values. For
every byte to be written, there is one data request.
Shown below is the Recommended single-density
format with 128 bytes/sector. In order to format a
diskette, the user must issue the Write Track command, and load the data register with the following
values. For every byte to be written, there is one
data request.
Number
of Bytes
Number
of Bytes
80
4E
12
3
00
rr
1)
Hex value of
Byte written
50
1
22
12
3
1
256
1
54
5982 )
F6 (writes (2)
FC (Index Mark)
4E
00
G%~
F5
FE (10 Address Mark)
Track Number (~through 4C)
Side Number (~or 1)
Sector Number (1 through 1A)
01 (Sector length)
F7 (2 CRCs written!
4E
1
11
6
1
128
1
10
369 2)
00
F5 (writes A 1)
FB (Data Adress Mark)
DATA
F7 (2 CRCs written)
4E
4E
1)
2)
3)
1)
2)
Write bracketed field 26 times
Continue writing until SAB 179X interrupts out.
Approx. 598 bytes.
314
Hex Value of
Byte Written
FF (or 00}3)
00
FE (10 Arldress Mark)
Track Numer
Side Number (00 or 01)
Sector Number (1 through lA)
{Sp.r.tnr lpnath!
F7 (2 CRe's written)
FF (or 00)3)
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF (or 00)3)
FF (or 00)3)
Write bracketed field 16 times
Continue writing until SAB 179X interrupts out.
Approx 369 bytes.
Optional '00' on SAB 179517 only.
:D
CD
n
PhY''''~
o
3
3
CD
j
-
46 Bytes
Q.
CD
c..
r--
en
j
(Q
Gap 4
Gapl
10
Post-Index Record
Pre-Index
369 Bytes
No 1
46 Bytes
Gap 2
Data Field
ID Gap
Record
17 Bytes
No 1
10
Oilla Gap Record
16Bytes No 1
Gap 3
Data Field
Gap 2
Record
No 1
Gap 3
10
Record
No 3
Gap 2
Data Field
Record
10
Record
No 16
No 3
Data Field
Gap 2
Record
CD
No 16
C
CD
#
Y
ID Record Byte
4
3
5
6
7
j
Ul
;:;:
<
"T1
o...
3
Data Field Byte
130
2-129
1
131
Data or
ID
Address
Hark
Track
Number
Side
Sector
Sector
eRe
eRe
Number
Number
Length
Byte 1
Byte 2
Deleted
Data
Address
128 Bytes
eRe
of User Data
Byte 1
,
Hark
-s....:
III
me
By" 1
5'
,
c
iii'
,--
Gap1
Gap 7.
7
~
CD
=
Gap 3
.!!.
I
IHEX HI
(HEX FFI
IHEXOII
I
I
[HEX 00)
[HEX FFI
IHEX til
~
f-------- 40 By'"
-
6 By'"
f---------"
I---
Wnt~
gate turn-on
of next d
en
Wnte turn-o fff"upd,"
ta field
of prevIous da
.......
IX!
(Q
X
SAB179X
256 Bytes/Sector (Mini-Diskette)
Non-standards Formats
Shown below is the recommended dual-density
format with 256 bytes/sector. In order to format a
diskette the user must issue the Write Track command and load the data register with the following
values. For every hyte to be written, there is one
data request.
Variations in the recommended formats are possible
to a limited extent if the following requirements
are met:
Number
of Bytes
60
"[ 'j
1
1
22
12
3
1
256
24
718"
Hex value of
Byte written
1) Sector size must be 128, 256, 512 of 1024 bytes.
2) Gap 2 cannot be varied from the recommended
format.
3) 3 bytes of A 1 must be used in MFM.
4E
00
F5 (Writes A 1)
FE (10 Address Mark)
Track Number (0 through 4C)
Side Number (00r 1)
Sector Number (1 through lA)
101 I::;ector Length)
F7 (2 CRCs written)
4E
00
F5 (Writes A 1)
FB (Data Address Mark)
DATA
F7 (2 CRCs written)
4E
4E
1) Write bracketed field 26 times
21 Continue writing until SAB 179X interrupts out.
Approx. 718 bytes.
In addition, the Index Address Mark is not required
foroperation by the SAB 179X. Gap 1, 3, and 41engths
can be as short as 2 bytes for SAB 179X operation,
however PPl lock up time, motor speed variation,
write-splice area, etc. will add more bytes to each
gap to achieve proper operation. It is recommended
that the recommended format be used for highest
system reliability.
FM
MFM
Gapl
Gap II
3)
16 bytes FF
11 bytes FF
6 bytes 00
Gap III
4)
10 bytes FF
4 bytes 00
GaplV
16 bytes FF
32 bytes 4E
22 bytes 4E
12 bytes 00
3 bytes Al
24 bytes 4E
8 bytes 00
3 bytes Al
16 bytes 4E
31 Byte counts must be exact.
4) Byte counts are minimum, except exactly 3 bytes
ofA1 must be written in MFM.
Control Bytes for Initialization
Data Pattern
in DR (Hex.)
00through F4
F5
F6
F7
F8 through FB
FC
FD
FE
FF
SAB 179X Interpretation
in FM (DDEN ~ 1)
SAB 179X Interpretation
in MFM (DDEN ~ 0)
Write 00through F4 with ClK ~ FF
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write F8 through FB, Clk ~ C7, Preser CRC
Write FC with Clk ~ 07
Write FD with Clk ~ FF
Write FE, Clk ~ C7, Present CRC
Write FF with Clk ~ FF
Write 00through F4, in MFM
Write A 1'1 in MFM, Preset CRC
Write C2 21 in MFM
Generate 2 CRC bytes
Write F8 through FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM
11 Missing clock transition between bits 4 and 5
21 Missing clock transition between bits 3 and 4
316
lJ
n
ID
.~
~
cr
"
.f"-
::;
PhY>"~
-=!;
~ ~
o
3
3
~::
ID
::l
c..
c..
~~
ID
~30
<
-------j
"
'"
2
72 Bytes
Gap 4
Gap 1
Pre"lndex
Post-Index
718 Bytes
72 Bytes
I--
o
o
All)
3 Bytes
Gap3
10
Gap2
Record 10 Gap
Data Gap
Nol 34Bytes 39 Bytes
------~
//
Byte
2
1
1
4
Oata
Field
Data
10
Record
Record
N,l
Gap2
No 2
Gap 3
Mark
HEX FE
J
G,
IHEX 4Ei
Record
Gap 2
No 1
No 2
O
:;j
of next data field
~
12Bytes-
------- 24 8ytes
12 BYtes-l
~
~
CJ)
l>
Write turn-off for update
of prevlOus data field
'"
.....
....,
<0
X
SAB179X
Absolute maximum ratings 1)
o to 70'C
-65 to + 150°C
+15 to -0.3 V
+15 to -0.3 V
Operating Temperature
Storage Temperatur~
VDD with Respect to Vss (Ground)
Max. Voltage to any Input with
Respect to VSS
D. C. Characteristics
= 0 to 70° C; VDD ~ + 12 V ±
TA
5%; VCC
~=
Symbol Parameter
IlL
Input Leakage
Output Leakage
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
ICC
Typ.
IDD
PO
---
-
Power Supply Current
Power Dissipation
10
il A
-2.8
-- 1-----
0.8
045
--..
60
m.l\~
~-
10
I--
-
'---
15
----
VDD"
10=- lOO v A
1--._---
--- i-----.
-
=
VOUT = VDD
-
I----
1---- V
35
VIN
-----
-
.-
Test Condition
Max.
L __
2.6
e-.--
Power Supply Current
Unit
Limit Values
Min.
IOL
= OV
+ 5V ± 5%; VSS
I----~.---
'N
06
~--.-
10
=
1.6mA
--
Capacitance3 )
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
11
Limit Value
(max.)
15
Unit
Test Condition
pF
Unmeasured pins
returned to GND
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
21 Leakage conditions are for input pins without internal pull-up resistors.
31
This parameter is periodically sampled and not 100% tested.
318
SAB 179X
A.C. Characteristics
TA=Oto70C,VDD= +12V± 5%; VSS=OV,VCC= +5V± 5%
All timing readings at VOL
0.8 V and VOH
2.0 V
Read Enable Timing
Symbol
Parameter
Limit Values
Min.
m:
TSET
Setup AD DR & CS to
THLD
Hold ADDR & CS from RE
TRE
RE Pulse Width
TDRR
DRO Reset from RE
TIRR
INTRO Reset from RE
Typ.
Max.
-
-
Unit
Test Condition
-
50
10
400
TDACC
Data Access from RE
TDOH
Data Hold from RE
CL = 50pf
-
r
DRQ~
oc
500
500
3000
ns
-
350
-
50
lTDRRI~"'16
400
CL = 50pf
f---
150
----------l
l2~s
i
I
VOH
I
I
I
I
INTRO
-TiRR----1
I
~
I
T Servu,,2)-
VOL
THLDi
VIL
VIH
RE
I
I
TSET -
I
TBAU
I
Valid
DRO rising edge:
DRO falling edge:
INTRO rising edge:
INTRO fallinC] edqe:
I
Data
l~TDDH~
T DACC
Indicates that the data register has dssembled data.
Indicates that the data register was read.
Occurs at end of command.
Indicates that the status register was read.
11
CS may be permanently tied LOW if desire~.
3'
Times double when CLK= 1MHz
21
T Service (worst case)
- FM = 27.5f.Ls
- MFM = 13.5 f.Ls
319
SAB 179X
Write Enable Timing
Symbol
Parameter
Limit Values
Min.
TSET
Setup ADDR & CS to WE
THLD
Hold ADDR & CS from WE
TWE
WE Pulse Width
TDRR
DRO Reset from WE
TIRR
INTRO Reset from WE
TDS
Data Setup to WE
TDH
Data Hold from WE
Max.
-
-
Units
Test Conditions
50
10
350
-
ns
-
250
400
500
500
3000
-
-
70
I'
ORO
Typ.
--rORRi ",16
~
31~s
1
---'r-
I I'--______
I
i
or
VOL
I
r--TIRR---··-II
-+I________...,i
INTRQ '\-,_+I_ _ _
I
I
IL----VOL
21
r - - - T SerVI~e -==1THLOr--
L,",-~I
I
1.----------
A0A1TI11~=
--VIC
WE
·SET
OAL
~
---------,1
.
I
I
Data must
be valid
VIH
~-----------
.
--L±.s L
T OH
DRO rising edge:
DRO falling edge:
INTRO rising edge:
INTRO failing edge:
Indicates that the data register is empty.
Indicates that the data register is loaded.
Indicate the end of a command.
Indicates that the command register is written to.
II
CS may be permanently tied LOW if desired. When writing Data into Sector Track or Data Register User
cannot read this Register until at least 4(.ts in MFM after the rising edge of WE when writing into the
command Register Status is not valid until some 28(.ts in FM, 14 '"s in MFIVi later.
21
T Service (worst case); FM
= 23.5 jlS; MFM = 11.5 jls
31 Times double when CLK= 1MHz
320
SAB 179X
Input Data Timing
Symbol
limit Values
Parameter
Min.
Tpw
RAW READ Pulse Width
Tbc
RAW READ Cycle Time"
Tc
RClK Cycle Time 31
Tx1
RClK hold to RAW READ
Tx2
RAW READ hold to RClK
11
21
31
Typ.
100
200
1500
2000
Units
Test Conditions
Max.
1)
1800 ns @ 70°C
-
ns
-
40
1)
1)
Pulse width on RAW READ (Pin 27) is normally 100 - 300ns. However, pulse may be any width if pulse is
entirely within window. If pulse occurs in both windows, then pulse width must be less than 300ns for
MFM at ClK = 2MHz and 600ns for FM at 2MHz. Times double for 1MHz.
tbc should be 2 f1.S, nominal in MFM and 4 f1.S nominal in FM. Times double when ClK = 1 MHz.
RClK may be high or low during RAW READ (Polarity is unimportant).
RAW REAO
---1
Tbe
if
"ls-
T '~TX21
Xl
1
I
RCLK
I
I
.1. Tb-~
Te
C=Ta
Nominal
Diskette
8"
8"
5"
5"
Mode
I
DDEN
MFM
FM
MFM
FM
I
I
0
I
0
i
1
1
ClK
2 MHz
2 MHz
1 MHz
1 MHz
Ta
I
Tb
Tc
1 f1.S
2 f1.s
2 f1.s
4f1.s
!
1 f1.S
2 f1.s
2 f1.s
4f1.s
2 f1.S
4f1.s
4f1.s
8f1.s
I
A PPl Data Separator IS recommended for 8" MFM
321
SAB179X
Write Data Timing (All Times Double when elK
=
1 MHz)
Symbol Parameter
Limit Values
Min.
450
150
Twp
Write Data Pulse Width
Twg
Write Gate to Write Data
Tbc
Write data cycle Time
Ts
Early (late) to Write Data
Th
Early (late) from Write Data
Twf
Write Gate off from WD
Twd1
WD Valid to ClK
Twd2
-
Max.
550
250
Il'p·
500
200
-
2
1
I
-
FM
MFM
FM
MFM
± ClK Error
ns
MFM
p's
FM
MFM
-
I
1-
100
30
ns
p's
2
1
-
WD V"lid after ClK
Test Conditions
2,3
or4
125
100
50
Units
ClK
ClK
ns
= 1MH7
= 2MHz
ClK = 1MHz
ClK = 2MHz
I
,-------------------.---------------------------------------------------,
r---SOGOS
eLK
11 MHz)
I
L
'---1
L
J
___________
I
I
WD
~~~I~
1wd1..[ I
I
--r~
1125ns.~12Snsl
eLK
--l'
12MHZ)IL-_ _ _
. I
L
I
~I_~
WD ------------------"-""-.:...:..L..'-"T'f'w':;d1:"':.1
I
r
--,
b
Twd2
Write Data/Clock Relationship (DDEN = 0)
WD must have rising edge in fi;st shaded area and trailing edge in second shaded area
322
SAB 179X
Miscellaneous Timing
Symbol
Limit Values
Parameter
Min.
TCD1
Clock Duty (lOW)
230
TCD2
Clock Duty (HIGH)
200
TSTP
Step Pu Ise Output
20r4
TDIR
Dir Setup to Step
-
TMR
Master Reset Pulse Width
50
TIP
Index Pulse Width
10
TWF
Write Fault Pulse Width
20
iP
Typ.
1
Test Conditions
20000
ns
-
iJ-s
2)
12
(',-J- - - - - ,
Units
Max.
-
± ClK Error
2)
,------I() VIH
1
~TIP--!
Wi'
MR
1',------,1
- - - - - - I I VIH
'I
~TWf~
------,1
"------1\ VIH
1-\
~TMR~
r CYC1
CLKlJL
T
~T±Dl
!CD2
VOH
DIRe VOL
-.J1
L
Step 10
_t:R1R0~
i--TDIRlTSTPr iTSTPr
\'1
""1-----i--TDIR1TSTPr
STEPVOH~~
VOI~
1)
2)
From step rate table.
Times double when ClK~1 MHz
323
SAlS 21@}{A
f~(Q)~LQ)~ []O~~ [F@[JmBlt~~rr!
C~rruit[j(Q)~~®[f f@mn~y
Features
SAB SAB SAB SAB
2791A 2793A 2795A 2797A
Single Density (FMI
X
X
X
X
Double Density IMFMI
X
X
X
'x
X
True Data Bus
X
Inverted Data Bus
X
X
Side Select Output
X
Internal ClK Divide
X
X
X
o On-Chip Pll Data Separator
o On-Chip Write Precompensation logic
Pin Connections
o Single +5V Supply
o Accommodates Single and Double Density Formats
IBM 3740 Single Density (FMI
IBM System 34 Double Density (MFMI
o Automatic Seek with Verify
o Multiple Sector ReadlWrite
o TTL Compatible
o Programable Control
Selectable Track-to-Track Access
Head load Timing
o Software Compatible with the SAB 179X Floppy
Disk Formatter/Controller Family
o Soft Sector Format Compatibility
Logic Diagram
Hltrocomput
ENP
Interface
lIE
t!:
Floppy DISK
"
Irlterfatf
RAW READ
DATA!Sl
l
WD
A'A1
rrrr
1 - - - RPW
----
WPW
rr - - - -
yeo
l1l
PUHP
Ii[
ENP
~/8
ffil
SAB
279XA
_._--
IN"H"F/SSO
WG
WPRT
Il'
- - - i'R00
'"
PUMP
ORa
INTRa
CLK
-------
SAB 2791AI2793A =ENMF 21 SAB 2793AI2797A =True Bus
SAB 2795AI2797 A= ssa
SAB 279XA is a floppy disk controller family of
N-channel MOS lSI components designed to
interface with SAB 8080/8051 family processors.
Its flexibility and ease of use makes it an ideal
floppy disk interface between conventional floppy
disks and all computer systems. Software com·
patible with its predecessor, the SAB 179X, the
device also contains a high performance Phase·
READY
TG 43
STEP
DIRC
HlO
HLT
I
1
}
One Shot
(If used)
lock·Loop Data Separator as well as Write Pre·
compensation Logic.
When operating in Double Density mode, Write
Precompensation is automatically engaged to a
value programmed via an external potentiometer.
An on·chip veo and phase comparator allows
adjustable frequency range for 5%"-8" Floppy
Disk and Micro Floppy Disk Interface.
AG 4/84
325
SAB279XA
Pin Definitions and Functions
Symbol
Number
Input (II
Output(OI
Functions
ENP
1
I
ENABLE PRECOMPA logic high on this input enables write precompensation
to be performed on the Write Data output
WE
2
I
WRITE ENABLEA logic Iowan this input gates data on the DAL into the
selected register when CS is low
CS
3
I
CHIP SELECTA logic Iowan this input selects the chip and enables computer
communication with the device
RE
4
I
READ ENABLE
A logic Iowan this input ~ontrols the placement of data from a
__ 1 __ ," __ '
._.'_,,- _ _
~\:;Il:;""'~C;U' C~I;:)lt;::1
"
.......... ,
UII U It:: L.JML
•
VVII~r
-;;::;:-;;;;: • •
I 1.,...;:)
I~
IUW
A0,Al
5,6
I
REGISTER SELECT LlNESThese inputs select the reg ister to receive/transfer data on the
DAL lines under RE and WE control:
RE
CS Al A([)
WE
([)
\)
Status Register
0
Command Register
\)
\)
1
Track Register
Track Register
\)
Sector Register
Sector Register
0
1
1
1
Data Register
Data Register
0
DAL0to
DAL7
7-14
I/O
DATA ACCESS LlNESEight bit directional bus used for transfer of commands,
status and data, These lines are inverted on SAB 2791A and
SAB 2795A.
STEP
15
0
STEPThe step output conta i ns a pulse for each step
DIRC
16
a
DIRECTIONDirection output is active high when stepping in, active low
when stepping out
5i8
17
I
5 'i,', 8" SELECT This input selects the internal VCO frequency for use with 5'/,'
drivesor8" drives
RPW
18
I
READ PULSE WIDTHAn external potentiometer tied to this input controls the phase
comparator within the data separator
MR
19
I
MASTER RESET
A logic low (50 !J.sec min.1 on this input resets the device and
loads hex 03 into the command register. The Not Ready bit
(Status bit 7) is reset during MR active. When MR is brought
to a logic high a Restore command is executed, regardless of
the state of the Ready signal from the drive. Also hex 01 is
loaded into Sector Register.
TEST
22
I
TESTA logic Iowan this input allows adjustment of external
resistors by enabl i ng internal signals to appear on selected pins
326
SAB 279XA
Symbol
Number
Input (I)
Output(O)
Functions
PUMP
23
0
PUMPHigh-impedance output signal which is forced high or low to
increase/decrease the VCO frequency
ClK
24
I
ClOCKThis input requires a free-running 50% duty cycle square wave
clock for internal timing reference, 2 MHz ± 1% for 8" drives,
1 MHz ±1 % for mini-floppies
ENMF
25
I
ENABLE MINI-FLOPPY (SAB 2791A/2793A)A logic low on this input enables an internal divide by 2 of the
master clock. This allows both 5'/4' and 8" drive operation with
a single 2 MHz clock. For a 1 MHz clock on Pin 24, this line must
be left open or tied to a logic 1
SSO
25
0
SIDE SELECT OUTPUT(SAB 2795A/2797 A)The logic level of the Side Select output is directly controlled
by the U flag in Type II or III commands. When U ~ 1, SSO is set
to a logic 1. When U ~ 0, SSO is set to a logic 0. The SSO is
compared with the side information in the sector ID field. If they
do not compare, Status Bit 4 (RNF) is set. The Side Select output
is only updated atthe beginning of a Type II or III command. It is
forced to a logic 0 upon a master reset condition
VCO
26
-
VOLTAGE CONTROllED OSCILlATORAn external capacitor tied to this pin adjusts the VCO center
frequency
RAW READ
27
I
RAW READThe data input signal directly from the drive. This input shall
be a negative pulse for each recorded flux transition
HlD
28
0
HEAD LOADThe HlD output controls the loading ofthe ReadlWrite head
against the media
TG43
29
0
TRACK GREATER THAN 43This output informs the drive that the ReadlWrite head is
positioned between tracks 44 and 76. This output is valid only
during read and write commands
WG
30
0
WRITE GATEThis output is made valid before writing is to be performed on
the diskette
WD
31
0
WRITE DATAMFM or FM output pulse perflux transition. WD contains the
unique address marks as well as data and clock in both FM and
MFMformats
READY
32
I
READYThis input indicates disk readiness and is sampled for a logic
high before read or write commands are performed. If Ready is
low the read orwrite operation is not performed and an
interrupt is generated. Type I operations are performed
regardless of the state of Ready. The Ready input appears in
inverted format as Status Register bit 7
327
I
SAB279XA
Pin Definitions and Functions (continued)
Symbol
Number
Input (II
Output (01
Functions
WPW
33
I
WRITE PRECOMPWIDTHAn external potentiometertied to this input controls the amount
of delay in write precompensation mode
TR00
34
I
TRACK00This input informs the SAB 279XA that the Read/Write head
is positioned over Track 00
IP
35
I
WPRT
INDEX PULSEThis input informs the SAB 279XA when the index hole is
encountered on the diskette
36
------
- f-I
WRITE PROTECTThis input is sampled whenever a write command is received.
A logic lOW terminates the command and sets the Write Protect
status bit
37
I
DOUBLE DENSITYThis input pin selects either single or double density operation.
When DDEN ~ 0, double density is selected. When DDEN' ~~ 1,
single density is selected
38
o
DATA REQUESTThis output indicates that the Data Register contains
assembled data in rend operations, or the DR is empty iri write
operations. This signal is reset when serviced by the computer
through reading or loading the Data Register
r'lP
I
DDEN
----
--DRQ
,
I
L.
INTRQ
HLT - - - -
- - - - - --vce
~--To-
L
I
40--·-----1
~
21
_
--
--
INTERRUPT REQUEST-
I ThiS output is set althe completion of any command and is reset
I when! he Status Register is read orthe Command Register is
written to
i ---~-EADLOADTIMINGWhen a logiC high IS found on the HLT Input the head IS assumed
to be engaged. It IS tYPically derrvGd from a Single shot trrggered
byHI D
t
- - ----
----------
POWER SUPF'L Y (+51/1
\iSs _ =~ .=[l"0--· .:-= ..... ~. :-- ~_: =~:. -G~?~~~E ~l:~~=-=-_ ~~.
328
___________.
SAB279XA
Block Diagram
,"(fAIN READ
I
Write Data
ITo o.sk)
I
RCLK
VCO
PUMP
ORa
INTRa
(omput'!r
AI
AI
Interface
Control
Control
PLA
(ontl'Ql
1230,,6)
(ontrol
Olsk
Interface
READY
STEP
DlRC
(ontrol
!liMF/SSO
CLK
HLO
HLT
329
SAB 279XA
General Description .
The SAB 279XA are N-channel MOS LSI devices
which perform the functions of a Floppy Disk
Formatter/Controller in a single chip implementation_ The SAB 279XA is IBM 3740 compatible in
single density mode (FM) and System 34 compatible in Double Density Mode (M FM)_ The
SAB 297XA contains all the features of its predecessor, the SAB 179X, plus a high performance
phase-Iock-Iopp data separator as well as write
precompensation logic_ In double density mode,
write precompensation is automatically engaged to
a value programmed via an external potentiometer.
In order to maintain compatibility, the SAB 179X
and SAB 279XA designs were made as close as
possible with the computer interface, instruction
set, and I/O registers being identical. Also, head
load control is identical in each case, the actual pin
assignments vary only by a few pins from any
one to another.
The processor interface consists of an S-bit bidirectional bus for data, status, and control word
transfers. The SAB 279XA is set up to operate on a
multiplexed bus with other bus-oriented devices.
The SAB 279XA is TTL compatible on all inputs and
outputs. The outputs will drive one TTL load or three
LS loads. The SAB 2793A is identical with the
SAB 2791A, except that the DAL lines are true for
systems that utilize true data busses.
The SAB 2795A/97 A has a side select output for controlling double sided drives.
Organization
The Floppy Disk Formatter block diagram is
illustrated on page 5. The primary sections include
the parallel processor interface and the Floppy Disk
interface.
Data Shift Register (DSR) - This S-bit register
assembles serial data from the Read Data input
(RAW READ) during read operations and transfers
serial data to the Write Data output during write
operations.
Data Register(DR)- This S-bit register is used as a holding register during disk read and write operations. In
disk read operations the assembled data byte is
transferred in parallel to the Data Register from the
Data Shift Register. In disk write operations information
is transferred in parallel from the Data Register to the
Data Shift Register. When executing the Seek
command the Data Register holds the address of the
desired track position. This register is loaded from the
DAL and gated onto the DAL under processor control.
Track Register (TR) - This R-nit register holds the
track number olthe current ReadlWrite head position.
It is incremented by one every time the head is
stepped in (towards track 76) and decremented by
one when the head is stepped out (towards track
00). The contents of the register are compared with
the recorded track number in the ID field during
disk read, write and verify operations. The Track
Register can be loaded from or transferred to the
DAL. This register should not be loaded when the
device is busy.
Sector Register (SR) - This S-bit register holds the
address of the desired sector position. The contents
of the register are compared with the recorded
sector number in the ID field during disk read or
write operations. The Sector Register contents
can be loaded from or transferred to the DAL. This
register should not be loaded when the device is busy.
330
Command Register (CR) - This S-bit register holds
the command presently being executed_ This
register should not be loaded when the device is
busy unless the new command is a Force Interrupt
command. The command register can be loaded
from the DAL, but not read onto the DAL.
Status Register (STR) - This S-bit register holds
device status information. The meaning of the
status bits is a function of the type of command
previously executed. This register can be read onto
the DAL, but not loaded from the DAL.
CRC Logic- This logic is used to check orto generate
the 16-bit Cyclic Redundancy Check (CRC). The
polynomial is: Glx) ~ X '6 + x" + x 5 + 1
The CRC includes all information starting with the
address mark und up to the CRC character. The CRC
register is preset to ones prior to data being shifted
through the circuit.
Arithmetic/Logic Unit (ALU) - The ALU is a serial
comparator, incrementer, and decrementer and is
used for register modification and comparisons
with the disk recorded ID field.
Timing and Control- All computer and Floppy Disk
interface controls are generated through this logic.
The internal device timing is generated from an
external crystal clock_
AM Detector - The address mark detector detects
ID, data and index address marks during read and
write operations.
Write Precompensation - enables write precompensation to be performed on the Write Data
output.
Data Separator - a high performance phase-Iockloop data separator with on-chip VCO and phase
comparator allows adjustable frequency range for
5';;' or S" Floppy Disk interfacing.
SAB 279XA
Processor Interface
The interface to the processor is accomplished
through the eight Data Access Lines (DAL) and
associated control signals. The DAL are used to
transfer data, status, and control words out of, or
Into the SAB 279XA. The DAL are three state buffers
that are enabled as output drivers when Chip Select
(tS) and Read Enable (RE) are active (low logic state)
or act as input receivers when CS and Write Enable
(WE) are active.
When transfer of data with the Floppy Disk Controller is required by the host processor, the device
address is decoded and CS is made low. The address
bits A 1 and AG, combined with the signals RE
during a read operation or WE during a write
operation are interpreted as selector for the following
registers:
A1
A0
"" "
1
1
1
0
1
READ
WRITE
Status Register
Track Register
Sector Register
Data Register
Command Register
Track Register
Sector Register
Data Register
During direct memory access (DMA) types of data
are transferred between the Data Register of the
SAB 279XA and the processor, the Data Request
(DRO) output is used in data transfer control
This
signal also appears as status bit 1 during read and
write operations.
In disk read operations the Data Request is activated (set high) when an assembled serial input byte
is transferred in parallel to the Data Register. This
bit is cleared when the Data Register is read by the
processor. If the Data Register is read after one or
more characters have been lost by having transferred new data into the register prior to processor
readout, the Lost Data bit is set in the Status Register.
The read operation continues until the end of sector
is reached.
In disk write operations the Data Request is activated when the Data Register transfers its contents
to the Data Shift Register, and requires a new data
byte. It is reset when the Data Register is loaded with
new data by the processor. If new data is not
loaded at the time the next serial byte is required by
the Floppy Disk, a byte of zeroes is written on the
diskette and the Lost Data bit is set in the Status
Register.
Upon completion of every command an INTRO is
generated. INTRO is reset either by reading the
Status Register or by loading the Command Register
with a new command. In addition, INTRO is generated if a Force Interrupt command condition Is met.
The SAB 279XA has two modes of operating depending on the state of DDEN (Pin 37). When DDEN ~ 1,
Single Density (FM) is selected. When DDEN ~ 0,
Double Density (MFM) is selected. In either case, the
elK input (Pin 24) is set at 2 MHz for 8" drives or
1 MHz for 5'//' drives.
On the SAB 2791A12793A, the ENMF input (Pin 25) can
be used for controlling both, 5%" and 8" drives with
a single 2 MHz clock. When ENMF ~ 0, an internal
divide by 2 of the CLK is performed. When EN MF ~ 1,
no divide takes place. This allows the use of a 2 MHz
clock for both, 5'/4' and 8" configurations.
The internal VCO frequency must also be set to the
proper value. The 5/8 input (Pin 17) is used to select
data separator operation by internally dividing the
read clock. When 5/8 ~ 0, 5'/," data separation is
selected; when 518 ~ 1,8" drive data separation is
selected.
CLOCK (24) ENMF (25)
5/8 (17)
DRIVE
2MHz
2MHz
1 MHz
1
0
8"
5' I,
'"
5' I,
'"
1
0
1
0
All other conditions are invalid.
331
I
SAB279XA
Functional Description
The SAB 279XA is software compatible with the
SAB 179X series of Floppy Disk Controllers.
Commands, status, and data transfers are performed in the same way. Software generated forthe
SAB 179X can be transferred to a SAB 279XA system
without modification.
In addition to the SAB 179X, the SAB 279XA contains an
internal data separator and write precompensation
circuit. The TEST (Pin 22) line is used to adjust both,
data separator and precompensation. When TEST 00,
the WD (Pin 31) line is internally connected to the
output of the write precomp single shot. Adjustment
of the WPW (Pin 33) line can then be accomplished.
A second single shot tracks the precomp setting at
approximately 3: 1 to ensure adequate Write Data
!1ld~p wirlthc:.
to
rn€,~~ 0~!\"~ ~~~S!f~~::t:8~:.
Similarly, data separation is also adjusted with
TEST ~ 0. The TG43 (Pin 29) line is internally
connected tothe output of the read data single shot,
which is adjusted via the RPW (Pin 18) line. The
DIRC (Pin 16) line contains the read clock output
(500 kHz for 8" drives). The VCO trimming capacitor
(Pin 26) is adjusted to center frequency.
Internal timing signals are used to generate pulses
during the adjustment mode so that these adjust·
ments can be made while the device is in operation.
The TEST line also contains a pull·up resistor, so
adjustments can be performed simply by grounding
the TEST pin, overriding the pull-up. The TEST pin
cannot be used to disable stepping rates during
operation as its function is quite different from the
SAB 179X.
Other pins on the device also include pull-up
resistors and may be left open to satisfy a logic 1
condition. These are: ENP, 518, ENMF. WPRT,
DDEN, HLT, TEST, and MR.
General Disk Read Operation
Sector lengths of 128, 256, 512 or 1024 are obtai n·
able either in FM or MFM formats. For FM, DDEN
should be placed to logic 1. For MFM formats,
DDEN should be placed to a logic 0. Sector
lengths are determined at format time by the fourth
byte in the ID field.
Sector Length Table*
Sector Length
Field (hex)
NumberofBytes
in Sector (decimal)
00
128
256
512
1024
01
02
03
• SAB 2795A/97 A may vary· see command summary.
332
The number of sectors per track as far as the
SAB 279XA is concerned can be from 1 to 255 sectors.
The number of tracks as far as the SAB 279XA is con·
cerned is from 0 to 255 tracks. For IBM 3740
compatibility, sector lengths are 128 bytes with 26
sectors per track. For System 34 compatibility
(MFM), sector lengths are 256 bytes/sector with 26
sectors/track; or lengths of 1024 bytes/sector with
8 sectors/track.
General Disk Write Operation
When writing is to take place on the diskette the
Write Gate (WG) output is activated, allowing
current to flow into the ReadiWrite head. As a
i-'!'"es~~t:8:;:8 8:-:-8;--:::C~:; '¥'¥';-i~i,,~ t:,0 1;, ~i. uald UYlt
must be loaded into the Data Register in response
to a Data Request from the SAB 279XA before the
Write Gate Signal can be activated.
Writing is inhibited when the Write Protect input is
logic low, in which case any write command is
immediately terminated, an interrupt is generated
and the Write Protect status bit is set.
For write operations, the SAB 279XA provides Write
Gate (Pin 30) and Write Data (Pin 31) outputs. Write
Data consists of a series of pulses set to a width
approximately three times greater than the pre·
comp adjustment. Write Data provides the unique
address marks in both formats.
Ready
Whenever a read or write command (Type II or III) is
received the SAB 279XA samples the Ready input. If
this input is logic low the command is not executed
and an interrupt is generated. All Type I commands
are performed regardless of the state of the Ready
input. Also, whenever a Type II or III command is
received. the TG43 signal output is updated.
TG 43 may be tied to ENP to enable write precompensation on tracks 44-76.
SAB279XA
Write Precompensation
veo Operation
When operating in double density mode (DDEN ~
0), the SAB 279XA has the capability of providing a
user-defined precompensatlon value for Write Data.
An external potentiometer (10K) tied to the WPW
signal (Pin 33) allows a setting of 100 to 300 ns
from nominal.
Setting the write precomp value is accomplished by
forcing the TEST line (Pin 22) to a logic 0. A stream
of pulses can then be seen on the Write Data (Pin 31)
line. Adjust the WPW Potentiometer for the desired
pulse width. This adjustment may be performed incircuit since Write Gate (Pin 30) is inactive while
TEST ~ 0.
After adjustments have been made, the TEST pin
is returned to a logiC 1 and the device is ready for
operation. Adjustments may be made in-circuit
since the DIRe and TG43 lines may toggle without
affecting the drive.
The PUMP output (Pin 23) consists of positive and
negative pulses. Their duration is equivalent to
the pnase difference of incoming Data vs. veo
frequency. This signai is imernaily connected to the
veo input, but a filter is needed to connect these
pulses to a slow moving De Voltage.
The internal phase-detector is unsymmetrical for a
random distribution of data pulses by a factor of
two, in favor of a PUMP UP condition. Therefore it is
desirable to have a PUMP DOWN !wice as responsive to prevent run-away during a lock attempt.
A first order lag-lead filter can be used at the PUMP
output (PIN 23). This filter controls the instantaneous response of the veo to bit-shifted data (jitter)
as well as the response to normal frequency shift i.e.
the lock-up time. A balance must be accomplished
between the two conditions to inhibit overresponsiveness to jitter and to prevent an extremely wide
lock-up response leading to PUMP run-away. The
filter affects these two reactions in mutually
opposite directions.
Data Separation
The SAB 279XA can operate with either an external
data separator or its own internal recovery circuit.
The condition of the TEST line (Pin 22) in conjunction with MR (Pin 19) wiil select internal or external
mode.
To program the SAB 279XA for external veo, a MR
pulse must be applied while TEST ~ 0. A clock
equivalent to eight times the data rate (e. g., 4.0 MHz
for 8" double density) is applied to the veo input
(Pin 26). The feedback reference voltage is available
on the Pump output (Pin 23) for external integration
to control the veo. TEST is returned to a logic 1 for
normal operation. Note: To maintain this mode,
TEST must be held low whenever MR is applied.
For internal veo operation, the TEST line must be
high during the MR pulse, then set to a logic" for
the adjustment procedure.
A 50 k Potentiometer tied to the RPW input (pin 18)
is used to set the internal Read Data pulse for proper
phasing. With a scope on Pin 29 (TG43). adjust the
RPW pulse for 118 of the data rate (250 ns for 8"
Double Density). An externai variable capacitor of
typically 5-60 pF is tied to the veo input (Pin 26) for
adjusting center frequency. With a frequency counter
on Pin 16 (DIRe) adjust the trimmer cap to yield the
appropriate data rate (500 kHz for 8" Double
Density). The DDEN line must be low while the
5/8 line is held high or the adjustment times above
will be doubled.
The following Filter Circuit is recommended
for8" FM/MFM:
2311
Pump
(Pin
O.l~f
Since 5'/ 4' Drives operate at exactly one-half the
data rate (250 Kbytes/sec) the above capacitor
should be doubled to 0.2 or 0.22 iLF.
333
I
SAB279XA
Command Summary
Commands for SAB 2791A, SAB 2793A
Commands for SAB 2795A. SAB 2797A
Bits
Type Command
I
I
I
I
I
Restore
Seek
Step
Step-in
Step-out
Read-Sector
Write Sector
Read Address
Read Track
Write Track
Force Interrupt
II
II
III
III
III
IV
Bits
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
T
T
T
m
m
0
0
1
h
h
h
h
h
V
V
V
V
V
L
L
E
E
E
1
1
1
r.
r.
r.
r.
r.
0
a.
0
0
0
I. ,
0
0
0
1
1
0
0
1
h
h
h
h
h
S
S
0
0
0
I,
r,
r,
r,
r,
r,
1
0
1
T
T
T
m
m
0
0
1
1
V
V
V
V
V
1
1
1
0
0
1
0
1
0
1
0
1
1
0
r,
r,
r,
r,
r,
U
U
U
U
U
r.
r.
r.
r.
r.
0
a.
0
0
0
1~
I;
(I
0
(I
E
E
E
E
E
I,
C
C
0
0
0
I.
1
1
1
1
1
0
0
0
I:
E
E
I:
Flag Summary
Command
Type
Description
Bit
I
r" r. ~ Stepping Motor Rate
I
V
I
I
11&111
II
11&111
11&111
II
II
II
IV
h
T
a.
C
U
E
S
L
L
m
~
~
~
Head Load Flag
Track Update Flag
= Data Address Mark
~
~
~
~
~
Side Compare Flag
UpdateSSO
15 ms Delay
Side Compare Flag
~
~
h
h
~
T
T
~
~
~
~
0, No verify
1, Verify on destination track
0, Unload head at beginning
1, Load head at beginning
0, No update
1, Update track register
0, FB(DAM)
1, F8 (deleted DAM)
a.
a.
~
C
C
~
U
U
= 1, Update SSO to 1
~
0, Disable side compare
1, Enable side compare
~0.
E
E
~
S
S
~
~
~
~
UpdateSSOt00
0, No 15 msdelay
1, 15 ms delay (30 ms for 1 MHz clock)
0, Compare for side 0
1, Compare for side 1
Sector Length Flag
Multiple Record Flag
1:
11 ~ 1:
12~ 1:
13~ 1:
13-10 ~0:
334
V
V
= 1 (implicit) for SAB 2791A193A
Ix~
10~
see page 13 for details
Track Number Verify Flag
LSB's Sector Length in 10 Field
00
01
10
11
L
~0
256
512
1024
128
L
~
1
128
256
512
1024
m
m
~
~
0, Single record
1, Multiple records
Interrupt Condition Flags
Interrupt on Not Ready to Ready Transition
Interrupt on Ready to Not ReadyTransition
Interrupt on next Index Pulse
Immediate Interrupt, requires a Reset'
Terminate with no interrupt (lNTRQ)
• See Type IV command description for further information.
SAB 279XA
Status Register Summary
Bit AllTypel
Commands
Read
Address
Read
Sector
Read
Track
Write
Sector
Write
Track
S7 NOT READY
S6 WRITE
PROTECT
S5 HEAD LOADED
S4 SEEK ERROR
S3 CRCERROR
S2 TRACK00
S1 INDEX
S0 BUSY
NOT READY
0
NOT READY
0
NOT READY
0
0
RNF
CRCERROR
LOST DATA
DRO
BUSY
RECORD TYPE
RNF
CRCERROR
LOST DATA
ORO
BUSY
0
0
0
LOST DATA
DRO
BUSY
NOT READY
WRITE
PROTECT
0
RNF
CRCERROR
LOST DATA
DRO
BUSY
NOT READY
WRITE
PROTECT
0
0
0
LOST DATA
ORO
BUSY
Status for Type I Commands
Meaning
Bit Name
S7
NOT READY
This bit, when set, indicates that the drive is not ready. When reset, it indicates thatthe
drive is ready. This bit is an inverted copy olthe Ready input and logically "ored" with MR.
S6 WRITE
PROTECT
When set, indicates that Write Protect is activated. This bit is an inverted copy ofWPRT
input.
S5 HEAD LOADED
When set, it indicates thatthe head is loaded and engaged. This bit is a logical "And" of
HLD and HL Tsignals.
S4 SEEK ERROR
When set, the desired track was not verified. This bit is reset to 0 when updated.
S3 CRCERROR
CRC encountered in ID field.
S2 TRACK 00
When set, indicates that ReadlWrite head is positioned to Track00. This bit is an inverted
copy of the TR00 input.
S1
INDEX
S0 BUSY
When set, indicates that index mark is detected from drive. This bit is an inverted copy
of the iP input.
When set, command is in progress. When reset, no command is in progress.
Status for Type II and III Commands
Bit Name
Meaning
S7 NOT READY
This bit, when set, indicates that the drive is not ready. When reset, it indicates thatthe
drive is ready. This bit is an inverted copy of the Ready input and "ored" with MR.
The Type II and III Commands will not execute unless the drive is ready.
S6 WRITE
PROTECT
For Read Record: not used. For Read Track: not used. On any Write: It indicates a
Write Protect. This bit is reset, when updated.
S5 RECORD TYPE
For Read Record: It indicates the record-type code from data field address mark.
1 ~ Deleted Data Mark. 0 ~ Data Mark. For any Write: forced to a zero.
S4 RECORD NOT
FOUND(RNF)
When set, it indicates that the desired track, sector, or side were not found. This bit is
reset when updated.
S3 CRCERROR
If S4 is set, an error is found in one or more ID fields; otherwise it indicates error in data
field. This bit is reset when updated.
S2 LOST DATA
When set, it indicates that the computer did not respond to DRO in one byte time. This
bit is reset to zero when updated.
S1
This bit is a copy of the ORO output. When set, it indicates that the DR isfull on a read
Operation orthe DR is empty on a write operation. This bit is resetto zero when
updated.
DATA
REOUEST
S0 BUSY
When set, command is under execution. When reset, no command is under execution.
335
SAB279XA
Summary of Adjustment Procedures
Write Precompensation
11
21
31
41
51
61
Set TEST (Pin 221 to a logic high.
Strobe MR (Pin 191.
Set TEST (Pin 221 to a logic low.
Observe pulse width on WD (Pin 311.
Adjust WPW (Pin 331 for desired pulse width (Precomp Valuel.
Set TEST (Pin 221 to a logic high.
Data Separator
11 Set TEST (Pin 221 to a logic high.
21 Strobe MR (Pin 191. Ensure that 5/B, and ODEN are set properly.
31 Set TEST (Pin 221 to a logic low.
41 Observe pulse width on TG43 (Pin 291.
51 Adjust RPW (Pin 1B) for l/B of the read clock (250ns for 8" DD, 500ns for 5' 1;' DD, etc.).
S} 8b;;c;,,·vc; f. t.yut:llt;y UII Dine iPin 16j.
7) Adjust variable capacitor on VCO pin for data rate (500 kHz for 8" DO, 250 kHz for 5 ' 1;' DD, etc.l.
8) Set TEST (pin 22) to a logic high.
NOTE: To maintain internal VCO operation, insure that TEST ~ 1 whenever a master reset pulse is applied.
Status Register
Upon receipt of any command, except the Force
Interrupt command, the Busy Status bit is set and
the regt of the status bits are updated or cleared for
the new command. If the Force Interrupt command
is received when there is a current command under
execution, the Busy status bit is reset, ~nd the rest of
the status bits are unchanged. If the Force Interrupt
command is received when there is not a current
command under execution, the Busy Status bit is
reset and the rest of the status bits are updated or
cleared as after a Type I command.
The user has the option of reading the Status Register
through progl am control or using the DRO line with
DMA or interrupt methods. When the Data Register
is read the DRO bit in the Status Register and the
DRQ line are automatically reset. A write to the
Data Register also causes both DRQs to reset.
The Busy bit in the status may be monitored with a
user program to determine when a command is
complete, in lieu of using the INTRQ line. When
using the INTRQ, a busy status check is not recommended !:lecause a read of the Status Register
to determine the condition of Busy will reset the
INTRQ line.
The format of the Status Register is shown below:
(BITS)
7
6
-~
S~S6
Status varies according to the type of command
executed as shown on page 11.
Because of internal sync cycles, certain time delays.
must be observed when operating under programmed 110. They are:
Operation
Next Operation
Delay Req:d.
FM
MFM
Writeto
Command Reg.
Read Busy Bit
(Status Bit 0)
12/Ls
6/Ls
Write to
Command Reg.
Read Status
Bits 1--7
28/Ls
14 fLS
Write to
Any Register
Read From Oiff.
Register
0
0
Times double when clock
336
~1
MHz
SAB279XA
Command Description
The SAB 279XA will accept eleven commands.
Command words should only be loaded in the
Command Register when the Busy status bit is off
(Status bit 0). The only exception is the Force Interrupt command. Whenever a command is being
executed, the Busv status bit is S6t. Wileen c
command is completed, an interrupt is genei'uted
alld the Busy status bit is reset. The Stat'J' Regist"r
indicates whether the complettd command P."countered an error or was fault-free. For ease of
discussion, commands are :iivldcd into f,jur t') ~es.
Commands and types are SUrl1r,'arrze,d Gil p~g', 10.
Type I Commands
The Type I commands include the Restore, Seek,
Step, Step-In, and Step-Out commands. Each of the
Type I commands contains a rate field (r o, rll which
determines the stepping motor rate.
A 2 f.1.s (MFM) or 4 f.1.S (FMI pulse is provided as an
output to the drive. For every step pulse issued, the
drive moves one track location in a direction
determined by the Direction output. The chip steps
the drive in the same direction it has been stepped
previously, unless the command changes the direction.
The Direction signal is active high when stepping in
and low when stepping out. The Direction signal is
valid 12 f.1.S before the first stepping pulse is
generated. The rates can be applied to a StepDirection motor through the device interface.
Stepping Rates
ClK
2MHz
1 MHz
rl
r0
TEST ~ 1
TEST - 1
0
0
1
1
0
1
0
1
3ms
6ms
10ms
15ms
6ms
12ms
20ms
30ms
After the last directional step, additional 15 milliseconds of head settling time are generated if the
Verify flag is set in Type I commands. Note that this
time doubles to 30 ms for a 1 MHz clock. There is also
a 15 ms head settling time if the E flag is set in any
Type II or III command.
When a Seek, Step or Restore command is executed
an optional verification of ReadlWrite head position
can be performed by setting bit 2 (V ~ 11 in the
command word to a logic 1. Th~ verification
operation begins at the cnd of the 15 mriiis,"cnncl
settling time after the head is loaded a93;1::-:.1 ths
media. The track number from the first encountered
ID field IS cClmpared against the contents of the
Track Register. If the track numbers com pal :, and
the ID field Cyclic Redundancy Check (CRCI is
correct, the verify operation is complete and an
INTRO is generated with no errors. If there IS a match
but not a valid CRC, the CRC Error status bit is set
(Status bit 3)' and the next encountered ID field is
read from the disk for the verification operation.
The SAB 279XA must find an ID field with correct track
number and correct CRC within 5 revoltuions of the
media; otherwise the Seek Error is set and an INTRO
is generated. If V ~ 0, no verification is performed.
The Head load (HlDI output controls the movement
of the Read/Write head against the media. HlD is
activated at the beginning of a Type I command if
the h flag is set (h ~ 1), at the end of the Type I
command if the Verify flag is set (V ~ 1), or upon
receipt of any Type liar III command. Once HlD is
active it remains active until either a Type I
command is received with h ~ 0 and V 0; or if the
SAB 279XA is in an idel state (non-busy) and 15 index
pulses have occured.
Head Load Timing (HLT) is an input to the SAB 279XA
which is used for the head engage time.
When HlT = 1, the SAB 279XA assumes the head
is completely engaged. The head engage
time is typically 30 to 100 ms depending on drive.
The low to high transition on HlD is typically
used to fire a single shot. The output of the single
shot is then used for HLT and supplied as an input
to the SAB 279XA.
00
337
I
SAB279XA
Head Load Timing
HLD
[ " to 100m<
JI--------
HLT from one - shot
When both HLD and HLT are true, the SAB 279XA will
men read trom or write to the media. The "And" of
HLD and HLT appears as status bit 5 in Type I status.
Summary of the Type I commands:
If h ~ 0 and V ~ 0, HLD is reset.
If h ~ 1 and V ~ 0, HLD is set at the beginning of the
command and HLT is not sampled nor is there an
internal 15 ms delay.
If h ~ 0 and V ~ 1, HLD is set near the end of the
command, an internal 15 ms occurs, and the
SAB 279X waits for HLT to be true.
Ifh ~ 1 and V~ 1, HLD is set atthe beginning of the
command.
Neilr the end of the command, after all the steps
have been issued, an internal 15 ms delay occurs
and the SAB 279X then waits for HLT to occur.
For Type II and III commands with E flag off, HLD is
made active and HLT is sampled until true. With E
flag on, HLD is made active, an internal 15 ms delay
occurs and then HLT is sampled u'ntil true.
Restore (Seek Track 8)
Upon receipt of this command the Track 00 (TR00)
input is sampled. If TR00 is active low indicating the
ReadIWrite head is positioned over track 0, the Track
Register is loaded with zeroes and an interrupt is
generated. If TROO is not active 10 t', stepping pulses
at a rate specified by the r, r, field are issued until
the TR00 input is activated. At this time the Track
Register is loaded with zeroes and an interrupt is
generated. If the TR00 input does not go active low
after 255 stepping pulses, the SAB 279XA terminates
operation, interrupts, and sets the Seek error status
bit. Averification operation takes place ifthe Vflag is
set. The h bit allows the head to be loaded at the start
of command. Note that the Restore command is
always executed when MR goes from an active to
an inactive state.
338
Seek
This command assumes that the Track Register
contains the track number of the current position of
the ReadIWrite head and the Data Register contains
the desired track number. The SAB 279XA will update
the Track Register and issue stepping pulses in the
appropriate direction until the contents of the Track
Register are equal to the contents of the Data
Register (the desired track location). A verification
operation takes place if the V flag is on. The h bit
allows the head to be loaded at the start of the
command. An interrupt is generated at the termination ofthe command. Note: When using multiple
drives, the Track Register must be updated for the
drive selected before seek commands are issued.
Step
Upon receipt of this command, the SAB 279XA issues
one stepping pulse to the disk drive. The stepping
motor direction is the same as in the previous Step
command. After a delay determined by the r, r, field,
a verification takes place if the V flag is on. If the
T flag is on, the Track Register is updated. The h bit
allows the head to be loaded at the start of the
command. An interrupt is generated at the termination of the command.
Step-In
Upon receipt of this command,t he SAB 279XA issues
one stepping pulse in the direction towards track 76.
If the T flag is on, the Track Register is incremented
by one. After a delay determined by the r, ro field, a
verification takes place if the V flag is on. The h bit
allows the head to be loaded at the start of the
command. An interrupt is generated at the termination of the command.
SAB 279XA
Step-Out
Exceptions
Upon receipt of this command, the SAB 279XA issues
one stepping pulse in the direction twoards track O. If
the T flag is on, the Track Register is decremented by
one. After a delay determined by the r, ro field, a verification takes place if the V flag is on. The h bit allows the
head'to be loaded at the start of the command. An interrupt is generated at the termination of the command.
On the SAB 2795A/97A devices, the ssa output is not
affected during Type I commands, and an internal
side compare does not take place when the (V)
Verify flag V is on.
Type II Commands
The Type II Commands are the Read Sector and
Write Sector commands. Prior to loading a Type II
command into the Command Register the Gomputer must load the Sector Register with the desired
sector number. Upon receipt of the Type II command, the Busy status bit is set. If the E flag is 1 (this
is the normal case) HLO is made active and HLT is
sampled after a 15 ms delay. If the E flag is 0, the
head is loaded and HLT is sampled without a
15 ms delay.
When an 10 field is located on the disk, the
SAB 279XA compares the track number on the 10
field with the Track Register. If they do not match,
the next encountered 10 field is read and a comparison is again made.lfthere has been a match, the
Sector Number of the 10 field is compared with the
Sector Register. If there is no sector match, the
next encountered 10 field is read off the disk and
again compared. If the 10 field CRC is correct,
the data field is then located and will be either
written into, or read from depending upon the
command. The SAB 279XA must find an 10 field with
a track number, sector number, side number, and
CRC within 5 revolutions of the disk; otherwise, the
Record-Not-Found status bit is set (Status bit4) and
the command is terminated with an interrupt.
Each of the Type II commands contains an m flag
which determines if multiple records Isectors) are to
be read or written, depending upon the command.
If m ~ 0, a single sector is read or written and an
interrupt is generated at the termination of the
command. If m ~ 1, multiple records are read or
written with the Sector Register internally updated
so that an address verification can occur on the next
record. The SAB 279XA will continue to read or write
multiple records and update the Sector Register in
numerical ascending sequence until the Sector
register exceeds the number of sectors on the track
or until the Force Interrupt command is loaded into
the Command Register, which terminates the
command and generates an interrupt.
For example: If the SAB 279XA is instructed to read
sector 27 and there are only 26 on the track, the
Sector Register exceeds the number available. The
SAB 279XA will search for 5 disk revolutions, interrupt
out, reset Busy, and set the Reco rd-N ot-Found status bit.
The Type II commands for SAB 2795A197A also contain
Side Select Compare flags. When C ~ 0 (bit 1) no side
comparison is made. Whtm C ~ 1, the LSB of the
side number is read off the 10 field of the disk and
compared with the contents of the (S) flag (bit 3).lf
the S flag corresponds to the side number recorded
in the 10 field, the SAB 279XA continues with the 10
search. If a comparison is not made within 5 index
puises, the interrupt line is made active and the
Record-Not-Found st~tus bit is set.
The Type II and III commands for the SAB 2795A/97A
contain a Side Select flag (bit 1). When U = ~, SSO is
updated to 0. Similarly, U ~ 1 updates ssa to 1.
The chip compares the ssa tothe 10 field. If they do
not correspond within 5 revolutions the interrupt
line is made active and the RNF status bit is set.
The SAB 2795A/97 A Read Sector and Write Sector commands include an L flag. The L flag, in conjunction with
the sector length byte of the 10 Field, allows different
byte lenghts to be implemented in each sector. For
IBM compatibility, the L flag should be set to a one.
Read Sector
Upon receipt of the Read Sector command, the head
is loaded, the Busy status bit set, and when an 10
field is encountered that has the correct track
number, correct sector number, correct side number, and correct CRC, the data field is presented to
the computer. The Data Address Mark of the data
fi·eld must be found within 30 bytes in single density
and 43 bytes in double density of the last 10 field
CRC byte; if not, the 10 field search is repeated.
When the first character or byte of the data field has
been shifted through the OSR, it is transferred to the
DR, and DRO is generated. When the next byte is
accumulated in the OSR, it is transferred to the DR
and another ORO is generated. If the computer has
not read the previous contents of the DR before a
new character is transferred that character is lost
and the Lost Data status bit is set. This sequence
continues until the complete data field has been
input to the computer. If there is a CRC error at the
end of the data field, the CRC Error status bit is
set and the command is terminated (even if it is a
multiple sector commandl.
339
SAB 279XA
At the end of the read operation, the type of Data
Address Mark encountered in the data field is recorded in the Status Register (bit 5) as shown:
disk. At this time the Data Address Mark is written
on the disk as determined by the a. field of the
command as shown below:
Status Bit 5
a,
Data Address Mark (Bit 0)
1
Deleted Data Mark
Data Mark
Deleted Data Mark
Data Mark
o
o
Write Sector
Upon receipt of the Write Sector command, the
head is loaded (HLD active) and the Busy status bit
is set. When an ID field is encountered that has the
correct track number, correct sector number, correct
side number, and correct CRC, a DRQ is generated.
The SAB 279XA counts off 11 bytes in single density
~i,d 22 ::'y"lO~ ill uuuuit::: Lier1:::iilY from me C;HL fJeld,
and the Write Gate (WG) output is made active if the
DRQ is serviced (i.e., the DR has been loaded by the
computer). If DRQ has not been serviced, the
command is terminated and the Lost Data status bit
is set. If the DRQ has been serviced, the WG is made
active and six bytes of zeroes in single density and
12 bytes in double density are then written on the
The SAB 279XA then writes the data field and gener·
ates DRQs to the computer. If the DRQ is not
serviced in time for continous writing, the Lost Data
status bit is set and a byte of zeroes is written on the
disk. The command is not terminated. After the
last data byte Mas been written on the disk, the twobyte CRC is computed internally and written on
the disk followed by one byte of hex FE in FM or in
MFM. The WG output is then deactivated. For a
2 MHz clock the INTRQ is set between 8 and 12 /Lsec
after the last CRC byte has been written. For partial
sector writing, the proper method is to write the data
and fill the balance with zeroes. By letting the chip fill
the zeroes, errors may be masked by the Lost Data
status and improper CRC bytes.
Types III Commands
Read Address
Upon receipt ofthe Read Address command, the
head is loaded and the Busy status bit is set. The
next encountered ID field is then read from the
disk, and the six data bytes of the ID field are
assembled and transferred to the DR. And DRQ is
generated for each byte. The six bytes ofthe ID field
are shown below:
TRACK
SIDE
SECTOR SECTOR CRC CRC
AD DR NUMBER ADDRESS LENGTH
1
2
1
2
3
4
5
6
Although the GRG characters are transferred to the
computer, the SAB 279XA checks for validity and the
CRC Error status bit is set if there is a CRC error. The
track address of the ID field is written into the
Sector Register so that a comparison can be made
by the host. At the end of the operation an interrupt
is generated and the Busy status.blt is reset.
All gap, header, and data bytes are assembled and
transferred to the Data Register. DRQs are
generated for each byte. The accumulation of bytes
is synchronized to each address mark encountered.
An interrupt is generated at the termination of the
command.
This command has several characteristics which
make it suitable for diagnostic purposes. They are:
no CRC checking is performed; gap information is
included in the data stream; the internal side compare is not performed; and the address mark
detector is on for the duration of the command.
Because the A.M. detector is always on, write
splices or noise may cause the chip to look for an
A.M. If an address mark does not appear on schedule with the Lost Data status flag being set.
The ID A.M., ID field, ID CRC bytes, DAM, data and
data CRC bytes for each sector will be correct. The
gap bytes may be read incorrectly during writesplice time because of synchronization.
Write Track Formatting the Disk
Read Track
Upon receipt of the Read TI ack command, the head
is loaded, and the Busy status bit is set. Reading
starts with the leading edge of the first encountered
index pulse and continues until the next index pulse.
340
Formatting the disk is a relatively simple task when
operating programmed I/O or when operating
under DMAwith a large amount of memory. Data
and gap information must be provided at the computer interface. Formatting the disk is accomplished
SAB279XA
by positioning the R/W head over the desired track
number and issuing the Write Track command.
Upon receipt of the Write Track command, the head
;s loaded and the Busy status bit is set. Writing starts
with the leading edge of thefirst encountered index
pulse and continues until the next index pulse, at
which time the interrupt is activated. The data
request is activated immediately upon receiving the
command, but writing will not start before the
first byte is loaded into th~ Data Register If the
DR has not been loaded by the time the index pulse
is encountered the operation is terminated by
making the device not busy. The lost Data status bit
is set, and the interrupt is activated. If a byte is not
present in the DR when needed, a byte of zeroes is
substituted.
This sequence continues from one index markto the
next index mark. Normally, whatever data pattern
appears in the Data Register, it is written on the disk
with a normal clock pattern, However, If the SAB 279XA
detects a data pattern of F5 thru FE In the Data Register,
This is interpreted as Data Address Marks with
missing clocks or CRC generation, The CRC generator
is initialized when any data byte from FB to FE IS about
to be transferred from the DR to the DSR at by receipt
of F5 In MFM, An F7 pattern will generate two CRC
characters in FM or MFM As a consequence, the
patterns F5 thru FE must not appear in the gilpS,
data fields, or ID fieids. Also, CRCs must be generated
by an F7 pattern, Disks may be formatted in IBM 3740
or System 34 formats with sector lengths at 128,256,
512, or 1024 bytes.
Control Bytes for Initialization
Data Pattern
in DR (HEX)
SAB 279XA Interpretation
in FM (iSDEN ~ 1)
SAB 279XA Interpretation
It) MFM (DDEN - 0)
Write 00 thru F4 with ClK ~ FF
NotAllowed
Not Allowed
Generate 2 CRC Bytes
Write F8 thru FB, ClK ~ Cl, Preset CRC
Write FC with ClK ~ D7
FD
Write FD with ClK ~ FF
FE
Write FE, Clk ~ C7, Preset CRC
FF _ _ _ _..1..Write FF with ClK ~ FF
_
00thru F4
F5
F6
F7
FB thru FB
FC
Write 00thru F4, in MFM
Write A 1'1 in MFM, Preset CRC
Write C2 21 in MFM
Generate 2 CRC Bytes
Write FBthru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM
I
11 Missing clock transition between bits 4 and 5
Missing clock transition between bits 3 and 4
21
Type IV Commands
The Force Interrupt command is generally used to
terminate a mUltiple sector Read or Write command
orto ensure Type I status in the Status Register. This
command can be loaded into the Command
Register at any time. If there is a current command
under execution (Busy status bit set) the command
will be termi nated and the Busy status bit reset.
The lower four bits of the command determine the
conditional interrupt as follows:
10: Not-Ready to Ready Transition
11: Ready to Not-Ready Transition
12: Every Index Pulse
13: Immediate Interrupt
The conditional interrupt is enabled when the
corresponding bit positions of the command
(13-10) are set to a1. Then, when the condition for
interrupt is met, the INTRO line will go high signifying that the condition specified has occurred.
If 13-10 are all set to zero (hex D0), no interrupt will
occur but any command presently under execution
will be immediately terminated. When using the
immediate interrupt condition (13·~ 1), an interrupt
will be immediately generaied and the current
command terminated. Reading the status or Writing
to the Command Register will not automatically
clear the interrupt. The hex DO is the only command
that will enable the immediate interrupt (hex DB)
to clear on a subsequent load Command Register or
read Status Register operation. Follow a hex DB
with DO command. Wait 8}J.s (double density)
or 16}J.s (single density) before issuing a new command after issuing a Force Interrupt command (times
double when clock = 1 MHz). loading a new command sooner than this will nullify the forced interrupt.
Forced interrupt stops any command ilt the end of
an internal micro-instruction and generates INTRO
when the specified condition is met. Forced interrupt will wait until AlU operations in progress are
completed (CRC calculations, comparisons, etc.).
MO're than one condition may be set at a time. If for
example, the Ready to Not-Ready condition (11 = 1)
and the Every Index Pulse (12 = 1) are both set, the
resultant command would be hex DA. The OR
function is performed so that either a Ready to NotReady or the next Index Pulse will cause an interrupt
condition.
341
SAB 279XA
Formats
IBM 3740 Format - 128 Bytes/Sector (8")
IBM System 34 Format - 256 Bytes/Sector (8")
Shown below is the IBM single-density format with
128 bytes/sector. In order to format a diskette, the
user must issue the Write Track command, and load
the Data Register with the following values. For
every byte to be written, there is one data request.
Shown in the following table is the IBM doubledensity format with 256 bytes/sector. In order to
format a diskette the user must issue the Write Track
command and load the Data Register with the
following values. For every byte to be written, there
is one data request.
Number
of Bytes
40
6
1
26
r-T
11
6
1
128
1
27
24721
Hex Value of
Byte Written
FF (or 001 31
00
FG (Index Markl
FF (or001
00
80
12
3
1
~!:: ~!!:,/\~d:-~~:: ~.~:i~~
Track Number
Side Number (00 or 011
SectorNumber(1 thru 1AI
00
F7 (2 GRGs written I
FF (or 001
00
FB (Data Address Markl
Data (E51
F7 (2 GRGs written)
FF lor 001
FF (or 001
') Write bracketed field 26 times.
') Continue writing until SAB 279XA interrupts out.
Approx. 247 (598) bytes.
3) Optional '00' on SAB 2795A/97 A on Iy is allowed.
342
Number
of Bytes
O~
wv
11
12
3
1
1
1
1
1
1
22
12
3
1
256
1
54
598 21
Hex Value of
Byte Written
4E
00
F6 (writes G21
FG (Index Markl
.r
00
F5 (writes A 11
FE (lD Address Markl
Track Number (0 through 4GI
Side Number (0 or 11
Sector Number (1 through 1AI
01 (Sector lengthl
F7 (2 GRGs written I
4E
00
F5 (writes A 11
FB (Data Address Markl
Data IE 51
F7 (2 GRGs written I
4E
4E
SAB 279XA
Recommended - 128 Bytes/Sector (Mini-Diskette)
Recommended - 256 Bytes/Sector (Mini-Diskette)
Shown below is the recommended single-density
format with 128 bytes/sector. In order to format a
diskette, the user must issue the Write Track
command, and load the Data Register with the
following values. For every byte to be written, there
is one data request.
Shown below is the recommended double-density
format with 256 bytes/sector. In order to format a
diskette the user must issue the Write Track
command and load the Data Register with the
following values. For every byte to be written, there
is one data request.
Number
of Bytes
Number
of Bytes
11
40
6
11
6
128
10
HexValue of
Byte Written
FF (or (0)
11
00
FE (lDAddress Mark)
Track Number
Side Number (00 or(1)
Sector Number (1 through 10)
00 (Sector length)
F7 (2 CRCs written)
FF (or00)
00
FB (Data Address Mark)
Data (E5)
F7 (2 CRCs written)
FF (or (0)
FF (or (0)
60
12
3
1
1
22
12
3
256
24
718 21
HexValue of
Byte Written
4E
00
F5 (Writes A 1)
FE (10 Address Mark)
Track Number (0 through 4C)
Side Number (0 or 1)
Sector Number (1 through 10)
01 (Sector Length)
F7 (2 CRCs written)
4E
00
F5 (Write A 1)
FB (Data Address Mark)
Data (E5)
F7 (2 CRCs written)
4E
4E
Non-Standard Formats
Variations in the IBM formats are possible to a
limited extent if the following requirements are met:
1. Sector size must be 128, 256, 512 or 1024 bytes.
2. Gap 2 cannot be varied from the recommended
format.
3.3 bytes of Al must be used in MFM.
In addition, the Index Address Mark is not required
for operation by the SAB 279XA. Gap 1, 3, and 4
lengths can be as short as 2 bytes for SAB 279XA
operation, however, PLL lock up time, motor speed
variation, write-splice area, etc., will add more bytes
to each gap to achieve proper operation. It is
recommended that the IBM format should be used
for highest system reliability.
FM
MFM
16 bytes FF
11 bytes FF
6 bytes 00
32 bytes4E
22 bytes4E
12 bytes 00
41
10 bytes FF
4 bytes 00
GaplV
16 bytes FF
24 bytes4E
8 bytes 00
3 bytes A 1
16 bytes4E
Gapl
Gapll
31
Al
Gaplll
11
21
31
41
Write bracketed field 16 times.
Continue writing until SAB 279XA interrupts oul.
Approx. 349 (718) bytes.
Byte counts must be exact.
Byte counts are minimum, except exactly 3 bytes
of A 1 must be written in MFM.
343
en
......
Co>
iii
3:
.,..
Physlc,l Indo
~
n
,.68yft's fH
92 By!.. HFH
...
0
...3
~
Gap 4
3~e8~~:~xFH
'44 Bytes HfM
Nommal
Index Address Hark
I
(221
.3 Bytes
~:t
Y
Gap'
Post
Indo
.3 A,II
Bytes
32 Bytes FH
MFM
62 Bytes MfH only
110
R ret
~~o 1
I
I ~'a I
GapGap
2
10
17 Bytes FH
34 Bytes HFH
Field
Record
No 1
Gap3
Data
Gap
33 Bytu FH
I
10
R~:O~
Oata
Gap2
66 Bytes HFH
'--
Record
No 1
16ap3
10
Rtco"'d
~
Gap 2
No I
..
Data
field
Record
No.26
fIeld
Record
No.3
~
~
Dab or
10
Address
Mark
Track
Number
Side
Number
Sector
Sector
Number
Length
eRe
eRe
Byte'
Byte 2
Oeleted
Data
User Dahl
Address
Mark
eRe
eRe
Byte I
8y1e2
---------1) Hissmg clock transition
bl!t~n bits 4 and 5
2) Hissing dock tranSition
AI 1J
Gap2
All)
Gap 3
between bits .3 and 4
FH
HFH
f------
, Byte
11 Byte.
22 By...
/
Write gat!' turn on for uPdate---"-/
of nut data field
1 Byte
31 By'"
---I :
~w
te turn off for updatr
• us data field
ofr1 Ir1!VIO
Gap2
10
Record
No. 26
Gap"
l>
I:D
I\)
......
CD
X
l>
:t1
PhY""~
"'o"
3
3
'c.."
:::l
'c.."
~
-
46 Bytes
:::l
I--
'"iD
c
Gap 4
Gap 1
Pre-Index
349 Bytes
Post-lnrll"X RII":(orrl
46 Bytes
~;
I
10
Address
Hark
10
r,,,,
N b
um er
Nol
Gap 2 Data Field
10 Gap
Record
17 Bytes
No 1
Gap 3
10
Data Gap Record
158yte'S
No 2
Data Field
Record
Gap 2
No 2
Gap 2
Dabfll':ld
10
Record
No 3
Record
Gap 2
'"
:::l
Data Field
Record
'"
~
No 16
No 16
"T1
o
3
!!l.
~
10 Record Bytes
3
4
7
1
eRe
eRe
Oell"ted
Byte 1
Byte 2
Data
S,de
Sector
Number
Number
2:
Data Field Bytes
6
5
Sector
length
I
L~~
pI
Gap 3
10
Recon!
No 3
2-129
Gap 2
131
eRe
(Re
at
6iii'
,..
,
128 Bytes
of User Data
Data
Address
Hark
------;
----
130
---
Byte 1
By,," 2
!
I
~
~
-
Gap 3
:
(HEX FF
(HE> FF)
(HEX ftt)
I
(HEX 01ll
(HEX Ff)
fHEX eel
:
40 Byte,,>
~ 68ytes I-------
t-----------" Bytes
wntegatel
of
next date> ufrn-on for update
.. Itld
I
~
I
6 Bytes--1
f-----l0 Bytes
6B",,---1
~
OJ
I\)
.......
CO
~
en
><
l>
'"~
en
:%I
.~ ~
~
-=-
CD
~
"30
Ph",,~----lL_______________________
~
~ ~
3
~"
CD
~~
~
=
3
CCD
C-
~~
o
~3:
<
0
=..
-
3
~
~
72
0::
r--
Byt~s
CT
CD
0
CD
?
Gap 4
Gap 1
718 Bytes
72 Bytes
10
Al')
P"-Iod,,, r"I-IOd"
3 Bytes
~
Dato
Gap2
Rtcord ID Gap
No 1 34Byh!s
Gop]
Field
10
DatnGap Record
Record
No 2
39 Bytes
No.1
Gap2
Data
field
Record
No 1
Trilck
Mark
Humber
Record
Gap2
No 3
Data
Field
10
Record
Re:ord
GapZ
Record
Ho.16
No_16
N>l
=
"
0
.3...
:1.
J
4
5
6
7
Side
Number
Sedor
Humber
Sector
eRe
eRe
length
Byte 1
Bytl2
: -251
1
Data or
Delded
Data
Address
C
258
259
...iii'
~
2';6 Bytes
eRe
eRe
of Jser Data
Byte 1
6yte 2
Gap3
Gap2
Gap'
:
I
I
IHEX 4EI
IHEX 81
IHEX
eel
A111
(HEX 4EI
(HEX ' "
.,11
I
- 6 0 B , t , , - 12 Bytes
~
~
Mark
!HEX I.E)
G.p,
Do u Field Bytes
ID Record Bytes
10
Address
10
Gap3
D;ta
FI!ld
I-----
12 Bytes~ f----------14 B'''s----~12 Bytes3 Bytes
- - 2 2 Bytes
~~~~
"W'got,tur
of o,d doto
~
/
for updat'
~
!
»
to
I\)
.....
CD
><
»
SAB279XA
Absolut Maximum Ratings 1)
oto + 70°C
-65 to + 150 DC
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Pin with
Respect to Ground (VSS)
Power Dissipation
D.C. Characteristics
TA ~ 0 to 70 DC; VCC'~ +5V ±5%. VSS -~
Symbol
-0.5to
+7V
2W
ov
Parameter
limit Values
Min.
ilL 1
Input Leakage Current'l
-
ilL 2
Internal Leakage Current'l
100
IOL
Output Leakage Current
-
VIH
Input High Voltage
2.0
VIL
Input LowVoltage
-
VOH
Output High Voltage
2.4
Typ.
Output Low Voltage
-
VOHP
Output High PUMP
2.2
VOLP
Output Low PUMP
-
ICC
Supply Current
-
----
Capacitance 3 )
---Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
~lA
-
-
-
0.8
0.45
--
IOH = -100 [,A
V
150
Limit Value
(max.)
IOL = 1.6 mA
IOHP = -1.0 mA
0.2
15
VIN = OV
VOUT= VCC
10
70
Test Conditions
VIN = VCC
10
1700
-
-
VOL
Unit
Max.
IOLP = +1.0 mA
mA
All outputs open
Unit
Test Condition
pF
Unmeasured pins
returned to GND
11
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
'I
ILL 1 applies to normal inputs. ilL 2 to inputs with internal pull-up resistors on pins 1. 17. 19. 22. 36. 37. and 40.
Also pin 25 on SAB 2791A193A.
31
This parameter is periodically sampled and not 100% tested.
347
SAB279XA
A.C. Characteristics
TA = 0 to 70°C; VCC = +5V ± 5%; VSS = OV.
All timing readings at VOL = 0.8 V and VOH = 2.0 V.
Read Enable Timing
Symbol
Limit Values
Parameter
Min.
TSET
Setup AOOR & CS to RE
50
THlO
Hold AOOR & CS from RE
10
200
TRE
RE Pulse Width
TORR
ORO Reset from RE
TIRR
INTRO Reset from RE
TnArr
f}~t::l
\h;diM frnrn QC
1 - - - - - - - - " ' 1 6 or
Max.
-
-
100
200
500
3000
"",
~nn
Units
Test Conditions
-
Cl
-
Read Enable Timing
Typ.
32~s
ns
= 50 pF
-
I Cl = 50 pF
--------,.,-1
VOH
ORO
I
I
"I
i
INTRQ.'r_-J+I---+-----------ILI________ VOL
' - - - - - - - - - - - VIL
f - - - - - - - - - - - - VIH
lit - - - t - - - \
Data are
vabd
T DACe
ORO rising edge:
ORO falling edge:
INTRa rising edge:
INTRa falling edge:
Indicates that the data register has assembled data.
Indicates that the data register was read.
Occurs at end of command.
Indicates that the status register was read.
'1
CS may be permanently tied
31
Time doubles when ClK
348
'0
lOW if desired.
1 MHz.
2)
T Service (worst case)
- FM = 27.5 ~(s
- MFM = 13.5 ~(s
SAB279XA
Write Enable Timing
Symbol
Parameter
Limit Values
Typ.
Min.
TSET
Setup ADDR & CS to WE
THlD
Hold ADDR & CS from WE
TWE
WE Pulse Width
TDRR
ORO Reset from WE
TIRR
INTRO Reset from WE
TDS
Data Setup to WE
TDH
Data Hold from WE
Write Enable Timing
Units
Test Conditions
Max.
50
-
10
-------
-
200
-
100
200
500
3000
150
ns
-
50
1 - - - - - - - - ' » 16 or
32~s
VOL
ORQ
I
i
-T IRR ll
---1
INTRa'r----J--+I-----+---------i
' - - - - - - - - - - VOL
' - - - - - - - - - - - - VIL
A0.A1.rr"
1------------ VIH
WE---+--j
T SET
I--
---------11.
Data must
----1 T±S
T
OH
ORO rising edge:
ORO falling edge:
INTRO rising edge:
INTRO falling edge:
~-----------
be . . alid .
L
Indicates that the data register is empty.
Indicates that the data register is loaded.
Indicate the end of a command.
Indicates that the command register is written to.
11
CS may permanently tied lOW if desired. When writing Data into Sector, Track or Data Register, the User
cannot read this register until at least 4fls in MFM after the rising edge of WE. When writing into the
Command Register status is not valid until some 28",s in FM/141ls in MFM later. These times double when
ClK = 1 MHz.
21
T Service (worst case); FM
= 23.5~IS;
31
Time doubles when elK
1 MHz.
=
MFM
= 11.5",s.
349
SAB279XA
Miscellaneous Timing
Symbol
Limit Values
Parameter
Typ.
Max.
230
250
20000
ns
--
Ils
TCD 1
Clock Duty (low)
TCD2
Clock Duty (high)
TSTP'
Step Pulse Output
2 or 4
-
TDIR
DIRC Setup to Step
-
12
TMR
Master Reset Pulse Width
50
TIP
Index Pulse Width
10
RPW
Read Window Pulse Width
120
240
r;:;comp Adjust
WPW
Unit
Min.
100
200
Write Data Pulse Width
± ClK Error
-
Test Conditions
700
1400
MFM
FM±15%
I---
300
400
~oo
ns
Input 0-5V
MFM
Pn:=!r.()m!",
=
1nnnc:.
MFM
600
VCO
Free Run Voltage Controlled Oscillator, 6.0
Adjustable by Ext. Capacitor on Pin 26 Oscillator, Adjustable
Pump Up +25%
5.0
Pump Down -25%
-
5% Change VCC
3.8
Adjustable External Capacitor
RClK
-
900
1200
Precomp = 300ns
MFM
4.0
-
Cext = 0
-
3.0
-
Cext = 35pF
PU = 2.2V, Cext = 35pF
MHz
4.2
--
3.5
20
35
Derived Read Clock = VCO: 8, 16,32
100
TA = 75°C, Cext = 35pF
pF
500
-
-
250
kHz
125
PUI
DON
11
PUIPD Time On (Pulse Width)
See stepping rates on page 13
350
-
VCO = 4.0 MHz nom.
DDEN = 0
5/8
= 1
t--250
-
PD = 0.2V, Cext = 35pF
Cext = 35pF
DDEN = 0
5/8
=0
DDEN = 1
5/8
= 1
DDEN = 1
5/8
=0
250
I - - - ns
500
MFM
FM
VCO = 4.0
MHz
SAB 279XA
Miscellaneous Timing
jj5
-----,1
'r-',
- - - - - I I VIH
"'-1
~TIP~
W1' \S-----,I
-----\1 VIH
"'-1
~TWF--l
MR
----.1
1-\
-----II
'--1
VIH
~T MR------1
351
SAB279XA
Read Data Timing
Symbol
Parameter
Limit Values
TPW
RAW READ Pulse Width
TBC
RAW READ Cycle Time
Min.
Typ.
100
1500
200
Units
Test Conditions
ns
-
Max.
-
2000
Read Data Timing
_~f-!;-pW-I-I-;_-_-_-_-_-_T_BC_-_-_ _~~_I-11
----1
I
I
LJ
I
LJ
Write Data Timing
Symbol
TWP
TWG
TWF
Parameter
Limit Values
Write Data Pulse Width
Write Gate to Write Data
Write Gate off from WD
All Times double when ClK
=
Min.
Typ.
Max.
400
500
250
600
200
-
-
300
Units
FM
ns
2
1
MFM
FM
1
2
Test Conditions
MFM
flS
FM
MFM
1 MHz; no Write precompensation.
Write Data Timing
WD
WG
352
-H~ _____ ~
~JTWG L ---IT WF!--.
----
L
SAB 8237A, SAB 8237A-5
High Performance
Programmable DMA Controller
• Four Independent DMA Channels
• Enable/Disable Control of Individual
DMA Requests
• Directly Expandable to any Number of Channels
• End of Process Input for Terminating Transfers
• Softwa re DMA Requests
• Independent Polarity Control for DREG
and DACK Signals
• Memory-to-Memory Transfers
• Memory Block Initialization
• Address Increment or Decrement
• Independent Autoinitialization of all Channels
• Single + 5 V Power Supply
• 40 Pin Dual-In-Line Package
• Fully compatible with the Industry Standard
9517 A/8237 A
• High performance: Transfers up to 1.6
MBytes/Second with 5 MHz SAB 8237A-5
Pin Configuration
Pin Names
Iml
A6
HEHR
AS
DB7-DB0
Data Bus (bidirectional)
10R,IOW
I/O Read and Write Input/Output
MEMR, MEMW
Memory Read and Write Output
*)
fOP
A0-A3
Address Input/Output
"Al
A4-A7
Adress Output
HLOA
ADSTB
AI
CS
Chip Select Input
CLK
Clock Input
HEMW
A4
AEN
AO
HRO
V((
i3
READY
Ready Input
ClK
DB1
HRG
Hold Request Output
RESET
DBl
HLDA
Hold Acknowledge Input
DA(K2
DB3
RESET
Reset Input
DREQ0-DRE03
DMA Request Input
OA(K3
DB'
OR£03
DA[KO
DACK 1
DREQ,
*) Pin always tied high
DMA Acknowledge Output
AEN
Address Enable Output
ADSTB
Address Strobe Output
EOP
End of Process Input/Output
DB5
DB'
GND
DACK0-DACK3
DB7
The SAB 8237A Multimode Direct Memory Access
(DMA) Controller is designed to improve system
performance by allowing external devices to directly t, ansfer information to or from system memory.
Memory-to-memory transfer capability is also
provided.
The SAB 8237 A contains four independent channels,
each with a separate register set, and may be
expanded to any number of channels by cascading
additional controller chips. The three basic transfer modes allow programmability of the types of
DMA service by the user. Each channel can be
individually programmed to Autoinitialize to its
original state following an End of Process ([(!p).
Each channel has a fu II 64K address and word
count capability.
The SAB 8237A is fabricated in +5V advanced
N-channel, silicon gate Siemens MYMOS technology and packaged in a 40-pin DIP. The
SAB 8237 A-5 is the 5 MHz version of the standard
3 MHz SAB 8237 A respectively.
AG 9/84
353
SAB 8237A
Pin Definitions and Functions
Symbol
Number
Input (I)
Output (0)
lOR
1
I/O
I/O READ
I/O Read is a bidirectional active low three-state line. In the idle
cycle, it is an input control signal used by the CPU to read the
control registers. In the Active cycle, it is an output control
signal used by the SAB 8237A to access data from a peripheral
device during a DMA Write transfer.
lOW
2
I/O
I/O WRITE
I/O Write is a bidirectional active low three-state line. In the idle
cycle it is an input control signal used by the CPU to load
information into the SAB 8237 A. In the Active cycle it is an
output control signal used by the SAB 8237A to load data to a
peripheral device durino a DMA Read trAnsf"r.
Write operations by the CPU to the SAB 8237 A require a rising
lOW edge following each data byte transfer. It is not sufficient
to hold the lOW pin low and toggle CS.
MEMR
3
0
MEMORY READ
The Memory Read signal is an active low three-state output
used to access data from the selected memory location during
a memory-to-peripheral or a memory-to-memory transfer.
MEMW
4
0
MEMORY WRITE
The Memory Write signal is an active low three-state output
used to write data to the selected memory location during a
peripheral-to-memory or a memory-to-memory transfer.
-
5
I
Pin 5 must be tied high.
READY
6
I
READY
Ready is an input used to extend the memory read and write
pulses from the SAB 8237 A to accommodate slow memories
or I/O peripheral devices. Ready must not make transitions
during its specified setup/hold time.
HLDA
7
I
HOLD ACKNOWLEDGE
The active high Hold Acknowledge from the CPU indicates that
control of the system busses has been relinquished.
ADSTB
8
0
ADDRESS STROBE
The active high Address Strobe is used to strobe the upper
address byte from DB0-DB7 into an external latch.
AEN
9
0
ADDRESS ENABLE
Address Enable is an active high signal used to disable the
system bus during DMA cycles and to enable the output of the
external latch which holds the upper byte of the address. Note
that during DMA transfers HLDA and AEN should be used to
deselect ali other I/O peripherals which may erroneously be
accessed as programmed I/O during the DMA operation. The
SAB 8237A automatically deselects itself by disabling the CS
input during DMA transfers.
354
Function
SAB 8237A
Symbol
Number
Input (I)
Output (0)
HRQ
10
0
HOLD REQUEST
The Hold Request to the CPU is used by the DMA to request
control of the system bus. Software requests or unmasked
DREQs cause the SAB 8237A to issue HRQ.
CS
11
I
CHIP SELECT
Chip Select is an active low input used to select the SAB 8237 A
as an 1/0 device during an 1/0 Read or 1/0 Write by the host
CPU. This allows CPU communication on the data bus. During
multiple transfers to or from the SAB 8237A by the host CPU
CS may be held low providing lOR or lOW is toggled following
each transfer.
ClK
12
I
CLOCK
This input controls the internal operations of the SAB 8237A
and its rate of data transfers. The input may be driven at up to
3 MHZ for the standard SAB8237A and up to 5 MHz for the
SAB 8237 A-5.
RESET
13
I
RESET
Reset is an asynchronous active high input which clears the
Command, Status, Request and Temporary register. It also
clears the First/last FliplFlop and sets the Mask register.
Following a Reset the device is in the idle cycle.
DACKO
DACK1
DACK2
DACK3
25
24
14
15
0
0
0
0
DMA ACKNOWLEDGE
The DMA Acknowledge lines indicate that a channel is active.
In many systems they will be used to select a peripheral. Only
one DACK will be active at a time and none will be active unless
the DMA is in control of the bus. The polarity of these lines is
programmable. Reset initializes them to active-low.
DREQO
DREQl
DREQ2
DREQ3
19
18
17
16
I
I
I
I
DMA REQUEST
The DMA Request lines are individual asynchronous channel
request inputs used by peripheral circuits to obtain DMA
service in Fixed Priority, DREQ0 has the highest priority and
and DREQ3 has the lowest priority. A request is generated by
activating the DREQ line of a channel. DACK will acknowledge
the recognition of DREQ signal.
The Polarity of DREQ is programmable. Reset initializes these
lines to active high.
DBO-DB7
30-26,
23-21
1/0
DATA BUS
The Data Bus lines are bidirectional three-state signals
connected to the system data bus. The outputs are enabled
during the 1/0 Read by the host CPU, permitting the CPU to
examine the contents of an Address register, the Status
register, the Temporary register or a Word Count register.
The Data Bus is enabled to input data during a host CPU 1/0
write, allowing the CPU to program the SAB 8237A control
registers. During DMA cycles the most significant eight bits
of the address are output onto the data bus to be strobed into
an external latch by ADSTB. In memory-to-memory operations
data from the source memory location comes into the
SAB 8237A's Temporary register on the read-from-memory
half of the operation. On the write·to-memory half of the
operation, the data bus outputs the Temporary register data
into the destination memory location.
Function
355
I
SAB 8237A
Symbol
Number
Input (I)
Output (0)
A0-A3
32-35
1/0
ADDRESS 0-3
The four least significant address lines are bidirectional3-state
signals. During DMA idle cycles they. are inputs and allow the
host CPU to load or read control registers. When the DMA is
active. they are outputs and provide the lower 4-bits of the
output address.
A4--A7
37-40
0
ADDRESS 4-7
The four most significant address lines are three-state outputs
and provide four bits of address. These lines are enabled only
during DMA service.
J:OP
36
1/0
END OF PROCESS
J:OP is an active low bidirectional open-drain signal providing
information concerning the' completion of DMA service. When
CI dldllllti'::. 'v·v·ulLi LUUTH goe::i to zerO,lne SAI:j 'dLJ/A pulses
J:OP low to provide the peripheral with a completion signal.
J:OP may also be pulled low by the peripheral to cause
premature completion. The reception ofJ:OP, either internal or
external, causes the currently active channel to terminate the
service, to set its TC bit in the Status register and to reset its
request bit. If Autoinitialization is selected for the channel, the
current registers will be updated from the base registers.
Otherwise the channel's mask bit will be set and the register
contents will remain unaltered.
During memory-to-memory transfers, J:OP will be output
when the TC for channel 1 occurs. ruP always applies to the
channel with an active DACK; external ruPs are disregarded
when DACK0-DACK3 are all inactive if the DMA is in state SI.
Function
In situations where two or more SAB 8237A DMAs are
cascaded, the ruP pins should be logically OR'ed (not
wire-OR'ed).
Because ruP is an open-drain signal, an external pullup
resistor is required. Values of 3.3 kQ or 4.7 kQ are recommanded; the J:OP pin cannot sink the current passed by a
1 kQ pullup.
VCC
31
-
POWER SUPPLY (+5V)
GND
20
-
GROUND (OV)
356
SAB 8237A
Block Diagram
EOP -RESEi ---
csREADY
eLK
-~
AEN - - -
Timing
Control
AOSTB -
HEHRMEMW
iOR
iOW
DR[aO-DREQ3 _4
-
HLOA
HRQ OA(KO-OACK 3
4
Rotating
Priority
logic
357
SAB 8237A
Register Description
Current Address Register
Each channel has a 16-bit Current Address register.
This register holds the value of the address used
during DMA transfers. The address is automatically
incremented or decremented after each transfer
and the intermediate values of the address are
stored in the Current Address register during the
transfer.
Current Word Count Register
Each channel has a 16-bit Current Word Count
register. This register should be programmed
with, and will return on a CPU read, a value one less
than the number of words to be transferred.
The word count is decremented after each transfer.
The intermediate value of the word count is stored
ill lilt~ reyisLer during Tne uanSfer. VVhen the value
in the register goes to zero, a TC will be generated.
Base Address and Base Word Count Registers
Each channel has a pair of Base Address and Base
Word Count registers. These 16-bit registers store
the original values of their associated current
registers. During Autoinitialize these values are
used to restore the current registers to their original
values. The base registers are written simultaneously with their corresponding current register in
8-bit bytes during DMA programming by the
microprocessor.
Command Register
This 8-bit register controls the operation of the
SAB 8237 A. It is programmed by the microprocessor
in the Program Condition and is cleared by Reset.
Mode Registers
Each channel has a 6-bit Mode register associated
with it. When the register is being written to by the
microprocessor in the Program Condition, bits \)
and 1 determine which channel Mode register it to
be written.
Request Register
The SAB 8237 A can respond to requests for DMA
service which are initiated by software as well as by
a DREO. Each channel has a request bit associated
with it in the 4-bit Request register. These are
nonmaskable and subject to prioritization by the
Priority Encoder network. Each register bit is set
or reset separately under software control or is
cleared upon generation of a TC or external EOP.
The entire register is cleared by a Reset.
358
Mask Register
Each channel has associated with it a mask bit
which can be set to disable the incoming DREO.
Each mask bit is set when its associated channel
produces an EOP if the channel is not programmed
for Autoinitialize. Each bit of the 4-bit Mask register
may also be set or cleared separately under
software control. The entire register is also set by a
Reset.
Status Reg ister
The Status registers may be read out of the
SAB 8237A by the microprocessor. It indicates
which channels have reached a terminal count
and which channels have pending DMA requests.
..... _---_ .. __ .........
I ell' .... ul al
Y
.
JlC!j':>U:::::1
The Temporary.register is used to hold data during
memory-to-memory transfers. Following the
completion of the transfers, the last word moved
can be read by the microprocessor in the Program
Condition.
SAB 8237A
Functional Description
DMA Operation
The SAB 8237A is designed to operate in two
r.lajor cycles. These are called Idle and Activa
cycles. Each device cycle is made up of a number
of states. State I (SI)is the inactive state. It is entered
when the SAB 8237A has no valid DMA requests
pending. While in SI. the DMA controller is inactive
but may be in the Program Condition, being programmed by the processor. State 0 (S0) is the first
state of a DMA service. The SAB 8237A has
requested a hold but the processor has not yet
returned an acknowledge. An acknowledge from
the CPU will signal that transfers may begin. S1,
S2, S3 and S4 are the working states of the DMA
service. If more time is needed to complete a
transfer than is available with normal timing, wait
states (SW) can be inserted before S4 by the use of
the Ready line on the SAB 8237A.
Memory-to-memory transfers require a read-from
and a write-to-memory to complete each transfer.
The states, which resemble the normal working
states, use two digit numbers for identification.
Eight states are required for each complete transfer.
The first four states (S11, S12, S13, S14) are used
for the read-from-memory half and the last four
states (S21. S22, S23 and S24) for the write-tomemory half of the transfer.
Block Transfer Mode
In Block Transfer mode, the SAB 8237 A will continue
making transfers until a TC (caused by the word
count going to zero) or an external End of Process
(EOP) is encountered.
Demand Transfer Mode
In Demand Transfer mode the device will continue
making transfers until a TC or external EOP is
encountered or until DREQ goes inactive. Thus, the
device requesting service may discontinue transfers
by bringing DREQ inactive. Service may be resumed
by asserting an active DREQ once again.
Cascade Mode
This mode is used to cascade more than one
SAB 8237 A together for simple system expansion.
The HRQ and HLDA signals from the additional
SAB 8237A are connected to the DREQ and DACK
signals of a channel of the initial SAB 8237A.
I
Idle Cycle
When no channel is requesting service, the
SAB 8237 Awill enter the Idle cycle and perform "SI"
states. In this cycle the SAB 8237A will sample the
DREQ lines every clock cycle to determine if any
channel is requesting a DMA service. The device
will also sample CS, looking for an attempt by the
microprocessor to write or read the internal
registers of the SAB 8237A.
Active Cycle
When the SAB 8237A is in the Idle cycle and a
channel requests a DMA service, the device will
output a HRQ to the microprocessor and enter the
Active cycle. It is in this cycle that the DMA service
will take place, in one of four modes:
Single Transfer Mode
In Single Transfer mode, the SAB 8237A will make
a one-byte transfer during each HRQ/HLDA handshake. When DREQ goes active, HRQ will go active.
After the CPU responds by driving HRQ active,
a one-byte transfer will take place. Following the
transfer, HRQ will go inactive, the word count will be
decremented and the address will be either
incremented or decremented.
359
SAB 8237A
TRANSFER TYPES
Each of the three active transfer modes can perform
three different types of transfers. These are Read,
Write and Verify. Write transfers move data from an
I/O device to the memory by activating lOR and
MEMW. Read transfers move data from memory
to an I/O device by activating MEMR and lOW. Verify
transfers are pseudo transfers; the SAB8237 A
operates as in Read or Write transfers g~nerating
addresses, responding to EOP, etc., however, the
memory and I/O control lines remain inactive.
Memory-to-Memory
The SAB8237A includes a block move capability
that allows blocks of data to be moved from one
memory adress space to another. Channel 0 forms
the source address and channell forms the destination address. The channel 1 wort! r.nl tnt i~ 11~l=Irl l!:t.
memory-to-memory transfer is initiated by setting
a software DMA request for channel 0.
Autoinitialize
By programming a bit in the Mode register a channel
may be set up for an Autoinitialize operation. During
Autoinitialization, the original values of the Current
Address and Current Word Count registers are
automatically restored from the Base Address and
Base Word Count registers of that channel following
EOP.
Extended Write
For Flyby Transactions late write is normally used,
as this allows sufficient time for the lOR signal to get
data from the peripheral onto the bus before MEMW
is activated. In some systems, performance can be
improved by starting the write cycle earlier.
Address Generation
In orderto reduce pin count, the SAB 8237A
multiplexes the eight higher order address bits on
the data liries. State S 1 is used to output the higher
order address bits to an external latch from which
they may be placed on the address bus. The falling
edge of Address Strobe (ADSTBI is used to load
these bits from the data lines to the latch. Address
Enable IAENI is used to enable the bits onto the
address bus through a 3-state enable. The lower
order address bits are output by the SAB 8237 A
directly. To save time and speed transfers, the
SAB 8237 A executes S 1 states only when updating
of AS-A 15 in the latch is necessary.
360
Compressed Timing
In order to achieve even greater throughput where
system characteristics permit, the SAB 8237 A can
compress the transfer time to two clock cycles.
By removing state S3 the read pulse width is made
equal to the write pulse width and a transfer consists
only of state S2 to change the address and state S4
to perform the read/write.
Priority
The SAB 8237 A has two types of priority encoding
available as software selectable options. The first is
Fixed Priority which fixes the channels in priority
order based upon the descending value of their
number. The channel with the lowest priority is
3 followed by 2, 1 and the highest priority channel0.
The second schema is Rotating Priority. The last
channel to qet service becomes the InwP"t nri()rit\l
channel with the others rotating accordingly.
'
Software Commands
There are two special software commands which
can be executed in the Program Condition.
Clear First/Last Flip/Flop: This command may be
issued prior to writing or reading SAB 8237 A
address or word count information. This initializes
the Flip/Flop to a known state so that subsequent
accesses to register contents by the microprocessor
will address lower and upper bytes in the correct
sequence.
Master Clear: This software instruction has the
same effect as the hardware Reset. The Command,
Status, Request, Temporary and Internal First/Last
Flip/Flop registers are cleared and the Mask
register is set.
SAB 8237A
Absolute Maximum Ratings
1)
o to 70°C
-65 to + 150°C
-0.5to +
7V
2W
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (VSS)
Power Dissipation
D.C. Characteristics
TA" Oto 70"C; VCC = 5V ±5%; VSS
Sym bol
= OV
Limit Values
Parameter
Min.
-Output High Voltage
VOH
Typ.
2.4
VO~
-t-------------
"
Unit
Test Condition
Max.
IOH
= -200 rIA
IOH
= -100 rIA (HRQ only)
10l
= 3.2 mA
-
3.3
•_ _ M
, Output low Voltage
VIH
Input High Voltage
_.
2.0
-- -_._----------_.- -----Input low Voitage
·0.5
-- -_._-- --..- - . -..-------- ----Input load Current
III
._-------
0.40
-
IlO
Output Leakayc: Current
---------------.------
ICC
VCC Supply Current
CO
CI
CIO
-
-1:10
130
150
Output Capacitance
4
8
Input Capacitance
8
15
1/0 Capacitance
10
18
-- --'
----
rIA
--
-
r---
-----------
OV
s
VIN
os
VCC
.
0.4 V :S VOUT < VCC
130
-----------
f---
f-110
---
-
c-----
~~-
Vil
V
VCC+0.5
mA
TA " + 25°C
TA
pF
fc
= O"C
II
All outputs
disconnected
= 1.0 MHz, Inputs = 0 V
1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
2) Typical values are for TA ••- 25"C, nominal supply voltage and nominal processing parameters.
361
I
, SAB8237A
A.C. Characteristics
TA = Oto 70"C; vcc = 5V ±5%; vss =
OV
DMA (Master) Mode
Symbol
Parameter
Limit Values
8237A
Min,
Max.
Unit
8237A-5
Min.
Max.
TAEl
AEN High from ClK low (S 1) Delay Time
300
200
TAET
AEN low from ClK High (S 1) Delay Time
200
130
TAFAB
ADR Active to Float Delay from ClK High
TAFC
READ or WRITE Float from ClK High
150
120
TAFDB
DB Active to Float Delay from ClK Hi>Jh
250
~,?0
TAHR
ADR from READ High Hold Time
TCV-l00
TAHS
DB from ADSTB low Hold Time
50
TAHW
ADR from WRITE High Hold Time
TCV-50
DACK Valid from ClK low Delay Time
TAK
TASM
-
-
-
90
TCV-l00
-
40
-
TCY -50
250
11
EOP High from ClK High Delay Time 21
150
250
170
-
170
ETIP low to ClK High Delay Time
250
170
ADR Stable from ClK High
250
170
TASS
DB to ADSTB low Setup Time
100
100
TCH
ClK High Time (transitions,,; 10 ns)
120
80
TCl
ClK low Time (transitions"; 10 ns)
150
68
TCV
ClK Cycle Time
320
200
ns
-
TDCl
ClK High to READ or WRITE low Delay 31
270
190
TDCTR
READ High from ClK High (S4) DeiayTime3J
270
190
TDCTW
WRITE High from ClKHigh (S4) DeiayTime 31
TDOl
-
200
-
160
HRG Valid from ClK High Delay Time 41
TD02
130
120
250
120
TEPS
EOP low from ClK low Setup Time
60
TEPW
EOP Pulse Width
300
TFAAB
ADR Float to Active Delay from ClK High
250
170
TFAC
READ or WRITE Active from ClK High
200
150
TFADB
DB Float to Active Delay from ClK High
300
200
Notes see next page,
362
-
40
-
220
ns
SAB 8237A
Symbol
Parameter
limit Values
8237A
Min.
Max.
Min.
THS
HlDA Valid to ClK High Setup Time
100
75
TIDH
Input Data from MEMR High Hold Time
0
0
TIDS
Input Data to MEMR High Setup Time
250
170
TODH
Output Data from MEMW High Hold Time 20
TODV
Output Data Valid to MEMW High
5)
-
10
200
125
TOS
DREO to ClK low (Sl, S4) Setup Time
0
0
TRH
ClK to READY low Hold Time
20
20
100
1)
TRS
READY to ClK low Setup Time
TSTl
ADSTB High from ClK High Delay Time
TSn
ADSTB low from ClK High Delay Time
TOH
DR EO from DACK Valid Hold Time
0
TROHA
HRO to HlDA Delay Time
1
-
Unit
8237A-5
Max.
-
ns
60
200
-
140
-
130
90
0
1
-
clk
1) DREO and DACK signals may be active high or low. Timing diagrams assume the active high mode.
2) EOP is an open collector output. This parameter assumes the presence of a 2.2 k" pullup to VCC.
3) The net lOW or MEMW pulse width for normal write will be TCY -100 ns and for extended write will be
2TCY -100 ns. The net lOR or MEMR pulse width for normal read will be 2TCY -50 ns and for compressed
read will be TCY -50 ns.
4) TOO is specified for two different output high levels. TOOl is measured at 2.0 V. TD02 is measured
a 3.3V. The value for TD02 assumes an external 3.:> kQ pull-up resistor connected from HRO to
vcc.
5) If N wait states are added during the write-to-memory half of a memory-to-memory transfer, this
parameter will increase by N (TCY).
363
SAB8237A
Peripheral (Slave) Mode
Symbol
Parameter
Limit Values
8237A
Min.
ADR Valid or CS Low to READ Low
50
TAW
ADR Valid to WRITE High Setup Time
200
TCW
CS Low to WRITE High Setup Time
200
TAR
Max.
Unit
8237A-5
Min.
Max.
50
130
-
130
-
TOW
Data Valid to WRITE High Setup Time
200
130
TRA
ADR or CS Hold from READ High
0
0
TRDE
Data Access from READ Low
-
200
-
140
20
100
0
70
I I lVI
11
uD riua' ueiay rrom KI:AU HIgh
TRSTO
Power Supply High to RESET Low Setup Time 500
500
TRSTS
RESET to First IOWR
2TCY
2TCY
TRSTW
RESET Pulse Width
300
300
TRW
READ Width
300
TWA
ADR from WRITE High Hold Time
20
20
TWC
CS High from WRITE High Hold Time
20
20
TWD
Data from WRITE High Hold Time
30
30
TWWS
WRITE Width
200
160
-
200
1) Output loading is 1 TTL gate plus 150 pF capacitance, unless otherwise noted.
Input Waveforms for AC-Tests
2.4
0.4
364
-
ns
SAB 8237A
Slave Mode Write Timing
i----------TCW
--------~
t-----------TWWS--------~
TWA
t------------------TAW-------------~~
Input valid
M-A3
t-----------------TDW---------~
DB¢-DB7
I
Input valid
Slave Mode Read Timing
-----..
/
CS
A0-A3
)
~TAR1
lOR
DB~-DB7
=t
K
Address must be valid
~
TR
TRW
TRDE
(
''1
TRDF3Data out valid _ _
1) Successive read and/or write operation by the CPU to program or examine the controller must
be timed to allow at least 600 ~s for the SAB 8237 A and at least 400 ns for the SAB 8237A-5, as
recovery time between active read or write pulses_
365
SAB8237A
'*
F
DMA Transfer Timing
50~ 50~
51
vI \J
ClK
W
HI nA
5H 52J 53
0
J
--'I
HRQ
J
em)}\'l\'l\
~~L
~I JII/~,--l
54
51
51
t
i
I
1)
l!'l IV']
I--
--'-
~ 1"'- r~
I
I
i
I
i
'1--+---
r
I
\\\\\\\\\
"""1\
-----T;r------~I
AET
'-----
--,-~~
I
I-
ADSTB
:
~
__
~
I'
TcH
I-'-"-'
TCY -
~"--+-H-+_+--+-+-h
1TRQHAH11-+
,
,J I
I
AEN
51
U[ V[ \J f-If \J -;-,-11+-
f-I
nt-+
DREQ
5'1 52J 53
~T~A~55-r+-+--+-~-+~------
I~-l~
DBO-DB? -------1,;~---+-I~t-~l-t-+-+--+--+---t!----~-
_
_T~
~
-I
I-
AO-A7
~
_
I TASM
t-I
Address valid
1DACK
!ill..
i
,--::-
~JS.
I
I.!!ill..
-r--'\ - -
-
(for extended Writel-
~
-
I TAFAB
_
H
.;JAHW
Address valid
--'-
_IAHR
I
JQCTI
~___
\
:Frf
,---,
r---"\
r-llilli
{
JAHR
--
~l-TW_______
2 --=--- ~~ -~~KI-1-~ IJ
lQQ,..
INT
EDP - - - - T I I - - - - - - - - - + - - - - t - .
EXT EOP
-~!.'~-"T'T"\\\rTT"\ST"T'T\\\'"t"'T"\\W
1) DREG should be held active until DACK is returned.
366
TAK
~
wllllmm
SAB8237A
Memory-to-Memory Transfer Timing
CLK
AD5TB
TFAAB
AO-A7
TFADB
OBO-OB7
TOCL
TFAC
r
TOUR
J
H-c
:::1flill!'
TAfC
1105
~~------+---~~--.I
MEMR
TOCTh'
INT
EOP
TEPS
=::::j
EXT
E5P
~
1EPW
~
~
I-
;::JTEPW
~
Y/ 777'-----'-\"'\1\ ~ Y/..-r-T777--r-r77"rr"77r-r-777rT7
Ready Timing
elK
Extended~
Write
READY
\\\\\\\\a
TRS
TRS
3~7
SAB8237A
Compressed Transfer Timing
ClK
AO-A7
READY
INT EOP
EXT EOP
------?,,~~
~ Jjj
Reset Timing
vee
RESET
lOR or lOW
368
~I----'_
_______..J)"
"'TO
~
TRSTW--
II
k,i~
SAB 8256A, SAB 8256A-2
Programmable Multifunction
UART (MUART)
• SAB 8256A compatible with processors up to
3 MHz system clock (e. g. SAB 8085A, SAB 8048,
SAB8051).
SAB 8256A-2 compatible with processors up to
8 MHz system clock (e.g. SAB 8085A-2, SAB 8086
- minimum mode, SAB 80186).
• Full-Duplex asynchronous serial interface with
programmable 5-8 data bits, 0.75-2 stop bits,
parity generation and checking.
• Internal baud rate generator programmable for
50-19200 Baud; 0-1 Megabaud possible with
external baud rate clock.
Pin Configuration
• Interrupt Controller with 8 priority levels; each
level independently maskable, programmable
for normal and fully nested operation with
SAB 8085 and SAB 8086 processor families.
• Five programmable 8-bit counter/timers,
internal or external clock, four are cascadable
to two 16-bit counter/timers.
• Two 8-bit I/O ports, bit programmable for
input/output, hand-shake mode supported.
I
logic Symbol
Mlkraprozessor·
PerlpheneSchrlltfstelle
Schnlttstelle
Vee
P 10
PII
PI2
Pl3
P14
AD~
- A0 4
P1O-P17
08 5 -OB7
P20-P27
P 15
P16
CS
R, D
P17
P 2D
mJ
WIl
P11
WR
E'fS
RESET
P21
ALE---
CS
W
;;:c
P23
P 24
INT
P25
EXTINT
~
P 26
P 27
hD
R,D
GND
TiC
CfS
eLK
SABB256A1
8256A-2
RESET
I
....
a>
Address
Read Registers
:II
CD
5AB 8085 Mode: AD3 AD2 AD1 AD0
5AB 8086 Mode: AD4 AD3 AD2 AD1
CQ
iii"
rot
...
C/)
CD
CL1
CL0
51
50
BITI
BRKI
FRO
8086
0
0
0
0
CLl
CL0
51
Command Word 1
PEN
EP
C1
C0
B3
RxE
IAE
NIE
END
B2
I
B1
B0
0
0
PEN
0
EP
C1
T24
T5C
CT3
CT2
C0
5BRK
I
TBRK
I
5RES
I
0
0
0
0
RxE
IAE
P16
P15
P14
P2C21 P2C1
I
P2C01
0
0
T35
T24
L6
L5
L4
P13
L3
FRO
B3
i
NIE
0
rot
B2
I
B1
B0
TBRK
I
P2C21 P2C1
I
SBRK
T5C
CT3
CT2
P12
P11
P10
0
0
0
P17
P16
P15
P14
P13
P12
I
0
P2C01
P11
P10
L1
L0
Pan 1 Control Register
L2
Interrupt-Level Enable Word
L1
L0
0
0
L7
L6
L5
L4
L3
L2
Interrupt Mask Register
CD
CD
~
Mode Register
Port 1 Control Word
L7
8086
Command Register 3
Mode Word
P17
BITI
Command Register 2
Command Word 3
T35
BRKI
Cc·mmand Register 1
Command Word 2
5ET
50
C/)
»
o::J
CO
N
U1
en
»
Write Registers
Address
SAB 8085 Mode: A03 A02
SAB 8086 Mode: A04 A03
I
L7
I
L5
L6
L4
L3
L2
L1
I
LO
I
A01
A02
0
Read Registers
AOO
A01
0
I
07
06
05
Interrupt-Level Oisable Word
07
06
05
I
04
I
03
I
02
I
06
I
05
I
04
I
03
I
01
0
00
1
I
07
I
06
I
05
I
07
I
06
I
05
04
02
DO
01
I
1
0
0
0
I
07
06
05
07
I
05
06
I
04
03
03
I
02
01
00
I
03
I
02
01
02
01
DO
I
00
I
03
Read Port 1
02
03
I
04
04
01
DO
I
1
0
0
I
07
I
05
06
03
04
Write Port 2
I
I
Receiver Buffer
Write Port 1
I
04
Interrupt Address Register
Transmitter Buffer
07
I
02
I
01
DO
02
I
01
DO
Read Port 2
I
02
01
00
I
1
0
0
I
07
I
05
06
04
03
Read Timer 1
Write Timer 1
CJ)
l>
OJ
I
w
-..J
-..J
07
I
06
I
05
04
03
02
Write Timer/Counter 2
01
I
00
I
0
1
I
07
I
06
I
05
I
04
I
03
I
02
Read Timer/Counter 2
01
00
I
00
N
(11
(7)
l>
~
~
SAB 8256A)
Data Vat,d
ALE
Read Cycle (SAB 8256A --> Processor)
; - - - - - - - lAD
-------1
ALE
llll
(iNTAl
385
SAB8256A
Interrupt Timings
CLK~~
p17(\nterrUPt~Pt~[--
,'r,------------
from P o r l 1 ) :
I--- tOPI---1
tOEX--l
EXTINT
Internal
Interrupt
~
\
\
~jr--""
---='-'r
INT _ _ _ _ _ _
\~
J
\'---- - - - '
O!,:, -----------------~I-----:::x
* ___ _
03 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
a.blt value 1)
>---
Basic Output from Port 1 and Port 2
------------:::x
OB,_)
A0-J _ _ _ _ _ _ _ _ _ _ _ _
V---------
__ _ _
O_ot_o_Vo_I-,_ _ ___
~~~ __________~)¢~_~_I_a_~_lid_I_,II_~_XI~7:,~I_,------------1) Instead of INTA, RD can serve as interrupt
acknowledge (reading the interrupt address
register).
2) Read from channel 2.
3) If INTA is enabled, RSTn instruction is output on
INTA (SAB 8085 mode) or interrupt vector is
output on second INTA (8086 mode) otherwise,
interrupt address is output on a read address
register operation.
387
SAB8256A
Count Pulse Timings and
Zero-Crossing of Counter
P12,P13
(Counter Input) ----II
I
I
11-.----- tePI ---------1"
I
INT
l
Edge Causing
Zero Count
tTPI--j
----------------~y
Loading Timer 5 (or Cascaded Counter/Timer 3 and 5) and
Zero-Crossing of Counters (Cascaded Counter/Timer 3 and 5)
P13
(Counter Input! _ _ _ _ _-1"
P15
(Trigger Input)
INT
Trigger Pulse for Timer 5 (Cascaded Event
Counter/Timer 3 and 5)
P15
(Trigger Input)
388
/
nm" (.)'OO'''~'' (re)",,'"
t=tTIL~
\""_ _ _ _ _ __
l-tTIH---J
SAB8256A
Reading event counters/timers
ALE
f'-F-ea-d
C-Y cle~/'- _" ;'f- -
I
I-_-<_i-_-----;"'"' Cyo, /'-J-1-_ - -
-tTR-V-I
__
Reset Timing
RESET _ _ _ _ _ _- ' {
...-J--------------
CTS for Single Character Transmission
External Baud Rate Clock for Serial Interface
TxC
(64xand 32x
Baud Rate.lnput)
-rt"~
1 t~J
Ct'~ I
/
\
tsCY
'iXC.
RxC
( 1x Baud Rate.
Input)
trcY
trPD
1
3S9
SAB8256A
Transmitter and Receiver Clock from Internal Clock Source
~!C
2.0
2.0
0.8
0.8
> Test POints <
AC testing: inputs are driven at 2.4 V for a logic
"1" and 0.45 V for a logic "0".
Timing measurements are made at 2.0 V for a
logic "1" and 0.8 V for a logic "0".
A.C. Testing load Circuit
Device
Under
Test
CL=100 pF
CL includes jig capacitance
402
~CL=100PF
SAB8259A
Waveforms
WRITE
i----TWLWH - - . - . ,
WR - - - - - - - - -......
( 5 - - - - - - - - - ~----------~~I ~-----Address Bus
C
A 0 - - - - - - - - J ~------_-----------~~.~--------
__-fT~WH~
Data Bus
READJINTA
_-------- -
RO/INTA
\
I
-----, TRLEL
EN
I
.
----I
IS
TRLRH ______ 3 - -----.<
I
---- IJRHEH
r--
~•
,J AHRl
-:
Xi
Address Bus
A0
•
I
:
1----- - TRLOV -------1
i
f-----TAHDV ----------'
Data Bus
I xRHA~
f--TRHDZ--l
~-----
----------------i
OTHER TIMING
R D i I N T A - \ ' - - -_ _
WR _________......\
1I
'
~---1.
~
r
r
~rnHRl~ '--------J
TWHRL-J-~
403
SAB8259A
INTA SEQUENCE
rIJHIH
1R~li
:NT _ _
INTA
C...
3
--J)-----~\('__-1===~\--l..-
__
-------~
DB - - - - - - - - - -
(02---------------~----~~---------L-------------~----
Notes: Interrupt output must remain HIGH at least until leading edge of first INTA.
1. Cycle 1 in SAB 8086/88 systems, the Data Bus is not active.
404
SAB8275
Programmable CRT Controller
• Programmable screen and character format
.6 independent visual field attributes
• SAB 8051, SAB 8085, SAB 8086 and SAB 8088
compatible
• 11 visual character attributes
(graphics capabilityl
• Dual row buffers
o Programmable DMA burst mode
• Cursor control (4 typesl
Light pen detection and registers
• Single +5V supply
o High performance MYMOS technology
I)
o Fully compatible with industry standard 8275
Pin configuration
Pin Names
LC3[~::::JV(C
lCO-lC3
line Count
DRQ
DMA Request
DACK
DMA Acknowledge
LC2 [
2
39::::J LAO
HRTC
Horizontal Retrace
LCl [
3
38:J LA,
VRTC
Vertical Retrace
LCO[ 4
310LTEN
ORQ [
5
36PRVV
DAn':: [
6
3SP vsp
HRTC [
7
34PGPAl
VRTC [
8
33
iITi[ 9
SAB
W"R[ 10
lPEN [
'1
8275
~GPAO
32DHLGT
31 PIRQ
30 ;JCClK
RD
Read Input
WR
Write Input
lPEN
Light Pen
DBO-DB7
Bidirectional Three-State Data Bus Lines
lAO, lA1
Line Attribute Codes
lTEN
Light Enable
Reverse Video
Video Suppression
DBD [
12
29~[(6
RVV
DBl [
13
28
:Jecs
VSP
DB2 [
14
27:J (CI.
DB3 [
1S
26:J
OBI. [
16
25 ::1((2
DBS [
17
24:J eCl
DB6 [
18
23
DB7 [
19
n:Jrs
GHO [
21)
21 :JAO
((3
::1e(o
GPAO, GPA1
General Purpose Attribute Codes
HlGT
Highlight
IRQ
Interrupt Request
CClK
Character Clock
CCO-CC6
Character Codes
CS
Chip Select
AD
Port Address
The SAB 8275 programmable CRT controller is a
single chip device to interface CRT raster scan
displays. It is manufactured in Siemens advanced
MYMOS technology. Its primary function is to
refresh the display by buffering the information
from main memory and keeping track of the
display position of the screen. The flexibility
designed into the SAB 8275 will allow simple
interface to almost any raster scan CRT display
with a minimum of external hardware and software
overhead.
AG 2185
405
SAB 8275
Pin Definitions and Functions
Input (I)
Output (0)
Symbol
Number
Function
LC3
LC2
LC1
LCO
1
2
3
4
a
LINE COUNT: Output from the line counter which is used to
address the character generator for the line positions on the
screen.
DRQ
5
a
DMA REQUEST: Output signal to the SAB 8237A DMA
controller requesting a DMA cycle.
DACK
6
I
DMA ACKNOWLEDGE: Input signal from the SAB 8237A
DMA controller acknowledging that the requested DMA cycle
has been granted.
HRTC
7
0
HORIZONTAL RETRACE: Output signal which is active during
the programmed horizontal retrace interval. During this period
the VSP output is high and the LTEN output is low.
VRTC
8
a
VERTICAL RETRACE: Output signal which is active during the
programmed vertical retrace interval. During this period the
VSP output is high and the LTEN output is low.
RD
9
I
READ INPUT: A control signal to read registers.
WR
10
I
WRITE INPUT: A control signal to write commands into the
control registers or write data into the row buffers during a
DMAcycle.
LPEN
11
I
LIGHT PEN: Input signal from the CRT system signifying that a
light pen signal has been detected.
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
12
13
14
15
16
17
18
19
I/O
BIDIRECTIONAL THREE-STATE DATA BUS LINES:
The outputs are enable during a read of the C or P ports.
LAO
LA1
39
38
a
LINE ATTRIBUTE CODES: These attribute codes have to be
decoded externally by the dot/timing logic to generate the
horizontal and vertical line combinations for the graphic
displays specified by the character attribute codes.
LTEN
37
a
LIGHT ENABLE: Output signal used to enable the video signal
to the CRT. This output is active at the programmed underline
cursor position, and at positions specified by attribute codes.
RVV
36
a
REVERSE VIDEO: Output signal used to indicate the CRT
circuitry to reverse the video signal. This output is active at the
cursor position if a reverse video block cursor is programmed
or at the positions specified by the field attribute codes.
406
SAB 8275
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
VSP
35
0
VIDEO SUPPRESSION: Output signal used to blank the video
signal to the CRT. This output is active:
- During the horizontal and vertical retrace intervals.
- at the top and bottom lines of rows if underline is
programmed to be number 8 or greater.
- when an end of row or end of screen code is detected.
- when a DMA underrun occurs.
- at regular intervals (1/16 frames frequency for cursor,
1/32 frame frequency for character and field attributes)to create blinking displays as specified by cursor, character
attribute, or field attribute programming.
GPA1,
GPAO
34
33
0
GENERAL-PURPOSE ATTRIBUTE CODES: Outputs which are
enable by the general purpose field attribute codes.
HLGT
32
0
HIGHLIGHT: Output signal used to intensify the display at
particular positions on the screen as specified by the character
attribute codes or field attribute codes.
IRQ
31
0
INTERRUPT REQUEST.
CCLK
30
I
CHARACTER CLOCK (from dot/timing logic).
CC6
CC5
CC4
CC3
CC2
CCl
CCO
29
28
0
CHARACTER CODES: Output from the row buffers used for
character selection in the character generator.
CS
22
I
CHIP SELECT: The read and write are enabled by CS.
AO
21
I
PORT ADDRESS: A high input on AO selects the "C" port or
command registers and a low input selects the "P" port or
parameter registers.
VCC
40
-
+ 5 V Power supply.
GND
20
-
Ground (OV)
Function
27
26
25
24
23
407
I
SAB 8275
SAB 8275 Block diagram showing counter and register functions
Character
Counter
DBO-7
CClK
Data
Bus
Buffer
CCO-6
DRQ
DACK
IRQ
Line
lCD- 3
Coun~r
RD
WR
Row
Counter
AD
CS
lAD-'
HRTC
VRTC
HlGT
RVV
lTEN
VSP
GPAO-'
Raster Timing
and
Video Control
light Pen
Registers
Functional Description
Data bus buffer
This three-state, bidirectional, 8-bit buffer is used to
interface the SAB 8275 to the system data bus.
This functional block accepts inputs from the system
control bus and generates control signa Is for overall
device operation. It contains the command,
parameter, and status registers that store various
control formats for the device functional definition.
408
lPEN
AD
Operation
Register
0
Read
PREG
0
Write
PREG
1
Read
SREG
1
Write
CREG
AO
RD
WR
CS
0
0
1
0
0
1
1
1
0
1
0
X
X
1
1
1
0
0
0
0
0
X
X
1
Write SAB 8275 parameter
Read SAB 8275 pa ra meter
Write SAB 8275 command
Read SAB 8275 status
Th ree-state
Th ree-state
SAB 8275
RD (Read)
Raster timing and video controls
A "low" on this input informs the SAB 8275 that the
CPU is reading data or status information from the
SAB 8275.
The raster timing circuitry controls the timing of the
HRTC (Horizontal Retrace) and VRTC (Vertical
Retrace) outputs. The video control circuitry
controls the generation of LAO-1 (line attribute!.
HGL T (highlight), RVV (reverse video), LTEN (Light
enable), VSP (video suppress), and GPAO-1
(general purpose attribute) outputs.
WR (Write)
A "low" on this input informs the SAB 8275 that the
CPU is writing data or control words to the
SAB 8275.
CS (Chip select)
A "low" on this input selects the SAB 8275. No
reading or writing will occur unless the device is
selected. When CS is high, the data bus in the float
state and RO and WR will have no effect on the chip.
Row buffers
The row buffers are two 80 character buffers. They
are filled from the microcomputer system memory
with the character codes to be displayed. While
one row buffer is displaying a row of characters, the
other is being filled with the next row of characters.
DRQ (DMA request)
FIFOs
A "high" on this output informs the OMA controller
that the SAB 8275 desires a OMA transfer.
There are two 16 character FIFOs in the 8275. They
are used to provide extra row buffer length in the
transparent attribute mode.
DACK (DMA acknowledge)
A "low" on this input informs the SAB 8275 that a
OMA cycle is in progress.
IRQ (Interrupt request)
A "high" on this output informs the CPU that the
SAB 8275 desires interrupt service.
Character counter
The character counter is a programmable counter
that is used to determine the number of characters
to be displayed per row and the length of the
horizontal retrace interval. It is driven by the CClK
(character clock) input, which should be a derivative
of the external dot clock.
Buffer input/output controllers
The buffer input/output controilers decode the
characters being placed in the row buffers. If the
character is a character attribute, field attribute or
special code, these controllers control the
appropriate action (Examples: An "end of screenstop OMA" special code will cause the buffer input
controller to stop further OMA requests. A
"highlight" field attribute will cause the buffer
output controller to activate the HGLT output).
Line counter
The line counter is a programmable counter that is
used to determine the number of horizontal lines
(sweeps) per character row. Its outputs are used to
address the external character generator ROM.
Row counter
The row counter is a programmable counter that is
used to determine the number of character rows to
be displayed per frame and length of the vertical
retrace interval.
Light pen registers
The light pen registers are two registers that store
the contents of the character counter and the row
counter whenever there is a rising edge on the lPEN
(Light Pen) input.
Note: Software correction is required.
409
SAB 8275
System Operation
The SAB 8275 is programmable to a large number of
different display formats. It provides raster timing,
display row buffering, visual attribute decoding,
cursor timing, and light pen detection.
It is designed to interface with the SAB 8237A DMA
controller and standard character generator ROMs
for dot matrix decoding. Dot level timing must be
provided by external circuitry.
SAB 8275 Block diagram showing systems operation
I
11
!
J
System Bus
DBO- DB7
MEMR,1OW
MEMW
i'OR
CS, HRU
HlDA
I
I
Memories
SAB 8237A
DMA
Controller
I
AO
DBO-DB7
WR
Rii
CS
IRQ
lCO- 3
DRQ
DACK
SAB
8275
CRT
Controller
1
;!
Character
Generator
CCO- 6
I
Video Siqna\
r
SAB
82731
CClK
Dot Timing
and Interface
Video Controls
VRTC
HRTC
~
Matching
Circuit
HSYNC
VSYNC
Raster timing
The character counter is driven by the character
clock input (CCLK).lt counts out the characters being
displayed (programmable from 1 to 80). It then
causes the line counter1o increment, and it starts
counting out the horizontal retrace (programmable
from 2 to 32). This is constantly repeated.
The line counter is driven by the character counter.
It is used to generate the line address outputs
(LCO-3) for the character generator. After it counts
all of the lines in a character row (programmable
from 1 to 16), it increments the row counter, and
starts over again. (See Character Format Section for
detailed description of Line Counter functions.)
410
The row counter is an internal counter driven by the
line counter. It controls the functions of the row
buffers and counts the number of character rows
displayed.
After the row counter counts all of the rows in a
frame (programmable from 1 to 64), it starts
counting out the vertical retrace interval
(programmable from 1 to 4).
The video suppression output (VSP) is active during
horizontal and vertical retrace intervals.
Dot level timing circuitry must synchronize these
outputs with the video signal to the CRT display.
SAB 8275
DMAtiming
The SAB 8275 can be programmed to request burst
DMA transfers of 1 to 8 characters. The interval
between bursts is also programmable (from 0 to 55
character clock periods ± 1). This allows the user to
tailor his DMA overhead to fit his system needs.
The first DMA request of the frame occurs one row
time before the end of vertical retrace. DMA requests
continue as programmed, until the row buffer is
filled. If the row buffer is filled in the middle of a
burst, the SAB 8275 terminates the burst and resets
the burst counter. No more DMA requests will occur
until the beginning of the next row. At that time, DMA
requests are activated as programmed until the
other buffer is filled.
The DMA request for a row will start at the first
character clock of the preceding row. lithe bu rst
mode is used, the first DMA request may occur a
number of character clocks later. This number is
equal to the programmed,burst space.
If, for any reason, there is a DMA underrun, a flag in
the status word will be set.
DMAtiming
Internal
Row
Counter
Lost Retrace Row
First Display Row
VRTC
ORa
Next
Row Buffer
Filled
The DMA controller is typically initialized for the next frame at the end of the current frame.
Interrupt timing
The SAB 8275 can be programmed to generate an
interrupt request at the end of each frame. This can
be used to reinitialize the DMA controller. If the
SAB 8275 interrupt enable flag is set, an interrupt
request will occur at the beginning of the last display
row.
=xx
Beginning of interrupt request
Internal
Row
Counter
VRTC
~'r---~>--_..J
IRa
411
SAB 8275
IRO will go inactive after the status register is read.
End of interrupt request
IRQ
"
-----.\'--------JrA reset command will also cause IRO to go inactive,
but this is not recommended during normal service.
vertical retrace (VRTC) signals. The timing of these
signals is programmable.
Another method of reinitializing the.DMA controller
is to have the DMA controller itself interrupt on
terminal count. With this method, the SAB 8275
interrupt enable flag should not be set.
The SAB 8275 can generate a cursor. Cursor location
and format are programmable. (See programming
section.)
Note: Upon power-up, the SAB 8275 interrupt
Enable Flag may be set. As a result, the user's cold
start routine should write a reset command to the
SAB 8275 before system interrupts are enabled.
General systems operational description
The SAB 8275 provides a "window" into the microcomputer system memory.
Display characters are retrieved from memory and
displayed on a row by row basis. The SAB 8275 has
two row buffers. While one row buffer is being used
for display, the other is being filled with the next row
of characters to be displayed. The number of display
characters per row and the number of character
rows per frame are software programmable,
providing easy interface to most CRT displays.
(see programming section.)
The SAB 8275 requests DMA to fill the row buffer
that is not being used for display. DMA burst length
and spacing is programmable. (See programming
section.)
The SAB 8275 displays character rows one line at a
time.
The number of lines per character row, the underline
position, and blanking of top and bottom lines are
programmable. (See programming section.)
The SAB 8275 provides special control codes which
can be used to minimize DMA or software overhead.
It also provides visual attribute codes to cause
special action or symbols on the screen without the
use of the character generator (see visual attribute
section).
The SAB 8275 also controls raster timing. This is
done by generating horizontal retrace (HRTC) and
412
The SAB 8275 has a light pen input and registers.
The light pen input is usedto load the registers. Light
pen registers can be read on command. (See programming section.)
Display row buffering
Before the start of a frame, the SAB 8275 requests
DMA and one row buffer is filled with characters.
When the first horizontal sweep is started, character
codes are output to the character generator from the
row buffer just filled. Simultaneously, DMA begins
filling the other row buffer with the next row of
characters.
After all the lines of the character row are scanned,
the roles of the two row buffers are reversed and the
same procedure is followed for the next row.
This is repeated until all of the character rows are
displayed.
Screen format
The SAB 8275 can be programmed to generate
from 1 to 80 characters per row, and from 1 to 64
rows per frame.
The SAB 8275 can also be programmed to blank
alternate rows. In this mode, the first row is
displayed, the second blanked, the third displayed,
etc. DMA is not requested for the blanked rows.
Row format
The SAB 8275 is designed to hold the line count
stable while outputting the appropriate character
codes during each horizontal sweep. The line count
is incremented during horizontal retrace and the
whole row of character codes are output again
during the next sweep. This is continued until the
whole character row is displayed.
SAB 8275
The number of lines (horizontal sweeps I per
character row is programmable from 1 to 16.
The output of the line counter can be programmed
to be in one of two modes.
Blanking is accomplished by the VSP (Video
Suppression) signal. Underline is accomplished by
the LTEN (light enable) signal.
Dot format
In mode 0, the output of the line counter is the same
as the line number.
Dot width and character width are dependent upon
the external timing and control circuitry.
In mode 1, the line counter is offset by one from the
line number.
Dot level timing circuitry should be designed to
accept the parallel output of the character generator
and shift it out serially at the rate required by the
CRT display.
Note: In mode 1, while the first line (line numberOI is
being displayed, the last count is output by line
counter.
Dot width is a function of dot clock frequency.
Mode 0 is use ful for character generators that leave
address zero blank and start at address 1, Mode 1 is
useful for character generators which start at
address zero.
Character width is a function of the character
generator width.
Underline placement is also programmable (from
line number 0 to 151. This is independent of the line
counter mode.
Note: Video control and timing signals must be
synchronized with the video signal due to the
character generator access delay.
Horizontal character spacing is a function ofthe shift
register length.
If the line number of the underline is greater than 7
(line number MSB = 11, then the top and bottom
lines will be blanked.
If the line number of the underline is less than or
equal to 7 (line number MSB = 0), then the top and
bottom lines will not be blanked.
If the line number underline is greater than the
maximum number of lines, the underline will not
appear.
413
SAB 8275
Visual Attributes and Special Codes
The characters processed by the SAB 8275 are 8-bit
quantities. The character code outputs provide the
character generator with 7 bits of address. The most
significant bit is the extra bit and it is used to determine if it is a normal display character (MSB = 0),
or if it is a Visual Attribute or Special Code (MSB = 1).
There are two types of visual attribute codes.
They are character attributes and field attributes.
Character attribute codes
Character attribute codes are codes that can be used
to generate graphics symbols without the use of a
character generator. This is accomplished by selectively activating the line attribute outputs (LAO-1),
the video suppression output (VSP), and the light
enable output. The dot level timing circuitry can use
these signals to generate the proper symbols.
Character attributes can be programmed to blink or
be highlighted individually. Blinking is accomplished with the video suppression output (VSP).
Blink frequency is equal to the screen refresh
frequency divided by 32. Highlighting is accomplished by activating the highlight output (HGL T).
Character attributes
LSB
MSB
11CCCCBH
I L-L -_ _ _ _
Special codes
HIGHLIGHT
BLINK
CHARACTER ATTRIBUTE
CODE
Four special codes are available to help reduce
memory, software or DMA overhead.
Special control character
MSB
LSB
111100SS
~ SPECIAL CONTROL CODE
S
S
Function
0
0
0
1
0
End
End
End
End
of Row
of Row-stop DMA
of Screen
of Screen-stop DMA
The end-of-screen-stop DMA code (11) causes the
DMA control logic to stop DMA for the rest of the
frame when it is written into the row buffer. It affects
the display in the same way as the end-of-screen
code (10).
If the stop DMA feature is not used, all characters
after an end-of-row character are ignored, except
for the end-of-screen character, which operates
normally. All characters after an end-of-screen
character are ignored.
Note: If a stop DMA character is not the last
character in a burst or row, DMA is not stopped until
after the next character is read. In this situation,
a dummy character must be placed in memory after
the stop DMA character.
Field attributes
The field attributes are control codes which affect
the visual characteristics for a field of characters,
starting at the character following the code up to,
and including, the character which precedes thenext
field attribute code, or up to the end of the frame. The
field attributes are reset during the vertical retrace
interval.
There are six field attributes:
1. Blink - Characters following the code are caused
to blink by activating the Video Suppression
Output (VSP). The blink frequency is equal to the
screen refresh frequency divided by 32.
2. Highlight- Characters following the code are
caused to be highlighted by activating the
Highlight Output (HGLT).
3. Reverse Video - Characters following the code
are caused to appear with reverseyideo by
activating the Reverse Video Output (RVV).
4. Underline - Characters following the code are
caused to be underlined by activating the Light
Enable Output (L TEN).
5, 6. General Purpose - There are two additional
SAB 8275 outputs which act as general purpose,
independently programmable field attributes.
GPAO-1 are active high outputs.
Field attribute code
LSB
MSB
10URGGBH
IIT~
The End-of-Row code (00) activates VSP and holds it
to the end of the line.
The End-of-Row-Stop DMA code (01) causes the
DMAcontrollogicto stop DMA forthe rest of the row
when it is written into the row buffer. It affects the
display in the same way as the end-of-row code (00).
The end-of-screen code (10) activates VSP and
holds it to the end of the frame.
414
H
B
R
= 1 for highlighting
= 1 for blinking
= 1 for reverse video
HIGHLIGHT
BLINK
GENERAL PURPOSE
REVERSE VIDEO
UNDERLINE
U = 1 for underline
GG = GPA1, GPAO
*" More than one attribute can be enabled at the same time.
Ifthe blinking and reverse video attributes are enabled
simultaneously, only the reversed characters will blink.
SAB 8275
The SAB 8275 can be programmed to provide
visible or invisible field attribute characters.
If the SAB 8275 is programmed in the visible field
attribute mode, all field attributes will occupy a
position on the screen. They will appear as blanks
caused by activation of the video suppression
output (VSP). The chosen visual attributes are
activated after this blanked character.
If the SAB 8275 is programmed in the invisible field
attribute mode, the SAB 8275 FIFO is activated.
Each row buffer has a corresponding FIFO. These
FIFOs are 16 cha racters by 7 bits in size.
When a field attribute is placed in the row buffer
during DMA, the buffer input controller recognizes
it and places the next character in the proper FIFO.
When a field attribute is placed in the buffer output
controller during display, it causes the controller to
immediately put a character from the FIFO on the
character code outputs (CCO-8). The chosen visual
attributes are also activated.
Since the FIFO in 16 characters long, no more then
16 field attribute characters may be used per line in
this mode. If more are used, a bit in the status word
is set and the first characters in the FIFO are written
over and lost.
Lig ht pen detection
A light pen consists of a micro switch and a tiny light
sensor. When the light pen is pressed against the
CRT screen, the micro switch enable the light
sensor. When the raster sweep reaches the light
sensor, it triggers the light pen output.
If the output of the light pen is presented to the
SAB 8275 LPEN input, the row and character position
coordinates are stored in a pair of registers. These
registers can be read on command. A bit in the
status word is set, i ndicati ng that the lig ht pen sig nal
was detected. The LPEN input must be a 0 to 1
transition for proper operation.
Note: Due to internal and external delays, the
character position coordinate will be off by at least
three character positions. This has to be corrected in
software.
Device programming
The SAB 8275 has two programming registers, the
command register (CREG) and the parameter
register (PREG). It also has a status register (SREG).
The command register can only be written into and
the Status registers can only be read from. They are
addressed as follows:
Note: Since the FIFO is 7 bits wide, the MSB of any
characters put in it are stripped off. Therefore, a visual Ao
attribute or special code mustnot immediately follow 0
a field attribute code. If this situation does occur, the
0
visual attribute or special code will be treated as
1
normal display character.
operation
register
Read
PREG
Write
PREG
Read
SREG
Write
CREG
Field and character attribute interaction
1
Character attribute symbols are affected by the
reverse video (RVV) and general purpose (GPAO-l)
field attributes. They are not affected by underline,
blink or highlight field attribute; however, these
characteristics can be programmed individually for
character attribute symbols.
The SAB 8275 expects to receive a command and a
sequence of 0 to 4 parameters, depending on the
command. If the proper number of parameter bytes
are not received before another command is given,
a status flag is set, indicating an improper
command.
Cursor timing
The cursor location is determined by a cursor row
register and a character position register which are
located by command to the controller. The cursor
can be programmed to appear on the display as:
1. a blinking underline
2. a blinking reverse video block
3. a non-blinking underline
4. a non-blinking reverse video block
The cursor blinking frequency is equal to the screen
refresh frequency divided by 16.
If a non-blinking reverse video cursor appears in a
non-blinking reverse video field, the cursor will
appear as a normal video block.
If a non-blinking underline cursor appears in a nonblinking underline field, the cursor will not be visible.
Instruction Set
The SAB 8275 instruction set consists of8 commands
Command
Reset
Start Display
Stop Display
Read Lig ht Pen
Load Cursor
Enable Interrupt
Disable Interrupt
Preset Counters
No. of parameter bytes
4
o
o
2
2
o
o
o
In addition, the status of the SAB 8275 (SREG) can
be read by the CPU at any time.
415
SAB 8275
1 Reset command
Data bus
Command
LSB
Operation
AD
Description
MSB
Write
1
Reset
command
0
Write
0
Screen Camp
Byte 1
S H H H H H H H
Write
0
Screen camp
Byte 2
V V R R R R R R
Write
0
Screen camp
Byte 3
U U U U L L L L
Write
0
Screen camp
Byte 4
M F C C Z Z Z Z
Parameters
0 0
0
0
0 0
0
Action - After the reset command is written, DMA
requests stop, SAB 8275 interrupts are disabled,
and the VSP output is used to blank the screen.
HRTC and VRTC continue to run. HRTC and VRTC
timing are random on power-up.
As parameters are written, the screen composition
is defined.
Parameter - S
Parameter - RRRRRR
Spaced rows
Vertical rows/frame
S
Functions
R
R
R
R
R
R
No. of rows/frame
0
Normal rows
Spaced Rows
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
2
Parameter-HHHHHHH
Horizontal characters/row
H H H H H H H
No. of characters per row
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
2
3
80
Undefined
0
Undefined
Parameter - VV
V
V
0
0
0
1
0
416
3
64
Parameter - UUUU
Underline placement
U
U
U
U
Line number of underline
0
0
0
0
0
0
0
0
0
1
0
3
2
16
Vertical retrace row count
No. of row counts per VRTC
2
3
4
Note: uuuu MSB determines blanking oftop and
botton lines (1 = blanked, 0 = not blanked).
SAB 8275
Parameter-LLLL Number of lines per character row
L L L L
No. of lines/row
o
o
0 0 0
0 0
000
1
2
3
16
Parameter- M
Ni
Line counter mode
Mode 0 (non-offset)
Mode 1 (offset by 1 count)
Parameter - F
z z z
Z
No. of character counis per HRTC
0
0
0
1
0
4
6
0
0
0
0
0
0
2
32
Field attri bute mode
F
Field attribute mode
o
Transparent
Non-transparent
Parameter - CC
Cursor format
C
C
Cursor format
o
o
0
1
Blinking reverse video block
Blinking underline
Nonblinking reverse video block
Nonblinking underling
o
Horizontal retrace count
Line Counter Mode
o
1
Parameter - ZZZZ
417
SAB 8275
2 Start display command
Data bus
Command
Operation
AO
Description
MSB
Write
1
Start display
0
LSB
0
1
S
S
S
B
B
No parameters
SSS
Burst space code
S
S
0
0
0
0
S
0
0
No. of character clocks between
DMA requests
0
0
1
7
15
23
31
39
47
55
0
1
0
0
0
1
0
BB
Burst count code
B
B
No. of DMA cycles per burst
0
0
0
1
0
1
2
4
8
1
Action - SAB 8275 interrupts are enabled, DMA
requests begin, video is enabled, interrupt enable
and video enable status flags are set.
3 Stop display command
Data bus
Command
Operation
AO
Description
MSB
Write
1
Stop display
0
1
LSB
0
0
0
0
0
0
No parameters
Action - Disables video, interrupts remain enabled. HRTC and VRTC continue to run, video enable status
flag is reset, and the "Start display" command must be given to re-enable the display.
4 Read light pen command
Data bus
Command
Parameters
AO
Description
MSB
Write
1
read light pen!
0
Read
0
Char. number
Read
0
Row number
(Char. position
in row)
(Row number)
Action - The SAB 8275 is conditioned to supply the
contents of the light pen position registers in the
next two read cycles of the parameter register.
Status flags are not affected.
418
LSB
Operation
1
1
0
0
0
0
Note: Software correction of light pen position is
required.
0
SAB 8275
5 Load cursor position
Data bus
Operation
Command
AD
Description
MSB
LSB
Write
1
Load cursor
1
Write
0
Char. number
(Char. position
in row)
Write
D
Row number
(Row number)
Parameters
D
D
D
0
D
D
D
Action - The SAB 8275 is conditioned to place, the next two parameter bytes into the cursor position
registers. Status flags not affected.
6 Enable interrupt command
Data bus
Command
Operation
AO
Description
MSB
Write
1
Enable
interrupt
1
D
LSB
1
0
0
D
0
D
0
0
0
0
No parameters
Action - The interrupt enable status flag is set and interrupts are enabled.
7 Disable interrupt command
Data bus
Command
Operation
AD
Description
MSB
Write
1
Disable
interrupt
1
1
LSB
D
0
D
0
No parameters
Action -Interrupts are disabled and the interrupt enable status flag is reset.
8 Preset counters command
Data bus
Command
Operation
AD
Description
MSB
Write
1
Preset
counters
1
1
LSB
1
0
0
0
No parameters
419
SAB 8275
Action - The internal timing counters are preset,
corresponding to a screen display position at the
top left corner. Two character clocks are required for
this operation. The counters will remain in this state
until any other command is given.
This command is useful for system debug and
synchronization of clustered CRT displays on a
single CPU. After this command, two additional
clock cycles are required before the first character
of the first row is put out.
Status flags
Command
Operation
AO
Description
Data bus
MSB
LSB
Read
1
Status word
OIEIRlPICYEDUFO
IE - (Interrupt Enable) Set or reset by command.
It enables vertical retrace interrupt. It is automatically set by a "Start Display" command
reset with the "Reset" command.
IR
420
(Interrupt Request) This flag is set at the
beginning of display of the last row of the
frame if the interrupt enable flag is set. It is
reset after a status read operation.
LP - This flag is set when the light pen input (LPEN)
is activated and the light pen registers have
been loaded. This flag is automatically reset
after a status read.
IC - (Improper Command) This flag is set when a
command parameter string is too long or too
short. The flag is automatically reset after a
status read.
VE - (Video Enable) This flag indicates that video
operation of the CRT is enabled. This flag is
set on a "Start Display" command, and reset
on a "Stop Display" or "Reset" command.
DU - (DMA Underrun) This flag is set whenever a
data underrun occurs during DMA transfers.
Upon detection of DU, the DMA operation is
stopped and the screen is blanked until after
the vertical retrace interval. This flag is reset
after a status read.
FO - (FIFO Overrun) This flag is set whenever the
FIFO is overrun. It is reset on a status read.
SAB 8275
Absolute Maximum Ratings
1)
Temperatu re under bias
Storage temperature
All output ans supply and supply voltages
All input voltages
Power dissipation
o to +70 'e
-65 to +150'e
-0,5 to
+7 V
-0,5 to +5,5 V
1,OW
DC Characteristics
(TA = o'e to 70'e, vee = 5 V ±5%)
Symbol
Parameter
Limit values
Min.
Max.
Unit
Test condition
VIL
Input low voltage
-0.5
0.8
VIH
Input high voltage
2.0
Vee+0.5V
VOL
Output low voltage
-
0.45
10L = 2.2 mA
VOH
Output high voltage
2.4
-
10H = -400 ItA
ilL
Input load current
10FL
Output float leakage
lee
vee supply current
±10
V
VIN =veetoOV
ItA
VOUT = vec to 0.45 V
-
160
mA
-
Unit
Test condition
Capacitance
(TA = 25'C, vce
Symbol
= GND = OV)
Parameter
CIN
Input capacitance
CliO
1/0 capacitance
Limit values
Min.
-
Max.
10
20
pF
fc
= 1 MHz
Unmeasured pins
returned to GND
1) Stresses above those listed under "absolute maximum ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
421
I
SAB 8275
AC Characteristics (SAB 8275)
(TA = OCto 70'C, VCC = 5.0V
± 5%, GND =
OV)
Clock timing
Symbol Parameter
Limit values
Min.
TCLK
Clock period
480
TKH
Clock high
240
TKL
Clock low
160
TKR
Clock rise
TKF
Clock fall
5
Max.
Units
Test condition
ns
-
Unit
Test condition
-
30
Bus parameters
Read cycle
Symbol Parameter
TAR
Address stable before READ
TRA
Address hold time for READ
TRR
READ pulse width
TRD
Data delay from READ
TDF
READ to data floating
Limit values
Min.
Max.
0
250
-
ns
200
CL
= 150 pF
100
Write cycle
Symbol Parameter
Limit values
Min.
TAW
Address stable before WRITE
TWA
Address hold time for WRITE
TWW
WRITE pulse width
250
TOW
Data seting time for WRITE
150
TWD
Data hold time f0r WRITE
0
422
Max.
Unit
Test condition
ns
-
0
-
SAB 8275
Other timings
Limit values
Symbol
Parameter
TCC
Character code output delay
150
THR
Horizontal retrace output delay
200
TLC
Line count output delay
400
TAT
Control-attribute output delay
TVR
Vertical retrace output delay
TRI
IRQ~ from RDj
TWQ
DRQj from WRj
TRQ
DRQl from WRl
TLR
DACKl to WR~
TRL
WRj to DACKj
TPR
TPH
Min.
Max.
Unit
Test condition
CL
275
= 50 pF
250
ns
200
0
-
LPEN rise
-
50
LPEN hold
100
-
I
-
423
SAB 8275
AC Characteristics (SAB 8275-2)
(TA = OC to 70°C, VCC = 5.0V
± 5%, GND = OV)
Clock timing
Symbol Parameter
TCLK
Clock period
TKH
Clock high
TKL
Clock low
TKR
Clock rise
TKF
Clock fall
Limit values
Min.
Max.
Unit
Test condition
ns
-
Unit
Test condition
320
120
5
-
30
Bus parameters
Read cycle
Symbol Parameter
TAR
Address stable before READ
TRA
Address hold time for READ
TRR
READ pulse width
TRD
Data delay from t1EAD
TDF
READ to data floating
Limit value
Min.
Max.
0
-
250
-
ns
200
CL = 150 pF
100
CL = 150 pF
Write cycle
Symbol Parameter
Limit values
Min.
TAW
Address stable before WRITE
TWA
Address hold time for WRITE
TWW
WRITE pulse width
250
TDW
Data seting time for WRITE
150
TWD
Data hold time for WRITE
0
424
Max.
Unit
Test condition
ns
-
0
-
SAB 8275
Other timings
Limit values
Symbol Parameter
Min.
TCC
Character code output delay
THR
Horizontal retrace output delay
TLC
Line count output delay
TAT
Control-attribute output delay
TVR
Vertical retrace output delay
TRI
IROl from RDj
TWO
DROI from WRr
TRO
DROl from WRl
TLR
DACKl to WRl
TRL
WRj to DACKj
TPR
TPH
Max.
Unit
Test condition
150
-
CL
= 50 pF
250
ns
200
a
-
LPEN rise
-
50
LPEN hold·
100
-
-
A.C. Testing input/output
24=X >
2.0
0.45
x=
2.0
Test Points
<::
0.8
0.8
AC Testing: Inputs are driven at 2.4 V for a logic" 1" and 0.45 V for a logic "0".
Timing measurements are made at 2.0V for a logic "1" and 0.8V for a logic "0".
A.C. Testing load circuit
Device
Under
Test
rt
CL
CL Includes Jig Capacitance
425
SAB 8275
Waveforms
Typical dot level timing
EXT DOT CLK
CCLK*
CCO-CC6
l
L
First Character Code
Second Character Code
ROM Access
Character
Generator
Output
First Character
Second Character
Attributes
& Controls
Video
(from Shift
Register)
~--------~v~----------~
Attributes
& Controls
(from Synchronizer)
First Character
Attributes & Controls
for First Character
}l.ttributes & Controls
for 2nd Character
*CCLK is a Multiple of the Dot Clock and an Input to the SAB 8275
426
SAB 8275
Line timing
CClK
CCO-CC6
HRTC
lCO-lC3
Present Line Count
~--~T~A~T------------~\r-------------------~~~~-------
Video
Controls
and
Attributes*
==xL
X
C:x
- - - - - ' '---~
:': . .'£
X'-------'>,1-----.
----'
*lAO-lA1 VSP lTEN HGlT RVV GPAO-GPA1
427
SAB 8275
Row timing
CClK
HRTC
lCQ-lC3
1 - - - - - - - Programmable from 1 to 16
Internal - - - - ' "
Row
last Row
Counter
Present Row
:
Frame timing
CClK
Internal
Row
Counter
- - - l - - Programmable from
1 to 4 Rows
VRTC
428
SAB 8275
Interrupt timing
AO
ES
REi
IRa
;f
L",~
DMAtiming
ORQ
LPEN
~
\'---
-~~
~HL
429
SAB 8275
Write timing
AO,CS
~TAW~T::~ TwI
Invalid
WR
TOW
DBO'DB7
Read timing
AO,CS
DBO'DB7
430
Invalid
~WDr--
Valid
K
Invalid
SAB 8275
Clock timing
((lK
431
SAB8276
Small· System CRT Controller
•
•
•
•
Programmable screen and character format
6 independent visual at!ributes
Cursor control (4 types)
SAB 8051, SAB 8085, SAB 8086 and SAB 8088
compatible
Dual row buffers
Programmable DMA burst mode
Single +5V supply
High perfor~ance MYMOS technology
Fully compatible with industry standard 8276
Pin Names
Pin configuration
LC3[~PV((
LC2 [2
•
•
•
•
•
LCO-LC3
Line Count
BRDY
Buffer Ready
39pNC
Buffer Select
lCl[ 3
3apNC
BS
Leo [ 4
37PLTEN
HRTC
Horizontal Retrace
5
36pRVV
VRTC
Vertical Retrace
65[6
3SpVSP
BROY
L
RD
Read Input
Write Input
HRTC [
7
31.pGPAl
VRH [
8
33PGPAO
WR
32PHLU"i
DBO-DB7
Bidirectional Three-State Data Bus Lines
LTEN
Lig ht Enable
RITC
9
"'WR[ 10
NC[ 11
OBO [
SAB
8276
31P
INT
30 :=JCClK
12
29::JC(6
DBl [13
2S::JC(S
DB2 [
14
21 ~[[4
DB3 [
15
26
=:J [(3
OBI. [
16
25
::J C[2
OB5 [
17
21.::JcC1
RVV
Reverse Video
VSP
Video Suppression
GPAO, GPA1
General Purpose Attribute Codes
HLGT
Highlight
INT
Interrupt Output
DB6 [18
B
::Je(o
CCLK
Cha racter Clock
DB7 [
19
22
Character Codes
20
21
:J (5
::J UP
CCO-CC6
GNO [
CS
Chip Select
C/P
Port Address
The SAB 8276 Small System CRT Controller is a
single chip device to interface CRT raster scan
displays. It is manufactur!'d in Siemens advanced
MYMOS technology. Its primary function is to
refresh the display by buffering the information
from main memory and keeping track of the
display position of the screen. The flexibility
designed into the SAB 8276 will allow simple
interface to almost any raster scan CRT display
with a minimum· of external hardware and software
overhead.
AG 2/85
433
I
SAB 8276
Pin Definitions and Functions
Input (I)
Output (0)
Function
Symbol
Number
LC3
LC2
LC1
LCO
1
2
3
4
0
BRDY
5
I
BUFFER READY: Output signal indicating that a row buffer
is ready for loading of character data.
BS
6
0
BUFFER SELECT: Input signal enabling WR for character
data into the row buffers.
HRTC
7
0
HORIZONTAL RETRACE: Output signal which is active during
the programmed horizontal retrace interval. During this period
the VSP output is high and the LTEN output is low.
VRTC
8
0
VERTICAL RETRACE: Output signal which is active during the
programmed vertical retrace interval. During this period the
VSP output is high and the LTEN output is low.
LINE COUNT: Output from the line counter which is used to
address the character generator for the line positions on the
screen.
RD
9
I
READ INPUT: A control signal to read registers.
WR
10
I
WRITE INPUT: A control signal to write commands into the
control registers or write data into the row buffers during a
DMAcycle.
NC
11
DBa
DB1
DB2
DB3
DB4
DB5
DB6
DB7
12
13
14
15
16
17
18
19
NC
38/39
LTEN
37
0
LIGHT ENABLE: Output signal used to enable the video signal
to the CRT. This output is active at the programmed underline
cursor position. and at positions specified by attribute codes.
RVV
36
0
REVERSE VIDEO: Output signal used to indicate the CRT
circuitry to reverse the video signal. This output is active at the
cursor position if a reverse video block cursor is programmed
or at the positions specified by the field attribute codes.
434
No Connection
1/0
BIDIRECTIONAL THREE-STATE DATA BUS LINES:
The outputs are enable during a read of the C or P ports.
No Connection
SAB 8276
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
VSP
35
0
VIDEO SUPPRESSION: Output signal used to blank the video
signal to the CRT, This output is active:
- During the horizontal and vertical retrace intervals,
- at the top and bottom lines of rows if underline is
programmed to be number 8 or greater.
- when an end of row or end of screen code is detected,
- when a DMA underrun occurs,
- at regular intervals (1/16 frames frequency for cursor,
1132 frame frequency for character and field attributes)to create blinking displays as specified by cursor or
field attribute programming,
GPA1
GPAO
34
33
0
GENERAL-PURPOSE ATIRIBUTE CODES: Outputs which are
enable by the general purpose field attribute codes,
HLGT
32
0
HIGHLIGHT: Output signal used to intensify the display at
particular positions on the screen as specified by the character
attribute codes or field attribute codes,
INT
31
0
INTERRUPT OUTPUT
CCLK
30
I
CHARACTER CLOCK (from dot/timing logic),
CC6
CC5
CC4
CC3
CC2
CCl
CCO
29
28
27
26
25
24
23
0
CHARACTER CODES: Output from the row buffers used for
character selection in the character generator,
Function
CS
22
I
CHIP SELECT: The read and write are enabled by CS,
Clp
21
I
PORT ADDRESS: A high input on C/F' selects "c" port or
command registers and a low input selects the "P" port or
parameter registers.
VCC
40
-
+5V Power supply,
20
-
Ground (OV)
GND
435
SAB 8276
SAB 8276 Block diagram showing counter and register functions
Character
Counter
DBO-7
Data
Bus
Buffer
CClK
CCO-6
ORQ
OACK
IRQ
line
Counter
WR
AD
(S
436
lCO- 3
Row
(Dunter
Raster Timing
and
Video Control
HRT(
VRTC
HlGT
RVV
lTEN
VSP
GPAO-1
SAB 8276
Functional Description
BS (BUFFER SELECT)
Data bus buffer
A "low" on this input enables WR of character
data to the SAB 8276 row buffers.
This three-state, bidirectional, 8-bit buffer is used to
interface the SAB 8276 to the system data bus.
This functional block accepts inputs from the system
control bus and generates control signals for overall
device operation. It contains the command,
parameter, and status registers that store various
control formats for the device functional definition.
C/P
Operation
0
Read
Reserved
0
Write
Parameter
1
Read
STATUS
1
Register
Write
COMMAND
C/P
RD WR CS
BS
0
0
1
1
0
Reserved
INT (Interrupt Output)
A "high" on this output informs the CPU that the
SAB 8276 desires interrupt service.
Character counter
The character counter is a programmable counter
that is used to determine the number of characters
to be displayed per row and the length of the
horizontal retrace interval. It is driven by the CCLK
(character clock) input, which should be a derivative
of the external dot clock.
Line counter
The line counter is a programmable counter that is
used to determine the number of horizontal lines
(sweeps) per character row. Its outputs are used to
address the external character generator ROM.
Row counter
0
1
0
0
1
1
0
1
0
1
Read 8276 Status
,1
1
0
0
1
Write 8276 Command
The row counter is a programmable counter that is
used to determine the number of character rows to
be displayed per frame and length of the vertical
retrace interval.
X
1
0
1
0
Write 8276 Row Buffer
Raster timing and video controls
X
1
1
X
X
High Impedance
X
X
X
1
1
High Impedance
The raster timing circuitry controls the timing of the
HRTC (Horizontal Retrace) and VRTC (Vertical
Retrace) outputs. The video control circuitry
controls the generation of HGLT (highlight),
RVV (reverse video), LTEN (Light enable),
VSP (video suppress). and GPAO-1 (general
purpose attribute) outputs.
Write 8276 Parameter
RD(Read)
A "low" on this input informs the SAB 8276 that the
CPU is reading data or status information from the
SAB8276.
WR(Write)
A "low" on this input informs the SAB 8276 that the
CPU is writing data or control words to the
SAB8276.
Row buffers
The row buffers are two 80 character buffers. They
are filled from the microcomputer system memory
with the character codes to be displayed. While
one row buffer is displaying a row of characters, the
other is being filled with the next row of characters.
CS (Chip select)
A "low" on this input selects the SAB 8276. No
reading or writing will occur unless the device is
selected. When CS is high, the data bus in the float
state and RD and WR will have no effect on the chip.
BRDY (BUFFER READY)
A "high" on this output indicates that the SAB 8276
is ready to receive character data.
Buffer input/output controllers
The buffer input/output controllers decode the
characters being placed in the row buffers. If the
character is a character attribute, field attribute or
special code, these controllers control the
appropriate action (Examples: A "HIGHLIGHT"
attribute will cause the Buffer Output Controller to
activate the HGLT output).
437
SAB8276
System Operation
The SAB 8276 is programmable to a large number of
different display formats. It provides raster timing,
display row buffering, visual attribute decoding,
cursor timing, and light pen detection.
It is designed to interface with standard character
generator for dot matrix decoding.
Dot level must be provided by external
circuitry.
SAB 8276 Block diagram showing systems operation
BRDY
INT
SA8
8088
MicroProcessor
LCQ-LC3
~
I
SA8
6205
Chora,ter
Generator
~IROMorRAMJ
iiS
r-
----"_---,/
I CCNC6",
SAB
8276
CRT
CeLK
Controller
Interface
T~
VRTC
- SYstem
Counterl
Timer
Video
Video Controls
Decoder
SAB
6253-5
SAB
8213'
Dot
Timing
logic
and
I--
1
n n
Disp\ay
Memory
I
Serial
Communications
Channet
VSYNC
Bus - - -
ProgramJ
SAB
B251A
USART
HSYNC
Matching
Circuit
SAB
8255A-5
Keyboard
r---
Controller
tJ
Keyboard
II
Status
I
Raster timing
The character counter is driven by the character
clock input (CCLK).lt counts out the characters being
displayed (programmable from 1 to 80). It then
cause the line counter to increment, and it starts
counting out the horizontal retrace (programmable
from 2 to 32). This is constantly repeated.
The line counter is driven by the character counter.
It is used to generate the line address outputs
(LCO-3) for the character generator. After it counts
all ofthe lines in a character row (programmable
from 1 to 16), it increments the row counter, and
starts over again. (See Character Format Section for
detailed description of Line Counter functions.)
438
The row counter is an internal counter driven by the
line counter. It controls the functions ofthe row
buffers and counts the number of character rows
displayed.
After the row counter counts all of the rows in a
frame (programmable from 1 to 64), it starts
counting out the vertical retrace interval
(programmable from 1 to 4).
The video suppression output (VSP) is active during
horizontal and vertical retrace intervals.
Dot level timing circuitry must synchronize these
outputs with the video signal to the CRT display.
SAB 8276
Interrupt timing
The SAB 8276 can be programmed to generate an
interrupt request at the end of each frame.
If the SAB 8276 interrupt enable flag is set, an
interrupt request will occur at the beginning of the
last display row.
Beginning of interrupt request
Internal
Row
Counter
VRTC
INT
IRQ will go inactive after the status register is read.
End of interrupt
A reset command will also cause IRQ to go inactive,
but this is not recommended during normal service.
underline position, and blanking oftop and bottom
lines are programmable (see programming section).
Note: Upon power-up, the SAB 8276 interrupt
Enable Flag may be set. As a result, the user's cold
start routine should write a reset command to the
SAB 8276 before system interrupts are enabled.
The SAB 8276 provides special control codes which
can be used to minimize overhead. It also provides
visual attribute codes to cause special action
on the screen without the use of the character
generator (see visual attribute section).
Generalsystems operational description
Display characters are retrieved from memory and
displayed on a row by row basis. The SAB 8276 has
two row buffers. While one row buffer is being used
for display, the other is being filled with ihe next row
of characters to be displayed. The number of display
characters per row and the number of character
rows per frame are software programmable,
providing easy interface to most CRT displays
(see programming section).
The SAB 8276 uses BRDY to request data to fill
the row buffer that is not being used for display.
The SAB 8276 displays character rows one line at
a time. The number of lines per character row, the
The SAB 8276 also controls raster timing. This is
done by generating horizontal retrace (HRTC) and
vertical retrace (VRTC) signals. The timing of these
signals is programmable.
The SAB 8276 can generate a cursor. Cursor location
and format are programmable (see programming
section).
Display row buffering
Before the start of a frame, the SAB 8276 uses
BRDY and BS to fill one row buffer with characters.
439
SAB 8276
When the first horizontal sweep is started, character
codes are output to the character generator from the
row buffer just filled. Simultaneously, the other
row buffer is filled with the next row of characters.
Mode 0 is useful for character generators that leave
address zero blank and start at address 1, Mode 1 is
useful for character generators which start at
address zero.
After all the lines of the character row are scanned,
the roles of the two row buffers are reversed and the
same procedure is followed for the next row.
Underline placement is also programmable (from
line number 0 to 15). This is independent of the line
counter mode.
This is repeated until all of the character rows are
displayed.
If the line number of the underline is greater than 7
(line number MSB = 1). then the top and bottom
lines will be blanked.
Screen format
The SAB 8276 can be programmed to generate
from 1 to 80 characters per row, and from 1 to 64
rows per frame.
The SAB 8276 can also be programmed to blank
alternate rows. In this mode, the first row is
displayed, the second blanked, the third displayed,
etc. Display data is not requested for the blanked
rows.
Row format
The SAB 8276 is designed to hold the line count
stable while outputting the appropriate character
codes during each horizontal sweep. The line count
is incremented during horizontal retrace and the
whole row of character co(jes are output again
during the next sweep. This is continued until the
whole character row is displayed.
The number of lines (horizontal sweeps) per
character row is programmable from 1 to 16.
The output of the line counter can be programmed
to be in one of two modes.
In mode 0, the output of the line counter is the same
as the line number.
In mode 1, the line counter is offset by one from the
line number.
.
Note: In mode 1, while the first line (line number 0) is
being displayed, the last count is output by line
counter.
440
If the line number of the underline is less than or
equal to 7 (line number MSB = 0), then the top and
bottom lines will not be blanked.
If the line number underline is greater than the
maximum number of lines, the underline will not
appear.
Blanking is accomplished by the VSP (Video
Suppression) signal. Underline is accomplished by
the LTEN (light enable) signal.
Dotformat
Dot width and character width are dependent upon
the external timing and control circuitry.
Dot level timing circuitry should be designed to
accept the parallel output of the character generator
and shift it out serially at the rate required by the
CRT display.
Dot width is a function of dot clock frequency.
Character width is a function of the character
generator width.
Horizontal character spacing is a function olthe shift
register length.
Note: Video control and timing signals must be
synchronized with the video signal due to the
character generator access delay.
SAB 8276
Visual Attributes and Special Codes
The characters processed by the SAB 8276 are 8-bit
quantities. The character code outputs provide the
character generator with 7 bits of address. The most
significant bit is the extra bit and it is used to determine if it is a normal display character (MSB = 0)'
or if it is a Visual Attribute or Special Code (MSB = 1).
Special codes
Four special codes are available to help reduce
memory, software or DMA overhead.
Special control character
MSB
LSB
111100SS
~
S
S
o a
o 1
o
SPECIAL CONTROL CODE
Function
End
End
End
End
of Row
of Row-stop Buffer Loading
of Screen
of Screen-stop Buffer Loading
The end-of-row code (00) activates VSP and holds it
to the end of the line.
The end-of-row Buffer Loading code (BRDY) causes
the Buffer Loading control logic to stop Buffer
Loading for the rest of the row when it is written into
the row buffer. It affects the display in the same way
as the end-of-row code (00).
The end-of-screen code (10) activates VSP and
holds it to the end of the frame.
The end-of-screen-stop Buffer Loading code (BRDY)
causes the Buffer Loading control logic to stop
Buffer Loading for the rest of the frame when it
is written into the row buffer. It affects the display
in the same way as the end-of-screen code (10).
If the stop Buffer Loading feature is not used, all
characters after an end-of-row character are
ignored, except for the end-of-screen character,
which operates normally. All characters after an
end-of-screen character are ignored.
Field attributes
The field attributes are control codes which affect
the visual characteristics for a field of characters,
starting at the character following the code up to,
and including, the character which precedes thenext
field attribute code, or up to the end oftheframe. The
field attributes are reset during the vertical retrace
interval.
There are six field attributes:
1. Blink - Characters following the code are caused
to blink by activating the Video Suppression
Output (VSP). The blink frequency isequal to the
screen refresh frequency divided by 32.
2. Highlight- Characters following the code are
caused to be highlighted by activating the
Highlight Output (HGLT).
3. Reverse Video - Characters following the. code
are caused to appear with reverse video by
activating the Reverse Video Output (RVV).
4. Underline - Characters following the code are
caused to be underlined by activating the Light
Enable Output (LTEN).
5, 6. General Purpose - There are two additional
SAB 8276 outputs which act as general purpose,
independently programmable field attributes.
GPAO-1 are active high outputs.
Field attribute code
MSB
LSB
10URGGBH
II TL
I
L-
H = 1 for highlighting
B = 1 for blinking
R = 1 for reverse video
HIGHLIGHT
BLINK
GENERAL PURPOSE
REVERSE VIDEO
UNDERLINE
U = 1 for underline
GG = GPA1, GPAO
* More than one attribute can be enabled at the same time.
If the blinking and reverse video attributes are enabled
simultaneously, only the reversed characters will blink.
Note: If a stop Buffer Loading character is not the
last character in a burst or rOiN, Buffer Loading is
not stopped until after the next character is read.
In the situation, a dummy character must be placed
in memory after the stop Buffer Loading character.
441
SAB 8276
Cursor timing
The cursor location is determined by a cursor row
register and a character position register which are
located by command to the controller. The cursor
can be programmed to appear on the display as:
1. a blinking underline
2. a blinking reverse video block
3. a non-blinking underline
4. a non-blinking reverse video block
Instruction Set
The cursor blinking frequency is equal to the screen
refresh frequency divided by 16.
The SAB 8276 instruction set consists of
7 commands.
If a non-blinking reverse video cursor appears in a
non-blinking reverse video field, the cursor will
appear as a normal video block.
If a non-blinking underline cursor appears in a nonblinking underline field, the cursorwill not be visible.
Device programming
The SAB 8276 has two programming registers, the
command register and the parameter register.
It also has a status register. The command
register can only be written into and the Status
registers can only be read from. They are addressed
as follows:
Ao
operation
register
a
a
Read
Reserved
Write
Parameter
1
Read
Status
1
Write
Command
The SAB 8276 expects to receive a command and a
sequence of a to 4 parameters, depending on the
command. If the proper number of parameter bytes
are not received before another command is given,
a status flag is set, indicating an improper
command.
Command
No. of parameter bytes
4
Reset
Start Display
Stop Display
Load Cursor
Enable Interrupt
Disable Interrupt
Preset Counters
a
a
2
a
a
a
In addition, the status of the SAB 8276 can be read
by the CPU at any time.
1 Reset command
Data bus
Command
Operation
C/f>
Description
MSB
Write
1
Reset
command
a a a a a a a a
Write
a
Screen comp
Byte 1
S
H
H
H
H
H
H
H
Write
0
Screen comp
Byte 2
V
V
R
R
R
R
R
R
Write
0
Screen comp
Byte 3
U
U
U
U
L
L
L
L
Write
0
Screen comp
Byte 4
M
1
C
C
Z
Z
Z
Z
Parameters
LSB
Action - After the reset command is written, BRDY goes inactive, SAB 8276 interrupts are disabled, and
the VSP output is used to blank the screen. HRTC and VRTC continue to run. HRTC and VRTC timing are
random on power-up. As parameters are written, the screen composition is defined.
442
SAB 8276
Parameter - S
Spaced rows
S
Functions
o
Normal rows
Spaced rows
Parameter - RRRRRR
Parameter-HHHHHHH
Horizontal characters/row
H H H H H H H
No. of characters per row
0
1
0
0
0
0
0
0
o
o
0
0
0
0
0
0
0
0
0
0
0
1
1
1
o
0
0
0
1
2
0
3
80
0
Undefined
R
R
0
0
0
0
0
0
Vertical rows/frame
R
R
R
R
0
0
0
0
0
0
0
0
0
No. of rows/frame
1
1
2
0
3
64
Parameter- UUUU
Underline placement
U
U
U
U
Line number of underline
0
0
0
0
0
0
0
0
0
2
3
0
Undefined
Parameter- VV
16
Vertical retrace row count
V
V
No. of row counts per VRTC
0
0
1
0
1
0
2
1
Note: uuuu MSB determines blanking oftop and
bottom lines (1 = blanked, 0 = not blanked).
3
4
Parameter- LLLL Number of lines per character row
Parameter - ZZZZ
L L L L
z z z z
o
0
0
No. of lines/row
0
000
o
0
2
3
o
000
000
o 0
Horizontal retrace count
No. of character counts per HRTC
0
2
4
6
o
32
16
Parameter- M
Line counter mode
Parameter - CC
Cursor format
M
Line counter mode
c
C
Cursor format
o
Mode 0 (non-offset)
. Mode 1 (offset by 1 count)
0
0
1
1
0
1
Blinking reverse video block
Blinking underline
Nonblinking reverse video block
Nonblinking underline
1
0
443
SAB 8276
2 Start display command
Data bus
Command
Operation
CIl'
Description
MSB
Write
1
Start display
a a
LSB
1
a a a a a
No parameters
Action - SAB 8276 interrupts are enabled, DMA requests begin, video is enabled, interrupt enable and
video enable status flags are set.
3 Stop display command
Data bus
Operation
Command
Write
CIl'
Description
MSB
1
Stop display
a
1
LSB
a a a a a a
No parameters
Action - Disables video, interrupts remain enabled. HRTC and VRTC continue to run, video enable status
flag is reset, and the "Start display" command must be given to re-enable the display.
4 Load cursor position
Data bus
Command
Operation
Cl'
Description
MSB
Write
1
Load cursor
1
Write
a
Char. number
Write
a
Row number
(Char. position
in row)
(Row number)
Parameters
LSB
a a a a a a a
Action - The SAB 8276 is conditioned to place, the next two parameter bytes into the cursor position
registers. Status flags not affected.
5 Enable interrupt command
Data bus
Command
Operation
CIl'
Description
MSB
Write
1
Enable
interrupt
1
No parameters
Action - The interrupt enable status flag is set and interrupts are enabled.
444
a
LSB
1
a a a
0
0
SAB 8276
6 Disable interrupt command
Data bus
Command
Operation
C/P
Description
MSB
Write
1
Disable
interrupt
1
1
LSB
0
0
0
0
0
0
0
0
No parameters
Action -Interrupts are disabled and the interrupt enable status flag is reset.
7 Preset counters command
Data bus
Command
Operation
C/P
Description
MSB
Write
1
Preset
counters
1
1
LSB
1
0
0
0
No parameters
Action - The internal timing counters are preset, corresponding to a screen display position at the top
left corner. Two character clocks are required for this operation. The counters will remain in this state until
any other command is given.
This command is useful for system debug and synchronization of clustered CRT displays on a single CPU.
After this command, two additional clock cycles are required before the first character of the first row is
put out.
Status flags
Data bus
Command
Operation
C/P
Description
MSB
Read
1
Status
word
0 IE IR X IC VE BU X
LSB
IE - (Interrupt Enable) Set or reset by command.
It enables vertical retrace interrupt. It is automatically set by a "Start Display" command
reset with the "Reset" command.
VE - (Video Enable) This flag indicates that video
operation of the CRT is enabled. This flag is
set on a "Start Display" command, and reset
on a "Stop Display" or "Reset" command.
IR - (Interrupt Request) This flag is set at the
beginning of display of the last row of the
frame if the interrupt enable flag is set. It is
reset after a status read operation.
BU - (Buffer Underrun) This flag is set whenever a
Row Buffer is not filled with character data in
time for buffer swap required by the display.
Upon activation ofthis bit, buffer loading
ceases, and the screen is blanked until after
the vertical retrace interval.
IC - (Improper Command) This flag is set when a
command parameter string is too long or too
short. The flag is automatically reset after a
status read.
445
SAB 8276
Absolute Maximum Ratings
1)
Temperature under bias
Storage temperature
All output ans supply and supply voltages
All input voltages
Power dissipation
o to +70 °e
- 65 to + 150°C
-0.5 to
+7 V
-0.5 to +5.5 V
1.0W
D.C. Characteristics
(TA = 0 to 70°C, vee = 5V ±5%1
Symbol Parameter
Limit values
Min.
Max.
VIL
Input low voltage
-0.5
0.8
VIH
Input high voltage
2.0
Vee+0.5V
VOL
Output low voltage
-
0.45
VOH
Output high voltage
2.4
-
ilL
Input load current
10FL
Output float leakage
ICC
vee supply current
±10
Unit
Test condition
-
V
10L = 2.2 mA
IOH = -400 flA
flA
VIN = vee to OV
VOUT = vee to 0.45 V
-
160
mA
-
Unit
Test condition
Capacitance
(TA = 25°C, vee = GND = OVI
Symbol Parameter
elN
Input capacitance
CliO
1/0 capacitance
Limit values
Min.
-
Max.
10
20
pF
fc
= 1 MHz
Unmeasured pins
returned to GND
11 Stresses above those listed under "absolute maximum ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
446
SAB 8276
A.C. Characteristics (SAB 8276)
ITA = Oto 70°C, VCC = 5.0V
± 5%, GND
= OV)
Clock timing
Symbol Parameter
Limit values
Min.
TCLK
Clock period
480
TKH
Clock high
240
TKL
Clock low
160
TKR
Clock rise
TKF
Clock fall
5
Max.
Units
Test condition
ns
-
Unit
Test condition
30
Bus parameters
Read cycle
Symbol Parameter
TAR
Address stable before READ
TRA
Address hold time for READ
TRR
READ pulse width
TRD
Data delay from READ
TDF
READ to data floating
Limit values
Min.
Max.
0
-
250
-
-
ns
200
CL=150pF
100
Write cycle
Symbol Parameter
Limit values
Min.
TAW
Address sta ble before WRITE
TWA
Address hold time for WRITE
TWW
WRITE pulse width
250
TDW
Data setting time for WRITE
150
TWD
Data hold time for WRITE
0
Max.
Unit
Test condition
ns
-
0
-
447
SAB 8276
Other timings
Symbol Parameter
Limit values
Min.
Max.
TCC
Character code output delay
150
THR
Horizontal retrace output delay
200
TLC
Line count output delay
400
TAT
Control-attribute output delay
TVR
Vertical retrace output delay
TRI
INT1from RDt
TWO
BRDYt from WRt
TRO
BRDY1from WRl
TLR
BSl to WRl
TRL
WRt to BSt
448
-
Unit
Test condition
CL = 50 pF
275
ns
250
200
0
-
-
SAB 8276
A.C. Characteristics (SAB 8276-2)
ITA = OCto 70'C, VCC = 5.0V
± 5%, GND = OV)
Clock timing
Symbol Parameter
TCLK
Clock period
TKH
Clock high
TKL
Clock low
TKR
Clock rise
TKF
Clock fall
Limit values
Min.
Max.
Unit
Test condition
ns
-
Unit
Test condition
320
120
5
-
30
Bus parameters
Read cycle
Symbol Parameter
TAR
Address stable before READ
TRA
Address hold time for READ
TRR
READ pulse width
TRD
Data delay from READ
TDF
READ to data floating
Limit values
Min.
Max.
0
-
-
250
-
ns
200
CL=150pF
100
Write cycle
Symbol Parameter
TAW
Address stable before WRITE
TWA
Address hold time for WRITE
TWW
WRITE pulse width
Limit values
Min.
Max.
Unit
Test condition
ns
-
0
250
TDW
Data setting time for WRITE
150
TWD
Data hold time for WRITE
0
-
449
SAB 8276
Other timings
Symbol Parameter
TCC
Character code output delay
THR
Horizontal retrace output delay
TLC
Line count output delay
TAT
Control-attribute output delay
TVR
Vertical retrace output delay
TRI
INTl from RDt
TWO
BRDVt from WRj
TRO
BRDVl from WRl
TLR
BSt to WRl
TRL
WRt to BSt
450
Limit values
Min.
Max.
Unit
Test condition
150
CL = 50 pF
-
250
ns
200
0
-
-
SAB 8276
A.C. Testing input/output
24~20> Test Points <::.2 0 > < =
0.45
0.8
0.8
AC Testing: Inputs are driven at 2,4 V for a logic "1" and 0.45 V for a logic "0".
Timing measurements are made at 2.0V for a logic "1" and O.SV for a logic "0".
A.C. Testing load circuit
DevIce
Under
Test
CL Includes Jig CapaCitance
451
SAB8276
Waveforms
Typical dot level timing
EXT DOT ClK
CClK*
CCO-CC6
First Character Code
ROM Access---l
Character
Generator
Output
L
l'--_-----'
Second Character Code
,----------,.X
w!
_______--'1:\
First Character
Second Character
Attributes
& Controls
Video
(from Shift
Registerl
Altri butes
& Controls
(from Synchronizer)
~-----------v-----------'~
First Character
Attributes & Controls
for First Character
Second Character
Attributes & Controls
for Second ChClrClcter
* CClK is a Multiple of the Dot Clock and an Input to the SAB 8276
452
SAB 8276
Line timing
CClK
CC 0 -((6
HRTC
lC O-l( 3
Video
Controls and
Attributes *
I
I
I
.J
f/.
Present Line Count
-~~--T-A-T------------~~'\~------------------'~~~-------
X
*VSP lTEN HGlT RVV GPAO-GPA1
453
SAB 8276
Row timing
CClK
HRTC
lCQ-lC3
r - - - - - - Programmable
Internal
Raw
Counter
last Row
from 1 to 16
Present Row
c,:
Frame timing
CClK
Internal
Row
Counter
---+-- Programmable
from
1 to 4 Rows
VRTC
454
SAB 8276
Interrupt timing
\
CClK
C/P
CCO-C(6
last Retrace
Character
J
\~-
First Retrace
Character
/
lCO-lC3
First line Count
~~
HRTC
Internal - - - - - - - 1 - - - - - Row
last Display Row
Counter -----~--t-----INT
L
INT
~Tr-
Timing for Buffer Loading
CClK
\'----..-.IA
1TR:tI
455
SAB8276
Write timing
~RC/P~ ~
TAW
ft ::~.-T_W_A_~
_ _ _I_nV_Q_lid_ _
::tl
000-007
Read timing
456
TWO
f--
~Wf-- I
---I-nV-Q-lid--JL~_ _ _ln_VQ_I_id_ _
SAB 8276
Clock timing
TCLK
f--TKH-
----,
((LK
TI5.L
f---TKL-
f---
-
f--TKR
I
457
SAB 8282AI SAB 8283A
Octal Latch
• Fully compatible with SAB 8282/SAB 8283
• 40% Less Power Supply Current
than Standard SAB 8282/SAB 8283
• Fully Parallel 8-Bit Data
Register and Buffer
• No Output Low Noise when Entering or
Leaving High Impedance State
• Add ress Latch for
SAB 80286, SAB 80186, SAB 8086, SAB 8085,
SAB 8048 and SAB 8051 Families
• High Output Drive Capability for
Driving System Data Bus
• 3-State Outputs
• Transparent during Active Strobe
• 20-Pin Package
Pin Names
Pin Configuration
Vee
01 0
Oil
Vee
01 0 -01,
Data In
00,
00,
DO o-D0 7
Data Out
00 2
00 3
OE
Output Enable
STB
Strobe
Vee
Power Supply (+5V)
GND
Ground (OV)
Oil
OGl 0
01,
01 1
DO,
01 1
01 3
001
01 3
00 3
01 4
01 5
004
01 5
01 6
00 5
01 6
005
017
006
01)
506
50)
SAB
8282A
01 4
OE
GNO
10
~O)
ill
ST8
GNO
SAB
8283A
DC\
10
The SAB 8282A and SAB 8283A are 8-bit
bipolar latches with 3-state output buffers.
They can be used to implement latches, buffers,
or multiplexers. The SAB 8283A inverts the input
data at its outputs while the SAB 8282A does not.
11
ST8
Thus, all of the principal peripheral and
input/output functions of a microcomputer system
can be implemented with these devices.
This device is fabricated in a fast bipolar ASBC
(Advanced Standard Buried Collector) process
of Siemens.
AG 1/85
459
I
SAB 8282A / SAB 8283A
Logic Diagrams
SAB 8282A
SAB 8283A
r--------,
r--------,
I
I
I
I
0
Q
I
I
I
000
01 0
01,
DO,
01,
01 2
D02
01 2
01 3
003
01 3
01,
DO,
01,
015
DOs
015
01 6
006
01 6
01 7
00 7
01 0
I
I
I
I
I
0
Q
5150
eLK
-------
DO,
002
-------
-------
003
00,
005
-------
006
007
-------
STS
Pin Definitions and Functions
Symbol
Number
Input II)
Output (0)
STB
11
I
STROBE - STB is an input control pulse used to
strobe data at the data input pins lAo-A,) into
the data latches. This signal is active HIGH to admit
input data. The data is latched at the HIGH to LOW
transition of STB.
OE
9
I
OUTPUT ENABLE - OE is an input control signal which
when active LOW enables the contents of the data
latches onto the data output pin 100 0 -00, or 00 0 -00,).
OE being inactive HIGH forces the output buffers to their
high impedance state.
DIo-Dl,
1-8
I
DATA INPUT PINS - Data presented at these pins
satisfying setup time requirements when STB is strobed
and latched into the data input latches.
12-19
0
DATA OUTPUT PINS - When OE is true, the data in the
data latches is presented as inverted ISAB 8283A) or
non-inverted ISAB 8282A) data onto the data output pins.
Vee
20
-
Power Supply 1+5V)
GNO
10
-
Ground 10V)
00 0-00,
ISAB8282A)
00,,00,
Function
ISAB8283A)
460
SAB 8282A / SAB 8283A
Functional Description
The SAB 8282A and SAB 8283A octal latches are
8-bit latches with 3-state output buffers.
Data having satisfied the setup time requirements
is latched into the data latches by strobing the STB
line HIGH to LOW. Holding the STB line in its
active HIGH state makes the latches appear
transparent.
Data is presented to the data output pins by
activating the OE input line. When OE is inactive
HIGH the output buffers are in their high impedance
state. Enabling or disabling the output buffers will
not cause negative-going transients to appear on
the data output bus.
Absolute Maximum Ratings 1)
o to + 70'C
- 65 to + 150'C
-0.5to +7V
-1.0 to +5.5V
1W
Temperature Under Bias
Storage Temperature
All Output and Supply Voltages
All Input Voltages
Power Dissipation
D. C. Characteristics
TA = Oto 70'C; Vee = +5V ±10%
Limit Values
Symbol
Parameter
Units
Test Conditions
Ve
Input Clamp Voltage
-1
V
Ie
Icc
Power Supply Current
SAB8282A
SAB 8283A
-
100
90
mA
all outputs open
1,
Forward Input Current
-
-0.2
1R
Reverse Input Current
50
VOL
Output LOW Voltage
0.45
VOH
Output HIGH Voltage
Min.
Max.
= -5 mA
VF = 0.45V
VR = 5.25V
flA
10L
= 32 mA
-
10H
= -5mA
±50
flA
VOFF = 0.45 to 5.25V
V
Vee
pF
F = 1 MHz
VBIAS = 2.5V, Vee
TA = 25'C
V
2.4
10FF
Output Off Current
VIL
Input LOW Voltage
V,H
Input HIGH Voltage
2.0
-
G'N
Input Capacitance
-
12
1) Stresses above those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device.
Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
-
0.8
2) Output Loading:
= 5.0V 2}
IOL
= 32 mA;
GL
=
10H
= 5V
= -5 mA;
300 pF
461
SAB 8282A / SAB 8283A
A.C. Characteristics
TA = Oto +70°C; Vee = +5V ±
Loading
Outputs:
IOL =
32 mA;
IOH =
Symbol
Parameter
[Ivav
{SHDV
tEHD2
10%
-5 mA; CL = 300 pF
Limit Values
Min.
Max.
Input to Output Delay
-Inverting
-Non-Inverting
5
5
22
30
STS to Output Delay
-Inverting
-Non-Inverting
10
10
40
45
Output Disable Time
5
18
30
tElDV
Output Enable Time
10
llVSL
Input to STS Setup Time
0
tSLIX
Inputto STS Hold Time
25
tSHSL
STS HIGH Time
15
Input. Output Rise Time
Input. Output Fall Time
-
'IUH, fOlOH
'IHILI tOHOL
Units
Test Conditions
21
ns
20
From 0.8 to 2.0 V
12
From 2.0 to 0.8 V
A.C. Testing Input, Output Waveform
Input/Output
A.C. Testing: Inputs are driven at 2.4 V for a logic" 1" and 0.45 V for a logic "0". Timing measurements
are made at 1.5Vfor both a logic "1" and "0".
Waveforms
All timing measurements are made at 1.5 V unless otherwise noted.
Timing
Inputs
STS
OE
tEH Z
,..---------...1 VOH -Q,1V
Outputs
-E=tELOV
-------t---~'~:__---------J1 VOL +Q.1V
11 SAS 8283A Only- Output may be momentarily
invalid following the high going STS transition.
462
.
21 See waveforms and test load circuit.
SAB 8282A / SAB 8283A
Output Test Load Circuits
18011
3311
Output
Output
Q------<
I
2,14V
1.5V
1.5V
)52,7\1
Output
Q------<
I
300 PF
0--
!300 PF
300 PF
switching
3 -state to VOH
3-state to VOL
Output Delay vs, Capacitance
ns
ns
50
50
SAB
8282A
SAB
8283A
40
40
i;'
OJ
o
30
10
o
--------
~ ----~ofS\
20
,~e-
--o
200
i;'
OJ
Cl
30
20
10
400
600
Load-
800
1000 pF
-- --
------~
\~
~otS
~
/
a
o
200
400
600
800
1000 pF
Load-
463
,o/"e~.'In.. •
'#1111.
SAB 8284B, SAB 8284B-1 qly
Clock Generator and Driver
for SAB 8086 Family Processors
• Provides Synchronization for Synchronous
and Asynchronous READY Signals
• Fully compatible with
SAB 8284A, SAB 8284A-1
• 30% less Power Supply Current than Standard
SAB 8284A, SAB 8284A-1
• 18-Pin Package
• Single +5V Power Supply
• Generates System Reset Output from
Schmitt Trigger Input
• Generates the System clock for SAB 8086 and
SAB 8088. Processors:
up to 8 MHz with SAB 82848
up to 10 MHz with SA8 82848-1
• Capable of Clock Synchronization with
Other SAB 8284Bs
• Uses a Crystal or a TTL Signal for
Frequency Source up to 30 MHz
Pin Names
Figure 1
Pin Configuration
X,
x2
Connections for crystal
Fie
Clock source select
I
EFI
External clock input
CSYNC
Clock synchronization input
17bx,
ASYNC
Ready synchronization select
AEN, [ 3
16bxz
RDY,
RDY,
Ready signal
ROY, [ 4
15bASYNC
AEN,
AEN,
Address enabled qualifiers for RDY,.,
RES
Reset input
CYSNC [ 1
18
PCLK [ 2
READY [ 5
SA8
82848
b Vcc
14bEFI
RDYZ [ 6
13bFiC
RESET
Synchronized reset output
AEN Z[ 7
12bosc
OSC
Oscillator output
ClK [ B
11 b RES
ClK
MOS Clock for the processor
GND[ 9
10 bRESET
PClK
TTL Clock for peripherals
SAB 8284B is a bipolar clock generator/driver
designed to provide clock signals for SAB 8086
and SAB 8088 processors and peripherals. It also
contains READY logic for operation with two bus
systems and provides the processors required
READY
Synchronized ready output
Vee
Power Supply (+5V)
GND
Ground (OV)
READY synchronization and timing. Reset logic with
hysteresis and synchronization is also provided.
This device is fabricated in a fast bipolar ASBC
(Advanced Standard Buried Collector) process
of Siemens.
AG 2/85
465
SAB 8284B
Pin Definitions and Functions
Symbol
Number
Input (I)
Output (0)
AEN,
AEN,
3, 7
I
ADDRESS ENABLE. AEN is an active lOW signal.
AEN serves to ~ its respective Bus Ready Signal
(RDY, or RDY,). AEN, validates RDY, while AEN, validates
RDY,. Two AEN signal iriputs are useful in system
configurations which permit the processor to access two
Multi-Master System Busses. In non Multi-Master
configurations the AEN signal inputs are tied true (lOW).
RDY"
RDY,
4,6
I
BUS READY (Transfer Complete). RDY is an active HIGH
signal which is an indication from a device located on the
system data bus that data has been received, or is
available. RDY1 is qualified by AEN, while RDY2 is
qualified by AEN,.
ASYNC
15
I
READY SYNCHRONIZATION SELECT. ASYNC is an input
which defines the synchronization mode of the READY
logic. When ASYNC is low, two stages of READY
synchronization are provided. When ASYNC is left open
or HIGH a single stage of READY synchronization is
provided.
READY
5
0
READY. READY is an active HIGH signal which is the
synchronized RDY signal input. READY is cleared after
the guaranteed hold time to the processor has been met.
X"X,
16,17
I
CRYSTAL IN. X, and X, are the pins to which a crystal is
attached. The crystal frequency is 3times the desired
processor clock frequency.
FIG
13
I
FREQUENCY/CRYSTAl SELECT_JIG is a strapping
option. When strapped lOW, F/C permits th~rocessors
clock to be generated by the crystal. When F/C is strapped
HIGH, ClK is generated from the EFI input.
EFI
14
I
EXTERNAL FREQUENCY IN. When F/C is strapped HIGH,
ClK is generated from the input frequency appearing on
this pin. The input signal is a square wave 3 times the
frequency of the desired ClK output.
ClK
8
0
PROCESSOR CLOCK. ClK is the clock output used by the
processor and all devices which directly connect to the
processor's local bus (i.e., the bipolar support chips and
other MOS devices). ClK has an output frequency which
is 1/3 of the crystal or EFI input frequency and a 1/3 duty
cycle. An output HIGH of 4.5 volts (Vee = 5V) is provided
on this pin to drive MOS devices.
PClK
2
0
PERIPHERAL CLOCK. PClK is a TTL level peripheral clock
signal whose output frequency is 1/2 that of ClK and has
50% duty cycle.
OSC
12
0
OSCillATOR OUTPUT. OSC is the TTL level output of the
internal oscillator circuitry. Its frequency is equal to that
of the crystal.
RES
11
I
RESET IN. RES is an active lOW signal which is used to
generate RESET. The SAB 8284B provides a Schmitt
trigger input so that an RC connection can be used to
establish the power-up reset of proper duration.
466
Function
SA882848
Symbol
Number
Input (I)
Output (0)
RESET
10
0
RESET. RESET is an active HIGH signal which is used
to reset the SAB 8086 family processors. Its timing
characteristics are determined by RES.
CSYNC
1
I
CLOCK SYNCHRONIZATION. CSYNC is an active HIGH
signal which allows multiple SAB 8284B to be
synchronized to provide clocks that are in phase. When
CSYNC is HIGH the internal counters are reset. When
CSYNC goes LOW the internal counters are allowed to
resume counting. CSYNC needs to be externally
synchronized to EFI. When using the internal oscillator
CSYNC should be hard-wired to ground.
Vee
18
-
Power Supply (+5V)
GND
9
-
Ground 10V)
Function
Figure 2
Block Diagram
RES
XI
Q
0
RESET
Crystal
Oscillator
X2
OSC
Fie
EFI
+3
+2
SYNC
SYNC
PClK
CSYNC
ROY,
ClK
AEN,
ROY2
AEN2
CK!
·1 FF1
0
I
I
Q
READY
ASYNC
467
I
SAB 8284B
Functional Description
General
The SAB 8248B is a single chip block generatorl
driver for SAB 8086 and SAB 8088 processors.
The chip contains a crystal·controlled oscillator,
a divide·by·three counter, "Ready" synchronization
and reset logic. Refer to Figure 2 for "Block
Diagram" and Figure 1 for "Pin Configuration".
The FIG input is a strapping pin that selects either
the crystal oscillator or the EFI input as the clock for
the +3 counter. If the EFI input is selected as the
clock source, the oscillator section can be used
independently for another clock source. Output
is taken from OSC.
Clock Outputs
Oscillator
The oscillator circuit of the SAB 8284B is designed
primarily for use with an external series resonant
fundamental mode crystal from which the basic
operating frequency is derived.
The crystal frequency should be selected at three
times the required CPU clock. X1 and X2 are the
two crystal input crystal connections. For the most
stable operation of the oscillator (OSC) output ci rcuit,
two series resistors (R , = R, = 510 Q) as shown in
figure 7 are recommended. The output of the
oscillator is buffered and brought out on OSC
so that other system timing signals can be derived
from this stable,crystal-controlled source.
The ClK output is a 33% duty cycle MOS clock
driver designed to drive the SAB 8086 and
SAB 8088 processors directly. PClK is a TTL level
peripheral clock signal whose output frequency is
112 that of elK. PClK has 50% duty cycle.
Reset Logic
The reset logic provides a Schmitt trigger input
(RES) and a synchronizing flip-flop to generate
the reset timing. The reset signal is synchronized
to the falling edge of ClK. A simple RC network
can be used to provide power-on reset by utilizing
this function of the SAB 8284B. Waveforms for
clocks and reset signals are illustrated in Figure 4.
It is advisable to limit stray capacitances to less than
10pF on X1 and X2 to minimize deviation from
operating at the fundamental frequency.
READY Synchronization
Clock Generator
Two READY inputs (RDY" RDY,) are provided to
accomodate two Multi-Master system busses. Each
input has a qualifier (AEN, and AEN" respectively).
The clock generator consists of a synchronous
divide-by-three counter with a special clear input
that inhibits the counting. This clear input (CSYNC)
allows the output clock to be synchronized with an
external event (such as another SAB 8284B clock).
It is necessary to synchronize the CSYNC input to
the EFI clock external to the SAB 8284B. This is
accomplished with two Schottky flip-flops (see
figure 3). The counter output is a 33% duty cycle
clock at one-third the input frequency.
468
SAB 8284B
The AEN signals validate their respective RDY
signals. If a Multi-Master system is not being used
the AEN pin should be tied lOW.
Synchronization is required for all asynchronous
active going edges of either RDY input to guarantee
that the RDY setup and hold times are met. Inactivegoing edges of RDY in normally ready systems
do not require synchronization but must satisfy
RDY setup and hold as a matter of proper system
design.
The ASYNC input defines two modes of READY
synchronization operation.
When ASYNC is lOW, two stages of synchronization are provided for active READY input signals.
Positive-going asynchronous READY inputs will
first be synchronized to flip-flop one at the rising
edge of ClK (requiring a setup time t R1VCH ) and
then synchronized to flip-flop two at the next
falling edge of ClK, after which time the READY
output will go active (HIGH). Negative-going
asynchronous READY inputs will be synchronized
directly to flip-flop two at the falling edge of ClK,
after which time the READY output will go inactive.
This mode of operation is intended for use by
asynchronous (normally not ready) devices in the
system which cannot be guaranteed by design to
meet the required RDY setup timing, tR1V CL, on each
bus cycle (Refer to Figure 5).
When ASYNC is high or left open, the first READY
flip-flop is bypassed in the READY synchronization
logic. READY inputs are synchronized by flip-flop
two on the falling edge of ClK before they are
presented to the processor. This mode is available
for synchronous devices that can be guaranteed to
meet the required ROY time (Refer to Figure 6).
ASYNC can be changed on every bus cycle to select
the appropriate mode of synchronization for each
device in the system.
Figure 3
CSYNC Synchronization
Clock
Synchronize
EFI
>---1----+---10
Q~----'--------'D
Q 1-~--1CSYNC
SAB
8284B
(To other SAB 8284B)
469
SA882848
Absolute maximum ratings
1)
oto 70'C
- 65 to 150'C
-0.5to 7 V
-1.0 to 5.5 V
lW
Temperature Under Bias
Storage Temperature
All Output and Supply Voltages
All Input Voltages
Power Dissipation
D.C. Characteristics
TA
= Ot070'C; Vee = +5V ±10%
Symbol
Parameter
I,
Forward Input Current (ASYNC)
Other Inputs
IR
Reverse Input Current (ASYNC)
Other Inputs
Limit Values
Min.
-
Unit
Test Condition
-1.3
-0.5
mA
V,
V,
50
50
!1A
VR = Vee
VR = 5.25 V
Max.
= 0.45 V
= 0.45 V
= -5 mA
Ve
Input Forward Clamp Voltage
-1.0
V
Ie
Icc
Power Supply Current
110
mA
All outputs open
V,L
Input LOW Voltage
0.8
V,H
Input HIGH Voltage
2.0
V,HR
Reset Input HIGH Voltage
2.6
VOL
Output LOW Voltage
-
0.45
VOH
Output HIGH Voltage CLK
Other Outputs
4
2.4
-
RES Input Hysteresis
0.25
V,HR-V,LR
-
-
V
5mA
-lmA
-lmA
-
') Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposureto absolute maximum rating conditions for extended periods may affect device reliability.
470
SAB 8284B
A.C. Characteristics
TA = Oto +70'C; Vee = +5V ±10%
Timing Requirements
Symbol
Parameter
tEHEL
External Frequency HIGH Time
tElEH
External Frequency lOW Time
tElEL
Limit Values
Min.
XTAl Frequency
12
tRlVCL
ROY" ROY, Active Setup to ClK
tA1VCH
ROY" ROY, Active Setup to ClK
tAlVCl
ROY" ROY, Inactive Setup to ClK
tCLR1X
ROY" ROY, Hold to ClK
tAYVCL
ASYNC Setup to ClK
50
tCLAYX
ASYNC Hold to ClK
0
tAlVAlV
AEN" AEN, Setup to ROY" ROY,
15
tCLA1X
AEN" AEN, Hold to ClK
0
tYHEH
CSYNC Setup to EFI
20
10%-10% V,N
3)
25 ')
MHz
ASYNC
= HIGH
ASYNC
= lOW
0
CSYNC Hold to EFI
10
tYHYL
CSYNCWidth
2· tElEL
ttlHCL
RES Setup to ClK
65
tCLItH
RES Hold to ClK
20
Input Rise Time
ns
35
tEHYl
Input Fall Time
Test Condition
90%-90% V,N
tEHEl +
tElEH+b
tlUL
Unit
13
EFI Period
tlLlH
Max.
-
-
ns
I
-
4)
20
From 0.8 V to 2.0 V
12
From 2.0 V to 0.8 V
Notes see next page.
471
SA882848
Timing Responses
Symbol
Parameter
Limit Values
Min.
telel
ClK Cycle Period
100
teHel
ClK HIGH Time
')
t eleH
ClKlOWTime
')
tCH1CH2
ClK Rise or Fall Time
-
tpHPl
PClK HIGH Time
tClCl-20
tpLPH
PClK lOW Time
tcLCL-20
tRYLeL
Ready Inactive to ClK 6)
-8
tRYHCH
Ready Active to ClK 5)
')
tCLIL
ClK to Reset Delay
tCLPH
ClK to PClK HIGH Delay
tCLPL
ClK to PClK lOW Delay
tCL2Cll
Fig. 7 & Fig. 8
1.0Vto 3.5V
10
-
ns
Fig. 9 & Fig. 10
Fig. 9 & Fig. 10
40
22
OSC to ClK HIGH Delay
-5
OSC to ClK lOW Delay
2
tOLOH
Output Rise Time (except ClK)
tOHOl
Output Fall Time (except ClK)
472
Test Condition
Fig. 7 & Fig. 8
tOlCH
,,=
Unit
-
tOLCL
') (1;' tem) +2 for ClK Freq. ~ 8 MHz
(1;' heel +6 for ClK Freq. = 10 MHz
2) (';' teLeel -15 for ClK Freq. ~ 8 MHz
(';' heel -14 for ClK Freq. = 10 MHZ
3)
EFI rise (5 ns max) + EFI fall (5 ns max).
Max.
-
-
35
20
From 0.8V to 2.0V
12
From 2.0V to 0.8V
4) Setup and hold necessary only to guarantee
recognition at next clock.
5) Applies only to T3 and T w states.
6) Applies only to T, states.
7) 30 MHz for SAB 8284B-1
SAB 8284B
A.C. Testing
Input/Output Waveform
2.4~5_ "'"t'~tC
T'"
0.45
A.C. Testing: Input are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0".
Timing Measurements are made at 1.5 V for Both a logic "1" and "0".
load Circuit
VL = 2.08V
RL
Device
under
test
f
=32Sil.
(L
CL = 100 pF for ClK
CL = 30 pF for READY
473
SAB 8284B
Waveforms
Figure 4
.
I
Clocks and Reset Signa s
Name I/O
EFI
J\f\
I
OSC
ClK
o
PClK
0
CSYNC
I
--j
tCLllH--j
I
ji
tllHCL
H·'--f-----j1cL1LC
RESET
0
f
Note All timing measurements are rna de aI 15 V,unless otherwise noted
474
SAB 8284B
Figure 5
Ready Signals - Asynchronous Devices
ClK
RDY I
RDYl _ _ _ _ _ _....J
tCLA1X
tCLAYX
READY
--------------~
tRYHCH
Figure 6
Ready Signals - Synchronous Devices
ClK
..
RDY,
RDYl
tRlVCL
tCLRIX
AEN,
AENl
..
..
ASYNC
tCLAIX
READY
tRYHCH
475
SAB 8284B
Testconditions
Figure 7
Clock High- and Low Time; Using X1, X2
Load
ClK
1)
R1
r-CJ
."b
Xl
2~z9
X2
J. R2
FIC
...
CSYNC
R1 =R2=510n
Figure 8
Clock High- and Low Time; Using EFI
Pulse Generator
EFI
\ICc
!
Fie
CSYNC
1)C L =100pF
476
CLK
Load
,)
SAB 8284B
Figure 9
Ready to Clock - Using Xl, X2
ICe
L-
R1
AEN,
ClK
1)
X,
.L24MHzdJ
l
load
"=r
R2
X2
Ready
)
load 2
OSC
Pulse Generator
Trigger
RDY2
FIG
AEN2
CSYNC
R1=R2=510Q
Figure 10
Ready to Clock - Using EFI
Pulse Generator
~
Trigger
Pulse Generator
EFI
ClK
load ,)
Vee
I
Fie
AEN,
RDY2
AEN2
CSYNC
11
21
CL
CL
Ready
load
2)
= 100 pF
= 30 pF
477
SAB 8286A/SAB 8287 A
Octal Bus Transceiver
• Fully compatible with
SAB 8286/SAB 8287
• Fully Parallel 8-Bit
Transceivers
• 40% Less Power Supply Current
than Standard SAB 8286/SAB 8287
• Data Bus Buffer 'Driver for
SAB 80286, SAB 80186, SAB 8086, SAB 8085,
SAB 8048 and SAB 8051 Families
• High Output Drive Capability
for Driving System Data Bus
• 3-State Outputs
• 20-Pin Package
• No Output Low Noise when Entering or
Leaving High Impedance State
Pin Configuration
Pin Names
A0
~c
A0
~c
Al
80
Al
80
A2
81
A2
81
A.
82
A.
Bi
A4
83
A4
83
84
As
85
As
As
6
As
7
SA8
8286A
SA8
8287A
8s
A7
87
DE
9
T
GND
10
11
The SAB 8286A and SAB 8287A are 8-bit
bipolar transceivers with 3-state outputs.
The SAB 8287A inverts the input data at
its outputs while the SAB 8286A does not.
Thus, a wide variety of applications for
Bo-B7
System Bus Data
DE
Output Enable
T
Transmit
Vee
Power Su pply (+ 5V)
GND
Ground (OV)
Bs
A7
10
Local Bus Data
84
85
N
GND
Ao-A7
87
11
buffering in microcomputer systems can be met.
This device is fabricated in a fast bipolar ASBC
(Advanced Standard Buried Collector) process
of Siemens.
AG 1/85
479
SAB 8286A / SAB 8287 A
Logic Diagrams
SA88286A
SA88287A
r---------,
r---------,
I
I
I
I
I
I
I
A0
A0
I
I
I
80
80
A1
81
A1
81
A2
82
A2
]2
A3
83
A3
83
A4
84
A4
84
A5
85
A5
85
A6
86
A6
86
A?
8?
A?
]?
DE
T
OE
T
I
1
I
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ________1
Pin Definitions and Functions
Symbol
T
Function
111
OE
9
A I -A 7
1-8
II
j
; I/O
I
B,-B 7
(SAB 8286A)
TRANSMIT - T is an input control signal used to
1control the direction of the transceivers.
When HIGH, it configures the trarisceiver's BI -B 7 as
outputs with Ao-A7 as inputs. T _LOW configures AO-7 as
1the outputs with B,-B 7 serVing as the inputs.
ENABLE - OE is an input control signal used to
IOUTPUT
enable the appropriate output driver (as selected
, by T) onto its respective bus. This signal
Iis active LOW.
LOCAL BUS DATA PINS - These pins serve to
either present data to or accept data from the
I processor's local bus depending upon the state
, ofthe T pin.
SYSTEM BUS DATA PINS - These pins serve to
- either present data to or accept data from the system
1 bus depending upon the state of the T pin.
Bo-B;
(SAB8287A)
Vee
20
I Power Supply (+5V)
GND
10
IGround (OV)
480
SAB 8286A / SAB 8287 A
Functional Description
The SAB 8286A and SAB 8287A transceivers are
S-bit transceivers with high impedance outputs.
With T active HIGH and OE active LOW, data
at the Ao-A7 pins is driven onto the Bo-B7 pins.
With T inactive LOW and OE active LOW, data at
the Bo-B7 pins is driven onto the Ao-A7 pins.
No output low glitching will occur whenever the
transceivers are entering or leaving the high
impedance state.
Absolute Maximum Ratings 1)
oto +70'C
-65to +150'C
-0.5to
+7V
-1.0to +5.5V
1W
Temperature Under Bias
Storage Temperature
All Output and Supply Voltages
All Input Voltages
Power Dissipation
D. C. Characteristics
TA = Ot070'C; Vee = +5V ±10%
Symbol
I Parameter
Ve
I Input Clamp Voltage
Icc
I Power Supply Current
I,
i Forward Input Current
IR
I
VOL
[ Output LOW Voltage - B Outputs
- A Outputs
VOH
10FF
VIL
V,H
CIN
Limit Values
Test Condition
Min.
-1
-0.2
IOutput HI GH Voltage - B Outputs
-A Outputs
I
[ 2.4
I 2.4
I Input Capacitance
1) Stresses above those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device.
Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
[ 10L
IO.9
Iv
I
I VF = 0.45V
. VR= 5.25V
V
I-
2.0
[-
I
I'R
! 0.8
[Input LOW Voltage - A Side
- B Side
I
I
I
'I,
[ Output Off Cu rrent
Output Off Cu rrent
Input HIGH Voltage
I
-5 mA
All outputs open
mA
!
~'rtA
, 0.45
I 0.45
lIe =
,V
~
Reverse Input Current
I
10FF
I
10L
= 32 mA
= 16 mA
[loH =-5mA
10H = -1 mA
I
VOFF = 0.45V
VOFF = 5.25V
I
I
Vee = 5.0V, See Note 2
. Vee = 5.0V, See Note 2
Vee = 5.0V, See Note 2
12
VBIAS = 2.5V, Vee = 5V
TA = 25'C
2) B Outputs: 10L = 32 mA; 10H = -5 mA; CL = 300 pF
A Outputs: 10L = 16 mA; 10H = -1 mA; CL = 100 pF
481
SAB 8286A / SAB 8287 A
A.C. Characteristics
TA = Oto +70°C; Vee = +5V ±
10%
loading
B Outputs:
IOL
= 32 mA; IOH = -5 mA; CL = 300 pF
Symbol
Parameter
tlVOV
A Outputs:
IOL
= 16 mA; IOH = -1
limit Values
Min.
Max.
Inputto Output Delay
Inverting
Non-Inverting
5
5
22
30
tEHTV
TransmitlReceive Hold Time
5
tTVEL
Transmit/Receive Setup
10
tEHOl
Output Disable Time
5
18
t ELOV
Output Enable Time
10
30
t'LlH, tOLOH
Input, Output Rise Time
tIHIL, tOHOl
Input, Output Fall Time
Unit
mA; C L
= 100 pF
Test Condition
-
1)
ns
-
20
From 0.8 to 2.0 V
12
From 2.0 to 0.8V
1) See waveforms and test load circuit.
Waveforms
All timing measurements are made at 1.5 V unless otherwise noted.
Timing
\V
J\.
Inputs
I
\
J
Outputs
tlVOV ' - -
W
J\.
-
1\
-
.JllisR
-OW
>.;':----VOL +O.1V
VOH
~
i--tEHTV-
T
\I
~
482
JrYIl
SAB 8286A / SAB 8287 A
Output Delay vs. Capacitance
ns
ns
50
50
SAB
8286A
SAB
8287A
40
~
CiJ
CJ
40
30
r--- ~ t~se - ~
-.I~
V~~~\t~\~ ~
20
..-~
10
o
o
200
400
600
~
CiJ
----
800
CJ
30
20
10
o
1000 pF
-:::
o
~
,~~\~
~
.. o~s
200
400
-----------
600
800
I
1000 PF
Load-
Load~
Output Test Load Circuit
B Output
B Output
A Output
1,5V
2,14V
1,5V
[J 52,7\1
[ 66\1
Ou tput
()------<
Ou tpu t
()------<
()------<
!300 PF
I'00PF
3-state to VOL
Output
3-state to VOL
switching
483
SAB 8286A / SAB 8287 A
Output Test Load Circuit
B Output
l,SV
}S012
Output
!300 PF
484
A Output
l,SV
2.28V
~9OOO
O"'P"'~
0---
3-state to
A Output
VO H
Tl00 PF
3-state to VO H
11412
Output
0--
tl00PF
switching
SAB 8288A Bus Controller
for SAB 8086 Family Processors
Fully compatible with SAB 8288
40% less Power Supply Current
than Standard SAB 8288
• Bipolar Drive Capability
• Provides Advanced Commands
Provides Wide Flexibility
in System Configurations
o 3-State Command Output Drivers
G Configurable for Use with an I/O Bus
• Facilitates Interface to One or
Two Multi-Master Busses
It
CI
CI
Pin Configuration
Pin Names
So- S,
::J Vee
19 ::JSe
20
IOSC 1
GLK C 2
Si C
18
3
DTfR"C 4
PSi
17 P MCE/PDEN
16
ALEC 5
PDEN
Status
ClK
Clock
ALE
Adress latch Enable
DEN
Data Enable
DT/R
Data Transmit/Receive
AEN
Address Enable
CEN
Command Enable
lOB
Input/Output Bus Mode
AIOWC
Advanced I/O Write
I
10WC
I/O Write
15 peEN
10RC
I/O Read
MRDCC 7
14p'INTA
AMWC
Advanced Memory Write
AMWCC 8
13 PIORC
MWTC
Memory Write
MWTCC 9
12
PAIOWC
llP IOWC
MRDC
Memory Read
INTA
Interrupt Acknowledge
MCE/PDEN
Master Cascade/Peripheral Data
Vee
Power Supply (+5V)
GND
Ground (OV)
AENC 6
GNDC 10
SAB
8288A
SAB 8288A Bus Controller is a 20-pin bipolar
component for use with medium-to-Iarge
SAB 80186, SAB 80.188, SAB 8086 and SAB 8088
processing systems. The bus controller provides
command and control timing generation as well as
bipolar bus drive capability while optimizing system
performance.
A strapping option on the bus controller configures
it for use with a multi-master system bus and
separate I/O bus.
This device is fabricated in a fast bipolar ASBC
(Advanced Standard Buried Collector) process of
Siemens.
AG 1/85
485
SAB8288A
Block Diagram
<.D
ro~
ro "
_
0
co 2
«'"
en
50
51
52
MRDC
Status
Decoder
MWTC
Command
Signal
Generator
AMWC
-
f----
10RC
10WC
~
m
c
Ol
u;
-0
c
E
E
'"
0
AIOWC
u
INTA
ClK
e"'5 {
~.f
AEN
Control
logic
CEN
I---
I--
Control
Signal
Generator
lOB
I
I
GND
+5V
Pin Definitions and Functions
Symbol
Number
Input (I)
Output (0)
lOB
1
I
INPUT/OUTPUT BUS MODE - When the lOB is strapped
HIGH the SAB 8288A functions in the I/O Bus mode. When
it is strapped lOW, the SAB 8288A functions in the System
Bus mode. (See sections on I/O Bus and Systems Bus
modes).
ClK
2
I
CLOCK - This is a clock signal from the SAB 8284A or
SAB 8284B clock generator and serves to establish when
command and control signals are generated.
S;,S";",s,
3,18,
19
I
STATUS INPUT PINS - These pins are the status input pins
from the SAB 80186, SAB 80188, SAB 8086 or SAB 8088
processors. The SAB 8288A decodes these inputs to
generate command and control signals at the appropriate
time. When these pins are not in use (passive) they are all
HIGH. (See chart under Functional Description).
486
Function
SAB 8288A
Symbol
Input (I)
Output (0)
I Function
0
Idirection
DATA TRANSMITIRECEIVE - This signal establishes the
of data flow through the transceivers. A HIGH
DT/Fi
14
1
ALE
AEN
MRDC
AMWC
ADDRESS LATCH ENABLE - This signal serves to strobe
5
I an address into the address latches. This signal is active
I
I
HIGH and latching occurs on the falling (HIGH to LOW)
transition. ALE is intended for use with transparent
D type latches.
16
II
Ithe
ADDRESS ENABLE - AEN enables command outputs of
SAB 8288A Bus Controller at least 105 ns after It
I
1
1becomes active (LOW). AEN going inactive immediately
3-states the command output drivers. AEN does not affect
I the 1/0 command lines if the SAB 8288A is in the 1/0 Bus
I mode (lOB tied HIGH).
17
10
I MEMORY READ COMMAND -
I
I
,8
0
MWTC
10WC
I
I
'9
10
1
111
AIOWC
12
1
1
I
1
114
MEMORY WRITE COMMAND - This command line
instructs the memory to record the data present on the
daja bus. This signal is active LOW.
0
I ADVANCED 1/0 WRITE COMMAND -
0
1110 READ COMMAND - This command line instructs an
1/0 device to drive its data onto the data bus. This signal is
active LOW.
0
I
I
The AIOWC issues
an 1/0 Write Command earlier in the machine cycle to give
' 1/0 devices an early indication of a write instruction.
I Its timing is the same as a read command signal.
I AIOWC is active Law.
1INTERRUPT ACKNOWLEDGE- Thiscommand line tells an
I interrupting device that its interrupt has been acknowledged
and that it should drive vectoring information onto
the data bus. This signal is active LOW.
I
I
:I
CEN
15
1
DEN
1
I
1110 WRITE COMMAND - This command line instructs an
1/0 device to read the data on the data bus. This signal is
active LOW.
.
I
13
. ADVANCED MEMORY WRITE COMMAND - The AMWC
issues a memory write command earlier in the machine
I cycle to give memory devices an early indication of a write
instruction. Its timing is the same as a read command
signal. AMWC is active LOW.
0
I
10RC
This command line
1instructs the memory to drive its data onto the data bus.
This signal is active LOW .
I
1
INTA
on this line indicates Transmit (write to 1/0 or memory)
and a LOW indicates Receive (Read).
16
I
COMMAND ENABLE - When this signal is LaWall
I SAB 8288A command outputs and the DEN and PDEN
I control outputs are forced to their inactive state. When this
, signal is HIGH, these same outputs are enabled.
I DATA ENABLE -
This signal serves to enable data
transceivers onto either the local or system data bus.
This signal is active HIGH.
487
I
SAB 8288A
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
MCE/PDEN
17
0
This is a dual function pin:
MCE (lOB is tied LOW) - Master Cascade Enable occurs
during an interrupt sequence and seNes to read a Cascade.
Address from a master PIC (Priority Interrupt Controller)
onto the data bus. The MCE signal is active HIGH.
PDEN (lOB is tied HIGH) - Peripheral Data Enable enables
the data bus transceiver for the I/O bus during I/O
instructions. It performs the same function for the I/O bus
that DEN performs forthe system bus. PDEN is active LOW.
Vee
20
-
Power Supply (+5V)
GND
10
-
Ground (OV)
Function
Functional Description
The command logic decodes the three SAB 80186,
SAB 80188, SAB 8086 or SAB 8088 CPU status
lines (SO, 5,', 5;) to determine what command is to be
issued. This chart shows the meaning of each status
"word".
'S2
Sf
50
Processor State
SAB 8288A Commahd
0 Interrupt Acknowledge
INTA
IORC
0
0
0
0
1
0
1
0 Write I/O Port
IOWC, AlTIWl::
0
1
1
None
1
0
0 Code Access
MRDC
1
0
1
MRDC
1
1
0 Write Memory
MWTC,AMWC
1
1
1
None
Read I/O Port
Halt
Read Memory
Passive
The command is issued in one of two ways
dependent on the mode of the SAB 8288A
Bus Controller.
I/O Bus Mode- The SAB 8288A is in the I/O Bus
mode ifthe lOB pin is strapped HIGH. In the I/O Bus
mode all I/O command lines (lORC, IOWC, AIOWC,
INTA) are always enabled (i.e., not dependent on
AEN). When an I/O command is initiated by the
processor, the SAB 8288A immediately activates
the command lines using PDEN and DT fA: to control
the I/O bus transceiver. The I/O command lines
should not be used to control the system bus in this
configuration because no arbitration is present.
This mode allows one SAB 8288A Bus Controller to
handle two external busses. No waiting is involved
488
when the CPU wants to gain access to the I/O bus.
Normal memory access requires a "Bus Ready"
signal (AEN LOW) before it will proceed. It is
advantageous to use the lOB mode if I/O or
peripherals dedicated to one processor exist in a
mUlti-processor system.
System Bus Mode- The SAB 8288A is in the System
Bus mode if the lOB pin is strapped LOW. In this
mode no command is issued until 115 ns after the
AEN Line is activated (LOW). This mode assumes
bus arbitration logic will inform the bus controller
(on the AEN line) when the bus is free for use. Both
memory and I/O commands wait for bus arbitration.
This mode is used when only one bus exists.
Here, both I/O and memory are shared by more
than one processor.
SAB 8288A
Command Outputs
The advanced write commands are made available
to initiate write procedures early in the machine
cycle. This signal can be used to prevent the
processor from entering an unnecessary wait state.
The command output are:
MRDC - Memory Read Command
MWTC - Memory Write Command
10RC -I/O Read Command
10WC - I/O Write Command
AMWC - Advanced Memory Write Command
AIOWC - Advanced I/O Write Command
INTA -Interrupt Acknowledge
INTA (Interrupt Acknowledge) acts as an I/O read
during an interrupt cycle. Its purpose is to inform
an interrupting device that its interrupt is being
acknowledged and that it should place vectoring
information onto the data bus.
Control Outputs
The control outputs of the SAB 8288A are Data
Enable (DEN)' Data Transmit/Receive (DT/R) and
Master Cascade Enable/Peripheral Data Enable
(MCE/PDEN). The DEN signal determines when the
external bus should be enable onto the local bus·
and the DT /R determines the direction of data
transfer. These two signals usually go to the chip
select and direction pins. of a transceiver.
If the system contains only one PIC, the MCE
signal is not used. In this case the second Interrupt
Acknowledge signal gates the interrupt vector
onto the processor bus.
Address Latch Enable and Halt
Address Latch Enable (ALE) occurs during each
machine cycle and serves to strobe the current
address into the address latches. ALE also serves to
strobe the status (5";;, $" 5;) into a latch for halt state
decoding.
Command Enable
The Command Enable (CEN) input acts as a
command qualifierforthe SAB 8288A.lfthe CEN pin
is high the SAB 8288A functions normally. If the CEN
pin is pulled LOW, ali command lines are held in their
inactive state (not 3-state). This feature can be used
to implement memory partitioning and to eliminate
address conflicts between system bus devices and
resident bus devices.
The MCE/PDEN pin changes function with the two
modes of the SAB 8288A. When the SAB 8288A is in
the lOB mode (lOB HIGH) the PDEN signal serves
as a dedicated data enable signal for the I/O or
Peripheral System bus.
Interrupt Acknowledge and MCE
The MCE signal is used during an interrupt
acknowledge cycle if the SAB 8288A is in the System
Bus mode (lOB LOW). During any interrupt
sequence there are two interrupt acknowledge
cycle no data or address transfers take place.
Logic should be provided to mask off MCE during
this cycle. Just before the second cycle begins the
MCE signal gates a master Priority Interrupt
Controller's (PIC) cascade address onto the
processor's local bus where ALE (Address Latch
Enable) strobes it into the address latches. On the
leading edge ofthe second interrupt cycle the
addressed slave PIC gates an interrupt vector
onto the system data bus where it is read by the
processor.
489
SAB8288A
Absolute Maximum Ratings
1)
oto + 70°C
-65to +150°C
-0.5to +7V
-1.0to +5.5V
Temperature Under Bias
Storage Temperature
All Output and Supply Voltages
All Input Voltages
Power Dissipation
lW
D.C. Characteristics
TA = 0 to 70°C; Vcc = +5V ±10%
Limit Values
Symbol
Parameter
Vc
Input Clamp Voltage
-1
Icc
Power Supply Current
140
Min.
-
Max.
IF
Forward Input Current
IR
Reserve Input Current
50
VOL
Output low Voltage
Command Outputs
Control Outputs
0.5
0.5
VOH
Units
Test Conditions
V
Ie = -5mA
mA
-0.7
Output High Voltage
Command Outputs
Control Outputs
2.4
2.4
-
V,L
Input low Voltage
-
0.8
V'H
Input High Voltage
2.0
-
10FF
Output Off Current
-
100
All outputs open
VF = 0.45V
~A
VR = Vcc
IOL = 32 mA
IOL=16mA
V
I/OH = -5 mA
10H=-lmA
[lA
VOFF = 0.4 to 5.25 V
Units
Test Conditions
ns
-
A.C. Characteristics
TA = Ot070°C; Vcc = +5V ±10%
Timing Requirements
Symbol
Parameter
limit Values
Min.
tCLCL
ClK Cycle Period
100
tCLCH
ClK low Time
50
leHCL
ClK High Time
30
tsvCH
Status Active Setup Time
35
tCHSV
Status Active Hold Time
10
tSHCL
Status Inactive Setup Time
35
tCLSH
Status Inactive Hold Time
10
tlUH
Input, Rise Time
t'Hll
Input, Fall Time
-
Max.
-
20
From 0.8V to 2.0V
12
From 2.0V to 0.8V
1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
490
SAB8288A
Timing Responses
Limit Values
Symbol
Parameter
tCVNV
Control Active De[ay
5
tCVNX
Control Inactive Delay
10
Min.
Max.
Units
Test Conditions
45
tCI.LHI tCLMCH
ALE MCE Active De[ay (from ClK)
tSVLH , tsvMCH
ALE MCE Active Delay (from Status)
tCHLL
AlE Inactive Delay
tCLML
Command Active Delay
tCLMH
Command Inactive Delay
tCHDTL
Direction Control Active De[ay
50
tCHDTH
Direction Control Inactive Delay
30
tAELCH
Command Enable Time
tAEHCZ
Command Disable Time
tAELCY
Enab[e Delay Time
-
20
4
15
10
35
MRDC
fClRC
MWTC
40
115
mwc
INTA
AMWC
A[OWC
Other
= 32 mA
10H= -5mA
CL = 300 pF
IOL
/iOL =16mA
io H =-1mA
CL = SO pF
200
tAEVNV
AEN to DEN
20
tCEVNV
CEN to DEN, PDEN
25
-
ns
tCELAH
CEN to Command
t OLOH
Output, Rise Time
20
From O.SV to 2.0V
t OHOL
Output, Fall Time
12
From 2.0V to O.SV
tCLML
A.C. Testing Input, Output Waveform
Input/Output
A.C. Testing Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". The clock is driven at
4.3V and 0.25V timing measurements are made at 1.5V for both a logic "1" and "0"
491
I
SAB8288A
Test Load Circuits - 3-State Command Output Test Load
1.5V
1.5V
Oulpulo--
Output
0--
!300 PF
!300 PF
3-slate 10 High
3-state to Low
Test Load Circuits - 3-State Command Output Test Load
2,14V
2,28V
52,7\1
Outpulo--
!
Output
300pF
Command Output
Test Load
492
[ 11411
()-----<
I
80 PF
Control Output
Test Load
SAB 8288A
Waveforms
Timing Diagram
State - - T4
T,
T1
T3
T4
'---ICLCL -t--ICLCH-
eLK
,/\
h
./\
-Er-~
-
~ ICHCL
- ~~y
~
\(
Cidre'Ss
valid
Address/Data 1)
tllitl....
t--
l-~
Y2)
"\
ALE
LI' ~
Write
Data valid
!£H!l
-
-r
k
-
-
~
DEN (Read)
(INTA)
~
-
\
PDEN (Read)
(INTA)
-
~
DEN (Write)
~
PDEN (Write)
OTIR (Read)
(INTA)
MCE
I
I
I
~
----
-~
w\
-
t
~~
-
~
\
~C~D:J_r-
'--
-
ICHDTH
-~
ISVMCH
1) Address/Data Bus is shown only for reference
purposes
2) leading edge of ALE and MCE is determined by
the falling edge of ClK or status going active,
whichever occurs last.
3) All timing measurements are made at 1.5Vunless
specified otherwise.
493
SAB8288A
DEN, PDEN Qualification Timing
CEN
tAEVNq
\11
1\
DEN
---tCEVNV-
\11
1\
Address Enable (AEN) Timing (3-State Enable/Disable)
tAELCV
Output
Command
CEN - - - - - - - - - - - - '
CEN must be low or valid prior to T2 to prevent the command from being generated.
494
SAB8289
Bus
Arbiter
SAB 8289
8 MHz
SAB 8289-110 MHz
• Provides Multi-Master System Bus Protocol
• Synchronizes SAB 8086/SAB 8088 Processors
with Multi-Master Bus
• Provides Simple Interface with SAB 8288
Bus Controller
• Four Operating Modes for Flexible System
Configuration
• Compatible with Intel Bus Standard MUlTIBUS™
(MUlTIBUS is a trademark of INTEL Corporation
USA)
• Provides System Bus Arbitration for SAB 8089
lOP in Remote Mode
Pin Configuration
52
Pin Names
20
VCC
S0-2
Status
lOB
I/O Bus Present
lOB
19
51
SYSB/RESB
System/Resident Bus
SYSB/RESB
18
50
RESB
Resident Bus Present
RESB
17
ClK
BClK
Bus Clock
INIT
Initialisation
BClK
16
lOCK
BREO
Bus Request
!NiT
15
CRDlCK
BPRO
Bus Priority Out
BREa
14
ANYRDST
BPRN
Bus Priority In
AEN
ClK
System Clock
AEN
Address Enable
ANYROST
Any Request
CROlCK
Common Request lock
CBRO
Common Bus Request
lOCK
Bus lock
BPRO
13
BPRN
12
CBRD
GND
11
BUSY
The SAB 8289 Bus Arbiter is a 20-pin, 5-volt-only
bipolar component for use with medium to large
SAB 8086/SAB 8088 multi-master/multiprocessing
systems. The SAB 8289 provides system bus
vee
+5V
GND
Ground (OV)
arbitration for systems with multiple bus masters,
such as an SAB 8086 epu with SAB 8089 lOP in its
REMOTE mode, while providing bipolar buffering
and drive capability.
AG 10/83
495
SAB8289
Pin Definitions and Functions
Symbol
Number
Input (I)
Output (0)
S0,S1,S2
1, 18, 19
I
Status Input Pins
These pins are the status input pins from a SAB 8086,
SAB 8088 or SAB 8089 processor. The SAB 8289 decodes
these pins to initiate bus request and surrender actions.
CLK
17
I
Clock
This is the clock from the SAB 8284A clock chip and serves to
establish when bus arbiter actions are initiated.
LOCK
16
I
Lock
LOCK is a processor generated signal which when activated
(low) serves to prevent the arbiter from surrendering the
multi-master system bus to any other bus arbiter, regardless
of its priority.
CROLCK
15
I
Common Request Lock
CROLCK is an active low signal which serves to prevent the
arbiter from surrendering the multi-master system bus to any
other bus arbiter requesting the bus through the CBRO input
pin.
RESB
4
I
Resident Bus
RESB is a strapping option to configure the arbiter to operate
in systems having both a multi-master system bus and a
Resident Bus. When it is strapped high the multi-master
system bus is requested or surrendered as a function of the
SYSB/RESB input pin. When it is strapped low the SYSB/RESB
input is ignored.
ANYRQST
14
I
Any Request
ANYROST is a strapping option which permits the multi master
system bus to be surrendered to a lower priority arbiter as
though it were an arbiter of higher priority (i.e., when a lower
priority arbiter requests the use of the multi-master system
bus, the bus is surrendered as soon as it is possible).
Strapping CBRQ low and ANYROST high forces the SAB 8289
arbiter to surrender the multi-master system bus after each
transfer cycle. Note that when surrender occurs BREO is
driven false (high).
lOB
2
I
10 Bus
lOB is a strapping option which configures the SAB 8289
Arbiter to operate in systems having both an 10 Bus
(Peripheral Bus) and a multi master system bus. The arbiter
requests and surrenders the use of the multimaster system
bus as a function of the status line, S2. The multi-master
system bus is permitted to be surrendered while the
processor is performing 10 commands and is requested
whenever the processor performs a memory command.
Interrupt cycles are assumed as coming from the peripheral
bus and are treated as would be an 10 command.
AEN
13
0
Address Enable
AEN is the output of the SAB 8289 Arbiter to the processor's
address latches, to the SAB 8288 Bus Controller and
SAB 8284A Clock Generator. AEN serves to instruct the Bus
Controller and address latches when to tri-state their output
drivers.
496
Function
SAB 8289
Symbol
Number
Input (I)
Output (0)
SYSB/RESB
3
I
System Bus/Resident Bus
SYSB/RESB is an input signal when the arbiter is configured
in the S.R. Mode (RESB is strapped high) which serves to
determine when the multi master system bus is request.ed
and when the multi-master system bus surrendering is
permitted. The signal is intended to originate from some
form of address mapping circuitry such as a decoder or
PROM attached to the resident address bus. Signal
transitions and glitches are permitted on this pin from 01 of
T4 to 01 to T2 of the processor cycle. During the period from
01 ofT2 to 01 of T4 only clean transitions are permitted on
this pin (no glitches). If a glitch does occur the arbiter may
capture or miss it, and the multi-master system bus may be
requested or surrendered, depending upon the state ofthe
glitch. The arbiter requests the multi-master system bus in
the S.R. Mode when the state of the SYSB/RESB pin is high
and permits the bus to be surrendered when this pin is low.
CBRO
12
110
Common Bus Request
CBRO is an input signal which serves to instruct the arbiter if
there are any other arbiters of lower priority requesting the
use of the multi-master system bus.
The CBRO pins (open-collector output) of all the SAB 8289
Bus Arbiters which are to surrender the multi-master-system
bus upon request are connected together.
The Bus Arbiter running the current transfer cycle will not
itself pull the CBRO line low. Any other arbiter connected to
the CBRO line can request the multi-master system bus. The
arbiter presently running the current transfer cycle drops its
BREO signal and surrenders the bus whenever the proper
surrender conditions exist. Strapping CBREO low and
ANYROST - high allows the multi-master system bus to be
surrendered after each transfer cycle. See the pin definition of
ANYROST.
INIT
6
I
Initialize
INIT is an active low multi master system bus input signal
which is used to reset all the bus arbiters on the multi-master
system bus. After initialization, no arbiters have the use of
the multi-master system bus.
BClK
5
I
Bus Clock
BClK is the multi-master system bus clock to which all
multimaster system bus interface signals are synchronized.
BREO
7
0
Bus Request
BREG is an active low output signal in the parallel Priority
Resolving Scheme which the arbiter activates to request the
use of the multi-master system bus.
BPRN
9
I
Bus Priority In
BPRN is the active low signal returned to the arbiter to
instruct it that it may acquire the multi master system bus on
the next falling edge of BClK. BPRN indicates to the arbiter
that it is the highest priority requesting arbiter presently on
the bus. The loss of BPRN instructs the arbiter that it has loss
priority to a higher priority arbiter.
Function
497
SAB8289
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
BPRO
8
a
Bus Priority Out
BPRO is an ac'ive low output signal which is used in the
serial priority resolving scheme where BPRO is daisy chained
to BPRN of the next lower priority arbiter.
BUSY
11
I/O
Busy
BUSY is an active low open collector multi-master system
bus interface signal which is used to instruct all the arbiters
on the bus when the multi-master system bus is available.
When the multi-master system bus is available the highest
requesting arbiter (determined by BPRN) seizes the bus and
pulls BUSY low to keep other arbiters off of the bus. When
the arbiter is done with the bus it releases the BUSY signal
permitting it to go high and thereby allowing another arbiter
to acquire the multi-master system bus.
vee
20
I
Power Supply (+5 V
GND
10
I
Ground (OV)
Function
± 10%)
Block Diagram
IN IT
BClK
Multlbus
Interface
(S1
SAB 8086/SAB 80881
SAB 8089 status
<51
I
,S0 ~
ClK
Processor
Control
~
CRQlCK
RESB
Control
local
Bus
Interface
ANYRQST
10B-
,5V
498
GNO
I
~ BREQ I
Multlbus TM
BPRN ~ Command
:::~Jr
CBRG
lOCK -
i
Signals
SAB 8289
Functional Description
The SAB 8289 Bus Arbiter operates in conjunction
with the SAB 8288 Bus Controller to interface
SAB 8086/SAB 8088/ SAB 8089 processors to a
multi-master system bus (both the SAB 8086 and
the SAB 8088 are configured in their max model.
The processor is unaware of the arbiter's existence
and issues commands as though it has exclusive
use of :he system bus. If the processor does not
have the use of the multi-master system bus, the
arbiter prevents the Bus Controller (SAB 82881, the
data transceivers and the address latches from
accessing the system bus (e.g. all bus driver
outputs are forced into the high impedance state).
Since the command sequence was not issued by
the SAB 8288, the system bus will appear as "Not
Ready" and the processor will enter wait states.
The processor will remain in Wait until the Bus
Arbiter acquires the use of the multi-master
system bus whereupon the arbiter will allow the
bus controller, the data transceivers, and the
address latches to access the system. Typically,
once the command has been issued and a data
transfer has taken place, a transfer acknowledge
(XACK) is returned to the processor to indicate
"READY" from the accessed slave device. The
processor then completes its transfer cycle. Thus
the arbiter serves to multiplex a processor (or bus
masterl onto a multi-master system bus and avoid
contention problems between bus masters.
Arbitration between Bus Masters
In general, higher priority masters obtain the bus
when a lower priority master completes its present
transfer cycle. Lower priority bus masters obtain
the bus when a higher priority master is not
accessing the system bus. A strapping option
(ANYRQST) is provided to allow the arbiter to
surrender the bus to a lower priority master as
though it were a master of higher priority. If there
are no other bus masters requesting the bus,
the arbiter maintains the bus so long as its processor has not entered the HALT State. The arbiter
will not voluntarily surrender the system bus and
has to be forced off by another master's bus
request, the HALT State being the only exception.
Additional strapping options permit other modes
of operation wherein the multi master system
bus is surrendered or requested under different
sets of conditions.
Modes of Operation
There are two types of processors in the SAB 8086
family. An Input/Output processor (the SAB 8089
lOP) and the SAB 8086/SAB 8088 CPUs.
Consequently, there are two basic operating
modes in the SAB 8289 bus arbiter. One, the lOB
(I/O Peripheral Bus) mode, permits the processor
access to both an I/O Peripheral Bus and a
multi-master system bus. The second, the RESB
(Resident Bus mode), permits the processor to
communicate over both a Resident Bus and a
multi-master system bus. An I/O Peripheral Bus is
a bus where all devices on that bus, including
memory, are treated as I/O devices and are
addressed by 110 commands. All memory
commands are directed to another bus, the
multi-master system bus. A Resident Bus can issue
both memory and I/O commands, but it is a
distinct and separate bus from the multi-master
system bus. The distinction is that the Resident
Bus has only one master, providing full availability
and being dedicated to that one master.
The lOB strapping option configures the SAB 8289
Bus Arbiter into the lOB mode and the strapping
option RESB configures it into the RESB mode.
It might be noted at this point that if both strapping
options are strapped false, the arbiter interfaces
the processor to a multi-master system bus only.
With both options strapped true, the arbiter interfaces the processor to a multi-master system bus,
a Resident Bus, and an I/O Bus.
In the lOB mode, the processor communicates and
controls a host of peripherals over the Peripheral
Bus. When the I/O Processor needs to communicate with system memory, it does so over the
system memory bus.
The SAB 8086 and SAB 8088 processor can
communicate with a Resident Bus and a multimaster system bus. Two bus controllers and only
one Bus Arbiter would be needed in such a
configuration. In such a system configuration the
processor would have access to memory and
peripheral of both busses. Memory mapping
techniques are applied to select which bus is to be
accessed. The SYSB/RESB input on the arbiter
serves to instruct the arbiter as to whether or not
the system bus is to be accessed. The signal
connected to SYSB/RESB also enables or disables
commands from one of the bus controllers.
499
SAB8289
Summary of SAB 8289 Modes, Requesting and Relinquisting the Multi-master system bus
Status Lines From
SAB 8086 I 88 I 89
lOB Mode
Only
RESB (Mode) Only
10B=High RESB=High
lOB Mode RESB Mode
10B=Low RESB=High
10B=Low SYSB/RESB SYSB/RESB SYSB/RESB SYSB/RESB
=High
=Low
=High
=Low
x
x
x
x
x
x
x
x
x
x
x
x
S2
S1
SO
COMMANDS
0
0
0
0
0
1
0
1
0
HALT
0
1
1
MEM
COMMANDS
1
1
1
0
0
1
0
x
x
1
x
x
0
x
1
1
1
1/0
IDLE
Single
Bus Mode
10B=High
RESB=Low
x
x
x
x
x
x
,
x
x
x
x
x
x
x
NOTE:
x = Multi-Master System Bus is allowed to be Surrendered.
Mode
Pin
Strapping
Multi-Master System Bus
Requested**
Surrendered"
HLT + TI.CBRO+HPBRO***
Single Bus
Multi-Master Mode
10B=High
RESB=Low
RESB Mode Only
10B=High
SYSB/RESB=High.
RESB=High ACTIVE STATUS
(SYSB/RESB=Low+ TI).
CRBO+HLT +HPBRO
lOB Mode Only
10B=Low
RESB=Low
(lID Status+ TI).CBRO+
lOB Mode.RESB Mode
10B=Low
(Memory Command)RESB=High (SYSB/RESB = High)
Whenever the processor's
status lines go active
Memory Commands
HLT+HPBRO
((I/O Status Commands)+
SYSB/RESB=LQW)).CBRO
+HPBRO**'+HLT
NOTES:
'LOCK prevents surrender of Bus to any other arbiter, CROLCK prevents surrender of Bus to any lower
priority arbiter.
'*Except for HALT and Passive or IDLE Status.
***HPBRO, Higher priority Bus request or BPRN = 1.
1. lOB Active Low.
4. TI=Processor Idle Status S2, ST, SO= 111
2. RESB Active High.
5. HLT=Processor Halt Status S2, ST, SO=011
3. +is read as "OR" and.as "AND".
500
SAB 8289
Absolute Maximum Ratings*
Ambient Temperature Under Bias 0 to 70°C
Storage Temperature
--£5 to 150°C
All Output and Supply Voltages -0.5 to 7 V
All Input Voltages
-1.0 to 5.5 V
Power Dissipation
1.5 Watt
D.C. Characteristics
TA = 0 to 70°C. VCC = 5 V
Symbol
Parameter
± 10%
Limit Values
Min.
Max.
Unit
Test Condition
VC
Input Clamp Voltage
-1.0
V
VCC=4.5 V./C= -5 mA
IF
Input Forward Current
-0.5
mA
VCC=5.5 V. VF=0.45 V
IR
Reverse Input Leakage Current
p.A
VCC=5.5 V. VR=5.5 V
VOL
Output Low Voltage
BUSY. CBRO
AEN
BPRO. BREO
V
IOL=20 mA
IOL=16 mA
IOL=10 mA
VOH
-
0.45
Output High Voltage
BUSY. CBRO
All Other Outputs
ICC
Power Supply Current
V1L
Input Low Voltage
V1H
Input High Voltage
Cin Status
Input Capacitance
Cin (Others)
Input Capacitance
'
60
Open Collector
2.4
-
V
-
165
mA
0.8
2.0
-
-
25
12
V
IOH=400 p.A
-
pF
*1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for extended perods may affect device
reliability.
501
SAB8289
A.C. Characteristics
TA=O to 70°C, VCC=5
v ± 10%
Timing Requirements
Limit Values
Symbol
Parameter
TClCl
ClK Cycle Period
125
TClCH
-
ClK low Time
TCHCl
ClK High Time
-
TSVCH
Status Active-Setup
65
TSHCL
Status Inactive-Setup
50
THVCH
Status Active Hold
THVCL
Status Inactive Hold
SAB 8289
Min,
65
SAB8289-1
Min,
Max.
Busy! LSetup to BCLKL
TCBSBL
CBRQ! lSetup to BCLKl
TBLBL
BCLK Cycle Time
-
53
-
tClCl-l0
55
45
20
100
TCLLL 1
LOCK Inactive Hold
10
10
TCLLL2
LOCK Active Setup
40
40
BPRNL ito BCLK Setup Time 15
SYSB/RESB Setup
T::l.SR2
SYSB/RESB Hold
20
Initialization Pulse Width
3TBLBL+
3TCLCL
-----
TNIH
TILiH
Input Rise Time
TIHIL
Input Fall Time
!
15
-
0
-
-
ns
100
0,65
30
[TBLBL]
BCLK High Time
TCLSRl
TCLCL-l0
-
-
20
TPNBL
-
10
TBHCL
-
Max,
35
10
30
Test Condition
100
35
TBYSBL
Unit
0,65
[TBLBL]
-
0
20
3TBLBL+
3TCLCL
20
-
12
20
From 0,8 to 2,0 V
12
From 2,0 to 0,8 V
LDenotes the spec applies to both transitions of the signal.
A,C. Testing Input/Output Waveform
Input/Output
0:: ~ -Test
pOlnts-1L
A.C, Testing: Inputs are driven at 2,4 V for a logic" 1" and 0,45 V for a logic "0': The clock is driven
at 4,3 V and 0,25 V, Timing measurements are made at 1,5 V for both a logic "1" and "0':
502
SAB 8289
Timing Responses
Symbol
Parameter
Limit Values
Min.
Max.
r
TBLBRL
BCLK to BREO Delay L
35
TBLPOH
BCLK to BPROL j')
40
TPNPO
BPRNL to BPROL Delay'l
r
r
Unit
-
25
TBLBYL
BCLK to BUSY Low
60
TBLBYH
BCLK to BUSY Fioat'l
35
-
65
Test Condition
-
TCLAEH
CLK to AEN High
TBLAEL
BCLK to AEN Low
ns
TBLCBL
BCLK to CBRO Low
60
TBLCRH
BCLK to CBRO Fioat'l
35
TOLOH
Output Rise Time
20
From 0.8 to 2.0 V
TOHOL
Output Fall Time
12
From 2.0 to 0.8 V
40
Lr Denotes the spec applies to both transitions ofthe signal.
NOTES:
11 BCLK generates the first BPRO wherein subsequent BPRO changes lower in the chain are generated
through BPRON.
'I Measured at 0.5 V above GND.
A.C. Testing Load Circuit
Device
Under
Test
1
CL='OOpF
CL = 100 pF
CL Includes jig capacitance
503
SAB 8289
State
Waveforms
-T4
T1-
Tl i -TlT-T4!
rr~H j
!
I
[LK
THV[H
SYSB/RESB
Processor CLK Related
Bus CLK Related
BPRN#l
----t----t---,
IBPRO#1J
BPRO#l
IBPRN#3)
NOTES:
1. LOCK active can occur during any state, as long as the relationships shown above with respect to the
CLK are maintained.
LOCK inactive has not critical time and can be asynchronous.
CRQLCK has no critical timing and is considered an asynchronous input signal.
2. Glitching of SYSB/RESB pin is permitted during this time. After I 2 of T1, and before I 1 of T4, SYSB/RESB
should be stable.
3. AEN leading edge is related to BCLK, trailing edge to CLK. The trailing edge of AEN occurs after bus
priority is lost.
504
SAB 8289
Additional Notes:
The signals related to ClK are typical processor signals, and do not relate to the depicted sequence of
events of the signals referenced to BClK. The signals shown related to the BClK represent a
hypothetical sequence of events for illustration. Assume 3 bus arbiters of priorities 1, 2 and 3 configured
in serial priority resolving scheme as shown in Figure 6. Assume arbiter has the bus and is holding
busy low. Arbiter # 2 detects its processor wants the bus and pulls low BREO#2. If BPRN # 2 is high (as
shown). arbiter #2 will pull low CBRO line. CBRO signals to the higher priority arbiter # 1 that a lower
priority arbiter wants the bus. [A higher priority arbiter would be granted BPRN when it makes the bus
request rather than having to wait for another arbiter to release the bus through CBRO]. ** Arbiter # 1
will relinquish the multi-master system bus when it enters a state not requiring it (see Table 1). by
lowering its BPRO#1 (tied to BPRN#2) and releasing BUSY. Arbiter #2 now sees that it has priority
from BPRN #2 being low and releases CBRO. As soon as BUSY signifies the bus is available (high),
arbiter #2 pulls BUSY low on next falling edge of BClK. Note that if arbiter #2 didn't want the bus at
the time it received priority, it would pass priority to the next lower priority arbiter by lowering its
BPRO#2 [TPNPO].
"Note that even a higher priority arbiter which is acquiring the bus through BPRN will momentarily
drop CBRO until it has acquired the bus.
505
SAB82258
ADMA-Advanced DMA Controller
for 16 bit Microcomputer Systems
• 16 bit DMA Controller for
16 bit Family Processors
SAB 80286
SAB 8086/88
SAB 80186/188
• 4 Independent Channels
• 16 Mbyte Addressing Range
• 16 M byte Byte Cou nt
• Memory Based Communication with CPU
III "On-the-Fly" Compare, Translate
and Verify Operations
Figure 1
Pin Configuration (Pad View, 286 mode)
• Transfer Rates up to
8 Mbyte/sec
• Single and Double Cycle
Transfer
.
• Automatic Chaining of Command Blocks
• Automatic Chaining of Data Blocks
CD Multiplexor Mode Operation with
32 Subchannels
" Local and Remote (Stand Alone) Mode of
Operation
Figure 2
Function Symbol
_~N~~~~~~~~~~~~~~
««««>««««
"
A.23 .. ,AB
U ... AI
OR,EOl
OREOII
IlllTI
om-!
EO;Dl
r
1
~
,,,
01S... DI
SAD
~ liA2BSmlla./
82258
Illll1
iiIT
",'''
51
n
HOLD
HlOA
-OS
Pm No lHa.rk
1m
--··-WIi
,~~~~u~~",
'" '"
SAB 82258 is an advanced DMA (Direct Memory
Access) Controller designed especially for the 16 bit
microprocessors SAB 80286 and SAB 8086/1861
88/188. In addition, the operation with other processors is supported by the remote mode. It has
4 independent DMA channels which can transfer
data at rates up to 8 Mbytes/secono at 8 MHz
clock in a SAB 80286 system or up to 4 Mbytesl
second at 8 MHz in a 8086/80186 system. This great
bandwidth allows the user to handle very fast data
transferor a large number of concurrent peripherals.
The device is fabricated in advanced +5 Volt
N-channel Siemens MYMOS technology and
packaged in a 68 pin package.
AG 2/85
507
SAB82258
Modes of Operation, Adaptive Bus Interface
SAB 82258 has been defi ned to work with all 16 bit
processors, i.e. SAB 80286, SAB 801861188
and SAB 8086/88 without additional support and
interface logic. Hence the local busses of above
processors are different in signals, functions
and timings, SAB 82258 has an adaptive bus
interface to meet the different requirements of
these local busses.
Figure 3
Figure 4
Function Symbol in 186 Mode
Function Symbol in Remote Mode
cr
ReSET SltAO¥ ~R[.OI
elK
Inn
~I.O~
~
____ --" A191S~
F,omSA8BC186
r
-'/A16IS3
!
~:~5:::~
-'23."A8
A7 .A'
DREQ3
CREOa
t 8~~:8
PACK 3
nim (..:
-
"""
Bus
d::(ln186modIJ
•
J
< .-----~:~ 'A01S
015.,oe
ADO
---R
-= ~E
-ALE
-OT/R
-bEN
- HOtD
fiLDA
As a result ofthis, a bus compatibility with identical
timing is attained with processors SAB 80286,
SAB 80186 and SAB 8086. A compatibility with
the 8 bit bus versions of these processors SAB 8088
and SAB 80188 is also guaranteed by defining the
508
,
i
~(in
SAB
BmB
remot.mod,l
-BIrr
.--n...
-BRn
-HOlD
- HlCA
physical bus width of SAB 82258 (per software)
as 8 bits. The only difference in operation with
SAB 8086 or SAB 80186 is that for SAB 8086 the
HOLD pin functions as RLl/GT line (if HLDA is held
high on RESET).
SAB 82258
Figure 5
Mode Selection
Pin
A2JIAREADY
=,
=0
'"
RESET
HLD.A:
l:~~ET =,
~
~
:
BUI Width
:
~i1~
~~
SAB 82258 can also operate in a remote or stand
alone mode where it is not coupled directly to a
processor. Figure 5 shows the way how SAB 82258
detects with which processor or in which mode it
is operating. Figure 2 shows the logic pinning in
the 286 mode - for operation with SAB 80286.
Figure 3 shows the logic pinning in the 186 modefor operation with SAB 80186/188 and SAB 8086188,
and Figure 4 shows the pinning when SAB 82258
is in the remote mode and not directly coupled to a
processor.
Pin Definitions and Functions
The pins of SAB 82258 have different meaning for
each of the 4 modes of bus operation. The pinning
in 286 mode and remote mode as well as 186 and
8086 mode are very similar. Table 1 summarizes the
pinning of SAB 82258 in the various modes, the
following sections give a detailed description of
the pin function in each of the modes.
509
SAB 82258
Table 1 Pin Name and Function
286 mode
Pin No.
Remote mode
186/8086 mode
Designation
Input/
Output
Designation
Input!
Output
Designation
Input!
Output
16
HOLD
0
HOLD
0
17
HLDA
I
HLDA
I
HOLD or
RQ/GT
HLDA
0(186)
I/O (8086)
I
SHE
I/O
SHE
I/O
SHE
I/O
14
11
13
8
2
3
10
1
M/io
Sf
0
I/O
I/O
I
I
I
I
SREL
0
0
S2
0
I/O
I/O
I
I/O
I/O
I
59
58
57
56
55
54
53
52
A23
A22
A21
A20
A19
A18
A17
A16
51
50
49
48
47
46
45
44
42
41
40
39
38
37
36
35
A15
A14
A13
A12
A11
A10
AS
A8
A7
A6
A5
A4
A3
A2
A1
AO
510
SO
CS
RD
WR
READY
0
0
0
0
0
0
Sf
SO
CS
RD
WR
READY
0
A23
A22
A21
A20
A1S
A18
A17
A16
0
0
0
0
0
0
0
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
AO
a
a
I
I
I
I
0
0
0
0
0
0
Sf
SO
CS
RD
WR
SREADY
0
AREADY
ALE
DT/R"
DEN
A 19/56
A18/S5
A17/S4
A16/S3
0
0
0
0
0
0
0
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A15
A14
A13
A12
A11
A10
AS
A8
A7
A6
A5
A4
A3
A2
A1
AO
a
I
0
0
0
0
0
a
a
0
0
0
a
0
a
a
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SAB 82258
286 mode
Pin No.
186/8086 mode
Remote mode
Designation
Input/
Output
Designation
Input!
Output
Designation
Input!
Output
18
20
22
24
27
29
31
33
19
21
23
25
28
30
32
34
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
ADO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
6
5
4
61
62
63
64
65
66
67
68
15
12
9,43
26,60
DREOO
DRE01
DRE02
DRE03
DACKO
DACK1
DACK2
DACK3
EODO
EOD1
EOD2
EOD3
RESET
ClK
VSS
VCC
I
I
I
I
DREOO
DRE01
DRE02
DREQ3
DACKO
DACK1
DACK2
DACK3
EODO
EOD1
EOD2
EOD3
RESET
ClK
VSS
VCC
I
I
I
I
DREOO
DRE01
DRE02
DRE03
DACKO
DACK1
DACK2
DACK3
EODO
EOD1
EOD2
EOD3
RESET
ClK
VSS
I
I
I
I
0
0
0
0
I/O
I/O
I/O
I/O
I
I
(Ground)
(Power
Supply)
0
0
0
0
I/O
I/O
I/O
I/O
I
I
(Ground)
(Power
Supply)
vce
0
0
0
0
I/O
I/O
I/O
I/O
I
I
(Ground)
(power
Supply)
511
SAB82258
Pinning in 286 Mode
In the 286 mode the SAB 82258 bus signals and
bus timings are the same as of the SAB 80286
processor. Additional features of SAB 82258
require a slight change in pin definitions. The
processor can access internal registers of the
SAB 82258. Therefore the bus signals must
support these accesses. This means that some
ofthe bus control signals must be bidirectional
and some additional bus control signals are
necessary. All pins and their functions are listed
below.
Figure 6
Pin Configuration in 286 Mode
PC Board View - As viewed
from the component side of
the pc board
Component Pad View - As viewed
from underside of component
when mounted on the board
.~N~~~~~~e~~~~~~~
~~~~~~~ro~~~~~~N~G
~«««<>««««
~~~~~4~~>~~~~~~~~
"
ILJL JLJLJ L J LJL.JLJLJLJLJLJLJ LJLJLJ t~
A16
A17
A 18
A19
A20
~~i
rmJ
J
J
[
09
02
[
0"
[
J
Fj
E ~~o
[ vee
J
DAm F~
~ FJ
~ ~~2
[
os
~
J
to1J0 J
EODT J
E002
E003
J
J
[DB
[ 06
[ 014
[is 015
'1',lr 1r l r l r , r l r l r l i l r l r l r l r lrlrlrl
512
D0
08
01
vee J
A23
Pin No.1 Mark
[
[
[
[
07
SAB 82258
Table 2
Pin Description for 286 Mode
(Contains also the description for pins identical in all modes I
Symbol
Number
Input (II
Output (01
Functions
BHE
1
1/0
Bus High Enable indicates transfer of data on the upper
byte ofthe data bus, D15-8. Eight-bit oriented devices
assigned to the upper byte ofthe data bus would normally
use BHE to condition chip select functions. BHE is active
LOW and floats to 3-state OFF when the SAB 82258 does
not own the bus.
BHE and AO encodings
BHE
AO
Function
0
0
0
1
1
0
1
1
Word transfer (D15-01
Byte transfer on upper half
of data bus (D15-81
Byte transfer on lower half
of data bus (D7 -01
Odd addressed byte on 8 bit
bus (D7-01
RD
2
I
Read command in conjunction with chip select enables
reading out of SAB 82258 register which is addressed by
the address lines A7-AO. This signal can be asynchronous
to SAB 82258 clock.
WR
3
I
Write command is used for writing into SAB 82258
registers. This signal can be asynchronous to SAB 82258
clock.
DREQODREQ3
4-7
I
DMA request input signals are used for synchronized
DMA transfers. DREQ3 has the meaning of 1/0 request
(IOREQI if channel3 is a multiplexer channel. These
signals can be asynchronous to SAB 82258 clock.
CS
8
I
Chip select is used to enable the access of a processor to
SAB 82258 registers. This access is additionally controlled
either by bus status signals or by the Read or Write
command signals. Chip select can be asynchronous to
SAB 82258 clock.
READY
10
I
Bus Ready terminates a bus cycle. Bus cycles are
extended without limit until terminated by READY LOW.
READY is an active LOW synchronous input requiring
setup and hold times relative to the system clock be met
for correct operation.
513
SAB 82258
Symbol
Number
Input (I)
Output (0)
Functions
sO,Sf
11, 13
I/O
The bus status signals control the support circuits.
The beginning of a bus cycle is indicated by Sf or SO or
both going active. The termination of a bus cycle is
indicated by all status signals going inactive in 186 mode
or bus ready signal (READY) going active in 286 mode.
The type of bus cycle is indicated by SO, S1 and S2
(in 186 mode) or M/TO (in 286 mode). S2 and M/TO have
the same meaning but in 186 mode the S2 signal can be
active only when at least one of Sf or SO is active,
whereas in 286 mode the M/TO signal is valid with the
address on the address lines. SAB 82258 can generate the
following bus cycles by activating the status signals
(and M/TO in 286 mode):
M/TO Sf
orS2
SO
Cycle Type
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
1
0
Read I/O-Vector
(for Multiplexor channel)
Read from 1/0 Space
Write into 1/0 Space
No bus cycle, does not occur
in 186 mode
Does not occu r
Read from Memory Space
Write into Memory Space
No bus cycle
1
1
1
When SAB 82258 is not the master of the local bus the
status signals are used as inputs for detection of
synchronous accesses to SAB 82258. The following
table shows the bus status and CS, signals and their
interpretation by SAB 82258.
CS
SO
Description
Sf
1
X
X
0
0
0
0
0
0
1
0
0
1
1
1
SAB 82258 is not
selected
no SAB 82258 access
Read from an
SAB 82258 register
Write into an
SAB 82258 register
No bus cycle
(no action)
(no action)
(Note 1)
Note 1: SAB 82258 is selected but no synchronous
access is activated. In this case SAB 82258
monitors RD and WR signals for detection of an
asynchronous access.
ClK
514
12
I
This clock provides the fundamental timing. It must be
two times the system clock. It can be directly connected to
the SAB 82284 ClK output. It is divided by two to generate
the SAB 82258 internal clock. The on chip divide-by-two
circuitry can be synchronized to the external clock
generator by a lOW to HIGH transition on the RESET
input, or by first HIGH to lOW transition on the Status
Inputs SO or Sf after RESET.
SAB 82258
Symbol
Number
Input (I)
Output (0)
M/IO
14
0
Distinction between memory and I/O space addresses.
RESET
15
I
An activation of the reset signal forces SAB 82258 to the
initial state. The reset signal must be synchronous to ClK.
HOLD
16
0
HOLD output, when true, indicates a request for control
of the local bus. When the SAB 82258 relinquishes the
bus it drops the HOLD output.
HlDA
17
I
HlDA. when true, indicates that the SAB 82258 can
acquire the control ofthe bus. When it goes low SAB 82258
must relinguish the bus at the end of its current cycle.
It can be asynchronous to the SAB 82258 clock.
00-015
18-25,
27-34
I/O
Data Bus - This is the bidirectional 16 bit data bus.
For use with an 8 bit bus, only the lower 8 data lines
D7-DO are relevant.
AO-A7
35-42
I/O
The lower 8 address lines for DMA transfers. They are also
used to input the register address when the processor
accesses a SAB 82258 register.
A8-A23
44-59
0
Higher address outputs.
DACKODACK3
61-64
0
The DACKi Signal acknowledges the requests on the
related DREQi signal. It is activated when the requested
transfer(s) is (are) performed. If the channel 3 is a
multiplexor channel the signal DACK3 has the meaning
of I/O acknowledge (lOACK).
EODOEOD3
65-68
I/O
The End of DMA Signals are implemented as open drain
output drivers with a high impedance pull up resistor and
thus can be used as bidirectional lines.
As outputs the signals are activated for two system clock
cycles atthe end of the DMA transfer of the corresponding
channel (if enabled) or they are activated under program
control (EOD output or interrupt output).
If the signals are held internally high but forced to low by
external circuitry, they act as "End-of-DMA" inputs. The
current transfer is aborted and SAB 82258 continues
with the next command.
Additionally, a special function is possible with the EOD2
pin: this pin can also be used as common interrupt signal
for all4 channels. In this mode this signal is not a open
drain output but a push pull output (output only). The other
EOD pins may be used as EOD outputs/inputs described
above.
VCC
26,60
Power supply (5 V)
VSS
9,43
Ground (OV)
Functions
515
SAB 82258
Pinning in 186 Mode
In 186 mode many pins have a different meaning
than in the 286 mode. They are listed below (for
corresponding 286 names see table 1).
Figure 7
Pin Configuration in 186 Mode
Component Pad View - As viewed
from underside of component
when mounted on the board
PC Board View - As viewed
from the component side of
the pc board
_ _ N~4~~~~~~~~~~~~
~~~~~~~~~~~~~mN~_
««««>««««
«~««<>««««
~
II II II
II
II II
dLJLJLJLJ LJLJL JLJLJLJLJLJLJ LJLJ LJ~~
S3/A 16
S4/A17
SS/A18
S6/A19
om
OTiR'
ALE
AREADY
siJ
[
J
[
AD0
ADS
AD1
AD9
A02
AOtO
AD 3
[
AD 11
J
J
J
J
[
[
[
[
~
~ ~
E ~~[4
~ ~
~ ~~;3
AD6
0AlKT
J
[
~~~; ~
EOD3
516
~
A012
~
t.uu,.
Pin No.1 Mark
[
J
~ ~~;4
r'! 1r 1,1 r 1 r 11' rlrl r 111 rlrl r
~!
1 r 1r 1r 1 r 1
~
8888 ~~ ~ ~g~
~i~gggg~~ffi~~~~~~~
AOtS
SAB 82258
Table 3
Changes of Pin Description in 186 mode
Symbol
Number
Input (I)
Output (0)
Functions
RD
WR
2,3
1/0
In 186 mode, the RD and WR pins are additionally used
as output pins to support 80186 or 8086 minimum mode
systems.
ALE
58
0
Address latch enable signal provides a strobe to separate
the address information on the multiplexed AD lines.
DEN
56
0
Data enable signal is used for enabling the data
transceiver.
DT/R
57
0
Data transmitlreceive signal controls the direction of the
data transceivers. When lOW, data is transferred to the
SAB 82258, when HIGH the ADMA places data on to the
data bus.
S2
14
0
Status signal as for SAB 186/8086/88 processors
(see also 51, SO description in 286 mode).
AREADY
59
I
This is an asynchronous bus ready signal, the rising edge
is internally synchronized, the falling edge must be
synchronous to ClK. During reset this signal must be
low for entering the 186 mode.
SREADY
10
I
Synchronous ready input. This signal must be synchronized externally. The use ofthis pin permits a relaxed
system-timing specification by eliminating the clock
phase which is required for resolving the signal level
when using the AREADY input.
ClK
12
I
This is the input for the one time system clock.
No internal prescaling is done.
ADOAD15
18-25
27-34
1/0
AO-A7
A8-A15
35-42
44-51
1/0
0
lower address and data information is multiplexed on
pin ADO-AD15. Additionally the demultiplexed address
information is available on address pin AO-A 15.
A16/S3A 19/56
52,55
0
The higher address bits are multiplexed with additional
status information.
517
SAB 82258
Pinning in 8086 Mode
In 8086 mode the bus arbitration is done via RQ/GT
protocol instead ofthe HOLD/HLDA protocol in 186
mode. The function of the other pins is identical to
186 mode.
Figure 8
Pin Configuration in 8086 Mode
Component Pad View - As viewed
from underside of component
when mounted on the board
"' ~UL
"'"'"'
_II
~
ADI
ADS
AD'
AD9
AD'
AD10
"
i=
53JA 16
S4/A 17
551 A 18
561 A 19
DEN
A16/S3
A17JS4
A1B/55
A19/S6
DEN
LJ
i=
ADl
AD1,
vee
oTiR"
A014
"
rr
Is
&._
ALE
AREADY
ilACKl
DATi««<444
~~~~~~~~>~~~~<~«
"
00
08
01
09
02
010
OJ
011
[J
vee
04
012
OS
013
06
014
01
01S
"
vee
vee
822)13
0AfK!'
DAIKl
DAIRl
DAITT
=
DACK 2
!JACK]
fIj()j
"
$_
A16
A11
A 18
A 19
A20
A21
A22
A23
"6
A11
A18
A19
A20
A21
A22
All
DACK 3
EOlfj
ETIDI
E50T
EDD 2
ftTIf]
EOO2
[003
N,..,
~~~~~~13~1~
Pm No 1Mark
sQ
LJLJLJ LJ L -.lLJL-.l LJLJ LJLJLJL.J LJULJt!~
L
J
!
.~
011
vee
~
~
04
012
OS
013
06
014
[' 07
[Je 01S
~
r, ,r',l,l,'" il,l,' ' l o l i l ' 1r lrlr,r,
mN_=
Ir
~
~
8888 ~~ ~ ~~g~
~F~mmmm~~~r~rm~o~
~~
DoaDu>~~w~m~~~
Table 5
Changes of Pin Description in Remote Mode
Symbol
Number
Input (I)
Output (0)
Functions
BREL
14
0
In this mode pin 14 is used to indicate when SAB 82258
has released the control of the local bus.
es
8
I
In Remote Mode the
input has two functions: besides
enabling the access to SAB 82258 internal registers it works
as an Access Request input. When forced to low it signals
the SAB 82258 that another bus master needs access to
the local bus of the SAB 82258 (e.g. to read/write SAB 8225 8
registers). SAB 82258 releases the bus as soon as possibl e
and indicates this by activating the BREL output.
HOLD
HLDA
16
17
0
I
Signals on these pins are only used for access to the
system bus. They are connected to the bus arbiter.
Resident bus accesses are directly executed (without
HOLD/HLDA sequence).
es
519
SAB 82258
Functional Description
General
SAB 82258 is an advanced general purpose DMA
controller especially tailored for efficient high speed
data transfers on a SAB 80286 as well as an
SAB 801861188 or SAB 8086/88 bus.
It supports two basic operating modes:
-local mode (tightly coupled to a processor) and
- remote mode (loosely coupled to a processor).
In the first case SAB 82258 is directly coupled to the
CPU and uses the same system support/control
devices as the CPU (see figure 10a). This mode is
possible with the above mentioned processors.
As a second basic operating mode a remote
(stand alone) mode is supported (see fig. 10b).
Here the SAB82258 has his own sets of bus interface
circuits and thus can dispose of its own local bus.
This allows the DMA-controller to work in parallel
to the main CPU and therefore overall system
performance could be increased. Besides that, this
mode is very useful for the design of modular
systems and allows connecting the ADMA to any
other processor via the system bus independent of
the processor's unique local bus.
Figure 10
Basic ADMA Operating Modes
b) Remote Mode
a) Local Mode
SAO
80286
S
Y
S
T
E
M
DACK 0-3
DREO 0-3
520
OREO
0-3
DACK
0-3
SAB 82258
SAB 82258 has four independent DMA channels
that can transfer up to 8 Mbytes/sec in the single
cycle mode (2 clocks/tra nsfer).ln the 2 cycle transfer
mode the maximum rate is 4 Mbytes/sec.
Switching between channels induces no time
penalty. Thus the overall maximum transfer rate of
8 Mbytes/sec is also valid for multiple channel
operation.
This fast operation is possible because of the
pipelined architecture of the SAB 82258 that allows
the different function units to work in parallel.
Figure 11
Block diagram of SAB 82258
Addr.
Channel
Control
Signals
Data
,,,
The ADMA supports two address spaces, memory
space and I/O space, each with a maximum address
range of 16 Mbytes. In addition, the maximum
block length (byte count) is also 16 Mbytesto
support applications where large blocks of data
have to be transferred (e.g. graphics).
521
SAB 82258
As source or as destination, four parameters can be
independently selected:
- Address Space (memory or 110)
- Physical Bus Width (8 bit or 16 bit),
- Logical Bus Width (same as physical bus width or
8 bit on a 16 bit physical bus)
and
- Transfer Direction (increasing, decreasing, fixed
pointer or constant value).
If the physical bus width of source or destination
does not meet the logical bus width an automatic
byte/word assembly (word/byte disassembly)
takes place ifthis minimizes the necessary transfers.
The same is true if the logical bus widths of source
and destination are different.
Transfers between different address spaces can be
performed within one cycle or in two cycles,
transfers within one address space can be performed only in two cycles.
The transfers can be executed free running or
externally synchronized via DRO where source or
destination synchronization is possible.
In summary, this very symmetrical operation of
SAB 82258 gives the user a great amount of design
flexibility.
Adaptive-Bus Interface
As shown in figure 5 the SAB 82258 bus interface
has two basic timing modes: the 286 mode and the
186 mode. In 286 mode SAB 82258 is directly
coupled to an SAB 80286, in 186 mode to an
SAB 80186 or SAB 80188. For each ofthese two
modes a slightly different variation exists:
522
- For the 286 mode, the Remote Mode, where the
ADMA operates as a bus master on the system
bus without being directly coupled to a processor.
In this mode SAB 82258 can dispose of its own
local bus and the communication with the main
processor is done via the system bus. To enable
access to ADMA registers by the main processor,
SAB 82258 must release its local bus. This "local
bus arbitration" in remote mode is done via the
CS and BREL lines.
- For the 186 mode the variation is the 8086 mode
where the SAB 82258 supports the RO/GT
protocol and thus can be directly coupled to a!1
SAB 8086 or SAB 8088.
Memory Based Communication
The normal communication between the ADMA and
the processor is memory based. This means that all
necessary data for a transfer is contained in a
command block in memory accessible for CPU and
SAB 82258 (see figure 12). To start the transfer the
CPU loads one of the command pointer registers of
SAB 82258 with the address of the command block
and then gives a "start channel command". Getting
the command SAB 82258 loads the entire command
block from memory into its on-chip channel
registers and executes it. On completing the
operation, channel status information is written
back by SAB 82258 into the channel status word
contained in the command block in memory. If
desired the actual contents of the channel registers,
i.e. source pointer, destination pointer and byte
count is transferred into the Channel Status Block.
The Channel Status Block immediately follows the
Command Block in memory (see figure 12).
SAB 82258
Figure 12
Memory Based Communication and Command Chaining
Memory Based Communication
~~ipb
"''--_--=C.:::om'''m':::'':..:''''o'''''lo'-'_ _-"al\
Higher Addrus!lower Address
I=l
I
In Memory
Incleasingl
Address
Command Chaining
(I=l
~
~
1
~
~
3) Simplest DMA Operation
b) Auto-reload DMA
I_
\ Wlltten alt.r ~yerv
T F"'c~om~m~,"~'~""'I,"~"O~'~' DMA termination
I
DMA
#1
Compare
lUMPil*con
__________ drtioo' met
DMA
Written after OMA
termination
poonter
II ENST=l
In command eltenslon.
#3
DMA
Command Block
Q!
byte counlend
I
STOP
STOP
C~annel
.,
external terminate
#2
byte
General
·condition- =
mask compareh,1
c) Conditional DMA Operation
Command Chaining
Data Chaining
Command blocks for any channel can be chained for
sequential execution (see figure 12). When
SAB 82258 comes to an end with one command, it
automatically starts to fetch and execute the next
command block until a stop command is found. As a
result a chain of command blocks can be executed
by the ADMA without any CPU intervention. Due to
conditional and unconditional STOP and JUMP
commands, quite complex sequences of DMA can
be executed by SAB 82258.
Data chaining permits an automatic, dynamic
linking of data blocks scattered in memory. There
are two types: list and linked-list data chaining.
Iffor a DMA the source blocks are to be dynamically
linked during DMA it is called source chaining and
the effect is that of gathering data blocks and
sending them out effectively as one block.
If one source block is dynamically broken-up into
multiple destination blocks, it is called destination
chaining. This results in scattering of a block.
.
This dynamic linking and un-linking of data blocks
makes the logical sequencing of data independent
of its physical sequencing in memory.
523
SAB 82258
Figure 13
Data Chaining
a) Linked List Chaining
Com mind Pointer
-----------Typt 1 Conlllllnd
b) List Chaining
Comm'nd Pointer
On Chip
On Chip
In Memory
Type 1 Command
Link Poln'"
Source Pointer
In Memory
Chain list Pointer
linked Lilt
In the case of linked list chaining (see figure 13a)
each data block has a descriptor containing
information on position of data block in memory,
length of data block, and a pointer to the next
description.
During data transfer the data block 1 is sent out first,
then 2 and so on till a 0 is encountered in the byte
count field.
524
The second type of data chaining is List Chaining
(figure 13 b).
Unlike linked list chaining, here the data block
descriptors are continuous in a block and thus
determ i ne the sequence of data blocks. The flexibility lost in terms of predefined sequence is gained
in terms of linking time.
SAB 82258
"On-The-Fly" Operations
A normal DMAcontroller blindly transfers data from
source to destination without looking at the data.
In case of the ADMA on-the-fly operations are
executed during the DMA transfer and allow
inspection and/or operation on the transferred data.
There are three on-the-fly operations possible:
- Mask/Compare,
- Translate and
- Verify
During a mask/compare operation each byte/word
transferred is compared to a given pattern. One or
more bits can be masked and thus do not contribute
to the result of the compare operation. The result
can be used by subsequent conditional stop or jump
operations.
For translate operation the byte (no word possiblel
that is fetched from source is added to a translate
pointer to build the effective source pointer. The
byte pointed to by this pointer is then fetched and
sent out to the destination. Of course a mask/
compare operation is possible on the byte sent out.
The verify operation is a type of block compare
operation to compare each byte/word of data
read from a peripheral with that in a data block in
memory. There are three options:
1. Verify with no termination on mismatch
(2-cycle transfer only)
2. Verify with termination on mismatch (2-cycle
transfer onlyl.
3. Verify and save (single cycle transfer only).
Here an actual transfer with compare takes place.
The transfer is not stopped on mismatch.
MUltiplexer Channel
When programmed to multiplexer mode channel
3 (supported by a multiplexer logicl can be used
to service up to 32 subchannel request lines (see
figure 14). Thus it is ideally suited to service a
large number of relatively slow equipment like
CRT terminals, line printers etc. Since multiple
subchannels are processed with the resource of
one DMA channel, the overhead of subchannel
switchi ng, of cou rse, decreases the total effective
throughput on the multiplexer channel.
Figure 14a
Multiplexer Channel
Ch.O
HOLD
Ch.1
SAD
82258
Ch.2
o
o
upto
32 Request
lines
HLDA T
0
C
Multi -
plexor
IOREa
IOACK
P
U
Ch.3
•
Multiplexor consists of one
or more SAB 8259 A
(Interrupt Controller)
525
I
SAB 82258
Figure 14b)
Structure of MUltiplexer Table
I
Multiplexor Table Pointer
On Chip
equests from Devices
~
IIII
I
SA8
B259A
Multiplexor Table
I.~!
P"
Subchannel
8 Bit Veclor
(Device Number)
In Memory Subchannel
a
Command Chain
Subch.#O Command
~Pointer
Type 1
Command
Subch.#O Mask
Type 1
Command
~pointel
Subch.# 1 Command
~Pointer
SUbch.# 1 Mask
~pointer
n
Subch.#2 Command
r---Rpointer
Stop and Mask
Intr. Command
Subchannel 1
Command Chain
Type 1
Type 2
Type 1
Subch.#2 Mask
SlOp and Mask
Rpointer
Intr. Command
~
Type 1
Type 1
Type 1
SlOp and Mask
Intr. Command
The mask pointer is the
address of the appropriate
SAB 8259A mask register.
526
SAB 82258
Operating the SAB 82258
Reset
When activating the reset input. SAB 82258 is forced
into its initial state. All channels and bus activities
are stopped, tristate lines are tristated and the
others enter the inactive state.
While the reset input is active line A23/ AREADY and
HLDA must be forced to the appropriate levels to
select the desired bus interface mode (see figures 5
and 36).
After deactivating reset the inactive state is maintained, in addition the state of SAB 82258 registers
is as follows:
- General Mode Register, General Burst Register,
General Delay Register, General Status Regisier
and the four Channel Status Registers are set to
zero,
- the Vector Not Valid bit of the Multiplexer
Interrupt Vector Register is set to 1,
- all other registers and bits are undefined.
Note that the General Mode Register (GMR) should
be loaded first to select the mode of operation
before any other activity is started on the ADM A.
DMA Interface
The DMA interface consists of three lines:
• DRQ - DMA request,
• DACK - DMA acknowledge and
• EOD - end of DMA
The first two lines work as request and acknowledge
lines to control synchronized DMA transfers as
known from conventional DMA controllers.
A special feature of SAB 82258 are the bidirectional
EOD lines. First they can be used as inputs to
receive an asynchronous external terminate signal
to terminate a running DMA. Second, as an output,
they can be used to send out a pulse which interrupts
the CPU and/or signals to the peripheral a specific
status (e.g. transfer aborted or end of a block or
send/receive next block ... ).
The EOD output signal can be generated synchronously to a transfer (during the last transfer) or
asynchronously to the transfers by a specific
command.
In addition the EOD output of channel 2 can be used
as a collective interrupt output for all DMA channels
while the other three retain their normal function.
Slave Interface
The slave interface is used to access SAB 82258
internal registers. Although nearly all of the
communication between CPU and ADMA is done
via memory based data blocks, some direct
accesses to ADMA registers are necessary. For
example during the initialization phase the general
mode registers must be written, or to start a channel.
the command pointer register and the general
command register must be loaded. Also during the
debugging phase it is of great benefitto have access
to all of the SAB 82258 internal registers.
The slave interface is enabled by the CS input and
consists of the following lines:
•
•
•
•
•
SO, ~
RD, WR
AO-A7
DO- 015
ADO-AD15 -
Status Lines (inputs)
Control Lines (inputs)
Register Address (inputs)
Data Lines (inputs/outputs) and
Address/Data Lines (inputs/outputs)
for synchronous access in 186 mode
Note, that all of these lines are outputs if SAB 82258
is an active bus master.
In 186 mode and 286 mode two types of accesses
are possible:
- Synchronous access by means of the status lines.
Processor and SAB 82258 are directly coupled
and must use the same clock,
- Asynchronous access by using the control lines
RD and WR (processor and ADMA may have
different clocks).
In all modes except the synchronous access in 186
mode the register address must be supplied on
address pins AO-A7. Using synchronous access
in 186 mode the address information is expected
at address/data lines ADO-AD7.
In remote mode only the asynchronous access is
possible because SAB 82258 first has to release its
local bus to enable the register access. On receiving an access request (activation of CS input)
SAB 82258 releases its local bus as soon as
possible and signals this by activating the BREL
line. Now the CPU can accomplish its access.
Reg ister Set
Figure 15 shows the user visible registers of
SAB 82258. A set of 5 registers, called the general
registers, is used for all the 4 channels. The mode
register is written first aher reset and it describes
the SAB 82258 environment - bus widths,
priorities etc. The General Command Register
(GCR) is used to start and stop the DMA transfer
on different channels. General Status Register
IGSR) shows the status of all the 4 channels; if
the channel is running, if interrupt is pending etc.
General Burst Register IGBR) and General Delay
Register IGOR) are used to specify the bus load
which is permissible for SAB 82258.
527
I
SAB 82258
There is 'a set of channel registers for each of the
4 channels. Most channel registers serve as cache
registers and need to be accessed only for
debugging. During normal operation they are
automatically loaded by SAB 82258 (see next
paragraph).
The layout of register addresses is shown in figure
16. All register lie at even addresses. Locations not
designated in figure 16 are reserved.
Figure 15
SAB 82258 Register Set
General Registers
o
15
I
GMR I
GSR
Status
Mode
Command
GCR
GBR
GDR
Burst
Delay
o
7
Channel Registers (4 sets; 1 per channel)
o
23
CPR
SPR
Command Pointer
DPR
TTPR
LPR
Destination Pointer
Translate Table Pointer
List Pointer
BCR
Byte Count
Source Pointer
Channel Command
Mask
Compare
CCR
MASKR
COMPR
DAR
15
CSR
Assembly
Channel Status
I
7
0
Multiplexor Channel Registers
0
7
MIVR
528
Interrupt Vector
LVR
Last Vector
SCR
Subchannel
SAB 82258
Figure 16
Layout of Register Addresses
Address Bits
0-5
0
2
4
6
8
A
C
E
10
12
14
16
18
1A
lC
1E
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
3E
GCR
SCR
GSR
GMR
GBR
GDR
CSR
DAR
MASKR
COMPR
Address Bits 7.6
00
GCR
SCR
GSR
10
11
GMR
GBR
GOR
CSR0
OAR0
MASKR"
COMPR"
CSR 1
OAR1
MASKR1
COMPR 1
CSR2
OAR2
MASKR2
COMPR2
CSR 3
OAR 3
MASKR3
COMPR3
MIVR
LVR
CPRL0
CPRH"
SPRL0
SPR H0
OPR Ul
OPR H0
TTPRL0
TTPRH0
LPR L0
LPR H0
CPR L1
CPR H1
SPR L1
SPR H1
OPR L1
OPR H1
TTPR L1
TTPRH1
LPR L1
LPRH1
CPR L2
CPR H2
SPR L2
SPR H2
OPR L2
OPR H2
TTPR L2
TTPRH2
LPR L2
LPR H2
CPRL3
CPR H3
SPR L3
SPR H3
OPR L3
OPR H3
TTPR L3
TTPRH3
LPR L3 /MTPR L
LPRH3/MTPRH
BCRL0
BCR H0
CCRL0
CCRH0
BCRL1
BCR H1
eCRL1
eCR H1
BCR L2
BCR H2
CCR L2
CCR H2
BCRL3
BCR H3
CCRL3
lCR H3
= General Command Register
= Subchannel Register
= General Status Register
General Mode Register
General Burst Register
General Delay Register
Channel Status Register
Data Assembly Register
Mask Register "
= Compare Register
=
=
=
=
=
=
01
MIVR
LVR
CPR
SPR
DPR
TTPR
LPR
MTPR
BCR
CCR
I
= Multiplexor Interrupt Vector Register
= Last Vector Register
= Command Pointer Register
= Source Pointer Register
= Destination Pointer Register
= Translate Table Pointer Register
= List Pointer Register
= Multiplexer Table Pointer Register
= Byte Count Register
= Channel Command Register
529
SAB82258
Register Description
General Mode Register
In the General Mode Register GMR (fiQure 17) the
system wide parameters are specified.
This register should be programmed first after
reset.
Figure 17
General Mode Register (GMR)
rJ _
~
_
')1_
t~(J··m.,~
Cn;)C1r'"l
!'!,.·l.~:pif'-xo"
'::n.0,~,'
Uta .... '"!;l
"'obtin,?,
::".1 fiX~Cl (bl'<"st)
-0 _ C:-.• ),~ t"!)";a+.inq (n1';1'f''' gr,".lp)
V' • .?,3 r,,-t~-:.i""·'l (l(';Wf;" gfO"p)
,) _ fOD2 pin .. EOD.?
1 _ EOD2 pt.-, .. COr!",mo,., I"ter.
530
SAB 82258
General Command Register
Individual channels are started and stopped by a
command written tothe General Command Register
GCR (figure 18), The GCR is directly loaded by
the CPU,
Figure 18
General Command Register (GCR)
000 _
:):11 _
~OP
018 _
01~ _
100 _
10~ _
110 _
11~ _
SH.RT
STt.fl in~di .... cIGtopped, no ,."ql.oec~
(;1-."""111 lnuo.tive/"tcpp<>d, r(>(1\,jG£I~ p(lrl(Ji"lll
:Mn'1el \1'. or(JlI!'lisAtioMl c'-coer.cinl'l
[)Mr, in croqrll~;
.
_ _ _ _ Inter ..... pt 3htu'1
I
r; _ ~o irrtllr"'",pt
, _ Int(lrr .... ot p{lnaina
' - - -___ COfItroj
;iP:lCP LOClltb.,
0_ Cerltrol
SP"'CB
en fl:ES
r.lJS
(remote mode)
or mt-mery b... a (loc~l modC')
1 _ Co"tr"ol S(JIIC(, Of'l S'iS t'L,JS (rrmotll modll)
or I/O ous (local ft1ooc)
" - - - - - -_____ Statln ChM,nel 1
" - - - - - - - - - - - - _ Sh!,I:' Cr:~nnel ::
" - - - - - - - - - - - - - - - - - - - Stll.tUI> CI-.l.H'ln('l 3
533
SAB 82258
The channel commands are contained in the
channel command block (figure 12). Up to 22 bits are
used to specify the command. There are two types
of channel commands:
Type 2 command blocks are 6 bytes long (see
figure 23) of which the first 2 bytes form the
command and the rest is either a relative displacement or an absolute address for the JUMP
operation. There are 2 basic type 2 commands
(figure 23):
• Type 1: for data movement
• Type 2: for command chaining control
a. JUMP - conditional and non-conditional
b. STOP - conditional and non-conditional
The command block for a Type 1 command is in
general 26 bytes long (see figure 12).
The conditional case tests for either of the 4 condition bits which are altered at the termination of
any DMA operation:
Channel Commands
For certain' type 1 transfers which, for example, do
not use "on-the-fly" match, translate or verify
feature, the command is only 16 bits long and only a
short command block is necessary (see figure 12).
The Type 1 command fields (see figures 21 and 22)
contain information on:
a. Bus width of source and destination
b. If source and/or destination address should be
incremented or decremented or kept constant
during the transfer
c. If source/destination is in memory or I/O space
(local mode) or in system or I/O space (remote
mode)
d. If data chaining (list or linked-list) is to be
performed
e. If the data transfer is synchronized (source or
destination)
f. If an "on-the-fly" match operation and/or
translate operation has to be performed
g. If a verify operation has to be performed.
534
•
•
•
•
Termination due to byte count end
Termination due to mask-compare
Termination due to external terminate
Verify operation resulting in mismatch.
It is thus possible to JUMP or STOP further
execution of commands based on any of these
conditions and optionally generate EOD or interrupt
signal.
The combination of type 1 and 2 commands gives
SAB 82258 a high degree of "programmability".
It can thus execute quite complex algorithms with a
fairly low demand for CPU service.
SAB 82258
Figure 21
Type 1 (DMA) Channel Command
15
13
12
11
10
9
67
...I
43210
Destination
1-
Source
I
LC IW/BIINC DECjMhojW1B!INCIDECI~
'-v------"L
Coue", Co""ip'ion SF""
1/0 or rcsiJC'nl
1 _ Mcmory or :;y~,l('m
(l _
:::;'ourcf' Pointer
,l() _ No II~c/DFC
81 _ ore
10 _ INC
11 _ tm puinb.'r ((;ondanl. value)
l -_____
Loqic",l Bus WiJlh
o_
8 bd,
1 _ 16 bil
Dl'!>lincllian Oer.criptiorl
Sam~
Lie
w,
I
~()urc(' del.(~r.
LC
NO dHinin:l
I
o
L'] -
chaining
lLl chaining
not a1 lowed
i~;l
Link,~rj
,";;pl"ct Ch;:nn.inq
D,",ii,.,iion
1 _ Sourcl-'
ror
~'IJX.
rral\~fer'
Channel:
Ch:Jininq
r, _ Tr:lr1!.h·r i~ sync.hroniLI·d
1 _ Tran!;fer not. ~yn"hronil"]d
fnnblr' [Of) Output
Fn"1bll' FxLernal fcrmin.1t(' [nput.
Chanm·l comm<'lnd Blo(:k It'nylh
J _
~}hort
1 - lang
(wilh
cornman::!
xbmsion)
;'ynr.hronilat.ion
L
nn - Tyo'
? "omm,nJ
~,ourCl :;ync.
1(1 _ Df'.Llno.ltion sync.
11 _ No :,yn(;. (rre~ runnin'j)
01 -
For
r~ulliplexor
Ch.1rmel
'')0 _ Type? command
01 - Bylp/II'Qrd multiplex opfratio~1
11) _ ~;inql(' lrant.fcr operation
11 _ Bbrk multiplf'x oppnd.ion
535
SAB 82258
Figure 22
Type 1 Channel Command Extension
7
I
5
I ~ IYRAI
VER
I I
MATCH
'---v---' '---v---'
L
Motch_Co.p",
00 .. Disablod
01 .. ~nable mi!::m.'\tch (Sytc/I'/ord)
10 .. t.ndble hyte mntr.h
1~ .. fl1.,dt> W¢"d matcl·
' - - - -___ '.'cdfy
'JJ .. :~o veri fy
Ci .. Ve"'ify
:n _ Ve"i"y ar·d t,alt (o~ rr:i,:,Mcltch)
11 .. \le"'1 fy flr1:] save
'-----------0_ Trar.slate [nabl e
:J _ T"'ar..sldte disabled
1 .. Trnr.51 atf' enati Cd
' - - - - - - - - - - _ . _ t,'1.;ble 8acl<..;p
c ..
~
536
Upciate ir'l CMn"el cornmilnd block di5abl('d
.. uodah' (''''Clblco
SAB 82258
Figure 23
Type 2 Command Blocks (for command chaining control)
o
15
Type 2 Command
Signed 16- bit Displacement
-Relative JUMP
-0Type 2 Command
24- bit Pointer
-0-
- A-bsolute JUMP
I
Type 2 Command
-0-0-
-Conditional STOP
-Unconditional STOP
-STOP and MASK
for MUX Channel
537
SAB 82258
Figure 24
Type 2 Command Format
15
13
11
10 9
5
o
4
I oI I
0
0
I
3
0
ICondition Code I
IVERIMAI ET IBC I
~
Condi tion Cod,
Byte cOvnt .. 0
ext ... "~I":;' Te"mi:'M.tr:
' - - -___ Byte/we. .\at.Ch
~
lr.ve ... t ~ha"'.nel sti,t.JS bits before
compl'!r ing wi tb ~or()i t'ior, C,JJ.:
Genfl!"'flt.e
roo
p,.lse
STOP and Mt.S'< for Mu/{ C'1linnd
'.11 _ Condido1a: STOP
10 _ Cc,.,diticnaP JUI1.F "da-':lv~
~1 _ Cc"(1itio~,al· JU~1P ,HJ~olute
*) Unconditional JUMP when all condition code bits are set 1.
538
SAB 82258
Channel Status Register
For each channel exists a Channel Status Register
(see figure 251. This register shows the current state
ofthe appropriate channel.
Figure 25
Channel Status Register
7654320
I~~ / / /:'SS'1vERI
FE
H
JDMA Termin.lionl
MAl ET BCJ
I
~
L
Flags set on DMt. termination
Be
- 8yt~ r:o\Jnt er1d
IT - ExCp.!""f'lal ter.,.,il1i1te
MA
_ Mat.ch/mi"mn.t~r.
'oJEK - 'verify operation p.rdil"1.'J i'1
mi~rTHltch
Single step nal t mode
Cha~"el
arerrttiflq
in SSI1 mooe
U"arrnel it"1 hal ted sta't.e
Fatal
er'l"'O'"
L.ast :;ucc.,anne] commr;nd t.rans:"el"'red
i!'i ol"ocebl";ed
*1 Valid only for channel3 in multiplexer mode. In all other cases 0 is returned.
539
SAB 82258
Multiplexer Channel Registers
Multiplexer Interrupt Vector Register
These registers are valid only for channel 3 if programmed as multiplexer channel.
This 8 bit register is read by the CPU to determine
which channels are stopped. The vectors of the
stopped subchannels are output on subsequent
read operations in order of their priority (0 has
highest priority).
Multiplexer Table Pointer Register (MTPR)
This 24 bit register is used to reference the multiplexer table in memory (see figure 14 b). It must be
loaded by the CPU. Physically the List Pointer
Regis~er is used, since data chaining is not allowed
for multiplexer channel.
Figure 26
Multiplexer Interrupt Vector Register (MIVR)
7
6
5 4
NV
o o
0
Vector
\
Subchannel Vector
Vectol" of t.h:-= highGst p"io~~\.y
suochanr'el stOlJped afid r·ot yet read
Non valid
oJ - l/ector" is val io
1 _ Veotor' is ~ot valid
(No ch.nnel stopped or
all "odors read,)
Last Vector Register (LVR)
Timings
This 8 bit register holds the last vector read by
SAB 82258 (from SAB 8259A). In case of a stop
caused by a fatal error on channel3, LVR determines
the failing subchannel.
The bus timings in 286 and Remote mode are
identical to that for SAB 80286, in the 186 and 8086
mode the timings are identical tothatfor SAB 80186.
For exact timings see timing diagrams of
A.C. Characteristics.
Subchannel Register
This 8 bit register must be loaded by the CPU with
the desired subchannel number before a
subchannel command is written into GCR.
540
Asynchronous control inputs are specified wi~h
setup and hold times which are only meaningful to
determine whether the SAB 82258 responds to the
signal in the current cycle or the next cycle.
SAB 82258
Absolute Maximum Ratings 1)
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground
Power Dissipation
oto 70°C
-65to +150°C
- 1 to +7V
3.6W
D.C. Characteristics 2 )
TA = 0 to 70°C; VCC = +5 ±10%
Symbol
Parameter
Min.
Max.
VIL
Input Low Voltage
(except CLK)
-0.5
+0.8
VIH
Input High Voltage
(except CLK)
2.0
VCC+0.5
VOL
Output Low Voltage
-
0.45
VOH
Output High Voltage
2.4
-
ICC
Power Supply Current
III
Input Leakage Current
SO, 51, 52, BHE, RD, WR, MilO
Limit Values
Units
Test Conditions
V
450
10L= 3.0 mA
10H = -400f!A
mA
TA = 25°C,
all outputs open
OV :s VIN :s VCC
-
HOLD (RQ/GT mode), EOD
-200
f!A
-1.5
mA
±10
f!A
other pins
ILO
Output Leakage Current
VCL
Clock Input Low Voltage
-0.5
+0.6
VCH
Clock Input High Voltage
3.8
VCC+l.0
CIN
Capacitance of Inputs
(except CLK)
CO
Capacitance of 1/0 or Outputs
CCLK
Capacitance of CLK Input
1)
2)
0.45V :s VOUT:s VCC
V
-
pF
fc = 1 MHz
10
-
20
12
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Clock must be applied.
541
SAB 82258
A.C. Characteristics
TA = 0 to +70'C; VCC = +5V ±10%
Any output timing is measured at 1.5V.
Symbol
Parameter
1
ClK Cycle Period
Limit Values
Units
Test Conditions
Min.
Max.
62.5
250
-
2
ClK low Time
15
230
at 0.6V
3
ClK High Time
20
235
at 3.2V
4
Output Delay
5
Output Del ay
60
0
Cl=125pF
40
6
DATA Setup Time
10
7
DATA Hold Time
5
8
READY Setup Time
38.5
9
READY Hold Time
25
10
Input Setup Time
ns
-
20
11
Input Hold Time
12
Add ress Set Up
13
Output Delay
0
50
14
Delay to Float
-
60
2.5
15
Chip Select Set Up
60
16
Command length
290
17
Data Set Up
165
18
Address Set Up
80
19
Command Inactive
290
19a
Access Time
-
542
-
at 8 MHz Operation
at 8 M Hz Operation
320
SAB 82258
A.C. Characteristics (continued)
Symbol
Parameter
Test Conditions
elK Timing for 186 Mode
20
ClK Period
21
ClK low Time
22
ClK High Time
23
ClK Rise Time
24
ClK Fall Time
125
500
55
-
-
ns
-
1.0 to 3.5V
15
3.5 to 1.0V
Ready Timing for 186 Mode
25
Ready Active Set Up Time
20
26
Ready Hold Time
10
27
Ready Inactive Set Up Time
35
28
Set UpTime
20
29
Hold Time
0
30
Data Delay
31
Status Delay
32
Delay to Float
ns
-
50
10
55
50
Asynchronous inputs are specified with setup and hold times which are only intended for determination
of whether the SAB 82258 responds to the signal in the current cycle or the next cycle.
543
SAB 82258
Waveforms
Figure 27
Timing of an Active Bus Cycle (286 mode)
15
I
lC
I
I
I
Processor Cycle
10 or 120
T1
T21 or 120 2)
ClK
A23 -A0,MIW
sUi
o15-o01lnputl
015 - o010utputl
READY
,1
l'
Synchronous
EDon IOutput)
Note1: D15-D0 floats during Single Cycle Transfer like a Read Cycle,
Note 2: T2 will be repeated, if READY is inactive,
544
SAB 82258
Figure 28
Timing of an Active Bus Cycle (186 mode)
T1
r-"I
'-'
~J= --=~
=
31
'-'~~ ' - ' Ir"""'\ ~
I- -
-
\-
-
-- -i;
-
301":
I
31
\
X
56-53
Addr.ss;«.
----
301":
I
X
3~t:
I
-3~r-
Address
- t
- .X
4
- -
L
r-J-
3~t
floa.t
-4
-
T4
13
T2
r-"I
I\I>-
'\
30r3~t
J( Addr.s
r-Data
6in
-
---=r~r
-
-
\r
'I;
1- 6 -
-32
Data. in
~
-
-4
~r-'I;
-
- qData out
l-t
71"- l~
----c:
4r-
T
l-
f-
4[":
-f-
-
-
3~1::..
I
41::
f-
4 tl-J7
1-
-
- 41::-f-
t-
4[
f-
--c:=
----
- 4r-f-
'I;
-4[--
-4rf-
-t
-
4
-
4
Note 3: For a Single Cycle Transfer tlie timing of AD15-AD0, DEN and DT/R is the same as in a
Read Bus Cycle_
Note 4: Additional T3 cycles will be inserted if bus is not ready (see fig_ 32)_
545
SAB82258
Figure 29
Timing of a Synchronous Access to the SAB 82258 (286 mode)
Processor States
TS
T-$tares
eLK
Si,Si Unputl
A7,AI (Inputl
Wnte
DIS-DD
Rl'ad·
015-011
546
f
TC
SAB 82258
Figure 30
Timing of a Synchronous Access to the SAB 82258 (186 mode)
Status. of iAPX 186
eLK
AD7-AD0
--7
A01\-A00
Data
In
14[-
Read
A01\-A00
Oata out
)-l------
547
SAB 82258
Figure 31
Timing of an Asynchronous Access to the SAB 82258
A7'A0,
BHE
=:Xl
Dr
~r--18-------------------1-1~l~
10
Write:
WR
11
17
01S'0~
lAD 1S'AO 01
r----16-----I---
1_9Q_~~r-----14~~~------------
_____________
01S'00
IA01S·AO·01
Figure 32
READY Timing (186 mode)
T21T3
T21T3
T3
~
:
elK
---'~r~
AREAOY
SREAOY
31f
I',
52,51,51
BUS READY
548
T3
BUS NOT READY
SAB82258
Figure 33
DREQ, DACK Timing (286 mode)
eLK
jt0-,.,,,--+---'~+--+--4-----
OREan
J;ill!2lIl
Bus Arbitration:
-
Bus Arbitration:
HOLD
HlDA
- -----II-------,4L
st
DACKn
.
Note 5: The trailing edge of DREQn, as specified in this dia!J(am, is necessary if only one bus cycle
should be executed.
A later trailing edge may cause an additional bus cycle (continuous DREa), if no READYwait-states are inserted.
549
SAB82258
Figure 34
DREQ, DACK Timing (186 mode)
~~2T
ClK
__S_ta_t._s__-r__+-__
rr~~Tr2~~lr
DREnn
~~~~~~---r-----+---
DACKn
Rli
or WR
Figure 35
BREL, Bus Tristate Timing (Remote mode)
I
550
T1orT21
I
T21
T1
SAB 82258
Figure 36
RESET Timing
eLK
RESET
i------2B---_t_'
A23/AREAOY
291"-
HLDA
(only
In
186 mode) _ _ _ _ _ _--'
----~-~t
7
RQ/GT mode
HOLD/HLOA mode
Figure 37
HOLD. HLDA Timing (286 model
I T-St,t,
I
T-St,t,
I
elK
HOLD
HlDA
13
A23 -A0
015-00 ---<~-----+-{
S1_S0,M!TIi,BHE
'---11----\--'
TO --/1--- T2
551
SAB 82258
Figure 38
HOLD. HLDA Timing (186 mode)
[LK
HOLD
HLDA
A19156 -A16153
BHE,S2 -S\i
Rli,WR,DTIR
AD1S-AD0,DEN
Figure 39
RQ/GT Timing (8086 mode)
elK
RliiiIT
A19/56-A16/S3
BHE,SZ-Sti
RD, WR, DTIR
AD15-AD0,DEN
552
________re_q_ue_s_t_________g_ra_nt______
-413~~r-re-le-a-se-----
SAB 82258
Figure 40
INTOUT, EOO Timing (286 mode)
[LK
INTOUT
4
I--
EODn
(Output)
EODn
(Inputl
Figure 41
INTOUT, EOO, elK Timing (186 mode)
[LK
INTOUT
(EOD 2 pin)
EODn
(Outputl
EODn
(Input)
:=-111
~~r-----------------------
553
SAB 82284
Clock Generator
and Ready Interface
for SAB 80286 Processors
SAB 82284 upto 16 MHz
SAB 82284-6 upto 12 MHz
• Generates System Clock for SAB 80286
Processors
• l8-Pin Package
• Uses Crystal or TIL Signal for Frequency Source
• Provides local READY and Multimaster
System Bus READY Synchronization
GI Single +5V Power Supply
• Generates System Reset Output from
Schmitt Trigger Input
Pin Names
Pin Configuration
c:: ~ ~ vee
17 PARDYEN
SRDY c:: 2
SRDYEN c:: 3
16 P51
15
pso
READY c:: 4
SAB
82284
EFI c:: 5
14~N.C.
ARDY
ClK
System Clock
FiE
Frequency/Crystal Select
Xl, X2
Crystal In
EFI
External Frequency In
PCLK
Peripheral Clock
ARDYEN
Asynchronous Ready Enable
ARDY
Asynchronous Ready
SRDYEN
Synchronous Ready Enable
SRDY
Synchronous Ready
6
13
~ PCLK
c:: 7
12
~ RESET
READY
Ready
X2C 8
11
~RES
Status
GNDC:: 9
10
PClK
sO,Sf
RESET
Reset
F/eC
Xl
The SAB 82284 is a bipolar clock generator/driver
which provides clock signals for SAB 80286
processors and support components. It also contains
logic to supply READY to the CPU from either
RES
Reset In
VCC
Power supply (+5V)
GND
Ground (OV)
asynchronous or synchronous sources and
synchronous RESET from an asynchronous input
with hysteresis.
AG 1/85
555
SAB 82284
Pin Definitions and Functions
Symbol
Number
Input (I)
Output (0)
ARDY
1
I
ASYNCHRONOUS READY is an active lOW input used to
terminate the current bus cycle. The ARDY
input is qualified by ARDYEN. Inputs to ARDY may be applied
asynchronously to ClK. Setup and hold times are given to
assure a guaranteed response to synchronous inputs.
SRDY
2
I
SYNCHRONOUS READY is an active lOW input used to
terminate the current bus cycle. The SRDY input is qualified
by the SRDYEN input. Setup and hold times must be satisfied
for proper operation.
SRDYEN
3
I
SYNCHRONOUS READY ENABLE is an active lOW input
which qualifies SRDY. SRDYEN selects SRDY as the source
for READY to the CPU for the current bus cycle. Setup and hold
times must be satisfied for proper operation.
READY
4
a
READY is an active lOW output which signals the current bus
cycle is to be completed. The SRDY, SRDYEN, ARDY, ARDYEN,
Sf, SO and RES inputs control READY as explained later in
the READY generator section. READY isan open collector
output requiring an external 300 ohm pullup resistor.
EFI
5
I
EXTERNAL FREQUENCY IN drives ClK when the FIC input is
strapped HIGH. The EFI input frequency must be twice the
desired internal processor clock frequency.
FIC
6
I
FREQUENCYICRYSTAl SELECT is a strapping option to select
the source forthe ClK output. When FIC is strapped lOW, the
internal crystal oscillator drives ClK. When FIC is'strapped
HIGH, the EFI input drives the ClK output.
X1,X2
7,8
I
CRYSTAL IN are the pins to which a parallel resonant
fundamental mode crystal is attached forthe internal oscillator.
When FIC is lOW, the internal oscillator will drive the ClK
output at the crystal frequency. The crystal frequency must
be twice the desired internal processor clock frequency.
ClK
10
0
SYSTEM CLOCK is the signal used by the processor and
support devices which must be synchronous with the
processor. The frequency of the ClK output has twice the
desired internal processor clock frequency. ClK can drive both
TTL and MOS level inputs.
RES
11
I
RESET IN is an active lOW input which generates the system
reset signal RESET. Signals to RES may be applied
asynchronously to CLK. A Schmitt trigger input is provided on
RES, so that an RC circuit can be used to provide a time delay.
Setup and hold times are given to assure a guaranteed
response to synchronous inputs.
RESET
12
0
RESET is an active HIGH output which is derived from the RES
input. RESET is used to force the system into an initial state.
When RESET is active, READY will be active (LOW).
556
Function
SAB 82284
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
PClK
13
0
PERIPHERAL CLOCK is an output which provides a 50% duty
cycle clock with 1/2 the frequency of ClK. PlCK will be in
phase with the internal processor clock following the first bus
cycle after the processor has been reset.
50,51
15,16
I
STATUS inputs prepare the SAB 82284 for a subsequent bus
cycle. SO and 51 synchronize PClK to the internal processor
clock and control READY. These inputs have pullup resistors to
keep them HIGH if nothing is driving them. Setup and hold
times must be satisfied for proper operation.
ARDYEN
17
I
ASYNCHRONOUS READY ENABLE is an active lOW input
which qualifies the ARDY input. ARDYEN selects ARDY as the
source of ready for the current bus cycle. Inputs to ARDYEN
may be applied asynchronously to ClK. Setup and hold times
are given to assure a guaranteed response to synchronous
inputs.
VCC
18
-
POWER SUPPLY (+5V)
GND
9
-
GROUND (OV)
Function
Block Diagram
Reset
RES
Xl
X2
RESET
CLK
EFI
F/C
ARDYEN
ARDY
SRDYEN
SRDY
READY
51
So
PCLK
557
SAB 82284
Functional Description
forced HIGH whenever either SO or Sl were active
(LOW) for the two previous ClK cycles. PClK
continues to oscillate when both SO and Sf are
HIGH.
Since the phase of the internal processor clock will
not change except during reset, the phase of PClK
will not change except during the first bus cycle
after reset.
Introduction
The SAB 82284 generates the clock, ready, and
reset signals required for SAB 80286 processors
and support components. The SAB 82284 is
packaged in an 18-pin DIP package and contains a
crystal-controlled oscillator, MaS clock generator,
peripheral clock generator, Multibus ready synchronization logic, and system reset generation
logic.
Oscillator
Clock generator
The ClK output provides the basic timing control
for an SAB 80286 system. ClK has output
characteristics sufficient to drive MaS devices.
ClK is generated by either an internal crystal
oscillator or an external source as selected by
the Fie strapping option. When Fie is lOW, the
crystal oscillator drives the ClK output. When
Fie is HIGH, the EFI input drives the ClK output.
The SAB 82284 provides a second clock output
(PClK) for peripheral devices. PClK is ClK
divided by two. PClK has a duty cycle of 50% and
TTL output drive characteristics. PClK is normally
synchronized to the internal processor clock.
After reset, the PClK signal may be out of phase
with the internal processor clock. The Sf and SO
signals ofthe first bus cycle are used to synchronize
PCLK to the internal processor clock. The phase of
the PClK output changes by extending its High time
beyond one system clock (see waveforms). PClK is
The oscillator circuit of the SAB 82284 is a linear
Pierce oscillator which requires an external,
parallel, resonant, fundamental-mode crystal. The
output of the oscillator is internally buffered. The
crystal frequency chosen should be twice the
required internal processor clock frequency. The
crystal should have a typical load capacitance
of 32 pF.
Xl and X2 are the oscillator crystal connections.
For stable operation of the oscillator, two loading
capacitors are recommended, as shown in the
figure below. The sum of the board capacitance
and loading capacitance should equal the values
shown. It is advisable to limit stray board
capacitances (not including the effect of the loading
capacitors or crystal capacitanc~) to less than 10pF
between the Xl and X2 pins.
Decouple VCC and GND as close to the
SAB 82284 as possible.
Recommended Crystal and Ready Connections
7 Xl
cb
I
(LK
1(2
1
(PU
~910n
READY 4
1
SAB 80286
V((
8 X2
6
558
10
SAB 82284
I
(l
(LK
or
Support
Component"
READY
Fie
Crystal Frequency
Cl Capacitance
C2 Capacitance
1 to 8MHz
8 to 16MHz
60pF
25pF
40pF
15pF
SAB 82284
Reset Operation
The reset logic provides the RESET output to force
the system into a known, initial state. When the RES
input is active (lOW), the RESET output becomes
active (HIGH). RES is synchronized internally at the
falling edge of ClK before generating the RESET
output (see waveforms). Synchronization of the
RES input introduces a one or two ClK delay before
affecting the RESET output.
At power up, a system does not have a stable VCC
and ClK. To prevent spurious activity, RES should
be asserted until VCC and ClK stabilize at their
operating values. SAB 80286 processors and support
components also require their RESET inputs be
HIGH a minimum number of ClK cycles. An RC
network, as shown below, will keep RES lOW long
enough to satisfy both needs.
Typical RC RESET Timing Circuit
vee
SAB
~
82284
lN914L
10k~
47~
RES
~
>il
I
A Schmitt trigger input with hysteresis on RES
assures a single transition of RESET with an RC
circuit on RES. The hysteresis separates the input
voltage level at which the circuit output switches
from HIGH to lOW from the input voltage level
at which the circuit output switches from lOW
to HIGH. The RES HIGH to lOW input transition
voltage is lower than the RES lOW to HIGH input
transition voltage. As long as the slope of the RES
input voltage remains in the same direction
(increasing or decreasing) around the RES input
transition voltage, the RESET output will make a
single transition.
Ready Operation
The SAB 82284 accepts two ready sources for the
system ready signal which terminates the current
bus cycle. Either a synchronous (SRDY) or
asynchronous ready (ARDY) source may be used.
Each ready input has an enable (SRDYEN and
ARDYEN) for selecting the type of ready source
required to terminate the current bus cycle. An
address decoder would normally select one of the
enable inputs.
The figure on synchronous ready mode illustrates
the operation of SRDY and SRDYEN. These inputs
are sampled on the falling edge of ClK when Sf
and SO are inactive and PClK is HIGH. READY is
forced active when both SRDY and SRDYEN are
sampled as lOW.
!10~F
The figure on asynchronous ready mode shows the
operation of ARDY and ARDYEN. These inputs are
sampled by an internal synchronizer at each falling
edge of ClK. The output of the synchronizer is then
sampled when PClK is HIGH. If the synchronizer
resolved both the ARDY and ARDYEN inputs to
have been active (lOW)' READY becomes active
(lOW) and the SRDY and SRDYEN inputs are
ignored.
READY remains active until either Sf or SO is sampled lOW, or the ready inputs are sampled as
inactive.
READY is enabled (lOW), if either SRDY +
SRDYEN = 0 or ARDY + ARDYEN = 0 when
sampled by the SAB 82284 READY generation logic.
READY will remain active for at least two ClK
cycles.
The READY output has an open-collector driver allowing other ready circuits to be wire ored with it.
The READY signal of an SAB 80286 system requires
an external 300 ohm pullup resistor. To force the
READY signal inactive (HIGH) at the start of a bus
cycle, the READY output floats when either Sf or
SO are sampled lOW at the falling edge of ClK.
,Two system clock periods are allowed forthe pullup
resistor to pull the READY signal to VIH. When
RESET is active, READY is forced active one elK
later (see waveforms).
559
SAB 82284
Synchronous Ready Operation
TS
TC
TC
TI
CLK
PCLK
VIH----------~~----------~----------------+_----+_--------
ARDYEN
SRDYEN--------------~--------_,~_r------~
SRDY ______________~-------J
Asynchronous Ready Operation
TS
TC
TC
TI
CLK
PCLK
VIH----------~------~--_r------~----------_TI----------~-
SRDYEN
ARDY------------~----~~r_~----~
AROYEN
560
_____-+---J
SAB 82284
Absolute Maximum Ratings 11
oto 70'e
-65to +150'e
-0.5 to
+ 7V
-1.0to +5.5V
1 Watt
Temperature under bias
Storage temperature
All output and supply voltages
All input voltages
Power dissipation
D.C. Characteristics
TA
= 0 to 70'e, vee = 5V ± 10%
Limit values
Symbol
Parameter
Min.
Max.
Unit
Test condition
IF
Forward input current
-0.5
mA
VF
= 0.45V
IR
Reverse input current
50
riA
VR
= 5.25V
ve
Input forward clamp voltage
-1.0
V
Ie
= -5mA
ICC
Power supply current
145
mA
Vil
Input lOW voltage
0.8
VIH
Input HIGH voltage
2.0
-
VOL, VCl
Output LOW voltage
-
0.45
VCH
elK output HIGH voltage
4.0
VOH
Output HIGH voltage
2.4
VIHR
RES input HIGH voltage
2.6
VIHR-VllR
RES input hysteresis
0.25
CI
Input capacitance
-
-
IOl
I
= 5mA
V
IOH=-1mA
-
10
pF
11 Stresses above those listed under "absolute maximum ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
561
SAB 82284
A.C. Characteristics SAB 82284
TA = 0 to 70"C, VCC = 5V ±10%
Limit values
Symbol
Parameter
T1
Min.
Max.
EFI to ClK delay
-
30
T2
EFI lOW time
32
T3
EFI HIGH time
28
T4
ClK period
62
T5
ClK lOW time
15
T6
ClK HIGH time
20
T7
ClK rise ti me
T8
ClK fall time
T9
Status setup time
22.5
0
-
T10
Status hold time
SRDY
+ SRDYEN setup time
T12
SRDY
+ SRDYEN hold time
T13
ARDY
+ ARDYEN setup time
4)
T14
ARDY
+ ARDYEN hold time
4)
T15
RES setup time
4)
T16
RES hold time
4)
T17
READY inactive delay
READY active delay
T19
PClK delay
T20
RESET delay
T21
PClK low time
T22
PClK high time
1)
2)
3)
4)
Test condition
at 1.5V
Cl = 150pF
IOl = 5mA
500
at 0.6V
-
see
1)
at 3.8V
from 1.0V to 3.5V
10
see
2)
from 3.5V to 1.0V
T11
T18
Unit
15
ns
0
-
at 0.8V and 2.0V on
input and 0.8V on ClK
16
0
5
24
0
40
at 0.8V
Cl = 150pF
IOl = 20mA
at 0.8V on ClK to
see 3)
0.8V or 2.0V on output
T413
-
at 0.6V
see 3)
at 3.8V
Cl = 150pF, IOl = 5mA. With either the internal oscillator with the recommended crystal and load or with
the EFI input meeting specification T2 and T3.
Cl = 150pF, IOl = 5mA
Cl = 75pF, IOl = 5mA
This is an asynchronous input. This specification is given for testing purposes only, to assure
recognition at a specific clock edge.
562
SAB 82284
A.C. Characteristics SAB 82284-6
TA = 0 to 70°C, VCC = 5V ±10%
Limit values
Symbol
Parameter
T1
Min.
Max.
EFI to CLK delay
-
35
T2
EFI LOW time
35
T3
EFI HIGH time
35
T4
ClK period
83
T5
ClK lOW time
20
T6
ClK HIGH time
25
T7
CLK rise time
T8
ClK fall time
T9
Status setup time
28
0
-
no
Status hold time
SRDY
+ SRDYEN setup time
25
T12
SRDY
+ SRDYEN hold time
0
T13
ARDY
+ ARDYEN setup time
41
5
+ ARDYEN hold time
41
30
25
10
ARDY
T15
RES setup time
41
T16
RES hold time
41
T17
READY inactive delay
T18
READY active delay
T19
PCLKdeiay
T20
RESET delay
T21
PClK low time
T22
PClK high time
11
21
31
41
Test condition
at 1.5V
Cl = 150pF
IOl = 5mA
500
at 0.6V
-
see
1)
at 3.8V
from 1.0V to 3.5V
10
see 21
from 3.5V to 1.0V
T11
T14
Unit
ns
-
5
0
at 0.8V
Cl = 150pF
IOl= 20mA
45
50
T420
at 0.8V and 2.0V on
input and 0.8V on ClK
-
at 0.8V on ClK to
see 3)
0.8V or 2.0V on output
at 0.6V
see 31
at 3.8V
Cl = 150pF, IOl = 5mA. With either the internal oscillator with the recommended crystal and load or with
the EFI input meeting specification T2 and T3.
Cl = 150pF, IOl = 5mA
CL = 75pF, IOl = 5mA
This is an asynchronous input. This specification is given for testing purposes only, to assure
recognition at a specific clock edge.
563
I
SAB 82284
elK versus EFI
The EFI input lOW and HIGH times as shown are required to guarentee the elK LOW and HIGH
times shown.
RESET and READY Timing versus.RES with S1 and SO HIGH
1)
564
This is an asynchronous input. The setup and hold times shown are required to guarantee the response
shown.
SAB 82284
READY and PClK Timing with RES HIGH
11
This is an asynchronous input. The setup and hold times shown are required to guarantee the response
shown.
565
SAB 82288 Bus Controller
for SAB 80286 Processors
SAB 82288 upto 16 MHz
• Provides Commands and Control for
local and System Bus
• Offers Wide Flexibility in System
Configurations
SAB 82288-6 upto 12 MHz
• Optimal Multibus®-Compatible Timing
• Control Drivers with 16 mA 10L and Tri-State
Command Drivers with 32 mA 10L
• Single +5V Supply
• Flexible Command Timing
Pin Names
Pin Configuration
CLK
-----,
READY [
1
ClK [
2
20 PVCC
51[3
MCE[ 4
ALE [
5
MB[ 6
CMDLY[ 7
Memory or I/O Select
MB
Multibus Mode Select
CENL
Command Enable Latched
19p5O
CMDlY
Command Delay
READY
Ready
P
DT/R
16 P DEN
15
P
CEN/AEN
CEN/AEN
Command Enable/Address Enable
ALE
Address latch Enable
MCE
Master Cascade Enable
DEN
Data Enable
14p CENL
DT/R
Data Transmit/Receive
IOWC
I/O Write Command
10RC
I/O Read Command
MWTC
Memory Write Command
MRDC [
8
13 PiNTA
MWTC [
9
12
GND[ 10
Bus Cycle Status
M/IO
18 pMJiO
17
SAB
82288
System Clock
SO,S1
P
IORC
11 plOWC
The SAB 82288 bus controller is a 20-pin MYMOS
component for use in SAB 80286 microsystems.
The bus controller provides command and control
outputs with flexible timing options. Separate
command outputs are used for memory and I/O
MRDC
Memory Read Command
INTA
Interrupt Acknowledge
VCC
Power supply (+5V)
GND
Ground (OV)
devices. The data bus is controlled with separate
data enable and direction control signals.
Two modes of operation are possible via a
strapping option: Multibus-compatible bus cycles,
and high-speed bus cycles.
Multibus® is a trademark of Intel Corporation.
AG 1/85
567
SAB 82288
Pin Definitions and Functions
Symbol
Number
Input (I)
Output (0)
READY
1
I
READY indicates the end of the current bus cycle. READY is an
active LOW input. Multibus mode requires at least one wait
state to allow the command outputs to become active. READY
must be LOW during reset, to force the SAB 82288 into the idle
state. Setup and hold times must be met for proper operation.
CLK
2
I
SYSTEM CLOCK provides the basic timing control for the
SAB 82288 in an SAB 80286 microsystem. Its frequency is
twice the internal processor clock frequency. The falling edge
of this input signal establishes when inputs are sampled and
control outputs change.
SO,51
3,19
I
BUS CYCLE STATUS starts a bus cycle and, along with MIlO,
defines the type of bus cycle. These inputs are active LOW.
A bus cycle is started when either 51 or SO is sampled LOW at
the falling edge of CLK. These inputs have pullups sufficient to
hold them HIGH when nothing drives them. Setup and hold
times must be met for proper operation.
Function
SAB 80286 bus cycle status definition
-
MilO
51
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
SO Type of bus cycle
0
1
0
1
0
1
0
1
Interrupr acknowledge
I/O read
I/O write
None; idle
Halt or shutdown
Memory read
Memory write
None; idle
MCE
4
a
MASTER CASCADE ENABLE signals that a cascade address
from a master SAB 8259A interrupt controller may be placed
onto the CPU address bus for latching by the address latches
under ALE control. The CPU's address bus may then be used to
broadcast the cascade address to slave interrupt controllers so
only one of them will respond to the interrupt acknowledge
cycle. This control output is active HIGH. MCE is only active
during interrupt acknowledge cycles and is not affected by any
control input. Using MCE to enable cascade address drivers
requires latches which save the cascade address on the falling
edge of ALE.
ALE
5
0
ADDRESS LATCH ENABLE controls the address latches used
to hold an address stable during a bus cycle. This control
output is active HIGH. ALE will not be issued for the halt bus
cycle and is not affected by any of the control inputs.
MB
6
I
MULTIBUS MODE SELECT determines timing of the command
and control outputs. When HIGH, the bus controller operates
in Multibus mode. When LOW, the bus controller optimizes the
command and control output timing for short bus cycles. The
function of the CEN/ AEN input pin is selected by this signal.
This input is intended to be a strapping option and not
dynamically changed. This input may be connected to VCC
or GND.
568
SAB 82288
Pin Definitions and Function (continued)
Symbol
Number
Input (I)
Output (0)
CMDLY
7
I
COMMAND DELAY allows delaying the start of a command.
CMDL Y is an active HIGH input.lfsampled HIGH, the command
output is not activated and CMDLY is again sampled atthe next
CLK cycle. When sampled LOW the selected command is
enabled. If READY is detected LOW before the command output
is activated, the SAB 82288will terminate the bus cycle, even if
no command was issued. Setup and hold times must be satisfied for proper operation. This input may be connected to GND
if no delays are required before starting a command.
MRDC
8
0
MEMORY READ COMMAND instructs the memory device to
place data onto the data bus. This command output is active
LOW. The MB and CMDLY inputs control when this output
becomes active. READY controls when it becomes inactive.
MWfC
9
0
MEMORY WRITE COMMAND instructs a memory device to
read the data on the data bus. This command output is active
LOW. The MB and CMDLY inputs control when this output
becomes active. READY controls when it becomes inactive.
TOwc
11
0
1/0 WRITE COMMAND instructs an 1/0 device to read the data
on the data bus. This command output is active LOW. The MB
and CMDL Y inputs control when this output becomes active.
READY controls when it becomes inactive.
10RC
12
0
1/0 READ COMMAN D instructs an 1/0 device to place data onto
the data bus. This command output is active LOW. The MB
and CMDLY inputs control when this output becomes active.
READY controls when it becomes inactive.
INTA
13
0
INTERRUPT ACKNOWLEDGE tells an interrupting device that
its interrupt request is being acknowledged. This command
output is active LOW. The MB and CMDLY inputs control when
this output becomes active. READY controls when it becomes
inactive.
CENL
14
I
COMMAND ENABLE LATCHED is a bus controller select signal
which enables the bus controller to respond to the current bus
cycle being initiated. CENL is an active HIGH input latched
internally at the start of each bus cycle. CENL is used to select
the appropriate bus controller for each bus cycle in a system
where the CPU has more than one bus it can use. This input
may be connected to VCC to select this SAB 82288 for all
transfers. No control inputs affect CENL. Setup and hold times
must be met for proper operation.
Function
569
I
SAB82288
Pin Definitions and Functions (continued)
Symbol
Number
Input (I)
Output (0)
CEN/AEN
15
I
COMMAND ENABLE/ADDRESS ENABLE controls the
command and DEN outputs of the bus controller. CEN/ AEN
inputs may be asynchronous to CLK. Setup and hold times are
given to assure a guaranteed response to synchronous inputs.
This input may be connected to VCC or GND.
When MB is HIGH this pin has the AEN function. AEN is an
active LOW input which indicates that the CPU has been
granted use of a shared bus and the bus controller command
outputs may exit Tri-state OFF and become inactive (HIGH).
AEN HIGH indicates that the CPU does not have control of the
shared bus and forces the command outputs into Tri-state
OFF and DEN inactive (LOW). AEN would normally be
controlled by an SAB 82289 bus arbiter which activates AEN
when that arbiter owns the bus to which the bus controller is
attached.
When MB is LOW this pin has the CEN function. CEN is an
unlatched active HIGH input which allows the bus controller
activate its command and DEN outputs. With MB LOW, CEN
LOW forces the command and DEN outputs inactive but does
not Tri-state them.
DEN
16
a
DATA ENABLE controls when data transceivers connected to
the local data bus should be enabled. DEN is an active HIGH
control output. DEN is delayed for write cycles in the Multibus
mode.
DTIR
17
a
DATA TRANSMIT/RECEIVE establishes the direction of data
flow to or from the local data bus. When HIGH, this control
output indicates that a write bus cycle is being performed.
A LOW indicates a read bus cycle. DEN is always inactive when
DT/R changes states. This output is HIGH when no bus cycle
is active. DT/R is not affected by any of the control inputs.
M/IO
18
I
MEMORY OR I/O SELECT determines whether the current bus
cycle is in the memory space or I/O space. When LOW, the
current bus cycle is in the I/O space. Setup and hold times
must be met for proper operation.
VCC
20
-
POWER SUPPLY (+5V)
GND
10
-
GROUND (OV)
570
Function
SAB 82288
Block Diagram
so
Status
51
-INTA
Status
Decoder
Command
Output
logic
M/iO
IORC
IOWC
Command
Outputs
MRDC
MWTC
State
Machine
ClK
DTIR
CENIAEN
CENL
Control
Inputs
CMDlY
Control
Input
logic
Control
Output
logic
DEN
ALE
Control
Outputs
MCE
READY
MB
571
SAB 82288
Functional Description
Introduction
The SAB 82288 bus controller is used in SAB 80286
systems to provide address latch control, data
transceiver control, and standard level-type command outputs. The command outputs are timed
and have sufficient drive capabilities for large TTL
buses and meet a1l1EEE-796 requirements for
Multibus. A special Multibus mode is provided to
statisfy all address/data setup and hold time requirements. Command timing may be tailored to
special needs via a CMDlY input to determine the
start of a command and READY to determine the
end of a command.
Connection to mUltiple buses is supported with
a latched enable input (CENl). An address
decoder can determine which, if any, bus controller
should be enabled for the bus cycle. This input is
latched to allow an address decoder to take full
advantage of the pipelined timing on the SAB 80286
local bus.
Buses shared by several bus controllers are supported. An AEN input prevents the bus controller
from driving the shared bus command and data
signals except when enabled by an external bus
arbiter such as the SAB 82289.
Separate DEN and DT /R outputs control the data
transceivers for all buses. Bus contention is
eliminated by disabling DEN before changing
DT/R. The DEN timing allows sufficient time for
Tri-state bus drivers to enter Tri-state OFF before
enabling other drivers onto the same bus.
The term CPU refers to any SAB 80286 processor or
SAB 80286 support component which may become
an SAB 80286 local bus master and thereby drive the
SAB 82288 status inputs.
Processor Cycle Definition
Any CPU which drives the local bus uses an internal clock which is one half the frequency of the
system clock (ClK) (see figure below). Knowledge
of the phase of the local bus master's internal clock
is required for proper operation of the SAB 80286
local bus. The local bus master informs the bus controller of its internal clock phase when it asserts
the status signals. Status signals are always
asserted in phase 1 of the local bus master's internal clock.
elK Relationship to the Processor Clock and Bus T·States
One Processor Clock Cycle
1 - - - - - One Bus T state
VCH
ClK VCl
PCLK
572
J
----~
...-----+---1\\...___,.........1
SAB 82288
Bus State Definition
The SAB 82288 bus controller has three bus states
(see figure below): Idle (TI), Status (TS), and
Command (TC). Each bus state is two ClK cycles
long. Bus state phases correspond to the internal
CPU processor clock phases.
The TI bus state occurs when no bus cycle is currently active on the SAB 80286 local bus. This state
may be repeated indefinitely. When control of the
local bus is being passed between masters, the
bus remains in the TI state.
Bus States
NEW CYCLE
READY
•
NEW CYCLE
Bus Cycle Definition
The S1 and SO inputs signal the start of a bus cycle.
When either input becomes lOW, a bus cycle is
started. TheTS bus state is defined to be the two ClK
cycles during which either Sf or SO is active (see
figure on bus cycle definition). These inputs are
sampled by the SAB 82288 at every falling edge of
ClK. When either S1 or SO is sampled lOW, the
next ClK cycle is considered the second phase of the
internal CPU clock cycle.
The local bus enters the TC bus state after the TS
state. The shortest bus cycle may have one TS state
and one TC state. longer bus cycles are formed by
repeating TC states. A repeated TC bus state IS
called a wait state.
The READY input determines whether the current
TC bus state is to be repeated. The READY input
has the same timing and effect for all bus cycles.
READY is sampled at the end of each TC bus state
to see if it is active. If sampled HIGH, the TC bus state
is repeated. This is called inserting a wait state.
The control and command outputs do not change
during wait states.
When READY is sampled lOW, the current bus
cycle is terminated. Note thatthe bus controller may
enter the TS bus state directly from TC if the status
lines are sampled active at the next falling edge of
ClK.
573
SAB 82288
Bus Cycle Definition
VCH
ClK
VCl
sEo
VIH
CPU
Vil
from
Sample
READY
vce
READY
Vil
Table 2
Command and Control Output for each Type Bus Cycle
Type of
bus cycle
M/TO
Sf
SO
Command
activated
Interrupt acknowledge
a
a
a
1
1
None; idle
a
a
a
a
1
Halt/shutdown
1
Memory read
1
a
a
Memory Write
1
None; idle
1
VO read
VOwrite
574
DT/R
state
ALE, DEN
issued?
MCE
issued?
INTA
LOW
yes
yes
IORC
LOW
yes
no
a
IOWC
HIGH
yes
no
1
none
HIGH
no
no
0
none
HIGH
no
no
1
MRDC
LOW.
yes
no
1
0
MWTC
HIGH
yes
no
1
1
none
HIGH
no
no
SAB 82288
Operating Modes
Two types of buses are supported by the SAB 82288:
Multibus and non-Multibus. When the MB input is
strapped HIGH, Multibus timing is used. In Multibus
mode, the SAB 82288 delays command and data
activation to meet IEEE-796 requirements on
address to command active and write data to command active setup timing. Multibus mode requires
at least one wait state in the bus cycle since the
command outputs are delayed. The non-Multibus
mode does not delay any outputs and does nOt require wait states. The MB input affects the timing
of the command and DEN outputs.
Command and Control Outputs
The type of bus cycle performed by the local bus
master is encoded in the M/TO, Sf, and SO inputs.
Different command and control outputs are activated depending on the type of bus cycle. Table 2
indicates the cycle decoding done by the SAB 82288
and the effect on command, DTlit ALE, DEN, and
MCE outputs.
Bus cycles come in three forms: read, write, and
halt. Read bus cycle include memory read, I/O
read, and interrupt acknowledge. The timing of the
associated read command outputs (MRDC, 10RC,
and INTA), control outputs (ALE, DEN, DT/R) and
control inputs (CEN/AEN, CENL, CMDLY, MB, and
READY) are identical for all read bus cycles. Read
cycles differ only in which command output is
activated. The MCE control output is only asserted
during interrupt acknowledge cycles.
Write bus cycles activate different control and
command outputs with different timing than read
bus cycles. Memory write and 1/0 write are write
bus cycles whose timing for command outputs
(MWTC and 10WC), control outputs (ALE, DEN,
DT/R) and control inputs (CENI AEN, CENL, CMDLY,
MB, and READY) are identical. They differ only in
which command output is activated.
Halt bus cycles are different because no command
or control output is activated. All control inputs are
ignored until the next bus cycle is started via Sf
and SO.
The basic command and control output timing for
read and write bus cycles is shown in the next five
figures. Halt bus cycles are not shown since they
activate no outputs. The basic idle-read-idle and
idle-write-idle bus cycles are shown. The signal
label CMD represents the appropriate command
output for the bus cycle. For those five figures, the
CMDLY input is connected to GND and CENL to
VCC. The effects of CENL and CMDLY are described
later in the section on control inputs.
The next two figures show non-Multi bus cycles. MB
is connected to GNDwhile CEN is connected to VCC.
The figure below shows a read cycle with no wait
states while the figure on the next page shows a
write cycle with one wait state. The READY input is
shown to illustrate how wait states are added.
575
SAB82288
Idle-Read-Idle Bus Cycles with MB = 0
Bus cycles can occur back-to-back with no TI bus
states between TC and T5. Back-to-back cycles do
not affect the timing of the command and control
outputs. Command and control outputs always
reach the states shown for the same clock edge
(within T5, TC, orfollbwing bus state) of a bus cycle.
A special case in control timing occurs for back-toback write cycles with MB = O. In this case, DT/R
and DEN remain HIGH between the bus cycles (see
respective idle-read-idle cycle diagram). The
command and ALE output timing does not change.
576
The figures on page 10 show a Multibus cycle with
MB = 1. AEN and CMDL Yare connected to GND.
The effects of CMDLY and AEN are described later
in the section on control inputs. The top figure
shows a read cycle with one wait state and the figure
below shows a write cycle with two wait states.
The second wait state of the write cycle is shown
only for example purposes and is not required.
The READY input is shown to illustrate how wait
states are added.
SAB 82288
Idle-Write-Idle Bus Cycles with MB
TI
=0
T5
TC
TC
TI
TC
ClK
SlSQ
ALE
\
\
\
DEN
~
\
\
\
\
VOH
I
DTIR
\
\
\
\
L
\
CMD
READY
Write-Write Bus Cycles with MB
=0
1st Write Cycle ---j- 2nd Write Cycle
I
I
TC
\
T5
I
TC
CLK~
I
//
\
\ '-_____..J!11:-.
\
VOH--~---------~
DEN
\y------L
VOH--~--------~~
DT/R
CMD
_
577
SAB 82288
Idle-Read-Idle Bus Cycles with MB = 1
578
SAB 82288
Idle-Write-Idle Bus Cycles with MB = 1
TI
TS
TC
TC
TC
TI
ClK
ALE
DEN
VOH--------------------T-----------~----------_T-------------
DT/R
The MB control input affects the timing of the
command and DEN outputs. These outputs are
automatically delayed in MultilJus mode to satisfy
three requirements:
1) 50 ns minimum setup time for valid address
before any command output becomes active.
2) 50 ns minimum setup time for valid write data
before any write command output becomes
active.
3) 65 ns maximum time from when any read
command becomes inactive until the slave's read
data drivers reach Tri-state OFF.
Three signal transitions are delayed by MB = 1 as
compared to MB = 0:
1) The HIGH to LOWtransition ofthe read command
outputs (lORC, MRDC, and INTA) is delayed
one CLK cycle.
2) The HIGH to LOW transition of the write
command outputs (IOWC and MWTC) is
delayed two CLK cycles.
3) The LOW to HIGH transition of DEN for write
cycles is delayed one CLK cycle.
Back to back bus cycles with MB = 1 do not change
the timing of any of the command or control
outputs. DEN always becomes inactive between
bus cycles with MB = 1.
Except for a halt or shutdown bus cycle, ALE will
be issued during the second half of TS for any bus
cycle. ALE becomes inactive at the end of the TS to
allow latching the address to keep it stable during
the entire bus cycle. The address outputs may
change during phase 2 of any TC bus state. ALE is
not affected by any control input.
The figure below shows how MCE is timed during
interrupt acknowledge (lNTA) bus cycles. MCE is
one CLK cycle longer than ALE to hold the cascade
address from a master SAB 8259A valid after the
falling edge of ALE. With the exception of the MCE
control output, an INTA bus cycle is identical in
timing with a read bus cycle. MCE is not affected by
any control input.
579
SAB 82288
MCE Operation for an INTA Bus Cycle
Control Inputs
The control inputs can alter the basic timing of
command outputs, allow interfacing to multiple
buses, and share a bu.s between different masters.
For many SAB 80286 systems, each CPU will have
more than one bus which may be used to perform a
bus cycle. Normally, a CPU will only have one bus
controller active fo r each bus cycle. Some buses
may be shared by morethan one CPU (i.e. Multibus)
requiring only one of them use the bus at a time.
Systems with multiple and shared buses use two
control input signals of the SAB 82288 bus
controller, CENL and AEN (see figure on system use
ofthose signals). CENL enables the bus controller to
control the current bus cycle. The AEN input
prevents a bus controller from driving its command
outputs. AEN HIGH means that another bus
controller may be driving the shared bus.
In the figure on theAEN and CENL signal, two buses
are shown: a local bus and a Multibus. Only one bus
is used for each CPU bus cycle. The CENL inputs of
the bus controllers select which bus controller is to
perform the bus cycle. An address decoder
determines which bus to use for each bus cycle.
The SAB 82288 connected to the shared Multibus
must be selected by CENL and be given access to
the Multibus by AEN before it will begin a Multibus
operation.
CENL must be sampled HIGH at the end of the TS
bus state (see waveforms) to enable the bus
controller to activate its command and control
outputs. If sampled LOW the commands and DEN
580
will not go active and DTlR' will remain HIGH. The
bus controller will ignore the CMDLY, CEN, and
READY inputs until another bus cycle is started via
Sf and SO. Since an address decoder is commonly
used to identify which bus is required for each bus
cycle, CENL is latched to avoid the need for latching
its input.
The CENL input can affect the DEN control output.
When MB = 0, DEN normally becomes active during
phase 2 of TS in write bus cycles. This transition
occurs before CENL is sampled. If CENL is sampled
LOW, the· DEN output will be forced LOW during TC
as shown in the timing waveforms.
When MB = 1, CEN/AEN becomes AEN, AEN
controls when the bus controller command outputs
enter and exit Tri-state OFF. AEN is intended to be
driven by a bus arbiter, like the SAB 82289, which
assures only one bus controller is driving the shared
bus at any time. When AEN makes a LOW to HIGH
transition, the command outputs immediately enter
Tri-state OFF and DEN is forced inactive. An inactive
DEN should force the local data transceivers
connected to the shared data bus into Tri-state OFF
(see next figure). The LOW to HIGH transition of
AEN should only occur during TI or TS bus states.
The HIGH to LOW transition of AEN signals that
the bus controller may now drive the shared bus
command signals. Since a bus cycle may be active
or be in the process of starting, AEN can become
active during any T-state. AEN LOW immediately
allows DEN to go tothe appropriate state. Three CLK
SAB 82288
edges later, the command outputs will go active
(see timing waveforms). The Multibus requires this
delay for the address and data to be valid on the bus
before the commands become active.
When MB = 0, CEN/AEN becomes CEN. CEN is an
asynchronous input which immediately affects
the command and DEN outputs. When CEN makes a
HIGH to LOW transition, the commands and DEN
are immediately forced inactive. When CEN makes a
LOW to HIGH transition, the commands and DEN
outputs immediately go to the appropriate state
(see timing waveforms). READY must still become
avtive to terminate a bus cycle if CEN remains LOW
for a selected bus controller (CENL was latched
HIGH).
Some memory or I/O systems may require more
address or write data setup time to command active
than provided by the basic command output timing.
To provide flexible command timing, the CMDLY
input can delay the activation of command outputs.
The CMDLY input must be sampled LOWto activate
the command outputs. CMDL Y does not affect the
control outputs ALE, MCE, DEN, and DTIR.
Waveforms
The waveforms show the timing relationships of
inputs and outputs and do not show all possible
transitions of all Signals in all modes. Instead, all
signal timing relationships are shown via the
general cases. Special cases are shown when
needed. The waveforms provide some functional
descriptions of the SAB 82288; however, most
functional descriptions are provided in the figures
of section Functional Description.
To find the timing specification for a signal transition
in a particular mode, first look for a special case in
the waveforms. If no special case applies, then use a
timing specification for the same or related function
in another mode.
CMDLY is first sampled on the falling edge of the
CLK ending TS. If sampled HIGH, the command
output is not activated, and CMDLY is again sampled
on the next falling edge of CLK. Once sampled LOW,
the proper command output becomes active immediately if MB = O. If MB = 1, the proper command
goes active no earlier than shown in the figures
on page 10.
READY can terminate a bus cycle before CMDLY
allows a command to be issued. In this case no
commands are issued and the bus controller will
deactivate DEN and DTIR in the same manner as if
a command had been issued.
581
SAB 82288
System Use of AEN and CENL
rD~
r-
Xl
READY
SRDY
r
~ CMD
r-
X2
SAB
62264
SRDYEN
XACK
ARDY
ARDYEN
ClK READY
91011
±SO/o
Si,so
~
READY
r-----
SAB ClK
82268
M/iO
CMD
,---v
-
5150
CEN
MB
1
.tv
.L
"
VI
:::>
~
r-
.3
II
~
MilO
~
ALE l -
'"
co
:E
:::>
:::>
Control> >:
51,SO
SYS/RESB
20kfi
vce
I
I IsrS:E
A~~
SAB
8283A
I
'---
ClK READY MilO
51 ,so
015-00
582
e---
AEN
SAB
80266
L---
HJ-
AEN
READY
SAB
ClK 82269
CNTl
M/iO
~
I I
I L
A23-AO
-
~---A,
Address
Decoder
r-
DT/R
CENl
MB
co
Commands>
ClK SAB
_ 82288 DEN
CENl I--
\ Data
READY
~ MilO
51,SO
\ Address
VCC
V--
~
H
SAB
6287A
-
Data>
r-
L.--
SAB 82288
Absolute Maximum Ratings 1)
o to 70°C
-65 to +150°C
-0.5to
+7V
lW
Ambient temperature under bias
Storage temperature
Voltage on any pin with respect to GND
Power dissipation
DC Characteristics
TA
= Oto 70
D
C, VCC
= 5V ±10%
Limit values
Symbol
Parameter
ICC
Power supply current
100
IF
Forward input current
ClK input
Other inputs
-1
-5
IR
Reverse input current
VOL
lOW output voltage
Command outputs
Control outputs
VOH
HIGH output voltage
Command outputs
Control outputs
Min.
-
2.4
ClK lOW input voltage
VIH
HIGH input voltage
2.0
VCH
ClK HIGH input voltage
3.9
Output off current
CI
Input capacitance
50
rIA
VR = VCC
IOl = 32mA
IOl = 16mA
VCl
ClK input capacitance
Test condition
VF = 0.45V
0.45
lOW input voltage
IOFF
Unit
mA
Vil
CClK
Max.
-0.5
IOH = -5mA
IOH = -lmA
0.8
V
0.6
-
vcc
-
+0.5
100
~IA
10
pF
1) Stresses above those listed under "absolute maximum ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
583
SAB 82288
AC Characteristics SAB 82288
TA = 0 to 70'C, VCC = 5V ±10%
Symbol
Parameter
T1
Limit values
Unit
Test condition
Min.
Max.
ClK period
62.5
250
at 1.5V
T2
ClK HIGH time
20
235
at 3.SV
T3
ClK lOWtime
15
230
at 0.6V
T4
ClK fall time
-
10
T5
ClK rise time
1.0 to 3.5V
T6
MilO and status setup time
22.5
T7
MilO and status hold time
0
T8
CENl setup time
20
TS
CENl hold time
0
T10
READY setup time
38.5
from 0.8 or
2.OV on input
to 0.8V on ClK
T11
READY hold time
25
T12
CMDlY setup time
20
T13
CMDlY hold time
T14
AEN setup time
1) 25
T15
AEN hold time
1) 0
T16
ALE, MCE active delay
T17
ALE, MCE inactive delay
T18
DEN (WRITE) inactive from CENl
T19
DT /R lOW from ClK
T20
DEN (READ) active from DT/R
10
50
ns
0
3
15
-
35
20
20
T21
DEN (READ) inactive delay
3
35
T22
DT/R HIGH from DEN inactive
10
40
T23
DEN (WRITE) active delay
-
T24
DEN (WRITE) inactive delay
3
T25
DEN inactive from CEN
T26
DEN active from CEN
T27
DT/R HIGH from ClK and CEN
T28
DEN Active from AEN
Notes see next page
584
3.5 to 1.0V
30
25
2)
50
30
from 0.8V on ClK
to 0.8 or 2.0V
on output
IOl = 16mA
IOH = -1mA
Cl=150pF
SAB 82288
AC Characteristics SAB 82288 (cont.)
Symbol
Parameter
T29
Command active delay
T30
Command inactive delay
T31
Command inactive from CEN
T32
Command active from CEN
T33
Command inactive enable from AEN
T34
Command float time
Limit values
Min.
Max.
3
20
25
---Unit
ns
Test condition
IOL = 32 mA
IOH = -5mA
CL = 300 pF
from 0.8V on CLK
to 0.8 or 2.0V
on output
40
1) AEN is an asynchronous input. AEN setup and hold times are specified to guarantee the response shown
in the waveforms.
2) T27 only applies to bus cycles where MB = 0, the SAB 82288 was selected, and DEN
terminated (because CEN = 0).
= 0 when the cycle
I
585
SAB 82288
AC Characteristics SAB 82288-6
TA
= 0 to 70°C, VCC = 5V ±10%
Symbol
Parameter
T1
Limit values
Unit
Test condition
Min.
Max.
ClK period
83
250
at 1.5V
T2
ClK HIGH time
25
235
at 3.9V
T3
ClK lOWtime
20
225
at 0.6V
-
10
T4
ClKfall time
T5
ClK rise time
T6
MilO and status setup time
28
T7
MilO and status hold time
0
T8
CENl setup time
30
T9
CENl hold time
0
T10
READY setup time
50
T11
READY hold time
35
T12
CMDlY setup time
25
T13
CMDlY hold time
0
T14
AEN setup time
1) 30
T15
AEN hold time
1) 0
T16
ALE, MCE active delay
1.0 to 3.5V
3
ns
25
T17
ALE, MCE inactive delay
DEN (WRITE) inactive from CENl
T19
DT/R LOW from ClK
T20
DEN (READ) active from DT IR
10
50
T21
DEN (READ) inactive delay
3
40
T22
DT IR HIGH from DEN inactive
5
45
T23
DEN (WRITE) active delay
-
T24
DEN (WRITE) inactive delay
3
35
-
35
40
35
T25
DEN inactive from CEN
40
T26
DEN active from CEN
35
T27
DT/R HIGH from ClK and CEN
T28
DEN Active from AEN
586
from 0.8 or
2.0Von input
to 0.8V on ClK
-
T18
Notes see next page
3.5 to 1.0V
2)
50
35
from 0.8V on ClK
to 0.8 or 2.0V
on output
IOl = 16mA
IOH = -1mA
Cl = 150pF
SAB 82288
AC Characteristics SAB 82288-6 (cant.)
Limit values
Symbol
Parameter
T29
Command active delay
T30
Command inactive delay
30
Min.
3
Max.
40
T31
Command inactive from CEN
35
T32
Command active from CEN
45
T33
Command inactive enable from AEN
T34
Command float time
-
Unit
ns
Test condition
IOL = 32 mA
IOH = -5mA
CL = 300 pF
from 0.8V on CLK
to 0.8 or 2.0V
on output
40
1) AEN is an asynchronous input. AEN setup and hold times are specified to guarantee the response shown
in the waveforms.
2) T27 only applies to bus cycles where MB = 0, the SAB 82288 was selected, and DEN = 0 when the cycle
terminated (because CEN = 0).
I
587
SAB 82288
ClK Characteristics
ClK
Status, ALE, MCE, Characteristics
588
SAB 82288
CENL, CMDLY, DEN Characteristics with MB
= 0 and CEN =
1 during Write Cycle
CLKir0V
I
DEN
[ENl
[MOLY
AEN Characteristics with MB
=1
elK
AEN
t@
J
DEN
r
1) AEN is an asynchronous input. AEN setup and hold time is specified to guarantee the response
shown in the waveforms.
589
SAB 82288
Read Cycle Characteristics with MB
= 0 and CEN = 1
DTIR
DEN
~
CENL
590
..
SAB 82288
Write Cycle Characteristics with MB = 0 and CEN = 1
DEN
VOH
OT/R
I
(MOLY
(MO
591
SAB 82288
=-
CEN Characteristics with MB = 0
TC-=r---=TC ---~+-----TS --~+----TC--
CLKUU~
[EN
T25
DEN
DT/R
READY
592
SAB 82289
Bus Arbiter for
SAB 80286 Processor Family
• Supports Multi-master System Bus
Arbitration Protocol
• Three Modes of Bus Release Operation for
Flexible System Configuration
• Synchronizes SAB 80286 Process with
MUlti-master Bus
• Compatible with IEEE 796 Standard Bus
(Multibus')
• Supports Parallel, Serial, and Rotating
Priority Resolving Schemes
Pin Configuration
Pin Names
S01 HOLD
~tat'Js Sill I Hold Input
51, H/IO
Status Inputs
H/iO
20
VCC
READY
19
S1
SYSB/RESB
1B
501 HOLD
RESET
17
ClK
BClK
16
lOC
INIT
15
AlWAYS/CRQlCK
BREQ
14
l lOCK
BPRO
13
AEN
BPRN
12
CBRQ
11
BUSY
L lOCK
Level Lock
CBRQ
Common Bus Request
LOCK
Bus Lock
GND
10
BUSY
Busy Input/Output
READY
Ready Input
SYSB/RESB
System/Resident Bus
RESET
Processor Reset
BClK
Bus Clock
INIT
Initialize
BREQ
Bus Request
BPRO
Bus Pnorlty Out
BPRN
Bus Priority In
ClK
System Clock
AEN
Address Enable
AlWAYS/CBQlCK
Always Releasel
Common Bus Request Lock
vce
+5V
GND
Ground (OV)
I
The SAB 82289 Bus Arbiter is a 5Volt, 20-pin
MYMOS component for use in multiple bus master
SAB 80286 systems. The SAB 82289 provides a
compact solution to system bus arbitration for the
SAB 80286 CPU.
The complete IEEE 796 Standard bus arbitration
protocol is supported. Three modes of bus release
operation support a number of bus usage models.
• Multibus is a trademark of Intel Corporation.
AG 12/84
593
Block Diagram
MULTIBUS
INTERFACE
STATUS [
INPUTS
'=::
SOIHOLD
51
MliO
CLK
READY
LOCAL
SYSTEM
CONTROL
ALWAYS
LOCK
CBOLCK
SYSBIREsB
RESET
AEN
-r.
=~
PROCESSOR
INTERFACE
MULTI BUS
INTERFACE
STATE
MACHINE
STATE
MACHINE
~
•
BUS REOUEST
AND
RELEASE
LOGIC
Functional Description
The SAB 82289 Bus Arbiter in conjunction with the
SAB 82288 Bus Controller and the SAB 82284 Clock
Generator interfaces the SAB 80286 processor or
some other bus master to a multi-master system
bus. The arbiter multiplexes a processor onto a
multi-master system bus. It avoids contention with
other bus masters.
The SAB 82289 has two separate state machines
which communicate through bus request and
release logic. The processor interface state
machine is synchronous with the local system
clock (ClK) and the multi-master system bus
interface state machine is synchronous with the
bus clock (BClK).
The SAB 82289 performs all signalling to request,
obtain, and release the system bus. External logic
is used to determine which bus cycles require the
system bus and to resolve the priorities of
simultaneous requests for control of the system
bus.
594
K=>
~
i.;l:!
~~
BRED
BPRN
BPRO
BCLK
CBRO
~~ BuSY
SIGNALS
SAB 82731
Dot Rate Generator
A complete video interface between CRT Controller and CRT Display
SAB 82731 - 50 MHz
SAB 82731-2 - 80 MHz
•
•
•
•
Dot shift rates up to 80 MHz (SAB82731-2)
Character length up to 16 dots
Proportional character spacing supported
Half dot shifts for character rounding
•
•
•
•
Character attribute processing
Single 5V power supply
40 pin DIP package
Interface optimized for next generation CRT
controllers
Functional Symbol
Pin Configuration
07
06
1
VCC
SAB 82731
08
05
OW
PROG
09
010
011
01
012
DB
Oi
014
PROG
9
015
VIDEO
10
11
T2
12
VT
RCLK
((LK
HOOT
00 -015
HOOT
13
X2
14
X1
O(LK
WOEF
15
(RVV
OW
16
17
(SYN
WI
18
(HOLD
W1
19
20
W3
RRVV
W2
The SAB 82731 is a general purpose video interface, which generates a video signal output for
the CRT monitor from parallel character and
attribute information coming from the character
generator and the CRT controller. The SAB 82731
--~
RRVV
(SYN
(HOLD
(BLANK
(RVV
WOEF
((LK
R(LK
I
--,---
X1:
W0-W3
--w
I
X2
~--1
I
T1
----i
~f-:
I
---I
T1
(BLANK
YSS
VIDEO
DCLK
L___
,-- ---l
T2~
1--11-1
VTH
I
---=----
I
I
L __ ___ .JI
together with minimal hardware, comprises
a complete video interface system for the CRT
controller and the CRT monitor. The device is
fabricated in a fast bipolar ASBC (Advanced
Standard Buried Collector) process of Siemens.
AG 12/83
595
SAB 82731
Pin Definitions and Functions
Input (I)
Output (0)
Function
1-8,
32-39
I
Character data parallel inputs
PROG
9
I
Program control input; used to program default width value
of CCLK and width of RCLK; the default width value of CCLK
and the width of RCLK are latched into the SAB 82731 via 00-07
at the rising edge of CCLK (active high)
VIOEO
10
0
Video output; provides the dot information clocked by the
internal dot clock
RCLK
11
0
Reference clock output; used to generate the timing for the
screen columns for data formatting. The period of RCLK is
programmable from 6 to 21 times the period of the internal
dot clock
CCLK
12
0
Character clock output; used to clock character and attribute
information out of the CRT controller. The period of CCLK is
programmable from 3 to 18 times the period of the internal
dot clock
HOOT
13
I
Half dot shift input; the video signal at the video output will be
delayed by half dot clock for character rounding (active high)
CBLANK
14
I
Character blank attribute input; the video output is blanked
(active high)
WOEF
15
I
Width defeat attribute input; the CCLK period is set to a
preprogrammed default value (active high)
CRVV
16
I
Character reverse video attribute input; inverts the character
data from 00-015 (active high)
Symbol
Number
00-015
596
SAB 82731
Pin Definitions and Functions
(continued)
Symbol
Number
Input (I)
Output (0)
DW
17
I
Double width attribute input; the internal dot clock frequency
and the CClK frequency are divided by two (active high).
The RClK frequency remains unchanged
W0-W3
18,19
21,22
I
Clock width inputs; they are used for programming the CClK
clock width on a character by character base
CHOLD
23
I
CClK inhibit input; this signal suppresses the CClK generation
and is used for TAB function (active low)
CSYN
24
I
CClK synchronization input; CClK will be synchronized to
RClK and the video output signal is defined by RRVV (active
high)
RRVV
25
I
Field reverse video input; the video signal at the video output
will be inverted (active high)
DClK
26
a
Dot clock output; ECl-level signal intended for test purposes
only. Must be grounded via a 3.3k resistor if used
Xl-X2
27,28
I
Inputs for fundamental mode crystal; its frequency must be
1/8 of the required dot clock frequency
VT
29
a
Tuning voltage for Pll-VCO; this output is used to tune
the lC-circuit and thus controls the oscillator frequency of the
internal dot clock
Tl-T2
30,31
I
lC-circuit inputs for PLL-VCO. Tl can be used to provide the
SAB 82731 with an external clock
VCC
40
-
+ 5V power supply
VSS
20
-
Ground (OV)
Function
597
SAB 82731
Figure 1: CRT System Block Diagramm
HSYN[
VSYN[
i
Control SI nals
I
I
Video Inter-
Character
M, (ro-
Vrdeo
foce Logic
Cnafocter Code
pr ocessor
<-~
Data
CRT -
Character
Generator
Controller
Sy stem-
- Clock Generation
- Shift Register
Character
bu s
Lme Address
Attnbutes
- Attribute
Processing
Field Attributes
~
---
Clock Signals
Figure 2: SAB 82731 Block Diagramm
(BLANK
--~----
V[[
---
VSS
(RVV
ow
-----
Attribute
Register
HOOT
RRVV
Attribute
Processing
Ot-015
y=;
VIDEO
16-61t
Shift
Register
RCLK
ol·OJ L - - V
W0-W3
-----,/
CSYN
--.--
WOEF
--.~
598
_.
-----
Xl
(eLKI
R(lK
Register &
PROG
(HOLD
(eLK
Genl"rotor
~l~;k
--------
Xl
---_.__
T1
Oscdlatar
-----
PLl
VT
.
~.-.---.-
T1
SAB 82731
General Description
The dot rate generator, SAB 82731, in a typical CRT
system shown in figure 1, interfaces the CRT
controller to the CRT video terminal (Video Interface
Logic). It receives the parallel data along with the
attribute and control information from the CRT
controller, processes it into a serial video signal
which can be fed to a video CRT terminal. It also
generates the basic dot clock {DCLKI. character
clock (CCLK) and reference clock (RCLK) signals.
CCLK and RCLK are required by the CRT controller.
CRT terminals requiring very high resolution,
extremely stable and absolutely flicker-free pictures,
place special demands on the dot rate generator.
In such applications very high dot rates up to 80 MHz
are necessary. This leaves very little time per dot
(pixel) to convert the data, attribute, and control
information into serial form for the video terminal.
The functions of SAB 82731 are largely determined
by the complexity and the demands of the CRT
controller it supports. Figure 2 shows the block
diagram of the dot rate generator. The dot clock is
generated by a voltage controlled LC circuit
connected at T1 and T2. Another clock is generated
which is crystal controlled and has a frequency 1/8
of the dot clock. This is used to stabilize the dot clock
using an on-chip phase locked loop (PLL). This
two-oscillator concept enables the use of low cost,
fundamental mode crystals.
The 16 bit shift register receives parallel inputs from
pins DO-D15. This allows a maximum character
width of 16 dots. The minimum width can be 3 dots.
The character width is programmable on a character
-(0 character base through pins WO-W3 for proportional character spacing. This also determines
the character clock (CCLK) frequency. Programming
of the default character width and the reference
clock (RCLK) is done through inputs DO-07 and
PROG. Signal WDEF can be used to switch between
the default character width and the one specified
dynamically through the lines Wf/J-W3. A special
problem is encountered when using variable
character width. For example, when tables are
formatted on the screen it is essential that every
entry in a column starts at the same dot distance
(and not the character distance) from the start of
line. This is directly supported by SAB 82731
providing a tabulator function using CHOLO signal.
It is possible to shift every line of character by half a
dot using the HOOT signal. This feature, known as
character rounding, further enhances the quality of
high resolution character display. Other features,
like blinking of characters, reverse video which
improves the readability of text on screen, are
directly supported by SAB 82731 using signals
CRVV and RRVVfrom the CRT controller, processing
them and effecting the final video signal to show the
characters with the desired attributes.
599
SAB 82731
Functional Description
Clock Generation
The-most fundamental clock required to run the
CRT display is the dot clock which provides the
reference for the dot data to be shifted serially to the
CRT. Ifl addition, it is basis for the character clock
CClK and the reference clock RClK required by the
CRT controllers.
Dot Clock
The dot clock is derived from on-Chip oscillator (T1,
T2). Its frequency is determined by an external
voltage controlled lC-circuit that has a center
frequency of about two times the desired dot clock
frequency. The on-chip Pll-circuit causes via VTthis
oscillator to be locked to the 16th harmonic of the
on-chip crystal oscillator (X1, X2) which is running
at 1/8 of the dot clock frequency (see figure 3a).
Alternatively, the SAB 82731 can be supplied with
an external TTL-level clock via T1 that must be
two times the dot clock rate (see figure 3b).
The SAB 82731 provides the dot clock at the DClK
output. It is an ECl-level output and is intended for
testing and adjustment purposes only.
Figure 3: Clock Generation
X1
X2
Crystal
Circuit
X1
VCC
XZ
T2
SAB
82731
T1
T2
Voltage
Controlled
LC - Circuit
I
VT
a) Internal Clock Generation
600
T1
SAB
82731
VT
ECLK
,
OCll(
Filter
b) External Clock Generation
I
I
Clock
Generator
I
SAB 82731
Designing the Oscillator Circuit
The whole external oscillator circuit consists ofthree
parts
- the crystal circuit,
- the voltage controlled LC-circuit and
- the loop filter for the PLL.
Figure 4a shows the general crystal circuit. The
crystal must be a fundamental mode series resonant
type with a resonant frequency of 1/8 of the desired
dot clock frequency. The capacitor Cx is necessary if
a fine adjustment of the dot clock rate must be done.
Figure 4b shows as example how the dot clock
frequency can vary with different values of Cx. The
capacitors Cl and C2 may be necessary to suppress
overtone oscillations if the crystal frequency is
below of 6 MHz. The exact values depend on the
used crystal and must be determined in an empiric
way. The recommended ranges are 1 to 10 nF for
Cl and a to 100 pF for C2.
The voltage controlled LC-circuit is shown in figure
4c. The effective oscillating LC-circuit consists of
the inductance L, the capacitance CD of the varactor
diode, and the parasitic capacitance CP.lts resonant
frequency is
fR = ::--r.=~~==;;:~
2" yL . (CD + CP)
where fR must be 2 x fDCLK. The value of CP
depends on many factors (e.g. layout, single/multilayer board ... ), thus it changes from application to
application. However a value of about 5 to 15 pF
seems to be a good approximation.
The value of CD (capacitive diode) should be
determined at a control voltage of 2.5V to get the
lock-in-range as wide as possible. The variation of
VT ranges from lV to VCC-l which results in a
minimum frequency shift of about 6-8% with
respect to the center frequency at 2.5V.
The value of the inductance L must be determined in
such a way that the resulting center frequency lies
as near as possible to the needed frequency
fR = 2 x fDCLK to guarantee a stable dot clock under
all operation conditions. Figure 4f shows a diagram
that will help you find the required inductance L. It
is based on the use of the capacitive diode BB 505G
that has a capacitance of 12 pF at a control voltage
of 2.5V. The use of other diodes will, of course, lead
to other diagrams.
At dot clock frequencies higher than 50 MHz the
needed inductance becomes lower than 100 nH.
In these cases, it is favorable to integrate the
inductance into the board layout. Figure 4e shows a
possible layout for the external oscillator circuit and
approximate (measured) values of the inductance
of the printed coil (track width and track distance
0.5 mm).
The loop filter converts the current pulses delivered
by the PLL into the control voltage VT for the VCO.
It is an essential part of the PLL and determines, for
example, the lock-in-range and the control action of
the PLL. A second-order filter that was found to work
well under all operation conditions and over the
full frequency range is shown in figure 4d.
601
SAB82731
Figure 4: Designing the Oscillator Circuit
Cl
Xl
1----------1
CX (pF)
fDCLK(MHz)
2.2
64.053
6.8
64.016
15
63.987
33
63.966
(nominal crystal frequency 8 MHzl
a) crystal CirCUit
bl example for the influence of ex on the dot
clock frequency
Rs
Tl
Df---------
VT
1kJl
T2
cl VCO-circuit
(1
VT
CK = 1nF
C, = 100nF
R
R =12kJl
( :33nF
CF =100 pF
d) PLL-Ioop filter
nH
3000
2000
1000
500
"'0
300
200
100-
50
40
30
20
e) example layout for printed circuit
602
70
40 60
100
200
10
20 30
50
100
f) L/f-dlagramm
---fR
--__ fOCL!<
MHz
MHz
SAB 82731
Reference Clock (RCLK)
RClK is the reference clock output used to generate
the timing for the screen layout and to define screen
columns fordata formatting and tabulator locations.
In addition, it is used to clock the field attribute
signals into the SAB 82731. The period of RClK is
programmable from 6 to 21 times the period of the
dot clock, i.e. the RClK high time is 3 dot clock
periods and the RClK low time is programmable
from 3 to 18 dot clock periods. It is programmed
via 04-07 at the rising edge of CClK, when PROG is
active (see table and figure 5).
It is recommended to program the RClK clock width
only once after a system reset.
Programming table for the clock width of RClK
04 .PROG
07
06
05
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
RClK period x dot clock period
0
1
0
0
1
0
1
0
16
17
18
19
20
21
6
7
8
9
10
11
12
13
14
15
Character Clock (CCLK)
CClK is the fundamental character clock output
used to clock character and attribute information
out of the CRT controller and into the SAB 82731.
It is a rising edge triggered clock and inside the
active character field its period is programmable
from 3 to 18 times the period of the dot clock, i.e.
the CClK high time is 2 dot clock periods and the
CClK low time is programmable from 1 to 16 dot
clock periods.
When CSVN is active (normally outside the active
character field) CClK is forced to match RClK.ln this
case the CClK high time is 3 dot clock periods
instead of 2.
In order to support proportional spacing, the
period of CClK can be reprogrammed at the
beginning of each CClK cycle via the Wf/;-W3 inputs
(i.e. at the beginning of each character) if PROG is
inactive.
6D3
SAB 82731
Programming of the character width is done via the
clock width inputs Wf/J-W3 according to the
programming table. The Wf/J-W3 input data is
clocked into the SAB 82731 at the rising edge of
CCLK and defines the width of the currently
displayed character (see figure 6).
If the width defeat attribute (WOEF) is active, the
period of CCLK will be set to the programmed
default value ignoring the clock width inputs
Wf/J-W3. This value is programmable from 3 to 18
times the period of the dot clock via the 0f/J-03 data
inputs, when the PROG input is active (see figure 5).
It is recommended to programm the default CCLK
clock width only once after a system reset.
The CCLK clock period will be doubled ifthe double
width attribute (OW) is asserted.
Note:
If the width ofCCLK is programmed to 17 or 18, zeros
are shifted out from the internal shift register after
the 16 data bits and displayed according to the
attribute signal.
Programming table for the clock width of CCLK
PROG = 1
03
02
01
Of/J
PROG = f/J
W3 W2
W1
Wf/J
CCLK clock period x dot clock period
0
0
0
0
0
0
0
0
1
0
1
0
16
17
18
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
Note:
PROG = 1: Programming the CCLK default clock width during the initialization phase via 0f/J-03 at the rising
edge of CCLK.
PROG = f/J: Programming the clock width of the current CCLK cycle via Wf/J-W3 at the rising edge of CCLK.
604
SAB 82731
Clock Initialization Sequence (PROG)
After power on the width of RCLK is a random
value between 6 and 21 and the width of CCLK is a
random value between 3 and 18.
It is recommended to initialize the SAB 82731 in the
following way:
- Activate the CSYN signal.
CCLK is forced to match RCLK, which has a
minimum clock width of 6 dot clock periods.
- Apply the clock width information to D0-D3 and
D4-D7 according to tables.
- Activate the PROG signal.
The default width of CCLK and the width of RCLK
are programmed at the next rising edge of CCLK
(see figure 5).
- Remove the PROG signal
CSYN can be removed at the beginning of the next
active data field.
Figure 5: Clock Initialization
OCLK
PROG
CSYN
00· 03
04- 07
08·015
W0-W3
(CLK
RCLK
after POWER ON:
undefined RCLK and (CLK
clock width
synchronize RCLK
and CCLK
program CCLK default width
100'031 and R(LK width
104' 071
605
SAB 82731
Character Data Signals
The character data signals are normally provided by
the character ROM and clocked into the SAB 82731
at the rising edge of CClK.
The character data signals consist of
• the character data lines (00-015),
• the character width information (W0-W3)
and
• the half dot shift signal (HOOT).
Dot Data (00-015)
The dot data signals will be clocked into the
SAB 82731 via the 00-015 inputs at the rising edge
of CClK. The actually used inputs are defined by the
W0-W3 inputs or the internally latched default
width information previously programmed. The
dot data will be displayed dependent on the control
signals and on the corresponding attribute information. The data are serially shifted out at the
video output starting with 00.
If CClK width is greater than 16, zeros are shifted out
for the rest of the dot clocks and displayed according
to the attribute signals.
Character Width (W0-W3)
The W0-W3 inputs are clocked into the SAB 82731
at the rising edge of CClK and determine the width
of the currently displayed character (see CClK).
Figure 6: Action of Clock Width Inputs W0-W3 on CClK
OCLK
W3
W2
Wl
CeLK
width=
606
SAB 82731
Half Dot Shift (HOOT)
The half dot shift character data signal is clocked
into the SAB 82731 at the rising edge of CClK.
When the half dot shift signal is active (high), the
output of the displayed data will be delayed by half
a dot line. The first dot of the character dot line is
transmitted during one and a half dot clock period
while the last dot of this character dot line is displayed
for half a dot clock period only. The remaining
character dots are transmitted within one dot clock
period and thus the whole character dots are shifted
by half a dot.
The HDOT signal is no character attribute signal,
because it can change from dot line to dot line of a
character. Thus it is reasonable to generate it from
the character ROM together with the dot data and
the width information.
Note that only the character dot line to which the
HDOT signal is attached is effected.
Figure 7: Function of HOOT on VIDEO
OCLK
HOOT
CCLK
VIDEO
11
2)
1)
2)
Width is assumed to 5 03-00=.SH
111 1/2 OCLK
2) 1/2 OCLK
607
SAB 82731
Character Attribute Signals
These signals are clocked into the SAB 82731 at the
rising edge of CClK. Thus they are valid for the
next character only.
The character attribute signals consist of:
• character blanking
CBlANK,
• character reverse video
CRVV,
OW,
• double width
• width defeat
WOEF.
Outside the active character field (which is defined
by the CSYN signal) all character attribute signals
are ignored.
Character Blanking (CBLANK)
The CBlANK input is clocked into the SAB 82731 at
the rising edge of CClK. If aktive (high), the blank
attribute will produce the effect of blanking the
display of the character. When the CBlANK attribute
is active the corresponding dot data information
00-015 will be as if all zeros where forced at the
inputs. The video output can be inverted to all ones
by simultaneously activating the CRVV attribute.
Independent of these character oriented operations
the video output signal is also effected by the RRVV
field attribute signal.
Although the CBlANK signal is normally a character
attribute, it may change from dot line to dot line of a
character. Thus together with the CRVV signal one
or more underlines or cursors can be generated
controlled by the CRT controller.
608
Character Reverse Video (CRVV)
The CRVV input is clocked into the SAB 82731 at the
rising edge of CClK. It is an active high signal. In the
character field, the CRVV attribute will produce the
effect of reversing the polarity of the display during
the transmission of the current character. CRVV is
also effective together with the CBlANK attribute
(see CBlANK description) and the RRVV signal.
Outside the character field, the CRVV attribute is
ingnored. Although the CRVV signal normally is a
character attribute signal it may change from dot
line to dot line of a character in order to support
underlines or cursors.
Double Width (OW)
The OW input is clocked into the SAB 82731 at the
rising edge of CClK. The dot clock frequency and
the CClK frequency will be halved when the double
width attribute is active (high), producing characters
that are twice as wide. The period of RClK is not
changed (see figure 8).
Width Defeat (WDEF)
The WOEF attribute signal is clocked into the
SAB 82731 at the rising edge of CClK. When the
width defeat attribute is active (high), the width of
CClK will be set to a default width value previously
programmed (see figure 9).
SAB 82731
Figure 8: Function of OW on OCLK and CCLK
OClK
ow
CClK
wldth=
4
4
I
Figure 9: Function of WOEF
DClK
WDEF
CClK
W3
WZ
W1
At (CClK f), WDEF =0
&
defines the C(lK
At 1((lK I), WDEF =1 defines ((lK width
as the default value 15) ignOring
At ICClKI)
defines Width of (ClK
when WDEF =0
width as 3
The default Width of ((lK was prevIOusly defined as 5
609
SAB 82731
Field Attribute Signals
The field attribute signals are clocked into the
SAB 82731 with the rising edge of RClK. Thus the
attributes are valid for a specifical part of the screen
independent of how many characters are displayed
within this part.
The SAB 82731 supports two field attributes:
• field reverse video RRVV and
• clock synchronization CSYN.
Field Reverse Video (RRVV)
The RRVV control signal is clocked into the
SAB 82731 at the rising edge of RClK. It immediately
effects the display by the polarity of the video output
in both the character field and the border of the
display. It is an active high signal.
Clock Synchronization (CSYN)
CSYN is a field attribute signal, because it defines
the active character field in addition to its function
of synchronizing CClK and RClK.
With a low level of CSYN (deactivated) clocked into
the SAB 82731 with the rising edge of RClK, the
beginning of the character field area is defined (see
figure 10) and the first character will be displayed.
At the next rising edge of RClK after CSYN is
activated (i.e. at the end of the character field), the
video output is forced to zero or, if the RRVV control
signal is active, to a high level. The currently
transmitted character will be truncated at this
location. At the same time, CClK will be forced to
match RClK starting with the next rising edge of
RClK (see figure 10). While CSYN is active all
character attribute and data signals are ignored and
only the field reverse video signal is effecting the
video output.
Before the deactivation of CSYN, the data and
attribute pipeline has to be filled by the CRT
controller with the information of the fi rst character.
Figure 10: Function of CSYN
D[LK
CSYN
RCLK
[[LK
W3
W2
W1
"0
Beginning of
IS forced to match
RClK
(Lost character IS truncated ~
(elK
610
charl1cter
field
End of character fIeld
SAB82731
Tabulator Function
The SAB 82731 supports tabulator functions by
providing the CHOLD (character clock inhibit) input.
CCLK Inhibit (CHOLD)
When the CHOLD signal is activated (low) it inhibits
the CCLK clock and thus freezes the information
pipeline between CRT-controller and SAB 82731
until the next tabulator location is reached. CHOLD
has to be activated simultaneously with the display
of the TAB-character. If the TAB-character doesn't
consist of all zeros, it must be blanked by activating
CBLANK.
The width of the TAB-character can be determined
by W0-W3 or by activating WDEF.
The CHOLD-signal is provided by the CRT-controller
and it is assumed to be triggered with the leading
edge of CCLK (figure 11). With the same edge of
CCLK, the TAB-character will be latched into the
SAB 82731. Thereby the attnibutes CBLANK and
WDEF must be active if used. Thus the TABcharacter will be displayed completely andtheCCLK
will be inhibited until reaching the specified
tabulator location, which is defined by CHOLD
inactive (high) at the rising edge of RCLK.
In the timing diagrams it is assumed that CHOLD
is deactivated by the trailing edge of RCLK. Figure 11
shows the normal case Where the display of the
TAB-character is finished before the deactivation of
CHOLD. The gap between the TAB-location and the
following character is normally blanked. In this
scheme the TAB-character will be handled by the
SAB 82731 like any other character (attribute processing is done quite normally).
In case of CHOLD active width being less than the
TAB-character width the TAB-character will also be
displayed completely. However, we have to
distinguish three different cases:
1) TAB-character is terminated before reaching
TAB-location. The next character will be
displayed as described before. In the gap the
video output is normally blanked.
2) TAB-character is finished exactly at the TABlocation. The next character will be displayed
immediately without delay.
3) TAB-character is not terminated when reaching
the TAB-location (see figure 12). The following
character will be displayed subsequently after
the display of the TAB-character (i.e. the start
of the following character is not at the TABlocation).
If the CHOLD signal is not deactivated the video
output will be continuously blanked. In the gap
between the end of the TAB-character and the
TAB-location all character attribute signals will
have no effect on the video output signa/. If the
RRVV control signal is active the video output signal
is inverted.
611
I
SAB 82731
Figure 11: Function of CHOLD (normal case)
D(LK
R(LK
((LK
~~=====i====~~==~~~
21
31
'I
WDEF
TAB request
End of TAB character
TAB loenlion
Start of next character
11 TAB character IS displayed completely video output
2l Video output IS blanked
IS
blanked
3) Next char']( ter
410elault Width 7, TAB character Width del"ed by WOEF
Figure 12: Function of CHOLD with CHOLD Width Less than Character Width (case 3)
TAB request
End 01 TAB character.
Start 01 next character
TAB location
'I TAB character IS displayed completely video output is blanked
21 Next character displayed subsequently Inot on TAB location I
JI Delault width, ", TAB character width delined by WDEF
612
SAB 82731
Video Output
The video output provides an ECl oriented signal
(see figure 13) and is matched to drive a 50 Ohm
coax cable (see figure 14), In case of external
attribute processing the external logic can be
ECl- or STTL-compatible,
Figure 13: Video Output Stage
vee
--------~--------------.
5011 Typ
Video
IO
I
VSS
Figure 14: Video Output Load
vee
Coax Cable
Video
1
D
0
son eOAX
)
Video Ampl.
0
vee
Video
V
5011 COAX
"
t
Video Ampl.
-)
JSOJl
SOJl
--
-~
~
613
SAB 82731
Figure 14: Video Output Load (continued)
vee
EeL Logic
vee
Reference
Voltog.f1liVv1)- - - - - + - - - - - - - L__'"T""_ _J
VSS
vee
STTL Logic
vee
vee
VSS
VSS
Figure 15: Proposed Converter for Video Output to TTL Level Output
vee
Video
vee
vee
270n
2x 2N2894A
~----+---o TTL Level
Output
1k
VSS
614
SAB 82731
Absolute Maximum Ratings 1)
o to + 70°C
-65 to + 150°C
-0.5V to +6V
-0.5V to +5.5V
1.5 Watts
Temperature under bias
Storage Temperature
All output and supply voltages
All input voltages
Power dissipation
D.C. Characteristics
TA = a to 70°C; VCC = 5V ±10%
Limit values
Symbol
Parameter
VC
Input clamp voltage
ilL
Forward input current
IIH
Reverse input current
VOL
Output low voltage
Unit
Test conditions
-1
V
IC
-
-0.7
mA
VIL
= 0.5 V
-
50
~A
VIH
= VCC
CCLK
0.5
V
IOL
= 8 mA
RCLK
0.5
IOL
= 4 mA
Min.
Max.
=
-5 mA
VCC-l.2V
VCC.(J.6V
-
IOL
=a
CCLK.RCLK
2.4
-
V
IOH
=
VIDEO
VCC.(J.2V
VCC
-
IOL
=a
VIL
Input low voltage
-
0.8
V
-
VIH
Input high voltage
2.0
-
ICC
Power supply current
-
250
mA
')
ZO
Output impedance VIDEO
40
70
Ohms
-
CIN
Input capacitance
-
15
pF
fc
VIDEO
VOH
I
Output high voltage
=
-400~
1 MHz
') Stresses above those listed under "absolute maximum ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
') All outputs open; VCC
= 5V;
TA
= 25°C.
615
SAB 82731
A.C. Characteristics
TA = 0 to 70°C; VCC = 5V ± 10%
Limit values
Symbol
SAB 82731
Parameter
Min.
Max.
tDHDH
DCLK cycle period
20
125
tCHCH
CCLK cycle period
3
18
SAB 82731-2
Min.
Unit
Test conditions
ns
-
JMax.
tDHDH
r-tCLCH
CCLK low time
tDHDH
-10
16 tDHDH
+20
ns
tCHCL
CCLK high time
2tDHDH
-20
-
tRHRH
RCLK cycle period
6
21
r---tDHDH
r-tRLRH
RCLK low time
3 tDHDH
-10
tRHRL
RCLK high time
3tDHDH
-20
tDVCH
Data and attribute
input set up time
30
tCHDX
Data and attribute
input hold time
0
tHLTE
CHOLD active before
end of TAB.-char.
30
tHLHH
CHOLD pulse width
20
tHHRH
CHOLD inactive set
up before rising
edge of .RCLK
30
tHLRH
CHOLD inactive hold
0
18 tDHDH
+20
1)
-
Fig. 16
ns
time after rising
edge of RCLK
') A.C. data for the SAB 82731-2 was not available at the time this data book was compiled.
Contact your Siemens representative for complete information.
616
SAB 82731
A.C. Characteristics
(continued)
Limit values
Symbol
Parameter
SAB 82731
Min.
tCHVV
Video output valid
after rising edge
Max.
SAB 82731-2
Min.
Unit
Test conditions
I Max.
-
6
-
ofCCLK
tOLOH
TIL-output rise time
tOHOL
TIL-output fall time
tVLVH
Video output
rise time
Fig. 16
10
1)
ns
Fig. 17
3
tVHVL
Video output
fall time
') A.C. data for the SAB 82731·2 was not available at the time this data book was compiled.
Contact your Siemens representative for complete information.
617
SAB 82731
A.C. Testing Waveforms
Figure 16: TTl-levellnputlOutput Testing
24 ==>{20'
05
'>
Test POints
< 20/C
.
~Q~8_~
_______________"~0~.8_
Figure 17: ECl-level Output Testing
vee - 0.3V
>
vee - O.3V
Test Points
Vee-O.5V
<
Vee-O.5V
A.C.'Testing Load Circuits
Figure 18: TTL-level Output load Circuit
vee
Figure 19: ECl-level load Circuit
y
VIDEO
RL
RCLK {CCLK
CL
I1sPF
VSS
vss
RCLK, RL =100Jl
CCLK,RL=lSOJl
618
SAB 82731
A.C. Waveforms
Figure 20: Basic Timing
tDHDH
DCLK
CCLK
D0- D15, WDEF,
WVrW3, DW
HDOT, CBLANK,
CRVV, PROG
VIDEO
I
RCLK
RRVV, CSYN
tCHDX
Figure 21: Timing on CHOLD
RCLK
---t--IHLHH
-----~
End of TAB ,hara,ter
Beginning of TAB ,hara,ter
Beginning of next
chcroc.ter
619
SAB 82731
Application Examples
Figure 22: Example of Interface to SAB 82730
(SYN
(BLANK
RRVV
morn
XI
BLANK~============~~~~~~======================~
WOEF
WOEF
R(LK
RCLK
CRVV
SAB
Choracter Attnbutes
(RVV
Xl
(ClK
81730
DAT
e·14
VT
TI
SAB
L(
i' 4
Tl
Oscillator
cod
PLL'Clrcu!t
82731
VIDEO
Address Bus
to System
B"
Data Bus
RAM or ROM may be selected either by addresses or by control signals. For pipeline register use positive
edge triggered D-Flipflops (non-transparent latch) like SN 74374.
620
SAB 82731
Figure 23: Example of Interface to SAB 8275
CC
LC
DS-D3
DS-DJ
D4,-D6
D4-06
Cnaradergenerator
PROG
07
T1
SAB
SAB
Xl
D7
82731
SAB
8275
X1
Oscillator
Tl
and
PLL Circuits
RCLK
CCLK
CCLK
RVV
LTEN
RRVV
VT
8276
vsp
HRCT
VRCT
VIDEO
VIDEO
I
HSYNC
VSYNC
621
Memory Components
SAB 81C5x
256 x a-Bit Static CMOS RAM
Preliminary data
MOS circuit
The SAB 81C5x is a 2048 bit static random access memory (RAM), organized as 256 words
by 8 bits, manufactured using CMOS silicon gate technology. The multiplexed address
and data bus allows to interface directly with the CMOS 8-bit organized processors and
microcomputers, for example with SAB 8085, SAB 8086, SAB 8088, SAB 8048, SAB 80C48,
SAB 8051 and SAB 80C482. Low standby power dissipation «1 j.tA) minimizes system
power requirements.
Features
•
256 x 8-bit organization
•
Multiplexed address and data bus
•
Tristate address/ data lines
•
Very low power consumption
Standby
1 iJA at 6 V
Operation 500 iJA at 6 V. 1 MHz
•
Wide supply voltage range: 2.5 to 6 V
•
Data retention: 1.5 V
I
AG4/84
625
SAB 81C5x
Pin configuration
top view
ADO
1
16
Voo
AD1
2
15
REi
14 WR
AD2
AD3 4
13 ALE
AD4 5
12 (SICS
AD5
6
11
AD7
Vss
7
10
AD6
N.C.
N.C.
Pin designation
Pin No.
Symbol
Description
1-6
10, 11
ADO-7
Address/data lines
12
CS,CS
Chip select
CS = active low;
internal pullup;
CS == active high
internal pulldown
13
ALE
Address latch enable
14
WR
Write enable
15
RD
Read enable
16
VDD
Power supply
(2.5 - 6 V)
7
Vss
Ground (0 V)
8, 9
NC
Not connected
626
SAB 81C5x
Logic symbol
CS{CS
Address {d ata
bus,8-bits
Ri5
SAB
B1 CSx
WR
ALE
Truth table for control and data bus pin status
CS
CS
RD
WR
H
L
X
L
H
L
ADO ... AD? during data portion of cycle
Function
X
floating
none
H
data from memory
read
L
H
H
L
data to memory
write
L
H
H
H
floating
none
I
627
SAB 81C5x
Block diagram
~
r-v
Address
latches
AL.A7
Gated
row
decoder
32.64
matrix
5
1t
J-
Read logic
5
~
ADO ... AD7
ALE
EStCS
628
D
---
REi
~
WR
~
H
Write
D
r-
logic
Gated
column decoder
J-
Control
logic
~ Address
latches
AO, Al
I
SAB 81C5x
Maximum ratings *)
°C
°C
-25 to 70
-55 to 125
Ambient temperature under bias
Storage temperature
Supply voltage referred to GND (Vss)
Total power dissipation
All input and output voltages
o to 7
V
250
-0.3 to Voo
V
mW
*) Stresses above absolute maximum ratings may cause permanent damage to the device.
DC characteristics
Tomb = 25°C; Voo = 2.5 to 6 V; Vss
=0 V
Test conditions
Standby supply current
Operating supply current
Operating supply voltage
Standby voltage
Input current
Output leakage current
L
H
L
H
Typ
Min.
100
/=1 MHz
100
Voo
Voo
IlL
for data retention
VI =0 to 6 V
Vo = 0 to 6 V
high impedance
IOL
input voltage
input voltage
output voltage
output voltage
VIL
VIH
VOL
VOH
IOL
IOH
Max.
Unit
1
Il A
Il A
V
V
Il A
Il A
500
6
6
1
1
2.5
1.5
-0.3
0.45
O. 7xVoo
Voo
0.45
=1 mA
=1 mA
O.75xVoo
V
V
V
V
AC characteristics:
Tamb
=
25°C to 70°C; Voo
=5
V; Vss
=0
V
Min.
ALE pulse width
Address set-up before ALE
Address hold from ALE
RD, WR pulse width
Data set-up before WR t
Data hold after WR t
Data hold after RD t
RD I to data out
Address float to RD I
CS or CS before ALE
CS or CS after WR or RD
tLL
tAL
tLA
tcc
tow
two
tOR
tRo
tAFC
tcs
tsc
Typ.
Max.
120
60
45
400
433
33
o
150
100
100
95
250
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
629
SAB 81C5x
Timing waveforms
Read
L
ALE
tAL
Bus
Floating
tlA
I
Address
tAFt
~
tRO
Floating
(SICS
Floating
Datal
I
~_,,=:J ________________ ~~I__---___---____---___ _
Write
L
ALE
I
I
tow
Bus
Floating
I
Address
I
(SICS
630
FloClting
i
DQtal
two
Floating
SAB 81C52P
256 x 8-Bit Static CMOS RAM
NMOS-Compatible
Preliminary data
CMOS circuit
The SAB 81 C 52 P is a CMOS silicon gate, static random access memory (RAM), organized
as 256 words by 8 bits. The multiplexed address and data bus allows to interface directly
to 8-bit NMOS microprocessors/microcomputers without any timing or level problems,
e.g. the families SAB 8085, SAB 8088, SA~ 8048, SAB 8051. and SAB 80515.
All inputs and outputs are fully compatible with NMOS circuits, except CS 1. Data retention is given up to VDD ;;: 1.2 v.0) The SAB 81 C 52 P has three different inputs for two chip
select modes which allow to inhibit either the address/data lines (AD 0 ... AD 7) and the
control lines (WR, RD, ALE, CS 2, CS 3). or only the control lines RD, WR.
The power consumption is max. 5.5 ',JW in standby mode and max. 2.75 mW in operation.
In standby mode, the power consumption will not increase if the control inputs are on
undefined potential.
Features
• 256 x 8-bit organization
• standby mode
• compatible with the ',JC/',JP families SAB 8085, SAB 8088, SAB 8048, SAB 8051.
the new SAB 80515, etc.
• very low power dissipation
• data retention up to VDD ;;: 1.2 VO)
fJ three different chip select inputs for two chip select modes
• no increasing power consumption in standby mode·if the control inputs are on
undefined potential
'Values for applications up to + 110°C upon request.
AG 10/84
631
256 x 8 Bit Static CMOS RAM
NMOS-Compatible
SAB 81C52P
Pin configuration
(top view)
ADO
1
16 Voo
ADI
2
15 RO
AD2
14 WR
AD3 4
13 ALE
ADt. S
12 (SI
ADS 6
11 AD7
Vss
7
10 AD6
(S2
8
9 (S3
Pin designation
Pin No. Symbol
1-6
10. 11
12
13
14
15
16
7
8
9
632
Function
AD0-7
Address/data lines
CS 1
Chip select 1 (standby)
active low; inhibits all lines including control lines
Address latch enable
Write enable
Read enable
Power supply
ALE
WR
RD
Voo
Vss
CS2
CS3
GND
Chip select 2; inhibits control inputs RD. WR
Counterpart to CS 2
253 x 8 Bit Static CMOS RAM
NMOS-Compatible
SAB 81C52P
Logic symbol
[Sl
[52
[53
SAB
ALE
81C52P
Address/data
bus, 8 bits
Ri5
WR
Truth table
L
H
H
H
H
H
*X
*X
*H
*H
H
H
L
X
L
L
X
H
L
L
L
L
L
H
X
X
*
H
H
L
X
X
floating (tristate)
addresses to memory
data from memory
data to memory
floating (tristate)
floating (tristate)
standby
store addresses
read
write
none
none
*: Level = Vss .. , VDD
X: Level = LOW or HIGH
633
256 x 8 Bit Static CMOS RAM
NMOS-Compatible
SAB 81C52P
Block diagram
---'\
rV
Gated
row
decoder
Address
latches
A2 ... A7
32 x 64
Matrix
Read logic
-
Write logic
r-
r-
Gated column
decoder
!--
~
Address
latches
AO, A1
...,
'(
7
ADO ... AD7
Bus
interface
.J'o,.
~
ALE
RD
WR
C51
C52
C53
634
Conlorol
logic
SAB 81 C52P
256 x 8 Bit Static CMOS RAM
NMOS-Gompatible
Maximum ratings
Maximum ratings are absolute limits. The integrated circuit may be destroyed if only a
single value is exceeded.
Supply voltage referred to GND (Vss)
All input and output voltages
Voo
V'M
Total power dissipation
Power dissipation for each output
Junction temperature
Storage temperature
Thermal resistance
Ptot
Po
7j
Tstg
RthSA
-0.3 to 6
Vss -0.3
Voo +0.3
250
50
125
-55 to 125
70
V
V
V
mW
mW
°C
°C
K/W
Operating range
In the operating range, the functions shown in the circuit description will be fulfilled.
Deviations from the electrical characteristics may be possible.
Supply voltage
Ambient temperature
to 5.5
I 4.5
-40 to 85*)
.) Values for applications up to 110°C upon request
635
256 x 8 Bit Static CMOS RAM
NMOS-Compatible
SAB 81C52P
Electrical Characteristics
The electrical characteristics include the guaranteed tolerance of the values which the IC
stays within for the specified operating range.
The typical characteristics are average values which can be expected from production.
Unless otherwise specified. the typical characteristics apply to Tamb and the specified
supply Voltage.
DC characteristics
T.mb = -40 to +85°CO); Voo
= 4.5
to 5.5 V; Vss = 0 V
Test conditions
Standby supply current
Supply current
Standby voltage for data retention
L input current (for each input)
Output leakage current
100
L input voltage
H input voltage
L output voltage
H output voltage
L input voltage CS 1
H input voltage CS 1
V'L
ViH
VOL
VQH
V'L
100
100K
Values
636
for
applications up to
110·C
upon request
0.8
V
0.4
V
V
V
V
1.2
V,=Ot06V
Vo = 0 to 6 V
tristate
} except CS 1
2.2
IOL = 1 mA
IOH = 1 mA
2.6
1
4
AC characteristics
Tomb = -40 to 85°CO). Voo = 4.5 to 5.5 V; Vss = 0 V
0)
1
1
fJA
fJA
V
fJA
fJA
500
~'H
ALE pulse width
ALE LOW to RD LOW
RD HIGH to ALE HIGH
ALE LOW to WR LOW
WR HIGH to ALE HIGH
Address setup before ALE
Address hold after ALE
WR or RD pulse width
Data setup before WR
Data hold after RD
Chip select (2. 3) before RD. WR
Chip select (2. 3) after RD. WR
Chip select 1 before ALE
Chip select 1 after RD. WR
Output delay time
Input capacitance against Vss
(for each input)
max.
1
f = 1 MHz
Voo
I'L
min.
min.
tLHLL
tLLRL
tRHLH
tLLWL
tWHLH
tAVLL
tLLAX
tWLWH
tOVWH
tRHOX
tcs
tsc
tCSLH
tCSWH
tRLOV
C,
max.
100
50
30
50
30
25
20
250
100
50
50
50
20
50
200
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
256 x 8 Bit Static CMOS RAM
NMOS-Compatible
SAB 81C52P
Timing diagram
ALE
CS 2/CS 3
CS 1
I
-::j,
tCSLH
637
256 x 8 Bit Static CMOS RAM
NMOS-Compatible
Application circuit
SAB 81 C 52 P with the
~C
SAB 81C52P
SAB 8051
.sv
401
19
d5'F~
10P~
Vee
20\1
vss
XTALl
rL
18
XTAL2
SAB 8051
21
P2.0 22
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7 f-=-
SAB 8751
.sv
fl.
1~~F
23
:zt
9 RESETI Vpo
'2S
rzt
'27
'28
31 EAIVOD
,,,{
Pl.0 ~
Pl.l ~
Pl.2
PU ~
Pl.4 ~
Pl.S ~
Pl.6 ~
Pl.7 ~
-.!Q.
P3.0 (RXD)
PO.O
PO.l
PO.2
PO.3
PO 4
PO.S
PO.6
PO.7
~ P3.1 (TXD)
P3.2
-¥
-1l
(INTO)
P3.3 (mTi)
--!.; P34 (TO)
--.!2 P3 S (Tl)
16 P3.6 (WR)
;---1l P3.7 (RD)
ALE/PROG
30
liD
l
~
.Sv
[/0
I
i
/
39
38
37
36
3S
34
33
32
ADO
AD 1
AQ 2
AD 3
AD4
ADS
AD6
AD7
?SEN
m
129
RD
WR
.SV
638
I
I
Voo
Vss
i
ALE
Power
faIlure
logic
GNO
0---
CS 2
CS1
-U-
SAB
81 (52 P
256.8 bits
RAM
HYB 4164-P1, HYB 4164-P2,
HYB 4164-P3
65,536-Bit Dynamic Random Access
Memory (RAM)
• 65,536 X 1 bit organization
• Industry standard 16-pin JEDEC configuration
• Single +5 V ± 10% power supply
• Low supply current transients
• CAS controlled output providing latched
or unlatched data
• Low power dissipation
- 150 mW active (max.)
- 20 mW standby (max.)
•
• All inputs and outputs TTL compatible
• High over- and undershooting capability
on all inputs
• Common 1/0 capability using
"early write" operation
120 ns access time,
220 ns cycle (HYB 4164·P1)
150 ns access time,
280 ns cycle (HYB 4164·P2)
200 ns access time,
330 ns cycle (HYB 4164-P3)
• Read-Modify-Write, RAS-only
refresh, hidden refresh
• 256 refresh cycles with 4 ms long refresh period
• Page Mode Read and Write
Pin Names
Pin Configuration
NCC~
16 ::JVss
A0 - A7
Address Inputs
15 ::J CAS
CAS
Column Address Strobe
WET 3
14 ::J DO
DI
Data In
mC4
13 ::J A6
NC
No Connection
12 ::J A3
DO
Data Out
DI
C 2
c: 5
A2 c: 6
A, c: 7
Vee c: 8
A0
11 ::J A4
RAS
Row Address Strobe
10 ::J As
WE
Write Enable
9::JA7
Vcc
Power Supply (+5 V)
Vss
Ground (OV)
The HYB 4164 is a 65536·word by 1·bit, MOS
random access memory circuit fabricated with
Siemens new 5-Volt only n-channel silicon gate
technology, using double layer polysilicon. To
protect the chip against a-radiation a Siemens
proprietary chip cover is used. The HYB 4164 uses
singletransistor dynamic storage cells and dynamic
control circuitry to achieve high speed at very low
power dissipation.
Multiplexed address inputs permit the HYB 4164 to
be packaged in an industry standard 16-pin dualin-line package.
System oriented features include single power
supply with ± 10% tolerance, on-chip address and
data latches which eliminate the need for interface
registers and fully TTL compatible inputs and outputs, including clocks.
In addition to the usual read, write and readmOdify-write cycles, the HYB 4164 is capable of
early and delayed write cycles, RAS-only refresh
and hidden refresh. Common 1/0 capability is given
by using "early write" operation.
AG 1/84
639
HYB 4164
Block Diagram
Clock
!
2S6K Bits
Address
Buffer
Column Decoder
ACO- AC7
4- Bit Data Bus
DO]
103
4- Bit 110 Buffer
A8
-
VCC
-
VSS
-
AS
Buffer
BIAS
Generator
AC8
ARB
-VBB
Functional Description
Device Initialization
Since the HYB 41256 is a dynamic RAM with a
single 5V supply, no power sequencing is required.
For power-up, an initial pause of 200 microseconds
is necessary for the internal bias generator to
establish the proper substrate bias voltage. To
initialize the nodes of the dynamic circuitry, a
minimum of 8 active cycles of the Row Address
Strobe (RAS) has to be performed. This is also
necessary after an extended inactive state of
greater than 4 milliseconds.
654
110 Decoder
$11
WE
Buffer
01
Buffe r
l
00
Buffer
f
I
01
00
Addressing (AO-AS)
For selecting one of the 262,144 memory cells, a
total of 18 address bits are required. First 9 Row
Address bits are set up on pins AO through A8 and
latched into the row address latches by the Row
Address Strobe (RAS). Then the 9 column address
bits are set up on pins AO through A8 and latched
into the column address latches by the Column
Address Strobe (CAS). All input addresses must be
stable on the falling edges of RAS and CAS. It
should be noted that RAS is similar to a Chip
Enable in that it activates the sense amplifiers as
well as the row decoder. CAS is used as a chip select
activating the column decoder and the input and
output buffers.
HYB 41256
Write enable (WE)
Hidden refresh
The read or write mode is selected with the WE
input.A logic high (VIH) onWE dictates read mode;
logic low (VIL) dictates write mode. The data input
is disabled when read mode is selected. When WE
goes low prior to CAS, data ouput (DO) will remain
in the high-impedance state for the entire cycle
permitting common 1/0 operation.
RAS-only refresh cycle may take place while
maintaining valid output data. This feature is
referred to as Hidden Refresh. Hidden Refresh is
performed by holding CAS at VIL of a previous
memory read cycle.
Data input (01)
Data is written during a write or read-modify-write
cycle. The falling edge of CAS or WE strobes data
into the on-chip data latch. In an early write cycle
WE is brought low prior to CAS and the data is
strobed in by CAS with setup and hold times
referenced to this signal.
Refresh cycle
A refresh operation must be performed at least
every four milliseconds to retain data. Since the
output buffer is in the high impedance state unless
CAS is applied, the RAS-only refresh sequence
avoids any signal during refresh. Strobing each of
the 256 row addresses (AD through A7) with RAS,
causes all bits in each row to be refreshed.
CAS can remain high (inactive) for this refresh
sequence to conserve power.
Data output (DO)
The output is three-state TTL compatible with a
fan-out oftwo standard TTL loads. Data Out has the
same polarity as Data In. The output is in a high
impedance state until CAS is brought low. In a read
cycle or read-write cycle, the output is valid after
tRAC from transition of RAS when tRCD (min) is
satisfied, or after tCAC from transition of CAS when
the transition occurs after tReD (max). In an early
write cycle, the output is always in the high
impedance state. In a delayed write or read-modifywrite cycle, the output will follow the sequence for
the read cycle. With CAS going high the output
returns to the high impedance state within tOFF.
Page mode
Page-mode operation allows effectively faster
memory access by maintaining the row address
and strobing random column addresses onto the
chip. Thus, the time necessary to setup and strobe
sequential row addresses for the same page is no
longer required. The maximum number of
columns that can be addressed in sequence is
determined by tRAS, the maximum RAS low pulse
width.
655
I
HYB 41256
Absolute Maximum Ratings*)
Operating Temperature Range
Storage Temperature Range
Voltage on Any Pin Relative to VSS
Voltage on 01 Relative to VSS
Power Dissipation
Data Out Current (Short Circuit)
0 to 70 'C
-65 to 150 'C
-1 to 7V
-1 to 11 V
1W
50mA
DC Characteristics
TA~O
to 70 'C, VSS~OV, VCC~+5 V ±10%
Symbol
Parameter
VIH
Lim it values
Min.
Max.
Input high voltage
(all inputs)
2.4
VCC+1
VIL
Input low voltage (all inputs)
-1.0
0.8
VOH
Output high voltage
2.4
-
VOL
Output low voltage
0.4
ICC1
Average VCC supply current
-12 tRC~220ns
-15 tRC~260ns
-20 tRC~330ns
85
70
60
ICC2
Standby VCC supply current
ICC3
Average VCC supply current
during RAS-only refresh cycles
-12 tRC~220ns
-15 tRC~260ns
-20 tRC~330ns
ICC4
-
Test condition
V
1}2)
-
31
41
5
mA
65
55
45
31
Average VCC supply current
during page mode
-12tPC~120ns
65
55
45
-15 tPC~150ns
-20tPC~200ns
II(L)
Input leakage current
(any input)
IO(L)
Output leakage current
(CAS at logic 1,
0,,; Vout,,; 5.5)
VCC
VSS
-
10
VCC su pply voltage
4.5
5.5
VSS supply voltage
0
0
Notes see page 5
656
Unit
/LA
-
11
V
HYB 41256
Capacitance
Limit values
Symbol
Parameter
Cll
Input capacitance (AO-ASI
6
CI2
Input capacitance (RAS, 011
7
CI3
Input capacitance (CAS, WEI
CO
Output capacitance (DO,
CAS~VIH to disaQle outputl
Min.
-
Max.
Unit
Test condition
5
pF
8
I
*1 Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. Exposureto absolute maximum rating conditions for extended periods may affect device reliability.
11 All voltages referenced to VSS.
21 Overshooting and undershooting on input levels of 6.5V or -2V for a period of 30ns max. will not
influence function and reliability of the device.
3) ICC depends on frequency of operation. Maximum current is measured at the fastest cycle rate.
41 RAS and CAS are both at VIH.
51 Effective capacitance calculated from the equation
C ~ I·Llt
'hLlV
~W!t
~
3V or measure d Wit
'hB oonton meter.
657
HYB 41256
AC Test Conditions
Input pulse levels
0 to 3.0V
Input rise an fall times
5ns between 0.8 and 2.4V
Input timing reference levels
0.8 to 2.4V
Output timing reference levels
0.4 to 2.4V
Output load
equivalent to 2 standard
TTL loads and 100pF
AC Characteristics
TA~O
to 70 T, VCC~5 V ±10% (unless otherwise specified; see notes 6, 7, 8)
Limit values
Symbol
Parameter
HYB41256
-15
-12
Min.
Max.
Min.
Unit
-20
Max.
Min.
Max.
tRC
Random read or write cycle time 9)
220
tRWC
Read-modify-write cycle time 9)
265
tRAC
Accesstimefrom RAS
tCAC
Accesstimefrom CAS 10)11)12)
tRAS
RAS pulse width
120
104
150
10·
200
104
tCAS
CAS pulse width
60
-
75
-
100
-
4
-
4
-
4
120
-
10)11)
-
tREF
Refresh period
-
tRP
RAS prechargetime
90
tCRP
CASto RAS prechargetime
10
tRCD
RAS to CAS delay time
30
tRSH
RAS hold time
60
tCSH
CAS hold time
120
tASH
Row address setup time
0
tRAH
Row address hold time
20
tASC
Column address setup time
0
13)
tCAH
Column address hold time
30
tAR
Column address hold time
referenced to RAS 14)
90
tT
Transition time (rise and fall) 6)
3
tRCS
Read command setuptime
tRCH
Read command hold time
referenced to CAS 15)
tRRH
Read command hold time
referenced to RAS"15)
310
-
120
-
60
-
Output buffer tu rn-off delay 16)
Write command setup time
tWCH
Write command hold time
0
17)
r--
100
I--- 30
75
-
-
20
0
-
50
30
105
50
0
-
25
45
ms
100
200
0
25
0
35
-
-
3
50
r-30
-
'40
I--- I
35
ns
100
0
r--
30
10
200
13S
3
I--- 0
-
-
100
150
0
-
-
-
40
390
75
-
I--- -
75
60
-
330
150
10
25
tWCS
658
I--- -
0
tOFF
Notes see page 7
-
260
0
50
I---
I--- 55
ns
HYB 41256
Limitvalues
Symbol
Parameter
HYB41256
-15
-12
Min,
tWCR
Write command hold time
referenced to RAS 14)
tWP
Write com mand pu Ise width
Max,
Min,
100
Max,
120
Write command to RAS lead time
tCWL
Write command to CAS lead time
tDS
Data in setup time 18)
0
tDH
Data in hold time 18)
40
tDHR
Data in hold time
referenced to RAS 14)
100
tCWD
CAS to WE delay 17)
60
tRWD
RASto WE delay 17)
120
tRRW
RMW cycle RAS pulse width
165
tCRW
RMW cycle CAS pulse width
105
40
tPC
Page mode cycle time 9)
120
tPRWC
Page mode read-write cycle time
160
tCP
Page mode CAS precharge time
50
55
0
-
-
Max,
~
45
-
Min,
155
-
tRWL
Unit
-20
45
120
75
150
200
125
150
195
65
~
0
,---
55
f--- -
155
ns
f---
100
r-200
f---260
r--160
I---
200
I---
255
r--90
Notes:
6) VIH and VIL are reference levels to measure timing of input signals. Also, transition times are measured
between VIH and VIL.
7) An initial pause of 200/-Ls is required after power-up followed by a minimum of eight initialization cycles
prior to normal operation.
8) The time parameters specified here are valid for a transition time of tT ~ 5ns for the input signals.
9) The specification for tRC (min), tRWC (min), and page-mode cycle time (tPC) are only used to indicate
cycle time at which proper operation over full temperature range (0 'C:5 TA:5 70 'C) is assured.
10) Measured with a load equivalent to two TTL loads and 100pF,
11) Assumes that tRCD:5 tRCD (max), IftRCD is greater than the maximum recommended value shown in
this table, tRAC will increase by the amount that tRCD exceeds the value shown,
12) Assumes that tRCD ~ tRCD (max),
13) Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a
reference point only; iftRCD is greater than the specified tRCD (max) limit, then access time is controlled
exclusively by tCAC,
14) tRCD + tCAH ~ tAR min, tRCD + tDH ~ tDHR min, tRCD + tWCH ~ tWCR min,
15) Either tRRH or tRCH must be satisfied for a read cycle,
16) tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced
to output voltage levels.
17) tWCS, tCWD and tRWC are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only: IftWCS ~ tWCS (min), the cycle is an early write cycle and the Data Outwill
remain open circuit (high impedance) throughout the entire cycle; if tCWD ~ tCWD (min) and tRWD ~
tRWD (min) the cycle is a read-write cycle and the Data Out will contain data read from the selected cell.
If neither of the above sets of conditions is satisfied, the condition of the Data Out (at access time) is
indeterminate.
18) tDS and tDH are referenced to the leading edge of CAS in early write cycles, and to the leading edge of
WE in delayed write of read-modify-write cycles.
659
I
HYB41256
Waveforms
Read cycle
RAS
VIHVIL-
CAS
VIHVIL-
Address
VIHVIL-
WE
VIHVIL-
Data Out
VOHVOL -
Write cycle (early write)
RAS
ii-----
IRAS _ ' R C
-~1 t==IRP~
r
~',~=~
F - - - - I C S H - - - - - - --:-t--'[RP
I
I
IRWl----~ I
I I
I
'---------IRSH - - - - - I I
I
I
tRCOH
----I[AS--·---
f-I
VIH\IlL -
Address
VIHVil -
WE
VIHVll-
Data In
VIHVll-
Dota Out
660
VOHVOl-
_C.J>.._--'=='-
High Z
r-----
HYB41256
Read-modify-write or late write cycle
VIHVll-
VIHVll-
Address
VIHVll-
WE
VIHVll-
Oata In
VIHVll-
Data Out
VDHVOL -
High Z
Valid Data
RAS-only refresh cycle
(DI and WE ~ don't carel
tR[--tRAS
RAS
VIHVIL-
CAS
VIHVIL-
Address
VIHVIL -
661
HYB41256
Hidden refresh cycle
Re.d Cycle
VIHVIL-
VIHVIL-
Address
VIHVIL-
WE
VIHVIL-
O.t. Out
VOHVOL-
Page-mode read cycle
Addresses
o.t.
662
Out
RAS only Refresh Cycle
HYB41256
Page-mode write cycle
CAS
VIHVll-
Addresses
WE
VIHVll-
Data In
Data Out
0~~= - - - - - - - - - - - - H , g h Z - - - - - - - - - - - - -
Page-mode read-write cycle
VIHVll-
VIHVll-
Addresses
VIHVll-
VIHVIL -
Data Out
Data In
VOHVOl-
------=~~1i!i.t
VIHVll-
663
HYB41256
Address Decoder Scrambling
(without redundancy)
The evaluation and incoming testing of RAMs normally requires a description of the internal address
scrambling of the device in order to check for 'worst case' pattern.
Internal address scrambling
RO
(511
(PinS)
AO
(Pin6)
A2
RO
(0
Ooto Stored =01
A7R=O
A8R=O
512 Sense Refresh Amps
(Pin71
Al
(Pin8)
V((
(Pin91
A7
Ooto Stored = iii
Ooto Stored=D!
(Pinl01 AS
A7R=1
A8R=0
A7R=0
A8R=1
512 Sense Refresh Amps
(Pinlll A4
Doto Stored =iii
(Pin121 A3
R511
(511
A7R=1
A8R=1
RA5
(Pin4)
WE
(Pin31
Ol
(Pin21
AS
(Pin 11
VSS
(PinI6)
(AS
(Pin 151
00
(PinI4)
A6
(Pin131
R511
(0
Address decoder scrambling AO
RO
RO= [AO ·AlI-IAO·A21
Al
External
Row
Address
A2
R2
A3
A4
RJ
AS
RS
A6
R6
A7
R7
A6
R6
A6
External
Internal
Row
Address
R4
(0
A7
(I
A6
(2
Column
AS
CJ
Address
A4
(4
AJ
(5
A2
(6
Al
(1
AO
(6
Note: The logic symbols are 'used solely
to indicate the logic function.
664
R1= [AI·AlI- [Ai ·A21
RI
Inhi!rna\
Column
Address
HYB 41256
Redundancy
Redundancf concept
The HYB 41526 takes advantage ofthe redundancy
concept for increasing yield. This is done by
providing the chip with a total of 8 spare rows and 4
spare columnj:Jairs. Two spare rows can be
selected independently in each of four 64K cell
arrays, and two spare column pairs can be selected
independently in each of two 128K cell blocks. The
spare lines can be selected by spare decoders
which have to be programmed by laser technique
during wafer probe.
Laser technology
For activation of redundant circuitry a laser pulse is
used to open polycide links within the spare row
and spare column decoders. The laser technique is
used because it is mature and has proven reliable in
a number of semiconductor applications including
the implementation of redundant memory
circuitry. Due to the fact, that the laser beam is very
fine and can easily and accurately be positioned,
and that it incorporates the energy for a controlled
blow up of the polycide links, the laser technique is
well suited for highly complex memory circuitry.
All that results in a more efficient use of chip real
estate.
Signature
With 01 at VIHR and performing at least one RASonly cycle with a cycle time of tRCR on any address
combination, in the case of non-repaired devices
the Data Output is in the high-performance state as
in normal RAS-onlycycles. For repaired devices the
Data Output will go to VOLR or VOHR after the access time tRACR.
Individual bit map recognition
If the test for signature has shown a repaired
device, additional tests can be performed to
reognize which addresses have been repaired and
how they are replaced by spare lines.
Rowand column redundancy can be recognized
independently.
Row redundancy
Row redundancy can be recognized with 01 at VIHR
and CAS at high, and RAS-only cycles on all 512 row
address combinations. The data output is low
(VOLR) for non-repaired addresses, and is high
(VOHR) for repaired addresses only. Within each
64Kcell array, spare row 1 is always used if only one
row is to be replaced. If two rows are to be replaced
in an 64K cell array, spare row 2 is used to replace
the defective row with the higher address.
Column redundancy
Redundancy testability (roll-call mode)
With the redundancy concept two categories of
devices, repaired and non-repaired ones, will be
available. These two categories have to be separated easily and reliably by both, the manufacturer
and the user (signature). When testing repaired
devices, the reconfigurated address scrambling
which results from activating spare rows and
columns has to be taken into account for efficient
device testing (individual bit map recognition).
The HYB 41256 has the capability of performing
these two novel functions. It is done with a simple
electrical test at the begi nning of the final test or
incoming inspection of each device (roll-call
mode). The roll-call mode for performing both
signature and individual bit map recognition can
be activiated with 01 at VIHR (10 V ± 10%).
Column redundancy can be recognized with 01 at
VIHR, and early write cycles with tRCDR 'S tRCO
(min) on all 512 column address combinations.
A8 row must be used to distinguish between the
two 128K cell blocks. The data output is low (VOLR)
for non-repaired addresses, and high (VOHR) for
repaired addresses. Within each 128K cell block,
spare column pair 1 is always used if only one
column is to be replaced. Otherwise, spare column
pair 2 is used to replace the defective column with
the higher address.
665
HYB41256
Recommended operating conditions
Roll-call mode
DC operating conditions and characteristics (Full operating voltage and temperature range unless otherwise
specified.)
Limitvalues
Symbol
Parameter
VCC
VSS
Supply voltage HYB 41256-12, -15, _20 '1
VIH
VIHR
Unit
Min.
Typ.
Max.
4.75
0
5.0
0
5.25
0
Logic 1 voltage: All inputs (except 01)
2.4
-
VCC+1
Logic 1 voltage: 01 '121
9.0
10
VIL
Logic 0 voltage: All inputs 11
-1.0
VOHR
Output logic 1 voltage lout ~-5 mA 11
2.0
VOLR
Output logic 0 voltage lout ~-4.2 mA 11
-
11
11
V
0.8
-
0.4
1) All voltages referenced to VSS.
2) VIHR at 01 must only be used for the roll-call-mode test and not for normal memory test~ or applications.
To avoid device damage, VIHR is to be applied after the initialization conditions (initial pause of 200fLS and
8 cycles) have been satisfied, and must never exceed 11 V.
AC operating conditions and characteristics
(Full operating voltage and temperature range unless otherwise specified.)
Limit values
Symbol
Parameter
Unit
HYB41256
-15
-12
-20
Min.
Max.
Min.
Max.
Min.
Max.
tRCR
Roll-call cycle time
330
-
390
-
490
-
tRCDR
Roll-call RAS to CAS delay
-
30
-
30
35
35
tRACR
Roll-call RAS access time
180
tCACR
Roll-call CAS access time
90
666
-
225
,--- 115
300
I--- -
150
ns
HYB41256
Column Redundancy
Early CAS - early write cycle
(01 at VIHR, tRCO ~ tRCO (min), row addresses AD to A7
~
don't care)
VIHVIL-
VIHVIL -
VIHVIL-
Address
VIHVIL-
Data Out
0~~~=
-----
Row Redundancy and Signature
RAS-only cycle
(01 at VIHR, WE
~
don't care)
RAS
VIHVIL-
CAS
VIHVIL -
Address
VIHVIL-
Data Out
VOHRVOLR-
667
HYB41256
Siemens 256K DRAM Chip Topology
VSS
,--
Column Decoder
64K Memory Array
- ~
- 1"
- i
... '"
A5 -
VCC
AO
~
RAS
and
RAS
ill
Clocks
CAS
512+4 Sense Amplifier
A1
A2
A3
CD
~
~
A4
A6
A7
1Spare ROW<
Column Decoder
~
-
2 Spare Column Pairs
to
V..0
A8 Buff.r
-Ae
Nibble
Decoder
and
Shift
Register
512+4 Sense Amplifier
64K Memory ArrQy
L-
668
~
Column Oecoder
~
Read/Write
Clocks
01/00
Buffer
01
WE
DO
HYB 41257-12/-15/-20
262,144-Bit Dynamic Random
Access Memory (RAM)
• Fast nibble mode on read and write cycles
via addresses A8 row and A8 column
30 ns access time
65 ns cycle time (HYB 41257-12)
40 ns access time
80 ns cycle time (HYB 41257-15)
50 ns access time
110 ns cycle time (HYB 41257-20)
• 262,144 x 1-bit organization
• Industry standard 16 pins
• Single +5V supply, ±10% tolerance
• Low power dissipation:
- 385 mW active (max.)
- 28 mW standby (max.)
• 120 ns access time
220 ns cycle time (HYB 41257-12)
150 ns access time
260 ns cycle time (HYB 41257-15)
200 ns access time
330 ns cycle time (HYB 41257-20)
• Read, write, read-modify-write,
RAS-only-refresh, hidden refresh
• All inputs and outputs TIL compatible
• Common 1/0 capability using "early write"
operation
• Valid data during CAS precharge until start
of next nibble cycle provides higher system
data rate
Pin configuration
•
•
•
•
On-chip substrate bias generator
Three-state data output
256 refresh cycles with 4 ms refresh period
Redundancy incorporated for increasing yield
- activation via laser links
- roll-call-mode as pretest with 01 at 10V provides:
redundancy signature individual address
decoder scrambling
Pin names
A8[~JVSS
A0 - A8
Address Inputs
OI [ 2
15 TeAs
CAS
Column Address Strobe
WE[ 1
14 JOO
01
Data In
DO
Data Out
=[ 4
AO [ 5
HYB
41257
13 JA6
12 J A3
RAS
Row Address Strobe
Write Enable
A2 [ 6
11 JA4
A1 [ 7
10 JAS
WE
vee [ 8
9 JA7
VCC
Power Supply (+5V)
VSS
Ground (OV)
The HYB 41257 is a 262,144 word by 1-bit dynamic
Random Access Memory. This 5V-only component
is fabricated with Siemens new high performance
N-channel silicon gate technology. The use of
tantalum polycide provides high speed. A Siemens
proprietary chip cover protects the chip against
a radiation.
Nine multiplexed address inputs permit the
HYB 41257 to be packaged in an industry standard
16-pin dual-in-line package. System-oriented
features include single power supply with ±10%
tolerance, on-chip address and data registers which
eliminate the need for interface registers, and fully
TIL compatible inputs and output, including clocks.
In addition to the usual read, write and readmodify-write cycles, the HYB 41257 is capable of
early and late write cycles, RAS-only refresh, and
hidden refresh. Common 1/0 capability is given by
using "early write" operation.
Nibble Mode is a new feature of the HYB 41257
allowing the user to perform a serial access of 4
bits at a high data rate by using an on-chip nibble
shift register which is controlled by one set of
addresses on pin 1(A8 Rowand A8 Column) and the
CAS clock only.
The HYB 41257 has the capability of using laser links
to perform redundancy. With the roll-call mode,
which is a new test feature, the user can separate
repaired devices easily, and additionally gets
information on the individual row and column
addresses which have been repaired and how they
are substituted by redundant lines.
AG 10/84
669
HYB41257
Block Diagram
AO
A1
A2
A3
A4
AS
A6
A7
------
aSpar. Rows
ClK
.1::
Memory
t-
e.
~
~
e
~
.3
8
Array
~
,.
ARO-AR7
f0
.
{}.
tt
2S6K Bits
Address
Buffer
ACO"AC7
Column Decoder
4· Bit Data Bus
001
103
4-Bit 1I0;Buffer
A8
VCC
VSS
-
ACB
AS
Buffer
Nibble Decoder
and
4'Bit Shift Register
ARB
BIAS
Generator
~
f--VBB
WE
Buffer
j
OJ
Buffer
DO
Buffer
DI
DO
!
I
Functional Description
Device Initialization
Adressing (AO-AS)
Since the HYB 41257 is a dynamic RAM with a single
5V supply, no power sequencing is required. For
power-up, an initial pause of 200 microseconds is
necessaryforthe internal bias generator to establish
the proper substrate bias voltage. To initialize the
nodes of the dynamic circuitry, a minimum of 8
active cycles of the Row Address Strobe (RAS) has
to be performed. This is also necessary after an
extended inactive state of greater than 4 milliseconds.
For selecting one of the 262,144 memory cells,
a total of 18 address bits are required. First
9 Row Address bits are set up on pins A0 through A8
and latched into the row address latches by the
Row Address Strobe (RAS). Then the 9 column
address bits are set up on pins A0 through A8 and
latched into the column address latches by the
Column Address Strobe (CAS). All input addresses
must be stable on the falling edges of RAS and CAS.
It should be noted that RAS is similar to a Chip
Enable in that it activates the sense amplifiers as
well as the row decoder. CAS is used as a chip select
activating the column decoder and the input and
output buffers.
670
HYB 41257
Write enable (WE)
Hidden refresh
The read or write mode is selected with the WE
input. A logic high (VIH) on WE dictates read mode;
logic low (VIL) dictates write mode. The data
input is disabled when read mode is selected.
When WE goes low prior to CAS, data output (DO)
will remain in the high-impedance state for the
entire cycle permitting common 1/0 operation.
RAS-only refresh cycle may take place while
maintaining valid output data. This feature is
referred to as Hidden Refresh. Hidden Refresh is
performed by holding CAS at VIL of a previous
memory read cycle.
Refresh cycle
Data is written during a write or read-modify-write
cycle. The falling edge of CAS or WE strobes data
into the on-chip data latch. In an early write cycle
WE is brought low prior to CAS and the data is
strobed in by CAS with setup and hold times
referenced to this signal.
A refresh operation must be performed at least
every four milliseconds to retain data. Since the
output buffer is in the high impedance state unless
CAS is applied, the RAS-only refresh sequence
avoids any output signal during refresh. Strobing
each of the 256 row addresses (A0 through A7) with
RAS causes all bits in each row to be refreshed.
CAS can remain high (inactive) for this refresh
seq uence to conserve power.
Data output (DO)
Nibble-mode cycle
The output buffer is three-state TTL compatible
with a fan-out of two standard TTL loads. Data Out
has the same polarity as Data In. The output is in a
high impedance state until CAS is brought low. In a
read cycle or read-write cycle, the output is valid
after tRAC from transition of RAS when tRCD (min) .
is satisfied, or after tCAC from transition of CAS
when the transition occurs after tRCD (max.).
In an early write cycle, the output is always in the
impedance state. In a delayed write or read-modifywrite cycle, the output will follow the sequence for
the read cycle. With CAS going high and RAS being
high, the output returns to the high impedance state
within tOFF.
For nibble-mode read cycles, the data output
shows a novel function that gives advantages for
system application. With RAS low the data output
remains valid after and during CAS high. That gives
time for a proper strobing of the data despite of
system time tolerances, and increases the system
data rate because the minimum CAS low time,
tCAS and tNAS, can be realized more easily. With
CAS going low for the next nibble cycle the data
output returns to the high-impedance state within
tNOFF. In a read, late write, or read-modify-write
mode for a normal cycle or the last nibble cycle,
the data output condition depends on whether CAS
or RAS is brought high first. With CAS going high
and RAS adow, the data output is valid until RAS
goes high and returns to the high-impedance state
within tOFF referenced to RAS. With CAS being
low at RAS high, the data output is valid until CAS
goes high and returns to the high-impedance state
within tOFF referenced to CAS.
Nibble-mode operation allows a very fast serial
data streaming up to 4 bits by applying only one
set of addresses for the first bit to be accessed as
normal (tCAC). By holding RAS low, only CAS has
to be cycled up and then down for reading or
writing the next 3 bits at a high data rate with tNAC
tCAC. After 4 bits have been accessed, the following
bit will be the same as the first bit accessed.
Address on pin 1 (row address AS and column
address AS) is used to select 1 ofthe 4 nibble bits for
initial access. Toggling CAS causes row AS and·
column AS to be incremented by the internal shift
register with AS row being the least significant
address, and allows access to the next nibble bit.
In nibble mode, any combination of read, write,
and read-modify-write operation is possible (e.g.
first bit: read; second bit: write; third bit: readmOdify-write, etc.).
Data Input (01)
671
HYB 41257
Absolute Maximum Ratings *)
Operating Temperature Range
Storage Temperature Range
Voltages on Any Pin Re[ative to VSS
Voltage on D[ Re[ative to VSS
Power Dissipation
Data Out Current (Short Circuit)
oto + 70 'C
- 65 to + 150 "C
-1 to +7V
-1 to +11 V
lW
50 mA
D.C. Characteristics
= 0 to 70 "C, VSS = OV, VCC = +5 V ± 10%
TA
Symbol
Parameter
V[H
Limit Values
Unit
Test condition
Min.
Max.
Input high voltage (a[[ inputs)
2.4
VCC+l
V[L
Input [ow voltage (all inputs)
-1.0
0.8
VOH
Output high voltage
2.4
-
VOL
Output [ow voltage
0.4
[CCl
Average VCC supply current
-12 tRC = 220 ns
-15 tRC = 260 ns
-20 tRC = 330 ns
85
70
60
3)
5
4)
[CC2
[CC3
Standy VCC supply current
1) 2)
V
-
r-.--
Average VCC supply current
during RAS-on[y refresh
cycles
- 12 tRC = 220 ns
-15 tRC = 260 ns
-20 tRC = 330 ns
f---
mA
65
55
45
3)
f---
[CC6
Average VCC supply current
during nibble mode
-12tNC= 65 ns
-15tNC = 80 ns
-20tNC = 110 ns
II(L)
Input leakage current (any input)
[OIL)
Output leakage current
(CAS at logic 1,
0,,; Vout ,,; 5.5)
VCC
VSS
-
10
VCC supply voltage
4.5
5.5
VSS supply voltage
0
0
Notes see page 5
672
10
8
7
rIA
-
V
1)
HYB 41257
Capacitance
--Symbol
Limit values
Parameter
Min.
.. _-
CI1
Input capacitance (AO-AS)
CI2
Input capacitance (RAS, 01)
CI3
Input capacitance (CAS, WE)
CO
Output capacitance
(DO, CAS = VIH to disable output)
Max .
Unit
Test conUi!i on
6
I-7
I - - pF
5)
S
.---
I
*) Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
1) All voltages referenced to VSS.
2) Overshooting and undershooting on input levels of 6.5 V or -2 V for a period of 30 ns max. will not
influence function and reliability of the device.
3) ICC depends on frequency of operation. Maximum current is measured at the fastest cycle rate.
4) RAS and CAS are both at VIH.
5) Effective capacitance calculated from the equation C
=
16~ t with 6 V
= 3 V or measured with
Boonton meter.
673
HYB41257
A.C. Test Conditions
Input pulse levels
Input rise an fall times
Input timing reference levels
Output timing reference levels
Output load
5 ns between
oto 3.0V
0.8 and 2.4 V
0.8 to 2.4 V
0.4 to 2.4 V
equivalent to 2 standard
TTL loads and 100 pF
A.C. Characteristics
TA = 0 to +70 °C; VCC = +5V ±10% (unless otherwise specified; see notes 6, 7, 8)
Limit values
Symbol Parameter
Min.
tRC
Random read or write cycle time 9)
220
tRWC
Read-modify-write cycle time 9)
265
tRAC
ACcess time from RAS 10) 11)
tCAC
Access time from CAS 10) 11) 12)
tRAS
RAS pulse width
tCAS
tREF
Max.
-
-60
CAS pulse width
60
Refresh period
-
tRP
RAS precharge time
90
tCRP
CAS to RAS precharge time
10
tRCD
RAS to CAS delay time 13)
30
tRSH
RAS hold time
60
tCSH
CAS hold time
120
tASR
Row address setup time
0
tRAH
Row address hold time
20
tASC
Column address setup time
0
tCAH
Column address hold time
30
tAR
Column address hold time
referenced to RAS 14)
90
IT
Transition time (rise and fall) 6)
3
tRCS
Read command setup time
tRCH
Read command hold time
referenced to CAS 15)
Read command hold time
referenced to RAS 15)
Notes see page 8
674
Min.
r--- -
-75
-
75
4
-
-
100
-
4
-
4
-
75
120
35
-
200
I---
0
20
I---
25
0
I-30
35
-
3
50
3
0
-
25
-
135
0
-
-
I-0
105
50
100
r---
150
--
ns
100
0
-
ms
I--- 10
75
ns
100
10
-
200
10 4
100
30
-
200
--
60
Max.
330
390
10 4
-
-20
150
150
0
25
Max.
1---
120
10 4
tRRH
Min.
260
310
120
Unit
HYB 41257-15
-12
30
50
ns
HYB 41257
Limit values
Symbol Parameter
-15
-12
Min.
tOFF
Output buffer turn-off delay 16)
tWCS
Write command setup time 17)
tWCH
Write command hold time
40
tWCR
Write command hold time
referenced to RAS 14)
100
tWP
Write command pulse width
0
Write command to CAS lead time
tDS
Data in setup time 18)
0
tDH
Data in hold time 18)
40
tDHR
Data in hold time
referenced to RAS 14)
100
tCWD
CAS to WE delay 17)
60
tRWD
RAS to WE delay 17)
120
tRRW
RMW cycle RAS pulse width
165
tCRW
RMW cycle CAS pulse width
105
tNC
Nibble-mode cycle time 9)
65
tNAC
Nibble-mode access time from CAS 10)
-
tNAS
Nibble-mode setup time
30
tNP
Nibble-mode precharge time
25
tNRSH
Nibble-mode RAS hold time
65
tNCWL
Nibble-mode WE to CAS lead time
30
tNWRH
Nibble-mode write RAS hold time
45
tNOFF
Nibble-mode output buffer
turn-off delay 19)
0
Nibble-mode WE command hold time
-
45
55
120
155
r---
r---
r--0
r--45
r--- -
0
-
55
-155
r--150
r---
-
r----
-
-
200
125
-
r---80
ns
40
100
200
260
I
160
110
-
-
50
40
r---30
r---
50
40
-
-
85
40
55
0
30
r---
-
75
-
c---
55
120
30
Max.
50
r--- -
45
-
Nibble-mode CAS to WE delay
Nibble-mode RMW CAS pulse width
Min.
40
-0
r--- -
30
tNCRW
-20
Max.
r----
tNCWD
tNWCH
Min.
30
-0
40
Write command to RAS lead time
tCWL
Nibble-mode WE pulse width
Max.
-
tRWL
tNWP
Unit
HYB 41257-
40
-
-
105
50
75
0
r-50
Notes see page 8
675
HYB 41257
Notes:
61 VIH and VIL are refere'1ce levels to measure timing of input signals. Also, transition times are measured
between VIH and VIL.
71 An initial pause of 200 llS is required after powerup following by a minimum of eight initialization cycles
prior to normal operation.
81 The time parameters specified here are valid for a transition time of tT
= 5 ns for the input signals.
91 The specifications for tRC Iminl, tRWC Iminl, and nibble cycle time ItNCI are only used to indicate cycle
time at which proper operation over full temperature range 10 'C:oS TA:oS 70 'CI is assured.
101 Measured with a load equivalent to two TTL loads and 100 pF.
111 Assumes that tRCD :oS tRCD(maxl. If tRCD is greater than the maximum recommended value shown in
this table, tRAC will increase by the amount that tRCD exceeds the value shown.
121 Assumes that tRCD ~ tRCD Imaxl.
131 Operation within the tRCD Imaxllimit ensures that tRAC Imaxl can be met. tRCD Imaxl is specified as a
reference point only; iftRCD is greater than the specified tRCD Imaxllimit, then access time is controlled
exclusively by tCAC.
141tRCD
+ tCAH
~
tAR min, tRCD
+ tDH
~
tDHR min, tRCD
+ tWCH
~
tWCR min.
151 Either tRRH or tRCH must be satisfied for a read cycle.
161 tOFF (maxi defines the time at which the output achieves the open circuit condition and is not referenced
to output voltage levels. tOFF is referenced either to the CAS leading edge with RAS being high or to the
RAS leading edge with CAS being high.
171 tWCS, ICWD and tRWC are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only: IftWCS ~ tWCSlminl, the cycle is an early write cycle and the Data Out
will remain open circuit Ihigh impedancel throughout the entire cycle; iftCWD ~ tCWD Iminl and
tRWD ~ tRWD Iminl the cycle is a read-write cycle and the Data Out will contain data read from the
selected cell. If neither of the above sets of conditions is satisfied, the condition of the Data Out lat
access timel is indeterminate.
181 tDS and tDH are referenced to the leading edge of CAS in early write cycles, and to the leading edge of
WE in delayed write or read-modify-write cycles.
191 tNOFF Imaxl defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels. tNOFF is referenced to the CAS falling edge of the next nibble cycle
with RAS being low.
676
HYB41257
Waveforms
Read cycle
Address
Data Out
Write cycle (early write)
I
VIHVll-
CAS
Address
WE
Data In
Data Out
VIHVll-
VIH-
VIL -
VIH-
VIH-
VIL-
VDHVOL-
High Z
677
HYB 41257
Read-modify-write or write cycle
VIHVll-
CAS
VIHVll-
Address
VIHVIL-
WE
YIHVll-
Data In.
VIHVll-
Data Out
YDH-
VOL -
RAS-only refresh cycle
(DI and WE = don't carel
ill
VIHVIL-
CAS
VIHVll-
Address
678
High Z
Vulld Data
HYB41257
Hidden refresh cycle
Read Cyde
RAS only Refresh Cycle
VIHVll-
VIHVll-
Address
VIHVIL-
vIH-'lllr-1-------------t-i,.
VIL-~
Data Out
Nibble-mode read cycle
I
RAS
ill
Address
Wi'
Data Out
679
HYB41257
Nibble-mode write cycle (early write)
RAS
VIHVIL-
ill
YIHVIl-
Address.
VIHYIL-
WE
I
VIL-
Data In
VIHVIL-
Data Out
~~~=-----------H'9h Z - - - - - - - - - - - - -
Nibble-mode read-modify-write
Address
Data In
Data Out
680
HYB41257
Address Decoder Scrambling (without redundancy)
The evaluation and incoming testing of RAMs
normally requires a description of the internal
address scrambling of the device in order to check
for 'worst case' pattern.
Internal address scrambling
(PinS)
AO
(PIn6)
A2
(Pm7)
A1
(Pin81
VCC
(Pm9)
A7
RO
RO
CSll
CO
Data Stored=OI
RAS
A7R=O
ASR=O
512 Sense Refresh Amps
Oata Stored:: 51
Data Stored=Dl
(Pin10) AS
A7R=1
ABR=O
Data Stored=m
(Pm121 A3
RS11
(Pin31
OJ
(Pm2)
A8
(Pm1)
VSS
(Pm16)
CAS
(PIn1S)
A7R=O
AeR=l
512 Sense Refresh Amps
{Pm11l A4
(Pm4)
WE
A7R=1
ABR::1
00
(Pln14)
A6
{Pm13}
RS11
CO
(511
Address decoder scrambling
AO
A1
External
Row
Address
A2
Al
~
I
A4
R2
Rl
R5
R6
A7
R7
AS
RB
A6
Internal
Row
Address
R4
A6
A7
Address
RO= lAO ·A21" lAO ·A21
R1= (Al·Ai)~ (A1·A21
R,
A5
A8
External
Column
RO
cO==
CO
[0 :(A7'A"61+(A'1'A81
C,
C2
AS
C3
A4
C4
Al
CS
A2
C6
A1
AO
C1
C8
Internal
[olumn
Address
tim: The logiC symbols are used solely
to Indicate the logic function.
681
HYB41257
Redundancy
Redundancy concept
Individual bit map recognition
The HYB 41257 takes advantage of the redundancy
If the test for signature has shown a repaired device,
additional tests can be performed to recognize
which addresses have been repaired and how
they are replaced by spare lines. Rowand column
redundancy can be recognized independently.
concept for increasing yield. This is done by
providing the chip with a total of 8 spare rows and
4 spare column pairs. Two spare rows can be
selected independently in each of four 64K cell
arrays, and two spare column pairs can be selected
independently in each of two 128K cell blocks. The
spare lines can be selected by spare decoders which
have to be programmed by laser technique during
wafer probe.
Laser technology
For activation of redundant circuitry a laser pulse is
used to open polycide links within the spare row and
spare column decoders. The laser technique is used
because it is mature and has proven reliable in a
number of semiconductor applications including
the implementation of redundant memory circuitry.
Due to the fact, that the lase"r beam is very fine and
can easily and accurately be positioned, and that it
incorporates the energy for a controlled blow up
of the polycide links, the laser technique is well
suited for highly complex memory circuitry. All
that results in a more efficient use of chip real estate.
Redundancy testability (roll-call mode)
With the redundancy concept two categories of
devices, repaired and non-repaired ones, will be
available. These two categories have to be
separated easily and reliably by both, the manufacturer and the user (signature). When testing
repaired device, the reconfigurated address
scrambling which results from activating spare
rows and columns has to be taken into account for
efficient device testing (individual bit map
recognition).
The HYB 41257 has the capability of performing
these two novel functions. It is done with a sjmple
electrical test at the beginning of the final test or
incoming inspection of each device (roll-call
mode). The roll-call mode for performing both
signature and individual bit map recognition can be
activated with DI at VIHR (10V ± 10%).
Signature
With DI at VIHR and performing at least one RASonly cycle with a cycle time of tRCR on any address
combination, in the case of non-repaired devices
the Data Output is in the high-impedance state as in
normal early write cycles. For repaired devices the
Data Output will go to VOLR or VOHR after the
access time tRACR.
682
Row redundancy
Row redundancy can be recognized with DI at VIHR
and CAS at high, and RAS-only cycles on all 512
row address combinations. The data output is low
(VOLR) for non-repaired addresses, and is high
(VOHR) for repaired addresses only. Within each
64K cell array, spare row 1 is always used if only one
row is to be replaced. If two rows are to be replaced
in an 64K cell array, spare row 2 is used to replace
the defective row with the higher address.
Column redundancy
Column redundancy can be recognized with DI at
VIHR, and early write cycles with tRCDR :s tRCD (min)
on al1512 column address combinations.
A8 row must be used to distinguish between the
two 128K cell blocks. The data output is low (VOLR)
for non-repaired addresses, and high (VOHR) for
repaired addresses. Within each 128K cell block,
spare column pair 1 is always used if only one
column is to be replaced. Otherwise, spare column
pair 2 is used to replace the defective column with
the higher address.
HYB 41257
Recommended operating conditions
Roll-call mode
OC operating conditions and characteristics (Full operating voltage and temperature range unless
otherwise specified).
Limit values
Symbol
Parameter
VCC
VSS
Supply voltage HYB 41257-12, -15, -20 1)
1)
Min.
Typ.
Max.
4.75
0
5.0
0
5.25
0
Unit
VIH
Logic 1 voltage: All inputs (except 01)
2.4
-
VCC+l
VIHR
Logic 1 voltage: 01 1) 2)
9.0
10
11
VIL
Logic 0 voltage: All inputs 1)
-1.0
VOHR
Output logic 1 voltage lout
= -5mA
VOLR
Output logic 0 voltage lout
= -4.2 mA
1)
-
2.0
1)
V
0.8
-
-
0.4
A.C. operating conditions and characteristics
(Full operating voltage and temperature range unless otherwise specified.)
Symbol
Limit values
Parameter
Unit
HYB41257-15
-12
Min.
Max.
Min.
Max
Min.
Max.
tRCR
Roll-call cycle time
330
-
390
-
490
-
tRCOR
Roll-call RAS to CAS delay
-
30
-
30
-
35
tRACR
Roll-call RAS access time
180
tCARC
Roll-call CAS access time
90
-
225
r--- 115
I
-20
ns
300
-150
1) All voltages referenced to VSS.
2) VIHR at 01 must only be used for the roll-call mode test and not for normal memory tests or applications.
To avoid device damage, VIHR is to be applied after the initialization conditions (initial pause of 200 fls
and 8 cycles) have been satisfied, and must never exceed 11V.
683
HYB41257
Column Redundancy
Early CAS - early write cycle
(01 at VIHR, IRCO
= tRCO (min). row addresses AD to A7 = don't care)
m
VIHVIL-
CAS
VIHVIL-
Address
VIHVIL-
WE
VIHVIL-
VOHR-
Data Out VOLR-
Row Redundancy and Signature
RAS-only cycle
(01 at VIHR, WE = don't care)
VIHVIL-
m
Address
Data Out
684
~~~= - - - - H i g h z----lG~~}-----
HYB 41257
Siemens 256K DRAM Chip Topology
VSS
r-
Column Detoder
64K Memory Array
AO
A'
A2
Al
A4
AI
A6
A7
-
---
VCC
~
RAS
RAS
"od
CAS
Clocks
-EAS
AI:! Buffer
- A8
512+4 Sense Amplifier
.ll
:Ii
i
1Spa.re ROW<
l%
Nibble
~
Column Oeccder
Decoder
~ ~
2 Spare (Cliumn Pairs
f$
Shift
Register
~
Read/Write
(locks
~
"od
S12~4
Sense Amplifier
64K Memory Array
L-
Column Decoder
01100
Buffer
Dr
-WE
DO
I
685
I
Telecom Components
PEB 2030
Frame Aligner Module
Preliminary data
Features
•
Detection of frame alignment signals for PCM 30 highways in accordance with CCITT
recommendation G 732
Delay compensation and clock alignment between transmission line and exchange
Compensation of phase jitter up to 60l-'s
Detection and initiation of route alarms (AIS, service word)
Indication of loss of frame alignment
Slip detection
Error simulation for test purposes
Digital interface TTL-compatible
•
•
•
•
•
•
•
Applications
The PEB 2030 frame aligner module is used for interfacing PCM 30 routes with PCM switching
networks. Its main applications are as follows:
in multiplex units for PCM transmission routes
in concentrators and subscriber multiplexers at one end of PCM routes
as an interface between PCM routes and public and private PCM switches (DIU)
for delay compensation between switching stages (e.g., Swiss Post Office IFS design
concept)
Data interfaces
Pin configuration, top view
•
•
•
•
Voo FP
IN
B8
By
B6
B5
B4
B3
B2
B,
P
24
22
21
20
19
18
17
16
15
14
13
23
~::::::::ll
2
DB,
DB2
6
SP
R/W
PE
7
8
RCL SCL BI
9
10
11
12
SCT
cr
so
Vss
SP
R IW
PE
RCL
SCL
BI
SCT
CE
SO
FP
IN
Synchronous pulse
Direction of data transfer
Alarm port enable
Route clock
Station clock
Buffer inactive
Station counter trigger pulse
Chip enable
Serial output
Fault pulse
PCM input
.
Parallel outputs
P
V
VSS
Parity bit
Ground (0 V)
Supply voltage ( + 5 V)
B1}
~8
DD
AG 12/81
689
Frame Aligner Module
PEB 2030
General description
The Siemens frame aligner module PEB 2030 is a monolithic NMOS circuit. Its main application
is the detection of frame alignment signals of PCM 30 routes according to CCITI recommendation G 732 and the clock adjustment with delay compensation between PCM routes and PCM
switches.
An incorporated buffer enables the PEB 2030 to compensate phase jitter up to 60l's.
Route alarms can be challenged by a bidirectional data interface.
Block diagram
PCM
in out
SP FP
CE
..•.... 32
RCL
8
FM
B1. .. B9
4
P
5
RIW
PE
SO
•
/2
DB1 DB2
FA
AP
B
COC
FM
BI
SCT
SCL
Frame alignment
Alarm port
Buffer
Coincidence circuit
Frame memory
Description of function
The PEB 2030 module is fabricated using the n-channel depletion technique.
The module, connected to a PCM 30 line, and the associated input clock (route clock RCI), are
synchronized with the PCM frame in accordance with CCITI recommendation G 732. In the stable
condition the module supplies 488 ns synchronous pulses (SP) at a bit rate of 4 kbitls which
identify the beginning of the PCM frames containing the bunched frame alignment signal (FAS).
During the synchronizing phase and in the event of frame alignment being lost, the synchronizing pulses are suppressed and a 21's fault pulse FP is delivered every 2501's. When a synchronized
stage exists, such a fault pulse appears only if an FAS is not recognized.
On the output side the PCM information can be read out in serial and in parallel form. For this
purpose, a reading clock (SCI) and a 488 ns reading synchronizing pulse (SCT) must be applied
at 2501'S intervals to fix the beginning of the frame. The module supplies a parity check bi~ven
parity) to each PCM word via a tri-state output which is activated by a chip enable (CE) in
the same way as the tri-state outputs for the parallel information.
690
Frame Aligner Module
PEB 2030
An alarm flip-flop (FA Alarm) in the module is set in the event of frame alignment loss, route
timing loss or loss of the CE or SCT signals. The alarm bit is recorded in another flip-flop in the
service word (bit 3), whereas a third flip-flop stage is set when logic" 1" signals are received
by the PCM route for the duration of two frames (Alarm Indication Signal AIS). A further flip-flop
is set when a slip of the frame occurs. The alarms are polled via a bidirectional data interface.
The alarm circuits can be triggered and reset for test purposes via the data interface.
Pin description
Symbol
Function
Description
1. Supply
VDD
+5V±5%
Power consumption 300 mW
Vss
OV
2. PCM interfaces
IN
PCM input
RCL
2.048 MHz ± 50 ppm
256 kbitls
B1 . . . B8
SO
256 kbitls
2.048 Mbit
SCL
2.048 MHz
P
Information bit from one negative RC
edge to the next.
Route clock
Parallel PCM output information.
B1 =most significant in!. bit
Parity bit (even parity)
Serial PCM output. Bit sequence with
decreasing significance.
Station clock. Information bits from one
neg. SCI edge to the next.
3. Control signals
SCT
SP
BI
FP
CE
4 kbit/s
width 488 ns
4 kbitls,
width 488 ns
Continuous signal
Width:
4 x 488 ns
= 1.95J-(s
256 kbit, width
488 ns or continuous
level
From one neg. SCI edge to the next.
Frame begins from pos.SCT edge ..
From one neg. RCI edge to the next.
Frame begins with FAS from pas. SP edge.
B 1 = 1 or not connected:
Buffer inactive.
Fault pulse delivered for every undetected
FAS or every 250J-(s in the event of frame
alignment loss.
Chip enable controls ..9!!tputs B1 to B8 , P
low-impedance. The CE must be active
during the SCT, so that the SCT supervision by station counter is not impaired.
691
Frame Aligner Module
PEB2030
4. Data interface
Write
DB input timing (Write)
------1
CB
r---------- -
-------
RfW
tw > 1 /hS
tWE > 100 ns
tOE > 100 ns
I
tEW
r
I
-
1- twE
tOE
f'·~
tED
~E';;tED -
Read
RfW
DB output timing (Read)
:::::::]
tEWA > 100 ns
tEM < 1.2
tEAR > 160 ns
tWE > 100 ns
0.8 <
I
--------f-
--------
DB
-
tEEAL
-1'
twE
-
tEAP~---
_I.-
L-
tEWR
Data transfer direction
RI
= 1 read alarm port
R I W = 0 write alarm port
Alarm port enable
bidirectional data interface for command
acceptance or alarm signalling:
'!l
DB,
o
o
AIS alarm
Slip alarm
692
> 50 ns
> 150 ns
o Command:
poll FA alarm,
AIS alarm
1 Command: poll B3 of the service word,
Slip alarm
o Command: reset alarm flip-flop
1 Command: failure simulation
FA alarm
B3 alarm
Alarms are signaled as log. '1'
/hS
CL = 300pF
PES 2030
Frame Aligner Module
Pulse diagram
::j
Is· 14
r-
~.
.1.
SP
IDe
L
sf>
Channel 0
Channel 1 -
Delivery of synchronous pulse SP in synchronized state
";:~
I
I •
Channel
a
+-
IDCFP
Channel 1 - - -
Delivery of fault pulse FP in the event of erroneous frame alignment signal
Pulse diagram
SCl
so
---of--------- Channel 0 - - - - - - - - - -•.;!..,--Channel 1 CE
88
I
P -rCh~~nell-o._----Hi9h
I
IraImpedance--------j_
I"High Impedance-
--l Channel 0 I-693
Frame Aligner Module
PEB 2030
Output signals (B1 to Ba,P) as functions of the station trigger pulse SCT and chip enable CE
RSMSRSMSRSMSRSMSRSMSRSMSRSMSRSMSRSMSRSMSRSM
IN
I
FP
SP
AISout
Erroneous FAS:(~
Correct FAS
RCL
RCL
PS, SO
PA, SO
SCL
SCL
·1.4<§<5.2
~
~s
Loss of frame alignment due to bit falsification on the PCM route
R
M
S
R
M
694
Frame alignment signal (FAS)
Service word
Simulated FAS (Random FAS)
Erroneous FAS
Erroneous service word
Frame Aligner Module
PES 2030
Absolute maximum ratings 1)
Min
Operating temperature
Storage temperature
Total power consumption
Input voltage
Supply voltage
Electrical characteristics (T,mb
T'mb
T"g
0
-55
VI
VDD
-0.3
-0.3
Ptol
=
250C)
Min
VDD
's
Supply voltage
Supply current
Input current
H input voltage
L input voltage
L output voltage
H output voltage
H output current (FP,SQ,SP,Bi'P)
L output current (FP,SQ,SP,Bi'P)
H output current (OBi)
L output current (OBi)
'IL
V,H
VIL
VOL
VOH
IOH
IQL
IOH
4.75
Max
70
125
400
7
7
Typ.
5
50
50
2.4
°C
°C
mW
V
V
Max
5.25
70
150
Unit
-0.02
0.46
-0.04
0.9
V
mA
J-lA
V
V
V
V
mA
rnA
mA
rnA
20
20
2.1
ns
ns
MHz
0.7
0.4
2.7
1m
Unit
Timing specification
Input H-L transfer time
Input L-H transfer time
Clock frequency
(pulse-pause ratio 1: 1)
IHL
tLH
tWH:tWL
Set up time
Hold time
Switching times
0.2
ts
1
150
40
tH
(VDD
from
(input)
to
(output)
CE
SCL
RCL
SCL
B1 · .. Ba,P
DB 1 ,DB 2
FP,SP
SQ
1)
feL
2.048
ns
ns
= 5V, T.mb = 25°C)
Test conditions
tDO
tDa
tDa
tDa
50
50
15
15
pF,
pF,
pF,
pF,
10 kD
5 kD
10 kD
10 kD
Min
Typ.
Max
Unit
200
350
200
200
ns
ns
ns
ns
Stresses above those listed under 'Absolute maximum ratings' may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicatd in the operational section of this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
The information describes the type of component
and shall not be considered as assured characteristics.
695
I
PEB 2040
Memory Time Switch
Preliminary data
Features
•
•
•
•
•
•
•
•
•
•
MOS circuit
Time/space switch for 2.048 MHz and 8.192 MHz PCM systems
Different kinds of operation modes (2 Mbit/s. 8 Mbit/s or mixed mode)
16 input PCM lines and speech memory for all 512 subscriber on chip
Connection memory for 256 channels of 8 output lines on chip
Non blocking time switch with 16/16 PCM lines can be built with two devices
fiP-interface for writing and reading the connection memory
Delay between input and output lines selectable
Tristate for further expansion or hot standby
Advanced NMOS technology
Single + 5 V power supply
Applications
•
•
•
•
•
All types of switching systems
Complete switch in PCM PABX for up to 512 subscriber with only two devices
Concentrator function
Frequency-transforming interface between 2 MHz and 8 MHz PCM systems
16/16 space switch for 8 MHz PCM systems
AG 7184
697
Memory Time Switch
PEe 2040
Pin configuration
40 elK
vss
SP
39 aUTO
IN 1
38 OUT1
IN 0
4
37 OUT2
IN 5
5
36
IN 4
6
3S OUT4
IN 9
7
34 OUTS
IN 8
8
33 OUT6
IN 13
9
IN 12
10
oun
32 OUT7
PE B 2040
31
DB7
IN 14
11
30
DB6
IN 15
12
29
DBS
IN 10
13
28 DB4
IN 11
14
27 DB3
IN 6
15
26 DB2
IN 7
16
25 DBl
IN 2
17
24 DBD
IN 3
18
23 WR
AO
19
22
RiS
Cs
20
21
Vee
General description
The SIEMENS memory time switch PES 2040 is a monolithic NMOS circuit with speech
and connection memory on chip. It connects any of 512 incoming PCM channels to any of
256 outgoing PCM channels. Two chips give a non blocking 512 channel switch.
Block diagrams of 2 PCM systems using the PEB 2040 are shown in figure 1. In- and
outputs are TTL compatible.
698
Memory Time Switch
PES 2040
Figure 1
Siock diagram of two PCM switch configurations with PES 2040
PEB
2040
PCM 2MHz
PCM 2MHz
16
OUT
IN
PEB
2040
Memory time switch 16/16 for a non blocking 512 channel switch.
PEB
16
2040
12
PEB 1-_~-,,;8,<--
2040
22
PCM 2MHz
PCM 2MHz
IN
OUT
16
8
PEB
PEB
2040
24
2040
14
e
Memory time switch 32/32 for a non blocking 1022 channel switch using the tristate
function.
699
Memory Time Switch
PES 2040
Functional description of MTS 16/8
The PEB 2040 is a memory time switch module which has the ability to connect any
of the 512 PCM channels of 16 incoming PCM lines to any of the 256PCM channels
of 8 output lines.
A block diagram of the main components is shown in figure 2.
The PCM information of a complete frame is stored in the 4K speech memory SM. That
means all of the 512 words with 8 bits are written into a fixed position of the SM. This
is controlled by the input counter every 125 Ils. The words are read with a random access
with an address that is stored in a connection memory CM for each of the 256 output
channels. The access to the CM is controlled by the output counter.
To realize a connection the 8M address and the eM address must be written into the PEB 2040 via
apP interface. The8M address contains the channel and line numberof the incoming peM words.
The eM address consists of the channel and line number of the output words.
700
Memory Time Switch
PEe 2040
Figure 2
Block diagram
/----10
Speech
Memory
SM
PCM Inputs
15
Connection
Memory
CM
8 bit
Control
logic
Output
counter
Input
counter
elK
SP
Comparator
110 register
Data Bus DBO -DB7
~P
interface
701
Memory Time Switch
PEB 2040
Operation modes
The PES 2040 can be connected to 2.048 Mbit/s and 8.192 Mbit/s PCM lines. The
operation mode is selected by the mode bits, where MI~ and MIl defines the bit rate
of the input lines and independently MO~ and Mal that of the output Jines.
The corresponding input and output addresses are given in table 1. The mode
MI~ = MIl = 1 is only for space switch application.
Table 1
Input configuration
PIN Nr.
3
4
5
6
7
8
9
1~
11
12
13
14
15
16
17
18
MI~=~, MIl
16x2 Mbit/s
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
~
5
4
9
8
13
12
14
15
=9>
MI~= 1. MIl =~
MI~=~, Mil = 1
MI~=
4x8 Mbit/s
8x2+2x8 Mbit/s
16x8 Mbit/s
IN
IN
IN
IN
1
~
2
3
1~
IN
~
IN
4
IN
8
IN
1
IN
3
IN 12
IN 14
1~
IN 1~
11
6
7
2
3
IN
6
IN
2
11
6
7
2
3
Output configuration
PIN Nr.
32
33
34
35
36
37
38
39
702
MO~ =~, MO 1 =~ MO~= 1, MO 1 =~
MO~=~,
8x2 Mbit/s
4x2/1 x8 Mbit/s
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
7
6
5
4
3
2
1
~
2x8 Mbit/s
Mal =1
OUT 7
OUT 5
OUT 3
OUT 1
OUT ~
OUT 1
1
~
5
4
9
8
13
12
14
15
OUT ~
1, MIl =1
Memory Time Switch
PES 2040
Pin description
Pin-No.
1
2
3
4
5
Name
Function
Vss
Ground (OV)
Synchronous pulse (8 kHz); rising edge for input counter
falling edge for output counter; difference between rising
and falling edge should be j = (2 + Nx4) telK
(N = f/J - 255)
rising edge synchronous with the incoming frames; output frame starts 2 clock pulses before the falling edge.
PCM input port 1
PCM input port '/J
PCM input port 5
PCM input port 4
PCM input port 9
PCM input port 8
PCM input port 13
PCM input port 1 2
PCM input port 14
PCM input port 1 5
PCM input port 1!1'l
PCM input port 11
PCM input port 6
PCM input port 7
PCM input port 2
PCM input port 3
Address '/J. for separating different modes of the control
words
Chip select
Supply voltage + 5 V ± 5%
Read pulse
W.rite pulse
DATA Bus '/J
DATA Bus 1
DATA Bus 2
DATA Bus 3
bidirectional
DATA Bus4
DATA Bus 5
DATA Bus 6
DATA Bus 7
PCM output port 7
PCM output port 6
PCM output port 5
PCM output port 4
PCM output port 3
PCM output port 2
PCM output port 1
PCM output port !1'l
Clock pulse 8.192 MHz. duty cycle 50%
SP
18
19
IN 1
IN '/J
IN 5
IN 4
IN 9
IN 8
IN 13
IN 12
IN 14
IN 15
IN 1~
In 11
IN 6
IN 7
IN 2
IN 3
A'/J •
2'/J
cs·
6
7
8
9
1~
11
12
13
14
15
16
17
21
22
23
24
25
26
27
28
29
3'/J
31
32
33
34
35
36
37
38
39
4'/J
•
~P·controlled
Voo
RU"'
WR'
DB '/J'
DB 1"
DB 2'
DB 3'
DB 4'
DB 5'
DB 6"
DB 7'
OUT 7
OUT 6
OUT 5
OUT 4
OUT 3
OUT 2
OUT 1
OUT!1'l
ClK
interface
703
Memory Time Switch
PEB 2040
PCM-interface
Control signals:
Clock: ClK felK = 8.192 MHz 50% duty cycle. t r• t f ;::;; 10 ns
synchronous pulse: SP felK = 8.000 kHz defines the PCM
frame with 1024 clock pulses
t r• t f :£ 10 ns
PCM input: IN '/J - IN 15
for 2 or 8. Mbit/s organized as 32 words of 8 bits or 128 words of 8 bit within a frame.
The frame for all input lines starts with the rising edge of the SP signal.
PCM output: OUT '/J - OUT 7
for 2 or 8 Mbit/s. The frame for all output lines is controlled by the falling edge of the SP
signal. The difference between the rising and the falling edge of the SP signal should be
J = (2 + N x4) t elK • '/J::; N::; 255 (fixed at space switch application:
J = (2 + 70 x 4) telK = 282 t elK • N = 70). N defi nes the delay of the output frame cou nted in
2 MHz bit steps relative to the input frame. as shown in the timing diagram.
The outputs have tristate capability.
704
PEB 2040
Memory Time Switch
MTS 16/8
Timing diagram
4
OUT 2Mbit/s
Channel 0, Bit 0
Example with delayed output frame
\\..,.___---J!
SP N= 255
OUT2~________~C~ha~n~ne~IO~,~BI~tO~______~X~
OUT 8~ ChO, BO
______~Ch~a~nn~e~IO~,~B~it~1
________~X:::
XCh 0, 81 XCh 0, B2 XCh 0, B3 XCh 0, 84 XCh 0, BS XCh 0, B6 XCh 0, B7
x:::
Space switch application
I 1 I 2
CLK~
o
SP
OUT
23
24
280
281
---f N =70 fixed
-------------------------------,J----.,----.I'_______________________
8.!1bi!!~
Clock timing
felK = 8,192 MHz
telK = 122 ns
50% duty cycle
..;C~h12;;;.;.:7,.;;B;.;,7...J~;.;.:.;;;.;....,\",;;,;.;.;.:,.;;;.;..J'-
Timing with felK = 8,192 MHz
min
max
t55
t52
tH 2
ts 8
tH 8
to
70
180
0
60
0
170
50
ns
ns
ns
ns
ns
ns
start of output frame
Cl = 200 pF
705
Memory Time Switch
f.lp Interface OB~ - OB7, Ff[),
PEB 2040
WFt CS,
A~
Commands for access to the connection memory, selected by A~
= 1.
All commands have a three byte strukture and must tie executed completly.
OB~
OB7
x
X
K1
K~
X
X
X
58
Key word
57
56
55
54
53
52
51
5~
5peech Memory Address
C7
C6
C5
C4
C3
C2
C1
C~
Connection Memory Address
Keyword
K1
K~
1
~
~
~
Write Connection Memory
Write Connection Memory, with checkbytes
Read Connection Memory
1
~
~
I
57
I
56
I
55
I
54
I
52
53
51
5~
5peech memory address, stored in the connection memory
I
C7
I
C6
I
C5
I
c4
I
C3.
I
C2
I
C1
I C~ I
Connection memory address
The speech memory address contains the channel and line number of the incoming PCM
words. The connection memory address consists of the channel and line number of the
output words with the following coordination.
2 Mbit/s input lines
bit ~-3 line number
bit 4-8 channel number
8 Mbit/s input lines
bit ~-1 line number
bit 2-8 channel number
2 Mbit/s output lines
bit ~-2 line number
bit 3-7 channel number
8 Mbit/s output lines
bit ~
line number
bit 1 -7 channel number
706
Memory Time Switch
PEB 2040
Example
Channel 7 of the coming 2 Mbit/s line No.9 shall be switched to channel 126 of the output
line No.1 of an 8 Mbit/s system without checkbyte:
Byte
f/J
1
2
20 H
79H
FDH
(f!> f/J 1 f/J f/J f/J f/J f/J)
~
Key
Word write
(f/Jf/J1 f/Jf/Jf/Jf/Jf/J)
(f/Jll11f/Jf/J1)
(111111f/J1)
(f/J 1 1 1 1 f/J f/J 1)
(1 1 1 1 1 1 f/J 1)
'---.-" ~
"-.-'-.,...
Channel 7
Line 9
For space switch application with MI '/J
Channel 126
= 1, MI
1
Line 1
= 1; MO
'/J = 1, MO 1 = '/J
8 Mbit/s input lines
bit '/J - 3 line number
bit 4 - 8 the lower 5 bits of the channel number
8 Mbit/s output lines
bit '/J
line number
bit 1 - '] channel number
The difference between the rising and the falling edge of the SP is fixed:
N = 7'/J, j = (2 + 70 x4) tCLK = 282 tCLK
The selection of 128 input channels is possible by writing the connection memory (CM) as
shown below.
In
In
In
In
CM-address
CM-address
CM-address
CM-address
'/Jf/J-3F
4f/J - 7F
8'/J - BF
C'/J - FF
....
....
....
....
S8-S4
S8 - S4
S8 - S4
S8 - S4
(SM-adr.)
(SM-adr.)
(SM-adr.)
(SM-adr.)
means
means
means
means
ch. f/!-ch.31
ch. 32 - ch. 63
ch. 64 - ch. 95
ch. 96 - ch. 127
3 elCsmples:
CM-address = 3F
SM-address = 1 FA
CM-address = 7F
SM-address = 1 FA
CM-address = Cf/!
SM-address = f/!f/!8
C7
C'/J
!/>'/J 111111
11l1119)1!/>
S8
Sf/!
C7
C'/J
9ll1l1l11
1111119l1'/J.
Sf/!
S8
C7
Cf/!
11 ID'/JID9lf/!'/J
f/!'/J9l!/>9l19lf/Jf/J
58
SID
output line 1, ch. 31
input line 1f/!, ch. 31
output line 1, ch. 63
input line 19l, ch. 63
output line f/J, ch. 96
input line 8, ch. 96
707
Memory Time Switch
PES 2040
Write connection Memory
x
X
1
S7
S6
S5
l/J
S4
C7
C6
C5
C4
X
53
C3
X
X
S8
S2
S1
Sl/J
C2
C1
Cl/J
}
A~~'.~~~.CS~~
5tores 58 - 5l/J into the Connection Memory addressed with C7 Write Connection Memory with check bytes desired
X
X
X
X
X
S8
S6
l/J
55
1
S7
54
53
52
51
Sl/J
C7
C6
C5
C4
C3
C2
C1
Cl/J
}
A~~'.~~~.CS~~
5tores 58 - 5l/J into the Connection Memory addressed with C7 -
1
X
X
X
S8
56
l/J
55
54
53
52
51
5l/J
C6
C5
C4
C3
C2
C1
Cl/J
X
X
57
C7
}
Cl/J.
Cl/J.
A~-'.AIT~~.CS~~
58 - 5l/J have been overwritten by the Connection Memory in the next frame after writing
the Connection Memory.
Read Connection Memory
X
X
X
X
l/J
X
C7
C6
C5
l/J
X
X
X
C4
C3
X
X
X
X
X
X
C2
C1
Cl/J
}
A~~'.~~~.CS~¢
overwrites 58 - 5l/J with the Connection Memory address C7 with the following sequence.
X
X
l/J
54
X
X
58
56
l/J
55
X
57
S3
52
51
5l/J
C7
C6
C5
C4
C3
C2
C1
Cl/J
708
Cl/J,
and can be read
PEe 2040
Memory Time Switch
selected A~=~
Mode/Status
Status
A~=~, R1J=~,
(WR"=1),
CS"=~
DB~
DB7
B
B
z
= 1
x
'/) I
RY
Chip busy during command execution
Incomplete command instruction
Mode register blocked (after "Power-on")
= 1
RY = 1
Z
Power on tristate
SB is set by "Power-on" or by "Write Moderegister",
SB is reset by "Write Moderegister",
"Write Moderegister" is blocked at most seven frames
after "Power-on",
During that time RY in the status register is set to "1"
SP and CLK should be applied immediately after
"Power-on"
A~
Mode
=,/), WR =,/),
(RD
= , ), CS =9>
DB7
R
DB'/)
TE
SB
R
Reset
,
TE = Tristate enable
S8 = Standby
MI1
R = ~ Reset
TE = ~ Mode without tristate function
TE = 1 Tristate dependent from code
S8 = 1 Tristade independent from code
MIl
MI'/J
Input
operation mode
~
'/J
1
'/J
l6x2 Mbit/s
4xS Mbit/s
2x8+Sx2 Mbit/s
,
'/J
I MI~ I Mal I MO~ I
MOl
MO'/J
Output
operation mode
'/J
'/J
1
'/J
8x2 Mbit/s
2xS Mbit/s
1x8/4x2 Mbit/s
"
1
16x8 Mbit/s
for space switch application only
709
Memory Time Switch
PEe 2040
Reset
DB7 = R
The PEB 2040 can be initialized by a mode byte with R=~. This causes the complete
connection memory to be overwritten with zeros. During this time the busy bit is set.
Tristate
DB6 = TE. DB4 = SB
The PCM outputs of the PEB 2040 have tristate capability.
1. SB = 1 is a standby mode. All outputs are tristate. The connection memory works in
the normal mode.
The chip can be activated immediately by setting SB = ~.
2. TE = 1. (SB = ~): The output channels are tristate. if the speech memory address
stored in the connection memory is 58 - S~ = ~. This means that channel f/J of
line ~ is not available for any output.
3. TE = ~, (SB = 9)): Channel 9) of line 9) is available, but tristate is not possible.
Operation Mode (Input/Output bit rate)
DB9)=M09). DB1 =M01. DB2=MI9). DB3=MI1
The operation mode is selected by the mode bits. where MI9) and MI1 defines the bit
rate of the input lines and independently M09) and M01 that of the output lines.
The corresponding input and output addresses are given in table 1.
Example
DB7
PCM mode: 16x2 Mbit/s input
PCM mode: 8x2 Mbit/s output
with tristate
710
DB9)
Memory Time Switch
PES 2040
Timing of IlP interface
Read operation
tRcy
tRR
tAO
DBO-DB7
3
Datu valid
Min.
Adr. stable before RlJ
Adr. hold after RlJ
RD width
RD to data valid
Adr. stable to data valid
Data float after RlJ
RD-cycle time
tAR
tRA
tRR
0
0
180
t RO
tAO
tOF
t Rcy
Max.
10
500
90
100
100
Unit
ns
ns
ns
ns
ns
ns
ns
Write operation
tW[Y
tww
WR
,DBO-DB?
tow
~~atavalid
Min.
Adr. stable before WR"
Adr. hold time
WR width
Data set up time
Data hold time
WR cycle time
tAW
tWA
tww
tow
two
twev
0
0
190
130
0
500
Max.
Unit
ns
ns
ns
ns
ns
ns
711
Memory Time Switch
PES 2040
The "busy time" during which a command or reset instruction is executed has to be
programmed with its maximum length or must be controlled via the busy bit of the status
register.
Busy time
Average
Max.
Unit
Reset
Read connection memory
Write connection memory
Write connection memory with check bytes desired
188
63
63
188
250
125
125
250
fls
fls
fls
fls
Typ
Max.
Unit
7
7
V
V
1
10
W
mW
Min.
Maximum ratings
Supply voltage
Input voltage
Total power dissipation
Output power dissipation
Operating temperature
Storage temperature
Vee
VI
Ptot
Po
Tamb
Tst g
DC and operating characteristics
Tamb = -0 to 70°C, Vee = 5 V ± 5%
Supply current
I DO
Input leakage current VI = 0 to Voe
IlL
H input voltage
VIH
L input voltage
VIL
H output voltage (10 = -0.2 rnA)
VOH
L output voltage (10 = 2.0 mAl
VOL
Tristate output leakage Vo = 0 to Voe IOL
AC testing input. output waveform
2.4
. }.o
/Test pom~
2.0"
0.8
0.8
-0,3
-0,3
-0
70
OC
-55
125
°C
150
10
Vee
0.8
I rnA
flA
60
10
2.0
0
2.4
-
-
V
V
V
V
0.4
10
10
flA
AC testing load circuit
Device
under
test
0.4
AC testing:
Inputs are driven at 2.4 V for a logic "1" and 0.4 V for a logic "~".
Timing measurements are made at 2.0 V for a logic ", .. and 0.8 V for a logic
712
"r!J".
PEB 2050
Peripheral Board Controller (PBe)
Preliminary data
MOS circuit
Features
•
Board controller for up to 16 subsribers of a digital switching system
•
Designed for different PCM systems
• Time slot assignment freely programmable for all connected subscribers
•
Control of voice, data, signaling and line board parar.1sters to minimize hardware
requirements and to simplify software
•
Provides two full duplex PCM highways for the system interface
•
System control uses the HDLC protocol with X.25 level 2 functions performed by
the PBC
•
•
Standard iJP interface
Two DMA channels for expansion of internal buffer capability of 16 bytes per direction
•
iJP access to all internal data streams including time slot-oriented data streams
•
Support of subscriber circuits by generating timing signals
•
Single 5 V power supply
•
Low power consumption
I
AG 5/83
713
PES 2050
General description
The Peripheral Board Controller PEB 2050 is a device for the control of voice, data, and
signaling paths of up to 16 subscriber~ on peripheral component boards in digital telephone systems. In combination with the highly flexible Siemens Codec Filter (SICOFI PEB
2060) it forms an optimized analog subscriber line board architecture. Its flexibility allows
the operation as a general purpose controller for data switching and MUX/De MU?< applications.
The PBC controls space and time switching functions between subscriber line devices and
time division multiplex highways. Further, it controls the flow of.information between the
subscriber interface ports and a processor, which can be an optional line card local" processor or the central processor directly. Last, it performs all protocol control functions,
using the HDLC protocol format for all information passing between the line card and the
central processor via a dedicated HDLC line or via interleaved time slots on the PCM lines.
To meet the different requirements the PBC PEB 2050 provides the following interfaces:
•
8 serial, bidirectional I/O ports for the transfer of voice, data, control, and signaling
information between the PBC and Codec Filters (e.g.SICOFI PEB 2060), digital
interface circuits or signal processors.
•
Double constructed PCM interface.
•
Fast serial communication link to the central processor.
•
Bit-parallel interface for the connection of 8 bit standard microcomputers such as the
SAB 8048. The interface is characterized by an interrupt control and two independent
DMA channels, one for the transmit and one for the receive direction.
714
PES 2050
Pin configuration
top view
SIP4
40
SIP 3
SIPS
39
SIP 2
SIP6
38
SIP 1
37
SIP 0
SIP7
4
RxHW01
RxHWOO
6
36
RESET
35
INTITYP
TxHW01
34 OA(K 1
TS(1
33 OA(K 0
32
TxHWOO
WR
31
Voo
11
30
07
06
TS(O
10
SYP
5(LK
PEB 2050
12
29
5IG5/0MIR 13
28
05
DIR/OMOR
14
27
04
Tx50
15
26
03
T5(2
16
25
02
Rx50 17
24
01
fS
23
DO
18
ALE 19
22 RO
Vss 20
21
I
(LK
715
PEB 2050
Pin designation
Pin No.
Symbol
Name/function
Functional description
SIP 4
Subscriber
interface port
(input/output)
These interface ports are used for bidirectional, bit-serial transfer of speech, data and
control words to and from the Siemens
Codec Filter (SICOFI) or standard Codec.
Corresponding with the direction signal the
PBC PEB 2050 is transmitting during the
high level of DIR within the first half of a
1 25 fJs frame.
4
SIP 7
5
RxHWD1
Receive highway
data (input)
Receive PCM highway 1 interface
6
R x HWD 0
Receive highway
data (input)
Receive PCM highway 0 interface.
The PBC serially receives a PCM word
(8 bits) through one of these leads at the
programmed time slot.
7
TxHWD1
Transmit highway
data (output)
Output of the transmit side onto the send
PCM highway 1 (serial bus). The 8-bit PCM
word is serially sent out on this pin at the
programmed time slot.
Tristate output.
8
TSC 1
Tristate control
(output, active low)
Normally high, this signal goes low while
the PBC is transmitting an 8-bit PCM word
on the PCM highway 1.
9
T x HWD 0
Transmit highway
data (output)
Output of the transmit side onto the send
PCM highway O.
10
TSC 0
Tristate control
(output, active low)
Tristate control of highway O.
11
SYP
Synchronization
SYP is a frame synchronization pulse which
resets the on-chip time-slot counters.
12
SCLK
Slave clock
(output)
Clock output for the peripheral devices. The
signals between the codec filter and the PBC
are latched and transmitted with the rising
edge of SCLK.
13
SIGS/DMIR
Signal strobe
(output, active
high)/direct
memory input
request (output,
active high)
The SIGS output supplies a programmable
strobe signal. In the DMA mode, this pin is
used as DMA input request.
716
PEB 2050
Pin designation
Pin No.
Symbol
Name/function
Functional description
14
DIR/DMOR
Direction
(output, active
high) direct
memory output
request (output,
active high)
DIR is an 8 kHz symmetric frame signal
which controls the direction of the data
transfer from and to the peripheral devices.
The PBC is able to receive data during the
low state of piR.
In the DMA mode this pin is used as DMA
output request.
DMIR and DMOR are generated by the PBCinternal HDlC receiver or transmitter and
are used for handshaking during the OMA
transfer.
15
T x SD
Transmit signaling
Data (output)
This line transmits the serial data to the
dedicated HOlC channel.
Tristate control to 2
(output, active low)
Normally high, this signal goes low while
the PSC is transmitting an HOlC message.
Receive signaling
Data (input)
This line receives the serial data from the
HOlC channel.
Chip select
(input, active low)
CS is used to address the PSC. A low level
at this input enables the PSC to accept
commands or data from a fJP within a write
cycle, or to transmit data during a 'read
cycle.
Address latch
enable (input,
active high)
A high level at this input indicates that the
data on the external bus is an address
selecting one of the PSC-internal sources or
desti nations. latching into the address latch
occurs during the high low transition.
16
17
R x SD
18
19
ALE
20
21
Ground: 0 V
ClK
Clock
(input)
A standard TTL clock provides the basic
timing of the controller. The clock is
synchronous to the PCM clock.
717
I
PEB 2050
Pin designation
Pin No.
Symbol
Name/function
Functional description
22
RD
Read strobe
(input. active low)
RD is used together with CS to transfer data
from the PBC to a iJP or memory.
23
DO
System data bus
The data bus transfers data and commands
between theiJP or memory and the PBC.
30
D7
31
VDD
32
WR
Write strobe
(input. active low)
During the low state of WR data can be trans·
ferred from the I'P or memory to the PBC.
33
DACK 0
34
DACK 1
DMA acknowledge (inputs,
active low)
DACK 0 and DACK 1 are used to acknowledge the DMA output and DMA input
request, respectively.
35
INT/TYP
Interrupt
request (output,
active low)
This signal is pulled down, when the PBC
is requesting an interrupt. In that case the
iJP should enter into an interrupt routine
for reading the status register 1.
36
RESET
Reset (input,
active high)
A "high" on this input forces the PBC into
reset state. The minimum reset pulse is 16
complete clock cycles.
37
SIP 0
Power supply: V DD = 5.0
Subscriber
interface port
(input/output)
40
718
SIP 3
± 0.25 V
These interface ports are used for bidirectional, bit-serial transfer of speech, data and
control words to and from the Siemens Codec
Filter (SICOFI) or standard Codec. Corresp~nding with the direction signal the PBC
PEB 2050 is transmitting during the high level
of DIR within the first half of a 125 iJs frame.
PEB 2050
Block diagram
SIP 0
Subscriber
interfuce unit
PCM
interfuce unit
Timing
control unit
Bus interface
control unit
PCM
hlghwuys
SIP 7
OIR
SIGS
SClK
SYP
ClK
RESET
Speciul purpose
registers
Voo
GNO
TxSO
RxSO
TSC
{ ' ___ ---'L
~--
CS
ALE
Rii
WR
I
INT 00-07 OMIR O~IOR OACKO OACKl
719
PEB 2050
Block diagram
OIR
DMOR
SYP
CK SCK
t SIGS
I OMIR
t·
SIP 0 ...
SIU "
I
TeU
CAM 0
~
RPeR
XH(R
XP(R
CAM 1
AOR
RKR
XKR
SIP 7 __ -
<=-=--
INT
DA(K 1
DA(K 0
Ro
WR
PIU
ALE
~
~
\/(cGNO~
I
Reset ----
T5C 0
720
Os
OJ
PES 2050
Description of the functional blocks
The PSC has been designed especially for use in peripheral subscriber boards, but its functional flexibility also permits its application in various parts of a digital exchange telecommunication system.
Used in peripheral subscriber boards it performs two essential functions:
1) Exchange of control data between a central processing unit, an "on board" processing
unit and individual subscriber connections. The PSC supports the ISO/CCITT's HDLC
communication line protocol. An application specific PSC internal controller controls
the distribution of data on the board.
2) The time slot controlled transfer of PCM data (64 Kbaud channels) between the PCM
highways and the subscriber connections.
Data transfers between both parts, such as signaling through PCM highways (common
channel) or the access of the "on board" fJP to 64 Kbaud channels, are considerably simplified by the IC.
The two central functional blocks are reflected in the circuit structure: The PCM synchronous portion constitutes the interfaces to the subscribers and the PCM highways. It comprises the following functional blocks:
o
o
o
SIU (Serial Interface Unit) with Last Look logic.
PIU (PCM Interface Unit)
CAM (Content Addressable Memory)
€I TCU (Timing Control Unit)
o
MODE register
CD PSC Sus
The asynchronous portion constitutes the interface to the local microprocessor (8-bit
parallel) and to the central control (serial HDLC interface) and comprises the following
functional blocks:
o
o
o
o
HDLC controller
fJP interface
fJP control and status register
ULCU (User Level Control Unit)
The two portions are interconnected by the following functional blocks:
€I X FIFO (Transmit FIFO)
G> Bidirectional FIFO
o SICU (Sus Interface Control Unit)
e SIR (Sus Interface Register)
721
I
PES 2050
Min
IMax
IUnit
T stg
-65
125
°C
Ambient temperature
Tamb
0
70
°C
Voltage at any pin vs. ground
V
-0.3
7
V
Total powpr consumption
P tot
600
mW
Maximum ratings
Storage temperature
Range of operation
DC characteristics
Tamb = 0 to 70°C; Vee
=5V ±
0.25 V; GND
=0
V
Conditions
Min
Typ.
Max
Unit
L input voltage
V IL
-0.5
0.8
Volts
H input voltage
V IH
2.0
5.5
Volts
L output voltage
VOL
0.45
Volts
H output voltage
V OH
Input leakage current
IlL
= +1.6 mA
IOH = -400 IJA
V IN = Vee to 0 V
Output leakage current
IOL
VOUT
Vee - supply current
Icc
Vee = 5 V
722
IOL
=
Vee to 0 V
2.4
Volts
-10
10
IJA
-10
10
IJA
rnA
85
120
PEB 2050
Capacitance
Tamb = 25°C; Vee
= GND = 0
V
Conditions
CIN
Input capacitance
fe
I nput/output capacitance
CliO
Output capacitance
COUT
AC characteristics
Tamb = 0 to 70°C; Vee
=5V±
=
Min
1 MHz
unmeasured pins
returned to GND
0.25 V; GND
=0
Typ.
Max
Unit
5
10
pF
10
20
8
15
pF
. pF
V
Microprocessor interface
Read cycle
Min
Max
Unit
Address hold after ALE
tLA
20
ns
Address to ALE setup
tAL
30
ns
Data delay from RD
t Ro
150
ns
10 7
ns
25
ns
RD pulse width
tRR
Output float delay
tOF
RD control interval case 1 *
tRI
2x CP
ns
RD control interval case 2**
tRI
100
ns
ALE pulse width
tAA
60
ns
150
Min
Write cycle
Max
Unit
WR pulse width
tww
100
ns
Data setup to WR
tow
50
ns
Data hold after WR
two
25
ns
WR control interval case 1*
tWI
2 x.CP
ns
WR control interval case 2**
tWI
50
ns
• Case 1: Read, write of BI FIFO and X FIFO
•• Case 2: All other registers
723
PES 2050
DMA Read
Min
DMA read time"
Max
Unit
tOMA
7 x CP
ns
DMOR hold time
tOH
75
ns
Address stable before RD
tAR
ns
0
Data delay from RD
t RO
Output floating delay
tOF
20
Address hold after RD
tRA
0
tRR
150
10 4
ns
Min
Max
Unit
7 x CP
ns
80
ns
RD pulse width
ns
150
DMA Write
DMA Write time*
tOMA
DMIR hold time
Address stable before WR
tAW
Address hold after WR
tWA
Data setup to WR
Data hold after WR
WR pulse width
tww
tlH
ns
ns
0
0
ns
ns
tDW
30
ns
tWD
25
100
ns
ns
*)
PBC clock/MHz
2.048
4.096
1.536
3.072
2 x CP/ns
980
490
1300
650
7 x CP/\lS
3.4
1.7
4.56
2.3
724
PEB 2050
Read cycle
~--------------~r-\~-----------
ALE
DB
-
_____ ~' -----~-----------------------
------
ADR
-----
DATA
- - - - ------ -------------
Write cycle
DB
DMA read
DMOR
r----,.r-------------
DB
OMA write
1 - - - - - - - - - - - tOM' - - - -
DMIR
WR
DB
725
PEe 2050
Clock timing
Min
Max
Unit
4.2
MHz
System clock
System clock frequency
ClK
Duty cycle
45
55
%
Synchron pulse period
tspp
125
M x 125
Synchron pulse width
tSYp
60
tCKL
IJs
ns
Pulse delay to ClK
tdSYP
10
tsSYP
50
•
Setup time to ClK
Clock rise/fall time
ClK,!
ns
ns
10
ns
Slave clock
Clock frequency
SClK
512
512
kHz
Clock delay time
tdSCLK
100
165
ns
tdDIR
120
190
ns
Min
Max
Unit
DIR Clock
Delay time to ClK
SIU interface
SIP data delay
t dSIP
160
300
ns
Data enable receive
tDER
100
180
ns
Data disable receive
tDDR
100
180
Data enable transmit
tDEx
0
ns
ns
Data hold transmit
tDAX
0
ns
Data setup transmit·
t DSX
CP/2+200
ns
Signaling strobe delay
t DS1G
110
726
160
ns
PEe 2050
SIP interface timing
Detail B
Detail A
Syp
r -
--l
lfl
I
I
I
..-----,
I
I
I
MCLK
SCLK
01 Rext
SICOFI
SIP
tSYp
Detail B
Syp
MCLK
SCLK
DlRext
t,,,,
SICOFI
SIGS
,~,9:JT
Uf----tdS,G
727
I
PEB 2050
Serial port timing
PCM interface
Conditions
Min
Max
Unit
Receive timing
Receive data setup OCR
Receive data setup OCR
Receive data hold OCR
Receive data hold OCR
Receive
=1
= o'
=1
=0
tOSRF
20
ns
tos RR
40
ns
tou RF
40
ns
tOH RR
10
ns
Timing
RxHWO
OCR =1
RxHWO
OCR = 0
°1 Common channel mode t DSRR 60 ns
728
PES 2050
PCM interface (cont'd)
Conditions
Min
Max
Unit
Transmit timing
Data enable DCX = 0
tDZXR
CL = 200 pF
80
160
ns
Data enable DCX = 1
t DZXF
CL = 200 pF
40
100
ns
Data hold time DCX.= 0
tDH XR
CL = 200 pF
45
160
ns
Data hold time DCX = 1
t DHXF
CL = 200 pF
40
100
ns
Data float on TS EXIT
tHZX
CL = 150 pF
35
80
ns
Time slot x to enable DCX = 0
tSONR
CL = 150 pF
70
130
ns
Time slot x to enable DCX = 1
tSONF
CL = 150 pF
40
100
ns
Time slot x to disable
tSOFF
CL = 150 pF
40
100
ns
Transmit
Timing
elK
TxHWD
Dex = 0
f HZX
TxHWD
DeX = 1
i
I
--..i
--J
fOZXF
TSe
DeX= 0
fSONR
TSe
DeX=1
729
PEe 2050
HOLe interface
Condition
Min
Max
Unit
Receive timing
Receive data setup
t DS
40
ns
Receive data hold
tDH
10
ns
Transmit timing
Transmit data delay
Data float on TS EXIT
tTD
CL
tHZX
CL
Time slot x to enable
tSON
CL
Time slot x to disable
tsoff
CL
Receive
=
=
=
=
200 pF
40
100
ns
200 pF
35
80
ns
150 pF
40
95
ns
150 pF
35
90
ns
Timing
elK
Transmit
Timing
CLK
TxSD
730
PEB 2050
AC testing input. output waveform
AC testing load circuit
2,4
2,0"
2,0
Test pOints/
0,8 /
"
Device
under
test
0,8
0,45
AC testing: inputs are driven at 2.4 V for a logic "'" and 0.45 V for a logic "0".
Timing measurements are made at 2.0 V for a logic "'" and 0.8 V for a logic "0".
731
PEB 2051
Peripheral Board Controller (PBe)
MOS circuit
Preliminary data
Features
•
Board controller for up to 16 subscribers of a digital switching system
•
•
Designed for different PCM systems
Time slot assignment freely programmable for all connected subscribers
•
Control of voice, data, signaling and line board parameters to minimize hardware requirements and to simplify software
•
Provides four full duplex PCM highways for the system interface
•
System control uses the HDLC protocol with X.25 level 2 functions performed by the
PSC
•
•
Standard IJP interface
Two DMA channels for expansion of internal buffer capability of 16 bytes per direction
•
IJP access to all internal data streams including time slot-oriented data streams
• Support of subscriber circuits by generating timing signals
•
Single 5 V power supply
•
Low power consumption
Plastic plug-in package 20 B 40 DIN 41666
40 pins, DIP
Appro •. weight 5.9 g
Dimensions in mm
AG 4/84
733
Peripheral Board Controller (PBC)
PEB 2051
General description
The Peripheral Board Controller PEB 2051 is a device for the control of voice, data, and
signaling paths of up to 16 subscribers on peripheral component boards in digital telephone systems. In combination with the highly flexible Siemens Codec Filter (SICOFI
PEB 2060) it forms an optimized analog subscriber line board architecture. Its flexibility
allows the operation as a general purpose controller for data switching and MUX/Oe MUX
applications.
The PBC controls space and time switching functions between subscriber line devices and
time division multiplex highways. Further, it controls the flow of information between the
subscriber interface ports and a line card local processor. Last, it performs all protocol
control functions, using the HOLC protocol format for all information passing between the.
line card and the central processor via interleaved time slots on the PCM lines.
To meet the different requirements the PBC PEB 2051 provides the following interfaces:
•
8 serial, bidirectionalI/O ports for the transfer of voice, data, control, and signaling information between the PBC and Codec Filters (e.g. SICOFI PEB 2060), digital interface
circuits or signal processors.
•
Four independent PCM interfaces.
•
Bit-parallel interface for the connection of 8 bit standard microcomputers such as the
SAB 8048. The interface is characterized by an interrupt control and two independent
'OMA channels, one for the. transmit and one for the receive direction.
734
Peripheral Bpard Controller (PBC)
PEB 2051
Pin configuration
top view
SIPI.
100 SIP3
SIPS
2
39 SIP2
SIP6
3
38 SIP 1
SIP7
10
37 SIPO
RxHOAO
RxHOAl
5
6
36 RESET
35 INT
TxHOAO
7
310 OACK 1
TxHOA 1
8
33 OACK 0
TxHOB 0
9
32 WR
TxHOB 1 10
PEB 2051
31
VDD
11
30 07
SClK 12
29 06
SIGS/OMIR 13
28 05
sYP
OIR 14
OMOR 15
RxHOB 0 16
27 04
26
03
25 02
RxHOB 1 17
24 01
ES 18
23 DO
Rii
ALE 19
22
vss 20
21 ClK
735
Peripheral Board Controller (PBC)
PEB 2051
Pin designation
Pin No.
Symbol
Name/function
Functional description
SIP 4
Subscriber
I nterface Port
(input/output)
These interface ports are used for
bidirectional, bitserial transfer of
speech-, data- and controlwords to
and from the Siemens-Codec-Filter
(SICOFI) or standard Codec. Corresponding with the direction signal the
PBC PEB 2051 is transmitting the
high level of DIR within the first half
of a 125 )Js frame.
4
SIP 7
5, 6
16, 17
RxHDA0,1
RxHDB0,1
} Receive Highways
Data (input)
Interface ports to the PCM highways.
7, 8
9,10
TxHDA0,1
TxHDB0,1
} Transmit Highways
Data (output)
The displacement between receive
and transmit direction is programmable up to 8 bits.
11
SYP
Synchronization
SYP is a frame synchronization pulse
which resets the on chip time slot
counters.
12
SCLK
Slave Clock
(output)
Clock output for the peripheral
devices. The signals between the
Codec-filter and the PBC are latched
and transmitted with the rising edge
of SCLK.
13
SIGS/DMIR
Signal Strobe
(output, active High)/
Direct Memory Input
Request (output,
active High)
The SIGS-output supplies a programmabie strobe signal. In the DMAmode this pin is used as DMA-inputrequest.
14
DIR
Direction
(output)
DIR is a 8 kHz symmetric frame signal
which controls the direction of the
data transfer from and to the peripheral devices. The PBC is able to receive datas during the low state of
DIR.
15
DMOR
Memory Output
Request (output)
active High
DMIR and DMOR are generated by
the PBC internal HDLC-receiver or
transmitter and are used for handshaking during the data transfer.
18
CS
Chip select
(input, active Low)
CS is used to address the PBC. A low
level at this input enables the PBC to
accept com'mands or datas from a )JP
within a write cycle, or to transmit
datas during a read cycle.
736
Peripheral Board Controller (PBC)
PEB 2051
Pin No.
Symbol
Name/function
Functional description
19
ALE
Address latch Enable
(input, active High)
A high level at this input indicates
that the data on the external bus is an
address selecting one of the PBC-internal sources or destinations. latching into the address latch occurs during the high low transition.
20
21
Vss
ClK
Clock (input)
A standart TTL-Clock provides the
basic timing of the controller. The
clock is synchronous to the PCMclock.
22
RD
Read Strobe
(input, active low)
RD is used together with CS to transfer data from the PBC to a fJP or
memory
23
00
System Data Sus
The data bus transfers data and
commands between the fJP or
memory and the PSC.
30
D7
31
32
Voo
WR
33
34
Ground
± 0.25 V
Supply Voltage
Voo = 5.0
Write Strobe
(input, active low)
During the low state of WR data can
be transfered from the fJP or memory
to the PSC.
DACK0
DACK1
} DMA-Acknowledge
(inputs, active Low)
DACK0 and DACK 1 are used to
acknowledge the DMA-output and
DMA-input request, respectively.
35
INT
Interrupt Request
(output, active Low)
These signal is pulled down, when the
PBC is requesting an interrupt. In that
case the. fJP should enter into an
interrupt routine for reading the
status reg ister 1.
36
RESET
Reset
(input, active High)
A "highft on this input forces the PSC
into reset state. The minimum reset
puIs is 16 complete clock cycles.
737
Peripheral Board Controller (PSC)
PES 2051
Block diagram
SIP
8'
Subscriber
interface unit
PCH
highways
SIP 7
OIR
SIGS
SCLK
SYP
Timing
control unit
Bus interface
control unit
CLK
RESET
Special purpose
registers
PBC Bus
CS
738
ALE RO WR INT Oa-07 OHIR OHOR OACK~ OACK1
OIR
o:J
0
...c.
0
iii"
...
III
2
1
1
4
1
2
3
1
1
cf>
1
1
cf> COP
1 SOP
1 NOP
1
4.2
I
5
6
BIT 7
CONTROL-BYTE
NOP-Command
If no status modification of the SICOFI or control-data exchange with the PBC is required,
a Normal Operation byte NOP is transferred.
7
BIT
NOP-Format
0
11111111111111111
4.3
SOP·Command
If the SICOFI-Status has to be changed, a Status Operation byte SOP is transferred,
which contains the following information:
BIT
7
6
IAD 1 RNoJ
5
4
3
2
1
0
1PU 1TR 1cf> 11 1 LSEL
I
AD , , , , , Address information which is relevant if 2 SICOFls are connected to one
PBC-Port. A SICOFI is identified, if AD is consistent with the level at SA
(see 4.5/6)
AfW . . . . ReadfWrite-information
Enables reading out from the SICOFI or writing information to the SICOFI
(READ = 1, Write = cf»
PU ..... Power up/Power down
PU = 1 sets the SICOFI to power-up mode (operating),
PU = cf> resets the SICOFI to power-down (standby).
TR ..... Trunk offering (Three party conferencing)
If TA = 1, the received voice bytes of channel A and B are added.
LSEL . .. Length select
Defines the number of the subsequent data-bytes
756
SICOFI 4.3.1
Signal Processing Codec Filter
PEB 2060
SOP-WRITE
If the SICOFI-status has to be defined initially or changed, the SOP-Command looks like
¢
7
IADI ¢ IpulTRI 0 11 I LSEL I
and the subsequent configuration-bytes are written into one or both of the two Configuration Registers CR1, CR2 available.
In this case, the meaning of LSEL is
status setting is completed (no byte following)
one byte will follow and is stored in CR1
two bytes will follow and are stored in CR2 and CR1 (see 4.6)
not used
¢
1
¢
1
¢
Corresponding to the configuration-bytes transmitted, the information contained in the
configuration-registers is for
CR1:
where
DB
RZ
RX
RR
RG
.....
.....
.....
.... ,
.....
Disable
Disable
Disable
Disable
Disable
B-Filter (DB = 1), restore
Z-Filter (RZ = ¢), restore
X-Filter (RX=¢), restore
R-Filter (RR = ¢), restore
GX, GR(RG=¢),restore
B-Filter (DB = 0)
Z-Filter (RZ = 1)
X-Filter (RX=1)
R-Filter (RR = 1)
GX, GR(RG=1)
TM ..... Test-Modes
¢
¢
¢
No Test-Mode
¢
¢
1
Analog loop-back via Z-Filter (Z = 1, 11 = ¢)
Disable High-Pass
¢
¢
¢
1
1
Cut off receive-path (HP active)
¢
¢
not used
¢
1
not used
¢
Digital loop back via B-Filter (B = 1, D3 = ¢, HP Active)
Digital loop back via PCM-Register (PCM-in = PCM-out)
and CR2:
¢
7
I DI c I B I AIEL IAMI
p./A
PCS
I
where
D
C
B
signaling PIN SD is input (D = 1) or output (D = ¢)
SC is input (C=1) or output (C=¢)
SB is input (B = 1) or output (B = ¢)
757
SICOFI -
Signal Processing Codec Filter
A
EL
AM
J1.IA
PCS
PEB 2060
SA is input (A = 1) or output (A = ¢)
signaling expansion logic connected (EL = 1) or not connected (EL = ¢)
Address-Mode
one SICOFI (AM=1) or two SICOFls (AM=¢)
connected to one PSC-port
(If AM = ¢, SA is input automatically)
wlaw (J1.IA=1), A-law (J1.IA=¢)
Programmed S-Filter-coefficients (PCS = ¢)
or fixed coefficients for S-Filter (PCS = 1)
Note:
1) The power-on-reset or a hardware-reset via RS-PIN reset all CR1-bits to ¢ (all of
the programmable Filters are disabled except the S-Filter, where fixed coefficients
are used) and set all CR2-bits to 1 (SA, SS, SC, SD are inputs; singaling expansion recognition; wlaw chosen; one SICOFI per PSC-Port). The Serial Interface
Port SIP remains tri-state until the content of CR2 has been defined (transmitted
and loaded).
2) If two SICOFls are connected to one PSC-Port, while initializing, both SICOFls get
the same SOP and CR2- information. The subsequent CR1-byte is assigned to
the addressed SICOFI only. If the two SICOFls need different CR2-information,
the SOP-CR2-sequence has to be provided once again (each SICOFI knows it's
address now).
4_3.2
SOP-Read
If the SICOFI-Status has to be evaluated, with the SOP-Command
7
¢
1AD 1 1 1 x 1 x 1 ¢ 1 1 11 1 ¢ 1
the content of CR1 and CR2 is read back on SIP. The meaning of the SOP-Sits is as
described in the SOP-write section.
4_4
COP·Command
7
With a COP-Command
coefficients for the programmable filters can be written into or read out from the
coefficient-RAM.
Where
AD ..... Address (relevant if 2 SICOFls are connected to one PSC-Port)
R/W . . .. Read (R/W = 1), Write (R/W = ¢)
Code
000
001
010
011
100
101
110
111
758
S-Filter coefficients part 1
S-Filter coefficients part 2
Z-Filter coefficients
S-Filter delay coefficients
X-Filter coefficients
R-Filter coefficients
GX, GR-coefficients
not used
(followed
(followed
(followed
(followed
(followed
(followed
(followed
by
by
by
by
by
by
by
B bytes
B bytes
B bytes
4 bytes
B bytes
B bytes
4 bytes
of
of
of
of
of
of
of
data)
data)
data)
data)
data)
data)
data)
SICOFI -
Signal Processing Codec Filter
PEB 2060
LSEL
cf>
1
cf>
4
12
cf>
8
Byte
Byte (presently not used)
Byte
Byte
7
Data-Byte Format
cf>
I S I sc I sc I sc I S I sc I sc I sc I
coefficient 1
S:
SC:
2
Sign
Shift-Code
Note: Subsequent to reading of the Filter coefficients, CR2 and CR1 are transmitted
additionally.
4.5
Signaling-Byte
The signaling interface of the SICOFI consists of 10 pins 3 transmit signaling inputs
Sin' 3 receive signaling outputs Sam and 4 signaling pins SA, SB, SC, SD, which are
programmable individually as either transmit input or receive output.
Data present at Sin and possibly at some or all of SA, SB, SC, SD (if programmed as
inputs) are sampled and transferred serially on SIP to the PBC.
Data received serially on SIP are latched and fed to Sam and possibly to some or all
of SA, SB, SC, SD (if programmed as outputs).
The signaling field format generally is
7
cf>
in transmit-direction
I SI1 I SI21 SI31 SO I sc I S8 I SA ISEL I
in receive-direction
IS011s021s031 SO I sc I S8 I ~
where SEL is the signaling expansion bit if EL = 1 in CR2.
For the different cases possible, the signaling byte format at SIP is for
CASE
BIT
1
2
3
4
5
6
A·SICOFI
B-SICOFI
A-SICOFI
B·SICOFI
Receive
6 5
S01 S02S03
S01 S02S03
S01 S02 S03
7
Signaling
4 3 2
Y Y Y
Y Y Y
SO SC SB
byte
1
cf>
Y Y
Y Y
SA Y
S01 S02 S03 SO SC SB SA y
S01 S02 S03 Y Y Y Y Y
Y Y Y Y S01 S02 S03 Y
S01 S02 S03 SO Y Y Y Y
Y Y Y Y S01 S02 S03 SO
Transmit Signaling
7 6 5 4 3 2
SI1 SI2 SI3 SO SC S8
SI1 SI2 SI3 SO SC SB
SI1 SI2 SI3 cf> cf> cf>
SI1 SI2 SI3 Z Z Z
SI1 SI2 SI3 SO Z Z
Z Z Z Z SI1 SI2
SI1 SI2 SI3 cf> Z Z
Z Z Z Z SI1 SI2
byte
1 cf>
SA X
SA Z
cf> X
Z Z
Z Z
SI3 SO
Z
Z
SI3 cf>
Z ... High impedance state
Y .. .Don 't care state
X ... Either high or low level state, thai is not evaluated by the PBC
759
SICOFI -
Signal Processing Codec Filter
PEB 2060
cases:
1 one SICOFI connected to one PBC-Port; EL = cp (no expansion logic); SA, SB, SC,
SO programmed as transmit signaling inputs
2 one SICOFI; EL =1 (expansion logic provided); SA, SB, SC, SO programmed as
in case 1
3 one SICOFI; EL = cp; SA, SB, SC, SO programmed as receive signaling outputs
4 one SICOFI; EL = 1; SA, SB, SC, SO programmed as in case 3
If an expansion logic is provided (cases 2, 4), the signaling bits SA, SB, SC, SO
which are programmed as signaling inputs or outputs can be used as additional
expansion bits in receive or transmit direction, respectively (As far as the SICOFI
is concerned, SIP is in a high impedance or don't care state while these bits are
transfered) .
5 Two SICOFls connected to one PBC-Port; SO programmed as transmit signaling
input
6 Two SICOFls, SO programmed as receive signaling output. If two SICOFls are connected to one PBC-Port, no expansion logic is provided. SA is programmed as input
automatically and defines the addressed SICOFI: SA =cp: A-SICOFI
SA = 1 : B-SICOFI
SB and SC are not usable in this configuration
4.6
Programming Procedure
The following table shows some control byte sequences. If the SICOFI has to be configured completely while initializing, up to 58 bytes are transfered.
DIR
Normal Status
NOP
NOP
NOP
NOP
SOP-Write
SOP
NOP
CR2
NOP
CR1
SOP-Read
SOP
CR2
Y
CR1
COP-Write
COP
NOP
NOP
COP-Read
COP
DB1
DB1
y
{NOP}
SOP
COP
DB2
NOP
DBN
{NOP}
COP
SOP
DBN
y
NOP
CR2
Y
CR1
{NOP}
COP
SOP
where
y ... ignored
DBn ... Data Bye #n
5.
Operating modes
5.1
Basic setting
Upon intial application of VDD or RS = 1 while operating, the SICOFI enters a basic setting mode.
Additionally, once the VDD supply is up, if it falls below a voltage, which could lead to
the loss of programmed coefficients (spikes on VDD-rail are ignored), the SICOFI is
forced to this mode again. Basic setting means, that the configuration registers 1 and
2 are initialized (see 4.3.1), receive signaling registers are cleared, SIP is in a high
impedance state, the analog output and the receive Signaling outputs are forced to
ground.
The serial interface is active to receive commands.
760
SICOFI 5.2
Signal Processing Codec Filter
PEB 2060
Standby mode
By reception of an SOP-command to load CR2, from the basic setting the SICOFI enters
the standby mode (basic setting replaced by individual (CR2). Being in the operating
mode, the SICOFI is reset to standby mode with a power-down command.
The interface is active to receive and transmit new commands and data.
5.3
Operating mode
From the standby mode, the operating mode is entered upon recognition of a powerup command. A received power-up command is recognized only, if Vss :j:GND at this
instant, otherwise the SCIOFI stays in the standby mode.
6.
Transmission Characteristics
The target figures in this specification are based on the subscriber line board requirements. The proper adjustment of the programmable filters (trans-hybrid balancing: B;
line termination: Z; frequency-response-correction: X, R) needs a complete knowledge
of the SICOFls analog environment. In the figures listed below it is assumed therefore,
unless otherwise stated, that the programmable filters have the following transfer
functions:
A ¢ dBm¢ signal is equivalent to 1,6 VRMS. A 3 dBm¢ signal is equivalent to 2.26
VRMS which corresponds to the overload point of 3.196 V
SYMBOL
PARAMETER
DRA
HD
IMD
Gain (either value)
Deviation from ideal
value
Deviation from initial
value
Loop gain (digital to
dig)
Transmit delay,
absolute
Receive delay, absolute
Harmonic distortion
Intermodulation
CT
CTxR
G
G1
DXA
MIN
TYP
MAX
UNITS
TEST CONDITION
±0.1 ±0.2
dB
800Hz at ¢ dBm¢
±0.1 ±0.2
dB
800Hz at ¢ dBm¢
± 0.1
dB
-46
-42
-56
!,sec
!,sec
dB
dB
dBM¢
f= 1.4 kHz, Note 1
f = 300 Hz, Note 1
Note 2
Note 3, 2f,-f2
Note 4, 2f,-f 2
Crosstalk
Transmit to Receive
-70
dBm¢
CT RX
Receive to Transmit
-70
dBm¢
¢ dBm¢,f = 300Hz to
3400Hz
¢ dBm¢.f=300Hz to
3400Hz
N
NRP
NRS
Idle channel noise
weighted
single frequency
-75
-55
dBm¢p
dBm¢
350
352
f = 0 to 100kHz, loop
around
761
SICOFI -
Signal Processing Codec Filter
Note 1:
Note 2:
PEB 2060
typical delays for B =0, 2 =0, R =X = 1, including delay through AID, D/A
Specific filter-programming (2, R, X) may cause additional group delays.
single frequency components between 300 Hz and 3400Hz, produced by a
dBM sine wave in the range 300Hz to 3400Hz
Note 3:
equal input levels in the range of -4dBM to -21 dBm, different frequencies
in the tange of 300 Hz to 3400 Hz
Note 4:
input level -9dBm, frequency range 300Hz-3400Hz and -23dBm, 50Hz
6.1
A-lawlJl"law Conversion codes
The encoding laws according to CCITT or AT&T recommendations are digitally
selectable.
6.2
Gain Adjustments
The transmit and receive path gain values are digitally programmable.
Convered range
Resolution
-40 ... +10,2dB
=::;0,5 dB
-40 ... +12 dB
=::;1,2 dB
All level-dependent charaCteristics hold true for any gain setting within the above defined
range.
6.3
Attenuation distortion
The attenuation-characteristics for transmit and receive-path are shown in the following diagrams.
dB
2
L
-
I
I
SICOFI specification
SICOFI typical
c
o
-
~c
0.65dB
~'"
0.125dB
-0.125dB
-1
0.05
0.1
0.18 0.2
0.3
0.5
1.0
2.0
3.0 3.4
ATTENUATION DISTORTION in RECEIVE DIRECTION
Reference frequency is 1 kHz
Input Signal level is dBm
762
5.0 kHz
SICOFI -
Signal Processing Codec Filter
PEe 2060
dB
2
L
SlCoFI1specificatiJ
-
SICOFI typical
I
c:
o
r--
.~
"c:
~
\.
o
0.65dB
0.125dB
0.125dB
-1
0.05
0.1
0.180.2
0.3
0.5
1.0
2.0
3.0 3.4
5.0 kHz
ATTENUATION DISTORTION in TRANSMIT DIRECTION
Reference frequency is 1 kHz
Input signal level is rf>dBmrf>
6.4
Group delay distortion
For either transmission path, the group delay distortion is within the limits of the following
figure. The minimum value of the group delay is taken as reference (see table).
~s
1000
l-
Transmit
!- Translt
750
IlA
I'''';''
500
420
\
250
150
\
'//h
!1/////,
85 Receiv e~
500 600
1000
--
~'/."h
....'.:
f
~
2000
2400
2800 3000
4000 Hz
GROUP DELAY DISTORTION
Input signal is rf>dBmrf>
6.5
Out-ol-Band Signals at Analog Input
When an out-of-band sine-wave signal with frequency f and level A is applied to the
analog input, the level of any frequency component below 4 kHz at the digital output
causes by the out-of-band signal is at least X dB below the level of a signal at the same
output originating from an 800 Hz Arf>dBmrf> sine-wave signal applied to the analog input.
763
SICOFI -
PEB 2060
Signal Processing Codec Filter
The minimum requirements fullfilled are listed below.
6.6
out-of-band
input frequency f
out-of-band
input level A
attenuation at
digital output
OHz=s;f=s; 60Hz
60Hz=s;f=s; 100Hz
3400Hz=s;f=s;4000Hz
4000Hz=s;f=s;4600Hz
4600Hz=s;f=s; 12kHz
12kHz=s;f=s; 20kHz
20kHz=s;f
-45dBmO=s;A=s;OdBmO
-45dBMO=s;A=s;OdBmO
-45dBmO=s;A=s;OdBmO
-45dBmO=s;A=s;OdBmO
-45dBmO=s;A=s;-15.8dBmO
-45dBmO=s;A=s;-23.2dBmO
-45dBmO=s;A=s;-25 dBmO
25dB
10dB
OdB
14dB
35dB
35dB
35dB
Out-of-8and Signals at Analog Output
With code words representing any sine-wave signal with the frequency f at a level of
ct>dBmct> applied to the digital input, the maximum level of the spurious out-of-band
signals is listed in the table below.
digital input
frequency range
300Hz
300Hz
3400Hz
3400Hz
6.7
spu rio us out-of-band
signal frequency range f
level
...... 3400Hz
...... 3400Hz
...... 4000Hz
...... 4000Hz
OdBmO
OdBmO
OdBmO
OdBmO
f<90kHz
90kHz=s;f=s; 1 MHz
3400Hz=s;f=s;4000Hz
4000Hz=s;f=s;4600Hz
max. level at
analog output
-40dBmO
-44dBmO
OdBmO
-14dBmO
Gain Tracking
The gain deviations stay within the limits in the figures below for either transmission path.
dB
2
e.G
t
O.4dB
0.2dB
I
~
-,
-2
-70
-60
-50
-40
-30
-20
-'0
o
'0 dBmO
- - . . Input level
GAIN TRACKING
Measured with noise signal according to
CCITT-Recommendation
"Reference level is -1ct>dBmct>
764
SICOFI -
PEB 2060
Signal Processing Codec Filter
dB
2
I
1.2dB
O.4dB
O.2dB
o
-1
"
-2
-70
-60
-50
-30
-40
-20
o
-10
10dBm
- - . . Input level
GAIN TRACKING
Measured with sine wave in the range 700-11 OOHz
• Reference level is -1 ¢dBm¢
6.8
Total Distortion
The signal-to-total distortion ratio independent of the actual gain adjustment exceeds
the limits in the following figures_
dB
40
35.9
34.2
./
SID
t
30
V
~/
29.6
20
-
35.9
\
28.3
t-
10
o
-60
-55
-50
-40
-34
-30 -27
-20
-10
o dBmO
SIGNAL-TO-TOTAL DISTORTION
Measured with noise signal
765
SICOFI -
PEe 2060
Signal Processing Co dec Filter
dB
40
35
/
SID
t
30
/
29
24
20
10
-60
-50
-45
-30
-40
-20
-10
o dBmO
SIGNAL-TO-TOTAL DISTORTION
Measured with sine-wave in the range 700-11 OOHz,
excluding submultiples of 8kHz
7.
Electrical characteristics
7.1
Absolute maximum ratings
Storage temperature
Ambient temperature under Bias
VDD with respect to AGND
VS5 with respect to AGND
AGND to DGND
Analog input and output voltage
with respect to VDD
with respect to V 55
All digital input and output voltages
with respect to DGND
with respect to V DO
Power dissipation
7.2
Operating range
Ambient temperature
V DD
= 5V
± 5% V 55
DGND=OV AGND=OV
766
= 5V ± 5%
-60 to 125°e
-10 to aooe
-0.3 to 5.5V
-5.5 to 0.3V
±O.3V
-11 to +0.3V
-0.3 to + 11V
-0_3 to 5_5V
-5.5 to 0.3V
1W
SICOFI -
Symbol
IDD
Iss
PSRR
Pdq,
Pd1
7.3
PES 2060
Signal Processing Codec Filter
Parameter
VDD supply current
standby
operating
Vss supply current
standby
operating
Power supply rejection
Min
Typ
Max
6
40
mA
mA
±5% supply
± 5% supply
6
8
mA
mA
dB
±5% supply
±5% supply
0-------.......-----~
PSB 6520
Tone Ringer
Functional description
The tone ringer PSB 6520 is designed for use as an electronic bell in a telephone set. Fig. 2
shows the block diagram and fig. 3 the application circuit of the PSB 6520 in the
telephone set.
Fig. 2
Block diagram of the PSB 6520 tone ringer.
nl
1~I~F
Voc
7
~@
~
1
*
Threshold circuit
with
hysteresis
-
Switching
frequency
generator
r--
Tone
frequency
generator
r-- Output stage r2
Vau
PSB 6520
2
GND
3
4
=:= [s
JRT
The Ie contains an oscillator which generates a square wave Voltage. Thefrequencyof this
voltage is periodically switched by a second oscillator back and forth between two basic
values having a ratio of 1 : 1.38. The basic frequency fn is adjusted by the resistor RT and
the switching frequency fs by the capacitor Cs (fig. 12 and 13).
Tone frequencies
fn [Hz] = 2. ~~~o~ 0
f2T
4
±
10%
[Hz] = 0.725· fn
±
2%
±
15%
750
Switching frequency fs [Hz]·= C (nF)
Good frequency stability is achieved by means of internal temperature compensation.
771
PSB 6520
Tone Ringer
An output stage increases the generated tone voltage and transfers it to a piezo-resonator
via an internal resistor. An electro-dynamic converter can be similarly driven, but must be
matched to the internal resistance of the output stage (fig. 6,,7,8 and 12) with a transmitter.
An integrated bridge rectifier enables, direct input via the call AC voltage signal (tip (a),
ring (b) wires or) via DC voltage (independent of polarity). A DC voltage supply without use
of the integrated bridge is possible via the connections 2 and 7. In conjunction with a
Z-diode, the bridge rectifier serves simultaneously as an overvoltage protection.
The application circuit shown in fig. 3 can handle overvoltages occurring due to lightning
strikes between terminals a and b according to the VDE 0433 standard, orthe occurrence
of an AC voltage of 110 V/50 Hz over a period of 30s, thus avoiding the possibility of any
damage to the 10. The threshold circuit with high threshold voltage and hysteresis is
designed to prevent activation (fig. 4) of the IC due to noise pulses.
Fig. 3
PSB 6520 application circuit for telephone sets.
1~F
Tip
Qrl
2,2kl1
r------------l
I
I
I
I
I
I
I
PSB 6520
VQ ,
Ring
b
I
:
*"'2,2~F
10~F
I
Piezoconverter
=
(47nF)
:~O
{~~
II[}
I
I
I
I
IL ____________ JI
The characteristic curves from fig. 4 to fig. 6 show the relation-ship between current consumption, supply voltage, output current, output power, output restistance and AC calling
voltage.
772
PSB 6520
Tone Ringer
Maximum ratings 1)
Supply voltage
Voltage pin 3 to pin 2
Voltage pin 4 to pin 2
Noise current
into the output
Test conditions
Voe
V3•2
V4.2
Min.
10 ms
IN OUT 30 IJs/mark to space
Max.
Unit
28
5.5
7
V
V
V
20
mA
125
°C
90
Vrms
110
22
mA
15
70
kHz
°C
ratio 1 : 100
Storage temperature
Tstg
Operating range
Calling voltage
Vab
Supply voltage
Tone frequency
Ambient temperature
I.
fIT
f= 50 Hz
Test circuit
fig. 3
Continous operation
5 s operation/
10 s pause
DC supply current
Validity of the
formula fIT
Tamb
DC characteristics
Supply voltage
Current. consumption
without load
-40
Test conditions
Voe
IDe
0.1
-20
Min.
Max.
Unit
26
V
1.5
1.8
mA
12.6
8.4
7.4
13.0
8.8
8.5
V
V
KQ
Typ.
-20°C to 70°C
Vs
= 8.8 V to
26 V.
Vrms
25°C
Hysteresis circuit
Threshold voltage
Switch-OFF voltage
Initial resistance
Voltage2) deviation at
output pin 5 referenced
to pin 2
Short circuit current
Tone frequency
temperature coefficient
Vth
VOFF
RINI
-20°C to 70°C
-20°C to 70°C
25°C
VOUT
25°C
lOUT
U5
TC
-20°C to 70°C
= 20 V.
25°C
12.2
8.0
6.4
Vs-3
35
V
mA
8.10.4
K· 1
1) Maximum ratings are absolute limits and the Ie can be destroyed by exceeding them. Functioning of the
integrated circuit is not assured under conditions other than those stated in the electrical characteristics.
Operation for long periods of time under maximum rating conditions can adversely affect the reliability of the
integrated circuit.
') An internal resistor of 500 Q is connected before the output.
773
PSB 6520
Tone Ringer
Characteristic curves
Fig. 5
Dependence of amplitude of
output current on the supply
voltage Vee in the case of short-circuit
Fig. 4
Dependence of current consurntion
on the supply voltage Vee without
output load
mA
60
mA
3
.
I
lOUT
I
/ VI
I
r
40
2
,/
t
V
I
I
I
II
I
I
I
/
/J~'
20
III
j/
II
I
/
I
I
oII
o
I
I
20
30 V
-Voc
Fig. 6
Dependence of output power
on the load resistance RouT (ohmic)
mW
BO
/' "'\
/ \
40
/
20
/
/
\
/
o
0.1
0.2
0.5
2
\
\
5
-ROUT
774
1/'
IV ,/
IVI
10 kll
10
20
30 V
PSB 6520
Tone Ringer
Fig. 6.1
Test circuit to determine output power at different load resistances
PSB 6520
w
Fig. 7
Test circuit to determine output power for variable call voltage
PSB 6520
1kll
Vab
w
775
PSB 6520
Tone Ringer
Fig. 8
Dependenca of effective output
resisfimce on the call voltage V,b
Fig. 7.1
Dependence of output power
on the call voltage for
power matching
mW
80
kfl
2
r.
/---
I
-
~
~
1\
I
40
/
/
20
/
00
10
20
30
40
50
60
70
o
80 V
Delay times
Fig. 9
Test circuit to determine delay times
r-------------..,
I
I 1~F
I
I
Q
b
776
I
I
I
IL _____________ .J
10
20
30
40
SOV
PSB 6520
Tone Ringer
Delay times
Fig. 9.1
Dependence of delay times
tON' tOFF
on V. b
r
I
I
I
r-
-
I
t,
-t
r--------~
I
\\
I
I
to
!
\
I
t,
~
V.b
>30V
-t
I
~b < 30V
-t
----------
t, - to
Effective value of input signal (call voltage V,b)
Effektive value of output signal (output voltage VOUT )
Time duration of applied call voltage V"
777
Tone Ringer
PSB 6520
Fig. 10
Dependence of switch-on delay
time tON on V. b (independent of RouT)
ms
Fig. 11
Dependence of switch-off delay
time tOFF on V. b (independent of Rv)
ms
100
150
\
\1
\ \
fOFF
~1 r\
-,'\ ~'\
Rour= 100kQ_
\ \ \ \1\
50
Rour=10kQ
100
[\1\
I
Ro~= 1klQ-
Rv=10 kQ
1\ r\\ Ry=8 kQ
I I I
~1\
20
r
~
1 II
\\ Ry=6
kQ
rI I
\
/
II
50
/
Ry=4
t\.
'I
I II
II
J'\ t'-. Ry=2
I II
Ry=O
i II
10
20
50
100 V
20
40
BOV
60
- - V.b
Fig. 1,2
Dependence of the frequencies
flT and fn on the resistor RT•
Fig. 13
Dependence of switching
frequency on the capacitor Cs
KHz
10
Hz
100
5
50
fzr
1"1
2
t,:f2=1.38
.\
t,T
~
\&
1\
~1\
10
0.5
"''\\."\.
''
5
'\~
~
0.2
2
0.1
1
2
5
10
20
~RT
778
50
100 KQ
~~
~
10
2
5
100
--[5
5 1000 nF
Tone Ringer
PSB 6520
Recommended circuitry of PSB 6520 with a small loudspeaker
Fig. 14
Matching a 4 Q loudspeaker to the PSB 6520
PSB 6520
10~F135V
I~
2. [ }
n,
3
2
4S1
7
Transformer
Pot core:
Ordering code 865651-KOOOO-R030
(18x11)
Material:
Bobbin:
N30, A = 5600 nH/W2
Ordering code 865652-80000-T001
Windings:
n,
= 800, d, = 0.08 mm CuL
n2
=
50, d2
= 0.4 mm
I
CuL
779
PSB 6521
Tone Ringer
Preliminary Data
The PSB 6521 bipolar integrated circuit, in conjunction with an electro-acoustic converter, replaces
the mechanical bell in the telephone set (Fig. 1). The component generates two periodic switchable tone frequencies that can either drive a piezo-ceramic converter directly, or a loudspeaker.
Special features
•
•
•
•
•
•
•
Integrated bridge rectifier allows direct input via call signal (ac voltage)
Low current consumption (several tone ringers can be connected in parallel)
High noise immunity due to built-in voltage-current hysteresis
Direct replacement of the mechanical bell requiring 4 additional external components
and an acoustic converter
Two tone frequencies, switched internally
Tone and switching frequencies adjustable by means of a resistor and a capacitor
Overvoltage protection in accordance with VDE 0433 (2kV - 10f700JLs)
Pin configuration
VAC '
8
VAC ,
GND 2
7
Vac
I
PSB 6521
Cs
3
6
N.C.
RT
4
5
VauT
Pin designation
Pin No.
1
2
Name
3
VAC'
GND
Cs
4
RT
5
6
N.C.
7
Vac
8
VAC ,
VauT
Function
AC voltage input (Fig. 3)
Ground
Connection for capacitor Cs
Connection for resistor RT
Output voltage
Not connected
Connection for smoothing capacitor 10JLF (internal supply
voltage)
AC voltage input
781
Tone Ringer
PSB 6521
Fig. 1
Block diagram of a standard electronic telephone set (Push button set and speech circuit connected in series)
Tip (a)
D-----4~-.,
PUSHBUTTON
SET
WITH PSB 8590
DTMF-DIALING
OR
PULSE DIALING
TONE RINGER
MODUL
WITH
PSB 6521
S
M
Ring ( b ) D - - - - - - " - - - - - - - - - 4 - - - -_ _ _ _--'
Functional description
The tone ringer PSB 6521 is designed for use as an electronic bell in a telephone set. Fig. 2
shows the block diagram and Fig. 3 the application circuit of the PSB 6521 in the telephone set.
Fig. 2.
Block diagram of the PSB 6521 tone ringer.
II
V oc
10 JF
I
~
VAel
~
~
Threshold
circuit with
hysteresis I-
Switching
frequency
generator
Tone
I - frequency I generator
PSB 6521
2
CMD
782
3
4
=res
OR1
Output ~V
stage
ex
T
Tone Ringer
PSB 6521
The IC contains an oscillator which generates a square wave voltage. The frequency of this voltage
is periodically switched by a second oscillator back and forth between two basic values having
a ratio of 1 : 1.25. The basci frequency fn is adjusted by the resistor AT and the switching frequency fs by the capacitor Cs (Figs. 12 and 13).
1,93 • 104
Tone frequencies
Switching
frequency
±
fn [Hz]
A [kO]
15%
f'T [Hz]
0,8 • fn
±2%
750
fs [Hz]
=
±
C(nF)
15%
Good frequency stability is achieved by means of internal temperature compensation.
An output stage increases the generated tone voltage and transfers it to a piezo-resonator via
an internal resistor. An electro-dynamic converter can be similarly driven, but must be matched
to the internal resistance of the output stage (Figs. 6,7,8 and 12) with a transmitter.
An integrated bridge rectifier enables direct input via the call a.c. voltage signal (tip (a), ring (b)
wires or via d.c. voltage (independent of polarity) ). A d.c. voltage supply without use of the
integrated bridge is possible via the connections 2 and 7. In conjunction with a Zener diode,
the bridge rectifier serves simultaneously as an overvoltage protection.
The application circuit shown in figure 3 can handle overvoltages occurring due to lightning strikes
between terminals a and b according to the VDE 0433 norm, or the ocurrence of an a.c. voltage
of 11 OV/50Hz over a period of 30s, thus avoiding the possibility of any damage to the IC. The
threshold circuit with high threshold voltage and hysteresis is designed to prevent activation (Fig.
4) of the IC dUe to noise pulses.
I
Fig. 3 PSB 6521 application circuit for telephone sets.
1 i'F
~ -
2.2 kll
-
-
-
-
-
-
-
I
V,o
Ring (b)
B
+
10 pF
-T
I
Ti P (a) --jl---l--£::=:=J--,
7
6
I
I
I
5
I
--L 2.2 i'F
PIEZO
CONVERTER
I
- - 1 - - - -.. . .
T
(47 nF)
0
~OO{[91
I
IL
_ _ _ _ _ _ _ _I
783
Tone Ringer
PSB 6521
The characteristic curves from fig. 4 to fig. 6 show the relationship between current consumption, supply voltage, output current, output power, output resistance and a.c. calling voltage.
Maximum ratings
1l
Test condition
Supply voltage
Voltage pin 3
to pin 2
Voltage in 4
to pin 2
Noise current
into the output
10ms
30ns/mark to
space ration
1 : 100
Storage
temperature
11
Max.
Min.
-40
Unit
28
v
5.5
V
7
20
V
mA
125
Maximum ratings are absolute values and the IC can be damaged by exceeding them. Functioning of the integrated circuit is not assured under conditions other than those stated in the
electrical characteristics. Operation for long periods of time under maximum rating conditions
can adversely affect the reliability of the integrated circuit.
Operating range
Test condition
Calling voltage
V'b
Max.
Min.
Unit
f = 50 Hz
Test circuit
Figure 3
Continuous operation
5 sec operationl
10 sec pause
Supply voltage
I.
DC supply current
Tone frequency
fn
Validity of the
lormula In
Ambient
temperature
784
Tamb
22
mA
0.1
10
kHz
-20
70
Tone Ringer
PSB 6521
D.C. characteristics
Test condition
Supply
VDe
Current consumption , DC
tion without load
Hysteresis
circuit
Threshold
Vthrsh
voltage
Switch-off
voltage
V'ti
Initial
resistance
R'N'
Voltage' deviation
VOUT
at output Pin 5
referenced to pin 2
Short circuit
current
lOUT
Tone frequency
Te
temperature
coefficient
Min.
-20°C to 70 e
VS = B.8V to 26V,
25°C
Max.
Typ.
Unit
1.5
26
1.8
V
mA
0
-20° to 70°C
12.2
12.6
13.0
V
-20 0 e to 70°C
8.0
B.4
B.8
V
25°e
25°C
6.4
7.4
Vs"3
8.5
Kn
V
U5 =20V, 25°C
-20°C to 70 0 e
35
8.1(5 4
mA
K-'
• An internal resistor of 500n is connected before the output
I
785
PSB 6521
Tone Ringer
Characteristic Curves
Fig. 4
Dependence of current consumption on the
supply voltage VDC without output load.
mA
3
IDe
t
,
2
I
III
I
'I
I
/1
II
I
I
I
I
o IJ
o
I
I
I
I
10
20
30
VOFF VI""" - -..... Voc
V
Fig,. 5
Dependence of amplitude of output current on
the supply voltage VDC in the case of short
circuit.
mA
60
I
lOUT
t
ltV
IV~J
40
1,/
I
/
1,/ /
/~
20
~
o
o
1/1
10
20
30
- - - I.... Voc
786
V
Tone Ringer
PSB 6521
Fig. 6
Dependence of output power on the load
resistance R,", (ohmic)
mW
80
L-..
V
40
/
20
/
\
\
/
\
\
/
o
0.1
0.2
0.5
1
2
5
10 kQ
~ROUT
Fig. 6.1
Test circuit to determine output power at
different load resistances
I
2.2 rF
10 rF
PSB 6521
ROUT
W
b
787
Tone Ringer
PSB 6521
Fig. 7
Dependence of output power on the call
voltage for power matching
rnA
80
I
v-
/
40
/
/
20
/
o
o
10
20 30
40 50
60
70 80 V
- - - . . Vab
Fig. 7.1
Test circuit to determine output power for
variable call voltage V"
2.2
~F
1 ~F 2.2 k!l
10l'F
788
PSB 6521
1 k!l
w
Tone Ringer
PSB 6521
Fig. 8
Dependence of effective output resistance on
the call voltage V"
kn
2
""- 1\
ROUTrms
t
'\
o
10
20
30
40
- - - a...
50 V
Vab
Delay times
Fig. 9
Test circuit to determine delay times
I
r - - - - - - - - - - - - --,
I
f3vff__a_',1_11~F
__ ~
{
V'"~
=
I
I
2.2 kfl
.---_;-1_-,-_--,
10 ,F I-..r---r---r--
01
b
789
Tone Ringer
PSB 6521
Fig. 9.1
Dependence of delay times too' tOff on V"
t
r-----V".30V
I
I
I
~
I
to
-"t
t,
V'b
Your
t
,..---------I
I
I
I
I
'\
'
'
I
to
t,
)
I
---..t
V'b
Your
t
r
I
~
I
to
V,b=30V
)
I
I
I
t,
_ _ _ Effective value of input signal
(Call voltage V.,)
Effective value of output signal
(Output voltage Vour)
t, - to
790
Time duration of applied call
voltage V"
----"1
Tone Ringer
PSB 6521
Fig. 10
Dependence of switch-on delay time too on
(independent of ROUT)
v""
100
\
\
1\ \ 1\
~,
,\~
\\ \ \ ~\
\ i\ \ ~\
~\ "
Rv '" 10 k!l
\\ 1\ ~~RvI I =86 k!lk!l
=
\.
20
~\
10
" " f1
20
Rv = 4 kO
II
= 2 kO
= 0 k!l
100 V
50
---II
....
Vab
Fig. 11
Dependence of switch-off delay time t," on
Vab (independent of Rv)
150
toff
t
RO~T10o' k!l
•
I
100
ROUT10 kl!
fJ
Rv'1 kol-
I. I
'/ II
50
I
I
o
o
20
40
60
80 V
---I"~VDC
791
PSB 6521
Tone Ringer
Fig. 12
Dependence of the frequencies fn and f'T on
the resistor RT.
fir f'T [KHz)
t
10
"-
5
~
f,zf,c1,25
"\
fir
2
~"\
f"
~
"\
.5
~
"\
.2
.1
~
"\
1
5
2
10
20
50 100
--.R r [KQ)
Fig. 13
Dependence of switching frequency on the
capacitor CUM
f, [Hz)
t
100
50~~----+-~---+--~r-~
20~-+~~+-~---+----r-~
2~-+---+--+--I---"Nlrr---1
o
792
2
5
100
5
2
- - . CUM [nF)
PSB 6521
Tone Ringer
Recommended circuitry of PSB 6521 with a small loudspeaker
Fig. 14
Matching a 4Q loudspeaker to the PSB 6521
2 I'F 135V
1,:,F
---::--"
a
2.2 kll
10l'F/35V
PSB 6521
b
Transformer
Pot core
(1Bx11)
Material
Bobbin
Windings
: Siemens Ordering code: B65651-KOOOO-R030
: N30, AL = 5600 nH/W 2
: Siemens Ordering code B65652-BOOOO-T001
: N1 = BOO, d1 = 0.08mm C"
N2 = 50, d2 = O.4mm C"
793
PSB 6620
Ringing Detector
Preliminary data
Features:
•
Integrated bridge rectifier allows direct connection to an AC voltage (e.g. a telephone
call signal)
Low current consumption
High "tapping" (noise) immunity
Built-in hysteresis for stable operation
Only three external components necessary
Regulated 5V output voltage
Logical TTL/CMOS output signal (open collector)
Overvoltage protection in accordance with VDE 0433 (2kV-10/700I-'s)
Pincompatible with TCM 1520 (Texas Instruments)
•
•
•
•
•
•
•
•
Pin configuration
V
AC2
8
V
7
GND
AC1
LouT
2
N.C.
3
6
Voc
S,,,
4
5
N.C.
PSB 6620
Pin description
Pin No.
1
2
3
4
5
6
7
8
Symbol
Description
VAC '
L001
N.C.
S
'"
N.C.
VDC
GND
AC voltage input
Logical TTL output (low active)
not connected
5V supply-voltage output
not connected
DC supply voltage input
ground
AC voltage input
VAC '
AG 10/84
795
Ringing Detector
PSB 6620
General description
The integrated circuit PSB 6620 is designed to detect a telephone call signal (AC voltage).
The supply voltage of the IC is divided from the AC-input-voltage (call signal). During the active
state of the device a regulated 5V DC-voltage and a TTL/CMOS-logic level is available at the
outputs. The high threshold activation voltage provides a good immunity against noise (e.g. dialing signals, charge indicator) and a built-in voltage hysteresis guarantees the stable operation.
The regulated 5V voltage (pin 4) of the PSB 6620 allows to supply other devices. The PSB 6620
is not limited to telephone applications. For example the device can be used to build up an inexpensive AC-voltage detector.
Block diagram with external components
1/LF 2k2
o-1l--'C::::J--<
-..
Z,,'
]j
28V
+
12.SV
I ~-j-_--+-=--~"""_---+--"'"_~~-=-~I GND
Electrical charact.eristics
Maximum ratings
11
Test condition
Supply voltage
(pin1 to pin8)
VAC P'"
Voltage pin 6 to pin 7 VDC
Output current
'N OUT
Input current AC
IP
Pulse current AC
"
Total power
consumption
Operating ambient
temperature
Storage ambient
temperature
796
Max.
Min.
28
26
20
30
Pin 1-8
pulse = 100ILs
pause=30s
Unit
V
V
mA
mA
A
W
Ptot
Top
-20
70
°C
T.to
-75
150
°C
Ringing Detector
PSB 6620
Operating characteristics (T'mb = 20°C to 70°C)
Test conditions
Supply voltage
Current consumption
without load
Supply output voltage
Supply output current
Logical output voltage
(pin 2 to pin 7)
Max. voltage on the
logical output
Logic output current
Vee
'ee
Vs,",
Voe=25V
Min.
0,4
VlauT
4,5
' SOUl =4mA ' T=25°
8
Rl =5000
VlauT = L, 'lauT = 5mA
VLoutmaK
Vl,", = H '/l,"' ~ 1mA
'Lout
VLout = 1V
'sauT
Temperature
coefficient from
Supply output voltage TCvs
Logical output Voltage TC vl
Typ
0,6
5
10
0,25
Max.
Unit
26
0,85
V
mA
5,5
0,7
V
mA
V
35
V
mA
10
ISoul =-5mA
+9
+0,3
'l,"' = 10mA
mV'K
mV/K
Hysteresis circuit (pin 6 to pin 7)
Test conditions
Threshold voltage
Switch-OFF voltage
Initial resistance
Input impedance
(cf. block diagram)
1)
12,2
V'h
VOIf
R'N'
Z•.b
Min
8
f~20kHz
100
Typ
12,6
8,4
7,4
Max
13,2
8,8
Unit
V
V
kO
kO
VAe = 1,3, V,m.
Maximum ratings are absolute values and the IC can be damaged by exceeding them.
Functioning of the integrated circuit is not assure under conditions other than those stated
in the electrical characteristics. Operating for long periods of time under maximum rating
conditions can adversely affect the reliability of the integrated circuits.
797
Ringing Detector
PSB 6620
Application examples:
a) Call Signal Indicator
>30Hz
50Hz
Ring
0---i1---....I
2/-1F
Logic
Output
1k
e.g.
~LED
b) Optical Call Signal Indicator
220V
10 },F /35V
Tip
l}'f
+
2k2
O-j I-C::J----,
max.60W
.--'--'--~
220V
360
;
PSB 6620
50Hz
1
L..
Ring
SITAC
e.g. BRT 22H
c) Automatic Telephone Answering System
Hook Switch
/
Tip
O>----...,.l-------~
I
I
I
I
Speech-
I
RingDetector
PSB 6620
Ring
C-
I
I
I
I
I
I
L ~---'-----..,
Control
Ring Detect e.g. SAB 80C482
798
Recorder
Ringing Detector.
PSB 6620
d) Cordless Telephone
r--------
------,
Fixed Station
I
~~P---JL~---~{
I
Ir--_....
I
I
I
RingDetector
PSB 6620
L
Audio
Frequency
Unit
I
I
Radio
Frequency
Unit
I
I
Ring
I
Ri~~~ng
I
Speech
Output
I
Radio
Frequency
Unit
I
I
I
Detect
I
I
l
Ring
- - --1
Mobile Station
I
Hook Switch
I
I
1-- - - -
Microcomputer
Unit
e.g. SAB 8051
I
J
I
I
Microcomputer
Unit
e.g. SAB 80C482
L _ '-_-_-_-_-_-_.....J
e) Bilingual Telephone Interface for Personal Computer
Tip
I
"'0
()
Received
Carrier
(fJ
-<
(fJ
~
m
<::
CD
c
(fJ
Pulse Dial
Ring Detect
I
L ______________ _
799
PSB 6620
Ringing Detector
f) AC . Current Indicator
1OI'F/16V
+
EI30/10
~
~
800
800
Wdg.
2k5
LED
PSB 8590
Dual Tone
Multifrequency Generator
Preliminary data
Features
•
CEPT-compatible
•
•
Direct line feeding
High frequency accuracy (deviation less than 0.4%)
•
Standard low cost clock crystal 4.19 MHz
•
Operation with either single contact or 2 - of - 8 keypads
•
Dual tone as well as single tone capability
•
Multi-key lockout and debouncing
•
•
Binary interface mode
Power dissipation limited by internal thermal overload protection
Pin configuration
16
Vee
15
(
14 Fs
13
F6
12
FJ
11
Fa
10
X2
9
X,
AG 11182
801
Dual Tone Multi Frequency Generator
PSB 8590
General description
The DTMF generator S 359 is a monolithic IC using the I2L technology. It provides
all dual tone multi frequency (DTMF) pairs required in tone dialing systems. The
eight different audio output frequencies are generated from an on-chip reference
oscillator with an external low cost clock crystal 4.19 MHz. The internal temperature
compensated voltage reference determines the audio output levels and it also controls
the on-chip shunt regulator which provides the adaptation to different feeding conditions.
In order to meet the CEPT recommendations an external 2-pole RC filter can easily
be connected.
The S 359 can interface directly to a single contact keypad. Furthermore, open
collector outputs can control the S 359 either in a BCD-mode or in a 2-of-8
keypad mode.
Block diagram
3
F,
4
Fl
FJ 5
6
F4
14
F5
13
F6
12
F7
11
FB
u
t:n
.2
"E
MQ
t:l
0
.0
>w
"'"
BJ
Bo
802
Dual Tone Multi Frequency Generator
PSB 8590
Connection to line
Hook
switch
~
Dial switch
:
R
Polarity guard
overvoltage protection
i >------..+---(=1------;«.
Ti p o--~It----
I
I
I
I
S 359
I
I
Bell
I
I
I
Ri ng
o--------<>------ 50 kO
Contact resistance RE ~ 1 kO for 1= 100
~A
803
Dual Tone Multi Frequency Generator
PSB 8590
Functional description
1. Line adaption
The DTMF generator has an internal temperature·compensated voltage reference. This reference
voltage controls a shunt regulator which sets the DC voltage Vs = Vcc - VEE to 5 V. The external
filtering capacitor C gives the shunt regulator for frequencies above 300 Hz the behavior of a high
impedance current sink. The shunt regulator includes a start·up circuit for the quick charging of
the filtering capacitor(Fig. 1) The shunt regulator can sink feeding currents up to 120 mA while the
power dissipation is limited by internal thermal overload protection. If the chip temperature exceeds
a preset value ("'" Ti = 150 oC, Pv "" 1 W), the filtering capacitor is discharged, the shunt regulator
is switched of and the voltage Vs rises to the breakdown voltage of the external overvoltage pro·
tection network (Fig. 2).
804
Dual Tone Multi Frequency Generator
PSB 8590
Figure 1
Tuning diagram'of the quick charging circuit tOC) for the filter capacitor
-
Is
Vee
8590
1Vs
12V
5
VE'E
5
closed
1Ve
2.2~F
open
"V~
Vs
sv
I
I
I
I
i~
Ve
QC
o.c
QC ott
1.SV
I
on
3
4 ms
-t
The control circuitry for the quick charging circuit has hysteresis with the following
thresholds
OC
on
on
off
x
>9V
< 6.5
<0.7 V
X
V
>0.7 V
805
PSB 8590
Dual Tone Multi Frequency Generator
Figure 2
Output waveforms Vs during thermal limitation (TL) of the power dissipation
-
Is,=30mA
-
i s,=O.5A
r
S
1
8590
Vs
12 v
~ Vc
2.2~F
VEE
open
closed
TL
U
U
U
U
Q(
n
n
n
n
Vc
ov
Vs
5V 12V
~
~15V
I
/"'1
......-1
......-1
......-1
I
"-J
'-J
'-J
'-J
~
The thermal limitation (TL) overrides the quick charger (QC).
2. Tone generation
The on-chip oscillator generates together with the external clock crystal the master
clock frequency fel = 4.194.304 MHz. This master clock fel is scaled by a factor of 16 to
fe2 = 262.144 kHz. The programmable dividers for the higher (f5 - fa) and lower (f, - f 4 )
frequency tone groups are driven by the clock f e2 . The programmable dividers generate
the clock for the 6 bit L/R shift register. Each shift register controls one D/A converter
and the polarity of its output waveform. The output sinewave is synthesized as a
stairstep-function with 11 voltage levels. The output waveform has 22 time segments
(Fig. 3). The time segments t, to try ta to t17 and t 19 to t22 are equal. The time
segments t7 and t'8 are equal but slightly different from the others in order to meet
806
Dual Tone Multi Frequency Generator
PSB 8590
the required output frequencies as closely as possible. The output waveforms are
symmetrical; therefore, no even harmonics exist. The stairstep function with 11 voltage
levels is calcu'lated such that, theoretically, the lowest order harmonics are the 21 51
and the 23 rd • Because of the different length of time segments t7 and t'8 and the
tolerances of the D/A converter, lower odd harmonics exist.
Figure 3
Synthesized output waveforms
1.0
0.92
0.76
0.54
0.28
t,
3. Output levels
Each D/A converter generates a five-level stairstep function. The mixer alternately
reverses the polarity of the five-level stairstep function which leads to the symmetrical
11-level stairstep function (Fig. 3). Furthermore, the mixer adds the stairstep function
of the lower and of the higher frequency groups.
The nominal amplitudes of the stairstep function at the mixer output are:
Lower frequency group
Higher frequency group
iML
iMH
= 42.5 fJA
= 53.5 fJA
Figure 4 shows the AC-schematic of the outpLl·t section of the S 359. The feedback
loop of the output amplifier is externally arranged. The resistors Rl to R3 determine
the output level (VOL and VOH ) and the output impedance R o , as shown below.
Ro =
R 1 +r3
Vm . H = i ML • H
( R 3+R 1 )
1+ --R 2 +r,
(R 3+R,)RL
'
r,
•
The ratio of the resistors R3/R2 is restricted to the range RJR2 < 1.2, otherwise the
output amplitudes are clipped. Normally, the resistors R2 and R3 are equal. Fig. 8
shows the sum level Ps and the output impedance Ro as a function of R, and R 2 •
807
I
PSB 8590
Dual Tone Multi Frequency Generator
Figure 4
AC schematic of the output stage
--. ;0.
'z
r,
+ rJ
rJ
= 1.7kll
= 2 kll
= 41.611
Bo.
B1
Mo.
RJ
Rz
iHH
r
r,
R,
rJ
0
VEE
An external RC filter network is necessary in order to meet the CEPT recommendation
concerning distortion and harmonics. The RC filter is easy to implement, because the
pins Mo, BI, Bo of the output amplifier are accessible. The 8590 is shown in Fig. 5
with a one-pole RCfilter for application corresponding to the recommendations of
the DBP and in Fig. 6 with a two-pole RC filter tor CEPT applications. Fig. 7 shows
the output spectrum for the most critical case, the frequency {s.
The nominal output levels P L. H are identical for the arrangement in Fig. 5 and Fig. 6,
they are
PL
= 20
log
PH
= 20
log
VOL
,!2 /1 mW' 6000
V OH
,!2 /1 mW' 6000
= -8.12
dBm
= -6.12
dBm
The sum output level P s is
P s = 10 log (10 PL/10 + 10 PM/10) = -4.0 dBm
and the preemphasis P D is
PD = PH - PL = 2 dB
808
PSB 8590
Dual Tone Multi Frequency Generator
Figure 5
PSB 8590 with a i·pole RC filter
XI
=
PSB 8590
470pF
In order to keep the insertion loss for all the DTMF frequencies less than 0.2 dB the
3 dB cutoff frequency of the filter should be at least 6 kHz.
Figure 6
S 359 with a 2-pole RC filter (Butterworth)
Vee
Mo
R2 56 kll
B]
R~kll
X,
22nF
== ck
T
[3
PSB 8590
X2
Bo
[1
=f
470pF
],R3
56kll
[1 ::;::
(
VEE
[4
The pole is
fp
= 2.7
T
3.3nF
RI 15611
2.2~F
kHz
809
Dual Tone Multi Frequency Generator
PSB 8590
Figure 7
Output spectrum for frequency f8 with a 2-pole Butterworth filter
dBm
o
f,
-20
r----
-
1----.....
-40
,
....
.......
1
-60
,,
.......
,
CEPT - requirements for the harmonics
.............
.....
I
, .......,
.......
....... .......
'
..............
............
-80
I
I I [[I
-100
10
20
II
I
50
kHz
----f
810
Dual Tone Multi Frequency Generator
PSB 8590
Figure 8
Sum output level Ps (-) and output impedance Ro (---) versus resistors RI , R2
n
dBm
-2
r:
4ml
_~I-Tt"
"
....... - "
V:
'I /' /--V--r-...
................
-5
"'-
V
......
,/
--:,
-8
~~
f""
-6
-7
....--- ....------- -- I--
~;
1/ VI
- 9
/
~
-
I
t
RI
sld
Jd-
'R! '6rri'"
---- ----- -- -f= Jt
.,:~---
----
--- - -
'-f-
i;}-J-
1250
1150
RQ
1050
r
950
850
750
650
R2 = R3
550
-R2
4. Interface to keypad
There are three different operation modes of the interface:
a) Single contact or 2-of-8 keypad
b) Electronic interface with a 2-of-8 keypad code
c) Electronic interface with a BCD code
Figure 9 shows the schematic of the interface inputs FI - Fa. The inputs are divided
into two groups FI - F4 and F5 - Fa. In addition, the pin Fa controls the operation modes.
The resistors RF are optimized for the single-contact keypad mode.
a) Interface to single contact or2-of-8 keypads (Fig. 9)
The buttons are debounced and electronically interlocked. If multiple buttons are
pushed, the frequencies of the firstly activated button are generated. The requirements
for the quality of the contacts are
Contact open:
Contact closed:
OFF resistance
ON resistance
ROFF> 50 kO
RON;;:; 1 kO
1= 100 iJA
811
Dual Tone Multi Frequency Generator
PSB 8590
Figure 9
Schematic of keypad interface
--------------l
S 359
i
I
I
I
I
A
B
D
Fe
--------1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
812
Dual Tone Multi Frequency Generator
PSB 8590
b) Electronic interface with a 2-of-8 keypad code
Figure 10
Electronic control using the key code
+5V
1,
F,
12
Fz
13
F3
14
F4
Is
Fs
16
F6
17
F7
la
Fa
The inputs I,
the inputs Is
generation of
Is to Is of the
'"
'"Vl
U"1
to 14 control the frequencies of the lower frequency group " - '4 and
to Is control the frequencies of the higher frequency group. For the
a dual tone, one input of I, to 14 of the lower group and one input of
higher group must have an H-Ievel.
If more than one input of the respective group has an H-Ievel, that is recognized as a
multiple button push the frequencies of the firstly sensed H-Ievels are generated.
Truth table
1
2
3
A
4
5
6
B
7
8
9
C
14
*
0
#
D
Inputs
Is
16
17
Is
Digit
813
I
PSB 8590
Dual Tone Multi Frequency Generator
c) Electronic interface with a binary code
Electronic control using the binary code
+5V
+5V
10kll
G,
F,
Gz
F2
GJ
FJ
G.
F.
VI
Gs
Figure 11a
0-
LI'I
m
Fs
Figure 11b
Application 11a
This application enables both dual and single frequency output.
The mode control input Fa is connected to ground. The dual tone pairs are generated corresponding
to the binary code on the inputs G, to G4 . The enable inputs Gs to G7 have the following function:
G5 enable lower and higher frequency group; G6 enable higher frequency group F5 to Fa;
G7 enable lower frequency group F, to F4
Application 11b
This application is optimized for dual tone output without single tone capability.
G, to G4 inputs for binary code; Gs enable lower and higher frequency group.
L-Ievel enables the frequencies, H-Ievel disables the frequencies. If the fr,equencies are disabled,
the internal clock is inhibited.
Table information is present at inputs G, to G4 in binary code
Digit
G4
G3
G2
G,
814
0
1
2
3
4
5
6
7
8
9
X
#
A
B
C
D
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
PSB 8590
Dual Tone Multi Frequency Generator
Pin description
Pin No.
1
2
3
4
5
Name
Function
Negative line connection
Mixer output
} Keyboard interface
6
7
8
9
10
11
12
13
14
15
16
Input of output amplifier
Output of output amplifier
} Connections for crystal f = 222 Hz
Keyboard interface and mode select
} Keyboard interface
Connection for filtering capacitor for the current sink
Positive line connection
Electrical characteristics
Absolute maximum ratings 1)
Min
Max
Unit
Voltage at any pin
Supply voltage
Storage temperature
Vee- 0 .3V
-0.3
-55
Vee - Vee
14
125
V
°C
Typ.
Max.
Unit
5
1.25
3.5
120
6
1.35
4.5
rnA
V
V
kO
0.15
V
V
V
V
V
V
Vee - Vee
T"tg
Operating characteristics (T.mb = -25°C to 70°C)
Test condition
Supply current
DC output voltage
Internal reference voltage
Input resistors
Input levels:
Logical L
Logical H
Logical L
Logical H
Logical L
BCD mode enable
11
Is
Vs
VR
RF
F1-F4
F1-F4
F5-F7
F5-Fa
Fa
Fa
16rnA. 12V
~
T
Xl
I
F,
Ma
56kQ
BI
S 359
Ba
JS6kll
Fs
VEE
[4
816
(
T
2.21lF
t
56Q
~
1SV<
Hz
Hz
%.
Dual Tone Multi Frequency Generator
PSB 8590
Figure 13
Circuit for measuring set-up time ts
60011
Vee
Ma
Xl
ck
T
51
2:. 12 V
C
;)T
52
[,
I
Vs
15V<
5611
2.2~F
open
I
I
I
I
I
I
52
Vs
'56kl1
Ba
X2
VEE
51
J56kl1
BE
PSB 8590
open
!I
U
I
I
I
iI
I
I
I
ts
-t
I
I
817
PSB 8591
Dual Tone
Multifrequency Generator
Preliminary data
Bipolar circuit
The DTMF generator PSB 8591 is an advanced development of the PSB 8590. The
PSB 8591 has an additional mute output. a chip disable function and a current sink disable
function.
Features
•
CEPT compatible output spectrum and output levels
•
Direct line powered
•
•
•
•
•
Mute output
Chip disable (CD)
Current sink disable (eSD)
MPU interface with data latch on-chip
Operation with either single contact or 2-of-8 keypads
•
2 key rollover with contact debounce
•
Dual-tone and single-tone operation
•
High frequency accuracy (typ. 0.4%)
•
•
Standard low cost clock crystal 4.19 MHz
Power dissipation limited by internal thermal overload protection
•
12L technology
AG 10/84
819
DTMF Generator
PSB 8591
Pin configuration
(top view)
VEE
20
Vee
HO
19
C
Fl
3
18
FS
F2
4
17
F6
F3
5
16
F7
F4
6
15
F8
CD
7
14
VR
CS5
8
13
X2
MiTfE
9
12
Xl
10
11
eo
B[
Pin designation
Pin. No.
Symbol
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Vee
MO
Negative line connection
Mixer output
820
Fl
F2
F3
F4
I
Koyboanf ;n'arta..
CO
Chip disable
CSO
Current sink disable
Mute output (open collector)
Input of output amplifier
MUTE
81
80
Output of output amplifier
Xl
X2
} Connections for crystal f
VR
Voltage reference
F8
F7
F6
F5
Keyboard interface and mode select
C
Vee
= 222 Hz
} Keyboard interface and write enable
Keyboard interface and supply current enable
Connection for filtering capacitor for the current sink
Positive line connection
DTMF Generator
PSB 8591
General description
The DTMF generator PSB 8591 is a monolithic IC using the 12L technology. It provides all
dual-tone multi-frequency (DTMF) pairs required in tone dialing systems. The eight different audio output frequencies are generated from an on-chip reference oscillator with
an external low cost clock crystal (2 22 Hz). The internal temperature compensated
voltage ref.erence determines the audio output levels and controls the on-chip shunt
regulator which provides the adaptation to different feeding conditions.
In order to meet the CEPT recommendations an external 2-pole RC-filter can easily be
connected. Typical telephone application are shown in figure 15. The PSB 8591 can
interface directly to a single contact keypad. Furthermore, the device can be controlled
either from a MPU (binary mode) or via a 2-of-8 keypad. The PSB 8591 works in parallel
to the speech circuit. If no button is pressed, the device consums only a low standby
current. When data is input via keyboard or MPU interface, a low-active mute signal is
generated.
Block diagram
X2
13
PSB 8591
F1 3
F2 4
F3 5
F4 6
FS 18
F6 17
F7 1
F8
5
r-----~BI
MUTE·o-:9_--+___....J
BO
20
821
PSB 8591
DTMF Generator
Connection to the telephone-line
PSB 8591
Single contact keypad interface
F1
F2
F3
F4
....
0LI'I
CD
CD
FB
Vl
Q..
F7
F6
FS
Two key rollover with contact debounce is provided.
Required contact spezifications:
Open contact: Resistance RN >400 kO
Closed contact: Resistance Re :S 1 kO for I = 100 iJA
822
DTMF Generator
PSB 8591
Functional description
1. Line adaptation
The DTMF generator PSB 8591 has an internal temperature-compensated voltage
reference. This reference voltage controls a shunt regulator which sets the DC voltage
Vs = Vee -VEE to 5 V. The external filtering capacitor C gives the shunt regulator for frequencies above 300 Hz the behaviorof a high impedance currentsink. The shunt regulator
includes a start-up circuit forthe quick charging of the filtering capacitor (fig. 1). The shunt
regulator can sink line currents up to 120 mA while the power dissipation is limited by
internal thermal overload protection. If the chip temperature exceeds a preset value
(""7j = 1 50°C. Pv "" 1 WI. the filtering capacitor is discharged. the shunt regulator is
switched off and the voltage Vs rises to the breakdown voltage of the external overvoltage
protection network (fig. 2). If the current sink is disabled (low level at CSD. pin 8) an
external shunt regulator or speech circuit should be used.
823
DTMF Generator
PSB 8591
Figure 1
Tuning diagram of the quick charging circuit (QC) for the filter capacitor. Additional test
cOf1ditions: Pin 7 (CD) open and button pressed.
Vee
Fl -Fa
Keyboard
16V~~
30mA
1
Vl
c
PSB 8591
1Vc =~ 2.2~F
V£E
pressld
Vc
!
\ _ _ sv
V,
:L
I
I
i
ac
ac
I,
30
mAl
1
i
1ST
I
OFF
ac
15V
ON:
/
-_t
The control circuitry for the quick charging circuit has a hysteresis with the following
thresholds:
QC
ON
ON
~.7 V
OFF
0.7 V
824
DTMF Generator
PSB 8591
Figure 2
Output waveforms Vs during thermal limitation (TL) of the power dissipation.
Additional test conditions: Pin 7 (CD) open and button pressed
.
I L1 =30mA
vee
-
I l2 =O.5A
r
J~
l8V
PSB 8591
1Ve
2.21l F
VEE
~
open
TL
U
U
U
U
QC
n
n
n
n
~
A
.........,
.........,
.........,.
~'.5
V,
ov
I
The thermal limitation (TL) overrides the quick charger (OC).
825
DTMF Generator
PSB 8591
2. tone generation
The on-chip oscillator generates together with the external clock crystal the master clock
frequency felK = 4.1 94304 MHz.
Clock felK is scaled by a factor of 16 to felK = 262.144 kHz. The programmable dividers for
the higher (fs-f8l and lower (f1- f4 ) frequency tone groups are driven by the clock f elK • The
programmable dividers generate the clock for the 6-bit L/R shift register. Each shift
register controls one D/A converter and the polarity of its output waveform. The output
sinewave is synthesized as a stairstep function with 11 voltage levels. The output
waveform has 22 time segments (fig. 3). The time segments tl to t 6, t8 to t17 and t 19 to t22
are equal. The time segments t, and t 18 are equal but slightly different from the others in
order to meet the required output frequencies as closely as possible. The output
waveforms are symmetrical; therefore. no even harmonics exist. The stairstep function
with 11 voltage levels is calculated such that. theoretically. the lowest order hatmonics
are the 21 st and 23rd. Because of the different length of time segments t7 and t 18 and the
tolerances of the D/A converter, lower odd harmonics exist.
Figura 3
Synthesized output waveforms
1.0
0.92
0.76
0.54
0.28
826
DTMF Generator
PSB 8591
3. Output levels
Each D/A converter generates a five-level stairstep function. The mixer alternately
reverses the polarity of the five-level stairstep function which leads to the symmetrical
11-level stairstep function (fig. 3). Furthermore. the mixer adds the stairstep function of
the lower and of the higher frequency groups.
The nominal amplitudes of the stairstep function at the mixer output are:
iML = 42.5 IJA
Lower frequency group
Higher frequency group
iMH = 53.5 IJA
Figure 4 shows the AC-schematic of the output section of the PSB 8591. The feedback
loop of the output amplifier is externally arranged. The resistors R, to R3 determine the
output level (VOL and V OH ) and the output impedance Ro. as shown below.
R, (r2 + ;3)
Ro = R, + r3 (1 R
+ R3 + R)
,
2 + r,
~
_.
OL. H -
IML. H X
(R3 + R,) RL x r,
Ro
R, (R 2 + r,)
x Ro + RL
The ratio of the resistors RalR2 is restricted to the range RalR2<1.2. otherwise the output
amplitudes are clipped. Normally. the resistors R2 and R3 are equal. Fig. 8 shows the sum
level P s and the output impedance Ro as a function of R, and R 2 •
827
PSB 8591
DTMF Generator
Figure 4
AC schematic of the output stage
r, = 1.7kQ
rz ·r3 =2kQ
r3
AC 0.31,,1'0--+'=
= '-1.6Q
ill
eo
MO
r,
R,
The internal feedback loop is normally closed (r2. r3. positive input of output amplifier).
If the current sink is disabled. the positiv input of the output amplifier is supported with a
fixed voltage of about 0.3 V. This voltage is derived from the internal reference voltage.
828
PSB 8591
DTMF Generator
An external RC filter network is necessary in order to meet CEPT recommendation
concerning distortion and harmonics. The RC filter is easy to implement, because the pins
MO, BI, BO of the output amplifier are accessible. The PSB 8591 is shown in fig. 5 with an
one-pole RC filter for application corresponding to the recommendations of the DBP and
in fig. 6 with a two-pole RC filter for CEPT applications. Fig. 7 shows the output spectrum
for the most critical case, the frequency fa.
The nominal output levels PL. Hare identical forthe arrangement in fig. 5 and fig. 6, they are
(12
VOL
)
,11 mW x 600 0
=-
12
VOH
)
,11 mW x 600 0
= - 6.12 dBm
PL
= 20 log
PH
= 20 log (
The sum output level Ps is
Ps = 10 log (10 EXP(PJ10)
and the preemphasis Po is
Po
= PH -
PL
+
8.12 dBm
10 EXP(PH/1 0)) = -4 dBm
= 2 dB
Figure 5
PSB 8691 with a 1-pole RC filter
MO
X1
PSB 8591
X2
BO
R
3
470pF
In order to keep the insertion loss for all the DTMF frequencies less than 0.2 dB the 3 dB
cutoff frequency of the filter should be at least 6 kHz.
829
DTMF Generator
PSB 8591
Figure 8
PSB 8591 with a 2-pole RC filter (Butterworth)
Vee
Rz 56kO
.HO
•T
22nF ==C3
-
X1
PSB 8591
X2
+
R4 47kO
BI
Cz
SO
[)~ikO
470pF
c,=: 3.3nF
C
VEE
C4 :;;
The pole is
flf ...
R,
560
i= 2.2J.1F
2.7 kHz
Figur.7
Output spectrum for frequency fa with a 2-pole Butterworth filter
dBm
o
I
I
I
i
-10
-20
-30
-40
-so -
" ~- ---- -~
..........
............
-60
-70
-80
-90
-1000
830
--±-------r-I
I
I
"I
1v\ UJ'.J~dl
I' . r
--~--
CEPT - requirements for the harmonics
"'l" '" "1"1
8
I.
MJ.L I•.. IIIJa I.&.L
16
24
.1
32
I!
I I
l,J
40 kHz
DTMF Generator
PSB 8591
Figure 8
Sum output level Ps (-) and output impedance Ro (---) versus resistors R" R2 •
dBm
-2
~
t-..........
1"- ......
-5
-6
-7
-8
- 9
r-. .........
7
1-.
V
/~
V
b/. ....'....
,/
~F"
~
V V
'/
I
~
-----.........
~,
It:m,...
sld
JL
- Rj
--- -- --rr': ~
---- --- -
r"/ V- ... .,. .... 1-- io'" ~---
V/
-----
.......I-
1150
Ra
1050
t
950
850
56
1---
.,/
Q
1250
750
1t7Q.
650
R2 =R3
550
450
lOS S'2
-R2
Operation modes:
a) Single contact or 2-of-8 keypad interface
b) MPU interface
Figure 9 shows the schematic of the interface inputs Fl to F8. The inputs are divided into
two groups Fl to F4 and F5 to F8. In addition, pin F8 controls the operation modes. The
resistors RF are optimized for the single-contact keypad mode.
a) Interface to single contact or 2-of-8 keypads (fig. 9)
The buttons are debounced and electronically interlocked. If multiple buttons are pushed,
the frequencies of the first activated button are generated. The requirements for the
quality of the contacts are
> 400 kQ
Contact open:
OFF resistance
ROFF
Contact closed:
ON resistance
1 kQ
1= 100 IJA
RON::::;
831
PSB 8591
DTMF Generator
Figure 9
Schematic of keypad interface
---------------,
PSB 8591
I
'ccl
01
I
I
I
F1
-------,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= 25 kO NOM
VR = 1.25 V ±O.1 V
RF
832
I
DTMF Generator
PSB 8591
The mode control input Fa is connected to ground; pin 7 (CD) ist open. Low level at pin a
(CSD) disables the current sink. The dual tone pairs are generated corresponding to the
binary code at the inputs G 1 to G4. as shown in the following table.
Table information is present at inputs G1 to G4 in binary code
Digit
0
1
2
3
4
5
6
7
a
9
G4
G3
G2
G1
H
H
H
H
H
H
H
L
H
H
L
H
H
H
L
L
H
L
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
H
H
H
L
H
H
L
*L
H
L
H
#
A
B
C
D
L
H
L
L
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
b) Figure 10
MPU interface
I. with open collector AND-Gate
II. with Schottky-diodes
G1
56kQ
G2
56kl1
G3
56kl1
F3
G4
56kQ
F4
F1
G3
TTL
logIC
level
GS
F5
G6
F6
4
FB
56kl1
F2
56kl1
F3
56 kl1
F4
G3
5
G4
18 ~
CI)
G5
G6
17 CD
Vl
F7
F1
G2
LIl
G7
56kQ
G1
a.
16
G7
F5
F6
F7
Fe
15
.5V
eso
5
6
18
....
'"co
LIl
17 ~
Q.
16
15
7
(SO
7
4
8
8
833
DTMF Generator
PSB 8591
The enable inputs G5 to G7 have the following functions:
G5
L
L
L
L
G6
G7
L
L
L
H
H
H
L
H
data fetch for fL and f H• output inhibited
single-tone. higher frequency group (fH).-data fetch for fL
single-tone. lower frequency group (fd. data fetch for fH
sending, dual-tone
The application in fig. 10 enables both. dual-and single-tone output.
Timing diagram
Binary data input; single-tone output,
Fa
Datu
connected to ground.
Valid datu
Gl-G4
I
-;
GS
I
Ddtu fetch fH
G6
Write enable fH fo--....I
G7
Write enable fl
I----:-.;;..;...;;.J.~_...:'--_~
MUTE
Single tone
output level
Higher frequency group
lower frequency group
Higher frequency group
-t
Timing diagram
Binary data input; dual-tone output.
Datu
Gl-G4
GS
G6.G7
Write enable
Dual tone
output level
834
Fa
connected to ground
The valid input data is
stored in clock-Ievelcontrolled flipflops
DTMF Generator
PSB 8591
Electrical characteristics
Absolute maximum ratings1)
min.
max.
V
Vee -0.3
Supply Voltage
Vee -Vee
-0.3
see operating
characteristics
22 (2ms)
V
Storage temperature
T. tg
-55
125
°C
Voltage at any pin
Operating characteristics
(Tomb
= -25°C to 70°C)
Test conditions
VL
VL
VL
VL
hK
Standby current 3 )
1St
Line current4 )
h
Supply current 6 )
Current sink voltage drop4)
(average DC value)
Is
VL
Minimal peak line voltage 6 )
Maximal peak line voltage 6 )
VLm ,"
} (see fig. 11)
VLm ••
VReF
RF
Input resistors at pin 3-6.
13-16. Fl-F8 and CSD
min.
typo
= 18 V
Leakage current 2 )
Internal reference voltage5 )
V
100
5V
20
= 18 V
0.6
0.4
5V
16
VL = 5V
16 mA;:;;h;:;;120 mA
max.
4.5
13
120
15
5
6
3
18
IJA
IJA
mA
mA
mA
mA
V
V
V
1.15
1.25
1.35
15
25
35
V
kQ
1) Stresses above those listed under "Absolute maximum ratings" may cause permanent damage to the device. This is
')
3)
.)
.)
')
a stress rating onlv and functional operation ofthe device at these or any other conditions above those indicated in
the operational section of this data sheet is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CD connected to ground, chip disabled
F1-Fe open, CD opent..£!ljp enabled
£!,trrent sink enabled (CSD = high level), button pressed or F5 and Fe connected to ground
CD open, chip enabled
Current sink disabled (CSD = low level), button pressed or F5 and Fe connected to ground
835
DTMF Generator
PSB 8591
Operating characteristics (T. mb
Input levels
Logical L
H
Logical L
H
Logical L. key code
Binary mode enable
Supply current enable
Logical L
Logical H
Mute output levels
Logical L
Logical H
= -25"C to 70"C)
Test conditions
V IL Fl-F4
V IH Fl-F4
V IL'I:m5. F8-F7
V IH 'I:m5. F5-F8
V IL F5. Fa
V ILF8
V ILF5
VIH~
-10 lolA
Input current
IIHm •• = 1 mA
VOLW'TE
IOLm..
VOHW'TE
IIHW'TE
IOHm ..
VOHW'TE
VILl!IJ
Output levels
Low group
High group
Sum level
PL
PH
Ps
Preemphasis
Po
Sum level
(Frequencies disabled)
Output dynamic
impedance
Pso
Roo
ROd
IILm ..
min.
typo
-0.3
0.5
-0.3
1.1
0.5
-0.3
-0.3
-0.3
0.7
0.15
Vee
0.7
VR
0.7
0.1
0.1
0.3
5
= 1 mA
= 1 mA
= 18 V
IL = 16 mA
to 120 mA
fig. 13
IL = 16 mA
to 120 mA
max.
0.5
Vee
100
-5.4
1.8
-8.12
-6.12
-4
-2.8
2.4
2.8
-80
= 120 mA
= 20 mA
CSDlow V L = 5 V
IL
IL
600
660
V
V
V
V
V
V
V
V
V
V
V
nA
dBm
dBm
dBm
dB
dBm
1000 0
1000 0
9
kO
10
20
kO
-7
2
4
(current sink
disabled)
Output dynamic impedance
in Standby mode
Rs,
Timing specification
Tone frequency deviation
Key debounce time
Set-up time (fig. 13)
VL
=5V
Mlf
td
t.
+7
%0
IL
6
7
ms
ms
L
5
ms
10
lois
= 16 mA
to 120 mA
'I = 16 mA
to 120 mA
Width of write pulse
(see page 15)
836
tw
2
DTMF Generator
PSB 8591
Tone frequency deviation (without tolerances of crystal)-
,.
Required frequency
Generated frequency·)
deviation
f2
'4
f3
fe
fe
,.,
fa
Unit
941
1209 1336 1477 1633
697
770
852
Hz
1212.6 1337.5 1472.7 1638.4 Hz
697.2 771.0 851.1 943
1.374 -1.037 2.087 3.829 1.1
-2.898 3.307 %0
2.75
Figure 11
Minimal/maximal peak line voltage
18
I\
!\.
\V
1\ r1\,
J
•
5
4
II'
1/\ /\ /
V
\ I IV
Vlm1n
2
I
o
-f
') The low cost crystal has the following deviations (including aging and temperature range): b.f/f~ 3.5 x 10-3 •
837
DTMF Generator
PSB 8591
Figure 12
Schematic af inputs CD (pin 7) and CSD (pin 8):
,Equivalent of input CSD
Equivalent of input CD
--~----------~--~Vcc
------~--------~--~~c
Reo
}-----+----C::J---+-- CO
J----~>----o
Ia =5\11\ typ
Reo =5kQ NOM,
R,:. 251dl NOM,
Figure 13
Measuring circuit for output sum level Pso. power enabled
600Q
-
Vcc
Xl
~
T
2~ 1ev
I
1'10
X2
PSB 8591
F1
BI
BO
[ 56kQ
~o
[ 56kll
15V< VbQtt < SOV
FS
VEE
C4
838
C
T
[ 5611
2,2\1 F
_.....
0
(SO
DTMF Generator
PSB 8591
Figure 14
Circuitry for measuring set-up time t., buttons pressed or binary mode
600Q
~
j vee
Fl -F8
Keyboard
1'10
Xl
r
PSB 8591
ck
BE
T
BO
X2
h18V
\off
I
56kQ
[ 56kQ
Vl
15V<
c
5rc:
[ 56Q
:iii: 2.21JF
I
op"en
Keyboard
unpressed
pressed
open
52
~
II
I
~--------------------
i
I
I
I
ts
-t
I
I
839
cg~lI
...aco
m,,'P
m::'"
en g en
~
3:
"11
8:::J
G')
CD
::J
CD
CO !:t. III
.... 0
:::J
~
Hook
switch
TIp
0
I
f
""~ !
R,"9~~
....
CD
Q.
....
o
:::J
CD
~
3
"-CD
;r+
..
o
III
en
"oCD
III
::T
:::J
~
.,
~
~
;:;:
::T
::T
-<
C"
.,
ii
....
iil
:::J
~
3
.,
CD
"'0
CJ)
OJ
CD
en
CD
_l
PSB 8591
DTMF Generator
Fig. 15 b
Application example
PSB 8591 connected to a integrated speech circuit
Vee
20
PSB 8591
Electronic
speech
circuit
MUTE 9
1
8
1 leso
1
VEE
Fig.15c
Principle blockdiagram of a key telephone using the CD-function.
In the case of local supply failure the PSB 8591 is activited so·that dialing is still
possible.
+
t-.
Local supply
-
IJ(
1
0
+
Signaling
v
Display
~
-
I
Interlace
Keyboard
(
)-B
A
Tip
r
U
Ring
~
....
+
-
-
~
;;,
Speech
rJ
CO
PSB 8591
circuit
dialer
MUTE
t/
841
PSB 8592
Dual Tone Multi Frequency
Generator
MOS-circuit
Preliminary data
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Advanced CMOS Technology
Last number redial up to 22 digits
Flash generation (register call)
CEPT compatible without external filtering
Standard low cost TV crystal 3,58 MHz
High frequency accuracy (better than 0,4%)
Operation with single contact matrix keyboard, 20 buttons
Multikey lockout and debouncing
Binary data input
Dual tone and single tone output
Defined audio output time and interdigital pause
Programmable access pause
Low operation and standby current
Mute output
Chip enable input
Internal power-on reset
20 Pin OIL package
Pin configuration
top view
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
Pin
Funktion
18
17
16
15
19
20
1
2
3
6
13
10
12
7
9
11
8
5
4
14
x1
x2
x3
x4
y5
y4
y3
y2
y1
Hook-Switch-Chipenable
Flash out
VDD dig
Vss dig
Pause 3,5,00
VDD ana
Vss ana
Freq. out
oz 1
oz 2
Mute out
AG 9/84
843
I
Dual Tone Multi Frequency Generator
PSB 8592
General description
The DTMF Generator PSB 8592 is specifically designed to implement a dual tone telephone dialing
system. The device can interface direclly to a standard pushbutton telephone single-contact
keyboard type x-y matrix code and operates together with an integrated speech circuit. All
necessary dual-tone frequencies are derived from the widely used standard TV crystal (3.58 MHz)
providing very high accuracy and stability. The required sinusoidal waveform for the individual
tones is digitally synthesized on the chip. The waveform so generated has very low total harmonic distortion. The votage reference is on speech circuit and regulates the signal levels of
the dual tones to meet the recommended telephone specifications. The Buffer-Amplifier is also
situated in the speech circuit, which provides the Overvoltage-Protection. Other applications of
the device include radio and mobile telephones, remote control and process control.
Block diagram
Functional description
Internal Logic Description
After detecting a key closure the oscillator will start. When the oscillation is high enough to operate
the first flip-flop the oscillator current will be reduced and the whole logic will be reset. The chip
command starts first the logic-comparator to suppress the switch bouncing. After the protection
time the valid code will be stored in the RAM. First the RAM will be reset, when the valid CodEl
is a new dialed number. Then the code will be read out of the RAM and will program the two
dividers of the sinewave synthesizer. This will be done continuously until the key is released,
or as long as the sending timer (80 ms) works. In the meantime further digits can be stored in
the RAM. After the sending timer has finished or the key contact opens the command starts the
844
Dual Tone Multi Frequency Generator
PSB 8592
pausetimer (80 ms), the same counter is used in both cases. At this point the command reads
the next digit from the RAM or finishes the function of the device. The command also sets the
MUTE output to high, when it is programming the dividers and sets the MUTE output to low before
finishing the function of the device and will remain low until new sinewaves are generated. If
the detected key closure is the redial function the commmand starts to readout the stored number
from the RAM. If the detected key closure is a single tone mode, the command only programs
the appropriate divider during key depression. The MUTE output has the same function as in
dual-tone-mode without timing.
Mute output:
_________________-----!I
sending DTMF-signals
L.-._ _ __
no key depressed
Tone Generation
When a valid key closure is detected or a digit is still in the RAM marked for access the command programs the high and low group dividers with appropriate divider ratios, so that the output of these dividers cycle at 26 times the desired high group and low group frequencies for
a minimum of 80 ms.
The outputs of the programmable dividers drive two 6 stage uo and down counters with connectsd sign bit. The symmetry pulses of the clock inputs to the two counters divided by 2 with
the sign bit allows 26 equal time segments to be generated within each output cycle.
The 26 segments are used to synthesize digitally a stair-step waveform to approximate the sinewave
function (see Figure) in one D/A converter for the high and low group frequency. To synthesize
the two sinewave functions in one D/A-converter it is necessary that the converter works in under
600 ns because he must be multiplexed between the two functions. This is done by connecting
a weighted capacitor ladder network between the outputs of the counter via sign bit circuit connected to V"' =Vee or Vss and virtual ground. The peak-to-peak amplitude of the stairstep function is weighted by a connected sample and hold capacitor with a different value for the high
and low frequency-group. After the sample and hold capacitor a low passfilter follows, one for
the high and one for the low frequency group. The individual tones generated with different
amplitudes and filtered separately are added linearly and drive an output buffer.
Single Tone Mode
A low group tone can be generated by activating the appropriate row inputs with ground. A high
group tone can be generated by activating the appropriate column inputs with Vee. In this mode
no digit frequency combination will be activated and no digit will be stored in the RAM.
The generation time depends on the duration of the input function. A stored dial-number remains
in the RAM.
Clock Generation
The device contains an oscillator circuit with the necessary paraSitic capacitances on chip so
that it is only necessary to connect the standard 3.58 MHz TV crystal across the OSCI and OSCO
terminals to implement the oscillator function. The oscillator functions whenever a row or column input is activated I,lntil all timing functions are terminated.
845
I
PSB 8592
Dual Tone Multi Frequency Generator
Connection to keyboard
x1
x2
x3
x4
PS B
8592
y5
y4
y3
y2
y1
Keyboard Interface
The device can be connected directly on a X-Y Matrix Key-Board without protection against multi
key function. Internal logic prevents the transmission of illegal tones when more than one key
is pressed. Individual tones can be obtained by connecting a column input to VDD or grounding
a row input. The inputs are static after key recognition, i.e. there is no noise generation as occurs with scanned or dynamic inputs. The interrupt of more than 4 ms on the key-inputs releases
the Key-function in the recognition-circuit.
After this next digit will be detected.
846
PSB 8592
Dual Tone Multi Frequency Generator
Synthesized output waveforms
+1
ro-
r--
+0.8
. .,o
.~
r0-
0
.
.,
0
~"1
--'
+0.6
.
0
+0.4
+0.2
o
"'
ro-
0
[
r'l
-0.2
L~.
0
L.
-0.4
0
··
.
Aktiv
Input
X1
X2
X3
X4
Y1
Y2
Y3
Y4
0
...1
L...
-1
..
~ • .1
0
-0.8
.
• ..1
0
L.
-0.6
.~j
r-.
.....
!-...
•
.... 1. ...
Output Frequency (Hz)
actual
specified
697
770
852
941
1209
1336
1477
1633
695.32731
773.4539
849.84449
942.97813
1207.67375
1336.64862
1480.37428
1638.98581
%
without crystal drift
- 0.241
+ 0.448
- 0.254
+ 0.210
- 0.110
+ 0.049
+ 0.228
+ 0.365
847
Dual Tone Multi Frequency Generator
PSB 8592
Special Functions
Keyboard configuration (maximal)
HiQh
L H~
gro~p freq~encie~
,
"
1209: 1336 : 1477 : 1633 :
Function
o 697
1
2
3
A
R
x1
9 770
4
5
6
B
P
x2
7
8
9
C
G
x3
*
0
#
D
F
x4
y1
y2
y3
y4
y5
w
r
o 852
R = Redial
P = Pause
G = Go for shortening
Pausetime
F = Flash
u
P 941
f
r.
The position of the 4 Special-Keys is in the device mask-programmable.
Redial-Function
If the redial-button is depressed after handset pickup, all stored numbers in the RAM including
Pause- and Flash-function will be sent out. After termination and during Redial-Function it is possible to dial further digits, which will be sent after termination of the Redial-Function. Before starting the redial-function a superversion circuit checks the usefulness of the RAM contents.
Programming of Pause
If the telephonsystem needs pauses for example for trunksearching or dial-tone connection, the
pauses must be stored in the RAM. To store such pauses only depress the Pause-Button, after
this further digits can be dialled. The number of pauses is unlimited. The timing of the pause
is programmable via the Pause-Programming-Pin.
There are 3 choice: Programming-Pin connected for 3 s,
connected to ground 5 s,
open unlimited Pause.
Go-Function
To Go-Button terminates the unlimited pause. Furthermore all timed pause-functions can be terminated earlier. With a transistor connected in parallel to the Go-Button-Switch the pause can
be terminated by operating the transistor with a dial-tone recognition-circuit.
848
Dual Tone Multi Frequency Generator
PSB 8592
Flash-Function
The Flash-Function will be handled like the pause-function, it will be stored in the RAM. The
number of Flashes is unlimited. The Flash-Output goes to Voo for 90 ms and after one Flashfunction is completed the DTMF-Signaling will continue after a pause of 900 ms.
Special-Pulse-Pause-Timing for German-Post-Application in the Redial-Mode
In the Redial-Mode in German-Post-Application the timing must be 80 ms for sending DTMF and
240 ms for pause.
This feature is realized with a lightly modified device. The reason for this is, to keep the sending
levels on carrier-wave-systems in the specified ratio.
BCD-Coding
The device has the possibility to operate with a BCD-Interface. The BCD-Inputs are the column
pins y1 to y5. To program the device for BCD-Code the row inputs x1 and x4 must be grounded
in the same time, when the BCD-Code appears on the column inputs. All digits including pause
and flash are stored in the RAM. The minimum timing will be 5 to 8 ms. A quick timing for BCDCode-Input is possible with Test-Mode-Feature.
Hook-switch/Power-Down
The device is in Power-Down-Mode, when the Hook-Switch-Input is low. In this mode the pull-up
resistances are disconnected on the 4 row-inputs and all inputs a passive. In this case the maximum ratings are valid on the inputs. When the Hook-Switch-Input is high = V DO' the row and
column-inputs are activated and the device can be started via the inputs.
Option: Different exchanges have interruptions in the power feed of the line during trunk-searching
time. Therefore it is difficult to detect the right onhook-switch function; we propose to provide
our line-power-fault detection with the following function. After every interruption of line power
feed, the device starts a timing of 320 ms, during this time the needed power comes from the
buffercapacitor (only DTMF and PAUSE-Function). If the power feed is restored in the meantime, the device will ignore the interruption, after 320 ms, the device will accept the interruption
as a exchange release and the stored digits are prepared for Redial. During the interruption the
device accept dialing but can no send DTMF.
849
I
Dual Tone Multi Frequency Generator
PSB 8592
Electrical Characteristics
Absolute Maximum ratings:
min
DC Supply voltage
VOD -V5S
Input voltage at any pin
max
unit
-0.3
+7
V
-0.3
Voo + 0.5
V
10
mW
Power Dissipation at 25°C
P
Operating Temperature
top
-25
+70
°C
Storage Temperature
t
-55
+125
°C
'"
D.C. Characteristics
Test conditions
min
Supply Voltage = Reference Voltage
One Key selected
Operating current
Tone, Mute output
unloaded
standby current
typ
max
V
2
mA
no key selected
output unloaded
MUTE output resistance
unit
3.5
JlA
4
5
7
Kn
min
typ
max
unit
A.C. Characteristics
Test conditions
Oscillator frequency
850
3.5795
MHz
Dual Tone Multi Frequency Generator
PSB 8592
Key closure recognition with x-y key-board
~~~]Ch
case=K=1e=y=1==O=f=f
~Key~M
5
case 2
Key 1
on
bouncing
ignored
~Ib======ig~n=o_re_d
~
~J
accepted
1M
=K=e~y=7==========================~
Key 5
accepted
ignored
ignored
I
case 3
Key 1
accepted
tp
Key 5
accepted
tp = time protection (4ms)
851
:to
CD
Rl
c:
!:!!.
III
-I
"tJ
n"
=.
0
:::I
CD
><
III
3
"tJ
CD
-{)I-I
~il
Line
hook
switch
•
Flash
::J
3:
c:
a:
..."T1
.0
DTMF
Mute
I
0
(I)
(I)
DTMF-
PSBI6520
C
"2-
circuit
PSB
4510
c:
(I)
::J
(")
'<
G)
(I)
::J
...
s:u
0
...
(I)
"enOJ
co
c.n
CD
N
PSB 7510
LCD Controller
MOS circuit
Advanceinfonnation
The PSB 7510 monolithic integrated circuit controls numeric LC displays in quadruple
multiplex operation.
Due to "MICROPACK" outline (film carrier), the LC display units are extremely thin and
compact.
Features
•
CMOS Si-gate technology
•
Selection of one flag per digit available
•
•
Supply voltage 2.5 V to 6 V
Display. up to 20 digits, 7 segment
•
2 different character sets
(0 - 9, 3 bars, A, U blank or
o - 9, 2 bars, A, b, c, d, blank)
•
64 pin MICROPACK
•
MUX4
•
•
On-chip oscillator
Cursor or blinking selectable
AG 8/84
853
LCD Controller
PSB 7510
Type
Ordering code
Quantity
per order
unit
(items)
Minimum
shipping
quantity
(items)
Series product
film
PSB 7510
Q 671 OO-Z 155-A 101
1500-2500
100
Sample
punched out
PSB 7510
Q 67100-Z 155-A 103
5
5
PSB 7510
Q 671 OO-Z 155-A 102
DIP 64
intermediate
carrier
Maximum
shipping
quantity
(items)
50
5
For prototyping, limited quantities of components can be delivered as punched out MICROPACK, or soldered on a DIP 64 intermediate carrier.
Shipment of the series product will be on metal film rolls (CMOS!). These film rolls are the
property of Siemens and must be returned when empty.
As the individual rolls do not contain a constant number of components, smaller or lager
quantities are possible for partial shipments of large quantities.
Logic symbols
ADO-4 -~--v
~-=---,y' OUTRO-~
WR - - -
;a -----'
ALE - - - RES - - -
PSB 7510
BCE - - -
OUTCO -l9
CRS - - MF - - BIC - - CS - - -
OSC I OSC 2 OSC3
854
LCD Controller
PSB 7510
Pin configuration
top view
Vee
VLCD
DUTRO
OUTR'
OUTRI
DUTR3
DUTCO
DUTe'
OUTCI
OUTCl
OUTe4
OUTCS
DUrc6
OUTC7
OUrci
OU!C9
47
46
4S
4,42
PSB 7510
40
39
38
37
36
35
ADO
(5
DUT(l9
OUTC38
DUTe37
DUT(l6
DUTCl5
DUT(J4
OUTOl
OUTel2
OUTel'
OUTC 30
OUT( 29
OUT(l8
OUTe 27
OUTe26
~=~::!;!~~~~~2~~~;!~
.... I..J ............................... ..., ...........
'-''-''-'v'-'
-I-I--I------
-~~I-~
....
55652555556555555
Pin designation
Pin No.
Symbol
Description
1
2
3
Voo
VLCO
OUTRO
Positive supply voltage
LCD input voltage
6
7
OUTR3
out CO
} Output row drivers
} Output column drivers
46
47
48
OUT C39
CS
ADO
52
53
54
55
56
57
58
59
60
61
62
AD4
RES
WR
WR
ALE
BCE
CRS
Vss
MF
64
OSC3
Chip select
}Binary inputs for address and data
BIC
Reset
Write data latch enable (non inverting)
Write data latch enable (Inverting)
Address latch enable
Blink and cursor enable
Character ROM select
Ground
Selection of multiple flag
Blink or cursor function select
OSC1
} Oscillator inputs
855
LCD Controller
PSB 7510
Figure 1
Block diagram
ALE WRWR
AD
AD
AD
AD
AD
MF
CRS
0
1
2
3
4
BCE
CS
BIC
RES
OSC 1
OSC 2
OSC3
OUTR o .. OUTR 3
OUTC 0 .. OUTe 39
Functional description
(fig. 1 and pin description)
The PSB 7510 controls LCos in a quadruple MUX mode.
The inputs AoO-Ao4 accept the display address and display data in binary code. The display
address is latched with ALE and used to address an internal RAM. The data is then stored
in the internal RAM using WR control signal (fig. 2). The further translation of the display
address and data in the RAM is asynchronous to the external control signals and is
performed internally using an on-chip oscillator.
In each MUX step the character ROM translates the RAM contents and loads the result
into a shift register. At the end of each MUX phase the shift register is latched and used to
control the bidirectional switches for the LCD drive signals. The LCD voltages are generated
from the input voltage VLCD by an integrated resistor network. Polarity as well as magnitude
of the 'actual LCD voltage for the output analog drivers is provided by a low-resistive
switching network.
The IC additionally features underscoring of selected digits by blinking or cursor.
Input BIC selects blinking or cursor and is enabled with blink or cursO! enable BCE.
856
PSB 7510
LCD Controller
Logic type
Positive logic is used
Voo = "H" high level = logical 1 = positive voltage
Vss = "L" low level = logical 0 = negative voltage
1. Chip select CS
The PSB 7510 responds to external signals only when CS is activated.
2. Reset RES
Reset clears the display and fills the internal RAM with blanks.
3. Address and data input ADO ... AD4
The address pending at ADO .... AD4 is latched with the falling edge of ALE. After this
address assigment, the display data pending at ADO ... AD4 is read into the RAM with the
trailing edge of WR (fig. 2). The inputs use binary code.
Figure 2
[5
ALE
ADO ..
AD4
____F_l_Oa_tl_n_g__
~X~
____
A_dd_re_s_s__
~X~
_____
D_at_a____
~x~
__
Fl_oa_t_'n_g__
4. Multiple flag MF (internal high-ohmic connection with V DD )
When MF - 1, normal data input can be used to set one flag per digit at any desired
position of the display. The character set automatically specified by MF - 1 (set I)
comprises the characters 0 ... 9, 3 bars A, U and a blank. In this case, the character ROM
select CRS input is "don't care".
The selected locations are specified by writing a "1" into the unused fifth data bit for this
character set (set I).
When a character with a flag is changed, the flag must also be rewritten.
857
LCD Controller
PSB 7510
5. Select of character set CRS (internal high-ohmic pullup resistor)
Input CRS is used to select the character set I or II, when MF - 0
Set I: CRS - 0
Set II: CRS-1
6. Blink or cursor function select BIC (internal high-ohmic pull up resistor with Vaa)
The input selects whether a digit is to be highlighted in the display by blinking or by
a cursor.
Blinking: BIC - 1
Cursor: BIC - 0
When using the blink option with characters with a flag, the flag blinks as well. The cursor
option is not available for characters with a flag.
7. Blink or cursor function enable BCE
BCE - 1 enables the blinking or the cursor function (fig. 3). The address of the
character in the display that is to be highlighted is latched with the falling edge of ALE.
ALE must be followed by a WR signal.
Following data information is "don't care".
This function can only be stopped with BCE - O.
Reset RES has no effect.
Characters can only be changed when this function is disabled. After a character
change, the blinking or cursor address must be given again. The blink or cursor function
is available only for one digit at a time.
Figure 3
Blink/cursor functions switched on
CS
BCE
ALE
~-------------------------
,----------
WR
ADO ..
AD4
_____
FI_O_Qt_in_g___JX~
____
A_dd_r_es_s__
_JX
Blink/Cursor _
function
sWitched on
858
LCD Controller
PSB 7510
8. Oscillator inputs OSC 1, OSC 2 and OSC 3
The RC circuitry of t!'lese inputs determines the frequency of the oscillator. With an
oscillator frequency of 25.6 kHz. the refresh rate is 40 Hz. (refer to fig. 4).
Figure 4
RC circuitry of oscillator inputs
Vss
i'
C,
=;=
!
esc
R
esc 2
osc 3
CIT
Suggested
1
L
62
63
PSB 7510
64
R",270kll
values:
C, .C 1 "" 47pF
9. LCD voltage VLCD
This voltage is applied from off-board and is divided by an integrated resistor network
into the optimum interim values.
10. Output drivers
They provide the analog voltages for the LC display
859
PSB 7510
LCD Controller
Display input data
Display
Data
II
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
Address
Address code
I
Set I
Set"
a
a
a
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
bar above
bar center
bar below
A
U
blank
bar above
bar center
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
B
C
0
blank
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
Input of an undefined data word causes a blank to be displayed at the respective display
location.
Figures 5
Uquid crystal matrix organization
yl
xl.
Cam 4
860
y2
yl
y2
xl
x2
x3
x4
yl
y2
F
A
G
B
E
C
0
P
PSB 7510
LCD Controller
Maximum ratings
Ambient temperature under bias
Storage temperature
Supply voltage referred to GND
All input and output voltages
Total power dissipation
Tamb
Tstg
Voo
V
Plot
-25·to 70
-40 to 125
o to 7
-0.3 to Voo+0.3
3
°C
°C
V
V
mW
Typ.
Unit
DC characteristics
Tamb -
25°C, Vss -0 V, Voo - 2.5 V to 6 V
Test conditions
L input voltage
(all inputs, OSC1)
H input voltage
lall inputs, OSC1)
Input leakage current
(all inputs, OSC1)
Operating supply voltage
LCD voltage
Supply current
Min.
Max.
V1L
Vss
0.25
V1H
0.7 X Voo
Voo
Voo V
V
~A
IlL
Voo
VLCO
100
X
Vss ~
Voo Voo 1100 -
2.5
VLCO ~ Voo
Vss
3 V, ext. clock
4 V: ext. clock
6 V: ext. clock
Resistor network for LCD voltage
6
Voo
30
50
100
62
V
V
~A
~
100
~A
kG
1
AC characteristics
Tamb
-25°C to 70°C, Vss-O V, Voo -2.5 V to 6 V
ALE pulse width
Address set-up before ALE
Address hold from ALE
Address latch cycle time
ILL
IAL
lLA
tCYA
Control pulse width WR, Vim
Data set-up before WR, WJ:f
Data hold from WR, WR
Write data cycle time
tee
low
two
tCYW
Oscillator frequency
Clock pulse width
Clock pulse rise time
Clock pulse fall time
tose
tWH
ITLH
tTHL
Voo - 6 V
Vee -6 V
External clock
tose 25 kHz
t osc 25 kHz
100
120
50
1
ns
ns
ns
100
150
50
1
ns
ns
ns
0.1
~s
~s
25
20
100
kHz
~s
5
5
~s
~s
861
LCD Controller
PSB 7510
Wavefonns
L
aCE
CS
r-n''''9j
I
I
tLL ----,
ALE
I
I
I
WR
I
or
II
I
I
WR
I
I.
tAL
I
ADO
to
AD4
OSCl
Tristate
*
tee ----j--:-iI
I
I
I
I
I
I
I
i
I
I
.!tlA·I·
~
I:
.II·
I
I
two:
tow
.!
Data
X
Tristate
-t
jr--------ot y-'~\I.-__
,...1.- - - l i f o
862
Address
~tCYW
----...1.1
-t
Assembly instructions for MICROPACKs
Delivery package
The MICROPACK PSB 7510 is generally delivered on metal film spools in metal cans. For
prototypes, the IC can also be packed individually. MOS handling is necessary.
Substrate connections
For assembly of the MICROPACK, the connection points on the substrate must be coated
with solder. This can be achieved by:
•
•
•
galvanic deposition and melting
screen printing and melting
dip or wave tinning
Solder tin composition: Sn 60 / Pb 40
Thickness of the layer: approx. 15 I-1m (after melting)
Lme Identical to the cllpton
edge of the MICROPACKS
Detllil "A"
.,IMeasure Ilfter etchmg
(Substrate connection I
-'-
7.6,0.1 ---'
' - - - - - 116
_._-.J
DimenSions
In
mm
Note: Necking of the connection leads is not required in the case of galvanically deposited
Sn/Pb and subsequent melting.
863
Assembly recommendations
All assembly recommendations are valid for the following substrate materia1s:
•
•
•
•
epoxy resin
hard-paper
ceramic (thick-thin-film)
flexible materials, as for example polyimide
• glass
I. Prototypes and small quantities
(e.g. up to approx. 1.0/year)
Recommended processing method:
Manual soldering with mini soldering iron
Principle
IC
Solder-coated
substrate lead
\\
Soldering Iron
Film
\\
MICROPACK leads
\
I
I
Required equipment and accessories
• devices for cutting and punching (only when processing from tape)
• forming tools
• temperalure-regulatedminiature soldering iron, certified for the soldering of
MOS components
• stereo microscope (magnification 6 ... 40 x)
• suction tube or tweezers
• hair brush
• sodium-free flux according to DIN 8511 (e.g. pure colophonium dissolved in alcohol)
• cleaning agents (if required): e.g. Freon T-P 35 and TF
• bench top suited for the processing of MOS components
Soldering data
• soldering temperature at the soldering iron tip: 230°C max.
• soldering time: approx. 1 to 2 s
864
Procedure
Caution!
The general rules for the processing of MOS components must be followed
during all operations.
Cut MICROPACK leads free with hand tool (for components delivered on spools only).
Cutting dimensions: 9.2
± 0.05
mm x 11.4
± 0.05 mm
Capton spacer material
c
:@
t
~I
-8-
>-
LrI
N
..;
J
o
I
1-4.23....1
x direction
Caution!
Ii--- 11.4,0.05
I
Only cut free along the dashed lines!
Do not cut the 4 capton spacers.
Form MICROPACK leads with hand tool.
(For the relief of mechanical stress when mounted)
Forming dimensions
Dimensions in mm
865
Punch MICROPACK out of the film tape with hano tool (for components delivered on spools
only)
{~
1
-EO':
I
I
)
I
I
\
Detail "A"
I
I
-1
I
I
-
r---
I
I
I
\
\
\
Punch" A"
0
0
0
0
I
)
0
·~r
<:>
Lay down the punched MICROPACK onto an electrically conductive surface vacuum pickup.
Coat the mounting points on the substrate with flux (with brush by hand).
Position the MICROPACK and adjust by hand under stereo microscope (approx. 5 to 10x
magnification).
Solder the individual leads by hand with soldering iron under stereo microscope
Importantl
First solder two opposite leads. This prevents a shifting of the MICROPACK
during the soldering process.
Cleaning (if required)
Move the substrates one after the other for approx. 1 minute in T-P 35 and TF for example
(no ultrasonic cleaning).
Place the cleaning substrates on an electrically conductive surface or in appropriate trays.
866
II. Medium quantities
(e.g. up to approx. 30.0/year)
Recommended,assembling method:
Pulse soldering with manual device
Principle
Soldering head
(Pulse resistance heating)
S,ld~-,,,t,d r:~l;:;n~
substrate
connect~on
I,'
,,"-'
{
]
/ D..I
Substrate
Required equipment and accessories
As in /., only instead of the soldering iron:
Pulse soldering device
Pulse soldering head (dimensions according to the drawing)
~
I
Soldermg o.rea
i
i i 0.6 ... 0.6
i - - - 6.2'0.05---< -
Dimensions in mm
Head holder
Control device (temperature, time)
Substrate holder (with micro-manipulator, if necessary)
Stereo microscope
Soldering data
Soldering temperature at the pulse soldering head: 230°C max.
Soldering time: approx. 2 s plus an additional holding time of 1 s until the solder becomes
solidified.
867
Procedure
As described in I. including the positioning of the MICRO PACK onto the substrate and the
adjustment.
Further steps
Position the substrate with the positioned MICROPACK onto the substrate holder of the
pulse soldering device.
Lower, adjust and set down the soldering head onto the MICROPACK leads manually, then
trigger the soldering pulse.
After the Pb/Sn solder becomes solidified (holding time, observation through stereo
microscope) raise the soldering head and place the substrate onto an 'electrically conductive
surface or in an appropriate tray.
Cautlonl
Ceramic and glass substrates must be preheated and the stated temperatures
must be maintained during the soldering process.
Ceramic: 150°C
Glass:
125°C
Neither preheating nor cooling may be sudden (danger of breakage).
Cleaning (if required) as in I.
868
III. Large quantities
(e.g. approx. 30.0/year)
Recommended assembling method:
Semi-automatic pulse soldering
Principle
Vacuum pickup tool
!,.
MlCROPACK
/
Soldering head....._ •
I Pulse
---', '';;,
resistance heatmg I \~,"
I /
I/
~~<
r ~'~c~~~~~~~~!!~~~~
u
,
Substrate - I
Substrate holder
Take up
Cut free
Form
I
I
i-- rn rn rn
1
i[O
:
I
,I
Punch out
Film gUide
Rerouting
Supply spool
far MICROPACKS
1
L ___ Pulse solderlAg
869
Required equipment and accessories
Semi-automatic pulse soldering device including tools for cutting. forming and punching.
Stereo microscope (magnification 6 to 40x).
Aux according to DIN 8511 (e.g. pure colophonium dissolved in alcohol).
Cleaning agents (if necessary): Freon T-P 35 and TF.
Soldering data
Soldering temperature at the pulse soldering head 230°C max.
Soldering time: approx. 2 s plus an additional holding time of 1 s until the solder becomes
solidified.
Procedure
Position the supply roll in the pulse soldering device.
Coat the mounting positions on the substrate with flux by hand or machine.
Position the substrate onto the substrate holder.
Cautionl
Ceramic and glass substrates must be preheated and the stated temperatures
must be maintained during the soldering process.
Ceramic:
Glass:
150°C
125 °C
Neither preheating nor cooling may be sudden (danger of breakage).
Machine-cut. form. punch and pre-adjust the MICROPACK.
Rne-adjust with micro-manipulator (under the stereo microscope or on a monitor).
Pulse-solder by machine.
Place the substrate onto an electrically conductive surface or in an appropriate tray.
Cleaning (if required): as in I.
IV. Very large quantities
(e.g. approx. 500.0/year)
Recommended assembling method:
Fully automatic pulse soldering
Processing method as in III. but fully automatic
870
Final inspection
It is recommended that a final visual inspection of the mounted MICROPACKs be included
after soldering or cleaning, respectively (under the stereo microscope, magnification 6 to 40x).
Important criteria
The solder transition between the MICROPACK leads and the substrate traces should be
concave tapered.
The connections to the semiconductor IC must not be damaged.
The solder on all substrate leads must be visibly melted.
MICROPACK and substrate surlace must not show signs of soiling after soldering or cleaning,
respectively.
Replacement
Experience shows that MICROPACKs can be replaced as many as five times depending
on substrate matenal and layer construction.
Desolder the MICROPACK with miniature soldering iron or hot air gun and tweezers. The
leads are heated to the melting point of the Pb/Sn solder and bent up with the tweezers.
Plane the mounting spots and recoat with flux.
Solder in a new MICROPACK using one of the methods described.
Manufacturers of assembly equipment for MICROPACKs
The following companies supply equipment for manual, semi-automatic and fully-automatic
assembling:
1. Weld-Equip Sales b.v.
Engelseweg 217
5705 AE Helmond
Netherlands
Fa. Weld-Equip Deutschland
Josef-Retzer-Str. 47
8000 MOnchen 60
Phone (089) 883601/02
2. Fa. Farco Schweiz
Girardet 29
CH 2400 Le Locle
Phone (0041) 39318954
3. The Jade Cooperation
3063 Philmont Avenue
Huntingdon Vallery, Penna, 19006
USA
Jade Corp. USA, represented by Fa. SF1
Assar-GabrielssonstraBe 1 S
6057 Dietzenbach-Steinberg
Phone (06074) 27051
871
Data Conversion Components
SDA 5200 N
6-Bit Analog Digital Converter
Preliminary data
The SDA 5200 N is an ultrafast AID converter with 6 bit resolution and overflow output.
After cascading, it enables straightforward construction of 7 bit or 8 bit AID converters,
respectively (refer to application circuit).
Apart from a guaranteed strobe frequency of 100 MHz and excellent linearity, the
SDA 5200 N has an outstanding analog bandwidth which - from the analog side - enables
application up to the limit of the Nyquist theorem.
The SDA 5200 N IS pin-compatible to the les SDA 5010, SDA 6020, and SDA 5200 S
(differing output code In the overflowi.
Main features
•
•
•
•
•
•
•
•
•
•
•
•
•
Strobe frequency 100 MHz
6 bit resolution (1.6%)
Overflow output (7th bit) at simultaneous blocking of the remaining outputs
cascading for 7 bit or 8 bit AID converters
Broad analog bandwidth (140 MHz)
High slew rate of the input stages (typ. 0.5 V/ns)
Processing of analog signals up to the Nyquist limit
linearity ± 1/4 lSB
.
No sample and hold required
Dynamic driving of reference inputs for analog addition and multiplication
Power dissipation 550 mW
Eel compatible
logic compatible supply voltage +5 V; -5.2 V
Die 16 package
~
simple
The following versions ' ) are available upon request:
•
•
Ie with a non-linear conversion characteristic of a given characteristic curve
Ie with any output code (e.g. gray code)
·1 Conditions upon request
AG 7/83
875
6 Bit Analog Digital Converter
SDA 5200 N
1 st encoding (AND)
2 nd encodl ng (OR)
I
~+Vs
I
I
I
___________ JI
IL ____ _
15
Signal chart
Do 0 6 05
0 4 03
02
-~
01
H
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
H
H
L
L
L
L
L
L
H
L
L
L
IL
L
L
L
H
L
L
L
L
L
L
L
I--
~
/
I
%
L1"
0
.L
64
876
114 LSB
2
"
62
63
64
SDA 5200 N
6 Bit Analog Digital Converter
Pin configuration (Ceramic 16 pin Dil package)
(top view)
Os~
Do 06
01
0,
OJ
0)
16
15
13
12
11
10
14
0,
[::::::]
1
2
as,
+ VIR
Pin
3
4
6
VIA - VIR
VH Strobe
+Vs
- Vs
Symbol
Function
1
OS,
2
+\ljR
\ljA
-\ljR
\ljH
Strobe
Digital ground 1
Positive reference voltage (+2 V)
Analog signal input (max. +2 V; -3 V)
Negative reference voltage (-3 V)
Hysteresis control (0 V ... +2.5 V)
Strobe input (ECl)
Positive supply voltage (+5 V)
Negative supply voltage (-5.2 V)
Data outputs, bits 1 ... 6 (ECl)
Overflow output
Digital ground 2
------+-
3
4
5
6
7
8
9 ... 14
15
16
-----+-
+Vs
-Vs
0, ... 0 6
Do
0 52
- - - - - - - - - - - -------
I
877
6 Bit Analog Digital Converter
SDA 5200 N
Maximum ratings
Supply voltage
Supply voltage
Input voltages
Strobe
Hysteresis control
Voltage difference
Operating temperature
Storage temperature
+Vs
-Vs
V,A, +V,R, -V'R
Vstrobe
V,H
°S,-OS2
Upper
limit A
-0.3
-6.0
-3.5
6.0
0.3
2.5
-Vs
a
a
3.0
0.5
70
125
-0.5
Tamb
a
T"g
-55
Characteristics
Power supply
Pas supply voltage
Neg. supply voltage
Current consumption
at +Vs ~ +5.0 V. V'A ~ -V'R
at -Vs ~ -5.2 V, V;A;;;; -V'R
Lower
limit B
+Vs
-Vs
Unit
V
V
V
V
V
V
°C
°C
Lower
limit B
typo
Upper
limit A
4.5
-5.7
0.0
-5.2
5.5
-4.7
V
50
55
80
80
mA
mA
+ V;Rm"
V
V
V
V
V
Is+
Is_
Unit
V
Analog part
Signal input
Max. input voltage
V,Am" = I (+V,Rm,,) - (-V;Rm,,) I
\oIA for 6 bit resolution
\oIA for '12 LSB Ii nearity
\oIA for '14 LSB linearity
Input current
at V'A = +\oIR
at V'A < -V'R
Input capacitance
at V'A < -\oIR
Reference inputs
Pos. reference voltage
Neg. reference voltage
Reference resistance
ViAmax
- V;Rmln
5
1.2
2.4
I'A
I'A
0.3
0.6
1.2
150
-500
500
500
pF
25
C'A
~A
nA
128
2
1.5
195
V
V
0
-1.1
-2.0
-0.9
-1.7
6
6
-0.6
-1.6
50
50
V
V
iJ A
iJ A
-1.1
-0.9
-0.7
-2.0
-1.7
-1.5
V
V
+ V'R
-V'R
RRef
-2.5
-3.0
96
Strobe input
H input voltage
L input voltage
H input current
L input current
V,H
\oiL
I'H
I'L
Data outputs (1000 to -2 V)
H output voltage
L output voltage
VQH
VQL
Digital part
878
SDA5200 N
6 Bit Analog Digital Converter
Lower
limit B
Characteristics (conrd)
Dynamic parameters
Aperture time
Aperture jitter
2
25
5
12
12
td
(strobe
Signal transition time
Signal transition time
Strobe frequency
Max. slew rate
Bandwidth (-3 dB)
td Hold
td
Set
'strobe
8
Pulse diagram of strobe input
and data outputs
SlgnQllnpU~
typo
Upper
limit A
Unit
17
17
ns
pS
ns
ns
ns
100
MHz
0.5
140
V/ns
MHz
Input current versus input voltage
max
~~l
I
min +--'f-~-
Data output
I
879
6 Bit Analog Digital Converter
SDA5200 N
Test circuit
470n
l~~
I
Analog
ground
l!---
lOJl..H_
~lOW
Analog
e-
51
52
"VIII'
0,
VIA
*'OOnF
~VIII
VH
0---
<>-F=
-:r.
Strobe
- ·V,
I
0-
--j~-'-"
son
~-
'OOnF
11
.1-
T
-ground
11
Overflow
11
input
lO_~1!
Digital
5011'00'6
~
T
+
".~--~ -11'--
0,
1 "
t--
0,
--<>
D,f---·-
~
~
11
0,
0,
---0
11
9
Q
LSB
,.'00 11
-2V
'OOnF
lines carried out as microstrip
Application circuit
7 bit AID converter with SDA 5200 Sand SDA 5200 N
1
0,
-
0,
SDA
5200S
I---0,1-- VIR
Ft.r-
VR• ,
+ VIR
00
0,
SDA
5200N
~
0,
1
880
SOA 5200 S
6-Bit Analog Digital Converter
Preliminary data
The SDA 5200 S is an ultrafast 6 bit AID converter with overflow output. It has been
designed as terminating device for a 7 bit or 8 bit AID converter comprising several
cascaded les (refer to application circuit), or exclusively for 6 bit operation.
Apart from a guaranteed strobe frequency of 100 MHz and excellent linearity, the
SDA 5200 S has an outstanding analog bandwidth which - from the analog side - enables
application up to the limit of the Nyquist theorem.
The SDA 5200 S is pin-compatible to the les SDA 5010, SDA 6020, and SDA 5200 N
(differing output code in the overflow).
Main features
Strobe frequency 100 MHz
o 6 bit resolution (1.6%)
I:) Overflow output (7th bit)
• Broad analog bandwidth (140 MHz)
Q High slew rate of the input stages (typo 0.5 V/ns)
~ Processing of analog signals up to the Nyquist limit
6) Linearity ± 1/4 lSB
• No sample and hold required
• Dynamic driving of reference inputs for analog addition and multiplication
• Power diSSipation 550 mW
• Eel compatible
• logic compatible supply voltage +5 V; -5.2 V
~ ole 16 package
41)
The following versions'} are available upon request:
• Ie with a non-linear conversion characteristic of a given characteristic curve
ED Ie with any output code (e.g. gray code)
') Conditions upon request
AG 7/83
881
6 Bit Analog Digital Converter
Block diagram
SDA 5200 S
r------------------ -------------------,
3
4'
- V'R
R,
~
Rl
R"
-------- ----=::r-+V'R
I
VH
51
0--'+------1
Comparator
stages
Strobe
Register
I
,I
I
1
I
I
I
I
1 st encoding (AND!
1
1
1
I
I
I
1
I
2 nd encoding lOR)
I
1
- Vs
I
I
1
1
1
I
fa+
<>--'4-----
17
I
IL ____ _
1
1
---------~
15
Signal chart
tl/4
---
Do 0 6 Os O. 03 O2 0,
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
~
X
0
A
A
/
II
.1.
64
882
~SB
f--
2
62
63
64
Vs
6 Bit Analog Digital Converter
SDA 5200 S
Pin configuration (Ceramic 16 pin Dil package)
(top view)
OS2
Do
06
Os
O.
OJ
O2
0,
16
15
14
13
12
11
10
9
4
Pin
1
2
3
4
5
6
7
8
9 ... 14
15
16
8
Symbol
OS1
+VR
V;A
- V;R
V;H
Strobe
+Vs
-Vs
0 , ... 0 6
Do
OS2
Function
Digital ground 1
Positive reference voltage (+2 V)
Analog signal input (max. +2 V; -3 V)
Negative reference voltage (-3 V)
Hysteresis control (0 V ... +2.5 V)
Strobe input (ECl)
Positive supply voltage (+5 V)
Negative supply voltage (-5.2 V)
Data outputs, bits 1 ... 6 (ECl)
Overflow output
Digital ground 2
883
6 Bit Analog Digital Converter
SDA 5200 S
Maximum ratings
Supply voltage
Supply voltage
Input voltages
Strobe
Hysteresis control
Voltage difference
Operating temperature
Storage temperature
+Vs
-Vs
iliA, +IIiR' -IIiR
Vstrobe
V,H
OSI-0 S2
Tamb
Tst9
Characteristics
Power supply
Pos. supply voltage
Neg. supply voltage
Current consumption
at +Vs = +5.0 V, ViA ~ -VIR
at -Vs = -5.2 V, V'A ~ -V'R
+Vs
-Vs
Lower
limit B
Upper
limit A
Unit
-0.3
-6.0
-3.5
-Vs
0
-0.5
0
-55
6.0
0.3
2.5
0
3.0
0.5
70
125
V
V
V
V
V
V
°C
°C
Lower
limit B
typo
Upper
limit A
Unit
4.5
-5.7
5.0
-5.2
5.5
-4.7
V
V
50
55
80
80
mA
mA
+ ViRma.IC
V
V
V
V
V
I S+
15_
Analog part
Signal input
Max. input voltage
V1Ama:-:
IliAm" = I (+V,Rm,,) - (-V,Rm,,) I
iliA for 6 bit resolution
iliA for '/2 LSB linearity
iliA for '14 LSB lir,~arity
Input current
at iliA = +V'R
at V'A < -V'R
Input capacitance
at V'A < -V'R
Reference inputs
Pos. reference voltage
Neg. reference voltage
Reference resistance
- VIRmln
5
1.2
2.4
I'A
I'A
150
-500
Rref
500
500
25
C'A
+ ViR
-V'R
0.3
0.6
1.2
-2.5
-3.0
96
~A
nA
pF
2
1.5
195
V
V
0
-0.9
-1.7
6
6
-0.6
-1.6
50
50
V
V
·-0.9
-1.7
-0.7
-1.5
V
V
I 128
Digital part
Strobe input
H input voltage
L input voltage
H input cu rrent
L input current
IliH
VIL
I'H
III
-1.1
-2.0
Data outputs (100 0 to -2 V)
H output voltage
L output voltage
VOH
VOL
-1.1
-2.0
884
~A
~A
6 Bit Analog Digital Converter
Characteristics (cont'd)
Dynamic parameters
Aperture time
Aperture jitter
SDA 5200 S
Lower
limit B
2
25
5
12
1.2
td
tstrobe
Signal transition time
Signal transition time
Strobe frequency
Max. slew rate
Bandwidth (-3 dB)
Pulse diagram of strobe input
and data outputs
SignQI Input
td
Hold
td Set
'strobe
8
typo
Upper
limit A
Unit
ns
ps
ns
ns
ns
MHz
V/ns
MHz
17
17
100
0.5
140
Input current versus input voltage
mox
II,
I
min t - - - f - - - - t - - - - t ----VIA
885
6 Bit Analog Digital Converter
SDA5200 S
Test circuit
470Q
!I!~
I
Analog
ground
~LOs,~
lOy.!!
+VUI
Digital
0 52 16
• ground
11
Do
Overflow
*100nF
11
Analog
Input
_=F
!~!'.I!
~
VIA
0,
-VIA
0,
VH
0,
Strobe
0,
'V,
0,
-V,
0,
100nF
Il
11
<>-f-=--
...
<>--
Il
11
~j~' -.!!
.-
sOQ
100nF
T
T
11
9
LSB
~
7-100 Q
-2V
-'- 100nF
') Lines carried out as microstrip.
Application circuit
7 bit AID converter with SDA 5200 Sand SDA 5200 N
L Do
- - -_. -
------- - - - - - - - < >
~
SDA
5200S
1----0,
-VIR
,Vr}V
IR
.. - . -
r---'-
.---
~l
r---
RoI
~
Do ' -
0,
0,
0,
SDA
5200N
--<>
-----0
0,
0,
0,
1--'-- -- ---------0 0,
0,1-->---·-···-----. 0,
f---
1
886
Do
._.----
SOA 6020
6-Bit Analog Digital Converter
The SDA 6020 is an ultrafast AID converter with 6 bit resolution. In addition to a
strobe frequency of typically 50 MHz and excellent linearity, the SDA 6020 has the following outstanding features:
• 6-bit resolution (1.6%). simple expansion to 8 bits
• ± 1/4 lSB linearity
•
•
•
•
•
No sample and hold required
Dynamic driving of reference inputs for analog addition and multiplication
ECl compatible (ECl - TTL matching possible, e.g. with SH 100.255)
low power dissipation 450 mW
logic compatible supply voltage +5 V; -5.2 V
Maximum ratings
Supply voltage
Supply voltage
Input voltages
Strobe
Hysteresis control
Voltage difference
Operating temperature
Storage temperature
+Vs
-Vs
VIA, +\.tjR, -VIR
VStrobe
VIH
OA-OD
Tamb
Ts
lower
limit B
Upper
limit A
Unit
-0.3
-6.0
-3.0
-Vs
0
-0.5
0
-55
6.0
0.3
3.0
0
3.0
0.5
70
125
V
V
V
V
V
V
0C
°C
AG 7183
887
SOA 6020
Pin configuration
(top view)
00
16
Do
15
D.
14
0,
13
01.
12
03
11
02
10
0,
9
[1::1]
,
2
0" ~V1R
3
VIA
4
-VIR
5
6
7
8
VH Strobe +Vs -Vs
Pin
Symbol
1
2
OA
+VIR
VIA
-VIR
VIH
Strobe
+Vs
-Vs
3
4
5
6
7
8
9-14
15
16
0,-06
Do
00
I
Function
Anlog ground
Positive reference voltage « +2.5 V)
Analog signal input (max. ±2.5 V)
Negative reference voltage (> -2.5 V)
Hysteresis control (0 V to +2.5 V)
Strobe input (ECl)
Positive supply voltage (+6 V)
Negative supply voltage (-5.2 V)
Data outputs bit 1 to 6 (ECl)
Overflow
Digital ground
(Ceramic 16 pin Oil package)
Block diagram
'VIR
i
r--1---------------------------------'
Overflow
63
r--
Do
i
62
VI
06
CII
VIA
Memory
Qnd
CompQrQtor stQges f---
encoder stages
co
r----
05
2VI
04
~
::J
Co
~
::J
0
!
OJ
01
0,
I
L. __
strobe
888
SOA 6020
Characteristics
---
Power supply
Pos. supply voltage
Neg. supply voltage
Current consumption
at +Vs = +5.0 V; ViA:::; -VIR
at -Vs = -5.2 V; VIA :::; -VIR
+Vs
-Vs
typ.'
Upper
limit A
Unit
4.5
-5.7
5.0
-5.2
5.5
-4.7
V
V
30
55
60
80
mA
mA
+VIR max
5
V
V
V
V
V
800
10
10
flA
flA
flA
Is
Is
Analog part (Tamb=25°C,+Vs=5V,-Vs=-5.2V)
Signal input
Max, input voltage
VIA max
VIA max = I + VIR max --VIR mini
VIA for 6 bit resolution
VrA for 1/2 LSB linearity
VIA for 1/4 LSB linearity
Input current
at VIA = +VIR in sample mode
IIA
at VIA = <-VIR in sample mode
h"
-VIR < VIA < +VIR in hold mode
IIA
Input capacitance
at VIA < -VIR
CIA
Reference inputs
Pos. reference voltage
Neg. reference voltage
Reference resistance
Lower
limit B
+VlR
-VIR
-VIR min
1.2
2.4
0.3
0,6
1.2
200
-10
-10
35
-2
64 R
-2.5
96
VIH
VIL
IrH
IlL
-1.1
-2.0
5
5
VQH
VOl
-1.1
-2.0
pF
V
V
128
2.5
2
256
-0.9
-1.7
30
30
-0.6
-1.5
100
100
V
V
flA
flA
Q
Digital part
Strobe input
H input voltage
L input voltage
H input current
L input current
Data outputs (100 Q to - 2 V)
H output voltage
L output voltage
-0.7
l-o.9[
-1.7 -1.5
V
V
Dynamic parameters
Aperture time
Aperture jitter
Strobe
Signal transition time
Signal transition time
Scanning frequency
td
tStrobe
tTHLQ
tTLHQ
'Strobe
15
50
2
25
8
12
12
20
20
ns
ps
ns
ns
ns
MHz
889
SDA 6020
Pulse diagram of strobe inputs
and data output
Input current versus input voltage
max
IIA
t-------------__ _
'
r :
I
Strobe input
I
Free
min +-.,--(.-----+-------+1-'- VIR
• VIR
--VIA
11 undefined output levels
Test circuit
Digital ground
10<;/
470<;/
;:.,.-..;.. 1 ~H
50<;/
~
•• 100 pF
10~H
U
-~."..-
0-
=f
Analog
input
~
u-
,~J
+ViR
DO
V'A
06
-ViR
05
VH
D.
Strobe
OJ
+Vs
01
100nF=
11
11
11
I
---<>
11
----0
,
1
1=
B -Vs
[ 50<;/
.... -TT
100nF
Groundplane
lILines effected as Microdrip
890
Overflow
11
+100nF
1
100nF
11
1OOnF
0,
11
9
[
JI C
LSB
)7 xl00 II
-2V
SOA 6020
Circuit example for expansion to 7 bit
i
,VIR
Do
06
VIA
6 Bit
AID
Os r----04
03
~
Strobe
-VIR
O2 0,
-
~
'VIR
Do
V'A
6 Bit
AID
06
05
04
OJ
~---
VA
Strobe
Strobe
O2
-\IlR
0,
0
1
-VR
891
SDA 6020
Circuit example for expansion to 8 bit
L~
I
V
-VIR
.-
JR
6 AID
No.1.
[~
31I. VR ~
r-
Strobe
-VIR
V
>- Strobe
-VIR
It.VR ~
V
Strobe
04
OJ
O2f-- f-
0, f--
1
-
Do
06
Os
6A/D
~
Strobe
-VIR
J
~
f---<> De
04
OJ
D2f-- +D,f--
j
1
'VIR
Do
06
6 AID
No.1
Strobe
-VIR
I
892
Os
-VIR
VIA
R
FLJ-
I
No.2
[~
D,~
Do
06
VIA
I-- VIA
R
OJ
D2~
1
6 AID
No.3
~V
04
+VIR
JR
[~
OS
I
t- I-
12VR
Do
06
VIA
Os
04
03
O2
0,
~~
SDA 8005
8-Bit/7 ns Analog Digital Converter
Preliminary data
Bipolar circuit
The SDA 8005 is a high speed DJA converter with excellent dynamic characteristics, it
offers the following features:
•
Settling time typo 7 ns
•
Extremely small glitch area
•
Digital input register
•
Data inputs 10 K and 100 K Eel compatible
•
Single power supply: -5.2 V
•
Deglitch control input
AG 3/85
893
8-Bit /7ns Digital-Analog Converter
SOA 8005
Functional description
The SDA 8005 is a high speed 8 bit D/A converter with Eel compatible data and strobe
inputs.
The data word is received in the input buffer by the low active strobe. An external ref·
erence voltage source with a reference resistor is needed. At a reference current of
2.5 mA the full scale output current amounts to 40 mA.
The output glitches can be minimized by adjusting the deglitch input voltage between
- 2.3 V and - 2.9 V. The deglitch input can also be left open.
Block diagram
+1 -/
I,
DO
Strobe Oeglitch
894
8-Bit / 7ns Digital-Analog Converter
SDA 8005
Pin configuration (Ceramic 16 pin OIL package)
top view
GNO
1
16 OO(LSB)
I ret
2
15 01
Oegl
3
14 02
Str
4
13 03
+1
5
12 04
-I
6
11 05
[
7
10 06
VEE
8
9
07 (MSB)
Pin designation
Pin No.
Symbol
Function
GNO
Ground
2
3
4
5, 6
I ret
Oegl
Str
+1, -I
Reference current input
7
C
Stabilization
8
16 ... 9
VEE
Supply voltage -5.2 V
00 ... 07
Oata input 0 (LSB) to 7 (MSB)
Oeglitch input
Strobe
Complementary current outputs
+1: zero current if 00 to 07 are high
B95
8-Bit /7ns Digital-Analog Converter
SDA 8005
Maximum ratings
Supply voltage
Lower
limit B
Upper
limit A
VEE
-6.0
0.3
V
Input voltages
Voo
-3.0
0
V
Strobe input voltage
-4.0
0
V
-5.2
0
V
Output voltages, +1, -I
VS'c
VOegl
V01 +, V01 _
-1.9
5
V
JUhction temperature
7j
125
°C
Storage temperature
Deglitch input voltage
.07
Tstg
-55
125
°C
Ambient temperature
Tamb
-25
85
°C
Thermal resistance
RthJU
85
K/W
Characteristics
Analog
Lower
limit B
~utputs
typo
Upper
limit A
Static performance
Ratio full scale output current
to reference current
16
Absolute unadjusted error
IOFs/lcef
ERR
+12)
%
Integrale nonlinearity
INL
0.40 1 )
0.55 2 )
LSB
Differential nonlinearity
DNL
0.6 1)
12)
LSB
Full scale temperature coefficient
-25°C to +25°C
+25°C to +85°C
TC
TC
120
80
ppm/oC
ppm/oC
30 3 )
fJA
mA
Zero code output current
-1
80
50
6 1)
Output voltage range
100
10 FS
Vo
Supply voltage sensitivity
Svs
0.03 1 )
tro
ts 0
1.3
ns
7
ns
80
pVs
15 4 )
30 4 )
pVs
pVs
Full scale output current
40 2 )
-1.4
+5
V
0.04 2 )
%/%
Dynamic performance l )
Output rise time
Output settling time
Adjusted worst case glitch area
Digital crosstalk
Data
Strobe
Comments see page 896
896
aData
aStrobe
8-Bit /7ns Digital-Analog Converter
Characteristics
Lower
limit B
Digital inputs
SDA 8005
typo
Upper
limit A
DC characteristics
H input voltage
lliH
-1.105
-0.810
V
L input voltage
lliL
-1.850
-1.505
V
Input capacitance D7
D6
DO to D5
Strobe
H input voltage
D7
D6
DO to D5
Strobe
C I07
C I06
CIOO ... 05
C IStr
I'H 07
IIH 06
IIH 00 ... 05
IIHSlr
Input coding
1.2
0.8
0.5
1.5
pF
pF
pF
pF
25
12
6
75
J-JA
J-JA
J-JA
J-JA
binary
Switching characteristics
Setup time
ts
0.5
ns
Hold time
tH
2.5
ns
Strobe time
(see Fig. 1)
t Slr
2
ns
Deglitch input
Deglitch input current
at VOegl = 2.3 V
at VOegl = 2.9 V
Iloegl
Iloegl
-150
Deglitch voltage range
VOegl
-2.9
Deglitch voltage (not cohnected)
VOegl
200
-2.3
J-JA
J-JA
V
V
0.5XVEE
Power supply1)
Supply voltage
VEE
Supply current
hE
98
mA
Power consumtion
Po
495
mW
-5.46
-4.94
V
897
8-Bit / 7ns Digital-Analog Converter
SDA 8005
Comments
1) Measured at
25°C
VEE =
-5.2 V
Full scale output current 10 = 20 mA
Output loads = 50 Q
2) Quaranteed at -25°C bis +85°C
-5.46 V to -4.94 V
Full scale output current 10 =
3) Measured at
1 mA to 40 mA
100°C
Full scale output current 10 = 20 mA
VOegl = -2.3 V
VEE = -5.2 V
4)
ViH = -0.95 V
ViL= -1.6 V
Input signal rise time tr
=
3 ns
Switching all inputs at the same time in the same direction (worst
case)
The crosstalk can be reduced by using other input signals.
898
8-Bit / 7ns Digital-Analog Converter
SDA 8005
Pulse diagram of the inputs
~.---
____--.,WI___oo-
thald
t"tup min
tstr min
t hold
min
07
= 0.5 ns
2 ns
= 2 ns
=
Figure 1
899
8-Bit / 7ns Digital-Analog Converter
SDA 8005
Terminology
Absolute unadjusted error
The full scale output current with the same reference voltage and reference resistance is
different for different chips. The variation results from the deviation of technology parameters. The specification is the maximum deviation from an average value.
Integral nonlinearity
The integral nonlinearity is the maximum deviation of the output from a linear regression
over the output values of all possible input codes.
Differential nonlinearity
Differential nonlinearity is the difference between the measured change and the ideal
1 LSB change between any two adjacent input codes. A specified differential nonlinearity
of ± 1 LSB max. over the operating temperature range ensures monotonicity.
Supply voltage sensitivity
The supply voltage sensitivity is the dependence of the analog output current on the supply
voltage VEE with all other parameters constant. It is specified in % per %.
Output rise time
The output rise time is the time between the 1 O%value and the 90%valueof Va max. atthe
leading edge.
Output settling time
The output settling time is the time from the trailing strobe edge (50% point) to the time when
the analog output signal is within ± 1/2 LSB of the final value.
The specified value is measured by using a comparator to detect the entry time point
(see fig. 2).
Adjusted worst case glitch area
Glitches which arise from input code switching can be minimized by varying the deglitch
input Voltage.
The specified value can be measured under following conditions:
•
input code change from 0111 1111 to 1000 0000 and viceversa
•
input data are received with strobe
•
deglitch input voltage is optimized for switching in both directions
900
8-Bit /7ns Digital-Analog Converter
SDA 8005
Figure 2 shows the test circuit and the timing diagram for the determination of the output
settling time.
Ultrafast ECl
comparator
~Q_--~...-_Scope
Data input
SOA 8005
00-07
-J
100 n
100 fl
'--.......--{)- 2 V
1.Skfl
non
Variable
r--{=}---1~-{:::Jf---o comparison va ltage
T100nF
__ ______ tl~~
I
11 lSB
_1._______ --
-r---=:tt
d-
n------r
: 1 :
I I I
td comparator
delay time
1.:.'+-+1_ _ _ _ comparator circuit 1
tr.
output
~_ _ _ comparator circuit 2
output
comparator circuit 3
output
Figure 2
901
8-Bit / 7ns Digital-Analog Converter
SDA 8005
Application instructions
- Board with at least one ground area in its entirety
- Ground-pin should be connected nearby the large ground area by using contact studs
or by direct soldering.
- Voltage supply must be blocked directly at the VEE-pin by using a 100 nF ceramic capacitor (preferably use a chip capacitor).
- The analog outputs should be loaded with 50 0 as near as possible at the package.
- The DC voltages (VEE, DEGL, V,ef) have to be checked to ensure low ripple and noise.
- To minimize the crosstalk of Strobe to the output you can place a voltage divider at the
Strobe input to build up an RC filter in combination with the input capacitance
(see figure 4).
- To connect the D/A-converter output to the 50 0 input of the scope, the line has to be terminated on the D/A-converter side to prevent reflections. The ground-connection between
the board and the instrument should have a very low impedance.
The ground-connection between the board and the instrument should have a very low
impedance.
l,Skll
strobe
6,8kQ
-2V
902
8-Bit /7ns Digital-Analog Converter
SDA 8005
Figure 3 shows an application where the output signal is transmitted over a 50 n line to a
receiver with a 50 n input, such as a high speed oscilloscope.
Iref
may be adjusted by varying Vref between 0 V and 2.5 V, when the reference resistor
is 1 kn.
(Rref)
Alternatively, the Rref value can be changed with Vref constant.
Data bus
A
\
/
07
SDA B005
lret
Oegl
3
str
4
+1
5
-I
6
[
VEE
7
8
[[
son
10nF 100nF
-5.2V
-2V
v,'f=0-+2.5V
[a
L....II---'C--------r::::=:J-,--c:J----t----CJ-~-_c:J___t__CJ__r---------~+V'ef
I
I
I
I
I
I
I
I
I
AIN
I
I
I
I
I
I
I
Comparator
Comparator
1- 64
65-128
-j--oVCC
I
Comparator
129 -192
I
~VEE
I
I
I
+1GNO
IClK 1
I
IClK 2
I
I
I
I
I
I
I
I
I
I
I
c..
.
iii"
co
I\)
3
CO
I
txJ
;::;:
l>
::l
Q)
0"
rQ
C
cEo
;::;:
Q)
C')
0
::l
<
m
:::l.
m
...
I
-rVcc,o
I
I
I
I
-t--<' VEE, 0
I
I
I
I
I
I
~GNO
I
I
I
3rd encoding stage
I
I
I
I
I
I
I
I
..
!
Strobe 1
!
Strobe 2
: IhGN01
I
----------------~
L __
DO
01
02
03
04
05
06
07
en
c
»
CO
9
o
8-Bit Analog/Digital Converter
SDA 8010
Pulse diagram
Scanning point
I
909
8-Bit Analog/Digital Converter
SDA 8010
Transfer characteristic and truth table
07 06 05 04 03 02 01
H
H
H
H
H
tJ
Ii
Ii
Ii
.H;
H
H
H
H
H
-
~1/2
DO
H
1-1
H . lj '>c; .
H L H
H
H
~
~~
"'
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
A
1
1--/
A
/
Lr
0
910
LSB
Jl
2
"
253 254 255 256 II; ILSB
8-Bit Analog/Digital Converter
SDA 8010
Maximum ratings
Lower
limit B
Upper
limit A
Vref
-0.3
-6.0
-2.5
6.0
0.3
1.5
Digital input voltages
VStr l' V Str 2
-3.5
Junction temperature
7j
0
125
°C
RthJA
50
K/W
Pos. supply voltages
Vee, Vee.
Neg. supply voltages
VEE, VEE. D
Analog input voltages
+ Vref ,
-
D
V
V
V
VAIN
V
Thermal resistance
Junction-air
(without dissipator)
Characteristics
Current supply
Pos. supply voltage
Neg. supply voltage
Current consumption
at Vee = Vee, D = 5 V
Current consumption
at VEE = VEE, D = 4.5 V
Vee, Vee.
D
VEE, VEE, D
Lower
limit B
typo
Lower
limit A
4.75
-4.75
5
-4.5
180
5.25
-4.25
lee +Iee, Q
lEE
+IEE,
V
mA
mA
90
D
V
Analog part
Reference inputs
Pos. reference voltage
Neg. reference voltage
Reference resistance
+Vref
-Vref
256 R
-1
-2
1
0
V
V
130
0
1
1.5
50
V
V
Large-signal bandwidth 1)
VI
VI
B
Slew rate of input signal
SR
CI
Input current2)
I!
300
30
400
V/I-lS
Input capacity
Signal input
Input voltage range
(peak to peak)
for 8 bit resolution
for 1/2 LSB linearity
MHz
pF
I-lA
Comments see page 911
911
8-Bit Analog/Digital Converter
SDA 8010
Characteristics
Lower
limit B
Digital part
Strobe inputs
H input voltage
VIH
typo
Upper
limit A
..., 1.165
-1.475
V
V
L input voltage
IliL
Max. Strobe frequency3)
f str, max
Strobe time 1
t Str 1
4
ns
Aperture delay4)
t d, ap
3
ns
2
ns
MHz
100
Strobe time 2
t Str 2
Setup time
Strobe 25)
tSetup, Str 2
0
ns
Hold time
Strobe 2 5)
t Hold, Str 2
3
ns
Characteristics
Lower
limit
typo
Upper
limit
Data outputs
-1.025
V
V
H output voltage
VaH
L output voltage
VaL
Signal transition time
td, a
12
ns
Time of valid
output data 6)
tv,
5
ns
912
a
-1.620
8-Bit Analog/Digital Converter
SDA 8010
Comments
1) The large signal bandwidth is measured at a strobe frequency of 100 MHz with a sine-
shaped input signal and with an amplitude of (peak to peak) 2 V in a 50 0 system. The
bandwidth is that input frequency at which either the amplitude value in the output
signal has decreased by 1 dB over the low frequency value, or at which significant errors
occur in the output code. If the voltage drop caused by the input capacitance being
driven with 50 0 is regulated out, or if a lower-ohmic input is used, the input bandwidth
increases further.
2) The input current is linearly dependent on the input voltage. The stated value represents
the input current at VA IN = + Vref •
3) That strobe frequency up to which a sine-shaped input signal with an amplitude of
(peak to peak) 2'11 and a frequency of 50 MHz is reproduced without significant errors in
the output code. The increase in signal-to-noise ratio with increasing analog frequency
as a result of jitter of the sampling point and dynamic distortion is not considered.
4) As the sampling of the analog signal occurs with the edge of signal Str 1, no mention
can be made here of an aperture period, but rather only of a delay (t d , ap) of the sampling
point.
5) This data describes a range for the adjustment of signal Str 2. The most favourable
behavior of the output signals is achieved when the L-phase of signal Str 2 is selected as
short as possible and placed at the end of the H-phase of signal Str 1.
6)
At f Str = 100 MHz, tStr
2
= 2 ns and
tSetup, Str 2
= O.
I
913
8-Bit Analog/Digital Converter
SDA 8010
Test circuit
GNOl
H--+-++-+-+++-.........-OGNOl
GNOI~----~---------+~GNO
=1=[3
[4
==
Vee -------+---.JV"~n~"---~-lVee
.V"f
Str 1?<>+------------.--i Str 1
05 ~----+-_I__I__+__+_--_o05
~_>--.rv-rr-.L'----...___-+---1 +Vref
04 f------~_I__I__+__+_--_o04
'------------------.-.1------+-1 +Vref ,s
03 f---------+-_I__+__+_---o03
rV
==[5
r
A IN -O+'----_+_----..-+--iA IN
02 f-----------+-_+__+_---oO 2
Ana log - Ij 1f--_--..
l--_~...-..F'i-_15_:_0
QI--01
ground
'I
[]
'--'
=r=[6
==[7 '----t--iVref,M
-Vref~_'------'-J"'VYY'~--f----l
~
-V,.f
'------------------------+--l-Vref,s
OO~------------~--_oOO
GNO~--+-[-I1----[.-12--+--L---lGNO
Vee ol--+-_--ro~~"Y'r~'----z_+_
T_+--vee 0
=1=[9
[10==
Str IO+--------.>----+--lL-s_tr_2_ _ _~_EE__lol-~----fY"YY"'-----~-VEE 0
50n~'__[ I_~50- tQ
....
--2V
Cl to C13 100 nF Chip Capacitor
914
loata
AnalO~ig;a~
A
'v
I
II
I
ISOA 8010 ~ata Control
ACQ
Graphic
output
IOEMUX)
»
00
0"
;::;
'C
'C
III
r+
0"
::J
(II
><
III
:!:1V
3
'C
(II
to
»
:::I
III
Q
CO
C
cEo
;::t:
III
100MHz
Clock
(')
o
:::I
<
CD
Processor
System
memory
~
..,CD
en
c
»
00
CD
cJ,
-
9
o
0
Thermospot
system
CD
a,
Pulse generator
Power supply
0
Programmable
voltage sources
3
"C
....c:ell
Temperature
....
Supply and
reference
voltage
II!
c:
"C
"C
Digital
osc illoscope
0
::l.
ell
s
Q.
....ell
II!
....
II!
....c:ell
Analog input
~rv
L--_ _ _ _--',
AID
Digital output signals
signals
"C
/V
CO
,
IXJ
;::;
»
::s
Q)
0
c.c
C
cO'
;::;
Q)
(')
0
::s
<
(1)
~
Logic analyzer
..,(1)
Function
generator
fstrobe
Synthesized
signal generator
r".c=:2$@
Pulse width
control
en
c
Plotter
hp 9845
computer
Floppy disk
»
CO
9
o
Switched Mode Power Supply (SMPS) Components
I
lOA 4600-2/l0A 4600-20
Control Ie for
Switched-Mode Power Supplies
BipolarlC
In addition to their use with TV receivers and video recorders, the ICs TDA 4600-2 and
TDA 4600-2 D can be applied in power supplied of hi-fi sets and active speakers due to
their wide operational ranges and superior voltage stability during high load changes.
Features
• Direct driving of switching transistor
• Low start-up current
• Reversing linear overload characteristic
• Collector current - proportional to base-current input
Maximum ratings
Supply voltage
Voltages
reference output
identification input
controlled amplifier
collector current simulation
blocking input
base current cut-off point
base current amplifier output
Currents
feedback, zero passage
controlled amplifier
collector current simUlation
base current cut-off point
base current amplifier output
Thermal resistances
junction-air
TDA
junction-case
TDA
junction- air
TOA
junction- air
TOA
4600 4600 4600 4600 -
Vg
2
2
20 1)
2 0 2)
Junction temperature
Storage temperature range
20
V
6
V1
V2
V3
V4
V5
V7
Va
3
7
7
Vg
Vg
V
V
V
V
V
V
V
Ii 2
Ii 3
Ii 4
Iq 7
Iq a
-3 to 3
-3 to 3
5
1.5
-1.5
mA
mA
mA
mA
mA
R thJA 1
70
15
60
44
K/W
K/W
K/W
K/W
TJ
Ts,g
125
-55 to 125
°C
°C
R'h JA
R'hJC
R thJA
± 0.6
Operating range
Supply voltage range
Case temperature range
TOA 4600 - 2
Ambient temperature range TOA 4600 - 2 0 3)
Vg
Tease
Tamb
17.8 to 18
o to 85
o to 70
I
~C
°C
1) Package soldered in PCB without cooling area
2) Package soldered in PCB with copper-clad 35 fllayer. cooling area 25 cm 2
3) R'h JA 1 - 44 K/W and P v - 1 W
AG 1/84
919
TDA4600-2
TDA4600-2D
Characteristics
Tamb =25°C,
according to test circuit 1 and diagram min
typ
max
Start operation
Current consumption (Vl not yet switched on)
Vg = 2V
Vg = 5V
Vg =10V
Switching point for V1
Normal operation (Vg
after switch on
Current consumption
=
10 V;
Vcontrol =
Ig
Ig
Ig
Vg
-1 0 V;
11
Vclock =
Vcontrol
Ig
Vcontrol
Ig
V1
V1
TC 1
V2 O)
V3
=-10 V
= 0V
Reference voltage 11 < 0.1 mA
11 = 5 rnA
Temperature coefficient of reference voltage
Feedback voltage
Control voltage
Vcontrol = 0 V
Collector current simulation voltage
Vcontrol = 0 V
Vcontrol = 0 V1-10 V
Blocking input voltage
Output voltage
Vcontrol = 0 V
Vcontrol = 0 V
Vcontrol = 0 V/-l 0 V
Safety operation (Vg = 10 V;
Vcontrol =
Current consumption (VS < 1.8 V)
Switch-off voltage (VS < 1.8 V)
V4 O)
LlV/)
Vs
Vq 7°)
Vq SO)
LlVqsO)
0.5
2.0
1.5
2.4
11.8
1
3 .2
12.3
mA
mA
mA
V
± 0.5 V; f = 20 kHz; duty cycle 1 : 2)
110
55
4.0
4.0
2.3
135
85
4.2
4.2
10-3
0.2
2.6
2.9
mA
mA
V
V
11K
V
V
1.8
0.3
5.5
2.7
2.7
1.4
2.2
0.4
6.3
3.3
3.4
1.8
2.5
0.5
7.0
4.0
4.0
2.2
V
V
V
V
V
V
160
110
4,5
4.4
-10 V; VClock = ± 0.5 V; f = 20 kHz; duty cycle 1 : 2)
Ig
14
22
28
I mA
Ext. blocking input
enable voltage
Vcontrol = 0 V
disable voltage
Vcontrol = 0 V
Supply voltage
for V8 blocked
Vcontrol = 0 V
Supply voltage for V1 off
(while further decreasing Vg)
V4
1.3
1.8
1.5
2.1
1.8
2.5
V
V
Vs
Vs
2.4
2.2
2.7
1.8
V
V
Vg
LlVg
6.7
0.3
7.4
0.6
7.8
1.0
V
V
Ion
350
450
ms
LI V2
100
500
mV
LlV2
500
1000
mV
20
75
10
30
V
kHz
VA
Vq 7
Characteristics
Tamb = 25 DC, according to test circuit 2
Switch-on time (secondary voltages)
Voltage change
S3 = closed (LIN3 = 20 W)
Sound output power
S2 = closed (LlN 2 = 15 W)
Standby operation
(secondary useful load = 3 W)
SI = open
LI V2
f
Nprimary
70
The cooling area should be optimized according to the limit values
0) only de part
920
12
(Tamb ,
T"
R'hJc, R thJA , R thJA ,)
TDA 4600 - 2
TDA 4600 - 2 D
Measurement circuit 1
/r----------------\--------~,
r
TDA 4600 - 2
TOA 4600- 20
I
I
'I
I
/
R,
22kll
Circuit description
During start-up, normal and overload operations the TDA 4600-2; or -2D regulates, controls
and protects the switching transistor installed in the flyback converter power supplies.
I) Start-up operation
The start-up operation is divided into three consecutive phases:
1. An internal reference voltage is built up which supplies the voltage regulator and effects
the charging of the coupling electrolytic capaCitor and the switching transistor. During
these procedures an 19 current less than 3.2 mA will be maintained, if the supply
voltage Vg does not exceed", 12 V.
2. At Vg '" 12 V an internal reference voltage V1 = 4 V is suddenly released to provide
all IC components with the exception of the control logic with a thermally stable and
overload-resistant current.
3. In concurrence with the release of the reference voltage the control logic is activated
by an additional stabilization circuit, and the IC is now ready for operation.
Above sequential start-up phases ensure the charging of the switching transistor by the
coupling electrolytic capacitor and subsequent precision switching.
921
TDA 4600·2
TDA4600·2 D
II) Normal operation
Zero passages of the feedback coil are registered at pin 2 and forwarded to the control
logic.
At pin 3 (input control, overload, and standby recognition) the rectified amplitude variations
of the feedback coil are applied. The regulating (control) amplifier operates with an input
voltage of about 2 V and a current of about 1.4 mA. According to the internal reference
voltage, ttie operating region of the regulating amplifier will be defined by the collector
current simulation pin 4 and the overload recognition. The simulation of the collector current
is generated by an external RC network at pin 4 and an internally set voltage level. By
increasing the capacitance (10 nFl, the collector current of the switching transistor is increased
as well and establishes the desired control range. The control range extends between
a 2 V clamped dc voltage and an ac voltage rising as a sawtooth wave, which may vary
up to a maximum amplitude of 4 V (reference voltage).
By reducing the secondary load to 20 W, the switching frequency increases to about 50 kHz
at an almost constant pulse duty factor (on-time to period approx. 1/3). During additional
secondary load reduction to about 1 W, the switching frequency will change to approx.
70 kHz, while the pulse duty factor falls to approx. 1/11. At the same time, the collector peak
current falls below 1 A.
The output level of the regulating (control) amplifier, the overload recognition, and the
collector current simulation are compared in the trigger and the control logic is instructed
accordingly. Pin 5 will provide additional blocking alternatives, i.e. the output at pin 8 is
blocked at a voltage of equal to or less than 2.2 Vat pin 5.
Based on the start-up circuit, the zero crossing identification, and the trigger-activated
release, the control logic flipflops are set which control both the base current amplification
and shut-down. The base current amplifier forwards the sawtooth voltage V4 to pin 8.
Also, a current feedback with an external resistance of R "" 0.68 Q is inserted between
pin 8 and pin 7. The resistance value determines the maximum amplitude of the base current
for the switch ing transistor.
III) Safety features
The base current shut-down, released by the control logic, clamps the output of pin 7 at
1.6 V and thus blocks the driving of the switching transistor. This preventive method will go
into effect, if the voltage at pin 9 falls below typo 7.4 V or if voltages of less than typo 22 V
are present at pin 5. In case of short-circuited secondary windings in the SMPS, the fault
condition will be continuously monitored by the IC.
With the load completely removed from the secondary winding in the SMPS, the IC is set
at a small pulse duty factor. The total power consumption of the SMPS is kept below n = 6
to 10 W during both operating conditions. After the output has been blocked at a supply
voltage Vg of less than or equal to typo 7.4 V, an additional voltage reduction of .1Vg = 0.6 V
will switch off the reference voltage (4 V).
922
TDA4600-2
TDA4600-2 D
Frequency versus output power
kHz
100
80
r
.'" r\.
~
c:::
60
cr
~
LL
~
40
I'--.
......
r-..... t---...
20
o
o
20
40
r- r--
60
r-- t-
80
Output power
100
120
100
120 W
W
-
Efficiency versus output power
%
100
I
80
.
~
c:::
:~
..... 60
.....
.....
II
I
I
40
20
o
/
1/
...-
7
o
20
40
60
80
Output power
923
TDA4600·2
TDA4600·2 D
Load characteristic
V Output voltage V2 versus output current IQ 2
160
~.
-
-- -- --
-- -- --- --, ~,\",
140
~
,, l7/
/}
1
120
.'"
:S:' 100
80
,
o~ 60
\'tin. 180V--//.
~
"
,
1/
/
/.
I
.E
g
I
,
' / ~"Iin.
250V
V
~ine 220V
/ V/
IA.
40
.,j
~~
20
o
o
100
200
300
400
500
600
700
800 900
1000 1100 1200 mA
Output current 10.2-
Output voltage V2 versus line voltage alterations
V
151
1
150
/
~
QI
./
] 149
....
...."
o"
Co
148
V
V
.E'"
V
",V V
V
../""
V
V
147
150
160
170
180
190
200
210
220
230
Line voltage
924
240
-
250
260 V
TDA4600-2D
Thermal resistance (only applicable to TDA 4600-2 D)
Standardized, ambience-related thermal resistance Rth JA 1 versus lateral length 1of a square
copper-clad cooling area (35 IJ.m copper lamination).
Rth JA
(I = 0) = 60 K/W
Tamb:S;; 70°C
Pv= 1 W
PCB in Ifertical position
circuit in vertical position
static air
1.0,-----.,-------,
R thJA1 (I)
RthJA!I-O)
O,91-----'~----+-----_j
O,81--~'---+-------1
RthJAl
R thJA
=f(1l
0,7 i------r-j--"'oo,;::----i
0,61------+-----"....,
o
100 mm
50
-I
925
TDA4600 -2
TDA4600 - 2 0
Block diagram
+
Start-up
circuit
r1
Control
amplifier
I
Standby
operation
TOA 4600 -2
TOA 4600-20
Ij.~
•
J
~
Vol tage
control
I
•
t
I~ero passage
identification
I--
J
t
3
926
-rJ:"" '"'''"t~
~
amplifier
Coupling - (charging
circuit
I--
j,
~~ -
I
Overload
identification
Reference
vol tage
Trigger
Start
Hold
Control
logic
Collector currentl
simulation
I
I
Base current
shut- down
Ext. blocking
alternatives
f
T
4
5
T
~
7
8
9
TDA 4600-2
TDA4600-2 D
Measurement circuit 2 and application circuit
220 V ac
14.7nFI~-4t~nF
(
r---- - - - - -
-----~
I
~-)
.
~--~--~---+~-~-~~~ ~-~-
I
r
B 2501
C1000
in'o
1N4007
II
I I
Cl.
~
I
I
:
1
g
:;::
BY 258/200
c;
-" .
I
I I
I
I
:
__I
I
I
22nF
79
15
13
11
L. ______ ._. ___ ._._._._. _ _ _ .__ ....!. AZV
.---------.-
2 61' IC
BY 2581
800
270 pF
1) Limits ICmaxof BU 208 if
permissible output
H
power is exceeded
2) Adjustment of secondary
voltage.
470 ~F
l
470~F
18 V
25V
56k12
100 kll
150V
3) Must be discharged
200V
_____ JS1
--~---------------------------------------
before IC change
:
~dS1 ~Sl
r====12~~= -=====47~r;= ===:~
==~
V4
~
331l
V3
~
1.5kll
V,
Vz
927
TDA4600-2
TDA 4600-2 D
Measurement diagram for overload operations
V
VClock
I+0~5
60
70
80
- ____ I
~s
-0,5
-
V4
VR = -10V
---- VR
=0
r
+-----------------------------~s
Va
I
r
--I
8-, _
6
I
I
I
I
4
I
I
2
J
I
I
I
I
I
I
I
I
~--
~----------------------------- ~s
-----I
Pin configuration
Pin No,
(TDA 4600-2: Plastic Power Package - 9 pin SIP package)
(TDA 4600-2D: Plastic 18 pin DIP package)
Function
Vre! output
Zero passage identification
Input regulating amplifier, overload amplifier
Collector current simulation
5
Possible connection for additional protective circuit
6
Ground
7
DC voltage output for charging the coupling capacitor
8
Pulse output - driving the switching transistor
9
Current supply input
only applicable to TDA 4600-2 D
1
2
3
4
10
11
12
13
14
15
16
17
18
928
interconnected (ground)
lOA 4601/TDA 4601 D
Control Ie for
Switched-Mode Power Supplies
Bipolar
Ie
During start-up, normal and overload operations the TDA 4601 or TDA 46010 regulates, controls
and protects the switching transistor installed in the flyback converter power supplies.
It also protects the complete SMPS by preventing an increase in the secondary voltage in
case of errors. In addition to their use with TV receivers and video recorders, these ICs can
be applied in power supplies of hi-fi sets and active speakers due to their wide operatiGnal
ranges and superior voltage stability during high load changes.
Features
• Direct driving of switching transistor
.. Low start-up current
• Reversing linear overload characteristic
lit Col/ector current - proportional to base-current input
• Protective circuit for the event of errors
AG 1/84
929
TDA4601
TDA4601 D
Maximum ratings
Supply voltage
Lower
limit
Upper
limit
Vg
0
20
V
V,
V2
V3
V4
V5
V7
Va
0
-0.6
0
0
0
0
0
6
0.6
V
V
V
V
V
V
V
112
113
114
115
10 7
loa
-3
-3
Voltages
reference output
zero-passage identification
control amplifier
collector-current simulation
blocking input
base-current cut-off point
base-current amplifier output
3
8
8
Vg
Vg
Currents
zero-passage identification
control amplifier
collector-current simulation
blocking input
base-current cut-off point
base-current amplifier output
Thermal resistance
junction-air
TDA 4601
junction-case
TDA 46C1
junction-air
TDA 4601 D')
junction- air
TDA 4601 D2)
Junction temperature
Storage temperature
3
3
0
0
0
-1.5
.5
5
1.5
0
mA
mA
mA
mA
mA
mA
I
R'hJA'
Ti
Tstg
K/W
70
15
60
44
R'hJA
R'h jc
R thJA
-55
1
KlW
K/W
KIW
125
125
°C
°C
Operating range
Supply voltage range
Case temperature range
TDA 4601
Ambient temperature range 3) TDA 4601 D
Vg
Tease
Tamb
1) Package soldered in PCB without cooling area.
2) Package soldered in PCB with copper-clad 35-~m layer, cooling area 25 cm 2
3) Rth JA, - 44 K/W and Pv - 1 W
930
7.8 to 18
o to 85
o to 70
I ~C
°C
TDA4601
TDA4601 D
Characteristics
=25 °c
according to test circuit 1 and diagram
Start operation
Tamb
Current consumption (V1 not yet applied)
Vg = 2V
Vg = 5V
Vg = 10 V
Switching point for V1
Ig
Ig
Ig
Vg
min
typ
max
11.0
1.5
2.4
11.8
0.5
2.0
3.2
12.3
mA
mA
mA
V
Normal operation
(Vg = 10 V; Veontrol
=
-10 V; Veloek = ± 0.5 V; f = 20 kHz; duty cycle 1 : 2) after switch-on
Current consumption
Veontrol = -1 0 V
Vcontrol = 0 V
Reference voltage
<0.1 mA
11 =5 mA
Temperature coefficient
of reference voltage
Control voltage Veontrol = 0 V
Collector-current simulation voltage
11
Veontrol = 0 V
Veontrol = 0 V/-10 V
Blocking voltage
Output voltages
Vcontrol = 0 V
Vcontrol = 0 V
Veontrol = 0 V/-10 V
Feedback voltage
Ig
Ig
110
50
135
75
160
100
mA
mA
V1
V1
4.0
4.0
4.2
4.2
4.5
4.4
V
V
V3
2.3
10-3
2.6
2.9
V
V4 ')
Ll V4 ')
V5
1.8
0.3
6.0
2.2
0.4
7.0
2.5
0.5
8.0
V
V
V
Vq 7')
Vq s')
LlVq s')
V2
2.7
2.7
1.6
3.3
3.4
2.0
0.2
4.0
4.0
2.4
V
V
V
V
TC 1
11K
') only dc part
931
TDA4601
TDA4601 D
Characteristics
Tamb =25°C
I~p
Imin
Imax
Safety operation
(Vg =
I
10 V; Vcontrol = -1 0 V; VCIOCk = ± 0.5 V; f = 20 kHz; duty cycle 1 : 2)
Current consumption (V5 < 1.9 V)
Switch-off voltage (VS < 1.9 V)
Blocking input
19
V4
14
1.3
1.8
Blocking voltage (Vcontrol - 0 V)
Vs
~t
Supply voltage for Va blocked
(Vcontrol = 0 V)
(with further decrease of Vg)
Vg
6.7
~
2
7.4
.dVg
0.3
0.6
Vq7
22
1.5
2.1
-0.1
28
1.8
2.5
mA
V
V
V
7.8
V
V
Characteristics
Tamb = 25 °C acc. to test circuit 2
Turn-on time (secondary voltage)
Voltage change with S 3 = closed
(ilN3 -20 W)
Voltage change with S 2 = closed
(.dN2 -15 W)
Standby operation with S 1 - open
(secondary useful load - 3 W)
..dV2 •
350
100
450
500
ms
mV
.II V2 •
500
1000
mV
.dV2 •
20
30
V
75
10
12
kHz
VA
ton
70
Nprlm.ry
The cooling area should be optimized in consideration of the limit values
(Tca •• ;
932
7j; Rth JC; Rth JA)·
TDA4601
TDA4601 D
Circuit description
During start-up, normal, overload, and disturbed operations the TDA 4601 10 regulates, controls
and protects the switching transistor installed in the flyback converter power supplies.
If an error occurs, the driving of the switching transistor is blocked and the voltage on the
secondary side is prevented from increasing.
I) Start-up operation
The start-up operation is divided into three consecutive phases:
1. An internal reference voltage is built up which supplies the voltage regulator and effects
the charging of the coupling electrolytic capacitor and the switching transistor. During
these procedures an Ig current less than 3.2 mA will be maintained, if the supply
voltage Vg does not exceed '" 12 V.
2. At Vg '" 12 V an internal reference voltage V1 = 4 V is suddenly released to provide
all IC components with the exception of the control logic with a thermally stable and
overload-resistant current.
3. In concurrence with the release of the reference voltage the control logic is activated
by an additional stabilization circuit, and the IC is now ready for operation.
Above sequential start-up phases ensure the charging of the switching transistor t)y the
coupling electrolytic capacitor and subsequent precision switching.
II) Normal operation
Zero passages of the feedback coil are registered at pin 2 and forwarded to the control
logic.
At pin 3 (input control, overload, and standby recognition) the rectified amplitude variations
of the feedback coil are applied. The regulating (control) amplifier operates with an input
voltage of about 2 V and a current of about 1.4 mAo According to the internal reference
voltage, the operating region of the regulating amplifier will be defined by the collector
current simulation pin 4 and the overload recognition. The simulation of the collector current
is gen~rated by an external RC network at pin 4 and an internally set voltage level. By
increasing the capacitance (10 nFl, the collector current of the switching transistor is
increased as well and establishes the desired control range. The control range extends
between a 2 V clamped dc voltage and an ac voltage rising as a sawtooth wave, which may
vary up to a maximum amplitude of 4 V (reference voltage).
By reducing the secondary load to 20 W, the switching frequency increases to about 50 kHz
at an almost constant pulse duty factor (on-time to period approx. 1/3). During additional
secondary load reduction to about 1 W, the switching frequency will change to approx.
70 kHz, while the pulse duty factor falls to approx. 1/11. At the same time, the collector peak
current falls below 1 A.
The output level of the regulating (control) amplifier, the overload recognition, and the
collector current simulation are compared in the trigger and the control logic is instructed
accordingly. Pin 5 will provide additional blocking alternatives, i.e. the output at pin 8 is
blocked at a vciltage of equal to or less than Vref /2 - 0.1 V at pin 5.
933
I
TDA4601
TDA4601 D
Based on the start-up circuit, the zero crossing identification, and the trigger-activated
release, the control logic flipflops are set which control both the base current amplification
and shut-down. The base current amplifier forwards the sawtooth voltage V4 to pin 8.
Also, a current feedback with an external resistance of R '" 0.68 Q is inserted between
pin 8 and pin 7. The resistance value determines the maximum amplitude of the base current
for the switching transistor.
III) Safety features
The base current shut-down, released by the control logic, clamps the output of pin 7 at
1.6 V and thus blocks the driving of the switching transistor. This preventive method will go
into effect, if the voltage at pin 9 falls below typo 6.7 V or if voltages of equal to or less than
Vref/2 - 0.1 V are present at pin 5. In case of short-circuited secondary windings in the
SMPS, the fault condition will be continuously monitored by the IC.
With the load completely removed from the secondary winding in the SMPS, the IC is set
at a small pulse duty factor. The total power consumption of the SMPS is kept below n = 6
to 10 W during both operating conditions. After the output has been blocked at a supply
voltage Vg of less than or equal to typo 6.7 V, an additional voltage reduction of L1 Vg = 0.6 V
will switch of the reference voltage (4 V).
Protective operation for faults with pin 5
For protection against disturbances such as primary undervoltages and/or secondary
overvoltages (e.g. as a result of alterations in the parameters of components of the SMPS),
it is possible to implement applications of the following kind:
•
Protective operation with periodic sampling
In the event of the fault condition, falling below the protective threshold V5 of typically V1/2
causes the output pulses on pin 8 to be inhibited and pin 5 to be clamped internally to
ground across typically 300 Q. The current consumption of the IC reduces (Ig :2: 14 rnA
for Vg = 10 V).
.
With a suitably high-impedance starting resistor') the supply voltage Vg then falls below
the minimal turn-off threshold (5.7 V) for the reference voltage V1. As a result V1 is turned off
and the blocking of pin 5 is cancelled.
Because of the renewed reduction in the current consumption of the IC (Ig S 3.2 rnA for
Vg s 10 V) the supply voltage can again climb to the turn-on threshold Vg :2: 12.3 V.
The protective threshold on pin 5 is released and the switched-mode power supply attempts
to turn on.
If the same fault is still present or another (V5 s V1I2 - 0.1 V), the turn-on will be interrupted
by the above, periodic protective operation, i.e. pin 8 is disabled, pin 5 is blocked, Vg falls
off, etc .
•J 10 kQI3 W in applica1ion circuit 1
934
TDA4601
TDA4601D
•
Protective operation with capture circuit
The starting resistor on pin 9 is chosen sufficiently low-impedance so that in the event of
a fault Vg does not fall below the maximum turn-off threshold (7.5 V) for V1• The blocking
of pin 5 is preserved because V1 will not have been turned off. A one-time fault is thus
captured and turning the SMPS on again is not possible, for example, until the supply voltage
has been manually turned off (power switch).
In the designing of the starting resistor it should be considered that in protective operation
the current consumption reduces to 19 :s; 28 mA for Vg = 10 V.
IV) Turn-on in wide-range power supply (90 to 270 Va c)
(application circuit 2)
Free-running flyback converters used as wide-range power supplies call for a power supply
to the TDA 4601 that is independent of the rectified line voltage, thus the sense of the
winding 11/13 corresponds to the secondary side of the flyback-converter transformer.
Turning on is hampered by the fact that the TDA 4601 must be supplied by the start-up
circuit until the entire load secondary side is charged. This leads to long turn-on times,
especially with a low line voltage.
If the special start-up circuit is used (marked by dashed lines) this time can be shortened.
The unregulated phase of the feedback control winding 15/9 is used as a turn-on aid.
The transistor T1 blocks after turn-on, when the winding 11/13 has taken over the power
supply to the TDA 4601, thus eliminating any effects on the control circuit during operation.
Pin configuration
(TDA 4601: Plastic Power Package - 9 pin SIP package)
(TDA 46010: Plastic 18 pin DIP package)
Pin No.
Function
1
2
Vref output
Zero-passage identification
Input regulating amplifier, overload amplifier
Collector-current simulation
Possible connection for additional protective circuit
Ground (rigidly connected to substrate mounting plate)
DC voltage output for charging the coupling capacitor
Pulse output, driving the switching transistor
Power supply
3
4
5
6
7
8
9
10
} ,oo"''''dto QCO""
18
935
TDA4001
TDA4601D
Block diagram
I
Start- up
circuit
TDA 4601
H
I
t--
(antral
amplifier
~
Standby
operation
I
J
J=J
--l
Vol tage
control
loverload
I
Identification
I
Reference
voltage
j
I
Zero passage
Identl flcatlon
!
~-
I
I
t-J
~
Base current
amplifier
Coupling - ccharging
circuit
I---
I
I
I
Contra I
logic
I
Base current
shut- down t--
Collector currentl
Simulation
Ext. block ing
alternatives
I
!
4
936
Trigger
Start
Hold
r
T
I
8
9
TDA4601
TDA4601D
Test and measurement circuit 1
o
TDA 4601
2.2kQ
1NF--i10~F T10~F
1
I,
\{lock
Q27Q
~ontrol
\19
Test diagram: overload operation
v
Vclock
I+0~5
+---+-....-+---+----+-1----+----+-+-..---__ f
10
20
30
40
60 70
80
-0,5
- VR =-10V
---- VR =0
O+-----------------~s
-f
-f---------------f
~s
937
TDA4601
TDA4601 D
Test and measurement circuit 2
Application circuit 1
i
220Vac
o
B 2501
C1000
TDA 4601
lN4007
BY 258/200
I
I
I
2.2nF
I
__I
79 *
13 *
15
11
L. _ _ .___ .______________________
*
~_
*
270pF
H470
BY 2581
BOO
1) Limits Ie"""of BU 208 if
permissible output
power is exceeded
AZV
2 61- IC
~F
2) Adjustment of secondary
voltage.
3) Must be discharged
before IC change
IBV
2SV
100kn
150V
200V
------------------------------------------
~
SI ~SI====~
o=====JSl
1=====~~Q= -=====~~n=
==,d]
V4
33n
'sN
V)
~
1.5kn
V1
_ _ _ Protective circuit to prevent increase of secondary voltage when fault occurs
938
V,
TDA4601
TDA4601 D
Additions to test circuit 2
kHz Frequency versus output power
100
I
~
c
OJ
"
~
80
60
'\.
~
CT
u..
~
40
.......
.............. .........
20
o
o
20
40
---60
r--
80
Output power
100
120 W
--
Efficiency versus output power
0/0
100
I
80
~
c
OJ
:g
.....
..... 60
LU
40
20
o
I
/
1/
-
/
/
I
o
20
40
60
80
100
120 W
Output powe r
939
TDA4601
TDA4601 D
Additions to test circuit 2
Load characteristic V2 sec versus output current 12 sec
V
160
-. - -- --
140
-- -- -- -
1.
120
,,
~ 100
OJ
C>
E
-0
-.e
>
:::J
VI",
:::J
60
lBOVi/
,.
I
,j
20
o
/~
,
40
....
~,
/2l)
,,
, v/
/ l/
.~~,"
'/
,~
80
0
-
VI",
250V
I
220V
v/
~
o
100
200
300
400
500
600
700
800
so<-
1000 1100
900
Output current 11
1200 rnA
Output voltage V2 sec versus line-voltage alterations
V
151
1,~
::>:
OJ
C\
E
§!
~
.e
./
149
V
V
v
V
V
:::J
o
148
/
V"
. .v
V
170
180
./
147
150
160
190
200
210
220
230
240
Line voltage---
940
250
260 V
TDA4601
TDA4601 D
Application circuit 2
Wide range 90 Vac to 270 Vac
4
90V·270Vac
~f~14.7nF
I
I I '{
1K231 }.
I
I
I
I
I
I
~ I
I
"I
c:
~ I
I
I
2501
(1000
-
I
I
I
I
I
I
I
I
I
I
I
i
o
l
lOA 4601
+
~_U_3
1
l,Skll
7
4
10kll 12kll
1.2 A I
l
1)
68nF
-J
100~~;SV
*
IU
,r
2.7klll
100~F/16 V
r-PLN 32/(9
51472,' B78108
~~2=70:::lkllc:---+_-+---,,-_...iil-----i -K ,
'y
..
~
rl'0kIlZ)
L
~
r'N~007
UI
BY360
I I
I
I
I
I
9
~I
100pF
270kll 6.2kll
lS0kll
,I~
II N22
..
I
I
I
I
3turns
I
~lL==-==-===~\~9~~~~~lsii:ii:~1~3:i:i~~~'~'*"i'*
16
14
Ie
1) Limits m" of BU 208
if permissible output
power is exceeded.
2) Adjustment of secondary
voltage.
3) Must be discharged
before IC change.
2*
12*
BYW29
BYW29
b
I 2.2mFI~
I
2A
2.7kll
TOB
780S
-- Special starting circuit.
V,/S V
V,IB. S V
v,l34.5 V
941
TDA 4ti01
TDA4601 D
Thermal resistance (only applies to TDA 4601 D)
Standardized, ambience-related thermal resistance Rth JA 1 versus lateral length I of a square
copper-clad cooling area (35 IJom copper lamination).
Rth JA (I = 0) = 60 K/W
Tamb ~ 70°C
Pv=1 W
PCB in vertical position
circuit in vertical position
static air
1.0 , - - - - - - - - , - - - - - - - - - ,
RlhJA1(1)
R1hJA(I-O)
0,9 1 - - ' < - - - - - + - - - - _ _ 1
0,8 1------'1.--+----__1
RlhJAl
= t(1)
R 1hJA
o,7 I-------t'-l---""'~--__I
0,61------+----
T
o
100 mm
50
-I
942
TDA 4700/TDA 4700A
Control Ie for Single-Ended
and Push-Pull Switched-Mode
Power Supplies
BipolarlC
This versatile SMPS control IC comprises digital and analog functions which are required
to design high-quality flyback, single-ended and push-pull converters in normal, half-bridge
and full-bridge configurations. The component can also be used in single-ended voltage
multipliers and speed-controlled motors. Malfunctions in electrical operation are recognized
by the integrated operational amplifiers and activate protective functions.
In addition to the noticeable reduction in components, our SMPS ICs offer a number of
advantages:
9 Feed-forward control (line hum suppression) Pin designation
• Symmetry inputs for push-pull converter
Pin No.
Function
o Dynamic output current limitation
1
Os
• Overvoltage protection
2
Reference voltage Vrel
• Undervoltage protection
3
Supply voltage Vs
• Soft start
4
Output Q 2
• Double pulse suppression
5
Output Q 1
6
Symmetry Q 2
Pin configuration,
7
Sync. output
top view
8
Soft start Csoll start
9
VCO RT
10
Capacitance Clilter
24 I SYM 01
Os
11
VCO CT
+ Vref
23 .. IOYN
12
Ramp generator RR
13
Ramp generator C R
22
-IOYN
"lis
14
Comparator input
02
4
21 Iov
15
Operational amplifier output
16
Operational amplifier input (-)
0.1
20 o.OV
17
Operational amplifier input (+)
18
Sync. input .
I SYM 0.2 6
19 ON/OFFlluv
19
ON/OFF, undervoltage
0. SYNC
18 I SYNC
20
Overvoltage output
21
Overvoltage input
17 +1 op amp
[soft start 8
22
Dynamic current limitation (-)
R,
16 -lop amp
23
Dynamic current limitation (+)
24
Symmetry Q 1
10
15 0. op amp
[rtlter
(,
11
14 1 COMP
RR
12
13
(R
(TDA 4700· Ceramic 24 pin DIL package)
(TDA 4700A· Plastic 24 pin DIL package)
AG 1/84
943
I
TOA4700
TOA 4700 A
Circuit description
Voltage controlled oscillator (VCO)
The veo generates a sawtooth voltage. The duration of the falling edge is determined by the
value of CT. The duration of the rising edge of the waveform and, therefore, approximately
the frequency, is determined by the value of RT. By varying the voltage at Cfiller, the oscillator
frequency can be changed by its rated value. During the fall time, the veo provides a trigger
signal for the ramp generator, as well as an L signal for a number of Ie parts to be controlled.
Ramp generator
The ramp generator is triggered by the veo and oscillates at the same frequency. The
duration of the falling edge of the ramp generator waveform is to be shorter than the fall
time of the veo. To control the pulse width at the output, the voltage of the rising edge of
the ramp generator signal is compared with a dc voltage at comparator K2. The slope of the
rising edge of the ramp generator signal is controlled by the current through RR. This offers
the possibility of an additional, superimposed control of the output duty cycle. This additional
control capability, called »feed-forward control«, is utilized to compensate for known
interference such as ripple on the input voltage.
Phase comparator
If the component is operated without external synchronization, the sync input must be
connected to the sync output for the phase comparator to set the rated voltage at Cfilter .
The veo then oscillates with rated frequency. In the case of external synchronization, other
components can be synchronized with the sync output. The component can be frequencysynchronized, but not phase-synchronized, with the sync input. The duty cycle of the
square-wave voltage at the sync input is arbitrary. The best stability as to small phase and
frequency interference deviation is achieved with a duty cycle as offered by the sync output.
Push-pull flipflop
The push-pull flipflop is switched by the falling edge of the veo. This ensures that only
one output of the two push-pull outputs is enabled at a time.
Comparator K 2
The two plus inputs of the comparator are switched such that the lower plus level is always
compared with the level of the minus input. As soon as the voltage of the rising sawtooth
edge exceeds the lower of the two plus levels, both outputs are disabled via the pulse
turn-off flipflop. The period during which the respective, active output is low can be infinitely
varied. As the frequency remains constant, this process corresponds to a change in duty
cycle.
944
TDA4700
TDA 4700 A
Operational amplifier K1
The K1 op amp is a high-quality amplifier. Fluctuations in the output voltage of the power
supply are amplified by K1 and applied to the free + input of comparator K2. Variations in
output voltage are, in this way, converted to a corresponding change in output duty cycle.
K1 has a common-mode input voltage range between 0 V and +5 V.
Pulse tum-off flipflop
The pulse turn-off flipflop enables the outputs at the start of each half cycle. If an error signal
from comparator K 7 or a turn-off signal from K 2 is present, the outputs will immediately
be switched off.
Comparator K3
Comparator K3 limits the voltage at capacitance Csof! start (and also at K2) to a maximum
of + 5 V. The voltage at the ramp generator output may, however, rise to 5.5 V. With a
corresponding slope of the rising ramp generator edge, the duty cycle can be limited to a
desired maximum value.
Comparator K 4
The comparator has its switching threshold at 1.5 V and sets the error flipflop with its output
if the voltage at capacitance Csof! start is below 1.5 V. However, the error flipflop accepts the
set signal only if no reset pulse (error) is applied. In this way the outputs cannot be turned
on again as long as an error signal is present.
Soft start
The lower one of the two voltages at the plus inputs of K2 is a measure for the duty cycle
at the output. At the instant of turning on the component, the voltage at capacitor Csof! start
equals 0 V. As long as no error is present, this capacitor is charged with a current of 6 J.l.A to
the maximum value of 5 V. In case of an error, Csof! start is discharged with a current of 2 f.LA.
A set signal is pending at the error flipflop below a charge of 1.5 V and the outputs are
enabled if no reset signal is pending simultaneously. As the minimum ramp generator voltage,
however, is 1.8 V, the duty cycle at the outputs is actually increased slowly and continuously
not before the voltage at Csof! start exceeds 1.8 V.
Error flipflop
Error signals which are led to input R of the error flipflop cause an immediate disabling of
the outputs, and after the error has been eliminated, the component to switch on again
using the soft start.
Comparator K 5, K 6, K 8, Vref overcurrent load
These are error detectors which cause immediate disabling of the outputs via the error
flipflop when an error occurs. After elimination of the error, the component switches on again
using the soft start. The output of K5 can be fed back to the input. This causes the IC output
stage to remain disabled even after elimination of the overvoltage. However, it requires
high-ohmic overvoltage coupling.
945
TDA4700
TDA 4700 A
Comparator K 7
K 7 serves to recognize overcurreflts. This is the reason why both inputs of the op amp
have been brought out. Turning on is resumed after error recovery at the beginning of the
next half period but without using the soft start.
The K 7 common-mode range covers 0 V to + 4 V. The delay time between occurrence of an
error and disabling of the outputs is only 250 ns.
Symmetry
In push-pull converters, a saturation of the transformer core must be prevented. The degree
of saturation of the transformer can be determined with an external circuit, thus the active
periods of the outputs can be decreased unsymmetrically at the symmetry inputs.
Outputs
Both outputs are transistors with open collectors and operate in a push-pull arrangement.
They are active low. The time in which only one of the two outputs is conductive can be varied
infinitely. The length of the falling edge at VCO is equal to the minimum time during which
both outputs are disabled simultaneously. The minimum L voltage is 0.7 V.
Reference voltage
The reference voltage source is a highly constant source with regard to its temperature
behavoir. It can be utilized in the external wiring of the op amp, the error comparators, the
ramp generator, or other external components.
946
TDA4700
TDA4700A
Maximum ratings
Supply voltage
Voltage at Q1, Q 2
Current at 01,02
Symmetry 1,2
Sync output
Sync input
Input Cfilter
Input RT
Input CT
Input RA
Input C A
Input comparator
K 2, K 5, K 6, K 7
Output K 5
Input op amp
Output op amp
Notes
Vs
Va
10
VSYM
VSYNCO
I syNC a
VSYNC I
VICI
VI AT
VI CT
VIAR
IICA
VIK
VOK5
VI op amp
VQopamp
Reference voltage
Input Csolt start
Vref
Junction temperature
Storage temperature
Tj
Thermal resistance (system-air)
TDA 4700
TDA 4700 A
VI soft start
Tstg
Q1,02high
Q1,021ow
SYNC 0 high
SYNC Q low
Lower
limitB
Upper
limit A
-0.3
-0.3
33
33
70
33
7
10
33
7
7
7
7
10
V
V
mA
V
V
mA
V
V
V
V
V
mA
-03
-0.3
33
33
33
Vs -1
max. I
Vrel
7
V
V
V
V
V
V
V
-55
125
125
°C
°C
65
65
K/W
K/W
-0.3
-0.3
0
-0.3
-0.3
-0.3
-0.3
-03
-10
-0.3
-0.3
-0.3
-03
RthSA
Rth SA
Operating range
Supply voltage
Ambient temperature
TDA 4700
TDA 4700 A
VCO frequency
Ramp generator frequency
Vs
10.5
30
V
Tamb
-25
0
40
40
85
70
250000
250000
°C
°C
Tamb
t
tAG
Hz
Hz
947
TDA4700
TDA4700A
Characteristics
Test
conditions
Lower
limit B
Is
C T = 1 nF,
fveo = 100 kHz
8
Vref
L1Vref
L1Vref
L1Vref
OmAVrRR/rated >V1RR
VI t.#' \./ \V'. L/
T
Voltage at output 1
1
1
I
I
1
I
I
Vol tage at output 2
VQt2V6~====!='! =:!:~lt!===t==~j
iJJ
!~I~!
. =
l--
I
O.5T
V
o
v
t
952
1T
Soft start- error-ON/OFF
1.5T
--f
~ soft start
+VIK2
OJ
g
II ••
.lC.
R.
I
13
r-----
lI\
Cl.l
Co
iii"
.lchII"
IQ
ISYM 0.1 ISYMo.2
24
6
12
iil
3
I
t
I
I
I
I
I
I
I
I
I
I
I
Input
14
comp.
Push-pull FF
8-
a
SSync.pulse
I
LeveL
+
K2
l)
I
I
a
R
Comparator
I
I
I
Rdominant
s
Output
I
I
I
I
a
501 aulput
(active l)
I 0.7 V '" Vl "'lV
I
Pulse turn-off FF
-Input
+Input
40.2oulput
(active
II 07V"'~l"'1V
.
Ramp
vOllage
~ Minimum•
I
I
17
I
I
I
~ V"'
3 +Vs SuppLy
voLtage
.
I
,2
Reference
vOllage
I
I
~10V
V
23
0.33
Soft .Iarl
~
pEt,
-r[
20
21
Overvolloge
J. ' softsturt
19
ON/OFF
undervoltage
22 ____
Dynamic
currenl
limltalion
.:~o~ercurrenl
-
Load
1:
- - - _____ ...JI
gg
0l=I00l=I0
...,...,
00
00
»
TDA4700
TDA 4700 A
veo frequency versus RT and CT'
Cr = 820pF
Cy1nt
~
- cT =2,2nF
.........
" I"
"t-...
\i'YI I': '-,"
1
~
cr =15nF
" 1'-...
"'-
f'..
"I'-.
"
I"
r-......
"'- 1'-..... r--..
Cr =47nF
"-
"-
'" "
l'-.....
954
TDA4700
TDA4700A
veo temperature response
Vs = 12 V; v = max.
L1 fveo
fK • K
l~]
with Cr as parameter
LK
AL[X]
fok K
!
3 10"
0
3.3nf
1.0nF
0.5nF
-10- 3
0
10
30
20
40
50
60
80
70
90
100 kHz
-{veo
Current consumption versus
rnA temperature
rnA
50
15
Output current versus
output voltage
I
I
I
I
I /
I /
10.110.2
14
13
~
40
12
I
I
'\
~
o
20
I
I
I
I
I
'\
20
~
40
60
-T
--------r
so .(
o
I
I
I
I
I
I
I
I
I
I
I
I
I
I
10
\
-25
/
,~I
30
11
10
I
I,
1
'\.
I
I
o
/
I
I
I
I
I
I
2V
_Va
955
TDA 4714A/TDA 47148
Ie for
Switched-Mode Power Supplies
Bipolar Ie
This versatile, 14-pin SMPS IC comprises digital and analog functions which are required
to design high-quality flyback, single-ended, and push-pull converters in normal, halfbridge and full-bridge configurations. The component can also be used in single-ended
voltage multipliers and speed-controlled motors. Malfunctions in electrical operation are
recognized by the integrated op amps and activate protective functions.
Features
•
•
•
•
•
•
•
•
•
Push-pull outputs (open collector)
Double pulse suppression
Dynamic current limitation
Overvoltage protection
IC undervoltage protection
Reference voltage source (± 2% for TDA 4714 B)
Reference overload protection
Soft start
Feed-forward control
Pin configuration
top view
Pin designation
Pin No.
Veef
14 Os
+Vs 2
13
.IOYN
02
12
-IOYN
01
4
[soft start 5
RT
CT
6
1
2
3
4
11 lov
5
6
10 1 COMP
8
9 CR
RR
7
9
10
11
12
13
14
Function
Reference voltage Vrel
Supply voltage Vs
Output 02
Output 01
Soft start C soft start
VCO RT
VCO CT
Ramp generator RR
Ramp generator CR
Input comparator
Input overvoltage
Dynamic current limitation (-)
Dynamic current limitation (+)
Os
(TDA 4714AJ4714B· Plastic 14 pin DIL package)
AG 1/84
957
TDA4714A
TDA4714 B
Circuit description
The following is a description of the individual functional units and their interaction.
Voltage controlled oscillator (VCO)
The VCO generates a sawtooth voltage. The duration of the falling edge is determined by the
value of CT. The duration of the rising edge of the waveform and, therefore, approximately
the frequency, is determined by the value of RT . During the fall time, the VCO provides a trigger
signal for the ramp generator, as well as an L signal for a number of IC parts to be controlled.
Ramp generator
The ramp generator is triggered by the VCO and oscillates at the same frequency. The
duration of the falling edge of the ramp generator waveform is to be shorter than the fall time
of the VCO. To control the pulse width at the output, the voltage of the rising edge of the
ramp generator signal is compared with a dc voltage at comparator K2. The slope of the
rising edge of the ramp generator signal is controlled by the current through RR' This offers
the possibility of an additional, superimposed control of the output duty cycle. This additional
control capability, called »feed-forward control«, is utilized to compensate for known
interference such as ripple on the input voltage.
Push-pull flipflop
The push-pull flipflop is switched by the falling edge of the VCO. This ensures that only
one output of the two push-pull outputs is enabled at a time.
Comparator K 2
The two plus inputs of the comparator are switched such that the lower plus level is always
compared with the level of the minus input. As soon as the voltage of the rising sawtooth
edge exceeds the lower of the two plus levels, both outputs are disabled via the pulse
turn-off flipflop. The period during which the respective, active output is low can be infinitely
varied. As the frequency remains constant, this process corresponds to a change in duty
cycle.
Pulse turn-off flipflop
The pulse turn-off flipflop enables the outputs at the start of each half cycle. If an error signal
from comparator K 7 or a turn-off signal from K 2 is present, the outputs will immediately be
switched off.
Comparator K3
Comparator K3 limits the voltage at capacitance Csoft start (and also at K2!) to a maximum of
5 V. The voltage at the ramp generator output may, however, rise to 5.5 V. With a corresponding slope of the rising ramp generator edge, the duty cycle can be limited to a desired
maximum value.
Comparator K4
The comparator has its switching threshold at 1.5 V and sets the error flipflop with its output
if the voltage at capacitance Csoft start is below 1.5 V. However, the error flipflop accepts the
set signal only if no reset pulse (error) is applied. In this way, the outputs cannot be turned
on again as long as an error Signal is present.
958
TDA 4714 A
TDA4714 B
Soft start
The lower one of the two voltages at the plus inputs of K2 is a measure for the duty cycle
at the output. At the instant of turning on the component, the voltage at capacitor Csolt start
equals 0 V. As long as no error is present, this capacitor is charged with a current of 6 (.LA
to the maximum value of 5 V. In case of an error, Csoft start is discharged with a current of 2 (.LA.
A set signal is pending at the error flipflop below a charge of 1.5 V and the outputs are
enabled if no reset signal is pending simultaneously. As the minimum ramp generator
voltage, however, is 1.8 V, the duty cycle at the outputs is actually increased slowly and
continuously not before the voltage at Csoft start exceeds 1.8 V.
Error flipflop
Error signals, which are led to input R of the error flipflop cause an immediate disabling of
the outputs, and after the error has been eliminated, the component to switch on again using
the soft start.
Comparator K5, K8, Vrel overcurrent load
These are error detectors which cause immediate disabling of the outputs via the error
flipflop when an error occurs. After elimination of the error, the component switches on
again using the soft start.
Comparator K 7
K 7 serves to recognize overcurrents. This is the reason why both inputs of the op amp
have been brought out. Turning on is resumed after error recovery at the beginning of the
next half period but without using the soft start. K 7 has a common-mode input voltage range
between 0 V and 4 V. The delay time between occurrence of an error and disabling of the
outputs is only 250 ns.
Outputs
Both outputs are transistors with open collectors and operate in a push-pull arrangement.
They are actively low. The time in which only one of the two outputs is conductive can be
varied infinitely. The length of the falling edge at VCO is equal to the minimum time during
which both outputs are disabled simultaneously. The minimum L voltage is 0.7 V.
Reference voltage
The reference voltage source is a highly constant source with regard to its temperature
behavior. It can be utilized in the external wiring of the op amp, the error comparators, the
ramp generator, or other external components.
I
959
TDA4714 A
TDA4714B
Maximum ratings
Lower
limitS
Upper
limit A
-0.3
-0.3
33
33
V
V
70
mA
Supply voltage
Voltage at Q 1. Q 2
Q 1/2 high
Current at Q 1, Q 2
Q 1/2 low
Input RT
Input CT
Input RR
Input CR
Input comparator
K2, K5, K7
Output K5
Reference voltage
Input Csoft start
VIRT
VICT
VI RR
IICR
-0.3
-0.3
-0.3
-10
7
7
7
10
V
V
V
mA
VIK2. 5. 7
VOK5
VOref
VI soft start
-0.3
-0.3
-0.3
-0.3
33
33
Vref
7
V
V
V
V
Junction temperature
Storage temperature
Tj
Tstg
-55
125
125
°C
°C
Thermal resistance (system-air)
RthSA
60
K/W
30
30
70
85
100000
250000
250000
V
V
°C
°C
Vs
Va
Ia
Operating range
Supply voltage TDA 4714 A
TDA4714S
Ambient temperature TDA 4714 A
TDA 4714 S
Frequency range
VCO frequency
Ramp generator frequency
960
Vs
Vs
Tamb
Tamb
f
fvco
fRG
10.5
11
0
-25
40
40
40
Hz
Hz
Hz
TDA 4714 A
TDA 4714 B
Characteristics
Supply voltage
Ambient temperature
Supply current
CT = 1 nF
fvco = 100 kHz
TDA 4714 B
TDA 4714 A
Lower
limitS
Vs
Tamb
Is
10.5
0
8
Vref
2.35
typ
Upper
limit A
Lower
limitS
30
70
16
11
-25
8
2.65
2.45
typ
Upper
limit A
30
85
20
V
°C
mA
2.55
V
Reference
Reference voltage
OmA
selection of CT; selection of CR S CT'
2. Determination of the VCO frequency
--0> selection of RT.
=
2 x output frequency
3. Determination of the rated slope of the rising ramp generator voltage, which the maximum
possible turn-on period per half wave depends on
--0> selection of RR.
4. Duration of the soft start process
--0>
selection of
Csoft start.
I
963
m
+V[RR
to
....
(J)
0"
lc
n
;0;
RR
R
---------
r-I
I
I
I
I
I
I
I
I
Input
comp.
I
Push -pull FF
-------------1
n
I
I
§~
I
10 ~
1+
K2
s
I
I
I
Discharge at Q=L (error)
.--"':-----,
3
I
I
I
Q
Pulse turn-off FF
Error FF
Q2 output
(active Ll
0.7V~Vl~1V
I
I
Rdominant
Minimum level
dominant
iil
I
R
Comparator
iii'
IC
3
I
Q
Ramp
voltage
0.
4
Q1 output
(attive Ll
0.7VSVl~1V
I
(R dominant)
IC undervoltage
.----c:::J
I
I
I
I
~ 2 Supply voltage
1
I
22~F
I
rl
I
I
L _____ _
0.33~~
Soft start
Vref OYercurrent load
TC
11
so f t startOvervoltage
13
I
12 ------------------~
Dynamic current limitation
14 0V
-1-1
~~
0l:I00l:I0
:::i:::i
0l:I00l:I0
m»
TDA4714 A
TDA4714 B
Pulse diagram
V~VoltageatCT
-5~----~------~~------~------~.---
ro
V(T
------
2
---------------------------Voltage at ramp generator
V
~RR
5.5
5
>
~RRJrated
\~~
/
> ~RR
~ soft start
\ / \ / l/
+VIKl
Voltage at output 1
l
I
I
I
Voltage at output 2
l-
I
I
I
--t
v
t
o
2
965
TDA 4714 A
TDA4714 B
veo frequency versus RT and CT
Cr =820pF
r..
Cy1nr
r---C
.......
=2,2nF
I
,I
cr = 4,7nF
'1111
cr =15nF
.........
........
""
'-
,
I"-
,
~~
"'-
~
'-
~
I',
" "-
'-
'""'-"- "-
cr =47nF
~
966
"-
"'-
"
"-
TDA4714A
TDA 4714 B
veo temperature response
Vs =12V;1'=max.
ilfvco
fK X K
rLX1 ]
with CT as parameter
1.i [x]
1 3'10"'
3.lnF
1.0nF
0.5nF
-10"
'--_--'--_ _
10
20
'--_--'--_~'--
o
30
40
__--'--_ ____'_ ___'___ ____'_ ___L_
. 50
60
70
80
90
____'
100 kHz
-tveo
Supply current versus temperature
Output current versus
L output voltage
rnA
rnA
15
50
14
I U'IU!
r-,
13
12
~
I
40
'\.
,
I
I
I
I
I
I,
r
,{I
I
I
'\
30
~
1\
40
60
I
I
I
I
I
I
I
I
I
--------;10
\
20
I
I
I
I
I
20
'\
11
10
-25
I
I
I
I
I
80 DC
o
o
I
I
I
I
I
I
I
I
I
I
I
I
2V
--T
967
lOA 4716A/lOA 47168
Ie for
Switched-Mode Power Supplies
Bipolar Ie
This versatile, 16-pin SMPS IC comprises digital and analog functions which are required
to design high-quality flyback, single-ended, and push-pull converters in normal, halfbridge a~d full-bridge configurations. The component can also be used in single-ended
volt&ge j-,-,ultipliers and speed-controlled motors. Malfunctions in electrical operation are
recognized by the integrated op amps, and activate protective functions_
Features
•
•
•
•
•
•
•
•
•
•
Push-pull outputs (open collector)
Double pulse suppression
Dynamic current limitation
Overvoltage protection
IC undervoltage protection
Reference voltage source (± 2% for TDA 4716 B)
Reference overload protection
Feed-forward control
Operational amplifier
Soft start
Pin configuration
top view
Pin designation
16 Os
0.2
0.1
4
13 lov
12 .lop Clmp
11 -lop amp
10 0. op amp
Pin- No.
Function
1
2
3
4
5
6
7
8
,9
10
11
12
13
14
15
16
Reference voltage Vref
Supply voltage Vs
Output 02
Output 0 1
Soft start C soft start
VCO RT
VCO C T
Ramp generator RR'
Ramp generator CR
Operational amplifier output
Operational amplifier input (-)
Operational amplifier input (+)
Input overvoltage
Dynamic current !imitation (-)
Dynamic current limitation (+)
Os
(TDA 4716A/4716B - Plastic 16 pin OIL package)
AG 1/84
969
TDA 4716 A
TDA4716 B
Circuit description
The following is a description of the individual functional units and their interaction.
Voltage controlled oscillator (VCO)
The VCO generates a sawtooth voltage. The duration of the falling edge is determined by the
value of CT. The duration of the rising edge of the waveform and, therefore, approximalety the
frequency, is determined by the value of RT. During the fall time, the VCO provides a trigger
signal for the ramp generator, as well as an L signal for a number of IC parts to be controlled.
Ramp generator
The ramp generator is triggered by the VCO and oscillates at the same frequency. The duration
of the falling edge of the ramp generator waveform is to be shorter than the fall time of the
VCO. To control the pulse width at the output, the voltage of the rising edge of the ramp
generator signal is compared with a dc voltage at comparator K2. The slope of the riSing
edge of the ramp generator signal is controlled by the current through RR. This offers the
possibility of an additional, superimposed control of the output duty cycle. This additional
control capability, called »feed-forward control", is utilized to compensate for known interference such as ripple on the input voltage.
Push-pull flipflop
The push-pull flipflop is switched by the falling edge of the VCO. This ensures that only one
output of the two push-pull outputs is enabled at a time.
Comparator K2
The two plus inputs of the comparator are switched such that the lower plus level is always
compared with the level of the minus input. As soon as the voltage of the riSing sawtooth edge
exceeds the lower of the two plus levels, both outputs are disabled via the pulse turn-off
flipflop. The period during which the respective, active output is low can be infinitely varied.
As the frequency remains constant, this process corresponds to a change in duty cycle.
Operational amplifier K 1
The op amp K1 is a high-quality amplifier. Fluctuations in the output voltage of the power
supply are amplified by K1 and applied to the free + input of comparator K2. Variations in
output voltage are, in this way, converted to a corresponding change in output duty cycle.
K1 has a common-mode input voltage range between 0 V and +5 V.
Pulse turn-off flipflop
The pulse turn-off flipflop enables the outputs at the start of each half cycle. If an error
signal from comparator K 7 or a turn-off signal from K2 is present, the outputs will immediately
be switched off.
Comparator K3
Comparator K3 limits the voltage of capacitance Csoft start (and also at K2!) to a maximum of
5 V. The voltage at the ramp generator output may, however, rise 10 5.5 V. With a corresponding slope of the rising ramp generator edge, the duty cycle can be limited to a desired
maximum value.
970
TDA 4716 A
TDA4716 B
Comparator K4
The comparator has its switching threshold at 1.5 V and sets the error flipflop with its output
if the voltage at capacitance C soft start is below 1.5 V. However, the error flipflop accepts the
set signal only if no reset pulse (error) is applied. In this way the outputs cannot be turned
on again as long as an error signal is present.
Soft start
The lower one of the two voltages at the plus inputs of K2 is a measure for the duty cycle
at the output. At the instant of turning on the component, the voltage at capacitor C soft start
equals 0 V. As long as no error is present, this capacitor is charged with a current of 6 iJ.A
at the maximum value of 5 V. In case ·of an error, Csolt start is discharged with a current
of 2 iJ.A. A set signal is pending at the error flipflop below a charge of 1.5 V and the outputs
are enabled if no reset signal is pending simultaneously. As the minimum ramp generator
voltage, however, is 1.8 V, the duty cycle at the outputs is actually increased slowly and
continuously not before the voltage at C soft start exceeds 1.8 V.
Error flipflop
Error signals, which are led to input R of the error flipflop cause an immediate disabling of
the outputs, and after the error has been eliminated, the component to switch on again
using the soft start.
Comparator K5, KB, Vrel overcurrent load
These are error detectors which cause immediate disabling of the outputs via the error
flipflop when an error occurs. After elimination of the error, the component switches on again
using the soft start.
Comparator K 7
K 7 serves to recognize overcurrents. This is the reason why both inputs of the operational
amplifier have been brought out. Turning on is resumed after error recovery at the beginning
of the next half period but without using the soft start. K 7 has a common-mode input voltage
range between 0 V and +4 V. The delay time between occurrence of an error and disabling
of the outputs is only 250 ns.
Outputs
Both outputs are transistors with open collectors and operate in a push-pull arrangement.
They are actively low. The time in which only one of the two outputs is conductive can be
varied infinitely. The length of the falling edge at veo is equal to the minimum time during
which both outputs are disabled simultaneously. The minimum L voltage is 0.7 V.
Reference voltage
The reference voltage source is a highly constant source with regard to its temperature
behavior. It can be utilized in the external wiring of the op amp, the error comparators, the
ramp generator, or other external components.
971
TDA4716 A
TDA 4716 B
Maximum ratings
Supply voltage
Voltage at 01. 02
0112 high
Current at 01. 02
o 1/2 low
Input RT
Input CT
Input RR
Input CR
Input comparator
K5. K7
Output K5
Inputop amp
Output op amp
Reference voltage
Input CsoH start
Vs
VQ
Lower
limitS
Upper
limit A
-0.3
-0.3
33
33
V
V
70
mA
-0.3
-0.3
-0.3
-10
7
7
7
10
V
V
V
mA
-0.3
-0.3
-0.3
-0.3
33
33
33
V
V
V
IQ
V IRT
VICT
VI RR
IICR
VIK5•7
V QK5
Vlopamp
VQopamp
V Qref
VI soft start
Junction temperature
Storage temperature
TJ
Thermal resistance (system-air)
RthSA
Tstg
Vs -1
but max. 7 V
V
-0.3
-0.3
7
V
V
-55
125
125
°C
°C
60
K/W
30
30
70
85
100000
250000
250000
V
V
°C
°C
V ref
Operating range
Supply voltage TDA 4716 A
TDA 4716 B
Ambient temperature TDA 4716 A
TDA 4716 B
Frequency
VCO frequency
Ramp generator frequency
972
Vs.
Vs
Tamb
Tomb
f
fvco
fRG
10.5
11
0
-25
40
40
40
Hz
Hz
Hz
TDA4716 A
TDA4716B
Characteristics
TDA 4716 A
Lower
limitS
Supply voltage
Ambient temperature
Supply current
CT = 1 nF
tvco = 100 kHz
Vs
typ
10.5
TDA 4716 B
Upper
limit A
Lower
limitS
30
70
16
11
-25
8
2.65
2.45
typ
Upper
limit A
30
85
20
V
2.55
V
Tamb
a
Is
8
Reference voltage
Vre!
2.35
Voltage change
Vs = 14 V ± 20%
Voltage change
Vs =25 V ± 20%
Voltage change
mA< Iret <5 mA
Temperature coefficient
Response threshold
of I ret overcurrent
LIVre!
8
8
mV
LIVre!
15
15
mV
°C
mA
Reference
a mA
~RRlrot'd
.-
~~
V
!
+--_.. -
- -
A~
~.
> V;RR
t/
i
i
Voltage at output 1
l
+--------
I
I
I
I
I
I
i
--
C-l
0.5 T
'li V
~
5
:s-'t 18
15
v
976
I
I
I
I,
I -.LI
i
~-
Vol tage at output 2
rt"
L/
L/
,
,
1T
1.5T
Soft start - error - ON/OFF
-t
~ soft start
+VIK1
CD
6'
n
+VjR R
Ie.
r-----
eT
R.
,
~
l
CL
iii'
8
Push-puLL FF
I
I
I
I
Output
op amp
I
I
I
I
I
ce
iil
3
----------------------------,t
13
Q
e
Ramp
voLtap.
tMinim~ml~:eL
111
-Input
op amp
02 output
(active L)
O.7V~Vl"1V
o
r=r
~------ ~s
Compi
Ki-:> Comparator
Rdominant
II
dominant
o
4
I PuLse turn-off FF
• Input
op amp
Discharge at
1
01 output
(active L)
I O.7V'" Vl"'W
I
a =L lerror)
I
I
I
Error FF IRdominant)
~----,
I
Ie undervoLtage
,........c=J
I
F
SuppLy voltage
IJ1 T 22~F
L _____ ~ Is
O.33~~
Soft start
<0
.....
.....
13
OvervoLtage
TCsottstnrt
rl
__________________ JI
Vref overcurrent load
15
14
Dynami( (urrent Limitation
160V
...........
gg
~~
:j:j
0)0)
aJl>
TDA 4716 A
TDA4716 B
veo frequency versus RT and CT
CT =B20pF
~
Cylnr
i'..
r--C =2,2nF
I
cT = 4,7nF
'1111
cT =15nF
"
"""" "
!" "
"
~
~
,
"-
i'
cT = 47nF
"'-
"-"'- f'...
t"-.
,
."-.
"
r-......
978
"
"
"-
TDA411~A
TDA4716 B
veo temperature response
Vs=12V;1'=max.
Mvco
fK x K
r, ] with C
IX
T
as parameter
T-~
~,~[XJ
1 3,10"'
0.5nF
-10·' '---_....L_ _'---_-"-_----''---_-L_----'_ _-L_----'_ _--'--_----l
o
10
20
30
40
50
60
70
80
90
100 kHz
-'V(O
Output current versus
L output voltage
Supply current versus temperature
rnA
rnA
15
50
14
,
13
/
/
I
I
I Q lIQZ
~
I /
I I
I,
40
\.
11
o
I
,
'\
,
30
'"
20
I
/
i
f
12
10
-25
I
I
I
I
I
I
I
I
20
'\
4D
10
\
60
--------;-
80 .[
o
o
I
2V
--T
979
lOA 4718/l0A 4718A
Control IC for Single-Ended
and Push-Pull Switched-Mode
Power Supplies
Bipolar Ie
This 18-pin SMPS control IC comprises digital and analog functions which are required to
design high-quality flyback, single-ended, and push-pull converters in normal and halfbridge configurations. In addition to the control functions, the circuit contains operational
amplifiers which detect malfunctions during electrical operation and suitable protective
measures. A PLL circuit for synchronization is one of the special advantages offered by this IC
in addition to the following features:
•
•
•
•
•
•
•
Feed-forward control (line hum suppression)
Push-pull outputs
Dynamic current limitation
Overvoltage protection
Undervoltage protection
Soft start
Double pulse suppression
(TDA 4718 - Ceramic 18 pin DIL package)
(TDA 4718A - Plastic 18 pin DIL package)
Pin configuration
top view
18 Cr
Os
17 C"""
RR
CR
3
16 Rr
I COMP 4
15 Csoft stod
I SYNC 5
14 0 SYNC
Iuv
1301
Iov
12 02
lis
-IDYN
11
+IDYN
10 Vre ,
+
Pin designation
Pin No.
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Os
Ramp generator RR
Ramp generator CR
+ input comparator K 2
Sync input
Input undervoltage, ON/OFF
Input overvoltage
Input dynamic current limitation (-) .
Input dynamic current limitation (+)
Reference voltage Vrel
Supply voltage Vs
Output Q 2
Output Q 1
Sync output
Soft start
VCO RT
Capacitance Cfilter
VCO CT
AG 1/84
981
TDA4718
TDA4718 A
Circuit description
Voltage controlled oscillator (VCO)
The VCO generates a sawtooth voltage. The duration of the falling edge is determined by
the value of CT. The duration of the rising edge of the waveform and, therefore, approximately
the frequency, is determined by the value of RT. By varying the voltage at Cfiller, the oscillator
frequency can be changed by its rated value. During the fall time, the VCO provides a trigger
signal for the ramp generator, as well as an L signal for a number of IC parts to be controlled.
Ramp generator
The ramp generator is triggered by the VCO and oscillates at the same frequency. The
duration of the falling edge of the ramp generator waveform is to be shorter than the fall time
of the VCO. To control the pulse width at the output, the voltage of the rising edge of the ramp
generator signal is compared with a dc voltage comparator K2. The slope of the rising
edge of the ramp generator signal is controlled by the current through RR' This offers the
possibility of an additional, superimposed control of the output duty cycle. This additional
control capability, called ..feed-forward control«, is utilized to compensate for known
interference such as ripple on the input Voltage.
Phase comparator
If the component is operated without external synchronization, the sync input must be
connected to the sync output for the phase comparator to set the rated voltage at Clilter'
The VCO then oscillates with rated frequency. In the case of external synchronization, other
components can be synchronized with the sync output. The component can be frequencysynchronized, but not phase-synchronized, with the sync input. The duty cycle of the
square-wave voltage at the sync input is arbitrary. The best stability as to small phase and
frequency interference is achieved with a duty cycle as offered by the sync output.
Push-pull flipflop
The push-pull flipflop is switched by the falling edge of the VCO. This ensures that only one
output of the two push-pull outputs is enabled at a time.
Comparator K2
The two plus inputs of the comparator are switched such that the lower plus level is always
compared with the level of the minus input. As soon as the voltage of the rising sawtooth
edge exceeds the lower of the plus levels, both outputs are disabled via the pulse turn-off
flipflop. The period during which the respective, active output is low can be infinitely varied.
As the frequency remains constant, this process corresponds to a change in duty cycle.
Pulse turn-off flipflop
The pulse turn-off flipflop enables the outputs at the start of each half cycle. If an error signal
from comparator K 7 or a turn-off signal from K2 is present, the outputs will immediately be
switched off.
Comparator K3
Comparator K3 limits the voltage at capacitance Cselt start (and also at K2!) to a maximum of
+ 5 V. The voltage at the ramp generator output may, however, rise to 5.5 V. With a corresponding slope of the rising ramp generator edge, the duty cycle can be limited to a desired
maximum value.
982
TDA4718
TDA4718 A
Comparator K 4
The comparator has its switching threshold at 1.5 V and sets the error flipflop with its
output if the voltage at capacitance Csoft start is below 1.5 V. However, the error flipflop accepts
the set signal only if no reset pulse (error) is applied. In this way the outputs cannot be turned
on again as long as an error signal is present.
Soft start
The lower one of the two voltages at the plus inputs of K2 is a measure for the duty cycle at
the output. At the instant of turning on the component, the voltage at capacitor Csoft start
equals 0 V. As long as no error is present, this capacitor is charged with a current of 6 iJA
to the maximum value of 5 V. In case of an error, C soft start is discharged with a current of 2 flA.
A set signal is pending at the error flipflop below a charge of 1.5 V and the outputs are enabled
if no reset signal is pending simultaneously. As the minimum ramp generator voltage,
however, is 1.8 V, the duty cycle at the outputs is actually increased slowly and continuously
not before the voltage at Csoll start exceeds 1.8 V.
Error flipflop
Error signals, which are led to input R of the error flipflop, cause an immediate disabling of
the outputs, and after the error has been eliminated, the component to switch on again
using the soft start.
Comparator K5, K6, K8, Vref overcurrent load
These are error detectors which cause immediate disabling of the outputs via the error
flipflop when an error occurs. After elimination of the error, the component switches on again
using the soft start.
Comparator K 7
K 7 serves to recognize overcurrents. This is the reason why both inputs of the op amp
have been brought out. Turning on is resumed after error recovery at the beginning of the
next half period but without using the soft start.
Outputs
Both outputs are transistors with open collectors and operate in a push-pull arrangement.
They are actively low. The time in which only one of the two outputs is conductive, can be
varied infinitely. The length of the falling edge at VCO is equal to the minimum time during
which both outputs are disabled simultaneously.
Reference voltage
The reference voltage source is a highly constant source with regard to its temperature
behavior. It can be utilized in the external wiring of the op amp, the error comparators, the
ramp generator, or other external components.
983
TDA4718
TDA4718 A
Maximum ratings
Supply voltage
Voltage at 01. 02
Current at 01. 02
Sync output
Sync input
Input Cfilter
Input RT
Input CT
Input RR
Input C R
Input comparator
K2. K5. K6. K7
Output K5
Reference voltage
Input Csoft start
Notes
Vs
Va
01.02high
10
01.021ow
SYNC 0 high
SYNC 0 low
VSYNCa
ISYNca
VSYNCI
VICf
VI RT
VICT
VI RR
IICR
V1K
VaKs
Vref
VI soft start
Junction temperature
Storage temperature
Tj
T stg
Thermal resistance (system-air)
TDA 4718
TDA4718A
RthSA
RthSA
Lower
limitS
Upper
limit A
-0.3
-0.3
33
33
70
7
10
33
7
7
7
7
10
V
V
mA
V
mA
V
V
V
V
V
mA
-0.3
33
33
Vref
7
V
V
V
V
-55
125
125
°C
DC
70
60
K/W
K/W
-0.3
0
-0.3
-0.3
-0.3
-0.3
-0.3
-10
-0.3
-0.3
-0.3
Operating range
Supply voltage
Ambient temperature
TDA4718
TDA4718A
Max. VCO frequency
Ramp generator frequency
984
Vs
10.5
30
V
Tamb
Tamb
-25
0
40
40
85
70
250000
250000
DC
DC
f
fRG
Hz
Hz
TCA4718
TCA4718 A
Characteristics
Test
conditions
Vs =11 Vt030V;
Tamb = -25°C
Supply current
Lower
limitS
typ
Upper
limit A
to +85 °C
Is
Cr = 1 nF
fvco = 100
8
20
mA
2.65
151)
V
mV
mV
mV
0.4
mV/K
kHz
Reference
Reference voltage
Reference voltage change
Reference voltage change
Reference voltage chenge
Temperature coefficient
Response threshold
of I rel overcurrent
Vrel
OmA~RRlrat.d >VJRR
. \/
\~
/
\,/
L/
~ saft start
+VIK 2
I
Voltage at output 1
I I
I
I
I
I
I
Vol tage at output 2
rlt
I
0.5 T
~ V
I
II
I
1T
1.5T
-t
Soft start- error-ON/OFF
'~
v
t~~~____-+u-~~~~__
o
988
m
g
Vi ••
.l [.
R.
~
[l.l
18
r-----
,Rl
16
.l ["""
17
I SYNC (lSYNC
5
14 ______________________ -,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
8/
I
Push-pull FF
Ramp
voltage
9SynLPU,Se
I
Input
[amp.
a.
iii·
ea
iil
3
~ Hinimum level
4.
I+ K 2
13 01 output
I
ladive L)
I 0.7V:O Vl " W
I
Q
I
I
R
(amp orator
I
a
Rdominant
Q
Pulse turn-off FF
Dis[harge at Q = L (error)
IErrar-FF(fl dominant)
Q
I
I
5
dominant
I
I
'
I
12 02 output
lactive L)
10.7V" Vl:oW
I
I
I
I
I( undervalluge
I
110
:T
v.
L ______ _
0.33~~5
Soft start
~
T
,---11 OV
1 -1II
________ ~ ______
,,' avereurrent I
[soft start
Overvolta~e
6
ONIOFF
Dynamic current
limitation
undervollage
Reference
voltage
22VF
gg
~~
:j:j
C»C»
~
TDA4718
TDA4718A
veo frequency versus Rr and Cr
Hz
CT =820pF
"
Cy1y
t'-....
t-------C T, =2,2 nF
"'1"-
..........
1
CT = 4,7nF
"-i'...
'1111 ~ r---r--,
CT = 1SnF
"-
~
"'
,
""-
1'-...
r---.
I..... ,
CT =47nF
"-
"'"I"-.
.....
'"""
990
r"\
"I"-.
I"
TDA4718
TDA4718A
VCO temperature response
Vs=12V; 1'= max.
Llfvco [1 ]
fK x K )ok with CT as parameter
--+--
3.3nF
1.0nF
0.5nF
-10"'
'--~-L~~'--~-L~---''--__-"-~--'~~...L...~--'~~...L...~--l
o
10
20
30
40
50
60
70
80
90
100 kHz
-fveo
Current consumption versus temperature
Output current versus
output voltage
rnA
rnA
15
50
I
I
I
I
I I
I I
[01102
14
13
~
40
r
'"
11
10
-25
o
"
20
40
I
I
7
20
"-
60
10
\
80
o
O(
I
,
, ,
,, ,
I
"'"'\
12
,{,
30
'\
/
/
/
I
o
I
I
I
I
I
I
,
,
,I
,
,
,
I
I
,
I
I
2V
--T
991
Integrated Circuits for Consumer Applications
Integrated Circuits for Consumer Applications
*See Consumer Data Book or contact
your local Siemens Representative.
995
Table of Contents
General Information
Summary of Types
Microcontroller and Microprocessor Components
Peripheral and Support Components
Memory Components
Telecom Components
Data Conversion Components
Switched Mode Power Supply (SMPS) Components
Integrated Circuits for Consumer Applications
I
I
I
I
I
I
I
The information contained here has been carefully
reviewed and is believed to be accurate. However, due
to the possibility of unseen inaccuracies, no respon·
sibility is assumed.
This literature does not convey to the purchaser of
electronic devices any license under the patent rights
of any manufacturer.
Issued by Integrated Circuits Division
186 Wood Avenue South, Iselin, NJ 08830 (201) 321·3400
Siemens Components, Inc.
CG/2000·286·121
BAN 15M 5185 Printed in U.S.A.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:07:12 16:19:37-08:00 Modify Date : 2017:07:12 17:10:21-07:00 Metadata Date : 2017:07:12 17:10:21-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:dadf351c-3514-1343-b872-f72644258a2a Instance ID : uuid:77eb61f5-1e0f-0d42-aa4d-7303ea8177ed Page Layout : SinglePage Page Mode : UseNone Page Count : 1000EXIF Metadata provided by EXIF.tools