1985_Siliconix_MOSPOWER_Applications 1985 Siliconix MOSPOWER Applications
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H MOSPOWER Applications Handbook Editor in Chief Rudy Severns Senior Staff Engineer Assistant Editor Jack Armijos Senior Applications Engineer Siliconix incorporated Santa Clara, California 95054 Library of Congress Cataloging in Publication Data Main entry under title: MOSPOWER applications handbook. Bibliography: p. Includes index. 1. Metal oxide semiconductor field-effect transistors-Handbooks, manuals, etc. 2. Power transistors--Handbooks, manuals, etc. I. Severns, Rudolf P. II. Armijos. Jack, 1949III. Title: M.O.S.P.O.W.E.R. applications handbook. TK7871.95.M67 1984 621 31'7 84-14140 ISBN 0-930519-00-0 Editorial production/supervision: Robin Berliner Interior design: Robin Berliner Cover design: Thomas Washburn Associates © 1984 by Siliconix incorporated. All Rights Reserved. This book, or parts thereof, may not be reproduced in any form without permission from Siliconix. Information contained in this book is believed to be accurate and reliable. However, we cannot accept responsibility for its use, nor for any infringement of patents at rights of others which may result from its use. Publication of this information does not imply any authority or license for the use of any patented feature. Printed in the United Stales of America 10 9 8 7 6 5 4 3 2 I ISBN 0-930519-00-0 ii Contributing Authors Edward R. Abramczyk Mark Alexander George Allen Dr. Richard H. Baker Dr. Richard Blanchard Gordon (Ed) Bloom Dr. Dan Y. Chen Robert R. Cordell C.P. Der Phil Ekstrom Alton Eris Z.D.Fang W. E. Frank David Giandomenico James Harnden Barry Harvey Michael Herrick John G. Kassakian Steve Kent DavidLau Dr. Fred C. Lee DavidMele iii Dr. R. D. Middlebrook Ramesh Oruganti Ed Oxner George Riehm William Roehr Gary Rothrock Ray Ruble Rudy Severns P. D. Wesel Richard Williams Acknowiedgement This book is the result of the efforts of many people. We have elected not to identify every contribution by scattering the authors' names throughout the text. Rather we have grouped them here for convenience. The following is an alphabetical listing of the authors and their contributions: Contributing Authors Sections Edward R. Abramczyk Sr. Design Engineer Siliconix incorporated Santa Clara, CA 2.9 2.9.1 Mark Alexander Applications Engineer Siliconix incorporated Santa Clara, CA 2.9 2.9.1 2.12 3.1 4.2 5.1 5.2 5.6 5.6.2 6.6.4 6.10 6.11 6.14.2 A.1 A.2 George Allen Testing Engineer Siliconix incorporated Santa Clara, CA 7.1 iv Dr. Richard H. Baker Gould Inc. Andover,MA 6.1.1 Dr. Richard Blanchard Vice-President of Design and Advanced Technology Development Siliconix incorporated Santa Clara, CA 1.3 2.9 2.9.1 2.11 4.2 5.6 5.6.2 7.1 Gordon (Ed) Bloom E. &J. Bloom Associates Arcadia,CA 6.1.2 6.1.3 Dr. Dan Y. Chen Assistant Professor of Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 5.3.4 5.5 6.7 6.8 6.9 Robert R. Cordell Tinton Falls, NJ 6.6.3 C.F.Der Westinghouse Electric Corp. Sykesville, MD 6.2 PhUEkstrom Chief Scientist Northwest Marine Technology Shaw Island, WA 6.12 Alton Eris Litton Industries Woodland Hills, CA 6.1.2 Ramesh Oruganti Massachusetts Institute of Technology Cambridge, MA 2.13.1 Z.D.Fang Virginia Polytechnic Institute and State University Blacksburg, VA 6.9 Ed Oxner Staff Engineer Siliconix incorporated Santa Clara, CA W.E.Frank Westinghouse Electric Corp. Sykesville, MD 6.2 David Giandomenico Graduate Student University of California Berkeley, CA 5.3.1 James Harnden FineH Systems SanJose,CA 6.12 6.14.1 6.14.2 1.1 1.2 2.2.1 2.3 2.4 2.5 2.6 2.7 2.10 2.13.2 3.2 5.3 5.6.1 A.3 A.4 A.5 6.1.5 George Riehm NEC Electronics Sunnyvale, CA 6.1.4 Barry Harvey Advanced Micro Devices Santa Clara, CA Michael Herrick NewYork,NY 6.1.6 William Roehr Applications Manager General Semiconductor Industries Tempe,AZ 6.3 6.6.1 6.6.2 John G. Kassakian Laboratory for Electromagnetic and Electronic Systems Massachusetts Institute of Technology Cambridge, MA 5.3.2 5.3.3 Gary Rothrock Fairchild Sunnyvale, CA 6.13 Steve Kent Cypress Semiconductor SanJose,CA 7.2 7.4 Ray Ruble Sr. Applications Engineer Siliconix incorporated Santa Clara, CA 2.8 6.5 Rudy Severns Sr. Staff Engineer Siliconix incorporated Santa Clara, CA Preface 2.1 2.13.2 4.1 5.3 5.4 5.6 5.7 6.1.3 6.1.4 P.O. Wesel Virginia Polytechnic Institute and State University Blacksburg, VA 6.8 Richard Williams IC Design Engineer Siliconix incorporated Santa Clara, CA 5.2 DavidLau Student Massachusetts Institute of Technology Cambridge, MA ·5.3.3 Dr. Fred C. Lee Professor of Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 2.13.1 5.3.4 5.5 6.7 6.8 6.9 Dave Mele MacLeod Labs, Inc. SanJose,CA 6.1.6 Dr. R. D. Middlebrook Professor of Engineering California Institute of Technology Pasadena, CA 2.2 v A book is a creation not only of the authors but also of the support people who made the finished book a reality and without whose help the book would never have been printed. Special thanks are due to Susan Scott for her endless hours of editing for English (engineers really can't spell!); to Ray Lubow, Ray Ruble, and Ed Oxner for technical editing; to Pam Lewis, Susan Hamel, and Linda Cosner for their seemingly unlimited patience in typing and retyping and retyping ... the manuscript; and to Robin Berliner who took the manuscript and the drawings (which most closely resembled chicken scratchings) and turned them into a beautifully finished text. A substantial portion of the credit for the book belongs to Jack Armijos who did the real grunt work of collating material, hounding the authors and editors to finish their work, and in general, seeing to it that the project kept moving. Rudy Severns July, 1984 vi Introduction to MOSPOWER FETs I11III Power MOSFET Structures _ MOSFET Electrical Characteristics _ Thermal Design and SOA _ _ Practical Design Considerations _ Applications Information _ I MOSFET Testing and Reliability _ Appendices _ i Index _ vii viii Table of Contents Chapter 1 Introduction to MOSPOWER FETs 1.1 1.2 1.3 Page General Remarks .............................................................. 1-1 A Little History ............................................................... 1-4 Fundamental Limitations of Power MOS Transistor Performance ....................... 1-6 Chapter 2 Power MOSFET Structures 2.1 2.2 2.2.1 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.9.1 2.10 2.11 2.12 2.13 2.13.1 2.13.2 Principles of MOSFET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1 FETs and BITs as Charge-Controlled Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4 Charge Transfer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-11 Planar MOS ................................................................. 2-17 DMOS (Double Diffused MOS) ................................................. 2-19 V-Groove MOS .............................................................. 2-21 Lateral Power DMOS (LDMOS) ................................................. 2-23 Vertical DMOS (VDMOS) ..................................................... 2-24 The Bilateral MOSFET ........................................................ 2-26 Depletion Mode Power MOSFETs: New Devices to Solve Old Problems ................ 2-33 Fabrication of Depletion Mode Power MOSFETs ................................... 2-39 Other Structures .............................................................. 2-41 Power Control with Integrated CMOS Logic and DMOS Output. . . . . . . . . . . . . . . . . . . . . .. 2-43 Drain-to-Source Breakdown and Leakage in Power MOSFETs ........................ 2-49 Modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-56 SPICE 2 Simulation of High Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-56 The High Frequency Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-70 Chapter 3 MOSFET Electrical Characteristics 3.1 3.2 Linear Operation ............................................................... 3-1 Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-9 Chapter 4 Thermal Design and SOA 4.1 4.2 Safe Operating Area and Thermal Design for MOSPOWER Transistors . . . . . . . . . . . . . . . . .. 4-1 HP-41CV Power MOSFET Thermal Analysis Program .............................. 4-17 ix Chapter 5 Practical Design Considerations 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.4 5.5 5.6 5.6.1 5.6.2 5.7 Page High Speed Gate Drive Circuits .................................................. 5-1 Temperature Compensated Biasing for Power MOSFETs in Linear Amplifiers ............ 5-9 Parallel Operation of Power MOSFETs ........................................... 5-15 Anomalous Oscillations and Turn-Off Behavior in a Vertical Power MOSFET ........... 5-33 Thermally Forced Current Sharing in Paralleled Power MOSFETs ..................... 5-43 An Analysis and Experimental Verification of Parasitic Oscillations in Paralieled Power MOSFETs ........................................................... 5-48 Power FET Paralleling ............ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-55 dVDsldt Turn-On in MOSFETs ................................................. 5-57 Inverse Diodes of Power MOSFETs .............................................. 5-65 MOSFETs Move In on Low Voltage Rectification .................................. 5-69 Using Power MOSFETs as High Efficiency Synchronous and Bridge Rectifiers in Switch Mode Power Supplies ................................................. 5-87 Use MOSPOWER Transistors as Synchronous Rectifiers in Switched Mode Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-95 Power MOSFETs and Radiation Environments .................................... 5-101 Chapter 6 Applications Information 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 6.3 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.13.1 6.13.2 6.13.3 6.13.4 6.13.5 6.13.6 6.13.7 6.13.8 6.13.9 Power Supply Applications ...................................................... 6-1 High Frequency Power Conversion with FET Controlled Resonant Charge Transfer . . . . . . .. 6-1 Practical Design Considerations for a Multi-Output eUK Converter ..................... 6-8 The Generalized Use of Integrated Magnetics and Zero-Ripple Techniques in Switch Mode Power Converters ............................................. 6-25 Siliconix Switch Mode Power Supply Kit ......................................... 6-49 A 500 kHz Switching Inverter for 12V Systems ................................... , 6-59 A Low Cost Regulator for Microprocessor Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-62 Solid State RF Generators for Induction Heating Applications ......................... 6-71 Using Power MOSFET Transistors to Interface from IC Logic to High Power Loads ................................................ , ......... 6-81 MPP500; The First Single Package Complementary MOSPOWER Device ............... 6-89 Applying 240 V MOSPOWER Transistors and Current Limiting Diodes to Electronic Pulse Dialer Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-93 Audio Amplifiers ............................................................. 6-97 The Autobias Amplifier. A New (AC Coupled) Topology for Automatically Biased Audio Amplifier Using Power MOSFETs ............................................. 6-97 A Simple Direct-Coupled Power MOSFET Audio Amplifier Topology Featuring Bias Stabilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-105 A MOSFET Power Amplifier with Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-111 Boost Op Amp Output Power With Complementary Power MOSFETs . . . . . . . . . . . . . . . .. 6-125 Bipolar-FET Combinational Devices ............................................. 6-130 Power FET Base Drive Circuit for High Power Darlington Transistors ................. 6-135 A High Power High Frequency FET Inverter for a Low Frequency Transmitter .......... 6-139 Linear Voltage and Current Regulators Using Power MOSFETs ...................... 6-145 Frequency Response Analysis of the MOSFET Source-Follower ...................... 6-151 Stepper Motor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-156 Design Tips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-165 Solving the Stepper Motor Interface Problems ..................................... 6-165 The D469, an Optimized CMOS Quad Driver for MOSPOWER FET Switches .......... 6-169 14 V, 4 A Battery Charger/Power Supply ........................................ 6-176 400 V, 60 Watt Push-Pull Power Supply ......................................... 6-177 Self Oscillating Flyback Converter . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. 6-178 Positive Input/Negative Output Charge Pump ..................................... 6-179 20 Watt, Class A Audio Amplifier .............................................. 6-180 Astable Flip-Flop with Starter .................................................. 6-181 High Current Analog Switches ................................................. 6-182 x 6.13.10 6.13.11 6.13.12 6.13.13 6.13.14 Laser Diode Pulsers .......................................................... A One-MOSPOWER FET Analog Switch ........................................ Stepping Motor Driver ........................................................ Constant Speed Motor Controller ............................................... Voltage-to-Frequency Converter with Digital Line Driver ........................... Page 6-184 6-185 6-186 6-187 6-188 Chapter 7 MOSFET Testing and Reliability 7.1 7.2 7.3 7.4 Understanding MOSPOWER Transistor Characteristics Minimizes Incoming Testing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-1 Accelerated Testing ............................................................ 7-8 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 -11 Reliability Report Example ..................................................... 7-13 Chapter 8 Appendices A.l A.2 A.3 A.4 A.5 A.6 A.7 Calculating the RMS Value of MOSFET Drain Current Using the HP-41CV .............. 8-1 HP-41CV Transient Thermal Impedance Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-3 Table of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-5 Glossary of Terms ............................................................. 8-7 Additional References .......................................................... 8-9 MOSPOWER Selector Guide ................................................... 8-16 Worldwide Sales Offices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-24 Index ............................. ........................................... 9-1 xi Preface Since the introduction of the first practical power MOSFETs, in October 1975 by Siliconix, these devices have undergone major performance improvements and are now widely accepted and used in power electronics equipment. criticisms, and contributions. If you do this and we are diligent in correcting and expanding the text, future editions of this handbook should provide a rich source of information for the user of power MOSFETs. Along with improvements in the devices, an understanding of how to use these devices in practical circuits has gradually evolved. Like any new semiconductor device, the process of understanding has been slow and the progress uneven. Even though our knowledge of these devices is far from complete, much has been learned which would be helpful to circuit designers. Unfortunately, this information has, until now, been scattered through a wide variety of publications or in some cases was unpublished. In this first edition, approximately 25 percent ofthe material is new, and a number of important issues are treated here in detail for the first time. Another 35 percent of the material is a rewrite and expansion on earlier work with an emphasis on putting the information in context by interrelating the various subjects. The remaining material is a collection of application examples taken from a variety of industries. The book is divided into four sections. Chapters 1 through 3 discuss the basic operation ofMOSFETs. Chapters 4 and 5 deal with the practical problems of using MOSFETs from a device point of view. Chapter6 is a collection of applications examples selected to demonstrate how to use MOSFETs from a circuit point of view. Chapter 7 provides an introduction to the testing and reliability of MOSFETs. The purpose of this handbook is to solve this problem by providing a source of detailed, up-to-date information on device characteristics and circuit applications. This is an ambitious goal, and total success in the first edition is not possible. What is available here is essentially a snapshot in time. This book is intended to be a beginning, not an ending, and subject to revision and updating as our understanding grows. If the book is to continue to grow and become the central reference work for MOSFET applications, it is vital that you, the reader, send us your comments, The intent throughout is to provide a balance of basic theory and practical design information since it is our belief that this leads to the best designs. The balance should make this book useful to technicians while still providing plenty of meat for the advanced worker. Rudy Severns July 1984 xiii Introduction to MOSPOWER FETs _ _ Silicon Chapter 1 Introduction to MOSPOWER FETs 1.1 General Remarks Introduction There are two basic field-effect transistors (FETs): the junction FET (JFET) and the metal-oxide semiconductor FET (MOSFET). Both have played important roles in modern electronics. The JFET has found wide applic.ation in such cases as high-impedance transducers (scope probes, smoke detectors, etc.), and the MOSFET in an ever-expanding role in integrated circuits where CMOS (Complementary MOS) is perhaps the most well-known. Before embarking on the differences between JFETs and MOSFETs, note that operationally there are three classes of FETs easily identified in Figure 1: depletion-mode JFETs, depletion-mode MOSFETs, and enhancement-mode MOSFETs. "-CHANNEL CLASS p-CHANNEL v•• o + 1 T 1 T IT 11 -A- All of these applications are best described as smallsignal where signal levels are measured in a few volts and where the relative power levels range from picoto micro-watts. Such FETs are microscopically small with the potential of placing thousands ofthem upon a single semiconductor chip. DEPLETION-MODE J-FET o v•• v•• o This handbook is about MOSFETs-power MOSFETs-and they are not microscopic. Before the reader plunges into the text, it is wise to review the differences between a small-signal FET and a power MOSFET. Also, the reader should identify our definition of power since this handbook is for power applications. + -B- DEPLETION·MODE MOSFET o v•• FETs and MOSFETs-How They Differ v•• o Junction FETs (JFETs) and small-signal MOSFETs differ in their cross-section as well as in their operation. Both are majority-carrier transistors in that they do not rely upon the mechanism familiar to the users of bipolar transistors: injection, diffusion, and collection. While the bipolar transistor needs an injection of base current to initiate transistor action, the FET is controlled by a gate-to-source potential. Current, hence power, is not a requirement for FET action. ENHANCEMENT-MODE MOSFET -c- o v•• + The "ABC's" of FET Bias Control Figure 1 1·1 - 'D + l1li Class A is defined as the depletion-mode class; all JFETs perform in this class. Class B is also defined as being in the depletion-mode class, but, as can be seen from the figure, it can support enhancement current. Class C is strictly enhancement. MOSFETs perform in either Class B or Class C. No JFET is capable of performance in either of these latter classes because it would require forward biasing of the gate junction-a condition strongly discouraged. Figure 3, the output characteristics for a typical nchannel JFET are shown with IDSS and Vp clearly identified. . U 290 OUTPUT CHARACTERISTICS lOSS /' 400 The JFET and the MOSFET have fundamental fabrication differences which are easily visualized from the cross-sectional view in Figure 2. Here the JFET has a diffused gate electrode, but the MOSFET has a gate electrode electrically isolated from the channel. In this illustration, the MOSFET is a Class C MOSFET-more commonly known as an enhancementmode MOSFET. GATE - ( / !~ I I 200 9 100 DRAIN /1 I -PlT"""FF I/ {t/ LOCUS I Yp • ,. 12 20 Vos - DRAIN-SOURCE VOLTAGE (V) Typical Output Characteristics of a J FET Showing the Saturation Drain Current, lOSS, and the Pinch-off Voltage, Vp Figure 3 CLASS 'A' DEPLETlON·MODE J·FET If the JFET gate is forward biased (positively for an (a) SQURCE GATE n-channel JFET and negatively for a p-channel JFET) , the pn-junction formed by the gate diffusion would be in current conduction. Two things occur: first, substantial gate current would flow resulting in a lowering of the gate input resistance; and, second, a slight increase in drain current would be observed. The latter results from both the contribution of gate current as well as from some further reduction of the depletion field which increases the available channel current. DRAIN CONDUCTIVE GATE GATE INSULATOR ~:::b~~~~gJL-r-..., CLASS 'C' ENHANCEMENT·MODE MQSFET (b) SOURCE cross-Sectional Comparison between a J FET (a) and an Enhancement-Mode MOSFET (b) Figure 2 GATE DRAIN CONDUCTIVE GATE GATE INSULATOR Operation is as follows. Gate control for the JFET depends upon the manipUlation of a depletion field about the gate diffusion. The gate is biased with an abundance of negative charge (using an n-channel JFET as an example) by tying the gate terminal to the source. As the drain-to-source voltage rises, a depletion region forms and almost all the electrons in the channel are swept away. The most depleted area is, of course, between the drain and gate; the least depleted area is between gate and source. As the drain potential increases, current will increase but only to a limit where beyond, with increasing voltage, no additional current passes. This current limit is called IDSS (saturation drain current at zero bias), and the drain voltage limit is called Vp (pinch-off drain voltage). In CHANNEL Class 'B' Depletion-Mode MOSFET Figure 4 Gate control for the MOSFET differs from that of the JFET. A Class B depletion-mode MOSFET, shown in Figure 4, may be compared with a Class C enhancement-mode MOSFET shown earlier in Figure 2. Note in the Class B MOSFET there is a channel connecting 1·2 the source and drain. Although gate control is essentially the same for both, operationally there is a difference. For an n-channel depletion-mode (Class B) MOSFET, a negative potential upon the gate will deplete the electrons within the channel (like charges repel, unlike charges attract), and drain current will be proportional to the gate potential. In fact, the output characteristics of a Class B MOSFET are remarkably similar to those of a Class A JFET as shown in Figure 3. If, however, a positive potential is applied to the gate, free electrons within the p-body will accumulate under the oxide and existing n-channel inverting the p-region. The enlarged n-channel allows additional drain current to flow over and above that current flow at zero bias. Thus, the depletionmode MOSFET takes on the characteristics of an enhancement-mode MOSFET. MOSFETs and MOSPOWER-The Successful Solution Both the Class B (depletion-mode) MOSFET and the Class C (enhancement-mode) MOSFETs shown in Figures 2 and 4, respectively, were originally developed for small signal applications requiring, at most, a few milliamperes of drain current with attendant power requirements of a few hundred milliwatts. There were several interrelated problems inhibiting high-power performance that were eventually solved by the introduction of the vertical double-diffused MOSFET structure. As the reader continues through this handbook, a clearer understanding of MOSPOWER theory, design, construction, and applications will evolve. POWER: Its Definition Used in This Handbook Conversely, the Class C enhancement-mode MOSFET has no current flow until inversion occurs. Consequently, for an n-channel enhancement-mode MOSFET, a positive gate potential is required. Closer examination of Figure IC shows an offset before conduction which is called the threshold voltage (VT). Before drain current flows (before inversion), an electric field must be established closely dependent upon such variables as the thickness of the gate insulation (silicon dioxide), the doping of the body (which, in turn, controls the availability of free electrons), and the gate material itself-whether metal or polysilicon. Threshold voltages generally lie between 1 and 6 volts. World-wide, the semiconductor industry has established a 1 watt power dissipation to set apart smallsignal transistors from power transistors. At the time of this writing (1984), it is premature to establish an upper limit although we can, without embarassment, suggest that the upper limit may not be totally the responsibility of the semiconductor itself but more probably that of the package. Today packages, such as the ubiquitous T03 (TO-204), limit performance to 250 watts. New packages just now emerging show promise to 500 watts. 1-3 1.2 A Little History The power MOSFET, as a practical commercial device, has been available since 1976. However, the history and attempts to produce power FETs go back much further. It may come as a surprise, but Shockley, Bardeen, and Brattain were actually trying to fabricate a field-effect transistor when they stumbledyes, stumbled-upon the bipolar transistor. Actually the field-effect transistor preceded the invention of the bipolar transistor by nearly 20 years! Although some try to contest who actually made the discovery, the U. S. Patent Office credits the invention to Dr. Julius Lilienfeld-the date of his patent? 1930! Unfortunately, the good doctor did not build the field-effect transistor (or FET), for in his day semiconductor material was not sufficiently advanced to be of much use. After Shockley and his crew developed their Nobel-prize winning bipolar transistor, Shockley went on to develop the FET. He announced the FET to the world in his classic paper [1] where he offered a general theory of operation and his predictions of performance. FETs were self-defeating and offered excessively high parasitic capacitances for the little gain in performance. Undoubtedly, the breakthrough came in 1959 when a paper authored by Wegener [2] identified the fundamental failing of the classic approach and offered a remarkable solution. Wegener's solution was simplicity itself. He proposed that rather than build planar FETs, we could achieve higher current densities if we built cylindrical junction FETs. Within a few years of this remarkable discovery, a plethora of published papers appeared, scattered through several different technical journals which announced the successful fabrication of moderate-power, field-effect transistors. Notable among these early researchers were Teszner, Zuleeg and Nishizawa [3]. The latter scientist is well-known for his Static Induction Transistor (SIT) which made its commercial entry during the mid1970's in Japan. Unfortunately, their time had not yet come, and little was heard of these power FETs. A few would appear, undergo some preliminary evaluation, possibly attain some publicity, and then quickly fade into oblivion. Part of the problem was the difficulty in manufacture and the problem of needing two power sources-one for drain voltage and the other for gate voltage (they were depletion mode devices). Finally, without support engineering, they simply never caught on. Consequently, although occasionally discussed, power FETs remained dormant until 1976. But Shockley's work was still 20 years from the introduction of a successful power FET although he was very close to the eventual understanding of what it would take to build a power FET. Many followed Dr. Shockley, making numerous experimental devices and hoping for power, but they all failed-and they all failed for the same reason. The path these unsuccessful experimenters followed was generally to parallel many cells. What they disregarded, forgot or tossed off as inconsequential was that paralleling for additional current handling may drop the channel resistance, but the parasitic elements increase at a higher ratio. As a consequence, these early power In 1976, Siliconix announced the world's first commercially-available power MOSFET in volume production with the registered name MOSPOWER. 14 Nearly simultaneously with this announcement by Siliconix, Hitachi of Japan announced the availability of complementary pairs of power MOSFETs ... and the race was on. Unlike previous attempts at achieving power, these devices were first, MOSFETsMetal Oxide Semiconductor Field-Effect Transistors-and second, they utilized a novel technology called double-diffusion, which will be further explained in a later chapter. GATE CHANNEL LENGTH The first Siliconix power MOSFET was of novel vertical construction, utilizing a four-level semiconductor process and an easily identifiable anisotropicetched V-groove shown in Figure 1. Hitachi, on the other hand, followed the classic planar design with source, gate, and drain accessible on the top surface ofthechip. SOURCE GATE SOURCE GATE DRAIN Planar Vertical Double-Diffused Power MOSFET Figure 2 It is important for the reader to note that despite the various trade names (TMOS, HEXFET, SIPMOS), the basic operation and construction of the power MOSFET are, for all practical intent, identical. SOURCE References 1, f I--------==--------j [1] Shockley, W., "The Unipolar 'Field Effect' Transis- tor," Proc. IRE 40 November 1952) pp. 1365-76. [2] Wegener, H.A.R., "The Cylindrical Field-Effect Transistor," IEEE Trans. Electron Devices, Volume 6 1959, pp. 442-449. CHANNEL '" _ , _ SUBSTRATE n+ LENGTH SIN 53° DRAIN [3] Teszner, S. and R. Giquel, "Gridistor-A New Field-Effect Device," Proc. IEEE 52 (1964) V-GROOVE DMOS Figure 1 pp. 1502-13. As the power MOSFET technology improved and competitors appeared, the technology evolved into what is now the standard-a vertical, planar fourlayer semiconductor process commonly called DMOS or double-diffused MOS, shown in Figure 2. [4] Zuleeg, R., "Multi-Channel Field-Effect Transistor Theory and Experiment," Solid State Electronics 10 (1967) pp. 559-76. 1-5 1.3 Fundamental Limitations of Power MOS Transistor Performance The goal of power MOS transistor suppliers is to produce devices with the best performance and the lowest manufacturing cost When die manufacture alone is considered (i. e., the cost of assembly and test are ignored) this goal becomes the production of devices with the lowest on-resistance per unit area for a given breakdown voltage. While one might conclude that this statement is obvious, the method for obtaining this performance is not. There are many practical considerations to be made before the "optimum" design for even a single voltage is obtained Various engineering approaches have led to a large number of device designs in the growing power MOS transistor field. Before discussing the practical issues faced when optimizing device performance, it is appropriate to identify the theoretical maximum performance per unit area as a standard against which various manufacturer's devices can be measured. This limit, shown in Figure 1, is obtained when the product of the resistance of a block of silicon and its surface area are plotted as a fraction of its breakdown voltage. This "normalization procedure" assumes that 100 percent of the surface of the silicon is injecting carriers and that 100 percent of the theoretical breakdown voltage ofthe silicon is obtained. Both ofthese assumptions can never be achieved in real devices, but it is possible to obtain accurate estimates of the limits imposed by practical considerations. The utilization of the transistor chip surface may be examined in two steps. First, the percentage of the surface area available for the active device is determined. The relationship between the chip area and ,00 i ~ 10-2 I "m 10-3 c 10-4 '0-5 L--L...J....J...J..J..I..u.L_L.......L....I....L.LJ..U":--'--'-'....I....Lu.J.I 101 103 104 BREAKDOWN VOLTAGE (BVossI, (VOLTS) The Theoretical Limit of MOS Power Transistor Performance [1] Figure 1 the potential active chip area may be derived from knowledge of the width of the region at the perimeter of the chip required for device termination, the number and size of the bonding pads, and the spacings and tolerances required for the active area. improved by another 5 to 7 percent over the utilization factor shown in Figure 2. A graph of this relationship consists of the three regions outlined below for a device with source and gate bonding pads on the surface. Region I: The chip size is dominated by the need for the two bonding pads placed far enough apart to allow for bonding. Region II: Minimum size bonding pads and minimum conductor widths are sufficient for the current densities involved. The surface geometry and layout dimensions chosen by a device manufacturer also impacts the device efficiency. The surface geometry requires optimization to obtain the greatest amount of injecting source perimeter per unit area. Figure 3 compares the layout efficiency of various surface geometries. While the geometries differ in efficiency by only a few percent, the "square-on-hex" pattern is most efficient. The width of the gate region must also be optimized. Region III: The current density increases to a level that requires either greater than minimum conductor widths and bonding pad sizes. Figure 4 shows the cross section of a contemporary MOSPOWER transistor. If the gate width is too large, surface utilization is poor; while if it is too small, the JFET formed by the body region results in an increase in device resistance. Optimum gate width is a function of the resistivity of the drain region and decreases as the voltage rating of the device decreases. Figure 2 shows the percentage utilization versus chip area for MOSPOWER transistors with two bonding pads and a nominal width for the region at the edge of the chip. For a chip 20 mils on a side (500 /Lm on a side), the surface utilization is below 40 percent, but rises rapidly to approximately 80 percent for a chip 40 mils on a side. If a manufacturer chooses to eliminate the area of the chip dedicated to the source pad and to "bond over active area," the chip utilization is The voltage rating of the MOSPOWER transistor also sets limits on device performance. At high voltages, devices are designed to obtain a breakdown SOURCE AND BODY GATE I ~REGIONI 100 II LREGION II I aD 60 ~ _ _ e __ • ~REGIONI""'------~====~ ..... l I 40 ~CELL SIZE------'I N- DRAIN 20 oL-_ _ o ~ _ _ _-L_ _ _-L_ _ _ 1 x 107 2 x 107 3 x 107 N+ ~ » 4 x 107 CHIP AREA (/-'m2) DRAIN Surface Utilization vs. Chip Area for MOS Power Transistors Figure 2 LINEAR GEOMETRY SOURCE GEOMETRY AND GRID UNIT CELL Illllill Cross Section of a Power MOS Transistor Figure 4 SQUARE ON CIACLE ON HEXAGON ON saUARE GRID SQUARE SQUARE GRID GRID SQUARE ON HEXAGONAL. GRID CIRCLE ON HEXAGONAL GRID DOD 000 000 q-p Q-P Orol0 oic)10 oi61 0 [(0'0 0[0 10 L_J 0-6 DOD 000 000 0-6 ~-~ l.r--·'! r--,! S 8 NOT APPLICABLE 10 : ! IDI :0: I I , f--Jl L--.Jl --151- r--·,j :O~s ! ~--i 51 <{ Ds) L--.Jl aT\ '--- f' HEXAGONAL GRID ~-9 o!o~o /--i,. 0-0 r--i \--f \~--f 09523 10 L_~ ..... S+a--+i I I I I I HEXAGON ON ( OS) (OS) COEFFICIENT G FOR CELLULAR GEOMETRIES 08862 09306 10146 The Efficiency of Various MOS Power Transistor Surface Geometries [2] Figure 3 \-7 , ,, ,00 voltage close to the theoretical minimum value set by the silicon. As the voltage is increased, it becomes difficult to obtain greater than 80 percent of the theoretical maximum. As the voltage rating decreases, another limit is encountered. The decrease in gate width and other device dimensions cannot continue indefinitely as the voltage rating decreases. The requirements for low resistance ohmic contacts to the source and body regions set a minimum source and body contact dimension, while the lateral diffusion of the body region beneath the gate sets another minimum dimension. These minimum dimensions establish a limit for low voltage devices. I ,. 10-1 4 3•• , 5. I •• e. 2., I I , I I 7. •• 1 2 3 4 5 6 7 8 9 10 11 12 When all of the limits discussed in this section are imposed on a power MOS transistor, the "practical limit" of Figure 5 results. This figure accounts for all of the overhead requirements for edge terminations, bonding pads, device dimensions, surface efficiencies, and voltage effects discussed. (This figure assumes an 85 percent surface utilization value.) The performance of various contemporary devices are also included on this figure for information. IRF308 GEVMOS GEVMOS 1ft HEXMOS SlUCONIX VN64GA SlLICONIX VN1200A SIUCONIX SYH IR HEXMOS AEG SlPMOS GEDMOS SILICONIX VNDK '0-5 "--'--'--''-'--'..LU.''--'--'-L...U-'-LIJ':--,--,-",-,-,.u.U 101 103 BREAKDOWN VOLTAGE (BVass). (YOLTS) References [1] Adler, M.S. and S.R. Westbrook, "Power Semiconductor Switching Devices - A Comparison Based on Inductive Switching," IEEE Transactions on Electron Devices, ED-29, No.6, June 1982, pp. 947952. [2] Chi, M. and C. Hu, "Some Issues on Power MOSFETs," PESC Record, June 1982, p. 392. . Theoretical MOS Power Transistor Performance Showing the Practical Limit [1] Figure 5 1-8 104 o Power MOSFET Structures _ _ Chapter 2 Power MOSFET Structures 2.1 Principles of MOSFET Operation One of the attractive features of MOSFETs is the ease with which the basic principles of operation can be understood. In many ways, the MOSFET is a solid state equivalent to a vacuum tube and, at least for first order behavior, is as easy to understand. (a) GATE s, .. A simplified model will be used to explain how a MOSFET works. The model chosen does not represent how practical devices are actually built, but it does operate in the same manner and makes the explanation easier. This discussion will address an n channel device. A p channel device would be just the opposite, with n and p regions interchanged. The basic operation is, however, still the same. p BODY (e) Figure la shows an npn junction structure. In many ways, this structure is identical to a bipolar junction transistor; the differences arise from the connections made to this basic structure. As shown in Figure lb, for a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), three ohmic contacts and an insulated capacitor plate are added to the npn structure. As long as the potential between body and gate is not positive, this device is essentially two diodes back-toback (Figure lc), and only a small junction leakage current will flow if a + or - potential is applied between the n region ohmic contacts. In this state, the device is OFF. s/D~./D • n-Channel MOSFET Structure Figure 1 to the gate structure, as shown in Figure 2a. Due to the presence of the gate oxide insulator, the gate metal and the body semiconductor form a capacitor which accumulates charge. Even if the potential between the gate and body is small (O-3V), the electron density in the body side of the capacitor will be less than the hole density and the device acts like two diodes back-to-back with a moderate increase in leakage current. The p region is doped so that there are more holes than electrons. This is, by definition, what makes it a p region. Even though the holes outnumber the electrons, there are still plenty of free electrons in the p region, and if the gate is made positive with respect to the body, some of these electrons will be attracted As the gate to body potential is increased, however, the charge density in the body, immediately adjacent to the gate oxide, will increase to the point where the electron density exceeds the hole density, and a 2-1 l1li portion of the body region (the channel) inverts to become n rather than p. This is shown in Figure 2b. The semiconductor structure is now n-n-n and has become simply a silicon resistor through which current can flow easily in either direction (Figure 2c). This is a variable resistor in which the resistance of the channel is controlled by the potential from gate to body. RDS(ON) ___________ I ~ U '''___......_--.J ~ vas (a) (b) SID SID SID At low values of drain-source voltage (VDS), the MOSFET, when turned ON, acts much like a normal resistor. However, as VDS is increased, RnS(on) becomes a function of VDS as illustrated in Figure 4. For high values of VDS (> 10-20 V), the MOSFET is no longer a resistor but acts as a very good current source if the gate-body voltage (VGS) is fixed. The transition from resistor to current source will depend on VGS, as indicated. The actual behavior in the resistor region will vary depending on the design compromises adapted for a particular device. SID .. (c) MOSFET TUrn-On Characteristic Figure 3 SID lOS .. <>o-----~-----oo NORMAL RESISTOR SID YGS3 > YGS2 > VOS1 RDS(ON) Channel MOSFET In the "ON" State Figure 2 ~-------------~u There is a limit to the minimum resistance of the channel. As the gate-body potential is increased, more charge collects in the channel region. This charge acts like an electrostatic shield to reduce the field in the rest of the body. This action very closely resembles the effect of space charge in a vacuum tube which acts to reduce the electron emission from the cathode. In a MOSFET, this "space charge" acts to limit the additional charge in the channel so that the channel resistance quickly reaches its minimum value. t 9 ~-------------~u ~-------------VGS1 Vos_ This charge scenario can be used to explain the RDS(on) versus VGS characteristic shown in Figure 3 which is typical of all power MOSFETs. Region I corresponds to the condition when the accumulative charge is not sufficient to cause an inversion. Region II corresponds to the condition where sufficient charge is present to invert a portion of the p region, forming the channel, but not enough that the "space charge" effect is important. Region III corresponds to the charge limited condition where RDS(on) does not change appreciably as the gate-body potential is raised. Comparison Between a MOSFET and a Normal Resistor Figure 4 For example, some power MOSFETs have a linear RnS(on)NDS 'curve, like a normal resistor. Other designs, where a minimum RnS(on) at low Vns is desired, will have a curved charactenstic as indicated by the dashed line in Figure 4. Both of these effects are caused by a narrowing or "pinch off" of the channel as Vns is increased. Figure 5 illustrates the channel narrowing or pinch off. 2·2 The body-source connection places a short between the base and the emitter of the parasitic npn BJT as shown in Figure 6b. The base-collector junction is, however, still present so that the equivalent circuit for the MOSFET is a MOSFET in parallel with a diode as shown in Figure 6c. For most applications, this equivalent circuit is adequate, but in some cases, a more accurate model is needed. Inherent in the structure of the MOSFET are parasitic resistances and capacitances. These parasitic elements are shown in Figure 7a and the equivalent circuit in Figure 7b. Channel Plnchoff In a MOSFET Figure 5 For a variety of reasons, a practical power MOSFET does not have four terminals. The normal practice is to connect the body directly to one of the n regions as shown in Figure 6a. When this is done, the n region to which the body is connected is defined to be the source connection. The other n region becomes the drain connection. To turn the device ON, the gate is made positive with respect to the source. G RG eg. Cg_ ~ c~ 0-n _T_ 51 . . T (a) egb p Rb i~ f--o n G ,~·ti±] (b) oo-_vv-.......-H Rb (b) Parasitic Elements Present In a MOSFET Figure 7 (c) The effect of these parasitic elements on the device and circuit behavior is discussed in Sections 2.2,3.1, 3.2,5.4, and 5.5. The Body Diode In a MOSFET Figure 6 2-3 2.2 FETs and BJTs as Charge-Controlled Devices "Field-effect transistors are voltage-controlled devices, and bipolar junction transistors are currentcontrolled devices." However, it will be seen that this difference is of only secondary importance in both switching and analog amplifier applications. The implication of these familiar statements is that FETs and BITs are fundamentally different, and must therefore be incorporated differently into a circuit environment. To the contrary, the point made in this introductory chapter is that both device types are fundamentally the same, in that they are chargecontrolled. This point of view is particularly useful with respect to switching (digital) applications, and even more important for high-power switching applications such as switched-mode power conversion. The main conclusion is that, as switches, FETs must be driven just as "hard", both ON and OFF, as BITs in order to achieve comparable switching speeds. The Principle of Charge-Controlled Devices Current is rate of flow of charge, expressed in the basic relation current = charge x rate of flow Therefore, for a current to exist, there must be: 1. charge present capable of moving 2. a controlling quantity to make the charge move In the simple device represented in Fig. I, there is a "channel" terminated at two contacts by which the device may be connected through a switch to an external circuit containing an emf potentially capable of controlling the circuit current. If the channel is an insulator, there is no mobile charge available, so no current flows even though there is a controlling quantity available when the switch is closed. In the broad sense of this chapter, all low-frequency electronic devices are charge-controlled, including that old-fashioned device, the TUBE. The term "lowfrequency" here means that "transit-time" devices, such as the travelling-wave amplifier and the klystron, are excluded. There are, of course, many differences between the various types of charge-controlled devices, differences which are of greater or lesser importance depending upon the application, and most of the balance of this book is concerned with these differences. Only one of these will be discussed in this chapter, namely, the requirement for a steady state input current in order to maintain an ACTIVE or ON condition in the BJT; the absence of this requirement in the FET is the principal reason why the FET is commonly thought to be fundamentally different from the BIT. If the channel is a conductor or an n-type semicon- ductor, as represented in the corresponding structure of Fig. 2, there are two types of charge originally present: positive charge on the crystal lattice ions, and negative electron charge. The channel is electrically neutral, and the total negative charge equals the total positive charge. When the external circuit switch is closed, the emf sets up an electric field in the channel which exerts a force on both charge types. However, only the 24 / controlling quantity is applied. The essence of a threeterminal active device such as the FET or the BJT is the separation of control and collection functions so that control is exercised at an input terminal and the resulting controlled current is collected at an output terminal. ZER OCURRENT'i7 CLOSED SWITCH { The FET NO CHARGE, THEREFORE NO CURRENT ( Consider again the device of Fig. I containing the insulating channel. How can mobile charge be introduced into the channel? That is, how can the device be converted into an electronically operated switch in which current collected from the channel can be controlled by a third terminal? __ L.... ( \ Charge can be induced in a previously insulating channel by induction across a dielectric. Suppose such a dielectric is introduced in a layer between a third (control) terminal and the side of the channel, as in Fig. 3(a). The control terminal, the dielectric, and the channel connected to the lower terminal constitute a capacitance: if a positive charge Q+ is inserted at the control terminal, an equal negative charge Q- is induced in the channel on the other side of the dielectric. This negative charge is capable of carrying current, so that if a positive potential is applied to the upper channel terminal by closing the output circuit switch, a current flows as in Fig. 3(b). This is the principle of the FET, in which the control terminal is designated the gate, and the lower and upper channel terminals are the source and drain, respectively. A channel containing no lJIobile carriers (an Insulator) can carry no current Figure 1 CURRENT FLOWS -----. CONTROL AND COLLECTION AT SAME TERMINr-AL_ _ ",,=-_--. FIXED posnVE CHARGE, MOBILE NEGATIVE CHARGE, THEREFORE CURRENT CAN FLOW I ELECTRON Ft.OW Quantitatively, the device turn-on process from the OFF into the ACTIVE mode is as follows. A charge Q+ is placed on the gate by an input current lin = dQ+ Idt; the gate-channel capacitance is thereby charged up and an equal and opposite charge Q- = - Q+ of electrons is induced in the channel. If a positive potential is placed on the drain, an output current results that is given by lout = - Q- ITt, where Q- is the charge in transit, and Tt is the mean transit time of the charge Q- that is in transit between the source and drain. A channel containing mobile carriers (a conductor) is able to carry current Figure 2 The most significant features of this process are: (1) To establish mobile charge in the channel, an input transient current (capacitive charging current) is required. (2) After a steady state is established, the controlling charge Q+ remains static (there is no more input current), but the controlled charge Q- is'in continuous motion clockwise around the output circuit, constituting a steady state (DC) output current. Thus, even though the total charge in transit in the channel remains constant at Q-, the individual negative charges are constantly being replaced, entering the channel at the negative electron charge is mobile and capable of carrying current; the positive charge is constrained to the fixed lattice ions. In the diagram of Fig. 2, a (clockwise) flow of electrons results, constituting a counterclockwise steady state (DC) current in which the electrons in the channel may be visualized as moving continuously past the fixed positive charges while retaining the same density distribution; that is, the channel is still essentially electrically neutral. In the two-terminal device of Fig. 2, the controlled current is collected at the same terminal at which the 2·5 - (a) ,I .( INSERTED POSITIVE " " CHARGEQ+ ' .... 8 8 + ~ CONTROL TERMINAL ~ 1- '* + 8 8 8 8 l- ( 8~ + 88 + + 8 dO+ Iln::dt" the mobile charge was made available; in practice, the output potential is usually present before the controlled charge is introduced, and the device itself becomes a (controlled) switch. In this case, the output current rises as the controlling charge is placed on the control terminal: thus, the rise-time Tr of the output current is determined by how fast the controlling charge Q+ is applied, that is, by the magnitude of the input current lin = dQ+ /dt. Therefore, to tum the device on fast, a large input charging current is needed. + e + ee + INDUCED NEGAnYe CHARGE (ELECTRONS) Q- = -Q+, CAPABLE OF CARRYING CURRENT -- ) An equivalent circuit model of the PET and associated input and output current waveforms are shown in Fig. 4. The essential features of this charge-control representation are the dependent current generator controlled by the input charge, and the tum-on waveforms showing that the rise time to a given output current is shorter if the required controlling charge is applied faster, requiring a larger transient input current (for a shorter time). DIELECTRIC (b) COLLECTED CURRENT FLOWS lout::: - ~ DRAIN DRAIN COLLECTION TERMINAL ..,_,"----------,!!!!!! CONTROLLED CURRENT Q- ~~ GArEO Q+ "'"'1'1 dt ELECTRON FLOW, GATE lout = -T[ MEAN TRANSIT TIMErt 0+ C>---------------+-------~ SOURCE SOURCE AREA Q+ CONTROL Principle of a charge-controlled device (FET): (a) An insulating channel can have mobile carriers Induced in It by a control charge Inserted at a control (Input) terminal (gate); (b) the Induced channel charge Is capable of carrying (output) current when a potential is applied to the collection terminal (drain). Figure 3 CURRENT '," ____.£-__.1-.1-______________- , . . . . . - _ . . - - , -___ AREA Q+ source and leaving at the drain after a mean transit time Tt. (3) The magnitude of the output current lout = - Q- ITt is determined by the controlling charge Q+ = - Q- . These three statements describe the principle of a charge-controlled device, in which a current in an output circuit is controlled by the charge placed on a control terminal. Basic equivalent circuit model of a charge-controlled device (FET). The same control charge inserted or extracted over a shorter time lowers the rise or fall time, respectively. Figure 4 A steady state, or DC, output current continues to flow as long as the controlling charge remains (statically) at the control terminal. Equally important as tum-on is the reverse, tum-off, requirement: to For clarity in the above explanation of the control and collection functions, the potential at the output terminal was asssumed to be applied by a switch after 2-6 I stop the output current, the controlling charge must be extracted, requiring a reverse gate current. To turn the device off fast, which means a short fall time 7f, the controlling charge must be withdrawn fast, requiring a large gate extraction current lin = - dQ+ Idt. The turn-off waveforms are also shown in Fig. 4. (a) INSERTED POSITIVE CHARGE Q+ (HOLES) The essential charge-control quantitative relations may be summarized as: CONTROL TERMINAL dO+ Iln""di lin = dQ+ dt lout = (b) The charge-control model represented by Fig. 4 emphasizes that, to realize the potential fast speed of the PET, the gate drive source must be low impedance and capable of both supplying and sinking the required transient insertion and extraction control charge currents. COLLECTED CURRENT FLOWS lout = COLLECTOR The input capacitance shown in the model of Fig. 4 merely accounts for the fact that a voltage appears at the input: it is a nonlinear capacitance, and so the input voltage is a nonlinear function of the control charge. However, the charge-control description of the device operation makes it clear that it is the input charge that does the work, and the input voltage is of strictly secondary importance. BASE -~ COLLECTION TERMINAL r ELECTRON FLOW, MEAN TRANSIT TIME 7t IIIF.JI The BJT The charge-control description of the BJT almost exactly parallels that of the FET, with appropriate change of terminology. Principle of a charge-controlled device (BJT): (a) Insertion of control charge (holes) at the base terminal induces injection of electrons into the base region (channel) from the emitter; (b) the induced electron base charge is capable of carrying (output) current when a potential is applied to the collection terminal (collector). Figure 5 In an npn junction transistor, the channel is the base p region, and the lower and upper contacts are the emitter and collector n regions, respectively. A conducting contact on the side of the base region becomes the third, control terminal, as shown in Fig. 5(a). The most significant features of the BJT are identical with those of the PET: (1) To establish mobile charge in the base, an input transient current lin = dQ+ Idt is required. (2) After a steady state is established, the controlling charge Q+ remains static, but the controlled charge Q- is in continuous motion around the output circuit constituting a steady state DC output current. Thus, even though the total charge in transit in the base remains constant at Q- , the individual negative charges are constantly being replaced. An input current lin = dQ+ Idt introduces positive charge (holes) into the base region, which induces an equal negative charge Q- of electrons to be injected into the base region from the emitter. This negative charge is capable of carrying current so that, if a positive potential is applied to the collector terminal, an output current lout = - Q-Irt flows where, again, Q- = - Q+ is the total charge in transit through the base region, and 7t is the mean transit time between emitter and collector. 2-7 (3) The magnitude of the output current lout = -Q-1Tt is determined by the controlling charge Q+ = - Q- . COLLECTOR Also, if the collector potential is previously present, the collector current rises as fast as the controlling charge is introduced into the base input terminal, so again a large input current lin = dQ+ /dt is necessary to achieve fast turn-on. Similarly, fast turn-off requires a fast extraction of the control charge by a large negative input current lin = -dQ+ /dt. I,n BASE 0-_.--.....---.., CONTROLLED CURRENT Q- Q+ lout=--=- " " So far, the properties of the BIT are seen to be identical to those of the FET, and so the same chargecontrol model and associated input and output current waveforms as in Fig. 4 are applicable. There is, however, one difference in the physical device structure that leads to an additional effect. EMITTER CONTROL CURRENT lin In the FET, the controlling charge Q+ and the (equal) controlled charge Q- remain separated on opposite sides of the gate dielectric. In the BJT, on the other hand, the controlling and controlled charges occupy the same physical volume, namely, the base region; nevertheless, the one-to-one ratio still exists, and again the resulting base-emitter voltage is (nonlinearly) related to the control charge Q+ by the diffusion or storage capacitance that replaces the gate-channel capacitance of the FET in Fig. 4. - a- =~ CONTROLLED CURRENT lout The presence of positive charge (holes) and negative charge (electrons) in excess of their eqUilibrium concentrations, in the same physical volume, leads to a gradual loss of both by the process of recombination. Therefore, after a BIT is turned on, the collected (output) current gradually decays back to zero as the controlling and controlled charges are lost to recombination. '. / " Basic equivalent circuit model of a charge-controlled device (BJT). A maintenance DC base current 10ut/,8 is required to make up for the hol_lectron recombination loss of the stored charge. Figure 6 The essential charge control quantitative relations are correspondingly augmented to become lin = dQ+ +~+ dt T Conversely, if the collected current is to be prevented from decaying, the recombination charge loss must be replaced: thus, a steady state (DC) maintenance control current must be provided to keep feeding in control charge Q+ at the same rate that it is lost by recombination. This loss rate is Q+ IT, where T is the mean lifetime of the hole-electron pairs in the BIT base region. Q- = -Q+ Q- lout = - - Tt In the steady state condition in the ACTIVE region, only the DC maintenance component of the input current remains, and the ratio of the DC output to DC input current is To account for recombination loss, the charge-control model and associated current waveforms of Fig. 4 may be augmented, as in Fig. 6, to represent an additional feature of the BIT: (4) To maintain the original DC output current at turn-on, a maintenance input DC current must be provided, represented in the model by the current through a resistance in parallel with the storage capacitance. I lout T = == f3 or hFE lin DC Tt - 2·8 where {3 and hFE are the familiar symbols for the "current gain" of the BJT. at which all the induced charge can be collected, the device is being overdriven and excess or uncollected charge is present in the channel. The waveforms are shown in Fig. 7, in which the saturated ON condition replaces the final ACTIVE condition as a result of input current being present beyond the time needed for saturation. It is clear that from a switching point of view the FET and the BJT are identical in principle. Both are charge-controlled devices whose input is capacitive, and to make the device operate fast the input capacitance must be charged and discharged fast, that is, the drive must be capable of sourcing and sinking sufficiently large transient currents. In contrast, the most obvious difference between the BJT and the FET, the presence of DC input current in the BJT, is irrelevant as far as the switching properties are concerned. It may be noted that the same conclusion applies to the BJT operated as an analog amplifier: for high frequencies the input admittance is dominated by the diffusion susceptance, and the {3 is irrelevant; only for low frequencies, down to and including the DC bias conditions, is the input admittance dominated by the {3-determined conductance. From this viewpoint, an "ideal" BJT would have an infinite {3, as essentially does the FET. lout CHARGE·CONTROLLED DEVICE (FET OR BJT) INPUT CURRENT '" Charge-Controlled Devices as Digital or Power Switches All the above discussion has been related to how a charge-controlled device is driven from the OFF to the ACTIVE region, and back, in order to emphasize the underlying simplicity of the device nature. In practice, when operated as a switch, either in digital signal processing or in switched-mode power processing applications, the device is driven from OFF through the ACTIVE to the ON or saturated condition, when additional effects come into play. Nevertheless, the charge control description continues to be useful and, qualitatively at least, the additional effects can be accounted for by superposition. OUTPUT CURRENT lout OUTPUT VOLTAGE Charge-controlled device operated as a switch: overdrive is needed to cause output saturation, resulting in excess stored charge that must be withdrawn before the switch begins to turn off (causing the storage time). Figure 7 When a device is used as a switch, the initial tumon phase is the same as already described: when the collection potential is already present on the output terminal, the channel charge Q- begins contributing output current as the input current lin = dQ+ Idt induces the corresponding charge - Q- = Q+. A load carrying the output current causes the output terminal collection potential to fall. If this potential remains high enough to continue to collect all of the channel charge after the input current ceases, the device is turned on into the ACTIVE region as already discussed. In the saturated ON condition, the channel contains two components of charge: the charge necessary to contribute the saturated output current as if the device were in the ACTIVE condition, plus the excess charge. From a practical point of view, there must always be some margin of excess charge to ensure that saturation is maintained, and also, the larger the excess charge the smaller is the saturation voltage drop along the channel, which is a desirable circuit property in the ON condition. If the device is a BJT, there must be a suitable steady state input current to maintain not only the active but also a suitable excess channel charge. However, if the output terminal potential falls sufficiently low that it ceases to collect all the induced channel charge before the input current ceases, then the saturated ON condition results in which the output current is limited to a value determined by the output circuit. Since input current continues beyond the point When a charge-controlled device is to be turned OFF, a qualitatively new effect occurs when the initial condition is saturated. As also shown in Fig. 7, the tum- 2-9 l1li off input current must first extract the excess charge before the output current begins to fall. This interval is known as the storage time TS, familiar in BJT devices, and the greater the excess charge the longer the storage time for a given tum-off input current. However, a quantity analogous to storage time also exists in FETs, although quantitatively it is much shorter than in BITs because the excess charge is much smaller. Nevertheless, it is notable that even this (charge-control) property is qualitatively the same in both FETs and BJTs. ON voltage drop (large excess charge) and short storage time (small excess charge). "Proportional base drive," in which the ON maintenance base current is made proportional to the output current (by a positive feedback transformer connection) is often used to alleviate this conflict. The FET is "easier" to drive than the BJT, not because one is "voltage-controlled" and the other "current-controlled", but because in the FET a maintenance ON gate current is not required, and the "storage time" is much smaller, so the design tradeoff between ON drop and storage time is essentially eliminated without the need for proportional drive. Basically, the FET and BIT are both charge-controlled, and both must be driven from a low-impedance source capable of both sourcing and sinking sufficient current to provide the desired tum-on and tum-off times. Optimization of base drive circuits for BJTs involves choice of suitable tradeoffs between the three conditions tum-on, saturation, and tum-off. The prime consideration is, of course, fast insertion and extraction of the controlling charge to obtain fast rise and fall times. However, a compromise must be found between the conflicting requirements of low saturation 2-10 2.2.1 Charge Transfer Characteristics Introduction Casual readers might question beginning the study of hybrid power FET circuits by examining the charge transfer characteristics. Indeed, some readers unfamiliar with power FETs might erroneously believe that no energy, ergo no charge, is needed to operate a power FET. Furthermore, these same readers might anticipate that the coupling of a high gate impedance power FET to a bipolar transistor or thyristor would obviate any need for an intermediate power driver other than, perhaps, a level shifter. Under some conditions, these might be proper assumptions, but first examine exactly how to turn ON a power FET. Surprisingly, it is similar to that of a bipolar transistor since both the power FET and the power bipolar transistor are charge-coupled devices! to rise (more positively for an n-channel MOSFET and more negatively for a p-channel MOSFET), two events begin: As the gate potential rises, channel inversion begins (see Figure 1), and the input capacitor, Cgs , begins to charge. In reality, the second event preceaes the first; the order is reversed here for emphasis since the first event is recognized without explanation. The current necessary to charge this input capacitor is computed using the following _ equation. :::=:;;kz~~~~~~:::O:X:'D~' Although the power FET and the power bipolar transistor are both charge-coupled devices, much of the similarity stops there. Operation of a power bipolar transistor is principally concerned with current gain whereas the power FET is, in effect, a voltage-controlled current source. If, indeed, this is true then how can a power FET be called a chargecoupled transistor? INVERSION LAYER ega'" ega + Can + ,PI - - n+ - SUBSTRATE DRAIN n- CHANNEL Positive Gate Bias Inserts the p-Reglon Immediately Beneath the Oxide to Effect Majority-Carrier Current Flow Figure 1 The answer lies in the way a power FET is turned ON. More properly it is identified as an enhancementmode MOSFET. This section concentrates on the operation of an n-channel, enhancement-mode power MOSFET remembering that the p-channel enhancement-mode power MOSFET obeys all the same laws but in complement. Any enhancement-mode MOSFET requires a finite gate voltage before conduction occurs. The level at which it conducts is called the threshold voltage, VT. As the gate voltage begins iN Cilt where, ilv is the gate-to-source voltage, Vgs ilt is the rise time of the incoming signal C is the input capacitance, Cgs , prior to turn-ON. 2-11 (1) but 400 Q= cav I ~ (2) / 2 ~ :;:: ~- rffl so combining Equations (1) and (2) yields .-~ - - - I ~ "' Q = iat / (3) -j I- V. ' What is unique about equation (3) is that it is easily measured! However, before looking into the mechanics of how to measure charge, note that the discussion up to this point only involves the gate charge prior to turn-ON [see equation (1)]. The entire switching cycle must be examined. The portion thus far is known as the subthreshold region. 12 vGG 10 I VDS where, Q is the charge necessary to raise the gate to Vgs. V " ,.-c-- r-.. / v •• 02;----=r- 3 I II 0, II 5 .~ ,,~ ~O% 10 15 20 25 C(pe) Gate Charge Characteristics Showing the 3 Regions Figure 3 (a) The Dynamic Characteristics of Gate Charge (a.l) Driving the power MOSFET into Conduction Up to this point, the power MOSFET is OFF. The input capacitor, Cgs , has a charge, Q, so the voltage across this capacitor is equal to the threshold voltage, VT, of the MOSFET. At this point, it might seem that only a small additional charge is necessary to drive the power MOSFET into action, that is, into conduction. When this occurs, the MOSFET is in the dynamic region-the transition region that demands attention. In Figure 3, the complete charge-transfer characteristics of a typical vertical planar double-diffused (VDMOS) MOSFET, region 1 is the area previously discussed, the sub-threshold region. Tho very noticeable events occur in region 2. First, in time, the drain-to-source voltage begins to drop; second, what appears to be an incredible increase in input capacity, Cgs , occurs as the fast-rising gate potential apparently stalls [see equation (2)]. What is happening is simply the Miller effect brought about through the interaction of the feedback, or gate-todrain capacitance, Cgd (more commonly recognized in FET terminology as Reverse Transfer Capacitance, Crss), and the common-source forward voltage gain, AV· Generally, whenever power MOSFETs are used as switches, they operate in what is commonly called the common-source mode as shown in Figure 2. As this transition region is entered, the charge characteristics are greatly altered by a phenomenon called the Miller effect. Cin = Cgs + Cgd(1 - A V) (4) +VDD where AV = ilVds ilVgs Remember that the quantity, ilV ds, is, for an n-channel MOSFET, a negative value, and for a p-channel MOSFET, the quantity, V gs, is a negative value. Thus in either case, this equation is calculated as (1 + voltage gain). 1----0 OUT Thus, either considerably more time is needed (assuming that the charging current, i, is a constant), or, to keep time, ilt, a constant considerably more current is needed. One thing must be kept in mind: the execution of equation (4) is not easy! If the charge-transfer characteristics for the particular Common-Source Configuration. Source Is "Common" Both to Input Circuit as Well as Output Circuit Figure 2 2-12 Next the Miller effect must be considered: the apparent flattening of the charging cycle. Since the calculation of input capacitance is, from equation (2), merely the slope of the charge curve, it appears to be a tremendous increase in input capacity. Fortunately, equation (4) can be bypassed; Cin is easily determined by an obvious extension of equation (2). power MOSFET are available, use them! Poised to move into the conduction or transient region, first take time to see how to use these charge-transfer characteristics. (a.2) Using the Charge-Thansfer Characteristics It takes a finite charge to energize a capacitor and that charge, 0, can be calculated using equation (2). If ao Cin= av equation (2) is merged with equation (3), a constantcurrent source will provide a linear rate of increasing voltage with time, at, as seen in Figure 4 as well as in region 1 of Figure 3. If the capacitance changes, for example, or if it increases because of the Miller effect then with a fixed charging current, i, the charge time, t, increases. Additionally, the effect of increasing capacitance (Miller effect) upon the voltage, av, can be examined. Where, with a fixed capacitance the rate of change was linear, now there is an abrupt slowing. All of these effects may be seen by careful examination of Figure 3. 02 - 01 (7) Vgs2 - Vgs l This value of Cin obtained from equation (7) equals that value that might have been obtained from equation (4) after a lot of labor. Finally consider the calculation of input capacitance for region 3, and an equation similar to equation (7): 03 - 02 Cin= - - - - Vgs3 - Vgs2 (8) Whether these equations are used to calculate the various input capacities or simply observed from Figure 3, it is clear that Cin of the subthreshold region (region 1) differs from the Cin of region 3-the former being somewhat lower. The reason for this is that capacitances within a power MOSFET-as with any FET-are depletion-field dependent. Being depletion-field dependent, they are voltage dependent as is evident from Figure 5. Since in the subthreshold region a power MOSFET is OFF, the drain voltage is at the rail, but when driven into full conduction, the voltage across the MOSFET is simply its VSAT, at worse only a few volts. +v CONSTANT CURRENT SOURCE A Linear Charging Rate Results When a Capacitor Is Charged from a Constant-Current Source Figure 4 (a.2.1) Calculating Switching Times from Charge Thansfer These charge-transfer characteristics can also be used to determine switching times with remarkable precision. Aside from turn-ON and turn-OFF switching To determine the amount of energy necessary to move a power MOSFET from a normally OFF state to a normally ON state, the difference in charge provides the answer. 1000 C g, W = 1/2 (ao) (aV) (5) ........ Using data extracted directly from Figure 3, we can calculate, with precision, the input capacitance states in all three regions: the subthreshold region (region 1), the turn-ON region (region 2), as well as after V SAT has been passed (region 3). "'" From equation (2) calculate the capacitance in the subthreshold region remembering that at the beginning of our initial tum-ON charge, Vgs = 0, which simply means that aV = aVgs. "" c~ Cgd 10 01 10 10 100 Vos - VOLTS (V) C=~ Vgs Voltage-Dependent Depletion Areas Also Affect DepletionDependent Capacitances, Cds and Cgd Figure 5 (6) 2-13 l1li times, the delay times must be considered. The first delay is that time required for the input capacity to charge to the threshold voltage at which tum-ON begins. In actual practice, tum-ON time (or more properly rise time) is generally specified as that interval between the 90% and 10% rise time, so region 1 really extends a bit further than the threshold voltage and, conversely, region 3 begins at the 10% level. A careful study of Figure 3 shows this quite plainly. The second delay is at tum-OFF when the input capacitor must be discharged to the voltage where the channel begins to revert to the nonconducting state. This latter state is akin to storagetime delay caused, not by minority carriers as might be anticipated with a power bipolar transistor, but by overcharging the input capacitor when the power MOSFET switch was turned-ON. contained in Figure 3, the method used to generate the charge-transfer characteristics must be considered. (a.2.2) Developing the Charge-Transfer Characteristics In Section (a.2), the charge-transfer characteristics were derived by observing the gate voltage with respect to time with a constant-current drive. That, in effect, is how the characteristics shown in Figure 3 are developed. Achieving the drain voltage characteristics involves nothing more than a simple monitor on the drain terminal of the power MOSFET under test. The circuit for this characterization is shown in Figure 6. Although admittedly simple, a few rules must be observed if these will be used to evaluate the charge characteristics. The first rule is to make absolutely sure that the base line-the abscissa-is in easy-todivide integers. If the current source is fractional, for example 4.7 rnA, then the sweep rate should be such that the product (iot) is 5 nC/cm and not 4.5 nC/cm which would occur at a sweep speed of 1 p..slcm. The second rule, which regrettably is often times beyond control, is to seek the largest, most easy to read chart possible to facilitate accurate measurements. A digitized oscilloscope with x and y output ports attached to a suitable recorder would be highly desirable. The third and most obvious rule is to duplicate the switching circuit. That is, simply be careful that the load impedance used in the test circuit (Figure 6) duplicates that which is used in the actual circuit. The final and potentially most important rule is to remember that the data derived from this test provides the turnON charge-transfer characteristics which means-as seen in Section (a.2)-that they only provide turnON delay, rise time, and tum-OFF delay [equations (9), (10), and (11)]. To calculate fall time, a new switching model is needed. There are three equations which can be used with the charge-transfer characteristics as depicted in Figure 3 to determine the three switching times: tum-ON delay, td(on); rise time, tr; and tum-OFF delay, td(off). A fourth, fall t,ime, tf, cannot be calculated using the charge-transfer characteristics of Figure 3, Q1 VGG td( on) = Rgen Qn Vg1 VGG - Vg1 tr = Q2 - Q1 Rgen Qn VGG - Vg1 Vg2 - Vg1 VGG - Vg2 td(off) = Q3 - Q2 VGG Rgen Qn VGG - Vg2 Vg2 (9) (10) (11) where the first two terms within each equation, aQ aVg Rgen, represent the classic RC time constant where Rgen is the driving impedance as' seen from the gate terminal.! (a.2.3) Developing a Switching Model for Fall Time Already many commercially available power MOSFET data sheets include the charge transfer characteristics The correlation of calculated switching time using these equations with that of measured data can be precise if data is taken carefully from the chargetransfer characteristics such as has been done in Figure 3. Before addressing the so-called problem of fall time, tf, and why it cannot be calculated from the data +---+ !Occasionally data sheets with erroneous generator impedance listed with the switching time parameters are discovered. If a data sheet offers a switching time test circuit, check whether the gate shunting resistor is considered in parallel with the generator impedance, viz., the correct value of Rl x R2 R -'--gen - Rl + R2 TO SCOPE INPUT PULSE ..JL CONSTANT CURRENT DKlOE Circuit for Monitoring Charge Transfer Characteristics Figure 6 2-14 1 in graphical form similar to what is shown in Figure 3. Offering such a graph is not particularly difficult for most vendors. For the most part, they can anticipate most turn-ON switching configurations based on such power MOSFET parameters as Breakdown Voltage, BVDSS; ON-Resistance, rDS(on); and Operating Drain Current, ID. When a power MOSFET is turned ON, the action is well defined: the fast-dropping ONresistance eventually crowbars the output capacitance ofthe MOSFET reducing the voltage drop to VSAT. All of this action can be reasonably well-defined on the vendor's data sheet. What he cannot do is to predict turn-OFF since this depends to a large measure on the type and size of the load and whether the load is resistive, reactive, or both. Consequently, the burden of developing a Fall-Time Charge-Transfer Characteristic lies with the end user and not with the supplier. The difference between turn-ON and fall time is shown in Figure 7. Note that this figure is elementary and does not represent a true model of the power MOSFET. The reader is encouraged to review Section 2.13 for specific modeling information. It should be obvious to the reader that to develop a fall time characteristic, the current (charge) must be controlled as it leaves Cgs , in other words, as the input capacitor is discharged. The circuit might look much like that in Figure 8. This circuit, however, presents a very fundamental problem: how to configure the circuit shown in Figure 6 (the turn-ON charge-transfer characteristics) to that shown here (the turn-OFF charge-transfer characteristics). The solution is simply to switch between the two using the circuit shown in Figure 9. Instead of a turn-ON charging diode (our constant current source) limiting the current from the pulse generator (Figure 6), the input capacitor of our power MOSFET is charged from a pre-set voltage. An analog switch is used to switch the circuit configuration from that of a turn-ON charging network to a turn-OFF discharging network. The finite ON-resistance inherent in the analog switch is not significant since a constant-current source or load represents a very high resistance. What is important is to have the voltage drop across these constant-current diodesand in particular, the discharge diode-as low as possible to ensure that the gate charge truly drops to as near zero as practical. C"nA:S(O~ VDD LtURCE - Cal TURN-ON 1· J Cd • (b) TURN-oFF During turn-ON (a), Cds begins fully charged and Is discharged through the low rDS(ON) of the MOSFET. However, at turn-OFF Cds begins fully discharged and charges to the rail through the load. Figure 7 Simple Turn·OFF Charge Transfer Circuit Figure 8 +VOD (a.2.4) Developing the Fall-Time Characteristics In Section (a.2.2) and the accompanying Figure 6, the gate of the power MOSFET is charged from a constant-current source. In the initial pre-drive state, prior to any attempt at turning ON the power MOSFET, the input capacitor, Cgs , is uncharged, and the gate voltage is zero. On the other hand, the draingate capacitance, Cgd, has the full drain-gate potential, Vgd, impressed across it. When considering the fall time, quite the opposite is true. The input capacitance, Cgs , is charged-perhaps overcharged-and the gate-arain capacitance, Cgd, rather than having the full drain-gate potential, enters the fall region with a very small potential which is discussed in Section (a.3). ---- I I PULSE IN '''' 5V..JnL TTL I TO SCOPE I r~C_: ! I I I ~V:-ITOSCOPEJ-' 1 DG186 iI I _ NO I ~ ~---~f-! - Automatic Turn-ON, Turn-OFF Charge Transfer Test Circuit Figure 9 2·15 (a.2.5) Calculating the Fall-Time excruciatingly long time that VSAT is finally achieved. The question that needs to be asked is: "Why? What makes this obvious slowdown in turn-ON occur?" Since this slowdown occurs after the measured (and calculated) rise time, the effect and its cause are generally disregarded. The results obtained from testing a power MOSFET in the circuit just described (Figure 9) can provide any of three views depending on how the viewing oscilloscope is synchronized. It can be set to view only the rise-time characteristics with results similar to what was seen earlier in Figure 3, or the fall-time characteristics as shown in Figure 10 can be seen, which, incidentally, also provide the turn-OFF delay, tct(off) , information. In the calculation of tum-OFF delay [equation (11)], data can be extracted from either Figure 3 or Figure 10. A third option would be to view the entire switching cycle: tum-ON delay, rise time, the steady ON state (which, depending upon the test conditions, could also be the tum-OFF delay), and the fall-time. Section (a.2.4) began by discussing the effects of turnON on the various parasitic capacitances paying attention to the rapidly changing voltages impressed across the gate-drain capacitance, Cgd. When the MOSFET is OFF, the voltage impressed across this gate-to-drain capacitor equals the full rail voltage, VDD. But as the MOSFET begins to switch ON, the drain voltage drops along with the impressed voltage across this capacitor. Figure 5 shows that as this drain voltage drops, the capacitance rises dramatically. In fact, as the drain voltage slowly settles toward VSAT, the drain-to-gate voltage, V dg, actually reverses polarity! Where, at the beginning of the rise time there was a drain voltage many times higher than the gate voltage, now the gate voltage is more positive than the drain! Since Figure 5 cannot show the effects of either zero or negative drain voltages, it is necessary to view the effect of this change in polarity on capacitance in Figure 11. '00 vGG I II 1\ \ II ~ v.' I-- I---a, 90% I---- v.' I ./ '''' a~ I ,." :III 11 I L a, Lt !::~ \ V r-r""- \ I::::: 51015202530 Q CHARGE ene) Turn-Off Charge Decay Characteristics Figure 10 '"F33D .,..., I..... ~ VN4000A I' t'- MTM56S With the assistance of the discharge-transfer characteristics provided in Figure 10, it is now possible to calculate the fall-time using the following equation: • 1 Q2- Ql ~ tf = Rgen Qn Vg2 - Vg1 Vg1 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 8 7 8 9 Yoo - DRAIN-YO-GATE VOLTAGE (VOLTS) (12) Gate-Drain Capacitance versus Drain-Gate Voltsge Figure 11 Using these four Equations-(9), (10), (11), and (12)-with the data obtained from Figures 3 and 10, all of the switching times can be calculated quite accurately. During the initial rise time (region 2 of Figure 3) , there is the contribution of a gradually rising gate-todrain capacitance, Cgd, on the Miller effect which, with some difficulty, could have been determined from equation (4). Now after having completed the turn-ON cycle (VDS dropping to within 10% of its original value), the voltage gain, AV, has also dropped (iJVDsliNoS --> 0), but because of the reversal of polarity across the gate-drain capacitor, its capacitance has soared to astounding heights. As a consequence, there is an extended Miller effect and slow decay of the drain-to-souree voltage to VSAT (region 3):- (a.3) Region 3: A Closer Examination In attempting to show how to correlate switching speed with the charge-transfer characteristics of power MOSFETs, an important point was by-passed. By closely examining region 3 of Figure 3, one should question why the power MOSFET, during its turnON cycle, does not turn-ON fully. Not only does it not turn-ON, but the Miller effect holds down the gate voltage build-up. It is only after what amounts to an 2-16 / 2.3 Planar MOS When small signal MOSFETs (such as those found in FM and TV receivers) were in vogue, someone might have asked if they could be used for a higher power than the few milliwatts obtained, and the answer would have been a resounding "No!" The construction of a planar small-signal MOSFET reflects a unique symmetry in that both the drain and source diffusions are, for all practical purposes, identical. What actually differentiates source from drain is the biasing arrangement; the gate is generally biased with respect to the source. The small-signal MOSFET was, in hindsight, simplicity itself. The structure is shown by the n-channel depletion-mode device in Figure 1. If our desire was to turn-ON this MOSFET, a positive gate voltage would accomplish it. When the gate receives a positive charge, the capacitor effect forces an accumulation of electrons to migrate under the oxide. But since there is a p-doped channel beneath this oxide, the migration of electrons effectively inverts this region into what might be termed p-doped. Once inversion occurs, current can flow from source-to-drain since the entire path including both the source and the drain has n-accumulation throughout. Conversely, a negative gate potential depletes the region, enhancing the p-type characteristics of the channel and preventing any current flow aside from any leakage that exists between the pair of back-to-back pn-diodes over which the gate has no control. SOURCE GATE The p-channel MOSFET is the exact inverse of the n-channel version. Where the n-channel MOSFETwas n-doped, the p-channel is p-doped. All that remains identical to the n-channel MOSFET is the oxide, the gate structure, and of course, the metallic contacts to the gate, source, and drain. Operationally it, too, is reversed. Now a negative bias enhances current conduction through the channel. The obvious extension combines n-channel and pchannel MOSFETs on the same substrate into what is popularly known as CMOS (complementary MaS). It is one of the foremost technologies today extending its influence from the fabrication of analog switches to microprocessors. Why the small-signal MOSFET is a small-signal MOSFET and incapable of handling power can be simply explained if the basic equations for current are examined both in the linear region and in the saturation region. DRAIN In the linear region, the drain-to-source current is given by: W [ VDS] IDS = "LJ.IoCOX VDS - -2- VDS 3-5 pm Planar Small-Signal MOSFET Figure 1 2·17 - where: W = device channel width L = device channel length fJ. = electron mobility in the inversion layer Although this restriction was well understood, there were, nonetheless, a few attempts during the 1960's to achieve power by paralleling multiple chips. These attempts failed for many reasons: an incorrect understanding of the contribution of parasitic elements (notably capacitance), improper headers and die attach methods to maintain low thermal resistance, and prohibitive costs. In the saturation region, it is given by: IDS fJ.CoxW (VGS-VT)2 2L = -- In the early 1970's, investigators began in earnest to resolve the conflict of high voltage and current in their efforts to overcome the problem. The novel technology that evolved was called double-diffused MOS which made possible the revolution in discrete power MOSFETs that is occurring today. The ~ndamental problem lies in the single term L, the effective device channel length. If a MOSFET is designed to withstand high voltages, the channel length must be increased to reduce the deleterious effects of the body-drain diode (pn junction) depletion region that, because of the increasing voltage gradient, moves progressively further into the channel region. If the channel length is not increased, punchthrough breakdown results, causing catastrophic destruction of the MOSFET. However, careful inspection of these two equations identifies that current is inversely proportional to L; consequently, increasing the breakdown characteristics reduces the power handling capability! References Richman, Paul, MOS Field-Effect Transistors and Integrated Circuits, New York, John Wiley and Sons, Inc., 1973. Sigg, Hans J., et. aI., "DMOS Transistor for Microwave Applications," IEEE Trans-Electron Devices, Vol. ED19, 1 January 1972, pp. 45-53. 2-18 ,I 2.4 DMOS Double-Diffused MOS Realizing the fundamental limitation of conventional planar MOS-a channel length proportional to breakdown voltage but inversely proportional to current-researchers focused upon a new structure which simultaneously accomplished both high voltage and higher current. During the decade of the 1970's, the literature described progressively advanced designs using this new structure-what became known as the double-diffused MOS. (a) SOURCE GATE SOURCE p+ n+ DRAIN Simultaneous with the progressive development of the double-diffused MOS technology was the evolution of the MOS gate. Previously the gate consisted of a metal overlay on oxide, but this new technology used a layer of polycrystalline silicon as shown in cross-section in Figure 1. Among the advantages offered by this polycrystalline silicon gate structure was the ease in interconnection between cells which now could be done in diffusion rather than by the more awkward techniques of metalization and bonding. A more significant advancement was the "selfaligning" polycrystalline structure that now could be controlled by a mask rather than by using metalization. Consequently, interelectrode capacitances fell, thus affording higher frequency (faster switching) performance for the MOSFET. (b) SOURCE GATE SOURCE Cross-Sectional ComparIson: Metal-Gate (a) vs. Silicon-Gate (b) OM OS Figure 1 doped region followed by a more heavily doped nregion. A typical profile showing this double-diffused structure is shown in Figure 2. The channel length is controlled by careful monitoring and control of the doping levels and the subsequent diffusion cycle which must consider both time and temperature. A double-diffused structure consists of a sequentially introduced set of impurities into the epitaxy that for an n-channel MOSFET consists of first a deep p- 2-19 - GATE CHANNEL LENGTH SOURCE These two differences allow a MOSFET that has both a short channel length and the ability to withstand a high drain potential without fear of punch-through. GATE DMOS transistors exhibit a difference in their drain current-to-gate voltage relationship. With the simple planar MOS structure, a square-law relationship is identified, and in the short-channel DMOS structure, the accelerating field potentials can easily reach values exceeding 104 V/cm. When this occurs, the drain current becomes linearly related to the gate voltage, as given by the equation: DRAIN Planar Vertical Double-Diffused Power MOSFET Figure 2 (1) One obvious difference between the DMOS structure and the conventional planar MOS structure is the channel length, L, determined by the difference between two sequential diffusions. Unlike the conventional planar MOS where the channel length is achieved through the photolithographic process and limited to 4 to 5 f.Lm, the DMOS channel length can be reproducibly controlled to values in the 1 to 2 f.Lm range! Furthermore, as this equation shows, drain current is no longer dependent upon channel length, L. Additionally, we can manipulate equation (1) to show that transconductance, gm, is independent of Vas. dIDS gm = - - = Cox· VSAT (2) dVas Operationally, the DMOS transistor works similarly to the planar MOS. An n-channel enhancement-mode DMOS transistor requires the application of a positive gate potential to cause surface inversion of the p-region. Once the surface has inverted, a conducting channel then bridges the source and drain-drift region allowing conduction to occur. A less obvious difference, but one of paramount importance, is what happens to the pn depletion field that formerly forced the construction of a long channel in the conventional planar MOS. In the DMOS process, the body region (for the n-channel MOSFET, the p-doped area) is more heavily doped than the ndrain (epitaxy) region. Consequently, the depletion field extends further into the drain region than into the body region when a reverse bias is placed across the drain-to-body (np) junction. This not only allows significantly higher voltages to be placed across the junction without forcing a longer channel, it also maintains a fixed threshold voltage with varying drain-to-source potential. This fundamental double-diffused process opened the door for the fabrication of at least three basic highpower MOSFET designs: the V-groove transistor, the lateral DMOS (LDMOS), and the popular vertical DMOS structure (VMOS), usually called DMOS. All of these power MOSFETs perform similarly as we shall now examine. 2-20 2.5 V-Groove MOS The first commercially available power MOSFET had a unique way to achieve the performance goals that the double-diffused MOS was expected to offer. It was, after a fashion, a truly double-diffused transistor despite its somewhat unconventional design. With the conventional double-diffused technology, the channel length was controlled by precise lateral diffusion; however, with V-groove, the control was vertical. It was critical to the performance of the device that a narrow channel be available; as a result, the structure's design began closely resembling the four-layer construction typical of the high-frequency transistor as we see in Figure 1. To gain access to the channel, it was necessary to anisotropic ally etch a groove that, once completed, could have an oxide overlay, and then have the gate metal sputtered. The finished V-groove cross-sectional view is shown in Figure 2. BASE EMlnER SOURCE OXIDE OXIDE II1II DRAIN V-Groove OM OS Power MOSFET Figure 2 SOURCE GATE SOURCE BASE CHANNEL LENGTH OXIDE OXIDE = SIN\30 n+ SUBSTRATE n+ DRAIN V-Groove OMOS Figure 3 COl.LECTOR Bipolar Transistor Figure 1 that this sharp-edged trough made reliable high voltage performance difficult; consequently, a truncated V-groove was developed. This new design is shown in Figure 3. Early in the development of these devices, the Vgroove was etched to a sharp trough. Once higher voltages were demanded, it was quickly recognized 2-21 Before beginning the discussion of V-groove technology, it is necessary to recognize that silicon is a crystalline allotrope element with three well-known crystallographic planes - < 100>, < 110>, and < Ill>. To build a V-groove structure, the starting silicon is always < 100>. The V-shaped groove results from what is known as preferential etching that follows the silicon crystallographic plane. Without interference, the etching process terminates when the sharp V-groove is formed; however, since a truncated etch is desired, it is critical to the fabrication that accurate timing be employed. Nevertheless, since the etch is "controlled" by the crystallographic plane of the silicon, the sides of the V-groove form a 54.7° angle with the surface and terminate at the < 111> plane. Because of the extreme care which is required in the manufacture of V-groove transistors, it is only used when the desired parameters cannot be achieved in any other way. Performance of this V-groove transistor follows that of the DMOS transistor closely with the following notable exceptions: 1. If the same diffusion schedule is maintained for the V-groove structure as for the DMOS structure, the channel length is longer by the geometrical factor associated with the 54.7° angle. The difference is approximately 1.7 times the channel length of an equivalent planar DMOS transistor. 2. Electron mobility is dependent upon the crystallographic plane, and for V-groove, the < 111> plane at the surface (channel) of the V -groove results in a reduction of this mobility of approximately 25 percent. 3. Threshold voltages tend to be higher for the same body dopant than a comparable DMOS structure as a result of a higher oxide charge inherent in < 111> structures. The channel region of an n-channel V-groove transistor is the p-diffusion (shown in Figure 1). To achieve electron velocity, this region must be short; it is in the design of high-frequency bipolar transistors to effectively reduce transit time. However, unlike the high-frequency bipolar transistor, reducing the length of this p-diffusion does not affect the operating breakdown voltage of the V-groove transistor. Access to this channel is accomplished using the V-groove. It is crucial to the success of the VMOS that the V-groove (truncated or not) extend slightly beyond the pdiffusion depth. References [1] Fuors, Dennis and Verma Krishna, "A Fully Implanted V-Groove Power MOSFET," Technical Digest, IEEE Electron Devices International Meeting, Washington, D.C., 1978, pp. 657-60. [2] Heng, TMS, et. aI., "Vertical Channel Metal-Oxide-Silicon Field Effect Transistor," Final Report, Westinghouse Research and Development Center, Pittsburgh, PA, November 1, 1976. 2-22 , 2.6 Lateral Power DMOS (LDMOS) Although lateral small-signal DMOS structures appeared in the closing years of the 1960's, power devices only became available commercially in 1977. LDMOSFET can exhibit an IDZ of 100 rnA compared to a more conventional VDMOS IDZ of 3 amps. The lateral DMOS transistor, shown in cross-section in Figure 1, has all three terminals-source, gate, and drain-on the top surface. This topology offers unusual advantages as well as several disadvantages that have limited the application ofthe LDMOS. 2. The gate-to-drain capacitance, Crss , is low. A low C rss offers the advantage of high switching speeds combined with high-frequency operation. The following advantages are offered by the lateral construction: The disadvantages of lateral construction are: 3. The drain is isolated from the case. 1. It has a severe geometric constraint and an ineffi- cient utilization of chip geometry. This constraint tends to limit the high voltage capabilities because limitations are imposed by the topology on the use of field shaping techniques. 1. It has a very low zero-temperature coefficient drain current, IDZ. For example, an 8 amp, 200 volt 2. As with the small-signal lateral MOSFET, the depletion region of the pn body-drain diode spreads laterally and thus adds to limitations in topology. Reference Richman, Paul, MOS Field-Effect Transistors and Integrated Circuits, New York, John Wiley and Sons, Inc., 1973. CHANNEL Cross-Sectional View of Idealized Lateral OM OS Structure Figure 1 2-23 - 2.7 Vertical DMOS The disadvantages recognized as inherent in the lateral DMOS structure have paved the way for industry to examine the vertical DMOS FET (DMOS). a series-connected JFET in the drain because the physical relationships between adjacent p-diffusions, acting as gates, pinch the current flow in its vertical descent to the backside drain. A simplified view of this restriction is shown in Figure 3. The spacing between the adjacent p-diffusions can be crucial in the performance of a high-power (current) DMOS PET. A more detailed analysis appears in Section The DMOS structure is conceptually similar to the LDMOS transistor except the drain contact lies on the backside ofthe wafer. Consequently, current flow is more vertical than horizontal as the cross-sectional view in Figure 1 illustrates. SOURCE GATE 2.13. SOURCE GATE cr---J 9A 1 LoGATE DRAIN Figure 2 Figure 1 The advantages of the DMOS structure, when compared with the lateral (LDMOS) structure, are simply the elimination of the disadvantages outlined previously for the LDMOS. However, although we gain in chip topology utilization, we do add another topology-related limitation which becomes increasingly more pronounced as the current flow rises. DEPLeTION BOUNDARY The electrical model of the vertical DMOS, although basically the same as any other DMOS structure, does offer an anomaly that distinguishes it from all other structures. As shown in Figure 2, there appears to be Figure 3 2-24 References Hu, C., "A Parametric Study of Power MOSFETs," Conference Record PESC, San Diego, CA, 1979. Lidow, A., T. Herman and H. Collins, "Power MOSFET Technology," Technical Digest, IEEE Electron Devices International Meeting, Washington, D.C., 1979, pp. 79-83. Lisiak, K. and J. Burger, "Optimization of Nonplanar Power MOS Transistors," IEEE Trans-Electron Devices 25 (1978), pp. 1229-34. - 2-25 2.8 The Bilateral MOSFET: A New Device Sees New Applications For many years there has been a need for a semiconductor capable of general purpose AC control. While there have been, and continue to be, some special purpose devices available which will do part of the job, no truly general purpose device for AC control was available. This situation has just changed. Advances in the field of MOSFET technology have now produced the first truly general purpose AC semiconductor: The Bilateral MOSFET. DRAIN J l GAIT~9-aSOURCE Until now, engineers wishing to control AC had numerous problems and few solutions. For low frequency AC switching, one could use thyristors, but they do not work at high frequencies and are hard to turn OFF. For switching both ON and OFF, one could use a bipolar transistor inside a diode bridge, but this is inefficient, cumbersome, expensive, and slow. For linear low-level applications, special attenuator and MUX ICs are available, but these function at low power levels only. For either linear or switching control of high level, high frequency AC, you were generally out of luck. Now, the bilateral MOSFET can handle all these jobs. DRAIN Bilateral MOSFET-Symbol Figure 1 New bilateral switches, such as the Siliconix BLSlOO family, give the designer requiring analog switching, subscriber line switching, or AC power conduction, a nearly ideal combination of characteristics which evades many of the compromises required by the approaches now in use. These n-channel enhancement mode devices have no inherent offset voltage and can transmit AC or DC signals with equal facility. Furthermore, the impedance in the ON-state is resistive, providing very low harmonic distortion. Bilateral MOSFET switches are a new product resulting from recent advances in power MOS technology. In terms of construction, the bilateral switch may be thought of as two n-channel DMOS power FETs with their source and gate leads connected in common. In fact, the first bidirectional devices were made by connecting two discrete power FETs in this fashion. The device that resulted from this pairing had such impressive characteristics that unified bilateral switches are now being manufactured. In operation, when a positive voltage greater than the threshold voltage (VT) is applied to the gate (with respect to the source), both FETs turn ON and conduct in series via their channels (see Figure 1). When the gate signal is removed, both channels turn OFF and conduction ceases. The source-to-drain diodes of the individual FETs do not conduct in reverse as they do in a unidirectional MOSFET because such conduction is blocked by the diode in the other half of the device. Reprinted with permission from Electronic Design, September 6, 1984; copyright Hayden Publishing Co., Inc., 1984. 2-26 Today, isolated gate drive presents few problems, both because of a proliferation of devices meant to accomplish this function and because FETs require so little static drive power. The designer has a choice of optical, transformer, or capacitive isolation, as well as combinations thereof. Each type of drive has its own properties. The choice of drive will depend on the system's requirements. Either of the diodes (depending on the drain-to-drain voltage polarity) may conduct when the device is turned ON but it will only conduct when the voltage drop across half the channel resistance exceeds the forward voltage of the diode. When one of the diodes does turn ON, it clamps the voltage across its associated half of the channel. This feature both reduces power loss in the bilateral switch at high power levels and serves as a surge protection in signal applications. Both diodes will conduct from the source to their respective drains if the source is biased above drain potential, a condition which should be avoided. Note that despite the fact that the two halves of the device are n-channel and operate in the enhancement mode, the resulting device is symmetrical and conducts identically in both directions. Transformer isolation may be either linear or switching in nature. Linear transformer drive is usually accomplished by rectifying a variable amplitude high frequency tone sent through the transformer. Transformer switching drive is accomplished by driving the transformer at two opposite polarity voltage levels: one for ON, the other for OFF. Note that proper voltsecond balance must be maintained in the transformer, or the core will saturate. To prevent saturation, the ExT applied to the primary in one direction must equal the ExT applied in the opposite direction. By making the OFF voltage greater than the ON voltage, ON intervals greater than 50% of total period can be achieved. Using 40 V gate breakdown FETs, this technique allows ON intervals to reach 80% of total period while maintaining proper volt-second balance in the transformer. Automatic control of voltsecond balance in the drive transformer may be achieved by placing a suitable capacitor in series with either the primary or secondary of the transformer. This will also reduce the reverse voltage stress on the gate oxide when duty cycles are below maximum. Good gate drive for the bilateral MOSFET switch requires some new, yet not difficult techniques. The gate-source terminal pair may be viewed as a voltagesensing capacitive load exactly as in a unidirectional MOSFET. Like the unidirectional MOSFET, input capacitance (Ciss) will vary with chip size, and thus, with voltage and current ratings. Bilateral devices will have approximately double the input capacitance of unidirectional devices of equal rating. The available threshold voltage (VT) range will also be the same as for unidirectional devices and is well controlled on the bidirectional devices to assure symmetry. There is one striking difference between the bilateral MOSFETswitch and any other device (see Figure 2). When the device is ON, the source terminal (gate return) is electrically in the center of a resistive divider formed by the two gate channels, and when the device is OFF, the source is referenced one diode drop above the more negative drain terminal. In many cases it will be necessary to use an isolated gate drive in order to avoid common mode effects. This seems a fair trade for true symmetrical AC capability and may, in some cases, be a convenience. Dl J 50% ON TIME DR:=JII~~J"" P' + 10 v-- 63385 75% ON TIME Dl - 30 v--------- Extending the Duty Cycle of a Transformer Isolated MOSFET Drive Figure 3 Rl R2 Transformer drive, especially when using shielded transformers, offers the best common mode rejection ratio (CMRR). However, transformers tend to be bulky and expensive, and if it is necessary to build them to UL or VDE insulation requirements, performance (primarily coupling) will suffer significantly, especially at higher frequencies. (R1 "" R2) D2 D2 EaUIVALENT DC CIRCUIT OFF STATE EQUIVALENT DC CIRCUIT ON STATE Source Reference Figure 2 2-27 - ing special purpose ICs) has evolved making old methods more practical. Modern capacitively isolated switching drives consist of a gated oscillator driving a rectification circuit through two matched capacitors (see Figure 5). The frequency of the oscillator must be high, perhaps 100 times the desired switching frequency. ON/OFF control of the MOSFET is achieved by gating the oscillator ON and OFF. The isolator in Figure 5 has a 1 MHz oscillator frequency and works well switching signals of :;;; 10 kHz and:;;; 30 VAC. Some telecommunications companies are studying this method to control bidirectional MOSFET switches for signal switching. Linear control could be achieved similarly by amplitude modulation of the oscillator. AC 1N5615 r --LOGOC{:'l INPUT --f..T. . L __ _ 68 K 1 W AC Parasitically Powered, Optically Isolated Drive Tr < 75 nsec Tf < 50 nsec 120 VAC Switch Figure 4 There are still limitations to the technique, however. CMRR is low, as would be expected. Capacitors, after all, conduct AC equally well in both directions. Presently available systems are better suited for linear controls, or for switching under tightly constrained circumstances than for high power switching systems where large common mode voltage transitions can be expected. If the load frequency being switched is too high, spurious turn-ON of the bilateral MOSFET may result. Present devices, which use a 1 MHz oscillator, can control frequencies of 5 to 10 kHz at levels suitable for telephone switching, but a 50 VRMS, 20 kHz signal, for example, would make some of the present units appear very leaky. The necessity of running the oscillator at frequencies much higher than the maximum frequency of the switched device also places a constraint on either the switching frequency of the main switch or the cost of the oscillator. Faster chips can be expected to alleviate this problem in the future. High DC isolation voltages are also a problem. The dielectric materials available for capacitors included in integrated circuits now place a limit on the maximum DC standoff voltage of such capacitors at 500 volts DC. Improvements in standoff voltage can be expected to come slowly. Optically coupled gate drive, likewise, may be either linear or switching in nature (see Figure 4). Generally, optical drives are smaller and less expensive than transformer drives and somewhat slower. Modern, shielded, optocouplers do, however, have good CMRRs, approaching the best transformers. Furthermore, units with sufficient voltage swing to drive a FET with switching times in the tens of nanoseconds are now available. Even using such high-speed devices, optocoupler speed remains the primary limitation on system switching speed. Sophisticated optical drives made from discrete PIN photo diodes and fast amplifiers can improve switching speed significantly when the extra speed is found to be worth the extra cost. Linear optical drives suffer primarily from nonlinearities in the optocoupler. These nonlinearities may be evaded by several means. The most common system is executed by using two matched optocouplers, each of which serves as a local feedback path to compensate for the nonlinearities in its companion. Similar, but more elaborate, systems can be made which are adequate for precision applications. Again, the primary limitation on the small signal gain bandwidth of linear optocoupling in terms of FET drives is cost. To recap briefly, with optically isolated drive, you can perform any drive function except very rapid switching. With transformer isolated drive, you can perform any drive function except keeping the switch in the Capacitively isolated drives are both an old system and a very new innovation. New technology (includ- 20 pF, 500 V 1/44011 1/6 4049 1/& 4049 AC Capacitor Isolated Gate Drive Driving a Bilateral Switch FigureS 2·28 Until now, the Venturini converter has had two horrendous drawbacks which limited its applicability. First, an N-phase to M-phase Venturini converter requires NxM AC power switches with individually isolated drives. In practice, this means using 2(NxM) unidirectional switches, each with its own drive and protective power diode. For a 3-phase to 3-phase converter, this adds up to 18 assemblies, each consisting of a power transistor, its drive electronics, a fast power diode with the same voltage and current rating as the transistor, and an isolated driver. The resulting system is incredibly complex, and only those who truly need the multifunctional capabilities of the Venturini are willing to bear the cost. ON state indefinitely. Transformer drive requires the most volume. By using capacitor-isolated drive, you can reduce costs, but only if you can accept limitations on load frequency and slower switching. One of the most obvious applications for the bilateral MOSFET is in the Venturini converter. The Venturini converter is an elegant voltage-independent, frequency-independent, bidirectional N-phase to Mphase switching converter. For example, a Venturini converter can be built to convert 3-phase 60 Hz power to 3-phase 400 Hz power bidirectionally, in a single stage, at well over 80% efficiency while regulating output voltage and input power factor. Venturini converters can also be built to convert 3-phase power to 2-phase, 5-phase, or any other number of phases. They can be built to change frequency to either a higher, lower, or variable frequency, including DC. Because Venturini converters are bidirectional, they will also function to synthesize multiphase sinusoidal power from DC or single-phase AC. They may also be used as regulators and power factor correctors. They may also be built as bidirectional synchro-toresolver converters, or, with an extra A to D stage, as an either-to-digital converter. The Venturini converter is probably as close to being a power anythingbox as any currently known device. JO. ,., ,., ,., TO ROTAnON AND AMPLITUDE PROCESSOR Y JO. ,., ,., Y This problem is now solved. Bilateral MOSFET switches conduct AC naturally and require a much less complex drive (though isolation is still necessary). In a 3-phase to 3-phase converter using bilateral MOSFET switches, several reductions take place: nine power components replace 36 power components; nine drivers replace 18; and drive complexity, cost, and volume are reduced. The second drawback to the Venturini converter is the lack of optimized control algorithms. Progress in solving this problem is more likely now that a practical J on. 3-, ,., , Y I I I I I T I JO. J on. T ,-3 .JO. I J 3-, SYMMETRIC MODE \ -'N ANTISYMMETRIC ) 3-Phase to 3-Phase Venturini Switch Matrix Figure 6 2·29 MODE-- -D.2Y I-"" -DAY ~ ~ 10- -- r- -o.ev -Day -1.0~ YDS - DRAIN TO SOURCE VOLTAGE (V) 1.0 ~~ A ~V 0 .• 0.' 0.7 0•• Ib) Enhancement·Mode Operation 05 , OA I') 0.2 0.1 +~ ~ + Day + 0.2 V YGS-OY ~~ 03 DepletLon-Mode ..4~ ;...--- r~ ........ ~ ~ /" I#}. /" ,/ J 1/ Vr VDS - DRAIN TO SOURCE VOLTAGE (V) The NOS100 Functions Both as a Depletion-Mode MOSFET (a) with VGS < 0, and an Enhancement-Mode Device (b) with VGS > 0 Figure 2 It is important to note that the on-resistance (RnS(on» of a NOS100 may vary substantially from device to device with zero applied VGS. This variation can be as large as 100%. Enhancementmode devices with similar specifications, on the other hand, may show only a 20 to 30% maximum variation in RDS( on). Ib) Enhancement-Mode The Difference Between an n-Channel Depletion-Mode MOSFET and an n-Channel Enhancement-Mode Device, is that IDSS is Substantially Greater than Zero for the Former, and Equal to Zero for the Latter Figure 1 Unexpectedly, this behavior results from the differing test conditions used when measuring RDS( on) for each type of device. Enhancement-mode power MOSFETs generally have a threshold voltage of2 to 4 volts, and are tested for RDS( on) at VGS = 10 volts. The effective enhancement voltage (V GS-VT) can therefore be as large as eight volts, but is no less than six volts. Unlike a JFET which is a depletion-mode only device and can accept only a single polarity of applied VGS, the NOSIOO can accept either a negative or positive VGS. With a negative applied VGS, the NOS100 works as a depletion-mode device with ID < IDSS. But with VGS positive, the NOS100 The NOS100 and other depletion-mode power MOSFETs, however, are normally tested for 2-34 a standard 1 rnA current-regulator diode (CRlOO) that supplies a constant collector current for the bipolar reference transistor Q 1. This transistor sets a constant voltage drop of one VBE across resistor RS. By varying the value of RS, adjustable output current is obtained. This circuit works well for currents up to several hundred rnA, but its sustaining voltage is only equal to the breakdown voltage of the current-regulator diode. RDS(on) with VGS equal to zero volts. Since the typical threshold voltage variation of the NOSIOO is from -2 to -4 volts, the effective enhancement voltage (V GS - VT) is then only +2 to +4 volts. For most power MOSFETs in the 100 to 150 volt range, the resistance of the conducting channel comprises 25 to 40% of the total device on-resistance. The conducting channel resistance (RCHAN) can be shown to be inversely proportional to the effective enhancement voltage (V GS-VT). Consequently, an enhancement-mode MOSFET will have an RcHAN that varies only by about 30% over its 2 to 4 volt threshold range. A depletion-mode MOSFETwith a - 2 to - 4 volt threshold, however, will exhibit an RCHAN that varies by 100% over this range. It is this variation in RCHAN that accounts for the wider spread in RDS(on) for the NOSIOO and other depletion-mode power MOSFETs. By connecting the gate terminal of an NOS 100 back to the other end of a source degeneration resistor, as shown in Figure 4, a simple adjustable current regulator is obtained. This two-component regulator performs just as well as the circuit in Figure 3, but uses fewer components and requires less board space. Applications 1. A two-terminal adjustable current r~gulator Many analog circuits require a constant current to be generated that is independent of supply voltage. This current may be used to bias an amplifier stage, such as a differential transistor pair, or may be used to charge a timing capacitor which generates a sawtooth voltage waveform. The NOS100 and One External Variable Resistor Form a Simple but very Useful Two-Terminal Current Regulator Figure 4 Two-terminal current regulator diodes such as the Siliconix CR series of devices have been available for a number of years. While these devices are very useful in certain applications, they are limited by their maximum voltage and current ratings (100 volts and 4.7 rnA, respectively). Clearly, if constant currents larger than 4.7 rnA are required, and at higher supply voltages, the designer must choose some form of discrete regulator circuit. Because the negative gate bias for the NOSIOO is generated by the drain current flowing through RS, _ one can solve analytically for the value of this resistor given the desired ID and the two parameters VT and lOSS. To accurately determine RS, however, both VT and lOSS must be known accurately as well. This necessitates measurement of VT and IDSS for every device, since these parameters may vary widely from device to device. Until now, the best way to implement a high-voltage two-terminal adjustable current-regulator was with an enhancement-mode MOSFET and a bipolar transistor as shown in Figure 3. This circuit employs Rather than using the analytical approach to determine the required value ofRS given a desired value of ID, a simpler method would be to replace RS with a multi-turn trimpot. This trimpot can then be adjusted until the desired operating current is reached. With RS being the gate bias resistor, the maximum possible output current will be equal to IDSS. This current is reached when RS equals zero. It is not possible to obtain values ofID in the low f.J-A range, unless the maximum value of RS is quite large (around 1M a ). This behavior occurs because the VGS of the NOSIOO is equal to - IORS. For VGS to approach VT, progressively larger values of RS are required. But VGS can never be equal to VT because ID would then be equal to zero and there would be no gate bias-a paradoxical situation. This Two-Terminal Adjustable Current-Regulator Uses Four Components Including an Expensive Current Regulator Diode Figure 3 2·35 Certain applications, particularly those in the telecom domain, often require a logic controllable AC switch with high breakdown voltage as well. The major difference here is that the switch must remain on whenever there is a failure in the gate drive circuitry or its power supply. Until now the only way of obtaining normally-ON switching action, combined with high breakdown voltage and moderate current handling capability was with electromechanical relays. The disadvantages of relays are numerous and include large drive power requirements, excessive EMI generation, finite contact lifetime and slow switching speed. Depletionmode power MOSFETs with their normally-ON resistive characteristics provide a solution to the problem of building a normally-ON solid-state AC switch. In most real applications for the circuit of Figure 4, the required output current will probably be in the range of a few rnA to several hundred rnA. The lkO trimpot chosen for RS, provides an ID adjustment range of approximately 5 rnA to 500 rnA. To illustrate the performance of the NOSIOO as a current regulator, the 1kO trimpot used in the circuit of Figure 4 was adjusted until ID was equal to 30 rnA at a VF offive volts. Figure 5 shows how the output current varied when VF was varied between 0 to 200 volts. As can be seen, the output current changed less than 1 rnA ( or 3.3 % ) resulting in a high output resistance of approximately 200 kO. 401-+-+_+-+-+-+-+----1_t___l The VQ5000 depletion-mode MOSFET array contains four devices. These transistors can be used as the basic switching elements in a dual normallyON solid-state AC switch shown in Figure 6. When the sources and gates of each pair of MOSFETs are connected together, two bilateral switches are formed. This switch configuration can conduct current and block voltage in both directions. 1 1301r=+=~~=F~=t=1=-r_t_l 13 ~ ~20~+-+-+-+-+-+-+--1-t---l I 9 10 J-+-+_+-+-+-+-+---1I_t___l 40 80 120 160 VF - FORWARD VOLTAGE DROP (V) 200 The rest of the circuitry shown in Figure 6 comprises a capacitive isolated driver stage that generates logic controllable DC bias for the two bilateral switches. Because the MOSFET's gate and source terminals are isolated by two capacitors from the logic circuitry, the AC signal being switched need not be referenced to the logic power supply ground. This is a very useful feature of the circuit The Two-Terminal Current Regulator Using a NOS100 Performs Very Well OVer an Applied VoHage Range of 0 to 200 V Figure 5 When the current regulator is to be operated at moderate current levels with large sustaining voltages, a small clip-on heatsink should be attached to the NOSIOO because the temperature coefficient of ID is positive. This recommendation was followed for the 30 rnA regulator described above. Each half of the driver circuit in Figure 6 is identical, and its operation can be understood if the signal path is traced from the LM555 output to the gates of the MOSFETs. 2. A normally-ON solid-state AC switch The LM555 is connected as a free running oscillator and generates a rectangular waveform at approximately 100 kHz. This signal is fed to the inputs of a Siliconix D469 CMOS quad driver Ie. Each pair of drivers within the D469 buffers the 555 output, and generates antiphase 100 kHz outputs that swing between ground and 12 volts. The remaining inputs of the two pairs of drivers are connected to control logic that allows the D469 outputs to be gated on or off as required. Solid-state AC switches that can handle reasonable amounts of power have been implemented with a variety of semiconductor devices such as bipolar transistors, SCRs, triacs and MOSFETs. Of these devices, only MOSFETs offer high breakdown voltage, low leakage, and linear on-resistance down to zero volts. If a solid-state AC or "bilateral" switch is built using enhancement-mode MOSFETs, then the switch is by nature normally-open or normally-OFF. This means that when the gate bias voltages for the MOSFETs are lost due to failure in the gate-drive circuitry ( or. its power supply), the switch turns off. In many AC switching applications this characteristic behavior is acceptable. The antiphase D469 outputs are fed into a pair of AC coupling capacitors that drive a bridge rectifier comprised offast small-signal diodes. Both outputs of the bridge rectifier are connected to the bilateral switch, such that when the outputs of the D469 are pulsing 2·36 SWITCH 2 1/2 VQ5000 SWITCH 1 1/2 VQ5000 5, '3 5, 52 52 10 10 kn 10kO l"~" .5,1.1F 8 9 5 • TANT SWITCH 2 CONTROL .nJlJl 110kHz '---"0.0'---+--------0 OFF 01 -ON 1/6CD4D69 1/6 CD4069 + 12V +12V SWITCH. CONTROL CD4069 'kfl PINS 5,7,9,11,13 "" GND PIN 14 "" + 12 V 2kn LM555 00022 I"F A VQSOOO Quad Depletion-Mode MOSFET Array, a 0469 Driver and a 555 Timer Form the Basis for an Isolated, Dual Normally On-Solid State Switch That Is Logic Compatible Figure 6 the VGS of the MOSFETs is negative. Under these conditions the bilateral switch is OFF. constant value. Not surprisingly, this value of limiting current is equal to the IDSS of the MOSFETs. The bilateral switch thus has built in current limiting which is a useful self-protecting feature. When the logic control signal gates the antiphase 0469 outputs off, the output of the bridge rectifier drops to zero. Consequently, the effective gate to source capacitance of the MOSFETs discharges through the 10 kf! resistor, and the bilateral switch turns on. The switch also turns on when the logic/ driver power supply fails, since the output of the bridge rectifier is then zero as well. 0.5 0.4 -- 03 02 !E V 0.1 ~ Figure 7 shows the on-state characteristics of the depletion-mode bilateral switch. The vertical axis in Figure 7 is the switch current in A and the horizontal axis is the voltage drop across the switch in V. One can see that the switch on-resistance is equal to the reciprocal of the slope of the trace in Figure 7, and is approximately 7.50. It should be noted that the on-resistance remains very linear through the zero-crossover region in the center of the photograph. As the voltage across the switch increases in either direction, the current increases linearly up to a point but then levels off at a il '"~ / -0.1 / rn _ 02 - 03 V I"""" F"" -0.4 - 0.5 -5 -4 -3 -2 -1 0 VOLTAGE DROP ACROSS THE SWITCH (V) The On-State Transfer Characteristics of the Normally-On Bilateral Switch Show a Constant RDS(on) Through the Zero Crossover Point Figure 7 2-37 - The switch off-state characteristics are shown in Figure 8. The vertical axis here is the switch leakage current in IlA and the horizontal axis is the sustaining voltage of the switch in V. As can be seen the switch leaks negligible current until the breakdown voltage ofthe MOSFETs is exceeded in either direction. In this case the switch breakdown voltage is ± 180 volts. as shown in Figure 9. The turn-on time is approximately 50 ILsec, while the tum-offtime is substantially less than this value (about 10 JLsec). The observed difference is explained by the fact that during switch turn-on, a finite amount of time is required for the effective gate to source capacitance (CGS( eft) to discharge through the 10 kn resistor. During switch turn-off, however, more than enough current is available to rapidly charge CGS(eff) to a negative voltage less than VT. sao 5 Y/DlV l ... ffi ~ w --- t.oo LOGIC CONTROL SIGNAL 1/ -800 - 200 - 100 0 100 SWITCH OUTPUT I NTO 1 Kfl LOAD 1\ 200 SUSTAINING VOLTAGE (V) 2y/DW The Off-State Transfer Characteristics of the Bilateral Switch Show That It Can Block AC Voltages Up to 180V Peak Figure 8 50 IAoS/DIV The Turn-On and Turn-Off Delay TImes of the Bilateral Switch Relative to the logic Control Signal (Top-Trace) Are Not Bllndlngly Fast, but Nonetheless Adequate for Many Applications Figure 9 The turn-on and turn-off times for the driver and switch configuration described are greatly different, 2·38 , 2.9.1 Fabrication of Depletion-Mode Power MOSFETs Combining low voltage depletion-mode MOS technology with high voltage MOSPOWER technology has produced a new type of power device-the depletion-mode power MOS transistor. This new class of transistors represents a merging of the strengths of both of its parents. Its announcement is the result of an I8-month effort to obtain a delicate balance between the need to tum the device off when a low negative voltage is applied to its gate (i.e., to pinch off), while having a low on-resistance when no voltage is applied to the gate. The hurdles that were overcome in the development program may be understood by referring first to Figure 1. This figure shows the cross section of both a low voltage enhancementmode and a low voltage depletion-mode MOS transistor. The threshold voltage of a MOS transistor is determined by a number of process parameters. For a given gate conductor (usually aluminum in a metalgate process and phosphorus-doped polycrystalline silicon in a silicon-gate process), the threshold voltage is set largely by the dopant profile in the body region. The low voltage enhancement-mode transistor of Figure I(a) is converted to a depletion-mode transistor by locally adjusting the body dopant using an ion-implantation. For the n-channel transistor of this figure, a phosphorus implant is used. from a common origin. The channel length L is reproducibly controlled to values in the 1 to 2 /Lm range. A small value of L results in both a large current per unit area and a low value for the device channel resistance. The development of a high voltage, n-channel MOSPOWER transistor requires considerably more process optimization than is shown in Figure 1. The dopant profile through the double diffused source, body and drain regions of a vertical DMOS device is shown in Figure 2. In this structure, the channel length L is determined by the difference between two sequential diffusions moving in the same direction In the DMOS power transistor structure, the body region is more heavily doped than the n-drain region as shown in Figure 2. With a reverse bias across this junction, the resulting depletion region extends further into the drain region than the body region. This behavior allows high voltages to be placed across the body-to-drain junction without significantly affecting the channel length of the DMOS transistor. SOURCE GATE DRAIN l1li P·TYPE BODY a. Enhancement-Mode SOURCE GATE DRAIN P-TYPE BODY b. Depletion-Mode The Cross Section of an NMOS Silicon Gate Transistor Figure 1 Reprinted with permission from Electronic Design, Vol. 32, No. 13; copyright Hayden Publishing Co., Inc., 1984. 2-39 diffusion cycles and the specific ion-implantation dose and energy. These profiles were verified experimentally on existing device geometries and the resulting transistor characteristics were measured. This information was used as a starting point for another round of simulations and experiments. DRIFT REGION SOURCE OXIDE =~~:6CNE N+ BODY SUBSTRATE DOPING PROFILE N+ SOURCE P CHANNEL N- DRIFT While the iterations were taking place in the process area, device layout was started in design. The device was designed to meet a 150 volt breakdown and a 5 ohm on-resistance specification. The design was completed as the process experiments were drawing to a close, so the mask set was run using the final process sequence. The culmination of this work is shown in cross section in Figure 3 where an enhancement-mode device is compared to a depletion-mode transistor. A photograph of the device is shown in Figure 4. This device was designed for a specific application, but the process was developed so it would be applicable to the complete line of power DMOS transistors. This goal was met, and the NOSIOO is the first device in a complete family of depletion-mode DMOS power transistors. N+ DRAIN The Doping Profile in a Vertical DMOS Transistor Figure 2 The first attempt to produce a depletion-mode power MOS transistor added only an ion-implantation step to the normal process sequence. Transistors produced in this fashion did exhibit the required depletion-mode characteristics, but suffered from two problems. First, these transistors could not be turned off with less than-lO volts from gate to source. In addition, the breakdown voltage was considerably less than desired. The use of only an ion-implantation with a dose sufficiently large to produce a depIetionmode device altered other characteristics in an unacceptable manner. Analysis ofthese results lead to an understanding of the problem. The lateral nature of the dopant profile shown in Figure 2 and the vertical dopant profile resulting from an ion-implantation do not produce the required body region profile without considerable optimization. The peak concentration in the body must be reduced while the remainder of the body region concentration is impacted in a minimal fashion. This balance was arrived at through an iterative procedure. Computer simulations were first used to home in on the body dopant profile. The results of these simulations were used to devise both SOURCE & BODY ~..,. GATE ...... 1 ..."r- l"" l ~F P N- BODY J DRAIN -------------------------N+ SUBSTRATE 6 DRAIN The Cross Section of a Depletion-Mode Vertical DMOS Power Transistor Shows the Conducting Channel with VGS OV Figure 3 = Photograph of the Depletion-Mode Device (NOS100) Figure 4 240 2.10 Other Structures There are many alternative solid-state devices that can handle high voltages, high power, and respectable switching performance although perhaps not at the speed of the power MOSFET. Since the early 1950's, the Darlington pair has offered quasi-MOS-like performance for high gain and reasonably high input resistance. Their nemesis has been their poor VSAT and long turn-OFF time. Thyristors, such as the ubiquitous SCR, have tremendous voltage standoff and power handling capability, but triggering and switching time have been their shortcoming. Early in the 1980's, a concentrated development effort appears to be rewarding industry with innovative power devices that, in some cases, have often encircled MOS technology and MOS performance in their designs. DRAIN/COLLECTOR -~~ EMITTER GATE EMlnER EPITAXY SUBSTRATE n+ DRAIN/COLLECTOR MOS-Bipolar Structure Figure 1 One of several useful criteria for judging the effectiveness of solid-state power devices is to compare their current capability per unit area of silicon. Another criterion, of course, is simply to compare performance. in Figure 2. Although they exhibit an impressive current density, their principal shortcoming is, as with all composite MOS-bipolar structures, an excessive storage time or turn OFF delay. The composite MOS-bipolar transistor structure as shown in Figure 1, whether the Darlington configuration or one of several alternative configurations, has found widespread industrial acceptance. Although often touted as exhibiting ultra-low ON-resistance, much like the power bipolar transistor, their slow switching speed and attendant high switching losses (again, much like the power bipolar transistor) have severely limited their usefulness above 30 kHz. SOURCE GATE SOURCE p+ More recent developments have focused attention on MOS-gated SCRs-variously called the InsulatedGate Transistor (IGT), the High-Conductance MOSFET, or Insulated-Gate Rectifier (IGR)-as shown COLLECTOR Insulated-Gate Rectifier (IGR) Figure 2 2·41 Reference Ghandi, S. K., Semiconductor Power Devices, New York, Wiley Interscience, 1977. Schultz, Warren, "High Current FETs-A New Level of Performance," Power Conversion International, March 1984, pp. 43-6. Smith, Marion, et. aI., "Insulated Gate Transistors Simplify AC-Motor Speed Control," EDN (February 9,1984). 242 'I 2.11 Power Control with Integrated CMOS Logic and DMOS 'Output Abstract sistors are being fabricated simultaneously with CMOS control logic to obtain DMOS/CMOS or D/CMOS power integrated circuits. This paper begins by quickly reviewing the history of DMOS or double-diffused discrete MOS transistors. Next, the development of the circuits presently available using D/CMOS technology is covered. D/CMOS circuits may be manufactured using different process sequences. The characteristics of each of the D/CMOS IC technologies are compared. Finally, the expected directions of technology and circuit development are discussed. In this section, unexploited aspects of D/CMOS devices are pointed out for specific applications. This paper examines the evolution and the present status of a new class ofpower integrated circuitsDMOS/CMOS or D/CMOS ICs. This type of circuit is a natural extension ofthe development ofthe discrete MOS power transistor that has occurred in the last few years. However, there are significant differences between D/CMOS ICs and either conventional MOS or bipolar circuits. The major difference is their ability to withstand and control voltages that are considerably greater than those of either circuit type. A second difference is their low power dissipation. Less obvious advantages also make D/CMOS ICs attractive in other applications. These advantages and their effect on future D/CMOS circuit trends are also discussed History of Discrete Power DMOS Transistors Introduction A detailed description of the development of contemporary power MOS transistors was given in a previous paper [11. The flow of discrete MOS power transistor development is shown in Figure 1. As shown in this figure, a ten-year span has witnessed large multiples in both current and voltage rating. The next few years will see continued advancement in discrete power MOS transistors, but not the large increases in current and voltage ratings that have occurred in the last few years. The on-resistance characteristics of these devices restrict their use in most cases to applications requiring less than 1000 volts. Larger chip sizes are possible, but yield considerations make it more attractive to parallel die or packages to obtain higher currents. The main focus for discrete technology in the coming years will be manufacturability and economics. Large reduction The term "integration" as used in electronics means the incorporation of more functions in a physical unit. The trend to integrate more devices on a piece of silicon is one manifestation of this trend. In integrated circuit development, progress within a given technology is usually made in a very predictable fashion. An example of this type of progress is the storage capability of the largest commercially available RAM. Over the last fifteen years, RAM capability has doubled every one and one-half to two years from lK in 1969 to 256 K today. Breakthroughs occur when new technology is injected into the mainstream of Ie development, allowing previously unfeasible circuits to be developed. Such a breakthrough is occurring today as high current, high voltage DMOS tran(This manuscript was prepared for and presented at Electro 84) 2-43 l1li Table 1 A Comparison of Power MOS and Bipolar Transistor Electrical Characteristics [11 in price will lead to greater device acceptance. The economics of scale resulting from increases in MOS power transistor use will enable them to compete more effectively with bipolar transistors. Paramete, Input Impedence The most significant development in discrete D MO S devices in the last two years is the announcement of MOS-gated regenerative (Le., latching) and conductivity modulated devices. These two similar types of devices promise to significantly enhance the CUfrent ratings of D/CMOS ICs. Current/Voltage 1970- High (11)5.101, Intormedl... (,0'.,02) SwHchlng Frequency HIgII(I_kHz' Intermedl... (20-10 kHz) On Re.I_ High Low OIfRHI_. High High 1..-1... (500 V) High (1200 V) ~bliity Rugged ..... Excellent Good Coot High Intormedlolw M..lmum Opoming High (2OO"C) Intermedlolw (ISO'C) Temper.tu,. - - Metal Gate Lateral DMOS TranSlStor 1975 ...... Metal Gate V-groove Transistor 30V/SO rnA circuits. The ease with whichDMOS transistors may be driven when compared to bipolar transistors is one obvious advantage. Ruggedness, particularly the absence of secondary breakdown in DMOS transistors, is another advantage. However, the voltage drop per unit area for transistors with equivalent voltage ratings is considerably greater for DMOS transistors. This disadvantage dictated that DMOS transistors be utilized first in ICs with voltage ratings beyond those ratings of bipolar transistors. The first application of D/CMOS technology was for high voltage display drivers. The development of these circuits took place in the 1977/78 time frame. 60V/1 Amp ...... Silicon Gate V-groove Transistor 100V/S Amp - ... Metal Gate Vertical DMOS Transistor 400V/IOAmp 1980 ...... Silicon Gate Vertical DMOS Transistor 1985 BIpolar Performance High (lot-lOll ohm.) Intennedl... (1CJ3.105 ohm., Cumonl GoIn VoHogo Maximum Ratings TECHNOLOGY MOS Performance SOOV/20Amp ...... High Voltage/High Current Technologies 10OOV/SO Amp _ -Regenerative & Conductivity Modulated 10OOV/IOO Amp Two classes of displays-plasma and electroluminescent panels-required voltages from 80 to 200 volts for successful operation. Line density and allowable cost per driver also dictated that as many outputs as possible (in multiples of8) be fabricated on one chip. Different drive schemes were developed to address and solve the problems presented by each panel type. This work resulted in the three different D/CMOS technologies which are the starting point for contemporary D/CMOS ICs. These three D/CMOS IC technologies are discussed in the next section. Devices A Chronology of Discrete DMOS Power Transistor Development Figure 1 The advent of MOS power transistors has lead to numerous comparisons between them and bipolar transistors. At first, the goal of the comparison was to show that one type of device was superior to the other for a given application. One such comparison is contained in Table 1. A more enlightened approach is to examine the characteristics of each type oftransistor, and then to make a selection based on the resulting match. Each transistor type has a range of applications which match the device requirements. Self Isolated D/CMOS IC Technology In one driver configuration, the output drive transistors were required to withstand 200 volts in an open drain configuration. The drive circuitry was required to dissipate minimum power, so CMOS logic was an appropriate choice. These two requirements lead to the development of "self isolated" D/CMOS technology as shown in Figure 2. The CMOS logic in this technology operates with a power supply up to 15 volts, while the DMOS output transistors are capable of 400 volts. Using silicon-gate technology with a 4 JLm feature size, the clock frequency of the logic is 5 MHz. The Development of ICs with Low Voltage CMOS Control and High Current, High Voltage DMOS Outputs The comparison of characteristics presented in Table 1 compels IC designers to consider the benefits derived from the incorporation of ICs in monolithic 2-44 / / / StB 5,8 G G G p- Substrate Low Voltage n-channel High Voltage n-channellateral CMOS FEY Enhancement and DepletIon Mode FEYs Cross-Section of a Self-Isolated D/CMOS I.C. Figure 2 Junction Isolated D/CMOS IC Technology Junction Isolated D/CMOS Technology with Complementary Outputs Other displays required lower voltages (60 to 120 volts) with totem-pole, n-channel outputs. These requirements were met usingjunction isolation to stand off the voltage between adjacent devices. DMOS transistors, because of their configuration, have a higher breakdown voltage than simultaneously fabricated bipolar transistors. A cross section of this technology is shown in Figure 3. Because ofits added complexity, junction isolated technology is capable of providing a variety of additional components. The most useful of these components is the npn transistor, though pnp transistors and a variety of diodes and resistors are also available. 8G SG D 8 A third D/CMOS configuration was required when high voltage push-pull outputs were needed. Junction isolation was essential but the process sequence had to be modified to accommodate the high voltage pchannel device. Size constraints made it advantageous to use DMOS technology for the p-channel device. This combination of constraints led to the junction isolated complementflry output structure shown in Figure 4. Both the junction isolation and the DMOS output transistors are capable of withstanding 120 to 150 volts. The low voltage CMOS logic is designed to operate in the 5 to 15 volt range. E BG S G D BG 5 G D ~---D~M~O~S--~~----~NP~N--~!L!----~NM~O~5------~L--~P~MO=S~~ Cross-Section of a Junction Isolated D/CMOS I.C. [1] Figure 3 n-Substrate High Voltage n-channel DMOS FEY High Voltage p-channel DMOS FEY Low Voltage "-channel Enhancement and Depletion Mode FEY. High Voltage CMOS Process Cross-Section of a Junction Isolated, Complementary Output D/CMOS I.C. [2] Figure 4 2-45 - -.'30 These three D/CMOS technologies are compared in Table 2 with respect to fabrication sequence and electrical performance. Table 2 contains the output configurations possible with each of the three major technologies. This table also provides the paralleled resistance and the current capability of DMOS output transistors. introduced and represents only an additional, well characterized process sequence. The growth of quality gate dielectrics is also well known. The gate conductor most often chosen is either aluminum or doped polycrystalline silicon. Aluminum as the interconnect metallization offers process simplification but results in larger device sizes. The use of poly silicon as the gate conductor adds a process step to the fabrication sequence, but it also allows another level of process interconnect. Status of Circuits Containing CMOS Logic and DMOS Output Transistors Circuits fabricated with each of these three D/CMOS technologies are becoming commercially available. Considering the design flexibility and economics of IC manufacture, the second technology - junction isolated D/CMOS - is likely to become the most popular industrial choice. This technology has a number of advantages for both IC manufacturers and users. Device Characteristics Similar to Those of Other Technologies The similarity between the bipolar and the junction isolated IC fabrication leads to a second significant advantage. Many of the available circuit devices have characteristics that are similar to those of bipolar technology. The circuit designer has to become familiar with the characteristics of only a few new devices as opposed to unlearning and relearning a whole set of new characteristics. Similarity to Existing Bipolar Process Technology The process cross section shown in Figure 3 differs only in a few ways from the cross-section of a bipolar IC. The most significant of these differences are the need to include a deep, lightly doped region called a p-well for the n-channel transistors, and the requirement for a gate dielectric (usuallv thermallv grown Si02), and a gate conductor. The p-well is easily Circuit Design Techniques Are Familiar Design techniques using the grounded substrate configuration of the junction-isolated D/CMOS technology are also well known. A designer is not faced with learning a set of new design techniques. Only an extension of existing knowledge is required. Table 2 Comparison of the Features of the D/CMOS Processes D/CMOS TECHNOLOGY SELF ISOLATED JUNCTION ISOLATED JUNCTION ISOLATED WITH COMPLEMENTARY OUTPUTS Epi Required No Yes Yes Masking Steps 9 - II 10 - 12 II - 13 Logic Voltage 5 - 15V 5 - 15V 5 - 15V Clock Rate 5 MHz 5 MHz 5 MHz 200- 400V 150V ISOV CHARACTERISTIC FABRICATION Output Voltage Output Configuration Single Ended (open collector) Single Ended, Totem Pole Single Ended, Totem Poie. Push-Pull ELECTRICAL Parallel Resistance of Output Devices (200 x 200 mil chip) 3-5n Total On-Chip Current Capability 2-4 amps i- 2 n 10-20 amps 2-46 2- 4 n 5-10 amps Circuits Are Similar to Other Device Families The negative ground configuration with CMOS compatible inputs is common in the electronics industry. Little, if any, systems modification is necessary to begin taking advantage of circuits fabricated with the junction isolated D/CMOS technology. For these reasons, the junction isolated D/CMOS technology is likely to gain industry-wide acceptance more rapidly. An example of a circuit fabricated using this technology is shown in Figure 5. This chip contains analog and digital control functions implemented using silicon-gate CMOS technology and two large output drive transistors in the totem-pole configuration. The input circuitry is TTL compatible with the low voltage section operating from a 30 volt supply. Level shift is accomplished using high voltage lateral DMOS transistors. The two large DMOS transistors are rated at 80 volts, and the large transistor supplies 12 amps while the small one supplies 8 amps. Resistors are placed in series with the two output transistors for sensing and controlling the current in each transistor. The chip size is 195 mils x 335 mils (4.9mm x 8.4mm). This junction isolated IC represents the state-of-the-art in power D/CMOS circuits. Photograph of a Driver Circuit Fabricated Using the Junction Isolated D/CMOS Technology Figure 5 environments with considerable electrical noise. The high currents through the transistors coupled with the presence of various four layer (and hence potentially latching) structures require care in both circuit layout and circuit use. The sensitivity of the IC to latch-up can be minimized through proper circuit design, but it cannot be eliminated in conventional junction isolation. Use of dielectric isolation instead of junction isolation as shown in Figure 6 will eliminate latch-up, but this technology adds considerable cost to the circuit The dielectric isolation technique may be applied to any of the three D/CMOS technologies, but it is probably more applicable to the two junction isolated versions. Directions for Future Development in D/CMOS Integrated Circuits The initial enthusiasm resulting from the promise of D/CMOS technology has tended to obscure two things-problems that need addressing before greater acceptance is earned, and growth directions to fully take advantage ofthe promise of this new technology. Concerns in both of these areas are essential if D/CMOS technology is to realize its full potential. These issues are discussed in this section. A major potential concern for D/CMOS circuit designers and circuit users is circuit performance in DRAIN SOURCE GATE . -.::'. .. ' .:~:. :):/:.:.:,.: . : ""J :::: " :";":', Cross-Section of a Dielectrically Isolated D/CMOS I.C. [1] Figure 6 2-47 - l1li Careful circuit use is as important as the design of the circuit in systems with large currents flowing. For this reason, it may be necessary to have more than one ground on the chip. A logic ground should be capable of providing stable current sinking. The presence of a separate high current ground for the output devices means that some ground "bounce" may be allowable without interfering with the operation of the low voltage section of the chip. of these device types promise to control more power per square mil of silicon surface than DMOS transistors. The conductivity enhanced device is gate controlled during both tum-on and tum-off, while the voltage across the regenerative device must go to zero before conduction stops. It is possible to integrate both of these structures in D/CMOS ICs. However, this integration cannot proceed without some caution. The presence of excess minority carriers in the drain region may increase circuit sensitivity to latch-Up. Considerable care must be taken to guarantee latchup free operation. One major hurdle facing high power D/CMOS IC manufacturers and users is the availability of packages, heat sinks, etc., that allow circuits to operate at or near their intrinsic limits. The last few years have seen continued progress in the high power package area in both plastic and hermetic packages. However, this area is key for future improvements in circuit performance and reductions in circuit costs. Summary and Conclusions This article has examined the evolution, present status, and future directions of D/CMOS IC technology. Three different specific technologies were discussed, and their features were compared. Based on this comparison, one D/CMOS technology, the junction isolated D/CMOS, was selected as the technology most likely to become an industry standard. One circuit that pushes junction isolated D/CMOS technology to its limits was examined as an example of what is possible. Finally, future directions for D/CMOS IC circuits were indicated by discussing both areas of concern and advantages of this technology. The theme running through this paper is the dynamic nature of this field. The promise of D/CMOS technology is being realized as both users and manufacturers begin to understand its limits. The DMOS transistor's ability to operate at both high and low temperature extremes offers significant advantages for many applications. The package power dissipation limits discussed in the previous paragraph set the ultimate limit, but both the logic and the output stage of a D/CMOS are capable of operating at 150°C and above. The positive temperature coefficient of resistance of DMOS transistors has both advantages and disadvantages. The output device resistance does increase with temperature resulting in increased power dissipation and decreased efficiency, but DMOS transistors are capable of stable operation at temperatures as high as 200°C and above. This behavior is in contrast with that of bipolar transistors which have a negative temperature coefficient. The low temperature performance of D/CMOS circuits also offers significant advantages over bipolar circuits. The speed and current handling capability of both the low voltage CMOS transistors and the output DMOS transistors increases as the temperature decreases from room temperature down to 77°K (liquid nitrogen) [3]. The dual advantages at lowered temperatures are enhanced device performance and increased power dissipation capability. References Another area in which D/CMOS circuits may offer advantages is in radiation environments. The major effect of ionizing radiation on MOS transistors is to change the threshold voltage due to charge generation and trapping in the gate dielectric. Techniques for "hardening" conventional MOS transistors apply as well to DMOS transistors. It should be possible to obtain D/CMOS integrated circuits capable of withstanding a total dose of 105 to 106 (rads silicon). The announcement of discrete DMOS-gated conductivity enhanced [4] and regenerative [5] structures foreshadows future circuit developments. Both 2-48 [1] RA Blanchard, "MOSFETS IN ARRAYS AND INTEGRATED CIRCUITS," Proceedings ofElectro 83 Paper 7/4 (1983). [2] RA Blanchard and W.G. Numann, "A High Voltage Chip Set for Use as Electroluminescent Panel Drivers," Proceedings of the Society of Information Display, April, 1982. [3] RA Blanchard and R Severns, "Designing Switched-Mode Power Converters for Very Low Temperature Operation," Proceedings of Powercon 10, D-2 (1983). [4] J.P. Russell, AM. Goodman, L.A Goodman, and J.M. Neilson, "The COMFET - A New High Conductance MOS-Gated Device," IEEE Electron Devices Letters, P63, EDL-4 No.3 (March, 1983). [5] A Pshaenich, "The MOS SCR, A New Thyristor Technology," Motorola Engineering Bulletin EB-103 (1982). 2.12 Drain to Source Breakdown and Leakage in Power MOSFETs An examination of almost any power MOSFET data sheet reveals values for both the drain to source breakdown voltage, BVDSS, and leakage current, IDSS, with zero applied gate-to-source voltage. At a cursory glance, these two parameters might seem to be unrelated until one looks at the test conditions for each. The breakdown voltage is measured at a specified leakage current and leakage current is measured at a specified voltage, often a percentage of the breakdown voltage. Specifying these two parameters separately on a data sheet is accepted practice (by many manufacturers), but is somewhat redundant. • )r-i--r-i--t-i-i+-i--t-i--r-1~ 5OY!dlv A statement relating breakdown voltage and leakage current would certainly help to clarify matters. In the ideal case, the BVDSS of a MOSFET is reached when the leakage current begins to increase drastically with a small change in applied voltage. In a properly designed and manufactured power MOSFET this effect is as shown in Figure 1. Beyond a certain voltage, the drain current suddenly begins to increase uncontrollably if not limited. Normal Breakdown Occurs in an n.Channel DMOS Power FET When the Applied Drain to Source Voltage Exceeds the Device's BVDSS Figure 1 Not all power MOSFETs show such predictable behavior as that illustrated in Figure 1. An unusual effect known as "latch-back" has also been observed in certain types of MOSFETs [1] (notably metal gate V-groove devices), and is shown in Figure 2. Here normal breakdown begins as BVDSS is reached, but as the leakage current rises towards a critical value, the sustaining voltage of the device suddenly drops or "latches-back" to a lower value. This latched-back breakdown voltage can be as much as 80% less than BVDSS· \ taVldlV Latchback Occurs in a Power MOSFET When the Parasitic Bipolar Transistor Begins to Conduct Collector Current Figure 2 2-49 - , Both the normal and latched-back modes of breakdown (Figures 1 and 2 respectively) are non-destructive if the increased leakage current is limited to a safe value. This prevents excessive power dissipation in the MOSFET, which could force the junction temperature above the maximum allowable limit and cause device destruction. n+ keeping the heavily doped nand p regions sufficiently far apart that there is no interaction between them. 5. Dielectric breakdown; here the electric field in a dielectric layer such as silicon dioxide (Si02) or silicon nitride (Si3N4) exceeds the dielectric strength of the material. This field causes very large currents to flow through the dielectric and can permanently alter its insulating properties. Commercially available power MOSFETs use sufficiently thick dielectric layers such that the electric fields within them never reach the critical value necessary to initiate breakdown. Since both zener and dielectric breakdown have been eliminated as potential causes of normal breakdown in power MOSFETs, we will examine the first three in more detail. Following this section, the phenomenon of latch-back and how modern power MOSFETs are designed to avoid it is discussed. Finally the temperature dependence of breakdown voltage and leakage current is examined. SUBSTRATE This Cross Section of an n-Channel VDMOS Power FET Shows How the Polysilicon Gate is Located Relative to the Source and Body Diffusions Figure 3 Causes of Normal Breakdown in Power MOSFETs 1. Avalanche breakdown [2] This phenomenon, as its name implies, is a sudden avalanche of mobile carriers caused by the increased electric field present within the depletion regions at the body drain pn junction. Electrons or holes that enter the depletion regions acquire sufficient energy from the electric field to knock bound valence electrons out of the silicon lattice atoms in that region. If one electron or hole produces on the average less than one additional carrier then the leakage current is not increased. There are five different phenomena that can cause normal breakdown to occur in semiconductor diodes and transistors under excessive applied voltage. Using Figure 3 as a guide, these five effects are [1,2]: 1. Avalanche breakdown; this breakdown is the dominant effect in commercially available power MOSFETs, and occurs when the electric field in the vicinity of the body-drain pn junction increases to a critical value. If, however, one or more additional carriers are produced and these extra carriers each produce one or more additional carriers then avalanching ensues. The depletion regions around the body-drain pn junction must be wide enough so that the mobile carriers can gain sufficient energy from the local electric field to initiate this process. 2. Reach-through breakdown; this breakdown is a special case of avalanche breakdown which is caused by the depletion region in the n - type epitaxial layer reaching the heavily doped n + substrate. 3. Punch through breakdown; this breakdown occurs when the depletion region of the reverse biased body to drain junction reaches the heavily doped n + source diffusion. The mathematics for describing this effect are already known from the analysis of gaseous breakdown phenomena. When this analysis is applied to the semiconductor case, the carrier multiplication factor can be derived. Basically it is [2] 4. Zener breakdown; a high electric field (on the order of 106 Vlcm) initiates this type of breakdown. There is a finite probability that electrons in their covalent bonds will be excited directly into the conduction energy band at the junction. These high electric fields can only be reached in heavily doped p + In + junctions, with resulting breakdown voltages < 6 volts. This type of breakdown is avoided in commercial power MOSFETs by (1) where VB is the junction breakdown voltage, VR is the applied reverse voltage and N is a numerical factor which depends upon the type of semiconductor crystal 2·50 I used (N = 3 to 6 for silicon). As VR approaches VB, M approaches infinity and the junction breaks down. is a major factor in the design of an optimized power MOSFET. If the epitaxial layer is too thick, the device will have an excessively high on-resistance for its breakdown voltage specification. Conversely, if the epitaxial layer is too thin, reach-through breakdown occurs below the desired breakdown voltage rating. Avalanche breakdown occurs when the maximum electric field in the vicinity of the junction reaches a critical value. Since the critical field in silicon is about 3 x 105 V/cm for impurity concentrations less than 10 16 atoms/cm3 [1], the breakdown voltage of a planar diffused pn junction is determined to a first order by the doping concentration on the lightly doped side [2]. This result follows from the derivation of the breakdown voltage for the one-sided step-junction (OSSJ) model. In this model, the acceptor doping concentration on the p - type side is much greater than the donor doping concentration on the n - type side. To a good approximation, the breakdown voltage of a power MOSFET is determined by the impurity concentration in the lightly doped epitaxial layer. 2. Reach-through breakdown This mode of breakdown occurs when the expanding depletion region in the n - type epitaxial layer reaches the heavily doped n + substrate. The spreading of the junction depletion region is inversely proportional to the square root of the impurity doping concentration [1]. As the depletion region enters the substrate, it begins to spread much more slowly, and the electric field rises rapidly towards the critical value necessary to initiate avalanching. When it reaches this critical value, localized avalanching occurs, and the device breaks down. A 100 volt power MOSFET requires a background (epitaxial layer) concentration of 3.5 to 6 x 10 15 atoms/cm3 , while a 500 volt MOSFET requires a lower concentration in the region of 1 x 10 14 atoms/cm3[3]. Since the resistivity of the epitaxial layer is inversely proportional to the dopant concentration, a high voltage MOSFET has a higher onresistance than a low voltage counterpart with the same die size. In almost all available power MOSFETs, the on-resistance is approximately proportional to the breakdown voltage raised to the 2.5 power [4]. This relationship is shown in Figure 4. 1 Commercially available power MOSFETs are designed by first choosing the background concentration to give the required avalanche breakdown voltage. The epitaxial layer thickness is then chosen so that at the avalanche breakdown voltage, the depletion region in the epitaxial layer just reaches the substrate. This epi layer selection process minimizes the device on-resistance for a given breakdown voltage and die size. 3. Punch-through breakdown This effect occurs when the widening depletion region at the body-drain junction reaches the heavily doped n + source diffusion. The field in the body depletion region sweeps electrons from the source across the reverse biased body-drain junction. The leakage current increases rapidly as a consequence. 1000 i I iI: ~ This breakdown mode is rarely observed in commercial power MOSFETs. They are normally designed to be avalanche breakdown limited. 100 ~ iii0: W iii ~ o ,. The Cause of Latchback and Its Avoidance [1] In power DMOS structures, the source-body contact is made some distance from the channel region. This contact shorts the emitter and base of the parasitic npn transistor (pnp for a p-channel MOSFET), formed by the source, body and drain regions. Figures Sa, b and c show this for the VMOS, LDMOS, and VDMOS structures, respectively. ~-~.~~~~~~~~,~.~~~~~,~~ BREAKDOWN VOLTAGE, BVDSS M The Observed Relationship Between R'DS(on) Multiplied by Chip Size (R'DS(on» and Breakdown Voltage for DMOS Power FETs, Shows That BVDSS is Proportional to R'DS(on) Raised to the 2.5 Power Figure 4 The source and body diffusions form a distributed series of npn bipolar transistors with their bases separated by the resistance of the body region below the source. To explain the phenomenon oflatch-back, a simplified model of the DMOS structure is used. This model, shown in Figure 6, consists of the gate It is important to ensure that the epitaxial layer is no thicker than necessary, if the MOSFET is to have minimum on-resistance. The epitaxial layer thickness 2·51 - SOURCE • BODY GATE -------------------------\ n+ a) VMOS Structure DRAIN SOURCE • BODY GATE DRAIN b) LDMOS Structure SOURCE • GATE BODY c) VDMOS Structure DRAIN Cross-Section and Circuit Models This Diagram Shows Distributed Parasitic npn Bipolar Transistor Inherent in the Three Common Power DMOS Structures Figure 5 2-52 DRAIN r--'VV'.,---£.---A/VI"---fE:--~---+! GATE 1---0 IT ----- BVCEO BVCES DRAIN·TQ.SOURCE VOLTAGE (V) SOURCE • This Curve Shows Idealized Latchback Occurring in a DMOS Power FET Where BVCEO is 50% of BVCES Figure 7 BODY The Simplified n-Channel DMOS Model, Used to Explain the Phenomenon of Latchback, Includes Only the Parasitic Bipolar Transistors at the Extreme Edges of the Body Diffusion Figure 6 curve, where the BVCEO is 50% of the BVCES or BVOSS. The trigger current IT is the value of avalanche current at which the transition to BVCEO occurs. Not surprisingly, this current can be shown to be [1] controlled channel and only the two npn transistors at the extremes of the body diffusion [1]. The bases of these two npn transistors are separated by a resistance Rp. The body contact resistance is modeled by a resistance RB. The body-drain diode is also included, and serves as the avalanche current generator in the model. This model is equally applicable to all three power MOSFETstructures mentioned above, despite their cross-sectional differences. (2) where VBE (Q2) is roughly 0.6 volts. Now that the mechanism which causes latchback in a power MOSFET has been described, at least two methods for preventing it, based on the model shown in Figure 6, can be listed. These are [1]: With the gate short-circuited to the source, the leakage current through 01 increases as the applied VOS reaches its avalanche breakdown voltage. This current causes the voltage drop across resistors Rp and RB to increase. If this drop is allowed to reach 0.6 volts, 02 will begin to conduct current. When this happens, the sustaining voltage of the MOSFET suddenly drops from the avalanche breakdown voltage of diode 01 to a lower value. This lower sustaining voltage is equal to the collector-emitter breakdown voltage of 02 under forward bias conditions. 1. Reduce the value of Rp + RB so that any lateral body-current flow does not result in the 0.6 volt drop necessary to tum on 02. 2. Change the shape of the body region such that the current flow in avalanche breakdown bypasses Rp (Rp is usually> > than RB). Most of the modem commercially available OMOS power FETs use technique #2 to prevent latch-back. Figure 8 shows how this can be accomplished in both vertical OMOS and V-groove type devices. The heavily doped p + regions that extend more deeply into the epitaxial layer form an integrated bypass diode that effectively diverts avalanche current away from the p --: type body region (and hence Rp). The equivalent model for this modified structure is shown in Figure 9. It has been experimentally verified that if the avalanche breakdown voltage of 02 is less than that of 01, the circuit will not suffer from latch-back. Most bipolar transistor manufacturers do not usually specify the collector-emitter breakdown voltage under forward bias conditions. They specify two other values of collector-emitter breakdown voltage. These are the BVCEO (with the base left open circuit), and the BVCES (with the base short-circuited to the emitter). The BVCES of transistor 02 is equal to the avalanche breakdown voltage of diode 01, which sets the BVOSS limit of the power MOSFET. The BVCEO of 02 approximately equals its collectoremitter breakdown voltage under forward bias conditions. Most bipolar transistors, including the parasitic device in a power MOSFET, exhibit a BVCEO that can be as low as 20% of their BVCES. Thus the latched-back sustaining voltage of a power MOSFET can be considerably lower than its BVOSS. Figure 7 shows an idealized latched-back breakdown voltage The Temperature Dependence of Breakdown Voltage and Leakage Current As mentioned previously, the breakdown voltage of a power MOSFET is determined to a first order by the doping concentration in the epitaxial layer. Since this 2·53 - SOURCE • BODY GATE p+ (a) n+ DRAIN SOURCE • BODY GATE (b) n+ DRAIN A Practical Device Modification to Prevent Latchback Is the Inclusion of an Integrated Bypass Diode, 02, as Shown In the Modified VDMOS and VMOS Structures Respectively Figure 8 2-54 " DRAIN D, ~________~____~~____~____~__~~E RB SOURCE & BODY The Circuit Model of CMOS Power FET with an Integrated Bypass Diode Is Very Similar to That in Figure 6, but Now Includes Diode D2 Figure 9 concentration does not vary substantially with junction temperature, one would expect the device breakdown voltage not to vary with temperature either. which works out to be approximately + 8% per °C, or a doubling of leakage current for every 12°C rise in junction temperature. In practice however, there is a slight variation in breakdown voltage with temperature (about a 5% increase per 100°C rise in junction temperature). This is due to a second order effect known as "phononassisted electron scattering." At elevated junction temperatures, the increased vibrational energy of the silicon lattice atoms causes the mobile charge carriers in the epitaxial layer to move in an increasingly random pattern, relative to the direction of the electric field. The body-drain junction leakage in a power MOSFET at a junction temperature of 150°C can therefore be more than three orders of magnitude greater than that at room temperature. This can limit the usefulness of a power MOSFET that exhibits excessive junction leakage current (say several hundred /-LA) at room temperatures, when operated at temperatures near its maximum data sheet limit (typically 150°C). Frequently, however, transistors with high leakage currents at 25°C do not have the same temperature coefficient as one with low leakage. Thus, the mobile carriers do not attain as high an average kinetic energy for a given electric field. Maximum kinetic energy is attained when the carriers move parallel to the field. Consequently, the value of the critical field required to initiate avalanching increases with temperature, and so does the device breakdown voltage. There are additional sources of leakage in a power _ MOSFET originating from the package in which the die is mounted. In a properly packaged device, these leakages are of the order of a few nA and do not constitute a significant part of the total leakage. In a device which has been defectively packaged, however, the additional leakage can reach several hundred nA and mayor may not be temperature sensitive. This situation is rarely encountered in properly manufactured and tested devices. The drain-to-source leakage through the body-drain junction, on the other hand, is highly temperature sensitive. The leakage current in a reverse biased pn junction is mainly proportional to the square of the intrinsic (i.e. undoped) carrier concentration in silicon (Ni). The value of Ni2 can be written as [2]: References [1] R.A. Blanchard, Optimization of Discrete High Power MOS Transistors, PhD. Thesis Dissertation, Department of Electrical Engineering at Stanford University, December 1981. (3) where K is a constant independent of temperature, Eg is the energy band-gap of silicon (1.12 eV) and K is Boltzmann's constant. One can see that the T3 term completely dominates the leakage current over a wide temperature range. The approximate fractional change in the leakage current of a reverse biased silicon pn junction is thus given by [2] [3] S.M. Sze and G. Gibbons, "Solid State Electronics," September 1966. =1 - (3- + ~) \VR = Constant IL1(aIL) aT 2 T Kl"" [4] Chenming Hu, "A Parametric Study of Power MOSFETs," PESC 1979 Conference Record. -- - rrn [2] David M. Navon, Electronic Materials and Devices, Houghton Mifflin Company, 1975. (4) 2·55 2.13 Modeling 2.13.1 SPICE 2: Simulation of High Power MOSFET Introduction The power MOSFET offers superior performance due to its high switching speed, low power voltagedriven gate requirement, ease of paralleling, and absence of secondary breakdown phenomenon that troubles the Bipolar Junction Transistors. Herren Jr., Nienhaus and Bowers developed a computer model for high power MOSFET[l]. This model takes into account the deviation ofthe device transfer characteristic (Figure 4c) from the ideal square law characteristic by the inclusion of a lumped source resistance. One of the chief attractive features of the model is that its parameter determination procedure requires only the manufacturer's published device data. constant), and KD (the channel length modulation constant). In the SCEPTRE version of the model, CGD and CDS are non-linear capacitors. However, CGD is modeled as a constant capacitor in the SPICE 2 version ofthe model[l]. CDS is given by: In the following article, the computer model is briefly described, and the model parameter determination procedure for the SPICE 2 program is explained. A computer model of the device type IRF330 was generated based on this procedure. Simulation results of both resistive and inductive switching circuits using this device are presented. In the SPICE 2 version ofthe model values of = 1.0 and n = Y2 have been assumed. Thus, the model parameters to be determined are 1) VT. 2) (3. 3) KD, 4) RS. 5) RD. 6) RG. 7) CDO. 8) CDG. 9) CGS. CDO CDS (1 + v~sr' where = CDO = capacitance value at zero VDS = junction contact potential = PB n = an exponent between 'h and Y2 RO SPICE 2[2] is a network analysis program using nodal analysis techniques and has the advantages of programming ease and relatively fast execution time. Version 2E2 was used in the following programs. VGO ~~. a Ra Jo tas Vas + High Power MOSFET Model[l] _ Figure 1 shows the high power MOSFET model for an n-channel MOSFET. A similar model exists for the p-channel MOSFET device. The substrate and the source are assumed to be shorted internally. JD is a non-linear current source depending on VGS, VGD, VT (the threshold voltage), [3 (the device conductance CDS Rs High Power MOSFET Model (Ref. 1) Figure 1 2-56 Figure Z shows the SPICE Z built-in level-l n-channel MOSFET model[Z] based on the model proposed by Schichman and Hodges. This model is adapted to the requirements of the high power MOSFET model as indicated in the next section. n-channel and p-channel devices are taken care of by using different built in SPICE Z models, viz., NMOS and PMOS. For n-channel MOSFETs VTO, the gate threshold voltage is considered positive for enhancement mode devices and negative for depletion mode devices. For p-channel MOSFETs, VTO is negative and positive for enhancement mode devices and depletion mode devices, respectively. -VDS Output Characteristics - To Locate P1 Thru P6 Figure 3 RD CGD e) P6, a point on the saturation (ohmic region) line. It may be more convenient to select this point from the saturation (low VDS) characteristics provided by the manufacturer. CBD DBD G B 10 STEP 3: Choose VTl, the approximate intersecting point of the transfer characteristic with the I D = 0 axis (Figure 4c), as the starting value ofVT· DBS CGS CBS CGB RS 80 ,",I PULSE TEST 410v VG~=J5V SPICE 2 Built-In MOSFET Model (Ref. 2) Figure 2 Determination of Model Parameters[l] ~= 50V= i==' Following is a step by step procedure to determine the model parameters based on Reference 1. F= J '5V ~ STEP 1: Figure 3 shows a set of output (dc) characteristics drawn in an exaggerated manner. Choose three characteristic curves Ll, LZ, and L3 corresponding to gate-to-source voltages VaSl, Vasz, and VaS3, respectively, according to the following guidelines. a) Ll-curve with the highest drain current b) L3-curve close to I D = 0 line c) LZ-curve approximately half-way between the above two curves. 1 4j"= 50 100 150 200 1= F= 250 300 Yos. DRAlN·yo-SOURCE VOLTAGE (VOLTS) a) Typical Output Characteristics 5 .1 . .1 .l'';~v.t-- aD ,:£8 PULSE TEST JV 4 STEPZ: Choose points PI (IDl, VDSl), PZ (IDZ, VDSZ), ... P6 (lD6, VDS6) as per the following guidelines. a) PI, any point well into the pinch-off region on line L1. b) PZ, on line LZ such that VDSZ = VDSl(VaSl-VaSZ) c) P3, any point well into the pinch-off region on line L3. d) P4 and P5, two points as far apart as possible on the near horizontal straightline segment of Ll curve. VGS=SOY W 3 I I JI 2 1 I J 45V- ~ 40V_ II - 2 4 6 8 Yos. DRAIN-YQ-SOURCE VOLTAGE (VOLTS) b) Typical Saturation Characteristics IRF330 Characteristics (Ref. 3) Figure 4 2·57 10 - 2000 Jas = 80 #,S PULSE TEST VDS = 10DV ' .. 1 MHz 1600 TJ "" +125"C TJ = 25"C ................ TJ = -55"C'-... 'NJ I\\' _\ 1\ ... ,J... rH. Clas rN /'/ ..a '\ t-- 1 • • Vas. GATE-TO-SOURCE VOLTAGE (VOLTS) ~10 H H ~ 9 VDSo DRAIN TO SOURCE VOLTAGE (VOLTS) c) Typlcal1l'ansfer Characteristics STEP 4: Rs d) Typical Capacitance Vs. Draln-ta-Source Voltage IRF330 Characteristics (Ref. 3) Figure 4 ( Im)Vz(VOS2 - VT) - (VOSl - VT) = ....>..I..:::D'-"'2"--_ _ _ _ _ _ _ _ __ (1m ID2)Vz- 1m For the SPICE 2 model, RS = Rs. STEPS: Let a X x (VOSl - ID4 * Rs - VT) y = (VOSl - IDS * Rs - VT) KD = ID4 y2 (VDSS - V OSl + VT) - IDS x2 (VDS4 - V OSl + VT) IDS x 2 - ID4 y2 For the SPICE 2 model, LAMBDA = l/KD. If the characteristic curves are horizontal in the pinch off region (without any discernible slope), this step may be skipped and KD = 00. STEP 6' 13 = . 1m { (VDSl- VOSl + VT)} (VOSl-IDl Rs- VT)2 1 + KD IfKD = 00 then 13 , = IDl (VOSl- 1m Rs - VT)2 For the SPICE 2 model, KP = 2*{3 STEP 7: VT to be obtained by solving (VDS3 -KVDOS3+ VT)} ID3 = 13 (VOS3-I D3 Rs - VT)2 {l + One way to achieve this would be to solve for VT, iteratively, the rearranged equation. ID3 VT = VOS3 - ID3 Rs- (VDS3- V OS3+ VT)} KD 2-58 IfKD = 00, then (iD3 VT = VGS3-ID3Rs-,,~ For the SPICE 2 model, VTO = VT. STEP 8: Repeat steps 4, 5, 6, and 7 until parameters VT, R s , KD, and 13 converge. It may be necessary to carry out a number of iterations before the parameters converge. STEP 9: Letb ~ 2(VGS6- VT-VDS6) ID6 c ~ _1__ ~(V--,D=S6~-----2ID~6~R:..:::s~)~(2:....:.V~G~S~6--:-~ID~6:.:R~s_--=2V..:..T~-~V~D~S~6) (3ID6 ID62 RD= -b +Jb2-4c 2 --~-- For the SPICE 2 model, RD = RD. STEP 11: Refer to the switching time test circuit (Figure 5). A simplified equivalent circuit during turn-on and turn-off is shown in Figure 6. Note: Since P6 lies on the ohmic region line, determining V GS6 is somewhat arbitrary. However, RD is not found to be critically dependent on this. STEP 10: Refer to the capacitance vs. VDS curves (Figure 4d). a)CGD = Crss(athighVDS) For the SPICE 2 model, CGS = CGD b) CGS = Ciss-C rss (at high VDS) For the SPICE 2 model, CGD = CGS c) CDO = Coss-Crss (at VDS = 0) For the SPICE 2 model, CBD = CDO/ (lxlO- lO ) and PB = 1.0 - +25V RL PULSE 11.n GENERATOR r----------------,I ! I I I I I R1 I v. II t_______ Note 1: CGD and CGS are approximated by constant value capacitances. Also, the units for CGS and CGD in SPICE 2 are farads/meter. This, however, does not create any error since the default values for channel length and width in SPICE 2 are 1.0 m each. 50n I OUT. , II , , I TO SCOPE R' 50n --------~ '0+ 001 SHUNT Switching Time Test Circuit (Ref. 3) Figure 5 R11IR2=R' Note 2: As pointed out in Reference 1, CGS and CGD have been interchanged in SPICE 2 MOSFET model, apparently an error. RG 'h~_ ' ( .!:IR1+R2VP Note 3: The unit for CBD in SPICE 2 is faradlmeter2 . The default drain area in SPICE 2 is 1 x 10-10 m2 . Simple Equivalent Circuit of Gate Input Figure 6 2-59 By adopting the above method, a computer model for the device type IRF330 was generated. The model listings may be seen in Figure 11 which shows a SPICE 2 program of a circuit using IRF330. Here, the NMOS model IRF330 along with resistor RF constitutes the device model. Let R' ~ R1R2 R1 + R2 V'p ~ VpR2 R1 + R2 RG1 = _ _T...oO::.::N~_ -R' V'p Ciss In V V'p- T The capacitor Crss is a highly non-linear function of VDS, especially at low VDS values, whereas it has been approximated as a constant value capacitor. This could be a source of error when using SPICE 2 with this model. The dynamic performance (rise and fall times) was found to be critically dependent upon the value of Crss chosen. where TON is the turn-on delay. Simulation with the Model To consider the turn-off delay, plot the load line on the output characteristics as in Figure 7. This intersects the ohmic region line at point Q. Find the gate-to-source voltage, VGS = VA, such that the corresponding pinch-off region characteristic passes through Q when extrapolated as shown. DC Characteristics Considering the turn-on process, The output characteristics, saturation characteristics, and the transfer characteristics were simulated with this device model. Comparing these simulated curves (Figures 8a, 8b, and 8c) with the characteristic curves provided by the manufacturer (Figures 4a, 4b, and 4c), we note that the model simulates the performance of the real device accurately both in the ohmic region and in the pinch-off region. However, in the area in which transition from one region to the other occurs, the model is less accurate. Then RG2 = _ _T...oO:::.;:FF,-=::---;- - R' V'p) Ciss In ( VA Switching Characteristics RGl The real test of a dynamic model is its ability to simulate dynamic behavior of the device in a circuit in a fairly accurate manner. With this in view, the model was tested with resistive loads and with an inductive load under switching conditions. a) Resistive Loads: i) Switching Time Test Circuit: This circuit, shown in Figure 5, is the test circuit adopted by the manufacturer for measuring the switching times at low voltages (Reference 3). The results of the simulation (Figure 9) indicate that, while the details of the waveforms (Figure 7C, Page 16, Reference 3) are not simulated accurately, yet the 'ON' and 'OFF' delays have the correct values. The rise and fall times are between 20 and 30 nsec while the actual device has typical values of 50 nsec. This discrepancy is probably due to the error introduced in simulating the nonlinear capacitor Crss with a fixed value capacitor. In fact, by changing Crss from 20 pF to 40 pF rise and fall times close to the manufacturer's specifications may be obtained. However, since IRF330 is a high voltage device, the value of 20 pF for Crss corresponding to higher VDS values was retained. + RG2 For the SPICE 2 model, RG = - - - - 2 Note: RG has to be included as an external resistance, since SPICE 2 MOSFET model has no built-in element for this purpose. - "os To Determine VA Figure 7 2·60 OUTPUT LfGENO: +: *: ves ~: 4. ';V VGS #: VGS VGS @: VG~ 5.tlV 5.6"V 10.11V VOS (VOLTS) !l.tI ? flllll[J+{I0 4.0000+00 6.0000+00 8 onOD+oo 1.0000+01 1.2000+01 1 4000+{)1 1.6000+01 ~ 6.51)110-01 6. SOIID-Ol 6. 51l /1LJ-O 1 6.5U40-"1 6.5fI JW-tJl J! 6.50 110-n1 m 2.6000+01 2.8000+01 3.0000+01 6.5040-01 .. '" _. N 6. 'JlIlln-lIl 6.51l4D-Ol 6.5fJ4D-1l1 6.50 /'0-01 2 2000+01 2.40flO+01 ::!llll <:3 3.2000+111 3.4000+01 3.6000+01 3.8000+1)1 ;5. ~g. .!!!." 4.0000+01 4. 2110D+() 1 4.4000+01 4.6000+01 4.8000+01 5.0000+01 5.2000+01 5.4000+01 5.6000+01 5.8000+01 6.0000+01 6.2000+01 6.4000+01 6.6000+01 6.80UO+01 7.0000+01 7.20UO+Ol 7 ,'1000+01 7.6UOO+Ol :II IX <: iii' < t:I III <: o 1u::::::::: 8.2000+rll 8. "000+01 8.6000+01 8.8000+01 9. OOOO+() 1 ~ Uggg!g~ - 9.6000+01 9.8000+01 6.504D-Ul 6. SOliD-Ol 6. S(JliIJ-Ol 6.50,,0-01 6.5040-01 6. 5(J/,O-O 1 6.50 LID-01 6. SO/tO-Ol 6.5040-01 6.50'10-01 6.50"0-fll 6.5()1ID-()1 6.5040-01 6.51)1,0-01 6.5040-01 6.5040-01 6.50"0-01 6.50 1'0-01 6 50',D-lll 6.50 110-01 6.50,,0-01 6.50"0-01 6.5040-01 6. 501iD-0 1 6.5""0-01 6.50"0-01 6.501,0-01 6.50"0-01 6.501'0-01 6.50 1'0-01 6.5040-01 6.5040-01 6.5040-01 6.501'0-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 2.0000+00 0.0 2. (981)-42 1 • aOOD+Ol 2.0000+01 0 10 (AMPS) 10 (MIPS) (+'#@=) ------------- III CHARACTrRISTIC~ 'I.OV 4. (1000+00 6.0000+00 8.0000+00 X + * .#@= * + , , + + + , , + + + + + < +1:) +111 + II + ... + b + < + + + + , • < ,I:) ,III , II · ... ,• in < # '" , , , · *, + + + + @ @ @ @ @ @ @ u~ Z III @ @I:) H @III @ II Z< # # # H # H # H H # H H # H # H # H H H H H I II #H b '" H H H + + + + + + + + + @ @ # # H H H H H H H H H + + + + + + + + + @ # H H < @ '" @ in :< @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ SAfURAT I ON CHARACTER I ST ICS VOS (VOLTS) (AMPS) (+*N@=I------------0.0 1. ooon-o 1 2.0000-01 3.0000-01 4.0001l-01 5.0000-01 6.0000-01 7. 0000-01 8.0000-01 9.0000-01 1.0000+00 1.1000+00 1.2000+0fJ 1.3000+00 1.4000+00 1.5000+00 1.6000+00 1.7000+00 1. 8000+00 mm e~ ..., ~ 1.900D+1H1 iil m Jl=N cagle 2.0000+00 2.1000+00 2.2000+00 2.3000+00 2.4000+00 2.5000+00 2.6000+00 2.7000+00 2.8000+00 2.9000+00 3.0000+00 3.1000+00 3.2000+00 3.3000+00 3.4000+00 3.5000+00 3.6000+00 3.7000+00 3.8000+00 3.9000+00 4.0000+00 If. 1000+00 !; (')3 CD:::r C .,ii~ -!l g !:a al ~~ t:~ggg:gg ~ m _ 0< r. '-I !!J I 4.4000+UO ,.. 5000+00 4.6000+00 4.7000+00 4.8000+00 4.9000+00 5.0000+00 5. 1000+00 5.2000+00 5.3000+00 '0 (AMPS) 10 ?0980-42 9.2090-02 1.8210-01 2.6970-01 3.5-111 0-0 1 lL 34110-01 5.0910-01 5. "1570-01 b.2830-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.50'10-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-0 ( 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 6.5040-01 x x 5.0000+00 1.7500+00 2.5000+00 1. 2500+00 0.0 x +XX +XX +·X + *X + *X= + *X= + + + + + + + + + + + + + <+ G) + m + II + ~ Q + + <+ + + + + + + + + + + + + + + + + + + + + + + + *#X *#X. *#x. *#@= . *#@~ ·N@= * /IX * • I/@- • #@c #@= * #f!:::. • #@= #@ = • • • #~. # @= # @= # @ * # " ·" <. G) " m" II " ... " in· <" " ·" " ·· " " " = @ # = @ # = @= # @= # @ N # = @ # = @ = @ # = ~ m @. # @ N @ # .# = @ II = @ I .... = ?Q @ # @ I @ I I = @ < = @ @ 1# ~ ~'\ m I m I i:> III i:> < II GO ~ < I @ @. DC TRANSrrR CURVE VGl (VOLlS) 10 (AMPS) I(Vll ) (AMPS) ~ n.n fJ.n l).n(JOD-O? 1.00(11 1-11' 3.0001}+{JO 3.05UO+00 3. 1DOD+OU 3. 1500+110 3.200D+1I1I 3.25lH}+(UI 3.301J[)+IlO 3.31)011+110 3.1101l11+00 3.45I1D+OO 3. suulHon J.55(1)+(10 3.6IlilO+OO III 3.6500+00 mo "'m 3. Boon+un .... "11 3.700{H(JO 3.7500+11U !!l,,,, .., 0. '" 1. 8~1I0+f1n 3.90110+00 1.9 r)IJIl+(JO 11.00(J[)+OO !!!!cn cg.. ::rc 03' CDD>- II.O')OD+IIII ... iiI!!!. '1.1000+(1) 4 15110+110 4.200D+1I1I .. !I. 0 -CD'" ::!.:u ~= '1.2500 i UO 11.300U+1I0 ll.35UO+00 ".400()+on 4.45110+01 1 11.5000+1H1 'L 5500+01J '1.600D+CJlJ !;l~ II> ~. 6500+00 4.700D+00 11.7500+00 11.8000+00 II. 850D+(J1) 11.9000+(10 11.950D+OO 5.UOOO+Oll < I:) en "< o !:i III - j'"'""'"" 5.100D+Qn 5.1500+00 5. 2000+01J 5.2500 - -111 2. ~991l-(I1 3.91180-111 5 19~D-Ol 6.5(1110-01 7.90?1J-1I1 9.189D-(I1 1.09 t )[)+1111 1.25BD+nO I. ~~ 71l+f)O 1.6010+011 1 7810+IH) 1 9661HIHl 2.156[J+0[) 2.3500+(JO 2.548D+01I 2.75UO+OIl 2. S'~5D+OO 3.1b'ID+OO 3.376D+OO 3.5900 i OO ,.8080+00 ~. 0290+no 11.2520+00 4.117/D+IIIJ ~. 7050+0 f J ~. 'J360+0n 5.168D+()O 5.4030+0U 5.6390+00 5.8780+UO 6.1180+00 6.360D+OO 6.6n1.JD+()1) 6.81190+00 + < C III II ~ + 0 0 < + + + + + + +. --------------------------------------------------- I LEGEND + * _ (It CD.. : '1(2) 1('12.) TIME \1(2) - - - - - - ----- ---- - -- - -- - -- 501)00+110 -- - - - - - - - - -- - --- - - - -- (+)----------------- -5 0000+00 (*)----------------- -30000+00 00 10000-08 20000-08 30000-08 40000-08 50000-08 60001;)-08 70000-06 80000-08 90000-08 I 0000-07 11000-01 12000-01 I ]OOO-l17 , 4000-07 15000-01 16000-01 I 7000-01 18000-fl' 19000-01 20000-01 2 1000-01 22000-01 2]000-01 24000-07 25000-07 26000-07 2 7000-07 28000-07 29000-07 ] 0000-07 1 1000-07 3 2000-07 3 3000-07 34000-07 3 5000-07 3.6000-07 3 7000-0, 3 8000-07 3 9000-0r 40000-07 4 1000-01 4.2000-07 43000-07 44000-01 4 5000-07 46000-07 4 7000-07 4.6000-07 49000-07 5.0000-07 51000-01 52000-07 53000-07 511000-07 5 5000-01 56000-07 5.7000-07 5800D-07 59000-07 60000-07 61000-07 62000-07 6300D-07 64000-07 6 5000-01 66000-07 6 7000-07 6 8000-07 6 J}OOO-07 70bOO-07 7 1000-07 72000-07 73000-07 74000-07 75000-07 7 6000-07 1 7000-07 7 8000-07 7 9000-01 80000-01 8 1000-07 82000-01 8 3000-07 8 11000-07 8 5000-07 86000-07 87000-01 88000-01 89000-07 90000-07 9 1000-07 9 2000-07 9 3000-01 94000-07 95000-07 96000-07 97000-07 9 6000-07 9.9000-01 10000-06 00 -1 2630-16 22440-16 24670-16 2 3260-16 -21310-16 76750+00 80200+00 8 3120+no 811850+110 8 6790+00 86750+00 90420+00 9 16110+00 930')0+00 94080+00 9 4960+110 9 Hl0+00 96350+01) 96890+00 9 1350+00 97150+00 98080+00 98310+00 98610+00 988:<'0+00 98990+00 991110+00 99270+00 99380+UO 991170+00 9 9,)50+00 'I 96~O+fJO 99670+00 9 97~0+00 9 9760+00 99800+00 99830+00 99650+00 99880+00 9 9890+00 99910+00 99920+00 9 9930+00 999110+00 9 9950+00 99960+00 99970+00 99970+00 9 9980+00 99980+00 99980+00 99980+00 <} 9990+00 <;I 9990+00 9 9990+00 23270+00 19610+00 I 6860+00 1 4360+00 I 2:<'110+00 1 1010+00 98650-01 8 11390-01 7 1870-01 61200-1)1 52100-01 411360-01 3 7770-01 3 2160-01 2 7380-01 23320-01 19850-01 1 6900-01 111390-01 1 .. : ~260·01 1 0430-01 8 8850-02 7 '630-0~ 6111120-02 511820-02 46700-02 391110-02 33860-02 28810-02 24550-0:<' 2 0880-02 t 1800-02 1 5130-02 1 2910-0:<' 10970-02 9 3630-03 7 91180-03 6 7910-03 5 1580-03 49270-03 41110-03 35160-03 3 0200-03 :<' 5960-03 :<' 2140-03 SPICE 2 Simulation Waveforms Switching Time Test Figure 9 2·64 -- - - -- I 5000+01 .. _." .. It'II""'''•• ''_'' •• ii) Switching Efficiency :*!~~~!*~!~!!~~.: One of the important considerations for the operating frequency in switching applications is the efficiency of the switch. Reference 3 (Page 18) describes a test performed to determine the efficiency of the switch at different frequencies with resistive load. Figure 10 shows a SPICE 2 diagram which simulates the test circuit. Figure 10 also shows additional SPICE 2 circuits to measure the device dissipation and the source power delivered. The measurement principle is as follows. TEST Of MOSfET MODEL ---------------------------------------------------------------------- :~~~~~~!~~-~:~!:!~~:~-~:~:~~!~~~!~~-~~-~~~-~~~-:-~:~!::-~~~::!~~~~~--- VO 1 0 PULSEjO. Rl 1 MOS1 RL " VO 0 01 0 Cl 6 7 2.ur C2 8 9 2 Itltl + flV =...!... Itl + C2 C2 tl =...!... C1 ur ~~~-~-~-~:-~-~-------------------------------------------------------- RG23665 .MODEL IRF310 NMOS(V10"3.60'18 KP=ll Illl lAMBDA=O. RS=.1293 CGS=20 PF !------------------:~~:~~~-~~-:~~:~.:~-~~:~--~~:.:~:~~-~:~:~:~!--------,TRAN 20 NS 6 2US 1.8US UIC ,PLOT TRAN V(41 V(21 V(ll I{VOI I{VZll I (VZ21 PRINT TRAN I(VZ1) V(6.7) IIVZ21 V(8,91 .. ~~!~~~~-~~~~!~:~~~~-------------------------------------------------[NO SPICE 2 listing for the Circuit to Test SWitching Efficiency Figure 11 Figure 12 shows the simulation results, along with experimental data from Reference 3. It is found that the model predicts the efficiencies at different frequencies in a reasonably accurate manner. T T Note: The 1000 Mil resistors across C1 and C2 are included to meet SPICE 2 programming requirements. By selecting Cl = C2 = T, fl VC1 = PI = average power dissipated in MOSFET ID. .. fl V C2 = P2 = average power delivered by source il Switch . . Power mput-MOSFET losses Efficlency = ---....!....-------Power input ~ 10 - 3 AMPS 9. • 96 I I SIMULATED I M o /~, R1 sn 0 \R? . ~ ~OS1 0 - I'r-- 95 93 R:on r-r-.. --EXPER!MEJAL (Raf 3) 97 9. IRF33~...... _........ 01 RC2 6 9 lOOO.MEG In one period, T, Cl 10 0 1NS ,INS .9999U5 2 US) 5. 3 0 0 IRrl30 100 DC -300 V POL VIZ) 4 0 5 " 0 0 0 0 .01 ReI 6 7 1000 MEG VZ170DCO.V G2 0 8 POLY(21 5 0 5 " 0 0 0 0 Gl = VDSiD = instantaneous power dissipated in MOSFET G2 = VDiD = instantaneous power delivered by source flV 2 4 5 5 6 '0 2. . CONDITIONS 50% DUTY CYCLE TJ = 10O"C RG = 5 OHMS = 300 ViLTS ro 'DO 200 5DO '.DO FREQUENCY (kHz) 0 Switching Efficiency vs Frequency Figure 12 b) Inductive Load Switching: Figure 13 shows a circuit (Page 18, Reference 3) that was used in order to study the ability of the model to simulate switching circuits with inductive loads. The diode was modeled as a near ideal device, and stray inductances were not included in the simulation model. A capacitive speed-up network was included in the MOSFET gate drive circuit. The inductance value was chosen to be large so that the current remains essentially constant over the interval of interest. The circuit was simulated both under ON and OFF transient conditions. SPICE 2 listings for switching off are given in Figure 14. The ON and OFF simulated waveforms are shown in Figures lSa and lSb, respectively. YO -=-3OQV 68 50'1 .. _ ...... va SPICE 2 Simulation Diagram to Test Switching Efficiency Figure 10 2·65 then at approximately 300 volts. VDS now falls at such a rate as to maintain the internal gate-tosource voltage, VOS, (across COS) ofthe device, equal to the value required to sustain the load current. In this case, this value of VOS would be 4.65V as may be seen from the output characteristics. D1 In Figure l5b, the gate voltage is switched off at 500 nsecs. Initially, a negative voltage appears across the gate-to-source, though the final voltage would be zero. This is due to Cl, the speed up capacitor. VDS now rises to maintain the internal gate to source voltage, VOS, once again at approximately 4.65 volts. ID continues to flow through the MOSFET. When VDS reaches a value a little more than 300V, the diode takes over conduction and the device current drops quickly from full value to zero. Switching Circuit with Clamped Inductive Load (Ret. 3) Figure 13 ***************** :*!~~~!*~!~!!~~*: !:~~~~:-~~~::~-~~~:~------------------------------------------------- :~:~:~~~~~~-~:-~~~~~!~~:-~~~!~~~~~-~~~:~~~~-:-~:~~~:-!~~::~~:~~~-----Rl 1 2 50.0HMS R2 2 3 1.K Cl R3 Vl Ll 2 3 1 6 3 OlUr tC=10 v 0 1.K 0 PUlSEI20 5 O. 500 NS .1N5 5 5.Htt Ie".. 3.0A In Figure l5a, the rise times of ID and VD are 0 nsec and 50 nsec, respectively. The corresponding values from Reference 3 are 80 nsec and 30 nsec. In Figure l5b, the fall times of ID and VD and the time delay (off) are 0 nsec, 50 nsec, and 25 nsec, respectively. The corresponding values from Reference 3 are 40 nsec, 40 nsec, and 60 nsec. A major discrepancy is observed in the rise and fall times of the drain current. This may be attributable to the likely presence of stray inductances in the experimental circuit. lNS 1.5 1 15) 01 5 6 0 V2 0 6 DC -JOO.V MOSl 5400 IRF330 IC:::2.3. 10., O. HODEL 0 0 *-----------------------------------------------------------------.--. RG 3 4 66.50HMS ,HODEL IRF330 NHOSIVTO:::3 60146 KP=13 44 LAMBDA=O RS= 1293 CGS"'20 PF :------------------~~~:~~~-~:-:~~:~:~-~~:~--~~::.~~::-~:~:~:~!--------.TRAN S.NS 950.N5 450.N5 ute .PLOT TRAN V13) VIS} IIV21 *~~!~~~!-~~~~~~~;,~~~~!-----------------------------------------------END SPICE 2 Listing for Inductive Load Circuit (Switch-Off Conditions) Figure 14 In Figure l5a, the gate voltage is applied at 500 nsecs. The voltage at the device gate quickly rises above the final value of 10V due to the presence of the speed-up capacitor, Cl. Until the gate input capacitor, Ciss, charges up to the threshold voltage, VT, the device remains in the cut-off region. The device starts to conduct at about 515 nsecs commutating the free-wheel diode. Since no parasitic elements are considered, this transfer takes place almost instantaneously. VDS remains until Note: When simulating a switch in series with an inductor using SPICE 2, the voltages across the switch and the inductor are sometimes inaccurately computed under switch off conditions (i.e., switch current and inductor current = 0). The voltages may even, erroneously, appear to be oscillatory. The more stringent relative error tolerance (RELTOL) value used in the program in Figure 14 is to avoid this source of error. 2..fi6 ~~; lEGEND: +: VI 3) ': VI 5) 0: IIV2) TIME fl. n 5.0000+00 1.IlQnUt()l 1.5000+01 ? nouo+nl (*) ----------------- o. (l 1.0000+n2 2.OIHIU~I)? 3.o0QO+()? II. (j{)OD+02 0.0 ?()(J(J() I [)" II.OClIIO+llli fi .IJOUO+OO + + + 4.7000-111 I . 3990-1)3 1.396U-[l3 1.39,,0-03 I. 3911J-03 11.75110-07 1.3SQU-(J3 4 800U-1I1 4 8500-01 1.38l0-03 1.3850-03 1.383U-01 ~.6511D-07 3en ".9110D-07 ID- 4.950[)-1l7 ~~ :IN '"~ 5. OUOo-o 7 1.3810-113 I. J 191J-03 5.0500-07 1.181111+01 r ...,~!!! 5. llIUU-O 5.1S0D-OJ ~~iii' 5.2500-0 I 5.3IJOO-07 .!!!3 5.351)()-flT 5.4001J-lJl cS' g, ~ 5.2o0D-Or ~Qi1f ::I 5. 4~IUD-07 5. ,000-07 ~ . 55(1)-(17 .!.$:;: ~< ~lr S'3 7", o a. -7 IH'OO+IJII 1.40 )0-03 ',.6uoO-O" '0'11 ~.600D-07 5 650IJ-f17 5.7000-117 5.75l10-07 5.8000-Cl7 5.8500-07 5. 900U-IJ I 5.9500-07 6.(JUOD-07 6.0500-07 G.10 I )O-07 6.1500-07 6. 2[IIJI)-(1 I 6.250[)-07 6.3000-07 6. 15OfJ-fJ7 < + I:) ,en +< + 0 + !:j + en +- # # # - • < 0> # ;;: '< , 0 # *, !:j en * - U "II # en 0# H + ,1 1.3111f)+-()1 1.311}()+1J1 1.3Ub(J+\I1 l.302D+II1 • o + o +' # + o+ # + U + 1 • 299()+fll o+ o+ 1.2950+01 1.292U+UI 0+ #+ 1. 28QO+1) 1 1.2870+01 # + /I + 1. 293D+1) 1 1 • 32~UtfJ1 o 1.3530tfJl # # # # 1.381LHfJ1 1.4011J+Ol 1.430D+1)1 *,en 0 #0 o I 22lU+{ll 1.267D+Ol 1.3160+111 1.1153U+01 1.1173U+01 1.493U+01 1.5110+01 , , . o o 1.~2/DHll * # 1. 543D+01 I. 5581J+O I 6. 'WUD-07 1.5710+01 1.5840+01 6.450U-07 ~ 16.5000-07 6.5501J-f17 n 6.6000-07 .!!. 6,650U-07 6.7000-07 6.7500-U7 6.8000-07 1.5950+01 1.6U6U+UI 1.616U+01 1.6260+01 I. 634U+0 I 1.6430+111 1.6501J+OI 1.6570+01 :c f URNS VI 3) I,. SOOD-Ol 4.5501J-UI Q wl\vr 1+)----------------- (# 1----------------- . I I (It-or~ o o # # * o o o ,* * o # o o * * # # I + . +. + .+ + + + + + + + + + + + + LEGENO: SHII(,H-OFF \"AVEHmN5 +: V( 3) *: V(5) #: I (V2) TIMf VI,) (+ )----------------- -1.01100+01 (*)----------------- (H )----------------11.500D-07 ..3111 CD- :>", 5.1000-07 O c. _m &l 1. 0020+01 L!. 9~UD-fl' S .0000-07 "CI"CI ., 1.0020+01 '1.600D-1I7 11.6IjOD-07 'I. lOOD-lIl lL 15UO-l17 I). fl50D-!)7 ~III 'J 15f}O-07 .a'~Uj" 5.2000-117 'J.2500-07 5.31100-07 5. 35(1[)-U i c I CALCULATED Ib L "' . II MEASURED /" 1l Ib 0 ,.00 FREQUENCY (MHz) 0 I 00 ~~ f MEASURED CALCULATED 10 ~! o I I ~ • ,. 9 ,. 1 1 100 FREQUENCY (MHz) 1000 VMP4 Figure 8 2-73 .. , FREQUENCY (MHz) 1000 Conclusious [3] Hans J. Sigg, et. al., "D-MOS Transistor for Microwave Applications," IEEE Trans. Electron Devices, Vol. ED-19, January 1972, pp. 45-53. This model offers a designer an excellent start in computer aided design of amplifiers. [4] Marvin Vander Kooi and Larry: R~gle, ,,"MOS Moves into Higher Power ApphcatIons, Electronics, Vol. 49, June 24,1976, pp. 98-103. References [1] James G. Oakes, et. al., "A Power Silicon Microwave MOS Transistor," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-24, June 1976, pp.305-311. [5] Arthur Evans, et. al., "High Power Ratings Extend VMOS FETs Domination," Electronics, Vol. 51, June 22,1978, pp. 105-112. [2] T. M. S. Heng, et. al., "Vertical Channel MetalOxide-Silicon Field Effect Transistor," Final Report, Westinghouse Research and Development Center, ONR Contract N00014-74-C-0012, November 1976. [6] Les Besser, Compact Reference Manual, National CSS, Inc., Version 4.50, January 1977. 2·74 MOSFET Electrical Characteristics _ _ Chapter 3 MOSFET Electrical Characteristics 3.1 Linear Operation Introduction Applications for power MOSFETs can basically be divided into two categories: those in which the devices are used as resistive on-off switches and those in which they are not. This latter group of applications is generically described by the term "linear", but it does not necessarily mean that a MOSFET is being used in a linear part of one of its characteristic curves. Rather, the term linear is used whenever a MOSFET is operated in a continuous or non-continuous fashion where the drain current is a function of gate-to-source voltage or vice-versa. Usually this is achieved by operating a MOSFET either as a voltage-controlled current source or as a voltage-controlled resistor with open or closed loop control. What distinguishes "linear" operation from switching operation is that in a switching circuit the drain current is determined by components external to the MOSFET, whereas in a linear circuit this is not necessarily so. for a Siliconix IRF630 power MOSFET. Two distinct regions of operation can be observed from this family of curves: the ohmic region where on-resistance is approximately constant and the saturation region where drain current is approximately constant. ) I .lv / I / II I T VGS = 40V II 3L V- I l1li 3QV 25V 20V I VDs(V) This section provides the potential user of power MOSFETs in linear applications with useful and technically correct information about MOSFET behavior with varying voltage, current and temperature. Each of the topics discussed in this section provides insight into how a MOSFET functions and the underlying physical phenomena that govern its properties. The Output Characteristics of an IRF630 DMOS Power FET at Tc 25°C Show the Drain Current Increasing Linearly from Zero and then levelling Off at Constant Values Dependent Only on VGS Figure 1 = With zero applied drain-to-source voltage, the drain current is zero independent of the gate-to-source voltage. As VDS is increased in value, with the gate biased positively at some voltage greater than approximately three volts, the drain current increases linearly at first but then levels off to an essentially constant value. The point at which this occurs is where VDS = Vas - VT, and this voltage is termed VDS(sat). VT is the device parameter known as threshold voltage, and the section on transfer characteristics discusses this in more detail. Output Characteristics The output characteristics of a MOSFET provide information about how the drain current (ID) varies with applied drain-to-source voltage (VDS) at various values of gate-to-source voltage (Vas). Figure 1 shows a typical family of output characteristic curves 3-1 The phenomenon that causes the drain current to leveloff or "saturate" with increasing drain-to-source voltage is known as channel pinch-off. Figure 2 shows in cross-section how this occurs in a vertical DMOS FET (like the 1RF630) for the conditions VOS > VT and VDS > VOS-VT· POLYSlUCON GATE tance equal to the width of the depletion region in the body diffusion. It is this depletion region and the one in the n- epitaxial layer that sustain the difference between the applied drain-to-source voltage and the value of VDS(sat). As the applied VDS is increased, the expanding depletion region in the body diffusion causes the pinched-off end of the channel to move towards the source diffusion. Consequently, the effective channel length L' decreases as VDS increases. It is important that this "channel shortening" effect, as it is known, be minimized since the saturated drain current is proportional to IlL'. The saturated drain current in the square-law region can be approximated by the equation [1]: Ya SOURCE METAL .: .::.r:.i. ': CONDUCTING n-TYPE P BODY DIFFUSION p+ CHANNEL, PINCHED OFF AT THE DRAIN END .. ", ... ---------------_ ... / ,, r---------------- ,.." ,/ _.'/ -' ID(sat) n- EPITAXIAL LAYER = p. Cox 2L' n+ SUBSTRATE w (VOS- VT)2 (1) Where p. is the carrier mobility in the conducting channel, Cox is the gate oxide capacitance per unit area, and W is the total effective channel width. Yo The Pinched-Off Channel In an-Channel VDMOS Device Is Shown for the Conditions VDS .. (VGS - VT) and VGS > VT Figure 2 One can see that if VOS is held constant, the drain current will vary only with L', assuming negligible drift in junction temperature (Le., p. and VT stay approximately constant). As VDS is increased, L' decreases and ID increases. This rise in drain current causes the MOSFET to have a finite output conductance in its saturation region. The "horizontal" family of curves shown in Figure 1 thus all have a slight upward slope no matter how slight. It can be shown that the output conductance in the square law region is equal to: . The depth of the conducting n-type channel below the silicon/silicon dioxide interface varies from zero at the pinched-off end, to a non-zero value at the edge of the source diffusion. The diagram shows the channel depth varying linearly with distance from the pinched-off end; however, this does not necessarily occur in practice. The reason for this is that the channel depth is dependent, among other things, on the impurity carrier concentration in the body diffusion below the channel. Since the carrier concentration varies non-linearly across the width of the body diffusion, so does the channel depth. The straight line approximation to the channel depth is shown for convenience only. 00 = iHD aVDS ID L' aL' x aVDS (2) Equation 2 shows that the output conductance is equal to the value of the drain current times the fractional change in effective channel length per volt of VDS. This accounts for the observed rise in output conductance of most devices as the drain current increases. Electrons traveling through the channel "see" no barrier as they approach the depletion region at the pinched-off end [ 1]. Consequently, the saturated drain current is determined by the rate at which the electrons arrive at the edge of the depletion region. In a first order analysis, this rate is only dependent on VOS and is insensitive to VDS. Thus the drain current would seem to be constant for VDS > VOS -VT. L' also varies as a function of the non-linear impurity carrier concentration across the body diffusion. However, almost all of the currently available power MOSFETs show less than 10% channel shortening as VDS is increased from zero to its rated breakdown voltage. This means that few devices will show more than an 11 % variation in saturated drain current over the operating drain to source voltage specification. In reality, however, the saturated drain current does increase somewhat as the applied VDS is increased. Notice that the pinched-off end of the channel is separated from the body-drain pn-junction by a dis- 3·2 The family of output characteristic curves for all power MOSFETs show a rather unexpected behavior as far as junction temperature is concerned. Figure 3 shows the family of curves for the same IRF630 used before, except in this case the junction temperature was raised to 125°C. One can see that in comparison to Figure 1, below gate-to-source voltages of 4.0 volts, the family of curves has moved up, while above VGS = 4.5 volts, the curves have moved down. In Figure 5, there are three distinct regions on the device's transfer curve, and each results from differing conduction phenomena. ,. D. ,. 12 ,. ) ID 4 l- v 77 (v I c. VGS"" 4DV t ~SQUARELAW 3~V If :~ 2 4 3!v 2lv I' 6I 8I I 10 12' vGS SUBTHRESHOLD 20V I This Diagram Shows the Three Distinct Regions on the Saturated Transfer Characteristic Curve Figure 5 VDS(V) = The Output Characteristics of an IRF630 at Tc 100"C Show That In Comparison to Figure 1, the Top Two Traces Have Moved Down While the Lower Traces Have Moved Up Figure 3 In region A to B, a small amount of drain current flows, but VGS is below the MOSFET threshold voltage VT. Since the magnitUde of the current that flows in this subthreshold mode of conduction is negligible compared to a device's maximum current handling capacity, very little work has been done to characterize power MOSFETs in this region. A paper by Swanson indicates that there is an exponential relationship between drain current and gate-to-source voltage for subthreshold conduction [2]. The device thus has a zero temperature coefficient point between VGS = 4.0 volts and 4.5 volts, and this is characteristic of all available power MOSFETs. The physical mechanisms that result in this characteristic behavior will be discussed in detail in the next section. Transfer Characteristics and Threshold Voltage In region B to C on the curve in Figure 5, the drain current is proportional to the square of the difference between VGS and VT. This is characteristic of all MOSFETs, both small signal and power devices, as indicated by equation (1). The actual derivation of equation (1) is outside the scope of this section, but basically it results from applying Gauss's law to find the surface charge density under the gate electrode, and then by performing some simple algebraic and calculus operations to solve for the drain current [3]. The transfer characteristic curve of a power MOSFET shows how the saturated drain current varies with applied gate-to-source voltage for a constant value of drain-to-source voltage. Figure 4 shows the ID versus VGS transfer curve of an IRF630 MOSFET, with VDS set to 10 volts and a case temperature of 25°C. ID(A ) 6 / / Obviously a plot of YID(sat) versus VGS in the square-law region should be linear. The reason one would plot this data is that the true threshold voltage of a device can be obtained from the extrapolated intercept of the straight line part of the curve onto the VGS axis. It should be noted that the value of threshold voltage found by this method can be considerably different from the threshold voltage· range most manufacturers specify on their data sheets. / V J V VGS(Y) The Saturated Transfer Characteristics of an IRF630 MOSFET at Tc 25"C Show a Square-Law Behavior up to 'D 3A, Above Which the Curve Becomes Linear Figure 4 = ! 16 = Thh; is because it is very cumbersome and time consur Ilg to determine the "true" device threshold 3-3 - voltage using the above method in a production environment. Therefore, almost all power MOSFET data sheets specify a pseudo-threshold voltage which is just the gate-to-source voltage range (usually 2 to 4 volts) required to cause a small drain current (frequently 1 rnA) to flow in the device under test. length [ 4]. The voltage at the surface of the channel at the source end is zero while at the pinched-off end it is equal to VDS(sat) or VGS - VT. Thus: ECHAN Figure 6 shows the V ID(sat) versus VGS curve of the IRF630 DMOS device in its square-law region. Also shown is the extrapolated intercept onto the VGS axis, which gives a true device threshold voltage of 2.90 volts. One can see that at this voltage the MOSFET conducts substantial drain current (25.6 rnA). This result indicates that the 1 rnA test current most manufacturers specify VT at is really a current resulting from subthreshold conduction phenomena. In most linear applications of power MOSFETs, however, knowing the true threshold voltage is of little consequence because good circuit designs usually accommodate a range of VT up to several volts. = (VGS- VT) - 0 L' = VGS- VT L' (3) As the E field accelerating the carriers increases with gate-to-source voltage, their velocity also increases since [4] VCARRIER ~ fJ- ECHAN (4) At sufficiently high electric fields (104 V/cm or 1VI fJ-m), the carrier velocity saturates at a value that is characteristic of the material and carrier type. A simplified expression for the drain current under these conditions is given by [5] (AYz) ID(sat) = Cox W Vsat 2 (VGS- VT) (5) 13 12 where Vsat = 5 x 106 cm/second for electrons in silicon [6] . 1.1 10 The electric fields required to cause the channel carrier velocity to saturate are easily achieved in DMOS power FETs. Since the effective channel length is typically in the 1 to 2 fJ-m range, velocity saturation can occur at gate-to-source voltages just a few volts above threshold. This is evident in Figure 4. 09 08 ~07 06 SLOPE"" 05 IA-Cax'z --.r- Another important aspect of the transfer characteristic curve depicted in Figure 4 is the transconductance or slope of the curve. Transconductance is defined as 04 03 0.2 X INTERCEPT = OlD TRUE THRESHOLD VOLTAGE 01 gm I = aVGS VDS = CONSTANT (6) 00~2.~30~3~'~3~2~3~3~34~~35~3~.~3~7~3~'~3.--4~0-+ For the square law and velocity saturated regions, the transconductance is YGS(¥) By Plotting VIO(SAT) versus VGS, the True Threshold Voltage of the MOSFET can be Obtained by Extrapolation of the Curve Onto the VGS Axis Figure 6 gm (square law region) = fJ- CoxW L' (V GS- VT) (7) Referring to Figure 5 again, it can be seen that as soon as the gate-to-source voltage at point C is reached, the transfer curve becomes linear. This linearization is the result of the effect known as "Velocity saturation" occurring. It can be explained as follows: gm (velocity sat. region) = Cox W Vsat 2 (8) One can see that the transconductance increases linearly with VGS in the square law region, but then levels off to a constant value in the velocity saturated region. This is characteristic of all short channel DMOS power FETs. No other semiconductor device shows such a linear relationship between input voltage and output current. The lateral electric field accelerating the mobile charge carriers through the pinched-off channel (see Figure 2) is equal to the difference in the voltage at either end of the channel divided by the effective channel 3-4 In the velocity saturated region, device transconductance is thus a function of two device variables: oxide capacitance per unit area (Cox) and effective channel width (W). For a given value of Cox, it can be seen that the transconductance increases with total W, which itself increases with die size. This is the reason why power MOSFETs having large continuous drain current ratings, and hence a large die size, also have high values of transconductance (in some cases as high as 20 siemens). and, from equation (5), for the velocity saturated region, BID (sat) = Coxz t(V _ V ) aVsat V aVT) aT 2 \ as T aT - sat aT (10) Experimental data has shown that the derivative of the magnitude of MOSFET threshold voltage with respect to temperature is negative, and reasonably constant at about -3 to -6 mVtC [7]. The derivatives of carrier mobility and saturation velocity are also both negative over the operating temperature range of a power MOSFET although Vsat is less sensitive to temperature than IL is. Figure 7 shows a typical data sheet transfer curve for the IRF630 device for TC = 25"C, - 55"C, and + 125"C. It was seen in the previous section that for a specific value of applied Vas, there is zero drift in the drain current with temperature. This is clearly evident in Figure 7 as the point at which all three curves cross through. One can see that below this "zero TC point", as it is known, the temperature coefficient of saturated drain current is positive while above the zero TC point it is negative. 50 if i ~ VDS Il!II: il ZERO Te POINT ......... ~ 3.0 2.0 .5'C--, 1.0 ,.5'C - i o 2.0 ~ Vsat ~ VT aVT """iff + --:::-::c:-=-=--- (12) aVsat ---aT It is interesting to note the similarity between equations (II) and (12). Both of them indicate that the zero TC point lies at some specific positive voltage above device threshold. This positive offset above threshold is in each case equal to the derivative of threshold voltage with respect to temperature (or two times the threshold voltage in the case of equation (11), divided by the fractional change per degree centigrade in either carrier mobility or saturation velocity). However, it is often difficult to determine in which region the zero TC point lies even from a clear diagram such as that shown in Figure 7. _55°C 4.0 (11) Vas (at zero TC point in VSR) = {II ~ 'I ~3.0~ ILiff 'I P 15 V !h I B 10 Vas (at zero TC point in SLR) = 2 aVT /1/ 40 z ~ c By setting equations (9) and (10) equal to zero, the value of Vas at the zero TC point can be determined for both the square law and the velocity saturated regions: 50 6.0 VGS - GATE SOURCE VOLTAGE (VOLTS) = The Transfer Curves of an IRF630 MOSFET at Tc -55'C, 25'C and 125'C Clearly Show the Occurrence of the Zero Temperature Coefficient or "Zero Tc" Point Figure 7 Obviously, the zero TC point of a power MOSFET must occur in either the square law region or the velocity saturated region. Using equations (I) and (5), it can be shown that the zero TC point may occur in either of these two regions. One should note that the temperature coefficient of drain current at low values of ID, is dominated by the threshold voltage drift with temperature. This is obvious from equation (9) since its second term becomes quite large as Vas approaches VT. From equation (I), for the square law region, Conversely, the temperature coefficient of drain current above the zero TC point is dominated by the 3-5 l1li mobility drift with temperature in the square law region and by the carrier saturation velocity drift with temperature in the constant transconductance region. usually lumped into single elements as shown in Figure 9. This model is adequate for low-frequency «5 MHz) small signal analysis but breaks down at higher frequencies. A more elaborate model is required at higher frequencies and must include parasitic package and bond wire inductances (see 2.13.2). Interelectrode Capacitance All types of DMOS power PETs, whether lateral, vertical or V-groove, have capacitances between the gate, source and drain terminals that are dependent upon the device geometry and die size. The origin of these capacitances in a closed-cell vertical DMOS device, like the IRF630, is shown in Figure 8. RG Cgd G~r.-m-~-.~--~--~--c.-.--O This Simplified Small-Signal Model of a DMOS Power FET in its Saturation Region is Adequate for Low Frequency « 5 MHz Analysis) Figure 9 n+ Manufacturers data sheets do not generally tabulate Cgs , Cgd and Cds directly; rather they specify the input, output and reverse transfer capacitances of the MOSPET connected in a common-source configuration. This is in accordance with standards set out by the Joint Electron Devices Engineering Council (JEDEC) and the Electronic Industries Association .(EIA). SUBSTRATE The three capacitances one finds listed on a data sheet, Ciss, Coss and Crss , are defined as follows This Cross Sectional View of a VDMOS Power FET Shows the Origin of the Interelectrode Capacitances Figure 8 [8]: One can see that the polysilicon gate structure has both capacitance to the source metalization overlaying it, as well as capacitance to the silicon surface below. Cgsm is the gate-to-source metal capacitance; Cgn+ is the gate to n+ source-diffusion capacitance; Cgp is the gate to p- type body-diffusion capacitance; and Cgd is the gate to drain-drift region capacitance. Commonly, the sum of Cgsm , Cgn+ and Cgp is referred to as C gs , the total gate-to-source capacitance. Ciss Coss Crss Cgs + Cgd Cds + Cgd Cgd (13) (14) (15) Usually the specifications for Ciss, Cos s and Crss will include the test conditions under which they are measured. These test conditions typically are as follows: f = 1 MHz (ii) VGS = 0 volts (iii) VDS = 25 volts (i) The parasitic npn bipolar transistor inherent to the structure of an n-channel DMOS PET has a reverse biased pn-junction between its base and collector. The depletion capacitance of this junction appears between the drain and source terminals of the MOSPET and is termed Cds. Additionally, many manufacturers include on their data sheets curves showing how the capacitance parameters vary with applied drain to source voltage. Some plot the variation of Ciss, Coss and Crss against VDS, but a more useful set of curves would be Cgs , Cds and Cgd plotted against VDS. Siliconix now supplies this latter set of curves on their data sheets so that the small-signal AC model capacitance Although the capacitances in a power MOSPET are distributed over the whole surface area of the die, for the purpose of simplified circuit analysis they are 3-6 where q is the elementary electronic charge (1.9 X 10- 19C), Ks is the dielectric constant of silicon (11. 7); EO is the permittivity of free space (8.86 X 10- 14F/ cm); CB is the epitaxial layer background concentration (atoms/cm3); VR is the applied reverse voltage to the junction (= VDS); and «P B is the built-in diode potential (= O. 7V). parameters can be written down directly. An example of these capacitance versus VOS curves for the Siliconix IRF630 MOSFET is shown in Figure 10. As can be seen, there is only a very slight variation in Cgs with applied VOS, but a much more substantial variation in Cgd and Cds. 10,000 For applied values of VOS » «PB, equation (16) shows that the value of Cds should vary approximately in proportion to 11 V VDS. This is in fact the case, although it may not be entirely obvious from Figure 10 which has been plotted on log-log graph paper. 1000 Cga r-100 --r- :--- The dependence of Cgd on VOS is very similar to that of Cds as seen in Figure 10, even though it is not a junction-depletion capacitance. The reason for this is the lower "plate" of C,gd formed by the region of mobile charge in the epItaxial layer below the polysilicon gate (reference Figure 8). This region of mobile charge effectively becomes smaller as the depletion regions between adjacent cells (in a closed cell structure) approach each other with increasing VOS. It should be fairly obvious that the relationship between Cds and VOS is not the same as that of Cgd and VOS. In the former, VDS modulates the effective capacitor thickness while in the latter it modulates the effective capacitor plate area. Cda C,d VGS =0 ,. F=1Mj 1 10 100 Vas - DRAIN SOURCE VOLTAGE (VOLTS) This Log-Log Plot of Device Capacitance versus Drain to Source Voltage Shows Very Little Variation In C~s but a Much More Substantial Variation in Cds and 1;gd Figure 10 One would probably expect Cgs not to vary at all with applied VOS, and for all practical purposes, this assumption can be made. Of the three capacitances that constitute Cgs , only Cgp shows a dependence on VDS. This is due to die widening of the depletion region in the p-type body diffusion as VOS increases. The further the body depletion-region moves towards the n+ source diffusion, the smaller Cgp becomes. This is because only the undepleted regIon of mobile charge at the surface of body diffusion, below the polysilicon gate, can form the lower "plate" of Cgp . Since most modem DMOS power FETs show typIcally less than 10% depletion spreading across the width of the body region as VOS is varied from zero to its rated breakdown value, the change in Cgp and hence Cgs is small. To determine a relation between Cgd and VDS, we must start by carefully examining FIgure 8. It can be shown that for a given value of depletion region width in the epitaxial layer, Wd(epi), the effective value of Cgd per unit area becomes reduced from the value of Cox (the gate-oxide capacitance per unit area) to a lower value given by: 2Wdx(ePi») Cgd (per unit area) = Cox ( 1 - --.....::..- where x is the average distance between the metallurgical junctions of adjacent cells. Again from the analysis of the one-sided-step-junction model, it can be shown that [12]: ~ The substantial decrease in the values of Cds and Cgd as VDS is increased is also due to depletion spreading, but in these two cases, it is due to spreading in the epitaxial layer rather than the body diffusion. Wd (epi) = /2KsE o(VR +«PB) qCB V- (18) Although the curve of Cgd versus VDS may look similar to that of Cds versus VOS, one can see that Cgd actually varies in proportion to (1- K V VDS) and not (11 VVOS). . Because Cds is a junction depletion-capacitance, an approximate relation for its value per unit area can be derived from the analysis of the one-sided-stepjunction (OSSJ) model [9]: Cds (per unit area) (17) As far as thermal effects are concerned, the capacitance parameters of a power MOSFET are one of the few that show negligible variation with temperature. In fact, it is a direct consequence of this invariance that the device switching times, which are capacitance dependent, are essentially independent of temperature. (16) 3-7 l1li [5] S.C. Sun and J.D. Plummer, "Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces," IEEE Transactions on Electron Devices, ED-27 No.8. References [1] Richard S. Muller and Theodore I. Kamins, Device Electronicsfor Integrated Circuits, John Wiley & Sons, 1981. [6] F.F. Fang and A.B. Fowler, "Hot Electron Effects and Saturation Velocities in Silicon Inversion Layers," Journal of Applied Physics, No. 41, March 15, 1970. [2] R.M. Swanson and J.D. Meindle, "Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits," IEEE J. Solid State Circuits, Vol. SC7, April 1972. [7] Paul Richman, MOS Field-Effect Transistors and Integrated Circuits, John Wiley & Sons, 1973. [3] David M. Navon, Electronic Materials and Devices, Houghton Mifflin Company, 1975. [8] EIA or JEDEC Specifications for MOSFET Device Parameter Measurement. [4] R.A. Blanchard, Optimization of Discrete High Power MOS Transistors, PhD Thesis Dissertation, Department of Electrical Engineering at Stanford University, December 1981. [9] A.S. Grove, Physics and Technology of Semiconductor Devices, John Wiley and Sons, 1967. 3·8 3.2 Switching Characteristics Introduction 2' Power MOSFETs, well-known as majority-carrier devices, are also well-known for their extraordinary switching speeds-far faster than the best power bipolar transistors currently available. When switching speeds are compared, the fall time rather than the rise time is of primary concern. It is here that the MOSFET excels. " When bipolar transistors are used in high-speed applications, a variety of schemes are often used to hasten the fall time, but none of them can equal what the power MOSFET can do without help of any kind! Yet the power MOSFET, like the bipolar transistor, is a charge-coupled device. Although MOSFETs differ in design, construction, and intended application, to achieve fast switching times, an understanding of their charge-transfer characteristics is crucial. Consequently, some of the schemes popular with bipolar transistors will also be useful for power MOSFETs. I I "'"'- 1Q=10A- - SA- - "- - 6A 4A 3A ,, 2A 1D '2 Figure 1 Since early 1981, an increasing number of power MOSFET vendors have added charge-transfer characteristic curves to their data sheets, but they have failed to offer supporting information, leaving the prospective user to question the usefulness of these curves. Improved switching efficiency, which is what the designer looks for in higher-speed switching, is a measure of power loss. In the majority of switching applications, as in switch mode power supplies, efficiency focuses upon switching losses. Aside from saturation losses which, depending upon bias, (see Figure 1) are fixed. Switching losses are a function of switching speed. Consequently, at low switching frequencies it is entirely possible and, indeed, probable that switching speed no longer becomes a primary loss mechanism. Therefore, the important switching characteristics are those involving high-speed switching which is best achieved by using power MOSFETs. Charge-Transfer Characteristics All power MOSFETs, without the encumbrances of Zener gate protection, whether metal gate or polysilicon, display a DC input resistance of many megohms. When used as a switch, the power required to maintain a quiescent condition (either ON or OFF) is zero whereas with a power bipolar transistor, it is not. In parallel with this high-input resistance, there is an equivalent input capacity consisting of gate-to-source capacitance, Cgs , and gate-to-drain capacitance, Cgd. Switching losses (efficiency) are more fully treated in Section 4.1. 3·9 III For an enhancement-mode MOSFET, the gate voltage must exceed the threshold to begin switching action. For an n-channel MOSFET, the direction is positive, and for a p-channel, it is negative. Since the input impedance of the power MOSFET is a nearly pure capacitance, the drive must first charge this capacitor; likewise, to turn OFF the power FET, it must be discharged. For this reason, the power MOSFET is considered to be a charge-coupled transistor. Consequently, for very high-speed switching, a driver is necessary that can both source and sink sufficient current to charge/discharge this input capacitance in a reasonably short time. 3, the gate voltage rises to its maximum drive potential as the drain voltage slowly settles to VSAT. Following the gate-charge cycle, first is the initial turn-ON delay td(on) [Region 1] which continues until conduction begins (0.9VDS). During this period, the gate potential is charging the equivalent input capacitance which, in the pre-threshold region, is merely Cgs-thus, the fairly constant slope. This pre-threshola capacitance can be calculated from the equation: C If the input capacitance is known, the energy necessary to charge the gate can be determined: 1 W = 2C. d 2 III Vgs Unfortunately, input capacitance is not well-defined because the Miller effect renders Equation 1 nearly useless. Rather than struggling with capacitance, a more viable method is to use the charge-transfer characteristics found on most power MOSFET data sheets. Figure 2 shows the typical charge-transfer characteristics for a Siliconix VN4000A, 400 V, 1.0n MOSPOWER PET. 400 1 VD. I If', II II' !J I VII I!I , '\ 1\ \ 'DD V '00 v " II VI 1 IY '-II 5 12 10 400 i, "!t 15 I II i. . • .~ " l'!l 4 ::> ~300 ~ n I ~ I ~ :;= ~- f-+ f4-~ f--I fiI ~ II! or I VGG ~ ~ ~ 200 or ~ ~ 0 I(' z c ri, :g'00 I VD • r-j" f-- V., 25 Q CHARGE (nC) TUrn-On Charge Transfer Characteristics Figure 2 Although Figure 2 may be similar to that supplied in most power MOSFET data sheets, it offers more information than is necessary for this discussion. Focusing attention on a less cluttered Figure 3, where just the 200 V data is reproduced, there are three distinct regions of importance. In Region 1, the gate voltage, Vgs, has risen to a level where there is drain current conduction. In Region 2, turn-ON is complete when the drain voltage has switched 90%. In Region I ....... Vg ' Q2~3 > 20 (4) i!i ~ 10 (3) N i§ \ I \ III II + Cgd(l - AV) CI. l l_- Qg2 - Qg1 Vg2 - Vgl I' 300 v I'- 2 A greatly simplified approach to determine the equivalent input (or Miller) capacitance uses data available from Figure 3. J.7'f.... , VD. Cin = Cgs I IN I (II VDS- OY ( ) The most obvious event that distinguishes Region 2 from Region 1 is the abrupt increase in input capacitance identified by the flattening of the gate-chargetransfer curve. As the power MOSFET turns ON, the Miller effect becomes the dominant input capacity. Miller effect capacity can be calculated using the equation: (1) Watt-seconds _ Q g1 ~-V~ I I 0, II' .,I... 5 15 10 I 20 25 Q(nC) o TUrn-On Charge Trensfer Characteristics Figure 3 Region 3 reveals two important bits of information, and it poses two questions: Why does the flat chargetransfer, so obvious in either Figure 2 or 3, remain as it does; and why does the drain voltage decay abruptly stop and slowly settle to VSAT? Equation (3) appears to contain explainable elements, viz. Cgs , th~ gate-to- 3-10 source capacity; Cgd, the gate-to-drain capacity; and A V, the voltage gam which equals (dVDS/dVgs). voltage, VDS, has decayed to VSAT. Then the gatecharge resumes its rise to the level of impressed gatedrive voltage, VGG. The two questions posed are interrelated. By magnifying a portion of Figure 3, a tangential approximately shows that the knee is very close to the gate-to-source voltage. Of particular significance is the resulting potential across Cgd during switching, best seen in Figure 6 where a spectacular rise in capacitance occurs. The Effects of Gate Drive on Feedback Capacitance The effects of drain-to-source voltage, VDS, upon the interelectrode capacitances are not determined easily from the Capacitance-versus-Voltage plot found on most power MOSFET data sheets (Figure 4) since Ciss, Coss , and C rss appear to become asymptotic beyond a few dozen volts. Since C gs and Cgd are depletion-dependent, they are voltage dependent. A far better understanding of this dependency is seen when these capacitances are plotted as shown in FigureS. 104 I"'-- r-.... CAPACITANCES VGS~O- 1400 1\ 1200 ~ 1000 rl ~ 800 l! 600 f 1\ \ " Cia. I U 101 4IMI \ 200 Figure 6 Co•• Cr•• \.. o -6-4-202 VDG DRAIN-TO-GATE VOLTAGE (VOLTS) o 25 50 75 YDS - DRAIN-SOURCE VOLTAGE (VOLTS) The answers to the questions become obvious. As the drain voltage decays during the switching cycle, the potential across Cgd also decays until VDS reaches V gs. Since Cgd is depletion dependent, its capacitance rises dramatically as the voltage between drain and gate diminishes and changes polarity when VDS drops below V gs-as it surely does during the switching cycle. As Cgd rises, the Miller capacitance in- _ _ creases even more rapidly and, despite the drop in ~ voltage gain (dVDS/dVgs), the increase in Miller capacity keeps the gate-charge characteristics nearly flat until VSAT is reached. 100 Figure 4 1000 ........ "". I" .......... i'- 100 'l"- Switching-Time Calculations Turn-ON Delay and Turn-ON (Rise) Time I"~ elM = ega + Cgd Ca•• = Cds rCr.. = Cgd 10 01 + ega "" Cgd "".+C•• 1 11111111 On every power MOSFET data sheet, switching times can be found. The data presented may be measured experimentally rather than by analysis. 1 10 100 The switching times can be computed from the chargetransfer characteristics using the following equations: VDS(YOLTS) Figure 5 Aside from turn-ON delay, td(on), which is directly affected by the pre-threshold mput capacity of Region 1 [see Equation (2)], trise and tfall are heavily influenced by the Miller effect, which is in turn affected by the gate-to-drain capacity, Cgd. td(on) tr = A more careful study of Region 3 reveals that the gate-charge curve is essentially flat until the drain = Qgl VGG Rgen In --'::""::'--VgI VGG - VgI Qg2 - QgI R I V GG - V gi gen n Vg2 - VgI VGG - Vg2 (5) (6) where Rgen is the source resistance in ohms, and the ratio Qg/V g is the equivalent input capacitance. 3-11 cation since the charge time is dependent upon both the load resistance and effective drain-to-source capacitance. The latter is dependent upon the MOSFET's Coss and the particular mounting configuration. A 0.003-inch fiber insulator between a T03 package and a grounded heatsink, for example, offers 200 pF of additional drain-to-source capacity. Figure 7 identifies a typical gate discharge transfer characteristic for a Siliconix VN4000A MOSPOWER FET that has a resistive load of'100 n with the MOSFET mounted to a grounded heatsink using a 3 mil fiber washer. A careful comparison of this figure to Figure 2 shows the VDS rise time of Figure 2 is obviously faster than the corresponding fall time of Figure 7. This confirms that rise time is generally swifter than fall time-even for a power MOSFET. This, in concert with the source resistance, becomes the familiar RxC time constant. Aside from Rgen, all the data necessary to calculate the turn ON delay, td(on), and rise time, tr, can be taken from the charge-transfer curves of Figure 2 or 3. Reasonable care is needed since small errors in the data may lead to enormous errors in the calculations. Table 1 provides a comparison between the measured data, taken from an average of 10 devices and calculated data using Equations (5) and (6). Table 1 ns Calc. Meas. Id(on) 29.9 32 Ir 52.8 52 VOO=200V R gen =50n Calc. Meas. 61.7 105 60 105 R c =100n 400 'furn-OFF Delay and 'furn-OFF (or Fall) Times Turn-OFF delay, td(off), and fall time, tf, can be readily calculated from the data contained in the charge-transfer characteristics of Figure 2 or 3 in a similar manner using the equations: Qg3 - Qg2 VGG td( off) = Rgen In - Vg3 - Vg2 Vg2 tf = Qg2 - Qgl ~ Rgen 1n Vg2 - Vgl Vgl < VGG 300 / ! II \. c \. 200 I (7) so.. ~ v.' I ,/ v•• -7 - '0% A problem arises, however, when tf data is taken from these charge-transfer curves. A short review of what happens during a typical switching cycle will illuminate the problem and reveal the cure. 5 15 ::; ~ .!!l Q \ \ I' ;;7 10 1i 100 tj I I L ~ ~ Q~ J (8) - g, \ 20 25 30 Q CHARGE Inc) 1I.Irn-Off Charge Decay Characteristics Figure 7 Every power MOSFET is bracketed by parasitic capacitances: Cgs , Cgd, and one not previously mentioned, Cds-the drain-to-source capacity. Before the MOSFET enters into the turn-ON cycle, Cds is fully charged to the rail potential. During the switching cycle, Cds begins its discharge through the ON resistance of the power MOSFET. When the time comes for the MOSFET to turn OFF, the conditions may differ in that rather than exhibiting a time constant consisting of rDS(on) and Cds (MOSFET ON resistance times the drain-to-source capacity), the time constant now becomes Rload and Cds (load resistance times the drain-to-source capacity)! If the load resistance/reactance differs from the ON resistance of the MOSFET, the calculation of tf will be in error if the gate charge transfer characteristics depicted in Figure 2 are used. The solution is to define a gate-discharge decay characteristic curve. Correlating 'furn-OFF (Fall) Time To illustrate the problem encountered when chargetransfer characteristics are used rather than discharge-transfer characteristics, a comparison is offered in Table 2. Table 2 os Meas. 48 If VoS=200V Calc. Fig. 2 32 Calc. Fig. 7 46 R gen =50n Conclusions What has been offered in this section suggests that switching times can be accurately determined for a variety of applications and test conditions provided charge-transfer data is offered on the MOSFET data sheet. Furthermore, one is able to recognize the importance of low feedback or gate-to-drain capacitance which suggests that higher speed rise and fall times can be achieved with low Cgd FETs. Gate-Discharge Decay Characteristics The gate-discharge characteristics are complicated because of the dependency upon the particular appli3-12 Thermal Design and SOA _ _ -~ I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Chapter 4 Thermal Design and SOA 4.1 Safe Operating Area and Thermal Design for MOSPOWER Transistors (ANS3-10) Introduction The MOSFET Thermal Model MOSPOWER transistors have evolved into true power devices. Like any power semiconductor, these devices have thermal and electrical limitations which must be observed if acceptable performance and service life are to be achieved. The Steady State Thermal Model Figure 1 gives a simplified thermal system diagram for a MOSFET and the electrical circuit analog for the steady state. By inspecting Figure IB, we can write an expression for Tr In general, thermal and electrical characteristics are mutually interrelated so actual limits depend on the particular device application. Tj = Ta + (Rojc + Rocs+ Rosa) PT To help the user, most data sheets contain information on maximum junction temperature (Tjmax), safe operating area (SOA), maximum voltage and current ratings, as well as steady state and transient thermal impedances. Despite the wealth of information presented in a good data sheet, it is not possible to provide graphs and reference tables to cover all possible applications. The designer is still faced with the problem of accurately calculating several quantities such as junction temperature (Tj), total power dissipation (PT) and correct SOA curve for the application. (1) For convenience we usually let: Roja = ROjc + Rocs + ROsa (2) so that: (3) This seems to be a very simple expression, but there is a hidden problem: in a MOSFET, PT is an exponential function of Tj which leads to some difficulty in calculating Tj and PT. Before solving that problem, pause to examine the elements of equation (1) and consider to what degree the designer can control these elements: The information on how to perform these calculations is scattered. This application note intends to solve the problem by collecting the necessary information in one place and arranging it in a logical order so that the thermal and SOA design for power MOSFETs are no longer a mystery but a relatively simple and direct procedure. 1. Ta is usually an externally imposed requirement stated in terms of maximum temperature of the heat exhaust medium. We begin by discussing thermal models for a MOSFET. With this information, we then solve for Tj and PT and predict the system thermal stability. Finally, we demonstrate the procedure for generating an SOA curve for a particular application. 2. Tjmax may be imposed externally such as in a military application where Tjmax may be limited to +lOSoC to +12SoC. In some applications, the overall MTBF de- 4-1 III Tj = JunctIon Temperature ROjc = Thermal ImpedanceJunction to Case Thermal Junton / SIlicon DIe Tc = Case Temperature ~reas _...c::====t~~_~lnISUlator e Ir- \~ T_-T Case J a ± ROcs = Thermal ImpedanceCase to Sink Ts = Heat Sink Temperature Heatslnk ROsa = Thermal Impedance, Sonk to Ambient ! AmbIent T a = AmbIent Temperature (B) Electrical Analog (A) Physical System MOSFET Thermal Model for the Steady State Figure 1 sired may dictate Tjmax- There is, of course, the maximum rating from the manufacturer, to be exceeded only if drastic reductions in operating life are acceptable_ In any case, the user makes the descisiion on the acceptable limits_ because if the heat input to the heatsink is dispersed rather than concentrated (at one point), the effective thermal impedance will be lower for a given heatsink_ The Transient Thermal Model 3_ For a given die size, the value of ROjc will depend on the package chosen_ The same device, for example, will have a smaller thermal resistance in a TO-3 package than in a TO-39 package_ Often, however, there is little flexibility in package choice, particularly for larger devices_ Another way to lower ROjc is to parallel devices_ For example, if the choice is between a single IRF440 or two IRF430's in parallel, both possibilities will have the same RDS(on), but the effective ROjc + ROcs for the two devices will be 1/2 that for the single_ Naturally there are disadvantages to paralleling multiple devices, so it is up to the designer to make the tradeoff. In many applications, the power dissipated in the MOSFET is pulsed rather than DC- For these applications, the thermal model must be modified to account for thermal capacity introduced by the die, the case, the case insulator, and the heat sink. A thermal model for pulsed operation is shown in Figure 2A where the mass of each component is represented by a capacitor. As a practical matter, some of the capacitors are much larger than others because of significant mass differences in various parts of the system_ For example, we can break down Ro jc(t) into its components as shown in Figure 2B_ The thermal time constants of elements in the packaged device are given in Table 1. 4_ Rocs is determined by package choice and by the device mounting method on the heatsink_ If the device is mounted directly on a smooth, flat surface, without an insulator, with a small amount of thermal grease and the proper screw torque, then Rocs will be low_ If on the other hand, the mounting uses an ungreased mica washer loosely clamped to a rough surface, the Roes will be large_ Reference 1 of the bibliography has a thorough discussion on semiconductor mounting_ Table 1 Element Thermal Time Constants Element die 5_ Rosa - The heat sink design is completely under the designer's control within practical and economic Iimits_ Multiple parallel devices 'may be helpful in reducing ROsa die attach case 4-2 Thermal Time Constant 50 - 500J-lsec 1 - 5 msec 1 - 5 seconds N T.-T I a ± Cl } C2 } ROje Die ROje(t) Rees ROsa C3 T.-T I ROes(t) a ± Ole Attach 1".'" RO,e(t) Case (8) Electrical Analog for the Junction to Case Impedance (A) Electrical Analog for the Complete System Transient Thermal Impedance Model Figure 2 The dominant time constant depends on the power pulse length. For example, if the pulse width is 100 /lsec, then thermal response is determined primarily by the die characteristics. The difference in time constants can be used to detect imperfections in die mounting. various widths but with the same peak value. The shorter the pulse, the smaller the rise in Tj. The variation in Rojc( t) with tp is shown graphically in Figure 4 where ROjc(t) is normalized so that: In most systems the heat sink time constant is long compared to the device time constants and does not enter into the calculation except for very long pulses (> 10 seconds). r (t) (4) ROJc For very short pulses, ret) is quite small, but as tp is increased r(t) approaches I, which is the same as saying that for long pulses the transient impedance approaches the steady state impedance. When a pulse of power is applied to this network, the peak value for Tj will depend on peak power and on pulse width (tp). Figure 3 shows the response of Tj to pulses of € ROjc (t) =-.:.....-- Steady State e E .,Co ::l of E TIl ~ 0.1 r-------::7'"t'''----+---+------j----..,j c: gu c: -.::l tp - millISeconds TIME (t) Thermal Response to a Single Power Pulse Figure 3 Single Pulse Normalized Transient Thermal Impedance Figure 4 4-3 III Equation (6) can readily be solved using the HP-41C program given in appendix A.2. From this curve we can readily calculate Tj if we know PT, Rojc and t c , using the expression: (5) Tj = Tc + PTr(t) Rojc Up to this point we have been discussmg thermal response to a single pulse; however, most applications have repetitive pulses. Variations in Tj will have the form shown in Figure 5. In this case Tjmax may be much higher (for the same t p) than it would have been in the single pulse case due to the temperature rise resulting from the average power dissipation. The value of ret) for a repetitive pulse can be approximated from the single pulse curve using the following expression: r (t) =D + (I-D) II + rz - TJmax "~ r~~\-'1---V=:4 ~~t TIME Thermal Response to Repetitive Power Pulses Figure 5 (6) r3 t Figure 6 is a graph of equation (6) plotted on the single pulse graph for several values of D. This graph, usually included in the data sheet, allows the user to determine ret) by inspection. For duty cycles not plotted, the value for ret) can be estimated by interpolating between the given curves. (7) D=..L T tp = Pulse width of the power pulse T = Pulse repetition interval = Composite T tp where tpw t/1\ ___ ~ ___ ~_ J pulse widths used to calculate II, r2, MOSFET Power Losses and r3 There are several possible power loss sources in a MOSFET: II = ret) for tpw = T + t p , D = 0 rz =ret) for tpw =t p , D =0 r3 =ret) for tpw =T, D =0 1.0 :0 taken from the single pulse curve, Figure 4. 1. Ps the switching transition loss. 2. PG the portion of the drive power dissipated in the gate structure. = 1, --- 0,75, rid 0.1 ~ D =0:50' ,.,..,- I?= ). 25 ,.,.. ~ : rile ",-" + """ P~ t ~ I.-~tp I -T-- tp 1. DUTY FACTOR, D = - ' I·PIlr.KAf.: T 2. PER UNIT BASE = Ro jc = 1.0°C/W 0,01 0.1 I 1.0 3. TJM-TC=PDMr(t) ROjc 111111 10 100 tp-TIME(mS) Normalized Transient Thermal Impedance for Single Uniform Repetitive Pulses Figure 6 4-4 1000 10,000 3. PL the power loss due to drain·source leakage current (lOSS) when the device is off. 4. Po the reverse diode conduction and trr losses. 5. Pc Table 2 gives a comparison of the switching losses for resistive, clamped inductive and unclamped inductive switching using representative values. ,Table 2 Switching Loss Comparison the conduction loss while the device is on. Switching Transition Losses Figure # Compared to a bipolar junction transistor (BJT), the switchmg loss in a MOSFET can be much smaller, but there are still some losses which must normally be ac· counted for. The switching losses depend on both the switch transition times and the type of load switched. Examples of several typical loads, along with Idealized switching waveforms and expressions for PS, are given in Figures 7 through 10. Ps =fs [ ts1 1 o ts2 Vos 10 dt + tS2 1 VOS 10 dt](8) 0 (AI (81 ts1 fs ts2 =vool I Voo 10 ="""RL I 7 100V lA lA lOOns lOOns 100kH O.33W 8 100V lA lA lOOns lOOns 100kH lW 9 150V 0 2A lOOns 400ns 100kH 6W I ~'" ~------1V:L I I I I I Waveform I I I 102 ""\ 101 '" 10 "'~~o' _--_--1-/..../ . \ - - - -/."'\-L--_-_- ~oos=vc I I SWllchlng I I 51 I I 52 SWltchmg I I (el ~ I I I Power DISSipation (01 Ps = Ps IAI "'~ 10 Ib2 The capacitive load (Figure 10) has a peculiarity in the turn-off waveform for VOS. If the turn-off time for the MOSFET channel (ts2) is very short and 100 is small (or C is large), then the rise time of VOS is controlled by the. load, i.e. the rate of charge of C, not by t s2. On the other For the idealized waveforms shown in the figures, the integration is quite easy and can be approximated by calculating the area of a triangle or trapezoid. VOS 101 Notice how much higher the losses are for inductive switching, particularly the undamped case. Note also that in Figure 9, ts2 is not the tum-off switching time of the FET, rather it is thetime the FET remains in avalanche breakdown. Breakdown will persist until the energy in L is dissipated and the current falls to zero. Their power losses can be calculated from the general expression: ts 1 VOS VOS 10 (151 + 1521 fs 6 • fs = SWllchlng Frequency Resistive Load Switching Waveforms Figure 7 Clamped Inductive Load Switching Waveforms Figure 8 4-5 :~~::~ (AI 10 (A) Test Circuit + <>---1 oJL Test Circuit VOS = Vc (B) (61 VOS= VOO SWitching Waveform '" J\"--_-J{\~___ SWltchmg Waveform (CI Power DISSipation Power DISSipation (01 Ps - 102 6VOSS 2 '52 Is _ 101. 0 Unclamped Inductive Load Switching Waveforms Rgure 9 Capacitive Load Switching Waveforms Rgure 10 hand, if 100 is large (or C is small), the charge time of C is short, and the rise time of VOS is agian equal to ts2- forms, a snubber can also remove much of the switching loss from the device. This allows it to run cooler, in tum helping reduce conduction losses (PC). In some cases the use of a snubber can significantly improve overall efficiency; in fact, use of a snubber should be considered even if it is not needed for device protection. A practical circuit example where such switching occurs is shown in Figure II where both the internal capacitance (COSS) and external parasitic capacitance (C p) are included. Given normal component values, at high loads 100 will be large, and the rise time of VOS at turn-off will reflect the switching speed of the gate drive. At light loads, however, 100 is small, and the rise time ofVOS may slow down appreciably even though the gate drive has not changed. This may deceive the user into believing that the MOSFET is switching off more slowly than it is. Gate Drive Losses A MOSFET gate represents a capacitive load with some series resistance to the driver as shown in the equivalent circuit in Figure 12. The total gate drive power (PGT) is (9) If the approximations are not accurate enough, then the usual procedure is to photograph the turn-on and turn-off waveforms, make straight line approximations, and then use Equation (8) to calculate the losses. Greater accuracy is possible using a calculator with an integration subroutine, but this is seldom required. Where Qg is the peak charge in the gate capacitance, Vgs is the peak gate voltage and fs is the switching frequency. The portion of PGT which is actually dissipated internal to the MOSFET is: PG = Vgs Qg fs( The switching losses within a MOSFET can be reduced by using a snubber across the device from drain to source. The usual purpose of a snubber is to reduce voltage and/or curren t stress on the device. By altering the switching wave- R'i) Rs+ G Typical values for RG range from 0.05 to device chosen. 4-6 (10) 4n depending on (AI 100 RS L-__ ~ ______ ~~~~~ __-,+ Va Ciss Driver Test Circuit Gate Drive Equivalent Circuit Figure 12 Vos Some additional loss will occur during the reverse turn-off interval (trd. This loss is usually small, but as the switching frequency is raised (> 100kHz), it can become significant. A reasonably accurate loss value can be obtained by photographing the voltage and current waveforms of the diode during the reverse turn-off interval and then applying equation (8) to a piecewise linear approximation of the waveforms. 10 SWitching Waveforms Combined Capacitive and Inductive Load Switching Waveforms Figure 11 While the trr losses are usually small and may frequently be ignored, there is a condition which can greatly increase this loss. The internal diode is actually the base-collector junction of a parasitic BJT. Under some conditions the BJT can be turned on by a rapid dV/dt waveform. When this happens, the current waveform during trr has a much larger amplitude and lasts longer. This greatly increases the power dissipation and can destroy the device. The best way to detect this condition is by careful observation of the trr current waveform. An applications note treating this problem in detail will be available from Siliconix. Drain to Source Leakage Current Losses When a MOSFET is turned off and VDS is still present, a small leakage current (I DSS) flows from drain to source. This will cause some power dissipation (PL) during the off interval: (11) where D is the conduction duty cycle of the switch. Conduction Losses Normally PL will be small since lDSS is typically only a few microamperes and may be ignored. If, however, Tj is high or if Vgs, during the off period, is not well below the threshold voltage of the device, then PL may become significant. IDSS is not easy to measure in a switching circuit because ID alternates between amperes and microamperes. If there is some question on the value for PL, a separate breadboard should be set up which reproduces VDS, Vgs and Tj during the off interval on a steady state basis. From this IDSS can be measured duectly. As a general rule, lDSS will double for an 11°C rise in Tj. In most applications, the major loss in the MOSFET is due to the non-zero on resistance, RDS(on), through which the drain to source current (10) must flow. When conducting as a switch, the device is simply a resistor, and the conduction losses (PC) are: 2 Pe={ID(rms)}RDS(on) (13) Note the root-mean-square (rms) value for lD is specified. This is quite different from a BJT in which the average value of the collector current is normally used. Internal Diode Losses The expression for Pc looks simple, but that is deceiving because RDS(on) is a function of several variables: the junction temperature (Tj) , the gate-to-source voltage (Vgs), the drain current (ID), and manufacturing variations. The MOSFET structure contains an internal diode oriented as shown in Figure 13A. In most respects this is a normal pn junction diode, and in some applications it is allowed to conduct during a portion of the operating sequence, eliminating the need for an additional external diode. The diode losses during conduction are proportional to the product of IRD and VF, which have the usual diode relationship (Figure 13B). The loss in the diode (PD) can be approximated rather well by: PD = lRD(avg) VF(avg) MOSFET The dependence of RDS(on) on Tj is shown in Figure 14. This curve has been normalized so that RDS(on) = 1 when Tj = 25°C. Notice there are two curves: one for a low voltage device and one for a high voltage device. Both curves have ~ positive temperature coefficient, i.e. as Tj increases, RDS Increases. This is characteristic of all power MOSFETs. (12) 4-7 _ o 2.4 / 2.2 500V deVice 2.0 IAI G V V ./ 1.6 z en 0 ex: 1.4 1.2 1.0 0.8 0.6 J ~ 6 Co E IBI V 1.8 0----1. 0.4 / V - " t-- I"01 K=I./lb Variation In Irms as a Function of the Trapezoidal Current Ration (K) Figure 21 The Converter Circuits Used for the Switch Current Calculations Figure 22 on ROja and RDS. As a rough guide, L should be at least twice the critical inductance (Lc) required to maintain continuous inductor current at full load over the range of Vs. Making L much larger than 3XLc usually isn't worthwhile since most of the benefits have already been achieved. We can calculate the rms values for the switch current (i I) in each circuit, first by assuming L is sufficiently large so that the switch current waveforms are rectangles, and second by assuming L is smaller so that the waveforms are triangles, but with the same value of D. The results of this calculation are listed in Table 3. Operation in discontinuous inductor current mode raises the power losses rapidly to levels even higl1er than indicated in Table 3. In general, operation at full power in the discontinuous mode is unacceptable from a power loss point of VIew and is usually avoided at powers above IOOW for off-line operation and 25 to SOW for lower voltages. In all cases il(rms) is lower when L is made larger or when circuit B is used in preference to A. The relative losses are proport!onal to [il(rms)12 plus a factor to allow for the thermal regeneration. Currents can be compared by exponentiating the ratio by a factor of 2.5 giving a more realistic comparison of the actual losses. The exponent will always be greater than 2, just how much greater depends 100 ~Tc en... Table 3 Comparison Values for rms Switch Current :; ~ I- CIRCUIT L Vs A Small 20V 3.0A B 2.79A :V·5{~V·5 20V 2.65A 2.42A 1.25 Small 25V 2.74 2.35 1.47 Large 25V 2.37 2.03 1.47 Small 30V 2.51A 1.77A 2.39 10 a: a: ~-BL ~tt=B () c 1.43 I 1.0 ~ L- RDS(on) 1.44 "' Power Limit Limit C .P Breakdown 0.1 1.0 ,Willi 10 100 D 1000 V DS - DRAIN SOURCE VOLTAGE (VOLTS) 1.44 1.77A TTl Current Limit :::l « a: 1.44 2.17 ~.Bs} 2.5 1.20 L.arge 30V zw 25°C 150°C III Z 1.36 Large t=Tj 1 Typical MOSFET SOA Curve Figure 23 1.66 4-12 two straight lines (dotted lines Figure 24) in the data sheets since this gives a more accurate definition of this boundary. 100 Tj enc.. f - - RDsLlmit DC :2: I- 2 10 w cr cr ~;;.. The data sheet SOA curve is not unique, even for one particular device. The reason is the SOA boundaries do not generally represent limits which, if exceeded, will result in immediate destruction, but rather these boundanes are limits beyond which the service life of the device becomes unacceptable. What is acceptable in one application may not be in another. To illustrate this point, we have added a third aXIs to the SOA curve (Figure 25) to represent useful life. As the boundaries are reduced, the useful life of the MTBF increases dramatically at first and then more slowly. This is why in applications where especially long service life or very high MTBF is required, significant derating may be needed beyond manufacturer's specifications. ~ ~DS limit Pulsed .. .' ~., (J .' 2 0 ./ ' ::J « cr I' I ~ 25°C 1.0 I V' 1/" FTj 150°C 0 ....... - Siliconix Approximation 0.1 10 100 VOS - DRAIN SOURCE VOLTAGE (VOLTS) 4. Snubbers can be used to remove some or all of PS. There are many different snubber circuits, and the literature is quite extensive [2-6]. The reduction in Ps will depend on the particular circuit chosen. The SOA curve is also a function of the Tc, Tjmax, tp and D. The data sheet SOA curve will normally be for Tc = 25°C, a single pulse, and a few different values of tp. Few actual applications enjoy these particular conditions. The manufacturers should not be criticized since there are an infinite number of possibilities, and they have merely chosen to standardize on one, to allow a direct comparison between different devices. The MOSFET SOA curve is also patterned after the traditional Bipolar Junction Transistor SOA graph. 5. An HP-41 program for calculating ID(rms) is given in appendix A.l. This will greatly simplify the rms calculation and make it easier to optimize the circuit. For each application, the user must create an SOA curve that reflects his specific requirements. Fortunately this is not a difficult task. RDS(on) SOA Boundaries Figure 24 The SOA Curve Useful life A typical example of a MOSFET data sheet SOA curve is given in Figure 23. The curve exhibits four limiting boundaries: maximum current (A-B), maximum power (B-C), maximum voltage (C-D) and the RDS(on) limit (E-A). The current limit is set at a level which limits the current density in the bonding wires and in the die surface metali· zation to provide reliable operation. The power limit is that power dissipation which will raise Tj from Tc to Tjmax. The voltage boundary is determined by the designed breakdown voltage of the device. Actual breakdown voltage of the device is higher than this limit but varies from one device to another and varies with temperature. The SOA boundary is selected to lie inside of all normal variations. The RDS(on) limit is due to the minimum "on" resistance of the device. For example, it is not possible to have IDA flowing through a 2Q resistor when only I V is applied. or MTBF Vos At the present time, all manufacturers do not draw the RDS(on) boundary the same way. The solid line in Figure 24 shows the actual limit allowing for the heating of the device due to the power being dissipated. The dashed lines represent the boundary for RDS(on) at 25"C and 150'C. Any of the three boundaries may appear on a data sheet. Siliconix has elected to approximate the actual limit with A Three Dimensional Representation of SOA for a MOSFET Figure 25 4-13 How to Create Real-World SOA Curves 2. Tjmax = 125°C Figure 26 is a typical data sheet SOA graph. As pointed out in the previous section, this graph is valid only for one set of conditions which in this case is: 3. Tc 85°C 4. tp 200 psec 5. D 0.25 6. The device is an lRF440 7. Rejc = IOC/W 8. ret) = 0.27 (from Figure 6) 2. Tc 3. D 4. tp o STEP 1: Re-draw the RDS(on) limited boundary. A typical user might wish to make the following changes: Points on the boundary for Tj < 125"C can be calculated from the following expressions: I. Tc higher 2. Tj lower 3. Repetitive pulses, D = 0 4. Derating of VDS and ID 5. A tp other than that shown on the graph (33) ID= ROjc ret) RDS(on) RDSN (Tj - T cJ RDS( on) RDSN VDS = (34) Rejc ret) For Tj = 125°C the boundary is defined by: The new SOA graph can be created with a simple step by step procedure as shown in the following example: ASSUME: A plot of the RDS(on) boundary for this example is shown in Figure 27. The values for RDSN are taken from Fig. 28. Voltage and current derating factor = 0.8 I. 100 100 , en 0- ::;: ~ I2: ." " 10 100 j1sec " w 2: ;;: I .P 1.0 / :::::: - 0.1 1.0 Tj ETj ;;: = 150°C a: Tc = 25°C tp = 100 j1sec and DC 0 100°C ,/' (,) 2: E::=:: .,.-: ,0 t?' 10 ~ DC ", 125°C ~ a: a: ~ (,) 0 Tj 0- ::;: ~ I2: w a: a: a: en /" 1.0 I eTj 0 V 85°C Single Pu Ise II,I!!! !I 10 100 0.1 1000 1 V DS - DRAIN SOURCE VOLTAGE (VOLTS) 10 100 V DS - DRAIN SOURCE VOLTAGE (VOLTS) IRF440 SOA Figure 26 The Modified ROS(on) Boundary Figure 27 4-14 Two points corresponding to this power are: VDS 40 60 80 101) 120 140 160 180 10 A SOV 2.97A B 200V 0.74A Now plot these two points and draw a straight line between them. This becomes the pulsed power boundary as shown in.Figure 29. TEMPERATURE (OC) The Effect of Temperature on ROS(on) Figure 28 STEP 2: Re-draw the ID and VDS boundaries parallel to the original boundaries but reduce them by a factor of 0.8 as shown in Figure 29. Note in this case the 10 boundary does not exist because the ROS boundary takes precedence. The graph in Figure 30 (solid line) is the final SOA curve for the IRF440, given the specified operating conditions. In comparison to the original SOA curve (dashed line), the new curve is very different. Clearly, if you use the unmodified curve, it is highly probable that device failure would occur if the device is operated anywhere near the original limits. Conclusion STEP 3: Re-draw the thermal boundary. The total power for the boundary can be determined from: TJ·-T c PT= As we have shown, the thermal calculations for a power MOSFET are not particularly complex or time consuming. It has also been shown how important these calculations are to achieve an efficient and reliable design. Most design parameters are under the designer's control, and by juggling the variables around a bit, an efficient design can usually be aclueved. If the thermal design is overlooked or given a short shnft, there is small chance for a successful design. (36) 148W ret) Rojc 100 100 Data Sheet SOA ... ::E if ::E ~ I- zw a:: a:: Ul ~ r\.. 10 I- zw a:: a:: Derated Power= :> :> z ({ a:: z ({ a:: CJ C I " 1.0 .9 C I C 1.0 10 100 == _J - =r _ Tc- II 0.1 1.0 ~~ - Derated BVDSS 1000 V DS - DRAIN SOURCE VOLTAGE (VOLTS) Rt ,'. CJ 0.1 1.0 125°C 85°C _ tp = 200 11 sec D = 0.25 I II1II " -, ~ 10 SOA " I 10 100 1000 V DS - DRAIN SOURCE VOLTAGE (VOLTS) Modified Boundaries for BVOSS and Power Figure 29 Final SOA Graph for the IRF440 Figure 30 4-15 References [1] W. Roehr, "Mounting Techniques for Power Semiconductors," Motorola Application Note AN778, February 1978. [2] R. Walker, "Circuit Techniques for Optimizing High Power Transistor Switching Efficiency ," Proceedings of POWERCON 5, May 1978. [3] T. Undeland, "Stress Reduction in Power Transistor Converters," IEEE-lAS Annual Meeting Proceedings, October 1976. [4] Harada, Ninomiya and Kohno, "Optimum Design of an RC Snubber for a Switching Regulator by Means of the Root Locus Method," Proceedings of the IEEE-Power Electronics Specialists Conference, June 1978. [5] G. Edwing and R. Isbell, "A New High Efficiency Tum-Off Switching Aid for Power Transistors in Switching Regulators," IEEE Journal of Solid State Circuits, Volume SC-17, November 6, December 1982, pp. 1210-1213 [6] E. Calkin and B. Hamilton, "Circuit Techniques for Improving the Switching Loci of Transistor Switches in Switching Regulators," IEEE Transactions on Industry Applications, Volume IA-l2, No.4, July/August J976. 4-16 4.2 HP-41CV Power MOSFET Thermal Analysis Program Introduction MOSPOWER FETs are being used in more and more switching circuits now that high voltage and high current devices are available at reasonable cost. One of the most misunderstood facts about MOSFETs is that they are not immune to thermal runaway when driven with gate-to-source voltages between 10 and 20 volts. Under these conditions, the drain-to-source on-resistance (RDS(on» increases exponentially with junction temperature and, consequently, so does the power dissipated by the MOSFET for a given RMS drain current. 8. Thermal resistance junction to case (Rojd 9. Thermal resistance case to heatsink (Rocs) 10. Thermal resistance heatsink to ambient (Rosa) Regression constants "a" and "b" are used by the program to determine the value of RDS(on) at different values of Tj. These constants can be obtained from an exponential curve-fit to data points taken from the normalized RDS(on) versus the Tj curve. This curve shows RDS(on) as a function of Tj normalized to its value at 25"C, and is of the form y = aebx . Most manufacturers now include the curve as part of their MOSFET data sheets. Proper heatsink design, as with bipolar transistors, is essential. Reference 1 gives an excellent account of thermal design for MOSPOWER FETs and presents an accurate graphical approach for selecting a heatsink with the correct thermal resistance. The curve fitting can be done using the exponential curve-fit program EXP which is included in the HP41 Statistics Pac. If this Pac is not available, then the thermal analysis program can be instructed to calculate constant "b" given the value of constant "a". This method is much faster than a separate curve-fit operation, but the accuracy is reduced slightly. In many cases though, this reduced accuracy is more than adequate for the thermal program to calculate useful results. This application note presents a program for the HP41CV programmable calculator that computes the total dissipated power (PT) and the operating junction temperature (Tj) of a MOSPOWER FET. The program features prompting for the ten input variables required and fast convergence to the solution (if one exists). Theory The ten input variables required are: 1. 2. 3. 4. 5. 6. 7. The program uses two iterative algorithms to determine the points on the Pr versus Tj curve at which the tangent line touches it and the Roja line intersects it (refer to Figure 1). Roja is the total thermal resistance from junction to ambient and is equal to ~c + Roes + Rosa· By finding the point on the P'f curve at which the tangent line touches, the range of Tj for which a solution will occur can be determined. This range will extend from Ta to either Tj(maximum) Regression constant a Regression constant b Fixed MOSFET power loses (PI) RMS drain current (ID(RMS» RDS(on) at 25"C AmbIent temperature (Ta) Maximum operating junction temperature (Tj(maximurn) ) 4·17 _ I and so: I'T(W) 4. Tj = Ta 4. 3. 3. 2. (4) KlabebTj By choosing an initial value of Tj = Ta + lib, the first iterative algorithm evaluates approximations of Tj(tangent) according to: 20 15 ,. PI + lIb + --"..,.- Tj(i) I'T . .. 7' (To) 100 125 150 Ta + lib PI + ---..:....,.,--,-Klabe{bTP-I)} (5) The convergence. condition chosen for this algorithm is that Tj(i)-Tj Y? 228 GTO 09 229 RCL 11 230 STO 14 231 GTOOS 232.LBL 09 233 RCLll 234 STO 15 23S GTO 08 236+LBL 10 237 "PT=" 238 ARCL 17 239 PROMPT 240 ''TJ='' 241 RCLll 2421NT 243 ARCL X 244 PROMPT 245 GT002 246 END - Practical Design Considerations _ Chapter 5 Practical Design Considerations 5.1 High Speed Gate Drive Circuits Introduction Many design aids and application notes have been written about driving power MOSFETs directly from CMOS or open-collector TTL logic. These schemes are very attractive because of their simplicity (see "Using Power MOSFET Transistors to Interface from IC logic to High Power Loads" in Section 6.3), but the switching times of MOSFETs driven in this manner are often too slow for many applications. This is not by any means a result of the MOSFET having inherently slow switching times; in fact, any power MOSFET can be switched ON or OFF in less than 10 nsec if desired. When a MOSFET is driven by logic, the loss of its potential high speed switching characteristics is actually due to the limited peak output current available to charge or discharge the effective gate-to-source capacitance. (Qg) required to change the gate-to-source voltage from 0 to 10 volts, or vice-versa, also increases. Logic gates, with their very limited peak output current (or iJQ/{)t) capability, are inevitably the limiting factors if used as gate drivers for modem, large power MOSFETs. Additionally, a phenomenon known as the "Miller effect" causes the effective gate-to-source capacitance of a common-source connected power MOSFET to assume a much larger value than its static specification during a switching transition. This phenomenon, illustrated in Figure 1, is well known to the designers of analog circuits and is often used to advantage. However, in high-speed gate drive circuits, it necessitates a substantial peak output current capability. Since Cgs(~ff) ~ iJQiiJVgs , from Figure 1 it can _ be seen that this parameter is essentially constant at about 700 pF below VGS = 6 volts. Cgs(eff) The larger the die area of the power MOSFET being driven, the larger its effective gate-to-source capacitance (Cgs(eff». Consequently, the total gate charge ;;; !:i 400 Vos=o w Cgs(eH) = 1900 pF .......... ~ !1 ..... = 700 pF _ I 3UDY 200 I;i! z ~ c ...!'! I ~ 0 4. o P;w , I I W400V I I I I I I 111- 7 l"tO'1 L CHARGE (ne) 400 .. RL = 10011 VGG = lOY w IN ~ Ii Vos = 0 w ~ 12 g !;! • 5 10 1520 25 30 35 Q- TURN-OFF CHARGE ~ 16 Uhf 2OOV,-HA' 300 Cgs(etf) [ TURN·ON CHARGE ~ . 4 ~ 0 I 300 I I I II ~'"' I II ~lJ II 300V \i- 200V c~ II 051015202530 Q- CHARGE (ne) The Q g Versus VGS Charge Transfer Curves for the Siliconix VNDA40 Geometry Show the Occurrence of Maximum Effective Gate to Source Capacitance at a VGS of Approximately 7 V Figure 1 5-1 200 YS=400V , 00 Rgen = 2 n, the four switching times for the MOSFET depicted in Figure 1 are as follows: increases rapidly when the MOSFET turns on or off at VGS = 7 volts, as indicated by the approximately horizontal portions of the tum-on and tum-off VGS versus Qg charge transfer curves. Above VGS = 7 volts, Cgs(eff) returns to a lower constant value of approximately 1900 pF. One can see that, due to the large capacitance in the "horizontal" region of the curves, a relatively large amount of charge is required to change VGS by only a fraction of a volt. td(on) = tr td(off) = tf = ON 10.2 nsec 4.3 nsec 4.3 nsec For a low value of Rgen, we see that the MOSFET will switch very rapidly. However, a low value of Rgen also means that the peak MOSFET gate current can be large during the switching transition. Increasing the value of Rgen reduces the peak gate current drawn by the MOSFET but degrades the switching speed of the device. It is up to the designer to trade off switching speed against peak MOSFET gate current for a particular application. It is difficult to quantify the actual value of C gs (eff) in the "horizontal" region of the charge transfer curves because it varies with VDS. In practice, one really doesn't need to know the value of Cgs(eff) in the "horizontal" region anyway. The curves shown in Figure 1 provide enough information to accurately determine how fast a MOSFET will switch when dri ven by a particular circuit. OFF 1.7 nsec OFF ON Vos Vos 90% 90% VGG '---+-1::1-- Vg, Vg ' 0 9 1 0 92 Og3 0 9 209 1 Qg3 TURN-ON TURN-OFF This Circuit May Be Used to Model the Current Source Driver Circuits Such as the Siliconix 0469 IC Figure 4 Switching Time Equations Q,l ld(on) "" Vgi t. 2- Qg QgJ If = - y y Rgen In g2 - Qg3 - Qg2 VGG ) Rgen 1n \VGG - Vgl gl (I) (VGG - Vgl) - y - - y - (2) GG - g2 (VGG) td(off) = VGG _ Vg2 Rgen In Qg2 - QgI (Y,,) Vg2 - Vgl Ygi If=--Rgenln Vg2 - (3) Certain gate drive circuits will appear to a MOSFET not as a voltage source with a series output resistor Rgen, but rather as a current source (or sink). This is the case for both the 0469 and OS0026 IC drivers to be discussed later. Figure 4 shows a circuit that can be used to model these two devices. If the peak output capability of a current-source type driver is known, the total tum-on or tum-off time for a power MOSFET driven by it can be very easily determined. (4) These Four Equations Enable One to Calculate the Switching Times of a Power MOSFET, Based on Classical Circuit Analysis of the Driver Circuit Model Shown in Figure 3 Figure 2 Rgen VGG t v -= 1 ,J By definition: 09 Cgs(eH) = d Vgs ~t ~Q = -1- (5) If the MOSFET depicted in Figure 1 is driven by a current-source driver with a 3 A output sink or source capability, the total tum-on or tum-off time, assuming a VGS swing of 0 to 10 volts and vice versa, is: This Simple Circuit Can Be Used to Model a Voltage Source Type Gate Drive Circuit Figure 3 25 nC ton (or toff) = ~ = 8.33 nsec In Figure 2, the pertinent equations for determining the four switching times td(on), tr , td(off), and tf are given, based on classical circuit analysis of the driver circuit model shown in Figure 3. In order to minimize the switching times, it can be seen that the output resistance Rgen must be made as low as possible. Doing this also increases the immunity to possible mode 1 (aVOS/at) breakdown (reference Section 5.4). As an example, if we let VGG = 10 V and This is a very fast switching time for any power MOSFET regardless of the application, but in many cases, more moderate switching times and hence lower gate currents will suffice. Let's examine three groups of high-speed gate drive circuits suitable for driving most of the larger power MOSFETs available when the required switching times are less than 50 nsec. 5-2 draws with one output at zero volts (30 mA) means its average power dissipation at low MOSFET duty cycles will be quite large (as high as 0.5 watts). Additionally the DSOO26 is configured as an invertingonly driver and requires two external TIL inverters when non-inverting drive is required. Direct Coupled Drive Circuits Using ICs Alone Until now, the most popular IC for driving MOSFETs in high speed switching applications has been the DS0026 MOS clock driver made by National Semiconductor. This dual-channel bipolar IC can sink or source a relatively large peak output current (1.5 A) and has inherently small propagation delays within its internal circuitry. It also operates from a wide supply voltage range (22 V). As an alternative, the D469 CMOS quad power MOSFET driver from Siliconix can be used to replace the DS0026 in just about all but the higher speed switching applications. Each driver in the D469 may be configured as being either logically inverting or non-inverting and can sink or source a peak current of 0.5 A. To obtain greater peak output current capability, necessary when driving large capacitive loads, each of the D469s outputs may be connected in parallel if desired. Unfortunately, the DS0026 has some drawbacks which prevent it from being the "perfect" IC driver. Since the DS0026 requires a large logical "1" input current (10 mA), it is unsuitable for use in applications where the control logic is LS TTL or high-speed CMOS. The large quiescent supply current the device 1 DS0020 +12 V +60Y 46.11 NON-INDUCTIVE o 1 fLF CERAMIC 100pF BNe IRF 243 INPUT 470n DSOO26 6211 20469 +12V +60 V ... ~ 46U NON-INDUCTIVE I. ~----------~l)T~ 13 BNe IRF 243 12 INPUT 0469 11 I. SOil 2,4,6,7,9 The Schematic Diagram of the Test Fixture Used to Evaluate the SWitching Performance of the DS0026 and 0469 Shows Identical Load Conditions for Each Device FIgure 5 5·3 l1:li Both the DS0026 and D469 were incorporated into a test fixture driving identical power MOSFETs with identical loads so that their switching performance could be compared. Figure 5 shows the schematic diagram of this fixture. The power MOSFETs used were Siliconix IRF243s with a maximum static Ciss of 1600 pF and a maximum static Crss of 300 pF. 44 nsec, respectively, while the DS0026s were 26 nsee and 42 nsee. It appears that the DSOO26 was somewhat faster (by 10 nsec) on the rising edge of its waveform than the D469, but both had very similar fall times. Some further tests were conducted to see how the D469, with two or more outputs connected in parallel, compared to the DSOO26 with both of its outputs connected in parallel. The load resistance for both MOSFETs was approximately 4.6 ohms (non-inductive), and the power supply voltage was 60 V. Both the DS0026 and the D469 were powered from a separate 12-volt power supply and driven by a TTL level pulse train. The pulse train had a pulse width of 150 nsec and a repetition rate of 1 kHz. DSOOJv-- V-- 01& r , /7 r'== 'Y ~ ~ 7' 0469/J 'l J 0469 - / / This Graph Shows the Gate Waveform Rise Time for 2 Paralleled DS0026 Outputs Versus 4 Paralleled 0469 Outputs (Vert: 2.4 V/Dlv. Horlz: 20 ns/Div) Figure B J This Graph Shows the Gate Waveform Rise Times for 1 DS0026 Output Versus 2 Paralleled 0469 Outputs (Vert: 2.4 V/Div, Horiz: 20 ns/Div) Figure 6 '" ~ ~ \\ ........; 0469 1\\ 1\ \ DSj"\ D\ I>..,; '" t\ ~ - The Fall Times of the Gate Waveforms for 2 Paralleled DS0D26 Outputs Versus 4 Paralleled 0469 Outputs (Vert: 2.4 V/Dlv, Horiz: 20 ns/Dlv) Figure 9 040. DS0026~ \\ Figures 8 and 9 show the rise and fall times of the gate waveforms for the D469 with four outputs in parallel versus the DS0026 with two outputs in parallel. Here it can be seen that the DS0026 with rise and fall times of 22 nsec and 30 nsec, respectively, was still the faster of the two - but not by much. The D469 came in a very close second with rise and fall times of 32 nsec and 42 nsec, respectively. Interestingly enough, the rise and fall times of the D469 with four outputs connected in parallel were virtually the same as those with only two outputs in parallel. The rise and fall times for the DS0026, on the other hand, showed some improvement. The Fall Times of the Gate Waveforms for 1 DS0026 Output Versus 2 Paralleled 0469 Outputs (Vert: 2.4 V/Dlv. Horiz: 20 ns/Dlv) Figure 7 Since the DS0026 contains two independent drivers and the D469 has four, a fair test would be to compare the two devices as dual drivers. Thus, two D469 outputs were paralleled and compared to a single DSOO26 output in drive capability. Figures 6 and 7 indicate that on a "per chip" basis, the D469 was essentially the equal of the DS0026. To be precise, the D469 gate waveform's rise and fall times were 36 nsec and 5·4 The main difference observed between the D469 and the DS0026 was the propagation delay-time each device exhibited. For the D469 this parameter was approximately 50 nsec while that of the DS0026 was in the range of 5 to 10 nsec. Figure 10 clearly show~ this difference. It should be noted that Figure 10 is the only one in which the difference in propagation delay is shown. Figures 6 through 9 do not show this because it is easier to compare switching waveforms when the oscilloscope traces are overlaid with one another. / / 'r---- I( J 050026 --../ /"" I r-- /0469 l When it is desired to drive very large single chip or multichip power MOSFETs with switching times in the range of 50 nsec to 20 nsec, a current booster stage may be added to either a D469 or a DS0026 with no loss of switching speed. Figure 11 shows how a complementary MOSFET booster stage can be connected to one output of a D469. The additional output buffer functions in exactly the same manner as a CMOS logic inverter, and its output voltage swings all the way to either power rail. Current is only drawn by the buffer during switching transitions; consequently, the average power it dissipates is proportional to the switching frequency. The buffer may also be used by itself if the TTL input level compatibility of the D469 is not required. '\ VDD \ 1\ \ ...."' "...../ J.~1 J J ~~ This Graph Clearly Shows the 50 ns Difference in Propagation Delay Between the DS0026 and the 0469 (Vert: 2.4 V/Div, Horiz: 20 ns/Div) Figure 10 MOSFET BEING DRIVEN I ~ NOTE: 01 AND 02 COMPRISE 1/2 A VQ7254 POWER MOSFET ARRAY A Simple CMOS Current Booster Stage Can Be Added to a 0469 Output to Increase Its Output Capability, or May Be Used on Its Own Figure 11 In summarizing the results of this comparative test, we can say that the D469 is really a DS0026 in a "CMOS disguise." Although the DS0026 was faster than the D469 in both cases, its speed advantage was no more than about 10 nsec in any of the rise and fall time measurements. As a two-channel driver the D469 is the obvious choice, especially when one considers its low power consumption compared to the DS0026. In the test fixture shown in Figure 5, the DS0026 drew an average supply current of 30 rnA and thus consumed about 360 mW of power while the D469 drew an average current of slightly more than 2 rnA and consumed about 25 mW of power. Needless to say, the DS0026 ran quite hot to the touch while the D469 was cold. The 50 nsec propagation delay of each driver in the D469 should not pose any problem at all as long as the MOSFETs in a particular circuit are all driven by D469s. Depending on the MOSFETs used in the buffer stage, the available output current can be as high as several amps. For the VQ7254 dual complementary pair shown in Figure II, the pulsed output current specification is three amps. This is a six-fold improvement over the 0.5 A peak output sink/source, capability of each channel of the D469 alone. For very high speed applications where MOSFET . ' switching times of less than 20 nsec must be achieved, both small internal propagation delays and high peak output current capability are the necessary characteristics of a gate driver circuit. Figure 12 shows a circuit which works very well with large capacitive loads. When the input to the driver is a logical "0," QI is held in conduction by one half of the DS0026, and Q2 is clamped off by QI. When a logical "I" input occurs, QI is turned off and a current pulse is applied to the gate of Q2 by the other half of the DS0026 through TI. After about 20 ns, TI saturates, and Q2 is held on by its own egs and the bootstrap circuit comprised of CI, DI and RI. For pulses less than 50 ILsec wide, the bootstrap circuit may not be needed because the input capacitance of Q2 discharges very slowly. At the end of the logical "I" input pulse, QI turns on, shutting off Q2. Direct Coupled Drive Circuits Using Discrete Components If the IC gate drivers described above begin to become the limiting factor in the performance of MOSFET switching circuits that use them, it is inevitably the result of two factors: (1) The peak output current capability of the IC is not high enough. (2) The device has inherent switching times which are too slow. 5-5 PERFORMANCE SUMMARY V+ '-'"F 5011000pF 20 15 225 7 15 4700pF 20 15 225 1fi 16 15.5 511 20 15 23 11 14 45 SU 50 20 22 18 14 1IX1RG2231U TERMINATED IN51 n 20 15 20 5· 19 13· V+ + 1 - 0 001 ",F 1-0.01 ",F } PARALLEL IN914 0, '000 pF 65 C, • MEASURED AT INPUT TO CABLE 100pF Sl PWM . , c>---+---A/IIv--4 5 V... ,/2 OS 0'" T1 -IS THREE TURNS 30 BIFILAR ON A FERRITE BEAD A Circuit Capable of Driving Very Large Capacitive Loads Is Shown in This Diagram Along with Its Tabulated Performance Under Varying Load Conditions Figure 12 If a wide range of duty cycles must be accommodated then the MOSFET gate will be overdriven at low duty cycles and underdriven at high duty cycles. This can lead to variations in the total MOSFET switching time as is evident from equations (1) to (4). However, for those applications where only a moderate variation in duty-cycle is to be accommodated, this simple circuit can work very well. One can see that the switching performance of the above mentioned driver is extremely good with large capacitive loads, and it is suitable for driving even the largest currently available power MOSFETs. ffigb Speed Isolated Drive Circuits Many switching applications involve driving power MOSFETs from control logic or other circuitry that is ground referenced. The question that inevitably arises is: how does one drive power MOSFETs whose sources are not ground referenced? The solution, of course, is to use some form of DC isolation between either the control logic and the driver or between the driver and the MOSFET(s). VDD ~VSl. . rt/4'"7OIT,lqJ F D469 DRIVEN MOSFETBEING ° ~ "':" There are basically two viable methods that can be used to provide DC isolation between a MOSFET and its associated control circuitry when necessary. These are: "':'" a) This Simple Transformer Coupled Circuit Provides Isolated Drive for the Power MOSFET 1---. I I (I) Transformer isolation (II) Opto-coupler isolation I ' VGS o~~~--+-4--'----------~ Each method has its own inherent advantages and disadvantages as far as performance/cost trade-offs are concerned. We will examine them in more detail. b) The Resulting Gate Voltage Can Be Seen to Be an Asymmetrical AC Waveform, Whose Amplitude Varies with Duty Cycle Figure 13 (I) Transformer isolation Figure 13(a) shows a simple transformer drive circuit that effectively isolates the ground referenced D469 from the n-channel MOSFET with a floating source. Unfortunately, this circuit has a major problem: the AC waveform across the primary winding can be asymmetrical. This follows from the fact that the average of the transformer winding volt-seconds product must equal zero as shown in Figure 13(b). Therefore, the gate enhancement voltage of the MOSFET will vary with duty cycle, being greater at low duty cycles and smaller at high duty cycles. There are transformer isolated drive circuits where VGS does not vary with duty cycle. Figure 14 shows a transformer coupled drive circuit in which the primary winding sees only a symmetrical AC waveform. VGS is fixed by the voltage swing at the output of the D469 drivers and the turns ratio of the transformer. The AC voltage swing across the primary of the transformer can be seen to have a peak to peak value of 2 VDD since one D469 output is at 0 volts while the other is at VDD and vice-versa. 5·6 PRIMARY DRIVE CIRCUITRY II This Transformer Coupled Drive Circuit Generates a Symmetrical Gate to Source Voltage Waveform for Each MOSFET, Whose Amplitude is Independent of Duty Cycle Figure 14 A Bipolar Transistor and Its Associated Components Reduce the Effective Drive Impedance Presented to the Gate Terminal of the MOSFET Figura 15 C 1 is added to the circuit to prevent a DC component from appearing across the primary of T 1 due to a potential lack of symmetry in the switching times of the two drivers used. The value of Cl is determined by the magnetizing current of Tl. It should be large enough so that the voltage drop across it due to the magnetizing current during one half a cycle is small compared to VDD. adding a bipolar transistor Ql and its associated components as shown in Figure 15, these problems can be overcome. At turn-off, Ql is driven on by the energy in Tl, clamping the gate of Q2 to its source. Even after all the energy in Tl is discharged, Ql still presents a relatively low impedance to the gate ofQ2· (II) Opto-Coupler Isolation Of course, current booster stages may be added to the D469 outputs in Figure 14 to increase the drive current to the primary winding and hence the gates of the MOSFET(s). Additional isolated windings may also be added to Tl so that totem pole MOSFETs in bridge circuits may be driven as illustrated in Figure 14. Figure 16 shows a different method of providing DC isolation in a totem pole MOSFET "H-bridge" circuit that uses n- and p-channel devices. Here a D469 driver is referenced to the positive power supply rail and an opto-coupler is used to provide DC isolation between it and the low voltage control logic. A - 12 volt power supply, referenced to the positive rail, is generated for the D469's ground pin with a zener diode, capacitor, and resistor. Often the impedance of the secondary winding(s) that drive the MOSFETs may well be high enough to cause mode 1 (lJ VDStat) triggering problems. By 112 DUAL OPTOCOUPLER .-"-.. "r.o LE~~ OR~ ~ . 1 1/40469 NOTE D IS A 12 VOLT ZENER This Schematic Diagram Shows a Different Method of Providing Isolation - Floating a D469 Driver and Optically Coupling the Logic Drive to the Upper MOSFETs Figure 16 5·7 ~~E. - The 0469 in this example provides gate-drive voltages for the p-channel MOSFETs that swing from the positive rail to 12 volts below it. The reservoir capacitor (C) must be large enough to ensure that sufficient charge is available for transfer to the gates of the pchannel MOSFETs. References [1] Rudy Severns, "Using the Power MOSFET as a Switch," Intersil Applications Note A036, 1981. [2] Mark Alexander and Jim Harnden, "The D469: An Optimized Quad Driver for MOSPOWER FET Switches," Siliconix Applications Note AN8311, 1983. Here again a complementary MOSFET current booster stage can be added to the floating D469 as well as to the ground referenced one to increase the output current capability. 5-8 5.2 Temperature Compensated Biasing for Power MOSFETs in Linear Amplifiers Introduction tial drain current (and hence gate-drive) is required, the drain current decreases as the junction temperature increases, causing the device power dissipation to decrease as well. If adequate heatsinking for the power MOSFET is provided then thermal runaway will not occur. Many of the highest performance audio amplifiers available today use power MOSFETs in their output stages. The advantages of using power MOSFETs instead of bipolar transistors in an amplifier output stag,.e have been well described in numerous artic1esL1,2,3]; however, important thermal characteristics of MOSFET output stages are often overlooked. The purpose of this application note is to familiarize the designer with these characteristics and to show how to compensate for them when necessary. Linear amplifiers, on the other hand, generally require a certain value of quiescent current in the output stage to minimize crossover distortion. This value of quiescent current is normally made less than 100 rnA per device to minimize power dissipation with no output signal. The problem here is that the quiescent gate-to-source bias voltage of each MOSFET may only be a few tenths of a volt greater than its threshold voltage (VT). Under these conditions, the temperature coefficient of drain current is positive, and if not compensated for, can result in thermal runaway in the _ output stage. It is a misconception that power MOSFETs have a negative temperature coefficient of saturated drain current at all values of gate-to-source voltage. Figure 1 shows that for large gate-drive voltages (six volts and above) the temperature coefficient of a power MOSFET is negative. In applications where substan- VDS~15V 1// -55"1V V 25°C 5 2. 1.5 ZERO TO POINT 1. ~ ~ 4 47 An obvious solution might be to bias the MOSFETs in an output stage at the zero TC point indicated in Figure 1. This would be acceptable if the zero TC point occurred at a drain current value within the required quiescent bias current range of interest. Unfortunately, since most power MOSFETs exhibit a zero TC point at a gate-to-source voltage of between four and seven volts, the corresponding drain current (depending on the device) can be as high as several amps. Such a large value of quiescent bias current is unacceptable because the power dissipation at idle would then be very high. The output devices would inevitably fail due to excessive junction temperature if called upon to deliver any appreciable power to a load. IIV /; /" 1~ 5 / 150"C 1. VGs(V) The Saturated 10 Versus VGS Transfer Characteristics of an IRF521 n-channel OMOS Power FET Clearly Show the Occurrence of the zero TC Point at a VGS of Approximately 4.7 V Figure 1 5·9 100 Figure 2 shows a typical complementary MOSFET source-follower output-stage and its associated bias and driver circuitry. The biasing network is generally an adjustable DC voltage source connected between the bases of the complementary Darlington bipolar transistor driver stage. If this bias voltage generator is fixed with respect to the junction temperature of the MOSFETs, their bias currents will rise as they heat up. As the bias currents of the MOSFETs rise, however, the quiescent power dissipation increases and causes the MOSFET junction temperatures to rise even further. This is clearly an unstable situation and must be avoided in a viable amplifier design. v++ v++ SILICONIX 1 +--'IIIfV- "G v-- V .. / 30 20 / ,. zo l'L . 80 80 100 120 Trel Figure 3 ZL provide a reasonably accurate description of the IN characteristics. For VDS > Vas - VT and VQS > VT, the drain current of a MOSFET is given byL 4J DEVICE v-- i ~ 5. v+ BACK / 80 ~~1 I I I I I I I I I I I V 70 9 V / IRF521 80 JI~".~, INPUT AND GAIN STAGES OF AMPUFIER / 90 v- ID(SAT) = A Commonly Used Driver and Output Stage Configuration In MOSFET Audio Power Amplifiers Figure 2 ~ (1) (Vas - VT)2 where This paper investigates the physical phenomena that govern the behavior of power MOSFETs with temperature and presents two simple biasing circuits that effectively compensate for the positive temperature coefficient of drain current at low bias levels. ( . 1 - ILCoxW .. ,.. - -L-'- (the trans1stor gam) and Theory IL carrier mobility {cm2N.sec} The experimentally observed temperature dependence of saturated drain current in a power MOSFET ;s illustrated in Figure 3. Clearly, under low bias conditions the temperature coefficient of drain current is positive. In order to compensate for such a temperature dependence, we need to know which electrical characteristics of a MOSFET vary with temperature and which ones are dominant at low valuesofID· Cox gate capacitance per unit area {F/cm2} W total gate width {cm} L' electrically effective channel length {cm} threshold voltage {V} VT = Despite their structural differences, the conventional planar MOSFET and a DMOS power FET exhibit similar electrical behavior in the saturated region of operation. Consequently, conventional device models It is important to accurately determine the true threshold voltage of a MOSFET in order to obtain agreement between equation (1) and the actual device characteristics . 5·10 Most manufacturers specify a convenient, fixed value of drain current (usually 1 rnA) at which the "threshold voltage" is measured. True threshold, however, is measured at a current proportional to the transistors W/L ratio[51, and it is often substantially larger than 1 rnA. Consequently, the threshold values obtained by measurement of V GS at an ID of 1 rnA and at a value proportional to W/L can differ by as much as 0.5 volts. that the temperature coefficient of drain current is as follows[7]; The graph of JID(SAT) versus VGS shown in Figure 4 provides an accurate method for determining VT as well as 13[6]. The straight line portion of the graph corresponds to the "square-law" operating region described by equation (1) and has a slope of 13/2 and an x-intercept equal to the true threshold voltage of the MOSFET. One can see that the equation closely agrees with measured data over a wide range of drain current, including the bias range of most audio power amplifiers. (2) tempco (ID) = aID (SAT) aT = IIDI 2 aVT) ( 1 aIL ~ aT - (VGS-VT) aT From device physics, it can be shown that over the temperature range of interest[4,8] a) for an n-channel MOSFET, aIL aVT . • - and - - are negative aT aT • (VGS-VT)ispositive Yiii(SjiT) ID(SAT) (A) (A112) - 1A 0.950 0.900 f D.'" 0700 aIL . • - and (V GS - VT) are negative aT I O.BOO 0.750 b) for a p-channel MOSFET, '""'" t-- II SlUCONIX IRF521 aVT • - - is positive aT 05 A 0650 I 0600 0550 / 05DD I SLOPE =~ The two terms in equation (2) can be seen to have opposing signs for both n or p-channel devices. (083 A/V2) I 0450 At low values of the effective gate drive (VGS - VT) and correspondingly low values of ID(SAT), the second term in equation (2) is dominant, and the tempco is positive . 7 0.350 .7 0.300 . 0250 100mA II In conclusion, at low values of (V GS - VT) the temperature coefficient of drain current is proportional to the temperature coefficient of threshold voltage. Figure 5 shows the experimentally determined _ threshold variation with temperature of a power MOSFET. Typically this change in VT is in the range .j 0.200 0150 lSmA II II 0.100 . ... 0050 2.0 2.2 2.4 lOrnA ~ II 2.6 28 1 mA 3.0 TRUE Yy 3.2 3A 36 3.8 40 42 4A = 2.92 V 2. VGS(V) A Method to Determine the True Threshold VT (and Transistor Gain B/2) from the Saturated Drain Current Transfer Characteristics (@ VDS = 20 V) Figure 4 , SILICONIX IRF521 ........ 2S ~ '" "'" 27 By differentiating equation (1) with respect to temperature, some insight can be gained into the temperature dependence of saturated drain current. The two terms in this equation which exhibit a variation with temperature are the carrier mobility and the threshold voltage VT. Differentiating equation (1), we see W""-3SmVI"C "'- ~ 2. 20 40 60 .. TEMPERATURE T (OC) Figure 5 5-11 ""I' 100 120 y++ of -2.5 to -6 mV/o e[4,9]. To achieve temperature compensated biasing then, the effective gate drive (Vas - VT) must remain nearly constant. This can be realized by controlling Vas so that it is varied by an amount equal to the change in threshold voltage with temperature. We now examine two practical circuits that provide output stage bias stabilization by reducing the MOSFET gate to souree voltages as their junction temperatures increase. INPUT AND GAIN STAGES OF AMPLIFIER r I Ir A~UST T Compensated Biasing Circuits I I r r There are basically two means of providing thermal bias compensation in a linear amplifier. The first method is to electrically sense the output stage idle current and use some form of feedback control circuitry to ensure that the bias remains constant. The second method also uses feedback control, but instead of sensing the idle current, the case temperatures (Te) of the MOSFETs are sensed by a thermal sensor, and the quiescent gate bias is reduced accordingly as Te increases. The first method works well to keep the idle current in a MOSFET output stage constant, but it often degrades the electrical performance of the amplifier. What one achieves is a very stable amplifier over its operating temperature range; however, the resulting distortion specifications or output volta.&e swing will very likely be unacceptable[lUJ. y-- y-- y- NOTE Q4. 08 AND Qg ARE MOUNTED ON A COMMON HEATSINK Superior Bias Stability Can be Obtained In a Complementary Source-Follower Output Stage Using Dual VBE MuHlpliers Figure 6 with temperature divided by the variation in baseemitter voltage with temperature. This multiplication factor is typically greater than one. The other VBE multiplier generates the difference between the voltage of the upper VBE multiplier and the required DC bias voltage between the bases of the emitter-followers. By adjusting the VBE multiplication factor of the upper multiplier, adjustable bias for the MOSFET output stage is achieved. The second method, on the other hand, in no way electrically interferes with the drain-to-souree current paths of the MOSFETs in the output stage. As well, it can provide comparable bias stability to the first method, if implemented properly. For this circuit, the total gate bias for the MOSFETs is given by Two simple, thermally compensated biasing circuits for MOSFET power amplifiers using either complementary source-follower output stages or complementary common-source output stages will now be described. Both circuits take advantage of the - 2.2 mvr C variation in base-emitter voltage of a bipolar transistor to decrease the gate bias voltage of the MOSFETs in an output stage as they heat up. VBIAS == (1 + R3/R4) VBE(Q4) + (1 + R1/R2) VBE(Q3) - 4VBE (3) and iJVBIAS aT Bias Stabilization of the Source-Follower Output Stage Using Dual VBE Multipliers If (1 Figure 6 shows a complementary source-follower output stage driven by complementary darlington emitter-followers that have two VBE multipliers in series between their bases. One VBE multiplier transistor (Q4) is thermally coupled (Le., glued) to the heatsink on which the MOSFETs are mounted. R3 and R4 are then adjusted to provide a VBE multiplication factor equal to the total threshold voltage variation of the nand p-channel MOSFETs = (1 + R3/R4) aVBE(Q4) aT (4) + R3/R4) == 3, then aVBIAS == -6.6mVloC aT This decrease in MOSFET gate bias voltage with temperature effectively compensates for the decrease in VT of both the nand p-channel devices with temperature. 5-12 Bias Stabilization of the Common-Source Output Stage Using a Temperature-Compensated Current Sink This effective change in p-channel MOSFET gate to source voltage compensates for the change in its VT with temperature (which is positive, not negative). Another means of biasing a complementary power MOSFET output stage is shown in Figure 7. The circuit uses a fixed gate resistor and an adjustable current sink to provide variable bias for the p-channel MOSFET. Transistor Oz is thermally coupled to the heatsink on which the MOSFETs are mounted. As Oz heats up, its VBE decreases and causes the current drawn through the collector of 01 to decrease as well. This reduces the gate drive voltage of the p-channel MOSFET as it and the n-channel device heat up. The op-amp automatically controls the n-channel MOSFET to mirror the bias current of the p-channel device, which keeps the output centered at zero volts. Conclusions . v+ It has been shown that in linear power amplifiers, where the MOSFET bias current levels are low, the temperature dependence of VT is the dominant factor in the variation of ID with temperature. By compensating for this effect alone, a high degree of thermal stability over an uncompensated bias arrangement can be achieved. Figure 8 compares the temperature stability of drain current for the two biasing circuits described with the uncompensated thermal characteristics of the n-channel MOSFET used. Both of the bipolar transistor VBE referenced compensation circuits are extremely effective in reducing bias sensitivity to temperature . v+ , 275% 1 IBIAS::: 50 mA ..00/0 II 225% I ~~~TB~~~ Iy+ OUTr>-~-'VII'r--r-_ _--1I--_VO;:;:UT:.:., CIRCUITRY I v- 200% / ZL 175% t ~ lofT} X 100% ~ 04 n-CHAHNEL DEVICE 150% / VUNCOMP~NSATED / / I v- v- 125% NOTE: Q2. 03 AND 04 ARE MOUNTED ON A COMMON HEATSINK This Complementary Common-Source Output Stage Uses a Temperature Compensated, Adjustable Current Sink for Bias Stability Figure 7 100% ....... I v- IDEAL ~ / 75% -r----:::: - CURRENT SOURCE VBE MULTIPLIER In this circuit, the gate bias ofthe p-channel MOSFET is given by VGS(P) = -RZ I 1 + VBE(OZ) R1 (5) 20 40 60 80 T(OC) '00 '20 Figure 8 and aVGS(p) aT IfRZ/Rl _ RZ x aVBE(OZ) R1 aT (6) These circuits provide an inexpensive but necessary solution to the problem of bias stabilization in a MOSFET power amplifier without compromising distortion or output voltage swing. == 1.5, then aVGS(p) == +3.3mV/oC aT 5-13 - References [1] Robert R. Cordell, "A MOSFET Power Amplifier With Error Correction," presented at the 72nd convention of the Audio Engineering Society, October 1982 (AES preprint). [6] Richard S. Muller, Theodore L. Kamins, "Device Electronics for Integrated Circuits," John Wiley; New York, 1977, pp. 360-361. [7] William N. Carr, Jack P. Mize, "MOS/LSI Design and Application, "McGraw-Hill; New York, 1972, pp. 87-88. [2] Erno Borbely, "High Power High Quality Amplifier Using MOSFETs, " Wireless World, March 1983. [8] Edward Yang, "Fundamentals of Semiconductor Devices," McGraw-Hill; New York, 1978, p. 23. [3] Tohru Sampei, Shin-ichi Ohashi, "100 Watt Super Audio Amplifier Using New MOS Devices," IEEE Trans. Consumer Electronics, Volume CE-23 , August 1977. [9] William Penney, Lillian Lau, editors, Staff of American Microsystems Incorporated, "MOS Integrated Circuits, Theory, Fabrication, Design and Systems Applications of M os LSI," Krieger Publishing; Malaban FL., 1972, p. 84. [4] Paul Richman, "MOS Field Effect Transistors and Integrated Circuits, "Wiley: New York, 1973, pp.84-86,pp.124-133. [10] Bill Roehr, "A Simple-Direct Coupled Power MOSFET Amplifier Featuring Bias Stabilization," IEEE Trans. Consumer Electronics, Volume CE-28 No.4, November 1982, pp. 546-552. [5] Paul Richman, "Characteristics and Operation of MOS Field-Effect Devices," McGraw Hill: New York, 1967,p.142. 5·14 5.3 Parallel Operation of Power MOSFETs (TA 84-5) Introduction Motivation for Paralleling There are many reasons for operating power MOSFETs in parallel, either as multiple die on a common substrate or as individually packaged devices. Compared to paralleled bipolar junction transistors (BJTs), paralleled MOSFETs present fewer problems, require less derating, and provide higher performance. Parallel operation, however, is still not trivial. Problems can and do occur. To parallel devices successfully, the designer must understand both the causes and the cures for the problems. Fortunately, most of the cures are simple and are more a matter of attention to detail than of exotic or complex design. There are many possible reasons for paralleling multiple devices: This discussion attempts to identify all the problems that users potentially could experience and provides an explanation of each problem. Then it will tell how to recognize these problems and will give practical means for eliminating them. • • • • Lower RDS(on) Lower circuit inductance Improved thermal performance Compensation for radiation effects • • • • Lower cost Redundancy Higher ID Derating In switching applications, the majority of the power dissipation is due to RDS(on). If RDS(on) is made smaller, the power loss will go down. RDS(on) for a given device is determined by the active die area and the breakdown voltage (BV DSS). RDS(on) decreases more or less linearly with _ increasing die area and increases exponentially (factor ~ 2.5) Although the discussion is quite extensive, the final conclusions will show that all of the problems may be easily avoided and that paralleling MOSFETs is reasonable and, in many cases, highly desirable. However, because of the lack of prior, in-depth discussion of paralleling MOSFETs, it is necessary to substantiate this contention. with BVDSS. In theory, RDS(on) may be made as small as desired simply by increasing the die area, but the cost per unit area of the die increases exponentially when the die dimensions are greater than about 0.125" x 0.125". This increase in cost puts a practical upper limit on die size. Presently this is in the range of 0.25" to 0.30" square. In addition, as die are made larger, fewer and fewer package choices are available. When RDS(on) must be reduced even further, paralleling is the best alternative. Throughout the discussion, the object will be to maintain a balance between simple, practical advice and reasonable, theoretical explanations. Many designers experienced in BJT applications have a well merited aversion to paralleling devices unless it is absolutely necessary. While this is certainly appropriate for BJTs, such thinking is a distinct handicap when using MOSFETs because useful opportunities for improved performance or reduced cost may be missed. It is important to keep an open mind and to read carefully the following arguments. Because of the rapid increase in cost of the larger die and the restriction on suitable packages, there are often compelling reasons to use smaller die in cheaper packages even when a suitably low RDS(on) device is available in a larger die. For example, a size five die (0.25" x 0.25") will have one half the 5-15 RDS(on) of a size four die (0.18" x 0.18"). However, the size five die will not fit in a TO-220 package. It requires a TO-3. At current prices, the cost of two TO-220s would be twenty to twenty.five percent less than one TO·3. As prices drop further, production increases and competition grows, this price differential should grow wider. (io DRAIN LO V1 + It has been shown (1) that paralleling is an effective means for ----I reducing the junction-to-heatsink thermal impedance (Rejs)' To use the previous example, Rejs for a size five die in a TO-3 package is about 1.2°C/W; for a size four die in a TO·220 package, Rejs = 1.3°C/W; but two TO-220's in parallel would reduce the effective Rejs to 0.65°C/W. For the same ID(rms) and heatsink, RDS(on) will be lower because Tj will be lower. This may aHow a further reduction in die size or as an alternate, the heatsink may be made smaller thus reducing its cost. The thermal design issues are treated in detail in Reference (1). For high power pulse applications, the limitation may be on GATE V2 VOS VOO LS + SOURCE Mechanism Responsible for Internal Voltage Spiking at Turn-off ID(peak) rather than RDS(on)' Again paralleling provides a means for increasing the allowable peak current. Very often in pulse applications, rapidly rising (high dildt) current waveforms are required. Sometimes the limiting factor on speed is the package inductance. One means of reducing this inductance is to parallel several smaller devices so that the total effective inductance is decreased in proportion to the number of devices paralleled. Also smaller packages will tend to have lower inductances. FIGURE 1 Concerns about Paralleling Devices When considering a design using parallel FETs, a number of concerns and possible problems arise. Generally these concerns falI into four categories: 1. Steady·state current sharing 2. Thermal stability and maximum Tj 3. Dynamic current sharing during switching 4. Parasitic oscillations Another problem which can arise in fast pulse applications- if low voltage high current devices are used - is a degradation in the external BVDSS capability caused by voltage spikes generated by the internal connection inductance (2). Figure 1 shows a MOSFET with the internal parasitic inductances. At turn-off, ID is flowing. As the device is turned off, the voltage polarities will be as indicated. The actual voltage across the j unction will be d As is so often the case, many problems that exist in theory are not significant in the actual hardware. Nevertheless, in the following discussion, many possible problems wilI be explained. Steady-State Current Sharing VDS=VDD+(LD+LS)~ dt For example, if a 50 ampere, 100 V device with 20nH of internal parasitic inductance is switched in 20nsec, the internal voltage spike between the drain and source terminals (which is not visible externally) will be 50V! The usable value for BVDSS has been reduced to 112 its data sheet value. Paralleling several smaller devices, possibly in smaller, lower inductance packages, can reduce the effective value of parasitic inductance and increase the usable operating voltage. The distribution of current among paralIel devices is a concern to the designer. With regard to the effects of asymmetrical current sharing, three questions need to be answered: What is the maximum junction temperature among the devices? 2. Does the asymmetry cause a significant increase in total dissipation? 3. Is any device operating outside of its safe operating area (SOA)? 1. When MOSFETs are subjected to large neutron fluxes (> 1013 neutrons/cm 2), RDS(on) may rise dramatically. One means to ensure that the post irradiation RDS(on) is not unacceptably high is to start with a low value for RDS(on) (much less than required) in the unirradiated circuit. To achieve this, it is usually necessary to parallel devices. When the current is not distributed equalIy, some devices may run hotter than others. Because the operating reliability is directly related to Tj' it is important to identify the maximum Tj which can occur. Obviously if any device is operating outside of its rated SOA, the reliability will also be greatly reduced. 5-16 Furthermore, it is important to know if the conduction asym· metry is creating a power loss penalty. 10 The answers to these questions depend on the operating state of the devices. There are two possibilities: linear or switching operation. When the devices are used as switches, Vas will be large (lO·15V), and the devices will be fully enhanced. In this mode the device acts like a positive temperature coefficient resistor. TYpical ROS(on) versus Tj characteristics are shown in Figure 2. Note that ROS(on) has been normalized (ROSN) to 25° C for comparison purposes. 8 VDS =50V u;- a. ~ I- zW 6 II: II: :::l 0 Z «II: Zero Temperature ______ Coefficient Point (OTC) 4 C I 9 2 24 J 2.2 V 18 1.6 / 1.4 iii 0 c: 12 10 0.8 06 04 °OL-~--~2--~~~4~CL--~6L-~--~8 500V deVIce 20 I- - -~ ~~ /.. ,/' V V VGS-GATE SOURCE VOLTAGE (VOLTS) /' Typical Transfer Characterlsllcs for an IRF330 FIGURE3 V" /'OOV devlce- than average current to heat up more than the other devices, increasing ROS(on)' which in turn reduces its 10 , The degree of thermally forced current sharing present has been analyzed (3), and an outline of the analysis is presented here. ~ 02 o ·60 ·40 ·20 0 20 40 60 (A) 80 100 120 140 160 180 Vos ! The Relationship Between ROS(on), TJand BVOSS FIGURE 2 Yos In-~ When the devices are operating in the linear mode, the behavior is quite different. Figure 3 shows a typical transfer charac· teristics graph (10 as a function of Vas) with Tj as a parameter. The interesting feature of this graph is that above 4.5A, the temperature coefficient (TC) is positive, but below 4.5A, the TC is negative. For this device Rejs= I °C/W, and if a perfect heatsink is assumed such that tc = 25° C then the maximum value for VOS at 4.5A is (8) T· -T VOS = _l__C_ = 27.8 V RejcIO (2) Current Sharing In Parallel MOSFETs FIGURE4 Since this is a 400V device, it is unlikely that the device would be used in the linear mode with such a low value of VOS' Most linear applications would use the device at currents well below 4.5A to exploit the BVOSS capability (400V), and therefore, they would be operating in the negative TC region. Since this is exactly the opposite of the switch mode, the two types of applications will be treated separately. A thermal model for two parallel devices is given in Figure 5A. The normal thermal impedances for junction to case (Rejc)' case to heatsink (Racs) and heatsink to ambient (Resa)' are present as well as the thermal coupling between the devices (Rc)' Three possibilities are indicated: 1. Rc between nodes Tcl and Tc2 represents die mounted on a common case or header. 2. Rc between nodes Tsl and T s2 represents the situation in which separate packaged devices are paralleled on a common heatsink. Current Sharing While Fully Enhanced When VGS is large (6·8 V above Vth), a MOSFET is essentially a positive TC resistor, and the current will divide among the paralleled devices in proportion to their individual ROS(on) as illustrated in Figure 4. As was shown in Figure 2, the TC will be positive, so there is a tendency for a device which has a greater 3. The situation where there is no common coupling between devices, i.e. separate heatsinks, is represented by Rc = "'. 5·17 - (A) T,. TI' Assume' for example, that lOA, 100V devices are being used which have the following characteristics: (B) T,. TI' p. .,- T.1 ..... _~_ Rsa Ta ~ Po Ts2 ... .,- p. Po .,- RiO = 0.12 n R20 = 0.16 n I = 20A Tc = 0.67 %/OC Rejc = 1.67° C/W Recs = 1.00° C/W Resa = 1.47°C/W R,. 7 :- Assume further that the die are mounted on the same header: :- Ra = 1.67° C/W Rd = 2.47°C/W ":' Ta Thermal Models for Two Parallel MOSFETs FIGURE 5 If Equations (5) and (6) are solved for values of Rc from 0 to 100° C/W, the graph shown in Figure 6 results. '02 Ra = Rejc + Recs Rd = Resa TI' .. .00 For analytical purposes, the model in Figure 5A can be simplified as shown in Figure 5B where the values for Ra and Rd depend on the position of Rc. For example, for devices paralleled on a common heatsink, . .. .. 96 IT '-- ...- (3) 92 90 (4) 86 84 From this network, it is possible to calculate the values of RDS(on) for each device (R1 and R2). Given the values for R1 and R2, one can then calculate the values of In (11 and 12), power dissipation (PI and P 2), and the junction temperatures (Tj1 and Tj2). Kassakian (3) has derived the following ex· pressions for this network. 0 • 3456789101112100 Rc(OC/W) FIGURE 6 Notice that when Rcis small the difference between Tj1 and Tj2 is also smali"{about 9°C) even though R20 is one-third larger than RiO! The effect on current sharing is almost non·existent (about 0.3A). As long as Rc is comparable to or smaller than Ra , the difference in junction temperatures should remain small. In practice this should not be difficult to achieve. For multiple die on a common header, this requirement holds very well. For multiple individual packages mounted on a common heatsink, this requirement can be met by having a reasonably heavy common web between devices and by mounting these devices relatively close to each other. Where In the past, many people (this author included) have touted thermally forced current sharing as a major feature of parallel device operation in MOSFETs. Yet thermally forced current sharing is not prominent except in the case of very high voltage devices with large TCs and separate heatsinks. RiO = 25° C value for RnS(on) in device #1 R20 = 25° C value for RnS(on) in device #2 A = Temperature coefficient of resistance. This can vary from 0.5 to 3%/° C depending on the device. = 11 + 12 The most common applications for MOSFET switches involve a load impedance that is large compared to RnS(on). In these applications, the total current (I) through all of the devices is determined by the load. In this case, the total power loss is By itself, this set of equations is not generally useful since the equations are non·linear: i.e. they contain cross products and powers of R1 and R2 (the dependent variables). Using numer· ical methods, this type of equation is usually solved on a computer. However, in most cases this is not necessary as the following example solution demonstrates. (7) where RT = the total on·resistance of the parallel devices. 5·18 In this case, the distribution of current between the devices is not considered; all that matters is the final value for Ror. The fact that some devices will be slightly warmer than others will increase Ror slightly, but this is usually a second order effect. 2. The quiescent operating or "Q" point is ill-defined and varies with temperature. 3. Thermal runaway and subsequent device failure are possible. From these analyses and other work (5), the following general observations can be made: The following discussion will examine these proble.ms and demonstrate a simple cure. For the purposes of this discussion, two parallel devices will be used, but the principles exposed apply to multiple parallel devices. Figure 7 shows the reference model for the discussion. 1. The current sharing between parallel devices is in pro- portion to RnS(on)' 2. When the devices are well coupled thermally, the differ- o ences in Tj are small even when the difference in RnS(on) is substantial. 3. For thermally coupled devices, forced current sharing is insignificant. 4. For high voltage thermally uncoupled devices, some forced sharing can occur, but since this is achieved at the expense of higher Tj and Ror, in most cases thermally uncoupled parallel operation is undesirable. 5. Parallel devices should be mounted on a common heatsink or substrate with a minimum common thermal impedance G 0--1--1 (Rc)' 6. Matching of devices for RnS(on) is usually not necessary unless the range of variation (±2D%) would allow too large a value for Ror. Rather than matching or screening devices s for RnS(on)' it is frequently cheaper and easier to add another device in parallel. 7. If a limit on the maximum value for Ror is desired and Two MOSFETs In Paraliel, Reference Circuit FIGURE 7 matching is acceptable, the matching for RnS(on) should be done at the anticipated average current for each device When two non-identical devices are paralleled, a variety of situations can arise depending on the differences between the devices. Figures 8, 9, and 10 show several possibilities as well as the resulting current imbalance. For the moment, the effect of and the planned value for VGS' 8. To minimize differences in RnS(on) and the final value for Ror, it is important to enhance the devices fully. A V GS oflD to 15 V is sufficient. 9. The relevant issue in paralleling is not current sharing, per se, but rather the junction temperature differences and any additional power losses. If the ATj and APT are small, the asymmetry in the current is irrelevant. Tj changes will be ignored. Figure 8 illustrates the effect of differences in gm' In this case, the current differential increases as I D is increased. 10 r---------------------~_,_, Current Sharing During Linear Operation In the linear mode of operation, the temperature coefficient of ON-resistance is negative. This means that if one device, in a group of parallel devices, is conducting more than its share of current, its temperature will rise. This will further increase this device's share of the total current. This process can lead to thermal runaway and is very similar in nature to the thermal instability present in BJTs. In the case of the MOSFET, the transconductance (gm = aIn/a Vas) is much lower, and the tendency towards instability is correspondingly less. 7 6 10 (A) , ,, ,, , , 4 3 2 , ,, I Thermal regeneration of this type combined with normal device characterization variations can cause three problems: 1. , (11- 12) 5 o 2 4 5 6 7 10 VGS(V) Large differences in current sharing can occur. The current distribution among parallel devices will vary with temperature and, in some cases, with total current (I). Current Difference between Two MOSFETs where gm is the same but Vth Is different FIGURE 8 5-19 - peak value of the difference between 11 and 12 is increased, and the range of V GS over which Ql takes all or most of the current is expanded. In most applications, the effect of differential heating in linear operation is to make the problem worse. One way to minimize the effect of asymmetrical currents is to maximize the thermal coupling between the devices (make Rc as small as possible). This is the same conclusion reached for parallel devices operating as switches! Figure 9 illustrates the effect of a one volt difference in Vth. In this example, all of the current flows through one device until V GS reaches 5 V. At that point, the second device begins picking up some of the current. The current asymmetry remains essentially constant for Vth > 6.5V. The problem here is that if the "Q" point is below 3A, one device will hog nearly all of the current! 10 9 10 9 7 10 (A) 6 4 10 (A) 3 4 3 o 7 4 8 9 10 VGS(V) Current Difference between Two MOSFETs where gm Is the same but Vth dille rent FIGURE 9 o 8 7 10 (A) 4 I I I 10 I A better solution would be to take randomly selected devices and force them to share. This can be done most easily by using small source resistors to provide negative feedback, as shown in Figure 12A. As an added advantage, this will also stabilize the "Q" point. I I I 9 5 Good thermal coupling by itself, however, is not enough to assure good current sharing; it merely reduces the degree of mismatch. For linear applications, some further means to force sharing must be taken. One obvious solution is to match devices. Unfortunately to get really good current sharing, it is necessary to match the entire transfer characteristic. This level of matching would rarely be practical. A useful compromise would be to match the devices at the "Q" point. This is fine in a stable thermal environment, but if the ambient temperature (Ta) varies over a wide range then it is unlikely the devices will remain matched. In any event, matching of devices can be costly and a considerable nuisance in production. 10 I 4 Current Imbalance from Figure 9 when Heating Ellects are taken into account FIGURE 11 Now it is necessary to include the effect of the iunction temperature on the current imbalance. Looking again at Figure 9, notice thatI l > 12. Itis reasonable to assume that Ql will heat up and Q2 will cool down. An approximation of what will occur is shown in Figure 11. From this figure, it can be seen that the I 3 VGS(V) Most practical applications will represent some combination of the two previous examples. A typical combination is shown in Figure 10. In this particular example, the device carrying the greater portion of the current will depend on the "Q" point. 5 2 I I o I I The effect ofthe source resistor can be quantified by examining its effect on the "Q" point of a single device as indicated in Figure 12B. It has been shown (6) that the effective gm (gm') will be -1 -2 Current Difference between Two Mismatched Devices FIGURE 10 Rs+ 1 gm 5-20 (8) 10 To minimize the effect of differences in gm' it is necessary that (9) 8 Typical devices will have values for lIg m in the range of 0.1 to 1.0 ohms. 7 RS=Oj VGG = S.4V 6 10 (A) (A) 5 4 o 2 3 VGS(V) Operating Point Stabilization FIGURE 13 1.667A. From Figure 12 we know that VGS = VGG- InRs (10) so that V GS in this case is 4 V. What we are seeking is a simultaneous solution to Equation (10) and the equation represented by the graph of the transfer characteristic. This is done by graphing Equation (10) (the straight line) on the transfer characteristic graph and by noting the intersection of the graphs. In Figure 13, the (8) intersection representing the "Q" point is at V GS = 5.4 V, and In = 1.2A. This same technique can be applied to parallel devices since stabilization of the "Q" point also stabilizes the current sharing. Using the example of Figure 9, the effect on sharing by adding a 2 ohm resistor in series with each device can be determined. A series of parallel lines are drawn for several different values of VGG. each having a slope corresponding to 2 ohms. Each line establishes a "Q" point with a given value of t.I. The values for t.I corresponding to the different values for. + 10 RS Forced Current Sharing using Source Resistors FIGURE 12 V GG can now be plotted and compared to the values for th~ original example (Figure 9). This is shown in Figure 15 wherein; can be seen that t.Iis reduced from 3.2to 0.5A! Clearly this is an effective means for equalizing the current distribution as well as stabilizing the operating point. The effect of Rs on the "Q" point stability (with fixed V GG) is shown in Figure 13. If the operating point is selected as V GG = V GS = 5.4V and Rs = othen In= 1.2AatT1, butit will rise to In = 2.7Aat T2 -an increase of more than 2:1! By making Rs = 3 ohms (as indicated by the sloping line), the change in In(t.I) when the temperature changes from Tl to T2 is reduced to 0.25A! This is a very great improvement. In this example, gm is approximately 2.5S so that Rs ~ 8/g m . Even if Rs is reduced to 1 n, t. I is still only 0.6A. Source resistors can also improve thermal stability by reducing differences between the transfer characteristics as Tj is varied. This effect can be illustrated by regraphing the example in Figure 13 as a function of V GG rather than V GS' This is done in Figure 16. In effect, the thermal regenerative gain is much lower and the stability greatly enhanced. For those readers not familiar with the graphic technique just used, a few words of explanation may prove helpful. The Note that Figure 16 is also an alternative method for determining t.I between non-identical devices; however, itis usually straight line representing Rs = 3 and V GG = 9V is shown in a graph representing the values of V GS for given values of ID' For example, if In = 1.667 A, the drop across Rs is 5V, viz. 3 x simpler to draw the resistive load lines for R s ' as was done in previous examples (Figures 13 and 14), than to redraw the graph in the form used in Figure 16. 5-21 - 10 The use of source resistors has several advantages: 1. The operating point is stabilized. 2. Excellent current sharing and equalization of power dissipation is achieved. 3. Transconductance differences are minimized so that the small signal gain is nearly the same in each device. 4. Thermal stability is enhanced. 5. The small signal linearity is improved. 10 (A) Q 1 2 8 3 9 10 11 12 13 14 VGsM Rs Load Lines Plolted on the Transfer Characteristic Graph FIGURE 14 Unfortunately, these benefits are not gained without some cost. The use of source resistors has the following disadvantages: 1. Additional components are needed: i.e. the resistors. 2. The large signal dynamic range is reduced by the voltage drop across the resistors, but since this voltage drop is usually small compared to VDS this is not a severe penalty. On the other hand, the source resistors tend to extend the lower limit of the large signal linear region (Figure 16), and this compensates by extending the dynamic range. 3. The voltage gain of the stage is reduced. In the common source configuration, the voltage gain (A) is A=gmRL (11) where RL is the load resistance. RS"'O From Equation (6), the gain will be reduced to A = gmRL 1 + Rsgm when source resistors are used. (12) From the foregoing discussion, the following general obser· vations regarding parallel devices operating in the linear mode can be made: 1. This mode of operation is very different from the switching mode in most respects. 2. To avoid excessive current asymmetry and thermal instability, some positive means must be provided to stabilize the operating point and force current sharing. 3. The simplest means to achieve the above goals is to use small resistors in series with each device's source lead. 4. Good thermal coupling between devices will greatly im· prove thermal stability and current sharing and help to minimize the size of Rs. 5. Matching of devices, while useful and effective, is usually not necessary. Small source resistors are usually a cheaper and simpler solution. The size of the resistors can be reduced by prescreening devices to eliminate those with larger than average characteristic deviations. 6. Multiple die devices will normally (at least at Siliconix) have the die selected from adjacent positions on the same wafer and will be well matched. In addition, the thermal coupling will be very good. The user cannot, however, add individual source resistors because the die are sealed within the case. If the degree ofintrinsic matching in multiple die devices is not adequate, the single die devices can be paralleled using individual source resistors. The Effect of Source Resistors on Current Sharing FIGURE 15 10r--------------------i--i---------, 10CA) The Effect 01 Rs on the Transfer Characteristics over Temperature FIGURE 16 5·22 Current Sharing During Switching Transitions impedances. Using symmetrical layouts is one way to doit. An example of a symmetrical layout for a parallel switch connection (push·pull) with three paralleled devices is gi ven in Figure 18. Many other practical symmetrical When parallel MOSFETs are used as switches, several ques· tions arise concerning device behavior during the switch transitions from OFF to ON and from ON to OFF: layouts are possible. 3. Good layout techniques are vital. The effect of Ls on the switching waveform is shown in Figure 19. Obviously Ls should be made as small as possible. Further examples of good layout technique are given in Figures 20 and 21. 1. What is the current distribution? 2. Can current asymmetries be severe enough to damage a device? 3. Is the switching time affected by current asymmetries? When a MOSFET makes a transition from one state to another, the device must pass through the linear region, if only momen· tarily. This means that much of what has been discussed concerning the linear mode of operation applies to dynamic switching. However, there are some differences: 1. The operating time in the linear region is very short (typically 10 to 100 nsec). 2. Because of the rapid transitions, thermal heating effects are usually negligible. 3. The use of source resistors is unacceptable because of the substantial increase in the effective value of RDS(on)' 4. The external parasitic and intentional resistances, induc· tances, and capacitances must be taken into account. Symmetrical Layout Example FIGURE 18 An equivalent circuit representing two parallel FETs is given in Figure 17. Differences in current during switching can be caused by: 1. Differences in the external circuit elements. 2. Differences in capacitive or inductive device characteristics. 3. Differences in device characteristics during linear operation. VGG The Effect of Common-Source Inductance on Switching FIGURE 19 Differences in package inductance and inter·terminal capaci· tance are amazingly small (~±5%) and usually can be ignored. This is fortunate since without a complex matching procedure, there is little that can be done anyway. GATE DRIVE Equivalent Circuit for Two Parallel MOSFETs During Switching Transitions FIGURE 17 If for example, Q1 and Q2 are identical, but the drive circuit impedances are different, Q1 and Q2 will not turn on simulta· neously. This problem, however, is under the control of the designer. The following steps can be taken to minimize this problem: 1. Minimize the values for R, Lg , Ls ' LD,C p and C s ' 2. There will be practical limits on how small the external impedance can be. When that limit is reached, every effort should be made to equalize the values for the remaining ·'nduclance ( • Noise Pickup • Parasitic Oscillation lnneel Direct To MOSFET Tonnlnal MInimizes Common·Source Inductance Low Impedance Onva For. • Fasl Switching • Mmimlze Noise Pickup • Minimize dV/dl Turn·On Suggested Drive Circuit Layout FIGURE 20 5·23 l1:li Figure 23. If V GS is a linear function of time (a ramp) then the graphs for 11 and 12 become their current switching waveforms as a function of time! The salient feature ofthese waveforms is that even though the two devices have very different threshold voltages, the current spike for Ql is small (about 1. 7A). In most cases, when unmatched devices are paralleled, only relatively small current differentials are observed. A good series of actual oscillographs is given in Reference (5) to illustrate this point. Applications do exist where from 20 to 50 devices are paralleled. In these applications, it is theoretically possible (but relatively unlikely) to generate destructive current spikes. Such spikes can be avoided by prescreening devices to eliminate those devices that are radically different from the median. Differences in device characteristics, on the other hand, can cause differences in current distribution during switching transitions. To illustrate what occurs, the techniques pre· viously used for linear operation can be applied to the example in Figure 9. If a clamped inductive load is assumed, Figure 22 shows the switching waveforms. IfID = 11 + 12 = 12A then the current during switching will assume the value shown in 1 I "( "" . . ' r" TI ~ 153 ( (S4 'MINIMIZE THE AREA 12 High dl/dt Paths In an H-Bridge FIGURE 21A r----------~,~~~"I , ft 10 : --I '1+12 : ,I ,1 1 + 10 (A) 1 , 6 1 , I 1 9 10 vGS(V) Values for Drain Current during Changed Inductive Switching when 11 + 12 is limited to 12A FIGURE 23 TWISTED PAIR, COAX OR STRIPLINE I.e. LOW L CONNECTION The following observations can be made regarding switching in parallel MOSFETs: Low Inductance Connections for High dl/dt Paths FIGURE 21B 1. Careful circuit layout is needed to minimize and equalize parasitic impedances. 2. Minimizing differe\ltial gate impedances will equalize VGS for each device. 3. Except for large numbers of devices, the current spikes during switching transitions will usually be well within the limits of the device capability. 4. If many devices are paralleled, simple prescreening which measures ID at a given value of V GS in the transition region (i.e. not fully enhanced) should be sufficient. This will eliminate the unusually different devices. '" lL I I I I I I I I I I Parasitic Oscillations in MOSFETs Most power MOSFETs presently available are very fast devices with appreciable gain at frequencies up to 300 MHz. This high frequency gain, coupled with the internal and circuit parasitic Clamped Inductive Load Switching Waveforms FIGURE 22 5-24 inductances and capacitances normally present, make it possible for unwanted parasitic oscillations to occur. The fre· quency of oscillation can range from 1 to 300 MHz. VGS The oscillations occur while the device is in the active mode where the transconductance is large. When the device is off or when V GS is large and the device is fully on, oscillations do not occur. This means that in a switching application, the oscilla· tion will occur on a transient basis during the turn·on and turn-off transitions. In an application where the device is biased on to some fixed point in the linear region, the oscilla· tions can be continuous. VOS An example of a parasitic oscillation during a turn-on transition is given in Figure 24. Figure 24A shows the normal drain·to· source (VDS) and gate·to·source (VGS) voltage waveforms when no oscillation is present; Figure 24B shows the same waveforms when an oscillation is present. An expanded portion ofthe oscillation envelope is given in Figure 25. In this case, the oscillation frequency is approximately 85 MHz. Although the oscillation amplitude shown is not very high, voltages of 100V or more are possible at the peak of the envelope. FIGURE 24B The existence of parasitic oscillations can have the following consequences: 1. Gate rupture due to overvoltage. 2. Gate rupture due to overheating of the gate structure. 3. Increased power dissipation in the device. 4. Increased voltage and current stress in associated circuit components. 5. HF to VHF electromagnetic interference (EMI). Expanded Time Base Showing Free Running Parasitic Oscillation FIGURE 25 None of these are normally acceptable, and, in nearly all cases, the parasitic oscillations must be eliminated. Many so called "mysterious" failures in MOSFETs are due to parasitic oscillations. A single device can oscillate by itself. Parallel devices can also oscillate as if they were a single device; this is referred to as a "common mode" oscillation. In addition, paralleled devices can oscillate in a "differential mode." The analysis for each mode is very similar, but the parasitic circuit elements controlling the oscillations are different. Common Mode Oscillation Figure 26 gives a model ofthe internal and external parasitic capacitances and inductances in a typical application. To analyze this circuit for oscillations, a simplified incremental model (Figure 27) can be used. Figure 27 is not exact but will still give useful answers. The following assumptions have been made and are normally valid: 1. LGe» LGi 5. C 1 = Cgse + Cgsi 2. LDe » LDi 6. C2 = Cgde + Cgdi 3. LSe » LSi 7. C3 = Cdse + Cdsi 4. RGe» RGi A more complex model could, of course, be used at the cost of greatly increased computational difficulty. Non-Oscillatmg MOSFET FIGURE 24A 5-25 - In some applications, the model may be further simplified if either Ln or LS is very small. The coefficients of the charac· teristic equations for these cases are .".,..--",/ I I I / ROI / (20) a1 = LGLSC~ (21) a2 = C~(LSRG + LGRn + LsRn) + gm LGLSC2 (22) aa = RnRGC~ + gmC2(LSRG + LGRn + LsRn) + (23) LG(C 1 + C2) + LS(C 1 + C3) a4 = gmRn RGC2 + RG(C 1 + C2) + Rn(C2 + Ca ) + (24) gmLS Equivalent cIrcuit FIGURE 26 LS = 0 L~ RO = LnLG (25) a1 = LnLGC~ (26) a2 = C~(LnRG + LGRn) + gm LnLGC2 (27) a3 = RnRGC~ + gm(LnRG + LGRn)C 2 + (28) LO LG(C 1 + C2) + Ln(C2 + Ca) a4 = gmRn RGC 2 + RG(C 1 + C2) + Rn(C 2 + Ca) (29) Incremental Model FIGURE 27 The practical question which must be answered is: "noes the circuit oscillate or not?" The characteristic equation can an· swer this question. If any of the roots of the polynomial are negative (i.e. lie in the right half-plane or have the term s-a) then the circuit will oscillate. There are several ways this can be determined. The characteristic equation for the incremental model is (7) a1S4 + a2S3 + a3S2 + a4S + 1 = 0 (13) Where a1 = C~L~ (14) a2 = C~[Ra 100nA). The best means for detecting oscillations is to place a scope probe between the gate and source terminals, directly on the device. The scope should havea bandwidth of at least 200 MHz sinceitis very difficult to detect VHF oscillations with an instrument that responds to only a few MHz. A low capacitance probe should be used, and as Circuit for Monitoring Charge Transfer Figure 1 little stray inductance as possible should be introduced. It is Since we are looking at high-frequency parasitic oscillation, it is vital that the circuit use direct pointto-point wiring-a few misplaced nanohenries may upset the results. possible for the measurement process itself to alter the circuit operation and to suppress or induce the osciliatlOn! Prevention of Oscillation in MOSFETs Examining the Conditions for Oscillation From the theoretical and experimental work on this problem, it is clear that preventing parasitic oscillations is not a major problem and can be accomplished by observing the following In Figure 2, the resulting charge-transfer characteristics are divided into three well-defined regions. In region 1, the gate voltage has charged the input capacitor of the power MOSFET to where turn-ON just begins (VT); in region 2, we witness not only the completion of the turn-ON cycle but also the effects of Miller capacitance upon the charge characteristics. In region 3, we see the drain-to-source voltage settling slowly to VSAT followed by a resumption of the gate charging cycle. guidelines: 1. Minimize the parasitic inductances and capacitances. In particular LG' LS' and Cgd should be made as small as possible. Making the parasitic elements smaller raises the resonant frequency. As the frequency is increased, the gain ofthe device will decrease, and the resistive damping present will become more effective. The net result is a reduced likelihood of oscillation. 2. Use small (1-5 ohm) differential resistors in the gate lead of 400 each device. Because of the silicon gate structure of Siliconix devices, most of the needed resistance will already be Z present. RG should, of course, be non-inductive. Carbon composition resistors are particularly good. 3. u; ti . 2Q g ~ (30) r---ir-- Vg1 ~ 100 the oscillation will not appear even though the circuit is potentially unstable. .-~ - - t ~ ~ r-... VGG J Q2;----1- 3 Vg2 I. Q, I'I--~O% 10 vide both RG and increased LG and can be very effective in suppressing oscillations. II I I For the differential mode of oscillation, ferrite beads pro- I V ~ f---' I 1/ 4. Minimize the differential values of LS and Ln. 5. ~ 15 I then ;::: s.!- r- ~ VDS 200 " T, z ~ "~ W If the switch transition time is short compared to 300 ~ Any resonant circuit has a non-zero value of Q. The higher Q is, the slower the oscillation will build up. The time constant (T) will be T=-- I N 15 20 25 A Typical Charge-Transfer Characteristic Figure 2 5-29 - Here we must point out that if we were to parallel power MOSFETs in such a manner as to ensure parasitic oscillation, we would discover a well-defined envelope of oscillation only in the immediate vicinity of the transition between regions 2 and 3. This welldefined envelope is shown in Figure 3 where we should carefully note its position on the charge curve. The gate voltage has passed threshold (VT), and the drain-to-source voltage has decayed to a point approaching but not having reached VSAT Oscillation found anywhere else is caused by other phenomena, perhaps excessive wiring inductance in the test circuit. Causes of Oscillation Oscillation results from a resonance induced by the combination of parasitic capacitive and inductive elements including, in particular, the loop inductance between discrete power transistors coupled with the characteristically high gain of the power MOSFETs. Since the interelectrode capacitances of a power MOSFET are voltage dependent, behaving as we see in Figure 5, this parasitic oscillation becomes conditional upon the applied drain voltage. In Section 3.2 we resolved that the prime cause ofthe extended Miller effect on the gate charge as well as the slow settling of the drain-to-source voltage to VSAT after turn-ON, was the result of a many-orderof-magnitude change in the gate-to-drain capacitance, Cgd as shown in § 3.2-Figure 6 (and again in Figure 6). The meteoric rise in gate-to-drain capacitance only begins as the power MOSFET gate charge enters into the transitional area between regions 2 and3. To understand the circumstances resulting in oscillation where it appears on the charge-transfer characteristic, we need to closely examine what changes take place in the power MOSFET. 1000 Cg• ......... "'c•• ' "" Envelope of Parasitic OSCillation Situated within Region 2 of the Charge Characteristics Figure 3 Cg. By expanding our oscilloscope time base, we can arrive at a close approximation of the frequency of oscillation. The result is given in Figure 4 for a pair of parallel-coupled Siliconix VN4000A MOSPOWER FETs. 10 01 10 10 100 Vas - VOLTS IV) The Interelectrode Capacitance of a VN4000A MOSPOWER FET as a Function of Drain Voltage Figure 5 -,- -I- f'~ 1000 \ VN4000A IRF33 VT; and c) Vgs»VT. Upper Traces: Vsupply = 10 V/div; Middle Traces: Vdraln 10 V/dlv; Lower Traces: Vgs 2V/div Figure 2 = 5-34 = The interaction of the parasitic bipolar transistor by dV/dt breakdown initially seemed to be a likely cause of the oscillation. This suspicion was strengthened by the anomalous turn-off behavior in which the MOSFET turns back on for an extended period. Interaction of the parasitic bipolar transistor requires that a source of current be injected across the baseemitter junction to turn it on. This situation can occur when a fast rising voltage is applied to the drain! collector of the transistor that causes a rapid expansion of the base-collector depletion region. The charge displaced from the base depletion region moves towards the source contact causing a resistive voltage drop in the base region. If this voltage drop exceeds approximately 0.6 volts, the emitter base junction becomes forward biased and the bipolar transistor turns on, shunting the cut-off MOSFET. Oscillation of the Power MOSFET when a 0.1 J-LF Capacitor is Connected -3 Inches from the Gate of the MOSFET Figure 3 For the above type of mechanism to be responsible, the oscillation can only exist in a large signal state since a high dV/dt at the drain is required to activate the parasitic bipolar transistor. An experiment to test this hypothesis demonstrated that the parasitic transistor is not involved but that the oscillation is due to a small-signal instability. The experiment involved removing the exciting transient introduced by the rising edge of the input pulse by shunting the gate of the MOSFET with a 0.1 JLF capacitor. This reduced the tendency of the MOSFET to oscillate as might be expected by AC grounding the MOSFET gate. However, when the capacitor is decoupled from the gate by moving it 3 inches towards the pulse generator, the circuit oscillated readily. The slowly increasing oscillation amplitude seen in Figure 3 started at near zero amplitude, and this indicated that the oscillation is indeed due to a small-signal instability. Thus, a small-signal analysis should reveal the conditions for oscillation for the power MOSFET. CGS RD I LD Small Signal AC Model of the Power MOSFET Inverter Circuit Shown in Figure 1 Figure 4 Writing KVL around the three loops and KCL at the three nodes for the circuit shown in Figure 4 yields ig Lg -ics Lcs =-Ig Rg + Vgs (1) id - ics Lcs = - Id Rd + Vds (2) Vgd + Vds = Vgs (3) Cgs Vgs +Cgd Vgd =-Ig (4) Cds Vds - Cgd Vgd = - Ig - V gsgm (5) Routh-Hurwitz Analysis Having established that the oscillation is due to a small-signal instability, the simple inverter circuit, shown in Figure 1, is modeled using the standard small-signal AC model as seen in Figure 4. A set of state equations can be written to describe this circuit, from which the characteristic polynomial can be found. The location of the roots of the characteristic polynomial in the complex frequency plane then will determine whether the circuit is stable. Ig +Id +Ics = 0 (6) These equations can be cast into a matrix state equation: 5·35 - (Lg + Lcs) Rd Lcs Rg Leff2 Leff2 [~:} Vds Lcs Rd Leff2 Cgd - Ceff2 Cgs + Cgd Ceff2 (Ld + Lcs) Rg Leff2 Cgd + Cds Lcs - Leff2 Lg + Lcs Ld + Lcs Leff2 Lcs - Leff2 Cgdgm - Ceff2 Ceff2 Cgd - Ceff2 (C gs + Lcs Ld + Lcs Lg Ceff2 == Cds Cgs (9) The characteristic equation is the determinant of the matrix A- sl where A is the state equation matrix written above. The characteristic polynomial is then P(s} = aos4 + als 3 + a2s2 + a3s + ~ (10) (11) + Lcs) Rg + (Lg + Lcs) Rrl] +Cgdgm Leff2 (12) Rrl Rg + Cgdgm [(Ld + Lcs) Rg + (Lg + Lcs) Rd] + (Cgs + Cgd) Lg + (Cgd' + Cds) Ld + (Cgs + Cds) Lcs a2 = Ceff2 0 01 = al (13) 02 a3 = Cgdgm Rrl Rg + (Cgs + Cgd) Rg + (Cgd + Cds) Rd + gm Lcs (14) ~=1 (15) Vds Although there is no analytic solution for the roots of a fourth order polynomial, stability only requires that all the poles lie in the left half s-plane. The Routh-Hurwitz criterion states that a necessary and sufficient condition for all of the roots of an nth order equation to lie in the left half of the s-plane is that all of the Hurwitz deteI;IIlinants, Ok (k= 1,2, ... n), must be positive. The Hurwitz determinants for a fourth order polynomial are given by where al = Ceff2 [(Ld + Cgd) gm (7) form a loop, and the inductors form a cutset. Kirchhoff's Voltage Law constrains one of the capacitor voltages to be the sum of the other two; hence, the three capacitors contribute only two state variables. Likewise, although there are three inductances, there are only two independent state variables because Kirchhoff's Current Law constrains the current in one of the inductors to be the sum of the other two. Thus, the six energy storage elements have only four independent state variables resulting in a fourth orde" characteristic polynomial. (8) + Cds Cgd + Cgd Cgs ~~ 0 Ceff2 where Leff2 and Ceff2 are defined as Leff2 == Ld Lg Leff2 = 03 = The order of the characteristic polynomial is determined by the number of energy storage elements which contribute a state variable. Note that although there are a total of six energy storage elements, the characteristic polynomial is only fourth order. This is because the three capacitors, C gs , Cds, and Cgd, 03 = 5·36 Ialao (16) a31 a2 al a3 ao a2 0 al al ao 0 0 a3 a2 al ao (17) 0 (18) ~ a3 0 ~ a3 a2 0 0 0 ~ = ~03 (19) To simplify the evaluation of the roots of the characteristic polynomial, it would be desirable to reduce the order of the polynomial by setting some of the capacitors or inductors to zero. Unfortunately, the removal of one inductor and one capacitor will not reduce the order of the polynomial because the number of independent state variables is not decreased. However, the algebra in solving these equations is still simplified enormously if some of the circuit elements can be set to zero, and thus, Rg and Lcs are set to zero. Setting Rg and Lcs to zero represents a typical situation since these quantities are usually very small (Rg«wLg and Lcs«Ld). By inspection, D1 is always a positive quantity since all of the component values are positive. An algebraic evaluation of D2 reveals that when Lcs is zero, D2 is always positive. Further, since D4= a4D3, and a4= I, the circuit's stability is indicated by the sign of the third Hurwitz determinant, D3. The algebraic expression for D3 when Lcs= Rg= 0 is D3 = { (Cgd + Cds) Rd [Cgd gm Lg Rd+ (Cgs + Cgd) Lg + (Cgd + Cds) Ld 1 -C eff2 Lg Rd - Cgd gm Ld Lg} (C eff2 Lg Rd + Cgd gm Ld Lg) (20) - Ceff2 (Cgd + Cds)2 Ld Lg RJ This equation is second order in all variables except Lg which fortunately is one of the variables which can control the oscillation. Solving the above equation for Lg with the constraint that D3 > 0 yields Lg<-------------------------------------------------(Ceff2 Rd + Cgd gm Ld) (gm Ld - Cgd gm R~ - Cds gm RJ - Cgd Rd) (21) for (22) Note that when the equation on the bottom is negative, the sign of the inequality is changed. Then the condition for stability is always satisfied because Lg is a positive quantity. uations of equations (21) and (22) for a conventional MOSFET show that these constraints are both easily satisfied. An examination of equation (23) reveals that the critical value of Lg is roughly inversely proportional to the gate area. Note that the capacitances and transconductance scale proportional to the area while both the on resistance and the load resistance is inversely related to the area. Substituting these dependencies into equation (23) shows that the maximum gate inductance for which the circuit will be stable decreases with increasing device size. Thus, as MOSFETs grow larger in size, they have a greater oscillation tendency. For a typical circuit, the load inductance terms dominate in equations (21) and (22). The condition for stability as given by equation (21) can then be reduced to Lg < + Cds)2 Rd --='------ (Cgd (23) Cgd gm For the inverter circuit studied here, this condition is a relatively severe constraint. Typical numerical eval- 5·37 - Computer Simulation Using SPICE ........UUD8/S5 ••••- •• SPICE 2G I5A (2SNOVB2) .. ······11 32 os····· OLe lESS TF.AN CRlTICAL 0.. •• INPUT LISTING T£JlPERA""'l'"RE = 2., OCC DEG C 0LG .. ••• ..03 ••••••••••• ION .. ••• .. ··"····························· ............ . The analytic solution in the previous section has limitations because of the assumptions that Rg= 0 and Lcs= 0 and because of the general complexity of D3. More significantly, the analysis does not show how close the circuit is to oscillation but only if the circuit is or is not in oscillation. LD CCS CCD 2~ 200P 200P 1000P 20U VG 40 ACI aJS 80 82 20 RD ~o ? Gil eo 66?{;e-C2 8708e+-05 '1 SC3e-C2 II 9S0e+Oo e 6-;.~-C2 12::2e+0~ 9 7G3e 02 14ele+0:; l1CZe-Cl o727e+05 1 22Ce (,.1 -I CCOe+05 I 344e el 6296e+CO ,. 738e+CC 98S2e+:::: 13Z6c+CI 19S4e...Cl :3 156e+Cl o4531e+Cl 3246e+Cl 2114e+Cl I riSGeH'l 1215e+Cl I CICe+C) B e97e+CC ,. 6B3e+C:' 6 BIBe+C:: 632Ce+C: 5843e+:::r. 5452e+CC 5128e+CC 485-4e+CC 462Ie+CC 4 .;20e +CC 4 24!ie+OO 1 C28e+OS 1 057e+03 I 087e+05 .1I7e+05 J 14ge+05 1 lele+05 • 214e+O-3 J 246e+05 .2:!Se+D5 1.320e+05 1,35'e-t09 1..39!5e+-D5 1.434e+0:3 1,4?4e"05 UIiUle+O!': UIi58e+D5 • .102e+05 Edu..ed. fJ'om the SPICE program Ol...tput. 1 44'5e-CI I 523e-C 1 1 572e-Cl 1 eS.;e-Cl I 5ti~e-Cl 157cl;-Cl I ~Se-C 1 152':e-CI 14'1iuc-Cl 146ge-C1 1444e C) I 42~e-CI 14C5e-Cl 1 SBle-Ol 1.5!:c-CI 1 S73e CI I S6ce-C 1 Edlted from the SPlCEproU&D o\.t.p\.t. SPICE Simulation of the Inverter Circuit's Loop Gain to Show the Effects of Gate Resistance (Note That the Gain Is Less than Unity at the Frequency Where the Phase is Zero, and Hence the Circuit is Stable) Figure 9 SPICE Simulation of the Inverter Circuit to Show the Effects of Common Source Inductance or the Loop Gain (Note That the Maximum Loop Gain Is Decreased (0.159) Which Decreases the Tendency to Oscillate) Figure 10 5·40 output capacitance and then returned to the inductor with the opposite current polarity. Neglecting the nonlinearity of the output capacitance and the damping of the output load resistance, the time for 1/2 cycle is Turn-off Behavior The turn-off behavior of the power MOSFET is shown in Figure 11. Initially, the gate voltage is high and the MOSFET is fully turned on. When the gate voltage falls, the drain voltage rises quickly and then abruptly drops to the "on-voltage," where it remains for several microseconds before ringing and settling to the supply voltage. t = 7T-v'LC (24) After this time, the parasitic diode is forward biased and the voltage across the inductor is If the damping losses are neglected, then Id = VDD/RL (26) and VL = 2VDD + VD- fwd (27) The drain voltage remains near zero during the time the diode is conducting. The current through the diode is dictated by the L-R circuit and is Id = 2VDD a) + VD-fwd (l-e- tR / L) _ VDD (28) R R The time at which the diode current is zero is [2VDD ton = (L/R) In + VD-fWd] LVDD + VD- fwd (29) For a reasonably large supply voltage, VDD» 0.7 volts, the above equation can be expanded in a Taylor series to give ton =L- [ 1 R VD-fWd] In 2 2VDD (30) Neglecting the reverse recovery of the diode for the _ moment, the drain voltage rises at this time and then the drain voltage rings and settles to the supply voltage. b) Oscillograph of the Turn-off Behavior of the Power MOSFET Inverter; a) Upper Trace: Vo = 10 V/dlv; Lower Trace: Vgs = 5 V/div; b) Upper Trace: Vo = 10 V/div; Lower Trace: 10 = 0.5 A/div Figure 11 Second Order Effects A comparison of experimental data with the calculated results of equation (30) reveals a large discrepancy in the "on-time." Also, the oscillograph of Figure 11 shows that the power MOSFET appears to turn on a third time. These discrepancies were found to be due to the effect of the reverse recovery of the diode (see Figure 12). Instead of turning off when the forward diode current crosses zero, the diode continues to conduct in the reverse direction before The sequence of events is shown in Figure 12. Before the MOSFET is turned off, energy has been stored in the inductor. When the device is turned off, the output capacitance of the power MOSFET and the inductor cycle for slightly more than one half cycle in which the inductive energy is dumped into the 5-41 the drain voltage begins to rise. Consequently, the total tum-on time expressed by equation (30) must be modified to include the reverse recovery time trr: ton"" -L [ 1 R VD-fWd] In 2 2VDD + termine if the circuit was stable, a set of expressions was derived that places a constraint on the maximum value of gate inductance for which the circuit will be stable. From this expression it may be seen that as the area of a MOSFET increases, the maximum allowable gate inductance decreases, which may explain why conventional MOSFETs do not have as great a tendency to oscillate as power MOSFETs. (31) trr Since the inductor once again has a downward current direction after the diode's reverse recovery, the situation is the same as when the MOSFET first turned off but with a lower initial current level, and thus the cycle repeats again. Experiments and computer simulations of the power MOSFET inverter circuit reveal that the addition of small amounts of gate resistance (Rg>woscLg) or common source inductance effectively stops the oscillation tendency while not severely degrading the performance of the MOSFET. Unfortunately, there appears to be no way of reducing the tendency of the power MOSFET to oscillate without degrading its performance. n I \ I \ z " I I I ~ Voo \ \ 1~:J---t====-C:=-=J-t::=-==j-I- The anomalous turn-off behavior was found not to be caused by dVldt breakdown of the parasitic bipolar transistor. Instead, it is caused by the intrinsic diode, clamping the output voltage to ground. The reverse recovery of the diode both extends the time during which the MOSFET is apparently on and causes the power MOSFET to seemingly tum "on" repeatedly as the output voltage settled to its final value. - - EFFECTS OF TRR ---~ T1ME- -TRR-~ The tum-off behavior will not be ob~erved in a typical power MOSFET circuit because when the MOSFET is used to drive an inductive load, the drain is usually clamped to the positive supply voltage. However, when the power MOSFET is used to drive an unclamped inductive load, the parasitic diode can extend the time required for the drain voltage to settle at its final value. Diagram of the Power MOSFET's Turn-off Behavior Showing the Effects of trr Figure 12 Another discrepancy is the dependency of the turnoff time on the supply voltage. From equation (31) the time is independent of the supply voltage when the supply voltage is much greater than 0.7 volts. However, when the peak voltage during turn-off is near the breakdown voltage, the MOSFET will conduct and dissipate some of the stored energy, resulting in a decrease in the tum-on time. In our experiment, even with a low supply voltage of ten volts and a load inductance of 17 ILH, the peak voltage sometimes exceeded 450 volts and resulted in a decreased turnon time with increasing supply voltage. References [1] D.K. Sharma and K.V. Ramamathan, "Modeling Thermal Effects on MOS IV Characteristics," IEEE Electron Dev. Let., Vol. EDL-4, p. 362, Oct. 1983. [2] Yasuhisa Omura, Eiichi Sano, and Kuniki Ohwada, "A Negative Drain Conductance Property in a Super-Thin Film Buried Channel MOSFET on a Buried Insulator," IEEE TIan. E1ec. Dev., Vol. ED-3~, Jan. 1983. Conclusions It has been found experimentally that the power MOSFET oscillates due to a small signal instability. The small signal instability was confirmed by analyzing a small signal model of a power MOSFET inverter circuit both analytically and with computer simulations. Using the Routh-Hurwitz criterion to de- [3] D.S. Kuo, C. Hu, and M.H. Chi, "dV/dt Breakdown in Power MOSFETs," IEEE Electron Dev. Let., Vol. EDL-4, p. 1, Jan. 1983. 542 5.3.2 Thermally Forced Current Sharing in Paralleled Power MOSFETs Abstract A static thermal model for a pair of paralleled devices is proposed and analyzed. The model includes the parametric variability necessary to represent both chip and package paralleled devices, and to represent various degrees of thermal coupling between the two devices. Analysis of the model produces a set of coupled non-linear equations which are solved numerically using an iterative algorithm. The drain currents and "junction" temperatures of both devices are then determined for a variety of conditions. A thermal model is proposed and analyzed to determine the extent of thermal forcing of current sharing in paralleled power MOSFETs. Both package paralleled and chip paralleled devices are examined. It is shown that the effects of thermal forcing on the current distribution among paralleled devices are relatively insignificant. The most reliable operation of paralleled devices is achieved if they are tightly coupled thermally. Introduction The drain-source resistance of a power MOSFET is dominated by the bulk spreading resistance of the drain region, and not the inverted channel resistance. The temperature dependence of this resistance is caused principally by the variation of the drift mobility. As a consequence, the resistance exhibits a positive temperature coefficient whose value is dependent upon conductivity type, but relatively independent of device construction. The TCR itself does exhibit some temperature dependence, which is more pronounced for high voltage devices. For n-channel, 400 V devices this coefficient varies from approximately 0.6%/oC at 25°C, to a value of approximately 1.2%rC at 150°C. For purposes of this analysis, the non-linear behavior of the TCR is not considered, and the high telnperature value is assumed for all devices. The drain-source resistance as a function of temperature, Rds(T), is thus The popularity of the power MOSFET arises from its low drive requirement, fast switching speed, and the relative ease with which it may be paralIeled to achieve higher power ratings. Since manufacturing yields are presently such that single devices with ratings above approximately 5 k VA are not economicalIy justifiable, it is this latter advantage which permits employing the device in applications above a few kW. Paralleling can be done by the manufacturer at the chip level, or by the user at the packaged device level. This paper considers the influence of the temperature dependence of the drain-source resistance on static current sharing among paralleled devices. The greatest effect of thermal forcing is achieved when the paralleled devices are thermally isolated from one another, thus permitting them to equilibrate at different temperatures. In practical applications complete isolation can only be approximated, in part due to the physical constraints on equipment size and component arrangement, and in part due to the conflicting requirements imposed by rhe need to eliminate electrical parasitics. » RdsCT) = RdsoCI+ACTj-Ta (1) where Rdso is the drain-source resistance measured at Ta , and A is the TCR. 5-43 - Because the current distribution among paralleled devices is governed by their relative drain-source resistances, it is often believed that the positive temperature coefficient of resistance forces current sharing among paralleled devices. [1,2,3] In order to determine the extent to which such forced sharing occurs, it is necessary to assume a thermal system and solve the resulting set of non-linear equations for the individual drain-source resistances. tions. Therefore the sources PI and P2 in Fig. I each depend on both Tjl and Tj2. The Thermal System Electrical Connection of Paralleled Devices Figure 2 Figure I shows the static thermal model for two devices in parallel. The resistances Rjc, Rcs , and Rsa represent the "junction" to case, case to sink, and sink to ambient thermal resistances, respectively. (Although there is no heat generating junction in a MOSFET, the term is used here generically to represent the heat source.) The voltages Tj, Tc , T s , and Ta , represent the junction, case, sink, and ambient temperatures, respectively. The resistance Rc represents the thermal coupling between devices. For mUltiple chips on a common header, the coupling occurs between the case nodes in the model. For two packaged devices on a single heat sink, the coupling occurs between the sink nodes in the model. The current sources PI and P2 represent the rate at which thermal energy is being dissipated in devices I and 2, respectively. The input parameters for this problem are the net drain current, I, and the reference drain-source resistances Rdsol and Rds02. The variables Tjl, Tj2, II, 12, PI: and P2 are then determined. For symbolic simplicity, the subscripts "ds" are not carried forward in the following analysis and discussion. The operating values of the drain-source resistance are referred to as RI and R2, while the initial, or reference, values are Rio and R20. Also, literal subscripts are used for thermal resistances, while numerical subscripts are reserved for electrical resistances. The model of Fig. I can be generalized slightly by recognizing that the point of thermal coupling can be moved by varying the relative values of Rjc, Rcs , and Rsa. Therefore, in the equations that follow, Rjc, Rcs and Rsa have been combined into an equivalent resis: tance Rct which represents the thermal circuit between the point of coupling and ambient, and an equivalent resistance Ra which represents the thermal resistance between the heat source and the point of coupling. This more general thermal model, in which chip paralleled or package paralleled devices may be represented by simply changing the relative values of Ra and Rd, is shown in Fig. 3. Ric Rc - -'\NV-Res T., Rc - -¥I\r- Rsa Ts2 Rsa T" Static Thermal Model for Two Paralleled Devices Figure 1 P2 The electrical connection of the devices is shown in Fig. 2, where Vds is the on-state drain-source voltage, and I is the net drain current. The non-linearity in this system arises because the distribution of the net current, I, between the devices depends upon the relative values of Rdsl and Rds2, as do the relative dissipa- Rc Generalized Static Thermal Model Figure 3 544 The model of Fig. 3 may now be analyzed. In terms 'of the temperatures of the coupled nodes, Tel and Te2, the junction temperatures are Tjl = PIRa + Tel (2a) Tj2 = P2Ra + Te2 (2b) The electrical dissipation in each device, as a function of net drain current is (3a) Te2 = [P2(Rc + Rd) + PIRd] [(Rc/Rd) + 2] + Ta (3b) (4a) P2 = [I(RIII R2)]2/R2 (4b) As indicated earlier, the on-state drain-source resistances are The temperatures of the coupled nodes, relative to O°C, may now be determined in terms of PI and P2, [PI(R c + Rd) + P2Rd] T I - --:-----e [(Rc/Rd) + 2] + Ta PI = [I(RIIIR2)]2/Rl RI = Rlo(1 + ATjl) (Sa) R2 = R20(1 + ATj2) (Sb) Finally, (2), (3), (4), and (S) can be combined to yield R I and R2 as functions of the net drain current, I, and the thermal environment, R, A[R{~+ R'~ ~,+ 1)+ R'} + R] R-R{, "R, R, A [ f~+R')( ~'+ ')+ R'} + R2 RI = RIo 2- 20 { ]+ hi (R] + R2) 2 R] + (R] + R2)2 d ~+2 Rd Rd Rc+ 2 Rd Rd R + 2 _c Rd ]} ]} (6a) (6b) Results For a given set of input parameters, (6a) and (6b) are solved numerically using an iterative algorithm. Both T0220 and T03 packages were considered for individually packaged devices in parallel, and for individual chips in parallel a Rcs value of one-half that for the package was assumed. This latter is a convenient assumption since it is satisfied automatically as Rc is "moved up" toward the "junction" in the model of Fig. 3. Case 2: (400 V, 3.S A, T0220) Rjc = 1.6rC/W Rcs = I.OO°C/W Rsa = 1.47°C/W RIo = 0.7S ohm R20 = 1.00 ohm I=7A A= .011 Although a wide variety of different conditions were studied, the essential conclusions of this work can be demonstrated by the results of a few specific cases. In each case it is assumed that the devices are paralleled at the chip level, Le., Ra = Rjc. The parameters for these cases are: Case 3: (400 V, 11 A, T03) Rjc = .83°C/W Rcs = .20°C/W Rsa = .60°C/W RIo = 0.2 ohm R20 = 0.3 ohm I = 22 A A= .012 Case I: (100 V, 10 A, T0220) Rjc = 1.67°C/W Res = I.OO°C/W Rsa = 1.47°C/W Rio = 0.12 ohm R20 = 0.16 ohm I = 20 A A= .0067 Equations (2)-(6) were solved for Rc varying from 0 to 100°C/W. The effect of forced current sharing is maximized for large Rc, which permits the necessary temperature difference between devices. This result is, of course, independent of the relative values of Ra and Rd. 545 - T('c) TI('c) '6. '05 '50 __----------t ~T" ------------r ~T,2 95 90 '20 85 80'--------L..-----.....J,O-~ ~ RcrcJw) '0 (a) (a) I(A) I(A) :8i!~~;:',: L - - - - - - - ' - - - - - - - L1'o--? '2 11 '0 ~RcfcJw) 12 '--------L..------L,o-~ ~ (b) (b) Variation of "Junction" Temperature (a), and Drain Current (b) with Thermal Coupling - Case 1 Figure 4 Variation of "Junction" Temperature (a), and Drain Current (b) with Thermal Coupling - Case 3 Figure 6 '20 Figures 4, 5, and 6 show the variations of "junction" temperature and drain current with thermal coupling. The results show the effect of forced current sharing to be practically non-existent. In fact, if the Tj's are constrained to be equal (by setting Ra = 0, Rd = Rjc + Rcs + Rsa , and Rc = 0), the drain currents differ by less than 5% from their values for the case of total thermal isolation (approximated by Rc = 100°C!W). Even though current sharing is not enhanced by thermal isolation, the figures show that the "junction" temperatures can be substantially different under such conditions. Reliability of the hot device is thus compromised with no apparent benefit. 110 '05 ~T,2 'OO'-------+------:l'O:--~ 100 II' " RcC°clw) (a) I(A) 42:~,------+-~~ ~I, t L.._------------T ~ ':0 <---" • 1Jo II Rcf'cIw) (b) Variation of "Junction" Temperature (a), and Drain Current (b) with Thermal Coupling - Case 2 Figure 5 546 Conclusions References Since the continuous drain current specification for a power MOSFET is a reflection of the maximum junction temperature limit, even though II in Figs. 4(b), 5(b), and 6(b) exceed this specification the device is quite happy as long as Tj < Tjmax. One is therefore led to the conclusion that forced current sharing is an illusion, and furthermore, that devices to be paralleled need not even be carefully matched for Rdso. Also, it is clear from the analysis that paralleling can be used to its best advantage if chips are paralleled by the manufacturer using techniques which result in the minimum value of Rc. [1] HEXFET Databook, International Rectifier Corporation, 1981, p. 20. [2] Oxner, E.S., Power FETs and Their Applications, Prentice-Hall Inc., N.J., 1982, p. 8. [3] MOSPOWER FET Design Catalog, Siliconix, 1982, p. 6-4. 5·47 5.3.3 An Analysis and Experimental Verification of Parasitic Oscillations in Paralleled Power MOSFETs © 1984 IEEE. To be published in IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-31, No. 7, July 1984. This appears here, with pennission of the IEEE. Abstract An analysis of the small signal dynamic model of the power MOSFET is presented which predicts the existence of high frequency parasitic oscillations when these devices are electrically paralleled. It is shown that the existence of these oscillations is a strong function of the small signal transfer admittance, gm, and the differential mode drain, gate and source resistances. The sensitivity of the oscillations to these parameters is determined. Experimental data verifying the qualitative aspects of the analytical results is presented. It is concluded that the problem is potentially most severe for devices which are paralleled by the manufacturer at the chip level. A practical solution to the problem is the introduction of differential mode gate resistance, either as lumped components, or by the use of polysilicon overlays. and have had observed amplitudes exceeding the gatesource breakdown voltage. The existence of the oscillation is a strong function of the gate drive source resistance, but for reasons to be shown, this is believed to be due to the extended duration of the saturation region transition for larger drive resistance. It will also be shown that, given a saturation region residence of sufficient duration to support an oscillation, the inception of this oscillation is a function of only the differential components of the gate and drain resistance, and the parasitic drain and source inductances. An earlier papert: 4] has shown the theoretical effect of gate and drain impedances on the parasitic phenomenon. This paper extends the previous analysis to include the effect of source impedance, and verifies the theoretical results experimentally. Introduction Anecdotal user reports have indicated "mysterious" failures of paralleled power MOSFETs. At the same time, the appearance of oscillations during the switching transitions of such paralleled devices has been reported in the literatureJi,2,3] The understanding of this behavior is of importance not only for reliably paralleling packaged devices, but also for successfully fabricating large devices using paralleled chips. In this latter case, since the user has fewer remedial options available (because of the lack of multiple gate access), the responsibility rests with the manufacturer to assure that the device is stable under all operating conditions. The Dynamic Model Figure 1 shows two electrically paralleled power MOSFETs, Ql and Q2. It is assumed that these devices are identical, and that the layout of their interconnection is symmetrical. Since oscillations occur only when the devices are in their active (saturation) region, it is the incremental model of the circuit of Fig. 1 operating in this region which is important. This model is shown in Fig. 2, which also includes parasitic elements necessary to the creation of an oscillatory system. The inductance, LG, and resistance, RG, represent the parasitic impedance between the common drive source connection and the gates of the two devices. The inductances LD and LS represent the parasitic drain and source impedances, respectively. The resistor RD represents the Phenomenologically, the oscillations occur at frequencies between 50 and 250 MHz, are observable at both the gate and drain tenninals of either device, 5·48 incremental drain-source resistance, which is primarily the resistance of the drift region of the drain. Because of the assumed symmetry of the problem, the parasitic elements are disposed symmetrically between the two devices. The absence of parasitic elements in series with RS and RL is justified below. The same is true of any parasitic elements which might have been included in these branches in the model of Fig. 2. LO Incremental Model, Including Parasitic Elements lor Saturation Region Operation 01 the Paralleled Devices of Figure 1 Figure 2 A Pair 01 Electrically Paralleled MOSFETs Figure 1 The differential mode circuit model of Fig. 3 may now be analyzed to determine its characteristic polynomial. However, rather than confront this rather complicated analysis, two separate situations are considered. The first, shown in Fig. 4(a), assumes no parasitic source inductance, and the second, shown in Fig. 4(b), assumes no parasitic drain inductance. In both cases the effects of gate resistance and parasitic gate inductance are determined. In this way it is possible to gain some insight to the oscillatory behavior as a function of the parasitic elements. The results of the detailed analysis of the effects of drain resistance is presented only for the case LD = O. It is believed that this situation will be more commonly encountered in practice because the physical location of the drain contact (chip substrate) results in very low differential drain inductance (compared to the corresponding differential source inductance) when devices are paralleled. For example, the heat sink will frequently be the common drain connection for T03 or T0220 packages. This produces an electrostatic geometry exhibiting a low inductance. Because of the symmetry and linearity of Fig. 2, the problem may be transformed into differential and common mode coordinates and the method of half circuits used to obtain the relevant characteristic equations. Establishing the plane of symmetry and opening all circuit branches cutting this plane quickly establishes the fact that, to the extent that a single device operates stably, the common mode response of the model cannot include oscillatory behavior. Essentially, the two devices are decoupled in the common mode. Thus the oscillations must be a result of the differential mode circuit. The differential mode circuit may be derived by recognizing that all nodes on the plane of symmetry are at incremental ground potential. The resulting model is shown in Fig. 3. It is now clear that since RS and RL are common mode elements that do not appear in the differential mode circuit, they will not have any effect on the circuit's unstable behavior. LG C, v, + RG RO RG Lo LO l1li Lo C, RO c, C, RL LS Differential Mode Circuit for the Model of Figure 2 Figure 3 5-49 + V2 • (b) (a) Oifferential Mode Circuits for the Model of Figure 2 Assuming: (a) LS Figure 4 = 0, (b) LO = 0 The differential mode circuit model of Fig. 4(a) is analyzed to determine its characteristic polynomial, which is (la) S4(LDLGC~) + S3(RGLDCe2+gmLDLGC2) + S2(LG (Cl + C2) + LD(C2 + C3) + gmRGLDC2) + S (RG(CI + C2» + 1 = 0 where C~ = Cl C2 + C2C3 + C3Cl A similar analysis of Fig. 4(b) yields (lb) S4 (LGLSC~) + S3 «RL)eC2 + gmLSLGC2) + S2(LG (Cl + C2) + LS (CI + C3) + gm (RL)eC2 + RGRDC~ + S (RG(CI + C2) + RD (Cl + C3) + gm (LS + RGRDC2» + 1 = 0 where (RL)e = RDLS + RGLS + RDLG of (la) is plotted in Fig. 5 as a function of gm for several combinations of LD and LG. These polynomials may now be evaluated for the existence of right half plane zeros by use of the Routh-Hurwitz criterion. '00 Theoretical Results Characteristics typical of a 100 V, 10 A power MOSPET were selected for use in evaluating (1). These characteristics are: CI = 700 pF C2 = 100 pF C3 = 300 pF The Routh-Hurwitz criterion was then applied for values of gm between 0.1 and 10 mhos, parasitic inductances between .05 and 50 nH, and parasitic gate resistances between .01 and 100 ohms. It was felt that the selected range of parasitic inductance encompassed both wiring inductance for package paralleled devices, and bond wire inductance for chip paralleled devices. 0"0"'".'---'0'-::2--:':0.:--7:,0:---:2=-0--:''::-0--;'::00~2o.0 gm(S) If the drain resistance, RD, is assumed to be zero, Minimum Value of RG Necessary to Assure Stability of the Model of Figure 4(a) with RO 0, as a Function of gm' for Various Values of LO and LG: (a) LO = 5 nH, LG = 5 nH (b) LO 20 nH, LG 5 nH (c) LO 5 nH, LG 20 nH (d) LO = 20 nH, LG = 20 nH Figure 5 it was found that for any combination of LD, LG, and gm, some value of RG could be found below which (la) possesses a pair of rhp zeros. This minimum value of RG necessary to assure no rhp zeros Figure 6 shows the results of solving (lb) (non-zero source inductance), again assuming RD = O. The interesting conclusion of this calculation is that for a Behavior with RD = = = =0 5·50 = = which rhp poles can exist as a function of RD for RG = o. Since the assumed device capacitance parameters are typical for devices with widely differing RDS(on) specifications, the results of this analysis imply an aggravation of the oscillation problem for low voltage devices, where RDS(on) is typically fractions of an ohm. ' ratio LG/LS greater than approximately 2.6, (Ib) possesses no rhp roots. '00 '0 Effect of RS In a system exhibiting a pair of rhp poles, the resulting oscillation will grow exponentially with a time constant proportional to its Q. The higher the Q, the slower will be the growth of the oscillation amplitude. Therefore, the duration of validity of the model of Fig. 2 is critical in determining whether these oscillations will be observed. In this respect, the gate drive source resistance, RS, of Fig. I is important because it, together with the device input and reverse transfer capacitances, Ciss and Crss , will determine the rise and fall times of the drain variables, and thus the duration of time spent in the saturation region. This is consistent with experimental results which have shown oscillations to appear in the presence of relatively large gate drive source resistance, but to disappear when the drive resistance was reduced. 02 0' 0050' - , -.... 02--'"'"'--','-,-"'"20--5'-0--'''-'----'200 gml S) Minimum Value of RG Necessary to Assure Stability of the Model of Figure 4(b) with RD = 0, as a Function of gm, for Various Values of LG and LS: = = = (a) LG 5 nH, LS 5 nH (b) LG = 5 nH, LS 20 nH (c) LG = 20 nH, LS = 20 nH Figure 6 It is clear that under the assumption RD = 0, the model of Fig. 2 predicts unstable behavior for a wide range of practical values of the parasitic parameters. Experimental Results Behavior with RD :f. 0 A series of experiments was performed to verify the qualitative aspects of the analytical results presented above. It is first shown that the oscillations appear primarily in the differential mode circuit. A critical value of the ratio LG/LS is observed, and the effect of RD to restrict the range of gm over which oscillations are possible is verified. Figure 7 shows the results of applying the RouthHurwitz criterion to (Ib) for LG = LS = 20 nH. The minimum value of RG necessary to assure no rhp roots is plotted as a function of gm for various values of RD. These curves show that as RD increases, the region of gm over which oscillations are possible decreases, until at some critical value of RD no rhp roots will exist even if RG = O. For this specific example, this critical value is 1.9 ohms. Figure 8 shows the behavior of the range of gm over 14 \ \ \ -- 12 " em(S) Rolli) 2' Theoretical Range of gm Over Which Oscillations Persist, as a Function of RD for RG = 0 and LG = LS = 20 nH Figure 8 Minimum Value of RG Necessary to Assure Stability of the Model of Figure 4(b), as a Function of gm for Various Values of RD Figure 7 5·51 Figure 9 shows the schematic of the experimental circuit. A pair of 1RF530's were placed adjacent to each other on a common heat sink. The pulsed gate source consisted of a DS0026 clock driver being driven by a 74LS123 monostable. The load resistor was a 2 ohm non-inductive Dale NH250 and the clamping diode was a fast recovery UES1403. The gate drive source resistor, RS, was adjusted to ensure that the saturation region residence time was long enough to permit the oscillations to develop. In addition to switching tests, steady-state oscillatory behavior was observed by placing the devices in their saturation regions using a DC gate drive. 211 (a) (b) UES 1403 (c) Circuit Used to Experimentally Verify Theoretical Conclusions Figure 9 To verify that the oscillations are differential mode in nature, an explicit differential source inductance was created by connecting the source terminals together with a small loop of wire (r = 0.35"). Connection was then made to common mode ground from the middle of this loop with a relatively long (3") piece of wire. The voltage waveform along the loop, with respect to common mode ground, was then observed while the devices were switching and exhibiting the parasitic oscillation. Figure 10 shows these waveforms and the corresponding measurement location referenced to the connection at the middle of the loop (100% is the source lead at the package). It is apparent that only a small fraction of the parasitic voltage shows up across the common mode source inductance, even though it is substantially larger than the differential mode source inductance, thus confirming the theoretical conclusion that the parasitic oscillation is a differential mode phenomenon. (d) Differential Source Voltage Measured at Different Points Along the Differential Source Inductance; (a) 10%, (b) 25%, (c) 75%, (d) 100% Figure 10 The source loop was next removed and replaced by a short, direct connection. The gate-to-gate connection was then made with a loop whose size was successively increased until oscillations ceased, thus confirming the theoretical prediction of a critical ratio LolLS above which there are no rhp poles. Although a quantitative measurement of the differential source and gate inductances was not attempted since a component of these inductances is internal to the package and not accessible, geometric approximations suggest that the observed critical ratio was approximately 2. 5·52 proximately constant. The measurements, however, were made at relatively low values of VD where the manufacturer's data shows Ciss, Crss , and Cos s changing quite rapidly as a function of VDS. Analysis has shown that both of these phenomena will give rise to an increase in the range of gm over which oscillations can occur as VD is increased, a conclusion consistent with the qualitative aspects of Figs. 8 and 11. The source and gate connections were next both made with short straight wires and the pulsed gate drive was replaced by a DC source. The gate voltage was then increased from zero until oscillations were observed and the corresponding drain current recorded. Increasing the gate voltage further eventually caused the oscillations to cease. The drain current at this point was also recorded. The transconductance, gm, at these points was then obtained from measurements or the manufacturer's data sheets, depending on the current level. It was observed that the resulting range of gm was sensitive to the applied drain voltage, Vcc. The range of gm supporting oscillations was thus determined as a function of Vcc and is shown in Fig. 11. The quantitative discrepancy between the analytical and experimental results can be attributed to several causes. The first is that the parameters for the model of Fig. 2 were measured at a frequency of 1 MHz, whereas the observed frequency of oscillation was 65 MHz. Although the distribution and value of the small signal energy storage elements are not likely to vary much between I and 65 MHz (because they are dominated by the MOS and junction structures, neither of which has strong frequency dependencies in this range), parasitic loss mechanisms within the device will likely exhibit a strong dependence upon frequency, with most of them producing losses which increase with frequency. For instance, the channel body resistance was not taken into account in the model, although Oxner has shown this to be an important component of Ro at high frequencies. [5] These additional parasitic losses will decrease the analytically predicted range of gm over which oscillations may persist, as can be inferred from Fig. 7 for the case of an increasing RG. An additional reason for the discrepancy is that measurements showed LG and LS to be approximately 50 nH, whereas the analysis resulting in Fig. 8 assumed values of 20 nH. 9m(S) Experimental Range of gm Over Which Oscillations Persist, as a Function of Vcc Figure 11 Conclusions Discussion An incremental, differential mode circuit model has been used to analytically predict experimentally observed oscillations in paralleled power MOSFETs. The oscillations depend upon the differential mode parasitic gate, drain, and source impedances, and not _ _ upon the common mode elements most accessible to the circuit designer. The region of potential oscillation increases as RD decreases, suggesting that the parasitic oscillation problem may be most severe for low voltage, high current devices. It is shown that the introduction of differential mode gate resistance can eliminate the potential for instability, and that increasing switching times can aggravate the tendency to oscillate. The experimental results reported above are essentially consistent with the theoretical analysis. The major discrepancy is between the theoretically predicted and experimentally observed ranges of gm over which oscillations can occur. For the IRF530 the maximum specified value of RDS(on) is 0.18 ohms, which, from Fig. 8, implies a very large range of gm based on the theoretical analysis. However, Fig. 11, which is based on measurements made for RG = 0, shows that the observed range is quite restricted, especially for low values of drain voltage. The range also increases rapidly as the drain voltage is increased. There are two plausible explanations of this latter behavior. The first is that the lightly doped drain region of the device is partly depleted when VDS > O. This depleted region increases as VDS increases, resulting in a reduction in the contribution of the n-drain region to the bulk drain resistance. The second is that the assumed values of the capacitances in the model of Fig. 2 were those for the devices operating deep in the saturation region where the capacitances are ap- These results are particularly significant for chip paralleled devices, for in this case the small parasitic inductance could give rise to very high frequency oscillations which could build up quickly relative to even "fast" switching times. In addition, these oscillations may not be observable because all the elements of the differential mode model of Fig. 3 are 5·53 inside the package. This suggests that devices to be paralleled at the chip level be fabricated using silicon gates of an appropriate sheet resistivity, or that small, discrete resistors be inserted in series with the gates of chips fabricated using metal gate technology. [1] For package paralleled devices, these results support the use of differential gate resistors [2,3] and gate drives which achieve fast switching times. In addition, the existence of a critical LGILS ratio supports the use of ferrite beads on gate leads to increase Lo. [3] References [2] [4] Acknowledgement The authors are grateful to Kurt Ware and Tom Lee, who as undergraduate students contributed to initial aspects of this work. This research was supported. in part by unrestricted grants from Lutron Electromcs Co., and the Gould Foundation. [5] 5·54 HEXFET Databook, International Rectifier Corporation, 1981, p. 20. Sloane, T.H., H.A. Owen, Jr., and T.G. Wilson, "Switching Transients in High Frequency High Power Converters Using Power MOSPETs," IEEE PESC Record, 1979. Oxner, E.S., Power FETs and Their Applications, Prentice-Hall Inc., N.J., 1982, p. 129. Kassakian, J.G., "Some Issues Related to the Behavior of Multiply Paralleled Power MOSFETs," Proceedings of IPEC-Tokyo, March 1983. Oxner, E.S., "Meet the V-MOSPET Model," RF Design, Jan/Feb 1979, pp. 16-22. 5.3.4 Power FET Paralleling Introduction Paralleling of power MOSFETs is not aLways as easy as it may seem. When all the devices are fully enhanced (fully ON), the probLem is minimaL both because the toLerance of RDS(on) is small and because the positive temperature coefficient of FET conduction resistance tends to enforce proper current sharing through junction temperature differentiaLs. During the switching period, however, current sharing can be a probLem. If this probLem is not attended to, the surge current in one of the devices during switching may exceed the ratings of the device. This is especially true for high-frequency high-puLse-current applications. In this paper, the causes of dynamic current imbaLance will be presented and recommendations for alleviating dynamic current imbaLance will be suggested. constant will take more than its share of current during switching. Device Parameter Values Typical gate-to-source threshold voltages VGS(th) for commercially available devices range from 2 to 4 V. Transconductance, gfs, depends on the device current rating. In general, the larger the current rating, the larger the gfs. For 5-A devices, the values range from 1 to 3 S. For 10-A devices, they range from 5 to 10 S. The magnitude of gate capacitance Ciss, which is the sum of gate-source and gate-drain capacitances, depends on the chip size. The higher the voltage and current ratings of the device, the larger the chip size, and, consequently, the larger the gate capacitance. Typical values of Cjss for commercially available devices range from approximately 5000 pF _ for a 500 V, 20 A device to 150 pF for a 100 V, 3 A device. The tolerance of Ciss for a given device is normally within ±30%. Dynamic Current Sharing The causes of dynamic current imbaLance can be classified into two categories: device reLated and circuit related. Device parameters that directly affect dynamic current imbalance include gate threshold voltage (VT), transconductance (gfs), and input capacitance (C g). Circuit parameters critical to dynamic current imbalance include the parasitic inductances of both the gate-drive circuit (LG) and the power circuit (Lp) as well as the gate-drive circuit source resistance (RG). The reason both VT and gfs are involved in current imbalance during switching should be obvious. Devices with lower VT and/or larger gfs will carry more current at any V GS in their linear region. Gate parameters Ciss, RG, and LG affect the time required to charge the gate capacitance from a gate-voltage source with a fixed impedance. A FET with a gate-drive circuit that has a smaller time Temperature Effects Device gate-source threshold voltage decreases with temperature. A typical device threshold decreases aproximately 5 mV per 0c. Transconductance, gfs, also decreases with temperature. The temperature coefficient is - 2% per °C. It can be seen from the above characteristics that if one of the paralleled devices heats up due to current imbalance, the negative temperature coefficient of VT tends to aggravate while the negative temperature coefficient of gfs tends to alleviate current sharing problems during switching. This is different from 5·55 conduction state current sharing in which both the positive temperature coefficient of channel resistance RDS(on) and the negative temperature coefficient of gfs contrIbute to reduction of current imbalance. duration of current imbalance during switching. To increase the drive circuit speed, one should reduce the gate-drive impedance (see Figure 1). It should be noted, however, that extremely small values of RG may not be enough to damp undesirable oscillation in the paralleled gate circuits. Parasitic inductances around the gate circuit must also be minimized. Recommendations for Controlling Current Sharing Problems There are basically two approaches to control dynamic current imbalance: by means of device parameter matching and by means of circuit techniques. Device Parameters Matching Dynamic current imbalance can be minimized by matching the three device parameters described in the previous section, i.e. VT, gfs, and Ciss. The sensitivity of current imbalance to each parameter is different, however. Of the three parameters mentioned, matching of gfs and Ciss is less critical. For transconductance mismatch, the worst case current imbalance is limited to the percentage of tranconductance mismatch. Furthermore, if a device heats up due to mismatch, the negative temperature coefficient of transconductance tends to reduce the imbalance. The effect of input capacitance mismatch depends on the external gate-drive impedance as described in a following paragraph. ... Lp LS FET Switching Circuit with Two Devices In Parallel Figure 1 Of the three device parameters to be matched, the most critical one is the gate threshold voltage VT. The amount of current imbalance due to VT mismatch is essentially unlimited. The negative VT temperature coefficient further worsens dynamic current imbalance. Conclusions The causes of current imbalance in paralleled MOSFET switching power circuits have been examined, and some techniques have been recommended for improving imbalance. It has been shown that some parameters are more critical than others in affecting the imbalance. Threshold voltage VT mismatch, for example, can be very critical to dynamic current sharing. The amount of current imbalance depends both on device parameters and circuit parameters. Reference 1 gives several numerical examples of the degree of current imbalance for some specific power MOSFETs. Circuit Means for Controlling Imbalance There are several circuit techniques recommended for minimizing dynamic current imbalance. All, however, result in some additional alterations to circuit performance. Thus, trade-off decisions must be made by the circuit designer. Gate Drive Circuit The optimum circuit technique for improving current sharing during switching is merely to increase switching speed. By increasing the gate-drive circuit speed, one can reduce the time required to charge and discharge the gate capacitance and thus reduce the Reference Forsythe, James, "Techniques for Controlling Dynamic Current Balance in Parallel Power MOSFET Configuration," 1983 Powercon 8. 5·56 5.4 dVns/dt Turn-On in MOSFETs (TA84-4) Introduction Under certain conditions, when a rapidly nsing voltage waveform IS applied from drain to source of a supposed "off" MOSFET, the device will turn-on. dV/dt turn-on is well known in SCRs and bipolar junction transistors (BITs). This phenomenon in MOSFETs is similar in many respects except that dV/dt turn-on occurs at much higher rates than it does in either SCRs or BITs. Because spurious turn-on can be destructive, it is of serious concern in those applications where it might occur. DRAIN eSTRAY GATE Several different modes of dVDS/dt turn-on have been identified, and in most cases, turn-on may be eliminated or the effect of turnon may be reduced to an acceptable level. npn RG Ro Lo To eliminate this problem, the mechanisms of the turn-on modes, the consequences of spurious turn-on, the means for reducing or eliminating turn-on, and the applIcations where turn-on is likely to be a problem, must be understood. The following discussIOn intends to provide the basic mformation on dVDS/dt turn-on needed by the design engineer. Vo-=- )~, ;- SOURCE N Channel MOSFET Equivalent Circuit Figure 1 Equivalent Circuit Model drive circuit, an equivalent senes battery (VD) IS present. In some cases, a DC bias may be present, so V D could be either positive or negative. Cstray represents the parasitic capacitance from drain to gate due to the circuit layout. This capacitance may be as large or larger than the intrinsic Cgd if careful layout is not used. Figure I is an equivalent circuit model for a power MOSFET which includes the parasitic elements within the device and withm the drive circuit (R D , LD, Vd ). The parasitic NPN BIT, an integral part of the device structure, is present in all VMOS and DMOS devices. To minimize the effect of the BIT, Rb is made as small as possible, and HFE is low. Nonetheless, in some circumstances the BIT can be turned on. RG is the mternal gate resistance. The value of this resistance varies from 0.05 to 5.00 depending on the manufacturer and the size of the device. Siliconix devices typically run from 0.5 to 4.00. The impedance of the drive circuit (Zgs) may take many forms, but the series R, L, battery is representative. RD comes from several sources: resistance deliberately placed in series to limit the peak current or reduce the rise time of Vgs , bypass capacitor ESR, wiring resistance, the on resistance of drive switches, etc. LD is due to the physical size and layout of the drive circuit. If a transformer is used for dnve isolation, the pnmary-to-secondary leakage inductance will add to LD. When series diodes or BITs are used in the The mtraterminal capacitances of a MOSFET are functions of VDS as shown in Figure 2·. Because Cgd and Cds are functions of VDS , spurious turn-on will depend on both dVDS/dt and VDS , whIch complicates the analysis. In the following discussion, the body-drain diode will be mentioned. This diode is the basecollector junction of the parasitic BIT. • NOTE: Because C be » C db , Cdb - Cds 5-57 l1li 1000 NO TURN-ON VTH2 "-..".,. I' J ...... LL E; W o zc:( !:: 100 ....... Cgs 1""0" , I oc:( D.. c:( o o " 1 VOS " '" 10 r--...~ (A) Cds IB) Mode 1 Equivalent Circuit Figure 3 Cgd 100 VOLTS Intratermlnal Capacitance Figure 2 The following modes of dVDs/dt turn-on have been observed: I. Device quiescent: Zgs high, MOSFET turns on. 2. Device quiescent: Zgs low, BJT turns on. 3. Body-drain diode conducting: Zgs low, BJT turns on. 4. Body-drain diode conducting: Zgs low, BJT goes into avalanche breakdown. Mode 1 Spurious MOSFET Turn-On. Rg = 10 ohms Figure 4 Mode 1 Turn-On The equivalent circuit for mode I turn-on is given in Figure 3 along with a generalized waveform for Vgs. The exact nature of the Vgs waveform will be a function of Zgs and Cstray, but in general, the lower the impedance presented by Zgs and the lower the value for C stray , the lower the peak value of Vgs. If Vgs exceeds V'h, the device will turn on. In most applications, the amplitude of I D , during turn-on will be limited by RDS(on). This mode of turn-on is not usually destructive, although it will increase the power losses. Figures 4 and 5 show actual turn-on waveforms when Zgs is resistive. 10Vi Vos ,... 1m ~ - - L \, ,... - Even when the FET is not turned on, a pulse of drain current will be present due to the intraterminal capacitances. An idealized waveform for this case is shown in Figure 6A, and a more realistic waveform is shown in Figure 6B. There will always be some series inductance which, when combined with the nonlinear capacitances, produces a distorted, damped sinusoid. ~ h.. ~ A. ,... 500lmV SinS Mode 1 Spurious MOSFET Turn-On. Rg Figure 5 This current pulse will be reflected into the switch which is generating the positive dVDS Idt. = 100 ohms Jl One additional complication to mode I turn-on has been suggested but not observed. If the FET is turned on, it is possible for parasitic oscillations to occur. This would raise Vgs and increase the power dissipation. It is possible for the gate to be ruptured ifVgs becomes large; however, if oscillation is not present during normal switching, it is unlikely that it will occur during mode I turn-on. The best way to detect potential mode I turn-on is to observe the gate-to-source voltage waveform with an oscilloscope. If a significant voltage spike appears during the drain voltage transition then some positive action will have to be taken to reduce the pulse amplitude. (A) Ideal (8) Realistic Pulse Drain Current Waveforms Figure 6 5-58 200 Mode 2 Turn-On The equivalent circuit for mode 2 turn-on IS given In Figure 7, along with VDS and ID waveforms. The mechanism forthis mode of turn-on is quite simple. As VDS slews, current will flow through Cdb • If enough current flows so that the voltage across Rb exceeds -O.65V, some of the current will flow into the base, turning on the BJT. In contrast to mode I, the acceptable d VDs/dt rate is only a function of the device design, not of the external circuit elements. OJ 150 '§ 100 ~ ;:; 50 a The result of mode 2 turn·on can be harmless or cata~trophic depending on VDS and the magnitude of the base current. a 100 300 400 IV) dVosldt Limits in Power MOSFET Figure 9 DRAIN + VDD- .... Z w C! W ~ 'j 200 VOLTAGE Mode 3 and Mode 4 Turn-On 0: 0: 0 ::l U > Frequently the body-drain diode is used as a catch diode for an inductive load. In a few applications, such as sinewave synthesis or some motor control schemes, the positivedVDS/dt is applied while the diode is conducting. Figure 10 shows the equivalent circuit for this condition. Just priorto the application the voltage ramp, IR is flowing through the BJT in a reverse direction. Much of the current will flow through Rb and the collector-base diode. Even in the inverted mode, however, the BJTwill have some current gain, and a portion of IR will flow in reverse through the emitter, as indicated. As a result of this current flow, the device is saturated with charge, i.e., it is hard on at the moment the dVDS/dt is applied. z BVCEO and base current is injected, the device will go into avalanche breakdown. Furthermore, if ID is not limited by the external circuit, the device can go into secondary breakdown and will be destroyed. BVCEO BVCER BVCEX BVCBO IC Mode 3 Equivalent Circuit Figure 10 Typical voltage and current waveforms for mode 3 operation, with and without turn-on, are shown in Figure Ii. Figure llA shows the waveforms for the case where the BJT does not turn-on and VCE Breakdown in a BJT Figure 8 So much for the bad news. Now for the good news. In modern MOSFETs, the dVDS /dt rate at which mode 2 turn-on can be initiated is generally very much higher than most applications will ever see. The dVDs /dt limits for Siliconix devices are shown in Figure 9. Realize that the rates shown correspond to transition times of one to three nsec. Very few applications require transitions this rapid. Even testing at these rates is a formidable problem. TURN-ON NO TURN-ON (8) (A) Mode 3 Waveforms Figure 11 5-59 - -3---, thus acts like a normal p-n junction diode. Looking at the waveforms, the sequence IS initiated by a switch closure at t = to' The current through the diode begins to reverse at a rate (dI/dt) which is determined by the switch transitIOn time and/orthe circuit series inductance. If the switch transItion is very rapid, the circuit Ind uctance will dominate; conversely, if the transition is slow, the SWItch dominates. During the interval to-t I> Vos changes only slightly (-I to + I volt). VOS does not change significantly until 10 reaches its maximum value and begins to fall. At t= tl, Vos begins rising rapidly. The rate of dVos/dt at this point is determined by the circuit series inductance, the peak current and the recovery characteristic of the diode. The recovery characteristic is in tum a function of the initial dI/dt. This relationship is illustrated by Figure 12. The more rapid dI/dt, the greater will be the peak amplitude ofIo , Q,. will be larger and trr shorter. More important, the dID/dt during the interval t l -t2 becomes greater as the initial dl/dt is increased. In some diodes, dIoIdt can increase dramatIcally and can form a sharp step or snap as indicated in Figure 13. At lower levels of initial dIo/dt, the step may not be present, but as the initial dIo/dt is increased, the step appears. This current step during recovery can generate extremely high rates of dV/dt in the circuit. -2---~ -1----0\ t + ------------~~------------~~~--_ IF + VarIatIon In Trr with IF Figure 14 failure. Notice that the BJT turn-on occurs during the interval tl-t2 and is triggered by the dVDs!dt resulting from the recovery characteristic of the diode. The dVDS/dt during the interval trt2 is related to the switch transition time, but it is not a direct function. This is very different from modes I and 2 where the current waveforms are coincident with and directly proportional to the transition time. + Mode 3 turn-on is an indirect function of transition time and is more directly controlled by the circuit and the recovery characteristic of the device. In terms of rating the device for dVos /dt capability, the appropriate voltage transition is not the switch transition but rather the transition which appears across the diode during the second portion of the recovery interval. Or-------~~----~~~-------T This complex interaction deserves a more detailed examination. The following discussion uses a successive approximation to explain what happens during mode 3 operation. An equivalent circuit for mode 3, where turn-on does not occur and the device can be viewed as a diode, is given in Figure 15. Note that the inductive load current is assumed to be constant during the recovery interval and is represented by a current source. L I and L2 are the circuit parasitic inductances. Variations In Trr and Q rr with di/dt Figure 12 Or-------~-------- _ V3 + r-"---, __~~---------T SOFT RECOVERY SNAP RECOVERY Soft Versus Snap Diode Recovery Waveform Figure 13 Mode 3 Equivalent Circuit FIgure 15 A further complication exists: the diode recovery characteristics are also influenced by the magnitude of 10 during reverse conduction. This relationship is shown qualitatively in Figure 14. The reverse recovery current waveform (II) can be approximated by triangular waveforms as shown in Figure 16. From this approximation, the voltage (V3) across the diode is easily determined, as shown. The critical point in the waveform is the rapid and large positive transition which occurs when the waveform Figure II B shows the waveforms when turn-on is present. Two cases are shown: recovery without damage and catastrophic 5-60 The device could respond to the voltage transient in several ways: I. !fthe amplitude is small and dVos /dt moderate, the device recovers normally. 2. Mode 3 turn-on could occur without avalanche breakdown. 3. Mode 4 turn-on could occur; i.e. the device avalanches before the BJT turns on. 4. Mode 3 turn-on could occur, lowering BVos s , leading to avalanche breakdown and perhaps second breakdown. Each of these turn-on scenarios is potentially destructive. ~::::1 dl 21 o'~~------------------------------- +Vo The complexity of the mteraction between the parameters makes it difficult to characterize FETs for mode 3 and 4. Figure 18 displays the results of preliminary testing of Siliconix devices. Competitive devices were also tested and found to be no better at best, and much worse in some cases. While this curve is hardly definitive, it does show that modes 3 and 4 turn-on levels are an order of magnitude lower than mode 2. The dl/dt levels used in th~ testing were in the range of 150 A/ usec. This is representative for motor control or low frequency AC synthesizer; however, LF transmitters and sonar transducer drivers would be expected to have much higher dl/dt rates which would further reduce the acceptable dV/dt. "2 VI ~ V2 -Vo 2" -Vo 1- --------------. , , ,, ,,, ,, ,, , ,, , 4Vs ,,, ,, , ___________ I I ~-~----------- +1V Fortunately, mode 3 operatIon is restricted to a few special applications such as: I. Motor drives and sinewave inverters where multiple repetitIve pulsing of the sWItches occurs. 2. Highly reactive resonant loads, such as found in LF transmitters, sonar transducer dnvers, and induction heating equipment. 3. Synchronous rectifiers where the body-drain diode is allowed to conduct. -1V Triangular Waveform Approximation Figure 16 di/ dt reverses. The amplitude of the transition is a function of di/dt dunng recovery-a diode characteristic. A diode with a snap characteristic would generate a very rapid, high amplitude voltage spike. Figure 16 indicates an infinite dVos /dt, which is not what is observed. A better approximation would be to use a trapezoidal waveform as indicated in Figure 17. Figure 17 also shows the actual waveforms. From this figure, we see that the large voltage transient still exists. Its amplitude is essentially the same, but the dVos/dt is finite. We can see that the reverse recovery characteristic of the diode determines both dVos /dt and the amplitude of the transients. dV/dl SLEW RATE (V/nS) 20 10 o Lo----.J...----.,.10,LO"..%----L-----2...JOLO.-V.----L-----:3...JOO% PERCENT OF RATEO FORWARD BODY-DRAIN DIODE CURRENT Vl'V2{+~~L-------~-'-'----------------- -vo Mode 3 Performance Figure 18 The Effect of Radiation and Tj on dVDS/dt "2 ____________ :: -vs L_.J 4Vs The effects ofTj and radiation on dVos/dt behavior have not been discussed. While little testing has been done, trends can be identified. Vth has a negative temperature coefficient of four to eight mV/cC, so that at high temperatures Vth is lower. This will lower the rate at which mode I turn-on occurs. At higher temperatures, Vbe will decrease in the BJT, and the gain will increase. Both of these effects will reduce the acceptable dVDS /dt rate for modes 2 and 3. -----------r/;.l p f: V3 " 2Vo ----------," ," Vo ---------+1V Ionizing radiation has two effects for total doses above IOKRad(Si). First Vth is reduced, and second the gain and diode recovery time of the BJT are reduced. This implies that mode I performance is degraded, but modes 2 and 3 should be improved. -1V Trapezoidal Waveform Approximation Figure 17 5-61 How to Avoid dVos/dt Problems ,1 I "f . .". . f" T I ~( ,t In most circUIts, dVosjdt turn-on may be avoided. There are many ways to accomplish this: I. Reduce dVosidt 2. Low impedance drive circuits 3. Good circuit layout practice 4. Negative gate bias 5. Series drain diode 6. Snubbers 7. Turn-on of the FET during commutation 8. Use MOSFETs with good dVjdt performance 9. Current fed topologies e \ The most obvious way to reduce dVjdt problems is to slow the switching speed. This can be accomplished easily by adding resistance in the gate as shown in Figure 19. The diode is added to provide a low impedance when the device is off so that mode I problems do not arise. + TWISTED PAIR, COAX OR STRIPLINE ie LOW L CONNECTION dV/dt Slowdown Circuit Figure 19 Low Inductance Connections Figure 21B The best means to avoid mode I turn-on is to use a low impedance driver and good circuit layout. Figure 20 illustrates how to design a good drive circuit. It is also very helpful to reduce the noise and ringing in the overall circuit. Mode 3 performance may be improved by reducing or eliminating the current in the body-drain diode. Two ways to do this are shown in Figure 22. In (A) the FETchannel is turned on to divert current away from the body diode. This can be very effective as shown in Figure 23. Figure 23 is a superposition of the FET and diode conduction characteristics in a VNE003A. In this particular device, the diode would not start conducting until 10>30 Amps. In very noisy environments, it may be necessary for Vgs to be negative during the switch off interval. The noise coupled to the gate will have to overcome a potential of Vth + Vbla,. MInimize Parasitic Feedback Capacitance --.. .n.. Another method which eliminates diode conduction entirely is shown in (B). A low voltage diode is placed in series with either the drain or source, and a normal diode is added in parallel to carry the commutation current. This approach will eliminate mode 3 turn-on, but there is a penalty in the power cost in the series diode and in the extra cost of the external diodes. i v~v-","---v~,1 ~wisted ( MINIMIZE THE AREA High di/dt Paths Figure 21A PaIr Reduces' • Inductance • NOIse Pickup • Parasitic OscIllatIon (nneCI Direct To MOSFET Termonal 1 f"'qf Minimizes Common-Source Inductance Low Impedance Dnve For • Fast Switching • MInimiZe Noise Pickup • MInimIZe dV/dt Turn-On Circuit Layout to Reduce Mode 1 Turn-On Figure 20 Figure 21 shows how to layout an H-Bridge switch-mode power converter primary to minimize noise, ringing, and coupling from one point of the circuit to another. The principle is quite simple; first Identify those paths in the circuit where the switched currents are flowing and then minimize the inductance and radiating area of these current loops. These techniques will not only reduce dVosjdt turn-on but will be beneficial in reducing EMI, eliminating voltage spikes and generally cleaning up the circuit waveforms. - S I I I (A) CHANNEL ON SHUNTING CURRENT + \.. SERIES DRAIN DIODE - -"\ I I I I D ~. r--....I I (6) SERIES DRAIN DIODE Schemes for Reducing Body-Drain Diode Conduction Figure 22 5-62 Appendix Another scenario for mode 2 turn-on has been postulated but not observed. Figure 25 shows a simplified boost converter where the MOSFET is represented by a perfect switch in parallel with the intrinsic BJT. When the switch is opened, some of the inductor current (ILl will flow into Cdb . If IL is large enough, it is conceivable that the BJT could be turned on. The effect on the turn-off waveform would be similar to storage time in a BJT, i.e. extended turn-off time. Body Diode/Forward Conduction Comparison Figure 23 In extreme cases, snubbers may be used to reduce the dVos/dt, the transient amplitude and to limit current pulses if turn-on should occur. The effect of dV/dt turn-on will depend on the impedance of the circuit in which the device is being used. For example, the circuit shown in Figure 24A is a voltage fed switch-mode power converter. When S I is closed, a positive dVos/dt will appear across S2. If S2 is turned on then a short circuit will appear across the transformer windmg. There is little to limit the current because the source impedance is very low. GIven the same circumstances in Figure 24B, the series inductor will limit the rate of current rise. The probability of damaging the switches will be reduced. Postulated Mode 2 Turn-On Mechanism Figure 25 Conceivably, several turn-off pulses could occur as the BJT turns on stealing base current. Like all mode 2 turn-on, this effect will only be possible for very rapid transitions. A mode of anomalous tum-off ringing has been identified by Giandomenico (6). This ringing could easily be mistaken for the mode turn-on just discussed or for parasitic oscillation. The ringing occurs when there is excessive unclamped drain inductive and is described by Giandomenico, et aI, as follows: "When the power MOSFET inverter circuit shown in Figure 26 is suddenly turned off, the drain voltage rises quickly and then abruptly drops to the "on-voltage" where it remains for several 2SV ~~'25 N" QuasI squareware Con~erter Voo:25V I Vo~ -25V Wirewound Resistor 117 pH L 1 1 170 RL -.J Voltage and Current Fed Converters Figure 24 Conclusions dVos /dt turn-on does exist in power MOSFETs, so the following conclusions may be drawn: I. Mode I is primarily a circuit problem which can best be eliminated by usmg low impedance drives and good circuit layout techniques. 2. Mode 2 occurs only for very high values of dVos/dt; therefore, this is seldom a problem. 3. Modes 3 and 4 are potentially the most troublesome but occur only in specialized applications. Modes 3 and 4 may be reduced or elimmated WIth circuit modIfications. The Power MOSFET Connected In an Inverting Configuration Figure 26 5-63 - microseconds before ringing and settling to the supply voltage (see Figure 27 A). This behavior was initially thought to be due to dV/dt breakdown and was thought to be related to the "on-state" oscillations. However, this turn-off behavior is in fact due to the clamping diode between the drain and source which is intrinsically incorporated into the vertical MOSFET structure. A typical display of the drain voltage and current during turn-off is shown in Figure 27B from which the turn-off phenomenon can be explained. "Neglecting reverse recovery, the time at which the diode current is zero is: ton = = 7T v'LC In [2VDD+VF] RL (6) VDD + VF "For a reasonably large supply voltage, Vdd> > 0.7 volts, the above equation can be expanded in a Taylor series to give: ton = •'When the device is turned off, the magnetic energy stored in the load inductance is transferred into the output capacitance and then returned to the inductor with the opposite current polarity. Neglecting the non-linearity of the output capacitance and the damping of the output load resistance, the time for the current reversal is: t (~) (~) RL [1 - ~] ln2 (7) 2V D D "Neglecting the reverse recovery of the diode for the moment, the drain voltage rises at this time and then rings and settles to the supply voltage. "A comparison of experimental data with the calculated results of eq. (7) reveals a large discrepancy in the "on-time." Further, the oscillographs of Figure 27 show that the power MOSFET appears to turn on a third time. These discrepancies are due to the reverse recovery of the diode (see Figure 27B). Consequently, the total turn-on time expressed by equation (7) must be modified to include the reverse recovery time, trr: (1) "After this time, the parasitic diode is forward biased, and the voltage across the inductor is: (2) where VF is the forward diode voltage. If the damping losses are neglected, then: ton = (3) ~ RL and [1 - ~] ln2 + trr (8) 2V DD "Since, after the diode's reverse recovery, the inductor once again has a downward current direction, the situation is the same as when the MOSFET first turned off but with a lower initial current level, and thus the cycle repeats again." (4) Bibliography A OV 1. J. Redonfey, "The Dv/DT Phenomenon in Power Transistors," The power transistor in its environment, ThompsonCSF, Semiconductor Division, Applications book, 1978. 2. J. Rockot, "Reverse Transistor Action In Transistor Inver- OV ters," Westinghouse Power Semiconductor Division, Tech Tip, pp. 1-13. OV 3. R. Severns, "dV/dt Effects in MOSFET and Bipolar Junction Transistor Switches," Proceedings of the IEEE Power Electronics Specialists Conference, June 1981, Boulder CO. 4. D. Kuo, C. Hu & M. Chi, "dV/dt Breakdown in Power MOSFETs," IEEE Electron Device Letters, Volume EDL-4, No.1, January 1983. 5. W. Slusark et aI., "Catastrophic Burnout in Power VDMOS Field-Effect Transistors," Proceedings of the 21st annual IEEE, Reliability and PhYSICS Symposium, 1983, pp. 173-177. 6. D. Giandomenico, et aI., "Analysis and Prevention of Anomalous Oscillations and Turn-Off Behavior in a Vertical Power MOSFET," private report done for Siliconix Inc., later published in the proceedings of POWERCON 11, April 1984, ~allas. B OA Oscillograph of the Turn-Off Behavior of the Power MOSFET Inverter a) Upper Trace: Vo = 10V/Oiv; Lower Trace: Vgs = 5V/Oiv. b) Upper Trace: Vo = 10V/Oiv; Lower Trace: 10 = O.2A/Oiv. Figure 27 7. "The drain voltage remains near zero during the time the diode is conducting. The current through the diode is dictated by the L-R circuit and is: F ( 2VDD +-VID=_-Rl_e-tRt/ L) L DD - VRL (5) 5-64 E. Oxner, "Static & Dynamic dV/dt Characteristics of Power MOSFETs," PCI Proceedings April, 1984, pp. 132-43. 5.5 Inverse Diodes of Power MOSFETs Introduction A parasitic anti-parallel diode is inherently built in the process of fabricating any power MOSFET transistor. This diode has voltage and current ratings equal to the FET, but has, in general, a slow reverse recovery. Depending upon circuit application, the parasitic diode could be a bonus or a problem, for the user. The slow recovery speed of the diode may result in a large recovery current spike and cause high power dissipation in an opposing FET switch. In this paper, first the formation of the parasitic diode will be described, then the problems associated with the diode in power circuits will be explained. Remedies for the problems will also be suggested. G OXIDE CHANNEL Epl n+ SUBSTRATE D DMOS Device Structure Figure 1 Formation of Parasitic Diode A DMOS device structure is used to explain the formation of a parasitic diode in the power MOSFET. As shown in Figure 1, source metalization overlaps both the p and the n+ regions. The reasons for this are, first, to stabilize the voltage of the p region so it does not drift when the device switches and, second, to suppress the action of the parasitic bipolar junction transistor in the structure thereby ensuring proper operation of the MOSFET. This metallization, however, connects an anti-parallel pn diode from source to drain. All MOSFET device structures, such as VMOS and HEXFET, have similar diode formation and, therefore, power MOSFETs will not block reverse voltage. considered to be a bonus for the user. However, the reverse recovery speed of the diode is normally between 200 and 400 nanoseconds. This can present problems in some circuit applications. . Problems of Using Parasitic Diodes in the Circuit In a power circuit with a single FET, the parasitic diode is seldom used and seldom presents any problems. However, in a power circuit with a loop consisting of two serially connected FETs and a voltage source, the diode may present a problem. Commonly used half bridge and bridge inverters are examples. Under certain operating conditions with these converters, the recovery of the diode causes problems as will be explained below. Because the parasitic diode uses the same Epi and p regions as the MOSFET, the voltage rating of the diode is the same as that of the companion MOSFET. The diode current rating is also the same as that of the MOSFET. Therefore, the parasitic diode is often Figure 2 shows a half bridge in which two FETs are used. In first quadrant operation, inductive current free-wheels through D2 and the load when 01 turns . 5·65 l1li OFF. When Q1 turns on again, there is a temporary short circuit formed by the loop of VS , Q1, and D2 during the reverse recovery time of D2. This will cause a large power spike in Q1 and D2 and may damage Q1. The reverse recovery time of D2 depends, among other parameters, on the amount of forward current flowing at the instant Q1 turns ON. If a discontinuous mode of operation is chosen, there will not be current flowing in DZ when Q1 turns ON; therefore, the problem described will not exist. A similar situation, of course, applies to QZ and D1. Va -=- D, v. n n l:v.J U L D, Va-=- Ib:' BACK EMF v, 0 0 n Ie) Two-Quadrant DC Chopper Circuit Figure 2 -v.__________ Similarly, in a bridge inverter circuit, the problem with the diode mayor may not be present depending on the nature of the load and inverter operating conditions. Figure 3 shows the inverter circuit diagram and several possible output voltage waveforms. Depending upon the gate drive timing sequence, the load voltage waveform can be classified into three categories: O Bridge Inverter and Three Basic Output Voltage Waveforms (a) Bipolar Square Wave (b) Unipolar Square Wave (c) Quasi-Square Wave Figure 3 Tn n 1. Bipolar square wave 2. Unipolar square wave 3. Quasi-square wave IL _v,J LJ I I I I I I I I I I I I An analysis of whether the diode will present problems will be given for each of the above three cases. Generally speaking, however, if the inverter circuit requires commutation of current from a diode to the opposing FET in the same totem pole then a severe current spike will occur. If the current is commutated from a diode to its companion FET then the problem will not occur. This is because the diode in the first case is subjected to reverse bus voltage, but in the second case, it is subjected to essentially zero voltage when the diode current is terminated. The next paragraph will discuss the load conditions under which the diode problem will exist for the three basic load voltage waveforms mentioned. 10104 L· I I I I I RLLOAD LEADING RLe LOAD LAGGING RLe LOAD (DIODE PROBLEM EXISTS) Figures 4, 5, and 6 show the load current waveforms and associated switch timing for different loads. Figure 4 shows the waveforms for the bipolar square wave output voltage. As can be seen, for R-L loads, Bridge Inverter Load Current Waveforms for the Case of Bipolar Square Wave Load Voltage Figure 4 5·66 v. I I I I I I -v.--r----r---Il I I I I I I I : Q,Q4 : I I I I I I I 1041>3 : 0,04 I I ~ I I I I : I Q,04 I RL LOAD I RL LOAD (DIODE PROBLEM EXISTS) Il LEADING RLe LOAD LEADING RLC LOAD Il LAGGING LAGGING RLe LOAD RLe LOAD (DIODE PROBLEM EXISTS) (DIODE PROBLEM EXISTS) Bridge Inverter Load Current Waveforms for the Case of Quasi-Square Wave Load Voltage Figure 5 Bridge Inverter Load Current Waveforms for the Case of Unipolar Square Wave Load Voltage Figure 6 diode current is always commutated by the companion FETs and, therefore, a diode recovery problem would not occur. For an R-L-C load, the current waveform could either lead or lag the voltage waveform. If the natural frequency of the RLC is higher than the inverter switching frequency then the current waveform will lead the voltage waveform. Figure 4, shows that the diode problem will not exist in this case because diode current is commutated by the companion FET. If, however, the current lags the voltage, which means the natural frequency of the RLC load is less than the inverter switching frequency, then the diode current will be commutated by the FET on the opposing part of the totem pole, and the diode recovery problem will occur. This has direct ramifications on the diode requirements for any resonant bridge converter. Circuit Remedy Since the diode is inherent in the MOSFET and its recovery time is much longer than the FET's switching time, a circuit remedy must be found in order to use the FET effectively. Figure 7 shows a scheme using a center-tapped inductor in each totem pole to limit the current surge during the diode reverse recovery time. This arrangement requires additional free wheeling diodes around this inductor to release inductive energy when the FET is cut OFF. Another circuit remedy is to use a Schottky diode, DS, in series with - Figure 5 shows the waveforms for the case of unipolar square-wave output voltage. For an R-L load, the load current may be continuous and, when it is, the diode current will be commutated by the opposing FET, and the diode recovery problem will occur. If the load current is discontinuous then the diode problem will not occur. Again, for the R-L-C load, only the lagging case presents problems. This is similar to the situation in the case of the bipolar voltage waveform. Figure 6 shows the waveforms for a quasi-square wave output voltage. The situation is similar to Figure 4. Among the three load conditions discussed, only the RLC "lagging" condition presents problems. Vs -=- Inverter Circuit Using Center Tapped Inductors to Reduce Temporary Current Spike Figure 7 5-67 each FET and use a fast recovery diode as the freewheeling diode. Figure 8 shows a circuit diagram of this arrangement. The purpose of the Schottky diode is to prevent current from flowing through the parasitic diode. Reverse current now has to flow through diode DF. Because of the fast reverse recovery nature of DF, the current spike during recovery is considerably reduced. Conclusion Due to the slow recovery of FET inherent diodes, a temporary short circuit could occur in several commonly used switching power circuits. The effects of the temporary short on the circuit are high power dissipation particularly at higher switching frequencies and possible damage to the FET. This should be avoided. It is noted that only certain operating conditions and load types. lead to diode reverse recovery problems and require a circuit remedy. Two solutions were recommended for this problem. One requires the addition of two inductors in the circuit. The other requires the addition of Schottky and high speed diodes. Va ..:... Reference Lee, F. C., D. Y. Chen, M. Smith, and G. Carpenter, "Characterization of High Power Darlington Transistors," 1982 Powercon. Inverter Circuit Using SchoHkys to Prevent the Temporary Circuit Short Figure 8 5-68 5.6 MOSFETs Move In On Low Voltage Rectification (T A84-2) The efficiency penalty imposed by the offset voltage inherent in Schottky and pn junction diodes has been a perennial thorn-in-the-paw for designers of low voltage, high current power supplies. Recent power MOSFET design advances allow designers to economically replace Schottky diodes and provide higher conversion efficiency in many applications. Using power MOSFETs will remove that thorn. a broad range, and then to optimize devices for certain applications such as low voltage rectification. MOSPOWER transistors may be used as synchronous rectifiers for any voltage, but they are receiving the most attention in the 10-50 volt breakdown range. Many designs for power MOSFETs are presently in use. In most cases these designs were originally optimized for the 100V to 400V range and, as a result, do not represent the practical limits of ON resistance for low voltages. To exploit the opportunity provided by the MOSFET, several questions must be answered: Figure 1 shows the performance of contemporary transistors normalized by multiplying total chip area (including all inactive chip area) by its on-resistance. 1. How is a MOSFET optimized for synchronous rectifier service? 2. What are the performance limits? This figure allows comparison of different size devices on the basis of the normalized resistance. The figure includes both theoretical and practical limits. From _ these limits, it is clear that below 100V, significant improvement remains to be made. 3. How is an optimized device used in a circuit to take advantage of its characteristics? 4. What is the basis for choosing between a MOSFET or a Schottky diode in a given application? Figure 2a shows the cross section of a contemporary MOS transistor. Device on-resistance can be minimized in several ways. First, the thinnest and lowest resistivity epitaxial layer consistent with the breakdown voltage is employed. Second, gate width must be optimized. If it is too wide, surface utilization is poor, while if it is too narrow, the JFET formed by body regions results in an unwanted increase in total resistance. The surface geometry also requires optimization to squeeze maximum performance from the devices. Figure 2b compares layout efficiency of various surface geometries. While the geometries vary only a few percent, one geometry (square-onhex) is more efficient than the rest. Keep in mind that The following discussion addresses each of these questions. When we have answered those questions, it will be quite clear that MOSFET synchronous rectifiers are a practical alternative to Schottky rectifiers, particularly for output voltages below 5Y. MOSFET Structures The present trend of power MOS manufacturers is to first provide transistor selections that perform across 5-69 SquarE> on CirclE' on 1. SourcE' geometry and grid Unll cell Coef'ICIE'nt of cellular squarE' grad square grll:S 0 0 0 0 0 0 O:~:O 0:0:0 0 00 0 '0' 0 000 o 0 000 [?i ~~~ ;0: 10 08862 I 0.0 0.0 0(0'10 °0'0 LC.JO 0(0'10 0'0 ci--o ,.-- ref gpomE'tru,'s Hl'ugon Square 01'1 Circle on He-lagon on on square heugonal helagonal heUigonal grId grid gnd grid [9] 09306 ... " ... 0__ ... 10746 ,.-- . > "0 t, r--" > '-_oJ <0...--- , 09523 10 The Efficiency of Various MOSFET Surface Geometries Figure 2b Low voltage, high current devices using some of these optimizing techniques are beginning to appear. Two such devices presently available are listed in Table l. These are practical synchronous rectifiers, but they are by no means fully optimized. A factor of two or more improvement should be possible. R,,, • (BVDSS)2 5 / ,/ [ IRF .~O{l Gl VMOS GL VMOS IR IILXMOS 5 10 • 8 q \0 11 l~ SlllCQNIX VN{,4GA SIUCONIX VNI.:!OOA SILICONIX SVH IR tll:XMOS Gl DMOS SIUCO:\IX V;-.,lJI... 10' 10' Br~Jl..lIo"n Table 1 The ratings of the lowest on· resistance commercially available MOSPOWER transistors. AlG SIPMOS DEVICE: PACKAGE: ON-RESISTANCE: BREAKDOWN: CURRENT: 10' Voh,.gc IBVI>St;1 IVolh) Normalized ROS(on) Comparison Figure 1 Source and Body SILICONIX VNCOO3A MOTOROLA POWER MODULE TO·3 .035 60V 60A Epoxy Module .018 60V 100A Electrical Characteristics oCPower MOS Transistors as Synchronous Rectifiers Gate The performance of a MOSPOWER transistor as a synchronous rectifier differs significantly from its use in either linear or switching applications. As shown in Figure 3, the MOS transistor will conduct current in an opposite direction to normal. The transistor should be operated so the intrinsic diode is not turned on, or the performance of the circuit may be altered, as shown in Figure 4 where current continues to flow for some time after the voltage is reversed. When the diode conducts, minority carriers exist. The presence of these minority carriers may have a second effect on circuit performance. The limit of a power MOS transistor is reduced when carriers are present in the body·drain junction region. When a MOSPOWER transistor is rapidly switched off, displacement current flows to discharge the body-drain junction capacitance. Figure 5a shows this behavior schematically. Figure 5b shows the dV/dt behavior of Siliconix devices without minority carriers present at the moment of transition. The dVldt turn-on threshold is greatly lowered when minority carriers are present. Reduction can be one to two orders of magnitude below that shown in Figure 5b. NN+ Dram Cross Section of a MOSPOWER Transistor Figure 2a the optimum design depends on breakdown voltage and drain current (in high current devices). Another means for reducing resistance is to increase chip area. In practice this means paralleling several die. 5-70 .. Reverse Conduction 300 Forward ConductIOn iii ~ 150 .;; ~ 100 t - - - - + - - - 7 " T...~ 50 v O~_~_L- a 100 __L-__L-~L-~L-~L-~ ~OO 300 400 VOLTAGE (V) The dV Idt Limits of Siliconix MOSPOWER Transistors When the Diode is Not Conducting Figure 5b Region of OperatIOn for Synchronous Rectification Several other considerations must also be made when using power MOS transistors for synchronous rectification. Gate-to-source voltage must be limited to manufacturer's maximum data sheet specifications. This requirement sounds straight forward, but the dynamic behavior of circuits, particularly switching circuits such as those found in switch mode power supplies, often results in unexpected transients. Careful design and analysis will prevent any unexpected voltage excursions. The Current versus Voltage Behavior of a MOSPOWER Transistor in Both the Forward and Reverse Directions Figure 3 Current The resistor-like characteristics of power MOS transistors are not maintained as the current increases for two distinct reasons. First, increase in current forces more carriers through the channel region, causing a transverse voltage drop. The channel region narrows, and the current that flows through the device saturates. This increase in ON-resistance as a function of gate voltage and channel current is shown in Figure 6. An increase in current also produces an increase in channel resistance due to device heating. Figure 7 shows the positive temperature coefficient of power MOS transistor resistance. Time The Reverse Recovery Characteristics of the Integral Diode of a MOSPOWER Transistor Figure 4 Designing in MOSFET Synchronous Rectifiers Gate Drive Timing Gate drive timing is critical to proper circuit operation. What constitutes proper timing varies with the type of converter circuit used. The popular quasisquare wave converter circuit (Figure 8) is a good example. Voltage and current waveforms are given in Figure 8b, and the proper timing for 11 and 12 conduction is a 50% duty cycle drive which is in phase with VS. While this is the most obvious timing scheme, it is not the only workable one. Figure 9 shows the waveform for 11 and 12 which exists in this circuit if a normal diode is utilized instead of a MOSFET. G S,B A Schematic Showing the Effect of Displacement Current (Id) on MOSPOWER Transistor Performance Figure 5a 5-71 l1li PW~l ON Resistance Characteristics 1.& fi) 'oLoA :IE ::c 1.6 u z 1.4 e. w ~ U) &1\ ~ 6A enw \ 1.2 a: 3~~~ z 0 r'-- "" 1.0 f--2A ~ ........ I "C ~ c PWM 0.& Quasi-Square Wave Converter Figure 8a < a: o o 2 4 6 Vas - VOS(th) & 10 12 GATE ENHANCEMENT VOLTAGE (VOLTS) II The Device Resistance as a Function of VGS and ISO for the IRF 730 Figure 6 12 TEMPERATURE EFFECTS ON rDS(on) 2.4 ""Z /" u ..: ..... 2.0 1/ en Vi ""e>::Z 1.6 0 1.2 / :i ..: ::E 0.8 ",: 0 Z I 14 V 0 u.J N 13 V ". 1/ ./ 0.4 VI~------t-------+-------;--------r---- ~ o -50 -25 0 25 50 75 100 125 150 175 Tj - JUNCTION TEMPERATURE (0C) V2~------t-------+-------;--------L---- The Normalized Resistance of a MOSPOWER Transistor as a Function of Temperature for the IRF 730 Figure 7 Quasi-Square Wave Converter Waveforms Figure 8b 5·72 time the secondary will be short circuited, and a large current spike will appear in the primary switches. This event is clearly undesirable. Fortunately, MaSFETs can switch rapidly and are easy to drive. These problems can be avoided with a little care when designing the drive circuit. In other circuits, timing waveforms and consequences of mistiming may be different. Two other converter circuits and their idealized waveforms are shown in Figures 11 and 1Z. In the buck-derived converter, there is no advantage to extending the conduction interval beyond 50% as there was in the quasi-square wave converter. On the other hand, ifthe conduction interval is too long, it does not cause current spikes in the primary switch due to the current limiting action of the input inductor. This performance is definitely an improvement over the quasi-square wave circuit. This circuit also accommodates too short a conduction interval by allowing the integral diode to conduct. Diode Rectifier Current Waveform in a Quasi-Square Wave Converter Figure 9 Notice that during the intervals when both S3 and S4 are off, IL divides more or less equally between the two rectifiers. In a diode this change in waveform isn't significant from a loss point of view. If we change the MOSFET gate drive timing as shown in Figure 10, the same current waveforms (without trr spikes) in the synchronous rectifiers will reduce power losses. The improvement occurs because conduction losses in a MOSFET are proportional to the rms current, and the extended conduction interval provides a lower rms waveform for the same average current. (a) Schematic 50') 1 V, rcdll~cd T Jo~~ Imllllg V~ (b) Waveforms V, O~ ____ ~~ ____ ~ -+______-L_ ______ - norm.1I Imllng Gate Drive Timing for Reduced Losses Figure 10 Consider what happens if the gate timing does not correspond to the ideal waveforms. There are at least two possibilities worth analyzing-too short and too long conduction intervals. If the conduction interval of S1 is terminated early, 11 must continue to flow (the switch is in series with an inductor!), and it will, through the integral diode within the MOSFET. This is not catastrophic, but it will increase the losses because of the higher forward drop of the diode. It will also introduce reverse recovery current spikes and may aggravate the dV/dt problem. If the conduction interval is too long so that S1, SZ, and either S3 or S4 are on simultaneously, then for some period of Buck-Derived Current Fed Converter Example Figure 11 The boost-driven circuit is even more tolerant of long conduction intervals. The conduction interval may be increased up to 50% with no effect on circuit operation. For drive circuit simplicity, 50% drive is usually used. For duty cycles beyond 50%, the primary 5·73 (a) Schematic D> 5 SI -_--G + M ......--_-'1oJ L .... S2 Auxiliary Winding Gate Drive Figure 13 D> 5 twice each switching cycle), VI =0, and there is no gate drive! 11 continues to flow, but now it goes through the integral diode-increasing the power losses. There is another drawback to using auxiliary winding drives in the quasi-square wave family of converters. Transformer winding voltages are directly proportional to input voltages and will vary with the input voltage. For example, if the gate drive voltage is 12V when the input voltage is low, then when the input voltage is doubled (not an uncommon requirement), gate voltage will also double to 24V. Except for Siliconix MOSPOWER devices, most MOSFETs are limited to ± 20V on the gate. Exceeding this level will destroy the device (Siliconix rates their gates at ±40V with 100% testing to SOY). Adjusting the winding so the gate drive is below 20V at high line may produce a condition where there is not sufficient gate enhancement at low line, thereby increasing the conduction losses. (b) Waveforms II I, ---, I I ---, v, I I Boost-Derived Current Fed Converter Example Figure 12 inductor will again limit switch current transients. In fact, in this circuit, synchronous rectifiers may be used to control output if their conduction duty cycles are greater than SO%. In this mode of operation, the output voltage is controlled by varying the conduction duty cycles of SI and S2 so that both switches are on simultaneously for part of the switching sequence. This allows the regulation function to be done on the secondary without having to couple a control signal back to the primary. This is a significant simplification. The winding voltage dependence on input voltage also increases the peak voltage seen by the rectifiers. For a SV output, the rectifier commonly sees a peak voltage of20 to 2SV, not including noise or transients. This requirement for a relatively high rectifier voltage rating (in proportion to output Voltage) means that the RDS of the MOSFET must be higher for a given device size. All of these problems may be overcome by using another circuit topology. The circuits in Figures 11 and 12 both have correct timing and relatively constant gate voltage when used with an auxiliary winding. They also subject the rectifier to a reverse voltage of twice the output voltage (lOV in SV supply) regardless of the input voltage. Clearly, gate drive timing and degree of tolerance to mistiming depend on which converter is used. The designer must take this into account when designing the drive circuits. Gate Drive Circuits The simplest way to provide gate drive is to use an auxiliary winding on the transformer secondary (Figure 13). The advantage ofthis method is its simplicity, but there are some disadvantages. For example, if this scheme is used in the quasi-square wave converter, when S3 and S4 are both off (a condition which occurs Even the best designed converter has some noise, ringing, and/or transients appearing across the transformer windings. When auxiliary winding drive is used, these transients are coupled directly into the gate where they may cause improper or mistimed 5·74 An alternative to using an auxiliary winding is to use a separate drive circuit derived from the primary switch drive circuits as shown in Figure 15. The example shown is for a quasi-square wave circuit. This drive scheme allows for proper timing of the gate drive. The advantages of using independent gate drive are several: 1. The amplitude of VGS may be optimized at a predetermined value. 2. The negative part of the drive may be eliminated, reducing drive power and gate stress. Gate Protection Methods Figure 14 3. Higher switching speeds are usually possible. turn-on and turn-off or even gate destruction. Frequently it is necessary to provide some gate protection (Figure 14). It is vital that gate protection be right at the devices with a minimum of series inductance and be capable of nsec response time. Not all transient suppressors and zeners will respond quickly enough. Notice also in Figure 14 that the source connection for the gate drive is brought out separately. This technique reduces pick-up from the high current in the source lead. Further protection can be provided by bringing the drive winding to the device as a twisted pair. 4. Gate protection is much easier. 5. Precise drive timing is easily achieved. 6. The rectifiers may perform control functions in some circuits (Figure 12). 7. In some applications, bi-directional power flow is desired. Use of a synchronous rectifier with independent drive allows bi-directional power flow [3,4,51. The most obvious disadvantage is increased circuit complexity. This additional complexity may not be great, so it is worthwhile to consider the advantages. Figure 14 also shows damping resistors (RD) across the gates. These resistors are added because drive circuit and winding leakage inductance can resonate with gate capacitance to generate a ringing voltage on the gate. Some form of damping should be used since this ringing may damage the gate or cause spurious turn-on or turn-off. The R-C network on the gate performs this function. Either series or shunt damping resistances may be used. The series resistance, however, reduces switching speed. If, by careful layout and transformer design, the ringing frequency is 1 MHz or above, a ferrite bead may be used for damping. This technique also helps to prevent high frequency parasitic oscillation. Avoiding dV/dt Problems Whatever drive scheme used, the integral diode should not be allowed to conduct. This will reduce conduction loss and eliminate diode reverse recovery current spikes. Even more important is the preservation of static dV/dt characteristics. Most MOSFETs remain quiescent with an applied dV/dt of 50V-lOOVl nsec as long as there is no reverse diode current. It is extremely unlikely for a low voltage power supply to _ even approach this limit. However, if diode current is present, the dV/dt capability may fall to a value as low as O.5V/nsec. Such rates are possible even in low voltage supplies. If a device is triggered on when the voltage is reversed, the transformer secondary is effectively short circuited and some damage could result. Thermal Design Considerations As shown in the previous section, RDS is a positive function of junction temperature (Tj). When ID is controlled by a current source (the inductor), positive thermal feedback is present. As the device becomes hotter, RDS increases which in turn increases power dissipation, and the junction temperature increases even further. For this reason, it is imperative to observe good thermal design practices. The achieva- Independent Gate Drive Circuit Example Figure 15 5·75 ble efficiency is very much dependent on the thermal design. A discussion of this subject is available in a Siliconix Applications Note [6]. lLe Equipment using cryogenic cooling has become relatively common. For the designer of power supplies to be used with such equipment, low temperature cooling provides a unique opportunity to drastically lower conduction losses. A MOSFET will work just fine at liquid nitrogen temperatures ( -196°C) and even at liquid helium temperatures (-265°C). For Tj = -196°C, RDSis20-25% ofitsvalueatTj = + 125°C. As an added bonus, heat transfer is much better because of the higher thermal conductivity of silicon at these temperatures. The switching properties are not significantly affected. If cryogenic cooling is available, it should be used. = the transconductance of the MOSPOWER transistor = carrier mobility The equations predict an increase in device performance proportional to the increase in carrier mobility. Figures 16 and 17 show the improvement in the characteristics of a VNEOO3A MOSPOWER transistor as the operating temperature is reduced from 2SO C to -196"C. These figures show that for this transistor, the gm increases almost a factor of 2, while the onresistance decreases the same amount. The operation of a MOSPOWER transistor does not depend on the injection of carriers across a junction, nor is the minority carrier lifetime a factor. As long as sufficient majority carriers are present in the source region, drain current will flow when a bias is present on the drain and voltage is applied to the gate. Carrier freeze-out in the source and drain regions does not impact device performance until the conduction electron (or hole) concentration is reduced to a small percentage of its original value. The Characteristics of a VNE003A MOSPOWER Transistor at 25"C (gm = 6.5S, ReSlon) = 56 mO) Figure 16 The main factor affecting MOSPOWER transistor operation is the mobility of the carriers as they flow through the body and drain regions. This mobility increases, so the device on-resistance should decrease. The drain current of a vertical DMOS transistor is given by IDS = Co Z VSAT (VGS - VGS (TH» (1) while its on-resistance is 1 1 The Characteristics of a VNE003A MOSPOWER Transistor at -196"C (gm = 12S, ReS(on) = 31 mO) Figure 17 (2) RDS(on)= {3 (VGS - VGS(TH» where MOSPOWER transistors are also beginning to be used in their third quadrant of operation. In this quadrant, the carriers flow from the drain to the source, opposite to normal current flow. The intrinsic body-to-drain diode is in parallel with the MOSPOWER transistor operated in this direction, as shown by Figure 18. A MOSPOWER transistor operated in this fashion has high current capability with a low forward voltage drop in one direction, and the normal breakdown voltage characteristic in the other direction. This device performance makes MOSPOWER transistors attractive for use as synchronous rectifiers. The characteristics of the VNE003A MOSPOWER transistor in the third quadrant are shown in Figures 19 and 20. These photographs are of particular interest, because of the offset voltage present when the Z (3 = TILe Co In these equations, L = the channel length IDS = the drain to source current Co = the capacitance per unit area of the gate oxide Z the amount of active source perimeter VSAT the saturation velocity of electrons in silicon VGS the gate-to-source bias voltage VGS(TH) = the threshold voltage of the MOSPOWER transistor 5-76 MOSPOWER transistor is operated at - 196"C. This offset voltage is present in Figure 17, but is more easily measured here. To demonstrate the possibilities of low voltage operation an actual power converter was built and tested. Source Gate Source HALF· BRIDGE A 5 V, 100 W Half Bridge SMPS Using MOSPOWER Transistors as the Switching Elements and a Synchronous Rectifiers Figure 21 Assuming that the majority of the power dissipation occurs in the rectifiers, the power saved by using MOSPOWER transistors in place of junction devices is given by N+ Dram Current (10) The Carrier Paths in a MOSPOWER Transistor Used as a Synchronous Rectifier Figure 18 PSA VED = 2 I LOAD [ R bulk- RDS(on) ] + (4) LOAD Voffset For a 6045 Schottky diode and the VNE003A the percentage of the output power saved as a function of IL has been calculated at 25"C and - 196"C. The results of these calculations are shown in Figure 22. This figure shows that at room temperature, a MOSPOWER transistor is a slightly more efficient rectifier at low currents, but is less efficient as the load current increases. However, at liquid nitrogen temperatures, the MOSPOWER transistor is more efficient until the load current approaches 25 amperes. As MOSPOWER transistors optimized for low voltage operation are introduced, the percentage of power saved will increase significantly. For SMPSs operating below 5 volts or greater than 100 volts, MOSPOWER transistors are particularly attractive as the output rectifiers. Below 5 volts the offset of a Schottky diode at very low temperatures results in a significant power loss. For outputs above 100 volts, fast switching pn diodes have a large offset voltage and a high bulk resistance. The Characteristics of a VNE003A MOSPOWER Transistor in the Third Quadrant at 25'C (Voffset = 180 mY, R bulk 29 mil) Figure 19 = +20 +1. PERCENTAGE OF OUTPUT POWER SAVED +12 The Characteristics of a VNE003A MOSPOWER Transistor in the Third Quadrant at -196'C (77"K) (Voffset = 460 mY, R bulk = 18.8 mil) Figure 20 +. r - +4 The 5 V, 100 watt power supply shown schematically in Figure 21 was constructed for operation at liquid nitrogen temperatures. For ease of testing, only the MOSPOWER transistors were cooled to this temperature. All other components were kept at room temperature above the nitrogen container. (The PWM 25 was used as the control I.C., but it was found to stop functioning properly at liquid nitrogen temperatures.) The MOSPOWER transistor operated as expected at LN2 temperatures. ~·CI II ~ -4 -. (25' C) -- -... --.... -r--- .............. 1-..., ............... _-12 -1. -20 ............. PERCENTAGE OF OUTPUT POWER LOST • I. 15 2. 25 The Percentage of the Output Power Lost or Saved by Using a VNE003A MOSPOWER Transistor to Replace a 6045 Schottky Diode at -196'C and 25°C. Figure 22 5-77 - It is possible to operate the entire power converter in LN2. The effect of low temperature operation on the other components is discussed in Appendix 1. MOSFET-Schottky Comparison In low voltage output power supplies, overall efficiency (Tj) is dominated by losses in the rectifiers. The relationship [7] between efficiency and the rectifier forward drop (Vr ) can be expressed by ID(rms)Reduction In a MOSFET, conduction loss (Pc) is due to RDS. It can be expressed simply as Pc = ID2 (rms) RDS Tj = 1-~ (7) ------~----- 1 + (Vr)/(Vo) (5) Where ~ is the percentage of power dissipated with the supply excluding the rectifier losses, and V0 is the nominal output voltage. Notice that it is the rms value of ID which counts. Since RDS is also a function ofID. (6) A graph of equation 7 is given in Figure 24, for several values of ~. The efficiency range for 2V and 5V outputs and for Vr = O.4V to 0.6V is also shqwn. From Figure 24, it is clear that with a low output voltage, the rectifier forward drop is a major factor in overall efficiency regardless of other circuit losses. Where a > 2. Obviously high efficiency requires that ID (rms) be as small as possible. There are practical ways to do this. One method is to make the averaging inductor larger which changes the shape of 11 and 12. Figure 23 gives examples of typical waveforms for large and small inductors. In both examples, average current is the same, but rms current is lower when a larger inductor is used. If we take the ratio of the two values and raise this ratio to the 2.5 power, the power loss difference is almost 40%! Clearly the value of the averaging inductor is critical. 100~-----+ ______-r______+-______ 8A 90~~~~~ ____ ~~ ____+-______ ~ ~ ____ ____ ~ ~ "~I I I I I I I I I I 60~--~r;-+-----+------~----~~~--~ I (b) I SA 4A -: - - - - - Vo = la\lg sv ~ Vo= '2V 3A S0r------;-------+------~------~----~ Large L - I rms = 4 04A 40~ The Effect of Current Waveform on RMS Value Figure 23 00 The rms current also depends on the topology chosen. For example, the circuits shown in Figures 8 and 11 have a lower rms rectifier current than the circuit in Figure 12, for the same output current. This occurs because of the pulsating nature of the output current in any boost derived converter. ____ ~ ______- L_ _ _ _ _ _ 01 ~ _ _ _ _ _ _L __ _ _ _ 04 ~ 05 Efficiency as a Function of Forward Drop (Vr) Figure 24 In a Schottky diode, there are other losses in addition to forward drop. The most prominent of these losses is reverse leakage current which can be substantial when the junction temperature is in the range of 100°C to 150°C (the normal device operating range). Another problem arises from the large capacitance of As previously indicated, in some cases gate drive timing may also be used to reduce I D(rms). 5-78 these diodes. Losses due to charging and discharging this capacitance are relatively small, but in high frequency (> 100kHz) inverters where the primary switches may have transition times of 20nsec or less, large current spikes may be generated. These spikes may increase dissipation and peak power stress in the primary switches. Psaved (Watts) 20 15 10 In a MOSFET, reverse leakage current is significant and capacitance may be as much as an order of magnitude lower. This reduction is a significant improvement particularly for high frequency conversion. Given the very fast transition times possible with a MOSFET, they should be usable as synchronous rectifiers at frequencies up to I MHz in switch mode converters, and at even higher frequencies in resonant converters. 0.6 o" -s -10 + IL Vos + PI (8) -- ,.....-:::::: --...... ~ ~ ROS(on)=IO ~ - RDS(ony2 Rbulk ......... 30 ~40 IL 50 (amps) RDs(on) =3 Rbul~ RbUI~ ios(on)=k~ 5 Rbulk ~ Putting a Price on Efficiency To this point, we have been emphasizing efficiency. For many applications, the decision on the device selection is based on the following economic considerations. The power lost in the MOSFET (PM) is expressed as (9) 1. Direct device cost. where the switching loss is assumed negligible. To determine which device is superior in a particular application, take the difference between equations 8 and 9. The result in terms of power saved when a MOSFET is used may be expressed as 2. Power converter selling price. 3. Life cycle cost of the system converter. On a device-to-device basis, MOSFETs have historically not looked very promising due to high prices and high RDS. However, prices have drastically decreased, and further reductions are expected. Manufacturers now know how to build very low RDS devices, so the cost gap between MOSFETs and _ Schottkies will be much narrower in the future. Psaved = I2L(rms) (RB - RDS) + IL Vos + PI ~ ~ .--...- The temperature effect on RDS, RD, and Vos and PI is also not included. RDS and RB increase with temperature as does PI, and Vos increases as Tj is reduced. Consequently as Tj is reduced, Psaved increasingly favors the MOSFET. Consider this behavior when comparing devices. where: IL = average output current I2L(rms) = RMS diode current RB = diode bulk resistance Vos = diode offset voltage PI = loses due to leakage PM = I2L(rms)RDS(on) V = RbU~ ~ Graph of Power Comparison Figure 25 The power lost (Ps) in a Schottky diode is expressed as Ps = I2L(rms)RB I ROS(on) (10) A graph of equation 10 can be used to determine which device is more efficient. If Psaved is positive, then the MOSFEThas the edge; if however, Psavedis negative, then the Schottky is better. A graph of equation 10, using typical values for RB and Vos and a range of values for RDS, is shown in Figure 25. This graph makes clear where each device is superior and shows the critical role played by RDS. A more useful comparison is the manufacturing cost of a power supply using each type of device. In this context, the improved efficiency possible with MOSFETs becomes important. With higher rectification efficiency, less cooling is required. This efficiency translates into either smaller heat sinks or (in higher power units) the elimination of a cooling fan. The lower circuit currents due to the higher efficiency also allows cost and size reduction in switches, filter capacitors, and magnetics. The net result is an overall cost reduction. There are additional factors not taken into account by the graph. As rectifier efficiency is changed, the RMS currents in the transformer windings, the primary switches and the filter capacitors will change. Most of these losses are 12(rms) dependent, and as rectifier efficiency is improved, the value for 13 will also improve significantly. Relating this to Figure 25, the zero crossing points will not change, but the degree of improvement in the areas where each device is superior will be enhanced. For telephone companies and large computer manufacturers, a third level of comparison (life cycle cost) becomes important. For these types of users, im- 5-79 proved efficiency translates into lower utility bills for both the direct load power and the power used to cool the equipment. Reduction in air conditioning loads reduces overall operating costs as well as the capital invested in the cooling equipment. In such systems, a higher initial cost for power conversion equipment is acceptable when improved efficiency reduces operating cost proportionately. Appendix 1. Operation of Other Power Converter Components at Low Temperature The Electrical Behavior of Semiconductor Devices The behavior of semiconductor devices such as diodes and transistors and of monolithic integrated circuits made up of these and other components varies greatly with temperature. A basic understanding of the effects of temperature may be gained by examining the variations of three key semiconductor parameters with temperature. These three parameters are: (1) Carrier mobility: The ease with which conduction electrons and holes move through the semiconductor crystal varies greatly with temperature. The mobility depends on the total number of impurities and the effect of crystal lattice vibrations on carrier movement. As the temperature of silicon is lowered from room temperature, carrier mobility increases as shown in Figure 26. The carrier mobility peaks between lQa'K and 20a'K, depending on doping concentration, but is typically a factor of 2 or 3 above room temperature mobility. (2) The number of dopant atoms ionized: As the temperature is reduced, the percentage of dopant atoms that remain ionized (and hence contribute to the conduction process) begins to decrease when KT approaches the ionization energy of the dopant atoms. For common dopant atoms in silicon, the temperature at which dopant "freezeout" begins is approximately 125"K, as seen in Figure 27. (3) Minority carrier lifetime: The relative position of the Fermi level and centers that control the recombination rate of carriers varies significantly with temperature. As the temperature is reduced, the probability that a trapping center will capture both a hole and a conduction electron increases, and minority lifetime therefore decreases. Clearly there are several ways to compare costs between Schottkies and MOSFETs as rectifiers. The best comparison method depends on the particular application, but a direct device-to-device comparison is rarely useful. Conclusion Changes in pricing and lower RDS make the MOSFET competitive with Schottky diodes in low voltage rectification applications. To gain the most advantage from using MOSFETs as synchronous rectifiers, the user should carefully consider circuit implementation and overall economic issues. A simple substitution of one device for anotht::r is definitely not the key to success. References [1] M.S. Adler and R.R. Westbrook, "Power Semiconductor Switching Devices - A Comparison Based on Inductive Switching," IEEE Transactions on Electron Devices, ED-29 , Number 6, June 1982, pp. 947-952. [2] M. Chi and C. Hu, "Some Issues on Power MOSFETs," PESC Record, June 1982 (392). [3] G. Cardwell and W. Neel, "Bilateral Power Conditioner," IEEE Electronics Specialist Conference Record, June 1973, pp. 214-221. 200r--l7"<~r--r--r--r--r---' [4] H. Matsuo and K. Harada, "New DC-DC Converters With an Energy Storage Reactor," IEEE Transactions on Magnetics, Volume Mag-13, Number 5, September 1017, pp. 1211-1213. 150 [5] R.D. Middlebrook, S. Cuk and W. Behen, "A New Battery Charger/Discharger Converter," IEEE Power Electronics Specialists Conference Record, June 1978. [6] R. Severns, "Safe Operating Area and Thermal Design for MOSPOWER Transistors," Siliconix, inc. Applications Note AN83-1O. [7] R. Kagan, M. Chi and C. Hu, "Improving Power Supply Efficiency with MOSFET Synchronous Rectifiers," Proceedings of POWERCON 9, 1982, p.D4. 700 The Effect of Temperature on the Mobility of Holes In Silicon [6] Figure 26 5-80 TlK) POWER transistor at 25"C, while Figure 29 shows the voltage drop of the same diode at -196"C. The photographs show that the bulk resistance (R bulk) of this diode is approximately the same at both temperatures, but that the offset voltage (Voffset) increases by a factor of two from .66 volts to 1.33 volts. This behavior results from the freeze-out of donor and acceptor atoms. As the temperature is further decreased, this offset will increase until the diode stops functioning altogether. ~nr~~~200~__~100~__~7~5________~~ INTRINSIC RANGE SLOPE· Eg SATURATION RANGE Schottky Barrier Diodes \ nl Reducing the operating temperature of a Schottky barrier diode from 25"C to - 196"C increases its forward voltage drop as shown in Figure 30 and 31. It can be seen from the photographs that the offset voltage increases by about a factor of two while the bulk resistance decreases. The decrease in bulk resistance is the result of an increase in carrier mobility at the lower temperature. However, the forward voltage drop at any current level increases as the temperature is reduced. I lOI30:-----LJ--4~--L--L---L--L---L--L---L---1 8 12 16 20 10001 T (K-I) Conduction Electron Concentration in a Silicon Substrate Doped with 1015 Donor Atoms per cm 3 [7] Figure 27 pn Junction Diodes The reduction in temperature increases the forward voltage drop of a pn junction diode as seen in Figures 28 and 29. Figure 28 shows the forward voltage drop of the body-to-drain diode of a VNE003A MOS- The Current vs. Voltage Characteristics of a 6045 Schottky Barrier Diode at 25°C (Voffset = .34 V, R bulk = 10 mO) Figure 30 The Current vs Voltage Characteristics of the Body-ta-Drain Diode of a VNE003A MOSPOWER Transistor at 25°C (Voffset = .66 V, R bulk = 43.5 mO) Figure 28 l1li The Current vs. Voltage Characteristics of a 6045 Schottky Barrier Diode at -196°C (77"K) (Voffset .61 V, R bulk 7 mO) Figure 31 = = Bipolar Transistors The Current vs. Voltage Characteristics of the Body-ta-Drain Diode of a VNE003A MOSPOWER Transistor at -196°C (77"K) (Voffset = 1.33 V, R bulk = 45.5 mO) Figure 29 Bipolar transistors operate through the injection of minority carriers from the emitter region through the base region to the collector region. The current gain 5-81 of a bipolar transistor depends upon both the injection efficiency of the emitter-base junction and the lifetime of the injected carriers as the flow across the base region. Both of these phenomena grow less efficient as the temperature is lowered, so the performance of a bipolar transistor should decrease as it cools. pacitors fabricated in the silicon substrate. The behavior of diodes and transistors over temperature has been discussed, but not that of integrated resistors and capacitors. Diffused resistors decrease in absolute value with temperature, though the temperature coefficient varies with dopant concentration. The change of diode, resistor and transistor characteristics does not track with temperature; integrated circuits specified for the commercial or military temperature range operate poorly as the temperature decreases, finally failing to function as designed. The temperature at which an I.C. ceases to function and whether the failure is recoverable upon reheating or not, is circuit dependent. This predicted performance is verified by Figure 32 and 33. The two figures show the electrical performance of a 2N6579 bipolar transistor at 25"C and at - 196'C. The significant decrease in hFE and the accompanying increase in VCE(SAT) are evident. Design of integrated circuits to operate at very low temperatures is possible; however, the performance of bipolar transistors at reduced temperatures makes them less attractive than MaS transistors for I.C. design. Table 2 shows that n-channel and p-channel MaS transistors operate to liquid helium temperatures (4.2"K). The relative stability of their threshold voltage and predictable increase in gm allow optimization of the device geometries for low temperature operation. The Current vs. Voltage Characteristics of a 2N6597 Bipolar Transistor at 25°C (hFE = 7) Figure 32 Table 2 The Characteristics of Various MaS Transistors Over Temperature [5] The Current vs. Voltage Characteristics of a 2N6597 Bipolar Transistor at -196°C (7rK) (hFE = .9) Figure 33 Other Electrical Characteristics Two parameters, device leakage and breakdown voltage, vary in a similar fashion for all of the devices discussed above. Device leakage decreases as the temperature is reduced, since this current is thermally generated. This current is an exponential function of the temperature. The breakdown voltage also decreases as the temperature decreases though not nearly as rapidly. The breakdown voltage decreases only a few percent per lOO"C. Vth (Volts) TYPE TK SD10ll Lateral DMOS n-channel 2N6661 V-groove DMOS n-channel 293 77 4.2 293 77 4.2 3408 7776 3.18 4.33 3362 7442 2783 1.15 2.54 1.82 IRDll01 Vertical DMOS n-channel 293 77 4.2 3678 7938 8712 2.65 3.91 4.17 IRD9120 Vertical DMOS p-channel 293 77 4.2 3698 6498 5408 -3.16 -3.83 -4.1 M0405 Metal Gate NMOS 293 77 4.2 42 128 149 1.1 1.7 1.4 M0405 Metal Gate PMOS 293 77 4.2 35 169 149 -0.7 -1.1 -1.8 CD4007 CMOS Metal Gate 293 77 4.2 752 576 171 2.2 2.7 2.2 CD4007 CMOS Metal Gate p-channel 293 77 4.2 907 1290 984 -1.3 -1.4 -2.0 VN30A V-groove n-channel 293 77 4.2 1048 8712 9248 0.4 2.4 1.3 ~ -- -- n-channel Integrated Circuits Both bipolar and MaS monolithic integrated circuits are made up of transistors, resistors, diodes, and ca- 5-82 Thermal Characteristics and Safe Operating Area of Components bond wire size increases because the conductivity of aluminum-the common lead wire material-increases with decreasing temperature as shown by Figure 43. The ability of electronic components to dissipate heat at very low temperatures is considerably enhanced. The power dissipation of a component is determined by the thermal characteristics of the device multiplied by the temperature difference between the power dissipating region of the component, and its ambient temperature. Operation of circuits or systems at liquid nitrogen or liquid helium temperatures multiplies the power dissipation capability of a typical device by a factor of 3 to 6. An effect that considerably enhances the power dissipation of silicon devices is its significant increase in thermal conductivity at low temperature. As seen in Figure 34, the thermal conductivity of silicon increases a factor of 10 between room temperature and liquid nitrogen temperature. Other materials including copper show an increase in thermal conductivity over this temperature range as well. Chlp/Bondwlre Limitation on Current Package Dlsslpallon Limitation iE :!. Safe Operating Area 9 E ~ U c: e c Increase in MOSFET SOA Performance Over Bipolar Transistors - due to No Thermally I••duced Secondary Breakdown Drain-source Voltage, VDS (Volts) - The Safe Operating Area of a Typical Bipolar and MOSPOWER Transistor Figure 35 10 3 Component Reliability ~ I E u f:: I« 10' ! .......... :..: V > t > i= The mechanisms that lead to the failure of semiconductor devices are characterized as having a rate of change determined by the Arrhenius equation: I 1'\ I Ii 10 R= A e -EAiKT I where u ::l a z a R A EA K T "I,si I / u j I 100 10 300 = = = = = specific rate of change constant determined by the component the activation energy (eV) Boltzmann's constant temperature in degrees Kelvin Activation energies for failure mechanisms in semiconductors have been found to range between .3 and 1.1 e V. Reduction of the operating temperature to liquid nitrogen or liquid helium levels significantly increases device lifetime when it is limited by thermally activated mechanisms. I .11 (11) 1000 T (K) The Thermal Conductivity of Silicon Over Temperature [8] Figure 34 Nature is unlikely to be too kind to the designer of a power conversion system for operation at very low temperatures. Reducing the operating temperature is likely to increase mechanical stress caused by differential expansion rates with temperature, causing a new class of failures. The safe operating area of a typical bipolar or MOSPOWER transistor must be modified when the transistor is operated at very low temperatures. A comparison of the SOA of a bipolar and a MOSPOWER transistor is shown in Figure 35. The secondary breakdown characteristics of a bipolar transistor do not allow its operation at full current and voltage regardless of the power handling capability of the package. A MOSPOWER transistor with its absence of secondary breakdown may operate at full current and voltage with adequate power dissipation. The limit set by the breakdown voltage is still present, but as discussed earlier, is reduced with decreasing temperature. The current limit set by the The Behavior of Passive Components at Very Low Temperatures The performance of each of the passive component types used in the design of an SMPS changes in its own fashion as the temperature is lowered. In this section, the behavior of passive devices is discussed and related to the underlying physical mechanism. 5·83 l1li Magnetic Components A typical power converter uses magnetic components such as inductors and transformers. To successfully design a low temperature converter the designer must know the characteristics of the core, winding, and structural materials. V/ / / ~ V. . . . Theory predicts that in a ferromagnetic material, as the temperature is reduced, Bmax will increase and in -practice this is exactly what-happens. As shown in Figure 36, as the temperature is reduced Bmax increases, rapidly at first and then leveling off as T approaches O"K. For example, reducing the temperature of a 50% Ni-Fe core from + 100"C to - 200"C increases Bmax by 18%. Core Losses of TDK H5B2 at 25'C Figure 37 /" I I V ..: IQ T.... penoIunC·q Core Losses of TDK H5B2 at -196'C (77'K) Figure 38 • l/" I / Typical Variation of Flux Density (Bm) with Temperature [3] Figure 36 Theory also predicts that the core losses will increase as T is reduced. This is due to increased conductivity of the core material and increased hysteresis losses. Again, theory and practice agree. However, the amount of increase in loss varies greatly from one material to another, as shown in Figures 37 through 42. In a ferrite material such as TDK H5B2 (Figures 37 and 38) the core loss increases dramatically. On the other hand, in the 80% Ni-Fe material (Figures 41 and 42) the increase in core loss is barely discernible. i/ Core Losses of .5 mil Supermalloy at 25'C Figure 39 If Copper or aluminum is usually used for the winding material. As shown in Figure 43, both materials have a large positive temperature coefficient, resulting in greatly reduced resistance at low temperatures. The resistance of copper, for example, drops by a factor of 13 between + l00"C and - 200"C. This increase in conductivity can be used to reduce the winding resistance and subsequent losses. One point should be kept in mind, however, for AC currents the skin depth varies as the square root of the resistivity. In a high frequency converter, as the resistivity of the windings is lowered, less of the material is conducting. Thus, the effective winding resistance does not drop as rapidly as the resistivity of the winding material. Core Losses of.5 mil Supermalloy at -196'C (77'K) Figure 40 5-84 it appears that by lowering the operating temperature from + 10erC to - 20erC, the insulation voltage stress may be increased by a factor of 2 to 5 for the same life in many film insulators. I 12.000 10.000 j 1\ ~ ~ _f-" 8000 "-...... ~"0 Core Losses of .5 mil 80% Ni-Fe at 25°C Figure 41 / 6000 "'r 4000 .. 2000 .liu ~ 6 j'-..., "~ \ -200 I -1 MIL > u ..: a -100 200 100 300 Temperature lOCI V J Temperature Effect on the AC Dielectric Strength of Type H Kapton Film [2] Figure 44 Core Losses of .5 mil 80% Ni-Fe at -196°C (77°K) Figure 42 '0' / '0' / w 3 10' V ~ 0 ~ ~ ~ ~ '0' - - .-.. ~.. - t - - - t - - - - 1 '0' 10 1 MIL Kapl0n H ,3'c 3500 VOLTS BREAK OWN / 3 _~'.L.~7_---,1~~'_ _'... 3IL'_...:.J.'Yc:... 14_---",11°C 16 1.8 2.0 ,., ,. ,.• RECIPROCAL OF ABSOLUTE TEMPERATURE 1 Resistivity of Copper, Aluminum, and Iron as a Function of Temperature [4) Figure 43 x 10 3 TEMPERATURE The Effect of Temperature on the Life of 1 mil Kapton H [2) Figure 45 For high voltage applications, the properties of the insulating material become critical. The net effect of low temperatures is to improve the electrical properties of the insulation, at the expense of the mechanical properties. The effect of temperature on the dielectric strength of .001" type H Kapton film is shown in Figure 44. We see that by reducing the temperature from + 10000C to ~ 20<1'C the dielectric strength almost doubles, a most desirable result. In a practical application, the usable voltage rating of an insulator is as much a function of its resistance to corona-induced deterioration as it is of dielectric strength. An indication of how strong a function of temperature the life of an insulating film is, can be seen from Figure 45. While the available data is certainly incomplete, The principal problem in magnetic components caused by lowering the operating temperature is increased brittleness in the materials. In particular the plastic bobbins and some insulating films can become very brittle at low temperatures. A large temperature range can also bring about problems due to the different coefficients of expansion of the various materials in the magnetic structure. These mechanical problems can, however, be overcome by careful design, handling, and mounting. Given appropriate materials, low temperature magnetic operation is advantageous, since it allows lower losses and small size to be achieved. 5-85 - An important benefit of low temperature operation in film capacitors is the improvement in voltage capability of the insulating film, as outlined in the magnetics discussion. From an energy storage point of view, low temperature operation is a big plus, since U = CV2 and the voltage capability is improved. A factor of 5 increase in V, increases U by 25 times. This is very attractive in those applications, such as pulsed loads, when large amounts of energy must be stored. Capacitors Many types of capacitors are used in power converters; some of these are usable at low temperatures and others are not. The temperature characteristics of several types of capacitors are shown in Table 3. The film and mica capacitors are very good, showing only small drops in capacitance. More surprising is the relatively good behavior of the solid tantalum types, some of which hold up very well even at 4.2"K! The wet tantalums are not usable at low temperatures due to large capacitance changes and very high ESR values. Very little information is available concerning the ESR of film capacitors at low temperatures, but we do know that the dissipation factor goes up somewhat, and that the resistivity of the foil or metalization goes down. For high current filtering applications the ESR is dominated by the metalization resistance, so that lower temperatures should result in a lower ESR. The lower ESR, coupled with the increased thermal conductivity of the capacitor body, should mean that the current rating of a film capacitor is much greater at lower temperatures. Unfortunately this is only an educated guess at the time. TYPE CeramiC MANF Corning Value 300"K I~FI 77"K 77°K 4.2"K -559 -549 -635 -£2.6 1.036 1.001 0457 0451 0387 0374 Elmenco 1 D02 0997 0997 0993 0990 0990 - 05 - 04 - 12 - 07 Film S& El 9923 9.955 9452 9.552 0309 9 444 - 48 - 41 - 62 - 51 S& El 1195 1246 1126 1176 1115 1161 - 58 - 58 - 67 - 68 S& EI 1017 1099 1012 1035 1 D09 - 05 - 58 - 08 - 65 Film (polysulfone) Film (polysulfone) While resistors are not used in the power conversion process, they are needed for the control functions. Many types of resistors exist and are readily available. The only type not suitable for low temperature operation is the ubiquitous carbon composition resistor. Besides having a large temperature coefficient, the resistance values display considerable hysteresis during temperature cycling. Table 4 summarizes the measured properties of several types of resistors. For most purposes, the metal film resistors are more than adequate, particularly at LN2 temperatures. For precision voltage dividers or similar uses, the bulk metal resistors are remarkably good, and should be adequate even at LHe temperatures. % Change fro 3000K 4.2"K Mica (polysulfonel Resistors 1027 Film (polycarbonate) S& EI 1221 '166 1170 1155 1233 Tantalum Kemet 1045 0998 0973 0909 0936 0854 1158 - 45 - 51 - 54 - 61 - 69 - 89 -104 -144 References [1] J.K. Watson, "Applications of Magnetism," Wiley - Interscience, 1980, p. 163. [2] Boeing Aerospace Co., "High Voltage Design Guide for Airborne Equipment." [3] Magnetics Inc., "Design manual featuring tape wound loops." [4] Private communications with Dick Gilbert, LSMC. [5] Private communications with Mike Dix, Staff Scientist at NASA Ames Research Center, Sunnyvale, CA. [6] G.L. Pearson and J. Bardeen, "Electrical Properties of Pure Silicon and Silicon Alloys Containing Boron and Phosphorus," Physics Review, 75, 865 (1949). [7] S.M. Sze, Physics of Semiconductor Devices, 2nd edition John Wiley & Sons, 1981, p" 26. [8] C.Y. Ho, R.W. Powell, and P.E. Liley, Thermal Conductivity of the Elements-A Comprehensive Review, American Chemical Society and American Institute of Physics, New York, 1975. [9] R.S. Kagan, M. Chi, and C. Hu, "Improving Power Supply Efficiency with MOSFET Synchronous Rectifiers," Proceedings of Powercon 9, p. D-4 (1982). Table 3 The Change in Capacitor Values Over Temperature [5] Value (Ohms) TYPE MANF Thick film Bulk Cornmg Leel Vishay metal Metal film Metal film NC55 Fit spares 0 42°K 77°K 42"K 09995 10231 1004 0999 10459 '0403 1295 1713 1927 +23 +46 +40 +296 +712 +927 9996 9974 99768 9972 99B71 -02 -02 - 02 - 01 1.0007 10015 10003 10008 10248 10361 10283 +01 +11 +10 + 24 + 35 + 28 09973 26077 09989 10031 26173 10161 +06 +04 +05 + 19 + 16 + 23 99987 Corning % Change fro 300 K 77"K 300" K 10131 1.0098 10039 26489 10217 Table 4 The Change in Resistor Values Over Temperature 5-86 5.6.1 Using Power MOSFETs as High-Efficiency Synchronous and Bridge Rectifiers in Switch-Mode Power Supplies (TA83-1) Introduction Switch-mode power supplies (SMPS) are well-known for their many features: high efficiency, light weight (and accompanying small size), and outstanding regulation. These features are principally as a result of their high switching frequency. Since the Schottky-barrier diode fails at high voltages, we are forced to consider alternate rectifiers. Heretofore, our only choice was to use fast recovery rectifiers in either the bridge or full-wave configuration, as shown in Figure I. With the recent introduction of improved pUlse-width modulator (PWM) integrated circuits capable of clock frequencies to 500 kHz and beyond, and power MOSFETs having saturation voltages superior to comparable power bipolar transistors, we must now turn our attention to the rectifiers. Historically, when high-speed rectifiers were required, if the voltage was low, say less than 30 V, the Schottkybarrier diode reclifier was the optimum choice. However, because of their inherently low peak reverse voltage rating, if our voltage was much higher we had no alternate choice but to use a fast-recovery p-n diode whose PIV ratings could be chosen to be more than adequate for most applications. Bridge & Full-Wave Rectifiers Figure 1 There are, unfortunately, two fundamental problems when using, or trying to use fast-recovery diodes in either of these configurations (Figure I). The first and major problem is that for high clock frequency SMPS applications these fast-recovery diodes are simply not fast enough! To allay any argument to the contrary, let us acknowledge that there are high voltage and high current fast diodes with reverse recovery times in the low nanosecond region. But, let us not forget that the new, high-efficiency switch-mode power supplies now appearing in the market as well as those under development are PWM switchers not high-frequency sinusoidal switchers. In other words, the diodes must rectify square waves, or at least something very close - perhaps trapezoidal. If we were to overlay the optimized SMPS squarewave output over a "typical" fast-recovery diode's conduction characteristic (Figure 2), our problem becomes apparent: we discover that we have conduction when we should have none! We have now reached a barrier where the Schottkybarrier diode and the fast-recovery p-n diode limit performance. This barrier prevents high voltage and high clock frequency SMPS design for two reasons: Schottkybarrier diodes are limited to a PIV generally below SOV; and, fast recovery diodes have excessive reverse recovery time. Low ON-resistance, high voltage power MOSFETs break through this barrier and offer the potential for higher efficiency, high-voltage switch-mode power supplies. The Problem Dermed Before we address the problem, we must first acknowledge that for low voltage, high-frequency SMPS applications the Schottky-barrier diode offers satisfactory performance as a rectifier. It is when we attempt to achieve efficient service at high voltages and high clock frequencies that the problems appear. An issue might be raised that PWM switch-mode power supplies do not deliver square waves as we find in Figure 2, but, in fact, taking into account the minority-carrier 5-87 - storage time of the typical switching bipolar transistor(s), the SMPS generally exhibIt a "dead" time. That is, as we see in Figure 3, we have a period where both the bipolar transistor's storage time as well as the reverse recovery time of the rectifying diode may recover without fear of the crowbar effect. Since we are discussing 'high-efficiency' SMPS design, we can anhcipate an output square-wave without dead time, or at least a very short dead time. Here we will discover that the wave is directly affected by a diode's reverse recovery time. In a bridge rectifier, for example, when one diode in the totem pole begins conduction, its counterpart (in the same totem pole) enters into reverse recovery (Figure 2) and for a brief period we have a crowbar. This effect is clearly seen in Figure 5. Our answer to this argument is that we are addressing high-efficiency switch-mode power supply design. Dead time seriously affects effIciency as we see in Figure 4. A Square Wave Superimposed Over the Diode Conduction Waveform Showing the Crowbar Effect of Reverse Recovery Time (t rr) Figure 2 Fast Recovery Diode Bridge Rectifier at 400 kHz Showing Effect of Reverse Recovery Time on Rectification Waveform Figure 5 , - ~ Our second problem involves the voltage drop across the rectifier. A bridge results in two (2) dIOde drops, as shown in Figure 6, whereas a full-wave rectifier has but one diode drop. Again, our efficiency is affected to our detriment. r-- The Typical Output Waveform of a Switch-Mode Power Supply Showing Dead Time Figure 3 CLOCK 10 EACH OUTPUT 10 I 1 MHz 250 KHz 2 MHz 1 500 KHz 300 KHz 200 KHz 1500 KHz 1 1125 KHz 1 250 KHz 150 KHz 100 KHz I~OMHZ ~ '" b i Output (Positive) Waveform Superimposed Over Sinusoidal Input Showing a 1.2 V Two-Diode Drop (Bridge Rectifier) Figure 6 w ~ :::l ... ..."o ... "- :::l :::l Enter the Power MOSFET .. Resolving Problem #1 W III II) Because of the market penetration of power MOSFETs, many of us are familiar with their outstanding features which we need not review. All we need to remember is that power MOSFETs exhibit no minority-carrier storage time. :::l OUTPUT PULSE WIDTH ~,.) Cr' MAX DUTY CYCLE Dead Time Affects Usable Pulse Width Figure 4 5-88 the channel current heretofore excited by the gate bias potential. A clearer understanding of this phenomenon is shown in Figure 9. This statement does, however, require qualification. When we categorically state, "no minority-carrier storage time," we are, in fact, referring to the basic MOSFET, assuming no parasitic elements. Intrinsic to every power MOSFET is a base-drain p-n diode which is, indeed, a parasitic element often considered in many applications as a "beneficial" diode (Figure 7). As we continue our study of synchronous rectification, we perhaps need to be reminded that any p-n diode will exhibit minority-carrier storage time which, in tum, will result in a finite reverserecovery time. N+ Drain Current (lD) Simplified Third Quadrant "Output" Characteristics Figure 9 The Cerrier Paths In a MOSPOWER Transistor Used as a Synchronous Rectifier Figure 7 Before moving on we need to pause to reflect on why we need to understand third-quadrant operation. We are, in effect, planning to replace the rectifier diode with a power MOSFET. We need to review the electrical schematic of a full-wave rectifier, shown in Figure 10. Consequently, if our commission is to use power MOSFETs as rectifiers we must somehow avoid activating this parasitic body-drain diode. Now that we have "set the stage" so to speak, let's review some perhaps not-so-familiarpower MOSFET characteristics. Anoda Cathode ...~ m + -I ! ~ 1_----------, o· It . ;" i I_----------------~~i ID :0 (,) '! Q Anode ,.. c Cathode g.= ~----------------------~g Full-Wave Diode Rectifier Figure 10 ~ I Here we have a pair of rectifier diodes in common-cathode connection. Note the polarity of the diode pair: anodes tied to the a-c source, cathodes tied in common to output a positive potential. If we envision the electrical symbol of the power MOSFET and superimpose this symbol in lieu of the rectifier diodes of Figure 10, we discover that our power MOSFET is installed "backwards," that is, we have the source tied to the a-c source and the drain outputting the d-c, as shown in Figure II. Drain-source Voltage First Quadrant Output Characteristics Figure 8 MOSFET Characteristics The classic first-quadrant saturation characteristics of a power MOSFET, shown in Figure 8, are generally wellknown. However, as long as we have a gate bias enhancing current flow, the first quadrant characteristics are also duplicated in the third quadrant! In the familiar first quadrant (Figure 8) the ultimate operational limit is breakdown voltage. Third quadrant operation differs in that here we discover our operational limit is when the "parasitic" body-drain diode enters conduction and 'captures' If our intent is to have the MOSFET act in lieu of the diode, we now must synchronize the MOSFET's tum-ON with the positive,going a-c cycle and tum-OFF when the a-c swings negative. Furthermore, we must never allow the parasitic p-n body-drain diode to participate. If we do, its reverse-recovery time will crowbar the other (MOSFET) rectifier. Remember, we're rectifying the output of a 5-89 - I current before we reach Vf -- forward voltage turn-ON of the parasitic body-drain diode. Figures 12, 13 and 14 provide typical characteristics taken from three popular power MOSFETs. r-________~SO~u=r~c~e_t,:~._~D~ra~i-n------~----o+ Source Drain MOSFETs as a FUll-Wave Rectifier Figure 11 high-efficiency SMPS square-wave with little or no dead time. We'll focus on how to synchronize the MOSFET later. Resolving Problem #2 Siliconix inc. Type VN64GA "Third Quadrant" Output Characteristics Superimposed Over Forward Diode Breakdown Figure 12 Interestingly enough, the solution of our first problem is also the solution to our second problem! Once we remove the diode we no longer have a dIode drop. We do, however, have an IR drop, and it is here where we must now focus our attention. The power MOSFET shown in Figure 12 offers a 60V BVOSS and a nominal rOS(on) of 0.4 Ohms at a drain current of lOA. The topology is V -groove double-diffused MOS. Selecting the Power MOSFET If, indeed the IR voltage drop is a problem needing resolution, it most certainly is if we expect to use power MOSFETs to resolve Problem #1. There is only one way for us to prevent turn-ON of the parasitic body-drain diode: we must maintain an IR drop across the power MOSFET below Vf - the forward voltage of the diode. Not only do we need a low IR drop across our power MOSFET (which sImply means we need an ultra-low rOS(on», we also need to select a MOSFET whose breakdown voltage ratings suffice to withstand the peak inverse voltage (PIV) that we will expect from our SMPS output. We are now approaching a paradoxical problem: as we seek ultra-low roS(on) power MOSFETs while simultaneously seeking a reasonably high breakdown voltage, we may discover that our costs get in our way! The relationship between roS(on) and breakdown voltage is: 25 rOS(on) -- k BV . International Rectifier Type IRF130 "Third Quadrant" Output Characteristics Superimposed Over Forward Diode Breakdown Figure 13 Consequently, the only way to achieve low rOS(on) is to increase the area of the semiconductor chip which, in turn, forces the price upward exponentially! The IRF 130, whose characteristics are displayed in Figure 13, is rated by the manufacturer at 100V with a typical roS(on) of 0.14 Ohm at a drain current of 6A. The structure is a vertical double-diffused MOS (VOMOS). The characteristics shown in Figure 14 are for a VNE003A VOMOS structure rated at 100 V with a typical roS(on) of 0.035 Ohm at a drain current of 60 A. We are able to interpret these data by remembering that we wish to pass as much current as possible WIthout exceeding Vf - the turn-ON voltage of the intrinsic parasitic body-drain diode. For all three illustrations, the turn·ON Since, as we learned earlier, the third quadrant output characteristics duplicate those of the first quadrant, we do have a reasonably simple means to select suitable power MOSFETs from the plethora of power MOSFETs available. All we need is a curve tracer, such as the Tektronix 576. By superimposing the first quadrant output characteristics over the reverse diode's forward characteristics, we, in effect, can duplicate the critical parameters from which we then can make a suitable selection based on both breakdown voltage and maximum permissible 5-90 p-type material, we discover that for an equivalent COS(on) p-channel MOSFET our costs are considerably higher than for its n-channel equivalent (with the same voltage rating). The Circuit The basic synchronous bridge rectifier circuit using both n- and p-channel MOSFETs follows that of the diode bridge much like we did for the full-wave rectifier shown in Figure II. The circuit is shown in Figure 15. [] Siliconix inc. VNE003A "Third Quadrant" Output Characteristics Superimposed Over Forward Diode Breakdown Figure 14 voltage, V f, lies close to - 0.6V. Consequently, we can make some reasonable approximations of the maximum current that each of these MOSFETs IS capable of handling (at 25°C). For the VN64GA (Figure 12) 2A; for the IRF130 (Figure 13) 4.2A; and for the VNE003A (Figure 14) > 20 VNE003A (Figure 14) > 20. In a practical sense we can dismiss the VN64GA as Schottkybarner diode rechflers are easily capable of handl!ng considerably more than 2A and withstand 60V. Were it not for the high standoff voltage of the IRF-130 (Figure 13), we might dismiss it as well. The VNE003A (Figure 14) offers us a little more, but, again, if it were not for the 100V rating, it, too, might be dismissed. Synchronous Bridge Rectifier Using n- & p-Channel MOSFETs Figure 15 The operallon of thiS MOSFET bndge rectifier is quite straight-forward. At the half-cycle when the upper rail swmgs pOSitive the gate bias on FETs Band 0 is also positive and the gate bias on FETs A and C is negative. Since FETs A and Bare n-channel, only FET B turns ON. However, since FETs C and 0 are p-channel, only C turns ON. With PETs Band C, ON current flows with the right terminal positive. Likewise, when the lower rail swings positive the gate bias on PETs A and C is positive; the bias on FETs Band o is negative and PETs A and 0 tum ON. Current continues to flow in the same direction as before, and we have gone through one cycle. We should by now recogmze the fundamental limitation of today's power MOSFETs: too high rOS(on)' But, on the other hand, we must not lose sight of the I!mltation of the Schottky-barrier rectifier diodes, as well as the limitations of the so-called fast recovery p-n diode. If we begin our examination of this bridge rectifier by Synchronous Bridge Rectifiers Using Power MOSFETs first applying a smusoidal input and observing the output from both the positive and negallve terminals with respect to one rail we obtain a waveform as shown in Figure 16. Setting aside our quest for low COS (on) n-channel power MOSFETs, let's turn our attention to the basic bridge rectifier (shown m Figure 1) and recall that the diode bridge recllfier suffers from a 2-diode drop (see Figure 6). If this bridge consisted of Schottky-barrier diodes across we might attain twice the normal voltage rating seemg that we use a totem pole of diodes across the rails. On the other hand, using conventional fast-recovery diodes, voltage is secondary but we're again troubled when rectlfying high efficiency SMPS square waves with little or no dead time. If we could implement a quad array of MOSFETs using low COS(on) n- and p-channel devices, we could escape the limitations of breakdown voltage, as well as offer high efficiency, because of the lack of minority-carrier storage time which is inherent in all MOSPETs. Again, of course, we're strapped with the COS(on) problem inherent in today's MOSFETs and especially with pchannel devices. Because of the reduced mobility of Output Waveforms of Synchronous Bridge Rectifier Figure 16 5-91 - We originally faulted the diode bridge rectifier for having a 2-diode drop, which regardless of current generally amounted to at least 0.6V per diode and perhaps more, depending upon the rectifier used. For MOSFETs, our voltage drop is dependent upon rOS(on} and current flow; in other words, the classic IR drop. Consequently, it is definitely to our advantage to use MOSFETs with the lowest ON resistance. In both Figures 17 and 18, the output current was 1.2 A into a pure resistance load. The total TOS(on) of the nand p-channel MOSFET pair was 0.6 Ohm for a total voltage drop (at 1.2 A) of 0.72 V which accounts for the slight 'thickening' of the trace in Figure 17. Because of the present limitation of p-channel rOS(on), as the load current increases we can expect a corresponding increase in the voltage drop. The output waveform, showing both positive and negative swing for a square-wave of 250 kHz is shown in Figure 19. The slope of the positive wave was the fault of the pulse generator used for driving the MOSFET bridge. (Compare Figure 19 with Figure 5.) We can obtain a better appreciation for the diode drop effect by a simple experiment using the synchronous MOSFET bridge. We first observe the output (positive for this experiment) with the input waveform superimposed. Because of the limitations of laboratory equipment we were forced to go to a 60 Hz line to obtain worthwhile current (the functIOn generator simply was incapable of outputting current). The effect is noticeable if we compare Figure 17 with Figure 18. In Figure 17, we have the bridge operating as a quad MOSFET; but in Figure 18 we have removed the gate drive to the MOSFETs causing the bridge to rely entirely upon the intrinsic body-drain diodes for rectification. The forward voltage drop is readily apparent in Figure 18. Output Waveform Showing Both Polarities with 250 kHz Square-Wave Drive Figure 19 Synchronous Full-Wave Rectifier Using Power MOSFETs The synchronous full-wave rectifier, shown in Figure 11, depends upon low rOS(on) n-channel power MOSFETs as the rectifier elements. For this illustration we will implement the VNEOO3A whose characteristics are shown in Figure 14. Output Waveform (Positive) MOSFET Bridge Rectifier Figure 17 To synchronize the MOSFETs we must tum-ON the gates with a gate-to-source voltage of at least +1OV to ensure optimum conductance. In a SMPS we are able to add "tickler" windings to the secondary windings of the output transformer to accomplish this, as shown in Figure 20. The Parts List for the SMPS shown in Figure 20 is as follows: R1 R2 R3 T1 5.6k 75k 56k see text R4 R5 R6 10k 7.5k 3.6k CI C2 C3 C4 QI, Q2 VN0600A Q3, Q4 VNEOO3A PWM25 - SilicoDix Pulse Width Modulator IIC Output Waveform (Positive) Body-Drain Diode Bridge Rectifier Figure 18 5-92 0.01 0.001 5uF 470uF + ~--------------------~ R3 15 R1 ~Q1 L1 t-------' + Switch-Mode Power Supply Using Synchronous MOSFET Rectifiers Figure 20 Transformer Design, Tl Undoubtedly the transformer output stage represents the major design problem for most SMPS designs. Although this lies outside the general scope of this article, a few words should suffice to give us a more comfortable feeling. Aside from the secondary winding we have a pair or'tickler" windings that provide the necessary gate voltage to 'synchronize' the gate turn-ON. The transformer has an Indiana General E-core #8031-1. Over a nylon bobbin we fIrst wind a 16-turn pnmary consisting of 8 strands of #30 AWG enamel (Litz wire) over which is wrapped a copper fOIl acting as a Faraday shield. The secondary has a total of 28 turns of #24 AWG enamel with both a center tap as well as addItional taps at ±12 turns which provide tickler windings of 8 turns each. With a pnmary of I OV /turn and a secondary of 3V /turn, we have a transformer turns rallo of 1:3.33. Output Waveforms of Tickler (Upper) and One-Half Secondary (5 VDIV) with Direct Drive from SMPS (Figure 19) Figure 21 In Figure 21 we are able to view the output waveform of one tickler and one-half of the secondary (from centertap). We see that the tickler winding supplies 12.5V of gate potential - adequate for complete turn-ON of the VDMOS synchronous rectifier. We are now ready to attach the VNEOO3A (Figure 14) to this secondary. - Another view of interest, shown in Figure 22, is the output from both secondaries of the transformer where we see the 1800 phase reversal common to all center-tapped secondaries. Feeding both VNE003As, we exit through suitable filtering at a fixed 5 V at lOA. In our experimental SMPS we were power limited by our laboratory supplies used for primary power. Nonetheless, from Figure 14, we can anticipate a reasonable current before the intrinsic body-drain diodes tum-ON. We have intentionally left the effects of temperature upon performance until last. As our operating temperature in- Waveforms Across Secondary Figure 22 5-93 +1 07 Reverse Breakdown u; ....... 0 2S'C G ~ 7S'C a: 0 w to O.6V I -E "" "" " "" " 05 ....... 03 0 a: Z ;0: 0 "w.. Other Radiation Damage -60 C 0: III -80 -90 Both ionizing and neutron irradiation will cause other parameter shifts such as lower gm. Since in most cases. the shifts are small and represent second order effects. we have chosen to ignore them in this discussion. At very high levels ofirradiation(>1 MRad(Si) or lOIS neutrons! em'), these other effects may not be second order. Unfortunately at this time, very little test data is available at extremely high irradiation levels. Device C 4D0 V -70 300Y o L 1~O .L 2~O 1 ~ 4~Q I I 5~O I 6~O 1 7~O I 8~O I g:O:OO:-L:-!;:;:-'--:-! DDSE [krad (sl)] BVoss Shift with Radiation Figure 14 © 1983 IEEE ref. #10 Strategies to Minimize the Effect of Radiation Damage Several strategies may be employed to minimize the effect of MOSFET radiation damage on circuit operation. The first and most obvious is to employ shielding. In a terrestrial application, like a nuclear plant, the addition of lead shielding for the instrumentation is quite practical. In a space application, however, large amounts of shielding are out of the question because of the weight yet some degree of shielding is usually possible. The second strategy is to employ devices specifically hardened for radiation. Many changes are possible in MOSFET design and processing which will improve the radiation resistance. The feasibility of devices with reasonably stable characteristics up to 10 MRad(Si) has been demonstrated (3). It is interesting to note that some of the first generation power MOSFETs, (which are no longer in production), were much more resistant to radiation damage than today's standard products. VOS=20 V ~ w -1 ." -. 60 V Z __==:::::::==---40 V l: U w -3 ~ ~ -4 OV g Z -5 g -6 "~ 0: III -7 Device 0 150V -8 -9~~~~~~~~~~~~~~~~~ 100 200 300 400 500 600 700 DOSE (krads) 800 Figure 15 900 1000 1100 © 1983 IEEE ref. #10 Siliconix has begun development of radiation resistant devices which will be available in the future. It should be kept in mind that the graph shown in Figure 16 IS representative of the change in R OS(on)' However. there can still be large variations in the actual shift seen in a particular device. The trend is clear: The higher the voltage rating. the greater the susceptibility to neutron damage. Until such time as "rad hard" devices are available, the most practical strategy is to design the circuit so that changes in device characteristics do not degrade circuit operation. 14 / 12 10 / ,..--------DEVICE A 450 V ~ DEVICEB / / 17 ~ >-"'- DEVICEC 150V Pre-Rad . 5x 10 ~ '\. 10 NEUT/CM2 Plot of ROS(on) VB Neutron Fluence Figure 16 © 1981 IEEE ref. #2 5-105 As was shown earlier, there are four distinct characteristic changes which must be accommodated: Vth shift, R OS( on) increase, BVOSS reduction and photo-current turn-on. One or more of _ these may occur in the same application depending on the irradiation scenario. Vth shift is essentially a gate-drive problem. To maintain proper operation, the Vgs applied to the gate of an n-channel device must be sufficiently positive (> + 10 V) to tum on the device fully before irradiation and yet negative enough (2-5 V below the final Vthl to tum off the device after the maximum irradiation, allowing for device-to-device variations. In practical terms, this means a drive waveform such as shown in Figure 17 must be used. One advantage of the negative bias during the off interval is that it reduces the shift in Vth at a given total dose. The exact amount of reduction at a given total dose would depend on the bias values and the duty cycle. Figure 18 gives an example of the effect of bias conditions on the shift in Vth. In this example it can be seen that even though the gate drive duty cycle is 50 % the shift in Vth lies much closer to the - 10 volts OC bias curve than to the + 10 volts bias curve. To obtain an accurate value for the shift, test devices should be irradiated with the actual circuit voltages, currents and duty cycle applied. The use of negative bias, while very effective in maintaining normal circuit operation, does bring with it some problems. In the circuit shown in Figure 19, for example, Vgs can reach - 30 V. Most MOSFETs are only rated for ± 20 V except for Siliconix parts which are rated for ± 40 V on the gate. The gate to source breakdown voltage can become a limiting factor in the design. +10 -10 -20 +10V - -30 --------------- Variation { in Vlh ~~----+_--------+_----t Actual Gate Waveform Figure 19B ------------_______ ~::::::::::;::::==;-' -10V - Of'.! OFF Gate Drive Waveform Figure 17 Another problem in some circuits is how to couple the asymmetrical (from a volt-second point of view) waveform given in Figure 17, to the gate in a transformer isolated circuit. 35,-----~------~------------~----_, in 30 ~ ~ 25 w 20 §! 15 ~ . If a power converter circuit is turned on and kept on during irradiation, the negative bias voltage can be self-generated. I n the pre-irradiation off-condition, the switches will be off. The bias is not needed to hold off the switches nor for starting. lfhowever, the converter is turned off after a high level of Irradiation, the bias voltage will disappear, and the switches will be on. If the bus power is still applied, the converter will be a short circuit across the bus. There are two ways this may be avoided. First the power bus could be disconnected before turning off the converter. This is usually done with a mechanical relay. If the converter is to be turned back on, the negative bias must be applied first. The second method would be to supply a rad hard bias supply which is always present. The bias supply would still have to be interlocked to a bus disconnect relay in case of failure. The degradation in BV DSS may be circumvented by using a device with an initial BV DSS higher than the normal circuit operation required. Another step would be to minimize the voltage across the device during irradiation. There are a number of topological means for doing this in power converters. For example, instead of using a parallel (or push-pUll) converter circuit, a half-bridge circuit could be used, reducing the voltage across the devices by a factor oftwo. :;: ";!... Vo = HOY JlJ100 kHz 9 0 l: f3 a: -1DV 10 j!: However, both ofthese schemes bring a penalty: RDS(on) will be increased unless larger devices are used. If neutron radiation is also present, the use of a higher voltage device will exacerbate the increase in R DS( on) due to neutron damage. YG = -10V 0.1 0.2 0.3 05 OA Total Dos. [Mrad (sl)] Photo-current turn-on is an easier problem to solve. To prevent damage, the current in the device must be limited to a safe value. In a power converter, the simplest approach is to use a circuit topology which inherently limits the current even when all switches and diodes are in conduction. An example of such a converter circuit is given in Figure 20, and many other circuits of this type exist. In some circumstances however, using this type of topology may not be enough. The problem arises from the turn-on of the parasitic BJT. The circuit shown will limit the current to the normal switch current, but this may be too high for the BJT, which does not normally carry any of the switch current. Second breakdown may then occur. Very short pulses (<100 nsec) may not be damaging, but longer pulses may destroy the FET. One means to eliminate this problem would be to deliberately turn on both FETs during the pulse interval so that much of the current is diverted through the FET channels. The Effect of Gate Bias on Vth Shift Figure 18 © 1982 IEEE ref. #6 NEGATIVE GATE BIAS EXAMPLES PWM Drive ] + ~SI 20V VI ; II + 10V - I 82 [ Negative Bias In a Converter Figure 19A 5-106 A not her protective scheme would be to place a BJT, as shown in Figure20, to shunt the current. This device is shorted from base to emitter and plays no role in normal circuit operation. It is assumed that the shunt BJT is capable of absorbing the normal switch current without failing. shift in a given device at a given Irradiation level IS strongly dependent on small variations in processing, the specific operating conditIOns dunng irradiatIOn, and the character of the radiation source. Wide vanations in test results for the same type of device done at different times or In different facilities is unfortunately typical of radiation testing of all semiconductors. One word of caution, not all "current fed" converters are self protecting. For example, the circuit shown in Figure 21 will have very high switch current due to the photocurrent in the diode. If high levels of irradiation are anticipated and there IS doubt concerning the adequacy of the deSign the best course of action is to install deVices, from the same lot as those to be used in the flight equipment, in the actual circuit-then irradiate them while the circuit IS operating. The total shift in Vth may be greatly reduced in long life, relatively low irradiation missions by operating the FETs at elevated temperatures (125 to 1400 C) to accelerate annealing. Obviously higher operating temperatures compromise reliability therefore this technique must be applied judiciously. Conclusion The increase in R DS( on) due to neutron damage is essentially a thermal problem. The power dissipated (PT) in the FET is proportional to: PTa 12 D(rm,) RDS(on) The electncal characteristics of power MOSFETs are altered by radiation. The degree and type of charactenstic change depends on the type, intensity, and duration of the radiation. In general, the effect of changing characteristics can be circumvented by proper Circuit design. Successful power converter designs have been demonstrated for total doses greater than 200 Krad(Si). When radiation hardened MOSFETs become available, circuits capable of surviving total doses approaching ten Mrad(Si) should be practical. (I) The junction temperature (TJ) may be expressed as. (2) Where: = ambient temperature Ta Reja = thermal impedance from junction to ambient. Clearly the MOSFET is suitable for use in high radiatIOn environments. As R DS( on) increases, Tj , will increase. The effect is, however, not linear because R DS( on) is also a positive function of Tj so the increase in R DS( on) due to radiation is magnified. The thermal system has positive regeneration and can go into thermal runaway if R DS( on) becomes too high. This dependence and the determination of thermal stability are treated in detail in a Siliconix Application Note (4). We recommend that the designer read the papers hsted In the bibliography to obtain a more detailed understanding of radiation effects in power M OS FETs. There are several things that can be done to minimize this problem: I) Use the lowest voltage MOSFET consistent with the circuit requirements. In some cases, the use of series low voltage devices may be helpful. The direct series of several devices is not usually attractive from a circuit point of view, but there exist(5) power converter circuits which automatically divide the voltage across several switches. I n these topologies, the use of lower voltage devices is quite practical. 2) Use a device with an initial RDS(on) much lower than the power level requires. If one device is not adequate, several can be paralleled. 3) Minimize the ambient temperature. 4) Minimize I D(rms)' In power converter circuits, this can be accomplished by making the averaging inductor larger or by using alternate topologies (4). In particular, the family of converter circuits which includes that shown in Figure 19 are very useful (5). 5) Minimize Reja' This may be done by using a lower impedance heatslnk, a non-isolated device mounting to the sink, parallel devices (lower effective Reja)' and in general, good mounting practices. Radiation Activated Crowbar Examples Figure 20 Unsuitable Current Fed Converter Example Figure 21 Acknowledgements Several of the figures used in the text were derived from the work of others: In a practical design, one or more of these techniques may be used to arrive at a satisfactory solution. Figures 2, 3, 4, 10 and II Figure 12 Figures 13, 14 and 15 Figure 16 Figure 18 Some Thoughts on Radiation Testing The radiation test data shown in earlier sections is, for the most part, typical. However, the data from some devices, even of the same type, can be very different because the degree of parameter 5·107 Reference I Reference 9 Reference 10 Reference 2 Reference 6 - References 6) D. Blackburn, et. al., "Ionizing Radiation Effects on Power MOSFETs During High Speed Switching," IEEE Trans. on Nuclear Science, Volume NS-29, No.6, December 1982. 7) W. Baker, Jr., "The Effects of Radiation on the Characteristics of Power MOSFETs," Proceeding of Powercon 7, 1980, p.3. 8) S. Rattner, "Additional Power VMOS Radiation Effects Studies," IEEE Trans. Nuclear Science, Volume NS-27, 1980. 9) S. Seehra and W. Slusark, "The Effect of Operating Conditions on the Radiation Resistance of VDMOS Power FETs," IEEE Trans. Nuclear Science, Volume NS-29, December 1982. 10) Blackburn, Benedetto and Galloway, "The Effect of Ionizing Radiation on the Breakdown Voltage of Power MOSFETs," IEEE Trans. Nuclear Science, Volume NS-70, No.6, December 1983. 1) H. Volmerange and A. Witteles, "Radiation Effects on MOSPOWER Transistors," IEEE Transactions on Nuclear Science, Volume NS-29, No.6, December 1982. 2) D. Blackburn, et. aI., "VDMOS POWER Transistor DrainSource Resistance Radiation Dependence," IEEE Transactions on Nuclear Science, Volume No. 28, No.6, December 1981. 3) G. Roper and R. Lowis, "Development of a Radiation Hard N-Channel Power MOSFET," IEEE 20th Annual Conference on Nuclear and Space Radiation Effects, July 18-20, 1983. 4) R. Severns, "SOA and Thermal Design for MOSPOWER Transistors," Siliconix Application Note AN83-1O. 5) R. Severns, "Switchmode and Resonant Converter Circuits," International Rectifier Application Note, 1981. 5-108 Applications Information . . I Chapter 6 Applications Information 6.1 Power Supply Applications 6.1.1 High Frequency Power Conversion with FET -Controlled Resonant Charge Transfer Abstract The author discusses FET-controlled, high frequency, sinusoidal, power conversion. An off line multi-output power converter with output power exceeding 250 watts up to 500 kHz has been demonstrated. System operation is such that current flow occurs as successive packets of charge made from individual sinusoids of current. The resonant charge transfer process where switching loss is independent of frequency is described along with FET circuit implementation. lower component loss and reduced component stress. Also there is no voltage or current overshoot. Resonant Charge Transfer (RCT) Figure 1 shows a diagram of the power-train for an RCT converter. Operation is as follows: Filtered AC is converted to DC between (160-250) V. FET Ql and Q2 are alternately turned on for a fixed period of 6 /LS but with a load-dependen~ variable PRF. The primary of the power transformer T is connected to the common point of QI and Q2 and in series with the resonant circuit consisting of L I and C3 + C4. Diodes D3 and D4 constrain the voltage excursion across C3 and C4 thereby stabilizing the resonant tank. Introduction Pressure to design cost effective reliable switching power supplies in smaller space points to high frequency operation. Further, the thermal impact on component reliability requires that supplies have higher efficiency which implies reduced switching loss. The secondary sections of T are auto-connected to give best cross-regulation and the main +5 V output is filtered and fed back (Vsense) to control the _ switching PRF of QI and Q2. Power conversion employing square waves has a fundamental disadvantage, vis-a-vis sinusoidal operation, because squarewave operation requires that the power switch (or its associated snubbing components) dissipate energy whenever (each time) voltage and current are handled (interrupted). Therefore, switching loss is directly related to the operating frequency; which is not the case using sine waves. Low voltage differential series-pass FET regulators are used to regulate the auxiliary outputs. A separate low power transformer is used to supply logic voltage but only during turn-on. After the system is up and running the rectified + (13- 15) V secondary voltage is fed back to the input of a + 5V regulator chip in the bias supply. This is done not only to improve the system efficiency but in addition to allow the logic system to be fed through the converter to utilize the energy stored on CI and C2 to improve hold-up-time after loss of the AC input. This paper presents a method that uses resonant charge transfer for DC to DC conversion. Resonant charge transfer gives low switching loss because each sinusoidal wave of current is allowed to terminate before the voltage forcing function is withdrawn. As a consequence, with resonant operation, the controlling switch turns both on and off at zero current to give Reprinted by courtesy of PCI, April 1983 Proceedmgs 6-1 SERIES RESONANT TANK AC REGULATION AND SURGE CONTROL 5W c, '60 '""\..., 25•• AUTO SECONDARY -(14-17) Y \ II c. II '.W II At POWER 250 W OUTPUT 1BDW EFFICIENCY 72% II '.W RCT Converter Pseudo System Diagram Figure 1 FIXED EH "" 2 E-N5 V +~o---~----------------------, Ip .. EH vr1/4 POWER SA I I ..•• .. I. '2 I G.• 5•• 3.G 2.G "., ,I.. RUN--.. G. E~_~~ W -5 PIN 750 550 360 200 I I I I I I I I I I I I I I I I I 1"'6p.8~ Po (MAX) 420 375 260 '50(80) '2' I __ ~ __ ~~~~ ____ D =1 I :~:I I w=nVi:C -ECo----4----------------------~ M A X _ '25 NORMAL.,. MIN----.. HOLDUP .... FULL POWER 'Om I POWER. EiPrI I I n = 72 " Resonant Waveforms Figure 2 6·2 - _ . FULL POWER Figure 2 shows the current waveforms for the resonant tank. Relevant operating values are obtained as follows: the capacitive input Pi-filter, V(A) and V(B) have the wave shape indicated. At 10 A output current the I/LH choke has a current variation of ±0.5 A. Assuming a minimum operating DC bus voltage of E= ±SO V and that the junction of the two 0.05 /Lf resonating capacitors is at -SO V, then when FET S + is turned on a sinusoidal pulse of current will flow. The peak of the sinusoid is equal to 6 A. This is because the reflected voltage across the primary winding of the 14 to I turns ratio transformer is about SO V, and therefore, the voltage head EH for the resonant loop is also equal to SO V (the effective primary loop inductance including reflected secondary leakage is = IS /LH). At full power output S+ and S- are alternately triggered at 6/Ls (W+ D) intervals and the 4 /Ls sinusoids are separated by 2 /LS intervals (D). Under this condition the average current is 2.5 amperes and the power drawn from the DC source is 200 watts. In order to control the output voltage at V(B) is compared to a stable reference voltage such that when V(B) goes below the reference the one-shot multivibrator (OS) is triggered. The OS produces a 6 /LS (fixed width) pulse which retriggers the primary power switches. Accordingly, a new packet of charge is added to the 15 mf filter input capacitor whenever it is required (up to a maximum PRF equivalent to 6 /Ls). This control strategy is termed fixed-pulseadaptive-variable-PRF because the PRF automatically adjusts to compensate for input DC bus variations, as well as load changes. This discontinuous format, where the control loop gain is zero between pulses, is quite stable because the 6 /LS pulses that drive the primary switches are inverted and fed back to the reference side of the comparator. This assures that each pulse "uncrosses" the comparator input. ®, At the maximum DC bus voltage of 250 V (E= ± 125 V) the voltage head is 170 V which gives a 12 A peak pseudo-sinusoid pulse of current with a linear fall rate of about 4.5 A//Ls (SO V + IS /LH). With 12 A pulses the maximum average current flowing in the resonant tank is now about 6 A and the power taken from the DC source is 750 watts. The measured output regulation is 1 mViA (Ro= 1 mil) from zero to 16 A. Also, it has been found that by adding a feedback path from V(A) to the reference side of the comparator the output impedance Ro can actually be made negative. The reason is that with V(A) feedback, the current flowing through the input resistance in the filter choke causes the average value of V(A) to increase. Thus the output voltage is a stable positive function of load current. One last item, with 5 /LS sinusoids (100 kHz) the 1 /LS choke has an impedance of 500 mil. This is sufficient for effective voltage filtering yet allows an output current slew rate of 1.0 A per mS per mV (very good transient response). RCT Control Figure 3 shows how the RCT converter is controlled. The resonant primary sinusoids are transformed and rectified to give approximately SO A 5 /LS (nominal width) current pulses. Using the values shown for II AC_ 2mO 10mn (t/4e = 1 :.ymv) OIJA_r\ --'-+-~fIIV-"'VIB) { 250mV 1 mU'--- STATIC IDA mS mY --DYNAMIC System Waveforms and Control Figure 3 VeAl : I I I I CHOKE I I I I I I I'I ~ I I 6-3 \- ~ I FEED BACK ! VARIABLE PRF (\ !lli! AI = 1 OA CONTROL FIXED PULSE ADAPTIVE I mF -I5J'8~ f--oV(A) ___ I(I.mo) I I I 'Iii tiN '" 10 mV ~ I VIB) -VREF - I FET Regulator Signal.SD, controlled from under/over voltage (uV/ o V) circuits, which are not shown, serves to tum off the two series-pass PETs and crowbar the 4.3 V output. When low, SD turns off the regulator. When SD goes high the regulator will tum on, provided the output current is below IL. In the future the FET will find wide application in the design of low voltage DC linear regulators. Figure 4 shows an example of a very low drop self-protected switch for an isolated 2 A output. Two individual SO m!l n channel PETs are connected directly in parallel and controlled by shut down signal SD which is obtained from a logic chip with open collector output. When SD is high the two PETs conduct current with a roS(on) of about 40 m!l (at 100'C). The maximum gate to source voltage is set by the Zener diode to give current limiting. Note that the PET type and Zener voltage can be selected to give current limit (IL) at the temperature stable point of the FET transconductance. When SD is Iowa third PET, used as an output shunt, clamps the output terminal to ground. The nonlinear connections to capacitor C2 and to the gate of the crowbar PET serve to ensure that when SD changes state the crowbar PET turns on after the series-pass PETs tum off and turns off before the series-pass FETs turn-on. Capacitor C introduces a small delay which provides a transient over-current capability. The regulator configuration of Figure S is simple (mainly three PETs and one LM324 chip), has low drop, and is flexible and functional in design (Le., additional FET units can be paralleled to give higher current). Further, when using n-PETs for positive voltage regulation or p-PETs for regulating negative voltages, the basic regulator loop is unconditionally stable and gives good static regulation (= 0.2S AI p, s- m V). The regulator loop is unconditionally stable because the series-pass PETs are used as a source follower (voltage gain < 1.0) yet they have high frequency response (even at low drawn-source voltage) and therefore the LM324 amplifier provides the low frequency dominant pole. Figure S shows an example of a low drop, low output impedance, high current FET regulator. The design provides for an isolated +4.3 V output with a current limit at = 11 A. Two low voltage SO mn PETs are connected in parallel and their source voltage is compared to REFV. Feedback through amplifier A (type LM324) controls the FET gate voltage to give an output regulation of = 1 mY/A. In order to obtain a current limit function the output of A is also fed back through B. Accordingly, when the PET gate voltage exceeds REFI, the voltage level of the REFV input to A is reduced. The values for REFV and REF{ are set to current limit at about II.S A. Also, REFC is set such that the negative going output of B "trips" C to crowbar the output at a level just above current limit. The reliability of FET low voltage regulators should prove quite high; the power components have low internal voltage stress, the PET has inherent ability to handle large short duration power peaks, and for DC regulator application large device leakage currents REGULATED INPUT +500 V o----+..----+--. +492 Y G +12 +12 REGULATED OUTPUT ~r-~----------~~~~2~A vo-'VVI.---+---+---fCl-i I 'uv FEEDBACK TolD 25OC-'/1..-100"C ~I • SIMPLE -FUNCTIONAL • STABLE IL - - - - - - - Low Voltage FET Switch Figure 4 6-4 ~:~o-------~-----r--~ r~~-+--~----------------------~---QI~~P~ I I , I I I G TO UV/OV SENSE t -.......M-o REFy CROWBAR REFI TURN-ON DELAY w------~--~--~ :1: \'"~ .~~""" LM324 REF • FLEXIBLE ·~~~~I~::~NSE 0 1- -FET STABLE • REG 1 mY/AMP RELIABLE STABLE LOOP Low Voltage FET Regulator Figure 5 are pennissible. In fact in "test regulator circuits" the FETs have been run so hot "the leads tum blue" with no perfonnance degradation. AC input-to-DC bus control is accomplished using a conventional SCR half-bridge with a perhaps unconventional but flexible SCR controller. The control method is shown in Figure 6. Surge Protection; Feedforward Phase Control Rectifier Control For an input sinusoid of AC voltage a priori amplitude infonnation is not available. Never use the conventional zero crossing time delay method for SCR trigger if it is necessary to isolate AC surges for the DC bus; instead, use a post-peak level-recross logic system where AC surges are automatically eliminated. The control system operates as follows: The goals for the power supply using RCT are shown in Table I. From the outset it was appreciated that this is a challenging specification especially for volume production. The design requires low power component stress, and AC surge control is mandatory. Negative AC sinusoidal loops from the secondary of the bias transfonner are used as input AC reference _ signals (the positive loops are distorted by the +5 V I~ic load) and inverted to give positive AC loops at ®. The AC waveform at is then co~ared to a DC reference level to give wavefonn \gJ. When the ISD signal is high wavefonn @ causes the SCR to be triggered at the trailing (rising) edge of @. Noise protection is provided by setting the values of Rand C so that insufficient trigger energy is available to the SCR below a minimum width of waveform Table I Resonant Regulator Specification Vin {(80 - 150) Vnos' 200 Vrms surge (160 - 300) Vnos' 400 Vrms surge eEl © Po: 180 W; ± 12 V, ±5 V, +5 V (16 A), +4.3 V (II A) Regulation: ±50 mV (total Matic + dynamic) Hold Up Time: 30 mS, +5 V (16 A) B & W: All Standard, Remote Sense, Sequenced Turn On/Off, Self Protecting, u V/o V Clamp @. Size: 254 in3 (.147 ft 3) © The reference level at is adjusted by the peak synchronized squarewave @ where the resistor values are set to allow the SCR to fire just after the peak Reliability: 5 yrs. Cost: minimum 6-5 • SCRTRIGOER ' " CON::l':nOC GAIN FA~II I I I I I ZERO CROSSING ~~t--.!!!!.t ®, r ®A?TVn-r--=-"'1 1 -1I I REF@) I I 1+5VI I I ® aior-, r! r;:..r--tHi \V I I I I I 160 V rmll-.l L __ .J L __ --I : ....I t==i ~==::J 90 V rms -1 I---; r---t 80 V rmll.-i---J L.......J AC AMPLITUDE DET AND~ I AC Surge Control Figure 6 when the AC input is between 80 Vnns and 90 Vnns . This is done to give maximum DC bus voltage at low AC line. resonant conversion should allow much higher operating frequency than will square wave operation. Finally, because the output of a phase control rectifier is sensitive to amplitude dependent voltage slope (dV/dU; the trigger point is adjusted upward as the input AC voltage increases. This is accomplished by detecting the average AC ~ak amplitude and adjusting the reference level at (£Y. The 324 integrator also gives a soft start function at "Power-up". 2. Reduced component stress. In low power systems (say less than 100 W output) component count may be a meaningful, perhaps dominant measure of reliability. However, in higher power ranges, especially when operating in harsh environment, component stress is dominant. The resonant mode, operating without current discontinuities, has little voltage overshoot, much reduced di/dt, and requires much less snubbing compared to square wave operation. Conclusions and Recommendations Several authors have written excellent papers regarding the do(s) and don't(s) of high power, high frequency design so this subject is not discussed here. It suffices to say that the selection of magnetics and filter capacitors are important as is circuit layout and grounding. However, the following items should be emphasized. 3. Use field effect transistors. In applications below 500 V and 50 A the PET bipolar race is about over; the PET is fast, more rugged (where it counts, i.e., SOA), more efficient and cost effective. Indeed, for sinusoidal operation the simple low cost proportional drive long used with bipolar power switches is unavailable. 1. Sinusoidal operation at high frequency is an important way to reduce the size of power supplies. The ease of design with FETs, their speed, voltage-activated low power drive requirements, unifonnity and stability now allows them to be an item of commerce (almost anyone's equivalent type will work without circuit tweaking). Resonant operation, where the sinusoidal current pulses are allowed to naturally tenninate, greatly reduces switching loss in the power handling components, especially in the power switches and power diode rectifiers. Accordingly, in the future 6-6 4. Use FETs for low voltage linear regulation. However, the trend is clear; the PET switching speed is quite adequate at 1 MHz sinusoidal operation, as are film capacitors. Low rDS(on) gives low voltage drop without saturation. The resulting high frequency response at low voltage coupled with the ease of drive, ability to parallel devices, the stability and uniformity of electrical parameters (especially transconductance), make them ideally suited for low voltage regulator applications. In the future the Gallium Arsenide FET technology offers potential for factors of 5 to 10 improvement in both speed and rDS(on). If this materializes, coupled with superior high frequency magnetic material such as Metglass, then sinusoidal operation in the 1.0 - 5.0 megahertz range appears practical. 5. Technology. For higher power systems, resonant charge transfer (where current flow naturally terminates) is compatible with the SCR switch. The RCT system described has been operated with 1 JLs sinusoids (it did not work as well as with 5 JLS sinusoids-the magnetics require redesign). 6-7 6.1.2 Practical Desig~ Considerations For a Multi-Output CUK Converter © 1979 IEEE. Reprinted, with permission, from PESC '79 IEEE POWER ELECTRONICS SPECIALISTS CONFERENCE, June 18-22, 1979, San Diego, CA, pp. 133-146. Abstract An experimental high frequency three output DC-DC converter design is presented in circuit detail, emphasizing the practical design needs of its contemporary optimum topology (t:UK) output stages. Power component selection criteria are also given along with suitable load protection methods against output voltage reversals at turn-on. Inductor coupling criteriafor ripple current reductions at input/output ports are developed including an alternate method for external tuning inductance insertion. Results of corresponding empirical evaluations of a 200 kHz, 55-W representative design are discussed. yielding maximum performance. The current work to date has been spearheaded by a team of researchers at the California Institute of Technology who, in 1977, revealed their fmdings [1], to the design community. The topology was appropriately termed optimum as it achieved all the desired goals stated above. Since 1977, further extensions [2, 3, 4], modeling methods [5, 6J and practical applications [7, 8, 9] have been suggested by the developers of the new topology which now make it an even more viable and attractive circuit structure for power conditioning designs. It is the intent of this paper to present a practical application of many of the features of the optimum topology (CUK) converter, including multiple outputs, isolation of input/output grounds and coupling of output filter inductances. Section 2 contains a short review of the basic topology operation and evolution of extensions for the reader's benefit. While total output power control achieved is less than 100 watts, the design presented does demonstrate the compelling simplicity of the topology and its many advantages. 1. Introduction This decade has seen many significant advances in the art of power conditioning system design and contemporary electronic component technology. In the area of DC-to-DC conversion methods, the designer now has LSI components at his disposal for converter control, amplification, and supervisory functions. Yet, with all the current progress made in DC power system design, the main power translation stages have remained relatively untouched. This lag can be easily attributed to the need for this part of a DC-to-DC network to control relatively large amounts of power to perform its function. Consequently, the main power conversion stages must be formed from discrete active and passive circuit devices that contribute significantly to the total design's complexity, size, reliability, and power loss. Because of its promise of significant and controllable current ripple reduction at chosen circuit ports, a three-output CUK converter power stage was included in an experimental pulse-width modulation system undergoing evaluation for high-frequency operation under an in-house R&D study program. It must be emphasized that the resultant total system design to be described herein does not represent a truly optimum network from power loss or bandwidth standpoints, as the main goal of the study was design information and education for system practicality and producibility. Nevertheless, it was proven that it is feasible to For these reasons, a great deal of effort has been expended on the search for a DC-to-DC power stage topology that has the simplest possible circuit structure with the minimum number of components while 6-8 utilize the CUK topology in converter applications requiring switching frequencies approaching 200 kHz with predictable circuit responses assuming proper layout and noise prevention practices [10] are followed. average current transfer ratio magnitudes for each of the circuits of Figure 1 are simply (continuous inductor currents assumed) 7jD I-D Perhaps the most important achievement of this particular design is the simultaneous reduction of input and one selected output port ripple currents to zero, utilizing tightly coupled inductor windings and small external inductances for ripple current adjustments. From a system design standpoint, this implies no need for EMI filtering for switching current noise at the input to the converter. In addition, no output filter capacitance for ripple voltage reduction is necessary at the selected output port. = 7jD =.!.!. D' ,D' =I - D (1) 12 where D is the duty cycle of conduction of transistor QI with respect to a constant timing period, TS, and 7j is the converter circuit efficiency. Section 3 presents the details of the total power conditioning system, including a somewhat unusual ramp slope control method of pulse-width modulation. Section 4 is devoted to power stage component selection for proper ratings and electrical values. In Section 5, the problem of output voltage reversal with power application is explored when input and output inductors are magnetically coupled, along with simple preventive circuit measures. (a) Basic Inverting Topology with Nonpulsating Input/Output Current Waveforms C1 Ripple current projections in a four winding inductor assembly are considered in Section 6 with emphasis placed on achievement of predictable coupling coefficients to increase the effective inductances of selected windings for current ripple reduction. This subject is continued in Section 7 where it is demonstrated that the desired ripple current reduction can be accomplished by selection of small external inductances working in conjunction with tightly-coupled multi-inductor components. (b) Coupling of Input/Output Inductances (Single Core Construction) (c) DC-Isolated Extension with Separated Coupling CapaCitance Laboratory evaluations of a representative 200 kHz converter are presented in Section 8 as verifications of the analytical predictions and circuit responses given in earlier sections. 2. Background (d) Coupled-Inductor, DC Isolated Extension The operation of the basic CUK converter stage h~s been covered in excellent detail in the references [I through 4]; however, for those not familiar with the topology, it is worthwhile to briefly review the fundamental design features and extensions. Circuit Evolutions of the CUK Converter Figure 1 Capacitor CI serves as the single energy transfer device between the input and output ports of the circuit in Figure I(a). During the interval D'TS when QI is OFF, diode D is forward-biased and CI is charging in the positive direction through inductance Lp. The voltage across the collector-emitter junction of the transistor is therefore positive and can be turned ON for the subsequent interval DTS. As soon as QI turns ON, CI becomes connected across the diode, thus reverse-biasing it. Thus, during the time DTS, Figure I illustrates the evolution of the new converter topology from its basic form (Ia) to coupling of input/output inductances (lb), introduction of transformer isolation (Ic), and fmally, recoupling of isolated input/output chokes (ld). The principal electrical features of all of these converters are nonpulsating input/output currents as shown graphically in Figure I(a). It is easy to demonstrate that the voltage and 6·9 Cl discharges through the load RL and inductance Lo, charging the output capacitance C2 to a negative voltage. Circuit operation is repeated when interval D'TS is reached. of the topology [4]. As shown in Figure l(c), the energy-transfer capacitor is simply broken into two parts, Cp and CI, with an isolation transformer separating the two halves of the circuit. Since no average or DC voltage can exist in the ideal sense across either transformer winding or the two inductances, the voltage on Cp is VQ and that on CI is V. Note that the sum of these two capacitor voltages is VQ + V = VQ ID' = VID, the same potential as that across the single coupling capacitance CI of Figures lea) and (b). Because inductances are present on the input and output lines, the currents are nonpulsating with no sharp transitions that contribute to increased EMI as are present in conventional buck and boost designs. Output voltage magnitude can be less than, equal to, or greater than the input voltage value, depending on duty cycle as implied by (1), thus achieving true generallevel conversion. Since both windings of the transformer in Figure l(c) are isolated by the two energy-transfer capacitors, no DC transformer core magnetization can take place. Automatic volt-second balance is therefore achieved in the topology, requiring no special magnetic or circuit designs for balancing, as might be the case in a conventional "push-pull" converter. A smaller ungapped, square-loop core can be used for the transformer as a result of this circuit feature, with lower core and winding copper losses than would be possible with comparable converter topologies, as discussed in length in [ 4] . The first extension of the converter topology to come to light was the feasibility of coupling of input and output inductances [2], as illustrated in Figure l(b), without impact on the basic DC-to-DC conversion property. Examination of the ideal voltage waveforms across Lp and Lo reveal that they are identical in magnitUde and timing, as diagrammed in Figure 2. Therefore, with proper choice of coupling coefficient and turns ratio, both inductances could be wound on a single core resulting in obvious reductions in converter size, weight, and component count. It has been shown, in fact, that significant reduction in ripple current magnitUdes can be achieved due to the magnetic coupling between the chokes if the turns ratio and coupling coefficient maintain specific mathematical relationships [3]. DC bias effects on the core material are, of course, additive because of the required phasing between windings. This fact must be taken into account when selecting the induction core material to prevent saturation due to DC magnetization effects. Because the basic converter operation of Figure lea) is unchanged from that of Figure l(c), the desirable feature of inductance coupling is still possible, as shown in Figure led), reducing the number of circuit magnetic assemblies to two. The extension to multiple and isolated outputs [4] should now be obvious, as shown in Figure 3 for a three-output design. Again, by coupling of circuit inductances on one magnetic structure, only two magnetic assemblies are required for the total power stage. However, one must judiciously choose the coupling coefficients and turns ratio relationships be- The problem of an inverted output not isolated from input ground potential was solved by a later extension V,- --,-----,-- -------T I-----~-;;---l <'--II I r---------, 1 V1-Vc-~V2+t,=VJ! 1L _________ J !------'I-I 1 L V,-Vl=V,-O'=-o'v, I I' I - - - - - -11f----...;- - - - - - -1----,> ~ I:----OT. "'~!-----T. Ideal Lp, Lo Voltage Waveforms for the Circuit of Figure 1a Figure 2 6-10 1 _ _ _ _ _ _ _ _ _ _ -.l +5 V, + 15 V, and -15 V DC, with corresponding maximum current capabilities of + 5 A, + 1 A, and -1 A DC, respectively. Since the +5 V load was the highest and desired tolerance, the lowest of the three outputs, the + 5 V output was chosen for converter pulse-width modulation (PWM) control with the ± 15 V lines controlled by cross-regulation through the converter transformer secondary turns ratio relationships. tween windings in order to steer and reduce ripple currents in the directions chosen for design needs. Transformer turns ratios are not restricted to 1: 1, but the ideal transfer voltage relationship specified by (1) must be modified to include the transformer turns ratio factor. For example, for the second output V02 in Figure 3, (lID ) V02 - = n2 X - - , n2 = NsZlNp (2) V£ I-D One further observation about the topology of Figure 3 is needed. Note that the primary and secondary coupling capacitances have been relocated to the other side of the respective primary and secondary transformer windings in contrast to those shown in Figure l(c) or l(d). Because the capacitances are transformer coupled and isolated by T1, they can be placed on either side of their respective winding with no change in circuit operation. Since the cases of electrolytic capacitors are usually common to their negative terminals this placement effectively grounds the cases of these capacitors, thus reducing the high frequency radiated noise due to the pulsating switching currents in these capacitors. Figure 4 is a schematic of the overall converter system, with each functional area identified. Like its CUK output power stage, the PWM control system is somewhat unique with respect to its control method. Because currently available PWM LSI integrated circuits do not use this control and isolation approach, SSI logic and discrete parts were employed. The system as shown consists of an error amplifier, individual clock and ramp generators, voltage comparator, amplification and buffer stages for correct gate drive levels for the power VMOS converter switch. Isolation between input/output grounds is achieved by allowing the error amplifier, which is powered by the + 5 V output, to interface with the ramp generator control through a high speed optical coupler. A simple shunt regulator, consisting of a temperature-compensated reference diode (VR3) and bias resistor (R4) provides the single regulated voltage needed for all remaining PWM Controls. The input + 28 V is used as the unregulated voltage source for this low power regulator. 3. Experimental Circuit Designs In order that the results of the development study of the CUK converter operation and its control electronics could be applied to representative production program needs, a three-output configuration was selected, each isolated from one another and from the input DC power ground. Voltage levels were set at Lp r--_ _ _~--------f'rrYYY""----,.----o+v, D'"" 1-0 " N., 01 +V02 ....2 No> DO N., n1=Np + N", C2 "2=Np n3= - ~3 Np N03 Tl D3 - C3 + Three-Output, DC Isolated, Scaled Version ofthe CUK Converter (Coupled-Inductors) Figure 3 6·11 IDII ERROR AMPUFIER ,..---.------.--~-__t"-+5 V(sENSE) +28V r----o +28V Lp +28 V RETURN \7p ,..-------fYfl"'1-----'----<> +28 V INPUT _ _--IT'-----'T]' TT,--..-...-...,..---o +15 vee D4 {.!..!,1f-~_ _ _ __'____'L--+___o+15VRETURN '--.--..---0 +5 '91f-~---HI_-'----JL-----o +5 VDe vee RETURN '-l11Z-'--------+----'----o -15 V RETURN C3 CUK POWER STAGE Exper]menta] Converter System Figure 4 ramp slope control method is diagrammed in Figure 5 for duty cycle adjustment. 02, Q4:a YN1206N2 TO Lp UIA, another Schmidt trigger gate, in conjunction with Rl, Cl, U2A, and diode CRl, form a very simple 200 kHz astable oscillator for fixed-frequency PWM synchronization. When the output of UIA is in a low state, U2A discharges both the oscillator capacitor Cl and the ramp capacitor C2 through diodes CRI and CR2 respectively, until the lower input voltage threshold point of UIA is reached. UIA's output then goes to the logic one state, allowing these capacitors to recharge. D .-'-~! Rae = RUM = 100n r + The output of the system comparator, UlB, is buffered and inverted by the remaining four Schmidt triggers within Ul, all connected in parallel, for lower output impedance drive through CR4 for rapid charge of the gate capacitance of the power stage VMOS device, Ql. This ensures fastturn-on ofQl to minimize switching losses. U2D discharges the stored charge in the gate capacitance of Ql when the driver gates return to the logic zero state concurrent with the discharge of the ramp capacitance, C2. Alternate Design Approach for Converter Power Drive Figure 4A The PWM operates as a fixed frequency, variable + 5 V potential is detected by the error amplifier which adjusts the lightemitting diode (LED) current in the optical coupler, OC-I. This current change alters the emitter current of the light sensitive transistor within OC-l changing the base voltage bias of the ramp control transistor, U2B. This action, in turn, changes the slope of the ramp voltage appearing across capacitor C2, causing a corrective shift in time when this ramp voltage reaches the fixed high level input voltage threshold of a CMOS Schmidt trigger inverter gate (UlB), designated as the comparator for the PWM system. This OFF time system. A change in The error amplifier itself is a conventional design with U2C as a buffer for current control of the LED within OC-1. VRl is a low voltage (1.23 V) reference diode selected for stable temperature characteristics with low bias current. Variable resistor R8 is used to remove output voltage variations due to initial component tolerance within the control loop. 6·12 - - - - - COMPARATOR THRESHOLD j - - _ j -_ _ _-, +10 V VG(Ol) tON tOFF DUTY CYCLE = - = 1 - - : = : 0 tOFF Ts CONTROL I °l~---~--~ I Ts I 1 :.~-----T'", -----l.~: Fixed-Frequency, PWM Converter Control Concept Figure 5 Three diodes in series (CR5, CR6, CR7) clamp the ramp control transistor current level to a fixed maximum value at converter input power application, thus limiting the duty cycle of drive to QI to prevent excessive power dissipation from high inrush currents. These diodes, along with CR8, also provide a path for discharge of capacitance C5 in the lead-lag frequency compensation network for the converter on input power removal. Resistor Rl3 is the companion component in this compensation. removal controls. Note that an additional winding (Tl-FB) was added to the power transformer to aid in rapid tum-on and saturation of Q1. The position of the winding in the source of Q4 also increases the effective VGS (ON) of Q4, thus increasing the available base current for Q1. The lower VMOS FET (Q2) turns on when Q4 is commanded off and removes the stored charge in the B-E junction rapidly through its low ON resistance. Resistance RUM and RBE provide for current limiting in the drive circuitry when the voltage across TI-FB reverses as a result of QI being turned OFF to prevent possible upset andlor damage in the controlling CMOS logic. Capacitors C3 and C4 are small noise filter capacitors for the bias regulator. A small ferrite bead on the gate lead of QI reduces high frequency noise problems due to gate drive. A suppression zener diode clamp (VR2) limits the tum-off transient voltage magnitudes across the drain-to-source terminals of Q I to safe levels. Switching losses in this alternate buffer and power control method are limited primarily to those due to Q 1. If a square loop core material is used for Tl, one must ensure that the DC imbalance produced by this non-capacitively coupled winding does not produce saturation. This scheme for the power switch of the converter system is very attractive for switching frequencies in the 40 kHz range should one choose to reduce the converter frequency of operation. The configuration of the CUK power stage shown in Figure 4, including component rating considerations, are the subjects of Sections 4, 5, and 6 to follow. 3.1 Alternate Converter Power Switch 4. Power Stage Component Selection The limited number of vendor suppliers of high current VMOS power FETs with low drain-to-source resistance plus their current high costs may prove to be uneconomical in some high-volume or militarized power system applications. Lower power VMOS is currently more available at a proportionally lower cost. Because the CUK power stage and its components were the key to an optimal converter design, much _ emphasis was placed on a proper understanding of the component values and ratings needed to achieve reliable and predictable operation. In our early experiments with the breadboard of the multi-output converter, we used an alternate design in the area of buffer stage and power control. This alternate scheme is shown in Figure 4A. A highfrequency power transistor (2N6277) is used in place of the high current VMOS (Q1 in Figure 4) and lower current VMOS devices used as base drive and In the matter of the energy transfer capacitances, because they are asked to transfer the entire power in AC form from input to outputs, the rms ripple current capability of these parts is a prime consideration. This subject was covered in [4] and [8] for single output CUK converters; however, the results can be used to predict the needs for a multi-output situation. Referring to the scaled and triple output 6-13 design of Figure 3, ripple current needs for the four energy transfer capacitances (Cp, CI-C3) can be estimated to be VQl (OFF)=Vll+ Vol =V,,+ V02 nl " n2 =y, + V03 II n3 (3) iCI (rms) = 101 In a similar fashion, reverse voltage levels appearing across the three secondary commutating diodes are _/Y02 iC2 (rms) = 102 (4) V~ where s again is the secondary number (1,2, or 3). (5) V~ The peak current level in QI is the sum of the average line current, Ill, and the reflected secondary load currents. 3 iCp (rms) = L nsics, or 3 IQl (ON) = 1£ + s= I y:;iVi x los, In terms of output voltages, (12) can be restated as 3 IQl (ON) = V02, VC3 = V03 IFDs (ON) = DTS Vllns 1] los (14) s= 1,2,or3 Since the output filter portions of the converter of Figure 3 are essentially that of a buck regulator, inductance and capacitance values for L o l - Lo3 and Co l - C03 can be formulated from standard formulae [11] based on ripple current and voltage needs for each output. Ripple current reduction by inductive coupling between the input and output chokes of Figure 3 will be considered in Sections 6 and 7. Like the output filter networks, the design of the isolation and scaling transformer (TI in Figure 3) can follow conventional techniques. For operation at high frequencies, ferrite toroids are recommended for the small core areas and low loss. Winding techniques for leakage inductance reduction are mandatory to reduce transient voltage spikes across semiconductor junctions during circuit transitory periods. Choice of turns ratios are based on desired limits of duty cycle variations with line and load changes, stress limitations on the surrounding semiconductors and energy transfer capacitances, and, of course, cross-regulation needs for the unregulated outputs. (8) where Pll is the total converter input power, and III is the average input current at that power level. Similarly, for the secondary transfer capacitances, 100~ [~+ 7j Cp> Cs > (13) II Forward current stress levels in the secondary commutating diodes is related to the corresponding secondary load current by the following relationship. Capacitance values of these parts are chosen to keep their voltage ripple magnitudes to reasonable values to minimize OFF voltage stresses on QI and the secondary commutating diodes. A good first approximation is I % of the corresponding average voltage stress for ripple voltage peak-to-peak magnitude. For example, for capacitor Cp in Figure 3, using the basic expression ill = CpdV/dt, IllDTS , or 0.01 Vll P£ DTS Cp> 100 2 V£ L [:~s +ns] los s=1 (7) = (12) s= I VCp = Vll' VCl = Vol, VC2 L nslos s= 1 (6) 3 L V ns Vos iCp (rms) = _1_ (11) VDs (OFF) = Vos + ns Vll _/Y03 iC3 (rms) = 103 (10) (9) Vos2 where s is the secondary number in question (1, 2, or 3). Peak OFF voltage Q 1 of Figure 3 is simply the line voltage magnitude plus the reflected secondary capacitance voltage of TI. 6·14 Even though gapping of the core material is not required in the ideal sense, as mentioned in Section 1, rapid load demand changes or sharp excursions in line voltage may produce transient conditions such that core movement into saturation is feasible. One practical application [8] did experience such situations; therefore, precaution must be exercised in evaluating the need for a gapped magnetic core for T1 in light of the intended converter application and dynamic input/output electrical specifications. by the time constants and magnitUdes of the power stage impedances and output load values. Figure 7 suggests some solutions to reversal protection for loads and output filter capacitors. In Figure 7(a), a blocking diode is placed in line with the secondary inductance to ensure a proper undirectional current path for steady-state output current, but prevents reverse current flow at turn-on. However, its presence does add to the power waste in the converter during normal operation. Figure 7(b) adds an output clamp diode to limit reverse transient potential to less than a volt, but does not conduct during normal operation. Use of a Schottky diode here is recommended due to the gray areas presently in prediction of damage thresholds for ICs or polarized filter capacitors. 5. Transient Output Reversal In eUK converter designs where magnetic coupling of input and output inductances is desirable for ripple reduction, one undesirable feature of operation is introduced; namely, that of transient voltage polarity reversal on power application. For systems where short term reversals of outputs could produce damage to output capacitances or loads (e.g., monolithic ICs), this phenomenon must be circumvented or reduced to acceptable magnitudes. The solution of Figure 7(a), while lowering converter efficiency, may be more attractive when the problem of transient currents in Tl producing core saturation is considered as mentioned in Section 4. There may be more sophisticated methods for reversal prevention; however, the two noted in Figure 7 seem to remain the simplest found to date. Figure 6 is a diagram of this temporary reversal for a single output C:UK converter with transformer isolation and coupling between input and output chokes. Inrush current through Lp due to first tum-on of Ql or by charging of the primary energy transfer capacitance Cp when VQ is applied produces a secondary transient current in the direction shown in Figure 6. This direction is opposite to that of normal current flow in converter steady-state operation, and results in a reversal of output voltage polarity for the transient time period. 6. Ripple Reduction by Inductor Coupling The proportionality of the two inductor voltage waveforms of the circuits of Figure l(a) led in [2] to the idea of inductive coupling and to the subsequent coupled-inductor extension of the CUK converter shown in Figure l(b). At first thought, the equal amplitUdes of the inductor voltages implies a need for l: 1 turns ratio only (or Lp = Lo for perfect coupling). However, in [3], it was shown that there is really no need for such restriction and the coupling of inductors may be achieved at any inductor values. In fact, proper choice of the relationship between turns ratio of self inductance and the coupling coefficient can result in This condition will persist until the potential levels of Cp and Cl reach values to counteract the voltage across Lol produced by the coupled primary inductance voltage. The reversal period will be determined .-------------. I INRUSH CURRENT (Q1 OR Cp) L ______ /- ~ / I I ~~~~~-~_Lp • +Vo I r------------.., I PRODUCES CURRENT IN I L_~~~~~~'~~~~_.J illustration of Output Reversal on Turn-On Figure 6 6·15 ADD BLOCKING T1 ~ I~ DIODE L., RL1 ., C, + Vol D' ~-~--~--------------~--~--~ .~[--.-:-+-c:;_~~~:f~D'~:~_"'_'_~~~~t~:-Co~'~f_R~L'~f~---D_C~~~·~Suggested Methods of Protection for Output Polarity Reversal on Turn-On Figure 7 zero current ripple at either input or output ports of the circuits of Figure l(b) or l(d), as dramatically demonstrated in [3] for a single output design. where Lp, Lol, L02, and L03 are the self or opencircuit inductances of the windings, and the various M's represent mutual inductance values between the four windings. We now define effective turns ratios (no 1--' n03) and coupling coefficients (kl--' k6) as In our case, however, the problem of ripple current steering and reduction is magnified due to the presence of more than one secondary inductance and the corresponding complex interrelationships between turns ratios and coupling coefficients. However, this problem is simplified if a first-order model, such as that shown in Figure 8, is utilized for analysis As shown, all windings are mutually coupled (M's), and the assumption is made that the primary and secondary voltages are related to the primary potential by proportionality factors a, b, and c. In the design of Figure 4, these factors would be the secondary tum ratios of Tl, or a = nl, b = n2, and c = n3, assuming an ideal transformer model for Tl. Proceeding with the voltage matrix for the model of Figure 8, we find ~ vPJ ~LP avp bvp cvp = Ml2 Ml3 M14 A... lIP no I = V "La!' A...!LP Uo2 = V Lo2' A" lIP n03 = V Lo3 ' (16) Ml3 M23 L02 M34 V1 = avp '13 First-Order Inductor Model for Ripple Current Predictions Figure 8 6·16 Z:::CYp Substitution of these definitions into the matrix of (IS) and solving for the various current derivatives will then allow us to solve for each winding's effective inductance value in relation to its self-inductance. After a few lines of algebra and the aid of Cramer's rule, dip _ vp di2 bvp di3 cVp I NEGATIVE NEGATIVE POSITIVE POSITIVE POSITIVE POSITIVE NEGATIVE NEGATIVE c0 0 3 kS> aOol @) b00 2< k2 "°0 1 kS> c003 k'S ::::::> COUPLING COEFFICIENTS"" 1(ALL WINDINGS) First-Order Inductor Model with External Inductances Figure 9 6-19 , , nol = , no2= ftp , , n03 = V~ LpL02 ' -k3 k3- ~P~02 where ~p = Lp + Qp, ~ol = Lol + Ql, ~02 = L02 + Q2, and ~03 = Lo3 + £3. Repeating the voltage matrix and solution for current rates, the effective inductance expressions for the four windings become the same equations as (18 21), except of course, for replacement of all k, n, and L symbols with primes as indicated in (23) above. For the condition bn~2 1<.'2 = I and ~l = cn~3 1<.'5 (30) when L' efp 00 and L' efsl- 00. Substitution for prime values as defined by (23) into (30) and solving for the external inductances yields substitution of the values from (23) into (24) shows that Q2=b~ -L02 (25) £3= still must be satisfied within the multi-winding inductor itself to reduce the effective inductances to the following simplified equations. (I - ki2) ~p (23) ~P~03 A case matrix similar to that of Table 2 can be prepared using (26) through (29); however, that case concerning itself with zero input and zero output ripple on the first secondary is of direct interest to this work. This situation according to (26) and (27) above should occur for (24) LCfp = ~PLo3 --, [:J~ for k2, k5 = (31) (32) -L03 1 (tightly coupled windings). Since the relationships of (26) and (27) do not include Lol or Lp in their denominators, then we can set (26) 1- bn'02 ki (33) (1 - kS2) Lefsl = 1_ , [ , 1,' cn03, AS anol JLol (I - ki2) ~02 J and still satisfy the conditions to allow and Lefsl ---. 00 • (27) , (1 - kS2) L [an'01 k5 03 J 00 Referring back to (24), it is mandatory that this condition be completely satisfied, as the contribution of small differences from zero can produce large changes in effective inductance predictions using (26) through (29), as can be seen by examination of the basic relationships of (18) through (21). Since it was proven in (25) that (24) is still dependent on predictable and uniform coupling properties of the tightly-wound inductor windings, a ripple current prediction problem can still exist. (28) 1- _2_ k .[ bn~2 Lefs3 = r.efp- (29) What is interesting, however, about condition (25) is that it can be absolutely satisfied if 1--- cn'03 (34) 6-20 which implies two non-coupled inductor assemblies, each with two windings, such that Lp and L02 are wound on the same core and Lol and L03 on the other. External inductances £2 and £3 are then added in series with L 02 and L03, respectively, to reduce both input and the first secondary (in our case, the high current + 5 V section) ripple currents to zero. In other words, the coupled-induct10.0 10 77 slope) slope) slope) slope) 15.0 127.0 5.0 50.0 87.4 108.0 >77.0 <10.0 <77.0 102.0 111.0 50 mV secondary voltages of Tl and T2 become unbalanced (vI" VI, v2, and V3 of Figure 9), and the equations (26 - 2 9 ) become invalid since they assume ideal time phasing between all potentials. +5V OUTPUT INPUT "'" The noise and ringing observed in the current waveforms are caused in part by the presence of inductive and capacitive parasitics in the breadboard layout that become significant at high switching frequencies which modulate current levels, and by the non-ideal nature of instrumentation with regard to grounding and noise . 050mV '"0 "Positive" Ripple Case Figure 11 .. mV 8.2 Group Two: Line/Load Variations +,V These tests were mainly performed to evaluate the steady state operating properties of the converter. The tests were conducted while maintaining zero current ripple in the input and the + 5 V output. These tests included line and load regulation and system efficiency measurements. OUTPUT INPUT I ..... 22=5~. ---. 0.. mV , .0 Table 5 Line Regulation with RL1 (5 V Output Load) = 1 RL2. RL3 (±15 V Output Loads) 15 n "Negative" Ripple Case Figure 12 = VIN VOLTS DC The values of £2 and £ 3 for different current ripple conditions are summarized in Table 4 along with the theoretical values from (36). Also shown in Table 4 are experimental and theoretical values for L~fs2 and LMs 3 under the zero ripple current condition. 22 28 32 +5V VOLTS DC +15V VOLTS DC 15.02 14.58 14.37 4.98 5.00 5.00 n. -15V VOLTS DC -14.92 -14.50 -14.29 Table 6 +5 V Output Load Regulation with Vln Examination of Table 4 shows excellent correlation between experimental and calculated values of circuit inductances. Variations noted are in part due to the differences between assumed and actual inductance values of Lp, Lo l, L0 2, and Lo3, and to the measurement accuracy in determining £20 and £30 of the fixed value, discrete chokes. RL2 The slight change in the magnetization current of Tl along with the input current level of Figures 10 through 12 is primarily caused by differences in switching times of Ql and the three secondary commutation diodes. During these switching periods, the = RL3 = 15 n = 28 V DC, RLl (0) +5V (VOLTS DC) +15V (VOLTS DC) -18V (VOLTS DC) 10 2 1 5.00 4.99 5.00 12.05 13.15 14.54 -12.06 -13.14 -14.46 In Tables 5 and 6 we observe that the load and line regulation of the + 5 V output are very satisfactory and do not need any comments. It is interesting to note that, although the line regulation of the + and 6-22 -15 volt outputs are well within required ranges, their absolute value decreases with increasing line voltage. This change is enhanced with respect to + 5 V load variations as noted in Table 6. This phenomenon can be explained when it is observed that + and - 15 volt output voltages are determined mainly by the voltage impressed across the N 1 winding of T1 during the off time of Ql. This voltage is made up of the voltage on Cl and the forward drop of diode D 1. The voltage on C2 does not significantly change with line variation; however, the forward voltage drop of Dl increases with decreasing line voltage due to increased value of the reflected current from the primary, thus increasing the total impressed voltage across N I. With + 5 V load variation, this effect becomes more pronounced. Since now, in addition to the forward voltage drop of DI which changes with load, the steady-state value of the voltage on CI also changes to make up for the changing drops in the winding resistance of T1, Lol and in its own ESR. As a net result, the voltage impressed across NI during the off time of Ql increases with increasing + 5 V load and decreases with decreasing +5 V load. 0- 22 28 32 3.5 2.6 2.3 77.0 72.8 73.6 // 10,..8 (b) With Diode Clamp +15 V Output Output Waveforms at Turn-On Figure 13 output effectively clamps this negative spike to a diode drop below the + 15 V return line. 9. Conclusions and Remarks A high frequency triple-output DC-to-DC converter design utilizing a CUK output power stage is proposed herein, with magnetic coupling between selected output filter inductances for attaining zero ripple currents at both the input power port and one output. The design also includes transient polarity reversal protection at the output port magnetically coupled to the input line. Po % (TOTAL) EFFICffiNCY (WATTS) 55.0 53.2 52.4 10,u.& ./ Table 7 Efficiency Measurements at Full Output Loads IQ PQ (AMP DC) (WATTS) / --' (a) Without Diode Clamp +15 V Output In Table 7, efficiency figures are calculated for minimum, nominal and maximum line voltages while the converter is delivering full output power. These figures compare well with practical efficiencies that are presently being obtained from conventional switching regulators operating at much lower switching frequencies. VQ (VOLTS DC) '"'" --- b- / 71.4 73.0 71.2 Power losses are attributed to those produced by semiconductor switching actions, dissipation in the energy transfer capacitances, IR drops in QI, and resistances of magnetic windings. As mentioned earlier, the experimental design did not include optimization measures to minimize these losses. Although the control electronics for converter pulsewidth-modulation were somewhat unconventional due _ to the use of ramp slope control, standard PWM LSI integrated control circuitry could be employed if desired. By the use of a VMOS power device instead of a bipolar transistor for the CUK converter primary switch, the interface electronics are greatly simplified and overall converter efficiency improved due to the micropower gate drive required for the VMOS field effect ~ansistor. 8.3 Group Three: Reversal Protection In this test, output voltage polarity reversal of the V output 'during tum-on was investigated. This voltage polarity reversal occurs only at the + 15 V output during tum-on due to magnetic coupling between Lp and L0 2. The photograph of Figure 13(a) shows that negative going spike went as high as - 20 volts and recovered in about 60 Ihsec after tum-on. Figure 13(b) demonstrates that a diode at the + 15 V + 15 Obviously, the converter could be designed to operate at lower switching frequencies with corresponding increases in energy transfer capacitor values and larger magnetic cores for the isolation transformer and inductor assemblies. In fact, the need for no output 6-23 filter capacitor on the regulated + 5 V line should simplify the frequency response of the converter as was pointed out in [3]; therefore, an extensively high switching frequency is not required in comparison to the filter comer frequency for reduction of voltage ripple on the regulated output. [2] Slobodan euk and R.D. Middlebrook, "Coupled-Inductor and Other Extensions of a New Optimum Topology Switching DC-to-DC Converter," IEEE Industry Applications Society Annual Meeting, 1977 Record, pp. 1110-1126 (IEEE Publication 77CH1246-8-IA). With regard to frequency response, no mention was made in this paper of breadboard converter performance in this area as these experiments are currently in process. Modeling of the converter for response predictions can follow published techniques [1, 2, 5] with modifications made to include nonregulated output loads and their filter networks reflected to the controlled output and the magnetic coupling of input! output inductances. Investigations are being performed in the areas of bandwidth improvement with increased stability margins by the use of multiple feedback control techniques such as those described in [6] and [8]. [3] Slobodan euk, "Switching DC-to-DC Converter with Zero Input or Output Current Ripple," IEEE Industry Applications Society Annual Meeting, 1978 Record, pp. 1131-1146, (IEEE Publication 73CH1346-61A). [4] R.D. Middlebrook and Slobodan Cuk, "Isolation and Multiple Output Extensions of a New Optimum Topology Switching DC-to-DC Converter," IEEE Power Electronics Specialists Conference, 1978 Record, pp. 256-264 (IEEE Publication 78CH1337-5 AES). [5] R.D. Middlebrook, "Modelling and Design of the CUK Converter," Proc. Sixth National Solid-State Power Conversion Conference (Powercon 6), pp. O3.1-G3.13, May 1979. [6] Shi-Ping Hsu, Art Brown, Loman Rensink, and R.D. Middlebrook, "Modeling and Analysis of Switching DC-to-DC Converters in ConstantFrequency Current-Programmed Mode," IEEE Power Electronics Specialists Conference, 1979 Record, paper 4A.6. [7] Slobodan euk and Robert W. Erickson, "A Conceptually New High-Frequency SwitchedMode Amplifier Technique Eliminates Current Ripple," Proc. Fifth National Solid-State Power Conversion Conference (Powercon 5), pp. 03.1-03.22, May 1978. [8] Loman Rensink, Art Brown, Shi-Ping Hsu, and Slobodan euk, "Design of a Kilowatt Off-Line Switcher Using a CUK Converter," Proc. Sixth National Solid-State Power Conversion Conference (Powercon 6), pp. H3.1-H3.26, May 1979. [9] R.D. Middlebrook, Slobodan euk, and W. Behen, "A New Battery Charger/Discharger Converter," IEEE Power Electronics Specialists Conference, 1978 Record, pp. 251-255 (IEEE Publication 78CH1337-5 AES). The success of external control of ripple current magnitudes reported in Section 7 and 8 has implications of corresponding circuit improvements to the basic single output CUK converters of Figure 1 that could simultaneously eliminate both input and output ripple currents. In addition, it should be possible for converter design with more than three outputs to utilize the techniques described in Sections 6 and 7 to attain zero ripple currents on the input and more than one output by proper choice of output inductances to be magnetically coupled. Acknowledgements The authors would like to thank Morris Rauch for his diligent work on the evaluation of the experimental breadboard and Karl Dakteris for the many hours spent in prototype magnetic designs. Thanks are due also to Dusan Jocic for excellent magnetic prototype construction work. Most of ay, special personal gratitude is sent to Drs. Slobodan Cuk and R.D. Middlebrook for their helpful advice and inspiration in putting this work together. References [1] Slobodan euk and R.D. Middlebrook, "A New Optimum Topology Switching DC-to-DC Converter, " IEEE Power Electronics Specialists Conference, 1977 Record, pp. 160-179 (IEEE Publication 77CH1213-8 AES). [10] R.D. Severns, "High-Frequency Switching Regulator Techniques," IEEE Power Electronics Specialists Conference, 1978 Record, pp. 290-298, (IEEE Publication 78CH1346-61A). [11] A.1. Pressman, "Switching and Linear Power Supply, Power Converter Design," Hayden Book Co., Inc., 1977, pp. 289-315. 6·24 6.1.3 The Generalized Use of Integrated Magnetics and Zero-Ripple Techniques in Switch Mode Power Converters © 1984 IEEE. Reprinted, with pennission, from IEEE Power Electronics Specialists Conference, PESC '84, Gaithersburg, MD, June 18-21, 1984. Abstract There is little disagreement among power converter designers that the magnetic parts of any switch mode design are the major contributors to supply cost, weight, and size. For these reasons, it is not uncommon for designers to select converter approaches that have a minimum magnetic content, even though, in many cases, one with more magnetic components would be more suitable from an overall circuit performance standpoint. Methods are presented that allow the discrete transformers and inductors of switch mode power converters to be unified in single magnetic structures. It is demonstrated that unified magnetics and zero ripple operation are general phenomena applicable to all types of switch mode power converters. Introduction Seemingly, a day does not pass now without an announcement of a new advance in microcircuit technology, bringing us closer to the age of ultra miniaturization of electronic products. For those of us who must design and develop power processing-systems it is a time of frustration and reflection, for as product sizes shrink, so must their power conditioners. Realizing that moving to higher switching frequencies to reduce magnetic size has practical boundaries, designers are now turning to another avenue of investigation - magnetic integration. This rather innovative-sounding, but accurate, term is used to describe magnetic design techniques whereby various inductive and transformer elements of a power converter can be combined on a single core structure. Twenty-five years ago, when the sizes of electronic systems were measured in terms of room dimensions, their power supplies could afford to be large. Today, with electronic products, such as calculators smaller than the dial of a watch, the power supply subsystems are often as large or larger than the electronics. Another example is the personal computer, where power supply areas often occupy up to 50% of enclosure volume, with a cost approaching 45% of product price. If one accepts the above definition of magnetic integration as applied to switch mode DC-to-DC power converters, then two converter topologies can be read- _ ily identified as integrated magnetic circuits, namely, the buck-boost-derived flyback converter and a special variation of the "boost-buck-derived" CUK converter[2] . Both of these circuits, together with their discrete magnetic counterparts, are shown in the lower portions of Figure 1. In the case of the flyback converter, the required inductance for energy storage is simply "built-into" the isolation transformer by proper choice magnetization inductance. Thus, the transformer of the flyback converter serves two important purposes - as an isolation element for input and output grounds and as a means of primary energy storage In a concerted effort to reduce power supply sizes, recent years have seen switch mode conversion and processing designs pushed higher and higher in operating frequency. Theoretically, at least, converters with high switching rates imply that their circuits will have smaller magnetic components. There are however, very practical limits to the size reduction obtainable from high frequency operation [1]. 6·25 I for supplying load power needs. In the case of the integrated-magnetic version of the transformerisolated CUK converter, its single magnetic houses all inductive functions of the converter and, by selecting proper amounts of mutual inductance that exist between windings, input and output ripple current magnitudes can be controlled, and even be reduced to zero in special instances [3] . magnetic buck and boost converters, it is worthwhile to digress briefly and review some not-so-familiar electromagnetic fundamentals and magnetic circuit modeling methods using electric circuit analogs. For those readers interested in a more comprehensive review than the one to follow, reference [4] is highly recommended. Recall that the similarity between Kirchoff's voltage and current laws for linear electric circuits and Ampere's circuital laws related to magnetomotive force and flux continuity in linear magnetic circuits permit the use of electric circuit analogs for analysis purposes. Such analysis makes voltage, V, analogous to magnetic potential, f; current, i, analogous to magnetic flux, cp; electrical resistance, R, analogous to magnetic reluctance, R. Furthermore, because the electric circuits derived by the use of these analogs are linear, they can be manipulated into even more useful forms by established duality relationships [5]. Transformation by duality then produces electric circuit models that relate magnetic reluctances, R's, to inductances, L's; flux linkages in windings, A'S, to voltages, v's; and flux levels in magnetic paths, cp's, to currents, i's. Both the buck-boost converter and its dual circuit, the CUK converter, can be evolved from the appropriate cascade arrangements of basic buck and boost circuits, as demonstrated in [2]. It is interesting to note that integ!:ated-magnetic versions of isolated buck-boost and CUK converters are perfectly feasible and welldocumented circuit possibilities, but little is publicly known about similar integration methods for transformer-isolated versions of their parent circuits, as visually emphasized by the vacant sections of Figure 1. In this paper, we will explore design techniques for the integration of the transformer and inductive components of buck and boost-derived converter topologies. To set the stage for this examination, a brief introductory section on basic electromagnetic modeling and analysis is included. Discussions of magnetic integration of the inductive components of a forward converter are then presented, with extensions for reducing the output ripple current significantly by external means. By duality integrated-magnetic boost converter circuits are then evolved and extensions illustrated for input ripple current reductions. I The rate of change of flux with time within a coil of wire (with or without a ferromagnetic core) of N turns can be related to A, as (1) by Lenz's and Faraday's Law. As shown in (1), a similar relationship can be stated in terms of the inductance (L) of the coil and the instantaneous current (i) thru it. In the case of a single coil of wire, cp is the measure of flux linkage within the core produced by self-induction. In an instance where there are multiple coils with common magnetic paths, the total flux linkage of one coil would be the sum of that produced by self-induction plus those produced by mutual interaction, or mutual induction, with the others. Integrated-magnetic "push-pull" DC-to-DC converter structures are then examined, including one based on a special variation of the Weinberg circuit. Results of laboratory tests of a representative integrated magnetic converter are then shown, followed by discussions of small-signal averaged modeling for stability and control analysis. Tools for Magnetic Circuit Modeling Integrated magnetics for converters brings to mind a picture of magnetic structures that are highly complex and unwieldy from design, analysis, and construction viewpoints. To some degree, this concern is understandable, for most engineers today are only familiar with magnetic design methods that address inductors and transformers as individual converter components. Just the thought of having to deal with a magnetic assembly with more than one major flux path is often a deterrent to an engineer to 'attempt such a design. The magneto motive force, F, of an excited coil of wire (with or without a ferromagnetic core) is defined as the product of the instantaneous current through it, i, and the number of turns, N, of the coil. In equation form, F can be directly related to magnetizing force, H, and its magnetic path length, 1, as F = Ni = HI (2) The self-inductance, L, of a single coil of wire of N turns, can be equated to the rate of change of flux with current from (1) as The attitude of designers in this regard is now changing. However, for many converter designers, the tools to properly design and model integrated-magnetic components have been unused over the years. Thus, before beginning the exploration of integrated- L = N dcp di 6-26 (3) INTEGRATED MAGNETICS DISCRETE MAGNETICS (a) (b) VolV~=nD 1'n:" ....>--<.--0+ ?• + Do--t-l!4, FORWARD CONVERTER (BUCK-DERIVED) (c) (d) ?• REVERSE CONVERTER (BOOST-DERIVED) (f) (e) V~ D L-_~-~-o+ FLYBACK CONVERTER (BUCK-BOOST-DERIVED) FLYBACK CONVERTER (BUCK-BOOST-DERIVED) (g) (h) VolV~ = nD/D' c+ V~ + c + L-------~~---J1:nL---_'--------~--_'--~+ L__ _ _ _ _ _~~---J ISOLATED CUK CONVERTER (CUK-DERIVEDI "r 1:n'---......_------...--........--<1 + ISOLATED CUK CONVERTER (CUK-DERIVED) Discrete and Integrated-Magnetic Converter Possibilities-What About the Forward and Reverse Designs? Figure 1 6-27 I - (,I Assuming that a linear relationship between flux level and magnetizing force is always maintained, R can be defined as the ratio of a change in F produced by a change in cp. From (2) and (3), reluctance can be expressed in terms of inductance as RIGHT-HAND RULE FLUX DIRECTION (4) (bl MEAN FLUX PATHS Reluctance can also be expressed in terms of related magnetic path length, cross-sectional area of the magnetic material, AC, and the permeability, /1-, of the path in question. If AC is uniform in value throughout the path, then R = /l-Ac = 1 P (5) • - RELATIVE TO WINDING A-8 A- RELATIVE TO WINDING E-F . - RELATIVE TO WINDING C-O Determining Flux Directions (a). and Dotting of Windings (b) Figure 2 where P is defined as material permeance, the reciprocal element of reluctance. visually express voltage polarities. However, this is easily done by the use of the right-hand rule and the three dotting rules given above. An example of multiple "dotting" is shown in Figure 2(b), where three sets of "dots" are needed to express winding polarities relative to each one of the three windings of the magnetic. In magnetic circuits, arrows are used to indicate the assumed directions of winding currents, rather than polarity marks for magnetomotive forces (often shortened to "mmfs"). The most popular method for determining flux direction is the "right-hand rule" illustrated in Figure 2(a). With the right hand positioned as shown, the flux direction will be indicated by the direction of the curvature of the fingers. Note that the thumb must be pointed in the assumed direction of winding current when making this determination. A Magnetic Circuit Modeling Example All of the fundamental definitions related to magnetic circuits given above, when combined with the techniques of electric circuit modeling and duality, produce a powerful set of analysis tools for quick and accurate examination of any magnetic circuit arrangement, no matter how complex it may be. The electric circuit models that result are just that - circuit models - and do not depend on abstract mathematical relationships (such as mutual inductance expressions) for performance evaluations. In representing multi-winding magnetic circuits in electric circuit diagrams, it is customary to use dot notation to convey the voltage polarity relationships of each winding relative to the others, as shown in Figure 2(b). Three basic rules are followed in the "dotting" of windings: RULE 1. Voltages induced in any two windings due to changes in mutual flux will have the same polarity at "dot-marked" terminals. As an illustration of the power of these modeling techniques, consider now an example. For this exercise, we will derive an electric circuit model for a two-winding transformer with parasitic leakage inductances, as shown in Figure 3(a). Here, an ungapped toroidal core provides the major magnetic path between windings (cpm), and each winding has a leakage path (cp 1, CP2) for flux that is not contained in the material path. We will assume for this exercise that the core's cross-sectional area is uniform throughout its body, and that a mean path length can be used to define the reluctance of the core. RULE 2. If positive currents flow into the "dotmarked" terminals of related windings, then the mmfs produced in each winding will have additive polarity. RULE 3. If any related winding is open-circuited, and if the currents flowing into the "dot-marked" terminals have a positive rate of change, then the voltage induced in the open winding will be positive at its "dot-marked" terminal. When a magnetic circuit arrangement has more than two windings and contains more than one major flux path, then multiple' 'dotting" windings is necessary to If we designate Np as the primary exciting winding, we can first determine the voltage polarity of the secondary winding using the right-hand rule. With a 6·28 primary current direction and the winding dotted as shown in Figure 3(a), fluxes rp 1, and rp2 must have positive directions as indicated in this figure. The dot for the secondary therefore must be at the top of this winding to produce a flux in the same direction as rp m. turns of the winding we select as reference for the final electric circuit representation. This is accomplished in Figure 3(d). The major purpose of this scaling step is to place all circuit permeances in a form that can be directly related to inductance. Note that the scaled model of Figure 3(d) also permits easy conversion of flux linkages to primary and secondary voltage values. With winding polarities established, we note that the secondary voltage, Vo , must have a polarity as shown, for the given polarity of exciting voltage, V s. Because the resulting secondary current is "out of the dot", we also note from our earlier transformer rules that this current, io , will produce an mmf that opposes that of the primary. Finally, we convert the scaled permeance network to one involving voltages and inductances. This conversion is shown in Figure 4(a). Note that we have added an ideal transformer to this network to properly scale terminal secondary voltage and current values. Using impedance translation methods, we can also "move" all or some primary inductances to the secondary side of the final electric circuit model if desired. Two versions of such impedance movements are shown in Figures 4(b) and 4(c). Next, we draw the equivalent magnetic circuit diagram for the arrangement of Figure 3(a). This is done in Figure 3(b), using the analogous relationships defined earlier. Note that rpm and rp 1 have the same polarity in the primary winding, since they are caused by is. However, in the secondary winding, rpm andrp2 have opposite polarity, since one flux (rpm> produces io while the other (rp2) is a consequence of io . In just four easy steps, we have been able to develop a realistic electric circuit model for a somewhat complex magnetic circuit arrangement. Note that the final models of Figure 4 do not involve mutual inductances and are in a form that a designer can easily relate physical properties of the corresponding magnetic system of Figure 3(a) to familiar electric circuit quantities. From the magnetic circuit of Figure 3(b), we can now develop a dual permeance network for it, resulting in the equivalent circuit of Figure 3(c). Our next step is to scale the network of Figure 3(c) by the number of Looking at Figure 4(c), we see that inductances Ll and L2 represent those produced by flux leakages, and are often called leakage inductances. Inductance Lc in the networks of Figure 4 represents that produced by the primary turns (Np ) wound on the ferromagnetic core of the transformer, and is not the mutual inductance (M) shared by primary and secondary windings. Recall that mutual inductance is a mathematical measure of the degree of coupling between two windings of a magnetic. In this case, we can easily find the value 1,1 '. 1,1 L, [~r2 + =0 . " m'O _,.~ fo_ • • + N, LOAD Ideal T ' ) >] Ibl '. L2 '0 t LOAD '0 1- 10' IdedlT) '0 LOAD Developing Reluctance and Permeance Circuit Models for a Two-Winding Transformer with Leakage Fluxes Figure 3 Electric-Circuit Equivalent Networks for the Two-Winding Transformer of Figure 3(a) Figure 4 6·29 - D' of M by writing the two nodal equations that relate input and output currents of the circuit models, and then isolate the common inductance terms within them. If this is done, then M is found to be NS M= Np X Np (6) I.e "Coupled-Inductor" Output Filter Network of a QuaslSquareWave Converter Figure 5 Achieving Zero-Ripple Currents Although the techniques of achieving zero-ripple currents in the windings of selected magnetic designs have recently been thoroughly explored [3], there is much historical evidence that the use of magnetic means to lower ripple currents in converter outputs is not a new discovery. For example, O.B. Crouse disclosed in his 1933 United States patent [6] a magnetic method for lowering the ripple voltage of an L-C filter for use in radio receiver power supplies. This method, upon close scrutiny, appears to be identical to one reported some years later by S. Feng [7] for reducing the' size of filter capacitors used across the outputs of power converters. Several other examples [8,9,10] also exist. age voltage across it equal to V0 in the presence of the ripple current. Ideally, the mutual inductance shared by the inductor windings is then chosen to completely remove the ripple current from the load (R) and to steer it to the inner winding (N3). For this reason, no output fIlter capacitor is shown across R in Figure 5. However, in practical designs, some capacitance is usually added across R for decoupling of noise and for additional energy storage for instantaneous load demands. To understand how the inductor arrangement of Figure 5 can magnetically reduce ripple currents, we can use the electric circuit model developed in Section 2.1. Looking at Figure 5, we can assume that the voltages impressed across the two windings of the inductor are proportional in amplitUde and equal in dynamic periods, such as those shown in Figure 6(a). For our purposes, we will therefore assume that the "primary" voltage is of a value equal to Vs, with the "secondary" excited by another proportional voltage, avs. With these assumptions, we can impose these voltages across the terminals of the electric circuit model from Figure 4(c), and then analyze what model values must be present to make the primary ripple current (is) vanish. In both cases, the method entailed the addition of another winding to the filter inductor, whose mutual inductance relationship to the original inductor winding was selected by design to "steer" the ripple current in the main winding to the added "secondary" winding and, therefore, away from the output of the filter. The resulting circuit arrangement is shown schematically in Figure 5, for application as the secondary fIlter of a forward converter. Note that a fIlter capacitor (C) is necessary for DC isolation of the "inter" winding and is selected to maintain an averw r-------------------, '0 • " LZ NS 1 I' "'. 1 1 1 1d L - - - - - - - - - - - - - - - lL:....~,;sf;mer Modal of Fig 41cl (b) o~U RE. U t, -- ", , > 0 The Coupled-Inductor of Figure 5 Modeled Using the Transformer Equivalent Circuit (a), Driven by Proportional Voltages (b) (Note: a = 1 for Figure 5) Figure 6 6-30 Comparing the constraints imposed on the values of L2 and Ll by (9) and (10), respectively, one finds that it is not possible to achieve zero values of is and io simultaneously. This point is also made by the current waveforms for is and io illustrated in Figure 8. Note also from the equations accompanying Figure 8 that the effective inductance seen at the "primary" terminals of the two-winding magnetic will be equal to its open-circuit value (Le. "secondary" side open) when L 1 is selected to reduce io to zero. Conversely, the effective inductance seen at the "secondary" terminals will be equal to its open-circuit magnitude when L2 is set to reduce is to zero. Ib) ". Circuit Conditions in the Model of Figure 6 for is Figure 7 +0 In actual practice, it is difficult to design and manufacture magnetic assemblies with consistent and specific values of parasitic leakag~ .inductance~ to achieve the zero-ripple current conditIOns as defmed by (9) or (10). One viable solution to this producibility problem is to tightly wind primary and secondary turns to reduce Ll and L2 to essentially zero, and then to insert a small external "trimming" inductor [8] in series with the input or output to emulate the required inductance needed for Ll or L2. This trimming method is shown in Figure 9, along with corresponding values of Lext necessary for zero-ripple current conditions. This analysis task is easily performed, as illustrated in Figure 7. Writing the circuit equations for Figure 7(b) gives (7) diO ) Lc ( dt (8) [aNP ] NS)2 ( Np Lc NS - 1 (9) = (NS)2 ( NS) Np Vs Np L2 = Because of recent emphasis on application of zeroripple-current filters in CUK converter v~ation~ [9], [10], it is now generally believed that thIS partIcular family of converter topologies is the only one that can benefit by their use. However, as we have just seen, this is not the case. In boost converters, these same principles of ripple current reduction can be applied to their input inductor arrangements, one example of which is shown in Figure 10. And, as we will soon see this method of ripple current reduction can also be ad;antageously used in both buck and boost derived integrated-magnetic converter systems. Therefore, if we select the leakage inductance of the secondary winding to meet the needs of (9), then the primary ripple current will be reduced to zero! Although not shown here, a similar analysis of the circuit model of Figure 6(b) for zero-ripple secondary current can be made. The value of primary leakage inductance for io = 0 is then found to be (10) L2=(~:)\ [~-'l L, =L, [~-'l '. ....._-'" -".f..= 0 Input and Output Cur-rent Waveforms of Figure 6(a) When Selected Values of L1 or L2 are Present (Note: a 1 for Figure 6(a» = Figure 8 6-31 r _________ (.) Laxt al 1-T:n,::":r :0:1 ~r ~ ~" L1 "'0 Ie l2""'0 10 "",0 ", " i ~ldealT bl [~_ Laxt ..... L- - - - - - - - - - - - - - ,d - - - - r ___________________ -, - J L (~)2 L, [;,.- -,] oxt " (b) al IS = l1"'0 Ie L2"""0 0 Laxt '0 • ", N, " I" L - - - - - - - - - - - - - - ,-=-~r:Sf:me~ Model for h ... 1 Using Small External Inductances to Trim Ripple Current Magnitudes In the Circuit of Figure 6(a) Figure 9 r'· ~ , I I OT....... OT----IoI o ' , \.-T--l o " ~ \.-T ----..J , 10 ~,-,:="Q1 t 01 C2 L ...... tlghtly-coupled wmdmgs L oxt = L, [ ~~ -,] Lc- magnetizing Inductance of L referenced to N2 Using a Coupled-Inductor Arrangement In a Basic Boost Converter to Reduce Input Ripple Current Magnitude Figure 10 this is accomplished, the voltage across L 1 is zero and so is the ripple! The preceding explanation for zero ripple, while correct, may leave one wondering what is really going on and if the results are truly general or just a bit of mathematical serendipity. Remember that, in this particular example, a = 1 because both windings are excited by the same source. This is not the case in general as the next example will show. For the special case where a = 1, then NpfNS > 1 (see Equation 9) if L2 is to have a positive value. A very simple intuitive explanation can be provided by looking again at Figure 6. If the current through Ll is to be zero, then the voltage across Ll must also be zero. To the left of Ll is the voltage source VS. To the right of Ll is a voltage divider formed by LC and the transformed value for L2: L2' = (NSf Np)2.L2' as well as the ideal transformer. The game being played is to adjust the values for Le, L2' , and NpfNS so that the v~ltage source aVS is transformed to a value equal to Vs at the right side of L 1. When We can now extend our zero-ripple example to a multiple winding inductor in a multiple output quasisquare wave converter in which more than one output has zero ripple. The use of a single mUltiple winding inductor reduces the total weight and volume of the 6-32 01 R3 DOTS Vo3 • - RELATIVE TO N, • - RELATIVE TO N2 ... - RELATIVE TO N Coupled-Inductor Arrangement lor a Quasi-Square Wave DC-DC Power Converter Figure 11 inductive portion of the system, and also lowers cost and enhances the dynamic cross-regulation properties between the outputs of the converter. One of several possible versions of a converter with "coupled" output inductances is given in Figure 11. ideal conditions exist (Le., diode drops may be neglected and perfect coupling of transformer windings has been achieved). With this assumption, we define VNJ = avs, a = NSJINp Those familiar with the design aspects of coupledinductors for converters such as this one will note that the winding arrangements, as well as the core structure itself, are somewhat unconventional. Here, a three-legged core is employed, with two inductor windings placed on the outer portion of the structure, and the third winding contained on the "center" leg. Air gaps are placed in each of the two outer legs. As illustrated by the inductor current waveforms of Figure 11, it is postulated that the ripple currents in two of the three inductor windings can be made to disappear! VN2 = bvS, b = NS31Np VN = CVS, C (lOA) = NS21Np where Vs is the dynamic waveform produced across either of the primary windings of T1 by the switching actions of Ql and Q2. By our earlier assumption, we know that this converter is being operated at a constant switching frequency, and that Ql and Q2 are being alternately turned on for a portion, D, of a switching cycle. The first three steps in evolving the model are shown in Figure 12. In part (a) flux directions are found in each of the three magnetic paths, using the righthand rule method and assuming that the center leg is the controlling and dominant source of mmf. At first glance, it may seem that the analysis effort necessary to understand how the magnetic arrangement can achieve significant current ripple reductions in selected windings is overwhelming. However, if we use the modeling techniques just demonstrated, the analysis becomes straightforward and its results illuminating. Three other minor flux paths are shown in Figure 12 (a). These represent "leakage" fluxes, Le., not contained within the core material and are to be expected in any practical magnetic winding arrangement. Therefore, we have added them to our magnetic system to ensure that our final electrical model will include leakage inductance effects associated with each of the three windings. Note that the dynamic voltages impressed across each of the three windings of the magnetic are proportional, always in phase with one another, and have the same frequency. Voltage proportions are ideally set by the ratios of the transformer secondary turns relative to primary turns, and for this analysis, we will assume 6-33 - I {.I • MATERIAL PERMEABILITV=~m • UNIFORM CROSS-SECTIONAL AREA (AJ THROUGHOUT {bl UNIFORM .... ,.. .1 II,...CROSS-:SECTIQN ~, ~·II ALL DIMENSIONS IN METERS {,I .; 1-' I:.:.-I-..:j -1"'~ :l : -1,,21-- I I I I I I I I I I I I I L - - - - - - - r - I - - - - ____ .J + r t ! -,fJlEANPATH (b-c + 28 + 2f + ig,l LENGTHS R .'. ~ R.,=3L . JoIoAc 'fR'2 RCT R'2"~ JoIoAc RC'" RC2 • 1'0.411'010-7 :::~ ~~ ·""....c (b-c + 28'" 2h + 2g2) (:I....C ."".,Ac Po" PERMEABILITY OF FREE SPACE Reducing the Inductor Assembly of Figure 11 to a Reluctance Network Figure 12 {.I Next, in part (b) a two·dimensional view of the struc· ture of (a) is given in order to be able to relate core dimensions and air gap lengths to values for reluc· tance. Because winding details are not important for these determinations, they are omitted for clarity. In part (c) an "electrical" network of reluctances is constructed from the magnetic path details of part (b). Also shown in part (c) are the equations relating reluctance values to core dimensions, permeabilities, and cross-sectional area. (bl We now add to our reluctance network of Figure 12(c) the mmf's produced by the three winding currents as well as surrounding leakage reluctances. This is done in Figure 13(a). The "polarity" of each of the winding mmf's in our model is established using Rule 2 in conjunction with the assumed flux directions in each leg of the core in Figure 12(a). Note that, because each winding current is directed into its respective "dot," the mmf polarities are such that they will produce fluxes that are in the same direction as those assumed in Figure 12(a) in their respective legs. AS1' R92> AC1 ' RC2 RN » RCT (a) Adding mmf's to the Network of Figure 12(c), (b) Slmpllficalion of (a) Figure 13 For the most part, air gap and leakage reluctances will always be much greater than those presented by magnetic material paths, since material permeabilities are much greater than that of air. Therefore, the magnetic model of Figure 13(a) may be reduced in complexity to that shown in Figure 13(b) with little loss in accuracy. Although the magnetic circuit model of Figure 13(a) is perfectly suitable for translation into an electrical equivalent network, some simplification may be made. 6·34 'e iii (.( + 0, PN - + .. 2 N,2 p, + ~;\C " i\, =N, I¢A +0,1 N'e 0. P" N,ll (b( P, - oN + °A ~ N1 G=1 ,e =OA + "B +"N P, + Ie N,2pg1 LN + C!'S - - P" + , IDE~ eN ..l.=OB+02 N, N2 12 N?P N N,2P2 N,2 pg2 N, N2 },2 Final Electric Circuit Model for the MagnetiC Arrangement of Figure 12(a) Figure 15 abilities of various parts of magnetic paths. The final model gives excellent visibility into the effects of winding voltages and currents; also, how we can reduce ripple currents in selected windings to zero! Referring to the converter circuit of Figure 11, we remind ourselves that we are interested in the model conditions that must exist if the dynamic currents, il and i2, are zero. Looking now at our final model in Figure IS, we simply set il and i2 to zero, and then establish what circuit conditions prevail as a result of their absence. These conditions are shown in Figure 16. Developing an Equivalent Electrical Circuit Model for the Reluctance Network of Figure 13(b) Figure 14 The next step in our model development is establishing a dual network for the reluctance and mmf system of Figure 13(b). Using the duality procedures outlined in [5], the permeance circuit of Figure 14(a) is easily obtained. A choice must now be made as to which of the three windings we want the final elements of the electrical model to be "referenced." We arbitrarily chose N 1, keeping in mind that we can always alter our final electrical model later to refer to N2 or to N if we so desire. We now scale all of the elements of the model of Figure 14(a) by Nl. This process gives us a model relating flux linkages to winding current values, as illustrated in Figure 14(b). We then convert the permeance model of Figure 14(b) to one involving inductances and winding voltages. This is done in Figure 14(c), with ideal transformers added to account for the model reference to N 1. Circuit Conditions In the Model of Figure 15 for Ripple Currents in N1, N2 Equal to Zero Figure 16 With il and i2 at zero value, the voltages impressed across the gap inductances, Lgl, and Lg2 will be simple reflections of associated winding voltages, avs and bvs, respectively. Also, the dynamic voltage ~ drops across the leakage inductances, Ll and L2, _ _ must be zero, because their respective branch currents ' are zero. At this point, we can make an important observation - the values of the leakage inductances, Ll and L2, are not important in establishing a zeroripple current condition in either winding N 1 or in winding N2! Finally, using conventional impedance transformations, we move the leakage inductances associated with N and N2 to the "primary" sides of their respective ideal transformers. The result of this last model manipulation is shown in Figure 15. In a few basic steps, we have been able to reduce a rather complex magnetic system to an equivalent electrical circuit. In reviewing our steps, we find that we can easily relate all of the elements of the final electrical model to the parameters of the magnetic assembly, including physical dimensions and perme- In order to discover what remaining parameters of the magnetic arrangement are important in making i 1 and i2 zero, we now determine the describing voltage 6-35 and current relationships for the circuit conditions illustrated in Figure 16 avs = (~) Lg1 (~;) Nl Vs = (N) b N2 N 1 Lg2 (dic) dt diC\ cvS - vx= LN ( dtJ Note that (15) and (16) are not interdependent. Therefore, for fixed values of a, b, c, N, Nt. N2, and LN, air gap inductance levels may be selected by design so that requirements of (15) and (16) are satisfied simultaneously. For example, assume that we have a converter application as shown in Figure 3 where a = 1, b = 2, c = 3, and Nl = N2. Placing these values into (15) and (16), one finds that gap inductance, Lg2, must be twice that of Lg l, and that the choice of N, N 1, and LN will determine the actual gap inductance levels required to produce zero-ripple current conditions in windings N 1 and N2. (11) (12) (13) Developing an Integrated-Magnetic Forward Converter It is interesting to note that, contrary to popular belief [3], integrated-magnetic concepts for power converters are not innovations of research performed over the past seven years. Like the magnetic methods of ripple current reduction described in the last section of this paper, the concept of integration of the magnetic functions of power processing circuits has historical roots in much earlier periods. Perhaps the best documented evidence of this fact is an obscure (and mistitled) United States patent by Cielo and Hoffman of the mM Corporation [14] in 1971, which discloses possible circuit methods for integration of the transformer and inductor of so-called "push-pull" DC-toDC converters. Later in this paper, we will examine the methods of this interesting patent by extending the integrated-magnetic forward converter concepts to include "push-pull" switch arrangements. (14) Combining (11) and (12) with (13) and (14) to eliminate the common diddt term gives LN = :. (Nl) _ !:(N1 )-1 Lgl a N a N2 (15) LN = ~(N2) _ ~(N2)_1 Lg2 b N b Nl (16) With a brief exposure to magnetic circuit modeling methods and a review of inductive ripple current reduction techniques behind us, let us proceed to systematically construct a single magnetic assembly wherein the transformer and the inductor of a forward converter can be contained. No rigorous synthesis procedure will be followed here, but rather a path of deduction and intuition based on the general operation of this converter and knowledge of the flux change relationships that must exist in its inductive components. Also, using (13) and (14), we can find the effective inductance, Le , that is seen at the input to winding N when il and i2 are zero. Performing this operation gives Looking at (15) and (16), we now realize that if their relationships are satisfied, the ripple currents in both N 1 and N2 will be entirely eliminated! These equations also predict that the zero-ripple current conditions are not dependent on external converter operational conditions, such as line, load, or switch duty cycle magnitudes! The phenomenon will be dependent, however, on winding turns, proportional constants set by the transformer secondary-to-primary turns ratios, leakage inductance of the center leg of the magnetic assembly and the values of the two air gap inductances. The first step in our integration process will be to redraw the forward converter circuit of Figure 1 in a manner so as to emphasize both the electrical and magnetic aspects of the converter. Then, assuming that the converter is operllting in the continuous mode of inductor energy storage, the equations describing circuit conditions for each of the two switching states are found, and then placed in a format relating corresponding flux changes in the transformer and inductor. Because we are interested at this time in only major flux relationships, the describing circuit equa- 6-36 tions can be ideal, thus ignoring all parasltlcs including switch and diode drops, switching losses, etc. The elimination of parasitics is not a requirement, but it is a convenience for this discussion. During D'T, The redrawn forward converter is illustrated in Figure 17. The core of the transfonner is shown ungapped, while the inductor core is shown with an air gap, as is the usual case for a magnetic that must withstand DC bias. Transfonner windings are drawn and dotted to emphasize an assumed counter-clockwise direction of flux in its core and to produce a positive voltage (V 1> across the secondary winding (N s) when the primary switch (Ql) is ON. Note also that we have included a "core-reset" winding (Np2) on the transfonner for energy removal during intervals when Q I is OFF. A core material with low residual flux is presumed. For the inductor with its winding position as shown, flux direction will be clockwise. ~ ¢L= Vo NL (21) ¢T = (NL)CPL NS + Vo NS • cpT (NL). NS CPL = • + CPo (19) ,..-------, ¢L I -1',1- I NL A I I V I ~-P-f>-P-'f--' L.. _ __ > ___ (23) where CPo = Vo INs. Turning now to the first righthand tenn of (22) and (23), we note that its contribution to CPT is dependent on a fraction, NL INS, of the flux change rate in the inductor of the converter. Since our ultimate goal is to make the inductor an integral part of the same magnetic assembly that also contains the transfonner windings, it is logical to assume that NL should be made equal to NS, so as to contain all inductor flux in a single magnetic path. I v, (22) Note that the last tenn of (22) is of a fonn that could be considered as defining a flux change in a magnetic medium that is dependent on the value of the output voltage, V0, of the converter and the number of secondary turns on the transfonner, Ns . It follows then, that if we make this consideration, that such a magnetic medium must be a part of the transfonner assembly to satisfy the conditions of (22). Therefore, we can rewrite (22) as (18) _ dCPL _ VI _ V0 L- d t - NL NL (20) Np2 Looking at the equations for interval DTs, we see that we can combine them to remove the intennediate secondary voltage value, V I: Next, the ideal voltages that appear across the transfonner and inductor windings are found by simple circuit analysis for each of the two switching states of the converter, DTs and (l-D)Ts = D'Ts. Using (1), we then relate the rate of flux change in the transfonner core (CPT) and in the inductor (cpO to these voltage magnitudes. During DT, • = _'1'_= dA.T _s V =VI CPT _ dt Npl NS Vs ¢T= .J v o = [~l NplJ D Vs Conventional Forward DC-DC Power Converter (Idealized) Drawn to Emphasize Magnetic Operations Figure 17 6-37 ¢L As we will see later when we analyze the integrated magnetic that results from this "synthesis" exercise, NS must be equal to NL to realize a non-pulsating output current waveform and to achieve an input-tooutput voltage transfer function that matches that of a forward converter. to release the energy stored in the center leg is needed, and its turns (NU must equal those of NS from our earlier discussions. Second, a winding (NP2) is needed in the same leg of the core as that of the primary for "reset" purposes. The magnetic arrangement that results is shown in Figure 18(b). Note that these two windings are dotted so as to produce the same flux directions in their respective core legs as those in Figure 18(a). Setting NL = NS in (23), we arrive at a final expression for ~T during interval DTs: Our final task in this deductive "synthesis" process is to combine the two magnetic arrangements of Figure 18 by the addition of switches and diodes to establish the required winding voltage values for each switching interval of the converter. From our knowledge of the forward converter, we would expect that no more than one switch and three diodes would be needed, and this is indeed the case. (24) Remembering our previous magnetic modeling, we can interpret (24) as defining a magnetic assembly in which there are three major flux paths. This equation also tells us that the flux change in an input source related l2ath (~T) contributes to the change in another path (cpU associated with the "inductor" I'ortion of the assembly, as well as to flux change (~o) in a third path. From the assumption made in (23), this third path is related to the output voltage value of the converter. Figure 19 is the schematic of the integrated-magnetic of the forward converter that results from our efforts. Reflecting now on the steps that were necessary to place the transformer and inductor on a single-core structure, we find that no exotic efforts were really required and that, in reality, the deductive procedure followed was rather straightforward and ele- ~version These general observations permit us now to sketch a possible magnetic path arrangement that satisfies the conditions of (24) for the switching interval DTs. This sketch is shown in Figure 18(a). Note that the "inductor" path includes an air gap, as we expect that this leg of the magnetic core will need one to establish the required amount of storage inductance and to sustain DC bias without material saturation. To the outer legs of the core arrangement, we have added windings for primary and secondary in accord with (18) and (19), dotted properly to produce the required polarity of V0 for the indicated directions of is and io . Using the magnetic arrangement of Figure 18(a) as a baseline, we now look at what must be added to permit the conditions of (20) and (21) to be satisfied for the other switching interval D'Ts. First, a winding A Forward Converter with Integrated Magnetics Figure 19 INTERVAL INTERVAL DT 1.1 r-<--'--<-~ y D'T Ibl I ~-<--.----..., I I I I I I I '. I I L !/IT I I I I _> __ I I I J.. ____ ...J !/IT· !/IL I A '. I A 'l I Np1 I I + 1/1 0 Developing Magnetic Core Arrangements for Each State of the Converter in Figure 11 Figure 18 6·38 gantly simplistic. It now becomes clear that we can use similar deductive methods to evolve integratedmagnetic versions of any transformer-isolated buckderived converter. Once this is done, we can then use the principles of duality between converter circuits [15,16] to formulate complementary boost topologies. • UNIFOAM CROSS-SECTIONAL AREA (AC) THROUGHOUT • MATERIAL PERMEABILITY OF ALL SECTIONS IS THE GAr,.1E • DOTS RELATIVE TO Npl Verification by Analysis Following the evolution of an integrated-magnetic arrangement for a converter, it is worthwhile, if not mandatory, that its structure be verified by analysis. This is necessary in order that no major design aspect has been overlooked, as well as to examine the effects of any circuit parasitics (such as leakage inductances, etc.) that may have been introduced by the integration process. "L For the integrated-magnetic forward design of Figure 19, the analysis procedure begins with the extraction of the magnetic from the overall circuit topology, labeling each winding as to voltage polarities as well as current directions that are imposed by the converter. It is also advantageous to mark each winding terminal and carry the identifying marks through the modeling procedure, so that the final electric circuit model found by the analysis can be directly substituted for the magnetic assembly in the converter topology. 'L5"L ~ "'Je 6. IDEAL T NL + Ibl 'p IDEAL T l'S ~~ 7 An isometric sketch of the extracted magnetic from Figure 19 is shown in Figure 20(a). To this sketch, we add flux directions in each leg, assuming that the primary winding, NPl, is the exciting and dominant winding of the magnetic. From this point on, the analysis procedure follows the same steps of the twowinding transformer example of Figure 3(a), keeping in mind that there are three magnetic paths and four sources of mrnf in this case. Also, since we are only interested in major flux paths, we have omitted all leakages for this examination. However, they can be easily added later and the corresponding electric circuit model changed to reflect their presence. An Electric Model (b) for the Magnetic System of (a) Taken from Figure 13 Figure 20 ideal transformer of turns ratio NPI :Ns , using standard impedance tranSlatIon methods. This is done to position most of the induct!plces to the "right" of this transformer in order that the final equivalent converter circuit can be compared to that of a forward converter with discrete magnetics. Note that this impedance movement also required a change in the turns ratio of the ideal transformer across Lg. The electric circuit model of the magnetic of Figure 20(a) is shown in Figure 20(b). For the sake of brevity, we have not included the intermediate steps of the modeling effort here, but they can be found in [ 17] . This particular model is referenced to the main primary of the magnetic, NPl, as evidenced by the turns ratios of the three ideal transformers within it. Inductance Lg represents that presented by the centerleg-winding, while the two inductances, Lc , represent those presented by the outer-leg windings of the core (referenced to NPl). In practical designs, we would expect that Lc would be much larger in inductance value than Lg, since the permeability of free air is much less than that of a ferromagnetic material. Therefore, we can simplify our analysis at this point by eliminating the reflected Lc across terminals 7 and 8 of the circuit model in Figure 21. Also, we can assume that the Lc across terminals 1 and 2 of the model can be viewed as the "magnetizing inductance" of a real transformer of ratio NPl:N s . It is also apparent that winding NP2 can be a part of this same transformer, since it parallels Lc. The next step is to place the electric circuit model into the converter circuit, as shown in Figure 21. In making this placement, we have also "moved" Lg and one of the two Lc inductances "through" the With these assumptions in mind, we can now redraw the circuit of Figure 21 in a slightly simpler form shown in Figure 22(a). We also remember that the 6·39 mil I I 02 02 (a) 01 + + + -C + + R V. R V. 1 1 Vs Vs PWM la~It-o CONTROL 101 ( NS) 2Lg Placing the Model of Figure 14(b) Into the Topology of Figure 13 Figure 21 (b) integrated converter of Figure 19 also constrained NL to be equal to Ns and, therefore, the turns ratio of the ideal transformer across L has been changed accordingly in Figure 22(a). With the turns ratio of this transformer now 1:1, it can be completely removed by simply reorienting the circuit positions of diodes D1 and D2. +0--+---4 L= Np1 ;((·fl I r \ (MAGNETIZING INDUCTANCE = Lei NL " NS Np1 • Np2 -+ TIGHTLY COUPLED Further Circuit Manipulation (a) to Derive the Discrete Magnetic Version of Figure 13 Shown in (b) Figure 22 This final analysis step leads to the converter configuration of Figure 22(b) , which matches that of a conventional forward converter! We see also that the equivalent output inductance of this converter is equal to that set by the gap of the integrated magnetic multiplied by the squared ratio of "transformer" secondary-to-primary turns. If we had not chosen NL to be equal to NS. this equivalent circuit and its predecessor in Figure 22(a) tells us that the equivalent inductance would not be of the same value for each switching state of the converter and, therefore, we could expect the output current to be somewhat pulsating, just as would be experienced in a forward converter with a "tapped" output inductor [ 17] ! as is evidenced by the dynamic current and voltage waveforms of Figures 23 and 24, respectively. These waveforms and their magnitudes were derived by inspection of 'the current and voltage conditions that must exist in the electrical circuit models of Figures 21 and 22 for each converter state (continuous mode of energy storage assumed). As we see from both sets of waveforms, current and voltage stresses on the switches and diodes remain the same as\ those that would be experienced in a conventional f9rward design. It is evident from the results obtained above that the analysis of an integrated magnetic by the use of electric model equivalents has great value and provides much valuable design information. It is particularly valuable in designing integrated-magnetic versions of existing converter designs, where fIlter inductances and transformer characteristics (turns ratios, etc.) are known quantities. Using the equivalent circuit, such as the one in Figure 22(b), these quantities can then be directly related to the parameters of the integrated magnetic, such as core dimensions and permeabilities, winding turns, etc. '01 '01 '02 'DC '. Voltage and Current Waveforms From a "black box" standpoint, we would expect an integrated-magnetic version of a converter to have the same voltage and current characteristics as its discrete-magnetic counterpart. For the forward converter design of Figure 19, this is indeed the case, f.- f- f.- l- 0 0 t-- I- ~ r--::::. 0 DT, DT, DT, DT, I-T,- I-T,- N L • Ns Idealized Currents In the SPC Topology of Figure 13 (Continuous mode) Figure 23 6-40 is ON, energy is stored in the center-leg of the magnetic. During this same time period (DT s), load needs are supported by the output capacitor, C, and by magnetizing energy stored in the outer leg of the magnetic from the previous switching cycle (via 03). When Q2 turns OFF, QI is turned ON and the energy stored in the center leg is magnetically routed to the output load, R, via winding N s , with diode DI now forward-biased and the other diodes non-conducting. Like its discrete-magnetic contemporary in Figure 1, the ideal input-to-output voltage transfer function is simply IJOS(Ql) 'NS (7-B) 'NL 16-51 (25) 'DC (CATHODE) with the "inductor" turns equal to that of the "primary" winding of the magnetic assembly. TS TS Adding Zero-Ripple Current Features Voltage Waveforms in the SPC of Figure 19 (Continuous Mode) Figure 24 Magnetic integration of the inductors and the transformers of buck and boost-derived converters does not lessen the possibility of adding additional windings to control ripple current magnitudes on output or input lines. Developing Integrated-Magnetic Boost Converters It is possible to follow similar procedures of deductive synthesis and analysis from the last section of this paper to evolve integrated-magnetic versions of various boost-derived converters, such as the reverse converter [16] in Figure 1. However, given a dual buck-derived converter approach, it is much easier to use duality methods [15,16] to derive these complementary circuits. As we have seen in prior examples of integratedmagnetic forward and reverse converters, the inductive part of their magnetic assemblies is isolated to one path of the core arrangement. Therefore, by adding another winding in these same paths and impressing a voltage across it that is proportional in amplitude and of the same frequency as that appearing across the original inductor winding, we can steer the ripple current from the inductor winding to the other winding and, therefore, away from the output. We also have the option of "trimming" the ripple current magnitude by external means [11] if we so desire. For example, given the integrated-magnetic forward converter, duality manipulations then produce the integrated-magnetic boost equivalent of the reverse converter of Figure 1. The unusual converter that results is shown in Figure 25. In this case, when Q2 - 1 Vs D An Integrated-Magnetic Version of the Reverse Converter Shown in Figure 1 Figure 25 6-41 Figure 26 shows an integrated-magnetic forward converter with output ripple current control capability. Note that another winding has been added to the center-leg section (NUV, along with a small series inductor (Lx) and DC-isolation capacitor (CR). Winding NL is the original inductor winding and the new winding, NLR, is wound in close proximity with it. This is done to minimize leakage inductance effects and to maximize the mutual inductance that will exist between the two windings. Push-Pull Designs with Integrated Magnetics Just as there are so-called "push-pull" versions of the forward converter with discrete magnetics, integrated-magnetic arrangements are also possible. Two viable approaches [14] are shown in Figure 28. The first alternative, shown in part (a) of this illustration, looks very similar to the single-switch forward design of Figure 19, except that another set of primary and secondary windings has been added on opposing sides of the outer portion of the core structure. With the windings dotted as shown (relative to the primary winding, Np , controlled by Ql), diode DI will conduct when Ql is ON, and diode D2 will conduct when Q2 is ON. During both conduction intervals, energy is stored in the center leg of the magnetic, and is then released to the load via diode D3 when QI and Q2 are both OFF. With the new winding positioned in the converter circuit as shown in Figure 26, the value of inductance Lx needed to cause the output ripple current to vanish is found easily using (9) with a = I: Lx = ( r;;~)2 Lg (~~ - 1) (26) where Lg is the inductance presented by the air gap of the center leg with NL turns. In the case of the second alternative shown in Figure 28(b), note that the phasing relationships (Le., dots) of the two secondary windings (N s) have been changed from those of Figure 28(a). This change now prevents significant energy from being stored in the center leg of the magnetic, since conducting secondaries lie on the same magnetic path as their corresponding primary windings. For example, in Figure 28(b), when Ql is ON, D1 will conduct and when Q2 is ON, D2 conducts. Therefore, another winding (NLl) has been added to the center leg to provide a means of energy storage in the cent!!r leg when either Ql and Q2 is conducting. In a similar manner, a ripple-control winding can be added to the integrated magnetic of a reverse converter, as is done in Figure 27. In this case, the value of Lx to reduce the input ripple current to zero is again the same as given by the solution of (26), assuming that windings NL and NLR are tightly coupled together. In actual designs, there will be some slight slope in the "zero" ripple currents of these two converters due to the presence of the inductances (Lc) of the outer-leg primary and secondary windings. However, since Lc is usually much greater in value than that posed by the "inductor" winding, Lg, this deviation from an ideally flat current waveform is normally so small that it can be neglected for all practical purposes. Ideal Voltage Transfer Functions The input-to-output voltage relationships for the continuous mode of inductive energy storage for the converters of Figure 28 can be easily found by equating the volt-seconds appearing in the center leg of their T+L r---- ----, 1 A ·0 1 1 1 v, Q1 1J::"!I~tT_ DT, Lg = gap mductance related to NL • - relative to Np1 Adding Ripple Control Features to the Integrated-Magnetic Forward Converter of Figure 19 (NL. NLR tightly coupled) Figure 26 6-42 D, v. Lg .. gap Inductance related to NL • dots relative to Np Adding Ripple Control Features to the Integrated-Magnetic Reverse Converter of Figure 25 (NL. NLR tightly coupled) Figure 27 (bl (.1 +C>------, l1li : Two "Push-Pull" Versions of the Forward Converter of Figure 19 Figure 28 integrated-magnetic assemblies during each of the two switching intervals, DTs and D'Ts . In the case of Figure 28(a), the DC voltage transfer is ideally found to be Vo _ NL { D } Vs - Np 1 - D [I - (NUNs)] For Ns equal to NL, (20) reduces to Vo = NS x D Vs Np (28) which confirms that this integrated-magnetic converter design is buck-derived. For the other circuit arrange- (27) 6-43 ment in Figure 28(b), the DC voltage transfer function is ideally I -f-~ "oSIQ1I DT, Vo NS[ 1 ](29) Vs = Np 1 + (D'/D)(NLl/NL2)(NS/Np) o~ 1 -f--I "08 102) In this instance, if - then (22) becomes VANODEI D1 1 Vo _ NS x D Vs - Np ~ Q1 ~ DT, -- Ql Q2 Q2 Ql Ia, ON 02 ON OFF --Nl. =Ns Voltage Waveforms In the Converters of Figure 28 (Continuous Mode) Figure 30 Voltage waveforms also are quite similar to those of a "push-pull" buck-derived converter, except that the magnetic integration process has yielded another potential benefIt-lower OFF voltage stress on the two switches of the converter. Ideally, the OFF voltage stress on either switch in a conventional "pushpull" converter will be equal to a maximum value of twice the input voltage magnitUde. However, in its integrated-magnetic version, Figure 28(a), maximum OFF voltage stress is equal to the value of source voltage plus the reflected output voltage. This implies that, by proper choice of turns ratio, we can signifIcantly reduce switch voltage stress by using integrated magnetics as compared to a conventional discrete-magnetic equivalent! Practical Design Considerations r-. In order to reduce the possible harmful effects of leakage inductances, the integrated-magnetic circuit variation of Figure 28(b) is often preferred over that of its contemporary approach in Figure 28(a). Note that, in Figure 28(a) , corresponding primaries and secondaries are positioned on the core legs so that they cannot be tightly coupled together (Le., wound tightly together). However, in the converter of Figure 28(b) , because corresponding primaries and secondaries lie on the same legs of the core structure, they can be wound tightly together to maximize their magnetic coupling and to minimize parasitic leakage inductances. Therefore, for this reason, the design of i '~ r--... DT, --- I -f-- OFF "":m D'T, '-- I--T,- I--T,- 'm ~ o - -- 0 ON ..!"'- - - 0 ,....... ~ ..- - ~ VANODEfD2) The typical current and voltage waveforms that will be observed in either converter circuit of Figure 28 are shown in Figures 29 and 30, respectively. In the case of the current waveforms, they look very similar to those of a conventional "push-pull" quasi-square wave converter, except that the magnetizing current of the outer legs of the magnetic produces a minor step in the otherwise continuous form of the output current. As discussed earlier, these .. steps" will usually be very small because of the high values of effective inductances of the windings on the outer legs. '. - - Voltage and Current Waveforms '02 ~ (31) which, like (28), confIrms that this circuit variation is a member of the buck-derived converter family. Interestingly enough, this converter, with its magnetic replaced by its electric-circuit equivalent [ 17], is found to be an integrated-magnetic version of the Weinberg circuit [ 18] ! 'D' o -DT, ID'T,-f-- f - - - 0 - '01 0 f-0 (30) '. D'T, r---- v. D'T, I---T,-I-T,- NL -N. Ideal Current Waveforms In the Converters of Figure 28 (Continuous Mode) Figure 29 6-44 Figure 28(b) is usually chosen rather than the circuit of Figure 28(a), even though the latter approach requires an additional winding to be added to the cel: 'ar leg for energy storage. tested by the authors over the past two years. Major areas of interest for these empirical examinations were verification of expected DC voltage transfer functions and anticipated dynamic waveforms within the converters. In all cases, the results obtained were very close to those predicted. Another advantage of the converter in Figure 28(b) is the presence of an inductor in series with both primary switches. Thus, high instantaneous current due to conduction time overlap is automatically eliminated. Also, this converter, like its discrete-magnetic counterpart, can be made to operate as a boost converter, if the primary switches are purposely forced to have overlapping conduction intervals [16]. Typical of the test results are the voltage waveforms taken for a low-power version of the integrated-magnetic Weinberg converter of Figure 28(b), shown in Figures 32(a) through (c). In this instance, the supply voltage was set at 40 VDC, and PWM duty cycles of Ql and Q2 manually adjusted to obtain an output voltage of 5 VDC, across a load of 5 ohms and an output capacitor, C, of 100 microfarads. PWM clock frequency was set very close to 100 kHz, resulting in a 50 kHz switching frequency of each primary power switch. Also, to minimize voltage "spikes" produced by leakage inductances, small R-C snubbers (1.2 K ohm x 0.01 ILF) were added across each primary winding and across NL2. Small-Signal Modeling Considerations Even though the magnetics of a buck or boost-derived converter have been magnetically integrated, modeling and analysis for stability and other dynamic studies is straightforward, using proven techniques such as the state-space averaging method [2]. All that is necessary is to derive an electric circuit model for the integrated-magnetic system, and then to add it in place of the magnetic in the converter topology. Following this, the normal procedures for deriving smallsignal averaged models are followed, accounting for additional inductive elements [19] as presented by the integrated-magnetic arrangement. The integrated magnetic used for this particular experiment was composed of two joined Ferroxcube E625 E-cores, with each of their center legs ground to produce a total air gap length of 0.01". Three bobbins were then placed on each leg of the core structure, each with two sets of windings. Each winding set was composed of 30 turns of # 20 AWG wire and 15 turns of#20 AWG wire. The completed magnetic was then connected into the converter arrangement of Figure 28(b), with windings phased as shown. Windings with 30 turns were used as primaries and for NLl, while the 15-turn windings were used for the secondaries and for NL2. For example, the averaged small-signal model for the integrated-magnetic version of the forward converter of Figure 16, using its equivalent electric-circuit topology from Figure 22, is illustrated in Figure 31. Note that the averaged model accounts for all of the inductive elements of the electric-circuit model, as well as its isolation transformer. If we had chosen to add leakage inductances to the electric-circuit representations in Figure 22, they could also have been easily accounted for in the equivalent small-signal model. Using the relationships developed in Section 2, the inductance of the 15T center-leg winding was calculated to be about 1 mh for an air gap length of 0.0 1". Inductances of the primary windings on the outer legs were also calculated to be about 10 times that of this center-leg winding, confirming the earlier assumption that these latter inductances are indeed much larger in value. Laboratory Investigations All of the integrated-magnetic versions of the various converters shown in this paper have been built and -- I '0 " 1 1 D n Averaged Small-Signal Model of the Integrated-Magnetic Forward Converter of Figure 19 Figure 31 6-45 (a) (b) o o o o (c) (d) o o o o Breadboard Test Photos of Voltages Within the IntegratedMagnetic Weinberg Converter of Figure 28(b) Figure 32 Comparing the lab photos of Figure 32 to the ideal waveforms of Figure 30 expected in this design, we find that they closely match in all instances. Also, the observed duty cycle of each primary switch is, in close agreement with that predicted earlier by (31) when correction is made for converter efficiency. common operational property-flux change. Therefore, if relationships can be established between their flux changes from a knowledge of their position in a converter circuit, then it is possible to use them to deductively synthesize a single magnetic system to house all transformer and inductive functions. Concluding Remarks With integrated-magnetic versions of frrst-order buck and boost converters established, the possibility of magnetic integration of all of their family member topologies becomes immediately evident. In this paper, we have presented a broader and more general insight into integrated-magnetic concepts for switch mode DC-to-DC power converter circuits and, hopefully in doing so, have dispelled a common belief among designers that the transformers and inductors of buck and boost-derived converters cannot be magnetically blended on a single core arrangement. Many of these possibilities are shown in [17], while others are still to be disclosed in the future. Although we have presented integrated-magnetic versions of single-output buck and boost converter arrangements, the idea is easily extended to ~ccommodate multiple outputs, or multiple inputs as the case may be. This is easily done by the addition of more secondary or primary windings on appropriate core legs, together with contemporary switches and diodes. Also contrary to popular thought, the demonstrated ability to integrate the magnetics of these converters also removes the restriction that impressed winding voltages be completely proportional in all respects. In general, this particular restriction is correct, if one thinks only in terms of winding arrangements placed on a single magnetic path. However, as we have seen, multiple-path arrangements are perfectly viable design approaches. It must be remembered that, even though the winding voltages of the transformers and inductors in converters may not be completely proportional in frequency and amplitude, they share a In this paper, we have also shown methods whereby more windings can be added to inductive core paths to control input or output ripple current magnitUdes, and significantly reduce them by proper internal and! or external magnetic means. Even though we have used single inductive paths in making this demonstration, it is also feasible to add more core legs with 646 appropriate air gaps to the integrated-magnetic systems to control ripple current characteristics of contemporary windings, much in the same manner as was shown in [13] for the two inductors of a CUK converter. References The discussion here has been restricted to switch mode power converters. Work presently in progress indicates that these techniques can also be applied to resonant converter circuits. Take for example the series resonant converter, with an inductor in series with the transformer primary. This inductor can be absorbed into the transformer simply by increasing the primary-secondary leakage inductance. This produces an integrated magnetic. Finally, we conclude our paper with the following reflective thoughts. Although recent years have seen an increased interest in integration concepts for minimizing the magnetic content of converters or for enhancing their conversion properties, such techniques have historical roots, reaching back into the early years of this century. It is interesting to note that many advances in magnetic concepts for electronics were made in these earlier periods, with years following the introduction of the first electronic digital computer seeing little or no new work being continued in this important aspect of power electronics design. Shortly thereafter, a sad decline in educational opportunities for engineers in the field of practical magnetics design began, and continues today. Ironically, it appears now that magnetics could hold the key to achieving smaller and more efficient power conversion systems. As was noted in the introduction of this paper, it is truly a time of frustration and reflection for the power electronics engineer. Acknowledgements [1] R. D. Middlebrook, "Reduction of Switching Ripple in Power Converters," Proceedings of the Sixth International PCI Conference, April 19--21, 1983, p. 6-14. [2] Siobodan Cuk, Modelling, Analysis, and Design of Switching Converters, Ph.D. Thesis, California Institute of Technology, Pasadena, CA, 1977. [3] Siobodan Cuk, "A New Zero-Ripple Switching DC-to-DC Converter and Integrated Magnetics," 1980 IEEE Power Electronics Specialists Conference Record, p. 12-32 (IEEE Publication 80CH1529-7 AES). [4] J. K. Watson, Applications of Magnetism, John Wiley and Sons, 1980. [5] C. Desoer and E. Kue, Basic Circuit Theory, McGraw Hill, 1969, p. 453-457. [6] G. B. Crouse, "Electrical Filter," U.S. Patent 1,920,948 (August 1,1933). [7] S. Feng et.al., "Smail-Capacitance Nondissipative Ripple Filters for DC Supplies," IEEE Transactions on Magnetics, Vol. MAG-6, No. 1, March 1970. [8] A. L1odye, "Choking Up on L-C Filters," Electronics Magazine, August 21, 1967 issue. [9] G. C. Waehner, "Switching Power Supply Common Output Filter," U.S. Patent 3,916,286 (October 28, 1975). [10] W. J. Hirschberg, "Improving Multiple Output Converter Performance with Coupled Output Inductors," 'Proceedings of POWERCON 9, July 1982. The authors would once again like to thank Morris Rauch for his help in constructing the breadboards of the various integrated-magnetic converters shown in this paper. Also, a special thank-you is sent to Colonel Wm. T. McLyman of CALTECH's Jet PropUlsion Laboratory for constructing one of the integrated magnetics for the breadboards, and to the engineering directorate of Christie Electric Corporation for the use of their laboratory facilities during the breadboard testing efforts. [11] G. E. Bloom and A. Eris, "Practical Design Considerations of a Multi-Output CUK Converter," 1979 IEEE Power Electronics Specialists Conference Record, p. 133-146 (IEEE Publication 79CH1461-3 AES). To J. Cielo and H. Hoffman of mM, we send a very special inspiration thanks for their exceptional 1971 patent concerning integrated magnetics for "pushpull" DC-to-DC power converter circuits. [12] L. Rensink, Switching Regulator Configurations and Circuit Realizations, Ph.D. Thesis, California Institute of Technology, Pasadena. CA. 1979. 647 [13] Slobodan Cuk, "Analysis of Integrated Magnetics to Eliminate Current Ripple in Switching Converters," Proceedings of the Sixth International PCI Conference, April 19-21, 1983, p. 361-386. [17] G. E. Bloom and Rudy Severns, Modern DC- to-DC Switchmode Power Converter Circuits, to be published in 1984 by Van Nostrand-Reinhold, Inc. (Catalog #0-442-21396-4), also available from e/j BLOOM Associatp-s, 1312 Lovell Avenue, Arcadia, CA 91006. [14] J. Cielo and H. Hoffman, "Combined Transformer and Indicator Device," U.S. Patent 3,553,620 (January 5, 1971). [18] A. H. Weinberg, "A Boost Regulator with a New Energy Transfer Principle," Proceedings of the 1974 Spacecraft Power Conversion Electronics Seminar (ESRO Publication SP-103). [15] Slobodan Cuk, "General Topological Properties of Switching Structures," 1979 Power Electronics Specialists Conference Record, p. 109-130 (IEEE Publication 79CH1461-3 AES). [19] R. D. Middlebrook, "Design Techniques for Preventing Input Filter Oscillations in SwitchedMode Regulators," Proceedings of POWERCON 5, May 1978, p. A3-1 to A3-16. [16] Rudy Severns, "Techniques for Designing New Types of Switching Regulators," Proceedings of the International PCI Conference, September 1979, paper 5.5. 6-48 6.1.4 Siliconix Switch Mode Power Supply Kit Introduction The Siliconix power supply kit is an educational tool which will give you a hands-on introduction to both switch mode power converters (SPC) and devices from Siliconix's expanding line of power converter components. The circuit operates at a switching frequency of 150 kHz and a ripple frequency of 300 kHz. The use of switching frequencies greater than 100 kHz represents the present trend in SPC design. The benefits of high frequency operation are reduced size, weight, and cost along with improvements in transient response and input noise rejection. SPC Circuit Description 1------.,.-.... Vo Power Supply Block Diagram Figure 1 There are literally hundreds of different SPC circuits from which to choose. For the kit we have chosen a buck-derived circuit which is commonly used in offline applications. Normally, this type of circuit would be operated from a 100 to 350 volt source, but for reasons of safety and convenience, we have scaled the source voltage down to 24 to 32 VDC. The waveforms and circuit operation remain the same. It is important to emphasize that the kit is designed as a learning tool and is not intended to be used as a production power supply. A simplified schematic for the power converter is S2) are connected in a half-bridge configuration. In this configuration the switches see a maximum voltage of Vs and a peak current of twice the input current (Ii). The relatively low voltage stresses on the power switches make this circuit suitable for high input voltage (100 to 400 volt) operation; however, for a given type of switch, the high switching currents become a limiting factor, so this design is rarely used at power levels above 500 watts. A block diagram of the power supply is shown in Figure 1. The power converter uses a control loop which compares the SPC output voltage (V0) to a regulated reference voltage (Vref) at the error amplifier. The error amplifier generates an error voltage proportional to the difference between V0 and Vref. The error voltage is then compared to a ramp signal and converted to a pulse-width-modulated (PWM) control signal for the power converter (SPC). As stated earlier the kit SPC operates from 24 to 32 volts, a much lower than normal voltage for this configuration for reasons of safety. The effect of low input voltage and high switching currents is a reduction in the circuit efficiency of 5 to 10%. This should be kept in mind when testing the circuit. 6-49 Ll L_ SWitching Section Level Translation and Isolation Low·Pass Filter Simplified Power Supply Schematic Rgure 2 correspondingly higher losses. Schottky diodes also have a fast reverse-recovery-time (trr) which reduces the rectifier losses at very high switching frequencies. Referring again to Pigure 2, the average value of V2 is the output voltage (Vo), and the relationship to the PWM is: Vo = Vs 2 (NNps) (1) Where D is the portion of the switching cycle during which the switches are conducting t1 D= - Ts V2 (2) where: t1 is the conduction time of the switches. Ts is the switching period. We can see from equation (1) that if V0 is to remain constant, D must become smaller as Vs increases and vice versa. This is the basis for the control action. Idealized Waveforms Figure 3 Switches S 1 and S2 conduct alternately for equal periods of time. The actual "on" time (tI) of the switches is controlled by the PWM drive to each switch. The waveforms shown in Pigure 3 illustrate how the circuit (in Pigure 2) works. The action of the switches causes a pulsating DC voltage (VI), the AC component of which is applied across the primary of T1 (C5 blocks the DC component). The primary voltage (Vp) is stepped down to approximately 7.5 volts by TI and rectified by BR2 producing a pulsating DC voltage (V2). Por most applications the switching noise and ripple must be very low, so in addition to averaging, the output filter must reject most of the AC component of V2. This is accomplished by making the cutoff frequency (fc) of the fiiter lower than the ripple frequency (fr). In the kit converter, fc is so much less than fr that the equivalent series resistance (ESR) of the output capacitors greatly reduces the available attenuation. Pigure 4 shows an equivalent circuit for the filter and attenuation curves with and without the ESR. BR2 is a dual Schottky diode assembly. Schottky diodes are used in low voltage, high current output applications because of their low forward voltage drop (Vp). BR2 has a rated Vp of 0.5 volts and accounts for about 30% of the circuit losses. A normal PN junction diode has a Vp of 0.8 to 1.2 volts with The filter inductor current waveform can have two possible shapes: either the current goes to zero during the switching interval, or it doesn't. Another way of stating this is either all of the energy stored in Ll while PET 1 or PET 2 are conducting is discharged into the load when PET 1 or PET 2 are off, or it is not. At first 6·50 = VBR2 performance. This will be discussed again in the control loop stabilization section. Ll The schematic for the complete power supply is given in Figure 5. All control loop and drive functions are performed by the Siliconix PWMl25 (ICI). The PWM125 is a high performance pulse-widthmodulator IC designed specifically for high frequency power converter applications. The PWMl25 has the same pinout and is functionally similar to its predecessor, the SG1525A. The PWM125 features separate analog and digital grounds, true TTL gate structures for precise metering of pulse modulated signals, and completely redesigned totem-pole output sections with very low crossover current (120 rnA). In earlier totem-pole designs (Le. l525A), crossover currents of 950 rnA caused catastrophic failure at high speeds. Other features unique to the Siliconix PWM series (PWM 25/27, 125) are high operating temperature and high voltage capability. The PWM125 will be discussed in greater detail later in this text. Gnd 100Hz 1kHz 10kHz 100kHz OdBI------1::: -IOdB -20dB-------- - - - - - --- --------- --- -1 FiOie - "', -30dB .2 ;'~~~b;R Poie--":::;:-- Slope , without ESR " -40dB ......~~~~......._~~~--U..'-'-'-_-'-........,'--'-"........ Figure 4 glance this seems like a trivial distinction, but it is not. The conduction mode of the inductor current defines the operating mode (continuous or discontinuous) of the converter. The open loop static and dynamic properties of the converter will differ dramatically from one mode to the other. This is characteristic of all SPC circuits. The conduction mode must be known to properly stabilize the loop and to predict the circuit Actual Circuit Waveforms The waveforms shown in Figure 3 are idealized. In the actual circuit, the waveforms are somewhat different, and it is worthwhile knowing why. Figure 6 shows the actual waveform (Vp) across the primary ofT!. What interests us are the spikes and ringing when one of the FETs turns off. 24V c. toOOJ.l f l 1 -= Cll '1011 2'5 13 C3 47IJf 14 10 Rl r--, 75k BR2 CTB34 12 L 1 121tH '--_-...--_-o~'out SV@8A - C13 47pf R3 75k R12 10k Siliconix SMPS Kit Schematic Figure 5 6·51 I L£ : Tl :JIIC Figure 78 n L£ "off" Vs Vin = 24 Volts lout=BA Vertical Scale - 5 V/Div. Horizontal Scale - 1 p,S/Div. -=- C5 IlL "on" Figure 7b Primary Waveform Figure 6 In a real transformer, the primary and secondary windings are not perfectly coupled, and some of the primary flux linkages will not be shared by the secondary. This creates an equivalent series inductance (referred to as leakage inductance) LQ shown in Figure 7a. The mechanism for generating the voltage disturbance is as follows: 1. Referring to Figure 7b, assume SI is off and S2 is on. The primary current is flowing through L Q and S2. 2. Referring to Figure 7c, if we turn S2 "off" suddenly, the current in L Q must continue to flow. What happens is that the voltage across L £ reverses and rises until 01 conducts (01 is the integral diode in the MOSFET). When the energy in L£ has been discharged, 01 will cease to conduct. The circuit now rings at a frequency determined by L £ and Ca , where Ca is the total device and stray capacitance at that node. If 01 were not present then the voltage across S2 would rise until the switch went into avalanche breakdown. 01 limits the voltage rise to just above Vs and acts as a clamp. Figure 7c To reduce the ringing, there is a simple RC network made up ofRS and C12 across the primary ofT1. This does not completely eliminate the ringing but greatly reduces it. Vin = 24 Volts lout=8A Vertical Scale - 5 V/Div. Horizontal Scale - 50 nS/Div. Another feature of this waveform which may appear puzzling is the apparent change in turn-off switching between heavy and light loads. This effect is shown in Figures 8 and 9. Figure 8 is the turn-off waveform for FET 2 with an 8A output load. The turn-off transition S2 Turnoff Voltage Waveform Figure 8 6-52 Vin = 24 V lout = 0.5 A Vertical Scale - 5 V/Div. Horizontal Scale - 50 nS/Div. Vln = 24 V lout = 0.5 A Vertical Scale - 5 V/Div. Horizontal- 1 ItS/Div. S2 Turnoff Voltage Waveform Figure 9 FET2 Gate Figure 11 Vgs A1 ~A2 ~'-'----' 11 ov 12 Figure 12a Vin = 24 V lout=8A Vertical Scale - 5 V/Dlv. Horizontal- 1 ItS/Div. FET 2 Gate Voltage Waveform Figure 10 Figure 12b is 50 nsec. Figure 9 is the same waveform with the output load reduced to 0.5 A, and the apparent switching time is 200 nsec. In fact, the switching time of the PET has not changed at all; it is 50 nsec in both cases. The reason for the slower transition time at light loads can be explained by referring back to Figure 7c. At tum-off the current flowing in S2 will be available to charge Ca , and the rate of voltage rise across S2 will be dependent on the current (ILQ) available to charge Ca. When the output current is 8 A, ample current is available to charge Ca , and the rate of voltage rise is determined by the PET switching characteristics. However, when the output load is reduced to 0.5 A, the current available to charge Ca is reduced by a factor of 16. In this case, the charging of Ca completely dominates the voltage rise time. Another waveform of interest is the gate drive waveform (Vgs) shown in Figures 10 and 11. Ideally Vfe should see symmetrical waveforms independent of D. A cursory examination of the oscillographs shows that this is, not so; the positive and negative amplitudes vary with D. Since this is an AC coupled waveform (through capacitor C3 in Figure 12a), the enclosed areas are equal as is shown in Figure 12b. From a 6-53 - in series with the primary of Tl. The AC voltage across C5, due to the transformer primary current, subtracts from the applied voltage and causes the tilt in the output waveform. As the power supply output load increases, the voltage drop across C5 increases which increases the tilt in V2. When this type of circuit is used directly from the AC mains at the same output power rating, the waveform tilt is insignificant. The higher primary voltage results in a lower primary current which, in tum, results in a smaller voltage drop across C5. By scaling down the input voltage for the kit, the effect of C5 is magnified. The waveform tilt could be reduced by increasing the value of C5, but this is not necessary for the purposes of this kit. - -~-; FET 1 _ _ _ _ ...JI Transformer Drive Clr. for Wide Variation of Duty Cycle Figure 13 practical point of view, this means that as D is increased, the amplitude of Vgs during t1 must decrease while the amplitude during t2 increases. In this particular application, the variation in Vgs is not large and is not a problem. In some circuits the variation in D may be much larger causing Vgs to be too large at small duty cycles and too small at large duty cycles. This problem can be eliminated by modifying the drive circuit as shown in Figure 13. For the kit this modification is unnecessary because of the small variation in duty cycle. Control Loop Stabilization For the power converter to function as a regulated power supply, some means is needed to maintain a constant output voltage, as the output load and input voltage vary. This function is provided by the feedback control loop. As was pointed out earlier, most of the control loop functions are provided by the PWM125 (IC1). The issue to be discussed now is that of loop stability and transient response performance. Figure 16 shows an equivalent block diagram of the power supply control loop. To analyze the stability of the loop, we will calculate the gain and phase characteristics of the loop and then graph them using a Bode plot. The voltage waveform at the output of BR2 (V2 of Figure 2) is shown in Figures 14 and 15. It is clearly not ideal. In addition to the ringing introduced on the primary leakage inductance, there is a distinct tilt to the top of the waveform which increases as the output load increases. The tilt is due to the impedance of C5 The total loop gain (AT) is: AT = G1 G2 G3 Vln = 24 V lout=1A Vertical Scale-2 V/Div. Horizontal Scale - 500 nS/Dlv. Vin = 24 V lout = 8 A Vertical Scale-2 V/Div. Horizontal Scale - 500 nS/Dlv. Output of BR2 @ 1 A Load Figure 14 Output of BR2 @ 8 A Load Figure 15 NOTE: Current Goes Slightly Negative During Transition Period. 6·54 (3) C13 47pl To Output R12 S.6k Error Amp >---4-..... ToPWM Gain Blocks Figure 16 R3 75k G I represents the gain of the power converter. The AC part of G I is determined by the output filter which, as we saw in Figure 4, is a simple 2 pole LC filter with an ESR zero. The result is a single-pole characteristic with the cutoff frequency (fc) equal to 2.4 kHz. The DC portion of Gl is determined by the duty cycle and the transformer (Tl) turns ratio for D = 0.5. The DC value for G I is: Gl = 0.7 Figure 17a (4) This analysis presumes that the converter is operating in the continuous inductor current mode. If the load is reduced to the point where the discontinuous mode exists then the converter will have a single, rather than a two pole characteristic. Simultaneously, the loop gain will drop. Fortunately, these two changes work together in this application, and the loop remains stable. 1.9 kHz 41 kHz Frequency Figure 17b G2 is the gain of the error amplifier, and we can calculate it from Figure 17. We will assume the amplifier gain is large. The DC value of G2 is very large (60 dB). There will be a pole at the origin due to C2, and a zero will appear in the transfer function at a frequency determined by R6 and C2: Where Vramp is the peak-to-peak amplitude of the ramp voltage which appears on pin 5 of ICI: Vramp = 3.2V p-p (8) So that: 1 fo = 27TRC = 1. 9 kHz (5) G3 = .31 The asymptotic gain at 1.9 kHz is: R6 G2 = R12 = 14.6 We can now plot AT, as shown in Figure 18, in asymptotic form. We can see that gain crossover is about 9 kHz with a single pole roll-off which should give us a phase margin close to 90 o. The ultimate test for stability is the transient response to a step load. The transient response of the kit is shown in Figure 19. The response is well damped with a very small step change (about 40 mY). Given that the load step is 1 A superimposed on a 5 A DC load, the transient response is excellent. The small high speed oscillations on the leading edge of the step response are inherent in the dynamic load and are not due to the control loop. (6) The combination of C 13 and R6 will produce a pole at 41 kHz. An asymptotic approximation for G2 is shown in Figure 17b. G3 is the gain characteristic of the pulse-widthmodulator. Given the particular modulator used in the PWM125 (ICI), the gain expression is very simple: G3= Vramp (9) It is quite possible to have a much higher gain crossover frequency and an even better transient response, (7) 6·55 l1li I 100Hz 1 kHz 10kHz 100kHz 1 MHz Figure 18 Clocking and Control Circuit (Figure 20) The ramp and timing signals are generated by charging a capacitor (Ct at pin 5) from an internal current source which is programmed by an external resistor (Rt at pin 6) using a current mirror technique. A comparator in the oscillator section is set to trip at 0.8 V (low) and 3.6 V (high). When capacitor Ct (pin 5) is charged to the high trip point, the discharge transistor (Qd) turns "on" and discharges Ct to ground through pin 7 (Qd collector). Pin 7 is normally connected to pin 5 on the PWM125. When the capacitor (Ct) is discharged to approximately 0.8 V, Qd is turned "off," and the cycle starts over again. The slow charge and fast discharge cycle generates the ramp signal for the pulse-width-modulator circuit. Other circuits in the oscillator generate the clock pulse for the metering circuits. Vln = 24 V lout= 5A Vertical Scale - 50 mV/Dlv. Horizontal Scale-100 / -~_ "177_ _ 7. PWMOUT • • DV ()!!._ _ _ _ _---l SOFTSTART & SHUTDOWN PWM125 Clock & Control Circuit Figure 20 ---1 V ....... /,,"--...-,,'3'0 COLLECTOR 11~PUT OUTPUT ENABLE F/F UU fin CLOCK fin PWM125 Metering & Output Circuit Figure 21 amplifiers, with a load resistance of ~ 10 megohms is 60 to 80 dB. Because the error amplifier is a transconductance design (Vo = gmRL Vi), as the output is loaded the gain is reduced. The details on how to use this amplifier were discussed in the section on control loop stabilization. in input voltage or output current are met with little or no change in output voltage. Figure 20 shows the error voltage vs. ramp at about 50% duty cycle. Metering and Output_Circuits The clock pulse generated by the oscillator circuit is used to trigger the metering flipflop which controls output gate selection. This ensures that the totem-pole outputs at pins 11 and 14 are never on simultaneously. The metering latch ensures that only one modulated pulse per clock period is allowed and prevents doublepUlsing of the outputs. The pulse-width-modulator compares the incoming ramp and error voltages to form the pulse width modulated signal shown in Figure 20 (the shaded areas). As the error voltage changes, the active time on is varied according to the reference crossing points on the rising and falling edges of the ramp, and the pulse width is varied or "modulated" accordingly. As demand for output current increases, or as the power converter input voltage changes, the change is sensed by the error amplifier, and the error voltage changes. These changes cause the ramp crossing points to shift and the pulse width to vary proportionately. Changes The output control gates are 3 input NOR gates (4 input in the PWM25, 27) controlled by the two previously described signals and the undervoltage lockout! . shutdown circuits. When bipolar transistors are used as the power switches, a period of dead time is re- 6-57 -- Regulation and Shutdown Circuits VrefOUT 0"----1~-----, The regulation circuit provides a 5.1 volt ± 1% source for the internal circuitry and a 20 rnA output at pin 16 (Vref). Also included is the undervoltage lockout which ensures a stable off condition when IC V+ (pin 15) is below 8 V. V+IN IC GROUND 0"'---1 . - - - - - _ TO FIG 3 PIN c IPWMj 60llA SOFT START CAP The soft-start circuit provides protection by bringing the pulse width up slowly. This feature prevents cold start stresses on the SPC components when the power supply is turned on under heavy load conditions. 0 - ' ' - - - - - - + - - &____ FROM V"f SHUTDOWN 0"1O,---'\M~+--J::. The shutdown circuit provides an external control for turning the outputs "on" or "off." When the shutdown transistor (Qs& is "off," a current source from the regulator circuit charges the soft-start capacitor at pin 8. The charge time determines the speed at which the modulated pulse comes up to the required width. When Ql is turned "on" by the undervoltage lockout circuit or by an active high (2.4 V) on the shutdown pin, the soft-start capacitor is discharged to ground which disables the PWM circuit. When Ql is turned "off," the soft-start capacitor charges again, and the soft-start cycle is repeated. PWM125 Regulator & Shutdown Circuit Figure 22 quired to get rid of the stored charge inherent to bipolar transistors. The maximum dead time allowed in the PWM125 is 120 nsec. When MOSPOWER FETs, which have no storage time problems, are used as the power switches, the dead time is set to minimum by connecting pin 7 (Qd collector) directly back to pin 5 (Ct). Do not use the PWM125 with bipolar transistors as there is no dead time control. Use the Siliconix PWM25 , 27 which have the adjustable dead time feature. 6·58 6.1.5 A 500 kHz Switching Inverter for 12 V Systems (AN79-1) The principles of operation may be described by the basic circuit shown in Figure 1, which includes the pulse width modulator (PWM) control circuit; the high frequency MOSPOWER PET Switch; the flyback circuit inductor (L), diode (D) and capacitor (C); and an error amplifier. This note describes the design of a 12 V to ±20 V inverter. The design is of the flyback type, made much more practical by the use of DMOS devices running at a high switching rate. It is an energy transfer circuit, not a voltage or current transfer circuit; the output power is maintained at a constant level for a given pulse width-modulator (PWM) operating point. If the load requires less current, the output voltage will soar. Conversely, if the output current demand increases, the output voltage will sag to maintain the constant output power (V x I). This contrasts sharply with conventional circuits that deliver a constant output voltage per PWM operating point. Maintaining constant power permits simplified circuitry with reduced magnetic and filter requirements. At the heart of this design is the PWM control circuit which provides the control pulse to the DMOS Power Switch in the flyback circuit. The output of the PWM is a pulse whose width is proportional to the input control voltage and whose repetition rate is determined by an external clock signal. To provide the control input to the PWM and to prevent the output voltage from soaring or sagging as the load changes the error amplifier and reference voltage complete the design. They act as the feedback loop in this control circuit much like that of a servo control system. Pertinent waveforms are given in Figure 2; 2a describes the conditions that exist at 50% (maximum) duty cycle and 2b describes those at a low duty cycle. VSUPPL v 1Vsl .....-otf-_-......_OUTPUT Operation is as follows: CONTROL II1II I 1. Between to and t} the DMOS is turned on and applies the supply voltage across L. The drain current is closely approximated as IL = t x V S/L and the final current IL (peak) = (tl - to) Vs/L. The energy stored in L is EL = (t} 2 - to 2) Vs2/2L. Figure 1 6-59 ~OCK E~GE t t _ . L -_ _ _ _ _ _ _ L -_ _ _ _ _- - ' _ ' - -_ __ TIME- I r PWM _ " ' -_ _........._ _ _. L -_ _........_ _ _L-_ _ __ OUTPUT IL~~~ --tO~--~tl-~t2~t~3~---~~--~--, .. a.VOUT + VDlODE~A .. VORAIN J ~ !"II - r-1ftltl Res '0.-oJ "'VI Figure 28 CLOCK EDGE t t t TIME- OUTPUT D 'L .0. PWM 0 0 .0. .0. VORAIN Figure 2b 2. At the instant of tl the VN64GA is turned off and its drain voltage increases to the voltage on C plus the forward voltage drop of D because of the inductor L. This works well when VOUT is much larger than VS and permits nearly all of the energy stored in L to be transferred to C with no large current or voltage spikes. L will be 'TJ VS2 /8 fCLOCK POUT, where'TJ is the overall power efficiency of the circuit. The power losses in the circuit are, in order of importance: A. (lD)2RDS loss in the MOSFET B. ILOAD VF loss in the catch diode D C. Transient charge losses in D due to a slow tum-on characteristic. This actually allows many volts of forward bias on D just at time tl while the diode is attempting to turn on. Tum-off losses are not important in this circuit. D. Loss in L due to hysteresis and saturation effects. The inductor is required to pass all of I = 4POUTI'TJ VSUPPLY, which usually results in magnetic saturation and losses. Fortunately, the higher frequencies allow fewer turns on L, reducing the number of turns and ISUPPLY product, and the core material of L can be high-frequency ferrite, which is less prone to saturation (for a given inductance). E. Simple CSTRA Y V20UT fCLOCK losses, where CSTRAY includes CDS of the FET and CD of the rectifier. 3. Between t2 and t3, no net DC current flows through L, and VDRAIN tends toward VSUPPLY, although a ringing will occur between L and the capacitance of the FET and D. The cycle is repeated at a frequency fCLOCK, such that the power drain from Vs is (1/2(tl - to)2 VS2)/ fCLOCK· If we let the duty cycle 8 = tl - to t3 - to = (t} - to) X fCLOCK, 1 where fCLOCK == - - - , t3 - to 8 VS2(t1 - to) then PIN = --'-"'----2 If 8 Figure 3 is the schematic of a simple 35 watt inverter designed to produce ± 20 V regulated outputs from 12-16 volt inputs. Ul is a simple Schmitt-trigger oscillator with a nominal 50% duty cycle. This duty cycle waveform buffered into Q5 by Q4 and U2 through U6 runs the system at full output power. VS 2 = 1/2 max, then PIN max = --:&,....=--8L lCLOCK The peak current through the DMOS will 4 POUT . closely be - - - ; and the value of mductor 'TJVS 6-60 VSUPPLY II FERRITE BEAD(S) UNITRODE '~~fGNo R21 100 R1 330 1/2W NOTES CAPACITORS IN MICROFARADS UNLESS NOTED RESISTORS IN OHMS, 1/4W, 5% UNLESS NorED tTHESE PARTS MOUNTED ON HEAT SINKS ·T,. T2. T3. LT. L2. L3.l4 - SEE TEXT FOR DETAilS C17 01 QPTC1 ,..- ....... 0,5 GEH11Al I L-+________________~. lN4148 '., " R,. ....- 20K 1K .Lr~\--------I :'L', , 5, f' 1K R13 '5 1K RlO 500 5V ..... ·UST ~ 12K C" 200 pF R17 lOOK 100 kHz, 150 Watt Half·Bridge Switching Power Supply Figure 1 R" 1K All outputs are isolated from the AC power line. The 5 volt output was chosen to be the main regulated output controlled by the pulse width modulator. Feedback from this output is optically isolated from the line side of the power supply. The complete supply is overcurrent protected by sensing the source current in the lower MOSPOWER FET (Q6) and using this signal to shut down the supply. Circuit Board The circuit board layout (Figure 2) uses double sided construction. Most of the traces are on the bottom side of the board while the top side is used as a ground plane. Three ground planes are used - one for the input and control circuitry, one for the ±15 volt outputs and one for the +5 volt output. If a common ground is desired for all DC outputs, both output ground planes may be connected together. Construction Details Plated-through holes are not necessary for making the circuit board, but they would be useful. If platingthrough is not used, all of the components connecting to top traces or the ground plane must be soldered on top of the board in addition to any soldering necessary on the bottom. There are a few connections from one side of the circuit board to the other side that do not have components mounted in them. If plating-through is not used, a short piece of wire must be soldered in these holes to both sides of the board. All solder points on the top side are indicated by an 'X'. Table I shows the recommended drill sizes to be used for drilling the circuit board . Careful circuit board layout is very important for the proper operation of high power, high-frequency switching regulators. Single point grounding is absolutely necessary to prevent ground loops from rendering the circuit totally unstable or inoperable. Ground planes are also required to lessen the effects of electromagnetic interference on the circuit. Presented here is a circuit board layout which is known to operate correctly and reliably. Use of this layout will make the construction of this power supply much simpler and will speed your evaluation of the VN4000 series of high-voltage MOSPOWER FETs. • • 10" Circuit Board (Bottom Side) Figure 2a Circuit Board (Top Side) Figure 2b 6-64 Secondary (2) - Table 1 Recommended Drill Sizes Make all connections to the bobbin according to the parts placement diagram (Figure 3). The following drill sizes should be used on the circuit board: #66 ICI-IC3. 1/4 W resistors. disc capacitors. opto-isolator. QI-Q5. 01-06. C6. Cl3 #60 TI bobbin leads. 1/2 W resistors. CS. C9. T3 secondary. TRI. 1'1. CIS. C21. C22. 02. 0I4 #57 I W resistors. T2 bobbin leads. 07-DIO. C7. 013. C13. CI9 #44 TO-3 lead sockets. line cord #23 1'1. IC4. IC5 and TO-3 screw-mount holes. 5 V CT 3/16" 0ll.0\2 1/4" C5 5/16" Banana jacks T2 - Primary (1) - The primary is made up of a type .of litz wire using several strands of regular enamel wire (refer to Figure 4). Cut 8 strands of #28 enamel wire (about 6 feet long) and place them together in parallel. Twist the ends only together (not the whole length), but do not solder. Fold this twisted bundle of wires in half and wind 8 turns of this doubled over bundle onto the bobbin. Cut the folded over end of the bundle so that there are now 4 ends coming out of the bobbin. Twist the ends of each newly cut bundle. Next, connect one of the beginning bundles (D) to the end of the other (B). This effectively connects the bundles in series, wound in the same direction, to fonn a single 16 tum primary. The purpose of winding in this manner is to equalize the flux across the transfonner core. There should now be two ends of the wire free and two ends connected to each other. Connect the free ends to the bobbin as shown in Figure 3. Make sure all windings are wound tight and neat - do not waste any space. Now put a layer of transfonner tape to cover the primary. Three transfonners are used in this power supply: 1) DMOS drive transfonner, 2) power transfonner and 3) current sense transformer. The winding details explained here should be closely followed, especially for the power transfonner T2. DMOS Drive Transfonner Using the correct bobbin and pot core (see parts list), wind the following: Primary (1) - Power Transfonner Using the appropriate bobbin, wind the following (pin 1 of the bobbin has a notch for identification): Transformers Tl - 30 turns of # 24 enamel wire 20 turns of #24 enamel wire 7915 7815 ~ ~c,~ C 0 I 0 I C ---t -15V + +1SV :!:i... C11,- GND 1,11,i GND TTTT +5V ~5V ~ L3RJR'{~: e11 R'<4 -H- , ,rt R'9 IC2...1.. C'2OPT!' L ADJ R'3~~gt CA 3130 G L4 R'8~~...L ~ ~,R17 -Ilc , 'C'5 ~R16 21 Parts Location Diagram Figure 3 6-65 .. . gSIIICOnIX incorporated l00KHZ-l50WATT .-J SWITCHING POWER SUPPLY IDII Secondary (4) - ± 15 volt secondary: Make another litz wire similar to the primary but this time parallel 6 strands of # 28 enamel wire about 40 inches long (refer to Figure 6). Twist the ends together and double the bundle over itself. Wind 5 turns of this doubled over bundle neatly on the bobbin (41/2 turns for ± 12 V outputs). Cut the double end and connect Band D together and connect to bobbin pin # 11. Connect the two free ends of the bundle to the other bobbin pins. Put a layer of transformer tape over these windings. Secondary (2) - Start-up Winding: Wind 4 1/2 turns of #24 enamel wire (about 20 inches long) evenly on top of the primary winding. Connect the ends as shown in Figure 3. Put a single layer of transformer tape over the start-up winding. Faraday Shield - This is a shield used to minimize radiated electromagnetic interference (EMI). Cut a piece of 5/8 inch copper tape about 3 inches long and wrap this around the existing windings (refer to Figure 5). Do not make a complete loop -leave about 1/4 inch between the ends so that they can't touch. Solder a small stranded wire (#20) onto the shield and connect it to the bobbin as shown in Figure 3. Put a layer of transformer tape over the Faraday shield. Secondary (3) - 5 volt secondary: Make up some insulated copper tape by placing transformer tape on one side of a 10 inch long piece of 5/8 inch wide, 2 mil copper tape (refer to Figure 7). Make two of these insulated tapes. Make sure the transformer tape is slightly wider than the copper tape so that the windings don't short to each other. Wind both of these insulated tapes at once (like bifilar tape) for two turns. Connect the beginning of one tape (A) to the end of the other tape (D) - this is the 5-volt center tap. Connect three # 18 stranded wires (or # 18 ribbon cable) in parallel to each of the free copper tape ends and to the center tap. Spread out the stranded wires flat when soldering to the copper tape - this makes a much neater and less bulky connection. Connect the ends of these paralleled wires to the output rectifiers and P.C. boards as shown in Figure 3. Wrap a final layer of transformer tape to hold everything together. Step 1 - Parallel 8 strands #28 wire I z::::::::::::ss : TWIST ENDS Step 2 - Fold In half ·c. .---- A c .... ·-----o Step 3 - Wind on bobbin T3 - Current Sense Transformer Place the windings directly on the toroid: Secondary (2) - Wind the secondary first. Wind 7 turns of #20 enamel wire (about 10 inches long) onto one side of the toroid (Figure 8). Primary (1) - Form the primary by soldering 2 strands of # 16 enamel wire to the circuit board connections (Figure 3). Run these strands through the center of the toroid. This forms the one turn primary. Solder the secondary into the board as shown (Figure 8). Step 4 - Connect C and A to pins 6 and 7 SOLDER WIRE TO THIS SIDE AND CONNECT TO BOBBIN PIN NO 1 Faraday Shield Figure 5 Primary Power Transformer Figure 4 6-66 Step 1 - Parallel 6 strands #28 wire A Step 1 - Make two insulated copper straps --------..--- TAPE #K \ TWIST ENDS Step 2 - Fold In half ( Step 3 - Step 2 - Place one strap on top of the other with leads on opposite sides. Wind on bobbin A D Step 3 - Wrap two turns of this double copper tape onto the bobbin. Connect A to D and solder this center tap into the circuit board. Connect the other free ends, Band C, to diodes D11 and D12· Step 4 - Connectthefree ends to bobbin pins #10, 12. Connect doubled over end to pin 11. C (CONNECT TO PIN 10) 5 V Secondary Figure 7 Mount IC4 and IC5 onto their heat sinks with thermal compound. IC5 should be insulated from the heat sink. Use metal screws for mounting IC4 and IC5 and use plastic screws for the other mounting screws for the TO-66 heat sinks. Cut off the center lead of each regulator and insert the other two pins into the circuit board. ± 15 V Secondary Figure 6 Output Inductors Ll and L2 are identical. Wind one tum of # 18 enamel wire through each core and solder to the circuit board. Schottky rectifiers Dll and D12 mount directly on the heat sink with thermal compound. Use star washers for a good electrical connection when bolting rectifiers Dll and D12 to the board. L3 is also one tum, but use three strands of # 18 in parallel. L4 is an air core inductor. Close wind 10 turns of # 16 wire on a 5/16 inch diameter form. Miscellaneous Heat Sinks Use star washers on both sides of the board when mounting C5. IC sockets may be used for ICl, IC2 and Opto 1. Mount the TO-3 heat sinks off the board with 1/4 inch spacers (to make space for R5, R6, R8, and RI9). No insulating washers are needed, but heat sink compound should be used. ALWAYS use an isolation transformer when connecting an oscilloscope to look at waveforms on the primary side of the power supply. Do not mount Q3 until after the initial test procedures. 6-67 will not change the output. No significant current should be flowing from the high voltage supply at this time. Check the ± 15 volt outputs for the correct voltage. While monitoring the supply voltage on pin 12 of ICI (using a floating voltmeter) connect a load to the 5 volt output to draw about 1 ampere. The supply voltage on pin 12 should increase to about 15-20 volts if the power supply winding #2 on T2 is working correctly. If everything works correctly so far, disconnect all power supplies and install Q3 in the circuit board. Using a variac or DC power supply and a floating voltmeter (or an isolation transformer and a nonfloating meter), increase the input voltage to the line cord to about 20 VDC or 40 Vrms while monitoring the supply voltage on pin 12 of ICI. This voltage should level off around 10-12 volts. Connect a minimum load to the power supply (5 n, 5 W) and increase the line voltage to full voltage. ICl's supply voltage should increase to about 15-20 volts. Current Sense Transformer Figure 8 Power-Up Procedures Even though this is a proven circuit board, the control circuitry should be checked separately before powering up the complete supply. To do this, connect an isolated + 12 volt supply through a diode between pin 12 of ICI and ground (Figure 9). Use an oscilloscope to check the drive signals at pins 9 and 11 of ICI. These signals should be in-phase, quasi-square waves at a frequency of 100 kHz (Figure lOa). When these signals check OK, look at the gate waveforms of the MOSPOWER FETs. These waveforms should be out of phase (Figure lOb). 07's waveform may have some overshoot. With Q3 still out of the circuit board, connect a variac or a high voltage DC power supply to the AC input. Slowly increase this power supply voltage (the control circuitry is still running with the floating 12 V supply) while monitoring the output voltage. When the 5 volt output gets somewhere between 4.5 volts and 6.5 volts the supply should begin regulating and further increases in the input voltage The power supply is now ready for use. Adjust the output voltage to 5 volts using RIO. Adjust the current limit R24 with the ± 15 volts fully loaded and the + 5 volt output delivering about 25 amperes. A minimum current of about 5 amperes must be drawn from the 5 volt output for the ± 15 volt outputs to be able to deliver 1 ampere each. The power supply may now be plugged in directly to the power line for operation. The only requirement necessary is to have a minimum load of about 1 ampere at all times on the + 5 volt output. Power Supply Features and Specifications +15 V FLOATING SUPPLY n ., ~PINI2 5 Volt Output • 20 amperes output current • 0.2% line regulation (±20% line variation) • 0.4% load regulation (no load to full load) • < 100 m Vp-p ripple and noise at full load • Output over-current protection • :;;;0.5 mS transient response time (no load to full load) • Over-current protected INPUT GROUND Power-Up Connection Figure 9 15V~ I I I: o 1 I I I: ~ : I II ~! I: I: I PIN 11 I :: 15 Volt Outputs • 1 ampere output current each • 0.2% line regulation • 1.0% load regulation • < 10 mV ripple • Short circuit current limiting !Hj !Hi o-----LJ lLJJ ~9 15V a) TL494 Drive Waveforms o------.w!I: n11W! !t: n~ 15V 15V~'!iiii o I" I " II VN4000A Features • 4000 volt B VDSS • < 1 ohm on-resistance • < 100 nS switching times • Rugged safe-operating area • No secondary breakdown Co b) DMOS Gate Waveforms Drive Circuit Waveforms Figure 10 6-68 Parts List Part # Resistors RI R2. R(). R9. R12. R13. R15. RI9 R3. R7 ~ R5. RS RiO Rll R14. Rl7 R16. R23 RI8 R20 R21 R22 R24 Capacitors CI C2 C3. C14. C16. Cl7 C4 C5 C6. CS. C9 C7 CiO. Cll Cl2 Cl3. CI9 CI5 C18. C2J. C22 CI9 C20 Integrated Circuits ICI IC2 IC3 Quantity 2 I 2 2 2 I 4 2 4 Description 5.1 KO ±5% 1/4 W Resistor I KO ±5% 1/4 W Resistor 3300 ±1O% 1/2 W 33 Kn ±1O% I W 500 ±5% 1/4 W 500 O± 10% Trimpot 1.2 KO ±5% 1/4 W 100 KO ±5% 1/4 W 4700 ±5% 1/4W 20 KO ±5% 1/4 W ISO ±1O% I W 1000 ±5% 1/4 W ISO 0 ±5% 1/4 W 100 0 ±1O% Trimpot Recommended Mfg. Allen Bradley 0.001 fLf Ceramic Disc 0.05 fLf Ceramic Disc 0.1 fLf. 25 V Ceramic Disc 1.0 fLf. 25 V Electrolytic 710 fLf. 200 V Electrolytic (320) 47 fLf. 25 V Electrolytic 1.0 fLf. 400 V TRW-35 2 fLf. 25 V Tantalum 200 fLf Mica 220 fL f. 10 V Tantalum 5 pf Mica or Ceramic 0.01 fLf. 5 K V Ceramic 10 fLf Electrolytic 6.S fLf Electrolytic TRW TlA94 PWM IC CA3l30 Op-Amp TlA30 Voltage Reference Texas Instruments RCA Texas Instruments 6-69 Sprague Mallory 227KOIOPIG Parts List (continued) Part # Quantity Integrated Circuits (continued) IC4 IC5 Description Recommended Mfg. /LA7815UC+15 V Regulator (JI,A7812UC+12 V) /LA7915UC-15 V Regulator (JI,A7912-12 V) Fairchild Fairchild Dlodes/Rectlfters D" D3 - D6, D14, DI5 D2 D? - DIO Dl1, DI2 DI3 D14 Transistors 6 I 4 2 4 IN4148 IN4107 IN5804 IN5831 IN5406 IN5360 Diode Zener Fast Recovery Schottky Rectifier Zener Motorola Motorola Unitrode Unitrode Motorola Motorola QI,Q4 Q2,Q5 Q3 Q6,Q7 Ferrites & Accessories TI TI Bobbin T2 T2 Bobbin T3 LI, L2 L3 Miscellaneous Optol THI FI TO-3 Heat Sink TO-220 Heat Sink TO-3 P .C. Sockets Dl1, DI2 Heat Sink Output Banana Jacks 3-Wire Line Cord Fuse Block for FI Transformer Tape Copper Foil 2 2 2N4400 2N4403 MPSUIO VN4000A MOSPOWER FET Motorola Motorola Motorola Sihconix F1146-1-06 Pot Core B475-1 IR8031-1 B680-2 BBR7727-1 Toroid F1146-I-TC9-315 F2037-J-TC9 Indiana General Indiana General Indiana General Indiana General Indiana General Indiana General Indiana General Hl1AI Opto-Isolator 3D304 Thermistor 2 A Fast Blow Fuse LAT03B5CB LAD66A4CB LSG-3DG2-1 E240-001 G_E. Midwest Components, Inc. Buss !ERC !ERC Augat IERC Type 10 Epoxy Film Type 1194 3M 3M 2 2 2 2 4 5 6-70 6.2 Solid State RF Generators for Induction Heating Applications © 1982 IEEE. Reprinted, with pennission, from Conference Record Industry Applications Society IEEE lAS - Annual Meeting, October 4-7, 1982, San Francisco, CA, pp. 939-944. Abstract Radio frequency power for induction heating has traditionally been generated by vacuum tube oscillators. These generators use high voltage tubes and generally operate in the frequency range of 100-500 kHz, 1-400 kW power output at approximately 50-60% efficiency. Although thyristor SCRs and bipolar transistors are marketed at this time, they are unsuitable due to either slow switching or low power performance. Until just recently, solid state devices with both high-frequency and high-power capabilities were not available. times. For surface heating and non-magnetic parts, high frequency power is required. Therefore, the power source must be capable of supplying a minimum of several kilowatts of power in the radio frequency range. In addition, the power supply must have adequate control, protection and monitoring circuits. A new power semiconductor - the power MOSFET - a highspeed field effect transistor, can now meet these criteria. The power MOSFET switching time is in the order of 50-100 nanoseconds and can generate many kilowatts of power at frequencies to 500 kHz. Over the past 50 years, the high voltage vacuum tube was the only device available for radio frequency power generation. Semiconductors, such as SCRs and bipolar and Darlington transistors, have appeared in the last decade. These components work well in the frequency range up to 10 kHz, but they do not have the characteristics that are required for a radio frequency power source necessary for induction heating applications. In addition, these solid state devices are limited by slow switching speeds and/or low power ratings. This paper describes a solid state RF generator using MOSFET transistors for the power semiconductors. The RF generator is a load tracking, resonant inverter capable offull power output over a frequency range of 100 kHz to 500 kHz. Output power levels are in the kilowatt range with induction coil KVAs to 200 KVA (400 V and 500 A) and more. This solid state RF generator has similar characteristics to the more familiar low frequency power converters presently used in the industry; namely, all solid state, high efficiency (approaching 90%), small and compact, and no vacuum tubes or moving parts. A new switching device, the power field effect transistor, is capable of both higher power outputs and significantly higher switching speeds. Some various . ' market names for these transistors are VMOS, MOSFET, HEXFET and DMOS (these are the manufacturer's distinct trade names). The availability of such components have been disclosed and described in increasing detail since 1979 or so [1, 2, 3, 4]. As a result, Westinghouse Electric Corporation has developed and manufactured a solid state, radio frequency power supply using the power MOSFET in the inverter circuit design of the RF generator. Introduction Power MOSFET Transistor The art of induction heating is to unifonnly heat metallic workpieces at specified temperature and The power MOSFET is a field effect transistor with ratings presently ranging from 50 V/60 A to 1000 VI 6-71 3 A among the various manufacturers. Figure I depicts an N channel and a P channel MOSFET transistor showing polarity of the terminal potentials and current flow for normal transistor action. The MOSFET contains an internal, reverse P-N junction diode (shown dotted in Figure I) which has the same current rating as the transistor. 5 This diode is a viable circuit element that can be used, just as any externally connected discrete diode, for a reverse current path around the transistor. D(+) example, a MOSFET having an input capacitance Ciss = 1000 pf, passes a gate current of I A when driven with a gate-source voltage rise time of 20 V/20 ns. At RF frequencies, these drive requirements can become formidable. A limiting factor with the MOSFET is the recovery time of the reverse diode. This internal diode is relatively slow, having a recovery time which can be in the order of 200 ns or more compared to FET transistor switching times of 20-100 ns. These differences in speeds must be recognized and dealt with in certain switching circuits. D{-) ._ IJ-* I- .~J-* 1'" ' '19--" S(-) N Channel "'I9-- J S(+) P Channel VDe INPUT Power MOSFET Symbol Shown with Internal Diode & Polarities of Voltage & Current Figure 1 The MOSFET transistor is a voltage controlled device with an insulated gate (G) which controls current flow between the drain (D) and source (S) terminals. A positive gate-source potential applied to the N channel MOSFET causes current to flow from the drain to the source. For the P channel MOSFET, the opposite is true: a negative gate-source potential causes current flow from the source to the drain. The drain current can be controlled linearly by the gate-source voltage or can be "switched on" by gate . overdrive to a level determined by the impedance of the external circuit. With sufficient gate overdrive, the drain-to-source characteristic appears resistive with "ON" resistances for high current MOSFETs being less than an ohm. This "ON" resistance has a positive temperature coefficient which forces current sharing among paralleled devices, eliminating the need for external current balancing components and making paralleling relatively easy. e.g =RFT HEATED _WORK PIECE L. Basic RF Inverter Figure 2 Solid State RF Generator A. Basic RF Inverter Figure 2 shows the basic circuit of a I kW resonant inverter developed for induction heating. MOSFET transistors QI-Q4 are configured as a full bridge, voltage fed inverter with the internal diode of each providing the return path to the DC source for reactive currents. For higher powers, paralleled MOSFET transistors are used; for example, four paralleled 6 A/450 V devices in each leg for a 3 kW rating. The DC terminals of the inverter are tightly coupled to RF bypass capacitor (RFBC) whose capacitance is sufficient to pass the AC component of inverter input without substantially changing its DC potential. The AC terminals of the inverter drive the RF load circuit which is essentially a high Q series resonant circuit formed by tuning capacitor. Ct. and induction load coil, Lt. Transformer RFT matches the load impedance to the VA capability of the inverter. while coupling capacitor RFCC prevents any DC current from flowing in the primary winding and Drain-source switching speeds can be very fast, as low as 20-100 nanoseconds, depending on drive circuit source impedance and gate capacitance. MOSFET transistors do not exhibit minority carrier storage effects as do bipolar transistors and switching times are determined primarily by how fast the gate capacitance can be charged and discharged. The fast switching speeds result in a low and thermally manageable switching energy loss per cycle which is requisite for RF operation. The steady-state gate-source input impedance is very high, being essentially capacitive. But dynamically the gate must be sourced and sinked by a high current source to produce fast switching speeds. For 6·72 Thus, MOSFET diodes I & 2 are conducting when MOSFET transistors I & 2 are turned on eliminating short circuit recovery problems. saturating the core. These two components are sized for minimal effect on the resonant circuit parameters, namely: RFCC »(~~y Ct Figure 3 shows "light load" inverter waveforms resulting from driving of the series load at a frequency (1) I Leakage Inductance of RFf «(~~y f> > 27T "LtCt Lt (2) 01,a2 I Eo Primary Inductance ofRFT » - - x -1- (3) wmin 0 EGS Output Where: Np E&I Primary-secondary turns ratio of RFT FETI's Eo Rated RMS output voltage of inverter Diode "s 10 Rated RMS output current of inverter Input I wmin Minimum output frequency of inverter Devices Ns oj Conducting In operation, the MOSFET transistors are switched as diagonal pairs: Q I & Q2 alternating each half cycle with Q3 & Q4 to provide a square wave voltage output at the AC terminals of the inverter. The waveform of the output current depends on the inverter output frequency which is the switching rate of thc MOSFET transistors. Driving the series resonant load off resonance - i.e. at a MOSFET switching frequency differing from the natural resonant frequency of Ct and Lt - results in low output current, while driving it at resonance results in maximum power to the load coil. In fact the output current is controlled in a closed loop by varying the driving frequency. Diode FET Diode FET 1,2 1,2 3,4 3,4 Inverter Waveforms for Light Load Figure 3 The output current takes the form of an "inductive ramp" with positive current from the DC source flowing through MOSFET transistors and a nearly equal negative current being returned to the source by the MOSFET diodes. The net DC current is nearly zero and very little power is delivered to the highly reactive load (PF = 0). Figure 4 shows the waveforms Q1,D2 The differences in switching speeds between the MOSFET transistor and its relatively slow reverse diode imposes an operational limitation on the inverter. Had MOSFET diodes 3 & 4 been conducting at the time MOSFET transistors QI and Q2 were switched on, they would have failed to recover in time to prevent short circuit currents from flowing between the positive bus and negative bus through the oncoming transistors and offgoing diodes. Commutation of current from a diode to a FET in adjacent legs of the inverter occurs whenever the output current leads the output voltage. One simple solution to the problem is to avoid leading currents and assure that the output current always lags the output voltage (lagging power factor). This is accomplished by always gating the MOSFETs at a frequency greater than the resonant frequency of Ct and Lt. With such a lagging power factor, current is always commutated from "its own diode" to the MOSFET transistor being gated on. EGS Output E&I oj oj/,/!'>b I FETl's F I o I 1 I I ;: I I I I : / V I -.;;:::::;;> / I ..... ,1 1 I Diode "s I Input I Conductmg DeViceS Inverter Waveforms for Heavy Load Figure 4 6-73 are in the MOSFET "tum on" charging path being dimensioned for a circuit Q = 1. The "tum off" discharge path includes only R2 & R3 (DI shorts Rl) increasing the circuit Q = 2 resulting in a faster discharge than charge of the input capacitance. This provides an asymmetrical gate drive signal with relatively slower tum on time and relatively faster tum off time. The result as shown in Figure 6 is that the "off going MOSFET" reaches its gate threshold voltage before the "on coming MOSFET" attains its threshold, providing a gating dead time of about 50 ns for the pair. Figure 7 shows G-S tum on tracking waveforms of diagonally fired MOSFETs. for the same series load being driven at nearly resonance by decreasing the inverter output frequency. The output current is a sinusoid with a high amplitude. In this situation a mostly positive current flows from the DC source through the MOSFET transistors with very little negative current being returned by the MOSFET diodes. The net DC current is large and "heavy power" is delivered to the highly resistive load (PF = I). In both extremes, the commutation of current from a MOSFET diode to "its own MOSFET transistor" is illustrated. B. Gate Drive Circuits The gate drive circuitry shown in Figure 5 is designed to perform the following functions: Since the gate drive is an alternating source, a significant negative potential (see Figure 6) is on the gate of the "off-going MOSFET" when the "on coming MOSFET" begins to switch. Thus, transient D-G currents caused by switching of the adjacent MOSFET should not cause the "off going" MOSFET to tum back on spuriously. I. Charge and discharge the input capacitances (Ciss) of the inverter MOSFETs for drain-to-source switching times of 100 ns or less. 2. Provide a dead time between tum on and tum off of alternate firing MOSFETs serially connected in one pole of the inverter to prevent short circuit "shoot through" currents. 3. Provide a low impedance to the gate and source of each MOSFET during steady state inverting operation to prevent possible misfiring by the switching of the adjacent device. [6] 4. Prevent misfiring of the MOSFETs during shutdown. - - -- 1'\. \ 03 - - . . . .v - -- - I POLE OF r---------~ 02 -- ir"""' Lx' -- - -- [,( V V X' :=f ./ -- V 03 ~ -- - - -\ - -I=- '- I--f-" 1 10 Vldlv 50 nsld, ... Photograph IS double exposed to show on and oNgOing dead times for the deVices \ 02 INVERTER OTHER PARALLELED Q1 GATE CIRCUITS - - " r-- + DC MOSFET G-S Turn On-TUrn Off Waveforms for Alternate Firing Devices Figure 6 DRIVER 01 04 - ~ AC o - OTHER PARALLEL!::D 04 GATE CIRCUITS , _________ -DC L 03 - -- ~ 04 -~ - -- 04 I I -- ~/ /- - - - ~ ?"" - - - ~ ;;::::::; ~ 10 Vidlv 50 nsidlv ~ ....::~.\ -f~ - - -- 03 -- Photograph IS double exposed to show on and offgorng dead limes for the deVices '-.:==--- _ MOSFET G·S Turn On-Turn Off Waveforms for Series Fired Devices Figure 7 Basic Gate Drive Circuits Figure 5 MOSFETs Q9 and QIO and transformer DT form a push-pull driver with four isolated secondaries for gating the inverter power devices. The turns ratio from 'h primary to each secondary is I: 1 being specially wound for low leakage inductance in the order of 0.4 fLH. This unavoidable transformer leakage inductance plus stray inductance in the same order of magnitUde as the leakage forms a RLC circuit to charge the input capacitance of the MOSFET. Resistors RI, R2 & R3 If the driver were stopped by removing pulses from driver MOSFET transistors Q9 and QIO, the current established in the primary of DT would freewheel through the other 'h primary and reverse diode of the device that was off. This would result in possible unscheduled gating of the inverter MOSFETs until the energy in DT transformer was dissipated and then result in an open circuited G-S drive connection thereafter. If the tuned load on the inverter was still ringing 6-74 3,',,60HZ DCFU II DCCT i--1::::I-- ::~Bi1~Eo~ RFBC G1 GATING PULSES G2 G3 G4 -----"I r-----, F==l I 1-, I "I 04 L __ ---1r---1L-________ ----l I I Q2 1==1 ciiJE ~ G2 RBO:RD~ L _____ ____ ---l S2 L __ -.l t~----+-----<-~tt4---:=======~===1!::===~--1 -::- '------------0- 11 RFCT CONTROL CARD RFCC Basic RF Generator Figure 8 down through the inverter MOSFET diodes to RF bypass capacitor, the switching of the diodes - Le_, rapid charge of D-S voltage - might now gate on the open circuited adjacent MOSFET causing a "shoot through" and failure. To alleviate this condition, driver MOSFETs Q9 and QIO are both turned on at the STOP command while series MOSFET Qs is turned off. Thus, the driver transformer is shorted at turn off and secondary drive voltage is reduced to nearly zero immediately. This presents a low impedance to the G-S drive circuits diverting any transient D-G currents from the gate of inverter MOSFET and preventing abnormal tum on. inverter powered from 3 phase than from single phase given the same voltage stress on the transistors. Radio frequency filtering by RFL choke and RFFC feed through capacitor minimizes RF feedback (at twice the output frequency) to the AC power lines. The DC surge suppressor holds down any surge voltage across bypass capacitor RFBC during the following situations: 1. Turn on of the main circuit breaker and LC resonant charging of RFBC. 2. Turn off of the inverter gating under heavy load and transfer of energy from the RFL choke to RFBC. 3. Tum off of the inverter gating under light load and transfer of energy from the high Q output circuit to RFBC. C. KW RF Generator Circuits The basic schematic of the overall 3 KW RF generator is shown on Figure 8. A 3 phase full wave diode rectifier is used to effectively utilize the voltage rating of the MOSFET transistors in the inverter. This is so because a single phase full wave rectifier would stress the inverter transistors with a 1.57/1 peak to average voltage (about 393 V peak for a 250 V DC supply) unless an elaborate DC filtering and lightload bleeder were used. The peak to average stress with the 250 V DC 3 phase supply is 1.049/1 or only 263 V peak. Since induction heating loads rarely have waveform modulation restrictions (especially when 3 phase diode rectifiers are used) filtering is quite unnecessary. Thus, about 50% more power can be handled by an The inverter bridge has four paralleled MOSFET transistors per leg mounted on a common water cooled heat sink. The gate circuits of each transistor is as shown in Figure 5. Four such circuits are mounted on a FET drive board and assembled to the heat sink for each leg. Paralleling of the 'four gate drive circuits is done by one set of leads from the appropriate driver transformer secondary. Each inverter leg assembly contains a snubber network (RN, CN), tranzorb voltage suppressor network (VZ, DZ) and DC equalizing resistor (RO). 6-75 - I D. Control The four inverter leg assemblies (QI-Q4) are interconnected in a symmetrical layout by multiple sandwiched, flat bus, such that equal and opposite currents are flowing to minimize inductances. This low inductance technique is used from RFBC bypass capacitor, through each drain-source tie, to the RF output. The total inductance from DC input to RF output is in the order of 0.3 /-tH. Basic control requirements for the RF generator are: 1. Control the RF output current (and necessarily the output power) by a closed loop system which effects changes in output frequency to excite the series load nearer to or further from its natural resonance. 2. Detect the phase angle (rp) of output current relative to output voltage and "switch in" limiting phase control to maintain a worst case lagging phase nearly zero. This is requisite for two situations: (1) light load where the "asked for current" by the reference is higher than can be achieved at resonance. This would result in an out-of-control situation with the frequency sliding past resonance to the low frequency limit. (2) to prevent improper commutation of current from the slow reverse connected MOSFET diodes to the fast transistors. 3. Detect voltage on the series tuning capacitor (Ct> and "switch in" limiting voltage control where excessive potential would occur as with higher than expected circuit Q. 4. Provide high frequency and low frequency limiting. Three RF current transformers provide control and protection signals to the controller: • RFCT provides a closed loop feedback signal for control of the RF output current and for load overcurrent trip. • rp CT provides a signal for output phase measurement and limiting. • DCCT provides a signal for instantaneous trip of the gating for an inverter fault. The output rating of the 3 KW RF generator is nominally a 250 V peak square wave at 18.7 Arms (sinusoid). The output voltage remains nearly constant, except for 60 Hz line variations, whereas the current will vary in amplitude as required. The fundamental of the square wave (E 1 = .9 x 250 = 225 Vrms) is the exciting voltage for the series resonant load circuit. RF induction load coils exhibit Q's in the order of 20-60. Thus quite high potentials (4500 V-13,500 V ideally) would be developed across a coil and tuning capacitor connected directly to the RF output terminals when driven at the resonant frequency for maximum power. In general, RF load coils . at 3 kW or so, can have much less impedance than 4500 V/18.7 A = 240 ohm and generally require impedance matching. Figure 9 shows the basic control scheme which implements the aforementioned requirements. It is a straightforward closed loop system with the operator's control potentiometer PTI providing the current reference Ic and RFCT/RECI providing the current feedback signal Ifb to OAI error integrator. The output of OAI decreases the frequency of pulses from the VCO (which is twice the output frequency) until zero error is achieved; i.e. the magnitude of output current is satisfied. Pulses from the VCO clock the timing flipflop whose Q and Q outputs drive OR gates ICI2A,B and ICI2C,D alternately at lh the VCO frequency. The OR gates drive emitter follower EFTI and EFT2 which, in turn, provide low impedance gating signals to the driver N channel MOSFETs Q9 and QIO. The usual RF matching transformer is air core with considerable exciting current and poor primary to secondary coupling. Such a transformer is not suitable for use with an inverter because of the reactive current and voltage requirements. Rise time and fall time at the gates of Q9 and QIO are about 10 ns with drain-source switching times in the order of 20 ns. The ICI2A,B and ICI2C,D paralleled pairs of OR gates are paralleled within one quad IC to increase current sinking and sourcing to enhance their switching times. All logic elements are CMOS operated at 15 volts. This allows direct interfacing with bipolar and FET transistors in the controller without need for level conversion. A universal, core type transformer (RFT) was developed to suit a 54:1 load impedance matching range. 7 Split primary and secondary windings on a 2 mil strip wound core are seriesed or paralleled to provide output voltages and currents from 5.1 V/823 A to 37.5/112 A in approximately 15 steps. Thus induction coils with impedances ranging from 102 V/823 A to 2250 V/112 A (20 :;;; Q :;;; 60) can be matched at the 3 kW level. The transformer is designed to operate from 100kHz to 500 kHz with a maximum primary exciting current of 1 amp and maximum loss of 94 watts. A high STOP or FAULT signal from the sequencing and protective logic circuits simultaneously make the 6-76 C33 q. PHASE SHIFT CONTROL REC2 R42 DT +15 V (INTERRupn GATE DRIVE PT' REC 1 Control System Figure 9 outputs of OR gates IC12A,B and IC12C,D a high. Driver MOSFETs Q9 and QlO are both turned on shorting the primary of the driver transformer (DT) for low impedance stopping of the inverter gate drive pulses. At the same time the -15 V gate drive signal to the P channel series clamp MOSFET Qs is removed, disconnecting the drive power supply from the shorted driver. Output Input VI Vdl Vep 0 0 0 1 1 0 0 I 1 0 1 Series capacitor voltage limiting occurs when the voltage sensed by transformer CPT and rectified by REC2 tends to exceed the maximum level desired. Capacitor voltage limit pot PT3 sets the maximum level at Vc* . When rectified voltage signal Vc is less than Vc* , integrator OA2 has a negative output back biasing DI5 and disconnecting OA2 from summing node SI to OAI. Should Vc tend to exceed Vc" , the output of OA2 goes positive and is connected to OA1 summing node. This constitutes additional negative feedback to OAI which "makes up" the existing difference between Ic* and 1tb limiting the VCO frequency from further reduction and holding the capacitor voltage at the limit level. 1 Thus, an output occurs from the EXCLUSIVE NOR gate whenever two 1's or two O's overlap, resulting in an average output voltage versus phase of the two square waves as shown in Figure 11. This "phase output" after processing by OA5 integration, OA6 inverter and diode D16 provides negative feedback to SI summing node of OAI whenever it exceeds the minimum desired phase determined by the setting of PT2 potentiometer. The VCO frequency is limited from further reduction holding the phase angle between voltage and current at the limit level. The interesting part of the phase detector lies in the development of the VI and Vdl input signals to the EXCLUSIVE NOR gate IC3C. The phase detector circuitry is shown in Figure 10. Basic phase detection occurs with the EXCLUSIVE NOR gate IC3C. The inputs are square waves representative of the RF output current (VI) and RF output voltage (Vdl). The truth table for EXCLUSIVE NOR gate IC3C is as follows. First it should be recognized that the phase characteristic shown in Figure 11 is really not suitable for stable closed loop control. This is because the phase 6-77 - I C2 +15V "31 OCT I~II 01. PHASE SHIFT CONTROL Vd Phase Detector Figure 10 (15 VOL.TS) ---:-,'---+-*-1-'-''-7----1--(75 VOLTS) 90 180 ~4---f~-~~~~~--_r--:~~ 36. 270' 90 90 270 Average Output of EXCLUSIVE NOR Phase Detector Figure 11 Average Output of EXCLUSIVE NOR Phase Detector with 90· Lag Figure 12 detector average output voltage does not monotonically increase with variation of cp from 90° lag to 90° lead. At cp = 0°, the slope changes and the average output decreases for further increasing leading phase. Therefore, detection at cp = 0° is hazardous since the phase control loop would become unstable with each incremental increase in cp incrementally decreasing the error signal to OA5. This results in increasing error to OAI which necessarily drives the frequency of the VCO to its lower limit giving nil current output at cp = 90° lead. The solution to this problem is to phase shift the current 90° lagging and change the characteristic to that shown in Figure 12. Thus, at cp = 0°, should the phase tend to go leading, the phase error would tend to increase resulting in more (not less) feedback to hold the phase at the desired level. This is accomplished by wideband amplifier OA3 connected as an integrator. OA3 integrates the current signal from cpCT which is squared by ZD clamp network into a ramp (see Figure 13). The integrated current waveform from OA3 is AC coupled to comparator OA4 which generates a square wave at 90° lagging (almost) from the original current signal. The lagging square wave is further "squared up" by EXCLUSIVE NOR gate IC3A into VI. The second problem is in the "almost" 90° lag generated by OA4 comparator. It happens that there is a constant, added delay time (t) of about 200 ns between the actual RF current and output of OA4 - mostly caused by OA4 (an LM211 high speed comparator). This fixed time delay is formidable since it represents a variable phase angle delay of 7.2°_36° when the frequency is varied from 100 kHz to 500 kHz. The problem is further compounded by a constant lead time (t') of Vd voltage signal from IC12A,B which is a digital representation of the RF output voltage. Vd leads the actual RF output voltage by about 300 ns. 6·78 OUTPUT CURRENT SQUARED CURRENT SIGNAL INTEGRATED CURRENT SIGNAL =1~VZD~~I H--I'----+--+-++"'+--+-f-+---+-I--H ==-J 01 50 Vldlv 2 AJdlv ~r-f+-+-t--H"-+-"-IIIr+--H EOC '" 242 V IOC=134A HII---+-+--+-++-+--+-f--HIII+--H -- ,:............... f '" 247 kHz ............... vI TPl OELAYED CURRENT SIGNAL MOSFET Voltage and Current Waveforms Figure 14 OUTPUT VOLTAGE SOOns Vd LOGIC GATE VOLTAGE SIGNAL vdl OELAYED VOLTAGE SIGNAL ,l ,, IrTP:!2_ _~ "'", , GIn : TP8 PHASE DETECTOR OUTPUT - ~ ,, V,I, ~jVERAIGE VALUE) o I .. '\ \ Phase Detector Waveforms Figure 13 IOC=137A f= 226 kHz ~ ~~ I The solution to this problem is to make the voltage signal Vdl lag the actual RF output voltage by the same fixed time as the current signal VI lags the output current. Since the EXCLUSIVE NOR phase detector measures the relative phase of VI and Vdl, the absolute phase of each is unimportant as long as they are equal. To accomplish this, delay line DLl and adjustable vernier capacitor C50 on the output of buffer gate IC24D provide most of the required time delay (t' + t). The remaining is provided by the propagation times of the squaring gate IC3B and paralleled delay line buffers IC24A,B,C. 100V/dlV 10A/d1Y EOC = 225 V / RF Output Voltage and Current Waveforms Figure 15 E. Test Results The RF generator was tested from a 1 kW output level using 4 HPWR-6501 MOSFETs to over 3 kW using 16 MOSFETs, 4 paralleled per leg. Some pertinent data and statements about those results follow: Solid State 3 KW, 100 kHz-450 kHz RF Generator Figure 16 1. Waveforms of voltage and current (see Figures 14 and 15) were as expected, except that MHz ringing at current commutations were significant. Worst case D-S ringing occurred off resonance with maximum EDS = 370 V at 250 V DC. 2. Current sharing among the paralleled MOSFETs was excellent with a worst case unbalance of 13.5% from the mean and a typical unbalance of less than 10% measured. The only precaution taken for paralleling was symmetry in circuit layouts and matching of gate threshold voltages (Vt) as follows: 3. Over 3 KW of output power was achieved with a _ typical set of recorded data tabulated below: Edc Ide Eo1 101 Volts Amps Volts Amps DC DC ons rms 236 16.6 198 > kHz 18.74 387.2 Degrees Lt = 30 p,H Ct = 3466 20.9 (1) Above data for RLC load - Vt within 1,2 V for devices in one inverter leg. Vt within 1,2 V for groups in alternate firing legs. Vt within 1 V for groups in diagonal firing legs. DC·RF Po Efficiency Watts % (Calculated) (Calculated) 88.5 no transformer 0.0055 uf R = 9.87 ohm (2) MOSFET T03 case temperature rise above inlet water < 5°C 6-79 I Conclusions References The objective of this project was to investigate the feasibility of using power MOSFET transistors for RF power conversion and to achieve at least 1 KW output at 450 kHz. A resonant inverter approach was chosen using the highest rated available MOSFETs. We were learning how to use the high powered MOSFET at about the sarne time that semiconductor manufacturers were gathering data for their applications. Our overall objective was to develop basic techniques to eventually achieve tens of kilowatts as higher nited devices became available. [1] [2] [3] [ 4] A 1 KW model and a 3 KW production unit were built that met the goals of power, frequency and efficiency. Significant ancillary developments were megahertz CMOS controls, nanosecond risetime drivers, ironcore RF load matching transformers and circuit measuring techniques for nanosecond transitions. [5] [6] More work needs to be done to "harden" the design for rugged field applications. The low surge current capability of the MOSFET (like the bipolar transistor, but unlike the SCR) makes it difficult to protect even with high speed gate suppression. We would recommend that compatible protective devices and/or techniques be developed to match the speed and surge capability of the MOSFET. We recommend also, that semiconductor manufacturers develop higher rated MOSFETs in more suitable packages for higher power designs. [7] Acknowledgments The authors wish to acknowledge the assistance of Dave Hoffman, Siliconix; Victor Li, Hewlett-Packard; and Brian Pelly, International Rectifier, in application of the power MOSFET to this project. We are indebted to Reuben Lee, retired from Westinghouse, for design of the RF matching transformer and for consultative help in design of other magnetics. 6-80 B. R. Pelly, "Applying International Rectifier's Power MOSFETs," IR Application Note AN930. D. Hoffman, "VMOS - Key to the Advancement of SMPS Technology," Power Conversion International - March/April, 1980, Volume 6, Number 2, PP 37-42. S. Davis, "Switching-Supply Frequency to Rise; Power FETs Challenge Bipolars," EDN, January 20, 1979, PP 44-50. R. Severns, "The Power MOSFET, A Breakthrough in Power Device Technology," Intersil Application Bulletin A033. W. Fragle, B.R. Pelly, B. Smith; "The HEXFET's Integral Reverse Rectifier - A Hidden Bonus for the Circuit Designer," Power Conversion International - March/April, 1980, Volume 6, Number 2, PP 17-36. S. Clemente, "Gate Drive Characteristics and Requirements for Power HEXFET's," IR Application Note AN-937. W.E. Frank, Reuben Lee; "New Induction Heating Transformers," IEEE Transactions on Magnetics presented at the 3rd Joint IntermagMagnetism and Magnetic Materials Conference; Montreal, Canada, July 20-23, 1982. 6.3 Using Power MOSFET Transistors to Interface from Ie Logic to High Power Loads (AN79-6) Topics considered are (1) the nature of the load, (2) general driving requirements of MOSFETs, and (3) the output characteristics of the logic element. on tum-off, whereas capacitive-like loads cause power surges on tum-on. The power waveform should be obtained, a suitable rectangular model derived, and peak junction temperature computed using techniques discussed elsewhere [1,2]. This calculation is especially important for incandescent lamp and motor loads as their current surges last from tens to thousands of milliseconds which causes a significant surge in the temperature of the MOSFET power driver. Load Considerations Inductive Loads Freedom from second breakdown limitations makes driving highly inductive or capacitive loads a natural application for MOSFETs. Inductive loads include transformers, solenoids or relays. High current inrush loads such as incandescent lamps, pulse forming networks, and motors also are generally handled easily. Some attention must be given to the load characteristics, however. Usually with inductive loads the peak voltage spike should be limited to a value below the breakdown rating of the transistor. Three techniques are commonly employed: free-wheeling diodes, peak clipping and snubbing. Typical circuits are shown in Figure 1. Power MOSFETS are an ideal element to interface power loads to integrated circuit logic. Although circuit design is simple, there are a few rules and precautions to observe in order to minimize power dissipation and to have reliable operation, which are not obvious at first glance. The spikes caused by most electromechanical inductive loads such as solenoids or relays are effectively handled by the free-wheeling diode in part (a). The ~ low impedance of the diode usually causes the current ~ to have a long decay time, however, which may be I intolerable in some applications. Speed may be traded for overshoot voltage, by using a resistance, R, in series with the diode [3]. In common with bipolar semiconductor devices, Power MOSFETS can be damaged if their voltage ratings are exceeded. Although their avalanche energy capability is much better than that of bipolar transIstors, it is not good design practice to have the MOSFET absorb inductive energy unless the part is rated for this type of service. The spikes generated from inductive loads may have tremendous energy content and usually some means of limiting their amplitude must be provided. The free-wheeling diode may be an inexpensive rectifier such as the IN4002. However, junction rectifiers do exhibit a turn-on transient which may allow excessive overshoot if the MOSFET is being driven off rapidly. For high speed switching, a Schottky or low voltage ion-implant rectifier is required; the ordinary fast recovery rectifier does not have a fast tum-on time. In addition the transient power generated during the tum-on and tum-off intervals must be determined in order to check for excessive channel temperatures. Highly inductive loads may generate significant power 6-81 v· r ., I I I LOAD: : I I I I I L __ J RIOPT) BVoss > Vz > v+ (a) Free-Wheeling Diode Clipper (b) Zener Diode Clipper (c) R-C Snubbing Methods of Limiting Inductive Spikes Figure 1 Often the safest and least expensive limiting technique is to use a zener diode as shown in part (b). The zener responds in picoseconds and can protect the MOSFET from supply transients as well as the inductive spike; consequently, zener limiting is particularly attractive on raw power buses. In a manner similar to using a resistor in series with a free-wheeling diode, faster decay of load current is achieved by clipping at a level above the supply voltage. Capacitive and High Inrush Loads Usually no auxiliary circuitry is required with capacitive-like loads. Although the MOSFET has no failure mode akin to secondary breakdown, it is necessary to observe the safe area curves of the MOSFET in order to avoid excessive temperature excursion during current inrush. When inrush power is excessive, usually increasing the gate drive will reduce it and may hold it within bounds. A lamp circuit and waveforms are shown in Figure 2. The R-C snubber is commonly used in power conversion circuits to limit spikes caused by transformer leakage inductance and wiring inductance. It also reduces power dissipation by shaping the load line to appear more resistive. Resistor R, in series with the capacitor, is required to limit the current surge on tum-on (a good idea even when MOSFETs are used) and to ensure that the circuit is adequately damped. Since the circuit is basically a resonant tank, it will exhibit a damped oscillation unless the circuit Q is 1/2 or less. Values are usually empirically determined. The peak voltage across the network will not exceed that calculated using the energy relationship: 1/2 U 2 = 1/2 CV2. Solving for the voltage, it is found that V= I Figure 2.1 illustrates the typical transient current, voltage and transistor dissipation of an incandescent lamp load being driven by a MOSFET circuit that is not drive limited - it can supply all the current that the load demands while maintaining operation in the ohmic region. Under these conditions, the output voltage quickly swings from its off state (VI) to on state in a time dictated by the transient gate drive current and the MOSFET's capacitances. The peak current is a function of the lamp's cold resistance and decays quasi-exponentially as the lamp filament heats and resistance increases. The transistor dissipation waveform is similar to the power waveform of Figure 2.1(c); this can be equated to the rectangular power pulse of 2.1(d) to simplify peak and average power calculations. VUc The resonant frequency can be calculated from the usual relationship and R selected so that Q ~ 1/2 by using The case where the power transistor is drive limited (where it cannot supply all of the peak current that the load demands) usually but not always - results in greater transistor dissipation. This is illustrated in the transient waveforms of Figure 2.2 where the peak current is much less than in the previous example, but also where transistor operation does not enter the ohmic region initially during the switching transition. The resulting power dissipation pulse is greater and may be destructive. R = 47TfL The equations and experience indicate that larger values of C lower the peak voltage and resonant frequency and consequently the resistor R also must be reduced. An optimum value exists for a given L-C combination which results in minimum overshoot. Another consideration is to minimize the power dissipation in the transistor; various techniques are discussed elsewhere [ 4,5] . MOSFETs make ideal drivers for incandescent lamps because they can handle high current surges without 6·82 +V, v oJ f 'PK PEAK CURRENT 'PK I.) 'a +V' ~, ~.o OUTPUT VOLTAGE v, v, PPK PPK PPK PPK Ib) PEAK DISSIPATION I,) EaUIVALENT RECTANGULAR POWER PULSE (d) 2.1) Current Determined by Load 2.2) Current Limited by Gate Drive Waveforms When Driving an Incandescent Lamp, High Inrush Loads Develop Similar Waveforms Figure 2 A bootstrap circuit is shown in Figure 3. Operation is as follows: when the driver bipolar is on, the gate potential is near ground and the MOSFET is off. Capacitor C is charged to VDD through the load and diode Dl. When the driver goes off, the gate voltage rises, turning on the MOSFET, which raises the source potential. If C is many times larger than the input capacitance of the MOSFET, it acts as a voltage source in series with the MOSFET source terminal potential, thereby providing a gate-source voltage close in value to VDD. The capacitor C will lose charge with time through the reverse resistance of diode D I, so that it becomes impractically large if the load must be held on more than a few seconds, unless a strobing technique is used as discussed in the following paragraph. However, many loads, such as hammer drivers in high speed printers, are actuated for under a millisecond so that capacitors in the range of 0.1 /-LF are adequate. In cases when the load is a solenoid, it may be permissable for the MOSFET to come out of the ohmic region as a result of a partial loss of gate drive after the solenoid has pulled in, because the hold-in current is very low. However, the power dissipation of the MOSFET may increase significantly un- _ less the drop in gate drive reduces drain current to a rather low value. failure caused by secondary breakdown. Lamp drivers may need to handle two types of surges, cold resistance inrush and flashover. Cold resistance inrush occurs on all lamps during turn-on; the peak is between 12 and 18 times the steady state current. Furthermore, the inrush current may be from 2 to 5 times rated current 5 milliseconds after power application. The inrush depends somewhat upon the lamp's design and the cold temperature of the bulb, which in turn is dependent upon the lamp's operating duty cycle and ambient temperature. Since the turn-on surge is a repetitive transient, for maximum MOSFET reliability, it is usually desirable to have sufficient gate drive to place the operating point in the ohmic region during the surge in order to minimize power dissipation. Driving Grounded Loads In many cases, the load is connected to ground and cannot be arranged as shown in Figures 1 and 2. Driving a grounded load forces the MOSFET to be used in a source follower circuit. The difficulty with a follower is that, to keep the MOSFET in the ohmic region with a large drain current flow, the gate must be about 10 volts above the source potential, which is only slightly lower than the supply. Therefore, the gate drive voltage must come from a voltage source which is about 10 volts above the supply voltage. If such a voltage is available, no significant problem exists other than ensuring that the driver circuit has a sufficient voltage rating. When no fixed voltage source is available, it may be generated using the bootstrap technique. VaD Driving Loads Connected to Ground by Using Bootstrapping Figure 3 6·83 When the load must remain actuated at full power for a long period of time, a pulsed signal may be applied to the drive circuit instead of a DC level. When load current is to flow, the driver is off, except for occasional brief on periods during which the MOSFET's source voltage drops to ground allowing C to recharge to VDD. The source for this strobe signal could be a system clock signal or the AC line. The higher the pulse repetition frequency, the smaller C may become, but C should usually be at least ten times the Ciss of the MOSFET to avoid transferring more than 10% of the charge on C to the gate during tum-on. current from the drain terminal to the gate terminal. Damage to the device from excessive current may result if the impedance of the current loop is very low, but this is usually not a problem unless the drainsource voltage is high enough to cause the bipolar to operate in a BVCEO(SUS) mode. Since the BVDSS rating of the FET is essentially the BVCBO rating of the bipolar, BVCEO(SUS) is approximately one half of BVDSS. Consequently, a second breakdown failure of the zener bipolar may occur when the drainsource terminal voltage exceeds one half of B VDSS. The carrier transit time through the channel is under Ins for most MOSFET structures, resulting in cut-off frequencies on the order of a gigahertz. Consequently, very fast switching is readily achieved, but parasitic oscillations can be troublesome if certain precautions are not observed. General Driving Considerations Regardless of the type of logic or network used to drive a MOSFET, consideration must be given to its properties such as: 1. The input protection zener diode 2. The high frequency response 3. The capacitive input impedance Usually oscillations are prevented by observing one or more of the following guidelines: I. Keep lead and trace lengths short. 2. Place ferrite beads on the gate lead close to the gate terminal or use a resistor of 10 to 1000 ohms in series with the gate. 3. Avoid a layout which may couple output signal to the input. 4. Surround the MOSFET with a ground plane and shield output from input. The input protection zener diode integral with some devices places restrictions on the drive levels. The positive voltage on the gate with respect to the source should not exceed the maximum voltage rating of the zener diode nor should the zener become forward biased by allowing the gate-to-source voltage to become negative. Since the MOSFET gate input resistance is essentially infinite, many can be driven from a CMOS or TTL output. However the input impedance of a MOSFET is capacitive and the drain current essentially follows the voltage on the gate. Although switching speed, per se, is not important when driving a lamp or electromechanicalload, the limited transient current available from the logic element may result in switching slow enough to cause significant transient power dissipation, particularly when a number of MOSFET stages are being driven in parallel. Accordingly, a transient analysis of some sort is usually required. The reasons for these restrictions are evident from the circuit of Figure 4 where it is seen that the zener is actually the base-emitter junction of a bipolar transistor whose collector is connected to the drain. Consequently, the zener exhibits a negative resistance characteristic similar to the BVCEO of a transistor. Above a few hundred microamperes, the voltage may switch from, for example, 20 volts to 8 volts. The lower voltage will limit the amount of current available from the MOSFET and excessive dissipation in the zener and drive circuitry may occur. o A fairly simple, yet quite accurate, analysis is to use a charge control approach as described by Evans and Hoffman [6]. For any particular time interval, A. _ (A. VGS)(Cin) tIG where A. VGS is the gate-source voltage change Cin is the effective input (gate-source) capacitance IG is the average gate current during switching A Parasitic npn Transistor in Zener Protected MOSFETs Figure 4 If the drive circuit can cause a negative gate-source voltage - a common situation with a source follower driving a capacitive load - the bipolar becomes turned on in the forward direction causing a flow of (all values must be determined for the time interval of interest). 6·84 Table 1 Pertinent Switching Relationships Interval Symbol Gate Voltage Change Tum-On Delay td(on) VG(TH)- VG(ofO Rise Time tr VG @ IDl(on) - VG(TH) Tum-Off Delay td(oft) VG(on) - VG @ ID2(on) Fall Time tf VG @ ID2(on) - VG(TH) Ciss Ciss 8VDS + - - Crss 8VGS Ciss Ciss 8VDS + - - Crss 8VGS consists of a p-channel MOSFET connected in series with an n-channel MOSFET (drain-to-drain) with the gates tied together and driven from a common Table I shows the appropriate quantities to use in the equation. For completeness, turn-on and turn-off delay relations are included, but these intervals are rarely of interest in power circuits. However, dissipation may be a problem during rise and fall time. J~. , { -V~~o Capacitance values used are the average values as V G varies over the ranges shown for the time interval of interest. Appropriate VDS values must also be used to detennine the capacitance. Key VGS points are: VG(off) Capacitance +Vl ~ +Vl ,-CHANNEL Off state gate voltage prior to turn-on = Threshold gate voltage V G(fH) VG@IDI(on) = VG corresponding to the peak value of drain current for capacitive or resistive loads or the value of drain current when the drain voltage enters the ohmic region for inductive loads On-state gate voltage prior to VG(on) turn-off VG@ID2(on) = VG corresponding to the value of drain current flowing prior to turn-off = CMOS Inverter Figure 5 signal - hence, the name CMOS (complementary MOS). When the input signal goes positive (+ V), the p-channel MOSFET is essentially off and conducts only IDSS (picoamperes). The n-channel unit is forward biased but since only IDSS is available from the p-channel, VDS is very low. Conversely, when the input goes low (zero), the p-channel device is turned full on, the n-channel device is off, and the output will be very near + V. Since the current (without a load) is extremely small, the inverter dissipates almost no power in either stable state; the only dissipated power of consequence occurs during the switching transitions as capacitances are charged. Due to the extremely high input impedance of a MOSFET, the CMOS gate has the capability of interfacing with many MOSFETs when only static conditions are considered. Driving from CMOS Logic The widely used CMOS logic elements are ideal for direct coupling to power MOSFETs because CMOS can operate with supplies up to 15 volts, a level which provides ample drive for the MOSFET. Since switching speed and transient load handling capability is related to the output impedance of the drive source, a brief examination of the CMOS circuit follows. The DC resistance between drain and source when the device is turned on is generally labeled "ON resistance" RON or RDS(ON). However, the CMOS gate has a limited output capability detennined by the gain of the n- and p-channel devices. Equivalent circuits of the CMOS output are shown in Figure 6. ' All CMOS circuits usually have an output configuration as shown by the inverter of Figure 5. The inverter 6-85 approximately as the square of increasing Vas. The p-channel transistor exhibits similar, but complemented, characteristics with less- gain and a more gradual transition from a current source to a resistor. +V2 V2 +V, ISlnk .. RL2 + Ronln) VO"V2-~ RL2 + Ronln) Is~ When driving a capacitive load the initial voltage change across the load will be a ramp due to the current source characteristic, followed by a rounding off due to the resistive characteristic dominating as VDS approaches zero. For fastest turn-on and therefore lower dissipation in the MOSFET, the peak output current should be achieved while the CMOS inverter is operating in the constant current mode. To accomplish this. the maximum current from ~he MOSFET is that which corresponds to a Vas that IS a few volts below the CMOS supply voltage, VI. From Figure 7, note that operating the CMOS dr~ver. at higher VCC will have a profound effect on ~wltchmg speed because the CMOS output current mcreases roughly as the square of Vas and the voltage where rounding occurs has been pushed to a higher level. ,d.,o"ll "~HANJ n·CHANNEL (b) Sinking Current (a) Sourcing Current CMOS Source/Sink Capabilities Figure 6 A look at the characteristic curves of CMOS transistors will provide insight into the dynamic driving source impedance presented to the MOSFET gate. Figure 7 shows the characteristic curves of n-channel and p-channel enhancement mode transistors typically found in CMOS circuits. Referring to the curve of Vas = 15V (gate-to-source voltage) for. the nchannel transistor, note that for a constant drIve voltage Vas. the transistor behaves like a current source for drain-to-source voltages greater than Vas - VT (VT is the threshold voltage of an MOS transistor - on the order of a volt or two). For a VDS below Vas - VT, the transistor behaves essentially like a resistor. Similar curves are obtained for lower values of Vas except that the magnitude of the current is significantly smaller and, in fact, IDS increases Therefore, the optimum interface from CMOS to a MOSFET is shown in Figure 8. In this configuration, the turn-on current is supplied from the p-channel FET which has the poorest characteristics of the CMOS pair, but when operating at 15 volts, serious rounding of the MOSFET's gate waveform can usually be made to occur at a level above that required to handle the load current. The turn-off current is supplied from the n-channel FET; it maintains good drive capability down to the threshold voltage of the MOSFET's gate which minimizes tailing of the drain current. 45 vG~"~e~·I'5IV 0 ".~~ VGS@VCC- 1OV 5 11 VGS" vee l• L OR 74COO 0 '0 '5 Vos - OUTPUT VOLTAGE (V) -15 - 10 Driving VMOS with a CMOS Gate Figure 8 VOS@VCCc 5V VGS" Ve~ = 1'0 ~ , Driving from TTL Logic The lower logic levels used in TTL make it much less satisfactory than CMOS for direct coupling to power MOSFETs; however, TTL can be directly coupled when lower output currents are required, or some additional circuitry can be added to make the match more universally applicable. The coupling problems are readily appreciated by analyzing the output circuit of TTL. VGS@VCC"15~ i..-'r 30 Transistor Output Characteristics of a CMOS Inverter Figure 7 6-86 pull-up resistor. To maintain a reasonably fast rise time, it is necessary to limit the peak drain current to the value obtained for a particular MOSFET type when the gate voltage is at 3.5 volts; the additional 1.5 volts are used as overdrive to place the operating point in the ohmic region. Figure 9 shows the totem-pole output circuit configurations commonly used in TTL. When the driver is off, the output is high, however, the output is slightly over two diode drops below the supply voltage for either configuration. Since the nominal supply is 5 volts, the output is approximately 3.5 volts, a level too low to fully utilize a power MOSFET. Full utilization of power MOSFETs is achieved with open collector TTL as shown in Figure 11. The open collector circuits do not have the top transistors and the lower transistors are designed to be used with supplies up to 15 volts. The MOSFET rise time is now mainly dependent upon the external resistor used. For fast rise time, the lower resistance values required may cause objectionable dissipation when the TTL output is low; use of the circuit of Figure 12 will provide high speed and low dissipation. It essentially restores the totem pole output to the TTL circuit using an external high voltage transistor. Since the bipolar transistor does not saturate, a general purpose transistor with a high fT will provide fast drive signal to the gate. v' v+ (a) Medium-Speed TTL Output Configuration (540017400 Families) J: 1 +V (b) High-Speed TTL Output Configuration <5V +'5V R, Basic TTL Output Configurations Figure 9 RL Va tOKn When the driver is on, the lower output transistor is also on; the output is low, on the order of a few tenths of a volt. The low level is satisfactory to ensure that the power MOSFET is cutoff, in most cases, but the high level needs to be raised. Open Collector TTL Is Used to Provide Greater Enhancement Voltage Figure 11 A method of boosting the TTL output level is shown in Figure 10. The external resistor allows the full-supply voltage to be applied to the MOSFET gate, but in doing so, the TTL output transistor becomes cut-off as the level increases above 3.5 volts. Consequently, the high drive capability and low output impedance of TTL is not effectively utilized, as the drive to the final value of gate voltage must come solely from the 'K!l Va +5V +v '5V I.L ,o.:}ova V,n 1 A "Totem Pole" Driver Increases Switching Speed and Reduces Dissipation Figure 12 Driving the VMOS with Standard TTL Figure 10 6-87 - [2] Bill Roehr, et al. "Silicon Rectifier Handbook," 2nd Edition, Chapter 2, pp. 30-39, Motorola, Inc., Phoenix, AZ. [3] loco cit. "Silicon Rectifier Handbook," Chapter 8, pp. 117-121. [4] E.T. Calkin and B.H. Hamilton, "Circuit Techniques for Improving the Switching Loci of Transistor Switches in Switching Regulators," IEEE Conference Record, 1972 lAS Annual Meeting, pp. 477-484. [5] Rollie J. Walker, "Circuit Techniques for Optimizing High Power Transistor Switching Efficiency," Proceedings of Powercon 5, May 1978, Power Concepts, Inc., Oxnard, CA. [6] Arthur Evans and Dave Hoffman, "Dynamic Input Characteristics of YMOS Power Switch," Siliconix Application Note, AN79-3. Summary MOSPOWER PETs can easily interface power loads to integrated circuit logic. Spikes from inductive loads usually must be limited to a level below the breakdown voltage of the MOSFET. High inrush, capacitive-like loads usually require high gate drive to place operation in the ohmic region during inrush. To avoid deleterious operation and ensure fast switching, consideration must be given to the input protection zener diode - if present - and capacitive input impedance. Direct coupling to CMOS is usually very satisfactory if the IC supply is 10 to 15 volts. With T2L, open collector elements are usually required to obtain sufficient gate voltage for the power MOSFET. References [1] Bill Roehr and Bryce Shiner, "Transient Thermal Resistance - General Data and Its Use"; Motorola Application Note, AN569 , Motorola Semiconductor Products Inc., Phoenix, AZ. 6·88 6.4 :MPP500: The First Single Package Complementary MOSPOWER Device Introduction The new MPP500 series of complementary power MOSFET pairs provide increased convenience for designers of small motor drives, inverters, and similar devices with load ratings of up to 150 W. Mechanical design is simplified because only half as many packages are needed to construct either a single-phase or a three-phase bridge. Electrical design is simplified because device matching by the designer is not required and because complicated isolated drives for the upper switches in the bridge are no longer necessary. This last simplification alone can result in a dramatic savings in system cost. In the MPP500, both FETs have equal die size and are mounted on a common header. Thus, the power handling capability of the two devices is, essentially, equal; for most applications, the difference in RDS(on) can be ignored. Three different drain-source voltage ratings are available: 100 V (MPP500), 80 V (MPP50l), and 60 V (MPP502); all three devices will handle 2.3 A continuous or 7.7 A pulsed. Input Drive Requirements The real advantage of the MPP500 lies in the ways it may be driven. Because the upper FET is a p-channel, it is only necessary to lower its gate terminal 10 V below the positive power rail to fully turn ON the device. This can be accomplished with any opencollector or open-drain logic output. It is not even necessary for the drive transistor to withstand the full power supply voltage. Because, if the power is stable, a suitable zener may be interposed between the current sink and the p-channel gate. Shut off can easily be accomplished with one pull-up resistor. Furthermore, the same current sink that turns on the p-channel FET ON can be used to simultaneously turn the complementary n-channel FET OFF. This is one of the benefits of using FETs with equal input capacitance. In fact, in Figure la the CMOS gate used to drive the MPP500 does not even have an open drain output. Further, because the PLUS 40 process with a 40 V gate breakdown is used in the MPP500, no zener is required for power input voltages less than 40 V. Some overlap conduction will occur under these circumstances during the switching transition as it does in CMOS logic, and for the same reason. A zener between the gates minimizes this. MPP500 Device Characteristics An MPP500 power MOSFET pair consists of one nchannel and one p-channel MOSFET which are matched for die size, breakdown voltage, and power handling capability. Die size matching means that the p-channel member of the pair has higher ON-resistance (RDS(on» than the n-channel member and that both FETs have equal input capacitance. The reason for the difference in RDS( on) is that holes (the majority carriers in p-channel devices) have less mobility in a semiconductor structure than do electrons (the majority carriers in n-channel devices). To construct devices with equal RDS( on), the p-channel device would require approximately 2.4 times the active area of the equivalent n-channel device and would, consequently, have 2.4 times as much input capacitance. This would mean that for equal gate drive impedance the p-channel device would switch more slowly than the n-channel device, and in certain applications, this would complicate system design considerably. Reprinted courtesy of PCI July, August 1984 6·89 -- Switching speed is a matter to which some attention must be paid. For resistive loads or situations where no zener is desired between the nand p channel gates, it makes sense to switch as rapidly as possible. Rapid switching minimizes overlap currents and maximizes efficiency. As with all other power MOSFETs, the limit to how fast you may switch depends on how much time and money can be put into the gate drive circuit . The MPP500 as a Power CMOS Driver The circuits shown in Figure 1 are useful for a variety of solenoid, lamp, and relay driver applications. Inverse diodes are inherent in all power MOSFETs, so additional diodes for inductive loads are not re9..uired unless very fast switching speeds are necessary II 1. Such fast switching speeds are seldom required for mechanical loads like motors and relays. • BOV o---~-., UK ,----, 1I4W I +lS V 0---., • : J+ 1 i) >-_.'_.7.......-+': LOGIC For reactive loads, the situation changes and a slower gate drive circuit may be a better choice. This situation exists because the reverse recovery time of the MOSFET inverse diode is typically between 200 and 400 ns. When switching speeds much faster than the diode reverse recovery time are desired, additional components will be needed. Otherwise, reverse conduction through the intrinsic diode or dV/dt effects during switching will damage the MOSFETs. At input voltages below 40 V, Schottky diodes in parallel with the MOSFET diodes are sufficient, since the forward drop of the Schottkys is less than the MOSFET diode drop. They, thus, will prevent the MOSFET diodes from conducting. At higher voltages, more complex arrays, using blocking diodes and conducting diodes or more complex drive schemes involving active commutation are required. For most inductive load circuits, a slower drive which trades switching losses for conduction losses in the extra diodes is simpler, less expensive, and dissipates less power. Generally, all that is required to switch at less than super-fast rates is a less expensive drive circuit. A CMOS logic gate is generally sufficient. A 4000 series CMOS gate, for example, will drive the MPP500 (both gates) with a current rise/voltage fall time of 300 to 700 ns. A series gate resistor can slow this further if desired. SIGNAL L ___ , '50 WATT POWER OUTPUT MPP 500 COMo----+-------I---= a: .05 /v 0- ,,,\ \ ~ / - "I'--- i""- ~WrTS ~V 1 WATT 50 100 L Pou,=2j WAT/ 200 500 1K 2K 5K 10K 20K FREOUENCY (Hz) Distortion vs Frequency for 25 Watt Amplifier Figure 7 The output devices are Siliconix type VN64GA, which typically have a transconductance of 3 mhos, an rds(on) of 0.3 Ohms, and an input capacitance of 700 pF. These characteristics are needed in order to have sufficient gain in the current bias loop, good power efficiency, and wide open loop bandwidth. The usually published frequency response at 1 watt power output is not shown as it conveys little information. Response is down 112 dB at 19 Hz and 100 kHz when driven from a 1 Kr! source with the input filter removed. Some listening tests have been run using a variety of associated equipment. Most listeners notice improved reproduction of high frequency transients and have difficulty in detecting overloads and clipping unless excessive. The power efficiency calculates at 53% at the 25 watt output level. The power dissipation is essentially independent of frequency and varies little with power output. It is about 17 watts at idle and increases to about 22 watts at output levels from 10 to 25 watts. A 50 Watt Design An amplifier designed to produce 50 W into 8 !l is shown on Figure 8. For this application low distortion is only required over a range from 50 Hz to 10 kHz. It was adapted to use an available power supply which produces + 78 V and - 52 V under no load and nominal line conditions. Most assemblies show no evidence of slew rate distortion until at least 30 kHz when a slight crossover glitch appears on the waveform at a level of 15 watts or more. The glitch is level sensitive due to imperfect bias tracking as a function of power output. Bias tracking also becomes worse as the frequency increases, probably because of stored charge problems in the rectifier diodes used for 02 and 03. This tracking error would normally not be encountered on speech or musical signals. Figure 9 shows total harmonic distortion at selected frequencies as a function of power output and Figure 10 shows distortion at 1, 10, and 50 walls as a function of frequency. In the important mid range, THO is under 0.1 %. Choice of suitable transistors for the diff-amp is limited. Good results have been obtained by using matched pairs of type 2N2484. The gain typically is about 400 at 2 mA and although the 60 volt VCEO rating seems marginal, no problems have been experienced. The narrower power bandwidth of the 50 watt amplifier as compared to the 25 watt amplifier is a direct result of the higher input capacitance of the higher power output devices. 6-102 To avoid serious high frequency distortion the diff-amp current was increased from 2 rnA to 4 rnA; the higher current necessitated a 2: I reduction in base circuit resistance in order to avoid an excessively tight match on the current gain of the diff-amp pair with the result that the bypassing action of C5, kept at I I'F, is less effective at low frequencies. The narrower power bandwidth of the 50 watt amplifier does not reflect a significant difference in the frequency response at I watt as compared to the 25 watt design. 1.0 lz as ~ 0.2 ~ 0.1 I f~50 o C f-'"' 0.05 ~ 0.02 o f-" 0.01 ::; ~ : 0.005 ~ ~ / ~ ~ I ....,.. r r-::d ~·HZ / 10 kHz V ...... 0 == ..... 1 kHz Hz ...-foOH;- a kHz g 0.002 I- 0.001 0.1 0.20.5 1 2 5 10 20 50 100 POWER OUTPUT (WATTS) Although not shown, data at 5 watts output is similar to that at 10 watts. The low frequency distortion is higher at these levels than at 50 watts because of the imperfect filtering action of Cs. Because of the clipper circuit, the voltage on Cs is a larger percentage of the input signal as the output drops from the 50 watt level. Distortion vs Power Output for 50 Watt Amplifier Figure 9 l 1.0 z o ~ The harmonic distortion spectrum is shown on Figure 11. The dynamic range of the instrument used is 90 dB. Note that the third harmonic is prominent at all power levels. The even harmonics quickly disappear, but at the 50 watt level, odd harmonics up to the 13th were detectable. Probably none of these harmonics is discernable by ear. ~ 0.21-~~~...-+--I--+-+--+-*--A is ~ o 0.1 ~ 0.05 ~-.J--I~-+......:~""",--t:~+--+-,:A--l "" ..J :: 0.02 e Power data is shown on Figure 12. The power efficiency calculates at 63 0J0 at the 50 watt output level. The power dissipation is essentially independent of frequency. The heat sink must handle about 40 watts of power. I--+--I'--+---'"",,;:;::--+-+--t;;;-f--j 0012~0-~5~0-1~0~0~2~00~~5~0~0-'1~K~~2K~-'~~~~ FREQUENCY (Hz) Distortion vs Frequency for 50 Watt Amplifier Figure 10 r------~------------------~---1_-o+80V 5100 7.5K 3.6K 1/2W VN1200A 7.5K .22 ..::::;~_+-l_O+-t--l,j~ ~O LJ......f L-._ _...... 150K 3.6K 1I2W 15K 27011 UNLESS NOTED. ALL RESISTORS: 1/4W.5% ALL CAPACITORS: 100V. VALUES IN ,.F +SDV Practical 50 Watt Autobias Figure 8 6-103 -=- 60 ... ;! zw 65 :IE 70 ...--.,.---.---,----r---,-"71r----,1.3 \ 'V-000HARMONICS 150 WATTS g \ ,.... \ 1\ \ 1\ I , \ z :> 75 9 ..... 80 w ..........., 1----+--±:=+-~~'-l-----1I---l1.1 \>'EVEN HARMONICS , , \ 85 ' 10', WATTS , ' \ \ , 1 WATT " , 1=2500 Hz 901~2~3~4~5~6~7~8~9~1~0~1~IJ-l~3~~15' HARMONIC Locus of Harmonic Spectrum Figure 11 Power Requirements FIgure 12 Finding suitable driver transistors for the diff-amp was not easy. The best transistor discovered to date is a D38WI4 manufactured by General Electric. The transistor has BVCEO > lOOV, which allows ample voltage margin, and hFE > 400 which places base current < 10 pA at 4 rnA of collector current. Consequently, base current matching to within I pA is not too difficult and this match will produce a maximum error of 20 mV in the diff-amp which translates into a 20 rnA error in the MOSFET idle current. -20 ...J ;! .J. R(1l) .1 Po=10W __ '- 47 1=2.5 kHz 2 213 0 -30 20 ffi -40 ...,. -60 r-- "~ -50 rOO ~ :IE 213 ::I 9 .. ~ -70 "0 -80 -90 The MOSPOWER output transistors are VN1200As. They have 120 V breakdown ratings, an "on" resistance under 0.2 ohms, transconductance of 5 Siemens, and an input capacitance of 1200 pF. This excellent combination of characteristics plays a major part in achieving the excellent results displayed by the simple autobias circuit. -~~ , 1\'" ~ ~ 47r THO(%) 4.1 2.1 1.5 _ 4.9 - 213il"'== ........ 00 i o ~ 8 10 12 HARMONIC 14 15 18 20 Open Loop Output Spectrum Even Harmonics FIgure 13 -20 ..... -30 ;! Finally, Figures 13 and 14 illustrate the tradeoffs in open loop harmonic content as the diode series resistance is varied in the dynamic bypassing scheme. With R =470, the bypassing effect is negligible, and no harmonics past the 11th are discernible. As R is reduced, high order harmonics are introduced which increase in level. However, harmonics below the 6th minimize at various values of R. In the final amplifier design, 2/30 was chosen as it minimized the large 3rd harmonic resulting in lowest overall total harmonic distortion. By better matching of the push-pull configuration, it should be possible to reduce the even harmonics below the levels shown. ffi -40 ::E ~ -50 z ::I LL -60 ~ m -70 .. ~ -80 2/30 ~ ,- ,:-... l\" ~ I PO =10J _ 1=2.5 kHz - R(1l) 47 2 213 0 " '" - THO(%) 4.1 2.1 1.5 4.9 ~ ""r--.,. R_ 47n ~ r--... ~ t- ;::::: on 2130 1 -90 9 11 13 HARMONIC 15 r-.. 17 20 19 21 Open Loop Output Spectrum Odd Harmonics FIgure 14 Conclusions The circuit scheme presented illustrates that using MOSPOWER transistors as power output devices produces an amplifier of extraordinary performance considering the circuit simplicity. It offers the following advantages over bipolar amplifier counterparts: 1. Only one driver stage 2. Simple overload protection 3. Stable bias point 4. Power efficiency independent of frequency. 6·104 6.6.2 A Simple Direct-Coupled Power MOSFET Audio Amplifier Topology Featuring Bias Stabilization © 1982 IEEE. Reprinted, with pennission, from INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, June 9-11, 1982, Arlington Heights, IL, pp. 136-137. Abstract Utilizing the high gain and high input impedance of short channel power MOSFETs, a simple circuit has been devised to provide sufficient drive for amplifiers up to 200 watts output. The circuit described features automatic control of the quiescent bias level and offers performance which meets criteria for high quality audio reproduction. Introduction Short-channel power MOSFETs offer several characteristics attractive for audio power amplifier applications namely: 1. Low distortion at all frequencies because of a linear transfer characteristic and a very high cut-off frequency. 2. A low drive power requirement because of a nearly infinite input resistance, relatively low capacitance, and high transconductance. 3. Failure immunity because second breakdown occurs well above the power rating. 4. Freedom from minority carrier storage delay time following signal overloads because FETs are strictly majority carrier devices. 5. High power efficiency because of low "on" resistance. rent with temperature at the desired idle level. Furthennore, as a result of production line variations a threshold voltage range on the order of 2 volts must be accommodated. Consequently, these FETs must be used within a closed loop bias system. The puzzler has been to provide a means of sensing the idle level despite the presence of the high current half-wave pulses which occur under Class-AB operation. A successful solution to the bias problem was the subject of an earlier paper by the author [ 1], however, the simple circuit in that paper used AC coupling of the audio signal. The circuit describeq in this paper applies this bias technique to a direct-coupled design. The resulting circuit is simple and offers outstanding perfonnance. The Autobias Principle The scheme previously reported extracts the idle current from the total current by means of a clipper circuit and filter which produces a voltage related to the idle level. A small resistor in series with the source _ _ of one of the power FETs is used to sample output ~ current. The voltage at idle is one-half of the clipping I level so that when the signal is large enough to cause current cut-off on negative half cycles (thereby producing an asymmetrical wavefonn) the peak clipper and filter produce an average voltage which is substantially the same as the zero signal level, regardless of the amplitude of the peak current, as illustrated by the wavefonns of Figure 1. The filtered voltage is used One of the major design problems has been providing a means of stabilizing the idle current level because short-channel FETs exhibit an increase of drain cur- 6·105 V+ J Rl1 T C6 ---- VOl 01 IIDLE 1 R13 CUPPING LEVEL R16 ~ ~----~----~--~~------ O' C7 Clipper Circuit Waveforms a) Clipper Input b) Clipper Output Figure 1 O. RB Op-Amp Bias Control for Class AB Figure 2 in a feedback loop to control the FET gate voltage and thereby maintain the bias current within close limits. Dl and D2 under large signal conditions. In addition, R16 should be over twenty times R20 to prevent a significant portion of the DC level on C7 from biasing D2. Capacitors C6 and C7 filter the clipped audio signal. A simple technique for achieving a stable automatic bias current is shown in Figure 2. The op-amp serves as a differential amplifier in a voltage comparator loop which serves to maintain the levels at its inputs equal. Thus the idle current is simply VDl/2RB, since R12 and R13 are equal. The loop gain is so high that variations of FET threshold voltage or other circuit constants have no measurable effect upon the idle current level. It is important to use a two stage clipper and also match the diodes Dl and D2 to avoid shifts in idle level under large signal conditions; a dual matched signal diode is an ideal choice. Circuit resistors should be chosen to force equal currents through Circuit Topology The general circuit topology is shown in Figure 3. It consists of an input differential amplifier using n-p-n transistors directly coupled to a p-n-p push-pull stage which drives the output power FETs in a totem pole arrangement. A similar topology has been previously used by Sampei, et al [2], and Harvey [3], however, the implementation is different and neither circuit has automatic bias. (+) RC 02. R20 RC FEEDBACK RB Amplifier Topology for Power MOSFETs Figure 3 6-\06 +v +v ~---+--- 51K os~t R2 51K '70 pF .... a~! R23 ~:~~ to Z, Rl0 UK as V' Rl. 51 K 2N3904 .. --t'"CR3 ~~~~ to Z2 R19 62011 Ra R20 06811 04 8211 jD2 R2. RB 211 R2S 12V,04W -4~V + Complete Amplifier Schematic Figure 5 07 The loads for the p-n-p drivers are provided by current sources (CR2 & CR3) and high-valued load resistors (RG) R2l, R22. This technique permits high gain to be achieved while allowing all the driver current to charge the input capacitance of the output devices. The drivers may work class AB when the input is a fast rising signal thereby providing a high peak current in phase with the drain current to provide a high slew rate. \ .OS '" "" ~ 05 L4 e ~ I a 03 .... 02 :;! 01 The drivers and the diff-amp stages are designed so that they cannot be driven into saturation. To do this requires that the stages load resistances and quiescent currents be chosen to limit the available voltage swing; to achieve reasonable gain from the diff-amp requires a driver supply voltage which at fIrst seems unnecessarily high (32 V) but is readily available from a standard 24 volt transformer. The current drain from this supply is fairly low, however, requiring only 8 rnA for each driver plus 2 rnA for the diff-amp. ............ P ....I=2W ',._ QS, as. VN120D f= 10 kHz .......... '-..... t- f", 1 kHz o ° .S MOSFET IDLE CURRENT (AJ Effect of Idle Level on Harmonic Distortion Figure 6 The - 9 V' line which rides on the - 40 V rail also supplies about 20 rnA and must be well fIltered to prevent AC ripple from being amplifIed by CR3 and injected into the gate of Q6. A zener diode is an effective fIlter and also provides a reference level for the current source transistors CRl and CR2. Neither the absolute value nor the regulation of the other supplies is critical. Any desired power output may be obtained from the circuit by simply altering the value of the main rails. Automatic switching between two supplies could also be used to improve power efficiency. No circuit changes are necessary other than altering the divider to the supply terminal, pin 7, of the op-amp to avoid exceeding its voltage rating (30 V) and using transistors with suffIcient voltage breakdown. In addition, the driver supply is non-critical with regard to hum or absolute value. It is possible to obtain this supply by bootstrapping from the amplifIer output, but a very large capacitor would be required to avoid a serious increase in low frequency distortion. The result is that bootstrapping works out to be less satisfactory and more expensive than the approach shown. The supply need not ride on the + 40 V rail. It is just as satisfactory to have a + 72 V supply with respect to ground; it could serve both channels of a stereo pair. 6-108 Power dissipation and efficiency as a function of power output are shown on Figures 8 and 9. Power efficiency is about 60% at full output and is essentially independent of'frequency. The diode D4 serves not only as part of the bias clipper network but also provides dynamic bypassing of the 2 ohm sense resistor. The diode reduces third harmonic distortion and increases power output at the expense of introducing a number of low-level high order harmonics into the output. This action is illustrated in detail in reference [1]. A similar network must be used in the source circuit Q5 to balance both halves of the push-pull output stage. 5. /' / V The zener diodes Z 1 and Z2 provide overload protection with a shorted output. They are chosen to limit the gate drive to a level such that ID< PD(rated)!V+. In addition, the zeners prevent large voltages from breaking down the FET gate-oxide layer. The zeners also conduct in the normal diode forward direction when the gate signal would normally swing the gate signal below the source. This action not only protects the gate but prevents the signal from saturating CR3 which would render the bias control loop inoperative. ./ ----- • 01 02 05 ~ t:- . 1 5. .. , V IV 20k,V ~kH' ~~ -- -V •• , 20 12 • 01 ....- P>- C V- f"""'.. . , :-- ------ ~ ,. 02 05 10 20 50 10 20 50 100 POWER OUTPUT (WATTS) Current from Main Supplies versus Audio Power Output Figure 9 Figure 10 shows a 100 kHz square wave output when the input filter Rl Cl is removed. With the filter in place, the slight 1 MHz ringing disappears. Rise time and frequency response can be varied by altering the value of C5. ,. /' 10 14 Curves of distortion as a function of frequency and power output are shown in Figure 7. In summary, total harmonic distortion is generally under 0.1 % throughout the audio range. The unusual rise in 20 Hz distortion at 16 watt is caused by the imperfect filtering of the output of the clipper circuit in the bias control loop. Because of the clipper circuit, the voltage on C5 becomes a larger percentage of the input signal as the output drops from the 50 watt level. L 50 Power Dissipation in Both Output Transistors versus Audio Power Output Figure 8 Performance V 20 POWER OUTPUT (WATTS) Since most power MOS devices have a cut-off frequency in the gigacycle range, parasitic RF oscillations can be troublesome. Most assemblies require bypasses on the order of 0.22 MF, connected from supply lines at the FET location. In addition, leads running to the gate terminal should be either shielded or used as a twisted pair with a ground lead. 1 10 20 kHz 10 kHz 20 Hz 30Hz 1 kHz 1\ .v 100 POWER OUTPUT (WATTS) Output Voltage with 100 kHz Square Wave Input. Input Filter Removed (5 V/Division) Figure 10 Distortion Characteristics Figure 7 6·109 The output coupling filter permits capacitive loads to be driven without introducing oscillation. With a 1 p,F load, distortion rises slightly at high frequencies. References [1] Bill Roehr, "The Autobias Amplifier, A New To- pology for Automatically Biased Audio Amplifiers Using Power MOSFETs," Journal of the Audio Engineering Society, Vol. 30, No.4, April 1982, pp. 208-216. Some listening tests have been conducted. Listeners are usually impressed and use terms like "smooth," "musical," and "excellent transient reproduction" to describe the sound. In addition, it is very difficult to detect when the output stages are driven into clipping. It appears that the circuit is suitable for the highest quality audio reproduction. [2] Tohru Sampei, Shin-ichi Ohashi, and Shikayaki Ochi, "100 Watt Super Audio Amplifier Using New MOS Devices," IEEE Transactions on Consumer Electronics, Vol. CE-23 , No.3, August 1977, pp. 409-416. Summary [3] Barry Harvey, "Power-FET Amplifier Designs Boost Fidelity, Reduce Complexity," EDN, Vol. 25, No. 17, Sept. 20, 1980, pp. 137-142. A simple circuit using short-channel power MOSFETs has been devised. It features high power efficiency and low distortion over the audio band, high slew rate, bias stability, fast overload recovery, and short-circuit protection. Listening tests have rated it very high in audio accuracy. Since it is potentially low cost and usable for power levels up to 200 watts, it should have wide application in the audio industry. [4] Edward M. Cherry and Gregory K. Cambrell, "Output Resistance and lntermodulation Distortion of Feedback Amplifiers," Journal of the Audio Engineering Society, Vol. 30, No.4, April 1982, pp. 178-191. 6·110 6.6.3 A MOSFET Power Amplifier with Error Correction Abstract higher turn-on voltage drive requirements and smaller transconductance at low current levels. The former tends to contradict generalizations which have been made to the effect that drive circuits for power MOSFETs are less expensive, at least for the reliable source-follower configuration. The latter results in transconductance droop in the crossover region if bias currents are not fairly high. Such transconductance droop can result in crossover distortion. Power MOSFETs are emerging as the device of choice for high-quality power amplifiers because of their speed, reduced needfor protection and falling cost. A low-distortion power amplifier design is illustrated which includes output stage error correction to reduce the effect of transconductance droop in the crossover region and thus allow operation at more efficient bias levels. Introduction In this paper we will illustrate a high-performance amplifier design which utilizes the advantages of the power MOSFET while dealing with the drawbacks of the device. Although not taken to an extreme, the underlying philosophy of the design is that smallsignal silicon is inexpensive, i.e., that the overwhelming portion of expense in a power amplifier is in items like the power transformer, filter capacitors, power transistors, heat sinks, chassis and related hardware. Thus, in order to take full advantage of the performance achievable with the MOSFET output ~ stage, a very high quality front-end and driver are - . . provided. The driver, operating from regulated boosted supplies, is capable of providing high voltage and current swings to the power MOSFETs with good headroom. Output stage transconductance droop is dealt with by employing a simple but very effective output stage error correction technique proposed by Hawksford. [1] The resulting design achieves a 20kHz THD figure of less than 0.0015 percent at an idle bias of only 150 mAo The rapid evolution of power MOSFETs during the last few years has brought them to the point where they are now very attractive for use in audio amplifier power output stages. Important improvements which have been made include increased voltage, current and dissipation ratings, reduced "on" resistance, availability of complementary pairs and greatly reduced cost. Although a 75-watt MOSFET is still more expensive that a ISO-watt bipolar transistor, the premium is small when considered relative to total amplifier cost and improved performance. The purpose of this paper is to demonstrate the level of performance achievable with current technology and illustrate practical circuit techniques for achieving this performance. Power MOSFETs have several fundamental advantages over bipolar power transistors, most notably speed and freedom from secondary breakdown. The latter provides higher "usable" power dissipation, improved reliability, and freedom from safe-area limiter circuits which can misbehave and cause audible degradation. MOSFETs also have some disadvantages in comparison with bipolar transistors. These include MOSFET vs. Bipolar Output Stages Design of MOSFET power amplifiers is quite straightforward and conventional as long as differ6·111 (a) 2' 16 (b) 80 ta pULLE TelT 10Wv )V_ == / 2. I--J p.s /1 PJSE JST rt I I VOS'" 25V 16 J 12 YGS-6'i_~ V r- V l v10 20 30 40 = /I (1/ I-- TJ J, -2' -16 I:i V II v 80 !S PULlE yeJT -12 E - (d) l- I I I i -30 -40 10 Ili lL 1/ lJ / j TJ= 12.t 1-""" ]'-...... TJI =25"C, TJ=I -...Ic .......I'-..... rA G b& 'L Iffl ~ V z -. E 1 -20 6 LPULl. TElT ~ -12 I -4 -Jv- t-Jv- t - -10 -2' -16 -Jv- t - - -. • I- .. VDI=:Z5~ Vo =Jv- t - -. ;j V V/, ~ [6 V VGS. GATE TO SOURCE VOLTAGE (VOLTS) J G ~ V 55' C 2 50 -r- r----- i z -i = +125"C TJ=2S"C r-(J=i r----- YOS. DRAIN TO SOURCE VOLTAGE (VOLTS) (c) lL 'L 1/ L -2 -50 VOS. DRAIN TO SOURCE VOLTAGE (VOLTS) t? -4 -6 -. -1. VGS. GATE TO SOURCE VOLTAGE (VOLTS) Drain and Gate Characteristics for Power MOSFET Types IRF-132 (a&b) and IRF-9130 (c&d) Figure 1 (Drawings courtesy of International Rectifier. Inc.) ences between MOSFETs and bipolar transistors are understood. Figure 1 shows the drain and gate transfer characteristics typical of the vertical DMOS devices used in this project (International Rectifier types IRF132 and IRF-9130). [2] The important point to see here is that these enhancement devices require about 3 volts of forward gate bias to begin to tum on (e.g., gate threshold voltage, Vt) and may require as much as 10 volts to conduct high currents (12 amperes). While the required bias voltage is thus higher than for bipolar transistors, it can still be generated by the traditional Vbe multiplier circuit. Thermal bias stability for the power MOSFETs is much better than that for bipolar transistors, even though the vertical DMOS devices have a Vgs temperature coefficient of about - 5.0 mVrC at a typical bias current of 150 rnA. This is partly due to the MOSFET's lower transconductance at the bias point. The MOSFETs negative temperature coefficient of transconductance also tends to improve thermal bias stability. As a result, in some cases, a Vbe multiplier transistor or associated reference diode need not be mounted on the heat sink. If the popular source-follower output stage configura- tion is used, the substantial gate drive voltage required for high currents means that the driver stage should be provided with a "boosted" power supply voltage greater than that of the main high-current supply in order to take full advantage of the voltage swing available from the latter. The current requirements for the boosted supply are small, and it can be regulated at little additional expense, thus reducing hum, crosstalk and modulation distortion. Several high-quality bipolar power amplifiers also use boosted driver supplies, some regulated. While bipolar transistors are regularly placed in parallel with small individual emitter ballast resistors, the paralleling issue is not as straightforward for power MOSFETs, at least in linear applications. It has been said that the negative temperature coefficients of transconductance and "on" resistance of MOSFETs act to suppress current hogging by one transistor, thus permitting easy paralleling of MOSFETs without ballast resistors. This appears to be true for hard- 6-112 switching applications where the paralleled devices are all fully turned-on together (Le., channels fully enhanced by forward gate voltage) so that current and dissipation imbalances are only a result of mismatched "on" resistance. Bipolar IRF.1J2 30 IRF·9130 25 20 However, the issue is more complex for linear, and especially low-distortion, applications because the operating region of interest is not the fully turned-on region, but rather the linear region wherein drain current at a specified gate voltage is important. Specifically, recognizing that the gate threshold voltage specification for these devices is 2-4 volts, an examination of the gate transfer characteristics of Figure I indicates that a very serious current imbalance can exist unless gate threshold voltages among paralleled devices are reasonably matched. It is also apparent that reasonable temperature differentials will not adequately reduce the imbalance. Because of the size of the worst-case threshold voltage differentials possible, source ballast resistors are not a reasonable approach to achieving balance. It thus appears that for high quality audio applications where paralleled devices are necessary, both threshold voltage and transconductance of paralleled devices should be matched. Threshold matching that guarantees that all devices are "on" to some extent in the quiescent bias state, and transconductance matching to within 20% is probably adequate. 15 10 05 14 10. AMPERES Power MOSFET Transconductance versus Drain Current. For comparison, note much greater ratio of transconductance to operating current typical of bipolar transistors Figure 2 This is done because both halves are "on" and contribute transconductance in the crossover region while ·only one half contributes transconductance at currents well outside the crossover region. This usually results in bias currents of less than 100 rnA per output transistor, sometimes as low as 20 mAo This small amount of bias current compared to several amperes of signal current being handled can sometimes result in unexpected temporary bias inadequacy, resulting in crossover distortion, because a small change in circuit parameters (about 50 mY) can cause the bias current to vary considerably. This can happen as a result of the time delay in the intentional thermal feedback loop created by placing the bias generator sensing junction on the heat sink; the temperature of this junction will differ from that of the power transistors as a result of thermal delay, low-pass filtering and attenuation. After a high dissipation interval ends, the amplifier may find itself temporarily underbiased because the power transistor junctions cooled down faster than the bias transistor. Modem complementary MOSFETs, with maximum "on" resistances of only about 0.3 ohms, are just about as efficient as bipolar transistors in terms of voltage dropped from supply rail to load in output stages. However, they typically require a higher operating current to achieve a given transconductance. This characteristic is illustrated in Figure 2. The device transconductance in a source-follower or emitter-follower output stage is important because it determines the small signal voltage drop through the stage as a function of current. This is especially important in Class-AB stages where it is desirable that the sum of the effective transconductances of both halves be high and be constant with current so as to avoid crossover distortion. It can be seen from Figure 2 that approaching this condition with power MOSFETs requires fairly substantial bias current (as a rough starting point, that current where transconductance is one-half its high-current asymptotic value), on the order of a few hundred milliamperes. Bipolar output stages can be operated in an overbiased mode, but the penalty can be dangerously reduced thermal stability if larger heat sinks are not used, or increased crossover distortion if larger ballast resistors are used. Much less thermal feedback is necessary for thermal stability of MOSFET output stages and their higher bias is less likely to disappear under transient thermal conditions. Compared to bipolar designs, Class-AB MOSFET power output stages also tend to have a wider Class-A region of operation and a smoother transition to the Class-B region of operation. In contrast, bipolar power transistors are typically biased at a much lower current, but this is not entirely advantageous. A typical bipolar output stage will often be biased approximately where the dynamic emitter resistance of the output devices (118m) at crossover is equal to the associated ballast resistance as a compromise in achieving approximately constant total output stage transconductance as a function of current. Although power MOSFETs require virtually no drive current at low frequencies, their substantial input capacitance means that drive circuits with forward and reverse drive capabilities similar to those employed 6-113 with bipolar transistors should be used for wideband, high slew-rate circuits for demanding audio applications. Although the gate-source capacitance can be on the order of 700 pF, this capacitance is effectively "bootstrapped" in a source follower output stage, typically reducing its effect by about an order of magnitude. The smaller gate-drain capacitance, about 100 pF, is also present. A 100 VI/J-s slope with an effective capacitance of 170 pF thus requires a 17 rnA current capability from each driver. BiPolar 10 MOSFET ~ ,~ K\ 05 Power MOSFETs tend to be inherently faster than bipolars, partly because there are no minority carrier effects. Their speed is primarily limited by the ability of the drive circuitry to charge the internal gate electrode capacitance through the effective gate resistance. The wider bandwidth, reduced excess phase and reduced variation of device speed with voltage and current tend to allow greater high-frequency negative feedback with greater stability. The higher switching speed also tends to reduce dynamic crossover distortion. Furthermore, the MOSFET's higher switching speed greatly reduces the flow of Class-AB common-mode current at high frequencies which poses such a destructive threat to many bipolar designs. 02 1 10 20 50 VeE or YOS. VOLTS 100 200 Safe Operating Area (SOA) Comparison of Bipolar Ring-Emitter Transistor (2SA-1072) and a Power MOSFET (IRF-9130). Rated power dissipations are 120 Wand 75 W, respectively Figure 3 much energy (product of power and time) is required to raise the temperature of the hottest point on the chip (which will not be much different than the average temperature of the whole chip) to a dangerous point. However, power MOSFETs do have a tendency to very high frequency parasitic oscillations in real-world circuits. This appears to be a result of the natural high speed of the device combined with the substantial drain-source capacitance (300 pF) typical of these devices, making formation of a Colpitts oscillator easy if inductance is present in the gate circuit. This often necessitates the use of a small resistor in series with the gate. In combination with the device input capacitance, this resistor (typically about 100 ohms) can create an additional pole which tends to reduce the high-frequency improvement over bipolar transistors. Figure 3 shows a comparison of safe operating area for a power MOSFET and a typical bipolar power transistor. Notice that there are no steep secondary breakdown SOA slopes at high voltages for the MOSFET - it is essentially limited by simple power dissipation over its full voltage range. This is also true for short-term dissipation well in excess of rated continuous dissipation, where ,thermal time constants govern the allowable excess dissipation. For example, a 25-ampere peak with 100 volts across the MOSFET can be handled for 10 microseconds. Figure 3 illustrates that "usable" dissipation (SOA at higher voltages) for a MOSFET may be equal to that of a bipolar power transistor of substantially higher rated power dissipation. Safe operating area at high voltages is particularly important when difficult reactive loads are being driven. In many power amplifiers the use of multiple paralleled output devices is for reasons of increased safe operating area rather than simple thermal considerations. Finally, freedom from secondary breakdown means freedom from complex safe-area limiter circuits, some of which are notorious for their misbehavior. [3] Perhaps one of the most important advantages of power MOSFETs for audio use is their freedom from secondary breakdown and large safe operating area (SOA). A highly simplified explanation of secondary breakdown in bipolar transistors is that it results from localized current hogging which in turn results from localized thermal "hot spots." Transistor current at a given base-emitter voltage has a very strong positive temperature coefficient. Thus, a "hot spot" carries more current and gets even hotter as a result. This regenerative process, once started, can be very rapid and unforgiving. It can persist even after the external voltage and current conditions re-enter the safe operating area, leading to destruction. The relationships in a power MOSFET are in contrast degenerative in nature because hotter regions exhibit reduced transconductance and thus tend to conduct less of the total current. This tends to equalize the temperature across the chip. The safe area of a MOSFET is thus primarily governed by simple thermal considerations of how Figure 4 illustrates a simple 50-watt MOSFET power amplifier design. It is notably similar to what a simple bipolar power amplifier design would look like. Transistors Q1 and Q2 comprise the input differential amplifier whose output is converted to a single-ended current by current mirror Q3, 4. This current feeds the common-emitter pre-driver Q5 which is provided with a constant-current load. Capacitor C1 provides Miller-effect feedback compensation and establishes a 6-114 B++ SOY R6 "0 R7 "0 R8 " 25mA a3 '-o..J r"'" ~ ~. L, ~. JT I~ V a7 ...... it- R'3 '00 3. B+ 35V a. r ":j~D' R12 '70 ;.~' Va, IN ....... R5 .3 K " R' lOOK R' '00 OUT a'......... R• •8K R3 '00 -= ":j~3 R' "0 R'O , K a.'" -= ~ R" 'DO R11 560 VQ8 ....... O'mA <),omA ,.~. t- I~ a,o L B- 35Y B-- 50 V A Simple MOSFET Power Ampillier. Note use 01 boosted supplies lor driver circuitry to satisly power MOSFET gate drive requirements Figure 4 stable gain-crossover frequency of approximately 2 MHz. Transistor Q6 is connected in a conventional Vbe multiplier circuit to provide adjustable bias (nominally about 8 V) for the output stage. If thermal feedback is required, a sensing diode placed directly in series with the emitter of Q6 (with appropriate modification of associated resistor values) and mounted on the heat sink will provide approximately the correct degree of compensation. Emitter-follower drivers Q7 and Q8 provide a low-impedance drive for the gates of power MOSFETs Q9 and QlO. The drivers isolate the high-impedance pre-driver collector circuit from the nonlinear input capacitance of the MOSFETs and provide adequate charge and discharge current for the MOSFET gate circuits. The boosted supplies for all circuits prior to the output stage enable the drive circuitry to provide adequate gate voltage to fully turn-on the MOSFETs while maintaining margin against saturation. Zener diodes DI-D4 protect the MOSFETs from excessive gate-source voltages of either polarity. provide higher performance and take full advantage of the capability of the MOSFET output stage. Although substantially adding to the complexity of the schematic in appearance, such improvements primarily involve only small-signal, low-voltage transistors and inexpensive passive components, and thus contribute only a small percentage increase to total amplifier cost. The front-end for the amplifier to be discussed here is shown in Figure 5. The input stage is a differential JFET-bipolar cascode with a constant current bias _ supply. The cascode allows the use of a low-noise dual JFET, achieving a referred input noise of less than 6 nV/-fHZ. It also provides good common-mode and power supply rejection, necessary because negative feedback is not very effective in reducing power supply and common-mode impairments introduced at the input stage. The degenerated JFET input stage can handle fairly large open-loop input signals with relatively low distortion, making the amplifier relatively immune to transient intermodulation distortion (TIM) and RFI effects. High-Performance Input and Driver Circuits As would be the case with a bipolar design as well, many improvements can be made to the "front-end" of the simplified amplifier of Figure 4 in order to The input stage is loaded by current sources (Q6, Q7) to provide high open-loop gain at low frequencies. 6-115 I +BO. .15 A17 A'. 470 410 A23 A'8 , K 'K 33 Q7'o.J 08....... ,...., ,...., D' D. • 19 'K I A•• A21 'K ~ "a'. ~ ...'" Q1';;:t-:~,~. i¥08 't~ '00 Va. 1- a' l 1 I c~b: "I IN .. A' • NPD5564 , A4 R3 C4 , R2 '00 0" a' ...... D4 --*- . ... .. •• o-t '\ ..... '00 C, ••F ~Q9 Vas ..... +1SV 'I C3 A" A" .~ ... :: " I .,. o.LJ rl AS '00 ,,,. '~F~ ,...22... A12 ...... FEEDBACK FROM OUTPUT ':" '00 tl,· . o,."-.J , K -=- 0.'o.J n ".., A7 UK STAGE -t+- A•• . ,7 TO OUTPUT 22K A'.r"" A11 -=-'7K A' 03' "K '00 '7 D7 ~ )015 -: ,...D'. 4.7 V A' •.3. ",~D' ,.K A25 RO • '00 470 A27 '00 -=- - so. -1BV MOSFET Power Amplifier Front End. Differential cascode circuitry minimizes distortion Figure 5 Transistors QI8 and QI9 provide regulated bias for the cascode bases and emitter-follower collectors. Adequate current is available so that these voltages remain stable even under clipping conditions. Diodes D4-D7 prevent the cascodes from saturating when the amplifier clips. Zener diode D8 provides for two identical drive signals offset by 22 volts to allow for biasing and error correction in the output stage. Emitter followers Q8 and Q9 isolate the input stage from second-stage (pre-driver) loading effects and produce a combined common-mode feedback to properly bias Q6 and Q7. This also provides additional common-mode rejection by reducing the commonmode impedance seen by the collectors of the input stage. Limiter diodes D2 and D3 prevent excessive signal swings at the collectors of Q4 and Q5 when the amplifier is clipPing. Overall negative feedback connections and frequency compensation are also shown in Figure 5. Rll and R12 set the closed-loop gain at approximately 20. The resistance of this divider was chosen to be fairly low to avoid noise and maintain good high-frequency characteristics. As a result, current flow and dissipation is not insignificant (100 mW in R12 at 50-watt operating level). To avoid thermally-induced distortion at low frequencies, these resistors should be over-sized metal-film types, I-watt and 2-watt respectively. The complementary pre-driver stage consists of a differential cascode (QIO-13) loaded with a Darlingtoncascode current mirror (Q14-I7) to provide a singleended drive for the output stage. The cascode achieves high speed by eliminating Miller effect and allowing the use of fast low voltage transistors in the commonemitter differential amplifier. Elimination of Miller effect is also important in reducing high-frequency distortion resulting from nonlinear collector-base junction capacitance. [4] The cascode configuration also improves low-frequency linearity and power supply rejection by reducing Early effect. The complementary pre-driver structure, made possible by the current mirror, greatly reduces second-order distortion. Feedback compensation is provided by C4 and R13 which implement rolloff feedback from the output of the pre-driver to the inverting amplifier input, estab6-116 lishing a stable gain crossover frequency of about 2 MHz. Providing compensation by feedback to the input stage tends to allow improved slew rate and reduced power supply coupling; the latter because both ends of the network are ground-referenced (in contrast to the Miller-effect compensation of Figure 4). Elements C3 and Rl4 act to stabilize the loop formed by C4 and R13. This front-end design enables the amplifier to achieve a slew rate in excess of 300 Vlp-s. 35 30 25 IRF·9530 20 IRF-132 Output Stage and Error Correction In virtually any well-designed power amplifier the output stage ultimately limits performance. It is here where both high voltages and large current swings are present, necessitating larger, more rugged devices which tend to be slower and less linear over their required operating range. The performance-limiting nature of the output stage is especially true in Class-B and -AB designs, where the signals being handled by each "half" have highly nonlinear "half-waverectified" waveforms and where crossover distortion is easily generated. In contrast, it is not difficult or prohibitively expensive to design front-end circuitry of exceptional linearity. Output Stage Transconductance versus Output Current 150mA). Reduced Total Transconductance In Central Region can Cause Crossover Distortion. Figure 6 <'bias = and less consistent, making it a significant parameter in source-follower stages. Figure 8 illustrates an error correction technique described by Hawksford which is well-suited to this application. [1] Here the output stage, being a source follower, is modeled as having exactly unity gain with an error voltage e(x) added. This error represents any departure from unity gain, whether it is a linear departure due to less than unity gain, a distortion due to transconductance nonlinearity, or injected errors like power supply ripple. A differential amplifier, represented by summer S2, merely subtracts the output from the input of the power stage to arrive at e(x). This error signal is then added to the input of the power stage by summer S 1 to provide that distorted input which is required for an undistorted output. Note that this is an error cancellation technique like feedforward as opposed to an error reduction technique like negative feedback. This technique is in a sense like the dual of feedforward. It is less expensive because the point of summation is a low-power internal amplifier node. It is less critical of component tolerances and frequency response matching because less circuitry is enclosed and that circuitry is simple. Feedforward tends to become less effective at very high frequencies because the required phase and amplitude matching for error cancellation becomes progressively more difficult to maintain. The technique of Figure 8 also tends to become less effective at very high frequencies because, being a feedback loop (albeit not a traditional negative feedback loop), it requires some amount of compensation for stability, detracting from the phase and amplitude matching. Overall negative feedback greatly improves amplifier performance (including dynamic distortions such as transient intermodulation distortion [4]), but it becomes progressively less effective as the frequency or speed of the errors being corrected increases. Highfrequency crossover notch distortion is a good example. For this reason, several high-performance amplifier designs now employ feedforward error correction in addition to conventional negative feedback. However, some of these designs can be complex and expensive. The philosophy of this design is based on the observation that only the output stage needs extra error correction and that such local error correction can be less complex and more effective. While the power MOSFET has many advantages, it was pointed out that the lower transconductance of the MOSFET will result in considerable crossover distortion unless rather high bias currents are chosen. Figure 6 illustrates this effect by showing the individual and summed transconductances of both halves of a Class-AB MOSFET output stage as a function of net output current. At a bias current of 150 rnA and a load of 8 ohms, this transconductance variation can result in open-loop output stage harmonic distortion on the order of one percent, as pictured in Figures 7a and 7b. Mismatches in the transconductance characteristics of the top and bottom output devices also contribute to the distortion of Figure 7. Again, while bipolar transistor transconductance is high enough and consistent enough that it is relatively unimportant in an emitterfollower stage, MOSFET transconductance is smaller A schematic of the MOSFET power amplifier's output stage and error correction circuit is shown in Figure 9. The error correction circuit is a slightly modified ver- 6-117 (a) (b) (\ f\ J } \ 1\ ~ :A -A r-..., \ y 1\v ""-...: ~ \ !'\/: 'T "- \v r "V --\ 'J ~ .......... \ (c) \ l- f\:-. '- ~ 7 ~ \ (d) ,...- ............. 1---'" "'-. -- / - '" ...... . . . .'--v - -........... L I-- ............ Output Stage Open-Loop distortion (THO); a) 1 kHz, No Error Correction; b) 20 kHz, No Error Correction; c) 1 kHz, with Error Correction; d) 20 kHz, with Error Correction. Vertical Distortion Scale 0.5 percent/div. All Measurements at Full Power (50 W). Figure 7 adequate to allow for the maximum bias plus VGS signal swing required by the MOSFETs. Transistors Q22 and Q23, in conjunction with R32 and R33, control the DC voltage drop across R34 and R3S. They thus set the bias for the MOSFETs by means of a Vbe-referenced feedback loop which also includes Q24, Q2S, Q26 and Q27. Resistors R38 and R39 control the loop gain of the bias loops and improve stability. Overall frequency compensation of the error correction and bias loops is provided by R36, R37, C6, C7 and CI0. 82 )( + f:(X) 81 Output Stage Error Correction 1 Figure 8 Figures 7c and 7d show open-loop distortion of the output stage with error correction to be less than 0.1 %, illustrating an improvement of better than an order of magnitude, even at 20 kHz. This was achieved with 5% tolerance resistors. While use of closer-tolerance resistors would improve the correction at lower frequencies, where it is unnecessary, their use would make a smaller improvement at 20 kHz because performance there is beginning to be limited by the speed of the error correction loop. Sensitivity of 20-kHz THD to tolerance in the error correction circuit has been measured to be approximately 0.0002% per percent in the closed-loop amplifier. For ultimate performance, a pot can be placed between the junctions of R38, R39 and R44, R4S. ilion of one illustrated in reference 1. Emitter followers Q20 and Q21 isolate the high-impedance predriver output nodes from the output stage and provide a low-impedance signal for the error correction summation process. Double emitter followers Q24, Q26 and Q2S, Q27 provide a high-current drive capability for the MOSFET gates and isolate the error correction summing nodes from the MOSFET gate loads. Note that Q24 and Q25 can be fast, inexpensive smallsignal transistors. Transistors Q22 and Q23 and resistors R38-R45 comprise the differential amplifier for summer S2 of Figure 8. The output current of these transistors is ~ummed with the input signal (summer S 1 of Figure 8) by means of R34 and R35. For error correction, the top and bottom halves (Q22 , Q23) work independently to produce identical correction signals. Input signals offset by ±1l volts, as supplied by the pre-driver circuit, provide DC operating voltage for these circuits. These offset voltages must be The output stage is completed by C8, C9 and RSO-S3 for control of parasitic oscillations and Dll-D14 for protection of the MOSFET gates from excessive drive voltages. As mentioned in Section 2, power MOSFETs are considerably more prone to high-frequency 6-118 +5DV 0'. R4. I. ... Jr-... R34 -K a26 ~ R3. I •• 47 ROO 47 R40 '70 022....... R44 330 I""" Q ili ~ It ill Il' BIAS ~: /. ~ ., R3B '7 Cl0~ R33 391 R3, 27 l~ R43 270 R46 1.8K ....... T; R45 33. R41 27. R51 47 C7 ii-R35 ••0 ~027 V i: 100 R47 180 R4' '7. 0231""'1 R37 180 r O'4 O" ~. IIf-~ +35 V 02B ':4 """011 15V ~ ~ '~'~ - - - - 0 OUT ... :"'013 15V ,. ~ 014 15V I~ 029 L -35 V M, 10 ...... 021 -SOY MOSFET Power Amplifier Output Stage. Q22 and Q23 Provide Error Correction Signals Figure 9 modulation) would be ineffective in detecting them. Some of these beliefs have been shown to be unfounded. 4-10 Nevertheless, it was decided to include some of these newer measures of distortion in the performance evaluation. parasitic oscillations than bipolar power transistors because of their inherent high-speed nature and because of their substantial drain-source capacitance, making it easy to form an efficient Colpitts oscillator structure with inductance in the gate circuit. The amount of series gate resistance required for suppression of parasitic oscillations grows in proportion to the amount of inductance in the gate circuit. For highspeed output stage operation it is therefore important to minimize this inductance. Although not employed in Figure 9, this can be done especially well by shielding the gate leads back to the driver transistors, grounding the shield to the local bypass ground at each end. Then only a lO-ohm series resistor at the driver end and a ferrite bead at the gate end are necessary. In spite of the error correction, which improves performance by more than an order of magnitude, transconductance variation in the output stage is still the dominant source of distortion in this amplifier. For this reason, output stage bias current continues to influence performance and tradeoffs can be made. The measurements presented here were made at a bias current of 150 rnA, resulting in a quiescent output stage power dissipation of 11 watts for the 50-watt amplifier. It should also be noted that the transconductance characteristics of the N- and P-channel output devices were not matched. Performance This amplifier employs substantial amounts of negative feedback (40 dB at 20 kHz), and 20-kHz total harmonic distortion (THD) was the primary performance metric used in the design process. In recent years several new forms of distortion have been described, sometimes in the belief that they were caused by large amounts of negative feedback and that traditional measures of distortion (e.g., harmonic and inter- A word about measurement technique is in order. In many cases the distortions being measured were below those levels measurable by conventional equipment and techniques. In order to add dynamic range to that provided by the equipment employed, a distortion magnifier circuit was utilized. This circuit scales the output level of the noninverting amplifier under test 6·119 - (a) THD;,s FREQUENCY 001 0003 ~ c:f 0001 i!: 00003 00001 (b) 20 50 100 200 SOD 1K 2K FREQUENCY, Hz SK 10K 20K SOK /' Total Harmonic Distortion (THO) as a Function of Frequency Figure 10 n IY\ down to that of the input, subtracts the two, reintroduces 11 percent of the scaled-down amplifier output signal, and finally multiplies the result by 9 for presentation to the measuring equipment. The net effect is to provide unity gain for the fundamental and a gain of ten to distortion products generated by the amplifier under test. Amplitude and phase balance adjustments were incorporated into the output signal path prior to the subtraction to achieve a fundamental null of greater than 60 dB to frequencies beyond 20 kHz. The excellent noise and distortion performance of the 5534-type operational amplifiers employed make this approach effective. 001 THD va \ ~ \ ['J / Y. '-- \ \.v/ l/-... '\ ft '-' IY\ \ \ 20 kHz Total Harmonic Distortion (THO) Products at Full Power (50 W) a) without Error Correction (THO Analyzer Reads .02%); b) with Error Correction (THO Analyzer Reads .0006%). Figure 12 The latter further improves the measurement floor in most cases. Most of the other distortion tests employed a similar arrangement. Due to an oscilloscope calibration error, all vertical deflections in the photographs are 6.4 percent low. Figures 10 and 11 show total harmonic distortion as a function of frequency and power. Dashed portions of the curves indicate that distortion is below the residual of the measuring system. Figure 12 shows the appearance of the 20-kHz full-power harmonic distortion products without and with output stage error correction. Figure 13 illustrates a virtually unmeasurable level of SMPTE* intermodulation distortion (60 & 6000 Hz, 4:1). LEVEL 0003 ~ c:f 0001 ________ 20 kHz i!' j I 1\ 00003 1 kHz Dynamic intermodulation distortion (DIM), a test for measurement of transient intermodulation distortion (TIM), is shown in Figure 14. [12] In this test a 3.18-kHz square wave and a 15-kHz sinewave are mixed 4:1 and passed through the amplifier. A spectrum analyzer is used to measure the in-band intermodulation components. Performance is shown for both 30-kHz and 100-kHz first-order low-pass filtering of the square wave source (DIM-30 and DIM100). As predicted by the good 20-kHz THD performance and high slew rate of this amplifier, both DIM-30 and DIM-100 distortion levels are very low; in fact, the former is unmeasurable. 00001 10 lEVEL, WATTS Total Harmonic 20 50 100 ~istortion (THO) as a Function of Level Figure 11 To measure harmonic distortion, for example, a sensitive THD analyzer [11] with a 20-kHz measurement floor of about 0.001 percent was employed in combination with this distortion magnifier to achieve a residual of about 0.0003 percent at 20 kHz, primarily limited by noise of the power amplifier under test. The distortion output of the analyzer was then observed with both an oscilloscope and a spectrum analyzer. Interface intermodulation distorion (lIM) [9] is measured by applying 1000 Hz to the amplifier under test • Society of Motion Picture and Television Engineers. 6·120 0.01 SMPTE 1M va LEVEL 10 0.... 03 0001 01 00003 003 PIM vs LEVEL if. i 0.0001 -------10 20 001 100 50 10 LEVEL, WATTS SMPTE Intermodulation Distortion as a Function of Level Figure 13 Phase Intermodulation Distortion (PIM) as a Function of Level. Note that Phase Modulation Is Expressed in rms nanoseconds. Figure 15 and 60 Hz to a test amplifier, each of which drives opposite ends of an 8-ohm load resistor. A spectrum analyzer is then used to measure distortion products at the output of the amplifier under test. Both amplifiers are operated at half the rated power of the amplifier under test and distortion products are referred to the I-kHz level at the output of the amplifier under test. For this test the spectrum analyzer was preceded by a modified version of the distortion magnifier to produce a magnification of 100. lIM was unmeasurable, at less than 0.0001 percent. 0.. 100 50 20 LEVEL, WATTS Damping factor (DF) as a function of frequency is shown in Figure 16, and is extremely high. It is high for three reasons: 1) the power MOSFETS present very light loading to the drivers, producing a low open-loop output impedance essentially equal to the inverse of their transconductance; 2) the error correction circuit tends to drive this open-loop output impedance to zero; 3) substantial overall negative feedback further reduces the output impedance by an amount approximating the feedback factor (40 dB at 20 kHz). Inclusion of a parallel R-L network (0.5 n, 0.5 JLH) at the output in series with the load for complete capacitive load stability will reduce the high-frequency damping factor to 125 at 20 kHz. DIM va. LEVEL DAMPING FACTOR V$ FREQUENCV 0.1 10.0001---------------_..... ;l- f ~ 3.000 0... ~ '",.000 /D'M-l00 ____1_ 0.01 I DIM-3D 300 0.003 100 10 LEVEL, WATTS "" &0 100 20 50 100 200 500 1K 2K 5K 10K 20K 50K 100K FREQUENCV, Hz Dynamic Intermodulatlon Distortion (DIM-30 and DIM-100) as a Function of Level Figure 14 Damping Factor as a Function of Frequency Figure 16 Phase intermodulation distortion (PIM) is shown in Figure 15. [10] PIM is measured in the same way as SMPTE-IM, except that phase modulation of the carrier is measured instead of amplitude modulation. The phase modulation is then expressed in time (e.g., rms nanoseconds) . Although the need for this much damping factor is doubtful, the importance of DF on frequency response and coloration has sometimes been underestimated. This is explained by the fact that most speaker systems are designed assuming they will be driven by a pure voltage source (sometimes, it seems, with limitless 6·121 (a) (a) (b) (b) I I t-hr V .....J r--- - I f ~ j\, - II V 20 kHz Square Wave into a 1-0hm Resistor In Series with a 1-Microfarad Capacitor; a) Smail-Signal (1 V/dlv); b) Full-Power (Input Bandlimited to 200 kHz). Top Trace 20 V/div. Bottom Trace Is Output Current at 20 A/div. Timebase is 10 /Ls/div. Figure 18 20 kHz Square Wave into an 8 Ohm Load; a) Small-Signal (1 V/div); b) Full Power (20 V/div) Figure 17 current capability as well!). For example, the impedance of a nominal4-ohm system may dip to 2.5 ohms and rise to over 50 ohms at various points across the frequency band due to driver and crossover resonances. A typical bipolar amplifier may have a damping factor of 100 (perhaps less at high frequencies), resulting in frequency response deviations on the order of 0.3 dB with such a load. Coloration due to low DF may also partly explain audible differences among vacuum-tube and low-feedback designs. Table I summarizes overall performance of the amplifier. Table 1 Summary of MOSFET Power Amplifier Performance POWER OUTPUT (RI = SO) Figure 17 illustrates small-signal and full-power 20kHz square waves into an 8-ohm load. Figure 18 shows small-signal and full-power 20-kHz square waves into a reactive load consisting of I-ohm and 1 p..F in series. In the full-power case the square wave has been band-limited to 200 kHz by a first-order low-pass filter. Figure 19 shows 500 kHz small-signal square waves into an 8-ohm resistive load and a reactive load consisting of I-ohm and I-p..F in series. It also shows a full-power 500 kHz square wave into an 8-ohm load. Few bipolar amplifiers would survive this test. TOTAL HARMONIC DISTORTION (20-20 kHz) <0.001% SMPTE IM DISTORTION 0.00013% DYNAMIC lNTERMODULATION DISTORTION (DIM·30) (DIM· 100) <0.006%' 0.014% INTERFACE lNTERMODULATION DISTORTION (IIM) 0.0001% PHASE INTERMODULATION DISTORTION (PIM) <0.1 os SLEW RATE >300 VI/Ls RISE TIME 100 os DAMPING FACTOR (20-20 kHz) >sooo SIN ("A" WTD, 108 dB re I WAIT) * Below Measurement Floor 6-122 sow (b) (a) r r---, I"t-- ".- r r-- --, I r- r---., r- h \ -r-- ......... f---J ' - r-- I ' - t--' (e) ,... r- 1----\ r,--- I---, 1\ \\.. V-- \.... ---.J 500 kHz Square Wave Response; a) Smail-Signal, B-Ohm Load (1 V/div); b) Small-SignaI1-0hm and 1-p.F Series Load (1 V/div); e) Full-Power, B-Ohm Load (20 V/dlv.). Tlmebase is 0.5 p.s/div. Figure 19 effectively by means of a simple error correction circuit. Although a MOSFET power amplifier can still be expected to cost a little more, the improved characteristics seem to justify the small premium in applications where performance is important. Conclusion Power MOSFETs are capable of exceptional performance when used in combination with good drive circuitry and simple error correction circuitry. Their ability to operate without complex and unreliable safe-area limiting circuitry makes them especially useful for demanding audio applications. Compared with bipolar transistors, the major disadvantage of MOSFETs (and source of distortion) seems to be the lower transconductance, but this can be dealt with Editors Note: This paper is intended to illustrate design techniques and performance achievable, and not as a construction project. 6·123 References [1] M. J. Hawksford, "Distortion Correction in Audio Power Amplifiers," 65th Convention of the Audio Eng. Soc., preprint # 1574, February 1980. [2] International Rectifier HEXFET Databook, International Rectifier Corporation, Copyright 1981. [3] T. Holman, "New Factors in Power Amplifier Design," J. Audio Eng. Soc., Vol. 29, No. 7/8, pp. 517-522, July/August 1981. [4] R. R. Cordell, "Another View of TIM," Audio, Vol. 64, Nos. 2 & 3, February and March 1980. [5] W. G. Jung, M. L. Stephens, C. C. Todd, "An Overview of SID and TIM," Audio, Vol. 63, Nos. 6-8, June-August 1979. [6] P. Garde, "Transient Distortion in Feedback Amplifiers," J. Audio Eng. Soc., Vol. 26, No. 5, pp. 314-321, May 1978. [7] E. M. Cherry, "Transient Intermodulation Distortion; Part I-Hard Nonlinearity," IEEE Trans. Aconst., Speech, Sig. Proc., Vol. ASSP-29, pp. 137-146, April 1981. [8] R. R. Cordell, "A Fully In-band Multitone Test for Transient Intermodulation Distortion," J. Audio Eng. Soc., Vol. 29, No.9, pp. 578-586. [9] R. R. Cordell, "Open-Loop Output Impedance and Interface Intermodulation Distortion in Audio Power Amplifiers," 64th Convention of the Audio Eng. Soc., preprint # 1537, November 1979. [10] R. R. Cordell, "Phase Intermodulation Distortion-Instrumentation and Measurements," J. Audio Eng. Soc., Vol. 31, No.3, pp. 114-124, March 1983. [11] R. R. Cordell, "Build a High-Performance THD Analyzer," Audio, Vol. 65, Nos. 7-9, Ju1ySeptember 1981. [12] E. Leinonen, M. Otala, J. Curl, "A Methodfor Measuring Transient Intermodulation Distortion (TIM)," J. Audio Eng. Soc., Vol. 25, No.4, pp. 170-177, April 1977. 6·124 6.6.4 Boost OP-AMP Output Power With Complementary Power MOSFETs (AN83 .. 5) Introduction A Current-Boosted DC Power Amplifier Many high-quality, monolithic op-amps are available today at low cost. They offer low noise and distortion, high slewrate and wide bandwidth. However, due to the limited chip-size, their small output transistors cannot deliver any appreciable power to a load. Circuit Topology The schematic for this simple circuit is shown in Figure 1. It is configured as a non-inverting DC amplifier with a closed-loop gain of 11. Drive for the power MOSFET output stage is taken from the op-amp's power supply pins, rather than its output pin. This may seem somewhat unconventional, but there are very good reasons for doing this. The output pin could be used to drive a pair of MOSFETs configured as a complementary source-follower. However, the source-follower output-stage has two major disadvantages: a voltage gain of less than unity, and a substantial DC threshold offset-voltage. This results in peak gate-drive voltages, from the op-amp, several volts greater in magnitude than the output at the MOSFET sources. Also, the output of most op-amps can only swing to within about 2 volts of the supply rails. Thus, the peak voltage swing at the output of the source-follower is restricted to significantly less than the power-supply rail voltages. Higher power monolithic and hybrid op-amps are available, but their cost is inevitably much higher than their lowpower counterparts. Also, their performance tends to be inferior in the categories of noise, distortion and slewrate. Clearly, a circuit topology that combines a low-power, high quality op-amp, a pair of inexpensive complementary power MOSFETs and a few additional components, is desirable. This combination should be expected to have very good performance, since power MOSFETs are inherently linear devices. This Applications Note presents a power-boosted op-amp circuit using Siliconix Nand P channel power MOSFETs. It is configured as a current-boosted DC amplifier operating from standard op-amp power supply voltages. The design takes advantage of a new thermally-stable biasing technique for the MOSFETs. Emphasis is placed on the ease of interfacing complementary power MOSFETs to an op-amp, and the high performance obtainable. The amplifier shown in Figure 1 does not have these limitations. Both the op-amp's output stage and the MOSFET current-booster stage provide voltage gain. The op-amp's output stage is used as an inverting commonemitter phase-splitter, while the MOSFETs are used as an inverting common-source output-stage. Since the collectors 6-125 +20V 1.3K +20V 20K R10 R11 .-----.-----T---~~~ 100 01 2N3904 J +20V / / 03 IRF 9520 /' 02/ 2N3904 R6 R7 IC 1 Vln -------_---------''4 R1 300 OUT R9 "':-MOSFET BIAS ADJUST RS 6 TL071 100K --- ~ IBIAS = 50 rnA 1K 1K 240 RL=sn,50W 1 100K R2 10K 04 IRF 520 100 ':' R5 NOTE: ALL RESISTORS 1/4W, 5% (EXCEPT RLI. VALUES IN n UK -20V -20V A Current Boosted DC Power Amplifier Using an Op-Amp, a Pair of Complementary Power MOSFETs and a Few Additional Components Figure 1 V+ V+ 03 P-CHANNEL DEVICE V'out 6 TL071 OP-AMP ~ Voul RS / R9 RL ':' ':' 1 04 N-CHANNEL DEVICE R5 V- V- A Simplified View of the Current Boosted Amplifier, Showing the Secondary Feedback Loop. This Is Formed by the Op-Amp's Output Stage, the MOSFETs, and the Feedback Network RS and Rg. Figure 2 6-126 of the output transistors in almost all monolithic op-amps are connected to their power supply pins, they can be used to drive the MOSFETs. where: Load resistors R4 and R5 are connected from the op-amp's supply pins to the power supply rails. They generate the necessary bias and drive voltages that the MOSFETs require. Since these voltages are referenced to the power supply rails rather than the output voltage, a significantly larger peak output swing is possible. This circuit easily generates peak gate-to-source enhancement voltages for each MOSFET in excess of 10 volts. Thus, the output voltage swing is limited only by the peak output currer,t multiplied by the RDS(on) of the MOSFETs. and RSRg « RS +Rg then, Thus: It should be noted that small resistors (1000) are included in series with the gates of each MOSFET. These are to suppress any potential parasitic oscillation that might occur in the circuit. The resistors should be placed as close to the MOSFET packages as possible, for maximum suppression. Care should be taken in the layout of the circuit to avoid excessively long lead lengths as well as any ground-loops. and so, and reA ) reA + REI + RE3 ( reA ) reA + REI + RE3 40 26 64 I2S 2.5 1.3 1.0 240 rnA/V 0 0 0 A/V KO KO 0 8 0 {J Vout Vin Vout Vin gm3 R4RL ~ (3) RS+Rg 124.0 1 + {J(124.0) l/{J RS + Rg Rg (4) This analysis has been done for the upper half of the output stage only. Since the upper and lower halves are reasonably well-matched, this analysis will suffice for both. Looking at Figure 2, it can be seen that a secondary feedback loop is formed by the op-amp's output stage, the power MOSFETs and the feedback network RS and Rg. The effect of this feedback loop is to stabilize the voltage gain seen, going from Vin to Vout. It can be shown through linear circuit analysis, that at low frequencies: ( l/grnA If, as in this case; Quiescent bias current for the op-amp also flows through resistors R4 and R5. Since this current is regulated internally by the op-amp, it does not affect circuit performance. In fact, it proves beneficial because some DC bias voltage for the MOSFETs is generated across R4 and R5. More will be said about DC biasing for the MOSFETs later. Vout Vin grnA(QA) reA REI RE2 gm3(Q3) R4 RS Rg RL (1) Vi out Rg RSRg ( 1 ) {J = - - = - - + - (2) V out RS + Rg RS + Rg gm3R4RL 6-127 Equation (4) shows that the low-frequency voltage-gain of the combined output-stage is set independently of the opamp. This additional gain reduces the voltage swing at the output of the op-amp, and improves the bandwidth, slewrate and distortion of the amplifier. Theoretically this improvement should be equal to 1/ {J or about a factor of 5 in this case. However, this value is only observed in the reduction of distortion over the source-follower outputstage. The rather large input capacitance of the MOSFETs (several hundred pF), degrades the frequency response somewhat and slows the amplifier down. The actual improvement in slew-rate was observed to be closer to a factor of 3, which is still more than acceptable. The full power bandwidth of this amplifier was well over 100KHz. A detailed frequency response analysis of this amplifier has not been presented here, because it is somewhat lengthy. Suffice to say, however, that the additional gain provided by the combined output-stage increases the overall gain-bandwidth-product of the circuit. As well, the MOSFET stage adds an extra pole to the open-loop transfer function. Thus the amplifier is unstable for closed loop gains less than about 1/ {J, or 5 in this case. If unity or very - low values of gain are desired, an externally compensated op-amp such as the TL080 should be used in place of the TL071. An external compensation capacitor can then be chosen so that the circuit will not oscillate at the particular closed-loop gain used. Ql and Q2 form a variable, temperature-compensated current-sink, connected to the positive supply pin of the op-amp. AP. trimpot RS is reduced from its maximum value, the additional current drawn by Ql, through R4, increases. At some point, the voltage across R4 will reach the threshold voltage of the P-channel MOSFET and it will begin to conduct current. Biasing the MOSFET Pair - A New Approach This current will tend to force the output of the amplifier positive, if the N-channel device is conducting a lesser current. But the output of the amplifier is DC coupled back to the inverting terminal of the op-amp. Thus, the op-amp adjusts the voltage across R5 to force the N-channel device to conduct the same current as the P-channel device. AP. trimpot RS is varied, the voltage at the op-amp's output pin can be seen to go more negative as the bias is increased. This makes sense because more current is then flowing out of the op-amp's negative supply pin, which increases the gate-to-source voltage of the N-channel MOSFET. AP. mentioned previously, the op-amp's DC operating current generates some bias voltage for the MOSFETs, across R4 and R5. This voltage is intentionally made less than either MOSFETs threshold voltage. Consequently the biasing circuitry comprised of Ql and Q2. has full control over the MOSFET idle current. The MOSFET threshold voltages are typically 3 volts for the N-channel device and 4 volts for the P-channel. Texas Instruments' TL071 BIFET op-amp was chosen for its low supply current of 2.5roA (max) as well as its high speed and low noise. The low supply current ensures that the voltage across R4 and R5 can be reduced to less than 3 volts. With the bias adjust trimpot (RS) set for minimum bias, the MOSFETs should not conduct any current. In some cases though, the values of R4 and R5 may have to be changed to ensure that the MOSFETs do turn off with RS set for minimum bias. It can be seen that the op-amp is used not only as the main gain element in this amplifier, but also as the bias controller for the N-channel MOSFET. Any variations in the idle current ofthe P-channel MOSFET are mirrored, under control of the op-amp, by the N-channel device. This keeps the output centered at zero. Table 1 Current Boosted DC Amplifier Performance Conditions: TA = 25°C. SUPPLIES MOSFET BIAS CURRENT sn ±20V. RL = 50mA. CLOSED-LOOP GAIN (AvcLl Output Voltage Swing: +1S.5V. -19.0V Output Sink/Source Capability: 2.5A DC Rise Time: 1J.LS Slew Rate: 35 V/J.LS Overshoot: +ve: 15%. -ve: 20% Output Offset: (Equal to AVCL x VIO (op-amp)) 75mV Noise Floor (at 10Hz bandwith): -90dB at 100mW into THO: 0.0075% at 100Hz and 20W 0.0162% at 1 KHz and 20W 0.1350% at 10KHz and 20W Bias Stability: After 20W output for Y, hour the bias decreased to 43mA. 6·128 sn = 11 Some provision must be made to compensate for the variation in MOSFET idle-current with temperature, at fixed gate-to-source voltages. The temperature coeffIcient of drain-current at low bias levels is positive, which is due to the decrease in threshold voltage with increasing temperature. This variation in threshold voltage is approximately -5mV/aC. If the voltage across 14 is changed by this amount as the output devices heat up, then the idle current will be thermally stable. the threshold voltage with temperature. Consequently the MOSFET idle current will decrease slightly as the temperature increases. This is desirable because the output stage power dissipation at idle will then decrease as the MOSFETs heat up. In this amplifier, the idle current decreased by approximately 15% for a 60a C temperature rise at the heatsink surface. This is easily achieved by thermally bonding (i.e. glueing) Q2 of the bias circuitry to the heatsink on which the MOSFETs are mounted. As Q2 heats up its base-emitter voltage decreases by about 2.2mVI" C. The effective change in voltage across R4 with temperature is thus: Table I lists the amplifier performance measured on a breadboard version. Of particular note is the large output voltage-swing possible, with a low impedance load. This makes it suitable for use in applications such as Winchester head-actuator drive amplifIers. Here, the larger the output voltage swing, the faster the head accelerates across the surface of the disc. dV (14) dT R4 --- x R6 + R7 Amplifier Performance (-2.2mVI"C) The excellent noise, distortion and slew-rate specifications make this amplifier suitable for audio use as well. Supplied by ±20V generated from a 12V battery, through a DC-to-DC converter, two of these amplifiers would be more than adequate as a car-stero booster-amplifier. In this amplifier, the sum ofR6 + R7 was set to about 4200 for a MOSFET bias current of 50mA. From equation 5, this gives an effective decrease in voltage across R4 of - 6.9mV/ a C. This decrease is somewhat larger than that of Small robots too, could benefit from servo power-amplifiers based on the design presented here. 6-129 6.7 Bipolar- FET Combinational Devices Introduction Because of the fundamental difference in operating mechanisms, FETs and BITs have different operating characteristics. From the user's point of view, FETs have the advantages of drive simplicity, fast switching speed, and second breakdown ruggedness, but have the disadvantage of higher conduction resistance. To reduce FET conduction resistance and minimize the power loss, a larger chip area is required. For a typical 400 V device with the same conduction drop, FETs require between 2.5 and 3 times the chip area of an equivalent BIT. Darlington Configuration [4, 6J In this configuration, a FE T and a BIT are connected in Darlington fashion with the FET as driver transistor and the BIT as output transistor. When the gate voltage of the FET is high, drain current, ID, is conducted into the base ofQl providing base current 'G As chip size increases, yield decreases exponentially. This drives the cost per useful chip up dramatically. This is the fundamental reason why FETs are not cost competitive in high voltage applications. By combining FETs and BITs in a single device, one may produce a device with the advantages of both. WITHOUT [)JODE 0 WITH DIODE D In this paper, four combinational configurations will be described, and the application characteristics of each will be discussed. Combinational Devices and Characteristics In general, FETs are used in combinational devices to simplify drive and to increase switching speed, while BITs are used for current carrying capability. Four configurations are considered in this paper. Shown in Figure 1 a is a FET-Darlington configuration. Figure 1 b is a cascode configuration, Figure 1c shows a parallel configuration, and Figure 1 d is a FET-Gated Configuration (FGT). The application characteristics of each of the four configurations are given below. '"th-. FET - Darlington (or Cascade) Configuration and Waveforms Figure 1a 6-\30 c/o 10 o~ c/o I. '. 10 iG '0 ElS ~, 18 10 '0 ~, ~, '0 '8 '8 IC L, 1 ( Emitter-Open (or Cascode) Configuration and Waveforms Figure 1b Parallel Configuration and Waveforms Figure 1c for the BJT which then conducts the load current. When the gate voltage is lowered, the FET turns off immediately, but the BJT does not tum off until the stored charge in its base is exhausted. To speed up tum-off of the BJT, a diode, D, may be added to provide a path for withdrawal of excess carriers in the base ofQl. Without the diode, excess carriers in the base of Ql decay by recombination only, and the BJT turns off slowly. With the diode, Ql can be turned off rapidly, but the gate drive must provide a large reverse current spike. At the instant ofturn-on, when Q2 is conducting and Q 1 is turning on, most of the load current passes through Q2 into the base of Ql. This provides an inherent base current "kick" to Ql as shown in the waveforms in Figure lao The tum-on speed of this combination device is usually somewhat faster than the speed of Ql alone. FET-Gated Transistor (FGT) Configuration and Waveforms Figure 1d such as BVCBO or BVCEX Only the BJT, however, must be rated to carry the maximum load current. The drain current rating ofthe FET need only be equal to the maximum base current for the BJT, which will be the maximum load current of the BJT divided by its forward gain (tl) at that current. Both parts of this combination may be fabricated monolithically as suggested by Figure 2 [61 from a common epi layer. The FET and BJT portions are then interconnected in Darlington configuration. EMITTER n + SUBSTRATE In the Darlington configuration, both the FET and the BJT must be rated to withstand the maximum voltage that the combined device will see in the circuit. The applicable voltage rating for the BJT is its BVCEO rating, not any of the other, higher, ratings DRAIN Device Structure for Monolithic 01 and 02 Figure 2 6-131 Cascode Configuration [1,2,3,91 most of the current because of its lower conduction drop. The FET switches efficiently and is free from second breakdown, while the BJT conducts efficiently with low voltage drop. Therefore, both the BJT and the FET are well utilized. Cascode connection results in a four-terminal device requiring two drives. (See Figure lb.) To turn the combination on and keep it conducting, base current must be maintained for Q 1 and a positive gate voltage must be provided for Q2. To turn the device off, a negative or zero gate signal is the only signal required. When Q2 turns off, the emitterofQl is open circuited and collector current is diverted through the Q 1 base terminal and zener Z to the Q2 source. Ql, therefore, turns offwith a reverse current gain ofunity and the turn-off time is much shorter. When compared with conventional reverse-bias turn-off of a BJT, it was observed experimentally that the storage time can be reduced by at least a factor of 2, and the fall time reduced by a factor of 104. All that is required to turn the combination off is a small gate current to discharge the gate capacitance of Q2. The disadvantages of this configuration are that it requires not only two driving signals but also precise timing of the driving signals, and storage time of the BJT is not controlled. For these reasons, a much more complicated drive circuit is needed which must cope with temperature and loading effects as well as sequencing. As in the Darlington configuration, both the FET and the BJT must be rated to withstand the maximum voltage the combined device will see in the circuit, and the BVCEO rating of the BJT is the applicable voltage rating. Likewise, in terms of current, the BJT must be rated to carry the maximum load current while the current rating of the FET will be less; how much less may be very difficult to calculate. The high surge current ratings characteristic of FETs will be advantageous in this instance. In addition to the advantages of ease of turning-off and high turn-off speed, Ql can be operated up to its BVCBO rating without reverse bias second breakdown (RBSB). In conventional reverse bias turn-off, emitter current is constricted due to base region lateral resistance. This may cause RBSB, and therefore, the device is normally operated only up to the BVCEO rating with a snubber circuit softening the turn-off process. In the cascode configuration, the emitter current ofthe BJT is zero during the turn-off process and, therefore, there can be no current constriction. Thus, the BJT will not suffer from RBSB. This has been experimentally confirmed with a variety of devices rq. A parallel configuration can also be fabricated on a monolithic chip. With proper metalization interconnection, the structure shown in Figure 2 for Darlington configuration can be made into a parallel configuration. FET-Gated Transistor Configuration (FGT) [71 This configuration is a combination of the Darlington and the cascode configurations described above. ReferringtoFigureld, Ql is the main transistor; Q2 and Q3 are FETs that are used to turn Ql on or off. By connecting the gates of the FETs, the configuration becomes a three- terminal device. When the gate voltage is high, both Q2 and Q3 conduct. This provides base current to Ql and the entire assembly turns on. When the gate voltage is low, both Q2 and Q3 turn off, and Ql is turned off by the opening of its emitter as in the cascode combination. The zener diode Z now serves two purposes. The first is to provide the path for Ql base current when the emitter of Ql is opened during turn-off. The second is to provide a path for Q2 gate discharge current at turnoff. As can be seen from the Ql base current waveform, there is a base current spike at turn-on, a large reverse base current spike at turn-off, and a current approximately proportional to the load during conduction. This is an ideal base current waveform for a BJT and is inherent in the configuration. It is accomplished with very little drive. Ql base current is derived from the load instead of a base power supply. In the cascode configuration, Q2 must have the same current carrying capability as Ql, but the drain voltage requirement need be only 10 V. By using a low voltage FET, the voltage rating of Ql can be enhanced from BVCEO to BVCBO. This is often a 50 to 100 percent improvement. Furthermore, as the FET required is a very low voltage part, it will be much smaller than a high voltage part of similar current rating. The disadvantages, from the user's point of view, are higher conduction voltage drop and more complicated drive signals. Parallel Configuration [41 The idea behind building a device with a FET and a BJT in parallel is to allow the FET to take the beating during switching and allow the BJT to conduct the current during conduction. At turn-on, the FE T must be turned on before the BJT, and at turn-off, the BJT must be turned off before the FET. Because of this switching sequence, the BJT will never be subjected to simultaneous voltage and current stress during switching. The FET is, in effect, an active snubber for the BJT and, therefore, no additional snubber is needed. When the device conducts, the BJT carries In this configuration, both the BVDSS rating ofQ2 and the BVCBO rating of Q 1 must be greater than the 6-132 30 nsec. This is v~ry fast for a BJT of this rating. Figure 5 shows device voltage (top), BJT base current (center), and device current (bottom) during turn-off. maximum voltage that the combination will see in the circuit, while Q3 remains a low voltage device. On the other hand, Q3 must have a drain current capability equal to Q 1, while Q2 can be rated for the base current of Q 1. That is, the maximum load current of Ql divided by its forward gain at that current. Both Q2 and Q3 are, therefore, much smaller in chip size than a comparable single FET which would control the same amount of power. The voltage rating ofQ2 and Q 1 and the current rating of Q3 and Q 1 become the rating for the FGT configuration. Besides the advantage of a simple drive, there are other advantages to this configuration. Smaller gate capacitance, due to small total chip area of Q2 and Q3, is one advantage. From the user's point of view, small gate capacitance translates into smaller gate current requirement and higher dv/dt capability. Another advantage is that the total chip size of this configuration is much smaller than the size of a comparable single FET [71. The disadvantage of this configuration is the high conduction voltage drop which is equal to the sum of the VCE ofQ 1. and VDS ofQ3. Figure 4 Figures 3 through 5 show oscillogram waveforms for the FGT configuration. Figure 3 shows the base current (top) and collector current (bottom) waveforms for the BJT. Both turn-on and turn-off current spikes are evident. Figure 4 shows device voltage ( top), device current (center), and BJT current (bottom) during turn-off. It can be seen that the device voltage rises long after emitter current is cut off. In other words, the emitter current crowding phenomenon which commonly occurs in conventional turn-off does not occur in this configuration, and thus, the device is free from reverse-bias second breakdown. Also from Figure 4, it can be seen that the device storage time is about 100 nsec and fall time is about Figure 5 Conclusions BJT-FET combinational devices extend the capabilities of bipolar transistors. A Darlington configuration provides an easy-to-drive BJT. A cascode configuration enhances the voltage capability of a BJT. - ; A parallel configuration is essentially an actively ~ snubbered BJT. And the FGT configuration extends the power range of a BJT. Each of these configurations loses some useful characteristics, and none of these devices can solve all problems. However, each configuration does have applications. Of the four configurations, only cascode and Parallel have been reportedly fabricated in monolithic form. The cascode configuration has been fabricated as a power hybrid circuit. The FGT has been demonstrated as a discrete circuit. Further research in this area is needed. Figure 3 6·133 [5] M.S. Adler, "A Comparison Between Bimos Device Types," IEEE Power Electronics Specialists Conference, June 1982, pp. 371-374. [6] R. Skanadore, "A New Bipolar High Frequency Power Switching Technology Eliminates Load-Line Shaping," Proceedings of PowerCon 7, 1980, pp. D2-1-D2-14. N. Zommer, "The Monolithic HV BIPMaS," IEEE International Electron Device and Material Conference, December 1981, pp. 263-266. [7] D. Chen and J.P. Walden, "Application of Emitter-Open Tum-Off Technique for High Voltage Inverter Applications," IEEE Power Electronics Specialists Conference, June 1981, pp. 252-257. D. Chen and S. Chandrasekran, "An FETGated High Voltage Power Transistor," IEEE Industrial Application Society, 1982, pp. 713-720. [8] D. Chen and S. Chin, "Design Considerations for FET -Gated High Voltage Transistors," IEEE Power Electronics Specialists Conference, 1983, pp. 144-149. [9] S. Clements, B. Pelly, R. Ruttonsha, and B. Taylor, "High Voltage High Frequency Switching Using a Cascode Connection of Bipolar Transistor and Power MOSFET," IEEE Industrial Applications Society, 1982, pp.1395-1405. References [1] [2] [3] [ 4] D. Chen and B. Jackson, "Tum-off Characterisitcs of Power Transistors Using Emitter-Open Tum Off, " IEEE Transaction on Aerospace and Electronic Systems, Vol. AES-17, No.3, May 1981, pp. 386-391. R. Blanchard, R. Baker and K. White, "A New High-Power MaS Transistor for Very High Current, High Voltage Switching Applications," Proceedings of PowerCon 8, April 1981, pp. NI-I. 6-134 6.8 Power FET Base Drive Circuit for High Power Darlington Transistors The increasing availability of very large power bipolar junction transistors has opened up many new avenues for power electronics applications. With present device technology, power transistors having a VCBO of 600 V and an IC of 300 A are being manufactured. This development makes it possible to extend the application of transistors to integral horsepower DC and AC motor drives and similar high power and high frequency applications. the negative drive at tum-off can be applied. The first involves the use of negative bias on both base-emitter junctions (see Figure 1a). Another method utilizes a diode connected between the bases of the two transistors (see Figure 1b) to provide a path for discharge current from the base of the output transistor. This path is necessary because the driver transistor (Q2) cuts off before alI base charge has been removed f~om the output transistor (QI). Without a diode or a resistance between the bases (Rl in Figure 1), the only method of charge removal from the power device would be internal recombination which is a gradual process. The presence of the diode insures that reverse potential is applied to the output device after the driver turns off. The power MOSFET with its high input impedance and surge current capability is an ideal device for driving large BJTs. It alIows the designer to couple low level logic control circuits directly to high power transistors without other intermediate elements. Comparison of Drive Methods Both methods of tum-off were compared on the D60T-D7ST transistor pair. The first two photographs (Figures 2a and 2b) show the colIector current, reverse base current and colIector-emitter voltage for a single reverse drive and dual reverse drive. Figure 2b shows that the device has a storage time of 5.4 microseconds at a colIector current of 80 amperes. Collector-emitter voltage was 140 volts. A forward drive current of4 amperes into the base of the driver transistor was employed so that upon application of reverse drive the D60T device was heavily saturated. The reverse bias potential (7 V) applied to the two devices resulted in a reverse base current of 5 amperes. Seven volts reverse bias was used because it was the maximum voltage which the emitter-base junction of the power device could withstand without avalanching. In a power Darlington the primary drive problem occurs at tum-off. There are several ways in which There are two distinct reverse current levels during the storage time. The primary level which lasts for Described in this paper are: 1. A comparison of drive methods for high power Darlington transistors. 2. A base drive circuit design using two power FETs. A discrete power Darlington, using a Westinghouse D7ST as the output stage and D60T as the driver stage, is used as an example in the folIowing discussion. The composite device is rated at 125 amperes continuous and 450 volts. It is connected as a four-terminal device with the base leads of both the driver and output transistors available. 6-135 , "5 h o --- --- --_. -4A I I 80 A 140 v ... I- a, RE~~~SE ~ CURRENT II / I II PATH (8) Dual Reverse Dnve R, Va - --+ r- v,. II" I\. - I- & APPLIED NEGATIVE BIAS DRIVER REVERSE DRIVE -SA R. 8. A ...k- -T+ ' "5 1\ 2ND REVERSE CURRENT PATH '4. r- I" I'" V APPLIED NEGATIVE BIAS POWER TRANSISTOR REVERSE DRIVE -=- 1- r- V • • Dual Reverse Drive Figure 1 a I l}" I (b) Single Reverse Drive Storage Time Comparison (8)TS::::58~S (b)TS=S4j.C.5 Single versus Dual Drive TS Comparison (80 Amperes IC) Figure 2 circuit. In this case, however, the 7 volt negative bias voltage was applied to both base-emitter junctions at turn-off. The magnitude ofthe reverse current measured at the base of the driver transistor was slightly smaller than it was when using a single reverse drive. This happened because both reverse currents were provided by the same negative bias source. It is conceivable that with a stronger negative bias, or a system using two independent negative biases, the dual drive scheme could be more effective than the single drive scheme. a, RE~~~SE W CURRENT PATH R, .. -=-- 7 Va 2ND REVERSE CURRENT PATH ~ IJ 12 R. REVERSE SPEED-UP DIODE tPPLIED NEGATIVE BIAS DRIVER AND POWER TRANSISTOR REVERSE DRIVE ~ From the above experimentation, the single drive scheme seems to provide a good compromise between drive complexity and fast device turn off. Additionally, in the single drive Darlington configuration, the designer has some flexibility in selecting the number of speed-up diodes employed. The speed-up diodes turn on as the driver device turns off and provides a negative bias of one or more diode drops to the driver's base-emitter junction. The internal construction of the large transistor makes it a somewhat distributed device so that reverse bias voltages across emitter-base junction may also prevent dv/dtturn on of the transistor. Some empirical measurements with two and three speed-up diodes are presented (Figures 3 a and 3 b). The results of these comparisons indicate a choice oftwo anti-parallel diodes would minimize the Darlington devices' storage time effects. The storage time comparison for 1, 2, and 3 series speedup diodes using a collector current of80 amperes was 5.4, 4, and 4.3 microseconds, respectively. Single Reverse Drive (with Speed·Up Diode) Figure 1 b 2.4 microseconds corresponds to the interval when charge is removed from both the driver device and the power device. The smaller secondary reverse current level, which occurs after the driver turns off, corresponds to the removal of charge from the power device through the reverse speed-up diode. Note that the smaller current level lasted approximately 3 microseconds, indicating that contributions to the overall storage time were roughly the same for both devices. Figure 2a, a dual reverse drive, exhibits a 6 microsecond storage time which is slightly greater than the single reverse storage time. All the conditions were identical to those employed in the single reverse drive 6·136 D V ""\ r- __ Vb. 8D "~l Vbe J If'} -7V - 10 V provides isolation between the control logic and the base drive which was DC coupled to the power circuit. The HP2601 utilizes a Schottky transistor output. The open collector output of the Schottky transistor is coupled into the bases of identical npn switching transistors whose collectors were connected to a positive 15 volt supply through resistors R5 and &J. In turn, the outputs of transistors Q2 and Q3 are low pass filtered using the networks R6-C6 and R7-C7. The diodes Dl and D2 increase the noise margin of the transistors Q2 and Q3. 1 "S 2V Ie / I (a) 2 Speed-Up Diodes Vee - 2V D VO. \ 1 "S f- 1\v -7V f- r--" If'I - 10 V ~ '~) ,\ V r-r- The transistor pairs (Q7, Q6) and (Q5, Q4) are complementary emitter followers. The resistorcapacitor network at the output of (Q6, Q7) coupled with the internal capacitance of the FET IRF531 provides a slower voltage rise at the gate of the FE T at turn on. In this case, a compromise had to be reached between the requirements offast turn on for the Darlington pair and oscillations caused by stray inductance in the circuit. The zener diodes (ZD4, ZD5) and (ZD2, ZD3) provide transient protection to the gates of the FETs. R9, with a value of 114 ohm, damps oscillations excited by stray reactances at turn-off, while RIO and the internal resistance of the FET provide a means of controlling the forward current. It should be noted that the forward and reverse drive are arranged in a symmetrical push-pull arrangement. Either the n-channel FET will be ON providing forward drive, or the p-channel FET will be ON providing reverse drive to the power Dar- Vb. VO. V I (b) 3 Speed-Up Diodes Storage Time Comparison (a)Ts '" 4j.ls (bITS = 43,...5 Single Drive, Series Speed-Up Diodes Storage Time Comparison (80 Amperes) Figure 3 The Base Drive Circuit The base drive circuitry for the Darlington power switch is shown in Figure 4 and Table 1. At the extreme left of Figure 4, the optical coupler HP260 1 -15Y Z o -::- 1 C2 Darlington Base Drive Circuit Figure 4 6-137 lington. The switching waveforms shown in the oscillagrams were made using the base drive circuit described. Table 1 Component Values for the Darlington Base Drive Circuit (All resistances are rated 1/4 Watt, 5% unless otherwise specified) C2 22uF C6,C7 87.6 pF C8 130 pF Rectifier Diodes DI.D2 D3.D4 25 V tantalum A 114 F Fast Recovery Diodes QI HP2601 Optocoupler Q2,Q3 TCGI61 npn switching transistor Q4,Q7 mm5262 npn switching transistor Q5,Q6 mm3726 pnp switching transistor RI 360 R2 180 R3 510 R4,R5 1.8 k 1/2 Watt R6.R7 1.6 k Rs 680 R9 1/2 I Watt RIO 11/6 24 Watts (6·11 4 Watt noninductive resistors) RII 30 1 Watt RI2 11 ZD2,ZD3, ZD4,ZD5 4 Watts noninductive 4.7 V zener diode ZDI IN4746A 18 V zener Diode 6·138 6.9 A High Power, High Frequency FET Inverter for a Low Frequency Transmitter Introduction This paper describes a,3 kW, 150 kHz FET inverter module that is part of a low frequency transmitter. The module is a single phase bridge inverter providing a quasi-square wave output voltage. A total of 16 such modules are cascaded to provide a variable frequency, variable voltage DC-to-sinusoidal power source for feeding a low-frequency transmitter antenna. A Read Only Memory (ROM) is used to coordinate the switching of the 64 FETs in the system and to achieve sinusoidal output with controllable voltage and frequency. Figure 2 shows the timing relationship between one voltage waveform and the individual secondary winding voltages that make it up. Since the load can be inductive, capacitive, or resistive, the load current may be leading, lagging, or in phase with the output voltage. Therefore, the primary current of each inverter may also have any phase relationship to the primary voltage. Current commutation in the inverter takes place from transistor to diode or vice versa, and problems associated with power MOSFET parasitic diode recovery could occur in the inverter. Schottky diodes are used to remedy this situation as will be described in the next section. A brief description of the system will be given first Then attention will be focused on power inverter operation. Breadboard construction and experimental waveforms obtained will also be presented. FET Bridge Inverter DC-to- Sinusoidal Inverter Figure 3 shows a diagram of one inverter power bridge. The source voltage is 300 V, and the maximum switched current is approximately 15 A. A low voltage Schottky diode, in series with each FET, is included. The reason for using the Schottky diodes is to prevent momentary "shoot through" caused by slow recovery of the FET parasitic diodes. In case of reverse current flow, the Schottky diodes divert the current from the parasitic diode to the discrete fast recovery diode. This avoids the problems associated with parasitic diode recovery. Because of the speed and power requirements in this application, this is necessary to prevent Mode 3 dv/ dt problems with the power MOSFETs. Figure 1 shows the DC-to-Sinusoidal inverter using 16 inverter power modules. The secondary windings of the transformers were connected in series. Through ROM-controlled timing of inverter switching, the upper 8 modules synthesize a stepped sinusoidal voltage, and the lower 8 modules synthesize a second stepped sinusoidal voltage. The resultant output is a vector summation of the two stepped waveforms. The amplitude of the output voltage is controlled by adjusting the phase angle between the two stepped waveforms, and the frequency is controlled by varying the frequency of the clock feeding the ROM. 6-139 LEAD CT IT Block Diagram for Vector Summation Scheme Figure 1 Gate Drive Circuit forms shown in Figure 3. A dead time of1 fLS is provided in the gating waveforms between A and D and also between Band C to prevent shoot through. When switches A and B conduct, the output voltage is negative. When one of the four pairs (QB, DD), (QD, DB), (Qc. D A) and (QA, DC) conducts, the output voltage is clamped to approximately 0 V. Which of the above four pairs conducts depends on the timing of the base drive waveform and the nature of the load. In order to use the vector summation method of obtaining an output voltage, this mode of operation is necessary. The clamping mode allows the output voltage of each inverter module to be independently controlled regardless of the direction of the system load current Figure 4 is a diagram of a typical gate drive circuit The dotted portion of the diagram provides an autoprotection mechanism which prevents the FET drain current from exceeding a preset value. This feature is essential in the present application because of the number of FETs involved in the system. In the drive circuit, both positive and a negative 12 V power supplies are used. A negative voltage supply is used to ensure the cut-offofFETs. This was done in this system because switching noise generated by other FETs in the inverter may induce spurious gate voltages. A negative gate voltage supply minimizes this risk. Due to such operation, however, the electrical stress on the four FET switches may be different. Two switches may turn off at a higher level of current than the other two. Clamping Mode of Operation To have a quasi-square output voltage waveform, the inverter FETs must be gated according to the wave- 6·140 90' ,, ,, I ,I j..-_ _ _ _ _ _ ! 256 CLOCK PULSE (CP) --------1~ I 1 - - - - - 1 2 8 CP VO,2-.. 128 CP'---~ ... I" F~==~===;~~~~I~==~~~~==s,=~ 51~ 75 2~ ,I ...--75 ....-51 V02~G7~===="81====~~4~0~~~'~~==~==~~~~f I -...7..--81 V03 12 32 84 i !.- V05 V06 --.., 32 84 I V07 I 71~ 81 ,, I.... 40 81 I V08 51 75------" .... 2 ,......-51 _75 :, Timing Waveform for Synthesizing Sinusoidal Output Voltage Figure 2 Semiconductor Devices: Two power FETs (IRF450) were paralleled to handle the required current level (15 A). With available MOSFETs, paralleling was necessary. 600 V fast recovery diodes (200 nsec recovery time) were used for reverse conduction around each FET pair and a Schottky diode was used to block reverse current through each FET pair. Capacitors: Two types of capacitors were used in the circuit CL was used to block DC voltage and prevent the transformer core from saturating. A polypropylene AC capacitor was selected for its low ESR The other capacitors were connected directly across the DC bus and physically very close to the inverter leg. These capacitors were used to decouple line inductance and minimize voltage spiking when a FET turned off. A low inductance type DC capacitor was chosen for this service. Transformer: At 150 kHz operation, Litz wire was used to reduce skin effect losses, and bifilar winding was used to minimize leakage inductance. A Ferrite core was used. The transformer was designed such that the maximum operating flux density was 500 Gauss. A toroidal core was chosen to minimize flux leakage. Snubber Circuit: The voltage spiking caused by FET turn-off can be controlled by tight power circuit layout and putting capacitors across the input lines. Normally, snubber circuits not only add to the parts count but also cause undesirable circuit interaction in a bridge inverter. Nonetheless, a simple RCD snubber with a small capacitor (1000 pF) was used Component Selection and Design 6-141 YD IR 20FQ045 SD VIN 200~f 022j.1.f 450 V 600V (PHASE) T 1 331'. I I- 33j.1.8 -I I 1: A 3.1/1os ~ I I,.-02p.. :l I 1p..,.- I I D V. I I I I I I I I I I --" I I I I I : I i I 1 0 r- I I I C I I I I I I I I I I I I I I I I I I I I I I I ~ FET Power Inverter Circuit and Gate Drive Timing Waveforms Figure 3 Experimental Results around each FET pair in the breadboard. This was found to be necessary to reduce tum-off speed and noise. Since the snubber capacitor is very small, the power loss associated with the snubber remains small, and the problems associated with snubber circuit interaction are minimized Breadboard Construction: Figure 5 shows a photo of the actual breadboard. All the FETs and diodes are mounted on the same heatsink with insulating material between them. This reduces the length of the power path. Gate drive boards are on the left and the transformer is on the right 6·142 Figures 6 through 9 show oscillograms from the operating breadboard. Figure 6 shows the gate voltage and current waveforms. A reverse gate voltage is applied to the FETs during the off period Figure 7 shows the output voltage waveform, and Figure 8 shows the load current waveform. The ringing in the voltage waveform is caused by the resonance of the transformer parasitic capacitance and circuit inductance. Figure 9 shows the tum-off switching waveforms of a FET. ,----------------, TO DRAIN +12 V ~----~--~--_+--~------~----~r-_;--~r_------4r--_;----4r~ 36K 820 390 lDO 20 lW 330 IJ-F + 16VJ 5V (05W) t---_+------,--.~TOGA~ HP2601 7.8 r- I I I I 50 Q14 1470 pF 5V 2K (aS W) I 1K 20 lW Z02 L-_T--~--~--------~~~~---4----------_TI--------+----------------+----~t-~TOSOURCE I FLOATINGl GROUND lN4148 L ____________________ JI * "i -12 V 1000 p.F116 V -=- Gate Drive Circuit with Auto Protection Circuit Figure4 Gate Voltage: 10V/Div. Gate Current: 200 mA/Div. TimeScale: 500 nsec/Div. Figure 6 Inverter Breadboard Figure 5 6·143 Inverter Output Voltage Across the Load: 100 VlDiv. Time Scale: 1 sec/Diy. Figure 7 Load Current Waveform: 8 A/Div. Times Scale: 1 sec/DiY. Figure 8 Turn·Off Voltage and Current Waveforms Drain Current: 4 A/Div. Drain Voltage: 50 VlDiv. Time Scale: 200 nsec/Div. Figure 9 6·144 6.10 Linear Voltage and Current Regulators Using Power MOSFETs Introduction A wide variety of linear integrated circuit voltage regulators are presently available in monolithic and hybrid form. These devices accept input voltages in the range of 0 to 120 V, provide regulated output voltages between 0 and 30 V, and handle load currents up to 10 A. A small number of monolithic current regulators are also available, but these devices are primarily limited to low current and low voltage applications. transistors, they do not require current equalizing resistors. Reference 3 comprehensively discusses the correct techniques for successful parallel operation of these devices. Low power gate control circuitry can be designed using CMOS or BIFET op-amps that draw very little standby current. A MOSFET linear regulator that delivers 10 A or more can be built with relatively few components. A separate driver transistor, necessary to boost the output current of an op-amp or other amplifier to drive a large series pass bipolar transistor, is unnecessary with a power MOSFET. When the voltage and/or current requirements of a particular application exceed the capabilities of the available IC regulators, one must turn to a discrete design. Power MOSFETs when operated in their saturation region [1] can be used to replace bipolar transistors as series pass elements in linear regulators. There are two major advantages in using MOSFETs over bipolar transistors: This section describes four selected voltage and current regulator circuits that make use of both openloop control (no feedback) and closed-loop control (with negative feedback) to regulate the output. Each circuit has its own inherent benefits and drawbacks that will be discussed in detail. 1. The average gate drive current for a MOSFET is considerably lower than the average base current of a comparably rated bipolar transistor. Voltage Regulator Circuits 2. A MOSFET can be operated at rated breakdown voltage and maximum drain current under certain pulsed conditions. Consequently, MOSFETs have a full rectangular SOA curve whereas bipolar transistors do not. [2] Linear voltage regulators generally take the form of a series-pass circuit in which the pass transistor sustains the difference between the input and output voltages. The simplest series-pass MOSFET regulator is shown in Figure 1. This is an open-loop circuit in which the IRF130 is operated as a DC source follower. The output voltage is equal to the MOSFET gate voltage (VG) less the value of gate-to-source voltage (VGS) Additionally, MOSFETs are easy to parallel if the proper precautions are taken, and, unlike bipolar 6·145 necessary to sustain the load current. Since the gate voltage is equal to the voltage generated across R1by current 11 the output voltage can be shown to be: (1) VOUT = I1 R 1-V GS VIN I-....:.!...--/ i.., When, for example, the output voltage of the regulator is adjusted to 5 V at a load current of 1 A, as lOUT is increased to 10 A, VOUT drops by 2.3 V to 2.7 V. This drop in output voltage with increasing load current is undesirable, but is an inherent characteristic of the circuit. Consequently, this type of regulator is not suited to low voltage applications because the percentage change in output voltage can be as high as 50%. Rather, it is suited to the higher voltage applications (20 V and above) where the percentage change in VOUTwill be much lower (10% or less). I. Q1 IRF 130 TI"'-55-<:- iiirl 125"'1 1) = VII TI =2."C_ VOUT Til" I ! This Simple Adjustable Output Voltage Regulator Uses an IRF130 MOSFET and a Small Number of Additional Components Figure 1 ~ ~~ • 25 (2) + VGS] (3) while the minimum output voltage is zero. Additionally, the value of drain-to-source voltage for the MOSFET should never exceed its rated BVDSS· Thus, IVIN-VOUTlmax = BVDSS ~GS INCREAS:NG W~H TI 'J 51 / YGS DECREASING WITH TJ ~V 30 35 40 4.5 5.0 5..5 e.o &.5 7.0 7.5 VGS - GATE SOURCE VOLTAGE (VOLTS) where VT is the MOSFET threshold voltage. VOUT(max) = VIN-[VF(CR1) I'!J. ZERO C I In the circuit of Figure 1, the MOSFET will always have a value of VDS that is greater than its V GS. This is because the current-regulator diode requires a certain minimum voltage drop across itself (-= 1.0 V) to function properly. Consequently, the MOSFET always operates in its saturation region. The maximum output voltage the circuit can generate is 1,5 V TC POI T'. T ~ To ensure that the power MOSFET always operates in its saturation region, VDS;;",VGS-VT Vas The ll"ansfer Characteristics of the IRF130 MOSFET Show that for a Constant 10. Below the Zero TC Point VGS Decreases with Temperature While Above It VGS Increases with Temperature Figure 2 Additionally, the output voltage varies with junction temperature, and this variation tends to aggravate the situation described above. At low values of lOUT, the temperature variation of output voltage is dominated by the threshold voltage drift with temperature. This change in threshold voltage is typically in the range of -3 to -6 mVrC and causes the output voltage to increase with temperature in equal magnitude. For a constant value ofIOUT, an increase in Tj of approximately 100°C can cause VGS (and, hence, VOUT) to change by as much as 600 mV. (4) When the load current is increased, a point is reached where the output voltage ceases to change as the junction temperature varies. This point is known as the zero temperature coefficient (or zero TC) point and is characteristic of all power MOSFETs. Above the zero TC point, the output voltage decreases with increasing junction temperature for a constant value of load current. This occurs because the MOSFET drain current is proportional to both the channel carrier mobility (f.L), as well as the square of (VGS- Despite its simplicity, the circuit shown in Figure 1 does have a major disadvantage which may limit its usefulness. This is quite evident when the transfer characteristics of the IRF130 MOSFET, shown in Figure 2, are examined. Because the output voltage is dependent on V GS, as V GS varies with load current (lOUT) and junction temperature (Tj), VOUT varies too. 6-146 VT). Since /Jo decreases with increasing Tj, (VGSVT) must increase to sustain a given value of load current. Above the zero TC point, even the decrease in VT with temperature is insufficient to compensate for the decrease in /Jo with temperature and, thus, VGS increases. At the zero TC point, however, the tance can be determined using the approximate relation: competing effects of a/Jo and aVT completely cancel aT aT each other and VOUT remains constant. where gm is the transconductance of the MOSFET used in the output stage and AVOL(S) is the openloop gain of the op-amp as a function of frequency. Since AVOL(s) for most op-amps decreases linearly with frequency, the value of ROUT will rise linearly with frequency. This is somewhat undesirable, particularly if the regulator must power circuits whose supply currents pulsate at high frequencies (Le., audio and video amplifiers). However, a suitable capacitor connected between VOUT and ground in the circuit of Figure 3 will overcome the increase in ROUT with frequency. ROUT~ When the performance of the open-loop regulator is unacceptable for a particular application, a c1osedloop method of controlling the output voltage becomes necessary. A slightly more complex c1osedloop voltage regulator using an IRF130 MOSFET and a TL071 BIFET op-amp is shown in Figure 3. The advantage of this circuit is that the TL071 functions as a DC error amplifier and keeps the output voltage virtually equal to the reference voltage (VREF) at its non-inverting input. The output voltage is almost completely independent of the MOSFET gate-tosource voltage as shown by the following equation: (VREF VOUT = + VIO)AVOL(DC) - VGS 1 + AVOL(DC) aVO aT (6) aVREF aT avIO aT (7) Here we have assumed negligible variation in A VOL(DC) with temperature which is valid in most cases. Thus, the drift in VOUT with temperature is mainly dependent upon the input offset voltage drift with temperature and the reference output voltage drift with temperature. Both of these drift components can be minimized by using precision components for the reference voltage generator and the DC error amplifier. In some cases, the temperature coefficients of VREF and VIO may partially cancel each other if their polarities are opposite. This would then result in a temperature coefficient for VOUT that is less than either that ofVREF or VIO. . CR' 1+ + AVOL(s) --=---+ v,. R, ,.~ C, 1 The temperature variation of VOUT in this regulator can be seen to be virtually independent of any temperature variation in V GS. This is obvious if equation 5 is differentiated with respect to temperature: (5) " 1/gm The designer should be aware that since this regulator uses a negative feedback loop, oscillation can occur if the circuit has an insufficient phase margin (M).[4] Most modern internally-compensated op-amps have a single low-frequency dominant pole (usually 10 Hz to 100 Hz) as well as several higher order poles and zeroes. The frequency of the dominant pole is normally chosen so that at the unity-gain crossover frequency, the op-amp has a phase margin of approximately 50° to 80° and is stable. This Simple Adjustable-Output Closed-Loop Voltage Regulator Provides a VOUT that Is Independent of the IRF130 MOSFET's Gate to Source Voltage Figure 3 Here, A VOL(DC) is the DC open-loop voltage gain of the op-amp, VIO is the input-offset voltage of the op-amp, and VREFis equal to 11 Rl. Since A VOL(DC) is large for most op-amps (100 dB or more is typical), the variation of Vo with VGS is insignificant. This regulator will have a very low DC output resistance because negative feedback is used to maintain a constant output voltage. The closed-loop output resis- The addition of a MOSFET output stage to the opamp in Figure 3 adds two poles and a zero to the loop transfer function[5]. This addition can result in an 6·147 conduct a drain current, independent of its drain-tosource voltage, that is equal to overall phase margin that is near zero or even negative. For an overall phase margin of 30° or less, instability in the regulator is very likely. The HP-41 program described in Reference 5 allows one to calculate the gain, poles, and zero of a MOSFET source follower. The program can be used as an aid in plotting the Bode diagrams of loop gain and loop phase for the circuit shown in Figure 3. lOUT = V,BE(Q1) RS (8) The 1 rnA constant-current diode used in the circuit provides operating bias for the bipolar transistor and ensures that its emitter current, and hence, VBE does not vary substantially with power supply voltage. Consequently, the circuit will have a very high degree of rejection to power supply voltage fluctuations. It is difficult to provide typical Bode diagrams of loop-gain and loop-phase versus frequency for the circuit of Figure 3 because the poles of the MOSFET source-follower vary widely with different load impedances. For each load condition, a different set of bode plots would have to be generated. This can be rather time consuming. Alternatively, the regulator itself can be built and then tested with different load impedances in an attempt to make it oscillate. This, in fact, was done with the circuit of Figure 3. It was found the regulator was unconditionally stable with no load, a purely resistive load, and a parallel resistive/capacitive load. The values of capacitance used varied from 0.1 jl.F to 1000 jl.F. With a purely capacitive load of more than 10 jl.F, however, oscillation in the gate drive voltage was noticed at the output of the op-amp. The frequency of oscillation was rather low (100 to 200 Hz), and the waveform was that of a distorted sinewave. The amplitude of oscillation was quite large, being equal to the limits of the op-amp's output swing (approximately 20 Vpp), but the DC output voltage showed no signs of any perturbation. Presumably, this was due to the filtering action of the purely capacitive load. The DC output voltage remained constant at a value almost exactly equal to VREF. Consequently, this type of instability could be tolerated in certain designs since the regulator appears to operate normally as far as the capacitive load is concerned. This Simple Open-Loop Current Regulator Uses a Simple VBE Voltage Reference to Establish a Constant Drain Current In the IRF130 MOSFET Figure 4 This simple current regulator does have a major disadvantage just like its voltage regulator counterpart. This is obvious since both VBE(Q1) and the value of RS will vary with temperature. The temperature variation in lOUT can be found by differentiating equation 8 with respect to temperature: iHOUT = ~ aVBE(Q1) aT RS aT VBE(Q1) aRs RS2 aT (9) The first term in equation 9 is the dominant term since it has a multiplier of lIRS rather than 1/RS2. Therefore, the temperature variation ofVBE(Q1) is mainly responsible for the drift in lOUT. Since equation (9) does contain two terms of opposite sign, it is possible to make the output current independent of temperature if the type of resistor used for RS is chosen according to the relation Current Regulator Circuits Discrete current regulators generally take the form of a series pass circuit like their voltage regulator counterparts. In these circuits as well, the pass transistor sustains the difference between the power supply voltage and the voltage across its load. The pass transistor is forced to conduct a constant current by suitable biasing circuitry. This circuitry prevents the output current from fluctuating due to variations in power supply voltage and load impedance. RS aT VBE aT (10) which basically states that the fractional change in RS per °C must be equal to the fractional change in VBE(Q1) per °C (about -0.34% per 0C). The simplest current regulator, an open-loop circuit, is shown in Figure 4. The regulator uses the baseemitter junction of a bipolar transistor (Q1) as a reference voltage generator across the MOSFET source resistor RS. This forces the MOSFET to A modified open-loop current regulator that is similar to the previous one is shown in Figure 5. This circuit 6·148 employs a slightly more complex Widlar band-gap, reference[6], instead of a simple temperature sensitive VBE reference. The advantages of using the band-gap voltage rpference in a current regulator are improved output current accuracy and temperature stability over the VBE referenced circuit. These advantages outweigh the need for the additional components. high-wattage resistor is used as the current sensing element, and the voltage generated across this resistor is fed back to the inverting terminal of the op-amp. The op-amp thus forces the current flowing through the MOSFET to be equal to The band-gap reference has a characteristic zero temperature-coefficient point that can be made to occur at any desired ambient temperature by simply choosing the circuit values appropriately. For the circuit in Figure 5, the zero TC point occurs at an ambient temperature of approximately 2YC, and the reference output voltage is equal to the band-gap voltage of silicon (1.205 V) plus a small constant (typically less than 0.1 V) that is circuit dependent. In this case, the reference output voltage is == 1.220 V, and the output current is therefore equal to where VREF is equal to I1R1 and VIO is the input offset voltage of the op-amp. 1.220 V lOUT = - RS VREF + VIO lOUT = -===---=..=. RSENSE (12) The variation of lOUT with temperature will be rather complicated due to the fact that all four terms in equation 9 (11, R1, VIO, and RSENSE) vary with temperature. For the CA3140 op-amp, the variation of VIO with temperature is only about 5 V/aC and does not constitute a major component of drift in the output current. If we also assume that R 1 is a low TC potentiometer, then . illOUT R1 ill1 - --=---xilT RSENSE ilT (11) (11R1 + VIO) (RSENSE)2 It should be noted that in order to achieve relative insensitivity in lOUT to changes in temperature, the resistors used in the band-gap voltage reference must be low temperature-coefficient types. This necessitates the use of high-quality metal-film or wire-wound resistors and not the less expensive carbon-composition type. The reference resistor RS, of course, should also be of high stability. Here, notice that the second term in equation (10) will be dominant since it has the term (RSENSE)2 as its denominator. Thus, the variation in lOUT will be primarily dependent upon the stability of resistor RSENSE as it heats up. We now turn our attention to Figure 6 where the circuit diagram for a two terminal closed-loop current regulator is shown. This circuit uses a CA3140 BIMOS op-amp to drive an IRF130 power MOSFET that is used as the series pass element. A low-value, Because this circuit is configured as a two terminal regulator, it must operate from a minimum supply voltage of about 12 V. This ensures proper operation of the voltage regulator circuitry that supplies 10 V to the op-amp. If this minimum operating voltage is CR1 xilRSENSE ---- (13) ilT CR100 - Q41RF13D R~ I~DV NOTE 01.02 & 03 PART OF CA 3046 TRANSISTOR ARRAY This Modified Open-Loop Current Regulator Uses a Widlar Band-Gap Voltage Reference for Improved Accuracy and Temperature Stability Figure 5 6-149 "" IN IRF130 RSENSE 0.10 20W can thus regulate currents up to 10 A from a source voltage as low as 7 V. The maximum voltage that either of the circuits in Figure 6 or 7 can sustain is equal to the breakdown voltage of the IRF130 MOSFET, which is around 100 V. OUT CR100 Since this current regulator uses a negative feedback loop like the voltage regulator in Figure 3, a sufficient phase margin for stable operation is necessary. Since the MOSFET is configured as a source-follower with a resistive load of O.ln, using typical values from the IRF130 data sheet as input data for the HP-41 sourcefollower polelzero finding program [5], we obtain D1 11 V D5W gain at DC zero frequency pole 1 frequency pole 2 frequency A Closed Loop Two-Terminal Regulator Can Be Built with a CA3140 B1MOS Op-Amp, a Low-Value High-wattage Current Sensing Resistor, and a Few Additional Components Figure 6 higher than desired, the op-amp and voltage reference can be powered from a voltage doubler using the Si7661 CMOS voltage converter IC as shown in Figure 7. This IC doubles the 5 V output from the voltage regulator to 10 V. With this modification, the circuit These pole and zero frequencies of the MOSFET source-follower combined with the 30 Hz dominant pole of the CA3140 and its higher order poles and zeroes, allow for stable operation with a feedback factor of unity as used in the circuits of Figures 6 and 7. "" D,62V RSENSE 010 20W IRF 130 IN D5W +0.2857 -979.4 MHz -4,707 MHz -2.753GHz ., 1 7661 OUT + C2 NC ·2 10ILF 15V 1M ThiS Modified Two-Terminal Closed-Loop Current Regulator Permits Operation from Applied Voltages as Low as 7 Volts, Due to Its Use of an SI7661 as a Voltage Doubler That Supplies the Op-Amp Figure 7 References [1] Adolph Blicher, Field Effect and Bipolar Power Transistor Physics, Academic Press, 1981, pp. 238-243. [4] Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, 1977, pp. 503-505. [2] Rudy Severns, "Safe Operating Area and Thermal Design for MOSPOWER Transistors," Siliconix Application Note AN83-10, November 1983, pp. 13-15. [5] Mark Alexander, "Frequency Response Analysis ofthe MOSFET Source-Follower," Siliconix Applications Note AN83-8, November 1983. [6] Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, 1977, pp. 258-260. [3] Rudy Severns, "Parallel Operation of Power MOSFETs," Siliconix Applications Note TA84-5, June 1984. 6·150 6.11 Frequency Response Analysis of the MOSFET Source-Follower (AN83-8) Introduction Power MOSFETs are becoming increasingly popular as output stages of linear power amplifiers. This trend will continue as the cost of these devices relative to bipolar transistors continues to decrease. Analysis of the Three-Capacitance MOSFET Model Figure 3 shows the schematic diagram of the threecapacitance MOSFET model. Rgen is the generator output impedance used in the test setup although the output impedance of a driver amplifier stage could be substituted instead. Rge is an external gate resistor usually included to suppress any potential parasitic oscillation that might occur in the circuit. Rgi is the intrinsic gate-electrode resistance of the MOSFET, and RL is the load resistance. Perhaps the most widely used MOSFET output-stage is the source-follower confIguration. It offers certain advantages over other types of output-stages: • When used in a complementary arrangement with Nand P-channel devices (see Figure I), only single-node drive is required. • Since the voltage-gain is positive and close to unity, the effective gate-to-source capacitance is V+ reduced. • The output impedance is only of the order of a few ohms or less. VDRIVE These characteristics make the source-follower suitable for use in wide-band, high-speed amplifiers, particularly for audio applications. Most designers of audio power amplifiers with MOSFET output-stages, however, use only the single-capacitance MOSFET model (see Figure 2) in their frequency response calculations. Experiments have shown that the actual -3dB frequency of a source-follower can be less than half that calculated using the singlecapacitance model. N-CHANNEL MOSFET VOUT .. I I l~N".~ Clearly, the single-capacitance MOSFET model is inadequate for frequency response calculations. What is needed is a more comprehensive model that will enable a designer to accurately predict how a MOSFET output-stage will behave with frequency. The three-capacitance model satisfies this requirement. V- V- A Complementary MOSFET Output Stage that Needs Only Single-Node Drive Figure 1 6-151 Rge Rgen G o Rgi Rgen Rge G Vo The Single Capacitance AC-Model of the MOSFET Source-Follower Figure 2 RL The Three Capacitance AC-Model of the MOSFET Source-Follower Figure 3 The analysis is as follows (refer to Figure 3) 1. KCL at N1 (IiNl = 0) Vo -0 - - + (Vo - O)SCds - gmVgs - VgssCgs = 0 RL Vo = gmRL + sRL Cds Vgs 1 + sRLCds 2. (1) KCL at N2 (IiN2 = 0) ((Vgs + Yo) - O)SCgd + (CVgs + Yo) - Vo)sCgs + CCVgs + yo) - VO = Rgi CVgs + Vo)SCgd + VgssCgs + VgsCSCgd + V~) - VO + Rge + Rgen CCVgs Rgi 0 + Rge + Rgen =0 + sCgs + 1/(R gi + Rge + Rgen)) + Vo CSCgd + 1/CRgi + Rge + Rg~n)) - Vi/(Rgi + Rge + Rgen) = Vgs= 1 s{Cgd + Cgs) + lICRgi + Rge + Rgen) [Vi Rgi + Rge + Rgen - VoCSCgd V gs - 1 + sCR . + Rge 1+V R )CC + C · ) [ I - V 0 C1 gl gen gd gs 6-152 0 + 1/(Rgi + Rge + Rgen)] + S (gl R· + Rge + Rgen)Cgd ] (2) 3. Substituting (2) into (1) and simplifying. 1 Vi + sCgs/gm x-------------------------------------------------1 + gmRL 1 + s [RL ((Cgs + Cds) + (Rgi + Rge + Rgen)(Cgs + (1 + gmRL)Cgd)] 1 T 52 [ RL (Rgi + Rge + gmRL (3) + Rgen)(Cds(Cgd + Cgs) + CgSCgd)] 1 + gmRL Since this transfer function is of the form: Vo - Vi = DC gain (1 (1 + ST3) + sTl)(1 + ST2) where fzero = - 1/(217' T3) fpole l = - 1/(217' Tl) fpo le2 = - 1/(217' T2) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 by setting the denominator of (3) equal to zero. it is then of the form ax 2 + bx + c= O. The quadratic formula can then be used to find the two pole frequencies. HP-41 Program "SFANL" An easy to use program for the HP-41CV programmable calculator was written to perform the somewhat tedious calculations involved. It features prompting for the eight input variables (Rgen• Rge. Rgi. RL. Cgs • Cgd. Cds. and gm) as well as the four output variables (DC gain. fzero • fpolel. and fpole2). The program has two entry points. the first being the initialization section where input data is prompted for and put into registers RO through R7. The second is the entry point into the calculation section of the program. which assumes that input data is already present in RO through R7. This second entry point is useful if only one or two input variable~ must be changed before a subsequent run of the program. The program listing is as follows: a) Main program SFINT/SFANL 01 02 03 04 05 06 07 08 09 LBL TSFINT TENTER GM PROMPT STO 00 TENTER CGS PROMPT STO 01 TENTER CDS PROMPT entry point for initialization begin initialization 6-153 STO 02 TENTER COG PROMPT STO 03 TENTER RGI PROMPT STO 04 TENTER RGE PROMPT STO 05 TENTER RGN PROMPT STO 06 TENTER RL PROMPT STO 07 LBL TSFANL RCL 00 RCL 07 Initialization done Entry point for calculations Begin calculations * + STO I STO RCL RCL PI * 2 mil I ENTER! ENTER! 1 08 09 00 01 DC gain calculated. save in Rg 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 * / CHS STO 10 RCL 08 RCL 03 save in R10 * RCL + RCL RCL + RCL + 01 04 05 06 * RCL 01 RCL 02 + RCL 07 * + RCL 08 STO 11 Denominator s coefficient calculated, save in R11 RCL 01 RCL 03 + RCL 02 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RCL 01 RCL 03 * RCL 11 RCL 12 XEQ TaROOT FS? 09 GTO TCMPLX PI 2 f po le1 calculated, save in X X< >Y PI 2 X<>Y TGAIN = ARCL 09 PROMPT TFZER = ARCL 10 PROMPT TFPL1 = ARCL X PROMPT TFPL2 = ARCL Y PROMPT GTO TSFANL LBL TCMPLX TCPX POLES PROMPT END Display DC gain Display f zero Display f po le1 Display f po le2 Loopback Prompt if poles are complex b) Subroutine aROOT (finds roots of ax 2+bx+c=0) * + RCL 04 RCL 05 77 + 78 RCL 06 79 + 80 * 81 RCL 07 82 * 83 RCL 08 84 85 STO 12 86 87 88 89 90 91 92 fzero calculated, 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Denominator s2 coefficient calculated, save in R12 Find roots of denominator Complex roots? Go if yes 6·154 LBL TaROOT CF 09 STO 19 RDN STO 18 RDN RCL 19 Entry point for aROOT Save a in R19 Save b in R18 * 4 * RCL 18 Xt2 X< >Y X Y STO 19 RCL 18 RCL 19 VARIABLE SAMPLE DISPLAY OC gain fzero fpolel fpole2 "GAIN = 888.9E-3" "FZER = -265.3E6" "FPLl = -1.964E6" "FPL2 = -61.21E6" A test was run to verify the program does indeed calculate values that match those taken from a test setup. In this case, a Siliconix VN1200A N-channel power MOSFET was connected as a class A source-follower with 24.0V between its drain and source. Also, the OC gate bias was adjusted so that the OC drain current was equal to 750 rnA. Complex roots calculated, return Under these conditions, the following data was recorded: + RTN END Real roots calculated, return Program Use and Verification Note: SIZE on the HP-41 CV should be set to 20 or greater, and the ENG 3 display-mode should be selected before using this program. Running the program IS a very simple procedure. When starting from label SFINT, after each prompt the appropriate input value should be entered into the X register and the RIS key pressed. gm Cgs Cds Cgd Rgi Rge Rgen RL REGISTER PROMPT Ro "ENTER "ENTER "ENTER "ENTER "ENTER "ENTER "ENTER "ENTER Rl R2 R3 R4 R5 R6 R7 GM" CGS" COS" CGO" RGI" RGE" RGN" RL" After the eighth Input value has been entered and the RIS key pressed, the HI'-41CV Will calculate and then display the four variables. After each variable is displayed, the IUS key should be pressed to see the next one. When the last variable is displayed, a subsequent pre~b of the RIS key Will restart the program at label SFANL. The output-variable sequence and sample display is shown as follows: VALUE UNITS 1.5 770 150 45 5 4.3 50 8 345.6 0.930 AIV pI<' pF pF n Kn n n kHz The non-dominant pole and zero frequencies were not measured since they were outside the measurement range of the equipment used. The input register map and associated prompts are listed below: VARIABLE VARIABLE gm Cgs Cds Cgd Rgi Rge Rgen RL f-3d8 DC gain Using the test data as input to the HP-4l program, the follOWing results were calculated: VARIABLE VALUE OC gain fzero 0.923 -310.0 -350.7 -171.7 fpolel fpole2 UNITS MHz kHz MHz Comparing the calculated dominant pole (fpoleO with the measured value, it can be seen that the program does indeed work very well. In this case, the error in the calculated dominant pole was approximately 1.5%. Clearly, till' thn'p ('apaCltance MOSFET model is quite adequatl' for fn'qul'ncy response analysis m the range of DC to a f(,w MHz. At higlU'r frequencies, though, package mdu('tan('l' and ('apacltance must be mcluded In the MOSFET modl'1 for an an'urate analYSIS. 6-155 6.12 Stepper Motor Interface "Commands, controls and data are more and more in digital form since digital information is readily manipulated, inexpensively, with integrated circuits. Thus, when an output motion is desired, a digital device (the stepping motor) provides a logical link between digital information and mechanical translation. " Flexible logic, not fixed, that can interpret instructions and issue control commands to the motor may be designed to take full advantage of the motor's strengths while avoiding its weaknesses. Driver Circuits The simplest motor drive scheme is called unipolar drive, (illustrated in Figure 1). There are two windings per motor phase, one for each polarity of magnetic field to be generated. Thus for one polarity of field, we close SW1; for the opposite polarity in the same motor phase, close SW2. This is a common arrangement which keeps drive circuitry simple, but does not make optimal use of the motor windings. Only half of the copper is in use at any given time. That's the opening statement in the introduction to one stepper motor manufacturer's handbook. The book then continues for the next 60 pages explaining this "Digital Device" in terms of slew rates, angular accuracy, ramping rates, inertia, load, torque, etc., none of which is digital terminology as encountered in everyday conversation. Introduction We can make better use of the motor windings by passing current in either direction, as appropriate, through each winding. Many high performance motors have only one winding per motor phase and require that "bipolar" drive be used. With other As long as physical laws are enforced, motion control systems will never be fully digital. However, if the stepper motor selected satisfies the load requirements, the motor/controller subsystem can be made to appear as a digital appendage to the logic system. In the past, attempts to achieve this relationship between stepper motor, controller, and logic system resulted in difficult and clumsy designs. But with the recent availability of new integrated circuits, power switches, and software specifically designed for stepper motor control, system design has been greatly simplified. v+ Between the logic system's commands and the motor lie two distinctly different problems. One problem is applying power to the motor's windings with sufficient voltage and current, at the precise time, with minimal power losses in the drive circuitry. The second problem is to create the necessary logic for motor control Simplified Diagram of a Unipolar, Resistance-Limited Drive Figure 1 6·156 motors, the two windings for a given phase can be connected in series. Since twice as many turns are energized, only half the current is needed for a given motor torque. In this article, we will concentrate on ways of implementing this "bipolar" drive. devices for switches to ground allows the use of the same logic sequence used for a unipolar coil drive. The H-bridge also requires twice as many power devices per coil as the two-supply bipolar method. Nevertheless, cost does not increase proportionately because the power-switch's voltage rating has been reduced by half while maintaining the same voltage drive across the coil. The term "bipolar" in this context refers to the two directions of current carried by each winding-not to bipolar transistors. In fact, we will use power MOSFETs exclusively as power switches since they are an advance which eases our job. The Power Switches Bipolar drive can be obtained by two methods. The half-bridge design, Figure 2, maintains one end of the coil at ground and switches the other between V + and V - , thereby reversing the current through the coil. The second method powers the coil with a single supply in an H-bridge configuration, Figure 3. In this case, either SW1 and SW4 can be on with SW2 and SW3 OFF, or vice versa, causing the polarity at the ends of the coil to reverse. v+ v+ v- v- Power MOSFETs have been improving steadily and are now ready to take over the job of H-bridge switches. Power MOSFETs are now commonly available up to 400 V at 20 A which provides a range capable of driving most available stepper motors to their performance limitations. Several direct advantages are gained with power MOSFETs when compared to power transistors. One distinct advantage is their speed. In power switching applications such as these, device heating is always a major concern. The faster any power device can be switched through its linear region to a state of minimum drop across the device, the more its internal heating will be minimized. Speed in the power MOSFETs, combined with the fact that they are nonsaturating, also allows balancing their turn-on and turn-off times. This eliminates the necessity of adding excessive "dead time" to avoid simultaneous device conduction when reversing the direction of current flow through the coil. With all this speed, at the power we're talking about, comes a good-news/bad-news story. The good news is that even very large power MOSFETs are extremely fast when driven as hard as the Si7250 drives them. In one lab setup, an IRF9530 switching three amperes turned off in seven nanoseconds, for a rate of change of current near 450 amperes/microsecond! One would expect it to switch even larger currents with comparable switching times, for still larger dIldt. Switchingtype power regulation (covered later in this article) can be done very efficiently with negligible power loss. Simplified Diagram of a Bipolar Drive Figure 2 The bad-news part of the story is that these rapid current changes make stray wiring inductance very important. That aforementioned test setup kept losing power devices when operating at higher currents, well within the device ratings. The problem was a piece of number 16 wire three inches long connecting the p-channel drain (which was switching) to the n channel drain (and internal diode). Its 70 nanohenry inductance developed a 30 volt spike when the p-channel device turned off. At full current, that spike rose to 90 volts, which, combined with the V + supply, exceeded the device's drain voltage rating. Simplified Diagram of an H-Bridge Circuit Providing Bipolar Drive Figure 3 Although the H-bridge drive reduces the number of power supplies required, this occurs at the expense of logic complexity. However, the use of p-channel devices for switches to the V + supply and n-channel 6-157 - ! The cure for the problem is easy. With the TO-220 drain tabs mounted side by side and strapped together, the inductance, and resulting voltage spike, are greatly reduced. As a similar precaution, the entire power path from the p-channel source through the supply bypass to the n-channel source should have a comparably low inductance. Wide foil conductors and switcher-rated capacitors are strongly recommended. In cases where inductance is unavoidable and extreme switching speed is not essential, one can simply reduce the switching speed. In the lab setup mentioned previously, a 100 ohm resistor in series with the device gate was sufficient to obtain safe operation even before fixing the offending wire. The switching times were still negligible. Switch Drivers Another advantage of power MOSFETs is that once they are turned ON, they need no drive power to remain ON. If a driver was then defined that would take advantage of these properties, it would have sufficient current capability to drive highly capacitive loads during transitions. But upon reaching a static condition, it would consume minimal power. One such integrated circuit designed especially to drive power MOSFETs is the Si7250. The Si7250 provides four sets of complementary outputs specifically designed to drive two H-bridges. Internal logic locks out any "illegal" inputs which could result in turning ON both devices in one leg of either H-bridge. Another feature is that the timing offset (skew) between each set of complementary outputs is specified, which eliminates some possible timing concerns. Another concern when using power MOSFETs is the nature of the load they present to their drivers. This load is purely capacitive and, under certain circumstances (during transitions), can be sizeable. Thi!\ capacitance need not be of particular concern if thoroughly understood. * Combining MOSFET H-bridges with the Si7250 driver is a simple, efficient way of obtaining a bipolar drive. Figure 4 shows how the Si7250 and a pair of VQ3001s combine to drive a stepper motor. The VQ3001 ·Oxner, Edwin S., "Power FETS and Their Applications," PrenticeHall, Inc., Englewood Cliffs, N.J., 1982. + 14V S1nso INPUT LOGIC BIPOLAR FULL STEP 1 1 1 0 0 0 1 1 o BIPOLAR FULL STEP 817250 STEPX+X-Y+Yo 1 0 1 o o STEPPER MOTOR COIL CURRENT FLOW BIPOlAR HALF STEP .,7250 STEP X+ 0 0 0 1 1 1 1 1 0 x- v+ v1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 0 STEP 1 1 0 0 0 1 1 1 1 Combining a Power MOSFET H-Bridge with a Predriver Bipolar Drive Figure 4 6-158 COIL A +1 +1 -1 -1 +1 BIPOLAR HALF STEP STEP +1 -1 -1 +1 +1 COIL A +1 +1 +1 0 -1 -1 -1 0 +1 +1 0 -1 -1 -1 0 +1 +1 +1 provides an H-bridge, two p-channel and two n-channel devices, in each fourteen-pin package. This compact three-package set results in an efficient driver for stepper motors up to a maximum drive voltage of 14V, the VDD limit of the Si7250. to the desired level, we must prevent it from rising further. Smaller motor applications commonly use a series resistor (perhaps winding resistance) to limit the current. This also slows down the current rise somewhat. Worse yet, the resistors necessary to limit the current in a large motor could easily dissipate a kilowatt of wasted power. They can also dissipate budgets and space. For stepper motors requiring higher voltages, the Si7250 controlling the p-channel devices in the V + end of the H-bridges must be isolated from the rest of the circuit and referenced to V +, as in Figure 5. A separate Si7250 is then used to drive the n-channels. Another method of limiting coil current is to remove the applied voltage once the current reaches the required level. In Figure 6a, for example, SWI and SW4 are turned ON to cause forward current through the motor's coil. Soon the current has built up enough to cause the current sensor in series to open SWl, the coil rings back against diode D3, and current flows through the path shown in Figure 6b. Since there is little voltage drop around this new path, the current decreases only slowly, but eventually drops below the current sensor's lower threshold. This causes SWI to close again bringing the current back up to its nominal value. A Watt Saved is a Watt Earned All the circuits discussed thus far depend on series resistance to limit the coil current. With high performance motors, this can waste considerable power. To achieve high step rates, large supply voltages must be used to cause the rapid build-up of current in the windings. The time required to cause a current change (M) in an inductance (L) is just ~I = Ltv, where V is the voltage applied. Once the current is up +5Y VDRIVE r - - - - - 817250YDD - - - - - ,114 I N X+IN I 1'5 3 X+OUT X + OUT I 113 N x::-iN X - OUT I '-C~I-",'2'_O X - OUT I I r-t:......;-il",-0'_O 111 {l! Y+iN v + OUT Y + OUT V-OUT {l! v:Tti (YORIVE -12 V) +-__--"-+.::.'2.!.Y_ _- - , YDD r- - 31 ---517250- ----1,4 X+OUT rl:>-r-o-=.=~-+t--lE6 L..tt-lr----~~~~~~~_r~~--Lt~I~'5~ CS X+OUT I 4---I-----l-'x!..:-:...!'N~...,.l..J...t:;:::)~o-**=r\_~I>c>_1I~'3!..o x - OUT X-OUT Y+OUT +-______ L__ <>-=++++---i Y+OUT +I~~H4~:>~~-F~~~"'-O--RESET Y+IN L____~Y~-'~N~;l~~~-==l~-~~~Y-OUT V-OUT _______ J t----------'GND Variation of the Circuit in Figure 4 for Higher-Voltage Stepper Motors Figure 5 6-159 This cycle resembles the action of a switching-type (pulse width modulated) power supply. The average current drawn from the power supply is a small fraction of the coil current. Not only is power saved, but the p-channel switches can be sized for their smaller average current. Since p-type silicon has a lower mobility than n-type, p-FETs occupy more real estate for a given current rating, and silicon real estate is expensive. The potential savings from requiring less of the p-channels can be considerable. v+ sW> sw. Another advantage of the H-bridge is illustrated in Figure 6c. Coil current is brought to zero simply by opening all the switches. The current path is through the diodes D2 and D3. The voltage across the coil is large and reversed, so the current decays as quickly as it originally built up. The energy stored in the coil is returned to the supply capacitor. (a) v+ Although the source-to-drain diodes inherent in power MOSFETs can be used for Dl through D4 in Figure 6, they are not well suited for use in a high frequency current-regulating bridge. Being pn diodes, they exhibit minority-carrier storage time and reverserecovery delay. Consequently, when D3 carries coil current in a current-regulating bridge, it stores charge. When SWI recloses, that charge is removed rapidly, creating a current spike in addition to the coil current. This extra current flow will cease abruptly when the stored charge is exhausted. The resulting large value of dlidt can cause a damaging voltage spike. While the origin of this spike is different, the result may be the same as previously: bridge failure. (b) In some cases, the same low inductance construction techniques discussed previously will be an effective remedy. For additional protection, Schottky-type diodes can be added across the internal pn diodes to carry most of the current. Preferably, they should be connected from drain to ground, as shown in Figure 7. Standard-recovery (not fast) pn diodes may also work here because their slow recovery time lets them act as "snubbers". Adding series resistance to the gates of the FETs to slow their turn-on time provides compatibility with FET diode reverse recovery time and can also solve this problem. Further, at least one supplier appears to be adjusting FET process parameters to soften internal diode recovery, and the problem may soon quietly disappear. v+ sw> sw. Like any semiconductor device, a power MOSFET can be destroyed by excessive voltage, current, or power dissipation. Moreover, its extreme speed capability makes over-voltage (spiking) of particular concern if circuit inductance is not carefully controlled. But these are the extent of their failure mechanisms. Current crowding and secondary breakdown phenomenon associated with bipolar transistors do not exist with power MOSFETs. (c) Simplified diagram of a current-limiting coil driver. Connecting the power supply to the coil causes coil current to rise, (a). When current reaches the required level, SW1 opens and current starts to decay, (b). Diode D3 retards the rate of current decay, its anode may be connected to ground for improved efficiency. With al\ switches open, the coli returns energy to the power supply, (c). Figure 6 6-160 R - SEE TEXT . -__ ~ __. -________ ~ ____ ~ __,-_v+ 5000j.tF +" RATED FOR SWITCHING POWER SUPPLY SERVICE 2K 2K 2K 1/474LS175 Q D 0010 0010 470 20K +, 2K 2K 2K 1/474LS175 Q D 470 20K ...n.r 100kHz Diagram of a practical current-limiting coil driver. The p-channel devices are switched off by current sensors when coil currents reaches 10 A. Operation is similar to that of a switching type power supply. The Schottky diodes and resistors R are antispike-measures discussed in the text. Figure 7 These devices excel in handling high peak current so long as average current and dissipation ratings are observed. Current gain does not sag at high current levels, nor does leakage to the gate endanger stability at high temperatures. Finally, MOSFETs parallel easily; the positive temperature coefficient of saturation voltage tends to make the devices share current evenly. the comparator collect its wits before being asked its opinion of the current level. This precaution can avoid a spectacular oscillation. Generating Driver Signals Fixed logic may suffice in stepper motor applications - - . not requiring long or fast traverses. But to obtain high . . . . . slew rates, the use of fixed logic is ruled out by the I stepper motor characteristics demonstrated in Figure 8. To avoid losing synchronization during start up, a stepper motor must accelerate from a "rest" position by some tapered acceleration profile, up to its maximum step rate. The same dynamics, of course, apply to decelerating the motor and load to a stop. Both problems can easily be solved by controlling the motor with algorithms in a micro controller. A Circuit in Practice A practical current-regulating H-bridge is shown in Figure 7. The current-sensing comparators have thresholds of 95 mVand 105 mV for a 10% hysteresis. Using low inductance current-sensing resistors, filter capacitors, and power distribution conductors is essential, but even with all reasonable precautions taken, the comparators are likely to do peculiar things for a few microseconds after the bridge switches. (A 10 A, 100 ns, 60 V switch is, after all, a fearsome neighbor!!!) The clocked D flip-flop is included to let Companies offering "motor controller ICs" have developed motor control software and stored it in the permanent memory of standard microcontrollers. 6·161 10,000 r-r-,---,--rrrrrrr----,---r-,--rrrTTr-,--"rrrrrn ',000 I------P""-----"_-t--------j z ~ w DISTANCE TRAVELLED (STEP NUMBER) "~ S 500\-------+-------\,--1-----'\------1 00'---'-L-L.J.-LJ..J..U.L,OO,----'---'-"--"-.L1.J."LL OO-O ---'---'-'-.L...L.JLJ:,O"',OOO DISTANCE (OR ANGLE) SPEED (STEPS/SEC) TRAVELLED Determining stepper motor operating constraints. Curve A is generated by plotting the maximum load under which the motor can start at various step rates and turn through one shaft revolution without losing synchronization. Curve B is generated by plotting the greatest frictional load the motor can drive without losing synchronization after accelerating to various speeds. FigureS DISTANCE TRAVELLED (STEP NUMBER) (a) (b) Stepper-motor shaft motion for constant acceleration controllers. For step-rate based controllers, the relevant plots are /LS time (a). For step-time based controllera, they are /LS step number. Figure 9 Any processor fast enough to outrun the motor, execute the algorithms, and manipulate the control lines will work. If a ready-made controller performs satisfactorily then it may be the quickest and most economical solution. But if available controllers lack some required performance features, or if a more specific acceleration curve is required for a specific motor/load combination, then coding your own controller may be the answer. Setting out to do so requires going back into the analog world of motion. number, and the time interval between the initiation of two steps is the difference between two square roots, However hard it is to calculate the length of the next step, we need only do it once for each step and save the results in the form of a look-up table. For applications where the system's properties are known when the code is written, calculate the step lengths directly in microseconds or in multiples of whatever units your timer counts in. For a more general controller, all we need is a table of relative step durations to be multiplied by a constant for any particular controlled system. The results are easy to use (Attachment, "Accelerating the Stepper"). Available torque for a typical stepper motor is nearly constant over a wide range of speeds, (Figure 8). Consequently, with a proper drive sequence, the motor can maintain constant acceleration. If acceleration does not exceed torque capability, the motor will reach its maximum step rate without skipping steps, an essential requirement for open loop motion control systems. Once the motor accelerates to its maximum step rate, the step intervals are held constant. To decelerate the motor, the microprocessor reads backward through the look-up table, commanding increasingly longer step intervals until the motor comes to a stop. The number of steps needed for deceleration will be equal to the number required for acceleration. If the required traverse is small, there may not be enough steps available to accelerate to the maximum step rate within the motor's torque limits. In this case, half the traverse will be spent accelerating and the other half decelerating with the maximum step rate never being reached. If the number of steps is large enough, the motor will accelerate to its maximum step rate with more than half the steps remaining. It will command full-speed steps until just enough steps remain for deceleration, then decelerate back to stop, Hard-wired acceleration controllers usually generate a pulse train with a linearly increasing frequency since linear voltage-controlled oscillators are easy to make in analog circuitry. This approach was convenient with hard wired controllers; however, microprocessor-based controllers require a different approach. Several microprocessors are available with built-in timers fast enough for motor step timing, but all of them are programmed in terms of time interval, not frequency. A microprocessor must be told how long to wait before issuing the next motor step. This information can be easily derived from a curve showing speed and elapsed time versus distance (shaft angle or step number), Figure 9. Both speed and elapsed time are square root functions of the step 6-162 Available torque may decrease as motor speed rises due to friction and other effects. In such cases, acceleration must be tapered down as speed increases. One convenient, approximate way to do this is by adding a constant to the step interval. For the first few steps where the intervals are long, the addend has little effect. As the speed increases and the step intervals shorten, the addend becomes increasingly larger in proportion to step length and prevents the motor speed from accelerating as fast as it otherwise would. either clockwise or counterclockwise shaft rotation. Regardless of the motor type used, the sequence of coil-current commands can be listed in a pair of tables-one for clockwise and one for counterclockwise steps. The last command to the motor drive can be saved as an index for moving to the next command. Figure 10 shows how this technique operates for a two-coil stepper motor in a half-step mode. The command bits are simply the required inputs for the Si7250 driver. Each 4-bit word is used both as a command sent to an output port and as an index for looking up the next command. Changing from one motor or mode to another only requires changing the look-up tables. A good choice for the constant addend is one-half of the full-speed step interval. This value increases the duration of the shortest step by 50%, and, to reach the same final speed, the acceleration sequence must include 9/4 times as many steps. The time required to reach final speed will increase by a factor of 15/8. This tapered sequence can drive the motor to greater final speeds than the linear sequence for any given initial single-step time interval. This strategy results in efficient and compact microprocessor code. The microprocessor used should have an appropriate timer and a fast multiply instruction, such as found in the MC68701 single-chip microcomputer. Using this processor, the required code and tables occupy less than one third of the internal 2K EPROM and provide motor speeds up to 7000 stepsl second. Driving a pair of H-bridges controlled with a pair of Si7250s as shown in Figure 7, the controller can solve a variety of industrial motion-control problems. The look-up table approach for step interval control can be used to establish the sequence in which motor currents are applied. Stepper motors are commonly available in a rich variety of types with 2, 3, 4, or 5 coils, "halfstep" or "fullstep" operating modes, and .....-... COUNTERCLOCKWISE CLOCKWISE - - - . X COIL COIL CURRENT USB fi 0 XV+ LSa 517250 INPUTS r- -8 A • • • D 8• - 5 A 10. Look-up table with hexadecimal commands for clockwise and counterclockwise rotation. If the coil command Is a 5, then 0 steps clockwise and 7 steps counterclockwise for a 2-coll, 4phase motor operating in haif-step mode. Table entries marked ( - ) denote illegal indexes and may be replaced by the nearest legal state. Figure 10 6-163 Attachment Since only moderate values of N are required for many applications it is often practical to precalculate + [n) and mUltiply by T (in units step lengths of 1/4 msec.) to get step duration in microseconds. When using an MC68701 microprocessor, the multiplication is 8 x 8, giving a 16-bit result directly usable by the microprocessor's 16-bit timer. Un i - Accelerating the Stepper Single-step time T is the first step interval when starting the motor from rest. This value, determined by available motor drive currents and load inertia, is obtained either by calculation or by experiment. Knowing T and the step size S in degrees of shaft rotation or units of linear load motion, acceleration is equal to 2Srr2. Suggested Reading List 1. R. Middlebrook and S. Cuk, "Advances in Switched-Mode Power Conversion," Volumes 1III, Teslaco Inc., 490 S Rosemead Blvd., Suite 6, Pasadena, CA 91107, 2nd Edition, 1983 If the first step interval of an acceleration sequence is of duration T, then step number n occurs at time Tn = TUn + 1 - [n). As n increases, step rate increases until the motor reaches full speed at step number N. This speed is approximately 2 jNff steRs per second, and total acceleration time is exactly T IN. 2. W. T. McLyman, "Transformer and Inductor Design Handbook," Marcel Dekker, Inc., NY 1978 The plot of n versus single-step speed multiples can be used to estimate the time required to complete a given motion. For example, suppose a motor must accelerate from rest to 1000 steps/second and then stop after moving a load through 200 steps. If T is determined to be 10 ms then motor speed must increase by a factor of 10. From the curves in the graph, a 10 x speed increase is reached at N = 25, and total acceleration time is 5T or 50 ms. Since acceleration and deceleration both require 50 ms and 25 steps, the load moves the remaining 150 steps at 1000 steps/second in 150 ms. Therefore, total travel time is 250 ms. 3. W. T. McLyman, "Magnetic Core Selection for Transformers and Inductors," Marcel Dekker, ·Inc., NY 1982 4. Proceedings of Powercon 1 through 11, Power Concepts, Inc., PO Box 5226, Ventura, CA 93003 5. Proceedings of the IEEE Power Electronics Specialists Conferences 1970-1984, sponsored by the IEEE Power Electronics Council 6. E. Hnatek, "Design of Solid State Power Supplies," 2nd Edition, Van Nostrand-Reinhold, 1982 7. A. Pressman, "Switching and Linear Power Supply Power Converter Design," 1977, Hayden Books 8. N. Grossner, "Transformers for Electronic Circuits," 2nd Edition, McGraw-Hili, 1983 9. J. Schaefer, "Rectifier Circuits-Theory and Design," John Wiley & Sons, 1965 10. E. Oxner, "PowerFETsandTheir Applications," Prentice Hall, 1982 11. G. Chrysis, "High Frequency Switching Power. Supplies-Theory and Design," McGraw-Hill, 1984 NUMBER OF STEPS TRAVELLED, n 12. J. Watson, "Applications of Magnetism" WileyInterscience, 1980 Motor Speed and Elapsed Time for Constant Acceleration Figure 11 6·164 6.13 Design Tips 6.13.1 Solving the Stepper Motor Interface Problems (AN82-1) Introduction Stepper motor drive techniques are evolving rapidly with their logic signals now very often being generated by microcontrollers. Off the shelf controllers such as those named here are serving many needs. As well, many users are choosing to develop their own software and apply standard microcontrollers to more efficiently suit their needs. In either case, the outputs of the controller will be TrL levels. The problem then is one of interface, applying those signals efficiently across the motor. load in less than 25ns. The optimum signal range for MOSPOWER gates is consistent with the IOV output swing of the Si7250. MOSPOWER devices once switched, require no drive to sustain their ·on" or "oft" state, the Si7250, in either static condition, draws exceptionally low power. When unselected, it powers down to an even lower current, resulting in a total motor drive circuit, both predriver and H-Bridges, which consumes less than two milliamps. To resolve the interface problem, Siliconix now offers the Si7250 H-Bridge predriver and controller, and the MOSPOWER devices necessary to complete the system. The Si7250 has TTL compatible inputs and four sets of complementary outputs, capable of driving MOSPOWER devices large enough to exercise even the largest stepper motors available, to their performance limitations. The Si7250 was designed specifically as a predriver to take full advantage of MOSPOWER's characteristics. MOSPOWER devices present a significant capacitive load to the driver during transitions. The Si7250 is capable of driving a 500pf Another distinct advantage of using the Si7250 as an HBridge controller is the safety provided by its internal logic. This eliminates the possibility of ever shorting two power devices directly across the power supply to ground. v+ Si7250 TRUTH TABLE ---'N-P-UT-P-'N-S------ - - - - - Figure 1 --- ~UTPUT-P-'N-S - - - - - - In thiS H-Bridge configuratIOn P-channel deVices are used to sWitch the coil to the (V+) power supply and the N-channel devices are used to switch the coil to GND NOTE: An driven by a on while a driven by a off. o o o o 0 0 0 0 1 0 I 0 0 1 1 o 0 a 1 , a 0 0 1 1 0 0 , 1 1 1 0 6-165 N-channel device logiC "1" is turned P-channel deVice logic "1" is turned Figure 2 shows the Si7250 and MOSPOWER H-Bridges driving a stepper motor using the VQ3001 which consists of two P-channels and two N-channels in one 14 pin package. The limitation of this circuit is that the motor drive voltage cannot exceed 14 V, the maximum operating voltage of the Si7250. +14V A ~~~tt~~----+ Y+lN~5~tt~L-~--r1~~ I &1 ~~~I~--~~~--~~ L.. _____ :!. _____ -' '::" GND STEPPER MOTOR COIL CURRENT FLOW SI7250 INPUT LOGIC "POLAR FUI.~ STEP S.725O I. o It- 1+ o Il_ ,~ V .. -0- STtP t:~~2::j . . o o : - +--'--:_,-+---'--:----1 , -, o o , , , 0 o , 0 Figure 2 world and referenced to V +. A separate Si7250 drives the N-channel end. Now the only components which care how high V + operates are the devices in the H-Bridge. Standard MOSPOWER devices are now available that extend this voltage range up to 100V (@ 20 AMPs) which should meet about any stepper motor's needs. Stepper motors may be operated in a wide range of voltages to achieve the desired responses. For higher voltage applications, it's still not difficult to use the Si7250 and take advantage of the protection and drive capabilities it provides. For higher voltage applications in Figure 3, the Si7250 which controls the P-channels in the (V +) power supply end of the bridge is opto-isolated from the rest of the 6-166 VORIVE +,y i+"iN 00-01 x:-iN N N USERS MASTER SYSTEM II-BIT) DATA BUS Y+iN n! r.l Y-TN Molor Control~t can tJ. SII·Walker PPMC-l0IB or PPMC-201A or Cybernetic Mitro 5plem. CYSOO orCV512orllqlll~.lenl +12V 12Y X+TN ES x:TN V ... OUT REffi V+"iN v::-rN _ _ _ _ .I f - - - - - - - - - - ' GND Figure 3 Both the driver CIrcuits shown so far depend on their inherent component series resistance to limit the coil current, with high performance motors, added senes resistance can waste a lot of power. At high step rates, large supply voltages must be used to make the current in the windings build up quickly. The time taken to cause a current change I in a winding of inductance L is just I· LtV, where V is the voltage across the coil (the voltage applied minus the back EMF of the motor). Once the current is up to the desired value, we must somehow prevent it from rising even higher. Small motors commonly use a series resistor (perhaps winding resistance) to limit the current, and this slows down the current rise somewhat. Worse yet the necessary resistors for a large motor can easily dissipate a kilowatt of wasted power. A better way of limiting coil current is to remove the applied voltage once the current is large enough. Figure 4 illustrates the basic idea. To send a forward current through a motor coil, SWI and SW4 turn on as before in (Fig. 4(a». After a time ILIV +, the current has built up to a value I, and the current sensor in series with SW4 opens SWI. The coil rings back against diode 03, and for awhile the current flows through the path shown in Fig. 4(b). There is little voltage drop around the path, so the current decreases slowly. Eventually it will drop below the current sensor's lower threshold, and SWI will close again for a short time to bring the current back up to its nominal value. 6-167 ~ ~ v+ ,., v+ v+ Ibl '" Figure 4 This cycle acts like a switching-type power supply. The average current drawn from the power supply (V+) is a small fraction of the coil current. Not only is power saved, but the P-channel switches can be sized to carry the smaller average current. Since P-channel devices are inherently less efficient than N-channels they occupy more silicon area for a given current rating, which is directly related to device cost. The potential savings by requiring less of the P-channels, and sizing them accordingly, can be considerable. A practical current-regulating H-Bridge is shown in Figure 5. The comparators have thresholds of 95 and 105 millivolts for a 10% hysteresis. Low-inductance currentsensing resistors, filter capacitors and power distribution conductors are essential, but even with all reasonable precautions taken, the comparators are likely to do peculiar things for a few microseconds after the bridge switches. (A ten ampere, 100 nanosecond, 60-volt switch is. after all, a fearsome neighbor!) The clocked D flipflop is included to let the comparator collect its wits before being asked its opinion of the current flowing. This precaution avoids a spectacular oscillation. ~----1-----1---1--~ 2K 2K 2K RATEDFDR SWITCHING POWER SUPPLY SERVICE 1/474LS175 a D D.01l! 0.0111 47H +5 2K 2K 2K 1/474LS175 a D 20K .n..r 47H 100 kHz Figure 5 6-168 '::' 6.13.2 The D469: An Optimized CMOS Quad Driver for MOSPOWER FET Switches (AN83-11) Introduction Many applications of power MOSFETs call for the devices to be used as on-off switches. While they can be directly driven by TIL or CMOS logic if moderate switching times are acceptable, to take full advantage of their high speed switching capabilities, a more robust driver is required. This driver should be able to provide at least 10 to 12 volts of gate drive at peak current of several hundred milliamps. The DSO026 is unsuitable for use in many applications, particularly where the control logic is low-power CMOS. Its configuration as an inverting-only driver is also an inconvenience to the designer. Clearly a device that retains the high speed drive capabilities of the DSO026 but has none of its disadvantages is desirable. Enter the 0469 IC, which was designed as an optimized driver for MOSPOWER FET switches from the start. Internally it contains four independent drive channels, and each one can be configured as either a logically inverting or non-inverting driver (see Figure 1). Since it is a CMOS device, the 0469 is compatible with low-power CMOS logic and microprocessors and draws very little current quiescently (2.5mA). Each of the O469's outputs can drive a 500pF load with typically 20nS rise and fall times and can be connected in parallel to drive larger capacitive loads if desired. Until now, the only devices capable of driving MOSPOWER FETs in high speed switching applications were discrete bipolar devices or IC's such as National's DSO026 MOS clock driver. While the DSO026 can drive a 1000pF load with typically 20nS rise and fall times, it does suffer from some serious drawbacks that restrict its use. Being a bipolar device, it draws a fair amount of current quiescently (30mA) and also requires a large logical "1" input current (lOrnA). Because the DS0026 is configured internally as a dual inverting driver, two additional TTL inverters are required to make the part usable when non-inverting drive is required. LOGIC DIAGRAM PIN CONFIGURATION IN, YDD Ifl, OUT, IN2 OUT2 1fl2 OUT3 IN3 OUT. 1fl3 Ifl. GND IN. The Block Diagram of the 0469 Reveals that Each Channel can be Configured as Either an Inverting or Non-Inverting Driver Figure 1 6-169 Turn-On Charge i!... 400 vok=bL 0 w 1\ > 200 ~ II: ::> 0 Z Ci II: 100 Q I m c > 0 '" ~ w J> CI -I :a 0 m < w U II: (II J> I- oil G) C CI m V o- '\ ~ F== Vos=O 4 m " -I > !!J o 100 ~ G) -fOOY IJ\ 0 r- _300V ~ I r- 0 5 10 15 20 25 30 35 Z 0 !:j <: 0 jLJljO- 8 in 0 c :a 200 0 m < Vos=400V- r-0 ::> 0 4 c 300 :a J> > C 8 '"'"I 12 ...0 0 ~ 400 < ~ (II * RL=1000 Vaa=10V 0 m llj ~ It o ... 16 I- G) 12 I (II Ii) < m r;, ...~ w ~ 3OOV,J 400V't5W 300 0 U Turn-Off Charge 16 200V~ V ~ CI * m <: ~ 0 0 5 10 15 20 25 30 r- -I !!J 0 - CHARGE(nC) CHARGE (nC) Switching Time Equations td(on) = ~ Rgen In (~) Vg, VGG-Vg, td(oft) = Og3- -Og2 - Rgen In (VGG) -VGG -V g2 Vg2 _Og2-0g'R gen In(VGG-Vg,) tr---Vg2 -V g, VGG -V g2 OFF t - Og2- Og, R In (V92) f-Vg2_V9' gen V; ON ON OFF Vos Vos Vaa '--!-k:t--Vg2 Vg l 10% Og1 0 g2 * Og3 Og3 TURN·ON Og20g1 VNDA GEOMETRY TURN·OFF The Charge Transfer Characteristics of a Hlgh-VoHage Power MOSFET Show the Occurence of Maximum Input-Capacitance dQldV) at a Gate-ta-Source VoHage of Approximately 7V (C Figure 2 = This applications note introduces the charge transfer characteristics of a power MOSFET and shows that the D469 is very well suited to gate drive applications. A brief discussion of additional driver power dissipation due to gate current then follows. To prove that the 0469 is a better choice than the DS0026 as a MOSFET gate driver, a comparative analysis between the two devices in switching time tests is performed. Finally, some applications of the 0469 in DC motor drive circuitry are described. At a cursory glance, the limited output voltage swing at peak current might seem to be a disadvantage. However, if one examines the charge·transfer characteristics of some of the higher current power MOSFETs, it becomes apparent that the maximum input capacitance occurs at gate·tosource voltages in the region of 7V. These charge transfer characteristics are now included in all Siliconix data sheets. Figure 2 shows pertinent data for the VNDA type geometry. The D469 and MOSFET Charge Transfer Characteristics The 0469 is ideally suited to driving MOSPOWER FETs because its peak source and sink current capability occurs in the output voltage ranges of 0 to 8 volts and 12 to 4 volts respectively, with a 12 volt power supply. When used to drive common·source connected N or P channel MOSFETs, maximum drive current is available at the point of maximum input capacitance. Each of the four output drivers in the D469 has an output resistance of approximately 8 ohms and is capable of sinking or sourcing a peak current of 500mA. The output voltage swing at peak output current is then limited to 4 volts above and below the ground and VDD rails respectively. The currents that flow in a D469's output stage during charge/ discharge cycles of the effective gate capacitance 6·170 +60V +12V 1.060026 0.11'F CERAMIC ~ 0.11'F CERAMIC 100pF 8 BNC Input lOr--+-~M.,.----<'-'~---:!.I 060026 7 TP1 620 4 +12V +60V 2.0469 0.1 I'F CERAMIC ~ 0.1 I'F CERAMIC 4.60 NON-INDUCTIVE 14 BNC Input (Q~_ _~.-.~3 5 t-----~~TP2 13 12 0469 8 IRF 243 11 10 TP1 500 2,4,6,7,9 The Schematic of the Fixture Used to Perform the 0469 versus 050026 Switching Time Tests Figure 3 A Comparative Analysis The D469 vs. The DS0026 in Switching Time Tests cause additional power to be dissipated by the driver. Equation (6) of reference 2 shows that this power is proportional to the gate-drive voltage as well as the switching frequency. For switching frequencies below 100 kHz, the additional power dissipated by the driver is so low it can be neglected. However, when the switching frequency is above 500kHz and the gate-drive voltage is appreciable, the additional driver power dissipation cannot be neglected. It should be calculated and added to the OC power dissipation of the driver. This value can then be used to determine if the operating junction temperature of the driver is within the maximum data sheet limits. 0469 and OS0026 IC's were incorporated into a test _ fixture, driving identical power MOSFETs with identical loads. Figure 3 shows the schematic diagram of this fixture. The power MOSFETs used were Siliconix IRF243s with typical gate-to-source capacitance of 1600pF and drain-to-gate capacitance of300pF. The load resistance for both MOSFETs was approximately 4.6 ohms (non-inductive), and the power-supply voltage was 60V. Both the OS0026 and 0469 were powered from a separate 12 volt 6·171 power supply and driven by a TIL level pulse train. The pulse train had a pulse width of 150nS and a repetition rate of 1KHz. Since the DS0026 contains two independent drivers and the D469 four, a fair test would be to compare the two devices as dual drivers. Thus, two D469 outputs were paralleled and compared to a single DS0026 output in drive capability. Figures 4 and 5 indicate that on a "per chip" basis the D469 was essentially the equal of the DS0026. Th be precise, the D469 waveform's rise and fall times were 36nS and 44nS respectively while the DS0026's were 26nS and 42nS. It appears that the DS0026 was somewhat faster (by IOnS) on the rising edge of its waveform than the 0469 was, but both had very similar fall times. The Rise TIme of 4 Paralleled 0469 Outputs versus 2 Paralleled OS0026 Output is Shown in this Photograph (VERT: 2.4V/Oiv, HORIZ: 20 nS/Olv) Figure 6 The Rise TIme of 2 Paralleled 0469 Outputs versus 1 OS0026 Output is Shown In this Photograph (VERT: 2.4V/Oiv,HORIZ: 20 ns/Olv) Figure 4 The Fall TIme of 4 ~aralleled 0469 Outputs versus 2 OS0026 Output Is Shown In this Photograph (VERT: 2.4V/Oiv, HORIZ: 20 nS/Olv) Figure 7 Figures 6 and 7 show the rise and fall times of the D469 with four outputs in parallel versus the DS0026 with two outputs in parallel. Here it can be seen that the DS0026 with rise and fall times of 22nS and 30nS respectively was still the faster of the two - but not by much. The D469 came in a very close second with rise and fall times of 32nS and 42n8 respectively. Interestingly enough, the rise and fall times of the D469 with four outputs connected in parallel were virtually the same as those with two outputs in parallel. The rise and fall times for the DS0026, on the other hand, showed some improvement. The main difference observed between the D469 and the DS0026 was the propagation delay-time each device exhibited. For the D469 this parameter was approximately 50nS while that of the DS0026 was in the range of 5 to IOnS. Figure 8 clearly shows this difference. It should be noted that Figure 8 is the only one in which the difference in propagation delay is shown. Figures 4 to 7 do not show The Fall Time of 2 Paralleled 0469 Outputs versus' 1 OS0026 Output Is ~hown in this Photograph (VERT: 2.4V/Oiv, HORIZ: 20 nS/Oiv) Figure 5 Some further tests were conducted to see how the 0469 with two or more outputs connec~ed in parallel compared to the DS0026 with both of its outputs connected in parallel. 6-172 v+ MOTOR WINDING I-- --J The 50 nS Difference in Propagation Delay Between the DS0026 and the 0469 is Clearly Seen in this Photograph (VERT: 2.4V/Div, HORIZ: 20 nS/Div) Figure 8 A Bipolar H-Bridge Motor Drive Circuit Using N- and P-Channel MOSFETs Figure 9 this because it is easier to compare switching waveforms when the oscilloscope traces are overlaid with one another. problem that is common to a number of applications other than motor drives. The problem is that the upper MOSFET switches which control the positive power supply to the load cannot have their gate-drive voltage referenced to ground. Summary In summarizing the results of this comparative analysis, we can say that the 0469 is really a OS0026 in a "CMOS disguise". Although the OS0026 was faster than the 0469 in both cases, its speed advantage was no more than about IOnS in any of the rise and fall time tests. As a 2-channel driver the 0469 is the obvious choice, especially when one considers its power consumption compared to the OS0026. In the test fixture shown in Figure 2, the OS0026 drew an average supply current of 30mA and thus consumed about 360 mW of power while the 0469 drew slightly more than 2 rnA and consumed about 25mW of power. Needless to say, the OS0026 ran quite hot to the touch while the 0469 was cold. The 50nS propagation delay of the OS469 should not pose any problem if all the MOSFETs in a particular circuit are driven by 0469s. When the P-channel MOSFETs are used as the upper switches, their source terminals are connected to the positive power rail. The gates of these MOSFETs are then driven 10 to 12 volts below the positive rail to turn them on. Because the gate drive is always referenced to the positive rail, the gates of the Nand P-channel MOSFETs in each half of the bridge can be driven directly by the 0469 if the power supply voltage is 14V or less. Operation at higher supply voltages, however, requires that the P-channel devices be isolated in some fashion from the 0469 that is ground referenced. The isolation problem crops up again ifN-channel MOSFETs are used as the upper switches in the bridge. Since their source terminals are connected to the load, one can see that the gate waveforms must swing to at least 10 or 12 volts above the positive rail if they are to turn on completely. Also, when either of the lower N-channel MOSFETs is conducting, the respective upper N-channel device must be off or cross-conduction will occur. 1b prevent this, the gate-to-source voltage of the upper MOSFET must be zero when the respective lower MOSFET is on and vice versa. This means that the gate-voltage of the upper N-channel devices must swing from the ROSe on) voltage drop of the lower MOSFETs all the way to 10 or 12 volts above the positive rail. Even with a 12 volt power supply, the gate voltage swing is almost 24 volts, and thus the 0469 cannot be used to directly drive the upper MOSFETs. Again, some form of driver isolation is required. Applications of the D469 Quad Driver The 0469 quad driver is well suited to applications such as OC motor control. Motors ranging In size from fractional up to several horsepower can be directly driven with power MOSFET devices, if they are provided with suitable gate drive. The 0469 fulfills the gate-drive requirements and provides the interface between the MOSFETs and lowpower CMOS or TTL control logic. Figure 9 shows a typical "H-bridge" motor drive circuit in which the winding current flow is bidirectional. N-channel MOSFETs are invariably used in the lower legs ofthe bridge since they can be directly driven by the 0469. In the upper legs of the bridge, both N- and P-channel devices can be used. In each case, driving the upper MOSFETs presents a 6·173 There are many methods of providing isolation between the D469 and the gates of the upper MOSFETs when using elevated supply voltages. As may be expected, certain methods will work better with N-channel MOSFETs, and others will work better with P-channel devices. c. ;8 >-r1I1~:[:)t--L___~=+=~-~-.J Three methods of providing gate-drive isolation will be considered. 'lWo of them provide DC isolation between the D469 and the gates of upper MOSFETs while the third provides isolation between a floating 0469 and the controllogic inputs. An H·Bridge Drive Using Capacitive Isolation for the P·Channel MOSFETs Figure 11 This method of isolation is even more compact and less expensive than that using transformers. Although a coupling capacitor several times the effective input capacitance of the P-channel MOSFETs is required, it is still small and inexpensive. This method does have the drawback of coupling noise spikes appearing at the MOSFET gates back to the outputs of the D469. Also capacitor isolation does not work well with N-channel MOSFETs in the upper half of the bridge. This is because the sources of the upper N-channel MOSFETs are not connected to an AC ground (such as the positive supply rail). Thus, there is no fixed reference for the AC coupled signal on the MOSFET side of the capacitor. An All N·Channel H·Brldge Drive Using Transformer Isolation Figure 10 a. 1ransformer Isolated Gate Drive Figure 10 shows an all N-channel H-bridge motor drive using transfo'rmer isolation between the D469 and the gates of both the upper and lower MOSFETs. Each transformer is driven by an AC waveform generated by two 0469 driver channels c. Floating 0469 With Opto-Isolated Logic Inputs Figure 12 shows a different method of providing isolation, namely referencing a D469 driver to the positive power rail and using an opto-coupler to provide the DC isolation between it and the low-voltage control logic. A -12V power supply, referenced to the positive rail, is generated for the D469's ground pin with a zener-diode, capacitor and resistor. The 0469 thus provides gate-drive waveforms to the P-channel MOSFETs that swing from the positive rail to 12 volts below it. If the reservoir capacitor C is made large enough, it will be able to supply enough charge to the D469 for transfer to the gates of the MOSFETs. This ensures that the upper MOSFETs will have fast switching times. In many cases the transformer will prove to be one of the most compact, least expensive and simplest methods of isolation to implement. It also works well with either N- or P-channel MOSFETs in the upper half of the bridge. However, there is a drawback with this method. The interwinding capacitance of the isolation transformers allow noise spikes appearing at the MOSFET gates to be coupled back to the D469 and cause possible damage. Care must be taken to ensure that any transients coupled back to the driver are of sufficiently low magnitude such that no damage is done. They can be minimized by the inclusion of a Faraday shield between the primary and secondary windings of the isolation transformer. Although this circuit is more complex than the previous ones, DC operation of the motor coils is provided if so required. Since the upper 0469 floats with respect to the positive power rail, any noise transients on this rail will not affect the operation of the driver or be coupled back to the logic inputs. This method has the disadvantage of being difficult to implement with an all N-channel bridge. The large voltage swing required at the gates of the upper Nchannel devices precludes the use of the circuit in this case. b. Capacitor Isolated Gate Drive A capacitor isolated N- and P-channel H-bridge motor drive is shown in Figure II. In this circuit, only the P-channel MOSFETs are isolated from the 0469; the N-channel devices are driven directly. The diodes are included to clamp positive gate-to-source transitions on the P-channel MOSFETs to +O.7v' 6-174 Yz DUAL OPTOCOUPLER ,.--'----., LED~ ~ED '\...~VEB + DRIV:;.1 ""\..; o C +12V R I NOTE: 0 IS A 12 VOLT ZENER A Different Method of Isolation: Floating a 0469 Driver and Optically Coupling the Logic Drive for the P-Channel MOSFETs Figure 12 In summarizing this look at motor drive circuits using the 0469 as a gate driver, one can see that if the correct methods of isolation are used then the 0469 certainly simplifies the task of interfacing logic circuitry to a DC motor. 1. Ed Oxner, Siliconix, inc., "Correlating the Charge Transfer Characteristics of Power MOSFETs with Switching Speed". Proceedings of Powercon 9, H-4 pages 1 to 5, 1982. 2. Rudy Severns, INTERNATIONAL RECTIFIER, Inc., "Simplified HEXFET Power Dissipation and Junction Temperature Calculation Speeds Heatsink Design". IR HEXFET Catalog, 1980. Pages A-80 to A-86. 3. Siliconix, inc., D469 Data Sheet, May 1983. 4. NATIONAL SEMICONDUCTOR CORP. DS0026 Interface Data Book 1980, Pages 6-10 to 6-16. mil I 6-175 6.13.3 14 Volt, 4 Amp Battery Charger/Power Supply Very low drive power makes MOSPOWER FETs more desirable than bipolar transistors in this simple, rninimum-parts-count battery charger. A low-power operational amplifier is used to control the VN64GA. A power bipolar transistor in the same circuit would require over 100 rnA of base current and a much more complicated drive circuit thus reducing overall efficiency and increasing circuit complexity. across the load. The response time is very fast, being determined by the op-amp. The 2N4400 current limiter circuit prevents the output current from exceeding 4.5 A. However, maintaining a shorted condition for more than a second will cause the VN64GA to exceed its temperature ratings. A generous heat sink, on the order of l"C/W, must be used. Operational amplifier A I directly drives the VN64GA with the error signal to control the output voltage. Peak rectifier Dl, Cl supplies error amplifier Al and the reference zener. This extra drive voltage is necessary because the MOSFET gate voltage must exceed its source voltage by several volts for the VN64GA to pass full load Cl'rrent. " The output voltage is pUlsating DC which is quite satisfactory for battery charging. To convert the system to a regulated DC supply, capacitor C2 is increased and another electrolytic capacitor is added 6·176 . 6.13.4 400 Volt, 60 Watt Push-Pull Power Supply An increase in DC!DC-converter efficiency is achieved by using MOSPOWER FETs in the power stage. Because the FET's drive requirements are low, a standard switching-regulator IC can provide both control and drive functions. pensation handled by C2. Diodes D1 and D2 provide isolation and steering for the 33 V zener transient clamp, D3. Output regulation is typically 1.25% from no-load to the full 60 W design rating. Regulation is essentially determined by the TL494. Output noise and ripple consists mainly of positive and negative 0.8 V spikes occurring when the output stage switches. The design shown delivers a regulated 400 V, 60 W output. The TL494 switching regulator governs the operating frequency and regulates output voltage. R1 and C I determine switching frequency, which is approximately 0.5 RC - 100 kHz for the values shown. The TL494 directly drives the FET's gates with a voltage-controlled, pulse-width-modulated signal. Each FET requires only 10 mW; the remaining drive power is dissipated by the turn-off resistors, R2 and R3. Operating in a push-pull configuration, the FETs switch primary current on in about 150 ns and then off in 300 ns. These short switching times - about a tenth of equivalent bipolar devices - and the resulting high operating frequency permit using physically small reactive components. NOTES UNLESS OTHERWISE NOTED, ALL RESISTORS 5%, V4W After full-wave rectification, the output waveform is filtered by a choke-input arrangement. The 1 ILH, 75 ILF filter accomplishes the job nicely at 100 kHz. A feedback scheme using R4, R5 and R6 provides for output-voltage regulation adjustment, with loop com- ALL CAPACITOR VALUES IN MICROFARADS, 25V 01 & Q2" VN64GA ON HEAT SINK D1 & 02 1 N4934 03 33V, 3W ZENER T1 PAl 12T, CT, NO 18 AWG SEC 215T, NO 24 AWG CORE INO GEN 8231·1 6-177 6.13.5 Self Oscillating Flyback Converter +3TO+1SV A low-power converter suitable for deriving a higher voltage from a main system rail in an on-board application is shown below. It uses the core characteristics to determine frequency. With the transformer shown, operating frequency is 250 kHz. Diode D1 prevents negative spikes from occurring at the MOSPET gate, the 100 n resistor is a parasitic suppressor, and Zl serves as a dissipative voltage regulator for the output and also clips the drain voltage to a level below the rated power PET breakdown voltage. ~I D2 ° 0.1 J.lf oLE:: 1 D, 1N4148 TRANSFORMER INDIANA GENERAL CORE F620·12·Q2 26 TURNS NO 28 WIRE TAIFILAR WOUND 6-178 6.13.6 Positive Input/Negative Output Charge Pump +7 TO +18 V A charge pump is a simple means of generating a low-power voltage supply of opposite polarity from the main supply. The 74C14 IC is a self oscillating driver for the MOSFET power switch. It produces a pulse width of 6.511-s at a repetition frequency of 100 kHz. When the MOSFET device is off, capacitor C is charged to the positive supply. When the power MOSFET switches on, C delivers a negative voltage through the series diode to the output. The zener serves as a dissipative regulator. Because the MOSFET switches fast, operation at high frequencies allows the capacitors in the system to be smaIl. lN4148 1 5K ~1 15 K [! J~ 1 VN1 0KM rOOD' .F 6·179 -=- '::::8 +-1<1---...-_-0 -5 v OUTPUT -::-'N4'4B I 'O.F -=- 5V 6.13.7 20 Watt, Class A Audio Amplifier Linear transconductance characteristics and low drive power requirements make MOSPOWER ideal in low-distortion audio amplifiers. MOSFET transconductance becomes linear at higher operating currents. This is in direct contrast to bipolar transistors which exhibit gain that changes significantly with changes in collector current. The Class A amplifier shown delivers 20 watts into an eight ohm load using a single VN64GA driving a transformer coupled output stage. This circuit is similar to the audio output stage used in many inexpensive radios and phonographs. Distortion is less than 5 percent at 10 watts using very little feedback (3%) with the VN64GA biased at 3 amperes. ALL RESISTORS 1f4 WA.TT. UNLESS NOTED • TRIAD T..,67A 6-180 6.13.8 Astable Flip-Flop with Starter + A pair of non-zenered MOSPOWER transistors, a pair of LEDs and a simple RC circuit make an easy sequential flasher with almost unlimited sequencing time - from momentary to several seconds. The infinite input resistance of the MOSFET gate allows for very long sequencing times that are impossible when using bipolars. One precaution, though, don't wire your circuit using phenolic or printed circuit boards when you're looking for slow sequencing (they exhibit too much leakage!). 6·181 6.13.9 High Current Analog Switches currents up to 12.5 amperes. Two MOSPOWER devices are necessary to enable current control in both directions. This is not possible with a single device because of the drain-source diode which is inherent in the MOSFET. Input signal range for this switch is limited by the maximum allowable gate-source enhancement voltage of ± 30 volts. Since 12 volts enhancement is required for 12.5 amperes output, then ±18 volts is the maximum signal range. Higher voltage inputs begin to turn off the VN64GA at the positive signal peaks thus limiting the MOSFET to pass less current. Turn-on is accomplished by driving the gates high (+30 V) and turn-off by driving the gates low (- 30 V). Off isolation is enhanced by biasing the For analog switches, MOSPOWER FETs provide an ideal combination of characteristics without the usual trade-offs inherent in more conventional components. Bipolar transistors require base current that causes offsets in the switched analog signal. Triacs also produce an offset and can only be used to switch AC or interrupted DC signals. MOSPOWER FETs provide none of these disadvantages. In the on-state, MOS looks resistive thus providing no offset voltage and very low distortion. Either ground referenced or high-voltage isolated bidirectional analog switches can be configured with MOSFETs. Drive circuits are simple because drive power requirements are minimal. The very low onresistance of the VN64GA makes it an ideal choice for analog switch circuits. OPERATE FROM +15V 74C14 ANALOG INPUT ~ ~ Q Vj~JG~A____-.~ HI-ON LO-OFF TTL 1 RT. Cr DETERMINE OSCILLATOR FREQUENCY, f '" RrCr INPUT c,. T1 DEPEND ON OSCILLATOR FREQUENCV HI-ON LO-OFF lOOK ----_<> _+----_+----_ _ -30 V Ground Referenced Analog Switch Figure 1 T 1 -1.2 Bl FILAR WOUND High Voltage Isolated Switch Figure 2 The circuit above shows a ground referenced, bidirectional switch with a signal range of ±18 volts for 6·182 common source node at - 30 volts. This has the effect of shunting to ground any signal that feeds through the drain-source capacitance. oscillator is gated on or off from a CMOS compatible input signal controlling the input Schmitt trigger. The VN64GA's input capacitance acts as both filter and storage capacitor for the half-wave rectified oscillator control voltage. Turn-on time of the analog switch depends on the oscillator frequency and is typically 10 microseconds for a 1 MHz oscillator. Isolated gate drive is required to operate the analog switch over its full ± 60 volt operating range. One way to accomplish this is to use a transformer isolated drive in a DC-to-DC converter as shown in Figure 2. The transformer can supply high voltage isolation, thus allowing the analog switch to operate as a true isolated switch up to thousands of volts above ground. When the switch is on, JFET QI is biased off by the negative supply DI, CI and therefore has no effect on operation. When the oscillator is turned off, QI loses its bias and turns on, thus shorting the MOSFET gate to source for fl:'':t run-off. The oscillator, buffer and control functions are all performed by a single hex CMOS Schmitt trigger. The 6-183 6.13.10 Laser Diode Pulsers The VN64GA can switch 10 amperes in 10 to 20 ns when driven by a low impedance source. This extremely fast switching speed is excellent for driving high-current laser diodes and to modulate these diodes at very high frequencies. A typical 2 watt peak power laser diode requires a maximum 200 ns, 10 ampere pulse at a 0.1 % maximum duty cycle. +15 V 0-_---, 08 n NON·INDUCTIVE 1/2W ...-::;z",..- LASER DIODE RCA SG2002 REP RATE-50 KHz PULSE WIDTH-20 ns INPUT The Laser Diode Pulser is a simple drive circuit capable of driving the laser diode with 10 ampere, 20 ns pulses. For a 0.1 % duty cycle, the repetition rate will be 50 kHz. A complementary emitter-follower is used as a driver. Switching speed is determined by the fr of the bipolar transistors used and the impedance of the drive source. :::-r; ..rL. Laser Diode Pulser Figure 1 +lSV lN4148 01 aBU A faster driver circuit is shown in Figure 2. It can supply higher peak gate current to switch the VN64GA very quickly. T$s circuit uses a MOSPOWER totem-pole stage to drive the high power switch. loon ~ LASER DIODE RCA &02002 INPUT 200 KHz MA)( o 1% DUTY CYCLE The upper MOSFET is driven by a bootstrap circuit. Typical switching times for this circuit are about 10 ns for both turn-on and turn-off. 0-+'''''''......-«:: High-Speed Laser Diode Driver Figure 2 6-184 6.13.11 A One-MOSPOWER FET Analog Switch Using four diodes in an array as shown allows using only one MOSPOWER transistor for analog switching. Current flow is controlled keeping the sourcebase connection of the MOSFET towards the load [the importance of this is stressed in AN77 -2]. Be sure to use diodes capable of handling the load current and be sure to use a transistor whose breakdown voltage specification exceeds the peak analog voltage anticipated. A suitable heat sink cannot be overstressed in such applications. BIAS Operationally, by increasing the gate-to-source bias voltage the MOSFET turns on. For applications other than either full on or full off, care must be taken not to exceed the dissipation of the MOSPOWER transistor. -6-185 6.13.12 Stepping Motor Driver Stepping motors find wide use in disk drives and machine control. MOSPOWER transistors are ideal motor drivers because of their freedom from second breakdown. The circuit shows how simple a motor drive becomes when using them. Note that snubbing networks are not used because load line shaping is not necessary with MOSPOWER and the inductance of the motor is fairly low so that the inductive spike is small. The MOSFET gates are tied directly to the outputs of the CMOS control circuitry. The logic is arranged to sequence the motor in accordance with the needs of the application. CMOS CONTROL CIRCUITRY I--+---+-----'~ 6-186 6.13.13 Constant Speed Motor Controller v' DC motors enjoy wide usage in applications varying from electric trains to electric drills. In many applications a constant speed characteristic is desirable. This circuit uses MOSFETs and a single IC to achieve this speed control. One feature of this circuit is that no tachometer is required for monitoring the speed. Speed is determined by sampling the reverse EMF generated by the motor. Motor speed is controlled by pulse width modulation. Be sure only to use this circuit for DC supply rails because MOSFET devices can only block voltage in one direction. -- I 6·187 6.13.14 Voltage-to-Frequency Converter with Digital Line Driver In industrial instrumentation systems, it is sometimes advantageous to amplify and digitize the transducer outputs at the physical location of the transducers. The data can then be digitally transmitted to a central computer location or terminal. A precision amplifier with digitally-controlled gain is excellent for amplifying the transducer signals up to the ±1O V level. A voltage-to-frequency converter (VFC) can then be used to convert the amplifier output voltage to a pulse train of variable frequency. A VFC provides an output frequency proportional to the average value of the input voltage over some specified range. The output pulse train can be transmitted over a single twisted pair for long distances without degradation of the data. In addition, the signal commons can be readily isolated if desired by coupling the output pulse train through an electro-optical coupler or pulse transformer. Low-cost integrated VFC circuits are adequate for some applications, but are generally limited in output drive capability. Some also require numerous external components. The VFC circuit shown can provide good accuracy and can drive very long cables or low-impedance loads. NOTE. ALL RESISTORS ARE IN OHMS UNLESS OTHERWISE NOTED fo '" v" R1C,.6.V - 10< VI <0 Voltage-to-Frequency Converter To visualize the circuit operation, assume that the integrator output V2 is ramping positive in response to a negative input V 1. This circuit configuration requires that the input voltage be negative. The 0169 output (OUT) is negative and transistor Ql is OFF. Since OUT is approximately -14 V, the 6.2 V zener will be conducting and the input to the comparator will be determined by the R2 voltage divider. The voltage at IN, the 0169 input, will be half of the integrator output V2 minus half of the 6.2 V zener voltage. A two-channel FET switch driver, the Siliconix 0169, is used as a comparator. The 0169 comparison threshold is internally 1.2 V with VR connected to ground and the complementary outputs both swing ±14 V when connected as shown. The ±14 V complementary output drives two MOSPOWER transistors connected in a totem-pole configuration. The MOSFETs ON-resistance will be approximately 2 to 3 ohms with ±14 V of gate drive, so the output voltage Vo will swing between +5V and zero even with a low-impedance load. When the integrator voltage ramps positive up to +8.6 V, the voltage at the 0169 input will be +1.2 V and 6·188 .----,..--_-_- Y? 12 GTO "IRMSO" D=f [ 12. IRMS=D 13 X<=O? + I. Ib + 1~1112 3 J CASE 4 D=t CASES 55X<>Y 342 Five Cases of Periodic Waveforms and the Derivation of IRMS for Each One Figure 1 8·2 44' 45 GTO "IRMS6" 48+LBL "IRMS3" 47RAD 481 49 RCL 01 19 FS? 01 361 lAMS = {D['a2+ \Ib + I~ - ~ (1.+ 'lJ)2]fl2 D=f 42 SORT 43 RCLoo 50- 35 SORT GENERAL CASE 41/ 14 GTO "IRMSO" 15 SF INDX 16 "ENTER 11" 17 PROMPT 18 STO 00 20 GTO "IRMSI" 21 "ENTER D" 22 PROMPT 23 STOOl 24 FS? 02 25 GTO "IRMS2" 26 FS? 03 27 GTO "IRMS3" 28 "ENTER 12" 29 PROMPT 30 STO 02 31 GTO "IRMS4" 32+LBL "IRMSI" 33 RCLoo D=t 37 GTO "IRMS6" 38+LBL "IRMS2" 39 RCLOI 402 51 PI 52' 53 ENTER t 54 SIN' 56 COS 57 ' 58 PI 592 50' 61/ 62 RCL 01 632 641 65 + 73 RCL 02 74 ' 75 RCL 00 76 X,. 2 77+ 76 RCL 02 79Xt 2 80 + 81 RCL 01 82' 833 841 85 FS? 05 86 GTO "IRMS5" 87 SORT 88 GTO "IRMS6" 89+LBL "IRMS5" 90 RCLOO 91 RCL 02 92 + ' 93 X t 2 94 RCL 01 95X t2 96 ' 974 981 99 100 SORT 101+L8L "IRMS6" 66 SORT 102"IRMS~" 67 RCL 00 68 ' 69DEG 70 GTO "IRMS6" 71+LBL "IRMS4" 72 RCL 00 103 ARCL X 104 PROMPT 105 GTO "IRMSO" 106 END I A.2 HP-41CV Transient Thermal Impedance Program Introduction Program Use This program enables curves of normalized transient thermal impedance versus pulse width to be plotted for repetitive waveforms of various duty cycles. Input data for the program is taken from a graph of normalized transient thermal impedance versus pulse width for a single-shot (Le., zero duty cycle) waveform. This program requires SIZE on the HP-4ICV to be set to at least fIve. I. When executing the program from label ZTINT, the prompt "ENTER D" will appear in the display, and the program will stop. Entering a number between 0.0 and 1.0 into the X-register and pressing the R/S key will cause this value to be used as the duty cycle in the calculations. Theory Each point that the program calculates for a given duty cycle and pulse width requires three points from the zero duty-cycle curve to be entered as input data. The program calculates each point according to the equation (Reference I): ZJCN = D + (1- D) Z I + Z2 - Z3 2. After (I) above or when executing the program from label ZTRAN, the prompt "ENTER TAU" will appear in the display, and the program will stop. Entering the desired pulse width in seconds and pressing the R/S key will cause this value to be saved for use in calculations. (1) Where: = pulse width of repetitive waveform (TAU) T = period of repetitive waveform = duty cycle of waveform (= TIT) D tpw = pulse width scale on zero duty cycle graph ZJCN = normalized transient thermal impedance = ZJCN at D = 0 and tpw = T + T ZI Z2 = ZJCN at D = 0 and tpw = T Z3 = ZJCN at D = 0 and tpw = T 3. The program will now prompt for Zl, Z2, and Z3 in sequence. When the display shows "ENTER ZN, TPW = X.XXX E ± X", where "ZN" = Zl, Z2, or Z3 and "TPW" is shown in the AlphaENG 3 format, the program will stop. The point on the zero duty-cycle curve (Zl, Z2, or Z3) at the indicated pulse width (TPW) should be entered into the X-register and the RIS key pressed. This must be done three times. T Program Description and Listing 4. After Z3 has been entered and the R/S key pressed, the program will calculate and then display the normalized transient thermal impedance, ZJCN. The display will show "ZJCN = X.XXX E ± X", where the numerical value is in the AlphaENG 3 format and the program will stop. Pressing the R/S key again will cause the program to restart at label ZTRAN. This program is quite straightforward and has two entry points. The fIrst entry point allows the desired duty cycle to be set once and then retained for a series of calculations. The second entry point allows a whole curve to be generated, without having to reenter the duty cycle with each iteration through the program. 8-3 Program Listing 01+LBL "ZTINT" 02 ENG 3 03 "ENTER D" 04 PROMPT 05 STO 00 06+LBL "ZTRAN" 07 "ENTER TAU" 08 PROMPT 09 STO 01 10 RCL 00 111/X 121 13 + 14 RCL 01 15 16 "ENTER Z1" 17 AVIEW 18 PSE 19 "TPW =" * 20 ARCL X 21 PROMPT 22 STO 02 23 RCL 01 24 "ENTER Z2" 25 AVIEW 26 PSE 27 "TPW" 28 ARCL X 29 PROMPT 30 STO 03 31 RCL 01 32 RCL 00 331 34 "ENTER Z3" 35 AVIEW 36 PSE 37 "TPW =" 38ARCL X 39 PROMPT 40 STO 04 41 RCL 00 421 43 RCL 00 4445 RCL 02 46* 47 + 48 RCL 03 49 + 50 RCL 04 51 52 "ZJCN" 53 ARCL X 54 PROMPT 55 GTO "ZTRAN" 56 END Register Map Reference Ro R1 R2 R3 Phillips Application Note #68, April 1975, "SOAR-The Basis for Reliable Power Circuit Design," page 13. R4 = = = = = D T Z1 Z2 Z3 8-4 A.3 Table of Symbols (Preferred Usage) BVCEO BVCES BVDSS BJT Cds Cgd C gn+ Cgp Cgs Ciss Coss Cox C rss CMRR DMOS D/CMOS Echan Eg Eox go ID(off) Breakdown Voltage, collector-toemitter, base open Breakdown Voltage, collector-toemitter, base shorted Breakdown Voltage, drain-to-source, gate shorted Bipolar Junction Transistor Capacitance, drain-to-source Capacitance, gate-to-drain Capacitance, gate to n + diffusion Capacitance, gate to p - type body diffusion Capacitance, gate-to-source Capacitance, common-source input Capacitance, common-source output Gate oxide capacitance per unit area Capacitance, reverse transfer (same as Cgd) Common-Mode Rejection Ratio ID(on) IDS IDSS IDZ IGSS J k L LD L' M MTBF n p Double-diffused MOS CMOS logic integrated with DMOS monolithically Electric field, lateral (across channel) Energy, band-gap (of silicon = 1.12 eV) Electric field within the gate oxide layer Conductance, output Current, drain, gate potential below threshold Pc PD PL Q QSS RB RBSB 8-5 Current, drain-to-source, ON state Current, drain-to-source (same as ID) Current, drain, with gate shorted to source Current, drain, zero-temperature coefficient Current, gate (leakage), source tied to drain Current density Boltzmann's constant Drain-to-source separation (channel length) Intrinsic Debye length Effective channel length Carrier multiplication Mean Time Between Failure Electron concentration per unit volume Hole concentration per unit volume Conduction loss Conduction loss, reverse diode Power loss due to IDSS (enchancement mode only) Charge Fixed positive charge density per unit area at the silicon-silicon dioxide interface Resistance, body Reverse Bias Second Breakdown - ... RCHAN RDD(on) IDS(on) RL RSja RSjc RScs RSsa Rp r(t) SOA t T TAorTa TC td(off) td ortd(on) tf Tj Tox tp tr trr v VB VBE VDMOS Resistance, conducting channel Resistance, drain-to-drain (bilateral switch) Resistance, ON, drain-to-source Resistance, load Resistance, thermal, junction-toambient Resistance, thermal, junction-to-case Resistance, thermal, case-to-sink Resistance, thermal, sink-to-ambient Resistance, p diffusion Transient thermal impedance, normalized Safe Operating Area Transit time Temperature Temperature, ambient Temperature, case Thrn OFF delay time Thrn ON delay time Thrn OFF fall time Temperature, junction Thickness of the insulating gate oxide Pulse width of power pulse Turn ON rise time Turn OFF time, reverse recovery (diode) Velocity, drift Voltage, breakdown, junction Voltage, base-emitter Vertical DMOS VDS(sat) orVSAT VGS VGS(on) VMOS Vo Vox VR VTor Vth VVMOS W Wd Voltage, saturated, drain-to-source Voltage, gate-to-source Voltage, gate-to-source, greater than VT Vertical MOS (DMOS) Voltage, contact (potential) Voltage across oxide layer Voltage, reverse, applied Voltage, threshold [also Vgs(th)J Vertical V-groove MOS Channel width Depletion width in epi layer Greek Symbols J3 EOX EO Current gain of a bipolar transistor (dldd1b) Dielectric constant of the oxide insulating layer Permittivity of free space (8.86xlO- 14) F/cm) fL fLn fLp p O'c 'T Tt TS c!> c!>F c!>B 8-6 Mobility, electron Mobility of electrons in n region Mobility of holes in p region Space charge density per unit volume Conductivity Relaxation time Time, transit Time, storage Electrostatic potential Fermi potential Potential, diode (for silicon 0.7 V) A.4 Glossary of Terms Acceptor. Also known as a "p-type" dopant. An element containing three electrons in its outer shell. Combined with silicon ( a semiconductor), it produces a region deficient in conduction electrons leaving holes available for conduction. Elements commonly used as acceptor dopants include boron and aluminum. In the periodic table they are classified as Group or Column III-A. an electric field. This electric field can result either from an externally applied electric charge, viz., a voltage, or it may simply be that field resulting from the close proximity of a chemically doped region that, of itself, contains a charge, either positive (p-doped) or negative (n-doped). Diffusion. The motion of particles away from regions of high concentration. In semiconductors, this process is used to obtain a dopant profile that is graded through the semiconductor material with the heaviest concentration being at the surface. Allotrope. The existence of two or more crystalline structural forms of an element. Anisotropic etch. Exhibits etching properties dependent upon the crystal orientation. This was commonly used in the original V-groove power MOS technology. Now it is generally obsolete for DMOS technology. (See Double-Diffused.) Donor. The "mirror image" of Acceptor above. Popular donor dopant elements include phosphorous, arsenic and antimony. These are classified within the periodic table as Group or Column V-A. Bilateral. The ability to pass an electric current in either of two directions with equal, or near-equal, affinity. Dopant. An element that, when diffused into a semiconductor, alters the conductivity of the semiconductor by contributing either a hole or a conduction electron. For silicon (a Group IV material), the dopants are found within either Group IlIA (p-dopant) or Group V-A (n-dopant). BJT. Bipolar Junction Transistor. Breakdown. Phenomenon by which, increasing the reverse bias voltage applied to a pn junction, causes it to go from a high resistance to a lower resistance region, with a corresponding increase on the reverse current. Double-diffused. Two superimposed diffusions using a single mask separated by time and temperature. _ ' Commonly used in the fabrication of power MOSFETs where the first diffusion becomes the body, and the second (or last) diffusion creates the source. • Carriers. Moving charges within a semiconductor, either conduction electrons or holes. Enhancement. In a normally-OFF MOSFET, the collection of carriers under the gate oxide until majority-carrier conduction occurs. Depletion layer. The region of a semiconductor device where essentially all charge carriers are swept out by 8-7 Epitaxial. The growth of a single crystal semiconductor film upon a single-crystal substrate. The epitaxial layer can have a vastly different dopant concentration from the substrate. Majority carriers. Charge carriers constituting more than one half the total charge-carrier concentration. Latch-up. In CMOS circuits and other semiconductors having four layers of alternating conductivity type, a current flow phenomenon where, during an abnormal conduction period, a parasitic thyristor action takes over and normal control is lost. Burnout generally results if drastic action is not taken quickly. Hole. Electron vacancy in the structure of a semiconductor which acts like a positive electronic charge. Intrinsic. A pure, undoped semiconductor crystal. Impurities. Atoms of a different chemical element which are foreign to the perfect crystal structure. Minority-carriers. The non-predominant mobile charge carriers in a semiconductor. For example, the injected base current in a bipolar transistor. Inversion. An electric field-induced phenomenon whereby a doped semiconductor surface changes its predominant charge characteristic. For example, a type p substrate is inverted to type n. Photolithography. A technique using light and selective masking to transfer a pattern to a surface. Polycrystalline. A material composed of many small crystals with random orientations. Ion-implantation. A procedure for doping a semiconductor by bombarding the surface with high-energy dopant ions. Known for its precise control. Secondary breakdown. In contrast to avalanche or first breakdown, generally results in irreversible damage to the transistor. It is the primary cause of failure in bipolar transistors when used to turn OFF an inductive load. Although several theories have been advanced, the mechanism has never been fully understood. Junction. Area of transition between semiconductor regions of different electrical characteristics. Latch-back. In MOSPOWER transistors, a breakdown voltage phenomenon resulting from the sudden interaction of a parasitic element (usually taking the form of a bipolar transistor) whose characteristic breakdown voltage is lower than that of its host. Thermal resistance. The temperature rise per unit power dissipation of a junction with respect to the temperature of an external reference point under conditions of thermal equilibrium. 8-8 I A.5 Additional References Adler, M.S. "A Comparison Between BiMOS Device Types," PESC' 82 Record, IEEE Power Electronics Specialists Conference, pp. 371-377. Baliga, B. Jayant and John P. Walden. "Improving the Reverse Recovery of Power MOSFET Integral Diodes by Electron Irradiation," Solid-State Electronics, 26, No. 12 (December 1983), pp. 1133-1141. Adler, M.S., et al. "Theory and Breakdown Voltage for Planar Devices with a Single Field Limiting Ring," IEEE Transactions on Electron Devices, Vol. ED-24 (1977), p. 107. Barlage, F. Michael. "Exploit VMOS FET's Advantage to Drive Bipolar Power Transistors," EDN, November 5, 1978, pp. 9398. Adler, M.S., and S.R. Westbrook. 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"Ideal FET Doping Profile," IEEE Transactions on Electron Devices, 30, No.6 (June 1983), pp. 619625. 8-15 A.6 MOSPOWER Selector Guide N-Chonnel MOSPOWER Device ~ TO·3 Breakdown Voltage (Volts) rD~~n) (0 s) Continuous (Amps) 10 Power Dissipation (Watts) Part Number 650 650 650 650 600 600 600 600 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 450 450 450 450 450 450 450 450 450 450 450 450 450 450 450 450 450 400 400 400 400 400 400 400 400 400 400 400 400 400 400 400 400 400 400 400 350 350 350 350 350 0.550 0.750 1.500 2.000 0.550 0.750 1.500 2.000 0.300 Q.400 0.400 0.500 0.600 0.850 1.100 1.500 1.500 1.500 1.500 1.500 1.500 2.000 2.000 2.000 2.000 3.000 4.000 0.300 Q.400 0.500 0.500 0.850 1.100 1.500 1.500 1.500 1.500 1.500 2.000 2.000 2.000 2.000 3.000 4.000 0.200 0.300 0.300 0.400 0.400 0.550 0.800 1.000 1.000 1.000 1.000 1.000 1.000 1.000 1.500 1.500 1.500 1.800 2.500 0.200 0.300 0.400 0.400 0.550 11.700 9.300 5.700 5.000 11.700 9.300 5.700 5.000 20.000 13.000 12.000 12.000 9.600 8.000 7.000 6.500 6.500 4.500 4.500 4.500 4.500 4.200 4.000 4.000 4.000 2.500 2.000 20.000 13.000 11.000 12.000 8.000 7.000 6.500 6.500 4.500 4.500 4.500 4.000 4.000 4.000 4.000 2.500 2.000 25.000 15.000 14.000 13.000 10.500 10.000 8.000 8.000 8.000 6.000 6.000 5.500 5.900 5.500 5.000 5.000 4.500 3.000 2.500 25.000 15.000 13.000 12.000 10.000 176 150 125 125 176 150 125 125 250 150 150 150 125 125 125 175 75 75 100 100 175 78 100 75 100 40 40 250 150 150 150 125 125 175 75 100 100 175 75 100 75 175 40 40 250 150 150 150 125 125 125 175 75. 125 125 75 75 175 125 75 125 40 40 250 150 150 150 125 VNT013A VNT012A VNT008A VNT009A VNS013A VNS012A VNS008A VNS009A VNPOOSA IRF450 2N6770 IRF452 BUZ45 IRF440 IRF442 BUP71 IRF430 2N6762 BUP66 VN5001A VNP002A BUZ46 BUP67 IRF432 VN5002A IRF420 IRF422 VNN006A IRF451 2N6769 IRF453 IRF441 IRF443 BUP70 IRF431 BUP64 VN4501A VNN002A 2N6761 BUP65 IRF433 VN4502A IRF421 IRF423 VNM005A IRF350 2N6768 IRF352 BUZ64 IRF340 IRF342 BUP69 IRF330 BUP62 VN4000A 2N6760 BUZ63 VNM001A BUP63 IRF332 VN4001A IRF320 IRF322 VNL005A IRF351 IRF353 2N6767 IRF341 8·16 MOSPOWER Selector Guide (Cont'd) N-Channel MOSPOWER (Cent'd) Device ~ TO-3 Breakdown Voltage (Volts) rPo~M's~) 350 350 350 350 350 350 350 350 350 350 350 350 200 200 200 200 200 200 200 200 200 200 200 200 200 150 150 150 150 150 150 150 150 150 150 150 120 120 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 90 90 90 80 80 60 60 60 60 60 60 60 60 60 0.800 1.000 1.000 1.000 1.000 1.000 1.500 1.500 1.500 1.500 1.800 2.500 0.060 0.085 0.085 0.120 0.120 0.180 0.220 0.400 0.400 0.400 0.600 0.800 1.200 0.060 0.085 0.120 0.120 0.180 0.220 0.400 0.600 0.600 0.800 1.200 0.180 0.250 0.035 0.055 0.055 0.060 0.080 0.085 0.110 0.180 0.180 0.180 0.200 0.250 0.250 0.300 0.400 4.000 4.500 5.000 0.180 0.250 0.035 0.055 0.080 0.080 0.085 0.110 0.120 0.150 0.180 10 Continuous (Amps) 8.000 8.000 8.000 6.000 6.000 5.500 5.000 5.000 4.500 4.500 3.000 2.500 47.000 30.000 30.000 25.000 22.000 18.000 16.000 9.900 9.000 9.000 8.000 5.000 4.000 47.000 30.000 25.000 25.000 18.000 16.000 9.000 8.000 8.000 5.000 4.000 14.000 12.000 65.000 40.000 38.000 32.000 27.000 33.000 24.000 14.000 14.000 14.000 10.000 12.000 12.000 8.000 7.000 1.900 1.800 1.700 14.000 12.000 60.000 40.000 33.000 31.000 27.000 24.000 18.000 16.000 14.000 8-17 Power Dissipation (Watts) 125 175 75 125 125 175 125 75 75 125 40 40 250 150 150 150 125 125 125 78 75 75 75 40 40 250 150 150 150 125 125 75 75 75 40 40 75 100 250 150 150 125 125 150 125 75 100 75 78 75 100 40 40 25 25 25 100 100 250 150 150 150 125 125 100 100 75 Part Number IRF343 BUP68 IRF331 BUP60 VN3500A VNL001A BUP61 IRF333 2N6759 VN3501A IRF321 IRF323 VNJ004A 2N6766 IRF250 IRF252 BUZ36 IRF240 IRF242 BUZ35 2N6758 IRF230 IRF232 IRF220 IRF222 VNG004A IRF251 2N6765 IRF253 IRF241 IRF243 IRF231 2N6757 IRF233 IRF221 IRF223 VN1200A VN1201A VNE003A IRF150 2N6764 BUZ24 IRF140 IRF152 IRF142 IRF130 VN1000A 2N6756 BUZ23 IRF132 VN1001A IRF120 IRF122 2N6658 VN99AA VN90AA VN0800A VN0801A VNC003A IRF151 IRF153 2N6763 IRF141 IRF143 VN0600A VN0601A IRF131 MOSPOWER Selector Guide (Cont'd) N-Channel MOSPOWER (Cont'd) Device ~ TO-3 , TO-220 Breakdown Voltage (Volts) rD~M'n) (0 s) ID Continuous (Amps) Power Dissipation 60 60 60 60 60 60 60 40 40 35 35 0.250 0.250 0.300 0.400 0.400 3.000 3.S00 0.120 0.150 1.800 2.500 12.000 12.000 8.000 10.000 7.000 2.000 2.000 18.000 16.000 2.000 2.000 75 75 40 80 40 25 25 100 100 25 25 2N6755 IRF133 IRF121 VN64GA IRF123 2N6657 VN67AA VN0400A VN0401A 2N6656 VN35AA 650 650 600 600 500 500 500 500 500 500 500 SOO 500 500 450 450 450 450 450 450 450 450 400 400 400 400 400 400 400 400 400 400 400 400 350 350 350 350 350 350 350 3SO 350 350 240 200 200 200 200 200 200 200 200 200 1.500 2.000 1.500 2.000 0.850 1.100 1.500 1.500 2.000 2.000 2.000 3.000 3.000 4.000 0.850 1.100 1.500 1.500 2.000 2.000 3.000 4.000 0.5SO 0.800 1.000 1.000 1.000 1.500 1.500 1.800 1.800 2.500 3.600 5.000 0.550 0.800 1.000 1.000 1.500 1.500 1.800 2.500 3.600 5.000 6.000 0.180 0.220 0.400 0.400 0.600 0.800 1.200 1.500 2.400 6.000 5.000 5.700 5.000 8.000 7.000 4.500 4.500 4.000 4.000 4.000 2.500 2.400 2.000 8.000 7.000 4.500 4.500 4.000 4.000 2.500 2.000 10.000 8.000 6.000 5.500 5.500 5.000 4.500 3.000 3.000 2.500 1.500 1.300 10.000 8.000 6.000 5.500 5.000 4.500 3.000 2.500 1.500 1.300 1.400 18.000 16.000 9.500 9.000 8.000 5.000 4.000 2.500 2.000 125 125 125 125 125 125 75 75 75 75 75 40 40 40 125 125 75 75 75 75 40 40 125 125 75 75 75 75 75 40 40 40 20 20 125 125 75 75 75 75 40 40 20 20 20 125 125 75 75 75 40 40 20 20 VNT008D VNT009D VNSOOSD VNS009D IRF840 IRF842 IRF830 VN5001D BUZ42 IRF832 VN5002D IRF820 BUZ74 IRF822 IRF841 IRF843 IRF831 VN4501D IRF833 VN4502D IRF821 IRF823 IRF740 IRF742 VN4000D BUZ60 IRF730 VN4OO1D IRF732 BUZ76 IRF720 IRF722 IRF710 IRF712 IRF741 IRF743 VN3500D IRF731 VN3501D IRF733 IRF721 IRF723 IRF711 IRF713 VN2406D IRF640 IRF642 BUZ32 IRF630 IRF632 IRF620 IRF622 IRF610 IRF612 8-18 (Watts) Pari Number MOSPOWER Selector Guide (Cont'd) N-Channel MOSPOWER (Cont'd) Device TO-220 /~ ~.) TO-202 Breakdown Voltage (Volls) 170 150 150 150 150 150 150 150 150 120 120 120 100 100 100 100 100 100 100 100 100 100 100 100 80 80 80 80 80 60 60 60 60 60 60 60 60 60 60 60 60 50 50 40 40 40 40 40 30 80 80 80 60 60 40 40 rD~M>n) (0 s) 6.000 0.180 0.220 0.400 0.600 0.800 1.200 1.500 2.400 0.180 0.250 6.000 0.085 0.110 0.180 0.180 0.200 0.250 0.250 0.250 0.300 0.400 0.600 0.800 0.180 0.250 4.000 4.000 4.500 0.085 0.110 0.120 0.150 0.180 0.250 0.300 0.400 0.600 0.800 3.000 3.500 0.100 0.100 0.120 0.150 3.000 3.000 5.000 1.200 4.000 4.500 5.000 3.000 3.500 3.000 5.000 8-19 ID Conllnuous (Amps) 1.400 18.000 16.000 9.000 8.000 5.000 4.000 2.500 2.000 14.000 12.000 1.400 Power Dissipation (Watls) 20 125 125 75 75 40 40 20 20 45 75 20 27.000 24.000 14.000 14.000 12.000 12.000 12.000 9.000 8.000 7.000 2.500 2.000 14.000 12.000 1.700 1.700 1.600 27.000 24.000 18.000 16.000 14.000 12.000 8.000 7.000 2.500 2.000 1.900 1.800 19.300 12.000 18.000 16.000 1.900 1.900 1.500 2.500 125 125 75 75 75 75 75 40 40 40 20 20 75 75 20 20 20 125 125 75 75 75 75 40 40 20 20 20 20 75 40 75 75 20 20 20 20 1.500 1.400 1.300 1.700 1.600 1.600 1.300 15 15 15 15 15 15 15 Part Number VN1706D IRF641 IRF643 IRF631 IRF633 IRF621 IRF623 IRF611 IRF613 VN1200D VN1201D VN1206D IRF540 IRF542 IRF530 VN1000D BUZ20 IRF532 VN1001D BUZ72A IRF520 IRF522 IRF510 IRF512 VN0800D VN0801D BSR82 VN88AD VN89AD IRF541 IRF543 VN0600D VN0601D IRF531 IRF533 IRF521 IRF523 IRF511 IRF513 VN66AD VN67AD BUZ10 BUZ71 VN0400D VN0401D BSR80 VN46AD VN40AD VN0300D VN88AF VN89AF VN80AF VN66AF VN67AF VN46AF VN40AF l1li MOSPOWER Selector Guide (Cont'd) N-Channel MOSPOWER (Cont'd) Device T O~~ ~ TO-39 Breakdown Voltage (Volts) rPo~M's1) SO SO 5.000 5.000 0.200 0.200 500 500 500 500 500 500 450 450 450 450 450 450 400 400 400 400 400 400 400 400 400 350 350 350 350 350 350 350 350 350 240 200 200 200 200 200 200 200 200 200 170 150 150 150 150 150 150 150 150 150 150 120 120 100 100 100 100 1.500 1.500 2.000 3.000 3.000 4.000 1.500 1.500 2.000 3.000 3.000 4.000 1.000 1.000 1.500 1.800 1.800 2.500 3.S00 3.S00 5.000 1.000 1.000 1.500 1.800 1.800 2.500 3.600 3.600 5.000 6.000 2.500 2.500 2.230 1.600 1.500 1.400 2.500 2.500 2.230 1.S00 1.500 1.400 3.370 3.000 2.750 2.090 2.000 1.770 1.350 1.250 1.150 3.370 3.000 2.750 2.090 2.000 1.770 1.350 1.250 1.150 0.800 25 75 75 40 20 40 25 75 75 40 20 40 25 25 25 20 20 20 15 15 15 25 25 25 20 20 20 15 15 15 6.25 2NS802 IRFF430 IRFF432 IRFF420 2NS794 IRFF422 2N6801 IRFF431 IRFF433 IRFF421 2NS793 IRFF423 IRFF330 2N6800 IRFF332 IRFF320 2NS792 IRFF322 IRFF310 2NS78S IRFF312 IRFF331 2N6799 IRFF333 IRFF321 2NS791 IRFF323 IRFF311 2N6785 IRFF313 VN2406B 0.400 0.400 O.SOO 0.800 0.800 1.200 1.500 1.500 2.400 6.000 0.400 0.400 0.600 0.800 0.800 1.200 1.500 1.500 2.400 4.500 4.500 6.000 0.180 0.180 0.250 0.300 5.500 5.500 4.500 3.500 3.500 2.800 2.250 2.200 1.800 0.800 5.500 5.500 4.500 3.500 3.500 2.800 2.250 2.200 1.800 0.500 0.500 0.800 8.000 8.000 7.000 6.000 25 25 25 20 2N6798 IRFF230 IRFF232 2N6790 IRFF220 IRFF222 2N6784 IRFF210 IRFF212 VN1706B 2N6797 IRFF231 IRFF233 2N6789 IRFF221 IRFF223 2NS783 IRFF211 IRFF213 NOS100B NOS101B VN1206B 2N6796 IRFF130 IRFF132 2NS788 8·20 10 Continuous (Amps) Power Dissipation (WaHs) 0.315 0.315 20 20 15 15 15 6.25 25 25 25 20 20 20 15 15 15 15 15 6.25 25 25 25 20 Part Number VN10KE VN10LE MOSPOWER Selector Guide (Cont'd) N-Chonnel MOSPOWER (Cont'd) Device ~ TO-39 m TO-237 , TO-92 Breakdown Voltage (Volts) 100 100 100 100 100 100 100 90 90 90 BO 80 BO 60 60 60 60 60 60 60 60 60 60 60 60 60 35 35 30 240 240 240 170 170 170 170 120 120 120 80 BO 60 60 60 60 60 60 60 60 30 240 240 240 200 200 170 170 120 120 120 60 60 60 60 rD~M'n) (0 s) ID Continuous (Amps) 0.300 0.400 0.500 0.500 0.600 0.600 0.800 4.000 4.500 5.000 0.500 0.500 4.500 0.180 0.180 0.250 0.300 0.300 0.400 0.500 0.500 0.600 0.600 0.800 3.000 3.500 1.800 2.500 1.200 6.000 10.000 10.000 6.000 10.000 10.000 24.000 6.000 10.000 10.000 4.000 4.000 3.000 3.000 5.000 5.000 7.500 7.500 7.500 7.500 1.200 6.000 10.000 24.000 24.000 28.000 6.000 10.000 5.000 6.000 10.000 5.000 5.000 5.000 7.500 6.000 5.000 4.000 4.000 3.680 3.500 2.010 0.900 0.900 O.BOO 4.000 4.000 0.800 8.000 8.000 7.000 6.000 6.000 5.000 4.000 4.000 3.500 3.680 2.010 1.100 1.000 1.400 1.200 0.350 0.300 0.250 0.250 0.300 0.250 0.250 0.080 0.300 0.250 0.250 0.350 0.350 0.400 0.400 0.300 0.300 0.300 0.250 0.250 0.250 0.700 0.210 0.160 0.080 0.080 0.100 0.210 0.160 0.230 0.210 0.160 0.200 0.200 0.179 0.150 8-21 Power Dissipation (Watts) 20 20 15 15 15 15 15 75 6.25 6.25 15 15 15 25 25 25 20 20 20 15 15 15 15 15 6.25 6.25 6.25 6.25 6.25 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 Part Number IRFF120 IRFF122 VNE010B VNE011B IRFF110 2N6782 IRFF112 2N6661 VN99AB VN90AB VND010B VND011B NOS102B 2N6795 IRFF131 IRFF133 2N6787 IRFF121 IRFF123 VNC010B VNC011B 2N6781 IRFF111 IRFF113 2N6660 VN67AB 2N6659 VN35AB VN0300B VN2406M BSR76 VN2410M VN1706M BSR72 VN1710M VN1720M VN1206M BSR70 VN1210M BSR67 VN0808M BSR66 VN0606M VN10KM VN10LM BSR65 BSR64 VN2222KM VN2222LM VN0300M VN2406L VN2410L VN2420L VN2020L BS107 VN1706L VN1710L VP1008L VN1206L VN1210L VN0610L VN0610LL B$170 VN2222L l1li MOSPOWER Selector Guide (Cont'd) N-Channel MOSPOWER (Cont'd) Device r Breakdown Yoltage (Yolts) rro~.w.,) ID Continuous (Amps) Power Dissipation (Watts) Part Number 60 30 7.500 1.200 0.150 0.350 0.4 0.4 VN2222LL VN0300L 90 SO 4.500 3.500 5.500 1.000 0.400 0.460 0.225 0.850 1.3 1.3 1.3 1.3 VQ1006P VQ1004P VQ1000P VQ1001P 4.500 3.500 5.500 1.000 0.400 0.4S0 0.225 0.850 1.3 1.3 1.3 1.3 VQ100SJ VQ1004J VQ1000J VQ1001J TO-92 ~ 60 30 14-Pln Dual-In-Une (Side Brazed) ~ 90 60 60 30 14-Pln Dual-In-Llne (Plastic) 8-22 MOSPOWER Selector Guide (Cont'd) P-Channel MOSPOWER Device fft Power Dissipation (Watts) Breakdown Voltage (Volts) ro~~n) (0 s) 10 Continuous (Amps) -100 5.0 -0.90 6.25 VP1008B -80 5.0 -0.9 6.25 VP0808B -30 2.5 -1.3 6.25 VP0300B -100 5.0 -0.37 1.0 VP1008M -80 5.0 -0.37 1.0 VP0808M -40 2.5 -0.48 1.0 VP0300M -30 2.5 -0.48 1.0 B5R78 VP0808L Part Number TO-39 m II TO-237 I I t~ ~ T~r ~ 14-Pln Dual-In-Llne (Side Brazed) ~ 14-Pin Dual-In-Line (Plastic) -80 5.0 -0.23 0.4 -45 14.0 -0.107 0.4 B5250 -30 2.5 -0.30 0.4 VP0300L -90 5.0 -0.4 1.3 VQ2006P -60 5.0 -0.4 1.3 VQ2004P -40 2.0 -0.6 1.3 VQ2001P -90 5.0 -0.4 1.3 VQ200SJ -60 5.0 -0.4 1.3 VQ2004J -40 2.0 -0.6 1.3 VQ2001J Power Dissipation (WaUl) Part Number 1.3 VQ3OO1P 1.75 VQ7254P N- and P-Channel Quad MOSPOWER Device Breakdown Voltage (Volts) rD~~n) (0 s) ~ 30 3.0·· 20 3.0·· ~ 30 3.0·· 20 3.0·· 10 Continuous (Amps) N-o.85 P-O.60 N-2.0 P-2.0 14-Pln Oual-In-Llne (Side Brazed) 11:1 N-0.85 P-o.60 N-2.0 P-2.0 14-Pin Dual-In-Line (Plastic) • ·Total (N + P) 8-23 1.3 VQ3001J 1.75 VQ7254J H Siliconix A.7 Worldwide Sales Offices United States International Central EUROPEAN Siliconix Incorporated 1327 Butterfield Rd., Suite 616 Downers Grove, IL 60515 (312) 960-0106 Twx: 910-695-3232 FRANCE Siliconix S.A.R.L. Centre Commercial de L'Echat Place de l'Europe 94019 Cnlleil Cedex Tel: (1) 377.07.87 Tlx: Siliconx 230389F Siliconix Incorporated Two King James South, Suite 143 24650 Center Ridge Road Westlake, OH 44145 (216) 835-4470 Twx: 810-427-9258 WEST GERMANY Siliconix GmbH Johannesstrasse 27 0-7024 Filderstadt-1 Postfach 1340 Tel: (0711) 702066 Tlx: 7-255 533 Siliconix Incorporated 3310 Keller Springs Road Suite 110A Carrollton, TX 75006 (214) 385-4046/4047 Twx: 910-860-9262 Siliconix GmbH Kirchfeldstr. 4 0-8025 Unterhaching Munich Tel: 089-611-4091 Tlx: 528305 Eastern Siliconix Incorporated 31 Bailey Avenue Ridgefield, CT 06877 (203) 431-3535 Twx: 710-467-0660 UNITED KINGDOM Siliconix LId. 3 London Rd. Newbury, Berks RG13 1JL Tel: (0635) 30905 Tlx: 849357 Siliconix Incorporated 395 Totten Pond Road Waltham, MA 02154 (617) 890-7180 Twx: 710-324-1783 Siliconix Incorporated Cranes Roost Ottice Park 311 Whooping Loop Altamonte Springs, FL 32701 (305) 831-3644 Twx: 810-853-0320 FAR EAST HONG KONG Siliconix (H.K.) LTD. 5th Floor Liven House 61-63 King Yip Street Kwun Tong, Kowloon Tel: 3-427151 Tlx: 44449SILXHX Northwestern Siliconix Incorporated 2201 Laurelwood Road Santa Clara, CA 95054 (408) 988-8000 Twx: 910-338-0227 JAPAN Nippon Siliconix Incorporated 101 Daigo Tanaka Bldg. 4-4 Iidabashi 3-Chome Chiyoda Ku, Tokyo 102 Tel: (03) 264-7905 Tlx: 2322739 NSIXJ Siliconix Incorporated Denver, CO (303) 771-9068 Southwestern Siliconix Incorporated 17821 E. 17th Street Suite 240 Tustin, CA 92680 (714) 544-8378 (714) 544-7275 Twx: 910-595-2643 8·24 H Siliconix U.S. and Canadian Sales Representatives U.S. Sales Representatives ALABAMA Huntsville (35815) Rep Inc P.O Box 4889 11535 Gilleland Rd. (205) 881-9270 Twx' 810-776-2102 ARIZONA Tempe (85281) Quatra Associates, Inc 1801 S. Jen Tilly Lane SUite B-lO (602) 894-2808 TWX' 910-950-1153 CALIFORNIA San Diego (92126) OHM SPUN Electronics 9560 Black Mt Rd .. Suite 125 (619) 695-8102 Telex 821-267 COLORADO Denver SILICON IX (303) 771-9068 CONNECTICUT Cheshire (06410-0160) Scientific Components 1185 South Main Street (203) 272-2963 Twx' 710-455-2078 FLORIDA Altamonte Springs (32701) Semtronic Associates 657 Maitland Ave. (305) 831-8233 Twx' 810-854-0321 FI. Lauderdale (33309) Semtronic Associates 3471 Northwest 55th St (305) 731-2484 Clearwater (33515) Semtronlc Associates 300 S Duncan Ave , SUite 270 (813) 461-4675 GEORGIA Tucker (30084) Rep Inc. 1944 Cooledge Road (404) 938-4358 Twx' 810-766-0822 ILLINOIS Des Plaines (60018) Electron Marketing Corp 3158 Des Plaines Ave. SUite 135 (312) 298-2330 Twx' 910-233-0183 INDIANA Indianapolis (46240) Fayetteville (13066) Tn-Tech Electronics, Inc 6836 E Genesee Street (315) 446-2881 Twx 710-541-0604 Wilson Technical Sales, Inc POBox 40699 4021 W. 71st Street (317) 298-3345 Twx: 910-997-8120 Fishkill (12524) Tn-Tech ElectroniCs, Inc 14 Westview Dnve (914) 897-5611 IOWA Cedar Rapids (52403) E. Rochester (14445) Electromec Sales, Inc 1500 2nd Ave S.E SUite 205 (319) 362-6413 Twx' 910-525-1342 Tn-Tech Electronics, Inc. 300 Main Street (716) 385-6500 Twx. 510-253-6356 Melville (11747) KANSAS Wichita (67217) R.T Reid ASSOCiates 20 Broadhollow Rd (516) 351-8833 Twx 990-997-3030 Design Solutions Inc. 4502 Cherry (316) 529-0114 NORTH CAROLINA Raleigh (27607) MARYLAND Baltimore (21208) Pro Rep 107 Sudbrook Lane (301) 653-3600 Twx 710-862-0862 MASSACHUSETTS Tyngsborough (01879) MICHIGAN Brighton (48116) Dayton (45414) OKLAHOMA Tulsa (74133) MISSOURI Gladstone (64118) ElectroniCs Mktg Assoc 7917 S 72nd East Ave. (918) 492-0390 Design Solutions Inc 1502 N E 58th Street (816) 452-8871 OREGON Beaverton (97005) SI. louis (63144) Design Solutions 1243 Hanley Industnal Ct (314) 961-7170 Twx 910-968-8332 Blair Hirsh Co , Inc 9645 S W. Beaverton Hwy (503) 641-1875 TENNESSEE Jefferson City (37760) NEW JERSEY Teaneck (07666) Rep Inc POBox 728 113 So Branner Ave. (615) 475-4105/9012/9013 Twx 810-570-4203 R T. Reid Associates 705 Cedar Lane (201) 692-0200 Twx 710-990-5086 NEW YORK Endwell (13760) TEXAS Grapevine (76051) Tn-Tech ElectroniCs Inc. 3215 E. Main Street (607) 754-1094 Twx' 510-252-0891 ElectroniCs Marketing Assoc POBox 487 403 E Wall (817) 481-750217503 & (817) 488-6583/6584 Twx 910-890-8659 8-25 Blair Hirsh Co., Inc POBox 2250 19410 36th Avenue West SUite t06 (206) 774-8151 Twx 910-977-0131 WISCONSIN Wauwatosa (53226) CANADIAN SALES REPS Arthur H Baler Company 4940 Profit Way (513) 276-4128 Twx 810-459-1624 Electromec Sales Inc 101 W Burnsville Pkwy (612) 894-8200 Twx 910-576-0232 WASHINGTON lynnwood (98036) Charlotte (28212) Arthur H Baler Company 16 Alpha Park (216) 461-6161 Twx 810-427-9278 MINNESOTA Burnsville (55337) SILICON IX (303) 771-9068 Larsen ASSOCiates 10855 West Potter Road (414) 258-0529 Twx 910-262-3160 OHIO Cleveland (44143) A P Associates 225 E. Grand River Ave (313) 229-6550 Telex' 287310 (APAIUR) UTAH Denver Rep Inc 7330 Chapel HIli Road SUite 206A (919) 851-3007 Twx 810-726-2102 Rep Inc Independence Office Park 6407 Idlewild Rd ,Ste 226 (704) 563-5554 Twx 810-726-2102 Telex 821765 Comp Tech, Inc 1 Bndgevlew Circle (617) 649-3030 Twx' 710-347-6661 Houston (77099) Electronics Marketing Assoc POBox 42388 11450 Blssonnet, SUite 309 (713) 498-8120 Islington, Ontario (M9B 6E3) Pipe Thompson, Ltd 5468 Dundas St W., Ste 206 (416) 236-2355 Twx 610-492-4367 North Gower, Ontario Pipe Thompson, Ltd (613) 258-4067 H Siliconix - - - - - - - - - - - - - - - - - _ _ . . . . u.s. ALABAMA Huntsville (35803) Hamilton/Avnet, #23 4812 Commercial Drive (205) 837-7210 Twx: 810-726-2162 Huntsville (35805) Pioneer/Huntsville 4825 UniverSIty Square (205) 837-9300 Twx, 810-726-2197 ARIZONA Phoenix (85021) Wyle Laboratorles-EMG 8155 N. 24th Ave (602) 249-2232 Twx 910-951-4282 Tempe (85281) Hamllton/Avnet, #04 505 South Madison Dr (602) 231-5100 Twx: 910-950-0077 CALIFORNIA Anaheim (92807) Zeus West, Inc 1130 Hawk Circle (714) 632-6880 Twx: 910-591-1696 Canoga Park (91304) Marshall Industries 8015 Deering Ave (818) 999-5001 Twx: 910-494-4821 Chatsworth (91311) Hamilton/Avnet #48 9650 DeSoto Ave. (818) 700-6500 Twx' 910-321-3639 Chatsworth (91311) Avnet Electronics #71 20501 Plummer (213) 700-2600 Costa Mesa (92626) Avnet Electronics 350 McCormick Ave. (714) 754-6111 Twx' 910-595-1928 Costa Mesa (92626) Hamilton Electro Sales, #29 3170 Pullman Street (714) 641-4100 Twx: 910-595-2638 Culver City (90230) Hamilton Electro Sales, #01 10912 W. Washmgton Blvd (213) 558-2121 or (714) 522-8200 Twx 910-340-6364 EI Segundo (90245) Wyle Laboratorles-EMG 124 Maryland Street (213) 322-8100 Twx 910-348-7140 Irvine (92714) Marshall Industries 17321 Murphy Ave. (714) 660-0951 Irvine (92714) Wyle Laboratorles-EMG 17872 Cowan Ave (714) 863-9953 Twx 910-595-1572 Distributors Ontario (91764) Milford (06460) Hamllton/Avnet #49 3002 E 'G' Street (714) 989-8309 Twx 910-321-2806 Falcon Electronics 5 Higgms Drive (203) 878-5272 Twx 710-462-8407 Rancho Cordova (95670) Wallingford (06492) Wyle DistributIOn Group Sacramento DIvIsion 11151 Sun Center Dr (916) 638-5282 Marshall Industries 20 Sterling Dr Barnes Industrial Park (203) 265-3822 Twx 710-465-0747 Reseda (91335) Jan Devices 6925 Canby, Bldg 109 (213) 708-1100 FLORIDA Altamonte Springs (32701) Sacramento (95348) Pioneer Electronics 221 North Lake Blvd (305) 834-9090 Twx' 810-850-0177 Hamllton/Avnet #35 4103 Northgate Blvd (916) 920-3150 San Diego (92123) FI. Lauderdale (33309) Hamilton/Avnet, #02 4545 Vlewrldge Ave. (619) 571-7510 Twx 910-335-1216 Hamilton/Avnet, #17 6801 N.W. 15th Way (305) 971-2900 Twx. 510-956-3097 San Diego (92123) FI. Lauderdale (33309) Wyle Laboratories-EMG 9525 Chesapeake Drive (619) 565-9171 Twx' 910-335-1590 Pioneer Electronics 1500 N W 62nd SI. SUite 506 (305) 771-7520 Twx 510-955-9653 Santa Clara (95052) Wyle Distribution Group 3000 Bowers Avenue (408) 727-2500 Twx 910-379-6480 SI. Petersburg (33702) Hamllton/Avnet, #25 3197 Tech Dnve No. (813) 576-3930 Twx' 810-863-0374 Sunnyvale (94086) Bell Industries 1161 No. Falroaks Ave (408) 734-8570 Twx: 910-339-9378 Winter Park (32792) Hamilton/Avnet 6947 Umverslty Blvd (305) 628-3888 Sunnyvale (94086) Winter Park (32789) Hamllton/Avnet, #03 1175 Bordeaux Avenue (408) 743-3300 Twx. 910-339-9332 Mllgray Electronics 1850 Lee Avenue (305) 647-5747 GEORGIA Norcross (30092) Sunnyvale (94086) Marshall Industries 788 Palomar Ave (408) 732-1100 Twx. 910-339-9298 Hamllton/Avnet, #15 5825 Peachtree Corners E-D (404) 447-7500 Twx 810-766-0432 COLORADO Englewood (80111) Norcross (30093) Marshall Industries 4364B Shakelford Road (404) 923-5750 Twx 810-766-3969 Hamllton/Avnet, #06 8765 E Orchard Rd , SUite 708 (303) 740-1000 Twx 910-931-0510 ILLINOIS Bensenville (60106) Thornton (80241) Wyle DistributIOn Group 451 E 124th Avenue (303) 457-9953 Twx 910-936-0770 Hamllton/Avnet, #10 1130 Thorndale Ave (312) 860-7780 Twx 910-227-0060 Wheatridge (80033) Elk Grove Village (60007) GBL/Goold Electromcs 610 Bonme Lane (312) 593-3222 Bell Industries 8155 W 48th Avenue (303) 424-1985 Twx' 910-938-0393 Elk Grove Village (60007) Pioneer/Chicago 1551 Carmen Drive (312) 437-9680 Twx. 910-222-1834 CONNECTICUT Danbury (06810) Hamilton/Avnet, #21 Commerce Drive, Commerce Park (203) 797-2800 Twx 710-460-0594 INDIANA Carmel (46032) HamiltonlAvnet, #28 485 Gradle Drive (317) 844-9333 Twx. 810-260-3966 8-26 Indianapolis (46250) PIOneer/Indiana 6408 Castle place Drive (317) 849-7300 Twx' 810-260-1794 KANSAS Lenexa (66214) Marshall Industries 8321 Melrose Dr (913) 492-3121 Overland Park (66215) Hamilton/Avnet, #58 9219 Quivira Road (913) 888-8900 Twx 910-743-0005 MARYLAND Columbia (21045) Hamllton/Avnet, #12 6822 Oak Hall Lane (301) 995-3500 (MD) (301) 621-5410 (DC) Twx. 710-862-1861 Gaithersburg (20760) Pioneer/Washington 9100 Gaither Road (301) 921-0660 Twx 710-828-0545 Gaithersburg (20760) Marshall Industnes 16760 Oakmont Ave (301) 840-9450 Twx' 710-828-0223 MASSACHUSETTS Burlington (01803) Milgray Electronics 79 Terrace Hall Ave. (617) 272-6800 Twx: 510-225-3673 Burlington (01803) Marshall Industries 1 Wilshire Road (617) 272-8200 Twx: 710-332-6359 Woburn (01801) Hamilton/Avnel, #18 50 Tower Office Park (617) 935-9700 Twx 710-393-0382 MICHIGAN Grand Rapids (49508) Hamilton/Avnet, #67 2215 29th SI. S. E. A5 (616) 243-8805 Livonia (48150) Hamllton/Avnet, #66 32487 Schoolcraft (313) 522-4700 Twx' 810-242-8775 Livonia (48150) Pioneer/Michigan 13485 Stamford (313) 525-1800 Twx 810-242-3271 MINNESOTA Minneapolis (55435) Industrial Components 5229 Edma Industnal Blvd. (612) 831-2666 Twx 910-576-3153 Minnetonka (55343) Hamilton/Avnet, #63 10300 Bren Road, East (612) 932-0600 Twx: 910-576-2720 H Siliconix u.s. Minnetonka (55343) PioneerfTwm Cities t0203 Bren Road, East (6t 2) 935-5444 Twx 910-576-2738 MISSOURI Earth City (63045) Hamilton/Avnet, #05 13743 Shoreline Ct (314) 344-t200 Twx' 910-762-0606 51. Louis (63146) Franklm Electronics 11638 Page Service Dr. (314) 993-5333 NEW HAMPSHIRE Manchester (03103) Hamilton/Avnet 444 E. Industrial Park Dr (603) 881-7435 NEW JERSEY Cherry Hill (08003) Hamilton/Avnet, #14 One Keystone Avenue (609) 424-0100 Twx: 710-940-0262 Fairfield (07006) Hamilton/Avnet, #19 10 Industrial Road (201) 575-3390 Twx: 710-734-4388 Fairfield (07006) Marshall Industries 101 Fairfield Road (201) 882-0320 Twx: 710-989-7052 MI. Laurel (08057) Marshall Industries 102 Gaither Dr., Unit 2 (609) 234-9100 (NJ) (215) 627-1920 (PA) Twx. 710-941-1361 NEW MEXICO Albuquerque (87123) Bell Industries 11728 Linn N.E. (505) 292-2700 Twx: 910-989-0625 Albuquerque (87119) Hamiiton/Avnet, #22 2524 Baylor Drive S E (505) 765-1500 Twx. 910-989-0614 NEW YORK Buffalo (14202) Summit Inc. 916 Main Street (716) 884-3450 Twx: 710-522-1692 Commack (11720) Falcon Electronics 2171 Jericho Turnpike (516) 462-6350 East Syracuse (13057) Hamllton/Avnet, #08 1600 Corporate Circle (315) 437-2642 Twx. 710-541-1560 Distributors (Cont'd) Endwell (13760) Warrensville Heights (44128) Marshall Industries 10 Hooper Road (607) 754-1570 Twx' 510-252-0194 Hamllton/Avnet, #62 4588 Emery Industrial Pkwy (216) 831-3500 Twx: 810-427-9452 Farmingdale (11735) MIlgray ElectroniCs, Inc 77 Schmitt Blvd (516) 420-9800 Twx. 510-2250-3673 Westerville (43081) Hamiiton/Avnet #79 777 Brooks Edge Blvd (614) 882-7004 Hauppauge (11788) OKLAHOMA Tulsa (74129) Hamllton/Avnet #20 933 Motor Pkwy. (516) 231-9800 Quality Components 9934 E. 21st Street So (918) 664-8812 Hamiiton/Avnet Hauppauge (11787) Marshall Industries 275 Oser Avenue (516) 273-2424 Twx: 510-224-6109 OREGON Hillsboro (97123) Port Chester (10523) Zeus Components, Inc 100 Midland Ave (914) 937-7400 Twx: 710-567-1248 Wyle Laboratorles-EMG 5289 N.E. Elam Young Parkway Bldg. E-100 (503) 640-6000 Rochester (14623) Lake Oswego (97034) Hamllton/Avnet, #61 333 Metro Park (716) 475-9130 Twx: 510-253-5470 Hamllton/Avnet, #27 6024 S.W Jean Road Bldg C Suite 10 (503) 635-8836 Twx: 910-455-8179 Rochester (14623) Marshall Industries 1260 Scottsville Road (716) 235-7620 Twx: 510-253-5526 PENNSYLVANIA Horsham (19044) PIOneer ElectroniCs 261 Gibraltar Road (215) 674-4000 Twx' 510-665-6778 Westbury (11590) Hamllton/Avnet #39 1065 Old Country Rd (516) 997-6868 Pittsburg (15222) Hamilton/Avnet 2800 Liberty Ave (412) 281-4150 Woodbury (11797) Ploneer/Long Island 60 Crossways Park W. (516) 921-8700 Twx: 510-227-9869 Pittsburg (15238) PlOneer/Plttsburgh 259 Kappa Drive (412) 782-2300 Twx 710-795-3122 NORTH CAROLINA Charlotte (28210) Pioneer/NC 9801-A Southern Pine Blvd. (704) 527-8188 Twx: 810-620-0366 TEXAS Addison (75001) Quality Components 4257 Kellway Circle (214) 387-4949 Twx. 910-860-5459 Raleigh (27604) Hamiiton/Avnet, #24 3510 Spring Forrest Rd. (919) 878-0819 X210 Twx' 510-928-1836 Austin (78758) Hamllton/Avnet, #26 2401 Rutland Drive (512) 837-8911 Twx' 910-874-1319 OHIO Cleveland (44105) Pioneer/Cleveland 4800 E 131 st Street (2t 6) 587-3600 Twx' 810-422-2210 Wyle Distribution 2120-F W Braker Lane (512) 834-9957 Dayton (45459) Austin (78758) Austin (78758) Dallas (75234) Pioneer ElectroniCs 13710 Omega Rd. (214) 263-3168 Twx: 910-860-5563 Dallas (75240) Zeus Components 14001 Goldmark (214) 783-7010 Houston (77063) Hamilton/Avnet, #11 8750 Westpark (713) 975-3500 Twx: 910-881-5523 Irving (75062) Hamiiton/Avnet, #16 2111 W. Walnut HIli Lane (214) 659-4151 Twx' 910-860-5929 Richardson (75083) Wyle Distribution 1810 N Greenville Ave (214) 235-9953 Twx' 310-378-7663 Sugarland (77478) Quality Components 1005 Industrial Blvd At Bournewood (713) 491-2255 UTAH Salt Lake City (84119) Hamllton/Avnet, #09 1585 West 2100 South (801) 972-2800 Twx' 910-925-4018 Salt Lake City (84104) Wyle Laboratorles-EMG 1959 South 4130 West (801) 974-9953 WASHINGTON Bellevue (98005) Hamiiton/Avnet, #07 14212 N.E. 121st Street (206) 453-5844 Twx: 910-443-2469 Bellevue (98005) Wyle DlstribullOn Group 1750 132nd Avenue N E. (206) 453-8300 Twx' 910-443-2526 WISCONSIN Milwaukee (53214) Marsh Electronics, Inc. 1563 South 101 st Street (414) 475-6000 Twx 910-262-3321 New Berlin (53151) Hamllton/Avnet, #57 2975 Moorland Road (414) 784-4510 Twx: 910-262-1182 Hamilton/Avnet, #64 954 Senate Drive (513) 433-0610 Twx: 810-450-2531 PIOneer ElectroniCs 9901 Burnet Rd. (512) 835-4000 CHIP DISTRIBUTOR Dayton (45424) Austin (78758) Quality Components 2427 Rutland Drive (512) 835-0220 Twx' 910-874-1377 FLORIDA Orlando (32807) PlOneerlDayton 4433 Interpomt Blvd (513) 236-9900 Twx' 810-459-1622 Chip Supply, Inc. 1607 Forsyth Rd. (305) 275-3810 Twx' 810-850-0103 Orlando (32817) Chip Supply, Inc 7725 N. Orange Blossom (305) 298-7100 8-27 l1li H Siliconix - - - - - - - - - - - - - - - - - - - - . . . . . Canadian Distributors BRITISH COLUMBIA Burnaby (V5G 4J7) RAE Industnal Elec. Ltd. 3455 Gardner Court (604) 291-8866 Twx: 610-929-3065 Tlx 04-356533 ONTARIO Downsview (M3J 123) Future Electronics 82 81. Regis Crescent N. (416) 638-4771 Twx: 610-491-1470 Mississauga (L4V 1M5) ALBERTA Calgary (T2E 6Z2) Hamllton/Avnet, #59 6845 Redwood Dnve (416) 677-7432 Twx: 610-492-8867 Hamiiton/Avnet 2816 21st Street N.E. (403) 230-3586 Nepean (K2E 7L5) Hamllton/Avnet, #60 2110 Colonade Road (613) 226-1700 Twx: 0534971 QUEBEC Pointe Claire (H9R 4C7) Future Elec, 237 Humus Blvd. (514) 694-7710 Twx: 610-421-3251 81. Laurent (H48 1M2) Hamiiton/Avnet, #65 2670 Sabounn Street (514) 335-1000 Twx: 610-421-3731 Ottawa (K2C 3P2) Future Elec Baxter Centre 1050 Baxter Rd. (613) 820-8313 8-28 H Siliconix - - - - - - - - - - - - - - - - - - - - . . . . European Representatives/Distributors AUSTRIA Ing. Ernst Steiner Hummelgasse 14 A-1130 Vienna Tel: 0222/827474/0 Tlx' 135026 BELGIUM J. P. Lemaire SA. Av. Limburg Styrum 243 B-1810 Wemmel Tel: (02) 460-05-60 Tlx: 24610 DENMARK Ditz Schweitzer A.S. Vallensbaekvel 41, Postboks 5 DK-2600 Glostrup Tel: (02) 45-30-44 Tlx' 33257 FINLAND Instrumentarium Electronics P.O. Box 64 SF 02631 Espoo 63 Tel' (358)-0-5281 Tlx: 124426 HAVUL SF FRANCE Almex 48 Rue de L'Aubepme B P. 102 92164 Anthony Cedex Tel: (1) 666-21-12 Tlx' 250067 Alrodis 40 Rue Vilion 69008 Lyon Tel: (7) 800-87-12 Tlx: 380636 A. Baltzmger B.P.63 67042 Strasbou rg Cedex Tel: (88) 331852 Tlx. 870952F Composants S.A. Avenue Gustave Eiffel B.P.81 33605 Pessac Cedex Tel: (56) 36-4040 Tlx: 550696F Composants S.A. 55 Avenue Louis Breguet 31400 Toulouse Tel' (61) 20-82-38 Tlx: 530957 Composants S.A. 183 Route de Paris 86000 Poitiers Tel: (49) 88-60-50 Tlx: 591525 Composants S.A. 57 Rue ManOir de Servigne ZI, Route de LOrlent B.P. 3209 35013 Rennes Cedex Tel: (99) 54-01-53 Tlx: 740311 I.T.T. Multicomposant 38 Avenue Henn Barbusse 92220 Bagneux Tel: (1) 664-16-10 Tlx: 270763 Sanelec Electronlque 7 Rue de la Couture ZI, de la Pllatene 59700 Marcq-en-BaroeUlI Tel' (20) 98-92-13 Tlx' 160-143F SCAIB 80 Rue d'Arcueil 94523 Rungis Cedex Tel: (1) 687-23-13 Tlx: 204-674F Ultratronik GmbH Munchner Slrasse 6 8031 Seefeld Tel: (08152) 7090 Tlx: 05-26459 GREECE General ElectroniCs ltd 209 Thlvon Street Nlkala, Piraeus GR-184 54 Tel' (1) 4904934 Tlx: 212949 GELT GR ITALY Dott Ing. Giuseppe De Mico S.P.A 20060 Cassma de Pecchl (MI) Via Vittorio Veneto 8 Milano Tel' (02) 9520551 Tlx: 330869 GERMANY Dltronlc GmbH Julius-Hoelder Str. 42 7000 Stuttgart 70 Tel: (0711) 720010 Tlx: 7255638 EBV Elektronlk GmbH Oberweg 6 0-8025 Unterhaching Tel' 089-61105-1 Tlx. 524535 EBV Elektronlk GmbH Alexanderstrasse 42 7000 Stuttgart 1 Tel: (0711) 247481 Tlx' 722271 EBV Elektronik GmbH Ostrasse 129 4000 Dusseldorf Tel: (0211) 84846/7 Tlx: 8587267 EBV Elektronlk GmbH Klebitzrain 18 3006 Burgwedel 1/Hannover TeJ. (05139) 5038 Tlx. 923694 EBV Elektronlk GmbH Schenckstr 99 6000 Frankfurt M 90 Tel: 069/785037 Tlx: 413590 Ing. Buro Ramer Konig Konigsbergerstrasse 16A 1000 Berlin 45 TeJ. 030-772-8009 Tlx' 184-707 Ing. Buro K.H. Dreyer Albert Schweitzer-Ring 36 2000 Hamburg 70 Tel: (040) 669027 Tlx: 2164484 Ing. Buro K.H. Dreyer Flensburger Strasse 3 2380 Schleswig Tel: (04621) 24055 Tlx' 02-21334 NETHERLANDS Koning en Hartman Elektrotechmek BV Postbus 43220 2504 AE The Hague 30 Koperweil Tel: 070-211641 Tlx: 31528 NORWAY A.S. Kjell Bakke 0Jre Raellngsvei 20 P.O. Box 27 N-2001 Liliesstrilm Tel: (02) 83-02-20 Tlx: 19407 PORTUGAL Telectra S.A.R.l. Praceta Av Dr Mario Moutinho, Lote 1258 1400 lIsboa Tel: (11) 616221 Tlx: 12598 SPAIN Commercial Espanola de Componentes S.A. Arzoblspo Morcilio 24 Oficina 5 Madrid 28029 Tel: (1) 733-7054/55 Tlx' 47010 Redls Logar SA Lopez de Hoyos 78 DPDO, Madrid 28002 Tel: (1) 4113561 Tlx: 23967 Redis Logar SA Aragon 208-210 Barcelona 11 Tel: (3) 2549048 SWEDEN Komponentbolaget NAXAB Box 4115 S-171-04 Solna TeJ. 08-985140 Tlx: 17912 KOMP 8-29 SWITZERLAND Abalec A.G. Landstrasse 78 CH-8116 Wlirenlos Tel: 01-730-0455 Tlx' 59834 UNITED KINGDOM Abercorn Electronics ltd. Abercorn House, 3 Plttville SI. Edinburgh, Scotland EH15 2BZ Tel: 031-669-6479 Barlec.Richfield ltd. Foundry Road, Horsham West Sussex RH13 5PX Tel' 0403-51881 Tlx: 877222 Dage Eurosem ltd. Rabans Lane Aylesbury Bucks HP19 3RG Tel' 0296-32881 Tlx: 83518 Farnell Electromc Components ltd. Canal Rd Leeds LS12 2TU Tel' 0532-636311 Tlx' 55147 Hartech ltd. Forum House, Stirlmg Rd. Chichester P019 2EN West Sussex Tel' 0243-773511 Tlx: 86230 Macro-Marketing ltd. Burnham Lane Slough, Berks Tel: (06286) 4422 Tlx: 847945 Micro-Tek Mktg. ltd 4 Bellfleld Avenue Harrow Weald Middlesex HA36SX TeJ. 01-428-3265 Semiconductor SpeCialists (UK) Ltd. Carroll House 159 High Street West Drayton Middlesex UB7 7XB Tel' (08954) 45522146415 Tlx' 21958 YUGOSLAVIA Contact: Belram S.A. 83 Avenue des Mimosas 1150 Brussels, Belgium Tel: 734-33-321734-26-19 Tlx' 21790 -- H Siliconix Worldwide Sales Offices International Representatives/Distributors AUSTRALIA NSD (Australia) PTY, Ltd. 22 Michellan CI. Bayswater, Victoria 3153 P.O. Box 148 Tel: 729-8855 Tlx. AA35443 BRAZIL Cosele Comerclo e SeNiclos Electronicos Ltda. Rua da Consolacao, 867 01310 Sao Paulo Tel: 255-1733 Tlx: 1130869-CSEL-BR HONG KONG Atek Electronics Co. Ltd. Rm. 1302 Argyle Centre, Phase 1 688 Nathan Rd. Kowloon Tel: 3-916833/4 Twx: 37119 ATEK HX Century Electronic Products Co. Unit 11", ll1F., Century Centre 44-46 Hung To Rd. Kwun Tong Kowloon, Hong Kong Tel: 3-42010112 Tlx: 51226 CEPCO HX Cable: CENTURYEPC Gibb, Livingston & Co, Ltd. 53 Wong Chuk Hang Rd Sungib Industrial Centre Aberdeen, Hong Kong Tel: 5-558331 Tlx: HX73470 INDIA KOREA Zenith Electronics 541 Panchratna Mama Parmanand Marg Bombay 400004 Tel: 384214 Tlx 011-3152 Authorized U.S. Agent Fegu Electronics Inc. 2584 Wyandotte SI. Mtn. View, CA 94043 Tel: (415) 961-2380 Tlx: 345599 A-Mee Trading Co , Ltd. 155-12 Yumri-Dong Mapo-Ku Seoul Tel: 716-6883 Tlx' K28569 TBTRACO LATIN AMERICA ISRAEL Intectra Inc. 2629 Terminal Blvd. MI. View, CA 94043 Tel' (415) 967-8818 Tlx: 345545 Intectra MNTV Cable: INTECTRA INDONESIA Carter Semiconductor (M) SON Berhad Jalan Lapangan Terbang, Ipon Tel: 514-033 Tlx: MA44050 Telsys Ltd. 12 Kehilat Venetsia St Tel AVIv Tel' 69010 494891 Tlx: 032392 MALAYSIA Sinar Electrik Hayam Wuruk, Jakarta-Barat Tel" (021) 623243 Tlx: LlONGKINYAMCO JKT NEW ZEALAND S.T.C. (NZ) Ltd. 10 Margot Street Epsom, Auckland 3 Tel: 500-019 Tlx. NZ21888 JAPAN Teilin Advanced Products Corp 1-1 Uchlsaiwal-Cho.2-Chome Chiyoda-Ku, Tokyo, 100 Tel' (03) 506-4670 Tlx: J-23548 PHILIPPINES Alexan Commercial 812 Elcano Street Binando, Manila Tel: 405-952 Tlx' 27484 CEI PH SINGAPORE Carter Semiconductor (S) PTE Ltd. 400 Orchard Road Orchard Towers No 09-07 Singapore 0923 Tel. 235-6653 Tlx' 36443 CARSIN SOUTH AFRICA Electrolink (PTY) Ltd. P.O Box 1020 Capetown 8000 Tel: 215-350 Tlx' 572-7320 TAIWAN Don Business Corp. 6F, No. 33, Alley 24, Lane 251, Nanking East Road Sec. 5, Taipei Tel 766-4515, 760-7801-3 Tlx: 25641 DONBC Cable: "DONBC" TAIPEI THAILAND Choakchai Electronic Supplies 128/22 Thanon Atsadang Bangkok 2 Tel: 221-0432 Tlx: 84809 CESLP T-H Cable' SAHAPIPHAT VENEZUELA P. Benavides S.R.L. Avilanas a Rio Editlcio Rio Caribe, Local 9 Caracas Tel: 52-92-97 Tlx: 21801 PBTH Manufacturing Facilities TAIWAN Siliconix (Taiwan) Ltd. Nantze Export Processing Zone Kaohsiung Tel: 3615101-4 Tlx: 78571235 HONG KONG UNITED KINGDOM Siliconix (H.K.) Ltd. 5/6/7th Floors Liven House 61-63 King Yip Street Kwun Tong, Kowloon Tel: 3-427151 Tlx: 44449SILXHX Siliconix Ltd. Morriston, Swansea SA6 6NE Tel: (0792) 74681 Tlx: 48197 8-30 UNITED STATES 2201 Laurelwood Road Santa Clara, CA 95054 Tel: (408) 988-8000 Tlx: 910-338-0227 Index _ Index Bilateral MOSFET: applications for, 2-29 characteristics, 2-26 construction, 2-26 gate drive, 2-27 input capacitance, 2-27 spurious tum ON. 2-28 surge characteristics, 2-30 thermal ratings, 2-30 threshold voltage, 2-27 Bipolar transistor: (See also parasitic) distributed series of, 2-51 high frequency, 2-22 Bipolar-FET combinations, 6-126 Body: diffusion, 3-2 dopant, 2-22 -drain diode, 2-18, 2-53, 7-6 region, 2-20 Boltzmann constant, 2-55 Breakdown, 8-7 avalanche, 2-50 dielectric, 2-50 drain-to-source, 2-49 latched-back, 2-49 (See also Latch-back) punch-through, 2-50 reach-through, 2-50, 2-51 secondary, 8-8 voltage, 1-6 collector-emitter, 2-53 comparisons, BJT, MOSFET, 5-55 relationship with ON-resistance, 2-51 temperature dependence, 2-53 zener, 2-50 Bulk resistance, 2-71 AC switch (see Switch) Accelerated testing, 7-8 Acceptor, 8-7 Activation energies, 7-9 Allotrope, 2-22, 8-7 Amplifier, audio, 6-180 autobias, 6-97 direct-coupled, 6-105 input and driver circuits, 6-111 magnetic, 2-31 power, with error correction, 6-107 Analog Switch: (See also Switch) one-MOSPOWER FET, 6-185 high current, 6-182 Anisotropic etch, 2-21, 2-70, 8-7 Audio switching, 2-32 Autobias, 6-105 Avalanche, 2-54 (See also Breakdown) Base, 2-70 Battery charger, 6-176 Beta, 2-71 Biasing circuits, 5 -12 Bilateral, 8-7 Bipolar - FET combinations, 6-130 cascode configuration, 6-132 Darlington configuration, 6-130 FET-gated transistor configuration, 6-132 parallel configuration, 6-132 BJT, 2-4, 2-7,8-7 action of parasitic, 5-65 as charge controlled device, 2-4 current gain, 2-9 operation at very low temperature, 5-81 storage time, 2-10 9·1 - CAD, Compact, 2-70 to 2-72 Capacitance: intratenninal, 5-57 input, 3-10 interelectrode, 3-6 Miller (see Miller effect) oxide, 3-5 reverse transfer, 2-12 Capacitors, 6-141 Carrier: concentration, 2-55 velocity, 3-4, 5-80 Carriers, 8-7 ($ee also Majority carriers) minority, 5-70, 8-8Channel, 2-4, 2-70 depth,3-2 length, 3-2, 3-4 pinch-off, 2-2, 3-2 Width,3-5 Characteristics: charge transfer, 3-9, 6-170 DC of MOSFET, 2-60 MOSFET, output first quadrant, 5-89, 5-98 third quadrant, 5-89 to 5-91, 5-98 Charge: controlled devices, 2-4 coupled: devices, 2-11 transistor, 3-10 mobile, 2-6, 2-7 pump, 6-179 saturation, 5-59 transfer: characteristics, 3-9 parallel connection, 5-56 'resonant converter, 6-1 to 6-4 Clamping, 6-140 Closed-cell, 3-6 CMOS, 2-17, 6-90 Collector, 2-70 Combinational devices, bipolar-FET, 6-l30 Common-source, output stage, 5-13 Compact: CAD program, 2-70 to 2-72 Complementary MOSPOWER, 6-89, 6-125 drive requirements, 6-85 Component selection, 6-141 Constant transconductance region, 3-6 Conductance, output, 3-2 negative, 5-34 Conduction: characteristics, fast recovery diode, 5-88 losses, 4-7 reverse, 5-71, 5-89 Control charge current, 2-7 Controlling imbalance, 5-56 Converter: boost derived wavefonns, 5-74 buck-boost, 6-26 Cuk, 6-8, 6-25 flyback, 6-25, 6-178 Jensen, 2-31 push-pull, 6-42 Venturini, 2-29 voltage-to-frequency, 6-188 Crowbar, 5-88 Cryogenic temperature, MOSFET perfonnance at 5-76 Crystallographic planes, 2-22 Cuk converter, 6-8, 6-25 Current: balance during switching, 5-51 -controlled device, 2-4 density, 1-7 diode commutated, 5-67 displacement, 5-70 gain, 2-9 gate, 2-10 hogging, 2-70 imbalance: dynamic, 5-55 means of controlling, 5-56 inductive, free wheeling, 5-65 leakage, 2-1, 2-53, 2-55 drain-to-source, 4-7 regulator, 2-35, 6-145 sharing, 5-16, 5-43 dynamic, 5-55 parallel MOSFETs, 5-43 problems, controlling, 5-56 source, 2-2 voltage controlled, 2-11 spiking, 5-66 Darlington: base drive circuit, 6-135 pair, 2-41 Data sheet, 7-1 D/CMOS ICs, 2-43 development of, 2-44 directions for future development, 2-47 junction isolated, 2-45 self isolated, 2-44 similarities to other technologies, 2-46 status of, 2-46 Dead time, 5-88 Delay: times, 2-14 turn OFF, 2-16 9-2 Donor, 8-7 Dopant, 8-7 Doping concentration, 2-50, 2-52 Double-diffused structure, 2-19, 8-7 Double-diffusion, 1-5, 2-20 Drain: current, square low regIOn, 3-2 region, 2-20 -to-source capacity, 3·-12 Driver circuits, 6-115, 6-140, 6-152 gate, synchronous rectifier, 5-74 high speed, isolated, 5-6 opto-coupler isolated, 5-7 transformer isolated, 5-6 using discrete components, 5-5 using ICs, 5-3 Driver: for power FETs, 6-169 power CMOS, 6-90 signals, 6-161 Driving: considerations, 6-84 from CMOS, 6-85 from TTL, 6-86 dVidt, 5-57, 5-70 a cause of oscillation, 5-35 avoidance, 5-62, 5-75 Mode 1 (static) turn-ON, 5-58 Mode 2 tum-ON, 5-59 Mode 3 tum-ON, 5-59 Mode 4 turn-ON, 5-59 Depletion: layer, 8-7 -mode: JFET, 1-1, 1-4 Power MOSFET: applications, 2-35 fabrication, 2-39 ON-resistance, 2-34 power ratings, 2-33 threshold voltage, 2-34 region, 2-55, 3-2 Device: charge controlled, 2-4 charge coupled, 2-11 current controlled, 2-4 parameters, 7-2, 7-4 Dialer circuits, 6-93 di/dt, 5-16 Die, 2-55 Dielecttic, 2-50 Diffusion, 8-7 susceptance, 2-9 Diode: (See also Parasitic) anti-parallel, 5-65 body-drain, 2-53 snap characteristics, 5-61 characteristics, temp effects, 5-94 clamping, 5-64 (See also Diode, parasitic; Diode, body-drain) current limiting, 6-93 fast recovery rectifier, 5-87 inverse, 5-65 (See also Diode, clamping) junction at very low temperature, 5-81 parasitic, 5 -65 anomalous switching effects, 5-33 as a rectifier, 5 -89 circuit remedies, 5-67, 5-68 conduction current, 5-63 current ratings, 5-66 formation of, 5-65 problems of using, 5-65 reverse: conduction, 5-130 recovery, 5-203, 5-204, 5-221 turn OFF behavior, 5-41 voltage ratings, 5-65 Schottky, 5-67, 5-81, 5-95 energy bands, 5-96 voltage drop, 5-81 DMOS, 1-5, 2-18, 2-19 channel, 2-71 length, 2-22 latchback prevention, 2-53 planar, 2-70 structure, 2-22, 2-70 transistors, history, 2-43 Efficiency, synchronous rectifier, 5-79, 5-87 Electric field, 2-55 Electrical behavior at very low temp, 5-80 (See also Temperature) Electron mobility, 2-18, 2-22 Emitter, 2-70 EMP (electromagnetic pulse), 5-102 Energy, activation, 7-9 Enhancement, 8-7 -mode MOSFET, 1-1 effective voltage, 2-35 Epitaxial, 8-8 layer, 2-51 Epitaxy, 2-70 Equivalent circuit, Mode 3 dVidt, 5-60 (See also Model) Etch, anisotropic, 8-7 Etching, preferential, 2-22 Failure: mechanism, 7-9 rate, 7-9 calculations, 7-23 9-3 Fall time, 2-14 (See also Switching time) calculations, 2-16 characteristics, 2-15 switching model, 2-14 Fast recovery rectifiers, 5-87 Feedback capacitance, effects of gate drive on, 3-11 Ferrite beads, prevent oscillation, 5-29 FET (Field Effect Transistor), 1-1, 1-4,2-4, 2-5 as charge-controlled device, 2-4 planar, 1-4 power, 1-4 regulator, 6-4 small signal, 1-1 FETs in series, 5-65 Flasher, sequential, 6-181 Flip-Flop, astable, 6-181 Flyback converter, 6-178 Frequency response analysis, 6-151 IC (see D/CMOS ICs) IGR (Insulated Gate Rectifier), 2-41 IGT (Insulated Gate Transistor), 2-41 Impedance, generator, effects on tum ON, 5-57 Impurity, 8-8 carrier concentration, 3-2 Inductance: common source, 5-33 effective, 6-17 gate, 5-33 self, 6-26 Induction heating, 6-71 Inductive loads, 6-81 Injecting source perimeter, 1-7 Inrush loads, 6-82 Integrated: Circuits, at very low temp, 5-82 Magnetics, 6-25 Interelectrode capacitance (see Capacitance) Interface, IC logic to power loads, 6-81 Inversion, 8-8 Inverter, 6-59 bridge diode, 5-66 DC-to-sinusoidal, 6-179 RF,6-72 Ion: implantation, 8-8 trapping, 5-246 (See also Radiation, effects of) Ionizing radiation, effects of, 5-102 Irradiation scenarios, 5-101 (See also Radiation) Isolated gate drive, 2-27 capacitive, 2-28 oscillator frequency, 2-28 Gate: -channel capacitance, 2-5 -charge curve, 3-11 charge dynamic characteristics, 2-12 control, 1-2 current maintenance, ON, 2-12 current, reverse, 2-7 diffused-, 1-2 -discharge decay characteristics, 3-12 drive, 3-11 circuit, 5-56, 6-74, 6-140 high speed, 5-1 isolated, 2-27, 2-28 optically coupled, 2-28 source, 2-7 speed,5-56 input capacitor, 2-66 (See also Capacitance) metal, 2-21, 2-70 MOS: 2-19, 2-40 oxide capacitance, 3-2 resistance (see Resistance) resistor, to prevent oscillations, 5-56 rupture, 5-25, 5-58 threshold voltage, 5-56 width, 1-7 Geometry: efficiency compared, 5-70 optimized for synch rect., 5-70 Glossary of terms, 8-7 Guard banding, 7-7 Jensen converter, 2-31 JFET, 1-1, 1-7,2-33 -depletion mode, 1-1 Junction, 8-8 temperature, 3-3 maximum, 4-1 Laser pulsers, 6-184 Latch-back, 2-49, 8-8 breakdown voltage, 2-49, 2-53 cause and avoidance, 2-51 sustaining voltage, 2-52 Latch-up, 8-8 Layout efficiency, 1-7 LDMOS: advantages of, 2-23 disadvantages, 2-23 Half-bridge, 5-65 HEXFET,5-65 High Conductance MOSFET, 2-41 Hole, 8-8 9-4 Leakage: body-drain junction, 2-55 current, 2-1, 2-53, 2-55 temperature dependence, 2-53 inductances, 6-29 Lifetime, 2-8 Linear: amplifiers, 5-9 transfonner drive, 2-27 Load: inductive, 2-65 resistive, 2-60 Losses: conduction, 4-7 drain to source leakage current, 4-7 gate drive, 4-6 internal diode, 4-7 switching transition, 4-5 Low frequency model, 3-6 (See also Model) gated devices, 2-44 MOSFET: (See also LDMOS, VDMOS, etc.) advantages, temperature related, 2-70 as current source, 2-2 as rectifiers, 5 -89 bilateral, 2-26 (See also Bilateral MOSFET) breakdown, drain-to-source, 2-49 (See also Breakdown) channel pinch-off, 3-2 charge transfer characteristics, 2-11 to 2-13, 6-170 developing them, 2-14 DC characteristics, 2-60 depletion-mode, 2-33 drain current, calculating, 8-1 dynamic model, 2-60 enhancement mode, 1-1 gate control, 1-2 geometries, efficiency, 5-70 high conductance, 2-41 leakage, 2-49 current, 2-1 ohmic region, 2-60, 3-1 ON-resistance, 2-2 operation at very low temp, 5-76 output characteristics, 3-1 parallel: controlling oscillation, 5-29 operation, 5-15 pinch-off region, 2-60 power, 1-1, 1-4, 1-5 driving, 2-12 energy band, 5-97 linear operation, 3-1 losses, 4-4 saturation region, 3-1 simulation of, 2-56 small signal, 1-1, 2-17 source follower, 6-147 source resistance, 2-56 structures for synchronous rectifiers, 5-69 switching characteristics, 2-60 thennal analysis program, 4-17 thennal model, 4-1 threshold voltage, 3-1 vertical double-diffused, 1-3 voltage controlled: current source, 3-1 resistor, 3-1 MOSPOWER, 1-4, 1-7 complementary, 6-85 electrical characteristics, 7-1 quad driver for, 6-169 synchronous rectifiers, 5-70 transistor structure, 7-2 Motor: speed control, 6-187 Magnetic: amplifiers, 2-31 circuits, linear, 6-26 integration, 6-25 Magnetizing force, 6-26 Magnetomotive force, 6-26 Maintenance, ON gate current, 2-10 Majority carrier, 8-8 devices, 3-9 transistor, 1-1 Matching device parameters (parallel operation), 5-56 Mean lifetime, 2-8 Metalization, 2-71 source, 5-65 Miller: effect, 2-12, 2-13, 2-16, 3-10, 3-11, 5-1 capacitance, 3-11 Minority carriers, 8-8 Mobile charge, 2-5, 2-7 (See also Charge) Model,6-151 dynamic, 2-60 equivalent circuit, 5-60 high frequency, 2-70 low frequency, 3-6 oscillation of parallel devices, 5-48 schematic, 2-71 thennal, 5-43 to 5-47 (See also Thennal, model) Modeling, 2-56 magnetic circuit, 6-26, 6-28 small signal, 6-45 SPICE,5-33 MOS: gate, 2-19, 2-41 (See also Gate) 9·5 stepper, 6-156 accelerating, 6-164 interface, 6-165 servo, microstepping, stepper, 6-92 Mutual induction, 6-26 Pinch-off, 2-2 drain voltage, 1-2 region, 2-60 channel, 3-2, 3-4 Planar: DMOS, 2-74 PETs, 1-4 MOS, 2-17, 2-19 PMOS, 2-57 Poles, rhp, 5-51 (See also Routh-Hurwitz criterion) Polycrystalline, 8-8 silicon gate, 2-19 structure, self aligning, 2-19 Polysilicon gate, 3-6 Post regulation, 2-31 Power: conversion, 6-1 high frequency, 6-1 switching losses, 6-1 dissipation, total, 4-1 PET paralleling, 5-55 temperature effects, 5-55 MOS, 1-6 supply kit, 6-49 switches, 6-157 Preferential etching, 2-22 Pseudo threshold voltage, 3-4 Pulse dialer circuits, 6-89 Pulse-width modulation, 5-87, 6-9, 6-13 Pulser, laser diode, 6-184 Punch-through, 2-18, 2-20, 2-50 breakdown, 2-51 Push-pull power supply, 6-177 PWM f.;;ee Pulse-width modulation) Neutron irradiation, 5-104 NMOS, 2-57, 2-60 Nodal analysis, 2-72 Ohms-per-square, 2-71 Ohmic region of MOSPETs, 2-60 ON-resistance, 1-6,2-2,5-98, 3-12 as function of gate voltage & channel current, minimized, 5-221 of NOS 100, 2-34 relationship with breakdown voltage, 2-50 Optical drives, 2-28 Oscillation: ~ee also Parasitic oscillation) anomalous, causes of, 5-30, 5-33 conditions for, 5-29 common mode, 5-25 differential mode, 5-28, 5-52 frequency, 5-25, 5-31, 5-48 parallel connected, 5-49 parasitic, parallel devices, 5-56 prevention, 5-29 problems, recognize, 5-29 second order effects, 5-41 theory of, 5-34 Oxide: capacitance, 3-5 charge, 2-22 Qualification, 7-11, 7-12 Parallel operation, 5-15 current sharing, forced, 5-43 oscillation, 5-48 thermally coupled, 5-43 Paralleling, 5-55 concerns about, 5 -16 multiple devices, 4-2 reasons for, 5-15 Parameters, matching, 5-56 Parasitic: bipolar transistor, 2-70, 2-71 body-drain diode, 5-89 capacitances, 1-4,2-70 device, 2-53 elements, 2-3, 2-18, 2-66, 2-72 oscillation, 5-24, 5-48 identifying the oscillator, 5 -31 inducing it, 5-31 why some will not oscillate, 5-31 Phonon, 2-55 Photolithography, 2-20, 8-8 Radiation, 5-101 ~ee also Irradiation) damage, strategies to reduce, 5-105 effects on dV/dt, 5-62 ionizing, effects of, 5-102 testing, 5-107 . types of, 5-101 RAM,2-43 Ratings, absolute maximum, 7-1 ReT (resonant charge transfer) control, 6-3 Reach-through breakdown, 2-50, 2-51 ~ee also Breakdown) . Recombination, 2-8 Rectification: synchronous, 5-69, 5-92 gate drive circuits, 5-71 to 5-75 using MOSPETs, 5-69, 5-92 using Schottky diodes, 5-69 9-6 Rectifier: bridge, full wave, 5-87 synchronous, nand p channel, 5-91 insulated gate (IGR), 2-41 low voltage ~ee Rectifier, synchronous) synchronous, 5-69, 5-92 Recovery current in diodes, 5-69 Regulation, post-, 2-31 Regulator: FET low voltage, 6-5 voltage and current, 6-145 Reliability, 7-11, 7-16 report, 7-13 Resistivity, epitaxial layer, 2-51 Resistance: drain, differential of paralleled devices, 5-48 drain-source: as a function of temperature, 5-43 normalized and compared, 5-70 gate, 5-48, 5-56 ~ee also Gate resistor) for preventing oscillation, 5-33 temperature dependence of, 5-43 -ON: effects of: drain current on, 5-72 temperature on, 5-72 radiation upon, 5-105 normalized comparison, 5-70 vs. gate-drain voltage, 5-99 Resonant charge transfer, 6-1 Reversal, protection, 6-23 Reverse: characteristics, 5-98 gate current, 2-7 recovery, 5-88 speed, 5-66 time, 7-6 RF generators, 6-71 Ripple currents, 6-21 reduction, 6-9, 6-18 rise time, 2-14 Routh-Hurwitz, 5-33, 5-50 analysis, 5-35 RF: generator, 6-67 inverter, 6-68 SCR,2-41 Secondary breakdown, 2-70, 5-83, 8-8 Self-aligning, polycristalline structure, 2-19 Self-inductance, 6-26 Servo motor, 6-92 Silicon lattice, 2-55 Simulation: computer, 5-38 SPICE 2, 2-56 Slew voltage, drain-to-source, effects of dV/dt, 5-54, 5-202 ~ee also dV/dt) Small signal, 1-1 Snubber circuit, 6-141 SOA: at very low temperature, 5-83 curve, 4-13 how to create, 4-14 Source, 2-70 diffusion, 3-2 follower, 5-12 Space charge, 2-2 S-parameters, 2-72 SPICE,5-38 ~ee also Modeling, Simulation, computer) SPICE 2 Simulation, 2-56 to 2-69 Square law region, 3-4 Static induction transistor (SIT), 1-4 Stepping motor driver, 6-186 Storage time, 2-10, 2-41 minority-carrier, 5-88, 5-89 Stray inductance, 2-66 Subthreshold region, 2-12 Surface charge density, 3-3 Surge, protection, 6-5 Sustaining voltage, 2-49 Switch: AC,2-26 normally ON, 2-36 drivers, 6-158 FET, low voltage, 6-4 Switches, resistive, 3-1 Switch-Mode Power Supplies (SMPS), 2-9, 5-87,5-95,6-1 Switching: audio, 2-32 behavior, anomalous turn-OFF, 5-33, 5-41 characteristics, 3-9 converter, 6-59 efficiency, 2-61, 3-9 frequency, 2-28 losses, 3-9 regulator, 6-62 speed, 2-4, 2-52, 3-9 time, 5-98 calculations, 3-11 from charge transfer, 2-13 turn-OFF, 3-12 turn-ON delay, 3-10 Safe operating area, 4-1 Saturation: drain current, 1-2, 3-2 voltage drop, 2-10 Scattering, electron phonon-assisted, 2-55 Schottky diode, 5-95 at very low temperatures, 5-81 ~ee also Diode) MOSFET comparison, synch. rect., 5-95 9-7 - Symbols, table of, 8-5 Symmetry, plane of, parallel devices, 5-49 Synchronous rectifiers, 5-87, 5-95 bridge, 5-91 full-wave, 5-92 power loss compared in Schottky, MOSPOWER,5-78 drive, 2-27 volt-second balance, 2-27 Transient: output reversal, 6-15 suppressors, 5-67 Transistor, 1-1 field effect ~ee PET) parasitic, interactions causing oscillation, 5 -35 power definition, 1-3 static induction, 1-4 Transit time, 2-7 Triacs, 2-30 Tum-ON: delay, 3-11 spurious, 5-58 to 5-64 (See also dV/dt) time, 3-11 Tum-OFF: delay, 2-14, 2-41, 3-12 time, 2-41, 3-12, 3-38 Typical peiformance curves, 7-1 Table of Symbols, 8-5 Temperature: effects, 5-55 junction effect on dVldt, 5-61 very low, operation at, 5-80 to 5-86 Test: circuits, 7-1 descriptions, 7-17 equipment, 7-7 external visual, 7-20 high temperature: gate bias, 7-18 reverse bias, 7-19 lead integrity, 7 -18 physical dimensions, 7 -17 pressure pot, 7-20 salt atmosphere, 7-18 temperature cycle, 7 -20 thermal shock, 7-19 Testing, 7-1 accelerated, 7-8 Thermal: concerns, 7-7 design, 4-1, 5-75 effects, 3-7 impedance, 5-16, 8-3 model,4-1 pulsed operation, 4-2 steady state, 4-1 transient, 4-2 resistance, 4-2, 7-6, 8-8 runaway, 2-66 stability, 4-1 time constants, 4-2 Third quadrant operation, 5-89 Threshold voltage, 1-3,2-11,2-62, 3-3 Thyristors, 2-41 Timing wave forms, synchronous rectifier, 5-72 to 5-74 Transconductance, 2-20, 3-4, 3-5, 5-56 Transfer characteristics, 3-3, 3-4 Transformer, 6-41, 6-141 construction, 6-65 design, 5-93 Velocity saturation, 3-4, 3-5 Venturini converter, 2-29 Vertical DMOS, 2-24 Vertical double-diffused MOSPET, 1-3 V-groove, 1-5,2-20,2-21,2-66 technology, 2-66 VMOS structure, 7-15 Voltage: breakdown: effects of radiation upon, 5-104 gate-source due to oscillation, 5-48 rating, 1-8 regulators, 6-145 reverse, 5-209 sustaining, 2-49 threshold, effects of radiation, 5-103 -to-Frequency converter, 6-188 transfer functions, 6-42 Y -parameters, 2-68, 2-69 Zener, 2-46 gate protection, 3-9 Zero: bias, 1-3 ripple: currents, 6-30, 6-41 techniques, 6-25 temperature coefficient (TC) point, 3-3 to 3-5 9-8
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