1985_U75_Hitachi_HD68484_ACRTC_Advanced_CRT_Controller_Users_Manual 1985 U75 Hitachi HD68484 ACRTC Advanced CRT Controller Users Manual
User Manual: 1985_U75_Hitachi_HD68484_ACRTC_Advanced_CRT_Controller_Users_Manual
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-- :-- -=· :-;= - ;; :--:;:-;.:: - ::--;: ELECTRONICS = . . iF ........ " . CORPORRTION 20151 Bahama Street Olatsworth, California 91311 (213) 644-7596 (818)7QO.a700 (818)341-4411 HD63484 ACRTC ADVANCED CRT CONTROLLER USER'S MANUAL #U75 .HITACHI When using this manual, the reader should keep the following in mind: 1. This manual may, wholly or partially, be subject to change without notice. 2. All rights reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this manual without Hitachi's permission. 3. Hitachi will not be responsible for any damage to the user that may result from accidents or any other reasons during operation of his unit according to this manual. 4. This manual neither ensures the enforcement of any industrial properties or other rights, nor sanctions the enforcement right thereof. 5. Circuitry and other examples described herein are meant merely to indicate characteristics and performance of Hitachi semiconductorapplied products. Hitachi assumes no responsibility for any patent infringements or other problems resulting from applications based on the examples described herein. May 1985 OCopyright 1985, Hitachi America, Ltd. Printed in U.S.A. TABLE OF CONTENTS 1. ACRTC INTRODUCTION 1.1 1.2 1.3 1.4 1.5 1. 6 1.7 1.8 Applications ....................................................... 3 System Configuration ............................................... 5 Block Diagram ..................................................... 6 Signal Description .................................................. 8 Address Space .................................................... 10 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Commands ....................................................... 15 Graphic Drawing .................................................. 16 2. SYSTEM INTERFACE 2.1 2.2 2.3 Basic Clock ....................................................... 17 CRT Interface .................................................... 17 MPU Interface .................................................... 28 3. DISPLA Y FUNCTION 3.1 3.2 3.3 3.4 3.5 3.6 Logical Display Screens ............................................ 30 Cursor Control ................................................... 37 Scrolling ......................................................... 40 Raster Scan Modes ................................................ 43 Zooming ......................................................... 45 Light Pen ........................................................ 46 4. SIGNAL DESCRIPTION 4.1 4.2 Pin Arrangement ...................... '" ........................ 47 Signal Functions .................................................. 48 5. REGISTER DESCRIPTION 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 Internal Register Access ........................................... 57 Address Register. ................................................. 60 Status Register .................................................... 61 FIFO Entry ...................................................... 64 Command Control Register ........................................ 65 Operation Mode Register .......................................... 69 Display Control Register ........................................... 75 Timing Control RAM ............................................. 79 Display Control RAM ................................ , ............ 96 Drawing Control Registers .................... , ................... 113 6. COMMANDS 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Command Overview ............................................. 125 Command Format ............................................... 125 Command Transfer Modes ....................................... 126 Register Access Commands ....................................... 127 Data Transfer Commands ........................................ 128 Graphic Drawing Commands ..................................... 135 Graphic Drawing Processor ....................................... 162 Graphic Drawing Operation ....................................... 166 FUNCTION OF COMMANDS . ............................................. 171 USE OF ARC AND ELLIPSE ARC COMMAND .............................. 301 ELECTRICAL SPECiFiCATION ............................................. 309 Abbreviations Name Description AARC ABT ACM ACP ADR AEARC AFRCT AGCPY ALINE AMOVE APLG APLL AR ARCT ARD ARE AREA ATC ATR BCA BCAI BCA2 BCERI BCER2 BCR BCSRI BCSR2 BCURI BCUR2 BCWI BCW2 BLINKI BLINK2 BOFFI BOFF2 BONI BON2 Absolute Arc Abort Access Mode Access Priority Area Definition Register Absolute Ellipse Arc Absolute Filled Rectangle Absolute Graphic Copy Absolute Line Absolute Move Absolute Polygon Absolute Poly Line Address Register Absolute Rectangle Area Detect Area Detect Interrupt Enable Area Detect Mode Attribute Code Attribute Control Block Cursor Address Block Cursor Address I Block Cursor Address 2 Block Cursor End Raster I Block Cursor End Raster 2 Blink Control Register Block Cursor Start Raster I Block Cursor Start Raster 2 Block Cursor Register I Block Cursor Register 2 Block Cursor Width I Block Cursor Width 2 Blink I Blink 2 Blink Off I Blink OtT 2 Blink On I Blink On 2 Abbreviations Name Description CCR CDM CDR CED CEE CER CHR CLR CLO CLI CM CCMP COFFI COFF2 CONI CON2 CP CPY CRCL CRE CSK CXE CXS CYE CYS DCR DDM OMOD ON OaT DP OPAH OPAL DPD ORC DRD DSD Command Control Register Command DMA Mode Cursor Definition Register Command End Command End Interrupt Enable Command Error Character Clear Color 0 Register Color I Register Cursor Mode Color Comparison Register Cursor Off 1 Cursor Off 2 Cursor On 1 Cursor On 2 Current Pointer Copy Circle Command Error Interrupt Enable Cursor Display Skew Cursor X End Cursor X Start Cursor Y End Cursor Y Start Display Control Register Data DMA Mode DMA Modify Display Number Dot Drawing Pointer Drawing Pointer Address High Drawing Pointer Address Low Drawing Pointer Dot DMA Request Control DMA Read Destination Scan Direction Abbreviations Name Description DSK DSP DWT EDG ELPS FE FRA FRAO FRAI FRA2 FRA3 GAl GBM GCR HC HDR HDS HDW HSD HSR HSW HWR HWS HWW HZ HZF IE LPAH LPAL LPAR LPD LPE LRA LRAO LRAI LRA2 LRA3 DISP Skew DISP Signal Control DMA Write Edge Color Register Ellipse FIFO Entry First Raster Address First Raster Address 0 First Raster Address 1 First Raster Address 2 First Raster Address 3 Graphic Address Increment Mode Graphic Bit Mode Graphic Cursor Register Horizontal Cycle Horizontal Display Register Horizontal Display Start Horizontal Display Width Horizontal Scroll Dot Horizontal Sync Register Horizontal Sync Width Horizontal Window Display Register Horizontal Window Start Horizontal Window Width Horizontal Zoom Horizontal Zoom Factor Interrupt Enable Light Pen Address High Light Pen Address Low Light Pen Address Register Light Pen Strobe Detect Light Pen Strobe Interrupt Enable Last Raster Address Last Raster Address 0 Last Raster Address 1 Last Raster Address 2 Last Raster Address 3 Abbreviations Name Description MIS MM MOD MASK MW MWO MWI MW2 MW3 MWR MWRO MWRI MWR2 MWR3 OMR OPM ORG PAINT PE PEX PEY PP PPX PPY PRA PRC PS PSE PSX PSY PTN PZCX PZCY PZX PZY RAM RARC MasterlSlave Modify Mode Modify Mask Register Memory Width Memory Width 0 Memory Width 1 Memory Width 2 Memory Width 3 Memory Width Register Memory Width Register 0 Memory Width Register 1 Memory Width Register 2 Memory Width Register 3 Operation Mode Register Operation Mode Origin Paint Pattern End Pattern End X Pattern End Y Pattern Pointer Pattern Pointer X Pattern Pointer Y Pattern RAM Address Pattern RAM Control Register Pattern Start Pause Pattern Start X Pattern Start Y Pattern Pattern Zoom Count X Pattern Zoom Count Y Pattern Zoom X Pattern Zoom Y RAM Mode Relative Arc Abbreviations Name Description RAR RARO RARI RAR2 RAR3 RC RCR RD REARC RFE RFF RFR RFRCT RGCPY RLINE RMOVE RN RPLG RPLL RPR RPTN RRCT RRE RSM RWP RWPH RWPL S SAH SAL SAR SARO SARI SAR2 SAR3 SCLR SCPY Raster Address Register Raster Address Register 0 Raster Address Register I Raster Address Register 2 Raster Address Register 3 Raster Count Raster Count Register Read Relative Ellipse Arc Read FIFO Full Interrupt Enable Read FIFO Full Read FIFO Ready Relative Filled Rectangle Relative Graphic Copy Relative Line Relative Move Register Number Relative Polygon Relative Poly Line Read Parameter Register Read Pattern RAM Relative Rectangle Read FIFO Ready Interrupt Enable Raster Scan Mode Read/Write Pointer Read/Write Pointer High Read/Write Pointer Low Source Scan Direction Start Address High Start Address Low Start Address Register Start Address Register 0 Start Address Register I Start Address Register 2 Start Address Register 3 Selective Clear Selective Copy Abbreviations Name Description SD SDA SE Scan Direction Start Dot Address Split Screen Enable Split Screen 0 Enable Split Screen 1 Enable Split Screen 2 Enable Split Screen 3 Enable Slant Split Split Screen 0 Width Split Screen 1 Width Split Screen 2 Width Status Register Start Raster Address Split Screen Width Start Vertical Cycle Vertical Display Register Vertical Display Start Vertical Sync Register Vertical Sync Width Vertical Window Register Vertical Window Start Vertical Window Width Vertical Zoom Factor Write FIFO Empty Interrupt Enable Write FIFO Empty Write FIFO Ready Write Parameter Register Write Pattern RAM Write FIFO Ready Interrupt Enable Window Smooth Scroll Write X Maximum X Minimum Y Maximum Y Minimum Zoom Factor Register SE~ SEl SE2 SE3 SL SPL SPO SPl SP2 SR SRA SSW STR VC VDR VDS VSR VSW VWR VWS VWW VZF WEE WFE WFR WPR WPTN WRE WSS WT XMAX XMIN YMAX YMIN ZFR HD63484 ACRTC (Advanced CRT Controller) Powerful visual interfaces are a key component of advanced system architectures. A proven technique uses raster scanned CRT technology for the display of graphics and text information. Systems which use first generation CRT Controllers (CRTCs) are constrained by hardware/software design time, manufacturing cost, and limited MPU bandwidth. To meet the functional requirements for powerful visual interfaces, and to support their use in high volume, cost sensitive applications, advanced circuit design and VLSI CMOS manufacturing technologies have been used to create a next generation CRTC, the HD63484 ACRTC (Advanced CRT Controller). The ACRTC concept is to incorporate major functionality, formerly requiring external hardware and software, on-chip. In this way, both higher performance and reduced system cost benefits are achieved. * High Level Command Language Increases Performance and Reduces Software Development Cost. ACRTC Converts Logical X-Y Coordinates to Physical Frame Buffer Addresses. 38 Commands including 23 Graphic Drawing Commands - LINE, RECTANGLE, POLYLINE, POLYGON, CIRCLE, ELLIPSE, ARC, ELLIPSE ARC, FILLED RECTANGLE, PAINT, PATTERN and COPY. On-chip 32 Byte Pattern RAM. Conditional Drawing function (8 conditions) for Drawing Patterns, Color Mixing and Software Windowing. Drawing Area Control with Hardware Clipping and Hitting. Maximum Drawing Speed of 2 Million Logical Pixels per Second is the same for Monochrome and Color applications. HITACHI * High Resolution Display with Advanced Screen Control Up to 4096 by 4096 Bit Map GRAPHIC Display and/or 256 Line by 256 Character by 32 Raster CHARACTER Display. Separate Bit Map GRAPHIC (2M byte) and CHARACTER (128K byte) Address Spaces with Combined GRAPHIC/CHARACTER Display. Three Horizontal Split Screens and One Window Screen. Size and Postition Fully Programmable. Independent Horizontal and Vertical Smooth Scroll for each Screen. 1 to 16 Zoom Magnitude - Independent X and Y Zoom Factors. Logical Pixel Specification as 1, 2, 4, 8 or 16 Bits for Monochrome, Gray Scale and Color Displays. Programmable Address Increment Supports Frame Buffer Memory Widths to 128 Bits for Video Bit Rates> 500 MHz. Unique Interleaved Access Mode for Screen Superimposition or 'Flashless' Displays. ACRTC provides Dynamic RAM Refresh Address. * High Performance MPU Interface Optimized Interface with the HD68000 MPU and HD68450 DMAC. 8 or 16 Bit Bus - Compatible With Other MPUs. Separate on-chip 16 Byte READ and WRITE FIFOs. Maskable Interrupts Including FIFO status. * Versatile CRT Interface Full Programmability of CRT Timing Signals. Three Raster Scanning Modes. Master or Slave Synchronization to Multiple ACRTCs or Other Video Generating Devices. Two Hardware Cursors. Three Cursor Modes. Progreammable Cursor and Display Timing Skew. Eight User Defineable Video Attributes. Light Pen Detection. * VLSI CMOS Process 2 HITACHI 1. ACRTC INTRODUCTION 1.1 Applications The overall function of a visual interface is logically partitioned into layers. At the lowest layer are CRT timing and control signal generation. At the top layer are general purpose drawing procedures which provide a high-level interface to the users OS or applcation software. At this layer, a number of popular standards have emerged including GKS, Core, NAPLP, GSX and others. Figure 1.1 shows how the ACRTC performs the key functions or logical drawing algorithm and physical drawing execution. Formerly, these function were performed by external hardware andlor MPU software. MPU Drawing Procedures Soft- Co-ordinates Conversion Drawing Pre-process Drawing Process MPU ware Soft............... ware (Algori thms) Drawing Execution c------. ACRTC Display Control Synchronizing CRTC Signals Generation Others Figure 1.1 ACRTC vs. CRTC HITACHI 3 As shown, the ACRTC reduces the 'gap' between device functionality and high level graphics procedures. Since the ACRTC device itself provides capabilities closely related to those of high level graphics packages, the effort (hardware and software design time and cost) required to develop a visual interface is significantly reduced. Noting the traditional and emerging applications for visual interfaces, figure 1.2 shows that a single ACRTC is suitable for a broad range of products in both alphanumeric and graphics areas. Multiple ACRTCs can achieve performance beyond that of any first generation CRTC configuration. Flight Silhulator Work Station CAD/CAM Terminal Game Machine Business Computer High-end Personal Computer Word Processor Videotex ,j Graphic Characte Dumb Terminal Applications ACIUC Coverage Figure 1.2 Application Spectrum 4 HITACHI 1.2 System Configuration MA16-19 CPU (8/16b) I\r-T"""T"Y'I System Memory ACRTC DISPl,2 CUDl,2 LPSTB EXSYNC DMAC Vcc,Vss VSYNC HSYNC Figure 1.3 System Configuration Existing CRTCs provide a single bus interface to the frame buffer which must be shared with the host MPU. However, the refresh of large frame buffers and the requirement to access the frame buffer for drawing operations can quickly saturate this shared bus bandwidth. As shown, the ACRTC uses separate host MPU and frame buffer bus interfaces. This allows the ACRTC full access to the frame buffer for display refresh, DRAM refresh and drawing operations while minimizing the ACRTCs usage of the MPU system bus. Thus, overall system performance. is maximized. A related benefit is that a large frame buffer (2M byte for each ACRTC) is useable even if the host MPU has a smaller address space or segment size restriction. The ACRTC can utilize an external DMA Controller. This increases system throughput when large amounts of command, parameter and data information must be transferred to the ACRTC. Also, advanced DMAC features, such as the HD68450 DMACs 'chaining' modes, can be used to develop powerful graphics system architectures. However, more cost sensitive or less performance sensitive applications do not require a DMAC. The interface to the ACRTC can be handled completely under MPU software control. While both ACRTC bus interfaces (Host MPU and Frame Buffer) exploit 16 bit data paths for maximum performance, the ACRTC also offers an 8 bit MPU mode for easy connection to popular 8 bit bus structures. HITACHI 5 1.3 Block Diagram RES I DREQ DACK DONE IRQ ---...... -I-- Drawing Address DMA Control Unit Register Address 20 Data Processor Data Inter rupt Control Unit Drawing Drawing 16 ,------,. Draw Enable Write I- I- f--D RAW I- f--M RD Fbi ~ A16/RAO t= F==>MMA19/RA3 MADO~15 ~ ,abF f< f< DO-1 5 r- Displ ay Address t-- F~ RS - I- - I- - RA4 Raster t Display Processor Address 5 ~ -I- '-- 20 CRT Interface CHR l - f-- CHR MPU Interface CCUD 1ft t 1--1-- LPSTB I-~ CUD1~2 K - I- GCUD 2 HSYNC I-f-VSYNC C:: I EXSYNC ; ~ Timing DISP Processor 2 -:--I-f-- -4- MCLK I - r - MCYC AS 2CLK J2 T Vee Vss Figure 1.4 Block Diagram 6 HITACHI -I-I-f-- 2CLK The ACRTC consists of five major functional blocks. These functional blocks operate in parallel to achieve maximum performance. Two of the blocks perform the external bus interface for the host MPU and CRT respectively. MPU Interface Manages the asynchronous host MPU interface including the programmable interrupt control unit and DMA handshaking control unit. CRT Interface Manages the frame buffer bus and CRT timing input and output control signals. Also, the selection of either display refresh address or drawing address outputs is performed. The other three blocks are separately microprogrammed processors which operate in parallel to perform the major functions of drawing, display control and timing. Drawing Processor Interprets commands and command parameters issued by the host bus (MPU and/or DMAC) and performs the drawing operations on the frame buffer memory. This processor is responsible for the execution of ACRTC drawing algorithms and conversion of logical pixel X-Y addresses to physical frame buffer addresses. Communication with the host bus is via separate 16 byte read and write FIFOs. Display Processor Manages frame buffer refresh addressing based on the user programmed specification of display screen organization. Combines and displays as many as 4 independent screen segments (3 horizontal splits and 1 window) using an internal high speed address calculation unit. Controls display refresh address outputs based on GRAPHIC (physical frame buffer address) or CHARACTER (physical frame buffer address + row address) display modes. Timing Processor Generates the CRT synchronization signals and other timing signals used internally by the ACRTC. The ACRTCs software visible registers are similarly partitioned and reside in the appropriate internal processor depending on function. The registers in the Display and Timing processors are loaded with basic display parameters during system initialization. During operation, the host pri"marily communicates with the ACRTCs Drawing processor via the on-chip FIFOs. o o o o o HITACHI 7 1.4 Signal Description Following is a brief description of the ACRTC pin functions organized as MPU Interface, DMAC Interface, CRT Interface and Power Supply. The detailed signal description is provided in section 4. MPU Interface ) RES - Input Hardware reset input to the ACRTC. DO - D15 - Input/Output The bidirectional data bus for communication with the host MPU or DMAC. In 8 bit data bus mode, DO-D7 are used. R/W - Input Controls the direction of host ~ ACRTC transfers. CS - Input Enables data transfers between the host and the ACRTC. RS - Input Selects the ACRTC register to be accessed and is normally connected to the least significant bit of the host address bus. DTACK - Output Provides asynchronous bus cycle timing and is compatible with the HD68000 MPU DTACK input. IRQ - Output Generates interrupt service requests to the host MPU. DMAC Interface DREQ - Output Generates DMA service requests to the host DMAC. =D--:-A-=C=K - Input Receives DMA acknowledge timing from the host DMAC. "'D=O~N-'=;E - Input/Output Terminates DMA transfer and is compatible with the HD68450 DMAC DONE signal. 8 HITACHI CRT Interface 2CLK - Input Basic ACRTC operating clock derived from the dot clock. MADO-15 - Input/Output Multiplexed frame buffer address/data bus. AS - Output Address strobe for demultiplexing the frame buffer address/data bus (MADO15). MAI6/RAO-MA19/RA3 - Output The high order address bits for graphic screens and the raster address outputs for character screens. RA4 - Output Provides the high order raster address bit (up to 32 rasters) for character screens. CHR - Output Indicates whether a graphic or character screen is being accessed. MCYC - Output Frame buffer memory access timing - one half the frequency of 2CLK. MRD - Output Frame Buffer data bus direction control. DRA W - Output Differentiates between drawing cycles and CRT display refresh cycles. DISPl, DISP2 - Output Programmable display enable timing used to selectively enable, disable and blank logical screens. CUD 1, CUD2 - Output Provides cursor timing determined by ACRTC programmed parameters such as cursor definition, cursor mode, cursor address, etc. HITACHI 9 VSYNC - Output CRT device vertical synchronization pulse. HSYNC - Output CRT device horizontal synchronization pulse. EXSYNC - Input/Output For synchronization between multiple ACRTCs and other video signal generating devices. LPSTB - Input Connection to an external light pen. 1.5 Address Space The ACRTC allows the host to issue 'commands using logical X-Y coordinate addressing. The ACRTC converts these to physical linear word addresses with bit field offsets in. the frame buffer. Figure 1.5 shows the relationship between a logical X-Y screen address and the frame buffer memory, organized as sequential 16 bit words. The host may specify that a logical pixel consists of 1, 2, 4, 8 or 16 physical bits in the frame butTer. In the example, 4 bits per logical pixel is used allowing 16 colors or tones to be selected. Up to four logical screens (Upper, Base, Lower and Window) are mapped into the ACRTC physical address space. The host specifies a logical screen physical start address, logical screen physical memory width (number of memory words per raster), logical pixel physical memory width (number of bits per pixel) and the logical origin physical address. Then, logical pixel X-Y addresses issued by the host or by the ACRTC Drawing processor are converted to physical frame butTer addresses. The ACRTC also performs bit extraction and masking to map logical pixel operations (in the example, 4 bits) to 16 bit word frame butTer accesses. 10 HITACHI \. \ \. :;j~----~r----t"-> cr:::>: ;:I CD: 0 2CLK - :I MCYC 5plit 5creen Display Cycle Refresh Address Output Cycle (in DRAM mode) CY[J: a::J: CD: Window Display Cycle Drawing·Possible Cycle c::Q:): (when no drawing In this cycle the output wi 1\ be fixed at "0" is executed the output will be fixed at "0",) Attribute Output Cycle -....rv U\.F ~ J\F ~ J'\.FV\.J\J\J\. f..r\.J\J\.r J\JVV"\J\... -t...-I ..J""' ~~ ~ ~ ~ w- H5YNC DI5Pl DI5P2 (W55=' )) ." . cE' c CD ....~ ~ » n n CD U) U) ~ [5A] AS MAD ~ -J -~ MA/RA O' IA: "HIGH" 0 5 5 5 5 W W I W A 5 W I 5 0 ~ 0 I 0 MRD "HIGH" DI5P2 (W55="1 ") AS l.J m----m---rn---r ~ ([}-€O)-- CD---pJI -f O' IAJ "HIGH" I MRD I "HIGH" I I DRAW CQ DI5P2 (WSS="l ") [DAl) ""~ 5 0 A 0 5 I 0 J. 0 5 W ~ 0 J. W ~ w--m-- m----m----m- 0 5 I 0 0 "-SL...A..Jl I I I I I I I I I I I I J I \ ~~ J I -~ m---hr- m----m---rn---r ~ 0---CD- ~ O· MA/RA 0 A DRAW , s I I I "HIGH" I I I I I : MRD DI5P2 (WSS="l ~ J I I I MA/RA MAD : oJ I CD Q. A5 I I I I [DAO] MAD S' 5 0 DRAW 0 3' ~ ~~ tD- Pr- m-- ~ ~ pr-..m- m----m----m- I 0 5 X o I 5 X 0 5 X W 5 I W ~ \ 5 X 0 0 X o X 0 2.2.1.2 Graphic Address Increment Mode During display operation, the ACRTC can be programmed to control the graphic display address in six ways including increment by 1, 2, 4 and 8 words, 1 word every two display cycles and no increment. Setting GAl to increment by 2,4 or 8 words per display cycle achieves linear increases in the video data rate i.e. for a given configuration setting GAl to 2, 4 or 8 words will achieve 2, 4 or 8 times the video data rate corresponding to GAI= l. This allows increasing the n'.Imber of bits/logical pixel and logical pixel resolution while meeting the 2CLK maximum frequency constraint. Figure 2.2 shows the summary relationship between 2CLK, Display Access Mode, Graphic Address Increment, # bits/logical pixel, memory access time and video data rate. The frame buffer cycle frequency (Fe) is shown by the following equation where: Fv Dot Clock N - # bits/logical pixel D - Display Access Mode 1 for Single Access Mode 2 for interleaved and Superimposed Access Modes A - Graphic Address Increment (1/2, 1, 2, 4, 8) Fc (Fv x N x D)/(A x 16) Dot Rate Access Mode Color No. (bit/pixel) Memory Cycle 250ns 1 500ns 250ns 2 500ns 250ns 4 500ns 250ns 8 500ns 250ns 16 500ns 16MHz S - D 32MHz S +1/2 + 1/2 + 1/2 +1 +1 + 1/2 +1 +1 +1 +2 +2 +1 +2 +2 +2 +4 +4 +2 +4 +4 +4 +8 +8 +4 +8 +8 +8 - 64MHz 128MHz D S D S D +1 +2 +2 +4 +4 +8 +8 +1 +2 +2 +4 +4 +8 +8 +2 +4 +4 +8 +8 +2 +4 +4 +8 +8 +4 +8 +8 - - - - - - - - - Figure 2.2 Graphic Address Increment Modes HITACHI 23 2.2.2 Dynamic RAM Refresh When dynamic RAMs (DRAMs) are used for the frame butTer memory, the ACRTC can automatically provide DRAM refresh addressing. The ACRTC maintains an 8 bit DRAM refresh counter which is decremented on each frame butTer access. During HSYNC low, the ACRTC will output the sequential refresh addresses on MAD. The refresh address assignment depends on Graphic Address Increment (GAl) mode as shown in figure 2.3(a). Address Increment Mode + 1 (GAI= 000) Refresh Address Output Terminal + 2 (GAI=001) MAD1-S +4 (GAI=010) MAD2-9 +S (GAI=011) MAD3-10 + 1/2 (GAI= 111 ) MADO-7 MADO-7 Figure 2.3 (a) GAl and DRAM Refresh Addressing The ACRTC provides "0" output on the remaining address line of MAD and MA/RA. DRAM refresh cycle timing must be factored into the determination of HSYNC low pulse width (HSW - specified in units of frame butTer memory cycles). If the horizontal scan rate is Fh (kHz), number of DRAM refresh cycles is N and the DRAM refresh cycle time is Tr (msec) then horizontal sync width (HSW) is specified by the following equation: HSW ~ N I (Tr X Fh) For example, if the scan rate is 15.75 kHz and the DRAMS have 128 refresh cycles of 2 msec, HSW must be greater than or equal to 5. HSW ~ 128 I (2 X 15.75) = 4.06 24 HITACHI ." ca' e (; N 2CLK W ~ DISP C HSYNC » AS ::a s: ::a CD -to MAD ~ A ~ MA/RA A ~ CD (II ::r -I 3' :i' ca ::t ~ (') -::t '" (J1 RA4 CHR DRAW MRD "High" ~ 1 0) : 0 0) 0 : REF) 0 ~ REF J 0 rBi ATB 0 ) o ~ 0) 0 1 A A 2.2.3 External Synchronization The ACRTC EXSYNC pin allows synchronization of multiple ACRTCs or other video signal generators. The ACRTC may be programmed as a single Master device, or as one of a number of Slave devices. To synchronize multiple ACRTCs, simply connect all the EXSYNC pins together. For synchronizing to other video signals, the connection scheme depends on the raster scan mode. In Non-Interlace mode, EXSYNC corresponds to VSYNC. In Interlace modes, EXSYNC corresponds to VSYNC of the odd field. Clock Signal ..... 2CLK ACRTC (slave) '- 2CLK EXSYNC ACRTC (Master) I EXSYNC '-- 2CLK ACRTC (slave) E5 --t---------------- ---------.., ! File Name: MOS : , ,," :' SARO ~-----------------------~ FFFF 1----4::.,:-,----- _____ .l.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----I ...................... "-,,~------_-_-_-_~_=_M_W_2========::__l.aoll -~--------------------~ Frame Buffer for Graphic 00000 ----___ r-- MW1---l-1 --- SAR1 - f---r-------------, ,: ,, ,, ,,, , I ,L,_______________ J I File Name: MOS I-----I.-.::.----- _______....L....-_ _ _......JI ~ __________________ ,-_________ _ ,, " """ r-,=_~~ SAR3 F FF F F'-----\. Screen # o 1 2 3 ctb ~~ t.UJ ________________ L _______ _ " Position Upper Base Lower Window " ,, , Left " .... , : Layout Symbol Right : _ V'L-_ __ _ _ _ _-.-J '''---''_ _ _---1 Figure 3.2 Display Screen Combination 32 HITACHI He I. -I I I : :~.r-___H_W __S_______I~_____H_W_W ____~ I : 1 HSW I I :. I : IHOS: I I I I HOW .' r-------~--------~~--------~r------- -- 1---------\------------- ------ --- C/l ~-- 1-----------+---- -- --- --- r----------t --- ----- -1.-_ _ _ _ _ _"- ____________________ --- sg-- < o i'J ~-----------------------~-------- --- Figure 3.3 Display Screen Specification HITACHI 33 (,J .j>.. x ~ o x - Memory Cycle 2CLK MCYC HSYNC "'n DISPI ; DISP2 cS' c Horizontal Display Width -(HDW+l)·M---........ Horizontal Display start I" (HDS+l)'M_ Horizontal Sync Width HSW.M W Horizontal Window ~ ~ Horizontal Window Start I- IHWS+l)·M .. Width (HWW+l)·M ~~?~~)~t~1 C iii' ~ Cycle 'C iii '< en n ; HSYNC CD VSYNC 3' s' ec DISPI :s -I DISP2 Vertical Display UPlit Start -(VDS+1)· H (VWS+1)· H Vertical Window Start Screen Vertical 0 Vertical Sync Width VSW·M Display Width SPQ· H - - - - < o...oll....f - - - - - ... 1.. Vertical Window Width I VWW' H .. VC.H------------------J ... 1 Vertical Cycle SPO-Upper EX. 1 SP1-Base SP3Window EX . 2 SP3SP1-Base W'Ind ow SP2-Lower SPO-Upper SPO-Upper EX. 3 SP1-Base SP2-Lower SP3-Window EX. 4 I ,I SP1-Base SP3Window SP2-Lower Figure 3.5 Example Screen Combinations HITACHI 35 3.1 .1 Graphic/Character Address Spaces The ACRTC controls two separate logical address spaces. The CHR pin allows external decoding if physically separate frame buffers are desired. Each of the four logical screens (Upper, Base, Lower and Window) is programmed as residing in the Graphics address space or the Character address space. ACRTC accesses to Graphics screens are treated as bit mapped using a 20 bit frame buffer address, with an address space of one megaword OM by 16 bit). ACRTC accesses to Character screens are treated as character generator mapped. In this case, a 64K word address space is used and 5 bits of raster address are output to an external character generator. Multiple logical screens defined as Character can be externally decoded to use separate character generators or different addresses within a combined character generator. Also, each Character screen may be defined with separate line spacing, separate cursors, etc. ------------------IF - First Raster Address (FRA) - Last Raster Address (LRA) --+O~-----+O~---oo --+0~-----+04----01 --+0~-----+04----02 -0Ht-0*0-ti0'--tt-0*0+-- 03 --+04------+04---- 04 --+0~-----+0~---05 --+0~-----+0~---06 ------------------07 - - - - - - - - - - - - - - - - - - 08 L . "" Ad're" Figure 3.6 Character Screen Raster Addressing 36 HITACHI 3.2 Cursor Control The ACRTC has two Block Cursor Registers and a Graphics Cursor Register. A Block cursor is used with Character screens. The cursor start and ending raster addresses are fully programmable. Also, the cursor width can be defined as one to eight memory cycles. A Graphics cursor is defined by specifying the start and end addresses in both the X and Y dimensions. HITACHI ~ Cursor1 ACRTI9 ~ Cursor2 Figure 3.7(a) Two Separate Block Cursors HITACHI 37 eeeeee eeeeee eeeeee e8eeee eeeeee eeeeee eeeeee BCSR=07 BCER=07 BCSR=02 BCER=07 eeeeee eeeeee eeeeee 05 06 07 08 BCSR=oo BCER=02 U..-------------;7 Figure 3.8 Graphic Cursor 38 HITACHI 01 02 03 04 Figure 3.7(b) Block Cursor Examples o 1F 00 CUD1 The ACRTC provides two separate cursor outputs, CUDl and CUD2. These are combined with two character cursor registers and a graphics cursor register to provide three cursor modes. 3.2.1 Block Mode Two Block cursors are output on CUDl and CUD2 respectively. 3.2.2 Graphic Mode The Graphic cursor is output on CUD 1. Using an external cursor pattern memory allows a graphic cursor of various shapes. Two Block cursors are multiplexed on CUD2. 3.2.3 Crosshair Mode The horizontal and vertical components of the Graphic cursor are output on CUDl and CUD2 respectively. This allows simple generation of a crosshair cursor control signal. CUDl HOrizontal Cursor Signal ________~n~______~n~______ <: !:': (;' !!!. ('l c til ~ CI> ~' !!!. ~I Figure 3.9 Crosshair Cursor HITACHI 39 3.3 Scrolling 3.3.1 Vertical Scroll Each logical screen performs independent vertical scroll. On Character Screens, vertical smooth scroll is accomplished using the programmable Start Raster Address (SRA). Line by line scroll is accomplished by increasing or decreasing the screen start address by one unit of horizontal memory width. On Graphics screens, vertical smooth scroll is accomplished by increasing or decreasing the screen start address by one unit of horizontal memory width. 3.3.2 Horizontal Scroll Horizontal scroll can be performed in units of characters for Character screens and units of words (multi logical pixels) for Graphic screens by increasing or decreasing the screen start address by 1. For smooth horizontal scroll, the ACRTC has dot shift video attributes which can be used with an external circuit which conditions shift register load/clocking. Since this dot shift information is output each raster, horizontal smooth scroll is limited to either the Background screens or the Window screen at any given time. However, horizontal smooth scroll is independent for each of the Background screens (Upper, Base, Lower). 40 HITACHI Defined Frame Buffer Start Address ( S A R ) SAR 1 SAR' Start Address ( S A R I --,I - --r----------I I I ) I I I I I I : ctlJ MOS I "" I I I I I I I I I I I I L----i---------~ Scroll ing I I I I I r----t- --- --- --,I dD MOS .. ctlJ MOS I I I I I I I I I I I ~--------------~ Figure 3.10 Scrolling By SAR (Start Address Register) Rewrite HITACHI 41 ~~ __________________ I8118 1881 ________________ Z Memory n ____ ~r-- I8n __ ~ u_ Address Figure 3.11 Horizontal Smooth Scroll - Base Screen Background DISPI DI SPZ MAD ~L____________________________~._ 1 Display Cycle Fm8B~I' I ---IBkl\I'lI"··lW~ - n -- - i BJw.i...··J '" I----IB.: '" I B Background Address * Empty Cycle or Drawing Cycle W Widnow Address Figure 3.12 Horizontal Smooth Scroll - 42 HITACHI Window Screen 3.4 Raster Scan Modes The ACRTC has three software selectable raster scan modes - Non-Interlace, Interlace Sync and Interlace Sync & Video. In Non-Interlace mode a frame consists of one field. In the Interlace modes, a frame consists of two fields, the even and odd fields. The Interlace modes allow increasing screen resolution while avoiding limits imposed by the CRT display device, such as maximum horizontal scan frequency or maximum video dot rate. Interlace Sync mode simply repeats each raster address for both the even and odd fields. This is useful for increasing the quality of a displayed figure when using an interlaced CRT device such as a Television Set with RF modulator. Interlace Sync & Video mode displays alternate even and odd rasters on alternate even and odd fields. For a given number of rasters/character, this mode allows twice as many characters to be displayed in the vertical direction as Non-Interlace mode. Note that for Interlace modes, the refresh frequency for a given dot on the screen is one-half that of the Non-Interlace mode. Interlace modes normally require the use of a CRT with a more persistent phosphor to avoid a flickering display. Even-Odd----- 1F 00 01 02 03 04 05 06 0 0 0 0 0 0 cxxx:xx:x:x:xJ 0 0 0 0 0 0 1F _______________ _ ,..... ,..... 00 >< ;o-c -,.}----------)< - 01 _>02 _>- ----------r-r;o-c __________ >c _ 03 ~~-~l_.~~-l_~'*~-Jf~*~.,-~)--.04 ---------- ~ 05_ >- _ _________ >-r- 06_>->- __________ ~_ 1E---------------IF oo~+---------~- --------- -01 02 -€18E388E:S361-03 04~~--------+4- -05 06-------------------------------07 08--------------OA,~+_------_++_- -OB OC~+_--------~~ - -00 07 07 ______________ _ OE~~------_rT_- 08 M ______________ _ 10--------------- Non-Interlace ---------------11 Interlace Sync. Interlace Sync. & Video Figure 3.13 Raster Scan Modes HITACHI 43 ~ ~ :t ~ C') :t [NON-INTERLACE] H-S-Y-N-C~ RCR~ ." ca" e ; ~ ...a 0l:Io ~ .. S' en g ::s ~~==========================~--------~============================~--------~ EXSYNC ~ VSYNC (OUTPUT) I.. .-j [INTERLACE-SYNC] VSYNC VC2 ~ '~~~:~'I: (VSW=2) Dummy RCR~ ~ Cl r- I ""''''' J I. ,::., 000'"'' :i [INTERLACE-SYNC & VIDEO] VC=ODD H/2 Dumm RCR ~ -V----~~VT.C~-5~~VC~-~3~~V~C~-1~--~~~3~v-~~r-~-v-- ~ -I ~r 5" cc FRAME VSYNC ~ EXSYNC~ (OUTPUT) C EVEN-FIELD tt 11 H/2 r~ F:~:E ODD-FIELD :1 3.5 Zooming The Base screen (Screen 1) is supported by the ACRTC zooming function. Note that ACRTC zooming is performed by controlling the CRT timing signals. The contents of the frame butTer area being zoomed are not changed. The ACRTC allows specification of a zoom factor (1 to 16) independently in the X and Y directions. For horizontal zoom, the programmed zoom factor is output as video attributes. An external circuit uses this factor to condition the external shift register clock to accomplish horizontal zooming. For vertical zoom, no external circuit is required. The ACRTC will scan a single raster multiple times to accomplish vertical zooming. 3xl Cf9&': .. lx2 t 3x2 ~ .--- Figure 3.15 Zooming HITACHI 45 3.6 Light Pen The ACRTC provides a 20 bit Light Pen Address Register and a Light Pen Strobe (LPSTB) input pin for connection with a light pen. A light pen strobe pulse will occur when the CRT electron beam passes under the light pen during display refresh. When this pulse occurs, the contents of the ACRTC display refresh address counter will be latched into the Light Pen Address Register along with a logical screen (Character or Graphic screen) designator. Also, an ACRTC status flag indicating light pen activity is set, generating an optional (maskable) MPU interrupt. Note that for Superimposed access mode, when the light pen strobe occurs in an area in which the Window overlaps a Background (Upper, Base or Lower) screen, the Background screen address will be latched. Various system and ACRTC delays will cause the latched address to differ slightly from the actual light pen position. the light pen address can be corrected using software, based upon system specific delays. Or, if the application does not require the highest light pen pointing resolution, software can 'bound' the light pen address by specifying a range of values associated with a given area of the screen. 46 HITACHI 4. SIGNAL DESCRIPTION 4.1 Pin Arrangement Out In [ { In/Out Out In Out Out Out In/Out In/Out CUD1 CUD2 RIW CS RS RES DONE DREQ DACK DTACK IRQ HSYNC VSYNC Vee EXSYNC Vss DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 [ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 '-' 64 63 LPSTB DISP1 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 DISP2 MADO MAD1 MAD2 MAD3 MAD4 CHR MRD DRAW AS MCYC Vss 2CLK Vee MAD5 MAD6 MAD7 MAD8 MAD9 44 43 42 41 40 39 38 37 36 35 34 33 In J Out In/Out Out In In/Out MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 MA16/RAO MA17/RA1 MA18/RA2 Out MA19/RA3 RA4 Figure 4.1 Pin Arrangement HITACHI 47 4.2 Signal Functions The ACRTC signal functions are grouped into 4 functional categories, MPU Interface, DMAC Interface, CRT Interface and Power Supply. All signals are TTL compatible. 4.2.1 MPU Interface 4.2.1.1 Reset (RES:INPUT) A low level on the RES input forces the ACRTC into the following state. (a) Drawing and Display operation is stopped. (b) ACRTC registers are initialized as follows. Status register (SR) - CEO, WFR and WFE bits are set to 1, all other bits reset to O. Command Control Register (CCR) - The ABT bit is set to 1. All other bits are reset to O. Operation Mode Register (OMR) - The M/S and STR bits are reset to O. All other bits are unaffected. An other ACRTC registers are unaffected by RES'. (c) The DRAM refresh address is placed on the MAD lines determined by the graphic address increment (GAl) mode. This remains the case until the start bit (STR) in the Operation Mode Register (OMR) is set to 1. HSYNC is also held low during the period from RES until the start bit in OMR is set to 1 by the host. 4.2.1.2 Bi-directional Host System Data Bus (DO-D15:INPUT/OUTPUT:3-STATE) These lines are used for data transfer between the ACRTC and the host system data bus (MPU and/or DMAC). 00-015 outputs are three state buffers and remain in the high impedance state except during host reads of ACRTC registers. During reset, depending on the state of the OACK input, the ACRTC can be configured for an 8 bit data bus using 00-07. In this case, 08-015 should be left open. 4.2.1.3 ReadIWrite (RIW:INPUT) R/W controls the direction of transfer between the host system bus and the ACRTC. During non-DMA transfers, when RlW is high, data is transferred from the ACRTC to the host, and when low, data is transferred from the host to the ACRTC. 48 HITACHI When the ACRTC executes a DMA transfer using an external DMAC, the polarity of R/W is reversed. In this case, when R/W is high, data is transferred from the host to the ACRTC, and when low, data is transferred from the ACRTC to the host. 4.2.1.4 Chip Select (CS:INPUT) The Chip Select, when low, enables access of the ACRTC by the host MPU. Note that Chip Select must not be low during DMA transfers (DACK = low). RS and R/W must be valid when CS is asserted and write data must be valid prior to the trailing (rising) edge of CS. When the ACRTC host data bus mode is 16 bit data bus, 8 bit data transfers are not allowed. 4.2.1.5 Register Select (RS: INPUT) RS is used to select ACRTC hardware accessed registers. When RS is low, reads (R/W = high) access the Status register and writes (R/W = low) access the Ad- dress register. When RS is high, reads and writes access the particular ACRTC Control register with address defined in the previous write to the Address register. If the accessed register is in the range of r80 - rFF, the address register will automatically be incremented to allow access to the next sequential register address. This allows high speed initialization of registers in the address range of r80 - rFF without requiring the MPU to reload the address register for each sequential access. Note that the address increment is 1 for 8 bit host interface mode and 2 for 16 bit host interface mode. Normally, RS is connected to the least significant bit of the MPU address bus. 4.2.1.6 Data Transfer Acknowledge (DTACK:OUTPUT:OPEN DRAIN) The ACRTC will drive DTACK low to indicate completion of a data transfer cycle. DTACK is compatible with asynchronous bus interface hosts including the HD68000 MPU and HD68450 DMAC. 4.2.1.7 Interrupt Request (lRQ:OUTPUT:OPEN DRAIN) This open drain output is driven low when the ACRTC requires interrupt service. In order to generate an IRQ, the interrupting condition must be enabled in the Command Control Register (CCR). The action required to clear the interrupting condition is specified in the Status Register description (section 5.3). HITACHI 49 4.2.2 DMAC Interface Three DMA handshaking lines allow the ACRTC to use an external DMA controller. The DMA protocol is directly compatible with HD68450 DMAC single address mode transfers. 4.2.2.1 DMA Request (DREQ:OUTPUT) =~" During DMA transfer mode, DREQ is used to request data transfer service from the host bus DMAC. DREQ is asserted to active low level by ACRTC execution of a Data DMA transfer command (when the Data DMA Mode bit (DDM) in CCR is set to 1) or by setting the Command/Parameter DMA transfer mode bit (CDM) in the CCR to 1. Data DMA can be programmed as burst or cycle steal, while Command/Parameter DMA can only be burst mode. 4.2.2.2 DMA Acknowledge (DACK:INPUT) DACK is an answer back signal from the DMAC to which DREQ has been issued and indicates that the host bus has been acquired, and data transfer can occur. Note that when DACK is asserted low, CS must not be low and the R/W signal polarity is reversed. RS and R/W must be valid prior to DACK assertion and data written to the ACRTC must be valid prior to the trailing (rising) edge of DACK. DACK is also used to define whether an 8 or 16 bit host data bus is used. During reset, if DACK is low, 8 bit mode is used and if DACK is high, 16 bit mode is used. In the case of 8 bit mode, host-ACRTC communication occurs on the DO-D7 portion of the data bus, white D8-D15 are disabled and driven high. When 8 bit bus mode is selected the automatic increment mode for the Address Register is set to '+ l' (alternating even and odd register addresses), while 16 bit bus mode sets it to '+ 2' (even addresses only). When 16 bit host data bus mode is used, 8 bit transfers are not allowed. When DMA is not used, DACK should be pulled up to a high level. 4.2.2.3 Done (DONE:INPUT /OUTPUT:OPEN DRAIN) DONE is used to terminate DMA transfers. During Data DMA transfers, =-=-= DONE is an output and when asserted low indicates DMA termination to the exter- nal DMAC. During Command/Parameter DMA transfers, DONE is an input asserted low by the external DMAC to terminate DMA. Note that Data DMA cannot be terminated by externally forcing DONE low. DONE is open drain when in the output state, and should be pulled up to high level when not used. 50 HITACHI 4.2.3 CRT Interface 4.2.3.1 Clock (2CLK:INPUT) This is the basic operating clock for the ACRTC which is derived from the external dot clock. The ACRTC internally divides 2CLK by 2 to generate the MCYC Memory Cycle Clock. Thus, 2CLK is twice the frequency of the frame buffer memory access timing. 2CLK must be a continuous clock input. 4.2.3.2 Vertical Synchronization (VSYNC:OUTPUT) VSYNC is used to output the active low Vertical Synchronization timing signal required by the CRT display device. 4.2.3.3 Horizontal Synchronization (HSYNC:OUTPUT) HSYNC is used to output the active low Horizontal Synchronization timing signal required by the CRT display device. HSYNC is also used when the ACRTC performs DRAM refresh addressing of the frame buffer. In the case that the STR start bit or the RAM bit in the Operation Mode Register (OMR) are set to 0, HSYNC asserted low indicates that the DRAM refresh addresses are present on MAD frame buffer address/data bus. 4.2.3.4 External Synchronization (EXSYNC:INPUT/OUTPUT) EXSYNC is an active low input and output signal used for synchronizing multiple ACRTCs or synchronizing the ACRTC with other video generating devices. The ACRTC is programmed as a master or slave by the state of the M/S bit in the Operation Mode Register (OMR). When the ACRTC is master, EXSYNC is an output which may be used to drive a slave video generating devices VSYNC input or a slave ACRTCs EXSYNC input. When the ACRTC is slave, EXSYNC is an input which receives the masters EXSYNC (master is another ACRTC) or VSYNC (tnaster is another video generating device). In both master and slave configurations, the timing of EXSYNC depends on the interlace mode. For example, in interlaced modes, EXSYNC timing corresponds to VSYNC of the odd field. HITACHI 51 4.2.3.5 Light Pen Strobe (LPSTB:INPUT) LPSTB input accepts a positive strobe pulse generated by an external light pen. When asserted high, the current frame buffer display refresh address is latched into the Light Pen Address Register and the LPD (Light Pen Detect) bit in the Status Register is set to 1, generating an interrupt if enabled to do so by the MPU. The stored address will be different from the actual address due to the following delays. (a) ACRTC address output delay (b) Address output to video signal output delay (c) Light pen detection to LPSTB delay (d) LPSTB to internal recognition delay The actual address should be calculated by adjusting the stored address considering the above delays. Also note that, for Superimposed access mode, when the light pen strobe occurs in the Window screen, the overlapped Background (Upper, Base, Lower) screen address is latched. 4.2.3.6 Memory Cycle (MCYC:OUTPUT) MCYC frequency is one-half that of thr ACRTC 2CLK input and is output continuously. MCYC determines frame buffer memory access timing. MCYC low indicates the address portion of the memory access while MCYC high indicates the data portion of the memory access. 4.2.3.7 Address Strobe (AS:OUTPUT) AS output is used to latch the frame buffer address. When AS is low, the MAD outputs contain the frame buffer address. AS is also used to load the external parallel to serial (shift register) converter with the data from frame buffer during the display cycle. 4.2.3.8 Memory Read (MRD:OUTPUT) During a frame buffer access, MRD indicates the direction of data transfer between the ACRTC and the frame buffer. When MRD is high, a frame buffer read cycle occurs, and when MRD is low, a frame buffer write cycle occurs. In superimposed mode, MRD low indicates the read cycle of window screen data (second phase). 4.2.3.9 Draw (DRAW:OUTPUT) The DRAW signal differentiates between ACRTC drawing and CRT display refresh cycles. When DRAW is low, the MAD outputs contain multiplexed drawing address and data information. When DRAW is high, the MAD outputs contain a display refresh address during the address portion of the cycle, and are high impedance during the data portion of the cycle. 52 HITACHI 4.2.3.10 Frame Buffer Memory Address/Data (MADO-MAD 1 5 :INPUT/OUTPUT:3-STATE) MADO-MAD15 are the time multiplexed, bi-directional frame buffer memory address and data bus. When AS is low, MAD contains the lower 16 bits of the drawing or display address. When AS is high and DRAW is low, MAD transfers the drawing data to and from the frame buffer. When no frame buffer access is occurring, the MAD bus is 3-stated. When the RAM bit in the Operation Mode Register (OMR) is set to 0, the 8 bit DRAM refresh address is output on MAD during HSYNC low. The particular bits of MAD used for this 8 bit refresh address depend on the programmed Graphic Address Increment (GAl) mode. 4.2.3.11 Memory Address/Raster Address (MA 16/RAO-MA 19/RA3:0UTPUT) These lines output either the 4 most significant bits of the frame buffer address (MA16-MA19) or the 4 least significant bits of the raster address (RAO-RA3). In Character mode (CHR = high), these lines are used as a raster address for connection to an external character generator. In Graphic mode (CHR = low) these lines are used with MADO-MAD15 to provide a 20 bit linear frame buffer address. 4.2.3.12 Raster Address 4 (RA4:0UTPUT) In Character mode (CHR = high), RA4 output the most significant bit of the raster address. Thus, 5 bits (RAO-RA4) provide up to 32 rasters per character. In Graphic mode (CHR = low), the state of this output is undefined. 4.2.3.13 Character (CHR:OUTPUT) CHR is an output indicating whether the current frame buffer address on MAD has been defined as corresponding to character (CHR = high) or graphic (CHR = low). When high, MADO-MAD15 contains a 16 bit frame buffer address, while other MAD lines contain raster address information. When low, MADO-MAD15, MA16-MA19 contains a 20 bit linear frame buffer address. CHR can be used to enable an external character generator. Also, CHR can be used to enable the appropriate memory bank in the case that character and graphic memory are separated. HITACHI 53 4.2.3.14 Display Timing (DISP1,DISP2:0UTPUT) These active low outputs indicate the active display period of the screen. They can be used in one of two ways. (a) Background screen/window screen display timing signal (b) Vertical/horizontal display timing signal 4.2.3.15 Cursor Display (CUD1,CUD2:0UTPUT) These outputs are externally logically combined with the video signal to produce the cursor display on the screen. Three modes of cursor display are selectable by setting the cursor mode (CM) bits in the Cursor Definition Register (CDR). Cursor Mode Description CUD1 CUD2 The separate display of two BLOCK cursors Block cursor 1 Block cursor 2 GRAPHIC The display of a GRAPHIC cursor and two multiplexed BLOCK cursors Graphic cursor Block cursor 1&2 CROSSHAIR The X and Y portions of a CROSSHAIR cursor X portion Y portion BLOCK 4.2.4 Power Supply 4.2.4.1 Vcc, Vss These pins supply power to the ACRTC. Vee is specified as 5V + 10% (4.5V~5.5V). 54 HITACHI 4.2.5 Video Attributes The ACRTC outputs 20 bits of video attributes on MADO-MAD15 and MA16/ RAO-MA19/RA3. These attributes are output at the last cycle prior to the rising edge of HSYNC and should be latched externally. Thus, video attributes can be set on a raster by raster basis. MA19 MA18 MA17 MA16 MAD15 BLlNK2 BLlNK1 SPL2 SPL 1 HZ3 ) MAD12 MAD11 \ MAD8 MAD7 } ] Blink Split Screen Number Horizontal Zoom HZO HSD3 HSDO ATC7 1 j Horizontal Scroll Dot Attribute Code MADO ATCO Figure 4.2 Video Attributes HITACHI 55 4.2.5.1 Attribute Code (ATCO-ATC7:MADO':MAD7) These are user defined attributes. The programmed contents of the Attribute Control bits (ATR) of the Display Control Register (DCR) are output on these lines. 4.2.5.2 Horizontal Scroll Dot (HSDO-HSD3:MADS-MAD11) These are used in conjunction with external circuitry to implement smooth horizontal scroll. These lines contain the encoded start dot address which is used to control the external shift register load timing and data. HSD usually corresponds to the start dot address of the background screens. However, if the window smooth scroll (SWS) bit of OMR (Operation Mode Register) is set to 1, HSD outputs the start dot address of the window screen segment. 4.2.5.3 Horizontal Zoom Factor (HZO-HZ3:MAD12-MAD15) These lines output the encoded 0-16) horizontal zoom factor as stored in the Zoom Factor Register (ZFR). Horizontal zoom is accomplished by the ACRTC repeating a single display address and using the HZ outputs to control the external shift register clock. Horizontal zoom can only be applied to the Base screen. 4.2.5.4 Split Position (SPL 1-SPL2:MA 16-MA 17) These lines present the encoded information shQwing the enabled background screen currently being displayed by the ACRTC. SPL2 o o 1 1 SPLI o 1 o 1 Background Screen not enabled or displayed Base Screen Upper Screen Lower Screen 4.2.5.5 Blink (BLINK l-BLlNK2:MA lS-MA 19) The lines alternate from high to low periodically as defined in the Blink Control Register (BCR). the blink frequency is specified in units of 4 field times. A field is defined as the period between successive VSYNC pulses. These lines are used to implement character and screen blink. 56 HITACHI 5. REGISTER DESCRIPTION 5.1 Internal Register Access The ACRTC incorporates more than 200 bytes of internal Control registers and Control RAM which are accessible by the host MPU. The programming model is shown in figure 5.l. For the detailed register descriptions in this section, the following terminology is used. Hexadecimal numbers are denoted by a leading $ i.e. $1234, $FF, etc. For directly accessible registers, the register address is shown as 'rNN' where NN is interpreted as an 8 bit hexadecimal value. For example, the Zoom Factor Register address is OEA hexadecimal, so ZFRs register address is shown as 'rEA'. For FIFO accessible Drawing Parameter Registers, the register address is shown as 'PrNN'. For example, the Color Comparison Register is addressed as parameter register 2 hex, so the CMP register address is shown as 'Pr02'. Bit subfields within the register are denoted using decimal bit numbers in which bit 0 is the least significant bit and bit 15 the most significant bit. When the register diagram is shown, unused bits will be shaded. Unless stated otherwise, unused bits may be freely written with any value, and that value will be returned on subsequent reads of the register. HITACHI 57 o 7 I I Add ress Reg i ster Status Register o 15 I I .. - - - - - - - - - - - - - - - - - - - - - - - , ."./ Write FIFO ~ ________~I£'Q_E!lE".Y ______ _'~ I Command Control Register I I Operation Mode Register Display Control Register Raster Counter Horizontal Sync. Horizontal Display Vertical Sync. I I I \ " \ \'''::..\:-::::::-~........ ' " ""', -..L_ _ _ _ _ _ _ _ _ _ _----" \\ 'r-------------------, \ \ \ \ Read FIFO \ \ \ \ \ Vertical Display Split Screen Width I Blink Control Horizontal Window Display Command Register / Vertical Window Display Contro I Registe r Graphic Cursor Split Screen 0 Control (U pper Screen) Pattern RAM Spl it Screen 1 Control (Base Screen) Split Screen 2 Control (Lower Screen) Color 0 Color 1 Color Comparison Edge oor Mask Split Screen 3 Control (Window Screen) B lock Cursor Cursor De inition Zoom Facter "- Pattern RAM Control Drawing Paramete r Register Area Definition Read/Write Pointer Light Pen Address Drawing Pointer Current Pointer Figure 5.1 Programming Model 58 HITACHI I C R R/W Reg. No. S S 1 AR 0 0 0 1 SR 110 rOO 110 r02 110 r04 .!l!l. r06 ro8 o o DATA (L) DATA (H) Register Name Address Register Status Register Abbr. AR SR FE CCR OMR DCR ._-- FIFO Entry Command Control Operation Mode Display Control 15 114 113 /12 11 110 / 9 - Address ceRjARoTcEDlD'p:[RfF IRFR IWFR IWFE FE ABT PSE DM CDM DRC GBM ICRE IAilE'REEiLPEJRFE jRRElwRElwEE GAl RAMI I ACM I RSM MIS ISTR IAC!bY"S~H~~±_DSK ATR DSP I SEI I SED SE2 SE3 _L - - I r7E 1 110 110 110 110 0 rBO r82 r84 r86 r88 1~ ~ ~ ~ 110 rBE No USE and RESERVED Raster Count H.>rizontal §ync.______ Horizon.tal9isplay --_._Vertical Sync. Vertical Display ~~ BCR HWR VWR GCR ~ ~ 110 r9C - r9E ACRTC Work Area rAO - -J-(g. ~ -- -J-(g. ~ JLg. ~ 110 rCE .gg. ~ -J-(g. ~ -J-(g. ~ -J-(g. r"~EI -J-(g. ~ 110 110 ~ VC .. - BONI I E - --- ----;;- ----;;-;-_. - - LRAO I I SAOL - LRA2 - Block Cursor 1 BCURI ---- I - -J- - FRA2 SA2H/SRA2 - SDA3 CONI I FRA3 MW3 SA3H/SRA3 - .1 BCSRI I j BCERI I BCER2 BCAI BCUR2 r----- Bcwi------r----BCSR2 CM HZF SA1H/SRAl MW2 - -c;:-- - CDR ZFR LPAR I SA2L LRA3 BCA2 rES Cursor Definition rEA Zoom Factor ~ L.:ight P,n Address 1 rEE rFO 110 110 SAOH/SARO FRAI SDA2 - BCWI FRAO MWI SAIL SA3L Va ";Es' I rFE - SDAI - I MWO SDAO LRAI - Raster Addre.. 2 RAR2 Memory Width 2 MWR2 CHR Start Address 2 SAR2 Star 3 Raster Address 3 RAR3 Memory Width 3 MWR3 CHR I Start Addre.. 3 SAR3 110 rE2 110 rE4 Block Cursor 2 - CXS CYS eYE - '1/0 rDE JLg. ~ BOFF2 No USE and RESERVED BASE Raster Address 1 RARI (Back ~or.,,'./'!!dthl MWRI CHR Ground) Start Address 1 SARI ~ I HWW VWS VWW <:i _._-=_. - Window _------- BOFFI ---- f---$A-Ifo LOWER (back Ground) VSW J SPI SPO SP2 BON2 HWS UPPER ~~e!.~ 1 HITACHI 67 o Interrupt Enable Bit (IE: bit 7 - bit 0) An IRQ is generated when an event flag in the Status register and the corresponding interrupt enable bit are both set to 1. Bit Name Set to 1 to enable interrupt for... 7 Command Error CRE Command Error 6 5 Area Detect ARE Clipping and Hitting detection Command End CEE command Termination 4 Light Pen Detect LPE LPSTB Asserted 3 2 1 Read FIFO Full RFE Read FIFO Full Read FIFO Ready RRE Read FIFO Ready Write FIFO Ready WRE Write FIFO Ready 0 Write FIFO Empty WEE Write FIFO Empty 68 HITACHI 5.6 Operation Mode Register (OMR: r04-r05) High·order (r04) Low·order (r05) / \/ 15 14 13 12 MIS STR ACP WSS 11 10 CSK 9 8 DSK 7 6 RAM I5 I4 GAl 3 I2 ACM 1 I \ 0 RSM lAccess M~:.a~ er Scan Mode L-Graphic Address Increment Mode '-RAM Mode ~DISP Skew -Cursor Display Skew '-Window Smooth Scroll -Access Priority L...Start ,-,Ma~erlSlave Figure 5.6 Operation Mode Register (OMR) OMR determines major operating parameters and modes of the ACRTC. The 2 most significant bits (MIS and STR) are reset to 0 and all other bits are unaffected by RES. o MasterlSlave (MIS: bit 15) MIS defines whether the ACRTC operates as a master or slave when combined with other ACRTCs or video generating devices. MIS is reset to 0 during RES. When a single ACRTC is used, MIS should be set to 1 and the EXSYNC pin left open. MIS Functions o Slave Mode: EXSYNC is defined as an input. ACRTC internal operations are reset on the rising edge of the EXSYNC input. For non-interlace modes, the masters VSYNC should be connected to the EXSYNC input. For interlaced modes, the VSYNC of the masters odd field should be connected to the EXSYNC input. In the specific case of multiple ACRTC synchronization, the master and all slaves ACRTCs EXSYNC pins should be connected independent of interlace mode. 1 Master Mode: EXSYNC is defined as an output. For non-interlace modes, the ""EX"S""y"Nr.=C output timing is the same as VSYNC output timing. For interlace modes, the EXSYNC output timing is generated by the VSYNC output for the odd field. Note: HSYNC and VSYNC are always outputs regardless of the state of the MIS bit. HITACHI 69 o o Start (STR: bit 14) The STR bit is used to start and stop ACRTC operation. STR is reset to 0 by ACRTC hardware RES. Initializing of registers which control basic ACRTC operation should only be performed when STR is reset to O. STR Functions 0 ACRTC display control and drawing operations are halted. DISP, CUD, VSYNC, etc. go to the inactive high level. HSYNC is set to low level, and the DRAM refresh address is output on the MAD lines regardless of the state of the RAM mode bit (bit 7 of this register). The internal time base for CRT control signals is reset. 1 ACRTC starts display and drawing operations. Drawing commands halted when STR was reset to 0 are resumed. Drawing Access Priority (ACP: bit 13) ACP determines whether or not the ACRTC executes drawing operations on the frame buffer during the display refresh period. ACP Functions o Display priority mode: During the display period, the ACRTC halts drawing operations. thus, flashing due to simultaneous display and drawing access of the frame buffer is eliminated. Drawing operations are performed during horizontal and vertical retrace. If DRAM refresh mode is enabled (RAM bit is reset to 0) drawing is inhibited during the DRAM refresh period. In Interleaved Access Mode drawing can occur simultaneously with display, without 'flashing', since drawing and display access to the frame buffer is interleaved. In Superimposed Access Mode, flashless Background screen drawing may occur during idle Window display cycles. 1 Drawing priority mode: Drawing is performed during the display period. To reduce the 'flashing' effect caused by drawing-display contention the ACRTC may be programmed to drive the DISP signals to the inactive high level during drawing operations. If the RAM bit is reset to 0 (DRAM refresh mode), drawing is inhibited during the DRAM refresh period. If the RAM bit is set to 1 (Static RAM mode), drawing is also performed during the DRAM refresh period. Note: Since the last cycle of HSYNC low time is used as a video attribute output period, this cycle is never used for drawing regardless of the state of ACP and RAM bits. 70 HITACHI o Window Smooth Scroll (WSS: bit 12) WSS determines whether horizontal smooth scroll is applied to the Window screen. Window smooth scroll is only available in the Superimposed access mode. Therefore, if the Window screen is disabled, or the access mode is Single or Interleaved, WSS must be reset to O. The horizontal smooth scroll is implemented by using four bits of SDA (Start Dot Address) programmed in the Window Start Address Register (SAR3). These bits are output on MAD12MAD15 during the video attribute output period (last cycle of HSYNC low) and are used to control an external circuit which modifies the parallel to serial converter (shift register) timing. WSS Functions 0 Horizontal smooth scroll is not performed for the Window screen. One cycle Window screen prefetch does not occur. 1 Horizontal, smooth scroll is performed for the Window screen. The Window display refresh cycle starts one cycle earlier than programmed in the Horizontal Window Register (HWR) Horizontal Display Start (HDS) field. o Cursor Display Skew (CSK: bit 11 - bit 10) CSK defines the delay time for CUDt and CUD2 in units of memory cycle independent of frame buffer access mode (Le. Single, Interleaved or Superimposed). The CUD 1 and CUD2 skew allows compensating for delays due to frame buffer memory, character generator or other external logic access time. In the Crosshair cursor mode, CSK = 00 should not be used. CSK Functions 11 10 0 0 No skew. CUD2 output is always high. 0 1 1 1 CUD1, CUD2 are skewed by one memory cycle. 0 CUD1, CUD2 are skewed by two memory cycles. 1 CUD 1, CUD2 are skewed by three memory cycles. o DISP Skew (DSK: bit 9 - bit 8) DSK defines the DISP1, DISP2 delay in units of memory cycle independent frame buffer access mode. DSK 9 0 0 1 1 Functions 8 0 No skew. 1 DISP1, DISP2 are skewed by one memory cycle. 0 DISP 1, DISP2 are skewed by two memory cycles. 1 DISP1, DISP2 are skewed by three memory cycles. HITACHI 71 o RAM Mode (RAM: bit 7) The RAM bit determines whether or not the ACRTC will place an 8 bit DRAM refresh address on the MAD outputs during HSYNC low. In this context, HSYNC low time is also referred to as the 'DRAM refresh period' except for the last cycle of HSYNC low, which is referred to as the 'Attribute output period'. The refresh addressing mechanism is compatible with standard 16K, 64K and 256K bit DRAMs. RAM Functions 0 Dynamic RAM mode: During the DRAM refresh period, the ACRTC outputs the 8 bit refresh address on MAD. Note that the particular MAD lines used for the DRAM refresh address are determined by the Gaphic Address Increment (GAl) mode. The DRAM refresh address is decremented by 1 every refresh cycle. 1 Static RAM mode: No DRAM refresh address is placed on MAD. Drawing is performed during the DRAM refresh period (HSYNC low - except the attribute output period) regardless of the Access Priority (ACP) definition. 72 HITACHI o Graphic Address Increment mode (GAl: bit 6 - bit 4) As described earlier, using the Gaphic Bit Mode field in the Command Control Register (GBM in CCR), the number of physical frame butTer bits associated with a logical pixel can be selected as 1, 2, 4, 8 or 16. However, when the frame butTer organization is fixed as 16 bit words, if 1 bit per pixel GBM is specified, each word contains 16 logical pixels. If 4 bits per pixel GBM is specified, each word contains only 4 logical pixels. thus, a '16 color' display compared to a monochrome display will require a 2CLK input which is 4 times faster to achieve the same logical pixel resolution. A simple technique for solving this problem is to increase the number of frame buffer bits output for each display cycle. In the above example, if 4 words (64 bits) of frame buffer are accessed each display refresh cycle, the 'color' system 2CLK input is the same frequency as the 'monochrome' system which has equivalent logical pixel resolution. GAl accomodates this technique and other special cases by modifying the frame buffer address increment used for each successive graphic screen display access. GAl allows the display address increment to be 1, 2, 4 or 8 words 06-128 bits), o increment (display constant pattern) and increment every two display cycles (used when superimposing screens character and graphic screens). GAl applies only to graphic screen display accesses. Graphic screen drawing accesses and character screen accesses used a fixed increment of 1 word. GAl 6 0 0 0 0 5 0 0 4 1 1 1 1 Functions 0 Graphic, screen display address incremented by 1 every display cycle. 1 Graphic screen display address incremented by 2 every display cycle. 1 0 Graphic screen display address incremented by 4 every display cycle. 1 1 Graphic screen display address incremented by 8 every display cycle. 0 0 0 1 0 1 1 1 Graphic screen display address not incremented. Graphic screen display address incremented by 1 every two display cycles. HITACHI 73 o Access Mode (ACM: bit 3 - bit 2) The ACRTC provides three frame buffer access modes - Single, Interleaved and Superimposed. ACM Functions 3 2 0 x Single Access Mode: The frame buffer is accessed once every display cycle. The Window screen access has higher priority than overlapped Background screen accesses. When ACP = 0 (display priority mode), drawing is not performed during the display period. 1 0 Interleaved Access Mode (Dual Access Mode 0): The frame buffer is accessed twice every display cycle. Display and drawing cycles are interleaved during each phase of the display cycle. Even if ACP = 0 (Display priority mode), 'flashless' drawing will occur during display period. The Window screen has highest priority as in Single Access Mode. 1 1 Superimposed Access Mode (Dual Access Mode 1): The frame buffer is accessed twice every display cycle. The first phase accesses the Background screen, the second phase accesses the Window screen. In this case the Background and Window screens have equal priority, and are superimposed. Drawing is performed during the second phase in which the Window screen is not being displayed even when ACP = O. x = Don't care Note: In Interleaved and Superimposed access modes the horizontal display width of the Background screen and the Window screen must be even. Also. for these modes. the relation between the starting position of the horizontal display on the Background screen and the starting position of the horizontal display on the Window screen must be even number/even number or odd number/odd number. o Raster Scan Mode (RSM: bit 1 - bit 0) RSM selects the ACRTC raster scan mode. RSM Functions 1 0 0 0 0 1 1 0 Interlace Sync Mode 1 Interlace Sync & Video Mode Non-Interlace Mode 1 74 HITACHI 5.7 Display Control Register (OCR: r06-r07) High·order (r06) Low-order (r07) \/ 15 14 13 DSP SE1 12 SEO 11 10 9 SE2 8 \ 7161514131211To SE3 ATR L Attribute Control '--- Split Enable 3 (Window) '--- Split Enable 2 (Lower) ' - Split Enable 0 (Upper) -Split Enable 1 (Base) ' - DISP Signal Control Figure 5.7 Display Control Register (OCR) OCR controls ACRTC screen organization and 8 bits of user defined video attributes. Logically, the ACRTC has a Background screen (Upper, Base and Lower split screens) and a Window screen. When overlapping occurs, either the Window screen has priority (Single Access Mode, Interleaved Access Mode) or the Window screen and the Background screen have equal priority (Superimposed Access Mode). OCR allows screens to be enabled, disabled and blanked. If the Upper, Lower and Window screens are disabled, they need not be defined. The Base screen must always be defined. When screens are blanked (DISP timing output held inactive high), the display address is also inhibited. The ACRTC uses the idle frame buffer bus (MAOO-15 and MA16-19) for drawing operations. HITACHI 75 o DISP Signal Control (DSP: bit 15) DSP defines the output mode of the DISPI and DISP2 display timing signals. DSP Functions 0 DJSl5l is driven active low during the display period of the Background screen (combined horizontal and vertical display). DISP2 is controlled similarly for the Window screen. 1 o DISP1 is driven active low during the horizontal display of both the Background and Window screens. DISP2 is driven active low during the vertical display period of both the Background and Window screens. Thus, DTSP2 is high during vertical retrace. This allows another device which shares direct access to the frame buffer with the ACRTC to determine when the frame buffer is available. Split Enable 1 (SEl: bit 14) SEI allows the Base screen (screen 1) to be blanked. Drawing can occur when the Base screen is blanked since frame buffer display access is suppressed. Note that the Base screen parameters must be defined, even if the Base screen is always blanked. SE1 Functions 0 The ACRTC inhibits the display enable timing (DISP1 and/or DISP2) and display address outputs associated with the Base screen. The area of the Base screen, though blanked, remains on the CRT screen. 1 The ACRTC outputs display enable timing and display addresses for the Base screen. 76 HITACHI o Split Enable 0 (SEO: bit 13 - bit 12) SE~ allows the Upper split screen (screen 0) to be enabled, disabled and blanked. If always disabled, the Upper screen parameters need not be defined. When the Upper screen is blanked, drawing may occur since frame buffer display access is suppressed. SE~ Functions 13 12 0 x The ACRTC disables the Upper screen. Therefore, the Background screen contains two parts maximum - the Base and Lower screens. The Base screen is moved upward by the number of rasters in the disabled Upper screen. 1 0 The display enable timing outputs and display address outputs are inhibited for the Upper screen. The area of the Upper screen, though blanked, remains on the CRT screen. 1 1 The ACRTC outputs display enable timing and display addresses for the Upper screen. x = Don't care o Split Enable 2 (SE2: bit 11 - bit 10) SE2 allows the Lower split screen (screen 2) to be enabled, disabled and blanked. If always disabled, the Lower screen parameters need not be defined. When the Lower screen is blanked, drawing may occur since frame buffer display access is suppressed. SE2 x Functions 11 10 0 x The ACRTC disables the Lower screen. Therefore, the Background screen contains two parts maximum - the Base and Upper screens. 1 0 The display enable timing and display address outputs are inhibited for the Lower screen. The area of the Lower screen, though blanked, remains on the CRT screen. 1 1 The ACRTC outputs display enable timing and display addresses for the Lower screen. = Don't care HITACHI 77 o Split Enable 3 (SE3: bit 9 - bit 8) SE3 allows enabling, disabling and blanking of the Window screen (screen 3). When disabled or blanked, the overlapped Background screens are displayed. SE3 Functions 9 0 8 x The ACRTC disables the Window screen and overlapped Background screens (as defined by SE~, SE 1 and SE2) are displayed. If always disabled, the Window screen parameters need not be defined. For Superimposed access mode the second (Window) phase of the display cycle is not used. The ACRTC may execute drawing operations during this second phase. 1 0 The ACRTC disables the display enable timing and display address outputs for the Window screen. The area of the Window screen, though blanked, remains on the CRT. However, Window screen parameters must be defined. For superimposed access modes, the overlapped Background screens are displayed. For Single and Interleaved access modes, the ACRTC may perform drawing during the display time for the blanked Window screen. 1 1 The ACRTC outputs the display enable timing and display addresses for the Window screen. x = Don't care o Attribute Control (ATR: bit 7 - bit 0) These 8 bits, can be freely programmed as user defined video attributes. These bits are output on MAD7 - MADO prior to the rising edge of HSYNC . When programmed dynamically, ATR allows video attributes to be controlled on a raster by raster basis. 78 HITACHI 5.S Timing Control RAM (rSO-9F) These registers are used to define the overall screen and CRT timing signal characteristics, and parameters associated with the Base, Upper, Lower and Window screens. Raster Count Register (RCR) Horizontal Sync Register (HSR) Horizontal Display Register (HDR) Horizontal Window Register (HWR) Vertical Sync Register (VSR) Vertical Display Register (VD R) Split Screen Width Register (SSW) Vertical Window Display Register (VWR) Blink Control Register (BCR) Graphic Cursor Register (GCR) HITACHI 79 5.S.1 Raster Count Register (RCR: rSO-rS1) High·order (r80) Low·order (r81) \ o Raster Count Figure 5.8 Raster Count Register (RCR) RCR is a read-only register which contains the number of the raster currently being scanned on the CRT. Note that the initial RCR value after hardware RES is undefined. If RCR read operation is desired, the HSW (Horizontal Sync Width) should be set greater than or equal to 3. RCR should only be read when HSYNC is high. The high order 4 bits of RCR are always O. RCR is updated depending on the ACRTC raster scan modes as shown. Scan Mode Functions Non-Interlace RCR starts counting at 0 and increments by 1 sequentially. Interlace Sync RCR starts counting at 0 and increments by 1 sequentially in both the even and odd fields. Because a dummy raster is added to the even field. the maximum raster number for the even field is one greater than that for the odd field. Interlace Sync and Video RCR starts counting at 0 in the even field and at 1 in the odd field. and increments by 2 sequentially in both fields. The even field always has even raster numbers and the odd field always has odd raster numbers. A dummy raster is added to the even field as in the Interlace Sync Mode. 80 HITACHI 5.8.2 Horizontal Sync Register (HSR: r82-r83l Low-order (r83) High-order (r82) / \/ \ o 15 Horizontal Sync Width Horizontal Cycle Figure 5.9 Horizontal Sync Register (HSR) o HSR defines the Horizontal Cycle (HC) and Horizontal Sync Width (HSW). Horizontal Cycle (HC: bit 15 - bit 8) HC specifies the horizontal scan time (including the horizontal retrace period) in units of memory cycles. HC is set depending on the specifications of the CRT display device. If H memory cycles are to be specified, HC should be set to H-l. When using interlaced scan modes, H should be an even number. H C LSB MSB Display (Memory cycle No.) 00000000 00000001 2 ) ~ 1 1 111110 11111111 1 255 256 HITACHI 81 o Horizontal Sync Width (HSW: bit 4 - bit 0) HSW specifies the HSYNC active low time in unis of memory cycles. HSW is set depending on the specifications of the CRT display device. Valid values for HSW are 2 - 31. When using the RCR register, HSW must be 3 or greater. When the ACRTC DRAM refresh feature is used, DRAM refresh timing should be factored into the choice of HSW. HSW MSB LSB 000,00 00001 00010 000 1 1 ~ 1 1 1 10 1 1 1 1 1 *' Pulse width (Memory cycle No.) *1 *2 2 3 ~ 30 31 Not used. *2 Two memory cycles are assummed. 82 HITACHI 5.8.3 Horizontal Display Register (HDR: r84-r851 Horizontal Window Display Register (HWR: r92-r931 High-order (r84) Low-order (r85) / \ o 15 HOW HDS Horizontal Display Width Horizontal Display Start Figure 5.10 Horizontal Display Register (HDRI High-order (r92) Low-order (r93) / \ o 15 HWW HWS Horizontal Window Width Horizontal Window Start Figure 5.11 Horizontal Window Display Register (HWR) HDR specifies the horizontal display start position and horizontal display width in units of memory cycles. HWR specifies the horizontal Window start position and horizontal Window width in units of memory cycles. HITACHI 83 o o Horizontal Display Start (HDS: r84) HOS defines the interval between the rising edge of HSYNC (Horizontal Front Porch) and the horizontal display starting point in units of memory cycles. If the Horizontal Display Start is HS memory cycles, HOS should be set to HS-l. Horizontal Window Start (HWS: r92) HWS defines the interval between the rising edge of HSYNC and the horizontal Window display starting point in units of memory cycles. If the Horizontal Window Start is HS memory cycles, HWS should be ,set to HS-l. HDS/HWS MSB LSB 00000000 00000001 1 2 ) ~ 111111 10 11111111 o o Display width (Memory cycle No.! 255 256 Horizontal Display Width (HOW: r85) HOW defines the display period for one raster in units of memory cycles. If the Horizontal Display Width is HW memory cycles, HOW should be set to HW-l. Horizontal Window Width (HWW: r93) HWW defines the Window display period for one raster in units of memory cycles. If the Horizontal Window Width is HW memory cycles, HWW should be set to HW-l. HDW/HWW MSB LSB 00000000 00000001 1 2 ) ) 111 11110 111 11111 84 HITACHI Display width (Memory cycle No.! 255 256 5.8.4 Vertical Sync Register (VSR: r86-r87) High-order (r86) Low-order (r87) \ o Vertical Cycle Figure 5.12 Vertical Sync Register (VSR) VSR defines the period of the vertical scan cycle in units of rasters. Vertical Cycle (VC: bit 11 - bit 0) VC defines the vertical scan cycle period (including vertical retrace) in units of rasters. VC is set depending on the specifications of the CRT display device. The way VC is programmed depends on the ACRTC raster scan mode. VC should be programmed with a non-zero value. Non-Interlace Mode When the number of rasters in one frame is V, VC is set to V. . Interlace Sync Mode When the number of rasters in one field (even or odd) is V, VC is set to V. The total rasters in one frame is 2V+ 1 due to one dummy raster operation. . Interlace Sync & Video Mode When the number of rasters in one frame (even field + odd field + dummy raster) is V, VC is set to V. o HITACHI 85 v C MSB LSB Vertical cycle (Number of rasters) 000000000000 000000000001 000000000010 ~ 1 2 \ 1. 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 * VC = * 4094 4095 0 cannot be used. 5.8.5 Vertical Display Register (VDR: r88-r89) High-order (r88) Low-order (r8g) \ / o 15 Vertical Sync Width Vertical Display Start Figure 5.13 Vertical Display Register (VDR) VDR defines vertical sync width (VSYNC low period) and vertical display start and width in units of rasters. 86 HITACHI o Vertical Sync Width (VSW: r89 bit 4 - bit 0) VSW defines VSYNC low pulse width in units of rasters. VSW is set depending on the CRT display device specification. VSW should be set to a non-zero value. vsw MSB LSB Pulse width (Number of raster) 00000 00001 00010 2 ~ ) 11110 11111 * VSW * 1 30 31 = 0 cannot be used. HITACHI 87 o Vertical Display Start (VDS: r88) VDS defines the period from the rising edge of VSYNC to the vertical display start position in units of rasters. If the vertical display start position is the VS raster, VDS is set to VS-l. The way to program VDS depends on ACRTC raster scan modes as described for VSR (r86-r87). VDS MSB lSB 00000000 00000001 ) 1 1 111110 1 1 111 1 1 1 88 HITACHI Display start (Number of rasters) 1 2 ~ 255 256 5.8.6 Vertical Window Display Register (VWR: r94-r97) High-order (r94) Low-order (r95) \ o Vertical Window Start High-order (r96) Low-order (r97) \ o Vertical Window Width Figure 5.14 Vertical Window Display Register (VWR) VWR is a read/write register that defines the vertical Window start position and width in units of rasters. o Vertical Window Start (VWS: r94-r95) VWS defines the period from the rising edge of VSYNC to the vertical Window start position in units of rasters. When the vertical Window start position is the VS raster, VWS is set to VS-l. Note that VWS must be greater than or equal to VDS. VWS LSB MSB 000000000000 000000000001 ) 1 1 1 1 1 1 1 1 1 1 10 1 1 1 1 1 111 1 1 1 1 Display start position (Number of rasters) 1 2 ~ 4095 4096 HITACHI 89 o Vertical Window Width (VWW: r96-r97) VWW defines the vertical display period of the Window screen in units of rasters. When the vertical window width is VW rasters, VWW is set to'VW. VWW MSB LSB Display width (Number of rasters) 000000000000 000000000001 000000000010 * 1 2 ~ ) 11111 1 1 1 1 1 1 0 111111111111 4094 4095 • VWW = 0 cannot be used. 5.S.7 Split Screen Width Register (SSW: rSA-rSF) High-order (r8A) Low-order (r8B) \ o Base Screen Width High-order (r8G) Low-order (r80) \ Upper Screen Width High-order (r8E) Low-order (r8F) \ o Lower Screen Width Figure 5.15 Split Screen Width Register (SSW) SSW defines the vertical width of·the Upper (split screen 0), Base (split screen 1) and Lower (split screen 2) screens. 90 HITACHI o Split Screen Width (SPO: r8C-r8D bit 11 - bit 0) (SPl: r8A-r8B bit 11 - bit 0) (SP2: r8E-r8F bit 11 - bit 0) SPO, SPI and SP2 define the vertical display period of the Upper, Base and Lower screens respectively in units of rasters. If the vertical screen width is SW rasters, SPO/SPl/SP2 are set to SW. Display width (Number of rasters) SPO/SP1/SP2 LSB MSB * 000000000000 000000000001 000000000010 1 2 ~ ) 1 1 1 1 1 1 111110 1 1 1 1 1 1 1 1 1 1 1 1 * SPO/SP 1/SP2 = 4094 4095 0 cannot be used. 5.8.8 Blink Control Register (BCR: r90-r91) Low-order (r91) High-order (r90) \ o BON 1 Blink ON 1 BOFF 1 BON 2 Blink OFF 1 BOFF 2 Blink ON 2 Blink OFF 2 Figure 5.16 Blink Control Register (BCR) BCR defines the blink on and ofT period for the BLINKI and BLINK2 video attributes. BLINKI and BLINK2 are output on MA18 and MA19 during each rasters video attribute output cycle. HITACHI 91 o Blink ON (BONl: r90 bit 15 - bit 12) (BON2: r91 bit 7 - bit 4) BON(1I2) defines the BLINK(1I2) attribute active high (ON) period. The unit is 4 field periods. BLINK(1I2) is always low (OFF) when BON(1/2) = 0 is programmed. 15 14 13 12 Blink "High" level (Field) 0 0 0 0 * 0 0 0 0 * 0 0 0 1 8 0 0 0 1 8 0 0 1 0 12 0 0 1 0 12 0 0 1 1 16 0 0 1 1 16 0 1 0 0 20 0 1 0 0 20 0 1 0 1 24 0 1 0 1 24 0 1 1 0 28 0 1 1 0 28 0 1 1 1 32 0 1 1 1 32 1 0 0 0 36 1 0 0 0 36 1 0 0 1 40 1 0 0 1 40 1 0 1 0 44 1 0 1 0 44 48 1 0 1 1 48 1 0 0 52 BON1 1 0 1 1 BON2 7 6 5 4 Blink "High" level (Field) 1 1 0 0 52 1 1 1 0 1 56 1 1 0 1 56 1 1 1 0 60 1 1 1 0 60 1 1 1 1 64 1 1 1 1 64 * BLINK is always "Low" 92 HITACHI o Blink OFF (BOFFl: r90 bit 11 - bit 8) (BOFF2: r91 bit 3 - bit 0) BOFF(1/2) defines the BLINK(1/2) attribute active low (OFF) period. the unit is 4 field periods. BLINK(112) is always high (ON) when BON(112) =1= 0 and BOFF(1I2) = 0 are programmed. 11 10 9 8 Blink "Low" level (Field) 0 0 0 0 * 0 0 0 0 * 0 0 0 1 8 0 0 0 1 8 0 0 1 0 12 0 0 1 0 12 0 0 1 1 16 0 0 1 1 16 0 1 0 0 20 0 1 0 0 20 0 1 0 1 24 0 1 0 1 24 0 1 1 0 28 0 1 1 0 28 0 1 1 1 32 0 1 1 1 32 1 0 0 0 36 1 0 0 0 36 1 0 0 1 40 1 0 0 1 40 1 0 1 0 44 1 0 1 0 44 1 0 1 1 48 1 0 1 1 48 1 1 0 0 52 1 1 0 0 52 1 1 0 1 56 1 1 0 1 56 1 1 1 0 60 1 1 1 60 1 1 1 1 64 1 1 1 0 1 BOFF1 * BOFF2 3 2 1 0 Blink "Low" level (Field) 64 In the case of BON(1/2) =1=0, BLlNK(1/2) will always become "HIGH" level. HITACHI 93 5.8.9 Graphic Cursor Register (GCR: r98-r9Dl High-order (r98) Low-order (r99) / \ o 15 CXE CXS Cursor X End High-order (r9A) Cursor X Start Low-order (r98) \ o Cursor Y Start High-order (r9C) Low-order (r9D) \ o Cursor Y End .Figure 5.17 Graphic Cursor Register (GCR) GCR defines the horizontal and vertical start and end positions for displaying a graphic cursor. Cursor X Start (CXS: r99) CXS defines the horizontal cursor start position from the falling edge of HSYNC in units of memory cycles. Cursor X End (CXE: r98) CXE defines the horizontal cursor end position from the falling edge of HSYNC in units of memory cycles. Cursor Y Start (CYS: r9A, r9B bit 11 - bit 0) CYS defines the vertical cursor start position from the rising edge of VSYNC in units of rasters. Cursor Y End (CYE: r9C, r9D bit 11 - bit 0) CYE defines the vertical cursor end position from the rising edge of VSYNC in units of rasters. o o o o 94 HITACHI 5.S.10 ACRTC Working Register {r9E-9F} Internal ACRTC work area. The host MPU must never access this register. HITACHI 95 5.9 Display Control RAM (rCO-rEF) The Display Control RAM are registers containing parameters used by the ACRIC address generation logic. There are four sets of Raster Address, Memory Width and Start Address registers providing independent control for each of the four logical screens (Upper, Base, Lower and Window). Also, the Cursor Definition Register contains information for two separate cursors. Raster Address Registers (RARO-RAR3) Memory Width Registers (MWRO-MWR3) Start Address Registers (SARO-SAR3) Block Cursor Register (BCR) Cursor Definition Register (CDR) Zoom Factor Register (ZFR) Light Pen Address Register (LP AR) 96 HITACHI 5.S.1 Raster Address Register (RARO: rCO-rC 1) (RAR 1 : rC8-rCS) (RAR2: rOO-r01) (RAR3: r08-rOS) High-order Low-order / \ o Last Raster Address Raster Raster Raster Raster address address address address register register register register 0 1 2 3 : : : : LRAO LRA1 LRA2 LRA3 (rCOl. (rCB), (rDOl. (rOBl. First Raster Address F RAO (r C1) FRA1 (rCg) FRA2 (rD1) F RA3 (rOg) Upper Screen Base Screen Lower Screen Window Figure 5.18 Raster Address Register (RAR) RAR specifies the raster addressing per character row (including line spacing) for character screens (CHR = high). RARO-3 apply to screens 0-3, the Upper, Base, Lower and Window screens respectively. First Raster Address (FRA: bit 4 - bit 0) FRA determine~ the first raster line address of the character row, and can be set to any value between 0 and 31. o FRA 413121110 0 0 0 0 0 0 0 0 0 1 ) 1 1 1 1 1 1 Raster address 0 1 ) 1 1 0 1 30 31 HITACHI 97 o Last Raster Address (LRA: bit 12 - bit 8) LRA determines the last raster line address of the character row, and can be set to any value between 0 and 31. LRA 121111101918 0 0 0 0 0 0 0 0 0 1 ) 1 1 1 1 1 1 Raster address 0 1 ) 1 1 0 1 30 31 The number of raster lines per character row is determined by the relation between FRA and LRA and also depends on the raster scan mode. In the following examples, FRA (=3) represents the first raster address in the even field. Note that the relation between FRA and LRA is not restricted. FRA can be less, equal or greater than LRA as shown below. In this example, non-interlace mode is used. 98 HITACHI i) Non-interlace mode ii) Interlace sync mode 03 - - - - FRA:03 Odd field Even field 03 FRA:03 04 LRA:08 04 -----03 LRA:08 05 Number of rasters:6 ---- -- 04 06---05 _____ 05 Number of rasters:12 07---06 _____ 06 08---07 _____ 07 08 __ ---08 iii) Interlace sync & Video mode Odd field Even field 03 _____ 04 05-------06 07 _____ 08 FRA 03 04 05 06 07 08 < LRA FRA LRA FRA:03 LRA:08 Number of rasters:6 FRA = LRA FRA 10 LRA FRA> LRA 30 31 00 01 02 03 FRA LRA HITACHI 99 5.9.2 Memory Width Register (MWRO: rC2-rC3) (MWR1: rCA-rCB) (MWR2: rD2-rD3) (MWR3: rDA-rDB) Low-order High-order \ / o MW Memory Width Character /G raph ic Memory Width Memory Width Memory Width Memory Width Register 0 Register 1 Register 2 Register 3 rC2 rCA r02 rOA rC3: rCB : r03: rOB: Upper Screen Base Screen Lower Screen Window Screen Figure 5.19 Memory Width Register (MWR) MWR defines the number of physical 16 bit frame buffer words which comprise all logical pixel X addresses for a single Y address. For example, if a screen is defined with 1024 logical pixel range in the X direction (X may very from 0 to 1023), and 4 bits per pixel are assumed, that screens MWR value should be 256. MWR also determines whether the defined screen is a Character (CHR = high) or Graphic (CHR = low) screen. MWRO-3 apply to screens 0-3, the Upper, Base, Lower and Window screen respectively. MWR should be greater than or equal to Horizontal Display Width (HOW r85). MWR must be greater than HDW to perform horizontal smooth scroll. MWR maximum value is 4096. Character/Graphic (CHR: bit 15) o CHR Functions 0 The screen is defined as GRAPHIC 1 The screen is defined as CHARACTER 100 HITACHI o Memory Width (MW: bit 11 - bit 0) M W 0 11 Memory width (Number of words) 000000000000 000000000001 0 1 ) ) 111111111110 1 1 1 1 1 1 1 1 1 111 4094 4095 HITACHI 101 5.9.3 Start Address Register (SARO: rC4-rC7) (SAR1: rCC-rCF) (SAR2: rD4-rD7) (SAR3: rDC-rDF) Low-order High-order / \ o Start Address High/Start Raster Address High-order Low-order / \ o 15 SAL Start Address Low Start Address Start Address Start Address Start Address Register 0: Register 1: Register 2: Register 3: Upper Screen Base Screen Lower Screen Window Screen Figure 5.20 Start Address Register (SAR) SAR defines the first frame buffer address for each screen. SARO-3 apply to screens 0-3, the Upper, Base, Lower and Window screens respectively. Screens defined as Character have a 64K by 16 bit physical address space. Screens defined as Graphic have a 1M by 16 bit physical address space. In either case, SAR can take on any address. Frame Buffer addresses will 'wraparound' to 0 when the physical address space limit is reached independent of split screen position. 102 HITACHI o o Start Address Low (SAL: bit 15 - bit 0) For Character screens, SAL contains the 16 bit start address. For Graphic screens, SAL contains the least significant 16 bits of the 20 bit start address. Start Address High (SAH: bit 3 - bit 0) Start Raster Address (SRA: bit 4 - bit 0) For Character screens, SRA provides the 5 bit (0-31) start raster address. j) Character Screen 04 _ _ _ _ SRA 05 _ _ __ 06 _ _ __ 07 LRA 02 FRA 03 _ _ __ 04 _ _ __ 05 _ _ __ 06 _ _ __ 07 LRA 02 FRA For Graphic screens, SAH provides the most significant 4 bits of the 20 bit start address. jj) Graphic Screen 19 15 0 I SAH I SAL I Increment or decrement of SRA provides vertical smooth scroll with nu additional external hardware. HITACHI 103 o Start Dot Address (SDA: bit 11 - bit 8) SDA is used to define a start dot horizontal offset (0-15). the contents of SDA are output on HSDO-3 (MAD8-11) during the video attribute output cycle of each horizontal scan. External circuitry which controls the parallel-serial converter (shift register) load and clock based on SDA and the corresponding HSD outputs allows horizontal smooth scroll for both Character and Graphic screens. 5.9.4 Block Cursor Register (BCUR: rEO-rE7) Low-order High-order / \/ \ 1511411311211111019 I 8T 716T51413I 211 10 BCA ~ Character Cursor Address High-order / Low-order \ o Block Cursor Register 1 (BCUR1) rEO, rE1, rE2, rE3 Block Cursor Register 2 (BCU R2) rE4, rE5, rE6, rE7 Block Cursor End Raster Block Cursor Width Figure 5.21 Block Cursor Register (BCUR) BCUR defines the block cursor location (frame buffer physical memory address), start and end raster and block cursor length for two independent cursors. Depending on cursor mode, the ACRTC CUD1 and CUD2 lines can support the simultaneous display of both block cursors. Should two (or more) screens be defined to contain the same frame buffer memory address, if the block cursor is located at that address, it will be displayed on both screens. Block Cursor Address (BCA1: rE2-rE3) (BCA2: rE6-rE7) BCA defines the 16 bit address for the block cursor. Note that the block cursor is only enabled for Character screens (CHR = high). o 104 HITACHI o o Block Cursor Start Raster (BCSR: bit 12 - bit 8) BCSR determines the 5 bit block cursor start raster address (0-31). Block Cursor Width (BCW: bit 15 - bit 13) BCW defines the block cursor width 0-8) in units of memory cycles. BCW 151 14 113 0 0 0 0 0 1 o 1 1 J 1 2111 10J 9 0 0 0 0 0 0 0 0 1 2 ) ~ 1 1 BCSR Cursor width (Memory cycle) 0 1 1 1 7 ~ 1 1 1 1 1 1 I8 Raster address 0 1 0 1 0 1 30 31 ~ 8 Block Cursor End Raster (BCER: bit 4 - bit 0) BCER determines the 5 bit block cursor end raster address (0-31). BCER 4 0 0 I 3 I 2 I 1 I0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 0 1 30 31 ) 1 1 Raster address ~ HITACHI 105 Based on FRA, LRA, BCSR and BCER, the block cursor can take on a number of different configurations as shown below. FRA ~ LRA (FRA:02. LRA:08) 02 03 04 05 06 07 08 •• ••• ••• •• ••• ••• FRA 30 31 00 01 02 03 04 30 31 00 01 02 03 04 > BCSR =BCER 02 BCSR: 04 BCER:07 BCSR : 07 BCER : 07 08 • • •• 08 ••••• ••• • ••• •• •••• •• BCSR> BCER BCSR: 07 BCER: 04 LRA (FRA:30. LRA:04) •• •• •• •• •••• •• ••• ••• •• •• •• •• ••• • 106 HITACHI BCSR BCER BCSR: 03 BCER: 01 BCSR >BCER BCSR : 31 BCER : 02 5.S.5 Cursor Definition Register (CDR: rE8-rES) Low-order (rEg) High-order (rEB) / \ o 15 Cursor Off2 Cursor Off1 Cursor On1 Cursor Mode Figure 5.22 Cursor Definition Register CDR defines the cursor types and the way in which the CUDl and CUD2 outputs are controlled. Depending on CDR, up to three cursors may be simultaneously displayed. Cursor types are defined as follows. BLOCK - The standard 'block' type (including underline) cursor typically used on alphanumeric displays. GRAPHIC - The ACRTC may generate a rectangular cursor area of arbitrary X and Y dimension. Normally, this is used to enable an external cursor bit map circuit. In this case, the cursor may take on any user defined graphic shape. CROSSHAIR - The ACRTC can display a crosshair cursor. The X and Y (horizontal and vertical) dimensions are independently programmable. HITACHI 107 o Cursor Mode (CM: rE8 bit 15 - bit 14) CM defines the type of cursor(s) to be displayed and the way in which the CUDI and CUD2 outputs are interpreted. CM Functions 15 14 0 x Block Cursor Mode: Block cursor 1 (defined in BCR1) is output on CUD1. Block cursor 2 (defined in BCR2) is 'output on CUD2. The Graphic cursor (defined in GCR) is not used. 1 0 Graphic Cursor Mode: Graphic Cursor (GCR) is output on CUD1. Block cursor 1 and 2 are combined and output on CUD2. 1 1 Crosshair Cursor Mode: The horizontal element is output on CUD 1 . The 'vertical element is output on CUD2. The Block cursor (BCR) is not used. x = Don't care. 108 HITACHI I I I o Cursor ON (CONI: rE8 bit 13 - bit 11) (CON2: rE9 bit 5 - bit 3) Cursor OFF (COFFl: rE8 bit 10 - bit 8) (COFF2: rE9 bit 2 - bit 0) CON and COFF determine the cursor blink timing. CONlICOFFl apply to CUD 1 and CON2/COFF2 apply to CUD2. The unit time is 4 field periods. In Crosshair Cursor Mode, CONlICOFFl is used for blink timing and CON21 COFF2 are not used. CON1 13 12 11 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 * Blink "High" level (Field period) * 8 12 16 20 24 28 32 10 9 8 Blink "Low" level (Field period) 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 8 12 16 20 24 28 32 * 5 4 3 Blink "High" level (Field period) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0 1 8 12 16 20 24 28 32 * Cursor is output at "Low" level. COFF1 0 0 1 1 0 0 1 1 CON2 * COFF2 2 1 0 Blink "Low" level (Field period) 0 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 8 12 16 20 24 28 32 * If "CON= 000" is set, cursor is output at "High" level. HITACHI 109 5.9.6 Zoom Factor Register (ZFR: rEA) High·order (rEA) Low-order (rEB) / 15 Horizontal Zoom Factor Figure 5.23 Zoom Factor Register (ZFR) ZFR determines the horizontal (memory cycle) and vertical (raster) multipliers (1 to 16) for zooming up. Zooming can only be applied to the Base screen. HZF and VZF should be set to 0 for no-zoom, and $F for 16 times zoom. 110 HITACHI o Horizontal Zoom Factor (HZF: bit 15 - bit 12) HZF defines the horizontal zoom factor in units of memory cycles. The ACRTC will output a same display address by HZF times. HZF is output as video attributes on MAD 12-15 lines for use by an external circuit which controls shift clock timing. HZF 15 14 13 12 0 0 1 1 o 0 0 0 0 ~ 1 1 1 1 0 1 Factor of zooming up in the horizontal director (Magnitude) 1 2 ) 0 1 15 16 Vertical Zoom Factor (VZF: bit 11 - bit 8) VZF defines the vertical zoom factor. The ACR TC performs the vertical zoom by modifying its frame butTer address (Graphic screens) or raster address (Character screens) so that multiples of the same raster data are displayed. VZF 111101918 0 0 0 0 0 0 0 1 1 2 1 1 0 1 15 16 ~ ) 1 1 1 1 Factor of zooming up in the vertical director (Magnitude) HITACHI 111 5.9.7 Light Pen Address Register (LPAR: rEC-rEF) High·order (rEe) / Low-order (rED) \/ \ o Light Pen Address "High" High·order (rEE) Low-order (rEF) / \ o 15 LPAL Light Pen Address" Low" Figure 5.24 Light Pen Address Register (LPAR) LP AR is a read only register. When the ACRTC LPSTB input is asserted, the current display address is latched into LP AR. The value in LP AR will differ from the actual display address under the light pen depending on various hardware delay times. Thus, the LP AR value should be adjusted by MPU software depending on system configuration. In Superimposed access mode, light pen strobes which occur within a superimposed Window/Background display cause the Background address to be latched. Character/Graphic (CHR: rED bit 7) CHR indicates whether the latched display address corresponds to a screen defined as Character or Graphic. o CHR 0 1 o o Functions LPAR contains Graphic screen address LPAR contains Character screen address Light Pen Address High (LPAH: rED bit 3 - bit 0) LPAH is only valid if CHR = 0 and contains the most significant 4 bits of the 20 bit Graphic screen display address. Light Pen Address Low (LP AL: rEE-rEF) If CHR = 0, LPAL contains the least significant 16 bits of the 20 bit Graphic screen display address. If CHR = 1, LPAL contains the 16 bit Character screen display address. 112 HITACHI 5.10 Drawing Control Registers The ACRTC refers to a number of registers during graphic drawing operations. a) Pattern RAM b) Drawing Parameter Registers Color 0 Register (CLO) Color 1 Register (CLl) Color Comparison Register (CCMP) Edge Color Register (EDG) Mask Register (MASK) Pattern RAM Control Register (PRC) Area Definition Register (AD R) Read/Write Pointer (RWP) Drawing Pointer (DP) Current Pointer (CP) The Pattern RAM is accessed using the Read and Write Pattern (RPTN, WPTN) commands. The Drawing Parameter Registers are accessed using the Read and Write Parameter Register (RPR, WPR) commands. 5.10.1 Pattern RAM The ACRTC includes 32 byte pattern RAM. The Pattern RAM is used for predefining data for the graphic drawing operations. A 16 by 16 bit pattern (or 16 sets of 16 by 1 bit) can be stored in the Pattern RAM as a binary representation of screen data. In this case, a two entry color 'palette' corresponding to 0 and 1 data values is defined using the Color 0 (CLO) and Color 1 (CLl) registers. To store color patterns in the Pattern RAM it is divided into four equal segments of either 4 by 4 bit patterns or 4 sets of 4 by 1 bit patterns. In this case, during drawing the color coded contents of the Pattern RAM are directly written to the frame buffer. The particular segment used is defined by the Pattern RAM Control register (PRC). When multiple drawing commands use a common pattern, pattern continuity can be achieved by adjusting the pattern scanning pointer. HITACHI 113 5.10.2 Drawing Parameter Registers Register No. Read/ Write Name of Register Abbr. Data (H) Pattem RAM Control Pr07 Pr08 RIW ADR Area Definition •• PrOB PrOc RIW PrOD PrOE R Prl1 Pr12 RWP .................... PrOF Prl0 Read Write Pointer R Pr13 Pr14 Pr15 Drawing Pointer Current Pointer •• DP CP .................... • R .... Register readable by a Read Parameter Register (RPR) command W .... Register writable by a Write Parameter Register (WPR) command . - .... Access is not allowed ~ .... Always set to "0" ••....... Set binary complements for negative values of X and Y axis. Figure 5.25 Drawing Parameter Registers 114 HITACHI Data (L) 5.10.2.1 Color 0 Register (ClO: PrOO) 115 1,4113112111 1,0 I 9 PrOO I I 8 I 7 I 6 I 5I 4I 3I 2 I 1 I 0 CLO Figure 5.26 Color Register 0 (CLO) When logical drawing data = 0 in the pattern RAM, the contents of CLO are stored in the frame buffer. 5.10.2.2 Color 1 Register (Cl1: Pr01) PrOl I 1'51141'3112111 1'0 I 9 I 8CLI17 I 6 I 5I 4I 3I 2 I 1 I 0 Figure 5.27 Color Register 1 (CL 1 ) When logical drawing data = I in the pattern RAM, the contents of CLI are stored in the frame buffer. HITACHI 115 5.10.2.3 Color Comparison Register (CCMP: Pr02) o Pr02 CCMP Figure 5.28 Color Comparison Register (CCMP) CCMP defines a comparison color for use with conditional drawing operations. Conditional drawing applies various logical comparisons between the drawing data and CCMP to determine if drawing should occur. 5.10.2.4 Edge Color Register (EDG: Pr03) 1'5 114 1,3 112 111 110 I 9 1 8 1 7 1 6 1 51 4 1 3 1 2 1 Figure 5.29 Edge Color Register (EDG) EDG defines the boundary edge color for use by the PAINT command. In one mode, the edge is defined as the color contained in EDG. In another mode, the edge is defined as any color except the color contained in EDG. 116 HITACHI 5.10.2.5 Mask Register (MASK: Pr04) Pr04 1'5 1'41'31'21" 110 I 9 I 8 I 7 I 6 I 5 I 4I 3I 2l' MASK I 1 0 Figure 5.30 Mask Register (MASK) When performing data transfer and drawing of the frame buffer, MASK is used to mask bits upon which drawing and other logical operations should not be performed. If MASK bit is 0, the corresponding frame buffer bit is excluded from logic operation. Note: Only DMOD, MOD, SCLR and SCPY command can use the MASK Register. HITACHI 117 5.10.2.6 Pattern RAM Control Register (PRC: Pr05 - Pr07) o 15 Pr05 PZCY PPY PPX PZCS Pattern Zoom Count X Pattern Point X Pattern Zoom Count Y Pattern Point Y 15114113112 11 10 9 8 0 0 0 0 7161514 3 2 1 0 0 0 Pr06 PSY 0 0 L Pattern Start X PSX L Pattern Start Y o 15 Pr07 PEY PZY PZX PEX Pattern Zoom Y Pattern End Y Pattern Zoom X Pattern End X Figure 5.31 Pattern RAM Control Register (PRC) PRe specifies the size of the patterns used for drawing and the start point within the Pattern RAM for the pattern scan. The pattern size can be independently specified in the X and Y dimensions (maximum 16 by 16 bits). 118 HITACHI o o o o o Pattern Start X (PSX: Pr06 bit 7 - bit 4) Pattern Start Y (PSY: Pr06 bit 15 - bit 12) PSX and PSY specify the pattern scan starting point horizontal and vertical addresses respectively. These should be set to between 0-15 for Color Register indirect drawing and between 0-3 for Pattern RAM direct drawing. Pattern End X (PEX: Pr07 bit 7 - bit 4) Pattern End Y (PEY: Pr07 bit 15 - bit 8) PEX and PEY specify the pattern scan ending point horizontal and vertical addresses respectively. These should be set to between 0-15 for Color Register indirect drawing and between 0-3 for Pattern RAM direct drawing. Pattern Zoom X (PZX: Pr07 bit 3 - bit 0) Pattern Zoom Y (PZY: Pr07 bit 11 - bit 8) PZX and PZY specify the magnification coefficient applied to the contents of the Pattern RAM. PZX, PZY = 0 specifies by 1 magnification (no magnification) while PZX, PZY = $F specifies by 16 magnification. Pattern Zoom Count X (PZCX: Pr05 bit 3 - bit 0) Pattern Zoom Count Y (PZCY: Pr05 bit 11 - bit 8) PZCX and PZCY specify the initial magnification counter values in the horizontal and vertical dimensions respectively. Normally, PZCX and PZCY should be set to O. Pattern Pointer X (PPX: Pr05 bit 7 - bit 4) Pattern Pointer Y (PPY: Pr05 bit 15 - bit 8) The current reference point within the Pattern RAM is specified by PPX and PPY. When using PPX, PPY to define a pattern scan starting point, the relationship PSX ~ PPX ~ PEX and PSY ~ PPY ~ PEY must be maintained. HITACHI 119 5.10.2.7 Area Definition Register (ADR: Pr08 - PrOB) XMIN X·Minimum o YMIN V-Minimum o XMAX X-Maximum o YMAX V-Maximum Figure 5.32 Area Definition Register (ADR) ADR is used to define a drawing area using logical X-V addresses relative to the origin defined with the ORG command.' The ACRTC will check logical drawing addresses against ADR depending on the AREA mode specified in the graphic drawing command. 120 HITACHI 5.10.2.8 Read Write Pointer (RWP: PrOc - PrOD) o PrOC Display Number Read/Write Pointer High 15 PrOD Read/Write Pointer Low Figure 5.33 Read Write Pointer (RWP) R WP specifies a 20 bit physical frame buffer for use with the data transfer commands. Display Number (ON: PrOC bit 15 - bit 14) ON specifies the logical screen containing the data to be transferred. o DN Functions 15 14 0 0 Upper Screen 0 1 Base Screen 1 0 Lower Screen 1 1 Window Screen o Read Write Pointer High (RWPH: PrOC bit 7 - bit 0) Read Write Pointer Low (RWPL: PrOD bit 15 - bit 4) R WPH and R WPL define the initial 20 bit frame buffer address used with the data transfer commands. HITACHI 121 5.10.2.9 Drawing Pointer (DP: Pr10 - Pr11) o Pr10 Display Number Drawing Pointer High 151141131121111101 9 18 1 7 1 6 15 14 3 12 11 10 Pr11 DPAL Drawing Pointer Low DPD Drawing Pointer Dot Address Figure 5.34 Drawing Pointer (DP) The ACRTC uses DP for containing the physical drawing address calculated during drawing commands. When executing a drawing command, DP is updated as the Current Pointer (CP), specifying the current logical X-V drawing address, is moved. Display Number (DN: PrlO bit 15 - bit 14) DN specifies the screen for graphic drawing. Interpretation is the same as DN in the Read Write Pointer (RWP) register. Drawing Pointer Address High (DPAH: PrlO bit 7 - bit 0) Drawing Pointer Address Low (DPAL: Prll bit 15 - bit 4) DPAH and DPAL specify the 20 bit physical drawing pointer address. o o 122 HITACHI o Drawing Pointer Dot (OPO: Prll bit 3 - bit 0) OPO specifies the physical pixel address to locate a logical pixel within the 16 bit word addressed by OPAH, OPAL. Interpretation depends on the specified relationship between logical pixels and physical frame buffer bits as determined by the Graphic Bit Mode (GBM). GBM Function of DPD 1 bit/pixel DPD specifies 1 of 16 logical pixels 2 bits/pixel DPD specifies 1 of 8 logical pixels using most significant 3 bits of DPD. The least significant bit is not used. 4 bits/pixel DPD specifies 1 of 4 logical pixels using most significant 2 bits of DPD. The 2 least significant bits are not used. 8 bits/pixel DPD specifies 1 of 2 logical pixels using the most significant bit of DPD. The 3 least significant bits are not used. 16 bits/pixel DPD is not used. "" 5.10.2.10 Current Pointer (CP: Pr1 2 - Pr13) 1'5114113112111 110 I 9 I 8 I 7 I 6 I 5I 4 I 3I 2 I r 114 1,31 12 1" 1'0 I 9 I 8 I 7 I 6 I 5I 4 I 3I 2 I Figure 5.35 Current Pointer (CP) CP specifies the logical X-Y coordinates of the current drawing address. As drawing proceeds, the ACRTC calculates the physical frame buffer address for each X-Y addressed logical pixel. the physi9il address corresponding to CP is stored in the Drawing Pointer (DP) register. Two-complement format is used to indicate positive and negative values. HITACHI 123 ~ ~ .j::o... J: TYPE ~ o - J: ." cD' c ; ... 9» ~ 3 3 1\1 ::::II C. (J) ~ MNEMONIC ORG WPR Register RPR Access Command WPTN RPTN ORO OWT OMOO RO Data WT Transfer Command MOD ClR SClR CPY SCPY AMOVE RMOVE ALINE RliNE ARCT RRCT APlL RPLL APLG RPLC CRCL Graphic Command ELPS AARC RARC AEARC IREARC AFRCT RFRCT PAINT DOT PTN AGCPY RGCPY *1) I COMMAND NAME I Origin I Write Parameter Register I Read Parameter Register I Write Pattern RAM I Read Pattern RAM I OMA Read OMAWrite IOMAModify I Read I Write I Modify I Clear Selective Clear Copy I Selective Copy I Absolute Move I Relative Move I Absolute line I Relative line I Absolute Rectangle I Relative Rectangle I Absolute Polyline I Relative Polyline I Absolute Polygon I Relative Polygon I Circle I Ellipse I Absolute Arc Relative Arc Absolute Ellipse Arc Relative Ellipse Arc Absolute Filled Rectangle I Relative Filled Rectangle I Paint I Dot Pattern Absolute Graphic Copy I Relative Graphic Copy OPERATION CODE PARAMETER 10 0 0 0:0 1 : 0 0:0 0 0 0:0 0 0 OIOPH OPl 10 0 0 0 11 0,0 0:0 0 0 ; RN 0 0 10 0 0 0" 1 ; 0 0:0 0 0 i RN 10 0 0 1 :1 0: 0 OiO 0 0 0: PRA 0 n 01 •...• On 1000 1:1 1:00:0000: PRA 0 n 10 0 0:0 1 '0 0'0 0 0 0:0 0 0 0 AX AY 0 0 0 'I O! 0 OiO 0 0 0,0 0 0 0 AX AY 10010111:00:0000;00:MMIIAX AY 10100:01:00:000 OiO 0 0 00 10100;10:00:0000;0000110 10100111!00iOOOOiOO:MMOO 10101:10:0 OiO 0 0 Oio 0 0 00 0 AX AY 0 0 1 'I 1 '0 0;0 0 0 0 io 0: MM 0 AX AY 0 1--'> 'S: oso ,0 0 0 0,0 0 0 0 SAH SAL AX AY 10 1 1 1 is; oso :0 0 0 0 io O! MM IISAH SAL AX AY 11 0 0 0:0 0;0 0:0 0 0 0:0 0 0 011 X Y 11 0 0 010 1 ~O 0:0 0 00:0 0 0 011 dX dY 11 0 0 0,1 0 '0 0; AREA:COC:OPM Y 11000,11'00' AREA:COL;OPM IIdX dY 11 0 0 1 :0 0 : 0 0' AREA;COl:OPM II X Y 11 0 0 1 :0 1 : 0 0; AREA:COL:OPM II dX dY 11001!10ioo:AREA:COL:OPM lin Xl.Yl •.. Xn.Yn 11 0 0 1 il 1 ;0 0: AREA;COL:OPM II n dXl.dYl •. dXn.dYn 11010,00,00:AREA:COUOPM lin Xl.Yl ... Xn.Yn 11 0 1 0:0 1 :0 0: AREA:COLiOPM II n dXl.dYl ....dXn.dYn 11010'1 O'OiC: AREA:COL:OPM II r 1101011;0;CiAREA:COl:OPM lIa b dX 11 0 1 1 ,0 0 'O'C' AREA:COL:OPM II Xc Yc Xe Ye 0 1 '0 1 ; 0 i c, AREA: COL: OPM II dXc dYe dXe dYe 0 1!10:0,C~AREA:COL:OPM--'-;--b Xc Yc Xe Ye 0 1,11 ;O'C' AREAiCOLiOPM b dXc dYc dXe dYe IJ 0,0 0 '0 0: AREA:COL;OPM X Y 11 1 0 0:0 1 : 0 0' AREA: COL: OPM II dX dY 11100:10 :O:E; AREAiCOUOPM II 11 1 0 0 '1 1 :0 0: AREA:COL!OPM II 0 1 ISL: SO AREA: COL; OPM SZ *2) 0 ,S : oso AREA;0 0: OPM Xs Ys ox OY 11111:S iOSO AREAiO 0i OPM IIdXs dYs OX OY lrx 1# (wordsll 3 2 - (cycles) B 6 6 n+2 4n+B 2 4n+l0 (4x+B)y+12[x'y/Bt]+(62-6B) (4x+B)y+16[x'y/Bt] +34 3 I (4x+8)y+16[x'y/Bt] +34 12 2 B 2 B 4 (2x+8)y+12 (4x+6)y+12 (6x+l0)y+12 5 (6x+l0)y+12 3 56 3 56 3 P'l+lB 3 P'L+1B 3 2P(A+8)+54 3 2P(A+B)+54 12n+21 ~[P'L+16]+B I 2n+2 I ~[P'L+16]+B I 2n+21 ~[P'l+16]+P'Lo+20 I 2n+2 I ~[P·L+16]+P·Lo+20 2 Bd+66 4 10d+90 5 Bd+1B 5 Bd+1B 7 1Od+96 1Od+96 (P'A+B)B+18 3 (p. A+B)B+1B (lBA+l02)B-5B *1) 8 (P'A+l0)B+20 ((P+2)A+l0)B+70 5 ((P+2)A+l0IB+70 I In case of rectangular filling 15 87 0 *21 SZ: I SZy I SZx I SZy.SZx: Pattern Size n: number of repetition xlv: drawing words of x-direction/y-direction LlLo/d: sum of drawing dots A/B: drawing dots of main/sub direction E: [E=O (stop at Edge color), E=l (stop at excepting Edge color)] C: [C=l (clock wise). C=O (reverse)] [t]: rounding up {4:0PM.Q00-Oll P= 6: OPM.l00 - 111 o o ~ ~ l> Z c (J) 6.1 Command Overview The ACRTC interprets and processes commands issued by the MPU. These commands are classified into three groups. 1) Register Access Commands 2) Data Transfer Commands 3) Graphic Drawing Commands 6.2 Command Format ACRTC commands consist of a 16 bit op-code, optionally followed by 1 or more 16 bit parameters. When 8 bit MPU mode is used, commands, parameters and data are sent to and from the ACRTC in the order of high byte, low byte. (a) 16 bit interface bit bit In the case of 16 bit interface, first o Operation 15 move the 16 bit operation code and then move necessary 16 bit Code parameters one by one. p1~1____________~ ·• Parameter Pnl~____________~ (a) 1 6 bit Interface bit bit (b) 8 bit interface In the case of 8 bit interface, first move the operation code's High byte and Low byte in this order and then move those of parameters in the same order. 0 7 I High Low I } Operation I Code High P1 Low · · High Parameter Pn Low (b) 8 bit Interface HITACHI 125 6.3 Command Transfer Modes Commands (and associated parameters) can be issued to the ACRTC in one of two ways - program transfer or DMA transfer. 6.3.1 Program Transfer Program Transfer occurs when the MPU specifies the FIFO entry address and then writes commands/parameters to the wrtte FIFO under program control (RS = high, R/W, CS = low). The MPU writes are normally synchronized with ACRTC FIFO status by software polling or interrupts. o Software Polling (WFR, WFE interrupts disabled) a) MPU program checks the SR (Status Register) for Write FIFO Ready (WFR) flag = 1, and then writes one word of command or parameters. b) MPU program checks the SR (Status Register) for Write FIFO Empty (WFE) fl.ag = 1, and then writes one to eight words of commands or parameters. Interrupt Driven (WFR, WFE interrupts enabled) a) MPU WFR interrupt service routine writes one word of command or parameters. b) MPU WFE interrupt service routine writes one to eight words of commands or parameters. In the specific case of Register Access Commands and an initially empty write FIFO, MPU writes need not be synchronized to the write FIFO status. The ACRTC can fetch and execute these commands faster than the MPU can issue them. o 6.3.2 Command DMA Transfer Commands and parameters can be tran~ferred from MPU system memory using in external DMAC. The MPU initiates and terminates Command DMA Transfer mode under software control (CDM bit of CCR). Command DMA can also be terminated by assertion of the ACRTC DONE signal. DONE is treated as an input in Command DMA Transfer Mode. Using Command DMA Transfer, the ACRTC will issue cycle stealing DMA requests to the DMAC when the write FIFO is empty. The DMA data is automatically sent from system memory to the ACRTC write FIFO regardless of the contents of the Address Register. 126 HITACHI 6.4 Register Access Commands Registers associated with the Drawing processor (the Pattern RAM and Drawing Parameter Registers) are accessed through the read and write FIFOs using the Register Access Commands. Command Function ORG Inicialize the relation between the origin point in the X-Y coordinates and the physical address. WPR Write into the parameter register RPR Read the parameter register WPTN Write into the pattern RAM RPTN Read the pattern RAM Figure 6.2 Register Access Commands HITACHI 127 6.5 Data Transfer Commands Data Transfer Commands are used to move blocks of data between the MPU system memory and the ACRTC frame buffer or within the frame buffer itself. Before issuing these commands, a physical 20 bit frame buffer address must be specified in the RWP (Read Write Pointer) Drawing Parameter Register. The DMA Data Transfer Commands (DRD, DWT and DMOD) are used to send large amounts of data between system and frame buffer memory. The programmer specifies the command and the X and Y logical pixel dimensions of the frame buffer data block. The ACRTC will automatically control the external DMAC to request data transfers via the read or write FIFOs. In Data DMA Transfer, the ACRTC DONE pin becomes an output which the ACRTC asserts to the external DMAC to terminate the transfer. Also, either cycle steal or burst DMA request mode can be used for data DMA (DRC bit of CCR). Note that DMA data transfer can be performed without an external DMAC, i.e. under MPU program control. In this case, the data DMA handshaking (DREQ, DACK and DONE) signals are disabled by resetting the DDM bit in CCR to O. After issuing a DMA data transfer command, the MPU reads or writes the appropriate data to the ACRTC FIFOs under program control. The programmer must insure that the amount of data transferred equa~s the amount specified as parameters to the command. Also note that the ACRTC will go into an indefinite wait state after the last transfer of a DRD command. Then, the command should be aborted (by setting the ABT bit in CCR to 1) and the next command issued. 128 HITACHI Function Command DRD DMA read of the frame buffer data DWT DMA write into the frame buffer DMOD DMA modify of the frame buffer data (bit maskable) RD One word read from the frame buffer WT One word write into the frame buffer MOD One word modify of the frame buffer (bit maskable) CLR Clear of frame buffer area SCLR Clear of frame buffer area (bit maskable) CPY SCpy Copy of frame buffer area into another area Copy of frame buffer area into another area (bit maskable) Figure 6.3 Data Transfer Commands Operation Code 15 8 I Command Code 10 0 0 0 0 2 olM 0 MI Parameter 15 0 .------p-a-ra-m-e-te-r-----,I ,. .----------,o 15 . Parameter Figure 6.4 Data Transfer Command Format HITACHI 129 6.5.1 Modify Mode The DMOD, MOD, SCLR and SCPY commands allow 4 types of bit levellogical operations to be applied to frame buffer data. The modify mode is encoded in the lower two bits (MM) of these op-codes. The bit positions within each frame buffer word to be modified are selectable using the mask register (MASK). Bits masked with 1 are modifiable, those masked with 0 are not. MM Modify Mode 0 0 0 1 1 0 AND frame buffer data with command parameter data and rewrite to the frame buffer. 1 1 EOR frame buffer data with command parameter data and rewrite to the frame buffer. o REPLACE frame buffer data with command parameter data. OR frame buffer data with command parameter data and rewirte to the frame buffer. Modify Mode Examples The following examples show the use of the REPLACE, OR, AND and EOR modify modes. The modifier data (issued as a prameter to the DMOD, MOD, SCLR and SCPY commands) and the non-masked data in the frame buffer are logically operated on, and the result is rewritten to the frame buffer. 130 HITACHI MM!OO SAePlace I0 0 0 0 1, 1 1 1 1 1 10 0 I0 0 0 1 I0 0 1 0 0 0 l' \11 o1 1 1)1 1 1 10001101 I 10 1 0 1 I 0 01 MASK Register 1 0 1 0 01 Read Data (Frame Buffer Data: before modified) 1 0 1 0 oj Write Data (Frame Buffer Data: modified) 0 0 I Modifier Data (Set by COMMAND PARAMETER) The read data bit positions for which the MASK register contains '1' is REPLACED with the command parameter modifier data. The result is rewritten to the read data location in the frame buffer. Figure 6.5(a) REPLACE Modify Mode HITACHI 131 MMr O' ~OR 10 0 0 0 10 0 0 I, , , , , , , 10 0 , 0 0 0 10 0 0 0 0 01 MASK Register I' , 0 , 0 01 Read Data (Frame Buffer Data: before modified) 0 , 0 rj 10 o 0 'L 0 , , , , , I' , 1 0 , o , oj I 1 , '1 1 Write Data (Frame Buffer Data: modified) Modifier Data (Set bV COMMAND PARAMETER) The read data bit positions for which the MASK register contains '1' is ORed with the command parameter modifier data. The result is rewritten to the read data location in the frame buffer. Figure 6.5(b) OR Mofify Mode 132 HITACHI MMr 10 BAND I 0 1 1 MASK Register 1 0 1 0 01 Read Data (Frame Buffer Data: before modified) 1 0 1 ~ Write Data 1 10 0 10001100 1 0 1 1 11 1 0 ~ 1 1 fl 1 1 I 0 0 11 01 1 0 0 0 1 I 0 11 0 0 o I0 1 o 0 I 1 0 0 0 I (Frame Buffer Data: modifiedl Modifier Data (Set by CDMMANO PARAMETERI The read data bit positions for which the MASK register contains '1' is ANDed with the command parameter modifier data. The result is rewritten to the read data location in the frame buffer. Figure 6.5(c) AND Modify Mode HITACHI 133 MM= 11 + 0 I EOR 0 0 0 0 I 0 0 0 0 11 1 1 1 1 1 10 0 MASK Register I0 0 0 1 I0 0 1 0 0 0 11 1 0 1 0 01 Read Data (Frame Buffer Deta: before modified) o 0 \1 1 0 1 0 01 Write Data (Frame Buffer Data: modified) o 0 r= 't \ 0 0 I 0 1 1 I0 1 o 1\ 0 1 I 1 I I Modifier Data (Set by COMMAND PARAMETER) The read data bit positions for which the MASK register contains '1' is EORed with the command parameter modifier data. The result is rewritten to the read data location in the frame buffer. Figure 6.5(d) EOR Modify Mode 134 HITACHI 6.6 Graphic Drawing Commands The ACRTC has 23 separate graphic drawing commands. Graphic drawing is performed by modifying the contents of the frame buffer based upon microcoded drawing algorithms in the ACRTC drawing processor. Most coordinate parameters for graphic drawing commands are specified using logical pixel X-V addressing. The complex task of translating a logical pixel address to a linear frame buffer word address, and further selecting the appropriate sub-field of the word (for example, a given logical pixel in 4 bits per logical pixel mode might reside in bits 8-11 of a frame buffer word) is performed at high speed by ACRTC hardware. Many instructions allow specification of X-V coordinates with either absolute or relative X-V coordinates (e.g. ALINE and RLINE). In both cases, twos complement numbers are used to represent positive and negative values. (a) Absolute Coordinate Specification The screen address (X, Y) is specified in units of logical pixels relative to an origin point defined with the ORG command. (b) Relative Coordinate Specification The screen address (dX,dY) is specified in units of logical pixels relative to the current drawing pointer (CP) position. A graphic drawing command consists of a 16 bit op-code and optionally 0 to 64K 16 bit parameters. The 16 bit op-code consists of an 8 bit command code, an AREA Mode specifier (3 bits), a Color Mode specifier (2 bits) and an Operation Mode specifier (3 bits). The Area Mode allows versatile clipping and hitting detection. A drawing area can be defined, and should drawing operqtions attempt to enter or leave that area, a number of programmable actions can be taken by the ACRTC. The Color Mode determines whether the Pattern RAM is used indirectly to select Color Registers or is directly used as the color information. The Operation Mode defines one of eight logical operations to be performed between the frame buffer read data and the color data in the Pattern RAM to determine the drawing data to be rewritten to the frame buffer. HITACHI 135 (j) Absolute Coordinate Specifica- y tion Specifies the addresses (x, y) based on the origin point set by the ORG command. (x, y) y -- -------1 I I I I I I ------~----~x~------x ! Origin (a) Figure 6.6(a) Absolute Coordinate Specification y (ij) Relative Coordinate Specifica- tion Specifies the relative addresses (~x, ~y) related to the current drawing point. 6y i Y -----, --- I 6X __ J CP (x,'y) ------I+---~x---------x Origin (b) Figure 6.6(b) Relative Coordinate Specification 136 HITACHI Function Command AMOVE Movement of current points RMOVE ALINE Drawing of straight lines RLiNE ARCT Drawing of rectangles RRCT APLL Drawing of polylines RPLL APLG Drawing of polygons RPLG CRCL Drawing of circles ELPS Drawing of ellipses AARC Drawing of arcs RARC AEARC Drawing of ellipse arcs REARC AFRCT Painting of rectangle areas (Tiling) ~-- RFRCT PAINT Painting of arbitrary areas (Tiling) DOT Making of dots PTN Drawing of basic patterns (rotation angle: 45°) AGCPY Graphic copy between frame memories (rotation angle: 90° /mirror tumover) RGCPY Figure 6.7 Graphic Drawing Commands Operation Code 15 8 7 5 4 I Command Code IAREAfOL 3 2 0 Parameter 1;..5_ _ _ _ _ _ _ _ _ _ _-,0 I OPM I IL _ _ _ _ _ Pa_r_am_e_te_r_ _ _ _....1 o ,---------------------, Parameter 15 Figure 6.8 Graphic Drawing Command Format HITACHI 137 6.6.1 Operation Mode The Operation Mode (OPM bits) of the Graphic Drawing Command specify the logical drawing condition. OPM Operation Mode REPLACE: Replaces the frame buffer data with the color data. 0 0 0 0 0 1 OR: ORs the frame buffer data with the color data. The result is rewritten to the frame buffer. 0 1 0 AND: ANDs the frame buffer data with the color data. The result is rewritten to the frame buffer. 0 1 1 EOR: EORs the frame buffer data with the color data. The result is rewritten to the frame buffer. 1 0 0 CONDITIONAL REPLACE (P=CCMP): When the frame buffer data at the drawing position (P) is equal to the comparison color (CCMP), the frame buffer data is replaced with the color data. 1 0 1 CONDITIONAL REPLACE (P:;t:CCMP): When the frame buffer data at the drawing position (P) is not equal to the comparison color (CCMP), the frame buffer data is replaced with the color data. 1 1 0 CONDITIONAL REPLACE (P < Cl): When the frame buffer data at the drawing position (P) is less than the color register data (CU, the frame buffer data is replaced with the color data. 1 1 1 CONDITIONAL REPLACE (P> Cl): When the frame buffer data at the drawing position (P) is greater than the color register data (Cl), the frame buffer data is replaced with the color data. Following are examples of each of the eight operation modes. In these examples, 4 bits/logical pixel is assumed. Figure 6.10 shows examples of a drawing pattern applied with various OPM modes. 138 HITACHI OPM = 000 L 000 I Replace 3 0 1011 1-1-1 DPD in DP 14 bit/pixel mode) I 0 0 0 110 0 1 010 0 , 1 0 1 0 01 \1/ 10 0 0 '10 1 0 1 10 0 , 1 0 1 0 0I I 10 1 0 1 I I Read data (Frame Buffer data: before correction) Write data (Frame Buffer data: after correction) Color data (Color register) One pixel of the frame buffer read data is REPLACED with the corresponding color register data and the result is rewritten to the frame buffer read data location. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(a) REPLACE Operation Mode HITACHI 139 OPMiOO1 I 001 lOR 3 0 10 11 1-1-1 10 0 0 1t. OPO in OP (4 bit/pixel mode) (( .\' ."1 0 0 1 1 0 1 o oj Read data (Frame buffer data: before correction) ~ 10 0 0 11 0 I I ~ 1 1 .110 I I) 1 11 t I 0 1 1 0 1 o 0I I Write data (Frame buffer data: after correction) Color data (color register) One pixel of the frame buffer read data is ORed with the corresponding color register data and the result is rewritten to the frame buffer read data location. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(b) OR Operation Mode 140 HITACHI QPM = OlD ~ a 1a I AND 3 0 1011 1·1·1 Ia a a 1I a o 1a a a 110 o 1 10 1 ~ 0 l 1 0 DPD in DP 14 bit/pixel model 010 01 1 0 010 11 a 001 Read data 1 1 a 1 a 0] Write data 1 J (Frame buffer data: before correction} (Frame buffer data: after correction) Color data (Color register) One pixel of the frame buffer read data is ANDed with the corresponding color register data and the result is rewritten to the frame buffer read data location. The dot pointer serves to extract the pixel from the frame butTer word - in this example, 4 bits/pixel. Figure 6.9(c) AND Operation Mode HITACHI 141 OPM = ! 011 011 I EOR 3 0 10 111-1-1 DPD in DP 14 bit/pixel mode) Read data (Frame buffer data: before correction) Write data (Frame buffer data: after correction) Color data (color register) One pixel of the frame buffer read data is EORed with the corresponding color register data and the result is rewritten to the frame buffer read data location. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(d) EOR Operation Mode 142 HITACHI OPM = 100 ~ 1 00 I Conditional Replacement IP 3 = CCMP) 0 1011 1·1·1 DPD in DP 14 bit/pixel mode) ~--~~~~~--------~ Color Comparison Register data (CCMP) Read data (Frame buffer data: before correction) r-......I'-~-......-.,--_-Jl._---., Write data (Frame buffer data: after correction) Color data IColor register) One pixel of the frame buffer read data is compared with the corresponding one pixel contents of the Color Comparison Register (CCMP). If equal, the read data is replaced with the color data and the result is rewritten to the read data location in the frame buffer. If not equal, the read data (unmodified) is rewritten to the read data location in the frame butTer. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(e) P=CCMP Operation Mode HITACHI 143 OPM = 101 ~ 1 0 1 I Conditional Replacement (P 3 + CCMP) 0 10 11 1·1·1 I o o 1 0 1o I 0 $ 10 0 DPD in DP (4 bit/pixel mode) 0 1 0' Color Comparison Register (CMP) data Read data (Frame buffer data: before correction) o 0 110 1 o 01 o 0 1 1 0 1 o 01 ~ y~ N ) 100 0 I 1 0, ',:,,1 ,I 0 1 0'" I Write data (Frame buffer data: after correction) Color data (Color register) One pixel of the frame buffer read data is compared with the corresponding one pixel contents of the Color Comparison Register (CCMP). If not equal, the read data is replaced with the color data and 'the result is rewritten to the read data location in the frame buffer. If equal, the read data (unmodified) is rewritten to the read data location in the frame buffer. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(1) P 144 HITACHI * CCMP Operation Mode QPM= 110 ~ Conditional Replacement (P 3 < C LI 0 1011 1·1·1 OPO in OP (4 bit/pixel model Read data (Frame buffer data: before correction) Write data (Frame buffer data: after correction) Color data (Color register) One pixel of the frame buffer read data is compared with the corresponding one pixel contents of the color data (CL). If the read data is LESS than the color data, the read data is replaced with the color data and the result is rewritten to the read data location in the frame buffer. If the read data is GREATER than or EQU AL to the color data, the read data (unmodified) is rewritten to the read data location in the frame buffer. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(g) P< CL Operation Mode HITACHI 145 OPM= 111 ! 111 I Conditional Replacement (P 3 > Cl) 0 10 11 j.j.j DPD in DP (4 bit/pixel mode) Read data (Frame buffer data: before correction) Write data (Frame buffer data: after correction) Color data (Color register) One pixel of the frame buffer read data is compared with the corresponding one pixel contents of the color data (CL). If the read data is GREATER than the color data, the read data is replaced with the color data and the result is rewritten to the read data location in the frame buffer. If the read data is LESS than or EQUAL to the color data, the read data (unmodified) is rewritten to the read data location in the frame buffer. The dot pointer serves to extract the pixel from the frame buffer word - in this example, 4 bits/pixel. Figure 6.9(h) P> CL Operation Mode 146 HITACHI ,-- - - - - - - - - - - - - , F//I I I I I I I t:L:d I i I L I Ii _ _ _ _ _ _ _ _ _ _ _ _ _ _ -lI Drawing Pattern Picture Memory before Drawing r--------------, I I I77A tL.:::I I I I I I I I I I I I I ,---------------, I I I I I77A W I I I I I I I Replacement I OR r---------------, I I I I I I I r--------------, I I f7?l I rLLl I I I I I I I I I I I n~i L ______________ I ~ AND EOR Figure 6.10 Operation Mode Example HITACHI 147 6.6.2 Color Mode The Color Mode (COL bits) specify the source of the drawing color data as directly or indirectly (using the Color Registers) determined by the contents of the Pattern RAM. COL 0 0 0 1 1 0 1 1 Color Mode = 0, Color Register 0 is used. = 1, Color Register 1 is used. When Pattern RAM data = 0, drawing is suppressed. When Pattern RAM data = 1, Color Register 1 is used. When Pattern RAM data = 0, Color Register 0 is used. When Pattern RAM data = 1, drawing is suppressed. When Pattern RAM data When Pattern RAM data -- Pattern RAM contents are directly used as color data. The Color Mode chooses the source for color information based on the contents (0 or 1) of a particular bit in the 16 bit by 16 bit (32 byte) Pattern RAM. A sub-pattern is specified by programming the Pattern RAM Control Register (PRC) with the start (PSX, PSY) and end (PEX, PEY) points which define the diagonal of the subpattern. Furthermore, a specific starting point for Pattern RAM scanning is specified by PPX and PPY. Pattern RAM ...-_ _--:.;.(P..;:.E~X, PE YI o (PPX, PPYI (PSX, PSYI Normally, the color registers (CL) should be loaded with one color data based on the number of bits per pixel. For example, if 4 bits/pixel are used, the 4 bit color pattern (e.g. 0001) should be replicated four times in the color register, i.e. Color Register = I0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 I In this way, color changes due to changing dot address are avoided. 148 HITACHI Graphic Pattern RAM (PEX, PEY) x = 1 (PSX, PSY) If the scanned Pattern RAM bit is equal '0', Color Register 0 (CLO) determines the color information. If the scanned Pattern RAM bit is equal '1', Color Register 1 (CLl) determines the color information. Figure 6.11 (a) Color Mode = 00 HITACHI 149 COL = 01 Graphic Pattern RAM (c) (PEX, PEY) Color Register 0 x = 1 (PSX, PSY) If the scanned Pattern RAM bit is equal '0', the drawing operation is suppressed and the frame buffer is not changed. If the scanned Pattern RAM bit is equal '1', Color Register 1 (CLI) determines the color information. Figure 6.11(b) Color Mode = 01 150 HITACHI COL = 10 Color Information =r= Color Register 0 Graphic Pattern RAM (PEX, PEY) r-------, (PPX, PPY) Color Register 1 (PSX, PSY) If the scanned Pattern RAM bit is equal '1', the drawing operation is suppressed and the frame buffer is not changed. If the scanned Pattern RAM bit is equal '0', Color Register 0 (CLO) determines the color information. Figure 6.11 (c) Color Mode = 10 HITACHI 151 leOL=lll PPX PPY Pattern RAM 3 F 2 B 1 D 0 0 C 3 B 2 A 9 0 0 8 3 7 0 2 6 1 5 0 4 3 3 0 2 2 1 0 01 c D E F 8 9 A B 4 6 0 2 3 ~. Bit Information on Pattern RAM Figure 6.11 (d) Color Mode = 11 In the former three color modes (Pattern RAM indirect), the actual color information is stored in the color registers (CLO, CLl) and selection is based on the 0 or 1 bit value during Pattern RAM scanning. In ~color mode = 11 (Pattern RAM direct), the Pattern RAM contents are directly used to generate color information. This is accomplished by remapping of the Pattern RAM so that it is interpreted as containing up to 4 by 4 logical pixel color patterns, each of which contains 16 bits of color information. 152 HITACHI Associated with this logical remapping of the Pattern RAM, the contents of the Pattern RAM Control Register (PRC) are interpreted differently. As shown below the pattern pointer, pattern start and pattern end (PPX, PPY, PSX, PSY, PEX and PEY) are restricted to specify a maximum 4 by 4 logical pixel pattern. Specifically, bits 15-14 and 7-6 must be set to O. " RN Register Name 05 ----- 06 07 Pattern Control - 15 14131211 10 9 8 7 6 5 4 3 2 1 0 o 0 PPY PZCY 0 0 PPX PZCX--0 0 PSY 0 o 0 0 0 0 PSX o 0 0 0 PZY 0 0 PEX 0 0 PEY PZX ~~" A pattern size less than 4 by 4 logical pixels can be specified (minimum is 1 by 1 logical pixel) as shown below. In this example a 2 by 4 logical pixel pattern is specified by setting PSX = 1, PSY = 0, PEX = 2 and PEY = 3. D E 9 A 5 6 2 1 As in color register indirect modes, normally one color is repeatedly assigned to the 16 bit color information depending on the number of bits per pixel. For example, when 4 bits per pixel are used, and color information for a pixel is 0001, the Patttern RAM should contain ... 100010001000100011 This prevents color change due to changing dot address. HITACHI 153 6.6.3 Area Mode Prior to drawing, a drawing 'area' may be defined (Area Definition Register). Then, during Graphics Drawing operation the· ACRTC will check if the drawing point is attempting to enter or exit the defined drawing area. Based on eight Area Modes, the ACRTC will take appropriate action for clipping or hitting. AREA Drawing Area Mode 0 0 0 Drawing is executed without Area checking. 0 0 1 When attempting to exit the Area. drawing is stopped and the ARD (Area Detect) and CEO (Command End) flags are set. 0 1 0 Drawing suppressed outside the Area - drawing operation continues and the ARD flag is not set. 0 1 1 Drawing suppressed outside the Area - drawing operation continues and the ARD flag is set. 1 1 0 0 Same as AREA = 0 0 O. 0 1 When attempting to enter the Area. drawing is stopped and the ARD and CEO (Command End) flags are set. 1 1 0 Drawing suppressed inside the Area and the ARD flag is not set. - drawing operation continues 1 1 1 Drawing suppressed inside the Area and the ARD flag is set. - drawing operation continues The following examples show execution of a CRCL (Circle) command using the various Area Modes. It is assumed that the Area Definition Register has been loaded to define the Area bounded by XMIN, YMIN and XMAX, YMAX. 154 HITACHI AREA = XOO : Area Mode (XMAX, YMAX) Area Definition (XMIN, YMIN) Drawing is executed without area checking. Figure 6.12(a) Area Mode = XOO HITACHI 155 AREA I: = 001 Area Mode (XMAX, YMAX) Area Definition / I I , I I \ \ \ , I I I " ---_ I ..... ,,; " (XMIN, YMIN) Drawing is executed as long as the CP (Current Pointer) resides in the defined area. When the drawing operation causes the CP to go outside the defined area, the drawing instruction is terminated and the ARD (Area Detect) and CED (Command End) flags in the Status Register (SR) are set to '1'. Figure 6.12(b) Area Mode = 001 156 HITACHI AREA = 010 I: Area Mode (XMAX, YMAX) (XMIN, YMIN) Wheh the CP (Current Pointer) is outside the defined area, drawing is suppressed but the drawing operation continues. When CP is inside the defined area, drawing operation is enabled. When the drawing instruction execution is completed, the CED (Command End) bit in the Status Register (SR) is set to '1'. The ARD bit (Area Detect) bit in the Status Register is not set to '1' at any time during the drawing instruction execution regardless of whether CP goes inside or outside the defined area. Figure 6.12(c) Area Mode = 010 HITACHI 157 AREA = 011 I : Area Mode (X MAX, YMAX) I / / , I I \ \ \ ,, (XMIN, YMIN) This mode is the same as AREA MODE = 010 in that drawing is enabled when CP (Current Pointer) is inside the defined area and suppressed when CP is outside the defined area. However, if at any time during the drawing instruction execution, CP goes outside the defined area, the ARD (Area Detect) bit in the Status Register (SR) will be set to '1'. The ARD bit can be monitored to determine when the CP goes outside the defined area. Figure 6.12(d) Area Mode 158 HITACHI = 011 AREA = 101 I: Area Mode (XMAX, YMAX) Area Definition / I I I I I \ I \ , , ~---------' (XMIN, YMIN) ........ _- -_/ I I / ;' Drawing is executed as long as the CP (Current Pointer) resides outside the defined area. When the drawing operation causes the CP to go inside the defined area, the drawing instruction is terminated and the ARD (Area Detect) and CED (Command End) flags in the Status Register (SR) are set to '1'. Figure 6.12(e) Area Mode = 101 HITACHI 159 AREA = 110 I: Area Mode (XMAX, YMAX) Area Definition / / I I I I \ \ \ (XMIN, YMIN) When the CP (Current Pointer) is inside the defined area, drawing is suppressed but the drawing operation continues. When CP is outside the defined area, drawing operation is enabled. When the drawing instruction execution is completed, the CED (Command End) but in the Status Register (SR) is set to '1'. The ARD bit (Area Detect) bit in the Status Register is not set to '1' at any time during the drawing instruction execution regardless of whether CP goes inside or outside the defined area. Figure 6.12 (f) Area Mode 160 HITACHI = 110 AREA=lll I: Area Mode (XMAX, YMAX) Area Definition / I I , I I \ \ \ " (XMIN, YMIN) This mode is the same as AREA MODE = 110 in that drawing is enabled when CP (Current Pointer) is outside the defined area and suppressed when CP is inside the defined area. However, if at any time during the drawing instruction execution, CP goes inside the defined area, the ARD (Area Detect) bit in the Status Register (SR) will be set to '1'. The ARD bit can be monitored to determine when the CP goes inside the defined area. Figure 6.12(g) Area Mode = 111 HITACHI 161 6.7 Graphic Drawing Processor ACRTC Graphic Drawing is performed in units of logical pixels which may be programmed to consist of 1, 2, 4, 8 or 16 physical bits in the frame buffer. In order to draw, the ACRTC Drawing Processor uses three operation control units. (a) Drawing Algorithm Control Unit Interprets graphic commands and parameters and executes the appropriate microprogrammed drawing algorithm. Note that this unit calculates coordinates using logical pixel X-Y addressing. (b) Drawing Address Generation Unit Converts logical X-V addresses from the DACU to a bit address in the frame buffer. The frame buffer is organized as sequential 16 bit words. The bit address consists of a 20 bit address OM word address space) and 0-4 bits specifying the logical pixel bit address within the physical frame buffer word. (c) Logic Operation Unit Using the address calculated in (a) and (b), performs logical operations between the existing (read) data in the frame buffer and the drawing pattern in the Pattern RAM, and rewrites the results to the frame buffer. Drawing Algorithm r--Control Unit Drawing Address Generation Unit - Figure 6.1 3 Drawing Processor 162 HITACHI Logic Operation Unit Bit Mode Data (bit) per pixel 1 bit/pixel 1 1 16 2 bit/pixel 2 4 8 4 bit/pixel Color or color image number Number of pixels per word 4 16 4 8 bit/pixel 8 256 2 16 bit/pixel 16 65536 1 Figure 6.14(a) Bits per Pixel HITACHI 163 0- .j>.. :I ~ (") :I Bit Mode 1 Word Data Configuration cD' ~ CD o 1 bit/pixel ~ 43 0 I I I I I I I I I I I I I I I I I I\ 7\ I ) Y ~ 1 pixel data ~ ~ '1J I I I I I I I LfJ )C' !. :r -< ~ • ~'( • 'YX • ill-I>-' "'( Start PEX Figure 6.17(b) Plane Drawing Example 170 HITACHI X ) l. ( o: • Color 0 : Color 1 x FUNCTION OF COMMANDS TYPE Register Access Command Data Transfer Command Graphic Command :c ~ (') :c - ~ MNEMONIC ORG WPR RPR WPTN RPTN DRD DWT DMOD RD WT MOD CLR SCLR CPY SCPY AMOVE RMOVE ALINE RUNE ARCT RRCT APLL RPLL APLG RPLC CRCL ELPS AARC RARC AEARC REARC AFRCT RFRCT PAINT DOT PTN AGCPY RGCPY COMMAND NAME Origin Write Parameter Register Read Parameter Register Write Pattern RAM Read Pattern RAM DMA Read DMAW,ite DMAModify Read Write Modify Clear Se lect ive Clear COpy Selective Copy Absolute Move Relative Move Absolute Line Relative Line Absolute Rectangle Relative Rectangle Absolute Polyline Relative Polyline Absolute Polygon Relative Polygon Circle Ellipse Absolute Arc Relative Arc Absolute Ellipse Arc Relative Ellipse Arc Absolute Filled Rectangle Relative Filled Rectangle Paint Dot Pattern Absolute Graphic Copy Relative Graphic Copy # (words) - (cycles) OPERATION CODE PARAMETER 0 0 0 0 1 ,0 0,0 0 0 0 '0 0 0 0 DPH DPL 3 8 0 0 0 '1 0,0 0,0 0 0 , RN 6 D 2 1 6 RN 0 0 0 '1 1,00'000, 0 0 1 ,1 0,0 0'0 0 0 0, PRA n Dl •...• Dn n+2 4n+8 n 2 0 0 1 ,1 1'00'0000, PRA 4n+l0 (4x+8)y+12 [x'y/8t] +(62-68) 0 1 0:0 1 '0 0'0 0 0 0,0 0 0 0 AX AY 3 (4x+8)y+16[x' y/8t] +34 3 00 1 0'1 0'00'0000,0000 AX AY (4x+8)y+16[x'y/8t] +34 o 0 1 011 1 : 0 0:0 0 0 0,0 0: MM AX AY 3 12 0100'01 '00'0000,0000 1 8 0100'10'00:0000,0000 D 2 B o 1 0 011 l'OO,OOOO,OO'MM D 2 (2x+8)y+12 4 o 1 0 1 1 0: a 0,0 a 0 010 0 0 0 D AX AY (4x+6)y+12 4 o 1 0 1 '1 1 '00,0000,0 OIMM D AX AY (6x+l0)y+12 o 1 1 0 'S: DSD ,0 a 0 0 ,0 0 0 0 SAH SAL AX AY 5 (6x+l0)y+12 1 1 1 ,S' DSD ,0 0 0 0,0 0 I MM SAH SAL AX AY 5 56 1 0 0 0 0 0 ,0 0,0 0 0 0,0 0 0 0 X Y 3 100 010 1 '0 0,0 0 0 0,0 0 a 0 dX dY 56 3 Y P'L+18 X 3 1 0 0 0,1 0 '0 0' AREA:COL OPM P'L+18 1 0 0 0 1 1 ,0 0' AREA:COL OPM dX dY 3 2P(A+B)+54 Y X 3 1 a 0 1 :0 0,0 0' AREA:COL OPM 2P(A+B)+54 1001:01,00' AREA;COLOPM dX dY 3 ~[P'L+16]+8 n 2n+2 Xl. Yl •.. Xn. Yn 1 o 0 1 '1 0,0 0' AREA:COL OPM ~[P'L+16]+8 2n+2 n dXl. dYl •. dXn. dYn 1 0 0 1 11 1 '0 0' AREAicOL OPM ~[P'L+16]+P'Lo+20 2n+2 n Xl, Yl •.. Xn, Yn 1 0 1 0,0 0,0 0' AREA:COL OPM ~[P'L+16]+P'Lo+20 1010,01 '00: AREA:COLOPM n dXl. dYl .... dXn. dYn 2n+2 8d+66 r 2 1 0 1 0 '1 0 'O'C' AREA!COL,OPM 10d+90 1 0 1 0 1 1 'O'C: AREA:COLIOPM a b dX 4 8d+18 1 0 1 1 ·0 a 'O'C' AREA:COL:OPM Xc Yc Xe Ye 5 8d+18 1 0 1 1 '0 1 ,O,C' AREA;COL:OPM 5 ~Yc dXe dYe Ye 10d+96 b Xc Yc Xe 7 1 0 1 1 '1 a 'O,C' AREAl cOLi OPM- a dXc dYe dXe dYe 7 10d+96 1 0 1 1,1 1 :O'C' AREA: COL: OPM b a (P'A+B)B+18 X Y 3 1 1 0 0 ,0 a '0 0' AREA;COL;OPM (P'A+B)B+18 1 1 0 0 '0 1 ,0 0' AR EA: COLi OPM dX dY 3 '1 ) (18A+l02)B-58 1 1 10010'0,E' AREAl COL: OPM 8 1 1 1 0 0'1 1 '0 0: AREA: COLi OPM SD I AREA: COL; OPM *2) (P'A+l0)B+20 SZ 2 1 1 0 1 ISL: , AREA: 0 0; OPM ((P+2)A+l0)B+70 Xs Ys DX DY 5 1 1 1 O,S :DSD , ((P+2)A+l0)B+70 AREAi a OIOPM dXs dYs DX DY 5 1 1 1 1 'S : DSD - o o o o o o o *') In case of rectangular filling *2) Slx I Sly. Slx: Pattern Size n: number of repetition x/y: drawing words of x-direction/y-direction ULoId: sum of drawing dots AlB: drawing dots of mainlsub direction E: [E=O (stop at Edge color), E=l (stop at excepting Edge color)] C: [C=l (clock wise), C=O (reverse)] [t] : rounding up 15 Sl: I 87 Sly I 0 p={4: OPM-OOO - 011 6: OPM-l00-lll C') o s: s: » 2 C en /ORG [1] ORG (Origin) PAGE ORG-1 Associates a logical X-Y screen origin with a physical frame buffer address. TYPE Register Access Command ORG DPH,DPL WORD NUMBER Wn=3 COMMAND CODE 15 I a a a 010 1 a 010 a a 010 a a a aI hexadecimal notation ($ a 4 a 0) EXECUTION CYCLES Cn=8 COMMAND PARAMETERS 15 a I~-------D-P-H------~I < DESCRIPTION> The ORG command must be issued to the ACRTC prior to graphic drawing. ORG defines the logical X-Y coordinate origin upon which all graphic drawing addresses are based and sets the screen number in which to draw. The DPH and DPL (Drawing Pointer High, Low) parameters establish the physical address in the frame buffer at which the origin is set. This physical address is composed of thl; following three components - DN (Screen Number) is a screen designator, DPAH, DPAL (Drawing Pointer Address High, Low) is a 20 bit address selecting one of 1 megawords in the frame buffer and DPD (Drawing Pointer Dot) specifies the bit field associated with the addressed logical pixel. The ORG command initializes the Drawing Pointer (DP) to the origin and clears the Current Pointer (CP). 174 HITACHI jORG ORG (Origin) ON: PAGE ORG-2 OP: 151413 oN I 87 I OPAH (8 bits) 0-0 J ON Screen Number 00 Upper Screen 01 Base Screen OPH (16 bits) 10 Lower Screen OPL (16 bits) 11 Window Screen OPAL (12 bits) 0 DPD (4 bits) II • The origin address of the X-Y coordinates is set with the 20-bit linear address using to OPAH and OPAL. • OPO determines the dot pOSition in 16-bit data addressed by OPAH/OPAL. • ON sets screen number for drawing. Figure Cl-l ORG HITACHI 175 IORG ORG (Origin) PAGE ORG-3 < EXAMPLE> The origin for the Upper screen (screen number 0) is set to bit position 4-7 at frame buffer word address $25. 4 bits per logic.al pixel and Memory Width (MW) $10 are assumed. = COMMAND CODE 15 0 I0 0 0 0 10 1 0 0 I0 0 0 010 0 0 0 I ($ 0 4 0 0) 1000010.00010000100001 ($ 0000) COMMAND PARAMETERS 0 15 0 15 §oYT6-o-,-oro-,' 0 11 0 1 O?J ($ 0 254) y 01234.56789 o I" I ABCDEF I' , I I' , I I' , I 1"'1 • I I' I I I' I I I' I I I'I I I' I I I' I I I" I 1" I I' I I I' " __________________ ~---------------------------------x Figure Cl-2 ORG Execution Example 176 HITACHI IWPR [2] WPR (Write Parameter Register) PAGE WPR-1 Write the contents of the Drawing Parameter Registers. TYPE WPR (RN) 0 Register Access Command WORD NUMBER Wn=2 COMMAND CODE hexadecimal notation 15 0 1 0 0 0 011 0 0 010 0 0L~ ($ 0 8 0 X) EXECUTION CYCLES Cn=6 5 bits COMMAND PARAMETERS o 15 o (Data) < DESCRIPTION> The Drawing Parameter Register number to be written is specified in the RN (Register Number) field of the op-code. The contents of the parameter (D) is written to the selected register. HITACHI 177 IWPR WPR (Write Parameter Register) PAGE WPR-2 The value $1111 is written to the CL 1 (Color 1) of the drawing parameter register. COMMAND CODE 15 0 1000011 ooOIOOOJoooo 11 ($ 080 1) COMMAND PARAMETERS 15 0 100011000110001100011 < Color Register> ($ 1 1 1 1) RN=Ol 1514131211109876543210 1000 11000110001 [0001 I Figure C2-1 WPR Execution Example 178 HITACHI I RPR [3] RPR (Read Parameter Register) PAGE RPR-1 < FUNCTION> Read the contents of the Drawing Parameter Registers. TYPE Register Access Command RPR (RN) WORD NUMBER Wn=l COMMAND CODJ: hexadecimal notation o 15 ~ EXECUTION CYCLES ($ 0 COX) Cn=6 5 bits COMMAND PARAMETERS - NON- < DESCRIPTION> The Drawing Parameter Register number to be read is specified in the RN (Register Number) field of the command code. After execution, the contents of the specified Drawing Parameter Register is loaded into the Read FIFO. HITACHI 179 IRPR RPR (Read Parameter Register) PAGE RPR-2 The value $1111 in the Drawing Parameter Register (Color Register 1: CL 1) is loaded into the Read FIFO. COMMAND CODE 15 I0 0 0 0 0/1 1 0 0 10 0 o! 0 0 0 0 1 I ($ 0 C 0 1) COMMAND PARAMETER - NON< Color Register 1 > 0 15 1000 11000 11 000 11 000 1 I 15 § 0 0 11000 11000 11 000 1 1 Figure C3-1 RPR Execution Example 180 HITACHI r------IWPTN [4] WPTN (Write Pattern RAM) PAGE WPTN-1 Write data to the Pattern RAM. TYPE WPTN (PRA) n, 01, 02, ... On Register Access Command WORD NUMBER Wn=n+2 COMMAND CODE hexadecimal notation 15 0 10 0 0 1 11 0 0 01 0 0 0 01 PRA I ($ 1 80 X) EXECUTION CYCLES Cn=4n+8 COMMAND PARAMETERS 0 15 I n (Number of Words) I 15 I 0 01 (Pattem Data) I 0 15 I On (Pattern Data) I < DESCRIPTION> WPTN command is used to write data into the Pattern RAM. Pattern RAM Address (PRA) of $O-$F is allocated to the Pattern RAM and each PRA represents 1 word (16 bits) of pattern RAM. The PRA (Pattern RAM Address) field of the command code selects the Pattern RAM word address at which writing starts. The first parameter is n, the number of words to be written. This is followed by n data words (01 -On). For the 8-bit interface, 1 word is divided into high and low bytes. The pattern data is sent in the order of the high byte, then the low byte. The first parameter n must be set to (the number of words) X 2. (In this case writing in unit of byte is not allowed.) HITACHI JSl IWPTN WPTN (Write Pattern RAM) PAGE WPTN-2 Two words of data, $2314 and $5713, are written to the Pattern RAM beginning at address $B. COMMAND CODE 0 15 I ($ 1 80 B) 0 0 01 0 0 0 010 0 1 0 1 ($ 0 0 0 2) 10 0 0 111 0 0 010 0 0 011 0 1 1 COMMAND PARAMETERS 15 [O=oJ? 01 0 0 0 15 10 0 1 010 0 1 110 0 0 110 1 0 0 1 I0 ($ 2 3 1 4) 0 15 I O}]O 0 I 1 0 1 0 1 1 1 0 0 1 1 I ($ 5 7 1 3) bit o 15 15 Pattern RAM 01--_ _ _ _--1..... LSB I I I I I I I 15 14 13 12 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 11 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 10 04 Figure C4-1 WPTN Execution Example 182 HITACHI rRPTN [5] RPTN (Read Pattern RAM) PAGE RPTN-1 TYPE Register Access Command Read Data from the Pattern RAM. RPTN (PRA) n WORD NUMBER Wn=2 hexadecimal notation COMMAND CODE 15 1 0 0 0 111 1 0 010 0 0 01 0 PRA 1 ($ 1 COX) EXECUTION CYCLES Cn=4n+ 10 COMMAND PARAMETERS 15 rl 0 -------n--(N-u-m--be-r-o-f-w--o-ro-)----~I < DESCRIPTION> RPTN command is used to read the data in the Pattern RAM. Pattern RAM address (PRA) of $O-$F is allocated to the Pattern RAM and each PRA represents 1 word (16 bits) of Pattern RAM. The PRA (Pattern RAM Address) field of the command code select the Pattern RAM word address at which reading starts. The parameter n specifies the number of words to be read. The specified Pattern RAM contents are loaded into the Read FIFO. For the 8 bit interface, 1 word of the pattern RAM is divided into high and the low bytes. The pattern data is put into the Read FIFO in the order of the high byte, the low byte. HITACHI 183 IRPTN RPTN (Read Pattern RAM) PAGE RPTN-2 Two words of data, $2314 and $5713 from the Pattem RAM beginning from address $B is placed in the Read FIFO. COMMAND CODE 15 0 1000111 1 00100001_1~-i2J ($1 COB) COMMAND PARAMETERS 15 0 ~oloooolooooloo 10 I ($0002) bit o 15 15r-----....;, ~ I Pattern RAM "C ~ o ~-------l.. LSS MSS ............ I I I ......... .......... ! ......... .................. ... 15 14 13 12 1 1 0 11 0 0 1 o 11 o 11 0 0 0 1 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 0 10 Read FIFO ~ ~ Figure C5-1 RPTN Execution Example 184 HITACHI lORD [6] ORO (OMA Read) PAGE ORO-1 Transfer data from the frame buffer to the MPU system memory. TYPE Data Transfer Command DRD AX, AY WORD NUMBER Wn=3 hexadecimal notation COMMAND CODE 15 li? EXECUTION CYCLES 0 1 ~~LO_~_~H~l.~~_oE_~~~ COMMAND PARAMETERS I AX 15 I [X~y tJ + (62-68) I .-- AY Cn= (4x+ 8)y+ 12 x=iAXi+1 y=iAYi+1 0 15 ($ 2 400) 0 I < DESCRIPTION> DRD command causes the ACRTC to enter DMA Data Transfer Mode in which the ACRTC will control the external DMAC to transfer data (in unit of words) from the rectangular area in the frame buffer to the MPU memory. The frame buffer data origin must be predefined in the Read Write Pointer (RWPI. The parameters of the command define the frame buffer area to be read in units of physical frame buffer words. At the end of DRD command execution, RWP will be set to RWPe. HITACHI 185 ORO ORO (OMA Read) PAGE ORO-2 Read FIFO RWP CPU Memory ACRTC Frame Buffer • If minus values are set in AX and A Y. the read direction becomes negative. The status of the ACRTC Read FIFO should be checked to insure the Read FIFO is empty before the ORO command is issued. If any data is in the Read FIFO before the ORO command issued. that data is read out incorrectly by the DMAC as the first data of the ORO command. Reading direction (1) X:+. Y:+ 186 HITACHI (2) X:+. Y:- (3) X:-. Y:+ (4) X:-. Y:- IOWT [7] OWT (OMA Write) PAGE OWT-1 TYPE Data Transfer Command Transfer data from the MPU system memory to the frame buffer. DWT AX, AY WORD NUMBER Wn=3 hexadecimal notation COMMAND CODE 15 0 10 0 1 01 1 0 0 0 I0 0 0 0 I0 0 0 0 I ($ 2 8 0 0) EXECUTION CYCLES Cn= (4x+ 8)y+ 16 [X; rJ +34 COMMAND PARAMETERS 15 1 AX 15 I { 0 X = lAX I + 1 y=IAyl+1 I 0 AY I < DESCRIPTION> DWT command causes the ACRTC to enter DMA Data Transfer Mode in which the ACRTC will control the external DMAC to transfer data (in unit of words) from the MPU memory to the rectangular area in the frame buffer. The frame buffer data origin must be predefined in the Read Write Pointer (RWP). The parameters of the command (AX, A Y) define the frame buffer area to be written in units of physical frame buffer words. At the end of DWT command execution, RWP will be set to RWPe. HITACHI 187 DWT DWT (DMA Write) PAGE DWT-2 Write FIFO AY+l RWP System Memory ACRTC Fram e Buffer * For AX and A Y, negative value can also be set. After DWT is issued, no further commands should be issued until the DMA data is transferred and the DWT command terminates. Writing direction (1) X:+, Y:+ 188 HITACHI (2) X:+, Y:- (3) X:-, Y:+ (4) X:-, Y:- IOMOO [8] OMOO (OMA Modify) PAGE OMOO-1 Transfer data from the MPU system memory to the frame buffer subject to logical modification. Data Transfer Command TYPE DMOD (MM) AX, A Y COMMAND CODE 15 0 100101110010000100iMMI hexadecimal notation WORD NUMBER Wn=3 EXECUTION CYCLES ($2COX) cn=(4x+8)Y+16[~ +34 COMMAND PARAMETERS 15 0 I tJ AX { I 15 X = lAX I + 1 y=IAyl+l 0 I AY I < DESCRIPTION> DMOD causes the ACRTC to enter DMA Data Transfer Mode in which the ACRTC will control the external DMAC to modify data in the rectangular area in the frame buffer using data in the MPU memory (in unit of words). The frame buffer data origin must be predefined in the Read Write Pointer (RWP). The parameters of the command (AX, A Y) define the frame buffer area to be written in units of physical frame buffer words. At the end of DMOD command execution, RWP will be set to RWPe. The MM (Modify Mode) field of the command code specifies the DMA data transfer modify mode. Each pixel transferred from MPU system memory is logically operated on the corresponding pixel from the frame buffer, and the result is rewritten to the frame buffer. Logic operation can be enabled and disabled on a bit by bit basis based on the contents of the MASK register. HITACHI 189 DMOD DMOD (DMA Modify) PAGE DMOD-2 AY+l RWP ACRTC Frame Buffer Afrer DMOD is issued. no further commands should be issued until the DMA data is transferred and the DMOD command terminates. 190 HITACHI IRD [9] RD (Read) PAGE RD-1 TYPE Data Transfer Command Read one word of data from the frame buffer and load the word into Read FIFO. RD WORD NUMBER Wn=1 COMMAND CODE 15 hexadecimal notation 0 I0 I 1 0 0 0 1 0 0 10 0 0 0 10 0 0 0 I ($ 4 4 0 0) EXECUTION CYCLES Cn=12 COMMAND PARAMETER - NON- < DESCRIPTION> RD reads one word (16 bits) of data from the frame buffer. The frame buffer address to be read must be predefined in the Read Write Pointer (RWP) before the RD command is issued. The results are loaded into the Read FIFO. The result may be read from the Read FIFO by the MPU anytime after the RD command is issued. If the Read FIFO is full when the command is executed, the ACRTC will enter a wait state until space becomes available in the Read FIFO. At the end of the RD command execution, the ACRTC increments RWP by one. HITACHI 191 IRD RD (Read) PAGE RD-2 DN: RWP: DN Screen Number 00 Upper Screen 01 Base Screen 10 Lower Screen 11 Window Screen 1514 0 I D N I ______ I RWPH (8 bits) I RWPL (12 bits) r____ I~ II D_A_T_A_H (16 bits) . DATAL (16 bits) . • RWPH and RWPL specifies the frame buffer address by setting the linear address of 20 bits. • DN specifies screen numbers. Figure C9-1 RWP Set Read the frame buffer data, $5555, at physical address $56 in screen 0 (upper screen). For this example, Memory Width (MW) is assumed to be $10. RWP 15 0 10 0 0 010 0 0 010 0 0 010 0 0 0 15 I ($ 0 0 0 0) I ($ 0 5 6 0) 0 10 0 0010 1 0 1101 1 010 0 0 0 Figure C9-2 Example of RWP Setting COMMAND CODE 15 0 10 1 0 010 1 0 010 0 0 010 0 COMMAND PARAMETERS - NON- 192 HITACHI ~ ($ 4 4 0 0) /RD RD (Read) Screen: 0 PAGE RD-3 [QQ] 1 2 3 4 5 7 6 8 9 A C B D E F 0 1 2 3 4 RWP 6 (address $56) .. ~ D- 5 Frame buffer data 7 8 9 A o1 0 RWPe (after execution) ~ !to 1 0 110 lOtio 1 0 1 D ($5555) Read FIFO 15 B- o1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ($5555) T- Figure C9-3 RD Execution Example HITACHI 193 /WT , [10] WT (Write) PAGE WT-1 < FUNCTION> Write one word of data to the frame buffer. TYPE WT D hexadecimal notation COMMAND CODE 15 0 10100110001000010000 I ($4800) Data Transfer Command WORD NUMBER Wn=2 EXECUTION CYCLES Cn=8 COMMAND PARAMETERS o 15 L D (16 bits) I ~~_~~----1 < DESCRIPTION> WT writes one word (16 bits) of data to the frame buffer. The frame buffer address to be written must be predefined in the Read Write Pointer (RWP) before the WT command is issued. The command parameter (D) is the data to be written. At the end of the WT command execution, the ACRTC increments the RWP by one. 194 HITACHI lWT WT (Write) PAGE WT-2 ON: RWP ON Screen Number 00 Upper Screen 15 0 o N r~J II 01 Base Screen r-.. J~ DATA H (16 bits) ---- 10 Lower Screen 11 Window Screen f--- RWPH (8 bits) RWPL (12 bits) DATA L (16 bits) • The frame memory is a 20-bit linear address separated into highorder RWPH (8 bits) and loworder RWPL (12 bits!. • Specify the Screen No. where drawing is executed. Figure C10-1 RWP Set Write the 16-bit data word $5555 to frame buffer address $56 on screen 0 (upper screen). For this example, Memory Width (MW) is assumed to be $10. RWP 15 0 I 0000100001000010000 I 15 ($ 0 0 0 0) 0 I0 0 0 010 1 0 110 1 1 01 0000 1 ($ 0560) Figure C10-2 Example of RWP Setting COMMAND CODE 15 0 101001100010000100001 ($ 4 8 00) COMMAND PARAMETERS 15 0 I 0 1 0 110 1 0 110 1 0 110 1 0 11 ($ 5 5 5 5) HITACHI 195 IWT WT (Write) 0 0 1 2 3 4 5 PAGE WT-3 1 2 3 4 5 6 7 RWP 8 9 A B C (Address 56) .. ~ D- RWPe (after execution) 6 7 8 9 101010101010101011 ($5555) A Figure C10-3 WT Execution Example 196 HITACHI D E F IMOD [11] MOD (Modify) PAGE MOD-1 Perform logical operation on one word in the frame buffer. TYPE MOD (MM) D WORD NUMBER Wn=2 COMMAND CODE hexadecimal notation 15 Ia Data Transfer Command 21 1 a a 11 1 a ~ a a a aiM M I ($ 4 C a X) EXECUTION CYCLES Cn=8 COMMAND PARAMETER 15 1r------- a --(1-6-bi-ts-)-------.1 D < DESCRIPTION> The MM (Modify Mode) field of the command code specifies the data transfer modify mode. This command performs logical operation on one word in the frame buffer with the data given the parameter and writes the result back in the frame buffer. The frame buffer word address to be modified must be predefined in the Read Write Pointer (RWP). The word is read from the frame buffer, then the logical operation defined by MM is performed between the data read from the frame buffer and the command parameter (D) for those bits not masked in the MASK register, and the result is rewritten to the frame buffer. At the end of the MOD command execution, the ACRTC increments the RWP by one. HITACHI 197 IMOD MOD (Modify) ON: PAGE MOD-2 RWP: ON Screen Number 00 Upper Screen 01 Base Screen 10 Lower Screen 11 Window Screen 1514 l l oN1 7 0 ______ .1 RWPH (8 bits) RWPL (12 bits) ~ • The frame buffer 20-bit linear address is separated into high order RWPH (8 bits) and loworder RWPL (12 bits). • Specify the Screen No. where drawing is executed. Figure C11-1 RWP Set .. OR all bits of the frame buffer word at physical address $56 with the 16-bit data word $AAAA. MM = 01 specifies OR modify mode. All bits are selected for logical operation byassuming the MASK register to $FFFF. For this example, Memory Width (MW) is assumed to be $10. 198 HITACHI IMOO MOD (Modify) < EXECUTION PAGE MOO-3 EXAMPLE> RWP 15 0 I ($ 0000) I ($ 0 5 6 0) 11 1 1 1 11 1 1 1 11 1 1 1 11 1 1 1 1 ($ F F F F) 10000100001000010000 0 15 10 0 0 0 I0 1 0 11 0 1 1 0 10 0 0 0 MASK 0 15 Figure C11-2 Examples of RWP and MASK Setting COMMAND CODE 15 0 10100111001000000;011 ($4COl) COMMAND PARAMETER 15 0 11 0 1 0 11 0 1 011 0 1 0 11 0 1 0 I ($ A A A A) HITACHI 199 lMOD MOD (Modify) 0 PAGE MOD-4 1 2 3 4 0 1 2 3 4 5 6 7 8 9 A B C 0 10 1 0 110 1 0 110 1 0 110 1 0 E F 1] ($5555) RWP -,/ ~~ 5 6 (A) MOD Command Read Cycle 0 1 2 3 4 5 1 2 3 4 5 6 7 8 9 A B 0 E 111 11'1' 11'1' 11'1' 1111 ~ ~ D- ($FFFF) RWPe (After execution) 6 (B) MOD Command Write Cycle Figure C11-3 MOD Execution Example 200 HITACHI C F IClR [12] ClR (Clear) PAGE ClR-1 Initialize a frame buffer area with a data in the command parameter. TVPE CLR D, AX, AV Data Transfer Command WORD NUMBER Wn=4 COMMAND CODE hexadecimal notation 15 0 [0101[1000[0000[0000[ { COMMAND PARAMETERS 15 ($ 5800) EXECUTION CYCLES Cn= (2x+ 8)y+ 12 X = IAXI+ 1 y=IAVI+1 0 I D (16 bits) I AX (16 bits) I AV (16 bits) 15 I 0 15 I 0 I < DESCRIPTION> The frame buffer area defined by the physical origin (RWP) and physical frame buffer word address (AX and A V) parameters is filled with the data parameter (Dl. Since the ACRTC performs the clear using 1 6 bit words, multiple logical pixels (if 4 bits/ pixel then 4 pixels) are cleared in one access. D is normally specified to contain multiple copies (if 4 bits/pixel then 4 copies) of the color information for a single color clear. At the end of CLR command execution, RWP will be set to RWPe. HITACHI 201 ICLR CLR (Clear) PAGE CLR-2 y AX: 2nd parameter A Y: 3rd parameter (4-bits/pixel) (AX,AY) 1\ AY+l ! I r------ RWP U RWPe \ I I I I AX+l ------- ~ X RWP is set with a 2-word (32-bit) data, as shown in Fig. C12-1. RWP The RWP needs to be specified in advance as follows. 202 HITACHI ICLR CLR (Clear) PAGE CLR-3 DN: RWP: 15 14 DN Screen Number 00 Upper Screen 01 Base Screen DN 7 I =-==----- J RWPH (8 bits) RWPL (12 bits) 10 Lower Screen 11 Window Screen 0 I~ • The frame buffer 20-bit linear address is separated into high order RWPH (8 bits) and low order RWPL (1 2 bits). • Specify the Screen No. where drawing is executed. Figure C12-1 RWP Set For this example 4 bits per logical pixel is used, the Memory Width (MW) is $10 and the clear operation is to start at address $56 on screen O. RWP 15 0 I ($ 0000) 10 0 0 010 1 0 110 1 1 01 0000 1 ($ 0 5 60) 10 0 0 010 0 0 010 0 0 0 0 0 0 0 15 0 Figure C12-2 Example of RWP Setting COMMAND CODE 15 0 101011100010000100001 ($ 5 800) COMMAND PARAMETERS 15 0 I ($ 1 1 1 1) 11 1 1 111 1 1 111 1 1 1 11 1 001 ($ F F F C) 10 0 0 110 0 0 110 0 0 1 10 0 0 1 15 15 11 1 1 1 11 1 1 111 1 1 1 11 0 0 o 1 01 ($ F F FA) HITACHI 203 ICLR CLR (Clear) PAGE CLR-4 10 0 0 o 2 3 4 6 5 7 8 9 A 11 = Clear data (pixel) B o 1 2 3 4 5 5 words r -____ ~A~ ______ ~ ( \ RWP (Address $56) r---------~~"I~ 0001000100010001~ 6 00010001000100010001' 7 00010001000100010001 8 00010001000100010001 9 00010001000100010001 A 00010001000100010001 B ~0001000100010001 Pc (address $B2) >- 7 words L=:t- RWPe (Address $B6) Figure C12-3 CLR Execution Example 7.04 HITACHI C D E ISClR [13] SClR (Selective Clear) PAGE SClR-1 TYPE Data Transfer Command Initialize a frame buffer area with a constant value subject to logical modification. SCLR (MM) D, AX, A Y WORD NUMBER Wn=4 COMMAND CODE hexadecimal notation a 15 10 10 1111 oolooooloolMM I { COMMAND PARAMETERS 15 r - - r ~-~---.--. . 15 ($5COX) EXECUTION CYCLES Cn= (4x+ 6)y+ 12 x=iAXi+ 1 y=iAYi+1 a D (16 bits) a 1,---------A-X-(-1-6-b-it-s)--------~1 15 a c'--_-._-_-_-~-AY-_-~.~-6-_?-its-)--------,1 < DESCRIPTION> The MM (Modify Mode) field of the command code specifies the data transfer modify mode. The frame buffer area defined by the RWP origin and the physical frame buffer word address (AX and A Y) parameters is selectively cleared. The contents of the frame buffer are read, and that data is logically operated on with the 0 parameter (excepts bits masked in the MASK register) using the logical operation defined by MM. The result is rewritten to the frame buffer. Since the ACRTC performs the selective clear using 16-bit words, multiple logical pixels (if 4 bits/pixel then 4 pixels) are cleared in one access. 0 is normally specified to contain multiple copies (if 4 bits/pixel then 4 copies) of the color information for a single color selective clear. At the end of SCLR command execution, RWP will be set to RWPe. HITACHI 205 ISCLR SCLR (Selective Clear) PAGE SCLR-2 < DESCRIPTION> 0 0000 2. 4 Rwpe-I : Modifier information : 1st parameter : 2nd parameter}. . In units of words : 3rd parameter I ooooooooloooOl-Pc 000000000000 000000000000 000000000000 Address location - - - - - . 10000100000000 specified by RWP. ___________ ~ ~ ~ Figure C 13-1 Command Parameter Set The operation is specified by the above operation mode, and is set with bits 1, 0 in the command code. This command can be utilized for clearing the character code, the specific attribute bits, and the specific color plane in the graphic display. The RWP needs to be specified in advance as follows. RWP 15 DN: DN Screen Number 00 Upper Screen 01 Base Screen 10 Lower Screen 11 Window Screen 14 DN 7 0 I ~IJIJPH (8 bits) RWPL (12 bits) I~ • The frame memory is a 20-bit linear address separated into high order RWPH (8 bits) and low order RWPL (12 bits) . • Specify the Screen No. where drawing is executed. Figure C13-2 RWP Set 206 HITACHI ISCLR SCLR (Selective Clear) PAGE SCLR-3 For this example 4 bits per logical pixel is used, the Memory Width (MWI is $10, the MASK register contains $FOFO and the selective clear operation is to start at address $56 on screen O. Based on MM, a logical operation (REPLACE, OR, AND or EORI is defined and SCLR is executed as shown. RWP 15 0 10 oio 010 0 0 010 0 0 010 0 0 01 ($ 00001 1000010 1 0 110 1 1 0100001 ($ 0 5 601 MASK 15 0 rll-1--1~11-0-0-0-0~ll--l-1-1~10-0-0-0~1 ($ F 0 F 01 Figure C13-3 Examples of RWP and MASK Setting Read Data Modifier Data o V \ I Read Data 6 V I \ MM •• Modifier Data MM t Write Data .to Write Data (Unit: pixel) Figure C13-4 Notation of Data HITACHI 207 ISCLR SCLR (Selective Clear) < EXECUTION PAGE SCLR-4 EXAMPLE> COMMAND CODE 15 0 10 1 0 1/1 1 0 0E> 0 0 010 OIMMI ($5 COX) COMMAND PARAMETERS 15 0 __ _ _ 0 0 110 0 0 110 0 0 1 I [~11111 1 1 l1 1111 li>001 ~o ~ ~Io 15 ($ 1 1 1 1) 0 ($ F F F C) 15 0 1111-111 1 1 1 11 1-,-11-1 0 1 0 208 HITACHI I ($FFFA) jSCLR SCLR (Selective Clear) < EXECUTION PAGE SCLR-5 EXAMPLE> 1 pixel I 000 1 I = 1st parameter (Mod ifier Data) "il o o (Modifier data) -- 2 4 3 = l"il"il"il~ ($1111) 5 6 I Mask I 1 2 3 RWP (Address $56) 1 , 5 words 4 l 5 oooooooooooooooopooq'" 6 7 00000000000000000000 00066666666666666000 8 000666666666666~6000 7 9 A 00066~66~~~666~66000 words 6 MM J 00000000000000000000 Pc (Address--JoooOlooooooOOOOOOOOOO ($62) - C (A) o 2 3 4 5 6 o 1 2 3 4 5 .o.o.o.o.o.o.o.o~o.o,~--~ 6 .0.0.0.0.0.0.0.0.0.0 7 .0.~A6A6A6A6A6A6AO.O 8 .0.6A6A6A6A6A6A6AO.O 9 .0.~A6A~A6A~A6A6AO.O A 6 .0.0.0.0.0.0.0.0.0.0 .0.0.0.0.0.0.0.0.0.0 C I !-RWPe (Address $C6) (6) Figure C 13-5 SCLR Execution Example HITACHI 209 ICpy [14] Cpy (Copy) PAGE CPY-1 Copy frame buffer data from one area (source area) to another area (destination area). CPY (S, DSD) SAH, SAL, AX, A Y I0 hexadecimal notation 12111087 I 0 I 1 1 0 SiD S D 0 0 0 0 10 0 0 0 I 15 87 [0000 -0 0 0 0 0 I SAH (8 bits) 15 SAL (12 bits) 10000 I AX (16 bits) I ---~-- . 1 0 - - I I EXECUTION CYCLES Cn= (6x+ 10)y+ 12 0 15 15 ($ 6 X 0 0) Jx = IAXI+ 1 Lv=IAYI+1 COMMAND PARAMETERS I Data Transfer Command WORD NUMBER Wn=5 COMMAND CODE 15 TYPE __._---" AY (16 bits) - 0 I < DESCRIPTION> The parameters to the command define the source area. The RWP must be predefined to point to the destination area (including screen number). The source area resides in the same screen as that of the destination area as defined in RWP. The source area is defined by the origin address (SAH/SAL) and physical frame buffer word (AX and A Y) dimensions. To allow rotation and proper operation for overlapping during copying, the command code contains fields which define the source and destination scanning direction. The S (Source Scan Direction) and DSD (Destination Scan Direction) fields of the command code define the source and destination scanning direction respectively as shown next page. At the end of the CPY command, RWP is set to RWPe. 210 HITACHI ICpy Cpy (Copy) PAGE CPY-2 Pss: 15 0 1==-=====--==1 r (1) SAL (12 bits) SAH ~ _ Pss (SAH. SAL) is set to be a 20-bit linear address separated into 2 words, high order SAH (S bits) and low order SAL (12 bits). ON: RWP: 15 ON Screen Number 00 Upper Screen t---t---::---01 Base Screen r--10 lower Screen 11 Window Screen 14 ON 7 0 I ~_RWPH(Sbits) RWPl (12 bits) I~ The frame buffer 20-bit linear address is separated into high order RWPH (S bits) and low order RWPl (12 bits). Specify the Screen No. where drawing is executed. Figure C14-1 Pss and RWP Set HITACHI 211 ICpy Cpy (Copy) PAGE CPY-3 < CPY Command Scan Direction> As to CPY, the direction of pointer scanning is specified in command code. (The pointer functions in the unit of word). (a) Scanning Direction of Source Area (S: Source Scan Direction) COMMAND CODE 15 11 L_~_L 0 1 Talbe C14-1 Source Scan Direction S=O Q EJ [;g IT] S = 1 ill ill Ell ill : Pss CJ : Pse As shown in Table C 14-1, the scanning direction in frame buffer of the copy source area is decided by the relation between bit 11 in the command code and the Pss and the Pse. (a) Scanning Direction of Destination Area (DSD: Destination Scan Direction) COMMAND CODE 15 1098 1 ID S DI 212 HITACHI 0 I ICpy Cpy (Copy) PAGE CPY-4 Table C14-2 Destination Scan Direction DSD = 000 DSD = DSD 001 = 010 cg ETI 8 0 0 = 100 DSD = 101 DSD = = 011 IT] 0 DSD DSD 0 110 DSD = 111 18 lIT Ell 1] _ : RWP 0 : RWPe As shown in Table C14-2. the scanning direction in frame buffer of the destination area is decided by the relation between bit 10 to 8 in the command code and the RWP. Upon termination of the command. RWPe. end point of the RWP moves as shown in Table C14-2. Relation to Linear Address Fig. C 14-2 provides the relation between CPY and specified value when S = 1 and DSD = 000. RWPe (Linear Address) I IRWPHIRWPLI-I AX x MW 1-1 MW Pse (Linear Address) 11 II SAH I SAL rf mI w ~ Q mm ~ 1+[gJ-1 AY x Mwi / ~} AY AX ~ ~ I SAH ISALll Pss (Linear Address) IIRWPHIRWPLII RWP (Linear Address) (Source Area) Figure C 14-2 Relations with Linear Addresses HITACHI 213 Icpy Cpy (Copy) PAGE CPY-5 For this example 4 bits per logical pixel is used, the Memory Width (MW) is $10 and the copy operation source area (SAH/SAL) start is frame buffer address $89 while the copy destination area (RWP) start is frame buffer address $80 on screen O. The source area scanning direction is specified as S = 1 and the destination area scanning direction is specified as DSD = 000. RWP 15 ~i~_~Io~oOoJoo~o a 919 a a 0 I a a 00) ($ a 8 a 0) a 15 ~~~_~1~! ]J~~o-~o ($ 010 aa0 I Figure C14-3 Example of Read Write Pointer Setting COMMAND CODE a ~_i~~Elo a _oJ~~o a 10 a a a 1 15 ($ 6 8 a 0) COMMAND PARAMETERS a [OYooro~~~~-?I§j_ O~O a a 0 I 15 15 10 a a ? 9.Jl~_~~?I~_O~O~l 10 a a a a ?--~[o 00 a [o_o_-:?mO10 a 15 ioo~~91()() -()OlO_~~O?IO 214 HITACHI a a 00) 1 ($ a8 9 0) I ($ a0 03) a 15 10 ($ 1 1 a 1 1 0 1 a ($ 0 06) Cpy Cpy (Copy) PAGE CPY-6 1 0 4 3 2 5 6 7 8 A 9 B 0 1 2 3 4 5 6 • • • • • • • • 0000 • • • • • • • • 00000000 • • • • • • • • 0000 7 8 9 A (A) B 1 0 4 3 2 5 6 7 8 9 A C B 0 1 Pse (Address $2C) 2 3 4 5 6 7 ..... •••• •••• pooo •••• ~ pooo 10 00 01 ~OO~ •••• RWPe (Address $70) ~ :-+, t2 8 9 A B .... •••• ..., '0000 171 ! RWP L! ~ ill / Pss (Address $89) 0000 oo~ 00001 ,1 ~ (Address $BO) (B) Figure C14-4 Example of CPY Execution HITACHI 215 I PAGE ~CPY-1 [15] SCPY (Selective Copy) Copy frame buffer data from one area (source area) to another area (destination area) subject to logical modification. The source and destination areas must reside on the same screen. SCPY(S,DSD,MM)SAH,SAL,AX,AY COMMAND CODE 15 111087 10 1 1 1 1S 10 solo 210 0 0 0 0 01M M 1 COMMAND PARAMETERS 15 I0 0 0 0 0 0 0 0 I I WORD NUMBER Wn=5 ($7XOX) EXECUTION CYCLES Cn= (6x+ 1O)y+ 12 { X = y= lAX I+ IAyl+ 1 1 10000 1 0 AX (16 bits) 15 I I hexadecimal notation TYPE Data Transfer Command 0 SAL (1 2 bits) 15 I 0 SAH (8 bits) 15 SCpy I 0 AY (16 bits) I < DESCRIPTION> The parameters to the command define the source area. The RWP must be predefined to point to the destination area (including screen number). The source area resides in the same screen as that of the destination area as defined in RWP. The source area is defined by the origin address (SAH/SAL) and physical frame buffer word (AX and A Y) dimensions. To allow rotation and proper operation for overlapping during copying, the command code contains fields which define the source and destination scanning direction. The S (Source Scan Direction) and DSD (Destination Scan Direction) fields of the command code define the source and destination scanning direction respectively as shown next page. The MM (Modify Mode) field of the command code specifies the data transfer modify mode. Based on MM, logical operation is performed (except for bits masked in the MASK register) between the source data and the destination data, and the result is written to the destination. At the end of the CPY command, RWP is set to RWPe. 216 HITACHI I SCPY SCPY (Selective Copy) PAGE SCPY-2 The source address and Read/Write Pointer need to be specified as follows prior to the execution. Pss: 15 0 _______ .1 SAH (8 bits) (1) 1 I~ SAL (12 bits) Pss (SAH, SAL) is set to be a 20-bit linear address separated into 2 words, high order SAH (8 bits) and low order SAL (12 bits). RWP: ON: 15 00 Upper Screen 01 Base Screen _ 14 7 ONI ______ ON Screen Number .. _ - - - 1 0 RWPH (8 bits) 1 RWPL (12 bits) I~ f---+-- 10 ! Lower Screen 11 Window Screen The frame buffer 20-bit linear address is separated into high order RWPH (8 bits) and low order RWPL (12 bits). Specify the Screen No. where drawing is executed. Figure C15-1 Pss and RWP Set HITACHI 217 Iscpy SCpy (Selective Copy) PAGE SCPY-3 < SCPY Command Scan Direction> As to SCPY, the direction of pOinter scanning is specified in command code. (The pointer functions in the unit of word) (a) Scanning Direction of Source Area (S: Source Scan Direction) COMMAND CODE 15 I 11 IS I 0 I Table C15-1 Source Scan Direction s=o 8 IT] ~ EEJ ill 18 Ell BJ S = 1 • :Pss D : Pse As shown in Table C 15-1, the scanning direction in frame buffer of the copy source area is decided by the relation between bit 11 in the command code and the Pss and the Pse. 218 HITACHI JSCPY SCPY (Selective Copy) (b) PAGE SCPY-4 Scanning Direction of Destination Area (DSD: Destination Scan Direction) COMMAND CODE a 10 9 8 15 ID S DI 1 1 Table C15-2 Destination Scan Direction DSD = 000 D ~ DSD = 100 DSD = 001 DSD = 010 DSD = 011 0 ETI ~ EJ D DSD 0 = 101 [l LET DSD = 110 DSD - 111 fIl TIT • :RWP o : RWPe As shown in Table C15-2. the scanning direction in frame buffer of the destination area is decided by the relation between bit 10 to 8 in the command code and the RWP. Upon termination of the command. RWPe. end poin( of the RWP moves a') shown in Table C15-2. The operation is decided by the modify mode (MM) and is specified by bit "a" or "1" in the command code. HITACHI 219 ISCPY SCPY (Selective Copy) PAGE SCPY-5 Relation to Linear Address Fig. C 15-2 provides the relation between SCPY and specified value when S = 1 and DSD = 000. Pse (Linear Address) \I SAB I SAL I+~-I ~ f :m L}AYHI I SAB ISAL .r IRWPH IRM'L II Pss (Linear Address) II RWP (LI near Address) Read Data ~ Modifier Data ~ \ I v / MM I ! I\!II Write Data RWPe (Linear Address) Figure C15.. 2 Relations with Linear Addresses 220 HITACHI AYXMW]I ISCPY SCPY (Selective Copy) PAGE SCPY-6 < EXAMPLE> For this example 4 bits per logical pixel is used, the Memory Width (MW) is $1 0, the MASK register contains $FaFa and the copy operation source area (SAH/SAL) start is frame buffer address $85 while the copy destination area (RWP) start is frame buffer address $Ba on screen a. The source area scanning direction is specified as S = 1 and the destination area scanning direction is specified as DSD = 000. RWP a 15 10 a 1a a a a a a 10 a a a 10 a a a 1 ($ a a a 0) a 15 10 a a a 11 a 1 1 10 a a a 10 a a 01 ($ a B a 0) MASK a 15 11 1 1 1 10 a a a 11 1 1 1 10 0 0 0 1 ($ F 0 F 0) Figure C15-3 RWP and MASK Setting Read Data o Modifier Data Modifier Data Read Data 'i1 ~ MM MM I • Write Data A " (Unit: pixel) Write Data Figure C15-4 Operation of SCPY HITACHI 221 ISCPY SCPY (Selective Copy) COMMAND CODE 15 PAGE SCPY-7 0 ! 10 1 1 1 11 0 0 0 10 0 0 0 0 0 1M MI COMMAND PARAMETERS 15 ,0 100001000010000100001 15 ($0001) 0 10000§000100001 0110 1 222 HITACHI ($ 08 50) 0 10 0 0 010 0 0 010 0 0 010 0 0 11 15 ($ 0000) 0 1000011 0001 0 1 0 1100001 15 ($780X) ($ 0006) SCpy SCPY (Selective Copy) PAGE SCPY-8 o 2 5 4 3 7 6 o 1 2 vvvvvvvv 3 4 VVVVVVVV 5 vv'Vv'V'Vv'V'V'V'Vv 6 'V 'V 'Vv 'V 'V 'V 'V 7 8 9 A B 6666000066660000666600006666 0000666600006666000066660000 C I (A) o 2 4 5 0001 I " Before Execution of SCPY 3 1 pixel 'V (modifier Data) 6 o Pse (Address $26) 7 1st Parameter ($1111 ) II (Modifier Data) 2 3 4 5 6 7 RWPe (Address $90) Pss (Address 8 9 A IH!l.AA B 0000 C t RWP (Address $BO) (B) After Execution of SCPY Figure C1S-S Example of SCPY Execution HITACHI 223 IAMOVE [16] AMOVE (Absolute Move) PAGE AMOVE-1 Move the Current Pointer (CP) to an absolute logical pixel X-Y address. TYPE Graphic Command AMOVE X, Y WORD NUMBER Wn=3 hexadecimal notation COMMAND CODE 15 11 0 00a 10 a a a 10 a a 010 a a 9 ($ 8 a a 0) EXECUTION CYCLES Cn=56 COMMAND PARAMETERS 15 I 0 I X (16 bits) a 15 I I Y (16 bits) < DESCRIPTION> The parameters (X, Y) of the AMOVE command specify the new value for the CPo The address is specified using logical pixel X-Y addresses relative to the \origin defined by the ORG command. y Pe (X, y) CP(A,fr:,///// /~~~ ;y/ f\ I; Y I/ --1E::'/A:=-",-,-Y_~I/- x ORG( 0,0) ---- X----- Figure C16-1 Function of AMOVE Command 224 HITACHI IAMOVE AMOVE (Absolute Move) PAGE AMOVE-2 If CP = (-13, -10) and AMOVE command is executed with parameters (X, Y) 2), then the CP is set to Pe as shown below. = (10, COMMAND CODE 15 0 11 0 0 0 10 0 0 0 10 0 0 0 10 0 0 0 I ($ 8000) COMMAND PARAMETERS 15 0 11 0 0 0 10 0 0 0 10 0 0 0 11 0 1 0 15 I ($OOOA) 0 ($ 0002) 100001000010000100 1 01 y Pe(l0.2) ORGe 0,0) .. 4 x Figure C16-2 Example of AMOVE Execution HITACHI 225 IRMOVE [17] RMOVE (Relative Move) PAGE RMOVE-1 Move the Current Pointer (CP) to a relative logical pixel X-Y address. ) TYPE RMOVE dX. dY Graphic Command WORD NUMBER Wn=3 COMMAND CODE hexadecimal notation 15 0 ($ 8 400) 110001010010000100001 EXECUTION CYCLES Cn=56 COMMAND PARAMETERS 15 I 0 I dX (16 bits) 15 I 0 I dY (16 bits) < DESCRIPTION> The parameters (dX. dY) of the RMOVE command are used to calculate the new value for the CPo The address is specified using logical pixel X-V displacements relative to CPo Y Pe (A+dX. B+dY) . .- .-'- .- ... ~ CP(A.B) .... .-....... ..-.-.- .. / I\- dY IJ dX----- B ORG( o. 0) ",A __ V x Figure C17-1 Function of RMOVE 226 HITACHI IRMOVE RMOVE (Relative Move) PAGE RMOVE-2 If CP 13, - 10) and RMOVE command is executed with parameters lX, Y) then the CP is set to Pe as shown below. = (- = (10, 2), COMMAND CODE 15 0 ($ 8400) 11 0 0 0 10 1 0 0 10 0 0 0 10 0 0 01 COMMAND PARAMETERS 0 15 10 0 0 0 10 0 0 0 10 0 0 0 11 0 1 01 dX ($ 0 0 0 A) 15 0 10 0 0 0 10 0 0 010 0 0 010 0 1 01 dY ($ 0 0 0 2) y ___________O_R_G_(_O_._O)~~--------------X Pee - 3 ,- 8) CP(-13,-lO) _~ O<=:O~ Figure C17-2 Example of RMOVE Execution HITACHI 227 IALINE [18] ALINE (Absolute Line) PAGE ALlNE-1 Draw a straight line from CP to a command specified end point. TYPE ALINE (AREA, COL, OPM) X, Y WORD NUMBER Wn=3 COMMAND CODE 15 Graphic Command hexadecimal notation 87 54 32 0 11 0 0 0 11 0 0 0 IA~EA 1COL 1OPM 1 ($88XX) EXECUTION CYCLES Cn=P·L+ 18 COMMAND PARAMETERS 15 I 0 I X (16 bits) 15 I 0 Y (16 bits) 1 < DESCRIPTION> The parameters (X, Y) define the line end point as absolute logical pixel X-Y addresses relative to the origin defined with the ORG command. As the line is drawn, CP is moved to Pe. However, the logical pixel at position Pe is not drawn. y Pe(X. Y) Y 1\ CP(A.B) /\\ y x Vx -------- Figure C18-1 Function of ALINE 228 HITACHI ALINE ALINE (Absolute Line) PAGE ALlNE-2 If CP = (- 13. - 10) and ALINE command is executed with parameters (X. Y) = (1 0.2). then a line is drawn and CP is set to Pe as shown below. COMMAND CODE 15 11 a 01 AREAl COL 1OPM 1 87 a a all a a 54 32 ($ 88 XX) COMMAND PARAMETERS a a all a a 1 01 X ($ a a a A) Ia a a 01 a a a 01 a a a 01 a a a 1 01 Y ($ a a a 2) 15 1a 01 a a a 15 a a 01 a y 2 -13 Pe(l0.2) x ORG(O.O) I I 10 I I I I I I I I CP(-13.-tO) , I I - -10 Figure C18-2 Example of ALINE Execution HITACHI 229 I RUNE [19] RLINE (Relative Line) PAGE RUNE-1 Draw a straight line from CP to a command specified end point. TYPE RliNE (AREA, COL, OPM) dX, dY WORD NUMBER Wn=3 COMMAND CODE 15 Graphic Command hexadecimal notation 87 54 32 0 11 0 0 01 1 1 0 OIAREA ICOL IOPMI ($ 8 C X X) EXECUTION CYCLES Cn=P·L+ 18 COMMAND PARAMETERS 0 15 I dX (16 bits) 15 I I 0 dY (16 bits) I < DESCRIPTION> The parameters (dX, dY) define the line end point as relative logical pixel X-Y displacements from the CPo As the line is drawn, CP is moved to Pe. However, the logical pixel at position Pe is not drawn. Figure C19-1 Function of RLINE 230 HITACHI JRLlNE RLiNE (Relative Line) PAGE RLlNE-2 < EXAMPLE> = If CP (-13. -10) and RUNE command is executed with parameters (dX. dY) then a line is drawn and CP is set to Pe as shown below. = (10.2). COMMAND CODE 15 87 11 a a of, 1 1 54 32 a a of AREA ICOL IOPM I ($ 8 C XX) COMMAND PARAMETERS a 15 10 a a 010 a a 010 a a 011 0101 ($ aa ($ a a 02) OA) a 15 10 a a 010 a a 01 a a a 010 a 1 01 y ~13 x -3 : I ORG(O.O) I I I I I I ~ ____ -8 '~Pe(-3.-8) ...... ..:... . . _________________ -10 -- CP(-13. -10) Figure C19-2 Example of RLINE Execution HITACHI 231 IARCT [20] ARCT (Absolute Rectangle) PAGE ARCT-1 Draw a rectangle defined by CP and the command specified diagonal point. TYPE Graphic Command ARCT (AREA, COL, OPM) X, Y WORD NUMBER Wn=3 COMMAND CODE 15 11 hexadecimal notation 8 7 00 11 00 5 4 3 2 0 0 OIAREA ICOl IOPM I ($90XX) EXECUTION CYCLES Cn= 2p(A+ B)+ 54 COMMAND PARAMETERS 0 15 I I X (16 bits) 0 15 I I Y (16 bits) < DESCRIPTION> The parameters (X, Y) define the diagonal point of the rectangle as absolute logical pixel X-V addresses relative to the origin defined by the ORG command. As the rectangle is drawn, CP is moved to Pe (which is the same a~ CPl. However, the logical pixel at position Pe is not drawn. Drawing starts in the X direction first, and is drawn in the direction shown below. The initial X direction is determined by the relationship between CP and (X, V). PeCX-, Y, 1)"'A,8) '\ -----II;Y Pe /.JF--\ (A,B) 1\ B 1 ORG(O,o) A lJ ------- ---- x - - - - Figure C20-1 Function of ARCT 232 HITACHI ARCT (Absolute Polyline) PAGE ARCT-2 If CP = (6, - 6) and ACT command is executed with parameters (X, Y) = (- 16, 10). then a rectangle is drawn and CP is set to Pe as shown below. Drawing starts from the X-axis direction. COMMAND CODE 15 87 54 32 0 I I I 11 0 0 11 0 0 0 01 AREA COL OPM ($ 90 XX) COMMAND PARAMETERS 15 0 11 1 1 111 1 1 111 1 1 1 [0 0 001 15 ($ F F F 0) 0 10 0 0 010 0 0 010 0 0 011 0 1 01 ($ 00 OA) y 10 x ORG(O,O) IvpeC6.-6) oo>eeeeeeeeae9S<9S<~9&9-·,..,eet~ PC 6 ,- 6) Figure C20-2 Example of ARCT Execution HITACHI 233 lRRCT [21] RRCT (Relative Rectangle) PAGE RRCT-1 Draw a rectangle defined by CP and the command specified diagonal point. TYPE Graphic Command RRCT !AREA, COL, OPM) dX, dY WORD NUMBER Wn=3 COMMAND CODE 15 hexadecimal notation 87 54 32 0 11 00 110 1 0 .01 AREAl COLI OPMI ($94XX) EXECUTION CYCLES Cn=2P(A+B)t54 COMMAND PARAMETERS 0 15 .------d-X-(1-6-b-im-)----~1 15 0 ~I------d-Y-(1-6-b-im-)----~1 < DESCRIPTION> The parameters (dX, dY) define the diagonal pOint of the rectangle as relative logical pixel X-Y displacemenm from the CPo As the rectangle is drawn, CP is moved to Pe. However, the logical pixel at position Pe is not drawn. Drawing stam in the X direction first. and is drawn in the direction show below. The initial X direction is detennined by the relationship between CP and (dX, dY). r--_ _---P-c(..... A.~dX. B+dY) 1\ CP(A,B) I dY J / II (X~Bf.....~\::---d-X--~/ B ORG(O,O) A,,) Figure C21-1 Function of RRCT 234 HITACHI IRRCT RRCT (Relative Rectangular) PAGE RRCT-2 If CP (6, - 6) and RRCT command is executed with parameters (dX, dY) = (- 16, 10), then a rectangle is drawn and CP is set to Pe as shown below. = COMMAND CODE 15 87 54 32 0 ($ 94 XX) 11 00 110 1 0 OIAREA ICOll OPMI COMMAND PARAMETERS 15 0 11 1 1 111 1 1 111 1 1 110 0 0 01 dX ($ F F F 0) 15 0 I 10 0 0 0 10 0 0 0 0 0 0 011 0 1 01 dY ($ 0 0 0 A) y _______________ ~0~-O-R-G-(-0.-0-)~--~r_--------------------X 10 ~ ~----. ----16 ~~e(6.-6) CP(6,-6) -~~ Figure C21-2 Example of RRCT HITACHI 235 IAPLL [22] APLL (Absolute PolyUne) PAGE APLL-1 Draw a polyline (multiple contiguous segments) from the CP through command specified points. TYPE Graphic Command APLL (AREA, COL, OPM) n, Xl, Y 1 ••• Xn, Yn WORD NUMBER Wn=2n+2 COMMAND CODE 15 hexadecimal notation 8 7 5 4 3 2 0 11 0 0 111 0 0 0 IAREA ICOL I OPMI ($ 9 8 X X) COMMAND PARAMETERS 15 I 0 n (16 bits) 15 I 0 Xl (16 bits) 15 I I Pn-1 I 0 Xn (16 bits) 15 I P2 I 0 Yn- 1 (16 bits) 15 I I 0 Xn- 1 (16 bits) 15 I I 0 Y2 (16 bits) 15 I P1 0 X2 (16 bits) 15 I I 0 Yl (16 bits) 15 I I I 0 Yn (16 bits) Pe I P2n+ 1 n is specified by the absolute value of a 1 6-bits binary number. 236 HITACHI EXECUTION CYCLES Cn=I(P·L+ 16j+8 APLL APLL (Absolute Polyline) PAGE APLL-2 < DESCRIPTION> The first parameter (n) specifies the number of line segments, that is, n = 1 specifies one line segment. The following parameters (Xn, Vn) are absolute logical pixel X-V addresses, which specify each segments end point relative to the origin defined by the ORG command. As the polyline is drawn, CP is moved to Pe. However, the logical pixel at position Pe is not drawn. y x ORG(O,O) Figure C22-1 Function of APLL HITACHI 237 APLL APLL (Absolute Polyline) PAGE APLL-3 < EXECUTION EXAMPLE> If the CP is at (- 8, - 6) on the split screen, n is set to 3, X 1 to - 4, Y 1 to 4, X2 to 8, Y2 to 6, X3 to 16 and Y3 to - 8, then the APLL command draws a poly line as shown below. COMMAND CODE 15 87 54 32 0 I I 11 0 0 111 0 0 01 AREAl COL OPM COMMAND PARAMETERS 15 0 I 0 0 0 01 0 0 0 01 0 0 0 01 0 0 1 1 1 15 ($ 0003) 0 1--1-1-1~11-1-1~11-1-1-1-1~11--0~01 ($ F F F C) rl 0 15 I 0 0 0 01 0 0 0 01 0 0 0 01 0 15 I 0 0 0 01 0 0 0 01 0 0 0 011 15 1 0 0 0 0 0 0 I ($ 0004) I ($ 0008) 0 ($ 0006) 10000100001000010 1 1 01 15 0 I 0 0 0 01 0 0 0 01 0 0 0 11 0 0 0 0 I 15 ($ 00 1 0) 0 ($ F F F 8) 11111111111111110001 y P2(8,6) x Pe(16,-8) Figure C22-2 Example of APLL Execution 238 HITACHI IRPLL [23] RPLL (Relative Polyline) PAGE RPLL-1 RPLL command draws a polyline which connects the Start point, current painter, and each relative coordinate point. TYPE Graphic Command RPLL (AREA, COL, OPM) n, dX I, dY I, ... dXn, dYn WORD NUMBER Wn=2n+2 COMMAND CODE 15 hexadecimal notation 87 0 54 32 C 11 0 0 111 1 0 0 IAREA 1COL 1OPM 1 ($ 9 8 X X) EXECUTION CYCLES Cn=~ (P·L+ 161+8 COMMAND PARAMETERS 15 I 0 n (16 bits) 15 I 0 dXl (16 bits) 15 1 dY 1 (16 bits) dX2 (16 bits) dY 2 (16 bits) dXn-l (16 bits) dYn-l (16 bits) I Pn-l I 0 dXn (1 6 bits) 15 I P2 I 0 15 I 1 0 15 I I 0 15 I PI 0 15 I 1 0 15 I I I 0 dYn (16 bits) Pe I P2n+ 1 Set "n" in binary absolute values of 16 bits. HITACHI 239 IRPLL RPLL (Relative Polyline) PAGE RPLL-2 < DESCRIPTION> As shown in figure below. the relative poly line command (RPLL) draws a poly line which connects the Start point CPo and each relative coordinate (P 1. P2. P3•.....• Pn- 1. Pel. The total number of points is set in the 1st command parameter (n 1). X and Y components of each point are set in the command parameters in the order the lines are drawn. CP moves to the End point Pe as the lines are drawn. However. a dot is not drawn at Pe. (X.,Y.):(A+dX.,B+dY.) (Xz,Yz):(X.+dXz,Y.+dYz) (X.,Y.):(Xz+dX.,Y.+dY.) (Xn-.,Yn-.):(Xn-.+dXn-.,Yn-.+dYn-.) (Xn,Yn):(Xn-.+dXn,Yn-.+dYn) y (x. p. ,Y.) dX. i ___ dXn ~~---,IddYY:3 PI(Xt ,YI) -~= dY. P(X CP(A,B~~I dY I dX 2 ~ .r- .... -~ ~~ .... 3 3, Y) 3 IJ x A--' Figure C23-1 Function of RPLL 240 HITACHI Pe(Xn,Yn) dXl B ORG(O,O) IdYn Pn-1(Xn-I,Yn-I~ IRPLL RPLL (Relative Polyline) PAGE RPLL-3 < EXECUTION EXAMPLE> If the CP is at (- 8, - 6) on the split screen, dX 1 is set to - 4, dY 1 to 4, dX2 to 8, dY 2 to 6, dX3 to 16 and dY 3 to - 8, then the RPLL command draws a poly line as shown below. COMMAND CODE 15 87 54 32 0 ($ 9 C XX) 11 0 0 1 11 1 0 0IAREA I COL I OPM I COMMAND PARAMETERS 15 0 I0 0 0 0 10 0 0 0 10 0 0 0 10 0 1 1 I 15 ($ 0003) 0 ($ F F F C) 11 1 1 111 1 1 1 11 1 1 111 1 0 01 15 0 ($ 0004) 1 00 001 00 001 00 001 0 1 001 15 0 ($ 0008) 10000100001000011 0001 15 0 ($ 0006) 1 0 0 0 01 0 0 0 010 0 0 010 1 1 01 15 0 ($ 0 0 1 0) I 0 0 0 01 0 0 0 01 0 0 0 1 10 0 0 01 15 0 111111111 1 11 1 1 1 11 0 0 01 ($ F F F 8) y p. (-4.,4.) ~8 I 6 _______ ~ I-- 16 ~ /~ ~ \ / PI (-12,-2) '~PH'-') 1\ ORGNJ x (0,0) Pe(l2 ,-4.) Figure C23-2 Example of RPLL Execution HITACHI 241 IAPLG [24] APLG (Absolute Polygon) PAGE APLG-1 APLG draws a polygon which connects the initial point, CP, and each absolute coordinate. TYPE Graphic Command APLG (AREA, COL, OPM) n, X" Y, ..... Xn, Yn WORD NUMBER Wn=2n+2 COMMAND CODE 15 hexadecimal notation 8 7 5 4 3 2 0 11 0 1 010 0 0 olAREAI COLI OPMI ($A 0 XX) COMMAND PARAMETERS 15 I 0 n (16 bits) 15 I 0 X, (16 bits) 15 I Y, (16 bits) X2 (16 bits) Y2 (16 bits) Xn-1 (16 bits) Yn-1 (16 bits) Xn (16 bits) Pn-1 I I 0 Yn (16 bits) Pm+1 Set "n" in binary absolute values of 16 bits. 242 HITACHI I 0 15 I P2 I 0 15 I I 0 15 I I 0 15 I p, 0 15 I I 0 15 I I I Pn EXECUTION CYCLES Cn=! {P'L + 16} + P'LO+ 20 APLG APLG (Absolute Polygon) PAGE APLG-2 < DESCRIPTION> y Pn-I (Xn- I • Yn-, ) Xn Figure C24-1 Function of APLG As shown in above figure. the APLG command draws a polygon line which connects the start point. CPo and each absolute coordinate (P,. P2 ...... Pn-l. Pn). then back to CPo The total number of pOints are set in the first command parameter. X and Y components of each point are set in the command parameters in the order the lines are drawn. CP moves to the end point CPe to draw a poly line. However a dot is not drawn at Pe. CP is the same point as Pe. HITACHI 243 APLG APLG (Absolute Polygon) PAGE APLG-3 If the CP is at (- 8, - 6) on the split screen, n is set to 3, X 1 to - 4, Y 1 to 4, X2 to 8, Y 2 to 6, X3 to 16 and Y3 to - 8 in the command parameter. The APLG command draws a polygon line as shown below. COMMAND CODE 15 0 11 0 1 010 0 0 01 AREAl COL 1OPMI ($A a XX) COMMAND PARAMETERS 0 15 I 0 0 0 01 a a a 01 a 0 a 01 a a 1 11 ($ a a 03) a 15 11 1 1 111 1 1 111 1 1 111 0 01 ($ F F F C) a 15 1a a a 01 a a a 01 a 0 a 01 a 1 a 01 ($ a a 04) ($ a a 08) ($ a a 06) ($ aa a 15 1a 0 a 01 a a a 01 a a a all a a 01 a 15 1a a a 01 a a a 01 a a a 01 a 1 1 01 a 15 1a a a 01 a a a 01 a 0 a 11 a a a 0\ 15 11 1 1 111 1 , ,1, 1 1 111 a a 0 aI 1 0) ($ F F F 8) y p. (8,6) ----------~~~~----~--~--/K---x P 3 (l6,-8) Figure C24-2 Example of APLG Execution 244 HITACHI IRPLG [25] RPLG (Relative Polygon) PAGE RPLG-1 APLG draws a polygon which connects the initial point. CP, and each relative coordinate. TYPE Graphic Command RPLG (AREA, COL, OPM) n, dX" dY " ... dXn, dYn WORD NUMBER Wn=2n+2 hexadecimal notation COMMAND CODE 15 11 87 a 1 010 1 54 32 a 01 AREAl COLI a OPMI ($A4XX) COMMAND PARAMETERS a 15 I n (16 bits) I a 15 I I dX, (16 bits) a 15 I a I dX2 (16 bits) a 15 I a dXn- 1 I (1 6 bits) 15 I dYn-l (16 bits) I a dXn (16 bits) I a 15 I Pn-l a 15 I P2 I dY 2 (16 bits) 15 I P, I dY, (16 bits) 15 I EXECUTION CYCLES Cn=I{P'L+ 16}+P'LO+20 dYn (16 bits) Pn I P2n+ 1 Set "n" in binary absolute values of 1 6 bits. HITACHI 245 IRPLG RPLG (Relative Polygon) PAGE RPLG-2 < gESCRIPTION > (Xl, Yl): (A+dXI, B+dYI) Y (X2, Y2): (XI+dX2, YI+dY2) (X3, Y3): (X2+dX3, Y2+dY3) (Xn-l, Yn-l): (Xn-2+dXn-I, Yn-2+dYn-l) (Xn, Yn): (Xn-l+dXn, Yn-l+dYn) p. (x., Y.) dX. d~ dX I ~ dYI CP [\ Pn -I (Xn -I , Yn-I) dXn dXs Y,'3 L~ X. , ", PI ( YI ) ..p"'" ~dYn Ps ( Xs ' Ys ) Pn(Xn, Yn) Pe (A, B) (A,B B ORG(O,O) x l! Figure C25-1 Function of RPLG As shown in above figure, the RPLG command draws a polygon line which connects the start point. CP, and each related coordinate (P 1, P2, P3, "., Pn - l , Pnl. then back to CPo The total number of points are set in the first command parameter. X and Y components of each point are set in the command parameters in the order the lines are drawn. CP moves to the end point Pe as the lines are drawn. However a dot is not drawn at Pe. CP is the same point as Pe. 246 HITACHI IRPLG RPLG (Relative Polygon) PAGE RPLG-3 If the CP is at (- 8, - 6) on the split screen, n is set to 3, dX 1 to - 4, dY 1 to 4, dX2 to 8, dY 2 to 6, dX3 to 16 and dY 3 to - 8 in the command parameter, then the RPLG command draws a polygon line as shown below. COMMAND CODE 15 0 11 0 1 010 1 0 olAREAI COL I OPMI ($A 4 XX) COMMAND PARAMETERS 15 0 1000010000100001000 '1 15 1 1 111 , 1 111 1 1 I' '1 1 , ($ 0 003) 0 001 ($ F F F C) 0 '5 10000100001000010 1 001 15 ($ 0004) 0 10 0 0 010 0 0 010 0 0 011 0001 15 ($ 0008) 0 10000100001000010 1 1 01 ($ 0006) 0 '5 100001000010001100001 ($ 0 0 1 0) 15 0 , 1 1 1 1 1 1 11 11 11' 0 0 01 '1' ($ F F F 8) y P2 (-4,4) ~8~~ ~16~ \ :V / " ~ ORG~v X PI (-12,-2) \ ~~e(-8'-6)_ \ '- 4--tCPC-8,-6) - (0,0) P 3 (12,-4) Figure C2S-2 Example of RPLG Execution HITACHI 247 ICRCL [26] CRCL (Circle Command) PAGE CRCL-1 CRCl Command draws a circle of the radius R placing the CP at the center. TYPE Graphic Command CRCl (C, AREA, COL, OPM) r WORD NUMBER Wn=2 hexadecimal notation COMMAND CODE 15 987 54 32 0 11 0 1 01 1 00 !cIAREA ICOl I OPMI C = 1 : ($ A 9 X X) C=0:($A8XX) EXECUTION CYCLES Cn=8d+66 COMMAND PARAMETERS 0 15 'I---------r-(-16--b-its-)--------~1 < DESCRIPTION> The Circle Command (CRCL) draws a circle placing the Current Pointer (CP) at the center. The command parameter r specifies radius in ~nits of pixels. First the CP moves in the X-direction from the center for the length of the radius r. Now this point is named Ps. The circle drawing starts at Ps and finishes at P 1 (= PsI. But, a dot is not drawn at P1. After the circle has been drawn, the CP moves back to the center and the command is finished. The position of the CP and Pe are the same. Bit 8 (C) of the command code specifies whether a circle is drawn clockwise or counterclockwise. When C= 1, it is drawn clockwise, when C = 0, counterclockwise as shown next page. The parameter radius r is allocated 16 bits, but only the low order 13 bits are effective. a 248 HITACHI CRCL CRCL (Circle Command) PAGE CRCL-2 y y Ps (A+r ,B) PiCA+r,B) ~--~ PI (A+r ,B) W"------''t P s (A+ r ,B) 000(0,0) ORG(O,O) x A x A (B) (A) Figure C26-1 Function of CRCL If the CP is (0, 0) on the split screen, and r is set 7 in the command parameter, then the CRCl Command draws a circle as shown in figure below. COMMAND CODE 15 li 0 0 1 01 1 0 0 ;oIAREA ICOl IOPMI ($A 8 XX) COMMAND PARAMETERS o ($ 0007) Ps(7,O) x ---r-~~~~~~~------- PI (7, 0) Figure C26-2 Example of CRCL Execution HITACHI 249 IELPS [27] ELPS (Ellipse Command) PAGE ELPS-1 ElPS Command draws an ellipse placing the CP at the center. TYPE ElPS (C, AREA, COL, OPM) a, b, OX COMMAND CODE 15 hexadecimal notation 987 54 32 0 11 0 1 011 1 0 :CIAREA ICOl IOPMI C= 1 :($ADXX) C = 0 : ($ A C X X) Graphic Command WORD NUMBER Wn=4 EXECUTION CYCLES Cn= 10d+90 COMMAND PARAMETERS 15 I 0 a (16 bits) 15 I 0 b (16 bits) 15 I I I 0 dX (16 bits) I < DESCRIPTION> The Ellipse Command (ELPS) draws an ellipse placing the current pointer (CP) at the center. On the X-V coordinates, if the center of an ellipse is CP (A, B), the major axis is dX, and the minor axis is dY. An ellipse is drawn according to Equation (1) as shown next page. (X-A)2 (Y-B)2 _ ( ) dX2+~-1 ............... 1 In Equation (1), letting the ratio of squared dX and dY be a, b; a : b = dX2 : dY2 . . . . . . . . . . . . . . . . . . . . .. (2) Then substituting (2) for Equation (1); (X~A)2 + (Y~B)2 = d: 2............. (3) 250 HITACHI ELPS ELPS (Ellipse Command) PAGE ELPS-2 The ELPS Command draws an ellipse according to Equation (3). The a, b, dX are specified in units of pixels. y ORO( 0,0) x Figure C27-1 Function of ELPS As shown in figure below, the CP moves in the X-direction from the center for the length of dX. This point is named Ps. The ellipse drawing starts at Ps and finishes at P 1 (= Ps). But. the dot is not drawn at P 1. After the ellipse has been drawn, the CP moves back to the center, and the command is finished. The first position of the CP and Pe are the same. y y Ps (A+dX, B) ~-----'1 1'1 ( A+dX, B) t"------'l PI (A+dX, B) I's(A+dX,B) ORG ORG (0,0) (0,0) x A (A) x A (B) Figure C27-2 Drawing Direction of ELPS HITACHI 251 IELPS ELPS (Ellipse Command) PAGE ELPS-3 Bit 8 (c) of the command code specifies whether an ellipse is drawn clockwise or counterclockwise. When C 1, it is drawn clockwise, when C 0, counterclockwise as shown in previous page. If the bit length of a, b, dX are La, 1.b, 1.dX, then the bit length of these parameters must be as follows; = = La + 1.dX ~ 13 1.b + 1.dX ~ 13 < EXECUTION EXAMPLE> If the absolute coordinate of CP is (16, 10) on the split screen, a is set to 9, b to 4, dX to 9 in the command parameter, then the ELPS Command (C 0) draws an ellipse as shown below. = COMMAND CODE 15 0 11 0 1 0 11 1 0;0 IAREA 1COL 1OPM I ($ A C X X) COMMAND PARAMETERS 15 0 I00 0 0 10 0 0 0 10 0 0 0 11 0 0 1 I a ($ 0 0 0 9) 0 15 10000/000010000/01001 b ($0004) 15 0 10 0 0 010 0 0 010 0 0 0 11 ~ dX ($ 0 0 09) =9 9 :4 2 : 62 y (16.10)' (16.10)\ -~PS(25'10) jPl(25.10) 10,/ ORG '/ (0,0) / ~16~ Figure C27-3 Example of ELPS Execution 252 HITACHI X IAARC [28] AARC (Absolute Arc) PAGE AARC-1 AARC draws an arc by current pointer (start point), end point, and center point of the absolute coordinate. TYPE Graphic Command AARC (C, AREA, COL, OPM) Xc, Yc, Xe, Ye WORD NUMBER Wn=5 COMMAND CODE hexadecimal notation EXECUTION CYCLES Cn=8d+ 18 COMMAND PARAMETERS 0 15 I Xc (16 bits) a 15 I Yc (16 bits) , I Xe (16 bits) a 15 I I a 15 I I Ye (16 bits) I < DESCRIPTION> As shown in Fig. C28-1, the AARC command draws an arc from the current pointer, CP, to Pe of the absolute coordinate, the absolute coordinates CC (Xc, Yc) being the center point. The X and Y components of the absolute coordinates CC and Pe are set in the first and second paraneters in units of pixels. After the arc drawing, current pointer moves to Pe. However a dot is not drawn at Pe. The command code bit 8 (C) selects whether an arc is drawn clockwise or counterclockwise. When C is "1", the arc is drawn clockwise, and when C is "0", the arc is drawn counterclockwise as shown in Fig. C28-1. HITACHI 253 AARC AARC (Absolute Arc) PAGE AARC-2 The command parameters are allocated 16 bits, but only the low order 1 3 bits are effective. Y Y /,/' ---- ............, 'Pe(Xe,Ye) I I I I I I x ORG(O,O) x ORG(O,O) (A) (B) Figure C28-1 Function of AARC Command If the coordinate of CP is at (12,4) on the split screen, Xc is set to 12, Vc to 10, Xe to 6, and Ve to 10 in the command parameter, then the AARC Command (C = 0) draws an arc as shown in figure next page. COMMAND CODE 15 0 11 0 1 1 10 0 0:0 IAREA ICOl I OPM I ($ B 0 XX) COMMAND PARAMETERS 15 0 '10-0-0-0~10--0-0-0~10-0-0-0~1-1--0~01 15 0 10000100001000011 010 1 15 10 0 0 0 10 0 0 0 10 0 0 0 10 1 15 ($OOOA) 0 01 0 10 0 0 0 10 0 0 0 10 0 0 0 11 0 1 0 254 HITACHI ($ 000 C) I ($ 0006) ($ 00 OA) IAARC AARC (Absolute Arc) PAGE AARC-3 I C=o I -- y Pe(6,10) CC(12,10) 1\ I 10 000(0,0) 10 V \ CP(l2,4) x ~12~ Figure C28-2 Example of AARC Execution HITACHI 255 IRARC [29] RARC (Relative Arc) PAGE RARC-1 RARC draws an arc by current pOinter (start point). end point, and center point of the relative coordinate. TYPE Graphic Command RARC (C, AREA, COL, OPM) dXc, dYc, dXe, dYe WORD NUMBER Wn=5 COMMAND CODE 15 hexadecimal notation 987 11 0 1 1 10 1 0 54 32 0 ic IAREA 1COL 1OPM 1 ~ ~ ~ ~ :~ : ! ~ ~: EXECUTION CYCLES Cn=8d+ 18 COMMAND PARAMETERS 0 15 I dXc (16 bits) 15 I 0 dYc (16 bits) 15 I I 0 dXe (16 bits) 15 I I I 0 dYe (16 bits) I < DESCRIPTION> As shown in Fig. C29-', the RARC command draws an arc from the current pointer, CP, to Pe (A + dXe, B+ dYe) of the relative coordinates, the relative coordinates CC (A+ dXc, B+ dYc) being the center points. The X and Y components of the relative coordinates CC and Pe are set in the first and second parameters in units of pixels. CP moves to the end point Pe when an arc is drawn. However a dot is not drawn at Pe. The command code bit 8(C) selects whether an arc is drawn clockwise or counterclockwise. When C is ",", the arc is drawn clockwise, and when C is "0", the arc is drawn counterclockwise as shown in Fig. C29-2. 256 HITACHI RARC RARe (Relative Arc) PAGE RARC-2 The command parameters are allocated 16 bits, but only the low order 13 bits are effective. Pe(A+dXe ,B+dYe) Y Y ..... ORG ',..---- ............ " Pe(A+dXe, B+dYe) _---- x (0,0) ORG x ( 0,0) A (A) (B) Figure C29-1 Function of RARC If the coordinate of CP is at (6, 10) on the split screen, dXc is set to 6, dYc to 0, dXe to 6, and dYe to 6 in the command parameter, then the RARC command (C = 0) draws an arc as shown next page. COMMAND CODE a 15 11 a 1 1 10 1 0:0 IAREA ICOl IODMI ($ B 4 XX) COMMAND PARAMETERS a 15 10 a a a 10 a a a 10 a a 010 1 a a 010 a a 010 a a a 10 a a 01 15 a a 06) ($ a a 00) ($ a a 06) ($ a a 06) a 15 10 ($ a 15 10 01 a a o@ij a 10 a a 010 1 Ia a a aIa a a a 10 a a a 10 1 01 a 01 HITACHI 257 IRARC RARC (Relative Arc) PAGE RARC-3 y Pe(I2,16) CP(','" ~ \~C<:~'lO) ) ~ ORG( 0,0) x Figure C29-2 Example of RARC Execution 258 HITACHI IAEARC [30] AEARC (Absolute Ellipse ARC) PAGE AEARC-1 TYPE Graphic Command AEARC draws an ellipse ARC. AEARC (C, AREA, COL, OPM) a, b, Xc, Yc, Xe, Ye COMMAND CODE 15 987 54 32 hexadecimal notation WORD NUMBER Wn=7 C = 1 : ($ B 9 X X) C = 0 : ($ B 8 X X) EXECUTION CYCLES Cn=10d+96 0 1101 11 10 OjCIAREAICOL IOPMI COMMAND PARAMETERS 15 I 0 a (16 bits) 15 1 0 b (16 bits) 15 1 Yc (16 bits) 1 0 Xe (16 bits) 15 1 1 0 15 I I 0 Xc (16 bits) 15 I 1 1 0 Ye (16 bits) 1 < DESCRIPTION> The AEARC command draws an arc from the current pointer, CP, to Pe of the absolute coordinate, the absolute coordinates CC (Xc, Yc) being the center point. the X and Y components of the absolute coordinates CC and Pe are set in the command parameters in units of pixels. CP moves to the end point Pe when an arc is drawn. However a dot is not drawn at Pe. HITACHI 259 AEARC PAGE AEARC-2 AEARC (Absolute Ellipse ARC) The command code bit a(C) selects whether an arc is drawn clockwise or counterclockwise. When C is "1", the arc is drawn clockwise, and when C is "0", the arc is drawn counterclockwise as shown in Fig. C30-1. y y Pe(Xe,Ye) x (Aj x (B) Figure C30-1 Function of AEARC < RELATED EQUATIONS> In the X-V coordinate, let the center point of the ellipse be CC(Xc, YC), let the length of the X-axis be dX, and let the length of the Y-axis be dY. Depending on (1), an ellipse ARC is drawn as shown in Fig. C30-2. (X-XC)2 dX2 + (Y-YC)2 dY2 = 1 ............. (1) When letting dX2 and dY2 be a and b, then a : b = dX2: dY2 .................. (2) by substituting (2) for (11. the result is (X- XC)2 a + (Y- YC)2 = d~2 .......... (3) b The AEARC draws an ellipse ARC according to Equation (3). 260 HITACHI AEARC PAGE AEARC-3 AEARC (Absolute Ellipse ARC) y x ORG(o, 0) Figure C30-2 Notation of an,Ellipse (1) y ,, \ I Pe(Xe,Ye) ORG(O, 0) ... - -------- ,,'" ........ I " x Figure C30-3 Notation of an Ellipse (2) When setting CP (A, B) and CPe (Xe, Ve) as shown in Fig. C30-3 for an ellipse arc drawing, the following equations are applicable. HITACHI 261 IAEARC AEARC (Absolute Ellipse ARC) PAGE AEARC-4 +x () A = .J dX2 sin2 (I + dV2 cos2 (I B= dXdV sin (I + Vc .J dX2 sin2 (I + dV2 cos2 (I ......... . Xe = dXdV cos a + Xc .J dX2 sin2 a + dV2 cos2 a ......... . dXdV cos (I c. . . . . . . . .. 4 (5) (6) dXdV sin a Ve = .J dX2 sin2 a + dV2 cos2 a + Vc .......... (7) a, b, Xc, Vc, Xe and Ve are given as a parameter to the AEARC command in units of pixels. When setting the command parameters, CC (Xc, Vc) of an ellipse, and CP (A. B) and Pe (Xe, Ve) and ellipse ARC must meet the above (4), (5), (6) and (7) equations. 262 HITACHI IREARC [31] REARC (Relative Ellipse ARC) PAGE REARC-1 REARC draws an ellipse ARC. TYPE REARC (C, AREA, COL, OPM) a, b, dXc, dYc, dXe, dYe WORD NUMBER Wn=7 . COMMAND CODE 15 Graphic Command hexadecimal notation 987 54 32 0 C = 1 : ($ B D X X) 1 101 111 1 o jCIAREA 1COL IOPMI C 0 : ($ B C X X) = EXECUTION CYCLES Cn=10d+96 COMMAND PARAMETERS 15 I 0 a (16 bits) 15 1 0 b (16 bits) 15 I 1 0 dXe (16 bits) 15 I I 0 dYc (16 bits) 15 1 1 0 dXc (16 bits) 15 1 I 1 0 dYe (16 bits) I < DESCRIPTION> As shown in Fig. C31-1, the REARC command draws an arc from the current pointer, CP, to Pe (dXe, dYe) of the relative coordinate, the relative coordinates CC (dXc, dYe) being the center point. The X and Y components of the relative coordinates CC and Pe are set in the command parameters in units of pixels. HITACHI 263 REARC PAGE REARC-2 REARC (Relative Ellipse ARC) The command code bit 8 (C) selects whether an arc is drawn clockwise or counterclockwise. When C is ",", the arc is drawn clockwise, and when C is "0", the arc is drawn counterclockwise as shown in Fig. C31 -, . Pe(A+dXe,B+dYe) Pe(A+dXe,B+dYe) Y ,...,..'" ,l -',-------- .... CC(A+dXc,B+dYc \ CP(A, B) " x OaG(O,O) w ~:"""':-:-::"..f'-,.,.,-::::,.lf x ORG(O,O) A (B) Figure C31-1 Function of REARC 264 HITACHI IAFRCT [32] AFRCT (Absolute Filled Rectangle) PAGE AFRCT-1 AFRCT command paints the rectangular area specified with CP (Current Pointer) and the command parameter (the absolute coordinates) according to a figure pattern stored in the Pattem RAM. TYPE Graphic Command AFRC (AREA, COL, OPM) X, Y WORD NUMBER Wn=3 hexadecimal notation COMMAND CODE 15 87 54 32 0 11 1 001 000 olAREAICOL IOPMI ($ CO XX) EXECUTION CYCLES Cn= (P'A+ 8)B+ 18 COMMAND PARAMETERS 15 I 0 I X (16 bits) 15 I 0 I Y (16 bits) < DESCRIPTION> The Absolute Filled Rectangle Command (AFRCT) paints the rectangle area according to the color information in the pattern RAM. The sizes of the rectangle are parallel to the coordinate axis. Two corner pOints on the diagonal are CP and Pc (X, Y) at the absolute coordinate point from the origin. Pc IX, Y) expressed in the absolute X - Y coordinates from the origin are given by the command parameter in units of pixels. y ORG(O,O) Figure C32-1 Function of AFRCT HITACHI 265 IAFRCT AFRCT (Absolute Filled Recangle) PAGE AFRCT-2 Painting in a rectangular area depends on the position of CP and Pc, as shown in Fig. C32-2. In Fig. C32-2, painting between CP and Pc is performed. CP is moved to Pe at the termination of the command. The drawing at the end point Pe is not performed. Pe Pc _--0 '~. CP CP , ,~~~~f l)c ---------0 Pe 0-.____ Pe Pc wit' CP CP ~~~3 0-- .----- . Pc Pe Figure C32-2 Painting Direction of AFRCT If the absolute coordinate of CP is (A, B) on the split screen, X is set to X 1 and Y to Y 1 in the command parameter, and the drawing parameter register for the pattern RAM is set to the following, the pattern start point (PSX, PSY), the pattem end point (PEX, PEY), the graphic pattern pointer (PPX, PPYI. then, the rectangular area is painted with the AFRCT command as shown next page. COMMAND CODE 15 0 11 1 0 010 0 0 olAREA ICOLI OPMI ($C 0 XX) COMMAND PARAMETERS 15 Ir-- - - X - 1-----110 15 ------1, ($X X XX) 0 ---Y-1 ;-1 266 HITACHI ($X X XX) IAFRCT AFRCT (Absolute Filled Rectangle) PAGE AFRCT-3 Y (CPCA,B) _LLLLLLLL Pattprn RAM PTN 15 (PEX, PEY) r----../ I CPPXJEI PPY): : I I =-~~~~~~~~ =-~~~~l~~~ =-~l~~~~~~ =-~~~~~~~~ ~ I ____ JI PTN o C PSX, PSY) bitO~ bit 15 x ORG(O,O) Figure C32-3 Example of AFRCT Execution HITACHI 267 IRFRCT [33] RFRCT (Relative Filled Rectangle) PAGE RFRCT-1 RFRCT command paints in the rectangular area specified with CP (Current Pointer) and the command parameter (the relative coordinates) according to a figure pattern stored in the Pattern RAM. TYPE Graphic Command RFRCT (AREA,COL,OPM)dX,dY WORD NUMBER Wn=3 hexadecimal notation COMMAND CODE 15 87 54 32 0 11 1 0 01 0 1 0 01 AREA 1COL 1OPM I ($ C 4 XX) EXECUTION CYCLES Cn= (P'A+ 8)B+ 18 COMMAND PARAMETERS 15 1 0 I dX (16 bits) 15 0 I dY (16 bits) 1 < DESCRIPTION> The Relative Filled Rectangle Command (RFRCT) paints the rectangular area according to the color information in the pattem RAM. The sizes of the rectangle are parallel to the coordinates axis. Two corner points on the diagonal are CP and Pe (A+dX, B+dY) at the relative coordinate point from CPo Pe (dX, dY) expressed in the relative coordinate from CP is given by the command parameter in units of pixels. Y Pe (A,B+dY+ 1) O-rIf)----Pc (A+dX, BtdY) dY ./ ORG(O,O) CP (A, dX --~-----------------------x Figure C33-1 Function of RFRCT 268 HITACHI IRFRCT RFRCT (Relative Filled Rectangle) PAGE RFRCT-2 Painting in a rectangular area depends on the position of CP and Pe, as shown in Fig. C33-2. In Fig. C33-2, painting between CP and Pe is performed. CP is moved to Pe at the termination of the command. The drawing at the end point Pe is not performed. Pe Pe BwL~ c~ CP CP CP ~ Pc FaPc 0-----Be ---0 Be Figure C33-2 Painting Direction of RFRCT If the absolute coordinate of CP is (A, B) on the split screen, dX is set to dX, and dY to dY, in the command parameter, and the drawing parameter register for the pattern RAM is set to the following, the pattern start point (PSX, PSY), the pattern end point (PEX, PEY), the graphic pattern pointer (PPX, PPY), then, the rectangular area is painted with the RFRCT command, as shown in Fig. C33-3. COMMAND CODE 15 0 11 1 001 0 1 0 OIAREA ICOL IOPMI ($C 4 XX) COMMAND PARAMETERS Ir-- ----,10 ($X X XX) Ir----- ------,1 ($X X XX) 15 ---dX-, 15 0 d- Y -, HITACHI 269 RFRCT PAGE RFRCT-3 RFRCT (Relative Filled Rectangle) Y 1::.1=J=J::J=J=_1::.1::. ~1::.1::.1::.l=.1::.1::.1::. 1::.l=. ~ ~ 1::.1::.1::.1::. Pa t tP.fn RAM PTN 15 CPEX. PEY) r---- ........... CPpx;E1 1 PPY) : I 1::.1::.1::.1::.1::.1::.1::.1::. I I I ____ oJI PTN ~ Pe CA. B-dYl-1) o (Psx. pSY) bitO~ dY \+ 1 bit 15 ----4------------------------------------ORGCO.O) Figure C33-3 Example of RFRC Execution 270 HITACHI X IPAINT [34] PAINT (Paint) PAGE PAINT-1 PAINT command paints the closed area surrounded by edge color using the figure pattern stored in the pattem RAM. TYPE Graphic Command PAINT (AREA, COL, OPM) WORD NUMBER Wn=l COMMAND CODE 15 hexadecimal notation 987 54 32 0 11 1 0011 0 oiEIAREAlcol IOPMI COMMAND PARAMETERS - NON- ($ C X XX) Command execution cycle number Cn=(18'A+ 102)B-58 (When painting rectangle) < DESCRIPTION> The "Paint" command (PAINT) paints the closed area surrounded by edge color defined in the parameter register (EDG: edge color), using the figure pattern stored in the pattern RAM. If the CP is inside the closed area, the paint operation is performed only inside the closed area. If the CP is outside, the paint operation is performed outside the closed area. Color code stored in color registers (ClO or Cll) are also considered to be an edge during PAINT execution. (See < Complex Figure Painting>.) When an unpaintable area is detected during this command, the coordinates are put in the Read FIFO and painting is continued. Therefore, a complex figure can be completely painted by re-issuing PAINT commands using the coordinate data put in the Read FIFO. < Definition of Edge Color> E = 0: The edge color is defined by the data in the EDG register. (See figure next page) E = 1 : The edge color is defined to be all colors except for the color in the EDG register. (See figure next page) HITACHI 271 PAINT PAINT (Paint) PAGE PAINT-2 E = 0: CP "red" is set to the EDG register. PAINT is executed at E=O. Background: Black Figure C34-1 Paint Function (E=O) Red E = 1: CP "black" is set to the EDG register. PAINT is executed at E=1. Background: Black Figure C34-2 Paint Function (E= 1) < Paint Using a Pattern > The PAINT command paints using a pattern stored in the pattern RAM. As the scan point in the pattern RAM moves corresponding to the movement of the drawing point, the figure is repeatedly drawn. Pattern RAM ( )-----K3 PTN 15 PE (PEX, PEYI !, I --~PP(PPX I " PPYI ' PTN 0 ,-P_S_(_PS_X_,_P_S_Y_I--, bit 0 ____________ bit 15 CP Figure C34-3 Paint Function Using Figure Pattern 272 HITACHI IPAINT PAGE PAINT-3 PAINT (Paint) < Paint Procedure> Figure C34-4 Paint Procedure Painting is continuously performed parallel to the X axis (left to right), and in the Y direction, dot by dot. Fig. C34-2 shows an example of painting the encircled area. First. painting begins from points S on a line which is parallel to the X axis from CPo Next, painting is executed on the adjacent line which is above or below the first line. This drawing is repeated and painting proceeds. In this way, the whole encircled area is painted. The current pointer, CP, moves to the end point Pe at the finish. < Complex Figure Painting> The PAINT command checks the outlined area for any un-painted areas during painting. If there are any during painting, the coordinates of the areas are pushed into the internal stack. Figure below shows a case of four coordinates being pushed into the stack. Figure C34-5 Paint Stack Function HITACHI 273 1PAINT PAINT (Paint) PAGE PAINT-4 The ACRTC can store four such coordinates. If the pOints are within four, one PAINT command can completely paint a complex figure. If the points are five or more all coordinates cannot be pushed into the stack. The un-stacked coordinates are put in the Read FIFO to be read out by the MPU. the MPU reads out the coordinates and issues another PAINT command to paint the un-painted areas using these coordinates after the initial PAINT command is finished. The coordinate for one point put in the Read FIFO consists of the following 3 words. 15 0 I CPx oI ·Coo PAINT Area Detection modes have each of the following functions. AREA 000 001 PAINT Command Execution Not check the specified area. AREA flag is set and the command execution is truncated, if CP moves outside the specified area during painting. 010 Paint only inside the specified area. AREA flag is not set. 011 Paint only inside the specified arera. If CP meets the edge of the specified area, AREA flag is set. 100 101 Not check the specified area. AREA flag is set and the command execution is truncated, if CP moves inside the specified area. 110 Paint only outside the specified area. AREA flag is not set. 111 Paint only outside the specified area. If CP meets the edge of the specified area, AREA flag is set. , 276 HITACHI PAINT PAINT (Paint) (i) PAGE PAINT-7 aaa aa AREA = AREA = 1 Sppcifipd Arpa (XMAX,YMAX) r----------1 I CP I I I I I I ------ (XMIN, YMIN) (ii) aa AREA = 1 (AREA flag is set.) (XMAX,YMAX) ,----------4 I I I CP I I I I I I .... ----(XMIN, YMIM) (iii) a1a AREA = (AREA flag AREA = (AREA flag a is not changed.) 1 1 is set.) (XMAX, YMAX) r----------., I I I CP I I I I ....I - - - - (XMIN, YM IN) a (iv) AREA = 1 1 (AREA flag is set.) (XMAX, YMAX) ,-----------, I I I I I CP I I I .... ----(XMIN,YMIN) (v) a AREA = 1 1 (AREA flag is not changed.) AREA = 1 1 1 (AREA flag is set.) (XMAX, YMAX) r-----------., I I : CP I I I I .... -----(XMI"I,YMIN) Figure C34-6A Paint Command Example with AREA Modes HITACHI 277 IPAINT PAINT (Paint) PAGE PAINT-8 < EXAMPLE> (In the case of E = "0") If a circle of the same color as specified in the edge color register (EDG) is drawn on the split screen, the pattern shown in Fig. C34-7 fetched from the pattern RAM is used and the pattern pointer (PP) is in the position shown in Fig. C34-7. Then the PAINT command with bit8 "0", CP in the position shown in Fig. C34-8 is executed as shown in Fig. C34-8. = COMMAND CODE 15 0 /1100/100;0IAREAICOL/OPM/ ($C 8 XX) Pattern RAM r-;r--T-,-.,--.-,,--1- PE (PEX, PE Y) H---t--..b4=t=:t-,- PP (PPX, PPY) / / PS(PSX,PSY) Figure C34-7 Setting of Pattern RAM 278 HITACHI ~ :E (I) • o ~ z ~ < < CJ Z - A. A. w 8r.:l c( \ ~ 0000000 0 o A. 0 0 (In the case of E = ",") If a circle of the same color as specified in the edge color parameter register (ED G) is drawn on the split screen and the inside of the circle is also painted in the same color and the surround of the circle is not the same color as the edge, Fig. C34-' 0 (A), and the pattern shown in Fig. C34-9 is in the pattern RAM, the pattern painter (PP) is in the position shown in Fig. C34-9. Then the PAINT command with bit 8 = ",", CP in the position shown in Fig. C34-' 0 (A) is executed as shown in Fig. C34-'O (8). Pattern RAM ~.....,.--r--r-.....-"""""~- PE (PEX, PEY) HH---b¢=t==I----1- PP (PPX, PPY) / / PS (PSX, PSY) Figure C34-9 Setting of Pattern RAM 280 HITACHI rPAINT PAINT (Paint) PAGE PAINT·11 exceptional edge color , ••••••~• •• 000000 EDG • 0000000000 •• .000000 000 0 0 00. CP • 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • 000000000000000 • • 0 000000000000000 • • 00 00000000000000 • • 0000 000000000000. 00000000000 • • 00000 .00000000000000000 • • 00000000000000000 • • 00000000000000000 • • 000000000000000 • • 000000000000000 • • 0000000000000 • • 00000000000 • •• 0000000 •• • • • •• 6 ••••••• 6 6 6 6 .6 6 6 666 • • ••• • • •• (A) 6 • 6 6 6 6 6 6 6 • 6 • • • 6 6 • 66 6 . 6 666 6 6 666 6 6 6 6 •• • • 6 @ 6 .66 • • 6 6 666 666 6 6 6 6 6 6 •• • D.D.D.D. D. 6 D. 6 6. • 6 •• • • • •• • • •• • •••••• (8) Figure C34-10 Example of PAINT Execution (E = "1") HITACHI 281 lOOT [35] DOT (Dot Command) PAGE DOT-1 DOT Command marks a dot on the coordinates where the CP points. TYPE Graphic Command DOT (AREA, COL, OPM) WORD NUMBER Wn=1 COMMAND CODE 15 hexadecimal notation 87 54 32 0 ($C C XX) 11 1 0 011 1 0 OIAREAI COL IOPM I EXECUTION CYCLES Cn=8 COMMAND PARAMETERS - NON- < DESCRIPTION> The Dot Command (DOT) marks a dot on the coordinate where the Current Pointer (CP) indicates. After dot drawing, the CP doesn't move. So, Pe, the dotting-finishing point, is the same point as the CPo y CP (A,B) • ORG (0,0) Pe (A,B) x Figure C35-' Function of DOT 282 HITACHI lOOT PAGE DOT-2 DOT (Dot Command) In the case of the absolute coordinate of the CP is (10, 8) on the split screen, the DOT Command marks a dot as shown in Fig. C35-2. COMMAND CODE 0 15 11 1 0 011 1 0 0IAREA ICOL I OPM 1 ($C C XX) COMMAND PARAMETERS - NONy Pe(lO,8) • CP(lO,8) __~O_R_G_(~O~,O~)_________ X figure C35-2 Example of DOT Execution The LINE Commands and ARC Commands do not draw a dot at the finishing points, Pe. The DOT Command can be used to draw a dot at the Pe to draw a complete line or arc. COMMAND CODE 15 87 54 32 I 0 11 1 001 1 1 0 OIAREA 1COL OPM I EXAMPLE End point / CP Start point ALINE X, Y Pe (X, Y) End point Pe (X, Yl / CP Start point ALINE X, Y DOT Figure C35-3 DOT Command for the End Point HITACHI 283 IPTN [36] PTN (Pattern) PAGE PTN-1 TYPE Graphic Command The graphic pattern defined in the pattern RAM is drawn onto the rectangular area specified by the current pOinter and by the pattern size. PTN (SL, SO, AREA, COL, OPM) S WORD NUMBER Wn=2 COMMAND CODE 15 hexadecimal notation 12111087 54 32 I I 0 11 1 0 1 1SL 1SO 1 AREA COL OPM I ($0 X XX) EXECUTION CYCLES Cn= (P·A+ 1O)·B+ 20 COMMAND PARAMETERS 15.-________~8~7__________,0 SZ ~I ___ S_Z_y__ ~I~ __ S_z_x__ ~1 SZx, SZy Setting: 0-255 Meaning: 1 -256 in units of pixels < DESCRIPTION> As shown in Fig. C36-1, the Pattern command (PTNI is used to draw the graphic pattern defined in the pattern RAM onto the rectangular area specified by the current pointer (CP) and by the parameter (SZ: SZy, SZx). The pattern to be taken out of the pattern RAM is set by the pattern start point (PS) and pattern end point (PE). The point at which to start pattern RAM scan to obtain color information is set by the pattern pointer (PP). The color information is set on color registers "0" and "1" for execution of pattern drawing. Parameter SZ is divided into X component (SZx) and Y component (SZy), each component being set in units of pixels. The PTN command has the CP scan direction set up in units of 45° in the operation code, together with the choice of 45° slanted pattern drawing. After pattern drawing, the CP is moved to the Pe (see Table C36-1). 284 HITACHI IPTN PTN (Pattern) PAGE PTN-2 Frame Buffer Pattern RAM y where, SL = 0 SD = 7 ~ CP SZX~,~SZY+' ORG (0,0) ~~-----------------------------x Figure C36-1 Function of PTN Table C36-1 Directions of CP Scan I"'"S~'-"S>f--_O _00_-+-__ II 0 1 1111 0 1 0 ~ o~ ~_~ ~~~_~I~OO~-+_~I_()I~-+_ _ I_I(_)___t -__ I __ II ____ ~ ~o '\:-\ • : CP 0: Pe HITACHI 285 IPTN PTN (Pattern) PAGE PTN-3 < Example of Command Execution> From the pattern RAM. take out a pattern using the PS (PSX. PSY) and PE (PEX. PEY). and execute the PTN command. (1) Where PP=PS. PZ=O. SZ=PE-PS. SL=O. SD=O COMMAND CODE 15 0 11 1 0 11 O! 0 0 01 AREA 1COL 1OPM 1 ($00 XX) COMMAND PARAMETERS 15 8 7 0 10000011 11000001011 ($ 0 7 05) Pattern RAM PTN15r-----------------~ PE (PEX, PEY) • • • • • • • • o 0 0 0· o • • •0 o· · ·0 o0 • 0 0 • • 0-0-· • 0- · 0 · · PE-PS, SL=O, SD=O COMMAND CODE 15 0 11 1 0 11 0 ;0 0 OIAREA 1COL 1OPM 1 ($ DO X X) 1 0 1 11 ($ 0 FOB) COMMAND PARAMETERS 15 10 8 7 0 0 0 1 1 1 11 0 0 0 0 0 Pattern RAM PTN15.----------------- . . . .. 00 0 0· • PE (PEX, PEYj ". ® •• e(!)e 0 · · .@. 00 0 0· • (!) • (!). • • (!). • (!). • (!). cpe •• PTN 0 PS (PSX, PSYj bit 0 Frame Buffer = PP bit 15 ye . .. .. .. .. .. .. .. .. .. .. .. -' o0 @ 0 • • 0 0 PE-PS, SL=O, SD=O COMMAND CODE 15 0 11101JoJoooIAREAICOLIOPMI ($00 XX) COMMAND PARAMETERS 15 8 7 ($0 FOB) 10 0 0 0 1 1 1 110 0 0 0 1 Pattern RAM PTN15r------------------, PE (PEX, PEY) • • • • • • ® (!)
-. PTN 0 bit 0 PS (PSX, PSY) = PP -- bit 15 Frame Buffer Pe . ./ .. .• .• .. . e000· • o • @. • • (!) • • @ • • Cf • • • 0 • CP Figure 36-7 Example of PTN Execution (6) HITACHI 291 IPTN PTN (Pattern) (7) PAGE PTN-9 Where PP=PS, PZ=O, SZ=PE-PS, SL=O, SD= 1 COMMAND CODE 15 0 ($ D 1 XX) 11 1 0 11 0 10 0 11 AREA 1COL 1OPM 1 COMMAND PARAMETERS 15 0 8 7 ($ 0 7 05) 10 0 0 0 0 1 1 11000001011 Pattern RAM PTN 15 PE (PEX, PEY) .~ • • @@@@. • @. • @• @. • • @ • @@@@. @.@. • • @. • @ • • • @• ~ · · · .· PTN 0 bit 0 PS (PSX, PSY) = PP bit 15 Frame Buffer Pe ·· .• •• ·· ·• ·• •• ·• ·• ·· ·· ·• •• ·• · . ·• • • 01 • ·0· · · • · · · ···· • · • ® • · · ··. · · ·· ·0· · · · · ·· • 0· 0• ·· ·· ··0· ·· ··· ·· ··· ·· ··@·@·@·@·0· · 0 . ·· ····· (!) • • '--..., • (!) • ·· ·· ·· ·· ·· ··0· 0. ·. · · · · · · . · · · · • • G( ·••· ·· .· ·· CP Figure 36:8 Example of PTN Execution (7) 292 HITACHI IAGCPY PAGE AGCPY-1 [37] AGCPY (Absolute Graphic Copy) AGCPY command copies a rectangular area specified by the absolute coordinates to the address specified by CP (Current Pointer) Graphic Command TYPE AGCPY (S, DSD, AREA, COL, OPM) Xs, Ys, DX, DY WORD NUMBER Wn=5 COMMAND CODE 15 121110 11 1 1 hexadecimal notation 87 54 32 0 oisl D S DIAREA 100 1OPM 1 ($EXXX) EXECUTION CYCLES Cn= {(P+ 2)A+ 1O)B+ 70 COMMAND PARAMETERS 15 I 0 15 I 0 Ys 15 1 I 0 I DX 15 I I Xs 0 DY I < DESCRIPTION> The Absolute Graphic Copy Command (AGCPY) copies data from an rectangular area in the frame buffer (the source area) to another location in the frame buffer (the destination area) with the initial starting pOint CPo The size of the source rectangular area is parallel to the coordinate axis. Two diagonal comer points are Pss (Xs, Ys) at the absolute coordinate pOint from the origin and Pse (Xs+ DX, Ys+ DY) at the relative coordinate point from Pss. Pss (Xs, Ys) expressed by absolute X- Y coordinates from the origin are set in the command parameter in units of pixels. Pse (DX, DY) expressed by relative X - Y coordinates from Pss are set in the command parameter in units of pixels. HITACHI 293 IAGCPY AGCPY (Absolute Graphic Command) PAGE AGCPY-2 Pe (A,B + OX + 1) y o Destination area Source area Pse (Xs+DX, Ys+DY) • ¢::l : • CP (A, B) • • ~DX / Pss (Xs, Ys) _____ Ys • J \ ~I~Y Direction of scan S=1 DSD = 000 ORG (0,0) --~~~~A--~~---------------?~------------------------X ~xs~ Figure C37·1 Function of AGCPY < DIRECTION OF POINTER SCAN> The direction of pointer scan is determined by S bit and DSD bit in the command code through the AGCPY command. (a) S (Source Scan Direction) COMMAND CODE 15 11 0 '---1-r-tls 1------,1 294 HITACHI IAGCPY PAGE AGCPY-3 AGCPY (Absolute Graphic Command) Table C37-1 Direction of Source Data Scan B[E] s= 0 s- 1 • : Pss o : Pse The direction of scan on the frame buffer in the source area is determined with bit 11 in the command code and the position of Pss and Pse. as shown in Table C3 7-1. (b) DSD (Destination Scan Direction) COMMAND CODE 15 1098 0 1.....---..--1s-o-r-I--------"I 0 HITACHI 295 IAGCPY PAGE AGCPY-4 AGCPY (Absolute Graphic Copy) Table C37-2 Direction of Destination Data Scan OSO~ooo OSO~OOI OSO~100 OSO~101 OSO~OI0 OSO=OII OSO=111 Go [EJ 08 131 .:CP o:Pe As shown Table C37-2, the direction of scan on the frame buffer in the destination area is determined with bits 10 through 8 in the command code and position of CP and Pe. After termination of the command, Pe, the end point of CP, is moved to the point shown in Table C37-2. If the absolute coordinates of CP is (4, 2) on the split screen, Xs is set to 18, Ys is set to 2, OX is set to 13 and OY is set to 7 in the command parameter. Then, the drawing is copied by the 1, OSO 000), as shown in Fig. C37-2 (8). AGCPY command (S = 296 HITACHI = AGCPY AGCPY (Absolute Graphic Copy) PAGE AGCPY-5 COMMAND CODE 15 0 ($ EO XX) 11 1 1 oloio 0 oIAREA/ 0 0 / OPM / COMMAND PARAMETERS 15 0 ($ 00 1 2) 10000100001000 1100 1 0/ 0 15 /000 % 0 0 % 0 0 % ($ 0002) 0 1 0/ 0 15 ($000 D) /0000/0000/0000/1101/ 15 0 ($ 0007) /000010000/000010111/ Y (34,12) ~ (28,6) X ORG (0,0) (A) Before Execution of AGCPY Y r---0 oPe(4,16) (8,12) (11,15) : r-------- - I I I I I I I I I .. ______ ...1I C (4,2) ORG (0,0) I I 7 I I 13 _ Pss (18, 2) 2 I I J ---------~ X 18 (B) After Execution of AGCPY Figure C37-2 Example of AGCPY Execution HITACHI 297 IRGCPY PAGE RGCPY-1 [38] RGCPY (Relative Graphic Copy) RGCPY command copy a rectangular area specified by the reative coordinates based on CP (Current Pointer) to an address specified by CPo TYPE Graphic Command RGCPY (S, DSD, AREA, COL, OPM) dXs, dYs, DX, DY WORD NUMBER Wn=5 hexadecimal notation COMMAND CODE 15 121110 87 54 32 0 11111lSlDSDlAREAl00lOPMI ($FXXX) EXECUTION CYCLES Cn= {(P+2)A+ 10jB+70 COMMAND PARAMETERS 0 15 I dXs 15 I 0 dYs 15 I I 0 DX 15 I I I 0 DY I < DESCRIPTION> The Relative Graphic Copy Command (RGCPY) copies data from an rectangular area in the frame buffer (the source area) to another location in the frame buffer (the destination area) with the initial starting point CPo The size of the source rectangular area is parallel to the coordinate axis. Two diagonal corner points are Pss (A+dXs, B+dYs) at the absolute coordinate point from CP and Pse (A+dXs+DX, B+dYs+DY) at the relative coordinate point from Pss. Pss (dXs, dYs) expressed by the relative X- Y coordinates from CP are set in the command parameter in units of pixels. Pse (DX, DY) expressed by the relative X - Y coordinates from Pss are set in the command parameter in units of pixels. 298 HITACHI IRGCPY RGCPY (Relative Graphic Copy) y PAGE RGCPY-2 Pe (A, B + DX+1) 0.,--_-, •• "-r-'. ..!-!/'---,. •• • CP (A, B) • di Pse (A+dXs+DX, B+dYs+DY) Pss (A+dXs, B+dYs) \ '\--dXs~ V ORG (0,0) ~Y DX _ _ _ ~ Direction of Scan S =1 DSD =000 x '-......A.,../ Figure C38-1 Function of RGCPY < DIRECTION OF POINTER SCAN> S-bit and 050 bit in the RGCPY command have the same function as those in the AGCPY command. Refer to the description about the AGCPY command for details. < EXECUTION EXAMPLE> If the absolute coordinate of CP is (4, 2) on the split screen, dXs is set to 18, dYs to 2, OX to 12 and OY to 6 in the command parameter. Then, the drawing is executed by the RGCPY command (5 1, 050 0001. as shown in Fig. C38-2 (B). = = HITACHI 299 RGCPY RGCPY (Relative Graphic Copy) PAGE RGCPY-3 COMMAND CODE 15 0 I 11 1 1 11 0 100 olAREAI 001 OPM ($FOXX) COMMAND PARAMETERS 15 0 100001000010001100101 15 ($ 00 1 2) 0 100001000010000100 1 01 15 ($ 0002) 0 10000100001000011 100 1 15 ($OOOC) 0 10000100001000010 1 1 01 ($ 0006) Y (40,13) • (28,6) ORG (0,0) (A) Before execution of RGCPY x Y Pe (4,15) o fT~("''') I (6,8) I r---I I 4)F-----I : I I ~ 18 Pss (22, ~2 12 CP (4, 2) ORG(O,O) x (B) After execution of RGCPY Figure C38-2 Example of RGCPY Execution ~OOHITACHI USE OF ARC AND ELLIPSE ARC COMMAND o Use of Arcs and Ellipse Arcs Commands How to Calculate Parameters of Arc Commands AARC Xc, Yc, Xe, Ye; RARC dXc, dYc, dXe, dYe; (Command Issuing Procedure) CP is moved to the start point (CPx, CPy) by MOVE, then (Xe, Ve) ARC is issued. I [Example 1] Given center coordinates (Xc, Yc), radius r, drawing start angle () 1 and drawing end angle () 2, calculate as follows (counterclockwise rotation): (Parameter calculation: / I I I I (CPx, CPy) I \ \ \ \ , (Xc, Vc) "- "- '----- CD absolute addressing) Calculate the start point (CPx, CPy): CPx = Xc + [r cos () 1 1] CPy = Yc + [r sin () 1 tl Calculate the end point (Xe, Ye): Xe = Xc + [R cos () 2 1] Ye = Yc + [R sin (}2 11 (where, R = ~(CPx- XC)2+ (CPy- YC)2 .. r) (Parameter calculation: (1) relative addressing) Calculate the start point (CPx, CPy): CPx = Xc + [r cos () 1 11 CPy = Yc + [r sin () 1 11 Same as in absolute addressing Calculate the center coordinates (dXc, dYc): dXc = - [r cos () 1 t1 dYc = - [r sin (}1 11 Calculate the end point (dXe, dYe): dXe = dXc + [R cos (}2 1] dYe = dYc + [R sin (}2 11 where, (R = ~(CPx- XC)2+ (CPy- YC)2 .. r) HITACHI 303 v [Example 2] Given center coordinates (Xc, Yc), start point (CPx, CPy) and drawing angle 0, calculate as follows (counterclockwise rotation): (Xe, YeJ / I I I I I \ \ (Parameter calculation: CD absolute addressing) Calculate the end point (Xe, Ye): Xe = Xc + [R cos (0+01) 11 Ye = Yc + [R sin (0+01) 11 where, R = J(CPx- XC)2+ . 5 ~ 0.5 V MA.T/RA. MA .. /RA. ~ @ ~ Vee -2.0V Address - ® MA,,/RA. VO.5V @ir- X ~ () -X w I\,) W K= I--Vee - 2.0 V ) 0.5V (@ i--=Vcc -2.0V Vee - 2.0V 1\ J I@ @l DRAW @ r=:0.5V @ x 0.8V @I @I ~ MRD ~~ Vee - 2.0V 0.5V , @ ./ 2.2V Data ~ 0.8V Vee - 2.0 V MAII/RA. MCYC 0.8V @ @ RA. \ 0.8V 0.8V I-- \ 0.5V Figure T -7 Frame Memory Read Cycle Timing (ACRTC - Frame Memory) 0.5V V (.) 1'1.) ~ :z: \ 2CLK ~ (') - \ 0.8V ~ :z: 0.8V \ @ Vee -2.0 V \ AS 0.5V 0.5V ~ ~ @ I@ MAD. -MAD.. .... MA.o / RAe ~ Vee - 2.0V Address 0.5V - I® >--< Vee - 2.0V 0.5 V Data t-- @> MAn/ RA. MA .. / RAo MA .. / RA. RA. MCYC ). \ - MRD 1'\ V ~ C Vee - 2.0V 0.5V ~ ~ @ ~ - Vee - 2.0 V J 0.5V , @ II 0.5V 0.5 V ~ @ DRAW 0.8V , 0.5V Figure T -8 Frame Memory Write Cycle Timing (ACRTC - Frame Memory) - r 0.5V 2CLK , Rdrp.sh eyelp. \ O.8V \ ·o.sv "1 ~ ) H ATR ~ ~ "Low" I ® C Vcc -2.oV o.sv ! J \ J @"J I--"'Vcc -2.oV , i\ __ I (@ Vce -2.oV ~ 1\ ~ ~ l: "Low" o.sv ~ HSYNC Refresh· Address I@t-- ATR ~ DRAW \ ® i@ MRD - - ~ WL '\ \ @{\ ~ ¥-Vcc -2.oV Refresh Address O.5V MA/RA MCYC \ ------ Vee -2.oV ~ MAD , . @ t-@ AS - Attribute Control Information Output Cycle O.5V J .~ * When AS is "High", a "0" output is given. - Figure T-9 Frame Memory Refresh/Attribute Control Information Output Cycle Timing (') l: w '" VI Vee -2.0V Co) ~ % ~ zCLK o % MCYC 8.8 Vcc-z.OV RSYNC VSYNC O.5V DISPl DISP2 o.r.V CUDl CUDlI O.5V Vcc -2.0V Vcc-z.oV VCC-lI.OV EXSYNC (OUTPUT) CRR O.5V Vcc-lIJJV O.5V Figure T -10 Display Control Signal Output Timing 'XSYNC === I· -I. \ (Fcom MAST'R) .EXSYNC MCYC MCYC l: ~ (') Ar~ 7"--../ ~@ O.8V f- ~' ~~ (Phase Not Shifted) When the leading edge of EXSYNC enters this period, ACRTC shifts the internal phase according to the above sequence. l: W N '.J - I = --I loW O.5V HSYNC (SLAV') 2CLK II 11 Cycl, {'ClK{ Figure T -11 EXSYNC Input Timing w t-,.) ex> J: ~ (Light pen rise cycle) (') J: ZCLK MCYC MADo-MAD" @ @ @ @ LPSTB O.8V 0.8 V (When LPSTB rises in this period, memory address "M + 3" is set in the light pen address register.) Figure T -12 Input lPSTB Timing and light Pen Address 0.8V @ 0.8V @ . --=-- I \ 0.8V @ \ 2.2V 0.5 V Figure T -13 RES Input and DACK Input Timing (System Reset and 16-bit/8-bit Selection) 2CLK IRQ Figure T-14 IRQ Output Timing HITACHI 329 Signal Load Condition 1----=----------DO~D15 DTACK 5.0V Test Point DREQ MADO~MADl5 RL= 1.8K Q MAl6/RAO~MAl9/RA3 C =40pF RA4 R =lOKQ VSYNC, IISYNC EXSYNC MCYC, AS, MRD DRAW, CHR • DISPl, DISP2 CUDl, CUD2 -- Figure T-15 Test Load Circuit A 5.0V IRQ. DONE 0------+ r { RL = 1.8kD c = 40pF Figure T -16 Test Load Circuit B 330 HITACHI All diodes are 1S2074(8)'5 or the equivalent. HITACHI AMERICA, LTD. SEMICONDUCTOR AND IC SALES & SERVICE DIVISION HEADQUARTERS Hitachi, Ltd. Nippon Bldg., 6-2, 2-chome Ohtemachi, Chiyoda-ku, Tokyo, 100, Japan Tel: 212-1111 Telex: J22395, J22432 REGIONAL OFFICES NORTHEAST REGION Hitachi America, Ltd. 5 Burlington Woods Drive Burlington, MA 01803 617/229-2150 U.S. SALES OFFICE Hitachi America, Ltd. Semiconductor and IC Sales & Service Division 2210 O'Toole Avenue San Jose, CA 95131 Tel: 408-942-1500 Telex: 17-1581 Twx: 910-338-2103 Fax: 408-942-8225 Fax: 408-942-8880 DISTRICT OFFICES • Hitachi America, Ltd. 1700 Galloping Hill Rd. Kenilworth, NJ 07033 201/245-6400 • Hitachi America, Ltd. 3500 W. 80th Street, Suite 660 Bloomington, MN 55431 612/831-0408 • Hitachi America, Ltd. 80 Washington St., Suite 302 Poughkeepsie, NY 12601 914/485-3400 • Hitachi America, Ltd. 1 Parklane Blvd., #1222E Dearborn, Mi 48126 313/271-4410 • Hitachi America, Ltd. 6161 Savoy Dr., Suite 850 Houston, TX 77036 713/974-0534 • Hitachi America, Ltd. 5775 Peachtree-Dunwoody Rd. Suite 270C Atlanta, GA 30342 404/843-3445 • Hitachi America, Ltd. 18004 Sky Park Blvd., Suite 200 Irvine, CA 92714 714/261-9034 • Hitachi America, Ltd. 10300 S.w. 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