1985_Zilog_Data_Book 1985 Zilog Data Book

User Manual: 1985_Zilog_Data_Book

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TRADEMARK ACKNOWLEDGEMENTS
Zilog

Z8® MCU
Z80® CPU
Z8000® CPU
Z8001® CPU
Z8002® CPU
Super-8® MCU
Z-BUS® Bus
Z800™ MPU
Z8003™ VMPU
Z8004™ VMPU
Z8010™ MMU
Z8070™ FPU
Z80,000TM CPU
asm800™ Z800™ Cross-Assembler
asm80KTM Z80,000TM Cross-Assembler
CC800™ Z800™ C Cross-Compiler
cc80KTM Z80,000TM C Cross-Compiler
pas800™ Z800™ Pascal Cross-Compiler
pas80K™ Z80,000TM Pascal Cross-Compiler
Z-SCANTM Emulator

Other Companies
Ada is a registered trademark of the U.S. Government, Ada Joint Program Office (AJPO).
C-ISAM is a trademark of Relational Database Systems, Inc.
CPIM 80 is a trademark of Digital Research, Inc.
CPIM 8000 is a trademark of Digital Research, Inc.
IBM is a registered trademark of International Business Machines, Corp.
MACRO 80 MAC80 is a trademark of Microsoft Corporation.
UNIX is a trademark of AT&T Bell Laboratories; Zilog is licensed by AT&T Technologies, Inc.
VAX is a trademark of Digital Equipment Corporation.

© 1982, 1983. 1985 by ZlIog, Inc, All nghts reserved. No part of
this publication may be reproduced, stored In a retneval system,
or transmitted, In any form or by any means, electronic, mechanIcal, photocopYing, recording, or otherwise, without the prior
wntten permission of Zllog
The Information contained herein IS subject to change without
notice Zilog assumes no responsibility for the use of any
circuitry other than circuitry embodied In a Zllog product No
other CIrCUit patent licenses are Implied
All specifications (parameters) are subject to change without
notice. The applicable Zllog test documentation will specify
which parameters are tested.

Table of Cale.1s
za Family ......................................... , ................................................ 3
Z8601/03 MCU Microcomputer.. ........................... .. ..................... .. ... . ............. 5
Z8611/12/13 MCU Microcomputer ................... ....................... ................ . .......... 23
Z8671 MCU Microcomputer with BASIC/Debug Interpreter...... . . .. ......................
. .......... 41
Z8681/82 ROM less Microcomputer. . .. ....
. . . . . . . . . . . . . .. . ......................
. ............ 63
"Z86L81/85 Low Power ROMless Microcomputer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ......... ....... .85
Super·a Family . ................................................................................... 107
"Z8800 Super-8 MCU Microcomputer. . . . . . . . . .. .. .................. . .................................... 109

zao family . ...................................................................................... 139
Z8400 CPU Central Processing Unit .. .. .. .. .. .... ...................... ............ ..
............ 141
Z8410 DMA Direct Memory Access Controller ................... " ........... ........... . . ........... . 171
Z8420 PIO ParaliellnputiOutput Controller.
.................
. . .. ............. . ............. 191
Z8430 CTC Counter Timer/Circuit
.. . . . . . . . .
. . . . . . . . . .. ............ ... ....
. . .. . .. 205
Z8440/1/2/4 SIO SeriallnputiOutput Controller.. ... ... . .......................... ... ..
. . ........ 217
Z8470 DART Dual Asynchronous RecelverlTransmitter. .. .............. ............ . .....
. . .. ..... . 235
Z8300 Low Power CPU Central Processing Unit. . . . . .. .
. . . . . . . . . .. .. ......
. ........ 249
Z8320 Low Power PIO ParaliellnputiOutput AC and DC Characteristics. .. ........ . .
.
. . . .. . .... 271
Z8330 Low Power CTC Counter/Timer Circuit AC and DC Characteristics . . . . . . . . . . .. ..... ....... .. . ............ 275
Z8340 Low Power SIO SeriallnputiOutput AC and DC Characteristics. . . . . . . . . . . ..
.. . . .. ... .
. 279
"Z84COO CMOS CPU Central Processing Unit ... '"
.. . . . . . . . . . . . . . .. ..................
. . 287
"Z84C20 CMOS PIO ParaliellnputiOutput AC and DC Characteristics. . . . . . . . . . . .
. . . . . . . .. .........
317
"Z84C30 CMOS CTC Counter/Timer Circuit AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ...
321
"Z84C40/1/2 CMOS SIO Serial InputiOutput AC and DC Characteristics. . . . . . . . . .. .......... ... . . . . . . . . . .. .. . 325
zaoo Family . ..................................................................................... 329
Z800 MPU Microprocessor. . . . . . .

.. . . . . . . . . . . . . . . . . . . . . . . .. ... .......... . .......

. ........ 331

zaooo Family . .................................................................................... 403
Z8001/2 CPU Central Processing Untt. . . . . . .. .......................... . ...........
. ........ 405
Z8003/4 VMPU Virtual Memory Processing Untt . . . . . . . . . . . . . . . . . . . . . . . . .. ............. ......... .. . ....... 441

zao,ooo Family

................................................................................... 475

Z80,OOO CPU Central Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ....... ............ .477

Z·BUS Peripherals . ................................................................................ 529
Z8070 FPU Floating POint Unit. . . .. ..... ....................... .......... ., .. .......... .... ..
. . 531
Z8010 MMU Memory Management Unit. . . . . . . . .. . ..................................... . ....... . ..... 559
Z8015 PMMU Paged Memory Management Unit . . . . .. . .......... . ................................. . .... 577
Z8016 Z-DTC Direct Memory Access Transfer Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ... ... .. 599
Z8030 Z-SCC Serial Communications Controller. . . . . . . . . . . . . . . . . . . . . . .. . .................................... 631
Z8031 Z-ASCC Asynchronous Serial Communications Controller. . . . . . . . . . . . . . . . . . .. .............. .......
" .. 653
Z8036 Z-CIO CounterlTimer and Parallel I/O Unit.... ............. ........................ .. .... .. ... ...673
Z8038 Z-FIO FIFO InputiOutput Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . ... 699
Z8060 FIFO Buffer Unit and Z-FIO Expander. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ................... .731
Z8068 Z-DCP Data Ciphering Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 739
Z8090/4 Z-UPC Universal Peripheral Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ....... 771
Z-BUS Component Interconnect .......................................................................... 755
"New Document

iii

Table of Coaleals (Continued)
Universal Peripherals .............................................................................. 769
Z8038 Z-FIO FIFO Input/Output Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . .
. .......................... 699
Z8060 FIFO Buffer Unit and Z-FIO Expander ................................................................. 731
Z8590/4 UPC Universal Peripheral Controller.. . ............................................................. 771
*Z8516 DTC Direct Memory Access Transfer Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ........................ 797
Z8530 SCC Serial Communications Controller ................................................................ 839
Z8531 ASCC Asynchronous Serial Communications Controller
.................. 861
Z8536 CIO Counter/Timer and Parallel 110 Unit ............................................................... 881
Z8581 CGC Clock Generator and Controller ................................................................. 907
*Z765A FDC Floppy Disk Controller ........................................................................ 915

Military Products . ................................................................................. 943
Development Products ............................................................................. 953
Z8 Development Module. . . . . . . . . .
. ...................................................... 955
Z8000 Development Module. . . . . . . . . . . . . . . . . . .
. ...................................................... 959
Z-UPC Development Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .. 963
EMS 8000 Emulator. . . . . . . . . . . . . . . . .
.......................
. .......................... 965
Z-SCAN 8 Emulator ................................................................................... 969
*Z-SCAN 80 Emulator. . . . . . . . . . . .
......................
. ........................... 975
Z-SCAN 8000 Emulator. . . . . . . . . . . . . . .
. ...................................................... 981
System 8000, Model 12 . . . . . . . .. ....
. .............................................. 985
System 8000, Model 22 . . . . . . . . . . . . . . .
. ...................................................... 987
System 8000, Model 32 ..... ',' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ... 989

Software . ........................................................................................ 991
Z800 Cross Software Package. . . .
. .................................................................. 995
*Z80,000 Cross Software Package. . . . .
............................................
. ............. 999
Z8070 Floating-Point Emulation Package.
.........
. .......................... 1003
ZRTSReal-TimeSoftware........
...........
. ............................................. 1011
*Ada .. . . . . . . .. . .. ...............
.........
. ............................................. 1015

Packaging . ..................................................................................... 1023
18-Pm Dual-in-Line Packages. .............................
. ............... 1023
28-Pin Dual-In-Llne Packages. . . . . . . . . . . . . . . . . . . .
.................
. .... 1024
. .... 1026
40-Pin Dual-In-Llne Packages. . . . . . . . . . . . . . . . . . . .
48-Pm Dual-in-Line Packages.. ..................
.............
. . . . . . . . . . . . .. 1028
64-Pin Dual-in-Line Package ............................................................................ 1030
44-Pm Chip Carriers. . . . . . . . . . . . . . . . . . . . . . . . . . .
. ......................................... 1031
68-Pin Chip Carriers. . . . . . . . . . . . . . . . . . . . . . .. ................
.........
. ......... 1032
Protopacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ......................................... 1035
Pin Grid Array. ...............................
. ......................................... 1037

Technical Training . .............................. , ................................................ 1041
Reader's Response Card . .......................................................................... 1045
Sales Offices . .............................................................................. Back Cover
*New Document

iv

Faaclloaalladex
Single Chip Microcomputers

Z8601
Z8611
Z8603
Z8613
Z8612
Z8671
Z8681
Z8682
Z86l81
Z86l85
Z8090
Z8590
Z8094
Z8594
Z8800
Z8801
Z8810
Z8811
Z8820
Z8821
Z8830
Z8831
Z8812
Z8813
Z8822
Z8823
Z8832
Z8833

Z8 8-Bit MCU, 2K ROM . . .. ......................................................
. .......... 5
Z8 8-Bit MCU, 4K ROM ........................................................................... 23
Z8 Prototyping Device, 2K External EPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . .
. .......... 5
Z8 Prototyping Device, 4K External EPROM Interface. . . . . . . . . . .
. ........... 23
Z8 8-Bit MCU, 4K External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ......... 23
Z8 8-Bit MCU with BASIClDebug Interpreter
..... ..... ...... .. ..... ....... .......
. .......... 41
Z8 8-Bit ROMless MCU ........................................................................... 63
Z8 8-Bit, Cost-effective, ROMless MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .............. 63
Z8 Lew Power, 8-Bit, ROM less MCU .................. , ................
. ............... 85
Z8 low Power, Power Down, 8-Bit, ROM less MCU . . . . . . . . . . . . . . . .
.. ... ..... ...
. ............. 85
Z8000 Z-UPC Universal Peripheral Controller. .
...............
. .............................. 771
UPC Universal Peripheral Controller. .
...........................
. .... 771
Z8000 Z-UPC Universal Peripheral Controller, External RAM. . . . . . . . . . . . . . .
. ..... ...
. ............. 771
UPC Universal Peripheral Controller, External RAM. . . . . . . . . . . . . . . . . . . . . . . . .
. . 771
Super-8 ROMless MCU . . . . .. ..................................... . . . . . . . . . .
. ............. 109
Super-8 ROM less MCU .
. .............................................................. 109
Super-8 MCU, 4K ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .............. 109
Super-8 MCU, 4K ROM.. .. .. .. .. .. .. .
.. .. ... .........
.. .. ... .......
.. .......... 109
Super-8 MCU, 8K ROM. . . . . . . . . . .
. . . . . . . . . . . . . .. ...............
. . 109
Super-8 MCU, 8K ROM. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .
. ............ 109
Super-8 MCU, 16K ROM. . . . . . . . . .
........ ..... .. ...... ..
. .............. 109
Super-8 MCU, 16K ROM. . . . . . . .. . .
...................
. ........................... 109
Super-8 MCU, 4K External ROM IE PROM ............................................................ 109
Super-8 MCU, 4K External ROM/EPROM . . . . . . . . . . . . . . . . . . . .
.. .. ... ...
.........
. . 109
Super-8 MCU, 8K External ROM/EPROM . . . .
. ........................ 109
Super-8 MCU, 8K External ROM/EPROM ............................................................ 109
Super-8 MCU, 16K External ROM/EPROM . . . . . .. . .................................................. 109
Super-8 MCU, 16K External ROM/EPROM ........................................................... 109

S-Bit Microprocessors

Z8108
Z8400
Z84COO
Z8300

Z800 High Integration MPU ....................................................................... 331
Z80 CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ............................................. 141
Z80 CMOS CPU . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . .. .. . . . . . . . . . .
. . 287
Z80l low Power CPU
....................................................................... 249

16-Bit Microprocessors

Z8001
Z8002
Z8003
Z8004
Z8100

Z8000 Segmented CPU
... .. ..... .........
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ........ 405
Z8000 Nonsegmented CPU ...................................................................... 405
Z8000 Segmented Virtual Memory Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ............ 441
Z8000 Nonsegmented Virtual Memory Processing Unit ................................................. 441
Z800 High Integration MPU ....................................................................... 331

32·Blt Microprocessor

Z80,000

Z80,000 CPU with 32-bit MMU and 256 Byte Instruction/Data Cache ....................................... 477

Peripherals

Arithmetic Processing Unit
Z8070
FPU Floating Point Unit .......................................................................... 531
Clock Product
Z8581
CGC Clock Generator and Controller ................................................................ 907
Serial Communication
Z8030
Z8000 Z-SCC Dual Channel Serial Communications Controller ............................................ 631
Z8530
SCC Dual Channel Serial Communications Controller ................................................... 839
Z8031
Z8000 Z·ASCC Dual Channel Asynchronous Serial Communications Controller ............................... 653
Z8531
ASCC Dual Channel Asynchronous Serial Communications Controller ...................................... 861
Z8440
Z80 SIOIO Dual Channel, Synchronous/Asynchronous, Seriallnput/Output Controller .......................... 217

v

FanC:llonallndex (Continued)
Peripherals (Continued)
Z84C40
Z80 CMOS SIO/O Dual Channel, Synchronous/Asynchronous, Serial Input Output Controller ..................... 325
Z8340
Z80l low Power SIO/O Dual Channel, Synchronous/Asynchronous, Serial Input Output Controller ................. 279
Z8441
Z80 S10/1 Dual Channel, Synchronous/Asynchronous, SeriallnputiOutput Controller.
. ........ 217
Z84C41
Z80 CMOS S10/1 Dual Channel, Synchronous/Asynchronous, SeriallnputlOutput Controller. . . . . . . . . . . . . . . . .. ..325
Z8442
Z80 S10/2 Dual Channel, Synchronous/Asynchronous, SeriallnputlOutput Controller. . .
. . . . . . . . .. . ........ 217
Z84C42
Z80 CMOS S10/2 Dual Channel, Synchronous/Asynchronous, Serial Input/Output Controller. . . . . . . . . . . .
. .... 325
Z8444
Z80 S10/4 Dual Channel, Synchronous/Asynchronous, Serial Input/Output Controller. .
. .......... 217
Z8470
Z80 DART Dual Channel, Asynchronous Receiver/Transmitter. . . . . . . . . .
. ........................ 235

Parallel I/O and CounterlTimer
Z8036
Z8000 Z-CIO Counter/Timer and Parallel 110 Unit ...... .
CIO Counter/Timer and Parallel 110 Unit. ....... .
Z8536
Z8038
Z8000 Z-FIO FIFO InputlOutputinterface Unit. . . . ..
. ....... .
Z8060
Z8000 FIFO Buffer Unit and Z-FIO Expander. ..
Z8420
Z80 PIO Dual Port, ParaliellnputlOutput Controller.
Z84C20
Z80 CMOS PIO Dual Port, Parallel Input/Output Controller ........ .
Z8320
Z80l low Power PIO Dual Port, ParaliellnputlOutput Controller
Z8430
Z80 CTC Four Channel, Counter/Timer Circuit. ..
Z84C30
Z80 CMOS CTC Four Channel, Counter/Timer CirCUit ..
Z8330
Z80l low Power CTC Four Channel, Counter Timer Circuit.. . ......... .
Z-BUS Peripherals
Z8010
Z8000 MMU Memory Management Unit.
Z8015
Z8000 PMMU Paged Memory Management Unit ...
Z8016
Z8000 Z-DTC Direct Memory Access Transfer Controller.
Z8090
Z8000 Z-UPC Universal Peripheral Controller ..
Z8094
Z8000 Z-UPC Universal Peripheral Controller, External RAM. . .. .
Z8068
Z8000 Z-DCP Data Ciphering Processor ..
. .. . ... .
Z8070
FPU Floating POint Unit.
Zllog Z-BUS Component Interconnect Summary.

. .. 673
. .... 881
. ... 699
. .... 731
· .... 191
· .317
.... 271
.. .. 205
..321
..275
. .. 559
.577
..... ...
.599
. .................... 771
. ... 771
.739
.. .. 533
· . 755

Other Peripheral Products
Z8590
UPC Universal Peripheral Controller.
Z8594
UPC Universal Peripheral Controller, External RAM.
Z8016
Z-DTC Direct Memory Access Transfer Controller.
Z8516
DTC Direct Memory Access Transfer Controller.
Z765A
FDC Floppy Disk Controller.
Z8410
DMA Dual Port, Direct Memory Access Controller ....
Z8070
FPU Floating POint Unit.

. ...
. ...
. ....
. ........
· ...
· ....
.. ....

Development Products
Z8 Development Module, 2K Prototyplng and Evaluation Board .....
Z8 Development Module, 4K Prototyplng and Evaluation Board.
Z-SCAN 8 Emulator.
. .. . .... .
Z-SCAN 80 Emulator.
. . .. .... . .. .
Z8000 Development Module, PrototYPlng and Evaluation Board ... .
Z8001 Development Module, PrototYPlng and Evaluation Board ... .
EMS 8000 Emulator
........ .
Z-SCAN 8000 Emulator. . .
. ......... .
Z-UPC Development Module. .
. ..................... .
System 8000 Multi-user Development System, Model 12
System 8000 Multi-user Development System, Model 22 .
System 8000 Multi-user Development System, Model 32 .
Software
Z800 Cross Software Package.
.........
Z80,000 Cross Software Package.
...................
Z8070 Floating-Point Unit Emulation Package. . . . . .
ZRTS Z8000 Rc.'al-Tlme, Multitasking Software Tools. . . . . . . . . . . . .
, . . .. .., ....
Ada High-level Programming language. . .

vi

771
771
599
797
915
171
533

.. .. 955
..955
969
..975
. ... 959
.959
.965
.981
.... ......
. 963
.................................... 985
. ......................... 987
. ........................... 989

. ......... .
.....
. .............. .
. ....................... .
....
. .............. .
,..
. ............ .

. ................. 995
.. .. .. .. .. 999
1003
.. ........ 1011
· 1015

Part KaBlber lad_
Number
05-0103-00
05-0122-02
05-0122-03
05-0124-00
05-0123-00
05-0144-00
05-0207-00
05-0289-00
05-1300-00
05-2300-00
05-3300-00
05-6101-01
05-6158-01
05-6168-01
05-6222-00
05-6223-00
05-6223-01
07-0106-00
07-0183-00
07-0203-00
07-0209-00
07-0211-00
07-0145-00
07-3014-01
07-3014-05
07-3015-01
07-3015-05
07-3016-01
07-3016-05
Z765A
Z8OO1
Z8002
Z8003
Z8004
Z8010
Z8015
Z8016
Z8030
Z8031
Z8036
Z8038
Z8060
Z8068
Z8070
Z8090
Z8094

Description
Z-SCAN 8000 Emulator ..................................................................... 981
EMS 8000 Emulator without pod, 60 Hz, 115V. . ................................................. 965
EMS 8000 Emulator without pod, 50 Hz, 230V .................................................... 965
EMS 8000 Emulator, External Probe Interface Board ............................................... 965
EMS 8000 Emulator, Map Memory Board ....................................................... 965
Z-SCAN 8 Emulator ........................................................................ 969
Z-UPC Development Module ................................................................. 963
Z8070 Floating-POint Unit Emulation Package ................................................... 1003
System 8000 Multi-user Development System, Model 12 ............................................ 985
System 8000 Multi-user Development System, Model 22 ............................................ 987
System 8000 Multi-user Development System, Model 32 ............................................ 989
Z8000 Development Module, Prototyping and Evaluation Board ...................................... 959
Z8 Development Module, 2K Prototyping and Evaluation Board ...................................... 955
Z8001 Development Module, PrototYPlng and Evaluation Board ...................................... 959
Z8 Development Module, 4K PrototYPlng and Evaluation Board ...................................... 955
Z-SCAN 80 Emulator, 115V. ...... .............................................. . ......... 975
Z-SCAN 80 Emulator, 230V . . . . . . . .. . ....................................................... 975
ZRTS Z8000 Real-Time, Multitasking Software Tools .............................................. 1011
Z800 Cross Software Package for System 8000 ................................................... 995
Z80,OOO Cross Software Package for System 8000 ................................................ 999
Z800 Cross Software Package for VAX UNIX ..................................................... 995
Z80,OOO Cross Software Package for VAX UNIX ................................................... 999
EMS 8000 Emulator II for System 8000 . . . . . . . . . . .. . ........................................... 965
Ada for System 8000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .................................... 1015
Ada System 8000 Software Update Service ..................................................... 1015
Ada for VAX VMS ........................................................................ 1015
Ada VAX VMS Software Update Service ........................................................ 1015
Ada for VAX UNIX......................................................................... 1015
Ada VAX UNIX Software Update Service ....................................................... 1015
FDC Floppy Disk Controller. . . .. . ........................................................... 915
Z8000 Segmented CPU ..................................................................... 405
Z8000 Nonsegmented CPU ................................................................. 405
Z8000 Segmented Virtual Memory Processing Unit. ............................................... 441
Z8000 Nonsegmented Virtual Memory ProceSSing Unit. ............................................ 441
Z8000 MMU Memory Management Unit. .. . ................................................... 559
Z8000 PMMU Paged Memory Management Unit ................................................. 577
Z8000 Z-DTC Direct Memory Access Transfer Controller •........................................... 599
Z8000 Z-SCC Serial Communications Controller .................................................. 631
Z8000 Z-ASCC Asynchronous Serial Communications Controller ..................................... 653
Z8000 Z-CIO CounteriTImer and Parallel 110 Unit. ................................................. 673
Z8000 Z-FIO FIFO Input/Output Interface Unit .................................................... 699
Z8000 FIFO Buffer Unit and Z-FIO Expander. .
. . . .. .. ..... .. .... . ......... 731
Z8000 Z-DCP Data Ciphering Processor ....................................................... 739
Z8000 FPU Floating-Point Unit. ............................................................... 531
Z8000 Z-UPC Universal Peripheral Controller .................................................... 771
Z-UPC Universal Peripheral Controller, External RAM .............................................. 771

vii

Pari R.....ber lad. (Continued)
Number

Description

Z8l00
Z8l08
Z8300
Z8320
Z8330
Z8340
Z8400
Z84l0
Z8420
Z8430
Z8440
Z844l
Z8442
Z8444
Z8470
Z84COO
Z84C20
Z84C30
Z84C40
Z84C4l
Z84C42
Z8516
Z8530
Z853l
Z8536
Z8581
Z8590
Z8594
Z8601
Z8603
Z86ll
Z86l2
Z8613
Z8671
Z8681
ZB682
Z86lB1
Z86l85
Z8800
ZB801
Z8810
Z881l
Z8812
Z8813
Z8820
Z8821
Z8822
Z8823
Z8830
Z8831
Z8832
Z8833
Z80,OOO

Z800 High Integration MPU, 16-bit Bus Interface .................................................. 331
Z800 High Integration MPU, 8-bIt Bus Interface ................................................... 331
Z80l Low Power CPU ...................................................................... 249
Z80l Low Power PIO Dual Port, ParaliellnputiOutput Controller ...................................... 271
Z80l Low Power CTC Four Channel, Counter Timer Circuit .......................................... 275
Z80l Low Power SIO Dual Channel, Synchronous/Asynchronous, SeriallnputlOutput Controller ............. 279
ZBOCPU ................................................................................ 141
Z80 DMA Dual Port, Direct Memory Access Controller. ............................................. 171
Z80 PIO Dual Port, ParaliellnputlOutput Controller ................................................ 191
Z80 CTC Four Channel, CounterlTimer Circuit. . . . . . . . . . . . . . . . . . . . . . . . .. . ........................ 205
Z80 SIO/O Dual Channel, Synchronous/Asynchronous, Serial Input/Output Controller ..................... 217
Z80 SIO/l Dual Channel, Synchronous/Asynchronous, SeriallnputiOutput Controller ..................... 217
Z80 S10/2 Dual Channel, Synchronous/Asynchronous, SeriallnputlOutput Controller ..................... 217
Z80 S10/4 Dual Channel, Synchronous/Asynchronous, SeriallnputiOutput Controller ..................... 217
Z80 DART Dual Channel, Asynchronous Receiver/Transmitter ........................................ 235
Z80 CMOS CPU ............ .. . ......................................................... 287
Z80 CMOS PIO Dual Port, ParaliellnputlOutput Controller........................................... 317
Z80 CMOS CTC Four Channel, CounteriTImer CircUit .............................................. 321
Z80 CMOS SIO/O Dual Channel, Synchronous/Asynchronous, SenallnputlOutput Controller ................ 325
Z80 CMOS SIO/l Dual Channel, Synchronous/Asynchronous, SeriallnputlOutput Controller ................ 325
Z80 CMOS S10/2 Dual Channel, Synchronous/Asynchronous, SeriallnputlOutput Controller.
. ... 325
DTC Direct Memory Access Transfer Controller ................................................... 797
SCC Serial Communications Controller ......................................................... 839
ASCC Asynchronous Senal Communications Controller . . . . . . . . . . . . . . . . . . . . . . . .. . ................. 861
CIO Counter/Timer and Parallel 110 Unit. ........................................................ 881
CGC Clock Generator and Controller ........................................................... 907
UPC Universal Peripheral Controller ........................................................... 771
UPC Universal Peripheral Controller, External RAM ................................................ 771
Z8 8-Bit Single Chip MCU, 2K ROM .............................................................. 5
Z8 Prototyping Device with 2K External EPROM Interface ............................................. 5
Z8 8-Bit Single Chip MCU, 4K ROM ............................................................. 23
Z8 8-Bit Single Chip MCU, 4K External Memory Interface ............................................ 23
Z8 Prototyping Device with 4K External EPROM Interface. . . . . . . . . . . . . . . . . . . . . .. . ................... 23
Z8 8-Bit Single Chip MCU With BASIC/Debug Interpreter ............................................. 41
Z8 8-Bit Single Chip, ROM less MCU . .. ........ . .............................................. 63
Z8 8-Bit Single Chip, ROMless MCU .. ........................... . ........................... 63
Z8 Low Power, Power Down, 8-Blt Single Chip ROM less MCU. ....... ......................... . .... 85
Z8 Low Power, 8-Blt Single Chip ROMless MCU .................................................... 85
Super-8 ROM less MCU ..................................................................... 109
Super-8 ROMless MCU ..................................................................... 109
Super-8 MCU, 4K ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ................ . ... 109
Super-8 MCU, 4K ROM. .. . .................. .... ... ............ ............ . ........ 109
Super-8 MCU, 4K External ROM/EPROM ....................................................... 109
Super-8 MCU, 4K External ROM/EPROM. . . . . . . . . . . .. . ........................................ 109
Super-8 MCU, 8K ROM. . . . . . . . . .. . ........................................................ 109
Super-8 MCU, 8K ROM. . . . . . . . .. .......... .............................................. 109
Super-8 MCU, 8K External ROM/EPROM. . . . . . . . . . .. ........................................ .109
Super-8 MCU, 8K External ROM/EPROM ....................................................... 109
Super-8MCU,16KROM ................................................................ 109
Super-s MCU, 16K ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .......................... 109
Super-8 MCU, 16K External ROM/EPROM ..................................................... 109
Super-8 MCU, 16K External ROM/EPROM ...................................................... 109
Z80,OOO CPU With 32-bit MMU and 256 Byte Instruction/Data Cache .................................. 477

A1185XX components are compatible Wlth processors cthar than Zllog'. ZSOOl, Z8OO2, zs003,
and Z8OO4. For further mformation refer to the IndlVldual product spectflcallons.

viii

Z8
Family

Zilog

Zilog Z8® Family
The Standard For
Single-Chip Microcompaters
March 19S5

In 1976, Zilog emerged into the
microprocessor world with its ZSO
CPU Family. With this industrystandard classic of 8-bit architecture,
Zilog established its design expertise
and cost-efficient production
capability.
While the Z80 earned and maintained strong customer support,
inevitable demands for new
applications-intelligent terminals,
dedicated control and communication-spawned an accompanying need for a new, lean technology.
With an instinct for simplicity and
elegance, Zilog architects created a
microcomputer with the most sophisticated computing power available
on a single chip: the Z8 Family. In a
bold departu re from the standard
AlB accumulator tradition, a fresh,
register-oriented architecture was
devised that challenges the "multichip solution." Z8-based designs
minimize chip-count while offering a
configuration that can be easily
expanded to meet the requirements
of enhancement options and future
improvements.

The Z8 Family encompasses the
whole spectrum of system development, from prototyping to full production. For prototyping and
preproduction, or where code flexibility is important, the Z8603 and
Z8613 Protopack EPROM-based
parts are the most appropriate. The
ROM-based ZS601 and ZS611
microcomputers are used in highvolume production applications after
the software has been perfected.
The Z8603 IS pin-compatible with
the Z8601, and the Z8613 is compatible with the ZS611.
For ROMless applications, two
versions of the Z8 microcomputer
are available: the ZS681 and Z8682
ROM less microcomputers. In addition, there is a military version of the
Z8611 4K ROM device, a 40-pin
ceramic package.
The newest member of the family,
the Z86LS1 IZ86L85, is a Low Power
ROM less microcomputer available
in a 40-pin DIP and a 44-pin PCC.

The Z8671 MCU is a complete
microcomputer pre-programmed
with a BASIClDebug interpreter. ThiS
device, operating With both external
ROM or RAM and on-chip memory
registers, is ideal for most industrial
control applications, or whenever
fast and efficient program development is necessary.
Dedicated control IS the key word
for Z8 applications. Since speed IS a
prime consideration in such applications, the entire ZS family is available
in both 8 and 12 MHz verSions,
supported by two development
tools: the ZS OM Development Module and the Z-SCAN S. The OM
provides elementary in-circuit emulation (ICE) capability, and the Z-SCAN
8 module provides full ICE capability
including trace memory. With these
tools, the user is equipped for practically any type of Z8 microcomputer
development.

3

Z8 Family of Products
UART Hardware, 128 RAM

ROM
Capacity

Maximum
Programmable
110 Pins

1/0 Pins

PCB
Footprint

Comments

32,4 Ports

8 Power,
Control

40-Pin DIP
44-Pin PCC

Masked ROM part used primarily
for high-volume production.

0

32,4 Ports

8 Power,
Control plus
24 EPROM

40-Pin DIP

Piggyback part used where program
flexibility IS required (prototYPlng).

Z8603

0

32,4 Ports

8 Power,
Control plus
24 EPROM

40-Ptn DIP
(C.O.B.)

Low-costllow-profile chlp-on-board

4KROM

Z8611

4K

32,4 Ports

8 Power,
Control

40-Pin DIP
44-Pin PCC

Masked ROM part, used primarily
for high-volume production.

4K Development
Part

Z8612

0

32,4 Ports

8 Power,
Control plus
24 External
Memory

64-Pin DIP
68-Pin PCC

ROMless part used primarily in
development systems.

4K Protopack

Z8613

0

32,4 Ports

8 Power,
Control plus
24 EPROM

40-Pin DIP

Piggyback part used when program
flexibility is required (prototyping).

4K Proto pack,
Low Profile

Z8613

0

32,4 Ports

8 Power,
Control Plus
24 EPROM

40-Pin DIP
(C.O.B,)

Low-costllow-profile chip-on-board

BASIC/Debug

Z8671

2K

24,3 Ports

8 Power,
Control

40-Pin DIP
44-Pin PCC

High level language applications,

ROMless

Z8681/
Z8682

0

24,3 Ports

8 Power,
Control Plus
8 External
Memory

40-Pin DIP
44-Pin PCC'

Low-cost ROM less production part
with reduced I/O, Program memory
is external.

ROMless,
Low Power

Z86L81

0

24,3 Ports

8 Power,
Control plus
8 External
Memory

40-Pin DIP
44-Pin PCC

Low Power ROMless, 50% of
standard current draw.

ROMless,
Low Power

Z86L85

0

24,3 Ports

8 Power,
Control plus
8 External
Memory

40-Pin DIP
44-Pin PCC

Low Power ROM less with Powerdown option,

Product

Number

2KROM

Z8601

2K

2K Protopack

Z8603

2K Protopack,
Low Profile

• Available only for Z8681.

4

Dedicated

Z8® Z8601
Z8® Z8603

Product
Specification

Zilog

Z8601 Smgle-ChlP MICrocomputer wIth 2K ROM
Z8603 Prototypmg DevIce wIth EPROM Interface

April 1985
Features

• Complete microcomputer, 2K bytes of ROM,
128 bytes of RAM, 32 I/O lines, and up to
62K bytes addressable external space each
for program and data memory.
• 144-byte register hie, includmg 124
general-purpose registers, four I/O port
regIsters, and 16 status and control
registers.
• Average instruction execution time of
1.5 /LS, maximum of 3 /LS.
• Vectored, priority interrupts for I/O,
counter/timers, and UART.
The Z8601 microcomputer introduces a new
level of sophistication to Single-chip architecture. Compared to earlier single-chip microcomputers, the Z8601 offers faster execution;
more efficient use of memory; more sophisticated interrupt, inpuVoutput and bit-manipulation capabilities; and easier system expansion.
Under program control, the Z8601 can be
tailored to the needs of its user. It can be con-

PORTO

PORT 2

(NIBBLE
PROGRAMMABLE)
1/0 OR Aa-A15

• On-chip oscillator that accepts crystal or external clock drive.
• Single + 5 V power supply-all pins TTLcompatible.

figured as a stand-alone microcomputer with
2K bytes of internal ROM, a traditional microprocessor that manages up to 124K bytes of
external memory, or a parallel-processing element in a system with other processors and
peripheral controllers linked by the Z-BUS. In
all configurations, a large number of pins
remain available for I/O.

+5V

P3,

XTAL2
XTAL1

P3,

P3,
Pa"

REm

P2,

RIW

P2,
P2,
P2,

os

(BIT PRO·
GRAMMABLE)

.0

110

P3,
Pa,

P20
P3,
P3,

PO,
PO,

P1,
P1,

PO,

P1,

PO,

P1,

PO,
PO,

1'1,

1/0 OR ADo-AD7

PO,
PO,

2037·001.002

P2,
P2e
P2,

PORT 1

Figure I. Pin function.

w

• Register Pomter so that short, fast mstruchons can access any of nme workmg
register groups m I /Ls.

GND

(BVTE
PROGRAMMABLE)

I-...

• Full-duplex UART and two programmable
8-bit counter/hmers, each with a 6-bit programmable prescaler.

1'1,
P1,
1'1,

Figure 2a. olD-pin Dual-In-Llne Package (DIP).
Pin Assignment.

5

I

Pin
Description

for 1/0 or external memory mterface.

AS. Address Strobe (output, active Low).
Address Strobe IS pulsed once at the begmnmg of each machine cyeie. Addresses output
Via Port 1 for all external program or data
memory transfers are valid at th~rallmg edge
of AS. Under program control, AS can be
placed in the high-Impedance state along with
Ports 0 and I, Data Strobe and Reacl/Write.

RESET. Reset (mput. active Low). RESET imtiahzes the 2860 I. When RESET is deachvated,
program execution begms from mternal program locahon OOOCH.

R/W. ReadlWrite (output). R!W is Low when
the 28601 is wrltmg to external program or
data memory.

DS. Data Strobe (output, achve Low). Data
Strobe IS activated once for each external
memory transfer.

XTALI. XTAL2. Crystal 1, Crystal 2 (hme-base
input and output). These pins connect a
parallel-resonant crystal (8 or 12 MHz maximum) or an external smgle-phase clock (8 or
12 MHz maximum) to the on-chip clock
oscillator and buffer.

Plio-Po.,. Plo-PI7. P20-P2? P30-P3,. 110 Port
Lines (input/outputs, TTL-compahble). These
32 Imes are divided into four 8-bit 1/0 ports
that can be configured under program control

 'I'>' .¢~~~.;' <{b" 'I"" '1",,~ 4'-"
6

5

4

3

2

1

«u

~

41

~

IIE!IET 7

39

HC

8

38

P24

ll!I 9

37

P2,

n

10

36

P2,

P3.

11

35

P2,

GHD

12

34

P20

P3,

13

33

P3,

POo

14

32

P3.

PO,

15

31

P17

PO,

16

30

P1.

HC

17

29

P1.

R/W

Z880t

MCU

18 19 20 21 22 23 24 25 26 27 28


IAQ>

IRQI
IAQ2

~~------------------i

IA01
IRQ1

NOT ADDRESSABLE

IAoo
IAoo

Figure 4. Program Memory Map

LOCATION
25.

STACK POINTER BITS 7-0)

IDENTIFIERS
OPL

2M

STACK POINTER (BITS 16-8)

SPH

......
......
...
......
......
...
25'

247

.

,

24'

REGISTER POINTER
PROORAM CONTROL FLAGS
INTERRUPT MASK REGISTER
INTERRUPT REQUEST REGISTER

INTERRUPT PRIOArrY REGISTER

r-_-~--lfj::r::,I,::r::;:~.:.:.::.~::

~~r~'~'~'__L-~~~--i ...

AP
fLAGS
IMR
IAQ

TMuppernlbbl.oflh....gl.terlll....dret.

~~wlcledbyth.regl.terpolnl.r.peclftes

Iheecllveworklng"'lIlltefgrouP

r---------....,"7

IPR

PORTS 0-1 MODE

PO'M

PORT 3 MODE

P3M

PORT 2 MODe
TO PRESCALER
TIMERICOUNTER 0
T1 PRESCALER
TIMERICOUNTER 1
TIMER MODE
SERIAL ItO

Figure S. Data Memory Map

P2M
PAEO

T.

PRE1

T'
TMA
SIO
Th.tower
nlbbl.ol
tMregl.ter

NOT

IMPLEMENTED

1lI••cId.....

prowldedby
lheln.tructlon
pol"tlioltl•

127

• paclfled
M.....

GENERAL·PURPOSE
REGISTERS

PORT 3
PORT 2
PORT 1
PORTO

Figure 6. Register File

8

P'P.
P'
PO

1----------1,.
-~

-----.OPOR••----- •

Figure 7. Register Pointer

2037-004,005,006,007

Address
Spaces
(Continued)

directly or indirectly with an 8-bit address
field. The Z8601 also allows short 4-bit register
addressing using the Register Pointer (one of
the control registers). In the 4-bit mode, the
register file is divided into nine workingregister groups, each occupying 16 contiguous
locations (Figure 7). The Register Pointer
addresses the starting location of the active
working-register group.

Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and R255)
is used for the external stack, which can reside
anywhere in data memory between locations
2048 and 65535. An 8-bit Stack Pointer (R255)
is used for the internal stack that resldes within
the 124 general-purpose registers (R4-RI27).

Serial

Port 3 lmes P30 and P37 can be programmed
as senal I/O lines for full-duplex serial asynchronous recelver/transmltter operahon. The
blt rate lS controlled by Counter/Tlmer 0, wlth
a maXlmum rate of 62.5K hlts/second for 8
MHz and 94.8K blts/second for 12 MHz.
The Z8601 automahcally adds a start blt and
two stop blts to transmltted data (Flgure 8).
Odd panty is also aVallable as an option. Elght
data blts are always transmltted, regardless of

panty selection. If parity is enabled, the elghth
bit lS the odd panty blt. An mterrupt request
(IRQ4) lS generated on all transmItted
characters.
ReceIved data must have a start bIt, eIght
data bIts and at least one stop bit. If panty IS
on, bit 7 of the receIved data is replaced by a
parity error flag. Received characters generate
the IRQ3 interrupt request.

Transmitted Data

Received Data

(No Parity)

(No Parity)

Input/
Output

I

I~I~I~I~I~I~I~I~I~I~I
LSTART BIT

LSTARTBIT

' - - - - - E I G H T OATA BITS

' - - - - - - E I G H T DATA BITS

' - - - - - - - - - O N E STOP BIT

TWO STOP BITS

Transmitted Data

Received Data

(With Parity)

(With Parity)

~pl~1 pl~I~I~I~I~I~I~I~1

TI

II

LSTART BIT
' - - - - - - S E V E N DATA BITS

' - - - - - - - - - 0 0 0 PARITY

LSTART BIT
' - - - - - S E V E N DATA BITS

'---------~:~I:~~::~TR FLAG

TWO STOP BITS

Figure 8. Serial Data Formala

Counter/
Timers

2037-009

The Z8601 contains two 8-bit programmable
counter/timers (To and TI), each driven by its
own 6-bit programmable prescaler. The TI
prescaler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number
from 1 to 64. Each prescaler drives its counter,
which decrements the value (1 to 256) that has
been loaded into th6 counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQs (Til-is
generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (singlepass mode) or to automatically reload the

I...w

initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time without
disturbing their value or count mode.
The clock source for TI is user-definable and
can be the internal microprocessor clock
(4 MHz maximum for the 8 MHz device and 6
MHz maximum for the 12 MHz device.) divided by four, or an external signal input via Port
3. The Timer Mode register configures the external timer input as an external clock (I MHz
maximum), a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. The counter/timers
can be programmably cascaded by connecting
the To output to the input of TI. Port 3 line P36
also serves as a timer output (TOUT) through
which To, TI or the internal clock can be output.

9

1/0 Ports

The 28601 has 32 lines dedicated to input
and output. These lines are grouped into four
ports of eight lines each and are configurable
as input, output or address/data. Under software control, the ports can be programmed to

provide address outputs, timing, status signals,
serial 1/0, and parallel 1/0 with or without
handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.

Port 1 can be programmed as a byte I/O
port or as an addressldata port for interfacing
external memory. When used as an 1/0 port,
Port I may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDY]
and DAV] (Ready and Data Available).
Memory locations greater than 2048 are
referenced through Port I. To interface external memory, Port I must be programmed
for the multiplexed Address/Data mode. If
more than 256 external locations are required,
Port must output the additional lines.
Port I can be placed in the high-impedance
state along with Port 0, AS, DS and R/W, allow-

ing the 2860 I to share common resources in
multiprocessor and DMA applications. Data
transfers can be controlled by assigning P33
as a Bus Acknowledge input and P34 as a Bus
Request output.

Port 0 can be programmed as a nibble 1/0
port, or as an address port for interfacing
external memory. When used as an 1/0 port,
Port may be placed under handshake control. In this configuration, Port 3 lines P32 and
P35 are used as the handshake controls DA Vo
and RDYo. Handshake signal assignment is
dictated by the 1/0 direction of the upper
nibble P04-P07.
For external memory references, Port can
provide address bits As-All (lower nibble) or
As-A]5 (lower and upper nibble) depending
on the required address space. If the address
range requires 12 bits or less, the upper nibble
of Port can be programmed independently as

1/0 while the lower nibble is used for addressing. When Port nibbles are defined as
address bits, they can be set to the highimpedance state along with Port I and the control signals AS, DS and R/W.

PORT 1:(110)

°

°

} 1M~:~~~~~~NTROLS
(P31 AND P3s)

Figure 9a. Pori 1

°

°

°

Port 2 bits can be programmed independently as input or output. The port is
always available for 1/0 operations. In addition, Port 2 can be configured to provide
open-drain outputs.
Like Ports and I, Port 2 may also be
placed under handshake control. In this configuration, Port 3 lines P3] and P36 are used as
the handshake controls lines DA V2 and RDY2.
The handshake signal assignment for Port 3
lines P3] and P36 is dictated by the direction
(input or output) assigned to bit 7 of Port 2.

_

} ~:=~KRED~~NTROLS
(P~AND

P3s)

Figure 9b. Port 0

PORT 1

(1/0 OR ADO-AD J)

°

Port 3 lines can be configured as 1/0 or control lines. In either case, the direction of the
eight lines is fixed as four input (P30-P33) and
four output (P34-P37)' For serial 1/0, lines P30
and P37 are programmed as serial in and serial
out respectively.
Port 3 can also provide the following control
functions: handshake for Ports 0, I and 2
(DAV and RDY); four external interrupt
request signals (IRQo-IRQ3); timer input and
output signals (TIN and TOUT) and Data
Memory Select (DM).

10

Figure 9c. Pori 2

PORTa
(110 OR CONTROL)

Figure 9d. Pori 3

2037·008

Interrupts

The Z8601 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out, and the two counter/
timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or individually enables or disables the six
interrupt requests. When more than one interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the Interrupt Priority register.
All Z8601 interrupts are vectored. When an
interrupt request is granted, an interrupt
machine cycle is entered. This disables all

subsequent interrupts, saves the Program
Counter and status flags, and branches to the
program memory vector location reserved for
that interrupt. This memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
Polled interrupt systems are also supported.
To accommodate a polled structure, any or all
of the interrupt inputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service.

Clock

The on-chIp oscIllator has a high-gain,
parallel-resonant amplifier for connechon to a
crystal or to any suitable external clock source
(XTALJ = Input, XTAL2 = Output).
The crystal source is connected across
XTALJ and XTAL2, using the recommended
capaCItors (Cl ::S 15 pF) from each pin to

ground. The speCifications for the crystal are
as follows:
• AT cut, parallel resonant
• Fundamental type, 8/12 MHz maximum
• Series resistance, Rs ::S 100 n

i...w

Ia

11

Z8603
Protopack
Emulator

The Z8603 MPE (Protopack) is used for
prototype development and preproduction of
mask-programmed applications. The Protopack
is a ROMless version of the standard Z860 I,
housed in a pin-compatible 40-pin package
(Figure II).
To provide pin compatibility and interchangeability with the standard maskprogrammed device, the Protopack carries
(piggy-backs) a 24-pin socket for a direct
interface to program memory (Figure I). The
24-pin socket is equipped with II ROM
address lines, 8 ROM data lines and necessary

control lines for interface to 2716 EPROM for
the first 2K bytes of program memory.
Pin compatibility allows the user to design
the pc board for a final 40-pin maskprogrammed Z8601, and, at the same time,
allows the use of the Protopack to build the
prototype and pilot production units. When the
final program is established, the user can then
switch over to the 40-pin mask-programmed
Z8601 for large volume production. The Protopack is also useful in small volume applications where masked ROM setup time, mask
charges, etc., are prohibitive and program
flexibility is desired.
Compared to the conventional EPROM
versions of the single-chip microcomputers,
the Protopack approach offers two main
advantages:
• Ease of developing various programs during
the prototyping stage. For instance, in
applications where the same hardware
configuration is used with more than one
program, the Z8603 Protopack allows
economical program storage in separate
EPROMs (or PROMs), whereas the use of
separate EPROM-based single-chip
microcomputers is more costly .

Figure 11. The Z8603 Microcomputer Protopack Emulator

Instruction
Set

Notation

Addressing Modes. The following notation is used
to describe the addressing modes and instruction
operations as shown in the instruction summary.
IRR

Indirect register paIr or mdirect working-register

Irr
X

1M

Indirect working· register pair only
Indexed address
Direct address
Relative address
Immediate

R

Register or working-register address

pair address

DA
RA

Working-regIster address only

Assignment of a value is indicated by the symbol
"_". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to blt 7 of the destmatlOn operand.

Flags. Control Register R252 contains the folloWing
six flags:

Indirect-register or mdired workmg-register

C

address

describing the instruction set.

Z
S
V
D
H

dst
src
cc

0

IR

Ir

Indirect workmg-regIster address only

RR

RegIster pair or working regIster pair address

Symbols. The following symbols are used in
Deshnahon locatIon or contents
Source location or contents

SP

Condlhon code (see bstj
Indirect address prefIx
Stack painter (control registers 254-255)

PC

Program counter

@

FLAGS Flag regIster (control register 252)
RP
Register pointer (control register 253)

IMR

12

• Elimination of long lead time in procuring
EPROM-based microcomputers.

Carry flag
Zero flag
SIgn nag
Overflow flag
Decimal-adjust flag
Half-carry flag
Affected flags are indicated by:

..
X

Cleared to zero
Set to one
Set or cleared according to operahon

Unaffected
Undefined

Interrupt mask regIster (control register 251)

2037·012

Condition
Codes

Value

Flags Set

Meaning

Mnemonic

1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000

Always true
Carry
No carry
Zero
Not zero
Plus
Mmus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
UnsIgned greater than or equal
UnsIgned less than
UnsIgned greater than
UnsIgned less than or equal
Never true

C
NC
Z

NZ
PL

Ml
OV
NOV

EQ

NE
GE

LT
GT

LE
UGE

ULT
UGT

ULE

Instruction
Formats

OPC

C
C ;

a

Z ; I
Z
S
S
V
V

; a
; a
; 1
; I
; a

Z ; I
Z ;

a

a

(S XOR V) ;
(S XOR V) ; 1
[Z OR (S XOR V)[
[Z OR (S XOR V)[

C ;

a

a
I

C; 1

a

(C ;
AND Z ; 0)
(C OR Z) ; I

I-...

CCF, 01, EI, IRET, NOP,
ReF, RET, SCF

da!

OPC

INC r

w

I

One-Byte Instructions

OPC
MODE
dst/arc

OR

I

OPC

.at

OR

hi 1 01 dstlare 1
11

1 1

01

.ot

ADC, ADD, AND, CP,

ClA, CPL, OA, DEC,
CECW, INC, INOW, POP,
PUSH, Rio, ALe, RR,
RRC, SRA, SWAP

LD, OR, SBC, SUB,
TeM, TM, XOR

JP, CALL (Indirect)

OPC

ope

ADe, ADD, AND, CP,

MODE
dst

OR 11 1 1 01

<1st

VALUE

SRP

LD, OR, sac, SUB,
TCM, TM, XOR

VALUE

ope

.at

ope

MODE
d,tl,re

LD, LOE, LDEI,
LDC, LDCI

,reldel

ope
del/ere
areldSI

.ot

ADC, ADD, AND,
CP, OR, SSC. SUB,
TCM, TM, XOR

MODE

MODE
dstlarc

OPC

LO
OR

1 1 1 0

OR 1 1 1 0

dsl
LD

ADDRESS

OR 11 1 1

01

LD

ope

JP

DA,

I

ope

LD

VALUE

I

MODE
ope
I-::::j~=j
L
dst

dsIICCR~ OPC

DPC

CALL

OJNZ, JR

Two-Byte Instructions

Three-Byte Instructions
Figure 12. Instruction Formats

2037-013

13

Instruction
Summary

Instruction
and Operation

AddrMode

ADC dst,sre
dst-dst+sre+C

(Note I)

ADD dst,sre
dst - dst + sre

(Note I)

AND dst,sre
dst - dst AND sre

dst

src

Opcode Flags Affected
Byte
(Hex)
CZSVDH

o•

10

• 0 •

00

• 0

CALL dst
DA
SP-SP-2
IRR
@SP - PC; PC - dst

D6
D4

------

CCF
C - NOT C

EF

*-----

(Note I)

R
IR

BO
BI

COM dst
dst - NOT dst

R
IR

60
61

CP dst,sre
dst - sre

(Note I)

AD

DA dst
dst - DA ds!

R
IR

40
41

• X

DEC dst
dst-dst-I

R
IR

00
01

DECW dst
dst-dst-I

RR
IR

DJNZ r,dst
RA
r - r- I
If r ,. 0
PC-PC+dst
Range: + 127, -128

Irr

82
92

------

LDEI dst,sre
Ir
Irr
dst - src
+ 1; rr-rr+l

Irr
Ir

83
93

------

r - r

FF

------

OR dst,sre
dst - dst OR sre

(Note I)

40

- * * 0

POP dst
dst - @SP
SP-SP+I

R
IR

50
51

------

PUSH Bre
SP-SP-I; @SP- Bre

0-----

RET
PC - @ SP; SP - SP + 2

AF

------

RL dst

R
IR

90
91

-***--

RLCdst~l~

10
II

80
81

-***--

RR dst

lc3-J I~

EO
EI

LEl=cil
R
' , • IR

CO
CI

SF

-----------

9F

R
IR

rE
r;O-F
20
21

RR
IR

AO
Al

DA
IRR

JR ee,dst
If CC IS true,
PC-PC+dst
Range: + 127, -128
LD dst,sre
dst - sre

RA

r
R

LDC dst,sre
dst - src

+

1m
R

0LDJ
4:iJ

SBC dst,sre
dst - dst- sre- C

(Note I)

SCF
C-I

------

* * *- -

4:iJ~I~

SRP Bre
RP - sre

1m
(Note I)

SUB dst,sre
dst - dst - sre

SWAPdst ~ R
IR

IRET
BF
FLAGS - @SP; SP - SP + I
PC - @SP; SP - SP + 2; IMR (7) - I
JP ee,dst
tf co IS true
PC - dst

70
71
CF

- * * 0

SRA dst

INC dst
dst-dst+1

R
IR

RCF
C-O

rA
r;O-F

EI
IMR (7) - I

14

r
lrr

LDE dst,sre

RRC dst

DI
IMR (7) - 0

Opcode Flags Affected
Byte
(Hex)
CZSVDH

src

NOP

CLR dst
dst - 0

INCW dst
dst - dst +

AddrMode
dst

clst - src

50

LDCI dst,sre
dst - arc
r - r + 1; rr - rr

Instruction
and Operation

C3
D3

------

I

FO
FI

X •• X

.

• 0

(Note I)

BO

• 0 - -

------

Irr
Ir

20

70

rC
r8
r9
r;O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5

Ir
Irr
1

31

(Note I)

Note 1

------

* * *0

TM dst, sre
dst AND sre

------

C2
D2

DO
DI

- •• 0

eB
e;O-F

Irr

I - - -

60

XOR dst,sre
dst - dst XOR sre

r
Irr

DF

.

(Note I)

------

X
r
Ir
r
R
IR
1m
1m
R

• • I

TCM dst,sre
(NOT dst) AND sre

eD
e;O-F
30

r
X
r
Ir
R
R
R
IR
lR

3D

These mstruchons have an lclentlcaJ set of addressing
modes, which are encoded for brevity The hrst opcode
mbble IS found 10 the mstruchon set table above The
second mbble IS expressed symbohcally by a 0 III this
table, and Its value IS found In the following table to the
left of the apphcable addressmg mode pair
For example, to determine the opcode of an ADC
Instruction use the addressmg modes r (desbnahon) and
Ir (source) The result lS 13.

Addr Mode
dst

src

R
R
R
IR

Ir
R
IR
1M
1M

Lower
Opcode Nibble

rn
rn
[i]

lID
[ID

III
8085-003

Registers

R240 810
Serial I/O Register
(FOH: ReadIWrite)

8244 TO
Counter/Timer 0 Register
(F~: ReadlWrite)

I~I~I~I~I~I~I~I~I
11...----SERIAL DATA

(~ •

Las)

To INITIAL VALUE (WHEN WAlnEN)
'----(RANOE: HHI DECIMAL Ot-oo HEX)
To CURRENT VALUE (WHEN READ)

8241 TMR
Timer Mode Register
(FIH: ReadlWrite)

8245 PREO
Preac:a1er 0 Register
(F5H: Write Only)

llli~o

~L

j

~

NOT T..,
USEDMODES
.. 00

: ~:
INTERNAL CLOC~ OUT .. 11
~o g~~

T MODES

FUNCTION
1 •.. NO
lOAD
To

0 .. DISABLE To COUNT
1 = ENABLE To COUNT

GATE INPUT "" 01
10

(NON.A~~=::::~::~~ ..

I-...

1 ... To MODULO-N

RESERVED

0 .. NO FUNCTION
t = LOAD T,
0 ... DISABLET,COUNT
1 = ENABLE T1 COUNT

EXTERNAL CLOCK IN~DT ... 00

COUNTMODE
o = To SINGLE·PASS

w

I

PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

TRIGGER INPUT = 11
(RETRIGGERABLE)

8242 Tl
Counter Timer 1 Register
(F2H: ReadlWrite)

820P2M
Port 2 Mode Register
(F~: Write Only)

R243 PREI
Preac:aler 1 Register
(F3H: Write Only)

R247 P3M
Port 3 Mode Register
(F7H: Write Only)

~L

COUNTMODE
o .. T, SINGLE.PASS
1 .. T, MODULO·N

CLOCK SOURCE

1 = T, INTERNAL

o = T1 EXTERNAL TIMING INPUT
(TIW MODe

[SE

LOPORT2PULL.UPSOPEN DRAIN
1 PORT 2 PULL-UPS ACTIVE

RESERVED

o P32 ;;;

o 0 P33 = INPUT
~~}P33=INPUT

PRESCALER MODULO
(RANGE 1-64 DECIMAL
01-00 HEX)

=

INPUT
P35
OUTPUT
1 P32 = alVti#RDYO P36 = ADYOIIDVO

t 1 P33

= DAVi/RDY1

~ :~~ ~ ~to~

PM

= OUTPUT

P34=DM
P34 = RDY1/DAV'i

:: ~ ~~:'~UT)

'-------~~: ~ ~~R~lLIN ::~ ~ ~~r.~TOUT

'-________

~ :~:~ g~F

Figure 19. Control Register.
2037·014

15

Registers
(Continued)

RWPOIM
Port 0 and I Mode Regiater

Flag Register

(FBti; Write Only)

(FCH; Reacl/Write)

R252FLAGS

I~I~I~I~I~I~I~I~I
...-POrUODE:]
OUTPUT.
00 ~
INPUT. 01

~-r
L

A,...A1& .. 1X

1X ""

EXTERNAL MEMORY TIMING
NORMAL .. 0

U~~
I

LUSER FLAG F1
LUSEA FLAG F2

Po,-Po,MODE
00 "" OUTPUT
01 .. INPUT
Ae~A11

STACK SELECTION
0 .. EXTERNAL

EXTENDED"" 1

1 • INTERNAL

HALF CARRY FLAG

DECIMAL ADJUST FLAG
OVERFLOW FLAG
810N FLAG

P1,'!' :'::EOUTPUT

ZERO FLAG

01 "" BVTE INPUT
10 .. ADrAD,

CARRY FLAG

11 .. HIGH·IMPEDANCE ADo-ADJ.

is, iii. MY. Aa-A11. AUi-AUi
IF SELECTED

R2t91PR
IDterrupt Priority Reglater

R2S3 RP
Reglater Pointer

(F9t!; Write Only)

(FDH; Reacl/Wrlte)

IIIII~"'-~

I~I~I~I~I~I~I~I~I

_:J

IRQS, IRa5 PRIORITY (GROUP A)
o = 1RQ6>1RQ3
1 = IRQ8 > IRQS

RESERVED = 000
C > A > B = 001
A>8>C",,010
A > C > 8 = 011

REGISTER

POINTER

g~ : ~ ~=
B > A > C = 110

~~

IROD, 1RQ2 PRIORITY (GROUP 8)
o "" IAOJ > IROO
1 = IROO > IRQ2

RESERVED = 111

IRQt, 1RQ4 PAtoRITY (GROUP C)
o = IRQ1 > IRQ4
1 = IRQ4 > IAQ1

R2S0 IRQ
Interrupt Request Regiater

R2St SPH
Stack Pointer

(FAH; Reacl/Write)

(FEH; Reacl/Write)

I~I~I~I~I~I
RESERVED

.. I~I~I

c=

~

IROO • PI2INPUT (Do • IROO)
IR01

= Pia INPUT

IRQ2 • PI1INPUT

IRQ3 ." P30 INPUT, SERIAL INPUT

IRQ4 • To. SERIAL OUTPUT

lAOS = T1

R2S11MR
IDterrupt Mask Register

R2S5 SPL
Stack Pointer

(F~; Reacl/Write)

(FFH; Reacl/Write)

Il___

C=
___ ''Do = IROO) IRoo-IRQ5
ENABLES

RESERVED

' - - - - - - - - 1 ENABLES INTERRUPTS

Figure 13. Control Registers (Contmued)

16

2037-014

Z8601
Opcode
Map

Lower Nibble (Hex)

o
o

6,5

6,5

,
s

i

8

!5

~

7

J

8

9

A
B

F

Bytes per
IDatructlon

8

9

A

B

C

6,5

6,5

10,5

10,5

10,5

10,5

6,5

6,5

12/10,5

12/10,0

6,5

12/10,0

6,5

LD

LD

DINZ

JR

LD

JP

INC

n,Ra

I2,Rl

(l,RA

ce,RA

rl, IM

cc,DA

n

n,ta
6,5

n,lta
6,5

B.,B,
10,5

IR.,B,
10,5

B"IM
10,5

IR"IM
10,5

RLe

RLC

ADC

ADC

ADC

ADC

ADC

6,5

n,ta
6,5

fl,lu
6,5

Bz,Rl

6,5

10,5

IR.,B,
10,5

ADC
B"IM
10,5

IB"IM
10,5

INC

INC

SUB

SUB

SUB

SUB

6,1

6,5

1l,112
6,5

IR.,B,
10,5

SUB

8,0

B.,B,
10,5

SUB

B"IM
10,5

IR"IM
10,5

JP

SRP

SBC

SIC

SBC

SIC

SBC

SIC

IRK,
8,5

IR,

n,ta

IB,

rl,I2

11, III

6,5

6,5

Rz,Rl
10,5

IRa, HI

8,5

10,5

B"IM
10,5

IR"IM
10,5

DA

OR

OR

OR

OR

OR

OR

1M

DA
B,

IR,

11, l2

Il,lr2

10,5
pop
B,

10,5

6,5

6,5

B.,B,
10,5

IR.,B,
10,5

B"IM
10,5

IR"IM
10,5

POP

AND

AND

AND

AND

AND

AND

11,r2

n,lra

Ba,Rl

6,5

6,5

6,5

6,5

10,5

IB.,B,
10,5

B"IM
10,5

IR"IM
10,5

TCM

TCM

TCM

TCM

B.,B,
10,5

IB.,B,
10,5
TN
IR.,B,

TeN

TCM

B"IM
10,5

IR"IM
10,5

IR,

COM COM
B,

IR,

11,(2

lllbz

10/12,1 12/14,1

6,5

6,5

PUSH PUSH

TN
n,ta

TN

TM

(1,112

Bz,Rl

12,0

18,0

IR.
10,5

DECW DECW LDE
BB,
6,5

IR,
6,5

RL

RL

B,
10,5

IR,
10,5

BB,
6,5

IB,
6,5
CLR
IR,

CLR
RRC
SRA

TM

TM

B"IM

IR"IM

Irl,bra

12,0

18,0

LDE

LDBI

6,5

6,5

RRC

CP

CP
n,lr2

I--I--I---

-

IR,
6,5

10,5

10,5

10,5

CP

CP

CP

IRa,Rl

IR"IM
10,5

CP

6,5

6,5

10,5

XOR

XOR

XOR

XOR

XOR

XOR

Il,lI

11, Ira

Rz,Rl

IR.,B,

B"IM

IRl,1M

12,0

18,0
LDCI
20,0

20,0

10,5

CALL

LD

DA

12, s, 81

10,5

10,5

10,5

B,

IR,

LD

LD

LD

LD

LD

B.,B,

IRZ,Rl

B"IM

IR"IM

8,5

8,5

n,lra
6,5

LD

IR,

In,ra

EI
14,0

- 16,0
-

IRET
6,5

LD

6,5

SWAP SWAP

DI

RET

RCF

11,:11:, H2

LDeI CALL·
,Irn

-

10,5

bra III,lua

18,0

I

-

10,5

I--6,5

SCF

I--6,5

CCF
I---

10,5

6,0

LD

NOP

B.,IR,

~,------,~~------~' ~,------~~,------~# ~,--------~~~----------,;~
a

2

2

a

Lower

0pc0cIe
Nibble

+ P1peliDe
CycIn~CycIu

ExeeutiOD

Upper

0pc0cIe _
Nibble

A

10,5

CP
B., R,

MDemoDlc

LegeDd:
R = 8·Blt Address
r = 4·BII Address
Rl or" = Dot Address
R, or l'2 = Src Address

SequeDCeI

Flnl
Opercmcl

Seccmcl
OperaDd

Opcode, First Operand, Second Operllnd
Note: The blank areas are not defined.

·2-byte mstruchon; fetch cycle appears as a 3-byte mstrucbon
8085·002

I...

Ii

-

6,1

RR

B,

I---

-

B"IM
10,5

12,0
LDC
ta,lrn

I---

6,1

B.,B,
10,5

11,

SRA

6,5

Il,ra

LDC

IR,
6,5

F

E

LDBI

fl,Irl2

IBB,
10,5

RR

D

ta,lrtl Iu,lrn

mcw mcw

B,
6,5

E

7

IB,

B,
6,5

D

6

6,5

B,
6,5

C

s

B,

B.
10,5

II:

,

6,5

B,

a

a

DEC DEC ADD ADD ADD ADD ADD ADD
B,

2

2

17

Absolute
Maximum
Ratings

Voltages on all pins
with respect to GND .......... -0.3 V to +7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to +150°C

Standard
Test
Conditions

The DC characteristics hsted below apply for
the folloWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin.
Standard conditions are:

Stresses greater than those hsted under Absolute Maximum Ratings may cause permanent damage to the devIce.

ThIS IS a stress rahng only; operahon of the device at any
condlbon above those mdlCated m the operabonal sections
of these speClhcabons IS not Imphed. Exposure to absolute
maximum ratmg conditions for extended periods may affect
devlCe rehablhty.

The Ordering Information section lists temperature ranges and product numbers. Package
drawings are in the Package Information section
in this book. Refer to the Literature List for additional documentation.

o +4.75 V S Vee S +5.25 V
o GND = OV

o O°C

S

TA

S

.sv

.&V

+70°C
Uk

.sv

.6V

Uk

74....

74""

CLf:fK --[)<>~i--"""'I><>-+-~ XTAU

I

18K

CL = , ••,MAX

r

L -_ _ _~

XTAL'

CL =

Figure 14. Test Load 1

Figure 15. Test Load 2

'6.,MAX

Figure 18. TTL External Clock IDtertac. ClrcuII
(Both the clock and Its complement ore required)

DC
Characteristics

18

Parameter

Min

Max

Unit

VeH

Clock Input High Voltage

3.8

Vee

V

Driven by External Clock Generator

VeL

Clock Input Low Voltage

-0.3

0.8

V

Driven by External Clock Generator

VIH

Input High Voltage

2.0

Vee

V

VIL

Input Low Voltage

-0.3

0.8

V

VRH

Reset Input High Voltage

3.8

Vee

V

VRL

Reset Input Low Voltage

-0.3

0.8

V

VOH

Output High Voltage

VOL

Output Low Voltage

IlL

Input Leakage

IoL

Output Leakage

IIR
Ice

Symbol

V

2.4

Condition

IoH = -250 pA

0.4

V

IoL = +2.0 rnA

-10

10

pA

-10

10

pA

o Vs
o Vs

Reset Input Current

-50

pA

Vee = +5.25 V, VRL = 0 V

Vee Supply Current

180

rnA

VIN s +5.25 V
VIN s +5.25 V

8085-0313, 0312

External I/O
or Memory
Read and
Write Timing

PORT 0,

iiM

PORT 1

iii

______~--~----~_i1~~------~0~------~~1~----r_---

(READ)

Do-Dr OUT

POAT 1

iii ------------------~~---i1~~----~0~----~~1~~-------­
(WRITE)

II
!...

Figure 17. External I/O or Memory Read/Write

Z8601/3-12

Z8601/3-8

Symbol

Parameter

1

TdA(AS)

Address Val!d to AS t Delay

50

35

2,3

2

TdAS(A)
TdAS(DR)

AS t to Address Float Delay

70

45

TwAS

AS Low Width

2,3
1,2,3
1,2,3

5

TdAz(DS)

Address Float to DS I

0

0

6-

TwDSR ------ DS (Read) Low WIdth

250

185

1,2,3

7
8

TwDSW
TdDSR(DR)

DS (WrIte) Low WIdth
DS I to Read Data ReqUIred ValId

160

110

1,2,3

9

ThDR(DS)

Read Data to DS t Hold TIme

10

TdDS(A)

11

TdDS(AS)

12 -

TdR/W(AS) - - - R/W ValId to

13

TdDS(R/W)

DS t to R/W Not Val!d

14

TdDW(DSW)

15

No.

3
4

Min

AS t to Read Data ReqUIred Val!d

Max

Min

360

Max

Notes"tO

220

80

55

130

200

DS t to Address Active Delay

45

2,3

DS t to AS I Delay

70

55

2,3

50

2,3

60

30
35

WrIte Data ValId to DS (WrIte) I Delay

50

35

2,3

TdDS(DW)

DS t to WrIte Data Not Val!d Delay

70

45

16

TdA(DR)

Address Val!d to Read Data ReqUIred Val!d

17

TdAS(DS)

AS

AS

t to DS I Delay

NOTES
1 When uSing extended memory bming add 2 TpC
2. Tlmmg numbers given are for minimum TpC
3 See clock cycle hme dependent charactenshcs table

2194-011

t Delay

0

410

2,3
2,3
255

80

55

1,2,3
2,3

t Test Load 1
o

W

CI

1,2,3

0
70

-iii

All bmmg references use 2 a v for a loglC 1" and 0 8 V for a loglC "0"
In nanoseconds (ns)
\I

* All umts

19

Additional
Timing
Table

Figure 18. Additional TIming

ZB6DI/3·B
No.

2

Symbol

Min

Max

Min

Max

TpC

Input Clock Period

125

1000

83

1000

TrC,TlC

Clock Input Rise And Fall Times

25

3

TwC
Input Clock Width
37
Timer Input Low Width
TwTinL
4
100
5 - TwTmH ---Timer Input High Width - - - - - - - - - - 3TpC

6

TpTin
TrTm,TITm

Timer Input PerlOd

7
8a

TwIL

Interrupt Request Input Low Time

8b

TwIL
TwIH

Interrupt Request Input Low Time
Interrupt Request Input High Time

9

ZB6DI/3·12

Parameter

Memory Port

70
2
3TpC - - - - - - 2

8TpC

8TpC

2

100
100
3TpC
3TpC

2
2,3

100
70
3TpC

2,4
2,3

3TpC

Interrupt request via Port 3 (P31-P33)
4. Interrupt request via Port 3 (P30)
.. Umts In nanoseconds (ns)

1 Clock hmmg references uses 3 8 V for a logic "I" and 0 8 V for
a logiC "0"
2 Tlmmg reference uses 2 0 V for a logic" 1" and 0.8 V for
a loglC "0"

Z86D3

15
26

Timer Input Rise And Fall Times

NOTES'

Not..*

A.·A,. ~__________________~A_D_D._E_SS_V_A_Ll_D__________________~t(

Timing
Do-D7

---______~T-.________0__' ____~j~--------------------------~~~--2~V-X
-------f\.DON'T CAllE

DATA IN VALID

Figure 19. Memory Port Timing

ZB6DI/3·B
No.
2

Symbol

Parameter

TdA(DI)

Address Vahd to Data Input Delay

ThDI(A)

Data In Hold Time

NOTES:
1. Test Load 2

Min

Max

ZB6DI/3·12
Min

460

a

Max

320

a

Notes*

1,2

I

'" Umts are nanoseconds unless otherwise specIfIed.

IS a Clock-eycle-Dependent parameter. For clock frequenother than the maXimum, USB the follOWing formula:
28601/3 = 5 TpC - 165
Z8601/3-12 = 5 TpC - 95

2. ThiS
OlBS

20

2194-012 2037-019

Handshake
Timing

OA~;'~:

~~:::;:"":
~

_________________

___________

ROY
(OUTPUT)

Figure 20a. Input Handshake

DATA OUT

DAII
ROY

(OUTPUT)
(INPUT)

r-

~ATA OUT VALID
------~~--------------------------------

5=

1 CD C'17~
---------------J===~===fL==

•

Figure 20b. Output Handshake

Z8601/3-8

No.

Symbol

Parameter

Min

TsDI(DAV)
Data In Setup Time
0
2
ThDI(DAV)
Data In Hold TIme
230
3
TwDAV
Data Avallable Width
175
4
TdDAVJf(RDY) DAV I Input to RDY I Delay
5-TdDAVOf(RDY)-DAV I OutputtoRDY I D e l a y - - - - - - - - - 0
6
7
8
9

TdDAVIr(RDY)
TdDAVOrRDY)
TdDO(DAV)
TdRDY(DAV)

DAV 1 Input to RDY 1 Delay
DAV 1 Output to RDY 1 Delay
Data Out to DAV I Delay
Rdy I Input to DAV I Delay

NOTES,
1. Test load I
2. Input handshake
3. Output handshake
t All hmmg references use 2 0 V for a logic" 1" and 0 8 V for

Max

Z8601/3·12

Min

Max

175

120
0

200

120
0
30
0

1,2
1,3
1,2
1,3

140

* UOits m nanoseconds (os),

a logiC "0"

ClockNumber
Cycle-TimeDependent
Characteristics
2
3
4
6
7
8
10
11
12
13
14
15
16
17
*

2194·013

Z8601/3-8

Z8601l3·12

Symbol

Equation

Equation

TdA(AS)
TdAS(A)

TpC-75
TpC-55
4TpC-140'
TpC-45
3TpC-125'
2TpC-90'
3TpC-175'

TpC-50
TpC-40
4TpC-llO'
TpC-30
3TpC-65,

TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
Td(DS)A
TdDS(AS)
TdR/W(AS)
TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)

TpC-55
TpC-55
TpC-75
TpC-65
TpC-75
TpC-55
5TpC-215'
TpC-45

I
W

0
160
120

175
0
50
0

Notes ..t

II
I:
...

2TpC-55'
3TpC-120'
TpC-40
TpC-30
TpC-55
TpC-50
TpC-50
TpC-40
5TpC-160'
TpC-30

Add 2TpC when usmg extended memory hmmg

21

ORDERING INFORMATION
ZS MCU, 2K ROM, S.O MHz
40-pin DIP
44-pin PCC

ZS MCU, 2K XROM, S.O MHz
40-pin Protopack

Z8601
Z8601
Z8601
Z8601

Z8603 RS
Z8603 TSt

PS
CS
PE
CE

Z8601 VSt

ZS MCU, 2K XROM, 12.0 MHz
40-pin Proto pack

ZS MCU, 2K ROM, 12.0 MHz
40-pin DIP
44-pin PCC
Z8601-12 PS
Z8601-12CS

Z8603-12 RS
Z8603-12 TSt

Z8601-12 VSt

Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = OOC to + 70°C
E = -40°Cto +85°C
M*= -55°C to +125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DIP, OOC to + 70°C.
tAvaliable soon.
* For Military Orders, contact your local Zilog Sales Office for Military Electrical SpeCifications.

22

00·2037-04

Z8® Z8611
Z8® Z8612
Z8® Z8613

Product
Specification

Zilog

March 1985
28611 Single-Chip Microcomputer wIth 4K ROM
28612 Development Device with Memory Interface
28613 Prototyping Device with EPROM Interface

Features

• Complete microcomputer, 4K bytes of ROM,
128 bytes of RAM, 32 I/O Imes, and up to
60K bytes addressable external space each
for program and data memory.

• Full-duplex UART and two programmable
8-bit counter/hmers, each wIth a 6-blt
programmable prescaler.

I......

-

...
...w

• Register Pomter so that short, fast mstruchons can access any of nme workmgregIster groups in I J1-S.

• 144-byte register hie, mcludmg 124
general-purpose registers, four I/O port
registers, and 16 status and control
regIsters.

• On-chIp osclllator whlCh accepts crystal or
external clock dnve.

• Average instruction execution hme of
1.5 J1-s, maximum of 3 J1-S.

• Smgle + 5 V power supply-all pms TTLcompahble.

~

I

• Vectored, priority mterrupts for I/O,
counter/hmers, and UART.

General
Description

The Z8611 microcomputer introduces a new
level of sophistication to single-chip architecture. Compared to earlier Single-chip microcomputers, the Z8611 offers faster execution;
more efficient use of memory; more sophisticated interrupt, input/output and bit-manipulation capabilities; and easier system expansion.
Under program control, the Z8611 can be
tailored to the needs of its user. It can be con-

figured as a stand-alone microcomputer with
4K bytes of internal ROM, a traditional microprocessor that manages up to 120K bytes of
external memory, or a parallel-processing element in a system with other processors and
peripheral controllers linked by the Z-BUS. In
all configurations, a large number of pins
remain available for I/O.

+5V

P3,

XTAL1

P2,

P3,

P2,

P3.

P2,

RESET

P2,

PORTO

RIW

P2,

(NIBBLE
PROGRAMMABLE)

ilS
AS

P2,

IIQO"'tA8-A,s

p'.

DND

P3,

po.
po,
po,
po,
po,
po,
po,
po,

PORT 1

(BYTE

PROGRAMMABl.E)
1/0 OR ADc-AD7

Figure 1_ Pin Functions

P2,

P3,
P3,

2038·001.002

P3,

XTAL2

P3,
P1,
P1,
P1,
P1,
P1,
P1,
P1,
P1.

Figure 2a_ 40-pin Dual-In-Line Package (DIP)
Pin Assignments

23

Pin
Description

for va or external memory interface.
RESET. Reset (mput, active Low). RESET imtializes the Z8611. When RESET is deactivated,
program execution begms from internal program location OOOCH.

AS. Address Strobe (output, achve Low).
Address Strobe is pulsed once at the begmning of each machine cycle. Addresses output
via Port I for all external program or data
memory transfers are valid at th~ailing edge
of AS. Under program control, AS can be
placed in the high-impedance state along wJth
Ports 0 and I, Data Strobe, and ReadlWrite.

R/W. ReadlWrite (output). R/W is Low when
the 28611 IS wrIting to external program or
data memory.

OS. Data Strobe (output, active Low). Data

XTALI. XTAL2. Crystall, Crystal 2 (time-base

Strobe is achvated once for each external
memory transfer.

input and output). These pins connect a
parallel-resonant crystal (8 or 12 MHz maximum) or an external single-phase clock (8 or
12 MHz maxImum) to the on-chip clock
oscillator and buffer.

POo-Po,. PIO-PI? P2o-P2,. P30-P3,. 110 Port
Lines (input/outputs, TTL-compatible). These
32 lines are divided mto four 8-bit va ports
that can be configured under program control

+" 4""""'-¢'~~~~ 4""'I'lI'-"",~",,~
6

5

4

3

2

1

~

U U

~

U

IIESET 7

39

NC

RIW

8

38

P2.

os

9

37

P2.

36

P2.

35

P2,

A! 10
P3s

11

GND

12

P3.

Z8611

34

P20

13

33

P33

Plio

14

32

P30

PO,

15

31

P17

Po.

16

30

P1.

Ne

17

29

Pt.

MCU

18 19 20 21 22 23 24 25 26 27 28

IR08
1 :; 1RQ3 > IAQ6

i

RESERVED", GOO

C > A > B = 001

A>I>C=010
A > C > B = 011
8>C>A=1oo

REGISTER
POINTER

C > 8 > A = 101
B > A > C = 110
RESERVED = 111

IRODt IRQ2 PRIORITY (GROUP 8)
o = IRQ2 > IROO
1 = IROO > IRQ2

IRQt. IRQ4 PRIORITY (GROUP C)
o = IRQt > IRQ4
1

= IRo. > IRQ1

R250mQ
IDterrupt Request Register
(FAH; Read/Write)

R254SPH
Stack Pointer
(FEH; Read/Write)

I~I~I~I~I~I~I~I~I

I~I~I~I~!~I~I~I~I

RESERVED

c::::

T

IROO • Pia INPUT (Do ... IRoo)
IRQ1 ... Pia INPUT
IAQ2 110 PSt INPUT

=

IAQ3 '30 INPUT, SERIAL INPUT
IRQ4 • To. SERIAL OUTPUT
IROS = T,

R2511MR
Interrupt Mask Register
(FBH; Read/Write)

8255 SPL
Stack Pointer
(FFH; Read/Write)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~!~I~I

II

c::::

1 ENABLES IROO-IRO&
(0, • 'ROO)

LI_ _ _ _

:~~~~S~~:~R

LOWER

'-------RESERVED

' -_ _ _ _ _ _ _ 1 ENABLES INTERRUPTS

ngure la. Control Registe.. (Continued)

34

2037-014

Opcode
Map

Low.. Nibble (Hex)

o
o

6,5

6,5

5

i

8

e

.!l

;3

7

I;

i

8

9

A
B

C

RLC

RLC
lB,

ADC
n,la

ADC
n,lu

6,5

6,5

6,5

INC

INC

SUB

6,5

SUB

Rz,RI

IR.,R,

6,1

rl,ra
6,5

ll,b.

8,0

6,5

JP

SRP

SBC

10,5

SBC

SBC

1M

ll,f2

[l,bz

8,5

8,5

6,5

6,5

DA

DA
lB,

OR

OR

11,la

10,5

10,5

6,5

pop
R,

POP

AND
n,la
6,5

TCM

lB,
6,5

COM

COM

B,

F

10,5

R"IM
10,5

IR"IM
10,5

ADC

ADC

ADC

ADC

R.,R,

lB.,R,

10,5

10,5

R"IM
10,5

lB"lM
10,5

I111M

cc,DA

"

-

R"IM
10,5

IR"IM
10,5

-

n,b,

OR

OR

OR

OR

R.,R,

IR.,R,

6,5

10,5

10,5

R"IM
10,5

lB"lM
10,5

AND

AND

AND

6,5

10,5

lB.,R,
10,5

AND

fl,lu

R.,R,

AND
R"IM
10,5

IB"IM
10,5

TCM

TCM

TeM

TeM

TeM

B"IM
10,5
TN
B"IM

lB"lM
10,5
TN
lB"lM

TM

TM

TM

rl, fa

n,bz

Bz,R1

TN
IRz,R.

12,0

18,0

DECW DECW LDE

LDEI

-

-

RL

12,0

18,0

LDE

LDEI

f---

6,1

EI

I2,lrn lrz,Irrl

6,5

INCW INCW
lB,

6,5

10,5

10,5

10,5

10,5

r--RET

CP

CP

CP

CP

CP

CP

1'1. r2

n,lta

Ra,Hl

IRz,Rl

IB"IM
10,5

6,5

6,5

6,5

6,5

10,5

10,5

B"IM
10,5

CLR

CLR

B,

lB,

XOR

XOR

XOR

XOR

XOR

XOR

11,(2

11,IrZ

Rz,R1

lRa,R.

B"IM

6,5

6,5

12,0

18,0

lB"lM
10,5

RRC

RRC

LDC

LDCI

6,5

6,5

12,0

18,0

SRA

LDC

LDCI CALL*

I2,Irn Ira,lrll

20,0

20,0

lBB,

CALL

LD

DA

la, z, HI

6,5

6,5

10,5

10,5

10,5

10,5

RR
B,

RR

LD

LD

LD

LD

IB,

LD

rl, Ira

Ba,Rl

B"IM

IB"IM

8,5

8,5

6,5

IRa,H.
10,5

LD

LD

IB,

l'l,la

-

IRET
6,5

Ha
10,5

6,5

SWAP SWAP

f--16,0

tl,:I:,

SRA

lB,

14,0

LD

n , trra In,lrl2

lB,

6,1

DI

rl,bra Irl,Irrz

6,5

---

IRz,R.
10,5

PUSH PUSH

BB,

ce,HA

Rz,Rl
10,5

10,5

10,5

rl,RA

-

lB.,B,

10,5

ra,RI

sse sse sse

10,5

IB,

n,BI

IR"IM
10,5

R.,B,

6,5
RL
B,

INC

R"IM
10,5

6,5

lB,

6,5

IP

F

E

10,5

n,lta

BB,

12/10,0

LD

D

SUB

SUB

6,5

lB.
10,5

6,5

IR

C

SUB

SUB

rl,12

B,

Byl.. per
InslructloD

Rz,Rl
10,5

IR.,R,

10/12,1 12/14,1

lB,

12/10,0

DJNZ

10,5

6,5

6,5

12/10,5

LD

10,5

n,Iu

R,

6,5

LD

10,5

6,5

lB,

6,5

8

Il,l2

B,

E

10,5

B

7

6,5

R,

D

6,5

A

8

6,5

B.
10,5

II:

6,5

9

5

lB,

lBR,

..

..

R,

R,

3

3

DEC DEC ADD ADD ADD ADD ADD ADD
R,

:I

2

-

ReF
6,5

-

SCF
6,5
CCF
6,0

NOP

B.,lB,

~~------~~~------,# ~~------~~,------~~ ~~--------~~~--------~#, ~
2

3

2

3

Low..
Opcocle
Nibble
Exec:ulloa

Cyclaa

t

Legead:
R = 8-Bl1 Address
r = 4-Bl1 Address

Upper
Opcocle-A
Nibble
Flnl
Operaad

Maemoalc

Secoad
Operaad

R, or" = Oat Address
R2 or ra = S'c Address

Sequeace:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined_

*2-byte instruction, fetch cycle appears as III 3-byte Instruction
8065-002

35

Absolute
Maximum
Ratings

Voltages on all pins
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to +150°C

Stresses g,....ter than those hsted under Absolute MaxI'
mum Ratmgs may cause permanent damage to the devIce.
Th,s IS a stress rdting only; operallon 01 the device at any
condlilon above those indicated in the operallonal sections
01 these speCIfications is not Imphed. Exposure to absolute
maxImum rating condlilons lor extended periods may affeel
deVICe reliability.

Standard
Test

The DC characteristics listed below apply for
the following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin.
Standard conditions are:

The Ordering Information section lists package
temperature ranges and product numbers. Package drawings are in the Package Information
section in this book. Refer to the Literature List
for additional documentation.

Conditions

o +4.75 V s VCC s +5.25 V
•• v

o GND = OV
o O°C S TA S +70°C·

•• v

Uk

•• v

•• v
CL~CK

Uk

74LS04

74....

--[)c>-'>-H!><,................

I

'8K

I

XTAL2

c,.. "pIMAX

' - - - - -..... XTAL1

Figure 14. Tall Load 1

DC
Character-

Istics

Figura IS. Teat Load 2

Figura 18. TTL External Clock Interface Circuit
(Both the clock and It. complement are required)

Pal'ClllUlter

Min

Max

Unit

VCH

Clock Input High Voltage

3.8

Vcc

V

Driven by External Clock Generator

VCL

Clock Input Low Voltage

-0.3

0.8

V

Driven by External Clock Generator

VIH

Input High Voltage

2.0

Vcc

V

VIL

Input Low Voltage

-0.3

0.8

V

VRH

Reset Input High Voltage

3.8

Vcc

V

VRL

Reset Input Low Voltage

-0.3

0.8

V

VOH

Output High Voltage

VOL.

Output Low Voltage

Symbol

Condition

Note.

= -250 p.A
= +2.0 rnA

V

IoH

0.4

V

IoL

10

p.A

OV:sVIN:S +5.25 V

2.4

CL· 'SplMAX

IlL

Input Leakage

-10

loL

Output Leakage

-10

10

p.A

OV:sVIN:S +5.25 V

IIR

Reset Input Current

-50

p.A

Vcc

Icc

Vcc Supply Current

180

rnA

=

+5.25 V, VRL

=0V

I. For Ao-AlI' MOS, SYNC, SCLK and lACK on the Z8612 verSIOn, IOH = -IOO".A and IOL = 1.0 rnA.

36

8085·0313, 0312 2037·015

External 1/0
or Memory

Read and
Write Timing

PORT O.

IiII

PORT 1

Ai
iii
(READ)

PORT 1

iii

DtrDr OUT

--------------~--~_1,~----_{~----~;~~~----

(WRITE)

I......

Figure 17. Exte.nall/O or Memory ReadlWrlte

No.

Z8611lZ/3-8
Min
Max

Symbol

Parameter

TdA(AS)

Address Valid to AS I Delay

50

TdAS(A)
TdAS(DR)

AS I to Address Float Delay
AS I to Read Data Required Valid

70

TwAS

AS Low Width

80

5

TdAz(DS)

Address Float to DS I

6-

TwDSR - - - - - DS (Read) Low Width
DS (Write) Low Width
TwDSW
TdDSR(DR)
DS I to Read Data Required Valid
ThDR(DS)
Read Data to DS I Hold Time

2
3
4

7
8

9

45
220

0

0
185

160

110

2,3
2,3
1,2,3

1,2,3
130

200

Notea*tO

2,3

55

250

1,2,3
1,2,3

0
70

0
45

2,3

70

55

2,3

R!W Valid to AS I Delay
DS I to R!W Not Valid

50
60

30
35

2,3

Write Data Valid to DS (Write) I Delay

50

35

DS I to Write Data Not Valid Delay

70

45

TdDS(A)

DS I to Address Active Delay

11

TdDS(AS)

DS I to

12 -

TdRIW(AS) TdDS(R/W)

15

TdDW(DSW)
TdDS(DW)

16

TdA(DR)

17

TdAS(DS)

Address Valid to Read Data Required Valid
AS I to DS I Delay

80

AS

I Delay

NarES:
I. When usmg extended memory liming add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. See clock cycle lime dependent characteristics table.

2194-011

35
360

10

13
14

Z8611/Z/3-IZ
Min
Max

410

2,3
2,3
2,3
255

55

1,2,3
2,3

t Test Load 1
o All timing references use 2.0V for a logIC "1" and O.SV for a logiC "0".
• All units in nanoseconds (ns).

37

-......
~

W

I

Additional
Timing
Table

Figure 18. Additional Timing

Z8611/2/S-8
Parameter

Z8611/2/S-l2

No.

Symbol

MID

Max

MiD

Max

Input Clock Period
125
TpC
TrC,TlC
Clock Input Rise And Fall Times
Input Clock Width
37
TwC
TwTmL
100
Timer Input Low Width
TwTmH--- Timer Input High Width - - - - - - - - - - - 3TpC
8TpC
TpTin
Timer Input Period
TrTm,TfTin
Timer Input Rise And Fall Times
TwIL
Interrupt Request Input Low Time
100
TwIL
Interrupt Request Input Low Time
3TpC
Interrupt Request Input High Time
3TpC
TwIH

1000
25

83

2
3
.4
56
7
8a
8b
9

1000
15

100

Not..*

26
1
70
2
3TpC - - - - - 2
8TpC
2
100
2
2,3
70
3TpC
2,4
3TpC
2,3

NOTES:
3. Interrupt request
4. Interrupt request

1 Clock tImmg references uses 3.8 V for a logiC "1" and 0.8 V for
a lOgIC "0".
2. Tlmmg reference uses 2.0 V for a logIC "1" and 0.8 V for
a logiC "0".

Z8612. Z861S
Memory Port
Timing

AO-A,O

.. Umls

~,--_ _ _ _ _
_----J
__

Do-D7

In

VI.
VI.

Port 3 (P31-P33)'
Port 3 (P30)'

nanoseconds (ns).

-'lL,k

-:-AD_D"_ESS_V_AL_'D_ _ _ _ _ _

~j..___0_'r_-_-_-_-~j~.c

X

DON'T CARE

T~

DATA IN VALID

Figure 19. Memory Port nmlng

Z8611/2/S·8
No.

Symbol

Parameter

2

TdA(DI)
ThDI(A)

Address Valid to Data Input Delay
Data In Hold Time

NOTES:
I Test Load 2

2

Min

Max

Z8611/2/S-l2
MiD

1,2

320

460

o

Notes*

Max

o

.. Unds are nanoseconds unless o\herwl8e speclbed.

thiS IS a Clock~Cycle·Dependent parameter. For clock frequenCles other than the maximum, use the follOWing formula:

Z861112/3 = 5 TpC - 165
7.8611/2/3-12 = 5 TpC - 95

38

2194-012 2037-019

Handshake
Timing

DA~;'~: ___________~_'
___~~::::W.:
~ __________
RDY
(OUTPUT)

Fig.... 20a.lnput Handshake

DATA OUT

(OUTPUT)
DB

s=

~.
DATA OUT VALID
-----~--------------------------------

1]~==2==~[==
CD
CI~~

_______________

RDY

~.

(INPUT)

Fig.... 2Ob. Output Handshake

Z8811l2/3-8
No.

Symbol

Parameter

Min

Max

Z8811l2/3-12
Min

Max

Notes*t

TsDI(DAV)
Data In Setup Time
o
0
2
ThDI(DAV)
Data In Hold Time
230
160
17S
120
TwDAV
Data Available Width
3
1,2
4
TdDAVIf(RDY) DAV I Input to RDY I Delay
17S
120
S-TdDAVOf(RDY)-DAV I Output to RDY I Delay - - - - - - - - 0 - - - - - - 0 - - - - - 1 , 3
1,2
6
TdDAVIr(RDY) DAV I Input to RDY I Delay
17S
120
1,3
TdDAVOrRDY) DAV I Output to RDY I Delay
o
0
7
8
TdDO(DAV)
Data Out to DAV I Delay
SO
30
TdRDY(DAV)
Rdy I Input to DAV I Delay
o
200
140
9
0

ClockCycle-TimeDependent
Characteristics

* Umts

In

I

nanoseconds (ns).

Equation

Z8611/2/3-12
Equation

TpC-7S
TpC-SS
4TpC-140'
TpC-4S
3TpC-12S*
2TpC-90*
3TpC-17S*
TpC-55
TpC-SS
TpC-7S
TpC-6S
TpC-7S
TpC-SS
STpC-21S*
TpC-4S

TpC-SO
TpC-40
4TpC-llO*
TpC-30
3TpC-65*
2TpC-SS*
3TpC-120*
TpC-40
TpC-30
TpC-SS
TpC-SO
TpC-50
TpC-40
STpC-160*
TpC-30

Z8811/2/3-8
Number
I
2
3
4
6
7
8
10
II
12
13
14
IS
16
17

Symbol
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR(DR)
Td(DS)A
TdDS(AS)
TdRIW(AS)
TdDS(RIW)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)

* Add 2TpC when using extended memory timing

2194·013

-

...
...w

I!

NOTES:

I. Test load I
2. Input handshake
3. Output handshake
t All tmunq references use 2.0 V for a lOglc "1" and 0.8 V for
.Ioglo "0".

I......

39

ORDERING INFORMATION
ZS MCU, 4K ROM, S.O MHz
40-pln DIP
44-pln PCC
Z8611 PS
Z8611 VSt
Z8611 CS
Z8611 PE
Z8611 CE
Z8611 CM'

ZS MCU, 4K XROM, 12.0 MHz
64-pin DIP
6S-pln PCC
Z8612-12 PS
Z8612-12 VSt
ZS MCU, 4K XROM, S.O MHz
40-pin Protopack
Z8613 RS
Z8613 RE
Z8613 TSt

ZS MCU, 4K ROM, 12.0 MHz
40-pln DIP
44-pin PCC
Z8611-12PS
Z8611-12VSt
Z8611-12CS

Z8 MCU, 4K XROM, 12.0 MHz
40-pln Protopack
Z8613-12 RS
Z8613-12 TSt

ZS MCU, 4K XROM, S.O MHz
. 64-pin DIP
6S-pln PCC
Z8612 PS
Z8612VSt
Z8612 CE
Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = O°Cto + 70°C
E = -40°Cto +85°C
M'= -55°Cto +125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DIP, OOC to + 70°C.
tAvailable soon .
• For MiI~ary Orders. contact your local Zilog Sales Office for Military Electrical Specifications.

40

00-2038·03

Z8® Z8671 MCV

with BASIC/Debug
Interpreter
Product
Specification

Zilog

April 1985

N

FEATURES
• The Z8671 MCU IS a complete microcomputer
preprogrammed with a BASIClDebug interpreter.
Interaction between the interpreter and its user IS
provided through an on-board UART.
• BASIC/Debug can directly address the Z8671's internal
registers and all external memory. It provides quick
examination and modification of any external memory
location or I/O port.

• The BASIC/Debug interpreter can call machine
language subroutines to increase execution speed.
• The Z8671's auto start-up capability allows a program to
be executed on power-up or Reset without operator
intervention .
• Single + 5V power supply-all I/O pins TTL-compatible.
.8MHz

GENERAL DESCRIPTION
The Z8671 Single-Chip Microcomputer (MCU) IS one of a
line of preprogrammed chips-in this case with a
BASIClDebug interpreter in ROM-offered by Zilog. As a
member of the Z8 Family of microcomputers, it offers the
same abundance of resources as the other Z8
microcomputers.
RESET

+5V
GND

R/W

PORTO

(NIBBLE
PROGRAMMABLE)
I/O or As-A15

os

XTAL1

AS

XTAL2

PO,

P2,

po,
po,

P2,

PO,

P2,

PO,

P2,

PO,

ZB671

P2,

PO,

MCU

P2,

P0 7

PORT 1
110 OR ADo-AD I

P2,

P27

P',

P3,

P1,

P3,

P',

P3,

P1,

P3,

P1,

P3,

P',

P3,

P',

P3,

P'7

P37

Figure 1. Pin Functions

Because the BASIClDebug interpreter is already part of the
chip circuit, programming is made much easier. The Z8671
MCU thus offers a combination of software and hardware
that is ideal for many industrial control applications. The
Z8671 MCU allows fast hardware tests and bit-by-bit
examination and modification of memory location, I/O ports,

+5V

P3,

XTAL2

P3,

XTAL1

P2 7

P37

P2,

P3,

P2,

RESET

P2,

R/VI

P2,

os

P2,

AS

P2,

P3,

P2,

GND

P3,

P3,

P3,

PO,

AD,

PO,

AD,

PO,

AD,

PO,

AD,

PO,

AD,

PO,

AD,

PO,

AD,

PO,

ADo

Figure 2a. 40-pin Dual-In-Line Package (DIP),
Pin Assignments

41

.......=

II

a

or registers. It also allows bit manipulation and logical
operations. A self-contained line editor supports interactive
debugging, further speeding up program development.

,,' ,J-

~ q"Oq"'.¢"'.¢'" x'>" q"'<{>'q~q""q"'~
6

The BASIC/Debug interpreter, a subset of Dartmouth
BASIC, operates with three kinds of memory: on-chip
registers and external ROM or RAM. The BASIC/Debug
interpreter is located in the 2K bytes of on-chip ROM.
Additional features of the Z8671 MCU include the ability to
call machine language subroutines to increase execution
speed and the ability to have a program execute on
power-up or Reset, without operator intervention.
Maximum memory addressing capabilities include 62K
bytes of external program memory and 62K bytes of data
memory with program storage beginning at location 800H.
This provides up to 124K bytes of useable memory space.
Very few 8-bit microcomputers can directly access this
amount of memory.
Each Z8671 Microcomputer has 32 110 lines, a 144-byte
register file, an on-board UART, and two counter/timers.

1/0
(BIT PROGRAMMABLE)

ADDRESS OR 1/0
(NIBBLE PROGRAMMABLE)

4

3

2

1 44 43 42 41 40
39

NC

R/W

8

38

P2,

os

9

37

P2,

AS

10

36

P2.

P3,

11

35

P2,

34

P2.

Z8671

GND

12

P3.

13

33

P3,

PO.

14

32

P3,

PO,

15

31

P17

PO.

16

30

P1.

NC

17

29

P1,

MCU

18 19 20 21 22 23 24 25 26 27 28
~f>~ qe::,.,.qf:;)'? q(i:j'o q01.  A > B := 001
A > B > C == 010
A> C > B == 011

IR03, lAOS PRIORITV (GROUP A)
o := IROS > IRQ3
1 == IRQ3 > IROS

REGISTER
POINTER

g
~ ; ~ ~ ~ ~g~
8> A > C '" 110

tRao, IRQ2 PRIORITY (GROUP B)
o = IRQ2 > IROO
1 :=: IROO > IRQ2

RESERVED == 111

IRQ1, IRQ4 PRIORITY (GROUP C)

o :=:

IRQl

>

IFlQ4

1 '" IFlQ4 > IRQ1

R250lRQ
Interrupt Request Register
(FAH: Read/Wnte)

R254SPH
Stack Pointer
(FEH: Read/Write)

I~I~I~I~I~I~I~I~I
RESERVED (MUST BE 0)

~

c=::

IROO

P32 INPUT (Do = IROO)

IRQl
IRQ2
IRQ3
IRQ4
lAOS

P331NPUT

P3l INPUT
P30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT

T,

R2511MR
Interrupt Mask Register
(FBH, Read/Wnte)

R255SPL
Stack Pointer
(FFH, Read/Wnte)

I~I~I~I~I~I~I~I~I

I'

c=:: '

1~I~t~I~I~I~I~I~1
ENABLES IRQO-IRQ5

(Do'" IROO)

' - - - - - - - RESERVED (MUST BE 0)

L I_ _ _ _

:~~~~s~~~~~~R

LOWER

' - - - - - - - - 1 ENABLES INTERRUPTS

Figure 12. Control Registers (Continued)

55

OPCODEMAP
Lower Nibble (Hex)

o
o

A

B

C

D

10,5

10,5

65

6,5

6,5

6,5

DEC

DEC

ADD

ADD

ADD

ADD

ADD

ADD

R,

IR,

(1,(2

f1.lr2

R2,R,

IR2,R,

R"IM

IR"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IR"IM

10,5

10,5

R,

IR,

r1,(2

f1, lr2

R2,R,

IR2,R,

R"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IR"IM

R,

IR,

r1,(2

f1, lr2

R2,R,

IR2,R,

R"IM

8,0

6,1_

6,5

6,5

10,5

10,5

10,5

10,5

JP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRR,

1M

r1,r2

f1, lr2

R2,R,

IR2,R,

R"IM

IR"IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA

DA

OR

OR

OR

OR

OR

OR
IR"IM

R,

IR,

(1,f2

f1, lr2

R2,R,

IR2,R,

R"IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP

POP

AND

AND

AND

AND

AND

AND
IR"IM

R,

IR,

(1,(2

f1, lr2

R2,R,

IR2,R,

R"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

R,

IR,

(1,(2

f1, lr2

R2,R,

IR2,R,

R"IM

IR"IM

10112, ,

12114,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

R2,R,

IR2,R,

R"IM

IR"IM

R2

IR2

(1,(2

f1, lr2

,0.5

10.5

12,0

18,0

DECW

DECW

LDE

LDEI

RR,

IR,

f1, lrr2

If1,lrr2

6,5

6,5

12,0

18,0

RL

RL

LDE

LDEI

R,

IR,

f2, lrr 1

Ir2,lrr1

A

B

C

D

E

6,5

12/10,5

12/10,0

6,5

12/10,0

6,5

LD

LD

DJNZ

JR

LD

JP

INC

fl.R2

f2,Rl

r"RA

cC,RA

r"IM

cC,DA

r1

8

6

6,5

F

r--r--r---

r--r--r---

r--~
DI

r--6,1
EI

'0,5

10,5

6,5

6,5

10,5

'0,5

10.5

10,5

r--14,0

INCW

INCW

CP

CP

CP

CP

CP

CP

RET

RR,

IR,

(1/2

(1, lr2

R2,R,

IR2,R,

R"IM

IR"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

R,

IR,

(1 (2

(1, lr 2

R2,R,

IR2,R,

R"IM

IR"IM

6,5

6,5

12,0

18,0

10,5

RRC

RRC

LDC

LDCI

LD

R,

IR,

fl,lrr2

Ir1,lrr2

fl,X,R2

6,5

6,5

12,0

18,0

20,0

20,0

SRA

SRA

LDC

LDCI

CALL'

CALL

LD

R,

IR,

Ir2,lrr1

IRR,

DA

f2,x,Rl

10,5

6,5

(2. lrr1

10,5

~
IRET

~
RCF

r--6,5

10,5

6,5

6,5

10,5

10,5

RR

RR

LD

LD

LD

LD

LD

R,

IR,

rl, IR2

R2,R,

IR2,R,

R"IM

IR"IM

SCF

r--6,5
CCF

85

8,5

10,5

c6,0
--

SWAP

SWAP

LD

LD

NOP

R,

IR,

Ir1,(2

R2,IR,

6,5

. . . -----...'V. .____-'J ......-----'V. .-----.I . . . ------.. v. ...------.,.I~"__v___'"
2
Bytes per Instruction

LOWER
OPCODE

NI~LE
EXECUTiON
CYCLES
UPPER
OPCODE ----. A
NIBBLE
FIRST
OPERAND

• 2 byte instruction fetch cycle appears as a 3-byte Instruction

56

PIPELINE
CYCLES

MNEMONIC

Legend:
R = 8-blt address
r = 4·blt address
R1 orr1 = Ost address
R2 or (2 = Src address
Sequence:
Opcode, First Operand, Second Operand

SECOND
OPERAND

NOTE The blank areas are not defined

ABSOWTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND ......................... -O.3Vto + 7.0V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. -65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for exlended periods may affect
device reliability.

STANDARD TEST CONDITIONS
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.

The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the
Package Information section. Refer to the Literature List for
additional documentation.

Standard conditions are:
•

+4.75V"'Vee'" +5.25V

• GND

=

+5V

OV

+5V

1.5k
+5V

+5V

74LS04

Uk
74LS04

I

18K

'-----P""

I

Figure 13. Test Load 1

CL

= 15ptMAX

XTAL1
CL = 15ptMAX

Figure 15. TTL External Clock Interface Circuit
(Both the clock and Its complement are required)

Figure 14. Test Load 2

DC CHARACTERISTICS
Symbol

Parameter

VCH

Clock Input High Voltage

VCL

Clock Input Low Voltage
Input High Voltage

VIH
VIL

Input Low Voltage
Input High Voltage

VRH

Res~

VRL

Reset Input Low Voltage

VOH
VOL

Output High Voltage

Min

Max

Unit

3.8

Vec
0.8

V

Driven by External Clock Generator

-0.3

V

Driven by External Clock Generator

2.0
-0.3

Vee
0.8

V

3.8

Vee
0.8

-0.3

V
V
V

V

IOH = -250!J.A
IOL = +20 mA

V

2.4

Output Low Voltage

0.4

Condition

IlL

Input Leakage

-10

10

!J.A

OV ~ VIN'" + 5.25V

IOL

Output Leakage

-10

10

!J.A

OV ~ VIN'" + 5.25V

IIR

Reset Input Current

-50

Vee

ICC

Vce Supply Current

180

!J.A
mA

=

+ 5.25V, VRL

=

OV

57

K

)(
~

PORTO,

--®-I

)(

DM

16
3

)j

PORT 1

Ao-A,

..   MODE
PRESCALER MODULO
(RANGE: 1-84 DECIMAL
01-00 HEX)

[gE

LO.ORT'.ULL.U.SO.EN DRAIN
1 PORT 2 PULL·UPS ACTIVE
RESERVED (MUST BE 0)

o P32

== INPUT

Pis

=

o0

Pit = INPUT

ps.

= OUTPUT

11

RESERVED

OUTPUT

1 Pia == 6JV!lIRDYO P3,:: RDYOl~

~~}.o, = IN.UT

~ ::~ ~ b'W£'J~~~

'------- ~;=: ~~~lL IN
'-_______ g:F

PI. . IlM

=:: ~ ~~~~~uTI
~~ ~ g~~r.~TOUT

~ ::=:~

Figure 18. Control Registers

76

2194-020

REGISTERS

R248P01M
Port 0 Register
(F8H; Write Only)

(Continued)

R252 FLAGS
Flag Register
(FCH; ReadlWrite)
I~I~I~I~I~I~I~I~I

--1

PO._Po,MODE:]
OUTPUT • 00
INPUT • Ot
• 1)(

~-r
L pa.-po, MODE

'

llI~~

LUBE"FLAGF'
LUSEA FLAO F2

00· OUTPUT

01 • INPUT
1)( • A,-A u

A12~A'1

EXTERNAL
MEMORY TIMING
NORMAL • 0
• EXTENDED. 1

STACK SELECTION
0 • EXTERNAL
1 • INTERNAL

HALF CARR"' FLAG
DECIMAL ADJUST FLAG

OVERFLOW FLAG
SION FLAG
ZERO FLAG

RESERVED (MUST BE 0)

CARRY FLAG

-ALWAYS EXTENDED TIMING AFTER RESET

R2491PR
Interrupt Priority Register
(F9H; Write Only)
I~I~I~I~I~I~I~I

R253RP
Register Pointer
(FDH; Read/Write)

I I III-'-~
RESERVED = 000
C > It. > 8 '" 001
A>8>C::010
A > C > 8 = 011

."_.:J

IRQ3, IAQ5 PRIORITY (GROUP AI
0=IAQ5>IRQ3
1 = IRQ3 > IAQ5

i...

.. I

=
I

REGISTER
POINTER

~ ~ ~ ~ : : ~~

IRQO, IA02 PRIORITY (GROUP II
o '" IA02 > IROO
1 = IROO > IRQ2

8 > A > C = 110
RESERVED

=

111

IRQ1, IRQ4 PRIORITV (GROUP C)
o = IAQ1 > IRQ4
1
IA04 > IAQ1

=

R250lRQ
Interrupt Request Register
(FAH; ReadlWrite)
I~I~I~I~I~I~I~I

RESERVED (MUST BE

O):::r-

R254SPH
Stack Pointer
(FEH; Read/Write)

.. I

c::=

I~I~I~I~I~I~I~I~I

IROO • PI! INPUT (Do • IROO)
IAQ1 • Pia INPUT

LI_ _ _

IROJ • PIt INPUT
IAQ3 • P30 INPUT, SERIAL INPUT

:~~~7s-;:~:~:r

UPPER

IRQ4. To. SERIAL OUTPUT
IRQIi. T,

R2511MR
Interrupt Mask Register
(FBH; Read/Write)

JI.

c::=
___ '

____

(DoENABLEB
.IAOO)

R255SPL
Stack Pointer
(FFH; ReadlWrite)

I~I~I~I~I~I~I~I~I

'"oo-'"Q'

RESERYED (MUST BE 0)

1...._ _ _

:~~~~?~:~~A LOWER

' - - - - - - - - 1 ENAILES INTERRUPTS

Figure 18. Control Registers (Continued)

2194-020

77

Z86L81185 OPCODE MAP
Lower Nibble (Hex)

o
o

C

D

5

6

7

8

9

6.5

10.5

10.5

10.5

10,5

6,5

6.5

DEC

DEC

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DJNZ

JR

R,

IR,

'l,f2

(1, lr2

R2.Rl

IR2.R,

R,.IM

IR,.IM

r,. R2

r2. R,

r,.RA

cc,RA

6.5

6.5

6.5

6.5

10.5

10.5

10,5

10,5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

AOC
IR"IM

R,

IR,

'l,f2

IR2,R,

R,. IM

6.5

6.5

'l,lr2
6,5

R2. R,

6.5

10.5

10.5

10.5

10.5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IR"IM

R,

IR,

'1,(2

'l, lr2

R2.R,

IR2.R,

R,.IM

8.0

6.1,

6.5

6.5

10,5

10.5

JP

SRP

SBC

SBC

SBC

sac

10.5

SBC

sac

IRR,

1M

'1,r2

IR2,R,

R,.IM

IR"IM

8,5

6.5

r" lr2
6.5

R2. R,

8,5

10.5

10.5

10,5

10.5

DA

DA

OR

OR

OR

OR

OR

OR
IR,.IM

R,

IR,

'1,r2

'1, lr2

R2.Rl

IR2.R,

R,. IM

10,5

6.5

6.5

10,5

10.5

10.5

10,5

POP

POP

AND

AND

AND

AND

AND

AND
IR,.1M

R,

IR,

'1,r2

(1, lr2

R2. R,

IR2.R,

R,. IM

6.5

6,5

6.5

6.5

10.5

10.5

10.5

10.5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

R,

IR,

'1,(2

'1, lr2

R2.Rl

IR2,R,

R"IM

IR"IM

10/12.1

12/14.1

6.5

6.5

10.5

10.5

10,5

10.5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

R2.R,

IR2.R,

R,.IM

IR"IM

R2

IR2

(1,r2

r" lr2

10,5

10.5

12,0

18,0

DECW

DECW

LDE

LDEI

RR,

IR,

(1, lrr2

Ir"lrr2

6.5

6,5

12,0

18,0

RL

RL

LDE

LDEI

R,

IR,

(2, lrr,

Ir2,lrr,

10,5

10.5

6.5

6.5

10,5

10,5

10.5

10,5

INCW

INCW

CP

CP

CP

CP

CP

CP

RR,

IR,

'1,r2

r,. lr2

R2.R,

IR2.R,

R,.IM

IR,.IM

6,5

6.5

6,5

6,5

10,5

10.5

10.5

10,5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

JP

INC

cc.DA

rl

R2. R,

IR2.R,

R,.IM

IR,.IM

f-f-f--

f-f-'---

-

6,1

6,1

EI

-

IR,

'1,r2

("lr2

12.0

18,0

10,5

RRC

RRC

LDC

LOCI

LD

-

R,

IR,

(1, lrr2

Ir"lrr2

6,5

12.0

18,0

20.0

20,0

-

10.5

SRA

SRA

LDC

LDCI

CALL'

CALL

LD

T2,lrr,

r"x,R2

R,

IR,

Ir2,lrr,

IRR,

DA

r2,)(,R,

6,5

6.5

10.5

10,5

10.5

10.5

RR

RR

LD

LD

LD

LD

LD

R2.R,

IR2,R,

R"IM

IR"IM

IR,

r,. IR2

8.5

6,5

10.5

SWAP

SWAP

LD

LD

R,

IR,

-

6,5

-

6,5

CCF

-

6.0

NOP

R2. IR,

Ir"r2
~J~,

6.5

SCF

6,5

R,

16,0

IRET
RCF

6.5

8,5

14.0

RET

6.5

________

LD
r,. IM

F

DI

R,

,~,

E
6,5

-

6,5

________

D

12/10,0

10,5

10,5

~,

C
6,5

A
12110.5 12/10.0

6.5

E

F

4

6,5

9

B

3

6.5

4

A

2

________

,~,

________

~J,,-

________

~~~

________

-,J~~

3

2

3

2

Byte. per Instruction

LOWER
OPCODE
NITE
EXECUTION
CYCLES

PIPELINE
CYCLES

Legend:

MNEMONIC

R2 or (2 = Src address

R = 8-bIt address
r = 4-brt address

R, or'1

=

Dst address

Sequence:
Opcode. First Operand. Second Operand

FIRST
OPERAND

SECOND
OPERAND

NOTE The blank areas are not defined

• 2 byte Instruction, fetch cycle appears as a 3-byte instruction

78

2194-021

ABSOWTE MAXIMUM RATINGS
Voltages on all pins except RESET
with respecttoGND ............... -O.3Vto + 7.0V
Operating Ambient
Temperature ..............See Ordering Information
Storage Temperature .............. -65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability

STANDARD TEST CONDITIONS
The DC characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.
Standard conditions are as follows:
•

+4.75VIA03
1 = IRQ3> IRQ5

RESERVED ;::: 000
C > A > 8 "" 001
A>8>C=010
,,>C>8=011

~~~~~

IRaO, IR02 PRIORITY (GROUP 8)

0=IRQ2>IAoo
1 ". IROO :> IR02

:

~=

8>A>C=110
RESERVED = 111

REGISTER

POINTER

{~

till

=

LDON1TCARE

IRQ1, IRQ4 PRIORITY (GROUP C)

o ;: :

IRQ1 :> IRQ4

1 = IACM :> IAQ1

R254SPH
Stack Pointer
(FEH; ReadIWrite)

R250lRQ
Interrupt Request Register
(FAH; ReadIWrite)
l~t~I~I~t~t~I~I~1

RESERVED (MUST BE

o)::r-

c=

IROO _ PI2 INPUT (Do

•

tROO)

IROl • Pia INPUT
IH02 • P3, INPUT
IRQ3 • '30 INPUT, SERIAL INPUT
IR04 • To. SERIAL OUTPUT

IRO&· T,

R2511MR
Interrupt Mask Register
(FBH; ReadIWnte)

Il___

R255SPL
Stack Pointer
(FFH; Read/Write)
1~1~I~t~I~I~I~I~1

C=
___ (Do •

1 ENABLES fROO-IRQS

tRQO)

RESERVED (MUST BE 0)

1'--___ r~~~:'~!:~:R LOWER

' - - - - - - - - 1 ENABLES INTERRUPTS

Figure 15. Control Registers (Continued)

2343-013

97

Z86L81185 OPCODE MAP
IAMr Nibble (Hex)

2

o

2

3

4

6

i

=-

Iz

I
go

7

8

9

A

a
C

D

E

F

4

5

6

7

8

9

A

a

C

D

E

10.5

10.5

10.5

10.5

6.5

6.5

12110.5

12110.0

6.5

12110.0

6.5

6.5

6.5

6.5

6.5

DEC

DEC

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DJNZ

JR

LD

JP

INC

Rl

IRI

r1,r2

rl. lr2

R2. Rl

IR2.Rl

Rl.IM

IR1.IM

rl. R2

r2. Rl

rl. RA

cc.RA

rl. IM

cc.DA

rl

6.5

6.5

6.5

6.5

10.5

10.5

10.5

10.5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IR1.IM

Rl

IRI

(1,r2

r1, lr2

R2. Rl

IR2.Rl

Rl. IM

6.5

6.5

6.5

sua

10.5

sua

10.5

INC

sua

10.5

INC

sua

6.5

sua

sua
IR1.IM

Rl

IRI

(1,r2

f1, lr2

R2. Rl

IR2.Rl

Rl. IM

6.1,

6.5

sac

10.5

sac

10.5

SRP

sac

10.5

JP

sac

6.5

sac

sac

IRRI

1M

r1,r2

rl. lr2

R2.Rl

IR2.Rl

Rl.IM

IR1.IM

8.5

8.5

6.5

6.5

10.5

10.5

10.5

10.5

DA

DA

OR

OR

OR

OR

OR

OR
IR1.IM

Rl

IRI

rl.r2

rl. lr2

R2. Rl

IR2.Rl

Rl.IM

10.5

6.5

6.5

10.5

10.5

10.5

10.5

POP

POP

AND

AND

AND

AND

AND

AND
IR1.IM

Rl

IRI

r1,r2

rl. lr2

R2. Rl

IR2.Rl

Rl.IM

6.5

6.5

6.5

6.5

10.5

10.5

10.5

10.5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

Rl

IRI

r1,f2

f1, lr2

R2. Rl

IR2.Rl

Rl.IM

IR1.IM

10112.1

12114.1

6.5

6.5

10.5

10.5

10.5

10.5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

R2. Rl

IR2.Rl

Rl. IM

IR1.IM

R2

IR2

(1/2

f1, lr2

10.5

10.5

12.0

18.0

DECW

OECW

LDE

LDEI

RRI

IRI

(1, lrr2

Irl,lrr2

6.5

6.5

12.0

r--

10.5

10.5

r-r-r--

r--

r--s:;-DI

r--

18.0

RL

RL

LDE

LDEI

Rl

IRI

r2, lrT 1

Ir2,lrr1
6.5

r-r--

10.5

8.0

F

6.1

EI

10.5

10.5

6.5

INCW

INCW

CP

CP

CP

CP

CP

CP

RRI

IRI

(1,r2

rl. lr2

R2. Rl

IR2.Rl

Rl. IM

IR1.IM

10.5

10.5

10.5

~

10.5

6.5

6.5

6.5

6.5

10.5

10.5

10.5

10.5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

Rl

IRI

(1.r2

(l, lr2

R2.Rl

IR2.Rl

Rl.IM

IR1.IM

6.5

6.5

12.0

18.0

10.5

RRC

RRC

LDC

LDCI

LD

Rl

IRI

r1, lrr2

Ir1,lrr2

6.5

6.5

12.0

18.0

20.0

20.0

10.5

SRA

SRA

LDC

LDCI

CALL"

CALL

LD

Rl

IRI

r2, lrT1

Ir2,lrr1

IRRI

DA

r2,x,Rl

6.5

6.5

6.5

10.5

10.5

10.5

10.5

RR

RR

LD

LD

LD

LD

LD

Rl

IRI

rl. IR2

R2. Rl

IR2.Rl

Rl.IM

IR 1.IM

RET

r---;-e:o
IRET

r-6.5

RCF

rl.x.R2

8.5

8.5

6.5

10.5

SWAP

SWAP

LD

LD

Rl

IRI

Ir1,(2

R2.IRI

~
SCF

~
CCF

r-6.0

NOP

v,..-----'JIo.....---__..v,..----#Io.....- - - - -.....v,..-----"'"#~"'--v--"

1o..
..._ _ _ _

2

2

3

3

aytes per Instruction

LOWER
OPCODE
NIB~LE
EXECUTION
CYCLES

PIPELINE
CYCLES

MNEMONIC

Legend:
R = S·blt address
r = 4·bit address
Rlorrl = Dst address
R20rr2 = Src address

Sequence:
Opcode. First Operand. Second Operand

FIRST
OPERAND

SECOND
OPERAND

NOTE' The blank areas are not defined

*2·byte Instruction, fetch cycle appears as a 3-byte Instruclton

98

8085-002

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins' with respect
to GND ......................... -0.3Vto + 7.0V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65
to + 150

°e

°e

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above these indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

• Except RESET

STANDARD TEST CONDITIONS

+SV

+5V

De

The
characteristics listed below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin.

1.5k

1.Sk

74LS04

74LS04

CLOCK

IN

Standard conditions are as follows:

:><:-......_ - 1 :><:-....- -

XTAL2

L -_ _ _ _ _

XTAL1

• + 4. 75V"; Vcc"; + 5.25V
• GND = OV

• ooe..; TA"; + 70 e for S (Standard temperature)
0

+5V

Figure 17a. Z86L81 External Clock Interface Circuit
2.1K

+SV

150pf

I

1.SK

74LS04

CLO~~

--1.>0-+---

XTAL 1

Figure 17b. Z86L85 External Clock Interface Circuit

Figure 16. Test Load 1

DC CHARACTERISTICS
Symbol

Parameter

VCH

Clock Input High Voltage

VCl

Clock Input Low Voltage

V'H

Input High Voltage

Vil

Input Low Voltage

VRH

Reset Input High Voltage

Min

Max

Unit

Test Condition

3.8

Vcc

V

Driven by External Clock Generator

-0.3

0.8

V

Driven by External Clock Generator

V

20

Vee

-0.3

0.8

V

3.8

VCC

V

-0.3

0.8

V

VRl

Reset Input Low Voltage

VOH

Output High Voltage

VOL

Output Low Voltage

III

Input Leakage

-10

10

IOl

Output Leakage

-10

10

2.4
0.4

V

IOH

= -250fJA

V

IOl

=

,..A
,..A

+2.0mA

OV" VIN";
OV" VIN";

+ 5.25V
+ 5.25V

IIR

Reset Input Current

-50

fJA

Vcc = + 5.25V, VRl = OV

ICC

VCC Supply Current

90

mA

8 MHz Clock (86L81/85·8L)

IMM

VMM Supply Current

10

mA

VMM

Backup Supply Voltage

2343-014,015,016

3

Vce

V

Power Down Mode (Z86L85 only)
Power Down (Z86L85 only)

99

AC CHARACTERISTICS
External 1/0 or Memory Read and Write Timing

~
+®PORTO,

iSM

PORT 1

--®-+

~

'i6'

).

Ao-A7

..(j)+

K
3

)

<

-B>A

A>B>C

B>A>C
C>A>B

I

I

J L=

GROUP A
o IROO >IR01
1 = IRQ1 > IROO

' - - - GROUPB
o = IR02 > (IR03,IRQ4)
1 = (IRQa,IR04) >IRQ2

C>B>A
A>C>B

SUBGROUPB
o = IRQ3> IRQ4

1

UNDEFINED

= IRQ4 > IRQ3

GROUPC
o = IR05 > (IRQ6,IR07)
1 = (IR06,IR07) >IRQ5
SUBGROUPC
o = lAOS> IRQ7
1 = IAQ7 > lAOS

R255 BANK 1 (FF) WUMSK
WAKE·UP MASK REGISTER

I~I~I~I~I~I~I~I~I
LI_ _ _ _ _ _

THESE BITS CORRESPOND TO BITS

IN WAKE·UP MATCH REGISTER; Os
MASK CORRESPONDING MATCH BITS

119

110 PORTS
The Super-8 comes in two versions: one version has 32 110
lines arranged into four 8-bit ports and the other version has
40 I/O lines arranged into five 8-bit ports. These lines are all
TTL-compatible, and can be configured as inputs qr
outputs. Some can also be configured as address/data
lines.
Each port has an input register, an output register, and a
register address. Data coming into the port is stored in the
input register, and data to be written to a port is stored in the
output register. Reading a port's register address returns the
value in the input register; writing a port's register address
loads the value in the output register. If the port is configured
for an output, this value will appear on the external pins.
When the CPU reads the bits configured as outputs, the
data on the external pins is returned. Under normal output
loading, this has the same effect as reading the output
register, unless the bits are configured as open-drain
outputs.
The ports can be configured as shown in Table 2.
Table 2. Port Configuration
Port

Configuration Choices

o

Address outputs andlor general 1/0
Multiplexed address/data or general 110
Control 1/0 for UART, handshake channels, and
counter/timers; also general 1/0 and external
interrupts
General 1/0

1
2and3

4

PortO

Port 0 can be configured as an 1/0 port or an output for
addressing external memory, or it can be divided and used
as both. The bits configured as 1/0 can be either all outputs
or all inputs; they cannot be mixed. If configured for outputs,
they can be push-pull or open-drain type.
Any bits configured for 1/0 can be accessed via R208. To
write to the port, specify R208 as the destination (dst) of an
instruction; to read the port, specify R208 as the source
(src).
Port 0 bits configured as 1/0 can be placed under
handshake control of handshake channel 1.
Port 0 bits configured as address outputs cannot be
accessed via the register.
Port 1

Port 1 can be configured as a byte-wide address/data port,
or as a byte 1/0 port. When configured as an address/data
port, it provides a byte-wide multiplexed address/data path.
Additional address lines can be added by configuring
Port O.

120

The 64-pin ROM less version of the Super-8 provides
separate address/data lines. Port 1 is then available for 1/0.
Port 1's input/output register address is R209. Data is read
from the port by specifying R209 as the source of an
instruction; data is written to the port by specifying R209 as
the destination.
When configured for 110, Port 1 can be placed under
handshake control.
When configured as an address/data port, Port 1 cannot be
accessed as a register.
Ports2and3

Ports 2 and 3 provide external control inputs and outputs for
the UART, handshake channels, and counterltimers. The
pin assignments appear in Table 3.
Bits not used for control 1/0 can be configured as
general-purpose 1/0 lines andlor external interrupt inputs.
Those bits configured for general 1/0 can be configured
individually for input or output. Those configured for output
can be individually configured for open-drain or push-pull
output.
All Port 2 and 3 input pins are Schmitt-triggered.
The port address for Port 2 is R210, and for Port 3 is R211.
Table 3. Pin Assignments for Ports 2 and 3

Bit

0
1
2
3
4
5
6
7

Port 2
Function
UART receive clock
UART transmit clock
810 receive clock
810 transmit clock
Handshake 0 input
Handshake 0 output
Counter 0 input
Counter 0 1/0

Bit

0
1
2
3
4
5
6
7

Port 3
Function
UART receive data
UART transmit data
810 receive data
810 transmit data
Handshake 1 inputIWAIT
Handshake 1 output/DM
Counter 1 input
Counter 1 1/0

Port 4
Port 4 can be configured as 1/0 only. It exists internally in all
versions of the Super-8, but has no connection to external
pins in the 40-pin models. Each bit can be configured
individually as input or output, with either push-pull or
open-drain outputs. All Port 4 inputs are Schmitt-triggered.
Port 4 can be placed under handshake control of
handshake channel O. Its register address is R212.
Ports 1 and 4 use the same handshake line in Port 2. Only
one can use the handshake feature at a given time.

UART

Receiver

The UART is a full-duplex asynchronous channel. It
transmits and receives independently with 5 to 8 bits per
character, has options for even or odd bit parity, and a
wake-up feature.

The UART begins receive operation when Receive Enable
(URC, bit 0) is set High. After this, a Low on the receive input
pin for longer than half a bit time is interpreted as a start bit.
The UART samples the data on the input pin in the middle of
each clock cycle until a complete byte is assembled. This is
placed in the Receive Data register.

Data can be read into or out of the UART via R239, Bank O.
This single address is able to serve a full-duplex channel
because it contains two complete 8-bit registers-one for
the transmitter and the other for the receiver.

Pins
The UART uses the following Port 2 and 3 pins:

Port/Pin
2/0
3/0
2/1
3/1

UART Function
Receive Clock
Receive Data
Transmit Clock
Transmit Data

Transmitter
When the UART's register address is specified as the
destination (dst) of an operation, the data is output on the
UART, which automatically adds the start bit, the
programmed parity bit, and the programmed number of
stop bits. It can also add a wake-up bit if that option is
selected.

If the 1X clock mode is selected, external bit synchronization
must be provided, and the input data is sampled on the
rising edge of the clock.
For character lengths of less than eight bits, the UART
inserts ones into the unused bits, and, if parity is enabled,
the parity bit is not stripped. The data bits, extra ones, and
the parity bit are placed in the UART Data register (UIO).
While the UART is assembling a byte in its input shift register,
the CPU has time to service an interrupt and manipulate the
data character in UIO.
Once a complete character is assembled, the UART checks
it and performs the following:
•

If it is an ASCII control character, the UART sets the
Control Character status bit.

•

It checks the wake-up settings and completes any
indicated action.

•

If parity is enabled, the UART checks to see if the
calculated parity matches the programmed parity bit. If
they do not match, it sets the Parity Error bit in URC
(R236 Bank 0), which remains set until reset by software.

•

It sets the Framing Error bit (URC, bit 4) if the character is
assembled without any stop bits. This bit remains set until
cleared by software.

lithe UART is programmed for a 5-,6-, or 7-bit character, the
extra bits in R239 are ignored.
Serial data is transmitted at a rate equal to 1, 1/16, 1/32 or
1/64 of the transmitter clock rate, depending on the
programmed data rate. All data is sent out on the falling
edge of the clock input.
When the UART has no data to send, it holds the output
marking (High). It may be programmed with the Send Break
command to hold the output Low (Spacing), which it
continues until the command is cleared.

Overrun errors occur when characters are received faster
than they are read. That is, when the UART has assembled a
complete character before the CPU has read the current
character, the UART sets the Overrun Error bit (URC, bit 3),
and the character currently in the receive buffer is lost.
The overrun bit remains set until cleared by software.

121

fi

....=

ADDRESS SPACE
The Super-8 can access 64K bytes of program memory and
64K bytes of data memory. These spaces can be either
combined or separate. If separate, they are controlled by the
DM line (Port P3s), which selects data memory when Low
and program memory when High.

OM LOW

OM HIGH
~

~

64K

r - - - - - , 64K

CPU Program Memory
Program memory occupies addresses 0 to 64K. On-chip
ROM always occupies the lowest part of program memory.
Space beyond the on-chip ROM can be accessed by
configuring Ports 0 and 1 as a memory interface. Port 1 can
be used as an 8-bit multiplexed address/data port; Port 0
can be configured to provide from 0 to 8 additional address
lines.

INTERNAL ROM
4K, 8K , OR 16K

32
INTERRUPT
VECTORS
....._
_ _... 00

~

_ _..... oo

DATA MEMORY

PROGRAM MEMORY

The address/data lines are controlled by AS, DS and RiW.
The first 32 program memory bytes are reserved for
interrupt vectors; the lowest address available for user
programs is 32 (decimal). This value is automatically loaded
into the program counter after a hardware reset.
In 40- and 48-pin ROMless versions, Port 1 is automatically
configured as a multiplexed address/data port.
Figure 6 shows the system memory space.

Figure 6. Memory Map
CPU Data Memory
The CPU data memory space, if separate from program
memory, is also accessed using Port 1 asADo-AD7, with DM
Low. Accesses are controlled by AS, DS, and RiW. Port 0
can be configured to provide additional address lines.

INSTRUCTION SET
The Super-8 instruction set is designed to handle its large
register set. The instruction set provides a full complement
of 8-bit arithmetic and logical operations, including multiply
and divide. It supports BCD operations using a decimal
adjustment of binary values, and it supports incrementing
and decrementing 16-bit quantities for addresses and
counters.
It provides extensive bit manipulation, and rotate and shift
operations, and it requires no special I/O instructions-the
I/O ports are mapped into the register file.

Flag Register
The Flag register (FLAGS) contains eight bits that describe
the current status of the Super-8. Four ofthese can be tested
and used with conditional jump instructions; two others are
used for BCD arithmetic. FLAGS also contains the Bank
Address bit and the Fast Interrupt Status bit.
The flag bits can be set and reset by instructions.

CAUTION
Instruction Pointer
A special register called the Instruction Pointer (lP) provides
hardware support for threaded-code languages. It consists
of register-pair R218 and R219, and it contains memory
addresses. The MSB is R218.
Threaded-code languages deal with an imaginary
higher-level machine within the existing hardware machine.
The IP acts like the PC for that machine. The command
NEXT passes control to or from the hardware machine to the
imaginary machine, and the commands ENTER and EXIT
are imaginary machine equivalents of (real machine) CALLS
and RETURNS.
lithe commands NEXT, ENTER, and EXIT are not used, the
IP can be used by the fast interrupt processing, as
described in the Interrupts section.

122

Do not specify FLAGS as the destination of an
instruction that normally affects the flag bits or the
result will be unspecified.
The following paragraphs describe each flag bit:

Bank Select. This bit is used to select one of the register
banks (0 or 1) between (decimal) addresses 224 and 255. It
is cleared by the SBO instruction and set by the SB1
instruction.

Fast Interrupt Status. This bit is set during a fast interrupt
cycle and reset during the IRET following interrupt servicing.
When set, this bit inhibits all interrupts and causes the fast
interrupt return to be executed when the IRET instruction is
fetched.

2355·009

Half·Carry. This bit is set to 1 whenever an addition
generates a carry out of bit 3, or when a subtraction borrows
out of bit 3. This bit is used by the Decimal Adjust (DA)
instruction to convert the binary result of a previous addition
or subtraction into the correct decimal (BCD) result. This
flag, and the Decimal Adjust flag, are not usually accessed
by users.
Decimal Adjust. This bit is used to specify what type of
instruction was executed last during BCD operations, so a
subsequent Decimal Adjust operation can function
correctly. This bit is not usually accessible to programmers,
and cannot be used as a test condition.
Overflow Flag. This flag is set to 1 when the result of a
twos-complement operation was greater than 127 or less
than -128. It is also cleared to 0 during logical operations.
Sign Flag. Following arithmetic, logical, rotate, or shift
operations, this bit identifies the state of the MSB of the
result. A 0 indicates a positive number and a 1 indicates a
negative number.
Zero Flag. For arithmetic and logical operations, this flag is
set to 1 if the result of the operation is zero.
For operations that test bits in a register, the zero bit is set to 1
if the result is zero.
For rotate and shift operations, this bit is set to 1 if the result is
zero.

Carry Flag. This flag is set to 1 if the result from an arithmetic
operation generates a carry out of, or a borrow into, bit 7.

After rotate and shift operations, it contains the last value
shifted out of the specified register.
It can be set, cleared, or complemented by instructions.

Condition Codes
The flags C, Z, S, and V are used to control the operation of
conditional jump instructions.
The opcode of a conditional jump contains a 4-bit field
called the condition code (cc). This specifies under which
conditions it is to execute the jump. For example, a
conditional jump with the condition code for "equal" after a
compare operation only jumps if the two operands are
equal.
The condition codes and their meanings are given in
Table 4.

Addressing Modes
All operands except for immediate data and condition
codes are expressed as register addresses, program
memory addresses, or data memory addresses. The
addressing modes and their designations are:
Register (R)
Indirect Register (IR)
Indexed (X)
Direct (DA)
Relative (RA)
Immediate (1M)

Table 4. Condition Codes and Meanings
Mnemonic

0000

F

1000
0111 •

C

C=1

Carry

1111 •

NC

0110'

Z
NZ

C=O
Z=1

Zero

1110'
1101
0101

0100
1100
0110'
1110'
1001
0001
1010
0010
1111 •
0111 •

Flags

Meaning

Binary

Always false
Always true

Z=O

No carry

PL
MI

8=0
8=1

Not zero
Plus
Minus

OV

V=1

Overflow

NOV
EQ
NE

V=O
Z=1
Z=O

Equal
Not equal

GE

(8XORV)=0

Greater than or equal

LT
GT

(8 XORV)= 1
(Z OR (8 XORV))=O

Less than
Greater than

LE
UGE

(Z OR (8 XOR V))= 1

Less than or equal
Unsigned greater than or equal

1011

UGT

C=O
C=1
(C=O AND Z=O) = 1

0011

ULE

(CORZ)= 1

ULT

No overflow

Unsigned less than
Unsigned greater than
Unsigned less than or equal

n

NOTE. Asterisks
indicate condition codes that relate to two different mnemonics but test the same flags. For example, Z and EO are both True if the
Zero flag is set, but after an ADD instruction, Z would probably be used, while after a CP instruction, EO would probably be used.

123

Registers can be addressed by an 8·bit address in the range
of 0 to 255. Working registers can also be addressed using
4·bit addresses, where five bits contained in a register
pointer (R218 or R219) are concatenated with three bits
from the 4·bit address to form an 8·bit address.

Notation and Encoding

The instruction set notations are described in Table 5.
Functional Summary of Commands

Figure 8 shows the commands, and Figure 9 provides a
quick reference guide to the commands.

Registers can be used in pairs to generate 16·bit program or
data memory addresses.

Table 5. Instruction Set Notations
Notation

Meaning

Notation

Meaning

cc
r
rb
rO
R
RR

Condition code (see Table 4)
Working register (between 0 and 15)
Bit of working register
Bit 0 of working register
Register or working register
Register pair or working register pair (Register pairs
always start on an even·number boundary)
Indirect address
Indirect working register
Indirect register or indirect working register
Indirect working register pair
Indirect register pair or indirect working register pair
Indexed
Indexed, short offset
Indexed, long offset

DA
RA
1M
IML
dst
src

Direct address (between 0 and 65535)
Relative address
Immediate
Immediate long
Destination operand
Source operand
Indirect address prefix
Stack pointer
Program counter
Instruction pointer
Flags register
Register pointer
Immediate operand prefix
Hexadecimal number prefix
Opcode

IA
Ir
IR
Irr
IRR
X
XS
XL

@

SP
PC
IP
FLAGS
RP
#
%
OPC

One·Byte Instructions
OPC

I

dot

I OPC

I ~g~: ~~i.'s~~:i;; .E:~~.'~~r NEXT. NOP.

I INC
Two·Byte Instructions

OPC

dot

ore

I tg~:~~D.At~·sc:i:~~u~~~i:~~~~~~g~·

OPC

6rc

dst

I LOC, LDCPD, LOCPI. LDE, LDEPD, LOEPI

OPC

dot

1 ~t~~Lg~R~~~Rg~~~A'~~'~~,Cs'riA',Pi:6':'

ope

ore

I PUSH, SRP, SRPO, SRPt

ope

dot 1 b

ope

dst

101

1 b 1>1

BITe, BITR
BITS

r

lope

dst

I OJNZ

ee

lope

dot

1 JR

dot lope

ore

1 LO

ore lopc

dst

1 LO

Figure 7. Instruction Formats

124

2355·010

Three-Byte I structlons
ADC, ADO, AND, CP, LD, OR, PUSHUD,
PUSHUI, sac, SUB, TCM, TM, XOR

OPC

ds.

sre

OPC

re

ds.

ACC, ADO, AND, CP, DIV, LD, LOW, MULT,

OR, POPUO, POPUI, SBC, SUB, TCM, TM, XOR

OPC

ds.

bioi

sre

BAND, BCP, BOR, BXOR, LOB

OPC

sre

BAND, BOR, BTJRT, BXOR, LOB

Bre

b 1'1
bioi

dB'

OPC

ds'

BTJRF

OPC

are

da'

RA

CPIJE, CPIJNE

OPC

dB'

X

are

LC, LDC, LDE

dB'

LD, LDC, LDE

OPC

x

I
I

OPC

I OPC I

da

CALL

da.

JP
our"Byte I structlons

OPC

dst Ix¢Oor1!

OPC

src Ix¢Oor1

OPC

da'

OPC

sre

OPC

ds.

OPC

dst

OPC

I 0000
I 0000
I 000'
I 000.

sre

sre

LOC, LOE

da'

ds.

LOC, LOE

are

sre

LOC

dst

dsl

LOC

sre

sre

LOE

ds.

da.

LOE

are

da'

} FOR LOC, x = EVEN
FOR LDE, x = ODD

LOW

Figure 7. Instruction Formats (Continued)

INSTRUCTION SUMMARY

Instruction
and Operation
ADC dst,sre
, dst - dst + sre + C

AddrMode Opcode
Byte
dst src
(Hex)

Flags Affected
CZSVDH

Instruction
and Operation

AddrMode Opcode
Byte
dst src
(Hex)

o*

rO
Rb

rB
rO

07

-*OU--

o*

BTJRF
ilsre = 0, PC

RA

rb

37

------

= PC + dst

BTJRT
Ilsre = i, PC

rb

37

------

= PC + dsi
Rb
rO

27
27

-*OU--

F6
F4
D4

------

EF

*-----

BO
B1

------

10

***-

ADDdst,sre
dst - dst + sre

(Note 1)

00

* * * *

AND dst,sre
dst - dst AND sre

(Note 1)

BAND dst,sre
dst - dst AND sre

rO
Rb

Rb
rO

67
67

-* 0 U--

BXOR dst, sre
dst - dst XOR sre

rO
Rb

BCPdst, sre
dst - sre

rO

Rb

17

-* 0 U--

BITCdst
dst-NOTdst

rb

57

-*OU--

CALLdst
SP-SP - 2
@SP-PC
PC-dst

DA
IRR
IA

BITR dst
dst-O

rb

77

------

CCF
C = NOTC

BITS dst
dst-1

rb

77

------

CLR dst
dst-O

-**

C Z S V D H

BOR dst, sre
dst - dst OR sre

(Note 1)

50

Flag!! Affected

0--

RA

R
IR

Figure 8. Command Summary

125
-------~--~-~-~,-----'----~-

INSTRUCTION SUMMARY (Continued)

Instruction
and Operation

AddrMode Opcode
Byte
dst src
(Hex)

Flags Affected
C Z S V 0 H

COMdst
dst +- NOT dst

R
IR

60
61

-** 0--

CP dst,src
dst - src

(Note 1)

AD

*

CPIJE
if dst - src = O,then
PC+-PC + RA
Ir+-Ir + 1

Ir

C2

------

CPIJNE
if dst - src = O,then
PC+-PC + RA
Ir+-Ir + 1

Ir

02

* * *--

------

R
IR

40
41

* * *U--

DECds!
dst +- dst - 1

R
IR

00
01

-** *--

RR
IR

01
SMR (0)+-0
DIV dst, src
dst ~ src
dst (Upper) +Quotient
dst (Lower) +Remainder
DJNZr,dst
r+-r - 1
if r = 0
PC+-PC + dst

80
81

-* **--

8F

------

****--

RR
RR

R
IR

94
95

RR

1M

96
rA
(r=OtoF)

9F

ENTER
SP+-SP - 2
@SP+-IP
IP +- PC
PC +-@IP
IP+-IP+2

1F

EXIT
IP +-@SP
SP +-SP + 2
PC+-@IP
IP+-IP+2

2F

INCdst
dst +- dst + 1
R
IR

------

------

rE
-***-(r=Oto F)
20
21

CZSVDH

BF

Restored to
before interrupt

BF
IRET (Normal)
FLAGS +- @SP; SP +- SP + 1
PC +- @SP; SP +- SP + 2; SMR (0) +-1

Restored to
before interrupt

IRET(Fast)
PC"'IP
FLAG +- FLAG'
FIS +- 0

JRcc,dst
if cc is true,
PC+-PC + d
LD dst,src
dst +- src

OA
IRR
RA

r
R
r
IR
R
R
R
IR
IR

1M
R

IR
r
R
IR
1M
1M
R
x

ceO
(cc=OtoF)
30

------

ccB
(cc=Oto F)

------

rC
r8
r9
(r=OtoF)
C7
07
E4
E5
E6
06
F5
87
97

------

LOB dst, src
dst +- src

rO
Rb

Rb
rO

47
47

------

LDC/LDE
dst +- src

r
Irr

Irr

C3
03
E7
F7
A7
B7
A7
B7

------

xs
r
x1
r
OA

------

------

Flags Affected

-***--

RR
IR

x
RA

EI
SMR(0) .... 1

xs
r
x1
r
OA

LDCD/LDED dst, src
dst +- src
rr +- rr - 1

Irr

E2

------

LDEIILDCI dst, src
dst +- src
rr+-rr+1

Irr

E3

------

F2

------

LDCPD/LDEPD dst,src
rr +- rr - 1
Irr
dst +- src

Figure 8. Command Summary (Continued)

126

AddrMode Opcode
Byte
dst src
(Hex)
AD
A1

INCWdst
dst +-1 + dst

JPcc,dst
if cc is true,
PC+-dst

DAdst
dst +- OA dst

DECWdst
dst +- dst - 1

Instruction
and Operation

INSTRUCTION SUMMARY (Continued)

Instruction
and Operation

AddrMode Opcode
Byte
(Hex)
dst src

LDCPI/LDEPI dst, src
Irr
rr-rr + 1
dst-src

Flags Affected
CZSVDH

F3

------

C4
C5
C6

------

RR

RR
IR
IMM

RR
RR
RR

R
IR
1M

84
85
86

*0**--

NEXT
PC-@IP
IP-IP + 2

OF

------

NOP

FF

------

40

-0**--

LDWdst, src
dst-src
MULT dst, src

ORdst,src
dst - dst OR src

RR
RR

(Note 1)

POPdst
dst-@SP;
sp-sp + 1

R
IR

50
51

------

POPUD dst, src
dst-src
IR-IR -1

R

IR

92

------

POPUI dst, src
dst-src
IR-IR + 1

R

IR

93

------

PUSH src
SP - SP - 1; @SP - src

R
IR

70
71

------

PUSHUD dst, src
IR-IR -1
dst -src

IR

R

82

------

PUSHUI dst, src
IR -IR + 1
dst-src

IR

R

83

------

Instruction
and Operation

R
IR

RRdst
C-dst(O)
dst (7) - dst (0)
dst (N) - dst (N + 1)
N = Ot06

R
IR

EO
E1

****--

RRCdst
C-dst(O)
dst(7)-C
dst (N) - dst (N + 1)
N = Ot06

R
IR

CO
C1

****--

SBO
BANK-O

4F

------

SBl
BANK-1

5F

------

30

* * * *

DF

1-----

DO
D1

***0--

SBCdst,src
dst-dst - src - C

(Note 1)

SCF
C-1
SRAdst
dst (7) - dst (7)
C-dst(O)
dst (N) - dst (N + 1)
N = Ot06

R
IR

****--

1 *

1M

31

------

SRPO
RPO-IM

1M

31

------

1M

31

------

RET
PC-@SP;SP-SP+2

AF

------

SUBdst,src
dst - dst - src

RLdst
C-dst(7)
dst (0) - dst (7)
dst(N+1) -dst(N)
N = Ot06

90
91

****--

(Note 1)

20

{
10

SRPsrc
RPO-IM
RP1-IM + 8

SRPl
RP1-IM

R
IR

C Z S V D H

RLCdst
dst(O)-C
C-dst(7)
dst (N + 1) - dst (N)
N = Ot06

0-----

C,· 0

Flags Affected

10
11

CF

RCF

AddrMode Opcode
Byte
(Hex)
dst src

* * * *

1 *

Figure 8. Command Summary (Continued)

127

I

INSTRUCTION SUMMARY (Continued)

Instruction
and Operation

AddrMode Opcode
Byte
dst src
(Hex)
R
IR

FO
F1

-** U - -

TCM dst,src
(NOT dst) AND src

(Note 1)

60

-** 0 - -

TMdst,src
dstANDsrc

(Note 1)

XORdst,src
dst ..... dst XOR src

(Note 1)

dst

CZSVDH

SWAPdst
dst (0-3) - dst (4-7)

WFI

AddrMode

Flags Affected

70

-** 0 - -

3F

------

BO

-**0--

Lower
Opcode Nibble

lID

Ir

NOTE· These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble Identifies
the command, and is found in the table above. The second nibble,
represented by a 0, defines the addressing mode as follows:

rn
m

R

R

R

IR

lID

R

1M

[[J

For example, to use an opcode represented as xD with an "RR"
addressing mode, use the opcode "x4."

o
1

*
U

=
=
=
=
=

Cleared to Zero
Set to One
Unaffected
Set or reset, depending on result of operation_
Undefined

Figure 8. Command Summary (Continued)

128

src

SUPER-8 OPCODE MAP
Lower Nibble (Hex)

o
o

2

2

3

4

6,5

6,5

6,5

6,5

10,5

DEC

DEC

ADD

ADD

ADD

R,

IR,

'1"2

'l, lr2

R2,R,

ADD

BOR'

LO

LO

OJNZ

JR

R"IM

rO·Rb

r"R2

r2,Rl

r"RA

cc,RA

6,5

12110,515 12110,0

C

o

E

F

6,5

12110,0

6,5

14,0

LO

JP

INC

r"IM

cc,DA

r1

NEXT
-

6,5

6,5

6,5

10,5

10,5

10,5

10,2

20,0

RLC

AOC

AOC

AOC

AOC

AOC

BCP

ENTER

r"b,R2

R,

IR,

'1,(2

r" lr2

R2,R,

IR2,R,

R"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

BXOR'

R,

IR,

'1,'2

'l, Ir2

R2,R,

IR2,R,

R"IM

'O·Rb

6,5

6,5

10,5

10,5

10,5

JP

NOTE
C

SBC

SBC

SBC

SBC

SBC

'1,(2

'l, lr2

R2,R,

IR2,R,

R"IM

-

22,0

EXIT

~

NOTE

WFI

A

-

6,5

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

OA

OA

OR

OR

OR

OR

OR

LOB'

R,

IR,

'1,(2

'l, lr2

R2,R,

IR2,R,

rO·Rb

10,5

10,5

6,5

6,5

10,5

10,5

R IM
"
10,5

8,5

6,5

POP

POP

AND

AND

AND

AND

AND

BITC

SBI

R,

IR,

'1,'2

'l,lr2

R2,R,

IR2,R,

R"IM

r"b

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM

COM

TCM

TCM

TCM

TCM

TCM

R,

IR,

'1,'2

r" lr2

R2,R,

IR2,R,

R"IM

ro·Rb

10112,0

12114,0

6,5

6,5

10,5

10,5

10,5

PUSH

PUSH

TM

TM

TM

TM

TM

NOTE

R2

IR2

'1,(2

r" lr2

R2,R,

IR2,R,

R"IM

10,9

10,9

10,5

10,5

24,5

24,5

24,5

10,5

MULT

MULT

LO

IR2,RR,

IM,RR,

fl,X,R2

4

5

6

OECW

9

OECW PUSHUO PUSHUI MULT

RR,

IR,

6,5

6,5

RL

RL

R,

IR,

IR2,R,

IR R2
"
10,5

IR"R2
10,5

POPUO POPUI

R2,RR,

28112,510 28112,510 28112,510

LO

IR2,R1

R2,RR,

IR2,RR,

IM,RR,

r2,x,R,

10,9

6,5

6,5

10,5

10,5

10,5

CP

CP

CP

CP

CP

RR,

IR,

'l,r2

'l, lr2

R2,R ,

IR2,R,

R"IM

C

o

10,5

6,5

6,5

6,5

CLR

XOR

XOR

XOR

XOR

XOR

R,

IR,

'1,'2

'l, lr2

R2,R,

IR2,R,

10,5

6,5

LO

6,5

6,5

16118,5

12,0

10,5

10,5

RRC

RRC

CPIJE

LOC'

LOW

LOW

LOW

R,

IR,

Ir,r2,RA

'l, lrr2

16118,5

12,0

6,5

6,5

SRA

CPIJNE LOC'

RR2,RR, IR2,RR, RR"IML

IRET

'----s:s
RCF

-

10,5

6,5

6,5

LO

LO

SCF

IR"IM

Ir1"2

'2, lrr 1

IA,

16,0

16,0

10,5

10,5

10,5

18,0

RR

RR

LOCO'

LOCI'

LO

LO

LO

LOC'

R,

IR,

'l, lrr2

fl, Irr2

R2,R,

IR2,R,

R"IM

'l,lrr2,xs

8,7

8,7

16,0

16,0

18,0

10,5

18,0

18,0

CALL

LO

CALL

LOC'

IRR,

R2, IR ,

DA,

'2, lrrl,xs

'2, lrr2

16i6,OI1

20,0

Ir"r2,RA

'2, lrr2

14,0

RET

CALL

IR,

IR,

-

'1,1'2

6,5

R,

EI

E

R,

SWAP LOCPO' LOCPI'

6,1

NOTE

6,5

SWAP

6,1
01

r---

0

6,5

R IM
"
12,5

-

e6,5

CCF

t t

t t t

~
NOP

Bytes per
Instruction

NOTE A

NOTEB

NOTEC

Legend:
r = 4·blt address
R = 8·bIt address
b = bit number
R1 orr1 = dst address

R2 or '2

NOTED

NOTEE

= src address

'Examples:
BOR rO·R2
IS BOR r, ,b,R2
or BOR r2,b,R,
LDCr"lrr2
IS LOC'l ,lrr2 = program
or LDE r"lrr2 = data

Sequence:
Opcode, first, second, third operands
NOTE The blank areas are not defined

Figure 9. Opcode Map
2355·011

I
j

-

NOTE

CLR

SRA

E

10,5

-

10,5

DIY

INCW

-

B

DIY

10,9

SBO

BAND'

DIY

INCW

B

F

ADD
IR2,R,

6,5

6,5

IRR,

A

B

7
10,5

RLC

10,0

3

9

A

6
10,5

10,5

129

INSTRUCTIONS
Table 6. Super-a Instructions
Mnemonic

Operands

Load Instructions
CLR
dst
LD
dst, src
LDB
dst, src
LDC
dst, src
LDE
dst, src
LDCD
dst, src
LDED

dst, src

LDCI

dst, src

LDEI
LDCPD

dst, src
dst, src

LDEPD

dst, src

LDCPI

dst, src

LDEPI

dst, src

LDW
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI

dst, src
dst
dst, src
dst, src
src
dst, src
dst, src

Instruction

Clear
Load
Load bit
Load program memory
Load data memory
Load program memory and
decrement
Load data memory and
decrement
Load program memory and
increment
Load data memory and increment
Load program memory with
pre-decrement
Load data memory with
pre-decrement
Load program memory with
pre-increment
Load data memory with
pre-increment
Load word
Pop stack
Pop user stack (decrement)
Pop user stack (increment)
Push stack
Push user stack (decrement)
Push user stack (increment)

Arithmetic Instructions
ADC
dst, src
ADD
dst, src
CP
dst, src
DA
dst
DEC
dst
DECW
dst
DIV
dst, src
INC
dst
INCW
dst
dst, src
MULT
dst, src
SBC
SUB
dst, src

Add with carry
Add
Compare
Decimal adjust
Decrement
Decrement word
Divide
Increment
Increment word
Multiply
Su btract with carry
Subtract

Logical Instructions
AND
dst, src
COM
dst
OR
dst, src
XOR
dst, src

Logical AND
Complement
Logical OR
Logical exclusive

130

Mnemonic

Operands

Instruction

Program Control Instructions
BTJRT
dst, src
Bit test jump relative on True
BTJRF
dst, src
Bit test jump relative on False
CALL
dst
Call procedure
CPIJE
dst, src
Compare, increment and jump on
equal
CPIJNE
dst, src
Compare, increment and jump on
non-equal
Decrement and jump on non-zero
DJNZ
r, dst
ENTER
Enter
EXIT
Exit
IRET
Return from interrupt
JP
cc, dst
Jump
JR
cc, dst
Jump relative
NEXT
Next
RET
Return
WFI
Wait for interru pt
Bit Manipulation Instructions
BAND
dst, src
Bit AND
BCP
dst, src
Bit compare
BITC
Bit complement
dst
BITR
Bit reset
dst
BITS
Bit set
dst
BOR
dst, src
Bit OR
BXOR
dst, src
Bit exclusive OR
Test complement under mask
TCM
dst, src
dst, src
Test under mask
TM
Rotate and Shift Instructions
RL
dst
Rotate left
Rotate left through carry
RLC
dst
Rotate right
RR
dst
Rotate right through carry
RRC
dst
Shift right arithmetic
SRA
dst
Swap nibbles
SWAP
dst
CPU Control Instructions
CCF
DI
EI
NOP
RCF
SBO
SB1
SCF
SRP
src
SRPO
src
SRP1
src

Complement carry flag
Disable interrupts
Enable interrupts
Do nothing
Reset carry flag
Set bankO
Set bank 1
Set carry flag
Set register pointers
Set register pointer zero
Set register pointer one

INTERRUPTS
The Super-S interrupt structure contains Sleveis of interrupt,
16 vectors, and 37 sources.

The vector number is used to generate the address of a
particular interrupt servicing routine; therefore all interrupts
using the same vector must use the same interrupt handling
routine.

Interrupt priority is assigned by level, controlled by the
Interrupt Priority register (IPR). Each level is masked (or
enabled) according to the bits in the Interrupt Mask register
(IMR), and the entire interrupt structure can be disabled by
clearing a bit in the System Mode register (R222).

Levels
Levels provide the top level of priority assignment. While the
sources and vectors are hardwired within each level, the
priorities of the levels can be changed by using the Interrupt
Priority register (see Figure 5 for bit details).

The three major components of the interrupt structure are
sources, vectors, and levels. These are shown in Figure 10
and discussed in the follOWing paragraphs.

Sources
A source is anything that generates an interrupt. This can be
internal or external to the Super-S. Internal sources are
hardwired to a particular vector and level, while external
sources can be assigned to various external events.

Vectors

If more than one interrupt source is active, the source from
the highest priority level will be serviced first. If both sources
are from the same level, the source with the lowest vector will
have priority. For example, if the UART Receive Data bit and
UART Parity Error bit are both active, the UART Parity Error
bit will be serviced first because it is vector 16, and UART
receive data is vector 20.

100
",

The levels are shown in Figure 10.

="'IiI

P0l'NG

112

EXTERNAL INTERRUPT (P27)
I

~:~~~~:LKI~~~:~~~i ~24) I
~:~~:~:LKI~~~;~~~i (~34) I

EXTeRNAL INTERRUPT (P3s)

--,VECTORS

INTERRUPT SOURCES
COUNTER 0 ZERO COUNT
EXTERNAL INTERRUPT (P26)

EXTERNAL INTERRUPT (P25)

I
I

114

lEVELS

:;;2
I

I
I
IIRQS

i
I

I
I
I
I

1 28

,'RQO

II

I
I
I

I
I

I

I
I

I

~13O

I'RQ7
I

I
I

·SYNC CHAN RECEIVE OVERRUN
*SVNC CHAN FRAMING ERROR
·SYNC CHAN PARITY ERROR
·SYNC CHAN BREAK/ABORT DETECT

IRa3

·SYNC CHAN SYNc/eTl CHAR DETECT
·SYNC CHAN END OF FRAME

• SYNC CHAN RECEIVE DATA
EXTERNAL INTERRUPT (P32)

• SYNC CHAN ZERO COUNT
EXTERNAL INTERRUPT (P22)
·SYNC CHAN TRI\NSMIT UNDERRUN

EXTERNAL INTERRUPT (P2:.d
TRANSMIT DATA
EXTERNAL INTERRUPT (P33)

* SYNC CHAN

8

!

,'RQO

10

UART RECEIVE OVERRUN
UART FRAMING ERROR
UART PARITY ERROR
UART WAKEUP DETECT
UART BREAK DETECT
UART CONTROL CHAR DETECT

16

UART RECEIVE DATA
EXTERNAL INTERRUPT (P30)

20

EXTERNAL INTERRUPT (P20)

22

UART ZERO COUNT
EXTERNAL INTERRUPT (P2,)
UART TRANSMIT DATA
EXTERNAL INTERRUPT (P3,)

I
!
I
I

18

IROG

24

!

26

!

I

IRQ1

I
I
I

·Not currently available,

Figure 10. Interrupt Levels and Vectors

2355·012

...

I:

The 16 vectors are divided unequally among the eight
levels. For example, vector 12 belongs to level 2, while level
3 contains vectors 0,2,4, and 6.

COUNTER 1 ZERO COUNT
EXTERNAL INTERRUPT (P3,)
EXTeRNAL INTERRUPT (P37)

fill

II

131

Enables
Interrupts can be enabled or disabled as follows:
•

Interrupt enable/disable. The entire interrupt structure
can be enabled or disabled by setting bit 0 in the System
Mode register (R222).

•

Level enable. Each level can be enabled or disabled by
setting the appropriate bit in the Interrupt Mask register
(R221).

•

Level priority. The priority of each level can be controlled
by the values in the Interrupt Priority register (R255, Bank
0).

• Source enable/disable. Each interrupt source can be
enabled or disabled in the sources' Mode and Control
register.

Two hardware registers support fast interrupts. The
Instruction Pointer (lP) holds the starting address of the
service routine, and saves the PC value when a fast interrupt
occurs. A dedicated register, FLAG', saves the contents of
the FLAGS register when a fast interrupt occurs.
To use this feature, load the address of the service routine in
the Instruction Pointer, load the level number into the Fast
Interrupt Select field, and turn on the Fast Interrupt Enable
bit in the System Mode register.
When an interrupt occurs in the level selected for fast
interrupt processing, the following occurs:
• The contents of the Instruction Pointer and Program
Counter are swapped.
• The contents of the Flag register are copied into FLAG:
• The Fast Interrupt Status Bit in FLAGS is set.

Routine
Before an interrupt request can be granted, a) interrupts
must be enabled, b) the level must be enabled, c) it must be
the highest priority interrupting level, d) it must be enabled at
the interrupting source, and e) it must have the highest
priority within the level.
If all this occurs, an interrupt request is granted.
The Super-8 then enters an interrupt machine cycle that
completes the following sequence:

• It resets the Interrupt Enable bit to disable all subsequent
interrupts.
•

It saves the Program Counter and status flags on the
stack.

• It branches to the address contained within the vector
location for the interrupt.
• It passes control to the interrupt servicing routine.
When the interrupt servicing routine has serviced the
interrupt, it should issue an interrupt return (IRET)
instruction. This restores the Program Counter and status
flags and sets the Interrupt Enable bit in the System Mode
register.

Fast Interrupt Processing
The Super-8 provides a feature called fast interrupt
processing, which completes the interrupt servicing in 6
clock periods instead of the usual 22.

132

• The interrupt is serviced.
• When IRET is issued after the interrupt service outline is
completed, the Instruction Pointer and Program Counter
are swapped again.
• The contents of FLAG' are copied back into the Flag
register.
• The Fast Interrupt Status bit in FLAGS is cleared.
The interrupt servicing routine selected for fast processing
should be written so that the location after the IRET
instruction is the entry point the next time the (same) routine
is used.

Level or Edge Triggered
Because internal interrupt requests are levels and interrupt
requests from the outside are (usually) edges, the hardware
for external interrupts uses edge-triggered flip-flops to
convert the edges to levels.
The level-activated system requires that interrupt-serving
software perform some action to remove the interrupting
source. The action involved in serving the interrupt may
remove the source, or the software may have to actually
reset the flip-flops by writing to the corresponding Interrupt
Pending register.

STACK OPERATION
The Super-8 architecture supports stack operations in the
register file or in data memory. Bit 1 in the external Memory
Timing register (R254 bank 0) selects between the two.
Register pair 216-217 forms the Stack Pointer used for all
stack operations. R216 is the MSB and R217 is the LSB.
The Stack Pointer always points to data stored on the top of
the stack. The address is decremented prior to a PUSH and
incremented after a POP.
The stack is also used as a return stack for CALLs and
Interrupts. During a CALL, the contents of the PC are saved
on the stack, to be restored later. Interrupts cause the
contents of the PC and FLAGS to be saved on the stack, for
recovery by IRET when the interrupt is finished.

be used as a general-purpose register, but its contents will
be changed if an overflow or underflow occurs as the result
of incrementing or decrementing the stack address during
normal stack operations.
User-Defined Stacks
The Super-8 provides for user-defined stacks in both the
register file and program or data memory. These can be
made to increment or decrement on a push by the choice of
opcodes. For example, to implement a stack that grows
from low addresses to high addresses in the register file, use
PUSHUI and POPUD. For a stack that grows from high
addresses to low addresses in data memory, use LDEI for
pop and LDEPD for push.

When the Super-8 is configured for an internal stack (using
the register file), R217 contains the Stack Pointer. R216 may

COUNTER/TIMERS
The Super-8 has two identical independently
programmable 16-bit counter/timers that can be cascaded
to produce a single 32-bit counter. They can be used to
count external events, or they can obtain their input
internally. The internal input is obtained by dividing the
crystal frequency by four.
The counter/timers can be set to count up or down, by
software or external events. They can be set for single or
continuous cycle counting, and they can be set with a
bi-value option, where two preset time constants alternate in
loading the counter each time it reaches zero. This can be
used to produce an output pulse train with a variable duty
cycle.

The counter/timers can also be programmed to capture the
count value at an external event or generate an interrupt
whenever the count reaches zero. They can be turned on
and off in response to external events by using a gate and/or
a trigger option. The gate option enables counts only when
the gate line is Low; the trigger option turns on the counter
after a transient High. The gate and trigger options used
together cause the counter/timer to work in gate mode after
initially being triggered.
The control and status register bits for the counter/timers are
shown in Figure 5.

ABSOWTE MAXIMUM RATINGS
Voltage on all pins with respect
to ground ....................... - 0.3V to + 7.0V
Ambient Operating
Temperature ..............See Ordering Information
Storage Temperature .............. - 65°C to + 150°C

Stresses greater than these may cause permanent damage to the device.
This is a stress rating only; operation of the device under conditions more
severe than those listed for operating conditions may cause permanent
damage to the device. Exposure to absolute maximum ratings for
extended periods may also cause permanent damage.

STANDARD TEST CONDITIONS
Figure 11 shows the setup for standard test conditions. All
voltages are referenced to ground, and positive current
flows into the reference pin.

+5V
lK

Standard conditions are:
•

+4.75V,.. ."',.. . . . ,.. .I),.~

6

5

•

3

2

't"b,."

,.~

1 44 43 42 41 40

ClK

7

3.

A,

D.

8

38

A,

37

A,

36

A,

35

A,

0,

•,.

D.

11

NC

12

+5V

13

0,

Z8400
Z80CPU

3.

AO
GND

32

RFSH

0,

,.

33

0,

15

31

M1

DO
0,

16

3'

RESET

2.

BUSREQ

17
18 19 20 21 22 23 24 25 26 27 28

Figure 2b. 44-Pin Chip Carrier Pin Assignments

GENERAL DESCRIPTION
The Z80, Z80A, Z808, and Z80H CPUs are third-generation
single-chip microprocessors with exceptional computational power. They offer higher system throughput and more
efficient memory utilization than comparable second- and
third-generation microprocessors. The internal registers
contain 208 bits of readlwrite memory that are accessible to
the programmer. These registers include two sets of six
general-purpose registers which may be used individually
as either 8-bit registers or as 16-bit register pairs. In addition,
there are two sets of accumulator and flag registers. A group
of "Exchange" instructions makes either set of main or
alternate registers accessible to the programmer. The
alternate set allows operation in foreground-background
mode or it may be reserved for very fast interrupt response.

The Z80 also contains a Stack Pointer, Program Counter, two
index registers, a Refresh register (counter), and an
Interrupt register. The CPU is easy to incorporate into a
system since it requires only a single + 5V power source. All
output signals are fully decoded and timed to control
standard memory or peripheral circuits; the CPU is
supported by an extensive family of peripheral controllers.
The internal block diagram (Figure 3) shows the primary
functions of the Z80 processors. Subsequent text provides
more detail on the Z80 1/0 controller family, registers,
instruction set, interrupts and daisy chaining, and CPU
timing.

+5V'"
GND ...
CLOCK ...

CPU

TIMING

Figure 3.

142

zao CPU Block Diagram
2001·003.004

Z80 MICROPROCESSOR FAMILY
The Zilog zao microprocessor is the central element of a
comprehensive microprocessor product family. This family
works together in most applications with minimum
requirements for additional logic, facilitating the design of
efficient and cost-effective microcomputer-based systems.
Zilog has designed five components to provide extensive
support for the zao microprocessor. These are:
• The PIO (Parallel Input/Output) operates in both
data-byte I/O transfer mode (with handshaking) and in bit
mode (without handshaking). The PIO may be
configured to interface with standard parallel peripheral
devices such as printers, tape punches, and keyboards.
• The CTC (Counter/Timer Circuit) features four programmable a-bit counter/timers, each of which has an

a-bit prescaler. Each. of the four channels may be
configured to operate in either counter or timer mode.
• The DMA (Direct Memory Access) controller provides
dual port data transfer operations and the ability to
terminate data transfer as a result of a pattern match.
• The SIO (Serial Input/Output) controller offers two
channels. It is capable of operating in a variety of
programmable modes for both synchronous and
asynchronous communication, including Bi-Synch and
SDLC.
• The DART (Dual Asynchronous ReceiveriTransmitter)
device provides low cost asynchronous serial
communication. It has two channels and a full modem
control interface.

Z80 CPU REGISTERS
Figure 4 shows three groups of registers within the zao
CPU. The first group consists of duplicate sets of a-bit
registers: a principal set and an alternate set (designated by
, [prime], e.g., A~. Both sets consist of the Accumulator
Register, the Flag Register, and six general-purpose
registers. Transfer of data between these duplicate sets of
registers is accomplished by use of "Exchange"
instructions. The result is faster response to interrupts and
easy, efficient implementation of such versatile pro-

gramming techniques as background-foreground data
processing. The second set of registers consists of six
registers with assigned functions. These are the I (Interrupt
Register), the R (Refresh Register), the IX and IY (Index
Registers), the SP (Stack Pointer), and the PC (Program
Counter). The third group consists of two interrupt status
flip-flops, plus an additional pair of flip-flops which assists in
identifying the interrupt mode at any particular time. Table 1
provides further information on these registers.
ALTERNATE REGISTER SET

MAIN REGISTER SET

A

ACCUMULATOR

F

FLAG REGISTER

A'

ACCUMULATOR

F'

FLAG REGISTER

B

GENERAL PURPOSE

C

GENERAL PURPOSE

B'

GENERAL PURPOSE

C'

GENERAL PURPOSE

0

GENERAL PURPOSE

E

GENERAL PURPOSE

D'

GENERAL PURPOSE

E'

GENERAL PURPOSE

H

GENERAL PURPOSE

l

GENERAL PURPOSE

H'

GENERAL PURPOSE

l'

GENERAL PURPOSE

__- - - 8 BITS - - - .

__- - - - - - - 1 6 B I T S - - - - - - - - _

INTERRUPT

G
~

IX INDEX REGISTER

4~ :

IV INDEX REGISTER

FLlp·FLOPS

STATUS

GSTORES IFF1

INTERRUPTS DISABLED

DURING NMI

INTERRUPTS ENABLED

SERVICE

SP STACK POINTER
INTERRUPT MODE FlIp·FlOPS

PC PROGRAM COUNTER

I INTERRUPT VECTOR

•

I

INTERRUPT MODE a
NOT USED
INTERRUPT MODE 1
INTERRUPT MODe 2

A MEMORY REFRESH

8BITS---"

Figure 4. CPU Registers

2001·005

143

Z80 CPU REGISTERS

(Continued)
Table 1. zao CPU Registers

Register

Size (Bits)

Remarks
Stores an operand or the results of an operation.

A,A'

Accumulator

8

F,F'

Flags

8

See Instruction Set.

B,B'

General Purpose

8

Can be used separately or as a 16-bit register with C.

C,C'

General Purpose

8

See B, above.

0,0'

General Purpose

8

Can be used separately or as a 16-bit register with E.

E, E'

General Purpose

8

See 0, above.

H, H'

General Purpose

8

Can be used separately or as a 16-bit register with L.

L,L'

General Purpose

8

See H, above.

I

Note: The (B,C), (D,E), and (H,L) sets are combined as follows:
B - High byte
C - Low byte
0- High byte
E - Low byte
H - High byte
L - Low byte
Interrupt Register

8

Stores upper eight bits of memory address for vectored interrupt
processing.

R

Refresh Register

8

Provides user-transparent dynamic memory refresh. Automatically
incremented and placed on the address bus during each
instruction fetch cycle.

IX

Index Register

16

Used for indexed addressing.

IV

Index Register

16

Used for indexed addressing

SP

Stack Pointer

16

Holds address of the top of the stack. See Push or Pop in instruction
set.

PC

Program Counter

16

IFF,-IFF2

Interrupt Enable

Flip-Flops

Set or reset to indicate interrupt status (see Figure 4).

Holds address of next instruction.

IMFa-IMFb

Interrupt Mode

Flip-Flops

Reflect Interrupt mode (see Figure 4).

INTERRUPTS: GENERAL OPERATION
The CPU accepts two interrupt input signals: NMI and INT.
The NMI is a non-maskable interrupt and has the highest
priority. INT is a lower priority interrupt and it requires that
interrupts be enabled in software in order to operate. INT
can be connected to multiple peripheral devices in a
wired-OR configuration.

The CPU services interrupts by sampling the NMI and INT
signals at the rising edge of the last clock of an instruction.
Further interrupt service processing depends upon the type
of Interrupt that was detected. Details on interrupt responses
are shown in the CPU Timing Section.

The zao has a single response mode for interrupt service for
the non-maskable interrupt. The maskable interrupt, INT,
has three programmable response modes available. These
are:

interrupt cannot be disabled by program control and
therefore will be accepted at all times by the CPU. NMI is
usually reserved for servicing only the highest priority type
interrupts, such as that for orderly shutdown after power
failure has been detected. After recognition of the NMI
signal (providing BUSREQ is not active), the CPU jumps to
restart location 0066H. Normally, software starting at this
address contains the interrupt service routine.

•

Mode 0 - similar to the aoao microprocessor.

•

Mode 1 - Peripheral Interrupt service, for use with
non-aOaO/ZaO systems.

•

Mode 2 - a vectored interrupt scheme, usually
daisy-chained, for use with zao Family and compatible
peripheral devices.

144

Non-Maskable Interrupt (NMI). The nonmaskable

Maskable Interrupt (I NT). Regardless of the interrupt
mode set by the user, the zao response to a maskable
interrupt input follows a common timing cycle. After the

interrupt has been detected by the CPU (provided that
interrupts are enabled and BUSREO is not active) a special
interrupt processing cycle begins. This is a special fetch
(M1) cycle in which IORO becomes active rather than
MREO, as in a normal M1 cycle. In addition, this special M1
cycle is automatically extended by two WAIT states, to allow
for the time required to acknowledge the interrupt request.

Mode 0 Interrupt Operation. This mode is similar to the
8080 microprocessor interrupt service procedures. The
interrupting device places an instruction on the data bus.
This is normally a Restart instruction, which will initiate a call
to the selected one of eight restart locations in page zero of
memory. Unlikethe8080, the Z80 CPU responds to the Call
instruction with only one interrupt acknowledge cycle
followed by two memory read cycles.
~ration. Mode 1 operation is very
similar to that for the NMI. The principal difference is thatthe
Mode 1 interrupt has only one restart location, 0038H.

Mode 1 Interrupt

level. The first device has highest priority, while each
succeeding device has a corresponding lower priority. This
arrangement permits the CPU to select the highest priority
interrupt from several· simultaneously interrupting
peripherals.
The interrupting device disables its lEO line to the next lower
priority peripheral until it has been serviced. After servicing,
its lEO line is raised, allowing lower priority peripherals to
demand interrupt servicing.
The Z80 CPU will nest (queue) any pending interrupts or
interrupts received while a selected peripheral is being
serviced.

Interrupt Enable/Disable Operation. Two flip-flops, IFF,
and IFF2, referred to in the register description, are used to
signal the CPU interrupt status. Operation of the two
flip-flops is described in Table 2. For more details, refer to the
Z80 CPU Technical Manual (03-0029-01) and zao Assembly
Language Programming Manual (03-0002-01).

Mode 2 Interrupt Operation. This interrupt mode has
been designed to utilize most effectively the capabilities of
the Z80 microprocessor and its associated peripheral
family. The interrupting peripheral device selects the starting
address of the interrupt service routine. It does this by
placing an 8-bit vector on the data bus during the interrupt
acknowledge cycle. The CPU forms a pointer using this byte
as the lower 8 bits and the contents of the I register as the
upper 8 bits. This points to an entry in a table of addresses
for interrupt service routines. The CPU then jumps to the
routine at that address. This flexibility in selecting the
interrupt service routine address allows the peripheral
device to use several different types of service routines.
These routines may be located at any available location in
memory. Since the interrupting device supplies the
low-order byte of the 2-byte vector, bit 0 (Ao) must be a zero.

Interrupt Priority (Daisy Chaining and Nested
Interrupts). The interrupt priority of each peripheral device
is determined by its physical location within a daisy-chain
configuration. Each device in the chain has an interrupt
enable input line (lEI) and an interrupt enable output line
(lEO), which is fed to the next lower priority device. The first
device in the daisy chain has its lEI input hardwired to a High

Table 2. State of Flip-Flops
Action

Comments

IFF1

IFF2

CPU Reset

0

0

Maskable Interrupt
INT disabled

01 instruction execution

0

0

Maskable interrupt
INT disabled

EI instruction execution

Maskable interrupt
INTenabled

LO A,I instruction execution

IFF2 -+ Parity flag

LO A,R instruction execution
AcceptNMI

0

RETN instruction execution

IFF2

IFF,

IFF2 -+ Parity flag
IFF, -+ IFF2
(Maskable interrupt
INT disabled)
IFF2 -+ IFF, at
completion of an
NMI service
routine.

145

INSTRUCTION SET
The Z80 microprocessr has one of the most powerful and
versatile instruction sets available in any 8-bit microprocessor. It includes such unique operations as a block
move for fast, efficient data transfers within memory, or
between memory and I/O. It also allows operations on any
bit in any location in memory.
The following is a summary of the Z80 instruction set which
shows the assembly language mnemonic, the operation,
the flag status, and gives comments on each instruction. For
an explanation of flag notations and symbols for mnemonic
tables, see the Symbolic Notations section which follows
these tables. The Z80 CPU Technica/ Manual (03-0029-01),
the Programmer's Reference Guide (03-0012-03), and
Assembly Language Programming Manual (03-0002-01)
contain significantly more details for programming use.
The instructions are divided into the following categories:

o Rotates and shifts
o Bit set, reset, and test operations
o Jumps
o Calls, returns, and restarts
o Input and output operations
A variety of addressing modes are implemented to permit
efficient and fast data transfer between various registers,
memory locations, and input/output devices. These
addressing modes include:
o Immediate
o Immediate extended
o Modified page zero
o Relative

o 8-bit loads

o Extended

o 16-bit loads

0 Indexed

o Exchanges, block transfers, and searches

0 Register

o 8-bit arithmetic and logic operations

0 Register indirect

o General-purpose arithmetic and CPU control

0 Implied

o 16-bit arithmetic operations

0

Bit

a·BIT LOAD GROUP

Mnemonic

LOr, r'
LOr, n

Symbolic
Operation

rs

t

X

X

P

0

0

ORs

A+-A>s

X

0

X

P

0

0

XORs

A +-AEils

X

0

X

P

0

0

CPs

A-s

X

t

X

V

ADCA,s
SUBs

X

X

t

10011

s is any 01 r, n,

10101

(HL), (IX + d),

[QD]
11001

(IY+d) as
shown lor ADD

illQJ

instruction. The

[lQIJ
[JJJJ

indicated bits
replace the
10001 inthe
ADD set above.

150

8·BIT ARITHMETIC AND LOGICAL GROUP (Continued)

Mnemonic
INCr
INC (HL)
INC(IX+d)

Symbolic
Operation
r-r+1
(HL)(HL)+1
(IX+d)(IX+d)+1

INC (IY+d)

(IY+d)(IY+d)+1

DECm

m-m-1

NOTE:

Flags
H
PNN C

S Z

* *

X

X V 0

·

X
X

X V 0
X V 0

•
•

X V 0

•

X V

•

X

*

X

1

76
00

Opcode
543 210 Hex
r

No. of No. of M No. ofT

Bytes

Cycles

States

Comments

4

11001

00
11
00

110 11001
011 101 DD
110 11001
-d'"
11 111 101 FD
00 110 11001
-d-

3

3
6

11
23

3

6

23

ITQI]

N

* * *
m is any of r, (HL), (IX + d), (IV + d) as shown for INC. DEC same format and states as INC. Replace [!QQ] With [IQI] In opcode

=

Q

GENERAL-PURPOSE ARITHMETIC AND CPU CONTROL GROUPS

Mnemonic

Symbolic
Operation

DAA

@

CPL

A-A

NEG

A-O-A

CCF

CY-CY

SCF
NOP
HALT

CY-1
No operation
CPU halted
IFF-O
IFF-1
Set interrupt
mode 0
Set interrupt
mode 1
Set interrupt
mode 2

DI*
EI*
IMO
1M 1
1M2
NOTES:

Flags
H
PNN C

S Z

• •

* *

X

X P

X

X

X

*

•

·

X V

1

0

States
4

•

00

101

111

2F

4

*

11
01

101
000

101
100

ED
44

00

111

111

3F

00
00
01
11
11
11
01
11
01
11
01

110 111
000 000
110 110
110 011
111 011
101 101
000 110
101 101
010 110
101 101
011 110

37
00
76
F3
FB
ED
46
ED
56
ED
5E

0

•

X
X
X
X
X
X

•

X
X
X
X
X
X

•
•
•
•
•
•

• •

X

•

X

• • •

·•

X

•

X

• • •

•
•

Cycles

27

•
•
•
•
•
•

•

Bytes

111

·

0

•
•
•
•
•

No. of No. of M No. ofT

100

X X X

•
•
•
•

Opcode
543 210 Hex

00

··
•
•

76

c:I

•
•
•
•
•

2

8

.1

4

2

4
4
4
4
4
2

2

8

2

2

8

2

2

8

Comments
Decimal adjust
accumulator.
Complement
accumulator
(one's
complement).
Negateacc.
(two's
complement).
Complement
carry flag.
Set carry flag.

converts accumulator content into packed BCD following add or subtract with packed BCD operands.
IFF indicates the interrupt enable flip-flop.
CV indicates the carry flip-flop.
indicates interrupts are not sampled at the end of EI or 01
@

*

151

16-BIT ARITHMETIC GROUP

Mnemonic

Symbolic
Operation

S Z

ADD HL, ss

HL - HL+ss

• •

ADCHL, ss

HLHL+ss+CY

SBCHL,ss

Flags

* *

HLHL-ss-CY

PNN C

H
X

X

X

•

X

X

X

V 0

X

X

X

V

0

*

ADD IX, pp

IX-IX+pp

• •

X

X

X

•

0

ADDIY,rr

IY-IY+rr

·

•

X

X

X

•

0

INCss
INC IX

ss - ss+ 1
IX-IX+1

• •
• •

X
X

•
•

X
X

• • •
• • •

INCIY

IY-IY+1

• •

X

•

X

• • •

DECss

ss-ss-1
IX-IX-1

• •
• •

X
X

•
•

X

DEC IX

X

• • •
• • •

DECIY

IY-IY-1

• •

X

•

X

• • •

76

Opcode
543 210 Hex

00

ssJ

001

11
01

101
ss1

101
010

ED

11
01
11
01

101
ssO
011
pp1

101
010
101
001

11

111
rr1
ssO
011
100
111
100
ss1
011
101
111
101

101
001
011
101
011
101
011
011
101
011
101
011

00
00
11
00
11
00
00
11
00
11
00

No,. of No. of M No. otT
Bytes Cycles States Comments
3

11

2

4

15

ED

2

4

15

DO

2

4

15

FD

2

4

15

1
2

1
2

10

2

2

10

DO
23
FD
23
DO
2B
FD
2B

6

1

1

6

2

2

10

2

2

10

ss
00
01
10
11

Reg.
BC
DE
HL
SP

pp
00
01
10

Reg.
BC
DE
IX
SP
Reg.
BC
DE
IY
SP

11
rr
00
01
10
11

ROTATE AND SHIFT GROUP
Symbolic
Mnemonic Operation

RLCA

RLA

Flags

S Z

PNN C

H

§]~ • •

X

0

X

•

0

L§J=--t§P • •

X

0

X

•

0

~

• •

X

0

X

·

0

~[fuJ

• •

X

0

X

•

0

A

A

RRCA

A

RRA

A

152

*
*

*
*

76

Opcode
543 210 Hex

No. of No. of M No. otT
Bytes Cycles States Comments

00

000

111

07

4

00

010

111

17

4

00

001

111

OF

4

00

011

111

1F

4

Rotate left
circular
accumulator.
Rotate left
accumulator.
Rotate right
circular
accumulator.
Rotate right
accumulator.

ROTATE AND SHIFT GROUP (Continued)
Symbolic
Mnemonic Operation

S Z

RLCr

* *

RLC(HL)

~:J
RLC(IX+d)

*

* *

Flags
H
P/v N C

X P

X 0

X P 0

X 0 X P 0

r,(HL),(IX + d),(IY + d)

RLC(IY+d)

RLm

* *

~

* *

X 0

X P 0

X 0 X p

0

m =r,(HL,(IX + d),(IY + d)
RRCm

L[i§J-§J

* *

X 0

X P 0

X 0

X P 0

X 0

X P 0

X 0

X P 0

X 0

X P 0

m =r,(HL),(IX + d),(IY + d)

RRm

SLAm

l~
*
m =r,(HL),(IX + d),(IY*+ d)
[ill~-.

*

*

m =r,(HL),(IX + d),(IY + d)

SRAm

~

* *

m =r,(HL),(lX + d),(IY + d)

SRLm

o~

* *

m =r,(HL),(IX + d),(IY + d)
RLO

No. of No.ofM No.ofT

Bytes

Cycles

States

Commenta

11 001 011
00 10001 r

CB

2

2

8

*

11
00

001 011
000 110

CB

2

4

15

*

11
11

011 101
001 011
-d00 10001 110

DO
CB

4

6

23

Rotate left
circular
registerr.
Reg.
000
B
001
C
010
0
011
E
001
H
101
L
111
A

11
11

FO
CB

*
*

111 101
001 011
-d00 10001 110
10101

4

6

Instruction
format and
states are as
shown for
RLCs. To form
newopcode
replace I000 I
orRLCswith
shown code.

[§ill

*

11001

*
*

IJQIJ

*

DTIl

~ * *

X 0 X P 0

•

11
01

101
101

101
111

ED
6F

2

5

18

~ *

X 0 X P 0

•

11
01

101 101
100 111

ED
67

2

5

18

(HL)

*

N

I

Q

23

10011

*

(HLI

RRO

Opcode
543 210

Hex

o· *

X 0

76

Rotate digit
left and
right between
theaccumulatorand
location (HL).
The content
of the upper
half of the
accumulator
is unaffected.

153

d

BIT SET, RESET AND TEST GROUP

Mnemonic

Symbolic
Operation

S Z

BITb. r

Z-rb

X

BITb.(HL)

Z-(HL)b

BITb.(IX+d)b Z-(IX+d)b

BIT b. (IV + d)b Z - (IV + d)b

SETb. r

rb- 1

X

X

X
X

X

X

X

Flags
H
PNN C

X

*

• •

X

X

X

1

•

X

X

X
X
X

X

0
0
0

0

•
•
•

•

• • •

76

Opcode
543 210 Hex

11
01
11
01
11
11

11
11

111
001
-d01
b
11 001
[IT) b
11 001
[IT) b
11 011
11 001
-d-

X

•

X

• • •

SET b. (IX+d) (IX+d)b-1

• •

X

•

X

• • •

SETb. (IV +d) (IV +d)b-1

• •

X

•

X

• • •

• •

X

•

X

• • • ITQ]

(HL)b- 1

[IT)
11
11

[IT)
RESb.m

mb- O
m"'r.(HL).
(IX + d). (IV + d)

011
r
011
110
101
011

b
011
001
-d01
b
110

• •

SETb.(HL)

001
b
001

101
011

2

2

8

CB

2

3

12

DD
CB

4

5

20

FD
CB

4

5

20

000
001
010
011
100
101
111
b
000
001

OlO
110
011
011
110
101
011

b
110
111 101
001 011
-db

CB

No. of No. of M No. ofT
Byte. Cycles States Comments

CB

2

2

8

CB

2

4

15

DD
CB

4

6

23

FD
CB

4

6

23

011
100
101
110
111

Reg.
B
C
D
E
H
L

A
Bit Tested
0
1
2
3

4
5

6
7

110
To form new
opcode replace
OJ] of SET b. s
with [IQ]. Flags
and time
states for SET
instruction.

NOTE: The notation mb indicates location m. bit b (0 to 7).

154

JUMP GROUP

Symbolic
Mnemonic Operation

Flags
Opcocle
H
PIVN C 76 543 210

S Z

··

X

•

X

··•

11

000 011
-n-n-

II condition co
is true PC-nn,
otherwise
continue

• •

X

•

X

• • •

11

co 010
-n-n-

JRe

PC-PC+e

• •

X

•

X

• • •

00 011 000
-e-2-

JRC,e

• •

X

•

X

•

00 111 000
-e-2-

JP(HL)
JP(IX)

IIC=O,
continue
IIC=1,
PC-PC+e
IFC=1,
continue
IIC=O,
PC-PC+e
IIZ=O
continue
IIZ=1,
PC-PC+e
IIZ=1,
continue
IIZ=O,
PC-PC+e
PC-HL
PC-IX

JP(IY)
DJNZ, e

JP nn

PC-nn

JP cc, nn

JR NC,e

JPZ,e

JR NZ,e

·

•

• •

• •

X

X

X

•
•

•

X

X

X

·•

• • •

• • •
• • •

• •
• •

X
X

•
•

X
X

• • •
• • •

PC-IV

• •

X

•

X

• • •

B-6-1
IIB=O,
continue

• •

X

•

X

• • •

IIB~O,

00 110 000
-e-2-

00 101 000
-e-2-

00 100 000
-e-2-+

11 101 001
11 011 101
11 101 001
11 111 101
11 101 001
00 010 000
-e-2-

Hex

No. of No. of M No. ofT
Bytes Cycles States Comments
3

3

10

3

3

10

18

2

3

12

38

2

2

7

Condition
cc
000 NZ (non-zero)
001 Z(zero)
010 NC (non-carry)
011 C(carry)
100 PO (parity odd)
101 PE (parity even)
110 P (sign positive)
111 M (sign negative)
II condition not met.

2

3

12

II condition is met.

2

2

7

II condition not met.

2

3

12

II condition is met.

2

2

7

II condition not met.

2

3

12

II condition is met.

2

2

7

II condition not met.

2

3

12

II condition is met.

1
2

2

8

2

2

8

2

2

8

IIB=O

2

3

13

IIB~O.

C3

30

28

20

E9
DD
E9
FD
E9
10

II
ft

4

PC-PC+e
NarES' e represents the extension in the relative addressing mode.
e is a signal two's complement number in the range < -126, 129 >.
e - 2 in the opcode provides an effective address of pc + e as PC is incremented by 2 prior to the addition of e.

155

:I

CALL AND RETURN GROUP
Symbolic
Mnemonic Operation
CALLnn

Flags

S Z

76

• •

11

001 101
-n-n-

• • X• X• • •

11

(SP-1)-PCH •
(SP-2)-PCl
PC-nn,
CALL cC,nn II condition
ccislalse
continue,
otherwise
same as
CALLnn
RET
RETcc

RETI
RETN1

RSTp

• X • X •

543 210 Hex

No. of No. of M No. ofT
Bytes Cycles Stetes Comments
3

5

17

cc 100
-n-

3

3

10

II cc is lalse.

-n-

3

5

17

II cc is true.

3

10

PCl -(SP)
PCH-(SP+1)
II condition
cc islalse
continue,
otherwise
same as RET

• • X• X• • •

11

001

001

• • X• X• • •

11

cc

000

Returnlrom
interrupt
Returnlrom
non-maskable
interrupt
(SP-1)-PCH
(SP-2)-PCl
PCH-O
PCl -p

• • X• X• • •

CD

C9

3

• •

X • X • • •

• • X• X• • •

NOTE: 1RETN loads IFF2 -IFF1

156

Opcode
PNN C

H

11
01
11
01
11

101
001
101
000

101
101
101
101
111

ED
4D
ED
45

5

II cc is lalse

11

II cc is true.
cc
000
001
010
011
100
101
110
111

Condition
NZ (non-zero)
Z(zero)
NC (non-carry)

000
001
010
011
100
101
110
111

OOH
08H
10H
18H
20H
28H
30H
38H

2

4

14

2

4

14

3

11

C(carry)
PO (parity odd)
PE (parity even)
P (sign positive)
M (sign negative)

P

INPUT AND OUTPUT GROUP

Symbolic
Mnemonic Operation

S Z

IN A. (n)

•

A+-(n)

INr,(C)

r+-(C)
il r= 110 only
the Ilags will
be affected

INI

(HL)-(C)
8-8-1
HL-HL+1
(HL)-(C)
8-8-1
HL-HL+1
Repeat until
8=0

Flags
H
PNN C

76

• •

11

• X • X •

Opcode

543 210 Hex
011 01
.... n-

D8

No. of No. of M No. ofT
Bytes Cycles States Commenta
2

3

11

ntoAo"'A7

Ace. to As '" A15

o •

11
01

101

101
000

ED

2

3

12

CtoAo"'A7
8toAs"'A15

X X X 1 X

11
10

101 101
100 010

ED
A2

2

4

16

CtoAo "'A7
8toAs"'A15

X 1 X X X X 1 X

11
10

101 101
110 010

ED
82

2

5

21

CtoAo "'A7
8toAs"'A15

X

X P

(j)

INIR

X

*X
®

(118;&0)
2

4

IItt

•a

16

(118=0)

(j)
IND

(HL)-(C)
8 .... 8-1
HL-HL-1
INDR
(HL)-(C)
8 .... 8-1
HL-HL-1
Repeat until
8=0
OUT(n),A (n)-A
OUT(C), r (C)-r

X

*X
®

X X X 1 X

X 1 X X X X 1 X

11
10

101
101

101
010

11
10

101
111

101
010

ED

2

4

16

CtoAo '" A7
8toAa"'A15

5

21

CtoAo"'A7
8toAs"'A15

AA

ED

2

(118;&0)

8A
2

4

16

(118=0)

•
•

• X
• X

• X •
• X •

• •
• •

11

010 011
-n11 101 101
01
001

D3

2

3

11

ntoAo"'A7

Ace. to AS '" A15
ED

2

3

12

CtoAo'" A7
8toAs"'A15

4

16

CtoAo"'A7
8toAs"'A15

5

21

CtoAo'" A7
8toAs"'A15

(j)
(C)+-(HL)
8+-8-1
HL-HL+1
(C)-(HL)
8-8-1
HL-HL+1
Repeat until
B=O

OUTI

OTIR

*

X X X X 1 X

11
10

101 101
100 011

ED
A3

2

X 1 X X X X 1 X

11
10

101 101
110 011

ED

2

X

®

83

(118;&0)
2

4

16

(118=0)

(j)

*X

OUTO

(C)-(HL)
8-8-1
HL-HL-1

X

X X X 1 X

11
10

101
101

101
011

ED
A8

2

OTDR

(C)+-(HL)
8-8-1
HL-HL-1
Repeat until
8=0

X 1 X X X X 1 X

11
10

101
111

101
011

ED

2

NOTES:

.
16-bit value in range < 0,65535 >.

* Hand Nflags are used in conjunction with the decimal adjust instruction (DAA) to properly correct the result into packed BCD format following addition or
subtraction uSinG Jperands with packed BCD format.

158

PIN DESCRIPTIONS

Ao-A1s. Address Bus (output, active High, 3-state). Ao-A15
form a 16-bit address bus. The Address Bus provides the
address for memory data bus exchanges (up to 64K bytes)
and for I/O device exchanges.

M1. Machine Cycle One (output, active Low). M1, together
with MREO, indicates that the current machine cycle is the
opcode fetch cycle of an instruction execution. M 1, together
with 10RO, indicates an interrupt acknowledge cycle.

BUSACK. Bus Acknowledge (output, active Low). Bus
Acknowledge indicates to the requesting device that the
CPU address bus, data bus, and control signals MREQ,
10RO, RD, and WR have entered their high-impedance
states. The external circuitry can now control these lines.

MREQ. Memory Request (output, active Low, 3-state).
MREO indicates that the address bus holds a valid address
for a memory read or memory write operation.

BUSREQ. Bus Request ~t, active Low). Bus Request
has a higher priority than NMI and is always recognized at
the end of the current machine cycle. BUSREO forces the
CPU address bus, data bus, and control signals MREO,
10RO, RD, and WR to go to a high-impedance state so that
other devices can control these lines. BUSREO is normally
wired-OR and requires an external pullup for these
applications. Extended BUSREO periods due to extensive
DMA operations can prevent the CPU from properly
refreshing dynamic RAMs.

00-07. Data Bus (inputloutput, active High, 3-state). 00-07
constitute an a-bit bidirectional data bus, used for data
exchanges with memory and 1/0.

Halt. Halt State (output, active Low). HALT indicates that the
CPU has executed a Halt instruction and is awaiting either a
nonmaskable or a maskable interrupt (with the mask
enabled) before operation can resume. While halted, the
CPU executes NOPs to maintain memory refresh.
INT. Interrupt Request (input, active Low). Interrupt Request
is generated by 1/0 devices. The CPU honors a request at
the end of the current instruction if the internal
software-controlled interrupt enable flip-flop (IFF) is
enabled. INT is normally wired-OR and requires an external
pullup for these applications.

IORQ. Input/Output Request (output, active Low, 3-state).
10RO indicates that the lower half of the address bus holds a
valid 1/0 address for an 1/0 read or write operation. 10RO is
also generated concurrently with M1 during an interrupt
acknowledge cycle to indicate that an interrupt response
vector can be placed on the data bus.

NMI. Non-Maskable Interrupt (input, negative edgetriggered). NMI has a higher priority than INT. NMI is always
recognized at the end of the current instruction,
independent of the status of the interrupt enable flip-flop,
and automatically forces the CPU to restart at location
0066H.

RD. Read (output, active Low, 3-state). RD indicates that the
CPU wants to read data from memory or an 1/0 device. The
addressed 1/0 device or memory should use this signal to
gate data onto the CPU data bus.
RESET. Reset (input, active Low). RESET initializes the CPU
as follows: it resets the interrupt enable flip-flop, clears the
PC and Registers I and R, and sets the interrupt status to
Mode O. During reset time, the address and data bus go to a
high-impedance state, and all control output signals go to
the inactive state. Note that RESET must be active for a
minimum of three full clock cycles before the reset operation
is complete.
RFSH. Refresh (output, active Low). RFSH, together with
MREO, indicates that the lower seven bits of the system's
address bus can be used as a refresh address to the
system's dynamic memories.
WAIT. Wait (input, active Low). WAIT indicates to the CPU
that the addressed memory or 1/0 devices are not ready for
a data transfer. The CPU continues to enter a Wait state as
long as this signal is active. Extended WAIT periods can
prevent the CPU from refreshing dynamic memory properly.
WR. Write (output, active Low, 3-state). WR indicates that the
CPU data bus holds valid data to be stored at the addressed
memory or 1/0 location.

159

10
~

~

CPU TIMING
The Z80 CPU executes instructions by proceeding through
a specific sequence of operations:
• Memory read or write
• I/O device read or write
• Interrupt acknowledge
The basic clock period is referred to as a T time or cycle, and
three or more T cycles make up a machine cycle (M 1, M2 or
M3 for instance). Machine cycles can be extended either by
the CPU automatically inserting one or more Wait states or
by the insertion of one or more Wait states by the user.

--------11,1---'
RFSH

-TW

Instruction Opcode Fetch. The CPU places the contents
of the Program Counter (PC) on the address bus at the start
of the cycle (Figure 5). Approximately one-half clock cycle
later, MREQ goes active. When active, RD indicates that the
memory data can be enabled onto the CPU data bus.
The CPU samples the WAIT input with the falling edge of
clock state T2. During clock states T3 and T4 of an M1 cycle,
dynamic RAM refresh can occur while the CPU starts
decoding and executing the instruction. When the Refresh
Control signal becomes active, refreshing of dynamic
memory can take place.

e

_1_

21

I- ®- ®
r---------'
...

= Wait cycle added when necessary for slow ancilliary devices.
Figure 5. Instruction Opcode Fetch

160

2001-006

Memory Read or Write Cycles. Figure 6 shows the timing
of memory read or write cycles other than an opcode fetch
(M1) cycle. The MREO and RD signals function exactly as in
the fetch cycle. In a memory write cycle, MREO also

becomes active when the address bus is stable. The WR line
is active when the data bus is stable, so that it can be used
directly as an RiW pulse to most semiconductor memories.

CLOCK

@--

WAIT

--+----+------~~~--~~-'

-

-@

-

READ {
OPERATION
00-07

-®

WR

....~;:~:

{

-------+----------~

I~·~------~GD~-------.I

~~------

~_-2-9---~~-----------i.

00-07

---------~(~-----;{.;~~D~AT~A~O~U~T-------_4~--Figure 6. Memory Read or Write Cycles

2001·007

161

Input or Output Cycles. Figure 7 shows the timing for an
1/0 read or 1/0 write operation. During 1/0 operations, the
CPU automatically inserts a single Wait state (TWN. This

extra Wait state allows sufficient time for an 1/0 port to
decode the address from the port address lines.

CLOCK

WAIT

--+---+---+---------~~~~~~

RD

OPERA~~~E

{
00-07

:~:::~:~~1_--_t------El38c:::::::::~::::::::::~~~~::::::
11I----------------F):....------------...I'1 .. ~.-

WR

WRI~~ {
OPERATION

~

00-07

___________

-(::::::::::::::::::~~::::::~~~:::::::)
~
DATA OUT

TWA = One wait cycle automatically Inserted by CPU.

Figure 7. Input or Output Cycles

162

2001·008

Interrupt Request/Acknowledge Cycle. The CPU
samples the interrupt signal with the rising edge of the last
clock cycle at the end of any instruction (Figure 8). When an
interrupt is accepted, a special M1 cycle is generated.

AO-A15

__________

During this M1 cycle, IORO becomes active (instead of
MREO) to indicate that the interrupting device can place an
8-bit vector on the data bus. The CPU automatically adds
two Wait states to this cycle.

PC

~J~------------~----~~~--~~~J~---

I

9

I~.~------~~~------~~I
WAIT

------------~----------------------~~~~~
J~

-.

DO-D7====~>-_------~(~«~(::::::~~=E~)C
NOTES: 1) TLI = Last slaleof any Instruction cycle.

2) TWA

= Walt cycle automatically Inserted by CPU.
Figure 8_ Interrupt Request/AcknDWledge Cycle

2001·009

163

Non-Maskable Interrupt Request Cycle. NMI is sampled
at the same time as the maskable interrupt input INT but has
higher priority and cannot be disabled under software
control. The subsequent timing is similar to that of a normal

memory read operation except that data put on the bus by
the memory is ignored. The CPU instead executes a restart
(RST) operation and jumps to the NMI service routine
located at address 0066H (Figure 9).

+...- - - - - - - - - - - - - I M I - - - - - - - - - - -__1

- - - - L A S T M CYCLE - - -__

T.

TLI

TO

T,

T,

CLOCK

------ "I ®*17 - --

1I1IiIi _______ ~----

-__

-CD-AO-Ai5

PC

REFRESH

------------------------~~~-------------rJ~---------~---_+---------~

®

• Although NMI is an asynchronous Input, to guarantee Its being recognized on the following machine cycle, NMl's falling edge must occur no later than the rising edge

of the clock cycle preceding the last state of any Instruction cycle (TLI).

Figure 9. Non·Maskl!ble Interrupt Request Operetlon

164

2001-010

Bus Request/Acknowledge Cycle. The CPU samples
BUSREO with the rising edge of the last clock period of any
machine cycle (Figure 10). If BUSREO is active, the CPU
sets its address, data, and MREO, 10RO, RD, and WR lines

to a high-impedance state with the rising edge of the next
clock pulse. At that time, any external device can take
control of these lines, usually to transfer data between
memory and 1/0 devices.

Tx

CLOCK

Tx

Tx

JL ~'\~ nL-i'--i

®-

"

"""

®-

r---\

~

J

~

-®I-

~

"

-

-®

F

.....

--®
FLOAT

Ao-Au

Do-D7

MREQ
RD,WR
IORQ

-

--®

-

!--®

.....

-----®

FLOAT

....

-®
Jr---

FLOAT

....

~

®~

"

111

-

-®

I'--

®~

)

UNCHANGED

NOTES. 1) TLM = Last slale ofany M cycle.
2) Tx = An arbitrary clock cycle used by requesting device.

Figure 10. Z-BUS Request/Acknowledge Cycle

200H)11

165

Halt Acknowledge Cycle. When the CPU receives a HALT
instruction, it executes NOP states until either an INT or NMI
input is received. When in the Halt state, the HALT output is
M 1 - - -...

T4

active and remains so until an interrupt is received (Figure
11). INT will also force a Halt exit.

I....- - - - - - - - M 1 - - - - - - -..... I....I - - - - - - - M1
T1

12

T3

T4

T,

T2

CLOCK

NMI

-----------------------I-.~·
~-----------------

NMi is an asynchronous input, to guarantee Its being recognized on the following machine cycle, MNI's failing edge must occur no
later than the rising edge of the clock cycle preceding the last state of any Instruction cycle (Tu).

* Although

Figure 11. Halt Acknowledge Cycle

Reset Cycle. RESET must be active for at least three clock
cycles for the CPU to properly accept it. As long as RESET
remains active, the address and data buses float, and the
control outputs are inactive. Once RESET goes inactive, two

internal T cycles are consumed before the CPU resumes
normal processing operation. RESET clears the PC register,
so the first opcode fetch will be to location OOOOH
(Figure 12).
1_---M1----T,

T,

CLOCK

-0-

-@Ao-A15

--------------------®~-~-------------------------+------------------FLOAT

Do-D7

-@lM1

/

------------------------~

MREQ,

~~------------~/I~~2~ZrZrIT7T------)fi'l~------------------~\~-_-_~-_-_--_-_-_--_
BUSACK
HALT

-

Figure 12. Reset Cycle

166

2001·012.013

AC CHARACTERISTICSt

Number Symbol

Parameter

Z80CPU
Min
Max

Z80ACPU
Min
Max

Z80BCPU
Min
Max

Z80HCPU
Min
Max

250'

165'

125'

TcC

Clock Cycle Time

400'

2

TwCh

Clock Pulse Width (High)

180

2000

110

2000

65

2000

55

2000

3

TwCI

Clock Pulse Width (Low)

180

2000

110

2000

65

2000

55

2000

4

TfC

Clock Fall Time

30

30

20

10

5

TrC

Clock Rise Time

30

30

20

10

6

TdCr(A)

Clock t to Address Valid Delay

145

110

90

80

7

TdA(MREQf)

Address Valid to MREO ~ Delay

8

TdCf(MREOf)

Clock ~ to MREO ~ Delay

100

85

70

60

9

TdCr(MREOr)

Clock t to MREO t Delay

100

85

70

60

125'

65'

35'

20'

10

TwMREOh

MREQ Pulse Width (High)

170'

110'

65'

45'

11

TwMREOI

Mi'iEQ Pulse Width (Low)

360'

220'

135'

100'

12

TdCf(MREOr)

Clock ~ to MREO t Delay

100

85

70

60

13

TdCf(RDf)

Clock ~ to RD ~ Delay

130

95

80

70

14

TdCr(RDr)

Clock t to RD t Delay

15

TsD(Cr)

Data Setup Time to Clock t

16

ThD(RDr)

Data Hold Time to RD t

17

TsWAIT(Cf)

WAIT Setup Time to Clock ~

18

ThWAIT(Cf)

WAIT Hold Time after Clock ~

85

100
50

35
0

70

70

ft

30

0

0

0

60

50

0

0

0

0

19

TdCr(Mlf)

Clock flo Ml ~ Delay

130

100

80

70

20

TdCr(Mlr)

Clock t to M 1 t Delay

130

100

80

70

21

TdCr(RFSHf)

Clock t to RFSH ~ Delay

180

130

110

95

22

TdCr(RFSHr)

Clock t to

RFSH t Delay

150

120

100

85

23

TdCf(RDr)

Clock ~ to RD t Delay

110

85

70

60

24

TdCr(RDf)

Clock t to RD ~ Delay

100

85

70

60

25

TsD(Cf)

Data Setup to Clock ~ during M2, M3,

60

50

c:I

60

30

70

II
•

40

30

M4, or Ms Cycles
26

TdA(IOROf)

Address Stable prior to IORO ~

27

TdCr(IOROf)

Clock t to IORO ~ Delay

90

75

65

28

TdCf(IOROr)

Clock ~ to iORQ t Delay

110

85

70

29

TdD(WRf)

Data Stable prior to WR ~

30

TdCf(WRf)

Clock ~ to WR ~ Delay

31

TwWR

WR Pulse Width

32

TdCf(WRr)

Clock ~ to WR t Delay

33

TdD(WRf)

Data Stable prior to WR ~

320'

180'

190'

80'

220'
100

60
5'

70

60

135'

100'
70

80
-10'

20'

55

25'
80

90
360'

75'

110'

60

-55'

55'

34

TdCr(WRf)

Clock t to WR ~ Delay

35

TdWRr(D)

Data Stable from WR t

36

TdCf(HALT)

Clock ~ to

37

TwNMI

NMI Pulse Width

80

80

70

60'

38

TsBUSREO(Cr)

BUSREO Setup Time to Clock t

80

50

50

40

80
120'

HAiJ t or ~

65
60'

300

60

55
15'

30'
260

300

225

'For clock periods other than the minimums shown, calculate parameters using the table on the following page. Calculated values above
assumed TrC = TIC = 20 ns.
tUnits in nanoseconds (ns).

167
------

--

~--

~~--.---~,-,---

. _ - ---"

AC CHARACTERISTICSt (Continued)

Number Symbol

Parameter

Z80CPU
Min
Max

Z80ACPU
Min
Max

Z80SCPU
Min
Max

Z80HCPU
Min
Max

39

ThBUSREO(Cr)

BUSREO Hold Time after Clock t

40

TdCr(BUSACKI)

Clock t to BUSACK.j. Delay

120

100

90

80

41

TdCI(BUSACKr)

Clock.j. to BUSACK t Delay

110

100

90

80

42

TdCr(Dz)

Clock t to Data Float Delay

90

90

80

70

43

TdCr(CTz)

Clock t to Control Outputs Float Delay
(MREO, IORO, RD, and WR)

110

80

70

60

44

TdCr(Az)

Clock t to Address Float Delay

45

TdCTr(A)

MREO t, IORO t, RD t, and WR t to
Address Hold Time

46

TsRESET(Cr)

RESET to Clock t Setup Time

47

ThRESET(Cr)

RESETto Clock t Hold Time

48

TsINTI(Cr)

INT to Clock t Setup Time

49

ThINTr(Cr)

INTto Clock t Hold Time

50

TdM1f(IOROI)

M1 Ho IORO Welay

0

0

110
160*

0

90

60

70
0

0
920*

45
0

0
80

0
55

0

0
270*

365*

565*

70
20*

60

0
80

80
35*

80*

90

0

51

TdCI(IOROI)

Clock .j. to IORO .j. Delay

110

85

70

52

TdCI(IOROr)

Clock t IORO t Delay

100

85

70

60

53

TdCI(D)

Clock.j. to Data Valid Delay

230

150

130

115

60

* For clock periods other than the minimums shown, calculate parameters using the following table. Calculated values above
assumed TrC = TIC = 20 ns.
tUnits in nanoseconds (ns).

FOOTNOTES TO AC CHARACTERISTICS
Number

Symbol

General Parameter

TeC

TwCh + TwCI + TrC + TIC

TdA(MREOI)

10

TwMREOh

7

Z80A

Z80S

TwCh + TIC

- 75

- 65

-50

-45

TwCh + TIC

- 30

- 20

-20

-20
-25

Z80H

11

TwMREOI

TeC

- 40

- 30

-30

26

TdA(IOROI)

TeC

- 80

- 70

-55

-50

29

TdD(WRI)

TeC

- 210

- 170

-140

-120

31

TwWR

TeC

- 40

- 30

-30

-25

33

TdD(WRI)

TwCI + TrC

- 180

- 140

-140

-120

35

TdWRr(D)

TwCI + TrC

- 80

- 70

-55

-50

45

TdCTr(A)

TwCI + TrC

- 40

- 50

-50

-45

50

TdM1f(IOROI)

2TeC + TwCh + TIC

- 80

- 65

-50

-45

AC Test Conditions:
VIH = 2.0V
VIL = 0.8 V
VIHC = VCC - 0.6 V
VILC = 0.45 V

168

Z80

VOH = 1.5V
VOL = 1.5V
FLOAT = ±05V

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect to ground ... 0.3V to + 7V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. ThiS IS a stress rating only;
operation of the device at any condition above these indicated in the
operational sections of these specifications IS not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

STANDARD TEST CONDITIONS
The DC Characteristics and Capacitance sections below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND (OV).
Positive current flows into the referenced pin.
Available operating temperature ranges are:

All ac parameters assume a load capacitance of 100 pf. Add
15 ns delay for each 50 pf increase in load up to a maximum
of 200 pf for the data bus AC timing measurements are
referenced to 1.5 volts (except for clock, which is referenced
to the 10% and 90% points).
+5V

• S = O°Cto +70°C, +4.75V";Vcc"; +5.25V
•

E = -40°Cto +85°C, +4.75V";Vcc"; +5.25V

•

M = -55°Cto +125°C, +4.5V";Vcc"; +5.25V

2.1K

The Ordering Information section lists temperature ranges
and product numbers. Package drawings are in the
Package Information section in this book. Refer to the
Literature List for additional documentation.

100pf

I

DC CHARACTERISTICS
All parameters are tested unless otherwise noted.
Symbol

Parameter

VILC

Clock Input Low Voltage

VIHC

Clock Input High Voltage

VIL

Min
-0.3

Max

Unit

0.45

V

VCC-·6

VCC+·3

V

Input Low Voltage

-0.3

0.8

V

VIH

Input High Voltage

2.0 1

VOL

Output Low Voltage

VOH

Output High Voltage

ICC

Power Supply Current

III

Input Leakage Current

ILO

3-State Output Leakage Current in Float

VCC
0.4

-10

Test Condition

V
V

IOL =2.0mA

V

IOH= -250iJA

200

mA

Note 3

10

iJ A

VIN=OtoVCC

102

iJ A

VOUT = 0.4 to VCC

1. For military grade parts, refer to the Z80 Military Electrical SpeCification.

2. A1S-AO, DrDo, MREQ, 1liOO, RlJ, and WR
3. Measurements made with outputs floating.

CAPACITANCE
Guaranteed by design and characterization.
Symbol

Parameter

CCLOCK

Clock Capacitance

CIN

Input Capacitance

COUT

Output CapaCitance

Min

Max

Unit

35

pf

5

pf

15

pf

NOTES
TA = 25°C, f = 1 MHz
Unmeasured pins returned to ground.

169

ORDERING INFORMATION
Z80 CPU, 2.5 MHz
44-pln LCC
44-pln PCC
Z8400 LM *
Z8400 VSt
Z8400LMB*t

40-plnDIP
Z8400PS
Z8400CS
Z8400PE
Z8400CE
Z8400CM*
Z8400CMB*
Z8400CMJ*

40-pinDIP
Z8400APS
Z8400ACS
Z8400APE
Z8400ACE
Z8400ACM*
Z8400ACMB*
Z8400ACMJ*

Z80B CPU, 6.0 MHz
40-pln DIP
44-pln PCC
Z8400B PS
Z8400B VSt
Z8400BCS
Z8400BPE
zaOH CPU, 8.0 MHz
40-pln DIP
44-pln PCC
Z8400H PS
Z8400H VSt

Z80A CPU, 4.0 MHz
44-pln LCC
44-pln PCC
Z8400A LM *
Z8400A VSt
Z8400ALMB*t

Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = O°Cto +70 oC
E = -40°C to +85°C
M*= -55°C to +125°C
* For Military Orders, refer to the Military Section.

t Available soon.

170

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B
J = JAN 38510 Class B

Z8410Z80®DMA
Direct Memory Access
Controller
Product
Specification

Zilog

April 1985

FEATURES
• Transfers, searches, and search/transfers in Byte-at-aTime, Burst, or Continuous modes. Cycle length and
edge timing can be programmed to match the speed of
any port.
•

•

Dual port addresses (source and destination) generated
for memory-to-I/O, memory-to-memory, or I/O-to-I/O
operations. Addresses may be fixed or automatically
incremented/decremented.

•

Extensive programmability of functions. CPU can read
complete channel status.

•

Standard Z80 Family bus-request and prioritized
interrupt-request daisy chains implemented without
external logic. Sophisticated, internally modifiable
interrupt vectoring.

•

Direct interfacing to system buses without external logic.

Next-operation loading without disturbing current
operations via buffered starting-address registers. An
entire previous sequence can be repeated automatically.

GENERAL DESCRIPTION
The Z80 DMA (Direct Memory Access) is a powerful and
versatile device for controlling and processing transfers of
data. Its basic function of managing CPU-independent
0,
0,

'..HO{
DATA.

BUS

Ao

"

0,

A,
A,

.
..
....

0,
D.

0,

iAi
BAD

"~l

A,

SYSTEM
ADDRESS
BUS

A,

BUSREQ

Z8410
Z80DMA

Mi

..
..
A,

A,

0,
0,

BUS {
CONTROL

transfers between two ports is augmented by an array of
features that optimize transfer speed and control with little or
no external logic in systems using an 8- or 16-bit data bus
and a 16-bit address bus.

A,

Ao

lEO

""

A"
A11
A12

iVii

0,
0,

A"
A14

IORQ

D.

+5V

OND

A"

MREQ

0,

ilAO
iiAl

0,
0,

BUSREQ

Mi

Rii

}

DMA
CONTROL

}

INTERRUPT
CONTROL

CEIWAIT
lEO

A"
A14
A13
A12

eLK

Figure 1. Pin Functions
2032-001,002

iN'fJPULSE

0,

w-

GND

A,

eLK

CONTROL
BUS

+5V

..
lEI

....

ROY

A"
A11

Figure 2. 40·pin Dual·ln·Line Package (DIP),
Pin AsSignments

171

Transfers can be done between any two ports (source and
destination), including memory-to-I/O, memory-to-memory,
and I/O-to-I/O. Dual port addresses are automatically
generated for each transaction and may be either fixed or
incrementing/decrementing. In addition, bit-maskable byte
searches can be performed either concurrently with
transfers or as an operation in itself.
The l80 DMA contains direct Interfacing to, and
independent control of, system buses, as well as
sophisticated bus and interrupt controls. Many

programmable features, including variable cycle timing and
auto-restart, minimize CPU software overhead. They are
especially useful in adapting this special-purpose transfer
processor to a broad variety of memory, I/O and CPU
environments.
The l80 DMA is an n-channel silicon-gate depletion-load
device packaged in a 40-pin, plastic or ceramic DIP. It uses a
single + SV power supply and the standard l80 Family
single-phase clock.

FUNCTIONAL DESCRIPTION
Classes of Operation. The l80 DMA has three basic
classes of operation:
•

Transfers of data between two ports (memory or I/O
peripheral)

• Searches for a particular 8-bit maskable byte at a single
port in memory or an I/O peripheral
• Combined transfers with simultaneous search between
two ports
Figure 4 illustrates the basic functions served by these
classes of operation.

SYSTEM
BUSES

A

t-..

~

I'

During a search-only operation, data is read from the source
port and compared byte by byte with a DMA-internal register
containing a programmable match byte. This match byte
may optionally be masked so that only certain bits within the
match byte are compared. Search rates up to 1.2SM bytes
per second can be obtained with the 2.S MHz l80 DMA or
2M bytes per second with the 4 MHz l80A DMA.
In combined searches and transfers, data is transferred
between two ports while simultaneously searching for a
bit-maskable byte match.

DMA

CPU

,.

During a transfer, the DMA assumes control of the system
address and data buses. Byte by byte, data is read from one
addressable port and written to the other addressable port.
The ports may be programmed to be either system main
memory or peripheral I/O devices. Thus, a block of data
may be written from one peripheral to another, from one
area of main memory to another, or from a peripheral to main
memory and vice versa.

INT
ROY
lEI

Data transfers or searches can be programmed to stop, or
interrupt, under various conditions. In addition, CPUreadable status bits can be programmed to reflect the
condition.

Modes of Operation. The l80 DMA can be programmed
to operate in one of three transfer and/or search modes:

• 8yte-at-a- Time: data operations are performed one byte

+5V

T

at a time. Between each byte operation the system buses
are released to the CPU. The buses are requ'ested again
for each succeeding byte operation.

lEI

ZCIT01

CTC
1lEO

Z·80DMA
lEI
RxCA

iNT

i'XcA

lEO

RxCB
TxCB

iiiiiiiiYii
iiiiRDvii

lEO

iNT

I

~

"

lEI

~

ROY

110
'---ll-_-+
~ Q" (flo -

OUT

I

=RD.eE.iOiiQ·M1

Figura 13. Read Cycle Timing

Figura 12. Wrlta Cycle Timing

eLK
WR'
PORT
OUTPUT _ _ _ _ _-' '\.--+----i---~~READY ______________- J

'WR

=RD' CE • IORQ • M1
Figure 14. Mode 0 Output Timing

2006·013,014,015

197

10
..,

S

Input Mode (Mode 1). When STROBE goes from Low to

High, data is latched into the selected port input register
(Figure 15). While STROBE is Low, the input data latches are
transparent. The next rising edge of S'i'ROBE activates INT, if
Interrupt Enable is set and this is the highest-priority
requesting device. The following falling edge of ClK resets
Ready to an inactive state, indicating that the input register is
full and cannot accept any more data until the CPU
completes a read. When a read is complete, the positive
edge of RD sets Ready at the next Low-going transition of
ClK. At this time new data can be loaded into the PIO.

"RD

Bidirectional Mode (Mode 2). This is a combination of
Modes 0 and 1 using all four handshake lines and the eight
Port A 1/0 lines (Figure 16). Port B must be set to the bit
mode and its inputs must be masked. The Port A handshake
lines are used for output control and the Port B lines are
used for input control. If interrupts occur, Port /l:.s vector will
be used during port output and Port B's will be used during
port input. Data is allowed out onto the Port A bus only when
ASTB is Low. The rising edge of this strobe can be used to
latch the data into the peripheral.

= !iii" aE • iORiI • ii1
Figure 15. Mode 1 Input Timing

CLK

WR"

ARDY

PORTA
DATA BUS

INT

BRDY
"WR

=RD • CE " IORO • Mt
Figure 16_ Mode 2 Bidirectional Timing

198

2006-016. 017

Bit Control Mode (Mode 3). The bit mode does not utilize
the handshake signals, and a normal port write or port read
can be executed at any time. When writing, the data is
latched into the output registers with the same timing as the
output mode.

Interrupt (RETI) instruction is executed by the CPU while lEI
is High. The 2-byte RETI instruction is decoded internally by
the Pia for this purpose.

Return From Interrupt Cycle. If a Z80 peripheral has no
interrupt pending and is not under service, then its lEO =
lEI. If it has an interrupt under service (i.e., it has already
Interrupted and received an Interrupt acknowledge) then its
lEO is always Low, inhibiting lower priority devices from
interrupting. If it has an interrupt pending which has not yet
been acknowledged, lEO is Low unless an "ED" is decoded
as the first byte of a 2-byte opcode (Figure 19). In this case,
lEO goes High until the next opcode byte is decoded,
whereupon it goes Low again. If the second byte of the
opcode was a "40," then the opcode was an RETI
instruction.

When reading (Figure 17) the Pia, the data returned to the
CPU is composed of output register data from those port
data lines assigned as outputs and input register data from
those port data lines assigned as inputs. The input register
contains data that was present immediately prior to the
falling edge of RD. An interrupt is generated if interrupts
from the port are enabled and the data on the port data lines
satisfy the logical equation defined by the 8-bIt mask and
2-bit mask control registers. However, if Port A is
programmed in bidirectional mode, Port B does not issue an
interrupt in bit mode and must therefore be polled.

After an "ED" opcode is decoded, only the peripheral
device which has interrupted and is currently under service
has its lEI High and its lEO Low. This device is the
highest-priority device in the daisy chain that has received
an interrupt acknowledge. All other peripherals have lEI =
lEO. lithe next opcode byte decoded is "40," this peripheral
device resets its "interrupt under service" condition.

Interrupt Acknowledge Timing. During M1 time,
peripheral controllers are inhibited from changing their
interrupt enable status, permitting the Interrupt Enable
signal to ripple through the daisy chain. The peripheral with
lEI High and lEO Low during INTACK places a
preprogrammed 8-bit interrupt vector on the data bus at this
time (Figure 18). lEO is held Low until a Return From

eLK

DAT:~~:

:========:X

DATA WO.D 1

X,-_D_AT_AW_O_.D_'........X"'_________

~ -----g-~-~-~-~-~->~~~~~~~~{'_~_)-'===~~:~r------------

~-D7 -------------«~D~AT~AI~N:»----------LDATA WORD 1 PLACED ON BUS

Figure 17. Mode 3 Bit Control Mode Timing, Bit Mode Read

T,

T.

T.

T,

T,

T.

T.

T,

CLK
CLK

!

Mt \ ' -_ _-'
IORQ AND M1

~---

INDICATE
} INTERRUPT
ACKNOWLEDGE

INTACK

'---I

ii
~-D7

-----<0

.•. -----_______ J ,

0

'.0 ______________--J!

•••
Figure 18. Interrupt Acknowledge Timing

2006·018.019,020

Figure 19. Return From Interrupt

199

N

I

"'0.

AC TIMING DIAGRAM

-----0-0-1 -cD--,.............,
CLOCK

Ci
B/A,C/i)

- ~ ~f\J\J'J\
./

-&-1

I~- TsPD(STB).

150

260

120

[4]

150

[5]
160

180

= 50 pi
[5]

120

220
200

= 50 pi

170
190

150

= 50 pi

[8]

CL
18

00
0

[3]

100

130

N

[2]

120

160

210

300

[6J
0

70

115

50

Notes

[5J

190

230

[5]
CL

= 50 pi

[5] Increase these values by 2 ns for each 10 pf Increase in loading up to
100 pfmax.
[6] TsCS(RI) may be reduced However, the time subtracted from TsCS(RI)
will be added to TdRI(DO)
• M1 must be active for a minimum of two clock cycles to reset the PIO
t Units in nanoseconds (ns)

201

...

'til

C

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
toGND .......................... -0.3Vto +7V
Operating Ambient
Temperature ..............See Ordering Information
Storage Temperature .............. - 65°e to + 150 0 e

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those Indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability

STANDARD TEST CONDITIONS
The De characteristics and capacitance sections listed
below apply for the following standard test conditions,
unless otherwise noted. All voltages are referenced to GND
(OV). Positive current flows into the referenced pin.

All ac parameters assume a load capacitance of 100 pf max.
+5V
2.1K

Available operating temperature ranges are:
• S = ooe to + 70 oe, + 4.75V"'; Vcc"'; + 5.25V
•

E = -40°Cto +85°C, +4.75V"';Vcc"'; +5.25V

•

M = -55°Cto +125°C, +4.5V"';Vcc"'; +5.5V

The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the
Package Information section. Refer to the Literature List for
additional documentation.

DC CHARACTERISTICS
Symbol

Parameter

VllC
VIHC
Vil
VIH
VOL
VOH
III
ILO

Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Output Leakage Current in Float
Power Supply Current
Darlington Drive Current
Port B Only

ICC
IOHD

Min

Max

-0.3

+0.45

VCC- 0.6
-0.3

VCC+0.3
+0.8

+2.0

VCC
+0.4

+2.4
±10
±10
100
-1.5

Unit

Test Condition

V
V
V
V
V
V

IOl = 2.0mA
IOH = -250 iJA.

,..A
,..A
mA
mA

VIN = OtoVCC
VOUT = O.4V to VCC
VOH = 1.5V
REXT = 390Q

Over specified temperature and voltage range.

CAPACITANCE
Symbol

Parameter

C

Clock Capacitance
Input Capacitance

CIN
COUT

Output Capacitance

Min

Max

Unit

10
5
15

pi
pi
pi

Over specified temperature range; f = 1 MHz.
Unmeasured pins returned to ground.

202

8085·0239

ORDERING INFORMATION

lao PIO, 2.5 MHz
40·pln DIP
Z8420 PS
Z8420CS
Z8420 PE
Z8420CE
Z8420CM*
Z8420CMS*

laOB PIO, 6.0 MHz
40·pln DIP

44·plnLCC
Z8420 LM*
Z8420 LMS*t

Z8420SPS
Z8420SCS

laOA PIO, 4.5 MHz
40·pin DIP
44·pin LCC
Z8420A PS
Z8420A LM *
Z8420ACS
Z8420A LMS*t
Z8420APE
Z8420ACE
Z8420ACM*
Z8420ACMS*

Codes

First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = O°Cto +70°C
E = -40°Cto +85°C
M*= -55°Cto +125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
S = 883 Class S

Example: PS is a plastic DIP, O°C to + 70°C.

t Available soon.
* For Military Orders, contact your local Zllog Sales Office for Military Electrical Specifications.

00-2006-03

203

Z8430
Z80®CTC
Counter/Timer Circuit
Product
Specification

Zilog

April 1985

FEATURES
• Four independently programmable counter/timer
channels, each with a readable downcounter and a
selectable 16 or 256 prescaler. Downcounters are
reloaded automatically at zero count.
• Selectable positive or negative trigger initiates timer
operation.

• Interfaces directly to the Z80 CPU or-for baud rate
generation-to the Z80 SIO.
• Standard Z80 Family daisy-chain interrupt structure
provides fully vectored, prioritized interrupts without
external logic. The CTC may also be used as an interrupt
controller.

• Three channels have Zero Count/Timeout outputs
capable of driving Darlington transistors.

GENERAL DESCRIPTION
The Z80 CTC four-channel counter/timer can be
programmed by system software for a broad range of
counting and timing applications. The four independently
programmable channels of the Z80 CTC satisfy common
microcomputer system requirements for event counting,
interrupt and interval timing, and general clock rate
generation.

CPU
DATA

elle

CTC
CONTROL
FROM
CPU

---------

{--

DAISY {
CHAIN
INTERRUPT
CONTROL

D,

ClK/TRG,

D,

ZC/TO,

D,
D,

ClK/TRG,
ZC/TO,

D,
D,
D,

ClK/TRG,

D,

zcrro,

OE
CS,

-- - CS,
_ _ M1
__

ClK/TRG,
RESET

=Lu.
=r"~
-+--

iOiiQ

iiD
lEI

zao CTC
zaOA CTC

lEO

iNT

System design is simplified because the CTC connects
directly to both the Z80 CPU and the Z80 SIO with no
additional logic. In larger systems, address decoders and
buffers may be required.
Programming the CTC is straightforward: each channel is
programmed with two bytes; a third is necessary when

D,

D,

D5

D,

D,

D,

D,

D,

GND

+5V

iiD

ClK/TRG,

ZC/TO,

ClK/TRG,

ZC/TO,

ClK/TRG,

ZC/TO,

ClK/TRG,

IORQ

CS,

lEO

CS,

iNT

RESET

lEI

OE

Mi

ClK

ttt

ClK +5 V GND

Figure 1. Pin Functions
2041·001. 002

Figure 2a. 40-pin Dual-In-Llne Package (DIP),
Pin Assignments

205

interrupts are enabled. Once started, the CTC counts down,
automatically reloads its time constant, and resumes
counting. Software timing loops are completely eliminated.
Interrupt processing is simplified because only one vector
need be specified; the CTC internally generates a unique
vector for each channel.
The Z80 CTC requires a single + 5V power supply and the
standard Z80 single-phase system clock. It is fabricated with
n-channel silicon-gate depletion· load technology, and
packaged in a 28-pin and a 44-pin chip carrier DIP. (Figures
2aand 2b)

+CJ

Q'I, Q'O

6

5

•

+CJ

Q".J Qb< Q'" Q'l- Q"

3

2

Q~

+v

1 44 43 42 41 40

GND

7

39

NC

NC

8

38

NC

AD

9

37

+5V

10

36

NC

35

elK/TAGo

3'

NC
Cl.KfTRG1

ZC/TOo

NC

11

ZC/T01

12

ZC/T02

13

33

"

32

CLK/TRG2

15

31

CLK/TRG3

lEO

16

30

NC

NC

17

29

CS,

lORa
NC

Z8430
CTC

18 19 20 21 22 23 24 25 26 27 28

"v4-" "v ~ 4' "v vv'" {,,'v$'
v". "v
~"v
Figure 2b. 44-pin Chip Carrier, Pin Assignments

FUNCTIONAL DESCRIPTION
The Z80 CTC has four independent counter/timer channels.
Each channel is individually programmed with two words: a
control word and a time-constant word. The control word
selects the operating mode (counter or timer), enables or
disables the channel interrupt, and selects certain other
operating parameters. If the timing mode is selected, the
control word also sets a prescaler, which divides the system
clock by either 16 or 256. The time-constant word is a value
from 1 to 256.
During operation, the individual counter channel counts
down from the preset time constant value. In counter mode
operation the counter decrements on each of the ClK/TRG
input pulses until zero count is reached. Each decrement is
synchronized by the system clock. For counts greater than
256, more than one counter can be cascaded. At zero
count, the down-counter is automatically reset with the time
constant value.
The timer mode determines time intervals as small as 41"s
(Z80A) or 6.4 I"s (Z80) without additional logic or software
timing loops. Time intervals are generated by dividing the
system clock with a prescaler that decrements a preset
down-cou nter.

Thus, the time interval is an integral multiple of the clock
period, the prescaler value (16 or 256), and the time
constant that is preset in the down-counter. A timer is
triggered automatically when its time constant value is
programmed, or by an external ClKITRG input.
Three channels have two outputs that occur at zero count.
The first output is a zero-count/timeout pulse at the ZC/TO
output. The fourth channel (Channel 3) does not have a
ZC/TO output; interrupt request is the only output available
from Channel 3.
The second output is Interrupt Request (INT), which occurs
ifthe channel has its interrupt enabled during programming.
When the Z80 CPU acknowledges Interrupt Request, the
Z80 CTC places an interrupt vector on the data bus.
The four channels of the Z80 CTC are fully prioritized and fit
into four contiguous slots in a standard Z80 daisy-chain
interrupt structure. Channel 0 is the highest priority and
Channel 3 the lowest. Interrupts can be individually enabled
(or disabled) for each of the four channels.

ARCHITECTURE
The ClC has lour major elements, as shown in Figure 3.
• CPU bus I/O
• Channel control logic
•

Interrupt logic

• Counter/timer circuits

CPU Bus 1/0. The CPU bus I/O circuit decodes the address
inputs, and interfaces the CPU data and control signals to
the CTe for distribution on the internal bus.

206

Internal Control Logic. The ClC internal control logic
controls overall chip operating functions such as the chip
enable, reset, and read/write logic.
Interrupt Logic. The interrupt control logic ensures that the
CTe interrupts interface properly with the Z80 CPU interrupt
system. The logic controls the interrupt priority olthe eTC as
a function of the lEI signal. If lEI is High, the eTC has priority.
During interrupt processing, the interrupt logic holds lEO
low, which inhibits the interrupt operation on lower priority
devices. If the lEI input goes low, priority is relinquished
and the interrupt logic drives lEO low.
2041·003

DATA

iNf

CPU
BUS
110

FROM {
80 CPU

lEI
lEO

CONTROL

ZCITO

Figure 3. Functional Block Diagram

If a channel is programmed to request an interrupt, the
interrupt logic drives lEO Low at the zero count, and
generates an INT signal to the Z80 CPU. When the Z80 CPU
responds with interrupt acknowledge (M1 and IORO), then
the interrupt logic arbitrates the CTC internal priorities, and
the interrupt control logic places a unique interrupt vector on
the data bus.
If an interrupt is pending, the interrupt logic holds lEO Low.
When the Z80 CPU issues a Return From Interrupt (RETI)
instruction, each peripheral device decodes the first byte
(ED16). If the device has a pending interrupt, it raises lEO
(High) for one M1 cycle. This ensures that all lower priority
devices can decode the entire RET!. instruction and reset
properly.

CounterlTimer Circuits. The CTC has four independent
counter/timer circuits, each containing the logic shown in
Figure 4.
Channel Control Logic. The channel control logic
receives the 8-bit channel control word when the
counter/timer channel is programmed. The channel control
logic decodes the control word and sets the following
operating conditions:

• Interrupt enable (or disable)
• Operating mode (timer or counter)
• Timer mode prescaler factor (16 or 256)
• Active slope for CLKITRG input
• Timer mode trigger (automatic or CLKITRG input)
• Time constant data word to follow
• Software reset

ZC/TO

Figure 4. CounterlTlmer Block Diagram

2041'()04. 005

Time Constant Register. When the counter/timer channel
is programmed, the time constant register receives and
stores an 8-bit time constant value, which can be anywhere
from 1 to 256 (0 = 256). This constant is automatically
loaded into the down-counter when the counter/timer
channel is initialized, and subsequently after each zero
count.
Prescaler. The prescaler, which is used only in timer mode,
divides the system clock frequency by a factor of either 16 or
256. The prescaler output clocks the down-counter during
timer operation. The effect of the prescaler on the
down-counter is a multiplication of the system clock period
by 16 or 256. The prescaler factor is programmed by bit 5 of
the channel control word.

207

Ia

Down-Counter. Prior to each count cycle, the
down-counter is loaded with the time constant register
contents. The counter is then decremented one of two ways,
depending on operating mode:
• By the prescaler output (timer mode)
• By the trigger pulses into the CLKITRG input (counter
mode)

Without disturbing the down-count. the Z80 CPU can read
the count remaining at any time by performing an I/O read
operation at the port address assigned to the ClC channel.
When the down-counter reaches the zero count, the ZCITO
output generates a positive-going pulse. When the interrupt
is enabled, zero count also triggers an interrupt request
signal (INT) from the interrupt logic.

PROGRAMMING
Each Z80 ClC channel must be programmed prior to
operation. Programming consists of writing two words to the
1/0 port that corresponds to the desired channel. The first
word is a control word that selects the operating mode and
other parameters; the second word is a time constant, which
is a binary data word with a value from 1 to 256. A time
constant word must be preceded by a channel control word.

Reset. The CTC has both hardware and software resets.
The hardware reset terminates all down-counts and disables
all ClC interrupts by resetting the interrupt bits in the control
registers. In addition, the ZC/TO and Interrupt outputs go
inactive, lEO reflects lEI, and Do-D7 go to the
high-impedance state. All channels must be completely
reprogrammed after a hardware reset.

After initialization, channels may be reprogrammed at any
time. If updated control and time constant words are written
to a channel during the count operation, the count
continues to zero before the new time constant is loaded into
the counter.

The software reset is controlled by bit 1 in the channel
control word. When a channel receives a software reset, it
stops counting. When a software reset is used, the other bits
in the control word also change the contents of the channel
control register. After a software reset a new time constant
word must be written to the same channel.

If the interrupt on any Z80 ClC channel is enabled, the
programming procedure should also include an interrupt
vector. Only one vector is required for all four channels,
because the interrupt logic automatically modifies the vector
for the channel requesting service.
A control word is identified by a 1 in bit O. A 1 in bit 2 indicates
a time constant word is to follow. Interrupt vectors are always
addressed to Channel 0, and identified by a 0 in bit o.

Addressing. During programming, channels are
addressed with the channel select pins CS1 and CS2. A 2-bit
binary code selects the appropriate channel as shown in the
follOWing table.

CSo

Channel

o

o
o

Interrupt Enable. D7 enables the interrupt, so that an

Interrupt output (INT) IS generated at zero count. Interrupts
may be programmed in either mode and may be enabled or
disabled at any time.
Mode. D6 selects either timer or counter operating mode.

1

Presca/er Factor. (Timer Mode
factor-either 16 or 256.

J

1 ENABLESINTERRUPTj
INTERRUPT

o DISABLES INTERRUPT

Channel Control Word Programming. The channel
control word is shown in Figure 5. It sets the modes and
parameters described below.

o
o

2
3

If the channel control word has both bits D1 and D2 set to 1,
the addressed channel stops operating, pending a new time
constant word. The channel is ready to resume after the new
constant is programmed. In timer mode, if D3 = 0,
operation is triggered automatically when the time constant
word is loaded.

MODE
o SELECTS TIMER MODE
1 SELECTS COUNTER MODE
PRESCALER VALUE*
1 = VALUE OF 256
o = VALUE OF 18
CLKITRO EDGE SELECTION _ _ _-I
o SELECTS FALLING EDGE
1 SELECTS RISING EDGE

t

L

Only).

Ds selects

CONTROL OR VECTOR
0= VECTOR
1 = CONTROL WORD
RESET
CONTINUED OPERATION
1 = SOFTWARE RESET

o=

TIME CONSTANT

o = NO TIME CONSTANT FOLLOWS
1 = TIME CONSTANT FOLLOWS

L..._ _ _ TIMER TRIGGER'
o = AUTOMATIC TRIGGER WHEN
TIME CONSTANT IS LOADED
1 = CLKITRG PULSE STARTS TIMER
'TlMER MODE ONLY

Figure 5. Channel Control Word

208

2041·006

ClocklTrigger Edge Selector. 0 4 selects the active edge or
slope of the ClK/TRG input pulses. Note that
reprogramming the ClKITRG slope during operation is
equivalent to issuing an active edge. If the trigger slope is
changed by a control word update while a channel is
pending operation in timer mode, the result is the same as a
ClK/TRG pulse and the timer starts. Similarly, if the channel
is in counter mode, the counter decrements.

not operate without a time constant value. The only way to
write a time constant value is to write a control word with 02
set.

Timer Trigger (Timer Mode Only). 03 selects the trigger
mode for timer operation. When 03 is reset to 0, the timer is
triggered automatically. The time constant word is
programmed during an 1/0 write operation, which takes one
machine cycle. At the end of the write operation there is a
setup delay of one clock period. The timer starts
automatically (decrements) on the rising edge of the second
clock pulse (T2) of the machine cycle following the write
operation. Once started, the timer ru ns conti nuously. At zero
count the timer reloads automatically and continues
counting without interruption or delay, until stopped by a
reset.

Time Constant Programming. Before a channel can start
counting it must receive a time constant word from the CPU.
During programming or reprogramming, a channel control
word in which bit 2 is set must precede the time constant
word to indicate that the next word is a time constant. The
time constant word can be any value from 1 to 256 (Figure
6). Note that 0016 is interpreted as 256.

When 03 is set to 1, the timer is triggered externally through
the ClKITRG input. The time constant word is programmed
during an I/O write operation, which takes one machine
cycle. The timer is ready for operation on the rising edge of
the second clock pulse (T2) of the following machine cycle.
Note that the first timer decrement follows the active edge of
the ClK/TRG pulse by a delay time of one clock cycle if a
minimum setup time to the rising edge of clock is met. If this
minimum is not met, the delay is extended by another clock
period. Consequently, for immediate triggering, the
ClK/TRG input must precede T2 by one clock cycle plus its
minimum setup time. If the minimum time is not met, the
timer will start on the third clock cycle (T3)'

• The time constant (T), which is programmed into the time
constant register

Once started the timer operates continuously, without
interruption or delay, until stopped by a reset.
Time Constant. A 1 in 02 indicates that the next word
addressed to the selected channel is a time constant data
word for the time constant register. The time constant word
may be written at any time.

Software Reset. Setting 01 to 1 causes a software reset,
which is described in the Reset section.
Control Word. Setting Do to 0 identifies the word as a control
word.

In timer mode, the time interval is controlled by three factors:
• The system clock period (~)
• The prescaler factor (P), which multiplies the interval by
either 16 or 256

Consequently, the time interval is the product of ~ x P x T.
The minimum timer resolution is 16x~ (41's with a 4MHz
clock). The maximum timer interval is 256 x ~ x 256 (16.4
ms with a 4MHz clock). For longer intervals timers may be
cascaded.

Interrupt Vector Programming. If the Z80 CTC has one or
more interrupts enabled, it can supply interrupt vectors to
the Z80 CPU. To do so, the Z80 CTC must be
pre-programmed with the most-significant five bits of the
interrupt vector. Programming consists of writing a vector
word to the I/O port corresponding to the Z80 CTC Channel
O. Note that Do of the vector word is always zero, to
distinguish the vector from a channel control word. 01 and
02 are not used in programming the vector word. These bits
are supplied by the interrupt logic to identify the channel
requesting interrupt service with a unique interrupt vector
(Figure 7). Channel 0 has the highest priority.

A 0 in 02 indicates no time constant word is to follow. This is
ordinarily used when the channel is already in operation and
the new channel control word is an update. A channel will

I

V7-V3~
SUPPLIED
BY USER

::: ~~
~ ~L:
L'== :~:
TCs

TC,

TC4

Te3

Figure 6. Time Constant Word

2041·007,008

~L

0
j

= INTERRUPT VECTOR WORD
= CONTROL WORD

CHANNEL IDENTIFIER
(AUTOMATICALLY INSERTED
BY CTC)
CHANNEL 0
o 0
o j
CHANNEL j
j
0
CHANNEL 2
1 1 = CHANNEL 3

=
=
=

Figure 7. Interrupt Vector Word

209

PIN DESCRIPTION
CEo Chip Enable (input, active Low). When enabled the CTC
accepts control words, interrupt vectors, or time constant
data words from the data bus during an 1/0 write cycle; or
transmits the contents olthe downcounter to the CPU during
an 1/0 read cycle. In most applications this signal is
decoded from the eight least significant bits of the address
bus for any of the four 1/0 port addresses that are mapped to
the four counter-timer channels.

ClK. System Clock (input). Standard single-phase Z80
system clock.

ClK/TRGo·ClK/TRG3' External ClocklTlmer Trigger
(input, user-selectable active High or Low). Four pins
corresponding to the four Z80 CTC channels. In counter
mode, every active edge on this pin decrements the
downcounter. In timer mode, an active edge starts the timer.

CS O·CS 1 • Channel Select (inputs active High). Two-bit
binary address code selects one of the four CTC channels
for an I/O write or read (usually connected to Ao and Al)'
SYSTEM
BUSES

~
CPU_
INT

T

~

V
PIO

--L

-

INT

lEI

+5V

T
ZC/T01

CTC

!NT

i---<

lEO

-

INT

•

WIRDYB

data and commands between the Z80 CPU and the Z80
CTC.

lEI. Interrupt Enable In (input, active High). A High indicates
that no other interrupting devices of higher priority in the
daisy chain are being serviced by the Z80 CPU.
lEO. Interrupt Enable Out (output, active High). High only if
lEI is High and the Z80 CPU is not servicing an interrupt
from any Z80 CTC channel. lEO blocks lower priority
devices from interrupting while a higher priority interrupting
device is being serviced.

INT. Interrupt Request (output, open drain, active Low). Low
when any Z80 CTC channel that has been programmed to
enable interrupts as a zero-count condition in its
downcounter.
IORQ. Input/Output Request (input from CPU, active Low).
Used with CE and RD to transfer data and channel control
words between the Z80 CPU and the Z80 CTC. During a
write cycle, 10RO and CE are active and RD inactive. The
Z80 CTC does not receive a specific write signal; rather, it
internally generates is own from the inverse of an active RD
signal. In a read cycle, 10RO, CE, and RD are active; the
contents of the downcounter are read by the Z80 CPU. If
10RO and M1 are both true, the CPU is acknowledging an
interrupt request, and the highest priority interrupting
channel places its interrupt vector on the Z80 data bus.

M1. Machine Cycle One (input from CPU, active Low).
When M1 and 10RO are active, the Z80 CPU is
acknowledging an interrupt. The Z80 CTC then places an
interupt vector on the data bus if it has highest priority, and if
a channel has requested an interrupt (IND.
RD. Read Cycle Status J!!put, active Low). Used in
conjunction with 10RO and CE to transfer data and channel
control words between the Z80 CPU and the Z80 CTC.

lEI

ZC/T02

00.07' System Data Bus (bidirectional, 3-state). Transfers all

.

lEI

ROY

DMA

SIO

1J1-----l\
I\r--V

RESET. Reset (input active Low). Terminates all
down-counts and disables all interrupts by resetting the
interrupt bits in all control registers; the ZC/TO and the
interrupt outputs go inactive; lEO reflects lEI; 00-07 go to the
high-impedance state.
ZC/TOo·ZC/T02' Zero CountlTimeout (output, active
High). Three ZCITO pins corresponding to Z80 CTC
channels 2 through 0 (Channel 3 has no ZCITO pin). In both
counter and timer modes the output is an active High pulse
when the downcounter decrements to zero.

Figure S. A Typical ZSO Environment

210

2041-009

TIMING
Read Cycle Timing. Figure 9 shows read cycle timing. This
cycle reads the contents of a down-counter without
CPU
disturbing the count. During clock cycle T2, the
initiates a read cycle by driving the following inputs low: RD,
IORQ, and CEo A 2-bit binary code at inputs CS1 and CS a
selects the channel to be read. M1 must be High to
distinguish this cycle from an interrupt acknowledge.

zao

CLK

X

X
I
I

CHANNEL ADDRESS

\
\
-

M1

DATA

Timer Operation. In the timer mode, a ClK/TRG pulse
input starts the timer (Figure 11) on the second succeeding
rising edge of ClK. The trigger pulse is asynchronous, and
it must have a minimum width. A minimum lead time (21 0 ns)
is required between the active edge of the ClK/TRG and the
next rising edge of ClK to enable the prescaler on the
following clock edge. If the ClKITRG edge occurs closer
than this, the initiation of the timer function is delayed one
clock cycle. This corresponds to the start-up timing
discussed in the programming section. The timer can also
be started automatically if so programmed by the channel
control word.

CLK/TRO

--.,..--------------,

-"

INTERNAL
TIMER

Figure 9. Read Cycle Timing

Write Cycle Timing. Figure 10 shows write cycle timing for
loading control, time constant, or vector words.
The CTC does not have a write signal input, so it generates
one internally when the read (RD) input is High during T1.
During T210RQ and CE inputs are low. M1 must be High to
distinguish a write cycle from an interrupt acknowledge. A
2-bit binary code at inputs CS 1 and CS a selects the channel
to be addressed, and the word being written is placed on the
data bus. The data word is latched into the appropriate
register with the rising edge of clock cycle T3.

zao

T,

ST"RT TIMING

Figure 11. Timer Mode Timing

-----------<

T,

-------...1

T,

TWA

Counter Operation. In the counter mode, the ClK/TRG
pulse input decrements the downcounter. The trigger is
asynchronous, but the count is synchronized with ClK. For
the decrement to occur on the next rising edge of ClK, the
trigger edge must precede ClK by a minimum lead time as
shown in Figure 12. If the lead time is less than specified, the
count is delayed by one clock cycle. The trigger pulse must
have a minimum width, and the trigger period must be at
least twice the clock period. If the trigger repetition rate is
faster than '/3 the clock frequency, then TsCTR(Cs), AC
Characteristics Specification 26, must be met.
The ZCITO output occurs immediately after zero count, and
follows the rising ClK edge.

T,

CLK

CSo. CS,.

..JX,-__

CE _ _ _

_..JXI..___

C_H_AN_N_EL_A_D_D_RE_S_S

'''-_ _-..JI

_ --or-------------,

RD

CLK/TRO

INTERNAL
COUNTER

----.If

ZC/TO _ _ _ _ _"

• .1

_M1 --or-------------,

Figure 12. Counter Mode Timing

_J

DATA _ _ _ _-..JX~

____

IN___

..JX~

_________

Figure 10. Write Cycle Timing

2041-010.011.012.013

211

INTERRUPT OPERATION

zao

The
CTC follows the Z80 system interrupt protocol for
nested priority interrupts and return from interrupt, wherein
the interrupt priority of a peripheral is determined by its
location in a daisy chain. Two lines-lEI and lEO-in the CTC
connect it to the system daisy chain. The device closest to
the + 5V supply has the highest priority (Figure 13). For
additional information on the Z80 interrupt structure, refer to
the zao CPU Product Specification and the zao CPU
Technical Manual.
HIGHEST PRIORITV
DEVICE

LOWEST PRIORITY

DEVICE

Figure 13. Daisy-Chain Interrupt Priorities

Within the Z80 CTC, interrupt priority is predetermined by
channel number: Channel 0 has the highest priority, and
Channel 3 the lowest. If a device or channel is being
serviced with an interrupt routine, it cannot be interrupted by
a device or channel with lower priority until service is
complete. Higher priority devices or channels may interrupt
the servicing of lower priority devices or channels.
A Z80 CTC channel may be programmed to request an
interrupt every time its downcounter reaches zero. Note that
the CPU must be programmed for interrupt mode 2. Some
time after the interrupt request, the CPU sends an interrupt
acknowledge. The CTC interrupt control logic determines
the highest priority channel that is requesting an interrupt.
Then, if the CTC lEI input is High (indicating that it has
priority within the system daisy chain) it places an 8-bit

interrupt vector on the system data bus. The high-order five
bits of this vector were written to the CTC during the
programming process; the next two bits are provided by the
CTC interrupt control logic as a binary code that identifies
the highest priority channel requesting an interrupt; the
low-order bit IS always zero.

Interrupt Acknowledge Timing. Figure 14 shows
interrupt acknowledge timing. After an interrupt request, the
Z80 CPU sends an interrupt acknowledge (M1 and IORO).
All channels are inhibited from changing their interrupt
request status when M1 is active-about two clock cycles
earlier than IORO. RO is High to distinguish this cycle from
an instruction fetch.
The CTC interrupt logic determines the highest priority
channel requesting an interrupt. If the CTC interrupt enable
input (lEI) is High, the highest priority interrupting channel
within the CTC places its interrupt vector on the data bus
when IORO goes Low. Two wait states (TWA) are
automatically inserted at this time to allow the daisy chain to
stabilize. Additional wait states may be added.

Return from Interrupt Timing. At the end of an interrupt
service routine the RETI (Return From Interrupt) instruction
initializes the daisy chain enable lines for proper control of
nested priority interrupt handling. The CTC decodes the
2-byte RETI code internally and determines whether it is
intended for a channel being serviced. Figure 15 shows
RETI timing.
If several Z80 peripherals are in the daisy chain, lEI settles
active (High) on the chip currently being serviced when the
opcode E0 16 is decoded. If the following opcode is 4016,
the peripheral being serviced is released and its lEO
becomes active. Additional wait states are allowed.

T,

T,

T,

T,

T,

T,

T,

T,

T,

CLK

CLK

\\-_____..JI
\\.-_-JI

M'1\

I
I

iffi\
Do-D7

\

\

I
I

ED

IEI- - - - - - - ,

______ J

OATA

-----------.(G§0~VE;;;C;;TO;R0---Figure 14. Interrupt Acknowledge Timing

212

lEO

r-

- - - -_ _ _ _- - - - 1
Figure 15. Return From Interrupt Timing

2041·014.015.016

ABSOWTE MAXIMUM RATINGS
Voltages on all pins with respect
to ground ......................... - O.3V to + 7V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. -65°Cto + 150°C

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

TEST CONDITIONS
The DC characteristics and capacitance section below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND (OV).
Positive current flows into the referenced pin.

Package Information section. Refer to the Literature List for
additional documentation.
+5V

Available operating temperature ranges are:
•

S = O°Cto +70°C, +4.75V~Vee~ +5.25V

•

E

•

M

2.1K

= -400Cto +85°C, +4.75V~Vee~ +5.25V
= -55°Cto +125°C, +4.5V~Vee~ +5.5V

The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the

DC CHARACTERISTICS
Symbol

Parameter

VILe

Clock Input Low Voltage

VIHe

Clock Input High Voltage

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

ICC
III

Power Supply Current:

ILO
IOHD

Darlington Drive Current

Min
-0.3

Max
+0.45

Unit

Condition

V

Vee- 0.6
-0.3

Vee+ 0.3
+0.8

V

+2.0

Vee
+0.4

V

V
V I O L = 2.0mA

+120

V
mA

Input leakage Current

±10

J.lA

VIN = 0.4 to Vee

3-State Output leakage Current in Float

±10

J.lA
mA

VOUT = 0.4 to vee
VOH = 1.5V

+2.4

-1.5

IOH = -250J.lA

REXT = 390Q

CAPACITANCE

Max

Unit

Symbol

Parameter

ClK

Clock Capacitance

20

pi

CIN

Input Capacitance

5

pi

COUT

Output Capacitance

15

pi

TA = 25°C. f = 1 MHz
Unmeasured pins returned to ground.

2041·017

213

I~
1,...--,
3

CLOCK

r-

..J
~

f-(n-2)TDIEI(IEOf) + TDM1(IEO) + TsIEI(IO) + TIL buffer
delay, if any. RESET must be active lor a minimum of 3 clock cycles.
Units are nanoseconds unless otherwise specilled

215

AC CHARACTERISTICS (Continued)
Z80ACTC

zaOCTC

Number Symbol

Parameter

Min

Max

Min

Max

Z80BCTC
Max

Min

Notest

150

[5]

26

TsCTR(Cs)

CLKITRG t to Clock t Setup
Time for Immediate
Count
300

27

TsCTR(Ct)

CLKITRG t to Clock t Setup
Time for enabling of
Prescaler on following
clockt
210

28

TdC(ZCITOr)

Clock t to ZC/TO t Delay

260

190

140

29

TdC(ZCITDQ

Clock ~ to ZCITD ~ Delay

190

190

140

210

210

150

[4]

NarES:

[1] TeC = TwCh + TwCl + TrC + TtC.
[2] Increase delay by 10 ns for each 50 pf increase in loading, 200 pf
maximum for data lines, and 100 pf for control lines.
[3] Increase delay by 2 ns for each 10 pf increase in loading, 100 pf
maximum
[4] Timer mode
[5] Counter mode.

[6] Parenthetical numbers reference the table number of a parameter,
e.g., (1) refers to TcC.
t 2.5TcC>(n-2)TDIEI(IEOf) + TDM1(IEO) + TsIEI(IO) + TIL buffer
delay, if any. RESET must be active for a minimum of 3 clock cycles.
Units are nanoseconds unless otherwise specified.

ORDERING INFORMATION
28-pln DIP

Z80 CTC, 2.5 MHz
44-pin LCC

Z8430 PS
Z8430 CS
Z8430 PE
Z8430CE
Z8430CM*
Z8430CMB*

Z80A CTC, 4.0 MHz
28-pln DIP
44-pin LCC
Z8430A PS
Z8430A CS
Z8430APE
Z8430ACE
Z8430ACM*
Z8430ACMB*

Z8430 LM *
Z8430 LMB*t

Z8430A LM *
Z8430A LMB • t

Z80B CTC, 6.0 MHz
28-pinDIP
Z8430 PS
Z8430CS
Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = O°Cto + 70°C
E = -40°C to +85°C
M*= -55°C to +125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DIP, O°C to + 70°C.

t Available soon
* For MIlitary Orders, contact your local Zilog Sales Offce for Military Electrical Specifications
216

Z8440/1/2/4 Z80® SIO

Serial Input/Output
Controller

Zilog

Product
Specification

April 1985

FEATURES
• Two independent full-duplex channels, with separate
control and status lines for modems or other devices.
•

Data rates of 0 to 500K bits/second in the x1 clock mode
with a 2.5 MHz clock (Z80 SIO), or 0 to 800K bits/second
with a 4.0 MHz clock (Z80A SIO).

• Asynchronous protocols: everything necessary for
complete messages in 5, 6, 7, or 8 bits/character.
Includes variable· stop bits and several clock-rate
multipliers; break generation and detection; parity;
overrun and framing error detection.

• Synchronous protocols: everything necessary for
complete bit- or byte-oriented messages in 5, 6, 7, or 8
bits/character, including IBM Bisync, SDLC, HDLC,
CCITT-X.25 and others. Automatic CRC generation/
checking, sync character and zero insertion/deletion,
abort generation/detection, and flag insertion.
• Receiver data registers quadruply buffered, transmitter
registers doubly buffered.
• Highly sophisticated and flexible daisy-chain interrupt
vectoring for interrupts without external logic.

GENERAL DESCRIPTION
The Z80 SIO SeriallnputiOutput Controller is a dual-channel
data communication interface with extraordinary versatility
and capability. Its basic functions as a serial-to-parallel,
parallel-to-serial converter/controller can be programmed
by a CPU for a broad range of serial communication
applications.
The device supports all common asynchronous and
synchronous protocols, byte- or bit-oriented, and performs
all of the functions traditionally done by UARTs, USARTs,
and synchronous communication controllers combined,
plus additional functions traditionally performed by the CPU.
Moreover, it does this on two fully-independent channels,

with an exceptionally sophisticated interrupt structure that
allows very fast transfers.
Full interfacing is provided for CPU or DMA control. In
addition to data communication, the circuit can handle
virtually all types of serial I/O with fast, or slow, peripheral
devices. While designed primarily as a member of the Z80
family, its versatility makes it well suited to many other CPUs.
The Z80 SIO is an n-channel silicon-gate depletion-load
device packaged in a 40-pin plastic or ceramic DIP. It uses a
single + 5V power supply and the standard Z80 family
single-phase clock. The Z8444 is packaged in a 44-pin
ceramic LCC.

PIN DESCRIPTION
Figures 1 through 6 illustrate the three 40-pin configurations
(bonding options) available in the SIO. The constraints of a
40-pin package make it impossible to bring out the Receive
Clock (RxC), Transmit Clock (TxC) , Data Terminal Ready
(DTR) and Sync (SYNC) signals for both channels.
Therefore, either Channel B lacks a signal or two signals are
bonded together:

The 44-pin package, the Z80 SIOI4, has all options (Figure
7).
The first bonding option above (SI0/2) is the preferred
version for most applications. The pin descriptions are as
follows:

• Z80 S10/1 lacks DTRB

B/A. Channel A or B Select (input, High selects Channel B).
This input defines which channel is accessed during a data
transfer between the CPU and the SIO. Address bit Ao from
the CPU is often used for the selection function.

• Z80 SIO/O has all four signals, but TxCB and RxCB are
bonded together

C/O. Control or Data Select (input, High selects Control).
This input defines the type of information transfer performed

• Z80 S10/2 lacks SYNCB

217

I-...

•S
N

CPU
DATA
BUS

CONTROL
FROM
CPU

-------

Do

RxDA

0,

RiCA

0,

TxDA

0,

TxCA

0,

SYNCA

OS

W/RDVA

0,

-----

--

RTSA

CE

DflIA _
DCDl

Z8442
Z80S10/2

CHANNEL A

lEI

M1
iOiiO

RxDB

AD

RxeB

TxDB

TxCB

c/o

B/A

c/o
AD

SYNCA

RTSB

-}~...

INT

CTSB

lEI

D'i'RB _ _ _

lEO

iiCiiB

CHANNEL 8

CONTROL

CE

M1
IV/liD'i'A

\iI/RDVB

B/A

-,{

-----

0,
IORQ

lEO

+sv

RESET

CHAIN
INTERRUPT
CONTROL

02
0,

iN't

CONTROL

Do

Os

0,

-}~.u

0,

CTSA

0,
0,

GND
IV/RDYB

RxOA

RxDS

RiCA

RxCl!

TxCA

~

TxDA

Tl1DB

I>fIiA

DflIII

RTSA

RTSB

CTSA

CTSB

DCDA

DCDB

ClK

REID

111

+sv

GND

ClK

Figure 1. Pin Functions

CPU
DATA
BUS

CONTROL
FROM
CPU

-------

DO

RxDA

0,

RxCA

02

TxDA

0,

TiCA

0,
W/iffiYA

Os

..," {

Do

0,

02

Os

0,

07

iNf

0,
IORQ

lEI

CE

lEO

B/A

M1

c/o
AD

+sv

RESET

M1

RxDB

IV/liD'i'A

IORQ

RiCB

SVNCA

AD

TxDi!

RxDA

SYNCB

TxCB

RiCA
TxCA

RxCii

TxDA

~

SVNCB

B/A

RTSB

INT

C'i'S!

lEI

DC DB

:::=}~

lEO

...

CONTROL

CHANNELS

I>fIiA
RTSlI
CTSA

DCiiA
ClK

11

+5V

GND

GND
W/_

RxOS

Tl1DB

Ii'ifl
C'i'S!

00Dii
RESET

ClK

Figure 3. Pin Functions

218

CHANNEL A

CONTROL

Z8441
Z80SIO/1

CE

0,

}.~D

RTSlI

c/o

CHAIN
INTERRUPT
CONTROL

-----

0,
07

Figure 2. 40-pln Dual-in-Line Package (DIP),
Pin Assignments

Figure 4. 40-pin Dual-In-Llne Package (DIP),
Pin Assignments

2042-001, 002, 003, 004

DO

RxDA

RiCA

---

CPU
DATA
BUS

CONTROL
FROM
CPU

TxDA

---

D,

TxCA

D,

SYNCA
W/RDYA

D,

-CHANNEL A

D,

A'fSA

D7

---

CE
lIESET

C'fSA
IlTIIl _
ZB440
ZBOSIO/O IiClIA

I.fi

iORo

RxDB

IIiTiillI

iii)

TxDB
SYNCB

.. i

iii'Si

~,

}-

--

INT

CTSB

lEI

DTRB

lEO

DCDB

1

+5V

GND

4

3

2

D7

D,

_

CONTROL

CE
B/A

I.fi

cm

+5V

RD
GND
W/_

RxDA

SYNCB

RiCA
TxCA

RxDB

TxDA

-}--

lORa

lEO

SYNCA

Rx1lcCB
1lcDB

ii'i'iiA

DTRB

RTSA

IImi

C'fU

caa

DCDA

DCDB

ClK

RESET

ClK

Figure 6. 40'pln Dual·ln·Line Package (DIP),
Pin Assignments

ClK. System Clock (input). The SIO uses the standard Z80
System Clock to synchronize internal signals. This is a
single-phase clock.

~ "4
5

D.

W/FmYA

Figure 5. Pin Functions

6

D2

D,

lEI

CHANNELS

Do

D,

INT

CONTROL

W/RDYB

B/A

CHAIN
INTERRUPT
CONTROL

D,

1 44 43 42 41 40

lEI

7

39

BlA

CTSA, CTSB. Clear To Send (inputs, active Low). When

lEO

8

38

C/D

M1

9

37

iiii

+5V

10

W/FmYA

11

programmed as Auto Enables, a Low on these inputs
enables the respective transmitter. If not programmed as
Auto Enables, these inputs may be programmed as
general-purpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow-risetime signals. The SIO
detects pulses on these inputs and interrupts the CPU on
both logic level transitions. The Schmitt-trigger buffering
does not guarantee a specified noise-level margin.

ZB444
SIO

38

GND

35

W/RDYB

SYNCA

12

34

SYNCB

RxDA

13

33

AlDB

RxCA

14

32

1lcCA

15

31

RiiCi
1iiCii

1lcDA

16

30

1lcDB

NC

17

28

NC

18 19 20 21 22 23 24 25 28 27 28

Figure 7. 44·pln Chip Carrier,
Pin Assignments

between the CPU and the SIO. A High at this input during a
CPU write to the SIO causes the information on the data bus
to be interpreted as a command for the channel selected by
B/A. A Low at C/O means that the information on the data
bus is data. Address bit Aj is often used for this function.

CEo Chip Enable (I nput, active Low). A Low level at this input
enables the SIO to accept command or data input from the
CPU during a write cycle, or to transmit data to the CPU
during a read cycle.
2042-005, 006, 014

00.07' System Data Bus (bidirectional, 3-state). The system
data bus transfers data and commands between the CPU
and the Z80 SIO. Do is the least significant bit.

OCOA, OCOB. Data Carrier Detect (inputs, active Low).
These pins function as receiver enables if the SIO is
programmed for Auto Enables; otherwise they may be used
as general-purpose input pins. Both pins are Schmitt-trigger
buffered to accommodate slow-risetime signals. The SIO
detects pulses on these pins and interrupts the CPU on both
logic level transitions. Schmitt-trigger buffering does not
guarantee a specific noise-level margin.
OTRA, OTRB. Data Terminal Ready (outputs, active Low).
These outputs follow the state programmed into the Z80
SIO. They can also be programmed as general-purpose
outputs.
In the Z80 SI0/1 bonding option, DTRB is omitted.

219

lEI. Interrupt Enable In (input, active High). This signal is
used with lEO to form a priority daisy chain when there is
more than one interrupt-driven device. A High on this line
indicates that no other device of higher priority is being
serviced by a CPU interrupt service routine.
lEO. Interrupt Enable Out (output, active High). lEO is High
only if lEI is High and the CPU is not servicing an interrupt
from this SIO. Thus, this signal blocks lower priority devices
from interrupting while a higher priority device is being
serviced by its CPU interrupt service routine.

RTSA, RTSB. Request To Send (outputs, active Low).
When the RTS bit in Write Register 5 (Figure 14) is set, the
RTS output goes Low. When the RTS bit is reset in the
Asynchronous mode, the output goes High after the
transmitter is empty. In Synchronous modes, the RTS pin
strictly follows the state ofthe RTS bit. Both pins can be used
as general-purpose outputs.

10RO is used in conjunction with BiA, ciB, CE, and RD to
transfer commands and data between the CPU and the SIO.
When CE, RD, and 10RO are all active, the channel selected
by BiA transfers data to the CPU (a read operation). When
CE and 10RO are active, but RD is inactive, the channel
selected by BiA is written to by the CPU with either data or
control information as ~cified by C/O'. As mentioned
previously, if 10RO and Ml are active simultaneously, the
CPU is acknowledging an interrupt and the SIO
automatically places its interrupt vector on the CPU data bus
if it is the highest priority device requesting an interrupt.

SYNCA, SYNCB. Synchronization (bidirectional, active
Low). These pins can act either as inputs or outputs. In the
asynchronous receive mode, they are inputs similar to CTS
and DCD. In this mode, the transitions on these lines affect
the state of the SynclHunt status bits in Read Register 0
(Figure 13), but have no other function. In the External Sync
mode, these lines also act as inputs. When external
synchronization is achieved, SYNC must be driven Low on
the second rising edge of RxC after that rising edge of RxC
on which the last bit of the sync character was received. In
othrr words, after the sync pattern is detected, the external
logic must wait for two full Receive Clock cycles to activate
the SYNC input. Once SYNC is forced Low, it should be kept
Low until the CPU informs the external synchronization
detect logic that synchronization has been lost or a new
message is about to start. Character assembly begins on
the riSing edge of RxC that immediately precedes the falling
edge of SYNC in the External Sync mode.

M1. Machine Cycle One.Q!put from zao CPU, active Low).
When Ml is active and RD is also active, the zao CPU is
fetching an instruction from memory; when M1 is active
while'iC5Fm is active, the SIO accepts M1 and 10RO as an
interrupt acknowledge if the SIO is the highest priority
device that has interrupted the zao CPU.

In the internal synchronization mode (Monosync and
Bisync), these pins act as outputs that are active during the
part of the receive clock (RXC) cycle in which sync
characters are recognized. The sync condition is not
latched, so these outputs are active each time a sync pattern
is recognized, regardless of character boundaries.

RxCA, RxCB. Receiver Clocks (inputs). Receive data is
sampled on the rising edge of RxC. The Receive Clocks
may be 1, 16,32, or 64 times the data rate in asynchronous
modes. These clocks may be driven by the zao CTC
Counter Timer Circuit for programmable baud rate
generation. Both inputs are Schmitt-trigger buffered; no
noise level margin is specified.

In the zao SI0/2 bonding option, SYNCB is omitted.

INT. Interrupt Request (output, open drain, active Low).
When the SIO is requesting an interrupt, it pulls INT Low.

lORa. Input/Output Request (input from CPU, active Low).

In the zao SIOIO bonding option, RxCB is bonded together
with TxCB.

RD. Read Cycle Status (input from CPU, active Low). If RD is
active, a me!!)~or 1/0 read operation is in progress. RD is
used with BIA, CE, and 10RO to transfer data from the SIO to
the CPU.
RxDA, RxDB. Receive Data (inputs, active High). Serial
data at TTL levels.

RESET. Reset (input, active Low). A Low RESET disables
both receivers and transmitters, forces TxDA and TxDB
marking, forces the modem controls High, and disables all
interrupts. The control registers must be rewritten after the
SIO is reset and before data is transmitted or received.

220

TxCA, 'nI:CB. 7i"ansmitter Clocks (inputs). In asynchronous
modes, the Transmitter Clocks may be 1, 16, 32, or 64 times
the data rate; however, the clock multiplier must be the same
for the transmitter and the receiver. The Transmit Clock
inputs are Schmitt-trigger buffered for relaxed rise- and
fall-time requirements; no noise level margin is specified.
Transmitter Clocks may be driven by the zao CTC Counter
Timer Circuit for programmable baud rate generation.
In the zao SIOIO bonding option, TxCB is bonded together
with RxCB.

'nI:DA, 'nI:DB. 7i"ansmit Data (outputs, active High). Serial
data at TTL levels. TxD changes from the falling edge of TxC.
W/RDYA, W/RDYB. Wait/Ready (outputs, open drain when
programmed for Wait function; driven High and Low when
programmed for Ready function). These dual-purpose
outputs may be programmed as Ready lines for a DMA
controller or as Wait lines that synchronize the CPU to the
SIO data rate. The reset state is open drain.

FUNCTIONAL DESCRIPTION
The functional capabilities of the Z80 810 can be described
from two different points of view: as a data communications
device, it transmits and receives serial data in a wide variety
of data-communication protocols; as a Z80 family
peripheral, it interacts with the Z80 CPU and other
peripheral circuits, sharing the data, address and control
buses, as well as being a part of the Z80 interrupt structure.
As a peripheral to other microprocessors, the 810 offers
valuable features such as non-vectored interrupts, polling,
and simple handshake capability. Figure 8 is a block
diagram.
DATA

Figure 9 illustrates the conventional devices that the 810
replaces.
CONTROL

The first part of the following discussion covers 810
data-communication capabilities; the second part
describes interactions between the CPU and the 810.

) ~!~)tL

)gr~~~iL
SYNC
WAIT/READY

I...-

•a
N

Figure S. Block Diagram

UART

CHANNEL
A
SYNCHRONOUS
COMMUNICATIONS
CONTROLLER

MICROPROCESSOR {
INTERFACE

-.---.-1

-

UART

SYNCHRONOUS
COMMUNICATION
CONTROLLER

B

MICROPROCESSOR
INTERFACE
........

zao

CHANNEL
A

SIO

-

CHANNEL

B

Figure 9. Conventional Devices Replaced by the ZSO SIO

2042·007.008

221

DATA COMMUNICATION CAPABILITIES
The SIO provides two independent full-duplex channels that
can be programmed for use in any common asynchronous,
or synchronous data-communication protocol. Figure 10a
illustrates some of these protocols. The following is a short
description of them. A more detailed explanation of these
modes can be found in the ZBO SIO Technical Manual
(03-3033-01 ).

The SIO does not require symmetric transmit and receive
clock signals, a feature that allows it to be used with a Z80
CTC or many other clock sources. The transmitter and
receiver can handle data at a rate of 1, 1/16, 1/32, or 1/64 of
the clock rate supplied to the receive and transmit clock
inputs.
In asynchronous modes, the SYNC pin may be
programmed as an input that can be used for functions such
as monitoring a ring indicator.

Asynchronous Modes. Transmission and reception can
be done independently on each channel with five to eight
bits per character, plus optional even or odd parity. The
transmitters can supply one, one-and-a-half, or two stop bits
per character and can provide a break output at any time.
The receiver break-detection logic interrupts the CPU both
at the start and end of a received break. Reception is
protected from spikes by a transient spike-rejection
mechanism that checks the signal one-half a bit time after a
Low level is detected on the receive data input (RxDA or
RxDB in Figure 5). If the Low does not persist, as in the case
of a transient, the character assembly process is not started.

Synchronous Modes. The SIO supports both byteoriented and bit-oriented synchronous communication.
Synchronous byte-oriented protocols can be handled in
several modes that allow character synchronization with an
8-bit sync character (Monosync), any 16-bit sync pattern
(Bisync), or with an external sync signal. Leading sync
characters can be removed without interrupting the CPU.
Five-, six-, or seven-bit sync characters are detected with Bor 16-bit patterns in the SIO by overlapping the larger
pattern across multiple incoming sync characters, as shown
in Figure 10b.

Framing errors and overrun errors are detected and
buffered together with the partial character on which they
occurred. Vectored interrupts allow fast servicing of error
conditions using dedicated routines. Furthermore, a built-in
checking process avoids interpreting a framing error as a
new start bit: a framing error results in the addition of
one-half a bit time to the point at which the search for the
next start bit is begun.

CRC checking for synchronous byte-oriented modes is
delayed by one character time so the CPU may disable CRC
checking on specific characters. This permits implementation of protocols such as IBM Bisync.

Figure 10a. Some zao SIO Protocols
PARITY

lT

P

STr

-MA-R""KIN""G..,.U""NE,----.I "1-D-AT-A-'I-l,I""11""I1 "1-D-AT-A-'11'"l11'"l11""l11

DATA

III

, MARKING LINE

ASYNCHRONOUS

::
::

DATA

SYNC

I

DATA

CRC1

CRC2

DATA

CRC,

CRC,

DATA

CRC1

CRC,

CRC,

CRC,

MONOSYNC

SYNC

SYNC

DATA
SIGNAL

I

!

BISYNC

:;

DATA

EXTERNAL SYNC
FLAG

I

ADDRESS

I

INFO{M:TION

FLAG

SDLC'HDLC'X.25

Figure 10b. Six-Bit Sync Character Recognition
5 BITS
~

SYN~

I

SYNC

I

DATA

DATA

DATA

DATA

----------

8
'----.....v..-----"
16

Figure 10. Data Communication

222

2042·009, 010

Both CRC-16 (X 16 + X15 + X2 + 1}andCCITT(X16 + X12
+ X5 + 1} error checking polynomials are supported. In all
non-SDLC modes, the CRC generator is initialized to as; in
SDLC modes, it is initialized to 1s. The SIO can be used for
interfacing to peripherals such as hard-sectored floppy
disks, but it cannot generate or check CRC for
IBM-compatible soft-sectored disks. The SIO also provides
a feature that automatically transmits CRC data when no
other data is available for transmission. This allows very
high-speed transmissions under DMA control with no need
for CPU intervention at the end of a message. When there is
no data or CRC to send in synchronous modes, the
transmitter inserts 8- or 16-bit sync characters regardless of
the programmed character length.
The SIO supports synchronous bit-oriented protocols such
as SDLC and HOLC by performing automatic flag sending,
zero insertion, and CRC generation. A special command
can be used to abort a frame in transmission. At the end of a
message the SIO automatically transmits the CRC and
trailing flag when the transmit buffer becomes empty. If a
transmit underrun occurs in the middle of a message, an
external/status interrupt warns the CPU of this status change
so that an abort may be issued. One to eight bits per
character can be sent, which allows reception of a message
with no prior information about the character structure in the
information field of a frame.

The receiver automatically synchronizes on the leading flag
of a frame in SDLC or HOLC, and provides a
synchronization signal on the SYNC pin; an interrupt can
also be programmed. The receiver can be programmed to
search for frames addressed by a single byte to only a
specified user-selected address or to a global broadcast
address. In this mode, frames that do not match either the
user-selected or broadcast address are ignored. The
number of address bytes can be extended under software
control. For transmitting data, an interrupt on the first
received character or on every character can be selected.
The receiver automatically deletes all zeroes inserted by the
transmitter during character assembly. It also calculates and
automatically checks the CRC to validate frame
transmission. At the end of transmission, the status of a
received frame is available in the status registers.
The SIO can be conveniently used under DMA control to
provide high-speed reception or transmission. In reception,
for example, the SIO can interrupt the CPU when the first
character of a message is received. The CPU then enables
the DMA to transfer the message to memory. The SIO then
issues an end-of-frame interrupt and the CPU can check the
status of the received message. Thus, the CPU is freed for
other service while the message is being received.

1/0 INTERFACE CAPABILITIES
The SIO offers the choice of polling, vectored or
non-vectored interrupts and block-transfer modes to
transfer data, status, and control information to, and from,
the CPU. The block-transfer mode can also be implemented
under DMA control.

Polling. Two status registers are updated at appropriate
times for each function being performed (for example, CRC
error-status valid at the end of a message). When the CPU is
operated in a polling fashion, one of the SIO's two status
registers is used to indicate whether the SIO has some data
or needs some data. Depending on the contents of this
register, the CPU will either write data, read data, or just go
on. Two bits in the register indicate that a data transfer is
needed. In addition, error and other conditions are
indicated. The second status register (special receive
conditions) does not have to be read in a polling sequence,
until a character has been received. All interrupt modes are
disabled when operating the device in a polled
environment.
Interrupts. The SIO has an elaborate interrupt scheme to
provide fast interrupt service in real-time applications. A
control register and a status register in Channel B contain
the interrupt vector. When programmed to do so, the SIO
can modify three bits of the interrupt vector in the status
register so that it points directly to one of eight interrupt
service routines in memory, thereby servicing conditions in
both channels and eliminating most of the needs for a
status-analysis routine.
Transmit interrupts, receive interrupts, and external/status
interrupts are the main sources of interrupts. Each interrupt

source is enabled under program control, with Channel A
having a higher priority than Channel B, and with receive,
transmit, and external/status interrupts prioritized in that
order within each channel. When the transmit interrupt is
enabled, the CPU is interrupted by the transmit buffer
becoming empty. (This implies that the transmitter must
have had a data character written into it so it can become
empty.) The receiver can interrupt the CPU in one of two
ways:
• Interrupt on first received character
• Interrupt on all received characters
Interrupt-on-first-received-character is typically used with
the
block-transfer mode.
Interrupt-on-all-receivedcharacters has the option of modifying the interrupt vector in
the event of a parity error. Both ofthese interrupt modes will
also interrupt under special receive conditions on a
character or message basis (end-of-frame interrupt in
SDLC, for example). This means that the special-receive
condition can cause an interrupt only if the
interrupt-on-first-received-character or interrupt-on-allreceived-characters mode is selected. In interrupt-on-firstreceived-character, an interrupt can occur from
special-receive conditions (except parity error) after the
first-received-character interrupt (example: receive-overrun
interrupt).
The main function of the external/status interrupt is to
monitor the signal transitions of the Clear To Send (CTS) ,
Data Carrier Detect (DCD), and Synchronization (SYNC)
pins (Figures 1 through 7). In addition, an external/status

223

I-...

•a
N

SYSTEM
BUSES

interrupt is also caused by a CRC-sending condition, or by
the detection of a break sequence (asynchronous mode) or
abort sequence (SDLC mode) in the data stream. The
interrupt caused by the break/abort sequence allows the
SIO to interrupt when the break/abort sequence is detected
or terminated. This feature facilitates the proper termination
of the current message, correct initialization of the next
message, and the accurate timing of the break/abort
condition in external logic.

A

...

'I

y
DMA
INT

In a ZeD CPU environment (Figure 11), SIO interrupt
vectoring is "automatic:" the SIO passes its internallymodifiable a-bit interrupt vector to the CPU, which adds an
additional a bits from its interrupt-vector (I) register to form
the memory address of the interrupt-routine table. This table
contains the address olthe beginning olthe interrupt routine
itself. The process entails an indirect transfer of CPU control
to the interrupt routine, so that the next instruction executed
after an interrupt acknowledge by the CPU is the first
instruction of the interrupt routine itself.

r-

RDY
lEI

ZCITO,

-

CTC

CPUlDMA Block 1l'ansfer. The SIO's block-transfer mode
accommodates both CPU block transfers and DMA
controllers (ZaO DMA or other designs). The block-transfer
mode uses the Wait/Ready output signal, which is selected
with three bits in an internal control register. The Wait/Ready
output signal can be programmed as a WAIT line in the CPU
block-transfer mode or as a READY line in the DMA
block-transfer mode.

lED
RxCA

I

TxCA
RxCB

fiCi
WiRDvA
WIRDYB

J

iNr

•

lEI

•

RDY

DMA

SIO

To a DMA controller, the SIO READY output indicates that
the SIO is ready to transfer data to, or from, memory. To the
CPU, the WAIT output indicates that the 810 is not ready to
transfer data, thereby requesting the CPU to extend the I/O
cycle.

A

...

'I

y

Figure 11. ~plcal ZSO Environment

INTERNAL STRUCTURE
The internal structure of the device includes a zao CPU
interface, internal control and interrupt logic, and two
full-duplex channels. Each channel contains its own set of
control and status (write and read) registers, and control and
status logic that provides the interface to modems or other
external devices.
The registers for each channel are designated as follows:
WRO-WR7 - Write Registers 0 through 7
RRO-RR2 - Read Registers 0 through 2
The register group includes five a-bit control registers, two
sync-character registers and two status registers. The
interrupt vector is written into an additional a-bit register
(Write Register 2) in Channel B that may be read through
another a·bit register (Read Register 2) in Channel B. The bit
assignment and functional grouping of each register is
configured to simplify and organize the programming
process. Table 1 lists the functions assigned to each read or
write register.
The logic for both channels provides formats,
synchronization, and validation for data transferred to and
from the channel interface. The modem control inputs, Clear
To Send (CTS) and Data Carrier Detect (DCD), are
224

Table 1. Register Functions
Read Register Functions
RRO

Transmit/Receive buffer status, interrupt status and
external status

RR1

Special Receive Condition status

RR2

Modified interrupt vector (Channel B only)

Write Register Functions
WRO

Register pOinters, CRC initialize, and initialization
cornmands for the various modes.

WR1

Transmit/Receive interrupt and data transfer mode
definition.

WR2

Interrupt vector (Channel B only)

WR3

Receive parameters and control

WR4

Transmit/Receive miscellaneous parameters and modes

WR5

Transmit parameters and controls

WR6

Sync character or SDLC address field

WR7

Sync character or SDLC flag
2042·011

monitored by the external control and status logic under
program control. All external control-and-status-Iogic
signals are general-purpose in nature and can be used for
functions other than modem control.

Data Path. The transmit and receive data path illustrated for
Channel A in Figure 12 is identical for both channels. The
receiver has three a-bit buffer registers in a FIFO
arrangement, in addition to the a-bit receive shift register.
This scheme creates additional time for the CPU to service
an interrupt at the beginning of a block of high-speed data.

Incoming data is routed through one of several paths (data
or CRC) depending on the selected mode and-in
asynchronous modes-the character length.
The transmitter has an a-bit transmit data buffer register that
is loaded from the internal data bus, and a 20-bit transmit
shift register that can be loaded from the sync-character
buffers or from the transmit data register. Depending on the
operational mode, outgoing data is routed through one of
four main paths before it is transmitted from the Transmit
Data output (TxD).

l-i' l
CPU I/O

I-...

TOCHANNELS, - - - - - - - - - - - - - - - - - - ' ' ' ' ' ' - - - - - - - - - - - - - - - - EXTERNAL STATUS LOGIC,
CONTROL LOGIC

-------"""'----....,.0::--------,

•a
N

TxDA

Figure 12. '1l'ansmit and Receive Data Path (Channel A)

2042'()12

225

PROGRAMMING
The system program first issues a series of commands that
initialize the basic mode of operation and then issues other
commands that qualify conditions within the selected mode.
For example, the asynchronous mode, character length,
clock rate, number of stop bits, even or odd parity might be
set first; then the interrupt mode; and finally, receiver or
transmitter enable.
80th channels contain registers that must be programmed
via the system program prior to operation. The channelselect input (8/A) and the control/data (C/O) are the
command-structure addressing controls, and are normally
controlled by the CPU address bus. Figures 15 and 16
illustrate the timing relationships for programming the write
registers and transferring data and status.

Read Registers. The SIO contains three read registers for
Channel 8 and two read registers for Channel A (RRO-RR2
in Figure 13) that can be read to obtain the status
information; RR2 contains the internally-modifiable interrupt
vector and is only in the Channel 8 register set. The status
information includes error conditions, interrupt vector, and
standard communications-interface signals.
To read the contents of a selected read register other than
RRO, the system program must first write the pointer byte to
WRO in exactly the same way as a write register operation.
Then, by executing a read instruction, the contents of the
addressed read register can be read by the CPU.
The status bits of RRO and RR1 are carefully grouped to
simplify status monitoring. For example, when the interrupt
vector indicates that a Special Receive Condition interrupt
has occurred, all the appropriate error bits can be read from
a single register (RR1).

WRO is a special case in that all of the basic commands can
be written to it with a single byte. Reset (internal or external)
initializes the pointer bits 00-02 to point to WRO. This implies
that a channel reset must not be combined with the pointing
to any register.
READ REGISTER 0

III ~I

Rx CHARACTER AVAILABLE
I L- INT
L..::=
PENDING (CH. A ONLy)

~~gUFFER

EMPTY

}

SYNC/HUNT
CTS
Tx UNDERRUN/EOM
BREAK/ABORT

*

·Used With "External/Status Interrupt" Modes

READ REGISTER 1 t

I~I~I~I~I~I~I~I~I
L-ALLSENT
I FI ELD BITS
I FIELD BITS IN
}
IN PREVIOUS SECOND PREVIOUS
BYTE
BYTE

1
0
1
0
1
0
1
0

0
1
1
0
0
1
1
0

0
0
0
1
1
1
1
0

o

3

o
o
o
o
o

4
5
6
7
8
8
8

1
2

•

'---- PARITY ERROR
-RxOVERRU N ERROR
CRC/FRAMI NG ERROR
END OF FR AME(SDLC)

* Residue data for eight Rx bits/character programmed
tUsed with speCial receive condition mode

READ REGISTER 2 (Channel B only)

Write Registers. The SIO contains eight write registers for
Channel 8 and seven write registers for Channel A
(WRO-WR7 in Figure 14) that are programmed separately to
configure the functional personality of the channels; WR2
contains the interrupt vector for both channels and is only in
the Channel 8 register set. With the exception of WRO,
programming the write registers requires two bytes. The first
byte is to WRO and contains three bits (0 0-02) that point to
the selected register; the second byte is the actual control
word that is written into the register to configure the SIO.

226

I~I~I~I~I~I~I~I~I

III ~I
Ll::=~~t}
~~f

V4

INTERRUPT
VECTOR

V5
V6
V7

tVanable.f "Status Affects Vector" is programmed

Figure 13. Read Register Bit Functions

2042-013

WRITE REGISTER 4

WRITE REGISTER 0
0

I I I
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

REGISTER
REGISTER
REGISTER
REGISTER
REGISTER

0
1
2
3
4
REGISTER 5
REGISTER 6
REGISTER 7

SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1'/2 STOP BITS/CHARACTER
2 STOP BITS/CHARACTER

B BIT SYNC CHARACTER
16 BIT SYNC CHARACTER
SDLC MODE (01111110 FLAG)
EXTERNAL SYNC MODE

NULL COD E
SEND ABO RT (SDLC)
RESET EXT/ STATUS INTERRUPTS
CHANNEL RESET
ENABLE IN T ON NEXT Rx CHARACTER
RESET TxlN T PENDING
ERROR RE SET
RETURN FROM INT (CH·A ONLY)

Xl CLOCK MODE
X16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE

NULL CODE
RESET Rx CRC CHECKER
RESET Tx CRC GENERATOR
RESET Tx UNDERRUN/EOM LATCH

I-...

WRITE REGISTER 5

WRITE REGISTER 1

I~I~I~I~I~I~I~I~I

III

I

I

EXT INT ENABLE
Tx INT ENABLE
L----STATUS AFFECTS VECTOR
(CH. B ONLY)

Rx INT DISABLE
}
Rx INT ON FIRST CHARACTER
INT ON ALL Rx CHARACTERS (PARITY AFFECTS VECTOR)
INT ON ALL Rx CHARACTERS (PARITY DOES NOT AFFECT
VECTOR)

•a
N

Tx 5 BITS (OR LESSVCHARACTER
Tx 7 BITSfCHARACTER

•

Tx 6 BITS/CHARACTER
Tx 8 BITS/CHARACTER
DTR

'---WAIT/READY ON R/T
'---WAIT/READY FUNCTION
L----WAIT/READY ENABLE
*Or on special condition
WRITE REGISTER 2 (Channel B only)

WRITE REGISTER 6

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

IIII~V4
I I ~f:}

INTERRUPT
VECTOR

IIIII1 ~imiiH}
.

SYNC BIT 3

*

SYNC BIT 4

SYNC BIT 5

V5
V6
V7

SYNC BIT 6
SYNC BIT 7
* Also SOLC address field

WRITE REGISTER 7

WRITE REGISTER 3

I~I~I~I~I~I~I~I~I

I I II II I L!:::::~~~g ::~; }
I
~~~~~SYNC
IlJ~~~~~'

SYNC
SYNC
SYNC
SYNC
SYNC

Rx 5 BITS/CHARACTER
Rx 7 BITS/CHARACTER

BIT
BIT
BIT
BIT
BIT
BIT

ii
12
10
13
14
15

•

*For SOLC it must be programmed to "01111110" for flag recognition

Rx 6 BITS/CHARACTER
Rx 8 BITS/CHARACTER

Figure 14. Write Register Bit Functions

2042·014

227

TIMING
The SIO must have the same clock as the CPU (same phase
and frequency relationship, not necessarily the same
driver).
Read Cycle. The timing signals generated by a Z80 CPU
input instruction to read a data or status byte from the SIO
are illustrated in Figure 15.
Write Cycle. Figure 16 illustrates the timing and data
signals generated by a Z80 CPU output instruction to write a
data or control byte into the SIO.
Interrupt-Acknowledge Cycle. After receiving an
interrupt-request signal from an SIO (INT pulled Low), the
Z80 CPU sends an interrupt-acknowledge sequence, M1
Low and 10RO Low, a few cycles later (Figure 17).

The SIO contains an internal daisy-chained interrupt
structure for prioritizing nested interrupts for the various
functions of its two channels, and this structure can be used
within an external user-defined daisy chain that prioritizes
several peripheral circuits.
The lEI of the highest-priority device is terminated High. A
device that has an interrupt pending or under service forces
its lEO Low. For devices with no interrupt pending or under
service,IEO=IEI.
To insure stable conditions in the daisy chain, all interrupt
status signals are prevented from changing while M1 is Low.
When 10RO is Low, the highest priority interrupt requestor
T,

T,

Tw

T,

(the one with lEI High) places its interrupt vector on the data
bus and sets its internal interrupt-under-service latch.
Return From Interrupt Cycle. Figure 18 illustrates the
return from interrupt cycle. Normally, the Z80 CPU issues a
Return From Interrupt (RETI) instruction at the end of an
interrupt service routine. RETI is a 2-byte opcode (EO-40)
that resets the interrupt-under-service latch in the SIO to
terminate the interrupt that has just been processed. This is
accomplished by manipulating the daisy chain in the
following way.

The normal daisy-chain operation can be used to detect a
pending interrupt; however, it cannot distinguish between
an interrupt under service and a pending unacknowledged
interrupt of a higher priority. Whenever EO is decoded, the
daisy chain is modified by forcing High the lEO of any
interrupt that has not yet been acknowledged. Thus the
daisy chain identifies the device presently under service as
the only one with an lEI High and an lEO Low. If the next
opcode byte is 40, the interrupt-under-service latch is reset.
The ripple time of the interrupt daisy chain (both the
High-to-Low and the Low-to-High transitions) limits the
number of devices that can be placed in the daisy chain.
Ripple time can be improved with carry-look-ahead, or by
extending the interrupt-acknowledge cycle. For further
information about techniques for increasing the number of
daisy-chained devices, refer to the zao CPU Product
Specification in this document.

T,

CLOCK

CLOCK

CE, C/i), ali

M1

I

\~_ _ _ _ _......,:
I

iiD

''---+-':I
iiD-----------+I----I

iii1

lEI

IORQ

G0

DATA

DATA

Figure 15. Read Cycle
T,

T,

Tw

:\:::::

----------(8)---Figure 17. Interrupt Acknowledge Cycle

T,

T,
CLOCK

CLOCK

CE, C/i),

:::::::::7

Bli _ _~"+

_____+-__~''-_

iiD----------------r--------

iii1---------------T---------DATA _ _ _ _ _ _ _ _ _ _ _ _

X3:X____

Figure 16. Write Cycle

228

IEI------

I

------,/

lEO _ _ _ _ _ _ _ _ _ _

...J-.Jr-

Figure 18. Return from Interrupt Cycle
2044·008, 009, 010, 011

ABSOWTE MAXIMUM RATINGS
Voltages on all pins with respect
toGND .......................... -0.3Vto+7V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This IS a stress rating only;
operation of the device at any condition above those indicated in the

operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the
Package Information section. Refer to the Literature List for
additional documentation.

STANDARD TEST CONDITIONS
The DC characteristics and capacitance sections listed
below apply for the following standard test conditions,
unless otherwise noted. All voltages are referenced to GND
(OV). Positive current flows into the referenced pin.

+5V
2.1K

I...

Available operating temperature ranges are:
• S = OOeto +70 o e, +4.75V"Vcc" +5.25V

N

•
S

• E = -40 0 eto +85°e, +4.75V"Vcc" +5.25V
•

M = -55°eto +125°C, +4.5V"Vcc" +5.5V

DC CHARACTERISTICS

Symbol

Parameter

VILC

Clock Input Low Voltage

VIHC

Clock Input High Voltage

VIL

Min

Max

-0.3

+0.45

Unit
V
V

VCC-0.6

VCC+0.3

Input Low Voltage

-0.3

+0.8

V

VIH

Input High Voltage

+2.0

V

VOL

Output Low Voltage

VCC
+0.4

VOH

Output High Voltage

V
V

+2.4

+10/-40

jlA
jlA
jlA

100

mA

III

Input Leakage Current

±10

IOL

3-State Output Leakage Current in Float

±10

IL(Sy)

SYNC Pin Leakage Current

ICC

Power Supply Current

Test Condition

= 2.0mA
= - 25O IlA
VIN = OtoVCC
VOUT = O.4VtoVCC
IOL

IOH

O

CPl

A - (HL)
HL -HL+l
BC - BC-l

CPIR

A - (HL)


I

HL - HL+l
BC-BC-l
Repeat until
A
(HL) 0'
BC = 0

I

11 101 101 ED

21

10 110 001 Bl

16

11 101 101 ED
10 101 001 A9

16

11 101 101 ED

21

lfBC:;:Oand
A,. (HL)

10 11l 001 B9

16

lfBC=Oor

IfBC?: Dand
A,. (HL)
IfBC=Oor
A
(HL)

=

=

CPD

A - (HL)
HL - HL-l
BC-BC-I

CPDR

A - (HL)


X

I

I

X

I


e - 2 In the opcode provides an e!leclLve eddreu 01 pc + e liS PC 'I Incremented
by 2 prior 10 the addllLon 01 e

Call and
Return Group

CALL nn

ISP-1) - PCH
ISP-2) - PCL
PC - nn

CALL ce, nn

If conchhon
CC IS

false

continue,
otherwise same as

· · ·..
··x ·x ·
X

X

11 001 101 CO

17

II ",,100

10

If cc

17

If CC II true.

18

hllse.

CALLnn

RET

PCL - ISP)
PCH - ISP+ 1)

RET cc

If condlhon
cc 18 false
continue,

· · ·
·· · ·
X

X

II 001 001 C9

X

X

II co 000

10

II

otherwise
same as
RET
RETI

Return from

RETN1

Return from

Interrupt

non-maskable
mterrupt

RST p

NOTE

Input and
Output Group

ISP-1) - PCH
ISP-2) - PCL
peH - 0
peL - p

A - In)

IN" (e)

, - (C)

INIR

· ·
· · ·
·· · ·
X

X

X

X

X

X

II
01
11
01

101
001
101
000

101
101
101
101

II

I

III

(HL) - Ie)
B - B-1
HL-HL-1
IHL) - Ie)
B - B-1
HL-HL-1

INO
INOR

X

X

X

X

P

0

14

II

I

9

Condlbon

000 NZ

non~zero

001
010
011
100

zero
non-carry

Z
Ne
C
PO
101 PE
110 P
111 M

co",!,

panlyodd
parity even
sign po81bve
sign negative

~ SoH

08H
10H
ISH
20H
2BH
30H
3BH

II 011 011 DB

II

II 101 101 ED
01
000

12

16

CloAO - A7
B to As - AI5

21

eloAo - A7
B 10 AS - A1S

,

OUT In), A

8=0
In) - A

OUTIC)"

(C) - ,
Ie) - IHL)
B - B-1
HL-HL+1
Ie) - IHL)
8 - B-1
HL-HL+1

X

X

X

X

X

X

11 101 101 ED
10 100 010 A2

X

X

X

X

X

11 101 101 ED
10 110 010 B2

@
X

5
Ilf B .. O)
4
(If 8=0)

16

oII.
OporatIOD

(HL)
B - B-1
HL-HL-I
Repeat until B

Summary of
Flag
Operation

X

(C) -

I

X

X

X

X

Do,
lutrv.etioll

s

9,

X
X
X
X
X
X
X
X
X
X
X

SBC A, s, CP s, NEG

AND.
DEC a

ADD DO,

SI

ADC HL. sa
SBC HL ...
RLA. RLCA. RRA. RReA
RL m, RLC m; RR m,
RRe m, SLA m;
SRA m, SRL m

R1O. RRD
DM
CPL
SCF
CCF
INr(C)
INI. IND. OUTI. OUTD
INIR. INDR; OTIR. OTDR
1OI.1OD
LDIR; 10DR
CPl. CPIR; CPD. CPDR
1OA. I. LDA. R
BIT b. ,

X
X

I

X
X
X
X

I
I
X
X
X

0
0
0
I
I
0
X

0

X
X

I
I

X
X

X
X

X

0
0

X

I

X

X

I
X

PlY H

K

ADD A.•. ADC A. ,
SUB

Opcoclo
No.of Ho.ol M H••01 T
71 M3 110 lie. 8ytH ey.... StCl"

11 101 101 ED
10 111 011

S
(IfB .. O)

21

4

16

(If B=O)

INC.

260

C

=0

OR s, XORs

Symbolic
Notation

X

Flags
PlY N
K

X
X
X

X
X

X

X

X
X
X
X
X
X
X
X
X

V
V

P
P
V
V
V
V

X
X

X

X
X
X
X
X

0
I
0
0
0
I
0
0
I

Do

ComllWDt.

C toAo - A7
B toAg - AIS

C

Comments

I
I

B-blt add or add With carry
B-blt subtract, subtract with carry, compare and negate accumulator

~I

0

0
P
P

Logical operattons.

B-blt increment
8-bil decrement
16-blt add
I6-blt add With carry
IS-bit subtract with carry
Rotate accumulator
Rotate and shift locations
Rotate digit left and right
DeCimal adjust /lccumulator
Complement accumulator

Set carry.

P

X
X

X

X

X
X

I
0
I

X

IFF

X

X

X

:1
:1

Complement carry
Input register mdlrect
Block mput and output Z

= 0 If B ¢

0 otherWise Z = 0

Block transfer Instructions P/V = 1 If BC .,. 0, otherwise PlY = 0
Block search mstructlons Z = 1 If A = (HL), otherWise Z ::: 0 PlY = 1
If BC .,. 0, otherwise PlY = 0
The content of the mterrupt enable flip-flop (IFF) IS copied mto the P/V fldg.
The state of bit b of location S IS copied mto the Z nag

Symbol
Operation
SIgn flag. S = I If the MSB of the result IS l.
S
Zero flag. Z = I 11 the result of the operahon IS O.
Z
Partty or overflow flag. Partty (P) and overflow
P/V
(V) share the same flag. Logical operahons affect
thiS flag WIth the parlty of the result whIle
arlthmehc operations affect th,s flag WIth the
overflow of the result. If PIV holds parity, PIV =
I If the result of the operahon IS even, P/V = 0 if
result Is odd. If PIV holds overflow, PIV = I If
the result of the operahon produced an overflow.
Half·carry flag. H = I If the add or subtract
H
operahon produced a carry mto or borrow from
bit 4 01 the accumulator.
Add/Subtract flag. N = I If the prevlOUS opera·
N
hon was a subtract.
Hand N flags are used in conlunchon WIth the
H&N
deCimal adjust mstruchon (DAA) to properly cor·
rect the result mto packed BCD format followmg
addition or subtrachon usmg operands WIth
packed BCD format.
Carry/Link flag. C = I If the operation produced
C
a carry from the MSB of the operand or result.

Operation
Symbol
The flag IS affected accordmg to the result of the
I
operahon.
The flag IS unchanged by the operahon.
The flag IS reset by the operation.
0
The flag IS set by the operahon.
I
X
The flag IS indeterminate.
PIV flag affected accordmg to the overflow result
V
01 the operahon.
PIV flag affected accordmg to the parlty result of
P
the operahon.
Anyone of the CPU regIsters A, B. C, D, E. H, L.
Any B·b,t locahon lor all the addressmg modes
allowed lor the parhcular mstruchon.
Any I6·blt locahon for all the addressmg modes
ss
allowed for that mstruchon.
Anyone of the two mdex registers IX or IY.
11
Refresh counter.
R
B·blt value m range < 0, 255 >.
n
I6·b,t value m range < 0, 65535 >.
nn

2001-001

Pin
Descriptions

Au-AIS' Address Bus (output, achve High,
3-state). Ao-A15 form a l6-bit address bus. The
Address Bus provides the address for memory
data bus exchanges (up to 64K bytes) and for
I/O devlCe exchanges.

BUSACK. Bus Acknowledge (output, active
Low). Bus Acknowledge mdicates to the
requestmg devlCe that the CPU address bus,
data bus, and control signals MREQ, 10RQ,
RD, and WR have entered their hlghImpedance states. The external circuitry
can now control these hnes.
BUSREQ. Bus Request (mput, achve Low).
Bus Request has a higher pnonty than NMI
and is always recognized at the end of the current machme cycle. BUSREQ forces the CPU
address bus, data bus, and control signals
MREQ, 10RQ, RD, and WR to go to a hlghImpedance state so that other devlCes can
control these Imes. BUSREQ is normally WlreORed and requires an external pullup for
these apphcahons. Extended BUSREQ
pen ods due to extensive DMA operahons can
prevent the CPU from properly refreshmg
dynamic RAMs.

Do-D7' Data Bus (input/output, active High,
3-state). 00-07 constitute an 8-bit bidirectional
data bus, used for data exchanges with
memory and I/O.

HALT. Halt State (output, active Low). HALT
indicates that the CPU has executed a Halt
instruction and is awaiting either a nonmaskable or a maskable interrupt (with the
mask enabled) before operation can resume.
While halted, the CPU executes NOPs to
maintain memory refresh.

INT. Interrupt Request (input, active Low).
Interrupt Request is generated by I/O devlCes.
The CPU honors a request at the end of the
current instruction if the internal softwarecontrolled interrupt enable flip-flop (IFF) is
enabled. INT is normally wire-ORed and
requires an external pullup for these
applications.

IORQ. Input/Output Request (output, active
Low, 3-state). IORQ indicates that the lower
half of the address bus holds a valid I/O
address for an I/O read or write operation.
IORQ is also generated concurrently with Ml
during an interrupt acknowledge cycle to indicate that an interrupt response vector can be

placed on the data bus.

MI. Machine Cycle One (output, active Low).
MI, together with MREQ, indicates that the
current machine cycle is the opcode fetch
cycle of an instruction execution. MI, together
with IORQ, indicates an interrupt acknowledge
cycle.

MREQ. Memory Request (output, active
Low, 3-state). MREQ indicates that the address
bus holds a valid address for a memory read or
memory write operation.

NMI. Non-Maskable Interrupt (input, negative
edge-triggered). NMI has a higher pnority
than INT. NMI is always recognized at the end
of the current instruction, independent of the
status of the interrupt enable flip-flop, and
automatically forces the CPU to restart at
location 0066H.
RD. Read (output, active Low, 3-state). RD indicates that the CPU wants to read data from
memory or an 1/0 device. The addressed 1/0
device or memory should use this signal to
gate data onto the CPU data bus.

RESET. Reset (input, active Low). RESET
initializes the CPU as follows: it resets the
interrupt enable flip-flop, clears the PC and
Registers I and R, and sets the interrupt status
to Mode O. During reset time, the address and
data bus go to a high-impedance state, and all
control output signals go to the inactive state.
Note that RESET must be active for a minimum
of three full clock cycles before the reset
operation is complete.

RFSH. Refresh (output, active Low). RFSH,
together with MREQ, indicates that the lower
seven bits of the system's address bus can be
used as a refresh address to the system's
dynamic memories.
WAIT. Wait (input, active Low). WAIT
indicates to the CPU that the addressed memory or 1/0 devices are not ready for a data
transfer. The CPU continues to enter a Wait
state as long as this signal is active. Extended
WAIT periods can prevent the CPU from
refreshing dynamic memory properly.

WR. Write (output, active Low, 3-state). WR
indicates that the CPU data bus holds valid
data to be stored at the addressed memory or
1/0 location.

261

CPU Timing

• Interrupt acknowledge

The basic clock period is referred to as a
T time or cycle, and three or more T cycles
make up a machine cycle (Ml, M2 or M3 for
instance). Machine cycles can be extended
either by the CPU automatically inserting one
or more Wait states or by the insertion of one
or more Wait states by the user.

Instruction Opcode Fetch. The CPU places
the contents of the Program Counter (PC) on
the address bus at the start of the cycle (Figure
5). Approximately one-half clock ~le later,
MREQ goes active. When active, RD indicates
that the memory data can be enabled onto the
CPU data bus.

The CPU samples the WAIT input with the
falling edge of clock state T2. During clock
states T3 and T4 of an Ml cycle dynamiC RAM
refresh can occur while the CPU starts
decoding and executing the instruction. When
the Refresh Control signal becomes active,
refreshing of dynamiC memory can take place.

The CPU executes instructions by proceeding through a specific sequence of operations:
• Memory read or write
• I/O device read or write

T,

Tw·

T,

CLOCK

AO-A15

Do-D7

_...l...._J

~I~

~~--~.~--~r---------+----

~SH------------~;~.------_I~~t=_______-~~
*TW

= Walt cycle added when necessary for slow ancllliary devices.
Figure S. Instruction Opcode Fetch

262

2005·882

CPU

Timing
(Continued)

Memory Read or Write Cycles. Figure 6
shows the timing of memory read or write
cycles other than an opcode fetch (MI) cycle.
The MREQ and RD signals function exactly as
in the fetch cycle. In a memory write cycle,

MREQ also becomes active when the address
bus is stable. The WR line is active when the
data bus is stable, so that it can be used
directly as an R/W pulse to most semiconductor memories.

I

9

OPER'Z~II~:

1

WR

Do-D7

----~----~ll~--~®~----I~----

-------t===~;~~~~D~AT~A~O~UT~=====j
Figure 6. Memory Read or Write Cycles

2005·883

263

CPU

Timing
(Continued)

Input or Output Cycles. Figure 7 shows the
timing for an 1/0 read or 1/0 write operation.
During 1/0 operations, the CPU automatically

inserts a single Wait state (TWA). This extra Wait
state allows sufficient time for an 1/0 port to decode the address from the port address lines.

CLOCK

WAIT

_+-_+_+_____....!o._t....of./oo...J

1

OPERA~~~E 1

iiD

Do-D7

WA

WRI~~
OPERATION

TWA

1
DO-D7

------t:::::::::::::::::~::::~~~~::::::}
DATA OUT

= Walt cycle automahcally Inserted by CPU.
Figure 7. Input or Output Cycles

Interrupt Request/Acknowledge Cycle. The
CPU samples the interrupt signal with the rising edge of the last clock cycle at the end of
any instruction (Figure 8). When an interrupt
is accepted, a special Ml cycle is generated.
Teo

T,

During this Ml cycle, IORQ becomes active
(instead of MREQ) to indicate that the interrupting device can place an 8-bit vector on the
data bus. The CPU automatically adds two
Wait states to this cycle.

T,

CLOCK

AO-A15 _ _ _ _ _ _+-J~------~-+---4+~}--_#-_H-J\---

WAIT _ _ _ _ _ _~-------------~--*--J

Do-D7

ILl = Last state of any mstruchon cycle.
TWA = Walt cycle automatically Inserted by CPU

Figure 8. Interrupt Request! Acknowledge Cycle

264

2005·884, 885

CPU

Timing
(Continued)

Non-Maskable Interrupt Request Cycle.
NMI is sampled at the same time as the
maskable interrupt input INT but has higher
priority and cannot be disabled under software
control. The subsequent timing is similar to

that of a normal memory read operation except
that data put on the bus by the memory is
ignored. The CPU instead executes a restart
(RST) operation and jumps to the NMI service
routine located at address 0066H (Figure 9).

AO-A15

,...

IQ

MiiEQ

liD

a

RFiii

* Although NMI IS an asynchronous mput, to guarantee Its bemg recogmzed on the followmg machme cycle, NMI's fallIng edge must
occur no later than the rlsmg edge of the clock cycle precedmg the last state of any instructIon cycle (TU)'

Figure 9. Non·Maskable Interrupt Request Operation

Bus Request/Acknowledge Cycle. The CPU
samples BUSREQ with the rising edge of the
last clock period of any machine cycle (Figure
10). If BUSREQ is active, the CPU sets its
address, data, and MREQ, IORQ, RD, and WR

lines to a high-impedance state with the rising
edge of the next clock pulse. At that time, any
external device can take control of these lines,
usually to transfer data between memory and
I/O devices.

CLOCK

aUSREQ

Ao-A16

Do-D,

______

~-+---4~--_~-----J

==========t~-~/o---...:!:~-----t-<
======t=)-.o--------'!::~--_H

~:=========~=)-~~---~~----1_i

RD,Wii

10RQ

RFIN

HALT

--------------~
UNCHANGED

--------------~-----------------------

NarES: 1) TLM = Last ,tate of any M cycle.

2) TX = An arbitrary clock cycle used by requestmg deVIce.

Figure 10. Z-BUS Request/Acknowledge Cycle
2005-021B, BB6

265

CPU

Timing
(Continued)

When in the Halt state, the HALT output is active
and remains so until an interrupt is processed
(Figure II). INT will also force a Halt exit.

Halt Acknowledge Cycle. When the CPU receives a HALT instruction, it executes NOP states
until either an INT or NMI input is received.

M 1 - - -_ _ _- - - - - - - M 1 - - - - - - - _ ..- - - - - - M 1

CLOCK

___________

r~_·

U-

NMI

________

* Although NMI IS an asynchronous Input, to guarantee Its bemg recogmzed on the followmg machme cycle, NMI's falling edge must
occur no later than the rlsmg edge of the clock cycle precedmg the last state of any instructIon cycle (TLI)'

Figure II. Halt Acknowledge Cycle

Reset Cycle. RESET must be active for at least
three clock cycles for the CPU to properly accept
it. As long as RESET remains active, the address
and data buses float, and the control outputs are
inactive. Once RESET goes inactive, two internal

T cycles are consumed before the CPU resumes
normal processing operation. RESET clears the
PC register, so the first opcode fetch will be to
location 0000 (Figure 12).

_M1-----T,

T,

_____

@J~

Do-D7

~

~~---------F~lO~A-T-------------+-------------------

__________________-J7

MR~

~~------------------7~F~7~~------~(~/~--------------------------~---------------RFSH,
//1/1//
\ ________

BU~~~~

Figure 12. Reset Cycle

266

2005-887, 888

AC
Cbaracteristlc:st
Number Symbol

Z8300·1

Z8300·3

(1.0 MHz)
Min Max

(2.5 MHz)
Min Max

Parameter

(ns)

(ns)

(ns)

(ns)

TwCh

Clock Cycle TIme
Clock Pulse Width (HIgh)

1000"

2

470

2000

180

2000

3

TwCI

Clock Pulse Width (Low)

470

2000

180

2000

TcC

4
TfC
5-TrC

Clock Fall Time

30

30

Clock RIse Time

30

30
145

6

TdCr(A)

Clock t to Address Valid Delay

7

TdA(MREQf)

8

TdCf(MREQf)

Address Vahd to MREQ
1 Delay
Clock 1 to MREQ 1 Delay

TdCr(MREQr) Clock t to MREQt Delay
9
IO-TwMREQh--MREQ Pulse Width (HIgh)
II

TwMREQI

MREQ Pulse WIdth (Low)

12

TdCf(MREQr)
TdCf(RDf)

Clock 1 to MREQ t Delay

13

ThD(RDr)

17
18

TsWAIT(Cf)
ThWAIT(Cf)

380
370"

Data Hold TIme to RD t
WAIT Setup TIme to Clock 1

125"
260
260

410"
890"

100
100
170"--360"

260
340

Clock 1 to RD 1 Delay

TdCr(RDr)
Clock t to RD t Delay
14
15-TsD(Cr)---Data Setup Time to Clock t
16

400"

260
140

100
130
100
50--0

0
190

70
0

WAIT Hold TIme after Clock 1

TdCr(Mlf)
19
Clock t to Ml 1 Delay
20-TdCr(Mlr)--Clock t to Ml t Delay

340

0
130

340

130

21

TdCr(RFSHf)

Clock t to RFSH 1 Delay

460

180

22

TdCr(RFSHr)
TdCf(RDr)

Clock 1 to RFSH t Delay

390

Clock 1 to RD t Delay

290

23

TdCr(RDf)
24
Clock t to RD 1 Delay
25-TsD(Cf)---Data Setup to Clock 1 durmg
M2 • M3. ~ or M5 Cycles
26
27

TdA(lORQf)
TdCr(IORQf)

Address Stable prior to IORQ
Clock t to IORQ 1 Delay

28

TdCf(IORQr)

Clock 1 to IORQ t Delay

260
160
790'

TdD(WRf)
Data Stable prior to WR 1
29
30-TdCf(WRf)--Clock 1 to WR 1 Delay

470"

31

890"

TwWR
TdCf(WRr)

32

WR Pulse Width
Clock 1 to WR t Delay

TdD(WRf)
Data Stable prior to WR 1
33
34
TdCr(WRf)
Clock 1 to WR i Delay
35-TdWRr(D)--Data Stable from WR t
36
37
38

320240

90

290

110
190"

240

90
360"

260
-30"

100
30"

210
290"

TdCf(HALT)

Clock 1 to HALT t or 1
TwNMI
NMI Pulse Width
TsBUSREQ(Cr) BUSREQ Setup TIme to Clock t

150
110
100
60---

80
130"--

760

300

210

80

210

80

*For clock periods other than the minimUmS shown in the table, calculate parameters using the expressions in the table on the
following page.

Calculated values above assumed.

=

=

TrC TfC 20 ns.
tAll timmgs assume equalloadmg on pms within 50 pf.

267

51

0
t'I

Q
c:I

AC
Characteristicst
(Continued)

Z8300-1

Number Symbol

Parameter

Z8300-3

Max
(ns)

Min
(ns)

39
ThBUSREQ(Cr) BUSREQ Hold Time after Clock t
0
40-TdCr(BUSACKf)-Clock t to BUSACK I D e l a y - - - - - - - - 310
41
TdCf(BUSACKr) Clock I to BUSACK t Delay
290
240
42
TdCr(Dz)
Clock t to Data Float Delay
TdCr(CTz)
Clock t to Control Outputs Float
43
290
DelaLi.MREQ, IORQ, RD,
and WR)
44
TdCr(Az)
Clock t to Address Float Delay
290
45-TdCTr(A)--MREQ t, IORQ t, RD t, a n d - - - - - - 400'
WR t to Address Hold TIme
46
TsRESET(Cr)
RESET to Clock t Setup TIme
240
47
RESET to Clock t Hold TIme
ThRESET(Cr)
0
48
TsINTf(Cr)
INT to Clock t Setup Time
210
49
ThINTr(Cr)
INT to Clock t Hold TIme
0
50-TdMlf(IORQf)-MI I tolORQ I D e l a y - - - - - - - - 2300'
51
TdCf(lORQf)
Clock I to IORQ I Delay
290
TdCf(lORQr)
52
Clock t to IORQ t Delay
260
TdCf(D)
Clock I to Data ValId Delay
53
290

0

Min
(ns)

Max
(ns)

120
110
90
110

110
160'-90
0
80
0
920'-110
100
230

*For clock perIOds other than the minimums shown 10 the table, calculate parameters

uSing the followmg expressions. Calculated values above assumed Tre

t All hmmgs assume equalloadmg on pms with 50 pF

= TiC = 20

ns.

Footnotes to AC Characteristics
Number Symbol

Z8300·3

Z8300·1

TeC

TwCh + TwCl + TrC + TIC

TwCh + TwCl + TrC + TIC

TdA(MREQf)

TwCh + TIC - 200

TwCh + TIC - 75

10

TwMREQh

TwCh + TIC - 90

TwCh + TIC - 30

11

TwMREQI

TeC - 110

TeC - 30

26

TdA(IORQf)

TeC - 210

TeC - 80

29-TdD(WRf)-----TeC - 5 4 0 - - - - - - - - - T e C - 2 1 0 - - - - - - - - - - 31

TwWR

TcC - 110

TeC - 40

33

TdD(WRf)

TwCl + TrC - 470

TwCl + TrC - 180

35

TdWRr(D)

TwCl + TrC - 210

TwCl + TrC - 80

45

TdCTr(A)

TwCl + TrC - 110

TwCl + TrC - 40

50

TdM If(lORQf)

2TeC + TwCh + TIC - 210

2TeC + TwCh + TIC - 80

AC Test Condlhons:
VIH = 2.0 V
VIL = 0.8 V
VIHC = VCC -0.6 V
VILC = O.4S V
VOH = 20V
VOL = 0.8 V
FLOAT = ±O.b V

268

Absolute
Maximum
Ratings

Standard
Test
Conditions

Voltages on all pins with respect
to ground ................... -0.3Vto +7V
Operating Ambient
Temperature ....... See Ordering Information
Storage Temperature ........ - 65°C to + 150°C
The DC characteristics and capacitance sections listed below apply for the following standard
test conditions, unless otherwise noted. All voltages are referenced to GND (OV). Positive current
flows into the referenced pin.
Available operating temperature is:

Stresses greater than those listed under Absolute Maximum Ratmgs may cause permanent damage to the device.
This is a stress ratmg only; operation of the device at any
condltion above those mdICated in the operational sections
of these specifications is not imphed. Exposure to absolute
maximum ratmg conditions for extended periods may affect

devlce reliability.

The Ordering Information section lists package
temperature ranges and product numbers. Package drawings are in the Package Information
section. Refer to the Literature List for addItional
documentation.
+5V

• S = O°C to + 70°C, + 4.75V :s; Vee :s;
+5.25V

~1K

All ac parameters assume a load capacitance
0'1 100 pI. Add IOns delay for each 50 pf increase
in load up to a maximum of 200 pf for the data
bus and 100 pf for address and control lines .

DC
Characteristics

Symbol
VILC
VlHe
VIL
VIH
VOL
VOH
ILl
110
Icc

Parameter

Min

Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Output Leakage
Power Supply Current

Frequency
28300-1 (1.0 MHz)
28300-3 (2.5 MHz)
1.

Capacitance

AIS-Ao,

Symbol
CC10CK
CIN
COUT

D7-DO,

MREQ, IORQ, RD,

Max

-0.3
0.45
Vcc-·6 VCC+ .3
-0.3
0.8
2.0
Vcc
0.4
2.4
10

±IO'

DOC
Max
30
45

Temperature
7DoC
25°C
25°C
Max Typical Max
25
40

15
25

Unit

Test Condition

V
V
V
V
V
V
p.A
p.A

IOL = 2.0mA
IoH = -250 p.A
VIN = 0 to Vcc
VOUT = 0.4 to Vce

Unit
rnA

20
35

rnA

Max

Unit

35
5

pF
pF
pF

and WR.

Parameter
Clock CapaCitance
Input CapaCitance
Output Capacitance

Min

15

Note

TA = 2S'C, f = I MHz.
Unmeasured pms returned to ground.

808S-0221

269

ORDERING INFORMATION
zaOl CPU, 1.0 MHz
40·pinDIP

zaOl CPU, 2.5 MHz
40·pinDIP

Z8300-1 PS

Z8300-3 PS

Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S '" O°C to + 70°C
E '" -40°Cto +85°C
M*= -55°Cto +125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DIP, O°C to + 70°C.

t Available soon.
* For Military Orders, contact your local Zilog Sales Office for Military Electrical Specifications.

270

00-2189-05

Z8320 Low Power
Z80L® PIO
Parallellnpat/Oatpat

Zilog

AC aDd DC Characteristics

March 1985

ABSOWTE MAXIMUM RATINGS
Voltages on all pins with respect
to ground ......................... - O.3V to + 7V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device This is a stress rating only;
operation of the device at any condition above these indicated In the
operational sections of these specifications is not implied Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

TEST CONDITIONS
The DC characteristics below apply for the following test
conditions, unless otherwise noted. All voltages are
referenced to GND (OV). Positive current flows into the
referenced pin.

+5V
2.1K

Available operating temperature range is:
• S = O°Cto +70°C, +4.75V~Vee~ +5.25V
The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the
Package Information section. Refer to the Literature List for
additional documentation.

DC CHARACTERISTICS
Symbol

Parameter

VILe

Clock Input Low Voltage

VIHe

Clock Input High Voltage

VIL

Min
-0.3

Max

1Ypical

+0.45

Unit

Condition

V

Vee- 0 .6

Vee + 0.3

V

Input Low Voltage

-0.3

+0.8

V

VIH

Input High Voltage

+2.0

V

VOL

Output Low Voltage

Vee
+0.4

VOH

Output High Voltage

+2.4

V

IOL = 2.0 mA

V

IOH = -250,..A

III

Input Leakage Current

±10

,..A

VIN = OtoVee

ILO

3-State Output Leakage Current in Float

±10

,..A

VOUT = 0.4 to Vee

ICC

Power Supply Current:

IOHD

Darlington Drive Current, Port B only

30
-1.5

20

mA
mA

VOH = 1 5V
REXT = 390Q

Over specified temperature and voltage range.

271

AC CHARACTERISTICS
----0---..(D+ ..(D+

CLOCK

r

-. ~'

~(\J\JJ\J'L

Ci
B/ArC/D

l

./

I--(i)-..!. -I !-@-

-0-1

X

)I

---®--I

~

OUT

Do-D7

-I®I...

+0-1

X

)(

IN

~

~

-®-

1~

I~
lEI

lEO

~I.J

- ®I--®---

READY

T

'F
1·;1 ®.=:(

®

-----'\

I~

MODEO

----x

MODE 1

~

-®-I

-®-

.

CARDY OR BRDYI

-®--1

X
-0--

MODE 2

----x

MODE 3

-®--I

I-:-----®-I

Number Symbol

2
3
4
5

Parameter

TcC

Clock Cycle Time

TwCh

Clock Width (High)

TwCI

Clock Width (Low)

TIC

Clock Fall Time

TrC

Clock Rise Time

NOTES:
[1] TcC ~ TwCh + TwCI + TrC + TIC.
[2] Increase TdRI(DO) by 10 ns lor each 50 pi increase in load up to 200
pfmax.
[3] Increase TdIO(DOI) by 10 ns for each 50 pi increase In loading upto
200 pfmax.
[4] For Mode 2: TwSTB > TsPD(STB).

272

Z8320-1
(1.0 MHz)
Min
Max

Z8330-3
(2.5 MHz)
Min
Max

1000
470
470

400
170
170

2000
2000
30
30

Notes'

[1]
2000
2000
30
30

[5] Increase these values by 2 ns lor each 10 pi Increase In loading up to
100 pfmax
[6] TsCS(RI) may be reduced However, the time subtracted lrom
TsCS(RI) will be added to TdRI(DO).
[7] 2.5 TcC > (N·2)TdIEI(IEOn + TdM1(IEO) + TsIEI(IO) ± TTL Buffer
Delay, if any
[8] M1 must be active for a minimum of two clock cycles to reset the PIO.
'Timings are preliminary and subject to change.

AC CHARACTERISTICS (Continued)
Z8320-1
(1.0 MHz)
Number Symbol

Parameter

6

TsCS(RI)

CEo B/A. C/O to RD. lORa j. Setup
Time

7

Th

Any Hold Times for Specified Setup
Time

8

TsRI(C)

RD. lORa to Clock t Setup Time

9

TdRI(DO)

RD. lORa j. to Data Out Delay

10

TdRI(DOs)

RD. lORa t to Data Out Float Delay

11

TsDI(C)

Data In to Clock t Setup Time

12

TdIO(DOI)

lORa j. to Data Out Delay
(INTACK Cycle)

13

TsM1(Cr)

M1 j. to Clock t Setup Time

14

TsM1(Cf)

M1 tlo Clockl- Setup Time (M1 Cycle)

15

TdM1(IEO)

M1 Ho lEO j. Delay (Interrupt
Immediately Preceding M1 j.)

16

TsIEI(lO)

lEI to lORa j. Setup Time (INTACK Cycle)

17

TdIEI(IEOf)

lEI Ho lEO Welay

Min

Max

140

Z8330-3
(2.5 MHz)
Min
Max

Notes·

50

0

0

300

115

[6]

1090

430

410

160

140

50

[2]

= 50p!

CL
340

860
540

210

0

0
760

[3]
[8]

300

[5.7]
[7]

140

360
480

190

[5]
CL

18

TdIEI(IEOr)

lEI t to lEO t Delay (after ED Decode)

19

TcIO(C)

lORa t to Clock j. Setup Time
(To Activate READY on Next Clock
Cycle)

20

TdC(RDYr)

Clock j. to READY t Delay

540

560

210

= 50p!
[5]

220
510

200

[5]
CL

= 50p!

21

TdC(RDYf)

Clock j. to READY j. Delay

22

TwSTB

STROBE Pulse Width

390

150

[4]

23

TsSTB(C)

STROBE t to Clock j. Setup Time
(To Activate READY on Next Clock
Cycle)

560

220

[5]

24

TdIO(PD)

lORa t to PORT DATA Stable Delay
(Mode 0)

25

TsPD(STB)

PORT DATA to STROBE t Setup Time
(Mode 1)

390

150

510
660

200

[5]

[5]

260

26

TdSTB(PD)

STROBE j. to PORT DATA Stable
(Mode 2)

590

230

27

TdSTB(PDr)

STROBE t to PORT DATA Float Delay
(Mode 2)

510

200

28

TdPD(IND

PORT DATA Match to INT j. Delay
(Mode 3)

1360

540

29

TdSTB(IND

STROBE tlo INT j. Delay

1240

490

NOTES:
[1] TcC = TwCh + TwCI + TrC + TIC
[2] Increase TdRI(DO) by 10 ns lor each 50 pi Increase In load upto 200
pi max.
[3] Increase TdIO(DOI) by 10 ns lor each 50 pi increase In loading upto
200 pi max.
[4] For Mode 2 TwSTB >TsPD(STB).

[5]

CL

= 50 p!

[5] Increase these values by 2 ns lor each 10 pi increase in loading up to
100 pi max.
[6] TsCS(RI) may be reduced. However, the time subtracted lrom
TsCS(RI) will be added to TdRI(DO).
[7] 2.5 TcC > (N-2)TdIEI(IEOf) + TdM1(IEO) + TsIEI(IO) ± TTL Buffer
Delay. II any.
[8] M1 must be active lor a minimum of two clock cycles to reset the PIO.
·Tlmlngs are preliminary and subject to change.

273
----------~----.

--~~-~--~~--

ORDERING INFORMATION
Z80L PIO, 1.0 MHz
40-pin DIP
Z8320-1 PS
Z80L PIO, 2.5 MHz
40-pinDIP
Z8320-3 PS

Codes
First letter is for package; second letter is for temperature.
C = Ceramic DIP
P = Plastic DIP
L = Ceramic LCC
V = Plastic PCC

TEMPERATURE
S = O°Cto + 70°C
E = -40°Cto +85°C
M*= -55°Cto + 125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Proto pack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DIP, O°C to + 70°C.

t Available soon.
* For Military Orders. contact your local Zilog Sales Office for Military Electrical Specifications.

274

00-2330-02

18330 Low Power
180L®CTC
CouDter/Timer Circuit

Zilog

AC aDd DC Characteristics

March 1985

ABSOWTE MAXIMUM RATINGS
Voltages on all pins with respect
to ground ......................... - O.3V to + 7V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. -65°Cto +150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above these indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating cond~lons for extended periods may affect
device reliability.

TEST CONDITIONS
The DC characteristics below apply for the following test
conditions, unless otherwise noted. All voltages are
referenced to GND (OV). Positive current flows into the
referenced pin.

+5V
2.1K

Available operating temperature range is:
• S = O°Cto +70°C, +4.75V";Vee"; +5.25V
The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the
Package Information section. Refer to the Literature List for
additional documentation.

DC CHARACTERISTICS
Symbol

VILe
VI He
VIL
VIH
VOL
VOH
III
ILO
ICC
IOHD

Typical

Unit

Min

Max

-0.3
Clock Input Low Voltage
Clock Input High Voltage
Vee- 0.6
Input Low Voltage
-0.3
Input High Voltage
+20
Output Low Voltage
Output High Voltage
+2.4
Input Leakage Current
3-State Output Leakage Current in Float
Power Supply Current:
-1.5
Darlington Drive Current

+0.45
Vee+ 0.3
+0.8
Vee
+0.4

V
V
V
V
V
V

±10
±10
30

,.Po
,.Po

Parameter

20

rnA
rnA

Condition

IOL = 2.0mA
IOH = -250,..A
VIN = OtoVee
VOUT = 0.4 to Vee
VOH = 1.5V
REXT = 390Q

Over specified temperature and voltage range.

275

AC CHARACTERISTICS
~I~

CLOCK

~O@.~ r-"\

~

)l

C80, 081

1-<9---

n

,. . . . w!\

X

~I

.t

\.

Ci

~

I--W--RUD

iOiiQ

\

~

J

CD-Fi

.t

\.

iii!

I-r~.
~
){..It--------------

--...L
'"

TaD

----!---'

Number

Symbol

Parameter

TwPh

Pulse Width (High)

500

Z8340-3t
(2.5 MHz)
Min
Max

Notes

200

2

TwPI

Pulse Width (Low)

3

TcTxC

TxC Cycle Time

1000

00

400

00

4

TwTxCI

TxC Width (Low)

460

00

180

00

5

TwTxCh

lis
A-A>s
A-Ass
A-s

INC (IY+d)

(IY+d)(IY+d)+1

DECm

m-m-1

Flags
H
PNN C

S Z

*

*

*
**
*

* *

Opcode
543 210 Hex

X
X

X V 0
X V 0

10 10001 r
11 10001 110
-n-

X
X

X V 0
X V 0

10 10001 110
11 011 101
10 10001 110
-d11 111 101
10 10001 110
-d10011
10101

X

*

X V 0

X
X V
X
X V
X
X V
X 1 X P
X 0 X P
X 0 X P
X
X V

*

0

0
0
0

X
X

X V 0
X V 0

•
•

00
11
00

X V 0

•

1

•

X V

3

5

7
19

FD

3

5

19

2

r

000
001
010
011
100
101
111

Reg.
B
C
D
E
H
L
A

sis any of r, n,
(HL), (IX+d),
(IY+d) as
shown for ADD
instruction. The
indicated bits
replace the
10001 inthe
ADD set above.

IIITl

*
00

*

DD

4
7

Will

•

X

2

ITQI]

X V 0

*

1
2

11001

X

X

No.of No. of M No. ofT
Bytes Cycles States Comments

[QITJ
0
0
0

*

* *

76

4

11001

110 11001
011 101 DD
110 11001
-d11 111 101 FD
00 110 11001
-d-

1
3

3
6

11
23

3

6

23

ITQI]

NarE: m IS any of r, (HL), (IX + d), (IY + d) as shown for INC. DEC same format and states as INC. Replace 1100 Iwith

D:QIJ in opcode.

GENERAL-PURPOSE ARITHMETIC AND CPU CONTROL GROUPS

Mnemonic

Symbolic
Operation

DM

@

CPL

A-A

NEG

A-O-A

Flags
H
PNN C

S Z
X

X P

•

• •

X

X

•

1

* *

X

X V

1

*

76

Opcode
543 210 Hex

No.of No. of M No. ofT
Bytes Cycles States Commenta

00

100 111

27

4

•

00

101

111

2F

4

*

11
01

101
000

101
100

ED
44

2

NarES @ converts accumulator content into packed BCD following add or subtract with packed BGD operands.
IFF indicates the interrupt enable flip-flop.
CY indicates the carry flip-flop.
indicates interrupts are not sampled at the end of EI or 01.

*

296

2

8

Decimal adjust
accumulator.
Complement
accumulator
(one's
complement).
Negateacc.
(two's
complement).

GENERAL-PURPOSE ARITHMETIC AND CPU CONTROL GROUPS (Continued)
Flags
H
PN N C

76

X

X

X

•

0

00

111

3F

4

X

0

X

•

0

00110111
00 000 000
01
110 110
11 110 011
11
111 011
11 101 101
01 000 110
11
101 101

37

ED
46
ED

01
11
01

56
ED
5E

Mnemonic

Symbolic
Operation

S Z

CCF

CY-CY

•

•

SCF
NOP
HALT

CY-1

•

•

No operation
CPU halted
IFF-O
IFF-1
Set interrupt
mode 0
Set interrupt
mode 1
Set interrupt
mode 2

• • X • X • • •
• • X • X • • •
• • X • X • • •

DI*

*

EI
IMO

1M 1
1M2

NOTES:

•
•

•
•

X
X

•
•

X
X

•
•

•
•

•
•

•

•

X

•

X

•

•

•

•

•

X

•

X

•

•

•

Opcode
543 210
111

010
101
011

110
101
110

Hex

No. of No. of M No. of T
Bytes Cycles States Comments

2

2

4
4
4
4
4
8

2

2

8

2

2

8

00

76
F3
FB

1

Complement
carry flag.
Set carry flag.

IQ

converts accumulator content into packed BCD following add or subtract with packed BCD operands.
IFF indicates the interrupt enable flip·flop.
CY indicates the carry flip·flop.
indicates interrupts are not sampled at the end of EI or DI.
@

c:::

*

16-BIT ARITHMETIC GROUP

Mnemonic

Symbolic
Operation

S Z

ADD HL, ss

HL-HL+ss

•

ADC HL, ss

HLHL+ss+CY

SBC HL, ss

ADD IX, pp

•

76
00

ssl

001

11
01

101
ss1

101
010

ED

11
01
11

101
ssO
011
pp1

101
010
101
001

ED

2

4

15

DD

2

4

15

•

X

X

X

•

0

~

X

X

X

V

0

HLHL-ss-CY
IX -IX + pp

Flags
H
P/V N C

•

X

X

X

V

X

X

X

•

~

0

01

ADD IY, rr

IY-IY+rr

•

•

X

X

X

•

0

INCss
INCIX

ss--ss+1
IX --IX+ 1

•
•

•
•

X
X

•
•

X
X

•
•

•
•

•
•

INCIY

IY-IY+1

•

•

X

•

X

•

•

•

DECss
DEC IX

ss-ss-1
IX -IX-1

•
•

•
•

X
X

•
•

X
X

•
•

•

•

DECIY

IY --IY-1

•

•

X

•

X

•

•

•

11
00
00
11
00
11
00
00
11
00
11
00

Opcode
543 210

111
rr1
ssO
011
100
111
100
ss1
011
101
111
101

101
001
011
101
011
101
011
011
101
011
101
011

Hex

No. of No. of M No. of T
Bytes Cycles States Comments

2

3

11

4

15

ss
00
01
10

Reg.
BC
DE
HL

11

SP

pp
01
10

Reg.
BC
DE
IX

11
rr
00
01
10
11

SP
Reg.
BC
DE
IY
SP

00

15

FD

2
1

1

6

DD
23
FD
23

2

2

10

2

2

10

DD
2B
FD
2B

2

2

10

2

2

10

4

6

297

ROTATE AND SHIFT GROUP
Symbolic
Mnemonic Operation

RLCA

RLA

RRCA

§]~
A

~
A

~
A

RRA

LCE§jI§l
A

·•
• ·
• ·
• ·
t

RLCr

Flags
H
P/v N C

S Z

t

X

0

X

·

0

•

0

t

Opcode

76

543 210

00

000

111

Hex

No. of No.ofM No.ofT
Bytes Cycles States Comments

4

07

Rotate left
circular
accumulator.

X

0

X

t

00

010

111

4

17

Rotate left
accumulator.

X

0

X

·

0

•

0

t

00

001

111

4

OF

Rotate right
circular
accumulator.

X

0

X

t

00

011

111

4

1F

Rotate right
accumulator.

X

0

X

p

0

t

11

001

011

CB

2

2

8

Rotate left
circular

00 10001

register r.

t

RLC(HL)

RLC(IX+d)

§]~:J
t t

X

0

X

P 0

t

11

001

011

CB

2

4

15

00 10001 110
X

0

X

P 0

t

r,(HL),(lX + d),(lY + d)

11
11

101

DO

001 011
+-d-+

CB

011

4

6

23

00 10001 110

t t

RLC(IY+d)

RLm

l@~ t t

X

0

X

P 0

t

11

111

~§]

6

Reg.
B

001

C

010
011

0
E

001

H

101
111

A

L

23

101

FD

11

001 011
+-d-+

CB

00

10001 110

format and
states are as
shown for

X

0

X

P 0

t

1010 I

X

0

X

P 0

t

10011

m = r,(HL,(IX + d),(lY + d)
RRCm

4

r
000

Instruction

RLCs. To form

t t

newopcode
replace I000 I

m = r,(HL),(lX + d),(IY + d)

or RLCswith
RRm

LED=§J t t

shown code.
X

0

X

P 0

t

[QTI]

X

0

X

p

0

t

11001

X

0

X

P 0

t

ITQI]

X

0

X

p

t

OJ]

m = r,(HL),(IX + d),(lY + d)
SLAm

[§!]~_o

t t

m = r,(HL),(IX+ d),(IY + d)
SRAm

~

t t

o+~

t t

m = r,(HL),(IX + d),(IY + d)

SRLm

m = r,(HL),(IX + d),(lY + d)

298

0

ROTATE AND SHIFT GROUP (Continued)
Symbolic
Mnemonic Operation

S

Flags
H
PNN

Z

RLO

X

0

X

P

0

C

•

(HL)

76

Opcode
543 210

Hex

11

101

101

ED

01

101

111

6F

No. of No. of M No. of T
Bytes Cycles States
2

5

18

Comments
Rotate digit
lefland
right between
theaccumulator and

RRO~
A

(HL)

* *

X

0

X

P

0

·

location (HL).
11

101

101

ED

01

100

111

67

2

5

18

The content
of the upper
half of the
accumulator
is unaffected.

BIT SET, RESET AND TEST GROUP

III
g

•n
c:I

Mnemonic

Symbolic
Operation

S

BIT b, r

Z +- rb

X

BITb, (HL)

Z +-(HL)b

BIT b,(IX + d)b Z +- (IX + d)b

Flags
H
PNN

Z
X

X

X

0

C

•

X

X

X

X

0

•

X

X

X

X

0

•

Opcode
76 543 210

Hex

011

CB

11

001

01

b

11

001

011

01

b

110

11

011

11

BIT b, (IY + d)b Z +- (IY + d)b

SET b, r
SETb, (HL)

rb +-1
(HL)b +-1

SET b, (IX + d) (IX + d)b +- 1

SET b, (lY + d) (IY + d)b +- 1

RESb,m

mb+- O
m=r.(HL),

X

•

*

X

• •

•

1

· ·

• •

•

X

·

X
X

X

•
•

•

· ·
X

X

X
X
X

X

X

(IX + d), (IY + d)

X

0

·

• • •

·
·• ·
• •

•

•

12

101

DO

4

5

20

001 011
+-d-+

CB

11

111

101

FO

001 011
+-d-+

CB

01

b

110
011

11

001

OJ]

b

CB

11

001

011

OJ]

b

110

011

101

DO

001 011
+-d-+

CB

CB

OJ]

b

110

11

111

101

FD

001 011
+-d-+

CB

·

•

·

• ITQ]

11

[j]

b

4

2
2

5

2

4

Reg.

8

3

110

11

2

2

b

11

2

CB

01

11

No. of No. of M No. ofT
Bytes Cycles States Comments

20

8
15

4

6

23

4

6

23

000

B

001

C

010

D

011

E

100

H

101

L

111

A

b

Bit Tested

000

0

001
010

2

011

3

100

4

101

5

110

6

111

7

110
To form new
opcode replace

[IT] of SET b, S
with [1QJ Flags
and time
states for SET
instruction.

NOfE: The notation mb Indicates location m, bit b (0 to 7).

299

JUMP GROUP
Symbolic
Mnemonic Operation
JP nn

PC-nn

JP cc, nn

If condition cc
is true PC-nn,

Flags

H

S Z

Opcode
PIVN C

·· · ·• •
·• • • • •

76

X

X

11

X

X

11

JRe

PC-PC+e

JRC,e

IfC=O,
continue

000 011
-n ....

C3

3

10

3

3

10

·· · ·
·· · ·• ·
X

•

X

X

•

X

00
00

• •

X

•

X

continue

·• •

00

Comments
Condition
cc
000 NZ (non-zero)
001

cc 010
-n ....

011 000
-e-2 ....
111

000
-e-2 ....

110 000
-e-2 ....

Z(zero)

010

NC (non-carry)

011

C(carry)

100

PO (parity odd)

101

PE (parity even)

110

P (sign positive)

111

M (sign negative)

18

2

3

12

38

2

2

7

If condition not met.

2

3

12

If condition is met.

2

2

7

If condition not met.

2

3

12

If condition is met.

2

2

7

If condition not met.

2

3

12

If condition is met.

2

2

7

If condition not met.

2

3

12

If condition is met.

IfC=1,
IFC=1,

3

-n ....

PC-PC+e
JR NC, e

No. of No. of M No. of T
Bytes Cycles States

-n ....

otherwise
continue

543 210 Hex

30

IfC=O,
PC-PC+e
JPZ, e

IfZ=O

• •

X

•

X

• • •

00

continue

101 000
-e-2 ....

28

IfZ=1,
PC-PC+e
JR NZ,e

IfZ=1,
continue

•

·

X

•

X

·• ·

00 100 000
-e-2 ....

20

IfZ=O,
JP(HL)

PC-PC+e
PC-HL

JP(IX)

PC-IX

JP(IY)
DJNZ, e

PC-IY
8-8-1
If8=0,

• •
• •

•
•

• • •

11

101

001

E9

1

4

11

011

101

DD

2

2

8

11

101

001

• • •

11

111

101

E9
FD

2

2

8

·• · • ·•

11

101

001

E9

010 000
-e-2 ....

10

2

2

8

If8=0

2

3

13

If 8*0.

• •

X
X
X
X

•

X
X
X
X

• • •

00

continue
If 8*0,
PC-PC+e

NOTES: e represents the extension in the relative addressing mode.
e is a signal two's complement number in the range < -126, 129 >.
e - 2 in the opcode provides an effective address of pc + e as PC is incremented by 2 prior to the addition of e.

300

CALL AND RETURN GROUP
Symbolic
Mnemonic Operation
CALLnn

(SP -1 )....PCH •
(SP-2)-PCl
PC-nn,

CALL cc, nn If condition
ccisfalse
continue,
otherwise

RET
RETcc

RETI
RETN1

RSTp

Flags

S Z

same as
CALLnn
PCl -(SP)
PCH-(SP+1)
If condition
cc is false
continue,
otherwise
same as RET

Return from
interrupt
Return from
non-maskable
interrupt
(SP-1)-PCH
(SP-2)-PCl

H

• X • X

PNN C

···

• • X• X• • •

76

Opcode
543 210 Hex

11

001 101
-n-n-

11

cc 100
-n.... n-

• • X• X• • •

11

001

001

·

11

cc

000

• X • X

·

CD

No. of No.ofM No.ofT

Bytes

Cycles

States

3

5

17

3

3

10

If cc is false.

3

5

17

If cc is true.

3

10

C9

3

• •

X • X • • •

• •

X • X • • •

• • X• X• • •

PCH-O
PCl -p

11
01
11
01
11

101
001
101
000

101
101
101
101
111

ED
4D
ED
45

Commenta

I

5

If cc is false.

11

If cc is true.
Condition
cc
000 NZ (non-zero)
001 Z(zero)
010 NC (non-carry)
011 C(carry)
100 PO (parity odd)
101 PE (parity even)
110 P (sign positive)
111 M (sign negative)

2

4

14

2

4

14

3

11

t
000
001
010
011
100
101
110
111

P
OOH
08H
10H
18H
20H
28H
30H
38H

NOTE: 1RETNloadsIFF2-IFF1

301

:I"

INPUT AND OUTPUT GROUP
Symbolic
Mnemonic Operation
INA,(n)
IN r, (C)

A .... (n)

Flags

S Z

·

• X • X
X

r .... (e)

Opcode
PNN C

H

X

·• ·
p 0

•

il r = 11 0 only
the Ilags will
be affected
INI

INIR

(HL) .... (C)
B .... B-1
HL .... HL+1
(HL) .... (C)
B .... B-1
HL .... HL+1
Repeat until

X
X

CD
*
®
1

XXXX
XXXX

1

1

X
X

76
11

No. of

543 210 Hex
011
01
.... n ....

11
01

101

11
10

101
100

11
10

101
110

DB

Bytes
2

No. of M No. of T
Cycles States Comments
3

11

ntoAo"'A7

kc. to As '" A15
ED

2

3

12

etoAo"'A7
BtoAs"'A15

101
010

ED

2

4

16

etoAo"'A7
BtoAs"'A15

101
010

ED

5

21

etoAo '" A7
BtoAs"'A15

101
000

A2
2

B2

(IIB*O)
2

4

16

(IIB=O)

B=O
INO

INOR

(HL) .... (C)
B .... B-1
HL .... HL-1
(HL) .... (C)
B .... B-1
HL .... HL-1

Repeat until
B=O
aUT(n),A (n) .... A
aUT(C), r (C) .... r

aUTI

OTIR

(C) .... (HL)
B .... B-1
HL+-HL+1
(C) +- (HL)
B+-B-1

.
16-bit value in range < 0, 65535 >.

*H and N flags are used in conjunction with the decimal adjust instruction (DAA) to properly correct the result into packed BCD format following addition or
subtraction using operands with packed BCD format.

303

g
n

III

d

PIN DESCRIPTIONS
Ao-A1S. Address Bus (output, active High, 3-state). Ao-A15
form a 16-bit address bus. The Address Bus provides the
address for memory data bus exchanges (up to 64K bytes)
and for I/O device exchanges.

M1. Machine Cycle One (output, active Low). MT, together
with MREQ, indicates that the current machine cycle is the
opcode fetch cycle of an instruction execution. M 1, together
with 10RO, indicates an interrupt acknowledge cycle.

BUSACK. Bus Acknowledge (output, active Low). Bus
Acknowledge indicates to the requesting device that the
CPU address bus, data bus, and control signals MREO,
10RO, RD, and WR have entered their high-impedance
states. The external circuitry can now control these lines.

MREQ. Memory Request (output, active Low, 3-state).
MREO indicates that the address bus holds a valid address
for a memory read or memory write operation.

BUSREQ. Bus Request ~t, active Low). Bus Request
has a higher priority than NMI and is always recognized at
the end of the current machine cycle. BUSREO forces the
CPU address bus, data bus, and control signals MREO,
10RO, RD, and WR to go to a high-impedance state so that
other devices can control these lines. BUSREO is normally
wired-OR and requires an external pullup for these
applications. Extended BUSREO periods due to extensive
DMA operations can prevent the CPU from properly
refreshing dynamic RAMs.

00-07. Data Bus (input/output, active High, 3-state). 00-07
constitute an a-bit bidirectional data bus, used for data
exchanges with memory and 1/0.

HALT. Halt State (output, active Low). HALT indicates that
the CPU has executed a Halt instruction and is awaitin!il
either a nonmaskable or a maskable interrupt (with the mask
enabled) before operation can resume. While halted, the
CPU executes NOPs to maintain memory refresh.
INT. Interrupt Request (input, active Low). Interrupt Request
is generated by 1/0 devices. The CPU honors a request at
the end· of the current instruction if the internal
software-controlled interrupt enable flip-flop (IFF) is
enabled. INT is normally wired-OR and requires an external
pullup for these applications.

IORQ. Input/Output Request (output, active Low, 3-state).
10RO indicates that the lower half of the address bus holds a
valid I/O address for an 1/0 read or write operation. 10RO is
also generated concurrently with M1 during an interrupt
acknowledge cycle to indicate that an interrupt response
vector can be placed on the data bus.

304

NMI. Non-Maskable Interrupt (input,~~e edgetriggered). NMI has a higher priority than INT. NMI is always
recognized at the end of the current instruction,
independent of the status of the interrupt enable flip-flop,
and automatically forces the CPU to restart at location
0066H.
RD. Read (output, active Low, 3-state). RD indicates that the
CPU wants to read data from memory or an 1/0 device. The
addressed 1/0 device or memory should use this signal to
gate data onto the CPU data bus.
RESET. Reset (input, active Low). RESET initializes the CPU
as follows: it resets the interrupt enable flip-flop, clears the
PC and Registers I and R, and sets the interrupt status to
Mode O. During reset time, the address and data bus go to a
high-impedance state, and all control output signals go to
the inactive state. Note that RESET must be active for a
minimum of three full clock cycles before the reset operation
is complete.
RFSH. Refresh (output, active Low). RFSH, together with
MREO, indicates that the lower seven bits of the system's
address bus can be used as a refresh address to the
system's dynamic memories.

WAIT. Wait (input, active Low). WAIT indicates to the CPU
that the addressed memory or I/O devices are not ready for
a data transfer. The CPU continues to enter a Wait state as
long as this signal is active. Extended WAIT periods can
prevent the CPU from refreshing dynamic memory properly.
WR. Write (output, active Low, 3-state). WR indicates that the
CPU data bus holds valid data to be stored at the addressed
memory or 1/0 location.

CPU TIMING

zaoc

The
CPU executes instructions by proceeding
through a specific sequence of operations:
•

Memory read or write

• 1/0 device read or write
•

Interrupt acknowledge

The basic clock period is referred to as a T time or cycle, and
three or more T cycles make up a machine cycle (M 1, M2 or
M3 for instance). Machine cycles can be extended either by
the CPU automatically inserting one or more Wait states or
by the insertion of one or more Wait states by the user.

Instruction Opcode Fetch. The CPU places the contents
of the Program Counter (PC) on the address bus at the start
of the cycle (Figure 5). Approximately one-half clock cycle
later, MREQ goes active. When active, RD indicates that the
memory data can be enabled onto the CPU data bus.
The CPU samples the WAIT input with the falling edge of
clock state T2. During clock states T3 and T4 of an M1 cycle,
dynamic RAM refresh can occur while the CPU starts
decoding and executing the instruction. When the Refresh
Control signal becomes active, refreshing of dynamic
memory can take place.

CLOCK

-=!_J-®

Do-D7

=:=)~--(H(B((=::~==~~c=====t==
I-~

-I--@
I-=J
'---------'

--~/"f--(- - - - - . .{ =
RFSH

• Tw

= Wait cycle added when necessary for slow ancllhary devices,

Figure 5. Instruction Opcode Fetch

2001-006

305

Memory Read or Write Cycles. Figure 6 shows the timing
of memory read or write cycles other than an opcode fetch
(M1) cycle. The MREQ and RD signals function exactly as in
the fetch cycle. In a memory write cycle, MREQ also

becomes active when the address bus is stable. The WR line
is active when the data bus IS stable, so that it can be used
directly as an R/W pulse to most semiconductor memories.

®-

ifIj

OPERA~~~~

{

00- 0 7

~1~
__

29 _ _ _ _

(

?~____________~
~

DATA OUT

Figure 6. Memory Read or Write Cycles

306

2001·007

extra Wait state allows sufficient time for an 1/0 port to
decode the address from the port address lines.

Input or Output Cycles. Figure 7 shows the timing for an

I/O read or I/O write operation. During 1/0 operations, the
CPU automatically inserts a single Wait state (TWA). This

T,

TWA

T3

CLOCK

Ao-A7

WAIT

--r-'~---+----------~~)~~+------H-+-+~~

--+----r--~------------~~~{~-'

AD

OPERA~~~

{
00-07

1'11-------------.....,(1--------------/ .. ®.-

WR

WRI~~ {
OPERATION

TWA

~~®_

00-07

~

-----------1-::::::::::::::::::~::::::~~~~::::::)
~
DATA OUT

= One walt cycle automatically Inserted by CPU
Figure 7. Input or Output Cycles

2001-008

307

Interrupt Request/Acknowledge Cycle. The CPU
samples the interrupt signal with the rising edge of the last
clock cycle at the end of any instruction (Figure 8). When an
interrupt is accepted, a special M1 cycle is generated.

During this M1 cycle, IORO becomes active (instead of
MREO) to indicate that the interrupting device can place an
8-bit vector on the data bus. The CPU automatically adds
two Wait states to this cycle.

AO-AI5 ____________~--J~__-------------p-c--_r------_+~r;-----~--_H--J~----

1~4~------~@Dr------~.~1
WAIT

----------~--------------------~~~~~

--- }+®_42---mc~~~

~

DO-D7

NOTES: 1) T1.1

(H(

~

= Last state of any Instruction cycle.
= Walt cycle automatically Inserted by CPU.

2) TWA

Figure 8. Interrupt Request/Acknowledge Cycle

308

2001·009

Non-Maskable Interrupt Request Cycle. NMI is sampled
at the same time as the maskable interrupt input INT but has
higher priority and cannot be disabled under software
control. The subsequent timing is similar to that of a normal

- - - - - L A S T M CYCLE

-----Io
••

memory read operation except that data put on the bus by
the memory is ignored. The CPU instead executes a restart
(RST) operation and jumps to the NMI service routine
located at address 0066H (Figure 9).

I...--------------M1-------------l~1
T3

T"

T.

T,

AO-A1S

-®-

• Although NMi Is an asynchronous Input, to guarantee Its being recognized on the following machine cycle, NMI'e tailing edge must occur no later than the rising edge

of the clock cycle preceding the last state of any Instruction cycle (Tll).

Figure 9. Non-Maskable Interrupt Request Operation

2001·010

309

Bus Request/Acknowledge Cycle. The CPU samples
BUSREQ with the rising edge of the last clock period of any
machine cycle (Figure 10). If BUSREQ is active, the CPU
sets its address, data, and MREQ, 10RQ, RD, and WR lines

to a high-impedance state with the rising edge of the next
clock pulse. At that time, any external device can take
control of these lines, usually to transfer data between
memory and I/O devices.

CLOCK

BUSACK

Ao-A15

Do-D.

MREQ
Ri),WR

-

-®

-

--@

-

--@

-+

--®

FLOAT

-+
FLOAT

--...
FLOAT

IORQ

-@~

UNCHANGED

NOTES' 1) TLM = Last state of any M cycle.
2) Tx = An arbitrary clock cycle used by requesting device.

Figure 10. Z·BUS Request/Acknowledge Cycle

310

2001-011

Halt Acknowledge Cycle. When the CPU receives a HALT
instruction, it executes NOP states until either an INT or NMI
input is received. When in the Halt state, the HALT output is

active and remains so until an interrupt is received (Figure
11). INT will also force a Halt exit.

M1----.I ....- - - - - - - - - M 1 - - - - - - - -.... I.....> - - - - - - - M1
~

~

~

~

~

~

~

CLOCK

_ _ _ _ I-j®·
~----------------------------

NMI

• Although NMlls an asynchronous input, to guarantee its being recognized on the following machine cycle, MNI's falling edge must occur no
later than the riSing edge of the clock cycle preceding the last stale of any instruction cycle (Tu).

Figure 11 . Halt Acknowledge

Reset Cycle. RESET must be active for at least three clock
cycles for the CPU to properly accept it. As long as RESET
remains active, the address and data buses float, and the
control outputs are inactive. Once RESET goes inactive, two

internal T cycles are consumed before the CPU resumes
normal processing operation. RESET clears the PC register,
so the first opcode fetch will be to location OOOOH
(Figure 12).
I__- - - M l - - - - - -

CLOCK

-0-

-@-

AO-A15 ______________________________~~--~r~--------------------------t-1l----------------

- - - -____
®J~

FLOAT

~~------------------------~--------------------

00-07

/

--------------------------------~

.!!R~

__-

R~~------------~/~7~7~ZrzrZT7~-----ij)~------------------~\~~-_-_~-_-_-_~-_-_BUSACK
HALT

-

Figure 12. Reset Cycle

2001 -012.013

311

Power-Down Release Cycle. The system clock must be
supplied to the Z80C CPU to release the power-down state.
When the system clock is supplied to the ClK input, the
Z80C CPU restarts operations from the point at which the
power-down state was implemented.
The timing diagrams for the release from power-down mode
are shown in Figure 13.
T,

CLK

T,

T,

NOTES:
1) When the external oscillator has been stopped to enter the power-down
state, some warm-up time may be required to obtain a stable clock for
the release.
2) When the HALT instruction is executed to enter the power-down state,
the zaoc CPU will also enter the Halt state. An interrupt signal (either
NMI or INT) or a RESET signal must be applied to the zaoc CPU after
the system clock is supplied in order to release the power-down state.

T,

T,

,
r

,
NMI

iii

'\J

r'
'J

HALT
If"
...

\

I

\

I
Figure 138.

T,

CLK

T,

T,

»)
"
)

RESET

'~ ,

I

;

('
»)

'Jr'

('
»)

/f

MI

HALT

T,

\

I

I
Figure 13b.

T,

T,

T,

T,

T,

CLK

j)
)

INT

)(

'~ ,

I

;

iii

»)( '

/\

"
J;

"
7)

I

I

HALT

Figure 13c.
Figure 13. Power-Down Release

312

\

T,

TWA

TWA

"For clock periods other than the minimums shown, calculate parameters using the table on the following page. Calculated values above
assumed TrC = TIC = 20 ns.
tUnrts in nanoseconds (ns).
2360-002

313

AC CHARACTERISTICSt (Continued)
Z84COO

Number Symbol

Min

Parameter

30

TdCf(WRf)

Clock ~ to WR ~ Delay

31

TwWR

WR Pulse Width

32

TdCf(WRr)

Clock ~ to WR t Delay

33

TdD(WRf)

Data Stable prior to WR ~

-

35

TdWRr(D)

Data Stable from WR t

36

TdCf(HAL1)

Clock ~ to HAiJ t or ~

Max
80

90
220'

360'

80

100
-10'

20'

65-

80

34- TdCr(WRf)--Clock t to WR ~ Delay

-

Z84COO·4

Min

Max

60'

120'

300

300

37

TwNMI

NMI Pulse Width

80

80

38

TsBUSREQ(Cr)

BUSREQ Setup Time to Clock t

80

50

39

ThBUSREQ(Cr)

"EiOSREQ Hold Time after Clock t

20

10

40- TdCr(BUSACKf)

Clock t to BUSACK ~ Delay

120

100-

41

TdCf(BUSACKr)

Clock ~ to BUSACK t Delay

110

100

42

TdCr(Dz)

Clock t to Data Float Delay

90

90

43

TdCr(CTz)

Clock t to Control Outputs Float Delay
(MREQ, IORQ, RD, and WR)

110

80

44

TdCr(Az)

Clock t to Address Float Delay

110

90
80'

--45-TdCTr(A)---MREQt, IORQt, ROt, andWRtto ---160'
Address Hold Time

60

46

TsRESET(Cr)

RESET to Clock t Setup Time

90

47

ThRESET(Cr)

RESET to Clock t Hold Time

10

10

48

TsINTf(Cr)

INT ~ to Clock t Setup Time

80

80

49

ThINTr(Cr)

iN'i't to Clock t Hold Time

-50-TdMlf(IORQf)-Ml ho IORQ Welay

10

10

920'

565'

51

TdCf(IORQf)

Clock ~ to lORa ~ Delay

52

TdCf(IORQr)

Clock t to iC5iID t Delay

100

85

53

TdCf(D)

Clock ~ to Data Valid Delay

230

150

85

110

'For clock periods other than the minimums shown, calculate parameters using the follOWing table. Calculated values above
assumed TrC = TIC = 20 ns.
tUnils In nanoseconds (ns).

FOOTNOTES TO AC CHARACTERISTICS
Number

Symbol

General Parameter

TcC

TwCh + TwCl + TrC + TfC

TdA(MREQf)

10

TwMREQh

11
26

7

Z84COO

Z84COO-4

TwCh + TfC

- 75

- 65

TwCh + TfC

- 30

- 20

TwMREQI

TcC

- 40

- 30

TdA(IORQf)

TcC

- 80

- 70

TcC

210
- 40

- 30

---29--TdD(WRf)
TwWR

TcC

33

TdD(WRf)

TwCI + TrC

- 180

- 140

35

TdWRr(D)

TwCI + TrC

- 80

- 70

45

TdCTr(A)

TwCI + TrC

- 40

- 50

50

TdM1f(IORQf)

2TcC + TwCh + TfC

- 80

- 65

P>C Test Conditions:

VIH = 2.0V
VIL = O.SV

314

170--

31

VOH = 1.SV
VOL = 1.SV

VIHC = VCC - 0.6 V
VILC = O.4SV

FLOAT = ±O.SV

ABSOWTE MAXIMUM RATINGS
Voltage on Vee with respect to vss ........ - 0.3V to + 7V
Voltages on all inputs with respect
to Vss ...................... - 0.3V to Vee + 0.3V
Operating Ambient
Temperature .............. See Ordering Information
Storage Temperature .............. -65°Cto +150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of ttie device at any condition above those indicated in the
operational sections of these specifications is nQt implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

STANDARD TEST CONDITIONS
The DC Characteristics and capacitance sections below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND (OV).
Positive current flows into the referenced pin.

The Ordering Information section lists temperature ranges
and product numbers. Package drawings are in the
Package Information section in this book. Refer to the
Literature List for additional documentation.

Available operating temperature ranges are:
+5V

• S = OOCto +70°C
• E = -40°Cto +85°C

2.1K

Voltage Supply Range: + 4.50V .;;; Vee';;; + 5.50V
All ac parameters assume a load capacitance of 100 pI. Add
10 ns delay for each 50 pf increase in load up to a maximum
of 200 pf for the data bus and 100 pf for address and control
lines. AC timing measurements are referenced to 1.5 volts
(except for clock, which is referenced to the 10% and 90%
points).

DC CHARACTERISTICS
Symbol

Parameter

Min

VILe

Clock Input low Voltage

VIHe

Clock Input High Voltage

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output low Voltage

VOH1

Output High Voltage

2.4

VOH2

Output High Voltage

Vee- 0.8

lee1

Power Supply Current

-0.3

Max

Unit

0.45

V

Vee-·6

Vee+· 3

V

-0.3

0.8

V

2.2

Vee
0.4

V
V
V
V

25

Condition

mA

= 2.0mA
= -1.6mA
IOH = - 250 I'A
Vee = 5V
ClK = 4 MHz
IOL

IOH

VIH = Vee - 0.2V
VIL = 0.2V
Standby Supply Current

10

Vee = 5V
ClK = (0)
VIH

= Vee

- 0.2V

VIL = 0.2V
Input leakage Current
3-State Output leakage Current in Float

-10

10

VIN = 0.4 to Vee

102

VOUT

= 0.4 to Vee

1. Measurements made with outputs floating.
2. A15·Ao, DrDo, MREO, IORO, RD, and WR.
3. ICC2 standby supply current is guaranteed only when the supplied clock is stopped at a low level during T4 of the machine cycle immediately following
the execution of a HALT instruction.

315

CAPACITANCE
Symbol

Parameter

CCLOCK

Clock Capacitance

35

pI

CIN

Input Capacitance

5

pI

COUT

Output Capacitance

15

pI

Min

Max

Unit

TA = 25°C, f = 1 MHz.
Unmeasured pins returned to ground.

ORDERING INFORMATION
Z80C CPU, 2.5 MHz
40-plnDIP
Z84COO PS
Z84COOCS
Z84COO PE
Z84COOCE

Z80C CPU, 4.0 MHz
40-pln DIP
Z84COO-4PS
Z84COO-4CS
Z84COO-4 PE
Z84COO-4CE

Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = O°Cto +70°C
E = -40°C to +85°C
M*= -55°Cto +125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
8 = 883 Class 8

Example: PS is a plabtic DIP, O°C to + 70°C.

t Available soon.
* For Military Orders, contact your local Zilog Sales Office for Military Electrical Specifioations.

316

00-2360-01

Z84C20CMOS
Z80®CPIO
Parallellnpat/Oalpat
Advance Information
AC and DC Characteristics

Zilog

April 1985

ABSOLUTE MAXIMUM RATINGS
Voltages on Vee with respect to Vss ..... - O.3V to + 7.0V
Voltages on all inputs with respect
to Vss ....................... - O.3V to Vee + O.3V
Storage Temperature .............. - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above these indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

STANDARD TEST CONDITIONS
The characteristics below apply for the following test
conditions, unless otherwise noted. All voltages are
referenced to GND (OV). Positive current flows into the
referenced pin. Available operating temperature range is:

+5V
2.1K

• S = O°Cto +70 oC, +4.50V";Vee"; +5.50V

• E = -40°C to +85°C, +4.50V"; Vee"; 5.50V
The Ordering Information section lists package temperature
ranges and product numbers. Refer to the Literature List for
additional documentation. Package drawings are in the
Package Information section.

DC CHARACTERISTICS
Symbol

Parameter

VILe

Clock Input

VIHe

Clock Input High Voltage

VIL

Input Low Voltage

-0.3

VIH

Input High Voltage

+2.2

VOL

Output

VOH1

Output High Voltage

+2.4

VOH2

Output High Voltage

Vee- O.S

III

Input Leakage Current

±10

,..A

ILO

3·State Output Leakage Current in Float

±10

,..A

Min

Low Voltage

-0.3
Vee- 0 .6

Low Voltage

Max
+0.45
Vee+ 0 .3
+O.S
Vee
+0.4

l)'p

Unit

'1l!st Condition

V
V
V
V
V
V
V

= 2.0mA
= -1.6mA
IOH = -250,..A
VIN = 0.4 to Vee
VOUT = 0.4 to Vee
IOL

IOH

Over specified temperature and voltage range.

317

DC CHARACTERISTICS (Continued)
Symbol

Parameter

ICC1

Power Supply Current

Min

Max

Typ

Unit

Test Condition

5

2

mA

Vee = 5V
ClK = 4MHz

= Vee - 0.2V
= 0.2V
Vee = 5V
ClK = (0)
VIH = Vee - 0.2V
VIL = 0.2V
VOH = 1.5V
REXT = 1.1K Q
VIH
VIL

ICC2

Standby Supply Current

IOHD

Darlington Drive Current. Port B only

10

-1.5

-5.0

0.5

IJ.A

mA

Over specified temperature and voltage range.

AC CHARACTERISTICS

CLOCK

Ci

8Ii, eli)

iiii.IORQ

DO- D7

l ---+----...r----+---~Lr-I+---+--OUT

IN

lEI

lEO

R.ADY
(ARDY OR BRDY)

iiiiiiiiE
iifi)

(ASTB OR

MODE 0

MODE 1

MODE 2

MODE 3

318

---------+-T~~~~----------,f_~~H_------+_--------

---------+~~,~---4------------~~H_------+_--------

AC CHARACTERISTICS (Continued)

Number Symbol

Parameter

Z84C20
Mln(ns) Max(ns)

Z84C20-4
Mln(ns) Max(ns)

TcC

Clock Cycle Time

400

[1]

250

[1]

2

TwCh

Clock Pulse Width (High)

170

DC

105

DC

3

TwCI

Clock Pulse Width (Low)

170

DC

105

DC

4

TIC

Clock Fall Time

30

30

5

TrC

Clock Rise Time

30

30

6

TsCS(RI)

CE, BfA, CfO to RD, lORa ~
Setup Time

7

Th

Any Hold Times for Specified
Setup Time

8

TsRI(C)

RD, lORa to Clock t Setup Time

50

[6]

50

0

40

115

115

9

TdRI(DO)

RD, lORa ~ to Data Out Delay

430

380

10

TdRI(DOs)

RD, lORa t to Data Out Float Delay

160

110

11

TsDI(C)

Data In to Clock t Setup Time

12

TdIO(DOI)

IORO+ to Data Out Delay
(INTACK Cycle)

13

TsM1(Cr)

Mi ~ to Clock t Setup Time

14

TsM1(Cf)

M1 tlo ClocU Setup Time (M1 Cycle)

15

TdM1(IEO)

M1 Ho lEO ~ Delay (Interrupt
Immediately Preceding M1 +)

16

TsIEI(IO)

lEI to lORa ~ Setup Time
(lNTACK Cycle)

17

TdIEI(IEOf)

lEI Ho lEO +Delay

Comment

50

50
340
90

0

0

CL

[8]
[5,7]

140

[7]
[5]

130

190

CL
18

TdIEI(IEOr)

lEI t to lEO t Delay (after ED Decode)

19

TcIO(C)

lORa t to Clock ~ Setup Time
(To Activate READY
on Next Clock Cycle)

20

TdC(RDYr)

Clock ~ to READY t Delay

160

210

= 50 pf
[5]

200

220
200

190

[5)
CL

140

= 50pf

21

TdC(RDYf)

Clock. to READY. Delay

22

TwSTB

STROBE Pulse Width

150

150

[4]

23

TsSTB(C)

STROBE t to Cloci< ~ Setup Time
(To Activate READY
on Next Clock Cycle)

220

220

[5)

24

TdIO(PD)

lORa t to PORT DATA Stable Delay
(Mode 0)

25

TsPD(STB)

PORT DATA to STROBE t Setup Time
(Mode 1)

NOTES:
[1] TcC = TwCh + TwCl + TrC + TIC.
[2] Increase TdRI(DO) by 10 ns lor each 50 pI increase in load up to 200
pI max.
[3] Increase TdIO(DOI) by 10 ns lor each 50 pI, increase in loading upto
200 pI max
[4] For Mode 2: TwSTB > TsPD(STB).
[5] Increase these values by 2 ns lor each 10 pI increase in loading upto
100 pI max.

150

200
260

S

= 50pf
[3]

190

300

140

[2]

160

210

I:
g

180

[5]

[5)

230

[6] TsCS(RI) may be reduced. However, the time subtracted Irom TsCS(RI)
will be added to TdRI(DO).
[7]2.5 TcC> (N-2)TdIEI(IEOf) + TdM1(IEO) + TsIEI(IO) + TIL Buffer
Delay, il any.
[8] M1 must be active for a minimum 01 two clock cycles to reset the PIO.

319
--~--~--~------

~---.--.~-~~-~

AC CHARACTERISTICS (Continued)

Number Symbol

Parameter

Z84CZO
Mln(ns) Max(ns)

Z84CZD-4
Mln(ns) Max(ns)

26

TdSTB(PD)

STROBE ~ to PORT DATA Stable
(Mode 2)

230

210

27

TdSTB(PDr)

STROBE t to PORT DATA Float Delay
(Mode 2)

200

180

28

TdPD(INT)

PORT DATA Match to INT ~ Delay
(Mode 3)

540

29

TdSTB(INT)

STROBE t to INT ~ Delay

490

490
440

Comment

[5]
CL

= 50 pi

NOTE:
[5] Increase these values by 2 ns for each 10 pf increase in loading up to
100pfmax.

320

00-2362-01

Z84C30CMOS
Z80®CCTC
Couater/Timer Circuit

Advaace lalorDlatioa
AC aad DC Characteristics

Zilog

April 1985

ABSOWTE MAXIMUM RATINGS
Voltages on Vee with respectto Vss ..... - O.3V to + 7.0V
Voltages on all inputs with respect
to Vss ....................... - O.3V to Vee + O.3V
Storage Temperature .............. -65°Cto +150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This IS a stress rating only;
operation of the device at any condition above these indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

STANDARD TEST CONDITIONS
The characteristics below apply for the following test
conditions, unless otherwise noted. All voltages are
referenced to GND (OV). Positive current flows into the
referenced pin. Available operating temperature range is:

+5V
2.1K

• S = O°Cto +70°C, +4.50V"'Vee'" +5.50V

• E = -40°Cto +85°C, +4.50V'" Vee'" 5.50V
The Ordering Information section lists package temperature
ranges and product numbers. Refer to the Literature List for
additional documentation. Package drawings are in the
Package Information section.

DC CHARACTERISTICS
Symbol

Parameter

VILe
VI He
VIL
VIH
VOL
VOHl
VOH2
III
ILO
ICCl

Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Input Leakage Current
3·State Output Leakage Current in Float
Power Supply Current

ICC2

Standby Supply Current

IOHD

Darlington Drive Current

Over specified temperature and voltage range.

Min

Max

-0.3
Vee- O.6
-0.3
+2.2

+0.45
Vee+ 0.3
+O.B
Vee
+0.4

1\'p

V
V
V
V
V
V
V
",A

+2.4
Vee- O.B
±10
±10

7

10

-1.5

-5.0

Unit

IJ.A

3

rnA

0.5

",A

rnA

Test Condition

IOL = 2.0 rnA
IOH = -1.6rnA
IOH = - 250 IJ.A
VIN = 0.4 to Vee
VOUT = 0.4 to Vee
Vee = 5V
CLK = 4MHz
VIH = Vee - 0.2V
VIL = 0.2V
Vee = 5V
CLK = (0)
VIH = Vee - 0.2V
VIL = 0.2V
VOH = 1.5V
REXT = 1.1KQ

321

AC CHARACTERISTICS

f-0-\

'---0-

CLOCK

+0-

+

rL '\~ n L-il\
X

IX:

eso, CS1

~

~I

~

\-

Ci

~I

~

READ

\-

10RQ

I--1

--®--

=4
\.

-®- ~I

®-rr-~I---w- L}
\

~

\.

--®-I

AC CHARACTERISTICS

(Continued)

Z84C30

Number Symbol

Parameter

Z84C30·4

Mln(ns)

Max(ns)

Mln(ns)

Max(ns)

1

TcC

Clock Cycle Time

400

DC[l)

250

DC[l)

2

TwCh

Clock Pulse Width (High)

170

DC

105

DC

3

TwCl

Clock Pulse Width (Low)

170

DC

105

DC

4

TfC

Clock Fall Time

30

5

TrC

Clock Rise Time

30

6

Th

All Hold Times

Notes·

30
30

0

0

7

TsCS(C)

CS to Clock t Setup Time

250

160

8

TsCE(C)

CE to Clock t Setup Time

200

150

9

TsIO(C)

IORQ ~ to Clock t Setup Time

250

115

10

TsRD(C)

RD ~ to Clock t Setup Time

240

11

TdC(DO)

Clock t to Data Out Delay

240

200

12

TdC(DOz)

Clock ~ to Data Out Float Delay

230

110

13

TsDI(C)

Data In to Clock t Setup Time

14

TsMl(C)

Ml to Clock t Setup Time

15

TdM1(IEO)

Ml Ho lEO ~ Delay (Interrupt
immediately preceding M1)

300

190

[3)

16

TdIO(DOI)

IORQ ~ to Data Out Delay (INTA Cycle)

340

160

[2),[6)

17

TdIEI(IEOf)

lEI ~ 10 lEO ~ Delay

190

130

[3)

18

TdIEI(IEOr)

lEI t to lEO t Delay (after ED Decode)

220

160

[3)

19

TdC(INT)

Clock t 10 INT ~ Delay

(TcC+200)

(TcC+140)

[4)

20

TdClK(INT)

ClKITRG t 10 INT ~
tsCTR(C) salisfied
tsCTR(C) not salisfied

(19)+(26)
(1) + (19) + (26)

(19)+(26)
(1)+(19)+(26)

[5)
[5)

115

60

50

210

90

21

TcCTR

ClK/TRG Cycle Time

22

TrCTR

ClK/TRG Rise Time

23

TfCTR

ClK/TRG Fall Time

24

TwCTRI

ClK/TRG Widlh (Low)

200

200

25

TwCTRh

ClKITRG Width (High)

200

200

26

TsCTR(Cs)

ClKITRG t to Clock t Selup Time for
Immediate Count

300

210

27

TsCTR(Ct)

ClKITRG t to Clock t Setup Time for
enabling of Prescaler on following
clockt

300

28

TdC(ZCITOr)

Clock t 10 ZCITO t Delay

260

190

29

TdC(ZCITOf)

Clock ~ to ZCITO ~ Delay

190

190

'RESET must be active for a minimum of 3 clock cycles.
NarES
[1] TcC = TwCh + TwCI + TrC + TIC.
[2] Increase delay by 10 nsfor each 50 pfincrease In loading. 200 pf
maximum for data lines, and 100 pf for control lines.

00-2363-01

(2TcC)

(2TcC)
50

[2)

[5)
50

50

50

[5)

[4)

210

[3] Increase delay by 2 nsforeach 10 pflncrease in loading. 100 pf
maximum.
[4] Timer mode.
[5] Counter mode.
[6]25 TcC >(n-2) TdIEI(IEOf) + TdMl(IEO) + TsIEI(IO) + TTL buffer
delay. if any.

323

I

a

Z84C40CMOS
Z80®CSIO
SeriallDpat/Oatpat
AdvaDce latormatioD
AC aDd DC Characteristics

Zilog

April 1985

ABSOWTE MAXIMUM RATINGS
Voltages in Vee with respectto Vss ...... - O.3V to + O. 7V
Voltages on all inputs with respect
to Vss ....................... - O.3V to Vee + O.3V
Storage Temperature .............. -65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above these indicated In the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

STANDARD TEST CONDITIONS
+5V

The characteristics below apply for the following test
conditions, unless otherwise noted. All voltages are
referenced to GND (OV). Positive current flows into the
referenced pin. Available operating temperature range is:

2.1K

• S = O°Cto +70°C, +4.50V4!tVee4!t +5.50V

• E = -40°Cto +85°C, +4.50V4!tVee4!t5.50V
Refer to the Literature List for additional documentation.

DC CHARACTERISTICS
Symbol

Parameter

VILe
VI He
VIL
VIH
VOL
VOHl
VOH2
III
ILO
IL(SY)
ICCl

Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Input leakage Current
3-State Output leakage Current in Float
SYNC Pin leakage Current
Power Supply Current

ICC2

Standby Supply Current

Min
-0.3
Vee- 0.6
-0.3
+2.2

Max
+0.45
Vee+ 0.3
+O.B
Vee
+0.4

~p

V
V
V
V
V
V
V

+2.4
Vee- O.B
±10
±10
+10/-40
15

10

Unit

~
~
~

7

rnA

0.5

~

Thst Condition

IOL = 2.0 rnA
IOH = -1.6rnA
IOH = -250~
VIN = 0.4 to Vee
VOUT = 0.4 to Vee
VIN = 0.4 to Vee
Vee = 5V
ClK = 4MHz
VIH = Vee - 0.2V
VIL = 0.2V
Vee = 5V
ClK = (0)
VIH = Vee - 0.2V
VIL = 0.2V

Over specified temperature and voltage range.
00-2364-01

325

IS
•

Z800
Family

Zilog

11109 Z800TM Fa.....y
32·BII CapablUlle.
16·BII Archileclare
8-BII Compallbllity
Advance IDfomaalioD
March 1985

The advancing demands of the
marketplace require that microprocessor-based designs provide a
higher level of performance and
integration, while maintaining compatibility with existing investments in
software. With these goals in mind,
the Z800 MPU Family was designed
with features found on many 32-bit
machines, yet maintaining object
code compatibility with the Z80
microprocessor.

Performance
The Z800 MPU features a 16-bit
three-stage pipelined internal architecture, with its programming model
structured from the register file of the
Z80 CPU. The internal processor
clock speed starts at 10M Hz, with
up to 25 MHz speeds planned.
To fully benefit from the higher
CPU speeds without making severe
demands on memory access
speeds, a 256 byte instruction/data
cache memory is Integrated onchip. Burst transactions are also
supported which effectively pre-load
the cache for maximum utilization.

Furthermore, the external bus can
be configured for either the 8-bit Z80
Bus or the 16-Bit Z-BUS interface.
Under software control, the external
bus clock can be scaled, wait states
automatically inserted for both memoryand I/O address spaces, while
still maintaining a faster internal
clock rate. Additional performance
can also be realized by using the
Z800 extended addressing modes
and instructions. An Extended Processor Unit (EPU) interface is also
supported for such coprocessors as
the Z8070 Arithmetic Processing
Unit.

Memory Management
As much as 16M bytes can be
directly addressed by the Z800
MPU. The on-chip Memory Management Unit also provides access
protection and dynamic relocation.
The utility of the larger address
spaces is enhanced by the optional
separation of program and data as
well as the implementation of System
and User Modes.

Integration
System cost and board space has
been reduced through the integration of on-chip peripheral functions.
Four 24-bit DMA channels, three
counter/timers, one UART, a clock
oscillator, and a dynamic memory
refresher controller are all available
on the Z800 chip. These functions,
along with the MMU and cache
memory, result in an outstanding
combination of performance and
value integrated onto a single chip.

Support
MPU features can be converted to
system benefits with appropriate
development support tools. Zilog
support starts with the UNIX environment on either a Digital Equipment
Corporation VAX-11 or Zilog System
8000. Cross-software includes an
assembler, C-compiler, linker/loader,
as well as a library of utilities.

329

Z800™MPU
Family

Zilog

Preliminary
Product
SpeclflcatloB

September 19a3

FEATURES
•

High performance 16-bit Z-BUS interface or 8-bit
ZaO-compatible bus interface.

•

Enhanced zao® instruction set that maintains
object-code compatibility with zao microprocessor.

•

On-chip paged Memory Management Unit (MMU).

•

Four on-chip 16-bit counter/timers.

•

Large memory address space: 512K byte and 16M
byte versions.

•

Four on-chip DMA channels.

•

On-chip full duplex UART.

•

On-chip, high-speed local or cache memory.

•

10-25 MHz CPU processor clock.

GENERAL DESCRIPTION
Zilog's new zaoo family of a- and 16-bit microprocessors
features high-performance microprocessors designed to
give the end-user a powerful and cost effective solution
to application requirements. The family consists of the
a-bit Za~-Bus microprocessors that are packaged in 40and 64-pin dual in-line packages, and 16-bit Z-BUS
microprocessors in 40- and 64-pin packages. The zaoo
family incorporates advanced architectural features that
allow fast and efficient throughput and increased
memory addressing while maintaining zao object code
compatibility. zaoo microprocessors offer both a continuing growth path for present Z80-based designs and a
high-performance microprocessor for future designs.
Central to the zaoo microprocessors is an enhanced version of the zao Central Processing Unit (CPU), To assure
system integrity, the ZaOD microprocessors can operate
in either user or system mode, allowing protection of
system resources from user tasks and programs.
System mode operation is supported by the addition of
the system Stack Pointer to the working register set. The
IX and IY registers have been modified so that in addition
to their regular function as index registers, each register
can be accessed as a 16-bit general purpose register or
as two Single-byte registers.
The zao CPU instruction set has been retained, meaning
that the zaoo microprocessors are completely binarycode compatible with present zao code. The basic addressing modes of the zao microprocessor have been

augmented with the addition of Indexed mode with full
16-bit displacement, Program Counter Relative with
16-bit displacement, Stack Pointer Relative with 16-bit
displacement, and Base Index mode. The new addressing modes are incorporated into many of the old zao
CPU instructions, resulting in greater flexibility and
power. Some additions to the instruction set include
a-and 16-bit signed and unsigned multiply and divide,
a-and 16-bit sign extension, and a test and set instruction
to support multiprocessing. The 16-bit instructions have
been expanded to include 16-bit compare, memory increment, memory decrement, negate, add, and subtract,
in addition to the previously mentioned multiply and
divide.
A requirement of many of today's microprocessor-based
system designs is to increase the memory address
space beyond the 64K byte range of typical a-bit
microprocessors. The zaoo microprocessors have an
on-chip Memory Management Unit (MMU) that enables
the microprocessors to address either 512K bytes or
16M bytes, depending on the device package. In addition
to enabling the address space to be expanded, the MMU
performs other memory management functions
previously handled by dedicated off-chip memory
management devices.
I/O address' space has been expanded by the addition of
an I/O Page register used to select pages of I/O addresses. The a-bit I/O Page register can select one of

331

256 possible pages of I/O addresses to be active at one
time, allowing a total of 64K I/O addresses to be accessed.
There are 256 bytes of on-chip memory present on all
members of the l8DD family. This memory can be configured as a high-speed cache or as a fixed address local
memory. When configured as a cache, the memory can
be programmed to be instruction only, data only, or both
data and instruction. The cache memory allows programs to run significantly faster by reducing the number
of external bus accesses. Operation and update of the
cache is performed automatically and is completely
transparent to the user. When used as a local memory,
the addresses are programmable, allowing "RAMless"
systems to be used.
Many features that have traditionally been handled by
external peripheral devices have been incorporated in
the design of the l8DD microprocessors. The "on-chip
peripherals" reduce system chip count and reduce interconnection on the external bus. All members of the l8DD
family contain an on-chip clock oscillator. Also present is
a refresh controller that provides 1D-bit refresh addresses for dynamic memories.
The 64-pin versions of the l8DD MPU contain additional
on-chip peripherals to provide system design flexibility.
To support high-bandwidth data transmission four
Direct Memory Access (DMA) channels are incorp~rated
on-chip. Each DMA channel operates using full 24-bit
source and destination addresses with a 16-bit count.
The channels can be programmed to operate in single
transaction, burst, or continuous mode. System event
counting and timing requirements are met with the help
of the four 16-bit counter/timers. The counterltimer func~ions can be externally controlled with gate and trigger
Inputs, and can be programmed as retriggerable or
nonretriggerable. Also, a full duplex UART, capable of
handling a variety of data and character formats, is present to facilitate asynchronous serial communication.

Regardless of whether the 8- or 16-bit bus is used, all
members of the l8DD family feature programmable bus
timing, allowing the user to tailor timing to the individual
system. Upon reset the l8DD microprocessors can be
programmed to have system timing that is one-fourth,
one-half, or equal to the speed of the CPU, with one-half
being the default. In addition to clock scaling, programmable wait states can be inserted during various bus
transactions. Without the use of external hardware, one
to th~ee wait states can be inserted into memory, 1/0,
and Interrupt acknowledge transactions. Furthermore,
separate memory wait states can be specified for upper
and lower memory areas, facilitating the use of different
speeds of ROMs and RAMs in the same system.
An additional feature of the 16-bit bus interface is the
ability to support "nibble-mode" dynamic RAMs. Using
this feature (known as burst mode), the bus bandwidth of
memory read transactions is essentially doubled. Burst
mode transactions have the further benefit of allowing
the cache to operate more efficiently by guaranteeing a
high probability that the contents of the accessed
memory will be present in the cache.
The l8DD family supports lilog's Extended Processor Architecture (EPA) in a number of ways. All members are
capable of trapping Extended Processor Unit (EPU) instructions in order to perform software emulation of the
EPU. The l8216 directly interfaces with an EPU such as
the l8D7D Floating Point Unit and operates in a manner
that is completely transparent to the user and the program. The other members of the l8DD family can interface easily with EPUs with the aid of support software.
The pin functions of four versions of the l8DD MPU
l81D8, l82D8, l8116, and l8216, are shown in Figure~
1-4, respectively. A block diagram of the l8DD MPU is
shown in Figure 5.

Z800 CPU
User and System Modes of Operation

The l8DD CPU can operate in either user or system
mode. In user mode, some instructions cannot be executed and some registers of the CPU are inaccessible.
In general, this mode of operation is intended for use by
application programs. In system mode, all of the instructions can be executed and all of the CPU registers can
be accessed. This mode is intended for use with programs that perform operating system functions. This
separation of CPU resources promotes the integrity of
the system, since programs operating in user mode cannot access those aspects of the CPU that deal with
system interface events.

332

To further support the dual userlsystem mode, there are
two copies of the Stack Pointer-one for the user stack
and another for the system stack. These two stacks
facilitate the task switching involved when interrupts or
traps occur. To ensure that the user stack is free of
system information, the information saved on the occurrence of interrupts or traps is always pushed onto the
system stack before the new program status is loaded.

AD,
AD,
AD,
AD,
AD,
AD,
AD,
AD,

BUS
TIMING
AND
STATUS

A,

AD,
AD'_}
AD,

BUS {
TIMING

AND

ADa

STATUS

AD,
AD,
AD,

DATA

-

A"

ADDRESSI
DATA

AD4

=} .~~,.

Z8208
MPU

A"
A"
A"
A"

BUS CONTROL

A"

ADDRESS

A"
A"

Z8108
MPU

A"

INTERRUPTS

a

A"

BUS CONTROL {

A"
A"

ADDRESS

INTERRUPTS {

8

A"
A"

CfTl/O

II
.,.,
c:::I

XTALI

+5V

Figure 1. Z8108 Pin Functions

Figure 2. Z8208 Pin Functions

AS

os
aNi
R/W

BUS
TIMING
AND
STATUS

ST,
ST,
ST,
ADDRESSI
DATA

AD,
AD'-1
AD,
AD,
AD,
AD,
AD,

TIMING
BUS {
AND
STATUS

:~:
AD,
Z8118
MPU

f ::~:ESS'

Z8216
MPU

""; C"",RGL {

AD10
AD11
AD12

BUS CONTROL {

ADn
AD14
AD15~

INTERRUPTS {

} ADDRESS

- - . . GND

Figure 3. Z8116 Pin Functions

2259-001, 002,

003, 004

Figure 4. Z8216 Pin Functions

333

INTERNAL

~~

BUS

ADDRESS/DATA
BUS

:~

ADDRBSS
BUS

)

CPU

"

A

BUS
INTERFACE

'4
~

CONTROL

256 BYTE
MEMORY

BUS

y

MEMORY
MANAGEMENT
UNIT

~

I - NMI
I - INTA
I - INT.*
I - INTc*

~

CLOCK
OSCILLATOR

A

~

'4

Y

A

~

I-

RDYO * -

"
r-

l-

RDY1 * -

'C

RDYa * -

COUNTER·
TIMER

"
0

1

I

2

3

CTI1*
CTI01*
CTI.*

I

1
2

I

CTlo*

I - CTIO.*

0

I

---

. - CTIOo*

I'"

IjL ~

DMA
CHANNEL

RDYa * -

I - Rx*
f..--. Tx*

UART

'C

DMASTBO * -

DMASTB1 * -

REFRESH
ADDRESS
GENERATOR

3

T

I

*Z8218 only

Figure 5. Z800 MPU Block Diagram
Address Spaces
The Z800 CPU architecture supports four distinct ad·
dress spaces corresponding to the different types of
locations that can be accessed by the CPU. These four
address spaces are:
•

CPU register space

•

CPU control and status register space

•

Memory address space

•

110 address space

CPU Register Space. The CPU register space consists
of all of the registers in the CPU register file. The CPU
registers are used for data and address manipulation.
Access to these registers is specified in the instruction.
The CPU registers are labeled F, A, B, C, 0, E, H, L, F',
A', B', C', 0', E', H', L', IX, IY, SSP, USP, PC, I, and R.

334

CPU Control and Status Register Space. The CPU
control register space consists of all of the control and
status registers found in the CPU control register file.
These registers govern the operation of the CPU and are
accessible only by the privileged Load Control instruc·
tion. The registers in the CPU control file consist of the
Master Status register, Bus Timing and Initialization
register, Bus Timing and Control register, InterruptlTrap
Vector Table Pointer, 110 Page register, System Stack
Limit register, Trap Control register, Interrupt Status
register, Cache Control register, and Local Address
register.
Memory Address Space. Two memory address spaces
are supported by the Z800 CPU; one for user and one for
system mode of operation. They are selected by the
User/System Mode (U/S) bit in the Master Status
register, which governs the selection of page descriptor
registers during address translation.

Each address space can be viewed as a string of 64K
bytes numbered consecutively in ascending order. The
a-bit byte is the basic addressable element in the
memory address spaces. However, there are other addressable data elements: bits, 2-byte words, byte strings
and multiple-byte EPU operands.
The address of a multiple-byte entity is the address of the
byte with the lowest address. Multiple-byte entities can
be stored beginning at either even or odd memory addresses.
I/O Address Space. I/O addresses are generated only
by the 1/0 instructions IN, OUT, and the 1/0 block move
instructions. Logical 1/0 addresses are eight bits in
length, augmented by the A register on lines Aa-A15 in
Direct Address addressing mode and by the B register
on lines Aa-A15 in Indirect Register addressing mode
and for block 1/0 instructions. The 16-bit logical 1/0 address is always extended by appending the contents of
the a-bit page register to the augmented 1/0 address.
Thus the complete address generated to address an 1/0
port consists of an 1/0 page number on A23-A16, the contents of the A or B register on Aa-A15, and the a-bit 1/0
address on A7-Ao.
Unlike memory references, in which a 16-bit word store
or fetch can generate two memory references, an 1/0
word store or fetch is always one 1/0 bus transaction,
regardless of bus size or 1/0 port address. Note,
however, that on-chip peripherals with word registers
are accessed via word 1/0 instructions for those 16-bit
registers, regardless of the external bus size.

Data Types
The CPU can operate on bits, binary-coded decimal
(BCD) digits (4 bits), bytes (a bits), words (16 bits), byte
strings, and word strings. Bits in registers or memory
can be set, cleared, and tested. BCD digits, packed two
to the byte, can be manipulated with the Decimal Adjust
Accumulator instruction in conjunction with binary addition and subtraction. Bytes are operated on by a-bit load,
arithmetic, logical, and shift and rotate instructions.
Words are operated on in a similar manner by the 16-bit
load and 16-bit arithmetic instructions. Block move and
search operations can manipulate byte strings up to 64K
bytes long. Block 1/0 word instructions can manipulate
word strings up to 32K words long. To support EPU
operations, byte strings up to 16 bytes in length can be
transferred by the CPU.
CPU Registers
The ZaDD MPU contains 23 programmable registers in
the CPU register address space. These registers are
illustrated in Figure 6.
Primary and Working Register Set. The working
register set is divided into the two a-bit register
files-the primary file and alternate (designated by ,
[prime]) file. Each file contains an a-bit accumulator (A),
a Flag register (F), and six general-purpose registers (B,
C, D, E, H, and L). Only one file can be active at any
given time. Upon reset, the primary register file is active.
Exchange instructions allow the programmer to exchange the active file with the inactive file.

PRIMARY FILE

A

ACCUMULATOR

AUXILIARY FILE

F

FLAG REGISTER

A'

ACCUMULATOR

F'

FLAG REGISTER

B

GENERAL PURPOSE

C

GENERAL PURPOSE

B'

GENERAL PURPOSE

C'

GENERAL PURPOSE

D

GENERAL PURPOSE

E

GENERAL PURPOSE

D'

GENERAL PURPOSE

E'

GENERAL PURPOSE

H GENERAL PURPOSE

L

GENERAL PURPOSE

H'

GENERAL PURPOSE

L'

GENERAL PURPOSE

""'1
..1 - - - - 8 B I T S - - -••

I

INTERRUPT VECTOR

I

I

R

I

IX INDEX REGISTER

IY INDEX REGISTER

PC PROGRAM COUNTER

SP STACK POINTER
USER

L

tl

SYSTEM

""'1.........- - - - - - - 1 6 B I T S - - - - - - - _ · 1

Figure 6. CPU Register Configuration

335

The accumulator is tne destination register for 8-bit
arithmetic and logical operations. The six generalpurpose registers can be paired (BC, DE, and HL) to form
three 16-bit general-purpose registers. The HL register
pair serves as a 16-bit accumulator for 16-bit arithmetic
operations.

CPU Flag Register. The Flag register contains six flags
that are set or reset by various CPU operations. This
register is illustrated in Figure 7.

Program Counter. The Program Counter (PC) is used to
sequence through instructions in the currently-executing
program and to generate relative addresses. The Program Counter contains the 16-bit logical address of the
current instruction being fetched from memory.

R Register. The R register can be used !:is a generalpurpose 8-bit readlwrite register. The R register is not
associated with the refresh address and its contents are
changed only by the user.
Stack Pointers. Two hardware Stack Pointers, the user

7

Is I z I

0
0

I HID IplVl

N

Ic

I

Figure 7_ CPU Flag Register
The flags in this register are:
Carry (C). This flag is set when an add instruction

generates a carry or a subtract instruction generates a
borrow. Certain logical and rotate and shift instructions
affect the Carry flag.
Add/Subtract (N). This flag is used by the Decimal Adjust

Accumulator instruction to distinguish between add and
subtract operations. The flag is set for subtract operations and cleared for addition operations.

Stack Pointer (USP) and the system Stack Pointer (SSP),
support the dual mode of operation of the
microprocessor. The SSP is used for saving information
when an interrupt or trap occurs, and for supporting
subroutine calls and returns in system mode. The USP is
used for supporting subroutine calls and returns in user
mode.
Status and Control Registers_ There are ten status and
control registers available to the programmer in the
Z8DD MPU. Table 1 shows the addresses occupied by
the registers in the status and control register addressing space.
Table 1. Status and Control Register Addressing Space

Parity/Overflow (PIV). This flag is set or cleared depend-

ing on the operation being performed. During arithmetic
operations it is set to indicate a twos complement
overflow. During logical and rotate operations, this flag
is set to indicate even parity of the result, or cleared to
indicate odd parity.
Half Carry (H). This flag is set if an 8-bit arithmetic operation generates a carry or borrow between bits 3 and 4, or
if a 16-bit operation generates a carry or borrow between
bits 11 and 12. This bit is used to correct the result of a
packed BCD addition or subtract operation.
Zero (Z). This flag is set if the result of an arithmetic or

logical operation is a zero.
Sign (S). This flag stores the state of the most significant
bit of the accumulator. The Sign flag is also used to indicate the results of a test and set instruction.

Dedicated CPU Registers

Index Registers. The two Index registers, IX and IY,
each hold a 16-bit base address that is used in the Index
addressing mode. The Index registers can also function
as general-purpose registers with the upper and lower
bytes capable of being accessed individually. The high
and low bytes of the IX register are called IXH and IXL.
The high and low bytes of the IY register are called IYH
and IYL.

Control Register Name
Bus Timing and Control
Bus Timing and Initialization
Cache Controi1
Interrupt Status
InterruptlTrap Vector Table
1/0 Page Register
Local Address Register2
Master Status (MSR)
Stack Limit
Trap Control

Address
(Hexadecimal)
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control

02
FF
12
16
06
08
14
00
04
10

NOTES:
1. See section on on-chip memory for register description.
2. See section on multiprocessing mode of operation for register description.

Bus Timing and Control Register. This 8-bit register
(Figure 8) governs the timing of transactions to high
memory addresses and the daisy-chain timing for interrupt requests, as well as the functionality of requests on
the various Z800 MPU interrupt request lines. On reset,
this register is cleared to all as.

Interrupt Register. The Interrupt register (I) is used in interrupt mode 2 to generate a 16-bit indirect logical address to an interrupt service routine. The Interrupt
register supplies the upper eight bits of the indirect address and the interrupting peripheral supplies the lower
eight bits.
336

Figure 8_ Bus Timing and Control Register

2259.Q()7,008

The fields in this register are:
I/O Wait Insertion (lID). This 2-bit field specifies the
number of additional wait states (in addition to the one
automatically inserted for 110) to be inserted by the CPU
in both 1/0 transactions and vector response timing (00
none, 01
one, 10
two, 11
three).

=

=

=

=

High Memory Wait Insertion (HM). This 2-bit field
specifies the number of automatic wait states (00
none, 01
one, 10
two, 11
three) for the CPU to
insert in memory transactions when the MMU is enabled
and there is a 1 in bit 15 of the selected page descriptor
register.

=

=

=

=

Daisy Chain Timing (DC). This 2-bit field determines the
number of additional automatic wait states the CPU inserts while the interrupt acknowledge daisy chain is settling (00
none, 01
one, 10
two, 11
three). A
value of 01 in the DC field indicates that one additional
cycle will be added to the four cycles that normally
elapse between interrupt acknowledge, AS and DS
assertions.

=

=

=

Multiprocessor Configuration Enable (MP). This 1-bit field
enables the multiprocessor mode of operation (0 =
disabled, 1
enabled). (See the multiprocessor mode
section).

=

Bootstrap Mode Enable (BS). This 1-bit field enables the
bootstrap mode of operation (0 = disabled, 1 = enabled). (See the UART section for details about bootstrap
mode.)

Interrupt Status Register. This 16-bit register (Figure
10) indicates which interrupt mode is in effect and which
interrupt sources have interrupt requests pending. It also
contains the bits that specify whether the interrupt inputs are to be vectored. Only the interrupt vector enable
bits are writeable; all other bits are read-only.

=

Bus Timing and Initialization Register. This 8-bit
register (Figure 9) is used to specify the duration of control signals for the external bus when the MMU is disabled or when the MMU is enabled and there is a 0 in bit
15 of the selected page descriptor register. It also controls the relationship between internal processor clock
rates and bus timing. It can be programmed by external
hardware upon reset.
During reset this register is initialized to one of two settings, depending on the state of the Wait input line on the
rising edge of reset: if the Wait line is not asserted, the
register is set to OOH. If the Wait line is asserted during
reset, then this register is set to the contents of the AD
lines.

I

Figure 10. Interrupt Status Register

!

The fields in this register are:
Interrupt Request Pending (lP). When bit IPn is set to 1,
an interrupt request from sources at level n is pending.
(See the Interrupt and Trap Structure section.)
Interrupt Mode (1M). A value of n in this 2-bit field indicates that interrupt mode n is in effect. This field can
be changed by executing the 1M instruction.
Interrupt Vector Enable (I). These four bits indicate
whether each of the four interrupt inputs are to be vectored. When In is set to 1, interrupts on the Interrupt n
line are vectored when the CPU is in interrupt mode 3;
when cleared to 0, all interrupts on this line use the same
entry in the InterruptlTrap Vector Table. These bits are
ignored except in interrupt mode 3.

Interrupt/Trap Vector Table Pointer. This 16-bit
register (Figure 11) contains the most significant 12 bits
of the physical address at the beginning of the InterruptlTrap Vector Table; the lower 12 bits of the physical
address are assumed to be O. The four least significant
bits of this register must be O.

Figure 9. Bus Timing and Initialization Register

The fields in this register are:
Clock Scaling (CS). This 2-bit field specifies the scaling of
the CPU clock for all bus transactions (00 = one bus
clock cycle is equal to two internal processor clock
cycles, 01 = bus clock cycle is equal to the internal
processor clock cycle, 10
one bus clock cycle is
equal to four internal processor clock cycles, 11
reserved). This field cannot be modified by software.

110 Page Register. This 8-bit register (Figure 12) in-

Low Memory Wait Insertion (LM). This 2-bit field
specifies the number of automatic wait states (00
none, 01
one, 10
two, 11
three) for the CPU to
insert in memory transactions when the MMU is disabled
or when the MMU is enabled and there is a 0 in bit 15 of
the selected page descriptor register.

1~1~1~1~1~·IA~I~7IA~1

=

=

=

=

=

=

Figure 11. InterruptITrap Vector Table Pointer

dicates the bits to be appended to the 16 bits that are
output during 110 transactions during the 1/0 address
phase.
7

0

Figure 12. 110 Page Register
2259-008, 010, 011, 012

337

Maste, Status Reglste,. The Master Status register
(Figure 13) is a 16-bit register containing status information about the currently-executing program. This register
is cleared to 0 during reset.

T,ap Cont,ol Register. This 8-bit register (Figure 15)
enables the maskable traps.
7

0

101010101011lEI81
0

~

I I I I I I Esp) ss I IEa IEa I £41 QJ E2I IEo I
0

UlS

0

BH

0

0

0

E1

Figure 13. Master Status Register

The bits in this register are:

The fields in this register are:
Interrupt Request Enable (EnJ. There are seven Interrupt
Enable bits, one for each type of maskable interrupt
source (both external and internal). When bit En is set to
1, interrupt requests from sources at level n are accepted by the CPU; when this bit is cleared to 0, interrupt
requests at level n are not accepted.
Single-Step (SS). While this bit is set to 1, the CPU is in
Single-stepping mode; while this bit is cleared to 0,
automatic single-stepping is disabled. This bit is
automatically cleared when a trap or interrupt is taken.
Single-Step Pending (SSP). While this bit is set to 1, the
CPU generates a trap prior to executing an instruction.
The SS bit is automatically copied into this field at the
completion of each instruction. This bit is automatically
cleared to 0 when a Single-Step, Page Fault, Privileged
Instruction, Break-on-Halt or Division trap is taken so
that the SSP bit in the saved Master Status register is
cleared to O.
Breakpoint-on-Halt Enable (BH). While this bit is set to 1,
the CPU generates a Breakpoint trap whenever a halt instruction is encountered; while this bit is cleared to 0, the
halt instruction is executed normally.
User/System Mode (U/S). While this bit is cleared to 0,
the CPU is in the system mode of operation; while it is
set to 1 the CPU is in the user mode of operation.

System Stack Limit Registe,. This 16-bit register
(Figure 14) indicates when a System Stack Overflow
Warning trap is to be generated. If enabled by setting a
control bit in the Trap Status register, pushes onto the
system stack cause the 12 most significant bits in this
register to be compared to the upper 12 bits of the
system Stack Pointer and a trap is generated if they
match. The low-order four bits of this register must be O.
0

~

IA1sIA1.IA+1.IAnIA1.1 1101 1101 A71 1101 Asl A41 0101010 1
Figure 14. System Stack Limit Register

338

Figure 15. Trap Control Register

System Stack Overflow Warning (S). While this bit is set
to 1 the CPU generates a Stack Overflow Warning trap
when the system stack enters the specified region of
memory. Upon reset this register is initialized to all Os.
EPU Enable (E). While this bit is cleared to 0, the CPU
generates a trap whenever an EPA instruction is encountered.
Inhibit User I/O (I). While this bit is set to 1, the CPU
generates a Privileged Instruction trap when an I/O instruction is encountered in user mode.

Cache Control and Local Address Registers. See the
on-chip memory section for information about the Cache
Control register, and the multiprocessor mode section
for information about the Local Address register.
Interrupt and Trap Structure
The l800 MPU provides a very flexible and powerful interrupt and trap structure. Interrupts are external asynchronous events requiring CPU attention, and are
generally triggered by peripherals needing service.
Traps are synchronous events resulting from the execution of certain instructions.
Interrupts. Two types of interrupt, nonmaskable and
maskable, are supported by the l800 MPU. The nonmaskable interrupt (NMI) cannot be disabled (masked)
by software and is generally reserved for highest priority
external events that require immediate attention.
Maskable interrupts, however, can be selectively disabled by software. Both nonmaskable and maskable interrupts can be programmed to be vectored or nonvectored. The CPU accepts interrupts between instructions
with the exception of the block move, search, and I/O instructions, which can be safely interrupted after any
iteration and restarted after the interrupt is serviced.

Interrupt Sources. The l800 MPU accepts nonmaskable interrupts on the NMI pin o!!!l: The l800 MPU
accepts maskable interrupts on the INT pins, and from
the on-chip counterltimers, DMA channels, and the
UART receiver and transmitter. The 40-pin members of
the l800 family accept maskable interrupts on INTA
only.

2259-013,014,015

Interrupt Lines A, B, and C can be selectively programmed to support vectored interrupts by setting the appropriate bits in the Interrupt Status register. The external interrupts can be programmed to be vectored or
nonvectored in interrupt mode 3.

Interrupt Modes of Operation. The CPU has four
modes of interrupt handling. The first three modes extend the l80 interrupt modes to accommodate additional interrupt input lines in a compatible fashion. The
fourth mode provides more flexibility in handling the interrupts. On-chip peripherals use the fourth mode
regardless of which mode is selected for externally
generated interrupt requests. The interrupt mode is
selected by using the privileged instructions 1M 0, 1M 1,
1M 2, or 1M 3. On reset, the l800 MPU is automatically
set to interrupt mode O. The current interrupt mode in effect can be read from the Interrupt Status register.
Mode O. This mode is identical to the 8080 interrupt
response mode. With this mode, the interrupting device
on any of the maskable interrupt lines can place a call or
restart instruction on the data bus and the CPU will execute it. As a result, the interrupting device, instead of
the memory, provides the next instruction to be executed.
Mode 1. When this mode is selected, the CPU responds
to a maskable external interrupt by executing a restart to
the logical address 0038H in the system program address space.
Mode 2. This mode is a vectored interrupt response
mode. With a single 8-bit byte from the interrupting
device, an indirect call can be made to any memory
location. With this mode the system maintains a table of
16-bit starting addresses for every interrupt service
routine. This table can be located anywhere in the
system mode logical data address space on a 256-byte
boundary. When an interrupt is accepted, a 16-bit pOinter
is formed to obtain the desired interrupt service routine
starting address from the table. The upper eight bits of
this pOinter are formed from the contents of the I
register. The lower eight bits of the pointer must be supplied by the interrupting device. The 16-bit pointer so
formed is treated as a logical address in the system data
address space, which can be translated by the MMU to a
physical address.
Mode 3. This is the intended mode of operation for
systems that take advantage of the enhancements of the
Z800 microprocessor family (such as single-step and
userlsystem mode) since the Master Status register is
automatically saved and another loaded for the interrupts. Also, vector tables can be used for the external interrupt sources to provide more interrupt vectors for the
28000™ family, l80 family, and l8500 Universal
Peripherals.

When an interrupt request (either maskable or nonmaskable) is accepted, the Master Status register, the
address of the next instruction to be executed, and a
16-bit "reason code" are pushed onto the system stack.
A new Master Status register and Program Counter are

then fetched from the InterruptlTrap Vector Table. The
"reason code" for externally generated interrupts is the
contents of the bus during the interrupt acknowledge sequence; for 8-bit data buses, the most significant byte of
the reason code is zero. For interrupts generated by onchip peripherals, the reason code identifies which
peripheral generated the interrupt and is identical to the
vector address in the InterruptiTrap Vector Table. The Interrupt/Trap Vector Table Pointer is used to reference
the table.

Traps. The l800 CPU supports eight traps that are
generated internally. The following traps can be disabled: the EPA trap, which allows software to emulate an
EPU; the Stack Warning trap, which is taken at the end of
an instruction causing the trap; the Breakpoint-on-Halt
trap, which is taken when a halt instruction is encountered; and the Single-Step trap, which is taken for
each instruction. In addition, 110 instructions can be
specified as privileged instructions. Traps cause the instruction to be terminated without altering CPU registers
(except for the system Stack Pointer, which is modified
when the program status is pushed onto the system
stack).
The saving of the program status on the system stack
and the fetching of a new program status from the Interrupt/Trap Vector Table is the same in any interrupt mode
of operation.
Traps can only occur if the trap generating features of
the l800 CPU (such as System Stack Overflow warning)
have been explicitly enabled. Traps cannot occur on instructions of the l80 instruction set unless explicitly
enabled by the operating system using l800 CPU extensions.
Extended Instruction. This trap occurs when the CPU encounters an extended instruction while the Extended
Processing Architecture (EPA) bit in the Trap Control
register is O. Four trap vectors are used by the EPA
trap-one for each type of EPA instruction. This greatly
simplifies trap handlers that use 110 instructions to access an EPU or software to emulate an EPU.
Privileged Instruction. This trap occurs whenever an attempt is made to execute a privileged instruction while
the CPU is in user mode (UserlSystem Mode control bit
in the Master Status register is 1).
System Cal!. This trap occurs whenever a System Call
(SC) instruction is executed.
Access Violation. This trap occurs whenever the MMU's
translation mode is enabled and an address to be
translated is invalid or (for writes) is write-protected.
System Stack Overflow Warning. This trap occurs only
while the Stack Overflow Warning bit in the Trap Control
register is set to 1. For each system stack push operation, the most significant bits in the Stack Pointer
register are compared with the contents of the Stack
Limit register and a trap is signaled if they match. The
Stack Overflow Warning bit is then automatically cleared
in order to prevent repeated traps.

339

IN
00

8
•

!
....

Division Exception. This trap occurs whenever the
divisor is zero (divide-by-zero case) or the true quotient
cannot be represented in the destination precision
(overflow); the CPU flags are set to distinguish these two
cases.
Single-Step. This trap occurs before executing an instruction if the Single-Step Pending control bit in the
Master Status register is set to 1. Two control bits in the
Master Status register are used for the Single-Step trap.
The Single-Step bit (bit 8), on being set when previously
clear, causes a trap to occur after the execution of the
next instruction. While this bit is set to 1, if an instruction
execution causes a trap, the Single-Step trap occurs
after the execution of the trap-handling routine. The
Single-Step Pending bit (bit 9), is used by the processor
to ensure that only one Single-Step trap occurs for each
instruction executed while the Single-Step bit is set to 1.
Breakpoint-on-Halt. This trap occurs whenever the
Breakpoint-on-Halt control bit in the Master Status
register is 1 and a halt instruction is encountered.

Interrupt and Trap Disabling. Maskable interrupts can
oe enabled or disabled independently via software by
setting or clearing the appropriate control bits in the
Master Status register.
A 7-bit mask field in the Master Status register indicates
which of the requested interrupts will be accepted. Interrupt requests are grouped as follows, with each group
controlled by a separate Interrupt Enable control bit. The
list is presented in order of decreasing priority, with
sources within a group listed in order of descending
priority.
•

Maskable Interrupt A line (bit 0)

•

Counter/Timer 0, DMAO (bit 1)

•

Maskable Interrupt B line (bit 2)

•

Counter/Timer 1, UART receiver, DMA 1 (bit 3)

•

Maskable Interrupt C line (bit 4)

•

Counter/Timer 2, UART transmitter, DMA2 (bit 5)

•

Counter/Timer 3, DMA3 (bit 6)

When a source of interrupts has been disabled, the CPU
ignores any interrupt request from that source.
The System Stack Overflow Warning trap, I/O instructions in user mode trap (Privileged Instruction trap), or
Extended Instruction trap can be enabled by setting control bits in the Trap Control register, and the Single-Step
and Breakpoint-on-Halt trap can be enabled by setting
control bits in the Master Status register; these are the
only traps that can be disabled.

InterruptlTrap Vector Table. The format of the Interrupt/Trap Vector Table consists of pairs of Master Status
register and Program Counter words, one pair for each

340

separate on-chip interrupt or trap source. For each external interrupt, there is a separate Master Status
register word and Program Counter word (for use if the
input is not vectored). If the external interrupt is vectored, a vector table consisting of one Program Counter
word for each of the 128 possible vectors that can be
returned for each input line is used instead of the
dedicated Program Counter word; thus for vectored interrupts, there is only one Master Status register for
each interrupt type.
The format of the InterruptiTrap Vector Table is shown in
Table 2.

Table 2. InterruptITrap Vector Table
Address
(Hexadecimal)

00
04
08
OC
10
14
18
lC
20
24
28
2C
30
34
38
3C

40
44
48
4C

50

54
58

5C
60
64
68-6C
70-16E

170-26E
270-36E

Contents
Unused
NMI Vector
Interrupt Line A Vector (End of Process)
Interrupt Line B Vector
Interrupt Line C Vector
C-TO
C-T1
C-T2
C-T3
DMAO Vector
DMAI Vector
DMA2 Vector
DMA3 Vector
UART Receiver Vector
UART Transmitter Vector
Single-Step Trap Vector
Breakpoint-on-Halt Trap Vector
Division Exception Trap Vector
Stack Overflow Warning Trap Vector
Page Fault Trap Vector
System Call Trap Vector
Privileged Instruction Trap Vector
EPU - Memory Trap Vector
Memory - EPU Trap Vector
A - EPU Trap Vector
EPU Internal Operation Trap Vector
Reserved
128 Program Counters for NMI and Interrupt line A Vectors (MSR from 04 and
08, respectively)
128 Program Counters for Interrupt Line
B Vectors (MSR from OC)
128 Program Counters for Interrupt Line
C Vectors (MSR from (0)

Addressing Modes
Addressing modes (Figure 16) are used by the CPU to
calculate the effective address of an operand needed for
execution of an instruction. Nine addressing modes are
supported by the zaoo CPU. Of these nine, four are additions to the zao addressing modes (Indexed with 16·bit
displacement, Stack Pointer Relative, Program Counter
Relative, and Base Index) and the remaining five modes
are either existing or extensions to the existing zao ad·
dressing modes.

Register. The operand is one of the a-bit registers (A, B,
C, D, E, H, L, IXH, IHL, IYH or IYL); or one of the 16-bit
registers (BC, DE, HL, IX, IY, or SP), or one of the special
byte registers (lor R).
Immediate. The operand is in the instruction itself and
has no effective address.

Register Indirect. The contents of a register specify the
effective address of an operand. The HL register is the
register most often used for memory accesses. The C
register is used for I/O and control register space accesses.

Direct Address. The effective address of the operand is
the location whose address is contained in the instruc-

tion. Depending on the instruction, the specified operand
is either in I/O or data memory space.

Index. The effective address of the operand is the location specified by adding the 16-bit address contained in
the instruction to a twos complement "index" contained
in the HL, IX, or IY register.
Short Index. The effective address of the operand is the
location computed by adding the a-bit twos complement
signed displacement contained in the instruction to the
contents of the IX or IY register. This addressing mode is
equivalent to the zao CPU indexed mode.

Relative. An a- or 16·bit displacement contained in the
instruction is added to the Program Counter to generate
the effective address of the operand.

Stack Pointer Relative. The effective address of the
operand is the location computed by adding a 16-bit twos
complement displacement contained in the instruction
to the contents of the Stack Pointer.

Base Index. The effective address of the operand is the
location whose address is computed by adding the contents of H L, IX, or IY to the contents of another of these
three registers.

Instruction Set
Notation
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations as shown in the instruction set.
BX
DA
1M
IR
X
R
RA
RX
SP
SR
SX
n
nn

Base Index
Direct Address
Immediate constant
Indirect Register
Index
Single register of the set (A, B, C, D, E, H, L)
Relative address
A byte in the IX or IY register
Cu rrent Stack Pointer
Stack Relative
Short Index
a-bit constant
16-bit constant

Symbols. The following symbols are used to describe
the instruction set.
dst
src
n
nn
SP
p
(C)
SSP
USP

(Destination location or contents)
(Source location or contents)
(An a-bit constant)
(A 16-bit constant)
(Current Stack Pointer)
(Interrupt mode)
(I/O port pointed to by C register)
(System Stack Pointer)
(User Stack Pointer)

Assignment of a value is indicated by the symbol" -".
For example,
* AbbrevIated set

dst - dst

+

src

indicates that the sou rce data is added to the destination
data and the result is stored in the destination location.
The notation "addr(n)" is used to refer to bit "n" of a
given location. For example,
dst(7)
specifies bit 7 of the destination.

Flags. The F register contains the following six flags.
C
H
N
P/v
S
Z

Carry flag
Half carry flag
Add/Subtract flag
Parity/Overflow flag
Sign flag
Zero flag

Condition Codes. The following symbols describe the
condition codes.
z·
NZ·
C·
NC·
S
NS
V
PE
PO
P
M

Zero
Not zero
Carry
No carry
Sign
No sign
Overflow
Parity even
Parity odd
Positive
Minus

341

Mode

In the Instruction

Register

I

Immediate

Register
Indirect

Operand Value

Operand Addressing

REGISTER ADDRESS

In a Register

rl

OPERAND

In Memory or I/O

I

The content of the
register

In the instruction

OPERAND

1 REGISTER ADDRESS

Direct
Address

r[1~A~D~DR~E~S~S}----

~[I~O~P~ER~A~N~DJI

The content of the location
whose address is in the
register

I

The content of the location
whose address is in the
instruction

.......

It,

ADDRESS

OPERAND

REGISTER ADDRESS

·Index

BASE ADDRESS

OPERAND

I

The content of the location
whose address is in the 16·bit
register, offset by the 8·bit
displacement in the
instruction

REGISTER ADDRESS

Short Index

DISPLACEMENT

• Relative

·Stack Pointer
Relative

·Baselndex

The content of the location
whose address is the 16·bit
address in the instruction,
offset by the content of
the 16·bit register

I

PCVALUE

~

•

[!D~IS~PL~A~C!EM~E~N~T:}-~====~-O-PE-R-A-ND'"1

SPVALUE

~

•

[!D~IS=PL~A~C!EM~E~N~T:}-~====--0--II""""O-PE-R-AN-D"1

The content of the location
whose address is the
content of the Program
Counter, offset by the
displacement in the
instruction
The content of the location
whose add ress is the
content of the Stack
Pointer, offset by the
displacement in the
instruction
The content of the location
whose address is the
content of a register,
offset by the displacement
in a register

REGISTER ADDRESS 1
REGISTER ADDRESS 2

* New Z800 Family addressing modes

Figure 16. Addressing Modes

342

2259-016

8·BII Load Group
Flags
Instruction

Addressing Modes

S

Z

H PN N

EXA,src

src= R,RX,IR,DA,X,SX,
RA,SR,BX

•

•

•

• •

Operation
Exchange Accumulator
A-src

•

EXH,L

•

C

•

•

•

•

•

Exchange H,L
H-L

src=A
dst= R,RX,IR,DA,X,
SX,RA,SR,BX,
(BC),(DE)
or
src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX,
(BC),(DE)
dst=A

•

dst=R
src = R,RXt,lM,lR,SX
or
dst = R,RXt,lR,SX
src=R

•

dst= R,RX,IR,DA,X,
SX,RA,SR,BX

•

dst=A
src = IR or SX in user
space
or
dst = IR or SX in user
space
src=A

•

dst=A
src = IR or SX in user
space
or
dst= IR or SX in user
space
src=A

•

Instruction

Addressing Modes

S

Z

H PN N

C

Operation

EX src,HL

src = DE,IX,IV

•

•

•

•

Exchange HL with
Addressing Register

LD dst,src

LD dst,src

LD dst,n

* LDUD dst,src

* LDUP dst,src

•

•

•

•

•

Load Accumulator
dst +- src

I
II

:I
•

•

•

•

•

Load Register (Byte)
dst +- src

•

•

•

•

•

Load Immediate (Byte)
dst +- nn

t

•

t

•

t

Load in User Data
Space (Byte)
dst +- src

*

•

*

•

t

Load In User Program
Space (Byte)
dst +- src

16-BII Load Group
Flags

•

•

src - HL
• PrlYlleged Instruction.
t Accessing bytes of IX or IY precludes us. of H or L.

343

16-Bit Load Group (Continued)
Flags
Instruction

Addressing Modes

S

Z

H PN N

C

Operation

EX (SP),dst

dst= HL,IX,IY

•

•

•

•

•

Exchange Addressing
Register with Top
of Stack

•

(SP) - dst
EXAF,AF'

*

t

t

* * *

Exchange Accumulator!
Flag with
Alternate Bank
AF-AF'

•

EXX

•

•

•

•

•

Exchange ByteiWord
Registers with Alternate
Bank
BC-Be'
DE- DE'
HL- HL'

LO(W] dst,src

dst= HL,IX,IY
src= IM,DA,X,RA,SR,BX
or
dst = DA,X,RA,SR,BX
src= HL,IX,IY

•

•

•

•

•

•

LO(W] dst,src

dst = BC,DE,HL,SP
src= IM,IR,DA,SX
or
dst= IR,DA,SX
src= Be,DE,HL,SP

•

•

•

•

•

•

dst= RR,IR,DA,RA

•

LOW dst,nn

Load Addressing
Register
dst +- src

Load Register Word
dst ... src

•

•

•

•

•

Load Immediate Word
dst +- nn

LO(W] dS!,nn

ds!= RR

•

•

•

•

•

•

Load Immediate Word
dst +- nn

LD(W] dst,src

LDAdst,src

POPdst

dst=SP
src = HL,IX,IY,IM,IR,
DA,SX
or
dst= IR,DA,SX
src=SP

•

dst= HL,IX,IY
src = X,RA,SR,BX

•

dst = RR*,IR,DA,RA

•

•

•

•

•

•

Load Stack Pointer
dst - src

•

•

•

•

•

Load Address
ds! - address (src)

•

•

•

•

•

POP
dst - (SP)
SP-SP+2

PUSH src

344

src = RR*,IM,IR,DA,
RA

•

•

•

•

•

•

PUSH
SP-SP-2
(SP) - src
'AF 1_01 SP.

Block Transfer and Search Group
Flags
Instruction
CPD

Addressing Modes

5

Z

t

H PN N

C

t

•

Operation
Compare and Decrement
A - (HL)
HL- HL - 1
BC-BC - 1

•

t

CPDR

Compare, Decrement
and Repeat
Repeat until BC =0 or
match:
A - (HL)
HL - HL - 1
BC-BC - 1

t

CPI

•

t

Compare and Increment
A - (HL)
HL-HL + 1
BC-BC-1

t

CPIR

•

t

I

•II
c:I

Compare, Increment
and Repeat
Repeat until BC =0 or
match:
A - (HL)
HL - HL + 1
BC-BC-1

LDD

•

•

0

t

0

•

Load and Decrement
(DE)-(HL)
DE - DE - 1
HL-HL - 1
BC-BC-1

LDDR

•

•

0

0

0

•

Load, Decrement and
Repeat
Repeat until BC =0:
(DE) -(HL)
DE - DE - 1
HL - HL - 1
BC-BC - 1

LDI

•

•

0

0

•

Load and Increment
(DE) -(HL)
DE - DE + 1
HL - HL + 1
BC-BC - 1

LDIR

•

•

0

0

0

•

Load, Increment and
Repeat
Repeat until BC =0:
(DE) -(HL)
DE - DE + 1
HL - HL + 1
BC-BC-1

345
-~-----~-~-~"~

.-~----

a·Bit Arithmetic and Logic Group
Instruction

Addressing Modes

S

Z

Flags
H PN N

C

Operation

ADC [A,]src

src = R,RX,IM,IR,
DA,X,SX,RA,
SR,BX

t

t

v

t

Add With Carry (Byte)

src = R,RX,IM,IR,
DA,X,SX,RA,
SR,BX

t

src= R,RX,IM,IR,
DA,X,SX,RA,
SR,BX

t

src= R,RX,IM,IR,
DA,X,SX,RA,
SR,BX

t

ADD [A,]src

AND [A,]src

CP [A,]src

A-A

t

t

V

p

t

0

+

+

src

C

Add (Byte)

0

A-A
0

+

src

And
A -AAND src

t

t

Compare (Byte)

V

A- src

•

CPL [A]

0

•

•

•

Complement
Accumulator
A- NOTA

t

DAA[A]

t

p

•

Decimal Adjust
Accumulator
A - Decimal Adjust A

DEC dst

DIV [HL,]src

DIVU [H L,]src

dst = R,RX,IR,DA,X,
SX,RA,SR,BX

t

src = R,RX,IM,DA,X,
SX,RA,SR,BX

t

src = R,RX,IM,DA,X,
SX,RA,SR,BX

0

•

V

Decrement (Byte)
dst-dst - 1

t

•

•

•

Divide (Byte)
A-HL+src
L - remainder

•

t

•

•

Divide UnSigned (Byte)
A - HL+src
L - remainder

•

EXTS [A]

t

•

•

•

•

•

Extend Sign (Byte)
L-A
If A(7) = 0, then H - 00
else H - FF

INC dst

MULT [A,]src

MULTU [A,]src

NEG [A]

dst = R,RX,IR,DA,X,
SX,RA,SR,BX

t

src= R,RX,IM,IR,DA,
X,SX,RA,SR,BX

t

src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX

0

t

t

V

0

•

Increment (Byte)
dst-dst

t

•

0

•

1

Multiply (Byte)
HL-A x src

t

•

0

•

Multiply Unsigned (Byte)
HL -A x src

t

t

V

t

Negate Accumulator
A- -A

346

+

8·Bit Arithmetic and Logic Group (Continued)
Flags
Instruction

Addressing Modes

OR [A,]src

src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX

SBC [A,]src

src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX

S

Z

H PN
0

P

N

C

Operation

0

0

OR
A +- A OR src

v

* *

*

Subtract With Carry
(Byte)
A +- A - src - c

SUB [A,]src

XOR [A,]src

src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX

*

src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX

* *

V

0

P

*
0

Subtract
A +- A - src

I

Exclusive OR

0

A +- A XOR src

IIc:I

16·Bit Arithmetic Operations
Flags
Instruction

Addressing Modes

ADC dst,src

dst= HL
src = BC,DE,HL,SP
or
dst= IX
src = BC,DE,IX,SP
or
dst= IY
src = BC,DE,IY,SP

ADD dst,src

ADD dst,A

S

Z

H PN N

*

dst= HL
src= BC,DE,HL,SP
or
dst= IX
src= BC,DE,IX,SP
or
dst= IY
src = BC,DE,IY,SP

•

•

dst = HL,IX,IY

* *

*

V

Operation

C

Add With Carry (Word)

0

dst +- dst

•

CPW [H L,]src

DECW dst

src = RR*,IM,DA,X,RA

* *

V

*

V

•

•

src = RR*,IM,DA,X,RA

dst = RR*,IR,DA,X,RA

•

•

0

+

c

+

src

Add Accumulator to
Addressing Register

0

dst

ADDW [HL,]src

src

Add (Word)

0

dst +- dst

V

+

*

+-

dst

+

A

Add Word

HL +- HL

+

src

Compare (Word)
HL - src

•

•

Decrement (Word)
dst +- dst - 1

*In X addressing mode, (HL

+ nn) IS precluded

347
- - - - - - - - - - - - -..

~-~--------~---

16-Bit Arithmetic Operations (Continued)
Flags
Instruction

Addressing Modes

S

Z

H PN N

C

DEC(WJ dst

dst=RR

•

•

•

•

•

•

Operation
Decrement (Word)
dst-dst-1

DIVUW

src= RR,IM,DA,X,RA

•

0

•

[DEHL,]src

DIVW [DEHL,]src

•

Divide Unsigned (Word)
HL-DEHL+src
DE - remainder

src= RR,IM,DA,X,RA

•

•

*

•

Divide (Word)
HL - DEHL+src
DE - remainder

•

EXTS HL

•

•

•

•

•

Extend Sign (Word)
If H(7)=0, then DE - 0000
else DE - FFFF

INCWdst

dst = RR,IR,DA,X',RA

•

•

•

•

•

•

Increment (Word)
dst - dst

INC(WJ dst

dst=RR

•

•

•

•

•

•

src = RR,IM,DA,X,RA

0

*

•

0

•

1

Increment (Word)
dst - dst

MULTUW [HL,]src

+
+

1

Multiply Unsigned
(Word)
DEHL - HL x src

MULTW [HL,]src

src= RR,IM,DA,X,RA

* *

•

0

•

Multiply (Word)
DEHL - HL X src

NEG HL

SBC dst,src

*
dst= HL
src = BC,DE,HL,SP

* *

Negate HL

V

HL- -HL

Subtract With Carry
(Word)

V

or

dst - dst - src - C

dst=IX
src = BC,DE,IX,SP
or
dst=IY
src = BC,DE,IY,SP

SUBW [HL,]src

src = RR,IM,DA,X',RA

*lnXaddressingmode,(Hl + nn)Jsprecluded

348

* *

V

*

Subtract (Word)
HL - HL - src

Bit Manipulation, Rotate and Shift Group
Instruction

Addressing Modes

BIT b,dst

dst

RES b,dst

dst

=R,IR,SX
=R,IR,SX

S

•

•

Z

Flags
H PN N

C

Operation

•

•

Bit Test

*
•

0

Z ..... NOT dst(b)

•

•

•

•

Reset bit
dst(b) - 0

RL dst

dst

=R,IR,SX

*

0

p

0

Rotate Left
tmp -dst
dst(O) - C
C - dst(7)
dst(n + 1) - tmp(n) for
n 0 to 6

=

L&BJ

II

:I

dst

•

RLA

•

0

•

0

*

Rotate Left Accumulator
tmp-A
A(O)-C
C +- A(7)
A(n + 1) - tmp(n) for
n 0 to 6

=

L&BJ
A

RLC dst

dst

=R,IR,SX

0

*

p

0

Rotate Left Circular
tmp - dst
C - dst(7)
dst(O) - tmp(7)
dst(n + 1) - tmp(n) for
n 0 to 6

=

~J
dst

RLCA

•

•

0

•

0

I

Rotate Left Circular
(Accumulator)
tmp-A
C-A(7)
A(O) - tmp(7)
A(n + 1) - tmp(n) for
n 0 to 6

=

~J
A

349

Bit Manipulation, Rotate and Shift Group (Continued)
Instruction

Addressing Modes

RLD

S

Z

* *

Flags
H PN N

C

p

•

0

0

Operation
Rotate Left Digit
tmp(0:3) +- A(0:3)
A(0:3) +- src(4:7)
src(4:7) - src(0:3)
src(0:3) - tmp(0:3)

I, -I-

Lil ~

A

RR dst

dst = R,IR,SX

* *

0

p

0

*

,I

dst

Rotate Right
tmp -dst
dst(7) - C
C - dst(O)
dst(n) +- tmp(n
n = 0 to 6

+ 1) for

L~
dst

•

RRA

•

0

•

0

*

Rotate Right
(Accumulator)
tmp +- dst
A(7) - C
C - A(O)
A(n) - tmp(n
n = 0 to 6

+ 1) for

L~[i]J
A

RRC dst

dst= R,IR,SX

* *

0

p

0

Rotate Right Circular
tmp - dst
C - dst(O)
dst(7) - tmp(O)
dst(n) +- tmp(n
n = 0 to 6

+ 1) for

LBiE£J
dst

350

Bit Manipulation, Rotate and Shift Group (Continued)
Flags
Instruction

Addressing Modes

RRCA

S

Z

H

•

•

0

PN N

•

0

C

Operation

*

Rotate Right Circular
(Accumulator)
tmp +- A
C +- A(O)
A(7) +- tmp(O)
A(n) +- tmp(n
n 0 to 6

=

+

1) for

~
dst

RRD dst

dst

=IR

0

P

0

•

I

Rotate Right Digit
tmp(O:3) +- A(O:3)
A(O:3) +- src(O:3)
src(O:3) +- src(4:7)
src(4:7) +- tmp(O:3)

:I

•
CI

I' 'I'B ~'I
A

SET b,dst

dst

=R,IR,SX

•

•

•

•

•

•

Set Bit
dst(b)

SLAdst

dst

=R,IR,SX

*

t

0

p

0

t

dst

+-

1

Shift Left Arithmetic
tmp +- dst
C +- dst(7)
dst(O) +- 0
dst(n + 1) +- tmp(n) for
n 0 to 6

=

0~o
dst

SRAdst

dst

=R,IR,SX

t

0

p

0

t

Shift Right Arithmetic
tmp +- dst
C +- dst(O)
dst(7) +- tmp(7)
dst(n) +- tmp(n
n Oto 6

=

+

1) for

~
dst

351

Bit Manipulation, Rotate and Shift Group (Continued)
Flags
Instruction

Addressing Modes

S

Z

H PN N

C

Operation

SRL dst

dst = R,IR,SX

0

*

0

*

Shift Right Logical

P

0

tmp - dst
C - dst(O)
dst(7) - 0
dst(n) - tmp(n + 1) for
n = 0 to 6

o~
ds!

TSETdst

dst = R,IR,SX

*

•

•

•

•

•

Test and Set
s - dst(7)
dst - FF

Program Control Group
Flags
Instruction

Addressing Modes

S

Z

H PN N

C

Operation

CALL cC,dst

dst= IR,DA,RA

•

•

•

•

•

CALL

•

If cc is satisfied then:
SP-SP - 2
(SP) - PC
PC - dst
CALLdst

dst= IR,DA,RA

•

•

•

•

•

•

CALL
SP-SP - 2
(SP) - PC
PC - dst

•

CCF

DJNZ dst

dst=RA

•

•
•

t

•

•
•

0

•

*
•

Complement Carry Flag
C-NOTC
Decrement and Jump If
Non-Zero

8-8-1
If 8+0 then PC - dst
JAF dst

dst=RA

•

•

•

•

•

•

Jump on Auxiliary
Accumulator/Flag
If Auxiliary AF then:
PC -dst

JAR dst

dst= RA

•

•

•

•

•

•

Jump on Auxiliary
Register File In Use
If Auxiliary File then:
PC -dst

JP cC,dst

dst= IR,DA,RA

•

•

•

•

•

•

Jump
If cc is satisfied then:
PC - dst

352

Program Control Group (Continued)
Flags
Instruction

Addressing Modes

S

Z

H PN N

C

Operation

JP dst

dst= IR,DA,RA

•

•

•

•

Jump

•

•

PC-dst

JR cC,dst

dst= RA

•

•

•

•

•

•

Jump Relative
If cc * is satisfied then:
PC-PC + dst

JR dst

dst=RA

•

•

•

•

•

•

Jump Relative
PC-PC

•

RET

•

•

•

•

•

+

dst

I

Retum
PC-(SP)
SP-SP - 2

•

RETcc

•

•

•

•

•

IIa

Retum
If cc is satisfied then:
PC-(SP)
SP-SP + 2

RST dstt

dst= DA

•

•

•

•

•

•

Restart
SP-SP - 2
(SP) - PC
PC -dst

•

SC nn

•

•

•

•

•

System Call
SP-SP - 4
(SP) -PS
SP -SP - 2
(SP) - nn
PS - System Call
Program Status

•

SCF

•

0

•

Set Carry Flag

0

C-1

Input/Output Instruction Group
Flags

*
*

Instruction

Addressing Modes

IN dst,(C)

dst = R,RX,DA,X,RA,
SR,BX

INA,(n)

S

Z

H PN N

C

Operation

0

•

Input

P

0

dst - (C)

•

•

•

•

•

•

Input Accumulator
A- (n)

* Uses abbreviated set of condition codes.
t dst must be D. 8. 16. 24. 32. 40. or 56.
Programmable as prMl8Q8d.

*

353

Input/Output Instruction Group (Continued)
Flags
Instruction

t IN[WJ HL,(C)

Addressing Modes

S

Z

H PN N

C

Operation

•

•

• •

•

Input HL

•

HL - (C)

t IND

•

•

•

•

Input and Decrement
(Byte)
(HL) - (C)

8-8-1
HL - HL - 1

t INDW

•

•

•

•

Input and Decrement
(Word)

(HL) - (C)

8-8-1
HL - HL - 2

t IN DR

•

1

•

•

•

Input, Decrement and
Repeat (Byte)
Repeat until 8 = 0:
HL

+-

(C)

8-8-1
HL - HL - 1

t INDRW

•

•

•

•

Input, Decrement and

Repeat (Word)
Repeat until 8 = 0:
HL

+-

(C)

8-8-1
HL - HL - 2

t INI

•

*

•

•

•

Input and Increment
(Byte)
(HL)

+-

(C)

8-8-1
HL - HL

t INIW

•

*

•

•

•

+

1

Input and Increment
(Word)

(HL)

+-

(C)

8-8-1
HL - HL

t INIR

•

•

•

•

+

2

Input, Increment and
Repeat (Byte)
Repeat until 8 = 0:
(HL)-(C)
HL - HL + 1

8-8-1
t Programmable as privJleged.

354

Input/Output Instruction Group (Continued)
Flags
Instruction

t

Addressing Modes

S

Z

•

INIRW

H PN N

C

Operation

•

•

Input, Increment and
Repeat (Word)

•

Repeat until 8 = 0:
(HL) -(C)
HL- HL - 2
8-8-1

tOUT (C),src

tOUT (n),A

src= R,RX,DA,X,RA,
SR,8X

•

•

•

•

•

•

Output
(C) - src

•

•

•

•

•

•

Output Accumulator

I.

(n)-A

t OUT(W] (C),HL

•

•

•

•

•

•

II

Output HL
(C)- HL

t OUTD

•

•

•

•

CI

Output and Decrement
(Byte)
8-8-1
(C) - (HL)
HL - HL - 1

t OUTDW

•

t

•

•

•

Output and Decrement
(Word)
8-8-1
(C) - (HL)
HL - HL - 2

t OTDR

•

•

•

•

Output, Decrement and
Repeat (Byte)
Repeat until 8 = 0:
8-8-1
(C)-(HL)
HL - HL - 1

t OTDRW

•

•

•

•

Output, Decrement and
Repeat (Word)
Repeat until 8 = 0:
8-8-1
(C)-(HL)
HL- HL - 2

t OUTI

•

•

•

•

Output and Increment
(Byte)
8-8-1
(C) - (HL)
HL - HL + 1

t Programmable as privileged.

355

Input/Output Instruction Group (Continued)
Instruction

t

Addressing Modes

OTIW

S

Z

Flags
H PN N

C

Operation

•

t

•

•

Output and Increment
(Word)

•

8-8-1
(C) - (HL)
HL - HL + 2

t

•

•

OTIR

•

•

Output, Increment and
Repeat (Byte)
Repeat until 8 = 0:
8-8-1
(C) - (HL)
HL - HL + 1

t

•

OUTIRW

•

•

•

Output, Increment and
Repeat (Word)
Repeat until 8 = 0:
8-8-1
(C) - (HL)
HL - HL + 2

t

t

TSTI (C)

0

P

0

•

Test Input
F - test (C)

CPU Control Group
Instruction

* DI mask

* EI mask

Addressing Modes

S

Z

Flags
H PN N

C

Operation

mask = Hex value between
o and 7F

•

•

•

•

•

Disable Interrupt

mask = Hex value between
o and 7F

•

If mask(i) = 1 then:
MSR(i) - 0;
If no mask then:
MSR O _ 6 - 0

•

•

•

•

•

Enable Interrupt
If mask(i) = 1 then:
MSR(i) - 1;
If no mask then:
MSRO _ 6 - 1

•

* HALT

•

•

•

•

•

•

Halt
CPU Halts

* 1M P

p=0,1,2,3

•

•

•

•

•

•

Interrupt Mode Select
Interrupt Mode - p

* LO dst,src

dst=A
src= I,R

0

0

•

Load Accumulator from
I or R Register
A - src

t Programmable as privileged.
• Privileged Instruction.

356

CPU Control Group (Continued)
Flags
Instruction
* LD dst,src

Addressing Modes

S

Z

H PN

N

C

Operation

dst=I,R
src=A

•

•

• •

•

•

Load I or R Register
from Accumulator
dst - A

* LDCTL dst,src

dst = (C), USP
src= HL,IX,IY
or
dst= HL,IX,IY
src = (C),USP

•

PCACHE

•

•

•

•

Load Control
dst - src

•
•

NOP

•

•

•

•

•

•
•

•
•

•
•

No Operation

a

Purge Cache

8

All cache entries
invalidated

•

* RETI

•

•

•

•

•

Return from Interrupt

IIc:I

PC-(SP)
SP-SP + 2

•

* RETIL

•

•

•

•

•

Return from Interrupt
Long
PS -(SP)
SP-SP + 4

•

* RETN

•

•

•

•

•

Return from
Nonmaskable Interrupt
PC -(SP)
SP-SP + 2
MSR(O-7) -IFF(O-7)

Extended Instruction Group1
Flags
Instruction

Addressing Modes

S

Z

H PN

N

C

Operation

EPUM src

src = IR,DA,X,RA,SR,BX

•

•

•

•

•

Load EPU from Memory

•

EPU ..... template
EPU - src

MEPU dst

dst = IR,DA,X,RA,SR,BX

•

•

•

•

•

•

Load Memory from EPU
EPU - template
dst - EPU

EPUF

0

*

P

0

•

Load Accumulator
from EPU
EPU - template
A-EPU

EPUI

•

•

•

•

•

•

EPU Internal Operation
EPU - template

1 Refer

to the Z8070 Z8000™ Floating-Point Product Specification (document number 00-2235-01) for the floating-point
extended instructions .

.. Privileged Instruction.

357
---~.------

-

EXTENDED PROCESSING
ARCHITECTURE
Features
The Zilog Extended Processing Architecture (EPA) provides an extremely flexible and modular approach to expanding both the hardware and software capabilities of
the Z800 CPU. Features of the EPA include:
•
•

Allows Z800 CPU instruction set to be extended by
external devices.
Increases throughput of the system by using up to
four specialized external processors in parallel with
the CPU.

•

Used by Z8070 floating-point EPU.

•

Permits modular
systems.

•

Provides
easy
management
of
multiple
microprocessor configurations via "single instruction stream" communication.

•

Simple interconnection between EPUs and Z800
MPU requires no additional external supporting
logiC.

•

Supports debugging of suspect hardware against
proven software.

•

EPUs can be added as the system grows and as
EPUs with specialized functions are developed.

design

of

Z800

CPU-based

General Description
The processing power of the Zilog Z-BUS Z800
microprocessor can be boosted beyond its intrinsic
capability by the Extended Processing Architecture
(EPA). The EPA allows the Z800 CPU to accommodate
up to four Extended Processing Units (EPUs), which perform specialized functions in parallel with the CPU's
main instruction execution stream.
The EPUs connect directly to the Z-BUS and continuously monitor the CPU instruction stream for an instruction
intended for the EPU (template). When a template is
detected, the appropriate EPU responds, obtaining or
placing data or status information on the Z-BUS by using
the Z800 CPU-generated control signals and performing
its function as directed.
The CPU is responsible for instructing the EPU and
delivering operands and data to it. The EPU recognizes
templates intended for it and executes them, using data
supplied with the template and/or data within its internal
registers. There are three classes of EPU instructions:
•

Data transfers between main memory and EPU
registers

•

Data transfers between CPU registers and EPU
status registers

•

EPU internal operations

358

Six addressing modes can be utilized with transfers between EPU registers and the CPU and main memory:

•

•

•
•

•
•

Direct Address
Indirect Register
Indexed
Stack Pointer Relative
Relative
Base Index

In addition to the hardware-implemented capabilities of
the EPA, there is an extended instruction trap
mechanism to permit software simulation of EPU functions. An EPU present bit in the Z800 MPU Trap Control
register indicates whether actual EPUs are present or
not. If not, when the CPU traps when an extended instruction is detected, a software "trap handler" can
emulate the desired EPU function. Thus, the EPA software trap routine supports systems not containing an
EPU.
EPA and CPU instruction execution are shown in Figure
17. The CPU begins operation by fetching an instruction
and determining whether or not it is an EPU instruction.
If the instruction is an EPU instruction, the state of the
EPU Enable bit in the Trap Control register is examined.
If the EPU Enable bit is reset (E
0), the CPU generates
a trap and the EPU instruction can be simulated by an
EPU instruction trap software routine. However, if the
EPU Enable bit is set (E = 1), indicating that an EPU is
present in the system, then the 4-byte EPU template is
fetched from memory. The fetching of the EPU template
is indicated by the status lines STo-ST3' The EPU meanwhile continuously monitors the Z-BUS and the status
lines for its own templates. After fetching the EPU
template, the CPU, if necessary, transfers appropriate
data between the CPU and memory or between the CPU
and the EPU. These transactions are indicated by unique
encodings of the status lines. If the EPU is free when the
template and the data appear, the EPU template is executed. If the EPU is still processing a previous instruction, it activates the PAUSE line (Z8216 only) to halt further execution of CPU instructions until execution is
complete. After the execution of the template is complete, the EPU deactivates the PAUSE line and CPU instruction execution continues.

=

r----------I
I

NO

Figure 17. EPA and Z8218 CPU Instruction Execution

MEMORY MANAGEMENT
Features
•

On·chip dynamic address translation

•

Permits addressing of large physical memory
o

512K bytes-40-pin devices

o

16M bytes-64-pin devices

•

Separate translation facilities for user and system
modes

•

Permits instructions and data to reside in separate
memory areas.

•

Write protection for individual pages of memory

•

Aborts CPU on access violation to support virtual
memory

General Description
The Z800 microprocessor contains an on-chip Memory
Management Unit (MMU), which translates logical addresses into physical addresses. This allows access to
more than 64K bytes of physical memory and provides
memory protection features typical of those found on
large systems. With the MMU, the CPU can access up to
16M bytes of physical memory, depending on package
size (the 40-pin package devices output only 19 address
bits). The MMU features a sophisticated trapping
mechanism that generates page faults on error condi-

2259-017

tions. Instructions that are aborted by a page fault can
be restarted In a manner compatible with virtual memory
system requirements. On reset, the MMU features are
not enabled, thus permitting logical addresses to pass to
the physical memory untranslated.
The physical address space is expanded by dividing the
64K byte logical address space (the space manipulated
by the program) into pages. The pages are then mapped
(translated) into the larger physical address space of the
Z800 microprocessor. The mapping process makes the
user software addresses independent of the physical
memory, so the user is freed from specifying where information is actually stored in physical memory. The actual size of the page depends on whether the program/data separation mode is enabled-if it is enabled,
each page is 8K bytes in length, and if it is not enabled,
the page length is 4K bytes. With the page mapping
technique, 16-bit logical addresses can be translated into 24-bit physical addresses (only the lower 19 bits are
externally available on 40-pin devices). Address translation can occur both in system and in user mode, with
separate translation facilities available to each mode.
The MMU further allows instruction references to be
separated from data references, which enables programs of up to 64K bytes in length to manipulate up to
64K bytes of data without operating system intervention.

359

MMU Architecture
The Z800 MMU consists of two sets of sixteen page
descriptor registers (Figure 18) that are used to translate
addresses, a 16-bit control register that governs the
translation facilities, a Page Descriptor Register Pointer,
an 1/0 write-only port that can be used to invalidate sets
of page descriptors, and two 1/0 ports for accesses to
the page descriptor registers. One set of page descriptor
registers is dedicated to the system mode of operation
and the other set is dedicated to the user mode of operation.
While an address is being translated, attributes
associated with the logical page containing that location
are checked. The correct logical page is determined by
the CPU mode (user or system), address space (program/data), and the four most significant bits of the
logical address. Pages can be write-protected to prevent
them from being modified by the executing task and can
also be marked as non-cacheable to prevent information
from being copied into the cache for later reference. The
latter capability is useful in multiprocessor systems, to
ensure that the processor always accesses the most
current version of information being shared among multiple devices. The MMU also maintains a bit for each page
that indicates if the page has been modified.
Each page descriptor register contains a Valid bit, which
indicates that the descriptor contains valid information.
Any attempt by the MMU to translate an address using
an invalid descriptor generates a page fault. Valid bits for
groups of page descriptor registers can be reset by
writing to an MMU control port.
15

Figure 18_ Page Descriptor Register

For each mode of CPU operation, the MMU can be configured to separate instruction fetches from data
fetches, and thus separate the program address space
from the data address space. When the programldata
separation mode is in effect, the sixteen page descriptor
registers for the current CPU mode of operation (user or
system) are partitioned into two sets, one for instruction
fetches and one for data fetches. A instruction fetch or
data access using the Program Counter Relative addressing mode is translated by the MMU registers
associated with the program address space; data accesses using other addressing modes and accesses to
the Interrupt Vector Table in interrupt mode 2 use the
MMU registers associated with the data address space.
In this mode of MMU operation, the page size is 8192
bytes. There are two control bits in the MMU Master
Control register that independently specify whether the
user and system modes of CPU operation have separate
program and data address spaces.

360

Each 16-bit page descriptor register consists of a 4-bit
attribute field and a 12-bit page frame address field. The
attribute field consists of the least Significant bits of the
descriptor and contains four control and status bits,
listed below.
Modified (M). This bit is automatically set whenever a
write is successfully performed to a logical address in
this page; it can be cleared to 0 only by a software
routine that loads the descriptor register. If the Valid bit
is 0, the contents of this bit are undefined.
Cacheable (C). While this bit is set to 1, information
fetched from this page can be placed in the cache. While
this bit is cleared to 0, the cache control mechanism is
inhibited from retaining a copy of the information.
Write-Protect (WP). While this bit is set to 1, CPU writes
to logical addresses in this page cause a page fault to be
generated and prevent a write operation from occurring.
While this bit is cleared to 0, all valid accesses are permitted.

Valid (V). While this bit is set to 1, the descriptor contains
valid information. While this bit is cleared to 0, all CPU
accesses to logical addresses in this page cause a page
fault to be generated.
MMU Control Registers and 1/0 Ports
MMU operation is controlled by one control register and
four dedicated 1/0 ports. The MMU Master Control
register (Figure 19) determines the programldata address space separation in effect in both user and system
modes and whether logical addresses generated in user
and system mode will be translated by the MMU. Page
descriptor registers are accessed indirectly through the
register address contained in the Page Descriptor
Register Pointer. The descriptor select port is used to access the page descriptor register that is pointed to by the
Page Descriptor Register Pointer. After this access the
Page Descriptor Register Pointer is left unchanged. The
block move 1/0 port is used to move blocks of words between the page descriptor registers and memory; reads
or writes to this 1/0 port access data pointed to by the
Page Descriptor Register Pointer, then increment the
pOinter by one. The Invalidation 1/0 Port is used to invalidate blocks of page descriptor registers; writes to
this port cause the Valid bits in selected blocks of page
descriptor registers to be cleared to 0, which indicates
that the descriptors no longer contain valid information.
15

Figure 19. MMU Master Control Register

MMU Master Control Register. The MMU Master Control register controls the operation of the MMU. This
register contains four control bits; all other bits in this

2259-018, 019

register must be cleared to O. The four control bits of the
MMU Master Control register are described below.

Page Fault Identifier (PFI). This 5-bit field latches information that indicates which page descriptor register was
being accessed when the access violation was
detected.

System Mode Program/Data Separation Enable (SPD).
While this bit is set to 1, instruction fetches and data accesses via the PC Relative addressing mode use the
system mode page descriptor registers 8-15, and data
references that do not use the PC Relative addressing
mode use the system mode page descriptor registers
0-7. While this bit is cleared to 0, system mode page
descriptor registers 0-15 are used to translate instruction and data references.

System Mode Translate Enable (STE). While this bit is set
to 1, logical addresses generated In the system mode of
operation are translated. While this bit is cleared to 0,
addresses are passed through the MMU extended with
zeros in the most significant bits and no attribute checking or modified bit setting is performed.

User Mode Program/Data Space Separation Enable
(UPD). While this bit is set to 1, Instruction fetches and
data accesses via the PC Relative addressing mode use
user mode page descriptor registers 8-15, and data
references that do not use the PC Relative addressing
mode use user mode page descriptor registers 0-7.
While this bit is cleared to 0, user mode page descriptor
registers 0-15 are used to translate instruction and data
references.

Block Move I/O Port. Block moves of data into and out
of the page descriptor registers are accomplished by
writing and reading words to or from this dedicated 110
port at location FFxxF4. Any word 110 instruction can be
used to access page descriptor registers via this port,
provided that the Page Descriptor Register Pointer is
properly initialized.

Invalidation I/O Port. Valid bits can be cleared (I.e., the
page descriptor registers invalidated) by writing to this
dedicated 8-bit port (Table 3). Individual Valid bits can
subsequently be set by software writing to the page
descriptor registers. Reading this 110 port returns unpredictable data.

Table 3. Invalidation Port Table
Encoding

Reglste,. Invalid
System Page Descriptor Registers 0-7
System Page Descriptor Registers 8-15
System Page Descriptor Registers 0-15
User Page Descriptor Registers 0-7
User Page Descriptor Registers 8-15
User Page Descriptor Registers 8·15
User Page Descriptor Registers 0·15

Translation Mechanism
Address Translation. Address translation is illustrated
In Figure 20. While the ProgramlData Space Separation

Page Descriptor Register Pointer. Moves of data into

bit is cleared to 0, the 16-bit logical address is divided into two fields, a 4-blt index field used to select one of 16
page descriptor registers, and a 12-bit offset field that
forms the lower 12 bits of the physical address. The
physical address is composed of the 12-bit page frame
address supplied by the selected page descriptor
register and the 12-bit offset supplied by the logical address.

and out of the MMU page descriptor registers use the
p~ge Descriptor Register Pointer. This 8-bit register contains the address of one of the page descriptor registers.
When a word 110 instruction accesses 110 address
FFxxF5 (descriptor select port), this register is used to
access a page descriptor register. When a word 110 instruction accesses 110 address FFxxF4 (block move 110
port), this register is also used to access a page descriptor register, but after the access, this register Is
automatically incremented by one.

While the ProgramlData Space Separation bit is set to 1,
the logical address is divided into a 3-bit index field and a
13-bit offset field. The page descriptor register consists
of an 11-bit Page Frame Address field. The phYSical address is a result of concatenating the page frame address and the logical offset. The page descriptor register
is chosen by a 4-bit index field, which consists of a Program/Data Address bit from the CPU and the three Index
bits from the logical address.

User Mode Translated Enable (UTE). While this bit is set
to 1, logical addresses generated in the user mode of
operation are translated. While this bit is cleared to 0,
addresses are passed through the MMU extended with
zeros in the most significant bits and no attribute checking or modified bit setting is performed.

Descriptor Select Port. Moves of one word of data into
and out of a page descriptor register are accomplished
by writing and reading words to or from this dedicated
110 port at location FFxxF5. Any word 110 instruction can
be used to access a page descriptor register via this
port, provided that the Page Descriptor Register Pointer
IS properly initialized.

361

15

I

L:

INDEX

I

}

I

OFFSET

LOGICAL
ADDRESS

I
4 3

D

15

15

.!

PAGE FRAME
ADDRESS

PAGI! DI!SCRIPTOR
REGISTERS

ATTRIBUTE

".....--USI!R

1#'/ ".....--SYSTEM

,

D
D

I

J

23

I

D
OFFSET

PAGE FRAME ADDRESS

I

}

PHYSICAL
ADDRI!SS

Figure 20_ Address Translation

ON·CHIP MEMORY
Features

•

Configurable as high-speed cache

the system or used as a cache for instructions or data.
Its mode of use (dedicated memory or a cache) is programmable; on reset it is automatically enabled for use
as a cache for instructions only.

•

Programmable to cache instructions, data or both

On·Chip Memory Architecture

•

Permits faster execution by minimizing external bus
accesses

The on-chip memory is organized as 16 lines of 16 bytes
each. Each line can hold a copy of 16 consecutive bytes
in physical memory locations whose 20 most significant
bits of physical address are identical. Each byte in the
cache has an associated Valid bit that indicates whether
the cache holds a valid copy of the memory contents at
the associated physical memory location. Figure 21 illustrates the cache organization.

•

256-byte local memory

•

Operation is transparent to user

•

Configurable as local RAM with user-definable addresses

zaoo

The
MPU has 256 bytes of on-chip memory, which
can be dedicated to memory locations programmed by

20 BITS

18 x 8 BITS

18 BITS

~,

.....

LINED

TAG 0

VALID
BITS

LINE 1

TAG 1

VALID
BITS

CACHE DATA

LINE 2

TAG 2

VALID
BITS

CACHE DATA

•
•
•

•
•
•

•
•
•

LINE 15

TAG 15

VALID
BITS

CACHE DATA

,

•
•

•
CACHE DATA

Tag n • thl 20 Address bite a••oclated with line n
Valid bill. 18 bits that Indicate which byte. In the cacha contain valid data
Cacha data

=- 18 byt••

Figure 21. Cache Organization

362

22158-020, 021

The on-chip memory has two modes of operation. If the
Memory/Cache bit in the Cache Control register is set to
1, then the 256 bytes of on-chip memory are treated as
physical memory locations. Memory accesses to addresses covered by the on-chip memory do not generate
bus transactions on the external bus and hence the accesses are faster. In this mode, the valid bits are ignored.
If the Memory/Cache bit is cleared to 0, then the 256
bytes of on-chip memory are treated as a cache
memory. The lines are allocated using a least-recently
used (LRU) algorithm. When a cache "miss" on a read
occurs (and the MMU does not assert cache inhibit), the
line in the cache that has been least recently accessed
is selected to hold the newly read data. All bytes in the
selected line are marked invalid except for the bytes
containing the newly accessed data. On a cache miss,
one or two bytes, depending on the bus size, are fetched
from main memory. Except for burst mode instruction
fetches, the cache does not pre-fetch beyond the
currently-requested address. A cache miss on a data
write does not cause a line to be allocated to the
memory location accessed.

write is to a valid location in the cache but the LRU
mechanism is unaffected. Also, for the EPU to memory
transfer, if the cache contains valid locations that are updated by an EPU transaction, the on-chip cache is also
updated.

Cache Control Register. The operation of the on-chip
memory is controlled by an a-bit Cache Control register
(Figure 22) that is accessed using a load control instruction. This register contains five control bits; all other bits
must be cleared to O.
7

0

IMIC! I ! 0 !LMaEa! 0 ! 0 ! 0 I
Figure 22. Cache Control Register

I

The bits in this register are:
High Memory Burst Capability (HMB). This 1-bit field
specifies whether a memory burst transaction occurs
when the MMU is enabled and there is a 1 in bit 15 of the
selected page descriptor register (0
burst mode not
supported, 1
burst mode supported).

=

=

The cache can hold both instructions and data. Two control bits in the Cache Control register can be separately
set to enable the cache to hold instructions and to hold
data. If the cache contains data, writes to data at locations contained in the cache also cause external bus
transactions to update the appropriate memory location.

Low Memory Burst Capability (LMB). This 1-bit field
specifies whether a memory burst transaction occurs
when the MMU is disabled or when the MMU is enabled
and there is a zero in bit 15 of the selected page descriptor register (0 = burst mode not supported, 1 = burst
mode supported).

Both the CPU and the on-chip DMAs access the cache.
For the CPU, if the MMU is enabled, the access can be
either cacheable or non-cacheable, depending on the
value of the Cacheable bit in the page descriptor register
used to translate the logical address. If the MMU is not
enabled, all memory transactions are considered to be
cacheable. Two bits in the Cache Control register, the
Cache Instructions Disable bit and the Cache Data
Disable bit, further determine the operation of the cache
for various situations. These bits enable the cache for instructions and for data.

Cache Data Disable (D). While this bit is cleared to 0,
data fetches are copied into the cache if the M/C bit = 0
(cache mode). If M/C
1, the state of this bit is ignored.

When the on-chip memory is used as fixed memory locations, neither the Cache Instruction Disable or Cache
Data Disable bits are used, and no distinction is made as
to whether the CPU is accessing data or instructions.
In general, when devices such as on-chip DMAs transfer
data to the memory, the cache data is modified if the

=

Cache Instructions Disable (I). While this bit is cleared to
0, instruction fetches are copied into the cache when the
M/C bit = 0 (cache mode). When M/C = 1, the state of
this bit is ignored.
Memory/Cache (M/C). While this bit is set to 1, the onchip memory is to be accessed as physical memory;
while it is cleared to 0, the memory is accessed
associatively as a cache.

If the on-chip memory is to be used as fixed memory
locations, the user can programmably select the ranges
of memory addresses for which the on-chip memory
responds.

CLOCK OSCILLATOR
The zaoo MPU has an on-Chip clock oscillatorlgenerator
that can be connected to a crystal or any suitable clock
source. The bus timing clock generated from the on-chip

2259-022

oscillator is output for use by the rest of the system. The
frequency of the processor clock is one-half that of the
fundamental frequency of the crystal.

363

0

:I
~

REFRESH
The l800 MPU has an internal mechanism for refreshing
dynamic memory. This mechanism can be activated by
setting the Refresh Enable bit in the Refresh Rate
register to 1. Memory refresh is performed periodically
at a rate specified by the Refresh Rate register. Refresh
transactions are identical to memory transactions except that different status signals are used and no data is
transferred. They can be inserted immediately after the
last clock cycle of any bus transaction, including an internal operation.

A 10-bit refresh address is generated for each refresh
operation with the refresh address being incremented by
two between refreshes for 16-bit bus versions, and by
one for 8-bit bus versions.

While the Refresh Enable bit is set to 1, the value of the
6·bit Rate field in the Refresh Rate register determines
the time between successive refreshes (the refresh
0, the refresh period is 256 properiod). When Rate
cessor clock cycles; when Rate
n (n > 0) the refresh
period is 4n. The Rate and Refresh Enable control bits
are programmed via an I/O instruction.

enables the refresh mechanism and specifies the fre·
quency of refresh transactions.

=

On reset, refresh is enabled, the rate is 32 processor
clock cycles, and the refresh address is not affected.
The Refresh mechanism is controlled by an 8-bit control
register, described below.

Refresh Rate Register. This 8-bit register (Figure 23)

=

The refresh transaction is generated as soon as possible
after the refresh period has elapsed (generally after the
last clock cycle of the current bus transaction). If the
CPU receives an interrupt request, the refresh operation
is performed first. When the l800 CPU does not have
control of the bus or is in the wait state, internal circuitry
records the number of refresh periods that have elapsed
and refresh cycles cannot be generated. When the CPU
regains control of the bus or the Wait input signal is
deactivated and the bus transaction completes, the
refresh mechanism immediately issues the skipped
refresh cycles. The internal circuitry can record up to
256 such skipped refresh operations.

Figure 23. Refresh Rate Register

The fields in this register are:
Refresh (Rate). This field indicates in processor clock

cycles the rate at which refresh transactions are to be
generated; a value of n in this field indicates a refresh
period of 4n, with Rate
0 indicating 256 clock cycles.

=

Refresh Enab/e (E). When this 1·bit field is set to 1, the

refresh mechanism is enabled.

UART
The l800 UART transmits and receives serial data using
any common asynchronous data-communication pro·
tocol.
Transmission and reception can be performed independently with five, six, seven, or eight bits per
character, plus optional even or odd parity. The transmitter can supply one or two stop bits and can provide a
break output at any time. Reception is protected from
spikes by a "transient spike-rejection" mechanism that
checks the signal one-half a bit time after a Low level is
detected on the receiver data input; if the Low does not
persist-as in the case of a transient-the character
assembly process is not started. Framing errors and
overruns are detected and buffered with the partial
character on which they occur. Furthermore, a built-in
checking process avoids interpreting a framing error as
a new start bit: a framing error results in the addition of
one-half a bit time to the point at which the search for the
next start bit is begun.
The UART uses the same clock frequency for both the
transmitter and the receiver. The input for the UART
clocking circuitry is derived from counter/timer 0, either

364

from its external input line for an external clock or from
the counter/timer output for a bit rate generated from the
internal processor clock. The UART input clock is further
scaled by 1, 16, 32, or 64 for clocking the transmitter and
receiver.
Two of the DMA channels can be used independently to
move characters between memory and the transmitter
or receiver without CPU intervention. Both the transmitter and receiver can interrupt the CPU for processor
assistance.
The UART uses two external pins, Transmit and Receive.
Data that is to be transmitted is placed serially on the
Transmit pin and data that is to be received is read in
from the Receive pin.

Asynchronous Transmission
The Transmitter Data Output line is held marking (High)
when the transmitter has no data to send. Under program control, the Send Break command can be issued to
hold the Data Output line Low (spacing) until the com·
mand is cleared.

2259-023

The UART automatically adds the start bit, the programmed parity bit (odd, even, or no parity), and the programmed number of stop bits to the data character to be
transmitted. When the character is five, six, or seven
bits, the unused most significant bits in the Transmitter
Data register are automatically Ignored by the UART.
Serial data is shifted from the transmitter at a rate equal
to 1, 1/16th, 1/32nd or 1/64th of the clock rate supplied to
the transmitter clock Input (as determined by the clock
scale field in the UART Configuration register). Serial
data is shifted out on the falling edge of the clock input.

Asynchronous Reception
An asynchronous receive operation begins when the
Receive Enable bit in the Receiver Control/Status
register is set to 1. A Low (spaCing) condition on the
Receive input line indicates a start bit. If this Low persists for at least one-half of a bit time, the start bit is
assumed to be valid and the data input is then sampled
at mid-bit time until the entire character is assembled.
This method of detecting a start bit improves error rejection when noise spikes exist on an otherwise marking
line. If the X 1 clock mode is selected, bit synchronization must be accomplished externally; received data is
sampled on the rising edge of the clock.
A received character can be read from the 8-bit Receiver
Data register. The receiver Inserts 1s when a character
length of other than eight bits is used. If parity is enabled,
the parity bit is not stripped from the assembled
character for character lengths other than eight bits. For
lengths other than eight bits, the receiver assembles a
character length of the required number of data bits,
plus a parity bit and 1s for any unused bits.
Since the receiver is buffered by one 8·bit register in addition to the receiver shift register, the CPU has enough
time to service an interrupt and to accept the data
character assembled by the UART. The receiver also
has a buffer that stores error flags for each data
character in the receive buffer. These error flags are
loaded at the same time as the data character.
After a character is received, it is checked for the following error conditions:
•

Parity Error: when the parity bit of the character
does not match the programmed parity.

•

Framing Error: if the character is assembled without
any stop bits (i.e., a Low level is detected for a stop
bit).

•

Receiver Overrun Error: if the CPU fails to read a
data character when more than one character has
been received.

The Parity Error, Framing Error, and Receiver Overrun
Error cause an interrupt request if the interrupt request
capability is enabled. Since the Parity Error and Receiver
Overrun Error flags are latched, the error status that is

read reflects an error in the current character in the
Receiver Data register plus any Parity or Overrun Errors
detected since the last write to the Receiver Control/Status register. To keep correspondence between
the state of the error buffers and the contents of the
receiver data buffers, the Receiver Control/Status
register must be read before the data.

Polled Operation
In a polled environment, the Receive Character
Available bit in the Receiver Control/Status register must
be monitored so the CPU can know when to read a
character. This bit is automatically cleared when the
Receiver Data register is read. To prevent overwriting
data in polled operations, the transmitter buffer status
must be checked before writing into the transmitter. The
Transmit Buffer Empty bit in the Transmitter Control/Status register is set to 1 whenever the transmit buffer is empty.

UART Control and Status Registers
The UART operation is controlled by three control and
status registers. The UART configuration register
specifies the character size and parity, the clock source
and scaling and loop-back enable. Both the transmitter
and the receiver have their own control/status register.

UART Configuration RegIster. This 8-bit register
(Figure 24) contains control information for both the
transmitter and receiver.

I

B/e

I p IEIOlcsl

Figure 24. UART Configuration Register
The control fields for this register are:
Loop Back Enable (LB). The UART is capable of local
loopback. In this mode the internal transmit data line is
tied to the internal receiver line and the external receiver
input is ignored. If this bit is set to 1, loop mode is enabled.
Clock Rate (CR). These two bits specify the multiplier
between the clock and data rates (00
data rate X 1,
01 = data rate X 16, 10 = data rate X 32, 11 = data
rate X 64). The same rate is used for both the receiver
and transmitter. If the X 1 clock rate is selected, bit synchronization must be accomplished externally.

=

Clock Select (CS). This bit specifies the clock input for
the UART. If the bit is set to 1, the counter/tlmer 0 output
pulse is used for bit-rate generation; if the bit is cleared
to 0, the input line to counter/timer 0 provides the clock
from an external source.
Parity Even/Odd (E/O). If parity is specified, this bit determines whether it is sent and checked as even or odd (1
= even).

365

Parity (P). If this bit is set to 1, an additional bit position
(in addition to those specified in the bits/character control field) is added to transmitted data and is expected in
received data. In the Receiver, the parity bit received is
transferred to the CPU as a part of the character, unless
eight bits/character is selected.
Bits/Character (B/C). Together, these two bits determine
the number of bits to form a character. If these bits are
changed during the time that a character is being
assembled, the results are unpredictable (00
5
6 bits/character, 10
7 bits/
bits/character, 01
character, 11
a bits/character).

=

=

=

=

Transmitter Interrupt Enable (IE). When this bit is set to
1, interrupt requests are generated whenever the
transmitter buffer becomes empty; when this bit is
cleared to 0, no requests are made.
Transmitter Enable (EN). While this bit is cleared to 0,
data is not transmitted and the transmitter output is held
marking. Data characters in the process of being
transmitted are completely sent if this bit is cleared to 0
after transmission has started.

Receiver Control/Status Register. This a-bit register
(Figure 26) specifies the operation of the receiver. The
control bits are described below.

Transmitter Control/Status Register. This a-bit
register (Figure 25) specifies the operation of the
transmitter.
7

IEN liE I

0

0

ISB FRKIFRCIVALI BE I

Figure 25. Transmitter ControllStatus Register

The control bits for this register are:
Transmitter Buffer Empty (BE). This bit is automatically
set to 1 whenever the transmitter buffer becomes empty,
and cleared to 0 when a character is loaded into the
transmit buffer. This bit is in the set condition after a
reset. This bit is controlled by the UART control circuitry,
it can be read by an I/O read but cannot be set to 1 or
cleared to 0 by an I/O write.
Value (VAL). This bit determines the value of the bits
transmitted while the FRC bit is 1 and dummy characters
are loaded into the transmitter buffer. When this bit is 1,
a mark character (all 1s) is sent; when this bit is 0, a
break character (all as) is sent.
Force Character (FRC). When this bit is set to 1, any
character loaded into the transmitter buffer causes the
transmitter output to be held High or Low (as indicated
by the VAL bit) for the length of time required to transmit
a char)cter; the character itself is not sent until after the
current character is transmitted. This allows a program
to generate a marking signal or a break of multiplecharacter duration simply by setting this bit to 1, setting
the VAL bit to 1 or 0, and loading the appropriate number
of dummy characters into the transmitter buffer.
Send Break (BRK). When set to 1, this bit immediately
forces the transmitter output to the spacing condition,
regardless of any data being transmitted. When this bit is
cleared to 0, the transmitter returns to marking.
Stop Bits (SB). This bit determines the number of stop
bits added to each asynchronous character sent. The
receiver always checks for one stop bit. If this bit is set
to 1, two stop bits are automatically appended to the
character (and parity) sent; if this bit is cleared to 0, only
one stop bit is appended.

366

7

0

IE+E I 0 ICA IOVEI PE IFE IERRI
Figure 28. Recelvar ControllStatus Register

Receiver Error (ERR). This bit is the logical OR of the PE,
OVE, and FE bits.
Framing Error (FE). This bit is automatically set to 1 for
the received character In which the framing error occurred. Detection of a framing error adds an additional onehalf of a bit time to the character time so the framing error is not interpreted as a new start bit. The bit is latched,
so once an error occurs it remains set until the bit is
cleared by software writing to this register.
Parity Error (PE). When parity is enabled, this bit is
automatically set to 1 for those characters whose parity
does not match the programmed sense (even/odd). This
bit is latched, so once an error occurs, it remains set until it is cleared by software writing to this register.
Receiver Overrun Error (OVE). This bit is automatically
set to 1 to indicate that more than two characters have
been received without a read from the CPU (or DMA).
Only the most recently received character is flagged
with this error, but when this character is read, the error
condition is latched until cleared by software writing to
this register.
Receiver Character Available (CA). This bit is
automatically set to 1 when at least one character is
available in the receive buffer; it is automatically cleared
to 0 when the Receiver Data register is read. This bit is
controlled by the UART control circuitry; it can be read
by an I/O read but cannot be set or cleared by an I/O
write.
Receiver Interrupt Enable (IE). While this bit Is set to 1,
interrupt requests are generated whenever the receiver
detects an error or the receiver has a character
available.
Receiver Enable (EN). When this bit is set to 1, receiver
operations begin. This bit should be set only after the
parameters in the UART Configuration register are set.

2259-025, 028

UART Bootstrapping Option

DMA Master Control register-DOR and EOP set

The 2800 CPU supports an automatic initialization of
memory via the UART after a reset operation. This
system bootstrapping capability permits ROM less
system configurations: the memory can be initialized by
a serial link before the 2800 CPU fetches information
from memory after the reset.

Count register-0100 (256 bytes to be transferred)

On the rising edge of reset, the AD lines are sensed; if
AD6 is being driven High, the 2800 CPU automatically
enters a Halt state. The UART is also automatically initialized to receive 8-bit character data with odd parity at
a x 16 clock rate. An external clock source is assumed.
A minimum of 15 processor clock cycles must elapse
before the transmission can begin.

Characters received are placed in memory starting at
physical memory location zero. If an error occurs, the
2800 CPU drives the Transmitter Output line Low. External circuitry monitoring this line can use this signal to
cause the transmitting device to begin the initialization
procedure again, starting with a reset and AD6 asserted
on the rising edge of RESET.

During the bootstrapping operation, DMA Channel 0 is
used to transfer received characters into the memory.
This channel is initialized as follows:

After 256 bytes of data have been transferred, the 2800
CPU automatically begins execution by fetching the first
instruction from memory location o.

Destination Address register-OOOOOO (starting memory
0)
address

=

Source Address register-undefined (not used when
DMAO is linked to UART)

Transfer Descriptor register-IE, EPS, and TC cleared,
ST-byte transfer, SRP-continuous, TYPE-flowthrough,
DAD-Auto-increment memory address

Each DMA channel is a powerful and versatile device for
controlling and processing transfers of data. Its basic
function of managing CPU-independent transfers between two ports is augmented by an array of features requiring little or no external logic in systems using an 8- or
16-bit data bus.
Transfers can be performed between any two ports
(source and destination), including memory-to-I/O, I/O-tomemory, memory-to-memory, and I/O-to-I/O. Except for
flyby, two port addresses are automatically generated
for each transaction and can be either fixed or incrementing/decrementing.
During a transfer, a DMA channel assumes control of
the system address and data bus. Data is read from one
addressable port and written to the other addressable
port, byte-by-byte or word-by-word. The ports can be programmed to be either system main memory or
peripheral I/O devices.
For both flyby and flowthrough DMA transactions, if the
destination is a memory location that corresponds to an
entry in the on-chip memory (either cache or fixed
memory location), the on-Chip memory is updated to
reflect the new contents of the memory location.

N

!

DMA CHANNELS
The 2800 MPU has four on-chip Direct Memory Access
(DMA) channels to provide high bandwidth data
transmission capabilities. There are two types of DMA
channels; two support flyby transactions and the other
two do not. The two types of DMA channels otherwise
have identical capabilities, although they have different
priorities with respect to interrupt requests and bus requests.

8

Except in flyby mode, two 24-bit addresses are
generated by the DMA for every transfer operation, one
address for the source port and another for the destination port. Two readable address counters (three bytes
each) keep the current address of each port.
The DMA devices use the same memory and I/O timing
as the CPU for bus transactions, as indicated by the appropriate bus timing register.
Modes of Transfer Operation

Each DMA can be programmed to operate in one of
three transfer modes:
•

Single Transaction. Data operations are performed
one byte or word at a time.

•

Burst. Data operations continue until a port's Ready
line to the DMA goes inactive.

•

Continuous. Data operations continue until the end
of the programmed block of data is reached or if an
end of process has been signaled before the system
bus is released.

In all modes, once a byte or word of data is read by the
DMA channel, the operation is completed in an orderly
fashion, regardless of the state of other signals (including a port's Ready line).
Pin Descriptions

Each DMA channel has a Ready input line. In addition,
two DMA channels have a flyby output line to support
high speed data transfers between I/O devices and
memory.

367

The flyby output is asserted by the DMA channel to
signal a peripheral device associated with the DMA
channel that it should participate in the data transmission during the current flyby bus transaction.
The Ready line is sampled on the rising edge of each processor clock cycle. If Ready is active, the DMA channel
requests control of the external system bus to perform
the DMA transaction. When the external system bus is
available for DMA transfers, the DMA channel with a request pending and the highest priority assumes bus
mastership. The priority of DMA channels from highest
to lowest is: DMAO, DMA1, DMA2, and DMA3. A DMA
channel in burst mode relinquishes bus mastership to a
higher priority DMA channel only when its Ready line is
deasserted (or EOP is signaled or terminal count is
reached). A DMA channel in continuous mode relinquishes bus mastership only when EOP is signaled or
terminal count is reached.

Priority ot On-Chip DMA Channels and External
Bus Requesters
The on-chip DMA channels are arranged in a daisy chain
with the external Bus Request input line being the "next
lower bus requester" on this chain. The on-chip DMAs
behave as if they were external bus requestors with
respect to acquiring the bus, relinquishing the bus, and
priority access to the bus.

End-ot·Process
If the end-of-process (EOP) capability is enabled,
transfers by DMA channels can be prematurely terminated by a Low on Interrupt A line during the transfer.
This capability is programmed by a control bit in the
DMA Master Control register. EOP occurs regardless of
the setting of the Interrupt A Enable bit in the Master
Status register. When an EOP is signaled, the EOP
Signaled (EPS) bit in the Transaction Descriptor register
of the active DMA channel is set to 1 and the Enable bit
is cleared to O. If interrupt requests are enabled (IE
1
in the Transaction Descriptor register), an interrupt request is generated by the channel that was active when
the EOP was signaled. After an EOP has been signaled,
the DMA relinquishes the bus within 16 cycles of the last
DMA bus transaction.

=

If the End-Of-Process signal on Interrupt A line is still
asserted when the CPU is bus master, the signal is interpreted as an interrupt request; thus both the DMA channel and the external EOP generating device can request
interrupts simultaneously. Separate mask bits in the
Master Status register enable the CPU to accept interrupts from these two sources.
On a flowthrough transaction, if the EOP signal is received while the information is being read into the Z800
MPU, the transfer is aborted and the data is not written
out from the Z800 MPU.

368

DMA Linking
The DMA devices can be linked together to achieve
DMA transfers to non-contiguous memory locations
(linked operation). Bits in the DMA Master Control
register allow DMA3 to be linked to DMAl and DMA2 to
be linked to DMAO, when DMAO and DMAl have flyby
capabilities. If the appropriate bit is set to 1 in the DMA
Master Control register, the master DMA (0 or 1) signals
its linked DMA each time its transfer is complete (count
0). This acts as an internal ready input to the linked
DMA that reloads the master DMA control registers.

=

Words are loaded into the master DMA control registers
in the following order: Destination Address register (two
words), Source Address register (two words), Count (one
word), Transfer Descriptor register (one word). After six
words have been transferred, the master DMA deasserts its internal ready line and begins the transfer of
the next block of data. The linked DMA can be programmed to interrupt the CPU on "count equal 0" (to notify
software that the last block is being transferred) or the
master DMA can be programmed to interrupt the CPU on
"count equals 0" when the last block move is programmed into the master DMA (to notify software that the entire sequence of transfers is completed). When linking is
enabled, the external Ready line is not asserted by the
master DMA when count equals zero; also, both master
and linked DMAs generate interrupts whenever the programmed condition arises.
When programming linked DMAs, the last word to be
programmed must be the master DMA's Transaction
Descriptor register. Also, the linked DMA must be programmed before the master DMA's status register is
programmed.

DMA Master Control Register. This l6-bit register
(Figure 27) specifies the general configuration of the four
on-chip DMA channels: the linking of the DMA channels,
the software ready enables, edge detection enables for
the Ready lines, and EOP enable.

Figure 27. DMA Master Control Register

The fields in this register are:
OMAO to Receiver Link (OOR). When this bit is set to 1,
DMA channel 0 is linked to the UART receiver.
OMA 1 to Transmitter Link (0 1T). When this bit is set to 1 ,
DMA channell is linked to the UART transmitter.
OMA2 Link (02L). When this bit is set to 1, DMA channel
2 is linked to DMA channel O.

2259-027

DMA3 Link (D3L). When this bit is set to 1, DMA channel
3 is linked to DMA channel 1.

End-of-Process (EOP). When this bit is set to 1, the INTA
line is used as an end-of-process signal for the active
DMA channel.

Software Ready for DMAO (SRO). When this bit is set to 1,
DMA channel 0 requests service if enabled.

Software Ready for DMA 1 (SR1). When this bit is set to 1,
DMA channel 1 requests service if enabled.

Enable Count n (ECn). When bit ECn is set to 1, edge
detection circuitry is enabled on Ready line n.
DMA Channel Control Registers
Transaction Descr/ptor Registers. These four 16-bit
registers, one for each channel, (Figure 28) describe the
type of DMA transfer to be performed and contain control and status information.
11
TYPE

I I
TC

DAD

IEPsl

Figure 28. Transaction Descriptor Register
The fields in this register are:

End-of-Process Signaled (EPS). This bit is set to 1
automatically when the channel is active and an end-ofprocess is signaled on the Interrupt A input line, thus
prematurely terminating the transfer.
Destination Address Descriptor (DAD). The setting of
this 3-blt field indicates the type of location (memory or
I/O) and how the address is to be manipulated (incremented, decremented or left unchanged), as shown
in Table 4.
Table 4. SAD and DAD Encodlngs
Encoding

Address Modification Operetlon

o0 0

Auto-Increment memory location
Auto-decrement memory location
Memory address unmodified by transaction
Reserved
Auto·lncrement (by 1) 1/0 location
Auto-decrement (by 1) 1/0 location
1/0 address unmodified by transaction
Reserved

o0 1
o1 0

o1 1
100
101
1 10
111

Transaction Type (Type). This 2-bit field specifies flyby or
flowthrough type of operation or count option (00
flowthrough, 01 = count option, 10 = flyby write, 11 =
flyby read). In flowthrough mode of operation, two bus
transactions occur for each DMA operation-a read
from the source followed by a write to the destination. In
a flyby operation, only one bus transaction occurs for
each DMA operation. In flyby write to memory, the flyby
output pin is pulsed instead of an I/O transaction being
performed and the contents of the Destination Address
register are output to specify the memory location. In
flyby read from memory, the flyby output pin is pulsed instead of an 1/0 transaction being performed and the contents of the Source Address register are output to
specify the memory location. Only two DMAs have flyby
capability. In the count option type of operation, the DMA
acts as a counter and the SRP field governs the counting
frequency; the "count each" option decrements the
count register once for each High-to-Low transition on
the Ready line while the DMA enable bit is set to 1; the
gate option decrements the count register once for each
eight internal processor clock cycles while the Ready
line is Low and the DMA enable bit is set to 1.

=

Bus Request Protocol (BRP). The setting of these two
bits indicates the mode of DMA operation (Table 5); their
interpretation depends on whether the channel is programmed for DMA operations or with the count option.
Table 5. Bus Request Protocol (BRP)
Encoding

Single Transaction
Burst
Continuous
Reserved

0 0
0 1
0

CounterlTlmer
Count each
Gated count
Continuous gated count
Reserved

Size of Transfer (ST). This 2-bit field specifies the size of
the entity to be transferred by the DMA channel (Table
6). For word transfers to or from memory locations, the
memory address must be even (least significant bit is 0).
Long word (32-bit) transfers are supported only in flyby
mode, with the cache disabled.
Table 6. Size of Transaction (ST)
Encoding
ST1 STO
0
0

Transfer Complete (TC). This bit is set to 1 automatically
when the count register has reached zero.

DMA

0
1
0

Size of
Transfer
Byte
16·bit word
32-bit longword
Reserved

Number to Incrementl
Decrement By
1
2
4

369

I
!

Interrupt Enab/e (IE). When this bit is set to 1, the DMA
generates an interrupt request at end of count or end of
process. When this bit is 0, no interrupt request is
generated.
Source Address Descriptor (SAD). The setting of this
3-bit field indicates the type of location (memory or I/O)
and how the address is to be manipulated (incremented,
decremented or left unchanged), as shown in Table 4.
DMA Enab/e (EN). While this bit is 1, the DMA transfer is
enabled.

Count Register. This 16-bit register is programmed to
contain the number of DMA transfers to be performed.
When the contents of the count register reach zero, further requests on the RDY input line are ignored. The
DMA channel can be programmed to generate an interrupt when the count register reaches zero.
Source Address Register and Destination Address
Register. These 24-bit registers contain the 24-bit
physical addresses to be used during the DMA transaction. They are not translated by the MMU. In flyby mode,
only one of these registers is used to supply the address

for the bus transaction as indicated in the Mode field in
the Transfer Descriptor register. The format for these
registers is shown in Figure 29.
1.

I
I"

0

A"

.• ..• .•
• . . • • . • • • •
0

0

o

I

A11

A121

0

• • •

Ao

0

o

I
I
0

0

0

Figure 29_ Source and Destination Address
Registers Format

Flyby Transaction Timing
The Transaction Type field in the Transaction Descriptor
register indicates whether the transaction is a read or a
write. For flyby read transactions, the Source Address
Descriptor indicates the transaction is a read from
memory; for write flyby transactions the Destination Address Descriptor indicates the transaction is a write to
memory. Additional wait states can be automatically inserted if programmed in the appropriate timing register.

COUNTER/TIMERS
The l800 MPU's four counter/timers can be programmed by system software for a broad range of counting
and timing applications. The four independently programmable channels satisfy common microcomputer
system requirements for event counting, interrupt and interval timing, and general clock generation.
Three of the four counter/timers can have external input;
the fourth can be used only in the timing mode.
Programming the counter/timers is straightforward:
each channel is programmed with four bytes. Once
started, the channel counts down, and optionally reloads
its time constant automatically and resumes counting.
Software timing loops are completely eliminated. Interrupt processing is simplified because each channel uses
a unique vector from the Interrupt/Trap Vector Table.
Each channel is individually programmed with three
registers: a configuration byte, a control byte, and a
time-constant word. The configuration byte selects the
operating mode (counter or timer), enables or disables
the channel interrupt, and selects certain other
operating parameters. In the timing mode, the CPU procassor clock is divided by fou r for input to the
counter/timers. The time-constant word contains a value
from 0 to 65,535.
During operation, the individual counter channel counts
down from the present time-constant value. In counter
mode operation, the counter decrements on each of the
input pulses until the count/time output condition is met.
Each decrement is synchronized by the scaled internal
processor clock. For counts greater than 65,536, two of

370

the counters can be programmably cascaded. When the
count/time output condition is reached, the downcounter
is automatically reset with the time constant value, if so
programmed.
The timer mode determines time intervals without additional logic or software timing loops. Time intervals are
generated by dividing the internal processor clock by
four and decrementing a presettable downcounter.
Thus, the time interval is an integral multiple of the processor clock period, the prescaler value four, and the
time constant that is preset in the downcounter. A timer
is triggered by setting the software trigger control bit in
the Control/Status register or by an external input.
Three channels can generate an external output when
the count/time output condition is met. The output is high
when the internal presettable downcounter contains all
zeros.
Each channel can be programmed to generate an Interrupt Request, which occurs only if the channel has its Interrupt Enable control bit set to 1 by software programming. When the l800 CPU accepts the interrupt request
it automatically vectors through the Interrupt Vector
Table.
The four channels of the l800 MPU are fully prioritized
and fit into four different slots in the l800 internal
peripheral daisy-chain interrupt structure. Channel 0 has
the highest priority and Channel 3 has the lowest. The
channels have separate interrupt enables and the CPU's
Master Status register has individual control bits that
selectively inhibit interrupts from each channel.

2259-029

Gate Operation. A counter/timer can be programmed to

Modes of Operation

count or time only when a gating condition is met. While
the counter/timer is enabled and the external gate
capability is selected, an external input line is monitored;
only while this line is High are the counting or timing
operations performed. The software gate facility filters
the state of the input line; while the software gate bit in
the Command and Status register is cleared to 0, the
gating condition is not met regardless of the signals on
the gating line. The gate facility is illustrated in Figure 30.

Three of the counter/timer channels have two basic
modes of operation: as counters or as timers. As
counters they monitor external input lines and record
Low to High transitions on these lines. In the timer mode,
the processor clock, scaled by four, is used instead of
the external input line. The duration of this counting or
timing can be either continuous from initial enabling (trigger operation) or only during intervals specified by
signals on an input line (gate and gate/trigger operation).
The count can be automatically restarted by programming the Retrigger Enable control bit in the
counter/timer's Configuration register. Channel number
2 has no external inputs, and thus operates only as a
timer.

Trigger Operation. A counter/timer can be programmed
to count or time only after a triggering condition occurs.
While the counter/timer is enabled and the external trigger capability is programmed, an external input line is
monitored; only after this line makes a Low-to-High transition is a counting or timing operation performed, The
software trigger facility causes the triggering condition
to be met regardless of the activity of this line. The trigger operation is illustrated in Figure 31.

Each of the four counter/timers has a software gate and
trigger facility that extends the hardware capabilities of
the counter/timers.

Counting Operation. While the appropriate enabling

GatelTrlgger Operation. One input line can be used for
both the gating and the triggering functions. A Low-toHigh transition on this line acts as a trigger and subsequent High signals on this line function as gate signals. If
non-retriggerable mode is programmed, subsequent
Low-to-High transactions do not cause a trigger.
GateiTrigger Operation is shown in Figure 32.

conditions are met, the counter/timer monitors its input
line for Low-to-High transitions. When such a transition
occurs, the Count/Time register is decremented by 1.

Timing Operation. While the appropriate enabling conditions are met, the counter/timer monitors the internal
processor clock scaled by four for Low-to-High transitions. When such a transition occurs the CountJTime
register is decremented by 1.
OATIl
INPUT _ _ _ _ _..1

Llli.-__n...rli.-_

COUNTER,
OR TIMER _ _ _..I
COUNTmME
REOISTER
DECIIIIMUTED

*

*

*

Figure 30. Gate Facility

TRIGO ...
INPVI' _ _ _ _ _ _ _ _.......

COUNTER

n

UNE _ _ _.....

~

_ _ _.....

__n__

COUNTITIME
IIIIOISTER
DECREMENTED

Figure 31. Trigger Operation

2259-000, 031

371

?

OATEITRIOOER
INPUT

------

GATE

TRIGGER

GATE

LJ

COUNTER
LINE
COUNT/TIME
REOISTER
DECREMENTED

Figure 32. GatelTrigger Operation

The software gate and trigger mechanism can also be
used in this mode of operation. A software gate before a
trigger (hardware or software) has no effect on the
counter/timer. After a hardware or software trigger, the
software gate must be set to 1 for the Count/Time
register to be decremented. A software trigger after a
hardware or software trigger has no effect unless the
Retrigger Enable control bit is set to 1.
CounterlTimer Control and Status Registers

Each counterltimer has two 8·bit control registers and
two 16·bit count registers. The Configuration register
and Command and Status register determine the
counterltimers's operation, the Counter/Timer Com·
mand/Status register provides information about the cur·
rent operation, the Time Constant register contains the
initialization value for the counterltimer, and the
Count/Time register contains the current value of the
count in progress.

Counter/Timer Configuration Register. This 8·bit
register (Figure 33) specifies the counterltimer's mode
of operation: the pin configuration, whether an interrupt
request is generated, and whether the countdown se·
quence is automatically restarted when the count
reaches zero or when a trigger occurs.

IC/sl RE liE ICTc·1

IPA

·CTC Is present on counter/timers
o and 2 only.

Figure 33. CounterlTlmer Configuration Register

The fields in this register are:

Input Pin Assignments (lPA). This 4·bit field specifies the
functionality of the input lines associated with the
counterltimer and whether the counterltimer monitors
an external input (counting operation) or uses the scaled
internal processor clock (timing operation). The four bits
in this field can be associated with enabling output
generation (EO), selecting the external signal or internal
clock (C/T) , enabling the gating facility (G), and enabling
the triggering facility (T). The selected options determine
the functions associated with each input line associated
with the counterltimer, as illustrated in Table 7.
CounterlTimer Cascade (CTC). When this bit is set to 1,
counterltimers 0 and 1 and/or counterltimers 2 and 3
form a 32·bit counter. When used as 32·bit counter/
timers, the control and status registers corresponding to
counterltimers 0 and 2 are not used, with the exception

Table 7. Input Pin Functionality

EO
0
0
0
0
0
0
0
0

IPA Field
CIT G
0
0
0
0

0
0

Unused

Unused

Timer

Unused

Trigger

Timer

0

Gate
Gate

Unused
Trigger

Timer
Timer

0
0

0
1

0

Unused
Trigger

Counter
Counter

Input

Counter
Timer

Counter

Gate
GateITrigger

0

Output

Unused
Trigger
Gate
GateITrigger

Timer

0

Output
Output

0
0

Output
Output

Timer
Timer

Input

Counter

Unused

Unused

Reserved

Unused

Unused
Unused

Reserved
Reserved

Unused

372

Input
Input
Input

1

1

0
0

Notes

1
1

0
0

Pin Functionality
CounterlTlmer 1/0 CounterlTlmer Input

0

1

1
1

0
0
0
0

T

2259-032. 033

of the CTC bits in the counter/timer configuration
registers. The CTC bits in the counter/timer configuration
registers of counter/timers 1 and 3 are never used.
Interrupt Enab/e (IE). While this bit is set to 1 the
counter/timer generates an interrupt request when the
count/time output condition is met. While this bit is no
interrupt request is generated.

°

Retrigger Enab/e (RE). While this bit is set to 1, the time
constant value is automatically loaded into the
Count/Time register when a trigger input is received
while the counter/timer is counting down. While this bit is
0, no reloading occurs.
Continuous/Single Cycle (C/S). While this bit is set to 1,
the countdown sequence is automatically restarted
when the count reaches zero by loading the time constant value into the Count/Time register. While this bit is
0, no reloading occurs.

Counter/timer channel 2 can be programmed as a
counter. However, since it has no external inputs to
count, this is not a useful mode of operation .•
Counter/Timer Command/Status Register_ This S-bit
register (Figure 34) provides software control over the
operation of the counter/timer and reflects the current
status of the counter/timer's operation. Control bits in
this register enable the counter/timer's operation and
provide software gate and trigger capabilities. Status
bits indicate whether a count is in progress, the
count/time output condition has been reached, or the
condition has been reached a second time.
7

0

I EN I aT I Ta I 0 I 0 ICIP ICefORI
Figure 34_ CounterlTlmer Command/Status Register

The fields of this register are:
Count Overrun (COR). When this bit is set to 1 the
count/time output condition has been reached and the
CC bit is set to 1, thus indicating a count overrun condition. While this bit is cleared to 0, the count/time output
condition has not been reached with the CC bit set since
the time the CC bit was cleared by software. Ttlis bit can
be read or written (set or cleared) by software I/O instructions.
CounVTime Output Condition has been Met (CC). When
this bit is set to 1 the Count/Time register has been
decremented to zero by the counter/timer control circuitry in single cycle mode, or the Count/Time register
has been reloaded in continuous mode. When this bit is
cleared to the count has not reached the count/time
output condition since the bit was cleared by software.
This bit can be read or written (set or cleared) by software I/O instructions.

°

2259-034

Count in Progress (C/P). While this bit is set to 1 the
counter/timer is operating and the Count/Time register is
non-zero; while this bit is cleared to the counter/timer
is not operating. This bit is controlled by the
counter/timer control circuitry; it can be read by an I/O
read but cannot be set or cleared by an I/O write instruction.

°

Software Trigger (TG). When this bit is set to 1 (and the
trigger operation of the counter/timer is enabled), if the
Enable bit is also set to 1, the trigger operation is enabled on the riSing edge of the first processor clock
period following the setting of this bit from a previously
cleared value. That is, if a hardware trigger has not
already occurred, the contents of the Time Constant
register are loaded into the CountlTime register and the
countdown sequence begins. If a hardware trigger has
already occurred, then if Retrigger Enable is set to 1, the
counter/timer is retriggered; otherwise, setting this bit
has no effect. Writing a 1 in this field when the previous
value was 1 has no effect on the operation of the
counter/timer. When this bit is cleared to zero, this bit
has no effect on the operation of the counter/timer.
Software Gate (GT). When this bit is set to 1 (and the gate
operation of the counter/timer is enabled), if the Enable
bit is also set to 1, operation begins on the riSing edge of
the first processor clock period following the setting of
this bit from a previously cleared value. Writing a 1 in this
field when the previous value was 1 has no effect on the
operation of the counter/timer. When this bit is cleared to
0, the countdown sequence is halted.
Enab/e (EN). While this bit is set to 1, the counter/timer is
enabled; operation begins on the rising edge of the first
processor clock period following the setting of this bit
from a previously cleared value. Reset clears this bit.
While this bit is cleared to 0, the value in the Time Constant register is constantly transferred to the Count/Time
register. If the Time Constant register is all zeros, the
output of the counter/timer is one. Thus, when the
counter/timer is not enabled, the counter/timer output in
conjunction with the Time Constant register can be used
as an I/O port. Writing a 1 in this field when the previous
value was 1 has no effect on the operation of the
counter/timer. While this bit is 0, the counter/timer performs no operation during the next (and subsequent)
processor clock periods.

Time-Constant Register. This 16-bit register holds the
value that is automatically loaded into the Count/Time
register when the counter/timer is enabled, or in the continuous or retrigger mode when the count reaches zero
or the trigger is asserted, respectively. This register can
be read or written by I/O instructions.
Count/Time Register. This 16-bit register holds the current value of the count or timing in progress. It is automatically loaded from the Time-Constant register, and
can be read by software using the I/O read instructions.

373

Pin Descriptions

Counter/timers 0, 1, and 3 have two external input lines
associated with them. The I/O lines transfer signals between the counter/timers and external devices. The input lines receive signals from external devices for the

counter/timers. The interpretations of the signals on
these lines is determined by the Input Pin Assignment
field in the Configuration register.

MULTIPROCESSOR MODE OF
OPERATION
Features

•

Allows global memory areas for shared resources

•

Global memory addresses are user-specified

•

Separate requests for local and global buses

•

Requesting mechanism is transparent to user

•

Easily interfaces to external arbiters

One mode of operation for the Z800 MPU is as an I/O
Processor (lOP); while in this mode, the Z800 MPU also
supports multiprocessor configurations. While operating
as an lOP, the Z800 MPU is able to support both a local
bus (of which the Z800 MPU is the default bus master)
and a global bus (for which the Z800 MPU must request
the bus and receive a bus grant signal before issuing a
bus transaction.)
To accomplish this functionality, two pins previously
used for the counter/timer 0 peripheral are dedicated to
be global bus request and global bus grant lines; thus
this feature is available only in the 64-pin devices. A
register in the Z800 MPU bus interface unit is accessed
for each bus transaction to determine whether the
physical address must be accessed via the global or
local bus.
Architecture
Pin Functionality. Two pins are used by the lOP for obtaining the global bus: the Global Request line is used to
request the global bus, one which the CPU does not control by default (counter/timer 0 input/output), and the
Global Acknowledge line receives an acknowledge of a
global bus request (counter/timer 0 input).
Local Address Register. The bus interface unit
distinguishes whether a bus transaction uses the local or
global bus by comparing the four most significant bits of
the physical address of memory (address bits 20 through
23) with a 4-bit Base field in the local Address register
(Figure 35). A mask field in this register specifies which
bits are to be used. If all the corresponding address bits
match the Base field bits (for those bit positions
specified by the mask field), then the bus transaction can
proceed on the local bus without requesting the global
bus; if there is a mismatch in at least one specified bit
position, then the global bus is be requested and the bus
transaction does not proceed until the global bus
acknowledge signal is asserted.

374

7

EE.fE'fE+E201

0

I I

8231 8221 821 820

Figure 35. Local Address Register

The bits in the local Address register are:

Base (Bn). When Bn is 1, address bit An must be 1 for a
local bus transaction to be performed (unless Match
Enable bit MEn is 0); when bit Bn is 0, address bit An must
be 0 for a local bus transaction to be performed.
Match Enable (MEn). When MEn is 1, address bit An is
compared 10 base bit Bn to determine if the address requires the use of the global bus. When MEn is 0, then any
values for An and Bn will produce a match. If each MEn is
0, then all bus transactions are performed on the local
bus.
CPU Accesses on the Global Bus

The control of the local bus uses BUSREQ and BUSACK
in the same way as in the non-multiprocessor mode of
operation. The input signal BUSREQ is asynchronous to
the processor clock; the CPU synchronizes BUSREQ internally. When the CPU acknowledges a local bus request by driving BUSACK active, then the CPU places all
other output signals, including GREQ, in 3-state. After
reset the CPU acknowledges a request for the local bus
before performing any transactions.
When the CPU has not granted the local bus then it can
request a global bus. A timing diagram for global bus request is shown in Figure 36. First, on a rising edge of
ClK, the CPU drives the address and status lines valid.
AS is not asserted, however; GREQ serves the function
of indicating that a valid address is on the local bus. On
the next falling edge of ClK the CPU drives GREQ active.
The CPU samples GACK on each falling edge of ClK until the arbiter drives GACK active and leaves BUSREQ inactive, indicating that the addressed global bus is
available to the CPU. The BUSREQ line is used by the arbiter to remove all of the devices that are simultaneously
requesting the global bus, except the one device that is
granted the global bus. The devices that are not granted
the global bus make their GREQ inactive. The input
signal GACK is asynchronous to the processor clock; the
CPU synchronizes GACK internally. The CPU that was
granted the bus performs one or more transactions on
the global bus until the CPU no longer needs the global

2259-035

DMA Accesses on the Global Bus

bus or the CPU is prepared to acknowledge a local bus
request. The CPU then drives GREQ inactive and wa~ts
for the arbiter to drive GACK inactive. The CPU relinquishes the global bus upon receipt of a local bus, DMA,
or refresh request or after any transaction except for a
test and set instruction (both data read and write are performed before relinquishing the bus) and for burst
transfers (the entire sequence of data reads are made).

Each on-chip DMA device can use the global bus to per·
form data transfers. The address generated during each
DMA initiated transfer is compared with the contents of
the Local Address register to determine whether the
global bus is requested; this operation is the same as for
CPU-generated requests.

ADDRESSI
DATA

HIGH

STo-ST.
RIW
BIW

Figure 36. Multiprocessor Mode Timing

EXTERNAL INTERFACE (ZaO-BUS)
Features
•

8-bit data bus

•

Multiplexed addressldata lines

•

Supports Z80 Family peripherals

Pin Descriptions
A. Address (output, active High, 3-state). These address
lines carry I/O addresses and memory addresses during
bus transactions. Of the 16 lines, only 11 are available
on the 40-pin version.
AD. Address/Data (bidirectional, active High, 3-state).
These eight multiplexed Data and Address lines carry I/O
addresses, memory addresses, and data during bus
transactions.
AS. Address Strobe (output, active Low, 3-state). The ris·
ing edge of AS indicates the beginning of a transaction
and shows that the address is valid.

2259-036

BUSACK. Bus Acknowledge (output, active Low). A Low
on this line indicates that the CPU has relinquished control of the bus in response to a bus request.
BUSREQ. Bus Request (input, active Low). A Low on this
line indicates that an external bus requester has obtained or is trying to obtain control of the bus.
ClK. Clock Output (output). The frequency of the processor timing clock is derived from the oscillator input
(external OSCillator) or crystal frequency .(inter~al
oscillator) by dividing the crystal or external OSCillator input by two. This clock is further divided by one, two, or
four (as programmed), and then output on this line.
HALT. Halt (output, active Low, 3·state). This signal indicates that the CPU has executed a Halt instruction and
is awaiting an interrupt before operation can resume.
INT. Maskable Interrupts (input, active Low). A Low on
one is available on the 40-pin version.

375

IORQ. Input/Output Request (output, active Low,
3-state). This signal indicates that ADo-AD7 and A16-A23
of the address bus hold a valid 1/0 address for a 110 read
or write operation. An 10RO signal is also generated with
an M1 signal when an interrupt is being acknowledged,
to indicate that an interrupt response vector can be
placed on the data bus. Interrupt acknowledge opera·
tions occur during M1 time and 110 operations never oc·
cur during M1 time.
M1. Machine Cycle One (output, active Low, 3-state).
This signal indicates that the current transaction is the
opcode fetch cycle of a RETI instruction execution. M1
also occurs with 10RO to indicate an interrupt
acknowledge cycle.

MREQ. Memory Request (output, active Low, 3·state).
This signal indicates that the address bus holds a valid
address for a memory read or write operation.
NMI. Nonmaskable Interrupt (input, falling-edge activated). A High-to-Low transition on this line requests a
nonmaskable interrupt.
RD. Read (output, active Low, 3-state). This signal indicates that the CPU or DMA peripheral is reading data
from memory or an 1/0 device.
RESET. Reset (input, active Low). A Low on this line
resets the CPU and on-chip peripherals.

CTIO. Counter/Timer //0 (bidirectional, active High,
3-state). These I/O lines transfer signals between the
counterltimers and external devices.

IE. Input Enable (output, active Low, 3-state). A Low on
this line indicates that the direction of transfer on the Address/Data lines is toward the CPU.
OE. Output Enable (output, active Low, 3-state). A Low
on this line indicates that the direction of transfer on the
Address/Data lines is away from the CPU.

PAUSE. CPU Pause (input, active Low, Z8216 only).
While this line is Low the CPU refrains from transferring
data to or from on Extended Processing Unit in the
system or from beginning the execution of an instruction.
RX. UART Receive (input, active High). This line receives
serial data at standard TIL levels.
ROY. DMA Ready (input, active Low). These lines are
monitored by the DMAs to determine when a peripheral
device associated with a DMA port is ready for a read or
write operation. When a DMA port is enabled to operate,
its Ready line indirectly controls DMA activity; the manner in which DMA activity is controlled by the line varies
with the operating mode (single-transaction, burst, or
continuous).

TX. UART Transmit (output, active High). This line

RFSH. Refresh (output, active Low, 3-state). This signal

transmits serial data at standard TIL levels.

indicates that the lower ten bits of the Address bus con·
tain a refresh address for dynamic memories and the
current MREO signal should be used to perform a
refresh read to all dynamic memories.

Bus Operations

WAIT. Wait (input, active Low). A Low on this line indicates that the responding device needs more time to
complete a transaction.

WR. Write (output, active Low, 3-state). This signal indicates that the bus holds valid data to be stored at the
addressed memory or I/O location.

XTALI. C/ock/Crysta/lnput (time-base input). Connects
a series-resonant crystal or an external single phase
clock to the on-Chip oscillator.

XTALO. Crystal Output (time-base output). Connects a
series-resonant crystal to the on-chip oscillator.

+ 5 V. Power Supply Voltage. (+ 5 nominal).
GND. Ground. Ground reference.
The following lines are available only on the 64-pin ver·
sion:

DMASTB. DMA Flyby Strobe (output, active Low). These
lines select peripheral devices for flyby transfers.

CTIN. CounterlTimer Input (input, active High). These
lines receive Signals from external devices for the
counter/timers.

376

Two kinds of operations can occur on the system bus:
transactions and requests. At any given time, one device
(either the CPU or a bus requester) has control of the bus
and is known as the bus master. A transaction is initiated
by the bus master and is responded to by some other
device on the bus. Only one transaction can proceed at a
time; eight kinds of transactions can occur:
DMA Flyby. This transaction is used by the DMA
peripheral to transfer data between an external
peripheral and memory.
Halt. This transaction is used to indicate that the CPU is
executing a halt instruction.
Internal Operation. This type of transaction does not
transfer data; it indicates that the CPU is performing an
operation that does not require data to be transferred on
the bus.
Interrupt Acknowledge. This transaction is used by the
CPU to acknowledge an interrupt and to transfer addi·
tional information from the interrupting device.
I/O. This transaction is used by the CPU or DMA
peripheral to transfer data to or from an external
peripheral.
Memory. This transaction is used by the CPU or DMA
peripheral to transfer data to or from a memory location.

Refresh. This type of transaction performed by the
refresh peripheral does not transfer data; it refreshes
dynamic memory.

RETI. This transaction is generated only by the CPU and
is used in conjunction with the Za4DD peripheral's interrupt logic.
Only the bus master can initiate transactions. A request,
however, can be initiated by a component that does not
have control of the bus. Two types of these requests can
occur:

Bus. This request is used by external devices to request
control of the system bus to initiate transactions.

Interrupt. This request is used to request the attention of
the CPU.
When an interrupt or bus request is made, it is answered
by the CPU according to its type. For an interrupt request, the CPU initiates an interrupt acknowledge transaction and for bus requests, the CPU enters bus disconnect state, relinquishes the bus, and activates an
Acknowledge signal.
Finally, the zaDD MPU itself may not be the system bus
master. See the multiprocessor mode section for a
discussion of this capability.

Transactions
Information transfers (both instructions and data) to and
from the ZaDD MPU are accomplished through the use of
transactions. All transactions start when AS is being
driven low and then raised High. This signal can be used
to latch ZaDD MPU addresses to de-multiplex the zaDD
Address/Data lines required by ZaD Family peripherals.
Coincident with AS assertion, the Output Enable line is
also asserted.
If the transaction requires an address, it is valid on the
rising edge of AS. No address is required for Interrupt
Acknowledge.
The Read and Write lines are used to time the actual
data transfer. (Refresh transactions do not transfer any
data and thus do not activate RD.) For write operations,
a low on WR indicates that valid data from the bus
master is on the AD lines. The Output Enable line is also
activated with WR. For read operations, the bus master
makes the AD lines 3-state before driving RD low so that
the addressed device can put its data on the bus. The
bus master samples this data on the falling clock edge
just before raising RD High. The Input Enable line is also
activated with RD.

Walt. The Wait line is sampled on the falling clock edge
when data is to be sampled (i.e. when RD or WR rises). If
the Wait line is low, another cycle is added to the transaction before data is sampled (RD or WR rises). In this
added cycle, and all subsequent cycles added due to
WAIT being low, the Wait line is sampled on the falling

edge and, if it is low, another cycle is added to the transaction. In this way, the transaction can be extended by
external devices to an arbitrary length to accommodate
(for example) slow memories or I/O devices that are not
yet ready for data transfer.
The WAIT input is synchronous, and must thus meet the
specified setup and hold times in order for the ZaDD MPU
to function correctly. This requires asynchronouslygenerated WAIT signals to be synchronized to the ClK
output before they are input into the ZaDD MPU.
Automatic wait states can also be generated by programming the Bus Timing and Control register and Bus
Timing and Initialization register; these are inserted in
the transaction before an external WAIT signal is sampled.

Memory Transactions. Memory transactions move instructions or data to or from memory when the ZaDD
MPU makes a memory access. Thus, they are generated
during program execution to fetch instructions from
memory and to fetch and store memory data. They are
also generated to store old program status and fetch
new program status during interrupt and trap handling,
and are used by DMA peripherals to transfer information. A memory transaction is three bus cycles long
unless extended with wait states, as explained previously.
During the first bus cycle, AS is asserted to indicate the
beginning of a transaction. The MREQ signal goes active
during the second half of this bus cycle, which indicates
a memory transaction. For a Read operation (Figure 37),
RD is activated during the first half of the second bus cycle; Output Enable is deasserted at the beginning of the
second cycle and Input Enable is asserted during the second half of the second cycle. The CPU samples information from the memory on the Address/Data bus with
the falling edge of the clock during the third bus cycle
and this same edge is used to deassert MREQ, and iE.
Thus the data has already been sampled before RD is
deasserted. For a Write operation (Figure 3a) the WR line
is asserted during the second half of the second cycle.

RETI Transactions. These transactions (Figure 39) are
similar to two memory read transactions except that M1
is asserted throughout each read transaction, falling early in the first bus cycle, and that MREQ, M1, RD and iE
are deasserted on the rising edge of the clock following
the third cycle. Each of the read transactions is followed
by a minimum of three bus cycles of inactivity. These
transactions are invoked when an RETI instruction is encountered in the instruction stream; they are used during
the re-fetching of the instruction from memory so that interrupt logic within ZaD peripherals that monitor the bus
for this instruction will function correctly.

377

Ct.>

OJ

1....-- T1~"-T2---"I<4--T3--------1

.. Z8208 only.
m = 18 for Z8108. 23 for Z8208.

figure 37. Memory Read Timing

I
i

I~ T1------..J~T2._...._..I4---T3-----..1

.. Z8208 only•
m = 18 for Z8l08. 23 for Z8208.

Figure 38. Memory Write Timing

I
~T1--'I4--T2--.I'---T3~~T4

~

I

I

ADO-AD7

As-Am

AS

-(

-Y

ADDRESS

ED (1'ROM
MEMORy)

+

T5---"'1~

T64""""-

T1---"1"--- T2--'~

I

T34""-

I

I

I
4D(FROM
MEMORy)

ADDRESS

ADDRESS

X

X

/

\

X

ADDRESS

- '-I

- """\

/

AD

/

WAIT

Oi*

~

IE·

I

I

T6--"1

I

I

MREQ

M1

T4--"1""'-- TS----.t......--

\.

/

-'

\.

\
/

\

/
\.

.. Z8208 only.
B-blt Data bus only; m =18 for Z8108, 23 for Z8208.

Figure 39. RETI Read Timing

W

--J

(0

a_oo8Z

/

X.

Internal Operations and Halt Transactions. There are
two kinds of bus transactions that do not transfer data:
Internal Operations (Figure 40) and Halt (Figure 41). Both
transactions look like a memory transaction, except that
RD and WR remain High and no data is transferred. For
the Internal Operation transaction, MREO is not
asserted. The Wait line is not sampled during either the
Internal Operation or Halt transactions.

1/0 Transactions. I/O transactions move data to (Figure
42) or from (Figure 43) peripherals and are generated

during the execution of I/O instructions.
I/O transactions are four clock cycles long at a
minimum, and may be lengthened by the addition of wait
cycles. The extra clock cycle allows for slower
peripheral operation.
The 10RO line indicates that an I/O transaction is taking
place. The I/O address is found on ADo-AD7 and Aa-A23
when AS rises.

Halt transactions are identical to memory read transactions except that HALT is asserted throughout the transaction, falling during the second half of the first bus
cycle, and remains asserted until an interrupt is
acknowledged. This transaction is invoked when a Halt
instruction is encountered in the instruction stream or a
fatal sequence of traps occurs. Although the Halt transaction is three cycles, the HALT line remains asserted
until an Interrupt request is acknowledged or a Reset is
received. Refresh (to maintain a minimum frequency of
bus transactions) or DMA transfers may occur while
HALT is asserted; also, the bus can be granted. The address put out during the address phase of this cycle is
the address of the Halt instruction.

The 10RO line and either RD and iE or WR with OE still
asserted, are asserted during the second cycle. Output
data to the peripheral is placed on the bus at this time; input data from the peripheral is read during the fourth
cycle (unless additional wait states are inserted in the
transaction).

I4--Tl--+-I~T2~I"--T3---..1

ADO-AD7

As-Am

UNDEFINED

HIGH

AD AND

HIGH

WR

OE*

ji*

'" Z8208 only.
m = 18 lor Z8108, 23 lor Z8208.

Figure 40. Internal OperatiDn Timing

380

2259-040

ADO-AD?

AS-Am

HIGH

RD AND WR

HIGH

OE·*

* Address of HALT Instruction.
*'" Z8208 only.
m = 18 for Z8108, 23 for Z8208.

II **

Figure 41. Halt Timing

I......--T1------I..---T2--+-I~TW---..I.-.--T3-----!

ADO-AD?

AS-Am

lORa

OE"

rE"

HIGH

• Z8208 only.
m = 18 for Z8108, 23
for Z8208.

Figure 42. 1/0 Write Timing
22590041.042

381

.. Z8208 only.
m = 18 for Z8l08, 23 for Z8208.

Figure 43. I/O Read Timing

Interrupt Acknowledge Transactions. These transac·
tions (Figure 44) acknowledge an interrupt or trap and
read information from the device that generated the in·
terrupt. The transactions are generated automatically by
the hardware when an interrupt request is detected.
The Interrupt Acknowledge transactions are five cycles
long at a minimum, and have two automatic Wait cycles.
The wait cycles are used to give the interrupt priority
daisy chain (or other priority resolution device) time to
settle before the identifier is read. Additional automatic
wait states can be generated by programming the Bus
Timing and Control register.
The interrupt acknowledge transaction is indicated by an
M1 assertion without MREO during the first cycle. During
this transaction the IORO signal becomes active during
the third cycle to indicate that the interrupting device
can place an 8·bit vector on the bus. It is captured from
the AD lines on the falling clock edge just before IORO is
raised High.

382

There are two places where the WAIT line is sampled
and, thus, where a wait cycle can be inserted by external
circuitry. The first serves to delay the falling edge of
IORO to allow the daisy chain a longer time to settle, and
the second serves to delay the pOint at which the vector
is read.

Refresh Transactions. A memory refresh transaction
(Figure 45) is generated by the l800 refresh mechanism
and can occur immediately after the final clock cycle of
any other transaction. The memory refresh counter's
10·bit address is output on ADo-ADg during the normal
time for addresses. The RFSH line is activated with
MREO. This transaction can be used to generate
refreshes for dynamic RAMs.

2259-043

. .·..,I""·I----T.-I-Tw,--.. .*I. . .--Tw---<·*I·....--T.--!

I--TLA.T----<.~I""·I----T,--

-

I

I

I

I

I

L.-

/

--(
ADo-AD7

UNDEFINED'

-

r
" DATA I

~

I

UNDEFINED

A8-Am

HIGH

/

/

\

\

HIGH

\

iH!* *

IE**

*.

'* AD1

and AD2 Indicate type of Interrupt being acknowledged.
Z8208 only.

m

= 18 for Z81OS. 23 for 28208.

Figure 44. Maskable Interrupt AcknDwledge Sequence

383

ADO-AD7

Ae-Am

OE**

IE* *
·10 least-significant bits are Refresh address, the rest are undefined .

•• Z8208 only.
m = 18 for Z8108, 23 for Z820B.

Figure 45. Refresh Timing

Requests
There are three kinds of request signals that the l800
MPU supports. These are:
•

Interrupt requests, which another device initiates
and the CPU accepts and acknowledges.

•

Bus requests, which an external potential bus
master initiates and the l800 MPU accepts and
acknowledges.

•

Global bus requests, which the CPU or on-chip DMA
initiates to acquire a global System bus.

When a request is made, it is answered according to its
type: for interrupt requests, an Interrupt Acknowledge
transaction is initiated; for bus requests, an
Acknowledge signal is sent; for global bus requests, an
Acknowledge signal is received.

Interrupt Requests. The l800 CPU supports two types
of interrupt, maskable and nonmaskable (NMI). The Interrupt Request line of a device that is capable of
generating an interrupt can be tied to the NMI or
maskable interrupt request lines. Several devices can be

384

connected to one pin with the devices arranged in a
priority daisy chain. However, all l80 family peripherals
should be on the same line (or no nesting of interrupts
among different lines. The CPU uses different protocols
for handling requests on the NMI pin than the protocol
used for maskable interrupt pins. The sequence of
events shown below should be followed:
Any High-to-Low transition on the NMI input is asynchronously edge-detected, and the internal NMI latch is
set. At the beginning of the last clock cycle in the last internal processor clock cycle of any instruction, the interrupt inputs are sampled along with the state' of the internal NMI latch.
If a maskable interrupt is requested and the Master
Status register indicates that requests on that line are to
be accepted, the next possible bus transaction is the Interrupt Acknowledge transaction, which results in information from the highest-priority interrupting device being read off the AD lines. This data is used to initiate the
interrupt service routine. For a nonmaskable interrupt request, the hexadecimal constant 0066 is used to initiate
the interrupt service routine, except in mode 3.

Bus Requests. To generate transactions on the bus, a
potential bus master (such as the DMA Controller) must
gain control of the bus by making a bus request. A bus
request is initiated by pulling BUSREO Low. Several bus
requesters may be wire ORed to the BUSREO pin;
priorities are resolved externally to the CPU, usually by a
priority daisy chain.
The asynchronous BUSREO signal generates an internal
BUSREO, which is synchronous. If the external BUSREO
is Low at the beginning of any machine cycle, the internal BOSREQ causes the Bus Acknowledge line
(BUSACK) to be asserted after the current machine cy-

cle is completed. (Exceptions are the TSET instruction
where the read-modify-write cycle is atomic and DMA
transfer in burst or continuous mode). The CPU then
enters Bus Disconnect state and gives up control of the
bus. Ali CPU Output pins, except BUSACK, are 3-stated.
The CPU regains control of the bus after BUSREO rises.
Any device desiring control of the bus must wait at least
two bus cycles after BUSREO has risen before pulling it
down again.
The on-chip DMA channels have higher priority than external devices requesting the bus via BUSREO.

EXTERNAL INTERFACE (Z·BUS)
Features
•

16-bit data bus

•

Multiplexed address/data lines

•

Supports high-speed burst mode transfers

•

Provides EPA interface

Pin Descriptions

A. Address (output, active High, 3-state). These address
lines carry 1/0 addresses and memory addresses during
bus transactions. Of the eight lines, only three are
available on the 40-pin version.

AD. Address/Data (bidirectional, active High, 3-State).
These 16 multiplexed address and data lines carry 1/0
addresses, memory addresses, and data during bus
transactions.
AS. Address Strobe (output, active Low, 3-state). The rising edge of Address Strobe indicates the beginning of a
transaction and shows that the address, status, RIW and
Bm signals are valid.

BUSACK. Bus Acknowledge (output, active Low). A Low
on this line indicates that the CPU has relinquished control of the bus in response to a bus request.

INT. Maskable Interrupts (input, active Low). A Low on
these lines requests an interrupt. Of the three lines, only
one is available on the 40-pin version.

I

NMI. Nonmaskable Interrupt (input, falling-edge activated). A High-to Low transition on this line requests a
Nonmaskable Interrupt.

I!I
CI

RESET. Reset (input, active Low). A Low on this line
resets the CPU.

=

RIW. ReadlWrite (output, Low
Write, 3-state). This
signal determines the direction of data transfer for
memory, 110, or EPU transfer transactions.
ST. Status (output, active High, 3-state). These four lines
indicate the type of transaction occuring on the bus and
give additional information about the transaction.

WAIT. Wait (input, active Low). A Low on this line indicates that the responding device needs more time to
complete a transaction.

XTALI. C/ocklCrystallnput (time-base input). Connects
a series-resonant crystal or an external single-phase
clock to the on-chip clock oscillator.

XTAlO. Crystal Output (time-base output). Connects a
series-resonant crystal to the on-chip clock oscillator.

BUSREQ. Bus Request (input, active Low). A Low on this

+ 5 V. Power Supply Voltage.

line indicates that an external bus requester has obtained or is trying to obtain control of the bus.

GND. Ground. Ground reference.

BIW. BytelWord (output, Low = Word, 3-state). This
signal indicates whether a byte or a word of data is to be
transmitted during a transaction.

The following lines are available on the 64-pin device
version only:

ClK. Clock Output (output). The frequency of the processor timing clock is derived from the oscillator input
(external oscillator) or crystal frequency (internal
oscillator) by dividing the crystal or external oscillator input by two. This clock is further divided by one, two or
four (as programmed), and then output on this line.

DS. Data Strobe (output, active Low, 3-state). This signal
provides timing for data movement to or from the bus
master.

(+ 5 nominal).

DMASTB. DMA Flyby Strobe (output, active Low). These
lines select peripheral devices for DMA flyby transfers.
CTIN. CounterlTimer Input (input, active High). These
lines receive signals from external devices for the
counter-timers.

CTIO. CounterlTimer 110 (bidirectional, active High,
3-state). These 110 lines transfer signals between the
counter/timers and external devices.

385

iE. Input Enable (output, active Low, 3-state). A Low on
this line indicates that the direction of transfer on the AddresslData lines is toward the CPU.

Only the bus master can initiate transactions. A request,
however, can be initiated by a device that does not have
control of the bus. Two types of requests can occur:

OE. Output Enable (output, active Low, 3-state). A Low

Bus. This request is used to request control of the bus to
initiate transactions.

on this line indicates that the direction of transfer on the
Address/Data lines is away from the MPU.

PAUSE. CPU Pause (input, active Low, Z8216 only).
While this line is Low the CPU refrains from transferring
data to or from an Extended Processing Unit in the
system or from beginning the execution of an instruction.

Interrupt. This request is used to request the servicing by
the CPU.

RX. UART Receive (input, active High). This line receives
serial data at standard TTL levels.

When an interrupt or bus request is made, it is answered
according to its type: for an externally generated interrupt request, an Interrupt Acknowledge transaction is initiated by the CPU; for bus requests, the MPU enters Bus
Disconnect state, relinquishes the bus, and activates an
acknowledge signal.

RDY. DMA Ready (input, active Low). These lines are

Transactions

monitored by the DMA channels to determine when a
peripheral device associated with a DMA channel is
ready for a read or write operation. When a DMA channel is enabled to operate, its Ready line indirectly controls DMA activity; the manner in which DMA activity is
controlled by the line varies with the operating mode
(single-transaction, burst or continuous).

TX. UART Transmit (output, active High). This line
transmits serial data at standard TTL levels.

Bus Operations
Two kinds of operations can occur on the system bus:
transactions and request. At any given time, one device
(either the CPU or a bus requester) has control of the bus
and is known as the bus master. A transaction is initiated
by the bus master and is responded to by some other
device on the bus. Only one transaction can proceed at a
time; nine kinds of transactions can occur:
Burst Memory. These transactions are used to transfer
four words of instructions from the memory to the CPU.
DMA Flyby. This transaction is used by the DMA
peripheral to transfer data between an external
peripheral and memory.
EPU Transfer. This transaction is used to transfer data
between the CPU and an EPU.

Halt. This transaction is used to indicate that the CPU is
executing the Halt instruction.
Internal Operation. These transactions do not transfer
data.
Interrupt Acknowledge. This transaction is used by the
CPU to acknowledge an external interrupt request and to
transfer additional information from the interrupting
device.

110. This transaction is used by the bus master to
transfer data to or from an external peripheral.
Memory. This transaction is used by the bus master to
transfer data to or from a memory location.
Refresh. These transactions by the refresh mechanism
do not transfer data; they refresh dynamic memory.

386

Data transfers to and from the Z8DD MPU are accomplished through the use of transactions.
All transactions start with Address Strobe (AS) being
driven Low and then raised High by the Z8DD MPU. On
the rising edge of AS, the Status lines STo-ST3 are valid;
these lines indicate the type of transaction being initiated (Table 8); seven types of transactions are discuss·
ed in the sections that follow. Associated with the status
lines are two other lines that become valid at this time:
RNi, and BIW.
Table 8. Status Table
Code

0000
0001
0010
0011
0100
0101
0110
0111
toDD
1001
1010
1011
1100
1101
1110
1111

Meaning
Internal operation
Refresh
I/O transaction
Halt
Interrupt acknowledge line A
Interrupt acknowledge (nonmaskable)
Interrupt acknowledge line B
Interrupt acknowledge line C
Memory Reference (cachable)
Memory Reference (non-cachable)
Memory-EPU transfer
Reserved
EPU Instruction fetch
EPU Instruction fetch (first word)
EPU-CPU transfer
Test and Set (data transfers)

If the transaction requires an address, it is valid on the
rising edge of AS. No address is required for EPU-CPU
transfer and Internal Operation transactions; the contents of the A and AD lines while AS is asserted are
undefined. If an address is generated, the OE signal is
also activated.

The Z-BUS MPUs use Data Strobe (OS) to time the actual
data transfer. (Note that Refresh, Halt, and Internal
Operation transactions do not transfer any data and thus
do not activate OS.) For write operations (RiW
Low), a
Low on OS indicates that valid data from the bus master
is on the AD lines. The Output Enable continues to be
asserted until OS is deasserted. For read operations
(RIW = High), the bus master makes AD Lines 3-state,
deasserts OE and asserts iE after driving OS Low so that
the addressed device can put its data on the bus. The
bus master samples this data on the falling clock edge
just before raising OS and iE High.

=

Walt. The Wait line is sampled on the falling clock edge
when data is sampled by the Z800 MPU (Read), or the
falling clock edge before OS rises (Read or Write). If
WAIT is Low, another cycle is added to the transaction
before data is sampled or OS rises. In this added cycle,
and all subsequent cycles added when WAIT is Low,
WAIT is again sampled on the falling clock edge and, if it
is Low, another cycle is added to the transaction. In this
way, the transaction can be extended to an arbitrary
length by external circuitry to accommodate (for example) slow memories or 1/0 devices that are not yet ready
for data transfer. Automatic insertions of wait states by
the CPU or on-chip DMA channels can be programmed
by setting fields in the Bus Timing and Control register
and Bus Timing and Initialization register to indicate the
number to be inserted.
Memory Transactions. Memory transactions move
data to or from memory when a bus master makes a
memory access. Thus, they are generated during pro·
gram execution to fetch instructions from memory and
to fetch and store memory data. They are also generated
to store old program status and fetch new program
status during interrupt and trap handling and after reset.

A memory transaction is three bus cycles long unless extended when WAIT is asserted, as explained above in the
Wait section. The status pins, besides indicating a
memory transaction, give the following information:
•

Whether the memory access is cacheable (1000) or
noncacheable (1001) information.

•

Whether the data for the access is supplied (written)
or captured (read) by an Extended Processing Unit
(1010).

•

Whether the information being fetched from memory
is an EPA template (1100, 1101).

•

Whether the memory access is part of the readmodify-write operation (Test and Set) (1111).

Bytes transferred to or from odd memory (address bit 0
is 1) locations are always transmitted on lines ADo-AD7
(bit 0 on ADo)· Bytes transferred to or from even memory
locations (address bit 0 = 0) are always transmitted on
lines ADs-AD15 (bit 0 on ADs). For byte reads (BIW High,
RiW High), the CPU or on-Chip DMA channel uses only
the byte whose address it put out on the bus. For byte
writes (BiW High, R/W Low), the memory should store
only the byte whose address was output. During byte
memory writes, the CPU (or on-Chip DMA channel in nonFlyby transactions) places the same byte on both halves
of the bus, and the proper byte must be selected by
testing Ao. For word transfers, (RiW = Low), all 16 bits
are captured by the CPU or DMA channel (Read: RIW =
High) or stored by the memory (Write: R/W = Low). For
these transactions (either memory or 1/0) the bytes of
data appear swapped on the bus with the most significant byte on ADrADo and the least significant byte on
AD15-ADs·
Memory transaction timings are shown in Figures 46-50.

387

II

8
II

!

...

ADO-AD,.

STATUS
B/W
1

R/W

=

08·

ji.

'Z8216 only.
m • 18 for Z8116, 23 lor Z8218.

Figure 46. Memory Read Timing

ADo-AD"

AS

STATUS
B/W
= 0

RlW

Ii·

HIGH

'Z8216 only.
m = 18 for Z8116, 23 lor Z8216.

Figure 47. Memory Write Timing

388

22~,047

I
ADO-AD,.

- -<
-

STATUS

R/W

B/W
1

=

ADDRESS

I

~

I
'\

I

DATA

'\
I

STATUS VALID

\
OE"

L

ADDRESS

ru
-

-

I

/

/

I
!

\

--\

ji"

'Z8218 only.
m iii 18 lor Z8116. 23
lor Z8218.

Figure 48. Memory Read Timing with External Walt Cycle

ADo-AD,.

jiTA'i'iiil

B/W
R/W

=0

OE"
'Z8218 only.

m =18 for Z8116, 23

ji"

HIGH

lor Z8218.

I

Figure 49. Memory Write Timing with External Walt Cycle
2259'()48, 049

389

ADo-AD 15

AU.-Am

STATUS
B/W
R/iii = 1

OE"

IE"
·Z8216 only.
m = 18 tor Z8116, 23 for Z8216.

Figure 50. Memory Read Timing with Internal Walt Cycle

Burst Memory Transactions. Burst memory transactions use multiple Data Strobes associated with a single
Address Strobe. The CPU uses burst transactions to
read four consecutive words in four data transactions.
The address of the first word read during a burst transaction has zeros in the three least significant bits. Control
bits in the Cache Control register indicate whether or not
portions of the memory system can support burst transactions.
The CPU uses burst mode reads only for fetching instructions. If an instruction is to be fetched from a location within a half of physical memory that supports burst
transactions, the CPU reads the eight bytes that contain
the first byte of the instruction. (EPA template fetches
and the RETI instruction do not use the burst
transaction.)
Timing for the first data transfer during a burst transaction is identical to that for a single memory read, including the automatic insertion of wait states, except
there are four T3 states. Subsequent data transfers do
not include automatic wait states. On the first data
transfer, if WAIT is sampled active then it is sampled
again every bus clock cycle until it is inactive, at which
time the data is read from the bus. Burst memory read
timing is shown in Figure 51.

390

Internal Operation and Halt Transactions. Two types
of bus transactions made by the CPU do not transfer
data: Internal Operations and Halt transactions. These
transactions look like a memory transaction, except that
DS remains High and no data is transferred.
For the Internal Operation transaction (Figure 52), the
Address lines contain arbitrary data when AS goes High.
The R/W line indicates Read (High) and the Status lines
indicate Internal Operation (0000).
A Halt transaction (Figure 53) is generated when the
CPU executes a Halt instruction or when a fatal sequence of traps and bus errors occurs. The address
placed on the AD lines is the location of the Halt instruction or the instruction that initiated the fatal sequence of
traps and errors. The Status lines indicate a Halt transaction (0011).
WAIT is not sampled during the Internal Operation or
Halt transaction.

ADO-AD16

DATA

DATA

ADDRESS

STATUS
B/W
R/W = 1

STATUS VALID

jE*
·Z8216 only.
m = 18 tor Z8116, 23 for Z8216.

Figure 51. Burst Memory Read Timing

ADo-AD,.

STATUS
B/W
R/W

=0
=1

IE·
·Z8216 only_
m = 18 for Z8116, 23 for Z8216.

Figure 52. Internal Operation Timing
2259-051, 052

391

ADO-AD1!

STATUS

B/W = 0

AlW =

1

OE:* *

iE* *

• Address of Halt Instruction.
uZ8216 only.
m = 18 for Z8116. 23 for Z8216.

Figure 53. Halt Timing
1/0 Transactions. I/O transactions (Figures 54 and 55)
move data to or from peripherals and are generated during the execution of 110 instructions. 110 transactions to
on-chip peripheral devices do not generate external bus
transactions.
I/O transactions are four bus cycles long at a minimum,
and they can be lengthened by the addition of wait
cycles either automatically generated as indicated in the
Bus Timing and Control register or generated by an external device. The extra clock cycles allow for slower
peripheral operation.
The status lines indicate that the access is an 110 transaction (0010). The 110 address is found on ADo-AD15 and
A1S-A23·

=

Byte data (BiW
High) is transmitted on ADo-AD7. This
allows peripheral devices to attach to only eight of the
AD lines. The Read/Write line (RiW) indicates the direction of the data transfer: peripheral-to-CPU (Read: RiW
High) or CPU-to-peripheral (Write: R/W
Low).

=

392

=

Interrupt Acknowledge Transactions. These transactions (Figure 56) acknowledge an interrupt and read an
identifier from the device that generated the interrupt. Interrupt Acknowledge transactions are generated
automatically by the hardware when an interrupt is
detected.
These transactions are five cycles long at a minimum,
with at least two automatic wait cycles, although others
can be added by programming the Bus Timing and Control register. The wait cycles are used to give the interrupt priority daisy chain (or other priority resolution
device) time to settie before the identifier is read.

~T1---+-r---T~I""---Tw--"·-I1"'4>-----T3-------1

I
ADO-AD15

A1e- Am

STATUS
BIW
RIW = 0

I

-K
-~
-

I

ADDRESS

I

DATA VALID

ADDRESS

STATUS VALID

/

WAIT

OE"

\

--\

ji"

·Z8216 only.
m = 18 for Z8116. 23 for Z8216.

HIGH

I
Figure 54. 1/0 Write Timing

I
ADO-AD,.

- K
-

-

STATUS
RIW

BlW
= 1

-

ADDRESS

I

1

I

,

,
I

~

'

ADDRESS

V
STATUS VALID

/
OE"

DATA

\

--\
·Z8216 only.
m 18 for Z8116, 23 for Z8216.

ji"

=

Figure 55. 110 Read Timing
2~.055

393

TW-------I.....--TW----+-f.--T3---./
-I-----TLAsr----.I-..--T1---.I..--T2-----f.-I
I
I
I
I
I
/
J

'\

UNDEFINED'

ADo-AD,.

I

}-~

DATA

'\

UNDEFINED

STATUS
B/W = 0
R/W = 1

STATUS VALID

/
OE**

\

/

\

\

/

'* AD1 and AD2 Indicate the type of interrupt being acknowledged.
** Z8216 only.

m=

18 for Z8116, 23 for Z8216.

Figure 56. Interrupt Acknowledge Timing
The Status lines identify the type of interrupt that is being
acknowledged. The possibilities are nonmaskable interrupt (0101) and the three external interrupt
acknowledges (0100, 0101 and 0111). No address is
generated; the contents of the bus are undefined when
AS rises. The Rm line indicates Read (High), and the
B/W line indicates Word (Low).
The only item of data transferred is the identifier that is
captured from the AD lines on the falling clock edge just
before OS is raised High. The length of time that OS is
asserted is identical with 110 timing programmed in the
Bus Timing and Control register.
There are two places where WAIT is sampled and thus a
wait cycle can be inserted by external devices. The first
place serves to delay the falling edge of OS to allow the
daisy chain a longer time to settle, and the second place
serves to delay the point at which data is read.

Refresh Transactions. A memory Refresh transaction
(Figure 57) is generated by the refresh mechanism and

394

can come immediately after the final clock cycle of any
other transaction. The memory refresh counter's 10-bit
address is output on the low order 10 bits of the bus during the first cycle of the transaction. The contents of the
rest of the bus are undefined. The Status lines indicate
Refresh (0001). This transaction can be used to generate
refreshes for dynamic RAMs. Refreshes may occur
while the CPU is in the Halt or Fatal state.

CPU· Extended Processing Unit Interaction
The Z800 CPU with a Z-BUS interface and PAUSE input
line (I.e., the Z8216) and one or more Extended Processing Units (EPUs) work together like a single CPU component, with the CPU providing address, status, and timing
signals and the EPU supplying and capturing data. The
EPU monitors the status and timing signals output by the
CPU so that it knows when to participate in a memory
transaction; for EPU to memory transfers, the CPU puts
its AD lines in 3-state while OS is Low, so that the EPU
can use them.

2259.056

ADo-ADlI

Ate-Am

AS
STATUS

n =0

R/W =

1

iii··

/1**
*10 lu,t..ignilicant bits are Refrelh addre••.

··Z82t8 only.
m • t810r Z8tt8. 23 lor Z82t8.

Figure 57. Memory Refresh Timing

In order to know which transaction it is to participate in,
the EPU must track the following sequence of events:
•

•

•

When the CPU fetches the first word of an EPA instruction template from memory (STs-STo = 1101),
the EPU must also capture the instruction returned
by the memory. The template has an 10 field that indicates whether or not the EPU is to execute the instruction. Because there is no alignment restriction
on EPA templates, the 10 field can not be in the first
word fetched.
The next non-refresh transaction by the CPU is the
fetching the second word of the instruction (STs-STo
= 1100). The EPU must also capture this word. If
the template is not aligned, a third fetch is made
(STa-STo = 1100).
If the instruction Involves a read or write to memory,
then transfers of data between memory and the EPU
(STa-STo = 1010) are the next non-refresh transactions performed by the CPU. The EPU must supply
the data (Write: RIW = Low) or capture the data
(Read: R/W = High) for each transaction, just as if it
were part of the CPU. In both cases, the CPU
3-states Its AD lines while data is being transferred
(OS Low).

•

If the instruction involves a transfer from the EPU to
the Z800 MPU, the next non-refresh transaction is
the CPU transferring data between the EPU and CPU
(STa-STo
1110).

=

In order to follow this sequence, an EPU has to monitor
the status lines to verify that the transaction it is monitoring on the bus was generated by the CPU. In a multiple
EPU system, there is no indication on the bus as to
which EPU is cooperating with the CPU at any given
time. This must be determined by the EPUs from the EPA
templates they capture.
When an EPU begins to execute an extended instruction,
the CPU can continue fetching and executing instructions. If the EPU wishes to halt the CPU from executing
another instruction or bus transaction, the EPU must activate the PAUSE line to stop the CPU until the EPU is
ready for subsequent CPU activity. This mechanism is
used to synchronize CPU-EPU activity.

EPU Transfer Transactions. These transactions
(Figures 58-60) move data between the CPU and an EPU,
thus allowing the CPU to transfer data to or from an EPU
or to read or write an EPU's status registers. They are
generated during the execution of the EPA instruction.

395

EPU-to-Memory transfers are five cycles unless extended by Wait Memory to EPU transfers are three cycles
unless extended by WAIT_
EPU-CPU transfer transactions have the same form as
110 transactions and thus are fou r clock cycles long,
unless extended by WAIT. Although AS is asserted, no
address is generated and the contents of the bus are
undefined; only one status code is used (1110).
In a multiple EPU system, the EPU that is to participate
in a transaction is selected implicitly by the ID code in
the EPU template, rather than by an address. The
Read/Write line (R/W
High) indicates the direction of
the data transfer into the CPU.

=

Requests
The Z800 MPU supports three types of request signal.
These are:
•

Interrupt requests, which another device initiates
and the CPU accepts and acknowledges.

•

Bus requests, which an external potential bus
master initiates and the CPU accepts and
acknowledges.

•

Global bus requests, which the CPU or on-chip DMA
initiates to acquire a global system bus.

When a request is made, it is answered according to its
type: for interrupt requests, an Interrupt Acknowledge
transaction is initiated by the CPU; for bus requests, an
acknowledge signal is sent; for global bus request, an
acknowledge signal is received.

Interrupt Requests. The Z800 MPU supports two types
of external interrupt, maskable and nonmaskable (NMI).
The Interrupt Request line of a device that is capable of
generating an interrupt may be tied to any of the interrupt pins. Several devices can be connected to one pin,
with the devices arranged in a priority daisy chain. The
CPU uses the same protocol for handling requests on
these pins. The sequence of events is given below:
Any High-to-Low transition on the NMI input is asynchronously edge-detected, and the internal NMI latch is
set. At the beginning of the last processor clock cycle of
any instruction, the interrupt inputs are sampled along
with the state of the internal NMI latch.
If a maskable interrupt is requested and the Master
Status register indicates that requests on that line are to
be accepted, or if the NMllatch is set, the next possible
bus transaction is an interrupt acknowledge transaction
that results in an identifier from the highest-priority interrupting device being read off the AD lines. This data is

ADo-AD1S

is
STATUS

alW

AIW = 1

OE·

iii·
·Z821S only.
m = 18 for Z811S. 23 for Z8216.

Figure 58. EPU to CPU Timing

396

2259-058

I
ADo-ADlI

STATUS
a/iii
R/iii = 0

0.·

-

-(

I

I

I
I

ADDRESS

"

EPU DATA VALID

"

I

ADDRESS

\..J

-

STATUS VALID = 1010

/

~

II·

\

HIGH

'Z8218 only.
m • 18 far Z81111 23 tor Z8218.

Figure 69, EPU Wrlta to Memory

I-+--T1----+-I------TI---------I.-...--T3--+1
DATA

ADDRESS

STATUS

Bliii

STATUS VALID

R/iii.1

·Z8218 only.
m • 1810. Z8118, 2310. Z8218.

II·
Figure 60. Memory to EPU Timing
2259-068, oeo

397

used to initiate the interrupt service routine. For a nonmaskable interrupt request in interrupt mode 0, 1, or 2,
an interrupt acknowledge transaction is not generated;
the hexidecimal constant 0066 is used to initiate the interrupt service routine.

Bus Requests. To generate transactions on the bus, a
potential external bus master (such as a DMA Controller)
must gain control of the bus by making a bus request. A
bus request is initiated by pulling BUSREQ Low. Several
bus requesters can be wire ORed to the BUSREQ pin;
priorities are resolved externally to the CPU, usually by a
priority daisy chain.
The asynchronous BUSREQ signal generates an internal
BUSREQ, which is synchronous. If the external BUSREQ
is Low at the beginning of any processor clock cycle, the
internal BUSREQ will cause the bus acknowledge line
(BUSACK) to be asserted after the current bus transaction is completed or after the write transaction of a TSET
instruction. The CPU then enters Bus Disconnect state
and gives up control of the bus. All Z800 Output pins except BUSACK are 3-stated.
The on-chip DMA channels have higher priority than the
off-chip devices requesting the external bus via
BUSREQ.

(de-asserted), the state of the Wait line is also noted: if
WAIT is asserted, then the contents of the AD lines on
the falling edge of the clock are used to program the content of the Bus Timing and I nitialization register, otherwise the constant 00 hexadecimal is used. If the hardware programming option is used, ADs is used to enable
the bootstrap via UART option.
After reset, the following control registers are initialized
as follows:
•

Program Counter, System Stack Painter, I, and R
registers initialized to 0

•

Master Status register-initialized to 0, e.g., system
mode of operation; Single-step mode, Breakpoint-anHalt and all maskable interrupts disabled

•

I/O Page register-I/O page 0 in use

•

Stack Limit register cleared

•

Refresh register-initialized to 88, e.g., refresh
enabled, rate
32 clock cycles

•

Cache Control register-initialized to 00, e.g. cache
enabled for program only (associative rather than
fixed location); also, all lines invalid

•

Memory Management Unit Master Control
register-initialized to 0, e.g., translation disabled

•

Trap Control register-initialized to 0, e.g., Stack
Warning disabled, EPA disabled, I/O not privileged

•

All peripheral control registers-peripheral disabled
(but see UART bootstrap option)

•

Interrupt Status register-Interrupt Mode 0

RESET
A hardware reset puts the Z800 MPU into a known state
and optionally initializes the Bus Timing and Initialization
control register of the Z800 MPU to a system specifiable
value. A reset begins at the end of any processor clock
cycle if the RESET line is Low. However, if a bus transaction is in progress it is allowed to be completed. A
system reset overrides all other operations of the chip,
including interrupts, traps and bus requests. A reset
should be used to initialize a system as part of the powerup sequence.
Within 128 processor clock cycles of the RESET line
becoming Low, the Z800 lines assume their reset values.
For either bus, the AD lines are 3·stated, and all control
outputs are forced High. While RESET is asserted, the
clock output is the processor clock frequency scaled by
four. RESET must be held low at least 128 processor
clock cycles.
The Reset line is sampled on the rising edge of the clock
output during reset. When the Reset line is sampled High

398

=

The following registers are unaffected:
•

CPU register file, including user Stack Pointer

•

Page Descriptor registers

•

Interrupt/Trap Vector Table Pointer register

On the rising edge of RESET, if Bus Request is asserted
the Z800 MPU will grant the bus before fetching the first
instruction from location O.
After RESET has returned to High, the CPU begins to
operate unless the Bootstrap UART feature is utilized.

PIN ASSIGNMENTS
The pin assignments of four versions of the Z8DD MPU,
the Z81D8, Z82D8, Z8116 and Z8216 are shown in
Figures 61·64 respectively.

A"

A..

A"

As
As

A"
A12
A,.
A"
A"
DMASTBo
HALT
DMASTB,

•••
As
As

WR

RFSH

RDY2

ROY,

WI!

AD,

RFSH

AD,

10RQ

AD,
RDYo

OND

A"
AD,

IE
M1

ADe
AD,

MREQ

ADo
TX

iili

AD,

CYINo

AD,

AS

MREQ

ADo
AD,

XTAL,

ADo

XTAL1

iNfA

lITAl,

NMI
BUSREQ

RESET

• 6'

Figure 61. Z8108 Pin Assignments

XTALo

elK
C1103

CliNt

ADo

OOA
NMl
BUSREQ

Ma

WAIT

RESET

CT1Na

INTc

BUSACK

CTIO,

PAUSE

+5 •

Figure 62. Z8208 Pin Assignments

A"

+5.

AD'0

A"

A"
AD'1

A"
AD,

A23

AD,

AD'2

ROV3

AD13

A18

AD,.

A"

AD'5

A"

DMASTBo

OIW
DMASTB,

.5'

RX
AD.

CTIOo

M1

RDY2

AD,
ROY,

RiIY

AD,

STo

AD,

ST,

AD,

AD'0
AD'1

AD,

AD'2

AD,
A18
A17

O!!

ROYo

AD'3

.ND

GND

A18
Ao,

ST,

AD,.
AD,S

oilY
RiW

AD,
AD,

IE

ST,
CTIOo

STo
ST,

AD,

OND

OND

ST,

AD,
AD,

XTALl

DS

AD,

XlAl,

AS

ADo

ST,

XTAl1
XTALo
elK
WAIT
BUSACK

-

OS
CllNo

AS

elK

RX
AD,
ADo
TX
AD,
CTlN,

ADo

iNfA
NMi
BUSREQ

008

iNfA

C1103

NMl

WAIT

RESET

CTlNa

lNfc

RESET

.5'

Figure 63. Z8116 Pin Assignments
2259-061, 082, 063, 064

A18
AD,

A17

AD,

WAIT

A17

.ND

.ND

BUSACK

ROVa

A18

A18

OND

elK

A18

O!!

IORQ

iili
AS

.5.

A"
A,.

BUSACK

CTlO,

PAUSE

+5'

Figure 64. Z8216 Pin Assignments

399

Z8000
Family

Zilog

Zilog Z8000® Family
A Bigh·Pedormaace 16-Bil Archileclure
With 32·Bil Nipalloa ia Niad
March 1985

A Complete Solution. Continuing
the family concept so successfully
introduced by Its 8·bit Z80 CPU,
Zilog devised the Z8000 Family of
16·bit parts. As you would expect
from Zilog, this family provides much
more than an extension of 8-bit architecture: the Z8000 Family lets you
deSign advanced concepts from the
mainframe and minicomputer worlds
into microcomputer systems.
And because the Z8000 Family
was built around a unifying set of
protocols and interconnections,
present and future family members
are entirely compatible. Your system
can grow as your applications mature or expand. A whole range of
functions have been planned for
from the beginning; the growing
family now includes parts to provide
memory management, DMA transfer, and extended processing.
System Flexibility. Even the smallest Z8000 systems offer high
throughput and easy programming
far superior to any existing microprocessor alternative. In mid-range
applications, Z8000 components
offer very powerful solutions to the
design problems of word processing, intelligent terminals, data communications, instrumentation, and
process control. In a complex network of multiple processors, smart
peripheral components, and a distributed memory configuration, the
Z8000 Family provides performance
and versatility exceeding that of
much larger-and far more
expensive-minicomputers.

Higher Throughput, Reduced
Cost. The powerful instruction set,
high execution speed, regular architecture, and numerous special features of the Z8000 microprocessors
dramatically increase system
throughput. Intelligent Z8000 peripheral controllers and extended processing units unburden the CPU
and boost throughput even further.
Simply put, the Z8000 Family
offers more for less money. The
Z8000 microprocessors give midrange minicomputer performance at
microprocessor cost. At component
prices, Z8000 peripheral controllers
perform complex system functions
that previously required an entire PC
board.
The Z8000 Family is designed for
multiple-processor operation-an
economical way of greatly increasing
system performance. Many special
features for multiple Z8000 CPUs
facilitate the design of multipleprocessor systems that share access
to a common memory. The Memory
Management Units can dynamically
relocate code and protect memory
areas. The Z8090/4 Z-UPC Universal
Peripheral Controller, a complete
slave microcomputer, can manipulate data off-line. Asynchronous
parts of multiple-processor systems
can be joined by the Z8038 Z-FIO
FIFO Interface Unit.
A Z8000-based system can also
include Zilog's Z8070 FPU Floating
Point Unit for high-speed, highly
accurate floating-point processing.

The Z8000's Extended Processing
Architecture (EPA) makes it easy to
add the FPU, and Zilog prOVides a
software simulation of the FPU for
system development.
An Unmatched CPU. The Z8000
microprocessor is not just a wider
data path, more registers, more data
types, more addressing modes,
more instructions, and more addressing space. It brings bigmachine concepts to the level of
components. Its general-register
architecture avoids bottlenecks
associated with dedicated or implied
registers. Special features support
parallel processors, operating systems, compilers, and the implementation of virtual memory.
The Z8000 CPU is also a very fast
machine. Its throughput is greater
than that of any other 16-bit microprocessor with comparable clock
speeds. And the Z8000 CPU is
available with speeds ranging from a
moderate 4 MHz clock rate that
allows you the choice of slowaccess, low-cost memories to a
high-speed 10 MHz clock rate for
high-performance systems. From
the four versions of the Z8000 microprocessors, you can select the one
best suited to YGur needs: the Z8001
for large memory applications, the
Z8002 for small memory applications, the Z8003 for virtual memory,
or the Z8004 for multiprocessors
sharing a common, small memory.

403

How to Manage Your Memory
Better. Trends are increasingly
toward systems with multiple users,
complex programs, security requirements, and continuously expanding
memory requirements. These design
problems pose questions not sufficiently answered by other microprocessor families.
Exemplifying the Z-Family commitment to advanced architecture, the
Z8010 Memory Management Unit
(Z-MMU) and the Z8015 Paged
Virtual Memory Management Unit
(Z-PMMU) both provide flexibility in
code segmenter page relocation
and sophistication in memory protection rarely found in the microprocessor world. These devices
encourage modular software
development-a critical factor as
programs reach new levels of
complexity.
You are free from specifying where
information is actually located in
physical memory because the
Z-MMU and Z-PMMU make software
addresses totally independent from
the actual physical memory address.
While some microprocessor CPUs
do have internal CPU relocation
registers, they are dedicated and
support few segments. These CPUs
also restrict memory protection. Not
true for the Z-MMU or Z-PMMU.
Various configurations of these devices can randomly relocate all 128
segments output by the Z8000 CPU
in any of its available memory
systems.

404

For even more sophisticated memory management, the Z8000 microprocessors include a new member
that supports virtual memory via an
instruction abort mechanism. The
Z8003 Virtual Memory Processing
Unit (Z-VMPU) can implement either
segmented virtual memory that
allows demand swapping of segments, or a paged virtual memory in
which the unit of memory allocation
is a page within a segment.
But the memory management
units are more than relocation devices. They offer you a host of memory protection features that allow the
system to protect its software from
unwanted uses and users. Segments
or pages can be specified as readonly to protect them from being
overwritten, as system-only to protect
the operating system from inadvertent user access, as execute-only,
and so on. A write warning zone is
especially useful in stack operations
so the operating system can deal
with growing stacks.

Peripheral Problem Solvers.
Z8000 peripheral components are
not dumb 1/0 circuits. They perform
intelligent, complicated tasks on
their own. They unburden the CPU,
reduce bus traffic, and increase
system throughput. Complex system
tasks that previously required burdensome conglomerations of MSI
can now be handled off-line by
Z-BUS peripherals with little CPU
overhead. Multifunction Z-BUS
peripherals are extensively programmable, so each can be
precisely tailored to its application.

Counting, timing, and parallel 110
problems seem less tiresome with
the Z8036 Z-CIO Counter and Parallei 1/0 device. It has three 16-bit
counterltimers, and three 1/0 ports.
It can even double as a programmable interrupt-priority controller.
Data communications are neatly
handled by the Z8030 Z-SCC Serial
Communication Controller and the
Z8033 Z-ASCC Asynchronous Serial
Communications Controller, dualchannel multi-protocol components
that between them, support all popular communications formats. Direct
memory access is amply supported
by the Z8016 Z-DTC DMA Transfer
Controller, a fast dual-channel device
that enhances the addressing power
of the Z8000 CPU in stand-alone or
parallel-processor environments.
General-purpose control and datamanipulation problems are smoothly
solved by the Z8094 Z-UPC Universal Peripheral Controller, a complete
off-line microcomputer-on-a-chip
with three 1/0 ports. This processor
executes the same friendly, capable
instruction set as our Z8 Microcomputer. Bits and pieces of asynchronous parallel-processing systems are
interconnected by the Z8038 Z-FIO
FIFO Input/Output, a surprisingly
flexible device that can interface any
major microprocessor and most
peripherals to the Z-BUS. Its buffer
depth can be expanded without limit
using the Z8060 Z-FIFO.
If encryption or decryption of data
is necessary, the Z8068 Data Ciphering Processor (Z-DCP) supports
three standard Ciphering options
and key parity check. It can also
input, output, and encipher simultaneously.

Z800 1/2 Z8000® CPU
Central Processing Unit

Zilog

Product
Specification

April19a5

FEATURES
• Regular, easy-to-use architecture
•

Instruction set more powerful than many minicomputers

•

Directly addresses a Mbytes

• Eight user-selectable addressing modes
• Seven data types that range from bits to 32-bit long words
and byte and word strings
• System and Normal operating modes
• Separate code, data, and stack spaces
• Sophisticated interrupt structure

•

Resource-shaping
systems

capabilities for

•

Multi-programming support

multiprocessing

• Compiler support
•

Memory management and protection provided by
Za010 Memory Management Unit

• 32-bit operations, including signed multiply and divide
• Z-BUS compatible
•

4, 6, and 10M Hz clock rate

GENERAL DESCRIPTION
The zaooo is an advanced high-end 16-bit microprocessor
that spans a wide variety of applications ranging from simple
stand-alone computers to complex parallel-processing
systems. Essentially a monolithic minicomputer central
processing unit, the zaooo CPU is characterized by an
instruction set more powerful than many minicomputers;
abundant resources in registers, data types, addressing
modes and addressing range, and a regular architecture
that enhances throughput by avoiding critical bottlenecks
such as implied or dedicated registers.
CPU resources include sixteen 16-bit general-purpose
registers, seven data types that range from bits to 32-bit long
words and byte and word strings, and eight user-selectable
addressing modes. The 110 distinct instruction types can
be combined with the various data types and addressing
modes to form a powerful set of 414 instructions. Moreover,
the instruction set is regular; most instructions can use any
ofthe five main addressing modes and can operate on byte,
word, and long-word data types.
The CPU can operate in either the system or normal mode.
The distinction between these two modes permits privileged
operations, thereby improving operating system
organization and implementation. Multiprogramming is
supported by the "atomic" Test and Set instruction;
multiprocessing by a combination of instruction and

AS
BUS{
TIMING

~

fltml
READIWlfITE

AD11

NORMAL/mT!M
BYTElWORD

...ro.!

ADDRESS I
DATA BUS

zaOO1
Z800~

CPU

T~\'l

SEGMENT:
NUMBER I

INTERRUPTS{

I
I
I

MULTI-MICRO {
CONTROL

I

+5 V GND eLK

RESET

Figure 1. Z8000 CPU Pin Functions

405

hardware features; and compilers by multiple stacks,
special instructions, and addressing modes.
The Z8000 CPU is offered in two versions: the Z8001 48-pin
segmented CPU and the Z8002 40-pin nonsegmented
CPU (Figure 1). The main difference between the two is in
addressing range. The Z8001 can directly address 8
megabytes of memory; the Z8002 directly addresses 64
kilobytes. The two operating modes-system and normaland the distinction between code, data, and stack spaces
within each mode allows memory extension up to 48
megabytes for the Z8001 and 384 kilobytes for the Z8002.
To meet the requirements of complex, memory-intensive
applications, a companion memory-management device is

offered for the Z8001. The Z8010 Memory Management
Unit manages the large address space by providing
features such as segment relocation and memory
protection. The Z8001 can be used with or without the
Z8010. If used by itself, the Z8001 still provides an 8
megabyte direct addressing range, extendable to 48
megabytes.
The Z8001, Z8002, and Z8010 are fabricated with
high-density, high-performance scaled n-channel silicongate depletion-load technology, and are housed in
dual-in-line packages (DIPs) and lead less chip carriers
(LCG).

REGISTER ORGANIZATION
The Z8000 CPU is a register-oriented machine that offers
sixteen 16-bit general-purpose registers and a set of special
system registers. All general-purpose registers can be used
as accumulators and all but one as index registers or
memory pointers.
Register flexibility is created by grouping and overlapping

{

RRO

RO 17

RHO

Rl

RHI

RLI

RHZ

RL2

RH3

RL3

RH4

RL4

RH5

RL5

RH6

RU

15

01 7

RLO

multiple registers (Figures 2 and 3). For byte operations, the
first eight 16-bit registers (RO ... R7) are treated as sixteen
8-bit registers (RLO, RHO ... , RL7, .RH7). The sixteen 16-bit
registers are grouped in pairs (RRO ... RR14) to form 32-bit
long-word registers. Similarly, the register set is grouped in
quadruples (ROO ... R012) to form 64-bit registers.

01
RRO

{

Rol7

RHO

RillS

RHI

RU

Rzi

RHZ

RU

R31

RH3

RU

RLO

17

01
ROO

ROO
RRZ r z
R3

{

RR4

RRZ {

R4

r

RR6

{

R6

RH7

RL7

RU

. R7 1

RH7

RL7

R91

RR10

r'

RR1Z

R13

r

RQI

1o1
Rill

{ Rlzl
R131

1 .w
R14

R15'

SYSTEM STACK POINTER (SEG. NO.1
NORMAL STACK POINTER (SEG. NO.)
SYSTEM STACK POINTER (OFFSET)
NORMAL STACK POINTER (OFFSET)

Figure 2. Z8001 General-Purpose Registers

406

RHa

RR8 {

{ RIO

R15

Rei

R6115

15

Rll

RR14

RLS
RQ4

R06

RR1'

RL4

RHS

RRe {

R9

RR10

RH4

R04

e
R7

RR8

R41
Rsl

RR4 {

R5

ROIl

R012
RR14

r141
R15'
R151

I

SYSTEM STACK POINTER
NORMAL STACK POINTER

r-1

Figure 3. Z8002 General-Purpose Registers

STACKS
The Z8001 and Z8002 can use stacks located anywhere in
memory. Call and Return instructions as well as interrupts
and traps use implied stacks. The distinction between
normal and system stacks separates system information
from the application program information. Two stack
pointers are available: the system stack pointer and the
normal stack pointer. Because they are part of the
general-purpose register group, the user can manipulate

the stack pointers with any instruction available for register
operations.
In the Z8001, register pair RR14 is the implied stack pointer.
Register R14 contains the 7-bit segment number and R15
contains the 16-bit offset. In the Z8002, register R15 is the
implied 16-bit stack pointer.

REFRESH
The Z8000 CPU contains a counter that can be used to
automatically refresh dynamic memory. The refresh counter
register consists of a 9-bit row counter, a 6-bit rate counter,
and an enable bit (Figure 4). The 9-bit row counter can
address up to 256 rows and is incremented by two each
time the rate counter reaches end-of-count. The rate counter
determines the time between successive refreshes. It
consists of a programmable 6-bit modulo-n prescaler (n = 1
to 64), driven at one-fourth the CPU clock rate. The refresh

period can be programmed by 1 to 64 /.Is with a 4 MHz
clock. Refresh can be disabled by programming the refresh
enable/disable bit.

I...

ROW

RATE

I

!

!

I

!

N
n

Figure 4. Refresh Counter

::

PROGRAM STATUS INFORMATION
This group of status registers contains the program counter,
flags, and control bits. When an interrupt or trap occurs, the
entire group is saved and a new program status group is
loaded.
Figure 5 illustrates how the program status groups of the
Z8001 and Z8002 differ. In the nonsegmented Z8002, the
program status group consists of two words: the program
counter (PC), and the flag and control word (FCW). In the
segmented Z8001, the program status group consists of

I
I

four words: a two-word program counter, the flag and
control word, and an unused word reserved for future use.
Seven bits of the first PC word designate one of the 128
memory segments. The second word supplies the 16-bit
offset that designates a memory location within the
segment.
With the exception of the segment enable bit in the Z8001
program status group, the flags and control bits are the
same for both CPUs.

AESEFIVED
WORD

ISE++++~I

I' I

'I'

SEGMENT NUMBER

I

I

I

I '

I c I z I SI I I HI, I '
PN

DA

I

I 'I ' I ' I ' I ' I ' I ' I '

II

FLAG AND

I

CONTROL
WOAD

ADDRESS

................................-'-......L.....J.I...J.I......JI_L....-I.-J.......L.....I.-...J...I....I

PROGRAM
COUNTER

28002 Program Status RegIsters

2800 I Program Status RegIsters

1 'I

0

10 10 1

1

,
01

1 'I

0

1 0 1 0 1 0 1 'I 'I

,I

,.

1,1
1

SEGMENT NUMBER

1

1

1

UPPER OFFSET

1

1

1

0

1

0

1

0

j'

UPPER POINTER

I

I

I

28002 Program Status Area Pomter

28001 Program Status Area Pomter

Figure 5. Z8000 CPU Special Registers

407
-------------

INTERRUPT AND TRAP STRUCTURE
The Z8000 provides a very flexible and powerful interrupt
and trap structure. Interrupts are external asynchronous
events requiring CPU attention, and are generally triggered
by peripherals needing service. Traps are synchronous
events resulting from the execution of certain instructions.
Both are processed in a similar manner by the CPU.
The CPU supports three types of interrupts (non-maskable,
vectored, and non-vectored) and four traps [system call,
Extended Process Architecture (EPA) instruction, privileged
instructions, and segmentation trap]. The vectored and
non-vectored interrupts are maskable. Of the four traps, the
only external one is the segmentation trap, which is
generated by the Z801 O.
The remaining traps occur when instructions limited to the
system mode are used in the normal mode, or as a result of
the System Call instruction, or for an EPA instruction. The

descending order of priority for traps and interrupts is:
internal traps, nonmaskable interrupt, segmentation trap,
vectored interrupt, and non-vectored interrupt.
When an interrupt or trap occurs, the current program status
is automatically pushed on the system stack. The program
status consists of the processor status (PC and FCW) plus a
16-bit identifier. The identifier contains the reason or source
of the trap or interrupt. For internal traps, the identifier is the
first word of the trapped instruction. For external traps or
interrupts, the identifier is the vector on the data bus read by
the CPU during the interrupt-acknowledge or trapacknowledge cycle.
After saving the current program status, the new program
status is automatically loaded from the program status area
in system memory. This area is designated by the program
status area pointer (PSAP).

DATA TYPES
Z8000 instructions can operate on bits, BCD digits (4 bits),
bytes (8 bits), words (16 bits), long words (32 bits), and byte
strings and word strings (up to 64 kilobytes long). Bits can be
set, reset, and tested; digits are used in BCD arithmetic
operations; bytes are used for characters or small integer
values; words are used for integer values, instructions and
nonsegmented addresses; long words are used for long
integer values and segmented addresses. All data elements

except strings can reside either in registers or memory.
Strings are stored in memory only.
The basic data element is the byte. The number of bytes
used when manipulating a data element is either implied by
the operation or-for strings and multiple register
operations-explicitly specified in the instruction.

SEGMENTATION AND MEMORY
MANAGEMENT
High-level languages, sophisticated operating systems,
large programs and data bases, and decreasing memory
prices are all accelerating the trend toward larger memory
requirements in microcomputer systems. The Z8001 meets
this requirement with an eight megabyte addressing space.
This large address space is directly accessed by the CPU
using a segmented addressing scheme and can be
managed by the Z801 0 Memory Management Unit.

8 7
LOGICAL ADDRESS

L----r.,.....--'

OFFSET

IMEMORY-----MANAGMENT
UNIT
BASE
ADDRESS
REGISTER
FILE

Segmented Addressing
A segmented addressing space-compared with linear
addressing-is closer to the way a programmer uses
memory because each procedure and data space resides
in its own segment. The 8 megabytes of Z8001 addressing
space is divided into 128 relocatable segments up to 64
kilobytes each. A 23-bit segmented address uses a 7-bit
segment address to point to the segment, and a 16-bit offset
to address any location relative to the beginning of the
segment. The two parts of the segmented address may be
manipulated separately. The segmented Z8001 can run any
code written for the nonsegmented Z8002 in anyone of its
128 segments, provided it is set to the nonsegmented
mode.

408

24-BIT PHYSICAL ADDRESS

L ________ _

__...1

Figure 6. Loglcal-to-Physlcal Address
Thlnslatlon

In hardware, segmented addresses are contained in a
register pair or long-word memory location. The segment
number and offset can be manipulated separately or
together by all the available word and long-word operations.
When contained in an instruction, a segmented address has
two different representations: long offset and short offset.
The long offset occupies two words, whereas the short offset
requires only one and combines in one word the 7-bit
segment number with an 8-bit offset (range 0-256). The
short offset mode allows very dense encoding of addresses
and minimizes the need for long addresses required by
direct accessing of this large address space.

where information is actually located in the physical
memory.
The relocation process is transparent to user software. A
translation table in the Memory Management Unit
associates the 7-bit segment number with the base address
of the physical memory segment. The 16-bit offset is added
to the physical base address to obtain the actual physical
address. The system may dynamically reload translation
tables as tasks are created, suspended, or changed.

Memory Management

In addition to supporting dynamic segment relocation, the
Memory Management Unit also provides segment
protection and other segment management features. The
protection features prevent illegal uses of segments, such as
writing into a write-protected zone.

The addresses manipulated by the programmer, used by
instructions and output by the Z8001, are called logical
addresses. The Memory Management Unit takes the logical
addresses and transforms them into the physical addresses
required for accessing the memory (Figure 6). This address
transformation process is called relocation. Segment
relocation makes user software addresses independent of
the physical memory so the user is freed from specifying

Each Memory Management Unit stores 64 segment entries
that consist of the segment base address, its attributes, size,
and status. Segments are variable in size from 256 bytes to
64 kilobytes in increments of 256 bytes. Pairs of
Management Units support the 128 segment numbers
available for each of the six CPU address spaces. Within an
address space, several Management Units can be used to
create multiple translation tables.

EXTENDED PROCESSING ARCHITECTURE
The Zilog Extended Processing Architecture (EPA) provides
an extremely flexible and modular approach to expanding
both the hardware and software capabilities of the Z8000
CPU. Features of the EPA include:
• Specialized instructions for external processors or
software traps may be added to CPU instruction set.
• Increases throughput of the system by using up to four
specialized external processors in parallel with the CPU.
•

Permits modular design of Z8000-based systems.

• Provides easy management of multiple microprocessor
configurations via "single instruction stream"
communication.
• Simple interconnection between extended processing
units and Z8000 CPU requires no additional external
supporting logic.
II Supports debugging of suspect ho.rdwarc ogoinst

proven software.
• Standard features on all Zilog Z8000 CPUs.
Specific benefits include:
• EPUs can be added as the system grows and as EPUs
with specialized functions are developed.
• Control of EPUs is accomplished via a "single instruction
stream" in the Z8000 CPU, eliminating many significant
system software and bus contention management
obstacles that occur in other multiprocessor (e.g.,
master-slave) organization schemes.

The processing power of the Zilog Z8000 16-bit
microprocessor can be boosted beyond its intrinsic
capability by Extended Processing Architecture. Simply
stated, EPA allows the Z8000 CPU to accommodate up to
four Extended Processing Units (EPUs), which perform
specialized functions in parallel with the CPU's main
instruction execution stream (Figure 7).
The use of extended processors to boost the main CPU's
performance capability has been proven with large
mainframe computers and minicomputers. In these
systems, specialized functions such as array processing,
special inputloutput processing, and data communications
processing are typically assigned to extended processor
hardware. These extended processors are complex
computers in their own right.
The Zilog Extended Processing Architecture combines the
best concepts of these proven performance boosters with
the latest in high·density MOS integrated-circuit design. The
result is an elegant expansion of design capability-a
powerful microprocessor architecture capable of
connecting single-chip EPUs that permits very effective
parallel processing and makes for a smoothly integrated
instruction stream from the Z8000 programmer's point of
view. A typical addition to the cu rrent Z8000 instruction set is
a set of Floating Point Instructions.
The Extended Processing Units connect directly to the
Z8000 Bus (Z-BUS) and continuously monitor the CPU
instruction stream. When an extended instruction is
detected, the appropriate EPU responds, obtaining or

409

placing data or status information on the Z-BUS using the
Z8000-generated control signals and performing its
function as directed.
The Z8000 CPU is responsible for instructing the EPU and
delivering operands and data to it. The EPU recognizes
instructions intended for it and executes them, using data
supplied with the instruction and/or data within its internal
registers. There are four classes of EPU instructions:
•

Data transfers between main memory and EPU registers

•

Data transfers between CPU registers and EPU registers

• EPU internal operations
• Status transfers between the EPUs and the Z8000 CPU
Flag and Control Word register (FCW)
Four Z8000 addressing modes may be utilized with
transfers between EPU registers and the CPU and main
memory:
• Register
•

Indirect Register

•

Direct Address

•

Index

In addition to the hardware-implemented capabilities of the
Extended Processing Architecture, there is an extended
instruction trap mechanism to permit software simulation of
EPU functions. A control bit in the Z8000 FCW register
indicates whether actual EPUs are present or not. If not,
when an extended instruction is detected, the Z8000 traps
on the instruction, so that a software "trap handler" can
emulate the desired EPU function-a very useful

development tool. The EPA software trap
the debugging of suspect hardware
software. This feature will increase in
designers become familiar with the EPA
Z8000 CPU.

routine supports
against proven
significance as
capability of the

This software trap mechanism facilitates the design of
systems for later addition of EPUs: initially, the extended
function is executed as a trap subroutine; when the EPU is
finally attached, the trap subroutine is eliminated and the
EPA control bit is set. Application software is unaware of the
change.
Extended Processing Architecture also offers protection
against extended instruction overlapping. Each EPU
connects to the Z8000 CPU via the STOP line so that if an
EPU is requested to perform a second extended instruction
function before it has completed the previous one, it can put
the CPU into the Stop/Refresh state until execution of the
previous extended instruction is complete.
EPA and CPU instruction execution are shown in Figure 8.
The CPU begins operation by fetching an instruction and
determining whether it is a CPU or an EPU command. The
EPU meanwhile monitors the Z-BUS for its own instructions.
If the CPU encounters an EPU command, it checks to see
whether an EPU is present; if not, the EPU may be simulated
by an EPU instruction trap software routine; if an EPU is
present, the necessary data and/or address is placed on the
Z-BUS. If the EPU is free when the instruction and data for it
appear, the extended instruction is executed. If the EPU is
still processing a previous instruction, it activates the CPU's
STOP line to lock the CPU off at the Z-BUS until execution is
complete. After the instruction is finished, the EPU
deactivates the STOP line and CPU transactions continue.

STOP LINE

DEDICATED

EPU
MEMORY

PERIPHERAL

PERIPHERAL

MEMORY

Figure 7. 1Ypical Extended Processor Configuration

410

CPU
IDLES IN
STOPI
REFRESH
STATE

r-----o~1

MONITOR Z·BUS
INSTRUCTION
STREAM

FETCH
NEXT
INSTRUCTION

r---------------~

I

CPU GENERATES

I

AND

>-,Y.=:ES~I-I DATA/ADDRESS

~~:~:S ON

EPU
EXECUTES
INSTRUCTION

L

CPU
EXECUTES
INSTRUCTION

I

I

I
I

I

___________ _

I
___ ..J
SET STOP
LINE AT CPU
UNTIL EPU
FREE

EPA TRAP
SERVICE
ROUTINE

&. DATA OR ADDRESSES ARE PLACED ON THE BUS AND USED BY THE EPU IN THE
EXECUTION OF AN INSTRUCTION.

Figure S. EPA and ZSOOO CPU Instruction Execution

INPUT/OUTPUT
A set of 1/0 instructions performs 8-bit or 16-bit transfers
between the CPU and 1/0 devices. 1/0 devices are
addressed with a 16-bit 1/0 port address. The 1/0 port
address is similar to a memory address; however, 1/0
address space need not be part of the memory address
space. 110 port and memory addresses coexist on the same
bus lines and they are distinguished by the status outputs.

Two types of 1/0 instructions are available: standard and
special. Each has its own address space. The 1/0
instructions include a comprehensive set of In, Out, and
Block 110 instructions for both bytes and words. Special 1/0
instructions are used for loading and unloading the Memory
Management Unit. The status information distinguishes
between standard and special 1/0 references.

MULTI·MICROPROCESSOR SUPPORT
Multi-microprocessor systems are supported in hardware
and software. A pair of CPU pins is used in conjunction with
certain instructions to coordinate multiple microprocessors.
The Multi-Micro Out pin issues a request for the resource,
while the Multi-Micro In pin is used to recognize the state of
the resource. Thus, any CPU in a multiple microprocessor
system can exclude all other asynchronous CPUs from a
critical shared resource.

Multi-microprocessor systems are supported in software by
the instructions Multi-Micro Request, Test Multi-Micro In, Set
Multi-Micro Out, and Reset Multi-Micro Out. In addition, the
eight megabyte CPU address space is beneficial in multiple
microprocessor systems that have large memory
requirements.

411

ADDRESSING MODES

zaooo

The information included in
instructions consists of
the function to be performed, the type and size of data
elements to be manipulated, and the location of the data
elements. Locations are designated by register addresses,
memory addresses, or I/O addresses. The addressing
mode of a given instruction defines the address space it
references and the method used to compute the address
itself. Addressing modes are explicitly specified or implied
by the instruction.

Addressing Mode

Figure 9 illustrates the eight addressing modes: Register
(R), Immediate (1M), Indirect Register (IR), Direct Address
(DA), Index (X), Relative Address (RA), Base Address (BA),
and Base Index (BX). In general, an addressing mode
explicitly specifies either register address space or memory
address space. Program memory address space and 1/0
address space are usually implied by the instruction.

Operand Addressing
In the Instruction

Operand Value

In a Register

InN.mory

R
Register

I

Immediate

I

OPERAND

Indirect
Register

I

REGISTER ADDRESS

REGISTER ADDRESS

The content 01 the

~

register

1M

I

In the instruction

"IR
~r-------;·~I~~OP:!E.'::RA~N~DJ

The content 01 the location
whose address Is in the
register

DA
.~

Direct
Address
"X

The content of the location whose address is the
address in the instruction
plus the content 01 the
working register.

Index

RA
Relative
Address

The content 01 the location
whose address is in the
instruction

PCYALUE

~

[~DIS~P~LA~C~EM~E!N~TJ--=====~~0--1

OPERAND

I

"BA

The content 01 the location
who.e addre.s is the
content of the program
counter. oUset by the
displacement in the
instruction
The content 01 the location
whose address is the

Base
Address

address in the register.
oUset by the displacement
in the instruction

"BX
Base
Index

I

• Do not use RO or RRO as mdIrect, mdex, or base regIsters.

Figure 9. Addressing Modes

412

OPERAND

I

The content 01 the location whose address is
the address in a register

plus the index value in
another register .

INSTRUCTION SET SUMMARY
The ZaDDD provides the following types of instructions:

•

Bit Manipulation

•

Load and Exchange

•

Rotate and Shift

•

Arithmetic

•

Block Transfer and String Manipulation

•

Logical

•

Input/Output

•

Program Control

•

CPU Control

LOAD AND EXCHANGE

Mnemonics

Operands

CLR
CLRB

EX
EXB

LO
LOB
LOL

LO
LOB
LOL

LO
LOB

LOA

LOAR

dst

R, src

R, src

Addr.
Modes

dst, 1M

R, src

R, src

Operation

7

7

7

8
11

8
12

dst ..... O

12

12

8
14
15

R

6

6
12

Exchange

IR

6
12

DA
X

15
16

R
1M

I...-

Clear

R
IR
DA
X

N

Q

R-src

12
16
16

18
19

3
7

3

3

5

7

11

DA
X

9
10

10
10

7
12

11
12
13

BA

14

14

13
14

11
13
13

17

17

16
17

BX

14

14

14

17

17

17

IR
DA
X

8
11
12

8
12
12

8
14
15

11
14
15

11
15
15

11
17
18

BA

14

14

14

17

17

17

BX

14

14

14

17

17

11

IR
DA

11
14

11
15

11
17

X

15

15

18

DA

12

13

15

Load Address

X
BA

13
15

13
15

16
15

R ..... source address

BX

15

15

15

RA

15

15

15

1M
IR

dst, R

Clock Cycles·
Word, Byte
Long Word
NS
SL
NS
SS
SL
SS

7
5 (byte only)
7
7

5
11

5
11

CI

Load Into Register
R ..... src

11
15

Load into Memory (Store)
dst ..... R

Load Immediate Into Memory
dst ..... IM

Load Address Relative
R ..... source address

LOK

R, src

1M

5

5

5

Load Constant
R ..... n (n

LOM

• NS - Non-segmented

R, src, n

IR

11

11

DA

14

15

X

15

15

SS - Segmented Short Offset

+ 3n
+ 3n
18 + 3n

= 0 ... 15)

11

Load Multiple

17

R +- src (n consecutive words)
(n

= 1... 16)

SL - Segmented Long Offset

413
-----

-----~~---~----

LOAD AND EXCHANGE (Continued)

Mnemonics
LOM

Operands
dst. R, n

LOR
LORB
LORL

R, src

LOR
LORB
LORL

dst, R

POP
POPL

dst,IR

PUSH
PUSHL

Addr.
Modes

Clock Cycles"
Word, Byte
Long Word
NS
SL
NS
SS
SS
SL

Operation
Load Multiple (Store Multiple)

IR

11

11

11 + 3n

DA

14

15

17 + 3n

dst - R (n consecutive words)

X

15

15

18 + 3n

(n

RA

14

14

14

17

17

17

= 1... 16)

Load Relative
R +- src
(range - 32768 ... + 32767)

RA

14

14

14

17

17

17

Load Relative (Store Relative)
dst - R
(range - 32768 ... + 32767)

IR, src

R

8

12

12

12

Pop

12

8
12

8

IR

12

19

19

19

dst+-IR

DA

16

16

18

23

23

25

Autoincrement contents of R

X

16

16

19

23

23

26

R

9

9

9

12

12

12

Push

1M

12

12

19

19

19

Autodecrement contents of R

IR

12
13

13

13

20

20

20

IR -src

DA

14

14

16

21

21

23

X

14

14

17

21

21

24

R

5

5

5

ARITHMETIC
AOC
AOCB

R, src

ADD
AOOB
AOOL

R, src

CP
CPB
CPL

CP
CPB

DAB
DEC
OECB

*NS

414

= Non-segmented

Add with Cerry
R - R + src + carry

R, src

dst, 1M

dst
dst, n

SS

R

4

4

4

8

8

8

1M
IR

7
7

7

14

7

7
7

14
14

14
14

14

DA

9

10

12

15

16

18

X

10

10

13

16

16

19

R

4

4

4

8

8

8

1M

7

7

14
14

14

14

IR

7

7

7
7

14

14

DA

9

10

12

15

16

18

X

10

10

13

16

16

19

Add
R-R+src

Compare with Register
R - src

IR

11

11

11

Compare with Immediate

DA

14

15

17

dst - 1M

X

15

15

18

R

5

5

5

Decimal AdJust
Decremented by n

R

4

4

4

IR

11

11

11

dst -dst - n

DA

13

14

16

(n

X

14

14

17

= Segmented Short Offset

SL

= Segmented Long Offset

= 1... 16)

ARITHMETIC (Continued)

Mnemonic.

Operand.

DIV
DIVL

R, src

Addr.
Mod..

X

107
107
107
108
109

107
107
107
109
109

107
107
107
111
112

744
744
744
745
746

744
744
746
746

744
744
744
748
749

R

11

11

11

11

11

11

R

1M
IR
DA

EXTS
EXTSB
EXTSL
INC
INCB

dst

dst, n

4
11
13
14

4
11
14
14

4
11
16
17

70
70
70
71
72

70
70
70
72
72

70
70
70
74
75

X

7
12
15
16

7
12
16
16

7
12
18
19

R

5

5

5

R
IR
DA

R,src

R

1M
IR
DA

X

NEG
NEGB

744

Operation
Divide (signed)
Word: Rn+1 - Rn,n+1 + src
Rn - remainder
long Word: Rn+2,n+3-Rn ... n+3+src
Rn,n + 2 - remainder

Extend Sign
Extend sign of low order half of dst
through high order half of dst

X

MULT
MULTL

Clock Cycle."
Long Word
Word, Byte
SL
NS
SL
NS
SS
SS

ds!

R
IR
DA

SBC
SBCB

R, src

SUB
SUBB
SUBL

R,src

Increment by n

I...-

dst-dst + n
(n = 1... 16)

282t
282t
282t
283t
284t

282t
282t
282t
284t

282t
282t
282t

28M

287t

28M

III)

Multiply (signed)
Word: Rn,n+ 1 - Rn+1 • src
long Word: Rn ... n+3 - Rn+2,n+3
tPlus seven cycles for each 1 In the
multiplicand

Negate
dst-O - ds!

Subtract with Carry
R-R - src - carry

R

1M
IR
DA

X

4
7
7
10
10

4
7
7
12
13

4
7
7

4
7
7
12
13

AND

9
10

4
7
7
10
10

7
12
15
16

7
12
16
16

7
12
18
19

Complement

4
7
7
9
10

4
7
7
10
10

4
7
7
12
13

8
14
14
15
16

8
14
14
16
16

8
14
14
18
19

Subtract

4
7
7
9
10

R-R - src

LOGICAL
AND
ANDB

R, src

R

1M
IR
DA

X

COM
COMB

R
IR
DA

dst

X

OR
ORB

R, src

R

1M
IR
DA

X
'NS

= Non-segmented

SS

= Segmented Short Offset

SL

R-RANDsrc

dst-Nardst

OR
R-RORsrc

= Segmented Long Offset
415

Q

CI

LOGICAL (Continued)
Clock Cycles·
Word, Byte
Long Word
NS
SL
NS
SL
SS
SS

Operands

Addr.
Modes

TCC
TCCB

cc. dst

R

5

5

TEST
TESTB
TESTL

dst

R
IR
DA
X

7
8
11
12

7
8
12
12

14
15

XOR
XORB

R.src

R

4
7
7
10
10

4
7
7
12
13

Exclusive OR
R-RXORsrc

IR
DA
X

4
7
7
9
10

Mnemonics

1M

5

7

8

Operation
Test Condition Code
Set LSB if cc is true

13
13
16
17

13
13
17
17

13
13
19
20

Test
dstORO

PROGRAM CONTROL
CALL

dst

IR
DA
X

10
12
13

15
18
18

15
20
21

Call Subroutine
Autodecrement SP
@SP-PC
PC-dst

CALR

dst

RA

10

10

15

Call Relative
Autodecrement SP
@SP-PC
PC-PC + dst (range -4094 to +4096)

R. dst

RA

11

11

11

Decrement and Jump If Non-Zero
R-R-1
If R ,p 0: PC-PC + dst(range - 254 to 9)

13

13

16

Interrupt Return
PS-@SP
Autoincrement SP

DJNZ
DBJNZ
IRETt

JP

cc.dst

IR
IR
DA
X

10
7
7
8

10
7
8
8

15
7
10
11

JR

cc.dst

RA

6

6

6

10
7

10
7

13
7

33

33

39

RET

cc

SC

src

1M

(taken)
(not taken)

Jump Conditional
If cc is true: PC - dst

Jump Conditional Relative
If cc is true: PC - PC + dst
(range - 256 to + 254)
(taken)
(not taken)

Return Conditional
If cc is true. PC - @ SP
Autoincrement SP
System Call

Autodecrement SP
@SP-oldPS
Push instruction
PS - System Call PS
*NS = Non-segmented
SS = Segmented Short Offset
tpnvileged instruction. Executed in system mode only

416

SL

= Segmented Long Offset

BIT MANIPULATION

Mnemonics

Operands

BIT
BITB

BIT
BITB

dst, b

dst, R

Addr.
Modes

Clock Cycles'
Word, Byte
Long Word
SL
NS
SS
SL
NS
SS

Operation

R

4

4

4

Test Bit Static

IR

8

8

8

Z flag - NOT dst bit specified by b

DA
X

10

11

13

11

11

14

R

10

10

10

Test Bit Dynamic
Z flag - NOT dst bit specified by
contents of R

RES
RESB

dst, b

RES
RESB

dst, R

SET
SETB

dst, b

SET
SETB
TSET
TSETB

R

4

4

4

IR

11

11

11

DA
X

13

14

16

14

14

17

R

10

10

10

Reset Bit Static
Reset dst bit specified by b

N

I...
•

Reset Bit Dynamic

N

Reset dst bit specified by contents R

dst, R

R

4

4

4

IR

11

11

11

DA
X

13

14

16

14

14

17

R

10

10

10

~

Set Bit Static

c:I

Set dst bit specified by b

Set Bit Dynamic
Set dst bit specified by contents of R

dst

R

7

7

7

IR

11

11

11

DA
X

14

15

17

15

15

18

Test and Set
S flag - MSB of dst
dst- al11s

ROTATE AND SHIFT
RL
RLB

dst, n

RLC
RLCB

dst, n

RLDB

R, src

RR
RRB

dst, n

RRC
RRCB

dst, n

RRDB

R, src

R

SDA
SDAB
SDAL

dst, R

R

SOL
SDLB
SDLL

dst, R

• NS = Non-segmented

R

6forn=1

Rotate Left

R

7forn=2

by n bits (n = 1, 2)

R

6 for n = 1

Rotate Left through Carry

R

7 for n=2

by n bits (n = 1, 2)

R

9

9

Rotate Digit Left

9

R

6 for n= 1

Rotate Right

R

7forn=2

by n bits (n = 1, 2)

R

6 for n= 1

Rotate Right through Carry

R

7 for n=2

by n bits (n = 1, 2)

9

9
(15 + 3n)

Rotate Digit Right

9
(15 + 3 n)

Shift Dynamic Arithmetic
Shift dst left or right by
contents of R

R

(15 + 3 n)

(15 + 3 n)

Shift Dynamic Logical
Shift dst left or right by
contents of R

SS

= Segmented Short Offset

SL

= Segmented Long Offset

417
_ _ _ ,,_." _ _
-~--

0_'

ROTATE AND SHIFT (Continued)
Clock Cycles'
Word, Byte
Long Word
NS
SL
NS
SS
SL
SS

Operands

Addr.
Modes

SLA
SLAB
SLAL

dst, n

R

(13 + 3n)

(13 + 3n)

Shift Left Arithmetic
by n bits

SLL
SLLB
SLLL

dst, n

R

(13 + 3n)

(13 + 3 n)

Shift Left Logical
by n bits

SRA
SRAB
SRAL

dst, n

R

(13 + 3n)

(13 + 3n)

Shift Right Arithmetic
by n bits

SRL
SRLB
SRLL

dst, n

R

(13 + 3n)

(13 + 3n)

Shift Right logical
by n bits

Mnemonics

Operation

BLOCK TRANSFER AND STRING MANIPULATION
CPO
CPDB

Rx,src,Ry,cc

IR

CPDR
CPDRB

Rx,src,Ry,cc

IR

CPI
CPIB

RX,src,Ry,cc

IR

CPIR
CPIRB

RX,src, Ry,cc

IR

CPSD
CPSDB

dst,src,R,cc

IR

CPSDR
CPSDRB

dst,src,R,cc

IR

• NS

418

= Non-segmented

SS

20

20

20

Compare, Decrement, and Repeat
Rx - src
Autodecrement src address
Ry-Ry-1
Repeat until cc is true or Ry = 0

(11 + 9 n)

20

20

20

= Segmented Short Offset

25

25

(11 + 14n)

SL

Compare and Increment
Rx - src
Autoincrement src address
Ry-Ry-1
Compare, Increment, and Repeat
Rx - src
Autoincrement src address
Ry+-Ry - 1
Repeat until cc is true or Ry = 0

(11 + 9 n)

25

Compare and Decrement
Rx - src
Autodecrement src address
Ry-Ry-1

= Segmented Long Offset

Compare String and Decrement
dst - src
Autodecrement dst and src addresses
R+-R-1
Compare String, Decrement, and
Repeat
dst - src
Autodecrement dst and src addresses
R+-R-1
Repeat until cc is true or R = 0

BLOCK TRANSFER AND STRING MANIPULATION (Continued)
Clock Cycles'
Mnemonics

Operands

Addr.
Modes

CPSI
CPSIB

dst,src,R,cc

IR

CPSIR
CPSIRB

dst,src,R,cc

IR

LDD
LDDB

dst,src,R

IR

LDDR
LDDRB

dst,src,R

IR

LDI
LDIB

dst,src,R

IR

LDIR
LDIRB

dst,src,R

IR

TRDB

dst,src,R

IR

TRDRB

dst,src,R

IR

TRIB

dst,src.R

IR

Long Word

Word, Byte

NS

SS

SL

25

25

25

NS

SS

(11 + 14 n)

20

20

20

20

25

(1<
,,

25

20

• NS = Non-segmented
SS = Segmented Short Offset
• Privileged instruction. Executed in system mode only.

SL

Load and Decrement
dst +- src
Autodecrement dst and src addresses
R+-R-1

Load and Increment
dst +- src
Autoincrement dst and src addresses
R+-R-1
Load, Increment and Repeat
dst +- src
Autoincrement dst and src addresses
R+-R-1
Repeat until R = 0

25

Translate and Decrement
dst +- src (dst)
Autodecrement ds! address
R+-R-1
Translate, Decrement and Repeat
dst +- src (dst)
Autodecrement dst address
R+-R-1
Repeat until R = 0

14 n)

25

Compare String and Increment
dst - src
Autoincrement dst and src addresses
R+-R-1

Load, Decrement and Repeat
dst +- src
Autodecrement dst and src addresses
R+-R-1
Repeat until R = 0

(11 + 9 n)

25

Operation

Compare String, Increment and
Repeat
dst - src
Autoincrement dst and src addresses
R+-R-1
Repeat until cc is true or R = 0

(11 + 9 n)

20

SL

25

Translate and Increment
dst +- src (dst)
Autoincrement dst address
R+-R-1

= Segmented Long Offset

419

N

00

...8

N

COt

•
d

BLOCK TRANSFER AND STRING MANIPULATION (Continued)

Operands

Addr.
Modes

TRIRB

dst,src,R

IR

TRTDB

src1,src2,R

IR

TRTDRB

src1,src2,R

IR

TRTIB

src1,src2,R

IR

TRTIRB

src1,src2,R

IR

Mnemonics

Clock Cycles·
Long Word
Word, Byte
5L
5L
N5
55
55
N5
(11

25

+ 14 n)

25

(11

25

(11

li"anslate, Increment and Repeat
dst +- src (dst)
Autoincrement dst address
R+-R-1
Repeat until R = 0
25

+ 14 n)

25

Operation

Translate and Test, Decrement
RH 1 +- src2 (src1)
Autodecrement src 1 address
R<--R-1
Translate and Test, Decrement, and
Repeat
RH1 +- src2 (src1)
Autodecrement src1 address
R+-R-1
Repeat until R = 0 or RH1 = 0

25

+ 14n)

Translate and Test, Increment
RH 1 +- src2 (src1)
Autoincrement src1 address
R+-R-1
Translate and Test, Increment and
Repeat
RH1 <-- src2 (src1)
Autoincrement src 1 address
R+-R-1
Repeat until R = 0 or RH1 = 0

INPUT/OUTPUT
INt
INBt

R,src

IR
DA

10
12

10
12

10
12

Input
R +- src

INDt
INDBt

dst,src,R

IR

21

21

21

Input and Decrement
dst +- src
Autodecrement dst address
R+-R-1

INDRt
INDRBt

dst,src,R

IR

IN It
INIBt

dst,src,R

IR

(11

21

• NS = Non-segmented
SS = Segmented Short Offset
tprivileged Instruction. Executed in system mode only.

420

+ 10 n)

21

SL

Input, Decrement and Repeat
dst +- src
Autodecrement dst address
R+-R-1
Repeat until R = 0
21

= Segmented Long Offset

Input and Increment
dst +- src
Autolncrement dst address
R<--R-1

INPUTIOUTPUT (Continued)
Clock Cycles·
Operands

Addr.
Modes

INIRt
INIRBt

dst,src,R

IR

OUTt
OUTBt

dst,R

IR
DA

10
12

10
12

10
12

Output
dst-R

OUTDt
OUTDBt

dst,src,R

IR

21

21

21

Output and Decrement
dst-src
Autodecrement src address
R-R-1

OTDRt
OTDRBt

dst,src,R

IR

OUTIt
OUTlBt

dst,src,R

IR

OTIRt
OTIRBt

dst,src,R

IR

R,src

DA

12

12

12

Special Input
R-src

SINDt
SINDBt

dst,src,R

IR

21

21

21

Special Input and Decrement
dst-src
Autodecrement dst address
R-R-1

SINDRt
SINDRBt

dst,src,R

IR

SINlt
SINIBt

dst,src,R

IR

Mnemonics

SINt
SINBt

Word, Byte

NS

SS

Long Word

SL

NS

SS

(11 + 10 n)

21

21

• NS = Non-segmented
SS = Segmented Short Offset
tPrivlleged instruction. Executed in system mode only.

SL

iii

Q
a

Output and Increment
dst-src
Autoincrement src address
R-R -1
Output, Incrament, and Repeat
dst-src
Autoincrement src address
R-R-1
Repeat until R = 0

11 + 10n)

21

I...

Output, Decrement and Repeat
dst-src
Autodecrement src address
R-R-1
Repeat until R = 0

(11 + 10 n)

21

Operation
Input, Increment and Repeat
dst -src
Autoincrement dst address
R-R -1
Repeat until R = 0

(11 + 10 n)

21

SL

Special Input, Decrament, and
Repeat
dst-src
Autodecrement dst address
R-R-1
Repeat until R = 0

21

Special Input and Incrament
dst-src
Autoincrement dst address
R-R-1

= Segmented Long Offset

421

INPUT/OUTPUT (Continued)
Clock Cycles·
Word, Byte
Long Word
NS
SL
NS
SS
SL
SS

Operands

Addr.
Modes

SINIRt
SINIRBt

dst,src,R

IR

SOUTt
SOUTBt

dst,src

DA

12

12

12

Special Output
dst +- src

SOUTDt
SOUTDBt

dst,src,R

IR

21

21

21

Special Output and Decrement
dst +- src
Autodecrement src address
R+-R-1

SOTDRt
SOTDRBt

dst,src,R

IR

SOUTIt
SOUTlBt

dst,sre,R

IR

SOTIRt
SOTIRBt

dst,sre,R

R

Mnemonics

(11 + 10n)

Special Input, Increment, and
Repeat
dst +- src
Autoincrement dst address
R+-R-1
Repeat until R = 0

(11 + 10 n)

21

21

Operation

Special Output, Decrement, and
Repeat
dst +- sre
Autodeerement sre address
R+-R-1
Repeat until R = 0
21

(11 + 10 n)

Special Output and Increment
dst +- sre
Autoinerement sre address
R+-R-1
Special Output, Increment, and
Repeat
dst +- sre
Autoinerement sre address
R+-R-1
Repeat until R = 0

CPU CONTROL
COMFLG

flags

7

7

7

Complement Flag
(Any combination of C, Z, S, P/V)

Dlt

int

7

7

7

Disable Interrupt
(Any combination of NVI, VI)

Elt

Int

7

7

7

Enable Interrupt
(Any combination of NVI, VI)

(8 + 3n)

HALTt

HALT

LDCTLt

CTLR,sre

R

7

7

7

Load into Control Register
CTLR +-sre

LDCTLt

dst,CTLR

R

7

7

7

Load from Control Register
dst +- CTLR

• NS = Non-segmented
SS = Segmented Short Offset
tPnvileged instruction. Executed in system mode only.

422

SL

= Segmented Long Offset

CPU CONTROL (Continued)
Clock Cycles·
Word, Byte
Long Word
NS
SS
SL
NS
SL
SS

Operands

AcIdr.
Modes

LDCTLB

FLGR,src

R

7

7

7

Load into Flag Byte Register
FLGR +- src

LDCTLB

dst,FLGR

R

7

7

7

Load from Flag Byte Register
dst +- FLGR

src

IR
DA

12
16
17

16
20
20

16
22
23

7

7

7

Mnemonics

LDPSt

X
MBITt

MREQt

dst

(12 + n)

R

Operation

Load Program Status
PS +- src

Test Multi-Micro Bit
Set S if MI is Low; reset S if M I is High
Multi-Micro Request

MRESt

5

5

5

Multi-Micro Reset

MSETt

5

7

7

Multi-Micro Set

NOP

7

7

7

No Operation

RESFLG

flag

7

7

7

Reset Flag
(Any combination of C, Z, S, PIV)

SETFLG

flag

7

7

7

Set Flag
(Any combination of C, Z, S, PIV)

• NS ~ Non-segmented
SS ~ Segmented Short Offset
tPnvileged Instruction. Executed in system mode only.

SL

~

r:
8...

N

C"t

•

~

Segmented Long Offset

423

CONDITION CODES
Code

Meaning

Flag Settings

F

Always false

T

Always true

Z

Zero

Z = 1

0000
1000
0110

NZ

Not zero

Z=O

1110

C

Carry

C = 1

0111

NC

No Carry

C=O

1111

PL

Plus

S=O

1101
0101

MI

Minus

S= 1

NE

Not equal

Z=O

1110

EQ

Equal

Z = 1

0110

OV

Overflow

PIV = 1

0100

NOV

No overflow

PIV = 0

1100

PE

Parity is even

PIV = 1

0100

PO

Parity IS odd

PIV = 0

1100

GE

Greater than or equal (signed)

(S XOR PIV) = 0

1001
0001

LT

Less than (signed)

(S XOR PIV) = 1

GT

Greater than (signed)

[Z OR (S XOR PIV)J = 0

1010

LE

Less than or equal (signed)

[Z OR (S XOR PIV)] = 1

0010

UGE

Unsigned greater than or equal

C=O

1111

ULT

Unsigned less than

C = 1

0111

UGT

Unsigned greater than

[(C = O)AND(Z = O)J = 1

1011

ULE

Unsigned less than or equal

(CORZ) = 1

0011

Note that some condition codes have Identical flag settings and binary fields in the Instruction:
Z - EO, NZ - NE, C - ULT, NC - UGE,OV - PE, NOV

= PO

STATUS CODE LINES
S10·S13
0000

424

CCFieid

Definition
Internal operation

0001

Memory refresh

0010

I/O reference

0011

Special I/O reference (e.g., to an MMU)

0100

Segment trap acknowledge

0101

Non-maskable interrupt acknowledge

0110

Non-vectored interrupt acknowledge

0111

Vectored interrupt acknowledge

1000

Data memory request

1001

Stack memory request

1010

Data memory request (EPU)

1011

Stack memory request (EPU)

1100

Program reference, nth word

1101

Instruction fetch, first word

1110

Extension processor transfer

1111

Reserved

PIN DESCRIPTION
AOO-A01S. Address/Data (inputs/outputs, active High,
3-state). These multiplexed address and data lines are used
for 1/0 and to address memory.
AS. Address Strobe (output, active Low, 3-state). The rising
edge of AS indicates addresses are valid.
BUSACK. Bus Acknowledge (output active Low). A Low on
this line indicates the CPU has relinquished control of the
bus.
BUSREQ. Bus Request (input, active Low). This line must
be driven Low to request the bus from the CPU.
B/W. Byte/Word (output, Low = Word, 3-state). This signal
defines the type of memory reference on the 16-bit
addressldata bus.
ClK. System Clock (input). CLK is a 5V single-phase
time-base input.
OS. Data Strobe (output, active Low, 3-state). This line times
the data in and out of the CPU.
MREQ. Memory Request (output, active Low, 3-state). A
Low on this line indicates that the addressldata bus holds a
memory address.

non-maskable interrupt. The NMI interrupt has the highest
priority of the three types of interrupts.

N/S. Normal/System Mode (output, Low = System Mode,
3-state). N/S indicates the CPU is in the normal or system
mode.
NMI. Non-Vectored Interrupt (input, active Low). A Low on
this line requests a non-vectored interrupt.
RESET. Reset (input, active Low). A Low on this line resets
the CPU.

R/W. ReadIWrite (output, Low = Write, 3-state). R/W
indicates that the CPU is reading from or writing to memory
or 1/0.
SEGT. Segment Trap (input, active Low). The Memory
Management Unit interrupts the CPU with a Low on this line
when the MMU detects a segmentation trap. Input on
Z80010nly.
SNo-SN6. Segment Number (outputs, active High, 3-state}.
These lines provide the 7-bit segment number used to
address one of 128 segments by the Z8010 memory
Management Unit Output by the Z8001 only.
STo-ST 3. Status (outputs, active High, 3-state). These lines
specify the CPU status (see Status Code Lines).

MI, MO. Multi-Micro In, Multi-Micro Out (input and output,
active Low). These two lines form a resource-request daisy
chain that allows one CPU in a multi-microprocessor system
to access a shared resource.

STOP. Stop (input, active Low). This input can be used to
single-step instruction execution.

NMI. Non-Maskable Interrupt (edge triggered, input, active
Low). A high-to-Iow transition on NMI requests a

VI. Vectored Interrupt (input, active Low). A Low on this line
requests a vectored interrupt.
WAIT. Wait (input, active Low}. This line indicates to the CPU
that the memory or 1/0 device is not ready for data transfer.

AD,

AD,

ADs

SN,

AD,o

SN,

AD11

AD,

AD'2
ADu

AD,

AD,

AD.

AD,

AD,o

AD,

STOP

SN,

AD"

AD,

Mi

AD,

AD'2

ADs

AD,s

AD,

AD,3

AD,
AD,

ADu

AD,

STOP

+fiV

AD~

Mi

AD,

Vi

SN,

AD,s

AD,

NVI
SEGT

GND

AD'4

AD,

CLOCK

+SV

GND

NMI

AS

RESET

NC

Vi
NVi

BNi

NMI

MO
MREQ

NIB

RESET

CLOCK

AS
NC
B/W

os

RNi

ST,

BUSACK

ST,

WAif

ST,

BUSREQ

ST,

ST.

SN.

ST,

BUSREQ

SN,

SN,

ST,

ST,

Figure 1Oa. 48-pin Dual·ln·Line Package (DIP),
Pin Assignments

MO

NIB

MREQ

RNi

os

BUSACK

WAif

Figure 11 a. 40-pin Dual-ln·Line Package (DIP),
Pin ASSignments

425

I-...
N

~

~u ..,.Q"'~,.Q"'~Q"'''.,.Q. .~q.".Qt) )(<,~ G-~Q ..,.Q~ ~~"o t:?J~'" ~'\ ~"o~'"~v ~CJ
9

8

7

6

5

4

3

2

1

~

~

66

~

~

63 62 61

NC

10

60

NC

STOP

11

59

SN4

iiI1

12

58

ADS

AD15

13

57

AD3

AD14

14

56

AD2

+5V

15

55

AD,

NC

16

54

SN2

NC

17

53

GND

NC

18

52

NC

iii

19

51

eLK

NVI

20

50

NC

SEGT

21

49

AS

Z8001

CPU

NMI

22

48

RESERVED

RESET

23

47

B/IN

MO

24

46

N/S

MREQ

25

45

R/W

NC

26

44

NC

Figure 10b. 68-pin Chip Carrier, Pin Assignments
~u
6

..,.Q..."J~"''V~''''''''Q...a~O)

5

4

3

2

~() ",,0"0 ~'\ ~"o ",QI>.

1 «43 42 41

~

STOP

7

39

AD,

iiI1

8

38

AD,

AD15

9

37

AD,

AD14

10

36

AD,

+5V

11

35

GND

34

ClK

NC

12

iii
NVi

13
14

Z8002

CPU

33

AS

32

RESERVED

NMI

15

31

B/W

RESET

16

30

N/S

MO

17

29

R/W

Figure 11 b. 44-pin Chip Carrier, Pin Assignments

Z8000 CPU TIMING
The Z8000 CPU executes instructions by stepping through
sequences of basic machine cycles, such as memory read
or write, 110 device read or write, interrupt acknowledge,
and internal execution. Each of these basic cycles requires
three to ten clock cycles to execute. Instructions that require
more clock cycles to execute are broken up into several
machine cycles. Thus no machine cycle is longer than ten
clock cycles and fast response toa Bus Request IS
guaranteed.
The instruction opcode is fetched by a normal memory read
operation. A memory refresh cycle can be inserted just after
the completion of any first instruction fetch (IF1) cycle and
can also be inserted while the following instructions are
being executed: MULT, MULTL, DIV, DIVL, HALT, all Shift
instructions, all Block Move instructions, and the Multi-Micro

426

Request instruction (MREQ).
The following timing diagrams show the relative timing
relationships of all CPU signals during each of the baSIC
operations. When a machine cycle requires additional clock
cycles for CPU internal operation, one to five clock cycles
are added. Memory and I/O read and write, as well as
interrupt acknowledge cycles, can be extended by
activating the WAIT input. For exact timing information, refer
to the composite timing diagram.
Note that the WAIT input is not synchronized in the Z8000
and that the setup and hold times for WAIT, relative to the
clock, must be met. If asynchronous WAIT signals are
generated, they must be synchronized with the CPU clock
before entering the Z8000.

MEMORY READ AND WRITE
Memory read and instruction fetch cycles are identical,
except for the status information on the STo-ST3 outputs.
Ouring a memory read cycle, a 16-bit address is placed on
the AOO-A015 outputs early in the first clock period, as
shown in Figure 12. In the Z8001, the 7-bit segment number
IS output on SNo-SNs one clock penod earlier than the 16-blt
address offset.)
A valid address is indicated by the rising edge of Address
Strobe. Status and mode information become valid early in
the memory access cycle and remain stable throughout.
The state of the WAIT input is sampled in the middle of the
second clock cycle by the falling edge of Clock. If WAIT is
Tn

CLOCK

-

T,

I

I

Low, an additional clock period is added between T2 and T3.
WAIT is sampled again in the middle of this wait cycle, and
additional wait states can be inserted: this allows interfacing
slow memories. No control outputs change during wait
states.
Although Z8000 memory is word organized, memory is
addressed as bytes. All instructions are word-aligned, using
even addresses. Within a 16-bit word, the most significant
byte (08-015) is addressed by the low-order address (Ao =
Low), and the least significant byte (00-07) is addressed by
the high-order address (Ao = High).

T,

T,

~WAIT

1

DATA SAMPLED

T

FOR READ

WAIT CYCLES ADDED

SAMPLED

WAIT

STATUS

(BIW. NI!,
STo-ST,)

SNo-SN.

SEGMENT NUMBER

Ai

MR.Q

AD

MEMORY ADDRESS

READ

(

')---

DATA IN

>

iii

READ

R1W
READ

~

/

AD

MEMORY ADDRESS

WRITE

DATA OUT

iii
WRITE

R1W
WRITE

\

r

Figure 12. Memory Read and Write Timing

427

INPUT/OUTPUT
1/0 timing is similar to memory readlwrite timing, except that
one wait state is automatically (TWA) inserted between T2

CLOCK

-

and T3 (Figure 13). Both the segmented Z8001 and the
nonsegmented Z8002 use 16-bit 1/0 addresses.

T,

T,

TN.

T.

I

I

~WAIT

.1

SAMPLED

~
DATA SAMPL ED
FOR READ

T

WAIT CYCLES ADDED

WAIT

.JITATUS 81W, ST.-ST.) _

ry

N/S

Ali

LOW

- r\

HIGH

MAEQ

ADINPUT

-

D<

PORT ADDRESS

(

}o------

DATA IN

> C

Di

INPUT

A/W
INPUT

ADOUTPUT

~

- LI
-

=x

PORT ADDRESS

DATA OUT

Di

OUTPUT

AlWOUTPUT

r

r\
Figure 13. Input/Output Timing

428

INTERRUPT AND SEGMENT TRAP
REQUEST AND ACKNOWLEDGE
The Z8000 CPU recognizes three interrupt inputs
(non-maskable, vectored, and nonvectored) and a
segmentation trap input. Any High-to-Low transition on the
NMI input is asynchronously edge detected and sets the
internal NMllatch. The Vi, NVI, and SEGT inputs, as well as
the state of the internal NMllatch, are sampled at the end of
T2 in the last machine cycle of any instruction.
In response to an interrupt or trap, the subsequent IF1 cycle
is exercised, but ignored. The internal state of the CPU is not
altered and the instruction will be refetched and executed
after the return from the interrupt routine. The program
counter is not updated, but the system stack pointer is
decremented in preparation for pushing starting information
onto th e system stac k.

This cycle has five automatic wait states, with additional wait
states possible, as shown in Figure 14.
After the last wait state, the CPU reads the information on
ADo-AD15 and temporarily stores it, to be saved on the stack
later in the acknowledge sequence. This word identifies the
source of the interrupt or trap. For the nonvectored and
nonmaskable interrupts, al116 bits can represent peripheral
device status information. For the vectored interrupt, the low
byte is the jump vector, and the high byte can be extra user
status. For the segmentation trap, the high byte is the
Memory Management Unit identifier and the low byte is
undefined.
After the acknowledge cycle, the N/§' output indicates the
automatic change to system mode.

The next machine cycle is the interrupt acknowledge cycle.

8
N

tool

I

LAST MACHINE
I
INSTRUCTIONj
-~~~i~U0c"T~NNY-(~~6CR~~~)
1··_ _ _ _ _ _ _ _ _ _ ACK~~~ciDGE----------. ~ler~~

I

CLOCK

Vi, iiVi, iiiIf

rt.si.Ji.s

m .·

T,

T;

_ _ _....l...+..L-_

INTIANAL

iiill

ACKNOWLEDGE

(\... _ _ _-J)
Figure 14. Interrupt and Segment Trap Request/Acknowledge Timing

STATUS SAVING SEQUENCE
The machine cycles, following the interrupt acknowledge or
segmentation trap acknowledge cycle, push the old status
information on the system stack in the following order: the
16-bit program counter; the 7-bit segment number (Z8001

N
Q

=
-v

AUTOMATIC ~AtT STATES

only); the flag control word; and finally the interrupt/trap
identifier. Subsequent machine cycles fetch the new
program status from the program status area, and then
branch to the interrupt/trap service routine.

429

BUS REQUEST ACKNOWLEDGE TIMING
A Low on the BUSREO input indicates to the CPU that
another device is requesting the AddresslData and control
buses. The asynchronous BUSREO input is synchronized
at the beginning of any machine cycle (Figure 15). BUSREO
takes priority over WAIT. If BUSREO is Low, an internal
synchronous BUSREQ signal is generated, which-after
completion of the current machine cycle-causes the
BUSACK output to go Low and all bus outputs to go into the
44---ANY M CYCLE---i

high-impedance state. The requesting device-typically a
DMA-can then control the bus.
When BUSREO is released, it is synchronized with the rising
clock edge; the BUSACK output goes High one clock
period later, indicating that the CPU will again take control of
the bus.

_ + _ - - - - B U S AVAILABLE----.~.

1

T1

T2

T3

Tx

Tx

Tx

Tx

Tx

Tx

CLOCK

INTERNAL
BUSREQ

SN

~--

AD

----

--- ---- ----

MREQ.DS.-----------------------+~
STo- ST 3.

-+.J) - - -

B/Vii. R/W. N/S ______________________

----

----

---

Figure 15. Bus Request/Acknowledge Timing

430

----

STOP
The STOP input is sampled by the last falling clock edge
immediately preceding any IF1 cycle (Figure 16) and before
the second word of an EPA instruction is fetched. If STOP is
found Low during the IF1 cycle, a stream of memory refresh
cycles is inserted after T3, again sampling the STOP input on
each falling clock edge in the middle of the T3 states. During
the EPA instruction, both EPA instruction words are fetched
but any data transfer or subsequent instruction fetch is

---IF'-----.II

_'
1

~

postponed until STOP is sampled High. This refresh
operation does not use the refresh prescaler or its
divide-by-four clock prescaler; rather, it double-increments
the refresh counter every three clock cycles. When STOP is
found High again, the next refresh cycle is completed, any
remaining T states of the IF1 cycle are then executed, and
the CPU continues its operation.

~

~

1.....----REFREsH-I
~
~
~ I

_ '---IREFRESH _ _ I

~

1

~

~

~

~

CLOCK

ITDP\~/~______\~/_____

XX= J \'--________
REFRESH

AD

ADORESS

)--

i-...
N

~

\'---oJ/

\I..-__-J/
ITO-IT3

===><____

..IX'-_______

IF_,_ _ _

MEMORY REFRESH

V--

--------"---

/
Riw

HIGH

Figure 16. Stop Timing

431

INTERNAL OPERATION
Certain extended instructions, such as Multiply and Divide,
and some special instructions need additional time for the
execution of internal operations. In these cases, the CPU
goes through a sequence of internal operation machine

cycles, each of which is three to eight clock cycles long
(Figure 17). This allows fast response to Bus Request and
Refresh Request, because bus request or refresh cycles
can be inserted at the end of any internal machine cycle.
T3

-

I

I

STo-STa

AD

I

INTERNAL OPERATION

~)--

UNDEFINED

HIGH

alw

UNDEFINED

H/i

SAME AS PREVIOUS CYCLE

I
Figure 17. Internal Operation Timing

HALT
A HALT instruction executes an unlimited number of 3-cycle
internal operations, interspersed with memory refresh
cycles whenever requested. An interrupt, segmentation
trap, or reset are the only exits from a HALT instruction.

432

The CPU samples the Vi, NVI, NMI, and SEGT inputs at the
beginning of every T3 cycle. If an input is found active during
two consecutive samples, the subsequent IF1 cycle is
exercised, but ignored, and the normal interrupt
acknowledge cycle is started.

MEMORY REFRESH
When the 6-bit prescaler in the refresh counter has been
decremented to zero, a refresh cycle consisting of three
T-states is started as soon as possible (that is, after the next
IF1 cycle or Internal Operation cycle).

Incremented by two, thus stepping through 256 consecutive
refresh addresses on AD1-ADs. Unless disabled, the
presettable prescaler runs continuously and the delay in
starting a refresh cycle is therefore not cumulative.

The 9-bit refresh counter value IS put on the low-order side of
the address bus (ADo-ADs); ADg-AD 15 are undefined
(Figure 18). Since the memory is word-organized, Ao is
always Low during refresh and the refresh counter is always

While the STOP input is Low, a continuous stream of memory
refresh cycles, each th ree T-states long, is executed without
using the refresh prescaler.

•
CLOCK

-

T1~"

T2_

T,_

I

I

I

...--

I...N

~

REFRESH

AD

REFRESH ADDRESS

R/ii, B/ii, HiS}

)------- ~--------

-C

SAME AS PREVIOUS CYCLE

I
Figure 18. Memory Refresh Timing

RESET
A Low on the RESET input causes the following results within
five clock cycles (Figure 19):
• ADo-AD15 are 3-stated

• AS,

DS, MREQ, STo-ST3, BUSACK, and MO are forced
High

• SNo-SN6 are forced Low
•

Refresh is disabled

• R/W, B/W, and N/S are not affected

When RESET has been High for three clock periods, three
consecutive memory read cycles are executed in the system
mode for the Z8001. The Z8002 has two consecutive read
cycles. In the Z8001, the first cycle reads the flag and control
word from location 0002, the next reads the 7-bit program
counter segment number from location 0004, the next
reads the 16-bit PC offset from location 0006, and the
following IF1 cycle starts the program. In the Z8002, the first
cycle reads the flag and control word from location 0002,
the next reads the PC from location 0004, and the following
IF1 cycle starts the program.

433

Ii
434

..
c

1::/

Ii

I~

VI

iii

I~

II

COMPOSITE AC TIMING DIAGRAM
Rlan

~

-

~

r~~
51

ii,

~

-

NVI

-®--

-

alaT
ii,

~

-®-- ~-

-

~

l---.?i

.0

~

This composite timing dlagram does not show actual
timing sequences Refer to
this diagram only for the
detailed timing relationships
of Individual edges Use the
preceding Illustrations as an
explanation of the various
timing sequences

~

~~

~

Timing measurements are
made at the following
voltages
High
Low

59

~

STOP

WAIT

W

~

~~

~

~
65

-

~

~

K

'--

~K=

Clock
Output
Input
Float

40V
20V
20V
V

o 8V

I...-

a
o

8V
8V
±O 5V

N

9

((

6'
1

~-0CLOCK

.JHD--j ' ~

-

~

~

l:::t0

><

® -f--~-t®
~ f-- I -

H9-

r® ~

is

MEMORY READ

"
~/~

)

~

~

.../

-®-

-MD

r-r--~ kiD----

r-®

NORMAL'SYSTEM,
BYTE'WORD

kiJ--

><

-®~

.f

---

f

---------

-®- ~

~

~

4v-1

..v

~~
~
~~ ~~

"i--------:--

tiP

""'

ACKNOWLEDGE

rJ= -1-c:

...,."1

~~

~

REA:,~Rf:.:

"

~

~

,f®--

1>
®-I-

~--

:D

[®

MEMORY WRITE . . . /

INPUT/OUTPUT

~

11

+-®L

i

>-

DATA IN

DATA OUT

- - f ~~-@-

K
I-'®

-0ADDRESS

ADo-AD,.

---

I

435

AC CHARACTERISTICSt
Z8001AI
Z8002A

Z8001l
Z8002

Number Symbol

Parameter

Min

Max

Min

Max

Min

Max
2000

TcC

Clock Cycle Time

250

2000

165

2000

100

2

TwCh

Clock Width (High)

105

1895

70

1930

40

1960

3

TwCI

Clock Width (Low)

105

1895

70

1930

40

1960

4

TIC

Clock Fall Time

20

10

10

5

TrC

Clock Rise Time

20

15

10

6

TdC(SNv)

Clock t to Segment Number Valid (50 pI load)

7

TdC(SNn)

Clock t to Segment Number Not Valid

8

TdC(Bz)

Clock t to Bus Float

65

55

50

9

TdC(A)

Clock t to Address Valid

100

75

55

10

TdC(Az)

Clock t to Address Float

65

55

50

130
20

110
10

475'

90
0

11

TdA(DR)

Address Valid to Read Data Required Valid

12

TsDR(C)

Read Data to Clock.j. Setup time

30

13

TdDS(A)

OS t to Address Active

80'

14

TdC(DW)

Clock t to Write Data Valid

15

ThDR(DS)

Read Data to OS t Hold Time

0

0

0

16

TdDW(DS)

Write Data Valid to OS t Delay

295'

195'

110'

17

TdA(MR)

Address Valid to MREQ.j. Delay

55'

35'

18

TdC(MR)

Clock.j. to MREQ.j. Delay

19

TwMRh

MREQ Width (High)

305'

20

TdMR(A)

20
45'
100

180'
10
20'

75

60

20'
70

80

50

210'

135'

80'

MREQ.j. to Address Not Active

70'

35'

20'

55'

21

TdDW(DSW)

Write Data Valid to DS.j. (Write) Delay

22

TdMR(DR)

i\ii"F'i'Eo .j. to Read Data Required Valid

23

TdC(MR)

24

35'

15'

370'

230'

140'

Clock.j. MREQ t Delay

80

60

50

TdC(ASf)

Clock t to AS.j. Delay

80

60

25

TdA(AS)

Address Valid to AS t Delay

55'

35'

45
20'

26

TdC(ASr)

Clock.j. to AS t Delay

27

TdAS(DR)

AS t to Read Data Required Valid

28

TdDS(AS)

OS t to AS .j. Delay

70'

35'

15'

29

TwAS

AS Width (Low)

85'

55'

30'

30

TdAS(A)

AS t to Address Not Active Delay

70'

45'

20'

31

TdAz(DSR)

Address Float to OS (Read) .j. Delay

32

TdAS(DSR)

AS t to Os (Read) .j. Delay

33

TdDSR(DR)

OS (Read) -I to Read Data Required Valid

34

TdC(DSr)

Clock .j. to OS t Delay

35

TdDS(DW)

OS t to Write Data Not Valid

36

TdA(DSR)

Address Valid to OS (Read).j. Delay

37

TdC(DSR)

Clock t to OS (Read) -I Delay

38

TwDSR

OS (Read) Width (Low)

39

TdC(DSW)

Clock.j. to OS (Write).j. Delay

40

TwDSW

OS (Write) Width (Low)

'Clock-cycle time-dependent characteristics. See Footnotes to AC Characteristics
tUnits in nanoseconds (ns)

436

Z8001BI
Z8002B

90
360'

80

45

220'

140'

0

0

0

80'

55'

30'

205'

130'

70'

70

65

50

75'

45'

180'

110'
120

275'

65'
85

65
110'

185'
95

185'

25'

80
110'

65
75'

AC CHARACTERISTICSt (Continued)

Number Symbol

Parameter

41
42
43

TdDSI(DR)

OS (1/0) j. to Read Data Required Valid

TdC(DSD

Clock j. to OS (1/0) j. Delay

TwOS

44

TdAS(DSA)

58 (I/O) Width (Low)
AS t to OS (Acknowledge) j. Delay

45

TdC(DSA)

Clock t to OS (Acknowledge) j. Delay

46

TdDSA(DR)

47

Z80011

Z8001AI

Z8002

Z8002A

Min

Max

Min

330'
120

Z8001BI

Z8002B

Max

Min

210'

Max

120'
65

90

410'

255'

160'

1065'

690'

410'

120

85

70

OS (Acknowledge) j. to Read Data Required
Delay

455'

295'

TdC(S)

Clock t to Status Valid Delay

110

85

165'
65

48
49

TdS(AS)

Status Valid to AS t Delay

TsR(C)

RESET to Clock t Setup Time

50

ThR(C)

RESET to Clock t Hold Time

51
52
53
54
55

TwNMI

NMI Width (Low)

TsNMI(C)

NMI to Clock t Setup Time

TsVI(C)
ThVI(C)

Vi, NVI to Clock t Setup Time
Vi, NVI to Clock t Hold Time

TsSGT(C)

SEGT to Clock t Setup Time

56
57
58
59
60

ThSGT(C)

SEGT to Clock t Hold Time

TsMI(C)
ThMI(C)

Mi to Clock t Setup Time
Mi to Clock t Hold Time

TdC(MO)

Clock t to MO Delay

TsSTP(C)

STOP to Clock j. Setup Time

50*

50

0

0

0

100
140
110
20
70

70
70
50
20
55

50
50
40
10
40

0
180
0

0
140
0

0
80
0

120
140

85
50
0
20
5
60

61

ThSTP(C)

STOP to Clock j. Hold Time

0

0

TsW(C)

WAIT to Clock j. Setup Time

ThW(C)

WAIT to Clock j. Hold Time

50
10

30
10

TsBRQ(C)

BUSREQ to Clock t Setup Time

65

ThBRQ(C)

BUSREQ to Clock t Hold Time

90
10

80
10

66
67

TdC(BAf.

Figure 15. Interrupt and SegmentiAddra88 Translation Trap, Request/Acknowledge Timing
2084-014,015

455

PIN DESCRIPTIONS
The Z8003 Z-VMPU is produced in a 48-pin package; the
Z8004 Z-VMPU is produced in a 40-pin package. The pin
functions of both the Z8003 and Z8004 are illustrated in
Figure 16; the pin assignments are illustrated in Figure
17. The signal names assigned to the Z-VMPU 110 pins
are listed alphabetically and are described in the following paragraphs.

ABORT. Abort Request (input, active Low). This input is
used to implement virtual memory. It is asserted by external
circuitry when an address does not correspond to a location
in main memory.
When ABORT is asserted with input SAT in the Z8003, or
with input NMI, Vi, or NVI in the Z8004, it initiates an Abort
Interrupt in the Z-VMPU.

AOo·A015. Address/Data (inputs/outputs, active High,
3-state). These multiplexed address and data lines are used
both for 1/0 and memory.
AS. Address Strobe (output, active Low, 3·state). The rising
edge of AS indicates that addresses are valid.
BUSACK. Bus Acknowledge (output, active Low). A Low on
this line indicates that the Z·VMPU has relinquished control
of the bus.
BUSREQ. Bus Request (input, active Low). This line must
be driven Low to request the bus from the Z-VMPU.
B/W. Byte/Word (output, Low = Word, 3-state). This line defines the size of the data being transferred.

OS. Data Strobe (output, active Low, 3-state). This line
strobes data in and out of the Z-VMPU.
MI, MO. Multi-Micro In, Multi-Micro Out (input and output,
active Low). These two lines form a resource-request daisy
chain that allows only one Z-VMPU in a multimicroprocessor system to access a shared resource at the
same time.
MREQ. Memory Request (output, active Low, 3-state). A
Low on this line indicates that a memory reference is in
progress.
NMI. Nonmaskable Interrupt (edge-triggered, input, active
Low). A High·to-Low transition on NMI requests a nonmaskable interrupt.
N/S. Normal/System Mode (output, Low = System mode,
3-state). N/S indicates the current Z-VMPU operating mode
(System or Normal).
NVI. Nonvectored Interrupt (input, active Low). A Low on
this line requests a nonvectored interrupt.
RESET. Reset (input, active Low). A Low on this line resets
theZ-VMPU.
SAT. Segment Address Translation Trap (Z8003 only, input,
active Low). A Low on this input requests a Segment Address Translation trap.
STOP. (Input, active Low). When asserted this line suspends
CPU operation either after the fetch of the first word of an
instruction or during an EPU instruction if the EPU is busy.

ClK. System Clock (input). CLK is a + 5V single-phase,
time-base input.

BUS{

TIMINO

AS

AD15
AD14

Ill!
Mml

BUS{

TIMING

AD13
AD12
AD11

AD10

RO_{

ADDRESSI

DATA

~.-{

ADDRESSI
DATA

Z8004
VMPU

Z8003
VMPU

INTERRUPTS{

MULTloMICRO{

MULTI·MICRO {
CONTROL

CONTROL

SEGMENT·PAGE
or TRANSLATION
TRAP

+5V GND eLK

+5 V GNO elK

Figure 16. Pin Functions

456

2084·016

AD,
ADo

AD,
SN,

AD,
AD,
AD,

SN,
AC,
AD,
AD,
SN,

M!
AD15

AD14

AD14

+.v

GND

iiVi

iiIIi
IiEm

Mo
!Iml
til
MREil

ST 3

~

~

~

~

ST,

ST,
ST,
ST,
SN,

Figure 17. Pin Assignments

INSTRUCTION SET SUMMARY
The Z8003/04 instruction set is presented in the instruc·
tion set summary. This summary lists the mnemonics,
operands, addressing modes, timing, and operation for
each instruction.
Timing Is given as the number of CPU clock cycles reo
quired for instruction execution. Timing requirements
are given for the three possible addressing representa·
tions used in word, byte and long word operations:
•

NS

nonsegmented addresses

is contained within the instruction itself. The only instructions of this type are those using the DA and X address·
ing modes.
With few exceptions, timing requirements are the same
for all instructions in either segmented or nonsegmented
mode, except for those instructions that employ the SS
and SL addresses. The timing for these instructions will
differ since the number of fetches needed to load the address, one word or two words, will vary.

•

SS

segmented short·offsetaddresses

NOTE

•

SL

segmented long·offset addresses

Timing values are given in the SS and SL columns of the instruction set summary
for ali addressing modes, even where the address representation does not apply.
These values are given to Indicate that the time requirements are the same for
both segmented and nonsegmented modes.

The SS and SL address representations apply only to
those instructions for which the address of the operand

INSTRUCTION SET SUMMARY
The Z8003/4 provides the following types of instructions:

•

Bit Manipulation

•

Load and Exchange

•

Rotate and Shift

•

Arithmetic

•

Block Transfer and String Manipulation

•

Logical

•

Input/Output

•

Program Control

•

CPU Control

2084-017

457

Load and Exchange

Mnemonics

Operands

Addr.
Modes

CLR
CLRB

dst

R

7
8
12
12

7
8
14
15

6
12
15
16

6
12
16
16

6
12
18
19

3
7
5(byte
7
9
10
14
14

3
7
only)
7
10
10
14
14

3
7

5
11

5
11

5
11

7
12
13
14
14

11
12
13
17
17

11
13
13
17
17

11
15
16
17
17

8
11
12
14
14

8
12
12
14
14

8
14
15
14
14

11
14
15
17
17

11
15
15
17
17

11
17
18
17
17

DA
X

11
14
15

11
15
15

11
17
18

DA
X
BA
BX

12
13
15
15

13
13
15
15

15
16
15
15

RA

15

15

15

IR
X
R,src

R

IR
DA
X

LO
LOB
LOL

R,src

R

1M
1M·

IR
DA
X
BA
BX

LO
LOB
LOL

dst,R

LO
LOB

dst, 1M

LOA

R,src

LOAR

IR
DA
X
BA
BX

R,src

IR

Operation
Clear

7
8
11
12

DA

EX
EXB

Clock Cycles
Word, Byte
Long Word
NS
SS
SL NS
SS
SL

dst - 0

Exchange
R -

Load Into Register
R -

R,src

1M

5

5

R,src,n

IR

Load Immediate Into Memory
1M
Load Address
R-

LOM

dst,R,n

n (n

= 0 ... 15)

Load Multiple

11
17
18

+3n

DA
X

11
14
15

11
15
15

11
17
18

+3n

RA

14

14

14

17

R (n

src (n consecutive words)

= 1 ... 16)

Load Multiple (Store Multiple)
dst - R (n consecutive words)
(n
1 ... 16)

=

LOR
LORB
LORL

R,src

LOR
LORB
LORL

dst,R

RA

14

14

14

17

17

17

POP
POPL

dst,IR

R
IR
DA
X

8
12
16
16

8
12
16
16

8
12
18
19

12
19
23
23

12
19
23
23

12
19
25
26

PUSH
PUSHL

IR,src

R
1M
IR
DA
X

9
12
13
13
14

9
12
13
14
14

9
12
13
16
17

12

12

12

458

source address

Load Constant

5

11
15
15

IR

source address

Load Address Relative

11
14
15

DA
X

R

dst -

R -

LOM

src

Load Into Memory (Store)
dst -

R -

LOK

src

17

17

Load Relative
R - src
(range -32768 ... + 32767)

20
21
21

20
21
21

20
23
24

Load Relative (Store Relative)
dst - R
(range -32768 ... + 32767)
Pop
dst - IR
Autoincrement contents of R

Push
Autodecrement contents of R
IR - src

Arithmetic

Mnemonlc8

Operands

Addr,
Mode8

ADC
ADCB

R,src

R

ADD

R,src

ADDL

5

Operation
Add with Carry

5

4
7
7
10
10

4
7
7
12
13

8
14
14
15
16

8
14
14
16
16

8
14
14
18
19

Add

4
7
7
9
10

4
7
7
10
10

4
7
7
12
13

8
14
14
15
16

8
14
14
16
16

8
14
14
18
19

Compare with Regl8ter

11
15
15

11

Compare with Immediate

17

dst -1M

X

11
14
15

DA
R,src

R
1M
IR

DA
X
dst, 1M

R + carry + src

4
7
7
9
10

R
1M
IR

X

CP
CPB

5

R-

AD DB

CP
CPB
CPL

Clock Cycle8
Word, Byte
Long Word
SL NS
SL
NS
SS
SS

IR

DA

R-

R + src

R - src

N

GO

DAB

dst

R

5

5

5

Decimal Adjust

DEC
DECB

dst,n

R
IR

4
11
13
14

4
11
14
14

4
11
16
17

Decrement by n

X

107
107
107
108
109

107
107
107
109
109

107
107
107
111
112

R

11

11

11

DA
X

DIV
DIVL

R,src

R
1M
IR

DA
EXTS
EXTSB
EXTSL

dst

INC
INCB

dst,n

R
IR

4
11
13
14

4
11
14
14

4
11
16
17

70
70
70
71

70
70
70
72
72

70
70
70
74
75

X

7
12
15
16

7
12
16
16

7
12
18
19

R

5

5

5

X
R,src

R
1M
IR

DA
X

NEG
NEGB

-..
ell

II

....

CI

dst-dst-n
(n
1 ... 16)

=

744
744
744
745
746

744
744
744
746
746

744
744
744
748
749

11

11

11

Divide (signed)
Word: Rn+1 - Rn,n+1 + src
Rn - remainder
Long Word: Rn +2,n+3 - Rn ... n +3 + src
Rn, n + 1 - remainder
Extend Sign
Extend sign of low order half of dst
through high order half of dst

DA
MULT
MULTL

8W

18

dst

R
IR

DA
SBC
SBCB

R,src

SUB
SUBB
SUBL

R,src

72

Increment by n
dst-dst+n
(n
1 ... 16)

=

282"
282"
282"
283"
284"

282"
282"
282"
284"
284"

282"
282"
282"
286"
287"

Multiply (signed)
Word: Rn,n+ 1 - Rn+ 1 • src
Long Word: Rn ... n+3 - Rn +2,n+3' src
" Plus seven cycles for each 1 in the
absolute value of the low order word of
the multiplicand
Negate
dst -

Subtract with Carry
R-

R
1M
IR

DA
X

4
7
7

9
10

4
7
7
10
10

4
7
7
12
13

-dst

8
14
14
15
16

8
14
14
16
16

8
14
14
18
19

R - src - carry

Subtract
R-

R - src

459

Logical

Mnemonics

Operands

AND
ANDB

A,sre

Addr.
Modes

dst

OR
ORB

A,sre

4
7
7
12
13

And

IA
DA
X

4
7
7
10
10

A
IA
DA
X

7
12
15
16

7
12
16
16

7
12
18
19

Complement

A

4
7
7
10
10

4
7
7
12
13

OR

IR
DA
X

4
7
7
9
10

R
IR
OA
X

7
8
11
12

7
8
12
12

7
8
14
15

R

5

5

5

1M

TEST
TESTB
TESTL

dst

TCC
TCCB

ce,dst

XOR
XORB

R,sre

Operation

4
7
7
9
10

A

1M

COM
COMB

Clock Cycles
Word, Byte
Long Word
NS
SL NS
SL
SS
SS

A - AAND src

dst - NOTdst

R - R OR sre

13
13
16
17

13
13
17
17

13
13
19
20

Test
dst OR 0

Test Condition Code
Set LSB If cc is true

R

4
7
7
10
10

exclusive OR

iR
DA
X

4
7
7
9
10

Addr.
Modes

Clock Cycles
Word, Byte
Long Word
NS
SS
SL NS
SL
SS

IR
DA
X

10
12
13

15
18
18

15
20
21

RA

10

15

15

1M

4
7
7
12
13

R - R XOR sre

Program Control

Mnemonics

Operands

CALL

dst

CALR

dst

Operation
Can Subroutine
Autodeerement SP
@SP-PC
PC - dst

Can Relative
Autodec rement SP
@ SP - PC
PC-PC + dst
(range -4094 to + 4096)

DJNZ
DBJNZ

R,dst

RA

11

11

Decrement and Jump If Non·Zero

11

R - R-l
If R .. 0: PC - PC
(range -254 to 0)

IRET"

13

16

+ dst

Interrupt Return

16

PS-@SP
Autoinerement SP

JP

ee,dst

IR
iR
DA
X

10
7
7
8

'Pnvileged Instructions; executed in system mode only.

460

15
7
8
8

15
7
10
11

(taken)
(not taken)

Jump Conditional
If ee is true: PC - dst

Program Control (Continued)

Mnemonics

Operends

RET

cc

SC

src

BIT
BITB

dst,b

BIT
BITB

dst,R

Addr.
Modes

Clock Cycles
Word, Byte
Long Word
SL NS
NS
SS
SS
SL
(taken)
(not taken)

Operation
Return Conditional
" cc is true. PC - @SP
Autoincrement SP

10
7

13
7

13
7

1M

33

39

39

System cell
Autolncrement SP
@SP-OldPS
Push Instruction
PS - System Call PS

R
IR
DA
X

4
8
10
11

4
8
11
11

4
8
13
14

Test Bit Static
Z flag - NOT dst bit specified by b

R

10

10

10

Teat Bit Dynamic
Z flag - NOT dst bit specified by
contents of R

N

I-.
••
I11III

Bit Manipulation

Addr.
Mod..

Clock Cycle,
Long Word
Word, Byte
NS
SS
SL NS
SS
SL

CI

Mnemonic,

Operends

Operltlon

RES
RESB

dst,b

R
IR
DA
X

4
11
13
14

4
11
14
14

4
11
16
17

Reaet Bit Stltlc
Reset dst bit specified by b

RES
RESB

dst,R

R

10

10

10

Reaet Bit Dynlmlc
Reset dst bit specified by contents R

SET
SETB

dst,b

R
IR

4
11

4
11

4
11

Sit Bit Stltlc
Set dst bit specified by b

SET
SETB

dst,R

R

10

10

10

Set Bit Dyn,mlc
Set dst bit specified by contents of R

TSET
TSETB

dst

R
IR
DA
X

7
11
14
15

7
11
15
15

7
11
17
18

Testlnd Set
S flag - MSe of dst
dst - all1s

ClockCyclas
Word, Byte
Long Word
SL
SL NS
SS
NS
SS

Rotate and Shift

Mnamonlcs

Oparends

Addr.
Mod..

RLDB

R,src

R

9

9

9

Rotlte Left Digit

RRDB

R,src

R

9

9

9

Rotate Right Digit

RL
RLB

dst,n

R
R

8 for n=1
7 for n=2

Rotate Left
Rotate dst by n bits (n = 1,2)

RLC
RLCB

dst,n

R
R

8 for n=1
7 for n=2

Rotlta Laft through Clrry
Rotate dst by n bits (n = 1,2)

RR
RRB

dst,n

R
R

6 for n=1
7 for n=2

Rotlta Right
Rotate dst by n bits (n = 1.2)

Operation

461

Rotate and Shift (Continued)

Mnemonics

Operands

RRC
RRCB

dst,n

SDA
SDAB
SDAl

dst,R

SDl
SDlB
SDll

dst,R

SlA
SLAB
SlAl

dst,n

Sll
SllB
Slll

dst,n

SRA
SRAB
SRAL

dst,n

SRL
SRlB
SRll

dst,n

Addr.
Modes

Clock Cycles
Word, Byte
long Word
Sl
NS
SS
Sl NS
SS

R
R

6 for n=1
7 for n=2

R

(15

+

Operation
Rotate Right through Carry
Rotate dst by n bits (n = 1,2)

3n)

(15

+

3n)

Shllt Dynamic Arithmetic
Shift dst left or right by contents of R

R

(15

+

3n)

(15

+

3n)

Shllt Dynamic logical
Shift dst left or right by contents of R

R

(13

+

3n)

(13

+

3n)

Shift lelt Arithmetic
Shift dst left by n bits

R

(13

+

3n)

(13

+

3n)

Shllt lelt logical
Shift dst left by n bits

R

(13

+

3n)

(13

+

3n)

Shllt Right Arithmetic
Shift dst right by n bits

R

(13

+

3n)

(13

+

3n)

Shllt Right logical
Shift dst right by n bits

Block Transfer and String Manipulation

Addr.
Modes

Clock Cycles
Word, Byte
Long Word
SL
NS
SS
SL NS
SS

Operation

20

Compare and Decrement

Mnemonics

Operands

CPD
CPDB

Rx,src,
Ry,cc

IR

CPDR
CPDRB

Rx,src,
Ry,cC

IR

CPI
CPDRB

Rx,src,
Ry,cc

IR

CPIR
CPIRB

Rx,src,
Ry,cc

IR

CPSD
CPS DB

dst,src,
R,cc

IR

CPSDR
CPSDRB

dst,src,
R,cc

IR

462

20

20

Rx - src
Autodecrement src address
Ry-Ry-l
(11

+

Compare, Decrement and Repeat

9n)

Rx - src
Autodecrement src address
Ry-Ry-l
Repeat until cc Is true or Ry = 0
20

20

20

Compare, Decrement and Repeat
Rx - src
Autodecrement src address
Ry-Ry-l

(11

+

Compere, Increment and Repeat

9n)

Rx - src
Autoincrement src address
Ry-Ry-l
Repeat until cc is true or Ry = 0
25

25

25

Compare String and Decrement
dst - src
Autodecrement dst and src addresses
R - R-l

(11

+

14n)

Compare String, Decrement and Repeat
dst - src
Autodecrement dst and src addresses
R - R-l
Repeat until cc is true or R = 0

Block Transfer and String Manipulation (Continued)

Addr.
Modes

Clock Cycles
Word, Byte
Long Word
SL NS
SS
SL
NS
SS

Operation

25

Compare String and Increment

Mnemonics

Operands

CPSI
CPSIB

dst.src,
R,cc

IR

CPSIR
CPSIRB

dst,src,
R,cc

IR

LDD
LDDB

dst,src,R

IR

LDDR
LDDRB

25

25

dst - src
Autolncrement dst and src addresses
R - R-l
(11

+

Compare String, Increment and Repeat

14n)

dst - src
Autoincrement dst and src addresses
R - R-l
Repeat until cc is true or R = 0
20

20

20

Load and Decrement
dst - src
Autodecrement dst and src addresses
R - R-l

dst,src, R

IR

(11

+

N

00

8W

-..

Load, Decrement and Repeat

9n)

dst - src
Autodecrement dst and src addresses
R - R-l
Repeat until R = 0

LDI
LDIB

dst,src,R

LDIR
LDIRB

dst,src,R

TRDB

dst,src,R

IR

20

20

20

IIICI

..,CIB

Load and Increment
dst - src
Autoincrement dst and src addresses
R - R-l

IR

(11

+

Load, Increment and Repeat

9n)

dst - src
Autoincrement dst and src addresses
R - R-l
Repeat until R = 0
IR

25

25

25

Translate and Decrement
dst - src (dst)
Autodecrement dst address
R - R-l

TRDRB

dst,src,R

IR

(11

+

Translate, Decrement and Repeat

14n)

dst - src (dst)
Autodecrement dst address
R - R-l
Repeat until R = 0

TRIB

dst,src,R

IR

25

25

25

Translate and Increment
dst - src (dst)
Autoincrement dst address
R - R-l

TRIRB

dst,src,R

IR

(11

+

Translate, Increment and Repeat

14n)

dst - src (dst)
Autoincrement dst address
R - R-l
Repeat until R = 0

TRTDB

srcl, src2, R

IR

25

25

25

Translate end Test, Decrement
RHI - src 2 (srcl)
Autodecrement srcl address
R - R-l

TRTDRB

srcl, src2, R

IR

(11

+

14n)

Translate and Test, Decrement
and Repeat
RHI - src2 (srcl)
Autodecrement srcl address
R - R-l
Repeat until R = 0 or RHI = 0

463
-~--~-~---.--~--

------~-~--

------- ----

Block Transfer and String Manipulation (Continued)
Clock Cycles
Word, Byte
Long Word
NS
SL NS
SS
SS
SL

Mnemonics

Operands

Addr.
Modes

TRTIB

src1. src2, R

IR

25

25

TRTIRB

src1, src2, R

IR

(11

+ 14n)

25

Operation
Trenslate and Test, Increment
RH1 - src2 (src1)
Auloincremenl src1 address
R - R-1
Translate and Test, Increment
and Repeat
RH1 - src2 (src1)
Auloincremenl src1 address
R - R-1
Repeal unlil R
0 or RH1
0

=

=

Input/Output

Addr.
Modes

Clock Cycles
Word, Byte
Long Word
NS
SL NS
SL
SS
SS

Operation

Mnemonics

Operands

IN·
INB·

R,src

IR
DA

10
12

10
12

10
12

Input
R - src

IND·
INOB·

dsl,src,R

IR

21

21

21

Input and Decrement
dsl - src
Aulodecrement dst address
R - R-1

IN DR·
INORB·

dst,src,R

IR

(11

+ 10n)

Input, Decrement and Repeat
dst - src
Autodecrement dst address
R - R-1
Repeat until R
0

=

INI·
INIB·

dst,src,R

IR

21

21

INIR·
INIRB·

dst,src,R

IR

(11

+ 10n)

21

Input and Increment
dst - src
Autoincrement dst address
R - R-1
Input, Increment and Repeat
dst - src
Auloincrement dst address
R - R-1
Repeat until R
0

=

OUT·
OUTB·

dst,R

IR
DA

10
12

10
12

10
12

Output
dst - R

OUTDo
OUTDB·

dst,src,R

IR

21

21

21

Output and Decrement
dst - src
Autodecrement src address
R - R-1

OTDR·
OTDRB·

dst,src, R

IR

(11

+ 10n)

Output, Decrement and Repeat
dst - src
Autodecremenl src address
R - R-1
Repeat until R
0

=

OUTI·
OUTIB·

dst,src,R

IR

21

• Privileged instructions, executed In system mode only

464

21

21

Output and Increment
dst - src
Autoincrement src address
R - R-1

Input/Output (Continued)

MnemonIcs

Operand,

Addr.
Moda,

OTIR'
OTIRB'

dst,src,R

IR

SIN'
SINB'

R,src

SIND'
SINB'

dst,src,R

SINDR'
SINDRB'

dst,src,R

SINI'

dst,src,R

Clock Cycle,
Long Word
Word. Byte
SL NS
NS
SS
SS
SL
(11

+ 10n)

Operetlon
Output, Increment and Repa't
dst - src
Autolncrement src address
R - R-l
Repeat until R = 0

DA

12

12

12

SpacIal Input
R - src

IR

21

21

21

Spacial Input and Decrement
dst - src
Autodecrement dst address
R - R-l

IR

(11

+ 10n)

N

i

Spacial Input, Dacrement and Repeat
dst - src
Autodecrement dst address
R - R-l
Repeat until R = 0

IR

21

21

21

SIN lB'

•

!

SpacIal Input and Increment
dst - src
Autoincrement dst address
R - R-l

SINIR'
SINIRB'

dst,src,R

SOUTo
SOUTB'

dst,src

SOUTD'
SOUTDB'

dst,src,R

SOTDR'
SOTDRB'

dst,srC,R

SOUTI'
SOUTIB'

dst,src,R

SOTIR'
SOTIRB'

dsl,src,R

IR

(11

+ 10n)

SpecIal Input. Increment and Repaat
dst - src
Autoincrement dst address
R - R-l
Repeat until R = 0

DA

12

12

12

SpecIal Output
dst - src

IR

21

21

21

SpacIal Output and Decrement
dst - src
Autodecrement src address
R - R-l

IR

(11

+ 10n)

SpecIal Output. Decrement and Repeat
dst - src
Autodecrement src address
R - R-l
Repeat until R = 0

IR

21

21

21

SpacIal Output and Increment
dst - src
Autoincrement src address
R - R-l

R

(11

+ 10n)

SpacIal Output, Increment and Repaat
dst - src
Auloincrement src address
R - R-l
Repeat until R = 0

• Privileged instructions, executed in system mode only.

465

CPU Control

Mnemonics

Operands

COMFLG

flags

Addr.
Modes

Clock Cycles
Word, Byte
Long Word
NS
SS
SS
SL
SL NS
7

7

7

Operation
Complement Flag
(Any combination of C,Z,S.PN)

01"

int

7

7

7

Disable Interrupt
(Any combination of NVI, VI)

EI"

int

7

7

7

Enable Interrupt
(Any combination of NVI, VI)

HALT"
LOCTL"

(8
CTlR,src

R

+

HALT

3n)

7

7

7

Load Into Control Register
CTlR -

LOCTl"

dst,CTlR

R

7

7

7

src

Load from Control Reglater
dst - CTlR

LOCTLB

FlGR,src

R

7

7

7

Load Into Flag Byte Register
FlGR -

LOCTlB

dstFlGR

R

7

7

7

Load from Flag Byte Register
dst -

LOPS"

src

IR
DA

X

MBIT"

12
16
17

16
20
20

16
22
23

7

7

7

src

FlGR

Load Program Status
PS - src

Test Multl·Mlcro Bit
Set S if MI is low;
clear S if MI is High

MREQ"

dst

R

(12

+

Multl·Mlcro Request

7n)

MRES"

5

5

5

Multl·Mlcro Reset

MSET"

5

5

5

Multl·Mlcro Set

NOP

7

7

7

No Operation

7

7

7

RESFLG

flag

Reset Flag
(Any combination of C.Z,S,PN)

SETFLG

flag

7

7

7

Set Flag
(Any combination of C,Z,S,PN)

• Privileged Instructions; executed in system mode only.

466

Extended Instructions
Clock Cycles
Function
Memory -

EPU -

CPU -

EPU

Memory

EPU Registers

Addr.
Modes

NS

IR
DA
X

(11
(15
(14

+ 3n)
+ 3n)
+ 3n)

(11
(15
(15

+ 3n)
+ 3n)
+ 3n)

(11
(18
(17

+
+
+

IR
DA
X

(11
(15
(14

+
+
+

3n)
3n)
3n)

(11
(15
(15

+ 3n)
+ 3n)
+ 3n)

(11
(18
(17

+ 3n)
+ 3n)
+ 3n)

(11

+ 4n)

(11

+ 4n)

(11

+ 4n)

55

5L

Operation

3n)
3n)
3n)

Write n words from EPU into memory

Load Memory from EPU

Load EPU from Memory
Read n words from memory into EPU

Load VMPU from EPU
Transfer n words from EPU to Z-VMPU registers

EPU - CPU Registers

(11

+ 4n)

(11

+ 4n)

(11

+ 4n)

Load EPU from VMPU
Transfer n words from Z-VMPU registers to EPU

Flags -

EPU

15

15

15

Load FCW from EPU
Load information from EPU into flags of the
Z-VMPU's Flag and Control Word

EPU -

Flags

15

15

15

Load EPU from FCW
Transfer information from Z-VMPU's Flag and
Control Word to EPU

EPU Internal Operations

(11

+ 4n)

(11

+ 4n)

(11

+ 4n)

Internal EPU Operations
Z-VMPU treats this template as a "no-operations";
it is typically used to initiate an internal EPU
operation. The character is a field in the
instruction.

467

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND ........... , .......... , .. -0.3Vto + 7.0V
Operating AmbientTemperature ......... ooe to + 70°C
Storage Temperature .............. - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only; opera·
tion ofthe device at any condition beyond those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

STANDARD TEST CONDITIONS
Standard test temperature/operating voltage ranges are
presented below. All voltages are referenced to GND. Positive current flows into the referenced pin.

Package Information section, Refer to the Literature List for
additional documentation.
+5V

• 0 °e to + 70°C, + 4. 75V .,; Vee"; + 5.25V
•

2.1K

-40 eto +85°e, +4.75V";Vee"; +5.25V
0

All ac parameters assume a load capacitance of 100 pf max,
except for parameter 6, which has a load capacitance of 50
pf max. Timing references between two output signals assume a load difference of 50 pf max.
The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the

Figure 18. Standard Test Load

DC CHARACTERISTICS
Symbol

Parameter

VeH
Vel
VIH
Vil
VOH
VOL
III
IOl
Icc

Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current

Min

Max

Unit

Condition

Vee- O.4
-0.3
2.0
-0.3
2.4

Vee+ 0.3
0.45
Vee+ 0.3
0.8

V
V
V
V
V
V
A
A
mA
mA
mA

Driven by External Clock Generator
Driven by External Clock Generator

0.4
±10
±10
300
400
400

IOH = -250A
IOl = +2.0mA
0.4 VIN + 2.4V
0.4 VOUT + 2.4V
4 + 6 MHz commercial
Extended Temp. Range
10 MHz Speed Range

AC CHARACTERISTICSt
Number

Symbol

Parameter

1
2
3
4
5
6

TcC
TwCh
TwCl
TIC
TrC
TdC(SNv)

7

TdC(SNn)
TdC(Bz)
TdC(A)
TdC(Az)
TdA(DR)
TsDR(C)
TdDS(A)
TdC(DW)
ThDR(DS)
TdDW(DS)

Clock Cycle Time
Ciock Width (High)
Clock Width (Low)
Clock Fall Time
Clock Rise Time
Clock I to Segment Number Valid
(50 pF load)
Clock I to Segment Number Not Valid
Clock t to Bus Float
Clock t to Address Valid
Clock t to Address Float
Address Valid to Read Data Required Valid
Read Data to Clock I Setup Time
DS t to Address Active
Clock t to Write Data Valid
Read Data to DS I Hold Time
Write Data Valid to DS t Delay

8
9
10
11
12
13
14
15
16

Z8003lZ8004
(4 MHz)
Max
Min
250
105
105

2000
2000
2000
20
20
130

20

Z8003A1Z8004A Z8003B/Z8004B
(8 MHz)
(10 MHz)
Min
Max
Min
Max
165
70
70

10
65
100
65
475*

30
80*

100
40
40

5

20
45*

40
50
40
180*
10
20*

75
0
195*

2000
10
10
70

55
75
55
305*

100
0
295*

2000
2000
2000
10
15
110

50
0
110*

t Timings are preliminary and subject to change. Units In nanoseconds,
468

2084·018

AC CHARACTERISTICSt (Continued)

Number

Symbol

Parameter

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

TdA(MR)
TdC(MR)
TwMRh
TdMR(A)
TdDW(DSW)
TdMR(DR)
TdC(MR)
TdC(ASf)
TdA(AS)
TdC(ASr)
TdAS(DR)
TdDS(AS)
TwAS
TdAS(A)
TdAz(DSR)
TdAS(DSR)
TdDSR(DR)
TdC(DSr)
TdDS(DW)
TdA(DSR)
TdC(DSR)
TwDSR
TdC(DSW)
TwDSW
TdDSI(DR)
TdC(DSf)
TwOS
TdAS(DSA)
TdC(DSA)
TdDSA(DR)

47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71

TdC(S)
TdS(AS)
TsR(C)
ThR(C)
TwNMI
TsNMI(C)
TsVI(C)
ThVI(C)
TsSGT(C)
ThSGT(C)
TsMI(C)
ThMI(C)
TdC(MO)
TsSTP(C)
ThSTP(C)
TsW(C)
ThW(C)
TsBRQ(C)
ThBRQ(C)
TdC(BAKr)
TdC(BAKf)
TwA
TdDS(S)
TsABT(C)
ThABT(C)

Address Valid to MREQ I Delay
Clock I to MFim I Delay
~Width (High)
~ I to Address Not Active
Write Data Valid to OS I (Write) Delay
MREQ I to Read Data Required Valid
Clock I MREQ I Delay
Clock I to AS I Delay
Address Valid to AS I Delay
Clock I to AS I Delay
AS I to Read Data Required Valid
OS I to AS I Delay
6§ Width (Low)
AS I to Address Not Active Delay
Addres~oat to OS (Read) I Delay
AS I to OS (Read) I Delay
OS (Read) I to Read Data Required Valid
Clock I to l5S I Delay
mll to Write Data Not Valid
Address Valid to 158 (Read) I Delay
Qgck I to 158 (Read) I Delay
OS (Read) Width (Low)
Q!gck I to OS (Write) I Delay
OS (Write) Width (Low)
158 (I/O) I to Read Data Required Valid
Clock I to OS (I/O) I Delay
OS (I/O) Width (Low)
AS I to DS~cknowledge) I Delay
Clock I to OS (Acknowledge) I Delay
OS (Acknowledge) I to Read Data
Required Delay
Clock I to Statu,LValid Delay
Status Valid to AS I Delay
RESET to Clock I Setup Time
RESET to Clock I Hold Time
NMI Width (Low)
N.MlJQ. Clock I Setup Time
~ NVI to Clock I Setup Time
YLNVi to Clock I Hold Time
SAT to Clock I Setup Time
SAT to Clock I Hold Time
MI to Clock I Setup Time
MI to Clock I Hold Time
Clock I to tiC Delay
STOP to Clock I Setup Time
STOP to Clock I Hold Time
WAIT to Clock I Setup Time
WA!I..lQ.Clock I Hold Time
BUSREQ to Clock I Setup Time
BUSREQ to Clock I Hold Time
Clock I to BUSACK I Delay
Clock I to BUSACK I Delay
&!dress Valid Width
OS I to STATUS Not Valid
ABORT I to Clock I Setup Time
ABORT I to Clock I Hold Time

Z8003lZS004
(4 MHz)
Max
Min

55'
80
210'
70'
55'

55'
70'
85'
70'
0
80'

370'
80
80
90
360'

205'
70
75'
180'

Z8003AJZ8004A zaOO3B1Z8004B
(10 MHz)
(8 MHz)
Max
Min
Max
Min

35'
135'
35'
35'

95

185'
410'
1065'

60
60

35'
35'
55'
45'
0
55'
45'
110'

255·
690'

120
455'
50·
180
0
100
140
110
20
70
0
180
0
140
0
50
10
90
10
150·
80·
50
0

110

120

100
100

15'
30'
20'
0
30'
130'
65

80
210'
90

80
0
30
10
80
10
95·
55·
30
0

85

40
140'

M
GO

70'
45
60

110'
75'
160'
410·

85
295'
30·
70
0
70
70
50
20
55
0
110
0

140'
45
40

25'
65'

85
185'

40

20'
80
220'

110'
330'
120

80'
20'
15'

230'

120
275'

20'
70

60
120·
60
65
165·

10·
50
0
50
50
40
10
40
0

60

80

85

75
75

0
50
0
20
5
60
5
50·
30'
25
0

70

60
60

'Clock-cycle-tlme-dependent characteristics. See table on
following page.
tTlmlngs are preliminary and subject to change. Units In
nanoseconds(ns).

469

IW

••-=
•c:t

COMPOSITE AC TIMING DIAGRAM

RES=E~T.

~....,~,---~~.t=

_ _ _ _ _ _ _, .

"l.

NMI

1-

51

V

ii, NYI

-

STOP

BUSREQ

BUSACK

------------~s'~~~

-~~
~~----------------t-------

~------~-----------+t.~~

ADDRESS

ADO-AD15

DATA IN

DATA OUT

MEMORY READ

J

MEMORY WRITE

J

INPUT/OUTPUT

INTERRUPT

~

--®-1:

s

BYT

470

~

/
J J-t----t-t-t-+-__r-..... J.-1---141\-':: ..!!...l.tl..i"'---"'I~ __
I-§CI ~~ Hv-

+

/J.--+----__--t-','i-+---,,.L

ACKNOWLEDGE...;'

RE
NORMA

~

kp--

----@}---.e:

--®-I

_
__ ~--

--+-~~~-------------------------~

CLOCK·CYCLE·TIME·DEPENDENT CHARACTERISTICS

Number
11
13
16
17
19
20
21
22
25
27
28
29
30
32
33
35
36
38
40
41
43
44
46
48
68
69

Symbol

TdA(DR)
TdDS(A)
TdDW(DS)
TdA(MR)
TwMRh
TdMR(A)
TdDW(DSW)
TdMR(DR)
TdA(AS)
TdAS(DR)
TdDS(AS)
TwAS
TdAS(A)
TdAS(DSR)
TdDSR(DR)
TdDS(DW)
TdA(DSR)
TwDSR
TwDSW
TdDSI(DR)
TwDS
TdAS(DSA)
TdDSA(DR)
TdS(AS)
TwA
TdDS(S)

Z8003
Equation
2TcC + TwCh -130 ns
TwCl-25 ns
TcC + TwCh - 60 ns
TwCh -50 ns
TcC-4O ns
TwCl-35 ns
TwCh -50 ns
2TcC-130 ns
TwCh-50 ns
2TcC -140 ns
TwCl-35 ns
TwCh-20 ns
TwCl-35 ns
TwCl-25 ns
TcC + TwCh - 150 ns
TwCl-30 ns
TcC-70 ns
TcC + TwCh - 80 ns
TcC-65 ns
2TcC-170 ns
2TcC-90 ns
4TcC + TwCI- 40 ns
2TcC + TwCh -150 ns
TwCh- 55 ns
TcC-90 ns
TwCl-25 ns

zao03A
Equation
2TcC + TwCh - 95 ns
TwCl-25 ns
TcC + TwCh - 40 ns
TwCh - 35 ns
TcC-30 ns
TwCl- 35 ns
TwCh -35 ns
2TcC-l00 ns
TwCh -35 ns
2TcC-l10 ns
TwCl-35 ns
TwCh -15 ns
TwCl-25 ns
TwCl-15 ns
TcC + TwCh - 105 ns
TwCl-25 ns
TcC- 55 ns
TcC + TwCh - 50 ns
TcC- 55 ns
2TcC-120 ns
2TcC-75 ns
4TcC + TwCl- 40 ns
2TcC + TwCh - 105 ns
TwCh -40 ns
TcC-70 ns
TwCl-15 ns

Z8OO3B
equation
2TcC + TwCh - 60 ns
TwCl-20 ns
TcC + TwCh - 30 ns
TwCh -20 ns
TcC-20 ns
TwCl-20 ns
TwCh -25 ns
2TcC-60 ns
TwCh - 20 ns
2TcC-60 ns
TwCl-25 ns
TwCh -10 ns
TwCl-20 ns
TwCl-10 ns
TcC + TwCh - 70 ns
TwCl-15 ns
TcC-35 ns
TcC + TwCh - 30 ns
TcC- 25 ns
2TcC-80 ns
2TcC-40 ns
4TcC + TwCl- 30 ns
2TcC + TwCh - 75 ns
TwCh -30 ns
TcC-50 ns
TwCl-l0 ns

I•
i

471

ORDERING INFORMATION
ZS003 Segmented VMPU, 4.0 MHz
4S-plnDIP

ZS004 Nonsegmented VMPU, 4.0 MHz
40-pinDIP

Z8003 PS
Z8003CS
Z8003 PE
Z8003CE

Z8004PS
Z8004CS
Z8004PE
Z8004CE

ZS003A Segmented VMPU, 6.0 MHz
4S-pinDIP

Z8004A Nonsegmented VMPU, 6.0 MHz
40-plnDIP

Z8003APS
Z8003ACS
Z8003APE
Z8003ACE

Z8004APS
Z8004ACS
Z8004APE
Z8004ACE

ZS003B Segmented VMPU, 10.0 MHz
4S-pinDIP

ZS004B Nonsegmented VMPU, 10.0 MHz
40-plnDIP

Z8003BPS
Z8003BCS
Z8003BPE
Z8003BCE

Z8004B PS
Z8004BCS
Z8004BPE
Z8004BCE

Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = O°Cto + 70°C
E = -40°C to +85°C
M*= -55°C to + 125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DIP, OOC to + 70°C.

t Available soon
* For Military Orders, contact your local Zil09 Sales Office for Military Electrical Specifications.

472

()()"2084-03

Z80,000

Family

Zilog

Zilog Z80,OOOTM Family
Provides 16· and 32·Bit
Microprocessor Solutions
Advance Information
March 19B5
Zilog continues its tradition of
state-of-the-art microprocessor components with the introduction of the
32-bit ZBO,OOO CPU and the ZB070
floating-point Arithmetic Processing
Unit (APU). These two devices bring
the performance of super minicomputers and mainframe computers
into the realm of microprocessorbased systems. The advances in
VLSI technology used in these integrated circuits herald a major breakthrough in the range of options
available to the systems designer.

The Z80,OOO. The zao,ooo CPU
provides the flexibility of a 16-bit
CPU. Oriented to applications in
which high throughput is required,
its file of 16 general-purpose registers handles bytes, words, and long
words with equal facility. The rich
instruction set combines powerful
addressing modes and operations
in a manner that aids assemblylanguage coding of time-critical
applications, and still provides the
completeness desirable for efficient
compiler-generated code.
The ZBO,OOO CPU can be configured under software control to use
16-bit logical addresses (ideally
suited for high-speed controller
applications) or 32-bit addresses (for
large-system tasks). The 32-bit address modes support both a linear
addressing space and an alternative
segmented addressing space,
which are selected by the user according to the application's
requirements.

Other system features include
System and Normal modes of operation, a sophisticated trapping
mechanism, a high-performance
bus structure, and built-in mUltiprocessor support. Finally, the device
has a high-performance interface to
the Za070 Arithmetic Processing
Unit so that the two devices can
operate in tandem to execute
floating-point instructions in the
CPU's instruction stream.
An on-chip cache and a memory
management unit (MMU), coupled
with a sophisticated instruction pipeline, enable the ZBO,OOO to execute
instructions at a rate of up to one
instruction per processor cycle. The
256-byte cache provides an automatic buffering mechanism to hold
the most recently fetched instructions and data on the chip itself.
Thus, subsequent references to
these items do not require lengthy
memory transactions but instead
can be fetched in a single processor
cycle. The memory management
unit on the chip contains all the information needed to translate the rnos!
recently used logical addresses
generated by the CPU into the physical addresses used by the memory
system. With each address translation, access attributes are automatically checked to determine whether
or not the access is permitted. The
MMU can be used to implement a
virtual memory or can be disabled
entirely for applications that do not
need memory management.

Peripheral Support. The ZBO,OOO
uses Zilog's Z_BUSTM, so the entire
ZBOOO family of circuits are available
for use with it. Multifunction Z-BUS
peripherals are extensively programmable, so each can be precisely
tailored to an application. Counting,
timing, and parallel I/O are tasks
handled by the ZB036 Z-CIO
CounterlTimer and Parallel I/O Unit,
which has three 16-bit counter/timers
and three I/O ports.
Data communications are the
domain of the Z8030 Z-SCC Serial
Communications Controller and the
Z8031 Z-ASCC Asynchronous Serial
Communications Controller, both
dual-channel multi protocol components that between them support all
popular communication formats.
Direct memory access components are supplied by the Z8016
Z-DTC DMA Transfer Controller, a
fast, dual-channel device that supports I/O-to-memory data transfers
without CPU intervention. In addition, the Z-BUS versions of the zaoo
can be used as I/O processors, with
iheir on-chip DMA channels programmed to transfer data in a
Z80,OOO-based system.

475

General-purpose control and
data-manipulation problems are
solved by the Z8090 Z-UPC Universal Peripheral Controller, a complete
microcomputer-on-a-chip that uses
the Z8 instruction set and features
three I!O ports and two 8-bit counter!
timers. The Z8038 Z-FIO FIFO Input!
Output Interface Unit can be

476

Interconnected with asynchronous
subsystems of a multiprocessor
system to interface any major microprocessor to the Z-BUS. Its buffer
depth can be expanded using the
Z8060 Z-FIFO Buffer Unit. Another
support peripheral circuit that can
be used with the Z80,OOO is the
Z8068 Z-DCP Data Ciphering
Processor.

The Z8581 CTC Clock Generator
Controller can be used to generate
the clock timing required by the
Z80,OOO. This device uses the same
technology as the Z80,OOO and
provides a power-on reset signal
and auxiliary clocking signals.
Finally, the Z8070 FPU Arithmetic
Processing Unit provides the
floating-point processing power for
the Z80,OOO CPU.

Z80,OOOTM CPU

Zilog

Preliminary
Product
Specification

April 1985

FEATURES
•

Full 32-bit architecture and implementation

•

4G (billion) bytes of directly addressable memory

•

Linear or segmented address space

•

Virtual memory management integrated with CPU

•

On-chip cache memory

•

General-purpose register file with sixteen 32-bit
registers

•

Nine general addressing modes

•

Numerous data types include bit, bit field, logical
value, signed integer, and string

•

Extended Processing Architecture supports floatingpoint operations

•

Regular use of operations, addressing modes, and
data types in instruction set

•

System and normal modes of operation with
separate stacks

•

Sophisticated interrupt and trap handling

•

Software is a binary-compatible
Z8000™ software

•

Hardware is compatible with other Z_BUSTM components

•

Mainframe performance

extension

of

GENERAL DESCRIPTION
The Z80,OOO CPU is an advanced, high-end 32-bit
microprocessor that integrates the architecture of a
mainframe computer into a single chip. While maintaining full compatibility with Z8000 family software and
hardware, the Z80,OOO CPU offers greater power and
flexibility in both its architecture and interface capability.
Operating systems and compilers are easily developed
in the Z80,OOO CPU's high-quality environment, and the
hardware interface provides for connection to a wide
variety of system configurations.
Addresses in the ZBO,OOO CPU are 32 bits. This allows
direct addressing of 4G bytes in each of four address
spaces: system-moCie data, system-mode instruction,
normal-mode data, and normal-mode instruction. The
CPU supports three modes of address representation.
The 16-bit compact addresses are compatible with
Z8000 non segmented mode. The 32-bit segmented addresses include both 16-bit offset, which is compatible
with Z8000 segmented mode, and 24-bit offset. In addition a full 32-bit linear address space is provided.

The CPU features a general-purpose register file with
sixteen 32-bit registers and nine operand addressing
modes. The various addressing modes allow encoding
choices for compact representation or for full 32-bit addressing. The in~truction set can operate on bit, bit field,
logical value, signed integer, unsigned integer, address,
string, stack, and packed decimal byte data types.
Logical and arithmetic instructions operate on bytes (8
bits), words (16 bits) and longwords (32 bits). The Extended Processing Architecture (EPA) supports floating-point
operations. In addition, the instruction set is highly
regular in combining operations, data types, and addressing modes. High-level language compilation is supported with instructions for procedure linkage, array index calculation, and bounds checking. Other instructions provide operating system functions such as system
call and control of memory management.
There are two main operating modes, system and normal, supported by separate stacks. User programs
operate in normal mode, while sensitive operating

477

J

I
9

system functions are performed in system mode. This
protects critical parts of the operating system from user
access. In addition, some instructions are privileged,
and execute only in system mode. Memory management
functions protect both system memory from user programs, and user memory from other users. Vectored,
nonvectored, and nonmaskable interrupts support realtime operating systems.
Memory management is fully integrated with the CPU;
no external support circuitry is necessary. A paging address translation mechanism is implemented. Registers
in the CPU pOint to address translation tables located in
memory; the most recently used table entries are kept in
a Translation Lookaside Buffer (TLB) in the CPU. The
CPU performs logical to physical address translation and
access protection for each memory reference. When a
logical memory reference causes a translation or protection violation, the state of the CPU is automatically
restored to restart the instruction. 1/0 ports can be
referenced either by dedicated instructions or by the
memory management mechanism mapping logical
memory addresses to 1/0 port addresses.
Extensive trapping facilities, such as integer overflow,
subrange out of bounds, and subscript out of bounds,
catch common run-time errors. Software debuggers can
use trace and breakpoint traps. Privileged instruction
traps and memory protection violation traps secure the

operating system from user programming errors or
mischief. The overflow stack allows recovery from otherwise fatal errors.
The CPU has full 32-bit internal address and data paths.
Externally, 32 pins time-multiplex the address and data.
The interface is compatible with the complete line of
Z-BUS peripherals. The hardware interface features
16-bit or 32-bit memory data path and programmable
wait states. Burst transfers and an on-chip cache for instructions and data help develop high-performance
systems. The interface supports multiprocessing configurations with interlocked memory references and two
types of bus request protocols. The system designer can
tailor the Z80,000-based system. to cost and performance needs.
In summary, the Z80,000 CPU meets and surpasses the
requirements of medium and high-end microprocessor
systems for the 1980s. Software program development
is easily accomplished with the CPU's sophisticated architecture. The highly pipelined design, on-chip cache,
and external interface support systems ranging from
dedicated controllers to mainframe computers. While
Zilog continues to develop support for the Z80,000 CPU,
Z8000 peripherals and development software are fully
compatible with this latest in Zilog's line of highperformance microprocessors.

REGISTERS
The Z80,000 CPU is a register-oriented processor offering
sixteen 32-bit general-purpose registers, a 32-bit Program
Counter (PC), a 16-bit Flag and Control Word (FCW), and
nine other special-purpose registers.
The general-purpose register file (Figure 1) contains 64
bytes of storage. The first 16 bytes (RLO,RHO, ... ,RL7,RH7)
can be used as accumulators for byte data. The first 16
words (RO,Rl ,... ,RI5) can be used as accumulators for
word data, as index registers (except RO), or for memory addresses in compact mode (except RO). Any longword register (RRO,RR2, ... ,RR30) can be used as an accumulator for
longword data, an index register in linear or segmented
mode (except RRO), or for memory addresses in linear or
segmented mode (except RRO). Ouadword registers
(ROO, R04, ... ,R028) can be used as accumulators for M ultiply, Divide, and Extend Sign instructions. This unique register organization allows bytes and words of data to be
manipulated conveniently while leaving most of the register
file free to hold addresses, counters, and any other data.
Two registers are dedicated to the Stack Pointer (SP) and
Frame Pointer (FP) used by Call, Enter, Exit, and Return

478

instructions. In compact mode, R15 is the Stack Pointer
and R14 ·the Frame Pointer. In linear or segmented
mode, RR14 is the Stack Pointer and RR12 is the Frame
Pointer.

ROO

R04

RQ8

I
I
I

RRO

7 RHO

RR2

7 RH2

7 RL2

o
o
o
o

7 RHI

o

0

RO, Rl

7 RH3 0 7 RL3 0

7 RLI

R2, R3

7 RH4

RR6

7 RH6

RR8

15

R8

o

15

R9

0

RR10

15

RIO

15

Rll

0

15

R12

15

R13

0

15

R14

o
o
o

15

R15

0

R0161 RR16
RR18

I

RR20

RR22

R02'1 RR24
RR26
R028

7 RLO

RR4

R0121 RR12
RR14

R020

o
o
o
o

7 RL4
7 RL6

7 RH5 0 7 RL5 0

R4. R5

7 RH7 0 7 RL7 0

R8. R7

31

0

31

0

31

0

31

0

31

0

31

0

RR28

31

0

RR30

31

0

I

Figure 1. General·Purpose Register File

207Hl01

The PC and FCW form the Program Status (Figure 2),
which is automatically saved for traps and interrupts.
The bits in FCW indicate operating modes, masks for
traps and interrupts, and flags set according to the result

of instructions. The remaining special registers are used
for memory management, system configuration, and
other CPU control (Figure 3).

15

8

1E/CISiNIEPAlvIE~VI~ usl TP I

Tic I z I S I PNI D I H I,V I 0

7

0

I

I~
-

'--

INTEGER OVERFLOW ENABLE (IV)
HALF CARRY (HI
DECIMAL-ADJUST (DI
PARITYIOVERFLOW (PNI
SIGN(s1
ZERO(Z)
CARRY(C)

TRACE(T)
TRACE PENDING (TP)
UNEARISEGMENTED MODE (ui)
NONVECTORED INTERRUPT ENAB LE (NVIE)
VECTORED INTERRUPT ENABLE (VIE)
EXTENDED PROCESSOR ARCHITECTURE(EPA)
SYSTEM/NORMAL MODE (SiNI

II

EXTENDED/COMPACT MODE (E/Ci

FLAG AND CONTROL WORD (PCW)
31

PROGRAM COUNTBR (PC)

Figure 2. Program Status Registers

ADDRESS SPACES
As shown in Figure 4, the CPU has three modes of address representation: compact, segmented, and linear.
The mode is selected by two control bits in the Flag and
Control Word register (Table 1). The Extended/Compact
(E/C) bit selects whether compact addresses (16 bits) or
extended addresses (32 bits) are used. For extended ad·
dresses the Linear/Segmented (US) bit selects whether
linear or segmented addresses are used.
The Load Address instruction can be used to manipulate
addresses in any mode of representation.
In compact mode, addresses are 16 bits. Address
calculations using compact addresses involve all 16 bits.
Compact mode is more efficient and less programconsuming for applications requiring less than 64K bytes
of program and less than 64K bytes of data. This etticien·

2071-002

cy is due to shorter instructions in compact mode, and
the fact that addresses in the register tile use word
rather than longword registers. Applications requiring
more than 64K bytes of either program or data should
use segmented or linear modes.

Table 1. Address Representation
Control Bits In FCW

EtC

US

o
o

o
o

Representation
Compact
Reserved
Segmented
Linear

479

31

PROGRAM STATUS AREA POINTER (PSAPI
31

NORMAL STACK POINTER (NSPI
31

30

10 I

MDTTD

II

NITTD

IG I

SDTTD

II

31

8

8

30

8

30

8
NLTB

G

SIZ

TF

PROT

SIZ

TF

PROT

SIZ

TF

PROT

SIZ

TF

7

NLTB

30

31

PROT

7

NLTB

G

31

7

NLTB

SITTD

7

TRANSLATION TABLE DESCRIPTOR REGISTERS

31

OVERFLOW STACK POINTER (OSPI

HARDWARE INTERFACE CONTROL REGISTER (HICRI
31

o

0

o

0

o

0

o

0

SYSTEM CONFIGURATION CONTROL LONG WORD (SCCLI

Figure 3. Special· Purpose Control Registers

480

2071.(1()3

15

(A) COMPACT ADDRESSES

31

16 15

30

I

SEGMENT
1

,

,

!

!

OFFSET
I

!

!

,

!

!

!

(i) 64K BYTE SEGMENT SIZE

31

24 23

30
SEGMENT
!

,

!

!

I

OFFSET
I

!

!

!

!

,

!

!

,

!

(II) 16M BYTE SEGMENT SIZE

(B) SEGMENTED ADDRESSES
31
,

,

,

,

,

!

(C) LINEAR ADDRESSES

Figure 4. Address Representations
In segmented mode, addresses are 32 bits. Segmented
addresses are composed of either a 15·bit segment
number and a 16·bit segment offset or a 7-bit segment
number and a 24-bit segment offset. Bit 31 of the address selects either of the two types of segmented addresses. Address calculations using segmented addresses involve only the segment offset; the segment
number is unaffected. In segmented mode, the address
space allows up to 32,768 segments of 64K-byte maximum size and up to 128 segments of 16M-byte maximum size. Many applications benefit from the logical
structure of segmentation by allocating individual objects, such as a program module, stack, or large data
structure, to separate segments.

tions using linear addresses involve all 32 bits. In linear
mode, the address space of 4G bytes is uniform and
unstructured. Many applications benefit from the flexibility of linear addressing by allocating objects at arbitrary positions in the address space.
Memory is byte addressable by the CPU. The address
used for multiple-byte data is the address of the mostsignificant byte. Multiple-byte data can be located at any
byte address with no alignment restrictions.
I/O ports can be addressed by either dedicated instructions or by the memory management mechanism mapping logical memory addresses to I/O ports. I/O ports
can be byte, word, or longword in size.

In linear mode, addresses are 32 bits. Address calcula-

NORMAL AND SYSTEM MODES
The CPU has two modes of operation, normal and
system, selected by the SIN bit in the Flag and Control
Word register. These modes impact on CPU operation in
three areas: privileged instructions, stack pOinters, and
memory management.
Since the most sensitive portions of the operating
system usually execute in system mode, separate stack
pointers are used to isolate the two operating modes.

2071.Q04

Some instructions, such as those performing I/O operations or accessing control registers, can only be executed in system mode; in addition, the memory
management mechanism allows access to some
memory locations in system mode only. Programs executing in normal mode can request services from the
operating system using the System Call instruction and
trap.

481

THEORY OF OPERATION
Figure 5 shows a block diagram of the Z80,000 CPU's internal organization, including the following major functional
units and data paths:
• The external interface logic controls transactions on the
bus. Addresses and data from the internal memory bus
are transmitted through the interface to the Z-BUS. The
Z-BUS is a time-multiplexed, address/data bus that connects the components of a microprocessor system.
• The cache stores copies of instruction and data memory
locations. Instructions are read from the cache on the instruction bus. Data is read from or written to the cache on
the memory bus. The cache also includes a copy of the
physical Program Counter, so that the logical addresses
of instructions are translated only for branches and when
incrementing the Program Counter across a page
boundary.
• The Translation Lookaside Buffer (TLB) translates logical
addresses calculated by the address arithmetic unit to
physical addresses used to access the cache.
• The address arithmetic unit performs all address calculations. This unit has a path to the register file for reading
base and index registers and another path to the instruction bus for reading displacements and direct addresses.
The result of the address calculation is transmitted to the
TLB.
• The register file contains the sixteen general-purpose
longword registers, Program Status registers, specialpurpose control registers, and several registers used to
store values temporarily during instruction execution.
The register file has one path to the address arithmetic
unit and two paths to the execution arithmetic and logic
unit.
• The execution arithmetic and logic unit calculates the
results of instruction execution, such as add, exclusiveOR, and simple load. This unit has two paths to the register file on which two operands can be read
simultaneously or one can be written. One of the paths to
the register file is multiplexed With a path from the memory bus.
• The instruction decoding and control unit decodes instructions and controls the operation of the other fu nctional units. This unit has a path from the instruction bus
and two programmable logic arrays for separate microcoded control of the two arithmetic units. This unit also
controls exception handling and TLB loading.
All of the functional units and data paths listed above are 32
bits wide.

482

The operation of the CPU is highly pipelined so that several
instructions are simultaneously in different stages of execution. Thus, the functional units effectively operate in parallel
with one instruction being fetched while an address is calculated for another instruction and results are stored for a third
instruction.
Figure 6 shows the six-stage, synchronous pipeline. Instructions flow through each stage of the pipeline in sequence.
The various pipeline stages can be working simultaneously
on separate Instructions or on separate portions of a single
complex instruction. Each pipeline stage operates in one
processor cycle, which is composed of two clock cycles,
called +1 and +2. Thus, a processor cycle is 200 ns with a 1a
MHz clock or 80 ns with a 25 MHz clock.
The instruction-fetch stage increments the Program Counter
and initiates instructions fetched from the cache. The
instruction-decoding stage receives and decodes instructions to set up control of the address-calculation stage.
The address-calculation stage can generally calculate a
memory address in one processor cycle, except for Base Index, Relative, and Relative Index addressing modes, which
require multiple cycles. After the logical effective address
has been calculated, the corresponding physical address is
provided by the TLB. The operand-fetch stage fetches the
data from the cache and latches it into a holding register.
The execution stage performs data manipulations. Byte,
word, and longword results are generally calculated in one
processor cycle, but certain instructions, such as multiply
and block-move operations, require multiple cycles. During
the execution stage, results are stored to registers. Results
are stored to the cache and external memory during the
operand-store stage. The flags are also set during the
operand-store stage.
The cache can handle two references during a processor
cycle. Instruction fetches use the +2 clock cycle for tag comparison and +1 for data access. Either an operand fetch or
store can use +1 for tag comparison and +2 for data access.
The pipeline allows single instructions, like register-toregister load and memory-to-register add, to execute at a
rate of one per processor cycle. Thus, the peak performance of the CPU is 12.5 million instructions per second
(MIPS) with a 25 MHz clock. In practice, the actual performance is reduced to approximately one-third of the peak because of delays due to the execution of multiple-cycle
Instructions,. Interference between instructions in the pipeline, and main memory accesses for cache and TLB misses.

Z·BUS

-------,

r------

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IL ________________

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

MEMORY BUS

CACHE
DATA

CACHE
ADDRESS TAGS

INSTRUCTION REGISTER

PHYSICAL PC

TRANSLATION
LOOKASIDE
BUFFER

INSTRUCTION
DECODING
ANO
CONTROL

UNIT

REGISTER
FILE

EXECUTION ARITHMETIC
AND LOGIC UNIT

I

~

Figure 5. ZSO,OOO CPU Functional Block Diagram

INSTRUCTION FETCH
PROGRAM

COUNTER
INCREMENT

CACHE TAG
COMPARE

-

INSTRUCTION DECODING

CACHE INSTRUCTION
READ
MICROWORD

GENERATION

OPERAND FETCH

ADDRESS CALCULATIONS
ADDRESS ARITHMETIC
CALCULATION

f.-+

TLBTAG
COMPARE

-

CACHE TAG
COMPARE
CACHE DATA READ

EXECUTION

-

REGISTER READ
AW CALCULATION

REGISTER WRITE

OPERAND STORE

r-

rlAG SETTING
CACHE DATA WRITE
MEMORY WRITE

TLB DATA READ

Figure 6. Instruction Pipeline

483

MEMORY MANAGEMENT
The CPU and the operating system cooperate in translating
logical to physical addresses and protecting memory for execute, read, and write accesses. The CPU implements a
paging translation mechanism similar to that in most mainframe and super-minicomputers. The operating system creates translation tables in memory, then initializes pointers to
the tables in control registers. The CPU automatically references the tables to perform address translation and access
protection. The CPU enables the operating system to implement efficient virtual memory by marking pages that have
been referenced or modified and by automatically recovering from address translation faults to allow instruction restart.
The paging translation scheme implemented by the CPU divides the logical address spaces into pages and the physical address space into frames. The logical pages and
physical frames are each 1K bytes. A logical page, which is
specified by the 22 most-significant bits of the logical ad-

dress, can be mapped into any physical frame, which is
specified by the 22 most-significant bits of the physical address. The 10 least-significant bits, which specify the byte
within a page or frame, are not translated. For each memory
reference, the CPU translates the logical address to the corresponding physical address and also tests whether access
to the memory location is permitted. For most references
the information needed to perform the translation is stored in
the CPU Translation Lookaside Buffer (TLB). The TLB (Figure 7) stores the translation information for the 16 most recently referenced pages in a fully associative memory. Only
when information to translate the page is missing from the
TLB does the CPU reference translation tables in memory.
In the case of a TLB miss, the CPU translates the logical address using the procedure described below and the translation information is loaded into the TLB entry of the least
recently referenced page.

10 9

31

LOGICAL ADDRESS

I

I PAGE OFFSET I

PAGE ADDRESS

L
...: >"
TRANSL ATION
LOOKA SIDE
BUFFER

PHYSICAL
FRAME
ADDRESSES

LOGICAL PAGE
ADDRESS TAGS

~,l.

31

PHYSICA L ADDRESS

I

10 9

FRAME ADDRESS

....

;..

0

IFRAMEOFFSETI

Figure 7. Address Translation Using the TLB

--

TA BLE DESCRIPTOR
REGISTERS

LEVEL 1
TABLE

31

LOGICAL ADDRESS

I

I
L1

+
PAGE TABLE

LEVEL 2
TABLE

24 23

I

16 151109
L2

L

1
TRANSLATION
LOOKASIDE
BUFFER

P

1

0
P·OFFSET

PAGE TABLE
I

L--------r--------~----~

ENTRY

~
LOGICAL PAGE
ADDRESS TAGS

PHYSICAL
FRAME
ADDRESSES

Figure 8. Automatic Loading of the TLB Using Tables in Memory

484

2071-005, ooe

The address translation mechanism is a three-level paging
scheme. A logical address is partitioned into an 8-bit level-1
field (L 1), an 8-bit level-2 field (L2), a 6-bit page number field
(P), and a 1a-bit page offset field (P-OFFSET). During translation, the L1, L2, and P fields are used as indexes into tables in physical memory. The TF field of the Translation Table
Descriptor register can be programmed to selectively skip
the first and secondlevel tables to reduce both the storage
space needed for tables and the number of references necessary to perform translation when the information to translate a page is missing from the on-chip TLB.
To load the TLB (Figure 8), the CPU selects one of four table
descriptor registers according to the address space for the
reference: system instruction, system data, normal instruction, or normal data. The table descriptor register points to
the beginning of the level-1 table in memory; the L1 field of
the logical address is used as an index into this table to selectthe level-1 table entry. Next, the level-1 table entry points
to the beginning of the level-2 table; the L2 field of the logical
address is used as an index into this table to selectthe level-2
table entry. After this, the level-2 table entry points to the beginning of the page table in memory; the P field of the logical
address is used as an index into this table to select the page
table entry. The page table entry contains the physical address ofthe frame corresponding to the logical address. The
CPU then loads the logical page address and physical
frame address into the TLB.
When bit31 inthe page table entry is 1, the frame is in physical 1/0 space. The CPU uses 1/0 status and timing for the
reference. Thus, the address translation process allows protected access to memory-mapped 1/0 devices.

Access protection information (Table 2) is encoded in the
4-bit PROT field contained in the Translation Table Descriptor, level-1 table entry, level-2 table entry, or page table entry.
During the translation process, a PROT field is encountered
at each level. The first PROT field with value other than 1000
is selected; the other PROT fields are ignored. The protection code specifies the types of access (execute, read, and
write) permitted in normal and system modes. A value of
1000 in the page table entry indicates no access.
There are several optional features that allow the number of
levels and the size of tables to be reduced. When memory
address spaces are not separated, two or more of the translation table descriptor registers can be loaded with the same
value so that tables are held in common. The table descriptor register can specify that either or both of the level-1 and
level-2 tables should be skipped during the translation process. Level-1 tables can be skipped when a 24-bit logical address space is sufficient, both level-1 and level-2 segment
tables can be skipped for compact addresses, and level-2
tables can be skipped for compatibility with Z8000 segmented addresses. The table size can be reduced by allocating only 256, 512, or 768 bytes for the tables; the
remaining table entries are assumed invalid. The tables can
be allocated efficiently for downward growing stacks by setting the G bit of the translation table descriptor or level-1
table entry.
During execution of an instruction, if an invalid translation table entry is encountered or a protection violation is detected,
the CPU traps to the operating system. The CPU automatically saves the state of registers and memory so the instruction can simply be restarted.

Figures 9 and 10 show the translation and table entry
formats.
31 30

8

II

I

I

I

7

I

I I
I

I

T L
L-

TABLE FORMAT (TF)
TABLE SIZE (SIZ)
PROTECTION (PROT)
NEXT LEVEL TABLE
BASE (NLTB)
GROWTH DIRECTION (G)

(TF)

00
01
10
11

THREE LEVELS
SKIP LEVEL 2 TABLES
SKIP LEVEL 1 TABLES
SKIP LEVEL 1 AND LEVEL 2 TABLES

TABLE SIZE
(5IZ)

VALID TABLE ENTRIES
Q

=

a

Q

= 1

01

o TO 63
o TO 127

10

o TO

191

128 TO 255

11

oTO 255

192 TO 255

00

oTO 255
64 TO 255

Figure 9. Translation Table Descriptor

2071-007

485

31 30

8

II

!

I

7

I

!

0

I 101

I

---r-

L-

L--

I

VALID (V)
TABLE SIZE (SIZ)

' - - - - - - - PROTECTION (PROT)
~!~~ ~J~TE~ TABLE

'-__________________

L .- - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

GROWTH DIRECTION (G)

LEVEL 1 TABLE ENTRY
31 30

8
!

7

)I

!

I

L-

VALID (V)

' - - - - - - - PROTECTION (PROT)
' - - - - - - - - - - - - - - - - - - - NEXT LEVEL TABLE
BASE (NLTB)

LEVEL 2 TABLE ENTRY
31 30

10 9

III

I

,

I

8

I I
!

7

I

IIIII
I I I ~ ::::::::;" ,.
!

,

E

MODIFICATION (M)
NONCACHEABLE (NC)
PROTECTION (PROT)
UNUSED

' - - - - - - - - - - - - - - - - - - - - FRAME ADDRESS (FA)
' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I/O

PAGE TABLE ENTRY

Figure 10. Table Entry Formats
Table 2. Protection Field Encoding
Encoding

System

Normal

0000
0001
0010
0011

NA

NA
NA

0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

RE
RE
RE
E
E
R
R
Next

RW
RW
RW
RWE
RWE
RWE
RWE

E
RE
NA

E
NA

R
Next
NA

Several instructions are provided to help the operating
system control memory management. The Purge TLB in·
structions are used to purge the TLB of a single entry,
normal mode entries, or all entries. The Load Physical
Address instructions translate logical addresses into
physical addresses, and set the flags to verify access
permission for system call parameters. The Load Nor·
mal Data and Load Normal Instruction instructions allow
system mode programs to reference normal memory
spaces.
The memory management mechanism can be selective·
Iy enabled for normal and system space references by
using the SX and NX bits of the System Configuration
Control Longword register.

R
RW
NA

E
RE
RWE

NA-no access is permitted
A-read access Is permitted
W-write access is permitted

E-execute access IS permitted
Next-use the protection field of the next level translation table; for page
table entries, a PROT field of 1000 indicates no access IS permItted.

486

2071-008

EXCEPTIONS
The CPU supports four types of exceptions: reset, bus
error, interrupts, and traps. A reset exception occurs
when the RESET line is activated; this causes the CPU to
be reset to an initialized state. A bus error exception occurs when external hardware indicates an error on a bus
transaction. An interrupt is an asynchronous event that
typically occurs when a peripheral device needs attention. A trap is a synchronous event that occurs when a
particular condition is detected during execution of an instruction.
In responding to a reset exception, the CPU fetches the
program status (FCW and PC) from physical address 2.
In responding to other exceptions, the CPU pushes the
old program status onto the system stack along with information specific to the type of exception. The CPU
then fetches a new program status from the table
designated by the Program Status Area Pointer control
register.
During exception processing, the mode of address
representation for the system Stack Pointer and Program Status Area Pointer is either linear or segmented,
selected by the XLiS bit in the System Configuration Control Longword register. Three types of interrupts are supported: vectored, nonvectored, and nonmaskable. The
vectored and nonvectored interrupts have mask bits in
the FCW. All interrupts read an identifier word from the
bus during an interrupt acknowledge transaction and
save the word on the system stack. Vectored interrupts
use the lower byte of this word to select a unique PC
value from the Program Status Area.
The CPU recognizes twelve trap conditions.
•

Extended Instruction trap occurs when an Extended
Processing Architecture instruction is executed and
the EPA bit in the FCW is clear.

•

Privileged Instruction trap occurs when an attempt is
made to execute a privileged instruction in normal
mode.

•

System Call trap occurs when the System Call instruction is executed to request service from the
operating system.

•

Address Translation trap occurs when an address
translation or access protection violation is
detected.

•

Unimplemented Instruction trap occurs when an attempt is made to execute an instruction with a
reserved bit pattern.

•

Odd PC trap occurs when an odd-byte address is
loaded into the PC.

•

Trace trap occurs after execution of an instruction
when tracing is enabled by setting the T bit in the
FCW.

•

Breakpoint trap occurs when the Breakpoint instruction is executed, usually to invoke a debugging or
monitoring program.

•

Conditional trap occurs when the Conditional trap instruction is executed and the specified condition
code is satisfied. This trap can allow detection of
user-defined exceptions.

•

Integer Arithmetic trap occurs when any of the
following three error conditions is detected:
• Integer Overflow error occurs when overflow is
detected during execution of an integer arithmetic
instruction and the IV bit in the FCW is set.
• Bounds Check error occurs when the Check instruction is executed and the source operand is
out of bounds.
• Index error occurs when the Index instruction is
executed and the subscript operand is out of
bounds.

In descending order, the priority of exceptions is: reset,
bus error, trap (other than trace), nonmaskable interrupt,
vectored interrupt, and non vectored interrupt. Trace
Trap uses two control bits, T and TP, so that when tracing is enabled, exactly one trace trap occurs after each
instruction is executed.
When an Address Translation trap occurs for the system
stack, the CPU cannot save the program status and
other exception information on the system stack. The
system can still recover from this otherwise fatal error
because the CPU saves the information on the overflow
stack designated in physical memory by the Overflow
Stack Pointer control register.

ADDRESSING MODES
The CPU locates operands (the data manipulated by instructions) in registers, memory, I/O ports, or in the instruction. The location of an operand is specified by one of nine
addressing modes (Figure 11): Register (R), Immediate
(1M), Indirect Register (IR), Direct Address (DA) , Index (X),
Base Address (BA), Base Index (BX), Relative Address (RA) ,
and Relative Index (RX). Most operations can be used with
any addressing mode; however, some operations are restricted. Instruction encoding provides compact representation for the most frequently used addressing modes.

The term Extended Addressing Modes (EAM) refers to the
following addressing modes that require one or more extra
words to be added to the opcode.
• In compact mode: DA and X (X is equivalent to BA)
• In linear or segmented modes: DA, X, BA, BX, RA, and
RX

487

Addressing Mode

Operand Addressing

In the Instruction

Operand Value
In Memory

In a Register

R
Register

REGISTER NUMBER

~I

OPE~AND

The contents of the
register

1M
Immediate

In the instruction

OPERAND

*IR
Indirect
Register

REGISTER NUMBER

Direct
Address

ADDRESS

~I[~A~D~D~RE~S~S=]-----""'~!I~O:PE~R~A~ND~

DA

.I

OPERAND

*X
Index

t~~j--='=NDE=X=-h~~+Ir---.....,
__~~I OPERAND
t~~~~~~__~I:.~=E:AD:D:RE:S:S~~

The contents 01 the
location whose
address is the
contents 01 the Base
register, plus the
displacement in the
instruction

~.

OPERAND

*BX

The contents 01 the
location whose
address is the
contents of the Base
register, plus the
contents 01 the Index
register, plus the
displacement in the
instruction

REGISTER NUMBER

Base
Index

REGISTER NUMBER
DISPLACEMENT

RA
Relative
Address

PC ADDRESS

h

[~D~IS~PLA~C~EM~E~N~TJf-~====::'-':"0-----+-1

OPERAND

*RX
Relative
Index

The contents 01 the
location whose
address is in the
instruction
The contents of the
location whose
address is the address
in the instruction, plus
the contents 01 the
Index Register

*BA
Base
Address

The contents 01 the
location whose
address is in the
register

~~====~

0--1 OPERAND

The contents 01 the
location whose
address is the
contents 01 the
Program Counter, plus
the displacement in
the instruction
The contents of the
location whose
address is the
contents of the
Program Counter, plus
the contents of the
Index register, plus the
displacement in the
instruction

*RO and RRO cannot be used lor Indirect, Base, or Index registers
Figure 11. Addressing Modes

488

2071.Q09

DATA TYPES
The CPU supports operations on the following data
types.
•
•

Bit
Bit field-1 to 32 contiguous bits within a longword

•

Signed integer-byte, word, longword, and quad·
word

•

Unsigned integer-byte, word, longword, and quad·
word

•

Logical value-byte, word, and longword

•

Address-word or longword

•

Packed BCD integer-byte

•

Stack-word and longword

•

String-dynamic length byte, word, and longword

FLAGS AND CONDITION CODES
Arithmetic, logical, and many other instructions affect
the six flag bits (C, Z, S, PIV, D, and H) in the FCW to pro·
vide information about an operation's result. Generally,
C indicates carry or borrow from the result, Z indicates
the result is zero, S indicates whether the result is

negative or positive, and PIV indicates parity or overflow.
D and H are used for decimal arithmetic.
Jump, Test Condition Code, and several other instruc·
tions test the state of the flags. The conditions that can
be tested are shown in Table 3.

Table 3. Flags and Condition Codes
Code

Meaning

F

Always false

T

Always true

Z

Zero

Flag Setting

Binary
0000
1000

Z=1

0110

NZ

Not zero

Z=O

1110

C

Carry

C = 1

0111
1111

NC

No carry

C=O

PL

Plus

S=O

1101

MI

Minus

S= 1

0101

NE

Not equal

Z=O

1110

EO

Equal

Z=1

0110
0100

OV

Overflow

V=1

NOV

No overflow

V=O

1100

PE

Parity even

P= 1

0100
1100

PO

Parity odd

P=O

GE

Greater than or equal

(S XOR V) = 0

1001

LT

Less than

(SXOR V) = 1

0001

GT

Greater than

(Z OR (S XOR V)) = 0

1010

LE

Less than or equal

(Z OR (S XOR V)) ~ 1

0010

UGE

Unsigned greater than or equal

C=O

1111

ULT
UGT

Unsigned less than
Unsigned greater than

C = 1
((C = 0) AND (Z = 0)) = 1

0111

ULE

Unsigned less than or equal

(C OR Z) = 1

0011

1011

Some of the condition codes correspond to identical flag settings: i.e., Z·EO, NZ·NE, C·ULT, NC-UGE, PE-OV, and PO-NOV. If no
condition code is specified, the default condition is T (always true).

489

INSTRUCTION SET SUMMARY
The CPU provides 11 types of instructions:

•

Input/Output

•

Load and Exchange

•

CPU Control

•

Arithmetic

•

Extended Instructions

•

Logical

•

Program Control

•

Bit Manipulation

Instructions are encoded in one or more words, located
in memory at even addresses. The generic instruction
mnemonic indicates the instruction operates on words;
addition of a "B" or "L" suffix to the mnemonic indicates operation on bytes or longwords, respectively.
For example: CLR operates on words, CLRB on bytes,
and CLRL on longwords.

•

Bit Field

•

Rotate and Shift

•

Block Transfer and String Manipulation

Load and Exchange
Mnemonic

Operands

Addressing Modes

Operation

CLR
CLAB
CLRL

dst

dst: R,IR,EAM

Clear

CVTBW
CVTBL
CVTWB
CVTWL
CVTLB
CVTLW

dst,src

CVTUBW
CVTUBL
CVTUWB
CVTUWL
CVTULB
CVTULW

dst,src

EX
EXB

dst,src

dst dst: R
src: R,IR,EAM
or
dst: IR,EAM
src: R

dst,src

LOA

dst,src

LOAR

LOK
LOKL

dst,src

dst,n

Convert
dst -

Convert Unsigned

dst: R
src: R,IR,EAM

Exchange

dst: R
src: R,IM,IR,EAM*
or
dst: IR,EAM*
src: R,IM
dst: R
src: EAM*

dst: R
src: RA

dst: R

n: 1M

dst -

dst -

490

convert (src)

src

Load
dst -

src

Load Address
dst -

Address (src)

Load Address Relative
dst -

Address (src)

Load Constant
dst - n
(n
0 .. 15)

=

'Compact mode allows BX with no displacement for EAM.

convert (src)

dst: R
src: R,IR,EAM
or
dst: IR,EAM
src: R

EXL
LO
LOB
LOL

0

Load and Exchange (Continued)
Mnemonic

Operands

Addressing Modes

Operation

LDM

dst,src,n

dst: R
src: IM,IR,EAM
n: 1M
or
dst: IR,EAM
src: R
n: 1M

Load Multiple

LDML

mask,src
or
dst,mask

LOR
LDRB
LDRL

dst,src

pOP
POPL

dst,src

PUSH
PUSHL

dst,src

mask: 1M
src: IM,IR,EAM
or
dst: IR,EAM
mask: 1M
dst: R
src: RA
or
dst: RA
src: R
dst: R,IR,EAM
src: IR

dst: IR
src: R,IM,IR,EAM

dst -

src (n words)

Load Multiple Long
dst (register mask) - src
or
dst - src (register mask)

II

$J

Load Relative
dst -

8

src

Q
CI

Pop
dst - src
Autoincrement src address

Push
Autodecrement dst address
dst - src

Arithmetic
Mnemonic

Operands

Addressing Modes

Operation

ADC
ADCB
ADCL

dst,src

dst: R
src: R

Add with Carry

ADD
ADDB
ADDL

dst,src

dst: R
src: R,IM,IR,EAM

Add

CHK
CHKB
CHKL

dst,src

CP
CPB
CPL

dst,src

DAB
DEC
DECB
DECL

dst -

dst -

dst + src + C

dst + src

dst: R
src: IM,IR,EAM

Check

dst: R
src: R,IM,IR,EAM
or
dst: IR,EAM
src: 1M

Compare

dst

dst: R

Decimal Adjust

dst,n

dst: R,IR,EAM
n: 1M

Decrement

compare dst with src bounds
if out of bounds then trap

dst - src

dst - dst - n
(n
1..16)

=

491
~~_,_e

-------~.--.-----

~-

--.~.---.--~-------

___

,~_

..

Arithmetic (Continued)
Mnemonic

Operands

Addressing Modes

Operation

DECI
DECIB

dst,n

ds!: IR,EAM
n: 1M

Decrement Interlocked
dst - dst - n
(n
1.. 16)

=

DIV
DIVL

dst,src

DIVU
DIVUL

dst,src

EXTS
EXTSB
EXTSL

dst

INC
INCB
INCL

dst,n

INCI
INCIB

dst,n

ds!: R
src: R,IM,IR,EAM

ds!: R
src: R,IM,IR,EAM

ds!: R

Divide
dst (low) - dst DIV src
dst (high) - dst REM src

Divide Unsigned
dst (low) - dst DIV src
dst (high) - dst REM src

Extend Sign
dst -

ds!: R,IR,EAM
n: 1M

sign_extend (dst (low))

Increment
dst - dst + n
(n
1.. 16)

=

ds!: IR,EAM
n: 1M

Increment Interlocked
dst - dst + n
(n
1.. 16)

=

492

INDEX
INDEXL

dst,sub,src

MULT
MULTL

dst,src

MULTU
MULTUL

dst,src

NEG
NEGB
NEGL

dst

SBC
SBCB
SBCL

dst,src

SUB
SUBB
SUBL

dS!,src

TESTA
TESTAB
TESTAL

dst

ds!: R
sub: R
src: IM,IR,EAM
ds!: R
src: R,IM,IR,EAM
ds!: R
src: R,IM,IR,EAM
ds!: R,IR,EAM

Index
calculate array index:
check, scale, and accumulate

Multiply
dst -

dst (low) • src

Multiply Unsigned
dst -

dst (low) • src

Negate
ds! - ds!

ds!: R
src: R

Subtract with Carry

ds!: R
src: R,IM,IR,EAM

Subtract

ds!: R,IR,EAM

Test Arithmetic

dst -

ds! -

ds! -

dst - src - C

dst - src

0

Logical
Mnemonic

Operands

Addressing Modes

Operation

AND
ANDB
ANDl

dst,src

dst: R
src: R,IM,IR,EAM

And

COM
COMB
COMl

dst

OR
ORB
ORl

dst,src

TCC
TCCB
TCCl

cC,dst

TEST
TESTB
TESTl

dst

XOR
XORB
XORl

dst,src

dst: R,IR,EAM

dst -

dst AND src

Complement
dst -

NOT dst

dst: R
src: R,IM,IR,EAM

Or

dst: R

Test Condition Code

dst -

dst OR src

I

if cc then
dst - dst OR 1
dst: R,IR,EAM

Test

ft

:I

dst OR 0
dst: R
src: R,IM,IR,EAM

Xor
dst -

dst XOR src

Program Control
Mnemonic

Operands

Addressing Modes

BRKPT

Operation
Breakpoint
(breakpoint trap)
Push PS onto System Stack
Push instruction
PS - Breakpoint PS

CAll

dst

dst: IR,EAM

Call
Autodecrement SP
@SP - PC
PC - Address (dst)

CAlR

dst

dst: RA

Call Relative
Autodecrement SP
@SP - PC
PC - Address (dst)

DJNZ
DBJNZ
DlJNZ

cnt,dst

cnt: R
dst: RA

Decrement and Jump if Not Zero
cnt - cnt - 1
if cnt
0 then
PC - Address (dst)

*

493

Program Control (Continued)
Mnemonic

Operands

Addressing Modes

Operation

ENTER

mask,siz

mask: 1M
siz: 1M

Enter Procedure

EXIT

Push registers (mask)
Push FP
Push mask
Push 0 (exception handler)
FP -SP
SP-SP + siz
update integer overflow mask

Exit Procedure
SP - FP
Pop exception handler
Pop mask
Pop FP
Pop registers (mask)
restore integer overflow mask

JP

cC,dst

dst: IR,EAM

Jump
if cc then
PC - Address (dst)

JR

cC,dst

dst: RA

Jump Relative
if cc then
PC - Address (dst)

RET

Return

cc

if cc then
PC - @SP
Autoincrement SP

SC

src

src: 1M

System Call
(system call trap)
Push PS onto System Stack
Push instruction
PS - System Call PS

TRAP

cC,src

src: 1M

Trap Conditional
if cc then
(condition trap)
Push PS onto System Stack
Push instruction
PS - Conditional Trap PS

494

Bit Manipulation
Mnemonic

Operands

Addressing Modes

Operation

BIT
BITB
BITL

dst,src

dst: R,IR,EAM
src: 1M
or
dst: R
src: R

Test Bit

RES
RESB
RESL

dst,src

dst: R,IR,EAM
src: 1M
or
dst: R
src: R

Reset Bit

SET
SETB
SETL

dst,src

TSET
TSETB

dst

Z -

NOT dst (src)

dst(src) -

0

dst: R,IR,EAM
src: 1M
or
dst: R
src: R

Set Bit

dst: R,IR,EAM

Test and Set

dst(src) -

II
0

1

I

C':II

•
CI

S - dst(MSB)
dst - -1

Rotate and Shift
Mnemonic

Operands

Addressing Modes

Operation

RL
RLB
RLL

dst,n

dst: R
n: 1M

Rotate Left

RLC
RLCB
RLCL

dst,n

RLDB

link,dst

dst rotate left n bits

= 1 or 2)

Rotate Left through Carry
dst,C - dst,C rotate left n bits
(n
1 or 2)

=

RR
RRB
RRL

dst,n

RRC
RRCB
RRCL

dst,n

RRDB

link,dst

SDA
SDAB
SDAL

dst: R
n: 1M

dst (n

link: R
dst: R

dst: R
n: 1M

dst: R
n: 1M

Rotate Left Digit
dst,link (0:3) - dst,link (0:3)
rotate left 1 digit

Rotate Right
dst (n

dst rotate right n bits

= 1 or 2)

Rotate Right through Carry
dst,C - dst,C rotate right n bits
(n
1 or 2)

=

dst,src

link: R
dst: R

dst: R
src: R

Rotate Right Digit
dst,link (0:3) - dst,link (0:3)
rotate right 1 digit

Shift Dynamic Arithmetic
dst -

dst arithmetic shift src bits

495
~_~

_ _ _ _ _" _ _

~~

_ _ _ _ _ _ ~~~ _ _ _ _ _ _ _ _r

Rotate and Shift (Continued)
Mnemonic

Operands

Addressing Modes

Operation

SDL
SDLB
SDLL

dst,src

dst: R
src: R

Shift Dynamic Logical

SLA
SLAB
SLAL

dst,n

dst: R
n: 1M

Shift Left Arithmetic

SLL
SLLB
SLLL

dst,n

dst: R
n: 1M

Shift Left Logical

SRA
SRAB
SRAL

dst,n

dst: R
n: 1M

Shift Right Arithmetic

SRL
SRLB
SRLL

dst,n

dst: R
n: 1M

Shift Right Logical

dst -

dst -

dst logical shift src bits

dst arithmetic shift left n bits

dst - dst logical shift left n bits

dst -

dst -

dst arithmetic shift right n bits

dst logical shift right n bits

Block Transfer and String Manipulation

496

Mnemonic

Operands

Addressing Modes

CPO
CPOB
CPOL

dst,src,
cnt,cc

dst: R
src: IR
cnt: R

CPOR
CPORB
CPORL

dst,src,
cnt,cc

dst: R
src: IR
cnt: R

CPI
CPIB
CPIL

dst,src,
cnt,cc

dst: R
src: IR
cnt: R

Operation
Compare and Decrement

dst - src
Autodecrement src address
cnt - cnt - 1
Compare, Decrement, and Repeat

Repeat
dst- src
Autodecrement src address
cnt - cnt - 1
Until cc is true or cnt=O
Compare and Increment

dst - src
Autoincrement src address
cnt - cnt - 1

Block Transfer and String Manipulation (Continued)
Mnemonic

Operands

Addressing Modes

Operation

CPIR
CPIRB
CPIRL

dst,sre,
ent,ee

ds!: R
sre: IR
en!: R

Compare, Increment, and Repeat

CPSD
CPSDB
CPSDL

dst,sre,
ent,ee

ds!: IR
sre: IR
en!: R

Compare String and Decrement

CPSDR
CPSDRB
CPSDRL

dst,sre,
ent,ee

ds!: IR
sre: IR
en!: R

CPSI
CPSIB
CPSIL

dst,sre,
ent,ee

ds!: IR
sre: SR
en!: R

CPSIR
CPSIRS
CPSIRL

dst,sre,
ent,ee

ds!: IR
sre: IR
en!: R

LDD
LDDB
LDDL

dst,sre,ent

ds!: IR
sre: IR
en!: R

LDDR
LDDRB
LDDRL

dst,sre,ent

LDI
LDIB
LOlL

dst,sre,ent

ds!: IR
sre: IR
en!: R

ds!: IR
sre: IR
en!: R

Repeat
dst - sre
Autoinerement sre address
ent - ent - 1
Unit ee is true or ent = 0

dst - sre
Autodeerement dst and sre addresses
ent - ent - 1

J

Compare String, Decrement, Repeat
Repeat
dst - sre
Autodeerement dst and sre addresses
ent - ent - 1
Until ee is true or ent = 0

I
I

Compare String and Increment
dst - sre
Autoinerement dst and sre addresses
ent - ent - 1

Compare String, Increment, Repeat
Repeat
dst - sre
Autoinerement dst and sre addresses
ent - ent - 1
Until ee is true or ent = 0

Load and Decrement
dst - sre
Autodeerement dst and sre addresses
ent - ent - 1

Load, Decrement, and Repeat
Repeat
dst ~'" src
Autodeerement dst and sre addresses
ent - ent - 1
Unitl ent=O

Load and Increment
dst - sre
Autoinerement dst and sre addresses
ent - ent - 1

497

Block Transfer and String Manipulation (Continued)
Mnemonic

Operands

Addressing Modes

Operation

LDIR
LDIRB
LDIRL

dst,sre,ent

dst: IR
sre: IR
ent: R

Load, Increment, and Repeat

TRDB

dst,sre,ent

TRDRB

TRIB

TRIRB

TRTDB

TRTDRB

TRTIB

498

dst: IR
sre: IR
ent: R

Repeat
dst - sre
Autoinerement dst and sre addresses
ent - ent - 1
Until ent=O

Translate and Decrement
dst - sre [dst]
Autodeerement dst address
ent - ent - 1

dst: IR
sre: IR
ent: R

Translate, Decrement, and Repeat

dst: IR
sre: IR
ent: R

Translate and Increment

dst: IR
sre: IR
ent: R

Translate, Increment, and Repeat

sre1,sre2,
ent

sre1: IR
sre2: IR
ent: R

Translate, Test, and Decrement

sre1,sre2,
ent

sre1: IR
sre2: IR
ent: R

Translate, Test, Decrement, Repeat

sre1,sre2,
ent

sre1: IR
sre2: IR
ent: R

Translate, Test, and Increment

dst,sre,ent

dst,sre,ent

dst,sre,ent

Repeat
dst - sre [dst]
Autodeerement dst address
ent - ent - 1
Until ent = 0

dst - sre [dst]
Autoinerement dst address
ent - ent - 1

Repeat
dst - sre [dst]
Autoinerement dst address
ent - ent - 1
Until ent=O

RH1 - sre2 [sre1]
Autodeerement sre1 address
ent - ent - 1

Repeat
RH1 - sre2 [sre1]
Autodeerement sre1 address
ent - ent - 1
Until RH1 *0 or ent=O

RH1 - sre2 [sre1]
Autoinerement sre1 address
ent - ent - 1

Block Transfer and String Manipulation (Continued)
Mnemonic

Operands

Addressing Modes

Operation

TRTIRB

src1,src2,
cnt

src1: IR
src2: IR
cnt: R

Translate, Test, Increment, Repeat

Mnemonic

Operands

Addressing Modes

Operation

IN*
INB*
INL*

dst,src

dst: R
src: IR,DA

Input

IND*
INDB*
INDL*

dst,src,cnt

INDR*
INDRB*
INDRL*

dst,src,cnt

INI*
INIB*
INIL*

dst,src,cnt

INIR*
INIRB*
INIRL*

dst,src,cnt

OTDR*
OTDRB*
OTDRL*

dst,src,cnt

OTIR*
OTIRB*
OTIRL*

dst,src,cnt

Repeat
RH1 - src2 [src1]
Autoincrement src1 address
cnt - cnt - 1
Until RH1 *0 or cnt=O

Input/Output

dst: IR
src: IR
cnt: R

dst: IR
src: IR
cnt: R

dst: IR
src: IR
cnt: R

dst: IR
src: IR
cnt: R

dst: IR
src: IR
cnt: R

dst: IR
src: IR
cnt: R

dst -

I9

src

Input and Decrement
dst - src
Autodecrement dst address
cnt - cnt - 1

Input, Decrement, and Repeat
Repeat
dst - src
Autodecrement dst address
cnt - cnt - 1
Until cnt=O

Input and Increment
dst - src
Autoincrement dst address
cnt - cnt - 1

Input, Increment, and Repeat
Repeat
dst - src
Autoincrement dst address
cnt - cnt - 1
Until cnt=O

Output, Decrement, and Repeat
Repeat
dst - src
Autodecrement src address
cnt - cnt - 1
Until cnt=O

Output, Increment, and Repeat
Repeat
dst - src
Autoincrement src address
cnt - cnt - 1
Until cnt=O

·Prlvlleged Instruction

499

Input/Output (Continued)
Mnemonic

Operands

Addressing Modes

Operation

OUT*
OUTB*
OUTL*

dst,sre

dst: IR,DA
sre: R

Output

OUTD*
OUTDB*
OUTDL*

dst,sre,ent

OUTI*
OUTIB*
OUTIL*

dst,sre,ent

dst: IR
sre: IR
ent: R

dst: IR
sre: IR
ent: R

dst - sre

Output and Decrement
dst - sre
Autodeerement sre address
ent - ent - 1

Output and Increment
dst - sre
Autoinerement sre address
ent - ent - 1

CPU Control
Mnemonic

Operands

Addressing Modes

Operation

COMFLG

flags

flags: 1M

Complement Flag

DI*

ints

ints: 1M

Disable Interrupt

EI*

Ints

Ints: 1M

Enable Interrupt

HALT*

Halt

IRET*

Interrupt Return
PS - @SP
Autoinerement SP

LDCTL*

LDCTLB

LDCTLL*

LDND*
LDNDB*
LDNDL*

• Privileged Instruction

500

dst,sre

dst,sre

dst,sre

dst,sre

dst: CTLR
sre: R
or
dst: R
sre: CTLR
dst: FLGR
sre: R
or
dst: R
sre: FLGR
dst: CTLRL
sre: R
or
dst: R
sre: CTLRL
dst: R
sre: IR,EAM
or
dst: IR,EAM
sre: R

Load Control Register
dst - sre

Load Flag Byte Register
dst - sre

Load Control Register Long
dst - sre

Load Normal Data Address Space
dst - sre

CPU Control (Continued)
Mnemonic

Operands

Addressing Modes

Operation

LONI*
LONIB*
LONIL*

dst,src

dst: R
src: IR,EAM

Load Normal Instruction Address
Space

cr
dst: IR,EAM
src: R

ast - src

LOPS*

src

src: IR,EAM

Load Program Status
PS - src

LOPNO*
LOPNI*
LOPSO*
LOPSI*

dst,src

dst: R
src: IR,EAM

Load Physical Address
dst - PhysicaL_Address (src)

NOP

No Operation

PCACHE*

Purge Cache

PTLB*

Purge TLB

PTLBENO*
PTLBENI
PTLBESO*
PTLBESI*

src

src: IR,EAM

PTLBN*

II

Purge TLB Entry

Purge TLB Normal

RESFLO

flag

flag: 1M

Reset Flag

SETFLO

flag

flag: 1M

Set Flag

Mnemonic

Operands

Addressing Modes

Operation

EXTR

dst,src,
pcs,siz

dst: R
src: R,IR,EAM
pes: IM,R
slz: IM,R

dst - src (pcs,slz)

dst,src,
pcs,siz

dst: R
src: R,IR,EAM
pes: IM,R
siz: IM,R

dst - src (pcs,slz)

dst,src,
pcs,slz

dst: R,IR,EAM
src: R
pes: IM,R
slz: IM,R

dst (pcs,siz) ... src

Bit Field

EXTRU

INSRT

Extract Field

Extract Unsigned Field

Insert Field

• Privileged Instruction.

501

EXTENDED INSTRUCTIONS
The Z80,000 CPU supports extended instructions
through the Zilog Extended Processing Architecture
(EPA). The EPA facility allows the operations defined in
the Z80,000 architecture to be extended by software or
hardware. In particular, floating-point operations are
supported by the Z8070 Arithmetic Processing Unit
(APU) or by a software package that emulates the APU.
Up to four Extended Processing Units (EPUs) can be included in a Z80,000 CPU system. The CPU and EPU
cooperate in execution of EPA instructions. When the
CPU encounters an EPA instruction, the instruction is
transmitted across the external bus to the appropriate
EPU. The CPU then performs transactions on the external bus to transfer data between the EPU and memory or
the EPU and CPU. Transfers between the EPU and CPU
can involve the CPU general-purpose registers or FCW
flag byte. EPU internal operations do not require any
data transfers. After the data transfers for the EPU instruction are completed, the CPU can continue processing while the EPU performs the operation. While the EPU
is processing an instruction, it can drive the EPUBSY
signal to stop the CPU.

The data processing operations performed by the EPU
are transparent to the CPU. The EPU can execute
floating point operations, decimal arithmetic, specialized
operating system functions, signal processing operations, or any other that the system designer chooses. For
this reason, no mnemonic is listed for the extended instructions, as the mnemonic will depend on the type of
EPU. EPUs designed to speed execution of special purpose operations can provide significant performance improvements. The operation of the EPU can be overlapped with operation of the CPU and other EPUs.
The EPA bit in the Flag and Control Word register indicates whether an EPU is present. If no EPU is present,
the CPU traps EPA instructions for software simulation.
Thus, the EPA facility can be used even with no external
support circuitry. This allows software compatibility between systems, whether or not an EPU is present. The
system designer can choose to include an EPU in highperformance systems but not in low-cost systems, and
software can be developed using the EPA instructions
before an EPU is available.

Extended Instructions
Operation

Addressing Modes

Load EPU from memory
dst - src
(n bytes or words)

dst, src, n

dst: EPU
src: IM,IR,EAM
n: 1M

Load memory from EPU
dst - src
(n bytes or words)

dst, src, n

dst: IR,EAM
src: EPU
n: 1M

Load EPU from CPU
dst - src
(n words or longwords)

dst, src, n

dst: EPU
src: R
n: 1M

Load CPU from EPU
dst - src
(n words or longwords)

dst, src, n

dst: R
src: EPU
n: 1M

Load EPU from Flags
dst - src

dst, src

dst: EPU
src: Flags

Load Flags from EPU
dst - src

dst, src

dst: Flags
src: EPU

EPU Internal Operation

502

Operands

CACHE
The CPU Implements a cache mechanism to keep on-chip
copies of the most recently referenced memory locations
(Figure 12). The CPU examines the cache on memory
fetches to determine if the addressed data are located in the
cache. If the information is in the cache (a hit), then the CPU
fetches from the cache, and no transaction is necessary on
the external interface. If the information is not in the cache (a
miss), then the CPU performs a memory read transaction to
fetch the missing information.
The cache stores data in blocks of 16 bytes. Each data word
In the cache has an associated validity bit to indicate
whether or not the word is a valid copy of the corresponding
main memory location. The cache contains 16 blocks, providing 256 bytes of storage.
The cache is fully associative, so that a block currently
needed and missing in the cache can replace any block in
the cache. Moreover, when a block miss occurs, the least
,.----'"1
ADDRESS TAG
ASSDCIATIVE
MEMORY
(16 x 28)

MATCH
16 LINES

,.---T"""-......
CA,;~~J1R~TA VA~:~~TY 16
(16x 128)

TAG
HIT

(16x 8)

LRU
STACK
(16x4)

32

28
32
PHYSICAL
ADDRESS

DATA

WORD
HIT

recently used (LRU) block in the cache is replaced. When a
cache miss occurs on an instruction fetch, the CPU fetches
the missing instruction from memory and prefetches the following words in the block using a burst transaction. When a
cache miss occurs on an operand fetch, the CPU fetches
the missing data from memory. (The CPU uses burst transactions only for fetching operands when more than one data
transfer is necessary: longword operands on a 16-bit bus,
unaligned operands, string instructions, Load Multiple instructions, and loading Program Status.)
On store references, the data IS written to memory (store
through), and if the reference hits in the cache, the data is
also written to the cache. If the store reference misses in the
cache, the cache is unaffected.
Software has some control over the cache. The cache can
be selectively enabled for instruction and data references by
bits CI and CD in the SCCL control register. The memory
management mechanism allows cacheing to be inhibited
for individual pages. The Pcache instruction can be used to
invalidate all information in the cache.
The cache has an option, controlled by bit CR in SCCL, to
inhibit block replacement on a miss. This option can be
used to lock fixed locations into the cache for fast, onchip
access. To do this, the cache is first enabled for block replacement of data references only. Selected blocks are read
into the cache. The block replacement algorithm is then disabled, while the cache is enabled for instruction and data
references.

Figure 12. Cache Organization

PIN DESCRIPTIONS
The CPU has 59 signal lines. Pin functions are shown in
Figure 13.

ADo-AD31. Address/Data (Bidirectional, active High,
3-state). These 32 lines are time-multiplexed to transfer
address and data. At the beginning of each transaction
the lines are driven with the 32-bit address. After the address has been driven, the lines are used to transfer one
or more bytes, words, or longwords of data.

AS. Address Strobe (Output, active Low, 3-state). The rising edge of AS indicates the beginning of a transaction
and shows that the address, STo-ST3, R/W, BUW, BW/L,
N/S, and BRST are valid.

BUSACK. Bus Acknowledge (Output, active Low). A Low
on this line indicates that the CPU has relinquished control of the local bus in response to a bus request.

iiiS'f. Burst (Output, active Low, 3-state). A Low on this
line indicates that the CPU is performing a burst transfer;
i.e, multiple Data Strobes following a single Address
Strobe.

iRS'TA. Burst Acknowledge (Input, active Low). A Low
on this line indicates that the responding device can support burst transfers.

BUSREQ. Bus Request (Input, active Low). A l,.ow on this
line indicates that a bus requestor has obtained or is trying to obtain control of the local bus.

2071.010

503

BUW; BW/L. Byte, Longword/Word; Byte, Word/
Longword (Output, 3-state). These two lines specify the
data transfer size.

NMI. Non-Maskable Interrupt (Input, Edge activated). A
High-to-Low transition on this line requests a nonmaskable
interrupt.

iiiVi. Non-Vectored Interrupt (Input, active Low). A Low on
this line requests a non-vectored interrupt.

BuW

BW/L

Size

High
Low
High
Low

High
High
Low
Low

Byte
Word
Longword
Reserved

N/S. Normal/System Mode (Output, Low = System Mode,
3-state). This line indicates whether the CPU is in normal or
system mode.

CE. Output Enable (Output,

elK. Clock (Input). This is the clock used to generate all
CPU timing.

Os. Data Strobe (Output, active Low, 3-state). DS is used for
timing data transfers.

EPUABORT. EPU Abort (Output. active Low). A Low on this
line indicates that the CPU is aborting execution of an EPA
instruction, typically because an Address Translation trap
has occurred.

EPU"BSY. EPU Busy (Input, active Low). A Low on this line
indicates that an EPU is busy. This line is used to synchronize the operation of the CPU with an EPU during execution
of an EPA instruction.

active Low, 3-state). A Low on
this line can be used to enable buffers on the AD lines to
drive away from the CPU.

R/W. ReadlWrite (Output, Low = Write, 3-state). This signal
indicates the direction of data transfer.

FiES'ET. Reset (Input, active Low). A Low on this line resets
the CPU.

R5Po·R5P1. Response (Input). These lines encode the response to transactions initiated by the CPU. Note that RSPo
and RSP1 can be connected together for Z-BUS WAIT
timing.

GREQ. Global Request (Output, active Low, 3-state). A Low
on this line indicates the CPU has obtained or is trying to obtain control of a global bus.

GAcK. Global Acknowledge (Input, active Low). A Low on
this line indicates the CPU has been granted control of a
global bus.

RESET

-====::
I-

INTERRUPT {
REQUESTS

EXTENDED
PROCESSOR
CONTROL
LOCAL BUS
CONTROL

GLOBAL BUS
CONTROL

I

RSP1

Response

High
Low
High
Low

High
High
Low
Low

Ready
Bus Error
Bus Retry
Wait

5T0·5T3. Status (Output.· active High, 3-state). These lines
specify the kind of transaction occurring on the bus. (See
Table 4.)

iE. Input Enable (Output, active Low, 3-state). A Low on this
line can be used to enable buffers on the AD lines to drive
toward the CPU.

RSPo

Vi. Vectored Interrupt (Input, active Low). A Low on this line
requests a vectored interrupt.

REm

AD

NMI

AS

iii

os

jijijj

R/W

EPUBSV

BUS STATUS
AND TIMING

BLIW

ZBO,OOO
CPU

BW/L
STATUS

EPUABDRT

N/S
BUSREQ

RESPONSE

4-

BUSACK

-

ADDRESS/DATA
BUS

4-

OE
iE

GREQ
GACK

BRST
BRSTA _ _

I
I

BUFFER
CONTROL

BURST TRANSFER
CONTROL

CLK

+5 V

GND

t

CLOCK

Figure 13. Pin Functions

504

2071'()11

MULTIPROCESSOR CONFIGURATIONS
The CPU provides support for interconnection in four types
of multiprocessor configurations (Figure 14): coprocessor,
slave processor, tightly-coupled multiple CPUs, and looselycoupled multiple CPUs.
Coprocessors, such as the Z8070 Arithmetic Processing
Unit, work synchronously with the CPU to execute a single
instruction stream using the Extended Processing Architecture facility. The EPUBSY and EPUABORT signals are dedicated for connection with coprocessors.
Slave processors, such as the Z8016 DMA Transfer Controller, perform dedicated functions asynchronously to the
CPU. The CPU and slave processor share a local bus, of
which the CPU is the default master, using the CPU's
BUSREO and BUSACK lines.

IAI COPROCESSOR

181 SLAVE PROCESSOR

Tightly-coupled, multiple CPUs execute independent instruction streams and generally communicate through
~hared memory located on a common (global) bus using
the CPU's GREQ and GACK lines. Each CPU is default master of its local bus, but the global bus master is chosen by an
external arbiter. The CPU also provides status information
about interlocked memory references (for Test and Set, Increment Interlocked, and Decrement Interlocked instructions), which can be used with multiported memories.
Loosely-coupled, multiple CPUs generally communicate
through a multiple-ported peripheral, such as the Z8038
FlO. The Z80,000 CPU's 1/0 and interrupt facilities can support loosely-coupled multiprocessing.

ICI TIGHTLY·COUPLED MULTIPLE CPU

ID) LOOSELY·COUPLED
MULTIPLE CPU

Figure 14. Multiprocessor Configurations

HARDWARE INTERFACE CONTROL
REGISTER
The Hardware I nterface Control register (HICR) specifies
certain characteristics of the hardware configuration
surrounding the CPU, including bus speed, memory data
path width, and number of automatic wait states. The
physical memory address space is divided into two sections, Mo and Ml, selected by bit 30 of the address. A
typical system would locate slow, 16-bit wide bootstrap
ROM in Mo and faster 32-bit wide dynamic RAM in Ml.
The phYSical 1/0 address space is similarly divided into
two sections, 1100 and 1/01, selected by bit 30 of the ad·
dress.
Fields in HICR specify the
characteristics (see Figure 3):
2071-012

following

interface

Bus speed (S)- The bus clock frequency is either 1/2 or
114 the clock frequency.
Memory data path (Mo.DP, Ml.DP)- The data path width
for Mo and Ml are each specified as 16 or 32 bits.
Automatic wait states (Mo. W, MI. W, liDo. W, 1101. W,
lACK. W1, lACK. W2)- The number of Wait states
automatically inserted by the CPU for references to Mo,
Ml, 1/00, 1/01, and interrupt acknowledge, are separately
specified.
Global bus protocol control (LAD, GE)-The CPU can access a global bus (a bus shared with other CPUs). On
references to the global bus, the CPU must use a re-

505

quest/acknowledge handshake with an external arbiter.
The GE field enables the use of the global bus; the LAD
field selects the portion of the address space used for
references to the global bus.

Minimum Address Strobe rate (MASR)- This optional
feature ensures that an Address Strobe will be
generated at least once every 16 bus clock cycles. This

is useful for refreshing pseudostatic RAMS.

EPU overlap (EPUO)- This bit, along with another bit in
an EPU control register, controls the degree of overlap
for CPU and EPU operations. The degree of overlap can
be limited to simplify debugging and recovery from exceptions, although to do so reduces overall execution
speed.

CPU TIMING
The CPU performs transactions on the external interface to
transfer data for fetching instructions, fetching and storing
operands, processing exceptions, and performing memory
management. In addition, the CPU performs internal operation and halt transactions, which do not transfer data. Each
transaction occurs during a sequence of bus clock cycles,
named T1, T2, etc.

input setup and hold times and output delays are specified
with respect to a rising edge of ClK. When CPU output transitions occur on different clock edges, the time between the
transitions is specified in terms of a constant delay and a variable number of ClK cycles. The number of ClK cycles depends on the bus timing scale factor, type of transaction,
and number of wait states.

The CPU has a single clock line, ClK, used to generate all
timing. Internally, the CPU derives another clock for bus timing by dividing ClK by 2 or 4. The scale factor for bus timing
(2 or 4) is selected at reset. In the AC timing characteristics
for the CPU (available in a separate data sheet from Zilog),

In the logical timing diagrams that follow, the signal transitions on the bus are shown in relation to the bus clock,
BClK. The beginning of a transaction, signified by a falling
edge of AS, always occurs on a rising edge of BClK. The
BClK signal is derived internally to the CPU as described

CLK

BCLK

AD

==x

)-------~

ADDRESS

\'----~;(AI BCLK = CLK

+2

CLK

BLCK

AD

--.J

=x:____

---J)- - - - - - - - - - - - - -<. . __

D_A_TA_I_N_--I>- -

A_D_DR_E_SS_ _ _

\~

-

-

-

-

-

______________----JI

(BI BCLK = CLK

+4

Figure 15. Memory Read Timing for Different Bus Scale Factors

506

2071.(113

above, but is not available on the pins. BClK can also be
derived externally to the CPU by dividing ClK by the selected bus timing scale factor. (The Reset section discusses
synchronization of the internal and external busciocks.) The
timing diagrams in Figure 15 show example memory read
transactions using the different scale factors.

In the description of bus transactions that follow, the term
"asserted" means an active signal and "negated" means an
inactive signal. A signal is either active when High or when
low, as specified in the pin functions.

BUS TRANSACTIONS
All bus transactions begin with Address Strobe (AS)
asserted and then negated. On the rising edge of AS the
lines for status (STo-ST3), ReadlWrite (R/W), data
transfer size (BW/L. BLlW), and Normal/System (N/S) are
valid. The status lines indicate the type of transaction being initiated (Table 4). The Rm line indicates the direction of data transfer. The data transfer size indicates
whether a byte, word, or longword of data is being
transferred. The N/S line indicates the CPU's operating
mode. The following sections describe timing for the different transactions.

data, and thus do not assert DS.) For write operations
(R/W
low) the CPU asserts DS when valid data is on
High) the CPU
the AD lines. For read operations (R/W
makes the AD lines 3-state before asserting DS, so the
addressed deVice can put Its data on the bus. The CPU
samples the datf' in the middle of a bus cycle, while
negating DS.

=

The AD lines can be used to transfer bytes, words, or
longwords. For read transactions, the three cases are
handled as follows:
•

Table 4_ Status Codes
ST3 -STo

Definition

0000
0001
0010
0011
0100
0101
0110
0111
1000
1 001
1010
101 1
1100
1101
11 10
1111

internal operation
CPU-EPU (data)
I/O
halt
CPU-EPU (instruction)
NMI acknowledge
NVI acknowledge
Vi acknowledge
cacheable CPU-memory (data)
non-cacheable CPU-memory (data)
cacheable EPU-memory
non-cacheable EPU-memory
cacheable CPU-memory (instruction)
non-cacheable CPU-memory (instruction)
reserved
interlocked CPU-memory (data)

On the rising edge of AS, the address on the AD lines is
also valid. Addresses are not required and therefore are
undefined for internal operation, halt, interrupt
acknowledge, and CPU-EPU data transactions.
The CPU uses Data Strobe (DS) to time the data transfer.
(internal operation and halt transactions do not transfer

=

Byte transfers use ADo-AD?; ADS-AD31 are ignored
(used only by 110).

• Word transfers use ADo-AD15; AD16-AD31 are ignored.
•

longword transfers use ADo-AD31.

For write transactions, the three cases are handled as
follows:
•

Byte transfers replicate the data on ADo-AD?, ADs-AD15,
AD16-AD23, and AD24-AD31'

• Word transfers replicate the data on AD o-AD 15 and
AD16-AD31'
• Longword transfers use ADo-AD31.
The Input Enable (IE) and Output Enable (OE) signals can
be used to enable buffers on the bidirectional AD lines. iE is
asserted when the buffers drive toward the CPU; OE is asserted when the buffers drive away from the CPU. Whenever
the direction for the AD lines changes, neither iE nor OE is
asserted for at least one ClK cycle.
To transfer more than one data item, the CPU can perform
burst transactions. The data items are transferred in the
same direction, and are equal in size. Data Strobe is used to
time each transfer. The CPU asserts Burst (BRST) to indicate
a burst transfer. The responding device asserts Burst Acknowledge (BRSTA) if it is capable of supporting burst transfers. If BRSTA is not asserted, the CPU transfers only a single
data item.

507

RESPONSE
Any time data is transferred, the responding device
returns a code on the Response lines (RSPo-RSP1) to indicate ready, wait, bus error, or bus retry. The response
is sampled at a time specific to each type of transaction,
generally before the AD lines are sampled or DS is
negated.
Ready indicates the completion of a successful transfer.
Wait indicates that the responding device needs more
time to complete the transaction. The CPU waits one bus
cycle before sampling the response again to accom·
modate slow memory or peripherals.
Bus error indicates that a fatal error has occurred during
the transaction; for example, bus timeout for a nonexistent device. Bus error is treated as an exception by the
CPU.

Bus retry illdicates that the transaction should be tried
again; for example, a transient parity error is detected.
The CPU tries the transaction again.
The CPU can insert wait states automatically under control of several fields in the Hardware Interface Control
Register. If an automatic wait state is programmed for a
bus cycle, the CPU ignores the response and wait is
assumed. Thus, wait states can be inserted automatically by the CPU or upon request of the responding
device.

It must be emphasized that the RSPo-RSP1 lines are syn·
chronous. Thus, they must meet the specified setup and
hold times for correct operation. A Simple system using
~Z-BUS WAIT can be implemented by connecting
WAIT to RSPo and RSP1.

CPU·MEMORY TRANSACTIONS
The CPU uses status 1000, 1001, 1100, 1101, or 1111 to
read from and write to memory. The transactions involve
a single data transfer or multiple, burst data transfers.
Single Memory Read
Figure 16 shows timing for a single memory read transaction with no wait states. AS is asserted during the first half of
T1. The rising edge of AS indicates that the address on AD
and control signals STo-ST3, RIW, BWtL. BLIW, and Nt§" are
valid. The control signals remain valid for the duration of the
transaction. BRST is negated during the transaction because only a single data item is being transferred. At the beginning OfT2 the CPU stops driving the address, asserts DS,
and prepares to receive data from memory. In the middle of
T2 R~-RSP1 are sampled read~e input data is latched,
and DS is negated. The signal OE is asserted during T1;
however, for this two-cycle read transaction, iE is not asserted. iE is unasserted because there is no bus clock transition between the negation of OE at the end of T1 and the
sampling of data in the middle of T2. The two-cycle read
transaction is a compatible extension of the Z-BUS threecycle read transaction. Two-cycle read transactions are intended for use with fast memories connected directly to the
CPU pins without buffers, such as an external cache.
For memory read transactions, the data transfer size is
equal to the data path width specified in HICR. The
memory should transfer the aligned longword addressed
by AD2-AD31 (ignoring ADo-AD1) for a 32-bit data path
or the aligned word addressed by AD1-AD31 (ignoring
ADo) for a 16-bit data path. The CPU selects the required
bytes from the transferred word or longword.
The timing for a single memory read transaction with one
wait state is shown in Figure 17. This is not a true wait
state because IE is asserted in the middle of T2 and continues until the middle of T3. For memory read transactions longer than two bus cycles, either because of
wait states or burst transfers, iE is asserted from the
middle of T2 until the end of data transfer. The signals OE

508

and

iE can be used to control

buffers on the AD lines.

The CPU can insert wait states in the middle of T2 if
RSPo-RSP1 are sampled wait or if automatic wait states
are programmed in the appropriate field of HICR. The
duration of a wait state is one BCLK cycle.

BeLK

AD

~

ADDRESS

>--®--c

v
I
ii

RlWJ
ITo-I!I
Nil
BW'L,BU~

=x

\0

)(

._ _ _ _ _ _ _ _ _ _......

\
BRITA
'RSPo-RSp,lnd data ,"mpled.

Figure 16. Single Memory Read Timing

2071-014

BCI.K

AD

==x:

I_WAIT STATE-i

ADDRESS

DS

DII

\

>----<

>--C

I

\
I

~

\

Ii

DATAIN

I

PJWJ
STO-S'!:I=:>(
BW/!:,B..,'!!
N/S

\:
)C

BRST

'"""
·ASPO-RSP1 and data sampled.

Figure 17. Single Memory Read Timing (1 Walt State)

2071-()15

509

Single Memory Write
A single memory write transaction (Figure 18) begins
with AS to indicate that address and control signals are
valid. At the beginning of h the CPU stops driving the
address and starts driving the data. In the middle of T2,
OS is asserted. The CPU negates DS in the middle of T3.
OE is asserted beginning at T1 and continues for the
duration of the transaction. The CPU samples
RSPo-RSP1 in the middle of T3.
For memory write transactions, the data transfer size is
less than or equal to the data path width specified in
HICR. Bytes and words can be written to a 16-bit
memory; bytes, words, and longwords can be written to
a 32-bit memory. The CPU writes bytes to any address,
but words and longwords are always written to an
aligned address (I.e., words are always written to an
even address and longwords are always written to an ad-

dress that is a multiple of four). When a program writes a
word or longword to an unaligned address, the CPU performs two or more write transactions to aligned addresses. For example, if the program writes a word to an
odd address, the CPU first writes the more significant
byte to the odd address, then it writes the less significant
byte to the successive even address.
Single memory read and write timing differ slightly from
loBUS specifications. The minimum read transaction is
two bus cycles, and the slave response is sampled at the
end of the data transfer. For the loBUS, the minimum
read transaction is three cycles, and the slave response
is sampled one cycle before the end of the data transfer.
For strict loBUS compatibility, it is possible to program
one automatic Wait state for memory read and to delay
the slave response with an external flipflop.

BeLK

AD

==x:

ADDRESS

>C

X\.____

D_AT_A_O_UT_ _ _ _

\0
'

f

_ _...J

Ii

STo-S!!

NIS
BW/L.BU~

==x:

x::

._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.

RiW~

C

*RSPO-RSP1 •• mpled.

Figure 18. Single Memory Write Timing

510

2071.(118

Burst Memory Transactions
Burst memory transactions use multiple Oata Strobes
following a single Address Strobe to transfer data at con·
secutive memory addresses. The signals BRST and
BRSTA control the burst transaction. The CPU uses
burst transactions to prefetch a cache block on an in·
struction fetch cache miss. The CPU also uses burst
transactions to fetch or store operands when more than
one transfer is necessary, as with unaligned operands,
string instructions, Load Multiple instructions, and
loading of program status.
If the memory does not support burst transfers, the burst
transfer protocol described below (Figure 19) allows BRSTA
to be tied High. The CPU then separates the burst transac·
tion into a sequence of single transfers.
At the beginning of a burst transaction, the CPU asserts
BRST along with other control signals. When the CPU
continues to assert BRST at the falling edge of OS, this
indicates to memory that the CPU can support another
data transfer following the one in process. When the
CPU negates BRST before the falling edge of OS, this in·
dicates to memory that the current transfer is the last in
the transaction.
When BRSTA is asserted at the time the RSPo-RSP1
lines are sampled ready, this indicates to the CPU that
memory can support another data transfer following the
one in process. When BRSTA is negated at the time the
RSPo-RSP1 lines are sampled ready, this indicates to the
CPU that the current data transfer is the last in the trans·
action.
The burst transaction can be terminated by either the
CPU or memory. If memory terminates the transfer by
negating BRSTA, the CPU responds by negating BRST
when OS is negated. (See the example for burst memory
read.) If the CPU terminates the transfer by negating
BRST before the falling edge of OS, memory responds by
negating BRSTA. (See the example for burst memory
write.) The CPU terminates the burst transaction when
all the required data items have been transferred or after
reaching the end of an aligned, 16-byte block.

Figure 19. CPU Burst Transfer Protocol

2071-017

511
-~------------

Burst Memory Read
Figure 20 shows timing for a burst memory read transaction with one wait state. In this example, three data
items are transferred, after which memory terminates
the burst. BRST is asserted at the beginning of T1; otherwise, the timing for the first transfer is identical to a
single memory read. In the middle of T3 the CPU
samples RSPo-RSP1 ready, latches the data, and
samples BRSTA active. During T4 the second data item
is transferred, accompanied by OS. The time for the
second and subsequent transfers can be extended with

wait states if RSPo-RSP1 are sampled wait; the CPU
does not insert automatic wait states after the first
transfer.
During Ts the third data item is transferred. At the same
time the RSPo-RSP1 lines are sampled ready, the data is
latched and BRSTA is sampled inactive. Memory terminates the bu rst transfer, and the CPU responds by
negating BRST.

3 DATA TRANSFERS, MEMORY TERMINATES BURST

BCLK

AD

==x:

ADDRESS

I..-_ _

__'X

DATA IN

X

DATA IN

)-

--C

Oi _ _ _
\~_-JI

\~-----------------'

R/WJ
STo-SIJ.=X

BW/L, BLly!
HIS

BRST

. - - - - - - -___________________________________________

~~_________________________________________________'

\~---------~--------~-----'
*RSPO-RSP1. BRSTA. and data sampled.

Figure 20. Burst Memory Read Timing (1 Wait State)

512

2071-018

Burst Memory Write
Figure 21 shows timing for a burst memory write transaction with no wait states. In this example, two data
items are transferred, and the CPU terminates the burst.
BRST Is asserted at the beginning of T,; otherwise, the
timing for the first transfer is identical to a single
memory write. In the middle of T3 the CPU samples
RSPo-RSP, ready and BRSTA active. At the beginning of
T4 the CPU negates BRST indicating that one more data

transfer will follow. During T4 the second data item is
transferred, accompanied by OS. The time for the second and subsequent transfers can be extended with
wait states if RSPo-RSP, are sampled wait; the CPU
does not insert automatic wait states after the first
transfer. Memory recognizes that the CPU has terminated the burst transfer and responds by negating
BRSTA before the end of T4.

2 DATA TRANSFERS, CPU TERMINATES BURST

BeLK

AD:::X

ADDRESS

X

DATA DUT

X

~

DATA OUT

J

I
S

\'----~
ii

>C

STO-S!!:::X
BW/L,
BU~
MIS
•_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _•

\~------_\~~/_--~I
*RSPo-RSP11 BRSTA .Impled.

Figure 21. Burst Memory Write Timing

Interlocked Memory lhmsactions
In tightly-coupled multiprocessor configurations, the CPU
must at certain times inhibit other bus masters from referring
to shared memory while the CPU performs two or more interlocked transactions. The CPU uses interlock protection
for data references associated with Test and Set, Decrement
Interlocked, and Increment Interlocked instructions. The
CPU also uses interlock protection for references to address
translation table entries when loading the Translation Lookaside Buffer. The CPU indicates interlocked protection for a

2071.019

sequence of memory references by using status 1111 for
any of the memory transactions previously described. While
the CPU indicates status 1111, the memory system must
prevent interlocked references to shared memory by other
processors. During a sequence of interlocked memory
transactions, the CPU does not acknowledge local bus requests nor does the CPU generate any bus transactions
with status other than 1111 .

513

INPUT/OUTPUT TRANSACTIONS
The CPU uses status 0010 to read from and write to 110
ports. 1/0 transactions are generated by 1/0 instructions
and, when address translation is enabled, by data
references to pages with bit 31 of the page table entry
set to 1.
The timing for 110 and memory transactions is very
similar. The major difference is that OS falls in the middle of T2 for 1/0 read timing, compared to the beginning
of T2 for memory read timing. This allows peripheral

devices more time for address decoding. Another difference is that t~e data transfer size (byte, word, or
longword) for 1/0 transactions is specified by the instruction, not by HICR. The final difference is that the CPU
does not support burst 110 transactions. Figure 22 shows
timing for an 110 read transaction. Single 1/0 write timing
is the same as that shown for a single memory write
(Figure 18).

BeLK

AD

J

ADDRESS

}- -

-

-

-

- - { DATA IN } - -

~

I
\_---'

ii

S~o-S!l

BW/L, BLlW
Nis

X

_ _- - I

' -_ _ _ _ _ _ _ _ _ _ _ _ __

*ASPo.. RSP1 and dl'l .empled.

Figure 22. 1/0 Read Timing

514

2071.()2()

EPU TRANSACTIONS
The CPU and EPU cooperate in the execution of EPA instructions (Figure 23). When the CPU encounters an EPA
instruction and the EPA bit in FCW is 1, the CPU broadcasts
the first two words of the instruction to the EPUs in the system using the CPU-EPU instruction transfer transaction. All
EPUs in the system recognize the transaction, but only one
of four possible EPUs is selected by bits 16 and 17 of the
EPU instruction. The CPU also transfers the PC value for the
instruction, which the selected EPU saves for use in exception handling. If data transfers are required to complete the
instruction, the CPU controls the data transfer transactions
while the EPU drives or receives the data.

the suspended EPA instruction on the system stack during
exception processing.

The EPUBSY signal, output from the EPU, is used to synchronize the CPU and EPU in executing EPA instructions.
(When multiple EPUs are present in a system, the EPUBSY
input to the CPU must be driven by an external AND gate
whose inputs are the EPUBSY signals from the EPUs). The
CPU must sample EPUBSY inactive before initiating an EPU
instruction transfer. If data transfers are required, the CPU
must sample EPUBSY inactive before initiating the first
transfer.

N

J

I
S

While the CPU samples EPUBSY active, no transactions are
initiated; however, the CPU may grant the local bus.
EPUBSY is also used to control the degree of overlap between CPU and EPU instruction execution. Ordinarily, the
CPU can continue processing other instructions after performing the data transfers associated with an EPA instruction and before the EPU has completed executing the
instruction. To simplify debugging and recovery from exceptions, overlap can be disabled under control of the EPUO bit
in HICR. When overlap is disabled (EPUO = 0), the CPU
samples EPUBSY in the middle of the bus cycle during
which the last data transfer for an EPA instruction occurs. If
EPUBSY is asserted, the CPU ceases processing instructions or interrupts until EPUBSY is sampled inactive in the
middle of a bus cycle. When overlap is enabled (EPUO =
1), the CPU does not sample EPUBSY after the last data
transfer, but only samples EPUBSY before initiating the next
EPU instruction transfer.
While processing an EPA instruction and after the instruction has been transferred to the selected EPU, the CPU may
detect an address translation exception. In such an event,
the CPU asserts EPUABORT, informing the selected EPU to
abort execution of the instruction; at all other times, the CPU
negates EPUABORT. The CPU then saves the address of

2071.021

Figure 23. EPA Instruction Processing

When CPU and EPU instruction processing overlap, the
CPU may complete all data transfers for an EPA instruction
(the queued instruction) before the EPU completes execution of a previous EPA instruction. If the EPU then detects an
exception during execution of the previous instruction, the
EPU does not execute the queued instruction. In such a
case, the address of the queued instruction is in an EPU
control register, and the CPU saves the address of a subsequent instruction on the system stack.
To simplify system hardware, the CPU and EPU AD lines
should be wired together with no buffers between them. If
the AD lines are separated by buffers, external circuitry must
generate IE and OE timing for CPU-EPU data and read and
EPU-memory write transactions.

515

CPU-EPU Instruction Transfer

Figure 24 shows timing for a CPU-EPU instruction transfer
transaction with status 01 00. The rising edge of AS indicates
that the AD lines and status are valid. During T1, the AD lines
are used to transfer the opcode, i.e., the first two words of the
EPA instruction. At the beginning of T2 the CPU stops driving the opcode, asserts DS, and starts driving PC on the AD
lines. In the middle of h the CPU samples RSPo-RSP1
ready and negates DS. The data transfer size for the transaction is longword.

tEPuiSY .amplad.

The duration of a CPU-EPU instruction or data transfer can
be extended with wait states if RSPo-RSP 1 are sampled wait.
The Z8070 APU, however, does not require wait states, nor
does it drive RSPo-RSP1. Systems using the Z8070 APU
must ensure that RSPo-RSP1 are both High, indicating
ready, during CPU-EPU instruction and data transactions.

__

*RSPo-RSP1 sampledi EPUBSY almpled If EPU Internal operation.

Figure 24. CPU-EPU Instruction 1i'ansfer Timing

516

2071-022

CPU-EPU Data li'ansfer li'ansactlons

Transactions to transfer data between the CPU and EPU use
status 0001. The EPA instruction opcode indicates the number of words to be transferred. One or more longwords of
data are transferred until all words have been transferred. If
the last transfer contains a single word. the data is on ADoAD1s. The CPU does not assert BRST and ignores RSPoRSP1 and BRSTA.
Figure 25 shows timing for a CPU-EPU data read transaction. This example has two data transfers; any number of

data transfers between one and eight is possible. The rising
edge of AS indicates that status and control signals are valid.
The CPU stops driving the AD lines at the end of T1. and the
EPU begins driving the AD lines in the middle of T2. At the
beginning ofT3• the CPU asserts DS. Inthe middle ofT3. the
CPU samples the data and negates DS. The second
longword of data is transferred during T4. After the last data
transfer, the CPU inserts an idle bus cycle (Ts in the example)
during which neither the CPU nor EPU drive the AD lines.

BCLK

JX

AD _ _ _ _ _ _ _

UNDEFINED

>- --{,-___

X

D_A_TA_I_N_ _-.J

DATA IN

r-----C

V

\:.

R/Vi

s.!o-s!l-------""\
BW/L. BL/W
N/S _ _ _ _ _ _ _J

'----________________________K

tEPUBSY lampled•

• ASPo-RSP, and data .ampled.

Figure 25. CPU-EPU Data Read Timing

2071-023

517

-----------

-~

- - - -- ---

Figure 26 shows timing for a CPU-EPU data write transaction. This example has three data transfers; any number of
data transfers between one and eight is possible. Timing for

the firstlransfer is identical to the CPU-EPU instruction transfer transaction. A second longword of data is transferred
during T3 , and the third longword is transferred during T4.

BCLK

-'X

AD _ _ _ _ _ _ _ _

UNDEFINED

X

DATA OUT

X

DATA OUT

X

DATA OUT

)(

Os _ - - J/

\
ii

---

r

/

\

A/W

r

STO - S T 3 - - - - - - - - - . ~----------------------~~

X

~~
BAST

\0

/

---'

BASTA

~

/
------I

tEPUBSY .ampled•

• RSPo-RSP1 sampled.

Figure 26. CPU-EPU Data Write Timing

518

2071-024

EPU-Memory Transactions
The CPU uses status 1010 or 1011 for the EPU to read from
and write to memory. The timing is identical for EPUmemory read and CPU-memory read. The EPU monitors
the CPU timing on the bus, and uses the two least-significant
address bits on the first transfer, the data transfer size, and
the length of the operand from the instruction to select the
bytes it needs from the AD lines.
The timing for an EPU-memory write transaction differs
slightly from a CPU-memory write transaction. Two extra bus
cycles are included to pass the AD lines from the CPU to
EPU after the address transfer and from EPU back to CPU
after the last data transfer. Figure 27 shows an example for a
single EPU-memory write transaction with no wait states.

The CPU stops driving the AD lines at the end of T1; the EPU
begins driving them in the middle OfT2. DS is asserted in the
middle of T3, one bus cycle later than for CPU-memory write
timing. The CPU negates DS in the middle of T4. The CPU
can insert wait states in the middle of T4. The EPU continues
to drive the AD lines until the end of T4. After the last data
transfer the CPU inserts an idle bus cycle (T5 in this example)
during which neither the CPU nor EPU drive the AD lines.
EPU-memory burst write transactions are similarly extended
by two bus cycles more than with CPU-memory burst write
timing. One cycle is inserted before the first data transfer,
and another after the last data transfer.

...J>- - - - -

'--_ _ _ _ _E_PU_DA_T_A_OU_T_ _ _ _ _

-c

\ . . . ._....,,1
[

r
""----__________________________________K

*EiiiiiSY sampled.

__

+ RSPo-RSP1Iampled; EPUBSY sampled It last transaction.

Figure 27. EPU-Memory Single Write Timing

2071.()25

519

INTERRUPT REQUEST AND
ACKNOWLEDGE
The CPU recognizes vectored, nonvectored, and nonmaskable interrupt requests. The decreasing order of priority for interrupts is nonmaskable, vectored, and nonvectored. NMI is edge sensitive; when NMI is asserted, an internallatch is loaded. Vi and NVI are level sensitive.
The CPU samples Vi, NVI, and the internal NMllatch on the
rising edge of ClK. The interrupt request signals can be
asynchronous to ClK; the CPU synchronizes them
internally.

is similar to a single 1/0 read. Wait states (either programmed
for automatic insertion or externally generated) can be inserted before OS falls in the middle of T2 and before OS rises
in the middle of T3. Inserting wait states before OS falls allows
for delay in the interrupt priority daisy chain. A word of data is
transferred on AOO-A01S' All of the interrupts save the transferred word on the system stack for processing the interrupt.
Vectored interrupts use the low-order byte of the word to select a unique PC value from the Program Status Area.

Figure 28 shows timing for an interrupt acknowledge transaction, indicated by status 0101, 0110, or 0111. The timing

--+l-_-Tz--.ro_-

ii, NYI

\ ' - -_ _ _ _ _ _ __

NMI

~'--'I
_____

INTERNAL
NMI LATCH

\'-----"""'-1.1AD

=x

r--<'I.____

UNDEFINED

..J

\'-----

I

STo-sta=x

BwiL",BU1!!!

NIS

.-----------------

.. RSPo-ASP1 sampled.

+ RSPo-ASP1 and data sampled.

Figure 28. Interrupt Response/Acknowledge Timing

520

2071~

INTERNAL OPERATION AND HALT
TRANSACTIONS
Figure 29 shows timing for internal operation (status
0000) and halt (status = 0011) transactions. Unlike other
bus transactions, data is not transferred in these operations.
Nevertheless, the transfer size for these transactions is
longword. The minimum duration for the transaction is two
bus cycles.

BeLK

AD

====><~

><:

______

U_N_DE_FI_N_ED_______

Ai

The CPU generates an internal operation transaction after a
sequence of interlocked memory transactions to free the
memory system lock when no other transactions need to be
performed. The CPU generates a halt transaction upon entering halt state-when the Halt instruction is executed, or
when memory indicates bus error during a fetch or store of
Program Status for exception processing. The CPU leaves
halt state when an interrupt or reset occurs. When the minimum Address Strobe rate option is enabled (controlled by
bit MASR in HICR), the CPU maintains a minimum rate for
Address Strobes by generating halt transactions in halt state
or internal operation transactions otherwise.

r
aTo-a!!

BW,r.B~!

--

J<

C
>C

.~-----

Figure 29_ Internal Operation and Halt Timing

BUS RETRY
During any transaction in which data is transferred, the responding device can indicate bus retry on RSPo-RSP1.
When bus retry is indicated, the CPU terminates the transaction in progress, negating OS and BRST. If bus retry is indicated during a burst transfer, the retry transaction begins

with the address for the data transfer where bus retry is
indicated.
The CPU does not acknowledge inerrupts or bus requests
between the retry response and the retry transaction.

BUS ERROR
During any transaction in which data is transferred, the responding device can indicate a bus error exception on
RSPo-RSP1' When bus error is indicated, the CPU terminates the transaction in progress, negating OS and BRST. A
bus error exception also causes termination of the Instruc-

2071.(127

tion in execution. In processing a bus error exception, the
CPU saves the Program Status, physical address for the
transaction, and a word identifying the status and control
signals used for the transaction.

521

BUS REQUEST AND ACKNOWLEDGE
The CPU supports two types of bus request/acknowledge
sequences, local and global. Other bus masters request the
local bus from the CPU using a handshake of BUSREQ and
BUSACK. The CPU requests a global bus from an external
arbiter using a handshake of GREQ and GACK.
To generate transactions on the local bus, a potential bus
master (such as a DMA controller) must gain control of the
bus by making a bus request (Figure 30). A local bus
request is initiated by asserting BUSREQ. Several bus
requestors may be wired to the BUSREQ signal; priorities
are resolved externally to the CPU, usually by a priority daisy
chain.
The CPU samples BUSREQ on the rising edge of ClK.
BUSREQ can be asynchronous to ClK; the CPU
synchronizes it internally. After BUSREQ is asserted, the
CPU completes any transaction or sequence of interlocked
transactions in progress, including possible retries. Next,
the CPU responds by asserting BDSACR and placing its
other output signals except EPUABORT in 3-state. The
EPUABORT signal remains valid while the CPU has granted
the local bus, and may be asserted if an EPA instruction is in
progress. later, when BUSREQ is negated, the CPU
negates BUSACK and begins driving all other output
signals.

BUSREQ

The CPU can initiate transactions with devices located on a
global bus shared with other CPUs. At any time, only one of
the CPUs can initiate transactions on the global bus. Control
of the global bus is arbitrated by external circuitry. Before
initiating transactions on the global bus, the CPU requests
control of the global bus from the arbiter using the protocol
described below.
The CPU uses two fields of HICR .to distinguish between
local and global bus transactions. The GE bit enables use of
the global bus. The 4-bit lAD field specifies one of sixteen
sections of the physical address space used for local
references.
Before every memory and 1/0 bus transaction (status codes
0010 and 1000 through 1111), the CPU compares the LAD
field with bits 26 to 29 of the physical address. If the
comparison is unequal and GE is 1, then the transaction is a
global bus reference; otherwise the transaction is a local bus
reference. In a tightly-coupled multiprocessor system
(Figure 14-c), each olthe local and global memory locations
and peripheral ports can have a unique system address.
Each CPU loads a distinct value into lAD, identifying its
local addresses; the CPUs refer to global addresses and
local addresses of other CPUs using the global bus request
protocol.

~'F-'_ _ _ _ _ _ _ _ _ _-I.:rlr----i/';F-'---

r-

/,F-C _ _""""'\\..._ _ _ _ _~"
;;~----.I:~

----I.~I_:_--'}- - - - - - - ,;. - - - - -.,~

AD _ _

AS, DS,
BRST, CiiiD

/'T--

------J/

-1.':

STo-STa _ _ _ _ _ _

BW~W~~~
DE, iE

>;

\. -

-

-

-

-

-

-:f.l- - - - - -

.,,...r-

}- ______ ,;. _____ .,~

):11_---

;; CJJ',rf

-

Figure 30. LDCBI Bus RequestlAcknDwledge Timing

522

2071.()28

Figure 31 shows timing for the global bus request/
acknowledge protocol. Before initiating a transaction on the
global bus, the CPU drives the address, STo-STs, BRST,
R/ViI, N/S, BUW, and BW/L valid at the beginning of a bus
cycle. Then, in the middle of the bus cycle, the CPU asserts
GREQ. When the global bus selected by the address IS

DS

available to the CPU, the arbiter asserts GACK. The CPU
samples GACK on the rising edge of ClK. GACK can be
asynchronous to ClK, the CPU synchronizes it internally.
The CPU performs one or more transactions on the global
bus, then negates GREQ. The arbiter responds by negating
GACK, and the CPU can then Initiate more transactions.

----------~,~'l~------------------~ff~'------~,~'l~----­

OE\

I~
~·------~'fJ'l~--------------------~/'~c------~)~

:'-1,

1..1.

1:=X

iJ

s;"

II

STO-S!J.)(
BwiL, BUW
,
~-----_r}J~------------------~/~'-------J/

.,1'
ii

BRST

\:~

''I

~----~~J~------------------~)~

iiiiTi ----------~h~t--------------------_Jff~'------~,~J~----Figure 31. Global Bus Request/Acknowledge Timing

2071.()28

523

-Figure 32 shows a state diagram for the local and global bus
request protocols. To prevent deadlock between CPUs
referencing each other's local memories, a CPU can be

preempted while it is waiting for GACK in State 2. If BUSREQ
is asserted before GACK, the CPU relinquishes the global
bus without performing any transactions.

STATE 0
GREQ = H
BUSACK = H
BUS = 2ST

(BiiSREQ = L).
(GAcK = H)
A

lj_GACK

STATE 1

=

H).

=L

ERROR
STATE 2

=
=
=

GREQ
3ST
BUSACK
L
BUS
3ST

BUSREQ

(BUSREQ = H).(GACK
(NEED_GBUS = H)
C

=H

=

0

E

(GAcK =

=
=

L
GREQ
BUSACK
H
BUS
2ST

L).(BUSREQ

STATE 3

=

(GACK = L).
(BUSREQ = L)

F

H)

STATE 4

=
=

L
GREQ
BUSACK
H
BUS = 2ST

G~GACK

'GREa -

H
(GACK

= L).

BUSACK

1(iiiiSREci' = L)
+(NEED_GBUS = L)l

BUS

l1li

I

= H

H

=H

2ST

GACK

=H

ERROR

NOTES: Interlaea olgnals ara High (H), Low (L), High or Low (2ST), or 3·stated (3ST).

NEED_GBUS 18 an active High algnallntern.' to the CPU.

Figure 32. State Diagram for CPU Bus Request Protocol
State Legend

Transition Legend

A

A local bus request occurs.

State 0

B

The global bus arbiter grants control of the
global bus when no global bus request is
pending. This Is an error. The CPU remains in
StateO.

The CPU controls the local bus and is neither
requesting nor controlling the global bus.
The CPU can perform transactions on the
local bus.

State 1

C

The CPU requests the global bus In response
to the internally generated Signal
NEED_GBUS.

The CPU has granted the local bus.
The CPU cannot perform transactions.

State 2

The CPU controls the local bus and Is requesting the global bus.
The CPU cannot perform transactions.

State 3

The CPU controls the local and global buses.
The CPU can perform transactions on the
global bus.

State 4

The CPU controls the local bus and Is relinquishing control of the global bus.
The CPU cannot perform transactions.

o

The local bus master relinquishes the bus.

E

The global bus arbiter grants the global bus to
the CPU while no local bus request is pending.

F

The global bus arbiter grants the global bus to
the CPU while no local bus request Is pending.
The CPU is preempted.

G

The global bus arbiter reclaims the global bus
before the CPU relinquishes the global bus.
This Is an error. The CPU's response to this
error Is undefined.

H

The CPU relinquishes control of the global bus
when It no longer needs the global bus or in
response to a local bus requesl.
The global bus arbiter reclaims the global bus.

524

2071.(J30

Reset
Figure 33 shows Reset timing. After RESET is asserted, the
CPU responds as follows.
• AD lines are turned to input direction
• AS, BRST, BUSACK, DS, EPUABORT, GREQ, iE, and OE
are negated
• STo-ST3 are driven to 1111

• BW/[ and BlIW are driven Low
• N/S and RIW are undefined
If RESET is asserted while the CPU is asserting BUSACK,
the CPU first negates B'DSACR, then the other CPU output
lines are removed from 3-state and driven as described
above. After RESET is asserted, external circuitry can detect
that the CPU has responded to the reset request by sensing
BW/[ and BUW Low. At power on, RrnET should be
asserted until after power has stabilized.
During reset, bits SX, NX, CI, and CD of the SCCl control
register are cleared, disabling the address translation and
cache mechanisms. Bit GE of HICR is also cleared,
disabling the global bus request protocol.

At the rising edge of RESET, the relationship between bus
timing, memory data path, and number of automatic wait
states is determined. If RSPo is High at the rising edge of
RESET, HICR is initialized with Mo.DP = 1, MoW = 7, and
S = 1. This corresponds to a default configuration of 16-bit
memory path, seven automatic wait states, and bus clock
scale factor 2. If RSPo is Low at the rising edge of RESET,
ADo-AD3 and AD11 are latched into the corresponding bits
of HICR, and AD15 must be High.
RESET need not be synchronous with ClK; however, the
CPU assumes that the last rising edge of ClK on which
RESET is asserted corresponds to a rising edge of BClK.
Thus, if RESET is synchronized with the rising edge of the
external bus clock, the internal and external bus clocks will
be in phase with respect to ClK. After RESET is negated,
the CPU reads FCW from memory address 2 and PC from
address 4 using status 1101. If BUSREQ is asserted before
RESET is negated, the CPU acknowledges the bus request
before fetching the Program Status.

525

I9

RESET

~

,
,

~~------------------------------~~----------J

,

-----------ih~'------------------------------~~------~
RSPo
-----------ih~'------------------------------~~------J

"
- -

-7~ADDRESS = 2

''''''---'r-

.'-'-\.'-----

:"

-----------{)~------------------------------7?------------------~,r_I

~~
J~
ALL HIGH

1:~lC

I
\

,.

rr

Il

---------7~--~-~-/~------------------*»---------------~n

--

iJ

r=

\:::

ff

Figure 33. Reset Timing

ORDERING INFORMATION
The Ordering Information section lists package temperature
ranges and product numbers. Refer to the Literature List for
additional documentation. Package drawings are in the
Package Information section.

526

00:2071·03

2071.()31

Z-BUS
Peripherals

Zilog

I·BUS Peripherals
latroductioa
March 1985

The Z-BUS is a high-speed parallel
shared bus that links the Z800,
Z8000, and Z80,000 microprocessor families and Extended Processing Units with the peripherals
needed to implement complete
systems. Through a common communications interface, Z-BUS peripherals and CPUs support the
following types of transactions:

• Data Transfer. 16 or 32 bits of
data can be moved between bus
controllers (such as a CPU) and
associated peripherals
• Interrupts. Interrupts can be
generated by peripherals and
serviced by CPUs over the bus.
• Resource Control. A daisy
chain priority mechanism supports distributed management of
shared resources which includes
peripheral devices and the bus
itself.

The heart of the Z-BUS is a set of
multiplexed address/data lines and
the signals that control these lines.
Multiplexing data and address onto
the same lines makes more efficient
use of pins and facilitates expansion
of the number of data and address
bits. Multiplexing also allows straightforward addressing of a peripheral's
internal registers, which greatly
simplifies 110 programming.
A daisy-chained priority mechanism resolves interrupt and resource
requests, thus allowing distributed
control of the bus and eliminating
the need for separate priority controllers. The resource-control daisy
chain also allows wide physical
separation of components.
Furthermore, Z-BUS is asynchronous in the sense that peripherals
need not be synchronized with the
CPU clock. All timing information is
provided by Z-BUS signals.

As a result of a common hardware
interface and protocol, users can be
assured that adequate system support for their Z800, Z8000, or
Z80,000 system design is readily
available with the following Z-BUS
peripherals and Extended Processing Units:
• Z8030 Serial Communications
Controller (Z-SCC)
• Z8036 Counter Input/Output
Circuit (Z-CIO)
• Z8038 FIFO Input/Output Interface Unit (Z-FIO)
• Z8068 Data Ciphering Processor
• Z8090/4 Universal Peripheral
Controller
• Z8070 Floating Point Unit (FPU
Extended Processor)

529

Z8070FPU
Floating Point Unit
Preliminary
Product
Specification

Zilog

April 1985

FEATURES
• Fast and complete implementation of proposed IEEE
Standard P754 Draft 10.0 for Binary Floating-Point
Arithmetic. With a 10 MHz clock, performs a
single-precision multiplication in under three microseconds.

• Speed versions offered from 10 MHz to 25 MHz.
• Provides for conversion of binary integer and Binary
Coded Decimal formats to and from floating-point
format.
• Can be interfaced through Zilog's Extended Processing
Architecture or a general-purpose interface.

• Supports Single, Double, and Double Extended
floating-point data types, 32- and 64-bit integers; BCD
strings.

• Frees CPU for performance of other tasks.

• Operations supported include add, subtract, multiply,
divide, square root, remainder, and compare.

GENERAL DESCRIPTION
The FPU supports several data formats, enabling it to
handle a wide range of business and scientific applications.
These include three binary floating-point formats and four
integer formats, including one for variable length Binary
Coded Decimal (BCD) strings. All of the FPU's internal
numeric manipulations use an 80-bit floating-point format;
however, transfers of data between the FPU's data registers
and CPU registers or memory can use any of the formats
desired, as specified in the floating-point instruction.

The Z8070 Floating-Point Processing Unit (FPU) is an
Extended Processing Unit (EPU) designed to perform
floating-point arithmetic functions while operating in parallel
with a CPU. By monitoring the same instruction stream as
the CPU, It is able to identify and execute those instructions
intended for it, thereby freeing the CPU to perform other
activities (Figure 1).
The FPU can use Zilog's Extended Processing Architecture
(EPA) for the Z800, Z8000, and Z80000, or using a
general-purpose interface, it can be integrated into systems
based on other popular microprocessors.
FPU

EXECUTION OF
FLOATING·POINT
INSTRUCTIONS

...

~

...

7

CPU
EXECUTION OF
CPU INSTRUCTIONS;
BUS CONTROL

MEMORY

A

..

SYSTEM BUS

'4

I"

CPU AND FPU
INSTRUCTIONS
AND DATA

Figure 1. The FPU Environment

2235-001

531

Floating-point arithmetic operations are performed
according to the requirements of the proposed IEEE
Standard P754 Draft 10.0. The 28070 supports:
• Single (32-bit), Double (64-bit), and Extended (80-bit)
Precision floating-point number formats.
• Addition, subtraction, multiplication, division, squareroot, remainder, square, reverse division, reverse
subtraction, absolute value, and compare operations.
• Conversions between different floating-point formats.
• Conversions between binary integers and floating-point
numbers.

• Non-numbers (NaNs) and infinity arithmetic.
• Floating-point exceptions and their handling.
Execution speeds are as follows:

Single

Operation
Add/subtract
Multiply
Divide

18
28

29

Number of Cycles
Double Double Extended
18
42
43

18
48

49

At 25 MHz, 1 cycle = 40ns; at 10M Hz, 1 cycle = 100 ns.

ARCHITECTURE
Overview
The 28070's contribution to a system is best understood by
examining its structure. Internally, the 28070 is organized as
two processors: an Interface Processor and a Data
Processor. The two processors have separate clocks,
freeing the Data Processor from interface speed constraints.
Figure 2 is a block diagram of the 28070 FPU.
The Interface Processor fetches and aligns instructions and
data, maintains the internal instruction queue, and executes
certain control and data movement instructions
independently of the Data Processor. By monitoring CPU
status and control signals, the Interface Processor knows
when an instruction fetch is to occur and will watch for an
Extended Instruction template. It will read and align the
instruction and data when the Extended Instruction
template has the correct EPU Identifier (ID) number.

The Data Processor, which operates independently of the
Interface Processor, contains eight 80-bit data registers
accessible to the user. It also contains the multiplier array,
ALU, accumulator, shifter, quotient predictor, and temporary
registers required for floating-point processing.
The parts of the Data Processor visible to the user are the
eight 80-bit data registers, specified in floating-point
instructions as source and/or destination registers.

Register Organization
The 28070 provides the following registers:
• Eight 80-bit data registers (FO-F7)
• Two 32-bit program counters (PC1 and PC2)
• Two 32-bit flags register (FFLAGS)

CPU ADDRESS/DATA LINES

• A 32-bit system configuration register (SC)

t
INTERP'ACE PROCESSOR

I

STATUS, CONTROL, AND
INTERRUPT REGISTERS

INSTRUCTION REGISTERS
DECODER AND TRANSLATOR

I

• A 32-bit user control register (USER)
• Two 80-bit operand registers (FOP1 and FOP2)
These are shown in Figures 3, 4, 5, 6, 7 and 8.

INTERFACE CONTROL

I
STATUS AND CONTROL REGISTERS

1----

-

1---------DATA PROCESSOR

I

DATA AND OPERAND
REGISTERS

I
SYSTEM

I

PC1

MULTIPLIER

IIQUOTIENTlr
PREDICTOR

USER

I

•
•

ALU

ACCUMULATOR

SHIFTER

I
I
I
I

PC2
F FLAGS
FOP1

I

FOP2

I

Figure 3. Status and Control Registers

Figure 2. Z8070 Block Dlagrem

532

2235·002. 003

79

64

78

63

31

PCl
31

PC2

Figure 5. Program Counter Registers

SIGN

EXPONENT

SIGNIFICAND

Figure 4. Data Registers
31

30

29

28

15

COMPARE AND REMAINDER FLAGS

14

13

12

11

10

9

8

7

6

5

4

3

2

v

V'

PREVIOUS OPERATION FLAGS

STICKY FLAGS

1

0

Figure 6. Flags Register

All of these are accessible to users except the System
Configuration register; it is reserved for privileged users.

BCD string, or when an attempt is made to convert a NaN to
an integer.

Data Registers. The Z8070 has a data register file of eight
80-bit data registers labeled FO to F7.

Previous Operation Flags (8-15)_ The same as the sticky
flags described above, but they reflect the exceptions of the
previous arithmetic operation.

Program Counter Registers (read only). PC1 holds the
address of the instruction being executed in the Data
Processor or the address of any control instruction being
executed. PC2 holds the address of any queued instruction.

Reserved (16-17). These bits are reserved.
Compare and Remainder Flags (18-23). Set with
comparisons as shown in Table 1.

Flags Register. The Flags register (Figure 6) contains
historical information on Z8070 operations.

Table 1. Comparison Results

Sticky Flags (0-7). Eight flags are set when the
corresponding arithmetic exception occurs, and remain set
until they are cleared by the programmer. These flags are:

Fe
FZ
FS
FV
FD

INV (Invalid Operation). Indicates an invalid operation or
result has occurred (e.g., 010).
FOV (Overflow). Indicates that the absolute value of a
floating-point number is too large to be accommodated by
the destination format.
UN (Underflow). Occurs when the absolute value of a
number is too small for the destination format, and further
denormalization would cause a loss of accuracy.

<

=

>

Unordered

0
0
0
0

0
0
0

1

0

0

1

1

0
0
0

0

0

FOP2E (24-25). Contains the two most significant bits of the
exponent of operand register FOP2.
FOP1 E (26-27). Contains the two most significant bits of the
exponent of operand register FOP1.

DZ (Divide by Zero). Indicates the division of a non-zero finite
number by zero.

R (28). Rounding bit; 1 if most recent result was rounded
up.

INX (Inexact Result). Indicates when the result is inexact due
to rounding or an untrapped overflow.

Invalid Op (29-31). Contains a code describing the reason
for an invalid operation result as follows:

DE (Denormalized number). Indicates that an operation was
performed on a denormalized number.
NAN (Signaling NaN). Occurs when a Signaling NaN is
encountered. (NaN stands for "Not-a-Number", and may
be used to force a trap or hold other information.)
IX (Integer Overflow). Occurs when the floating-point
number is too large in magnitude to convert to an integer or
2235·004,005,006

000
001
010
011
100
101
110
111

infinity minus infinity
zero multiplied by infinity
zero divided by zero, or infinity divided by infinity
all invalid remainders
unordered compare
square root of a negative number
non-decimal digit on BCD convert
conversion of NaN to decimal or integer

533

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

INTERRUPT VECTOR NUMBER
• read only

Figure 7. System Configuration Register

IR (24-25). Set to indicate the reason for an interrupt as
follows:

System Configuration Register. The System
Configuration register is a 32·bit control register (Figure 7).
In systems that distinguish between System and User
modes of operation, it is restricted to privileged users.

00 = Arithmetic
01 = Invalid opcode
10 = Invalid EPU id
11 = Privilege mode violation

Interrupt Vector (0·7). This field identifies the source and
cause of an interrupt.

10 (26-27). These (read only) bits hold the 10 of the Z8070
expressed in binary form. Instructions are executed only if
the 10 in the opcode matches these bits.

SV (9). Set to shift the interrupt vector left one bit, and set the
lSB to zero.
VIS (10). Set when the interrupt vector is to include status
information.

EPUIOS (28-31). This field contains four bits, one for each
possible EPU 10 An instruction specifying an 10 whose
corresponding bit is a 1 will cause an Invalid EPU 10
interrupt.

NV (11). Set when there IS no Interrupt vector (leaves lines
3·stated).
OLC (12). Set to disable interrupts from lower priority
devices on the interrupt daisy chain.

User Control Register. The User Control register (Figure
8) is a 32-bit register, accessible to all users. The user
controls rounding modes and enables/disables traps with
this register.

IUS (13). Set when the interrupt is under service.
IP (14). Set to indicate a pending interrupt.

RM (0-1). Sets the rounding modes as follows:

MIE (15). Set to enable interrupts.

00 = Round to Nearest
01 = Round toward Zero
10 = Round toward Positive Infinity
11 = Round toward Negative Infinity

INTACK (16-17). Set to indicate which type of interrupt
acknowledge to respond to as follows:

OX = Non-maskable
10 = Non-vectored
11 = Vectored

7fap Enables (8-15). The setting of these bits enables the
trap associated with each exception listed below.

OVRLP (18-19). Indicates the Overlap mode as follows:

INV (Invalid)
FOV (Overflow)
UN (Underflow)
OZ (Oivide-by-Zero)
INX (Inexact result)
DE (Oenormalized number)
NAN (Signaling NaN)
IX (Integer Overflow)

00 = No Overlap, Simple Overlap (Z80,000)
01 = Reserved
10 = Intermediate Overlap
11 = Maximum Overlap (Not available for Z8000)
AC (20). Set to synchronize processors if ClK.1 and ClK.D
are running at different speeds.
F (21). Set if an interrupt service routine will be unable to
successfully return to the interrupted program. Also set if
two or more floating-point instructions have been fetched
after the EPU requested an interrupt, but before the interrupt
acknowledge.

Undefined (16-31). These bits are undefined, and reserved
for future use.

Floating Operand Registers (read only). The Z8070
contains two 80-bit Floating Operand registers (Figure 9),
labeled FOP1 and FOP2, which contain the input operand
(FOP1) and the default result (FOP2) for use by trap
handlers.

RPC (22). Set if an interrupt service routine will need to alter
its return address to successfully continue the interrupted
program.
U (23). Set when the Z8070 is used.
31

16

'V'

UNDEFINED

.J

15

"

14

13

12

11

10

'V'
TRAP ENABLES

9

8

7

6

5

4

3

2

1

0

.I

Figure 8. User Control Register

534

223S'()()7. 008

79 78

64 63

I I
S

EXPONENT

L

I

SIGNIFICAND

15 LEAST SIGNIFICANT BITS OF
EXPONENT (2 MSB. IN FLAG REGISTER)
FOPI (INPUT OPERAND)

79 76

6463

I I
S

SIGNIFICAND

EXPONENT

L

15 LEAST SIGNIFICANT BITS OF
EXPONENT (2 MSB. IN FLAG REGISTER)

FOP2 (RESULT)

Figure 9. Floating Operand Registers

PROGRAMMING
Floating-point instructions are contained in the same
program as standard CPU instructions. To the programmer,
instruction execution appears linear, as if a single processor
is executing all the instructions. In many cases however,
CPU and Z8070 processing can occur in parallel, greatly
increasing system throughput.
Parallel processing depends upon the type of FPU
instruction being executed and the Overlap mode set in the
System Configuration register. Instruction overlap is a type of
system organization that allows the FPU to queue
instructions by distributing processing between two
processors.
interleaving CPU and FPU instructions allows processing to
be overlapped, thereby increasing total system processing
speed by distributing processing between two processors.
Details about the behavior of the Z8070 under each of the
overlap modes can vary according to the particular
interface. The basic idea is explained in Table 2.
Table 2. Overlap Modes

NO OVERLAP

Instruction 1 executing
CPU stopped
INTERMEDIATE INSTRUCTION OVERLAP

Instruction 1 executing
Instruction 2 queued

Generally, while in No Overlap mode the Z8070 attempts to
stop the CPU whenever the Z8070 is doing any processing.
This mode does not take advantage of the Z8070's overlap
capabilities, but can be useful for debugging purposes.
In Intermediate Overlap mode, the Z8070 allows the CPU to
continue with CPU processing while a floating point
operation is proceeding in the FPU, but attempts to stop the
CPU after a second floating point instruction is transferred.
In Maximum Overlap mode, the Z8070 allows the CPU to
continue processing after a second FPU instruction has
been transferred to the Z8070, and allows a subsequent
third FPU instruction to be fetched. Maximum Overlap
mode, not available for Z8000 interface, is used for
applications requiring maximum performance.
Floating point exceptions cause flushing of floating point
instructions queued behind the instruction responsible for
the exception. The use of Intermediate Overlap mode allows
software to recover cleanly from exceptions (such as divide
by zero, or overflow). When Maximum Overlap mode is in
effect, programs that encounter an enabled exception must
restart the program from a known point, such as rerunning
the exception-causing module, or simply exit the program.
Figure 10 illustrates instruction processing with No-Overlap
and with Maximum Overlap. In general, any time lost by
stopping the CPU is negligible, and the interaction of CPU
and FPU is transparent to the user. it is possible, however, to
arrange programs to take advantage of the parallel
processing capabilities inherent in the system.

MAXIMUM INSTRUCTION OVERLAP

Instruction 1 executing
Instruction 2 queued
Instruction 3 being fetched

2235-009

535

FPU

CPU

FPU

CPU

T,
FPU OPCODE 1
FETCH

•

FPUOPCODE1
FETCH
OPERAND
FETCH

OPERAND
FETCH
FPU OPCODE2
FETCH

FPUOPCODE1

EXECUTION

OPERAND
FETCH

•
•

CPU OPCODE 1
FETCH
OPERAND
FETCH
FPUOPCODE2

EXECUTION

CPUOPCODE1
EXECUTION

CPUOPCODE1
FETCH

•
FPUOPCODE1
EXECUTION

•
•

•
•

•

FPUOPCODE3
FETCH
OPERAND
FETCH

OPERAND
FETCH

•

FPUOPCODE4
FETCH
OPERAND
FETCH
CPU OPCOCE 2
FETCH

CPU OPCODE 1

EXECUTION

•
•

FPUOPCODE2
FETCH

OPERAND
FETCH
FPUOPCODE3
EXECUTION

OPERAND
FETCH

CPUOPCODE2
EXECUTION

CPUOPCODE2
FETCH
FPUOPCODE2
EXECUTION

CPUOPCODE3
FETCH
FPUOPCODE4
EXECUTION

CPU OPCODE 3
EXECUTION

CPU

•

•

STOPPED

•

Tn
FPUICPU PROCESSING IN MAXIMUM MODE

CPU
STOPPED

FPUICPU PROCESSING IN NO OVERLAP MODE

Figure 10. Instruction Processing
An interleaving of CPU and 28070 instructions enhances
the ability of a system to process in parallel. Without
interleaving, floating'point instructions might be received
faster than they can be processed, forcing the 28070 to halt
further CPU processing until the current extended
instruction is completed. Also, some instructions take a
relatively long time to process (e.g., FSQR or FREMSNF);
interleaving allows the CPU to process instructions while
these extended instructions are being processed by the
FPU.
Parallel processing is facilitated by interleaving instructions
asin
CLR

FO

FLDO
FMULO
INC
INC
FAOO
OJN2

F1, @R2
F1,@R4
R2, #8
R4,#8
FO,F1
R6,OOTLOOP

OOTLOOP:

536

In this dot product loop, the two CPU commands are placed
directly after the multiply command so the CPU can execute
them while the 28070 is busy with the (relatively slow)
multiply command.
Programming constructions like the following
FAOO
FLO

F1,@R2
@R4,F1

cause the 28070 to halt the CPU to ensure that valid results
are read from F1 during the subsequent load operation.

Data Types and Formats
This section describes the different data types and formats
that the FPU is able to manipulate. These data types include
binary floating-point and binary and decimal integers, and
can be represented in 32-,64-, and 80-bit formats.

Binary Floating-Point. All binary floating-point numbers
assume the following format:

I I
SIGN

EXPONENT

I

SIGNIFICAND

2235·010

where the Sign bit specifies a positive (cleared to 0) or
negative (set to 1) number. The negative or positive
floating-point number is equal to:

For the 80-bit Double Extended Precision Binary format, the
value is determined as follows:
•

Significand x 2(exponent-bias)
The significand portion contains the fraction and the integer
bit (in Single and Double Precision binary, the integer bit is
implicit). The significand then, is the integer bit followed by
the binary point and the fraction. The exponent locates the
actual binary point, and the sign bit specifies a positive or
negative number.
In the following description of the binary floating-point
formats, "s" is the sign, "e" is the exponent, "f" is the
fractional part of the significand, and "j" is the integer part
(possibly implicit) of the significand.

Ife = 32,767 and f;l-O, then v = NaN.

•

If e = 32,767 and f = 0, then v = (-1 )8(infinity).

•

IfO

OS
READ

~

"--

/

R/W
READ

AD

MEMORY ADDRESS

WRITE

W RITE

i

FPU DATA OUT

DS
WRITE

\

R/W
WRITE

I

I

I

_r

Figure 16. Z8070-Memory Transfers, Z8000 Interface

2235-016

547

.
CLOCK

T,

T,
II

I

-

TWA
..

III

II

WAI~

I

..

T3
II

..

1

~

DATA SAMPLED
FOR READ

i

WAIT CYCLES ADDED

SAMPLED

WAIT

STATUS
(B/W, ST ,·ST 31

AS

-

-

ex
r\
HIGH

MREQ

AD
INPUT

TO
CPU

ex

-

J

-

=x

I

(

}-------

DATA IN

> C

OS

R/iii

AD
OUTPUT

TO

-

INPUT

INPUT

FPU

-

~
CPU DATA OUT

OS
WRITE

r

--

R/W

OUTPUT

"
Figure 17. Z8070-CPU Data Transfers, Z8000 Interface

548

2235-017

zaoo INTERFACE
R/W. ReadlWrite (input, Low

= Write). Tells the Z8070
whether the CPU is performing a read or write.

The Z8100 is the Z-BUS external interface of the Z800
family; it interfaces to the Z8070 via the Z-BUS architecture.
The Z81 08 uses the Universal Interface.

STo·ST 3. Status (input, active High). These lines specify the
type of bus transaction as follows:

Like the other Z-BUS units, the Z8100 is designed to
interface with the Z8070 without using external logic. The
CPU is responsible for fetching instructions, performing
address calculations, and generating the timing signals for
bus transactions; however, the Z8070 does the actual data
manipulation.

AOo·A023' Address/Data (bidirectional, active High,
3-state). These multiplexed address and data lines are
supplied by the CPU.

The Z8100 architecture provides a group of unique
instruction opcodes for EPU instructions. All these fall into
one of four groups:

AS. Address Strobe (input, active Low). The rising edge of
AS indicates the beginning of a transaction and shows that
the address, status, and control signals are valid.

BLlW, BW/L. Byte, Longword/Word; Byte, Word/
Longword. These signals specify the data transfer size.
BW/[ is tied High to program the Z8070 for 8/16 bit date
transfers.
BW/[

Load EPU from memory
Load memory from EPU
Load accumulator from EPU
EPU internal operation
These fall into one of the following formats:

Size in Bits

1

ED opcode, 4-byte template
ED opcode, 2-byte displacement, 4-byte template
ED opcode, 2-byte address, 4-byte opcode

8 (Byte)
16 (Word)

o

Nonmaskable interrupt acknowledge
Nonvectored interrupt acknowledge
Vectored interrupt acknowledge
EPU to data memory transfer
EPU to stack memory transfer
Instruction fetch after first word
Instruction fetch, first word
CPU to EPU transfer

0101
0110
0111
1010
1011
1100
1101
1110

In addition to the pins described earlier for all interfaces, the
Z800 Interface (Figure 18) uses the following Z8070 pins:

BUW

Type of Transaction

STo-ST3

The 8100 uses the ED opcode portion as an instruction, to
tell it what type of EPU instruction follows. It handles the
displacement and template as data. The FPU uses the
template to determine what action it is to perform.

BUSACK. Bus Acknowledge (input, active Low). When
BUSACK goes Low, the EPU 3-states the AD lines until
BUSACK goes High again and an EPU-to-memory or CPU
transfer is required.
OS. Data Strobe (input, active Low). OS provides timing for
data transfers on the bus.

A
20-50MHz

=~
.:.-

XTAL,

).

ADo·A015

r

~

t..

XTALo
ADDRESS

A16- A23

fROM EXTE''''!Al
MEMORY LOGIC

--

ADo-A015

ADDRESS/DATA

AD16-AD23

r

ZB100
MPU

os

os

R/W

Riw
iNT

L

OPTo

aiiii

-

al/W

I

STo·ST3

-J

STo·ST3

4

ClK.1

ClK
GND

Reffi

*

=1

OPT, = 0

BuSACK
BSY

PAUSE

+5V

10,

ZB070
FPU

aW/L

aUSACK

OPT

100

As

As

i'NfA,B, OR C

SETTO +5V
FORZ·BUS

lEI
I~O

WAIT

~

.. SYSTEM ]
RESET

Figure 18. Z8100·Z8070 Interface

ClK.D

RESET

+5V

-J

GND

=l
=l

INTERRUPT
DAISY CHAIN
SETTOGND
OR +5VFOR
EPUID

J

~

--

SEPARATE OR
CPU CLOCK
SIGNAL

*
549

Bus Transactions

and timing signals from the CPU These tell it when to
participate in a data transaction.

As the Z81 00 fetches and executes instructions, the Z8070
monitors the instruction stream and the status bits (STo-ST3)'
When the Z81 00 fetches an extended instruction (assuming
the EPA enable bit is set), it sets its status lines to 1101 for the
first word of the four-byte instruction template and to 1100 for
the second.

For transactions between the Z8070 and memory, the
Z8100 3-states its address/data lines while DS is active so
the Z8070 can supply data over the bus (Figures 19 and 20).
Z8070 to CPU transactions are four processor cycles long
unless extended by WAIT (Figure 21).

Once the Z8070 sees the 1100 status code, it begins to
capture template information and to monitor the address

The BSY/PAUSE line halts all CPU activity except responses
to refresh requests, bus requests, and reset.

I~T1------..I"'---T2~I~T3~1

ADo-AD«

ADDRESS

R/W

STo·ST3
BlloY

STATUS VALID = 1010

Figure 19. Z8070 Memory Read, Z800 Interface

550

2235-019

I
ADO-AD15

RiW

- -(

a/w

ADDRESS

I
I
'\

'\
I

--X
- "'\
-

STo·STa

I

-

I

I
'\
I

EPU DATA VALID

ADDRESS

rL-J
STATUS VALID = 1010

-

/
I

I

I

\

I

I

I

Figure 20. l8070 Memory Write, l800 Interface

...--..,

3-1

, - - - ; * * I · o - - - T _ I -T

ADD-AD,.

DATA

UNDEFINED

STATUS

aiW.

RlW

=1

STATUS = 1110

Figure 21. l8070·CPU Data Thlnsfer, l800 Interface

2235-020, 021

551

EPU Templates
The four-byte template requires two word-fetch cycles if it is
on an even boundary and one byte-fetch followed by two
word-fetches if it is on an odd boundary. In the case of odd
boundaries, it only captures the upper byte from the bus
during the last word-fetch.
The template is always fetched from memory using the
CPU's external interface, regardless of the current state of
the on-chip cache. Even though the opcode and
addressing portion of the EPU instruction may be executed
from the 28216's on-chip cache, the template is always
fetched from memory.
The CPU activity following the extended instruction fetch
depends on the type of extended instruction. For an EPU
internal operation, no further bus transactions are required;
it fetches the next instruction. For an EPU to CPU transfer,

the next non-refresh transaction after the template fetch will
be the EPU to CPU transfer, a word transaction identified by
status code 1110. During this cycle, the CPU emits the
address of the previous transaction.
For transactions between the EPU and memory, the next
one to 16 transactions after the template fetch will be data
transfer cycles. The amount of data to transfer is encoded in
the instruction template, but the actual number of cycles
also depends on whether the block to be transferred starts
on an even or odd boundary.
The 28100/28070 interface handles all activity prior to, and
following, the extended instruction template fetch. 2i1og's
2800 Assembler supports the 28070 by replacing 28070
source mnemonics with the proper opcode and template
information.

Z80,OOO INTERFACE
In addition to the pins described earlier for all interfaces, the
280,000 Interface (Figure 22) uses the following 28070 pins:
ABORT. Abort (input, active Low). Aborts current
instruction.
ADo·AD31' Address/Data (bidirectional, active High,
3-state). These multiplexed address and data lines are
supplied by the CPU.
AS. Address Strobe (input, active Low). The rising edge of
AS indicates the beginning of a transaction and shows that
the address, status, and control signals are valid.

BUW, BW/L. Byte, Longword/Word; Byte, Word/Longword
(inputs). These signals specify the data transfer size as
follows:

RSPo

RSP1

Response

0
0
1
1

0
1
0
1

Wait
Bus Error
Retry
Ready

RIW. Read/Write (input, Low

High). Tells the 28070
whether the CPU is performing a read or write.

STo·ST3. Status (input, active High). These lines specify the
type of bus transaction as follows:

BLJiiii

BW/[

Size in Bits

STo-ST3

1

1
1

8 (Byte)
16 (Word)
32 (Longword)

0101
0110
0111
1010
1011
1100
1101
1110

o
1

o

BRST. Burst (input, active Low). BRST active indicates that
the CPU may generate burst transfers.
BRSTA. Burst .Acknowledge (input, active Low). A Low on
BRSTA indicates that the memory can support burst
transfers.
BUSACK. Bus Acknowledge (Input, active Low). When
BUSACK goes Low, the EPU 3-states the AD lines until
BUSACK goes High again and an EPU-to-memory or CPU
transfer is required.
DS. Data Strobe (input, active Low). DS provides timing for
data transfers on the bus.

552

RSPOO·RSP01' Response (bidirectional, active High).
These lines encode the response monitored by the EPU to
transactions initiated by the 280,000 CPU as follow:

Type of Transaction
Nonmaskable interrupt acknowledge
Nonvectored interrupt acknowledge
Vectored interrupt acknowledge
EPU to data memory transfer
EPU to stack memory transfer
Instruction fetch (after first word)
Instruction fetch, first word
CPU to EPU transfer

The 28070 and the 280,000 are designed to serve together
as coprocessors, so the interface between them is
straightforward. The address/data, bus control, and timing
pins are connected directly, enabling the iE and OE signals
from the 280,000 to control buffer circuits.
The 280,000 and 28070 use EPUABORT and BSY to
control the 28070. The 28070 asserts BSY to halt the
280,000, and the 280,000 asserts EPUABORT to
abort 28070 operation.

_I fr

SET TO
+5V
GNDOR l - 100
+SVFO
10,
EPUI

GNO

.r-

l

lEO

TNT

PERIPHERAL
DAISY
CHAIN

~

=0

OPTO

I

lEI

:'-

ADo-AD31

.,
~

5 To·5T3
OPT1 '" 1

.,
~

RSPO-RSP1

Z8070
FPU

.,

AS

OS
R/W

Bl/W
BW/L

SEPARII:FE
ORC
CLO
SIGN AL

:~-

N/S
CLK.D

BRST
BRSTA
BUSACK

--r--

RESET

BSV

RESET

ABORT

CLK.!

t--

1-

1

CLOCK

1
CLK

~

EPUABORT
EPUBSV

RESET

I--

I--

-

rrr-

lf0ffffl-

l-

I-

t-

BRSTA
BRST

-

N/S
BW/L
BL/W
R/W

OS
Z80,OOO
CPU

AS
~

RSPo·RSP1

I- ~

r- '----

r---

I-I-- I--I-- I--I-- I--I-- I--I-- ~

.,

MEMORY AND
PERIPHERALS

5To·ST3

~

ADo·AD31

.,

iE

I

OE

1

VI
BUSACK
+5V

GNO

BUSREQ

•

J

-J JFigure 22. Z80,OOO·Z8070 Interface

2235·022

553

The Za010's interface clock and the CPU's clock connect to
a common signal. The Za010's interface clock must be
synchronous with the CPU's clock, and skew between the
two should be minimal. The Za010's data processor clock
can be asynchronous.

transaction. The EPUs use bits 16 and 11 of the instruction
longword as an 10 code. The CPU also transmits the logical
Program Counter that points to the instruction; the Za010,
assuming it is selected, saves this for exception handling.
If the instruction requires data transfers to or from memory,
the CPU controls the bus while the Za010 drives or receives
the data. If the Za010 needs time to process or format the
data, it asserts BSY to delay the CPU.

Instruction Execution

The zao,ooo architecture is designed to enable EPUs
(including the Za010) to serve as coprocessors, executing
instructions in parallel.

The Za010 also uses BSY to control the CPU for overlap
modes. It works together with the EPUO bit in the CPU's
Hardware Interface Control Register, as follows:

When the CPU, with its EPA bit enabled, encounters an EPA
instruction, it outputs the first two words of the instruction to
the EPUs using a CPU-EPU instruction transfer bus

Overlap Mode

OVRLP
Z8070

EPU
Z80,OOO

a

No overlap

00

Simple overlap

00

Intermediate overlap

10

Maximum overlap

11

Description

The Z8070 executes an EPU instruction before the CPU proceeds.
After the Z8070 has received instruction 1 the CPU proceeds to EPA
Instruction 2 then waits for the Z8070 to complete instruction 1.

o

When the Z8070 is executing instruction 1 and instruction 2 is in its
queue, the CPU waits for the Z8070 to complete instruction 1.
When the Z8070 is executing instruction 1 and has instruction 2 and 3
in its queue, the CPU proceeds to EPA instruction 4 and waits for the
Z8070 to complete instruction 1 before issuing instruction 4.

UNIVERSAL INTERFACE

---

SETTOGNDOR

General

+ 5VFOR EPUID

The Universal Interface option (Figure 23) supports
non-Zilog processors, and the zao and zaoo versions not
directly supported by the Za010.

IDo
. . . . . . 023

........ 022

In general, the Za010 is treated as an I/O device similar to
Za500 peripherals (e.g. the Za530 SCC). Data is transferred
over the data bus (00-031)' with the Chip Enable (CEl, Read
(RO), and Write (WR) lines controlling the direction. When
CE and WR go Low, instructions are written to the Za010;
when CE and RO go High, data is read from the Za010.
Universal Interface is enabled at reset by the Za010 OPTo
and OPT1 pins.

.......

021

........ 020

....... Dt9

ID,

~~ ~1

DATA BUS

(24.31)

D"

026 .......

025 ........

D24

INT~:

}

lEI -+-DATA BUS

(0.23)

lEO

BLI~ ~

BW/L -+--

Signal Descriptions

In addition to the pins described earlier for all interfaces, the
Universal Interface uses the following Za010 pins:

Ao. Address Line (input, active High). Selects between
status (1) and normal (0) transactions. Permits access to the
contents of the Status register, and initiates read or write
transactions.

l

INTEARUPT
CONTROL

DATA SIZE

-=- } CPU OPTION
WAIT

SiP

SEQUENCE IN PROGRESS

CHIP ENABLE
N/S

~

WR

NORMALISYSTEM MODE

. . - - READ

WRITE

I

BUS TIMING

RESET

ABORT. Abort (input, active Low). Aborts current
instruction.

Figure 23. Z8070 Universal Interface

554

2235·023

BL/W, BW/L. Byte, LongwordlWord; Byte, Word/
Longword. These signals specify the data transfer size.

BW/L is tied High to program the 28070 for 8/16 bit data
transfers.

BLlW

BW/L

1

1
1

o

WR. Wnte (input, active Low). This signal indicates that the
CPU is writing to the 28070.

Size in Bits

8 (Byte)
16 (Word)
32 (Longword)

o

1

WAIT. Wait (output, open drain). ThiS signal IS activated
when a read or write of floating pOint instructions or data is
attempted while BSY is asserted. It is released when the data
can be accepted or supplied.

Z8070 Transfer and Timing
This interface supports four basic cycles:

CEo Chip Enable (input, active Low). CE signals the

• Read Cycle

beginning of a 28070 transaction and is valid only for the
length of a single transaction or machine cycle.

• Write Cycle

0 0 .031 • Data Bus (bidirectional, active High, 3-state). These

• Interrupt Acknowledge Cycle

are the Data Lines for the Universal Interface.

• Read Status Cycle

INTACK. Interrupt Acknowledge (input, active Low). This
line indicates to the 28070 that an interrupt acknowledge
cycle is in progress.

A Read cycle is distinguished by CE and RD being pulled
Low. A Write cycle is distinguished by CE and WR being
pulled low. An Interrupt Acknowledge cycle is distinguished
by INTACK being pulled Low. All instruction, data, and status
transfers are based on these baSIC cycles.

RD. Read (input, active Low). ThiS signal indicates a read
operation.
SIP. Sequence in Progress (output, active Low). This signal
is forced Low during the first bus transaction of an
instruction, and is held Low until all data transfers associated
with that transaction are complete.

CLK.I

Au

Read Cycle Timing
Figure 24 illustrates read cycle timing. Ao (Low) and the
status on INTACK must remain stable throughout the cycle.
If CE falls after RD falls, or rises before RD rises, the effective
RD is shortened.

CLK.I

~

iifiAci

I
(HIGH)

(HIGH)

Do-D31

lEO

INT

\

I

(HIGH)

\..
\.

Figure 24. Read Cycle Timing, Universal Interface
2235·024. 025

CE

~

WR

\

Do-D31 - { DATA VALID

RD

lEI

(HIGH)

INTACK

CE

WR

I

Ao

I
I
)

RD

(HIGH)

lEI

(HIGH)

lEO

(HIGH)

INT

(HIGH)

Figure 25. Write Cycle Timing, Universal Interface

555

Write Cycle Timing

Z8070 lhmsaction Timing

Figure 25 illustrates write cycle timing. Ao and the status on
INTACK must remain stable throughout the cycle. If CE falls
after WR falls, or rises before WR rises, the effective WR is
shortened.

At any time, the Z8070 can be in one of the following states:

Interrupt Acknowledge Cycle Timing

In Universall nterface, the Z8070 is treated as an I/O device.
After Reset, it is in the Ready state, ready to accept an
instruction via a Write cycle. After the first Write cycle, it
changes to the Sequence-in-Progress state.

Figure 26 illustrates interrupt acknowledge cycle timing.
Between INTACK going low and the falling edge of RD, the
internal and external IEIII EO daisy chains settle. If there is an
interrupt pending on the Z8070, and lEI is High when RD
falls, the acknowledge cycle was intended for the Z8070. In
this case, the Z8070 may be programmed to respond to RD
Low by placing its interrupt vector on 00-07 and internally
setting the appropriate Interrupt-Under-Service latch.
Read Status Cycle Timing

Read status cycles are like the normal read cycles shown in
Figure 24 exceptthat Ao is High; a Read Status Cycle can be
performed at any time. Ao and the status on INTACK must
remain stable throughout the cycle. If CE falls after RD falls,
or rises before RD rises, the effective RD is shortened.

Ready
Sequence-in-Progress
Busy

During the Sequence-in-Progress state, the SIP line is held
Low. It is asserted until the instruction sequence and all
associated data transfers are complete.
For example, if the Z8070 is programmed to use a 16-bit
bus, and the instruction consists of two 16-bit words, the
Z8070 changes from the Ready state to the
Sequence-in-Progress state after the first word (most
significant word first) is transferred. It waits for the transfer of
the second word of the instruction, then determines if any
data transfers are required. It waits for these as necessary.

10

11

12

13

14

15

CLK.I

I

AO \ ' -_ _ _ _ _..J

\'------\\o.._ _

r

---J

(HIGH)

Do·D•• ------~

VECTOR

\'--__1
lEI

lEO

(HIGH)

\'--------------------

\_---------~;--

Figure 26. Interrupt Acknowledge Cycle Timing, Universal Interface

556

2235-026

The Z8070 enters the Busy state when It cannot accept
additional Read or Write cycles, either because the internal
queues are full, or because the requested data is not yet
ready. In the Busy state, the BSY signal is held Low which is a
signal for the CPU to avoid Write or Read cycles. If either a
Write or Read cycle is attempted, the Z8070 will drive the
WAIT line Low. WAIT is released when the Read or Write
cycle can proceed. Note that a Read Status cycle can be
performed at any time, even while WAIT is asserted.
After the instruction transfer and any associated data
transfers are complete, if the internal queues are full, the
Z8070 becomes Busy; otherwise, it becomes Ready.
The Z8070 is always expecting either a Read or a Write
cycle, depending on what state it is in. The use of the BSY
line depends on what overlap option is in effect.

CAUTION; If the Z8070 expects a Read cycle and the
CPU performs a Write cycle, data may be lost. If it
expects a Write cycle and the CPU performs a Read
cycle, spurious data is transferred. Both situations
should be avoided.

The Status register allows the CPU to read the status of the
Z8070 (Table 5). The Read Status cycle can occur at any
time: during Ready, Sequence-in-Progress, and Busy
states, between bytes of an instruction, and during data
transfers.

Table 5. Status Register

a

2

1\'pe

Function

BSY

Read only

1 if Z8070 cannot accept more
data

SIP

Read only

1 if instruction sequence is in
progress

R/W

Read only

Status bit 0 replicates the information provided by the BSY
pin; this allows software to determine if the Z8070 is in the
Busy state.
Status bit 1 replicates the information provided by the SIP
pin; this allows software to determine if the Z8070 is in the
SIP state.

Address Modes
In Universal Interface mode, the Z8070 ignores distinctions
between addressing modes such as R, IR, OA, and X that
move data to, or from, external locations. Specifically, the
Z8070 merely places data on, or reads data from, the data
bus 00-031. This is consistent with the universal interface
philosophy of treating the Z8070 as an I/O device.

Data Bus Width

Z8070 Status Register

Status Register
Bit
Name

For example, the Z8070 can be polled at any time to
determine whether it expects a Read cycle or a Write cycle.
To do this, read the Status register (set Ao to 1 and perform a
Read cycle). Status bit2 on 02 will be 1 if the next operation
should be a Read cycle, or 0 if the next operation should be
a Write cycle.

1 if the next instruction should
be a Read
a if the next instruction should
be a Write

Because of the programmable bus width, the Z8070 acts as
an 8, 16, or 32-bit I/O port. Instructions and data transfers
require multiple Read or Write cycles with the most
significant byte, word, or longword first.
For example, if the single precision number 1234ABCO is to
be transferred over an 8-bit bus, the transactions will occur
as follows:
first byte:
second byte:
third byte:
fourth byte:

12
34
AB
CO

Interrupts, Traps and Aborts
The CPU should respond to an interrupt request by issuing
the appropriate interrupt acknowledge cycle. The
least-significant 8 bits of the Z8070's System Configuration
register contain the vector value read by the CPU during
interrupt acknowledge. The CPU should use this vector
either 1u identify the interrupt source as the 28070 and/or to
select the proper service routine. This is shown in Figure 26.

557

Exception Handling and Overlap
The choice of overlap mode depends on how the user
recovers from arithmetic exception conditions. The Z80l0
can be programmed to cause an interrupt when certain
exceptions occur. When an exception occurs, any
instruction that had been transferred or was in the process of
being transferred to the Z80l0, is flushed. In the Universal
Interface mode, the PC1 and PC2 registers cannot be used
for exception recovery because the Z80l0 does not monitor
addresses.
Both the No Overlap and Intermediate Overlap modes have
the benefit of allowing only one Z80l0 instruction to be
processed at a time. This allows the exception handling
routine to read the Z80l0 flags to determine the cause of the
interrupt, take appropriate action, and resume processing.
In the Maximum Overlap mode, the user must allow for
recovery of the instruction that caused the exception, and
any subsequent instruction in the queue. Since the queued
instruction is lost as a result of the exception, the exception

558

handling routine needs to a) read the Z80l0 flags to
determine the cause of the interrupt, b) take any action
required by the exception itself, c) determine if a subsequent
instruction was flushed during the exception (and if so,
re-transfer that instruction), and d) resume processing.
Hardware Interfacing and Description
The Universal Interface is patterned after the interface for the
Zilog 8500 peripherals, which have been interfaced to the
Zilog's Z80 and Motorola's 68000 CPU, among others. Only
a minimal amount of "glue logic" is required.
The reader should consult the following documents in the
Zllog Microprocessors Applications Reference Book,
Volume 2, 00-2320-01; they demonstrate the versatility of
the 8500 peripheral interface:
"Interfacing Z80 CPUs to the 8500 Peripheral Family," May
1983, pp. 2,29-51.
"Interfacing the 8500 Peripherals to the 68000," October
1982, pp. 4,93-104.

00-2235-03

18010 18000® MMU
Memory Management Unit
Product
Specification

Zilog

AprIl 1985

Features

• Dynamic segment relocation makes software
addresses independent of physical memory
addresses.
• Sophisticated memory-management features
include access validation that protects
memory areas from unauthorized or
unintentional access, and a write-warning
indicator that predicts stack overflow.
• For use with both Z8001 and ZS003 CPU.

General
Description

The ZSOlO Memory Management Unit (MMU)
manages the large 8M byte addressing spaces
of the Z8001 CPU. The MMU provides dynamic
segment relocation as well as numerous
memory protection features.
Dynamic segment relocatIon makes user software addresses independent of the physical
memory addresses, thereby freeing the user
fro'1l specifying where information is actually

• 64 variable-sized segments from 256 to
65,536 bytes can be mapped into a total
physical address space of 16M bytes; all 64
segments are randomly accessible.
• Multiple MMUs can support several translation tables for each Z8001l3 address space.
• MMU archItecture supports multi-programming systems and vIrtual memory Implementations.
located in the physical memory. It also provIdes a flexible, effiCIent method for supporting multi-programming systems. The MMU
uses a translation table to transform the 23-bit
logical address output from the Z8001 CPU
into a 24-bit address for the physical memory.
(Only logIcal memory addresses go to an MMU
for translation; I/O addresses and data, in
general, must by pass this component.)

eli
DMASYNC

PHYSICAL
ADDRUB

.80M.NT

TRAP
DMAIB.GMENT

CHIP,.LBCT

+5V GND eLK

mET

Figure 1. Pin FunctloD8
2046-001. 002

A!
58

RESET

ST,

...
A"

'21
A20

ST,
ST,

ST,
AD,

A18

AD,

Vee

AD10

A"

AD11

A"

ClK

A"
A16

OND

A14

AD13

A"
A12

AD14

AD12

AD15

A11

SNo

A"

SN,

.

BU' TIMING {

NiS

Rfiii

iiEllT
liliP

SN,

Ag

SN,

RESERVED

SN.

SN,

SN,

Figure 2. 48-pln Dual-In-Line Package (DIP).
Pin AlSignmento

559

...
=
o

ICI

General
Description
(Continued)

Memory segments are variable in size from
256 bytes to 64K bytes, in Increments of 256
bytes. Pairs of MMUs support the 128 segment
numbers available for the various zaOOl CPU
address spaces. Within an address space, any
number of MMUs can be used to accommodate
multiple translation tables for System and Normal operating modes, or to support more
sophisticated memory-management systems.
MMU memory-protection features safeguard
memory areas from unauthorized or unintended access by associating special access
restrictions with each segment. A segment is
assigned a number of attributes when its
descriptor is entered into the MMU. When a
memory reference is made, these attributes are
checked against the status information supplied by the Z8001/3 CPU. If a mismatch oc-

curs, a trap is generated and the CPU is interrupted. The CPU can then check the status
registers of the MMU to determine the cause.
Segments are protected by modes of permitted use, such as read only, system only,
execute only and CPU-access only. Other segment management features include a writewarning zone useful for stack operations and
status flags that record read or write accesses'
to each segment.
The MMU is controlled via 22 Special 110
instructions from the zaooc CPU in System
mode. With these instructions, system software
can assign program segments to arbitrary
memory locations, restrict the use of segments
and monitor whether segments have been read
or written.

NC

,.

Ne

11

••.,

A"

12

5.

ST,

A"
A"

"
14

57

ADa

9 8 7 8

543

2 1 H

~

Hnu A U

~

NC

ST,

58

AD,

A"

15

56

AD10

+5.

18

54

ADu

NC

17

53

C.K

NC

18

NC

11

Z8010
....U

.,.

GND
NO

A"

20

50

NC

A"

21

A"

22

4'
4.

AD12

A"
AI<

23

47

ADI3

24

48

A"

2.

45

AD1I1

A"

28

44

NC

NC

AD14

~U"~~H"M"HUH"~~~U

~~~~~)f~~~~~~~~~~~

Figure 2a. 68-pin Chip Carrier.
Pin Assignments

560

2046-003

-

General
Descriptlon
(Continued)

'TATUa

''''OIIII&TIOII

-

. . ....,. IIU...

O,.IIITIOATA.

. . . . .T MU.....

OPPMTIDATA

I Nr....

"'DI-ADII

Itfoo.IN.

ADa-ADIi

. . . . . .T

TRAP

_UT

.u,....... PHYSICAL
ADDllUi

.TATUI
IIIPOMIATloti

. . . . .IIT
TRAP

. . .UIIT

au...........VIlCAL
AD. . . . .

Figure 3. The ehacled areas ID these block clIagrama IUWllrate the reaourc:el uoed ID the two modeo 01 MMU operalioD. In
the Ad.u- TraDilotloD Mode abOWD OD the lell. a~ are traDilateci automatically. In the Commaud Mode abOWD
OD the right. speclllc reglsten are ac:ceued WllDg Special 110 collUDCllldo.

2046-004

561

Segmented
Addressing

Memory
Protection

562

A segmented addressing space-compared
with linear addreSSing-Is closer to the way a
programmer uses memory because each procedure and data set can reside in its own
segment.
The 8M byte 28001 addressing spaces are
divided into 128 relocatable segments of up to
64K bytes each. A 23-bit segmented address
uses a 7-bit segment address to point to the
segment, and a 16-bIt offset to address any
byte relative to the beginning of the segment.
The two parts of the segmented address may
be manipulated separately.
The MMU divides the physical memory into
256-byte blocks. Segments consist of physically
contiguous blocks. Certain segments may be
designated so that writes into the last block
generate a warning trap. If such a segment is
used as a stack, this warning can be used to
increase the segment size and prevent a stack
overflow error.
The addresses manipulated by the programmer, used by instructions and output by the
28001 are called logical addresses. The MMU
takes the logical addresses and transforms
them into the physical addresses required for
accessing the memory (Figure 4). This address
transformation process is called relocation.
The relocahon process is transparent to user
software. A translation table in the MMU
associates the 7-bit segment number with the
base address of the physical memory segment.
The 16-bit logical address offset is added to the
physical base address to obtain the actual
phYSICal memory location. Because a base
address always has a low byte equal to zero,

only the high-order 16 bits are stored in the
MMU and used in the addItIon. Thus the loworder byte of the physical memory location is
the same as the low-order byte of the logical
address offset. This low-order byte therefore
bypasses the MMU, thus reducing the number
of pins required.

Each memory segment IS assigned several
attributes that are used to provide memory
access protechon. A memory request from the
2800113 CPU is accompamed by status informatIon that indIcates the attrIbutes of the
memory request. The MMU compares the
memory request attributes with the segment
attrIbutes and generates a Trap Request
whenever It detects an attrIbute violation. Trap
Request Informs the 2800113 CPU and the
system control program of the violatIon so that
approprIate actIon can be taken to recover.
The MMU also generates the Suppress SIgnal
SUP in the event of an access VIOlatIon. Suppress can be used by a memory system to inhIbit stores into the memory and thus protect the
contents of the memory from erroneous
changes.
FIve attrIbutes can be associated WIth each
segment. When an attempted access violates
anyone of the attributes associated with a segment, a Trap Request and a Suppress signal
are generated by the MMU. These attributes
are read only, execute only, system access
only, inhIbit CPU accesses and inhIbit DMA
accesses.

Segments are specified by a base address
and a range of legal offsets to this base
address. On each access to a segment, the offset is checked against this range to insure that
the access falls within the allowed range. If an
access that lies outside the segment is attempted, Trap Request and Suppress are generated.
Normally the legal range of offsets within a
segment is from 0 to 256N + 255 bytes, where
OsNs255. However, a segment may be
speCified so that legal offsets range from 256N
to 65,535 bytes, where OsNs255. The later
type of segment is useful for stacks since the
28000 stack manipulation instructions cause
stacks to grow toward lower memory locations.
Thus when a stack grows to the limit of its
allocated segment, additional memory can be
allocated on the correct end of the segment.
As an aid in maintaining stacks, the MMU
detects when a write is performed to the lowest
allocated 256 bytes of these segments and
generates a Trap Request. No Suppress signal
is generated so the write is allowed to proceed.
This write warning can then be used to indicate that more memory should be allocated to
the seqment.

II·BlT LOGICAL ADD. . . .
•
BIT .... MUST BE
EQUAL TO FLAG URS

7

OFFSET

-..,

r---------I
I
I
I
I
I
I

.: :

TULE OF 84
SEGMENT DESCRIPTOR
REGt8TEAB

I

..,
.
.
"

24·BIT PHYSICAL ADOMas

Figure 4. Logical-to-Physical Address Trcmslalion

2046-005

MMU
The MMU contams three types of regIsters:
Register
Segment Descriptor, Control and Status. A
Organization set of 64 Segment Descriptor RegIsters supp!Jes
the mformation needed to map logICal memory
addresses to physical memory locations. The
segment number of a logical address determmes whICh Segment Descnptor Register IS
used in address translation. Each Descnptor
Register also con tams the necessary mformation for checking that the segment location
referenced is wlthm the bounds of the segment
and that the type of reference IS permItted. It
also indicates whether the segment has been
read or wrItten.
In addition to the Segment Descnptor
RegIsters, the 28010 MMU contams'three 8-blt
control registers for programming the device
and SIX 8-blt status regIsters that record mformatlon in the event of an access violation.
Segment Descriptor Registers. Each of the 64
Descriptor Registers contains a l6-bit base
address field, an 8-bit limit field and an 8-bit
attribute field (Figure 5). The base address
field IS subdivided mto high- and low-order
bytes that are loaded one byte at a time when
the descriptor is imtlalized. The limit field contains a value N that indICates N + I blocks of
256 bytes have been allocated to the segment. •
The attribute field contains eIght flags
(FIgure 6). Five are related to protecting the
segment against certain types of access, one
indICates the speCIal structure of the segment,
and two encode the types of accesses that have
been made to the segment. A flag is set when
its value is I. The follOWing brief descriptions
indicate how these flags are used.
Read-Only (RD). When thIS flag IS set, the segment IS read
only and 15 protected agamst any WrIte access.
System·Only (SYS) , When thIS flag IS set, the segment can
be accessed only In System mode, and IS protected agamst
any access In Normal mode.
CPU-Inhullt (CPUI), When thIS flag IS set, the segment IS
not accessIble to the currently execuhng process, and IS
protected agamst any memory access by the CPU, The
segment IS, however, accessable under DMA.
Execute-Only (EXC). When thIS flag IS set, the segment
can be accessed only durmg an instruction fetch or access
by the relahve addressmg mode cycle, and thus IS pro~
teded agamst any access durmg other cycles
DMA-InhIlllt (DMAI). When thIS flag IS set, the segment
can be accessed only by the CPU, and thus IS protected
agamst any access under DMA.
Dlrechon and Warnmg (DIRW), When thIS flag IS set, the
segment memory locations are conSIdered to be orgamzed
In descendmg order and each Wrlte to the segment IS
checked for access to the last 256·byte block. Such an
access generates a trap to warn of potenhal segment
overflow but no Suppress SIgnal IS generated.
I

Changed (CHG). When thIS flag IS set, the segment has
been changed (wrItten) ThIS bIt IS set automahcally durmg
any WrIte access to thIS segment If the wrIte access does not
cause any vlOlahon.
Referenced (REF). When thIS flag IS set, the segment has
been referenced (eIther read or wrItten) ThIS bIllS set
automahcally durmg any access to the segment If the
access does not cause a vlOlahon.
*In the stack mode, segment size
2046·006, 007, 008

IS

BASE ADDRESS LIMIT ATTRIBUTE
FIELD
FIELD
~

87

•"::~~: ~

SDA
SDA1
SD",

07

FIELD

07
LO
L1

.•

BAl2

L2

A1
A.

SORa3 BAH83 BAL83

L83

A83

BAH2

I
I
I
I
I
I
I
I

Figure 5. Segment Descriptor Registers

7

•

IREFICHGrlAWIDMAllEXCICPUllSYSI RD

I

Figure 6. Attribute Field in Segment Descriptor Register

Control Registers. The three user-accessIble
8-bit control registers in the MMU direct the
functlonmg of the MMU (Figure 7). The Mode
Register provides a sophistICated method for
selechvely enabling MMUs in multlple-MMU
configurations. The Segment Address Register
(SAR) selects a parhcular Segment Descriptor
Register to be acpessed during a control
operation. The Descriptor Selection Counter
RegIster points to a byte within the Segment
Descriptor Register to be accessed during a
control operahon.
7

&

8

4

3,2

0

....J!

LH_.L.T_RN_'.L.U_R_SIL..MST....JIL..N_MS..JI_.....I_D.....

os

!• •I
I

SEGMENT DESCRIPTOR NUMBER

.

'

I

'

7

0

MDDE

•
I

21
0 , •

I

I

SEGMENT

_ ADDRESS

0

I DSC I g:~~~~J~R

_'-....I..--J'--'--'._.J.,_....I---J. COUNTER

L.

Figure 7. Control Registers

The Mode Register contains a 3-bit identihcahon held (ID) that dishnguishes among
eIght enabled MMUs in a multlple-MMU conhguration. This field IS used during the segment trap acknowledge sequence (refer to the
sectIOn on Segment Trap and Acknowledge).
In addition, the Mode Register contains five
flags.
Multiple Segment Table (MST), ThIS flag mdlcates whether
mulhple segment tables are present In the hardware confIguratIon. When thIS flag IS set, more than one table IS
present and the Nis lme must be used to determme
whether the MMU contams the approprIate table.
Normal Mode Select (NMS). ThIS flag mdlcates whether
the MMU IS to translate addresses when the N/S lme IS
HIgh or Low, If the MST flag IS set, the N/S lme must
match the NMS flag for the MMU to translate segment
addresses, otherWIse the MMU Address lInes remam
3-stated,

64K-256N

563

i...o

I

Upper Range Select (URS). ThIs flag IS used to md10ate
MMU
whether the MMU contams the lower-numbered segment
Register
descriptors or the hIgher-numbered segment descriptors.
Organization The most slgmhcant bIt of the segment number must match
(Continued)
the URS flag for the MMU to translate segment addresses,
otherwIse the MMU Address hnes remam 3·stated.
Translate (TRNS). ThIs flag md10ates whether the MMU IS
to translate 10g1Oal program addresses to phys10al memory
locahons or IS to pass the 10g1Oal addresses unchanged to
the memory and wIthout protechon checkmg. In the non·
translahon mode, the most slgmhcant byte of the output IS
the 7·b!t segment number and the most slgmhcant bit is O.
When thIs flag IS set, the MMU performs address translahon and attribute checkmg.
Master Enable (MSEN). ThIs flag enables or dIsables the
MMU from performmg ItS address translahon and memory
protechon functions. When thIs flag IS set, the MMU performs these tasks; when the flag is clear the Address lmes
of the MMU remam 3-stated.

The Segment Address Register (SAR) pOints
to one of the 64 segment descriptors. Control
commands to the MMU that access segment
descriptors implicitly use this pointer to select
one of the descriptors. This register has an
auto-incrementing capability so that multiple
descriptors can be accessed in a block
reael/write fashion.
The Descriptor Seleclion Counter Register
holds a 2-bit counter that indicates which byte
in the descriptor is being accessed during the
reading or writing operation. A value of zero
in this counter indICates the hIgh-order byte of
the base address field is to be accessed, one
indicates the low-order byte of the base
address, two indicates the limit field and three
indicates the attribute field.
Status Registers. Six 8-bit registers contain
information useful in recovering from memory
access violations (Figure 8). The Violation
Type Register describes the conditions that
generated the trap. The Violation Segment
Number and Violation Offset Registers record
the most-significant 15 bits of the logical
address that causes a trap. The Instruction
Segment Number and Offset Registers record
the most-significant 15 bits of the logical
address of the last instruction fetched before
the first accessing violation. These two
registers can be used in conjunction with
external circuitry that records the low-order
offset byte. At the time of the addressing'violation, the Bus Cycle Status Register records the
bus cycle status (status code, reael/write mode
and normaVsystem mode).
The MMU generates a Trap Request for two
general reasons: either it detects an access

564

violalion, such as an attempt to write into a
read-only segment, or it detects a warning
condilion, which is a write into the lowest 256
bytes of a segment with the DIRW flag set.
When a violation or warning condition is
detected, the MMU generates a Trap Request
and automatically sets the appropriate flags.
The eight flags in the Violation Type Register
describe the cause of a trap.
Read-Only V.olation (RDV). Set when.Jhe CPU attempts to
access a read-only segment and the R/W lme .s Low.
System Violation (SYSV). Se\..!<--------- ----- 1----- - -- -----

1{(4)

~

1\ .. f---' .".
®

Ai

g
iii

SNo-SN,

SIOIACKNOWLEDGE

I

MEMORY ACCESS

j

--------®- I+:X

~

DMASYNC

@STO-ST.

N/i R/ii

A,-AII

---

~

,---\"

------------

------------

®-

~~

:it

.@ ......

~-

~:========== . [\/

a

>~

/

~
~

~

i..lt'.1!...

MeMORV ACCESS

~ -@

r-k!D

~

~I~

-I

'\

r---®-~

®-~

/
,.-----

------

'------ ------

-<

~

\L

MEMORY ACCESS

"

31

TRAP ACKNOWLEDGE

9

®--

~

;r

-[®

==============> ~

~

~:====================================:

~ f.®

572

2046-014

AC Characteristics
No.

Symbol

Z8010

Parameter

4 MHz
Min
Max

Clock Cycle Time
250
Clock WIdth (HIgh)
105
Clock WIdth (Low)
105
Clock Fall Time
Clock RIse TIme
DS I (Acknowledge) to Read Data
Valid Delay
TdDSA(RDf)
DS t (Acknowledge) to Read Data
7
Float Delay
TdDSR(RDv)
DS I (Read) to AD Output Driven Delay
8
TdDSR(RDf)
58 1 (Read) to Read Data Float Delay
9
10- TdC(WDv) - - CLK t to Write Data Valid Delay
ThC(WDn)
CLK I to Write Data Not Valid
30
11
Hold TIme
Address Strobe WIdth
60
12
TwAS
TsOFF(AS)
Offset Vahd to AS' t Setup TIme
13
45
ThAS(OFFn)
AS t to Offset Not Valid Hold TIme
14
60
15- TdAS(C)--- AS I to CLK t Delay
110
TdDS(AS)
DS t to AS I Delay
16
50
TdAS(DS)
17
AS t to 58 I Delay
50
TsSN(C)
SN Data Vahd to CLK t Setup TIme
18
100
ThC(SNn)
CLK t to SN Data not Vahd Hold TIme
19
0
DMASYNC Vahd to CLK t Delay
20 - TdDMAS(C) 120
TdSTNR(AS)
21
Stal!os (STo-ST 3 , N/S, R/W) Vahd to
50
AS t Delay
TdC(DMA)
22
CLK t to DMASYNC j Delay
20
TdST(C)
Status (STo-ST 3 ) Vahd to CLK t Delay
23
100
TdDS(STn)
58 t to Status Not Vahd Delay
24
0
25 - TdOFF(Av)-- Offset Valid to Address Output
Valid Delay
TdST(Ad)
Status Valid to Address Output
26
Driven Delay
TdDS(Af)
27
i5S t to Address Output Float Delay
TdAS(Ad)
28
AS I to Addres Output Driven Delay
TdC(Av)
CLK t to Address Output Valid Delay
29
AS t to SEGT I Delay
30 - TdAS(SEGT) TdC(SEGT)CLK t to SEGT t Delay
31
TdAS(SUP)
AS t to SUP j Delay
32
TdDS(SUP
DS t to SUP t Delay
33
TsCS(AS)
ChIp Select Input Valid to AS t Setup
34
10
TIme
35 - ThAS(CSn)-- AS t to Chip Select Input Not Valid---60
Hold Time
TdAS(C)
AS t to CLK t Delay
10
36
TsCS(RST)
Chip Select Input Valid to RESET t
37
150
Setup Time
ThRST(CSn)
RESET t to Chip Select Input Not
0
38
Valid Hold Time
TwRST
RESET Width (Low)
2TcC
39
40 - TdC(RDv) - - CLK t to Read Data Valid Delay
TdDS(C)
DS t to CLK t Delay
41
30
TdC(DS)
42
CLK I to DS t Delay
0
I
TcC
TwCh
2
3
TwCl
4
TIC
5-TrC
TdDSA(RDv)
6

NOTES:
1. 50 pI Load.
2. 2,2K Pull-up.
r All 6 MHz bmings are preliminary,
*

Units In nanoseconds (ns),

Z8010
6MHzt
Min
Max

10 MHz
Min
Max

Z8010

165
70
70

100
40
40

20
20
100

10
15
80

10
10
60

75

60

45

80
60
80

60
45
50

100
75
125

60
20

10

50
35
40
90
30
40
40
0
80
30

30
20
20
50
15
30
30
0
60
10

15
60
0

10
30
0

Notes*

N

I...
0

II
II
c::I

175

90

60---1-

155

75

45

160
145
255
160
300
150
155

130
70
155
100
200
90
100

100
40
100
60--1,21,2
100
1,2
55
1,2
60

10

10

40

20

10
100

10
60

0

0

2TcC
460

2TcC
300

20
0

190
10
0

Tlmmg measurements are made at the followmg voltages:
Low
Hlgh
4,0 V
Clock
2.0 V
Output
Input
20V
±0,5 V
Float

bov

oav
oav
oav

573

Absolute
Maximum
Ratings

Voltages on all pins with respect
toGND ................... -0.3Vto +7.0V
Operating Ambient
Temperature ....... See Ordering Information
Storage Temperature ........ - 65°C to + 150°C

Stresses greater than those lIsted under Absolute MaxImum Ratmgs may cause permanent damage to the deviCe.
ThIs IS a stress ratmg only; operation of the deVIce at any
condIhon above those mdICated III the operatIonal sechons
of these speclhcahons IS not ImplIed. Exposure to absolute
maXImum ratmg condIhons for extended penods may affect
device rehablhty.

Standard
Test
Conditions

The DC characteristics and capacitance section below apply for the following standard test
conditions, unless otherwise noted. All voltages
are referenced to GND. Positive current flows
into the referenced pin.
Standard conditions are as follows:

drawings are in the Package Information section
in this book. Refer to the Literature List for additional documentation.
+5V

22.

• +4.75 V ~ Vee ~ +5.25 V
• GND = 0 V
• O°C ~ TA ~ +70°C
The Ordering Information section lists temperature ranges and product numbers. Package

DC
Characteristics

Symbol

Parameter

Min

Max

Unit

VCH

Clock Input Hlgh Voltage

Vce-OA

VCC+ 0.3

V

Dnven by External Clock Generator

VCL

Clock Input Low Voltage

-0.3

OA5

V

DrIven by External Clock Generator

VIH

Input Hlgh Voltage

2.0

VCC+0.3

V

VIL

Input Low Voltage

-0.3

0.8

VOH

Output Hlgh Voltage

VOL

Output Low Voltage

2A
OA

Condition

V
V

IOH

V

IOL

= -250 ~A
= +2.0 rnA

IlL

Input Leakage

±10

~A

OA s VIN

S

+2A V

IOL

Output Leakage

±10

~A

OA

VIN

S

+2A V

ICC

Vce Supply Current

300

rnA

S

NOTE: The on-chIp back-bias voltage generator takes approxImately 20 ms to pump the back-bias voltage to -2 5 V after the power has
been turned on The performance of the Z8010 Z-MMU 1S not guaranteed dunng thls penod.

574

8085·0209

ORDERING INFORMATION
ZS010 MMU, 4.0 MHz
4S-pin DIP
6S-pin LCC
Z8010 PS
Z8010 LL *t
Z8010 CS
Z8010 CEt
ZS010A MMU, 6.0 MHz
4S-pin DIP
6S-pin LCC
Z8010APS
Z8010ALL*t
Z8010A CS
ZS010B MMU, 10.0 MHz
4S-pin DIP
6S-pin LCC
Z8010BPS
Z8010BLL*t
Z8010BCS

Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic 01 P
Ceramic LCC
Plastic PCC

TEMPERATURE
S = O°Cto + 70°C
E = -40°C to +85°C
M*= -55°Cto +125°C
L* = -55°Cto +110°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DIP, O°C to + 70°C.

t Available soon
* For Military Orders, contact your local Zilog Sales Office for Military Electrical Specifications.

575

Z80 15 Z8000® PIIMU
Paged Memory
Management Unit
Product
Specification

April 1985

FEATURES
•

PMMU architecture supports multiprogramming
systems and virtual memory implementations.

•

Dynamic page relocation makes software addresses
independent of physical memory addresses.

• Sophisticated memory management features include
access validation that protects memory areas from
unauthorized or unintentional access, and a writewarning indicator that predicts stack overflow.

• 64 pages, each 2048 bytes in length, can be mapped
into a total physical address space of 16 megabytes; all
64 pages are randomly accessible.
•

Pages larger or smaller than 2048 bytes can be easily
implemented.

• The number of accessible pages can be increased by
using multiple PMMUs.

GENERAL DESCRIPTION
The Z8015 Paged Memory Management Unit (PMMU), a
new member of Zilog's Z8000 Family, is designed to support
a paged virtual memory system for the Z8003 Virtual
Memory Processor Unit (VMPU). Although designed
primarily for the Z8003, the PMMU can also be used to
support other CPUs in the Z8000 Family. The sophisticated
memory management features of the PMMU include
access validation for memory protection, a write-warning

that gives advance warning of possible stack overflow, and
the generation of instruction aborts for accesses to pages
not in main memory. Each PMMU can manage a basic
memory area of sixty-four 2048-byte, fixed-size pages. The
VMPU's 8M byte logical address space is translated by the
PMMU into a 16M byte physical address space. Page size
can be easily changed and multiple PMMUs can be
combined to support more pages.

FUNCTIONAL DESCRIPTION
The Z8015 Paged Memory Management Unit (PMMU)
manages the 8M byte addressing spaces of the Z8003
VMPU. The PMMU provides dynamic page relocation as
well as numerous memory protection features.
Dynamic page relocation makes user software addresses
independent of the physical memory addresses, thereby
freeing the user from specifying where information is
located in the physical memory. It also provides a flexible,
efficient method for supporting multiprogramming systems.
The PMMU uses a content-addressable translation table to
transform each 23-bit logical address output from the VM PU
into a 24-bit address for the physical memory. (Only logical
memory addresses go to a PMMU for translation; 1/0
addresses and data bypass this component.) The
translation table consists of 64 page descriptors; each
descriptor contains address translation, status, and access
information for one memory page. Each PMMU can then

manage up to 64 pages of memory.
Multiple PMMUs can be used to support more than 64
pages within a given address space. In addition, PMMUs
can be used to accommodate separate translation tables for
System and Normal operating modes.
The PMMU is designed to support a memory page 2048
bytes in length. This basic page length can be increased or
decreased using a minimal amount of external circuitry.
The PMMU is specially designed to operate with a Z8003
VMPU to implement a paged virtual memory ~ystem. If the
current PMMU instruction addresses a page not in main
memory (a page fault), the PMMU initiates an Instruction
Abort operation in the VMPU. During an abort, the PMMU
aborts the execution of the current instruction, then saves
the information needed to restart the aborted instruction. On
completion of the abort, the PMMU initiates a trap in the

577

i...
CIt

I
c:I

VMPU to a routine that brings the addressed page into main
memory, updates the descriptor table of the PMMU to allow
address translation to the new page, and restarts the
execution of the interrupted instruction.
The logical address that caused the page fault is available in
three violation address registers of the PMMU. This
information can be used to fetch the required instruction or
data page into main memory andlor to create a page
descriptor entry so that the executing program can access
those instructions or data. The logical address of the
instruction generating the page fault is available in three
instruction address registers of the PMMU. This information
can be used to reset the Program Counter to restart the
instruction. The instruction to be restarted must also be
examined to determine if adjustments must be made to any
VMPU registers to ensure correct execution. Finally, the
ReadIWrite Data Count register can be accessed so that
certain instructions, such as Load Multiple, can be restarted
correctly.
As an aid in implementing efficient paging algorithms, the
PM M U provides Changed and Referenced flags for each
page descriptor register. The Changed flag indicates that a
page has been altered and hence must be copied to
secondary storage before that physical memory can be
overwritten by another page. The Referenced flag can be
used to determine which pages have not been accessed by
an executing program-these are the pages that should first
be removed from memory when room must be made to
bring another page into memory.
PMMU memory protection features safeguard memory

areas from unauthorized or unintended access by
associating special access restnctlons with each page. A
page is assigned a number of attributes when its descriptor
is initially entered into the PM M U. When a memory reference
is made, these attributes are checked against the status
information supplied by the VMPU. If a mismatch occurs,
the instruction is aborted, a Trap Request signal is
generated, and the VMPU is interrupted. The VMPU then
checks the status registers of the PMMU to determine the
cause of the abort.
Pages are protected by modes of permitted use, such as
read only, system only, and execute only. A Valid flag
indicates whether or not a descriptor has been initialized.
Other page management features include a Write Warning
flag useful for stack operations.
The PMMU is controlled by 20 Special 1/0 instructions,
which can be issued from the VMPU in System mode only.
With these instructions, system software can assign
program pages to arbitrary memory locations, restrict the
use of pages, and monitor whether pages have been read
or written.
The PMMU has two operating modes: an Address
Translation mode in which addresses are translated
automatically as they are received, and a Command mode,
during which specific registers in the PMMU are accessed
using Special 110 commands. Figure 1 shows two simplified
block diagrams that illustrate the internal organization and
data/signal flow within the PMMU. The resources used in the
Translation and the Command modes are shown,
separately, in Figures 1a and 1b.

SEGMENTED ADDRESSING AND
ADDRESS TRANSLATION
Compared with linear addressing, a segmented addressing
space is closer to the way a programmer uses memory
because each procedure and data set can reside in its own
segment.
The 23-bit addresses output by the VM PU divide an 8M byte
addressing space into 128 segments of up to 64K bytes
each. A 23-bit segmented address consists of a 7-bit
segment number and a 16-bit offset used to address any
byte relative to the beginning of the segment. The two parts
of the segmented address (segment number and offset) can
be manipulated separately.
The PMMU divides physical memory into 2048-byte pages.
Pages are assumed to be allocated in memory on 2048-byte
boundaries so that the 11 low-order bits of the starting
location of each page are always equal to zero. Segments in

578

a virtual memory system can consist of pages that need not
be in physical storage. Those segment pages in main
memory need not be contiguous. Segments can have a
variable number of pages. Certain pages can be
designated so that writes into the last 128 bytes generate a
warning trap without causing an instruction abort. If such a
page is used as the last page of the system stack, the
warning trap can be used to initiate the allocation of another
page to the stack segment to prevent a stack overflow error.
The addresses manipulated by the programmer, used by
instructions, and output by the VMPU are called logical
addresses. The PMMU translates logical addresses into the
physical addresses required for accessing memory; this
process is called relocation.

Figure 1a. Address Translation Mode PMMU Operating Modes, Simplified Flow Diagram

The translation activity in the PMMU that provides address
relocation is controlled by four internal control flags and six
input lines, The four flags are:

Normal Mode Select (NMS) Flag. When the Multiple Page
Table flag is set, this flag indicates whether the PMMU
contains System OJ Normal page desc.-iptors,

Master Enable (MSEN) Flag. This flag controls when the
PMMU outputs physical addresses on its Address bus (A)
lines, When this bit IS clear, the A lines remain 3-stated and
no checking is performed,

The six input lines used in the control of the PMMU are:

Translate (TRNS) Flag. This flag determines whether the
output on the A lines is the logical address as input (with
most significant bit at 0) or a translated address, When
translation is not performed, no checking is done,
Multiple Page Table (MPT) Flag. This flag Indicates
whether separate PMMUs are to be used for System and
Normal pages,

2081·001

Nis Line. This line is used by the PMMU to distinguish
System mode accesses from Normal mode accesses,
When the Multiple Page Table flag is set, the N/S line acts as
a chip-select mechanism,
Chip Enable (CE) Line. This line acts as a master enable
control line: it must be asserted for any address translation to
occur or for any address to be output by the PMMU,

Status Lines (STo·STJJ. These four lines are used by the
PMMU to determine the type of transaction in progress,

579

S'[Q:-ST3

R/W Nil

Figure 1b. Command Mode PMMU Operating Modes, Simplified Flow Diagram
Access violation checking, write warning checking, and
page fault monitoring functions occur only when the PMMU
is enabled for address translation. For example, if Chip
Enable is not asserted, the PMMU does not generate an
Abort Request even if none of its descriptors match the
logical address.
The address translation process is transparent to user
software; a simplified flow diagram of this process is shown
in Figure 2. A content-addressable translation table in the
PMMU compares the 7-bit segment number and five

580

most-significant bits of the offset with the logical address
field of each descriptor. If a match occurs and that
descriptor's Valid flag is set, the physical address field of that
descriptor is accessed. The 11-bit logical address within the
page is concatenated to this 13-bit physical base address to
obtain the actual physical memory location. Because the
base address of a page always has the low-order 11 bits
equal to zero, only the high-order 13 bits are stored in the
PMMU and used in the translation. The PMMU outputs the
16 most significant bits of the translated address.

2081-002

~_ _ _1..;,1~10;....__
8r"7_ _ _ _ _-.0 LOGICAL

SEGMENT NUMBER

I-_O_F_FS_ET_-+-_ _I -_ _ _ _--IADDRESS

PHYSICAL
ADDRESS
23

~~-----~v~----~
OUTPUT BY PMMU

Figure 2. Loglcal·to-Physlcal Address Translation

MEMORY PROTECTION
Each memory page is assigned several attributes that are
used to provide memory access protection. A memory
request from the VMPU is accompanied by status
information that indicates the attributes of the memory
request. The PMMU compares the memory request
attributes with the page attributes and generates Instruction
Abort Request, Suppress, and Trap Request signals
whenever it detects an attribute violation.
An Abort Request is used to generate the Abort and Wait
inputs to the VMPU that cause the current instruction to be
aborted. The Suppress input is used by the VMPU to inhibit
stores into the memory and thus protect the contents of the
memory from erroneous changes. A Trap Request informs
the VMPU and the system control program of the violation
so that appropriate action can be taken for recovery.
Three attributes: read only, execute only, and system access
only, can be associated with each page. When an
attempted access violates anyone of the page attributes,
Abort Request, Trap Request, and Suppress signals are
generated by the PMMU.
Each descriptor register has a Valid flag in the attribute field.
When set to 1, this flag indicates that the descriptor contains

2081·003

valid translation information and its logical address field is to
be used in the associative match process. If Chip Enable is
asserted and no match is found, the PMMU, if enabled,
generates Abort Request, Trap Request, and Suppress
signals. The PMMU is enabled under either of the following
conditions: the MSEN and TRNS flags are both 1 and the
MPT flag is 0; or the MSEN and TRNS flags are both 1, the
MPTflag is 1, and both input N/S and the NMS flag have the
same value.
Normally, the legal range of offsets within a segment goes
from 0 to 65,535 bytes. A stack segment, however, has legal
word offsets ranging downward from 65,534 to 0 bytes; the
stack manipulation instructions cause stacks to grow toward
lower memory locations. When a stack grows to the limit of
its allocated segment, additional memory can be added to
the segment. As an aid in maintaining stacks, the PMMU
detects when a write is performed to the lowest-allocated
128 bytes of a stack page and generates a Trap Request if
the DIRW attribute flag is set in the page descriptor. Since
neIther a Suppress nor Abort Request signal is generated,
the write is allowed to proceed. This write warning can then
be used to indicate that more memory (that is, another page)
needs to be allocated to the segment.

581

PMMU REGISTER ORGANIZATION
The PMMU contains a set of 64 page descriptor registers
that supply the information needed to map logical memory
addresses to physical memory locations. The PMMU also
contains three 8-bit control registers for programming the
PMMU, and nine 8-bit status registers to record information
in the event of an access violation.

Page Descriptor Registers
The segment number and five most-significant bits of a
logical address determine, by associative lookup, which
page descriptor register is used in address translation. Each
register also contains the necessary information to enable
checking to ensure that the type of reference made is
permitted. An indication that the segment has been
previously read or written is also contained in the register.
Each of the 64 page descriptor registers contains a 12-bit
logical address field, a 13-bit physical address field, and a
7-bit attribute field (Figure 3).

Read-Only (RD). When this flag is set, the page is read-only
and is protected against any write access.
System-Only (SYS). When this flag is set, the page can be
accessed only in System mode, and is protected against
any access in Normal mode.
Execute-Only (EXC). When this flag is set, the page can be
accessed only during an Instruction Fetch cycle and is thus
protected against access during other cycles.
Direction and Warning (DIRW). When this flag is set, the
page's memory locations are considered to be organized in
descending order and each write to the page is checked for
access to the lowest 128 bytes. Such an access generates a
Trap Request signal to warn of potential stack overflow, but
neither an Abort Request nor a Suppress signal is
generated.
Changed (CHG). When this flag is set, the page has been
changed (written into). This bit is set automatically during
any write access to this page if the write access does not
cause a violation.

Referenced (REF). When this flag is set, the page has been
Figure 3. Page Descriptor Register Format
The logical address field is used during the associative
search phase of address translation; a match of this field
with the most-significant bits of the logical address indicates
that the descriptor is to be used during physical address
generation. The physical address field supplies the
most-significant bits of the generated physical address.
The attribute field contains seven flags (Figure 4). Three
flags protect the page against certain types of access, one
indicates the special structure of the page, and two encode
the types of accesses that have been made to the page. The
seventh flag is used to indicate whether or not the
information in the descriptor is valid. A flag is set when its
value is 1. During a write to only the attribute field, bit 7 of the
byte is ignored. When an attribute field is read, bit 7 is
undefined. When an entire descriptor is accessed, bit 7 will
be part of the physical address field. The following
descriptions explain how these flags are used.
Valid (VALID). When this flag is set, the descriptor contains
valid page information for the currently executing process.
When this bit is clear, the logical address generated by the
VMPU is not compared against the contents of the logical
address field, so the descriptor is not used for address
translation. Only descriptors that have this flag set are used
during the associative search.
8
IVALIDI REF I CHG I DIRW I EXC I SYS I RD

°I

Figure 4. Attribute Field of Page Descriptor Register

referenced (either read or written). This bit is set
automatically during any access to the page if the access
does not cause a violation.
The byte format that is required to write into or read from an
attribute field is shown in Figure 5.

IVALIDI

REF

I I I I I I
CHG DIRW

!XC

SYS

RD

Figure 5. Format of Byte for Reading or Writing
a Descriptor's Attribute

Control Registers
The three user-accessible, 8-bit control registers in the
PMMU direct the functioning of the PMMU (Figure 6). The
Mode register provides a sophisticated method for
selectively enabling
PMMUs in
multiple-PMMU
configurations. The Descriptor Address (DAR) register
selects the particular page descriptor register to be
accessed during a control operation. The Descriptor
Selection Count (DSC) register points to the byte in the Page
Descriptor register to be accessed during a control
operation.
32
IMSENITRNS I

°

ID

I MPT I NMS I

MODE

65

1~~~~~~JOR
°

I. .

_0....1._0...I1..........I._D_ES-'f_R_IPT_0I...IR_NU_M...
IB_ER.....I_...

I 0

21

0 0 0I

...._.l....-...i..........I._-'I_-I-1_

...._

Dse

I ~~~~+rJ~R

..1 _.... COUNT

Figure 6. Control Registers
582

2081·004,005.006

Mode Register

Status Registers

The Mode register contains a 3-bit identification (10) field
that can distinguish up to eight enabled PMMUs in a
multiple-PMMU configuration. This field is used during the
Trap Request acknowledge sequence. In addition, the
Mode register contains the following four flags:

The following nine 8-bit status registers contain information
useful in recovering from memory access violations
(Figure 7):

Multiple Page Table (MPT). This flag indicates whether
more than one page table is present in the hardware
configuration. When this flag is set, more than one table is
present and the N/S line is used to determine whether the
PMMU contains the appropriate table.
Normal Mode Select (NMS). This flag indicates whether
the PMMU is to translate addresses when the N/S line is
High or Low. If the MPT flag is set, the N/S line must match
the NMS flag for the PMMU to translate addresses;
otherwise, the PMMU address lines remain 3-stated.
Translate (TRNS). This flag indicates whether the PMMU is
to translate logical program addresses to physical memory
locations or is to pass the logical addresses unchanged to
the memory without protection checking. In the
Non-Translation mode, the most-significant output byte is
the 7-bit segment number and the most-significant bit is O.
When TRNS is set, the PMMU performs address translation
and attribute checking.
Master Enable (MSEN). This flag enables or disables the
PMMU from performing its address translation and memory
protection functions. When this flag is set, the PMMU
performs these tasks; when the flag is clear the address lines
of the PMMU remain 3-stated.

Descriptor Address Register (DAR)
This register points to one of the 64 page descriptor
registers. Control commands to the PMMU that access
page descriptors implicitly use this pointer to select one of
the page descriptor registers. The DAR has autoincrementing capability so that multiple descriptors can be
accessed in a block read/write fashion.

Descriptor Selection Count (DSC) Register
This register holds a 2-bit counter that indicates which byte
in the descriptor is being accessed during Read or Write
operations. A zero in this counter indicfltes that the
highest-order byte of the descriptor is to be accessed
(most-significant byte of the logical address field), a one
indicates the next byte of the descriptor, a two indicates the
third byte, and a three indicates the least-significant byte
(containing the attribute field).

2081-007

1

FATL! sww !pww ! EXCV! PGFT!

0

! svsv! RDV

SEGMENT NUMBER

I]
1

TRAP
TYPE

I

VIOLATION
ADDRESS

OFFSET
__
_ _BVTE
_ _ _ _ _....
......_ _ _ _UPPER

7

:I::::::LOW:ER:O:FFS:ET:BV:TE:::::I
10

Ii...

SEGMENT NUMBER

......____U_P_PE_R_O_FF_S_ET_B_V_TE____....II]INSTRUCTION
ADDRESS

:I
:I

7

:I::::::LOW:ER:O:FFS:ET:BV:TE:::::I
7

d

3

, CPU STATUS
,
,
COUNT

..,

CI'I

BUS CYCLE
STATUS

READ/WRITE
DATA COUNT

Figure 7. Status Registers

Trap Type Register. This register describes the conditions
that generate a Trap Request signal.
Violation Segment Number and Violation Offset
Registers. These three registers record the logical address
that caused a Trap Request.
Instruction Address Registers. These three registers
record the logical address of the last instruction fetched
before the first warning, access violation, or page fault.
Bus Cycle Status Register. This register records the bus
cycle status (status code, Read/Write operation and
Normal/System mode).
Read/Write Data Count Register. This register contains a
4-bit counter that counts the number of read and write data
transactions whose addresses have been translated by the
PMMU since the last instruction fetch cycle. This count is

583

locked when an Abort Request is generated, and indicates
the number of successful data transactions performed by
the aborted instruction.

Violation Type Register (VTR) Flags
The VTR is used by the PMMU to determine the cause of a
Trap Request. The PMMU generates a Trap Request when:
it detects an access violation, such as an attempt to write into
a read-only page; it detects a warning condition, which is a
write into the lowest 128 bytes of a page with the DIRW flag
set; or no entry matches the logical address (a page fault).
The following seven flags are contained by the Violation
Type register (VTR):

Read-Only Violation (RDV). This flag is set when the
VMPU attempts 110 access a read-only page and the RIW
line is Low.

System Violation (SYSV). This flag is set when the VMPU
accesses a system-only page and the N/S line is High.
Execute-Only Violation (EXCV). This flag is set when the
VMPU attempts to access an execute-only page other than
during an instruction fetch cycle.

Page Fault (PGFT). This flag is set when no logical address
field of the valid descriptors In the PMM U matches the upper
12 bits of the logical address.

Primary Write Warning (PWW). This flag is set when an
access is made to the lowest 128 bytes of a page with the
DIRW flag set.

Secondary Write Warning (SWW). This flag is set when the
VMPU writes data into the last 128 bytes of the system stack
and EXCV, SYSV, PGFT, RDV, or PWW is set. With SWW set,
subsequent write warnings for accessing the system stack
do not generate a Trap Request.

Fatal Condition (FATL). This flag is set when any other flag
in the Trap Type register is set and either a violation is
detected or a write warning condition occurs in Normal
mode. FATL is not set during a stack push in System mode
that results in a warning condition. This flag indicates that a
memory access error has occurred in the trap processing
routine. Once set, no Trap Request or Abort Request signals
are generated on subsequent violations. However, as long
as the PMMU is enabled, Suppress signals are generated
on this and subsequent VMPU violations until the FATL flag
is reset.

ABORT, TRAP REQUEST, AND
ACKNOWLEDGE
The PMMU generates a 'four-clock-cycle Abort Request
(ABORT) when it detects an access violation or a page fault.
This signal on the ABORT (pin 33) and WAIT (pin 28) inputs
of the VMPU inserts a five-cycle abort sequence that causes
the VMPU to terminate instruction execution. A Trap
Request is generated when the PMMU detects an access
violation, page fault, or write warning. This signal on the
translation trap line of the VMPU (SAT, pin 14) causes the
VMPU to generate a trap acknowledge after the instruction
abortion (for an access violation or page fault) or after the
execution of the instruction (for a write warning). In the case
of an access violation or page fault, the PMMU also
activates Suppress (SUP), which can be used by the
memory to inhibit memory writes.

enabled PMMUs use the AddresslData (AD) lines to
indicate their status. A PMMU that has generated a Trap
Request outputs a 1 on the AD line associated with the
number in its 10 field; a PMMU that has not generated a trap
request outputs a 0 on its associated AD line. AD lines with
no associated PMMU remain 3-stated. During a trap
acknowledge, a PMMU uses AD line 8 + i if its 10 field is i.

Trap Request remains Low until a trap acknowledge is
received (status = 0100). If a VMPU-generated violation
occurs, Suppress is asserted for that memory reference. (If a
28001 or Z8002 CPU generates the violation, any
subsequent CPU memory reference also causes Suppress
to be asserted until the end of the instruction.) Intervening
DMA accesses are not suppressed, however, unless they
generate a violation. Violations detected during DMA
accesses cause Suppress to be asserted for that access
only; no Trap or Abort Requests are generated during DMA
accesses.

Following the Acknowledge cycle, the VMPU automatically
pushes the program status onto the system stack and loads
another program status from the trap vector at location 20H
in the program status area. The PMMU's trap line is reset
during the trap acknowledge. Suppress is not generated
during the stack push. If the push operation creates a write
warning condition, a Trap Request is generated and
serviced at the end of the context swap. The SWW flag is
also set. Servicing this second Trap Request also creates a
write warning condition, but because the SWW flag is set, no
Trap Request is generated. If a violation or page fault rather
than a write warning occurs during the context swap, the
FATL flag is set rather than the SWW flag. Subsequent
Violations or faults cause Suppress but not Trap Request to
be asserted. Without the SWW and FATL flags, trap
processing routines that generate memory violations or
faults would repeatedly be interrupted and called to process
the trap they created.

Trap Requests to the VM PU are handled' similarly to
interrupts. To service a PMMU trap, the VMPU issues a trap
acknowledge. The acknowledge is usually preceded by a
dummy instruction fetch that is not used by the VMPU (the
PMMU has been designed to ignore this dummy fetch).
During the identifier fetch of the acknowledge cycle, all

The VMPU routine to process a Trap Request should first
check the FATL flag to determine if a fatal system error has
occurred. If not, the SWW flag should be checked to
determine if more memory is required for the system stack.
Finally, the trap itself should be processed and the Trap Type
register reset.

584

MULTIPLE PMMUs
Although only one PMMU should be actively translating
addresses at a given time, PMMU architecture directly
supports various methods for multiple PMMU
configurations. The following four examples illustrate
different ways that PMMUs can be used to implement
memory management systems capable of handling more
than 64 pages.

with translating addresses generated during instruction
fetches (status codes 1100 and 1101) and the other with
addresses generated during data fetches (status codes
1000, 1001, 1010, 1011, and 1111). Chip Enable for each
PMMU is obtained from the status code (i.e., status lines
STo-ST3)'

Example 1. The first approach extends the capability of one

multiple translation tables. Multiple tables reduce the time
required to switch tasks by assigning separate tables to
each task. Multiple translation tables for multitask
environments can use the Master Enable flag to enable the
appropriate PMMUs through software.

PMMU for handling 64 pages to a multiple-PMMU
configuration that manages more than 64 pages. The Chip
Enable line IS used to select a particular PMMU to translate a
page address. For example, if one PMMU is assigned only
pages for logical addresses whose bit number 11 is a 0 and
another PMMU is assigned those whose bit number 11 is a
1, then the state of output line AD11 can be used to select the
appropriate PMMU to translate a logical address.

Example 2. Another way of using Chip Enable separates

Example 3. Several PMMUs can be used to implement

Example 4. A final method uses two translation tables to
separate system from normal memory. The MPT and NMS
flags in the Mode register can be used in conjunction with
the N/S line to select the PMMU that contains the
appropriate table.

program pages from data pages. One PMMU is associated

Example 1. To implement 4096-byte pages, address bit
AD11 is not used in the translation process but is used
directly as the most Significant bit of the address location
within a selected 4096-byte page. This can be achieved by
doing the following: (1) set the AD11 input to be equal to the
logical OR of the ST3 and AD11 output lines of the VM PU, (2)
require that the least significant bit in the logical address field

d

of each descriptor register be set to 1, and (3) use the logical
address bit AD11 output by the VMPU instead of the
physical address A11 output by the PM M U. The AD11 input
must be 1 during address translation but must equal the
AD11 output by the CPU during command cycles to the
PMMU; ST 3 is used to distingUish the two types of
transactions.

Example 2. To implement 1024-byte pages an additional
address bit must be translated. Two PMMUs are used. The
CE Input is driven by ADlO for one PMMU and its
complement, AD10, for the other.

DMA OPERATION
At the start of a DMA cycle, DMASYNC must go Low
whether or not the PMMU is used to translate DMA
addresses, to indicate the beginning of a DMA cycle. When
DMASYNC has been Low for two cycles, the PMMU
assumes that a DMA device has control of the bus. A Low on
DMASYNC inhibits the PMMU from using an indeterminate
segment number on lines SNo-SNs. When the DMA logical
memory address is valid, the DMASYNC line must be High
on a rising edge of the clock and then be Low by the next
falling clock edge. The PMMU then performs its address
translation and access protection functions during the clock
period begun in this DMASYNC pulse. Upon the release of
the bus at the termination of the DMA cycle, the DMASYNC
line must go High. After two clock cycles of DMASYNC
High, the PMMU assumes that the VMPU has control of the
bus and that subsequent memory references are VMPU
accesses. The first memory reference occurs at least two

-..,
iI
iI

CHANGING PAGE SIZE
The PMMU directly supports pages of 2048 bytes in length.
However, the addition of external circuitry enables the
PMMU to support systems with larger or smaller pages. The
following examples illustrate the technique for changing the
supported page size.

ien

cycles after the VMPU regains control of the bus. During
VMPU cycles, DMASYNC should remain High. Refer to the
paragraph "Memory Read and Write" and Figure 8 for
further information.
Direct memory access (DMA) opere.lions can OGGur
between instruction cycles and can be handled through the
PMMU. The PMMU permits DMA in either the System or
Normal mode of operation. For each memory access, the
page attributes are checked, and If a violation is detected,
Suppress is activated. DMA violations generate a Suppress
only on a per-memory-access basis.
The DMA device should note the Suppress signal and
record sufficient informalion to enable the system to recover
from the access violation. Neither a Trap Request nor an
Abort Request is ever generated during a DMA operation,
therefore warning condllions are not signaled.

585

PMMU COMMANDS
The various registers in the PMMU can be read and written
using VMPU Special I/O commands. The machine cycles of
these commands cause the status lines to indicate that a
special input/output operation is in progress. During these
machine cycles, the PMMU enters the command mode. In
this mode, the rising edge of AS indicates that acommand is
present on lines AD a-AD 15 . If this command indicates that
data is to be written into one of the PMM U registers, the data
is read from lines ADa-AD15 while OS is Low. If the
command indicates that data is to be read from one of the
PMMU registers, the data is placed on lines ADa-AD15
while OS is Low.
There are five commands that read or write various fields in
the page descriptor register. The status of the read/write line
indicates whether the command is a read or a write.
The autoincrementing feature of the Descriptor Address
Register (DAR) can be used to block load page descriptors
using the repeat forms of the Special I/O instructions. The
DAR is autoincremented at the end of the field. The
command accessing the entire page descriptor register
references the fields in the order of logical address, physical
address, and attribute; four bytes are written in succession.
Table 1 gives the five commands that are used to write data
into descriptor fields.
Table 1. Descriptor Field Write Commands
Opcode
(Hex)

Instruction

OA

Read/Write Attribute field

OB

Read/Write Descriptor (all fields)

OE

Read/Write Attribute field; Increment DAR

OF

Read/Write Descriptor (all fields), increment DAR

15

Reset all Valid Attribute flags

Table 2 gives the three commands that are used to read and
write the control registers.
Table 2. Control Registers' Read/Write Commands
Opcode
(Hex)

Instruction

00

Read/Write Mode register

01

Read/Write Descriptor Address register

20

Read/Write Descriptor Selector Count register

The status registers are read-only registers, although the
Trap Type Register (TTR) can be reset. Twelve instructions,
shown in Table 3, access these registers.
Table 3. Status Registers' Access Instructions
Opcode
(Hex)

Instruction

02

Read Trap Type register

03

Read Violation Segment Number register

04

Read Violation Offset (high-byte) register

05

Read Bus Status register

06

Read Instruction Segment Number register

07

Read Instruction Offset (high-byte) register

11

Reset Trap Type register

13

Reset SWW flag In VTR

14

Reset FATL flag In VTR

21

Read Violation Offset (low-byte) register

22

Read Read/Write Data Counter register

23

Read Instruction Offset (low-byte) register

USE OF THE PMMU WITH OTHER
Z8000CPUs
The PMMU is designed to operate in conjunction with the
Z8003 VMPU; however, it can also be used with other CPUs
in the Z8000 Family. The following examples suggest simple
system configurations; more sophisticated arrangements
are possible.
The Z8004 VM PU generates nonsegmented 16-bit
addresses only. The PMMU can be used to implement a
paged virtual memory by tying the segment number inputs
of the PMMU to 0 and requiring the most significant seven
bits of the logical address field to be O. Since the Z8004
VMPU lacks a translation trap request input pin, the
nonmaskable (or other interrupt request) pin should be used
instead.
The PMMU extends the physical addressing capability of
the Z8004 without using the segmentation mechanism of
the Z8003. This use is similar to the way in which 16-bit

586

minicomputers extend their addressing capability.
The Z8001 and Z8002 CPUs do not support the instruction
abort mechanism. A page fault for one of these CPUs is, in
general, non-recoverable, since during an interrupt, the
current instruction runs to completion, possibly overwriting
CPU registers. For the non segmented Z8002, this means
that all pages that the CPU can access must be in physical
memory and appropriate information must be in the PMMU
page descriptor registers. For the segmented Z8001, this
means that programs must explicitly request segments
before accessing them and must free segments after use. It
also means that segments are allocated in units of the page
size and that limit protection is performed with this
granularity. Use of the PMMU with the Z8001 and Z8002
CPUs permits a paged allocation of main memory and
extends the physical address capability of the Z8002.

PMMUTIMING
The PMMU translates addresses and checks for access
violations by stepping through sequences of basic clock
cycles corresponding to the cycle structure of the VMPU.
Timing diagrams that show the relative timing relationships
of PMMU signals during the baSIC operations of memory
read/write and PMMU control commands are given in this
section.
Memory Read and Write
Memory read and instruction fetch cycles are identical,
except for the status information on the STo-ST3 inputs.
During a memory read cycle (Figure 8), the 7-blt segment
number is input on SNo-SN6 one clock period before the
address offset; a High on DMASYNC during T3 Indicates
that the segment offset data is valid. The address offsets are
placed on the AD o-AD 15 inputs early in the first clock
period. Valid address offset data is indicated by the rising
edge of AS. Status, mode, and chip enable Information
becomes valid early in the memory access cycle and must
remain stable throughout. The most significant 16 bits of the
address (physical memory location) remain valid until the
end of T3. Abort Request, Trap Request, and Suppress are
asserted in T2 (Figure 9). Abort Request is asserted for four
clock cycles. Trap Request remains Low until trap
acknowledge (status = 0100) is received. Suppress is
asserted during the current machine cycle and terminates
during T3.
PMMU Command Cycle
During the command cycle of the PMMU (Figure 11),
commands are placed on lines ADa-AD15 during T1. The
status lines indicate that a Special I/O instruction is In
progress, and the CS line enables the appropriate PMMU
for that command. Data to be written to a register In the
PMMU must be valid on lines AD a-AD 15 late in T2. Data
read from the PMMU is placed on lines ADa-AD15 late in the
TWA cycle.
Input/Output and Refresh
Input/output and refresh operations are indicated by codes
on status lines STo-ST3' During these operations, the
PMMU refrains from any address translation or protection
checking. Lines Aa-A23 remain 3-stated during these
operations.

Reset
The PMMU can be reset by either hardware or software
mechanisms. A hardware reset occurs on the falling edge of
the Reset signal; a software reset is performed by a VMPU
special I/O command. A hardware reset clears the Mode
register, Trap Type Register, and Descriptor Selection Count
register. If the CS line is Low, the Master Enable flag in the
Mode register is set to 1. All other registers are undefined.
After reset, lines AD o-AD 15 and Aa-A23 are 3-stated. The
SUP and ABORT open-drain outputs are not driven. If the
Master Enable flag is not set during reset, the PMMU does
not respond to subsequent addresses on ItS AD lines. To
enable a PMMU after a hardware reset, a PMMU command
must be used In conjunction with CS
A software reset occurs when the Reset Violation Type
Register command is issued. This command clears the Trap
Type Register and returns the PMMU to its Initial state (as If
no violations or warnings had occurred). Note that the
hardware and software resets have different effects.
Abort, Trap Request, and Acknowledge
The PMMU generates a Trap Request whenever it falls to
find a page entry corresponding to the logical address (that
is, a page fault), detects an access violation, or detects a
write into the lowest 128-byte block of a page with the DIRW
flag set (Figure 12). In the case of an access Violation or
page fault, the PMMU also activates Suppress and Abort
Request. The Suppress Signal IS used by memory to inhibit
memory writes. The Trap Request remains Low until a trap
acknowledge signal (status = 0100) is received. Violations
detected during DMA cycles cause Suppress to be asserted
during that cycle only, but no Trap Request is generated.
When the PMMU issues a Trap Request, it awaits the
indication of a trap acknowledge Subsequent Violations
occurring before the trap acknowledge indication is
received are detected and appropriately processed. During
a Trap Acknowledge cycle, the PMMU drives one of its
Address/Data lines; the selection of the line is a function of
the identification field of the Mode register. After the Trap
Request has been acknowledged by the VMPU, the
Violation Status register should be read by a special I/O
command in order to determine the cause of the trap. The
Trap Type register should be reset s() thal subsequenlliaps
are recorded correctly.

587

CLK

-

TN

T,

T,

T,

I

I

I

I

N/S.
STO-STs

SNo-SNa

SEGMENT NUMBER

\

DON'T CARE

/

AS-A23

DMASYNC

ADDRESS VALID

/

\

ADs-AD15

MEMORY ADDRESS

1>- - -

(

DATA IN

)

/
R/W

/

L

Figure 8. Memory Read Timing

588

2081-009

T,

T,

TWA

TWA

TWA

TWA

AD

ALLOW MORE WAIT STATES
T3
T1

aLJL

eLK

As

fr

5
TWA

---v

,

~

~Y:r:C

'~

TRAP

DEASSERTED
['NTRAPACK

\

»"
os!

\'--------"~/y\~

____----J..Jrf

v

'~
;

'--

Figure 9. Abort and Trap Request Timing

208Hl10

589

CLK

-

TN

T,

T,

T,

I

I

I

I

N/S,

STo-ST3

SEGMENT NUMBER

SNo-SNa

DON'T CARE

/

\

,

Aa-A23

DMASYNC

/

\

ADa-AD,.

R/W

ADDRESS VALID

MEMORY ADDRESS

/
Figure 10. Memory Write Timing

590

DATA OUT

L

CLOCK

-

T,

T,

I

I

TWA

•

T,

•

I

I

CS

STo-STa

Nlii

Ai

ADa-ADlI

INPUT

- D<

- r--------- - - - - - - - - -------- r-------

----

LOW

- r\
-

D<

COMMAND VALID

i

~------

DATA IN

C

Di

RlVi

ADa-ADlI

OUTPUT

-

-J

-

-

=x

\..COMMAND VALID

DATA OUT

Di

r

--"\

RIW

Figure 11. 1/0 Command Timing

2081-012

591

I__--------------ACK~~~~:DGE - - - - - - - - - - - - - -.....1 ~~~J~~

AUTOMATIC WAIT STATES

r~----------~A,----------~,
TWA

TWA

TWA

TWA

TWA

T,

Ts

CLOCK

HIGH

STO-ST3

SEGMENT TRAP ACKNOWLEDGE

ADo-AD15

(

IDENTIFIER

)

'------

Figure 12_ Trap Request and Acknowledge Timing

SIGNAL DESCRIPTIONS
The Z8015 is produced in 54-pin and 58-pin packages; the
functions performed by the device's input and/or output pins
are shown in Figure 13. Pin/signal name assignments are
shown in Figure 14.

AS. Address Strobe (input, active low). The rising edge of
AS indicates that lines ADo-AD15, STo-ST3, R/iN, CE, and
N/S are valid.

CEo Chip Enab/e (input, active low). This line selects a

As-A23. Address Bus (outputs, active High, 3-state). These

PMMU to translate a logical address.

address lines are the 15 most significant bits of the physical
memory location.

ClK. System Clock (input). ClK is a + 5V single-p'hase,

ABOiiT. Abort Request (output, active low, open drain). A
low on this line indicates MMU requests for an instruction
abort. This line is enabled when a page fault or access
violation is detected.
AOo-A01S. Address/Data Bus (inputs/outputs, active High,
3-state). ADo-AD? are used for addresses and inputs only.
They carry the low-order byte in the offset of logical
addresses intended for translation. ADs-AD15 are
multiplexed address and data lines that are used both forthe
eight most significant bits of the logical address and for
commands.

592

time-base input used for both the VMPU and PMMU.
CS. Chip Select (input, active low). This line selects a
PMMU for a control command.
OMASVNC. DMAISegment Number Synchronization
Strobe (input, active High). A low on this line indicates a
DMA access is occurring; a High indicates the segment
number is valid. It must be High during VMPU cycles and
low when SN lines are 3-stated.
OS. Data Strobe (input, active low). This line provides
timing for the data transfer between the PMMU and the
Z8003VMPU.

2081-013

N/S. Normal/System Mode (input, Low = System mode).
N/'S indicates to the PMMU that the VMPU or DMA is in the
Normal or System mode.

REffi. Reset

(input, active Low). A Low on this line resets

thePMMU.

Riw. Read/Write (input, Low = write). R/W indicates
whether the VMPU is reading from or writing to either
memory or the PMMU.
SNo-SN6. Segment Number (inputs, active High). These
lines provide the 7-bit segment number of a logical address.
STo-ST 3. Status (inputs, active High). These lines (Table 4)
specify the status of the associated VMPU.

SliP. Suppress (output, active Low, open-drain). This signal
is asserted during the current bus cycle when a page fault or
any access violation, except write warning, occurs.

TRiP.

Tt-ap Request (output, active Low, open-drain). The
PMMU interrupts the VMPU with a Low on this line when the
PMMU detects a page fault, access violation, or write
warning.

0000
0001
0010
001 1
0100
01 01
01 10
o1 1 1
1000
1 001
1 01 0
1011
1 1 00
110 1
1110
1111

Definition

Internal operation
Memory refresh
I/O reference
Special I/O reference (for example, to a
PMMU)
Translation trap acknowledge
Nonmaskable interrupt acknowledge
Nonvectored interrupt acknowledge
Vectored interrupt acknowledge
Data memory request
Stack memory request
Data memory request (External Processing
Architecture)
Stack memory request (External Processing
Architecture)
Instruction space access
Instruction fetch, first word
External Processing Unit-CPU transfer
Bus lock, data memory request

cs

AD14

OMASYNC

AD13

CE

AS

AD12

TRAP

os

AD10

A"
An

ADt
AD,

A"
A20

AD,
AD,

A19

AD,

A"
A17

NIS
RI'Ii

SUP

NC

ABORT

ST,

RESET

NC

NC

NC

A23

ST,

A22

ST,

A"

ST,

A20

AD,

AD,
AD,

A"

AD,

A"

AD,

A"

A"

AD_

A"
A"

A"

ClK

Vee

GNO

SN,

A"

A17

ACiD

SN,
SN,

A"
A,

A"

AD11

SN,

A,

A"

AD12

SN,
SN,

SUP

ADo

ZaD1S
PMMU

PHYSICAL
ADDRESS

SUPPRESS

SNo
TRAP

ABORT
DMASYNC

RNi

AS

ST,

Os

ST,

N/§"

ST,

CS

STo

CE

.5V

GND

}

STATUS

A"

AD13

A"

AD14

A"

AD15

A"

AD,

A"
GNO

Vee

A_

AD,

AD,

A,

A04

RESERVED

AD,

SN,

AD,

SN,

AD,

SN,

ADo

SN,

SNo

SN,

SN,

REsET

Figure 13. Pin Functions

2081-014,015

ST3-STO

AD15

ADu

ADDRESSI
DATA aus

Table 4. Status Lines

Figure 14a. 64-pin Dual-In-Line (DIP),
Pin AsSignments

593

N

...

==
en

."

••
d

A23
NC

10

80

11

59

NC
NC

A22

12

58

ST,

A"
A20
A19
A18

13

57

ST,

14

56

15

55

53

ADa
AD,
ClK
GND

Vee

16

54

17

Za015
Z·PMMU

A17
A16

52

AD,o

19

51

AD11

A15

20

50

AD12

A14
A13
A12
All
AlO
GND

21

49

AD13

22

48

AD14

23

47

AD15

24

46

AD,

25

45

Vee

26

44

NC

18

H~~~~g~M~~D~~~~~~

",0)

";~Q c.,,~b c.;,~b C:J~~ e:,~":1 C:J~'l-c.,,~"" C:J~~ t;r-Q~ 'lir'Q' ~'" 'tfoQ~ ~b. ~'? 't'Qfo

~--=----"
--:-----

----

-

~

--®

~-

-

MEMORY ACCESS

TRAP
ACKNOWLEDGE

MEMORY ACCESS

-

TRAP
ACKNOWLEDGE

®-I-+

\J.

~.

~

~

\l.

~

~

®- -I

?,

A

:::::::::::::::~~~~ r-----------------------------------------------------------------------

~
,

1~~®f4-;

~

~

596

208H)17

ABSOWTE MAXIMUM RATINGS
Voltages on all pins with respect
to GND ......................... -O.3Vto + 7.0V
Operating Ambient
Temperature ..............See Ordering Information
Storage Temperature .............. - 65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the

operational sections of these specifications IS not implied Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the
Package Information section. Refer to the Literature List for
additional documentation.

STANDARD TEST CONDITIONS
The following dc characteristics apply for the given standard
test conditions unless otherwise noted. All voltages are
referenced to GND. Positive current flows into the
referenced pin.

The type of test circuit used is as follows:
+5V

•

I....

UK

Standard conditions are as follows:

en

+4.75V';;; Vcc';;; +5.25V

I

• GND = OV
• O°C.;;;TA.;;; +70°C

DC CHARACTERISTICS

Symbol

Parameter

VCH
VCl
VIH
Vil
VOH
VOL
III
IOl
IcC

Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vcc Supply Current

2081·018

Min

Max

Unit

Condition

VCC - 0.4
-0.3
2.0
-0.3
2.4

VCC + 0.3
0.45
VCC + 0.3
0.8

V
V
V
V
V
V
IlA
IlA
mA

Driven by External Clock Generator
Driven by External Clock Generator

0.4
±10
±10
300

IOH = - 25OIlA
IOl = +2.0mA
0.4" VIN" + 2.4V
0.4" VIN" + 2.4V

597

ORDERING INFORMATION
Z8015 Z-PMMU, 4.0 MHz
64-pin DIP
68-pin PCC
Z8015 CS
Z8015 VSt
Z8015 CE
Z8015 VEt

Z8015A Z-PMMU,
64-pln DIP
Z8015ACS
Z8015ACE

6.0 MHz
68-pin PCC
Z8015AVSt
Z8015AVEt

Codes
First letter IS for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = O°Cto + 70°C
E = -40°C to +85°C
M*= -55°Cto +125°C

R
= Proto pack
= Low Profile Protopack
T
DIP = Dual-In-Line Package
LCC = Leadless Chip Carrier
PCC = Plastic Chip Carrier (Leaded)
FLOW
8 = 883 Class 8

Example' PS is a plastic DIP, O°C to + 70°C.

t Available soon
* For Military Orders, contact your local Zilog Sales Office for Military Electrical SpeCifications.

598

18000® 18016 I-DTC
Direct Memory Access
Transfer Controller

Zilog

Product
Specification

April 1985

FEATURES
• Memory-to-peripheral transfers up to 2.66M bytes per
second at 4 MHz.
• Memory-to-memory transfers up to 1.33M bytes per
second at 4 MHz.
• Two fully independent, multi-function channels.
• Masked data pattern matching for Search and
Transfer-and-Search operations.
• Funneling option that permits mixing of byte and word
data during transfer operations.

• Can operate in logical address space with Zilog
Memory Management Units, providing an 8M byte
logical addressing range and 16M byte physical addressing range.
• Programmable chaining operation provides automatic
loading of control parameters from memory into each
channel.
• Software- or hardware-controlled Wait state insertion.
• Z-BUSTM daisy-chain interrupt hierarchy and busrequest structure.

GENERAL DESCRIPTION
The Z8016 DMA Transfer Controller (DTG) is a high performance data transfer device designed to match the
power and addressing capability of the Z8000 CPUs. In
addition to providing block data transfer capability between memory and peripherals, each of the two DTC
channels can perform peripheral-to-peripheral and
memory-ta-memory transfers. A special Search mode of
operation compares data read from memory or
peripherals with the contents of a pattern register. A
search can be performed concurrently with transfers or
as an operation in itself.
I n all operations (Search, Transfer, and Transfer-andSearch), the DTC can operate in either Flowthrough or
Flyby transfer mode. In the Flowthrough mode, data is
stored temporarily within the DTC on its way from source
to destination. In this mode transfers can be made between a word-oriented memory and a byte-oriented
.per!pheral through the bidirectional byte/word funneling
option. In Flyby mode, data is transferred in a single step
(from source to destination), thus providing twice the
throughput.
The Z8016 DTC takes full advantage of the Z8000
memory management scheme by interfacing directly to
the Z8010 Memory Management Unit (MMU) or the
Z8015 Paged Memory Management Unit (PMMU). In this
configuration, 8M bytes of logical address range are provided for each CPU address space. Alternatively, the

Z8016 DTC can operate independently of an MMU
directly addressing up to 16M bytes of physical addres~
space.
In addition to providing a hardware WAIT input to accommodate different memory or peripheral speeds, the
Z8016 DTC allows the user to program the automatic insertion of either zero, one, two, or four Wait states for
either source or destination addresses. Alternatively, the
WAIT input pin function can be disabled and these
software-programmed Wait states used exclusively.
The Z8016 DTC minimizes CPU involvement by allowing
each channel to load its control registers from memory
automatically when a DMA operation is complete. By
loading the address of the next block of control
parameters as part of this operation, command chaining
is accomplished. The only action required of the CPU is
to load the address of the control parameter table into
the channel's Chain Address register and then issue a
Start Chain command.
In some DMA applications, data is transferred continuously between the same two locations. To service
these repetitive DMA operations, base registers are provided on each channel to reinitialize the current source
and destination address registers. This re-initialization
eliminates the need for reloading registers from memory
tables.
599

i...
•

5

The Za016 DTC is directly Z-BUS compatible, and
operates within the zaooo daisy-chain vectored-priority
interrupt scheme. The Demand Interleave operation
allows the DTC to surrender the bus to the external
system, or to alternate between internal channels. This
capability allows for parallel operations between dual
channels or between a DTC channel and the CPU.
The DTC can be used to provide a central DMA function

SEGMENT
NUMBER

SNo

ADD

SN1

AD1

SN2

AD2

SNa

AD3

SN4

AD4

SNs

ADS

SNs

ADs
AD7

SN7IMMUSYNC

ADa

STATUS

STo

AD9

ST1

AD10

ST.

Z8018

AD11

ST3

DTC

AD1.

R/iN

AD13

BtW
N/S

AD1S
Cs/wAIT

BAI

DREQ1, DREQ.

BAO

DACK1, DACKa
EOP

AS
58

+5V

GND

The Za016 DTC is packaged in a 4a-pin DIP and uses a
single + 5 V power supply.
The Za016 DTC pin functions and assignments are
shown in Figures 1 and 2, respectively.

ADDRESSI
DATA

AD14

BUSREQ

for the CPU or to provide dispersed DMA operations in
conjunction with a wide variety of zaooo Family
peripheral controllers.

BAI

lEO

BUSREQ

INT

BAO

lEI

+5V

CLK

ADD
AD1

AS
58

AD.

Cs/wAIT

AD3

RtW

AD4

DACK1

ADs

DACK2

ADs

EOP

AD7

DREQ.

ADs

DREQ1

AD9

BtW

AD10

ST3

AD11

ST.

AD1.

ST1

AD13

STo

AD14

NlS

AD1S

SNo

SNs

SN1

INT

SNs

SN7IMMUSYNC

lEI

SN4

GND

lEO

SN3

SN2

CLK

Figure 1. Pin Functions

Figure 2. 48-pln Dual-in-Line Package (DiP),
Pin Assignments

SIGNAL DESCRIPTIONS
ADo-AD15' Address/Data Bus (bidirectional, active
High, 3-state) pins 5-20. These multiplexed Address/Data lines are used for all 110 and memory transactions.

AS. Address Strobe (bidirectional, active Low, 3-state)
pin 44. When the DTC is bus master the rising edge of AS
(while DS is High) indicates that addresses are valid.
When the DTC is not bus master, the address lines are
sampled on the rising edge of AS. There are no timing requirements between AS as an input and the DTC clock,
because the Z-BUS does not use a bused clock. If AS
and DS are simultaneously Low, the DTC will be reset.

600

BAl. Bus Acknowledge In (input, active Low) pin 1.
Signals that the bus has been released for DTC control.
In multiple-DTC configurations, the BAI pin of the
highest-priority DTC is normally connected to the Bus
Acknowledge pin of the CPU. Each lower-priority DTe
has its BAI connected to the BAO of the next higherpriority DTC.
BAO. Bus Acknowledge Out (output, active Low) pin 3. In
a multiple-DMA configuration, this pin signals that no
higher-priority DTC has requested the bus. BAI and BAO
form a daisy chain for multiple-DTC priority resolution.

2129-001,002

BUSREQ. Bus Request (bidirectional, active Low, opendrain) pin 2. BUSREO is used by the DTC to obtain control of the bus from the CPU. Before driving BUSREO ac·
tive, the DTC samples this line to ensure that another request is not already being made by another device.
Since the DTC internally synchronizes the sampled
BUSREO signal, transitions on BUSREO can be asynchronous with respect to the DTC clock.

B/W. Byte/Word (output, 3-state) pin 35. This output indicates the type of data transferred on the Address/Data
(ND) bus. A High on this line indicates a byte (8·bit)
transfer and a Low indicates a word (16-bit) transfer. This
signal is activated when AS goes Low and remains valid
for the duration of the transaction.
ClK. DTC Clock (input) pin 45. The Clock signal controls
internal operations and the rates of data transfer. It is
usually derived from a master system clock or an
associated CPU clock. When the DTC is used with an
MMU, both must be driven from the same clock signal.
While many DTC input signals are asynchronous, transitions for other signals (such as WAIT inputs) must meet
setup and hold requirements relative to the DTC clock.
(See the timing diagrams for details.)
CS/WAIT. Chip Select/Wait (input, active Low) pin 42.
When the DTC is not in control of the system bus, this pin
serves as a Chip Select (CS) input. A CPU or other external device uses CS to activate the DTC for reading and
writing the DTC's internal registers. (CS can be held Low
for multiple transfers to and from the DTC, provided that
AS and DS are enabled for each transfer.) There are no
timing requirements between the CS input and the DTC
clock; the CS input timing requirements are only defined
relative to AS.

When the DTC is in control of the system bus, this pin
serves as the WAIT input. Slow memories and peripheral
devices can use WAIT to extend DS during bus transfers.
Unlike the CS input, transitions on the WAIT input must
meet certain timing requirements relative to the DTC
clock (see the Active State timing diagram for details).
The WAIT function can be disabled using a control bit in
the Master Mode register, in which case this input is
treated as a Chip Select only and is ignored when the
DTC is in control of the system bus.
DACKlo OACK2. DMA Acknowledge (output, active Low)
pins 39 and 40. There is one DMA Acknowledge line
associated with each channel. The DACK lines are programmed In the Channel Mode register to be pulsed,
held active, or held inactive during DMA transfers. During Flyby operations the DACK line is used for two purposes. It selects the peripheral involved in the transfer,
and it provides timing information on when to access the
bus. During flowthrough operations the DACK line can
be programmed to be active or inactive during a DMA
transfer. DACK is not output during chaining operations.

OREQ1. OREQ2' DMA Request (input, active Low) pins
36 and 37. There is a DMA Request line associated with
each channel. These lines can make transitions indepen·
dent of the DTC clock. They are used by external logic to
initiate and control DMA operations performed by the
DTC.
OS. Data Strobe (bidirectional, active Low, 3-state) pin
43. A Low on this signal while AS is High indicates that
the ND bus is being used to transfer data. When the CPU
is bus master and is transferring information to or from
the DTC, DS is a timing input used by the DTC to move
data to or from the ND bus.
EOP. End of Process (bidirectional, active Low, open·
drain, asynchronous) pin 38. This line is output when a
Terminal Count (TC) or Match Condition (MC) termination
occurs (see Termination section). An external source
can terminate a DMA operation in progress by driving
EOP Low. EOP always applies to the active channel; if no
channel is active, EOP is ignored. The Suppress output
of the MMU can be connected to EOP to terminate DMA
accesses that violate the MMU protection settings. To
provide full access protection, an external EOP is accepted even during chaining.

lEI. Interrupt Enable In (input, active High) pin 46. lEI is
used with lEO to form an interrupt daisy chain when
there is more than one interrupt-driven device. A High
lEI indicates that no other higher-priority device has an
interrupt under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active High) pin 48.
lEO is High only if lEI is High and the CPU is not servicing an interrupt from the requesting DTC. lEO is connected to the next lower-priority device's lEI input and
thus inhibits interrupts from lower-priority devices.

INT. Interrupt Request (output, open-drain, active Low)
pin 47. This signal is pulled Low when the DTC requests
an interrupt.

N/S. Normal/System (output, 3·state) pin 30. The N/S
signal is activated when the DTC is bus master. The N/S
signal indicates which memory space is being accessed
by going High for normal memory and Low for system
memory.

RIW. Read/Write (bidirectional, 3-state, Low = write) pin
41. When the DTC is not bus master, R/W is a status input used to indicate whether data is being read from
(High) or written to (Low) the DTC. When the DTC is bus
master, R/W is an output used to indicate whether the
DTC is reading or writing the addressed location. During
Flyby DMA operations, the "Flyby peripheral" (Figure 3)
inverts the R/W signal to determine whether it must read
or write.

601

i...
•

5

SNo-SNe. Segment Number (output, 3-state) pins 21-25
and 28-29. In logical address configuration, these lines
provide the segment number field of a 23-bit segmented
address. The SNo-SNe 1/0 address information can be
used to increase the DTC's logical I/O address space
beyond that of the CPU. In physical address configuration, these lines provide bits 23 through 17 of a 24-bit
linear address. The 24th bit (MSB) is output on SN7/MMU
Sync.

SN7 or MMU Sync. Segment Number 7 or MMU Sync
(output, 3-state) pin 27. In a logical address space configuration (with MMU), this line outputs an active High
pulse prior to each machine cycle. The MMU uses this
signal to synchronize access to its translation table and
to differentiate between CPU and DTC control. The MMU
ignores MMUSYNC if the status lines (STo-ST3) indicate

that an 1/0 transaction is being performed. This output is
Low when the DTC is not bus master and the MM1 bit in
the Master Mode register is set.
In a physical address space configuration (without
MMU), this line outputs SN7, which becomes the 24th
address bit in a linear address space. The 24-bit linear
address configuration allows the DTC to access 16M
bytes of memory. This pin floats to the high impedance
state when the DTC is not bus master and the MM1 bit is
cleared.

STo-ST3. Status (bidirectional, 3-state) pins 31-34.
When the DTC is bus master, these lines are outputs indicating the type of memory or 1/0 transaction being performed. When the DTC is not bus master, the status lines
are inputs used to detect Interrupt and Segment Trap
Acknowledge cycles (Table 1).

Table 1. Status Codes

ST1

STo

Transaction/Operation

0
0

0

0

o
o

1
1

0

0
0

0

Internal Operation
Memory Refresh
1/0 Transaction
Special 1/0 Transaction
Segment Trap Acknowledge
Nonmaskable Interrupt Acknowledge
Nonvectored Interrupt Acknowledge
Vectored Interrupt Acknowledge
Memory Transaction for DatalDTC Chaining
Memory Transaction for Stack
Reserved
Reserved
Memory Transaction for Program Fetch (Subsequent Word)
Memory Transaction for Program Fetch (First Word)
Reserved
Reserved

STa

o
o
o
o
o
o
o
o

0

1
1

0
1

1

1

o
o
o
o

0
0

0
0

1

1

0
0

0
0

Status Code
Generated/Decoded

Generated
Generated
Decoded
Decoded
Decoded
Decoded
Generated
Generated

Generated

FUNCTIONAL DESCRIPTION
Channel Initialization
The Z8016 DTC operates with a minimum of interaction
with the host CPU. Each channel's operation is determined by the settings of its own set of control registers.
Each channel is initialized when the DTC loads its control parameters from memory into its control registers
during the chaining operation. To initiate the chaining
operation, the CPU is required to program the Master
Mode register and each channel's Chain Address
register. Then each channel's control registers are
automatically loaded by the DTC with control
parameters stored in a chain control table in memory,
located at the address pointed to by that channel's Chain
Address register. Once the channel registers are loaded,
the DTC is ready to perform DMA operations.

602

Initiating DMA Operations. DMA operations can be
initiated in three ways:
• Software Request. The CPU can issue Software Request commands to start DMA operations on a
specific channel. This channel must then request control of the bus and perform transfers.
• Hardware Request. DMA operations can be started by
forcing a channel's DREQ input Low, as described in
the Transfer Modes section.
• Starting After Chaining. If the Software Request bit of
the Channel Mode register is loaded with a 1 during
chaining, the channel will perform the programmed
DMA operation at the end of chaining. If the channel is

programmed for Single Operation or Demand mode, it
will perform the operation immediately. The channel
will give up the bus after chaining and before the
operation if the CPU Interleave bit in the Master Mode
register is set. Note that once a channel starts a
chaining operation by fetching a reload word, it reo
tains bus control at least until all of the registers
specified in the reload word have been loaded from
memory.
Transfers

The Z8016 DTC uses three basic types of operation:
Transfer, Search, and Transfer·and·Search.
During a Transfer operation, the DTC obtains control of
the system ND bus from the CPU. Data is read from one
addressable port (source) and is written to another ad·
dressable port (destination) in words or bytes. This ap·
plies to both Flyby and Flowthrough transfers.

Flowthrough transfers are used for all combinations of
addressable memory and I/O spaces. These transfers
use independent double Addressing/Transfer cycles, in
which data is stored temporarily in the DTC while being
transferred from source to destination (Figure 4).
Flowthrough transfers can use the funneling option,
which allows mixing of data sizes between source and
destination. For example, a byte·oriented peripheral can
conveniently supply data to a word· oriented memory.
This option requires no added circuitry for either
memory or peripherals.

Z8016

1/0 OR
MEMORY

..e.

Flyby transfers use a single addressing/transfer cycle, in
which data IS transferred directly from the source to the
destination with no intermediate storage (Figure 3). This
method of transfer provides higher throughput than
Flowthrough transfers but cannot be used for memory·
to· memory transfer.

DACK

DTC

~

JIf.

::...
DATA-

"""-7

""=

i

FLYBY
PERIPHERAL
(e.g., FlO)

JIf."j::...

MEMORY
ADDRESS-

..7

,...

""=

Figure 3. Configuration of a Flyby Transaction

Z8016
DTC

PERIPHERAL
OR
MEMORY

I

TEMPORARY
REGISTER

...

~":....

';I"

"""
1

I

PERIPHERAL
OR
MEMORY

j:>..

......... ~

"""....7

""".7
2

} . , , , ' " BUS

I

Figure 4. Configuration of a Flowthrough Transaction

)

2129'003.004

I...
•

603

During a Search operation, data is read from the source
port and compared byte-by-byte with a pattern register
containing a programmable match byte. The Search
operation can be programmed to stop either when the
read data matches (Stop-on-Match) or when it fails to
match the masked pattern (Stop-on-No-Match). For
word reads, the Channel Mode register can be used to
select either 8- or 16-bit compares.
Transfer-and-Search operations combine the transfer
and search functions to facilitate the transfer of variablelength data blocks. While data is being transferred between two ports, a simultaneous search is made for a
bit-maskable byte match. Transfer-and-Search can be
performed in either Flowthrough or Flyby mode. A Flyby
Transfer-and-Search can be used to increase
throughput for transfers between peripherals or between
memory and a peripheral; it cannot be used for memoryto-memory transfers.

Transfer Modes_ The Z8016 DTC operates in either of
two transfer modes: Single or Demand. The Demand
mode is further divided into the Demand Dedicated with
Bus Hold, Demand Dedicated with Bus Release, and Demand Interleave modes.
The Single mode is used with peripherals that transfer
single bytes or words at irregular intervals. Each Software Request command causes the channel to perform
a single DMA operation and each application of a Highto-Low transition on the DREQ Input also initiates a DMA
operation. Each time a Single mode DMA operation
ends, the channel relinquishes the bus unless a new
transition has occurred on DREQ.
In the Demand mode, when the DREQ input is active,
transfer cycles are executed repeatedly until the
transfer is completed. In the Demand Dedicated with
Bus Hold mode, the active channel retains control of the
bus until the transfer is complete, even after the DREQ
input has gone inactive. In the Demand Dedicated with
Bus Release mode, the active channel releases control
of the bus when the DREQ input goes inactive. When the
DREQ input becomes active again, control of the bus is
re-acquired and the transfer operation continues.
The Demand Interleave mode has two options, programmable in the Master Mode register bit MM2. If MM2 is
set, the DTC relinquishes and re-requests bus control
after every DMA operation.
This permits the CPU and other devices to gain bus control. If both channels receive active DREQ inputs, each

604

channel relinquishes control to the CPU after each
operation. In the second option (MM2 is 0), control can
pass from one channel to the other without requiring the
DTC to release bus control. If both channels receive active DREQ inputs, control alternates between channels
and the DTC retains bus control until all channel operations are complete.

Wait States_ The Z8016 DTC can insert Wait cycles into the DMA Transaction cycle under hardware or software control. The CSIWAIT input can be multiplexed to
function as a Chip Select for the DTC when it does not
have control of the bus, and as a WAIT input when the
DTC is the bus controller. Multiplexing CS and WAIT requires external logic, but the DTC can be programmed to
insert Wait states automatically without external logic
when accessing either 1/0 or memory addresses. Either
zero, one, two, or four Wait states can be added. Wait
states can be programmed separately for the Current
Address registers and for the Chain Address register.
Programmable Wait cycle insertion allows memories
and peripherals of different speeds to be associated with
1/0 and memory addresses.

Interrupts. On the Z8016 DTC, each channel is an interrupt source and has its own vector register for identifying the source of the interrupt during a CPU/DTC Interrupt Acknowledge transaction. An interrupt can result
from a Match Condition (MG), End-Of-Process (EOP), or
Terminal Count (TC) on either channel. The user selects
the action to be performed by setting bits in the Channel
Mode register.
Three bits in each channel's Status register control interrupts. These are the Channel Interrupt Enable (CIE) bit,
the Interrupt Pending (IP) bit, and the Interrupt Under
Service (IUS) bit.
Devices connected to any of the CPU's three interrupt
inputs resolve priority conflicts with an interrupt daisy
chain, as shown in Figure 5. The daisy chain has two
functions. During an Interrupt Acknowledge transaction,
it determines which interrupt source is being
acknowledged. At all other times, it determines which interrupt sources can initiate an interrupt request.
The Z8016 DTC has an interrupt queuing capability,
which includes a two-deep interrupt queue on each
channel. This allows the DTC to continue normal operation between the time an interrupt is issued and the time
the Interrupt Acknowledge is received.

+SV

VI
NVI
NMI

CPU

TV

INT
lEI

INT

INT
lEO

lEO

lEI

lEI

lEO

TO LOWER
DEVICES

STO-ST3

I

DTC

t..

r-

.~
DECODE

PERIPHERAL

PERIPH.RAL

INTACK

~

STo
ST3

I...
•

i1iACK
~

NVIACK

i

f>"'- N11ifiACi<

Figure 5. Interrupt Daisy Chain

Termination
DMA operations can end in one of the following three
ways:
• A Terminal Count (TC) termination occurs when a
channel's Current Operation Count register goes to O.

• An End·of·Process (EOP) termination occurs when
the DTC'S EOP pin is driven Low by external logic.
• A Match Condition (MC) termination occurs when data
being Searched or Transferred·and·Searched meets
the match condition programmed In the Channel
Mode register.

MEMORY MANAGEMENT
The DTC can be configured to operate In physical ad·
dress space or logical address space. When the DTC is
operated in logical address space, the segment and off·
set portions of the address registers combine to form
23-blt logical addresses. In conjunction with a CPU, DMA
operations can be handled through the Za010 MMU or
the Za015 PMMU. MMUs offer dynamic segment reloca·
tion, segment protection, and other memory manage·
ment features.

2129·005

In the physical address space configuration, the seg·
ment and offset portions of the DTC's address registers
are combined with the SN7 output to form a single 24-bit
linear address. The extended I/O addressing capability
of the DTC can be used to increase the DTC's physical
1/0 address space beyond that of the CPU. Figure 6 iI·
lustrates various DTC configuration options with the
CPUs and MMUs.

zaooo

605

DTC WITH Z800113 (SEGMENTED) CPU

Z8018

Z800113
CPU

DTC

1-16-1

I

OFFSET

I

DTC WITH Z800214 (NONSEGMENTED) CPU

Z8018

Z800214
CPU

DTC

1-16-1

I

OFFSET

I

DTC WITH Z800113 (SEGMENTED) CPU AND MMU

Z8001l3

Z8018

CPU

DTC

II SEG I
1-16-1
OFFSET

1j.·---24'---·~1

LINEAR ADDRESS

Figure 6. DTC Configurations

606

2129-006

INTERNAL STRUCTURE
The internal structure of the Z8016 DTC includes driver
and receiver circuitry for interfacing with Zilog's Z-BUS.
The DTC's internal bus interfaces with the Z-BUS and

services all internal logic and registers, as illustrated in
the DTC block diagram (Figure 7).

EXTERNAL BUS

CHANNEL 1
REGISTERS

CHANNEL 2

REGISTERS

INTERNAL BUS

MASTER MODE

I...
•

COMMAND

CHAIN
CONTROL

CONTROL
LOGIC

i

INTERFACE
TO
PERIPHERALS

TEMPORARY

Figure 7. Dle Block Diagram

REGISTER DESCRIPTION
The DTC contains chip· level control reg'isters as well as
channel· level registers that are duplicated for each
channel. Registers on the DTC that can be read by the
CPU are either fast- or slow· readable. CPU 1/0 instructions can read fast· readable registers without Wait
states. Slow-readable registers can be read by the CPU
only if Wait states are inserted. This requires external
logic to generate and time the application of Low signals
on the CPUs WAIT input if the slow-readable registers
are to be read.

Logical/Physical Address Space (LPA). The setting of
this bit determines how the system will view the segment
and offset portions of the Current ARA and ARB
registers. When LPA is set to 1 (Logical Address Space),
the segment and offset portions of the Current ARA and
ARB registers are treated as separate portions of the ad·
dress. The 16·bit offset portion of the address will appear on pins ADo-AD15 when AS is Low. The 7·bit segment number appears on pins SNo-SNs for the duration
of the transaction.

Master Mode Register. This register selects the way in
which the DTC interfaces to the system. The following
descriptions indicate how the individual bits in the
Master Mode register are used. The Master Mode
register is fast· readable.

When this bit is set to 0 (Physical Address Space), the
segment and offset portions of the Current ARA and ARB
registers are treated as a single address and all eight
segment bits in the register are used. Both the 1/0 and
the memory addresses in Physical Memory Space are
generated by loading the offset portion of the Current Address register onto the ADo-AD15 bus and the segment
portion of that register onto the SNo-SN7 bus. (I n con·
junction with the nonsegmented Z8000 CPUs, either
Logical or Physical Address Space setting may be used.)

Chip Enable (CE). The setting of this bit enables the DTC
to request the bus, perform DMA operations and reload
registers.

Wait Line Enable (WLE). This bit is set to enable sampling of the CS/WAIT line during memory and 110
transactions.

Control Registers
The four control registers direct the functioning of the
DTC. (Figure 8.)

2129·007

607

Disable Lower Chain (OLC). This bit is set to inhibit all
lower priority devices on the interrupt daisy chain. While
OLe is 0, the OTC generates Low and High signals on the
lEO output in response to lEI.
No Vector on Interrupt (NVI). This bit determines
whether the OTC channel or a peripheral returns a vector during Interrupt Acknowledge cycles. While the bit is

cleared, a channel receiving an Interrupt Acknowledge
will drive the contents of its Interrupt Save register onto
the NO bus while OS is Low. While this bit is set, interrupts are serviced in an identical manner, but the A/O
bus remains in a high impedance state throughout the
Acknowledge cycle.

COMMAND REGISTER

MASTER MODE REGISTER

-.---r-

~

L CHANNEL 2/CHANNEL 1

~~

CHIP ENABLE

L...=

LOGICAL/PHYSICAL
ADDRESS SPACE
CPU INTERLEAVE
ENABLE

INTERRUPT UNDER SERVICE
INTERRUPT ENABLE

WAIT LINE ENABLE
DISABLE LOWER CHAIN
NO VECTOR ON INTERRUPT
I..

~~
~~
~~
1

1

'-~

0

0

0

RESET

0

0

1

INTERRUPT CONTR OL

0

1

0

SOFTWARE REQUEST

0

1

1

FLIP BIT

NVI ACKNOWLEDGE

1

0

0

HARDWARE MASK

Vi ACKNOWLEDGE

1

0

1

START CHAIN

I..

NMI ACKNOWLEDGE
SEGMENT TRAP
ACKNOWLEDGE

SET/CLEAR
INTERRUPT PENDING

1

1

0

NOT RECOGNIZED

1

1

1

NOT RECOGNIZED

CHAIN CONTROL REGISTER
(CHAIN LOADABLE ONLy)
(WRITE ONLy)

I091 Dal 071 061 Os I041 031 02 I01 IDo I

[II~
I L '""..,"'''. WO,""

CHANNEL MODE (2 WORDS)
INTERRUPT VECTOR (1 WORD)
PATTERN AND MASK (2 WORDS)
BASE OP·COUNT (1 WORD)

' - - - - - - - - - BASE ARB (2 WORDS)
L-_ _ _ _ _ _ _ _ BASE ARA (2 WORDS)
L-_ _ _ _ _ _ _ _ _ _ CURRENT OP·COUNT (1 WORD)
L-_ _ _ _ _ _ _ _ _ _ _ CURRENT ARB (2 WORDS)

L-_ _ _ _ _ _ _ _ _ _ _ _ CURRENT ARA (2 WORDS)

TEMPORARY REGISTER

Figure 8. Control Registers

608

2129-008

Interrupt Acknowledge Field (two bits). This field is used
to select the type of Interrupt Acknowledge cycle the
OTC is to respond to. The setting of this field must correspond to the IEIIIEO daisy chain on which the OTC is
located. The OTC can respond to Nonmaskable Interrupt
(NMI), Nonvectored Interrupt (NVI), or Segment Trap
Acknowledge cycles.
CPU Interleave Enable. When this bit is set, interleaving
of bus use between the CPU and the OTC is enabled.

Chain Control Register. This 16-bit register specifies
which registers are to be loaded from memory during a
chaining operation. The Chain Control register is loaded
from the memory location pointed to by the Chain Address register. The Chain Control register is chain
loadable only and cannot be accessed by the CPU.
Command Register. The Command register is an 8-bit
write-only register written to by the host CPU to execute
commands. The Command register Is loaded from the
data on AOrAOo; the data on A01s-AOa is disregarded.
Temporary Register. This 16-bit register is used to
hold data during Flowthrough transfers, Search operations, and Transfer-and-Search operations. The Temporary register cannot be written or read by the CPU.

Channel·Level Registers
Each of the OTC's two channels has a complete set of
channel-level registers. This set consists of both
General-Purpose and Special-Purpose registers, as illustrated in Figure 9. The General-Purpose registers are
commonly found on OMA devices and can be read or
written by the CPU. The Special-Purpose registers provide additional features specific to the Z8016 OTC.

General·Purpose Registers. The General-Purpose
register set on each channel consists of the Current Address registers A and B, the Base Address registers A
and B, the Base and Current Operation Count registers,
and the Channel Mode register (Figure 10).
CUllent and Base Address Registers A and B. The
Current Address registers A and B are used to point to
the source and destination lor OMA operations. The contents 01 the Base Address registers A and Bare translerred into the Cu rrent Address registers A and B at the end
of a OMA operation if the user enables base-lo-current
reloading in the Completion field of the Channel Mode
register. The base-to-current reload operation facilitates
repetitive OMA operations without the multiple memory
accesses required by chaining.
Each of the Base and Current Address registers A and B
consist of two words. The first word contains a 7 -bit Tag
field and an 8-bit Segment Number field. The second
word contains a 16-bit offset. The use of the Tag field is

described below. The use of the Segment Number field
depends upon the setting of the LPA bit in the Master
Mode register. The Base and Current Address registers
are fast-readable and can be loaded by chaining.
Programmable Wait Field. This field allows the insertion
of zero, one, two, or four Wait states into memory or 1/0
accesses addressed by the offset and segment fields.
Address Control Field. At the end of each iteration of a
OMA operation, the address can be incremented,
decremented, or left unchanged. Memory addresses are
changed by one if the address points to a byte operand
or by two if the address points to a word operand.
Address Reference Field. This portion of the Tag field is
used to select whether the address pertains to memory
space or 1/0 space. The N/S output line is always Low
(indicating System) lor 1/0 space but can be either High
(Normal) or Low (System) for memory space.

CUllent and Base Operation Count Registers. The
16-bit Current Operation Count register specifies the
number of words or bytes to be transferred, searched, or
translerred-and-searched. For word-to-word operations
and byte-word funneling, this register must be programmed with the number of words to be transferred or
searched.
The Base Operation Count register reinitializes the current source and destination in the Current Operation
Count register. Each time data is transferred or searched, the Current Operation Count register is decremented
by one. Once all of the data is transferred or searched,
the Current Operation Count register will contain zero. If
the transfer on search stops belore the Current Operation Count register reaches zero, the contents of the
register indicate the number of bytes or words remaining
to be transferred or searched. This allows a channel to
be restarted from where it lelt off without requiring
reloading of the Current Operation Count register. The
Current and Base Operation Count registers are slowreadable and can be loaded by chaining.
Channel Mode Register. This register selects the type
of OMA operation the channel is to perform, how the
operation is to be executed, and what action is to be
taken when the operation finishes. The Channel Mode
register is slow-readable and can be loaded by chaining.
Data Operation and Transfer Type Field. These fields
are used to select the type of operation the channel is to
perform along with the operand size. The specific codes
are listed in Tables 2 and 3. The Flip bit is used to select
which of the Current Address Registers A (ARA), or B
(ARB), points to the source and which points to the
destination address.

609

I...
•

i

DTCINTERNAL
BUS

CURRENT
ADDRESS REGISTER A

CURRENT OPERATION
COUNT REGISTER

BASE
ADDRESS REGISTER A

BASE OPERATION
COUNT REGISTER

CURRENT
ADDRESS REGISTER B

CHANNEL MODE
REGISTER

BASE
ADDRESS REGISTER B

GENERAL.PURPOSE CHANNEL REGISTERS

DTCINTERNAL
BUS

SPECIAL·PURPOSE CHANNEL REGISTERS

Figure 9. Channel·Level Reglstera

610

2129·009

BASE AND CURRENT ADDRESS
REGISTERS A AND B
15

8 7

6

5

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

4

3

2

1

:rA~

SEGMENT

I"
o

1

WAIT STATES

1 WAIT STATE

1 0 2 WAIT STATES
1

0

0

""0 r-;-

-1 I--

1

4 WAIT STATES

INCREMEN T ADDRESS

DECREME NT ADDRESS

X HOLD ADD RESS
-'--

0

0

0

SYSTEM DATA ME MORY

0

0

1

SYSTEM STACK M EMORY

0

1

0

SYSTEM PROGRA M MEMORY

0

1

1

1/0

1

0

0

NORMAL DATA ME MORY

1

0

1

NORMAL STACK MEMORY

1

1

0

NORMALPROGRAM MEMORY

1

1

1

SPECIAL I/O

I...
•

i

OFFSET

BASE AND CURRENT OPERATION COUNT REGISTERS

CHANNEL MODE REGISTER

1041 031 021 0, 1Do I

II I

L

.'''"'O~" "'CO

PULSED DACK

HARDWARE REQUEST MASK
SOFTWARE REQUEST

CHAIN {
ENABLE

;~gJJ~~

EOP

B TO C {
TC
RELOAD
MC
ENABLE
EOP------------~

L-______________

TRANSFER TYPE FIELD

TC

INTERRUPT {
ENABLE

MC------------------~
EOP--------------------~

Figure 10. General·Purpose Channel Registers
2129-010

611

Table 2. Data Operation Field
Operand Size
CodelOperation

ARA

Transaction
Type

ARB

Transfer

0001
100X
0000
0011
0010

Byte
Byte
Word
Byte
Word

Byte
Word
Word
Byte
Word

Flowthrough
Flowthrough
Flowthrough
Flyby
Flyby

Transfer·and·Search

0101
110X
0100
0111
0110

Byte
Byte
Word
Byte
Word

Byte
Word
Word
Byte
Word

Flowthrough
Flowthrough
Flowthrough
Flyby
Flyby

Byte
Word

N/A
N/A

Search

1111
1110

Byte
Word

101X

Illegal

Completion Field. This field is used to program the ac·
tion taken by the channel at the end of a DMA operation.
When a DMA operation ends, the channel can perform
any combination of the following options:
• Interrupt the CPU (Interrupt Enable field)
• Base·to·Current reload (B to C Reload field)
• Chain reload the next DMA operation (Chain Enable
field)
The options are performed according to the bits set in
the Interrupt Enable, B to C Reload, and Chain Enable
fields for each type of termination that occurs; the NAC
bit in the Status register is automatically set on comple·
tion of a DMA operation.
Match Control Field. This 2-bit field determines whether
matches use an 8-bit or 16-bit pattern and whether the
channel is to Stop-On-Match or Stop·On-No-Match. The
specific codes for the Match Control field are listed in
Table 3.
Table 3. Transfer Type Field and Match Control Field
Code

Transfer Type

00
01
10

Single Transfer
Demand Dedicated/Bus Hold
Demand Dedicated/Bus
Release

11

612

Demand Interleave

Match Control

Stop on No Match
Stop on No Match
Stop on Word
Match
Stop on Byte Match

Pulse DACK (PD). This bit determines when the DACK
line is active. While cleared, the channel's DACK line is
active whenever the channel is performing a DMA
operation, regardless of the type of transaction. While
the PD bit is set, the DACK pin is inactive during chaining, Flowthrough Transfers, Flowthrough Transfer-and·
Searches, and Searches. DACK is pulsed active during
Flyby Transfers and Flyby Transfer-and-Searches at the
time necessary to strobe data into, or out of, the Flyby
peripheral.
Hardware Request Mask (HRM). If this bit is set, a DMA
operation can be started by applying a low on the channel's DREQ input.
Software Request (SR). If this bit is set during chaining,
the channel performs the programmed DMA operation at
the end of the chaining operation.

Special

Purpose Registers. The Special-Purpose
registers on each channel are the Pattern and Mask
registers, the Status register, the Interrupt Vector
register, the Interrupt Save registers, and the Chain Address register (Figure 11).

Pattern and Mask Registers. These registers are used
in Search and Transfer-and-Search operations. The Pattern register contains the pattern that the read data is
compared to. The Mask register allows the user to exclude or mask selected Temporary register bits from
comparison by setting the corresponding Mask register
bit to 1. The Pattern and Mask registers are slowreadable and can be loaded by chaining.
Status Register. The Status register on each channel
reports the status of that channel. The functions of the
individual bits are indicated in the following field descriptions. The Status register is fast- readable.

Completion Status Field. Three bits indicate whether the
DMA operation ended as a result of TC, MC, or EOP. The
TC bit is set if the Operation Count (reaching zero) ends
the DMA operation. The MC bit is set if a pattern match
termination occurs. The EOP bit is set when an EOP termination ends a DMA transfer. The appropriate combination of the TC, MC, and EOP bits is set if multiple reasons
exist for ending a DMA operation. The Match Condition
High byte (MCH) and Match Condition low byte (MCl)
bits report the match states of the upper and lower comparator bytes of the last word transferred. The MCH and
MCl bits are updated with each transfer.
These bits are set when the associated comparator
bytes are matched, regardless of whether Stop-onMatch or Stop-on-no-Match is programmed.
Hardware Interface Status Field. The Hardware Request (HRQ) bit provides a means of monitoring the
channel's DREQ input line. While DREQ is low, the HRQ
bit is set. While the Hardware Mask (HM) bit is set, the
DTC is prevented from responding to a low on the DREQ
line. However, the HRQ bit always reports the status of
DREQ regardless of the status of the HM bit.

OTC Status Field. This field reports the current channel
status to the CPU. The "channel initialized and waiting
for request" status is implicitly indicated if bits ST12
through STg are clear.

rupt Acknowledge transaction is in progress. When an
interrupt source has an Interrupt Under Service (IUS
1), all lower priority interrupt sources are prevented
from requesting interrupts.

Second Interrupt Pending (SIP). When a second interrupt is to be issued before the first interrupt is
acknowledged, this bit is set and the channel relinquishes the bus until an Acknowledge occurs.

Interrupt Vector and Interrupt Save Registers. The
8-bit Interrupt Vector register contains the vector or
identifier to be output during an Interrupt Acknowledge
cycle. When an interrupt occurs, the contents of the Interrupt Vector register and bits STg-ST15 of the Status
register are stored in the 16-bit Interrupt Save register.
Because the vector and status are stored, a new vector
can be loaded during chaining and a new DMA operation
can be performed before an Interrupt Acknowledge cycle occurs. If another interrupt occurs on the channel
before the first is acknowledged, further channel activity
is suspended. When a clear IP command is issued, the
status and vector for the second interrupt are loaded into
the Interrupt Save register and channel operation
resumes. The DTC can retain only two interrupts for
each channel. The Interrupt Save register is fastreadable.

Waiting for Bus (WFB). This bit is set when the channel
is waiting for bus control to perform a DMA operation.
No Auto-Reload or Chaining (NAC). This bit is set under
the following conditions:

• A channel completes a DMA operation and neither
Base-to-Current reloading nor auto-chaining is enabled.
• A channel is issued an EOP during chaining.
• A Reset is issued to the DTC.
Chaining Abort (CA). This bit is set when a channel is
issued an EOP during chaining or a Reset is issued to the
DTC. The Chain Abort (CA) bit holds the No Auto-Reload
or Chaining (NAC) bit in the set state until the EOP bit is
cleared. The CA bit is cleared when a new Chain Address
Segment and Tag word or Offset word is loaded into the
channel.
Interrupt Status Field. The Channel Interrupt Enable
(CIE), Interrupt Pending (IP), and Interrupt Under Service
(IUS) bits are used to control the way a channel
generates an interrupt. An interrupt source with its IP bit
set makes an interrupt request if all of the following conditions are met: Interrupts are enabled, (CIE bit = 1),
there is no Interrupt Under Service (IUS bit = 0), no
higher priority interrupt is being serviced, and no Inter-

=

Chain Address Register. This register points to the
chain control table in memory containing data to be loaded into the channel's registers. The Chain Address
register consists of two words (Figure 11). The first word
consists of a Segment and Tag field. The second word
contains the 16-bit offset portion of the memory address.
Bit 15 in the Segment field is ignored when the DTC is
configured for logical address space (LPA
1). The Tag
field contains two bits used to designate the number of
Wait states to be inserted during accesses to the Chain
Control table. The Chain Address register is fastreadable and is loadable by chaining.

=

Table 4 provides a list of register addresses.

613

STATUS REGISTER

1015101410131012101110101 Dg I 081 071 Dsl 051 041 0 31 0 21 01 I 00 1

INTERRUPT {
STATUS

DTC
STATUS

~~:

I

I

EOP
TC }
MC

IP

{N~~

COMPLETION
STATUS

MCl
MCH
HRQ} HARDWARE

WFB

INTERFACE

SIP

HM
STATUS
RESERVEO

RESERVED

INTERRUPT SAVE REGISTER

1015101.10131012101110101 osl

II

Dsl Or! Dsl 051 0.1 031 021 011 OoJ

I

I

VECTOR
CHANNEL NUMBER
0= CH1
1 = CH2
TC
EOP
MC
CHAIN ABORTED
MCl
MCH
HAROWARE REQUEST

CHAIN ADDRESS REGISTER
8 7

15 14
SEGMENT

0

0

o WAIT STATES

0

1

1 WAIT STATES

1

0

2 WAIT STATES

1

1

4 WAIT STATES
THIS BIT IS
FOR PHYSICAL
AOORESS ONLY

OFFSET

PATTERN AND MASK REGISTERS

INTERRUPT VECTOR REGISTER

I

INTERRUPT
VECTOR

Figure 11. Special. Purpose Channel Registers

614

2129-{)11

Table 4. Register Address Summary
Address
(A Dr-ADO>
XOlll00X
X010lllX
X010110X

(Hex)
38
2E
2C

Control Registers
Master Mode
Command Channel 1
Command Channel 2

General·Purpose Channel Registers
XOOll01X
XOO0101X
X001100X
XOO0100X
X001001X
XOOOO01X
X001000X
XOOOOOOX
XO 01111 X
XOOOlllX
X001110X
XOOOll0X
X001011X
XOOOOllX
X001010X
XOOO010X
X011001X
XOll000X
X011011X
X011010X

lA
OA
18
08
12
02
10
00
lE
OE
1C
OC
16
06
14
04
32
30
36
34

Current Address Register A·Channel 1, SegmentlTag
Current Address Register A·Channel 1, Offset
Current Address Register A·Channel 2, Segment/Tag
Current Address Register A·Channel 2, Offset
Current Address Register 8·Channel 1, SegmentlTag
Current Address Register B·Channel 1, Offset
Current Address Register B·Channel 2, Segment/Tag
Current Address Register B·Channel 2, Offset
Base Address Register A·Channel 1, SegmentlTag
Base Address Register A·Channel 1, Offset
Base Address Register A·Channel 2, SegmentlTag
Base Address Register A·Channel 2, Offset
Base Address Register B·Channel 1, SegmentlTag
Base Address Register B·Channel 1, Offset
Base Address Register B·Channel 2, Segment/Tag
Base Address Register B·Channel 2, Offset
Current Operation Count Channell
Current Operation Count Channel 2
Base Operation Count Channell
Base OperatIOn Count Channel 2

I....
•

5

Special· Purpose Channel Registers
Xl00101X
Xl00l00X
Xl00111X
Xl00ll0X
XO 10111 X
X010ll0X
X010l01X
X010100X
X101101X
Xl0ll00X
X010011X
X010001X
X010010X
X010000X
Xl 01011 X
Xl0l001X
Xl0l0l0X
Xl0l000X
NOTE: X

4A
48
4E
4C
2E
2C
2A
28
5A
58
26
22
24
20
56
52
54
50

Pattern Channell
Pattern Channel 2
Mask Channel 1
Mask Channel 2
Status Channel 1
Status Channel 2
Interrupt Save Channell
Interrupt Save Channel 2
Interrupt Vector Channell
Interrupt Vector Channel 2
Chain Address, Channel 1 SegmentlTag
Chain Address, Channel 4 Offset
Chain Address, Channel 2 SegmentlTag
Chain Address, Channel 2 Offset
Channel Mode Channel 1 High
Channel Mode Channel 1 Low
Channel Mode Channel 2 High
Channel Mode Channel 2 Low

= Ignored.

615

ADDRESSING
The address generated by the DTC is always a byte address, even though the memory is organized as 16-bit
words. All word-sized data is word-aligned and must be
addressed by even addresses (Ao
0). With byte
transfers, the least significant address bit determines
which half of the ND bus is used for the transfer. An

=

even address specifies the most significant byte
(ADs-AD1S), and an odd address specifies the least
Significant byte (ADo-AD7). This addressing mechanism
applies to memory accesses as well as to 1/0 and
Special 1/0 accesses.

COMMANDS
The Z8016 DTC responds to several commands that give
the CPU direct control over operating parameters. The
commands described below are executed immediately
after being written by the CPU into the DTC's Command
register. A summary of the DTC commands is given in
Table 5.

Software Request

Reset

The SeUClear Hardware Mask command sets or clears
the Hardware Mask bit in the selected channel's Mode
register.

The Reset command forces the DTC into an idle state, in
which it waits for a Start Chain command. The Start
Chain command initiates a chain operation on either
channel.

A channel's Software Request command initiates a
previously programmed transfer. If both channels are
active, Channel 1 has priority.

Set/Clear Hardware Mask

Table 5. OTC Command Summary

Command
Reset
Start Chain Channell
Start Chain Channel 2

OOOX
101X
101X

xxxx
XXXO
XXXI

AO

Clear Software Request Channel 1
Clear Software Request Channel 2
Set Software Request Channel 1
Set Software Request Channel 2

010X
010X
010X
010X

XXOO
XXOI
XX10
XX11

40
41
42

Clear Hardware Mask Channell
Clear Hardware Mask Channel 2
Set Hardware Mask Channel 1
Set Hardware Mask Channel 2

100X
100X
100X
100X

XXOO
XXOI
XX10
XXII

80

Clear CIE, IUS, IP Channell
Clear CIE, IUS, IP Channel 2
Set CIE, IUS, IP Channel 1
Set CIE, IUS, IP Channel 2

001E
001E
001E
001E

SPOO
SPOI
SP10
SP11

Clear Flip Bit Channel 1
Clear Flip Bit Channel 2
Set Flip Bit Channel 1
Set Flip Bit Channel 2

011X
011X
011X
011X

XXOO
XXOI
XX10
XXII

• NOTES: 1.
2
3
4.
S

616

Example
Code
(HEX)

Opcode Bits
7654
3210

=

00

AI

43
81
82

83

60
61

62
63

E
Set to 1 to perform set/clear on CIE, Clear to 0 for no effect on CIE.
5
Set to 1 to perform set/clear on IUS, Clear to 0 for no effect on IUS.
P
Set to 1 to perform set/clear on IP. Clear to 0 for no effect on IP.
X = "don't care" bit ThiS bit IS not decoded and may be 0 or 1.
Flip bit = reset to 0 for ARA = src, ARB = dst Set to 1 for ARA = dst,
ARB = src.

=
=

Set/Clear IP, IUS, and CIE

Set/Clear Flip Bit

The Set/Clear IP, IUS, and CIE commands manipulate
the Interrupt Control bits located in each channel's
Status register. These bits implement the interrupt daisychain control. The IP, IUS, and CIE bits for each channel
can be set and cleared individually or in combination.

The Set/Clear Flip Bit command reverses the source and
destination, thereby reversing the direction of data
transfer without reprogramming the channel.

TIMING
The following descriptions and timing diagrams refer to
the relative timing relationships of DTC signals during
basic operations. For exact timing information, refer to
the composite timing diagrams.

Bus Request And Acknowledge
Before the DTC can perform a DMA operation, it must
gain control of the system bus. The BUSREO, BAI, and
BAO interface pins provide connections between the
DTC and the host CPU and other DMA devices to arbitrate which device has control of the system bus.
When the DTC wants to gain bus control, it drives
BUSREO Low. Bus Request and Acknowledge timing is
shown in Figure 12.

Flowthrough Transactions
Timing for Flowthrough 1/0 and Flowthrough Memory
transactions (Figures 13 and 14, respectively) is identical. There are two types of 1/0 space on the Z8016: I/O
and Special 1/0. Status lines STo-ST3 specify when an
1/0 operation is being performed and which of the two
1/0 spaces is being accessed. During an 1/0 transaction,

status signal N/S will be Low to indicate a System Level
operation.
The timing for 1/0 operations is identical to the timing of
Flowthrough memory transactions. An 1/0 cycle consists
of three states: T1, T2, and T3. The TWA state is a Wait
state that can be inserted into the transaction cycle. The
AS output is pulsed Low to mark the beginning of a
T-cycle. The N/S line is set Low (System) and the R/W
and B/W lines select Read or Write operations for bytes
or words. The N/S, R/W and B/W lines become stable
during T1 and remain stable until the end of T3.
1/0 address space is byte-addressed but both 8- and
16-bit data sizes are supported. During 1/0 transactions,
the B/W output is High for byte transactions and Low for
word transactions.

The R/W output is High during Read operations and Low
during Write operations. DS is driven Low to signal the
peripherals that data can be gated onto, or received
from, the bus. DS is driven High to signal the end of the
1/0 transaction.

CLOCK

DREQ~

~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~H~_ _-J/r--~:'~'-----

~------------~h~------~f~

f\\

BAI

os: R/W

I

CPU

B/W,N'S:
(SNo-SNs)*

ADo~AD16 {

CPu

(SNo-SNll * *

MMUSYNC·

//

~.•

BUSREQ

STo-ST" All

:

L

_DTC__-,~' >--------------~r------+iLJr----~-~--~~------~-,l
DS,R/W,.
r~
B/W,Nis
CPU
;
OTe
I)---~~
1\-----1' 1\--1'1-----+-1

(SNo-SN,I' ----------~)

~~~--s~~~ ~

_____________~),~
J;-I
CPU

-®

~~-------L~
Ole
.,.-

7

'I

MMUSYNC*

----------~~~/~--------7;

®--

f - - ~"'®r

__-o_______
,

,~·------------~)~r~---------

* For logical addressmg only

*'For phYSical addressing only
Note 1 The DTC will begin drIVing the bus on the clock cycle following the clock cycle

626

In

,which the set-up parameters are met.

2129-021,022

AC CHARACTERISTICSt
Timing for OTC as Bus Slave and CPU-OTC Bus Exchange

4MHz
Max

Min

6MHz
Max

Number

Symbol

Parameters

64

TwDRQ

DREQ Pulse Width (Single Transfer Mode)

20

20

65

TsDRQ(C)

DREQ Valid to Clock t Setup Time

60

50

66

ThDRQ(C)

Clock t to DREQ Valid Hold Time

20

67

TdC(BRQf)

Clock t to BUSREQ • Delay

150

120

68

TdC(BRQr)

Clock. to BUSREQ t Delay

165

150

69

TdBRQ(BUSc)

BUSREQ t to Control Bus Float Delay

140

110

70

TdBRQ(BUSd)

BUSREQ t to AD Bus Float Delay

140

110

71

TdDSA(RDV)

OS. (Acknowledge) to Data Output Valid Delay

135

120

72

TdDSA(RDZ)

OS t (Acknowledge) to Data Output Float Delay

80

75

73

TdDSR(DOD)

OS. (lOR) to Data Output Driven Delay

135

120

74

TdDSR(RDZ)

OS t (lOR) to Data Output Float Delay

75

TwAS

AS Low Width

70

50

76

TsA(AS)

Address Valid to AS t Setup Time

30

10

77

ThAS(Av)

AS t to Address Valid Hold Time

50

40

78

TdAS(DS)

AS t to OS • Delay (1/0)

50

40

79

TsCS(AS)

CS Valid to AS t Setup Time

80

ThCS(AS)

AS t to CS Valid Hold Time

Min

20

80

75

0

0

40

30
3TcC

81

TwAS(DS)

AS and OS Simultaneously Low Time (Reset)

82

TdBAI(Az)

BAI t to SNo-SN7, ADo-AD15 Float Delay (Reset)

3TcC
135

120

83

TdBAI(ST)

BAI t to STo-ST3, R/W, B/W, N/S Float Delay (Reset)

100

80

84

TdBAI(DS)

BAI t to OS,

85

TdDS(Dn)

OS t (lOW) to Data Valid Hold Time

86

TdAC(DRV)

Address Valid to Data (lOR) Required Valid Delay

87

TdAZ(DS)

Address Float to OS • (lOR) Delay

88

TwDS(lO)

OS (10) Low Width

89

TsD(DS)

Data (lOW) Valid to OS t Setup Time

90

TrDS(W)

OS t (lOW) to OS • (lOW) (Write Recovery Time
applies only for Issuing Command)

91

TsBAK(C)

BAI Valid to Clock t Setup Time

92

TdAS(DS)

93
94

AS Float Delay (Reset)

100
40

85
40

540

345

0

0

150'

150

40

40

4TcC

4TcC

60

50

AS t to OS • (ACK) Delay

100

100

TwDS(AK)

OS (ACK) Low Width

150

150

TdBRQ(BAI)

BUSREQ. to BAl. Required Delay

95

TsS(AS)

Status Valid to AS t Setup Time

98

TdBAI(BAO)

BAI t, • to BAa t, • Delay

80

70

99

TdIEI(IEO)

lEI t, • to lEO t, • Delay

80

60

0

0

40

0

NOTES'

'2000 ns for reading slow-readable registers (worst case)
tUnits In nanoseconds (ns).

627

I:0

...

•.

I

ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This IS a stress rating only,
operation of the device at any condition above those Indicated in the
operational sections of these specifications is not implied Exposure to
absolute maximum rating conditions for extended pen ods may affect
device reliability

Voltages on all pins with respect
to GND ......................... -0.3V to + 7.0V
Operating Ambient
Temperature .............. See Ordering Information
Storage Tem peratu re .............. - 65°C to + 150°C

STANDARD TEST CONDITIONS
Package Information section. Refer to the Literature List for
additional documentation.

The DC characteristics and capacitance sections below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND.
Positive current flows into the referenced pin.

+5V
+5V

Standard conditions are as follows:
•

+4.75V~ VCC~ +5.25V
FROM OUTPUT
UNDER TEST

•

GND = OV

•

TA as specified in Ordering Information

~

1

50P

All AC parameters assume a load capacitance of 50 pf max.
The Ordering Information section lists package temperature
ranges and product numbers. Package drawings are in the

Standard Test Load

Parameter

Min

Max

Unit

VCH

Clock Input High Voltage

Vcc-O.4

VCC+ 0.3

V

Driven by External Clock Generator

VCl

Clock Input Low Voltage

-0.3

0.45

V

Driven by External Clock Generator

VIH

Input High Voltage

2.0

VCC+ 0.3

Vil

Input Low Voltage

-0.3

VOH

Output High Voltage

Val

Output Low Voltage

0.8

Condition

V
V
V

IOH = -250 pA

0.4

V

10l

2.4

=

+2.0 mA

III

Input Leakage

±10

pA

0.4 S VIN S VCC

IOl

Output Leakage

±10

pA

0.4 S VIN S + VCC

Icc

VCC Supply Current

350

mA

NOTE: VCC = 5 V ± 5% unless otherwise specified.

CAPACITANCE

Symbol

Parameter

CCLOCK

Clock Capacitance

CIN

Input Capacitance

COUT

Output Capacitance

TA = 25°C, f = 1 MHz.
Unmeasured pins returned to ground.

628

Min

!

Open-Drain Test Load

DC CHARACTERISTICS
Symbol

2'2K

Max

Unit

40

pI

5

pI

10

pI

ORDERING INFORMATION
ZS016 Z-OTC, 4.0 MHz
4S-pin DIP

ZS016A Z-OTC, 6.0 MHz
4S-pin DIP

Z8016 PS
Z8016CS
Z8016 PE
Z8016CE

Z8016A PS
Z8016A CS
Z8016A PE
Z8016A CE

Codes
First letter is for package; second letter is for temperature.
C
P
L
V

= Ceramic DIP
= Plastic DIP
= Ceramic LCC
= Plastic PCC

TEMPERATURE
S = °C to + 70 °C
E = -40°Cto +85°C
M*= -55°Cto +125°C

a

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DIP, O°C to + 70°C.

t Available soon.
* For Military Orders. contact your local Zilog Sales Office for Military Electrical Specifications.

00-2129-02

629

Z8030 Z8000®
Z-SCC Serial
Communications Controller

Product
Specification

Zilog

April 1985

Features

synchronous characters and CRC generation and checking with CRC-16 or
CRC-CCITT preset to either Is or Os.

• Two independent, 0 to 1.5M bit/second, fullduplex channels, each with a separate crystal
oscillator, baud rate generator, and Digital
Phase-Locked Loop for clock recovery.

• SDLC/HDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handling, abort
generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.

• Multi-protocol operation under program
control; programmable for NRZ, NRZI, or
FM data encoding.
• Asynchronous mode with five to eight bits
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detection and generation; parity,
overrun, and framing error detection.

• Local Loopback and Auto Echo modes.
• 1.544M bit/second T 1 digital trunk compatible
version available.

• Synchronous mode with internal or external
character synchronization on one or two

General
Description

The Z8030 Z-SCC Serial Communications
Controller is a dual-channel, multi-protocol
data communications peripheral designed for
use with the Zilog Z-Bus. The Z-SCC functions
as a serial-to-parallel, parallel-to-serial converter/controller. The Z-SCC can be softwareconfigured to satisfy a wide variety of serial

t SERIAL

........ ADr

TxDA

........ AD6

RxDA ..-fDATA

~

ADs

"i'Rx'CA

ADDRESSI

......... AD4

RTxCA

DATA BUS

........

SYNCA

ADa

communications applications. The device contains a variety of new, sophisticated internal
functions including on-chip baud rate
generators, Digital Phase-Locked Loops, and
crystal oscillators that dramatically reduce the
need for external logic.

---l CHANNEL
f CLOCKS

CH·A

......... A02

CHANNEL
CON"tftOL$
FOR MODEM,
DMA,OR
OTHER

AD,

AD,
AD,

ADo
AD,

AD,

AD,

AD,

AD,

iNT

os

lEO

i$

lEI

R/Vi

INTACK

OS;;

+5V
W/REQA
SVNCA
RTxCA

RxDA
TRxCA

CHANNEL
CONTROLS
FOR MODEM,

DMA,OR
Z8030

z·scc

GlSa

'4--

DeDB ..---

OTHER

CH·S

TxDA
DTAIREQA
RlSA

cs,
GND
WIAEQB
SYNCS

RTxCB
RxDB
TAxea
TxDB
DTR/REQB

elSA

Alsa

DeDA

else

PCLK

DeDa

t t t

+5

v

GND PClK

Figure I. Pin Functions

2016-001.002

Figure 2. 40-pin Dual-in-Line Package (DiP),
Pin Assignments

631

!
i

General
Description
(Continued)

The Z-SCC handles asynchronous formats,
synchronous byte-oriented protocols such as
IBM Bisync, and Synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data
transfer application (cassette, diskette, tape
drives, etc.).
The device can generate and check CRC
codes in any Synchronous mode and can be
programmed to check data integrity in various
modes. The Z-SCC also has facilities for

~
6

modem controls in both channels. In applications where these controls are not needed,
the modem controls can be used for
general-purpose 1/0.
The Z-Bus daisy-chain interrupt hierarchy
is also supported-as is standard for Zilog
peripheral components.
The Z8030 Z-SCC is packaged in a 40-pin ceramic DIP and 44-pin chip carrier and uses a
single + 5V power supply.

't-()'\'?-Q.. '?-<:/""r-Q... .p<:l>.,.Q"'.".Q.,..pC

..LC_

\~_ _ _ _ _ _ _ _ _ _ _

'C

-J!

CS, _ _ _ _ _

\_____---..J;Figure 13. Write Cycle Timing

Interrupt Acknowledge Cycle Timing.
Figure 14 illustrates Interrupt Acknowledge
cycle timing. The address on ADo-AD7 and
the state of CSo and INTACK are latched by
2016-012, 013

the rising edge of AS. However, if INTACK is
Low, the address and CSo are ignored. The
state of the R/W and CS j are also ignored for
the duration of the Interrupt Acknowledge
645

Timing
(Continued)

intended for the Z-SCC. In this case, the
Z-SCC may be programmed to respond to DS
Low by placing its interrupt vector on
ADo-AD7' It then sets the appropriate
Interrupt-Under-Service latch internally.

cycle. Between the rising edge of AS and the
falling edge of DS, the internal and external
IEI/IEO daisy chains settle. If there is an interrupt pending in the Z-SCC and lEI is High
when DS falls, the Acknowledge cycle was

Cio

==::x:

(IGNORED)

><==:'1--:- - - - -

r---'f.
~
__-J}---

A~_AD7==::X:~~~G:NO:R~ED~):)~----~'~'~----~~~_V_E_~_OR

,

iii

Figure 14. Interrupt Acbowledge Cycle Timing

Absolute
Maximum
Ratings

Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to +150°C

Stresses greater than those hsted under Absolute Maxi·
mum Ratmgs may cause permanent damage to the devlCe.
This is a stress ratmg only; operallon of the deVIce at any
condition above those mdlCated m the operational sections
of these specifications IS not imphed. Exposure to absolute
maxImum rating condihons for extended periods may affect
device rehabliity.

Standard
Test
Conditions

The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:

• +4.75 V S Vee S +5.25 V
• GND = OV
• TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.

+5V

21K

+5V

FROM OUTPUT
UNDER TEST

~ "'K
150~

Figure IS. Standard Test Load

DC
Characteristics

Capacitance

Symbol

VIH
VIL
VOH
VOL
IlL
IoL
Ice
Vee = 5 V
Symbol

CIN
CoUT
CliO

±

Figure 16. Open·DralD Tut Load

Parameter

Min

Max

Unit

Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current

2.0
-0.3
2.4

Vee+ 0.3
0.8

V
V
V
V
,.A,.ArnA

0.4
±IO.O
±IO.O
250

Condltlon

IoH =
IoL=
0.4 oS
0.4 oS

- 250 ,.A+2.0 mA
VIN oS +2.4V
VOUT oS +2.4V

5% unless otherwise specified, over speclhed temperature range.

Parameter

Input Capacitance
Output Capacitance
Bidirectional Capacitance

Min

Max

Unit

10
15
20

pi
pi
pi

Test Condition

Unmeasured Pins
Returned to Ground

f = 1 MHz, over speclhed temperature range.

646

2016-014 8085·006. 001

Read and
Write
Timing

n
Cio

III..
READ

~

~

~

J(
~

X

){
I------===:)
®-~

®I--

--\-@

E-

I

~

X
® -

::::j-@
I-

r-w.

)(

i

-Ie

.... @

~

r-:::---®
C0
Z4

~

W/A.Q
WAIT

~

W/R.Q

~

REQUEST

DTRIRI:Q

-------®----L

REQUEST

\,
n

No.

Symbol

Parameter

Min

'MHz
Max

1
TwAS
AS Low Width
70
2
TdDS(AS)
DS I to AS I Delay
50
3
TsCSO(AS)
CSc to AS I Setup TIme
0
4
ThCSO(AS)
CSo to AS I Hold Time
60
5-TsCSl(DS) --CS J to DS I Setup T l m e - - - - - - - - - - - 100
6
ThCSl(DS)
CS] to DS IJioid Time
55
7
TsIA(AS)
!NTACK to AS I Setup TIme
0
8
ThIA(AS)
!NTACK to AS I Hold Time
250
9
TsRWR(DS)
R!W (Read) to iSs I Setup Time
100
10-ThRW(DS)--R/Wto DS I Hold Time - - - - - - - - - - 55
11
TsRWW(DS)
R/W (Write) to DS I Setup Time
0
12
TdAS(DS)
AS I to DS I Delay
60
13
TwDSI
DS Low Width
390
14
TrC
Valid Access Recovery Time
6TcPC
+200
15-TsA(AS)---Address to AS I Setup Time - - - - - - - - - 30
16
ThA(AS)
Address to AS I Hold Time
50
17
TsDW(DS)
Write Data to DS I Setup Time
30
18
ThDW(DS)
Write Data to DS I Hold Time
30
19
TdDS(DA)
DS I to Data Active Delay
0
20-TdDSr(DR)--DS I to Read Data Not Valid D e l a y - - - - - - - 0
21
TdDS£(DR)
DS I to Read Data Valid Delay
22
TdAS(DR)
AS I to Read Data Valid Delay
NOTES:
1. Parameter does not apply to Interrupt Acknowledge
transactions.
2016-015

250
520

6MHz
Min
Max

Notes*t

50
25
I
0
40
1
80 - - - - - - 1 40
1
0
250
80
40
0
40
250
6TcPC
2
+ 130
10 - - - - - 1 30
1
20
20
0
0
180
335

2 Pardmeter applIes only between transactions mvolvmg the
*Tlmmgs are prelImmary and subject to change.
tUmts m nanoseconds (ns).

sec.

647

Interrupt

~

AckDowlec1ge
TlmiDg

- - - - - -.....
iii

I+--~"i)__-+I ~;:::=@:=::::rl

A~-AD.------------------+-------------1:-=~~~~~~~~~-------1.1

_~~~

____

~~

__

J~~~

_____

-J~'-

_ _ __

lEO

Reset

~

TlmiDg

iii - - - '

Cycle
TlmiDg

\ ....._ _

-~~/

....11'\

+---+ .,.----

PCLK

4MB.
No.

Symbol

Parameter

Min

Max

23
24
25
26

8MH.
Min
Max

Notes*t

TdDS(DRz)
DS I to Read Data Float Delay
70
45
TdA(DR)
Address Required Valid to Read Data Valid Delay
570
420
240
200
i5S I to Wait Valid Delay
TdDS(W)
240
DS I to WIREQ Not Valid Delay
200
TdDSf(REQ)
5TcPC
Z / - TdDSr(REQ)-DS I to DTRlREQ Not Valid Delay - - - - - - - - 5TcPC
+300
+250
28
TdAS(lNT)
AS I to INT Valid Delay
500
500
29
TdAS(DSA)
AS I to DS I (Acknowledge) Delay
250
250
30
TwDSA
DS (Acknowledge) Low Width
390
250
31
TdDSA(DR)
DS I (Acknowledge) to Read Data Valid Delay
180
250
120
100
32 - TsIEI(DSA) - - lEI to OS I (Acknowledge) Setup Time - - - - 33
ThIEI(DSA)
lEI to DS I (Acknowledge) Hold Time
0
0
34
TdIEI(IEO)
lEI to lEO Delay
120
100
35
TdAS(IEO)
AS I to lEO Delay
250
250
36
TdDSA(INT)
DS I (Acknowledge) to INT Inactive Delay
500
500
37-TdDS(ASQ)--DS I to AS I Delay for No R e s e t - - - - - - - - 30
15
38
TdASQ(DS)
AS I to DS I Delay for No Reset
30
30
250
39
TwRES
AS and DS Coincident Low for Reset
250
40
TwPCI
PCLK Low Width
2000
105
1000
70t
41
TwPCh
PCLK High Width
105
1000
2000
70t
42-TcPC
PCLK Cycle Time - - - - - - - - - - - - 250 -4000--165° - 2000
43
TrPC
PCLK Rise Time
20
15
44
TIPC
PCLK Fall Time
20
10

3
4

4
5

6
4
7

NarES:
3. Float delay IS defined as the bme reqUIred for a ± 0 5 V change In the output With a maximum de load and minimum ae load.
4. Open·dram output, measured WIth opea·dram test load.
5. Parameter IS system dependent For any Z.SCC m the daJsy cbem, TdAS(DSA) must be greater than the sum of TdAS(IEO) for the h,ghest prlOnty device In the daJsy
cham, TslEI(DSA) for the Z·SCC, and TdIEH(lEO) for each devIce separating them In the deury chom.
6. Parameter apphes only to a Z·SCC pulhnq IN! Low at the begmnIng of the Interrupt Acknowledge transactIon.
1. Internal ClICUltry allows for the reset provIded by the Z8 to be recogmzed a. a reset by the Z·SCC .

• TlImnqs are prehnunary and subject to change. All hmmg references assume 2.0 V for a logiC "1" and 0.8 V for a loglc "0".

t Umt. In nanosecond. (n.).
l Parameter equals 64 ns for Z8030A 51441 verSlOD compatible wlth TI operabon.

() Parameter equals 153 os for Z8030A SL441 version compabble with Tl operabon.

648

2016'()16, 017, 018

General
Timing

PCLK

WIRf.Q
REQUESr

WAIT

WIAEQ _______________

-;~~:d--------------------~-------

RTxC, TRxe
RECEIVE _________- : : - : - - ;

I
i

2016-019

649

6 MHz

4 MHz
No.

Symbol

Parameter

Min

Max

I

TdPC(REQ)

PCLK I to W/REQ Vahd

250

2

TdPC(W)

PCLK I to Wait Inactive Delay

350

3

TsRXC(PC)

RxC I to PCLK t Setup Time (PCLK

4 case only)

TwPCL

80
TsRXD(RXCr)
RxD to RxC t Setup Time (XI Mode)
0
4
5-ThRXD(RXCr)-RxD to RxC t Hold Time (XI M o d e ) - - - - - - -150
6

TsRXD(RXCf)

RxD to RxC I Setup Time (XI Mode)

7

ThRXD(RXCf)

RxD to RxC I Hold Time (XI Mode)

8
9

TsSY(RXC)

SYNC to RxC t Setup Time

ThSY(RXC)

SYNC to RxC t Hold Time

Min

Max

Notes*t

250
350
70

TwPCL

1,4

0
150- - - - - - 1 -

0

0

1,5

150

150

1,5

-200

-200

3TcPC
+200
10 -TsTXC(PC)--TxC I to PCLK t Setup T l m e - - - - - - - - -0

3TcPC
+200

I

0- - - - - - 2 , 4 -

II

TdTXCf(TXD)

TxC I to TxD Delay (XI Mode)

300

300

2

12

TdTXCr(TXD)

TxC t to TxD Delay (XI Mode)

300

300

2,5

13

TdTXD(TRX)

TxD to TRxC Delay (Send Clock Echo)

200

200
6

180

180
RTxC High Width
TwRTXh
14
15-TwRTXI---RTxC Low W i d t h - - - - - - - - - - - - -180

180 - - - - - - 6 400

16

TcRTX

RTxC Cycle Time

400

17

TcRTXX

Crystal Oscillator Period

250

18

TwTRXh

TRxC High Width

180

180

6

TRxC Low Width

180

180

6

TRxC Cycle Time

400

400

200

19
TwTRXI
20-TcTRX
21

TwEXT

DCD or CTS Pulse Width

200

22

TwSY

SYNC Pulse WIdth

200

NOTES:
1. RxC IS RTxC or TRxC, whichever

IS supplymg the receive
clock
2. TxC IS TRxC or RTxC, whichever IS supplymg the transmit
clock.
Both RTxC and SYNC have 30 pf capacitors to the ground
connected to them

4. Parameter appires only

If

the data rate

IS

one-fourth the PCLK

rate In all other cases, no phase relationship between RxC and
PCLK or TxC and PCLK

650

IS

required.

1000

6

250

1000

3

------6-

5. Parameter applies only to FM encodmg/decodlng.
6. Parameter apphes only for transmitter and receiver; DPLL and
baud rate generator timmg requirements are Idenhcal to chip
PCLK reqUlrements.
* Tlmmgs are prehmmary and subject to change.

t Umts

In

nanoseconds (ns).

System
Timing

iiTiC. TRxC
RECEIVE

W/AEQ
REQUEST

W/AEQ
WAIT

SYNC
OUTPUT

ATxC. TRxC
TRANSMIT

I

W/REQ
REQUEST

W/AEQ
WAIT

----------r-=~~

i

DTA/AEQ
REQUEST

K
SYNC
INPUT

I--

0 ..

o n
ae:
a CD

c n
C

D_A_TA_ _ _ _ _ _

NW __________~\~____________________;:-~

C

----'I

cs, _ _ _

\~

____----'r_

Figure II. Write Cycle Timing

Interrupt Acknowledge Cycle Timing.
Figure 12 illustrates Interrupt Acknowledge
cycle timing. The address on ADa-AD7 and
the state of CSa and INTACK are latched by
664

the rising edge of AS. However, if INTACK is
Low, the address and CSa are ignored. The
state of the RI'W and CSI are also ignored for
the duration of the Interrupt Acknowledge
2016·012.013

Timing
(Continued)

intended for the Z-ASCC. In this case, the
Z-ASCC may be programmed to respond to
DS Low by placing its interrupt vector on
ADo-AD7. It then sets the appropriate
Interrupt-Under-Service latch internally.

cycle. Between the rising edge of AS and the
falling edge of DS, the internal and external
lEI/lEO daisy chains settle. If there is an interrupt pending in the Z-ASCC and lEI is High
when DS falls, the Acknowledge cycle was

(IGNORED)

iiiTiCi

\

~:.

~~-----------------'
c::::,.
,•

A~AD.::::::J<~(I~GN~O=R~ED~):)~----~.~'l~----~~___V_E_CT_OR__-J}----

•

I...

Figure 12. Interrupt Acknowledge Cycle Timing

Absolute
Maximum
Ratings

Voltages on all pins with respect
toGND ................... -0.3Vto +7.0V
Operating Ambient
Temperature ....... See Ordering Information
Storage Temperature ........ - 65°C to + 150°C

Stresses greater than those hsted under Absolute Maxi·
mum Ralings may cause permanent damage to the device.
Th,s is a stress ratong only; operailon of the deVIce at any
condllion above those Ind,cated In the operailonal secilons
of these speclflcailons IS not Imphed. Exposure to absolute
maxImum railng condlilons for extended periods may affect
deVIce rellablhty.

Standard
Test
Conditions

The DC characteristics and capacitance sections below apply for the followmg standard test
conditions, unless otherwise noted. All voltages
are referenced to GND. Positive current flows
into the referenced pin.
Standard conditions are as follows:

• +4.75 V S Vee S +5.25 V
• GND = OV
• TA as speCified in Ordering Information
All ac parameters assume a load capacitance
of 50 pf max.
+SV

FROM OUTPUT

UNDER TEST

~ "'K
I"~

Figure 13. Standard Test Load

DC

Symbol

Characteristics

Figure 14. Open-Drain Test Load

Parameter

Min

Max

Unit

Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current

2.0
-0.3
2.4

Vee +0.3
0.8

V
V
V
V

0.4
± 10.0

±IO.O

J,!A
J,!A

250

rnA

Condition

IClH = - 250 J,!A
+2.0 rnA
0.4 S VIN S + 2.4V
0.4 S VOUT S +2.4V

IoL =

Vee = 5 V ± 5% unless otherWise speCified, over speCIfied temperature range

Capacitance

Symbol

Parameter

Input Capacitance
Output CapaCitance
Bidlrechonal CapacItance

Min

Max

Unit

10

pf
pf

15
20

Condition

of

f = 1 MH?, over specified temperature range.
Unmeasured. pms returned to ground.

2016·014 8085-006.001

665

Read and
Write
Timing

~
~

~

X

~kD-1

X

-

Alii

-c4. ~

- ®~
/

~

READ

\.

Alii
WAITE

- ®I-

~ -®

jjj

-----®---ADo-AD7
WAITE

ADO-AD7
READ

:=}
@-I:=}

J(

01-

•

0

X

+®-- - ® -

~

-

)i

~

@-I- +®--

11

~

,)!,

~
,,!!,

@ I-

24

wn,.Q

\.

WAIT

~

W/AeQ

~

REQUEST

DTRlREQ
REQUEST

I
2
3
4
56
7
8
9
10 II
12
13
14

Symbol

Parameter

~

/'
~

No.

'i7'

"-Min

4 MHz
Max

6 MHz

Min

Max

Notes*t

TwAS
TdDS(AS)
TsCSO(AS)
ThCSO(AS)
TsCS!(DS) - ThCSI(DS)
TslA(AS)
ThIA(AS)
TsRWR(DS)
ThRW(DS)-TsRWW(DS)
TdAS(DS)
TwDSI
TrC

AS Low Width
70
50
DS I to AS I Delay
50
25
C~ to AS I Setup T,me
0
0
I
CSo to AS I Hold T,me
60
40
I
CS] to DS I Setup T , m e - - - - - - - - - - I O O - - - - - - 80 - - - - - - 1 CS] to DS IJioid T,me
55
40
I
INTACK to AS I Setup Time
0
0
INTACK to AS I Hold Time
250
250
R!W (Read) to DS I Setup T,me
100
80
RIW to DS I Hold T,me
55
40 - - - - - - - R/W (Write) to DS I Setup T,me
0
0
AS I to DS I Delay
60
40
DS Low Wldth
390
250
Valid Access Recovery Time
6TcPC
6TcPC
2
+200
+130
15 - TsA(AS) - - - Address to AS I Setup Time - - - - - - - - - 30
10 - - - - - - 1 16
ThA(AS)
Address to AS I Hold T,me
50
30
I
17
TsDW(DS)
Wnte Data to DS I Setup T,me
30
20
18
ThDW(DS)
Wrlte Data to DS I Hold T,me
30
20
19
TdDS(DA)
DS I to Data Achve Delay
0
0
20-TdDSr(DR)--DS I to Read Data Not Valid Delay
0
0-------21
TdDSf(DR)
DS I to Read Data Vahd Delay
250
180
22
TdAS(DR)
AS I to Read Data Valid Delay
520
335
NOTES:
1. Parameter does not apply to Interrupt Acknowledge
transactIons.
2. Parameter appbes only between transactIons involvmg

666

theZ-ASCC
*Tunmgs are prehmmary and subject to change.

r Umts 10 nanoseconds (ns).

2016-015

Interrupt
Acknowledge
Timing

ii

~

------""'\.
iii

~----~~~-----'I

ADO-AD7----------------------~--------------~~--{

,.,

I...

Reset
Timing

i

Cycle
Timing

4MHz
No.

Symbol

Parameter

Min

Max

6 MHz
Min
Max

23
TdDS(DRz)
DS t to Read Data Float Delay
70
45
24
TdA(DR)
Address Required Valid to Read Data Vahd Delay
570
420
25
TdDS(W)
DS I to Wait Valid Delay
240
200
TdDSf(REQ)
DS I to W/REQ Not Valid Delay
26
240
200
27--TdDSr(REQ)-DS t to DTRlREQ Not Valid D e l a y - - - - - - - - 5TcPC
5TcPC
+250
+300
28
TdAS(INT)
AS t to INT Valid Delay
500
500
29
TdAS(DSA)
AS t to DS I (Acknowledge) Delay
30
TwDSA
DS (Acknowledge) Low Width
250
390
31
TdDSA(DR)
DS I (Acknowledge) to Read Data Valid Delay
250
180
32 - TsIEI(DSA) - - lEI to DS I (Acknowledge) Setup Time - - - - - 120
100
33
ThIEI(DSA)
lEI to DS t (Acknowledge) Hold Time
0
0
34
TdIEI(lEO)
lEI to lEO Delay
120
100
35
TdAS(lEO)
AS t to lEO Delay
250
250
36
TdDSA(INT)
DS I (Acknowledge) to INT Inactive Delay
500
500
37-TdDS(ASQ)--DS t to AS I Delay for No R e s e t - - - - - - - - 30
15
38
TdASQ(DS)
AS t to DS I Delay for No Reset
30
30
39
TwRES
AS and DS Coincident Low for Reset
250
250
40
TwPCl
PCLK Low Width
105
2000
70
1000
41
TwPCh
PCLK High Width
70
105
1000
2000
42 -- TcPC
PCLK Cycle Time - - - - - - - - - - - - 250- 4000 - - 1 6 5 - 2000
43
TrPC
PCLK Rise Time
20
15
44
TfPC
PCLK Fall Time
20
10

Notes*t
3
4

4

5

6
4
7

NOTES:
3. Float delay IS defmed as the hme requIred for a ± 0.5 V change
In the output with a maXimum de load and mInimUm ae load.
4. Open~dram output, measured wlth open-dram test load.

5. Parameter IS system dependent. For any Z-ASCC m the daISY
cham, TdAS(DSA) must be greater than the sum of TdAS(IEO)
for the hlghest pnonty devlCe In the daISY cham, TsIEI(DSA)
for the Z-ASCC, and TdIEIf{lEO) for each deVice separatIng
them In the daISY cham.

2016-016,017,018

6. Parameter appbes only to a Z-ASCC pullmg INT Low at the

begmnmg of the Interrupt Acknowledge transaction.
7. Internal circUltry allows for the reset provIded by the Z8 to be
recogmzed as a reset by the Z~ASCC.
* TImmgs are prehmmary and subject to change All hmmg references assume 2.0 V for a lOgIC "I" and 0.8 V for a lOgiC "0".
r Umts m nanoseconds (ns).

667

-------l~----------

,---E17)

'------~"...-.....\~---I/

----~

668

2245-007

4 MHz
No.

Symbol

Parameter

I

TdPC(REQ)

PCLK

j

to W/REQ Vahd

2

TdPC(W)

PCLK

j

to Wait Inachve Delay

RxC f to PCLK f Setup Time (PCLK - 4 case only)
RxD to RxC f Setup TIme (XI Mode)
RxD to RxC f Hold Time (XI Mode)

Min

Max

6 MHz
Min

250
350

Max

Notes*t

250
350

3

TsRXC(PC)

4
5-

TsRXD(RXCr)
ThRXD(RXCr) -

6
7

TsRXD(RXCf)
ThRXD(RXCf)

8

TsTXC(PC)

RxD to RxC j Hold TIme (XI Mode)
TxC j to PCLK f Setup Time

9

TdTXCf(TXD)
TdTXCr(TXD) -

TxC j to TxD Delay (XI Mode)
TxC f to TxD Delay (XI Mode)

TdTXD(TRX)

TxD to TRxC Delay (Send Clock Echo)
RTxC High Width

180

180

6

13
14
15 16

TwRTXh
TwRTXI
TcRTX
TcRTXX - - TwTRXh

RTxC Low Width
RTxC Cycle Time
Crystal OSCIllator Period - - - - - - - - - TRxC High Width

180
400
250 -1000 - 180

180
400
250 180

6
6

17
18
19

TwTRXI
TcTRX
TwEXT

TRxC Low Width
TRxC Cycle TIme

180
400

180
400

200

200

10 II
12

RxD to RxC

j

80

Setup Time (XI Mode)

DCD or CTS or

TwPCI

70

TwPCI

1,4

I
0
150 - - - - - - 1 1,5
0

0
150
0
150
0

1,5

150
0

2,4

300
2
300
300 - - - - - 3 0 0 - - 2,5-

lIT Pulse WIdth

1000 - - - 3 6

6
6

NOTES.

1 RxC

IS

RTxC or TRxC, whichever

18

supplymg the receive

clock
2. TxC IS TRxC or RTxC, whIchever IS supplymg the transmit
clock.
3 Both RTxC and FIT have 30 pF capaCItors to the ground
connected to them

4. Parameter appltes only If the data rate IS one-fourth the PCLK
rate In all other cases, no phase relationship between RxC and

PCLK or TxC and PCLK IS requITed.
5. Parameter applies only to FM encodmg/decodmg.
6. Parameter applies only for transmItter and receiver, DPLL and
baud rate generator hmmg requIrements are Identical to chip

PCLK requirements.
Tlmmgs are prehmmary and subject to change.
r Umts m nanoseconds (ns)
It

669

I

System
Timing

RT.C,~
AECEIVE

\

j

\

W'REQ
REQUEST

14-

'"

WIREQ
WAIT

14-

,

14-

~

:1
\

RTxC. TRaC
TRANSMIT

W'RBQ------------------------~----------~

REQUEST

W'RaQ
WAIT

DTNREQ·------------------------~----~
REQUEST

CTS, DCii,RI

No.

Symbol

Parameter

1
2
3

TdRXC(REQ)
TdRXC(W)
TdRXC(INT)

RxC I to W/REQ Valid Delay
RxC I to Walt Inactive Delay
RxC I INT Valid Delay

45
6
7

TdTXC(REQ)-TxC
TdTXC(W)
TxC
TdTXC(DRQ)
TxC
TdTXC(INT)
TxC

8

TdEXT(INT)

I
I
I
I

DCD.

)

CD

4MHz
Min

8
8

8
+2
to WIREQ Valid Delay - - - - - - - - 5
to Wait Inacuve Delay
5
to DTRlREQ Valid Delay
4
to INT Valid Delay
4
+2
or CTS Transition to INT Valid Delay
2

ru

NOTES:
1. ~n~dram output, measured wtth open-dram test load.
2. RxC 18 RTxC or TRxC, whichever 18 supplymg the receive
clock.
3. TIC IS TRxC or RTxC, whtchever 18 supplymg ilie transnut
clock.

670

t

Max

6MH.
Min
Max

Notes*

12
12
2,4
8
12
12
8
1.2,4
12
8
12
1.2,4
+3
+2
+3
5
- - 8 - - - 5 - - 8 - - - 3.48
5
8
1.3,4
3,4
4
7
7
6
4
6
1.3.4
+3
+2
+3
5
3
2
3
1.5

4. Uruts equal to TcPC.
5. Umt. equal to AS.
... TimIngs are prellmmary and subJect to change.

2245-008

ORDERING INFORMATION
Z8031 Z·ASCC, 4.0 MHz
44·pinPCC
Z8031 VS

Z8031 Z·ASCC, 4.0 MHz
40·pinDIP
Z8031 PS
Z8031 CS

Z8031 Z·ASCC, 8.0 MHz
44·pinPCC
Z8031 A VS

Z8031A Z·ASCC, 6.0 MHz
40·pinDIP
Z8031APS
Z8031ACS

Codes
First letter is for package; second letter is for temperature.
C = Ceramic DIP
P = Plastic DIP
L = Ceramic LCC
V = Plastic PCC

R
T
DIP
LCC
PCC

=
=
=
=
=

TEMPERATURE
S = O°Cto + 70°C
E = -40°Cto +85°C
M*= -55°Cto +125°C

FLOW
B = 883 Class B

I...

Protopack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

i

Example: PS is a plastic DIP, O°C to + 70°C.

t Available soon
* For Military Orders, contact your local Zllog Sales Office for Military Electrical Specifications.

00-2245-03

671

Z8036 Z8000® Z-CIO
Counter/Timer and
Parallel I/O Unit

Product
Specification

Zilog

April 1985

Features

General
Description

• Two independent 8-bit, double-buffered,
bidirectional I/O ports plus a 4-bit
special-purpose I/O port. I/O ports
feature programmable polarity,
programmable direction (Bit mode), "pulse
catchers," and programmable opendrain outputs.

• Flexible pattern-recognition logic, programmable as a 16-vector interrupt controller.

• Four handshake modes, including 3-Wire
(like the IEEE-488).

• Three independent l6-bit counter/timers
with up to four external access lines per
counter/timer (count input, output, gate,
and trigger), and three output duty cycles
(pulsed, one-shot, and square-wave),
programmable as retriggerable or
nonretriggerable.

• REQUEST/WAIT signal for high-speed data
transfer.

• Easy to use since all registers are read/write
and directly addressable.

The Z8036 Z-CIO Counter/Timer and
Parallel I/O element is a general-purpose
peripheral circuit, satisfying most
counter/timer and parallel I/O needs
encountered in system designs. This versatile
device contains three I/O ports and three
counter/timers. Many programmable options
tailor its configuration to specific applications.

The use of the device is simplified by making
all internal registers (command, status, and
data) readable and (except for status bits)
writable. In addition, each register is given its
own unique address so that it can be
accessed directly-no special sequential
operations are required. The Z-CIO is directly
Z-Bus compatible.

ADDRESS/DATA
BUS

1

.-..... AD,
ADa

P
'_)
PAsA
........

........ ADs

PAs ..........

........ AD4

PA4.........

_

ADa

PAa _ _

_

AD2

PA 2

AD,

PA,

_

ADo

PAo"""'"

CONTROL

----.
{

----.

os-

~w

Z8038 PC 2

Z·CIO

--+- CSo

cs,

iNT

INTERRUPT {

--+- INTACK
lEI

--+-

lEO

AD,
AD,

PORT A

AD,

ADo

os

CsO

RiW
OND

··0

pes ......... }

BUS TIMINO {' ----. AS
AND RESET

AD,

..-.

PC, ........

PB,

PORTe

'"

PA,

PB,

PA,

PB,

P.,

PCo .......

PB,

P",

PB, _ _ )

PB,

PA,

PB6 ........

PBs
PB
4

-

PBa _

PORT B

PB,

PAs

PB,

PA,

PCLK

INTACK

iNT

PB,

+5V

Po. __

PB, .........

PC,
PC,

PC,

PCLK +5 V GND

Figure 1. Pin Functions

2014-001,002

Figure 2a. 40-pin Dual-In-Line Package (DIP).
Pin Assignments

673

I

§

Pin

ADo-AI>,. Z-Bus Address/Data lines

Description

(bidirectionaV3-state). These multiplexed
Address/Data lines are used for transfers
between the CPU and Z-CIO.

INT. Interrupt Request (output, open-drain,
active Low). ThIs SIgnal IS pulled Low when
the Z-CIO requests an interrupt.
INTACK. Interrupt Acknowledge (input, active

AS*. Address Strobe (input, active Low).

Low). This signal indicates to the Z-CIO that
an Interrupt Acknowledge cycle is In progress.
INTACK is sampled whIle AS is Low.

Addresses, INTACK, and CSo are sampled
while AS is Low.
CSg and CSl. Chip Select a (input, active
Low) and Chip Select 1 (Input, active High).
CSo and CSj must be Low and High, respectively, in order to select a device. CSo is
latched by AS.
DS*. Data Strobe (input, active Low). DS provides timing for the transfer of data into or out
of the Z-CIO.
lEI. Interrupt Enable In (input, active High).
lEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High IEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active
High). lEO is High only if lEI is High and the
CPU is not serviCing an interrupt from the
requesting Z-CIO or is not requesting an interrupt (Interrupt Acknowledge cycle only). lEO
is connected to the next lower priority deViCe's
lEI input and thus inhibits interrupts from
lower priority devices.
·When AS and OS are detected Low at the same time (normally
an Illegal condItion), the Z-CIO

IS

PAa-PA7. Port A I/O lmes (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer information between the Z-CIO's Port
A and external devices.
PBo-PB,. Port B I/O lines (bidIrectional,
3-state, or open-drain). These eight I/O lines
transfer information between the Z-CIO's Port
B and external devices. May also be used to
provide external access to Counter/Timers
1 and 2.
PCo-PCa. Port C I/O lines (bidirectional,
3-state, or open-drain). These four I/O lines
are used to provide handshake, WAIT, and
REQUEST lines for Ports A and B or to provide
external access to Counter/Timer 3 or access
to the Z-CIO's Port C.
PCLK. (input, TTL-compatible). This IS a
peripheral clock that may be, but is not
necessarily, the CPU clock. It is used with
timers and REQUESTIWAIT logic.

8/W. Read/Write (input). RIW indicates that
the CPU is reading from (High) or writing to
(Low) the Z-CIO.

reset.

6

R/W
NC

5

4

3

2

1

~ ~ ~

41

~

7

39

•

3.
37

PAD

PBo

1.

36

PA,

P8,

11

3.

PA,
PA,

GND

P8,

9

cs
AS

Z8036

z.e.o

P8,

13

3'
33

P8,

14

3.

PA,

1.

31
3.

PAt
PA,

29

NC

"

P8,

,.

P8,

17

P8,

PA,

18 19 20 21 22 23 24 25 26 27 28

Figure 2b. "-pin Chip Carrier.
PIB AsaigDJDeBts

674

2014·003

Arc:hitec:ture

The 28036 2-CIO Counter/Timer and
Parallel I/O element (Figure 3) consists of a

INTERRUPT

CONTROL
LOOIC
INTERRUPT

2-Bus interface, three I/O ports (two generalpurpose 8-bit ports and one special-purpose

f---------~'N=TE~R=N7.AL~B~U~S--------~\G~RT~
~
110

CONTROL

'-----'

Z·BUS
INTERFACE

I

~

INTERNAL
CONTROL
LOGIC

i

110

Figure 3. Z-CIO Block Diagram

2014·004

675

Architecture

(Continued)

4-bit port), three 16-bit counter/timers, an
interrupt control logic block, and the internal
control logic block. An extensive number of
programmable options allow the user to tailor
the configuration to best suit the specific
application.
The two general-purpose 8-bit I/O ports
(Figure 4) are identical, except that Port B can
be specified to provide external access to
Counter/Timers 1 and 2. Either port can be
programmed to be a handshake-driven,
double-buffered port (input, output, or bidirectional) or a control-type port with the direction
of each bit individually programmable. Each
port includes pattern-recognition logiC, allowing interrupt generation when a specific pattern is detected. The pattern-recognition logiC
can be programmed so the port functions like
a priority-interrupt controller. Ports A and B
can also be linked to form a 16-bit VO port.
To control these capabilities, both ports contain 12 registers. Thre~ of these registers, the

Input, Output, and Buffer registers, comprise
the data path registers. Two registers, the
Mode SpeCification and Handshake Specification registers, are used to define the mode of
the port and to specify which handshake, if
any, is to be used. The reference pattern for
the pattern-recognition logiC is defined via
three registers: the Pattern Polarity, Pattern
Transition, and Pattern Mask registers. The
detailed characteristics of each bit path (for
example, the direction of data flow or whether
a path is inverting or noninverting) are programmed using the Data Path Polarity, Data
Direction, and Special I/O Control registers.
The primary control and status bits are
grouped in a single register, the Command
and Status register, so that after the port is initia
ly configured, only this register must be
accessed frequently. To facilitate initialization,
the port logic is designed so that registers
associated with an unrequired capability are
ignored and do not have to be programmed.
TO COUNTEM1MERS 1 AND 2
(PORT B ONLy)
~

INTERNAL

INPUT
BUFFERI

OUTPUT
DATA
REGISTER

INVERTERS

AND

,',

CATCHER

PATTERN

RECOGNITION
LOGIC

INPUT
DATA

OUTPUT

BUFFERI

REGISTER

INVERTERS

PORT
CONTROL

LOGIC

TO PORT C

Fig.... 4. Poria A and B Block Diagram

676

2014-005

Architecture
(Continued)

The function of the special-purpose 4-bit
port, Port C (Figure 5), depends upon the
roles of Ports A and B. Port C provides the
required handshake lines. Any bits of Port C
not used as handshake lines can be used as
I/O lines or to provide external access for the
third counter/timer.
Since Port C's function is defined primarily
by Ports A and B, only three registers (besides
the Data Input and Output registers) are
needed. These registers specify the details of
each bit path: the Data Path Polarity, Data
Direction, and Special I/O Control registers.
The three counter/timers (Figure 6) are all
identical. Each is comprised of a 16-bit downcounter, a 16-bit Time Constant register
(which holds the value loaded into the downcounter), a 16-bit Current Counter register
(used to read the contents of the downcounter). and two a-bit registers for control
and status (the Mode Specification and the
Command and Status registers).
The capabilities of the counter/timer are

numerous. Up to four port I/O lines can be
dedicated as external access lines for each
counter/timer: counter input, gate input, trigger input, and counter/timer output. Three different counter/timer output duty cycles are
available: pulse, one-shot, or square-wave.
The operation of the counter/timer can be programmed as either retriggerable or nonretriggerable. With these and other options, most
counter/timer applications are covered.
The interrupt control logic provides standard
Z-Bus interrupt capabilities. There are live
registers (Master Interrupt Control register,
three Interrupt Vector registers, and the Current Vector register) associated with the interrupt logic. In addition, the ports' Command
and Status registers and the counter/timers'
Command and Status registers include bits
associated with the interrupt logic. Each of
these registers contains three bits for interrupt
control and status: Interrupt Pending (IP),
Interrupt Under Service (IUS), and Interrupt
Enable (IE).

TO PORT TO PORT

A

B

TO COUNTERI
TIMER 3

INPUT
BUFFER!
INVERTERS
AND

1',
CATCHER

~PORT
~I/O

OUTPUT
BUFFERI
INVERTERS

PORT
CONTROL
LOGIC

~r----=:J--, ~

)'-----{'i>;-NTERNAL PORT
CONTROL liNES

Figure S. Pori C Block Diagram

2014-006

677

I

§

Architecture
(Continued)

INTERNAL

BUS

CURRENT
COUNT
REGISTER
(MSI's)

18-BIT

DOWN
COUNTER
CURRENT
COUNT
REGISTER
(LSB',)

COUNTER

I\r-----I

CONTROL
LINES

TO PORT

Figure 6. Coulller/Tlmer Block Diagram

Functional
Description

The following describes the functions
of the ports, pattern-recognition logic,
counter/timers, and interrupt logic.

1/0 Port Operations. Of the Z-CIO's three
I/O ports, two (Ports A and B) are generalpurpose, and the third (Port C) is a specialpurpose 4-bit port. Ports A and B can be configured as input, output, or bidirectional ports
with handshake. (Four different handshakes
are available.) They can also be linked to form
a single 16-bit port. If they are not used as
ports with handshake, they provide 16 input or
output bits with the data direction programmable on a bit-by-bit basis. Port B also
provides access for Counter/Timers I and 2. In
all configurations, Ports A and B can be programmed to recognize specific data patterns
and to generate interrupts when the pattern is
encountered.
The four bits of Port C provide the handshake lines for Ports A and B when required.
A REQUEST/WAIT line can also be provided
so that Z-CIO transfers can be synchronized
with DMAs or CPUs. Any Port C bits not used
for handshake or REQUESTIWAIT can be used
as input or output bits (individually data direction programmable) or external access lines for
Counter/Timer 3. Port C does not contain any
pattern-recognition logic. It is, however,
capable of bit-addressable writes. With this
feature, any combination of bits can be set
and/or cleared while the other bits
remain undisturbed without first reading the
register.

port's Data Direction register specifies the
direction of data flow for each bit. A I
specifies an input bit, and a 0 specifies an output bit. If bits are used as I/O bits for a
counter/timer, they should be set as input or
output, as required.
The Data Path Polarity register provides the
capability of inverting the data path. A I
specifies inverting, and a 0 specifies noninverting. All discussions of the port operations assume that the path is noninverting.
The value returned when reading an input
bit reflects the state of the input just prior to
the read. A I's catcher can be inserted into the
input data path by programming a I to the
corresponding bit pOSition of the port's Special
I/O Control register. When a I is detected at
the I's catcher input, its output is set to a I
until it is cleared. The I's catcher is cleared
by writing a 0 to the bit. In all other cases,
attempted writes to input bits are ignored.
When Ports A and B include output bits,
reading the Data register returns the value
being output. Reads of Port C return the state
of the pin. Outputs can be speCified as opendrain by writing a I to the corresponding bit of
the port's Special I/O Control register. Port C
has the additional feature of bit-addressable
writes. When writing to Port C, the four most
significant bits are used as a write protect
mask for the least significant bits (0-4, 1-5,
2-6, and 3-7). If the write protect bit is written
with a I, the state of the corresponding output
bit is not changed.

Bit Port Operations. In bit port operations, the

678

2014-007

Functional
Description
(Continued)

Ports with Handshake Operation. Ports A and
B can be specified as 8-blt Input, output, or
bidirectional ports with handshake. The Z-CIO
provides four different handshakes for its
ports: Interlocked, Strobed, Pulsed, and
3-Wire. When specified as a port with handshake, the transfer of data into and out of the
port and interrupt generation is under control
of the handshake logic. Port C provides the
handshake lines as shown in Table 1. Any Port
C lines not used for handshake can be used as
simple I/O lines or as access lines for Counter/
Timer 3.
When Ports A and B are configured as ports
with handshake, they are double-buffered.
This allows for more relaxed interrupt service
routine response time. A second byte can be
input to or output from the port before the
interrupt for the first byte is serviced. Normally, the Interrupt Pending (IP) bit is set and
an interrupt is generated when data is shifted
into the Input register (input port) or out of the
Output register (output port). For input and
output ports, the IP is automatically cleared
when the data is read or written. In bidirectional ports, IP is cleared only by command.
When the Interrupt on Two Bytes (lTB) control
bit is set to 1, interrupts are generated only
when two bytes of data are available to be read
or written. This allows a minimum of 16 bits of
information to be transferred on each interrupt. With ITB set, the IP is not automatically
cleared until the second byte of data is read or
written.
When the Single Buffer (SB) bit is set to 1,
the port acts as if it is only Single-buffered.
This is useful if the handshake line must be
stopped on a byte-by-byte basis.
Ports A and B can be linked to form a 16-bit
port by programming a 1 in the Port Link Control (PLC) bit. In this mode, only Port A's
Handshake Specification and Command and
Status registers are used. Port B must be
specified as a bit port. When linked, only Port
Port AlB CoaflguraUOD

A has pattern-match capability. Port B's
pattern-match capability must be dIsabled.
Also, when the ports are linked, Port B's Data
register must be read or written beforQ
Port A's.
When a port is specified as a port with handshake, the type of port it is (input, output, or
bidirectional) determines the direction of data
flow. The data direction for the bidirectional
port is determined by a bit in Port C (Table 1).
In all cases, the contents of the Data Direction
register are ignored. The contents of the
Special I/O Control register apply only to output bits (3-state or open-drain). Inputs may not
have l's catchers; therefore, those bits in the
Special I/O Control register are ignored. Port
C lines used for handshake should be programmed as inputs. The handshake specification overrides Port C's Data Direction register
for bits that must be outputs. The contents of
Port C's Data Path Polarity register still apply.
Interlocked Handshake. In the Interlocked
Handshake mode, the action of the Z-CIO must
be acknowledged by the external device
before the next action can take place. Figure 7
shows timing for Interlocked Handshake. An
output port does not indicate that new data is
available until the external device indicates it
is ready for the data. Similarly, an input port
does not indicate that it is ready for new data
until the data source indicates that the previous byte of the data is no longer available,
thereby acknowledging the input port's acceptance of the last byte. This allow:s the Z-CIO to
interface directly to the port of a Z8 microcomputer, a UPC, an FlO, an FIFO, or to another
Z-CIO port with no external logic.
A 4-bit deskew timer can be inserted in the
Data Available (DAY) output for output ports.
As data is transferred to the Buffer register,
the deskew timer is triggered. After the
number of PCLK cycles speCified by the
deskew timer time constant plus one, DAY is

Pea

Pea

PCI

BIt I/O

BIt I/O

Bit I/O

BIt I/O

Port A: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake)'

RFD orDAV

ACKIN

REQUESTIW AIT
or Bit I/O

BIt I/O

Port B: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake)'

REQUEST/WAIT
or Bit I/O

BIt I/O

RFD or DAV

ACKIN

Port A or B: Input Port (3,W,re
Handshake)

RFD (Output)

DAV (Input)

REQUESTIWAIT
or Bit I/O

DAC (Output)

Port A or B: Output Port (3,W,re
Handshake)

DAV (Output)

DAC (Input)

REQUESTIWAIT
or BIt I/O

RFD (Input)

Port A or B: Bidirectional Port
(Interlocked or Strobed Handshake)

RFD orDAV

ACKIN

REQUESTIWAIT
or Bit I/O

IN/OUT

Ports A and B:

Bit Ports

PCo

'Both Ports A and B can be speCified input or output Wlth Interlocked, Strobed, or Pulsed Handshake at the same I1me If neither
uses REQUESTIWAI!.

Table I. Port C Bit Utilization

679

I
i

Functional
Desc:rlptlon
(Continued)

allowed to go Low. The deskew timer therefore
guarantees that the output data is valid for a
specified minimum amount of time before DAV
goes Low. Deskew timers are available for output ports independent of the type of handshake
employed.
Strobed Handshake. In the Strobed Handshake mode, data is "strobed" into or out of
the port by the external logic. The falling edge
of the Acknowledge Input (ACKIN) strobes
data into or out of the port. Figure 7 shows
timing for the Strobed Handshake. In contrast
to the Interlocked Handshake, the signal
indicating the port is ready for another data
transfer operates independently of the ACKIN
input. It is up to the external logic to ensure
that data overflows or underflows do not occur.
3-Wire Handshake. The 3-Wire Handshake is
designed for the situation in which one output
port is communicating with many Input ports
Simultaneously. It is essentially the same as the
Interlocked Handshake, except that two signals
are used to indicate if an input port is ready
for new data or if it has accepted the present
data. In the 3-Wire Handshake (Figure 8), the
rising edge of one status line indicates that the
port is ready for data, and the rising edge of
another status line indicates that the data has
been accepted. With the 3-Wire Handshake,
the output lines of many input ports can be
bussed together with open-drain drivers; the

OUTPUT HANDSHAKE

INPUT HANDSHAKE

DATA:::X:

output port knows when all the ports have
accepted the data and are ready. This is the
same handshake as is used on the IEEE-488
bus. Because this handshake requires three
ines, only one port (either A or B) can be a
3-Wire Handshake port at a time. The 3-Wire
Handshake is not available in the bidirectional
'Ilode. Because the port's direction can be
'langed under software control, however,
bidirectional IEEE-488-type transfers can be
performed.
Pulsed Handshake. The Pulsed Handshake
(Figure 9) is designed to interface to
mechanical-type devices that require data to
be held for long periods of time and need
relatively wide pulses to gate the data into or
out of the device. The logiC is the same as the
Interlocked Handshake mode, except that an
internal counter/timer is linked to the handshake logic. If the port is specified in the input
mode, the timer is inserted in the ACKIN path.
The external ACKIN input triggers the timer
and its output is used as the Interlocked Handshake's normal acknowledge input. If the port
is an output port, the timer is placed in the
Data Available (DAV) output path. The timer is
triggered when the normal Interlocked Handshake DAV output goes Low and the timer output is used as the actual DAV output. The
counter/timer maintains all of its normal
capabilities. This handshake is not available to
bidirectional ports.

VALID

X"'_________
STROBED
HANDSHAKE......,. -

RPD
OATA LATCHED

IN BUFFER REGISTER

-

DATA _____~~NEa~~~~---------

..., - - -

DATA MOVED
TO INPUT
REGISTER

INTERLOCKED
HANDSHAKE
BUFFER REGISTER
"EMPTIED"
NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER

Figure 7. mterlocked cmcI. Strobed Hcmd8bakee

OUTPUT HANDSHAKE

INPUT HANDSHAKE

DATA:=X

VALID

DAC

DATA
III'D

iiiV

INPUT

INPUT

RPD
OUTPUT

X\..._________

--*~

OUTPUT _ _ _~-J

NEXTIYTE

==:::-___

..1

DAC

INPUT

iiiV

OUTPUT

IUP,.ER REGISTER
"EMP11ED"

NEXT IYTE

IHlmOFROM
OUTPUT REGISTER TO
IUFFER REGISTER

Figure 8. 3-WIre Hcmdshake

680

2014·008, 009

Functional
Description
(Continued)

REQUESTIWAIT Line Operation. Port C can
be programmed to provide a status signal output in addition to the normal handshake lines
for either Port A or B when used as a port with
handshake. The additional signal is either a
REQUEST or WAIT signal. The REQUEST
signal indicates when a port is ready to perform a data transfer via the Z-Bus. It is
intended for use with a DMA-type device. The
WAIT signal provides synchronization for
transfers with a CPU. Three bits in the Port
Handshake Specification register provide controls for the REQUESTIWAIT logic. Because
the extra Port C line is used, only one port can
be specified as a port with a handshake and a
REQUESTIWAIT line. The other port must be
a bit port.
Operation of the REQUEST line is modified
by the state of the port's Interrupt on Two
Bytes (lTB) control bit. When ITB is a, the
REQUEST line goes active as soon as the
Z-CIO is ready for a data transfer. If ITB is I,
REQUEST does not go active until two bytes
can be transferred. REQUEST stays active as
long as a byte is available to be read or
written.
The SPECIAL REQUEST function is reserved
for use with bidirectional ports only. In this
case, the REQUEST line indicates the status of
the register not being used in the data path at
that time. If the IN/OUT line is High, the
REQUEST line is High when the Output
register is empty. If IN/OUT is Low, the
REQUEST line is High when the Input register
is full.
Pattern-Recognition Logic Operation. Both
Ports A and B can be programmed to generate
interrupts when a specific pattern is recognized at the port. The pattern-recognition logic
is independent of the port application, thereby
allowing the port to recognize patterns in all of
its configurations. The pattern can be
independently specified for each bit as 1, a,
rising edge, falling edge, or any transition.
IndiVidual bits may be masked off. A patternmatch Is defined as the simultaneous satisfaction of all nonmasked bit specifications in the
AND mode or the satisfaction of any nonmasked bit specifications in either of the OR or
OR-Priority Encoded Vector modes.

OUTPUT PORT

Fig.... 9. PuJaed Handshake
2014'()10

The pattern specified in the Pattern Definition regIster assumes that the data path is programmed to be noninverting. If an input bit in
the data path is programmed to be inverting,
the pattern detected is the opposite of the one
specified. Output bits used in the patternmatch logic are internally sampled before the
invertlnoninvert logic.
Bit Port Pattern-Recognition Operations. During bit port operations, pattern-recognition
may be performed on all bits, including those
used as 1/0 for the counter/timers. The input
to the pattern-recognition logic follows the
value at the pins (through the mvertlnoninvert
logic) in all cases except for simple inputs with
I's catchers. In this case, the output of the I's
catcher is used. When operating in the AND
or OR mode, it is the transition from a nomatch to a match state that causes the interrupt. In the "OR" mode, if a second match
occurs before the first match goes away, it
does not cause an interrupt. Since a match
condition only lasts a short time when edges
are specified, care must be taken to avoid
losing a match condition. Bit ports speCified in
the OR-Priority Encoded Vector mode generate
interrupts as long as any match state exists. A
transition from a no-match to a match state is
not required.
The pattern-recognition logic of bit ports
operates in two basic modes: Transparent and
Latched. When the Latch on Pattern Match
(LPM) bit is set to a (Transparent mode), the
interrupt indicates that a specified pattern has
occurred, but a read of the Data register does
not necessarily indicate the state of the port at
the time the interrupt was generated. In the
Latched mode (LPM= I), the state of-all the
port inputs at the time the interrupt was generated is latched in the input register and held
until IP is cleared. In all cases, the PMF indicates the state of the port at the time it is read.
If a match occurs while IP is already set, an
error condition exists. If the Interrupt On Error
bit (lOE) is 0, the match is ignored. However,
if IOE is I, after the first IP is cleared, it is
automatically set to I along with the Interrupt
Error (ERR) flag. Matches occurring while ERR
is set are ignored. ERR is cleared when the
corresponding IP is cleared.
When a pattern-match is present in the
OR-Priority Encoded Vector mode, IP is set to
I. The IP cannot be cleared until a match is no
longer present. If the interrupt vector is
allowed to include status, the vector returned
during Interrupt Acknowledge indicates the
highest priority bit matching its speCification at
the time of the Acknowledge cycle. Bit 7 is the
highest priority and bit a is the lowest. The bit
initially causing the interrupt may not be the
one indicated by the vector if a higher priority
bit matches before the Acknowledge. Once the
Acknowledge cycle is initiated, the vector is
681

I

§

FunctloDCll
Description
(Continued)

frozen until the corresponding IP is cleared.
Where inputs that cause interrupts might
change before the interrupt is serviced, the l's
catcher can be used to hold the value.
Because a no-match to match transition is not
required, the source of the interrupt must be
cleared before IP is cleared or else a second
interrupt is generated. No error detection is
performed in this mode and the Interrupt On
Error bit should be set to O.

FuDCIioD

TIlIGa....

.A..
PULlIOUTPUT

C/Ta

PBD

Counter Input

PBS

PB 1

Trigger Input

PB6

PB2

Gate Input

PB 7

PB3

PCD
PC 1
PC2
PC3
~

The flexibility of the counter/timers is
enhanced by the provision of up to four lines
per counter/timer (counter input, gate input,
trigger input, and counter/timer output) for
direct external control and status. Counter/
Timer I's external I/O lines are provided by
the four most significant bits of Port B.
CounterlTimer 2's are provided by the four
least significant bits of Port B. Counter/Timer
3' s external I/O lines are provided by the four
bits of Port C. The utilization of these lines
(Table 2) is programmable on a bit-by-bit basis
via the Counter/Timer Mode Specification
registers.
When external counter/timer I/O lines are to
be used, the associated port lines must be
vacant and programmed in the proper data
direction. Lines used for counter/timer I/O
have the same characteristics as simple input
lines. They can be specified as inverting or
noninverting; they can be read and used with
the pattern-recognition logic. They can also
include the I's catcher input.
CounterlTimers I and 2 can be linked internally in three different ways. CounterlTimer
I's output (inverted) can be used as Counter/
Timer 2's trigger, gate, or counter input.
When linked, the counter/timers have the
same capabilities as when used separately. The
only restriction is that when Counter/Timer I
drives Counter/Timer 2's count input,
Counter/Timer 2 must be programmed with
its external count input disabled.
There are three duty cycles available for the
timer/counter output: pulse, one-shot, and
square-wave. Figure 10 shows the counter/

..,
..,
..,
r-1 r-1 P"; r-1 . , r.....J LJ LJ LJ LJ LJ LJ LJ LJ

.-J
I

TO

I

U
TO-1

'I

I

TC-1

I

TO..,

\- - -\ '

\

-----_,J------J

ON.IHOT ~
OUTIIIUT

C/Ta

PB4

Table 2. Counter/Timer ExterllCll

Ports with Handshake Pattern-Recognition
Operation. In this mode, the handshake logic
normally controls the setting of IP and,
therefore, the generation of interrupt requests.
The pattern-match logic controls the Pattern
Match Flag (PMF). The data is compared with
the match pattern when it is shifted from the
Buffer register to the Input register (input port)
or when it is shifted from the Output register to
the Buffer register (output port). The patternmatch logic can override the handshake logic
in certain situations. If the port is programmed
to interrupt when two bytes of data are
available to be read or written, but the first
byte matches the specified pattern, the
pattern-recognition logic sets IP and generates
an interrupt. While PMF is set, IP cannot be
cleared by reading or writing the data
registers. IP must be cleared by command.
The input register is not emptied while IP is
set, nor is the output register filled until IP is
cleared.
If the Interrupt on Match Only (IMO) bit is
set, IP is set only when the data matches the
pattern. This is useful in DMA-type applications when interrupts are required only after a
block of data is transferred.
Counter/Timer Operation. The three
independent 16-bit counter/timers consist of a
presettable 16-bit down counter, a 16-bit Time
Constant register, a 16-bit Current Counter
register, an 8-bit Mode Specification register,
an 8-bit Command and Status register, and the
associated control logic that links these
registers.
POUlI. OR
COUNTUlINPUT

C/TI

CounterlTlmer Output

~:

\

II

L-

I~

-r-

IQUARIWAV.
I"IRITHALP
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _-II

. .UA... WAV.
OUTIIIUT
8ECONDHALF

'~
Figure 10. Counter/Timer Wa.,.1or1U

682

2014-011

Functional
Description
(Continued)

timer waveforms. When the Pulse mode is
specified, the output goes High for one clock
cycle, beginning when the down-counter
leaves the count of 1. In the One-Shot mode,
the output goes High when the counter/timer is
triggered and goes Low when the downcounter reaches O. When the square-wave output duty cycle is specified, the counter/llmer
goes through two full sequences for each
cycle. The initial trigger causes the downcounter to be loaded and the normal countdown sequence to begin. If a I count is
detected on the down-counter's clocking edge,
the output goes High and the time constant
value is reloaded. On the clocking edge, when
both the down-counter and the output are I's,
the output is pulled back Low.
The Continuous/Single Cycle (C/SC) bit in
the Mode Specification register controls operation of the down-counter when it reaches terminal count. If C/SC is 0 when a terminal
count is reached, the countdown sequence
stops. If the C/SC bit is I each time the countdown counter reaches I, the next cycle causes
the time constant value to be reloaded. The
time constant value may be changed by the
CPU, and on reload, the new time constant
value is loaded.
Counter/timer operations require loading the
time constant value in the Time Constant
register and initiating the countdown sequence
by loading the down-counter with the time
constant value. The Time Constant register is
accessed as two 8-bit registers. The registers
are readable as well as writable, and the
access order is irrelevant. A 0 in the Time
Constant register specifies a time constant of
65,536. The down-counter is loaded in one of
three ways: by writing a 1 to the TrIgger
Command Bit (TCB) of the Command and
Status register, on the rising edge of the external trigger input, or, for Counter/Timer 2 only,
on the rising edge of Counter/Timer I's internal output if the counters are linked via the
trigger input. The TCB is write-only, and read
always returns O.
Once the down-counter is loaded, the countdown ~equence continues toward termmal
count as long as all the counter/timers' hardware and software gate inputs are High. If any
of the gate inputs goes Low (0), the countdown
halts. It resumes when all gate inputs are I
again.
The reaction to triggers occurring during a
countdown sequence is determined by the state
of the Retrigger Enable Bit (REB) in the Mode
Specification register. If REB is 0, retriggers
are ignored and the countdown continues normally. If REB is I, each trigger causes the
down-counter to be reloaded and the countdown sequence starts over again. If the output

is programmed in the Square-Wave mode,
retrigger causes the sequence to start over
from the initial load of the time constant.
The rate at which the down-counter counts is
determined by the mode of the counter/timer.
In the Timer mode (the External Count Enable
[ECE] bit is 0), the down-counter is clocked
internally by a signal that is half the frequency
of the PCLK input to the chip. In the Counter
mode (ECE is 1), the down-counter is
decremented on the rising edge of the counter/
timer's counter input.
Each time the counter reaches terminal
count, its Interrupt Pending (IP) bit is set to 1,
and if interrupts are enabled (IE = 1), an interrupt is generated. If a terminal count occurs
while IP is already set, an internal error flag is
set. As soon as IP is cleared, it is forced to a I
along with the Interrupt Error (ERR) flag.
Errors that occur after the internal flag is set
are ignored.
The state of the down-counter can be determined in two ways: by reading the contents of
the down-counter via the Current Count
register or by testing the Count In Progress
(CIP) status bit in the Command and Status
register. The CIP status bit is set when the
down-counter is loaded; it is reset when the
down-counter reaches o. The Current Count
register is a 16-bit register, accessible as two
8-bit registers, which mirrors the contents of
the down-counter. This register can be read
anytime. However, reading the register is
asynchronous to the counter's counting, and
the value returned is valid only if the counter
is stopped. The down-counter can be reliably
read "on the fly" by the first writing of a I to
the Read Counter Control (RCC) bit in the
counter/timer's Command and Status register.
This freezes the value in the Current Count
register until a read of the least significant
byte is performed.

Interrupt Logic Operation. The interrupts
generated by the Z-CIO follow the Z-Bus
operation as described more fully in the Zilog
Z-Bus Summary. The Z-CIO has five potential
sources of interrupts: the three counter/timer~
and Ports A and B. The priorities of these
sources are fixed in the follOWing order:
Counter/Timer 3, Port A, Counter/Timer 2,
Port B, and Counter/Timer I. Since the
counter/timers all have equal capabilities and
Ports A and B have equal capabilities, there is
no adverse impact from the relative priorities.
The Z-CIO interrupt priority, relative to
other components within the system, is determined by an interrupt daisy cham. Two pins,
Interrupt Enable In (lEI) and Interrupt Enable
Out (lEO), provide the input and output
necessary to implement the daisy chain. When
lEI is pulled Low by a higher priority deVice,

683

I

s
c

Functional
Description
(Continued)

the Z-CIO cannot request an interrupt of the
CPU. The following discussion assumes that
the lEI line is High.
Each source of interrupt in the Z-CIO contains three bits for the control and status of the
interrupt logic: an Interrupt Pending (IP)
status bit, an Interrupt Under Service (IUS)
status bit, and an Interrupt Enable (IE) control
bit. IP is set when an event requiring CPU
intervention occurs. The setting of IP results in
forcing the Interrupt (INT) output Low, if the
associated IE is I.
The IUS status bit is set as a result of the
Interrupt Acknowledge cycle by the CPU and
is set only if its IP is of highest priority at the
time the Interrupt Acknowledge commences. It
can also be set directly by the CPU. Its
primary function is to control the interrupt
daisy chain. When set, it disables lower priority sources in the daisy chain, so that lower
priority interrupt sources do not request servicing while higher priority devices are being
serviced.
The IE bit provides the CPU with a means of
masking off individual sources of interrupts.
When IE is set to I, an interrupt is generated
normally. When IE is set to 0, the IP bit is set
when an event occurs that would normally
require service; however, the INT output is not
forced Low.
The Master Interrupt Enable (MIE) bit allows
all sources of interrupts within the Z-CIO to be
disabled without having to individually set
each IE to O. If MIE is set to 0, all IPs are
masked off and no interrupt can be requested
or acknowledged. The Disable Lower Chain

(DLC) bit is included to allow the CPU to
modify the system daisy chain. When the DLC
bit is set to I, the Z-CIO's IEO is forced Low,
independent of the state of the Z-CIO or its lEI
input, and all lower priority devices' interrupts
are disabled.
As part of the Interrupt Acknowledge cycle,
the Z-CIO is capable of responding with an
a-bit interrupt vector that specifies the source
of the interrupt. The Z-CIO contains three vector registers: one for Port A, one for Port B,
and one shared by the three counter/timers.
The vector output is inhibited by setting the No
Vector (NV) control bit to I. The vector output
can be modified to include status information
to pinpoint more precisely the cause of interrupt. Whether the vector includes status or not
is controlled by a Vector Includes Status (VIS)
control bit. Each base vector has its own VIS
bit and is controlled independently. When
MIE = 1, reading the base vector register
always includes status, independent of the
state of the VIS bit. In this way, all the information obtained by the vector, including
status, can be obtained with one additional
instruction when VIS is set to O. When
MIE = 0, reading the vector register returns
the unmodified base vector so that it can be
verified. Another register, the Current Vector
register, allows use of the Z-CIO in a polled
environment. When read, the data returned is
the same as the interrupt vector that would be
output in an acknowledge, based on the
highest priority IP set. If no unmasked IPs are
set, the value FFH is returned. The Current
Vector register is read-only.

Programming

Programming the Z-CIO entails loading control registers with bits to implement the desired
operation. Individual enable bits are provided
for the various major blocks so that erroneous
operations do not occur while the part is being
initialized. Before the ports are enabled, IPs
cannot be set, REQUEST and WAIT cannot be
asserted, and all outputs remain high-impedance. The handshake lines are ignored until
Port C is enabled. The counter/timers cannot
be triggered until their enable bits are set.
The Z-CIO is reset by forcing AS and DS
Low Simultaneously or by writing a 1 to the
Reset bit. Once reset, the only thing that can
be done is to read and write the Reset bit.
Writes to all other bits are ignored and all
reads return Os. In this state, all control bits
are forced to O. Only after clearing the Reset

bit (by writing to it) can the other command
bits be programmed.
Register Addressing. The Z-CIO allows two
schemes for register addressing. Both schemes
use only six of the eight bits of the address/
data bus. The scheme used is determined by
the Right Justify Address (RJA) bit in the
Master Interrupt Control register. When RJA
equals 0, address bus bits 0 and 7 are ignored,
and bits I through 6 are decoded for the
register address (Ao from ADj). When RJA
equals I, bits 0 through 5 are decoded for the
register address (Ao from ADo). In the following register descriptions, only six bits are
shown for addresses and represent address/
data bus bits 0 through 5 or I through 6,
depending on the state of the RJA bit.

684

Registers

Master IDtenupt CoDtrol Register
Address: 000000
(Read/Write)

MASTER
INTERRUPT
ENABLE
(MIE)

~~

DISABLE LOWER CHAIN (DLC)
NO VECTOR (NV)

Master ConflguratioD CoDtrol Register
Address: 000001
(Read/W rite)

~RESET

~

PORT A VECTOR INCLUDES

PORTB~JJ

L

ENABLE (PRE)

RIGHT JUSTIFIED ADDRESSES
0:: SHIFT LEFT (Ao from AD1)
, = RIGHT JUSTIFY (Ao from ADo)

[

COUNTERITIMER 1
ENABLE (CTfE)

COUNTERfTlMERS VECTOR
INCLUDES STATUS (CT VIS)

!&Q

o

1
0
1

o

0

INDEPENDENT

COUNT

CIT ,'s
CIT 1'8
CIT 1'8

GATES CIT 2
TRIGGERS CIT 2

IS CIT 2'8

COUNT INPUT

STATUS (PA VIS)

PORT C AND COUNTERI

PORT B VECTOR INCLUDES

~

1
1

COUNTERfTlMER 2
ENABLE (CT2E)

STATUS (PB VIS)

COUNTERITIMER LINK
CONTROLS (LC)

PORT A ENABLE (PAE)

TIMER 3 ENABLE
(PCE AND C13E)

PORT LINK CONTROL (PLe)
O=PORTS A AND B OPERATE INDEPENDENTLY
1 : PORTS A AND B ARE LINKED

Figure II. Master Control Registers

Port HaDdshake SpeciflcatioD Registers
Addresses: 100001 Port A
10 100 I Port B
(Read/Write)

Port Mode SpeclflcatioD Registers
Addresses: 100000 Port A
101000 Port B
(Read/Write)

PORTTVPE~

SELECTS (PTS)
PTS1 PTSO,

----0 ----0 BIT PORT
o 1 INPUT PORT
1
1

0
1

OUTPUT PORT
BIDIRECTIONAL
PORT

INTERRUPT ON TWO
BYTES (ITB)
SINGLE BUFFERED
MODE (SB)

L

J

I~I~I~I~I~I~I~I~I

LATCH ON PATTERN MATCH (LPM)
(BIT MODE)
DESKEW TIMER ENABLE (OTE)
(HANDSHAKE MODES)

HANDSHAKE TYPE SPECIFICATION
BITS (HST)
HST1 HSTO

PATTERN MODE SPECIFICATION
BITS (PMS)
PMS1 PMSO
- . - - - . - DISABLE PATTERN MATCH
o
1 "AND"MODE
1
0 "OR" MODE
1
1 "OR·PRIORITY ENCODED
VECTOR" MODE

g

~ ~~~~Ri~;~~~~~f:~AKE

1
1

0
1

-c

OESKEW TIME SPECIFICATION
BITS

~~i~~~~I~HE~ ~~~8C°ciNSTANT,
LSB IS FORCED 1.

PULSED HANDSHAKE
THREE·WIRE HANDSHAKE

REQUEST/WAIT SPECIFICATION BITS
(RWS)
RWS2 RWS1 RWSO FUNCTION

T

INTERRUPT ON MATCH ONLY (IMO)

1

o
1
1

~~~~~~~~~T OISABLED
INPUT WAIT
SPECIAL REQUEST
OUTPUT REQUEST
INPUT REQUEST

Port Command and Status Registers
Addresses: 001000 Port A
001001 Port B
(Read/Partial Write)

10" 0,1 0, I0.1 0, I0, I0, 10.1
INTERRUPT UNDER.JjJ
SERVICE (IUS)
INTERRUPT ENABLE (IE)

:

I

INTERRUPT PENDING (IP)

I

I

I

IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING CODE'
NULL CODE

0

0

0

CLEAR IP & IUS

0

0

1
0

0

1

•

1

1

1

0

0

CLEAR IP

1

0

1

SET IE

1

CLEAR IE

1

1 0
1 1

SET IUS
CLEAR IUS
SET IP

~

I L

L

INTERRUPT ON ERROR (lOE)

PATTERN MATCH FLAG (PMF)
(READ ONLy)
INPUT REGISTER FULL (IRF)
(READ ONLy)
OUTPUT REGISTER EMPTY (ORE)
(READ ONLy)

INTERRUPT ERROR (ERR)
(READ ONLy)

Figure 12. Port Specification Registers

2014-012. 013

685

I

§

Registers
(Continued)

Data Path Polarity Registers
Addresses: 100010 Port A
101010 Port B
000101 Port C (4 LSBs only)
(Read/Write)

Data Direction Registers
Addresses: 100011 Port A
101011 Port B
000110 Port C (4 LSBs only)
(Read/Write)

' - - - - - DATA DIRECTION (DD)

' - - - - - DATA PATH POLARITY (DPP)
0= NON·INVERTING
1 = INVERTINQ

o-OUTPUT BIT
1-INPUT BIT

Special 1/0 Control Registers
Addresses: 100100 Port A
101100 Port B
000111 Port C (4 LSBs only)
(Read/Write)

' - - - - - SPECIAL INPUT/OUTPUT (SIO)

0 .. NORMAL INPUT OR OUTPUT

1 = OUTPUT WITH OPEN DRAIN OR
INPUT WITH 1', CATCHER

Figure 13. Bit Path Definition Registers

Port Data Registers
Addresses: 001101 Port A
001110 Port B
(Read/Write)

Port C Data Register
Address: 001111
(Read/Write)

4 MBa.

o_WRITING OF CORRESPONDINO LSD ENABLED
1_WRITINO OF CORRESPONDING L881NHI81TED

(READ RETURNS 11

Figure 14. Port Data Registers

Pattern Polarity Registers (PP)
Addresses: 100101 Port A
101101 Port B
(Read/Write)
Pattern Transition Registers (PT)
Addresses: 100110 Port A
101110 Port B
(Read/Write)

PM PT PP PAneAN SPECIFICATION
BIT MASKED OFF
ANY TRANSITION
100ZERO
1 0 1 ONE
1 1 0 ONE·TO·ZERO TRANSITION (\0)
1 1 1 ZERO-YO-ONE TRANSITION (I)

(lOX
o 1 )(

Pattern Mask Registers (PM)
Addresses: 100111 Port A
101111 Port B
(Read/Write)
Figure 15. Pattern Definition Registers

686

2014-014,015,016

Registers
(Continued)

Counter/Timer Command and Status Registers
Addresses: 0010 10 Counter/Timer 1
001011 Counter/Timer 2
001100 Counter/Timer 3
(ReacllPartial Write)

INTERRUPT UNDER SERVICE (IUS)

--1jJl

INTERRUPT ENABLE (IE)

I

I

I

1

I

NULL CODe

0

0

CLEAR IP & IUS

0

0

1

SET IUS

0

1

0

CLEAR IUS

0

1

INTERRUPT PENDING (IP)

E~

COUNT IN PAOGAESS (CIPI

(READ ONLY)
TRIGGER COMMAND BIT (TeB)
(WRITE ONLY· READ RETURNS 0)
GATE COMMAND BIT (GCB)
READ COUNTER CONTROL (RCC)
(READ/SET ONLY CLEARED BY READING CCR LSB)

IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING CODE.
0

1

SETIP100
CLEAR IP

1

SET IE

0

1

110

CLEAR IE

1

1

1

I

INTERRUPT eRROR (ERR) - - - - '
(READ ONLy)

Counter/Timer Mode Specification Registers
Addresses: 011100 Counter/Timer 1
011101 Counter/Timer 2
011110 Counter/Timer 3
(Read/Write)

CONTINUOUS SJ!!·

OLE CYCLE (eISC)

JJillj

EXTERNAL OUTPUT
ENABLE (EOE)
EXTERNAL COUNT
ENABLE (EeE)
EXTEANAL TAIGGEA

ENABLE (ETE)

L

§

OUTPUT DUTV CVCLE

SELECTS (DCS)

9~S1 ~ PULSE OUTPUT

I~
I

0

1

ONe·SHOT OUTPUT

1
1

0
1

SQUARE-WAVE OUTPUT
DO NOT SPECIFY

AETAIGGEA ENABLE BIT (AEBI

EXTERNAL GATE ENABLE (EGE)

Counter/Timer Current Count Registers
Addresses: 010000 Counter/Timer l's MSB
010001 Counter/Timer l's LSB
010010 Counter/Timer 2's MSB
010011 Counter/TImer 2's LSB
010100 Counter/Timer 3's MSB
010101 Counter/Timer 3's LSB
(Read Only)

MOST----'
SIGNIFICANT

'----LEAST
SIGNIFICANT

BYTE

BYTE

CounterITlmer Time Constant Registers
Addresses: 010110 Counter/Timer I's MSB
010111 Counter/Timer 1'. LSB
011000 Counter/Timer 2's MSB
011001 Counter/Timer 2's LSB
011010 Counter/Timer 3's MSB
011 0 11 Counter/Timer 3' s LSB
(Read/Write)

MOST----'
SIGNIFICANT

BYTE

' - - - - LEAST
SIGNIFICANT
BYTe

Figure 16. Conter/Timer Registers

2014·017

687

Registers

Interrupt Vector Register
Addresses: 000010 Port A
000011 Port B
000100 Counter/Timers
(Read/Write)

(Continued)

Current Vector Register
Address: 011111
(Read Only)

'----- ~~~~:~:;:;~::'T~ASED
UNMASKED IP.
IF NO INTERRUPT PENDING

' - - - - - INTERRUPT VECTOR

ALL 1', OUTPUT.

PORT YECTOR STATUS

PRIORITY ENCODED VECTOR MODE:
~

x

~

x

Ql
x

NUMBER OF HIGHEST PRIORITY BIT
WITH A MATCH

ALL OTHER MODES:
D3 D2 D1

ORE liF PMF
o 0 0

NORMAL

ERROR

COUNTERITIMER STATUS
D2 D1

o
o

"0

1

1
0

1

1

CIT 3
CIT 2

err 1

ERROR

Figure 17. Interrupt Vector Registers

Register
Address
Summary

Main Control Registers
Register Name
Master Interrupt Control
Master Conhgurahon Control
Port A's Interrupt Vector
Port B's Interrupt Vector
Counter/TImer's Interrupt Vector
Port C's Data Path Polarity
Port C's Data Direchon
Port C's SpeCIal I/O Control

Address'
100000
100001
100010
100011
100100
lOOlOl
100110
100111

Port A Specification Registers
Register Name
Pori A's Mode Specification
Port A's Handshake Specification
Port A's Data Path Polarity
Pori A's Data Direction
Pori A's SpeCIal 110 Control
Port A's Pattern Polarity
Pori A's Pattern Transition
Port A's Pattern Mask

001000
001001
001010
001011
001100
001101
001110
001111

Most Often Accessecl Registers
Register Name
Port A's Command and Status
Port B's Command and Status
Counter/Timer I's Command and Status
Counter/Timer 2's Command and Status
Counter/TImer 3's Command and Status
Port A's Data
Port B's Data
Port C's Data

Address·
101000
101001
101010
101011
101100
101101
101110
101111

Port B Specification Registers
Register Name
Port B's Mode SpecIfication
Pori B's Handshake SpeCIfication
Port B's Data Path Polarity
Port B's Data Dlreciion
Port B's SpeCIal 110 Control
Port B's Pattern Polarity
Port B's Pattern Translhon
Port B's Pattern Mask

Address'
010000
010001
010010
010011
010100
010101
010110
010111
011000
OIJOOI
OllOlO
011011
011100
011101
011110
011111

CounterITimer Related Registers
Register Name
Counter/Timer I's Current Count-MSBs
Counter/TImer I's Current Count-LSBs
Counter/Timer 2's Current Count-MSBs
Counter/TImer 2's Current Count-LSBs
Counter/TImer 3's Current Count-MSBs
Counter/TImer 3's Current Count-LSBs
CounterlTlmer l's Time Constant-MSBs
CounterlTimer I's TIme Constant-LSBs
CounterlTlmer 2's TIme Constant-MSBs
Counter/Timer 2's Time Constant-LSBs
CounterlTlmer 3'9 TIme Constant-MSBs
Counter/TImer 3's Time Constant-LSBs
CounterlTimer l's Mode SpecIfICation
Counter/TImer 2's Mode Specificahon
Counter/TImer 3's Mode Specificahon
Current Vector

Address·
000000
000001
000010
000011
000100
000101
000110
000111

Address·

'When RIA

688

= 0,

AO from ADI: when RIA

=

I,

Ao from ADO

2014-018

Timing

Read Cycle. The CPU places an address on
the address/data bus. The more significant bits
and status information are combined and
decoded by external logic to provide two Chip
Selects (CSo and CSl). Six bits of the least
significant byte of the address are latched
within the Z-CIO and used to specify a Z-CIO
register. The data from the register specified is
strobed onto the address/data bus when the
CPU issues a Data Strobe (DS). If the register
indicated by the address does not exist, the
Z-CIO remains high-impedance.

ca.

Write Cycle. The CPU places an address on
the address/data bus. The more significant bits
and status information are combined and
decoded by external logic to provide two Chip
Selects (CSo and CSl). Six bits of the least
significant byte of the address are latched
within the Z-CIO and used to specify a Z-CIO
register. The CPU places the data on the
address/data bus and strobes it into the Z-CIO
register by issuing a Data Strobe (DS).

ca. _ _- J

_ _- J

iii
ADo-AD7

r-

\

~

Figure 18. Read Cycle Timing

WRITE DATA

C

Figure 19. Write Cycle Timing

Interrupt Acknowledge Cycle. When one of
the IP bits in the Z-CIO goes High and interrupts are enabled, the Z-CIO pulls its INT
output line Low, requesting an interrupt. The
CPU responds with an Interrupt Acknowledge
cycle. When !NTACK goes Low with IP set, the
Z-CIO pulls its Interrupt Enable Out (lEO)

Low, disabling all lower priority devices on the
daisy chain. The CPU reads the Z-CIO interrupt vector by issuing a Low DS, thereby
strobing the interrupt vector onto the address/
data bus. The IUS that corresponds to the IP is
also set, which causes lEO to remain Low.

--J!

HiT _ _ _ _ _ _ _ _ _

,.,
,...

\\-------

\'-_--:'

iii

~INTACK IS

decoded from Z8000 status.

Figure 20. Interrupt Acknowledge Timing

2014-019,020, 021

689

I
i

Absolute
Maximum
Ratings

Voltages on all pins with respect
toGND ................... -0.3Vto +7.0V
Operating Ambient
Temperature ....... See Ordering Information
Storage Temperature ........ - 65°C to + 150°C

Standard
Test
Conditions

The DC characteristics and capacitance sections below apply for the following standard test
conditions, unless otherwIse noted. All voltages
are referenced to GND. Positive current flows
into the referenced pin.
Standard conditions are as follows:
• +4.75 V,;; Vee';; +5.25 V

Stresses greater than those listed under Absolute MaxImum Ratmgs may cause permanent damage to the devIce.

ThIs is a stress rating only; operahon of the device at any
condition above those indicated in the operational sections
of these specifIcations is not implied. Exposure to absolute
maximum rahng conditions for extended periods may affect
devICe reliabIlity.

• GND = 0 V
• TA as speCified in Ordering Information
All ac parameters assume a load capacitance
of 50 pf max.
The Ordering Information section lists temperature ranges and product numbers. Package
drawings are in the Package Information section
in this book. Refer to the Literature List for additional documentation .

.5V

•••

d·
+5V

K

FROM OUTPUT
UNDEATEST

50 Pf

Figure 21. Standard Test Load

DC
Characteristics

Symbol

Parameter

VIH

Input HIgh Voltage

VIL
VOH
VOL

Input Low Voltage
Output High Voltage
Output Low Voltage

IlL
IOL
Icc

Input Leakage
Output Leakage
Vee Supply Current

J

Figure 22. Open-Drain Test Load

Min

Max

Unit

2.0

Vee+ 0.3
0.8

V
V
V
V
V
/LA

-0.3
2.4

0.4
0.5
± 10.0
± 10.0
200

JLA

Condition

IOH=
IOL=
IOL=
0.4 s
0.4 s

-250/LA
+2.0 rnA
+3.2 rnA
VIN S +2.4 V
VOUT S +2.4 V

rnA

Vee = 5 V ± 5% unless otherWise speCified, over specifIed temperature range.

Capacitance

Symbol

Parameter
Input CapaCitance
Output CapaCitance
Bidlrechonal CapaCitance

Min

Max

Unit

10
15
20

pi
pi
pi

Test Condition

f = 1 MHz, over speCIhed temperature range.
Unmeasured pms returned to ground.

690

8085·0209.0001

CPU
Interface
Timing

CS,

wW

------H-~~_r---------+~----------

READ

AlW

WAITE

iii

I

ADDA•••

ADo-AD7

CIO

§

WRITE

CIO
READ

Interrupt
Timing

PATTERN MATCH ~
INPUT,S. - - - - '
BIT PORT

T

.

ACKIN
NOTE ..

PATTERN MATCHES

@

\

.

.. 1

@

.

COUNTER

INPUT

%
PCL!(

-®
is

---®-

\

INT

Interrupt
Acknowledge
Timing

ADO~AD7

------~...::~~.....)~-----

________ XUNDEFINED)......

iii

lEI

lEO

2014-022,023,024

691

4MHz
No.

Symbol

Parameter

Min

Max

6 MHz
Min

Max

Notes*t

I
TwAS
AS Low W1dth
70
2000
50
2000
2
TsA(AS)
Address to AS t Setup Time
10
30
3
ThA(AS)
Address to AS t Hold Time
50
30
I
4 -TsA(DS) ---Address to DS j Setup T i m e - - - - - - - - - 1 3 0 - - - - - - 1 0 0 - - - - - - - I - 5
TsCSO(AS)
CSo to AS t Setup Time
6
ThCSO(AS)
CSo to AS t Hold T,me
7
TdAS(DS)
AS t to DS I Delay
8-TsCSI(DS)--CS 1 to DS I Setup Time

0
60
60
100

0
40
40
80--------

9
TsRWR(DS)
R/W (Read) to DS I Setup Time
100
80
10
TsRWW(DS)
R/W (Write) to DS I Setup T,me
o
0
II
TwDS
DS Low Width
390
250
12 - TsDW(DSf)-- Write Data to DS I Setup T i m e - - - - - - - - - 30
20 - - - - - - - - 13
TdDS(DRV)
DS (Read) I to Address Data Bus Driven
0
0
14
TdDSf(DR)
DS I to Read Data Valid Delay
250
180
Write Data to DS t Hold T,me
15
ThDW(DS)
30
20
16- TdDSr(DR) - - DS t to Read Data Not Valid D e l a y - - - - - - - 0 - - - - - - 0 - - - - - - - 17
TdDS(DRz)
DS t to Read Data Float Delay
70
45
2
18
ThRW(DS)
R/W to DS t Hold Time
55
40
19
ThCSI(DS)
CS 1 to DS t Hold Time
55
40
20-TdDS(AS)--DS t to AS I D e l a y - - - - - - - - - - - - 50 - - - - - - 2 5 - - - - - - - 21

Trc

Vahd Access Recovery Time

1000

650

3

22
TdPM(INT)
Pattern Match to INT Delay (Bit Port)
1+800
1+800
6
23
TdACK(INT)
ACKIN to INT Delay (Port with Handshake)
4+600
4,6
4+600
24-TdCI(INT)--Counter Input to INT Delay (Counter Mode)------I +700-----1 + 7 0 0 - - - 6 25
26

TdPC(lNT)
TdAS(INT)

PCLK to INT Delay (T,mer Mode)
AS to INT Delay

I +700
300

1+700

6

27
TsIA(AS)
INTACK to AS t Setup Time
o
o
28
ThIA(AS)
INTACK to AS t Hold Time
250
250
29
TsAS(DSA)
AS t to DS (Acknowledge) I Setup T,me
350
250
5
30-TdDSA(DR)--DS (Acknowledge) I to Read Data Valid Delay'------ 2 5 0 - - - - - - 1 8 0 1 - - - - 31
TwDSA
DS (Acknowledge) Low Width
390
250
32
TdAS(IEO)
AS t to lEO I Delay (lNTACK Cycle)
350
250
5
33-TdlEI(lEO)--lEI to lEO Delay---------------150-----100---~5j__34
TsIEI(DSA)
lEO to DS (Acknowledge) I Setup Time
100
70
5
lEI to DS (Acknowledge) t Hold T,me
35
ThIEI(DSA)
100
70
36
TdDSA(INT)
DS (Acknowledge) I to INT t Delay
600
600
NOTES:

1. Parameter does not apply to Interrupt Acknowledge transachons.
Float delay IS measured to the hme when the output has
changed 0.5 V from steady state with mlmmum ae load and
maximum de load.
3. ThiS IS the delay from iSS I of one CIa access to
j of
another CIa access.
4 The delay IS from DAV I for 3-Wire Input Handshake. The
delay IS from DAC I for 3-Wlre Output Handshake. One
addlhonal AS cycle IS required for ports 10 the Smgle Buf·
fered mode.
2.

:os

692

5. The parameters for the devlCes many parhcular daiSY
cham must meet the followmg constramt. the delay from
AS 1 to:5S 1 must be greater than the sum of TdAS(IEO)
for the highest Priority peripheral, TsIEI(DSA) for the
lowest priority penpheral, and TdIEI(IEO) for each
peripheral separatmg them m the cham.
6. Umts equal to AS cycle + ns.
* Tlmmgs are prelimmary and subject to change.
t Umts In nanoseconds(ns), except as noted

Strobed
Handshake

INPUT

OUTPUT

Interlocked
Handshake

I

~. ~ -~tr'----INPUT

AC::

§

-----\-'~---'3"--BT~...;;';.....'--------

DATA

OUTPUT

a-Wire
Handshake

iCiii

DATA

DAY

INPUT

INPUT
R~D

OUTPUT

"ilil

OUTPUT

-----....1[

DATA

DAC

INPUT

OUTPUT
II~D

INPUT

/WI

OUTPUT

2014-025, 026, 027

693

No.

Symbol

Parameter

TsDl(ACK)
ThDl(ACK)

Data Input to ACKIN ! Setup T,me
Data Input to ACKIN ! Hold Time - Strobed
2
Handshake
ACKIN ! to RFD ! Delay
TdACKf(RFD)
3
4-TwACKI---ACKIN Low W,dth - Strobed Handshake
5
TwACKh
ACKIN High W ldth - Strobed Handshake
6
7

RFD 1 to ACKIN ! Delay
Data Out to DAV ! Setup T,me
TdDAVf(ACK) DAV ! to ACKIN ! Delay
8
9-ThDO(ACK)--Data Out to ACKIN ! Hold Time

10
II

TdRFDr(ACK)
TsDO(DAV)

Min

a

4MHz
Max

6MHz
Min
Max

Notes*t

a

500

a

a

250
250

a

a

25

20

a

a

1------1------2-

TdACK(DAV)
ThDl(RFD)

ACKIN! to DAV 1 Delay
I
I
2
Data Input to RFD ! Hold T,me - Interlocked
a
a
Handshake
12
TdRFDf(ACK)
RFD! to ACKIN 1 Delay - Interlocked Handshake
a
a
13-TdACKr(RFD)-ACKIN 1 (DAV1 )toRFD 1 Delay I n t e r l o c k e d - - O - - - - - - O - - - - - - - and 3-Wire Handshake
14
TdDAVr(ACK) DAV 1 to ACKIN 1 (RFD 1 ) - Interlocked and
a
a
3-Wire Handshake
15
TdACK(DAV)
ACKIN 1 (RFD 1 )to DAV ! Delay - Interlocked and
a
a
3-Wlre Handshake
16-TdDAVIf(DAC)-DAV! toDAC 1 Delay - Input3-W,re H a n d s h a k e - - O - - - - - - O - - - - - - - 17
ThDl(DAC)
Data Input to DAC 1 Hold T,me - 3-Wlre
a
a
Handshake
18
TdDACOr(DAV) DAC 1 to DAV 1 Delay - Input 3-Wire Handshake
a
a
19
TdDAVIr(DAC) DAV 1 to DAC ! Delay - Input 3-Wire Handshake
a
a
20-TdDAVOf(DAC)-DAV! to DAC 1 Delay - Output 3-Wlre H a n d s h a k e - O - - - - - - O - - - - - - - 21
ThDO(DAC)
Data Output to DAC 1 Hold T,me - 3-Wire
I
2
Handshake
22
TdDACIr(DAV) DAC 1 to DAV 1 Delay - Output 3-Wire Handshake
I
2
23
TdDAVOr(DAC) DAV 1 to DAC ! Delay - Output 3-Wlre Handshake
a
a
NOTES:
1. ThIS hme can be extended through the use of the deskew
hmers.
2. Umts equal to

694

AS cycle.

* Tlmmgs are prelimmary and subject to

change. All hmmg
references assume 2.0 V for a logic" 1" and a 8 V for a logiC "0".
t Umts m nanoseconds (ns), except as noted

Counter/
Timer
Timing

peLK

..eLK,2
INTERNAL

_ _ _ _...J

COUNTER

INPUT

QATE

INltUT

I

COUNTER
OUTPUT

~

4 MHz
No.

Symbol

Parameter

Min

Max

S

6 MHz
Min

Max

Notes*t

PCLK Cycle T,me
165
4000
250
4000
TcPC
2000
TwPCh
PCLK Hlgh Width
105
2000
70
2
PCLK Low Width
2000
70
2000
TwPCl
105
3
20
10
PCLK Fall T,me
4
TIPC
PCLK R,se T,me
15
TrPC
20
5
Counter Input Cycle Time
500
330
6-TcCI
Counter Input Hlgh Width
230
150
7
TClh
Counter Input Low W,dth
150
230
8
TwCIl
Counter Input Fall T,me
20
15
TlCI
9
10
TrCI
Counter Input Rise T,me
20
15
11- TsTI(PC)---Trigger Input to PCLK I Setup T,me --150 - - - - - - - - - - - - - - - 2 - - (T,mer Mode)
12
TsTI(CI)
Trlgger Input to Counter Input I Setup
150
2
Time (Counter Mode)
13
TwTI
Trlgger Input Pulse W,dth (Hlgh or Low) 200
l4-TsGI(PC)---Gate Input to PCLK I Setup T,me---lOO - - - - - - - - - - - - - - - 2 - - (Timer Mode)
TsGI(CI)
Gate Input to Counter Input ! Setup
100
2
15
Time (Counter Mode)
ThGI(PC)
Gate Input to PCLK I Hold T,me (Tlmer 100
2
16
Mode)
17 -ThGI(CI)---Gate Input to Counter Input I Hold--lOO - - - - - - - - - - - - - - - 2 - - Time (Counter Mode)
475
TdPC(CO)
PCLK to Counter Output Delay (Timer
18
Mode)
TdCI(CO)
Counter Input to Counter Output Delay
475
19
(Counter Mode)
NOTES
1. PCLK IS only used with the counter/hmers (m Timer mode), the
deskew hmers, and the REQUEST/WAIT logiC If these functions are not used, the PCLK mput can be held low
These parameters must be met to guarantee that tngger or gate

2014-028

are valid for the next counier/bmer cycle
* TImmgs are prehmmary and subject to change. All hmmg refer-

ences assume 2.0 V for a logiC "I" and
t Umts In nanoseconds (ns)

a 8 V for

a logLC

"a"

695

0

REQUEST!

WAIT
Timing

No.

Symbol

Parameter

TdDS(REQ)

iSSl to REQ I Delay

2

TdDS(WAIT)

iSSl to WAIT I Delay

3
4
5

TdPC(REQ)

PCLK I to REQ I Delay

TdPC(WAIT)

PCLK I to WAIT I Delay

TdACK(REQ)

ACKIN I to REQ I Delay

6

TdACK(WAIT)

ACKIN I to WAIT I Delay

Min

NOTES'
1. The Delay

IS from DAV I for the 3-Wire Input Handshake. The
delay IS from DAC 1 for the 3-Wlre Output Handshake.
2. Umts equal to AS cycles + PCLK cycles + ns.

4 MHz
Max

6 MHz
Min
Max

Notes*t

500
500
300
300
3+2
+ 1000
10+600

1,2
3

3. Umts equal to PCLK cycles + ns.
* Tlmmgs are prehmmary and subject to change. All hmmg references assume 2.0 V for a \OglC "I" and 0.8 V for a logic "0".
t Umts In nanoseconds (ns), except as noted.

Reset

Timing

RBSET
INTERNAl.

No.

1
2
3

____________________

Symbol

Parameter

Min

TdDSQ(AS)

Delay from DS I to AS I for No Reset

TdASQ(DS)

Delay from AS I to DS I for No Reset

TwRES

Mmimum WIdth of AS and DS both Low for Reset

40
50
250

NOTES.

1 Internal clrcutry allows for the reset provIded by the Z8
held Low while AS pulses) to be sufficient

696

(iSs

4 MHz
Max

~r

6 MHz
Min
Max

Notes*t

15
30
170

* Tlmmgs are prehmmary and subject to change. All hmmg references assume 2.0 V for a logic "I" and 0.8 V for a loglC "0"
t DOlts m nanoseconds (ns),

2014-029, 030

Miscellaneous
Port
Timing

ANY INPUT

---'l@-r=iLl'-:-'---

1'.CATCHBR
INPUT

r \ .

I~~~-----------

PATURN ----------~,r-------~
). PATTERN MATCHES ) (
MATCH
INPUT,S. --------~~

_______(s}~5:t~~~====~-~*~====::1
V

DATA TO.B
LATCH.D TO
V
PATURN MATCH _ _ _ _ _ _.JA

No.

2

3
4
5
6

,-------

1\.'-_ _ _ _ __

4 MHz
Max

6MHz
Min
Max

Any Input Rise Time

100

100

Any Input Fall Time

100

Symbol

Parameter

TrI

TIl
Twl's

I's Catcher High Width

250

170

TwPM
TsPMD

Pattern Match Input Valid (Bit Port)

750

500

ThPMD

Data Latched on Pattern Match Hold Time (Bit Port)

Min

NOTES:
1. If the Input IS programmed Invertmg, a Low-going pulse of the
same width wIll be detected.

100

a

a

1000

650

Data Latched on Pattern Match Setup Time (Bit Port)

Notes"t

I

• Tlmmgs are prelImmary and subject to change. All hmmg references assume 2.0 V for a logic"}" and 0.8 V for a logic "0",

t Urllts In nanoseconds (ns).

Bidirectional
Port
Timing

IN/jj'jff

J

r-~

Figure 2b. 44-pln Chip Carrier. Pin Assignments

CPU
INTERFACE
OR
110 PORT

CPU

INTERPACE

DATA
BUS v-"'1I"---t

128 X 8

FIFO BUFFER

t--yo/

DATA
BUS

PORT 1 SlOB : PORT 2 SIDE

Figure 3. FlO Block Diagram

700

2020-003,004

Functional
Description

Operating Modes. Ports 1 and 2 operate in
any of twelve combinations of operating
modes, listed in Table 2. Port I functions in
either the Z-BUS or non-Z-BUS microprocessor
modes, while Port 2 functions in Z-BUS, nonZ-BUS, Interlocked 2-Wire Handshake, and
3-Wire Handshake modes. Table I describes
the signals and their correspondmg pins in
each of these modes.
Signal
Pin.

Z-BUS
Low Byte

Z-BUS
High Byte

lKl

REQ/WT
DMASTB
DS
R/W
CS
AS

REQIWT
DMASTB

[i]

[£J
@]
~

W
@]
[ill
[!]

W

iNTACK
lEO
lEI
INT

Os
R/W
CS
AS
Aa
Al
A2
A3

The pin diagrams of the FlO are identical,
except for two pins on the Port 1 side, which
select that port's operating mode. Port 2's
operating mode is programmed by two bits in
Port l's Control register O. Table 2 describes
the combinations of operating modes; Table 3
describes the control signals mapped to pins
A-I m the five possible operating modes.

Mon-Z-BUS

REQIWT
DACK
RD
WR
CE
C/O
INTACK
lEO
lEI
INT

IDt.r1ocked
HS Port·

S-Wlr.
HS Port·

RFD/DAV
ACKIN
FULL
EMPTY
CLEAR
DATA DlR

RFDIDAV
DAV/DAC
DAC/RFD
EMPTY
CLEAR
DATA DlR

INa

INa

OUTI
OE
OUT3

OUTI
OE
OUT3

'2 s.de only.
Table I. Pin Assignment.
Mode

MI
0
0
0
0

5
6

8
10
11

MO

Bl
0

BO

0
1
0

Z·BUS High Byte
Z-BUS High Byte
Z-BUS H.gh Byte
Z·BUS High Byte

Z·BUS H.gh Byte
Non·Z-BUS
3-Wire Handshake
2· Wire Handshake

0

Non·Z·BUS
Non·Z·BUS
Non·Z-BUS
Non·Z-BUS

Z·BUS Low Byte
Non-Z-BUS
3·Wire Handshake
2· Wire Handshake

0
0

0
0

0
0

Port 2
Z·BUS Low Byte
Non·Z·BUS
3· W.re Handshake
2· Wire Handshake

0

0
0
0
0

Port 1
Z-BUS Low Byte
Z·BUS Low Byte
Z·BUS Low Byte
Z·BUS Low Byte

Table 2, Operating Model

701

Functional
Description

CHANNILA

(Continued)

Z8D02

P
'rY

. , - - - - , PORT.



PORTa

1"---./ 

SYSTEM
MEMORY

P
'rY
zaoBU8
I/O

...

} HANDSHAU
BIGNALB

MEMORY

ZoBU8

zaoaus

Figure 4. CPU 10 CPU ConflguratlOll

702

Figure 5. CPU 10 1/0 CoaliguratlOD

2020-005, 006

Pins Common
To Both Sides

Z-BUS
Low Byte
Mode

Pin
Signals

Pin
Names

Pin
Numbers

MO
MI
+5 Vdc
GND

MO
MI
+5 Vdc
GND

21
19
40
20

Pin
Signals

Pin
Names

Pin Number.
Pori
I
2

ADO-AD7
(Address/Data)
REQIWAIT
(RequesVW alt)

DO-~

11-18

DMASTB
(Direct Memory
Access Strobe)

B

2

38

DS
(Data Strobe)
RiW
(ReadIWnte)

C

3

37

D

4

36

Gs

E

5

35

F

6

34

G

7

33

H

8

32

Output, active H,gh. Sends mterrupt enable to
lower priorlty deVIce lEI pm.

9

31

Input, acbve High. ReceIves interrupt enable Irom
hIgher priority device lEO sIgnal.

10

30

Output, open dram, achve Low. SIgnals FlO Interrupt request to CPU.

(ChIp Select)
AS
(Address Strobe)
INTACK
(Interrupt
Acknowledge)
lEO
(Interrupt
Enable Out)
lEI
(Interrupt
Enable In)

A

INT
(Interrupt)

Z-BUS
High Byte
Mode

MI and MO program Port I
SIde CPU mterface
DC power source
DC power ground

29-22
39

Pin
Signals

Pin
Namel

Pin Numbers
Port
I
2

ADO-A~

DO-D7

11-18

(Address/Data)
REQIWAIT
(Request/Walt)

A

29-22
39

DMASTB
(Direct Memory
Access Strobe)

B

2

38

DS
(Data Strebe)

C

3

37

RiW

D

4

36

(ReadlWrite)

Gs

Signal
Description

Signal
Description
Mulbplexed b,dlrecbonal address/data hnes, Z-BUS
compabble.
Output, acbve Low, REQUEST (ready) lme lor DMA
transler; WAIT Ime (open-dram) output lor synchromzed CPU and FlO data translers.
Input, acbve Low. Strobes DMA data to and Irom
the FIFO buller.

N
00

Input, acbve Low. ProvIdes bmmg lor data transler to or Irom FlO.
Input; acbve HIgh sIgnals CPU read Irom FlO;
active Low sIgnals CPU wnte to FlO.
Input, acbve Low. Enables FlO. Latched on the
rlsmg edge 01 AS.
Input, active L~ Addresses, CS and iNTAcK
sampled whlle AS Low.
Input, acbve Low. Acknowled~ an mterrupt.
Latched on the rlsmg edge of AS.

C

W
00
N0

.....e

Signal
Description
Multiplexed bIdirectional address/data hnes, Z-BUS
compabble.
Output, active Low, REQUEST (ready) Ime for DMA
transler; WAIT ltne (open-dram) output for synchromzed CPU and FlO data transfers.
Input, active Low. Strobes DMA data to and from the
FIFO buller.
Input, active Low. ProvIdes timing for transler of data
to or from FlO.
Input, acbve H,gh. Signals CPU read from FlO; active
Low SIgnals CPU Wrlte to FlO.
Input, active LQ!!.. Enables FlO. Latched on the
rlsmg edge of AS.
Input, acbve LoJ!, Addresses, CS and INTACK are
sampled while AS IS Low.

E

5

35

(ChIp Select)
AS
(Address Strobe)

F

6

34

Ao

G

7

33

Input, active HIgh. With Ai, A2, and A3, addresses
FlO mternal registers.

Al
(Address BIt I)

H

8

32

A2
(Address BIt 2)

9

31

Input, actIve HIgh. With
FlO mternal regIsters.
Input, acbve HIgh. W,th
FlO internal registers.

A3
(Address Bit 3)

10

30

(Address Bit 0)

Input, active High. With
FlO Internal registers.

Ao, A2, and A3, addresses
Ao' AI,

and A3, addresses

Ao, AI, and A2, addresses

Table 3. SlgnaVPin Descriptions

703

Non-Z-BUS
Mode

Pin
Signals

Names

Pin Numbers
Port
4

DO-D7

11-18

Pin

DO-D7
(Data)
REQIWT
(RequestIW ait)

A

DACK
(DMA Acknowledge)

B

HiS

C

2

Signal
Description

29-22

BidIrectional data bus.

39

Output, active Low, REQUEST (ready) line for DMA
transfer; WAIT line (open-drain) output for synchronized CPU and FlO data transfer.

38

Input, actIve Low. DMA acknowledge.

37

Input, actIve Low. Signals CPU read from FlO.

(Read)
WR
(Wnte)

D

4

36

Input, actIve Low. Signals CPU wnte to FlO.

CE
(Chip Select)

E

5

35

Input, actIve Low. Used to select FLO.

cii5

F

6

34

Input, active High. Identifies control byte on DO-D7;
actIve Low ldentIhes data byte on DO-D7.

INTACK
(Interrupt
Acknowledge)

G

7

33

Input, actIve Low. AcknoWledges an interrupt.

lEO
(Interrupt
Enable Out)

H

8

32

Output, active HIgh. Sends mterrupt enable to
lower priorIty deVIce lEI pm.

lEI
(Interrupt
Enable In)

9

31

INT
(Interrupt)

10

(ControVData)

Port 2-1/0
Port Mode

Input, active High. Receives interrupt enable from

higher pnonty deVice lEO signal.
Output, open drain, active Low. Signals FlO interrupt
to CPU.

30

Signal
Description

Pin
Signals

Pin
Names

Pin
Numbers

DO-D7
(Data)

DO-D7

29-22

2-Wire HS'
3-Wlre HS

BIdIrectional data bus.

RFD/DAV
(Ready for Data/Data
Available)

A

39

2-Wlre HS
3-Wlre HS

Output, RFD actIve High~nals penpherals that FlO
is ready to receIve data. DA V active Low signals
that FlO IS ready to send data to peripherals.

ACKIN
(Acknowledge Input)

B

38

2-Wlre HS

Input, actIve Low. Signals FlO that output data is
received by penpherals or that input data is vahd.

DAV/DAC
(Data Available/Data
Accepted)

B

38

3-Wlre HS

Input; DA V (actIve Low) signals that data is valid on
bus. DAC (actIve High) signals that output data is
accepted by peripherals.

FULL

C

37

2-Wlre HS

Output, open dram, actIve High. Signals that FlO
buffer IS full.

DAC/RFD
(Data Accepted/Ready
for Data)

C

37

3-Wlre HS

EMPTY

D

36

2-Wlre HS
3-Wlre HS

Output, open dram, actIve High. Signals that FIFO
buffer IS empty.

CLEAR

E

35

2-Wire HS
3-Wlre HS

Programmable mput or output, actIve Low. Clears all
data from FIFO buffer.

DATA DIR
(Data DirectIon)

F

34

2-Wlre HS
3-Wlre HS

Programmable mput or output. Active High signals
data mput to Port 2; Low signals data output from
Port 2.

INa

G

33

2-Wlre HS
3-Wlre HS

Input Ime to DO of Control Register 3.

OUT]

H

32

2-Wlre HS
3-Wlre HS

Output line from D] of Control Register 3.

OE
(Output Enable)

31

2-Wlre HS
3-Wire HS

Input, actIve Low. When Low, enables bus drivers.
When High, floats bus dnvers at high Impedance.

OUT3

30

2-Wire HS
3-Wlre HS

Output Ime from D3 of Control register 3.

Mode

DIrection controlled

'Handshake

Table 3. Signal/Pin Descriptions (Contmued)

704

by mternal programmmg. Both

actIve High. DAC (an output) signals that FlO has
received data from penpheral; RFD (an input) signals
that the lIsteners are ready for data.

Reset

The FIO can be reset under either hardware
or software control by one of the following
methods:
• By forcing both AS and DS Low simultaneously in Z-BUS mode (normally illegal).
• By forcing RD and WR Low simultaneously
in non-Z-BUS mode.
• By writing a 1 to the Reset bit in Control
register 0 for software reset.
In the Reset state, all control bits are cleared
to O. Only after clearing the Reset bit (by

CPU
Interfaces

The FIO is designed to work with both
Z-BUS- and non-Z-BUS-type CPUs on both Port
1 and Port 2. The Z-BUS configuration interfaces CPUs with time-multiplexed address and
data information on the same pins. The Z8001,
Z8002, and Z8 are examples of this type of
CPU. The AS (Address Strobe) pin is used to
latch the address and chip select information
sent out by the CPU. The RlW (Read/Write)
pin and the DS (Data Strobe) pin are used
for timing reads and writes from the CPU to
A~~~~~S

ADo-AD7 - - (

writing a 0 to it) can the other command bits
be programmed. This action is true for both
sides of the FIO when programmed as a CPU
interface.
For proper system control, when Port I is
reset, Port 2 is also reset. In addition, all Port
2' s outputs are floating and all inputs are
ignored. To initiate the data transfer, Port 2
must be enabled by Port 1. The Port 2 CPU
can determine when it is enabled by reading
Control register 0, which reads "floating" data
bus if not enabled and "OIH" if enabled.
the FIO (Figures 6 and 7).
The non-Z-BUS configuration is used for
CPUs where the address and data buses are
separate. Examples of this type of CPU are the
Z80 and 8080. The RD (Read) and WR (Write)
pins are used to time reads and writes from the
CPU to the FIO (Figures 9 and 10). The c/lS
(Control/Data) pin is used to directly access
the FIFO buffer (CiD=O) and to access the
other registers (C/D = 1). Read and write to all

)>-______-«

TO CPU

)>-_____

"--.I

cs

R/WJ

\1... __
\~_----,I
Figure 6. Z-BUS Read Cycle Timing

-«

ADO-AD7 _ _

A~~~~SS

H'-___

DA_TA_F_"D_M_C_PU
______} - -

'Alii

c

\

\'--_ _--'1
Figure 7. Z-BUS Write Cycle Timing

2020-007. 008

705

CPU

Interfaces
(Continued)

registers except the FIFO buffer I are two-step
operations, described as follows (Figure 8).
First, write the address (c/iS = 1) of the register
to be accessed into the Pointer Register (State
0); second, read or write (C/O = 1) to the
register pointed at previously (State 1). Continuous status monitoring can be performed in
State 1 by continuous Control Read operations
(C/O = 1).
1The FIFO buffer can also be accessed by thIS two-step operahon.

RD OR WR

Figure 8. Register Access In Non-Z-BUS Mode

CID===><___________>C
DO-D7

---------------«:T~O~C~pu~r_
\~

____________

~r_

\ .... _ _ _ _...J!
Figure 9. Non-Z-BUS Read Cycle Timing

---'X'-__________x:=:

CID _ _

Do-D7

------«===:!F:RO~M~C~PU~===»----\~

WR

____________...J!

\'-____.....1
Figure 10. Non-Z-BUS Write Cycle Timing

WAIT
Operation

Interrupt
Operation

706

When data is output by the CPU, the
REQ/WT (WAIT) pin is active (Low) only when
the FIFO buffer is full, the chip is selected,
and the FIFO buffer is addressed. WAIT goes
inactive when the FIFO buffer is not full.

When data is input by the CPU, the
REQ/WT pin becomes active (Low) only when
the FIFO buffer is empty, the chip is selected,
and the FIFO buffer is addressed. WAIT goes
inactive when the FIFO buffer is not empty.

The FlO supports Zilog's prioritized daisy
chain interrupt protocol for both Z-BUS and
non-Z-BUS operating modes (for more details
refer to the Zilog Z-BUS Summary).
Each side of the FlO has seven sources of
interrupt. The priorities of these devices are
fixed in the following order (highest to lowest):
Mailbox Message, Change in Data Direction,
Pattern Match, Status Match, Overflow/

Underflow Error, Buffer Full, and Buffer
Empty. Each interrupt source has three bits
that control how it generates the interrupt.
These bits are Interrupt Pending (IP),
Interrupt Enable (IE), and Interrupt Under
Service (IUS).
In addition, each side of the FlO has an
interrupt vector and four bits controlling the
FlO interrupt logic. These bits are Vector

2020-009, 010, 011

Interrupt
Operation

(Continued)

Includes Status (VIS), Master Interrupt Enable
(MIE)' Disable Lower Chain (DLC), and No
Vector (NV).
A typical Interrupt Acknowledge cycle for
Z-BUS operahon IS shown in Figure II and for
non-Z-BUS operation in Figure 12. The only
difference is that in Z-BUS mode, INTACK is
latched by AS, and in non-Z-BUS mode
INTACK is not latched.
When MIE = I, reading the vector always
includes status, independent of the state of the

ADo-AD?

VIS bit. In this way, when VIS = 0, all information can be obtained with one additional
read, thus conserving vector space. When
MIE = 0, readmg the vector register returns
the unmodified base vector so that It can be
verified.
In non-Z-BUS mode, the IPs do not get set
while m State I. Therefore, to minimize mterrupt latency, the FlO should be left in State O.
In Z-BUS mode IPS are set by an AS following
the event.

~------«~~V~EC:TO:R~>--

\______r--

iii

7

lEI

'NT _ _ _ _ _ _ _...J/

Figure 11. Z-BUS Interrupt Acknowledge Cycle

Do-Dr

------------<

'NTACK \

..._ _ _ _ _ _ _ _ _ _ _ _- - ' ,

\ ..... _ _--'1
'E' _ _ _...J/
'NT _ _ _ _ _ _- - J/

Figure 12. Non-Z-BUS Interrupt Acknowledge Cycle

CPU to CPU
Operation

2020·012,013

DMA Operation. The FlO is particularly well

suited to work with a DMA in both Z-BUS and
non-Z-BUS modes. A data transfer between the
FlO and system memory can take place during
every machine cycle on both sides of the FlO
simultaneously.
In Z-BUS mode, the DMASTB pin (DMA
Strobe) is used to read or write into the FIFO
buffer. The RlW (Read/Write) and DS (Data
Strobe) signals are ignored by the FlO;

however, the CS (Chip Select) signal is not
ignored and therefore must be kept invalid.
Figures 13 and 14 show typical timing.
In Non-Z-BUS mode, the DACK pin (DMA
Acknowledge) is used to tell the FlO that its
DMA request is granted. After DACK goes
Low, every read or write to the FlO goes into
the FIFO buffer. Figures 15 and 16 show
typical timing.

707

CPU to CPU
Operation

DATA FROM FlO TO MEMORY

(Continued)

\~_ _--II
AIW

-----------------------------

\'-___-Jr--

Figure 13. Z-BUS flO to Memory Data Transaction

DATA FPlOM MEMORY TO FlO

\~

___---"r-

III.

\'-_---.11
Figure 14. Z-BUS Memory to FlO Data Transaction

ADDAESSES

===><_____M_EM_O_R_Y_A_DD_"_E_SS_O_F_W_R_'T_E____J)(~____________________
"J}-

DATA

{DATA FROM FlO TO MEMORV}---{I..______________

aus

MEMORY
WRITE

110
READ

DACK~~_______________________________________________

Figure IS. Non-Z-BUS FlO to Memory Transaction

ADDR.,••S

===><

MEMORY ADDRESS OF READ

MIMORY
- - - - - ' \~~.__________J./
~

XI..________________________

\'-_---.11

\'-_. . .1

~~I..------------------------------------------------Figure 16. Non-Z-BUS Memory to FlO Data Transaction

708

2020·014, 015, 016, 017

CPU to CPU
Operation

(Continued)

The FlO provides a special mode to enhance
its DMA transfer capability. When data is
written into the FIFO buffer, the REQ/WT
(REQUEST) pin is active (Low) until the FIFO
buffer is full. It then goes inactive and stays
inactive until the number of bytes in the FIFO
buffer is equal to the value programmed into
the Byte Count Comparison register. Then the
REQUEST signal goes active and the sequence
starts over again (Figure 17).

CD

ACTIVE

INACTIVE

When data is read from the FlO, the
REQ/WT pin (REQUEST) is inactive until the
number of bytes in the FIFO buffer is equal to
the value programmed in the Byte Count Comparison register. The REQUEST signal then
goes active and stays active until the FIFO buffer is empty. When empty, REQUEST goes
inactive and the sequence starts over again
(Figure 18).

CD

~::..t--"""T--""--""0

ACTIVE

.....::;CD::..j.-_ _r-;CD;;.'-_--I-- NUMBER OF BYTES IN
EMPTY

CD
-+--------r--

CD

CD

FIFO

INACTIVE

FULL

CD

....:::+----i----~~,.._---

FJlI..

EMPTY

NUMBER IN BYTE COUNT COMPARISON REGISTER

NUMBER IN BYTE COUNT COMPARISON REGISTER

NOTES:
1. FIFO empty.
2. REQUEST enabled, FlO requests DMA tr.nsfer.
3. DMA transfers d.ta into the FlO.
4. FIFO fulL REQUEST inactive.

NOTES:
1. FIFO empty.
2. CPU/DMA hils FIFO buffer from the opposite port.

5. The FIFO empties from the opposite port until the number
of bytes in the FIFO buffer is the same as the number programmed in the Byte Count Comparison register.

4. REQUEST goes active.

3. Number of bytes in FIFO buffer is the same as the number
of bytes programmed in the Byte Count Comparison register.
S. DMA transfers data out of FIFO until it is empty.

Figure 17. Byte Count Control: Write to FlO

Figure 18. Byte Count Control: Read from FlO

interrupted. Port 2's message IP status is
readable from the Port 1 side. When Port 2's
CPU reads the data from its Message In register, the Port 2 IP is cleared. Thus, Port l's
CPU can read when the message has been
read and can now send another message or
follow whatever protocol that is set up between
the two CPU's. The same transfer can also be
made from Port 2's CPU to Port I's CPU.

Message Registers. Two CPUs can communi-

cate through a dedicated "mailbox" register
without involving the 128 x 8 bit FIFO buffer
(Figure 19). This mailbox approach is useful
for transferring control parameters between
the interfacing devices on either side of the
FlO without using the FIFO buffer. For
example, when Port l's CPU writes to the
Message Out register, Port 2's message IP is
set. If interrupts are enabled, Port 2's CPU is
REGISTER
ADDRESS
"C"

PORT 1
~------,\I
MaSUGIOUT

RIGISTIR

MESSAGE
REGISTER
PORT 1
TO
PORT 2

PORT 1
MBaSAGBIN

MESSACS
REGISTEFI
PORT 2

RIGI.TlR

TO
REGISTER

PORT 1

REGISTER
ADDRESS
"B"

1----,
PORT 2
MBSSAGEIN
REOISTaR

\r--==__--./

PORT I
MESSAG.OUT

RRGI.nR

ADDRESS
"8"

NOTE: Usable only for CPU/CPU interface.

Figure 19. Message Register Operation

2020·018,019,020

709

CPU to CPU

CLEAR (Empty) FIFO Operation. The CLEAR

Operation

FIFO bit (active Low) clears the FIFO buffer of
data. Writing a 0 to this bit empties the FIFO
buffer, inactivates the REQUEST line, and
disables the handshake (if programmed). The
CLEAR bit does not affect any control or data
register. To remove the CLEAR state, write a 1
to the CLEAR bit.
In CPU/CPU mode, under program control,
only one of the ports can empty the FIFO by
writing to its Control Register 3, bit 6. The
Port 1 CPU must program bit 7 in Control
Register 3 to determine which port controls the
CLEAR FIFO operation (0 = Port 1 control;
I = Port 2 control).
Direction of Data Transfer Operation. The

(Continued)

Data Direction bit controls the direction of data
transfer in the FIFO buffer. The Data Direction
bit is defined as 0 = output from CPU and
I = input to CPU. This bit reads correctly
when read by either port's CPU. For example,
if Port l's CPU reads a 0 (CPU output) in its
Data Direction bit, then Port 2's CPU reads a I
(input to CPU) in its Data Direction bit.
In CPU/CPU mode, under program control,
only one of the ports can control the direction
of data transfer. The Port 1 CPU must program
bit 5 in Control Register 3 to determine which
port controls the data direction (0 = Port I
control; I = Port 2 control). Figure 20 shows
FlO data transfer options.

(PROGRAM REGISTERS FOR OPERATING MODE,

PORT 2 CONFIGURATION, DATA TRANSFER CONTROL, ETC.)

PORT 1 (CPU)

PORT 2 (CPU)

PORT 2 (110)

(DMA OR INTERRUPT·
DRIVEN TRANSFERS, AS
FOR POAT 1)

TRANSFERS DATA BYTE·
AT·A-TIME UNTil

I
I
I

Full OR Empty

t

t

EXCHANGE BYTES
VIA MESSAGE REGISTER

TERMINATES ON ANY
OF THESE CONDITION$:

TERMINATES ON ANY
Of THESE CONDITIONS:

"DMA BLOCK LENGTH REGISTER", 0
·FIO PAnSAN MATCH INTERRUPT
"BYTE COUNT DISABLES REQ

·CPU COMPLETES BUFFER DUMP
·FIO PAnERN MATCH INTERRUPT
"FlO BYTE COUNT INTERRUPT
-FlO Full I Empty INTERRUPT

I

I

I

l"

'y/

I
I
I
I
I

I
I
I
I
I

//)
"'-,

FIFO BUFFER IS

/'"

I

I
EXCHANGE BYTES
VIA MESSAGE REGISTERS
---~--

... - - - -

\

I

Y
I
I

I
I
I

I
I

I
I
I

I
I
I
I

CONTINUE OR REPROGRAM PORT REGISTERS WITH NEW BLOCKS OF CONTROL BYTES.

Figura 20. FlO Data TraDSfar Options

710

2020-021

CPU to I/O
Operation

When Port 2 is programmed in the Interlocked 2-Wire Handshake mode or the 3-Wire
Handshake mode, and Port A is programmed
in Z-BUS or non-Z-BUS Microprocessor mode,
the FlO interfaces a CPU and a peripheral
device. In the Interlocked 2-Wire Handshake
mode, RFD/DAVand ACKIN strobe data to
and from Port 2. In the 3-Wire Handshake
mode, RFD/DAV, DAVIDAC, and DAC/RFD
signals control data flow.

Interlocked 2-Wire Handshake. In the Interlocked Handshake, the action of the FlO must
be acknowledged by the other half of the
handshake before the next action can take
place. In output mode, Port 2 does not indicate
that new data is available until the external
device indicates it is ready for the data.
Similarly, in input mode, Port 2 does not indicate that it is ready for new data until the data
source indicates that the previous byte of the
data is no longer available, thereby acknowledging Port 2's acceptance of the last byte.
This allows the FlO to directly interface to a
Z8's port, a CIO's port, a UPC's port, another
FlO port, or another FIFO Z8060, with no
external logic (Figures 21 and 22).
3-Wire Handshake. The 3-Wire Handshake is
designed for applications in which one output
port is communicating with many input ports
simultaneously. It is essentially the same as the
Interlocked Handshake, except that two signals
are used to indicate that an input port is ready
for new data or that it has accepted the present
data. In the 3-Wire Handshake, the rising
edge of the RFD status line indicates that the
port is ready for data, and the rising edge of
the DAC status line indicates that the data has
been accepted. With 3-Wire Handshake, the
lines of many input ports can be bussed
together with open-drain drivers and the out-

put pori knows when all of the ports are ready
and have accepted the data. This handshake is
the same handshake used in the IEEE-488
Instruments. Since the port's direction can be
changed under software control, bidirectional
IEEE-488-type transfers can be performed.
Figures 23 and 24 show the timings associated
with 3-Wire Handshake communications.

CLEAR FIFO Operation. In CPU-to-I/O
operation, the CLEAR FIFO operation can be
performed by the CPU side (Port 1) under software control as previously explained. The
CLEAR FIFO operation can also be performed
under hardware control by defining the
CLEAR pin of Port 2 as an input (Control
Register 3, bit 7 = 1).
For cascading purposes, the CLEAR pin can
also be defined as an output (Control Register
3, bit 7 = 0), which reflects the current state
of the CLEAR FIFO bit. It can then empty
other FIOs or initialize other devices in the
system.
Data Direction Control. In CPU-to-I/O mode,
the direction of data transfer can be controlled
by the CPU side (Port 1) under software control as previously explained. The data direction can also be determined by hardware control by defining the Data Direction pin
of Port 2 as an input (Control Register 3,
bit 5 = 1).
For cascading purposes, the Data Direction
pin can also be defined as an output (Control
Register 3, bit 5 = 0) pin which reflects the
current state of the Data Direction bit. It can
then be used to control the direction of data
transfer for other FIOs or for external logic.
On the Port 2 side, when data direction is 0,
Port 2 is in Output Handshake mode. When
data direction is 1, Port 2 is in Input Handshake mode.

711

CPU to I/O
Operation
(Continued)

DATA IN

=::x

VALID DATA

\

ACKU.

X
I

X

X
'----l
VALID DATA

IIPD

Figure 21. Interlocked Handshake Timing (Input) Port 2 Side Only

DATA OUT

=::x

VALID DATA

X"'__....JX

VALID DATA

XIo..____

~

,'-_---J!

DAV - - " " ' \ ' , -_ _~/r-----.'----l

Figure 22. Interlocked Handshake Timing (Output) Port 2 Side Only

DATA IN

Rtu~

=:)(

J

\
\

D~:

x:::=::x

VALID DATA

!

VALID DATA

X"'____

''''_____

I

'----/

OUT ______________- - '
DAC

Figure 23. Input (Acceptor) TlmlnglEEE·488 HS Port. Port 2 Sid. Only

DATA OUT

DAV
OUT

=:)(

X

VALID DATA

\

X

VALID DATA

X

'--J

I

OAC
IN
AFI:

--.r--\

I

\

Figure 24. Output (Source) TlmlnglEEE·488 HS Port. Port 2 Side Only

712

2020·023, 024, 025

Programming

The programming of the FlO is greatly
simplified by the efficient grouping of the
various operation modes in the control
registers. Since all of the control registers are
read/write, the need for maintaining their
image in system memory is eliminated. Also,
the read/write feature of the registers aids in
system debugging.
Each side of the FlO has 16 registers. All 16
registers are used by the Port 1 side; Control
register 2 is not used on the Port 2 side. All
registers are addressable 0H through FH.
In the Z-BUS Low Byte mode, the FlO allows
two methods for register addressing under control of the Right Justify Address (RJA) bit in
Control register 0. When RJA = 0, address
bus bits 1-4 are used for register addressing
and bits 1, 5, 6, and 7 are ignored (Table 4).
When RIA = 1, bits 0-3 are used for the
register addresses, and bits 4-7 are ignored.
Control Registers. These four registers specify
FlO operation. The Port 2 side control
NonZ-BUS

°

Interrupt Status Registers. These four
registers control and monitor the priority
interrupt functions for the FlO.
Interrupt Vector Register. This register stores
the interrupt service routine address. This vector is placed on Do-D7 when IUS is set by the
Interrupt Acknowledge signal from the CPU.
When bit 4 (Vector Includes Status) is set in
Control Register 0, the reason for the interrupt
is encoded within the vector address in bits I,
2, and 3. If bit 5 is set in Control register 0, no
vector is output by the FlO during an Interrupt
Acknowledge cycle. However, IUS is set as
usual.

•

S

Da

-'3

~

Al

Au

Ao,-ADs
AD,-ADc

ADc
ADa

ADa

AD2
ADI

ADI
ADo

ADo

x

0
0

x
x
x

0

x
x

D2

~

DI

DO

Description
Control Register 0
Control Register 1
Interrupt Status RegIster 0

x
x

0
0
0

0
0
0

0
0

Interrupt Status RegIster 1

x

0

0

1

Interrupt Status Register 2
Interrupt Status RegIster 3

x
x

0

Interrupt Vector RegIster
Byte Count RegIster

x
x

0
0

0
0
0

x

Control RegIster 2'

x

0
0

x

0
0

Message In RegIster

x
x

Pattern Match Register

x

Pattern Mask RegIster

x
x

Data Buffer Register

I

x
0

Byte Count ComparIson
RegIster
Control Register 3
Message Out RegIster

0

0

x
x
x
x

0
0

x

0

x
x

x
0

0

1
0

x
x

x = Don't Care
*Register

IS

I
N

o,-Dc

Z-BUS High
Z-BUS Low { RJA=O
RIA = I

registers operate only if the Port 2 device is a
CPU. The Port 2 CPU can control interface
operations, including data direction, only
when enabled by the setting of bit in the Port
1 side of Control Register 2. A 1 in bit 1 of the
same register enables the handshake logic.

only on Port 1 sIde

Table 4_ flO Register Address Summary

713

Programming Byte Count Compare Register. This register

(Continued)

contains a value compared with the byte count
in the Byte Count register. If the Byte Count
Compare interrupt is enabled, an interrupt will
occur upon compare.
Message Out Register. Either CPU can place
a message in its Message Out register. If the

opposite side Message register interrupt is
enabled, the receiving side CPU will receive
an interrupt request, advising that a message
is present in its Message In register. Bit 5 in
Control Register I on the initiating side is set
when a message is written. It is cleared when
the message is read by the receiving CPU.
Message In Register. This register receives a

message placed in the Message Out register by
the opposite side CPU.
Pattern Match Register. This register contains

a bit pattern matched against the byte in the

Data Buffer register. When these patterns
match, a Pattern Match interrupt will be
generated, if previously enabled.
Pattern Mask Register. The Pattern Mask

register may be programmed with a bit pattern
mask that limits comparable bits in the Pattern
Match register to non-masked bits (1 = mask).
Data Buffer Register. This register contains

the data to be read from or written to the
FIFO buffer.
Byte Count Register. This is a read-only

register, containing the byte count for the
FIFO buffer. The byte count is derived by subtracting the number of bytes read from the buffer from the number of bytes written into the
buffer. The count is "frozen" for an accurate
reading by setting bit 6 (Freeze Status register)
in Control Register 1. This bit is cleared when
the Byte Count register read is completed.
Z·BUS

TO
COMM.
LINE

Z·BUS

MASTER
CPU

NOTES:
1. Data from master CPU - Z-FIO Port 2.

2. Z-FIO Port 1 -DCP.
3. DCP -RAM.
4. RAM -Z-SCC.
S. Z-SCC - data comm. lme loop.

Figure 25. Typical Application: Node Controller

714

2020-026

Registers

Control Register 2*
Address: 1001
(ReadlWrite)
I~I~I~I~I~I~I~I~I

I

~ ;::RTAT ISIDEENABLED
2 SIDE ENAILE

'THIS A

BITS 2-7 NOT UB

0'8 FRg:'roERTR READS ALL

HANDSHAKE

MUST BE PROO":'MED.

ZSIDE

Control Register a
Address: 1010
(ReadlWrite)

Control Register I
Address: 0001
(ReadlWrite)

'·'·lnT~==..=-~~. I
•

11 ~:::~ESTIWAifENABLED
L

10,10,10,10.1010 I

~~
' I'

1

=

DATA DtRee

UT LIN!; (PIN 30)'"

~:~:f~UW~.rT
OM

-=====--- °
•

REQUEST

0", PORT 1 SID:

1 - START DMA ON
1 = STOP DMA ON PBYTE COUNT
1 .. MESSA
AnERN MATCH

1 = PORT 2 SIDE

L

1 '"' M
GE MAILBOX REGISTE
1
ESSAGE MAILBOX AEGIS A UNDEA SEAVICE'
'"' FREEZE STATU

'AEAD ONLY BITS

PORT 2 8IDE-o'::E PROGRAMMED 0)

,~EAI).()NLY Brrs

TEFl FULL-

ONLY WHEN PO

NOT USED IMUST BE
5 PROGRAMMED
AEGISTEA COUNT
0)

CPU

=:~t: DATADlREC110N

0= CLEAR FIFO BUFFER

",PORT 1 SIDE co
1 = PORT 2 SIDE CONTROLS CLEAR

AT 21S AN 110 PORT

NTROLS

•...,..at...

Figure 26, Control ,,--

Interrupt Status Reglst
Address: 0010 er 0
(ReadIWrite)
ID,ID.ID.ID.I~ID

I

III L:!"
I

I

I

:OT USED
~UST BE PROGRAMMED 0)

ESSAGE IHTERRU PT PENDING (lP)

MESSAGE INTER

M

RUPT ENABlE

IUS. IE, AND I.
ESSAGE INTERRUPT U
PEl
THE FOLLOWIN:RioWFimEN USING
NDER SERVICE (IUS)

o

NULL CODE

MMAND:

CLEAR IP a IUS
seT IUS
CLEAR IUS

SET IP

Figure'D, Inl..rupl Slalus RegiBl...

2020-027,028

715

i

Registers

Interrupt Status Register 1
Address: 0011
(ReadlWrite)

(Continued)

DATA DIRECTION CHANGE INTERRUPT
UNDER SERVICE (IUS)

DATA DIRECTION CHANGE INTERRUPT
ENABLE (IE)
DATA DIRECTION CHANOE INTERRUPT

jJ I II' L
~

I

I
I
I

I
,

I

PENDING (IP)

= PATTERN MATCH FLAG·

I

I

I

I

UNDER SERVICE (IUS)

L:'-:'-:'-_

IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:

1

PATTERN MATCH INTERRUPT PENDING (lP)
PATTERN MATCH INTERRUPT ENABLED (IE)
PATTERN MATCH INTERRUPT
NOT USED
(MUST BE PROGRAMMED 0)

IUS,IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:

0
0
0

0
1
1

SETIP
CLEAR IP

1

0

1

SET IE

1

0
1

CLEAR IE

1

1

CLEAR IP 6 IUS
SET IUS
CLEAR IUS

0

0

0
0

1

0

1

0
1

1

0
1

1

1

1

0

NULL CODE

CLEAR IP 6 'US
SET IUS

1

CLEAR IUS

0

SET IP

CLEAR IP
SET IE

1

CLEAR IE

-READ-ONLY BITS

Interrupt Status Register 2
Address: 0100
(ReadlWrlte)

BYTE COUNT COMPARE INTERRUPT
UNDER SERVICE (IUS)

BYTE COUNT COMPARE INTERRUPT
ENABLE (IE)
BYTE COUNT COMPARE INTERRUPT
PENDING (lP)

iJ I ~~
L

L UNDERFLOW ERROR·

I

I
I

I

I

I
I

ERROFlINTERFlUPT PENDING (IP)

I

ERROR INTERRUPT ENABLED (IE)

I

I

ERROR INTERRUPT UNDER SERVICE (IUS)

I

I

OVERFLOW ERRORIUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:

IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
NULL CODE

0

0

0

o

0

0

NULL CODE

a IUS

0
0

0
1

1
0

o

0

1

CLEAR IP

o

1
0

1
0

o

0
1

SET IUS

0
1

1
1
0
0

SET IE

0
1

1
1

0

1
1

CLEAR IE

1

1

1
1

1
1

CLEAR IP

SETIUS
CLEAR IUS
SETIP
CLEAR IP

1

a IUS

CLEAR IUS
SETIP
CLEAR IP
SET IE

1

CLEAR IE

·READ'()NLV BITS

Interrupt Status Register :I
Address: 0101
(ReadIWrite)

FULL INTERRUPT UNDER SERVICE (IUS)
FULL INTERRUPT ENABLE (IE)
FULL INTERRUPT PENDING (lP)

~
:U I ~
I

I

I

I

IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:

SET IUS

0
0

0
1

CLEAR IUS

0

1
0
0

SETIP
CLEAR IP
SETIE
CLEAR IE

1
1

1
1

EMPTY INTERRUPT PENDING (IP)

I

I

I

I

I

o
o

0

0

NULL CODE

0

1

CLEARIP61US

NULL CODe:
CLEAR IP 6 IUS

BUFFER EMPTY·
EMPTY INTERRUPT ENABLE (IE)
EMPTV INTERRUPT UNDER SIRVICE (lUI)
BUFFER FULL-

IUS. IE. AND III ARE WRITTEN USING
THE FOLLOWING COMMAND:

1
0

SET IUS
CLEAR IUS

1

1
1

0
0

0
1

1

1

0

SETIE

1

1

1

CLEAR IE

IETIP
CLEARIP

-REAo.oNLV BITS

Figure 27. Interrupt Status Regl8ten (Continued)

716

2020·028

Registers
(Continued)

Byte Count Register
Address: 0111
(Read Only)

Interrupt Vector Register
Address: 0110
(ReadlWrite)

I~I~I~I~I~I~I~I~I

I I I

I I I I I II I
REFLECTS NUMBER OF BYTES IN BUFFER

NO INTERRUPTS PENDING

Figure 28. Byte Count Register
VECTOR STATUS

1

o

0

0

BUFFER EMPTY

o

1

BUFFER FULL

1

0

OVER/UNDERFLOW ERROR

o

1

BYTe COUNT MATCH

1

0

PATTERN MATCH

1

0

1

DATA DIRECTION CHANGE

1

1

0

MAILBOX MESSAGE

1

1

1

Figure 29. Interrupt Vector Register

Pattern Match Register
Address: II aI
(ReadIWnte)

Pattern Mask Register
Address: III a
(Read/Write)

ID,I D,I D, ID.lo,1 0, I0,10 I

I~I~I~I~I~I~I~I~I

0

II I I I I I I
STORES BYTE COMPARED WITH
BYTE IN DATA BUFFER REGISTER

I I I I I II I
IF SET, BITS ().7 MASK BITS 0 7
IN PATTERN MATCH REGISTER
MATCH OCCURS WHEN ALL
NON·MASKED BITS AGREE

Figure 30. Pattern Match Register
Figure 31. Pattern Mask Register

Data Buffer Register
Address: IIII
(Read/Write)
I~I~I~I~I~I~I~I~I

IIIIIIII
CONTAINS THE BYTE TRANSFERRED
TO OR FROM FIFO BUFFER RAM

Byte Count Comparison Register
Address: 1000
(ReadlWrite)
I~I~I~I~I~I~I~I~'

11111111
CONTAINS VALUE COMPARED TO BYTE COUNT
REGISTER TO Issue INTERRUPTS ON MATCH
(BIT 7 ALWAYS 0.)

Figure 32. Data Buffer Register

Figure 33. Byte Count Comparison Register

Message Out Register
Address: 1011
(Read/Write)

Message In Register
Address: 1100
(Read Only)

'~I~I~I~I~I~I~I~I

11111111
STORES MESSAGE SENT TO MESSAGE

IN REGISTER ON OPPOSITE PORT OF FlO

Figure 34. Message Out Register

2020-029,030,031,032,033,034,035,036

10, I 0.1 0,10.10,10, I 0, 10.'
1\ I I I I I I
STORES MESSAGE RECEIVED FROM MESSAGE
OUT REGISTER ON OPPOSITE PORT OF CPU

Figure 35. Message In Register

717

Absolute
Maximum
Ratings

Voltages on all pins with respect
toGND ................... -0.3Vto +7.0V
Operating Ambient
Temperature ....... See Ordering Information
Storage Temperature ........ - 65°C to + 150°C

Stresses greater than those listed under Absolute Mal"mum Ratings may cause permanent damage to the devIce.

This is a stress ratmg only; operation of the device at any
condition above those indicated In the operational sections
of these specifications 18 not Imphed. Exposure to absolute
maximum rating conditions for extended periods may affect

devIce reliability.

Standard
Test
Conditions

The DC characteristics and capacitance sections below apply for the following standard test
conditions, unless otherwise noted. All voltages
are referenced to GND. Positive current flows
into the referenced pin.
Standard conditions are as follows:

The Ordering Information section lists temperature ranges and product numbers. Package
drawings are in the Package Information section
in this book. Refer to the Literature List for additional documentation.

• +4.75 V :S Vee :S +5.25 V
• GND = 0 V
• TA as specified in Ordering Information
+5V
2.2K

+5V

FROM OUTPUT
UNDER TEST

~ 2.2K
1

50P
•

Standard Test Load
DC
Characteristics

Symbol

VIH
VIL
VOH

V~L
IlL

1m
ILM
ICC

Open-Drain Test Load

Parameter

Min

Max

Unit

Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage

2.0
-0.3
2.4

Vcc +0.3
0.8

V
V
V
V
V
".A

Input Leakage
Output Leakage
Mode Pins Input Leakage
(Pms 19 and 21)
Vee Supply Current

-10.0
-10.0
-100

0.4
0.5
+ 10.0
+ 10.0
+ 10.0

p.A
p.A

200

rnA

Condition

10H = - 250 p.A
10L = +2.0 rnA
101 = +3.2 rnA
0.4 :s VIN :s + 2.4V
0.4 :s VOUT :s + 2.4V
0< VIN < Vee

Vee = 5 V ± 5% unless otherwlse specIfied, over speclhed temperature range.

Capacitance

Symbol

C IN
COUT

CvO

Parameter

Input Capacitance
Output Capacitance
Bidirectional Capacitance

Min

Max

Unit

10
15
20

pi
pi
pi

100
100

ns
ns

Condition

Unmeasured pms returned to ground.

Inputs

tr
tf

Any Input Rise Time
Any Input Fall Time

f = 1 MHz, over specihed temperature range.

718

8085·0209.0002

AC Characteristics
No.

Symbol

Parameter

Min

4 MHz
Max

TwAS
AS Low Width
I
70
2
TsA(AS)
Address to AS t Setup Time
30
3
ThA(AS)
Address to AS t Hold Time
50
4
TsCSO(AS)
CS to AS t Setup Time
0
---- 60
5 - ThCSO(AS) CS to AS t Hold Time - - - 6
TdAS(DS)
AS t to DS t Delay
60
7
TsA(DS)
Address to DS I (with AS t to DS I = 60 ns)
120
8
TsRWR(DS)
RJW (Read) to DS I Setup Time
100
9
TsRWW(DS)
RJW (Write) to DS I Setup Time
0
10 -TwDS - - - - DS Low Width - - - - - - - - - - - - - 390
II
TsDW(DSf)
Write Data to DS I Setup Time
30
12 TdDS(DRV)
DS (Read) I to Address Data Bus Driven
0
13 TdDSf(DR)
DS I to Read Data Vahd Delay
14 ThDW(DS)
Write Data to DS f Hold Time
30
15 - TdDSr(DR) - - DS f to Read Data Not Vahd Delay - - - - - - - 0
16 TdDS(DRz)
DS f to Read Data Float Delay
17
ThRW(DS)
R/Wto DS f Hold Time
55
18 TdDS(AS)
DS f to AS I Delay
50
19
Trc
Vahd Access Recovery Time
1000

6 MHz
Min

Max

Notes*t

50
10

30
0
-40
40
100
80
0
250
20
0
250

--1-

N

00
W
00

180

0

20
0
70

45
40
25
650

2

lilt

0
3

NmES.
1. Parameter does not apply to Interrupt Acknowledge transactIons.
2. Float delay IS measured to the hme when the output has
changed. O.5V from steady state wIth minimum ae load and
maxImum de load.

This 16 the delay from iSS of one FlO access to OS of another FlO
access (either read or write).
* All hmmg references assume 2 OV for a logic "1/1 and 0 BV for
a logic "0" All hmmgs are prellmmary and subject to change
t Umts In nanoseconds (ns)

R/W ----+i-T---+---------+"""'le---------REA.

-----+-1-'

..,.
WftlTE

ADo_ AD

====]===~~t---=_---1=~=3E==:::r--

1·1 ;~~::..
PIO
READ

_ _ _ _ _ _ _ _ _ _-j-=~~-~~~~~~~---------

Figure 36. Z-BUS CPU Interface Timing

2020-037

N
•
IIJ

719

AC Characteristics
4 MHz
No.

Symbol

Parameter

Min

Max

TsIA(AS)
INTACK to AS t Setup Time
20
0
21
ThIA(AS)
INTACK to AS t Hold Time
250
TsDSA(DR)
OS (Acknowledge) I to Read Data Valid Delay
250
22
23
TwDSA
OS (Acknowledge) Low Width
390
24- TdAS(IEO)-- AS t to lEO I Delay (INTACK C y c l e ) - - - - - - - - 350
25
TdlEl(IEO)
lEI to lEO Delay
150
26
TslEl(DSA)
lEI to OS (Acknowledge) I Setup Time
100
ThIEI(DSA)
lEI to OS (Acknowledge) t Hold Time
27
50
TdDS(INT)
OS (INTACK Cycle) to INT Delay
900
28
Interrupt Daisy Chain Sellle Time
29
TdDCST
NOTES:
4 The parameters for the devlces many parhcular da~ ch~
must meet the followmg constramt: The delay from AS to DS
must be greater than the sum of TdAS(IEO) for the hIghest
pnonty peripheral, TsIEI(DSA) for the lowest prlOfity perlpheral

ADo-AD-,

6 MHz
Min

Max

Notes*t

0
250
180
250
250 - - - 4 100
4
70
30

4

800
4

and TdIEI(IEO) for each peripheral, separatmg them m the
chain.
* Tlmmgs are prelImmary and subject to change.

t Umts

In

nanoseconds (ns),

UNDEFINED

lEI

lEO

Figure 37. Z·BUS CPU Interrupt Acknowledge Timing

720

2020-038

AC Characteristics
No.

Symbol

Parameter

Min

4 MHz
Max

6 MHz
Min
Max

30

TdMW(INT)
Message Write to !NT Delay
TdDC(INT)
Data Direction Change to INT Delay
TdPMW(INT)
Pattern Match to INT Delay (Write Case)
32
33
TdPMR(lNT)
Pattern Match (Read Case) to !NT Delay
34-TdSC(INT)--Status Compare to INT D e l a y - - - - - - - - - - - -

5
6

31

35
36
37

38

TdER(INT)
TdEM(INT)
TdFL(!NT)
TdAS(lNT)

----6-

Error to INT Delay
Empty to INT Delay
Full to INT Delay
AS to INT Delay

6
6

NOTES.
5. Write IS from the other side of FlO.
6. Write can be from either side, dependmg on programmmg
of FlO.

MEaSAGIl
WRITE

DATA
DIRI!CTION
CHANGE

..-{

Notes*t

* Timings are prehmmary and subject to change

t Umts equal to AS Cycles + ns.

OS'

WRITE

"

MESSAGE
REGISTER
OUT

OS'

WRITE
CONTROL
REGISTER 3

WRITE DATA

OS

BUFFER
REGISTER

MATCH

READ DATA
BUFFER
REGISTER

OS

STATUS
COMPARE

WRITE OR READ
DATA BUFFER
REGISTER

Os'

BAROA

WRITE OR READ

34

- - - - " " ' " 1_---{35i}--_-..,~

OS

DATA BUFFER
REGISTER
i------{~i}-----_J

EMPTY

READ DATA
BUFFER

REGISTER

i------{,jD------i
PULl.

WRITE DATA
BUFFER
REGISTER

Ai

1-------(J8}-------I
INT

Figure 38. Z-BUS Interrupt Timing

2020·039

721

AC Characteristics
No.

Symbol

I
2
3
45
6
7
89
10
II
12

TdDS(WAIT)
AS t to WAIT j Delay
TdDSI(WAlT)
DSI t to WAIT t Delay
TdACK(WAIT) ACKIN j to WAIT t Delay
TdDS(REO) - - DS j to REO t Delay
,
TdDMA(REO)
DMASTB j to REO t Delay
TdDSI(REO)
DSI t to REO j Delay
TdACK(REO)
ACKIN j to REO j Delay
TdSU(DMA) - - Data Setup T,me to DMASTB - - - - - - - ,
TdH(DMA)
Data Hold T,me to DMASTB
TdDMA(DR)
DMASTB j to Vahd Data
TdDMA(DRH)
DMASTB t to Data Not Vahd
TdDMA(DR2)
DMASTB t to Data Bus Float

Parameter

Min

NOTES
1 The delay IS from DAV for 3-Wlre Input Handshake The delay
IS from DAC for 3-Wlre Handshake

4 MHz
Max

6 MHz
Min
Max

190
1000
1000
350
350
1000
1000

160
1000
1000
300
300
1000
1000

200
30

Notes*t

150
20
100

150
0

0
70

45

* Tlmmgs are prehmmary and subject to change.
In nanoseconds (ns)

t Umts

Ai
Di
READ/WRITE

DATA
BUFFER

BY OTHER SIDE

REGISTER

DSI
WRITE/READ
BY OTHER SIDE

REGISTER

DATA
BUFFER

J

r---w--

\

WAIT

ACKIN

,

~

J

INPUTI

\

OUTPUT

PORT

---r

<

MASTER

PORT

COMMANDS

s~~~~

CIPHER TEXT}I
~

Y

PERIPHERAL

DEVICE OR

I

BUFFER

ENCRYPT AND DECRYPT
KEYS CLEAR TEXT

Figure 5b. Dual-Port Configuration. Direct Control
2080·004, 005, 006

i

DCP

STATUS

COMMANDS ~

I

)

COMMANDS

ENCRYPT AND DECRYPT

Single-Port Configuration. The simplest configuration occurs when the Mode register con-

SYSTEM

)

Figure 4. Single-Port Configuration. Multiplexed Control

Data Flow. Bits M2 and M3 of the Mode
.egister control the flow of data into and out of
the DCP through the master and slave ports.
Three basic configurations are provided: one
single-port and two dual-port.

A

MASTER KEY

COMMANDS
ENCRYPT AND DECRYPT
KEYS, CLEAR TEXT
CIPHER TEXT

Operating Modes: Multiplexed Control VB.
Direct Control. The DCP can be operated in
either of two basic interfacing modes, determined by the logic level on the CIK input pin.
In Multiplexed Control mode (C/K Low), the
DCP is configured internally to allow a master
CPU to address five of the internal control/status/data registers directly, thereby controlling the device via mode and command
values written to these registers. Also, in this
mode, the auxiliary port is enabled for keybyte input.
If the logic level on C/K is brought High,
the DCP enters Direct Control mode, and the
auxiliary port pins are converted into direct
hardware status or control signals capable of
instructing the DCP to perform a functionally
complete subset of its cipher processing at
very high throughputs. This operating mode is
particularly well suited for Ciphering data for
high-speed peripheral devices such as
magnetic disk or tape.

HIGH SPEED
MICROPROGRAMMED
DEVICE

:r

AUXILIARY
PORT
PU:US

743

I

Functional
Description
(Continued)

When an encrypted key is entered, the
parity-check logic operates only after the
decrypted key is available. The encrypted data
is not checked for parity. The PAR signal
reflects the state of the decrypted bytes on a
byte-to-byte basis as they are clocked through

the parity-check logic on their way to the key
register. Thus, the time during which PAR
indicates the status of a byte of decrypted key
data may be as short as four clock cycles. The
LPAR bit in the Status register indicates if any
erroneous bytes of key data were entered.

Programming

Initialization. The DCP can be reset in
several ways:

Code

Hex

• By the "Software Reset" command.
• By a hardware reset, which occurs
whenever both MAS and MDS go Low
simultaneously.
• By writing to the Mode register.
• By aborting any command.
These sequences initiate the same internal
operations, except that loading the Mode
register or aborting any command does not
subsequently reset the Mode register. Once a
reset process starts, the DCP is unable to
respond to further commands for approximately five clock cycles. If a power-up hardware
reset is used, the leading edge of the reset
signal should not occur until approximately I
ms after Vee has reached normal operating
voltage. This delay time is needed for internal
signals to stabilize.
Registers. The registers in the DCP that can
be addressed directly through the master port
are shown with their addresses in Table 2. A
brief description of these registers and those
not directly accessible follows.
C/K MP2 MPI MR/W MCS Register Addressed
0
X
0
0
0 Input Register
X
I
0
0
0 Output Register
0
0
I
0
0 Command RegIster
0
I
0
I
0 Status Register
I
0
0 Mode Register
I
X
X
X
X
I No Register Accessed
X
X
0
0 Input Register
I
X
0 Output Register
I
X
X
I
Table 2. Master Port Register Addresses

CIK

AU~-K/D

H
H
H
H
H
H
H
L

L
L
L
t
t
I
H
Data

Pins
AUXa-ElD
L
H
X
L
H
X
X
Data

Command

90
91
92
II
12
BI
B2
31
32

Load Clear M Key Through Auxiliary Port
Load Clear E Key Through Auxiliary Port
Load Clear D Key Through Auxiliary Port
Load Clear E Key Through Master Port
Load Clear D Key Through Master Port
Load Encrypted E Key Through AUXiliary Port
Load Encrypted D Key Through AUXiliary Port
Load Encrypted E Key Through Master Port
Load Encrypted D Key Through Master Port

85
84
A5
A4

Load Clear IVE Through Master Port
Load Clear IVD Through Master Port
Load Encrypted IVE Through Master Port
Load Encrypted IVD Through Master Port

8D
8C
A9
A8

Read
Read
Read
Read

39
41
40
CO
EO
00

Encrypt With Master Key
Start Encryption
Start Decryption
Start
Stop
Software Reset

Clear IVE Through Master Port
Clear IVD Through Master Port
Encrypted IVE Through Master Port
Encrypted IVD Through Master Port

Table 3. Command Codes in Multiplexed Control Mode

Command Register. Data written to the 8-bit,
write-only Command register through the
master port is interpreted as an instruction. A
detailed description of each command is given
in the Commands section; the commands
and their hexadecimal representations are
summarized in Table 3. A subset of these
commands can be entered impliCitly in Direct
Control mode (C/K High)-even though the
Command register cannot be addressed in that
mode-by transitions on auxiliary lines
AUXs-S/S, AUXs-E/D, and AUX7-K/D. These
implicit commands are summarized in Table 4.

Auxs-S/s Command Initiated
Start Decryption
t
Start Encryption
t
I
Stop
Load D Key Clear through master port
L
Load E Key Clear through master port
L
L
End Load Key command
Not allowed
H
AUX pins become Key-Byte inputs
Data

Table 4. Implicit Command Sequences in Direct Control Mode

744

Functional
Description
(Continued)

through the master port. Slave port and clear
text read from the Master port.
In both dual-port configurations, the Master
Port Flag (MFLG) and the Slave Port Flag
(SFLG) are used to indicate the status of the
data register associated with the master port
and slave port, respectively. For example, during encryption in the master port clear configuration, MFLG goes Low (active) when the
Input register is not full; SFLG goes Low
(active) when the Output register is not empty.
If cyphering operation changes direction,
MFLG and SFLG switch their register association (see Table 1).
Mode Register Bits
Encryptl
Port
Decrypt Configuration
Bit Mt Bit M3 Bit M2

a
a
a
I
I
I

a
a
I
a
a
I

a
1
a
a
I

a

Input
Register
Flag

Output
Register
Flag
SFLG
MFLG
SFLG
MFLG
SFLG
SFLG

Table I. Association of Master Port Flag (MFLG)
and Slave Port Flag (SFLG)
with Input and Output Registe..

Dual Port, Slave Port Clear Configuration.
This configuration is identical to the previously
described dual-port, master port clear configuration except that the direction of ciphering is reversed. That is, all data flowing in or
out of the master port is Cipher text, and all
data at the slave port is clear text.
Master Port Read/Write Timing. The master
port of the DCP is designed to operate directly
with a multiplexed address/data bus such as
the Zilog Z-BUS. Several features of the master
port logic are:
• The level on Master Port Chip Select (MCS)
is latched internally on the riSing (trailing)
edge of Master Port Address Strobe (MAS).
This action relieves external address decode
circuitry of the responsibility for latching
chip select at address time.
• The levels on MPJ and MP2 are also latched
internally on the rising edge of MAS and
are subsequently decoded to enable reading
and writing of the DCP's internal registers
(Mode, Command, Status, Input and Output). This action also eliminates the need for
external address latching and decoding.
• Data transfers through the master port are
controlled by the levels and transitions on
Master Port Data Strobe (MDS) and Master
Port ReadlWrite (MRlW). The former controls the timing and the latter controls the
transfer direction. Data transfers disturb
neither the chip-select nor address latches,

so once the DCP and a particular register
have been selected, any number of reads or
writes of that register can be accomplished
without intervening address cycles. ThiS
feature greatly speeds up the loading of
keys and data, given the necessary transfer
control external to the DCP.
Loading Keys and Initializing Vector (IV)
Registers. Because the key and InitialiZing
Vector (IV) registers are not directly
addressable through any of the DCP's ports,
keys and vector data must be loaded (and in
the case of vectors, read) via "command data
sequences." Most of the commands recognized
by the DCP are of this type. A load or read
command is written to the Command register
through the master port. The command processor responds by asserting the Command
Pending output. The user then either writes
eight bytes of key or vector data through the
master or auxiliary port, as appropriate to the
specific command, or reads eight bytes of vector data from the master port.
In Direct Control mode, only the E Key and
D Key registers can be loaded; the M Key and
IV registers are inaccessible. Loading the E
and D Key registers is accomplished by placing the proper state on the AUXs-EiD input
(High for E Key, Low for D Key) and then raising the AUX7-K/D input-indicating that key
loading is required. The command processor
attaches the proper key register to the master
port and asserts the AUXa-CP (Command
Pending) signal (active Low). The eight key
bytes can then be written to the master port. In
the Multiplexed Control mode, all key and
vector registers can be written to and all but
the Master (M) Key register can be loaded with
encrypted, as well as clear, data. If the operation is a Load Encrypt command, the subsequent data written to the master or auxiliary
port (as appropriate) is routed hrst to the Input
register and decrypted before it is written into
the specified key or Initializing Vector
register.
Parity Checking of Keys. Key bytes contain
seven bits of key information and one parity
bit. By DES designation, the low-order bit is
the parity bit. The parity-check cirCUit is
enabled whenever a byte is written to one of
three key registers. The output of the parltycheck circuit is connected to PAR and the
state of thiS signal is reflected in Status register
bit PAR (S3). Status register bit PAR goes to 1
whenever a byte with even parity (an even
number of Is) is detected. In addition to the
PAR bit, the Status register has a Latched Parity bit (LPAR, S4) that IS set to I whenever the
Status register PAR bit goes to J. Once set, the
LPAR bit is not cleared until a reset occurs or
a new Load Key command is issued.

745

I
i

Programming
(Continued)

Status Register. The bit assignments in the
read-only Status register are shown in Figure
6. The PAR, AFLG, SFLG and MFLG bits
indicate the status of the corresponding output
pins, as do the busy and command pending
bits when the DCP is in a Direct Control mode
(C/K: High). In each case, the output signal
will be active Low when the corresponding
status bit is a I. The parity bit indicates the
parity of the most recently entered key byte.
The LPAR bit indicates whether any key byte
with even parity has been encountered since
the last Reset or Load Key command.
The Busy bit is I whenever the ciphering
algorithm unit is actively encrypting or
decrypting data, either as a response to a command such as Load Encrypted Key (in which
case the Command Pending bit is I) or in the
ciphering of regular text (indicated by the
Start/Stop bit being!). If the ciphered data
cannot be transferred to the Output register
because that register still contains output from
a previous ciphering cycle, the Busy bit
remains I even after the Ciphering is complete.
Busy is 0 at all other times, even when ciphering is not possible because data has not been
written to the Input register.
The Command Pending bit is set to I by any
command whose execution requires the
transfer of data to or from a nonaddressable
internal register, such as when writing key
bytes to the E key register or reading bytes
from the IVE register. Thus, the Command
Pending bit is set following all commands ex-

cept the three start commands, the Stop command and the Software Reset command. The
Command Pending bit returns to 0 after all
eight bytes have been transferred following
Load Clear, Read Clear, or Read Encrypted
commands; and after data has been transferred, decrypted, and loaded into the desired
register following Load Encrypt commands.
The Start/Stop bit is set to I when one of the
start commands is entered and it is reset to 0
whenever a reset occurs or when a new command other than a Start is entered.

Mode Register. Bit assignments in this 5-bit
read/write register are shown in Figure 7. The
Cipher type bits (Mj and Mo) indicate to the
DCP which ciphering algorithm is to be used.
On reset, the Cipher Type mode defaults to
Electronic Code Book mode.
Configuration bits (M3 and M2) indicate
which data ports are to be associated with the
Input and Output registers and flags. When
these bits are set to the single-port, masteronly configuration (M3 M2 = 10), the slave
port is disabled and no manipulation of Slave
Port Chip Select (SCS) or Slave Data Strobe
(SDS) can result in data movement through the
slave port; all data transfers are accomplished
through the master port, as previously
described in the Functional Description. Both
MFLG and SFLG are used in this configuration; MFLG gives the status of the Input
register and SFLG gives the status of the Outpu t register.
When the configuration bits are set to one of
the dual-port configurations (M3 M2 = 00 or
01), both the master and slave ports are
available for input and output. When M3,
M2 = 01 (the default configuration), the
master port handles clear data while the slave
port handles encrypted data. Configuration

M3, M2 = 00 reverses this assignment. Actual
data direction at any particular moment is controlled by the Encrypt/Decrypt bit.
The Encrypt/Decrypt bit (M4) instructs the
DCP algorithm processor to encrypt or decrypt
the data from the Input register using the
ciphering method specified by the Cipher
Type bits. The Encrypt/Decrypt bit also controls data flow within the DCP. For example,
when the configuration bits are 0, I (dual-port,
master clear, slave encrypted) and the
Encrypt/Decrypt bit is I (encrypt), clear data
will flow into the DCP through the master port
and encrypted data will flow out through the
slave port. When the Encrypt/Decrypt bit is set
to 0 (decrypt), data flow is reversed.

E~

MASTER PORT FLAG

o '"

INACTIVE

1 == ACTIVE

SLAVE PORT FLAG
o '" INACTIVE
1 = ACTIVE
AUXILIARY PORT FLAG

o

= INACTIVE
1 == ACTIVE

PARITY (PAR)
o == 000 PARITY
1 == EVEN PARITY

L-----LPAR

o

== ALL BYTES HAD

000 PARITY

1 '" ONE OR MORE BYTES
HAD EVEN PARITY
' - - - - - - BUSY
o = NOT BUSY
1 '" BUSY
' - - - - - - - - COMMAND PENDING
o '" INACTIVE
1 '" ACTIVE
' - - - - - - - - START/STOP

o '"

STOP ENTERED

1 '" START ENTERED

Figure 6. Status Register Bit Assignments

RESERVED

T-C

o•
00 •
= ""
EL.ECTRONIC CODe BOOK (DEFAULT)
01 '" CIPHER FEEDBACK
10 = CIPHER BLOCK CHAIN
11 = RESERVED

PORT CONFIGURATION
00 '" DUAL PORT, MASTER

ENCRYPTED, SLAVE CLEAR
01 = DUAL PORT, MASTER CLEAR,
SLAVE ENCRYPTED (DEFAULT)
10 '" SINGLE PORT, MASTER ONI..Y
11 '" RESERVED

L...._ _ _ _ ENCRYPT/DECRYPT
1 = ENCRYPT

o '"

DECRYPT

Figure 7. Mode R"gister Bit Assignments

746

2080-007, 008

Programming
(Continued)

Commands

Input Register. The 64-blt, write-only Input
register is organized to appear to the user as
eight bytes of pushdown storage. A status circuit monitors the number of bytes that have
been stored. The register IS considered empty
when the data stored in It has been or is being
processed; It is considered full when one byte
of data has been entered m Cipher Feedback
mode or when eight bytes of data have been
entered in Electronic Code Book or Cipher
Block Chain mode. If the user attempts to write
data into the Input register when It IS full, the
Input register disregards the attempt; no data
m the register is destroyed.
Output Register. The 64-bit, read-only Output
register is organized to appear to the user as
eight bytes of pop-up storage. A status circuit
detects the number of bytes stored in the Output register. The register is considered empty
when all the data stored in it has been read by
the master CPU and is considered full if it still
contains one or more bytes of output data. If a
user attempts to read data from the Output
register when it is empty, the buffers driving
the output bus remain in a 3-state condition.
M. E. D Key Registers. The following
multibyte key registers cannot be addressed
directly, but are loaded in response to commands written to the Command register.
All operations of the DCP result from command inputs, whiCh are entered m Multiplexed
Control mode by writing a command byte to
the Command register. Command inputs are
entered in Direct Control mode by raising and
lowering the logic levels on the AUX7-K/D,
AUXs-E/D, and AUX5-S/S pins. Table 3 shows
all commands that can be given m Multiplexed
Control mode. Table 4 shows a subset of the
implicit commands that can be executed in the
Direct Control mode.

Load Clear M Key Through Auxiliary Port
(90H).

Load Clear E Key Through Auxiliary Port
(91H).

Load Clear D Key Through Auxiliary Port
(92H).

These commands may be used only for
multiplexed operations; they override the data
flow specifications set m the Mode register and
cause the Master (~ Key, Encrypt (E) Key, or
Decrypt (D) Key register to be loaded with
eight bytes written to the auxlhary port. After
the Load command is written to the Command
register, the AUXiliary Port Flag (AFLG) goes
active (Low) and the corresponding bit in the
Status register (S2) becomes I, indicating that
the device is able to accept key bytes at the
aUXiliary port pins. Additionally, the Command Pending bit (S6) becomes I durmg the
entire loading process.

There are three 64-bit, write-only key
registers in the DCP: the Master (M) Key
register, the Encrypt (E) key register, and the
Decrypt (D) key register. The Master key
register can be loaded only with clear data
through the auxiliary port. The Encrypt and
Decrypt Key registers can be loaded in any of
four ways: (I) as clear data through the auxiliary port, (2) as clear data through the master
port, (3) as encrypted data through the auxiliary port, or (4) as encrypted data through
the master port. In the last two cases, the
encrypted data is first routed to the Input
register, decrypted using the M Key, and finally written to the target key register from the
Output register.

Initializing Vector Registers (IVE and
IVD). Two 64-bit registers are provided to
store feedback values for Cipher feedback and
chained block ciphering methods. One initiahzing vector register (IVE) is used during
encryption, the other (IVD) is used durmg
decryption. Both registers can be loaded with
either clear or encrypted data through the
master port (in the latter case, the data is
decrypted before being loaded into the IV
register), and both may be read out either
clear or encrypted through the master port.

Each byte is written to its respective key
register by placing an active Low signal on the
Auxiliary Port Strobe (ASTB) once data has
been set up on the auxiliary port pins. The
actual write process occurs on the rising (trailing) edge of ASTB. (See SWitching Characteristics section for exact setup, strobe width, and
hold hmes.)
The Auxiliary Port Flag (AFLG) goes inactive immediately after the eighth strobe goes
active (Low). However, the Command Pending
bit (S6) remams I for several more clock
cycles, until the key loading process IS completed. All key bytes are checked for correct
(odd) parity as they are entered.

Load Clear E Key Through Master Port
(liB).
Load Clear D Key Through Master Port
(l2H).

These commands are available in both
Multiplexed Control and Direct Control
modes. They override the data flow specifications set in the Mode register and attach the
master port inputs to the Encrypt (E) Key or
Decrypt (D) Key register, as appropriate, until
eight key bytes have been written. In
Multiplexed Control mode, the command is
initiated by writing the Load command to the
Command register. In Direct Control mode,
the command is initiated by ralsmg the
AUX7-K/D control input while the AUXs-S/S

747

I
i

Commands

(Continued)

input is Low. In this latter case, the level on
AUXe-E/D determines which key register is
written (High = E register).
Once the command has been recognized,
the Command Pending bit (S6 in the Status
register) becomes I. In Direct Control mode,
AUXa-CP goes active (Low), indicating that
key entry may proceed. The host system then
writes exactly eight bytes to the master port (at
the Input register address in Multiplexed Control mode). When the key register has been
loaded, the Command Pending bit returns to
0. In Direct Control mode, the AUXa-CP output goes inactive, indicating that the DCP can
accept the next command.
Load Encrypted E Key Through Auxiliary
Port (B1H).
Load Encrypted 0 Key Through Auxiliary
Port (B2H).

These commands are used in Multiplexed
Control mode only. Their execution is similar
to that of the Load Clear E (D) Key Through
Auxiliary Port command, except that key bytes
are first decrypted using the electronic code
book algorithm and the Master (M) Key
'register. The key bytes are then loaded into
the appropriate key register, after having
passed through the parity-check logic.
The Command Pending bit (Ss) Is I during
the entire decrypt-and-Ioad operation. In addition, the Busy bit (Ss) is I during the actual
decryption process.
Load Encrypted E Key Through Master Port
(31H).
Load Encrypted 0 Key Through Master Port
(32H).

These commands are used in Multiplexed
Control mode only. Their execution is similar
in effect to that of the Load Clear E (D) Key
Through Master Port command. The commands
differ in that key bytes are initially decrypted
using the electronic code book algorithm and
the Master (M) Key register. Once decrypted,
they are loaded byte-by-byte into the target
key register, after having passed through the
parity-check logic.
The command pending bit (Ss) is I during
the entire decrypt-and-load operation. In addition, the busy bit (Ss) is I during the actual
decryption process.
Load Clear IVE Register Through
Master Port (85H)
Load Clear IVO Register Through
Master Port (84H)

These commands are used in Multiplexed
Control mode only. Their execution is virtually
identical to that of the Load Clear E (or D) Key
Through Master Port command. The commands
differ in that the data written to the input
register address is routed to either the Encryption InitialiZing Vector (lVE) or Decryption
Initializing Vector (lVD) register instead of a
key register. No parity checking occurs. The

748

Command Pending bit (Ss) is I during the
entire loading process.
Load Encrypted IVE Register Through
Master Port (ASH).
Load Encrypted IVD Register Through
Master Port (A4H).

These commands are analogous to the Load
Encrypted E (or D) Key Through Master Port
command. The data flow speCifications set in
the Mode register are overridden and the eight
vector bytes are decrypted using the Decryption (D) Key register and the electronic code
book algorithm. The resulting clear vector
bytes are loaded into the target Initializing
Vector register. No parity checking occurs.
The Busy bit (Ss) does not become I during
the decryption process, but the Command
Pending bit (Ss) is I during the entire
decryption-and-Ioad operation.
Read Clear IVE Register Through
Master Port (80H).
Read Clear IVO Register Through
Master Port (8CH).

In the Multiplexed Control mode, these commands override the data flow specifications
set in the Mode register and connect the
appropriate InitialiZing Vector register to the
master port at the Output register address. In
this state, each IV register appears as eight
bytes of FIFO storage. The first byte of data Is
available six clocks after loading the Command register. The Command Pending bit In
the Status register remains a I until sometime
after the eighth byte is read out. The host
system is responsible for reading exactly eight
bytes.
Read Encrypted IVE Register Through
Master Port (A9H).
Read Encrypted IVO Register Through
Master Port (A8H).

In the Multiplexed Control mode only, these
commands override the specifications set in
the Mode register and encrypt the contents of
the speCified Initializing Vector register using
the electronic code book algorithm and the
Encrypt (E) key. The resulting cipher text is
placed in the output register, where it can be
read as eight bytes through the master port.
During the actual encryption process, the Busy
bit (Ss) is I. When the Busy bit becomes 0, the
encrypted vector bytes are ready to be read
out. The Command Pending bit (Ss) is I
during the entire encryption and output process; it becomes when the eighth byte is read
out. The host system is responsible for reading
exactly eight bytes.

°

Encrypt with Master (M) Key (39H).

In the Multiplexed Control mode, this command overrides the data flow specifications set
in the Mode register and causes the DCP to
accept eight bytes from the master port, which
are written to the Input register. When eight
bytes have been received, the DCP encrypts

Commands
(Continued)

the input using the Master (M) Key register.
The encrypted data is loaded into the Output
register, where it can be read out through the
master port. The Command Pending bit (S6)
and the Busy ISs) bit are used as status
indicators in the three phases of this operation.
The Command Pending bit becomes I as
soon as the Input register can accept data.
When exactly eight bytes have been entered,
the Busy bit becomes and remains I until the
encryption process is complete. When Busy
becomes 0, the encrypted data is available to
be read out. The Command Pending bit
returns to when the eighth byte has been
read.
Start Encryption (41H)
Start Decryption (40H)
Start (COH).
The three start commands begin normal data
ciphermg by setting the Status register's
Start/Stop bit (S7) to 1. The Start Encryption
and Start Decryption commands explicitly
specify the ciphering direction by forcing the
Encrypt or Decrypt bit (M4) in the Mode
register to I or 0, respectively. The Start command, however, uses the current state of the
Encrypt/Decrypt bit, as specified in a previous
Mode register load.
When a start command has been entered,
the port status flag (MFLG or SFLG) associated with the Input register becomes active
(Low), indicating that data may be written to

°

Timing
The control and/or data signals and the
Requirements timing requirements for clock/reset, Direct
Control mode, Multiplexed Control mode
(master port), master (slave) port read/write,
and auxiliary port key entry functions are
illustrated in Figures 8 through 12. The ac
switching characteristics of the signals
involved in the above functions are described
in the AC Characteristics. The specific timing
periods described are identified by numerics
(I through 48), which are referenced in both
the timmg diagrams and m the AC
Characteristics.
A two-to-seven character symbol is listed in
AC Characteristics for each period described.
The symbol specifies the signal{s) involved, the
state of each sIgnal, and optionally, the port
associated with a signal. Symbols are encoded
as follows:
General Form: Ta Ab (Cb)
Where:
(l) T IS a constant.
(2) a represents anyone of the follOWing symbols:
Symbol Meaning
c
Clock
d
Delay
f
Fall TIme

the Input register to begin ciphering.
In Direct Control mode, the Start command
is issued by raising the level on the AUXs-S/S
input (Table 4). The ciphering direction is
speCified by the level on AUX6-E/D. If
AUXs-E/D is High when AUXs-S/S goes High,
the command is Start Encryption; if AUXs-EiD
is Low, it is Start Decryption.
Stop (EOH).
The Stop command clears the Start/Stop bit
(S7) in the Status register. This action causes
the input flag (MFLG or SFLG) to become
inactive and inhibits the loading of any further
input into the algorithm unit. If ciphering is in
progress [Busy bit ISs) is I or AUX2-BSY is
active], it is allowed to finish, and any data in
the Output register remains accessIble.
In Direct Control mode, the Stop command
is implied when the signal level on the
AUXs-S/S input goes from High to Low
(Table 4).

Software Reset (00).
This command has the same effect as a hardware reset (MAS and MDS Low): it forces the
DCP back to its default configuration, and all
processing flags go into Inactive mode. The
default configuration includes setting the Mode
register to Electronic Code Book ciphering
mode and establishes a dual-port configuration
with master port clear and slave port
encrypted.
h
Hold Time
r
Rise Time
Setup Time
s
w
Width
(3) A,C represent any of the following signal
names:
Symbol Signal Name
Address Strobe
A
BSY, Busy
B
C
Clock
D*
Data In or the address
at the master port.
E/lS, Enable/DIsable
E
F*
Flag {MFLG, SFLG, or
(AFLG)
G*
Data Strobe (MDS,
SDS, or ASTB)
K
KID, Key/Data
M
CIK, Control/Key
Mode
sis, Start/Stop
N
PAR, Parity
P
Q*
Data Out (master or
slave port)
R
CP, Clock Pulse
S*
ChIp Select (master or
slave port)
MRfW, Master Port
W
read/write
749

N

i

i

(4)

Timing
Requirements
(Continued)

AC

Number

Switching
Characteristics

b represents anyone of the
following signal state descriptors (symbol).
Symbol State Indicated
h
High
Low
I
v
Valid
x
Invalid
z
High Impedance
*These signal names may be
modified by the following optional numeric port identifiers:
Identifier Port
1
Master Port
2
Slave Port
3
AUX (Key) Port
Symbol

Parameter

For example: Dl specifies data
in at Master Port; F2 specifies
Slave Port flag-SFLG.

~

~~1C

eLK

:=}

'-

1=...----

0

Figure 8. Clock and R_I
Min

Max

Notes*t

Clock

2
3

TwCh
TwCI
TcC

Clock Width (High)
Clock Width (Low)
Clock Cycle Time

105
105
250
Reset

4 - - TdGll(Glh) -

MDS*MAS Low to MDS*MAS High-- TC - - - - - - - - - (Reset Pulse Width)
5
TdC(Glh)
Clock High to MDS*MAS High
0
50
Direct Control Mode
6
TsNl(Mh)
sis Low to C/K High (Setup)
2TC
7 - - TsKl(Mh) - - KID Low to ClK High (Setup) - - - - 2TC
8
TdMh(Nh)
C/K High to sis high
4TC
9
TdMh(Kh)
C/K High to KiD High
4TC
10
TsEv(Kh)
ElD Valid to KID High (Setup)
2TC
ll--TdKh(Rl) - - KID High to CP Low - - - - - - - - - - - 200
12
ThKl(Ex)
KID Low to ElD Invalid (Hold)
TC
13
TdCl(Nh)
Clock Low to SIS Valid
20
80
14
TsEv(Hn)
EIi5 Valid to SIS High (Setup)
2TC
15 - - TdNh(Fll) - - SIS High to MFLG (SFLG) Low - - - - - - - 230
(Port Input Flag)
16
TdCh(Fll)
Clock High to MFLG (SFLG) Low
230
(Port Input Flag)
17
TdCh(Bl)
Clock High to BSY Low
300
18 --TdCl(Bh)-- Block Low to BSY High - - - - - - - - - - 220
19
TdCh(Fll)
Clock High to MFLG (SFLG) Low
230
(Port Output Flag)
20
TdNI(Flh)
SIS Low to MFLG (SFLG) High
230
2
(Port Input Flag)
Multiplexed Control Moele-Master Port
21
TwAI
MAS Width (Low)
80
22
TdWv(Ah)
MRIW Valid to MAS High
40
23
TsSll(Ah)
MCS Low to MAS High (Setup)
0
24 --ThAh(Slh) - - MAS High to MCS High (Hold)
60 - - - - - - - - 25
TsDlv(Ah)
Address-In Valid to MAS High
55
(Address Setup Time)
ThAh(Dlx)
MAS High to Address-In Invalid
60
26
(Address Hold Time)
• Notes referenced at end of AC Characteristics table.

750

2080-009

Number

AC
Switching
Characteristics
(Continued)

Parameter

Symbol

Master (Slave) Port Read/Write
MCS (SCS) Low to MDS (SDS) Low
MDS (SDS) High to MCS (SCS) High
(Select Hold Time)
MRlW Valid to MDS Low (Setup)
TsWv(Gll)
29
MDS High to MRlW Invahd (Hold)
30 - - ThG Ih(Hwx) MDS (SDS) Low to MDS (SDS) HIgh
TwGll(Glh)
31
Width-Write Data Read
Width-Status Register Read
32-- TdCl(Glh)-- Clock Low to MDS (SDS) High
MDS (SDS) High to MDS (SDS) Low
TdGlh(HGIl)
33
(Data Strobe Recovery T,me)
Write-Data Valid to MDS (SDS) High
TsDlr(Hlh)
34
Setup Time-Key Load
Setup Time-Data Write
Setup Time-Command/Mode
Register Write
ThGlh(Dlx)
MDS (SDS) High to WrIte-Data
35
Invalid (Hold Time-All Writes)
36--TdGll(Qlv)-- MDS (SDS) Low to Read-Data Valid
Read Access Time-Status Register
Read Access Time-Data
ThGlh(Qlx)
37
MDS (SDS) High to Read-Data Invalid
(Read Hold Time)
38--TdGll(Flh)--MDS (SDS) Low to MFLG (SFLG)
High (Last Strobe)
TdGll(Rh)
39
MDS High to CP High
(Last Strobe, Key Load)
ThGl(HNl)
40
MDS (SDS) High to SIS Low
(Hold Time After Last Input Strobe)
41
TdGI(HPv)
MDS High to PAR Valid (Key Write)
27
28

*

TdSll(Gll)
ThGlh(Slh)

Min

Max

70
0

NotesoOt

3

70
0
125
155
20
125

70

200
100
100

N

i

40

'tI

5

K

155
120
80

•

125---4-TC + 280
3TC
200

Notes referenced at end of AC Charactenstlcs table.

=
=

'INPUT PORT

I

OUTPUT PORT

Figure 9. Control and Status Signals (Direct Control Mode)
2080-010

751

AC
Switching
Characteristics
(Contmued)

Number

Symbol

Parameter

Min

Max

160
20
125

70

Notes*t

Auxiliary Port Key Entry
42
43
44

TwG3
TdCl(G3h)
TdG3h(G31)

45

TsD3v(G3h)

46

ThG3h(D3x)

47
48

TdG3h(Pr)
TdG3l(F3h)

ASTB Low to ASTB High (Width)
Clock Low to ASTB High
ASTB High to Next ASTB Low
(Recovery Time)
Write-Data Valid to ASTB High
(Data Setup Time)
ASTB High to Write-Data Invalid
(Data Hold Time)
ASTB High to PAR Valid
ASTB Low to AFLG High
(Last Strobe)

200
40
200
230

NOTES:

All transItIon times are assumed to be :s 20 ns.
All units m nanoseconds (ns). All hmmgs are
prehmmary and subject to change.

I. Parameter TaCh(Fll) applies to all input blocks ex·
cept the hrst (when sis first goes HIgh).
2. When sis goes Inachve (Low) In DIrect Control
mode, the flag assocIated wIth the input port turns off.

3. Direct Control mode only.
4. In Cipher Feedback mode, the port flag (MFLG or
SFLG) goes inachve follOWIng the leading edge of the
first data strobe (MDS or SDS); m all other modes and
operahons, the flags go inachve on the eIghth data
strobe.

eLK

lID

MCi

MP(AD)

WRITE

MAlW

iliiS

MP(AD)

READ

MAlW

Figure 10. Master Port, Multiplexed Control Mode Read/Write Timing

752

2080·011

AC
Switching
Characteristics
(Continued)

CLK

Sli

WRIT.

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iiii

~:-------------------<

Figure 11. Maller (Slave) Port Read/Writ.

CLK

.. ~
h:r~
I
~~,.......;..i4R--";:-YT-E-.';""---.l.)O

--AS_
--65_

BUS
MASTER

PERIPHERAL
AND MEMORY

RIW ReadlWrite (Low = write). This signal determines the
direction of data transfer for memory or 1/0 transactions.

--RIW_
--B/W _

_ _ WAii'--

BlIW

...-R'E'S"ET----.
ADDRESS/DATA
EXTENDED ADDRESS
STATUS

BUS REQUEST SIGNALS

BW/[

Size

High

High

Byte

Low

High

Word

High

Low

Longword

Low

Low

Reserved

_BUSREQ_

CPU

--BUSACK_

...---BAi_

REQUESTER

L--m_

INTERRUPT SIGNALS

_Jiiii'--

CPU

~
STATUS

DECODE

PERIPHIRAL

BAI, BAO Bus Acknowledge In, Bus Acknowledge Out

RESOURCE REQUEST SIGNALS
--MMRQ_

_MMSi'--

_MMAI=:J
_MMAO

Figure 1. Z·BUS Signals

Bus Request Signals. These signals make bus requests
and establish which component should obtain control of the
bus.
(active Low). These signals tie together peripherals such as
the Z8016 Z-DTC to form the bus-request daisy chain.

C:::=IEIIEO_

Z·BUS
COMPONENT

WAIT (active Low). A Low on this line indicates that the
responding device needs more time to complete a
transaction.

MULTI·MICRO
REQUEST
NETWORK

BUSACK Bus Acknowledge (active Low). A Low on this line
indicatesthattheZ-BUS CPU has relinquished control olthe
bus in response to a bus request.
BUSREQ. Bus Request (active Low). This line is driven by all
bus requestors. A Low indicates that a bus requestor has, or
is trying to obtain, control of the bus.

757

'til
=
{ft

Interrupt Signals. These signals are used for Interrupt
requests and for determining which
Interrupting
component is to respond to an acknowledge. To support
more than one type of interrupt, the lines carrying these
signals can be replicated. (The Z8000 CPU supports three
types of interrupts: non-maskable, vectored, and
non-vectored.)
IEI,IEO. Interrupt Enable In, Interrupt Enable Out (active
High). These signals form the interrupt daisy chain.
INT. Interrupt (active Low). This signal can be driven by any
peripheral capable of generating an interrupt. A Low on INT
indicates that an Interrupt request is being made.
INTACK. Interrupt Acknowledge (active Low). This signal is
decoded from the status lines. A Low Indicates an interrupt
acknowledge transaction is in progress. This signal is
latched by the peripheral on the rising edge of AS.

Resource Request Signals. These signals are used for
resource requests. To manage more than one resource, the
lines carrying these signals can be replicated. (The Z8000
supports one set of resource request lines.)
MMAI, MMAO. Multi-MIcro Acknowledge In, Multi-Micro
Acknowledge Out (active Low). These lines form the
resource-request daisy chain.
MMRQ. Multi-MIcro Request (active Low). This line is driven
by any device that can use the shared resource. A Low
indicates that a request for the resource has been made or
granted.
MMST. Multi-Micro Status (active Low). This pin allows a
device to observe the value of the MMRQ line. An input pin
other than MMRQ facilitates the use of line drivers for
MMRQ.

TRANSACTIONS
All transactions start with Address Strobe being driven Low
and then raised High by the bus master (Figure 2). The
Status lines are valid on the rising edge of Address Strobe
and indicate the type of transactions being initiated. If the
transaction requires an address, It must also be valid on the
rising edge of Address Strobe.
For all transactions except null transactions, which do
notl:ling beyond this point, data is then transferred to, or
from, the bus master. The bus master uses Data Strobe to

)()O(

time the movement of data. For a read (R/W = High), the
bus master makes the AD bus inactive before driving Data
Strobe Low so that the addressed memory or peripheral can
put its data on the bus. The bus master samples this data just
before raising Data Strobe High. For a write (RtW = Low),
the bus master puts the data to be written on the AD bus
before forcing Data Strobe Low.
For an 8-bit Z-8US, data is transferred on ADo-AD? Address
bits may remain on ADa-AD15 while OS is Low.

,

)0( K

CLOCK

,

MASTE~)\.

)
'
BUSMt
SAMPLES WAIT

BUS
SAMPLES

INPUT DATA

,

STO-ST3

X

RIW,BIW

, ,

AD

ADDRESS FROM

,

BUS MASTER

I

DATA TO
BUS MASTER

\
ADo-AD15

\

,
DATA FROM BUS MASTER

Figure 2. Typical1l'ansaction Timing

758

r-<

Z-BUS CONNECTIONS
Table 1. Z-BUS Component Connections to Signal lines. This table shows how the various Z·BUS components attach to each signal
line. When a device is both a bus requestor and a peripheral, the attributes in both columns of the table should be combined (e.g., input
combined with output and 3-state becomes bidirectional and 3-state.)

Signal

CPU

Requestor

Peripheral

AOO-A015

Bidirectlonal 2

Bidlrectional 2

Bldlrectlonal 1

Bldlrectional 2

3-state

3-state

3-state

3-state

Extended

Output

Output

D

Input

Address s

3-state

3-state
Input 10

D

Input

Input

Status

Memory

Output

Output

3-state

3-state

Output

Output

3-state

3-state

B/iN g

Output

Output

Input3

Input

Bl/iN, BW/L14

Output

Output

Input

Input

Input

OutputS

OutputS

Open Drain

Open Drain

Input

Input

Input

Input

R/Vi

3-state

WAIT
AS

OS

Input

Output

Output

3-state

3-state

Output

Output

3-state

3-state

CS4

D

D

Input

Input

RESET

Input

Input 13

Input 5

D

Input

Bidirectional

D

D

D

BUSREQ

Open Drain

BUSACK

Output

D

D

BAI?

D

Input

D

D

BAa?

D

Output

D

D

INT

Input

D

Output

D

Open Drain

INTACK6

D

D

Input 11

D

IEIl

D

D

Input

D

lEO?

D

D

Output

D

MMRQ12

Output
Open Drain

MMST12

Input

MMAI?,12

Input

MMAO?,12

Output

NOTES
1 Only ADO-ADJ, unless peripheral IS 16-bit
2. For an S-blt bus, only ADO-AD? are bldrectlonal.
3. Only for a 16-blt peripheral.
4. Derived signal, one for each peripheral or memory, decoded from status
and address lines
5. Optional-peripherals are tYPically reset by AS and DS being Low
simultaneously; however, they can have a reset Input.
6. Derived signal, decoded from status lines
? Daisy-chain lines

S
g
10
11
12

Optional slgnal(s)
For 16-blt data bus only
Optional-usually only Input on peripherals that are also requestors.
May be omitted If peripheral Inputs status lines
Optional signal, any component may attach to the resource request
lines
13 Optional signal, a bus requestor may also be reset by As and iSS gOing
Low and BAI being High Simultaneously
14 For 32-blt bus only
D No Connection

759

MEMORY TRANSACTIONS
For a memory transaction, the Status lines distinguish
among various address spaces, such as program and data
or system and normal, as well as indicating the type of
transaction, The memory address is put on ADo-AD15 and
on the extended address lines,
For a Z-BUS with 16-bit data, the memory is organized as
two banks of eight bits each (Figure 3), One bank contains

all the upper bytes of all the addressable 16-bit words, The
other bank contains all the lower bytes, When a single byte is
written (R/Vii = Low, B/Vii = High), only the bank indicated
by address bit Ao is enabled for writing,
For a Z-BUS with 8-bit data, the memory is organized as one
bank which contains all bytes, This bank always inputs and
outputs its data on ADo-AD?,
16·BIT Z·BUS DATA PATH

D15

D

Do

BUS DRIVER RECEIVERS

AO-A15
LOWER
BYTE
BANK

EXTENDED
ADDRESS

---t==::::!==i..).----------.J

LOWER
BANK
ENABLE

Figure 3. Byte/Word Memory Organization

I/O TRANSACTIONS
1/0 transactions are similar to memory transactions with two
important differences, The first is that 1/0 transactions take
an extra clock cycle to allow for slow peripheral operation,
The second is that byte data is always transmitted on

ADo-AD?, regardless of the 1/0 address, (ADs-AD15 contain
arbitrary data in this case,) For an 1/0 transaction, the
address indicates a peripheral and a particular register or
function within that peripheral.

NULL TRANSACTIONS
The two kinds of null transactions, internal operation and
memory refresh, are distinguished by the Status lines, Both
transactions look like a memory read transaction except that
Data Strobe remains High and no data is transferred,
For an internal operation transaction, the Address lines
contain arbitrary data when Address Strobe goes High, This
transaction is initiated to maintain a minimum transaction
rate when a bus master is doing a long internal operation (to
support memories which generate refresh cycles from
Address Strobe),

760

For a memory refresh transaction, the Address lines contain
a refresh address when Address Strobe goes High, This
transaction is used to refresh a row of a dynamic memory,
Any memory or 1/0 transaction can be suppressed
(effectively turning it into a null transaction) by keeping Data
Strobe High throughout the transaction,

INTERRUPTS
associated with one interrupt vector and each interrupt
vector can have one interrupt source or more associated
with it. Each vector has a Vector Includes Status bit (VIS)
controlling its use.

A complete interrupt cycle consists of an interrupt request
followed by an interrupt-acknowledge transaction. The
request, which consists of INT pulled Low by a peripheral,
notifies the CPU that an interrupt is pending. The
interrupt-acknowledge transaction, which is initiated by the
CPU as a result of the request, performs two functions: it
selects the peripheral whose interrupt is to be
acknowledged, and it obtains a vector that identifies the
selected device and cause of interrupt.

Finally, each peripheral has three bits for controlling
interrupt behavior for the whole device. These are a Master
Interrupt Enable bit (MIE), a Disable Lower Chain bit (DLC),
and a No Vector bit (NV).
Peripherals are connected together via an interrupt daisy
chain formed with their lEI and lEO pins (Figure 4) The
interrupt sources within a device are similarly connected into
thiS chain with the overall effect being a daisy chain
connecting the interrupt sources. The daisy chain has two
functions: during an interrupt-acknowledge transaction, it
determines which interrupt source is being acknowledged;
at all other times it determines which interrupt sources can
initiate an interrupt request.

A peripheral can have one or more sources of interrupt.
Each interrupt source has three bits that control how It
generates interrupts. These bits are an Interrupt Pending bit
(IP), and Interrupt Enable bit (IE), and an Interrupt Under
Service bit (IUS).
A peripheral may also have one or more vectors for
identifying the source of an interrupt during an
interrupt-acknowledge transaction. Each interrupt source is

INTERRUPT

INTERRUPT

VECTOR

VECTOR

~
~

... ~
~
I

L...I----J/ ,r~_--,I

,I'----...J

• • •

lEI

HIQHE~~

PRIOAI~~

Z·BUS
PERIPHERAL

+c:J Ti"' Tt i

INTACK

ADo-AD?

AS
Z·BUS
CPu

os
iNf
WAIT

STATUS

AOa-AD15

1 I

'.

==ll

p

STATUS
DECODER

I

LOWEST
PRIORITY

Z·BUS
PERIPHERAL

'~O

lEI ADo~AD7 AS

os

iNf

INTACK

Z·BUS
PERIPHERAL

1 I

lEI ADo-AD7 AS

lEO

• , Itt I t
I

rI

t

t

)

/~
,

t

'I I

os

iNf INTACK lEO

t

t

+f

r

FROM '6-BIT PERIPHERALS

Figure 4. Interrupt Connections

761

Figure 5. State Diagram for an Interrupt Source
Transition Legend

A
B

C
D
E
F
G

H
j1

J2

The peripheral detects an interrupt condition and sets
Interrupt Pending.
All higher priority peripherals finish interrupt service, thus
allowing lEI to go High.
An interrupt-acknowledge transaction starts, and the IEII
IEO daisy chain settles.
The interrupt-acknowledge transaction terminates with the
peripheral selected. Interrupt Under Service (IUS) is set to
1, and Interrupt Pending (IP) mayor may not be reset.
The interrupt-acknowledge transaction terminates with a
higher priority device having been selected
The Interrupt Pending bit In the peripheral is reset by an 110
operation.
A new interrupt condition is detected by the peripheral,
causing IP to be set again.
Interrupt service is terminated for the peripheral by resetting
IUS.
IE is reset to 0, causing interrupts to be disabled
IE is set to 1, re-enabling interrupts.

NOTES:
• This diagram assumes MIE = 1 The effect of MIE = 0 IS the same as
that of setting IE = 0
• The OLe bit does not affect the states of Individual interrupt sources. Its
only effect is on the lEO output of a whole peripheral

762

State Legend

0

2
3
4

5
6
7
8

No interrupts are pending or under service for this
peripheral.
An Interrupt IS pending, and an interrupt request has been
made by pulling INT Low.
An interrupt is pending, but no interrupt request has been
made because a higher priority peripheral has an interrupt
under serVice, and this has forced lEI Low.
An interrupt-acknowledge sequence IS in progress, and no
higher priority peripheral has a pending interrupt.
An interrupt-acknowledge sequence IS in progress, but a
higher priority peripheral has a pending interrupt, forcing
lEI Low.
The peripheral has an interrupt under service. Service may
be temporarily suspended (indicated by lEI going Low) If a
higher priority device generates an interrupt.
This IS the same as State 5 except that an interrupt is also
pending In the peripheral.
Interrupts are disabled from this source because IE = 0.
Interrupts are disabled from this source and lower priority
sources because IE = and IUS = 1.

°

1. Transition I to state 6 or 7 can occur from any state except 3 or 4 which
only occur dUring Interrupt acknowledge
2. Transition J from state 6 or 7 can be to any state except 3 or 4, dependIng on the value of lEI, IR and IUS

.~==~~

STl'~E I

;:'_:_IH- ,~ ~

________________________________

iii

\r--------,
STATE 3

STATE~QH
~

~~ ----------------------------~----,
U BUSACK
S BAD
iii
s iAii
LOW

LOW

LOW

LOW

~

i

~

STATE 5
IQH

~
~ BIJSR£Q~
U

BUBACK

HIGH

1

rh:

BAO

~

HIGH

•

~

iii

LOW

LOW

iiiO

5

LOW

~

STATE.

iii

dJ

STATE 7

[J = BUS REQUESTOR
Figure 6. Bus Request Mechanism States
Bus Requestor Legend

2

3

4

5
6
7
8

Requestor does not want bus and is not pulling BUSREQ
Low.
Requestor mayor may not want bus, it is pulling BUSREQ
Low in either case.
Requestor is not pulling i30SREQ Low; if it wants control of
the bus, it must wait for BUSREQ and BAI to rise before
requesting the bus.
Requestor is either using the bus ~ating the Low
on its BAI input. It will stop driving BUSRE-o when its BAa
output goes Low. If It wants to use the bus, but did not want
to at the time BUSREQ and BAI were last Hi~nSR~~SREQ
went from Low to High, then it must wait for
and
BAI to rise before requesting and using the bus.
Requestor is not pullin~USREQ Low. If it wants to use the
bus, it must wait for its 8Af to become High before requestingthebus.
Requestor is propagatlngd~R~~h on its BAI input. If it
wants the bus It will pull B
Low.
Requestor is propagating the High on its BAI input.
Requestor is not ulling BUSREQ Low. If it wanted the bus
at the time BUSRE went from Low to High, it may request
the bus when its BAI in~~E~es; otherwise if it wants the
to rise.
bus, it must wait for BU

Bus State Legend
1
2
3
4

5

6

7

The CPU owns the bus and no one is requesting it.
A bus requestor has requested the bus by pulling BUSREQ
Low, but the CPU has not responded.
A Low from the CPU's BUSACK is propagating down the
BAI/IDiD daisy chain. Bus requestors are using the bus.
The Low from BUSACK has propagated to the end of the
daisy chain causing all bus requestors to release BUSREQ,
which floats High. The CPU has not yet acknowledged
return of the bus.
The CPU acknowledges the High on BUSREQ with a High
on BUSACK, which has propagated down the BAl/BAC)
daisy chain.
Some device whose BAI input is High requests the bus by
pulling BUSREQ Low. The CPU has not yet responded with
a Low on BUSACK.
The CPU has responded to a Low on BUSREQ with a Low
on BITSACK. The previous !::!jgb state on BUSACK is stili
propagating down the BAI/BAO daisy chain.

li'ansltlon Legend
A

A bus requestor requests the bus by pulling down on

BUSREO.

763

B

The CPU responds to BUSREQ by pulling down
BUSACK.

C

The Low from BUSACK propagates to the end of the
BAI/SAO daisy chain, causing all the bus requestors to
let BUSREQ rise.

D

The CPU responds to BUSREQ High by driving
BUSACK High.

E

The High from ....,...,==
BUSREQ propagates to the end of the
BAI/BAO daisy chain.

Figure 5 is a state diagram for interrupt processing for an
interrupt source (assuming its IE bit is 1). An interrupt source
with an interrupt pending (IP = 1) makes an interrupt
request (by pulling iNf Low) under these conditions:
• it is enabled (IE

= 1, MIE = 1)

• it does not have an interrupt under service (IUS = 0)
• no higher priority interrupt is being serviced (lEI = High),
and
• no interrupt-acknowledge transaction is in progress, as
indicated by INTACK at the last rising edge of AS.
lEO is not pulled down by the interrupt source at this time;
lEO continues to follow lEI until an interrupt-acknowledge
transaction occurs.
Some time after INT has been pulled Low, the CPU initiates
an interrupt-acknowledge transaction, indicated by INTACK
Low. Between the rising edge of AS and the falling edge of
OS, the lEI/lEO daisy chain settles. Any interrupt source with
an interrupt pending (IP = 1, IE = 1, MIE = 1) or under
service (IUS = 1) holds its lEO line Low; all other interrupt
sources make lEO follow lEI. When OS falls, only the highest

764

priority interrupt source with a pending interrupt (IP = 1) has
its lEI input High, its IE bit setto 1, and its IUS bit setto o. This
is the interrupt source being acknowledged, and at this
point it sets its IUS bit to 1, and, if the peripheral's NV bit is 0,
identifies itself by placing the vector on ADo-AD? If the NV
bit is 1, then the peripheral's ADo-AD? pins remain floating,
thus allowing external circuitry to supply the vector. All
interrupts, including the Z8000's nonvectored interrupt,
need a vector for identifying the source of an interrupt. If the
vector's VIS bit is 1, the vector will also contain status
information further identifying the source of the interrupt. If
the VIS bit is 0, the vector held in the peripheral will be output
without modification.
While an interrupt source has an interrupt under service
(IUS = 1), it prevents all lower priority interrupt sources from
requesting interrupts by forcing lEO Low. When interrupt
servicing is complete, the CPU must reset the IUS bit and, in
most cases, the IP bit (by means of an I/O transaction).
A peripheral's Master Interrupt Enable (MIE) bit and Disable
Lower Chain (DLC) bit can modify the behavior of the
peripheral's interrupt sources in the following way: if the MIE
bit is 0, the effect is as if every Interrupt Enable (IE) bit in the
peripheral were 0; thus all interrupts from the peripheral are
disabled. If the DLC bit is 1, the effect is to force the
peripheral's lEO output Low, thus disabling all lower priority
devices from initiating interrupt requests.
Polling can be done by disabling interrupts (using MIE and
DLC) and by reading peripherals to detect pending
interrupts. Each Z-BUS peripheral has a single directly
addressable register that can be read to determine if there is
an interrupt pending in the device and, if so, the source of
the interrupt.

BUS REQUESTS
Figure 7 shows how the bus request lines connect bus
requestors and the CPU on a Z-BUS. Figure 8 shows the
states of the bus request mechanism as the Z-BUS is
acquired, used, and released.
To generate transactions on the bus, a bus requestor must
gain control ofthe bus by making a bus request. This is done
by pulling down BUSREO. A bus request can be made in
either of two cases:
•

BUSREO is initially High and BAI is High, indicating that
the bus is controlled by the CPU and no other requestor
is requesting the bus.

•

BAI is High and the requestor had wanted to request the
bus at the time of the last Low-to-High transition of
BUSREO. This insures that a module will not be locked
out indefinitely by a higher priority bus requestor.

After BUSREO is pulled Low, the Z-BUS CPU relinquishes
the bus and indicates this condition by making BUSACK
Low. The Low on BUSACK is propagated through the
BAI/BAO daisy chain (Figure 7). BAI follows BAD for

Z-BUS CPU

BUS
REQUESTERS

+5V

components not requesting the bus, and any component
requesting the bus holds Its BAD High, thereby locking out
all lower priority requestors. A bus requestor gains control of
the bus when its BAI input goes Low. When it is ready to
relinquish the bus, it stops pulling BUSREO Low and allows
BAD to follow BAi: This permits lower priority devices that
made simultaneous requests to gain control of the bus.
When all simultaneously requesting devices have
relinquished the bus, and the Low on BAi/BAO has
propagated to the lowest priority requestor, BUSREO goes
High, returning control of the bus to the CPU.
The CPU responds to the High on BUSREO by driving
BUSACK High. The High on BUSACK is propagated down
the BAI/BAO daisy chain, thus allowing bus requestors to
make new bus requests. Because high priority bus
requestors can pull BUSREO Low before low priority
devices have a High on BAI, a way is needed for low priority
devices to request the bus when BUSREO is Low. That is
provided by the rule that a requestor may request the bus if
BAI is High and it had wanted the bus at the time of the last
Low-to-High transition on BUSREO.
As soon as BUSREO is pulled Low by any requestor, each of
the other requestors on the bus drives BUSREO Low and
continues to do so until it drives its BAD output Low. This
provides a handshake between the CPU and the bus
requestors by ensuring that BUSREO will not go High until
the CPU's acknowledgement of BUSACK has reached
every requestor. Bus requestors can therefore run
asynchronously to the CPU. This rule also allows the
bidirectional BUSREO line to be buffered using the logic
shown in Figure 8. This logic is similar to the logic inside a
bus requestor that keeps BUSREO Low when it has initially
been pulled Low by a different requestor.

+ 5 v --'IN'v--1'---t
+5V

!
COMMON

Figure 7. Bus Request Connections

iiiiSiiEc.i

Figure 8. Bus Request Line Buffering

765

!:=
N

RESOURCE REQUESTS
Resource requests are used to obtain control of a resource
that is shared between several users. The resource can be a
common bus, a common memory, or any other resource.
The requestor can be any component capable of
implementing the request protocol.
Unlike the Z-BUS itself, no component has control of a
general resource by default; every device must acquire the
resource before using it. All devices sharing the general
resource drive the MMRQ line (Figure 9). When Low, the
MMRQ line indicates that the resource is being acquired or
used by some device. The MMST pin allows each device to
observe the state of the MMRQ line.

YES

ACTIVATE

iiMiiQ
FORCE

nAllLOW

When MMRQ is High, a device may initiate a resource
request by pulling MMRQ Low (Figure 10). The resulting
Low on MMRQ is propagated through the MMAI/MMAO
daisy chain. If a device is not requesting the resource, its
MMAO output follows its MMAI input. Any device making a
resource request forces its MMAO output High to deny use
of the resource to lower priority devices.
A device gains control of the resource, if its MMAI input is
Low and its MMAO output is High, after a sufficient delay to
let the daisy chain settle. If the device does not obtain the
resource after this short delay, it must stop pulling MMRQ
Low and make another request at some later time when
MMRQ is again High. When a device that has gained
control of a resource is finished, it releases the resource by
allowing MMRQ to go High.
The four unidirectional lines of the resource request chain
allow the use of line drivers, thus facilitating connection for
components separated by some distance. In the case of the
Z8000 CPU, the four resource request lines may be
mapped into the CPU MI and MO pins using the logic
shown in Figure 11. With this configuration, the Multi-Micro
Request Instruction (MREQ) performs a resource request.
+5V

For any resource requested, this walt tlma must be less than the mlmmum
walt time plus resource usage time of all other requestors.

Figure 10. Resource Request Protocol
MMAI

MMST

iiMiiQ

r-~------~~

MMAO

Mi----o(
MMAI

MMST
MMRQ
MMAO

+-~_r>_---- iiMiiQ

MiO.----------+
L=L~---~ iiiiAO

MMAI
MMST
MMRQ

Figure 11. Bus Request logic for Z8000

MMAOi

Figure 9. Resource Request Connections

766

00-2031-03

V.iversal
Peripherals

Zilog

Uaivenal Peripherals
Two Venioas Exlead
Raage of Appliealioas
March 1985

Zilog's Universal Peripheral Components Family is more than a group
of simple liD circuits- they are intelligent, fully programmable devices
capable of performing complicated
tasks independently. Their capabilities unburden the master CPU,
reduce bus traffic, increase system
throughput, and greatly simplify
overall system hardware design
requirements.
The peripheral components,
where needed, are produced in two
versions to increase their range of
application. One version, identified
by the number Z80xx, is capable of
interfacing with Zilog's multiplexed
Z-8US only or with both the Z-8US
and conventional multiplexed buses.
The second version, identified by
the number Z85xx, is capable of
interfacing with conventional nonmultiplexed buses. Many of these
Z85xx peripherals will function with
and add capability to non-Zilog
CPUs. Contact your local Zilog sales
office, local distributor or representative for additional information and
detailed specifications. This section
ofthe data book includes only product specifications or product briefs
on the Z85xx series of components.
For the specifications or briefs on
the Z80xx components refer to the
Z-8US peripherals section.
All of the peripheral components
are extensively programmable to
permit each to be tailored to its own
applicatlon(s). All Z-8US peripherals
share common interrupt and busrequest structures; they can also be
operated in either a priority-interrupt
or polled environment.

Counting, timing, and parallel 110
transfer problems are easily solved
using the Z8036/Z8536 CIO
Counter/Timer and I/O Unit. This
component has three 16-bit counterl
timers, three liD ports, and can
double as a programmable priorityinterrupt controller.
Data communications problems
are neatly handled by the Z8030/
Z8530 SCC Serial Communications Controller. This device is a

serial, dual-channel, multi-protocol
controller which supports all popular
communications formats. The SCC
supports virtually all serial data transfer applications.
Interface problems with the interconnection of major components
within an asynchronous, parallel
processor system can be solved
using the Z8038 Z-FIO FIFO I/O
Interface Unit. This generalpurpose interface unit provides
expandable, bidirectional buffering
between asynchronous CPUs in a
parallel processing network, or
between a CPU and peripheral
Circuits andlor deVices. The Z-FIO
can be used with systems having
either multiplexed or nonmultiplexed
buses.

General-purpose control and data
manipulation problems are easily
handled by the Z8090/4 and
Z8590/4 UPC Universal Peripheral Controller. The UPC is a com-

plete microcomputer designed for
off-line applications. This microcomputer executes the same friendly,
capable instruction set as Zilog's Z8
microcomputer, it has three liD ports,
six levels of priority-interrupt, and 2K
bytes of memory on chip. The UPC
is intended for applications that
require an intelligent peripheral
controller that can assume many of
the tasks normally required of the
master CPU.
The Z8581 Clock Generator
and Controller (CGC) is a versatile
addition to Zilog's family of universal
microprocessor components. The
selective clock-stretching capabilities
and variety oftiming outputs of this
device allow it to meet the timing
design requirements of various microprocessors easily, including those
of LSI and VLSI peripherals.
The outputs of the Z8581 CGC
directly drive the Z80 and Z8000
microprocessor clock inputs, The
oscillator input frequency reference
sources can be either crystals or
TIL-compatible oscillators.
Two new universal peripherals
have been added to the ever expanding line of Zilog peripherals.
They are the DMA (Direct Memory
Access) Transfer Controller (DTC)
and the Floppy Disk Controller
(FDC).

769

Z8590/4 NOD-Multiplexed Bus
1809014 I-BUS, Z8® UPC
UDivenal Peripheral CODtrollers

Zilog

Product
SpecificatioD

April 1985

FEATURES
• Complete slave Z8 microcomputer, for distributed
processing use.
•

Unmatched power of Z8 architecture and instruction set.

• Three programmable I/O ports, two with optional 2-Wlre
Handshake.
• Six levels of priority interrupts from eight sources: six from
external sources and two from internal sources.
• Two programmable 8-bit counter/timers each with a 6-bit
prescaler. CounterlTimer TO IS driven by an Internal

source, and Counter/Timer T1 can be driven by internal
or external sources. Both counter/timers are
independent of program execution.
• 256-byte register file, accessible by both the master CPU
and UPC, as allocated in the UPC program.
• Z8090 and Z8590-2K bytes of on-chip ROM for
efficiency and versatility.
• Z8094 and Z8594-2K bytes of RAM or EPROM for
efficiency and versatility.

GENERAL DESCRIPTION
The Universal Peripheral Controller (UPC) is an intelligent
peripheral controller for distributed processing applications
(Figure 1). The UPC unburdens the host processor by
assuming tasks traditionally done by the host (or by added
hardware), such as performing arithmetic, translating or
formatting data, and controlling I/O devices. Based on the
Z8 microcomputer architecture and instruction set, the UPC
contains 2K bytes of internal program ROM, a 256-byte
register file, three 8-bit I/O ports, and two counter/timers.
The UPC is offered In two basic configurations: the Z8090/4,
which interfaces to multiplexed address/data CPUs such as
the Z8000, and the Z8590/4, which interfaces With
non-mUltiplexed CPUs such as the Z80. Both devices have
the same instruction set and I/O port configuration. The
difference in the devices is in the UPC-to-host interface pins
and the sequence of data transfer between the units.
The UPC offers fast execution time, an effective use of
memory, and sophisticated interrupt, I/O and bit
manipulation. Using a powerful and extensive Instruction set
combined with an efficient internal addressing scheme, the
UPC speeds program execution and efficiently packs
program code Into the on-chip ROM.

An important feature of the UPC is an internal register file
containing I/O port and control registers accessed both by
the UPC program and indirectly by its associated master
CPU. This architecture results in both byte and
programming efficiency, because UPC instructions can
operate directly on I/O data without moving it to and from an
accumulator. Such a structure allows the user to allocate as
many general-purpose registers as the application requires
for data buffers between the CPU and peripheral devices.
All general-purpose registers can be used as address
pointers, Index registers, data buffers, or stack space.
The register file is logically divided into 16 groups, each
consisting of 16 working registers. A Register Pointer is used
in conjunction with short format instructions, resulting in
tight, fast code and easy task switching.
Communication between the master CPU and the register
file takes place via one group of 19 interface registers
addressed directly by both the master CPU and the UPC, or
via a block transfer mechanism. Access by the master CPU
is controlled by the U PC to allow Independence between the
master CPU and UPC software.

771

The UPC has 24 pins that can be dedicated to 110 functions.
Grouped logically into three 8-line ports, they can be
programmed in many combinations of input or output lines,
with or without handshake, and with push-pull or open-drain
outputs. Ports 1 and 2 are bit-programmable; Port 3 has four
fixed inputs and four outputs.
To relieve software from coping with real-time counting and
timing problems, the UPC has two 8-bit hardware
counter/timers, each with a fixed divide-by-four, and a 6-bit
programmable prescaler. Various counting modes may be
selected.

HOST CPU
INTERFACE

Z8090

AS
OS
BUSTO
MASTER
CPU

R/W

CO
WAiT

Z8590

In addition to the 40-pin standard ROM configuration, the
UPC is available in a Protopack RAM/ROM version with a
socket for up to 2K bytes of RAM or ROM and with 36 bytes
of internal ROM permitting downloading from the master
CPU.
This range of versions and configurations makes the UPC
compatible with most system peripheral device control
considerations.

Z8·UPC MICROCOMPUTER

110

INTERFACE
REGISTERS
(PART OF REGISTER
FILE)

AID
110

Rii
ViR
CO
WAIT

iN'f

iNi

INTACK

INTACK

lEI

lEI

lEO

lEO

+5V GND PCLK

Figure 1. Functional Block Diagram

772

2017·087

PIN DESCRIPTIONS Z8090 Z-UPC
AOo·A07' Z-8US AddresslData Lines (bidirectional). These
multiplexed address and data lines are used to transfer
information between the master CPU and the slave Z-UPC.
AS. Address Strobe (input, active Low). The rising edge of
AS initiates the beginning of a transaction and indicates that
the Address, Status, RiW, and CS signals must be valid.
CS. Chip Select (input, active Low). A Low on this line during
the rising edge of AS enables the Z-UPC to accept address
or data information from the bus during a master CPU write
cycle or to transmit data to the bus during a read cycle.
OS. Data Strobe (input, active Low). OS provides timing for
data movement to the bus master. A simultaneous Low on
AS and OS resets the Z-UPC. It is held in reset as long as OS
is Low. Raising this pin's voltage above Vee forces the Z-UPC
into test mode.
P1 O·P17. P2o·P27. P30·P37' /10 Port Lines (inputs/outputs,
TTL-compatible). These 24 lines are divided into three 8-bit
I/O ports and may be configured in the following ways under
program control:

P1o-P17. Port 1 (input/output-as output it can be push-pull
or open-drain). Bit-programmable Parallel 1/0.
P2o-P27. Port 2 (input/output-as output, it can be push-pull
or open-drain). Bit-programmable Parallel 1/0.
P30-P37. Port 3 (four inputs, four outputs). Parallel 1/0,
handshake control, timer 110, or interrupt control.
PCLK. Clock (input). TTL-compatible clock input, 4 MHz
maximum. This signal does not need to be related to the
master CPU clock.
R/W. Read/Write (input). This status signal indicates that the
master CPU is executing a Read cycle if High, and a Write
cycle if Low.
WAIT. Wait (bidirectional, active Low, open-drain). When the
CPU accesses the Z-UPC register file, this signal requests
the master CPU to wait until the Z-UPC can complete its part
of the transaction. This signal is an input and held High
during RESET to put the Z-UPC in the shift state.

pa,

P30

AODRESSI
DATA BUS

PORT 1

P10~

BUS {
TIMING
ANDRBSET

ZS090
Z-UPC

lEO OR P37

3

par

lEI OR P30

4

pa,

INf OR pa.

pa.

INTACK OR P30

P24

DS

P31-4--

pa,

Ci

pa7_

MASTER { _

INTERR~:~

WAIT

pa,_

lEI OR P30
lEO OR P37

PORT 2
AD,
AD,
AD,
AD,
ADo

Figure 2_ Pin Functions

2017·069,095

pa,
pa,

::-}PORT8
P3,

INTOR P3,
INTACK OR P30

7

P20
Pas
PI<
P17
P1,
P1,
P1,
P1,
P1,
P1,
P1.

Figure 3. Pin Assignments

773

PIN DESCRIPTIONS Z8590 UPC

AID. AddresslData (input). A Low on this pin defines
information on the data bus as an address. A High defines
the information as data.

P2a-P27' Port 2 (input/output-as output, it can be push-pull
or open-drain). Bit-programmable Parallel I/O.

CS. Chip Select (input, active Low). A Low enables the UPC

P30-P37' Port 3 (four inputs, four outputs). Parallel 110,
handshake control, timer I/O, or interrupt control.

to accept address or data information from the master CPU
during a write cycle or to transmit data to the master CPU
during a read cycle. This line is usually generated from
higher bits of the address lines.

PCLK. Clock (input). TTL-compatible clock input, 4 MHz
maximum. This signal does not need to be related to the
master CPU clock.

080.087. Data Bus (bidirectional). This bus is used to
transfer address and data information between the master
CPU and the UPC.
P10·P17, P20·P27, P30·P37. 110 Port Lines (bidirectional,
TTL-compatible). These 24 lines are divided into three 8-bit
I/O ports and may be configured in the following ways under
program control:
P1 a-P17. Port 1 (input/output-as output it can be push-pull
or open-drain). Bit-programmable Parallel I/O.

DATA
BUS

.......
.......
.......
.......
.......

PI,

DB,

PI.

DB•
DB,
DB,
DB,

PI,

RD. Read (input, active Low). A Low enables the master
CPU to read information from the UPC. Raising the voltage
on this pin above Vee will force the UPC into test mode.

WAIT. Wait (output, active Low, open-drain). When the CPU
accesses the UPC register file, this signal requests the
master CPU to wait until the UPC can complete its part of the
transaction.
WR. Wflte (Input, active Low). A Low on thiS pin enables the
master CPU to write information to the UPC. A simultaneous
Lo~n RD and WR resets the UPC. It is held in reset as long
asWRisLow.

--

P3,
P3.

PORT 1

P2,

P2t
P2,

Po.

P10 . . - . .

Z8seo
UPC

INTOR P3,
INTACK OR P3.

MASTER { _

INTERR~~

P2,

:~=}PORT3

P2.
P2,

P20

P30
P2rP2t-

P3,
P3,
PI,
PI.

-

lEI OR P3.
lEO OR P3,

PORTa

+sv-....
PClK
GND_

Figure 4. Pin Functions

774

DB,

DBo

Figure 5. Pin Assignments

2017-068.096

FUNCTIONAL DESCRIPTION
Address Space. On the 40-pin UPC, all address space is
committed to on-chip memory. There are 2048 bytes of
mask-programmed ROM and 256 bytes of register file. 110 is
memory-mapped to three registers in the register file. Only
the Protopack version of the UPC can access external
program memory. See the section entitled "Special
Configurations" for a complete description of the Protopack
version.

contiguous locations (Figure 8). The Register Pointer (RP)
addresses the starting point of the active working-register
group, and the 4-bit register designator supplied by the
instruction specifies the register within the group. Any
instruction altering the contents of the register file can also
alter the Register Pointer. The UPC instruction set has a
special Set Register Pointer (SRP) instruction for initializing
or altering the pointer contents.

Program Memory. Figure 6 is a map of the 2K on-chip

Stacks. An 8-bit Stack Pointer (SP) , register R255, is used for

program ROM. Even though the architecture allows
addresses from 0 to 4K, behavior of the device above
program address 2047 (7FFH) is not defined. The first 12
bytes of program memory are reserved for the UPC interrupt
vectors. In the RAM version, addresses OCH through 2FH
are reserved for on-chip ROM.

addressing the stack, residing within the 234
general-purpose registers, address location 6H through
EFH. PUSH and POP instructions can save and restore any
register in the register file on the stack. During CALL
instructions, the Program Counter is automatically saved on
the stack. During UPC interrupt cycles, the Program
Counter and the Flag register are automatically saved on the
stack. The RET and IRET instructions pop the saved values
of the Program Counter and Flag register.

Register File. This 256-byte file includes three 110 port
registers (1-3H), 234 general-purpose registers (6-EFH), and
19 control, status and special 110 registers (OH, 4H, 5H, and
FO-FFH)' The functions and mnemonics assigned to these
register address locations are shown in Figure 7. Of the 256
UPC registers, 19 can be directly accessed by the master
CPU; the others are accessed indirectly via the block
transfer mechanism.
The I/O port and control registers are included in the register
file without differentiation. This allows any UPC instruction to
process 110 or control information, thereby eliminating the
need for special 110 and control instructions. All
general-purpose registers can function as accumulators,
address pointers, or index registers. In instruction
execution, the registers are read when they are defined as
sources and written when defined as destinations.
UPC instructions may access registers directly or indirectly
using an 8-bit address mode or a 4-bit address mode and a
Register Pointer. For the 4-bit addressing mode, the file is
divided into 16 working register groups, each occupying 16
2047
LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED AFTER
RESET

.....

USER
ROM

........
12
11
10

"

IRQS LOWER BYTE

IDENTIFIER
(UPC Side,

LOCATION
FFH

STACK POINTER

SP

FEH

MASTER CPU INTERRUPT CONTROL

MIC

FDH

REGISTER POINTER

RP

FCH

PROGRAM CONTROL FLAGS

FLAGS

FBH
FAH
F9H
FBH

INTERRUPT MASK REGISTER

IMR

INTERRUPT REQUEST REGISTER

IRQ

INTERRUPT PRIORITY REGISTER

IPR
PIM

PORT 1 MODE REGISTER

F7H

PORT 3 MODE REGISTER

FBH

PORT 2 MODE REGISTER

P2M

FSH
F4H

To PRESCALER

PREO

P3M

COUNTERITIMER 0

TO

F3H

T, PRESCALER

PREI

F2H

COUNTERITIMER 1

T,

F1H

TIMER MODE REGISTER

TMR

FOH

MASTER CPU INTERRUPT YECTOR REG.

MIV

EFH

IRQS UPPER BYTE

9

IRQ4 LOWER BYTE

B

IRQ4 UPPER BYTE

7

IRQ3 LOWER BYTE

B
5

IRQ3 UPPER BYTE
IRQ2 LOWER BYTE

4

IRQ2 UPPER BYTE

3

IRQl LOWER BYTE

2

IRQl UPPER BYTE

1

IRQO LOWER BYTE

0

IRoo UPPER BYTE

Figure 6. Program Memory Map

2017-001,002

Ports. The UPC has 24 lines dedicated to input and output.
These are grouped into three ports of eight lines each and
can be configured under software control as inputs, outputs,
or special control signals. They can be programmed to
provide Parallel 110 with or without handshake and timing
signals. All outputs can have active pullups and pulldowns,
compatible with TTL loads. In addition, they may be
configured as open-drain outputs.

GENERAL-PURPOSE REGISTERS

6H
SH

DATA INDIRECTION REGISTER

DIND

4H

LIMIT COUNT REGISTER

LC

3H

PORT 3

2H
lH
OH

PORT 2
PORT 1
DATA TRANSFER CONTROL REGISTER

P3

••

PI
DTC

Figure 7. Register File Organization

775

I.
I

I•
~

o

1 1 1

o

FFH
FDH
FOH
EFH
EDH
DFH
DOH
CFH
COH
BFH
BOH
AFH
ADH
9FH
90H
8FH
80H
7FH
70H
6FH
60H
5FH
50H
4FH
40H
3FH
30H
2FH
20H
1FH
10H
OFH

0 0

THE 4-BIT REGISTER}
POINTER PROVIDES THE
UPPER NIBBLE OF THE
REGISTER FILE ADDRESS
FOR THE 4-BIT ADDRESS
MODE.

THE LOWER NIBBLE
OF THE REGISTER FILE
{ ADDRESS (O101) IS
PROVIDED BY THE
INSTRUCTION.

0

Figure 8. Register Pointer Mechanism

Port 1. Individual bits of Port 1 can be configured as input or
output by programming Port 1 Mode register (P1 M) F8H'
This port is accessed by the UPC program as general
register 1H. It is written by specifying address 1H as the
destination of any instruction used to store data in the output
register. The port is read by specifying address 1H as the
source of an instruction.
Port 1 may be placed under handshake control by
programming Port 3 Mode register (P3M) F7H. This
configures Port 3 pins P33 and P34 as handshake control
lines DAV'1 and RDY1 for input handshake, or RDY1 and
DAV 1 for output handshake, as determined by the direction
(input or output) assigned to bit 7 of Port 1. The Port 3 Mode
register also has a bit that programs Port 1 for open-drain
output.
Port 2. Individual bits of Port 2 can be configured as inputs or
outputs by programming Port 2 Mode register (P2M) F6H.
This port is accessed by the UPC program as general
register 2H, and its functions and methods of programming
are the same as those of Port 1. Port 3 pins P31 and P36 are
the handshake lines DAV2 and RDY2, with the direction
(input or output) determined by the state of bit 7 of the port.
The Port 3 Mode register also has a bit used to program Port
2 for open-drain output.
Port 3. This port can be configured as I/O or control lines by
programming the Port 3 Mode register. Port 3 is accessed as
general register 3H. The directions of the eight data lines are
fixed. Four lines, P30 through P33, are inputs, and the other
four, P34 through P37, are outputs. The control functions
performed by Port 3 are listed in Table 1.

776

Table 1. Port 3 Control Functions
Function

Handshake

Line

Direction

P31
P33
P34
P36

In
In
Out
Out

P30
P31
P33

In
In
In

IRQ3
IRQ2
IRQ1

P31
P36

In
Out

TIN
TOUT

P3S
P32
P30
P37

Out
In
In
Out

INT
INTACK
lEI
lEO

P3s

Out

AID

{

UPC Interrupt
Request-

{

CounterfTimer

{

Master CPU

{

Test Mode

Signal

DAV2/RDY2
DAV1/RDY1
RDY1/DAV1
RDY2/DAV2

-P30, P31, and P33 can always be used as UPC interrupt request mputs,
regardless of the configuration programmed.

The UPC contains two 8-bit
programmable counter/timers, each driven by an internal
6-bit programmable prescaler.

CounteriTimers.

The T1 prescaler can be driven by internal or external clock
sources. The TO prescaler is driven by an internal clock
source. Both counterltimers operate independently of the

2017·003

processor instruction sequence to relieve the program from
time-critical operations like event counting or elapsed-time
calculation. TO Prescaler register (PREO) F5H and T1
Prescaler register (PRE1) F3H can be programmed to divide
the input frequency of the source being counted by any
number from 1 to 64. A Counter register (F2H or F4H) is
loaded with a number from 1 to 256. The corresponding
counter IS decremented from this number each time the
prescaler reaches end-of-count. When the count is
complete, the counter issues a timer interrupt request; IRQ4
for TO or IRQ5 for T1. Loading either counter with a number
(n) results in the interruption of the UPC at the nth count.
The counters can be started, stopped, restarted to continue,
or restarted from the initial value. They can be programmed
to stop upon reaching end-of-count (Single-Pass mode) or
to automatically reload the initial value and continue
counting (Modulo-n Continuous mode). The counters and
prescalers can be read at any time without disturbing their
values or changing their counts. The clock sources for both
timers can be defined as anyone of the following:
•

UPC internal clock (4 MHz maximum) divided by four.

•

External clock input to Counter/Timer T1 via P31 (1 MHz
maximum).

• Retriggerable trigger input for the UPC internal clock
divided by four.
•

Nonretriggerable trigger input for the U PC internal clock
divided by four.

•

External gate input for the UPC internal clock divided by
four.

TO is driven by the UPC internal clock divided by four.
Interrupts. The UPC allows six interrupts from eight
different sources as follows:
•

Port 3 lines P3o, P32, and P33.

• The master CPU, three.
• The two counter/timers.
These interrupts can be masked and globally enabled or
disabled using Interrupt Mask Register (IMR) FBH. Interrupt
Priority Register (IPR) F9H specifies the order of their priority.
All UPC interrupts are vectored.

Table 2 lists the UPC's interrupt sources, their types, and
their vector locations in program ROM. Interrupt Request
IRQO is dedicated to master CPU communications.
Interrupt Requests IRQ1, IRQ2, and IRQ3 are generated on
the falling transitions of external inputs P33, P31, and P30.
Interrupt Requests IRQ4 and IRQ5 are generated upon the
timeout of the UPC's two counter/timers. When an interrupt
request is granted, the UPC enters an interrupt machine
cycle. This cycle disables all subsequent interrupts, saves
the Program Counter and Status Flags, and branches to the
program memory vector location reserved for that interrupt.
This memory location and the next byte contain the 16-bit
address of the interrupt service routine for that particular
interrupt request.
The UPC also supports polled systems. To accommodate a
polled structure, any or all of the interrupt inputs can be
masked and the Interrupt Request register polled to
determine which of the interrupt requests needs service.
Following any hardware reset operation, an EI instruction
must be executed to enable the setting of any interrupt
request bit in the IRQ register. Interrupts must be disabled
prior to changing the content of either the IPR (F9H) or the
IMR (FBH). 01 is the only instruction that should be used to
globally disable interrupts.
Master CPU Register File Access. There are two ways in
which the master CPU can access the UPC register file:
direct access and block access.

Direct Access. Three UPC registers-the Data Transfer
Control (OH), the Master Interrupt Vector (FO H), and the
Master Interrupt Control (FE H)-are mapped directly into
the master CPU address space. The master CPU accesses
these registers via the addresses shown in Table 3.
The master CPU also has direct access to 16 registers
k[1own as the DSC (Data, Status, Command) registers. The
DSC registers are numbered 0 through F (DSCO-DSCF).
These registers can be any 16 contiguous register file
registers beginning on a 16-byte boundary. The base
address of the DSC register group is designated by the IRP
(I/O Register Pointer), which is bits 04-07 of the Data Transfer
Control register (OH). Figure 9 shows how the register
address is made up of the 4-bit IRP field, concatenated with
the low order 4-bits of the address from the master CPU.

Table 2. Interrupt Types, Sources, and Vector Locations

Name

Source

Vector
Location

Comments

IRQO

EOM, XERR, LERR

0,1

Internal (RO Bits 0, 1,2)

IRQ1

DAV1,IRQ1

2,3

External (P33) • Edge Triggered

IRQ2

DAV2, IRQ2, TIN

4,5

External (P31). Edge Triggered

IRQ3

IRQ3, lEI

6,7

External (P30) • Edge Triggered

IRQ4

TO

8,9

Internal

IRQ5

T1

10,11

Internal

777

Block Access. The master CPU may transmit or receive

blocks of data via address xxx1 01 01. When the master CPU
accesses this address, the UPC register pointed to by the
Data Indirection register is read or written. The Data
Indirection register is incremented, and the Limit Count
register is decremented, for example, when the master CPU
issues a read or write to address xxx1 01 01 while the Data
Indirection register contains the value 33H' The operation
causes register 33H to be read or written and the Data
Indirection register to be incremented to 34H. This scheme is
well suited to Block 1/0 Instructions and allows the master
CPU to efficiently read or write a block of data to or from the
UPC.

The Limit Count register (04H) is decremented and is used to
control the number of bytes to be transferred by master CPU
block accesses. If the master CPU attempts a read or write
to the UPC after the Limit Count register reaches 0, the
access is not completed, the LERR bit (01) of the Data
Transfer Control register is set (indicating a limit error), and
the LERR error causes an IROO interrupt request.
The IRP field of the Data Transfer Control register, the Data
Indirection register, and the Limit Count register are not
directly accessible to the master CPU and therefore must be
set by the UPC. This allows the UPC to protect itself from
master CPU errors and frees the master CPU from tracking
the UPC's internal data layout.

Table 3. Master CPu/UPC Register Map
DTC REGISTER (OH)

----------..
IRP

8090/4
8590/4
No-Shift
Identifier

Address

8090/4
Shift
Address

OTC
OINO

xxx11000

xx11000x

xxx10101
xxx10000
xxx11110
xxxOOOOO
xxxOOO01
xxxOOO10

xx10101x
xx10000x
xx11110x
xxOOOOOx
xxOOOO1x
xxOO010x
xxOO011x
xx00100x

UPCAddress
Decimal

Hex

ADDRESS FROM CPU

0
5
@5*'
240
254
*n
n+
n+
n+
n+
n+
n+
n+
n+
n+
n+
n+
n+
n+
n+
n+

2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
5
@5"
FO
FE

MIV
MIC
OSCO
OSC1
OSC2
OSC3
OSC4
OSC5
OSC6
OSC7
OSC8
OSe9
OSCA
OSCB
OSCC
OSCO
OSCE
OSCF

~ NON·SHIFTED·

xxxOOO11

xxx00100
xxx00101
xxx00110
xxx00111

xxx01000
xxx01001
xxx01010
xxx01011
xxx01100
xxx01101
xxx01110
xxx01111

x = don't care
*n is the value in the IRP x 16
• *Master CPU accesses the register address In Register 5.

778

I~I~I~I~I~I~I~I~I

-~~

.

I~I~I~I~I~I~I~I~I

xx00101x

xx00110x

REGISTER ...

xx00111x
xx01000x

FILE

xx01001x
xx01010x
xx01011x

xx01100x
xx01101x
xx01110x

xx01111x

• The shift or no-shift state 15 set during a hardware reset. If the Wait line is held
High dUring the hardware reset, the 809014 is in Ihe shift stale after the reset. If
WAIT IS held Low, II IS in Ihe no-shift slale. The shift state is maintained untillhe
next hardware reset. Figure 9 shows one way to interface the 8090/4 for the use
cfne-shift.

Figure 9. DCS Register Addressing Scheme

2017·004

SPECIAL CONFIGURATIONS
The Protopack version of the UPC is Identical to the 40-pin
ROM-based UPC with the following exceptions:

Any static RAM that can be interchangeably used with a
2716 EPROM can be plugged into the Protopack socket.

• All but 36 bytes of internal ROM are omitted from the
Protopack RAMIROM version

Protopack Pin Functions. Forty of the pins on the

• The memory address and data lines are buffered and
brought out to the socket on the Protopack. This socket
uses a 2Kx8 RAM or ROM.
The Protopack version of the UPC allows the user to
prototype the system in hardware with an actual U PC device
and to develop the code Intended to be mask programmed
into the on-chip ROM of the 40-pin UPC for the production
system. The Protopack version of the UPC is an extremely
versatile part. RAM program memory can be used on the
40-pin Protopack with RAMIROM for all but 36 bytes of the
UPC's memory space. This memory can then be
downloaded from the master CPU using a bootstrap
program stored in the 36 bytes (C-2F). Figure 10 is a
memory map for the RAM version. This package will also
accept a ROM, provided that the area from C to 2F is not
used for programming.

Using the Z8094/Z8594 with EPROM or RAM. The
Z8094 Z-UPC and the Z8594 UPC can be used with an
EPROM or RAM plugged into the socket on top olthe 40-pin
package. Instructions for using a RAM are provided in
Chapter 8 of the UPC Technical Manual (document
#00-2055-01). If an EPROM is used, the following design
considerations must be observed for proper operation:
1. The pin-out for the EPROM is 2716-compatible.
2. Programs in the EPROM must begin at 30H. The internal
bootstrap ROM resides in locations OCH to 2FH.
3. The LDE instructions that would attempt a write to the
EPROM cannot be used.
4. The UPC must be taken out of the Download mode by
the host CPU after a reset. This IS accomplished by
having the host CPU write two bytes to the UPC The first
byte must reset the Interrupt Pending bit (05) in the
Master CPU Interrupt Control (MIG) register. The second
byte must set the End of Message bit (DO) in the same
register.

Protopack versions have functions identical to those of the
40-pln version. The remaining 24 pins have additional
functions described below. (Figure 11 shows the Protopack
versions' pin functions and pin assignments.)

AD-AlD. Program Memory Address Lines (output). These
lines are identical in all RAMIROM versions in the
Protopack. They are used to address 2K bytes of external
UPCmemory.

00-07. Program Data (input/output). Data is read in from the
external memory on these lines. The RAM version also
writes external memory through this bus.

MOS. Memory Data Strobe (output, active Low). This signal
is Low during an instruction fetch or memory write.

MRIW. Memory ReadlWrite (output RAM versions only).
This signal is High when the UPC is fetching an instruction
and Low when it is loading external memory.
ZB094
+5V

40 P31

PCLK

PCLK 2

39 P3.

P37/IEO

P37/IEO 3

38 P27
37 P2.

P30/lEI

P3011EI 4

P3s/iN'f

P3s/iNT 5

36 P2s

P3,IINTACK

P3,IINTACK 6

35 P24

os

AD7

34 P2,

ViR

33 P2,

RIW

8

AS

AID 9

32 P2,

cs

CS

10

31 P20

GND

GND 11

30 P3,

WAIT

WAIT 12

29 P3,

AD,

DB7 13

28 P17

AD.

DBa 14

27 P1e

AD,

DBs 15

26 Pl,

AD,

DB, 16

25 P14

AD,

DB, 17

24 Pl,

AD,

DB2 18

23 P12

AD,

DB1 19

22 P11

ADo

DBo 20

21 P10

Sockel Pin D.flnillon,

PROGRAM
MEMORY

BOOTSTRAP ROM

UPC INTERRUPT
VECTORS

PROTOPACK

MEMORY

{

INTERNAL

Pi" 8 Ao

pin 9 Do

pin 10 01
pin 11 02
pm 12 GND
pm 13 03
pm 14 04
pin 15 08
pm 16 08

pm 17 07
pm 18 MOS
Pin 19 A10
pm 20 GND
21 MRIW
22 Ag

pin
pin
pin
pin

23 As
24 +5V

Figure 11 . Z8094/Z8594 UPC Protopack Pin Assignments

ROM

}

PROTOPACK

MEMORY

00

Figure 10. Z8094/Z8594 UPC Memory Map
2017-005.008

•

I

Do

~

'SOCKET FOR 2716 EPROM (2K • 8) OR RAM

pm1 A7
plO 2 As
pin 3 As
pm4A4
pmSA3
pin 6 A2
pin 7 A1

I

I!
•~

Z8594
+5V 1

II

779

ADDRESSING MODES
The following notation is used to describe the addressing
modes and instruction operations as shown in the
instruction summary.
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address

IRR
Irr
X

DA

RA

1M
R

r
IR
Ir
RR

Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working-register pair address

ADDITIONAL SYMBOLS
Destination location or contents
Source location or contents
cc
Condition code (see list)
@
Indirect address prefix
SP
Stack Pointer (control register FFH)
PC
Program Counter
FLAGS Flag register (control register FCH)
RP
Register Pointer (control register FDH)
IMR
Interrupt Mask register (control register FBH)
dst

src

Assignment of a value is indicated by the symbol "+-': For
example,
dst +- dst + src
indicates that the source data is added to the destination
data and the result is stored in the destination location. The
notation "addr(n)" is used to refer to bit "n" of a given
location. For example,
dst(7)
refers to bit 7 of the destination operand.

FLAGS
Control Register FCH contains the following six flags:

Affected flags are indicated by:

C
Z
S

o

V
D
H

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag

1

X

Cleared to 0
Set to 1
Set or cleared according to operation
Unaffected
Undefined

CONDITION CODES

780

Value

Mnemonic

1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000

C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Meaning

Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow

Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true

Flags Set

C=1
C=O
Z=1
Z=O
8=0
8=1
V=1
V=O
Z=1
Z=O
(8 XOR V) = 0
(8 XOR V) = 1
[ZOR(8XORV)] = 0
[ZOR(8XORV)] = 1
C=O
C=1
(C = 0 AND Z = 0) = 1
(C OR Z) = 1

INSTRUCTION FORMATS
OPC
dol

CCF, 01, EI, IRET, Nap,
RCF, RET, SCF
OPC

INCr

One-Byte Instructions
OPC

MODE

dstlsrc

OPC
dot

OR 11 1 101 daUarc

I

CLR, CPL, DA, DEC,
DECW, INC, INCW, POP,
PUSH, RL, RLC, RR,
RRC, SRA, SWAP

ADe, ADO, AND, CPt

OR 1 1 1 0
OR 1 1 1 0

OPC

dol

MODE
src

ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR

MODE
dltlsrc

OPC
arc/ds!

LD, LDE, LDEI,
LDC, LOCI

dstlsrc

OPC

arc/ds.

I

dol
OPC
VALUE
doUCCR~ OPC

MODE
dot
VALUE

SRP

OPC
dot

sre
dot

LD, OR, SBC, SUB,
TCM, TM, XOR

MODE
OPC
orc
dol
MODE

OPC

OR

It

1 1 01

dsl

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR

I•

LD
OR 1 1 1 0
OR I 1 1 0

.re
dsl
LD

dstlsrc

i
B

ADDRESS
LD
OR 11 1 1 01

arc

ee

OPC

JP

DAu
DAL

:I

•X

LD

DJNZ, JR

lWo-Byte Instructions

2037,013

MODE
sre
dol

JP, CALL (IndlreC1)
lOR 11 11 01

OPC
VALUE

I

OPC

OPC
DAu
DAL

CALL

d

Three-Byte Instructions

781

OPCODEMAP
Lower Nibble (Hex)

o

o

2

3

4

5

6

i

e

.!!

7

~

I

8

:)

9

A

B

C

D

E

F

2

3

4

5

6

7

8

9

A

B

C

D

E

6,5

10,5

10,5

10,5

10,5

6,5

6,5

12110,5

121100

65

121100

65

6,5

6,5

6,5

DEC

DEC

ADD

ADD

ADD

ADD

ADD

ADD

LD

LD

DJNZ

JR

LD

JP

INC

R,

IR,

r1.r2

f1.lr2

R2,R,

IR2,R,

R"IM

IR"IM

f1.R2

f2,R1

r1 RA

ccRA

r,IM

ceDA

rl

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

RLC

RLC

ADC

ADC

ADC

ADC

ADC

ADC
IR"IM

R,

IR,

'1,T2

'1, lr2

R2,R,

IR2,R,

R"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IR"IM

R,

IR,

'1,T2

'1, lr2

R2,R,

IR2,R,

R"IM

8,0

6,1

6,5

6,5

10,5

10,5

10,5

10,5

JP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRR,

1M

'1,r2

r" lr2

R2,R,

IR2,R,

R"IM

IR"IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA

DA

OR

OR

OR

OR

OR

OR
IR"IM

R,

IR,

'1,T2

T1, lr2

R2,R,

IR2,R,

R"IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP

POP

AND

AND

AND

AND

AND

AND

R,

IR,

r1/2

'1, Ir2

R2,R,

IR2,R,

6,5

6,5

6,5

10,5

10,5

R IM
"
10,5

IR"IM

6,5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

R,

IR,

r1,r2

T1, lr2

R2,R,

IR2,R,

R"IM

IR"IM

12114,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

R2,R,

IR2,R,

R"IM

IR"IM

R2

IR2

(1,r2

T1, lr2

10,5

10,5

12,0

18,0

DECW

DECW

LDE

LDEI

RR,

IR,

T1, Irr2

Ir"lrr2

6,5

6,5

12,0

-

---s:1
DI

---s:1

18,0

RL

RL

LDE

LDEI

R,

IR,

T2, lrT 1

Ir2,lrr,

-

10,5

10112,1

F

EI

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

INCW

INCW

CP

CP

CP

CP

CP

CP

RR,

IR,

r1,T2

r" lr2

R2,R,

IR2,R,

R"IM

IR"IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

R2,R,

IR2,R,

R"IM

IR"IM

R,

IR,

r1. T2

'1,lr2

6,5

6,5

12,0

18,0

RRC

RRC

LDC

LDCI

LD

R,

IR,

T1,lrr2

Ir"lrr2

T1,x,R2

-

6,5

6,5

12,0

18,0

20,0

20,0

10,5

SRA

LDC

LDCI

CALL'

CALL

LD

r2, lrT1

R,

IR,

Ir2,lrT1

IRR,

DA

T2. x,R1

6,5

6,5

6,5

10,5

10,5

10,5

10,5

RR

RR

LD

LD

LD

LD

LD

R2,R,

IR2,R,

R"IM

IR"IM

R,

IR,

r" IR 2

8,5

8,5

6,5

10,5

SWAP

SWAP

LD

LD

R,

IR,

Ir1,r2

R2,IR,

16,0

IRET

e:s
RCF

10,5

SRA

14,0

RET

e:s
SCF
-

6,5

CCF

e:o-NOP

. . ---_v,.----J . . ---_v,.-----',1 ....- - - - -.....v,.-----",,1~'---v---'
2

2

3

3

Bytes per Instruction

LOWER
OPCODE
NlrE

EXECUTION,
CYCLES

PIPELINE
CYCLES

MNEMONIC

Legend:

R = 8-blt address
r = 4-brt address
R1 orr1 = Dstaddress
R20rr2 = Src address

Sequence:
Opcode, Fltst Operand, Second Operand

FIRST
OPERAND
* 2-byte mstructlon,

782

SECOND
OPERAND

NOTE The blank areas are not defined

fetch cycle appears as a 3-byte mstructlon

8085-002

INSTRUCTION SUMMARY
AddrMode
Instruction
and Operation

dst

src

Opcode
Byte
(Hex)

Flags Affected

C Z S V

o

H
*
*

ADCdst,src
dst +- dst + src + C

(Note 1)

10

*

* * *

o

ADDdst,src
dst +- dst + src

(Note 1)

00

*

* * *

o

ANDdst,src
dst +- dst AN 0 src

(Note 1)

50

-**

06
04

------

CALLdst
OA
SP +-SP - 2
IRR
@SP +- PC; PC +- dst
CCF
C +-NOTC

0--

EF

*-----

CLRdst
dst +- 0

R
IR

BO
Bl

------

COMdst
dst +- NOT dst

R
IR

60
61

-**

CPdst,src
dst - src

(Note 1)

AD

* * * *--

R
IR

40
41

* *

*

X--

DECdst
dst +- dst - 1

R
IR

00
01

-**

*--

DECWdst
dst .... dst - 1

RR
IR

80
81

-* **--

8F

-----------

DJNZr,dst
RA
r .... r - 1
ifn·O
PC+-PC + dst
Range: +127, -128

rA
r =0 - F

INCdst
dst +- dst + 1

INCWdst
dst +- dst + 1

------

9F

EI
IMR (7) +-1

rE
r

=0 -

R
IR

20
21

RR
IR

AO
Al

-***-F

8085-003

OA

-**

IRR

=0 30

LD dst,src
dst +- src

r
R

Flags Affected
CZSVDH

-----cB
c=O-F

1m
R

r

X

X

r
Ir
r
R
IR
1M
1M
R

r
Ir
R
R
R
IR
IR

-----rC
r8
r9
r= 0 - F
C7
07
E3
F3
E4
E5
E6
E7
F5

LDCdst,src
dst +- src

r
Irr

Irr

C2
02

------

LOCI dst,src
dst +- src
r +- r + 1; rr +- rr + 1

Ir
Irr

Irr
Ir

C3
03

------

LDE dst,src
dst +- src

r
Irr

Irr

82
92

------

LDEI dst,src
dst +- src
r +- r + 1; rr +- rr + 1

Ir
Irr

Irr
Ir

83
93

------

FF

------

(Note 1)

40

-**0--

POPdst
dst+-@SP;
SP +- SP + 1

R
IR

50

------

PUSH src
SP +- SP - 1; @SP +- src

R
IR

70
71

------

CF

0-----

RET
PC+-@SP,SP+-SP+ 2

AF

------

~I~

90
91

* *

* *--

R
IR

10
11

* *

*

l[iJ LDJ I~

EO
El

*

* *

NOP
OR dst,src
dst +- dst OR src

Rei'

*--

RLdst
* *

* * *

*
RLe dst

L:{i}:ciJ
C

------

cD
c

src

Opcode
Byte
(Hex)

C+-O

BF
IRET
FLAGS +- @SP; SP +- SP + 1
PC +-@SP; SP +- SP + 2; IMR (7) +-1
JP cC,dst
If cc IS true
PC +-dst

dst

JRcc,dst
RA
If cc is true,
PC +- PC + dst
Range. + 127, -128

0--

DAdst
dst .... OAdst

01
IMR (7) +-0

AddrMode
Instruction
and Operation

F

RRdst

7

0

*

*

783

Il
r:en

!c=
~

INSTRUCTION SUMMARY (Continued)
AddrMode Opcode
Byte
dst src
(Hex)

Instruction
and Operation

and Operation

CO
C1

* * * *

XORdst,src
dst ... dst XOR src

3D

* * * * 1 *

OF

1-----

00
01

***0--

1m

31

------

(Note 1)

20

* * * * 1 *

IR

FO
F1

X * *

(Note 1)

60

-** 0--

7 0 IR

SBCdst,src
dst ... dst ... src'" C

(Note 1)

SCF
C"'1
SRA dst

l@] [!f¢JJ

R
IR

SRPsrc
RP"'src
SUBdst,src
dst ... dst ... src
SWAP dst

17 : _I_ ; 01 R

TCMdst,src
(NOT dst)ANO src
1M dst,src
dstANOsrc

AddrMode Opcode
Byte
(Hex)
dst 'src

Inst~uction

CZSVDH

RRCdst~R
C

Flags Affected

(Note 1)

70

(Note 1)

CZSVDH

BO

-**0--

NorE: These Instructions have an identical set of addreSSing modes,
which are encoded for brevity. The first opcode nibble is found in
the instruction set table above The second nibble IS expressed
symbolically by a D in this table, and its value IS found In the
follOWing table to the left of the applicable addreSSing mode pal<
For example, the opcode of an ADC instruction using the
addreSSing modes r (desllnatlon) and Ir (source) is 13.

AddrMode
dst

Lower
Opcode Nibble

src

R

R

m
m
[II

R

IR

[II

R

1M

III

IR

1M

X--

-** 0--

Flags Affected

Ir

m

REGISTERS
R248P1M

R247P3M

Port 1 Mode Register

Port 3 Mode Register

(F8H)

(F7H)

I~I~I~I~I~I~I~I~I
Pto-Pt, 110 DEFINITION

' - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

III

~:=:::::::::::
1 PORT 1 PULL·UPS ACTIVE

o Pas = QlLTPUT

R246P2M

1 P" = INT
RESERVED

Port 2 Mode Register

o P33 = INPUT

(F6H)

1 P33

=

DiW1/RDY1

'------ ~ ~:: : ~:~R~~~
P2Q-P2, 110 DEFINITION
' - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

'--_ _ _ _ _ _ ~~: : :~rUT

P34
P34

=

OUTPUT

= RDY1/DAV1

~:: ~ ~~~:~OUT)
P37 = OUTPUT

P37 = lEO

'--------- ~ =: : ::~~~K

Figure 12. Port Mode Registers

784

8085-003 2017-009

REGISTERS (Continued)
R2511MR
Interrupt Mask Register
(FBH)

L'ENABLESIRQO

~~~
L

R250lRQ
Interrupt Request Register
(FA H)

~~ :::~ :;3:~::~~PU

II

1 ENABLES IRQ1
1 ENABLES IRQ2

IRQ2

= P31 INPUT

1 ENABLES IRa3

IRa3

=

1 ENABLES IRQ4

IRQ4

COMMUNICATIONS

P30 INPUT

= To
IROS = 11

1 ENABLES IROS

L.._ _ _ _ _ _ _ RESERVED

RESERVED
L -_ _ _ _ _ _ _ _ 1 ENABLES INTERRUPTS

R2491PR
Interrupt Priority Register
(F9H, Write Only)

RESERVEOT'
INTERRUPT GROUP PRIORITY

RE~;r:.v;~ ~ gg~

__-+_-+-_+-_...1

=
=
=
=

011
100
101
110

IRQO, IRQ2 PRIORITY (GROUP B)

IRQ3, IRQS PRIORITY (GROUP A)
L.._ _ _ _ _ _ 0 = IRQS > IRQ3

= 111

RESERVED

1

o = IR02 > IROO
1 = IROO> IRQ2

= 010

A>B>C
A>C>B
B>C>A
C>B>A
B>A>C

IRQ', IRQ4 PRIORITY (GROUP C)
IRQ1 > IRQ4
= IRQ4 > IRQ1

o=

1

= IRaa > lAOS

Figure 13. Interrupt Control Registers
R240MIV
Master CPU Interrupt Vector Register
(FOH)

R254MIC
Master CPU Interrupt Control Register
(FEH)

I~I~I~I~I~I~I~I~I

LO-

~ug

, END OF MESSAGE

IL..- - - _

VECTOR DATA (Do = LSB)

o WAIT ENABLE WHEN WRITE
1 WAIT DISABLE WHEN WRITE

o ENABLE LOWER CHAIN
1 DISABLE LOWER CHAIN

o DISABLE DATA TRANSFER
1 ENABLE DATA TRANSFER
o VECTOR OUTPUT
, NO VECTOR OUTPUT
1 . -_ _ _ _ _

~ ~~S~~~T~:UCI~~~~~~~~U::N~~~g'NG

L.._ _ _ _ _ _ _

~ ~N~~~~~~~UJ~DuE~Di:R~~~~'CE

L.._ _ _ _ _ _ _ _

~ :~i~~=~~i ~~g~~~i ~~s::LL:g

Figure 14. Master CPU Interrupt Registers
R253RP
Register Pointer
(FDH)

R252 FLAGS
Flag Register
(FCH)

LUSERFLAGF'

~~~
L

c=

DON'T CARE

USER FLAG F2
HALF CARRY FLAG
OECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG

ZERO FLAG
L -_ _ _ _ _ _ _ _ CARRY FLAG

R255SP
Stack Pointer
(FFH)

I~I~I~I~I~I~I~I~I
L..I_ _ _ _

~Tp~:~:'~INTER

Figure 15. UPC Control Registers
2017-010,011,012

785

REGISTERS (Continued)
RODTC
Data Transfer Control Register
(OOH)

R4LC
Limit Count Register
(04H)

I~I~I~I~I~I~I~I~I

I

LIMIT COUNT VALUE
' - - - - - - - (RANGE, 0-255 DECIMAL
OO-FF HEX)

(EOM) 0
1 END OF MESSAGE
NO LIMIT ERROR
LIMIT ERROR

(XERR)

NO TRANSFER ERROR
TRANSFER ERROR

(EDX)

DISABLE DATA TRANSFER
ENABLE DATA TRANSFER

"'(I"'R'-'P)_ _ _ _ _ _ _ 1 110 REGISTER POINTER

R5DIND
Data Indirection Register
(05H)
I~I~I~I~I~I~I~I~I

L.1-----_:~~'!'~c;~~N

ADDRESS

Figure 16. Master CPU·UPC Data Transfer Registers

RES~o.:'JE~O,!'~~
=
INTERNAL

loOUl

01

CLOCT~ g~~

: :~

R241 TMR
Timer Mode Register
(F1H)

R243PRE1
Prescaler 1 Register
(F3H)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

J

[I

~

EXTERNTA~ ~~g~~
INPUT

= 00

TRI8~~~ :~~~~

: ~~
(NON.RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)

l

01 =
NO FUNCTION
= LOAD
To
0
1

= DISABLE To COUNT

0
1

= NO FUNCTION
= LOAD 11

0
1

= DISABLE T1 COUNT

= ENABLE To COUNT

~,!U~,\~'?ci'LEE
=
1

PASS
T1 MOOULO • N

CLOCK SOURCE
o = EXTERNAL TIMING INPUT
(T,N) MODE
1 = T1 INTERNAL

PRESCALER MODULO
' - - - - - - - (RANGE, 1-84 DECIMAL
01-00 HEX)

= ENABLE T1 COUNT

R244 TO
Counter/Timer 0 Register
(F4H)

R242 T1
Counter/Timer 1 Register
(F2H)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

I

I

To INITIAL VALUE
' - - - - - - (RANGE, 1-256 DECIMAL
01-00 HEX)

T1 INITIAL VALUE
' - - - - - (RANGE, 1-256 DECIMAL
01-00 HEX)

R245 PREO
Prescaler 0 Register
(F5H)

~L

COUNTMODE

o = To SINGLE·PASS
1 = To MODULO. N
RESERVED
PRESCALER MODULO
(RANGE, 1-64 DECIMAL
01-00 HEX)

Figure 17. UPC Counter/Timer Registers

786

2017·014,013

Table 4. Control Register Reset Conditions

Control Register
OOH
Data Transfer Control Register

06

Os

04

03

02

01

00

X

X

X

X

0

0

0

0

Disable data transfer from
master CPU

0

0

0

Stops TO and T1

04H
Limit Count Register

Not Defined

05H
Data Indirection Register

Not Defined

FOH
Interrupt Vector Register

Not Defined

F1H
Timer Mode

0

0

0

X

X

X

0

X

X

X

0

0

Single-Pass mode

X

X

X

X

X

X

0

0

Single-Pass mode External
clock source

i
~

Port 2 lines defined as Inputs

F6H
Port 2 Mode
F7H
Port 3 Mode

I.
I

Not Defined

F4H
T1 Register
F5H
T1 Prescaler

0

Not Defined

F2H
TO Register
F3H
TO Prescaler

Comments

07

0

0

0

0

X

0

0

Ports 1.2 open drain;
P3s = INT; P30. P31. P32.
P33 defined as input; P34.
P36. P37 defined as output.
Port 1 lines defined as inputs

F8H
Port 1 Mode
Not Defined

F9H
Interrupt Priority
FAH
Interrupt Request

X

X

0

0

0

0

0

0

Reset Interrupt Request

FBH
Interrupt Mask

0

X

X

X

X

X

X

X

Interrupts disabled

0

0

0

Master CPU interrupt disabled;
wait enable when write;
lower chain enabled

FCH
Flag Register

Not Defined

FDH
Register Pointer

Not Defined

FEH
Master CPU Interrupt
Control Register
FFH
Stack Pointer

0

0

0

0

0

Not Defined

NOTE' X means not defined

787

MASTER CPU INTERFACE TIMING Z8590/4

peLK

AID

______

-J'~------------------~~----------------

DBo-DB,

WRITECASE _ _ _ _ _I--+,~+------+_"-'+--++--------

D~DB,_----_t~~~R1~~~:!~~::t_-_i~~~~-----

READ CASE

RD

INTERRUPT ACKNOWLEDGE TIMING Z8590/94

DBO-DB, --------------<1

VECTOR

1'---:--:---'

RD

III

110

788

2022-015,016

Z8590/4 AC CHARACTERISTICS

4 MHz
Number

2
3
4
5
6
7
8
9
10

Symbol

Parameter

TrC

Clock Rise Time

TwCH

Clock High Width

TfC

Clock Fall Time

TwCI

Clock Low Width

TpC

Clock Period

TsA/D(WR)

AID to WR ~ Setup Time

TsA/D(RD)

AID to RD ~ Setup Time

ThA/D(WR)

AID to WR t Hold Time

ThAID(RD)

AID to RD t Hold Time

TsCSf(WR)

CS ~ to WR ~ Setup Time

Min

105
105
250

TsCSf(RD)

CS ~ to RD ~ Setup Time

TsCSr(WR)

CS t to WR ~ Setup Time

TsCSr(RD)

CS t to RD ~ Setup Time

ThCS(WR)

CS to WR t Hold Time

ThCS(RD)

CS to RD t Hold Time

16
17
18
19
20

TsDI(WR)

Data in to WR ~ Setup Time

Tw(WR)

WRLowWidth

26
27
28
29
30
31
32
33
34
35

Notes*t

20
1855
20
1855
2000

80
80
30
30
0

11
12
13
14
15

21
22
23
24
25

Max

Il

0
60
60
0
0

Tw(RD)

RDLowWidth

ThWR(DI)

Data in to WR t Hold Time

TdRD(DI)

Data Valid from RD ~ Delay

ThRD(DI)

Data Valid to RD t Hold Time

TdRD(Dlz)

Data Bus Float Delay from RD t

TdRD(DBA)

RD ~ to Read Data Active Delay

TdWR(W)

WR ~ to WAIT ~ Delay

TdRD(W)

RD ~ to WAIT ~ Delay

N
GO
ell

IIii;

0
390
390
0

CI

~

[1,3]
0
70
0

[3]
[3]
[3]

150
150

TdDI(W)

Data Valid to WAIT t Delay

TsACK(RD)

INTACK ~ to RD ~ Setup Time

0
90

[3]
[2]
255

TdRD(DI)

RD ~ to Vector Valid Delay

ThRD(ACK)

RD t to INTACK t Hold Time

ThIEI(RD)

lEI to RD t Hold Time

0
100
255

TwRDI

RD (Acknowledge) Low Width

TdIEI(IEO)

lEI to lEO Delay

TsIEI(RD)

lEI to RD ~ Setup Time

TdACKf(IEO)

INTACK ~ to lEO ~ Delay

TdACKr(IEO)

INTACK t to lEO t Delay

120

[3]

150
250
250

NOTES:

[1] This parameter is dependent on the state of the UPC at the time of
master CPU access.
[2] In case where daisy chain is not used.
[3] All output ac parameters use test load 1.

• Timings are preliminary and subject to change. Units in nanoseconds
(ns).
t The timing characteristics given reference 2.0V as High and O.8V as
Low.

789

Z8090/4 MASTER CPU INTERFACE TIMING

PCLK

ADo-AD, ------.,.~H_~~;.......,.,

I)------f.+f+f

MASTER CPU
READ

'Ui.~"''':::::::':--f'

ww ------------~~------~
WRITE

-------+f-----.....:jL...+------1--+----"""-

RIW

READ _ _ _ _ _ _ _+-11-_ _...1

ADO-AD,

------.,..w.-:...j.---""5..w.-,.;;;;.....:.----+--.:....-...;;.--i

MASTER CPU
WRITE _ _ _ _ _

....J1I....-+....:::=_-{1-______+ ______...:r

Z8090/4 INTERRUPT ACKNOWLEDGE TIMING
UNDEFINED

VECTDR

Ai
DS

------t---~kl--__~~~"
~'" .. " ". "¥'"

. .,,

Figure 2b. 44-Pin Chip Carrier.
Pin Assignments

861

811

...enw

Pin
Description

862

The follpwing section describes the pin
functions of the ASCC. Figures 1 and 2 detail
the respective pin functions and pin
assignments.
AlB. Channel AlChannel B Select (input).
This signal selects the channel in which the
read or write operation occurs.
CEo Chip Enable (input, active Low). This
signal selects the ASCC for a read or write
operation.
CTSA. CTSB. Clear To Send (inputs, active
Low). If these pins are programmed as Auto
Enables, a Low on the inputs enables the
respective transmitters. If not programmed as
Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs.
The ASCC detects pulses on these inputs and
can interrupt the CPU on both logic level
transitions.
Die. DataiControl Select (input). This signal
defines the type of information transferred to
or from the ASCC. A High means data is
transferred; a Low indicates a command.
DCDA. DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if they are programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-trigger buffered to accomodate slow
rise-time signals. The ASCC detects pulses on
these pins and can interrupt the CPU on both
logic level transitions.
Do-o,. Data Bus (bidirectional, 3-state). These
lines carry data and commands to and from
the ASCC.
DTR/REQA. DTR/REQB. Data Terminal
Ready/Request (outputs, active Low). These
outputs follow the state programmed into the
DTR bit. They can also be used as generalpurpose outputs or as Request lines for a DMA
controller.
lEI. Interrupt Enable In (input, active High).
lEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High lEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active
High). lEO is High only if lEI is High and the
CPU is not servicing an ASCC interrupt or the
ASCC is not requesting an interrupt (Interrupt
Acknowledge cycle only). lEO is connected to
the next lower priority device's lEI input and
thus inhibits interrupts from lower priority
devices.
INT. Interrupt Request (output, open-drain,
active Low). This signal is activated when the
ASCC requests an interrupt.

INTACK. Interrupt Acknowledge (input, active
Low). This signal indicates an active Interrupt
Acknowledge cycle. During this cycle, the
ASCC interrupt daisy chain settles. When RD
becomes active, the ASCC places an interrupt
vector on the data bus (if lEI is High).
INTACK is latched by the rising edge
of PCLK.
PCLK. Clock (input). This is the master ASCC
clock used to synchronize internal signals;
PCLK is a TTL level signal.

RD. Read (input, active Low). This signal indicates a read operation and when the ASCC is
selected, enables the ASCC's bus drivers.
During the Interrupt Acknowledge cycle, this
signal gates the interrupt vector onto the bus
if the ASCC is the highest priority device
requesting an interrupt.
RxDA. RxDB. Receive Data (inputs, active
High). These input signals receive serial data
at standard TTL levels.
RIA. RIB. Ring Indicator (inputs, active Low).
These pins can act either as inputs, or part of
the crystal oscillator circuit. In normal mode
(crystal oscillator option not selected), these
pins are inputs similar to CTS and DCD. In
this mode, transitions on these lines affect the
state of the Ring Indicator status bits in Read
Register 0 (Figure 8) but have no other function.
RTxCA. RTxCB. Receive/Transmit Clocks
(inputs, active Low). These pins can be programmed in several different modes of operation. In each channel, RTxC may supply the
receive clock, the transmit clock, the clock for
the baud rate generator, or the clock for the
Digital Phase-Locked Loop. These pins can
also be programmed for use with the respective RI pins as a crystal oscillator. The receive
clock may be I, 16,32, or 64 limes the data
rate in Asynchronous modes.
RTSA. RTSB. Request To Send (outputs,
active Low). When the Request To Send (RTS)
bit in Write Register 5 (Figure 9) is set, the
RTS signal goes Low. When the RTS bit is
reset in the Asynchronous mode and Auto
Enable is on, the signal goes High after the
transmitter is empty. With Auto Enable off, the
RTS pin strictly follows the state of the RTS bit.
Both pins can be used as general-purpose
outputs.
TxDA. TxDB. Transmit Data (outputs, active
High). These output signals transmit serial data
at standard TTL levels.

TRxCA. TRxCB. Transmit/Receive Clocks
(inputs or outputs, active Low). These pins can
be programmed in several different modes of
operation. TRxC may supply the receive clock
or the transmit clock in the input mode or sup-

Pin
Description
(Contmued)

ply the output of the Digital Phase-Locked
Loop, the crystal oscillator, the baud rate
generator, or the transmit clock in the output
mode.

W/REQA. W/REQB. Wait/Request (outputs,
open-drain when programmed for a Wait function, driven High or Low when programmed
for a Request function). These dual-purpose
outputs may be programmed as Request lines
for a DMA controller or as Wait lines to synchronize the CPU to the ASCC data rate. The
reset state is Wait.

WR. Write (input, active Low). When the
ASCC is selected, this signal indicates a write
operation. The coincidence of RD and WR is
interpreted as a reset.
Functional
Description

The functional capabilities of the ASCC
can be described from two different points
of view: as a data communications device,
it transmits and receives data in a wide
variety of data communications protocols; as a
microprocessor peripheral, the ASCC offers
valuable features such as vectored interrupts,
polling, and simple handshake capability.

handle data at a rate of 1116, 1/32, or 1/64 of
the clock rate supplied to the receive and
transmit clock inputs.

Data Communications Capabilities. The
ASCC provides two independent full-duplex
channels programmable for use in any common Asynchronous data communication protocol. Figure 3 and the follOWing description
briefly detail this protocol.
Asynchronous Modes. Transmission and
reception can be accomplished independently
on each channel with five to eight bits per
character, plus optional even or odd parity.
The transmitters can supply one, one-and-ahalf, or two stop bits per character and can
provide a break output at any time. The
receiver break-detection logic interrupts the
CPU both at the start and at the end of a
received break. Reception is protected from
spikes by a transient spike-rejection
mechanism that checks the signal one-half a
bit time after a Low level is detected on the
receive data input (RxDA or RxDB in
Figure 1). If the Low does not persist (as in the
case of a transient), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together with the partial
character on which they occur. Vectored interrupts allow fast servicing of error conditions
using dedicated routines. Furthermore, a
built-in checking process avoids the interpretation of a framing error as a new stilrt bit: a
framing error results in the addition of one-half
a bit time to the point at which the search for
the next start bit begins.
The ASCC does not require symmetric
transmit and receive clock signals-a feature
allowing use of the wide variety of clock
sources. The transmitter and receiver can

Baud Rate Generator. Each channel in the
ASCC contains a programmable baud rate
generator. Each generator consists of two 8-bit
time constant registers that form a 16-bit time
constant, a 16-bit down counter, and a flip-flop
on the output producing a square wave. On
startup, the flip-flop on the output is set in a
High state, the value in the time constant
register is loaded into the counter, and the
counter starts counting down. The output of
the baud rate generator toggles upon reaching
0, the value in the time constant register is
loaded into the counter, and the process is
repeated. The time constant may be changed
at any time, but the new value does not take
effect until the next load of the counter.
The output of the baud rate generator may
be used as either the transmit clock, the
receive clock, or both. It can also drive the
Digital Phase-Locked Loop (see next section).
If the receive clock or transmit clock is not
programmed to come from the TRxC pin, the
output of the baud rate generator may be
echoed out via the TRxC pin.
The follOWing formula relates the time constant to the baud rate (the baud rate is in
bits/second and the BR clock period is in
seconds):
PCLK
lIme constant = 2 (clock factor) (baud) -2

Digital Phase-Locked Loop. The ASCC contains a Digital Phase-locked-Loop (DPll) to
recover clock information from a data stream
with NRZI or FM encoding. The DPll is driven
by a clock that is nominally 32 (NRZI) or 16
(FM) times the data rate. The DPll uses this
clock, along with the data stream, to construct
a clock for the data. This clock may then be
used as the ASCC receive clock, the transmit
clock, or both.

TT lr
::-MA::-:R::::K'::::NG~L~'N::::E--'I 1""1-DA-T-A'l'Ir,';"1:1:O:AT:A:I:I'""'"'II DATA II' , MARK'NG LINE
PARITY

ASYNCHRONOUS

Figure 3. ASee Protocol

2016·004

863

E
w
...

fi

Functional
Description
(Continued)

For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x
clock is counted, the DPLL is searching the
incoming data stream for edges (either I to 0
or 0 to I). Whenever an edge is detected, the
DPLL makes a count adjustment (during the
next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from
o to 31, but with a cycle corresponding to two
bit times. When the DPLL is locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
O. The DPLL looks for edges only during a
time centered on the 15 to 16 counting
transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input
or the output of the baud rate generator. The
DPLL output may be programmed to be
echoed out of the ASCC via the TRxC pin (if
this pin is not being used as an input).

Data Encoding. The ASCC may be programmed to encode and decode the serial data
in four different ways (Figure 4). In NRZ
encoding, a I is represented by a High level
and a O. is represented by a Low level. In NRZI
encoding, a I is represented by no change m
level and a 0 is represented by a change in
level. In FMI (more properly, bi-phase mark),
a transition occurs at the beginning of every
bit cell. A I is represented by an additional
transition at the center of the bit cell and a 0 IS
represented by no additional transition at the
center of the bit cell. In FMO (bl-phase space),
a transition occurs at the beginning of every
bit cell. A 0 is represented by an additional
transition at the center of the bit cell, and a I
is represented by no additional transition at
the center of the bit cell. In addition to these
four methods, the ASCC can be used to
decode Manchester (bi-phase level) data by
using the DPLL in the FM mode and programming the receiver for NRZ data. Manchester
encoding always produces a transition at the
center of the bit cell. If the transition is 0 to I,

the bit is a O. If the transition is I to 0, the bit
is a!.
Auto Echo and Local Loopback. The ASCC is
capable of automatically echoing everything it
receives. In Auto Echo mode, RxD is connected to TxD internally. Auto Echo mode can
be used with NRZI or FM encoding with no
additional delay, because the data stream is
not decoded before retransmission. In Auto
Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter is
actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The ASCC is also capable of local loopback.
In this mode TxD is connected to RxD internally, just as in Auto Echo mode. However, in
Local Loopback mode, the internal transmit
data is tied to the mternal receive data and
RxD is ignored (except to be echoed out via
TxD). The CTS and DCD
inputs arE! also ignored as transmit and receive
enables. However, transitions on these inputs
can still cause interrupts. Local Loopback
works with NRZ, NRZI or FM coding of the data
stream.

110 Interface Capabilities. The ASCC offers
the choice of Polling, Interrupt (vectored or
nonvectored), and Block Transfer modes to
transfer data, status, and control information to
and from the CPU. The Block Transfer mode
can be implemented under CPU or DMA
control.
Polling. All interrupts are disabled. Three
status registers in the ASCC are automatically
updated whenever any function is performed.
The idea behind polling is for the CPU to
periodically read a status register until the
register contents indicate the need for data to
be transferred. Only one register needs to be
read; depending on its contents, the CPU
either writes data, reads data, or continues.
Two bits in the register indicate the need for

DATA
NRZ

NRZI

\
\

I
I

\
\

FMt

FM.

MANCHBSTBR

Figure 4. Data Encoding Methods

864

2016·005

Functional
Description
(Continued)

data transfer. An alternative is a poll of the
Interrupt Pending register to determine the
source of an interrupt. The status for both
channels resides in one register.
Interrupts. When an ASCC responds to an
Interrupt Acknowledge signal (!NTACK) from
the CPU, an interrupt vector may be placed on
the data bus. This vector is written in WR2 and
may be read in RR2A or RR2B (FIgures 8
and 9).
To speed interrupt response time, the ASCC
can modify three bits in this vector to indicate
status. If the vector IS read in Channel A,
status is never included; If it IS read m
Channel B, status is always included.
Each of the six sources of interrupts in the
ASCC (Transmit, Receive, and External/Status
interrupts in both channels) has three bItS
associated with the interrupt source: Interrupt
Pending (IP), Interrupt Under Service (IUS),
and Interrupt Enable (IE). Operahon of the IE
bit is straightforward. If the IE bit is set for a
given interrupt source, then that source can
request interrupts. The exception is when the
MIE (Master Interrupt Enable) bit in WR9 is
reset and no interrupts may be requested. The
IE bits are write only.
The other two bits are related to the interrupt priority chain (Figure 5). As a
microprocessor peripheral, the ASCC may
request an interrupt only when no higher
priority device is requesting one, e.g., when
lEI is High. If the device in question requests
an interrupt, it pulls down INT. The CPU then
responds with INTACK, and the interrupting
device places the vector on the data bus.
In the ASCC, the IP bit signals a need for
interrupt servicing. When an IP bit is I and
the lEI input is High, the !NT output is pulled
Low, requesting an interrupt. In the ASCC, If
the IE bit is not set by enabling interrupts,
then the IP for that source can never be set.
The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request
is bemg servlCed. If an IUS is set, all interrupt
sources of lower priority in the ASCC and
external to the ASCC are prevented from
requestmg interrupts. Jhe mternai mterrupt

PERIPHERAL
lEI 00-07

iNf

sources are inhibited by the state of the internal daisy chain, while lower priority devices
are inhibited by the IEO output of the ASCC
being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an
Interrupt Acknowledge cycle if there are no
hIgher priority devices requesting interrupts.
There are three types of interrupts:
Transmit, Receive, and External/Status. Each
interrupt type is enabled under program control with Channel A having higher priority
than Channel B, and with Receiver, Transmit,
and External/Status interrupts prioritized in
that order within each channel. When the
Transmit interrupt is enabled, the CPU is
interrupted when the transmit buffer becomes
empty. (This implies that the transmitter must
have had a data character written into it so
that it can become empty.) When enabled, the
receiver can interrupt the CPU in one of three
ways:
• Interrupt on First Receive Character or
SpeCial Receive Condition.

• Interrupt on Special ReceIve Condition
Only.
Interrupt on First Character or Special Condition and Interrupt on SpeCial Condition Only
are typically used with the Block Transfer
mode. A Special Receive Condition is a
receiver overrun, and, optionally, a parity
error. The Special Receive Condition interrupt
is different from an ordinary receive character
available interrupt only in the status placed in
the vector during the Interrupt Acknowledge
cycle. In Interrupt on First Receive Character,
an interrupt can occur from Special Receive
Conditions any time after the first receive
character interrupt.
The main function of the External/Status
interrupt is to monitor the signal transitions of
the CTS, DCD, and ill pins; however, an
External/Status interrupt is also caused by a
Transmit Underrun condition, or a zero count
in the baud rate generator, or by the detection
ot a Break.

lEI 00-01

!NT

PERIPHERAL

lNTACK lEO

lEI 00-07

iNT INTACK

+5V

Do-D7V-______________________________________________

~

INT.-------------~,r---------------+--~--------------~_+~
INTACK~--------------~

__________________

~

_________________"

Figure 5. Interrupt Schedule

2016·006

w
....

i

• Interrupt on All Receive Characters or
Special Receive Condition.

PERIPHERAL

INTACK lEO

aen

865

Functional
Description
(Continued)

CPU/DMA Block Transfer. The ASCC provides a Block Transfer mode to accommodate
CPU block transfer functions and DMA controllers. The Block Transfer mode uses the
WAIT/ REQUEST output in conjunction with
the WaiVRequest bits in WRl. The WAIT/
REQUEST output can be defined under software control as a WAIT line in the CPU Block
Transfer mode or as a REQUEST line in the

DMA Block Transfer mode.
To a DMA controller, the ASCC REQUEST
output indicates that the ASCC is ready to
transfer data to or from memory. To the CPU,
the WAIT line indicates that the ASCC is not
ready to transfer data, thereby requesting that
the CPU extend the I/O cycle. The DTR/
REQUEST line allows full-duplex operation
under DMA control.

Architecture

The ASCC internal structure includes
two full-duplex channels, two baud rate
generators, internal control and interrupt
logiC, and a bus interface to a nonmultiplexed
bus. Associated with each channel are a
number of read and write registers for mode
control and status information, as well as logic
necessary to interface to modems or other
external devices (Figure 6).
The logic for both channels provides
formats, synchronization, and validation for

data transferred to and from the channel interface. The modem control inputs are monitored
by the control logic under program control.
All of the modem control signals are generalpurpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) registers, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that determines the

} SERIAL DATA
' 4 - - } CHANNEL CLOCKS

III
INTERNAL

WAITfREQUEST

CONTROL
LOGIC

MODEM, DMA, OR
}

OTHER CONTROLS

}

MODEM, DMA, OR
OTHER CONTROLS

DATA

CONTROL

INTERRUPT
CONTROL

INTERRUPT

LINES

LOGIC

CONTROL

} SERIAL DATA

ttt

} CHANNEL CLOCKS

III

+SVGND PCLK

WAIT/REQUEST

Figure 6. Block Diagram of ASCC Architecture

866

2244-005

~

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0o ..n
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as:
c::
n

CD c..1'l

~tiI
CPU 110

SR GENERATOR

INPUT

~

BRGENERATOR
...._ _ _ _ _...._ _ _ _ _...' ~ OUTPUT

RECEIVE

RECEIVE

DATA

ERROR

FIFO

FIFO

TRANSMIT
CLOCK

R,D

DPLL

DPLL OUTPUT

BA GENERATOR OUTPUT

~

M

DPLL OUTPUT - - - -..
- -

TRxC----.

CLOCK
MUX

RT,C-"""f"--.

RFCElVE CLOCK

TRANSMIT CLOCK
DPLLCLOCK
SR GENERATOR CLOCK

iii
(OSCILLATOR)

8l
.....

Figure 7_ Data Path

33S1l1£Saz

Architecture
(Contmued)

baud rate. Finally, associated with the interrupt logic is a write register for the interrupt
vector accessible through either channel, a
write only Master Interrupt Control register
and three read registers: one containing the
vector with status infomation (Channel B only),
one containing the vector without status
(Channel A only), and one containing the
Interrupt Pending bits (Channel A only).
The registers for each channel are
designated as follows:
WRO-WRI5 - Write Registers 0-5,8-15.
RRO-RR3, RRlO, RR12, RR13, RR15 - Read
Registers 0 through 3, 10, 12, 13, 15.
Table 1 lists the functions assigned to each
read or write register. The ASCC contains only one WR2 and WR9, but they can be accessed by either channel. All other registers are
paired (one for each channel).
Data Path. The transmit and receive data path
illustrated in Figure 7 is identical for both
channels. The receiver has three 8-bit buffer
registers in an FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme
creates additional time for the CPU to service
an interrupt at the beginning of a block of
high speed data. Incoming data is routed
through one of several paths depending on the
selected mode (the character length also determines the data path).
The transmitter has an 8-bit Transmit Data
buffer register loaded from the internal data
bus and an ll-bit Transmit Shift register that
can be loaded from the Transmit Data register.

Programming

868

The ASCC contains 11 write registers in
each channel that are programmed by the
system separately to configure the functional
personality of the channels.
In the ASCC, register addressing is direct
for the data registers only, which are selected
by a High on the Die pin. In all other cases
(with the exception of WRO and RRO), programming the write registers requires two
write operations and reading the read registers
requires both a write and a read operation.
The first write is to WRO and contains three
bits that point to the selected register. The second write is the actual control word for the

Read Register FuncUoDS

RRO

TransmlVRecelve buffer status and External status

RRI

Special ReceIve Condlhon status

RR2

Modlhed interrupt vector (Channel B only)
UnmodIfied mterrupt vector (Channel A only)

RR3

Interrupt Pending b,ts (Channel A only)

RR8

ReceIve buffer

RRJO

MIscellaneous status

RRI2

Lower byte of baud rate generator I1me constant

RRl3

Upper b\,te of baud rate generator time constant

RRl5

External/Status mterrupt information
Write Register FuncUons

WRO

CRC mitiallze. iml1allzal1on commands for the
various modes, Register Pomters.

WRI

TransmlVReceive mterrupt and data transfer mode
definition

WR2

Interrupt vector (accessed through either channel)

WR3

Receive parameters and control

WR4

Transmlt/Receive mlscellaneous parameters and
modes

WR5

TransmIt parameters and controls

WR8
WR9

TransmIt buffer
Master mterrupt control and reset (accessed
through eIther channel)

WRJO

MIscellaneous transmitter/receiver control blls

WRll
WRl2
WRl3
WRl4
WRl5

Clock mode control
Lower byte of baud rate generator I1me constant
Upper byte of baud rate generator I1me constant
MIscellaneous control b,ts
External/Status mterrupt control
Table I. Read and Write Register Functions

selected register, and if the second operation
IS read, the selected read register is accessed.
All of the registers in the ASCC, including the
data registers, may be accessed in this fashion.
The pointer bits are automatically cleared after
the read or write operation so that WRO (or
RRO) is addressed again.
The system program first issues a series of
commands to initialize the basic mode of
operation. For example, the character length,
clock rate, number of stop bits, even or odd
parity might be set first. Then the interrupt
mode would be set, and finally, receiver or
transmitter enable.

Programming Read Registers. The ASCC contains eight

(Contmued)

read registers (actually nine, counting the
receive buffer (RRB) in each channel). Four of
these may be read to obtain status information
(RRO, RRI, RRIO, and RRIS). Two registers
(RRI2 and RRI3) may be read to learn the
baud rate generator time constant. RR2 contains either the unmodified interrupt vector
(Channel A) or the vector modified by status
information (Channel B). RR3 contains the

Interrupt Pending (lP) bits (Channel A).
Figure B shows the formats for each read
register.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring; e.g.,
when the interrupt vector indicates a Special
Receive Condition interrupt, all the appropriate error bits can be read from a single
register (RRl).

Read Register 0

Read Register 10

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

L
~~~

~ R,CHARACTERAVAILABLE
ZERO COUNT
Tx BUFFER EMPTY
DCD

RINO INDICATOR

,

CTS

BREAK

I~~
~ ~WOCLOCKSMISSING

IIen

...w

ONE CLOCK MISSING

Read Register I

fi

Read Register 12

LOWER BYTE OF
TIME CONSTANT

Read Register 2

Read Register 13

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

INTERRUPT VECTOR·

-MODIFIED IN B CHANNEL

Read Register 3

~~

UPPER BYTE OF
TIME CONSTANT

Read Register 15

1~1~1~1~1~1~1~I~i

~~~

~CHANNELBEXTISTATIP'
CHANNEL B Tx ,PCHANNEL B Rx IP-

CHANNEL A EXT/STAT Ip·

CHANNEL A Tx

,p.

CHANNEL A Rx IP-

o

I~~:.~",.

~
~CTSIE
,

o

BREAK IE

-AI.WAYS 0 IN B CHANNEL

Figure 8. Read Register Bit Functions

2244·007

869

Programming Write Registers. The ASCC contains 11 write
(Continued)
registers (12 counting WR8, the transmit
buffer) in each channel. These write registers
are programmed separately to configure the
functional "personality" of the channels. In
addition, there are two registers (WR2 and
Write Register 0

WR9) shared by the two channels that may be
accessed through either of them. WR2 contains
the interrupt vector for both channels, while
WR9 contains the interrupt control bits.
Figure 9 shows the format of each write
register.
Write Register 3
I~I~I~I~I~I~I~I~I

o
o
o

0

0

0

1 REGISTER 1

1

0

o

1

1 REGISTER 3

REGISTER 0
REGISTER 2

f

0

1

0

1

1

REGISTER"

1

1

o

0

o

0

REGISTER 8

1

REGISTER 10

REGISTER 5
0

NULL CODe

o
o

RE"'STER 8j

NULL CODE

1

1 REGISTER 11

1

0

REGISTER 12

1

0

REGISTER 13

1
1

0 REOISTER 14
1 REGISTER 16

Rx 5 BITS/CHARACTER

1

Rx 7 BITS/CHARACTER

1

0

Rx 6 BITS/CHARACTER

1

1

Rx 8 BITS/CHARACTER

•

o

0

o
o

0

POINT HIGH

1

RESET EXTISTAT INTERRUPTS

o

1

NULL CODe

1

0

1

0

1

1
1

1
1

0

ERROR RESET

1

RESET HIGHEST IUS

0

0

Write Register 4

i

I~I~I~I~I~I~I~I~I

NULL CODE

o
o

ENABLE INT ON NEXT Rx CHARACTER
RESET TxlNT PENDING

0

1

~ ::::~ ::::'~DD
DO NOT PROGRAM
1 STOP BIT/CHARACTER

1

0

1 VI STOP BITSfCHARACTER

1

1

2 STOP BITS/CHARACTER

X 1 CLOCK MODE

·WITH POINT HIGH COMMAND

Xi6 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE

Write Register 1
I~I~I~I~I~I~I~I~I

~

Write Register 5

~L EXT INT ENABLE

I~I~I~I~I~I~I~I~I

Tx INT ENABLE

PARITY IS SPECIAL CONDITION

o

0

Rx INT DISABLE

o

1

Rx INT ON FIRST CHARACTER OR SPECIAL CONDITION

1

OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION

1

1

RxlNTONSPECIALCONDlTIONONLY

' - - - - - - WAIT/DMA REQUEST ON

RECEIV~

' - - - - - - - WArf/DMA REQUEST FUNCTION
' - - - - - - - - WAIT/DMA REQUEST ENABLE

o

0

Tx 5 BITS (OR LESS)lCHARACTER

o

1

Tx 7 BITS/CHARACTER

1

0

Tx 6 BITs/cHARACTER

1

1

Tx 6 BITs/CHARACTER

'-------- DTR

Write Register 2

~~

INTERRUPT VECTOR

v,

Figure 9. Write Register Bit Functions

870

2244·007

Write Register 12

Programming Write Register 9
(Continued)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

LL.:::
~~

DLC

MIE

:rATUI HIGHlIT'lTIJI"'mW

ll!~

LOWER BYTE OF
TIME CONSTANT

FORCE HARDWARE RESET

Write Register 13
I~I~I~I~I~I~I~I~I

Write Register 10

ll!~

I~I~I~I~I~I~I~I~I

~j
o
o

1

NAZI

1

0

Flii (TRANSITION ... 1)

1

1

FYO (TRANSITION" 0)

0

HRZ

Write Register 14

IL

L...:::
~

Write Register 11

1

I...

I~I~I~I~I~I~I~I~I

I

I~I~I~I~I~I~I~I~I

.RGEN....TOREN. .LE

BR GENERATOR SOURCE

In'RIREOUEST FUNCTION
AUTO ECHO
LOCAL LOOPBACK

0

0

0

,

0

TIiiill OUT.

o

1

TiW! OUT

.. TRANSMIT CLOCK

0

1

0

TRxC OUT

= BR GENERATOR OUTPUT

1

1

,

0

UPPER BYTE OF

TIME CONSTANT

XTAL OUTPUT

~ OUT,. DPLL OUTPUT

0

0

0
0

TRANSMIT CLOCK = R'fiC PIN

0

,

,

fIfIillOil

,

NULL COMMAND

ENTER SEARCH MODE

RESET MISSING CLOCK
DUllE DPLL

,
0

,,,
0

SET SOURCE .. BR GENERATOR
SET SOURCE

III

RTiC

SET FM MODE

SET NAZI MODE

TRANSMIT CLOCK '"' TRxC PIN
TRANSMIT CLOCK. IR GENERATOR OUTPUT
TRANSMIT CLOCK - DPLL OUTPUT

Write Register 15
I~I~I~I~I~I~I~I~I
RECEIVE CLOCK .. BR GENERATOR OUTPUT

1-_ _ _ _ _ _ _ fi'fiC5 XTAUNOXTAL

Figure 9. Write Register Bit FlIDCtlons (Contmued)

2244-007

871

Timing

The ASCC generates internal control signals
from WR and RD that are related to PCLK.
Since PLCK has no phase relationship with
WR and RD, the circuitry generating these internal control signals must provide time for
metastable conditions to disappear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involving the ASCC. The recovery
time required for proper operation is specified
from the riSing edge of WR or RD in the first
All. DIe

transaction involving the ASCC to the falling
edge of WR or RD in the second transaction
involving the ASCC. This time must be at least
6 PLCK cycles plus 200 ns.
Read Cycle Timing. Figure 10 illustrates read
cycle timing, Addresses on AlB and D/C and
the status on INTACK must remain stable
throughout the cycle. If CE falls after RD
falls,or rises before RD rises, the effective RD
is shortened.

X
x:::
----'---------ADDRESS VALID

\ .....- 1

\
1

\ \ -_ _ _ _- J

Do-D?---------~«(:::=X

DATAYALID )

Figure 10. Read Cycle TIming

throughout the cycle. If CE falls after WR falls
or rises before WR rises, the effective WR is
shortened.

Write Cycle Timing. Figure II illustrates
write cycle timing. Addresses on AlB and D/C
and the status on INTACK must remain stable
~,~ti ________-J)(~

______________AD_D_RU_._Y_A_UD_______________

X:::

\_--1

\

\ _____......1

Do-D?------__________~(==::::~DA:U~Y:AL~ID~::::)~------Flgurell. Write Cycle Timing

when RD falls, the acknowledge cycle was intended for the ASCC. In this case, the ASCC
may be programmed to respond to RD Low by
placing its interrupt vector on Do-D7 and sets
the appropriate Interrupt-Under-Service latch
internally.

Interrupt Acknowledge Cycle Timing. Figure
12 illustrates interrupt acknowledge cycle timing. Between the time INTACK goes low and
the falling edge of RD, the internal and external lEI/lEO daisy chains settle. If there is an
interrupt pending the ASCC and lEI is High

:~-----

Do-D?

//

(

Figure 12. Interrupt Acknowledge Cycle Timing

872

2023-005,006,007

Absolute
Maximum
Ratings

Voltages on all pins with respect
to GND ................... - O.3V to + 7.0V
Operating Ambient
Temperature ....... See Ordering Information
Storage Temperature ........ - 65°C to + 150°C

Standard
Test
Conditions

The DC characterisbcs and capacitance sections below apply for the folloWing standard test
conditions, unless otherwise noted. All voltages
are referenced to GND. Positive current flows
into the referenced pin.
Standard conditions are as follows:
• +4.75 V

S

Vee

S

+5.25 V

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.

Thls IS a stress rating only; operation of the devlce at any
condItIon above those mdlCated m the operahonal sechons
of these speclhcations IS not ImplIed. Exposure to absolute
maXImum ratmg conditions for extended penods may affect
deVICe reliabIlity.

The Ordering Information section lists temperature ranges and product numbers. Package
drawmgs are in the Package Information section
in this book. Refer to the Literature List for addibonal documentation.
All ac parameters assume a load capacitance
of 50 pf max.

• GND = 0 V
• TA as speCified in Ordering Information
+5V

FROM OUTPUT
UNDER TEST

Figure 13. Standard Test Load

DC
Characteristics

Symbol
VIH
VIL
VOH
VOL
IlL

1m
Icc

iI

+5V

2.1K

'·'K
SOp.

Figure 14. Open-Drain Test Load

Parameter

Min

Max

Unit

Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current

2.0
-0.3
2.4

Vee +0.3
0.8

V
V
V
V

0.4
±JO.O
±JO.O
250

pA
pA

Condition

IOH =
IOL=
0.4 :5
0.4 :5

-250 pA
+2.0 mA
VIN :5 + 2.4V
VOUT :5 +2.4V

rnA

Vee = 5 V ± 5% unless otherwIse speClfied, over speCIfied temperature range.

Capacitance

Symbol

Parameter
Input Capacitance
Output Capacitance
Bldlrechonal CapacItance

Min

Max

Unit

10
15
20

pi
pi
pi

Test Condition

f = 1 MHz, over speClfIed temperature range
Unmeasured pms returned to ground.

8085·006,001

873

Read and
Write
Timing

PCLK

\..........~~
~

A/B,D/e

:)~-

~~~
J(

~
~\

~~
---.

--®

~(i3~

-I®

----0-~

.......J

-@---------oo

i-@-

------®- r----

@;
00-07
READ

ACTIVE

®- ~

)!

---®------

--0-1\

VAL.ID

®25
27

-::~ ~
1

~
DO-D7
WRITE

)Q:
®-i-

}(

r--i-®

----@- f-----

W/REQ
WAIT

\,-32

WIREQ
REQUEST

DTR/REQ

--:::---W
'i4'

=4

I-®-J

REQUeST

w

\.

-

'ii'

4 MHz
No.

Symbol

Parameter

Min

Max

6 MHz
Min
Max

Notes*t

I
TwPCI
PCLK Low WIdth
105
2000
70
1000
2
TwPCh
PCLK HIgh WIdth
105
2000
70
1000
3
TIPC
PCLK Fall TIme
20
10
4
TrPC
PCLK RIse TIme
20
15
5-TcPC
PCLK Cycle TIme - - - - - - - - - - - - 2 5 0 - 4 0 0 0 --165 -2000 - - - - 6
TsA(WR)
Address to WR I Setup TIme
80
80
7
ThA(WR)
Address to WR 1 Hold TIme
0
0
8
TsA(RD)
Address to RD I Setup Time
80
80
9
ThA(RD)
Address to RD 1 Hold TIme
0
0
IO-TsIA(PC)---INTACK to PCLK 1 Setup TIme
0
0 -------II
TsIAI(WR)
INTACK to WR I Setup TIme
200
200
12
ThIA(WR)
INTACK to WR 1 Hold TIme
0
0
13
TsIAI(RD)
INTACK to RD I Setup TIme
200
200
14
ThIA(RD)
INTACK to RD 1 Hold TIme
0
0
15-ThIA(PC)--INTACK to PCLK 1 Hold TIme
100
100-------16
TsCE1(WR)
CE Low to WR I Setup TIme
0
0
17
ThCE(WR)
CE to WR 1 Hold TIme
0
0
18
TsCEh(WR)
CE HIgh to WR I Setup TIme
100
70
19
TsCE1(RD)
CE Low to RD I Setup Time
0
0
I
20
ThCE(RD)
CE to RD 1 Hold TIme
0
0
I
21-TsCEh(RD)--CE HIgh to RD I Setup TIme
100
70 - - - - - - 1 22
TwRDI
RD Low WIdth
390
250
I
23
TdRD(DRA)
RD I to Read Data Achve Delay
0
0
24
TdRDr(DR)
RD 1 to Read Data Not Vahd Delay
0
0
25
TdRDI(DR)
RD I to Read Data Vahd Delay
250
180
26
TdRD(DRz)
RD 1 to Read Data Float Delay
70
45
2
NOTES
1. Parameter does not apply to Interrupt Acknowledge
transactIons

874

2 Float delay IS clefmed as the hme required for a ± 0.5 V change
1U the output wlth a maximum de load and mlnlmUm ae load .
• Tlmmgs are prehmmary and subject to change,
t Umls 10 nanoseconds (os).

2023-008

Interrupt
Acknowledge
Timing

PCL!(

IIo-D1---+----H~8l----

..

,

...E

Reset
Timing

Cycle
Timing

Ci

/

_---J

;,~--~\,------

~WWR---'~·====~\==:®_Q~_-~~~~/~====~,~
4MBz
No.

Symbol

Parameter

Min

Max

____

6MBz
Min

Max

Notes*t

27
TdA(DR)
Address Required Vahd to Read Data Vahd Delay
590
420
390
250
WR Low Width
28
TwWRl
29
TsDW(WR)
Write Data to WR , Setup Time
0
o
30
ThDW(WR)
Wnte Data to WR I Hold Time
0
o
31 -TdWR(W)--WR , to Walt Valid Delay - - - - - - - - - - - - 240 - - - - - 2 0 0 - - - 4 32
TdRD(W)
RD , to Wait Vahd Delay
240
200
4
33
TdWRf(REQ)
WR , to iN/REQ Not Vahd Delay
240
200
RD , to iNlREQ Not Vahd Delay
34
TdRDf(REQ)
240
200
35
TdWRr(REQ)
WR I to DTR/REQ'Not Vahd Delay
5TcPC
5TcPC
+250
+300
36 -TdRDr(REQ)--RD I to DTR/REQ Not Vahd Delay - - - - - - - - - 5TcPC -----5TcPC - - - - +300
+250
37
TdPC(lNT)
PCLK , to INT Vahd Delay
4
500
500
38
TdIAI(TID)
INTACK to TID , (Acknowledge) Delay
5
39
TwRDA
RD (Acknowledge) Width
285
250
40 -TdRDA(DR)--RD , (Acknowledge) to Read Data Vahd Delay------190 - - - - - 1 8 0 - - - - 41
TsIEI(RDA)
lEI to RD , (Acknowledge) Setup Time
120
100
42
ThIEI(RDA)
lEI to RD I (Acknowledge) Hold Time
0
o
43
TdIEI(lEO)
lEI to lEO Delay Time
120
100
44
TdPC(IEO)
PCLK I to lEO Delay
250
250
45 -TdRDA(INT) --RD , to INT Inachve Delay - - - - - - - - - - - -500 - - - - - 5 0 0 - - - 4 46
TdRD(WRQ)
RD I to WR , Delay for No Reset
30
15
47
TdWRQ(RD)
WR I to RD , Delay for No Reset
30
30
TwRES
WR and RD Comcident Low for Reset
250
250
48
6TcPC
6TcPC
49
Trc
Vahd Access Recovery Time
+ 130
3
+200
NOTES
3 Parameter applies only between transachons Involvmg the
ASCC
Open-dram output, measured with open-dram test load
Pdrameter IS system dependent For any ASCC In the daiSY
cham, TdIA1(RD) must be greater than the sum of TdPC(lEO)
2023,009, 010,011

for the hlghe'>t PrIOrIty deVice In the ddl~Y cham, TslEl(RDA)
for the ASCC, and TdIEIf(lEO) for each deVice separatmg them
In the daiSY cham
* Tlmmgs dre prelimmary and subject to change.
t Umts In nanoseconds (ns)

875

General
Timing

PCLK

W/REQ
REQUEST

W/REQ
WAIT

ATxC. TA.e
RECENE

RxD

fiiC.

RTxC

TRANSMIT

TxD

TR.C
OUTPUT

ii'i'iii

\

~

\

\'--_......1

lfi'i, RD, ill

876

2244-008

4 MHz

No.

Symbol

Parameter

Min

6 MHz

Max

Min

Max

1 TdPC(REQ)
PCLK I to WIREQ Vahd Delay
250
250
TdPC(W)
PCLK I to Walt Inachve Delay
350
350
2
3
TsRXC(PC)
RxC t to PCLK t Setup TIme (PCLK
4 case only)
80 TwPCI
70 TwPCI
4
TsRXD(RXCr)
RxD to RxC t Setup TIme (Xl Mode)
0
0
5-ThRXD(RXCr)-RxD to RxC t Hold Time (Xl Mode)
150
150
6
TsRXD(RXCf)
RxD to RxC I Setup TIme (XI Mode)
0
0
ThRXD(RXCf)
RxD to RxC I Hold TIme (Xl Mode)
150
150
7
TsTXC(PC)
TxC I to PCLK t Setup TIme
0
8
0
TdTXCf(TXD)
9
TxC I to TxD Delay (Xl Mode)
300
300
10-TdTXCr(TXD)-TxC t to TxD Delay (XI M o d e ) - - - - - - - - - - 300
dOO
11
TdTXD(TRX)
TxD to TRxC Delay (Send Clock Echo)
12
TwRTXh
RTxC HIgh Width
180
180
TwRTXl
RTxC Low WIdth
13
180
180
TcRTX
RTxC Cycle Time
400
400
14
15-TcRTXX---Crystal OSCIllator P e r i o d - - - - - - - - - - -250-1000--250-1000
16
TwTRXh
TRxC HIgh WIdth
180
180
17
TwTRXl
TRxC Low WIdth
180
180
TcTRX
TRxC Cycle TIme
400
400
18
TwEXT
DCD or CTS or RI Pulse WIdth
200
19
200
NOTES'
1 RxC IS RTxC or TRxC, whIchever IS supplymg the receive
clock.
2. TxC IS TRxC or RTxC, whIchever IS supplymg the transmIt

clock

Both RTxC and Hi have 30 pF capacItors to ground connected to them.

Notes*t

1,4
1
11,5
1,5
2,4
2
2,56
6
6
36
6
6

4. Parameter applies only if the data rate IS one-fourth the PCLK
rate 1n all other cases, no phase relatIonship between RxC and
PCLK or TxC and PCLK

IS

reqUlred.

5 Parameter applies only to FM encodmg/decodlng
6. Parameter applIes only for transmitter and receiver, DPLL and
baud rate generator hmmg requIrements are Identical to chip

PCLK requIrements
.. TImmgs are prelimmary and subject to change
t Umts m nanoseconds (ns)

877

N
00

...IIIen
W

Wi
nn

System
Timing

RTaC, TRxC
RECEIVE

W'RI:Q
REQUEST

W'RI:Q
WAIT

__________________+-______- - J

RTxC, TRxe
TRANSMIT

WIiiEa
REQUEST

-0------~--------------

DTRIRiQ
REQUEST

CTS, DeD,RI

No.

Symbol

t

j

(j)

4MB.

Parameter

Min

Max

6MH.
Mln
Max

Notes*t

12
8
12
2
8
12
1,2
12
8
8
1,2
16
10
16
10
3
TdRXC(INT)
RxC t to INT Valid Delay
4 -TdTXC(REQ) - - TxC I to WIREQ Valid Delay - - - - - - - - 5 - - 8 - - - 5 - - 8 - - - - - 3 - 1,3
5
TdTXC(W)
TxC I to Wait Inactive Delay
8
5
8
5
7
4
7
3
6
TdTXC(DRQ)
TxC I to DTR/REQ Valid Delay
4
1,3
TdTXC(INT)
10
6
6
10
TxC I to INT Valid Delay
7
6
2
DCD or CTS Transition to INT Valid Delay
2
6
TdEXT(lNT)
8
2

TdRXC(REQ)

RxC t to W/REQ Valid Delay

TdRXC(W)

RxC I to Wait Inactive Delay

NOTES:
1. (}pen-dram output, measured wIth open-dram test load.
2. RxC is RTxC or TRxC, whIchever IS supplymg the receIve
clock.
3. Txe IS TRxC or RTxC, whIchever IS supplymg the transmIt

*

TImmgs are prelimmary and subject to change.

t Umts equal to TePC.

clock.

878

2244-009

ORDERING INFORMATION
Z8531 ASCC, 4.0 MHz
44-pinPCC
Z8531 VS

Z8531 ASCC, 4.0 MHz
40-plnDIP
Z8531 PS
Z8531 CS

Z8531 ASCC, 6.0 MHz
44-pinPCC
Z8531 A VS

Z8531 A ASCC, 6.0 MHz
40-plnDIP
Z8531 A PS
Z8531ACS

Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = O°Cto + 70°C
E = -400Cto+85°C
M*= -55°C to +125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Protopack
Low Profile Proto pack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DI P, 0 °C to + 70°C.
tAvaiiable soon .
• For Military Orders. contact your local Zllog Sales Office for Military Electrical Specifications

00-2244-03

879

18536 CIO
Coaater/TiDler aad
Parallel I/O Uait
Product
Specificalioa

Zilog

April 1985

Features

General
Description

• Two independent 8-bit, double-buffered,
bidirectional I/O ports plus a 4-bit
special-purpose I/O port. I/O ports
feature programmable polarity,
programmable direction (Bit mode), "pulse
catchers," and programmable opendrain outputs.

• Flexible pattern-recognition logie, programmable as a 16-vector interrupt controller.

• Four handshake modes, including 3-Wire
(like the IEEE-488).

• Three independent 16-bit counter/timers
with up to four external access lines per
counter/timer (count input, output, gate,
and trigger), and three output duty cycles
(pulsed, one-shot, and square-wave),
programmable as retriggerable or
nonretriggerable.

• REQUESTIWAIT signal for high-speed data
transfer.

• Easy to use since all registers are
read/write.

The Z8536 CIO Counter/Timer and
Parallel I/O element is a general-purpose
peripheral circuit, satisfying most counter/
timer and parallel I/O needs encountered in
system designs. This versatile device contains
three I/O ports and three counter/timers. Many
programmable options tailor its configuration
to specific applications. The use of the device
is simplified by making all internal registers

(command, status, and data) readable and
(except for status bits) writable. In addition,
each register is given its own unique internal
address, so that any register can be accessed
in two operations. All data registers can be
directly accessed in a single operation. The
CIO is easily interfaced to all popular
microprocessors.

D,
D,
D,

'"

Rli

iIiil
aND

pa,
pa,
pa,
pa,
P",

pa,
pa,
pa,
PCLK

A<
PA<
PA,
P",
PAa

p....
PA,
PA,
PA,

INTACK

lEO

iiii'
+sv

PC,

PC,

PC,

PC,

lEI

PCLK +SY aND

Fig.... 1. Pill Functions

2021-001.002

f1gure 2a. 40-pin Dual-in-Line Package (DIP).
Pin Assignments

881

~0 ~<:)
6

5

<:)'1. <:)<0 Q'?

Q~ Q".> Q'l-

4

1 44 43 42 41 40

3

2

Q"

Q~

{,«,

Wi!

7

39

NC

8

38

A.

GND

9

37

PAD

A,

PB.

10

36

PA,

PB,

11

35

PA,

PB,

12

PB,

13

PB4

Z8536

34

PA,

33

PA4

14

32

PA,

PB,

15

31

PAs

PBS

16

30

PA,

PB,

17

29

NC

elo

18 19 20 21 22 23 24 25 26 27 28

*' .@' ~o q,v~q,v"q,v'J,(p"J)(~4. ~*' ~CJ

q,VV

~

Figure 2b. 44-pin Chip Carrier.
Pin ASSignments

Pin
Description

882

Ao-Al' Address Lines (input). These two lines
are used to select the register involved in the
CPU transaction: Port A's Data register, Port
B's Data register, Port C's Data register, or a
control register.
CEo Chip Enable (input, active Low). A Low
level on this input enables the CIa to be read
from or written to.
Do-D,. Data Bus (bidirectional 3-state). These
eight data lines are used for transfers between
the CPU and the CIa.
lEI. Interrupt Enable In (input, active High).
lEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High lEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active
High). IEO is High only if lEI is High and the
CPU is not servicing an interrupt from the
requesting CIa or is not requesting an interrupt (Interrupt Acknowledge cycle only). IEO
is connected to the next lower priority device's
lEI input and thus inhibits interrupts from
lower priority devices.
INT. Interrupt Request (output, open-drain,
active Low). This signal is pulled Low when
the CIa requests an interrupt.
INTACK. Interrupt Acknowledge (input, active
Low). This input indicates to the CIa that an
Interrupt Acknowledge cycle is in progress.
INTACK must be synchronized to PCLK, and

it must be stable throughout the Interrupt
Acknowledge cycle.

PAo-PA7' Port A I/O lines (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer information between the CIa's Port A
and external devices.
PBg-PiJ? Port B I/O lines (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer information between the CIa's Port B
and external devices. May also be used to
provide external access to Counter/Timers
I and 2.
PCo-PCa. Port C I/O lines (bidirectional,
3-state, or open-drain). These four I/O lines
are used to provide handshake, WAIT, and
REQUEST lines for Ports A and B or to provide
external access to Counter/Timer 3 or access
to the CIa's Port C.
PCLK. Peripheral Clock (input, TTLcompatible). This is the clock used by the
internal control logic and the counter/timers
in timer mode. It does not have to be the
CPU clock.
RD*. Read (input, active Low). This signal
indicates that a CPU is reading from the CIa.
During an Interrupt Acknowledge cycle, this
signal gates the interrupt vector onto the data
bus if the CIa is the highest priority device
requesting an interrupt.

WR*. Write (input, active Low). This signal
indicates a CPU write to the CIa.
·When RD and WR are detected Low at the same bme (normally
an illegal condIhon), the CIO lS reset.

2021-003

Architecture

The CIO Counter/Timer and Parallel I/O
element (Figure 3) consists of a CPU interface,
three I/O ports (two general-purpose 8-bit
ports and one special-purpose 4-bit port),
three 16-bit counter/timers, an interrupt-

control logic block, and the internal-control
logic block. An extensive number of programmable options allow the user to tailor the configuration to best suit the specific application.

INTERRUPT
CONTROL
LOGIC

INTERNAL BUS

INTERRUPT
CONTROL

PORTe
I/O

III

en

=
S
Figure 3. CIO Bloclc Diagram

2021-004

883

Architecture
(Contmued)

TO COUNTERITlMERS 1 AND 2
(PORT B ONLy)
INTERNAL

~

2f

INPUT

BUFFERI
INVERTERS

AND

1',
CATCHER

OUTPUT

BUFFERI
INVERTERS

Figure 4. Port. A and B Block Diagram

The two general-purpose 8-bit I/O ports
(Figure 4) are identical, except that Port B can
be specified to provide external access to
Counter/Timers 1 and 2, Either port can be
programmed to be a handshake-driven,
double-buffered port (input, output, or bidirectional) or a control-type port with the direction
of each bit individually programmable, Each
port includes pattern-recognition logic, allowing interrupt generation when a specific pattern is detected, The pattern-recognition logic
can be programmed so the port functions like
a priority-interrupt controller, Ports A and B
can also be linked to form a 16-bit I/O port.
To control these capabilities, both ports contain 12 registers, Three of these registers, the
Input, Output, and Buffer registers, comprise
the data path registers, Two registers, the
Mode SpeCification and Handshake Specification registers, are used to define the mode of
the port and to speCify which handshake, if
any, is to be used, The reference pattern for
the pattern-recognition logic is defined via
three registers: the Pattern Polarity, Pattern
Transition, and Pattern Mask registers, The
detailed characteristics of each bit path (for

884

example, the direction of data flow or whether
a path is inverting or non inverting) are programmed using the Data Path Polarity, Data
Direction, and Special I/O Control registers,
The primary control and status bits are
grouped in a single register, the Command
and Status register, so that after the port is initially configured, only this register must be accessed frequently, To facilitate initialization,
the port logic is designed so that registers
associated with an unrequired capability are
ignored and do not have to be programmed,
The function of the special-purpose 4- bit
port, Port C (Figure 5), depends upon the
roles of' Ports A and B. Port C provides the
required handshake lines. Any bits of Port C
not used as handshake lines can be used as
I/O lines or to provide external access for the
third counter/timer,
Since Port C's function is defined primarily
by Ports A and B, only three registers (besides
the Data Input and Output registers) are
needed, These registers speCify the details of
each bit path: the Data Path Polarity, Data
Direction, and Special I/O Control registers,

2014·005

Architecture

TO COUNTERf
TIMER 3

(Continued)

INPUT

BUFFERI
INVERTERS
AND

".

CATCHER

PORT

110

OUTPUT
BUffERI

INVERTERS

C~~~~~L
PORT

)'-----~NTEANAL
~

POAT
gONTROL LINES

\

Fig..... &. Pori C Block Diagram

The three counter/timers (Figure 6) are all
Identical. Each is comprised of a 16-bit downcounter, a 16-blt Time Constant register
(which holds the value loaded into the downcounter), a 16-blt Current Count register (used
to read the contents of the down-counter), and
two 8-bit registers for control and status (the
Mode Specification and the Command and
Status registers).
The capabilities of the counter/timer are
numerous. Up to four port I/O lines can be
dedicated as external access lines for each
counter/timer: counter input, gate input, trigger Input, and counter/timer output. Three different counter/timer output duty cycles are
available: pulse, one-shot, or square-wave.

2014-()()6

The operation of the counter/timer can be programmed as either retriggerable or nonretriggerable, With these and other options, most
counter/timer applications are covered.
There are five registers (Master Interrupt
Control register, three Interrupt Vector
registers, and the Current Vector register)
associated with the Interrupt logic. In addition,
the ports' Command and Status registers and
the counter/timers' Command and Status
registers include bits associated with the interrupt logic. Each of these registers contains
three bits for Interrupt control and status:
Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE).

885

Architecture

INTERNAL

IUS

(Continued)

CURRENT
COUNT
REGISTER
(Msal)

l\r---...J

CURRENT
COUNT

1-_ _-'

R~s-:;m

I------l

COUNTER
CONTROL
UNES

TO PORT

Figure 6. Counter/Tlmer Block Diagram

Functional
Description

886

The following describes the functions
of the ports, pattern-recognition logic,
counter/timers, and interrupt logic.
I/O Port Operations. Of the CIO's three I/O
ports, two (Ports A and B) are generalpurpose, and the third (Port C) is a specialpurpose 4-bit port. Ports A and B can be configured as input, output, or bidirectional ports
with handshake. (Four different handshakes
are available.) They can also be linked to form
a single 16-bit port. If they are not used as
ports with handshake, they provide 16 input or
output bits with the data direction programmable on a bit-by-bit basis. Port B also provides access for CounterlTimers 1 and 2. In all
configurations, Ports A and B can be programmed to recognize specific data patterns
and to generate interrupts when the pattern is
encountered.
The four bits of Port C provide the handshake lines for Ports A and B when required.
A REQUESTIWAIT Ijne can also be provided
so that CIO transfers can be synchronized with
DMAs or CPUs. Any Port C bits not used for
handshake or REQUESTIWAIT can be used as
input or output bits (individually data-direction
programmable) or external access lines for
Counter/Timer 3. Port C does not contain any
pattern-recognition logic. It is, however,
capable of bit-addressable writes. With this
feature, any combination of bits can be set
and/or cleared while the other bits remain
undisturbed without first reading the register.
Bit Port Operations. In bit port operations, the

port's Data Direction register specifies the
direction of data flow for each bit. A 1
specifies an input bit, and a 0 specifies an output bit. If bits are used as I/O bits for a
counter/timer, they should be set as input or
output, as required.
The Data Path Polarity register provides the
capability of inverting the data path. A 1
specifies inverting, and a 0 specifies noninverting. All discussions of the port operations assume that the path is noninverting.
The value returned when reading an input
bit reflects the state of the input just prior to
the read. A l's catcher can be inserted into the
input data path by programming a 1 to the
corresponding bit pOSition of the port's Special
I/O Control register. When a 1 is detected at
the l's catcher input, its output is set to 1 until
it is cleared. The l's catcher is cleared
by writing a 0 to the bit. In all other cases,
attempted writes to input bits are ignored.
When Ports A and B include output bits,
reading the Data register returns the value
being output. Reads of Port C return the state
of the pin. Outputs can be specified as opendrain by writing a 1 to the corresponding bit of
the port's Special I/O Control register. Port C
has the additional feature of bit-addressable
writes. When writing to Port C, the four most
significant bits are used as a write protect
mask for the least significant bits (0-4, 1-5,
2-6, and 3-7). If the write protect bit is written
with ai, the state of the corresponding output
bit is not changed.

2014-007

Functional
Description
(Continued)

Ports with Handshake Operation. Ports A and
B can be specified as 8-bit input, output, or
bidirectional ports with handshake. The CIO
provides four different handshakes for its
ports: Interlocked, Strobed, Pulsed, and
3-Wire. When specified as a port with handshake, the transfer of data into and out of the
port and interrupt generation is under control
of the handshake logic. Port C provides the
handshake lines as shown in Table I. Any Port
C lines not used for handshake can be used as
simple I/O lines or as access lines for
Counter/Timer 3.
When Ports A and B are configured as ports
with handshake, they are double-buffered.
This allows for more relaxed interrupt service
routine response time. A second byte can be
input to or output from the port before the
interrupt for the first byte is serviced. Normally, the Interrupt Pending (IP) bit is set and
an interrupt is generated when data is shifted
into the Input register (input port) or out of the
Output register (output port). For input and
output ports, the IP is automatically cleared
when the data is read or written. In bidirectional ports, IP is cleared only by command.
When the Interrupt on Two Bytes (lTB) control
bit is set to 1, interrupts are generated only
when two bytes of data are available to be read
or written. This allows a minimum of 16 bits of
information to be transferred on each interrupt. With ITB set, the IP is not automatically
cleared until the second byte of data is read
or written.
When the Single Buffer (SB) bit is set to 1,
the port acts as if it is only single-buffered.
This is useful if the handshake line must be
stopped on a byte-by-byte basis.
Ports A and B can be linked to form a l6-bit
port by programming a 1 in the Port Link Control (PLC) bit. In this mode, only Port A's
Handshake Specification and Command and
Status registers are used. Port B must be
specified as a bit port. When linked, only Port
A has pattern-match capability. Port B's
Port AlB Configuration
Ports A and B: Bit Ports
PortA: Input or Output Port
(Interlocked. Strobed, or Pulsed
Handshake)'
Port B: Input or Output Port
(Interlocked, Strobed. or Pulsed
Handshake)'
Port A or B: Input Port (3-Wlre
Handshake)
Port A or B: Output Port (3-Wire
Handshake)
Port A or B: BIdirectional Port
(Interlocked or Strobed Handshake)

PCa

pattern-match capability must be disabled.
Also, when the ports are linked, Port B's Data
register must be read or written before
Port A's.
When a port is specified as a port with handshake, the type of port it is (input, output, or
bidirectional) determines the direction of data
flow. The data direction for the bidirectional
port is determined by a bit in Port C (Table 1).
In all cases, the contents of the Data Direction
register are ignored. The contents of the
Special I/O Control register apply only to output bits (3-state or open-drain). Inputs may not
have 1's catchers; therefore, those bits in the
Special I/O Control register are ignored. Port
C lines used for handshake should be programmed as inputs. The handshake specification overrides Port C's Data Direction register
for bits that must be outputs. The contents of
Port C's Data Path Polarity register still apply.
Interlocked Handshake. In the Interlocked
Handshake mode, the action of the CIO must
be acknowledged by the external device
before the next action can take place. Figure 7
shows timing for Interlocked Handshake. An
output port does not indicate that new data is
available until the external device indicates it
is ready for the data. Similarly, an input port
does not indicate that it is ready for new data
until the data source indicates that the
previous byte of the data is no longer
available, thereby acknowledging the input
port's acceptance of the last byte. This allows
the CIO to interface directly to the port of a Z8
microcomputer, a UPC, an FlO, an FIFO, or
to another CIO port with no external logic.
A 4-bit deskew timer can be inserted in the
Data Available (DAV) output for output ports.
As data is transferred to the Buffer register,
the deskew timer is triggered. After the
number of PCLK cycles specified by the
deskew timer time constant plus one, DAV is
allowed to go Low. The deskew timer therefore
guarantees that the output data is valid for a
speCified minimum amount of time before DA V
~

PCI

PCO

Bit I/O
RFD or DAV

BIt I/O
ACKIN

BIt I/O
REQUEST/WAIT
or Bit I/O

BIt I/O
BltVO

REQUEST/WAIT
or BIt I/O

Bit I/O

RFD or DAV

ACKIN

RFD (Output)

DAV (Input)

DAC (Output)

DA V (Output)

DAC (Input)

RFD or DAV

ACKIN

REQUEST/WAIT
or BIt VO
REQUEST/WAIT
or BIt VO
REQUEST/WAIT
or Bit I/O

RFD (Input)
IN/OUT

• Both Ports A and B can be speCifIed mput or output wlth Interlocked, Strobed, or Pulsed Handshake at the same bme If neither uses

REQUESTIWAI!.

Table I. Port C Bit Utilization

887

Functional
Description
(Continued)

goes Low. Deskew timers are available for output ports independent of the type of handshake
employed.
Strobed Handshake. In the Strobed Handshake mode, data is "strobed" into or out of
the port by the external logic. The falling edge
of the Acknowledge Input (ACKIN) strobes
data into or out of the port. Figure 7 shows
timing for the Strobed Handshake. In contrast
to the Interlocked handshake, the signal
indicating the port is ready for another data
transfer operates independently of the ACKIN
input. It is up to the external logic to ensure
that data overflows or underflows do not occur.
3-Wire Handshake. The 3-Wire Handshake is
designed for the situation in which one output
port is communicating with many input ports
simultaneously. It is essentially the same as the
Interlocked Handshake, except that two signals
are used to indicate if an input port is ready
for new data or if it has accepted the present
data. In the 3-Wire Handshake (Figure 8), the
rising edge of one status line indicates that the
port is ready for data, and the rising edge of
another status line indicates that the data has
been accepted. With the 3-Wire Handshake
the output lines cif many input ports can be '
bussed together with open-drain drivers; the
output port knows when all the ports have
accepted the data and are ready. This is the
INPUT HANDSHAKE

DATA:J(

same handshake as is used on the IEEE-488
bus. Because this handshake requires three
lines, only one port (either A or B) can be a
3-Wire Handshake port at a time. The 3-Wire
Handshake is not available in the bidirectional
mode. Because the port's direction can be
changed under software control, however,
bidirectional IEEE-488-type transfers can be
performed.
Pulsed Handshake. The Pulsed Handshake
(Figure 9) is designed to interface to
mechanical-type devices that require data to
be held for long periods of time and need
relatively wide pulses to gate the data into or
out of the device. The logic is the same as the
Interlocked Handshake mode, except that an
internal counter/timer is linked to the handshake logic. If the port is specified in the input
mode, the timer is inserted in the ACKIN path.
The external ACKIN input triggers the timer
and its output is used as the Interlocked Handshake's normal acknowledge input. If the port
is an output port, the timer is placed in the
Data Available (DAV) output path. The timer is
triggered when the normal Interlocked Handshake DAV output goes Low and the timer output is used as the actual DAV output. The
counter/timer maintains all of its normal
capabilities. This handshake is not available to
bidirectional ports.
OUTPUT HANDSHAKE

X'-_________

VALID

STROBED
HANDSHAKE-......r -

RFD

-

NEXT BYTE

DATA

.... , - - INTERLOCKED

DATA MOVED

DATA LATCHED
IN BUFFER REGISTER

HANDSHAKE

TO INPUT
REGISTER

BUFFER REGISTER
"EMPTIED"

NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER

Figure 7. Interlocked and Strobed Handshakes

OUTPUT HANDSHAKE

INPUT HANDSHAKE

DATA

==x

VALID

DAY

---I\\~

DAC

DAC
INPUT

OUTPUT

OUTPUT

DATA
RPD
'NPUT _ _ _ _ _ _..J

INPUT

RPD

X'-_________

_ _ _~-J

DiY

OUTPUT

BUFFER REGISTER
"EMPTIED"

NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER

Figure 8. 3·Wire Handshake

888

2014-008, 009

FUllctiollCl1
Descriptloll

(Continued)

REQUEST/WAIT Line Operation. Port C can
be programmed to provide a status signal output in addition to the normal handshake lines
for either Port A or B when used as a port with
handshake. The additional signal is either a
REQUEST or WAIT signal. The REQUEST
signal indicates when a port is ready to perform a data transfer via the CPU interface. It is
intended for use with a DMA-type device. The
WAIT signal provides synchronization for
transfers with a CPU. Three bits in the Port
Handshake Specification register provide controls for the REQUESTIWAIT logic. Because
the extra Port C line is used, only one port can
be specified as a port with a handshake and a
REQUESTIWAIT line. The other port must be
a bit port.
Operation of the REQUEST line is modified
by the state of the port's Interrupt on Two
Bytes (ITB) control bit. When ITB is 0, the
REQUEST line goes active as soon as the CIO
is ready for a data transfer. If ITB is 1,
REQUEST does not go active until two bytes
can be transferred. REQUEST stays active as
long as a byte is available to be read or
written.
The SPECIAL REQUEST function is reserved
for use with bidirectional ports only. In this
case, the REQUEST line indicates the status of
the register not being used in the data path at
that time. If the IN/OUT line is High, the
REQUEST line is High when the Output
register is empty. If IN/OUT is Low, the
REQUEST line is High when the Input register
is full.
Pattern-Recognition Logic Operation. Both
Ports A and B can be programmed to generate
interrupts when a specific pattern is recognized at the port. The pattern-recognition logic
is independent of the port application, thereby
allOWing the port to recognize patterns in all of
its configurations. The pattern can be independently specified for each bit as 1, 0, riSing
edge, falling edge, or any transition. Individual bits may be masked off. A patternmatch is defined as the simultaneous satisfaction of all nonmasked bit specifications in the
AND mode or the satisfaction of any nonmasked bit specifications in either of the OR or
OR-Priority Encoded Vector modes.
INPUT PORT

AtKIN'

OUTPUT PORT

iiAV'-Qo-..,

Figure 9. Pulaed HcmcI8bake
2014.C

ADDRESS VALID

~

/

<

READ DATA

==:x

lEI

IBO

<

I
WRITE DATA

)--

Figure 20. Write Cycle nmlD!J

Interrupt Acknowl~e. The CIO pulls its
Interrupt Request (INT) line Low, requesting
interrupt service from the CPU, if an Interrupt
Pending (IP) bit is set and interrupts are
enabled. The CPU responds with an Interrupt
Acknowledge cycle. When Interrupt Acknowledge (INTACK) goes true and the IP is set, the

iiTiCK

\

Do-D7

Figure 19. Read Cycle TlmlDIJ

INT

/

iiiii

}--

x::

ADDRESS VALID

~

iii

I

\

",,-At

CIO forces Interrupt Enable Out (lEO) Low,
disabling all lower priority devices in the interrupt daisy chain. If the CIO is the highest
priority device requesting service (lEI is
High), it places its interrupt vector on the data
bus and sets the Interrupt Under Service (IUS)
bit when Read (RD) goes Low.

------.fJ,,'-------.J1
J';

~'F-,-------...Jr
H

~'F--'- - - - -

iii

j'~

~-D.

- _____~£~r---_«~V~E~~O~.~}___
Figure 21. Interrupt Aclmowledge Timing

2021-006. 007. 008

897

Ia

Absolute
Maximum
Ratings

Voltages on all pins with respect
toGND ................... -0.3Vto +7.0V
Operating Ambient
Temperature ....... See Ordering Information
Storage Temperature ........ -65°C to + 150°C

Stresses greater than those hsted under Absolute Maxi·
mum Ratings may cause permanenl damage 10 the device.
This .s a slress rating only; operation of the device at any
condition above those Indicated In the operational sections
of these specIfications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affeel
device rehabillty.

Standard
Test
CondltioDS

The DC characteristics and capacitance sections below apply for the follOWing standard test
conditions, unless otherwise noted. All voltages
are referenced to GND. Positive current flows
into the referenced pin.
Standard conditions are as follows:

The Ordering Information section lists temperature ranges and product numbers. Package
drawings are in the Package Information section
in this book. Refer to the Literature List for additional documentation.
All ac parameters assume a load capacitance
of 50 pf max.

• +4.75 V

:S

Vee

:S

+5.25 V

• GND = OV
• TA as specified in Ordering Information
+5"

.J
+IV

....
FROM OUTPUT
UNDER TEST

SOplr
':'

Figure 22. SlaDclard Teet Load

DC
Cbarac:terlstlcs

Symbol

Parameter

Input High Voltage

VIH
VIL
VOH

Input Low Voltage
Output High Voltage

VOL

Output Low Voltage

IlL

Input Leakage
Output Leakage
Vcc Supply Current

h
Ice

Figure 29. Opa-DraiD T88I Load

MiD

Max

UlIlt

2.0

Vee +0.3
0.8

V
V
V
V
V
p.A
p.A

-0.3
2.4

0.4
0.5
±10.0
±10.0
200

CondltlOD

IoH =
IoL=
IoL=

- 250 p.A
+2.0 rnA
+3.2 rnA
0.4 ::s VIN ::s +2.4 V

0.4 ::s VOUT ::s +2.4 V

rnA

Vee = 5 V ± 5% unless otherwIse specifIed, over speclhed temperature range.

Capacitance

Symbol

Parameter

MID

Max

UlIlt

15
20

pi
pi

Tast Condltlon

------------------------------------------------------------Input Capacitance
C
10
pi
IN

COUT
CliO

Output CapaCitance
Bidirectional CapaCitance

f = 1 MHz, over specIfIed temperature range.
Unmeasured PlllS returned to ground.

898

8085-0209. 0001

CPU

Interface
Timing

PCL!(

READ ------------1---t~~==~~~~~+_----1_---------~-D,

Do-D,

DATA VALID

WRrr. ____________J

Interrupt
Timing

PATTIIRN MATCH
INPUT(8)
orr PORT

~1'-________________________________________
PATTERN MATCHES
_
· @ f - - - - -..I

iCiiiii

NOTE 4

COUNTBR
INPUT __________J

"
33

PCL!(

..
Interrupt
Acknowledge
Timing
iii

1.1

iii

2021-()09, 010, 011

~~---

899

6 MHz
Min
Max

Symbol

Parameter

1

TcPC
TwPCh

PCLK Cycle time

250

4000

165

4000

2

PCLK Width (High)

105

2000

70

2000

3

TwPCl

PCLK Width (Low)

105

2000

70

2000

4
TrPC
5 -TfPC

Min

4 MHz
Max

No.

20
20

PCLK Rise Time
PCLK Fall Time

10
15

6

TsIA(PC)

INTACK to PCLK t Setup Time

100

100

7

ThIA(PC)

INTACK to PCLK t Hold Time

8

TsIA(RD)

INTACK to RD I Setup Time

0
200

0
200

9
10 -

ThIA(RD)
INTACK to RD t Hold Time
TsIA(WR) - - INTACK to WR I Setup Time

0
200

200

0

11

ThIA(WR)

INTACK to WR t Hold Time

0

0

12

TsA(RD)

Address to

RiS I Setup Time

80

80

13

ThA(RD)

14
15 -

TsA(WR)

Address to RD t Hold Time
Address to WR I Setup Time

16
17

ThA(WR)--- Address to WR t Hold Time
TsCEl(RD)
CE Low to RiS I Setup Time

RiS I Setup Time

TsCEh(RD)

CE High to

18

ThCE(RD)

CE to RD t Hold Time

19
20 -

TsCEl(WR)
CE Low to WR I Setup Time
TsCEh(WR) - - BE HIgh to WR I Setup Time

21

ThCE(WR)

BE to WR

22

TwRDl
TdRD(DRA)

RiS Low Width
RiS I to Read Data Active Delay

23

t Hold Time

TdRDf(DR)
RD I to Read Data Valid Delay
24
25- TdRDr(DR)-- iID t to Read Data Not Valid Delay
26

TdRD(DRz)

RiS t to Read Data Float Delay

27

TwWRl

WR Low Width

28

TsDW(WR)

Write Data to WR I Setup Time

29
30

ThDW(WR)
Trc

Write Data to WR t Hold Time
Valid Access Recovery Time

Notes*t

0

0

80
0

80
0

0

0

100

70
0

0
0
100

0
70

0

0

390

250

0

0
255

0

180
0

70
390

45

2

250

0

0

0
1000'

0
3

650

31

TdPM(lNT)

Pattern Match to INT Delay (Bit Port)

2+800

32

TdACK(lNT)

10+600

2
10

6
4,6

33

TdCI(INT)

ACKIN to INT Delay (Port with Handshake)
Counter Input to INT Delay (Counter Mode)

2+700

2

34

TdPC(INT)

PCLK to INT Delay (Timer Mode)

3+700

3

6
6

35

TsIA(RDA)

INTACK to RD I (Acknowledge) Setup Time

350

250

36

TwRDA

RD (Acknowledge) Width

350

250

37

TdRDA(DR)

RD I (Acknowledge) to Read Data Valid Delay

TdIA(lEO)
38
INTACK I to lEO I Delay
39-TdIEI(IEO)--IEI to lEO Delay
40

TsIEI(RDA)

lEI to RD I (Acknowledge) Setup Time

41

ThIEI(RDA)

42

TdRDA(INT)

lEI to RD t (Acknowledge) Hold Time
RD I (Acknowledge) to INT t Delay

NOTES:
1. Parameter does not apply to Interrupt Acknowledge trans-

actions.
2. Float delay IS measured to the hme when the output has
changed 0.5 V With mmlmum ae load and maximum de load.
3. Tre IS the speClfJed number or 3 TePe, whlChever is longer.
4. The delay lS from DA V I for 3-Wire Input Handshake. The
delay IS from DAC I for 3-Wlre Output Handshake.
5. The parameters for the devices In any parhcular daisy cham
must meet the followmg constralOt: The delay from INTACK 1

900

5

250

180

350

250
100

150
100
100

70

5
55

70
600

600

to RD I must be greater than the sum of TdIA{lEO) for the
highest PrIOrIty perIpheral, TsIEI(RDA) for the lowest PrIOrIty
peripheral, and TdIEI(IEO) for each penpheral separahng them
In the cham.
6. Units are equal to TePe plus ~s,
* Tlmmgs are prellmmary and subject to change. All hmmg refer~
ences assume 2.0 V for a logic "1" and 0.8 V for a logic "a".
r Umts m nanoseconds (ns), except as noted.

Strobed
Handshake

INPUT

OUTPUT

Interlocked
Handshake

.ATA

INPUT

AeK..

~""""I DATAVALlD~,
_~~_
\

.. ________~~--,--

t

;®-y-®---._.~I'---------

DATA

OUTPUT

3-Wire
Handshake

iCiffii

DATA

Dii

INPUT

INPUT
RPD
OUTPUT

DAC
OUTPUT

------...J!'

DATA

DAC

INPUT
OUTPUT
RPD
INPUT

DiY

OUTPUT

2014-025, 026, 027

901

4 MHz
No.

1
2
3
4
56
7
8
9
10 11
12
13
14
15 16
17
18
19
20 21
22
23

Symbol

Parameter

MID

Max

6MHI
MID

Max

Note.*t

Data Input to ACKIN I Setup Time
o
o
Data Input to ACKIN I Hold Time500
Strobed Handshake
o
TdACKf(RFD)
ACKIN I to RFD I Delay
o
TwACKI
ACKIN Low Width-Strobed Handshake
250
TwACKh--- ACKIN High Width-Strobed Handshake - - - - 2 5 0 - - - - - - - - - - - - - - TdRFDr(ACK) RFD I to ACKIN I Delay
0
0
TsDO(DAV)
Data Out to DAV I Setup Time
25
20
TdDAVf(ACK) DAV I to ACKIN I Delay
0
0
ThDO(ACK)
Data Out to ACKIN I Hold Time
2
2
2
TdACK(DAV) - ACKIN I to DAV I Delay
2------ 2 ------2THDI(RFD)
Data Input to RFD I Hold Time-Interlocked
Handshake
TdRFDf(ACK)
RFD I to ACKIN I Delay Interlocked Handshake
o
o
TdACKr(RFD) ACKIN I (DAV I) to RFD I Delay-Interlocked and
3-Wire Handwshake
0
o
TdDAVr(ACK) DAV I to ACKIN I (RFD I)-Interlocked and 3-Wire
0
Handshake
o
TdACK(DAV)- ACKIN I (RFD I) to DAV I Delay-Interlocked and - - - - - - - - - - - - - - - 3-Wire Handshake
0
0
TdDAVIf(DAC) DAV I to DAC I Delay-Input 3-Wlre Handshake
0
0
ThDI(DAC)
Data Input to DAC I Hold Time-3-Wire Handshake
0
0
TdDACOr(DAV) DAC I to DAV I Delay-Input 3-Wire Handshake
0
0
TdDAVIr(DAC) DAV I to DAC I Delay-Input 3-Wire Handshake
0
0
TdDAVOf(DAC) DAV I to DAC I Delay-Output 3-Wire Handshake - 0 - - - - - - 0 - - - - - - - ThDO(DAC)
Data Output to DAC I Hold Time-3-Wire
Handshake
2
2
2
2
TdDACIr(DAV) DAC I to DAV I Delay-Output 3-Wire Handshake
2
2
TdDAVOr(DAC) DAV I to DAC I Delay-Output 3-Wire Handshake
0
o
TsDI(ACK)
ThDI(ACK)

NOTES:
1. This tIme can be extended through the use of deskew tImers.
2. Umts equal to TcPC.

902

* Tlmmgs are prehmlnary and subject to change. All tlmmg references assume 2.0 V for a logiC "I" and 0.8 V for a logiC "a".
t Units In nanoseconds (ns). except as noted.

Counter/
Timer
Timing

..,LK

PCLllI2
(INTERNAL)

COU ..T ....
•NPUT

I:
CII
4 MHz
No.

Symbol

TcCI
2
TClh
3
TWCIl
4
TlCI
5-TrCI - - - - TsTI(PC)
6
TsTI(CI)
7
8
9
10 11
12
13
14

Parameter
Counter
Counter
Counter
Counter

Input
Input
Input
Input

Min

Cycle Time
High Width
Low Width
Fall Time

Max

500
230
230

W

6 MHz
Min

Max

Notes*t

330
150
150
20

Counter Input Rise Time - - - - - - - - - - - - - - - 20
Trigger Input to PCLK I Setup Time (Timer Mode)
150
Trigger Input to Counter Input I Setup Time
150
(Counter Mode)
Tngger Input Pulse Width (High or Low)
TwTI
200
TsGI(PC)
Gate Input to PCLK I Setup Time (Timer Mode)
100
TsGI(CI) - - - Gate Input to Counter Input I Setup Time - - - - 100
(Counter Mode)
ThGI(PC)
Gate Input to PCLK I Hold Time (Timer Mode)
100
ThGI(Cl)
Gate Input to Counter Input I Hold Time
100
(Counter Mode)
TdPC(CO)
PCLK to Counter Output Delay (Timer Mode)
475
475
TdCI(CO)
Counter Input to Counter Output Delay
(Counter Mode)

15
15

NOTES
1. These parameters must be met to guarantee trIgger or gate
are vahd for the next counter/hmer cycle.

* TIIDmgs are prehmmary and subject to change. All hmmg refer-

ences assume 2.0 V for a logiC "1" and 0.8 V for a loglC "0",
In nanoseconds (ns),

i Umts

2021-012

903

~

S

REQUEST/

WAIT
Timing

4 MHz
No.

Symbol

Parameter

Min

Max

]

TdRD(REQ)

RD I to REQ I Delay

500

2

TdRD(WAIT)

RD I to WAIT I Delay

500

3

TdWR(REQ)

WR I to REQ I Delay

500

TdWR(WAIT)
WR I to WAIT I Delay
4
5-TdPC(REQ)--PCLK I to REQ t Delay

6 MHz
Min

Max

Notes*t

500
300

6
7

TdPC(WAIT)

PCLK I to WAIT t Delay

300

TdACK(REQ)

ACKIN I to REQ t Delay

8

TdACK(WAIT)

ACKIN I to WAIT t Delay

8+ 1000
10+600

1,2
],2

NOTES:
1. The delay IS fronm DAV I for 3-Wlre Input Handshake. The
delay IS from DAC I for 3-Wlre Output Handshake.
2. UOits equal to Tcpe + ns.

* Tlmmgs are prelimmary and subject to change. All bmmg refer-

ences assume 2.0 V for a logIc "1" and 0.8 V for a logic "0".
except as noted.

t UOlts In nanoseconds (ns),

Reset

Timing

RESET
INTERNAL

____________________

~r

4 MHz
No.

Symbol

Parameter

Min

Max

6 MHz
Min

TdRD(WR)

Delay from RD t to WR I for No Reset

50

2

TdWR(RD)

Delay from WR t to RD I for No Reset

50

50

3

TwRES

Minimum Width of RD and WR both Low for Reset

250

250

.. Timmgs are prelimmary and subject to change. All hmmg refer-

Max

Notes*t

50

t Units In nanoseconds (ns).

ences assume 2.0 V for a logic "I" and 0.8 V for a logic "0".

904

2021·013 014

Mlac:ellaDeou8

Port
Timing

ANY INPUT

".CA~:~

-0=V--t'f--

~11--'_ __

______..11b---. TClK

V2

Figure 5. Z8581 Functional Block Diagram

SYSTEM INTERFACE CONSIDERATIONS
Due to the fast rise and fall times produced by the 28581,
transmission line concepts must be applied in order to avoid
ringing and reflections on the clock outputs. More
specifically, the interconnections between the clock outputs
and the loads they are driving must be treated as
transmission lines, and it is necessary to match the source
impedance of the clock outputs to the characteristic
impedances of these transmission lines. In most cases the
impedances can be matched by placing termination
resistors in series with the clock outputs. These resistors
range in value from 22 to 220 ohms, with the value chosen to
optimize the clock risetime at the load. (See example below.)
It is important to control the impedance seen by the clock
output by keeping leads short and avoiding stray
inductances wherever possible.
Another important consideration is the bypass capacitor. To
avoid distortion of the power supply, the 28581 requires a
high frequency 0.01 /IF ceramic capacitor between Vee and
ground, and the leads connecting this capacitor to the pins
should be kept as short as possible.

910

r
r

33pf
XTAllA
22Q
ZClK

t::::I

Z8881

ClK

Z8000

33pf
XTAl18

GND

vce

NOTE: The Z8581 requires a parallel-resonant fundamental type crystal. The
capacitor may be varied to fine tune the frequency.

Figure 6. Z8561/Z8000 Interface

2248-005, 006

ABSOWTE MAXIMUM RATINGS
Voltages on all inputs and outputs
with respect to GND ................. - 0.3V to + 7.0V
Operating Ambient
Temperature ................. See ordering information
Storage Temperature .............. -65°Cto +150°C
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only: operation of the device at any

condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The Ordering Information section lists package temperature
ranges and product numbers. Refer to the Literature List for
additional documentation. Package drawings are in the
Package Information section.

STANDARD TEST CONDITIONS
The DC characteristics below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND (OV). Positive current flows
into the referenced pin.

references between two output signals assume a load
difference of SO pf max.
+5V

00

• S = O°Cto +70°C, +4.75V~Vee~ +5.25V
• E
•

M

= -40°Cto +85°C, +4.SV~Vee~ +S.2SV
= -SSOCto +12SoC, +4.SV~Vee~ +S.SV

All ac parameters assume a total load capacitance (C),
including parasitic capacitances, of 100 pf max, except for
parameters 8, 9, 21, and 22 which are 200 pf max. Timing

DC CHARACTERISTICS

Symbol

Parameter

VeH

Clock Input High Voltage

Vel

Clock Input low Voltage

VIH

Input High Voltage

Min
Vee -0.4

-0.3

Max
Vee + 0.3

0.45

Unit

Condition

V

Driven by External Clock Generator

V

Driven by External Clock Generator

2.0

Vee + 0.3

V

-0.3

0.8

V

Vil

Input low Voltage

VOH

Output High Voltage

2.4

V

IOH

VOH
(ZClK,

Output High Voltage

Vee - 0.3

V

IOH = - 250 J.lA tested at 5 J.ls after
ZClK or TClK rises High

TClK)
VOL

2.4
Output low Voltage

a
....
g
CII

Available operating temperature ranges are:

0.4

=

-250J.lA

= -250J.lA
= = +2.0 mA

V

IOH

V

IOl

0.4 '" VIN '" + 2 4V

III

Input leakage

±10

J.lA

Icc

Vee Supply Current

150

mA

911

AC CHARACTERISTICS
Z8581

6 MHz
Number Symbol

Parameter

Min.

Units

Notes1

TwCH

Clock Input High Width

31

18

ns

2

2

TwCL

Clock Input Low Width

31

18

ns

2

3

TpC

Clock Input Cycle Time

82

50

ns

2

4

TIC

Clock Input Fall Time

10

7

ns

2

5-TrC

Clock Input Rise Time

10

7--ns--2-

6

TdOSC

Clock Inputto OSC Delay

30

20

ns

7

TdZC

OSC to ZCLK Delay

20

15

ns

8

TIZC

ZCLK Fall Time

10

10

ns

9

TrZC

ZCLK Rise Time

10

10

ns

--10-TsSC

Stretch Controls to OSC t Setup

35

20

20

10

11

ThSC

Stretch Controls to OSC t Hold

12

Td(ST/CR)

STRT ~ to 2·bit Counter Reset Delay

13

Td(OSC/CC)

OSC t to 2-bit Counter-Change

14

Tw(STRD

STRT Low Width

35
20
50

-15-Td(RSTO)--ZCLK t to RSTO ~ Delay

ns
ns
25

ns

17

ns

30
30

ns
20--ns

16

Ts(RSTI)

RSTI ~ to ZCLK t Setup

30

20

17

Th(RSTI)

RSTI Ho ZCLK t Hold

30

20

ns

18

Tw(RSTO)

RSTO Low Width

16

16

cycles

19

Ts(ST/ZC)

STRT ~ to ZCLK t Setup to include ZCLK edge

40

ns

30

ns

20-TdTC

Clock Input to TCLK Delay

40

21

TrTC

TCLK Rise Time

10

10

ns

22

TfTC

TCLK Fall Time

10

10

ns

NOTES: 1. All timings are prelimln8ry and subject to change.

2. Clock input other than a crystal oscillator.
3. Assuming ZCLK rising.

912

Max.

Z8581·10
10MHz
Min
Max

30-- ns

3

XTAL1A

OSC

ZCLK

STRITCH
CONTROL

STRT

II

CO,C1

(II

...

00

§

UTI

®
RSTO

)

XTALIA

TCLK

Timing measurements are made at the following voltages:

zelK, TClK
Output
Input

2248-007

High

Low

4.0V
2.0V
2.0V

O.BV
O.BV
O.BV

913

ORDERING INFORMATION
Clock Generator and Controller, 6.0 MHz

Clock Generator and Controller, 10.0 MHz

18-pln DIP
Z8581 PS
Z8581 CS
Z8581 PE
Z8581 CE
Z8581 CM'
Z8581 CMB't

18-pln DIP
Z8581·10 PS
Z8581-10CS
Z8581-10 PE
Z8581-10CE
Z8581-10CM'
Z8581-10 CMB't

Codes
First letter is for package; second letter is for temperature.
C
P
L
V

=
=
=
=

Ceramic DIP
Plastic DIP
Ceramic LCC
Plastic PCC

TEMPERATURE
S = OOCto +70°C
E = -40°C to +85°C
M'= -55°C to +125°C

R
T
DIP
LCC
PCC

=
=
=
=
=

Proto pack
Low Profile Protopack
Dual-In-Line Package
Leadless Chip Carrier
Plastic Chip Carrier (Leaded)

FLOW
B = 883 Class B

Example: PS is a plastic DIP, O°C to + 70°C.

t Available soon
'For Military Orders, contact your local Zllog Sales Office for Military Electrical Specifications.

914

00-2315-03

Z765AFDC
Floppy Disk Controller

Zilog

Advance Information
Product
Specification

April 1985

FEATURES
Address Mark detection circuitry internal to the FDC
simplifies the phase locked loop and read electronics. The
track stepping rate, head load time, and head unload time
are user-programmable.

_ Drives up to 4 floppy-disk drives (FOD)

Z765A features are:

_ Compatible with most general-purpose microprocessors

_ IBM-compatible format, Single and Double Density

_ Single phase 8 MHz clock

_ Multisector and multitrack transfer capability

_ + 5V Only

_ Data scan capability-scans a single sector or an entire
cylinder comparing byte-for-byte host memory and disk
data

_ 40-Pin Dual-In-Line (DIP) package

_ Data transfers in DMA or non-DMA mode
_ Parallel seek operations on up to four drives

GENERAL DESCRIPTION
The Z765A is an LSI Floppy Disk Controller (FOG) chip
which contains the circuitry and control functions for
interfacing a processor to four floppy-disk drives. It supports
IBM System 3740 Single Density format (FM) and IBM
System 34 Double Density format (MFM) including
double-sided recording. The Z765A provides control
signals which simplify the design of an external phase
locked loop and write precompensation circuitry. The FDC
Simplifies and handles most of the burdens associated with
implementing a floppy-disk interface. (Figure 1).

_ READ DATA

Ilandshaking signals make DMA operation easily
incorporated with the aid of an external DMA Controller
chip, such as the Z80 DMA .. The FOC operates in either the
OMA or non-DMA mode. In the non-DMA mode the FDC
generates interrupts to the processor every time a data byte
is to be transferred. In the DMA mode, the processor need
only load the command into the FOC and all data transfers
occur under control of the FDC and DMA controllers.

== SCAN EQUAL

The Z765A executes 15 commands; each command
requires multiple 8-bit bytes to fully specify the operation
which the processor wishes the FDC to perform. The
commands are:

_ WRITE DATA
_ WRITE DELETED DATA
_ READ DELETED DATA
_ READTRACK
_ READID
_ FORMAT TRACK

_ SCAN HIGH OR EQUAL
_ SCAN LOW OR EQUAL
_ SEEK
_ RECALIBRATE
_ SENSE INTERRUPT STATUS
• SPECIFY
_ S~NSE DRIVE STATUS

915

DO.D'¢=>

¢=I

DATA
BUS
BUFFER

REGISTERS

_

WRCLOCK
WRDATA
WRENABLE

TERMINAL
COURT

SERIAL
INTERFACE
CONTROLLER

~

PRESHIFTO
PRESHIFTl
_

DRO

READ DATA WINDOW
VCO/SYNC

READ
WRITE
DMA
CONTROL
LOGIC

INT

¢=I

INPUT
PORT

D/S_

_

READY

_

WRITE PROTECT/TWO SIDE

_INDEX
_

RESET_

¢=I

CS
eLK .......

DRIVE

UNIT SELECT 0

INTERFACE

UNIT SELECT 1

CONTROLLER

MFMMODE

¢=I

+5V ---..
GND ____

FAULT/TRACK 0

OUTPUT
PORT

liW/SEEK
HEAD LOAD
HEAD SELECT
LOW CURRENT DIRECTION
FAULT RESET/STEP

Figure 1. Z765A FOe Block Diagram

SYSTEM
DATA
BUS

------

WCK
D,
D,

RESET

SERIAL
INTERFACE
CONTROL

D,
D,
D,
D,

RDW

D,

VCO/sYNC

0,
RDY

Z765A

iiACK

WP/TS

ORO

IDX

TC

-

-

FLT/TR,

D/S

US,

iiii
WR

US,

--

} DRIVE
INTERFACE
INPUTS

liW/SEEK

INT

HDL

RESET

HD

LCT/DIR

cs

FR/STP

D/S

HDL

Do

ROY
WP/TS

D,

FLT/TRo

0,

PS,

0,

PS,

0,

WDA

06

US,

0,

US,

DRO

HD

TC
DRIVE
INTERFACE
OUTPUTS

liW/SEEK

0,

DACK

MFM

cs

+5V

iiii
WR

MFM
WE

IDX

VCO/SYNC

INT

ROD

CLK

ROW

GND

WCK

LCT/DIR
FR/STP

t

CLK

GND

Figure 3. Pin A66ignments

+5V

Figure 2. Pin Functions

916

2357-001.002,003

PIN DESCRIPTIONS (Figures 2 and 3)
ClK. Clock (input). Single phase 8MHz square wave clock.
CS. Chip Select (input). IC selected when 0 (Low), allowing

1m' and WR to be enabled.
00.07. Data Bus. Bidirectional 8-bit Data Bus. Disabled
whenCS = 1.

OACK. DMA Acknow/edge (input). DMA cycle is active
when 0, and controller is performing DMA transfer.
ORQ. Data DMA Request (output). DMA Request is being
made by FDC when DRQ = 1.
DIS. Data/Status Register Select (input). Selects Data
Register (D/S = 1) or Status Register (D/S = 0) contents of
the FDC to be sent to Data Bus. Disabled when CS = 1.

FRISTP. Fau/t Reset/Step (output). Resets fault FF in FDD in
ReadlWrite mode, contains step pulses to move head to
another cylinder in Seek mode.

FlT/TRo. Fault/Track 0 (input). Senses FDD fault condition
in Read/Write mode and Track 0 condition in Seek mode.

HO. Head Select (output). Head 1 selected when 1 (High);
Head 0 selected when 0 (Low).

HOl. Head Load (output). Command which causes
read/write head in FDD to contact diskette.

lOX. Index (input). Indicates the beginning of a disk track.

RD. Read (input). When 0, control signal for transfer of data
from FOC to Data Bus. Disabled when CS = 1.
ROD. Read Data (input). Read data from FOD, containing
clock and data bits.
ROW. Read Data Window (input). Generated by PLL, and
used to sample data from FDD.
ROY. Ready (input). Indicates FOD is ready to send or
receive data.

RESET. Reset (input). Places FOC in idle state. Resets
output lines to FDD to O. Does not affect SRT, HUT or HLT in
Specify command. If ROY pin is held High during Reset,
FDC generates an interrupt within 1.024 msec. To clear this
interrupt use Sense Interrupt Status command.

RW/SEEK. Read Write/Seek (output). When 1 (High) Seek
mode selected; when 0 (Low) Read/Write mode selected.

TC. Terminal Count (input). Indicates the termination of a
DMA transfer when 1 (High). It terminates data transfer
during Read/Write/Scan command in DMA or Interrupt
mode.

US1. USo. Unit Select (output). FDD Unit selected.
VCO/SYNC. (output). Inhibits VCO in PLL when 0 (Low);
enables VCO when 1 .

WCK. Write Clock (input). Write data rate to FDD. FM

FOC.

= 500
KHz, MFM = 1 MHz with a pulse width of 250 ns for both
FM and MFM.

lCTlOIR. Low Current/Direction (output). Lowers Write

WOA. Write Data (output). Serial clock and data bits to FDD.

INT. Interrupt (output). Interrupt Request generated by

current on inner tracks in Read/Write mode; determines
direction head will step in Seek mode. A fault reset pulse is
issued at the beginning of each Read or Write command
prior to the occurrence of the Head Load signal.

MFM. MFM Mode (output). MFM mode when 1; FM mode
when O.

PS1. PSo. Precompensation (preshift) (output). Write

WE. Write Enab/e (output). Enables write data into FDD.
WP/TS. Write Protect/Two Side (input). Senses Write Protect
status in Read/Write mode and Two-Side Media in Seek
mode.

WR. Write (input). When 0, control signal for transfer of data
to FDC via Data Bus. Disabled when CS = 1.

precompensation status during MFM mode. Determines
early, late, and normal times.

917

Table 1. Internal Registers

The bits in the Main Status Register are defined as follows:
Bit
Symbol

Description

FOO 0 Busy

OoB

FOO number 0 is in the Seek mode If any bit is set, FOG will not accept read
or write command

01

FDO 1 Busy

01 B

FOO number 1 is in the Seek mode. If any bit is set, FOG will not accept read
or write command.

02

FOO 2 Busy

02B

FOO number 2 is in the Seek mode. If any bit is set, FOG will not accept read
or write command.

03

FD03 Busy

03B

FOO number 3 is in the Seek mode. If any bit is set, FOG will not accept read
or write command.

04

FOG Busy

GB

A read or write command is In process. FOG will not accept any other
command.

05

Execution Mode

EXM

This bit is set only during execution phase in non-OMA mode. When 05
goes low, execution phase has ended and result phase has started. It
operates only during non-OMA mode of operation.

06

Oata Input/Output

010

Indicates direction of data transfer between FOG and Oata Register. If 010 =
1, then transfer IS from Oata Register to the processor. If 010 = 0, transfer is
from the processor to Oata Register.

07

Request for Master

ROM

Indicates Oata Register is ready to send or receive data to or from the
processor. Both bits 010 and ROM should be used to perform the
handshaking functions of "ready" and "direction" to the processor.

No.

Name

00

INTERNAL REGISTERS
The Z765A contains two registers which may be accessed
by the main system processor: a Status register and a Data
register. The 8-bit Main Status register (Table 1) contains the
FDC status information and may be accessed at any time.
The 8-bit Data register is several registers in a stack; one
register at a time is presented to the data bus. The Data
register stores data, commands, parameters, and FDD
status information. Data bytes are read out of, or written into,
the Data register in order to program or obtain the results
after a particular command. Only the Status register may be
read and used to facilitate the transfer of data between the
processor and Z765A.
The relationship between the Status/Data registers and the
signals RD, WR, and Dis is shown in Table 2.
The Data Input/Output (010) and Request for Master (ROM)
bits in the Status register indicate when data is ready and the
direction transfer on the data bus (Figure 4). The maximum
time between the last RD or WR during a command or result

918

phase and the set or reset 010 and ROM is 12J.1s; every time
the Main Status register is read the CPU should wait 12J.1s.
The maximum time from the trailing edge of the last RD in
the result phase to when 04 (FDC busy) goes Low is 12J.1s.
Table 2. Relationships Between StatuslData Registers
and RD, WR, and DIS

DIS

RD

0

0

Function

Read Main Status Register
0

Illegal

0

0

Illegal

0

0

Illegal

0
0

WR

Read from Oata Register

0
0

Write into Oata Register

STATUS REGISTER IDENTIFICATION
Bit
No.

Name

Description

Symbol
Status Register 0

D7 = OandDs = 0
Normal Termination of command, (NT). Command was completed and
properly executed.

Interrupt Code

IC

D7 = OandDs = 1
Abnormal Termination of command, (AT). Execution of command was started
but was not successfully completed.
D7=1andDS=O
Invalid Command issue, (IG). Command which was issued was never started.
D7=1andDs=1
Abnormal Termination because during command execution the ready signal
from FDD changed state.

D5

Seek End

SE

When the FDC completes the SEEK command, thiS flag is set to 1 (High).

D4

Equipment Check

EC

If a fault signal is received from the FDD, or if the Track 0 signal falls to occur
after 77 step pulses (Recalibrate Command) then this flag is set.

D3

Not Ready

NR

When the FDD is in the not-ready state and a read or wnte command is Issued,
this flag is set. If a read or write command is issued to Side 1 of a single-sided
drive, then this flag IS set.

D2

Head Address

HD

This flag is used to indicate the state of the head at Interrupt.

D1

Unit Select 1

US1

This flag IS used to indicate a Dnve Unit Number at Interrupt.

DO

Unit Select 0

USo

This flag is used to indicate a Drive Unit Number at Interrupt.

Status Register 1
End of Cylinder

EN

When the FDC tries to access a sector beyond the final sector of a cylinder,
this flag is set.

Data Error

DE

When the FDC detects a Cyclic Redundancy Check (CRG) error in either the
ID field or the data field, this flag is set.

Overrun

OR

If the FDC IS not serviced by the host system during data transfers within a
certain time interval, this flag is set.

Not used. This bit is always 0 (Low).

DS
D5

Not used. This bit always 0 (Low).

D3

During execution of READ DATA, WRITE DELETED DATA or SCAN command,
if the FDC cannot find the sector specified in the Internal Data Register (IDR),
this flag is set.
No Data

ND

During execution of the READ ID command, if the FDC cannot read the ID
field without an error, then thiS flag is set.
During execution of the READ A cylinder command, if the starting sector
cannot be found, then this flag is set.

919

STATUS REGISTER IDENTIFICATION (Continued)
Bit
No.

Name

Symbol

Description
Status Register 1 (Continued)

01

Not Writeable

NW

During execution of WRITE DATA. WRITE DELETED DATA or Format A
cylinder command. if the FDC detects a write protect signal from the FDD.
then this flag is set.
If the FDC cannot detect the 10 Address Mark after encountering the index
hole twice. then this flag is set.

Do

Missing Address Mark

MA

If the FDC cannot detect the Data Address Mark or Deleted Data Address
Mark. this flag is set. Also at the same time. the MD (Missing Address Mark in
data field) of Status register 2 IS set.

Status Register 2
Not used. This bit is always 0 (Low).

07
06

Control Mark

CM

During execution of the READ DATA or SCAN command. if the FDC
encounters a sector which contains a Deleted Data Address Mark. this flag IS
set.

05

Data Error in Data Field

DO

If the FDC detects a CRC error in the data field then this flag is set.

04

Wrong Cylinder

WC

This bit is related to the NO bit. and when the contents of Cylinder (C) on the
medium is different from that stored in IDR. this flag is set.

03

Scan Equal Hit

SH

During execution of the SCAN command. if the condition of "equal" is
satisfied. this flag IS set.

02

Scan Not Satisfied

SN

During execution of the SCAN command. if the FDC cannot find a sector on
the cylinder which meets the condition. then this flag is set.

01

Bad Cylinder

BC

This bit IS related to the NO bit. and when the contents of C on the medium is
different from that stored in the lOR and the contents of C is FFH. then this flag
is set.

Do

Missing Address Mark In
Data Field

MD

When data is read from the medium. if the FDC cannot find a Data Address
Mark or Deleted Data Address Mark. then this flag is set.

Status Register 3
07

Fault

FT

This bit is used to indicate the status of the Fault signal from the FDD.

06

Write Protected

WP

This bit is used to indicate the status of the Write Protected signal from the
FDD.

05

Ready

RY
I

This bit is used to Indicate the status of the Ready Signal from the FDD.

04

Track 0

TO

This bit IS used to indicate the status of the Track 0 Signal from the FDD.

03

Two Side

TS

ThiS bit is used to indicate the status of the Two Side signal from the FDD.

02

Head Address

HD

ThiS bit is used to Indicate the status of the Side Select signal to the FDD.

01

Unit Select 1

US1

This bit is used to Indicate the status of the Unt Select 1 signal to the FDD.

Do

Unit Select 0

USo

This bit is used to indicate the status of the Unit Select 0 signal to the FDD.

920

OUT FOC AND INTO PROCESSOR

DATAIN/OUT
(010)

L

OUT PROCESSOR AND INTO FDC

I I

REQUEST FOR MASTER
(RQM)
NOT
READY

I I

Viii - - - - - - . ,U
I

iiD~---~-~--...,
I
I
I
I
I
I
I
I
A

NOTES:

I aI
[AJ -

A

I aI

A

I

C

I
I

I

D

I

C

I lal
D

A

I

Data reglater ready to be written Into by processor

[j] -

Data regllter not ready to be written Into by processor

[Q] -

Data register ready for next data byte to be read by processor

[Q] - Data register not ready to be read by processor

Figure 4. Data Transfer

COMMAND SEQUENCE
The Z765A is capable of performing 15 different
commands. Each command is initiated by a multi byte
transfer from the processor; the result after execution of the
command may also be a multi byte transfer back to the
processor. Because of this multi byte interchange of
information between the Z765A and the processor, each
command consists of three phases:

Command Phase. The FOC receives all information
required to perform a particular operation form the
processor.

Result Phase. After completion of the operation, status and
other housekeeping information are made available to the
processor.
The Instruction set shows the required preset parameters
and results for each command. Most commands require 9
command bytes and return 7 bytes during the result phase.
The W to the left of each byte indicates a command phase
byte to be written; an R indicates a result byte.

Execution Phase. The FOC performs the operation it was
instructed to do.

PROCESSOR INTERFACE
During Command or Result phases the Main Status register
must be read by the processor before each byte of
information is written into, or read from, the Data register.
Then the CPU should wait for 12",s before reading the Main
Status register. Bits 06 and 07 In the Main Status register
must be in a 0 and 1 state, respectively, before each byte of
the command word may be written into the Z765A. Many of
the commands require multiple bytes and, as a result, the
Main Status register must be read prior to each byte transfer
to the Z765A. During the Result phase, 06 and 07 in the
Main Status register must both be 1's before reading each
byte from the Data Register. Reading the Main Status
register before each byte transfer to the Z765A is required
only in the Command and Result phases, not during the
Execution phase.

2357-004

If the Z765A is in the non-OMA mode and reading data from
FOO, then the receipt of each data byte is indicated by an
interrupt signal on pin 18(INT = 1). The generation of a Read
signal (RO = 0) or Write signal (WR = 0) will clear the
interrupt and output the data onto the data bus. If the
processor cannot handle interrupts fast enough (every 13",s
for the MFM mode and 27",s for the FM mode), then it may
poll the Main Status register and bit 07 (ROM) functions as
the interrupt signal. If a Write command is in process, the
WR signal negates the reset to the interrupt signal.
In the non-OM A mode it is necessary to examine the Main
Status register to determine the cause of the interrupt, since
it could be a data interrupt or a command termination
interrupt, either normal or abnormal. If the Z765A is in the

921

COMMAND SYMBOL DESCRIPTION
Symbol

Name

Description

DIS

Data/Status Select

DIS controls selection of Main Status register (DIS = 0) or Data register (DIS = 1)

C

Cylinder Number

C stands for the current/selected cylinder (track) numbers 0 through 76 of the medium.

D

Data

D stands for the data pattern which is going to be written into a sector.

DrDo

Data Bus

8-bit Data Bus, where D7 stands for a most significant bit, and Do stands for a least
significant bit.

DTL

Data Length

When N is defined as 00, DTL stands for the data length which users are going to read
out or write into the sector.

EOT

End ofTrack

EOT stands for the final sector number on a cylinder. During Read or Write operations,
FDC will stop data transfer after a sector number equal to EOT

GPL

Gap Length

GPL stands for the length of Gap 3. During ReadlWrite commands this value
determines the number of by1es that VCO/SYNC will stay low after two CRC bytes.
During Format command it determines the size of Gap 3.

H

Head Address

H stands for head number 0 or 1, as specified in ID field.

HD

Head

HD stands for a selected head number 0 or 1 and controls the polarity of pin 27. (H
HD in all command words.)

=

HLT

Head Load Time

HLT stands for the head load time In the FDD (2 to 254 ms in 2 ms increments).

HUT

Head Unload Time

HUT stands for the head unload time after a Read or Write operation has occurred (16
to 240 ms in 16 ms Increments).

MF

FM or MFM Mode

If MF is Low, FM mode is selected, and If it is High. MFM mode is selected.

MT

Multitrack

If MT IS high, a Multitrack operation is performed. If MT = 1 after finishing ReadlWrite
operation on side 0, FDC automatically starts searching for sector 1 on side 1.

N

Number

N stands for the Number of data by1es written in a sector.

NCN

New Cylinder Number

NCN stands for a New Cylinder Number or desired position of head which is going to
be reached as a result of the Seek operation.

ND

Non-DMA Mode

ND stands for operation in the Non-DMA mode.

PCN

Present Cylinder Number

PCN stands for the cylinder number or present position of Head at the completion of
Sense Interrupt Status command.

R

Record

R stands for the sector number which will be read or written.

RIW

ReadlWrite

RIW stands for either Read (R) or Write (W) signal.

SC

Sector

SC indicates the number of Sectors per Cylinder.

SK

Skip

SK stands for Skip Deleted Data Address mark.

SRT

Step Rate Time

SRT stands for the Stepping Rate for the FDD (1 to 16 ms in 1 ms increments). Stepping
Rate applies to all drives (F(16) = 1 ms, E(16) = 2 ms, D(16) = 3 ms, ...).

STO
ST1
ST2
ST3

Status 0
Status 1
Status 2
Status 3

STO-3 stands for one of four registers which store the status information after a
command has been executed. This Information is available during the result phase after
command execution. These registers should not be confused with the main status
register (selected by DIS = 0). STO-3 may be read only after a command has been
executed and contains information relevant to that particular command.

STP

Step

During a Scan operation, If STP = 1, the data in contiguous sectors is compared by1e
by by1e with data sent from the processor (or DMA); if STP = 2, then alternate sectors
are read and compared.

USo, US1

Unit Select

Used to select between drives 0-3.

922

INSTRUCTION SET1, 2
Data Bus

Phase

R/W

D7

D6

Ds

D4

D3

D2

D1

Do

1
HD

1

0

USI

USa

Remarks

Read Data

Command

W
W
W
W
W
W
W
W
W

MT

MF

SK

0

0

X

X

X

X

X
C
H
R
N
EOT
GPL
DTL

Execution

Result

Command Codes
See Note 3
Sector 10 information prior to
command execution. The 4 bytes
are commanded against header
on Floppy disk.

Data transfer between the FDD
and main system
R
R
R
R
R
R
R

STO
ST1
ST2
C
H
R
N

Status information after command
execution
Sector 10 Information after
command execution

Read Deleted Data
Command

W
W
W
W
W
W
W
W
W

MT

MF

SK

0

1

X

X

X

X

X
C
H
R
N
EOT
GPL
DTL

Execution

Result

1
HD

0

USI

0
USa

Command Codes
Sector 10 information prior to
command execution. The 4 bytes
are commanded against header
on Floppy Disk.

Data transfer between the FDD
and main system
R
R
R
R
R
R
R

STO
ST1
ST2
C
H
R
N

Status information after command
execution
Sector 10 information after
command execution

NOTES. 1. Symbols used in this table are described at the end of this section.
2. DIS should equal binary 1 for all operations.
3. X ~ Don't care, usually made to equal binary 0

923

....N

~

en

III

.,
n
III

INSTRUCTION SET1, 2 (Continued)
Data Bus

Phase

R/W

07

06

05

04

W
W
W
W
W
W
W
W
W

MT
X

MF
X

0

0

0

X

X

X

03

02

01

Do

Remarks

0
US1

1
USo

Command Codes

HD

Write Data
Command

Sector IC information prior to
command execution. The 4 bytes
are commanded against header
on Floppy Disk.

C
H
R
N
EOT
GPL
DTL

Execution

Result

Data transfer between the main
system and FDD
R
R
R
R
R
R
R

STO
ST1
ST2
C
H
R
N

Status information after command
execution
Sector ID information after
command execution.

Write Deleted Data
Command

W
W
W
W
W
W
W
W
W

MT
X

MF
X

0

0

X

X

1
X
C
H
R
N
EOT
GPL
DTL

Execution

Result

0
US1

Command Codes
USo
Sector ID information prior to
command execution. The 4 bytes
are commanded against header
on Floppy disk.

Data transfer between the FDD
and main system
R
R
R
R
R
R
R

STO
ST1
ST2
C
H
R
N

NOTES: 1. Symbols used in this table are described at the end of this section.
2. DIS should equal binary 1 for all operations.
3. X = Don't care, usually made to equal binary O.

924

0
HD

Status information after command
execution
Sector ID information after
command execution

INSTRUCTION SET1, 2 (Continued)
Data Bus

Phase

R/W

07

06

05

04

02

01

Do

Remarks

0
HD

0
USa

Command Codes

US1

03
Read A Track

Command

W
W
W
W
W
W
W
W
W

0
X

MF
X

SK
X

0
X

0
X

Sector ID information prior to
command execution

C
H
R
N

EOT
GPL
DTL

N

...:I

Data transfer between the FDD
and main system. FDC reads all
data fields from index hole to EOT

Execution

Result

STO
ST1
ST2
C
H
R

R
R
R
R
R
R
R

Status information after command
execution
Sector ID information after
command execution

N
Read 10

Command

W
W

0
X

MF
X

0
X

1
X

0
X

US1

0
USa

Command Codes

The first correct ID information on
the cylinder is stored in Data
Register.

Execution

Result

0
HD

R
R
R
R
R
R

STO
ST1
ST2
C
H
R

n

~j

Status information after command
execution
Sector ID information read during
Execution phase from Floppy
Disk.

NOTES: 1. Symbols used in this table are described at the end of this section.
2. DIS should equal binary 1 for all operations.
3. X ~ Don't care, usually made to equal binary a.

925

~

..
CIt

III
tI

n

INSTRUCTION SET1, 2 (Continued)
OataBus

R/W

Phase

07

06

Os

04

0
X

MF
X

0
X

0
X

03

02

01

Do

0
US1

USa

Remarks

Format A Track

Command

W
W
W
W
W
W

X

1
HO

Command Codes
Bytes Sector
SectorslTrack
Gap3
Filler byte

N
SC
GPL
0

Execution

FOC formats an entire track.

Result

R
R
R
R
R
R
R

Status information after command
execution

STO
ST1
ST2
C
H
R
N

In this case, the 10 information
has no meaning.

Scan Equal

Command

W
W
W
W
W
W
W
W
W

MT
X

MF
X

SK
X

1
X

0
X
C
H
R
N
EOT
GPL
OTL

NOTES'

R
R
R
R
R
R
R

STO
ST1
ST2
C
H
R
N

Symbols used In this table are descnbed at the end of this section.
2 DIS should equal binary 1 for all operations

3 X = Don't care, usually made to equal binary a

926

Command Codes

0
US1

USa
Sector 10 information prior to
command execution

Data compared between the FDD
and the main system.

Execution

Result

0
HO

Status information after command
execution
Sector 10 Information after
command execution

INSTRUCTION SET1, 2

(Continued)

OataBus
Phase

R/W

07

06

05

04

03

02

01

00

0
US1

USo

Remarks

Scan Low or Equal
Command

W
W

MT
X

MF
X

SK
X

1
X

W
W
W
W
W
W
W

X

0
HD

1

Sector ID information prior to
command execution

C

H

R

N
EOT
GPL
STP

N
Data compared between the FDD
and main system

Execution

Result

Command Codes

R
R
R
R
R
R
R

Status Information after command
execution

STO
ST1
ST2
C
H
R
N

Sector 10 information after
command execution

Scan High or Equal
Command

W
W
W
W
W
W
W
W
W

MT
X

MF
X

SK
X

1
X

1
X

1
HD

0
US1

Command Codes
USo
Sector 10 information pnor to
command execution.

C
H
R
N
EOT
GPL
STP

Data compared between the FDD
and main system.

Execution

Result

R
R
R
R
R
R
R

Status Information after command
execution

STO

sn
ST2
C
H
R
N

Sector 10 information after
command execution.

Recalibrate
Command

W
W

0
X

0
X

0
X

0
X

0
X

Execution

Command Codes
0

US1

USo
Head retracted to Track 0

NOTES' 1. Symbols used in this table are described at the end of this section.
2. DIS should equal binary 1 for all operations.
3. X = Don't care, usually made to equal binary O.

927

....

en
en
III

lIS

"
n

INSTRUCTION SET1, 2

(Continued)

Data Bus
Phase

R/W

D7

D6

D5

D4

D3

D2

D1

Do

0

0

Remarks

Sense Interrupt Status

Command

W

Result

R
R

Command

W
W
W

0

0

0

0

0

Command Codes

STO
PCN

Status information about the FOC
at the end of seek operation

Specify

0
-SRT

0

0

0

0

Command Codes

0
HUT-

HLT

NO

Sense Drive Status

Command

Result

W
W

0
X

0
X

0
X

0
X

R

0
X

0

0
US1

0
USa

Command Codes

Status information about FOO

ST3
Seek

Command

W
W
W

0
X

0
X

0
X

0
X

1

X

1
HD

Command Codes

1

US1

USa

NCN
Head is positioned over proper
cylinder on diskette.

Execution

Invalid

Command

W

Invalid Codes

Result

R

STO

NOTES: 1. Symbols used in thiS table are described at the end of thiS section
2. DIS should equal binary 1 for all operations.
3. X = Don't care, usually made to equal binary a.

928

Invalid Command Codes
(NoOp-FDC goes into Standby
state.)
STO

= 80(H)

DMA mode, no interrupts are generated during the
Execution phase. The Z765A generates DROs (DMA
Requests) when each byte of data is available. The DMA
Controller responds to this request with both a DACK (DMA
Acknowledge) = 0 and an RD (Read signal) = O. When the
DMA Acknowledge signal goes Low (DACK = 0), then the
DMA request is cleared (ORO = 0). If a Write command has
been issued, a WR signal appears instead of RD. After the
Execution phase has been completed [Terminal Count (TC)
has occurred] or the last sector on the cylinder (EOT)
read/written, then an interrupt occurs (INT = 1) which
signifies the beginning of the Result phase. When the first
byte of data is read during the Result phase, the interrupt is
automatically cleared (I NT = 0).
The RD or WR signals should be asserted while DACK is
true. The CS signal is used in conjunction with RD and WR
as a gating function during programmed I/O operations. CS
has no effect during DMA operations. If the non-DMA mode
is chosen, the DACK signal should be pulled up to Vee.
During the Result phase all bytes shown in the Command
Table must be read. For example, the Read Data command

has seven bytes of data in the Result phase; all seven bytes
must be read to successfully complete the Read Data
command and allow the Z765A to accept a new command.
The Z765A contains five Status registers. The Main Status
register can be read at any time by the processor. The other
four Status registers (STO, ST1, ST2, and ST3) are available
only during the Result phase and can be read only after
completing a command. The particular command that has
been executed determines how many of the Status registers
are read.
The bytes of data which are sent to the Z765A to form the
Command phase and are read out of the Z765A in the
Result phase must occur in the order shown in the
Command Table. That is, the Command Code must be sent
first and the other bytes sent in the prescribed sequence. No
foreshortening ofthe Command or Result phases is allowed.
After the last byte of data in the Command phase is sent to
the Z765A, the Execution phase automatically starts. In a
similar fashion, when the last byte of data is read out in the
Result phase, the command is automatically ended and the
Z765A is ready for a new command.

POLLING FEATURE OF THE Z765A
After Reset is sent to the Z765A, the Unit Select lines USa
and US1 automatically go into a polling mode (Figure 5).
Between commands (and between step pulses in the Seek
command) the Z765A polls all four FDDs looking for a
change in the Ready line from any of the drives. If the Ready
line changes state (usually due to a door opening or
closing), then the Z765A generates an interrupt. When
Status register 0 (STO) is read (after Sense Interrupt Status is

issued), Not Ready (NR) is indicated. The polling of the
Ready line by the Z765A occurs continuously between
commands, thus notifying the processor which drives are
on or off line. Each drive is polled every 1.024 ms except
during the Read/Write commands. When used with a4 MHz
clock for interfacing to minifloppies, the polling rate is 2.048
ms.

I....t - - - - - - - - - - A P P R O X 1.0ms - - - - - - - - -••1
... 151'5 . . . . . 15f./S . . . . 151-15 . .1...I-------76ol-ls-------;~

uso

us,
DRIVE 0

DRIVE 1

DRIVE 2

DRIVE 3

Figure 5. Polling Features

2357'()05

929

COMMANDS
Read Data

A set of nine (9) byte words are required to place the FDC
into the Read Data Mode. After the Read Data command is
issued, the FDC loads the head (if it is in the unloaded state),
waits the specified head settling time (defined in the Specify
command), and begins reading 10 Address Marks and 10
fields. When the current sector number (R) stored in the 10
Register (lOR) compares with the sector number read off the
diskette, then the FDC, via the data bus, outputs data
byte-to-byte from the data field to the main system.
After completion of the read operation from the current
sector, the Sector Number is incremented by one, and the

data from the next sector is read and output on the data bus.
This continuous read function is called a Multi-Sector Read
Operation. The Read Data command can be terminated by
the receipt of a TC signal which should be issued when the
DACK for the last byte of data is sent. Upon receipt of this
signal, the FDC stops outputting data to the processor, but
continues to read data from the current sector, checks
Cyclic Redundancy Count (CRC), and at the end of the
sector, terminates the Read Data command. The amount of
data which can be handled with a single command to the
FDC depends upon multitrack (MT), MFM/FM (MF), and
Number of Bytes/Sector (N). Table 3 shows the Transfer
Capacity.

Table 3. 1l"ansfer Capacity
Maximum 1l"ansfer Capacity
(Bytes/Sector)
(Number of Sectors)

Final Sector
Read from
Diskettes

Multi· Track
MT

MFM/FM
MF

Bytes/Sector
N

o
o

0

00
01

(128) (26)

3,328

26atSideO

(256) (26)

6,656

or 26 at Side 1

00

(128) (52)
(256) (52)

6,656
13,312

26 at Side 1

0

01

o
o

0

o
o

01

(256) (15)

3,840

15atSideO

02

(512) (15)

7,680

or 15 at Side 1

0

01
02

(256) (30)
(512) (30)

7,680
15,360

15 at Side 1

0

02

(512) (8)

4,096

8atSideO

1

03

(1024) (8)

8,192

or8 at Side 1

0

02
03

(512) (16)
(1024) (16)

8,192
16,384

8 at Side 1

MT allows the FDC to read data from both sides of the
diskette. For a particular cylinder, data is transferred starting
at Sector 1, Side and completing at the last sector, Sector
L, Side 1. This function pertains to only one cylinder (the
same track) on each side of the diskette.

If the FDC twice detects the index hole without finding the
right sector (R), then the FDC sets Status register 1's No Data
(NO) flag to 1, and terminates the Read Data command.
(Status register also has bits 7 and 6 set to and 1
respectively.)

When N = 0, then DTL defines the data length which the
FDC must treat as a sector. If DTL is smaller than the actual
data length in a Sector, the data beyond DTL in the Sector is
not sent to the Data Bus. The FDC internally reads the
complete sector performing the CRC check and,
depending upon the manner of command termination, may
perform a Multi-Sector Read Operation. When N is
non-zero, then DTL has no meaning and should be set to
FFH·

After reading the 10 and Data fields in each sector, the FDC
checks the CRC bytes. If a read error is detected indicating
incorrect CRC in the 10 field, the FDC sets Status register 1's
Data Error (DE) flag to 1, and if a CRC error occurs in the
Data Field, the FDC also sets Status register 2's Data Error in
Data Field (DO) flag to 1, and terminates the Read Data
command. (Status register 0, bit 7 = 0, bit 6 = 1.)

°

At the completion of the Read Data Command the head is
unloaded, after the Head Unload Time Interval specified in
the Specify Command has elapsed. If the processor issues
another command before the head unloads, there is no
head settling time between subsequent reads. This time
saved is particularly valuable when a diskette is copied.

930

°

°

If the FDC reads a Deleted Data Address Mark off the
diskette, and the SK bit 0 in the first Command Word = 0,
then the FDC sets Status register 2's Control Mark (CM) flag
to 1, and after reading all the data in the sector, terminates
the Read Data command. If SK = 1, the FDC skips the
sector with the Deleted Data Address Mark and reads the
next sector. When SK = 1, the CRC bits in the deleted data
field are not checked.

During disk data transfers between the FDC and the
processor, via the data bus, the FDC must be serviced by
the processor every 27/-1s in the FM Mode, and every 13/-1s in
the MFM Mode, or the FDC sets Status register 1's Overrun
(OR) flag to 1, and terminates the Read Data command.

If the processor terminates a read or write operation in the
FDC, then the 10 information in the Result Phase is
dependent upon the state of the MT bit and EOT byte. Table
4 shows the values for C, H, R, and N when the processor
terminates the command.

Table 4. C, H, R, and N Values When Processor Terminates Commands

MT

HO

o

o
o

10 Information at Result Phase

Final Sector Transferred
to Processor

C

H

R

N

Less than EOT

NC

NC

R+1

NC

C+ 1

NC

R

= 01

NC

NC

NC

R + 1

NC

Equal to EOT
Less than EOT

C+ 1

NC

R

= 01

NC

N

Less than EOT

NC

NC

R+ 1

NC

~

Equal to EOT

NC

LSB

R

= 01

NC

Less than EOT

NC

NC

R+ 1

NC

IIJ

C+ 1

LSB

R

= 01

NC

n

Equal to EOT

o
o

EqualtoEOT

....

CII

III

a

NOTES: NC (No Change): The same value as the one at the beginning of command execution.
LSB (Least Significant Bit): The least significant bit of H IS complemented.

Write Data
A set of nine (9) bytes is required to set the FDC in the Write
Data mode. After the Write Data command is issued, the
FDC loads the head, waits the specified head setting time,
and begins reading 10 fields. When all four bytes (C, H, R,
and N) loaded during the command match the four bytes of
the 10 field from the diskette, the FDC takes data from the
processor byte-by-byte via the data bus and outputs it to the
FDD.
After writing data into the current sector, the sector number
stored in the R register is incremented by one, and new data
is written into the next data field. The FDC continues this
Multisector Write Operation until a Terminal Count signal is
issued. If a Terminal Count signal is sent to the FDC, it
continues writing into the current sector to complete the data
field. If the Terminal Count signal is received while a data
field is being written, the remainder of the data field is filled
With zeros.
The FDC reads the 10 field of each sector and checks the
CRC bytes. If the FDC detects a read error (CRC error) in
oneolthe 10 fields, it sets Status register 1's DE flag to 1, and
terminates the Write Data command. (Status register 0, bit
7=0,bit6=1.)
The Write command operates in the same manner as the
Read command for the following items:

• 10 information when the processor terminates command
•

Definition of DTL when N =

°

and when N/-O

Refer to the Read Data command for details.
In the Write Data mode, data transfers between the
processor and FDC via the data bus, must occur every 27/-1s
in the FM mode and every 13/-1s in the MFM mode. lithe time
interval between data transfers is longer, then the FDC sets
Status register 1's Overrun (OR) flag to 1, and terminates the
Write Data command. (Status register 0, bit7 = 0, bit6 = 1.)

Write Deleted Data
This command is the same as the Write Data command
except a Deleted Data Address mark, Instead of the normal
Data Address mark, is written at the beginning of the data
field.

Read Deleted Data
This command is the same as the Read Data command
except that when the FDC detects a Data Address mark at
the beginning of a data field and SK = 0, the FDC reads all
the data in the sector and sets Status register 2's CM flag to
1, and terminates the command. If SK = 1, then the FDC
skips the sector with the Data Address mark and reads the
next sector.

•

Transfer capacity

•

End of cylinder (EN) flag

Read Track

•

No data (NO) flag

•

Head unload time interval

This command is similar to the Read Data command except
that this is a continuous Read operation where the entire
data field from each of the sectors is read. Immediately after
931

sensing the index hole, the FOC starts reading all data fields
on the track as continuous blocks of data. Ifthe FOC finds an
error in the 10 or Data CRC check bytes, it continues to read
data from the track. The FOC compares the 10 information
read from each sector with the value stored in the IDR and, if
there is no comparison, sets Status register 1's NO flag to 1.
Multitrack or skip operations are not allowed with this
command.
This command terminates when the number of sectors read
is equal to EaT. If the FOC does not find an 10 Address mark
on the diskette after it senses the index hole for the second
time, it sets Status register 1's Missing Address mark (MA)
flag to 1 and terminates the command. (Status Register 0, bit
7=0,bit6=1.)

and terminates the command after setting Status register 0,
bit 7 to and bit 6 to 1. Also the loss of a Ready signal at the
beginning of a command execution phase causes Status
register 0, bit 7 and 6 to be set to and 1 respectively.

°

°

Table 5 shows the sector size relationship between N, SC,
and GPL.
Table 5. Functional Description of Commands
Format

FM Mode

°

Format Track
The Format command allows an entire track to be formatted.
After the index hole is detected, data is written on the
diskette; Gaps, Address marks, 10 fields and data fields, all
per the IBM 3740 Single Density format or IBM System 34
Double Density format, are recorded. The processor, during
the command phase, supplies values i.e., Number of
bytes/sector (N), Sectors Cylinder (SC), Gap Length (GPL),
and Data Pattern (D) which determine the particular format
to be written.

N

SC

GPLI

GPL2,3

8" Standard Floppy

Read 10
The Read 10 command gives the present position of the
recording head. The FOC stores the values from the first 10
field it can read. If no proper 10 Address mark is found onthe
diskette before the index hole is encountered for the second
time, Status register 1's MA flag is set to 1; if no data is found,
Status register 1's No Data (NO) flag is set to 1. The
command is then terminated with STO bit 7 =
and bit
6 = 1. During this command, data transfer between FOC
and the CPU occurs only during the result phase.

Sector Size

MFM
Mode4

128 bytes sector 00

1A

07

1B

256

01

OF

OE

2A

512

02

08

1B

3A

1024

03

04

47

8A

2048

04

02

C8

FF

4096

05

01

C8

FF

256

01

1A

OE

36

512

02

OF

1B

54

1024

03

08

35

74

2048

04

04

99

FF

4096

05

02

C8

FF

8192

06

01

C8

FF

5'/4" Minifloppy

128 bytes/sector 00

12

07

09

128

00

10

10

19

256

01

08

18

30

The data field is filled with the byte of data stored in O. The 10
field for each sector is supplied by the processor; that is, four
data requests per sector are made by the FOC for Cylinder
number (C), Head number (H), Sector number (R), and
Number of bytes/sector (N). This allows diskette formatting
with nonsequential sector numbers.

512

02

04

46

87

The processor must send new values for C, H, R, and N to
the Z765A for each sector on the track. If FOC is set for the
OMA mode, it issues four OMA requests per sector. If it is set
forthe Interrupt mode, it issues four interrupts per sector and
the processor must supply C, H, R, and N loads for each
sector. The contents of the R register are incremented by 1
after each sector is formatted; thus, the R register contains a
value of R when it is read during the Result phase. This
incrementing and formatting continues for the whole track
until the FOC detects the index hole for the second time,
whereupon it terminates the command.
If the Fault signal is received from the FOO at the end of a
Write operation, the FOC sets Status register O's EC flag to 1

932

FM Mode

MFM
Mode 4

1024

03

02

C8

FF

2048

04

01

C8

FF

256

01

12

OA

OC

256

01

10

20

32

512

02

08

2A

50

1024

03

04

80

FO

2048

04

02

C8

FF

4096

05

01

C8

FF

NOTES: 1. Suggested values of GPL in Read or Write commands to
avoid splice point between data field and 10 field of contiguous
sections.
2. Suggested values of GPL in format command.
3. All values except sector Size are hexidecimal.
4. In MFM mode FOC cannot perform a ReadlWrite format
operation with 128 bytes sector. (N = 00)

Scan Commands
The Scan commands allow comparison of data read from
the diskette and data supplied from the main system. The
FDC compares the data on a byte-by-byte basis and looks
for a sector of data which meets the conditions of DFOD =
Dprocessor, DFOD ~ Dprocessor. or DFOD ~ Dprocessor- The
hexadecimal byte of FF from memory or from FDD can be
used as a mask byte because it always meets the condition
of the comparison. One's complement arithmetic is used for
comparison (FF = largest number, 00 = smallest number).
After a whole sector of data is compared, if the conditions
are not met, the sector number is incremented (R + STPR) and the scan operation continues until one of the
following conditions occur: the conditions for scan are met
(equal, low, or high), the last sector on the track is reached
(EaT), or the terminal count (TC) signal is received.
If the conditions for scan are met, the FDC sets the Status
register 2's Scan Hit (SH) flag to 1 and terminates the Scan
command. If the conditions for scan are not met between
the starting sector number (R) and the last sector on the
cylinder (EaT), then the FDC sets Status register 2's Scan
Not Satisfied (SN) flag to 1, and terminates the Scan
command. During the scan operation, the receipt of a signal
from the processor or DMA controller causes the FDC to
complete the comparison of the particular byte in process
and then to terminate the command. Table 6 shows the
status of bits SH and SN under various conditions of Scan.

Table 6.

Scan Equal

Bit 2

= SN

Bit3

= SH

0

Scan Low
or Equal

Scan High
or Equal

0
0

= Dprocessor

DFDD '" Dprocessor
DFOD

= Dprocessor

0

DFOD < DProcessor

0

DFDD > Dprocessor

0
0

Comments

DFDD

0

During the Scan command, data is supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to avoid having Status
register 1's Overrun (OR) flag set, it is necessary to have the
data available in less than 27/As (FM mode) or 13/As (MFM
mode). If an Overrun occurs, the FDC ends the command
with Status register 0, bit 7 cleared to 0 and bit 6 set to 1.

Seek
The Read/Write head within the FDD is moved from cylinder
to cylinder under control of the Seek command. The FDC
has four independent Present Cylinder registers for each
drive which are cleared only after the Recalibrate command.
The FDC compares the Present Cylinder Number (PCN)
which is the current head position with the New Cylinder
Number (NCN), and if there is a difference, performs the
following operations:
PCN < NCN: Direction signal to FDD set to 1, and Step
Pulses are issued. (Step In)

Status Register 2
Command

(MT) is programmed, the last sector on the track must be
read. For example, if STP = 02, MT = 0, the sectors are
numbered sequentially 1 through 26 and the Scan
command is started at sector 21, the following happens.
Sectors 21 , 23, and 25 are read, then the next sector, 26, is
skipped and the index hole is encountered before the EaT
value of 26 can be read resulting In an abnormal termination
of the command. If the EaT had been set at 25 or the
scanning started at sector 20, then the Scan command
would be completed in a normal manner.

DFDD

= Dprocessor

0

DFDD > Dprocessor

0

DFDD < Dprocessor

If the FDC encounters a Deleted Data Address mark on one
of the sectors and SK = 0, then it regards the sector as the
last sector on the cylinder, sets Status register 2's Control
Mark (CM) flag to 1 and terminates the command. If SK = 1,
the FDC skips the sector with the Deleted Address mark,
reads the next sector, and sets Status register 2's Control
Mark (CM) flag to 1 to show that a Deleted sector has been
encountered.
When either the Step (STP) (contiguous sectors = 01 or
alternate sectors = 02) sectors are read or the Multitrack

PCN > NCN: Direction signal to FDD cleared to 0, and Step
Pulses are issued. (Step Out)
The rate at which Step pulses are issued is controlled by
Stepping Rate Time (SRT) in the Specify command. After
each Step pulse IS Issued NCN is compared against PCN,
and when NCN = PCN, Status register O's Seek End (SE)
flag is set to 1, and the command is terminated. At this point
FDC interrupt goes High. Bits 00-03 in the Main Status
register are set during the Seek operation and are cleared
by the Sense Interrupt Status command.
During the command phase of the Seek operation the FDC
is in the FDC Busy state, but during the execution phase it is
In the Nonbusy siaie. While the FOG is in the Nonbusy sto.tc,
another Seek command may be issued, and in this manner
parallel Seek operations may be done on up to four drives at
once. No other command can be issued for as long as the
FDC is in the process of sending step pulses to any drive.
If an FDD is in a Not Ready state at the beginning of the
command execution phase or during the Seek operation,
then Status register D's Not Ready (NR) flag is set to 1, and
the command is terminated after bit 7 is set to 1 and bit6toO.
If writing three bytes of Seek command exceeds 150/As, the
timing between the first two step pulses may be 1ms shorter
than that set in the Specify command.

933

Recalibrate
The function of this command is to retract the ReadlWrite
head within the FDD to the Track 0 position. The FOC clears
the contents of the PCN counter and checks the status ofthe
Track 0 signal from the FDD. As long as the Track 0 signal is
Low, the Direction signal remains 0 and step pulses are
issued. When the Track 0 signal goes High, the Status
register O's SE flag is set to 1 and the command is
terminated. If the Track 0 signal is still Low after 77 step
pulses have been issued, the FDC sets Status register O's SE
and Equipment Check (EC) flags to 1s and terminates the
command after Status register 0, bit 7 is cleared to 0 and bit
6 is set to 1.
The ability to do overlap Recalibrate commands to multiple
FDDs and the loss of the Ready signal, as described in the
Seek command, also applies to the Recalibrate command.
If the Diskette has more than 77 tracks, the Recalibrate
command should be issued twice, in order to position the
Read/Write head to Track O.

Sense Interrupt Status
An interrupt signal is generated by the FDC for one of the
following reasons:
1. Upon entering the Result phase of command:
o Read Data
0 Read Track
o Write Data
0 Read 10
o Write Deleted Data
0 Format Track
o Read Deleted Data
0 Scan
2. Ready Line of FDD changes state
3. End of Seek or Recalibrate command
4. During Execution phase in the non-DMA mode
Interrupts caused by reasons 1 and 4 occur during normal
command operations and are easily discernible by the
processor. During an execution phase in non-DMA mode,
Os in the Main Status Register is High. Upon entering the
Result phase this bit is cleared. Reasons 1 and 4 do not
require Sense Interrupt Status commands. The interrupt is
cleared by ReadinglWriting data to the FDC. Interrupts
caused by reasons 2 and 3 may be uniquely identified with
the aid of the Sense Interrupt Status command which resets
the Interrupt signal and, via bits 5,6, and 7 of Status register
0, identifies the cause of the interrupt (Table 7).
Table 7. Interrupt Identification

Seek End
BitS

Interrupt Code

Bit 6

Bit7

o
o

934

Cause

Ready Line changed state,
either polarity

o

Normal Termination of Seek
or Recalibrate command

o

Abnormal Termination of
Seek or Recalibrate
command

The Sense Interrupt Status command is used in conjunction
with the Seek and Recalibrate commands which have no
result phase. When the disk has reached the desired head
position, the Z765A sets the interrupt line true. The host CPU
must then issue a Sense Interrupt Status command to
determine the actual cause of the interrupt, which could be
Seek End or a change in ready status from one of the drives.
Figure 6 is a graphic example.

Specify
The Specify command sets the initial values for each of the
three internal timers. The Head Unload Time (HUT) defines
the time from the end of the execution phase of one of the
Read/Write commands to the head unload state. This timer
is programmable from 16 to 240ms in increments of 16ms
(01 = 16ms, 02 = 32ms ... OF16 = 240ms). The Step Rate
Time (SRT) defines the time interval between adjacent step
pulses. This timer is programmable from 1 to 16ms in
increments of 1ms (F = 1ms, E = 2ms, and 0 = 3ms). The
Head Load Time (HLT) defines the time between the Head
Load signal's going High and the start of the Read/Write
operation. This timer is programmable from 2 to 254ms in
increments of 2ms (01 = 2ms,02 = 4ms, 03 = 6ms ... 7F =
254ms).
The time intervals mentioned are a direct function of the
8MHz clock; if the clock were reduced to 4MHz (minifloppy
application), all time intervals would be increased by a factor
of 2.
The choice of a DMA or non-DMA operation is made by the
Non-DMA (NO) bit. When this bit is High (NO = 1), the
Non-DMA mode is selected; when NO = 0, the DMA mode
is selected.

Sense Drive Status
The processor uses this command to obtain the status of the
FDDs. Status register 3 contains the Drive Status information
stored internally in FDC registers.

Invalid
If an Invalid command (not defined above) is sent to the
FDC, then the FDC terminates the command after Status
Register 0 bit 7 is set to 1 and bit 6 to O. No interrupt is
generated by the Z765A during this condition. Bits 6 and 7
(010 and ROM) in the Main Status register are both High,
indicating to the processor that the Z765A is in the Result
phase and the contents of Status register 0 (STO) must be
read. When the processor reads Status register 0, it finds an
80H indicating the receipt of an Invalid command.
A Sense Interrupt Status command must be sent after a
Seek or Recalibrate Interrupt, otherwise the FDC considers
the next command as an Invalid command.
This command may be used as a No-Op command to place
the FDC in a standby or No Operation state.

"I_

SEEK (OR RECALIBRATE) COMMAND

COMMAND PHASE

'I"

SENSE INTERRUPT STATUS COMMAND

..

EXECUTIONPHASE _ _ COMMANDPHASE_I_AESULTPHASE_

'NT

I

I

I

D/s-¥n un u Jjl
AD

---u

U
DIO~
RQM

IJU

I

u

U

u--u

OPCOOEFOR

HO/DRIVE NOT
WRITTEN

u---u

U

U

-.ll.......---,~y'---:--INSTRUCTION
WRITTEN

ljJ n

un.

____

u
n

--I

NCNWRITTEN

INTOZ765A

n

n

N

~

~

en

;III
IiIJ

REGISTER STO
READ BY
PROCESSOR

WRITTEN
INTOZ765A

INTOZ765A

J[

STATUS

OPCOOE FOR
INSTRUCTION

INTO Z765A

J[

"n

Figure 6. Seek, Recalibrate, and Sense Interrupt Status

1··-----------REPEATNTlMES----------_oo·1

INDEX~

Figure 7. Data Format, FM Mode

1··-----------REPEATNTlME.S------------.~11

INDEX~

Figure 8. Data Format, MFM Mode

GA_P_'_~~_'_O_~___G_A_P_2__~____D_A_~

L-___
GA_,._'_'__-L___I_'M____L-___

VCD/SYNC

____

~ G_A_P_3__-L_____'_o~>l~1-<~I----GA-p-4-b--~
__

...JI

_~
__" ' __________________

WE

/

r-------'\

\

f

NOTE Read - - - - -

Wr.te---

Figure 9. Data Timing Relationships

2357-006, 007, 008, 009

935
-------~

AC CHARACTERISTICS
TA

=

-10°C to

+ 70°C; Vee = + 5V ± 5% unless otherwise specified.

Number Symbol

Parameter

TcC

Clock Cycle Time

Min

Typ1

Max

Unit

120

125
125
250

500

ns
ns
ns

2

TwCh

Clock Width (High)

3

TrC

Clock Rise Time

20

ns

4

TfC

Clock Fall Time

20

ns

5
6
7

TsAR
TwRD

DIS, CS, DACK to RD -I Setup Time
DIS, CS, DACK from RD t Hold Time
RDWidth

8

TdRDf(Do)

RD -I to Data Output Delay

9

TdRDr(Dz)

RD t to Data Float Delay

10

TsCS(WRf)

11

ThCS(WRr)

Control Signal (DIS, CS, DACK) to
WR -I Setup Time
Control Signal (DIS, CS, DACK) from
WR t Hold Time

0

ns

12

TwWR

WRWidth

250

ns

13

TsD(WRr)

Data to WR t Setup Time

150

ns

14

ThD(WRr)

Data from WR t Hold Time

5

ns

15

TdRDr(INT)

RD t to INT Delay Time

500

ns

16

TdWRr(INT)

WR t to INT Delay Time

500

ns

17

TcDRO

DRO Cycle Time

18

DACK -I to DRO -I Delay

ThRA

19

TdDRO(DACK)
TdDACK(DRO)

20

TwDACK

DRO t to DACK -I Delay
DACKWidth

21

TwTC

TCWidth

22

TwRST

Reset Width

40

ns
ns

0
0
250

ns

20

200

ns

CL

100

ns

CL

= 100pf
= 100 pf

ns

0

13
200
200
2

/ls
ns
ns
TcC

TcC

= 125 ns

TcC
14

TcC
4
2
2
1

TcWCK

WCK Cycle Time

24

TwWCKh

WCK Width (High)

350

/ls
/ls
/lS
/ls
ns

25

TrWCK

WCK Rise Time

20

ns

26

TfWCK

WCK Fall Time

ns

27

TdWCKr(PS)

WCK t to Preshift Delay Time

20

20
100

28

TdWCKr(WEr)

WCK t to WE t Delay Time

20

100

ns

100

80

250

29

TdWCKr(WDA)

WCK t to WDA Delay Time

20

TwRDDh

RDD Width (High)

40

31

TWCY

Window Cycle Time

= 0 5'14"
= 1 5'/4"
= 08"
= 1 8"

MFM
MFM
MFM
MFM

= 0 5'/4"
= 1 5'/4"
= 08"
= 1 8"

32

TsW(RDDh)
ThW(RDDI)

Window to RDD t Setup Time
Window from ROD -I Hold Time

15

ns

33
34

TsUS(RWh)

Umt Select to RW/SEEK t Setup Time

12

/lS

TsRWr(DIR)

RW/SEEK t to LCT/DIR Setup Time

7

/ls

35

TsDI R(STEPr)

LCTIDIR to STEP t Setup Time

1

/ls

36

ThUS(STEPI)

Unit Select from STEP -I Hold Time

5

/ls

ns
ns

4
2
2

= 25°e and nominal supply voltage.

MFM
MFM
MFM
MFM

ns

30

2. Under software control, the range is from 1 msto 16 ms at 8 MHz clock period.

936

8" FDD
5'/4" FDD

ns

23

NOTES. 1. Typical values forTA

Test Condition

/ls
/ls
/ls
/lS

AC CHARACTERISTICS (Continued)
TA = -10°C to + 70°C; Vee = + 5V ± 5% unless otherwise specified.
Number Symbol

Parameter

Typl

Min

Max

Unit

37

TwSTEPh

STEP Width (High)

38
39

TcSTEP
TwFRh

STEP Cycle Time
FAULT RESET Width (High)

40

TwWDAh

Write Data (WDA) Width (High)

41

ThUS(SEEKD
ThSEEK(DIR)

Unit Select from RW/SEEK ~ Hold Time

15

J.lS

42

RW/SEEK from LCTIDIR Hold Time

30

J.ls

43
44

ThDIR(STEPD
TwlDX

LCT/DIR from STEP. Hold Time
INDEX Width (High and Low)

24
10

TcC

45

TdDROh(RDI)

ORO t to RD ~ Delay Time

800

f's

46

TdDROh(WRI)

ORO t to WR • Delay Time

250

47

TdDROh(RWh)

ORO t to RD t or WR t Delay Time

6

8

7

16
8

Note 2

Test Condition

f'S

Note 2

f's

10

f'

ns

To-50

J.ls

J.ls

12

J.ls

NOTES. 1 TYPical values for TA ~ 25°e and nominal supply voltage.
2 Under software control, the range IS from 1 msto 16 ms at 8 MHz clock period

Processor Read Operation
eLK

~~-~
-°1AD

1

~

I

CD-

J

~
DATA

--

------c

CD

)-----

--®--

Processor Write Operation

~"'~K~
--::'®IWA

-®-®-------0

--®------DATA

)

®

-

K
--®---

937

DMA Operation
DRQ

---®-----•

®}-----·~I

FDD Write Operation

-@WRITE CLOCK

WRITE ENABLE

PRESHIFT 0 OR 1

WRITE DATA

Normal
Late

Preshift 0

Preshift 1

o
o

o
o

Early

Seek Operation
U50,1

=:)

---

K

STABLE

- -

®

RW/SEEK

®

-@

@

DIRECTION

~

-@

--... 143

~

STEP

-®
•

938

-®-

""

@

•

FLT Reset
FAULT RESET =
FILE UNSAFE RESET

-1:1'--

INDEX

~

FDD Read Operation

READ DATA WINDOW

Terminal Count

RESET

TC~

-='I®I---=-

RESET~

----=.I®I---=-

939

ABSOLUTE MAXIMUM RATINGS
TA = 25°C
Operating Temperature ................ O°C to + 70°C
Storage Temperature .............. - 65°C to + 150°C
All Output Voltages .................... - .3V to + 7V
All Input Voltages ...................... - .3V to + 7V
Supply Voltage Vee .................... - .3V to + 7V
Power Dissipation ............................. 1W

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above these indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

DC CHARACTERISTICS
TA = O°C to + 70°C; Vee = + 5V

± 5% unless otherwise specified.

Symbol

Parameter

VIL
VIH
VOL
VOH

Input low Voltage
Input High Voltage
Output low Voltage
Output High Voltage
Input low Voltage (ClK + WR Clock)
Input High Voltage (ClK + WR Clock)

VILe
VIHe
lee
III
ILOH
ILOL

Min

'TYP'

Max

-0.3
2.0

0.8

2.4
-0.3

Vee
0.45

2.4

Vee + 0.3
150
10
-10
10
-10

low level Output leakage Current
=

V
V
V
V
V
V
mA

Vee
0.40

Vee Supply Current
Input Load Current
(All Input Pins)
High level Output leakage Current

'Typical values for TA

Unit

Test Condition

IOL = 2.0mA
IOH = -200,..A

,..A
,..A

VIN = Vee
VIN = OV

,..A

VOUT = Vee
VOUT = +0.40V

,..A

25°e and nominal supply voltage.

CAPACITANCE
TA

= 25°C; fc = 1 MHz; Vee = OV

Symbol

Parameter

CeLoeK
CIN

Clock Input Capacitance
Input Capacitance
Output Capacitance

COUT

Min

Max

Unit

20
10
20

pF
pF

Test Condition

All pins except pin under
test tied to AC Ground

pF

ORDERING INFORMATION
Ordering information is available from your local Zilog Sales
Office.
Package drawings are in the Package Information section in
this book.
Refer to the Literature List for additional documentation.

940

00·2357·01

Military
Products

Zilog

Military Products

April 1985
Zilog offers high reliability versions
of many of our Z8000, Z80, and Z8
logic circuits. Zilog military microcircuits are fabricated, assembled, and
tested in accordance with the latest
requirements of MIL-STD-883 using
the highest quality and reliability
standards.
Zilog's multi-million dollar fabrication facility in Nampa, Idaho incorporates the highest quality and latest
technological equipment available
for semiconductor wafer processing.
Our Nampa wafer fabrication line is
JAN M il-M-3851 0 certified and
meets stringent government requirement for process control, facility
cleanliness, documentation, and
equipment calibration.
Zilog has implemented at our
Campbell, California military testing
(operations) facility the latest test
procedures to ensure maximum
performance and reliability in addition to full compliance with the military specifications.

Zilog has extensive operator training programs, carefully monitored
internal process specification controls, strict equipment maintenance
procedures, ongoing research and
development, and continuous data
management to ensu re that Zilog
military products represent the industry standard for excellence.

MILITARY SOFTWARE
Ada
Ada, a high-level programming
language developed and specified
by the U.S. Department of Defense,
is designed for use in imbedded
applications.
Zilog currently has an Ada Compiler available which implements
90% of the ANSI/Mil-STD-1815A
requirements. This Compiler, developed by Irvine Computer Science
Corporation (lCSC), features high
compile speed and efficient code

generation. The compiler generates
Z8001 segmented memory or
Z8002 nonsegmented memory
object code. Full implementation
and validation is planned for the
Spring of 1985.

II
••
••
IIJ

~

l

Do

JAN MIL-M-38510
Zilog Military Products has a clear
and ongoing commitment to the
qualification and production of highreliability JAN MiI-M-3851 0 QPL
components.
Zilog's strong JAN commitment is
exemplified by the qualification of
our Z8002, Z8002A, Z8400 and
Z8400A Military microprocessors.
To meet the industry needs for a
strong support network, our goal is
the qualification of many of our
Z8000 peripheral products.
Zilog Military Products has proven
its ongoing involvement in the military community and Will continue to
dedicate resources toward that goal.

943

;

MIL-STD-883 MILITARY PROCESSED PRODUCT
•

MH-Std-883 establishes uniform methods and procedures for testing microelectronic devices to insure the
electrical, mechanical, and environmental integrity and
reliability that is required for military applications.

•

Mil-Std-883 Class B is the industry standard product
assurance level for military ground and aircraft
application.

• The total reliability of a system depends upon tests that
are designed to stress specific quality and reliability
concerns that affect microelectronic products.
• The following tables detail the 100% screening and electrical tests, sample electrical tests, and Qualification!
Quality Conformance testing required.

Zilog Military Product Flow

ENVIRONMENTAL SCREENING
• STABILIZATION BAKE
• TEMPERATURE CYCLE
• CENTRIFUGE
• FINE LEAK
• GROSS LEAK

944

2351-010

Military Product Cross Reference
Products Are Available in MIL-STD-883 Class B Flow
Unless Otherwise Noted (t).
Package
Device

2.5

Speed in MHz
4.0
6.0
8.0
X

'Z8001

X

'Z8001A

X

'Z8001B

X

'Z8002

X

'Z8002A

X

'Z8002B

X

'Z8010

X

'Z8010A

X

'Z8010B

X

Z8030

X

Z8030A

X

Z8530

X

Z8530A

X

Z8036

X

Z8036A

X

Z8536

X

Z8536A

X

Z8038
Z8038A

X

Z8581

X

Z8420

Z8430

Z8440

Z8442
Z8444
Z8444A

(@)68

F

Z8000 SEG CPU

48

(@)68

F

Z8000 SEG CPU

48

(@)68

F

Z8000 SEG CPU

40

(t)44

Q

Z8000 NON-SEG CPU

40

(t) 44

Q

Z8000 NON-SEG CPU

F

Z8000 NON-SEG CPU

40

(t) 44

(t) 48

(@)68

Z8000 Z-MMU Z-BUS

(t) 48

(@)68

Z8000 Z-MMU Z-BUS

(t) 48

(@)68

40

(t) 44

F

Z8000 Z-SCC Z-BUS

40

(t) 44

F

Z8000 Z-SCC Z-BUS

40

(t) 44

F

Z8000 SCC Multi Bus

40

(t)44

F

Z8000 SCC Multi Bus

40

(t)44

F

Z8000 Z-CIO Z-BUS

40

(t) 44

F

Z8000 Z-CIO Z-BUS

40

(t) 44

F

Z8000 CIO Multi Bus

40

(t)44

F

Z8000 CIO Multi Bus

(@)40

(@)44

F

Z8000 Z-FIO Z-BUS

(@)40

(@)44

F

Z8000 Z-FIO Z-BUS

F

Z8000CGC

F

Z8000CGC
Z80CPU

40

(t) 44

Q

Z80CPU

40

(t) 44

Z80PI0

X

40

(t) 44

Z80PI0

28

(t) 44

Z80CTC

X

28

(t) 44

X
X
X
X
X

Z80S10/0

40

Z80S10/0

40

Z80S10/1

40

Z80 S10/1

40

Z80S10/2

40

Z80S10/2
(t) 44

X

Z8611
Z8671
Z8681

(t) 44

X
X
X

-=...
I»

~

•
a
t~
fit

Z80CTC

40

X

II

Z8000 Z-MMU Z-BUS

Q

X

Z8442A

48

Description

(t) 44

X

Z8441 A

38510

(TBO) 44

X

Z8440A
Z8441

Pins

40

X

Z8430A

Pins

(t) 18

X

Z8420A

MIL-M-

(t) 18

X

Z8400A

L(LCC)

(TBO)44

Z8581-10
Z8400

10.0

JAN

C(DIP)

Z80 SIO/O, 1,2
Z80 SIOIO, 1,2

(t) 40

(TBO) 44

Z8MCU

(t) 40

(TBO) 44

Z8 MCU BASIC Debug

(t) 40

(TBO)44

Z8ROMIess

• Available In -55°C to + 110°C temperature range.
Future Package, contact your local sales representative for current availability
Device/Package currently available in military temperature range only Contact your local sales representative for current Class B flow availability.
Q
JAN qualifled/dual-in-Ilne package only
Future proposed JAN product/dual-In-Ilne package only
F
TBD To be determined
@

t

945

Table I
MIL·STD·883 Class B Screening Requirements
Method 5004
Mil-Std-883
Test

Method

Test Condition

Requirement

Internal Visual

2010

Condition B

100%

Stabilization Bake

1008

ConditionC

100%

Temperature Cycle

1010

ConditionC

100%

Constant Acceleration (Centrifuge)

2001

Condition E or D(Note 1), Y1 Axis Only

100%

Fine Leak

1014

Condition A2

100%

Gross Leak

1014

ConditionC

100%

Zilog Military Electrical Specification
Stallc/DCTC = +25°C

100%

Condition D(Note 2), 160 hours,

100%

Imtlal Electrical Tests

Burn-In

1015

TA = +125°C
Interim Electrical Tests

Zllog Military Electrical Specification
StaticlDC TC = + 25°C

100%

PDA Calculation

PDA = 5%

100%

Final Electrical Tests

Zilog Military Electrical Specification
StaticlDC TC = + 125°C, - 55 0c(Note 3)
Functional, Switching/AC TC = +25°C

100%

Quality Conformance Inspection (QCI)
Group A
Each Inspection Lot
Group B
Every 6 Weeks
Group C
Every 12 Months
Every 12 Months
Group D

5005
5005
5005
5005

External Visual

2009

(See Table II)
(See Table III)
(See Table IV)
(See Table V)

QA-Shlp
NOTES
1 Applies to larger packages which have an Inner seal or cavity perimeter of two Inches or more In total length or have a package
mass of ;'5 grams
2 In process of fully implementing of Condition D Burn-In Circuits Contact factory for copy of specific burn-In circuit available.
3 TC = - 55°C to + 125°C unless otherWise specified on Individual device electncal specification

946

Sample
Sample
Sample
Sample
100%
100%

Table II Group A
Sample Electrical Tests
MIL-STD·883 Method 5005
LTPD
Max Accept =2

Subgroup

Tests

Temperature (Td

Subgroup 1

StaticlDC

+25°C

2

Subgroup 2

Static/DC

+125°C

3

Subgroup 3

StatlclDC

-55°C

5

Subgroup 7

Functional

+25°C

2

Subgroup 8

Functional

-55°C and +125°C

5

Subgroup 9

Switching/AC

+25°C

2

Subgroup 10

Switching/AC

+ 125°C

3

Subgroup 11

Switching/AC

-55°C

5

NOTES:
• The specific parameters to be included for tests In each subgroup shall be as specified In the applicable detail electncal speclflcalion. Where no
parameters have been identified in a particular subgroup or test within a subgroup, no Group A testing IS required for that subgroup or test
• A single sample may be used for all subgroup testing. Where required size exceeds the lot Size, 100% inspection shall be allowed
• Group A testing by subgroup or within subgroups may be performed in any sequence unless otherWise specified.
• TC = - 55°C to + 125°C unless otherWise specified on individual device electncal specification.

-a
;

.:_Do
::

947

Table III Group B
Sample Test Performed Every 6 Weeks to
Test Construction and Insure Integrity of Assembly Process.
MIL·STD·883 Method 5005

Subgroup

MiI·Std·883
Method

Test Condition

Quantity or
LTPD/Max Accept

Subgroup 1
PhYSical Dimensions

2016

2/0

Subgroup 2
Resistance to Solvents

2015

4/0

Subgroup 3
Solderability

2003

Subgroup 4
Internal Visual and Mechanical

2014

SubgroupS
Bond Strength

2011

C

15(Note2)

1018

1000 ppm.
maximum at + 100°C

3/0

Solder Temperature
+245°C ± 5°C

15(Note 1)

1/0

Subgroup 6(Note 3)
Internal Water Vapor Content

or 5/1

Subgroup 7(Note 4)
Seal
7a) Fine Leak
7b) Gross Leak

5

1014

7a) A2
7b) C

Subgroup 8(Note 5)
Electrostatic Discharge Sensitivity

3015

Zilog Military Electrical
Specification
Static/DCTC = +25°C
A = 20-2000V
B

= >2000V

15/0

Zilog Military Electrical
Specification
Static/DCTC = +25°C
NOTES.
1. Number of leads inspected selected from a minimum of 3 devices.
2. Number of bond pulls selected from a minimum of 4 devices.
3. Test applicable only if the package contains a dessicant.
4. Test not required if either 100% or sample seal test is performed between final electrical tests and external visual during Class B screening.
5. Test required for initial qualification and product redesign.

948

Table IV Group C
Sample Test Performed Periodically Every
12 Months to Verify Integrity of the Die.
MIL-STD-883 Method 5005
Quantity or

MII-Std-883

Subgroup

Method

Test Condition

LTPD/Max Accept

Subgroup 1
Steady State Operating Life

1005

Condition D(Note 1), 1000 hours at

5

+ 125°C

End Point Electrical Tests

Subgroup 2
Temperature Cycle

Zilog Military Electrical Specification
TC = +25°C, +125°C, _55°C(Note3)

1010

ConditionC

Constant Acceleration (Centrifuge)

2001

Condition E or O(Note 2), Y1 Axis Only

Seal
2a) Fine Leak
2b) Gross Leak

1014

Visual Examination

End Point Electrical Tests

-j......
II

15
2a) Condition A2
2b) Condition C

i

10100r1011
Zilog Military Electrical Specification
TC = +25°C, + 125°C, _55°C(Note3)

NOTE:
1. In process of fully implementing Condition D Burn-In Circuits. Contact factory for copy of specific burn-in circuit available.
2. Applies to larger packages which have an inner seal or cavity perimeter of two inches or more in total length or have a package
mass of ;'5 grams.
3. Tc = -55°C to + 125°C unless otherwise specified on individual device electrical specification.

949

Table V Group 0
Sample Test Performed Periodically Every 12 Months to Insure Integrity of the Package.
MIL-STD-883 Method 5005
Subgroup

MiI·Std-883
Method

Quantity or
Test Condition

LTPD/Max Accept

Subgroup 1
Physical Dimensions
Subgroup 2
Lead Integ rity
Seal
2a) Fine Leak
2b) Gross Leak
Subgroup 3
Thermal Shock

2016
2004

15
Condition B2 or D(Note 1)
2a) Condition A2
2b) Condition C

1011

Condition B minimum,
15 cycles minimum

Temperature Cycling

1010

Condition C, 100 cycles minimum

Moisture Resistance

1004

Seal
3a) Fine Leak
3b) Gross Leak

1014

Visual Examination

1004 or 1010
Zilog Military Electrical Specification
TC = +25°C, + 125°C, _55°C(Note6)
2002

Condition B minimum

Vibration Variable Frequency

2007

Condition A minimum

Constant Acceleration (Centrifuge)

2001

Condition E or D(Note 2), Y1 Axis Only

Seal
4a) Fine Leak
4b) Gross Leak

1014

Visual Examination

1010or1011
Zilog Military Electrical Specification
Tc = +25°C, +125°C, _55°C(Note6)
1009

Seal
5a) Fine Leak
5b) Gross Leak

1014

Visual Examination

1009

Subgroup 6
Internal Water Vapor Content

15

4a) Condition A2
4b) Condition C

End Point Electrical Tests
Subgroup 5
Salt Atmosphere

15

3a) Condition A2
3b) Condition C

End Point Electrical Tests
Subgroup 4
Mechanical Shock

15

1014

Condition A minimum
15
5a) Condition A2
5b) Condition C

1018

5,000 ppm. maximum water
content at + 100°C

3/0 or 5/1

Subgroup 7(Note 3)
Adhesion of Lead Finish

2025

15(Note4)

2024

5/0

Subgroup 8(Note 5)
Lid Torque

NOTES:
1. Lead Integrity Condition 0 for leadless chip carners
2. Applies to larger packages which have an inner seal or cavity
perimeter of two inches or more in total length or have a package
mass of ,,5 grams.

950

3.
4
5.
6.

Not applicable to leadless chip carriers.
LTPD based on number of leads.
Not applicable for solder seal packages.
Tc - 55°C to + 125°C unless otherwise specified on indiVidual
deVice electrical specification

00-2034-04

Developmeat
Products

Zilog

Comprehensive
Development Environments
for All Zilog Microprocessors
April 1985

Zilog's development system products feature Ideal environments for
software development for the Z8 and
Z8aaa microprocessors. The modularized design approach of the Zilog
development systems allows the
user a choice of hardware and software modules to meet current
needs, while providing the necessary upgrade possibilities for future
requirements.
The System 80.0.0. concept partitions software and hardware development tools into specially tailored
devices. Software and hardware
checkout are handled by separate
yet compatible products. Software
can be developed on both Zilog and
non-Zilog hosts using available compilers and cr:Jss-compilers. In either
case, compatible hardware emulation systems are available at several
levels of complexity. Standard
RS-232 links provide for uploading
and downloading of programs
between hosts and emulators.

System 80.0.0., a high-performance,
multiuser, multitasking software
development host, combines the
commercial system's function and
the development system concept.
The Z8aaa-based System 80.0.0.
hardware incorporates a highperformance Winchester disk, as
well as intelligent disk and tape controllers, to further improve performance. The UNIX-based operating
system is specifically designed for
software development and test processing. Numerous development
tools are available including a symbolic debugger, various libraries,
and the programming languages C,
Ada, FORTRAN, and Pascal.
Because the operating system treats
emulators as System 80.0.0. peripherals, the system works with EMS
80.0.0., Z-UPC, Z-SCAN 8, 80., 80.0.0.
or non-Zilog emulators to provide
total product development support
for multiple microprocessors.
Zilog has an emulation device
called Z-SCAN (Zilog Stand-Alone
Analyzer) and a high-level emulation
device called EMS 80.0.0.. The basIc
idea behind Zilog development
systems is to allow hardware and
software to be developed simultaneously from the beginning of the project. Along with Zilog's System 80.0.0.
host, or other UNIX hosts such as
VAX, a multiuser development environment can be created in conjunction with the Z-SCAN family and the
EMS 80.0.0..

Z-SCAN is easy to master and so
low-cost that every engineer can
afford one. The Z-SCAN family includes emulators for the Z8, Z8a,
and Z8aaa family of microprocessors. The features of the Z-SCAN
family include hardware breakpoints,
real-time trace, and real-time emulation from mapped memory. The
menu-oriented user interface provides a short learning time for the
first time user, as well as advanced
debug capabilities for the experienced engineer.
EMS 80.0.0. is a sophisticated emulation management system that aids
in the development of Z8DDa MPU
implementations. By providing logic
state analysis, high-speed emulations, complex triggering, a large
real-time trace buffer, and large
mappable memory, EMS 80.0.0.
makes emulation and debugging
both easier and faster. EMS 80.0.0.
also provides in-circuit emulation for
Z8aa1, Z8DD2, and Z8aD3 microprocessors.
The Z8 and Z8Daa Development
Modules are single-board microcom
puters that permit the development
of code for the Z8, Z8aa1 , and
Z8a02. They facilitate prototyping
with large wire-wrap areas and are
totally transparent to the host CPU
systems.

Z8\!) Develop.eDt
Modale

Zilog

Product
DescrlptloD

April 1985
• Two 4K zas are used on the board:
one as board manager and one for
emulahon (without real-time trace)
or other user-defined configuration.

81

J
i••

• 4096 bytes of static RAM allow convenient creation and debugging of
user code.
• On-board socket tests user code in a
2716 or 2732 EPROM.
• Up to 4096 hardware breakpoints on
address compare cover the entire
internal ROM space.
• Versatile monitor software allows
debugging, with register/memory
examination and manipulation, and
file upload and download.
• "Transparent" operation allows
terminal-to-host communication
without disconnecting the Development Module.
• Wire-wrap area for prototyping.
• za board management is operated at
7.3728 MHz for baud rate purposes.
The User za has SWitch-selectable 8
or 12 MHz crystals.

OVERVIEW
The za Development Module is a
Single-board microcomputer system
speClhcally designed to assist In the
development and evaluation of hardware and software designs based on the
Z8 microcomputer family. It allows the
user to build a prototype using the za
prototyping device, thereby developing
code that will eventually be maskprogrammed into the Z8 on-chip ROM.
Two Z8 devices exist on the Z8
Development Module: the Monitor za
serves as a board controller, while the
User Z8 is user-definable. All user
ports on the User za are uncommitted
and can be configured to suit any application.

Up to 4096 bytes of high-speed static
RAM are available to simulate internal
ROM. Also, dll oCl-boa!'d EPROM
socket allows the user to substitute
EPROM for the ROM. This enables the
user to store the software without
building special hardware.
The EPROM-resident monitor software offers register and memory
manipulation, as well as a convenient
means to upload and download software between the host and user RAM
space.
The Development Module connects
to the CRT terminal and host system
via two on-board RS-232-C serial ports;
this places the Development Module

between the CRT and host. A simple
command makes the Development
Module transparent in the serial path,
which allows software to be developed
on the host-resident assembler without
disconnecting the Development Module
from the CRT and host.
The Development Module can
operate stand-alone for simple debugging operations, or it can interface
directly to a host system such as the
Zilog System 8000 for software development and file storage.
Fourteen square inches of wire-wrap
area with 5 V and ground points are
provided near the User Z8 for prototyping.

955

FUNCTIONAL DESCRIPTION
Hardware. The two Z8 microcomputer
units (Monitor MCU and User MCU)
are at the heart of the Z8 Development
Module. The Monitor MCU controls
operation of the User MCU using the
monitor/debug software, which resides
in 4K bytes of EPROM. Hardware
breakpoint logic provides a maximum
of 4096 breakpoints. Single-stepping
with software trace capabilities is also
available.
The User MCU is controlled by the
Monitor MCU via internal address/data
and control lines brought out to exter-

nal pins. Th,s effectively leaves all
ports on the User MCU unconfigured
and available for the user. The 4K
bytes of static RAM on the internal bus
are reserved for code that is executed
by the User MCU. Execution IS done in
real time at full processor speed.
In addition to the wire-wrap area, a
40-pin header (3M type 2395-1002) for
the User Z8 can connect to a ribbon
cable with a 40-pin plug, which will
then plug into a target system. Two
switches, Mode and Reset, provide a
means to re-enter the Momtor and to

Monitor Commands. This group of commands controls
execution of the User MCU, monitors user interrupts and
transfers control from the monitor to the host system.
GO 


Causes User MCU to execute its
program and disallows further
debugging until a BREAK or
HALT command is encountered.

HALT

Halts program execution of the
User MCU.

QUIT

Returns control to the host system
and enters the "transparent" mode.

INTERRUPTS IE/D]

Enables or disables all usergenerated interrupts. Note: All
user interrupts are automatically
disabled when a breakpoint is
encountered. It is necessary to
reenable such interrupts with this
command.

956

reinitialize the system, respectively.
The baud rate, from 110 to 19200, is
the same baud rate used for the terminal and host and is selected with an
on-board, four-element DIP switch.
Software. The monitor/debug program
includes debug, disassembly, inpuV
output, control, and host interface commands. These commands are grouped
into four major functional blocks:
monitor, debug, manipulation, and file
commands (see the following command
list).

Debug Commands. This group of commands allows the user
to debug code by tracing through code and setting breakpoints and jumps to specified locations within the "internal"
ROM space, which is simulated in 4K bytes of RAM.
BREAK 


Sets a breakpoint at the specified
address.

KILL I < ADDRESS> ]

Clears the breakpoint at the
specified address.

JUMP 


Allows the User MCU to jump to a
specified address anywhere within
the internal ROM space by changing the value of the Program
Counter.

NEXT I]

Causes execution of n instructions
of the User MCU and then halts
the User MCU.

TRACE

Causes single-step execution of the
User MCU. Every instruction
executed is output to the console.

I----t\
I~
I\r-

MONITOR

I·CODE

TRACE
STOP/GO

EPROM

REGISTERS

...

1.

;:....

.

t..

MONITOR DATA BUS

11
MONITOR

1"

MONITOR
EPROM

MCU

BREAK

PROGRAM

POINT

COUNTER

Ir

11

ir

v

1
RAM

ir

,7

DATA
MUX

~
I OAT!
BUS

USER
MCU

III
t..

MONITOR ADDR BUS

ADDR
MUX

V

~
BUS

I)::..
~
BUS

A

,

~

RS232C
PORTS

Y

ll~
TO CRT

TO HOST

Z8 Development Module Block Diagram

Manipulation Commands. The manipulation commands
display and alter registers and memory. This group can be
subdivided into two categories: register manipulation and
memory manipulation.

COMPARE

[1

Compares two blocks of user
memory data, one beginning at
ADDRESS I and the other at
ADDRESS 2 for n bytes.

Reglste, Manipulation

ZAPI < STARTING
ADDRESS> I < n> II

Disassembles and displays code at
a speC"ified starting address for a
specified number of bytes.

REGISTER [ I I < NEW
REG VALUE> I
WORKING REGISTERS

Allows examination and modification of the Z8 internal registers.
Displays contents of the current 16
working registers.

File Commands. The file group enables the user to upload
and download programs to and from the host system.

PHILL  < NUMBER
OF REGISTERS>
[ I

Stores the sequence of DATA
BYTES into User MCU registers
beginning at the STARTING
REGISTER and continues for the
NUMBER OF REGISTERS
speCified.

LOAD


Memory Manipulation
DISPLAY I [ II
number of bytes.
Allows a sequence of data bytes
SET 

beginning at the ADDRESS speci
fied to be written into user
[]
memory.
FILL < STARTING
ADDRESS>

[]

Stores the sequence of DATA
BYTES into user memory beginning at the starting ADDRESS and
continues for the LENGTH
speCified.

MOVE < SOURCE
ADDRESS>
< DESTINATION
ADDRESS>I1

Moves contents of a user memory
block from a source address to a
destination address for a length
of n bytes.

1007-001

Downloads a file to user memory
starting at the low address of the
file and continuing until the entire
file is transferred.
Creates a RIO file image of user
UPLOAD
memory, beginning at ADDRESS

I, creating default length records,

 and imaging memory for the
[] specified number of bytes.

Note: The following notation is used in the command description.
< > Enclose descriptive names for the
quantities to be entered, and are not
actually entered as part of the
command.
[I
Denote optional entries in the command syntax.
Denotes \\or."

957

SPECIFICATIONS
Processor:
Two 64-pin DIP ZSs
PIn spaCIng IS 0.070
Row spaCIng is 0.75
CPU Clock Frequency:
7.37 MHz for Monitor
8/12 MHz for User
Memory:
MonilorZ8
Scratch Pad RAM
RAM memory sIze: IK bytes
RAM addressIng: %2000 to %23FF
Mimmum speed: 300 ns

EPROM
Word size: 8 bits
Memory size: 8K bytes
AddressIng: 0 to %FFF internal
%1000 to %IFFF external
MInimum speed: 350 ns

User Z8
RAM (EPROM eqUIvalent)
Word size: 8 bils
Memory sIze: 4K bytes
AddressIng: 0 to %FFF (relative to
User)
%9000 to %9FFF (relative
to Monitor)
MInimum speed: 350 ns

Baud rate: Programmable 10 110, 150,
300, 600, 1200, 2400, 4800,
19200 bps
Emulalor cable lenglh: 12 Inches max.

Input/OulpUl:
Monitor Z8
Baud rales: Programmable to 110, 150,
300,600, 1200,2400,4800,
9600, 19200 bps
Connector Iype: Two 25-pin DB-25S
connectors
User Z8
Parallel interface: 32 1/0 lines undehned
Connector type: 40-pin PC edge
connector

Dimensions (LxW):
29.94 cm (II in.) x 35.56 em (l4V, in.)
Power Requirements:
IAAal +5Vdc ±S%
Environmental:
o to 50°C (+ 32° 10 + 122°F)
Up 10 90% humIdity wIthout condensahon

Ordering Information is available at
your local Zilog Sales Olliee.
Refer to the Literature List for additional documentation.

958

00-1007·02

Z8000®
Development Module

Zilog

Product
Description

April 1985

I

r
I

• Z800llZ8002 CPU Evaluation and
Debug Support
• 16K Words Dynamic RAM
(Expandable to 321 for User Cod..
Execution and Debug
• 32 Programmable 110 Lines
• EPROM Monitor and Debugger
• Transparent Operation Allows
Software Development without
Disconnection from CRT and Host
System
• RS-232C Standard Serial Interlaces
Compatible with Most CRT Terminals and Development Hosts
• Wire-wrap Area for Prototyplng

OVERVIEW
The 28000 Development Module is a
complete, single-board microcomputer
that is used as a tool for the evaluation
and debug of Z8000-based microprocessor systems. The Development
Module is used in the first stages of the
design and development process, not
only as a tool for evaluating 28000
microprocessor capabilities, but also as
an environment in which code can be
executed and debugged.
Evaluation. The Development Module
provides a ready-made environment in
which the user can execute software
unique to his Z8000-based application,

evaluate the CPU's performance, and
then reach a realistic decision about Its
suitability for a specific application.

Software Debug. In addition to use as
an evaluation tool, the Z8000 Development Module can be used to debug
and modify user code. For the software
designer, the Development Module is a
real Z8000 environment in which he
can execute code and carry out fairly
extensive debugging. For the hardware
designer, the Development Module is
an example of 28000 hardware design
which provIdes special hooks and wirewrap facihties to strap on additional
logic.

959

FUNCTIONAL DESCRIPTION
Z8000 code developed on a software
host may be downloaded serially to the
Development Module RAM area vIa a
serial port, and executed and debugged under EPROM monitor control.
Once the system is connected, no further disconnection is necessary as the
module has two serial ports (one connected to a host and the other connected to a CRT terminal). A simple
software command makes the development process transparent in the serial
path, thereby allowing direct communication between the host and termmal.
The serial RS-232C interfaces allow virtually any software development host
and CRT terminal to be used. For
PROM-based code testing, the development module is self-contained and
can operate stand-alone with a CRT
terminal, since the host is only
required for storage of user code
on disk.
A variety of jumper areas and
switches permit the selection of clock
rates ranging from 2.5 to 3.9 MHz; the
use of 2708, 2716, or 2732 EPROMs;
the use of 4K or 16K RAMS; serial
interface to modem, terminal, or teletype; 1/0 port addressing; and baudrate selection from 110 to 19200 baud.
Hardware. The Z8000 Development
Module is available in two versions:
one supports the segmented Z8001
microprocessor; the other supports the
non-segmented 28002 microprocessor.

Z8001 Development Module. The
Z8001 Development Module consists of
a Z8001 CPU, 16K words of dynamic
RAM (expandable to 32K words), 4K
words of EPROM monitor (userexpandable to 8K words), a Z80A SIO
providing dual serial ports, a Z80A
CTC peripheral chip providing four
counterltimer channels, two Z80A PIO
devices providing 32 programmable
VO lines, and wire-wrap area for prototyping hardware.
Z8002 Development Module. The
Z8002 Development Module consists of
a Z8oo2 CPU, 16K words of dynamic
RAM (expandable to 24K words), 2K
words of EPROM monitor (userexpandable to 8K words), a 280A SIO
device providing dual serial ports, a
Z80A CTC peripheral device providing
four counterltimer channels, two Z80A
PIO devices providing 32 programmable VO lines, and wire-wrap area
for prototyping.

960

COMMAND
INTERPRETER

DEBUGGER

,/

!l~

/
ZUog

1/

I~

V

'i!i::

1/
Figure I. Monitor Block Diagram

Software. The monitor software
(Figure 1) contained in EPROM (4K
words for the 2800 I and 2K words for
the Z8002) provides debugging commands, 1/0 control and host interface.
It consists of a terminal handler, command interpreter, debugger and
upload/download handler.

ensures command validity and passes
them to other software modules in the
monItor.

Terminal Handler. A Terminal Handler
provides interface to the console
device to facilitate output to a display
or printing mechanism and mput from
a standard ASCII keyboard.

Upload/Download Handler. The
Upload/Download Handler provides an
interface between the serial connection
and the host computer, the command
interpreter and the memory resources
of the Z8002 Development Module. It
formats and interprets asynchronous
data streams to and from the host and
provides error checking and recovery
for the serial interface (see Figure 2).

Debugger. The Debugger provides a
basic set of debug commands to allow
the user to start and stop program execution, display and alter CPU
registers, flags or memory, and trap
instruction sequences.

Memory Organization. Tables 1 and 2
show the memory maps for the two versions of the Development Module. The
organization of ROM and RAM in both
the segmented and nonsegmented
modes is indicated.

Command Interpreter. The Command
Interpreter scans console inputs,

/

ADDRESS

I I I

BYTE CHECK
COUNT SUM

I

I

CHECK C
SUM R

DATA

I I I I

I I I I

I

Figure 2. Serial Data Format

1047·00]' 002

Segment 0

Segment I

Address (Hex)

Memory

Address (Hex)

Memory

Address (Hex)

Memory

0000

Mamtor

0000

Monitor

0000

OFFF

EPROM

IFFF

EPROM

3FFF

Expansion RAM
(User Installed)

1000

User EPROM
(User Installed)

2000

User EPROM
(User Installed)

4000

Unused

3FFFF

FFFF

3FFF
4000

BFFF
COOO
FFFF

Standard
RAM
Expansion RAM
(User Installed)

4000

Momtor RAM
(Scratchpad Area)

49FF
4AOO
BFFF
COOO
FFFF

Table I. Z8002 Development Module Memory Map

Standard RAM
Expansion RAM
(User Installed)
Table 2. Z8001 Development Module Memory Map

MONITOR COMMAND SUMMARY

The following notation is used in the
command description:
< > Enclose descriptive names for the
quantities to be entered, and are
not actually entered as part of the
command.
[]

Denote optional entries in the command syntax.
Denotes "OR", ego WIB denotes that
either W or B may be used but not
simultaneously.

<

Prompt sign for the nonsegmented
28002 monitor.
Prompt sign for the segmented
Z8001 monitor.

The following commands apply when
the 28001 monitor is used. All commands listed remain the same except
those that permit reference to segmented addresses as follows:
 =
[ < segment number>] < offset
address>
 =
"<"">"
BREAK < address>
[]

Sets and clears a breakpoint at a
given memory address. The option
< n > allows specifIcation of the
number of occurrences, where n IS
from I to 128. The default is one.

COMPARE

 

Compares two blocks of memory
data beginning with the addresses
specified for  bytes, where n
is from I to 128. Errors are
reported on the console device.

DISPLAY < address>
[LIWIB]

Displays and modifies memory for
 number of words or bytes.
The optional entry allows data to
be handled as bytes, words, or
long words. The default is words.

FILL < address I >
< address 2> < word>

Stores the  from memory
address I to and including
address 2.

GO

Begins program execution at the
address contained m the current
PC; execution is resumed where it
was last mterrupted. All registers
are restored prior to execution.

IOPORT 

[WIB]

Allows direct communicahons from
the console to a selected I/O port.
A word (W) or a byte (B) may be
read from the selected port and a
word or byte may be sent to the
selected port; default is byte.

JUMP < address>

Unconditional branch to the specifIed address. All registers are
restored prior to execution.

MOVE < address I >
 

Moves contents of a memory block
from source address < address I >
to destination address
 for  bytes.

NEXT[]

Executes the next  machine
instructions.  may be from
I to 128. If n is omitted, I is
assumed.
Punches a copy of memory from
address I to address 2 on paper
tape on the console device. Automahcally turns on punch and a
null leader IS created.
Upload/Download section
describes the tape format used.

PUNCH < address I >


QUIT

Places serial channels into transparent mode. The 28000 Development Module must be connected to
both the Zilog host and the console
device, and the Development
Module acts as a message
switcher.

REGISTER
[ < register name> ]

Allows exammation and modification of Z8000 registers. 8-bit, 16-bit
or 32-bit quantities may be
selected by the appropriate
register-naming conventions.

TAPE

Loads memory from paper tape via
the console deVICe. The
Upload/Download section
describes the tape format used.

961

,

I

I

SPECIFICATIONS
Microprocessor
2800 I or 28002 CPU
Clock Rate: 2.5 MHZ or 3.9 MHz
Memory
ROM: 2K or 4K Words (Expandable
to 8K Words)
RAM: 16K Words (Expandable
to 32K Words)

Input/Output
Parallel: 32 Lmes (Two Z80A-PIOs)
Serial: Dual RS-232C or RS-232C and
Current Loop (Z80A-SIO)

Power
+5 V, 3 A
+12 V, I A
-12 V, 0.2 A

Note
The user has access to all bus sIgnals to allow

Physical
Height

custom system expanSIon mto the WIre-wrap area

off-board.

Interrupts
Maskable Vectored (256), Maskable
Non-vectored, Non-maskable,

Width
Depth
Weight

1.75 in. (4.5 em) InclUSive of
Standoffs
14.0 In. (35.6 em)
11.0 in. (27.9 em)
Approx. 30 oz. (850 gm)

SegmentatIon Trap

Ordering Information is available at
your local Zilog Sales Office.
Refer to the Literature List for additional documentation.

962

QO.1047-()2

Z-UPCDM
Uaiversal Peripheral Coatroller
Developmeat Module

Zilog

Product
Brief

April 1985

FEATURES
• Development Module (DM) for
Zilog's Universal Peripheral Controller (UPC).
• Emulates four versions of the
UPC:Z8090,Z8094,Z8590, and
Z8594.

• Connects to the host and terminal
via standard RS-232-C interface.
• Emulates Z-BUS and non-Z-BUS
UPCs with either masked ROM
or protopack with RAM/EPROM.

• Single-step trace capability.
• Monitor software allows file upload and download, register and
memory manipulation.

OVERVIEW
The Z-UPC is a simple and costeffective development tool that emulates four versions of Zilog's
Universal Peripheral Controller
(UPC). As a Development Module,
the Z-UPC is an ideal tool for system
development from design through
manufacturing.

Both Z-Bus compatible and non-ZBUS compatible types of UPC are
emulated by the Z-UPC. The Z-BUS
compatible Z-UPCs that are emulated are the Z8090 and Z8094. The
non-Z-BUS compatible UPCs that
are emulated are the Z8590 and the
Z8594. Connection with the host

and a terminal is accomplished via
two RS-232-C interfaces.
By supporting eight popular terminal
types and a wide variety of hosts,
the Z-UPC is easily integrated into
most operating environments.

963

FUNCTIONAL
DESCRIPTION
The Z-UPC is physically located
between the host system and the
user's terminal, connected via the
RS-232-C interface. The target cable
connects directly to the front for
safety and convenience. The Z-UPC
can operate in stand-alone mode for
simple debugging operations, or it
can be placed in transparent mode
to allow software development with
the host.
Hardware

The Z-UPC contains both a Z8 MCU
and a UPC. The Z8 MCU controls
monitor functioning, including operational commands and debug software. The UPC itself features a
256-byte register file including three
I/O port registers, 234 generalpurpose registers, and 19 control,
status, and special I/O registers.

Twenty-four pins can be dedicated
to I/O functions. These pins are
grouped logically into three eightline ports, which can be configured
in various combinations as input or
output, with or without handshake,
and with push-pull or open-drain
outputs.
Software

The monitor/debug program resides
in 4096 bytes of PROM and contains
debug, I/O, control, and host interface commands. This software is
divided into four functional groups:
• Monitor commands control the
Z8 MCU to monitor interrupts
and transfer control from the
monitor to the host system.

• Debug commands allow tracing
and jumps to user-specified
PROM locations.
• Manipulation commands permit
display and alteration of registers
and memory.
• File commands enable the user
to upload and download to and
from the host system.

ORDERING INFORMATION
Z-UPC DM (05-0207-00)
Refer to the Literature List for additional documentation.

Figure 1. Stand·Alone Development System

964

2322-001

OQ-2322.()2

EMS 8000
Emulator

Product
Description

Zilog

April 1985

FEATURES
• Snapshot feature permits partitioning of a large realtime trace module into many small trace memories.

• Complex triggering.

• Up to 126K bytes of high-speed, static, mappable
memory can be accessed by the target system.

• Large mappable memory space.

• Pulse output feature permits use of a high-end logic
analyzer.
• Network debugging is supported.
• Full access to the target microprocessor's registers,
memory, and I/O space is permitted.
• Transparent mode allows the same terminal to be
used for host and EMS user interface.

• Large real-time trace buffer.
• Real-time partitionable trace module for multiple recordings of program execution.
• Three parallel event comparators which can be
allocated for trigger, trace, breakpoint recognition,
and enable/disable functions.
• General-Purpose counter for benchmarkIng critical
software routines.

• Emulates Z8001/3 or Z8002 CPUs at 6 MHz clock
rates.

Figure 1. EMS 8000 Emulator

965

GENERAL DESCRIPTION
The Emulator System 8000 (EMS), shown in self-test configuration in Figure 1, is a state-of-the-art in-circuit subsystem. The EMS supports the software/hardware
engineer in developing products using the Zilog Z8000
family of microprocessors and peripheral components.
Combined with Zilog's enhanced UNIX System (ZEUS),
EMS 8000 provides the designer with a complete and
powerful set of tools for speeding up the product
development cycle.

The EMS is modular in design with a friendly, screenoriented, self-prompting user interface. High performance is gained with a 1024 entry, real-time trace that is
qualifiable and triggerable, and can be enabled with
multilevel event recognition. Also, newly developed programs can be loaded into the development (target) hardware and executed in a real-time environment. The EMS
can be networked into eight distinct Z8000 microprocessors that start and stop simultaneously.

The EMS links the application software developed on a
host system and the target system, and aids in the integration of the software into the target system by executing in a real-time environment. The EMS uses the full
capability of the target microprocessor and can start or
stop program execution or perform single-step execution. The user has full access to the target microprocessor's registers, memory, and I/O space.

Individual emulator systems can be defined as being
either in or out of a break group. Systems which are outside of a break group can function as independent
emulators with all of the EMS 8000 capabilities and full
use of host resources. Systems which are in the break
group are used to debug multiple processor systems.

SCREENS
The EMS is an interactive operating system that provides
self-prompting commands and a set of powerful tools for
complex debugging. The EMS command entry is organized into a set of pages called screens. Each screen is
dedicated to a particular function and contains the commands and data fields necessary to accomplish specific
functions. The screens are designed to fit on a standard
display terminal, 80 columns wide by 24 lines long.

The user communicates with EMS through five command (menu-driven) screens and two support screens.
The command screens are entered by typing the first letter of the screen name (e.g., A for allocation). Screens
can be changed by sequentially typing  and the
first letter of the screen name. Table 1 explains the
screens and their functions.

Table 1. EMS Screen Descriptions
Screen

Function
Command (Menu· Driven) Screens

Allocation

Assigns EMS resources to specific tasks such as tracing and breakpoints.

Configuration

Allows various hardware controls to configure global features of EMS.

Pattern

Allows entry of recognized patterns.

Mapping

Substitutes EMS mappable memory for target memory.

Debug

Examines and edits memory/registers, 110, displays trace results, begins emulation, sets
software breakpoints, turns watch area on and off, uploads and downloads files to and
from the host computer, single/multiple steps through program execution.

Help

Lists global command controls and helpful reminders not listed in the above menu
screens. It can be displayed on all other screens by typing a .

Change

This is the intermediate step between two command screens and is entered by typing a
.

Support Screens

966

HARDWARE DESCRIPTION
The EMS is a full-featured emulation peripheral. The
heart of the EMS is a Central Controller Unit (CCU) with a
4 MHz Z80, 256K of dynamic memory, and 16K of ROM.
The CCU contains the monitor program that provides a
screen-oriented user interface, and operates continuously to allow the user to monitor the progress of
emulation and breakpoints in real-time. The other EMS
modules include a two-board Trigger module, a real-time
Trace module, an External Probe interface module, a
Mappable Memory module, and a microprocessor Personality module with a CPU Pod (Figure 2).
Figure 3 shows a fully configured EMS system with the
following units:
• EMS 8000
• CPU Pod/cable assembly. The CPU Pod contains the
processor chip to be emulated plus the required interface circuitry. Pods are available for the Z8001/3 and
Z8002.
• 64K mappable memory (standard).
62K mappable memory addition (optional).
• Host computer and user CRT terminal (required).

The EMS uses dual-processor architecture to unburden
the emulating processor from the configuration chores
of the emulation system. (The Z80 CPU is used for EMS
configuration and monitor functions and the Z8000 CPU
for actual emulation.) This independence allows for improved debugging when unreliable target operation
occurs.
A 10 MHz Z8000 CPU is used to emulate the 6 MHz
maximum clock rate of the EMS to compensate for timing delays caused by buffering. The buffering provides
better emulation control in problem targets and allows
mappable memory to override existing target memory.
Fast (90 ns) mapped memory allows emulation at 6 MHz
with no Wait states. (Wait states can be forced if desired
for compatibility with target memory.) Multilevel pattern
recognition resources can be allocated in complex sequential, logical, and enable/disable combinations to the
functions of trace qualifying and triggering, event counting, and timer modes. The counter/timer modes support
a long count of 48 bits (40 when time is displayed in
microseconds). This ensures adequate count capability
for analysis of human-related events in real time.

• External probes (optional).
• Target (the system being emulated).

TARGET SYSTEM
GENERATES CLOCK
(EMULATED PROCESSOR ENVIRONMENT)

TO
TERMINAL
CENTRAL CONTROLLER

SERIAL UNIT
TO HOST
COMPUTER

} COMMUNICATIONS
CHANNELS

INTERRUPT
TO BREAK
GROUP EMS's
DATA/ADDRESS READ·WRITE CONTROL
TRIGGER MODULE

TRACEBOARD sox, K

RESOURCE A
RESOURCE B
RESOURCE C

MAPPABLE
MEMORY BOARDS

63 BLOCKS OF
2K BYTES

GENERAL PURPOSE
COUNTER

TIMING STROBES
SYNCHRONIZED TO EMULATED

Figure 2. EMS 8000 System Block Diagram

967

I

SOFTWARE DESCRIPTION
The EMS can use ZEUS (UNIX) when the System 8000 is
the host computer. This total system provides a complex
hierarchical file structure that includes C, a Z8000
assembler, a compiler writing system, and a general·
purpose microprocessor. Because the EMS interfaces with
Zllog computer systems, the user has access to powerful
development tools for speeding up the product
development cycle. Software downloads to the ZEUS UNIX
operating system.
EMS software is friendly and easy to use. The menu prompt
for each EMS screen reminds the user about the type of data
that is available or the options that are permitted. Error
checking prevents the user from entering illegal states and
allows graceful recovery from emulation target problems
(e.g., bad clock or power failure). Global command keys
allow the user to control the starting and stopping of
emulation, execution of command scripts, and entering
Transparent mode independently of the command screens.
A Help screen, which summarizes global commands and
command entry, is available to help the user gain familiarity
with EMS.

The EMS operating system is downloaded from a host
computer, allowing easy implementation of future upgrades
to improve its effectiveness and applicability. The hosts that
can be configured with the EMS are:
•

Zilog System 8000

•

Vax UNIX

• PDP 11 UNIX
The terminals that can be configured with EMS 8000 are:
•

ADM31

•

CITOH

•

Televideo 920

• VT 100
•

VTZ2/10

TERMINAL
(ADM 31, CITOH,
Televideo 920, VT 100,
VTZ 2110)

HOST

(PDP 11 UNIX. Vax UNIX,
Ztlog System 8000)

EMS 8000

I~'"

Figure 3. EMS 8000 System Configuration

Ordering Information is available at your local Zilog Sales
Office.
Refer to the Literature List for additional documentation,

968

00·2224-01

Z-SCAN 8

Z8® Emulator

Zilog

Product
Description

April 1985

•
•

Provides real-time emulation
capability for the family of Z8
Microcomputers.
Operates with Zilog systems
and other hosts; Z-SCAN 8
uses standard RS-232 links and
is compatible with many standard CRTs and software hosts.
This includes Zilog's S8000
systems, and others with user-

supplied load/save routines and
cross-software support.

•

Hardware/software debugging
is fast and convenient. Two
screens display the status of
the Z-SCAN 8 monitor and Z8
target resources. Target memory can be displayed and modified in a scrollable window.

•

Fulfills the user's essential
real-time debugging needs with
its real-time trace, two complex breakpoints, single-step
capability, and four blocks of
mappable memory.

•

Interactive and easy to use .
Commands are selected from
menus; command arguments
are self-prompting.

OVERVIEW
The Z-SCAN 8 Emulator is a combination of hardware and software
that allows efficient, interactive
emulation of the Z8 Microcomputer. By the simple exchange of
target devices, the selected Z8
MCU can be emulated in a realistic
mode that allows user inspection
and control over the environment

being tested. Real-time trace, two
breakpoints, single-step capability,
and extensive mappable memory
ensure the user a tool that accurately simulates the anticipated
Z8 operating environment.
Z-SCAN 8 is an in-circuit emulator
designed specifically for Zilog's

Z8601 (2K), Z8611 (4K), and
Z8681/82 (ROMless) Microcomputers. Z-SCAN 8 works with
Zilog's family of development
hosts, interfacing via two RS-232
serial ports to the host and a CRT
terminal. A list of compatible CRT
terminals is provided in Table 1.

969

i•

Table 1. Terminals Supported by the
Z·SCAN 8 Monitor
Manufacturer

Table 2. Recommended Sources for Cross·Software

Model

Source

Description

ZlIog
1315 Dell Avenue
Campbell, CA 95008
(408) 370-8000

System 8000*. Cross-assembler for Z8 and
Z8-UPC microcomputers.

Lear Siegler

ADM31

Televideo

TVI912
TVI 920

Zentec

Zephyr

Soroc

10120
10135

Beehive

Bee 100
Bee 107
Micro-B 1

DEC (any)

VT52
VT100
ANSI A3_64 or
ISO DP 6429
compatible

Third Party
Allen Ashley
395 Sierra Madre Villa
Pasadena, CA 91107
(213) 793-5748

Avocet Systems, Inc.
804 South State St.
Dover, DE 19901
(302) 734-0151
Microtec
P.O. Box 60337
Sunnyvale, CA 94088
(408) 733-2919
Relational Memory
Systems, Inc.
P.O. Box 6719
San Jose, CA 95150

General Terminals, 1-200
Inc.
1-400
Hazeltine

1420
1500
Exec 80

Hewlett Packard

2620
2640

IBM

3101

Because it uses a standard serial
interface, Z-SCAN a can also be
used with virtually any software
host system that runs a crossassembler or cross-compiler
capable of generating za code (see
Table 2). This means software can
be developed on many general-

ASMB-Z8*. Cross-assembler; operates with any
standard CP/M-based system.
System-Za'. Cross-assembler; includes ASMBza and text editor, operates with any standard
CP/M-ZaO-based system.
Z8 Cross-assembler (XASMZ8); operates with
CP/M-80, CP/M-86, and MDOS.

ASM Z8. Cross-assembler; operates with any
general-purpose mainframe (DEC, IBM, DG,
etc.) in FORTRAN.
ASM Z8*. Relocatable macro cross-assembler;
operates with Intel Intellec 800 and Series"
microcomputer development systems.

'These Include the upload and download software for communicating.

purpose computers. Only a simple
upload and download utility is
needed for operation since communication between the host
system and Z-SCAN a is through a
standard serial port using Tektronix
hex format. Once software has
been downloaded into the target,

Z-SCAN a can be disconnected
from the host and operated stand
alone. Transparent operation
allows the terminal to be used with
the host in such a way that
Z-SCAN a effectively disappears
from the terminal-to-host link,
without any physical re-cabling.

The Z-SCAN a can be substituted
for a za microprocessor in any of
its configurations or operational
modes and can perform all the
functions of the processor. Additionally, the Z-SCAN a allows the
user to

•

Inspect and display the condition or status of internal
registers and CPU pins for up
to 1,024 machine cycles
preceding the breakpoint.

•

Execute a program or any
number of instructions in Single
step mode.

•

Substitute up to aK bytes of
RAM for external program or
data memory.

FUNCTIONAL
DESCRIPTION
The Z-SCAN a emulator is a compact, portable device that can be
used in a wide variety of functional
configurations and applications. It
has been designed to ease debugging of both hardware and software, to integrate hardware and
software in Za-based systems, and
to provide the user with a powerful
and versatile tool for the development of new systems and new applications for old systems.

970

•

Control any function or operation of the processor and its internal (and in some cases, external) hardware.

Z·SCAN 8

Z8 BOARD

Z8000 BOARD

~

L...:.::J
MONITOR
PROGRAM
(EPROM)

r::l

L.:J

BREAK·

TRACE
MEMORY
1K )(48

TERMINAL

POINT
LOGIC

MAPPABLE
MEMORY
4)(2K
BLOCK
DEBUG
SCREEN

CONFIGURATION
SCREEN

I ..

1'1

4881T8

I

I

I

EMULATOR
CABLE
~

TEST
SYSTEM

ADDRESS ; , ; ;
CONTROL 2
3

Figure 1. Z·SCAN 8 System Block Diagram

User Interface, Z·SCAN 8 Com·
mand Screens
All communication between the
user and Z-SCAN 8 takes place
through the terminal. The format
consists of two selectable screen
menus: the Configuration menu
and the Debug menu. The operator
can manipulate each of these
primary menus to enable variations
for which the user can select a
particular set of conditions, such
as parameters and other variables,
for user control during emulation.
Z-SCAN 8 executes two types of
commands: screen commands and
manipulation commands. The latter
are used to control the display on
the monitor and are normally executed by a control character or an
arrow key. Screen commands are
those used to define and control
the conditions of an emulation.

used for a specific emulation. It is
comprised of five submenus:
•
•

Load

The Debug Screen

•

Save

•

Map

•

Target

Because it controls those conditions most often changed, the
Debug screen is the screen most
frequently entered during a series
of tests or emulations. The Debug
screen is comprised of five
submenus:

These submenus allow the user to
•

Set the host serial-link baud
rate.

•

Watch

•

Connect the user directly to
the host system, in effect, making the Z-SCAN 8 transparent.

•

Memory

•

Break

•

Download programs or data
from a host file.

•

Xecute

•

Allocate mappable memory in
the Z-SCAN 8.

•

Display

•

Inform the Z-SCAN 8 of target
configuration.

The Configuration Screen
The Configuration screen is primarily used to inform the Z-SCAN
8 of certain default values to be

82()()'()Ol

Host

In practice, the Configuration
screen is seldom changed after initial setup until some other type of
test or exercise is contemplated.

The Watch command allows the
user to designate up to twelve
16-byte lines of memory for
display. This display is automat-

971

i•

WE

Os

MDS SYNC

"'-,\ (~

IIIII

-1

HIG~;:;;;;R

6K BYTES

I

4 BITS
4 BITS
(NOT USED)

~

1K

_

~_L_

(I
ADDRESS

....._ _ _......

I CONTROL I PORT
DATA
P~RT
3

Figure 2_ Bit Significance, Trace Memory Word
ically updated to show any change
occurring in the section of memory
specified.
The Memory command is used to
compare two blocks of memory, fill
a block of memory with a hexadecimal string, or move a block of
memory to another range of addresses.
The Break command is used to
define two complex breakpoints,
which operate independently.
The Display command allows the
user to specify what portion or
range of program, data, or register
memory is to be displayed on the
screen.

Trace Memory
The trace memory of the Z-SCAN 8
consists of a 48-bit by 1K block of
RAM that can be used by the
operator to record the condition
and status of certain elements of
the processor's environment for up
to 1,024 machine cycles. The trace
memory can then be displayed and
the display used to analyze an entire series of steps in a routine.
The bit significance of the 48-bit
trace memory word is shown in
Figure 2.

Breakpoints

Mappable Memory

Two complex breakpoints are
available in the Z-SCAN 8. Each
breakpoint can be programmed independently to stop all processor
activity at some arbitrarily selected
point and save the state of the
system in the trace memory for
later analysis. The breakpoints may
specify a stop on address, on data,
or on a status such as an interrupt
acknowledge. Or the breakpoint
may specify that a pulse be
generated and sent to the BNC
connector at the back of the
machine rather than stopping the
emulation.

Mappable memory in the Z-SCAN 8
consists of four 2K bloqks of highspeed static RAM. Each of the
blocks can be assigned independently to replace a section or
block of the target system's
memory. The block can be assigned anywhere in the Z8's
memory space and can be
specified to respond to program or
data memory or both. Mapping
must be done on 2K word boundaries only, and the entire block can
be write-protected. When a break
results from a write-protect violation, an error message appears on
the CRT.

INTERFACE TO NON·
ZILOG HOSTS
Load/save communication between
a Zilog (or other) host system and
the Z-SCAN 8 monitor is accomplished by exchanging
messages containing printable
ASCII characters. Message types
are:
•

972

•

Error text

•

Data block

All messages exchanged during a
Load or Save command are text
lines, each ending in RETURN (carriage return). Memory and other

data are converted into hexadecimal numerals for transmission,
and the resultant message is
readable left-to-right, high-order
digit first, as it is transmitted over
the RS-232 link.

Single-character, data-block
acknowledgment

8200·002

Z·SCAN 8 SPECIFICATIONS
Processor:
4O-pln, 2K and 4K ZS CPU
Emulation Frequency:
up to 12 MHz
1/0:
Two RS-232-C serial ports for terminal and host
CRT Terminal:
Any standard CRT system, including
ZlIog's 88000 systems.
Baud Rate:
Terminal:
9800
Hoet:
Determined by user selection from
300 to 3S,000

Mappable Memory:
SK high-speed, static RAM assignable In 2K blocks
Breakpoints:
Two comples breakpoints; breakable
on data, address, or interrupt
acknowledge
Emulator Cable:
24 Inches
Front Panel:
TARGET RESET and MONITOR RESET switches, POWER ON indicator,
40-pln connector type.
Rear Panel:
BNC connector for pulse output,
standard L.S-TTL level 2 x 25 pin connectors, 3M type 34S3 (terminal and

host), 3-pln power connector,
1'A In., fuseholder (screwdriver release type), POWER ON switch
rocker type), 115/220 voltage selection switch (sliding type)
Power:
180-264 volts ac or SO-130 volts ac,
switch selectable; 47-63 Hz; 2 amp
maximum
Dimensions:
4 inches x 17.5 inches x 14.5 Inches
(HWD); 10.2 centimeters x 44.5 centimeters x 36.S centimeters
Environment:
10·C to 50·C (operating)
Unit Weight:
25 pounds

Ordering Information is available at
your local Zilog Sales Office.
Refer to the Literature List for additional documentation.

OO·2192'()1

973

i•

Z·SCAN80®
Emulator
Product
DescriptioD

Zilog

April 1985

FEATURES
• Real-time emulation for the Z80 microprocessor

• Line assembler

• Two complex breakpoints

• Standard RS-232-C links; compatible With standard
CRTs and software development systems (hosts)

• 4K x 32 bits of real-time trace
• 32 1K-byte blocks of mappable memory
• Disassembly from trace and user memory
• Screen-oriented, user-friendly software

I

• Can be used stand-alone or in combination with virtually
any host computer
• Transparent operation for direct communication between
CRT and host computer

~.

.-------~

i

,"

,

,,

--

OVERVIEW
The Z-SCAN 80 Emulator combines hardware and software
to provide efficient, interactive emulation of the Z80 CPU
Running at up to 8 MHz, the Z-SCAN 80 Emulator closely
matches the Z80H chip in high-speed operations and
efficiency. This screen-oriented development system is
designed to give even a first-time user an easy-to-use
window into the target system.
Based on the Z8001 ™CPU, the emulator interfaces via two
RS-232-C serial ports to the host computer and CRT
terminal. This standard interface allows the Z-SCAN 80
Emulator to be used with virtually any software development
host system that runs a cross-assembler or crosscompiler
capable of generating Z80 code. Such hosts include the
VAX' and Zilog's System 8000™ (running the UNIX"
operating system). Only a simple upload and download
utility is needed for operation, since communication
between the Z-SCAN 80 Emulator and the host is through a

standard serial port using Tektronix or Intel hex format. A list
of terminals compatible with the Z-SCAN 80 FmlJlAtor is
shown in Table 1.
Table 1. Terminals Supported by the Z-SCAN 80 Emulator
Manufacturer

Model

Lear Siegler
Televldeo
Hewlett Packard
Digital Equipment
Qume
Zentec

ADM31
920
2621
VT100
102
1051

975

- - - - - - - - - -- --

The Z-SCAN 80 Emulator is a versatile development system,
able to perform in a number of scenarios. With Zilog's
System 8000 or another host, the Z-SCAN 80 Emulator
becomes a complete hardware and software station for
developing high-level applications programs. In stand-alone
mode, the Z-SCAN 80 Emulator is useful in manufacturing
environments for simple testing and debugging of
PROM-based target systems. Figure 1 shows the Z-SCAN
80 Emulator both as a stand-alone system and with a host.

and target. Once software has been downloaded into the
target, the emulator can be disconnected from the host and
operated stand-alone. With the use of mappable memory,
the designer can develop programs without a target system.
Software for the Z-SCAN 80 Emulator is user-friendly and
screen-oriented; a first-time user can easily learn the
Z-SCAN 80 Emulator in a few hours by working with the
terminal display. The user can manipulate the screen to
display any combination of target resources, for configuring
mappable memory and for debugging and program
development tasks. Memory and registers can be changed
via the terminal screen. Real-time trace, two sophisticated
hardware breakpoints, single-step capability, and a large
mappable memory complete the toolbox necessary to
construct the Z80 operating environment.

One accomplishment of the Z-SCAN 80 Emulator is
transparent operation, which allows the terminal to be used
with a host in such a way that the Z-SCAN 80 Emulator
effectively disappears from the terminal-host link, without
physical recabling. The designer can focus entirely on
applications program development, while the Z-SCAN 80
Emulator takes care of communications between CRT, host,
HOST DEVELOPMENT SYSTEM
WITH HARDWARE EMULATION

HOST
COMPUTER

STAND-ALONE
DEVELOPMENT SYSTEM

Z-5CAN80
EMULATOR

D

=

Figure 1. Z-SCAN 80 Emulator Environment

976

2325-001

HARDWARE DESCRIPTION
The Z-SCAN 80 Emulator is made up of two boards of
hardware and firmware components that provide emulation
of the Z80 CPU and monitoring of the development process.
A Z80H chip, running at up to 8 MHz, is contained in a pod
located near the target on the emulator cable. This
arrangement shortens the time delay that would result if the
Z80H device were located inside the Z-SCAN 80 Emulator,
and ensures real-time emulation of the Z80 CPU.
Figure 2 shows a block diagram of the Z-SCAN 80 Emulator
system.

Mappable Memory
Thirty-two 1 K-byte blocks of high-speed static RAM allow
the Z-SCAN 80 Emulator to emulate a portion of the target
memory space. Any block can be mapped on any 1K-byte
boundary of the physical address space; each block can be
individually protected against writes during target
execution.

Mappable memory can be configured as a surrogate for
target memory, or as an addition to existing memory in the
target system.

lRIce Memory
A 4K x 32-bit block of RAM is provided to trace address,
data, and control signals. Up to 4096 trace cycles can be
handled by the trace facility.

Hardware Breakpoints
Two sophisticated breakpoints are provided, each with a
pass count of 1 to 255, for detection of address, data, and
control signal states. The breakpoints allow for a break in
program execution on any combination of program
conditions.

Z·SCAN 80 IIMULATOR

MONITOR BOARD

MONITOR
PROGRAM
(EPROM)

EMULATOR BOARD

r::l

L:J

TRACE
MEMORY
4K x 32

BITS

MAPPABLE
MEMORY
321K·8YTE
BLOCKS

BREAK·
POINT
LOGIC

Z·SCAN

SCREENS

Figure 2. Z-SCAN 80 Emulator System Block Diagram

SOFTWARE DESCRIPTION
Host·resident software for the Z-SCAN 80 Emulator consists
of load and send routines for upload and download
between the host computer and the Z-SCAN 80 Emulator,
and the corresponding Z-SCAN firmware routines.
The load and send modules perform upload and download
using Tektronix (Tek) hex or Intel hex. Print and Do
commands use ASCII format. Table 2 shows upload and
download protocols for the various operating systems.
The monitor software provides an interface between the
emulator hardware, the host load and send programs, and

2325-002

the user. Most of the software is dedicated to the user
interface, i.e., the screens and commands.
Table 2. Upload/Download Protocols
Host Operating System

Protocol

VAX, UNIX III
S8000, ZEUS
CP/M
Intel MOS, Intellec

TekHex
TekHex
Intel or Tek Hex
Intel Hex

977

The main functions of the Z-SCAN 80 Emulator software are
as follows:

• Allows Z-SCAN terminal to be used as host terminal
(transparent mode)

• Accepts commands to initiate upload and download
between host and target

• Selects host baud rate

• Displays and edits target registers, ports, and memory
• Starts, single-steps and halts target system execution
• Substitutes Z-SCAN mappable memory for target
memory

• Block memory moves, compares, and fills on target
memory
• Tailors screen configuration to desired display (e.g.
simultaneous display of specific registers and ports)
• Self-tests hardware

• Displays trace memory

Z-SCAN SCREENS
The Z-SCAN screens give the user access to a constant flow
of debugging and program development information. A
Z-SCAN screen consists of a command window, up to five
roll windows, and a scroll window.

Scroll windows consist of the following displays:

Command Window

• Traced target cycles

The Z-SCAN command window (the first three lines), IS
manipulated by the user with a set of commands and
subcommands to perform debugging tasks. It is used for
the following functions:

• Help descriptions

• Menu-displays menu of commands
• Command history-displays the last two commands
executed
• Status-displays status information on target emulation
and the last Load and Save commands
• Subcommand Input (interactive editor commands)displays subcommands
Table 3 summarizes the Z-SCAN 80 Emulator commands.

Roll and Scroll Windows
Below the command window, the rest of the screen is
divided between roll windows and a scroll window. A roll
window is used for displaying parameter values (registers,
breakpoints, etc.) and their labels both Immediately before
and after the most recent emulation. A scroll window
displays a continuous listing of values and addresses
specified by the user, for example, target memory
disassembly.
The Edit command initiates interactive editing of either a roll
or scroll window; the Watch and Unwatch commands
determine which roll or scroll windows appear onscreen.
Roll windows consist ofthe following parameters and labels:
• Target CPU registers
• Watched target memory

• Target memory
• Disassembled target memory

Table 3. Z-SCAN 80 Emulator Commands
Command

Action

Abort

Re-initialize host link
Assemble instruction and store in memory
Set breakpoint
Compare hex string against a block of target
memory
Compare two blocks of target memory
Interpret commands from host file
Enter window for interactive editing
Write hex string Into block of target memory
Start target execution
Stop target execution
Load block of target memory from host file
Set memory map
Set memory values
Move a block of target memory
Conditionally wait for keyboard character to
continue Interpreting commands from
hostflle
Send screen image to host file
Read target I/O port
Set register values
Reset target system
Store block of target memory in host file
Execute a certain number of instructions
Test emulator hardware
Unasslgn window and enlarge adjacent
display
Assign and display Window
Write target I/O port

Asm

Break
Check
Compare
Do
Edit
Fill
Go

Halt
Load
Map
Mem
Move
Pause

Print
Read
Reg
Reset
Save
Step
Test
Unwatch

• Complex breakpoints
• Mappable memory
• Host protocol options

978

Watch
Write

Z-SCAN SELF-TEST
The Z-SCAN SO Emulator monitor software performs an
automatic self-test on power-up and reset. It also performs
confidence and diagnostic tests by user command. The
automatic self-test operates without disturbing the contents
of the target memory or registers. The Z-SCAN SO Emulator
displays the results of the test via the terminal.

Systematic confidence tests of the emulator hardware can
be instituted by the user with the Test command. These tests
allows the user to distinguish target errors from Z-SCAN
errors. Diagnostic tests can also be run using command
SCripts downloaded from the host file.

Z-SCAN 80 SPECIFICATIONS
PROCESSOR EMULATED:
ZSO,ZSOA,ZSOB,ZSOH

EMULATION FREQUENCY:

One cable from emulator to pod, 4S", 50-pin (part number
59-0279-00)
One cable from pod to target, approximately S" (part
number 59-0277-00)

Upto S MHz

FRONT PANEL:

I/O:

Power-on indicator and reset switch
40-pin and 50-pin connectors

Two RS-232-C serial ports, one each for terminal and host

REAR PANEL:
CRT TERMINAL:
Standard terminals listed in Table 1 are supported

BAUD RATE:
Terminal: 9600 bits/second
Host: Determined by user selection from 110 to 19,200
bits/second

TRACE MEMORY:
4K x 32 bits

MAPPABLE MEMORY:
32K high-speed static RAM assignable in 1 K-byte blocks
with individual write protect

Power-on switch
BNC connectors for Break pulse output and input
Two 25-pin 0 subminiature connectors
A 3-pin power connector
A 1 1/4" fuseholder (screwdriver-release type)

POWER:
1S7-264 volts ac at 3 amps maximum-50 Hz version
105-130 volts ac at 3 amps maximum-60 Hz version

DIMENSIONS:
4" X 17.5" X 14.5" (HWO)
10.2 cm x 44.5 cm x 36.S cm

ENVIRONMENT:

HARDWARE BREAKPOINTS:

oto 40 degrees Centigrade

2 complex breakpoints (breakable on address, data, and
status)

UNIT WEIGHT:
25 pounds

EMULATOR CABLES:
One cable from emulator to pod, 4S", 40-pin (part number
59-027S-00)

ORDERING INFORMATION
DESCRIPTION:
Z-SCAN SO Emulator, 115V (part number 05-6223-00)
Z-SCAN SO Emulator, 230V (part number 05-6223-01)
Ordering Information is available at your local Zilog Sales
Office.
Refer to the Literature List for additional documentation.

00-2325-01

979

Z-SCAN 8000®
Emulator

Zilog

Product
Description

April 1985
• Provides Real Time Emulation up
to 4 MHz 01 the Z8001 and Z8002
CPUs.
• Two RS-232C Serial Ports Make It
a Peripheral Usable with Most
Standard CRTs and Soltware
Hosts.

• Transparent Operation Permits
Direct Communication Between
CRT and Host without Physical
Disconnect.
• Highly Interactive. ScreenOriented User Interlace Makes
Z-SCAN Easy To Use.

• Shadow Monitor Removes All
Restrictions on Target System
Memory Space, Making It Fully
Available To the User.
• High-Speed Mappable Memory
(no walt states) Is Available to
Simulate Target System
RAM/ROM.

OVERVIEW
The Z-SCAN 8000 Emulator is an incircuit emulator that has been designed
as a peripheral unit for Zilog's 28001
and Z8002 16-bit microprocessors.
InterfaCing via two RS-232C Serial
ports to host and CRT terminal,
Z-SCAN 8000 can work with Zilog's
family of development hosts.
Because it employs a standard serial
interface, Z-SCAN 8000 can also be
used with Virtually any software host
system that runs a cross assembler or
cross compiler capable of generatmg
Z8000 code. Communication between
the host system and Z-SCAN 8000 IS
WIth a standard serial format reqUIring

only a simple upload and download
utility to operate. For PROM-based
target systems, Z-SCAN can operate
stand-alone with a CRT termmal
because the monitor and debug software is EPROM-resident.
In keepmg WIth Zilog's design
philosophy of separating a development system into two identifiable units
(the software host and an emulation
penpheral), Z-SCAN 8000 hts into
three scenariOS, making it a highly versatile unit:
• As a peripheral to Zllog's PDS 8000,
ZDS-I, or System 8000, Z-SCAN
8000 completes the development

support package for the 2800 1 and
Z8002 microprocessors available
from Zllog.
• As a peripheral to any development
host with the capability of compiling
or assembling 28000 code, Z-SCAN
8000 allows a low-cost emulation
capability which precludes substantial reinvestment in a software host
system.
• As a stand-alone m-circult emulator
that can operate with most CRT
terminals, Z-SCAN 8000 provides
simple testing and debuggmg
capability for PROM-based target
systems.

981

SYSTEM FEATURES
User Interface. Z-SCAN 8000 mcor-

porates the use of a two-dimensional
screen-oriented user interface which
makes it easy to use. Because it is
general-purpose in nature, the user
interface does not require a customized
CRT terminal to operate. The only
requirements are that the CRT terminal
have screen erase, line erase, and cursor addressing capability.
The objective of the user interface is
to provide a screen format with a
menu-like approach, which directs the
user through the operation of the emulator. The user is aware at all times of
where he/she is in the debug process
because Z-SCAN 8000 provides the
CRT information about system para-

ADDRESS/DATA

SEGMENT

BUS

BUS

COMPARE
VALUE

SEGMENT
COMPARATORS

STATUS
BUS

COMPARE

VALUE

STATUS
COMPARATORS

DON'T

DON'T

DON'T

CARE

CARE

CARE

INSTRUCTION
FETCH
DETECT

meters, system resources, current

execution, and error messages. When
the system is turned on, a bootstrap
routine produces a display informing
the user of the unit's configuration and
requesting the user to define set-up
parameters. A menu of display chOlces
shows the user the different capabilities
of the system:
• The Memory/I/O command display
shows the various memory and I/O
manipulation commands which
access the target system.
• The Resources display presents the
user with the full complement of
arguments applicable to emulation
of the target system.
• The Execution display shows all the
commands and parameters necessary to cause emulation to take
place.
At all times, execution of specific
Monitor commands IS pOSSible, and
information on other relevant system
parameters and resources is always displayed. This highly interactive user
interface makes it possible to use
Z-SCAN 8000 without frequent
reference to the operating manual.
Shadow Memory. Z-SCAN 8000 IS a

single, CPU-based system that can be
configured to emulate either the Z8001
or Z8002 by moving jumpers to select the
alternate screen monitor, and by changing the emulator cable.
Although the system uses a single
CPU for both monitor and emulahon
functions, no restrictions are placed on
the target system memory size. ThiS IS
because the entire monitor resides in
shadow memory and, therefore, does
not appear in the target system memory
space. This feature also prOVides the
benefit of making future system expansion possible without any hardware
redesign.

982

Figure I. Hardware Trigger Implementation

Hardware Trigger. Z-SCAN 8000

offers the capability of settmg breakpoints in three different fields or in a
combination of these fields. These are
the Address/Data Field, the Segment
Field, and the Control/Status Field. A
Pass Counter can be set up to a maximum of 255 counts to allow multiple
pass triggermg. In addition, Z-SCAN
8000 may also be set to break on
instruction fetches only (single-step
execution), or, by usmg a Pass
Counter, may be set up to a maximum
of 247 counts to allow triggering on
mulhple instruchon fetches (multi-step
execution).
With these two capabilities, a breakpomt argument can be set up which IS
on ORed condition allowing for either
a break-on-field (or combmation of
helds) argument or for "n" mstruction
fetches, whIChever occurs hrst. This
ORed situation is convenient when
traCing through a program in search of
a specific occurrence. A pulse output,
provldmg a trigger pulse on breakpoint match condition IS available on
the rear panel to trigger auxiliary test
instrumentation.
Mappable Memory. Z-SCAN 8000

offers a 4K work block of high-speed
stahc RAM. ThiS block is available to
the user to simulate a target system

memory block which would typically
be ROM. No Wait states are required
at 4 MHz. This block is mappable
anywhere in the Z8001 and Z8002
address space and can be speCified to
be Normal Code, Normal Data, Normal
Stack, System Code, System Data,
System Stack, or Space Independent.
Mapping must be done on 4K word
boundaries only, and the entire block
can be write protected against illegal
writes to cause system emulation either
to break on such occurrences or continue emulation. An error message
appears on the CRT display informing
the user of an illegal write.
Software Trace. Z-SCAN 8000 offers a
software trace feature which provides
insight into target system activity and
CPU resources. In the Trace Mode, the
system displays the address of the
instruction being executed and the
contents of the CPU registers (both
general-purpose and control) consecutively, covering one full screen
format.
For example, displaying the CPU
registers associated with every instruction executed just prior to executing a
Break is tremendously useful to the
user during debug of target system
achvity.

1041-001

SPECIFICATIONS

CPU
ZSOO I or ZS002 per conhgurahon
Clock Rate
500 kHz-4.0 MHz (external)

110
Two RS-232C Senal Ports for CRT and
host
Baud Rate
Automatically selected from 50 to 19.2K
Breakpoint
Address, Data, Segment and Address,
Control, Address and Control, Data and
Control, Segment and Address and
Control, Instruction Fetch, OR combinahon of Instruction Fetch and any Field

Mappable Memory
4096 x 16 Stahc RAM (no Wait states at
4 MHz wh1le operating off User clock)

Front Panel
Target/Momtor, Reset, and NMI toggle
SWitches

Inputs
One standard LS-TTL load plus 30 pF

Power

110/220 Vac, 50160 Hz SWitch selectable,
60 VA maXimum

maxImum

Outputs
Capable of dnvmg one standard LS-TTL
load plus 30 pF preload

Dimenslons
4 m. (10.2 em) (H) x 14V2 m. (36.8 em)
(W) x 18 m. (45.7 cm) (D)

Rear Pemel Output
BNC connector for pulse output, standard
LS-TTL

Emulator Cable
12 mches

argument

.,.

AC CHARACTERISTICS

Number
Symbol

ZSOD1I2
Parameter

Min (us)

Max (us)

Z-SCAN
Min (us)

250
1 TcC
Clock Cycle Time
2000
250
2 TwCh
Clock Width (High)
105
2000
105
3 TwCl
Clock Width (Low)
105
2000
105
4 TfC
Clock Fall Time
20
5- TrC
Clock Rise T i m e - - - - - - - - - - - - - - - - - - - 20
6 TdC(SNv)
Clock I to Segment Number Valid (50 pF load)
130
7 TdC(SNn)
Clock I to Segment Number Not Valid
20
35
65
Clock I to Bus Float
8 TdC(Bz)
100
9 TdC(A)
Clock I to Address Valid
10- TdC(Az)---Clock I to Address Float - - - - - - - - - - - - - - - 65
455
11 TdA(DI)
Address Valid to Data In Required Valid
383
12 TsDI(C)
Data In to Clock I Setup Time
50
76
13 TdDS(A)
DS I to Address Active
80
-4
14 TdC(DO)
Clock I to Data Out Valid
100
15- ThDI(DS)-- Data In to DS I Hold T i m e - - - - - - - - - - 0
-20
16 TdDO(DS)
Data Out Valid to DS I Delay
295
269
17 TdA(MR)
Address Valid to MREQ I Delay
55
29
18 TdC(MR)
Clock I to MREQ I Delay
80
19a TwMRh
MREQ Width (High)
210
193
19b-TwMRh--- MREQ Width (High) During Monitor O p e r a t i o n - - - - - - - - - - - - 184
20 TdMR(A)
MREQ I to Address Not Active
70
53
21 TdDO(DSW)
Data Out Valid to DS I (Write) Delay
55
59
22 TdMR(DI)
MREQ I to Data In Required Valid
350
287
23 TdC(MR)
Clock I MREQ I Delay
80
24-TdC(AS£)--Clock I to AS I Delay - - - - - - - - - - - - - - - 80
25 TdA(AS)
Address Valid to AS I Delay
55
29
Clock I to AS I Delay
26 TdC(ASr)
90
27 TdAS(DI)
AS I to Data In Required Valid
340
277
28 TdDS(kS)
DS I to AS I Delay
70
53
29-TwAS
AS Width ( L o w ) - - - - - - - - - - - - 70
53
30 TdAS(A)
AS I to Address Not Active Delay
60
43
31 TdAz(DSR)
Address Float to DS (Read) I Delay
0
-41

Max (us)

2000
2000
2000
20
20175
165
163
154-

163

143

134
134144

4

983

B

i

AC CHAHACTERlSnCS

Z8001I2

Number
Symbol

Parameter

Min (na)

Max (na)

Z·SCAN
Min (na)

Max (na)

32 TdAS(DSR)
AS t to DS (Read) I Delay
70
53
33 TdDSR(DI)
DS (Read) I to Data In Required Valid
185
122
34 TdC(DSr)
Clock I to DS t Delay
70
65
35 TdDS(DO)
DS t to Data Out and STATUS Not Valid
75
58
36-TdA(DSR) - - Address Valid to DS (Read) I Delay
180 - - - - - - - 1 5 4 - - - - - 37 TdC(DSR)
Clock t to DS (Read) I Delay
174
120
38 TwDSR
DS (Read) Width (Low)
275
258
39 TdC(DSW)
Clock I to DS (Write) I Delay
149
95
40 TwDSW
DS (Write) Width (Low)
185
168
41-TdDSI(DI)-- DS (Input) I to Data In Required Valid
320 - - - - - - - 2 6 6 - - - - - 42 TdC(DSf)
Clock I to DS (110) I D~lay
174
120
43 TwDS
DS (1/0) Width (Low)
410
393
44 TdAS(DSA)
AS t to DS (Acknowledge) I Delay
1065
1048
45 TdC(DSA)
Clock I to DS (Acknowledge) I Delay
120
174
46-TdDSA(DI)--DS (Acknowledge) I to Data In Required Delay---435 - - - - - - - 3 8 1 - - - - - 47 TdC(S)
Clock t to Status Valid Delay
110
162
48 TdS(AS)
Status Valid to AS t Delay
60
45
49 TsR(C)
RESET to Clock t Setup Time
180
208
50 ThR(C)
RESET to Clock t Hold Time
0
15
51-TwNMI--- NMI Width (Low)
100
116 - - - - - 52 TsNMI(C)
NMI to Clock I Setup Time
140
154
53 TsVI(C)
VI, NVI to Clock t Setup Time
110
118
54 ThV1(C)
VI, NVI to Clock t Hold Time
0
22
55 TsSGT(C)
SEGT to Clock t Setup Time
70
78
56-ThSGT(C)-- SEGT to Clock I Hold Time
0
22 - - - - - 57 TsMI(C)
MI to Clock t Setup Time
180
188
58 ThM1(C)
MI to Clock t Hold Time
0
22
165
59 TdC(MO)
Clock t to MO Delay
120
60 TsSTP(C)
STOP to Clock I Setup Time
140
148
61-ThSTP(C)--STOP to Clock I Hold Time
0
22 - - - - - 62 TsWT(C)
WAIT to Clock I Setup Time
50
78
63 ThWT(C)
WAIT to Clock I Hold Time
10
25
64 TsBRQ(C)
BUSREQ to Clock I Setup TimE>
90
98
65 ThBRQ(C)
BUSREQ to Clock t Hold Time
10
32
66-TdC(BAKr)--Clock t to BUSACK t D e l a y - - - - - - - - - - - - - 1 0 0 - - - - - - - 1 4 5 - 67 TdC(BAKf)
Clock I to BUSACK I Delay
100
145
Ordermg Information is available at
your local Zilog Sales Office.
Refer to the Literature List for addlbonal documentabon.

984

00-1041.()3

SystemSOOO
Series Two: Model 12

Zilog

Product
Brief

March 1985

f

FEATURES
• UNIX operating system with enhancements, including the full
screen vi editor, record locking,
andC-ISAM.

I

r...

• 11.1 MHz CPU with 32 KB cache
memory.
• Up to twice the operating speed of
original System 8000 family
members.

N

• Software compatibility with complete System 8000 family.
• Up to sixteen users.
• Up to two integral 52 MB disks.
• Up to 2 MB of memory.
• Integral 21.3 MB cartridge tape
drive for disk backup.
• Optional Intelligent Communications Processor which supports
popular protocols.
• Support of multiple industrystandard languages.

OVERVIEW
The System 8000 Series Two Model
12 is a high performance, mUlti-user,
UNIX supermicro computer system
designed for today's demanding
business applications. Up to sixteen
users-from novices to sophisticated
programmers-can work on the same
system with each user simultaneously
performing a different task. Sharing
files and transmitting messages is
easy.

Model 12 IS one of the fastest and
most efficient members of Zilog's
System 8000 family, which has enjoyed years of trouble-free operation
by thousands of satisfied users. Programs developed on any System
8000 model can be transferred to,
and executed by, Model 12 and all
the other models. An extensive selection of excellent software tools, service, and support programs
accompanies the System 8000 family
of products.

Configurations

The UNIX operating system, with
Zilog and UC Bork01cy enhancements
including the full screen vi editor,
record locking, and C-ISAM from
Relational Database Systems, Inc., is
standard on all System 8000 supermicros.
Memory configurations (RAM) from
512 KB to 2 MB are available.

985

A sealed, 5 1/4-inch high-performance
Winchester hard disk provides economical and highly reliable on-line
data storage. This disk has an exceptionally fast 30msec access time and
offers 52 MB of total storage space. A
second disk can be added, making
available 104 MB of storage.
A cartridge tape drive, which stores
up to 21.3 MB, is used for disk
backup. These cartridges provide
virtually unlimited offline storage of
data.
Up to eighteen serial ports and two
parallel ports are available. These
ports are used to connect the system
with input/output devices such
as CRT terminals, printers, and communication modems. Up to sixteen
users are supported by the system.
Communications protocols such as
IBM 2780/3780 bisync and X.25 can
be implemented with the optional
Intelligent Communications Processor
(ICP 8/02) board.

System Architecture

Model 12 uses field-proven, state-ofthe-art VLSI components. Foremost
among them are Zilog's 11.1 MHz
Z8001 16-bit High-Performance CPU
(HPCPU) board, with 32 KB cache
memory, and three high-performance
Z8010 Memory Management Units.
These high-performance components
are specially selected for their superior
speed.
Intelligent controllers, for the Winchester disk and the cartridge tape, free
the operating system from lOW-level
device handling functions. The Winchester disk controller contains a
dedicated Z8001 CPU with 16K bytes
of local memory which substantially
increases system performance.
The optionallCP 8/02 Intelligent Communications Processor contains a
Z8002 CPU with 128K bytes of dualported memory and DMA-supported

I/O ports that allow communication
over both asynchronous and synchronous lines, such as IBM 2780-3780
bisync and X.25 packet-switched
networks.
Comprehensive Software

The UNIX operating system provides
an excellent environment for business
applications.
The System 8000 comes with an
impressive collection of more than
300 utility programs and development
tools that make it easy for both end
users and OEMs to develop new
applications quickly.
High level programming languages
for scientific and industrial applications are offered, including Pascal, C,
and Ada.

SPECIFICATIONS
CPU

Cartridge Tape Drive

Physical

- High-performance 16-bitZ8001
CPU, 11.1 MHz, with 32 KB cache
memory

-

-

Memory

- Minimum: 512 KB
- Maximum: 2 MB
- Management: Three Highperformance Z801 0 MMUs
- Error Handling: Parity or Error
Checking and Correcting (ECG)
52 MB Winchester Disk

-

Disk Size: 5 1/4 inches
Rotation Speed: 3,600 rpm
Average Seek Time: 30 msec
Data Transfer Rate: 5 Mbits/sec

986

ReadlWrite Speed: 30 ips
Rewind/Search Speed: 90 ips
Tracks: 4
Recording Density: 6400 BPI
Capacity (unformatted): Up to
21.3 MB

Height: 66 cm (26 in.)
Width: 20 cm (8 in.)
Depth: 46 cm (18 in.)
Weight: 43 kg (95 pounds),
approximately

Electrical
Options

- Up to 16 users
- Up to 18 serial ports,
2 parallel ports
- Upt02 MB memory
- Second Winchester drive
- ICP 8/02 Intelligent Communications Processor
- Two slots available for board
options

- Phase: Single
- Frequency: 47 to 63 Hz
Nominal
Selectable
Voltages ± 10%

Maximum
Sustained
Current

100-115 VAC/50 Hz 250A
220-240 VAC/50 Hz 125A

Maximum
Current
Surge
4.0A
2.0A

Environmental

- Operating Temperature:
10°C (50°F) minimum,
40°C (104°F) maximum
- Relative Humidity:
20 to 80% (Noncondensing)

00·1241-01

System 8000
Series Two: Nodel 22
Product
Briel

Zilog

April 19B5

FEATURES

f

• UNIX operating system with enhancements, including the full
screen vi editor, record locking
andC-ISAM

I

• 11.1 MHz CPU with 32 KB cache
memory.

I

• Twice the operating speed and
efficiency of original System BODO
family members.

N
N

• Media and software compatibility
with complete System BODO family.
• Up to forty users.
• Up to four integral 52 MB disks.
• Up to 4 MB of memory.
• Integral 21.3 MB cartridge tape
drive for disk backup.
• Optional industry-standard 9-track
tape drive.
• Optional Intelligent Communications Processor which supports
popular protocols.
• Optional IEEE 754 hardware Floating Point Processor which executes double-precision, extended
multiplications in 3.2B j.lsec.
• Support of multiple industrystandard languages.

OVERVIEW
The System BODO Series Two Model
22 is a high-performance, mUlti-user,
UNIX supermicro computer system
designed for today's demanding
business applications. Up to forty
users-from novices to sophisticated
programmers-can work on the same
system with each user simultaneously
performing a different task. Sharing
files and transmitting messages is
easy.

Model 22 is one of the fastest and
most officient members of Zilog's
System BODO family, which has enjoyed years of trouble-free operation
by thousands of satisfied users. Programs developed on any System
BODO model can be transferred to,
and executed by, Model 22 and all
the other models. An extensive selection of excellent software tools, service, and support programs
accompanies the System BODO family
of products.

9B7

Configurations
The UNIX operating system, with
Zilog and UC Berkeley enhancements
including the full screen vi editor,
record locking, and C-ISAM from
Relational Database Systems, Inc., is
standard on all System 8000 supermicros.
Memory configurations (RAM) from
512 KBt04 MB are available.

ports are used to connect the system
with input/output deVices such as
CRT terminals, printers, and communication modems. Up to forty users are
supported by the system. Communications protocols such as IBM 2780/
3780 bisync and X.25 can be
implemented with the optionallntelligent Communications Processor (ICP
8/02) board.

System Architecture

A sealed, 51/4-inch high-performance
Winchester hard disk provides economical and highly reliable on-line
data storage. This disk has an exceptionally fast 30m sec access time and
offers 52 MB of total storage space.
Up to three additional 52 MB disks
may be added at low cost. Model 22
is designed to contain and support
four of these disks for a storage
capacity of 208 MB.

Model 22 uses field-proven, state-ofthe-art VLSI components. Foremost
among them are Zilog's 11.1 MHz
Z8001 16-bit High-Performance CPU
(HPCPU) board, with 32 KB cache
memory, and three high-performance
Z8010 Memory Management Units.
These high-performance components
are specially selected for their superior
speed.

A cartridge tape drive, which stores
up to 21.3 MB, is used for disk
backup. The basic Model 22 comes
with one cartridge tape drive and can
be configured for a second, optional
unit. An industry-standard, half-inch
9-track tape drive is optional.

Intelligent controllers, for the Winchester disk and the cartridge tape, free
the operating system from low-level
device handling functions. The Winchester disk controller contains a
dedicated Z8001 CPU with 16K bytes
of local memory which substantially
increases system performance.

Up to forty-two serial ports and five
parallel ports are available. These

SPECIFICATIONS
CPU
- High-performance 16-bit Z8001 ,
CPU 11.1 MHz, with 32 KB cache
memory

Memory
- Minimum: 512 KB
- Maximum: 4 MB
- Management: Three Highperformance Z801 OA MMUs
- Error Handling: Parity or Error
Checking and Correcting (ECC)

52 MB Winchester Disk
-

Disk Size: 51/4 inches
Rotation Speed: 3,600 rpm
Average Seek Time: 30 msec
Data Transfer Rate: 5 Mbits/sec

Cartridge Tape Drive
- Read/Write Speed: 30 ips
- Rewind/Search Speed: 90 ips
988

- Tracks: 4
- Recording Density: 6400 BPI
- Capacity (unformatted):
Upt021.3 MB

Options
- Upt040users
- Up to 42 serial ports,
5 parallel ports
- Up to 4 MB memory
- Up to four Winchester drives
- ICP 8/02 Intelligent
Communications Processor
- FPP 8/01 Floating Point Processor
- Five slots available
for board options
- Industry standard 9 track tape
(1600 bpi)

Physical
-

Height: 84 cm (33 in.)
Width: 48 cm (19 in.)
Depth: 61 cm (24 in.)
Weight: 114 kg (250 pounds),
approximately

The optional FPP 8/01 Floating Point
Processor is a high-speed, bit-slice
technology implementation of the
IEEE Standard P754 Draft 10. Doubleprecision extended multiplication, for
example, executes in only 3.8 "sec.
The optionallCP 8/02 Intelligent Communications Processor contains a
Z8002 CPU with 128K bytes of dualported memory and DMA-supported
I/O ports that allow communication
over both asynchronous and synchronous lines, such as IBM 2780/3780
bisync and X.25 packet-switched
networks.

Comprehensive Software
The UNIX operating system provides
an excellent environment for business
applications.
The System 8000 comes with an
impressive collection of more than
300 utility programs and development
tools that make it easy for end users
and OEMs to quickly develop new
applications.
High level programming languages
for scientific and industrial applications are offered, including Pascal, C,
and Ada.

Electrical
- Phase: Single
- Frequency: 47 to 63 Hz
Nominal
Selectable
Voltages ± 10%

Maximum
Sustained
Current

100·115 VAC/60 Hz 7.5A
220·240 VAC/50 Hz 4.0A

Maximum
Current
Surge
20A
10A

Environmental
- Operating Temperature:
10°C (50°F) minimum,
40°C (104 oF) maximum
- Relative Humidity:
20 to 80% (Noncondensing)

ORDERING INFORMATION
Ordering Information is available at
your local Zilog Sales Office.
Refer to the Literature List for additional documentation.

OO·1238'()1

System 8000
Series Two: Model 32
Product

Zilog

Brief

.t

March 1985

FEATURES

i

• UNIX operating system with enhancements, including the full
screen vi editor, record locking,
andC-ISAM.

I

• 11.1 MHzCPU with 32 KB cache
memory.

I

• Twice the operating speed and
efficiency of original System 8000
family members.

=

• Media and software compatibility
with complete System 8000 family.
• Up to forty users.
• Up to four integral high performance 168 MB disks.
• Up to 4 MB of memory.
• Integral 21.3 MB cartridge tape
drive for disk backup.
• Optional industry-standard 9-track
tape drive.
• Optional Intelligent Communications Processor which supports
popular protocols.
• Optional IEEE 754 hardware Floating Point Processor which executes double-precision, extended
multiplications in 3.28Ilsec.
• Support of multiple industrystandard languages.

OVERVIEW
The System 8000 Series Two Model
32 is a high performance, multi-user,
UNIX supermicro computer system
designed for today's demanding
business applications. Up to forty
users-from novices to sophisticated
programmers-can work on the same
system with each user performing a
different task simultaneously. Sharing
files and transmitting messages is
easy.

Model 32 is the fastest and most efficient members of Zilog's System 8000
family, which has enjoyed years of
trouble-free operation by thousands
of satisfied users. Programs developed on any System 8000 model can
be transferred to, and executed by,
Model 32 and all the other models.
An extensive selection of excellent
software tools, service, and support
programs accompanies the System
8000 family of products.

989

Configurations
The UNIX operating system, with
Zilog and UC Berkeley enhancements
including the full screen vi editor,
record locking, and C-ISAM from
Relational Database Systems, Inc., is
standard on all System 8000 supermicros.
Memory configurations (RAM) from
512 KB to 4 MB are available.
A sealed, 8-inch, 168 MB Winchester
hard disk with Storage Module Disk
(SMD) controller is standard on the
Model 32. The SMD hard disks, with
their 20msec access time, provide the
best performance in the System 8000
family. Their field reliability record is
superb. Up to three additional 168
MB disks may be added at low cost.
The Model 32 is designed to contain
and support four of these disks for a
total of 672 MB of storage.
A cartridge tape drive, which stores
up to 21.3 MB, is used for disk
backup. The basic Model 32 comes
with one cartridge tape drive, and can
be configured for a second, optional
unit. An industry standard half-inch 9track tape drive is optional.
Up to forty-two serial ports and five
parallel ports are available. These

SPECIFICATIONS
CPU
- High-performance 16-bit Z8001
CPU, 11.1 MHz, with 32 KB cache
memory

ports are used to connect the system
with input/output devices such as
CRT terminals, printers, and communication modems. Up to forty users are
supported by the system. Communications protocols such as IBM 2780/
3780 bisync and X.25 can be
implemented with the optional Intell igent Communications Processor (ICP
8/02) board.

System Architecture
Model 32 uses field-proven, state-ofthe-art VLSI components. Foremost
among them are Zilog's 11.1 MHz
Z8001 16-bit High-Performance CPU
(HPCPU) board, with 32 KB cache
memory, and three high-performance
Z8010 Memory Management Units.
These high-performance components
are specially selected for their superior
speed.
Intelligent controllers, for the SMD
Winchester disk and the cartridge
tape, free the operating system from
low-level device handling functions.
The SMD controller contains a dedicated, customized bit-slice-based
processor which provides extremely
high-performance, optimized to UNIX
support.
.

168 MB SMD Winchester Disk
-

Disk Size: 8 inches
Rotation Speed: 3,600 rpm
Average Seek Time: 20 msec
Data Transfer Rate: 10 Mbitslsec

990

The optionallCP 8/02 Intelligent Communications Processor contains a
Z8002 CPU with 128K bytes of dualported memory and DMA-supported
1/0 ports that allow communication
over both asynchronous and synchronous lines, such as IBM 2780-3780
bisync and X.25 packet-switched
networks.

Comprehensive Software
The UNIX operating system provides
an excellent environment for business
applications.
The System 8000 comes with an
impressive collection of more than
300 utility programs and development
tools that make it easy for end users
and OEMs to develop new applications quickly.
High level programming languages
for scientific and industrial applications are offered, including Pascal, C,
and Ada.

Cartridge Tape Drive

Physical

-

-

ReadlWrite Speed: 30 ips
RewindlSearch Speed: 90 ips
Tracks: 4
Recording Density: 6400 BPI
Capacity (unformatted):
Upt021.3 MB

Memory
- Minimum: 512 KB
- Maximum: 4 MB
- Management: Three Highperformance Z801 0 MMUs.
- Error Handling Parity or Error
Checking and Correcting (ECC)

The optional FPP 8/01 Floating Point
Processor is a high-speed, bit-slice
technology implementation of the
IEEE standard P754 Draft 10. Double
precision extended multiplication, for
example, executes in only 3.8Ilsec.

Height: 84 cm (33 in.)
Width: 48 cm (19 in.)
Depth: 61 cm (24 in.)
Weight: 114 kg (250 pounds),
approximately

Electrical
Options
- Up to 40 users
- Up to 42 serial ports,
5 parallel ports
- Memory expansion up to 4 MB
- Up to four SMD Winchester drives
- ICP 8/02 Intelligent Communications Processor
- FPP 8/01 Floating Point Processor
- Four slots available for board options
- Industry-standard 9 track tape
(1600 bpi)

- Phase: Single
- Frequency: 47 to 63 Hz
Nommal
Selectable
Voltages ± 10%

MaXimum
Sustamed
Current

100-115 VAC/50 Hz 75A
220-240 VAC/50 Hz 4.0A

Maximum
Current
Surge

20A
10A

Environmental
- Operating Temperature:
1Q°C (50°F) minimum,
40°C (104°F) maximum
- Relative Humidity:
20 to 80% (Noncondensing)

OD-1242.-----<

==

"

Other Ada library modules referenced by the source. ada program text.

Intermediate code representallOn is ICSC propnatary non Diana .

....._ _ _-' Optional assembler-In put-code text file can be written.

Unlinked separately compiled
object modules.

Linked executable program file.

2374·002,003

1017

ORDERING INFORMATION
Compiler and three months free maintenance including
released updates. Single CPU license.

Part Number

Description

Host

Target

07-3014-01
07-3015-01
07-3016-01

Zilog/lCSC Ada
Zilog/lCSC Ada
Zilog/lCSC Ada

Zilog System 8000 UNIX
DEC VAX VMS
DEC VAX UNIX

Z8002
Z8002
Z8002

Compiler software maintenance agreement includes
update releases and phone consultation for Ada compiler.
The compiler must be covered by a software support
agreement in order to receive software updates. Failure to

maintain a software support agreement will require
repurchasing the compiler to restart the software support
agreement.

Part Number

Description

Prerequisite

07-3014-05

Ada System 8000 software update service for PIN 07-3014-01
12 months coverage.
Ada-VAX VMS Host software update service for PIN 07-3015-01
12 months coverage.
Ada-VAX UNIX host software update service for PIN 07-3016-01
12 months coverage.

System 8000 UNIX

07-3015-05
07-3016-05

DEC VAX VMS
DEC VAX UNIX

SOFTWARE AVAILABILITY
Software delivery within four weeks of receipt of a valid
customer purchase order and a signed Red End-User
Software License Agreement.

ZILOG/ICSC ADA LANGUAGE IMPLEMENTATION
The Zilog/lCSC Ada compiler enables cost-effective
utilization of the language features described in the
language reference manual, ANSI/MIL-STD 1815A.
Features defined in ANSI/MIL-STD 1815A that are not
implemented in Ada version 3.1 are indicated with an '.

Chapter 1. Introduction
Chapter 2. Lexical Elements
Character set
Lexical elements, separators and delimiters
Identifiers
Numeric literals
Decimal literals
Based literals
Character literals
String literals
Comments
Pragmas
Include files and conditional compilation
Reserved words
Allowable replacement of characters

Chapter 3. Declarations and Types
Declarations
Objects and named numbers
Object declarations
Number declarations
Types and subtypes
1018

Type declarations
Subtype declarations
Classification of operations
Derived types
Scalar types
Enumeration types
Character types
Boolean types
Integer types
Operations of discrete types
Real types
Floating point types
Operations of floating point types
* Fixed point types
• Operations of fixed point types
• Array types (single dimension arrays only)
Index constraints and discrete ranges
Operations of array types
String types
Record types
* Discriminants
• Discriminant constraints
Variant parts
Operations of record types
Access types
Incomplete type declarations
Operations of access type
Declarative parts

Chapter 4. Names and Expressions
Names
Indexed components
Slices
Selected components
, Attributes
implemented = FIRST, LAST, RANGE, LENGTH,
POS, VAL, PRED, SUCC, IMAGE, VALUE, BASE,
ADDRESS, SIZE, COUNT, CALLABLE,
TERMINATED.
Literals
Aggregates
Record aggregates
'Record aggregates discriminant and variant
Array aggregates
Expressions
Operators and expression evaluation
Logical operators and short-circuit control forms
Relational operators and membership tests
Binary adding operators
Unary adding operators
Multiplying operators
Highest precedence operators
Accuracy of operations with real operands
Type conversions
Qualified expressions
Allocators
Static expressions and static subtypes
Universal expressions
Chapter 5. Statements
Simple and compound statements-sequences of
statements
Assignment statement
Array assignments
If statements
Case statements
Loop statements
Block statements
Exit statements
Return statement
Goto statements
Chapter 6. Subprograms
Subprogram declarations
Formal parameter modes
Subprogram bodies
Comformance rules
Inline expansion of subprograms
Subprogram calls
Parameter associations
Default parameters
Function subprograms
Parameter subprograms
Parameter and result type profile-overloading of
subprograms
Overloading of operators

Chapter 7. Packages
Package structure
Package specifications and declarations
Package bodies
Private type and deferred constant declarations
Private types
Operations of a private type
Deferred constants
'Limited types
Chapter 8. Visibility Rules
Declarative region
Scope of declarations
Visibility
Use clauses
Renaming declarations
exception renaming
subprogram renaming
'object renaming
'package renaming
Package Standard
Context of overload resolution

I~

Chapter 9. Tasks
Task specifications and task bodies
Task types and task objects
Task execution and activation
Task dependence and termination of tasks
Entries, entry calls, and accept statements
Delay statements, duration and time
Select statements
Selective waits
Conditional entry calls
Timed entry calls
Priorities
In tasks
'In main
Task and entry attributes
, Abort statements
'Shared variables

I

Chapter 10. Program Structure and Compilation
Issues
Compilation units-library units
Context clauses-with clauses
'Subunits of compilation units
, Automatic reoidering of compilation
The program library
Elaboration of library units
Program Optimization
constant folding and address folding

1019

Chapter 11. Exceptions
Exception declarations
Exception handlers
Raise statements
Exception handling
Exceptions raised during execution of statements
Exceptions raised during elaboration of declarations
Exception raised during task communications
Exceptions and optimization
Supressing checks
RANGE_CHECK and INDELCHECK
"Other check supression
Chapter 12. Generic units
Generic declarations
Generic formal objects
Generic formal types
Generic formal subprograms
Generic bodies
Generic instantiation
Matching rules for formal objects
Matching rules for formal private types
Matching rules for formal scalar types
"Matching rules for formal array types
"Matching rules for formal access types
"Matching rules for formal subprograms

1020

Chapter 13. Representation Clauses and
Implementation-Dependent Features
Representation clauses
" Length clauses
"Enumeration representation clauses
"Record representation clauses
Address clauses
"I nterru pts
Change of representation
The package system
System·dependent named numbers
Representation attributes
Representation attributes of real types
Machine code insertions
Interface to other languages
Unchecked programming
"Unchecked storage deallocation
Unchecked type conversions
Chapter 14.lnpuLOutput
External files and file objects
Package sequential_io
Package direcLio
Package texLio
Package io_exceptions
" Low_level_io
" Fixed_io

Packaging
Informalion

Zilog

PACKAGE INFORMATION
l'

10

I

I

Ii

18-Pln Dual-In-Llne Package (DIP),
Ceramic

0.300
1-0.320--1

:[:€:::::::I

B1I

I-2._.025
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325

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0.025
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0.180

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g,g~ r- o.o<;;lrr-~

0.015
0.050
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0.100
TYP --,

0.125
MIN

0.003

18-Pin Dual-In-Line Package (DIP),
Plastic

NOTE: Package dimensions are given in inches. To convert to millimeters, mu~iply by 25.4.

1023

PACKAGE INFORMATION (Continued)
15

28

I

D

0.598
MAX
PIN 1
IDENTIFICATION ~
I

0
14

.. I·~--l1~~

+.007

'

1

I-~~, ~I ;:~GEi'9fj

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1- - - -

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0.125
MIN

0.060
0.020

0.065
-0.035
BOTH EN OS

---

0.090

---.

11_0.021
0.015

28-Pin Dual-in-Line Package (DIP),
Ceramic

NOTE. Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.

1024

PACKAGE INFORMATION (Continued)
15

28

0.062

RAD

I·
~::~~-

1-·

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0.018
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0.050

"

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TYP

i
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28-Pin Dual-in-Line Package (DIP),
Plastic

NOTE: Package dimensions are given In Inches To convert to millimeters. multiply by 25.4.

1025

PACKAGE INFORMATION (Continued)
21

40

,

It~S::D

~======~
1"0

PIN 1
IDENTIFICATION

~I~~~~~~~~~==~~~
20

C

t~~

0095

0.040

-I

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1
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0.530

I~MAX~I

±.002- -

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m

0.125
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-

0.060
0.020

0.050
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ENDS

~I l

0.100
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0.018
~II- %.003

40·Pln Dual·ln·Line Package (DIP).
Ceramic

NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.

1026

TYP

PACKAGE INFORMATION (Continued)
40

21

T

0.560

I~~=r=n=r=r=nr=rr=n=rr=n=r=r=n=~~

40-Pin Dual-In-Line Package (DIP),
Plastic

NOTE' Package dimensions are given in inches To convert to millimeters, multiply by 25.4.

1027

PACKAGE INFORMATION (Continued)
48

PIN 1
IDENTIFICATION

25

~rDro

P==========~
24

I"

2.425

MWfAX

MAX

'I

.,..-~
~
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! !

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0.125
MIN
0.080
0.020

l ,.

0.050
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BOTH ENDS

j

l ,.

0.100
.010 TYP

4S·Pln Dual·ln·Llne Package (DIP),
Ceramic

NOTE: Package dimensions are given In inches. To convert to millimeters, multiply by 25.4.

1028

j

L ,.

0.018
.003 TYP

PACKAGE INFORMATION (Continued)

25

48

0.062

RADIUS

15'
4 PLACES

r;-~::~~~

fo-

4- ,,!.J-1~11_0'060
0.180
MAX

'.~'''M·"'~l! ~~ .tt~
REF

I.r--- 0.650=-'1
0.610

MIN.

_

=I

0.060

TYP.

0.040

48-Pln Dual-In-Llne Package (DIP),
Plastic

NOTE: Package dimensions are given In inches. To convert to millimeters, multiply by 25.4.

1029

PACKAGE INFORMATION (Continued)
33

84

PIN 1
IDENTIFICATION
~--------------------~4HMAX--------------------~

~

':12 TVP
-~- .009

i~

1-.750 REF-I

.070,..005

TYP

64-Pin Dual-in-Line Package (DIP),
Ceramic

NOTE: Package dimensions are given in Inches. To convert to millimeters, multiply by 25.4.

1030

l

.095 MAX

---r
.130
.100
BOTH ENDS

PACKAGE INFORMATION (Continued)

IrI-

-~:::~~~:-

-~-g:g~

1 _,.~,,~o
0.013
0.011
0.020 x 45 0 REF.

SQ'-I
SQ.
0.475 SQ.
0.489 SQ.

0.528
0.492

-I

18

6

D

23

28

44-Pln Leadless Chip Carrier (LCC),
Ceramic, Jedec l\tpe C

PIN1
IDENTIFICATION
45 0 x 0.045 MAX",

0.026..L

NOMINALT

45 0 x 0.010 MAX

3 PLACES

6

X,'t'tt~~~"" ;-f0.6SO
! I

I

o.lf

0

,,45 - x 0.064 MAX
"

:

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r

0.620

lo013]
To.o18

I "1~_0.021

....
+-0.098
11
_ _ 0.170

44-Pln Plastic Chip Carrier (PCC)

NOTE: Package dimensions are given in inches. To convert to millimeters. multiply by 25.4.

1031

PACKAGE INFORMATION (Continued)

~:::~ 4 P L _ l

•

-~::::

•

Ir=

~::~~

2PL-

~:~::

0.653

-0.637 SQ-

0.094
0.076
0.020RTYP

SQ-

INSIDE AND OUTSIDE

1//45° )(0.010

Y

6~

" t

t

-~_

0.028

0.022

0.050
TYP

r
0.806
0.794
4 PL

45 0 x 0.040 REF
PIN 1 INDEX

68·Pin Leadless Chip Carrier (LCC).
Ceramic. Jedec lYpe A

NOTE' Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.

1032

PACKAGE INFORMATION (Continued)

' - 0.008 R REF
88PL

~

~::!~SQ~

45° )( 0.040
REF

~

0.643 S Q 0.592

IJ

~:::: so

II

68-Pln Leadless Chip Carrier (LCC).
Ceramic, Jedec '1\'pe C, Preliminary

NOTE· Package dimensions are given in inches. To convert 10 millimeters, muttiply by 25.4.

1033

PACKAGE INFORMATION (Continued)
45°

x 0.045 MAX

PIN 1
IDENTIFICATION

0.026-.l

NOMINALT

0.928

+0.018
I

I~~!-:::

45° x 0.010 MAX

3PL

P--i=0.170

6S-Pln Plastic Chip Carrier (PCC)

NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.

1034

PACKAGE INFORMATION (Continued)
40

L[~ODDDDDDDDDDD
O.

--) D D

~~~~

M AX MAX

F

llJ"DDDDDDDDDDDD

:~ 1_,

20

1

,

IDENTIFI CATION
SOCKE

TA

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t
0.300

-

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TYP

I-OR~~-I

O.OSO;, 020

'I

1220 MAX

~

:~I
MAX

0010

,

2.020 MAX

~
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rO.S30 SO'~I
MAX

\--LI_O.10D±.010TYP
0.OSO;,.01S

BOTH ENDS

-11-~~d~3

•

TYP

1~O~

\
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0'18S

ti

:r

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MIN

-002.

I
...
=

40·Pin Protopack (R)

NOTE Package dimensions are given In Inches To convert to millimeters, multiply by 25.4.

1035

PACKAGE INFORMATION (Continued)

1 .1.-.----e-0•0 •0 •00000000
• • • • • • • • • • • • •I • • •

0.453

__________________~_+ ___
--ll_°--l'j_O°--l"~inn_o~
JJ

TT; ............... ..

0.987.J.

~

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IDENTIFICA~:~~/;/
SOCKET A

_ I 0.100 x 11 ="':.:~ -0.520----: _0.330_

IDENTIFICATION
0.100)( 19

=1 . 9 0 0 - - - - - - _ 1

r - - - - - - - - - - - - - 2.311 - - - - - - - - - - - - 1
CERAMIC L I D \

G-l0
EPOXY/GLASS\

)----t---,
"-LOW

I

PIN STANo.OFF"/
4PL
-

PAOFILE
SOCKET

0.200 -0.300-1

1

-0.300--0.400-

40-Pin Low Profile Protopack (T)

NOTE Package dimensions are given in inches To convert to millimeters, multiply by 25.4.

1036

PACKAGE INFORMATION (Continued)
I-- 0.055

~I

1: k
IfII
0.019 DIA
TYP

::::: DIA
4PL

T

::::: DIA

'00 rr======91
"00
·00
'00
'00

45 0 x 0.045 MAX
~--0.800---I

TYP

0.045
0.008 REF

I-.. 0.093
I 0.077

II

O.OO5R

TYP
0.800
1.000

0.030 x 45° REF
3PL

~---1.000----I

~ ~'130
MIN

0.190
0.180

68-pln Pin Grid Array (PGA), Preliminary

NOTE: Package dimensions are given in Inches. To convert to millimeters, multiply by 25 4

1037

Techaical
Traiaiag

Zilog

Zilog

Technical TraiDing

AprIl 1985
Continuing to respond to our customers' need for technical
training and information, Zilog's Training and Education
Department is offering an exceptionally wide range of
courses in 1985. Whether your need is introductory
exposure, product evaluation, or detailed design
information, Zilog's technical training seminars provide the
knowledge you want in the easiest, most efficient manner.
Each course is designed to meet the educational needs of
computer professionals by combining lecture presentations
with "hands-on" laboratory exercises. In addition to the
scheduled sessions held at Zilog's modern facilities in
Campbell, California, courses may be arranged at your
company's'site.
Why waste valuable time and effort with weeks of self-study?
Why risk expensive errors during product development?
Zilog's technical training seminars can give your designers
the knowledge necessary to take full advantage of Zilog's
innovative state-of-the-art microprocessor components and
microcomputer systems.
The Zilog Training Center is located at:
1315 Dell Avenue
Building C, Mail Stop C1-2
Campbell, CA 95008
Telephone: (408) 370-8091

Three days

This basic introduction to microcomputers is intended for
non-technical
personnel.
The course discusses
microcomputer fundamentals and capabilities. Topics
include:
•

Definition of a microcomputer

• Microcomputer organization

• Microcomputer operating procedures
• Overview of Zilog products
There are no prerequisites for this course.

Microprocessors: A General Introduction

Three days

This seminar is an introductory course in microprocessor
technology for engineers, programmers, and other
technical personnel. Microprocessor fundamentals and
capabilities and the basics of microcomputer design are
described. Topics include:
• Microprocessor architecture and organization
• Instruction execution
• Central processor units, memories, support devices
• Overview of Zilog microprocessor products
A background in digital logic, including binary and hex
number systems, is suggested as a course prerequisite.

ZS Component Family

Current detailed brochures, including dates and prices, are
available from your local Zilog Sales Office or the Corporate
Training Center.

Microcomputer Basics and Concepts

• Purpose and operation of peripheral devices

Three days

The Z8 is Zilog's powerful single-chip, 8-bit microcomputer.
This seminar IS deSigned for hardware and software
development personnel who are familiar with
microcomputer system design and who are interested in
learning Z8 architecture, capabilities, and supporting
systems. Some of the topics covered are:
• Z8 architecture and timing
• Z8 assembly language programming
• Interfacing memory and peripheral devices
• Z8 software development tools
• Z8 Development Module and other supporting products
Designers interested in using the Z8090 UPC Universal
Peripheral Controller should also attend this seminar, since
the architecture of the UPC is very similar to that of the Z8.

1041

zao Component Family

Four days

This basic course on Z80 components is designed for
hardware and software development personnel with a
modest background in microprocessors and assembly
language programming This course should be taken by
anyone interested in effectively using the Z80 family of
products. Some topics covered are:
• Z80 architecture and timing
• Z80 assembly language programming overview
• Z80 interrupt processing
• Z80 PIO Parallel 110 Controller
• Z80 CTC CounterlTimer Controller

•

Use of the on-chip cache, memory management, and
peripheral devices

• Software development tools and other supporting
products

zaooo Processor Family

• Z8000 CPU architecture: Z8001, Z8002, Z8003, and
Z8004

• Z80 DMA Direct Memory Access Controller
• Z80 SID Serial 110 Controller

• Z-BUS Memory and peripheral interfacing

This course offers a "hands-on" approach to learning by
doing. As each chip is covered, students measure their
progress by programming a single-board computer in the
laboratory.

• Z8000 Assembly language programming

zao Assembly Language

Four days

This seminar is for programmers needing to learn the Z80
assembly programming language. The course includes
class presentation and hands-on programming labs that
allow the students to write their own assembly language
programs. Some of the topics covered are:
•

Language structure and syntax

• Z80 instruction set
• Z80 CPU flag and register utilization
•

Macros

• Subroutines

zaoo Processor Family

Four days

The Z800 family of high-performance microprocessors are
object-code compatible with the Z80 microprocessor. This
seminar is intended for hardware and software personnel
interested in designing with Z800 family processors.
Students are assumed to have some familiarity with
microprocessor architecture and assembly language
programming. Some of the topics covered include:
• Z800 CPU architecture: Z81 00 and Z81 08
•

Memory and peripheral interfacing

• Z800 assembly language programming

1042

Four days

Zilog's basic course on the Z8000 family processors is for
hardware and software development personnel who are
familiar with microprocessor system design. Design and
interface techniques of the Z8000 CPUs and CPU support
chips are covered in detail. Anyone interested in effectively
using the Z8000 family processors should take this course.
Some of the topics covered include:

• Z8010 MMU Memory Management Unit
• Z8015 PMMU Paged Memory Management Unit
• Z8000 Software development tools
• Z8000 Development Module and other support
products

zao,ooo Processor Family

Four days

The Z80,000 is a 32-bit microprocessor that is object-code
compatible with the Z8000 family of 16-bit processors. This
course provides hardware and software personnel with the
background needed for design, development, and
debugging of Z80,000-based systems. The Z80,000
Processor Family course is recommended for engineers
already familiar with microprocessor architectures and
assembly language programming who are interested in
effectively using Z80,000 family processors. Some topics
covered are:
• Z80,000 CPU architecture
•

Memory and peripheral interfacing

•

Use of the on-chip cache and memory management
device

• Z80,000 assembly language programming
• Software development tools and other supporting
products

EMS 8000 Emulation System

One day

This seminar details the use of the EMS 8000 emulator
during development and debugging of Z8000-based
systems. The emulator commands and their operation are
fully described. The EMS 8000 emulation system is a
powerful development tool for the hardware and software
engineer. Some of the topics covered include:

Use of triggers as breakpoints or trace qualifiers

•

Mapping EMS memory to the target system

•

Performance
applications

measurements

Three days

UNIX for Non-Technical Users is a lab-Oriented presentation
of the file generation and maintenance utilities In UNIX. This
course is intended for users with little or no computer or
operating systems experience. TopICS include:
•

Introduction to UNIX

• The hierarchical file system

• EMS 8000 hardware design
•

UNIX for Non-Technical Users

for

• File generation and manipulation
• The 'vi' screen editor

benchmarking

•

Linking EMS systems for multiprocessor emulations

•

Building user-definable macros of EMS commands

• The C shell enVIronment
Lectures are supplemented with lab exercises uSing the
Zilog System 8000.
UNIX User's Seminar

Five days

This course is recommended for all engineers interested In
using the EMS 8000 Emulation System to analyze and
debug Z8000-based systems. The Z8000 Components
family course or equivalent experience is recommended as
a prerequisite.

The UNIX User's Seminar IS a comprehensive overview of
the powerful mUltiuser, multitasking UNIX operating system.
It is intended for programmers, engineers, and other
technical personnel with little or no knowledge of UNIX.
Some topics covered are:

Data Communications Concepts

• The kernel, shell, and file system

Four days

An introductory course in data communications, this
seminar provides the engineer with a thorough background
in the terminology and operating concepts of this
ever-expanding field. Topics include:
• Data transmissions modes and formats
•

Data link controls: HOLC, SOLC, Bisync

• Packet switching: X.25, X.75
• Open systems interconnection

• The C shell environment
• File management tools
• Editors and text processing
•

Program development tools

The lecture is supplemented with lab sessions using the
System 8000 microcomputer. As a prerequisite, students
must have a general understanding of computers,
operating systems, and simple programming tools such as
editors.

• Z8030/Z8530 Serial Communications Controller
•

Local area networks

• Future trends
A background in digital electronics and a general
microcomputer course or equivalent experience is
recommended as a prerequisite for this course.

1043

Advanced UNIX Concepts

Two days

A detailed examination of several topics introduced in the
UNIX User's Seminar, this course is recommended for
programmers using a UNIX system for software
development. Topics covered include:
• The 'awk' processor
• The 'make' file processor

The C programming course is for programmers interested in
learning C, a high-level systems programming language.
The course includes class presentation and hands-on
programming labs that allow students to write their own C
programs on a System aooo microcomputer. Some topics
covered are:

• Data types, data structures, and pointers

• Networking with UNIX

• Program flow control

• Advanced document formatting
Lab exercises using a System aooo microcomputer
supplement the lecture. The UNIX User's Seminar or
instructor approval is required as a prerequisite for this
course.
Three days

The UNIX System Administrator course is designed for
persons responsible for maintaining and administering a
UNIX-based system. Some topics covered are:
• System organization: kernel, shell, and file systems
• System start-up and shut-down
• File system checking and repair
• Adding and deleting users
• System reconfiguration and upgrades
Lectures are supplemented with lab exercises on the
System aooo microcomputer. The UNIX User's Seminar or
instructor approval is required as a prerequisite for this
course.

1044

Four days

• Program structure

• Advanced shell programming

UNIX System Administrator

C Programming

• Program development on the System aooo
• System calls on the UNIX Operating System.
Some high-level language programming experience is
suggested as a course prerequisite.

Advanced Peripherals Course
Three days
This course is an in-depth study of the zaooo/zasoo family
of peripheral devices, with emphasis on the Za030/ZaS30
SCC, za036/zaS36 Cia, and za03a Fla.
Introduction to Ada Programming
This introduction to the Ada programming language is
intended for programmers familiar with high-level
languages.

Data Book
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West
Sales & Technical Center
Zilog , Incorporated
1315 Dell Avenue
Campbell, CA 95008
Phone: (408) 370-8000
TWX: 910-338-7621
Sales & Technical Center
Zilog, Incorporated
15643 Sherman Way
Suite 430
Van Nuys, CA 91406
Phone: (818) 989-7485
TWX: 910-495-1765
Sales & Technical Center
Zilog, Incorporated
125 Baker Ave .
Suite 180
Costa Mesa, CA 92626
Phone: (714) 261-1281
Sales & Technical Center
Zilog,lnccrporated
1750 112th Ave . N.E.
Suite 0 161
Bellevue, WA 98004

Zilog

an affiliate of
Elf{ON Corporation

1315 Dell Ave.
Campbell , CA 95008
(408) 370-8000
TWX: 910-338-7621
00-2034-0';
Printed in U.SA

Sales & Technical Cenler
Zilog , lncorporaled
5700 Lombardo Cenlre
Suite 245
Seven Hills, OH 44131
Phone: (216) 447-1480
FAX: 216-447-1483

South
Sales & Technical Center
Zilog , lncorporaled
1750 North Collins
SuiteF
Richardson , TX 75080
Phone: (214) 231-9090
TWX: 910-880-5850

East
Sales & Technical Cenler
Zilog, Incorporated
24 New England Executive Park
Burlington, MA 01803
Phone: (617) 273-4222
TWX: 710-332-1726
Sales & Technical Center
,I

Canada
Sales & Technical Cenler
Mail Box 151
5915 Airport Road
Suite 400
Mississauga, Toronto
Canada L4VITI
Phone: (416) 673-0634
FAX: 416-673-0628

United Kingdom
Zilog U.K. lid.
Zilog House
43-53 Moorbridge Road
Maidenhead , SL6 8PL
Berkshire, England
Phone: (44) (628) 39200
Telex: (851) 848609

France
Zilog, SARl.
Cedex 31 , Place des Corolles
92098 Paris La Defense

France
Phone: (33) (1) 334-6009
Telex: (842) 611445



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