1986_CMOS_NMOS_Special_Function_Data 1986 CMOS NMOS Special Function Data
User Manual: 1986_CMOS_NMOS_Special_Function_Data
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Master Index
Handling and Design Guidelines
CMOS ADCs/DACs
I
I
I
CMOS Decoders/Display Drivers
I
CMOS Operational Amplifiers/Comparators
I
CMOS/NMOS PLLs/Frequency Synthesizers
CMOS Remote Control Functions
I
II
CMOS Smoke Detectors
II
Miscellaneous Functions
II
II
Reliability
Package Dimensions
II
MOTOROLA
CMOS/NMOS
SPECIAL FUNCTIONS DATA
Prepared by
Technical Information Center
This book presents technical data for the CMOS and NMOS Special Function integrated
circuits. Complete specifications are provided in the form of data sheets. In addition, a Function Selector Guide and a Handling Precautions chapter have been included to familiarize
the user with these circuits.
Motorola reserves the right to make changes to any product herein to improve reliability,
function or design. Motorola does not assume any liability arising out of the application or
use of any product described herein; neither does it convey any license under its patent
rights nor the rights of others.
Motorola Inc. general policy does not recommend the use of its components in life support applications where in a failure or malfunction of the component may directly threaten
life or injury. Per Motorola Terms and Conditions of Sale, the user of Motorola components
in life support applications assumes all risk of such use and indemnifies Motorola against
all damages.
For marketing and application information contact:
Motorola Inc.
P.O. Box 6000
Austin, TX 78762
Attn: MOS Logic Marketing
Mail Stop: F-8
Printed in U.S.A.
Series A
Second Printing
©Motorola Inc., 1986
Previous Edition © 1984
"All Rights Reserved"
Product Preview data sheets herein contain information on a product under
development. Motorola reserves the right to change or discontinue these
products without notice.
Advance Information data sheets herein contain information on new pro-
ducts. Specifications and information are subject to change without
notice.
Master Index
1-1
II
II
1-2
MASTER INDEX
This index includes Motorola's entire MCl4000 series CMOS products, although complete
data sheets are included for only the Special Functions. Data sheets for devices in other books,
are designated in the page number column as:
Logic - See DL 131, CMOS Logic Data
Telecom - See DL 136, Telecommunications Data
MCU - See DL 132R1, Single-Chip Microcomputer Data
MPU -
Device
Number
Me
6190
6195
6196
14000U8
140018
14001 U8
140028
14oo2U8
140068
14007U8
140088
140118
14011U8
140128
14012U8
140138
140148
140158
140168
140178
140188
140208
140218
140228
140238
14023U8
140248
140258
14025U8
140278
14028B
14029B
14032B
See DL 133, 8-8it Microprocessor and Peripheral Data
Page
Description
Number
6-3
N-Channel, Silicon Gate, Frequency Synthesizer ................. .
N-Channel, Silicon Gate, Frequency Synthesizer ................. .
6-4
6-4
N-Channel, Silicon Gate, Frequency Synthesizer ................. .
Dual3-lnput NOR Gate Plus Inverter ........................... . Logic
Quad 2-lnput NOR Gate ...................................... . Logic
Quad 2-lnput NOR Gate ...................................... . Logic
Dual4-lnput NOR Gate ....................................... . Logic
Dual4-lnput NOR Gate ....................................... . Logic
18-Bit Static Shift Register .................................... . Logic
Dual Complementary Pair Plus Inverter ......................... . Logic
4-Bit Full Adder ............................................. . Logic
Quad 2-lnput NAND Gate .................................... . Logic
Quad 2-lnput NAND Gate .................................... . Logic
Dual4-lnput NAND Gate ..................................... . Logic
Dual4-lnput NAND Gate ..................................... . Logic
Dual D Flip-Flop ............................................. . Logic
8-Bit Static Shift Register ..................................... . Logic
Dual4-Bit Static Shift Register ................................ . Logic
Quad Analog Switch/Multiplexer .............................. . Logic
Decade Counter/Divider ..................................... . Logic
Presettable Divide-by-N Counter ............................... . Logic
14-Bit Binary Counter ........................................ . Logic
8-Bit Static Shift Register ..................................... . Logic
Octal Counter/Divider ....................................... . Logic
Triple 3-lnput NAND Gate .................................... . Logic
Triple 3-lnput NAND Gate .................................... . Logic
7-Stage Ripple Counter ...................................... . Logic
Triple 3-lnput NOR Gate ...................................... . Logic
Triple 3-lnput NOR Gate ...................................... . Logic
Dual J-K Flip-Flop ........................................... . Logic
BCD-to-Decimal/8inary-to-Octal Decoder ...................... . Logic
8inary/Decade Up/Down Counter ............................. . Logic
Triple Serial Adder (Positive Logic) ............................. . Logic
1-3
II
II
Device
Number
Me
140348
140358
140388
140408
140428
140438
140448
140468
14049U8
140508
140518
140528
140538
140608
14066B
140678
140688
14069U8
140708
140718
140728
140738
14075B
14076B
14077B
14078B
140818
14082B
14093B
140948
140978
140998
14160B
14161B
14162B
14163B
14174B
14175B
14194B
14400
14401
14402
14403
14405
14408
Page
Description
8-Bit Universal Bus Register ................................... .
4-Bit Shift Register .......................................... .
Triple Serial Adder (Negative Logic) ............................ .
12-Bit Binary Counter ........................................ .
Quad Transparent Latch ...................................... .
Quad NOR R-S Latch ........................................ .
Quad NAND R-S Latch ....................................... .
Phase-Locked Loop ......................................... .
Hex Inverter/Buffer .......................................... .
Hex Buffer ................................................. .
8-Channel Analog Multiplexer/Demultiplexer .................... .
Dual4-Channel Analog Multiplexer/Demultiplexer ................ .
Triple 2-Channel Analog Multiplexer/Demultiplexer ............... .
14-Bit Binary Counter and Oscillator ............................ .
Quad Analog Switch/Multiplexer .............................. .
16-Channel Analog Multiplexer/Demultiplexer ................... .
8-lnput NAND Gate .......................................... .
Hex Inverter ................................................ .
Quad Exclusive OR Gate ...................................... .
Quad 2-lnput OR Gate ....................................... .
Dual4-lnput OR Gate ........................................ .
Triple 3-lnput AND Gate ...................................... .
Triple 3-lnput OR Gate ....................................... .
Quad D-Type Register ....................................... .
Quad Exclusive NOR Gate .................................... .
8-lnput NOR Gate ........................................... .
Quad 2-lnput AND Gate ...................................... .
Dual4-lnput AND Gate ....................................... .
Quad 2-lnput NAND Schmitt Trigger ........................... .
8-Bit Bus-Compatible Shift/ Store Latch ........................ .
Dual 8-Channel Analog Multiplexer/Demultiplexer ................ .
8-Bit Addressable Latch ...................................... .
Synchronous Programmable Decade Counter ................... .
Synchronous Programmable 4-Bit Binary Counter ................ .
Synchronous Programmable Decade Counter ................... .
Synchronous Programmable 4-Bit Binary Counter ................ .
Hex D Flip-Flop ............................................. .
Quad D Flip-Flop ............................................ .
4-Bit Universal Shift Register .................................. .
PCM Mono-circuit ........................................... .
PCM Mono-circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
peM Mono-circuit. . . . . . . . . . . . . . . . . . . . . .
PCM Mono-circuit ........................................... ,
PCM Mono-circuit ............................................
Binary-to-Phone Pulse Converter ...............................
1-4
Number
Logic
Logic
Logic
Logic
Logic
Logic
Logic
6-13
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Device
Number
Me
Description
14409
14410
14411
14412
14413
14414
14415
14416
14417
14418
14419
14422
14433
14435
14442
14443
Binary-to-Phone Pulse Converter .............................. .
2-of-8 Tone Encoder ......................................... .
Bit-Rate Frequency Generator ................................. .
Universal Low-Speed Modem ................................. .
PCM Sampled Data Filter ..................................... .
PCM Sampled Data Filter ..................................... .
Quad Precision Timer/Driver .................................. .
PCM Time Slot Assigner Circuit ............................... .
PCM Time Slot Assigner Circuit ............................... .
PCM Time Slot Assigner Circuit ............................... .
2-of-8 Keypad-to-Binary Encoder .............................. .
Remote Control Transmitter (Product Cancelled) ................. .
3 Y2 Digit A/ D Converter ...................................... .
3Y2 Digit A/D Logic Subsystem (Product Cancelled) .............. .
Microprocessor-Compatible A/ D Converter ..................... .
6-Channel A/ D Converter Subsystem .......................... .
Microprocessor-Compatible A/D Converter ..................... .
6-Channel A/D Converter Subsystem .......................... .
Remote Control Transmitter .................................. .
Remote Control Receiver ..................................... .
Automotive Speed Control Processor .......................... .
Smoke Detector Circuit (Product Cancelled) ..................... .
Smoke Detector Circuit (Product Cancelled) ..................... .
Smoke Detector Circuit (Product Cancelled) ..................... .
Smoke Detector Circuit (Product Cancelled) ..................... .
Low Cost Smoke Detector .................................... .
Low Cost Smoke Detector .................................... .
Interconnectable Smoke Detector ............................. .
Addressable Asynchronous Receiver/Transmitter ................ .
Hex Contact Bounce Eliminator ................................ .
Hexadecimal-to-7 Segment Latch/Decoder ROM/Driver .......... .
PCM Remote Control Transmitter .............................. .
7-Segment LED Display Decoder/Driver with Serial Interface ...... .
Industrial Control Unit ........................................ .
Triple Gate ................................................. .
Strobed Hex Inverter/Buffer .................................. .
Hex 3-State Buffer .......................................... .
Hex TTL- or CMOS-to-CMOS Level Shifter ...................... .
Dual Expandable AOI Gate (Superceded by 14506UB) ............. .
Dual Expandable AOI Gate .................................... .
Dual4-Bit Latch ............................................. .
BCD Up/ Down Counter ...................................... .
BCD-to-7-Segment Latch/Decoder/Driver ...................... .
8-Channel Data Selector ...................................... .
BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking .... .
14444
14447
14457
14458
14460
14461
14462
14464
14465
14466
14467-1
14468
14469
14490
14495-1
14497
14499
14500B
14501 UB
14502B
14503B
14504B
14506B
14506UB
14508B
14510B
14511B
14512B
14513B
1-5
Page
Number
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Logic
Telecom
Telecom
Telecom
Telecom
3-3
3-15
3-16
3-25
3-29
3-39
7-3
7-3
9-3
8-3
8-8
8-13
7-13
9-9
4-3
7-21
4-8
9-16
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
4-14
Logic
4-20
II
II
Device
Number
Me
14514B
14515B
14516B
14517B
14518B
14519B
14520B
14521B
14522B
14526B
14527B
14528B
14529B
14530B
14531B
14532B
14534B
14536B
14538B
14539B
14541B
14543B
14544B
14547B
14548B
14549B
14551B
14553B
14554B
14555B
14556B
14557B
14558B
14559B
14560B
14561B
14562B
14566B
14568B
14569B
14572UB
14573
14574
14575
14580B
Description
4-BitTransparent Latch/4-to-16 Line Decoder (High) ............. .
4-Bit Transparent Latch/4-to-16 Line Decoder (Low) .............. .
Binary Up/ Down Counter .................................... .
Dual 64-Bit Static Shift Register ............................... .
Dual BCD Up Counter ........................................ .
4-Bit AND/OR Selector ...................................... .
Dual Binary Up Counter ...................................... .
24-Stage Frequency Divider ................................... .
Programmable BCD Divide-by-N Counter ....................... .
Programmable Binary Divide-by-N Counter ...................... .
BCD Rate Multiplier ......................................... .
Dual Monostable Multivibrator (Not Recommended for New Designs)
Dual 4-Channel Analog Data Selector .......................... .
Dual 5-lnput Majority Logic Gate ............................... .
12-Bit Parity Tree ............................................ .
8-Bit Priority Encoder ........................................ .
5-DecadeCounter ........................................... .
Programmable Timer ........................................ .
Dual Precision Monostable Multivibrator ........................ .
Dual4-Channel Data Selector/Multiplexer ...................... .
Programmable Oscillator-Timer ................................ .
BCD-to-7-Segment Latch/Decoder/Driver for Liquid Crystals ...... .
BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking .... .
High-Current BCD-to-7-Segment Decoder/Driver ................ .
Dual Monostable Multivibrator (Retriggerable/ Resettable) ......... .
Successive Approximation Register ............................ .
Quad 2-Channel Analog Multiplexer/Demultiplexer ............... .
3-Digit BCD Counter ......................................... .
2 x 2-Bit Parallel Binary Multiplier .............................. .
Dual Binary to 1-of-4 Decoder ................................. .
Dual Binary to 1-of-4 Decoder (Inverting) ........................ .
1-to-64 Bit Variable Length Shift Register ....................... .
BCD-to-7-Segment Decoder .................................. .
Successive Approximation Register ............................ .
NBCD Adder ............................................... .
9's Complementer ........................................... .
128-Bit Static Shift Register ................................... .
Industrial Time-Base Generator ................................ .
Phase Comparator and Programmable Counters ................. .
Dual Programmable BCD/ Binary Counter ....................... .
Hex Gate ................................................... .
Quad Programmable Op Amp ................................. .
Quad Programmable Comparator .............................. .
Programmable Dual Op Amp/ Dual Comparator ............... ; .. .
4 x 4 Multiport Register ....................................... .
1-6
Page
Number
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
4-28
4-33
4-39
Logic
3-40
Logic
Logic
Logic
Logic
Logic
Logic
4-44
3-40
Logic
Logic
Logic
Logic
6-18
Logic
Logic
b-3
5-3
5-3
Logic
Device
Number
Me
14581B
14582B
14583B
14584B
14585B
14597B
14598B
14599B
142100
143403
144110
144111
145000
145001
145026
145027
145028
145029
145040
145041
145100
145104
145106
145107
145109
145112
145143
145144
145145-1
145146-1
145151-1
145152-1
145155-1
145156-1
145157-1
145158-1
145159-1
145402
145406
145409
145411
145414
145415
145418
Description
4-Bit Arithmetic Logic Unit .................................... .
Look-Ahead Carry Block ..................................... .
Dual Schmitt Trigger ......................................... .
Hex Schmitt Trigger ......................................... .
4-Bit Magnitude Comparator .................................. .
8-Bit Bus-Compatible Counter Latch ........................... .
8-Bit Bus-Compatible Addressable Latch ........................ .
8-Bit Addressable Latch ...................................... .
4 x 4 Cross Point Switch ...................................... .
Quad Line Driver ............................................ .
Hex Of A Converter with Serial Interface ........................ .
Quad Of A Converter with Serial Interface ....................... .
48-Segment Multiplexed LCD Driver (Master) .................... .
44-Segment Multiplexed LCD Driver (Slave) ..................... .
Remote Control Encoder ..................................... .
Remote Control Decoder ..................................... .
Remote Control Decoder ..................................... .
Remote Control Decoder ..................................... .
Analog-to-Digital Converter with Serial Interface ................. .
Analog-to-Digital Converter with Serial Interface ................. .
4 x 4 Cross Point Switch ...................................... .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
PLL Frequency Synthesizer ................................... .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
4-Bit Data Bus Input PLL Frequency Synthesizer
(Not Recommended for New Designs) ........................ .
4-Bit Data Bus Input PLL Frequency Synthesizer ................. .
4-Bit Data Bus Input PLL Frequency Synthesizer ................. .
Parallel Input PLL Frequency Synthesizer ....................... .
Parallel Input PLL Frequency Synthesizer ....................... .
Serial Input PLL Frequency Synthesizer ......................... .
Serial Input PLL Frequency Synthesizer ......................... .
Serial Input PLL Frequency Synthesizer ......................... .
Serial Input PLL Frequency Synthesizer ......................... .
Serial Input PLL Frequency Synthesizer with Analog Phase Detector.
13-Bit Linear Codec .......................................... .
RS-232 Interface ............................................ .
Pulse Dialer ................................................ .
Baud Rate Generator ........................................ .
Dual Tuneable Low-Pass Sampled Data Filters ................... .
Dual Tuneable Linear Phase Low-Pass Sampled Data Filters ....... .
Master Digital Loop Transceiver ............................... .
1-7
Page
Number
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Telecom
Telecom
3-47
3-47
4-49
4-49
7-27
7-27
7-27
7-27
3-52
3-52
Telecom
6-28
6-29
6-28
6-28
6-28
6-35
6-36
6-37
6-50
6-63
6-73
6-84
6-95
6-108
6-108
6-120
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
II
II
Device
Number
Me
145419
145422
145426
145428
145429
145432
145433
145440
145441
145445
145450
145453
146805
146818
146823
1468705
Page
Description
Number
Slave Digital Loop Transceiver ................................. Telecom
MDPSK Universal Digital Loop Transceiver (2-Wire Master) ......... Telecom
MDPSK Universal Digital Loop Transceiver (2-Wire Slave) .......... Telecom
Data Set Interface ............................................ Telecom
Telset Audio Interface Circuit .................................. Telecom
2600 Hz Tone Signalling Filter .................................. Telecom
Tuneable Notch/Band-Pass Filter ............................... Telecom
Low-Speed Modem Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Telecom
Low-Speed Modem Filter ..................................... , Telecom
300 Baud FS K Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Telecom
1200 Baud FSK Modem ....................................... Telecom
33-Segment LCD Driver with Serial Interface . . . . . . . . . . . . . . . . . . . . .
4-59
Family of 8-Bit CMOS MCUs/MPUs ............................. MCU,MPU
Real-Time Clock/RAM ........................................ MCU,MPU
Parallel Interface ............................................. MCU,MPU
8-Bit CMOS MCUs with EPROM ................................ MCU,MPU
1- 8
Handling and Design Guidelines
2-1
II
®
I
MOTOROLA
HANDLING AND DESIGN GUIDELINES
HANDLING PRECAUTIONS
1. Do not exceed the Maximum Ratings specified by the
data sheet.
2. All unused device inputs should be connected to VDD
or VSS.
3. All low-impedance equipment (pulse generators, etc.)
should be connected to CMOS or NMOS inputs only
after the device is powered up. Similarly, this type of
equipment should be disconnected before power is
turned off.
4. A circuit board containing CMOS or NMOS devices is
merely an extension of the device and the same
handling precautions apply. Contacting edge connectors wired directly to devices can cause damage.
Plastic wrapping should be avoided. When external
connections to a PC board address pins of CMOS or
NMOS integrated circuits, a resistor should be used in
series with the inputs or outputs. The limiting factor
for the series resistor is the added delay caused by the
time constant formed by the series resistor and input
capacitance. This resistor will help limit accidental
damage if the PC board is removed and brought into
contact with static generating materials. For convenience, equations for added propagation delay and
rise time effects due to series resistance size are given
in Figure 1.
5. All CMOS or NMOS devices Should be stored or
All MOS devices have an insulated gate that is subject to
voltage breakdown. The gate oxide for Motorola's devices is
about 800 A thick and breaks down at a gate-source potential of about 100 V. The high-impedance gates on the devices
are protected by resistor-diode networks. However, these
on-chip networks do not make the IC immune to electrostatic damage (ESD). Laboratory tests show that devices
may fail after one very high voltage discharge. They may also
fail due to the cumulative effect of several discharges of
lower potential.
Static-damaged devices behave in various ways, depending on the severity of the damage. The most severely
damaged are the easiest to detect because the input or output has been completely destroyed and is either shorted to
VDD, shorted to VSS, or open-circuited. The effect is that
the device is no longer functional. Less severe cases are
more difficult to detect because they appear as intermittent
failures or degraded performance. Another effect of static
damage is, often, increased leakage currents.
CMOS and NMOS devices are not immune to large static
voltage discharges that can be generated while handling. For
example, static voltages generated by a person walking
across a waxed floor have been measured in the 4-15 kV
range (depending on humidity, surface conditions, etc.).
Therefore, the following precautions should be observed.
FIGURE 1 -
NETWORKS FOR MINIMIZING ESD AND REDUCING CMOS LATCH UP SUSCEPTIBILITY
VDD
D1
I
To Off-Board
Connection
l
I
R1
MaS
Input
or
Output
MaS
Input
or
Output
To Off-Board
Connection
D2
~---'
Advantage: R2< R1 for the same = VSS
level of protection.
Impact on ac and dc
characteristics is minimized.
Advantage: Requires minimal board area
Disadvantage: R1> R2 for the same level of
protection, therefore rise and fall
times, propagation delays, and output
drives are severely affected.
Disadvantage:
More board area, higher initial cost
Note: These networks are useful for protecting the following:
A. digital inputs and outputs
B. analog inputs and outputs
C. 3-state outputs
D. bidirectional (JIO) ports
EQUATION 1 - PROPAGATION DELAY
vs. SERIES RESISTANCE
EQUATION 2 - RISE TIME
vs. SERIES RESISTANCE
t
t
R",,---
R""
where:
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay in seconds
C= the board capacitance plus the driven device's
input capacitance in farads
k=O.33 for the MC145040/1
k= 0.7 for other devices
:~~:
where:
R = the maximum allowable series resistance in ohms
t = the maximum rise time per data sheet in seconds
C = the board capacitance plus the driven device's
input capacitance in farads
k=O.7 for the MC145040/1
k = 2.3 for other devices
2-2
6.
7.
8.
9.
10.
11.
12.
transported in materials that are antistatic. Devices
must not be inserted into conventional plastic
"snow", styrofoam or plastic trays, but should be left
in their original container until ready for use.
All CMOS or NMOS devices should be placed on a
grounded bench surface and operators should ground
themselves prior to handling devices, since a worker
can be statically charged with respect to the bench
surface. Wrist straps in contact with skin are strongly
recommended. See Figure 2.
Nylon or other static generating materials should not
come in contact with CMOS or NMOS circuits.
If automatic handling is being used, high levels of
static electricity may be generated by the movement
of devices, belts, or boards. Reduce static build-up by
using ionized air blowers or room humidifiers. All parts
of machines which come into contact with the top,
bottom, and sides of IC packages must be grounded
metal or other conductive material.
Cold chambers using C02 for cooling should be
equipped with baffles, and devices must be contained
on or in conductive material.
When lead-straightening or hand-soldering is
necessary, provide ground straps for the apparatus
used and be sure that soldering ties are grounded.
The following steps should be observed during wave
solder operations.
a. The solder pot and conductive conveyor system of
the wave soldering machine must be grounded to
an earth ground.
b. The loading and unloading work benches should
have conductive tops which are grounded to an
earth ground.
c. Operators must comply with precautions previously
explained.
d. Completed assemblies should be placed in antistatic containers prior to being moved to subsequent stations.
The following steps should be observed during board
cleaning operation.
a. Vapor degreasers and baskets must be grounded to
13.
14.
15.
16.
17.
an earth ground. Operators must likewise be
grounded.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor
degreaser immediately upon removal from the antistatic container.
d. Cleaned assemblies should be placed in antistatic
containers immediately after removal from the
cleaning basket.
e. High velocity air movement or application of
solvents and coatings should be employed only
when module circuits are grounded and a static
eliminator is directed at the module.
The use of static detection meters for line surveillance
is highly recommended.
Equipment specifications should alert users to the
presence of CMOS or NMOS devices and require
familiarization with this specification prior to performing any kind of maintenance or replacement of devices
or modules.
Do not insert or remove CMOS or NMOS devices
from test sockets with power applied. Check all power
supplies to be used for testing devices to be certain
there are no voltage transients present.
Double check test equipment setup for proper polarity
of voltage before conducting parametric or functional
testing.
Do not recycle shipping rails. Continuous use causes
deterioration of their antistatic coating.
RECOMMENDED FOR READING
"Total Control of the Static in Your Business"
Available by writing to'
3M Company
Static Control Systems
PO Box 2963
Austin, Texas 78769-2963
Or by Calling:
1-800-328- 1368
FIGURE 2 - TYPICAL MANUFACTURING WORK STATION
NOTES: 1. 1/16 inch conductive sheet stock covering bench top
work area.
2. Ground strap.
3. Wrist strap in contact with skin.
4. Static neutralizer. (ionized air blower directed at work.)
Primarily for use in areas where direct grounding
is impractical.
5. Room humidifier. Primarily for use in areas where the
relative humidity is less than 45%. Caution: building
heating and cooling systems usually dry the air causing
the relative humidity inside of buildings to be less than
outside humidity.
2-3
II
I
CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
prevent it.
Figure 3 shows the layout of a typical CMOS inverter and
Figure 4 shows the parasitic bipolar devices that are formed.
The circuit formed by the parasitic transistors and resistors is
the basic configuration of a silicon controlled rectifier, or
SCR. In the latch-up condition, transistors 01 and 02 are
turned on, each providing the base current necessary for the
other to remain in saturation, thereby latching the devices
on. Unlike a conventional SCR, where the device is turned
on by applying a voltage to the base of the NPN transistor,
the parasitic SCR is turned on by applying a voltage to the
emitter of either transistor. The two emitters that trigger the
SCR are the same point, the CMOS output. Therefore, to
latch up the CMOS device, the output voltage must be
greater than VOO + 0.5 Vdc or less than - 0.5 Vdc and have
sufficient current to trigger the SCR. The latch-up
mechanism is similar for the inputs.
Once a CMOS device is latched up, if the supply current is
not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below.
2.
3.
4.
5.
6.
1. Insure that inputs and outputs are limited to the maximum rated values, as follows:
FIGURE 3 -
-O.55Vin5VOO+O.5 Vdc referenced to VSS
-0.55Vout5VOO+0.5 Vdc referenced to VSS
IIinl510 mA
Iioutl5 10 mA when transients or dc levels exceed the
supply voltages.
If voltage transients of sufficient energy to latch up the
device are expected on the outputs, external protection diodes can be used to clamp the voltage. Another
method of protection is to use a series resistor to limit
the expected worst case current to the Maximum
Ratings values. See Figure 1.
If voltage transients are expected on the inputs, protection diodes may be used to clamp the voltage or a
series resistor may be used to limit the current to a
level less than the maximum rating of lin = 10 mA. See
Figure 1.
Sequence power supplies so that the inputs or outputs
of CMOS devices are not powered up first (e.g.,
recessed edge connectors may be used in plug-in
board applications and/ or series resistors).
Power supply lines should be free of excessive noise.
Care in board layout and filtering should be used.
Limit the available power supply current to the devices
that are subject to latch-up conditions. This can be accomplished with the power supply filtering network or
with a current-limiting regulator.
CMOS WAFER CROSS SECTION
N-Channel
P-Channel
Input
VDD
VDD
VSS
P-Channel
Output
Field Oxide
N - Substrate
FIGURE 4 -
P-ChannelOutput
P- Well
LATCH UP CIRCUIT SCHEMATIC
~
P - Well Resistance
::: :>--___--'vvv.--_p_+_N_-_~~-P----------P-~~ ¥A
( N%
N - Substrate Resistance
Q2
2-4
N-ChannelOutput
~VVSS
~
ss
CMOS ADCs/DACs
3-1
II
CMOS ADCs/DACs
Device
Number
II
Function
ADC
ADC Linear
Subsystem
DAC
Successive
Approximation
Register
Function
MCl4433
MCl4435
MCl4442
MCl4443
MCl4444
3% Digit AID Converter
Product Cancelled - See Other AI D Converters
Microprocessor-Compatible AI D Converter
6-Channel AID Converter Subsystem
Microprocessor-Compatible AI D Converter
MCl4447
MC14549B
MC14559B
MCl44110
MCl44111
6-Channel AID Converter Subsystem
Successive Approximation Register
Successive Approximation Register
Digital-to-Analog Converter with Serial Interface
Digital-to-Analog Converter with Serial Interface
MC145040
MC145041
Analog-to-Digital Converter with Serial Interface
Analog-to-Digital Converter with Serial Interface
On-Chip
Oscillator
8 Bits
Number
of Analog
Channels
11
8 Bits
11
3'1, Digit BCD
1
8 Bits
11
8 Bits
Device
Number
Number
of Pins
Successive
Approximation
MC145040
20
",
Successive
Approximation
MC145041
20
",
Dual Slope
MCl4433
24
Successive
Approximation
MCl4442
28
15
Successive
Approximation
MCl4444
40
8 to 10 Bits
6
Single Slope w/
Auto Zeroing
MCl4443
16
8 to 10 Bits
6
Single Slope wi
Auto Zeroing
MCl4447
16
Serial
[Compatible with
the Serial Peripheral
Interface (SPI)
on CMOS MCUs]
6 Bits
6
MCl44110
18
6 Bits
4
Emitter-Follower
Outputs
Emitter-Follower
Outputs
MCl44111
14
Serial or Parallel
:s8 Bits
Cascadable for
>8 Bits
MC14549B
16
:s8 Bits
Cascadable for
>8 Bits
MC14559B
16
I/O Format
Resolution
Serial
[Compatible with
the Serial Peripheral
Interface (SPI) on
CMOSINMOS MCUsl
Parallel
Parallel
3-2
Other Features
®
MC14433
MOTOROLA
3 Y2 DIGIT AI D CONVERTER
The MC14433 is a high performance, low power, 3Y:. digit AID converter combining both linear CMOS and digital CMOS circuits on a single monolithic IC. The
MC14433 is designed to minimize use of external components. With two external
resistors and two external capacitors, the system forms a dual slope AI D converter with automatic zero correction and automatic polarity.
The MC14433 is ratiometric and may be used over a full-scale range from 1.999
volts to 199.9 millivolts. Systems using the MC14433 may operate over a wide
range of power supply voltages for ease of use with batteries, or with standard 5
volt supplies. The output drive conforms with standard B-Series CMOS
specifications and can drive a low-power Schottky TTL load.
The high impedance MOS inputs allow applications in current and resistance
meters as well as voltmeters. In addition to DVM/DPM applications, the
MC14433 finds use in digital thermometers, digital scales, remote AI D, AI D control systems, and in MPU systems.
• Accuracy: ± 0.05% of Reading ± 1 Count
• Two Voltage Ranges: 1.999 V and 199.9 mV
• Up to 25 Conversionsls
• Zin> 1000 M ohm
• Auto-Polarity and Auto-Zero
• Single Positive Voltage Reference
• Standard B-Series CMOS Outputs- Drives One Low Power
Schottky Load
• Uses On-Chip System Clock, or External Clock
• Wide Supply Range: e.g., ±4.5 V to ±B.O V
• Overrange and Underrange Signals Available
• Operates in Auto Ranging Circuits
• Operates with LED and LCD Displays
• Low External Component Count
• See also Application Notes AN-769 and AN-nO
• Chip Complexity: 1326 FETs
BLOCK DIAGRAM
CMOS LSI
(LOW-POWER COMPLEMENTARY MOS)
II
3% DIGIT AID CONVERTER
L SUFFIX
CERAMIC PACKAGE
CASE 623
P SUFFIX
PLASTIC PACKAGE
CASE 709
ORDERING INFORMATION
MC14XXX
C
Suffix
Denotes
L
Ceramic Package
P
Plastic Package
20-23
00-03
BCD Data
16-19
DS1-DS4
Digit Strobe
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OR Overrange
DU
V ref Reference Voltage
CMOS
Analog
Subsystem
Control
Integrator
Conversion
3-3
VAG Analog Ground
Vx Analog Input
Offset
VDD=Pin 24
VSS=Pin 13
VEE= Pin 12
MC14433
MAXIMUM RATINGS
Symbol
Value
Unit
VDD to VEE
V
-05 to + 18
-O.!) to
VDD +0.5
V
V
lin
±10
TA
Tstg
-40 to +85
mA
DC
-65 to + 150
DC
Rating
DC Supply Voltage
Voltage, any pin, referenced to VEE
DC Input Current, per Pin
Operating Temperature Range
Storage Temperature Range
RECOMMENDED OPERATING CONDITIONS IVSS=O orVEE)
II
Symbol
Value
Unit
DC Supply Voltage - VDD to Analog Ground
VEE to Analog Ground
Parameter
VDD
VEE
+5.0 to +8.0
-2.8 to -8.0
Vdc
Clock Frequency
fClk
32 to 400
kHz
Zero Offset Correction Capacitor
Co
01 ±20%
/L F
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit. For proper
operation it is recommended that Yin and
Vout be constrained to the range
VEE~IVin or Vout)~VDD·
ELECTRICAL CHARACTERISTICS ICI=O.l /LF mylar, RI=470 kO@V re f=2000 V, RI=27 kO@V re f=200.0mV, Co =Ol /LF,
RC = 300 kO; all voltages referenced to Analog Ground, pin 1, unless otherwise indicated)
VOO
Characteristic
Symbol
Vdc
VEE
Vdc
-40°C
Min
Max
25°C
Min
Typ
85°C
Max
Min
Max
Unit
%rdg
Linearity-Output Reading INote 1)
IV re f=2000 V)
IV re f=2000 mY)
Stability - Output Reading
IVX=1990 mY, V re f=2000 mY)
5.0
-5.0
5.0
-5.0
-005
-1 Count
±0.05
+0.05
+ 1 Count
±005
5.0
-5.0
3*
LSD
Symmetry - Output Reading (Note 2)
IVref = 2.000 VI
5.0
-5.0
4*
LSD
Zero-Output Reading
IVX=O V, V re f=2000 V)
Bias Current - Analog Input
Reference Input
Analog Ground
5.0
-5.0
0
LSD
5.0
5.0
5.0
-5.0
-5.0
- 5.0
±20
±20
±20
± 100
± 100
±500
pA
5.0
-5.0
65
Common Mode Rejection (fclk = 32 kHz,
VX= 1.4 V, Vref=2.oo0 V)
Input Voltage* Pins9, 10
(VO=45 or 0.5 V)
IVO=90 or 1.0 VI
(VO= 13.5 or 1.5 VI
"0" Level
V
5.0
10
15
"1" Level
dB
VIL
2.25
4.5'0
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
VIH
3.5
7.0
11.0
VOL
VOH
VOL
VOH
5.0
5.0
5.0
5.0
-5.0
-5.0 4.95
-5.0
-5.0 4.95
Output Current - PinS 14 to 23
(VSS=OV)
IVOH=46VI Source
(VOL =0.4 V)
Sink
(VSS = - 5.0 V)
IVOH=45VI Source
(VOL = - 4.5 VI Sink
IOH
IOL
5.0
5.0
-5.0 -0.25
-5.0 0.64
IOH
IOL
5.0
5.0
- 5.0 -0.62
-5.0 1.6
Input Current - DU, Pin 9
IDU
5.0
-5.0
±03
±0.00001
±03
± 1.0
IQ
5.0
8.0
-5.0
-8.0
3.7
7.4
0.9
1.8
2.0
4.0
1.6
3.2
5.0
-5.0
Output Voltage - Pins 14 to 23
(VSS=O V)
"0" Level
"1" Level
(V SS = - 5.0 V) "0" Level
"1" Level
Quiescent Current
(VDD to VEE, ISS = 01
DC Supply Rejection
(VDD to VEE, ISS=O, V re f=2000 V)
3.5
7.0
11.0
2.75
5.50
8.25
5.0
10
15
(VO=05 or4.5 VI
(VO= 10 or 9.0 V)
(VO= 1.5 or 13.5 V)
3.5
7.0
11.0
V
0.05
0.05
0.05
4.95
-5.0
-5.0
5.0
-
-0.2
0.51
-0.36
0.88
-0.14
0.36
-
-
-0.5
1.3
-0.9
2.25
-0.35
0.9
-
4.95
4.95
4.95
-4.95
-4.95
4.95
mA
0.5
/LA
mA
mVIV
Notes 1 Accuracy - The accuracy of the meter at full scale is the accuracy of the setting of the reference voltage. Zero IS recalculated during
each conversion cycle. The meaningful specification is linearity. In other words, the deviation from correct reading for all inputs other
than positive full scale and zero is defined as the linearity specification.
2. Symmetry -- Defined as the difference between a negative and positive reading of the same voltage at or near full scale.
* Tighter tolerances are available. Consult Logic and Special Functions Product Marketing for details at (512) 928-6880.
* Referenced to VSS for Pin 9. Referenced to VEE for Pin 10
3-4
MC14433
TYPICAL CHARACTERISTICS
FIGURE 1 - TYPICAL ROLLOVER ERROR
versus POWER SUPPLY SKEW
FIGURE 2 - TYPICAL QUIESCENT POWER SUPPLY CURRENT
versus TEMPERATURE
4.0
1
1/
-
i--"'"
--
-!--
1
..
~
~
r-::..:: __
Voo = +5 V
NOTE' ROLLOVER ERROR IS HIE DIFFERNCE IN
OUTPUT READING FOR THE SAME ANALOG
INPUT SWITCHED FROM POSITIVE TO NEG·
ATIVE.
I
I
I
I
I
I
-4
-3
-1
-2
---
VEE' = -5 V
•
-
I
VEE=-8V
Voo = +B V
-40
-20
(IVDDI - IVEEP, SUPPLY VOLTAGE SKEW (VOLTS)
FIGURE 3 - TYPICAL N-CHANNEL SINK CURRENT
AT VOO-VSS = 5 VOL TS
-
1---r--
I
--+-
r-I-
o
20
40
TA, TEMPERATURE (DC)
80
60
FIGURE 4 - TYPICAL P-CHANNEL SOURCE CURRENT
AT VOO-VSS = 5 VOLTS
5. 0
-3. 0
0
~
f-
z
4da C
-400C_
3.0
/,V
cc
::::J
0
+25 0 C
/~
0
+B5° C -
// ~ ....
j)
--2.0
1/
.........:::
::::J
~
c::i
~
10
/
V
V
V
...... ~
+2~0 C
L--- ~ ~C
~
./
V
rr
I-- I--
/~V"
01P
01/
1.0
3.0
2.0
4.0
5.0
-1.0
VoS, DRAIN TO·SoURCE VOLTAGE (Vdc)
- 3.0
·2.0
4.0
5.0
VDS, DRAIN ·To·SoURCE VOLTAGE (Vdc)
FIGURE 5 - TYPICAL CLOCK FREQUENCY
versus RESISTOR IRC)
FIGURE 6 - TYPICAL % CHANGE OF CLOCK FREQUENCY
versus TEMPERATURE
4. 0
I! 11lt,
~
. Note
3.0
~
2.0
'"
1.0
""
0
>-
::::J
'~
~
~±5 V SUPPLY
~
~ ~1.0
""
u
a
~
---
-2.0
"""'-::::: ~8VSUPPLY
-
t-----
-.;::: t - -
--f--
NORMALIZED AT 25 0C
0
10 kl!
-4.0
1 MI!
100 kH
-40
20
RC, CLOCK FREQUENCY RESISTOR
CONVERSION RATE
MULTIPLEX RATE
CLOCK1~~~~UENCY + 1.5%
GLOCK FREQUENCY
80
3-5
20
40
TA, TEMPERATURE 10C)
60
80
MC14433
For Vx(max) = 200 mV
RI=28 kO (use 27 kO±5%)
PIN DESCRIPTIONS
ANALOG GROUND (VAG, Pin 1)
Analog ground at this pin is the input reference level for
the unknown input voltage (Vx) and reference voltage
(Vref). This pin is a high impedance input. The allowable
operating range for VAG is from VEE + 2.8 V to VDD
-4.5 V.
I
Note that for worst case conditions, the minimum
allowable value for RI is a function of C, min, VDD min, and
fClk max. The worst-case condition does not allow /). V + Vx
to exceed VDD. The 0.5 V factor in the above equation for
/).V is for safety margin.
OFFSET CAPACITOR (COl, C02; Pins 7,8)
REFERENCE VOLTAGE (Vref, Pin 2)
UNKNOWN INPUT VOLTAGE (VX, Pin 3)
This AI D system performs a ratiometric AI D conversion;
that is, the unknown input voltage, VX, is measured as a
ratio of the reference voltage, Vref. The full scale voltage is
equal to that voltage applied to Vref. Therefore, a full scale
voltage of 1.999 V requires a reference voltage of 2.000 V
while full scale voltage of 199.9 mV requires a reference
voltage of 200 mV. Both Vx and Vref are high impedance inputs. In addition to being a reference input, Pin 2 functions
as a reset for the AID converter. When Pin 2 is switched low
(referenced to VEE) for at least 5 clock cycles, the system is
reset to the beginning of a conversion cycle.
These pins are used for connecting the offset correction
capacitor. The recommended value is 0.1 JLF (polystyrene or
mylar).
DISPLAY UPDATE INPUT (DU, Pin 9)
If a positive edge is received on this input prior to the
ramp-down cycle, new data will be strobed into the output
latches during that conversion cycle. When this pin is wired
directly to the EOC output (Pin 14), every conversion will be
displayed. When this pin is driven from an external source,
the voltage should be referenced to VSS.
CLOCK (Clk I, Clk 0, Pins 10, 11)
The MCl4433 device contains its own oscillator system
clock. A Single resistor connected between pins 10 and 11
sets the clock frequency. If increased stability is desired,
these pins will support a crystal or LC circuit. The clock input, Pin 10, may also be driven from an external clock source
which need have only standard CMOS output drive. For external clock inputs this pin is referenced to VEE. A 300 kO
resistor results in clock frequency of about 66 kHz. (See the
typical characteristic curves.) For alternate circuits see
Figure 7.
EXTERNAL COMPONENTS (R" R,IC" C,; Pins 4,5,6)
These pins are for external components for the integration
used in the dual ramp AID conversion. A typical value for
the capacitor is 0.1 JLF (polystyrene or mylar) while the
resistor should be 470 kO for 2.0 V full scale operation and
27 kO for 200 mV full scale operation. These values are for a
66 kHz clock frequency which will produce a conversion time
of approximately 250 ms. The equations governing the
calculation for the values for integrator components are as
follows:
R,= Vx(max) x ~
C,
NEGATIVE POWER SUPPLY (VEE, Pin 12)
This is the connection for the most negative power supply
voltage. The typical current is 0.8 mAo Note the current for
the output drive circuit is not returned through this pin, but
through Pin 13. VX-VEE should be greater than 0.8 V.
/).V
/).V= VDD- Vx(max) -0.5 V
T =4000 x
~
fClk
NEGATIVE POWER SUPPLY FOR OUTPUT
CIRCUITRY AND INPUT DU (VSS, Pin 13)
This is the low voltage level for the output pins of the
MCl4433 (BCD, Digit Selects, £OC, OR) and the DU input.
When this pin is connected to analog ground, the output
voltage is from analog ground to VDD. When connected to
VEE, the output swing is from VEE to VDD. The allowable
operating range for VSS is between VOD -3.0 volts and
VEE·
where:
R, is in kO
VDD is the voltage at Pin 24 referenced to VAG
Vx is the voltage at Pin 3 referenced to VAG, In V
fClk is the clock frequency at Pin 10 in kHz
C, is in JLF, /).V is in Volts
T is the conversion time, in seconds
Example:
C,=O.l JLF
VDD=5.0 volts
fClk=66 kHz
For Vx(max)=2.0 volts
R,=480 kO (use 470 kO±5%)
END OF CONVERSION (EOC, Pin 14)
The EOC output produces a positive pulse at the end of
each conversion cycle. This pulse width is equivalent to one
half the period of the system clock (Pin 11).
3-6
MC14433
OVERRANGE (OR, Pin 15)
TRUTH TABLE (oS1 = 1)
The OR pin is low when Vx exceeds Vref. Normally it is
high.
Coded Condition
of MSD
03
01
02
00
BCD to 7 Segment
Decoding
1
1
1
0
Blank
1
0
1
0
Blank
1
1
1
1
+0 UR
Blank
-0 UR
1
1
1
0
Blank
1
0
0
+1
0
'0Hooke,
-1
....' 1} only
seg b
0
0
0
0
7 .... 1 and c to
1
1
1
+ lOR
0
-lOR
1
1
3-1 MSD
0
0
Notes for Truth Table.
03 - Y, digit, low for "1", high for "0"
02 - Polarity: "1" = positive, "0" = negative
00 - Out of range condition exists if 00 = 1. When used in conJunction with 03 the type of out of range condition is indicated, i.e., 03=0-OR or 03= l-UR
+0
DIGIT SELECT (oS4, OS3, OS2, OS1; Pins 16, 17, 18, 19)
-0
The digit select output is high when the respective digit is
selected. The most significant digit (Y2 digit) turns on immediately after an EOC pulse followed by the remaining
digits, sequencing from MSD to LSD. An interdigit blanking
time of two clock periods is included to ensure that the BCD
data has settled. The multiplex rate is equal to the clock frequency divided by 80. Thus with a system clock rate of 66
kHz, the multiplex rate would be 0.8 kHz. Relative timing
among digital select outputs and the EOC signal is shown in
the Digit Select Timing Diagram, Figure 8.
BCD DATA OUTPUTS (QO, Q1, 02, 03, Pins 20, 21, 22, 23)
Multiplexed BCD outputs contain 3 full digits of information during DS2, 3, 4, while during DS1, the 'h digit, over-
When only segment band c of the decoder are connected to the
y, digit of the display 4, 0, 7 and 3 appear as 1.
POSITIVE POWER SUPPLY (VDO, Pin 24)
The overrange indication (03 = 0 and 00= 1) occurs when the
count is greater than 1999, e.g., 1.999 V for a reference of 2.000 V.
The underrange indication, useful for autoranging circuits, occurs
when the count is less than 180, e.g, 0.180 V for a reference of
2.000 V.
The most positive supply voltage pin. VDD - Vx should be
greater than 2.5 V. VOD - VEE should be greater than 7.8 V.
VDD determines VOH for the digital outputs, and VIH for the
digital inputs.
Caution: If the most significant digit is connected to a display other
than a "1" only; such as a full digit display, segments other than b
and c must be disconnected. The BCD to seven segment decoder
must blank on BCD inputs 1010 to 1111.
range, underrange and polarity are available. The adjacent
truth table shows the formats of the information during DS 1.
FIGURE 7 -
ALTERNATE OSCILLATOR CIRCUITS
(a) Crystal Oscillator Circuit
(b) LC Oscillator Circuit
r -_ _.....--'-10~Clk I
. -_ _...._ _ _....-'1-=-\0 CJk J
c:=:=J
18 M
MCl4433
MCl4433
....----....,1~1 Clk 0
47 k
f=..!..
211' ~V
L/Ll.-
For L= 5 mH and C= O.Ol/LF, f,.,32 kHz
10 pF< Cl and C2<200 pF
FIGURE 8 -
EOC~ ~ Y,
'2/Lc
DIGIT SELECT TIMING DIAGRAM
nL...--_______
Clock Cycle
== 16,400 Clock Cycles
between EOC pulses
---i
i""1.{---....,.-t--118 Clock Cycles
DS1 (MSD)J
y, Digit
2 Clock Cycles
I
...l
L . ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
(BlankingTime)~
F
DS2-----------~·
'----------',
DS3------------------------~
DS4 _______________________- - J
(LSD)
3-7
--L
I
MC14433
FIGURE 9 -
INTEGRATOR WAVEFORMS AT PIN 6
Start
t
Time
Segment
Number
FIGURE 10 - EQUIVALENT CIRCUIT DIAGRAMS OF THE
ANALOG SECTION DURING SEGMENT 4
OF THE TIMING CYCLE
End
3
t
Typical Positive
Input Voltage
I
CIRCUIT OPERATION
grator amplifiers, is charged during this period. Also, the
integrator capacitor is shorted. This segment requires 4000
clock periods.
Segment 2 - The integrator output decreases to the comparator threshold voltage. At this time a number of counts
equivalent to the input offset voltage of the comparator is
stored in the offset latches for later use in the autozero process. The time for this segment is variable, and less than 800
clock periods.
Segment 3 - This segment of the conversion cycle is the
same as Segment 1.
Segment 4 - Segment 4 is an up-going ramp cycle with
the unknown input voltage (Vx) as the input to the integrator. Figure 10 shows the equivalent configuration of the
analog section of the MC14433. The actual configuration of
the analog section is dependent upon the polarity of the input voltage during the previous conversion cycle.
Segment 5 - This segment is a down-going ramp period
with the reference voltage as the input to the integrator.
Segment 5 of the conversion cycle has a time equal to the
number of counts stored in the offset storage latches during
Segment 2. As a result, the system zeros automatically.
Segment 6 - This is an extension of Segment 5. The time
period for this portion is 4000 clock periods. The results of
the AID conversion cycle are determined in this portion of
the conversion cycle.
The MC14433 CMOS integrated circuit, together with a
minimum number of external components, forms a modified
dual ramp AID converter. The device contains the
customary CMOS digital logic providing counters, latches,
and multiplexing circuitry as well as the CMOS analog circuitry providing operational amplifiers and comparators required to implement a complete single chip AID. Autozero,
high input impedances, and autopolarity are features of this
system. Using CMOS technology, an AID with a wide range
of power supply voltage and low power consumption is now
available with the MC14433.
During each conversion, the offset voltages of the internal
amplifiers and comparators are compensated for by the
system's autozero operation. Also each conversion 'ratiometrically' measures the unknown input voltage. In other
words, the output reading is the ratio of the unknown
voltage to the reference voltage with a ratio of 1 equal to the
maximum count 1999. The entire conversion cycle requires
slightly more than 16000 clock periods and may be divided into six different segments. The waveforms showing the conversion cycle with a positive input and a negative input are
shown in Figure 9. The six segments of these waveforms are
described below.
Segment 1 - The offset capacitor (Co), which compensates for the input offset voltages of the buffer and inte-
3-8
MC14433
FIGURE 11 - 3 Y, DIGIT VOLTMETER - COMMON ANODE DISPLAYS, FLASHING OVERRANGE
*RI=470 kO for 2 V Range
RI=27 kO for 200 mV Range
* * Mylar Capacitor
APPLICATIONS INFORMATION
The display uses an LED display with common anode digit
lines driven with an MC14543B decoder and an MC1413 LED
driver. The MC1413 contains 7 Darlington transistor drivers
and resistors to drive the segments of the display. The digit
drive is provided by four MPS-A 12 Darlington transistors
operating in an emitter follower configuration. The
MC14543B, MCl4013B and LED displays are referenced to
VEE via Pin 13 of the MCl4433. This places the full power
supply voltage across the display. The current for the display
may be adjusted by the value of the segment resistors shown
as 150 ohms in the above figure.
The power supply for the system is shown as a dual ± 5 V
supply. However, the MCl4433 will operate over a wide
range of voltages, and balance between the + 5 and - 5 V
supplies is not required. See the recommended operating
conditions and Figure 1.
3% DIGIT VOLTMETER - COMMON ANODE
DISPLAYS, FLASHING OVER RANGE
An example of a 3% digit voltmeter using the MCl4433 is
shown in the circuit diagram of Figure 11. The reference
voltage for the system uses an MC1403 2.5 V reference IC.
The full scale potentiometer can calibrate for a full scale of
199.9 mV or 1.999 V. When switching from 2 V to 200 mV
operation, RI is also changed, as shown on the diagram.
When using RC equal to 300 kO, the clock frequency for
the system is about 66 kHz. The resulting conversion time is
approximately 250 ms.
When the input is overrange, the display flashes on and
off. The flashing rate is one-half the conversion rate. This is
done by dividing the EOC pulse rate by 2 with Y, MC14013B
flip-flop and blanking the display using the blanking input of
the MC14543B.
3-9
MC14433
FIGURE 12 - 3'12 DIGIT VOLTMETER WITH LOW COMPONENT COUNT
t I
RI RI/CI
nput
+5
I
-
Vx
Zener Diode
or
MCl403
Reference
J-
1/
1\
r~CO2
CI COl
Clk I
Vx
J
~
C
1
MCl4433
DU
300 k
Clk 0
VAG
EOC
I
00
01
02
03
Vref
Resistor Network
or Individual Resistors
MC14511B
OR
vssiJ.
VDDI---VEEr-
A
B
C
D
+2LT
r~~s
BI
VDD
R
a
b
c
d
e
f
g
~ ~
DS3 DS2
OS4
OSl
ROp
for V re f=2.000 V
Vx: 1.999 V full scale
I
RM
VEE*
IMinus)
r Vref= 200.0 mV
Vx: 199.9 mV full scale
(change 470 kD to RI = 27 kD
and decimal point position)
+5V
I
Minus
Control
*V EE can range between - 2.8 and
11 V. Also see Figure 18 for
ne gative supply generated from a
po sitive supply.
I
- I BBB
I
I
I
Comma
Cathod
LED
Displa
517 MC1413
Digit Driver
Alternate Overrange Circuit
with Separate LED
OR1117MC14131r---l--~+5V
t~
choice of the designer, the values of resistors R, RM, ROp,
and RR that govern brightness are not given.
During an overrange condition the 3% digit display is
blanked at the BI pin on the MC14511 B. The decimal point
and minus sign will remain on during a negative overrange
condition. In addition, an alternate overrange circuit with
separate LED is shown.
3 Y2 DIGIT VOLTMETER WITH LOW COMPONENT
COUNT USING COMMON CATHODE DISPLAYS
The 3Y2 digit voltmeter of Figure 12 is an example of the
use of the MCl4433 in a system with a minimum of components. This circuit uses only 11 components in addition to
the MCl4433 to operate the MCl4433 and drive the LED
displays.
In this circuit the MC14511 B provides the segment drive
for the 3% digits. The MC1413 provides sink for digit current. (The MC1413 is a device with 7 Darlingtons with common emitters.) The worst case digit current is 7 times the
segment current at Y. duty cycle. The peak segment current
is limited by the value of R. The current for the display flows
from VDO (+ 5 V) to ground and does not flow through the
VEE (negative) supply. The minus sign is controlled by one
section of the MC1413 and is turned off by shunting the current through RM to ground, bypassing the minus sign LED.
The minus sign is derived from the Q2 output. The decimal
point brightness is controlled by resistor ROp. Since the
brightness and the type and size of LED display are the
3 Y2 DIGIT VOLTMETER WITH LCD DISPLAY
A circuit for a 3Y2 digit voltmeter with a liquid crystal
display is shown in Figure 13. Three MC14543B LCD latch/
decoder/display drivers are used to demultiplex, decode the
three digits, and drive the LCD. The half digit and polarity are
demultiplexed with the MC14013B dual D flip-flop.
Since the LCD is best driven by an ac signal across the
LCD, the low-frequency square wave drive for the LCD is
derived from the MC14024B binary counter which divides the
digit select output from the A/D. This low frequency square
wave is connected to the backplane of the LCD and to the individual segments through the combination of the output cir-
3-10
MC14433
FIGURE 13 - 3% DIGIT VOLTMETER WITH LCD DISPLAY
I
+V
-v
cuitry of the MC14543B and the exclusive OR gates at the
outputs of the MCl4013B. Alternatively the square wave can
be derived from a 50/60 Hz input signal when available.
The minus sign and the decimal point to the right of the
half digit are connected to the inverted low frequency square
wave signal. Unused decimal points are tied directly to the
low frequency square wave.
The system shown operates from two power supplies
(plus and minus). Alternatively one supply can be used when
VSS is connected to VEE. In this case a level must be set for
analog ground, VAG, which must be at least 2.8 V above
VEE. This circuit may be implemented with a resistor network, resistor/forward-biased diode network or resistorzener diode network. For example, a 9 V supply can be used
with 3 V between VAG and VEE, leaving 6 V for VOO to
V AG. This system leaves a comfortable margin for battery
degeneration (end of life). Two versions of this circuit for
Single supply operation is shown in Figure 14.
For panel meter operation from a single 5 V supply, a
negative supply can be generated as shown in Figure 18.
FIGURE 14 - TWO CIRCUITS FOR GENERATION
OF Vref AND VAG FROM A SINGLE SUPPLY
VDD
VDD
~---_-~Vref
Vref
4 Silicon Diodes
2.8 V
VAG to VEE'"' 2.8 V min
3-11
iii
!:
.,..,.....
(")
FIGURE 15 - 3% DIGIT AUTORANGING MUL TIMETER
VIN 0--
W
W
Common Anud .. LED D'Sl'i.JY
®ElE1B
v'"
.~
(
W,X. Y,Z Connect
cp
~
J\.)
"rn
Relays-ClareMR31A12
3 Position. 7 Pole (FunCllOn)
- 2 PositIOn. 2 Pole (AC-DC)
2 PO!'lttOn, f Pole (Hold!
All 2 Input NAND
All 4 Input NAND
All Inverters
MCl4011 B
MCl4012B
MCl4049UB
All Transmission Gates MCl4066B
I
I
MC14433
PARALLEL BCD DATA OUTPUT CIRCUIT
The output of the MCl4433 may be demultiplexed to produce parallel BCD data as shown in Figure 16. Two levels of
latches are required for a complete demultiplexing of the
data since the outputs of the MC14042B latches change sequentially with the DS1 to DS4 strobe pulses. To key output
validity to one leading edge, i.e., that of the EOC signal of
the MCl4433, information is transferred to the second set of
latches (MC14175B latches). A single set of latches can be
used when reading of output is restricted to within 12,000
clock pulses after EOC. This requires synchronous system
operation with respect to the BCD data bus.
In this system the output ground level is VSS. In most
cases, a two supply system with VSS connected to VAG is
recommended. This allows connecting analog ground and
digital ground together without destroying a power supply.
This circuit works well with that of Figure 12.
3% DIGIT AUTORANGING MULTIMETER
An autoranging multimeter including ac and dc voltage
ranges from 200 mV to 200 V, ac and dc current from 2 mA
to 2 A fullscale and resistance ranges from 2 kO to 2 MO fullscale is shown in Figure 15. In this multimeter only two input
jacks are required for all ranges and functions, eliminating
the need for changing leads on the instrument when changing ranges or functions. Although only four ranges are provided for each function, the technique used may be expanded to more ranges if desired. Range switching uses
mechanical relays. However, the relays may be replaced with
solid state analog switches.
The MCl4433 provides the overrange and underrange
control signals for the automatic ranging circuits. For additional information, see Motorola Application Note AN-769,
"Autoranging Digital Multimeter Using the MCl4433 CMOS
AI D Converter."
FIGURE 16 -
DEMULTIPLEXING FOR MC14433 BCD DATA
Multiplexed
BCD
DS1 DS2
DS3 DS4
Ii
1
I I
00 01 02 03
o- Pal
-
~
1
C MC14042B Pol
I
I I
Voo
00 01 02 03
MC14042B C
I I
00 01 02 D3
00 01 02 03
Pol
MC14042B
C f--
~
C MC14042B Pol I--VO D
00 01 02 03
00 01 02 03
00 01 02 03
00 01 02 03
I I
02 03
I I
02 03
I I
D2 D3
00 D1 02 D3
00 01
VD D-R
I
I
I I
MC14175B
00 01 02 03
00 01
C-
1 LJ 1
VOD
_
-R
MC14175B
00 D1
C
-
VDD-R
MC14175B
I I
Cf--
00 01 02 03
00 01 02 03
111 1
1 11 1
VO~ R
MC14175B
CI--
00 01 02 03
1 tJ 1
EOC
3-13
II
MC14433
FIGURE 17 -
CHANNEL DATA ACQUISITION HARDWARE
r---------------------~----------------------_.------------------+5
.----------+-------------------5
,..-------------- IRQ
.-------Restart
,..-------R/W
GNO
Co
AG
MCl4433
VOO
II
X7
OS4
OS3
OS2
OSl
03
02
01
00
Vx
Clk 0
X
300 k
X6
Clk I
VSS
X5
OU
VCC IROA
PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBO
EOC
CBl
CB2
+5V
+5V
+5V
PA7
10k
PA6
X3
PA5
+5
PA4
X2
PA3
Xl
Cr-~--~---~----------------------~ PA2
Br-----~--~r_------------------~ PAl
PAO
XO ~
Ar-------------~----------------------~
CSO
VEE ~ lNH
Analog
E
VSS
",2
GNO
07
06
05
04
MC6821
X4
4
R/W
Data
ToM C6800
Bus
System
03
02
01
DO
CAl
~
t'l
Inputs
-5
Address
}
8 CHANNEL DATA ACQUISITION NElWORK
nel to be measured via the MCl4051 B analog multiplexer.
Control lines CB1 and CB2 are used for data flow control and
are connected to DU and EOC of the MCl4433.
A more detailed explanation of this system including the
actual software required for the M6800 microprocessor may
be found in Motorola Application Note AN-nO, "Data Acquisition Networks With NMOS and CMOS."
Figure 17 shows an 8-channel data acquisition network using the MCl4433 and an MC6800 microprocessor system.
The interface between the microprocessor data bus and the
AID system is done with an MC6821 PIA. One half of the
PIA is used with the BCD and digit select outputs of the
MCl4433, while the second half of the PIA selects the chanFIGURE 18 -
Bus
NEGATIVE SUPPLY GENERATED FROM POSITIVE SUPPLY
116 MC14049UB
NEGATIVE SUPPLY GENERATED FROM POSITIVE
SUPPLY
VDD=5 V
vSS=o V
When only + 5 V is available, a negative supply voltage
can be generated with the circuit of Figure 18 using one
MCl4049UB. Two inverters from CMOS hex inverter are
used as an oscillator (=3 kHz) with the remaining inverters
used as buffers for higher current output. The square wave
output from the oscillator is level-translated to a negative going signal. This signal is rectified and filtered. A VDD voltage
of + 5 V for the hex buffer will result in a - 4.3 V no load output voltage while the output with a 2 mA load is =3.4 V.
510 K
3-14
®
MC14435
MOTOROLA
3-1/2 DIGIT AID LOGIC SUBSYSTEM
CMOS LSI
(LOW-POWER COMPLEMENTARY MOS)
The MC14435 AID Logic is designed specifically for use in
a dual-slope integration AID converter system.
The device consists of 3-112 digits of BCD counters, 13 memory
latches, and output multiplexing circuitry. An internal clock oscillator is provided to generate system timing and to set the output
multiplexing rate. A single capacitor is required to set the oscillator
frequency.
3-1/2 DIGIT AID LOGIC
SUBSYSTEM
•
On-Chip Clock to Control Digit Select, Multiplexing, and BCD
Counters Simultaneously
•
Multiplexed BCD Output
•
Built-In 100-Count Delay for Accurate System Conversion of
Low-Level Inputs
•
System Over-Range Output
•
Linear Companion Device Available From Motorola
(MC1405L/1505L)
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc (MC14435 EFLlFLlFP)
= 3.0 Vdc to 6.0 Vdc (MC14435EVL!VL! VP)
L SUFFIX
C'=RAMIC PACKAGE
CASE 620
P SUFFIX
MAXIMUM RATI NGS (Voltages referenced to VSS Pin 8.)
PLASTIC PACKAGE
Rating
Symbol
DC Supply Voltage
Value
- MC14435EFL!FL!FP
- MC14435EVL!VL!VP
Input Voltage, All Inputs
CASE
648
+18to-0.5
+6.0 to -0.5
Vin
DC Current Drain per Pin
Unit
Vdc
VDD
VDD +0.5
to VSS -0.5
Vdc
I
10
mAdc
Operating Temperature Range MC14435EFL!EVL
MC14435F L!FPIVL!VP
TA
-55 to +125
-40 to +85
°c
Storage Temperature Range
T stg
-65 to +150
°c
PRODUCT CANCELLED
Refer to Other AI D Converters Listed
in the Function Selector Guide of This
Book
3-15
PIN ASSIGNMENT
DS3
V OD
16
DS1
DS2
15
C1
00
14
C2
01
13
Camp
02
12
au
03
11
RC
1/2 D
10
VSS
OR
II
®
MC14442
MOTOROLA
CMOS LSI
(LOW-POWER SILICON GATE
COMPLEMENTARY MOS)
ANALOG-TO-DIGITAL CONVERTER (ADC)
II
The MC14442 ADC is a 28-pin bus-compatible 8-bit AID converter
with additional digital input capability. The device operates from a
single 5 V supply and provides direct interface to the MPU data bus
used with all Motorola M6800 family parts. It performs an 8-bit conversion in 32 machine cycles and allows up to 11 analog inputs. In addition,
the part can accept up to 6 digital inputs. These inputs are designed to
be either analog or digital inputs. All necessary logic for software configuration, channel selection, conversion control an<;l bus interface is included.
•
•
MICROPROCESSOR-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTER
Direct Interface to M6800 Family MPUs
Dynamic Successive Approximation AID
• 32 P.s Conversion at fE = 1.0 MHz
• Ratiometric Conversion
• Completely Programmable
• Completely Software Compatible with the MC14444 ADC
• 5 Dedicated Analog Inputs
• 6 Inputs Usable for Either Analog or Digital Signals
• Completely TTL Compatible Inputs at Full Speed with Supply
Voltage of 5 V ± 10%
ORDERING INFORMATION
MC14XXXt~
Suffix Denotes
Ceramic Package
Plastic Package
BLOCK DIAGRAM AND PIN ASSIGNMENT
VAG
Vref
11
11
ANO
AN2-AN5
PO-P5
Vref
VDD
Po-P5
4
SC
AND
D6
AN2
D5
AN3
D4
AN4
D3
AN5
D2
Analog
Data
Register
(Read Only)
D1
PlIAN111
DO
P2(AN81
P3(AN91
4
AO-3
00-07
Digital
Data
Register
(Read Only)
8
R/IN
D7
8
Control
~~~~~------------------~~-----------------'
3-16
RS1
CS
13
14
""L-_
_ _ _--rReset
MC14442
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +6.5
V
DC Input Voltage (Referenced to VSS)
-0.5 to VCC+0.5
V
DC Output Voltage (Referenced to VSS)
-0.5 to VCC+0.5
V
DC Input Current, per Pin
±10
mA
lout
DC Output Current per Pin
±10
mA
100
DC Supply Current, VDD and VSS Pins
±20
mA
500
mW
VDD
DC Supply Voltage (Referenced to VSS)
Yin
V out
lin
Power Dissipation, per Package t
PD
Storage Temperature
Tstg
TL
Lead Temperature (10-Second Soldering)
-65 to + 150
°C
300
°C
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid applications of any voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation it is
recommended that Yin and V out be constrained to the range V SS s (Vin or
Vout)SVDD·
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VDD)
* Maximum Ratings are those values beyond which damage to the device may occur.
tPower Dissipation Temperature Derating:
Plastic "P" Package: -12mW/oC from 65°C to 85°C
Ceramic "L" Package: no derating
DC ELECTRICAL CHARACTERISTICS (VDD=5.0 V ± 10%, VSS = 0 V, TA = -40°C to 85°C unless otherwise noted)
I
Characteristic
I Symbol I
Conditions
I
Min
I
Max
Unit
Bus Control Inputs (R/W, Enable, Reset, RS1, CS)
Input High Voltage
Input Low Voltage
Input Leakage Current
Vin=O to 5.5 V
Data Bus (00-D7)
Input High Voltage
-
V
-
0.8
V
-
± 10
p.A
2.0
Input Low Voltage
VIH
V IL
Three-State (Off State) Input Leakage Current
ITSI
Output High Voltage
VOH
VDD=5.5 V,
VSSsVinsVDD
IOH= -1.6 mA
Output Low Voltage
VOL
IOL = 1.6 mA
2.4
-
-
V
0.4
V
V
Penpherallnputs (PO-P5)
Input High Voltage
VIH
2.0
-
Input Low Voltage
VIL
-
0.8
V
Input Leakage Current
lin
-
± 1.0
p.A
VDD=5.5 V,
VSSsVinsVDD
Current ReqUirements
Supply Current
VDD=5.5 V
Input Current, Vref
Vref-4.5 to 5.5 V
ANALOG CHARACTERISTICS (T A = -40°C to 85°C)
Characteristic
Description
Analog Multiplexer
Leakage Current
Leakage current between all deselected analog inputs and any selected
analog input with all analog input voltages between VSS and VDD
AID Converter (VSS=O V, VAG=O V, 4.5 VsVrefsVDDs5.5 V)
Resolution
Number of bits resolved by the AID
8
-
Bits
Nonlinearity
Maximum deviation from the best straight line through the AID transfer
characteristic
-
± y,
LSB
Zero Error
Difference between the output of an ideal and an actual AI D for zero
input voltage
-
±v,
LSB
Full-Scale Error
Difference between the output of an ideal and an actual AID for full-scale
input voltage
-
±v,
LSB
Total Unadjusted Error
Maximum sum of Nonlinearity, Zero Error, and Full-Scale Error
-
±v,
LSB
Quantization Error
Uncertainty due to converter resolution
-
± y,
LSB
Absolute Accuracy
Difference between the actual input voltage and the full-scale weighted
equivalent of the binary output code, all error sources included
-
±10
LSB
Conversion Time
Total time to perform a single analog-ta-digital conversion
-
32
E cycles
Sample Acquisition Time
Time required to sample the analog input
-
12
E cycles
3-17
II
MC14442
AC CHARACTERISTICS (T A = -40° to 85°C) (See Figure 1)
Characteristic
Signal
Symbol
Min
Max
Unit
Enable Clock Cycle Time (lifE)
E
943
E
440
Enable Clock Pulse Width, Low
E
PWUE)
410
-
ns
Enable Clock Pulse Width, High
tcyC(E)
PWH(E)
Clock Rise Time
E
tdE)
-
25
ns
Clock Fall Time
E
tf(E)
-
30
ns
RS1, R/W, CS
tAS
145
-
ns
Data Delay (Read)
00-07
tOOR
-
335
ns
Oata Setup (Write)
00-07
tosw
185
-
ns
Address Hold Time
RS1, R/W, CS
00-07
tAH
10
-
ns
tOHW
10
-
ns
Output Data Hold Time
00-07
tOHR
10
-
ns
Input Capacitance
PO-P5,
Cin
-
55
pF
-
15
-
15
Address Setup Time
II
Input Data Hold Time
ns
ns
ANO-AN10,
R/W, E, RS1,
CS, RESET
Three-State Output Capacitance
00-07
Cout
pF
FIGURE 1 - BUS TIMING
~----------------tcyC(E) ----------------~
~------ PWUE) ------~..
~I " " . . . - - - - - - - PWHIE)-------+-I
2.0
0.8
tAS
R/W,
-----l~
2.0V
CS,
RS1
0.8V
tOOR
2.4
2.4
MPU
Read
00-07
0.4
0.4
tOHW
2.0
MPU
Write
2.0
00-07
0.8
3-18
0.8
MC14442
PIN FUNCTIONS
Pin No.
MC14442 MPU INTERFACE SIGNALS
Function
Pin Name
1
VAG
A/D Converter Analog Ground
Type
Supply
Supply
Digital Ground
2
VSS
3
07
Data Bus Bit 7 (MSB)
I nput/ Output
4
06
Data Bus Bit 6
Input/Output
5
05
Data Bus Bit 5
Input/Output
6
04
Data Bus Bit 4
Input/ Output
7
03
Data Bus Bit 3
Input/Output
8
02
Data Bus Bit 2
Input/Output
9
01
Data Bus Bit 1
Input/ Output
10
DO
Data Bus Bit 0 (LSB)
Input/ Output
11
R/W
12
E
13
RS1
Input
Register Select
Input
Chip Select
Input
Input
P5(AN7)
Digital Port or Analog Channel 7
Input
17
P4(AN6)
Digital Port or Analog Channel 6
Input
18
P3(AN9)
Digital Port or Analog Channel 9
Input
19
P2(AN8)
Digital Port or Analog Channel 8
Input
20
Pl(ANl1)
Digital Port or Analog Channel 11
Input
Digital Port or Analog Channel 10
Input
CS
Reset
16
Enable Clock (E) - The enable clock provides two functions for the MCl4442. First, it serves to synchronize data
transfers into and out of the ADC. The timing of all other external signals is referenced to the leading or trailing edge of
the enable clock. Secondly, the enable clock is used internally to derive the necessary SAR AID conversion clocks.
Because this conversion is a dynamic process, enable clock
must be a continuous signal into the ADC during an AI D
conversion.
Input
Read/Write
Enable Clock (<1>2)
Reset
14
15
Bidirectional Data Bus (DO-07) - The bidirectional rj;JliJ
lines DO-D7 comprise the bus over which data is transferred
in parallel to and from the MPU. The data bus output drivers
are three-state devices that remain in the high-impedence
state except during an MPU read of an ADC data register
21
PO(ANlO)
22
AN5
Analog Channel 5
Input
23
AN4
Analog Channel 4
Input
24
AN3
Analog Channel 3
Input
25
AN2
Analog Channel 2
Input
26
ANO
Analog Channel 0
27
VDD
Supply Voltage
28
Vref
A/D Converter Positive Reference
Voltage
ReadlWrite (R/W) - The R/W signal is provided to the
MCl4442 to control the direction of data transfers to and
from the MPU. A low state on this line is required to transfer
data from the MPU to the ADC control register. A high state
is required on R/W to transfer data out of either of the AOC
data registers.
Reset (Reset) - The reset line supplies the means of
externally forcing the MCl4442 into a known state. When a
low is applied to the Reset pin, the start conversion bit of
the control register is cleared. Analog channel 0 is
automatically selected by the analog multiplexer. The AID
status bit is also cleared. Any AI D results present in the
Analog Data register are not affected by a reset. Reset forces
the data bus output drivers to the high-impedance state. The
internal byte pointer (discussed in the following pages) is set
to point to the most significant byte of any subsequently
selected internal register. In order to attain an internally
stable reset state, the Reset pin must be low for at least one
complete enable clock cycle.
Input
Supply
Input
Chip Select (CS) - Chip select is an active-low input used
by the MPU system to enable the ADC for data transfers. No
data may be passed to or from the ADC through the data bus
pins unless CS is in a low state. A selection of MPU address
lines and the M6800 VMA signal or its equivalent should be
utilized to provide chip select to the MCl4442.
MC14442 ANALOG INPUTS AND DIGITAL INPUTS
(Refer to the ADC Block Diagram)
Dedicated Analog Channels (ANO. AN2-AN5) - These
input pins serve as dedicated analog channels subject to AID
conversions. These channels are fed directly into the internal
12-to-1 analog multiplexer which feeds a single analog
voltage to the AID converter.
Shared Analog Channels (AN6-AN11) - These input pins
are also connected to the analog multiplexer and may be
used as analog channels for AID conversion. However.
these pins may also serve as digital input pins as described
next.
3-19
II
MC14442
II
Shared Digital Inputs (PO-P51 - PO-P5 comprise a 6-bit
digital input port whose bits may also serve as analog channels. The state of these inputs may be read at any time from
the ADC digital data register. The function of these pins is
not programmed, but instead is simply assigned by the
system designer on a pin-by-pin basis.
may be degraded if VAG is wired to VSS at the AOC
package unless VSS has been sufficiently filtered to remove
switching noise. Ideally V AG should be single-point grounded to the system analog ground supply.
CAUTION: Digital values read from the PO-P5 bit
locations do not guarantee the presence of true digital input levels on these pins. PO-P5 pass through a
TTL-compatible input buffer and into the digital data
register. These buffers are designed with enough
hysteresis to prevent internal oscillations if an analog
voltage between 0.8 and 2 V is present on one or
more of these six pins.
The MCl4442 ADC has three 16-bit internal registers. Each
register is divided into two 8-bit bytes: a most significant
(MS) byte (bits 8-151 and a least significant (LS) byte (bits
0-7). Each of these bytes may not be addressed externally,
but instead are normally addressed by a single 16-bit instruction such as the M6800 LDX instruction. An internal byte
pointer selects the appropriate register byte during the two E
cycles of a normal 16-bit access. In keeping with the M6800
X register format, the pointer points first to the MS byte of
any selected register. After the E cycle in which the MS byte
is accessed, the pointer will switch to the LS byte and remain
there for as long as chip select is low. The pointer moves
back to the MS byte on the falling edge of E after the first
complete E cycle in which the AOC is not selected. (See
Figure 2a for more detail.) The MS byte of any register may
also be accessed by a simple 8-bit instruction as shown in
Figure 2b. However, the LS byte of all registers may be
accessed only by 16-bit instructions as described above. By
connecting the ADC register select (AS1) to the MPU
address line A 1, the three registers may be accessed sequentially by 16-bit operations.
MC14442 INTERNAL REGISTERS
MC14442 SUPPLY VOLTAGE PINS
Positive Supply Voltage (VDOI - VOO is used internally
to supply power to all digital logic and to the chopper
stabilized comparator. Because the output buffers connected to this supply must drive capacitive loads, ac noise on
this supply line is unavoidable internally. Analog circuits using this supply within the MCl4442 were designed with high
VDO supply rejection; however, it is recommended that a
filtering capacitance be used externally between VOD and
VSS to filter noise caused by transient current spikes.
Ground Supply Voltage (VSS) - VSS should be tied to
system digital ground or the negative terminal of the VOD
power source. Again, the output buffers cause internal noise
on this supply, so analog circuits were designed with high
VSS rejection.
CAUTION: RSl should not be connected to
address line AO and the addressing of the ADC
should be such that RSl does not change states
during a 16-bit access.
Positive AID Reference Voltage (Vref) - This is the
voltage used internally to provide references to the analog
comparator and the digital-to-analog converter used by the
SAR AID. The analog-to-digital conversion result will be
ratiometric to Vref- VAG (full scale). Hence Vref should be a
very noise-free supply. Ideally Vref should be Single-point
connected to the voltage supply driving the system's
transducers. Vref may be connected to VDD, but degradation of absolute AID accuracy may result due to switching
noise on VDD.
INTERNAL REGISTER ADDRESSING
Addressing Signals
AID Ground Reference Voltage (VAG) - This supply is
the ground reference for the internal OAC and several
reference voltages supplied to the comparator. It should also
be noise-free to guarantee A/O accuracy. Absolute accuracy
3-20
Reset
CS
R/W
RSl
0
X
X
X
Reset
1
0
0
0
No Response
1
0
0
1
MPU Write to Control Register
1
0
1
0
MPU Read from Analog Data
Register
1
0
1
1
MPU Read from Digital Data
Register
1
1
X
X
Chip Deselected (No Response)
ADC Response
MC14442
FIGURE 2 -
ADC ACCESS TIMING
a - Typical 16-Bit ADC Access
II
RS1,
R/W
Byte Pointer
Reset to MS Byte
b - Typical 8-Bit ADC Access
Select
MS Byte
3-21
MC14442
MCl4442 CONTROL REGISTER
(Write Only)
15
o
X
(MSBl
AO
(LSBl
~------8-Bit Write------~
~---------------16-Bit Write---------------~
II
Analog Multiplexer Address (AO-A3) - These four
address bits are decoded by the analog multiplexer and used
to select the appropriate analog channel as shown below.
will begin immediately after the completion of the control
register write.
Unused Bits (X) - Bits 4-7 and 9-15 of the ADC Control
Register are not used internally.
Hexadecimal Address 1A3 = MSB)
Select
o
ANa
1
Vref
2-5
6-B
AN2-AN5
AN6-ANll
C-F
Undefined
NOTE: A 16-bit control register write is required to change
the analog multiplexer address. However, 8-bit writes to the
MCl4442 can be used to initiate an AI D conversion if the
analog MUX is already selecting the desired channel. This is
useful when repeated conversions on a particular analog
channel are necessary.
Start AID Conversion (SC) - When the SC bit is set to a
logical 1, an AID conversion on the specified analog channel
MCl4442 ANALOG DATA REGISTER
(Read Only)
a
15
EOC
(MSBl
RO
(LSBl
1+------8-8it Read------~
,....---------------16-Bit
Read---------------~
AID Result (RO-R7) - The LS byte of the analog data
register contains the result of the AID conversion. R7 is the
MSB, and the converter follows the standard convention of
assigning a code of $FF to a full-scale analog voltage. There
are no special overflow or underflow indications.
bit is cleared by either an 8-bit or a 16-bit MPU write to the
ADC control register. The r.emainder of the bits in the MS
byte of the analog data register are always set to a logical 0
to simplify MPU interrogation of the ADC status. For example, a Single M6800 TST instruction can be used to determine
the status of the AI D conversion.
AID Status (EOC) - The AID status bit is set whenever a
conversion is successfully completed by the ADC. The status
MCl4442 DIGITAL DATA REGISTER
(Read Only)
o
o
15
P5
~------8-Bit Read------~
~----------------16-BitRead--------------------~
Logical Zero (0) zero.
These bits are always read as logical
Shared Digital Port (PO-P5) - The voltage present on
these pins is interpreted Be; Cl digital signal and the corresponding states are read from these bits.
WARNING: A digital value will be given for each pin even
if some or all of the pins are being used as analog inputs.
Analog Multiplexer Address (AO-A3) - The number of the
analog channel presently addressed is given by these bits.
3-22
MC14442
ANALOG SUBSYSTEM
(See Block Diagram)
2 enable clock cycles for the write into the control register
even if only one byte is written. In this case, the second E
cycle does not affect any internal registers. During the next
121> enable cycles following a write command, the analog
multiplexer channel is selected and the analog input voltage
is stored on the sample and hold DAC. It is recommended
that an input source impedance of 10 KG or less be used to
allow complete charging of the capacitive DAC.
During cycle 13 the AID is disconnected from the
multiplexer output and the successive approximation AI D
routine begins. Since the analog input voltage is being held
on an internal capacitor for the entire conversion period, it is
required that the enable clock run continuously until the AI D
conversion is completed. The new 8-bit result is latched into
the analog data register on the rising edge of cycle 32. At this
point the end of conversion bit (EOe) is set in the analog
data register MS byte. (See Figure 3, AID Timing
Sequence.)
General Description
The analog subsystem of the MCl4442 is composed of a
12-channel analog multiplexer, an 8-bit capacitive DAC
(digital-to-analog converted, a chopper-stabilized comparator, a successive approximation register, and the
necessary control logic to generate a successive approximation routine.
The analog multiplexer selects one of twelve channels and
directs it to the input of the capacitive DAC. A fullycapacitive DAC is utilized because of the excellent matching
characteristics of thin-oxide capacitors in the silicon-gate
CMOS process. The DAC actually serves several functions.
During the sample phase, the analog input voltage is applied
to the DAC which acts as a sample-and-hold circuit. During
the conversion phase, the capacitor array serves as a digitalto-analog converter. The comparator is the heart of the
ADC; it compares the unknown analog input to the output of
the DAC, which is driven by a conventional successiveapproximation register. The chopper-stabilized comparator
was designed for low offset voltage characteristics as well as
VDD and VSS power supply rejection.
NOTE: The digital data register or the analog data register
may be read even if an AI D conversion is in progress. If the
analog data register is read during an AID conversion, valid
results from the previous conversion are obtained. However,
the EOC bit will be clear (logic 0) if an AID conversion is in
progress.
Device Operation
An AID conversion is initiated by writing a logical 1 into
the SC bit of the ADC control register. The MCl4442 allows
FIGURE 3 -
MPU Write
ToADC
Control
Register
Sample Analog Input
~ ~llnput Should Be Stablel
1
2
3
4
5 6
7 8
AID TIMING SEQUENCE
.1...
SAR AID Conversion
.1
9 10 11 12 13 14 15 16 1718 19 20 21 22 2324 2526 27 28 29 3031 32
R/IN
RS1
Analog Data
Register IRO-R7
Valid Data F~om Previous Conversion IEOC Cleared)
and EOC)
------1___- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -.......'1'- Valid.
EOC--1
3-23
11
MC14442
FIGURE 4 - TYPICAL MC14442 APPLICATION IN A CLIMATE CONTROLLER
ROM
I
Latch/
Decoder/
Driver
...- - - - - - - -....- - - - - - v r e f
MC6802
MPU
MCl4442
ADC
~----~~--r---------VAG
Heat/AC
Control
MC6821
PIA
Duct
Damper
Control
3-24
MC14443
MC14447
@ MOTOROLA
CMOS MS.
ANALOG-TO-DIGITAL CONVERTER
LINEAR SUBSYSTEM
(LOW-POWER COMPLEMENTARY MOS)
The MCl4443 and the MCl4447 are 6-channel, single-slope, 8-10 bit
analog-to-digital converter linear subsystems for microprocessor-based
data and control systems. Contained in both devices are a one-of-8
decoder, an 8-channel analog multiplexer, a buffer amplifier, a precision
voltage-to-current converter, a ramp start circuit, and a comparator.
The output driver of the MCl4443's comparator is an open-drain
N-channel which provides a sinking current. The output driver of the
MCl4447's comparator is a standard B-Series P-Channel, N-Channel
pair.
A processor system (such as the MC141000 or MC146805) provides
the addressing, timing, counting, and arithmetic operations required for
implementing a full analog-to-digital converter system. A system made
up of a processor and the linear subsystem has features such as
automatic zeroing and variable scaling (weighting) of six separate
analog channels.
• Quiescent Current 0.8 mA Typical at VDD = 5 V
MICROPROCESSOR-BASED
ANALOG-TO-DIGITAL
CONVERTER
~.,..
J"fu~)l~
uu
"rmrrn ~ I
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
PLASTIC PACKAGE
CASE 620
CASE 648
• Single Supply Operation +4.5 to + 18 Volts
ORDERING INFORMATION
• Direct Interface to CMOS MPUs
• Typical Resolution - 8 Bits
b
MC14XXX
• Typical Conversion Cycle as Fast as 300 ~s
• Ratio Metric Conversion Minimizes Error
• Analog Input Voltage Range: VSS to VDD - 2 V
• Chip Complexity: MCl4443 MCl4447 -
Suffix
Denote.
L
Ceramic Package
P
PlastiC Package
150 FETs
151 FETs
BLOCK DIAGRAM
PIN ASSIGNMENT
15
Ch1
Ramp Start
Ch2
Ch3
Ch4
Ch5
Ch6
Ref
Voltage
AO
A1
3
13
12
11
10
16
.,
.,x
15
14
."a.
4
~
13
12
11
.--_ _ _ _ _-1~--~--=-6 Ref Cu rrent
Set
Voo
~
Pin 14
VSS ~ Pin 5
A2
3-25
10
E
MC14443, MC14447
MAXIMUM RATINGS (Voltages referenced to Vssl
Rating
Symbol
Value
Unit
V
VDD
-0.5 to + 18
Input Voltage. All Inputs
Yin
-0.5 to VDD+0.5
V
DC Input Current. per Pin
lin
± 10
DC Supply Voltage
Operating Temperature Range
Storage Temperature Range
TA
-40 to +85
mA
DC
Tstg
-65 to + 150
DC
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however.
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit. For proper
operation it is recommended that Yin and
V out be constrained to the range VSS .;;
(Vin or V out )';; VDD.
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSSI
I
Characteristic
Output Voltage- Comparator
Yin @ Pin 4==0 V
"0" Level
Symbol
VOD
V
VOL
5.0
-40°C
Min
Max
0.05
0.05
0.05
10
15
Vin@ Pin4== 1.0V
(Rpullup== 10 kf!. MCl4443 onlyl
Input Voltage-Address. Ramp Start
(VO==4.5 or 0.5 VI
(VO==9.0 or 1.0 V)
(VO== 13.5 or 1.5 VI
"1" Level
VOH
10
15
"0" Level
"1" Level
Yin @ Pin 4=0 V
(VOL =OA VI
(VOL ==0.5 VI
1VOL=1.5VI
4.95
9.95
14.95
4.95
9.95
14.95
85°C
Typ
Max
0.01
0.01
0.01
0.05
0.05
0.05
4.99
9.99
14.99
Min
Max
Unit
0.05
V
0.05
0.05
4.95
9.95
14.95
V
V
VIL
5.0
1.5
10
15
4.0
2.25
4.50
6.75
3.0
1.5
1.5
3.0
4.0
3.0
4.0
V
VIH
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
5.0
5.0
10
15
-2.5
-0.52
-1.3
-3.6
-2.1
-0.44
-1.1
-3.0
-4.2
-0.88
-2.25
-8.8
-1.7
-0.36
-0.9
5.0
0.52
13
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
5.0
(VO=05 or4.5 VI
(VO= 1.0 or 9.0 VI
(VO= 1.5 or 13.5 VI
Output Drive Current- Comparator
Yin @ Pin 4== 1.0 V (MCl4447 onlyl
(VOH==2.5 VI
(VOH=4.6 VI
(VOH==9.5 VI
(VOH= 13.5 VI
5.0
25°C
Min
mA
IOH
-
-
-2A
mA
IOL
10
15
±0.3
2A
Input Current- Address. Ramp Start
lin
15
Input Current- Analog Inputs
lin
15
±01
±50
nA
Input Capacitance- Address. Ramp Start
Vin==O V
Cin
15
5.0
7.5
pF
Quiescent Current
IDD
0.8
1.5
1.7
1.5
mA
10
3.0
0
±0.3
15
Crosstalk Between Any Two Input Channels
Reference Current Range
Channel Input Voltage Range
4.0
mV
10
50
p.A
VAl
0
0
0
3.0
8.0
13.0
V
0.285
VSO
Reference Voltage Range
Conversion Linearity
C>loo pF. VAI=O to 2.5 V. V re f=25 V
1/;,:-(1,,.,7nV V::,=70V
VAI = 0 to 120 V. Vref= 12.0 V
VTC
Vref
V
OAOO
OA20
10
15
Comparator Threshold
p.A
IR
VCr
10
15
Buffer Amplifier Output Offset
± 10
0.195
0.275
0.290
5
10
15
0
0
5
10
15
2.0
2.0
2.0
VBO
VBO
VSO
3.0
8.0
13.0
10
15
-0.5
-0.5
-0.5
+0.5
+0.5
+U.O
V
V
% Full
Scale
LC
3-26
I
-
I
-
I
-
I
-
MC14443, MC14447
SWITCHING CHARACTERISTICS (CL = 50 pF, T A = 25 0 C)
Characteristic
Symbol
VOO
V
Output Rise Time-Comparator
5.0
tTLH
10
15
Output Fall Time-Comparator
5.0
tTHL
10
15
MC14443
Propagation Delay Time-Comparator
5.0
tpLH
10
(RL = 10 k to VDD)
15
5.0
tpHL
10
15
MC14447
5.0
tpLH
10
15
5.0
tPHL
10
15
Multiplexer Propagation Delay
5.0
tM
10
15
Ramp Start Delay Time
5.0
tTS
10
15
Acquisition Time*
5.0
tA
C=1000pF
10
15
Rref= 100 kO
...
* AcquIsition Time Includes multiplexer propagation delay, ramp start propagation delay and
the selected input voltage.
(MC14447 only)
Min
Typ
Max
Unit
120
240
ns
75
150
65
130
ns
250
500
350
700
650
1300
ns
550
1100
500
1000
550
1100
350
700
ns
300
600
600
300
600
ns
1200
475
950
500
1000
450
ns
980
540
1080
750
1500
180
ns
360
125
250
110
220
40
ns
80
25
50
20
40
jlS
30
60
15
30
14
28
the time required to charge ramp capacitor to
-
-
-
PIN DESCRIPTIONS
A2, A1, AO, ANALOG MUX ADDRESS INPUTS (PINS 2,
1, 16) - These inputs determine the input voltage source to
be presented to the measurement system according to the
Truth Table shown in Figure 2.
Ref Current, REFERENCE CURRENT (PIN 6)
- To
discharge the ramp capacitor, the reference current is fixed
via a resistor (Rref) to a positive supply from Pin 6. Typical
current is equal to (VOO-Vref)/Rref.
Ramp Start, RAMP START (PIN 3) - When Ramp Start
is low, the ramp capacitor is charged to a voltage associated
with the selected input channel. When Ramp Start is
brought high, the connection to the input channel is broken
and the capacitor begins to ramp toward VSS. See Figure 4.
Comp Out, COMPARATOR OUTPUT (PIN 7) - This output is low when the capacitor has reached the discharged
voltage and is high otherwise. The MC14443 requires a pullup resistor on Pin 7 due to the open-drain configuration. The
MC14447 does not require a pull-up resistor.
Ramp Cap, RAMP CAPACITOR (PIN 4) - The ramp
capacitor is used to generate a time period when discharged
from a selected voltage via a precise reference current. A
polystyrene or mylar capacitor is recommended. The value
should be ~ 100 pF so that the board and stray capacitances
have negligible effects. Large values of capacitance with the
associated large leakage currents are not recommended
because the leakage current must be insignificant in comparison to the minimum reference current (10 pAl.
Ref Voltage, REFERENCE VOLTAGE (PIN 8) - This is the
known voltage to which the unknown is compared.
VSS, NEGATIVE POWER SUPPLY (PIN 5)
system ground.
INPUT CHANNELS (PINS 9, 10, 11, 12, 13, 15) - Input
channels 1 through 6 are used to monitor up to six separate
unknown voltages. Selection is via the address inputs.
VDD, POSITIVE POWER SUPPLY (PIN 14) - This pin is
the package positive power supply pin.
This is
3-27
II
MC14443, MC14447
FIGURE 1 - VOLTAGE TO PULSE WIDTH CONVERSION
Voltage
Reference
Voltage' (VR + VSO)
Unknown
Voltage' (VX
(VSO)count = to
+ VSO)count = tx
(V R + VSO)count = tR
(VR)count = tR -- to
(V X )count = tx - to
(V x
+ VSO)
(VX)count =
(VR)count
Voltage
II
at 0
Input'
V
tx - to
tR - to
(Vao)
L...i...--=::!===::::::======::.
"'Voltages measured at pin 4
with ramp start low_
to
time
tx
FIGURE 2 - TRUTH TABLE
A2
Al
AO
0
0
0
VSS
0
0
1
Ch1
Channel 1
Input Selected
Channe~
0
1
0
1
0
1
Ch2
Ch3
Channel 3
Channel 2
1
0
0
Ch4
Channel 4
1
0
1
Ch5
Channel 5
1
1
0
Ch6
Channel 6
1
1
1
Vref
Channel 7 (External Reference)
FIGURE 3 - TYPICAL APPLICATIONS
Address Lines ~
from the
Microprocessor
Ramp start
from the
0 (ground)
.--------
Ramp Capacitor
"Qj
~
Rl
16
15
Microprocesso r
1
14
13
Channel 2
UU
12
Channel 3
11
Channel 4
7
10
8
9
Channel 5
Channel 6
:;E :;E
R2
-'-
FIGURE 4 - SOFTWARE FLOW
(CONVERSION SEQUENCE)
Step No.
A2
Al
AO
Ramp Start
Comment
1.
1
1
1
0
Channel 7 Selected (Reference Voltage)
2.
1
1
1
1
Record time until Pin 7 goes low
3.
0
0
0
0
Channel 0 Selected (Ground)
4.
0
0
Record time until Pin 7 goes low
0
0
0
0
1
1
5.
0
Channel 1 Selected
1
1
6.
0
Record time until Pin 7 goes low
Calculate tCh7 - tChO
= tChi Step 2-Step 4
Calculate tChl - tChO - tCh( Step 6-Step 4
Calculate Vunknown
7.
0
1
8.
0
1
0
0
= VCh7(tChl'/tChi)*
0
Channel 2 Selected
1
Record time until Pin 7 goes low
Calculate tCh2 - tChO
I
Channell
.r .r
5
6
Comparator
Output to
I
"'''
.r.r
.r.r
3
~E--4
tI
M icroprocesso r
1
2
~IRCUIT
= tCh2
Calculate Vunknown - VCh7 (tchiltCh7')t
etc.
* Weighting
of the analog signal on Channell.
tWeighting of the analog signal on Channel 2.
3·28
I
Uo'oowo
Analog
,Voltage
Inputs
®
MC14444
MOTOROLA
CMOS LSI
ANALOG-TO-DIGITAL CONVERTER (ADC)
(LOW-POWER SILICON GATE
COMPLEMENTARY MOS)
The MCl4444 ADC is a 4O-pin bus-compatible 8-bit AID converter
with additional digital I/O capability. The device operates from a single
5 V supply and provides direct interface to the MPU data bus used with
all Motorola M6800 family parts. It performs an 8-bit conversion in 32
machine cycles at 1 MHz and allows for up to 15 analog inputs. In addition, the part has a 3-bit digital I/O port and can accept up to 9 digital
inputs. Six of these inputs are designed to be either analog or digital
inputs. All necessary logic for software configuration, channel selection, conversion control, bus interface and maskable interrupt capability
is included.
MICROPROCESSOR-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTER
•
Direct Interface to M6800 Family MPUs
•
•
•
•
•
•
•
•
•
•
Dynamic Successive Approximation A/D
321's Conversion at fE = 1.0 MHz
Ratiometric Conversion
Completely Programmable
Polled or Interrupt Driven Operation
3 Dedicated Digital Inputs
3-Bit Digital I/O Port
9 Dedicated Analog Inputs
6 Inputs Usable for Either Analog or Digital Signals
Completely TTL Compatible Inputs at Full Speed with Supply
Voltage of 5 V ± 10%
~
~
.;.~...
40
,. , • ,. .
1
"
,
40 I '
I'
.
CASE 734
ORDERING INFORMATION
Suffix Denotes
Ceramic Package
Plastic Package
MO
15
15
PO-5
sc
Analog
Data
Register
(Read Only)
A0-3
Digital
Data
Register
L---.."D-100-,..,....,2~---+-----+'~-~ (Read Only)
0100-2
DDIR
h~------------4.----------J
3-29
L SUFFIX
CERAMIC PACKAGE
1+-J'"""-4.-+--ANO,2-15
Bus
Control
Logic
CASE 711
"".
"
BLOCK DIAGRAM
VAG
PSUFFIX
PLASTIC PACKAGE
013-5
II
MC14444
MAXIMUM RATINGS*
Symbol
Value
Unit
-0.5 to +6.5
V
OC Input Voltage (Referenced to VSS)
-0.5 to VCC+0.5
V
OC Output Voltage (Referenced to VSS)
-0.5 to VCC+0.5
V
±10
mA
OC Supply Voltage (Referenced to VSS)
Yin
Vout
lin
II
Parameter
VOO
OC Input Current, per Pin
lout
OC Output Current, per Pin
±10
mA
100
OC Supply Current, VOO and VSS Pins
±20
mA
Po
T stg
Power Oissipation, per Package T
h
Storage Temperature
500
mW
-65 to +150
°C
300
°C
Lead Temperature (10-Second Solderingl
* Maximum Ratings are those values beyond which damage to the device may occur.
tPower Oissipation Temperature Oerating:
Plastic "P" Package: -12mW/oC from 65°C to 85°C
Ceramic "L" Package: no derating
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid applications of any voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range VSSS(Vin or
Vout)sVOO·
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VOOI.
DC ELECTRICAL CHARACTERISTICS (VOO: 5.0 V ± 10%, VSS: 0 V, T A: - 40° to 85°C unless otherwise noted)
I
ISymbol I
Characteristic
Bus Control Inputs (R/W, Enable, Reset, RS1, CS)
Conditions
I
I Max
Unit
2.0
-
V
-
O.B
V
-
±1O
p.A
V
Min
Input High Voltage
Output Leakage Current (Off State)
Oata Bus (00-07)
Input High Voltage
Input Low Voltage
VIH
V IL
Three-State (Off State) Input Leakage Current
ITSI
VOO:5.5 V,
VSSSVinsVOO
Peripheral 1/0 (0100-0102, 013-015, PO-P5)
Input High Voltage
VIH
2.0
-
Input Low Voltage
VIL
-
O.B
V
-
±1.0
p.A
Input Leakage Current
013-015, PO-P5
Output High Voltage
0100-0102
VOH
VOO:5.5 V,
VSSsVinSVOO
IOH: -0.19 mA
Output Low Voltage
0100-0102
VOL
10L =0.975 mA
Three-State (Off State) Input Leakage Current
0100-0102
ITS I
VOO=5.5 V,
VSSSVoutsVOO
lin
VOO-O.4
-
V
-
0.4
V
±10
p.A
Current ReqUIrements
Supply Current
Converter Input Current
Reference Input Current
Vref
100
VOO=5.5 V, fE= 1 MHz
-
10
mA
IAOC
Analog input current at
fE: 1 MHz with multiplexer
inputs between VSS and VOO
-
±500
nA
Iref
Vref=4.5 to 5.5 V
-
BOO
p.A
3-30
I
MC14444
ANALOG CHARACTERISTICS
(T A = - 40°C to 85°C)
Characteristic
Description
Analog Multiplexer
On Resistance
Resistance between each analog input and multiplexer output
-
5
kO
Leakage Current
Leakage current between all deselected analog inputs and any selected
analog input with all analog input voltages between VSS and VDD
-
±400
nA
AID Converter (VSS=O V, VAG=O V, 4.5 V:5V re f:5VDD)
Resolution
Number of bits resolved by the AID
8
-
Bits
Nonlinearity
Maximum deviation from the best straight line through the AI D transfer
characteristic
-
± y,
LSB
Zero Error
Difference between the output of an ideal and an actual AID for zero
input voltage
-
± y,
LSB
Full-Scale Error
Difference between the output of an ideal and an actual AID for full-scale
input voltage
-
± y,
LSB
Total Unadjusted Error
Maximum sum of Nonlinearity, Zero Error, and Full-Scale Error
-
±%
LSB
Quantization Error
Uncertainty due to converter resolution
-
±%
LSB
Absolute Accuracy
Difference between the actual input voltage and the full-scale weighted
equivalent of the binary output code, all error sources included
-
± 10
LSB
Conversion Time
Total time to perform a single analog-to-digital conversion
-
32
E cycles
Sample Acquisition Time
Time required to sample the analog input
-
12
E cycles
AC CHARACTERISTICS (T A = - 40° to 85°C) (See Figure 1)
Characteristic
Signal
Symbol
Min
Max
Unit
Enable Clock Cycle Time (lifE)
E
tcycE
943
-
ns
Enable Clock Pulse Width, High
E
PWEH
440
-
ns
Enable Clock Pulse Width, Low
E
PWEL
410
-
ns
Clock Rise Time
E
tEr
-
25
ns
-
Clock Fall Time
Address Setup Time
E
tEf
RS1, R/W, CS
tAS
30
ns
145
-
ns
Data Delay (READ)
00-07
tOOR
-
335
ns
Data Setup (WRITE)
00-07
tosw
185
-
ns
Address Hold Time
RS1, R/W, CS
tAH
10
-
ns
Input Data Hold Time
00-07
tDHW
10
-
ns
Output Data Hold Time
00-07
tOHR
10
-
ns
ANO-AN15
Cin
-
55
pF
-
15
Input Capacitance
010-015,
R/W, E, RS1,
CS, RESET
Three-State Output Capacitance
High-Impedance Output Capacitance
3-31
0100-0102
00-07
Cout
-
15
pF
IRQ
Cout
-
15
pF
II
MC14444
II
RilN,
CS,
RSl
MPU
Read
MPU
Write
3-32
MC14444
MCl4444 MPU INTERFACE SIGNALS
PIN FUNCTIONS
Pin No.
1
Pin Name
Function
Type
VAG
A/D Converter Analog Ground
Supply
2
VSS
Digital Ground
3
0100
Digital Port
Input/ Output
Supply
4
DIOl
Digital Port
Input/Output
5
DI02
Digital Port
Input/ Output
6
DI3
Digital Port
Input
Input
7
DI4
Digital Port
8
DI5
Digital Port
9
D7
Data Bus Bit 7 IMSB)
Input/Output
Input
10
D6
Data Bus Bit 6
Input/Output
11
D5
Data Bus Bit 5
Input/Output
12
D4
Data Bus Bit 4
Input/Output
13
D3
Data Bus Bit 3
Input/Output
14
D2
Data Bus Bit 2
Input/Output
15
Dl
Data Bus Bit 1
Input/ Output
16
DO
Data Bus Bit 0 (LSB)
Input/Output
17
R/W
18
E
Read/Write
Input
Enable Clock 1¢2)
Input
19
RS1
Register Select
Input
20
CS
Chip Select
Input
21
Reset
22
P51AN15)
Reset
Input
Digital Port or Analog Channel 15
Input
23
P41AN14)
Digital Port or Analog Channel 14
Input
24
P31AN13)
Digital Port or Analog Channel 13
Input
25
P21AN12)
Digital Port or Analog Channel 12
Input
26
P11AN11)
Digital Port or Analog Channel 11
Input
27
POIAN101
28
AN9
Digital Port or Analog Channel 10
Input
Analog Channel 9
Input
Input
29
AN8
Analog Channel 8
30
AN7
Analog Channel 7
Input
31
AN6
Analog Channel 6
Input
32
AN5
Analog Channel 5
Input
33
AN4
Analog Channel 4
Input
34
AN3
Analog Channel 3
Input
35
AN2
Analog Channel 2
Input
36
ANO
Analog Channel 0
Input
37
MO
Analog Multiplexer Output
38
IRQ
Interrupt Request
39
VDD
Supply Voltage
40
Vref
AI D Converter Positive Reference
Voltage
Test Only
Open-Drain
Bidirectional Data Bus (DO-D7) - The bidirectional data
lines DO-D7 comprise the bus over which data is transferred
in parallel to and from the MPU The data bus output drivers
are three-state devices that remain in the high-impedence
state except during an MPU read of an ADC data register.
Enable Clock (E) - The enable clock provides two functIOns for the MCl4444. First, it serves to synchronize data
transfers into and out of the ADC. The timing of all other external Signals is referenced to the leading or trailing edge of
the enable clock. Secondly, the enable clock is used internally to derive the necessary SAR AI D conversion clocks.
Because this, conversion is a dynamic process, enable clock
must be a cl)ntinuous signal into the ADC during an AID
conversion.
ReadlWrite (R/W)
The R/W signal is provided to the
MCl4444 to control the direction of data transfers to and
from the MPU. A low state on this line is required to transfer
data from the MPU to the ADC control register. A high state
IS required on R/W to transfer data out of either of the ADC
data registers.
Reset (RESET) - The reset line supplies the means of
externally forcing the MCl4444 into a known state. When a
low is applied to the RESET pin, the start conversion, Interrupt enable and 1/0 port data direction bits of the control
register are cleared. Analog channel 0 IS automatically
selected by the analog multiplexer. The AID status bit is also
cleared. Any AI D results present In the Analog Data register
are not affected by a reset. Reset forces the data bus and 1/0
port output drivers to the high-impedance state. The internal
byte pointer (discussed In the following pages) is set to point
to the most significant byte of any subsequently selected internal register. In order to attain an Internally stable reset
state, the RESET pin must be low for at least one complete
enable clock cycle.
Chip Select (CS) - Chip select is an active-low input used
by the MPU system to enable the ADC for data transfers. No
data may be passed to or from the ADC through the data bus
pins unless CS is in a low state. A selection of MPU address
lines and the M6800 VMA Signal or its equivalent should be
utilized to provide chip select to the MCl4444.
MCl4444 ANALOG INPUTS AND DIGITAL I/O
(Refer to the ADC Block Diagram)
Dedicated Analog Channels (ANO, AN2-AN9) - These
input pins serve as dedicated analog channels subject to AID
conversions. These channels are fed directly into the internal
16-to-1 analog multiplexer which feeds a single analog
voltage to the AID converter.
Output
Supply
Input
3-33
Shared Analog Channels (AN10-AN15) - These input
pins are also connected to the analog multiplexer and may be
used as analog channeis for AID conversion. However,
these pins may also serve as digital input pins as described
next.
II
MC14444
Shared Digital Inputs (PO-P51 - PO-P5 comprise a 6-bit
digital input port whose bits may also serve as analog channels. The state of these inputs may be read at any time from
the ADC digital data register. The function of these pins is
not programmed, but instead is simply assigned by the
system designer on a pin-by-pin basis.
I
CAUTION: Digital values read from the PO-P5 bit
locations do not guarantee the presence of true digital input levels on these pins. PO-P5 pass through a
TTL-compatible input buffer and into the digital data
register. These buffers are designed with enough
hysteresis to prevent internal oscillations if an analog
voltage between 0.8 and 2 V is present on one or
more of these six pins.
AID Ground Reference Voltage (VAG) - This supply is
the ground reference for the internal DAC and several
reference voltages supplied to the comparator. !t should also
be noise-free to guarantee AID accuracy. Absolute accuracy
may be degraded if VAG is wired to VSS at the ADC
package unless VSS has been sufficiently filtered to remove
switching noise. Ideally VAG should be single-point grounded to the system analog ground supply.
Multiplexer Output (MOl - The analog multiplexer selects
one of 16 analog input channels and connects it to the input
of the AID converter. The multiplexer output is internally
connected to the AI D input and requires no external
jumpers. Since loading of the MO pin affects the charging
time of the DAC. it is recommended that no connection be
made to the MO pin.
Digital 110 Port (0100-0102) - These pins serve as a 3-bit
digital 1/0 port. At reset the port is configured as an input
and may be read from the ADC digital data register. The port
may be programmed as an output by setting the DDIR bit in
the control register to a logical 1. See the control register
discussion for further details. When configured as an output,
the DIO port will provide CMOS logic levels for limited dc
load currents. (Refer to the Electrical Specifications for the
dc drive capability of this port.) New output states are
transferred to the external pins on the last falling edge of E
during a 16-bit write to the control register. When configured
as an input, the port will accept both TTL and CMOS logic
levels.
Dedicated Digital Inputs (013-DI5) - These three pins are
dedicated as digital inputs whose values may be read from
the ADC digital data register. They are also TTL and CMOS
compatible.
MC14444 SUPPLY VOLTAGE PINS AND TEST PIN
Positive Supply Voltage (VDDI - VDD is used internally
to supply power to all digital logic and to the chopper
stabilized comparator. Because the output buffers connected to this supply must drive capacitive loads. ac noise on
this supply line is unavoidable internally. Analog circuits using this supply within the MC14444 were designed with high
VDD supply rejection; however, it is recommended that a
filtering capacitance be used externally between VDD and
VSS to filter noise caused by transient current spikes.
Ground Supply Voltage (VSS) - VSS should be tied to
system digital ground or the negative terminal of the VDD
power source. Again, the output buffers cause internal noise
on this supply, so analog circuits were deSigned with high
VSS rejection.
Positive AID Reference Voltage (Vref) - This is the
voltage used internally to provide references to the analog
comparator and the digital-to-analog converter used by the
SAR AID. The analog-to-digital conversion result will be
ratiometric to V ref - VAG (full scale!. Hence V ref should
be a very noise-free supply. Ideally Vref should be singlepoint connected to the voltage supply driving the system's
transducers. Vref may be connected to VDD. but degradation of aLk:iviutt; A/D aCCuracy· iTiJY result diJe to sV'.!itching
noise on VDD.
3-34
MC14444 INTERNAL REGISTERS
The MCl4444 Abc has three 16-bit internal registers. Each
register is divided into two 8-bit bytes: a most significant
(MS) byte (bits 8-15) and a least significant (LS) byte (bits
0-7). Each of these bytes may not be addressed externally.
but instead are normally addressed by a single 16-bit instruction such as the M6800 LDX instruction. An internal byte
pointer selects the appropriate register byte during the two E
cycles of a normal 16-bit access. In keeping with the M6800
X register format, the pointer points first to the MS byte of
any selected register. After the E cycle in which the MS byte
is accessed. the pointer will switch to the LS byte and remain
there for as long as chip select is low. The pointer moves
back to the MS byte on the falling edge of E after the first
complete E cycle in which the ADC is not selected. (See
Figure 2a for more detail.) The MS byte of any register may
also be accessed by a simple 8-bit instruction as shown in
Figure 2b. However. the LS byte of all registers may be
accessed only by 16-bit instructions as described above. By
connecting the ADC register select (RS1) to the MPU
address line A 1, the three registers may be accessed sequentially by 16-bit operations.
CAUTION: RS1 should not be connected to
address line AO and the addressing of the ADC
should be such that RS 1 does not change states during a 16-bit access.
INTERNAL REGISTER ADDRESSING
Addressing Signals
RESET
CS
0
X
1
1
R/W RS1
ADC Response
X
X
Reset
0
0
0
No Response
0
0
1
MPU Write to Control Register
1
0
1
0
MPU Read from Analog Data
Register
1
0
1
1
MPU Read from Digital Data
Register
-
~
P O_r_,s_e,_--,
~_l---L_X_.LI_x_ILL._n_l_p_u_e_se_le_C_te_O_\_I~_O_M_e_5_
MC14444
FIGURE 2 -
ADC ACCESS TIMING
a - Typical 16-Bit ADC Access
CS
11
----+..,.
RS1,
Riw
Byte Pointer
Reset to MS Byte
b - Typical a-Bit ADC Access
RS1,
R/iN
""-I1.oII.......1I...II'..JU
Select
MS Byte
3-35
MC14444
MCl4444 CONTROL REGISTER
(Write Only)
15
D
AD
(LSBI
(MSBI
~---------------16-Bit Write--------------~~
I
Analog Multiplexer Address (AO-A3) - These four
address bits are decoded by the analog multiplexer and used
to select the appropriate analog channel as shown below.
will begin immediately after the completion of the control
register write.
Unused Bits (X) - Bits 9-13 of the ADC Control Register
are not used internally.
Hexadecimal Address (A3= MSB)
o
Select
Interrupt Enable (IE) - The interrupt enable bit. when set
to a logical 1, allows the I RQ pin to be activated at the completion of the next analog to digital conversion.
ANO
VREF
2-9
AN2-AN9
AN10-AN15(PO-P51
A-F
Control Register MSB - The MSB of the most significant
byte of the ADC control register must be written as a logical
Digital I/O Output (0100-0102) - When the MPU configures the 3-bit 1/0 port as an output, these are the bit locations into which the output states are written.
o.
I/O Port Data Direction (DDIR) - This is the data direction bit for the 3-bit 1/0 port. A logical 1 configures the port
as output while a logical 0 configures the port as input.
NOTE: A 16-bit control register write is required to change
the analog multiplexer address or to update the 010 port.
However, 8-bit writes to the MCl4444 can be used to initiate
an AID conversion if the analog MUX is already selecting the
desired channel. This is useful when repeated conversions
on a particular analog channel are necessary.
Start A/D Conversion (SC) - When the SC bit is set to a
logical 1, an AID conversion on the specified analog channel
MCl4444 ANALOG DATA REGISTER
(Read Only)
15
RO
(LSBI
~---------------16-Bit Read------------------'~
A/D Result (RO-R7) - The LS byte of the analog data
register contains the result of the AID conversion. R7 is the
MSB, and the converter follows the standard convention of
assigning a code of $FF to a full-scale analog voltage. There
are no special overflow or underflow indications.
A/D Status (EOe) - The AID status bit is set whenever a
conversion is successfully completed by the ADC. The status
bit is cleared by either an 8-bit or a 16-bit MPU write to the
ADC control register. The remainder of the bits in the MS
byte of the analog data register are always set to a logical 0
to simplify MPU interrogation of the ADC status. For example, a single 8-bit M6800 TST instruction can be used to
determine the status of the AID conversion.
3·36
MC14444
MCl4444 DIGITAL DATA REGISTER
(Read Only)
15
o
8
DIO
P5
o
~---------------16-Bil Read---------------~
Digital 1/0 Port (0100-0102) - The states of the three
digital 1/0 pins are read from these bits regardless of
whether the port is configured as input or output.
Shared Digital Port (PO-P5) - The voltage present on
these pins is interpreted as a digital signal and the corresponding states are read from these bits.
Dedicated Digital Input (013-015) - The states of the
three dedicated digital inputs are read from these bits.
WARNING: A digital value will be given for each pin even
if some or all of the pins are being used as analog inputs.
Analog Multiplexer Address (AO-A3) - The number of the
analog channel presently addressed is given by these bits.
ANALOG SUBSYSTEM
(See Block Diagram)
General Description
2 enable clock cycles for the write into the control register
even if only 8 bits are written. In this case, the second E cycle
does not affect any internal registers. During the next 12V2
enable cycles following a write command, the analog
multiplexer channel is selected and the analog input voltage
is stored on the sample and hold DAC. It is recommended
that an input source impedance of 10 KO or less be used to
allow complete charging of the capacitive DAC.
During cycle 13 the AlDis disconnected from the
multiplexer output and the successive approximation AI D
routine begins. Since the analog input voltage is being held
on an internal capacitor for the entire conversion period, it is
required that the enable clock run continuously until the AID
conversion is completed. The new 8-bit result is latched into
the analog data register on the rising edge of cycle 32. At this
point the end of conversion bit (EOC) is set in the analog
data register MS byte, and the interrupt request ORO} pin
goes low if interrupt has been enabled by the IE bit of the
control register. (See Figure 3, AID Timing Sequence.)
The analog subsystem of the MCl4444 is composed of a
16-channel analog mUltiplexer, an 8-bit capacitive DAC
(digital-to-analog converter), a chopper-stabilized comparator, a successive approximation register, and the
necessary control logic to generate a successive approximation routine.
The analog multiplexer selects one of sixteen channels and
directs it to the input of the capacitive DAC. A fullycapacitive DAC is utilized beca,use of the excellent matching
characteristics of thin-oxide capacitors in the Silicon-gate
CMOS process. The DAC actually serves several functions.
During the sample phase, the analog input voltage is applied
to the DAC which acts as a sample-and-hold circuit. During
the conversion phase, the capacitor array serves as a digitalto~analog converter. The comparator is the heart of the
ADC; it compares the unknown analog input to the output of
the DAC, which is driven by a conventional successiveapproximation register. The chopper-stabilized comparator
was designed for low offset voltage characteristics as well as
VDD and VSS power supply rejection.
NOTE: The digital data register or the analog data register
may be read even if an AI D conversion is in progress. If the
analog data register is read during an AI D conversion, valid
results from the previous conversion are obtained. However,
the EOC bit will be clear (logical Ol if an AID conversion is in
progress.
Device Operation
An AID conversion is initiated by writing a logical 1 into
the SC bit of the ADC control register. The MC14444 allows
3-37
II
MC14444
FIGURE 3 - TYPICAL AID TIMING SEQUENCE
MPU Write
ToADC
Control
Register
Sample Analog Input
~ ~(lnputShouldBeStable)
1
2 3 4
5 6
7. 8
_I.
SARA/DConversion
-I
9 10 11 12 13 14 15 16 17. 18 1920 21 22 23 24 25 26 27 28 29 30 31 32
R/Vii
I
RS1
Analog Data
Register IRO-R7
Valid Data From Previous Conversion IEOC Clear)
and EOC)
------~~------------------------------------------------------------------~rl~
TR'O
(If
Enabled)
FIGURE 4 - TYPICAL MC14444 APPLICATION IN A CLIMATE CONTROLLER
MC6002
MPU
~-----------1~------ Vref
~-----'---~~-------VAG
3-38
®
MC14447
MOTOROLA
FOR COMPLETE DATA
SEE MCl4443
CMOS MS.
ANALOG-TO-DIGITAL CONVERTER
LINEAR SUBSYSTEM
(LOW-POWER COMPLEMENTARY MOS)
The MCl4443 and the MCl4447 are 6-channel, single-slope, 8-10 bit
analog-to-digital converter linear subsystems for microprocessor-based
data and control systems. Contained in both device::: are a one-of-8
decoder, an 8-channel analog multiplexer, a buffer amplifier, a precision
voltage-to-current converter, a ramp start circuit, and a comparator.
The output driver of the MCl4443's comparator is an open-drain
N-channel which provides a sinking current. The output driver of the
MCl4447's comparator is a standard B-Series P-Channel, N-Channel
pair.
A CMOS MPU or MCU provides the addressing, timing, counting, and arithmetic operations required for implementing a full
analog-to-digital converter system. A system made up of a processor and the linear subsystem has features such as
automatic zeroing and variable scaling (weighting) of six
separate analog channels.
• Quiescent Current 0.8 mA Typical at VDD = 5 V
MICROPROCESSOR-BASED
ANALOG-TO-DIGITAL
CONVERTER
~fifIIIIIa
J"~J~i)H ~"rmrnn ~
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
PLASTIC PACKAGE
CASE 620
CASE 648
• Single Supply Operation +4.5 to + 18 Volts
ORDERING INFORMATION
• Direct Interface to CMOS MPUs
• Typical Resolution - 8 Bits
• Typical Conversion Cycle as Fast as 300 p's
MC14X XX
• Ratio Metric Conversion Minimizes Error
Suffix
Tt==
• Analog Input Voltage Range: VSS to VDD - 2 V
• Chip Complexity: MCl4443 MCl4447 -
L
P
Denotes
Ceramic Package
Plastic Package
150 FETs
151 FETs
BLOCK DIAGRAM
PIN ASSIGNMENT
15
Ch1
Ramp Start
3
13
Ch2
12
Ch3
Ch4
Ch5
Ch6
A1
A2
"
x
11
a.;;"
10
~
4
Ref
Voltage
AO
A1
15
Ramp Start V OD
14
Ramp Cap
Ch2
13
VSS
Ch3
12
Ref Current Ch4
11
Ch5
10
Comp Out
6 Ref Cu rrent
.-----------~~---4~~Set
VD D
~
Pin 14
VSS = Pin 5
A2
3-39
16
Ch 1
Ref Voltage Ch6
II
®
MC14549B
MC14559B
MOTOROLA
CMOS MS.
!LOW·POWER COMPLEMENTARY MaS)
SUCCESSIVE APPROXIMATION REGISTERS
SUCCESSIVE APPROXIMATION
REGISTERS
The MC14549B and MC14559B successive approximation registers
are 8-bit registers providing all the digital control and storage necessary
for successive approximation analog-to-digital conversion systems.
These parts differ in only one control input. The Master Reset (MR) on
the MC14549B is required in the cascaded mode when more than 8 bits
are desired. The Feed Forward (FF) of the MC14559B is used for register
shortening where End-of-Conversion (EOC) is required after less than
eight cycles.
Applications for the MC14549B and MC14559B include analog-todigital conversion, with serial and parallel outputs.
II
• Totally Synchronous Operation
• All Outputs Buffered
• Single Supply Operation
L SUFFIX
CERAMIC PACKAGE
P SUFFIX
PLASTIC PACKAGE
CASE 620
CASE 648
1
ORDERING INFORMATION
• Serial Output
• Retriggerable
• Compatible with a Variety of Digital and Analog Systems such as the
MC1408 8-Bit DI A Converter
Mmxm
tSUfflX
• All Control Inputs Positive-Edge Triggered
• Supply Voltage Range=3.0 Vdc to 18 Vdc
• Capable of Driving Two Low-Power TTL Loads, One Low-Power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range
Denotes
L
Ceramic Package
P
A
PlastiC Package
Extended Operating
Temperature Range
Limited Operating
Temperature Range
C
• Chip Complexity: 488 FETs or 122 Equivalent Gates
PIN ASSIGNMENT
MAXIMUM RATINGS (Voltages referenced to Vssl
Rating
DC Supply Voltage
04
VDD
05
03
02
Symbol
Value
Unit
06
VDD
-0.5 to + 18
Vdc
07
01
Vin
-0.5 to VDD +0.5
Vdc
Sout
00
Input Voltage, All Inputs
DC Input Current, per Pin
lin
±10
mAdc
Operating Temperature Range- AL Device
CLlCP Device
TA
-55 to + 125
-40 to +85
°C
Storage Temperature Range
Tstg
-65 to + 150
°C
D
EGC
C
* For MC14549B Pin 10 is MR input
TRUTH TABLES
MC14549B
SC SC(t-1 )
X
X
MR MR(t-1) Clock
X
X
X
0
0
X
X
0
Action
~
None
-...r-
Reset
--r-
Start
SC SC(t-1 ) EOC Clock
--r-
0
0
0
-r
Action
l-
Nane
Start
X
-.r-.r-
Start
Conversion
0
-..J
Continue
Conversion
Continue
Conversion
0
X
X
0
X
Conversion
X
For MC14559B Pin 10 is FF input
MC14559B
X
Conversion
Continue
Conversion
-...r
Retain
Conversion
Result
I°1
v
r-
I I I0
)(
(':~ntinue
I
Previous
Operation
II
X
1
I
--.r
I I
Start
Conversion
X = Don't Care
t-1 = State at Previous Clock-r
3-40
I
This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to this high
impedance circuit. For proper operation it
is recommended that Yin and V out be
constrained to the range VSS .;;;: (Vin or
Vuui.~
c
CIJ
50
~
~
2
-
25
Vottset
•
o
IV
o
SOO
ns
-
5-15
-
2
7.5
/"
31
47
SlF
S2F
Program Step
LINEARITY ERROR (integrallinearityl. A measure of how straight a
device's transfer function is, it indicates the worst-case deviation of
linearity of the actual transfer function from the best-fit straight line.
It is normally specified in parts of an LSB.
3-49
p,s
ns
/'
15
SOF
p's
-
Ideal ..
CI>
CD
:!!
""0
>
0
/?'
p's
-
/~ ~Actual
~.;/ VT
/~ ""
..;
c::
3.5
2
5
~~
75
#.
0:
p,s
5
10
15
;/
CI)
I
-
3.5
Of A TRANSFER FUNCTION
en
c
p,s
5
5
10
15
5
10
15
100
>
ns
-
500
5-15
FIGURE 1 -
-
750
3.5
5
10
15
Input Capacitance
1000
2
5
5
10
15
Hold Time, Clock to Enable (Figures 3 and 41
2
-
63
$3F
pF
II
MC144110, MC144111
FIGURE 2 -
DEFINITION OF STEP SIZE
VRn Out
;~~tr
Stepsize=~±O.75 VJ?l
(For any adjacent pair of digital numbers)
~
Digital Number
FIGURE 3 -
SERIAL INPUT, POSITIVE CLOCK
~_%_---
Ft
su
Clock
_ _ _ _ _ _ _J
I'~_+----'I"----- ==J
FIGURE 4 -
____
D_N
_ _ __
SERIAL INPUT, NEGATIVE CLOCK
D_N_J)(~_ _ _ __
____
3·50
MC144110, MC144111
PIN DESCRIPTIONS
INPUTS
Din, DATA INPUT - Six-bit words are entered serially,
MSB first, into digital data input, Din. Six words are loaded
into the MCl44110 during each D/A cycle; four words are
loaded into the MC144111.
R1 Out through Rn Out, RESISTOR NETWORK OUTPUTS - These are the R-2R resistor network outputs.
These outputs may be fed to high-impedance input FET op
amps to bypass the :)n-chip bipolar transistors. The R value
of the resistor network ranges from 7 to 15 kO.
Enibie, NEGATIVE LOGIC ENABLE - The Enable pin
must be low (active) during the serial load. On the low-tohigh transition of Enable, data contained in the shift register
is loaded into the latch.
Q1 Out through On Out, NPN TRANSISTOR OUTPUTS
- Buffered DAC outputs utilize an emiter-follower configuration for current-gain, thereby allowing interface to lowimpedance circuits.
Clock, SHIFT REGISTER CLOCK - Data is shifted into
the register on the high-to-Iow transition of Clock. Clock is
fed into the D-input of a transparent latch, which is used for
inhibiting the clocking of the shift register when Enable is
high.
SUPPLY PINS
VSS, NEGATIVE SUPPLY VOLTAGE usually ground.
This pin is
VDD, POSITIVE SUPPLY VOLTAGE - The voltage applied to this pin is used to scale the analog output swing from
4.5 to 15 volts, peak-to-peak.
OUTPUTS
Dout, DATA OUTPUT - The digital data output is
primarily used for cascading the DACs and may be fed into
Din of the next stage.
3-51
II
®
MC145040
MC145041
MOTOROLA
•
Advance Information
8-Bit AID Converters
With Serial Interface
C ERAMIC
CASE 732
Silicon-Gate CMOS
II
The MC145040 and MC145041 are low-cost 8-bit AID Converters with serial interface ports to provide communication with microprocessors and microcomputers.
The converters operate from a single power supply with a maximum nonlinearity of
± 'h lSB over the full temperature range. No external trimming is required.
The MC145040 allows an external clock input (AID ClK) to operate the dynamic
AID conversion sequence. The MC145041 has an internal clock and an end-ofconversion signal (EGC) is provided.
• Operating Voltage Range: VDD = 4.5 to 5.5 Volts
• Successive Approximation Conversion Time:
MC145040 - 10 I(S (with 2 MHz AID ClK)
MC145041 - 20 I(S Maximum (Internal Clock)
11 Analog Input Channels with Internal Sample and Hold
0- to 5-Volt Analog Input Range with Single 5-Volt Supply
Ratiometric Conversion
Separate Vref and VAG Pins for Noise Immunity
Monotonic Over Voltage and Temperature
No External Trimming Required
Direct Interface to Motorola SPI and National MICROWIRE Serial Data Ports
TTL/NMOS-Compatible Inputs May Be Driven with CMOS
Outputs are CMOS, NMOS, or TTL Compatible
Very low Reference Current Requirement
low Power Consumption: 11 mW
Internal Test Mode for Self Test
PLASTIC
CASE 738
PLASTIC LEADED
CHIP CARRIER (PLCC)
CASEnS
ORDERING INFORMATION
MC14XXXX
l
TT
SUffiX
1
2
~P
I- L
'-FN
2.5 V $ Vref $ VOO
Vref=VOO
Plastic ( - 40 to + 85°C)
Ceramic (- 55 to + 125°C)
PLCC (-40 to +85°C)
BLOCK DIAGRAM
AND
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ANB
11
AN9
12
ANlO
AUTO· ZEROED
COMPARATOR
ANALOG
MUX
INTERNAL TEST Vref+VAG
2
VOLTAGE OF
Din
°out
17
16
IS 15
SCLK_1:...::8_ _ _ _~
19
AID CLK IMC145040 ONLY)::jL==~~===r_ _ j - - - - - - - - - - - - - - - - - - - - - . l
EOC (MC145041 ONLY)
19
MICROWIRE is a trademark of National Semiconductor
This document contains information on a new product. Specification and information herein are subject to change without notice.
3-52
VOO=PIN 20
VSS-PIN 10
MC145040, MC145041
MAXIMUM RATlNGS* (For all product grades)
-
Symbol
Parameter
Value
Unit
-0.5to +7.0
V
Vref
DC Reference Voltage
VAGtoVDD+O.l
V
VAG
Analog Ground
VDD
DC Supply Voltage (Referenced to VSS)
Vin
V out
lin
lout
VSS-O.l to Vref
V
DC Input Voltage, Any Analog or Digital
Input
VSS-l.5to
VDD+ 1.5
V
DC Output Voltage
VSS-0.5 to
VDD+0.5
V
DC Input Current, per Pin
±20
mA
DC Output Current, per Pin
±25
mA
±50
mA
IDD,ISS OC Supply Current, VOD and VSS Pins
T stg
Storage Temperature
TL
-65 to + 150
Lead Temperature (8-Second Soldering)
260
This device contains protection circuitry to
guard against damage due to high static voltages
or electric fields. However, precautions must be
taken to avoid applications of any voltage higher
than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and
V out should be constrained to the range VSS :s
(Vin or V out ) :S VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD.) Unused outputs must be left open.
°C
JOC---
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Operation Ranges below.
OPERATION RANGES (Applicable to Guaranteed Limits for all product grades)
Suffix
Symbol
Parameter
L1
L2
Pl, FNl
P2, FN2
Unit
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
V
V
VOD
DC Supply Voltage (Referenced to VSS)
Vref
DC Reference Voltage (Note 1)
VAG +2.5 to VDD
VDD
VAG+2.5toVDD
VDD
VAG
Analog Ground (Note 1)
VSS to Vref-2.5
VSS
VSS to V re f- 2.5
VSS
V
VAl
Analog Input Voltage (Note 2)
VAG to Vref
VAG to Vref
VAG to Vref
VAG to Vref
V
VSS to VOD
-55 to + 125
VSS to VDD
VSS to VDD
VSS to VOD
V
-55 to + 125
-40 to +85
-40 to +85
°C
Vin, V out Digital Input Voltage, Output Voltage
TA
Operating Temperature
NOTES: .
1. Reference voltages down to 1.0 V (Vref - VAG = 1.0 V) are functional, but the AI D Converter Electrical Characteristics are not guaranteed.
2. VSS:S VAI:S VAG produces an output of $00 and Vref:S VAI:S VDD produces an output of $FF. See VAG and Vref pin descriptions.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, Full Temperature and Voltage Ranges Per Operation Ranges Table)
Symbol
Parameter
Test Conditions
Guaranteed
Limit
Unit
VIH
Minimum High-Level Input Voltage
(Din' SCLK, CS, A/O CLK)
2.0
V
VIL
Maximum Low-Level Input Voltage
(Oin, SCLK, CS, AID CLK)
0.8
V
VOH
Minimum High-Level Output Voltage (Dout)
(EOC)
(D out , EOC)
lout = - 200 p.A
lout= -100 p.A
lout= -20 p.A
2.4
2.4
VDD-O.l
V
VOL
Maximum Low-Level Output Voltage (Oout)
(EOC)
(Dout, EOC)
lout= + 1.6 mA
lout= + 1.0 mA
lout= 20 p.A
0.4
0.4
0.1
V
Maximum Input Leakage Current
(Din, SCLK, CS, AID ClK)
Vin = VSS or VDD
±2.5
p.A
lin
10Z
Maximum Three-State Leakage Current (Dout)
Vout=VSS or VDD
± 10
vA
IDD
Maximum Power Supply Current
Vin = VSS or VDD, All Outputs Open
MC145040: AID CLK=2 MHz
2
mA
Iref
Maximum Static Analog Reference Current (Vref)
Vref= VDO
VAG=VSS
10
vA
IAI
Maximum Analog Mux Input Leakage Current
between all deselected inputs and any selected
input. (ANO-AN10)
VAl = VSS to VOD, L1 and L2 Suffix
Pl,P2, FN1, FN2 Suffix
± 1000
±400
nA
3-53
II
MC145040, MC145041
AID CONVERTER ELECTRICAL CHARACTERISTICS
(MC145040: 1 MHz [:VAlIO~
O.B
II
Figure 2
Figure 1
EOG
"~or
dE'"
0.4
2.4
td
SGLK
Dout
Figure 3
Figure 4
SGLK
EOG
Figure 5
Figure 6
VOD
VDD
TEST
TEST
1.8 k
POINT
POINT
,.....---....,EOC
DEVICE
DEVICE
UNDER
12k
UNDER
24 k
TEST
TEST
All diodes are silicon
All diodes are silicon
Figure 7. Test Circuit
Figure 8. Test Circuit
3-55
3k
MC145040, MC145041
PIN DESCRIPTIONS
DIGITAL INPUTS AND OUTPUTS
CS (Pin 15)
II
Active-low chip select input. CS provides three-state control of Dout. CS at a high logic level forces Dout to a highimpedance state. In addition, the device recognizes the falling
edge of CS as a serial interface reset to provide synchronization between the MPU and the AID converter's serial data
stream. To prevent a spurious reset from occurring due to
noise on the CS input, a delay circuit has been included such
that a CS signal of duration ::s 1 AID ClK period ~C145040)
or ::s500 ns (MC145041) is ignored. A valid CS signal is
acknowledged when the duration is 2: 3 AID ClK periods
(MC145040) or 2:3 fLS (MC145041).
ANALOG INPUTS AND TEST MODE
ANO through AN10 (Pins 1-9, 11, 12)
Analog multiplexer inputs. The input ANa is addressed by
loading $0 into the serial data input, Din. ANl is addressed by
$1, AN2 by $2 ... AN 1a via $A. The mux features a breakbefore-make switching structure to minimize noise injection
into the analog inputs. The source impedance driving these inputs must be ::; 10 kr!. NOTE: $B addresses an on-chip test
voltage of (Vref + VAG)/2, and produces an output of $80 if
the converter is functioning properly. However, a ± 1 lSB
deviation from $80 occurs in the presence of sufficient system
noise (external to the chip) on VOD, VSS, Vref, or VAG.
POWER AND REFERENCE PINS
VSS and VDD (Pins 10 and 20)
CAUTION
A reset aborts a conversion sequence, therefore
high-to-Iow transitions on CS must be avoided
during the conversion sequence.
Dout (Pin 16)
Serial data output of the AID conversion result. The 8-bit
serial data stream begins with the most significant bit and is
shifted out on the high-to-Iow transition of SClK. Dout is a
three-state output as controlled by CS. However, Dout is
forced into a high-impedance state after the eighth SClK, independent of the state of CS. See Figures 9, 10, 11, or 12.
Din (Pin 11)
Serial data input. The 4-bit serial data stream begins with
the most significant address bit of the analog mux and is
shifted in on the low-to-high transition of SClK.
Device supply pins. VSS is normally connected to digital
ground; VDD is connected to a positive digital supply voltage.
VDO - VSS variations over the range of 4.5 to 5.5 volts do
not affect the AID accuracy. Excessive inductance in the VDD
or VSS lines, as on automatic test equipment, may cause AID
offsets > Y, lS B .
VAG and Vref (Pins 13 and 14)
Analog reference voltage pins which determine the lower
and upper boundary of the AID conversion. Analog input
voltages 2:V ref produce an output of $FF and input voltages
::; VAG produce an output of $00. CAUTION: The analog input voltage must be 2: VSS and::; VDD. The AID conversion
result if ratiometric to Vref - VAG as shown by the formula:
_ V
. _[output code x (V
Vm $FF
ref
AG
;1 + quantizing + linearity
error
J error
SCLK (Pin 18)
Serial data clock. The serial data register is completely
static, allowing SClK rates down to DC in a continuous or intermittent mode. SClK need not be synchronous to the AID
ClK (MC145040) or the internal clock (MC145041). Eight
SClK cycles are required for each simultaneous data transfer,
the low-to-high transition shifting in the new address and the
high-to-Iow transition shifting out the previous conversion
result. The address is acquired during the first four SCLK
cycles, with the interval produced by the remaining four cycles
being used to begin charging the on-chip sample-and-hold
capacitors. After the eighth SClK, the SClK input is inhibited
(on-chip) until the conversion is complete.
Vref and VAG should be as noise-free as possible to avoid
degradation of the AID conversion. Noise on either of these
pins will couple 1: 1 to the analog input signal, i.e. a 20 mV
change in Vref can cause a 20 mV error in the conversion
result. Ideally Vref and VAG should be single-point connected
to the voltage supply driving the system's transducers.
PIN ASSIGNMENTS
N
~
Z
..:
c
c
0
:z
..:
:>
*
20
19
AN3
AID ClK (Pin 19, MC145040 only)
AID clock input. This pin clocks the dynamic AID conversion sequence, and may be asynchronous and unrelated to
SClK. This signal must be free running, and may be obtained
from the MPU system clock. Deviations from a 50% duty
cycle can be tolerated if each half period is > 238 ns.
18
AN4
Din
AN5
16
AN7
Vref
10 11
co
en
C)
~ >en ~
End-of-conversion output. EOC goes low on the negative
edge of the eighth SClK. The low-to-high transition of EOC
indicates the AID conversion is complete and the data is ready
for rransfer.
Dout
CS
AN6
EOC (Pin 19, MC145041 only)
SCLK
12
0
t!J
Z
..:
..:
ANO
VDD
ANI
*
AN2
SCLK
AN3
Din
AN4
Dout
AN5
CS
AN6
Vref
AN7
VAG
ANa
AN10
VSS
AN9
:>
*NOTE:
AID ClK (MC145040)
EOC (MC145041)
3-56
3:
o
.....
~l
Dout
I~_
j-,------,.
I __ . __
o
~
5='
3:
o
.....
~
SClK
CJ1
INPUT
Din
~
CJ1
i.
--
--~ ~ rn
:1
I
SAMPLEA"LOG-t
--~
I
I
SHifT IN NEW MUX AOORESS, SiMULTANEOUSLY SHifT OUT PREVIOUS CONVERSION VALUE
2ClK....
. .,.1AID
CYCLES
•
AID CONVERSION INTERVAL
20 AID ClK CYCLES
RESET
RESET
Figure 9. MC145040 Timing Diagram
Utilizing CS to Three-State D out
w
tn
.......
~
Dout
SClK
~------
0,.
--~
SAMPLE ANALOG INPUT
MSB
~---- SHIFT IN NEW MUX ADDRESS, SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
I
-+
12
NOC~
CYCLES
RESET TO
INITIALIZE
.1.
.1
AID CONVERSION INTERVAL
20 AiD ClK CYCLES
Figure 10. MC145040 Timing Diagram
Not Utilizing CS, AID Conversion Interval Controls Three-State
NOTES:
D7, D6, D5. . DO = The result of the previous AI D conversion.
A3, A2, A 1, AO = The mux address for the next AI D conversion.
II
o
~
.....
II
I
1.,.----.,
tS
~------------------~
Dout
SClK
MSB
SAMPll ANALOG INPUT
lJin
EGC
J
~
n
~
o
.....
I
==~
I
-10( < 12 I's ~ :-s 20 I'S ~
AID CONVERSION INTERVAL
SHIFT IN NEW MUX ADDRESS, SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
RESET
RESET
Figure 11. MC145041 Timing Diagram
Utilizing CS to Three-State D out
(,.)
cJ,
cs
OJ
Dout
T
SCLK
MSB
EDC
-j
JJI
I
I"
RESET TO
INITIALIZE
~
SA"'ll ANA",' INPUT
Din
SHIFT IN NEW MUX ADDRESS, SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
_I"
I
<
12
Figure 12. MC145041 Timing Diagram
Not Utilizing CS, AID Conversion Interval Controls Three-State
NOTES:
D7, D6, D5 ... DO = The result of the previous AI D conversion.
A3, A2, Al, AO=The mux address for the next AID conversion.
IlS
I
_1- AID CONVERSION INTERVAL _I
~:-S2ol's
~
(J1
o
.?
3:
I
.
3:
o
.....
~
(J1
o
~
.....
MC145040, MC145041
APPLICATIONS INFORMATION
DESCRIPTION
This example application of the MC145040/MC145041
ADCs interfaces three controllers to a microprocessor and
processes data in real-time for a video game. The standard
joystick X-axis lIeft/right) and Y-axis (up/down) controls as
well as engine thrust controls are accommodated.
Figure 13 illustrates how the MC145040/MC145041 is used
as a cost-effective means to simplify this type of circuit design.
Utilizing one ADC, three controllers are interfaced to a CMOS
or NMOS microprocessor with a serial peripheral interface
(SPI) port. Processors with National Semiconductor's
MICROWIRE serial port may also be used. Full duplex operation optimizes throughput for this system.
DIGITAL DESIGN CONSIDERATIONS
Motorola's MC68HC05C4 CMOS MCU may be chosen to
reduce power supply size and cost. The NMOS MCUs may
be used if power consumption is not critical. A VDD to VSS
0.1 fLF bypass capacitor should be closely mounted to the
ADC.
Both the MC145040 and MC145041 will accommodate all
the analog system inputs. The MC145040, when used with a 2
MHz MCU, takes 24 ps to sample the analog input, perform
the conversion, and transfer the serial data at 1 MHz. Thirtytwo AID Clock cycles (2 MHz at input pin 19) must be provided and counted by the MCU after the eighth SCLK before
reading the ADC results. The MC145041 has the end-ofconversion (EOC) signal (at output pin 19) to define when data
is ready, but has a slower 40 pS cycle time. However, the 40 pS
is constant for serial data rates of 1 MHz independent of the
MCU clock frequency. Therefore, the MC145041 may be used
with the CMOS MCU operating at reduced clock rates to
minimize power consumption without sacrificing ADC cycle
times, with EOC being used to generate an interrupt. (The
MC145041 may also be used with MCUs which do not provide
a system clock.)
for buffer amplifiers. Separate lines connect the Vref and VAG
pins on the ADC with the controllers to provide isolation from
system noise.
Although not indicated in Figure 13, the Vref and controller
output lines may need to be shielded, depending on their
length and electrical environment. This should be verified during prototyping with an oscilloscope. If shielding is required, a
twisted pair or foil-shielded wire (not coax) is appropriate for
this low frequency application. One wire of the pair or the
shield must be VAG.
A reference circuit voltage of 5 volts is used for this application. The reference circuitry may be as simple as tying VAG to
system ground and Vref to the system's positive supply. (See
Figure 14.) However, the system power supply noise may require that a separate supply be used for the voltage reference.
This supply must provide source current for Vref as well as
current for the controller potentiometers.
A bypass capacitor across the Vref and VAG pins is recommended. These pins are adjacent on the ADC package which
facilitates mounting the capacitor very close to the ADC.
ANALOG DESIGN CONSIDERATIONS
Controllers with output impedances of less than 10 kilohms
may be directly interfaced to these ADCs, eliminating the need
3-59
SOFTWARE CONSIDERATIONS
The software flow for acquisition is straightforward. The
nine analog inputs, ANO through ANa, are scanned by reading
the analog value of the previously addressed channel into the
MCU and sending the address of the next channel to be read
to the ADC, simultaneously. All nine inputs may be scanned in
a minimum of 216 ps (MC145040) or 360 pS (MC145041).
If the design is realized using the MC145040, 32 AID clock
cycles (at pin 19}must be counted by the MCU to allow time
for AID conversion. The designer utilizing the MC145041 has
the end-of-conversion signal (at pin 19) to define the conversion interval. EOC may be used to generate an interrupt,
which is serviced by reading the serial data from the ADC. The
software flow should then process and format the data, and
transfer the information to the video circuitry for updating the
display.
II
MC145040, MC145041
+5 V
IVDD
Vref!
LEFT/RIGHT
-
CONTROLLER
#1
Cs
ANO
UP/DOWN
Din
ANl
ENGINE THRUST
°out
ADC
LEFT/RIGHT
II
....--
CONTROLLER
#2
AN3
UPIDOWN
ENGINE THRUST
LEFT/RIGHT
5 VOLT
REFERENCE
CIRCUIT
CONTROLLER
#3
MC145040
AN4
--'"
UP/DOWN
A/D CLK
IMC1450401
EOC
AN5
MC145041
AN6
ENGINE THRUST
AN10
AN8
I
-=1-VSS
~
DIGITAL +V
DO NOT CONNECT
AT Ie
Vref
5V
SUPPLY
MC145040
MC145041
TO
JOYSTICKS
ANALOG GND
00 NOT CONNECT
DIGITAL GND
AT IC
Figure 14. Alternate Configuration Using the Digital
Supply for the Reference Voltage
3-60
.
MC68HC05C4
MC6805K2
MC6805S2
•
VIDEO
CIRCUITRY
•
VIDEO
MONITOR
Figure 13. Joystick Interface
ANALOG +V
,p
SPI PORT
IMC1450411
AN99
AN7
VAG
}
SCLK
AN2
CMOS Decoders/Display Drivers
4-1
II
CMOS DECODERS/DISPLAY DRIVERS
Device
Number
Function
MCl4495-1
Hexadecimal-to-7-Segment Latch/ Decoder
ROM/Driver
7-Segment LED Display Decoder/Driver with
Serial Interface
BCD-to-7-Segment Latch/ Decoder/Driver
BCD-to-7-Segment Latch/Decoder/Driver with
Ripple Blanking
BCD-to-7-Segment Latch/Decoder/Driver for
Liquid Crystals
BCD-to-7-Segment Latch/Decoder/Driver with
Ripple Blanking
High-Current BCD-to-7-Segment Decoder/Driver
BCD-to-7-Segment Decoder
Serial Input Multiplexed LCD Driver (Master)
Serial Input Multiplexed LCD Driver (Slave)
LCD Driver with Serial Interface
MCl4499
MC14511B
MC14513B
MC14543B
MC14544B
MC14547B
MC14558B
MC145000
MC145001
MC145453
II
Display Type
LCD
Muxed LCD
LED,
Incandescent,
Fluorescent*
LED,
Incandescent
Input Format
Drive Capability
Per Package
Parallel BCD
7 Segments
Serial Binary
[Compatible with
the Serial Peripheral
Interface (SPI)
on CMOS MCUsl
33 Segments
or Dots
Serial Binary
[Compatible with
the Serial Peripheral
Interface (SPI)
on CMOS MCUsJ
48 Segments
or Dots
44 Segments
or Dots
Parallel BCD
7 Segments
Serial Binary
28 Segments +
[Compatible with
4 Decimal Points
the Serial Peripheral
Interface (SPI)
on CMOS MCUsl
LED
Parallel Hex
7 Segments +
A thru F Indicator
(Interfaces to
Display Drivers)
Parallel BCD
7 Segments
Display Control
Inputs
Segment Drive
Current
Device
Number
Number
of Pins
Blank
Blank, Ripple Blank
-1 mA
-1 mA
MC14543B
MC14544B
16
18
20 p.A
MCl45453
40
-200 p.A
MCl45000
24
-200 p.A
MCl45001
18
25 mA
25 mA
MC14511B
MCl4513B
16
18
65 mA
MC14547B
16
50 mA
MCl4499
18
10 mA*
MCl4495-1
16
MCl4558B
16
On-Chip
Latch
...
...
...
...
...
...
...
...
Blank, Lamp Test
Blank, Ripple Blank,
Lamp Test
Blank
Oscillator
(Scanner)
...
Ripple Blank,
Enable
* Absolute maximum working voltage = 18 V
* On-chip current-limiting resistor
4-2
®
MC1449S·1
MOTOROL.A
Advance Information
CMOS MSI
(LOW·POWER COMPLEMENTARY MOS)
HEXADECIMAL-TO-SEVEN SEGMENT LATCH/
DECODER ROM/DRIVER
The MCl4495-1 is constructed with CMOS enhancement-mode
devices and NPN bipolar output drivers in a monolithic structure. The
circuit provides the functions of a 4-bit storage latch. The decoder is implemented utilizing a mask-programmable ROM. With a 5-volt power
supply, it can be used without resistor interface to drive seven segment
LEOs. The series output resistors of. typically, 290 ohms are internal to
the·device.
The MCl4495-1 is an improved version of the MC14495 with CMOS
input levels and decreased propagation delays.
Applications include MPU systems display driver, instrument display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
•
•
Low Logic-Circuit Power Dissipation
High Current-Sourcing Outputs with Internal limiting Resistors
•
•
Latch Storage of Code
Supply Voltage Range = 4.5 to 18 V
•
•
CMOS Input Switching Levels
Standard ROM Provides Hex-to-Seven Segment Decoding
•
Other ROM Options Available Upon Request (Contact your Motorola
Sales Office)
•
Chip Complexity: 187 FETs plus 9 NPNs or 49 Equivalent Gates
HEXADECIMAL-TO-SEVEN SEGMENT
LATCH/DECODER ROM/DRIVER
~ftI!IIIlItt.
,J 'f«<1lU ~ u '6~l~ ~ ij
1
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
CASE 620
PLASTIC PACKAGE
CASE 648
ORDERING INFORMATION
MC14XXX
1I e
..... VOO
f'--'C
~14
31 9
c
b P13
51 A
a P12
61 B
11
~16
41 h+i
71
L 1 Ceramic Package
P1 Plastic Package
d ~15
2[ f
BLOCK DIAGRAM
Suffix Denotes
E
a
-
g 'b
e'
d
j Pl1
LE
81 VSS
D
blO
C
9
ALPHANUMERIC DISPLAY
13
14
15
.'-'.
0
2
4
LE
V DD = Pin 16
Vss= Pin 8
This document contains information on a new product. Specifications and Information herein
are subject to change without notice
4-3
TRUTH TABLE
c
d
g
h+i
7 8 9 10 11 12 13 14 15
5 6
1 2 3 4
b
e
3
-,i -,le.]e,; 1,-' -'U-Tri
I I ":-"
,,-, ,- , - '
:i,:'~ ::!'-:! ':';E.: "t"
.1-.
l-"-- I~_-LJ
~,-,:
12
INPUTS
OUTPUTS
D C
B
A a
b
c
d
e
f
9
0
0
0
0
0
0
0
0
0 0 1
0 1 0
1 0 1
1 1 1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
1
0
1
0
0
0
0 0
0 0
1 0
1 0
Open
Open
Open
Open
2
3
0
0
0
0
1
1
1
1
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 1
1
1
1
1
0 0
1 0
1 1
0 0
1
1
1 0
1 0
1 0
0 0
Open
Open
Open
Open
4
5
6
7
1
1
1
1
0
0
0
0
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
1
1 1
1 0
0 1
1 1
0
0
1
1
1
1
1
1
1
Open
Open
Open
Open
8
1
1
1
1
1
1
1
1 0
1 0
1 1
1 1
1
0
1
1
0
1
1
1
1
1
1
1
Open
Open
Open
0
0 1 0 0 1
1 0 1 1 1
0 1 0 0 1
1 1 0 0 0
1
1
1
1
1
0
1
1
1
h+i
J
DISPLAY
0
1
9
A
b
C
d
E
F
II
MC14495·1
MAXIMUM RATINGS (Voltages referenced to Vssl.
Rating
Symbol
Value
Unit
VOO
-0.5 to+ 18
V
Yin
-0.5 to VDO + 0.5
V
I
10
mA
DC Supply Voltage
Input Voltage, All Inputs
DC Current Drain per Input Pin
Operating Temperature Range
Storage Temperature Range
Maximum Continuous Output Power
(Source) per Output @ 25°C
Pins 1,2,3,12,13,14,15
Pin 4
t
I
TA
-40 to+85
°C
Tstg
-65 to+ 150
°C
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high inpedance circuit. For proper operation it is
recommended that Vin and Vout be constrained to the range VSS .;;; (V in or Vout)
.0;;;; VOD·
mW
POHmax:j:
50
100
POHmax= IOH (VOO-VOH)
ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS)
-40°C
Voo
Symbol
Characteristic
Input Voltage #
(VO=3.8 or 0.5 V)
(VO=8.8 or 1.0 V)
(VO= 13.8 or 1.5 V)
"0" Level
(VO=0.5 or 3.8 V)
(VO = 1.0 or 8.8 V)
IVO= 1.5 or 13.8 V)
"1" Level
VIH
VOL
Output Drive Voltage: a-g, h+i
(JOH= o mAl
IIOH= 5 mAl
IIOH= 10 mAl
VOH
Max
Min
Typ
Max
Min
Max
5
10
15
-
1.5
3.0
4.0
-
1.5
3.0
4.0
-
-
2.25
4.50
6.00
1.5
3.0
4.0
3.5
7.0
11.0
2.75
5.50
8.25
-
-
-
3.5
7.0
11.0
0
0
0
0.05
0.05
0.05
-
0.05
0.05
0.05
-
4.0
2.05
-
Unit
V
-
5
10
15
3.5
7.0
11.0
-
5
10
15
-
0.1
0.1
0.1
-
4.0
2.45
1.3
-
4.0
-
0.8
4.8
3.0
1.7
9.0
7.4
-
9.0
7.2
5.8
4.4
9.8
8.0
6.7
5.3
14.0
12.0
10.4
8.8
7.2
5.6
14.8
13.0
11.7
10.3
8.8
7.1
-
0.3
-
-
-
-
-
-
10
(JOH= o mAl
1I0H= 5 mAl
IIOH= 10 mAl
1I0H= 15 mAl
1I0H=20 mAl
(IOH=25 mAl
15
V
-
V
V
5
(JOH= o mAl
(IOH= 5 mAl
(JOH= 10 mAl
IIOH= 15 mAl
604
5.3
14.0
12.2
10.9
9.7
8.5
704
J
85°C
Min
VIL
Output Voltage: a - g, h + i
Yin = VOD or 0, lout = 0 p.A
Output Sink Current:
IVOL =004 V)
(VOL =0.5 V)
1VOL = 1.5 V)
25°C
V
-
-
204
-
-
-
9.0
6.9
5.0
3.05
-
-
V
-
14.0
11.7
9.6
7.45
5.25
3.0
-
-
± 1.0
p.A
± 1.0
p.A
V
-
mA
IOL
5
10
15
-
-
0.5
1.00
1.25
±0.1
-
±0.OOOO1
±0.1
-
-
-
-
-
-
Input Current Il Device)
lin
15
-
Input Current IP Device)
lin
15
-
±0.3
-
±O.OOOOl
±0.3
-
Input Capacitance
Cin
-
-
-
-
5.0
7.5
-
-
pF
Quiescent Current
Vin=O or VDD, 10ut=0 p.A
IPer Package)
IDD
5
10
15
-
0.3
1.5
3.0
-
0.08
-
0040
0.85
0.2
1.0
2.0
mA
-
0.25
1.25
2.50
Total Supply Current" t
(Dynamic plus Quiescent,
Per Package)
ICl = 50 pF on all outputs, all
buffers switching)
IT
-
-
-
-
IT= (1.9 p.A/kHz)f+ IDO
IT= 13.8 p.A/kHz)f+ 100
IT=15.7 p.A/kHzlf+IOD
5
10
15
tTo calculate total supply current at loads other than 50 pF: ITICl) = ITI50 pF) + 3.5 x 10- 31Cl - 50) VDDf
where: IT is in p.A (per package), Cl in pF, VDD in V, and f in kHz is input frequency.
"The formulas given are for the typical characteristics only at 25°C.
#Noise immunity specified for worst-case input combination. Noise margin tor oothi' and u i.,v.,i ~ 1.0 V iiiiii @ V[)D=5.0 V
2.0 V min @ VDD= 10 V
2.5 V min @ VOD= 15 V
4-4
p.A
MC14495·1
SWITCHING CHARACTERISTICS
(CL=50 pF, TA=25°C)
Voo
Characteristic
Output Rise Time, a - g, h + i Outputs (Figure 1)
Output Fall Time, a - g, h + i Outputs (Figure 1)
Output Fall Time, j Output
(Figures 3 and 4)
Propagation Delay Time, A, B, C, D to a - g,
h + i Outputs (Figure 2)
Symbol
Hold Time, LE to A, B, C, D (Figure 7)
Latch Enable Pulse Width, LE (Figure 7)
5
10
15
-
210
145
90
450
300
200
5
10
15
-
1.5
1.3
1.1
3.5
2.75
2.25
5
10
15
-
-
105
40
30
250
100
75
-
ns
tPLH
5
10
15
5
10
15
-
935
2400
-
340
-
230
900
500
-
lB.O
-
7.0
3.5
2.0
-
11.0
-
B.O
25.0
20.0
10.0
-
P.s
9.0
5.0
p's
tPLZ
5
10
15
5
10
15
-
4.0
-
BOO
-
-
400
200
1500
1000
500
ns
ns
tPLH
-
1300
-
500
350
3000
1500
1000
5
10
15
-
16.0
6.0
5.0
30.0
15.0
10.0
5
10
15
-
14.0
8.0
6.0
30
20
15
10.0
5.0
4.0
25
15
10
/Ls
-
ns
5
10
15
-
p's
p's
tPLZ
-
5
10
15
tsu
th
tw
-
5
10
15
100
65
65
35
25
25
-
5
10
T5
125
75
75
45
30
25
-
5
10
15
525
200
140
210
80
55
OUTPUT CIRCUIT
(Except Pin 11)
VDD
t
Unit
ns
tTHL
tpZL
Setup Time, A, B, C, D to LE (Figure 7)
Max
p's
tpHL
Propagation Delay Time, LE to j Output
(Figures 4 and 6)
Typ
lTHL
tpZL
Propagation Delay Time, LE to a - g, h + i Outputs
(Figure 5)
Min
ns
tPHL
Propagation Delay Time, A, B, C, D to j Output
(Figures 3 and 4)
V
tTLH
290 {)
-= VSS
4-5
-
-
ns
-
ns
II
MC14495·1
INPUT/OUTPUT FUNCTIONS
SEGMENT DRIVER (a, b, C, d, e, f, g, h + i; PINS 12, 13, 14,
15,1,2,3,4)
The segment drivers are emitter-follower NPN transistors.
To limit the output current, a resistor, typically 290 ohms, is
integrated internally at each output. Therefore, external
resistors are not necessary when driving an LED at the
supply voltage of VDD = 5.0 volts.
INPUT DATA (A, B, C, D; PINS 5, 6, 9,10)
The inputs A, B, C, and D are fed to a 4-bit latch which is
controlled by the Latch Enable input.
LATCH ENABLE (LE; PIN 7)
The data on inputs A, B, C and D will pass through the
latch. and will be decoded immediately when LE is low. In this
mode of operation the circuit is performing the function of a
conventional decoder/driver. The data may be loaded into
the latch when LE = low and will be latched with the riSing
edge of LE. The data will remain stored as long as LE is high.
OUTPUT 0; PIN 11)
This open-drain output is activated (goes low) whenever
inputs A, B, C, and D are all set to a logic one. Otherwise the
output is in the high-impedance state. See the truth table.
II
SWITCHING WAVEFORMS
Figure 2
Figure 1
Segment
Outputs
Segment
Outputs
Figure 3
A,B,C,O'5...0_o/c_O_ _ _ _ _ _ ,
~ ~LZ
:.j
j Output
---.....
tpZL
90%
Figure 5
1
A,B,C,D _ _ _ _- - J
Figure 4
VOO
LE
20 k
Output
Under
Test
Segment
Outputs
4-6
MC14495·1
SWITCHING WAVEFORMS
Figure 6
A,B,C,D
LE
j Output
Figure 7
A,B,C,D
/
----~_50%----II
k
_-_f_t_p_~
~'h~
50%
LE
II
TYPICAL CIRCUIT @ VOO = 5.0 V
VDD=5.0 V
t
16
12
A-5
13
14
B- 6
15
MCl4495-1
1
C- 9
2
a
a
b
,I'"
,1:1,
c
d
e
f
g
D
-
3
10
7
LE
8
11
4
~l L
h + i
j (Open Drain)
-1
d
A through F
Indicator
~, LED
~::x
4-7
Common
Cathode
LED
Display
®
MCl4499
MOTOROLA
CMOS LSI
ILOW-POWER COMPLEMENTARY MaS)
7-SEGMENT LED DISPLAY DECODER/ DRIVER
WITH SERIAL INTERFACE
The MCl4499 is a 7-segment alphanumeric LED decoder/driver with
a serial interface port to provide communication with CMOS microprocessors and microcomputers. This device features NPN output drivers
which allow interfacing to common cathode LED displays through
external series resistors.
I
•
•
•
•
7-SEGMENT LED DISPLAY
DECODER/DRIVER
WITH SERIAL INTERFACE
High-Current Segment Drivers on Chip
CMOS MPU Compatible Input Levels
Wide Operating Voltage Range: 4.5 to 6.5 V
Drives Four Characters with Decimal Points
P SUFFIX
PLASTIC PACKAGE
CASE 707
FIGURE 1 -
BLOCK DIAGRAM
Decimal
Data
Clock
Segment
Outputs
Segment~--------~--------~'
Decoder
A
~
______________---.
I}
II
III
IV
Osc
.. Transparent Latch
VDD= Pin 18
VSS=Pin9
4-8
Character
Selectors
MC14499
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit. For proper operation it is recommended that Vin and V out be constrained
to the range VSS .;;; (Vin or V out ) .;;; VOO.
MAXIMUM RATINGS (Voltages referenced to Vss)
Rating
Symbol
DC Supply Voltage
Input Voltage, all Inputs
Operating Temperature Range
TA
Storage Temperature Range
Value
Unit
VOO
-0.5 to+ 7.0
Vdc
VIN
-0.5 to VDD+ 0.5
Vdc
TSTG
o to + 70
oC
-65 to+ 150
°C
ELECTRICAL CHARACTERISTICS (VOO = 4.5 to 6.5 V)
Characteristic
Pin
Min.
Input Voltage
'O'level
'1'Ievel
Input Current (VIN == 0 to VOO)
5,12,
13
Oscillator Input Voltage '0' level
6
VIL
VIH
liN
'l'level
VOSC==VOO
Segment Driver Voltage below VOO
IOUT==50mA
IOUT==10mA
Segment Driver OFF Leakage
0.3xV OO
VOUT== 0.8 V
VOUT= 0.5 V
Quiescent Current
Min.
0. 7xV OO
±0.1
0. 25xV OO
100
-100
1-4, VOO14,15, -VSOH
16,17
0. 75xV OO
30
-30
-
Typ.
70 0
Max.
0.45xV OO 0. 3xV OO
0. 55xV OO
±0.001
±0.1
0. 3xV OO 0. 25xV OO
0. 7xV OO
50
80
-50
-80
1.1
0.8
-
0.9
0.7
100
-
1
50
5.5
-0.2
8
-2
-
7,8,
10,11
IOOH
IDOL
6
-0.2
0. 7xV OO
0.8xVDO
10
-10
1.0
0.75
Unit
Max.
0. 3xV OO Vdc
Vdc
± 1.0
IJ,A
0. 2xV OO Vdc
Vdc
IJ,A
IJ,A
1.1
0.8
Vdc
Vdc
100
IJ,A
4
-0.1
mA
mA
18
VIN == 0, lOUT = 0, COSC == 15 nF
Maximum Power Dissipation
1
-
0.5
1
1
mA
500
-
-
500
500
mW
SWITCHING CHARACTERISTICS (VOO = 5V ± 10 0 /0, T A = 0 to 70 oC)
Ch aracteristic
Min.
10FF
VOUT== 0
Digit Drivers
Source (On)
Sink (Off)
Max.
0. 7xV OO
VILO
VIHO 0. 75xV OO
IIOL
IIOH
Oscillator Input Current VOSC==O
25 0
00
Symb.
Fig.
PIN ASSIGNMENT
Symbol
Min.
Clock High time
3
tCH
2
IJ,S
Clock Low time
3
tCL
2
IJ,S
2
Clock Rise time
3
tCR
2
IJ,S
3
2
IJ,S
Max.
Unit
d
VDD
18
17
16
b
Clock Fall time
3
tCF
Enable Lead time
3
tElead
200
ns
Enable Lag time
3
tElag
200
ns
5
Data
Data Set-up time
3
tOSup
200
ns
6
Osc
CL
13
Data Hold time
3
tOHold
1
IJ,S
IV
EN
12
Scanner Frequency*
5
l/tScan
50
Osc/Oigit Lead time
5
too
Osc/Segment Lead time
5
tos
10
IJ,S
II
10
Digit Overlap
5
tov
5
IJ,S
* Scanner Capacitance = 22nF.
4-9
300
Hz
10
IJ,S
4
9
8
III
9
VSS
15
14
11
II
MC14499
CIRCUIT OPERATION
The circuit accepts a 20-bit input, 16-bits for the four
digit display plus 4-bits for the decimal point - these
latter four-bits are optional.
SCANNER
The scanner frequency is determined by an on-chip oscillator, which requires an external frequency determining
capacitor. The capacitor voltage varies between two trigger
levels at the oscillator frequency.
The input sequence is the decimal point code followed by
the four digits, as shown in figure 2.
In order to enter data the enable input, EN, must be low,
O. The sample and shift are accomplished on the falling
clock edge, see figure 3. Data are loaded from the shift
register to the latches when EN goes high, = 1. While the
shift register is being loaded the previous data are stored
in the latches.
An external oscillator signal can be used, within the
recommended operating range of 200 to 800Hz - to
avoid flicker and digit overlap. For test purposes this
frequency can be increased up to 10kHz.
=>
I
A divide by four counter provides four non-over lapping
scanner waveforms corresponding to the four digits see figure 5.
If the decimal point is used the system requires 20 clock
;JUlses to load data, otherwise only 16 are required.
CASCADING
SEGMENT DECODER
The circuit may be cascaded in the following manner.
The code used in this matrix decoders is shown in
figure 6.
If a 1111 word is loaded into the decimal point latch, the
output of the shift register is switched to the decimal
point driver, see figure 4. Therefore, to cascade n four digit
display drivers a set-up is used which will firstly load
the 1111 cascading word:
OUTPUT DRIVERS
EN =0
2 Load 20-bits, the first four bits being 1, with 20
clock pulses.
There are two different drivers:
3 EN = 1, to load the latch
The segment and decimal point drivers; these are NPN
emitter followers with no current limiting devices.
4 Repeat steps 1 to 3 (n-1) times
The digit output buffers; These are short circuit
protected CMOS devices.
5 (nX20)-bits can be loaded into n circuits, with 1111
A typical application circuit is shown in figure 7.
as decimal point word to continue the cascading.
FIGURE 2 - INPUT SEQUENCE
+- time
Bit No.
120 119 118 117116 115 114 113112 111
j, ~ I 9
18
I 7 I 6 I 51 4 I 3 I 2 I 1 I
shift ~
III
III
'0,
'0,
'0,
'0,
~I 0 0 0 0
I~
Digit IV
:::... ... =..... ...
Digit III
Digit II
4-10
Digit I
Decimal Point
MC14499
FIGURE 3a - SERIAL INPUT, POSITIVE CLOCK
Cl
DIN
_ _ _ _-oJ 1'--+------'1 '--_ _ _ _0_2_
-
-
-
-=x___
DN
_ _ __
II
FIGURE 3b - SERIAL INPUT, NEGATIVE CLOCK
r-----
Cl
DIN _ _ _ _
D'_ _....J
=~~-£
LF-
~_-+-_---'I '--_______ ~____
FIGURE 4 - CASCADING MC 144995
DIGIT
DIGIT
SEGM
SEGM
---_~DATA
--'-_001 CLOCK
--+-_--trn
Me 14499
MC 14499
(0
( 2)
4-11
MC14499
FIGURE 5 - SCANNER WAVEFORMS
too
I Itosc
osc
tSCAN
DIGIT I
II
DIGIT
n
DIGIT
m
DIGITlSZ
tov
SEGMENT
OUTPUTS
tos
FIGURE 6 - SEGMENT CODE
0000
II
"
1000
Ci
0
L'
0001
0010
0011
0100
0101
0110
0111
,
I
,
,-,
,-,
1001
,
C
1010
:1, ,
-,
,,J
0
I,
I
1011
4-12
I
1100
,,
1101
' I
~,
I I
1110
dash
1111
blank
MC14499
FIGURE 7 - APPLICATION EXAMPLE
SEGMENT
OUTPUTS
t
(7)
~
a
~
~
b
c
,r-
d
MCI4499
IS
...
,
...
'
e
f
c~
9
III
mn
T
~NO
DIGIT
OUTPUTS
RI-8
~F ~F~"~" ~
(4)
T
11
I
"'." I
#1
10
tQl
II
III
III
0
I I
-
°#2
~.,
I
l
R1 - R8: 36-82n
C:
22 nF
....
VDD Typ: 5-6 V
IS max.: 40-50 mA
lOmax.:
81S max,
4-13
,-,
I"
--#3
III
0
V·'II'4
J.
~Q3
I
t"
....Q4
II
®
MC14511B
MOTOROLA
BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER
I
CMOS MS.
The MC14511 B BCD·to-seven segment latch/decoder/driver is con·
structed with complementary MOS (CMOS) enhancement mode de·
vices and NPN bipolar output drivers in a single monolithic structure.
The circu it provides the functions ofa 4-bit storage latch, an 8421
BCD-to-seven segment decoder, and an output drive capability. Lamp
test (LT), blanking (Si), and latch enable (LE) inputs are used to test
the display, to turn·off or pulse modulate the brightness of the
display, and to store a BCD code, respectively. It can be used with
seven-segment light emitting diodes (LED), incandescent, fluorescent,
gas discharge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display driver, computer/calculator display driver, cockpit display driver,
and various clock, watch, and timer uses.
(LOW-POWER COMPLEMENTARY MOS)
BCD-TO-SEVEN SEGMENT
LATCH/DECODER/DRIVER
1
P SUFFIX
L SUFfiX
•
CERAMIC PACKAGE
CASE 620
Quiescent Current = 5.0 nA/package typical @ 5 V
•
Low Logic Circuit Power Dissipation
•
High·Current Sourcing Outputs (Up to 25 mAl
•
Latch Storage of Code
•
Blanking Input
•
Lamp Test Provision
•
Readout Blanking on all Illegal Input Combinations
ORDERING INFORMATION
MC14XXXB
"ESYffIX
~
.
•
Lamp Intensity Modulation Capability
•
Time Share (Multiplexing) Facility
Denote5
L
C«amoc Package
P
PlastiC Package
A
Extended Operating
C
Temperature Range
limited Operating
Temperature Range
PIN ASSIGNMENT
•
Supply Voltage Range = 3.0 V to 18 V
B
•
Capable of Driving Two Low·power TTL Loads, One Low·power
Schottky TTL Load or Two HTL Loads Over the Rated
Temperature Range.
c
•
PLASTIC PACKAGE
CASE 648
VOo
IT
tl7)b
Bi
Chip Complexity: 216 FETs or 54 Equivalent Gates
LE
eC/c
b
d
0
MAXIMUM RATINGS
(Voltages referenced to Vss)
Rating
DC Supply Voltage
Input Voltage, All Inputs
DC Current Drain per Input Pin
Operating Temperature Range - AL Device
CLlCP Device
Storage Temperature Range
d
A
Symbol
Value
Voo
-0.5 to +18
V
Vin
-0.5 to Voo + 0.5
V
OISPLAY
I
10
mA
TA
-55 to +125
-40 to +85
°c
!L/! 1!2!3!'-/!slb 1718191
T stg
°c
Maximum Output Drive Current
(Source) per Output
'OHmax
-65 to +150
25
Maximum Continuous Output Power
(Sourcel per Output :j:
POHmax
50
Unit
VSS
3
2
1
5
4
6
TRUTH TABLE
mA
INPUTS
mW
strained to the range VSS .;; (Vin or V out ) .;; VoD.
Due to the sc~r.sj~g c3pab~!jty of thj~ circuit . damage can occur to the device if Vno is
applied, and the outputs are shorted to VSS and are at a logical 1 (See Maximum
Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
VSS or Voo)·
4-14
81
LT
D
C B A
X
X
0
X
X
X
X
1
1
1
1
1
1
1
8
X
0
1
X
X
X
X
0
0
0
0
0
0
0
Blank
0
0
1
1
1
,
0
1
1
1
1
0
1
0
0
1
0
1
1
1
0
0
0
0
0
1
1
1
1
1
,1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This device contains circuitry to protect the inputs against damage due to high static
lIoltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. A destructive high current mode may occur if Vin and V out are not con-
I
OUTPUTS
LE
1
b
c
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
I ~ I' I I~ ~
u
:
X
a
:
:
1
1
1
d
0
1
1
e
1
0
0
0
1
1
1
0
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
vl v v v v
~ a a 0 ?
f
DISPLAY
9
1
2
3
1
1
4
1
1
1
1
1
1
1
0
0
0
5
6
7
1
1
1
1
1
8
9
0
0
0
0
0
0
0
0
Blank
Blank
~ ~ ~
-81~nk
0
0
0
Blank
Blank
I
= Don't Care
'Depends upon the BCD code previously applied
when LE ~ 0
I
MC145118
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Tlow
voo
Characteristic
Symbol
Vdc
"0" Level
VOL
5.0
10
15
"1" Level
VOH
5.0
10
15
Input Voltage"
(VO ~ 3.80r 0.5 V)
(VO = 8.80r 1.0 V)
(VO = 13.80r 1.5 V)
"0" Level
VIL
(V 0 ~ 0.5 or 3.8 V)
(VO = 1.0 or8.8 V)
(VO = 1.5 or 13.8 V)
"1" Level
VIH
Output Drive Voltage (AL Device)
Source
(lOH ~ OmA)
(IOH = 5.0 rnA)
(IOH ~ 10 rnA)
(IOH ~ 15 rnA)
(IOH ~ 20 rnA)
(IOH ~ 25 rnA)
VOH
Output Voltage
Vin=VDDorO
Vin=OorVDD
5.0
10
15
(lOH =
(IOH =
(IOH =
(IOH=
(IOH =
(IOH ~
15
~
1.5
3.0
4.0
10
2.25
4.50
6.75
15
IOL
Output Drive Current (CLlCP Device)
Sink
(VOL =0.4 VI
(VOL =0.5 V)
(VOL=1.5V)
IOL
V
V
1.5
3.0
4.0
1.5
3.0
4.0
2.75
5.50
8.25
3.5
7.0
11.0
4.10
4.10
4.1
3.90
3.90
4.57
4.24
4.12
3.94
3.40
3.40
3.70
3.54
3.0
9.10
9.10
9.1
9.00
9.00
8.60
8.60
9.58
9.26
9.17
9.04
8.90
8.70
14.1
14.1
14.0
14.0
13.6
13.6
4.10
4.10
3.60
3.60
2.80
9.10
9.10
8.75
8.75
8.10
8.10
25 rnA)
Output Drive Current (AL Device)
(VOL .00.4 V)
Sink
(VOL=0.5V)
(VOL = 1.5 V)
Unit
4.1
9.1
14.1
3.5
7.0
11.0
3.5
7.0
11.0
2.80
(IOH ~ 0 rnA)
(IOH = 5.0 rnA)
(IOH ~ 10 rnA)
(IOH ~ 15 mAl
(IOH = 20 rnA)
(IOH = 25 rnA)
Max
0.05
0.05
0.05
V
14.59
14.27
14.18
14.07
13.95
13.70
11
3.5
V
8.6
8.2
14.1
V
13.6
13.2
V
5.0
(IOH~20mA)
(IOH
Min
0.05
0.05
0.05
4.57
9.58
14.59
VOH
OmA)
5.0 rnA)
10 rnA)
15mA)
Thigh'
Max
V
5.0
10
(IOH ~
(IOH ~
(IOH =
(IOH=
0
0
0
4.1
9.1
14.1
4.1
9.1
14.1
Typ
V
(IOH=OmA)
(IOH ~ 5.0 rnA)
(IOH = 10 rnA)
(IOH ~ 15 rnA)
(IOH ~ 20 rnA)
(IOH = 25mA)
Output Drive Voltage (CLlCP Device)
(IOH ~ 0 rnA)
Source
(IOH ~ 5.0 rnA)
(IOH = 10 rnA)
(IOH = 15 mA)
(IOH = 20 rnA)
(IOH = 25 mAl
25°C
Min
0.05
0.05
0.05
5.0
10
15
OmA)
5.0 rnA)
10 rnA)
15mA)
20 rnA)
25 rnA)
.
Max
Min
14.1
14.1
13.75
13.75
13.1
13.1
4.57
4.24
4.12
3.94
3.75
3.54
9.58
9.26
9.17
9.04
8.90
8.75
14.59
14.27
14.18
14.07
13.95
13.80
4.1
3.3
2.5
9.1
V
8.45
7.8
14.1
V
13.45
12.8
mA
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
5.0
10
15
0.52
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
rnA
1.3
3.6
(Continued)
4-15
MC145118
ELECTRICAL CHARACTERISTICS (Continued)
Thigh·
Voo
Vdc
Max
Unit
Input Current (AL Device)
'in
15
-
± 0.1
-
±000001
±0.1
-
± 1.0
I'A
Input Current ICLlCP Devicel
'in
15
-
±03
-
±0.00001
± 0.3
-
± 1.0
I'A
Input Capacitance
Cin
-
-
-
5.0
7.5
-
-
pF
QUiescent Current IAl Devicel
(Per Package) Vin=O or VDD.
100
5.0
10
20
-
0.005
0.010
0.Q15
5.0
10
20
-
150
300
600
I'A
150
300
600
!-lA
'out = 0 I'A
QUiescent Current ICLlCP Devlcel
(Per Package) Vin=O or VDD.
lout = I'A
100
Total Supply Current,,·t
(Dynamic plus Quiescent.
Per Package)
ICl 50 pF on all outputs, all
buffers switchingl
IT
a
I
25°C
T low •
Symbol
Characteristic
Min
5.0
10
15
-
5.0
10
15
-
-
Max
Min
-
-
5.0
10
Symbol
Output Rise Time
tTLH = (0.40 ns/pF) CL + 20 ns
tTLH = (0.25 ns/pF) CL + 17.5 ns
tTLH = (0.20 ns/pF) CL + 15 ns
-
!-lA
5.0
10
15
tpLH
tPHL = (1.3 ns/pF) CL + 655 ns
tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pFI CL + 182.5 ns
tpHL
Blank Propagation Delay Time
tPLH = (0.30 ns/pF) CL + 585 ns
tpLH =' (0.25 ns/pF) CL + 187.5 ns
tpLH = (0.15 ns/pF) CL + 142.5 ns
tPLH
tPHL = (0.85 ns/pF) CL + 442.5 ns
tPHL = (0.45 ns/pFI CL + 177.5 ns
tPHL = (0.35 ns/pFI CL + 142.5 ns
tpHL
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
tPLH
5.0
10
15
CL + 290.5 ns
CL + 112.5 ns
CL + 80 ns
tpHL = (1.3 ns/pF) CL + 248 ns
tPHL = (0.45 ns/pF) CL + 102.5 ns
tPH L = (0.35 ns/pFI CL + 72.5 ns
tpHL
Setup Time
tsu
Hold Time
th
Latch Enable Pulse Width
tWL
The formulas given are for the tYPical chdractertstlcs only
4-16
Min
Typ
Max
40
30
25
80
60
50
125
75
65
250
150
130
640
250
175
1280
500
350
720
290
200
1440
580
400
600
200
150
750
300
220
485
200
160
970
400
320
313
125
90
625
250
180
313
125
90
625
250
180
-
Unit
ns
tTHL
Lamp Test Propagation Delay Time
I
Voo
Vdc
5.0
10
15
Time
(1.5 ns/pF) CL + 50 ns
(0.75 ns/pF) CL + 37.5 ns
(0.55 ns/pF) CL + 37.5 ns
= (0.45 ns/pF)
= (0.25 ns/pFI
= (0.20 ns/pFI
-
C
tTLH
Time
CL + 620 ns
CL + 237.5 ns
CL + 165 ns
tPLH
tPLH
tPLH
20
40
80
= 25 0 C)
Characteristic
Data Propagation Delay
tPLH = (0.40 ns/pF)
tPLH = (0.25 ns/pF)
tPLH = (0.20 ns/pFI
-
tTo calculate total supply current at loads other than 50 pF
IT,Cl)
'T150 pF) + 3.5 x 10- 3 IC l -50) VDDf
where: 'T is in!-lA Iper packagel, CL in pF, VDD in Vdc,
and f in kHz is input frequency.
"The formulas given are for the typical
characterIStics only at 25°C.
1.0 Vdc min @ VDD 05.0 Vdc
2.0Vdcmin@VDO ·lOVdc
2.5 Vdc min @ VDO
15 Vdc
Output Fall
tTHL =
tTH L =
tTH L =
Min
(1.9 !-lA/kHz) f + 100
'T = (3.8 I'A/kHzl f + 'DD
'T = (5.7 !-lA/kHzl f + 'DD
IT
15
(CL = 50 pF. TA
Max
0.005
0.010
0.015
-
20
40
80
'T'aw= -55°C for AL Device, -40 o C for CLlCP Device.
Thigh = +125 0 C for AL Device, +85 0 C for CLlCP Device
*Naise Immunity specified for worst·case input combination
NOise Margin for both" 1" and "0" level =
SWITCHING CHARACTERISTICS*
Typ
-
-
-
-
-
-
-
-
ns
ns
ns
ns
5.0
10
15
-
5.0
10
15
100
40
30
-
-
5.0
10
15
60
-
-
30
-
5.0
10
15
520
220
130
260
110
65
-
-
ns
ns
-
~v
-
-
ns
MC14511B
FIGURE 1 - DYNAMIC POWER DISSIPATION
SIGNAL WAVEFORMS
Input L E low, and Inputs D,
BT and Lf high.
f in respect to a system clock.
All outputs connected to respective CL loads.
A, S, and C
50% Duty Cycle
~
Any Output
50%
VOH
.
--VOL
FIGURE 2 - DYNAMIC SIGNAL WAVE FORMS
(a) Inputs D and LE low, and Inputs A, B, 81 and L Thigh,
Input C
(b) Input D low, Inputs A, B, Bi and
IT high.
Ir-::~-------- V DD
LE
Input C
_ _ _ _ _...;:.;.;.x:I _ _ _ _ _ _ _ VSS
F
tsu
________,~----------VDD
50%
' - - - - - - - VSS
~---------------- Vo H
Output 9
\ ....___________________
_
vOL
(c) Data DCBA strobed into latches.
20 ns
20 ns
j,------ V D D
LE
-------VSS
4-17
II
MC14511B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT
Voo
Common
Anode LEO
Common
Cathode LED
"'=' 1.7 V
_ _ _ "'='1.7 V
I
Vss
FLUORESCENT READOUT
Voo
INCANDESCENT READOUT
Voo
Voo
Filament
Supply
-=
-= Vss
VSS
-=
VSS or appropriate
voltage below VSS'
(CAUTION: Maximum working voltage = 18.0 V)
LIQUID CRYSTAL (LCD) READOUT
GAS DISCHARGE READOUT
Excitation
Voo
Appropriate
Voltage
Voo
-=
"'''A filament pre·warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.
(Square Wave,
VSS to VOO)
VSS
Direct dc drive of LCO's not recommended for life of LCO readouts.
4-18
MC145118
LOGIC DIAGRAM
13 a
A 7
12 b
11 c
B 1
10 d
9e
15 f
C2
14 9
06
LE 5
VDD = Pin 16
VSS = Pin 8
4-19
II
®
MC145138
MOTOROLA
BCD·TO·SEVEN SEGMENT LATCH/DECODER/DRIVER
I
CMOS MSI
The MC14513B BCD-to-seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4-bit storage latch, an
8421 BCD-to-seven segment decoder, and has output drive capability.
Lamp test (LT), blanking (Bi), and latch enable (LE) inputs are used
to test the display, to turn-off or pulse modulate the brightness of the
display, and to store a BCD code, respectively. The Ripple Blanking
Input (RBI) and Ripple Blanking Output (RBO) can be used to
suppress either leading or trailing zeroes. It can be used with
seven-segment light emitting diodes (LED), incandescent, fluorescent,
gas discharge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.)
display driver, computer/calculator display driver, cockpit display
driver, and various clock, watch, and timer uses.
•
Quiescent Current = 5.0 nA/package typical @ 5 V
•
Low Logic Circuit Power Dissipation
•
High-current Sourcing Outputs (Up to 25 mAl
•
Latch Storage of Binary Input
•
Blanking Input
•
Lamp Test Provision
•
Readout Blanking on all Illegal Input Combinations
•
Lamp Intensity Modulation Capability
•
Time Share (Multiplexing) Capability
•
Adds Ripple Blanking In, Ripple Blanking Out to MC14511B
•
Supply Voltage Range = 3.0 V to 18 V
•
Capable of Driving Two Low-Power TTL Loads, One Low-power
Schottky TTL Load to Two HTL Loads Over the Rated
Temperature Range.
(LOW·POWER COMPLEMENTARY MOS)
BCD·TO·SEVEN SEGMENT
LATCH/DECODER/DRIVER
WITH RIPPLE BLANKING
PSUFFIX
PLASTIC PACKAGE
CASE 707
L SUFFIX
CERAMIC PACKAGE
CASE 726
1
ORDERING INFORMATION
MC,.Xxx.
tSUffiX
Denotes
L Ceramic Package
P Plastic Package
A Extended Operating
Temperature Range
C LImited Operating
Temperature Range
PIN ASSIGNMENT
MAXIMUM RATINGS (Voltages referenced to Vss)
Rating
Symbol
DC Supply Voltage
VDD
Input Voltage, All Inputs
DC Current Drain per I nput Pin
Vin
I
Operating Temperature Range - AL Device
CLlCP Device
Storage Temperature Range
TA
Maximum Continuous Output Drive Current
(Source) per Output
Maximum Continuous Output Power
(Source) per Output t
T stg
IOHmax
Value
-0.5 to +18
Unit
-0.5 to VDD + 0.5
10
-55 to +125
-40 to +85
-65 to +150
V
V
mA
°c
°c
25
mA
50
mW
INPUTS
RBI
POHmax
lE
X
X
X
I
0
0
0
0
0
0
0
0
X
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS
or VOOl.
IT
X
0
,,
,,
,,
,
,
,,,
,
,,
,
"
,
, ,
X
X
This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high imped·
ance circuit. A destructive high current mode may occur if Vin and V out is not constrained to the range VSS ~(Vin or Vout ) ~VDD'
Due to the sourcing capabijity of this Cifc;uit, daiTlaga can occur to the device if VDD is
applied, and the outputs are shorted to VSS and are at a logical 1 (see Maximum
Ratings).
BI
X
X
X
X
X
0
0
0
0
0
0
0
X
X
0
0
X
X
X
X
X
0
C
X
x
~
,
,,
,
,
,,
,
,
,,,
,
,
,,,
,
,
OUTPUTS
0 C
X X
x X
0 0
0 0
0 0
0 0
0 0
0
B A
x
x
X
X
0 0
0 0
0
0
,
,,
,
,
0 ,
,,
,
,
, ,
,, , ,
, ,,
,,
,, ,, ,, ,
0
0
,
0 0
0
0
0 0 0
0 0
0
0
0
0 0
0
0
RBO
,,,,,,,
b
9
, ,, ,,,
,,
, ,, , ,, , ,
, , , , ,,
, ,, ,,
, ,,,,,
,,, ,,, ,,, ,, , , ,
,,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0
0
0 0 0 0
0
0
0 0
0
0 0
0
0
0
0 0 0 0
0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
X X X X
Dan', Care
RBO ~ RBI ~5CBAL indicated bv other tOWS of table
Oepends upon the BCD code previously applied when LE
4-20
I
d
0
DISPLAY
B
Blank
Blank
,
0
2
3
4
5
6
7
B
9
Blank
Blank
Blank
Btank
Blank
Blank
MC14513B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vssl
Output Voltage - Segment Outputs
"a" Level
Yin ~ VDD or a
Symbol
Output Voltage - RBO Output
"0" Level
VOL
a or VDD
"1" Level
VOH
Input Voltage±;
"0" Level
(VO ~ 3.8 or 0.5 VI
(VO ~ 8.8 or 1.0 VI
(VO = 13.8 or 1.5 V)
VIL
(VO = 0.5 or 3.8 V) "1" Level
(VO = 1.0 or 8.8 V)
(Va = 1.5 or 13.8 V)
VIH
Vin~OorVDD
=
=
=
=
=
=
5.0
10
15
5.0
10
15
0.05
0.05
0.05
Max
Unit
a
4.1
9.1
14.1
0.05
0.05
0.05
V
4.1
9.1
14.1
5.0
10
15
0.05
0.05
0.05
4.95
9.95
14.95
0.05
0.05
0.05
4.95
9.95
14.95
5.0
10
15
0.05
0.05
0.05
V
4.95
9.95
14.95
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
5.0
4.10
4.10
4.1
3.90
3.90
3.40
3.40
4.57
4.24
4.12
3.94
3.75
3.54
9.10
9.10
V
V
10
5.0 mAl
10 mAl
15 mAl
20 mAl
25 mAl
15
9.00
9.00
8.60
8.60
14.1
14.1
14.0
14.0
13.6
13.6
4.10
4.10
3.60
3.60
2.80
2.80
9.10
9.10
3.5
3.0
9.58
9.26
9.17
9.04
8.90
8.75
9.1
14.59
14.27
14.18
14.07
13.95
13.80
14.1
V
8.6
8.2
V
13.6
13.2
V
VOH
5.0
= 0 mAl
= 5.0 mAl
= 10 mAl
= 15 mAl
15
20 mAl
25 mAl
a
Min
V
10
~
Max
V
(IOH = 0 mAl
(IOH = 5.0 mAl
(IOH = 10 mAl
(lOH c_ 15 mAl
(IOH = 20 mAl
(IOH = 25 mAl
=
Thigh *
TYiJ
VOH
(lOH = 0 mAl
(lOH = 5.0 mAl
(lOH c 10 mAl
liOH=15 mAl
(lOH ~ 20 mAl
(IOH ~ 25 mAl
(IOH
(IOH
(IOH
(IOH
(IOH
(IOH
4.1
9.1
14.1
5.0
10
15
a mAl
Output Drive Voltage - Segments
(CL/CP Device)
(lOH~OmA)
Source:
(lOH = 5.0 mAl
(IOH = 10 mAl
(lOH = 15 mAl
(lOH = 20 mAl
(IOH ~ 25 mAl
Min
0.05
0.05
0.05
5.0
10
15
Vin~VDDorO
(IOH
UOH
(lOH
(lOH
UOH
(IOH
Max
V
5.0
10
15
VOH
Output Drive Voltage - Segments
(AL Device)
Source:
(lOH = a mAl
(IOH = 5.0 mAl
UOH = 10 mAl
UOH = 15 mAl
(lOH = 20 mAl
(lOH = 25 mAl
Min
VOL
"1" Level
Vin ~
Vdc
25 0 C
Tlow*
voo
Characteristic
8.75
8.75
8.10
8.10
14.1
14.1
13.75
13.75
13.1
13.1
4-21
4.57
4.24
4.12
3.94
3.75
3.54
9.58
9.26
9.17
9.04
8.90
8.75
14.59
14.27
14.18
14.07
13.95
13.80
4.1
3.3
2.5
9.1
V
8.45
7.8
14.1
13.45
12.8
V
II
MC14513B
ELECTRICAL CHARACTERISTICS (Continued)
Symbol
Output Drive Current - ABO Output
(AL Device)
(VOH = 2.5 V)
Source
(VOH = 9.5 V)
(VOH = 13.5 V)
(VOL
(VOL
(VOL
= 0.4 V)
= 0.5 V)
= 1.5 V)
Sink
Output Drive Current - RBO Output
(CL/CP Device)
Source
(VOH = 2.5 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
II
(VOL
(VOL
(VOL
= 0.4 V)
= 0.5 V)
= 1.5 V)
Sink
25°C
Tlow*
Thigh*
VDD
Vdc
Min
Max
Min
Typ
Max
Min
Max
5.0
10
15
-0.40
-0.21
-0.81
-
-0.32
-0.17
-0.66
-0.64
-0.34
-1.3
-
-0.22
-0.12
-0.46
-
IOL
5.0
10
15
0.18
0.47
1.8
-
0.15
0.38
1.5
0.29
0.75
2.9
0.10
0.26
1.0
-
-
-
Output Drive Current - Segments
(AL Device)
Sink
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
IOL
Output Drive Current - Segments
(CL/CP Device)
Sink
(VOL = 0.4 VI
(VOL = 0.5 V)
(VOL = 1.5 V)
IOL
mA
mA
IOH
IOL
Unit
mA
IOH
5.0
10
15
-0.25
-0.13
-0.52
-
5.0
10
15
0.12
0.30
1.2
-
-
-
-
-0.21
-0.11
-0.44
-0.64
-0.34
-1.3
0.098
0.25
0.98
0.29
0.75
2.9
-
-
-
-0.17
-0.092
-0.36
O.DBO
0.21
0.80
-
-
mA
mA
-
5.0
10
15
0.64
1.6
4.2
-
0.51
1.3
3.4
0.88
2.25
8.8
5.0
10
15
0.52
1.3
3.6
-
-
0.44
1.1
3.0
0.88
2.25
8.8
-
0.36
0.9
2.4
-
0.36
0.9
2.4
-
mA
-
-
--
-
15
-
±0.1
-
±0.00001
±0.1
-
±1.0
/J.A
Input Current (CLlCP Device)
lin
15
-
±0.3
-
±0.00001
±0.3
-
±1.0
Input Capacitance
Cin
-
-
-
5.0
7.5
-
-
/J. A
pF
Quiescent Current (AL Device)
(Per Package) Vin = 0 or VDO,
100
5.0
10
15
-
5.0
10
20
-
0.005
0.010
0.015
5.0
10
20
-
150
300
600
/J. A
5.0
10
15
-
20
40
80
-
0.005
0.010
0.015
20
40
80
-
150
300
600
/J. A
Input Current (AL Device)
'out = 0 /J.A
Quiescent Current (CL/CP Device)
(Per Package) Vin = 0 or VOO,
lout = 0 /J.A
Total Supply Current"t
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
'Tlow
=
lin
100
IT
-
-
-
-
-
5.0
10
15
IT
IT
IT
-55 0 C for AL Device, -400 C for CLlCP Device.
= (1.9 /J.A/kHz)
= (3.8 /J.A/kHz)
= (5.7 /J.A/kHz)
-
f + 100
f + '00
f + 100
t To calculate total supply current at loads other than 50 pF:
'T(CL) = IT(50 pF} + 3.5 x 10-3 (CL - 50) VDOf
where: IT is in /J.A (per package), CL in pF, VDD in V,
and f in kHz is input frequency.
Thigh = +125 0 C for AL Device, +25 0 C for CLlCP Device.
# Noise immunity specified for worst-case input combination.
Noise Margin for both" 1" and "0" level =
1.0 V min @ VOD = 5.0 V
2.0 V min @VOD = 10 V
2.5Vmin@VDD=15V
•• The formu las given are for the typ ical characteristics
only at 25°C.
FIGURE 1 - DYNAMIC POWER OISSIPATION
SIGNAL WAVEFORMS
Input LE and RBI low, and Inputs D, §T and
IT
high.
f in respect to a system clock.
All outputs connected to respective C L loads.
~
50% Duty Cycle
Any Output
/J. A
VOH
50%
--VOL
4·22
MC14513B
SWITCHING CHARACTERISTICS* (CL
~ 50 pF TA ~ 25 0 CI
All Types
Characteristic
Output Rise Time - Segment Outputs
Symbol
VOO
Vdc
tTHL = (3.25 ns/pFI CL
tTHL = (1.35 ns/pF) CL
tTHL = (0.95 ns/pF) CL
Propagation Delay Time-RBI and BI Inputs'
tPHL
tPHL
Propagation Delay Time-L T Input"
tpLH ~ (0.45 ns/pF) CL + 290.5 ns
tpLH ~ (0.25 ns/pFI CL + 112.5 ns
tpLH ~ (0.20 ns/pF I CL + 80 ns
tpLH
tpHL
(1.3 ns/pFI CL + 248 ns
tpHL
(0.45 ns/pF) CL + 102.5 ns
tpHL ~ (0.35 ns/pFI CL + 72.5 ns
tPHL
0
Hold Time
Latch Enable Pu Ise Width
-
--
960
480
380
125
75
65
250
150
130
270
135
110
540
270
220
640
250
175
1280
500
350
720
290
200
1440
580
400
600
200
150
750
300
220
485
200
160
970
400
320
625
250
180
ns
5.0
10
15
--
5.0
10
15
-
.•
ns
-
ns
5.0
10
15
-
5.0
10
15
-
-
-
tsu
th
iwL(LE)
"The formulas given are for the typical characteristics only.
4-23
ns
ns
5.0
10
15
tpHL ~ (0.85 ns/pF) CL + 442.5 ns
tpHL ~ (0.45 ns/pF) CL + 177.5 ns
tPHL ~ (0.35 ns/pF) CL + 142.5 ns
Setup Time
480
240
190
Unit
ns
-
tPLH
tPLH = (1.05 ns/pFI CL + 547.5 ns
tpLH = (0.45 ns/pFI CL + 177.5 ns
tPLH = (0.30 ns/pF) CL + 135 ns
0
-
tPLH
0
tpHL ~ (13 ns/pF) CL + 655 ns
tpH L ~ (0.60 ns/pF) C L + 260 ns
tpHL ~ (0.35 ns/pF) CL + 182.5 ns
80
60
50
tTHL
+ 107.5 ns
+ 67.5 ns
+ 62.5 ns
Propagation Delay Time-A, B, C, D Inputs'
(0.40 ns/pFI CL + 620 ns
tPLH
tpLH
(0.25 ns/pFI CL + 237.5 ns
tpLH ~ (0.20 ns/pFI CL + 165 ns
40
30
25
tTHL
tTHL = (1.5 ns/pF) CL + 50 ns
tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
Output Fall Time - RBO Outputs
Max
tTLH
5.0
10
15
Output Fall Time-Segment Outputs"
Typ
ns
5.0
10
15
Output Rise Time - RBO Output
Min
tTLH
5.0
10
15
-
-
-
ns
ns
5.0
10
15
-
313
125
90
5.0
10
15
-
313
125
90
625
250
180
ns
-
-
-
ns
15
100
40
30
5.0
10
15
60
40
30
5.0
10
15
520
220
130
5.0
10
-
-
-
-
-
-
-
-
-
-
260
110
-
65
ns
ns
II
MC14513B
FIGURE 2 - DYNAMIC SIGNAL WAVEFORMS
BT
a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B,
20 ns
and [Thigh.
20 ns
9;1
VDD
50%1
l0o/~1
Input C
~------~~
VSS
tPLH~PHL
_ -VOH
Output g
I
VOL
tTLH
I
tTHL
BT and CT high.
b. Inputs A, 8, D and LE low, and Inputs RBI,
94
20 ns
20 ns
VDD
50%-
Input C
c. Setup and Hold Times: Input RBI and D low, Inputs A, B,
ns
2o
l§
BT
and
CT
high.
90%""0- - - - - - - - - V D D
LE
50%
__________1_0_%.JI . , - - - - - - - - V S S
Input C
j:=
tsu-==l
rth
50%
VDD
\ ' -_ _ _ _ __
-
VSS
~-------------------VOH
Output g
\
'-.--------------VOL
d. Pulse Width: Data DCBA strobed into latches.
I
I
--l
1--20 ns
r-- I I __- - - - V DD
90%~1
:
50% I
20 nS--i
LE
10%
tWL(LEI~
4-24
-----VSS
~
MC14513B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT
Voo
Common
Anode LED
Common
Cathode LED
"" 1.7 V
"" 1.7 V
II
FLUORESCENT READOUT
VDD
INCANDESCENT READOUT
VOO
Filament
Supply
-=
LIQUID CRYSTAL (LC) READOUT
GAS DISCHARGE READOUT
Voo
VSS or appropriate
voltage below VSS'
Excitation
(Square Wave,
VSS to VOO)
Appropriate
Voltage
1/4 Of MC14070B
.. -itA filament pre-warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.
Oirect de drive of LC's not recommended for life of LC readouts.
4-25
MC145138
LOGIC DIAGRAM
15 a
A7
14 b
13 c
B 1
II
12 d
11 e
17 f
C2
169
06
LE 5
TYPICAL APPLICATIONS FOR RIPPLE BLANKING
LEADING EDGE ZERO SUPPRESSION
Displays
I
MC14513B
Input
Code
o
0
0
(0)
0
MC14513B
o
0
0
(0)
0
MC14513B
o
0
I
I
I I
I I
I
1
(5)
MC14513B
o
0
(0)
4-26
0
0
MC14513B
o
0
0
(1)
1
I
I
MC14513B
o
0
1
(3)
MC14513B
TYPICAL APPLICATIONS FOR RIPPLE BLANK ING (Cont)
TRAILING EDGE ZERO SUPPRESSION
Displays
I
I
I
MC14513B
a
a
1
(5)
1
I
I
I
I I
MC14513B
a a a a
(0)
MC14513B
a a a
1
I
I
MC14513B
a a
(1)
(3)
4-27
1
MC14513B
a a a a
(0)
I
MC14513B
a a
0
(0)
a
Input Code
®
MC14543B
MOTOROLA
CMOS MS.
BCD·TO·SEVEN SEGMENT LATCH/DECODER/DRIVER
for LIQUID CRYSTALS
(lOW-POWER COMPLEMENTARY MOS)
BCD-TO·SEVEN SEGMENT
LATCH/DECODER/DRIVER
I
The MC 14543B BCO-to-seven segment latch/decoder/driver is
designed for use with liquid crystal readouts, and is constructed with
complementary MOS (CMOS) enhancement mode devices. The circuit provides the functions of a 4-bit storage latch and an 8421 BCOto-seven segment decoder and driver. The device has the capability
to invert the logic levels of the output combination. The phase (Ph),
blanking (BI), and latch disable (lO) inputs are used to reverse the
truth table phase, blank the display, and store a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is applied to
the Ph input of the circuit and the electrically common backplane
of the display. The outputs of the circuit are connected directly to
the segments of the LC readout. For other types of readouts, such
as light-emitting diode (LED), incandescent, gas discharge, and
fluorescent readouts, connection diagrams are given on this data
sheet.
Applications include instrument (e.g., counter, DVM etc.) display
driver, computer/calculator display driver, cockpit display driver,
and various clock, watch, and timer uses.
for
LlOUID CRYSTALS
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
PLASTIC PACKAGE
CASE 620
CASE 648
1
ORDERING INFORMATION
•
5.0 nA/package Typical
logic Circuit Quiescent Current
5V
Me,.x,,"
@
tSUfflX
L
P
A
• latch Storage of Code
• Blanking Input
• Readout Blanking on All Illegal Input Combinations
• Direct LED (Common Anode or Cathode) Driving Capability
• Supply Voltage Range = 3.0 V to 18 V
• Capable of Driving Two low-power TTL loads, One low-power
Schottky TTL Load or Two HTl Loads Over the Rated Temperature Range
• Pin-far-Pin Replacement for C04056A (with Pin 7 Tied to VSS).
C
TRUTH TABLE
INPUTS
LD
61
Ph·
• Chip Complexity: 207 FETs or 52 Equivalent Gates
MAXIMUM RATINGS (Voltages referenced to Vss)
OUTPUTS
D
C 6
Symbol
Value
VDD
-0.5 to +18
V
Input Voltage, All Inputs
Vin
-0.5 to VDD + 0.5
V
DC Input Current per Pin
lin
±10
mA
Operating Temperature Range - Al Device
Cl/CP Device
TA
-55 to +125
-40 to +85
°c
Storage Temperature Rance
T stg
-65 to +150
°c
DC Supply Voltage
Maximum Continuous Output Drive Current
(Source or Sink) per OulfJui
IOHmax
!OLfnax
10
mA
Maximum Continuous Output Power*
(Source or Sink) per Output
POHmax
POLmax
70
mW
d
X 0
0 1
1 0
0 1
0
0 0
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
1 0
0
1
1
1
1
1
0
1
0
0
1
1
1
1
0
0
1 0
1 0
Unit
A abc
x x
1
Rating
Denotes
Ceramic Package
PlastiC Package
Extended Operating
Temperature Range
Limited Operating
Temperature Range
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1 0
0
1
1
1
0 0
0 0
0 0
0 0
0 0
1
0
0
0
0
0
0
1
1
0
0
1
1
0
X
X
X
1
1
0
0
0
0
0
f
9
0
0
0
0
1
0
0
0
D;splay
1
1
1
1
1
1
1
1
1
0
1
1
1
1
e
1
0
0
0
0
0
0
0
0
0
0
0
0
Blank
0
0
0
0
0
Inverse of Output
Display
Combinations
as above
Above
x
= Don't care
t '" Above t;omOmations
..
=.
For liquid crystal readouts. apply a square wave to Ph
For common cathode LED readouts. select Ph = 0
For common anode LED readouts. select Ph
1
Depends upon the BCD code prev10usly applied when LO
:0
*POHmax
= IOH
(VOH - VDD) and POl max
= IOl
(VOL - VSS)
.... =
4·28
=
1
MC14543B
ELECTRICAL CHARACTERISTICS
Characteristic
Output Voltage
Vin
VDD or 0
Vin
o or
(Voltages Referenced to Vss)
Symbol
"0" Level
VOL
5.0
10
15
"1" Level
VOH
5.0
10
15
"0" Level
Vil
VDD
Input Voltage"
(Va 4.5 or 0.5 V)
(VO 9.00rl.0V)
(VO ~ 13.5 or 1.5 V)
Voo
Vdc
Tlow
.
Min
Max
0.05
0.05
0.05
4.95
9.95
14.95
4.95
9.95
14.95
Thigh'
Typ
Max
0
0
0
0.05
0.05
0.05
5.0
10
15
Min
Max
Unit
0.05
0.05
0.05
V
4.95
9.95
14.95
V
V
5.0
10
15
"1" Level
25°C
Min
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
VIH
(VO 00.5 or 4.5 V)
(VO c 1.00r9.0V)
V
5.0
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
5.0
5.0
10
10
15
5.0
10
10
15
-3.0
-0.64
-2.4
-0.51
-1.7
-0.36
-1.6
--4.2
0.64
1.6
-1.3
-3.4
0.51
1.3
4.2
3.4
-4.2
-0.88
-10.1
-2.25
-8.8
0.88
2.25
10.1
8.8
5.0
-2.5
-2.1
-1.7
5.0
10
10
15
-0.52
-0.44
-1.3
-3.6
-1.1
-3.0
--4.2
-0.88
-10.1
-2.25
-8.8
IOl
5.0
10
10
15
0.52
1.3
0.44
1.1
Input Current (Al Device)
lin
15
± 0.1
± 0.00001
± 0.1
± 1.0
Input Current (CLlCP Device)
lin
15
i
0.3
±0.00001
±03
± 1.0
5.0
7.5
0.005
0.010
0.015
5.0
10
20
150
300
600
}).A
20
40
150
300
600
}).A
(VO~1.50r13.5V)
Output Drive Current (Al Device)
(VOH = 2.5 VI
Source
(VOH = 4.6 V)
(VOH = 05 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
(VOL
(VOL
(VOL
(VOL
Sink
IOl
Output Drive Current (CLlCP Device)
Source
(VOH = 2.5 V)
IOH
(VOH
(VOH
(VOH
(VOH
= 0.4 V)
~ 0.5 V)
= 9.5 VI
= 1.5V)
= 4.6 VI
= 0.5 V)
= 9.5 V)
= 13.5 V)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 9.5 V)
(VOL=1.5VI
Sink
mA
IOH
0.36
0.9
mA
2.4
mA
3.6
3.0
I nput Capacitance
C ,n
OUlescent Current (AL DeVice)
(Per Package) Vin=O or VDD,
lout = O}).A
100
5.0
10
15
5.0
10
20
QUiescent Current (CLlCP DeVice)
(Per Package) Vin=O or VDD,
lout = O}).A
100
5.0
10
15
20
40
80
IT
5.0
10
Total Supply Current"'(
(Dynamic plus QUiescent.
Per Package)
(Cl =50 pF on all outputs, all
huffers sWitching)
-0.9
-2.4
-0.36
-0.9
-2.4
0.88
2.25
10.1
8.8
0.005
0.010
0.015
2.4
80
IT=(1.6 I-'A/kHz) f + 'DO
IT=(3.1 }).A/kHz) f + 'DO
IT=(4.7 }).A/kHz) f + 100
15
'Tlow ~550C for AL DeVice. -40°C for CLlCP Device.
Thigh - +125 0 C for AL Device. +85 0 C for CLlCP Device
..:...:Nolse immunity sp~cjfied for worst-case input combination
NOise Margin for both" 1" and "0" level - 1.0 V min @ VOO = 5.0 V
2.0 V min @ VDO = 10 V
2.5 V min @ VDD = 15 V
tTo ca)culate total supply current at loads other than 50 pF
3
3.5
x
10(CL
~50) VDOf
IT(50
pF)
+
IT(CL)
where IT is in}).A (per package), CL in pF, VDD in V, and f in kHz is input frequency.
,. The formulas given are for the typical characteristics only at 25°C.
4-29
mA
0.36
0.9
}).A
}).A
pF
I-'A
II
MC14543B
SWITCHING CHARACTERISTICS*
(CL
= 50 pF
TA
I
= 25°C)
Symbol
Characteristic
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
tTLH
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 12.5 ns
tTHL
Turn·Off Delay Time
tpLH = (1.7 ns/pF) CL + 520 ns
tPLH = (0.66 ns/pF) CL + 217 ns
tpLH = (0.5 ns/pF) CL + 160 ns
tpLH
Turn-On Delay Time
tPH L = (1.7 ns/pF) CL + 420 ns
tpHL = (0.66 ns/pF) CL + 172 ns
tpHL = (0.5 ns/pF) CL + 130 ns
tpHL
Setup Time
tsu
Hold Time
th
Latch Disable Pulse Width (Strobing Data)
*The formulas given are for the typical
characteristic~
tWH
,
Typ
Max
-
100
50
40
200
100
80
-
-
100
50
40
200
100
80
5.0
10
15
-
605
250
185
1210
500
370
5.0
10
15
-
505
205
155
1650
660
495
5.0
10
15
350
450
-
500
-
5.0
10
15
40
30
20
-
-
-
-
-
-
5.0
10
15
250
100
80
125
50
40
-
VDD
Min
5.0
10
15
5.0
10
15
Unit
ns
ns
ns
ns
-
-
-
ns
ns
ns
-
only.
LOGIC DIAGRAM
VDD = Pin 16
VSS = Pin 8
9 a
A 5
10 b
11 c
B 3
12 d
13 e
C 2
15 f
14 9
D 4
LD 1
4-30
MC145438
FIGURE 2 - TYPICAL OUTPUT SINK
FIGURE 1 - TYPICAL OUTPUT SOURCE
CHARACTE RISTICS
CHARACTERISTICS
24
1-
6.0 I---+---""'......,-+--+---+--+.",c-A-~
~
18
~
1---+--+--+--+---Ir:F--+-+-~
7 "'\ ,
t"-,
7V
Voo = 10 Vdc
12
V /V
G
LU
'-'
a:
'"0;;z
=>
o
~ -18 I---+--+.,.,..".'+--+---+--l----+-~
~ 6.0
o
-24 '-----'-_-'-_-'-_J..----'_-'-....L...J....---l
-16
-12
-8.0
-4.0
VOO = 15 Vdc
11<
r-
G -12
I.........
\/
.5
~
a:
\
o
~
o
~5.0IVdC
4.0
r-....
1'-- t-
~POLmax = 70 mWdc
I
I
VSS=OVdc
I
12
8.0
16
II
(VOL - VSS), SINK DEVICE VOLTAGE (Vdc)
(VOH -VOO),SOURCE DEVICE VOLTAGE (Vdc)
FIGURE 3 - DYNAMIC POWER DISIPATION
SIGNAL WAVEFORMS
FIGURE 4 - DYNAMIC SIGNAL WAVEFORMS
(a~
Inputs D, Ph, and BI low, and Inputs A, B, and LD high.
lr---------,.l=-4---- VDD
C
"------- VSS
Inputs BI and Ph low, and Inputs D and LD high.
f in respect to a system clock.
VOH
l'-----......:..:::.:::..;'f""-+--
All outputs connected to respective CL loads.
(b) Inputs D, Ph, and BI low, and Inputs
VOL
A and B high.
---......l.::-f-----------
VDD
LD
VSS
50% Duty Cycle
Any Output
th
~
VOH
C
~~----~~I:--~---------VDD
' - - - - - - - - - - - VSS
---VOL
~VOH
VOL
(c) Data DCBA strobed into latches
LD
4-31
_____tw~
5_0_%~-------:::
l-J'
MC14543B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
INCANDESCENT READOUT
Appropriate
Voltage
LIQUID CRYSTAL (LCI READOUT
Common
Backplane
Square Wave
(VSS to VOO)
II
GAS DISCHARGE READOUT
LIGHT EMITTING DIODE (LEDI READOUT
Common
Note:
Appropriate
Voltage
Common
Cathode LED
Anode LED
Bipolar transistors may be added for gain (for VOO ";;;10V or lout;:;;' 10 mAl.
CONNECTIONS TO SEGMENTS
PIN ASSIGNMENT
LD
VDD
C
B
D
Voo = Pin 16
VSS=Pin8
A
Ph
BI
DISPLAY
b
\Ll\/\213I'-/lslblllalgl
VSS
4
4-32
®
MC14544B
MOTOROLA
CMOS MS.
BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER
FOR LIQUID CRYSTALS
(LOW-POWER COMPLEMENTARY MaS)
The MC 14544B BCD-to-seven segment latch/decoder/driver is
designed for use with liquid crystal readouts, and is constructed with
complementary MOS (CMOS) enhancement mode devices. The circuit provides the functions of a 4-bit storage latch and an 8421 BCDto-seven segment decoder and driver. The device has the capability
to invert the logic levels of the output combination. The phase (Ph),
blanking (BI), and latch disable (LD) inputs are used to reverse the
truth table phase, blank the display, and store a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is applied to
the Ph input of the circuit and the electrically common backplane
of the display. The outputs of the circuit are connected directly to
the segments of the LC readout. The Ripple Blanking Input (RBI)
and the Ripple Blanking Output (RBO) can be used to suppress
either leading or trailing zeroes.
For other types of readouts, such as light-emitting diode (LED),
incandescent, gas discharge, and fluorescent readouts, connection
diagrams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display
driver, computer/calculator display driver, cockpit display driver,
and various clock, watch, and timer uses.
•
Logic Circuit Quiescent Current = 5.0 nA/package typical
5V
•
Latch Storage of Code
•
Blanking Input
BCD-TO-SEVEN SEGMENT
LATCH/DECODER/DRIVER
WITH RIPPLE BLANKING
II
P SUFFIX
PLASTIC PACKAGE
CASE 707
L SUFFIX
CERAMIC PACKAGE
CASE 726
OROERING INFORMATION
MWXXXO
1tSUffiX
Denotes
L
Ceramic Package
P
Plastic Package
A
Extended Operating
C
Temperature Range
Limited Operating
Temperature Range
@
PIN ASSIGNMENT
•
Readout Blanking on All Illegal Input Combinations
•
Direct LED (Common Anode or Cathode) Driving Capability
•
Supply Voltage Range
•
Capability for Suppression'of Non-significant zero
•
Capable of Driving Two Low-power TTL Loads, One Low-power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range
MAXIMUM RATINGS
= 3.0
V to 18 V
(Voltages referenced to Vss)
Rating
DC Supply Voltage
Symbol
Value
Unit
VDD
-0.5 to +18
Vdc
Input Voltage, All Inputs
Vin
-0.5 to VDO + 0.5
Vdc
DC Input Current per Pin
lin
±10
mAdc
Operating Temperature Range - AL Device
CL/CP Device
TA
-55 to +125
-40 to +85
°c
T stg
-65 to +150
°c
Maximum Continuous Output Drive Current
(Source or Sink) per Output
IOHmax
IOLmax
10
mAdc
Maximum Continuous Output Power*
(Source or Sink) per Output
POHmax
POLmax
70
mW
Storage Temperature Range
*POHmax
= IOH
(VOH - VOO) and POLmax
= IOL (VOL - VSS)
4-33
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit. For proper
operation it is recommended that Vin and
V out be constrained to the range VSS .;;
(V in or V out ) .;; VDO,
Unused inputs must always be tied to an
appropriate logic voltage level (e.g" either
VSS or Vool.
MC145448
ELECTRICAL CHARACTERISTICS
Characteristic
Output Voltage
Vin = VOO or 0
(Voltages Referenced to Vss)
Symbol
"0" Level
"1" Level
VOL
VOH
Vin = 0 or VOO
Input Voltage#
(VO = 4.5 or 0.5 V)
(Va = 9.0 or 1.0 V)
(Va = 13.5 or 1.5 V)
II
"0" Level
vDD
Vdc
Min
Tlow *
Max
5.0
10
15
5.0
10
15
2SoC
Min
0.05
0.05
0.05
4.95
9.95
14.95
Typ
Max
0
0.05
0.05
0.05
a
0
4.95
9.95
14.95
5.0
10
15
Min
Thigh *
Max
0.05
0.05
0.05
4.95
9.95
14.95
V
5.0
10
15
VIH
Output Drive Current (CL/CP Devicel
Source
(VOH = 2.5 V)
(VOH =4.6 V)
(YaH = 0.5 V)
(VOH =9.5 V)
(VOH = 13.5 V)
Sink
(VOL = 0.4 VI
(VOL = 0.5 VI
(VOL = 9.5 VI
(Val = 1.5 VI
IOH
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
5.0
5.0
10
10
15
5.0
10
10
15
-3.0
-0.64
-2.4
-0.51
-1.7
-0.36
-1.6
-4.2
0.64
1.6
-1.3
-3.4
0.51
1.3
4.2
3.4
-4.2
-0.88
-10.1
-2.25
-8.8
0.88
2.25
10.1
8.8
5.0
-2.5
5.0
10
10
15
-0.52
-2.1
-0.44
-4.2
-0.88
-10.1
-2.25
-8.8
0.88
2.25
10.1
8.8
-1.7
-0.36
V
mA
IOH
IOL
IOl
V
V
Vil
"1" Level
(VO = 0.5 or 4.5 V)
(VO = 1.0 or 9.0 V)
(VO = 1.5 or 13.5 V)
Output Drive Current (AL Device)
(VOH = 2.5 V)
Source
(YaH = 4.6 V)
(VOH = 0.5 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
Sink
(VOL = 0.4 V)
(Val = 0.5 V)
(VOL = 9.5 V)
(VOL = 1.5 V)
Unit
-0.9
-2.4
0.36
0.9
mA
2.4
mA
5.0
10
10
15
-1.1
-3.0
0.44
-1.3
-3.6
0.52
1.3
1.1
3.0
3.6
-0.9
-2.4
0.36
0.9
mA
2.4
Input Current (AL Device)
lin
15
±0.1
±0.00001
±0.1
± 1.0
/lA
Input Current (CLlCP Device)
lin
15
± 0.3
±0.00001
± 0.3
± 1.0
IJA
Input Capacitance
Cin
5.0
7.5
Quiescent Current (AL Device)
(Per Package) Vin=O or VOO,
100
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
IJA
Quiescent Current (CLlCP DeVIce)
(Per Package) Vin=O or VOO,
lout = OJ.LA
100
5.0
10
15
20
40
80
2.0
40
80
150
300
600
IJA
Total Supply Current' • 't
(Dynamic plus Quiescent.
Per Package)
(Cl = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
lout = O/lA
0.005
0.010
0.015
IT
IT
IT
=
=
=
(1.6 /lA/kHz) f + 100
(3.1 /lA/kHz) f + 100
(4.7 IJA/kHz) f + 100
'Tlow = -55°C for AL Device. -40 0 C for CLlCP Device.
Thigh = +125 0 C for AL Device. +85 0 C for CLlCP Device.
,.Noise immunity specified for worst'case input combination.
Noise Margin for both "1" and "O"level = 1.0 V min @ VOO = 5.0 V
2.0 V min @ VOO = 10 V
2.5 V min @ VOO = 15 V
tTo calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10-3 (CL -50) VOOf
where: IT is in /lA (per package). CL in pF. VOO in Vdc, and f in kHz is input frequency .
• 'The formulas given are for the typical characteristics only at 25°C.
4·34
pF
IJA
MC14544B
SWITCHING CHARACTERISTICS*
(CL; 50 pF TA; 25°C)
Characteristic
VDD
Min
Typ
Max
5.0
10
15
-
100
50
40
200
100
80
5.0
10
15
-
100
50
40
200
100
80
5.0
10
15
-
-
605
250
185
1210
500
370
5.0
10
15
-
505
205
155
1650
660
495
5.0
10
15
0
0
0
-40
-15
-10
-
th
5.0
10
15
80
30
20
40
15
10
-
ns
tWH
5.0
10
15
250
100
80
125
50
40
-
ns
-
Symbol
Output Rise Time
tTLH; (3.0 ns/pF) CL + 30 ns
tTLH; (1.5 ns/pF) CL + 15 ns
tTLH; (1.1 ns/pF) CL + 10 ns
tTLH
Output Fall Time
tTHL; (1.5 ns/pF) CL + 25 ns
tTHL; (0.75 ns/pF) CL + 12.5 ns
tTHL; (0.55 ns/pF) CL + 12.5 ns
tTHL
Turn-Off Delay Time
tpLH ; (1.7 ns/pF) CL + 520 ns
tpLH ; (0.66 ns/pF) CL + 217 ns
tpLH; (0.5 ns/pF) CL + 160 ns
tPLH
Turn-On Delay Time
tPHL; (1.7 ns/pF) CL +420 ns
tPHL; (0.66 ns/pF) CL + 172 ns
tPHL; (0.5 ns/pF) CL + 130 ns
tpHL
Setup Time
tsu
Hold Time
Latch Disable Pulse Width (Strobing Data)
ns
ns
ns
ns
'The formulas given are for the tYPical characterIStics only.
LOGIC DIAGRAM
Voo
= Pin 18
VSS = Pin 9
A 5
B 3
C 2
04
LD 1
4-35
Unit
-
ns
-
II
MC14544B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
INCANDESCENT READOUT
LlOUID CRYSTAL (LC) READOUT
Appropriate
Voltage
MC14544B
Output
Common
Backplane
Ph
Square Wave
(VSS to VO O )
II
GAS DISCHARGE READOUT
LIGHT EMITTING DIODE (LED) READOUT
Common
-=Note:
VSS
Bipolar transistors may be added for gain (for VOO ';;;;10V or lout;:;' 10 mAl.
TRUTH TABLE
R81
LD
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
,,
,
,,,
,
,,
,,
,
,,
,
X
,,
X
0
t
t
X
Appropriate
Voltage
Anode LEO
x
IN~UTS
1
Voo
Common
Cathode LEO
--'---
,
OUTPUTS
81
Ph'
0
C 8 A
0
0
0
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,
,
,
,,
0
0
0
X
0
t
L~
1
•.
,, ,
1
0
,
,
,
,,
,
,
0
0
0
0
0
0
0
0
,, , , ,
,, ,
,,
,, , , ,
0
0
0
0
0
0
0
X
X
t
X
R80
a
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
"
t
b
0
0
d
e
f
9
DISPLAY
0
0
0
0
Blank
, , ,
,,
, ,, , , ,,
,,,
,,
, ,, ,,
,, , ,, , , , ,
, , ,, , , , ,
,, , ,,
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0 0
0 0
0 0
0 0
0 0
0
0
0
0
0
0
,.
0
0
0
0
0
0
0
0
For liquid crystal readouts, apply a square wave to Ph. For
common cathode LED readouts, select Ph = O. For common
anode LED readouts, select Ph = 1.
Depends upon the BCD Code previously applied when LD = 1.
Blank
,
0
2
3
#
4
5
6
7
8
9
0
0
0
0
Blank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
Blank
"
Inverse 01 OutpuT
Display
Comblnarlons Abovl:'
asabOllt!
Don't Care
Above Combinations
4-36
RBO=RBI •
(ABeD)
MC14544B
FIGURE 2 - TYPICAL OUTPUT SINK
FIGURE 1 - TYPICAL OUTPUT SOURCE
CHARACTERISTICS
CHARACTERISTICS
24
1
-6.0 1----4---"Io-,..-4--+----4.--+ofL-A-----l
~
~
~
-12 1----4--+--+--+----tr:F--+-_+_--1
a::
I
12
II
c.>
c.>
a::
7V
'"
Z
:::>
i
18
:::>
UJ
u;
o
..j
-18
9
-24 L---L_--'-_..I....._VS_SJ...=_O_V..Ld_C_J......JI...-I_...J
-16
-12
-8.0
-4.0
0
6.0
~
o0
(VOH -VOO),SOURCE OEVICE VOLTAGE (Vdc)
FIGURE 3 - DYNAMIC POWER DISIPATION
SIGNAL WAVEFORMS
1/
VOO = 15 Vdc
\1/
.5
~
a::
\
/1>,
\
/V
,
VOO
I
=
10 Vdc
1',
t-.....
rf5.01VdC
I-- Po Lmax
I
-I= 70 mWdc
I
VSS = 0 Vdc
I
12
16
4.0
8.0
(VO L - VSS), SINK OEVICE VO LTAG E (Vdc)
II
FIGURE 4 - DYNAMIC SIGNAL WAVEFORMS
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.
lr---,..----......,,[~l------ VDD
C
Inputs BI and Ph low, and Inputs D and LD high.
f in respect to a system clock.
All outputs connected to respective CL loads.
(b) Inputs D, Ph, and BI low, and Inputs
20 ns
A and B high.
VDD
A, B, and C
---~:-+----------- VDD
LD
50% Duty Cycle
Any Output
~
VOH
C
- , . ; . . - - - - - - - - - - VSS
th
,-~---~I------------ VOO
' - - - - - - - VSS
---VOL
' - - VOH
VOL
(c) Data DCBA strobed into latches
LD
4-37
-----VDD
50%
- - - - - - - - - - . " -.- - - - - - - - VSS
tWH
O
MC14544B
TYPICAL APPLICATIONS FOR RIPPLE BLANKING
LEADING EDGE ZERO SUPPRESSION
Displays
I
I I
I
II
MC14544B
MC14544B
Input
a a a a
a a a a
Code
(0)
(0)
MC14544B
MC14544B
a
I
I
I
I
a a a a
1
MC14544B
MC14544B
a a a
a a
1
(1)
(0)
(5)
I
I
1
(3)
TRAILING EDGE ZERO SUPPRESSION
Displays
I
I
I
I
I I
I I
MC14544B
MC14544B
MC14544B
a
a a a a
a a a
a
1
(5)
1
(0)
1
I
I
---
MC14544B
a a
(1)
(3)
4-38
1
MC14544B
MC14544B
a a a a
a a a a
(0)
(0)
Input Code
®
MC14547B
MOTOROLA
CMOS MS.
HIGH CURRENT
BCD-TO-SEVEN SEGMENT DECODER/DRIVER
(LOW-POWER COMPLEMENTARY MOS)
HIGH CURRENT
The MC14547 BCD-to-seven segment decoder/driver is constructed
with complementary MOS (CMOS) enhancement mode devices and
NPN bipolar output drivers in a single monolithic structure. The circuit
provides the functions of an 8421 BCD-to-seven segment decoder with
high output drive capability. Blanking (81), can be used to turn off or
pulse modulate the brightness of the display. The MC14547 can drive
seven-segment light-emitting diodes (LED), incandescent. fluorescent
or gas discharge readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
BCD-TO-SEVEN SEGMENT
DECODER/DRIVER
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
CASE 620
PLASTIC PACKAGE
CASE 648
• High Current Sourcing Outputs (Up to 65 mAl
ORDERING INFORMATION
• Low Logic Circuit Power Dissipation
• Supply Voltage Range = + 3.0 V to + 18 V
MC14XXXB ~SUffIX
• Blanking Input
• Readout Blanking on All Illegal Combinations
• Lamp Intensity Modulation Capability
Denote.
L
Ceramic Package
P
Plastic Package
A
Extended Operating
C
Temperature Range
Limited Operating
Temperature Range
• Multiplexing Capability
• Capable of Driving Two Low-Power TTL Loads,
One Low-Power Schottky TTL Load or
Two HTL Loads over the Rated Temperature Range
16
• Use MC14511 B for Applications Requiring Data Latches
15
14
4
17'/b
eC/c
f
13
12
d
11
10
MAXIMUM RATINGS
* (Voltage referenced to VSS, Pin 8)
Rating
DC Supply Voltage
Input Voltage, All Inputs
Operating Temperature Range
MC14547BAL
MC14547BCL!CP
Symbol
Value
Unit
DISPLAY
VDD
-0.5to+18
V
Vin
- 0.5 to VOD + 0.5
V
-55 to +125
-40 to +85
°c
IL71 112131'-/lslb 1711:/\ 91
TA
Tstg
-65 to +150
°c
Maximum Continuous Output Drive Current
(Source) per Output
IOHmax
65
mA
Maximum Continuous Power Dissipation
POHmax
1200'
mW
Storage Temperature Range
TRUTH TABLE
OUTPUTS
INPUTS
* Maximum Ratings are those values beyond which damage to the device may occur.
'See power derating curve (Figure 1l.
This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. A destructive high current mode may occur if Vin and V out is not
constrained to the range VSS .;;;; (Vin or V out ) .;;;; VDD·
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is
applied, and the outputs are shorted to VSS and are at a logical 1 (See Maximum
Ratings).
Unused inputs must always be tied to an appropriate logic voltage level
VSS or VDD)'
4-39
(e.g., either
61
D C
6
A
a b
c
d
e
f
g
DISPLAY
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
0
0
0
1
0
0
0
1
1
0
1
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
0
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Blank
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
x=
0
0
0
0
1
1
1
1
1
1
1
1
Don't care
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
2
3
4
5
6
7
8
0
1
1
0
0
Blank
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
9
Blank
II
MC14547B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vss)
Characteristic
Output Voltage
Vin = VDD or 0
"0" Level
II
VOO
VOL
Vdc
5.0
10
15
"1" Level
Vin
Symbol
VOH
= 0 or VDD
Input Voltage #
(Va = 3.8 or 0.5 V)
(VO = 8.8 or 1.0 V)
(Va = 13.8 or 1.5 V)
"0" Level
(Va = 0.5 or 3.8 V)
(Va = 1.0 or 8.8 V)
(Va = 1.5 or 13.8 V)
Output Drive Voltage (AL Device)
(lOH = 5.0 rnA)
(lOH = 10 rnA)
(lOH = 20 mAl
(lOH = 40 mAl
(lOH = 65 mAl
"1" Level
= 5.0 mAl
= 10 mAl
= 20 mAl
= 40 mAl
= 65 mAl
Drive Voltage (CL/CP Device)
= 5.0 mAl
= 10 mAl
= 20 mAl
= 40 mAl
= 65 mAl
(lOH = 5.0 mAl
(lOH = 10 mAl
(lOH = 20 mAl
IIOH = 40 mAl
(lOH = 65 mAl
(lOH = 5.0 mAl
(lOH = 10 mAl
IIOH = 20 mAl
(/OH = 40 mAl
IIOH == 65 mAl
Output Drive Current (AL Device)
(VOL = 0.4 V)
1VOL = 0.5 V)
(VOL = 1.5 V)
Output Drive Current (CL/CP Device)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
25°C
Thigh*
Min Max
0.05
0.05
0.05
4.3
9.3
14.4
Typ
0
0
0
4.6
9.6
14.6
Max
0.05
0.05
0.05
2.25
4.50
6.75
1.5
3.0
4.0
-
3.5
7.0
11.0
2.75
550
8.25
-
3.5
7.0
11.0
-
4.2
4.1
3.9
3.7
3.2
4.3
4.3
4.2
4.0
3.7
-
4.3
4.0
9.2
9.1
9.0
8.9
8.5
93
9.3
9.2
90
8.8
14.2
14.1
14.0
13.8
13.5
14.3
14.3
14.2
14.0
13.7
4.1
4.0
3.8
3.5
3.0
9.1
9.0
8.8
8.5
8.1
14.1
14.0
13.8
13.5
13.0
4.3
4.3
4.2
4.0
3.7
9.3
9.3
9.2
9.0
8.8
14.3
14.3
14.2
14.0
13.7
0.26
0.65
1.7
0.22
0.55
1.5
Min
-
-
4.4
9.4
14.4
-
-
5.0
10
15
VIH
VOH
5.0
10
15
5.0
Source
10
3.5
7.0
11.0
15
1.5
3.0
4.0
-
-
-
3.8
-
-
-
3.1
-
9.1
8.8
-
-
-
8.4
-
14.0
-
-
13.8
13.5
-
-
-
Source
-
10
15
V
-
-
-
-
-
-
3.0
-
9.3
-
-
-
-
9.2
-
-
-
-
-
8.1
-
14.4
-
-
-
-
-
14.2
-
13.3
-
4.2
-
-
-
-
V
-
-
3.6
-
-
-
3.0
8.9
-
-
-
8.6
-
-
-
8.0
-
13.9
-
-
-
13.6
-
-
-
13.0
-
5.0
10
15
0.32
0.80
2.10
-
5.0
10
15
0.26
0.65
1.8
-
3.9
-
-
-
2.9
-
9.2
-
-
-
-
9.0
-
-
-
-
8.0
14.2
-
-
-
14.0
-
-
-
13.0
-
0.44
1.13
4.4
-
0.18
0.45
1.2
-
0.44
1.13
4.4
-
0.18
0.45
1.2
-
-
-
mA
IOL
-
-
-
-
mA
IOL
Sink
V
1.5
3.0
4.0
5.0
3.9
Sink
V
V
4.0
-
VOH
Unit
V
VIL
(lOH = 5.0 mAl
(lOH = 10 mAl
(lOH = 20 mAl
(lOH = 40 mAl
(lOH = 65 mAl
UOH
(IOH
(lOH
(lOH
IIOH
Output
(lOH
(lOH
IIOH
(lOH
(lOH
5.0
10
15
Tlow*
Min Max
0.05
0.05
0.05
4.1
9.1
14.1
-
*Tlow = -55°C for AL Device, -40°C for CL/CP Device
Thigh = + 125°C for AL Device, +85°C for CL/CP Device
#Noise immunity specified for worst-case input combination.
Noise Margin for both "1" and "0" level =
1.0 V min @ VDD = 5.0 V
2.0 V min @ VDD = 10 V
2.5 V min @ VDD= 15 V
4-40
-
-
-
-
-
MC14547B
ELECTRICAL CHARACTERISTICS (Continued)
Tlow "
Min Max
25°C
Typ
Thigh"
Min Max
Symbol
VDD
Vdc
Input Current (AL Device)
lin
15
-
±01
-
±O.OOOOl ±01
-
± 10
/LA
Input Current (CLlCP Device)
lin
15
-
±03
-
±O.OOOOl ±0.3
-
± 10
Cin
-
-
-
-
5.0
7.5
-
-
/LA
pF
IDD
5.0
10
15
-
5.0
10
20
-
0.005
0.010
0.015
5.0
10
20
-
150
300
600
/LA
20
40
SO
-
0.005
0.010
0.015
20
40
SO
150
300
600
/LA
Characteristic
Input Capacitance
Quiescent Current (AL Device) (Per Package)
Vin = 0 or VDD, lout= 0 /LA
Quiescent Current (CLlCP Device) (Per Package)
Vin=O or VDD, 10ut=0 p.A
IDD
Total Supply Current"" t
(Dynamic plus Quiescent,
Per Package)
(Cl = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
5.0
10
15
-
-
Min
-
-
Max
-
-
IT = (1.9p.A/kHz) f + IDD
IT = (3.S p.A/kHz) f + IDD
IT = (5.7 p.A/kHz) f + IDD
Unit
p.A
II
• Tlow = -55°C for AL Device, -40°C for CLlCP Device
Thigh = + 125°C for AL Device, +S5°C for CLlCP Device
t To ca)culate total supply current at loads other than 50 pF:
IT (Cl) = IT (50 pF) + 3.5 x 10- 3 (CL - 50) VDDf
where: IT is in p.A (per package), CL in pF, VDD in V,
and f in kHz is input frequency .
•• The formulas given are for the typical
characteristics only at 25°C.
SWITCHING CHARACTERISTICS (CL
=
50 pF T A
= 25°C)
Characteristic
Output Rise Time
Output Fall Time
Symbol
VDD
Vdc
Min
Typ
Max
Unit
tTlH
5.0
10
15
-
40
40
40
80
80
80
ns
5.0
10
15
-
125
75
70
250
150
140
ns
5.0
10
15
-
1500
ns
5.0
10
15
-
750
300
200
750
300
200
750
300
200
tTHl
Data Propagation Delay Time
tplH
tpHl
Blank Propagation Delay Time
tpLH
tpHL
4-41
-
-
-
-
5.0
10
15
-
5.0
10
15
-
-
-
500
250
170
600
400
1500
600
400
1500
600
400
1000
500
340
ns
MC14547B
LOGIC DIAGRAM
8T4
A 7 -
---++-+-.......- - - - - - - - - - - ,
.......
13 a
12 b
B 1 -
.......----I..-HH-.
11 c
10 d
I
C 2 -.......---++..
9 e
15 f
06--------1
14 g
FIGURE 1 - AMBIENT TEMPERATURE POWER DERATING
1200
" "'"
~
..........
"'"
.~
....... r--..,
........
/CL DEVICE
i>.. ~
""- '<..
CP DEVICE
o
25
50
75
85
100
/' AL DEVICE
125
TA. AMBIENT TEMPERATURE lOCI
4-42
150
175
MC14547B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT
Common
Anode LED
Common
Cathode LE D
"" 1.7 V
_ _ _ "" 1.7 V
-=
Vss
INCANDESCENT READOUT
VDD
vss
LIGHT-EMITTING DIODE (LED) READOUT
USING A ZENER DIODE TO REPLACE DROPPING RESISTORS
VDD
Common
Cathode LED
GAS DISCHARGE READOUT
VOD
Appropriate
Voltage
Vss
FLUORESCENT READOUT
VOO
-=
VSS
• VZD should be set at VDD - 1.3 V - VLED· Wattage of zener
diode must be calculated for number of segments and worst-case
conditions .
Filament
Supply
•• A filament pre-warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.
Vss or appropriate
voltage below VSS.
4-43
(Caution: Absolute maximum
working voltage = 18.0 V)
II
®
MC14558B
MOTOROL.A
CMOS MS.
BCD-TO-SEVEN SEGMENT DECODER
(LOW-POWER COMPLEMENTARY MOS)
I
The MC14558B decodes 4-bit binary coded decimal data dependent on the state of auxiliary inputs, Enable and RB I, and provides an
active-high seven-segment output for a display driver.
An auxiliary input truth table is shown, in addition to the BCD
to seven-segment truth table, to indicate the functions available with
the two auxil iary inputs.
Leading Zero blanking is easily obtained with an external flip-flop
in time division multiplexed systems displaying most significant
decade first.
BCD-TO-SEVEN
SEGMENT DECODER
~r1111118
16~~~1 ~ ij ti 16~l~ ~ ~
•
•
•
•
•
•
•
Quiescent Current = 5.0 nA/package typical @ 5 Vdc
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Segment Blanking for All Illegal Input Combinations
Lamp Test Function
Capability for Suppression of Non-Significant Zeros
Lamp Intensity Function
Capable of Driving Two Low-power TTL Loads, One Low-power
Schottky TTL load or Two HTl Loads Over the Rated Temperature Range
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
PLASTIC PACKAGE
CASE 620
CASE 648
ORDERING INFORMATION
MC14XXXB ~SUffIX
T-
t:
Denotes
L CeramIc Package
P PlastIC Package
A
Extended Operating
Temperature Range
C LImIted OperatIng
Temperature Range
MAXIMUM RATINGS
(Voltages referenced to Vss)
Rating
PIN ASSIGNMENT
Symbol
Value
Unit
Vdc
VDD
-0.5 to +18
Input Voltage. All Inputs
Vin
-0.5 to VOD + 0.5
Vdc
DC Input Current, per Pin
'in
±10
mAde
Operating Temperature Range .- AL Device
CLlCP Device
TA
-55 to +125
-40 to +85
°c
Storage Temperature Range
TUg
-65 to +150
°c
OC Supply Voltage
B
15
3
Enable
14
4
RBO
13
5
RBI
6
0
A
8
RBI
Pin 5
BCD
Input
Code
RBO
Pin 4
0
0
X
0
Lamp Test
b
1
X
1
Blank Segments
1
1
0
1
Display Zero
1
0
0
0
Blank Segments
1
X
1·9
1
1-9 Displayed
d
4-44
10
9
VSS
DISPLAY
X = Don't Care
RBI = Ripple Blankinllinput
RBO = Ripple BI.,kinll Output
12
11
Function Performed
0
16
C
AUXILIARY INPUT TRUTH TABLE
Enable
Pin 3
VDO
2
l-:-/b
eOc
!
d
MC14558B
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V SS)
voo
Charac:teristic:
Output Voltage
Von = VDD or
Symbol
Vdc:
"0" Level
VOL
5.0
10
15
"I" Level
VOH
5.0
10
15
a
Vin=OorVDD
Input Voltage U
(VO = 4.5 or 0.5 Vdd
(VO = 9.0 or '.0 Vdd
(VO = 13.5 or 1.5 Vdc)
"0" Level
4.95
9.95
14.95
4.95
9.95
14.95
Sink
Output Drive Current (CL/CP Device)
Source
(VOH = 2.5 Vdd
(VOH = ,4.6 Vdcl
(VOH = 9,5 Vdd
(VOH = 13.5 Vdd
Sink
Thigh·
Typ
M. .
a
a
a
0.05
0.05
0.05
5.0
10
15
Min
Max
Unit
0.05
0.05
0.05
Vdc
4.95
9.95
14.95
Vdc
Vdc
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V,H
(VO = 1.5 or 13.5 Vdd
Output Drive Current (AL DeVIce)
Source
(VOH = 2.5 Vdd
(VOH = 4.6 Vdcl
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdcl
Min
0.05
0.05
0.05
5.0
10
15
"I" Level
(VOL = 0.4 Vdd
(VOL = 0.5 Vdd
(VOL = 1.5 Vdd
M ..
VIL
(VO = 0.5 or 4.5 Velc)
(VO = 1.0 or 9.0 Vdc)
(VOL = 0.4 Vdd
(VOL = 0.5 Vdd
(VOL= 1.5Vdcl
25°C
Tlow·
Min
5.0
10
15
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
5.0
5.0
10
15
-3.0
-0.64
-1.6
-4.2
-2.4
-0.51
-1.3
-3.4
-4.2
-0.88
-2.25
-8.8
-1.7
-0.36
-0.9
-2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
5.0
5.0
10
15
-2.5
-0.52
-1.3
-3.6
-2.1
-0.44
-4.2
-0.88
-2.25
-8.8
-1.7
-0.36
-0.9
-2.4
5.0
10
15
0.52
1.3
3.6
0.44
0.88
2.25
8.8
0,36
0.9
2.4
3.5
7.0
Vdc
mAdc
10H
IOL
mAdc
mAdc
IOH
10L
-1.1
-3.0
1.1
3.0
mAde
Input Current (AL DeVIce)
lin
15
tOl
fOOOOOl
:to.l
il.0
!JAdc
Input Current (CL/CP Device)
lin
15'
±0.3
iO.OOOOl
:t03
il.0
!JAde
Input Capacitance
QUIescent Current IAL Delilce)
V in ='0 or VOO
(Per Package)
10ut=O /LA
QUIescent Current (CLiCP DeVIce)
Vin=O or VOO
(per Packaqe)
10ut=0 /LA
Total Supply Current ° ° t
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers sWItching)
5.0
Cin
pF
7.5
5.0
10
15
5.0
10
20
0.005
0.010
0.Q15
5.0
10
20
150
300
600
IDD
5.0
10
15
20
40
80
0.005
0.010
0.015
20
40
80
150
300
IT
50
10
15
IDD
600
IT = (1.2I'A/kHz) f + IOD
IT = (2.4I'A/kHz) f + 100
IT = (3.6I'A/kHz) f + IDD
°T,ow = -55 0 C for AL DeVIce, -40 0 C for CL/CP Device.
ThIgh = +125 0 C for AL Device, +85 0 C for CLlCP Device.
"Noise Immunity spet;lfied for worst·case input combination
NOIse MargIn for both "I" and "0" level, = '1.0 Vdc min@ VDD = 5,0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
tTo calculate total supply current at loads other than 50 pF:
IT(CL) = 'T(50 pF) + 41( 10-3 (CL -50) VDDf
where: I,. IS in!JA (per package), CL in pF, VDD in Vdc, and f on kHz is input frequency .
• ° The formulas gIven are for the typical characteristics only at 25 0 C.
This device 'contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is ad·
vised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high im·
pedance circuit. For proper operation it is recommended that Vin and V out be constrained to the range VSS .. (V in or V out )
'" VDD
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDDI.
4-45
II
MC14558B
SWITCHING CHARACTERISTICS·
leL ~ 50 pF, T A • 25°C; see Figure 1)
CharlCteristic
II
Symbol
Output Rise Time
tTLH = 13.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = 11.1 ns/pFI CL + 10 ns
tTLH
Output Fall Time
tTHL" 11.5 ns/pFI CL + 25 ns
tTHL = 10.75 ns/pF) CL + 12.5 ns
tTHL" (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time
tPLH = 11.7 ns/pFI CL + 495 ns
tPLH = (0.66 ns/pFI CL + 187 ns
tPLH" (0.5 ns/pFI CL + 120 ns
tTHL
Propagation Delay Time
tpHL = (1.7 ns/pF) CL + 695 ns
tpHL = 10.66 ns/pFI CL + 242 ns
tpHL = (0.5 ns/pF) CL + 160 ns
tPHL
VDD
Min
Typ
MIl.
-
100
200
100
80
5.0
10
15
-
5.0
10
15
-
Unit
ns
50
40
nl
tPLH
5.0
10
15
200
100
580
220
145
1160
440
230
780
275
185
1560
550
370
80
ns
-
5.0
10
15
100
50
40
nl
-
• The formulae given are for the typical characteristics only.
TRUTH TABLE
OUTPUTS·
INPUTS
0
Pin 6
C
B
A
Pin 2
Pin 1
Pin 7
a
Enable
RBI
Pin 3
Pin 5
1
1
0
0
0
0
1
1
x
0
0
0
1
0
Pin 13
b
Pin 12
c
Pin 11
d
Pin 10
f
Pin 15
9
Pin 14
RBO
Pin 4
DISPLAY
n
1
1
1
1
1
0
1
0
0
0
1
1
0
1
I
I
2
U
1
X
0
0
1
0
1
1
0
1
1
0
1
1
1
X
0
0
1
1
1
1
1
1
0
0
1
1
~
1
X
0
1
0
0
0
1
1
0
0
1
1
1
'-I
1
X
0
1
0
1
1
0
1
1
0
1
1
1
5
1
X
0
1
1
0
0
0
1
1
1
1
1
1
b
1
X
0
1
1
1
1
1
1
0
0
0
0
1
1
X
1
0
0
0
1
1
1
1
1
1
1
1
1
X
1
0
0
1
1
1
1
0
0
1
1
1
q
0
0
0
0
0
0
Blank
i
I
8
1
0
0
0
0
0
0
0
0
0
X
X
X
X
1
1
1
1
1
1
1
0
B
0
1
X
X
X
X
0
0
0
0
0
0
0
1
Blanlt
• All non-valid BCD input cOdes produce. blank display
X
e
Pin 9
=.
Don't Car.
FIGURE 1 - SIGNAL WAVEFORMS
20 ns
Any Input
Any Output
-----~
4-46
MC14558B
I
4-47
MC14558B
TYPICAL APPLICATIONS
FIGURE 2 - LEADING AND TRAILING ZERO
SUPPRESSION WITH LAMP TEST
N3
N4
---
RBc5
RBi
ABo
~ ABI
Nl
N2
r----
ABo
ABI
r--
N·2
N·l
RBI RBO
I""'" ABI
RBc5
l ...
ABo
En
En
En
En
En
En
1
1
1
1
1
1
I
N·3
RiJ
, - RBI
En
I
Vss
FIGURE 3 - LEADING AND TRAILING ZERO SUPPRESSION
WITH PWM INTENSITY BLANKING AND NO LAMP TEST
N3
N4
N2
N·l
Nl
N·2
N·3
Vee
r-
RBc5
ABI
nking
En
!
1
-
ABo
RBI
En
1
-
A8i
ABo
L...
En
1
RsO
ASci
L.....
FIGURE 4 - ZERO SUPPRESSION WITH LAMP TEST
AND INTENSITY BLANKING
N4
N3
N·2
N2
Blankinll"'--4~-~-"""
LampT."~::~~::::~~~-l
~-'-------------r------------------------------~
4-48
N·3
®
MC145000
MC145001
MOTOROLA
SERIAL INPUT
MULTIPLEXED LCD DRIVERS
(MASTER AND SLAVE)
CMOS LSI
(LOW-POWER COMPLEMENTARY MOS)
The MC145000 {Master} LCD Driver and the MC145001 (Slave) LCD
Driver are CMOS devices designed to drive liquid crystal displays in a
multiplexed-by-four configuration. The Master unit generates both
frontplane and backplane waveforms, and is capable of independent
operation. The Slave unit generates only frontplane waveforms, and is
synchronized with the backplanes from the Master unit. Several Slave
units may be cascaded from the Master unit to increase the number of
LCD segments driven in the system. The maximum number of frontplanes is dependent upon the capacitive loading on the backplane
drivers and the drive frequency. The devices use data from a
microprocessor or other serial data and clock source to drive one LCD
segment per bit.
• Direct Interface to CMOS Microprocessors
• Serial Data Port, Externally Clocked
SERIAL INPUT
MULTIPLEXED LCD DRIVERS
(MASTER AND SLAVE)
~~
24~VUUlU'
24~~VlUl'
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
CASE 623
PLASTIC PACKAGE
CASE 700
• Multiplexing-By-Four
• Net dc Drive Component Less Than 50 mV
• Master Drives 48 LCD Segments
• Slave Provides Frontplane Drive for 44 LCD Segments
18
• Drives Large Segments -Up to one Square Centimeter
~
"VDl~lJ~
P
• Supply Voltage Range= 3 V to 6 V
•
Latch Storage of Input Data
•
Low Power Dissipation
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
CASE 726
PLASTIC PACKAGE
CASE 707
• LogiC Input Voltage Can Exceed VDD
• Accomodates External Temperature Compensation
• See Application Note AN-823A, Section 4
• Chip Complexities: MC145000-1723 FETs or 431 Equivalent Gates
MC145001-1495 FETs or 374 Equivalent Gates
ORDERING INFORMATION
MC14XXXX
T
Suffix Denotes
L Ceramic Package
P Plastic Package
L
PIN ASSIGNMENTS
FP1
FP2
VDD
OSCout
OSCin
Frame-Sync. Out
FP3
FP4
FP5
Data Out
FP6
FP7
FP8
Data Clock
Data In
BP1
FP9
FP10
FP11
BP2
BP3
BP4
VSS
FP12
FP1
FP2
FP3
FP4
FP5
FP6
FP7
VDD
OSCin
Frame-Sync. In
Data Out
Data Clock
Data In
FP11
FPlO
FP9
FP8
VSS
MC145001
Slave
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the ranges VSssVoutSVDD
andVSSSVin s15V
Unused inputs must always be tied to an appropriate logic voltage level.
MC145000
Master
4-49
II
MC145000
MAXIMUM RATINGS (Voltages referenced to Vss)
Characteristic
DC Supply Voltage
Input Voltage, Data In and Data Clock
Input Voltage, Pin 22 of Master
DC Input Current, per Pin
Operating Temperature Range
Storage Temperature Range
Symbol
Value
Unit
VDD
-0.5 to +6.5
V
Yin
-0.5to15
V
Yin osc
- 0.5 to VDD + 0.5
V
lin
±10
mA
TA
T stg
-40 to +85
°C
-65 to + 150
°C
ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS)
Characteristic
RMS Voltage Across a Segment
(SPi-FPjl
"ON"
Segment
"OFF"
Segment
I
Average DC Offset Voltage
"0" Level
Input Voltage
"1" Level
Output Drive Current High-Current State"
VO=2.85 V
VO= 1.B5 V
VO= 1.15 V
VO=0.15 V
Min
25°C
Typ
Max
-
1.73
3.46
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.00
2.00
-
-
-
-
30
50
10
20
30
50
-
30
50
mV
VIL
3.0
6.0
-
1.35
2.70
0.90
1.80
-
-
0.90
1.BO
-
0.90
1.80
V
VIH
3.0
6.0
2.10
4.20
-
2.10
4.20
1.65
3.30
-
2.10
4.20
-
ISH
3.0
150
220
160
400
-
-
75
110
80
200
190
200
200
-
35
55
40
100
-
500
1000
BOO
-
-
-
500
-
125
250
200
125
140
2.4
2.2
400
-
35
0.6
0.5
100
-
190
15
13
B50
-
BO
140
180
100
-
140
360
-
VOO
V
VON
3.0
6.0
-
VOFF
3.0
6.0
Vdc
3.0
6.0
85°C
Min Max
-
-
-
Unit
V
V
V
Sackplanes
VO=5.85 V
VO=3.85 V
VO=2.15V
VO=015V
Low-Current State"
VO=2.B5 V
VO= 1.85 V
VO=1.15V
VO=0.15 V
VO=5.85 V
VO=3.85 V
VO=2.15V
VO=0.15 V
Output Drive Current - Frontplanes
High-Current State"
VO=2.85 V
VO=1.85V
VO=1.15V
VO=0.15V
VO=5.B5
VO=3.85
VO=2.15
VO=0.15
-40°C
Min Max
Symbol
V
V
V
V
Low-Current State"
VO=2.85 V
VO= 1.85 V
VO= 1.15 V
VO=0.15 V
VO=5.85 V
VO=3.85 V
VO=2.15V
VO=0.15V
ISH
ISL
IBL
IFH
IFH
6.0
3.0
6.0
3.0
6.0
400
100
IFL
IFL
3.0
6.0
60
2.B
2.2
100
100
16
13
200
250
300
300
-
500
600
400
250
500
300
70
1.2
1.1
200
80
2.8
2.5
330
-
95
7.5
6.5
425
105
10
9
570
-
40
70
60
50
60
120
100
95
70
180
200
50
90
250
240
120
-
-
30
1.4
1.1
50
40
2.8
2.5
100
-
60
-
-
-
50
B.O
6.5
100
-
-
-
-
-
-
-
-
-
-
-
-
-
45
3.7
3.2
210
-
-
-
-
35
90
100
25
-
p.A
p.A
-
175
-
-
lin
6.0
-
±0.1
-
±O.OOOOl
±0.1
-
±1.0
Input Capacitance
Cin
-
-
-
-
5.0
7.5
-
-
Quiescent Current (Per Package)
Vin=O or VDD, 10ut=0 p.A
100
3.0
6.0
-
10
185
-
2.5
50
15
175
-
20
-
p.A
-
Input Current
-
p.A
-
-
9
p.A
-
-
25
4.0
3.2
50
10
I'A
-
20
35
30
25
15
0.7
0.5
25
I'A
-
130
p.A
p.A
pF
p.A
• For a time (ta 2.56/ osc. freq.) after the backplane or frontplane waveform changes to a new voltage level, the circuit is maintained in the highcurrent state to allow the load capacitances to charge quickly. Then the circuit is returned to the low-current state until the next voltage level
change occurs.
4-50
MC145000
SWITCHING CHARACTERISTICS ICL - 50 pF TA = 25°CI
Characteristic
Symbol
Data Clock Frequency
fcl
Rise and Fall Times - Data clock
Setup Time
Data In to Data Clock
Hold Time
Data In to Data Clock
Pulse Width
Data Clock
VOO
3.0
6.0
tr,tf
3.0
6.0
Min
Typ
-
12.5
24
-
-
Max
7..5
125
125
10
-
-
tsu
30
6.0
48
-
16
-
-5
0
-
th
3.0
6.0
-
-
tw
3.0
6.0
65
40
-
-
-
Unit
MHz
,.s
ns
ns
ns
SWITCHING WAVEFORMS
Data In
VDD -
Data Clock
VDD -
0-
0-
DEVICE OPERATION
The Slave unit (Figure 2) consists of the same circuitry as
the Master unit, with two exceptions: it has no backplane
drive circuitry, and its shift register and latch hold 44 bits.
Eleven frontplane and no backplane drivers are available
from the Slave unit.
Figure 1 shows a block diagram of the Master unit. The
unit is composed of two independent circuits: the data input
circuit with its associated data clock, and the LCD drive circuit with its associated system clock.
Forty-eight bits of data are serially clocked into the shift
register on the falling edges of the external data clock. Data
in the shift register is latched into the 48-bit latch at the beginning of each frame period. (As shown in Figure 3, the
frame period, tframe, is the time during which all the LCD
segments are set to the desired "ON" or "OFF" states.)
The binary data present in the latch determines the appropriate waveform signal to be generated by the frontplane
drive circuits, whereas the backplane waveforms are invariant. The frontplane and backplane waveform:;:, FPn and
BPn, are generated using the system clock (which is the
oscillator divided by 256) and voltages from the V /3
generator circuit (which divides VDD into one-third increments). As shown in Figure 3, the frontplane and
backplane waveforms and the "ON" and "OFF" segment
waveforms have periods equal to tframe and frequencies
equal to the system clock divided by four.
Twelve frontplane and four backplane drivers are available
from the Master unit. The latching of the data at the beginning of each frame period and the carefully balanced voltagegeneration circuitry minimize the generation of a net dc component across any LCD segment.
LCD DRIVER SYSTEM CONFIGURATIONS
Figure 4 shows a basic LCD Driver system configuration,
with one Master and several Slave units. The maximum
number of slave units in a system is dictated by the maximum backplane drive capability of the device and by the
system daw update rate. Data is serially shifted first into
the Master unit and then into the following Slave units on
the falling edge of the common data clock. The oscillator is
common to the Master unit and each of the Slave units. At
the beginning of each frame period, tframe, the Master unit
generates a frame-sync pulse IFigure 3) which is received by
the Slave units. The pulse is to ensure that all Slave unit
frontplane drive circuits are synchronized to the Master
unit's backplane drive circuits.
A single multiplexed-by-four, 7-segment (plus decimal
point) LCD and possible frontplane and backplane connections are shown in Figure 5. When several such displays are
used in a system, the four backplanes generated by the
Master unit are common to all the LCD digits in the system.
The twelve frontplanes of the Master unit are capable of controlling forty-eight LCD segments (6 LCD digits), and the
eleven frontplanes of each Slave unit are capable of controlling forty-four LCD segments (5 Y2 LCD digits).
4-51
II
MC145000
FIGURE 1 Data Out
20
BLOCK DIAGRAM OF THE MCl46000 (MASTER) LCD DRIVER
Bit 1
Bit 1
FPl
FP2
FP3
*
.r;
.:::
.....J
(J)
CD
'6>
Q)
:c
6
Q)
.~
0
8
~
B-c:
~
~
II
FP4
FP5
FP6
FP7
Q)
~
in
5
U
2
~
a:
4
'"
'S
9
10
11
FP8
FP9
FP10
FP11
13
FP12
Bit 48
19·
Data
Clock
·Pins 18 and.19 can
be driven to voltages
greater than VDD,
Frame-Sync
Pulse
18·
Data In
System Clock
22
23
OSCin OSC out
FIGURE 2 -
21
Frame-Sync
Out
BLOCK DIAGRAM OF THE MCl45001 (SLAVE) LCD DRIVER
Data Out
15
FPl
2
3
'"
li;
'S
Til
'6>
2
U
.r;
Q)
~
a:
Q)
6
0
CD
~
B-c:
~
~
8
10
11
12
14·
Data
Clock
·Pin!! 13 and 14 can be
driven to voltages
greater than VDD,
13·
Data In
System Clock
17
OSCin
16
Frame-Sync
In
4-52
FP3
FP4
FP5
FP6
FP7
Q)
~
CD
5
.~
.....J
:c
(J)
4
FP2
FP8
FP9
FP10
FP11
MC145000
FIGURE 3 - VOLTAGE WAVEFORMS
Voo -
System Clock
(Oscillator + 256)
n nnn nn nn r
O_~UUUUUUUU
VD:~J~~~_l
Frame-8ync Pulse
BP1
Voo 2/3 (VOOI 1/3 (V ~Ol -
BP2
VOO 2/3 (VOOI1/3 (VOOI-
0-
II
0-
Backplane
Waveforms
BP3
Voo 2/3 (VOOI 1/3 (VOOI-
0Voo 2/3 (V ~Ol 1/3 (VOOI-
BP4
0-
....
I4--tframe-........~I ~-tframe---.{
Example: One segment ON
Frontplane waveform (FPI) for segment
f to be "ON" and
{
d, e, g to be
"OFF" (Figure 51
ON segment
voltage waveform
across segment f
(BP1-FPll
VOO2/3 (VOOI 1/3 (VOO)-
0-
VOO2/3 (VOOI 1/3 (VOOI -
i
- - - .....-
Example: All segments OFF.
Frontplane waveform (FP2) for segments (
Voo _
t'
2/3 (VOOI 1/3 (VOO) -
a, b, c and h to
be "OFF"
(Figure 51.
OFF segment
voltage waveform
across segment b.
(BP2-FP21
Frame RMS Voltage= VOO/$
Frame de Offset Voltage< 50 mV
0-
-1/3 (VOO)-2/3 (VOO) -VOO -
tframe~
r-
r-, 1"1 11 r-1 n
1"1 11 11
- - l L-I L-I L-J
L.J L.J L.J L-J L-I
0-
VOO2/3 (VOO) 1/3 (VOO) -
i
Frame RMS Voltage=VDO/3
Frame de Offset Voltage<50 mV
0-
- 1/3 (VOO) -2/3 (VOO)-Voo -
j..-. tframe -
.......
, •..-- tframe----.t
4-53
MC145000
FIGURE 4 -
BASIC SYSTEM CONFIGURATION
Frame Sync.
Rext
(Optional)
System Clock
Oscillator o---------,-.JV\I\rData Clock
O-----+--_---I-~f--------+_-_-+_----I
OSC out
MC145000
Master LCD
Driver
Serial Data In
OSCin
Data
Out
MC145001
Slave LCD
Data
Driver
In L..._......._ _ _....J
Data
MC145001
Slave LCD
Driver
4 Backplanes
I
LCD Array
FIGURE 5 -
FRONTPLANE AND BACKPLANE CONNECTIONS TO A MULTIPLEXED-BY-FOUR
7-SEGMENT (PLUS DECIMAL POINT) LCD
FPl
.Pl
yfl
FP2
BP1
SEGMENT TRUTH TABLE-
Ib
BP2~BP2
el
Ie
..
~--~III~BP4
Typical Backplane Configuration
BP2
9
b
BP3
e
c
a
BP4
d
d
Because there IS no standard for backplane and frontplane connections on
multiplexed displays, this truth table may
be used only for this example.
BP3-~-_ _------.--~------BP3
BP4---__. . . .
FP1
f
FP2
BPl
Typical Frontplane Configuration
PIN DESCRIPTIONS
DATA CLOCK (Master: Pin 19)
(Slave: Pin 14)
The input pin for the external data clock, which controls
the shift registers. This pin can be driven to 15 volts
regardless of the value of VDD.
FRONTPLANE DRIVE OUTPUTS
(Master: FP1-FP12; Pins 1-11 and 13)
(Slave: FP1-FP11; Pins 1-8 and 10-12)
The frontplane drive waveforms for the LCDs.
DATA OUT (Master: Pin 20)
(Slave: Pin 15)
BACKPLANE DRIVE OUTPUTS
(Master: BP1-BP4; Pins 14-17)
The backplane drive waveforms for the LCDs.
The serial data output pin.
FRAME-SYNC OUT (Master: Pin 21)
The output pin for the frame-sync pulse, which is
generated by the Master unit at the beginning of each frame
period, tframe. From Figure 1, the 48-bit latch is loaded during the positive Frame-Sync Out pulse. Therefore, if the Data
Clock is active during this load interval, the display will
flicker.
DATA IN (Master: Pin 18)
(Slave: Pin 13)
The serial data input pin. Data is clocked into the shift
register on the falling edge of the data clock. A high logic
ievei wiii cause th& corresponding LCD segment to be turned on, and a low logic level will cause the segment to be
turned off. This pin can be driven to 15 volts regardless of
the value of VDD, thus permitting optimum display drive
voltage.
FRAME-SYNC IN (Slave: Pin 16)
The input pin for the frame-sync pulse from the Master
unit. The frame-sync pulse synchronizes the Slave frontplane drive waveforms to the Master backplane drive
waveforms.
4-54
MC145000
OSCin (Master: Pin 22)
(Slave: Pin 17)
Vee (Master: Pin 24)
(Slave: Pin 18)
The input pin to the system clock circuit. The oscillator
frequency is either obtained from an external oscillator or
generated in the Master unit by connecting an external
resistor between the OSCin pin and the OSCout pin (Pin 23).
Figure 6 shows the relationship between resistor value and
frequency.
The positive supply voltage.
VSS (Master: Pin 12)
(Slave: Pin 9)
The negative supply (or ground) voltage.
OSCout (Master: Pin 23)
The output pin of the system clock circuit. This pin is connected to the OSCin input (Pin 17) of each Slave unit.
FIGURE 6 - TYPICAL OSCILLATOR FREQUENCY
vs EXTERNAL RESISTOR VALUE
10 M
~
~
II
~
~tDD=6V
1M
"iii
>
VDD=3V~
10 k
1k
100 k
10 k
1M
10M
Oscillator Frequency (Hz)
APPLICATIONS
The following examples are presented to give the user further insight into the operation and organization of the Master
and Slave LCD Drivers.
An LCD segment is tL!rned either on or off depending
upon the RMS value of the voltage across it. This voltage is
equal to the backplane voltage waveform minus the frontplane voltage waveform. As previously stated, the backplane
waveforms are invariant (see Figure 3). Figure 10 shows one
period of every possible frontplane waveform.
For a detailed explanation of the operation of liquid crystal
materials and multiplexed displays, refer to a brochure entitled "Multiplexed Liquid Crystal Displays," by Gregory A.
Zaker, General Electric Company, Liquid XTAL Displays
Operation, 24500 Highpoint Road, Cleveland, Ohio 44122.
first bit to be entered has been shifted into bit-location one,
the second bit into bit-location two, and so on. Table 1
shows the bit location in the latch that controls the corresponding frontplane-backplane intersection. For example,
the information stored in the 26th-bit location of the
latch controls the LCD segment at the intersection of FP7
and BP3. The voltage waveform across that segment is equal
to (BP3 minus FP71. The same table, but with the column for
FP12 deleted, describes the operation of the Slave unit.
In applications of this type, all the necessary data to completely update the display are serially shifted into the Master
and succeeding Slave units within a frame period. Typically,
a microprocessor is used to accomplish this.
Example 2: Many keyboard-entry applications, such as
calculators, require that the most significant digit be entered
and displayed first. Then as each succeeding digit is entered,
the previously entered digits must shift to the left. It is,
therefore, neither necessary nor desirable to enter a completely new set of data for each display change. Figure 7
shows a representation of a system consisting of one Master
and three Slave units and displaying 20 LCD digits. If each
digit has the frontplane-backplane configuration shown in
Figure 5, the relationship between frontplanes, backplanes,
and LCD segments in the display is shown in Table 2.
Example 1: Many applications (e.g., meters, gasoline
pumps, pinball machines, and automobile dashboard
displays) require that, for each display update, an entirely
new set of data must be shifted into the Master and cascaded Slave units. The correspondence between the frontplanebackplane intersections at the LCD segments and the data
bit locations in the 48-bit latch of the Master (or 44-bit latch
of the Slave) is necessary information to the system
designer. In Figure 1, it is shown that data is serially shifted
first into the 48th-bit location of the shift register of the
Master. Thus, after 48 data bits have been shifted in, the
4-55
MC145000
Digits (or alphanumeric characters) are entered, mostsignificant digit first, by using a keyboard and a decoder external to the MC145000. Data is entered into the Master
and cascaded Slave units according to the following format:
1) Initially, all registers and latches must be cleared by
entering 160 zero data bits. This turns off all 160 segments of
the display.
2) Entering the most-significant digit from the keyboard
causes the appropriate eight bits to be serially Shifted into
the Master unit. These eight bits control LCD segments a
through h of digit 1, and cause the desired digit to be
displayed in the least-significant digit location.
3) Entering the second-most-significant digit from the
keyboard causes eight more bits to be serially shifted into the
Master unit. These eight bits now control LCD segments a
II
through h of digit 1, and the previously entered eight bits
now control segments a through h of digit 2. Thus the two
digits are displayed in the proper locations.
4) Entering the remaining 18 digits from the keyboard fills
the 20-digit display. Entering an extra digit will cause the first
digit entered to be shifted off. the display.
Example 3: In addition to controlling 7-segment (plus
decimal point) digital displays, the MC145000 and MC145001
may be used to control displays using 5 x 7 dot matrices. A
Master and three Slave units can drive 180 LCD segments,
and therefore are capable of controlling five 5 x 7 dot
matrices (175 segments). Two control schemes are
presented in Figures 8 and 9; one using a single Master unit,
and one using two Master units.
TABLE 1 - THE BIT LOCATIONS, IN THE LATCH, THAT CONTROL THE
LCD SEGMENTS LOCATED AT EACH FRONTPLANE-BACKPLANE INTERSECTION
FRONTPLANES
FPl
FP2
FP3
FP4
FP5
FP6
FP7
FP8
FP9
FPlO
FPll
FP12
BPl
4
8
12
16
20
24
28
32
36
40
44
48
BP2
3
7
11
15
19
23
27
31
35
39
43
47
BP3
2
6
10
14
18
22
26
30
38
42
46
BP4
1
5
9
13
17
21
25
29
34
33
37
41
45
(Jl
w
Z
S
c..
~
u
«
III
FIGURE 7 - A 20-DIGIT DISPLAY
(EQUIVALENT TO A 4x40 ARRAY)
3 digits controlled
by Slave #3
5Y, digits controlled by
Slave #1
5 It, digits controlled by
Slave #2
6 digits controlled by Master
Note that only six
of the 11 Irontplanes are used
Data In
FP11
FP7
FP6
I
FJlO
FP2
FP10
FP1
I
I
FP9 FP11
FPl
FP11
FP2
FJlO
I
FP10 FP12
FP2
I
F!9 Fplll
FP1
I
TABLE 2 - THE RELATIONSHIP BETWEEN FRONTPLANE-BACKPLANE INTERSECTIONS
AND LCD SEGMENTS FOR THE SYSTEM CONFIGURATION OF FIGURE 7
.._. . . .
t-o------ Master -----I~~I
BP1
FP12
FP11
FP10
FP9
a1
11
a2
12
gl
g2
FPl
FPll
a6
16
a7
17
b7
g7
b6
g6
FP10
#l--l"~I....t-----Slave #2---1.~I",,,,---Slave #3~
-- -
---
FPl
FP11
FP10
FP1
FP11
FP10
a12
112
a13
113
a17
117
a18
118
g12
b13
g13
b17
g17
b18
g18
b12
FP9
FP2
BP2
bl
8P3
~,
e1
~2
t:?
c6
e6
e7
e7
e12
e12
e13
e13
e17
e17
BP4
h1
d1
h2
d2
h6
d6
h7
d7
h12
d12
h13
d13
h17
d'7
digit 1
b2
---
-Slave
FP2
digit 2
I_ - -I
digit 6
digit 7
I- - -I
digit 12
4-56
I
digit 13
I- - -I
digit 17
I
-- -
FP7
FP6
a20
120
b20
g20
e18
e18
e20
e20
h18
I d18 I
I h~U I
dLU
digit 18
I_ - -I
digit 20
I
I
MC145000
EXAMPLE OF A 5 x 7 DOT MATRIX DISPLAY SYSTEM CONTROLLED
BY ONE MASTER AND THREE SLAVE UNITS
FIGURE 8 -
I
Master
Slave #1
JI
Slave #3
Slave #2
I
FP11
FP9
I
FP12
FP10 I FPS
I
I
I
I
I
I
I
,
I FP1
I
I FP10
I
I
FP11
FP2
FP3
,
I
I
FP4
FP2
I
,
,
I
FP4
I
FP6
I
I FP3
I
I
FP5
I FP1
I
I
I
FP7
I
I
I
I
FP6
FP8
I
I
,
I FP3
F~5
I
FP9
,1
BP1
FP7
I
I
I
FP5
f
!
BP2
r
BP3
BP4
... ...
~-
~---
.-
~!
!~
.,.. T
I
I
FP7
I
I
I
I
FP6
'T'-I
I
I
I
FP5
I
I
FP4
I
I
I
I
I
I
I FP7
I
I
FP9
i
I
I
'FP11
f
I
FPS
FP6
I
~1
, T T'I
I
../~r
/":
~
/"
/":
I
./
T T'-
/1
I
I
FP9
I
FP10
I
Ft2
I
I
FP'lO
FP1
FPS
FP4
I
I
I
I
FP2
I
l
I
I
FPll
I
I
I
I
T 1'-
I
I
f
I
I
:
I
~.--
~
. /~!
./ ~
"'i"l""
I
I
I
,
.. r
../ ~ -
~.-.-
~r
V1:~
-
!
I
I
FP3
FP1
FIGURE 9 - EXAMPLE OF A 5x 7 DOT MATRIX DISPLAY SYSTEM
CONTROLLED BY TWO MASTER AND TWO SLAVE UNITS
Master A
FP11
FP9
FP12 ~ FP10 ~ FPS
A
A
I A
I
I
I
I
I
I
BP1 A
,
I
I
,
,
I
I
I
,
I
I
I
__
--~~~~
BP2A - -__
Master A
__
FP4
FP7 A FP5
~
,I
~
I
__
A
BP4A
BP1 B
--~~~~
I
I
,
I
I
I
I
I
,
I
I
I
__
~~~.---~~~
---4~a-~~~~--~
A :
I
~
__
__ __
~
,
I
I
__
~
,
I
~----~
__
I
__
~----~
FP7
A
I
A
FPS
A
I
I
I
I
,I ,I
I
~~~----~
-
FP11,A FP9
I
I
--~~~
FP2 A
A
I
,
FP3
I
I
:
I
FP10
FP1
I
A
I
BP3A
I
M,,,,,, B
~
FP6
Slave A
I
I
~
__HH__
~
~
I
I
I
I
,
,
I
I
I
,I
,
I
I
I
I
I
I
~~~~r---~~
__ __
FP5
FP6
A
__
,
I
~
I
I
I
__
FP4
A
,
~
~~----_.~._~~~
~~----
__ __ __
~
~
~
---._.~--~~:~~:.---~~~--~--~----~--~--~~-----~:~-~:~:~~_
__
__~__--~~~__~__~----~__~j(
~~~--~~
__
~-'~
BP2B--~~____~~--~~~~~----~~~~~--~~'-~~.
BP3B--~~____~~--~~~~~----~~~I~~~--~~__~~
I
I
I
I
I
I
I
I
I
,
I
I
I
I
I
I
I
I
F~12 I F~10
I F~8
B FP'll B FP9 B
B
B
I
FP7
I
I
I
I
, ,I I,
I
I
I
I
I F~5 I
I
I
I
I
I
I
I FP3
B FP6 B
FP4 B
B
,
I
FP2
I
I
I
I
I
I
I
I
I
I
, I,
, I
I
I
I
I
I
I
I
I
I
I
I
I
I F~ll I
B FP1
B
B
T
~P9
FP8
B
B FPlO B
B
Leos can be obtained from:
AND, LXD, Hamlin, and other suppliers.
4-57
I FP6 I FP4
B
FPl B
FP5
B
I
Master B
I
Slave
B
B
II
MC145000
FIGURE 10 - POSSIBLE FRONTPLANE WAVEFORMS
1-.--..
Frame-Sync
Pulse
tl rame
---·~-.jl
I-
voJ'-----~
o
Frame-Sync
Pulse
VOO
/3tuLn-n-iI
FPl for e, 9 on
FP2 for b, c on
I
off
2V OO
FP2 for a, b, c, h
off
VOO/3
2VOO/3
VOO/3
0
I
I
I
Voo
FPl lor e on
FP2 for a on
VOO
2VOO/3
FPl for d, 9 on
FP2 for b, h on
VOO/3
o
2VOO/3
VOO/3
0
Voo
FPl for I on
FP2 lor b on
VOO
2VOO/3
FPl for d, e on
FP2 for c, h on
VOO/3
2VOO/3
VOO/3
o
FPl for e on
FP2 for c on
FPl for d on
FP2 for h on
FPl for f, 9 on
FP2 for a, b on
FPl for e, f on
FP2 for a, con
VOO
VOO
2VOO/3
VOO/3
FPl for e, f, 9 on ' 2VOO/3
FP2 for a, b, c on VOO/3
o
0
VOO
VOO
2VOO/3
VOO/3
FPl for d, f, 9 on 2VOO/3
FP2 for a, b, h on VOD/3
o
0
VOO
VOO
2VOO/3
VOO/3
FPl for d, e, f on 2VOO/3
FP2 for a, c, h on
VOO/3
o
0
VOO
VOO
2VOO/3
FPl for d, e, 9 on 2VOO/3
FP2 for b, c, h on VOO/3
VOD/3
o
FPl for d, f on
FP2 for a, h on
VOotJut-J1!
VOO/3
n
-
0
r
2VOO/3
~I
~
I
I
I
I
FPl lor d, e, f, 9
v :]
tframe
VOO
FPl for e, d, f, 9 on 2VOO/3
FP2 for a, b, c, h on VOO/3
0
J
4-58
I
I
®
MC145453
MOTOROLA
.VMI~i\
Advance Information
Ii:
li!!
40
LCD Driver with Serial Interface
1
PLASTIC
CASE 711
LSI CMOS
The MC145453 Liquid-Crystal Display Driver consists of a 36-stage serial-in/parallei-out shift register with 33 latches and drivers. Each package drives up to 33 nonmultiplexed LCD segments; e.g., a 4 '/z-digit, 7-segment-plus-decimal display. This
device may be paralleled to increase the number of segments driven.
The input format is a Start Bit (high), followed by 33 Display Bits, plus 2 Trailing
Bits (don't cares). A high Start Bit, after propagating to the last shift register stage,
triggers generation of an internal load signal which transfers the 33 Display Bits into
latches. An internal reset clears only the shift register which readies the device for
the next bit stream.
•
•
•
•
•
•
•
On-Chip Oscillator Provides 50 Percent Duty Cycle Backplane Drive
No External Load Signal Required
Operating Voltage Range: 3 to 10 V
Operating Temperature Range: -40 0 to 85°C
TTL-Compatible Inputs May Be Driven With CMOS
May Be Used With Segmented-Alphanumeric, Bar-Graph, or Dot-Matrix LCDs
Advantages Over Multiplexed LCD Systems: Wider Viewing Angle
Optimum Contrast at Low Voltage
Better Legibility at Extreme Temperature
PLASTIC LEADED
CHIP CARRIER (PLCCI
CASE 777
ORDERING INFORMATION
MC145453P Plastic DIP
MC145453FN PLCC
BLOCK DIAGRAM
SP OUT
OUT 33
SP IN
OUT 2 OUT 1
OSCIN----.....-J
DATA -------i~
CLOCK -------i~
LOAD
35
34
CONTROL LOGIC
36·STAGE SHIFT REGISTER
This document contains information on a new product. Specifications and information herein are subject to change without notice.
4-59
II
MC145453
MAXIMUM RATlNGS* (Voltages Referenced to VSSI
Value
Unit
- 0.5 to + 11.0
V
DC Input Voltage
- 0.5 to VDD + 0.5
V
DC Output Voltage
- 0.5 to VDD + 0.5
V
DC Input Current, per Pin
±20
mA
lout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VDD and VSS Pins
±50
mA
Po
Power Dissipation, per Packaget
500
mW
Symbol
VDD
Vin
V out
lin
Tstg
TL
Parameter
DC Supply Voltage
Storage Temperature
-65 to + 150
°C
260
°C
Lead Temperature (10-Second Soldering I
This device contains protection circuitry to
guard against damage due to high static voltages
or electric fields. However, precautions must be
taken to avoid applications of any voltage higher
than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS ~ (Vin
or Vout)~VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or
VDD except Osc In which must be tied to VSS).
Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur.
tPower Dissipation Temperature Derating: -12 mW/oC from 65°C to 85°C.
II
PIN ASSIGNMENTS
;:!
~
f-
l-
:::J
:::J
:::J
0
0
0
0
:::J
~
f-
~
:::::
f-
E>
'-'
:2
•
OUT 13
l-
~
f-
0
N
f-
:::J
:::J
:::J
0
0
0
;::::;
f-
:::J
<:>
N
N
f-
:::J
<:>
44 43 42 41 40
39
OUT 23
OUT 12
38
OUT 24
OUT 11
37
OUT 25
36
OUT 26
OUT 10
10
OUT 9
11
35
OUT 27
NC
12
34
NC
OUT 8
13
33
OUT 28
OUT7
14
32
OUT 29
OUT 6
31
15
OUT 30
OUT 5
16
30
OUT 31
OUT 4
17
29
OUT 32
18 19 20 21
""
~
N
I--
I--
I--
<:>
0
0
:::J
:::J
:::J
0
OUT 18
OUT 19
OUT 16
OUT 20
OUT 15
OUT 21
OUT 14
OUT 22
OUT 13
OUT 23
OUT 12
OUT 24
OUT 11
OUT 25
OUT 10
OUT 26
OUT 9
OUT 27
OUT 8
OUT 28
OUT7
OUT 29
OUT 6
OUT 30
22 23 24 25 26 27 28
OUT 5
OUT 31
«
«
co
OUT 4
OUT 32
Cl
'-'
CI)
VSS
OUT 17
~
'-'
:2
'-'
'"
0
'-'
I--
f-
~
<:>
0CD
:::J
0CD
""
""
I--
:::J
OUT 3
OUT 33
OUT 2
BP IN
OUT 1
BP OUT
OSC IN
DATA
0
NC = NO CONNECTION
VDD
Data sheet continued following page 11-9
4-60
CLOCK
CMOS Operational Amplifiers/Comparators
5-1
II
CMOS OPERATIONAL AMPLIFIERS/COMPARATORS
Device
Number
MC14573
MC14574
MC14575
Function
Quad Programmable Op Amp
Quad Programmable Comparator
Programmable Dual Op Amp/Dual Comparator
Quantity
Per Package
Single Supply
Voltage Range
Dual Supply
Voltage Range
Frequency Range
Device
Number
Number
of Pins
Operational Amplifiers
4
3 to 15 V
± 1.5 to ± 7.5 V
DC to -1 MHz
MC14573
16
Comparators
4
3 to 15 V
±1.5to ±7.5V
DC to -1 MHz
MC14574
16
2 and 2
3 to 15 V
± 1.5 to ± 7.5 V
DC to -1 MHz
MC14575
16
Function
Operational Amplifiers
and Comparators
II
5-2
®
MC14573
MC14574
MC14575
MOTOROLA
CMOS MSI
QUAD PROGRAMMABLE OPERATIONAL AMPLIFIER
QUAD PROGRAMMABLE COMPARATOR
DUAl/DUAL PROGRAMMABLE
AMPLIFIER-COMPARATOR
The MC14573, MC14574, and MC14575 are a family of quad operational low power amplifiers and comparators using the complementary
P-channel and N-channel enhancement MaS devices in a single
monolithic structure. The operating current is externally programmed
with a resistor to provide a choice in the tradeoff of power dissipation
and slew rates. The operational amplifiers are internally compensated.
• These low cost units are excellent building blocks for consumer, industrial, automotive and instrument applications. Active filters, voltage
reference, function generators, oscillators, limit set alarms, TTL-toCMOS or CMOS-to-CMOS up converters, A-to-D converters and zero
crossing detectors are some applications. These units are useful in both
battery and line operated systems.
• Low Cost Quads
• Power Supply - Single 3.0 to 15 V
Dual ± 1.5 to ± 7.5 V
• Wide Input Voltage Range
• Common Mode Range 0.0 to VDD - 2.0 V for Single Supply
• Externally Programmable Power Consumption with One or Two
Resistors
QUAD PROGRAMMABLE
OPERATIONAL AMPLIFIER
QUAD PROGRAMMABLE
COMPARATOR
DUAL/DUAL PROGRAMMABLE
OPERATIONAL
AMPLIFIER-COMPARATOR
.I -
J
-.
.•.
,'I·
" ,
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
CASE 620
PLASTIC PACKAGE
CASE 648
ORDERING INFORMATION
• Internally Compensated Operational Amplifiers
"".m
• High Input Impedance
• Comparators - JEDEC B-Series Compatible
• Chip Complexities: MC14573-30 FETs
MC14574-38 FETs
MC14575-46 FETs
(
I.'
1~UC~ffiX
Denotes
Ceramic Package
Plastic Package
limited Operating
Temperature Range
PIN ASSIGNMENT
Output A
Output D
MCl4673
Quad Op Amplifier
lop,,, A (
MCl4574
Quad Comparator
VDD
lop'" B (
MCl4575
Dual Op Amplifier (A & 61 plus
Dual Comparator (C & DI
} lop,,, D
VSS
} lop'" C
Output 6
Output C
ISet A, 6
ISet C, D
5-3
II
MC14573, MC14574, MC14575
MAXIMUM RATINGSt (Voltages referenced to VSS)
Rating
Symbol
Value
Unit
VDD
-0.5 to + 18
V
Input Voltage, All Inputs
Yin
-0.5 to VOD +0.5
V
DC Input Current, per Pin
lin
±1O
mA
DC Supply Voltage
Programming Current Range
IS et
2
mA
Operating Temperature Range
TA
-40 to +85
°C
Storage Temperature Range
Tstg
-65to +150
°C
Package Power Dissipation"
Po
800
mW
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this high Impedance circuit. For proper operation it is recommended that VJn and Vout be constrained to the
range VSS ~ (Vin or Vout ) ~ VDD
"Derate above 25°C @ 4.6 mW/oC
tMaximum Ratings are those values beyond which damage to the device may occur.
RECOMMENDED OPERATING RANGE
Rating
OC Supply Voltage
Programming Current
VDD = 3V
5 V < VOD < 15 V
Symbol
Value
VOD to VSS
+ 3.0 to + 15
V
ISet
2 to 50
2 to 750
p.A
Unit
OPERATIONAL AMPLIFIER ELECTRICAL CHARACTERISTICS
(IS et = 20 p.A RL = 10 MO CL = 15 pF TA = 25°C, unless otherwise indicated)
Characteristic
Symbol
Input Common Mode Voltage Range
VICR
Output Voltage Range
RL = 1 MO to VSS
VOR
Input Offset Voltage
MC14573, MC14575
Via
VOO
V
Min
Typ
Max
Unit
3
5
10
15
0
0
0
0
-
1.5
3.5
85
13.5
V
3
5
10
15
0.05
0.05
0.05
0.05
2.95
4.95
9.95
14.90
V
3
5
10
15
-
±30
±30
±30
±30
mV
-
-
±5
±8
±1O
±1O
~Vlo/~T
-
-
15
-
Input Capacitance
Cin
-
-
5
10
pF
Input Bias Current
liB
-
1
50
pA
liB
-
-
110
-
-
-
1
100
nA
pA
AVOL
3
5
10
15
2
8
8
8
PSRR
3
5
10
15
45
54
54
54
-
V/mV
Power Supply Rejection Ratio
MC14573, MC14575
8
10
12
12
57
67
67
67
Common Mode Rejection Ratio
MC14573, MC14575
CMRR
3
5
10
15
45
50
54
54
70
73
75
75
-
IOH
5
55
80
-
p.A
IOL
3
2.1
2.5
5.5
15
4.2
5.0
11.0
30
-
mA
5
10
15
SR
-
0.6
0.8
GBW
5
0.5
1
M
-
-
48
-
Degrees
VII'S
-
-
-
SO
-
dB
IDD
15
-
2.6
3.4
mA
II
MC14573, MC14574, MC14575
COMPARATOR ELECTRICAL CHARACTERISTICS (lSet= 20 p.A, RL = 10 MO, CL = 50 pF, T A = 25°C, unless otherwise indicated)
Symbol
Characteristic
Input Common Mode Voltage Range
VICR
Output Voltage Range
"0" Level
VOL
VOO
Min
Typ
Max
Unit
3
5
10
15
0
0
0
0
-
V
-
1.5
3.5
8.5
13.5
3
5
0
0
0
0
0.05
0.05
0.05
0.05
V
15
-
3
5
10
15
2.95
4.95
9.95
14.95
3
5
10
15
-
V
V
10
Output Voltage Range
"1" Level
VOH
Input Offset Voltage
MC14574, MC14575
Via
3
5
10
15
-
±8
±8
±10
±10
-
-
±30
±30
±30
±30
mV
p..V/oC
~VIO/~T
-
-
15
-
Input Capacitance
Cin
-
-
5
10
pF
Input Bias Current
liB
-
1
50
pA
nA
Average Temperature Coefficient of VIO
Input Bias Current
II
-
-
TA= -40°C to +85°C
Input Offset Current
Open Loop Voltage Gain
Power Supply Rejection Ratio
MC14574, MC14575
-
-
1
110
-
-
-
100
pA
VOL
3
5
10
15
1
1
1
1
20
10
6
6
-
V/mV
3
5
10
15
45
57
67
67
67
3
45
50
PSRR
Common Mode Rejection Ratio
MC14574, MC14575
CMRR
Output Source Current
VOH = 2.6
VOH = 2.5
VOH = 4.6
VOH = 9.5
VOH = 13.5
Output Sink Current
V
V
V
V
V
IOH
VOL=O.4V
VOL = 0.4 V
VOL = 0.5 V
VOL = 1.5 V
IOL
Output Rise and Fall Time, 100 mV Overdrive
tTLH,
tTHL
Propagation Delay Time, 5 mV Overdrive
td
Propagation Delay Time, 100 mV Overdrive
td
Channel Separation
Supply Current, Per Pair (RL =
liB
-
00,
ISet= 20p..A, Vin+ = 1.0 V, Vin- =0 V)
(AL = 00, Pins 8 and 9= VOO)
5·6
54
54
54
5
10
15
54
54
3
5
5
-0.35
-2.5
-0.00
55
65
67
67
-
-
dB
-
dB
-
-
10
-1.3
15
-5.0
-0.66
-5.0
-1.1
-2.5
-9.5
3
5
10
15
1.3
1.9
3.5
14
2.6
3.8
6.5
25
-
3
5
-
140
100
120
140
250
180
200
250
ns
15
10
12
15
30
20
24
30
p..s
8
4
6
8
p..s
-
4
2
3
4
-
80
-
dB
180
0.05
250
1.0
p.A
-
10
-
15
-
3
5
-
10
-
15
-
3
5
10
15
-
-
-
100
5
15
-
mA
-
mA
-
-
MC14573, MC14574, MC14575
COMPARATOR ELECTRICAL CHARACTERISTICS (IS et = 200 p.A, RL = 10 MO, CL = 50 pF, TA = 25°C, unless otherwise indicated)
Characteristic
Symbol
Input Common Mode Voltage Range
VICR
Output Voltage Range
"0" Level
VOL
Output Voltage Range
"1" Level
VOH
Input Offset Voltage
MC14574, MC14575
VIO
VOO
V
Min
Typ
Max
Unit
5
10
15
0
0
0
-
3
V
-
8
-
13
5
10
15
-
0.05
005
0.05
V
V
-
0
0
0
5
10
15
4.95
9.95
14.95
5
10
15
-
5
10
15
-
±1O
± 13
±15
±30
±30
±30
mV
p.V/oC
Input Capacitance
Cln
-
Input Bias Current
IFB
-
Average Temperature Coefficient of VIO
TA= -40°C to +85°C
TA= -40°Cto +85°C
Input Bias Current
Input Offset Current
Open Loop Voltage Gam
Power Supply Rejection Ratio
MC14574, MC14575
Output Sink Current
(RL =
Vin+ = 1.0 V, Vin- =0 V)
5-7
pF
-
1
50
pA
-
1
nA
-
100
pA
AVOL
5
10
15
2
1
1
7
4
4
-
5
10
15
45
-
54
54
67
67
67
5
10
15
40
50
50
65
67
67
-
3
5
10
15
- 2.5
-0.60
-1.3
-5.0
-50
-1 1
-2.5
-9.5
5
10
15
1.9
3.5
14
3.8
6.5
25
-
tTLH,
tTHL
5
10
15
-
75
50
45
150
100
90
ns
td
5
10
15
-
25
3.5
5
5.0
7
10
p's
5
10
15
-
0.6
0.75
0.75
1.2
p's
-
-
-
SO
-
dB
IDD
15
-
1.S
2.5
mA
td
00,
10
-
10L
Channel Separation
-
5
-
VOL = 0.4 V
VOL = 0.5 V
VOL = 1.5 V
Propagation Delay Time, 100 mV Overdrive
20
-
-
10H
Propagation Delay Time, 5 mV Overdrive
-
-
VOH = 2.5V
VOH=4.6V
VOH = 9.5 V
VOH = 13.5 V
Output Rise and Fall Time, 100 mV Overdrive
-
-
liB
CMRR
Output Source Current
-
-
110
PSRR
Common Mode Rejection RatiO
MC14574, MC14575
Supply Current, Per Pair
flVIO/flT
-
-
-
-
-
V/mV
-
dB
-
dB
-
mA
-
-
mA
-
-
1.5
1.5
MC14573, MC14574, MC14575
If a pair of op amps is not used. the ISet pin for that pair
may be tied to VOO for minimum power consumption. To
minimize power consumption in an unused pair of comparators this is not effective. The comparators should use a
high value set resistor and the inputs should be set to a
voltage that will force the output to VOO li.e .• + in = VOO.
-in=Vss).
It should be noted that increasing ISet for comparators will
decrease propagation delay for that comparator.
For operational amplifiers. the maximum obtainable output voltage (VOH! for a given load resistor connected to
VSS is given by:
The programming current ISet is fixed by an external
resistor RSet connected between VSS and either one or
both of the IS et pins (8 and 9). When two external programming resistors are used. the set currents for each op amp pair
or comparator are given by:
IS et (/LA) '"
VOO-VSS-1.5
RSet (Mm
Pins 8 and 9 may be tied together for use with a single programming resistor. The set currents for each op amp pair or
comparator pair are then given by:
VOO-VSS-1.5
ISet A. B = ISet C. 0 (/LA) ,..
VOH=4x ISetx RL -0.05 V. RL in
2 RSet (Mm
The total device current is typically 13 times IS et per pair if
the outputs are in the low state. and 5 times IS et per pair if
the outputs are in the high state. For op amps with an output
in the linear region the device current will be between the
values of 5 times and 13 times ISet.
n.
ISet in A
Note: VOH Max= VOO
Typical ap amp slew rates are given by:
SR ,.. 0.04 ISet (V//-Ls). ISet in /LA
SET CURRENT versus VDD
SET CURRENT versus TEMPERATURE
1000
RSet-10 k{l
V
-
-
1000
Rset-100
k{l~ ~
RSet-Constant Value
:<
.5 100
.....
-,
i
J-=-
RSet-1 M{l~ ~
~
-
10
1
1
10
12
14
16
-40
-55
85
LOW FREQUENCY OPEN LOOP VOLTAGE GAIN versus ISet
GAIN-BANDWIDTH PRODUCT versus ISet
357123571235712
235712357123
7 1
t-
6
I....
r-..~t0
0
5
~
~
~~
~~~
........ f=::1==
j...
~ 15V
Voo-l ov
5V
1
I"'
50
100,.A
IS et • PROGRAMMING CURRENT
~~
3
~~
60
125
TEMPERATURE (OC)
VOO. SUPPLY VOL TAGE (VOLTS)
1 mA
~
~
~
~£i:
~
~~
100 p.A
1 mA
ISet. PROGRAMMING CURRENT
5·8
~~ 105 VV
MC14573, MC14574, MC14575
COMPARATOR PROPAGATION DELAY versus ISet
( ± 50 mV OVERDRIVE!
357123571
357
SLEW RATE versus ISet
5712357123571
I I
11111
60
~
50
~
40
~
30
-
VOO-15V
V
-
20
10
10 p,A
1-1111
V
I-::
2 p,A
V Vi-" VOO- 5 V
/. ,,/
-
a
V
IIII
100 p,A
1 rnA
ISet. PROGRAMMING CURRENT
IS et • PROGRAMMING CURRENT
OPEN LOOP GAIN versus FREQUENCY
VOO- 5 V
10
10 0
O~
o IS et - 20 p,A " ' "
o
I
ISet-200 p,A"
0
"
0
100
1k
"
or-
~
~
z
-"'""~
a
a
a
10
~
"''"'
10k
FREQUENCY 1Hz!
IS et -200 p,A "" ' ""
"
0
CI)
C(
-100
~~
-200
10
"'""'",""
0
"'''"'
0
~
20
"'' '
10
\ 1\
0
10
100 k I M
100
1k
100 k
'\ '\
1M
10 M
~ ~.
-100
""j" " ~
100 k I M
10 k
-'\,.'"
OPEN LOOP PHASE DELAY versus FREQUENCY
VOO-10V
ISet- 200 p,A
10k
1k
~
FREQUENCY 1Hz!
~
100
,,,,"
50
OPEN LOOP PHASE DELAY versus FREQUENCY
Voo- 5 V
:r
c..
II
0r--ISet-20 p,A
o~
a
OPEN LOOP GAIN versus FREQUENCY
VOO-10V
I
a
-200
10
10M
FREQUENCY (Hz!
"j""
8
1
100
1k
10 k
100 k I M
FREQUENCY (Hz)
5-9
"~
10 M
MC14573, MC14574, MC14575
SMALL SIGNAL TRANSIENT RESPONSE
VOO = 10 V NON-INVERTING UNITY GAIN
ISet=200 p.A, Vin AVERAGE=5 V
LARGE SIGNAL TRANSIENT RESPONSE
VOO= 10 V NON-INVERTING UNITY GAIN
IS et=200 p.A, Vin AVERAGE=5 V
1
l
~
f\
1
I
/
\
\
~
'I
~
500 ns/DiVISION
500 ns/DiVISION
SMALL SIGNAL TRANSIENT RESPONSE
VOO= 10 V NON-INVERTING UNITY GAIN
IS et =20 p.A, Vin AVERAGE = 5 V
LARGE SIGNAL TRANSIENT RESPONSE
VOO = 10 V NON-INVERTING UNITY GAIN
IS et=20 p.A, Vin AVERAGE = 5 V
z
o
en
;;;
~
c
en
>
o
:;;
1f\1...
II
t
\
I
J'v
500 ns/DiVISION
I
1\
~
500 ns/DIVISION
EQUIVALENT INPUT NOISE VOLTAGE (EN) versus FREQUENCY
2000
TYPICAL INPUT LEAKAGE versus TEMPERATURE
VOO= 15 V Vin=7.5 V
~
1800
/
1000
1600
1400
~
1\
100
~ 1200
~ 1000
~
/
....
~
z
800
0
'Set-200 p.A
I-
~
600
I'
/
1
400
l'
20 0
,....
'Set-20 p.A
II IIII1I
!'-
111111111I111111I1I1I1111111Irr:t+ff9R
10
100
1k
10 k
0.11
100 k
I
-20
I
20
I
40
I
60
TEMPERATURE (0 C)
FREQUENCY (Hz)
5·10
I
I
80
100
MC14573, MC14574, MC14575
COMPARATOR PROPAGATION DELAY versus OVERDRIVE·
VDD = 10 V, tPLH and tPHL
100
10
• A 10 mV overdrive is a signal on one input
01 a comparator that ranges Irom 10 mV
less than the other input to 10 mV more
than the other input.
_ISet-20 ",A
"1
-r-- f-..-
" ...... to--
ISET-200 ",A
0, 1
o
10
20
30
40
50
60
70
80
90
100
OVERDRIVE (mV)
OPERATIONAL AMPLIFIER SCHEMATIC
~th CIRCUIT
II
,lSet Circuit
~02
To gates of 01 and 02 on other half of pair
Non-Inverting Input (+)
Inverting Input (-)
4
*I-+-----+-+-----,
t----<------~.._.,
~I-C
1f lf ]]7
1
VSS
COMPARATOR SCHEMATIC
~th CIRCUIT
IS et Circuit
To gates of 01 and Q2 on other half of pair
r-----1
,Voo
,
Voo,
I
5-11
Oo'p"'
II
5-12
CMOS/NMOS PLLs/Frequency Synthesizers
6-1
II
CMOS/NMOS PLLS/FREQUENCY SYNTHESIZERS
Device
Number
MC6195*
MC6196*
MC14046B
MC14568B
MC145106t
Function
Frequency Synthesizer TV Tuning System
Frequency Synthesizer TV Tuning System
Phase-Locked Loop
Phase Comparator and Programmable Counters
PLL Frequency Synthesizer
MC145145-1# 4-Bit Data Bus Input PLL Frequency Synthesizer
4-Bit Data Bus Input PLL Frequency Synthesizer
MC145146-1
Parallel Input PLL Frequency Synthesizer
MC145151-1
Parallel Input PLL Frequency Synthesizer
MC145152-1
Serial Input PLL Frequency Synthesizer
MC145155-1
Serial Input PLL Frequency Synthesizer
MC145156-1
Serial Input PLL Frequency Synthesizer
MC145157-1
Serial Input PLL Frequency Synthesizer
MC145158-1
Serial Input PLL Frequency Synthesizer with
MC145159-1
Analog Phase Detector
* Closest equivalent for MC6190 through MC6194, which are
being phased out and are not recommended for new designs.
tClosest equivalent for MC145104, MC145107, MC145109,
MC145112, and MC145143, which are being phased out and are
not recommended for new designs.
#Closest equivalent for MC145144, which is being phased out and
is not recommended for new designs
Prescale Modulus
Single-Ended
3-State
Phase Detector
Output
Serial
[Compatible with the
Serial Peripheral
Interface (SPII on
CMOS MCUs]
Single
V'
V'
V' ,
V'
Parallel
Single
Divider Programming
Format
I
Dual
Double-Ended
Phase Detector
Output
V'
V'
V'
V'
(Analog Detector
Outputl
Dual
+R
12*
14
14
11*
12*
V'
12*
V'
4-Bit Bus
2 Control Lines
Single
V'
V'
12
Dual
V'
V'
12
Single
V'
12*
12*
V'
V'
* Limited
number of selectable values
* Mask-programmable to one fixed value
6-2
+A
12*
14
V'
V'
V'
Number of
Divider Stages
7
7
7
6
8*
7
+N
Device
Number
Number
of Pins
14
14
MC145155-1
MC145157-1
18
16
10
10
10
MCl45156-1
MC145158-1
MC145159-1
20
16
20
9
14
MC145106
MC145151-1
18
28
10
4
MC145152-1
MC14568B
L8
14
MC145145-1
18
10
MC145146-1
20
MC6195
MC6196
20
20
MC14046B
16
12*
12*
16
®
MC6190 MC6192
MC6191 MC6193
MC6194
MOTOROLA
MOS
FREQUENCY SYNTHESIZER TV TUNING SYSTEM
This series of phase locked loop subsystems is constructed In
NMOS Silicon gate technology and are primarily intended for TV and
CATV tuning applications. These products make it possible to receive
all VHF and UHF TV frequencies.
(N-CHANNEL, SILICON-GATE,
DEPLETION LOAD)
FREQUENCY SYNTHESIZER
TV TUNING SYSTEM
• Single 5 V Supply
• Low External Parts Count
• Keyboard Interface Uses Low Cost 4 x 4 Keyboard
L SUFFIX
CERAMIC PACKAGE
CASE 695
• Remote Control Capability
• Manual Channel Selection
• Scan Up/Scan Down
• Auto Programming of all Active Channels
1
2S~
~UUUUU-
• Automatic Switching to AFT Mode Option
• Channel Information Output Interfaces to Leds
• On Chip Reference Oscillator Uses External Crystal
PSUFFIX
PLASTIC PACKAGE
1
CASE 710
II
NOT RECOMMENDED FOR NEW DESIGNS
PRODUCT BEING PHASED OUT
Closest equivalents are the MC6195 and MC6196
6-3
®
MC6195
MC6196
MOTOROLA
MOS
(N-CHANNEL, SILICON-GATE,
DEPLETION LOAD)
FREQUENCY SYNTHESIZER TV TUNING SYSTEM
FREQUENCY SYNTHESIZER
TV TUNING SYSTEM
These phase-locked loop devices are constructed in NMOS silicon
gate technology and are primarily intended for TV and CATV tuning applications.
•
•
•
•
Single 5 V Supply
Low External Parts Count
Remote Control Capability
Scan Up/Scan Down Channel Selection
• Automatic Switching to AFT Mode
• Channel Information Output Interfaces to LEDs
• On-Chip Reference Oscillator Uses External Crystal
1
_
i
l
:
20
P SUFFIX
1
PLASTIC PACKAGE
CASE 738
BLOCK DIAGRAM
I
Scanning
(Test)
'::.SS~_ _ _ _ _--,
Scan
Up/Down
Ch
--1-6----~
19
L..-_--r_ _...J
A
BCD
Up/Down
Counter
13
12
C
11
} BCD
M''''p''"d
Output
for Display
D
Toggle
or Remote
10
VH
9 VL
Channel ROM
VC
VHF High Band
VHF Low Band
Video COincidence
On or
Remote
Prescaled
Input
AFT
6
PD
12-Bit MaskProgrammable Reference Divider
Pin1=Vss
Pin 4= Reset
Pin 15= VDD
Externai
4 MHz
Reference
Crystal
6-4
Phase Detector
Output
MC6195, MC6196
PIN ASSIGNMENT
MAXIMUM RATINGS
Rating
Symbol
DC Supply Voltage
Input Voltage, All Inputs
Operating Temperature Range
Storage Temperature Range
Unit
Value
VDD
-0.3 to + 7
V
Yin
- 0.3 to + 7
V
VSS
fin
SS
TA
o to 70
°C
OS Cin
On-Rm
Tstg
-65 to + 160
°C
Reset
T-Rm
PD
This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Yin and Vout be constrained to the ralle)e vC,C,,,,IV'fl <)' Vout)sVDD
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
VSS or VDD)·
Ch
AFT
VDD
VC
AC
VL
VH
B
D
C
ELECTRICAL CHARACTERISTICS IT A = 25°C, Voltages Referenced to VSS)
Characteristic
Symbol
VOO
Min
Typ
Max
VDD
-
4.75
5.0
5.25
Power Supply Voltage
Output Voltage:
A, B, C, D,
Units
V
V
o Level
VOL
5
-
-
0.8
1 Level
VOH
5
2A
-
-
o Level
VIL
5
-
-
0.8
On-Rm AFT (PLL Mode)
1 Level
VIH
-
-
oLevel
VIL
5
5
2.0
Ch, T-Rm
-
-
OA
1 Level
VIH
5
4.0
-
-
5
5
5
5
5
-
-
-
-
±20
±1
300
200
±200
AFT
Input Voltage:
Reset, VC
V
Input Current·
f1.A
lin
fin,Os cin
Reset, VC
AC
AFT (PLL Model
Ch, T-Rm
VIL=OV, VIH=VDD
VIL=OV, VIH=VDD
VAC=VDD
VIL=OV
VIL=OV, VIH=4V
A,B,C,D
-
60
-
-
VIH= VDD
IIH
5
VIL=OV
IlL
5
-
-
-3
mA
Cin
5
-
5
10
pF
Cout
IOH
5
-
6
10
5
5
50
20
-
-
-
-
5
5
400
50
Input Capacitance
Output Capacitance
Output Current:
PD
A,B,C,D
-
30
VOL=OA V
VOL=12V
On-Rm, SS
VOL=OAV
IOL
5
1.6
Output Leakage Current VL, VH, On-Rm, SS
IL
5
-
Output Leakage Current PD
Breakdown Voltage VL, VH, On-Rm, SS
IL
5
VBDSO
5
IDD
Quiescent Current, All Outputs Open
-
-
pF
f1.A
VOH=12V
VOH=27V
A, B, C, D, VL, VH
PD
1.0
-
-
-
-
-
-
mA
.-
10
f1.A
-
±1
7
-
-
f1.A
V
5
-
-
60
mA
SWITCHING CHARACTERISTICS (T A = 25°C, CL = 50 pF, VDD = 5 V)
Symbol
Min
Typ
~ax
Units
Output Rise Time
tTLH
-
-
10
f1.s
Output Fall Time
tTHL
-
-
1
f1.s
Propagation Delay, AC to A, B, C, D (Outputs)
tPLH, tPHL
-
-
100
f1.s
Input Rise and Fall Times
tTLH, tTHL
-
-
100
Characteristic
Operating Frequency
fin,Os Cin
AC
f1.s
MHz
Yin = 500 mV POp
Vin=5 V POp
6-5
-
8
60
4.1
-
Hz
MC6195, MC6196
MC6190 FAMILY DEVICE CHARACTERISTICS
The relationship between T-Rm, On-Rm, and the state of
the On/Off Latch are illustrated in the flowchart in Figure 1.
The Phase-Locked Loop Frequency Synthesizers MC6190
through MC6196 are products designed for use in various
types of TV and CATV applications.
The MC6190 through MC6194 offer keyboard interface,
BCD output data for channel display, band-switching information, AFT control, On/Off control, and battery or
capacitor backup memory retention. The differences between these parts primarily have to do with the frequency
divide numbers required for selected channels.
The MC6195 and MC6196 differ from the MC6190 through
MC6194 in that they do not allow keyboard interface and do
not have backup memory retention.
Some of the characteristics and intended applications are
shown in the following table.
Device
MC6190
MC6191
MC6192
MC6193
MC6194
MC6195
MC6196
I
Ref
4
4
4
4
3
4
4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Prescaler
VHF UHF
256 256
256 256
256 256
64 256
64
256
256 256
256 256
Band
CATV
USA
Japan
CATV
CATV
CATV
USA
CHANNEL-SCAN OPERATION
UP/DOWN LATCH - The Up/Down latch stores the
channel-scan information that is received at Ch (pin 16), and
controls the direction of count of the BCD Up/Down
Counter. The operation of the channel-scan circuitry is
shown in the following table:
Lowest Highest
Channel Channel
00
99
02
83
01
62
02
59
02
60
00
59
02
83
Input Voltage Level (ChI
Low ( :s 0.4 V)
High (~4.0 V)
Channel-Scan Direction
Down
Up
High Impedance
No Scan
The input voltage level must be held for a minimum of two
clock cycles to insure the desired up or down count. At
reset, the latch is taken to the scan-up state.
BCD UP/DOWN COUNTER - The BCD Up/Down
Counter counts in the range from 00 through 99 and supplies
BCD information to the channel-display multiplexing circuitry and the channel ROM. The counter scans the channels
at a rate of either one every 30,8, or 1 clock cycle (2,7.5, or
60 channels per second for a 60 Hz Signal at AC, pin 14):
1) Invalid channels are scanned at a rate of one per
clock cycle (60 channels per second for 60 Hz at AC)
2) Valid channels are scanned at a rate of one per 30
clock cycles (2 channels per second for 60 Hz at AC)
3) If the channel-scan key is depressed (i.e., Ch, pin 16,
is taken either low or high) for more than 120 clock
cycles, the valid channels are scanned at a rate of
one per 8 clock cycles (7.5 channels per second for
60 Hz at AC).
CIRCUIT OPERATION
The MC6195 and MC6196 are phase-locked loop frequency synthesizer devices that are the nucleus of digital tuning
systems for CATV and U SA TV converters. As shown in
Figure 4 and 5, the devices interface with a linear control
chip, an ECl prescaler, LED display interfacing devices, and
a minimum of external components. The following sections
will explain the functions of the various blocks in the block
diagram.
The channel-scan function is shown in the flowchart in
Figure 2. A list of the valid channels programmed into the
MC6195 is given in Table 1; Table 2 is a list of valid channels
programmed into the MC6196.
At reset, the counter is taken to zero. If, during scanning,
the On/Off Latch is changed to the OFF state, the counter
stops but maintains its present state.
ON/OFF OPERATION
ON/OFF LATCH - The On/Off Latch stores the On/Off
information that is either directly received at T-Rm (Pin 17) or
received from a remote source at On-Rm (pin 18).
If On/Off information is to be directly received at T-Rm,
the latch operates as follows: When T-Rm is taken to VSS
(the direct-control mode) for at least two clock cycles (at AC,
pin 14), the state of the On/Off Latch changes either from
ON to OFF or from OFF to ON. In this mode of operation,
On-Rm is the three-state output of the On/Off latch, and
assumes the high-impedance state when the latch is toggled
ON or the low-voltage level (VSS) when the latch is toggled
OFF.
If On/Off information is to be received at On-Rm from a
remote source, the latch operates as follows: When T-Rm is
taken to VOO (the remote-control mode), On-Rm becomes
the input from the remote-control unit. When taken to VOD,
On-Rm sets the On/Off Latch to the ON state. When taken
to VSS, On-Rm sets the latch to the OFF state.
CLOCK - The Clock provides timing for the BCD
Up/Down Counter.
PHASE-LOCKED LOOP OPERATION
CHANNEL ROM - The Channel ROM is a 100- by 15-bit
channel-conversion ROM, which converts the BCD channel
number from the BCD Up/Down Counter into the preset
code (for the 12-bit programmable divider) corresponding to
the selected valid channel.
12-BIT PROGRAMMABLE DIVIDER - The 12-bit Programmable Divider divides the prescaled local oscillator frequency at fin (pin 201 by the programmed value supplied by
the Channel ROM. The output of the divider goes to one in-
6-6
MC6195, MC6196
FIGURE 1 -
FLOWCHART SHOWING THE RELATIONSHIP OF TMO, ONRM, AND
THE STATE OF THE ON/OFF LATCH
T------------------,
,
'H
r
·Note:
H=VDD
L=VSS
T = High-Impedance State
I
_ _ _ _ _ ..J
------------------~,,~----------------~/'~----------------------~,,~--------------------~/
Direct-Control Mode
(On-Rm is the output exhibiting the state of the On/Off Latch)
TABLE 1 -
Remote-Control Mode
(On-Rm is the input controlling the state of the On/Off Latch)
FREQUENCY ASSIGNMENTS FOR THE MC6195
Divide No.
Start
Divide No.
Delta
6
361
3
1
6
334
3
1
1
6
345.
3
1
0
Channel Nos. Osc Freq
Osc Freq
Start Stop Start (MHz) Delta (MHz)
Band
VH
VL
()()
01
722
02
04
668
1
05
06
690
07
13
788
6
394
3
1
1
14
22
734
6
367
3
1
1
23
36
830
6
415
3
1
1
37
53
914
6
457
3
0
1
54
59
686
6
343
3
0
1
TABLE 2 -
FREQUENCY ASSIGNMENTS FOR THE MC6196
Channel Nos. Osc. Freq.
Start Stop Start (MHz)
Osc. Freq.
Delta (MHz)
Divide No.
Start
Divide No.
Delta
Band
VL
VH
02
04
101
6
101
6
1
0
05
06
123
6
123
6
1
0
07
13
221
6
221
6
0
1
14
83
517
6
517
6
0
0
6-7
II
MC6195, MC6196
FIGURE 2 -
OPERATION OF THE CHANNEL-SCAN CIRCUITRY FOR AC (PIN 14)=60 Hz
I
6-8
MC6195, MC6196
put of the Phase Detector, to be compared to the reference
frequency.
The Display Multiplexer has a sinking capability of 1.6 mA
at 0.4 volts, and can interface with TTL and LSTTL logic.
REFERENCE OSCILLATOR - The Reference Oscillator
circuit consists of an inverter and resistor internal to the
device, and requires an external crystal. For critical applications, capacitors from OSCin and OSCout to ground can provide the crystal with the optimum capacitive load.
Depending upon the mask option chosen, either a 4 MHz
or a 3.57954 MHz reference crystal may be used.
START-UP AND POWER-ON RESET
When power is applied to the chip, reset is generated (See
Figure 3). The BCD Up/Down Counter is reset and begins
the channel-scan operation, stopping at the lowest valid
channel. The display is blanked. When the input at T-Rm
(pin 17) takes the On/Off Latch to either the ON state or the
remote-control state, the display is activated and the lowest
valid channel number is displayed.
12-BIT PROGRAMMABLE REFERENCE DIVIDER - The
12-Bit Programmable Reference Divider divides the
Reference Oscillator frequency by a number that has been
programmed at the mask level. The output of the Reference
Divider goes to one input of the Phase Detector, to act as the
reference frequency.
FIGURE 3 -
POWER-ON RESET EXTERNAL CIRCUIT
VOO=5 V.
PHASE DETECTOR - The Phase Detector compares the
signal from the 12-bit Programmable Divider to the signal
from the 12-Bit Programmable Reference Divider and gives
an output that is the phase difference between the two
Signals. The output of the Phase Detector goes to the AFT
Switch.
1 El
f01,'
B
p." .
AFT SWITCH OPERATION
The AFT Switch is controlled by the AFT input pin (pin 6).
When AFT is open-circuit, the device is in the AFT mode.
In this mode, PO (pin 5) becomes the output of the Phase
Detector and supplies the tuning voltage to the external
linear amplifier. Thus, the internal phase-locked loop circuitry forces the change to the desired channel. Then, when
video coincidence is detected at the VC input (pin 7),
receiver lock is indicated, and receiver control is switched to
the external receiver AFT circuits.
In a typical application, the receiver AFT circuit is built into
the system with a nominal reference voltage of 1.3 volts. The
dynamic range should be ± 1.0 volt from this nominal value
with a positive voltage (referenced to 1.3 volts) for positive
frequency error and a negative voltage for negative frequencyerror
The external AFT circuit retains control until loss of video
coincidence occurs or a channel change is begun. In the AFT
mode, the phase-locked loop regains control by an internal
pull-down circuit. Proper operation of this pull-down circuit
requires the VC input to be current-limited to 200 p.A.
When the AFT input pin is taken to VSS, the device is in
the non-AFT mode, and PO (pin 5) is switched to a highimpedance state.
Voo
Reset
tOOk
TEST MODE
If SS (pin 19) is forced high during the channel-scan
operation, Test Mode is started.
PIN DESCRIPTIONS
VSS (PIN 1)
VSS is the negative power supply pin, usually ground.
OSCout (PIN 2)
OSCout is the output of the oscillator circuit.
OSCin (PIN 3)
OSCin is the input of the oscillator circuit.
Reset (PIN 4)
DISPLAY SECTION
Reset is the input for power-on reset. It is normally tied to
VDD through a 0.1 p.f capacitor. (See Figure 3).
ZERO CROSSING DETECTOR - The Zero Crossing
Detector is a hysteresis gate with a threshold voltage of
about 1 volt. and is used to multiplex the display LEDs.
PD (PIN 5)
PD is the output of the phase detector.
DISPLAY MULTIPLEXER - The Display MUltiplexer provides the BCD data to the A, B, C, and D output pins. When
AC (pin 14) is high (VDD), the data outputs display the most
Significant digit of the channel number. When AC is low
(VSS), the data outputs display the least significant digit.
The display is blanked when the On/Off Latch is in the OFF
state.
AFT (PIN 6)
AFT is the AFT control input pin, which is either left opencircuited or tied to ground.
6-9
MC6195, MC6196
VC (PIN 7)
This is the video coincidence input from the linear
amplifier. A high logic level (VDD) supplied to this pin indicates receiver lock.
VL (PIN 8)
VL is the VHF low-band output. It is an open-drain
N-channel that can act only as a current sink. This output is
accessed by the channel ROM and is normally used for band
switching.
VH (PIN 9)
VH is the VHF high-band output. It is an open-drain
N-channel that can act only as a current sink. This output is
accessed by the channel ROM and is normally used for band
switching.
A, B, C, 0 (PINS 13, 12, 11, 10)
These inputs normally are multiplexed BCD data outputs
for channel display. They may, however, be used as inputs
for presetting channel values.
The AC and Reset inputs are used to strobe in the preset
channel data in the following manner:
1) The logical AND of AC and Reset enables the preset of
the MSD of the channel number.
2) The logical AND of AC and Reset enables the preset of
the LSD of the channel number.
I
AC (PIN 14)
AC is the ac voltage input, which provides the internal
system clock for the multiplexed data output pins and the
channel scanning operation.
An internal clamp limits the voltage swing at this input to a
value between - 0.60 and 5 volts. If the input goes below
ground, an internal diode clamps to, typically, - 0.6 volts. A
normal input to this pin is a 12 VRMS 117 V p-p sine wave),
current limited with a series resistor to 200 p.A. For the internal clamps to work properly, the input level must be current
limited.
fin (PIN 20)
fin is the input pin that receives the prescaled local
oscillator frequency. Internal circuitry provides dc bias to the
fin input so that the prescaled local oscillator frequency can
be ac coupled. If this input is to be dc coupled, standard TTL
input voltages are required for logic levels.
APPLICATIONS
A system constructed with the MC6195 PLLfrequency
synthesizer chip, a CATV up converter, and a minimum
number of external components, is shown in Figure 4; a
system using the MC6196 PLL, a linear control chip, and external components is shown in Figure 5.
MC2801 LINEAR CONTROL CHIP - This linear control
chip integrates all the control circuits and regulators required
in the system on a Single chip.
The filter amplifier provides active filtering in the PLL network. The output of this amplifier, PD, drives the tuner
varicap diodes. The non-inverting input of this amplifier,
"NI", is internally biased with the AFT reference voltage (1.3
volts) to simplify the external circuitry. This bias voltage,
however, can be externally changed with a single resistor, if
required.
A high-voltage regulator provides up to 34 volts for the
filter amplifier.
The coincidence output "CO", will go high when the
video sync/signal (in video input, "VI") and the fly back
pulse (in fly back input, "FI") are synchronized. "CO"
detects channel lock.
The band-switch circuit decodes band-select information
and provides constant-current output to an external transistor for band-switching operation. The decoding format is
shown below:
Voo (PIN 15)
VDD is the positive power supply pin, typically + 5 volts.
Toggle or Remote Input - T-Rm is a three-state input pin
that may either toggle the On/Off Latch or permit remote
operation (See Figure 1). Normally, the pin is left in the highimpedance state and there is no On/Off operation.
On-Rm (PIN 18)
On-Rm is either the three-state output from the On/Off
Latch or the input to the On/Off Latch from the remotecontrol receiver (See Figure 1),
VL Input
0
0
0
1
0
Ch (PIN 16)
Ch is the three-state input pin that determines the direction of channel scan (scan up or scan down).
T-Rm (PIN 17)
VH Input
1
Selected Band
UHF Band
VHF High Band
VHF Low Band
The low-voltage regulator section provides a regulated 5
volts to the MC6196 and the other circuits, with current
limiting capability. The output current rating is determined
by the external series pass transistor.
MC12071 PRESCALER - The ECL prescaler may be used to
count down the local oscillator frequency by 256 for UHF
and VHF, to supply an incoming frequency of less than
4.1 MHz to the PLL programmable divider.
SS (PIN 19)
SS is an open drain output that goes low during channel
scanning. It is also used as an input for the LSI Test Mode.
6-10
MC6195, MC6196
FIGURE 4 - CATV TUNING SYSTEM BLOCK DIAGRAM
MC7805CT
+5V
117 Vac
+5V
VDD
Reset
~/-II-I
A
100 k
B
C
D
~I II I
T-Rm
on/Off
l
1k
LD
m
Ss
+5V~
Channel Up
CD
:::;;
u
On-Rm
AFT
1
-1
Channel
Down ~+5V
Ch
PD
25 k
25
f -.....- -...I-J~Vac
VC
VL
VH
1------------....., LO/K
~---t
0.01
GND
~50 pF
All Diodes -
1N4001
6-11
NOTE: All capacitor values not
otherwise labeled are in "F
II
II
i:
FIGURE 5 -
o
USA TV TUNING SYSTEM BLOCK DIAGRAM
(7)
~
CD
9'
3:
o
Horizontal
Time Base
(7)
~
CD
(7)
:5a.
:5
:5
a.
:5
0
0
u
~
....J
....J
Cij
Fly Back
Aux Supply
0
0
r---------·I
II
q>
~
I\)
I
I
I
I
I
I
I
I
L------l
I
0)
Qj
0>
~Cij
~
t--u
0(1)0.
('>10).~~..::
uc...u
~....J
(5
>
Am'
Ol
C
w
C
~
Out
I-
D
AC
I
I
~
'"
NI
'
I
I
I
On-Rm
AFT
+
I
I
I
I
I
B
'c
U
Relay
VHI
VL-VCC2
-=
Chl-----o...
VEE
~VDD
o
I
I
I
Down
I
I
I
I
I
I --
I
I
i
1.
,
I
~
L------------O
I
I
I _______________ _
L
I
...L
I~_-O
w
Scanning
I
I
_________________________ JI
Tuning Voltage
Supply
-=
®
MC140468
MOTOROLA
PHASE LOCKED LOOP
The MC14046B phase locked loop contains two phase comparators, a voltage-controlled oscillator (VCO), source follower, and
zener diode. The comparators have two common signal inputs,
PCAin and PCBin. Input PCAin can be used directly coupled to large
voltage signals, or indirectly coupled (with a series capacitor) to
small voltage signals. The self-bias circuit adjusts small voltage signals
in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1 0u t, and maintains
90 0 phase shift at the center frequency between PCAin and PCBin
signals (both at 50% duty cycle). Phase comparator 2 (with leading
edge sensing logic) provides digital error signals, PC2 0ut and LD,
and maintains a 0 0 phase shift between PCAin and PCBin signals
(duty cycle is immaterial). The linear VCO produces an output signal
VCOout whose frequency is determined by the voltage of input
VCOin and the capacitor and resistors connected to pins C1A, C1B,
R 1, and R 2. The source-follower output SF out with an external resistor is used where the VCOin signal is needed but no loading can be
tolerated. The inhibit input Inh, when high, disables the VCO and
source follower to minimize standby power consumption. The zener
diode can be used to assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning, voltage-tofrequency conversion and motor speed control.
= 1.4 MHz Typical
•
VCO Frequency
•
VCO Frequency Drift with Temperature
@ VDD = 10 V
•
= 1% Typical
Quiescent Current = 5.0 nA/package
•
@
VDD
= 10 V
CMOS MS.
(LOW-POWER COMPLEMENTARY MOS)
PHASE LOCKED
LOOP
(fIIIII/IIIftJfIIJIIIlI
lJIIf)J~11U ~ u JynYl~ ~ ~
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
PLASTIC PACKAGE
CASE 620
CASE 648
ORDERING INFORMATION
= 0.04%loC
Typical
Me'4XXXO
JtSUfflX
VCO Linearity
L
typical
@
5V
fO = 10 kHz,
•
Low Dynamic Power Dissipation - 70 J.1W Typical
VDD = 5.0 V, R1 = 1.0 MD, R2 = 00, RSF = 00
•
Buffered Outputs Compatible with MHTL and Low-Power TTL
@
Diode Protection on All Inputs
•
Supply Voltage Range
•
Pin-for-Pin Replacement for CD4046B
•
Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle
Limited
•
Phase Comparator 2 switches on Rising Edges and is not Duty
Cycle Limited
='
PIN ASSIGNMENT
LD
2
PCAin 14
V DD
VSS
= Pin
= Pin
Limited Operating
Temperature Range
PCl out
VeOin
PlastiC Package
Extended Operating
Temperature Range
3.0 to 18 V
BLOCK DIAGRAM
PCSin
P
A
C
•
Denote.
Ceramic Package
3
9
16
8
PC1 0ut
PCBin
13 PC2 0ut
VCO out
1
LD
4
VCO out
6-13
PCAin
PC2 0u t
Inh
R2
C1A
Rl
11 R1
12 R2
C1B
SFout
6
7
VSS
VCOin
C1A
C1S
10 SF out
Inh
VDD
Zener
MC14046B
MAXIMUM RATINGS
(Voltages referenced to Vss)
Rating
DC Supply Voltage
Input Voltage. All Inputs
Value
VDD
-0.5 to +18
Vdc
Vin
-0.5 to VDD + 0.5
Vdc
Unit
OC Input Current. per Pin
lin
±10
mAdc
Operating Temperature Range - AL Device
CLlCP Device
TA
-55 to +125
-40 to +85
°c
Storage Temperature Range
T stg
-65 to +150
°c
ELECTRICAL CHARACTERISTICS
Characteristic
Tlow
Vee
Vdc
"0" Level
VOL
5.0
10
15
"I" Level
VOH
5.0
10
15
"0" Level
VIL
Vin - 0 or VDO
Input Voltage"
(VO 04.5 or 0.5 V)
(VO 09.0 Or 1.0 V)
(VO = 13.5 or 1.5 V)
Min
(VOL = 0.4 V)
(VOL = 0.5 VI
(VOL = 1.5 VI
Min
0.05
0.05
0.05
4.95
9.95
14.95
4.95
9.95
14.95
TVp
Max
Thigh·
Min
Max
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
5.0
10
15
4.95
9.95
14.95
Unit
V
V
V
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
VIH
(VO = 0.5 Or 4.5 V)
(VO" 1.0 Or 9.0 V)
(VO = 1.5 or 13.5 V)
Output Drive Current (AL Device)
Source
(VOH = 2.5 V)
(VOH = 4.6 VI
(VOH = 9.5 V)
(VOH = 13.5 vI
2SoC
Max
5.0
10
15
"I" Level
.
(Voltages Referenced to VSS)
Symbol
Output Voltage
VincVDDorO
rI
Symbol
5.0
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
'i.50
8.25
3.5
7.0
11.0
5.0
5.0
10
15
-1.2
-0.25
-0.62
-1.8
-1.0
-0.2
-0.5
-1.5
-1.7
-0.36
-0.9
-3.5
-0.7
-0.14
-0.35
-1.1
5.0.
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
5.0
5.0
10
15
-1.0
-0.2
-0.5
-1.4
-0.8
-0.16
-0.4
-1.2
-1.7
-0.36
-0.9
-3.5
-0.6
-0.12
-0.3
-1.0
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
IOH
mA
Sink
IOL
Output Drive Current (CLlCP Device)
Source
(VOH = 2.5 VI
(VOH = 4.6 VI
(VOH = 9.5 V)
(VOH = 13.5 V)
IOH
Sink
IOL
5.0
10
15
Input Current (AL Device)
lin
15
±0.1
±O.OOOOI
±0.1
± 1.0
}lA
Input Current (CLlCP Device)
lin
15
± 0.3
±O.OOOOI
±0.3
± 1.0
IJA
5.0
7.5
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
mA
mA
pF
I nput Capacitance
Cin
Quiescent Current (AL Device)
(Per Package) Inh = PCAin = VDD,
Zener = VCOin = 0 V. PCBin = VDD
or 0 V, lout = O}lA
Quiescent Current (CLlCP Device)
(Per Package) Inh = PCAin = VDD,
Zener = VCOin = 0 V, PCBin = VDO
or 0 V, lout = 0 IJA
100
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
}lA
IDD
5.0
10
15
20
40
80
0.010
0.020
0.040
20
40
80
150
300
600
IJA
IT
5.0
10
15
TOlal Supply Current t
Onh = "0", fo = 10 kHz, CL = 50 pF,
Rl = 1 MO, R2 = QQ, RSF = QQ, and
50% Duty Cycle)
IT = (1.46 IJA/kHz) f + IDD
IT = (2.91 }lA/kHz) f + 100
IT = (4.37 IJA/kHz) f + 100
*Tlow = -55 0 C for AL DevIce, -40 0 C for CLlCP Device.
Thigh = +125 0 C for AL Device, +85 0 C for CLlCP Device.
""Noise immunity specified for worst·case input combination.
Noise Margin for both "I" and "0" level = 1.0 Vdc min @ VDO = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
tTo Calculate Total Current in Genaral:
IT"'2.2xVDD
1 x 10-1 VD02
(VCOin-l.65+ VDD-l. 35
Rl
R2
t/
4
COo.% Duty100
Cycle of PeAin) +
10
(VCO. -1.65)3/4
on
+ 1 x 10- 3 (CL +9) VDO f+
RSF
where: IT in IJ.A, CL in pF, VCOin, VDD in Vdc, f in KHz, and
+ 1.6 x
RI, R2, RSF in MO, CL on vCO out '
6-14
IJA
MC14046B
ELECTRICAL CHARACTERISTICS*
(CL = 50 pF, T A = 25°C)
Maximum
Minimum
Characteristic
Symbol
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5ns/pF) CL + 15ns
tTLH = (1.1 ns/pF) CL + 10ns
tTLH
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns!pF) Cl + 9.5 ns
tTHL
VDD
Vdc
AL
Device
CL/CP
Device
Typical
All Types
AL
Device
CLlCP
Device
5.0
10
15
-
-
350
150
110
400
200
160
200
100
80
Units
ns
-
-
-
-
180
90
65
5.0
10
15
-
-
100
50
37
175
75
55
5.0
10
15
1.0
0.2
0.1
1.0
0.2
0.1
2.0
0.4
0.2
-
-
Rin
15
150
15
1500
-
-
Vin
5.0
10
15
-
-
200
400
700
ns
PHASE COMPARATORS 1 and 2
I nput Resistance - PCAin
Rin
- PCB in
, Minimum Input Sensitivity
AC Coupled - PCAin
C series = 1000 pF, f = 50 kHz
DC Coupled - PCAin, PCBin
-
5 to 15
f max
5.0
10
15
-
-
300
600
1050
-
400
800
1400
MU
MU
mV p.p
See Noise Immunity
VOL TAGE CONTROLLED OSCILLATOR (VCOI
Maximum Frequency
IVCOin = VDD, Cl = 50 pF,
Rl=5kn,andR2:~)
0.50
1.0
1.4
5.0
10
15
Temperature - Frequency Stability
(R2 =~)
linearity (R2 = ~)
(VCOin = 2.50 V ± 0.30 V, Rl > 10 kn)
(VCOin = 5.00 V ± 2.50 V, R1 ;;, 400 kn)
(VCOin = 7.50 V ± 5.00 V, Rl ;:, 1000 kH)
0.70
1.4
1.9
MHz
%/oC
0
0.12
0.04
0.015
10
%
Output Duty Cycle
Input Resistance - VCOin
0.35
0.7
1.0
Rin
5.0
10
15
1
5 to 15
50
%
1500
Mn
15
150
50
SOURCE·FOLLOWER
Offset Voltage
(VCOin minus SF out , RSF
> 500 knl
linearity
(VCOin = 2.50 V ± 0.30 V, RSF
(VCOin = 5.00 V ± 2.50 V, RSF
(VCOin = 7.50 V ± 5.00 V, RSF
5.0
10
15
1.65
1.65
1.65
5.0
10
15
0.1
0.6
0.8
2.5
2.5
2.5
V
%
> 50 knl
> 50 kn)
> 50 kH)
ZENER DIODE
Zener Voltage liz
2.2
2.2
2.2
= 50!,A)
= 1 mAl
Dynamic Resistance (I z
'The formula given is for the typical characteristics only.
6-15
II
MC14046B
FIGURE 1 - PHASE COMPARATORS STATE OIAGRAMS
PHASE COMPARATOR 1
Input State
I
~
Q
PCA i
nt-->\.
11
PCB in
10
I
I
o
PC1 0ut
PHASE COMPARATOR 2
Input State
3·St8te
Output Disconnected
o
PC2 0ut
lD
(lock Detect)
o
o
Refer to Waveforms in Figure 3.
I
FIGURE 2 - DESIGN INFORMATION
Clwrect.-istic
Using Phase Comperetor 1
No signal on input PCAin.
VCO in PlL system adjusts to center frequency
(fO>-
Phase angle between PCAin and PCB in.
900 at center frequency (fol. approaching 0 0
and 1800 at ends of lock range (2fL),
Always 0 0 in lock (positive rising edges),
Ves
No
High
Low
Locks on harmonics of center frequency.
Signal input noise rejection.
Using Phase Comperetor 2
VCO in PLL system adjusts to minimum fre·
quency (fmin)'
Lock frequency range (2fL>-
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock. 2fL; full VCO frequency range; f max - fmin.
Capture frequency range I2fCl.
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
Oepend's on low·pass filter characteristics
(see Figure 3). fe" fL
Center frequency (fO),
fC; fL
The frequency of VCO out • when VCOin ; 112 VOO
veo output frequency (f)'
Note: These equations ~re intended
to be a design guide. Since calculated
component values may be in error
by 81 much 81 a factor of 4, labor·
atory experimentation may be reo
quired for fixed designs. Part to part
frequency variation with identical
passive components is less then
t20%.
fmin
1
(Veo input; VSS)
;
R2(C1+ 32 pF)
f max
1
;
Rl(Cl +32pF) +
fmin
Where: 10K" Rl" 1M
10K" R2" 1M
l00pF "Cl " .01 "F
6-16
(Veo input; VOO)
MC14046B
FIGURE 3 - GENERAL PHASE-LOCKED LOOP CONNECTIONS AND WAVEFORMS
VCOin
PCA in
@
VCO out
4
Frequency f'
@ Frequency Nf' =
f
l"Ex7er-;;-a,1
-o-N
L_C~~~.J
Typical Low-Pass Filters
Typically:
(a)
(b)
R3
Input ~ Output
R3
Input~Output
C2~ 2fc",,~j21TfL
-
1T
1~~
R3 C2
(R3
N
2 1'l':,f
+ 3,OOOn) C 2 = 100Nl1f - R4 C2
2
fmax
~C2
Note:
6N
f max
flf
= f max
- fmin
Sometimes R3 is split into two series resistors each R3 -0- 2_ A capacitor Cc is then placed from the midpoint to ground_ The value for
Cc should be such that the corner frequency of this network does not significantly affect wn_ In Figure B, the ratio of R3 to R4 sets
the damping, R4 '" (0.1 )(R3) for optimum results.
LOW-PASS FILTER
Oefinitions:
N = Total division ratio in feedback loop
K = VOO/7T for Phase Comparator 1
K = VOO/4 7T for Phase Comparator 2
K
W
n
_ 2 7T I':. fVCO
VCO - VOD-2 V
2 7T fr
for a typical design wn '" 10 (at phase detector input)
~
Filter B
Filter A
'" 0.707
~
=
=~KKVCO
NR3C2
NWn
2K,pKVCO
F(s)= _ _
1_
R3 C2 S+ 1
i
KKVCO
<'un = NC2(R3+R41
N
l' = 0.5 wn(R3 C 2 + KcpKVCO)
F(s)
=
R3 C 2S+ 1
S(R3C2+R4 C2)+1
Waveforms
Phase Comparator 2
Phase Comparator 1
peAin
~
VDD
PCAin
Vss
PCBin
~
I
,
I
I
I
: ,
---i i
LD
U
I :
PC2 0llt
'
~
~
VDD
vss
VOH
I
, :
VOL
I
VOH
U'
ll~ ____
:
VOL
VOH
U----VOL
-VOH
VCOin
~"'---------""'----
-VOL
Note: for further information, see:
(1) F. Gardner, "Phase-Lock Techniques", John Wiley and Son, New York, 1966,
(2) G, S, Moschytz, "Miniature RC Filters Using Phase-Locked Loop", BSTJ, May, 1965.
(3) Garth Nash, "Phase-Lock Loop Oesign Fundamentals", AN-535, Motorola Inc.
6-17
II
®
MC145688
MOTOROLA
CMOS MSI
PHASE COMPARATOR AND
PROGRAMMABLE COUNTERS
(LOW·POWER COMPLEMENTARY MOS)
The MC14568B consists of a phase comparator, a divide-by-4, 16, 64
or 100 counter and a programmable divide-by-N 4-bit binary counter lal/
positive-edge triggered) constructed with MaS P-channel and
N-channel enhancement mode devices (complementary MaS) in a
monolithic structure.
The MC14568B has been designed for use in conjunction with a programmable divide-by-N counter for frequency synthesizers and phaselocked loop applications requiring low power dissipation and/ or high
noise immunity.
This device can be used with both counters cascaded and the output
of the second counter connected to the phase comparator (CTL high),
or used independently of the programmable divide-by-N counter, for
example cascaded with a MC14569B, MC145228 or MC145268 (CTL
low).
PHASE COMPARATOR
AND PROGRAMMABLE
COUNTERS
~ffIIIIIIIII
lJI~~~~~ ~ U 16rW1\YY~ ~ ~
• Quiescent Current = 5.0 nA typ/pkg @ 5 V
• Supply Voltage Range = 3.0 to 18 V
• Capable of Driving Two Low-Power TTL Loads, One Low-Power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range.
• Chip Complexity: 549 FETs or 137 Equivalent Gates
I
MAXIMUM RATINGS
l SUFFIX
CERAMIC PACKAGE
P SUFFIX
PLASTIC PACKAGE
CASE 620
CASE 648
ORDERING INFORMATION
MC,.Xxx. 11SUffiX
(Voltages referenced to VSSI
Rating
Symbol
Value
Unit
VDD
-0.5to+18
V
Input Voltage, All Inputs
Vin
-0.5 to VDD + 0.5
V
DC Input Current, per Pin
lin
±1O
mA
TA
-55 to +125
-40 to +85
°c
T stg
-65 to +150
°c
DC Supply Voltage
Operating Temperature Range - A L Device
CLlCP Device
Storage Temperature Range
TRUTH TABLE
F
Pin 10
G
Pin 11
o
o
BLOCK DIAGRAM
r----------,
Denotes
L Ceramic Package
P PlastiC Package
A Extended Operating
Temperature Range
C L,mited Operating
Temperature Range
Division Ratio
of Counter D1
o
4
a
16
64
100
I
I
PCin 1 4 o - - t - - - t
! - - - - - - t - _ U I 3 PC o ,,!
The divide-by-zero state on the programmable
divide-by·N 4·bit binary counter, 02, is illegal.
!-----+-~,,12LD
'------"
CTL lOW
CTL HIGH
PC out
PCin
PCi~
Cl
p.c.
CTL 15O--~+-"'"
L _ _ _ _..J---I~--Ul 0 f
LD
Cl
"0"
PE
3
o--"-....- H
01
2 (}---t-----I
"O"~
~-Ql~2
VDD
VSS
Pin 16
P,n 8
6-18
MC145688
ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vss)
Characteristic
au tpu t Vol tage
Yin
VOO or 0
Y,n
o or
Symbol
"0" level
Val
5.0
10
15
"1" level
VaH
5.0
10
15
VDO
"0" level
Input Voltage#r
(Va 4.5 or 0.5 Vdc)
(VO 9.0 or 1.0 Vdc)
13.5 Or 1.5 Vdc)
(Va
~
~
0.4 Vdcl
0.5 Vdc)
1.5 Vdc)
Sink
Output Drive Current (CLlCP Device)
Source
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdcl
(VOH = 13.5.Vdcl
IVOl ~ 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL" 1.5 Vdc)
Sink
25°C
Min
0.05
0.05
0.05
4.95
9.95
14.95
4.95
9.95
14.95
Thigh'
Typ
Max
0
0
0.05
0.05
0.05
Min
5.0
10
15
Max
Unit
0.05
0.05
0.05
Vdc
4.95
9.95
14.95
Vdc
Vdc
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
5.0
5.0
10
15
-1.2
-0.25
-0.62
-1.8
-1.0
-0.2
-0.5
-1.5
-1.7
-0.36
-0.9
-3.5
-0.7
-0.14
-0.35
-1.1
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
5.0
5.0
10
15
-1.0
-0.2
-0.5
-1.4
-0.8
-0.16
-0.4
-1.7
-0.36
-0.9
-3.5
-0.6
-0.12
-0.3
-1.0
5.0
10
15
0.52
1.3
3.6
0.44
0.88
2.25
8.8
0.36
0.9
2.4
Vdc
mAdc
IOH
0
0
Max
VIH
1.5 or 13.5 Vdc)
Output Drive Current (A l Device)
Source
(VOH 2.5 Vdc)
(VOH 4.6 Vdcl
(VOH ~ 9.5 Vdc)
(VOH
13.5 Vdcl
(VOL
(VOL
(Val
.
Vil
0.5 or 4.5 Vdc)
1.0 or 9.0 Vdc)
0
Tlow
Min
5.0
10
15
"1" level
(Va
(Va
(VO
VDD
Vdc
IOl
mAdc
mAdc
IOH
IOl
-1.2
1.1
3.0
mAdc
Input Current IAl Device)
lin
15
±0.1
± 0.00001
± 0.1
± 1.0
).IAdc
Input Current (CLlCP Device)
lin
15
± 0.3
±0.00001
±0.3
± 1.0
).IAdc
5.0
7.5
IDO
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
!lAdc
IDO
5.0
10
15
20
40
80
0.005
0.010
0.015
20
40
80
150
300
600
).IAdc
Total Supply Current' '·t
IOynamic plus Quiescent,
Per Package)
ICl 50 pF on all outputs, all
buffers sWitching)
IT
5.0
10
Three-State Leakage Current, Pins 1,13
(AL Device)
ITL
15
±0,1
±0,00001
±0,1
±3,0
).IAdc
Three-State Leakage Current, Pins 1 , 13
(CL/CP Devices)
ITL
15
± 1.0
±O,OOOOl
± 1,0
±7.5
"Adc
I npu t Capacitance
Quiescent Current (AL Device)
Cin
IPer Package) Yin = 0 or VDD,
lout=O p.A
Quiescent Current ICLlCP Device)
!Per Package) Yin = 0 or VDD,
10ut=0 p.A
).IAdc
IT = (0.2 ).lA/kHz) f + IDO
IT = (004 "A/kHz) f + IDD
IT = (0,9 "A/kHz) f + IDD
15
'Tlow -55°C for Al Device, -40°C for CLlCP Device.
Thigh = +125 0 C for Al Device, +85 0 C for CLlCP Device.
"NOise Immunity specified for worst-case input combination
NOise Margin for both" 1" and "0" level - 1.0 Vdc min @ VOO
PIN ASSIGNMENT
o 5.0 Vdc
2.0 Vdc min @ VOO - 10 Vdc
2.5 Vdc min @ VOO
15 Vdc
tTo calculate total supply current at loads other than 50 pF
3
ITICl)
ITI50 pF) + 1 x 10- ICl -50) VODf
where: IT IS in I1A (per package), Cl in pF, VDO in Vdc, and f in kHz is input frequency.
"The formulas given are for the typical characteristics only at 25°C
t Pin
pF
15 is connected to VSS or VDD for input voltage test.
Ql/C2
VDD
PE
CTL
"0"
PCin
PC out
Dp2
LD
Dpl
G
DpO
VSS
6-19
C1
II
MC14568B
SWITCHING CHARACTERISTICS (CL = 50 pF, T A = 25°C)
Characteristic
Symbol
Output Rise Time
tTLH
Output Fall Time
tTHL
VOO
V
Min
Typ
Max
Unit
5.0
10
15
-
180
90
65
360
180
130
ns
5.0
10
15
-
100
50
40
200
100
80
ns
-
125
60
45
250
120
90
ns
-
-
/is
-
-
-
-
-
-
Minimum Pulse Width, Cl, 01/C2, or PCin Input
tWH
5.0
10
15
-
Maximum Clock Rise and Fall Time,
Cl, 01/C2, or PCin Input
tTLH,
tTHL
5.0
10
15
15
15
15
PHASE COMPARATOR
Input Resistance
Input Sensitivity, de Coupled
Turn-Off Delay Time,
PC out and LD Outputs
Turn-On Delay Time,
PC out and LD Outputs
Rin
5.0 to 15
-
5.0 to 15
tpHL
5.0
10
15
tpHL
-
106
-
Mf!
See Input Voltage
-
-
550
195
120
1100
390
240
ns
1350
600
380
ns
5.0
10
15
-
675
300
190
5.0
10
15
3.0
8.0
10
6.0
16
22
-
5.0
10
15
1.0
3.0
5.0
2.5
6.3
9.7
-
5.0
10
15
-
450
190
130
900
380
260
5.0
10
15
-
720
300
200
1440
600
400
0IVIOE-8Y-4 16 64 OR 100 COUNTER (01)
Maximum Clock Pulse Frequency
Division Ratio=4, 64 or 100
MHz
lei
Division Ratio= 16
Propagation Delay Time, 01/C2 Output
Division Ratio=4, 64 or 100
tpLH,
tpHL
Division Ratio= 16
-
-
ns
-
-
PROGRAMMABLE OIVIDE-BY-N 4-BIT COUNTER (02)
Maximum Clock Pulse Frequency
(Figure 3al
lei
Turn-On Delay Time, "0" Output
(Figure 3a)
tpLH
Turn-Off Delay Time, "0" Output
(Figure 3al
tpHL
Minimum Preset Enable Pulse Width
tWH(PE)
6-20
5.0
10
15
1.2
3.0
4.0
5.0
10
15
-
5.0
10
15
-
5.0
10
15
-
-
-
-
1.8
8.5
12
-
MHz
450
190
130
900
380
260
ns
225
85
60
450
170
150
ns
75
40
30
250
100
75
ns
-
MC14568B
SWITCHING TIME TEST CIRCUITS AND WAVEFORMS
FIGURE 1 - PHASE COMPARATOR
~
2
A lags B, PC out IS
lOW.
A leads S, PC out is high.
"O"ou, REF
@
PCin
PGl
LD
PC out
FIGURE 2 - COUNTER 01
20~S_20n~tW(C')
Cl
10%
50"lro
f
L
50%
_ _..:.1.:;.00/,;::';0-:-
tTLH
tTHL
FIGURE 3 - COUNTER 02
a.
b.
"0" _ _ _ _ _ _ _ _ _ _ _ _- '
ON is the value programmed on the Op Inputs.
6-21
max
tpHL
I.
QlIC2
f
In
II
MC14568B
LOGIC DIAGRAM
PCin
14~--~A~------~~--r--r========~
r~t----~
out
-o13PC
B(Ae!.)
C1
II
G
9
11
~------------------~OLD
Counter 01
0---+------'
0---+------------+--.....
~----_----<...
f--.......-+----Det ou t[7
12hp5
LD [ 8
11 ~ P6
P8 [ ...9_ _ _1O~ P7
PO
P1
P2
P3
P4
P5
P6
P7
P8
VOO
VSS
Pin 1
Pin 18
6-29
MC145106
MAXIMUM RATINGS (Voltages referenced to VSSI
Symbol
Value
Rating
DC Supply Voltage
-0.5 to + 12
VDD
Input Voltage, All Inputs
-0.5 to Vnn +0.5
Yin
DC Input Current, per Pin
I
±1O
Operating Temperature Range
-40 to +85
TA
Storage Temperature Range
Tstg
-65to+150
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation it is
recommended that Yin and V out be constrained to the range VSS s (Vin or Vout)
s VDD
Unit
V
V
mA
°C
°C
ELECTRICAL CHARACTERISTICS
IT A = 25°C Unless Otherwise Stated, Voltages Referenced to VSS)
Characteristic
Power Supply Voltage Range
Supply Current
Input Voltage
"0" Level
"1" I_evel
Input Current
IFS, PUll-Up Resistor Source Current)
"0" Level
VOO
Vdc
Min
Typ
Max
VDD
-
4.5
-
12
V
IDD
5.0
10
12
-
6
20
28
10
35
50
mA
VIL
5.0
10
12
-
-
V
-
-
1.5
3.0
3.6
5.0
10
12.
3.5
7.0
8.4
-
5.0
10
12
5.0
10
12
-5.0
-15
-20
-20
-60
-80
-
-
VIH
lin
IPO to P8)
IFS)
II
All Types
Symbol
"1" Level
IPO to P8, Pull-down Resistor Sink Current!
5.0
10
12
5.0
10
12
-
-
-
-
-
-
-
-
-
-
-
7.5
22.5
30
30
90
120
-
-50
-150
-200
-0.3
-0.3
-0.3
,
"0" Level
5.0
10
12
-2.0
-6.0
-9.0
-6.0
-25
-37
-15
-62
-92
IOSCin,fin)
"1" Level
5.0
10
12
2.0
6.0
9.0
6.0
25
37
15
62
92
5.0
10
12
-0.7
-1.1
-1.5
-1.4
-2.2
-3.0
-
5.0
10
12
0.9
1.4
2.0
1.8
2.8
4.0
-
1.0
1.5
0.2
0.3
-
5.0
10
12
-
1.0
0.5
-
-
-
-
-
6.0
5.0
10
12
-
mA
IOH
Source
IVO=0.5VI
IVO=0.5 VI
IVO=0.5 V)
Sink
Input Amplitude
(fin @ 4.0 MHz)
(Oscin @1O.24 MHz)
IOL
-
-
-
Input Resistance
IOSCin,fin)
Cin
Three State Leakage Current
I Detout)
IOZ
Vp-p
Sine
MO
Pin
Input Capacitance
IOsCin, fin)
p.A
0.3
0.3
0.3
75
225
300
IOSCin,fin)
Output Drive Current
VO=4.5V)
IVO=9.5 V)
IVO= 11.5 V)
Unit
-
pF
p.A
-
-
1.0
1.0
1.0
Input Frequency
I-40°C to +85°C)
fin
4.5
12
0
0
-
4.0
4.0
MHz
Oscillator Frequency
I-40°C to +85°C)
OS c in
4.5
12
0.1
-
10.24
10.24
MHz
0.1
6-30
-
-
-
MC145106
TYPICAL CHARACTERISTICS
FIGURE 2 - MAXIMUM OSCILLATOR INPUT
FREQUENCY versus SUPPL Y VOLTAGE
FIGURE 1 - MAXIMUM DIVIDER INPUT
FREQUENCY versus SUPPL Y VOLTAGE
25
25
->-
20
20
2:
0..
0
+25 C
::>
'"c:c
15
~
>
;:::
~
10
ig
/ /J
~
/~ "/
g 5.0
o
30
20
fin, MAXIMUM FREQUENCY (MHz)
10
I
I
/.11
40
o
50
-:,...-""
o
20
10
I
I
+85 0 C
10
> 5.0
","~f-"""
>
+25 0 C
15
>
jl/-400C
+85 0 C
o
'"
I I iI
-"
/-40 0 C
I
V
30
40
OSCin, MAXIMUM FREOUENCY (MHz)
TRUTH TABLE
Selection
PB
P7
P6
P5
P4
P3
P2
P1
PO
Divide By N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
2 (Note 1)
3 (Note 1)
2
3
4
0
1
1
1
1
1
1
1
1
255
1
1
1
1
1
1
1
1
1
511
1: Voltage level
0: Voltage level
Note 1:
= VDD
= 0 or open circuit
PIN DESCRIPTIONS
PO - PB - Programmable divider inputs (binary)
fin - Frequency input to programmable divider (derived
from VeO)
OScin - Oscillator/amplifier input terminal
OSCout - Oscillator/amplifier output terminal
LD - Lock detector, high when loop is locked,
pulses low when out of lock.
Detout - Signal for control of external veo, output high
when fin/N is less than the reference frequency; output
low when fin/N is greater than the reference frequency.
Reference frequency is the divided down oscillatorinput frequency tYpically 5.0 or 10 kHz.
FS - Reference Oscillator Frequency Division Select. When
using 10.24 MHz Osc frequency, this control selects
10kHz, a "0" selects 5.0 kHz.
720ut - Reference Osc frequency divided by 2 output; when
using 10.24 MHz Osc frequency, this output is 5.12
MHz for frequency tripling applications.
VOD - Positive power supply
VSS - Ground
input
The binary setting of 00000000 and 00000001 on
PB to PO results in a 2 and 3 division which is not
in the 2N_1 sequence. When pin is not connected
the logic signal on that pin can be treated as a "0".
6-31
50
MC145106
PLL SYNTHESIZER APPLICATIONS
The MC145106 is well suited for applications in CB radios
because of the channelized frequency requirements. A
typical 40 channel CB transceiver synthesizer, using a single
crystal reference, is shown in Figure 3 for receiver IF values
of 10.695 MHz and 455 kHz.
In addition to applications in CB radios, the MC145106 can
be used as a synthesizer for several other systems. Various
frequency spectrums can be achieved through the use of
proper offset, prescaling and loop programming techniques.
In general, 300-400 channels can be synthesized using a
single loop, with many additional channels available when
multiple loop appro,aches are employed. Figures 4 and 5 are
examples of some possibilities.
In the aircraft synthesizer of Figure 5, the VHF loop (top)
will provide a 50 kHz, 360 channel system with 10.7 MHz
R/T offset when only the 11.0500 MHz (transmit) and
12.1200 MHz (receive) frequencies are provided to mixer #1.
FIGURE 3 -
When these signals are provided with crystal oscillators, the
result is a three crystal, 360 channel, 50 kHz step synthesizer.
When using the offset loop (bottom) in Figure 5 to provide
the indicated injection frequencies for mixer #1 (two for
transmit and two for receive) 360 additional channels are
possible. This results in a 720 channel, 25 kHz step synthesizer which requires only two crystals and provides RIT
offset capability. The receive offset value is determined by
the 11.31 MHz crystal frequency and is 10.7 MHz for the
example.
The VH F marine synthesizer in Figure 4 depicts a Single
loop approach for FM transeivers. The VCO operates on frequency during transmit and is offset downward during
receive. The offset corresponds to the receiver IF (10.7 MHz)
for channels having identical receive/transmit frequencies
(simplex), and is (10.7 - 4.6= 6.1) MHz for duplex channels.
Carrier modulation is introduced in the loop during transmit.
SINGLE CRYSTAL CB SYNTHESIZER FEATURING ON-FREQUENCY VCO DURING TRANSMIT
.---+__
I
LD
MC145106
26.965- 27.405
MHz (transmit)
26.510 - 26.950
MHz (receive)
Programmable Divider
VDD
Gnd
Switch
Wafers
RIT
Mixer
Buffer
L--_ _ _ _ _--,
1.365-1.805 MHz (transmit)
0.91 - 1.35 MHz (receive)
10.24 MHz
16.270-16.710
MHz
to Receiver
Receiver 1st
2nd Mixer Local Osc Signal
6-32
MC145106
FIGURE 4 -
Gnd
VHF MARINE TRANSCEIVER SYNTHESIZER
Lock Detect
o
Loop
Filter
Transmit Range
156.025 - 157.425 MHz
* 157.4
VCO and
Buffer
Receiver L.O. Range
145.575 - 152.575 MHz
* 151.3
Transmit
Modulation
Circuit
.l
D
NOTES:
• Receiver IF= 10.7 MHz
• Low Side Injection
• Duplex Offset = 4.6 MHz
• Step Size=25 kHz
• Frequencies in MHz unless
noted
• Values in Parentheses are
for a 5.0 kHz Reference
Frequency
• Example Frequencies for
Channel 28 Shown by *
#Can be eliminated by adding
184 to -+- N for Duplex
Channels.
6-33
Duplex
14.75#
(29.501
MC145106
FIGURE
5 - VHF AIRCRAFT 720 CHANNEL TWO CRYSTAL FREQUENCY SYNTHESIZER
TRANSMIT
118.000 - 135.975 MHz
125 kHz Steps)
RECEIVE
128.700-146.675 MHz
VHF Loop
Programming
750 kHz - 2545 kHz
N=150-509
I
TRANSMIT
11.0500 MHz
11.0525 MHz
RECEIVE
12.1200 MHz
12.1225 MHz
I
TRANSMIT
10.24 MHz
RECEIVE
11.31 MHz
(Select Frequency to Give
Desired RIT Offset)
Programming
810 kHz - 812.5 kHz
N= 324-325
6-34
®
MC145143
MOTOROLA
PLL FREQUENCY SYNTHESIZER
The MC145143 is a phase locked loop building block variation of the
MC145106/MC145112 family. The device contains the oscillator
circuitry required to operate with fundamental mode crystals to
10.24 MHz. The oscillator circuitry is connected to the phase detector
through a divide-by-16 and a 29_1 divide-by-N counter. The reference
oscillator can be divided in steps of 16 between 32 and 8176 before
interfacing with the phase detector. The external input to the phase
detector requires a VSS to VDD signal and forces the phase-detector
output high if higher in frequency than the output of the divide-by-N
counter. An out-of-Iock signal is provided from the on-chip lock
detector with a "0" level for an out-of-Iock condition.
•
Operation to 25 MHz
•
•
4.5 to 12 V Operation
Programmable Reference Divisions from 32 to 8176 (16 x 2 to
16x511)
•
Three-State Phase Detection
•
On-Chip Lock Detection
CMOS MS.
(LOW-POWER COMPLEMENTARY MOS)
PLL
FREQUENCY SYNTHESIZER
P SUFFIX
PLAsm: PACKAGE
CASE 648
PIN ASSIGNMENT
vss
NOT RECOMMENDED FOR NEW DESIGNS
PRODUCT BEING PHASED OUT
16
PO
15
P1
14
13
12
11
10
9
Closest equivalent is the MC145106
This device contains Circuitry to protect the
Inputs against damage due to high static
voltages or electric fields. however. It IS
advised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to this high
Imped,;nce Circuit For proper operation It IS
recommended that V ,n and Vout be
constrained to the range VSS
(V ,n or
Vout)'
6-35
VOO
®
MC145144
MOTOROLA
4-BIT DATA BUS INPUT PLL FREQUENCY SYNTHESIZER
The MC145144 is one of a family of LSI PLL frequency synthesizer
parts from Motorola CMOS. The family includes devices having serial,
parallel and 4-bit data bus programmable inputs. Options include singleor dual-modulus capability, transmit/receive offsets, choice of phase
detector types and choice of reference divider integer values.
The MC145144 is programmed by a 4-bit input, with strobe and address lines. The device features consist of a reference oscillator, programmable reference divider, digital-phase detector, programmable
divide-by-N counter and the necessary latch circuitry for accepting the
4-bit input data. When combined with a loop filter and VCO, the
MC145144 can provide all the remaining functions for a PLL frequency
synthesizer operating up to the device's frequency limit. For higher VCO
frequency operation, a down mixer or a fixed divide prescaler can be used between the VCO and MC145144.
CMOS LSI
(LOW-POWER COMPLEMENTARY MaS)
4-BIT DATA BUS INPUT PLL
FREQUENCY SYNTHESIZER
• Tailored for TV Tuning Applications
• Low Power Drain
• 3.0 to 9.0 Vdc Supply Range
•
I
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
CASE 620
PLASTIC PACKAGE
CASE 648
>30 MHz Typical Input Capability @5 Vdc
• Programmable Reference Divider for Values Between 3584 and 3839
PIN ASSIGNMENT
• On- or Off-Chip Reference Oscillator Operation
Voo ,.
• Single Modulus 4-Bit Data Bus Programming
•
..;- N Range = 4 to 4092 in Steps of Eight
OSCin
2
OSCout
3
AO
4
• "Linearized" Digital Phase Detector Enhances Transfer Function
Linearity
• Pin-for-Pin Compatible with the MN6044
NOT RECOMMENDED FOR NEW DESIGNS
PRODUCT BEING PHASED OUT
Closest equivalent is the MC145145·1
6·36
®
MC145145·1
MOTOROLA
Advance Information
HIGH-PERFORMANCE
CMOS
LOW POWER COMPLEMENTARY MOS
SILICON GATE
4-BIT DATA BUS INPUT PLL FREQUENCY SYNTHESIZER
The MC145145-1 is programmed by a 4-bit input, with strobe and address lines. The device features consist of a reference oscillator, 12-bit
programmable reference divider, digital-phase detector, 14-bit programmable divide-by-N counter and the necessary latch circuitry for accepting the 4-bit input data. When combined with a loop filter and VCO, the
MC145145-1 can provide all the remaining functions for a PLL frequency synthesizer operating up to the device's frequency limit. For higher
VCO frequency operation, a down mixer or a fixed divide prescaler can
be used between the VCO and MC145145-1.
The MC145145-1 offers improved performance over the MC145145.
The ac characteristics have been improved and the input current requirements have been modified.
• General Purpose Applications:
CATV
TV Tuning
AM/FM Radios
Scanning Receivers
Two Way Radios Amateur Radio
•
•
•
•
Low Power Consumption
3.0 to 9.0 V Supply Range
On- or Off-Chip Reference Oscillator Operation
Single Modulus 4-Bit Data Bus Programming
•
-+- R Range= 3 to 4095
•
-+- N Range= 3 to 16383
4-BIT DATA BUS INPUT PLL
FREQUENCY SYNTHESIZER
J_
-
18
1
1
MC145145L1
MC145145P1
CERAMIC PACKAGE
CASE 726
PLASTIC PACKAGE
CASE 707
PIN ASSIGNMENT
01
• "Linearized" Digital Phase Detector Enhances Transfer Function
Linearity
02
DO
03
fin
REFout
VSS
V with fR in
Phase with fV (Figures 3 and 6)
twt/>
Input Rise and Fall Times
OSCin, fin (Figure 4)
tr,tf
Input Pulse Width
ST (Figure 5)
tw
-
9
-
3
5
40
9
35
25
30
18
10
10
60
60
-
ns
-
-
ns
-
-
-
II
6-39
MC145145·1
GRAPH 1 -
OSCin AND fin MAXIMUM FREQUENCY VERSUS TOTAL DIVIDE VALUE
GRAPH 1A - VDD=3V
GRAPH 1B - VDD = 5 V
::<:
~
14
28
26
24~~-1--+--+--r-'~~~~-+~~~'~--+-~
22~~-4--+--+--~~-4~+--+--r-~'~--+-~
12r-~~--+--+--~-~~--+--+--r-~'~--+-~
20r-~-+--+-~~r-4-~--+--~-~--~r+--~~
~
10r-~~--+-~~~~~--+--+--"--~'~--+-~
18~~-T~r-~-+~~+--+--r-+--~'H---+-~
a
a
E
E
E
;:;
E
;:;
16r-~74--~~~r-+--+--+-~-4--~~--~~
14r-+--+--r-+--+--~
:W 12 t---::--+---+---c-r--i:
:W
.<
j
10
8
Max
Total Divide Value
Total D,v,de Value
GRAPH 1C - VDD = 9 V
::<:
28r-~-4--+--+--r-~--4--+--+--~·4-<~
1.000
0.993
~~
f"~ ~
~ , ~t--5V
:;:
'3 V
0
f'.-.
'-.... '"
3V
5V
9V
....... ~ ~
1
'\
1'9 V
-40
- 20
20
40
60
80
-40
labelled "Typical"
IS
not to be used for design purposes, but
- 20
20
40
60
Temperature (OCI
Temperature (OCI
* Data
\
IS
Intended as an indication of the Ie's potential performance
6-40
80
MC145145·1
PIN DESCRIPTIONS
DATA INPUTS (Pins 2,1,18,17) - Information at these
Inputs IS transferred to the mternal latches when the ST input is In the high state Pin 17 (03) is most significant
ST (Pin 11) - When high, thiS Input will enter the data
that appears at the 00,01,02 and 03 inputs, and when low,
will latch that Information. When high, any changes In the
data information will be transferred Into the latches
fin (Pin 3) - Input to -+- N portion of synthesizer fin IS
typically derived from loop VCO and IS AC coupled mto Pin
3. For larger amplitude signals (standard CMOS-logic levels)
DC coupling may be used
VSS (Pin 4) VDD (Pin 5) -
PD out (Pin 12) - Three-state output of phase detector for
use as loop error signal
Frequency fV> fR or fV Leading Negative Pulses
Frequency IV < fR or fV Laggmg. Positive Pulses
Frequency fV = fR and Phase COinCidence HlghImpedance State
Circuit Ground
Positive power supply
OSCin, OSCout (Pins 6 and 7) - These pins form an onchip reference oscillator when connected to terminals of an
external parallel resonant crystal
Frequency setting
capacitors of appropriate value must be connected from
OSCin to ground and OSCout to ground. OSC ln may also
serve as Input for an externally-generated reference signal
ThiS signal will tYPically be AC coupled to OSC ln , but for
larger amplitude signals (standard CMOS-logic levels) DC
coupling may also be used. In the external reference mode,
no connection IS required to OSC out
LD (Pin 13) - Lock detector Signal. High level when loop
IS locked (fR, fV of same phase and frequency I Pulses low
when loop is out of lock
R pulsing low.
---+
7/
10~
.0046 MHz
Steps)
t
LD
REFout
OSCin
DO
~ D2
~ D3
8
AO
9
Al
7.9996 to 320184 ~
(100 Hz Steps)
in
16
AO
~»-i-
/'
Loop 2
Filter
....
VC02
/
4.000
(1
9
A1
,..10
A2
fin 2
ST
fl
"
Address &~a
To Controller
VDD
b5
b
NOTES:
Chip sele/
3
VSS
4
provides program sequence lor the +
N I \ LOOP 1)
and +
NL \ Loop
2) Counters.
2. + Rl = 1000, fRl = 10.1 kHz; + R2= 1010, fR2= 10 kHz.
3. fVCOl = NHfRl) + N2(fR2) = NWR2+6f) + N2(fR2) wherl?6f= 100 Hz.
4. Other fRl and fR2 values may be used with appropriate -;. Nl and -;. N2 changes.
MC145145·1
TABLE 1 -!-
..t.
~
Nl
396
397
+
PROGRAMMING SE~UENCE FOR TWO-LOOP SYNTHESIZER OF FIGURE 9
fin1 (MHz)
3.9996
":"
4''f7
~
495
t
+N2
400
399
tvC02 (MHz)
4.0000
3.9900
301
401
400
30100
4.0100
4.0000
8.0095
8.0096
8.0097
3.0200
4.0200
4.0100
8.0195
8.0196
8.0197
,
4.9995
"1,,
"A"
~
t
t
.J.
f
"A"
"C"
302
402
401
+
303
,1
I
"A"
1
"1,,
+
1585
1586
1684
"J..
"8"
t •
"F"
~
1600
1599
+
1501
+
3.0300
15L
16.0000
15.9900
+
15.0100
17.0084
.J.
~
+
+
+
8.0295
Increasing
In 100 Hz Steps
+
19.9995
19.9996
19.9997
+
20.0095
20.0085
20.0086
,
20.0184
20.0185
20.0186
"C"
"0"
t
20.0284
Increasing
In 100 Hz Steps
+
•
1
"0"
16.0085
16.0186
32.0084
32.0085
32.0086
4
"E"
,
,
tvC01 (MHz)
7.9996
7.9997
"F"
32.0~84
.~
6-47
II
MC145145·1
CRYSTAL OSCILLATOR CONSIDERATIONS
the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input! output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable is discussed first.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-~ompensated crystal
oscillators (TXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-to-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Products, 2553 N. Edgington St., Franklin Park, I L 60131, phone
(312) 451-1000.
CL= CinCout +Ca+CO+ C1·C2
Cin + Cout
C1 + C2
where
Ca
Co
C1 and C2
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverted along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD'" 5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
PARTIAL LIST OF CRYSTAL MANUFACTURERS
ADDRESS
NAME
United States Crystal Corp.
Crystek Crystal
Statek Corp
5 pF (see Figure C)
6 pF (see Figure C)
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
External capacitors (see Figure Al
The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Couto
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified t1ll the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i.e. R1 '" 0 ohms.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply Voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A.
DESIGN AN OFF-CHIP REFERENCE
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference Signal from the MECL device is ac
'coupled to OSCin. For large amplitude Signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.
TABLE A -
Cin
Cout
3605 McCart St., Ft. Worth, TX 76110
1000 Crystal Dr., Ft. Myers, FL 33906
512 N. Main St., Orange, CA 92668
PHONE
(817) 921-3013
18131936-2109
(714) 639-7810
RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro- Technology, June, 1969.
Technical Note TN-7, Statek Corp.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.
6-48
MC145145·1
FIGURE A - PIERCE CRYSTAL OSCILLATOR CIRCUIT
r-
-----------l
Rf
I
Frequency
Synthesizer
I
I
I
I
I
I
IL_
_ _ _ _ _ _ _ _ ....1
OSC out
* May
be deleted in certain cases. See text.
FIGURE B - EQUIVALENT CRYSTAL NETWORKS
RS
1
cr-f
I
LS
Cs
~
01--0
2
Co
Values are supplied by crystal manufacturer (parallel resonant crystal).
FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER
a
o
~
II
,I
I
:;:: Cin
,
--11-- -------,,----0
I
::r:I
I
_J._
_.L._
6-49
Cout
®
MC145146·1
MOTOROI.A
Advance Information
HIGH-PERFORMANCE
CMOS
LOW-POWER COMPLEMENTARY MaS
SILICON-GATE
4-BIT DATA BUS INPUT PLL FREQUENCY SYNTHESIZER
The MC145146-1 is programmed by a 4-bit input, with strobe and address lines. The device features consist of a reference oscillator, 12-bit
programmable reference divider, digital phase detector, 10-bit programmable divide-by-N counter, 7-bit divide-by-A counter and the necessary
latch circuitry for accepting the 4-bit input data. When combined with a
loop filter and VCO, the MC145146-1 can provide all the remaining functions for a PLL frequency synthesizer operating up to the device's frequency limit. For higher VCO frequency operation, a down mixer or a
dual modulus prescaler can be used between the VCO and the
MC145146-1.
The MC145146-1 offers improved performance over the MC145146.
Modulus Control output drive has been increased and the ac
characteristics have been improved. The input current requirements
have also been modified.
4-BIT DATA BUS INPUT PLL
FREQUENCY SYNTHESIZER
• General Purpose Applications:
CATV
TV Tuning
AMI FM Radios
Scanning Receivers
Two Way Radios
Amateur Radio
II
Low Power Consumption
3.0 to 9.0 V Supply Range
Programmable Reference Divider for Values Between 3 and 4095
On- or Off-Chip Reference Oscillator Operation
Dual Modulus 4-Bit Data Bus Programming
• + N Range=3 to 1023, + A Range=O to 127
• "Linearized" Digital Phase Detector Enhances Transfer Function
Linearity
01
02
DO
03
fin
fR
PO out
VDO
OSC out
LD
AO
ST
A1
A2
~__~__________~'8
"""-----~
~------------------+-+-~r----'
~1
_____
___+-~
___+-~~
_________________-+~~1-
________________
Latches
Voo= Pin 6
Vss=Pin4
This document contains information on a new product. Specifications and information herem
are subject to change without notice
6-50
IV
Modulus Control
OSCin
OSC,n
D2 ~w~
-+-+~~
D3 ~19~______________-+-+~~
R
V
VSS
• Two Error Signal Options:
Single Ended (Three State)
Double Ended
• Chip Complexity: 5692 FETs or 1423 Equivalent Gates
DO
D1
MC145146P1
PLASTIC PACKAGE
CASE 738
PIN ASSIGNMENT
•
•
•
•
•
OSCout
MC145146L1
CERAMIC PACKAGE
CASE 732
~
fR
MC145146·1
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Value
Unit
-05 to +10
V
Parameter
DC Supply Voltage
VDD
Input or Output Voltage (DC or Transient)
Yin, Vout
lin, lout
100, ISS
-0.5 to VDD+05
V
Input or Output Current (DC or Transient), per Pin
±10
mA
Supply Current, VDO or VSS Pins
±30
mA
500
mW
-65 to + 150
°C
260
°C
Power Oissipation, per Packaget
Po
Storage Temperature
Tstll
TL
Lead Temperature (S-Second Soldering)
* Maximum
Ratings are those values beyond which damage to the device may occur.
tPower Dissipation Temperature Derating
Plastic "P" Package: -12 mW/oC from 65°C to 85°C
Ceramic "L" Package: No derating
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid applications of any voltage
higher than maximum rated voltages to
this high-impedance circuit. For proper
operation it is recommended that Yin and
Vout be constrained to the range
VSSS(Vin or Vout)sVOO
Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
either VSS or VOO)
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
-40°C
Characteristic
lout ""
°
85°C
VOO
Min
Max
Min
Typ
Max
Min
Max
Units
°
VOO
-
3
9
3
-
9
3
9
V
VOL
3
5
9
-
-
0.05
0.05
0.05
0.05
0.05
0.05
V
-
0.001
0.001
0.001
-
-
0.05
0.05
0.05
1 Level
VOH
3
5
9
2.95
4.95
8.95
-
2.95
4.95
8.95
2.999
4.999
8.999
-
3
5
9
-
-
0.9
1.5
2.7
-
-
1.35
2.25
405
0.9
1.5
2.7
3
5
9
2.1
3.5
6.3
-
21
3.5
6.3
1.65
2.75
4.95
-
3
5
9
-0.60
-0.90
-1.50
-0.50
-0.75
-1.25
-1.5
-2.0
-3.2
-
3
5
9
1.30
1.90
3.80
-
1.10
1.70
3.30
5.0
6.0
10.0
-
3
5
9
-0.44
-0.64
-1.30
-
-0.35
-0.51
-100
-1.0
-
-1.2
-
- 2.0
-
3
5
9
0.44
0.64
1.30
0.35
0.51
1.00
1.0
1.2
2.0
-
Power Supply Voltage Range
Output Voltage
Vin=O V or VOO
25°C
Symbol
Level
,.A
Input Voltage
Level
Vou t=0.5 V or VOO--O.5 V
(All Outputs Except OSC out )
°
VIL
1 Level
VIH
Output Current - Modulus Control
V ou t=2.7V
Source
V out =4.6 V
V out =8.5 V
V ou t=0.3V
Vout=OA V
V out =0.5 V
Sink
-
-
-
-
-
2.95
4.95
8.95
-
-
-
0.9
1.5
2.7
2.1
3.5
6.3
-
-0.30
-050
-0.80
-
IOL
0.66
1.08
2.10
-
10H
Sink
10L
V
-
mA
10H
Output Current - Other Outputs
Vout =27V
Source
V out =4.6 V
V ou t=8.5 V
V ou t=03 V
Vout=OA V
V ou t=0.5 V
-
-
-
-
-
-
-
-
mA
-
-
-
-022
-0.36
-0.70
-
0.22
0.36
0.70
-
-
-
Cin
--
-
10
-
6
10
-
10
pF
3-State Output Capacitance PO out
Cout
--
--
10
-
6
10
-
10
pF
Quiescent Current
Vin=O V or VDD
10ut=0 ,.A
3-State Leakage Current - PO out
Vout=O V or 9 V
100
3
5
9
-
200
300
400
800
1200
1600
,.A
-
1600
2400
3200
9
-
±03
-
-
--
800
1200
1600
±0.0001
±01
-
±30
p.A
Input Current - Other Inputs
lin
9
-
±03
-
±0.00001
±01
Input Current - fin, OSC m
lin
9
-
±50
-
±10
±25
Input Capacitance
10Z
-
6-51
-
± 10
p.A
± 22
,.A
MC145146·1
SWITCHING CHARACTERISTICS
(T A = 25°C, CL = 50 pF)
Characteristic
Output Rise Time, Modulus Control (Figures 1 and 7)
Output Fall Time, Modulus Control (Figures 1 and 7)
VDD
Min
Typ
Max
Units
tTLH
3
5
-
50
ns
-
30
20
115
60
40
25
17
15
60
34
30
ns
60
40
30
140
80
60
ns
125
80
50
ns
-
ns
tTHL
Output Rise and Fall Time, Other Outputs (Figure 1)
I
Symbol
Propagation Delay Time
fin to Modulus Control (Figures 2 and 7)
Setup Times
Data to ST (Figure 3)
9
-
3
5
-
9
-
tTLH,
tTHL
3
5
-
9
-
tpLH,
tpHL
3
5
-
9
10
10
10
55
40
25
0
0
0
80
50
30
60
30
18
-
35
25
20
15
10
10
-
25
20
15
10
10
-
10
-
25
20
10
100
60
40
175
100
70
ns
-
20
5
2
5
2
0.5
JLs
40
35
25
30
20
15
-
ns
tsu
3
5
9
Address to ST (Figure 3)
3
5
9
Hold Times
Address to ST (Figure 3)
th
3
5
9
Data to Strobe (Figure 3)
3
5
9
Output Pulse Width, v
oVCO
I
Rl
LOW.,.PASS FILTER DESIGN
"'N =
C
(/IRO--
I
(/Iv 0 - -
Fis) = _ _
,_
R1CS + 1
B)
PDouto
'VV'>v
"i
Rl
V and 4>R
KVCO = 211'AfVCO
AVyCO
for a typical design "'N :: (211'/10) fr (at phase detector input)
r =1
6-54
MC145146·1
FIGURES
PHASE DETECTOR OUTPUT WAVEFORMS
fR
Reference
IOsc + RI
fV
Feedback
Ifin + NI
Po
Out
R
v
~
n
U
~
I
I
I
~
LO
NOTE: The
Po
u
IJ
output state is equal to either VOO or VSS when active. When not active, the output is high impedance and the voltage at that
pin is determined by the low pass filter capacitor.
6-55
II
MC145146·1
PIN DESCRIPTIONS
DATA INPUTS (Pins 2, 1,20, 19) - Information at these
inputs is transferred to the internal latches when the ST input is in the high state. Pin 19 (03) is most significant.
will latch that information When high, any changes in the
data information will be transferred into the latches.
LD (Pin 13) - Lock detector signal. High level when loop
is locked (fR, fV of same phase and frequency). Pulses low
when loop is out of lock.
fin (Pin 3) - Input to -;- N portion of synthesizer fin is
typically derived from loop VCO and is AC coupled into Pin
3. For larger amplitude signals (standard CMOS-logic levels),
DC coupling may be used.
Vss (Pin 4) -
MODULUS CONTROL (Pin 14) - Signal generated by the
on-chip control logic circuitry for controlling an exter,1al dual
modulus prescaler. The modulus control level will be low at
the beginnmg of a count cycle and will remam low until the
-;.- A counter has counted down from its programmed value.
At this time, modulus control goes high and remains high
until the -;.- N counter has counted the rest of the way down
from its programmed value (N-A additional counts since
both -;- Nand -;.- A are counting down during the first portion
of the cycle). Modulus control is then set back low, the
counters preset to their respective programmed values, and
the above sequence repeated. This provides for a total programmable divide value (NT) == N-P + A where P and P + 1
represent the dual modulus prescaler divide values respectively for high and low modulus control levels; N the number
programmed into the -;.- N counter and A the number programmed into the -;.- A counter
Circuit Ground.
PDout (Pin 5) - Three-state output of phase detector for
use as loop error signal.
Frequency fV> fR or fV Leading: Negative Pulses.
Frequency fV < fR or fV Lagging: Positive Pulses.
Frequency fV == fR and Phase Coincidence: HighImpedance State.
VDD \Pin 6) -
Positive power supply.
OSCin, OSCout (Pins 7 and 8) - These pins form an onchip reference oscillator when connected to terminals of an
external parallel resonant crystal. Frequency setting
capacitors of appropriate value must be connected from
OSCin to ground and OSCout to ground. OSCin may also
serve as input for an externally-generated reference signal.
This signal will typically be AC coupled to OSCin, but for
larger amplitude signals (standard CMOS-logic levels) DC
coupling may also be used. In the external reference mode,
no connection is required to OSC out .
tv (Pin 15) - This is the output of the -;.- N counter that is
internally connected to the phase detector input. With this
output available, the -;.- N counter can be used independently.
ADDRESS INPUTS (Pins 9, 10, 11) - AO, A 1 and A2 are
used to define which latch receives the information on the
data input lines. The addresses refer to the following latches:
A2 Al
AO Selected
a a a
a a 1
a 1 a
a 1 1
a a
a 1
1
a
1
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
a
1
2
3
4
5
6
7
Function
DO Dl
-;.-A Bits
1
-;.-A Bits
4
5
-;.- N Bits
1
-;.- N Bits
4
5
-;.- N Bits
8 9
Reference Bits
1
Reference Bits 4
5
Reference Bits 8
9
a
a
a
cfJV, cfJR (Pins 16 and 17) - These phase detector outputs
can be combined externally for a loop error signal. A singleended output is also available for this purpose (see PD out ).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by cfJV pulsing
low. cfJR remains essentially high.
If the frquency fV is less than fR or if the phase of fV is lagging, then error information is provided by cfJR pulsing low.
cfJv remains essentially high.
If the frequency of tv == tR and both are in phase, then
both cfJv and cfJR remain high except for a small minimum
time period when both pulse low in phase.
D2 D3
2
3
6
6
3
7
2
6
3
7
2
10 11
fR (Pin 18) - This is the output at the ... R counter that is
internally connected to the phase detector input. With this
output available, the -;.- R counter can be used independentIy.
ST (Pin 12) - When high, this input will enter the data
that appears at the DO, D1, D2 and D3 inputs, and when low,
6-56
MC145146·1
SWITCHING WAVEFORMS
FIGURE2
FIGURE 1
,----VDD
ITHL
Any
Output
-Vss
~-t
Modulus
Control
FIGURE4
FIGURE 3
Data or
Address
.h=r
-VDD
VSS
V
II
16
Mod 14
Control
6 VDD
Control Voltage
To FM anQ AM
Oscillators
4
A2 A1 AO
ST
From
AM OSC
NOTES: 1) For FM: Channel spacing = fR = 25 kHz, ... R = 160.
For AM: Channel spacing = fR = 1 kHz, ... R = 4000.
2) Various channel spaCings and reference oscillator frequencies can be chosen since any -+ R value from 3 to 4095 can be established.
3) Data and address lines are inactive and high impedance when pin 12 is low. Their interface with the controller may therefore be
shared with other system functions if desired.
6-58
3:
o
......
".
en
......
".
cp
FIGURE 10 - SYNTHESIZER FOR UHF MOBILE RADIO TELEPHONE CHANNELS DEMONSTRATES USE OF THE MC145146-1 IN
MICROPROCESSOR/MICROCOMPUTER CONTROLLED SYSTEMS OPERATING TO SEVERAL HUNDRED MHz
~-
- - - -
;- - -
-~}
For Use with External
Phase Detector (Optional)
--~
Choice of
Ref. Osc.
Frequency
(On-Chip Osc.
Optional)
------.
Lock Detect
Signal
Receiver
L.O.
443.325-- 443.950
MHz
(25 kHz Steps)
LD
PDo",F, ,
IOSCin
Transmitter
Modulation
and 15.7 MHz
Otfset
cPR 17
(J)
c:n
CO
~VDD
MC145146-1
Mod ~
Control
4
VSS
fin 3
\
V
To Shared
Controller Bus
NOTES 1)
2)
3)
4)
5)
cPV 16
/ ChiP Select
to Controller
Dual Modulus Prescaler
Receiver I.F.= 10.7 MHz, low side inJection.
Duplex operation with 5 MHz receive/transmit separation
fR = 25 kHz, ~ R chosen to correspond with desired reference oscillator frequency
Ntotal = 17733 to 17758= N.P + A; N = 277, A = 5 to 30 for P = 64
For faster response, use the MC10154 down counter.
II
Transmitter Signal
459.025--459650 MHz
125 kHz Steps)
......
II
3:
o
-a.
.p..
U'1
-a.
.p..
en
~
FIGURE 11 - 666 CHANNEL, COMPUTER CONTROLLED, MOBILE RADIO TELEPHONE SYNTHESIZER FOR
800 MHz CELLULAR RADIO SYSTEMS
- - - - ...
1- - -.-)
Ref. Osc.
11.100 MHz
(On-Chip Osc.
Optional!
:
Receiver
2nd. L.a.
33.300 MHz
For Use With
External
Phase Detector
(Optional!
Receiver First L.O
825.030- 844980 MHz
(30 kHz Steps)
I
Lock Detect Signal
OSC out fR
-1
fV
LD
PDout
t - I-
- - I OSCin
(J)
m
o
VDD
.5
~RE
MC145146-1
16
~V
Mod 114
Control
41
VSS
fin
Transmitter Signal
825.030- 844.980 MHz
(30 kHz Steps)
\
Controller Bus
NOTES: 1)
2)
3)
4)
5)
I
V
+
32/ + 33 Dual Modulus Prescaler
Receiver 1st. I.F. =45 MHz. low side injection; Receiver 2nd. I.F. = 11.7 MHz. low side injection.
Duplex operation with 45 MHz receive/transmit separation.
fR = 7.5 kHz. + R = 1480.
Ntotal = N-32 + A = 27501 to 28166; N = 859 to 880; A = 0 to 31
Only one implementation is shown. Various other configurations and dual modulus prescaling values to
+
128/ + 129 are possible.
MC145146·1
CRYSTAL OSCILLATOR CONSIDERATIONS
the area of 8 to 15 M Hz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input! output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable is discussed first.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-compensated crystal
oscillators (TXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-to-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OS Cout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Products, 2553 N. Edgington St., Franklin Park, IL 60131, phone
(312) 451-1000.
CL=CinCout +Ca+CO+ C1·C2
Cin + Cout
C1 + C2
where
Co
C1 and C2
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference signal from the MECL device is ac
co~pled to OSCin. For large amplitude signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD=5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp
Crystek Crystal
Statek Corp
5 pF (see Figure C)
6 pF (see Figure C)
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
External capacitors (see Figure A)
The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Cout·
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified by the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i.e. R1 = 0 ohms.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals
Discussions with such manufacturers can prove very helpful
See Table A.
DESIGN AN OFF-CHIP REFERENCE
TABLE A -
Cin
Cout
Ca
ADDRESS
3605 McCart St., Ft. Worth, TX 76110
1000 Crystal Dr, Ft. Myers, FL 33906
512 N. Main St, Orange, CA 92668
PHONE
1817) 921·3013
1813) 936·2109
1714) 639·7810
RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro- Technologv, June, 1969
Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.
6-61
MC145146-1
FIGURE A ~ PIERCE CRYSTAL OSCILLATOR CIRCUIT
r------·
------l
Rf
I
I
I
I
I
_ _ _ _ _ _ _ ..J
I
I
IL_
Frequency
Synthesizer
_
OSCin
OSCout
o
Rl*
f-....+..---'VV'v---'
I
Cl,T
* May
C2
be deleted in certain cases. See text.
FIGURE B - EaUIVALENT CRYSTAL NETWORKS
RS
I
LS
Cs
~
10 r--o
2
~
Co
Values are supplied by crystal manufacturer (parallel resonant crystall.
FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER
a
o
~
II
I
I
_L Cin
-T-
--ll--
--------,I----~O
I
_l_
I
I
:;:: Cout
I
_.l._
6-62
®
MC145151-1
MOTOROLA
HIGH-PERFORMANCE
Advance Information
CMOS
LOW-POWER COMPLEMENTARY MOS
SILICON-GATE
PARALLEL INPUT PLL FREQUENCY SYNTHESIZER
PARALLEL INPUT PLL
FREQUENCY SYNTHESIZER
The MC145151-1 is programmed by 14 parallel input-data lines. The
device features consist of a reference oscillator, selectable-reference
divider, digital-phase detector and 14-bit programmable divide-by-N
counter. When combined with a loop filter and VCO, the MC145151-1
can provide all the remaining functions for a PLL frequency synthesizer
operating up to the device's frequency limit. For higher VCO frequency
operation, a down mixer or a fixed divide prescaler can be used between
the VCO and MC145151-1.
The MC145151-1 offers improved performance over the MC145151.
The ac characteristics have been improved and the input current requirements have been modified.
• General Purpose Applications:
CATV
TV Tuning
AM/FM Radios
Scanning Receivers
Two-Way Radios Amateur Radio
MC145151L1
MC145151P1
CERAMIC PACKAGE
CASE 733
PLASTIC PACKAGE
CASE 710
PIN ASSIGNMENT
• Low Power Consumption
• 3.0 to 9.0 V Supply Range
• On- or Off-Chip Reference Oscillator Operation
• Lock Detect Signal
• -+- N Counter Output Available
• Single Modulus/Parallel Programming
• 8 User-Selectable -+- R Values - 8, 128,256,512,1024,2048,2410,
8192
II
• -+- N Range= 3 to 16383
• "Linearized" Digital Phase Detector Enhances Transfer Function
Linearity
• Two Error Signal Options:
Single Ended (Three-State)
Double Ended
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates
Voo= Pin 3
Vss=Pin2
T~~~~~ ..::2"'-1_ _ _ _ _ _ _-+~
L-~~~~~~~~~~~~_r~
N13
N11
N9
N7 N6
N4
This document contains information on a new product. Specifications and information herein
are subiect to change without notice
6-63
NO
Note: NO through N13 inputs and inputs
RAO, RA 1 and RA2 have pullup resistors
not shown.
MC145151·1
MAXIMUM RATINGS* IVoltages Referenced to VSS)
Value
Unit
+ 10
- 0.5 to VOO + 0.5
V
Input or Output Current IDC or Transient), per Pin
±10
rnA
Supply Current, VOO or VSS Pins
±30
rnA
500
mW
DC
Parameter
Symbol
VOO
Yin, Vout
lin, lout
100, ISS
Po
Tstg
h
DC Supply Voltage
-0.5 to
Input or Output Voltage IDC or Transient)
Power Dissipation, per Packaget
-65 to
Storage Temperature
+ 150
V
DC
260
Lead Temperature 18-Second Soldering)
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid applications of any voltage
higher than maximum rated voltages to
this high-impedance circuit. For proper
operation it is recommended that Yin and
V out be constrained to the range
VSS,sIVin or Vout),sVOO·
Unused inputs must always be tied to
an appropriate logic voltage level le.g.,
either VSS or VODI.
* Maximum
Ratings are those values beyond which damage to the device may occur
tPower Dissipation Temperature Derating:
Plastic "P" Package: -12 mW/DC from 65 DC to 85 DC
Ceramic "L" Package: No derating
ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSS)
-40°C
Characteristic
Power Supply Voltage Range
Output Voltage
Vin=O V or VOO
10ut"'0 p.A
o Level
1 Level
I
85°C
VOO
Min
Max
Min
Typ
Max
Min
Max
VOO
-
3
9
3
-
9
3
9
V
VOL
3
5
9
-
-
0.05
0.05
0.05
0.05
0.05
0.05
V
-
0.001
0.001
0.001
-
-
0.05
0.05
0.05
3
5
9
2.95
4.95
8.95
-
2.95
4.95
8.95
2.999
4.999
8.999
-
2.95
4.95
8.95
3
5
9
-
-
0.9
1.5
2.7
-
-
1.35
2.25
4.05
3
5
9
2.1
3.5
6.3
-
2.1
3.5
6.3
1.65
2.75
4.95
-
2.1
3.5
6.3
-
3
5
9
-0.44
-0.64
-1.30
-
-0.35
-0.51
-1.00
-1.0
-1.2
-2.0
-0.22
-0.36
-0.70
-
3
5
9
0.44
0.64
1.30
0.35
0.51
1.00
1.0
1.2
2.0
VOH
Input Voltage
o Level
V out =0.5 V or VOD-0.5 V
IAII Outputs Except OSCout)
VIL
1 Level
VIH
Output Current
Vout= 27 V
V ou t=4.6 V
V ou t=8.5 V
25°C
Symbol
-
-
-
0.9
1.5
2.7
-
-
-
-
-
-
-
-
0.9
1.5
2.7
Sink
V ou t=0.3 V
Vout=OA V
V ou t=0.5 V
Input Current - fin, OSCin
Input Current - Other Inputs
Iwith Pullups)
IOL
V
-
mA
IOH
Source
Units
-
-
0.22
0.36
0.70
-
lin
9
-
±50
-
±10
±25
p.A
-
0.3
-
0.00001
0.1
1.0
p.A
IlL
9
9
-
±22
IIH
-
-400
-
-90
-200
-
-170
Cin
-
-
10
-
6
10
-
10
pF
3-State Output Capacitance -
Cout
-
-
10
-
6
10
-
10
pF
POout
Quiescent Current
Vin=O V or VOO
10ut=0 p.A
100
3
5
-
-
-
1600
2400
3200
p.A
-
800
1200
1600
-
-
200
300
400
-
9
9
800
1200
1600
-
±0.3
-
±O.OOOl
±0.1
-
±3.0
p.A
Input Capacitance
3-State Leakage Current Vout=O V or 9 V
POout
IOZ
-
6-64
-
MC145151·1
SWITCHING CHARACTERISTICS (T A = 25°C CL = 50 pF)
Characteristic
Symbol
Output Rise and Fall Time (Figures 1 and 4)
tTLH,
tTHL
Output Pulse Width,
.pR, .pV with fR in Phase with fV (Figures 2 and 4)
tw(.p)
Input Rise and Fall Times
OSCin, fin (Figure 3)
tr, tf
VDD
3
5
Min
Typ
Max
Units
-
60
40
30
100
60
40
20
5
2
140
80
60
175
100
70
5
2
0.5
ns
-
9
-
3
5
9
3
5
9
25
20
10
-
-
ns
p's
PIN DESCRIPTIONS
fin (Pin 1) - Input to -i- N portion of synthesizer. fin is
typically derived from loop VCO and is ac coupled into Pin 9.
For larger amplitude signals (standard CMOS Logic levels)
dc coupling may be used.
VSS (Pin 2) -
Circuit ground.
VDD (Pin 3) -
Positive power supply.
PDout (Pin 4) - Three-state output of phase detector for
use as loop error signal. Double-ended outputs are also
available for this purpose (see ¢V and ¢R).
Frequency fV > fR or fV Leading: Negative Pulses
Frequency tv < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: HighImpedance State.
RAO, RA1, RA2 (Pins 5, 6, and 7) - These three inputs
establish a code defining one of eight possible divide values
for the total reference divider, as defined by the table below.
Pullup resistors ensure that inputs left open remain at a
logic one and require only a SPST switch to alter data to the
zero state.
Reference Address
Code
RAO
RA2
RA1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
0
1
1
1
Total
Divide
Value
8
128
256
512
1024
2048
2410
8192
¢R, ¢V (Pins 8 and 9) - These phase detector outputs
can be combined externally for a loop-error signal. A singleended output is also available for this purpose (see PDoutl.
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by ¢V pulsing
low. ¢R remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by ¢R pulsing
low. ¢V remains essentially high.
6-65
If the frequency of fV = fR and both are in phase, then
both ¢V and ¢R remain high except for a small minimum
time period when both pulse low in phase.
tv (Pin 10) - This is the output of the ... N counter that is
internally connected to the phase detector input. With this
output available, the -+- N counter can be used independently.
N Inputs (Pins 11 to 20 and 22 to 25) - These inputs provide the data that is preset into the -i- N counter when it
reaches the count of zero. NO is least significant and N13 is
most significant. Pullup resistors ensure that inputs left open
remain at a logic one and require only a SPST switch to alter
data to the zero state.
Transmit/Receive (Pin 21) - This input controls the offset
added to the data provided at the N inputs. This is normally
used for offsetting the VCO frequency by an amount equal
to the IF frequency of the transceiver. This offset is fixed at
856 when T / R is low and gives no offset when T / R is high. A
pullup resistor ensures that no connection will appear as a
logic one causing no offset addition.
OSCout, OSCin (Pins 26 and 27) - These pins form an
on-chip reference oscillator when connected to terminals of
an external parallel resonant crystal. Frequency setting
capacitors of appropriate value must be connected from
OSCin to ground and OSCout to ground. OSCin may also
serve as the input for an externally-generated reference
signal. This signal will typically be ac coupled to OSCin, but
for larger amplitude signals (standard CMOS-logic levels) dc
coupling may also be used. in the external reference mode,
no connection is required to OSCout.
LD (Pin 28) - lock detector signal. High level when loop
is locked (fR, fV of same phase and frequency). Pulses low
when loop is out of lock.
II
MC145151·1
GRAPH 1 - OSCin AND fin MAXIMUM FREOUENCY VERSUS TOTAL DIVIDE VALUE
GRAPH lA - VDD=3V
~
~
'"
I
GRAPH 18 - VDD = 5 V
16
~
14
25°C
28
26
z
24r-~-+--r-~-+--~~-+L-r-~-+~~r-1-~
12
22r-1-~--+--+~~1-~r-+-~~~~'~--+-~
10
.~ 18r--r~~~-+--~~~--4--+--r-~fr4--+--"
20r-~-4--+-~~r-~~--+-~~~~'~--+-~
E
!
'K
'K
0
16r-1-~--~~~r-1-~--+-~~~~'~--+-~
E
~
~
:E
14r-~-+--r-1--+--~
~
j
12r-~-4--+-~
.<
1
10
Max
Total Divide Value
Total Divide Value
GRAPH lC - VDD=9V
~
~
28r-~~--+--+--r-~~--1--+--+-~~Hr-~~
26
I 24r-~~--+--+--~~~--4--+--+-~~H~4-~
~ 22r-~~~+--+--r-~~--4--+--+-~~~r-~~
.~ 20 r--t--+-t---t--_...:..:....
8E
~
I
'K
~ 14
1,2
Max
Total Divide Value
GRAPH 2 - OSCin AND fin MAXIMUM FREQUENCY VERSUS TEMPERATURE FOR
SINE AND SQUARE WAVE INPUTS
GRAPH 28 - TOTAL DIVIDE VALUE~6
GRAPH 2A - TOTAL DIVIDE VALUE= 3,4, OR 5
1.12
1.09
~~ 1.06
':::f! 1.03
f~
. ..,
3V •
~~-
,
!!
"
-~ ~
1.00
r--....
! ~ 0.97
~] 0.94
.~ ~
~~
1
.~~
gs
~~
,,~
0.91
0.88
0.85
0.82
0.79
i;;N
~
-......,
E'"
'~ ~5V
3V
'.
-20
20
40
60
.,
1
1.000
0.993
.<-
80
\
1.021
1.014
1.007
-40
Temperature I° C)
* Data
,
·~t
~~
r-.9 V
-40
1.063
3V
,,
1.056
1.049
,
1.042
5 V,
1.035
9 V r\
1.028
-
f'..
--"- --,....... ~ ....
-20
40
20
Temperature 1°C)
3V
5V
9V
60
80
labelled "Typical" is not to be used for design purposes, but is intended as an indication of the Ie's potential performance
6·66
MC145151·1
PHASE LOCKED LOOP - LOW PASS FILTER DESIGN
AI
1
Fisl = R1 CS
BI
PD out
+
1
VCO
Rl
Wn =
cPR 0---
R2
cPVo--C
I
C)
PD out 0 - Rl
cPR
cPV
>-----<'--oVCO
Rl
C
Assuming gain A is very large, then:
I
NOTE: Sometimes Rl is spli1 into two series resistors each Rl -;- 2. A capacitor Cc is then placed from the midpoint to ground to further filter
cPV and cPR· The value of Cc should be such that the corner frequency of this network does not significantly affect "'n·
DEFINITIONS: N = Total Division Ratio in feeoback loop
K,p = VDO/411' for PDout
K,p = VDD/211' for tPV and tPR
KVCO = 211'AfVCO
AVVCO
for a typical design Wn == 2;Ofr (at phase detector input!,
RECOMMENDED FOR READING:
Gardner, Floyd M., Phaselock Techniques (second edition), New York, Wiley-Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley-Interscience, 1980.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976.
Egan, William F, Frequency Synthesis by Phase Lock. New York, Wiley-Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983.
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
6-67
MC145151·1
SWITCHING WAVEFORMS
FIGURE 1
FIGURE2
~r~~------tw~------~,~,----
tTHL
Any
Output
~R,cjN* 50%\"' _________,
* f r in phase with fv
FIGURE3
FIGURE 4 -- TEST CIRCUIT
tf
-VDD
Vss
I
6-68
Device
Under
Test
Output
MC145151·1
FIGURE5
PHASE DETECTOR OUTPUT WAVEFORMS
fR
Reference
(Osc + RI
fV
Feedback
(fin + NI
Po Out
-----InL..----...ln~u---~-
u
I
NOTE: The Po output state is equal to either VOO or VSS when active
When not active, the output is high impedance and the voltage at that
pin is determined by the low pass filter capacitor
6-69
II
MC145151·1
FIGURE 6 - 5 MHz TO 5.5 MHz LOCAL OSCILLATOR CHANNEL SPACING= 1 kHz
2.048 MHz
Voltage
Controlled
OscIllator
5-55 MHz
o 1 1 1 0 0 0 1 0 0 0 = 5 MHz
I 0 1 0 1 1 1 1 1 00= 5.5 MHz
FIGURE 7 - SYNTHESIZER FOR LAND MOBILE RADIO UHF BANDS
Transmit: 440.0-470.0 MHz
Receive: 418.6-448.6 MHz
125 kHz Steps)
Ref. Osc
10.0417 MHz
IOn-Chip Osc
OptlonaD
ReceIve
o
~
N = 2384 to 3484
Transmit
IAdds 856 to
~ +NValuel
60.2500 MHz
NOTES:
n fA =4.1667 kHz; +R=2410; 21.4 MHz low side injection during receive
21 MC145151·' current drain;;;: 5 rnA for VDO=5 Vdc
31 Frequency values shown are for the 440-470 MHz band. Similar implementation applies to the 406-441 MHz band. For 470-512 MHz, consider referance oscillator frequency X9 for mixer injection signal (90.3750 MHz)
6-70
MC145151·1
CRYSTAL OSCILLATOR CONSIDERATIONS
the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable is discussed first
USE OF A HYBRID CRYSTAL OSCILLATOR
CL= CinCout +Ca+CO+ C1·C2
Cin+Cout
C1+C2
Commercially available temperature-compensated crystal
oscillators (TXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-to-rail (VOO to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OS Cin
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Products, 2553 N. Edgington St, Franklin Park, IL 60131, phone
(312) 451-1000
where
Co
C1 and C2
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference signal from the MECL device is ac
cOt:Jpled to OSCin. For large amplitude signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage sWing
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown In Figure A
For VOO = 5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequenCies to approximately 8 MHz, 20 pF for frequencies in
PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp
Crystek Crystal
Statek Corp
5 pF (see Figure C)
6 pF (see Figure CI
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
External capacitors (see Figure AI
The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Cout.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified by the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i.e. R1 =0 ohms.
To .verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout· (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or Rl must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A
DESIGN AN OFF-CHIP REFERENCE
TABLE A -
Cin
Cout
Ca
ADDRESS
3605 McCart SI, Ft. Worth. TX 76110
1000 Crystal Dr, FI Myers, FL 33906
512 N. Main St, Orange, CA 92668
PHONE
18171921-3013
18131 936-2109
1714) 639-7810
RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp
O. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro- Technology, June, 1969.
Technical Note TN-7, Statek Corp
P J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969
6-71
I
MC145151·1
FIGURE A - PIERCE CRYSTAL OSCILLATOR CIRCUIT
r-
-----------l
Rf
I
I
I
I
_ _ _ _ _ _ _ -1I
I
I
:L_
Frequency
Synthesizer
_
OSCout
o
Rl*
i-9---'VV'V---'
::L C2
Cl ~
* May
be deleted in certain cases. See text.
FIGURE B - EQUIVALENT CRYSTAL NETWORKS
RS
I
1
o--f
LS
Cs
~
0r--o
2
Co
Values are supplied by crystal manufacturer (parallel resonant crystal).
FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER
a
o
~
II
I
I
_1-
- , - Cin
--11--
----------.,---~O
I
_1_
I
I
::r:
I
_J.._
6·72
Cout
®
MC145152·1
MOTOROLA
Advance Information
HIGH-PERFORMANCE
CMOS
LOW-POWER COMPLEMENTARY MOS
SILICON-GA TE
PARALLEL INPUT PLL FREQUENCY SYNTHESIZER
PARALLEL INPUT PLL
FREQUENCY SYNTHESIZER
The MC145152-1 is programmed by sixteen parallel inputs. The
device features consist of a reference oscillator, selectable-reference
divider, two output phase dectector, lO-bit programmable divide-by-N
counter and 6-bit programmable -;- A counter. When combined with a
loop filter and VCO, the MC145152-1 can provide all the remaining functions for a PLL frequency synthesizer operating up to the device's frequency limit. For higher VCO frequency operation, a down mixer or a
dual modulus prescaler can be used between the VCO and
MC145152-1.
The MC145152-1 offers improved performance over the MC145152.
Modulus Control output drive has been increased and the ac
characteristics have been improved. Input current requirements have
also been changed.
MC145152Ll
MC145152Pl
CERAMIC PACKAGE
CASE 733
PLASTIC PACKAGE
CASE 710
• General Purpose Applications:
CATV
TV Tuning
AM/FM Radios
Scanning Receivers
Two-Way Radios Amateur Radio
PIN ASSIGNMENT
28
27
• Low Power Consumption
26
• 3.0 to 9.0 V Supply Range
• On- or Off-Chip Reference Oscillator Operation
25
• Lock Detect Signal
• Dual Modulus/Parallel Programming
23
• 8 User-Selectable ...;- R Values - 8,64, 128,256,512,1024,1160,
2048
21
•
24
22
20
...;- N Range=3 to 1023, ...;- A Range=O to 63
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates
10
19
l'
18
12
17
13
16
14
15
BLOCK DIAGRAM
OSCout
LD
OSCin
r----------------------+----~------~ ~~~~~s
VDD=Pin 3
Vss=Pin2
A5
A3 A2
AO
NO
N2
This document contains information on a new product. Specifications and information herein
are sublect to change without notice
6·73
N4 N5
N7
N9
Note: NO through N9, AO through A5 and
RAO through RA2 have pullup resistors
not shown.
MC145152·1
MAXIMUM RATINGS* (Voltages Referenced to VSS)
VOO
Vin. Vout
lin. lout
IDO. ISS
Po
Tstg
TL
Value
Unit
-0.5 to + 10
V
Parameter
Symbol
OC Supply Voltage
Input or Output Voltage (DC or Transient)
-0.5 to VOO+0.5
V
Input or Output Current (DC or Transient). per Pin
±10
rnA
Supply Current. VOO or VSS Pins
±3O
rnA
500
mW
-65 to + 150
°C
260
°C
Power Oissipation. per Packaget
Storage Temperature
Lead Temperature (8-Second Soldering)
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however.
it is advised that normal precautions be
taken to avoid applications of any voltage
higher than maximum rated voltages to
this high-impedance circuit. For proper
operation it is recommended that Vin and
Vout be constrained to the range
VSS:S(Vin or Vout):SVOO·
Unused inputs must always be tied to
an appropriate logic voltage level (e.g .•
either VSS or VOOI.
* MaXimum
Ratings are those values beyond which damage to the deVice may occur.
tPower Oissipation Temperature Oerating:
Plastic "P" Package: -12 mW/oC from 65°C to 85°C
Ceramic" L" Package: No derating
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
-40°C
Characteristic
Symbol
Power Supply Voltage Range
Output Voltage
Vin""O V or VDD
10ut",,0p.A
VOO
o Level
1 Level
VOL
VOH
Input Voltage
o Level
Vout"" 0.5 V or VOO-O.5 V
(All Outputs Except OSCout)
VIL
1 Level
VIH
Output Current - Modulus Control
Source
Vout"" 2.7 V
Vout""4.6 V
Vou t",,8.5 V
Sink
Vout"" 0.3 V
Vout""OA V
Vout"" 0.5 V
IOH
Output Current - Other Outputs
Source
Vout""2.7 V
Vou t=4.6 V
V ou t=8.5 V
IOH
V out =0.3V
Vout=OA V
Sink
IOL
IOL
Vout =0.5 V
25°C
85°C
VDD
-
Min
Max
Min
Typ
Max
Min
Max
3
9
3
-
9
3
9
3
5
9
-
0.05
0.05
-
0.05
-
0.001
0.001
0.001
0.05
0.05
0.05
-
0.05
0.05
0.05
3
5
9
2.95
4.95
8.95
-
2.95
4.95
8.95
2.999
4.999
8.999
-
2.95
4.95
8.95
-
3
5
9
-
-
1.35
2.25
4.05
0.9
-
0.9
1.5
2.7
-
0.9
1.5
2.7
3
5
9
2.1
3.5
6.3
-
2.1
3.5
6.3
1.65
2.75
4.95
-
2.1
3.5
6.3
-
3
5
9
-0.60
-0.90
-1.50
-
-0.50
-1.5
-
3
5
9
1.30
1.90
3.80
-
3
5
9
-0.44
-
-0.64
3
5
9
0.44
0.64
1.30
-
-
-
-
-
1.5
2.7
-
Units
V
V
-
V
rnA
-0.30
-0.50
-0.80
-
-0.75
-2.0
-
-1.25
-3.2
-
1.10
1.70
5.0
6.0
10.0
-
3.30
-
0.66
1.08
2.10
-0.35
-0.51
-1.00
-1.0
-1.2
-2.0
-
-0.22
-0.36
-0.70
0.35
0.51
1.00
1.0
1.2
2.0
-
0.22
-
-
0.36
-
-
0.70
±5O
-
±1O
±25
-
±22
p.A
0.3
-
0.00001
0.1
1.0
p.A
-400
-
-90
-200
-
10
-
6
10
-
10
pF
800
1200
1600
-
-
-
400
800
1200
1600
1600
2400
3200
p.A
-
200
300
-
-
-
-
rnA
Input Current - fin. OSCin
lin
Input Current - Other Inputs
(with Pullups)
IIH
9
9
IlL
9
Input Capacitance
Cin
-
Quiescent Current
Vin=O V or VOO
10ut=0 p.A
IDO
3
5
9
-1.30
-
-
-
6-74
-
-
-
-
-170
MC145152·1
SWITCHING CHARACTERISTICS (T A = 25°C. CL = 50 pF)
Characteristic
Output Rise Time. Modulus Control (Figures 1 and 5)
Symbol
VOD
Min
Typ
Max
Units
tTLH
3
5
-
50
ns
-
30
Output Fall Time. Modulus Control (Figures 1 and 5)
tTHL
Output Rise and Fall Time. LD. "'V. tPR (Figures 1 and 5)
tTLH.
tTHL
Propagation Delay Time
fin to Modulus Control (Figures 2 and 5)
tpLH.
tpHL
Output Pulse Width
tWI",)
",R. ",V with fR in Phase With fV (Figures 3 and 5)
Input Rise and Fall Times
OSCin. fin IFigure 4)
t r • tf
9
-
20
115
60
40
3
5
-
60
34
30
ns
ns
9
-
25
17
15
3
5
-
60
40
9
-
30
140
80
60
3
5
-
125
80
50
ns
ns
9
-
55
40
25
3
25
100
175
5
9
20
10
60
40
100
70
3
5
-
-
20
5
2
9
-
2
0.5
-
5
/Ls
II
6-75
MC145152·1
GRAPH 1 - OSCin AND fin MAXIMUM FREQUENCY VERSUS TOTAL DIVIDE VALUE
GRAPH 18 - VDD=5V
GRAPH 1A - VDD =3 V
~
28
~
14
24
12r--r~--+--+--r-~~--+--+--r--r'~--+-~
u..
.;:;
o
0
E
E
E
;c
E
;c
~
~
.<
1
Total Divide Value
Total Divide Value
GRAPH 1C - VDD=9V
N
~
28~-r-4--+--+--r--r~--1__+--+-~~~r_1_~
26
I 24~~~--r--r~~~-r~--+--r~~~+-~~
~ 22H-~~·~r--r~--+--r~--+--r~~~+-~~
1
E
I
20
18 r_-t---+--t----t--
.~ 16r-~~--+__+--+-~--r_1__+--+_~~~r_~~
~141l• •
112fTotal Oivide Value
GRAPH 2 - OSCin AND fin MAXIMUM FREQUENCY VERSUS TEMPERATURE FOR
SINE AND SQUARE WAVE INPUTS
GRAPH28 - TOTALDIVIDEVALUE?6
GRAPH 2A - TOTAL DIVIDEVALUE=3, 4, OR 5
1. 12
~
1.09
~~
~;;
1.06
1.03
g'u
3V _
-
~
~~-
- ..... ~
~~
~ ~ 1.00
gS
§
~
§~
:<
c
.<~
1
........
0.97
0.94
0.91
0.88
0.85
0.82
0.79
1.063
3V
,,
1.056
1.049
\
g~
\
u:~ 1.042
\
\
5
V,
g'u
1.035
'c;~
9
V:\.
Q;N
1.028
gs
E'" 1.021
~~~
~~
r': ~
r'\.,
\
~ ~5V
3V
- 20
20
40
60
f'..
'"
~ '"
'9V
80
1.000
0.993
-40
Temperature (0 CI
3V
5V
9V
....... ~~
.<-
1
"
-40
.§ ~ 1.014
~ §
:<,fE 1.007
\
- 20
20
40
60
80
Temperature (0 CI
* DJt;] !abe!!ed "Typica!" is not to be used for desian r"rrnSflS but is intended as an indication of the lC's potential performance
6-76
MC145152·1
PIN DESCRIPTIONS
fin (Pin 1) - Input to the positive edge triggered + Nand
-+- A counters. fin is typically derived from a dual modulus
prescaler and is AC coupled into Pin 1. For larger amplitude
signals Istandard CMOS logic levels) DC coupling may be
used.
the beginning of a count cycle and will remain low until the
+ A counter has counted down from its programmed value.
At this time, modulus control goes high and remains high
until the + N counter has counted the rest of the way down
from its programmed value IN - A additional counts since
both + Nand -+- A are counting down durin\} the first portion
of the cycle I. Modulus control is then set back low, the
counters preset to their respective programmed values, and
the above sequence repeated. This provides for a total programmable divide value INT) N-P + A where P and P + 1
represent the dual modulus prescaler divide values respectively for high____
tf
* fr in phase with fv
FIGURE 5 - TEST CIRCUIT
Device
Under
~-c
Output
Test
6-78
VSS
MC145152·1
FIGURE 6
PHASE DETECTOR OUTPUT WAVEFORMS
fV
Feedback
(fin ...
Nl
~R
LJ
U
U
¢V
LOU
U
U
NOTE: The Po output state is approximately equal to either VOO or VSS when active. When not active, the output IS high impedance and the
voltage at that pin is determined by the low pass filter capacitor.
RECOMMENDED FOR READING:
Gardner, Floyd M, Phaselock Techniques (second edition!. New Vork, Wiley-Interscience, 1979
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition!. New York, Wiley-Interscience, 1980
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976
Egan, William F, Frequency SynthesIs by Phase Lock. New Vork, Wiley-Interscience, 1981
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice Hall, 1983
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
6-79
II
MC145152·1
B. The period of fvco divided by P must be greater than
the sum of the times:
a. Propagation delay through the dual modulus
prescaler.
b. Prescaler setup or release time relative to its
modulus control signal.
c. Propagation time from fin to the modulus control
output for the MC145152-1.
A sometimes useful simplification in the MC145152-1 programming code can be achieved by chOOSing the values for
P of 8, 16, 32 or 64. For these cases, the desired value for
Ntotal will result when Ntotal in binary is used as the program code to the -+- Nand -+- A counters treated in the following manner:
DUAL MODULUS PRESCALING
The technique of dual modulus prescaling is well established as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically. the approach allows relatively low-frequency programmable
counters to be used as high-frequency programmahl,'
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and performance that would otherwise result if a fixed (single
modulus) divider was used for the prescaler.
In dual modulus prescaling, the lower speed counters
must be uniquely configured. Special control logic is
necessary to select the divide value P or P + 1 in the prescaler
for the required amount of time (see modulus control definition). The MC145152-1 contains this feature and can be used
with a variety of dual modulus prescalers to allow speed,
complexity and cost to be tailored to the system requirements. Prescalers having P, P + 1 divide values in the
range of -7- 3/ -7- 4 to -;- 64/ -7- 65 can be controlled by the
MC145152-1.
Several dual modulus prescaler approaches suitable for
use with the MC145152-1 are given in Figure 7. The approaches range from the low cost -7- 15/ -7- 16, MC3393P
device capable of system speeds in excess of 100 MHz to the
MC12000 series having capabilities extending to greater than
500 MHz. Synthesizers featuring the MC145152-1 and dual
modulus prescaling are shown in Figures 8 and 9 for two
typical applications.
II
A. Assume the -+- A counter contains "b" bits where 2b
= P.
B. Always program all higher order -+- A counter bits
above "b" to zero.
C. Assume the -+- N counter and the -+- A counter (with all
the higher order bits above "b" ignored) combined into a single binary counter of 10+ b bits in length. The
MSB of this "hypothetical" counter is to correspond
to the MSB of -7- N and the LSB is to correspond to
the LSB of -+- A. The system divide value, Ntotal, now
results when the value of Ntotal in binary is used to
program the "New" 10+b bit counter.
FIGURE 7 - HIGH FREQUENCY DUAL MODULUS
PRESCALERS FOR USE WITH THE MCl45152-1
DESIGN GUIDELINES APPLICABLE
TO THE MC145152-1
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
* MC12018
MC3393
The system total divide value (Ntotall will be dictated by
the application. i.e.
N
total -
frequency into the prescaler
frequency into the phase detector
=
N P A
• +
+51 +6
+81 +9
+ 101 + 11
+32/ +33
+40/+41
+ 64/ +65
+ 128/ + 129
+ 15/ + 16
440
500
500
225
225
225
520
140
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Min
Min
Min
Min
Min
Min
Min
Typ
* Proposed Introduction
N is the number programmed into the -7- N counter; A is
the number programmed into the -7- A counter. P and P + 1
are the two selectable divide ratios available in the two
modulus prescalers. To have a range of Ntotal values in sequence, the -+- A counter is programmed from zero through
P - 1 for a particular value N in the divide N counter. N is
then incremented to N + 1 and the -7- A is sequenced from
zero through P - 1 again.
There are minimum and maximum values that can be
achieved for Ntotal. These values are a function of P and the
size of the -7- Nand -7- A counters. The constraint N ~ A
always applies. If Amax = P - 1 then Nmin ~ P - 1. Then
Ntotal-min = (P-ll P+A or (P-l) P since A is free to
assume the value of zero.
Ntotal- max = Nmax • P + Amax
To maximize system frequency capability. the dual modulus
prescaler's output must go from low to high after each group
of P or P + 1 input cycles. The prescaler should divide by P
when its modulus control line is high and by P + 1 when its
modulus control is low.
For the maximum frequency into the prescaler (tvco max),
the value used for P must be large enough such that:
A. tvco max divided by P may not exceed the freqUency
capability of Pin 1 of the MC145152-1.
By using two devices. several dual modulus values are achievable:
Modulus
Control
.----i--.l *
~\...__De_V_ic_e_A_--,H
Device
DeVice
B
A
MC10131
MC10138
MC10154
MC12009
+ 20/ + 21
+501 +51
+40/+41
or
+801 +81
DeVice B
MC12011
+ 32/ + 33
+ 801 +81
+ 641 + 65
or
+ 1281 + 129
r-
MC12013
+40/ + 41
+ 1001 + 101
+ 801 + 81
NOTE: MC12009. MC12011 Anti MC12013 are Din equivalent.
MC12015. MC12016. and MC12017 are pin equivalent.
6-80
MC145152·1
FIGURE 8 - AIRCRAFT NAV RECEIVER SYNTHESIZER DEMONSTRATES
A LOW COST DUAL MODULUS SYSTEM EMPLOYING THE MC145152-1
VDD
Lock Detect Signal
28
LD
RAO
86.000 -
C
R2
95.950 MHz
I/>RI-'7-<~'\jR"I"""-'--I
Rl
VCO
I/>v~8:........c~v\"""'-9-f
VDD
Channel Programming
+N= 114 127, +A=O -
14
NOTES:
1. fR=50 kHz, + R=64; 22.0 MHz low side injection; NTOTAL= 1720 1919.
2. Using 22.0 MHz for the receiver I. F. demonstrates how the choice of I. F. value can sometimes reduce the number of + N bits that must be
programmed. Using the more common 21.4 MHz I.F. would require six rather than four + N programming inputs.
II
FIGURE 9 - SYNTHESIZER FOR LAND MOBILE RADIO UHF BAND
COVERAGE DEMONSTRATES USE OF THE MC145152-1
IN SYSTEMS OPERATING TO SEVERAL HUNDRED MHz
"1"
"0"
406 - 470 MHz
112.5 kHz Stepsl
"1"
Lock Detect Signal
VCO
Ref. Osc
MC145152-1
12.8 MHz
Modr9~>-________________
Cntd
lan-Chip Osc
Optionail
Channel Programming
~
+
NOTES:
1. NTOT AL = N.64 + A = 32480 to 37600; N = 507 to 587; A =
2. fR = 12.5 kHz, + R = 1024 (code 101).
64/
+
65 Dual Modulus Prescaler
°
to 63.
3. The prescaling approach can be chosen for the application to enhance economy e.g., Single chip MC3393P to approximately 100 MHz.
MC12011 or MC12013 with dual flip flop to approximately 250 MHz.
MC12011 or MC12013 with MC10178 to over 500 MHz.
6-81
MC145152·1
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers, The most desirable is discussed first.
the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input! output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:
USE OF A HYBRID CRYSTAL OSCILLATOR
CL = CinCout + Ca + CO+ ~
Cin + Cout
C1 + C2
Commercially available temperature-~ompensated crystal
oscillators (TXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies, An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin, In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-to-rail (VDD to VSS)
voltage swing, If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used, OSCout, an unbuffered output, should be left
floating,
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc" Component Products, 2553 N, Edgington St., Franklin Park, IL 60131, phone
(312) 451-1000.
where
Ca
Co
C1 and C2
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference si,gnal from the MECL device is ac
coupled to OSCin. For large amplitude signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier la digital inverter! along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD = 5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp,
Crystek Crystal
Statek Corp
5 pF (see Figure C)
6 pF (see Figure C)
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
External capacitors (see Figure A)
The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Couto
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified QV the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i,e. R1 =0 ohms,
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout, (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals,
Discussions with such manufacturers can prove very helpful.
See Table A.
DESIGN AN OFF-CHIP REFERENCE
TABLE A -
Cin
Cout
ADDRESS
3605 McCart St., Ft. Worth, TX 76110
1000 Crystal Dr" Ft. Myers, FL 33906
512 N, Main S\., Orange, CA 92668
PHONE
1817) 921-3013
18131 9362109
171416397810
RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.
D, Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro- Technologv, June, 1969,
Technical Note TN-7, Statek Corp.
P J. Ottowitz, "A Guide to Crystal Selection", Electronic
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb"
1969.
Design, May, 1966,
6-82
MC145152·1
FIGURE A -
PIERCE CRYSTAL OSCILLATOR CIRCUIT
----l
1- - - - -
Frequency
Synthesizer
I
I
I
I
I
I
I
I
I
--1
L_
OSC out
* May be deleted
In
certain cases. See text
FIGURE B -
EQUIVALENT CRYSTAL NETWORKS
RS
1
<>-I
0
2
~
LS
Cs
~
II
Co
Values are supplied by crystal manufacturer (parallel resonant crystal)
FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER
a
~
II
0----.,,...--- --11-I
I
:;:: Cln
.....-------.I---~O
II
I
_1_
I
,
::y:: Cout
I
_~_
6-83
®
MOTOROLA
MC145155·1
Advance Information
HIGH-PERFORMANCE
CMOS
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
The MC145155-1 is programmed by a clocked, serial input, 16-bit
data stream. The device features consist of a reference oscillator,
selectable-reference divider, digital-phase detector, 14-bit programmable divide-by-N counter and the necessary shift register and latch circuitry for accepting the serial input data. When combined with a loop
filter and VCO, the MC145155-1 can provide all the remaining functions
for a PLL frequency synthesizer operating up to the device's frequency
limit. For higher VCO frequency operation, a down mixer or a fixed
divide prescaler can be used between the VCO and MC145155-1.
The MC145155-1 offers improved performance over the MC145155.
The ac characteristics have been improved and the input current requirements have been modified.
• General Purpose Applications:
CATV
Two Way Radios
Scanning Receivers
AM/FM Radios
TV Tuning
Amateur Radio
• Low Power Consumption
• 3.0 to 9.0 V Supply Range
• On- or Off-Chip Reference Oscillator Operation with Buffered
Output
LOW-POWER COMPLEMENTARY MaS
SILICON GATE
SERIAL INPUT PLL
FREQUENCY SYNTHESIZER
MC145155Ll
MC145155Pl
CERAMIC PACKAGE
CASE 726
PLASTIC PACKAGE
CASE 707
• Compatible with the Serial Peripheral Interface (SPI) on CMOS
MCUs
PIN ASSIGNMENT
• Lock Detect Signal
• Two Open-Drain Switch Outputs
• 8 User-Selectable ...;- R Values - 16, 512, 1024, 2048, 3668, 4096,
6144,8192
18
17
16
• Single Modulus/Serial Programming
15
• ...;- N Range= 3 to 16383
• "Linearized" Digital Phase Detector Enhances Transfer Function
Linearity
13
• Two Error Signal Options Ended
14
12
Single Ended (Three-State) or Double
11
10
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates
VDD = Pin 5
BLOCK DIAGRAM
Vss=Pin7
os~"'~
OSCin 17
REFout 15
fin .;.9_ _ _,
R
v
~_-----+I
~--1:::::::~ SW2
Enabie .:..:12=---_ _ _ _~'-
SWl
Data 111L-_ _ _ _ _ _ _--I.r~~~..&..-..&..-..&..-"--"--"--"--'--'--'--"I
Clock -'..10"--_ _ _ _ _ _ _ _ _- - - - - - - - - - - - - - - - - - '
This document contains .information on a new product. Specifications and information herein
are subJect to change without notice
6-84
MC145155·1
MAXIMUM RATINGS* (Voltages Referenced to VSSI
VDD
Yin, V out
lin, lout
IDD' ISS
PD
Tstg
h
Value
Unit
-0.5 to + 10
V
Parameter
Symbol
DC Supply Voltage
-0.5 to VDD+0.5
V
Input or Output Current (DC or Transientl, per Pin
±10
mA
Supply Current, VDD or VSS Pins
±30
mA
500
mW
Input or Output Voltage (DC or Transientl
Power Dissipation, per Packaget
Storage Temperature
-65 to + 150
°C
260
°C
Lead Temperature (S-Second Solderingl
* MaXimum Ratings are those values beyond which damage to the deVice may occur
tPower Dissipation Temperature Derating:
Plastic "P" Package: -12 mW/oC from 65°C to S5°C
Ceramic "L" Package: No derating
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid applications of any voltage
higher than maximum rated voltages to
this high-impedance circuit. For proper
operation it is recommended that Yin and
V out be constrained to the range
VSSs(Vin or VoutlsVDD·
Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
either VSS or VDDI
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSSI
-40°C
Characteristic
Power Supply Voltage Range
Output Voltage
Vin=O V or VDD
10ut==0 p.A
o Level
1 Level
Input Voltage
oLevel
V ou t=0.5 V or VDD-0.5 V
(All Outputs Except OSCoutl
1 Level
Output Current V ou t=0.3V
Vout=OA V
V ou t=05 V
SW1, SW2
Output Current Vout=2.7V
V ou t=46 V
V ou t=S5 V
Other Outputs
Source
85°C
VDD
Min
Max
Min
Typ
Max
Min
Max
VDD
-
3
9
3
-
9
3
9
V
VOL
3
5
-
-
0.05
0.05
0.05
0.05
0.05
0.05
V
-
0.001
0.001
0.001
-
9
0.05
0.05
0.05
3
5
9
2.95
4.95
S.95
-
2.95
4.95
S.95
2.999
4.999
S.999
-
2.95
4.95
8.95
3
5
9
-
-
1.35
2.25
4.05
0.9
1.5
2.7
-
-
0.9
1.5
2.7
3
5
9
2.1
3.5
6.3
-
2.1
3.5
6.3
1.65
2.75
4.95
-
-
-
2.1
3.5
6.3
-
3
5
9
O.SO
1.50
3.50
-
OA8
0.90
2.10
3.0
3.6
6.0
-
0.24
OA5
1.05
-
3
5
9
-0.44
-064
-1.30
-
-0.35
-0.51
-1.00
-1.0
-
-1.2
-
-
-2.0
-
-0.22
-0.36
-0.70
3
5
9
0.44
0.64
1.30
-
1.0
-
VOH
VIL
VIH
-
-
-
-
-
-
-
-
-
-
Sink
-
-
0.9
1.5
2.7
V
-
mA
-
-
-
mA
IOH
IOL
Units
-
IOL
Sink
V out =03V
Vout=OA V
V ou t=0.5 V
25°C
Symbol
-
-
0.35
0.51
1.00
1.2
-
2.0
-
0.22
0.36
0.70
-
Input Current -
Data, Clock
lin
9
-
±03
-
± 0.00001
±01
-
± 1.0
p.A
Input Current -
fin, OSCin
lin
9
-
±50
-
±1O
±25
-
±22
p.A
IIH
9
-
0.3
-
0.00001
0.1
-
1.0
p.A
IlL
9
-
-400
-
-90
-200
-
-170
Cin
Cout
-
-
10
-
6
10
-
10
pF
-
-
10
-
6
10
-
10
pF
Quiescent Current
Vin=O V or VDD
lout= 0 p.A
3-State Leakage Current - PD out
Vout=O V or 9 V
IDD
3
5
-
-
1600
2400
3200
p.A
IOZ
g
-
±03
-
SOO
1200
1600
-
-
200
300
400
-
9
SOO
1200
1600
-
-
± 00001
±01
--
±30
p.A
Off-State Leakage Current SW1, SW2 - V out =9 V
IOZ
9
-
0.3
-
0.0001
0.1
-
3.0
p.A
Input Current - Other Inputs
(with Pullupsl
Input Capacitance
3-State Output Capacitance PD out
6-85
-
II
MC145155·1
SWITCHING CHARACTERISTICS IT A = 25°C, CL = 50 pF)
Characteristic
Output Rise and Fall Time (Figures 1 and 7)
Propagation Delay Time
Enable to SW1, SW2 (Figures 2 and 7)
Symbol
VOO
Min
Typ
Max
Units
tTLH,
tTHL
3
5
-
140
80
60
ns
9
60
40
30
3
5
-
40
25
15
100
40
25
ns
tPHL
Setup Times
Data to Clock (Figure 3)
tsu
9
-
3
5
30
20
18
12
10
-
9
-
70
32
25
30
16
12
-
12
12
15
-8
-6
-5
-
5
10
20
-15
-8
0
25
20
10
100
60
40
175
100
70
ns
-
20
5
2
5
/ls
0.5
40
35
25
30
20
15
9
Clock to Enable (Figure 3)
3
5
9
Hold Time
Clock to Data (Figure 3)
th
3
5
9
Recovery Time
Enable to Clock (Figure 3)
trec
Output Pulse Width
q,R, q,V with IR in Phase With IV (Figures 4 and 7)
twq,
Input Rise and Fall Times
Any Input (Figure 5)
t r , tl
3
5
9
3
5
9
3
5
9
,..----
Input Pulse Width, Clock, Enable (Figure 6)
tw
3
5
9
I
6-86
ns
-
-
ns
-
ns
-
2
-
-
ns
MC145155·1
GRAPH 1 -
OSCin AND fin MAXIMUM FREQUENCY VERSUS TOTAL DIVIDE VALUE
GRAPH 1B - VDD=5V
GRAPH 1A - VDD=3V
1
16
~
u..
12
10
i
1
1
I
/
1 I
-'_/
Typical"
"../
~ ...-
Cl
E
§
1
1
'x
~
x
1
1
I
J_
•. [.<
3
;; 26
24~~-1~+--+~r-~~~~-+~r--r'Mr-~~
22~~-1~+--+~~-r~r-4--+~r--r;~r-~~
//
./
20f-~~~+-~~~-r.~~+--+~~~;~r-~~
81
"
.-l
1/'1./
b'
4
25°C
28
r
V-
.,,-/
Guaranteed
1
,...
1
f- TI\-25°C
--Square Wave. VDD'VSS
14 1--_ - Sine Wave. 500 mV . ~
pp
~.
t··;/
5
Total Divide Value
~
18f-~~__~-+~~~~--+--+~~~;~f-~~
o
E
16f--r~~~~~~-~~~+--+~~~'~f-~~
~
12
§
x
~~
~~
14f--r-+--~-r-4--+
f-~---I~+---+:
x 10
j
8
Ma
6
Total Divide Value
GRAPH 1C - VDD=9V
~
28~-r-1~+--+~r--r~~-r-1~+--+~~r--r~
~ 26
24~~~--~-r-1~~~~--4--+--~'~-+~
~ 22 ~---+---t-=-~-+--+--+-~~r-4--+--I-o+--+~
1
20
E 18f--r-4--+--+-
II
~ 16f-~---I~+--+~+--+~~-r~~+--+~~+---+~
~ 14f--+:~~
1
12
r-----H"~~fu
Total Divide Value
GRAPH 2 -
OSCin AND fin MAXIMUM FREQUENCY VERSUS TEMPERATURE FOR
SINE AND SQUARE WAVE INPUTS
GRAPH 2B - TOTAL DIVIDE VALUE~6
GRAPH 2A - TOTAL DIVIDE VALUE=3, 4, OR 5
1.12
g
g.
1.09
a; 1.06
~~
1.03
~~
g
3V _
~~-
- --,
1.063
,
g~
....." ~
1.00
E 0.97
~
~] 0.94
":
1
0.88
~
"- ,
0.85
'3 V
"
0.82
0.79
~r.-..5V
-40
-20
20
40
60
1.042
.~~
1.035
gs
1.028
E"C
1.021
Ii
1.007
l
1.000
x-
~9V
5 V,
,,
,,
,
\
\
\
",
"- f'.,.
'"
3V
5V
9V
"r-::.::.~
0.993
-40
80
\
9V \
1.014
::;;~
-20
20
40
60
Temperature lOCI
Temperature lOCI
* Data
1.049
U:~
~N
~~
~ ~ 0.91
x~
3V
1.056
labelled "Typical" is not to be used for deSign purposes. but is Intended as an indication of the Ie's potential performance
6-87
80
MC145155·1
PIN DESCRIPTIONS
RAO, RA1, RA2 (Pins 18,1, and 2) - These three inputs
establish a code defining one of eight possible divide values
for the total reference divider, as defined by the table below:
Reference Address
Code
RAO
RA1
RA2
Total
Divide
Value
0
0
0
0
16
0
1
512
0
0
1
1
1
0
1
1024
1
1
1
0
0
0
1
1
1
0
1
CLOCK, DATA (Pins 10 and 11) - Shift register clock and
data input. Each low-to-high transition clocks one bit into
the on-chip 16-bit shift register. The data is presented on the
DAT A input at the time of the positive clock transition. The
DAT A input provides programming information for the
14-bit + N counter and the two switch signals SWl and
SW2. The entry format is as follows:
N Counter Bits-------1~~
Ul
Ul
2048
-1
:2
3668
z
z
t
6144
8192
Last Data Bit in (Bit No. 16)
First Data Bit
In
,j
(Bit No.1)
ENABLE (Pin 12) - When high ("1") transfers contents of
the shift register into the latches, and to the programmable
counter inputs, and the switch outputs SWl and SW2.
When low ("0") inhibits the above action and thus allows
changes to be made in the shift register data without affecting the counter programming and switch outputs. An onchip pull-up establishes a continuously high level for
ENABLE when no external signal is applied to Pin 12.
SW1, SW2 (Pins 13 and 14) - SWl and SW2 provide
latched open drain outputs corresponding to data bits
numbers one and two. These will typically be used for band
switch functions. A logic one will cause the output to
assume a high-impedance state, while a logic zero will cause
an output logic zero.
Positive power supply.
PDout (Pin 6) - Three state output of phase detector for
use as loop error signal. Double-ended outputs are also
available for this purpose (see fR or fV Leading: Negative Pulses.
Frequency fV < fR or fV Lagging: Positive Pulses.
Frequency fV = fR and Phase Coincidence: High-Impedance State.
VSS (Pin 7) -
N
~
S
Ul Ul
I
·1
4096
¢V, ¢R (Pins 3 and 4) - These phase detector outputs
can be combined externally for a loop error signal. A singleended output is also available for this purpose (see PDout).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by ¢V pulsing
low. ¢R remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by ¢R pulsing
low. ¢v remains essentially high.
If the frequency of fV = fR and both are in phase, then
both ¢V and
Rcr--
R2
Vcr-C
I
S(R1C + R2C) + 1
C)
II
PD out 0 - Ro----J~~--~--~
vO---~~,---,-~
c
>----<>VCO
Assuming gain A is very large, then:
I
R2CS + 1
F(s) = - - - R1 CS
NOTE: Sometimes R1 is split into two series resistors each R1 -+ 2. A capacitor Cc is then placed from the midpoint to ground to further filter
V and ¢R· The value of Cc should be such that the corner frequency of this network does not significantly affect Wn.
OEFINITIONS: N = Total Oivision Ratio in feeaback loop
KIP = VOO/411' for POout
KIP = VOO/2 ... for tl-V and cl>R
KVCO = 21r.1fVCO
.1VVCO
for a typical design Wn ==
2~dr
(at phase detector input),
r;: ,
RECOMMENDED FOR READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley-Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley-Interscience, 1980.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley-Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983.
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kiniey, Haroid, The PLL Synthesizer Cook.book:. Blue Ridge Summit, PA, Tab Books, 1980.
6-90
MC145155·1
FIGURE 8
PHASE DETECTOR OUTPUT WAVEFORMS
fR
Reference
(Osc -<- RI
fV
Feedback
(fin -<- NI
Po
Out
V
NOTE: The
Po output state is equal to either VOD or VSS
when active. When not active, the output is high impedance and the voltage at that
pin is determined by the low pass filter capacitor.
6-91
II
MC145155·1
FIGURE 9 -
UHF/
VHF
Tuner
Or
CATV
Front
End
TV/CATV TUNING SYSTEM
MC12071
Prescaler
D
C
I
o
c
k
CMOS
MPU/MCU
LED Displays
FIGURE 10 -
FMI AM RADIO SYNTHESIZER
II
2.56 MHz
FM
OSC
+-
MC3393
16 Prescaler
To AM/FM
Oscillators
MC1451551
D
1/2 MC1458
C
I
o
c
AM
OSC
k
CMOS
MPU/MCU
6-92
To Display
MC145155·1
CRYSTAL OSCILLATOR CONSIDERATIONS
the area of 8 to 15 M Hz, and 10 pF for higher frequencies
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input! output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable is discussed first
USE OF A HYBRID CRYSTAL OSCILLATOR
CL=CinCout +Ca+CO+ Cl.C2
Cin + Cout
Cl + C2
Commercially available temperature-~0mpensated crystal
oscillators (TXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-to-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OS Cout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Products, 2553 N. Edgington S1., Franklin Park, I L 60131, phone
(312) 451-1000.
where
Ca
Co
Cl and C2
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference signal from the MECL device is ac
'coupled to OSCin. For large amplitude signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD=5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp
Crystek Crystal
Statek Corp
5 pF (see Figure C)
6 pF (see Figure C)
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
External capacitors (see Figure A)
The oscillator can be "trimmed" on-frequency by making
a portion or all of Cl variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time
In some cases, stray capacitance should be added to the
values for Cin and Couto
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified tw the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency
Rl in Figure A limits the drive level. The use of Rl may not be
necessary in some cases; i.e. Rl =0 ohms
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or Rl must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R 1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful
See Table A.
DESIGN AN OFF-CHIP REFERENCE
TABLE A -
Cin
Cout
ADDRESS
3605 McCart St, Ft. Worth, TX 76110
1000 Crystal Dr, Ft Myers, FL 33906
512 N. Main St, Orange, CA 92668
PHONE
18171921-3013
18131 9362109
17141 639-7810
RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro-Technologv, June, 1969
Technical Note TN-7, Statek Corp.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb,
1969.
6-93
I
MC145155·1
FIGURE A -
PIERCE CRYSTAL OSCILLATOR CIRCUIT
r-
Rf
I
I
I
I
I
I
_ _ _ _ _ _ _ _ ..J
I
IL_
OSCin
OSCout
C11: 7:
C2
* May be deleted in certain cases. See text.
FIGURE B -
EQUIVALENT CRYSTAL NETWORKS
RS
I
1
~
LS
Cs
~
0r--<>
2
Co
Values are supplied by crystal manufacturer (parallel resonant crystall.
FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER
a
o
~
11
--11--
I
I
_L
-T-
Cin
..--------,I~---O
I
I
::r:
I
I
_J._
_1_
6-94
Cout
®
MOTOROLA
MC145156·1
Advance Information
HIGH-PERFORMANCE
CMOS
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
The MC145156-1 is programmed by a clocked, serial input, 19-bit data
stream. The device features consist of a reference oscillator, selectablereference divider, digital-phase detector, 10-bit programmable divide-by-N
counter, 7-bit programmable divide-by-A counter and the necessary shift
register and latch circuitry for accepting the serial input data. When combined with a loop filter and VCO, the MC145156-1 can provide all the remaining functions for a PLL frequency synthesizer operating up to the
device's frequency limit. For higher VCO frequency operation, a down
mixer or a dual modulus prescaler can be used between the VCO and
MC145156-1.
The MC145156-1 offers improved performance over the MC145156.
Modulus Control output drive has been increased and the ac
characteristics have been improved. Input current requirements have also
been modified.
• General Purpose Applications:
CATV
Two-Way Radios
AM/FM Radios
TV Tuning
Scanning Receivers
Amateur Radio
•
•
•
•
Low Power Consumption
3.0 to 9.0 V Supply Range
On- or Off-Chip Reference Oscillator Operation with Buffered Output
Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
•
•
•
•
Lock Detect Signal
Two Open-Drain Switch Outputs
Dual Modulus/ Serial Programming
8 User-Selectable -+- R Values - 8,64, 128,256,640, 1000, 1024,2048
•
-+- N Range==3 to 1023, -+- A Range=O to 127
• "Linearized" Digital Phase Detector Enhances Transfer Function
Linearity
• Two Error Signal Options: Single Ended (Three-State)
Double Ended
LOW-POWER COMPLEMENTARY MOS
SILICON-GATE
SERIAL INPUT PLL
FREQUENCY SYNTHESIZER
-I
1
MC145156L1
MC145156P1
CERAMIC PACKAGE
CASE 732
PLASTIC PACKAGE
CASE 738
PIN ASSIGNMENT
RAl
RAO
RA2
OSCin
R~
VCO
V~
Clock
."
q>
o
.6
Data
Enable
.12
.13
~
:r::
.J::o.
RfT
MC10131
Dual F/F
Channel
Selection
To
Display
MC12013
........
..---
----~------
+40/ +41 Dual Modulus Prescaler
NOTES:
1) for NAV: FR =50 kHz, + R =64 using 10.7 MHz lowside injection, Ntotal= 1946-2145
for COM-T FR = 25 kHz, + R = 128 using 21.4 MHz highside injection, Ntotal = 4720-5439
for COM-R FR =25 kHz, + R = 128 using 21.4 MHz highside injection, Ntotal = 5576-6295
2) A + 32/ + 33 dual modulus approach is provided by substituting an MC12011 (+ 8/ + 9) for the MC12013. The devices are pin equivalent.
3) A 6.4 MHz oscillator crystal can be used by selecting + R = 128 (code 010) for NAV and + R = 256 (code 011) for COM
s:
(')
......
,J::Io.
c.n
......
en
cp
......
FIGURE 11 - FMI AM BROADCAST RADIO SYNTHESIZER
,-----_ _ _-'••
~?~~apetect
• + 12
' - - - - - - - -•• FM B +
' - - - - - - - -•• AM B +
Optional
Loop
Error Signal
'1>
o
(Jl
~
R~
-= 1~7REFout
VCO
MC145156-1
VDD
V~
Mod Control ~
7 VSS
::::c
Cf11
Df12
E+13
I
a
n
o
t
a
cab
k
I
To
Display
NOTE 1:
for FM: channel spacing = 25 kHz, -+- R = -+- 128 (code 010)
for AM: channel spacing = 5 kHz, -+- R = -+- 640 (code 100)
II
MC145156·1
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable is discussed first.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-compensated crystal
oscillators (TXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-to-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Products, 2553 N. Edgington St., Franklin Park, IL 60131, phone
(312) 451-1000.
I
DESIGN AN OFF-CHIP REFERENCE
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference signal from the MECL device is ac
cOCJpled to OSCin. For large amplitude signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD=5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
TABLE A -
CL= CinCout + Ca + CO+ ~
Cin+ Cout
C1 + C2
where
Cin
Cout
Ca
Co
C1 and C2
5 pF (see Figure C)
6 pF (see Figure C)
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
External capacitors (see Figure A)
The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Cout.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified by the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i.e. R1 =0 ohms.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A.
PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp.
Crystek Crystal
Statek Corp.
the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC inputloutput capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:
ADDRESS
3605 McCart St., Ft. Worth, TX 76110
1000 Crystal Dr., Ft. Myers, FL 33906
512 N. Main St., Orange, CA 92668
PHONE
1817) 921-3013
(813) 936-2109
(714) 639-7810
RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro- Technology, June, 1969.
Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.
6-106
MC145156·1
FIGURE A - PIERCE CRYSTAL OSCILLATOR CIRCUIT
r- -----------l
I
Rf
Frequency
Synthesizer
I
I
I
I
I
iL _ _ _
I
_
_ _ _ _ _ _ _ -.J
OSC out
o
Rl*
1-+----J\Jv"v--ol
* May be deleted in certain
cases. See text.
FIGURE B - EQUIVALENT CRYSTAL NETWORKS
RS
1
0---4
LS
Cs
~
01--0
2
II
Co
Values are supplied by crystal manufacturer (parallel resonant crystal).
FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER
a
o
tfro
II
I
I
_L Cin
-T-
--11--
- - - - - - - r l- - - - 0
I
I
I
:;:: ~out
I
_J._
_J._
6-107
®
MC145157·1
MC145158·1
MOTOROLA
Advance Information
HIGH-PERFORMANCE
CMOS
SERIAL INPUT PLL FREQUENCY SYNTHESIZERS
The MC145157-1 and MC145158-1 have fully programmable 14-bit
reference counters, as well as fully programmable -+- N (MC145157-1)
and -+- NI -+- A (MC145158-1l counters. The counters are programmed
serialiy through a common data input and latched into the appropriate
counter latch, according to the last data bit (control bit) entered.
When combined with a loop filter and VCO, these devices can provide all the remaining functions for a PLL frequency synthesizer
operating up to the device's frequency limit. For higher VCO frequency
operation, a down mixer or a fixed-divide prescaler can be used
between the VCO and the PLL for the MC145157-1 and a dual-modulus
prescaler for the MC145158-1.
The MC145157-1 and MC145158-1 offer improved performance over
the MC145157 and MC145158. Modulus Control output drive has been
increased and the ac characteristics have been improved. Input current
requirements have also been modified.
I
LOW-POWER COMPLEMENTARY MOS
SILICON-GATE
SERIAL INPUT PLL
FREQUENCY SYNTHESIZER
dinr
t6
~r 1f 1111
MC1451S7L1
MC14S1SSL1
MC14S1S7Pl
MC14S1SSPl
CERAMIC PACKAGE
CASE 620
PLASTIC PACKAGE
CASE 648
• General Purpose Applications:
CATV
AM/FM Radios
Two-Way Radios
TV Tuning
Scanning Receivers
Amateur Radio
• Low Power Consumption
• 3.0 to 9.0 V Supply Range
•
Fully Programmable Reference and -+- N Counters
•
-+- R Range= 3 to 16383
•
-+- N Range= 3 to 16383 for the MC145157-1
PIN ASSIGNMENT
MC14S1S7-1
= 3 to 1023 for the MC145158-1
• Dual Modulus Capability for the MC145158-1
-+- A Range=O to 127
• fv and fr Outputs
• Lock Detect Signal
• Compatible with the Serial Peripheral Interface (SPI) on CMOS
MCUs
•
•
"Linearized" Digital Phase Detector
Single-Ended (Three-State) or Double-Ended
Outputs
Phase
Detector
OSCin
cf>R
OSCout
cf>V
tv
REFout
fR
VDD
PD out
S/R out
VSS
Enable
LD
Data
fin
Clock
MC14S1SS-1
OSCin
cf>R
OSCout
cf>V
fv
VDD
PDout
vSS
ThiS IS advance information and specifications are subject to change without notice
6-108
II II
t
REFout
tR
Modulus
Control
Enable
LD
Data
fin
Clock
MC145157·1, MC145158·1
MC145157-1
Enable....:,....:.,-------t--.......---r----...,
OSC . . :,_ _ _~
In 2
OSCout~'4------·
REFout"':""':"'---O<
hL-----~.r-.1-I~~~~I-L-'--I-L1-_4_------....:.'~2 S/R out
Clock..:::9~~-----------+------------'
MCl45158-1
Enable
..,:'..:..'------+-+--,---....
II
OSCin '
OSCou~ -=-2_ _ _~
REF
out
. . :'. .;,4_ _-0<:
l-Bit
Control
SIR
VDD= Pin 4
VSS=Pin6
6-109
MC145157-1, MC145158-1
MAXIMUM RATINGS* (Voltages Referenced to VSS)
VDD
Vin, Vout
lin, lout
100, ISS
Po
Tstq
TL
Value
Unit
-0.5 to + 10
V
Parameter
Symbol
DC Supply Voltage
-0.5 to VDD+0.5
V
Input or Output Current IDC or Transient), per Pin
±10
mA
Supply Current, VDD or VSS Pins
±30
mA
500
mW
Input or Output Voltage (DC or Transient)
Power Dissipation, per Packaget
Storage Temperature
-65 to + 150
°C
260
°C
Lead Temperature (S-Second Soldering)
This device contains circuitry to protect
the inputs against damage due to high
siatic voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid applications of any voltage
higher than maximum rated voltages to
this high-impedance circuit. For proper
operation it is recommended that Vin and
Vout be constrained to the range
VSSslVin or Vout)sVDD
Unused inputs must always be tied to
an appropriate logic voltage level Ie. g.,
either VSS or VDD)
* Maximum Ratl(lgs are those values beyond which damage to the device may occur
tPower Dissipation Temperature Derating:
Plastic "P" Package: -12 mW/oC from 65°C to 85°C
Ceramic "L" Package: No derating
ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSS)
-40°C
Characteristic
Power Supply Voltage Range
Output Voltage
Vin=O V or VDD
10ut"'0 /l- A
o Level
1 Level
Input Voltage
oLevel
V ou t=05 V or VDD-05 V
(All Outputs Except OSC out )
1 Level
II
Output Current Vout =2.7 V
V out =46 V
V out =85 V
Modulus Control
Source
V out =03V
V out =04 V
V out =05 V
Output Current V out =2.7 V
V out =46 V
V out =8.5 V
Sink
Other Outputs
Source
V out =03V
V out =04 V
V out =05 V
Sink
25°C
85°C
Symbol
VDO
Min
Max
Min
Typ
Max
Min
Max
VDO
-
3
9
3
-
9
3
9
V
VOL
3
5
9
-
0.05
0.05
0.05
-
0.05
0.05
0.05
-
0.05
0.05
0.05
V
-
0.001
0.001
0.001
3
5
9
2.95
4.95
S.95
-
2.95
4.95
8.95
2.999
4.999
S.999
-
2.95
4.95
8.95
3
5
9
-
0.9
1.5
2.7
-
1.35
2.25
4.05
0.9
1.5
27
3
5
9
2.1
3.5
6.3
-
2.1
3.5
6.3
1.65
2.75
4.95
-
3
5
9
-0.60
-0.90
-1.50
-0.50
-0.75
-1.25
-1.5
- 2.0
- 3.2
-
3
5
9
1.30
1.90
3.S0
1.10
170
3.30
5.0
6.0
10.0
-
3
5
9
-0.44
-0.64
-1.30
-0.35
-0.51
-1.00
-1.0
-1.2
-20
-
3
5
9
0.44
0.64
1.30
0.35
0.51
1.00
1.0
1.2
2.0
VOH
VIL
VIH
-
-
-
-
-
-
-
-
-
-
-
-
-
0.9
1.5
2.7
2.1
3.5
6.3
-
-0.30
- 0.50
-O.SO
-
-
mA
-
-
-
-
0.66
LOS
2.10
-
-
mA
IOH
IOL
V
-
IOH
IOL
Units
-
-
-0.22
-0.36
-0.70
0.22
0.36
0.70
-
-
Input Current - Data, Clock, Enable
lin
9
-
±03
-
± 0.00001
±01
-
± 10
/l- A
Input Current - fin, OSCrn
lin
9
--
±50
-
±10
± 25
-
±22
/l- A
Cin
Cout
-
-
10
-
6
10
-
10
pF
-
-
10
-
6
10
-
10
pF
100
3
5
9
-
-
SOO
1200
1600
-
1600
2400
3200
/l- A
-
200
300
400
-
-
Soo
1200
1600
9
-
±03
-
± 00001
±01
-
±30
/l- A
Input Capacitance
3-State Output Capacitance PDout
Quiescent Current
Vin=O V or VDO
10ut=0 /l- A
3-State Leakage Current - PD out
Vout=O V or 9 V
IOZ
-
6-110
-
-
MC145157-1, MC145158-1
SWITCHING CHARACTERISi"ICS ITA = 25°C, CL = 50 pFI
Characteristic
Symbol
Output Rise Time, Modulus Control I Figures 2 and 81
tTLH
Output Fall Time, Modulus Control (Figures 2 and 81
tTHL
VDD
3
5
Min
Typ
Max
Units
-
115
60
40
ns
9
50
30
20
25
17
15
60
34
30
ns
60
40
30
140
80
60
ns
55
40
25
125
80
50
ns
3
5
9
Output Rise and Fall Time, LD, fV, fR, S/R out , q,V, q,R IFigures 2 and 81
tTLH,
tTHL
3
5
9
Propagation Delay Time
fin to Modulus Control I Figures 3 and 81
Setup Times
9
-
tsu
3
5
30
20
18
12
10
9
-
70
32
25
30
16
12
-
12
12
15
-8
-6
-5
-
5
10
20
-15
-8
0
-
100
60
40
175
100
70
ns
9
25
20
10
3
5
-
5
2
0.5
/1S
-
-
9
3
5
9
th
3
5
9
Recovery Time
Enable to Clock (Figure 41
tree
Output Pulse Width
q,R, q,V with fR in Phase with fV (Figures 5 and 81
twq,
Input Rise and Fall Times
Any Input IFigure 61
t r , tf
3
5
9
tw
3
5
9
-
20
5
2
3
5
40
35
25
30
20
15
9
6-111
-
3
5
Clock to Enable (Figure 41
Input Pulse Width, Enable, Clock IFigure 71
-
-
tpLH,
tpHL
Data to Clock IFigure 41
Hold Time
Clock to Data (Figure 41
-
-
ns
-
-
-
ns
-
ns
-
-
ns
II
MC145157-1, MC145158-1
GRAPH 1 -
OSCin AND fin MAXIMUM FREQUENCY VERSUS TOTAL DIVIDE VALUE
GRAPH 1A - VDD=3V
GRAPH 1B - VDD=5V
~
::r::
~
14
~
2B
26
..t
22
24~4--+--+--+--~4-~~~-+~--~'r+--+-~
20~4--+--+-~~~~~--+--+~r-~'r+--+-~
~
10~~~~+-~~~~~--+--+--~~'r4--+-~
lB~~~~~-+--hr~-+--+--+~r-~'r+--+-~
o
E
o
E
16~4-74--~~~~4--+--+--+~~~'r+--+-~
~
~
12~4--+~+--t
E
;c
E
;c
x
14~4--+--+--+--~4-~
x 10
1
1
8
Max
Total Divide Value
Total Divide Value
GRAPH lC - VDD=9V
~
28~-+~--+--+--+--+~--4--+--+--+~~~~~
~ 26
I 24~~~--+--T--~~~r-4--+--+--+~~r-4-~
~ 22~-r~'~+--+--+--+~r-4--+--+--+'~r-~~
!
E
20
1Br--+-+--+--+-
~ 16~~~~+--+--+--+-'~4--+--+--+~~~~~
I
~
14
112
Total Divide Value
GRAPH 2 -
OSCin AND fin MAXIMUM FREQUENCY VERSUS TEMPERATURE FOR
SINE AND SQUARE WAVE INPUTS
GRAPH2B - TOTALDIVIDEVALUE2>:6
GRAPH 2A - TOTAL DIVIDE VALUE=3, 4, OR 5
1.12
~
§..,
..t ~
i~
g£
1.09
1.06
1.03
3V _
~~--
- ---
1.00
0,97
----
----
1.063
3V
1.056
1.049
g~
~~ 1.042
~
~
E
c
x~
1
~~
""' ........
~~
~, ~
~] 0.94
~
0.91
[',.
0.88
0.85
,
~r:-...5V
'3 V
!t
~:iE
l
"
0.82
0.79
5 V,
1.035
:;;N 1.028 9 V
C§-S
E'" 1.021
x-
\
\
\
\
\
\
1\ ,
1.014
1.007
\
,
"
,
i"'--. '"
1.000
0.993
3V
5V
9V
......... ~ .....
1\9 V
-40
- 20
20
40
60
80
-40
- 20
20
40
60
BO
Temperature (OCI
Temperature lOCI
* Data labelled "Typical" is not to be used for design purposes, but is intended as an Indication of the ICs potential performance
6-112
MC145157·1, MC145158·1
PIN DESCRIPTIONS
For the following text, the dash number has been omitted
from the part number for simplicity
INPUTS
OSCin, OSCout (Pins 1, 2) - These pins form an on-chip
reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of
appropriate value must be connected from OSCin to ground
and OSCout to ground. OSCin may also serve as the input
for an externally-generated reference signal. This signal will
typically be AC coupled to OSCin, but for larger amplitude
signals (standard CMOS-logic levelsl DC coupling may also
be used. In the external reference mode, no connection is required to OSC out .
fin (Pin 8) - Input frequency from VCO output. A rising
edge signal on this input decrements the ~ N counter (-;- A
or -;- N counter for the MC145158). This input has an inverter
biased in the linear region to allow use with AC signals as low
as 500 mV p-p or with a square wave of VDD to VSS
Clock, Data (Pins 9, 10) - Shift register clock and data input. Each low-to-high transition of the clock shifts one bit of
data into the on-chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic
one selects the reference counter latch and a logic zero
selects the -;- N counter latch (-;- A, -;- N counter latch for the
MC145158). The data entry format IS as follows
MC145157
MC145158
~
0
u
+
+
Rand + N Data Input
R Data Input
ro
ro
Ul
~
2
First Data Bit Into ~
Shift Register
MC145158 - A,
+
~ A
~
0
u
ro
~
N Data Input
., ..
N-------'.~,
ro ro
Ul
2
~
First Data Bit Into ~
Shift Register
OUTPUTS
fR, tv (Pins 13, 3)
Divided reference and fin frequency
outputs. The fR and fV outputs are connected internally to
the -;- Rand -;- N counter outputs respectively, allowing the
counters to be used independently, as well as monitoring the
phase detector inputs.
PDout (Pin 5) - Single ended (three-state) phase detector
output. This output produces a loop error signal that IS used
with a loop filter to control a VCO. This phase detector output is described below and illustrated in Figure 9
Frequency fV> fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High-Impedance
State
cPR, cPV (Pins 16, 15) - Double-ended phase detector outputs. These outputs can be combined externally for a loop
error Signal. A single-ended output is also available for thiS
purpose (see PDout)
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by cPV pulsing
low. cPR remains essentially high (see Figure 9 for
illustration)
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by cPR pulsing
low; cPV remains essentially high
If the frequency of fV = fR and both are In phase, then
both ct>v and cPR remain high except for a small minimum
time period when both pulse low in phase
S/Rout (Pin 12 of the MC145157) - Shift register output.
This output can be connected to an external shift register to
provide band switching, control information, and counter
programming code checking
Modulus Control (Pin 12 of the MC145158) - Modulus
control output. This output generates a Signal by the on-chip
control logic circuitry for controlling an external dual
modulus prescaler. The modulus control level will be low at
the beginning of a count cycle and will remain low until the
-;- A counter has counted down from its programmed value
At this time, modulus control goes high and remains high
until the -;- N counter has counted the rest of the way down
from its programmed value (N - A additional counts since
both -;- Nand -;- A are counting down during the first portion
of the cycle). Modulus control is then set back low, the
counters preset to their respective programmed values, and
the above sequence repeated. This provides for a total programmable diVide value (NT) = N· P + A where P and P +
1 represent the dual modulus prescaler divide values respectively for high and low modulus control levels, N the number
programmed into the -;- N counter and A the number programmed into the -;- A counter. Note that when a prescaler is
needed, the dual modulus version offers a distinct advantage. The dual modulus prescaler allows a higher reference
frequency at the phase detector Input, increasing system
performance capability, and SimplifYing the loop filter
design
LD (Pin 7) - Lock detect signal. ThiS output IS at a high
logic level when the loop IS locked (fR, fV of same phase and
frequency), and pulses low when the loop is out of lock
REF out (Pin 14) - Buffered reference OSCillator output
This output can be used as a second local oscillator,
reference oscillator to another frequency syntheSizer, or as
the system clock to a microprocessor controller
CONTROLS
Enable (Pin 11) - Latch Enable Input. A logic high on this
pin latches the data from the shift register Into the reference
divider or -;- N, - A latches depending on the control bit. The
reference diVider latches are activated If the control bit IS at a
logic high and the -;- N, ~ A latches are activated If the control bit IS at a logic low. A logic Iowan thiS pin allows the
user to change the data in the shift registers without affecting the counters
DUAL MODULUS PRESCALING
The technique of dual modulus prescallng IS well established as a method of achieving high performance frequency
6-113
II
MC145157-1, MC145158-1
synthesizer operation at high frequencies. Basically, the approach allows relatively low-frequency programmable
counters to be used as high-frequency programmable
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and performance that would otherwise result if a fixed (single
modulus) divider was used for the prescaler.
In dual modulus prescaling, the lower speed counters
must be uniquely configured. Special control logic is
necessary to select the divide value P or P + 1 in the prescaler
for the required amount of time (see modulus control definition). The MC145158 contains this feature and can be used
with a variety of dual modulus prescalers to allow speed,
complexity and cost to be tailored to the system requirements. Prescalers having P, P + 1 divide values in the
range of -+- 3/ -+- 4 to ... 128/ -+- 129 can be controlled by the
MC145158.
Several dual modulus prescaler approaches suitable for
use with the MC145158 are given in Figure 1. The approaches range from the low cost .... 15/ -+- 16, MC3393P
device capable of system speeds in excess of 100 MHz to the
MC12000 series having capabilities extending to greater than
500 MHz.
b. Prescaler setup or release time relative to its
modulus control Signal.
c. Propagation time from fin to the modulus control
output for the MC145158.
A sometimes useful simplification in the MC145158 programming code can be achieved by choosing the values for P
of 8, 16, 32, 64 or 128. For these cases, the desired value for
Ntotal will result when Ntotal in binary is used as the program code to the -+- Nand ... A counters treated in the
following manner:
A. Assume the ->- A counter contains "b" bits where 2b =
P.
B. Always program all higher order ... A counter bits
above "b" to zero.
C. Assume the -+- N counter and the -+- A counter (with all
the higher order bits above "b" ignored) combined into a single binary counter of 10+ b bits in length. The
MSB of this "hypothetical" counter is to correspond
to the MSB of -\- N and the LSB is to correspond to the
LSB of ... A. The system divide value, Ntotal, now
results when the value of Ntotal in binary is used to
program the "New" 10+ b bit counter.
DESIGN GUIDELINES APPLICABLE
TO THE MC145158
FIGURE 1 - HIGH FREQUENCY DUAL MODULUS
PRESCAlERS FOR USE WITH THE MCl45158
The system total divide value (Ntotal) will be dictated by
the application, i.e.
II
+5/+6
+81 +9
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
* MC12018
MC3393
frequency into the prescaler
Ntotal= frequency into the phase detector = N·P+ A
N is the number programmed into the -+- N counter; A is
the number programmed into the .... A counter. P and P + 1
are the two selectable divide ratios available in the two
modulus prescalers. To have a range of Ntotal values in sequence, the -+- A counter is programmed from zero through
P-1 for a particular value N in the .... N counter. N is then incremented to N + 1 and the .... A is sequenced from zero
through P-1 again.
There are minimum and maximum values that can be
achieved for Ntotal. These values are a function of P and the
size of the .... Nand -+- A counters. the constraint N ~ A
always applies. If Amax = P - 1 the Nmin ~ P - 1. Then
N(total- min) = (P-1) P+ A or (P-1) P since A is free to
assume the value of zero.
* Proposed
+
101 + 11
+321 +33
+401 +41
+641 +65
-;. 128/ + 129
+ 151 + 16
440
500
500
225
225
225
520
140
a. Propagation delay through the dual modulus
prescaler.
Min
Min
Min
Min
Min
Min
Min
Typ
Introduction 1983
By USing two devices several dual modulus values are achievable:
Modulus
Control
,------1--~---,* ~ *
~
Device A
H
Device B
N(total- max) = Nmax·P + Amax
To maximize system frequency capability, the dual modulus
prescaler's output must go from low to high after each group
of P or P + 1 input cycles. The prescaler should divide by P
when its modulus control line is high and by P + 1 when its
modulus control is low.
For the maximum frequency into the prescaler (Fvcomax),
the value used for P must be large enough such that:
A. fvco max divided by P may not exceed the frequency
capability of Pin 8 of the MC145158.
B. The period of fvco(max), divided by P, must be greater
than the sum of the times:
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Device
Device
B
A
MC10131
MC10138
MCI0154
r--
MCI2009
MC12011
MC12013
+201 + 21
+321 + 33
+50/ + 51
+80/ +81
+401 +41
+ 100/ + 101
+40/ +41
+64/ +65
or
+ 128/ + 129
or
+80/ +81
+80/ +81
NOTE: MC12009, MCI2011 and MCI2013 are pin equivalent.
MC12015, MC12016. and MC12017 are pin equivalent.
6-114
MC145157-1, MC145158-1
SWITCHING WAVEFORMS
FIGURE3
FIGURE2
lTHL
~---VOO
Any
Output
Modulus
Control
FIGURE 4
FIGURE 5
~~~~-------tw¢------~1~r---Data
¢R,¢V*-
50%\. .__________,
tsu
* fR In phase with fV
Clock
Vss
-
Enable
VOO
~----- VSS
II
Previous
Data
Latched
FIGURE 7
FIGURE6
Enable,
Clock
Any Input
t.--____
----..t
-",-L~
-VOO
t_w_-_-_-_------
50%
VSS
FIGURE 8 -
TEST CIRCUIT
Output
Device
Under
Test
MC145157-1, MC145158-1
FIGURE 9
PHASE DETECTOR OUTPUT WAVEFORMS
IV
Feedback
(fin'" Nl
PD Out
y'-------'r-----U~-----+-----
u
u
~V
II
u
u
NOTE: The Po output state is approximately equal to either VOO or VSS when active. When not active, the output is high impedance and the
voltage at that pin is determined by the low pass filter capacitor.
6-116
MC145157-1, MC145158-1
PHASE LOCKED LOOP - LOW PASS FILTER DESIGN
AI
PDout O
"VV'v
I
I
Rl
oveo
C
~Ro-~vo--
,+ ,
Fls) = R1 CS
BI
PDouto-----~~~~--~------oVCO
Wn =
r = 0. 5w n fR2e + __N_)
~Vo--
'\
Fisl
CI
KKVCO
R2CS + 1
PD out 0 - R1
~R
II
>----<---0 veo
~v
R1
e
Assuming gain A is very large, then:
I
NOTE: Sometimes Rl is split into two series resistors each Rl -;- 2. A capacitor Cc is then placed from the midpoint to ground to further filter
V and R. The value of Cc should be such that the corner frequency of this network does not significantly affectwn.
DEFINITIONS: N = Total Division Ratio in feedback loop
K4> = VOO/4 ... for PDout
K~ = VDD/2 ... for ~V and ~R
KVCO = 211'4fveo
4VVCO
for a typical design Wn ;:
r;:
2~ofr
lat phase detector inputl,
1
RECOMMENDED FOR READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley-Interscience, 1979 .
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley-Interscience, 1980.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley-Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983.
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
6-117
MC145157-1, MC145158-1
CRYSTAL OSCILLATOR CONSIDERATIONS
the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input! output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable is discussed first.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-~I)mpensated crystal
oscillators (TXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-to-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Products, 2553 N. Edgington St., Franklin Park, I L 60131, phone
(312) 451-1000.
II
CL=CinCout +Ca+CO+ C1·C2
Cin + Cout
C1 + C2
where
Co
C1 and C2
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD= 5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp.
Crystek Crystal
Statek Corp.
5 pF (see Figure C)
6 pF (see Figure C)
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
External capacitors (see Figure A)
The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Cout·
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified t'" the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i.e. R1 = 0 ohms.
To verify that the maximum de supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or Rl must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of Rl.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A.
DESIGN AN OFF-CHIP REFERENCE
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference signal from the MECL device is ac
coupled to OSCin. For large amplitude signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.
TABLE A -
Cin
Cout
Ca
ADDRESS
3605 McCart St., Ft. Worth, TX 76110
1000 Crystal Dr., Ft. Myers, FL 33906
512 N. Main St., Orange, CA 92668
PHONE
(817) 921-3013
(813) 936-2109
(714) 639-7810
RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro-Technology, June, 1969.
Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit - Definiti"ons and
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.
6-118
MC145157-1, MC145158-1
FIGURE A -
PIERCE CRYSTAL OSCILLATOR CIRCUIT
r- -----.
------l
Rf
I
Frequency
Synthesizer
I
I
I
I
I
_ _ _ _ _ _ _ --1
I
:L _ _ _
_
OSC out
o
C1.T .T C2
R1*
i---+--.....JV\I'\r---'
* May
be deleted in certain cases. See text.
FIGURE B -
EQUIVALENT CRYSTAL NETWORKS
RS
1
~
0r-o
2
Cs
LS
~
II
Co
Values are supplied by crystal manufacturer (parallel resonant crystal).
FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER
a
Bba
II
O~"'Ir---_--II--
I
I
:;=:
-----~i- - - - 0
II
Cin
I
_1_
I
I
::r:
I
_~_
6-119
Cout
®
MC145159·1
MOTOROI.A
Advance Information
HIGH-PERFORMANCE
CMOS
LOW-POWER COMPLEMENTARY MOS
SILICON-GATE
SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH
ANALOG PHASE DETECTOR
SERIAL INPUT PLL FREQUENCY
SYNTHESIZER WITH
ANALOG PHASE DETECTOR
The MC145159-1 has a programmable 14-bit reference counter, as
well as programmable divide-by-NI divide-by-A counters. The counters
are programmed serially through a common data input and latched into
the appropriate counter latch, according to the last data bit (control bit)
entered.
When combined with a loop filter and VCO, this device can provide
all the remaining functions for a PLL frequency synthesizer operating up
to the device's frequency limit. For higher VCO frequency operations, a
down mixer or a dual modulus prescaler can be used between the VCO
and the PLL.
-
MC145159Pl
20
• General Purpose Applications:
CA TV
TV Tuning
AMI FM Radios
Scanning Receivers
Two Way Radios Amateur Radio
1
• Low Power Consumption
-+- R Range= 3 to 16383
•
-+- N Range= 16 to 1023, -+- A Range=O to 127
RR
OSCin
VDD'
OSC out
• Dual Modulus
• Compatible with the Serial Peripheral Interface (SPI) on CMOS
MCUs
•
PIN ASSIGNMENT
RO
• 3.0 to 9.0 V Supply Range
• On- or Off-Chip Reference Oscillator Operation
II
PLASTIC PACKAGE
CASE 738
CH
Charge
APDout
VDD
Frequency
Steering Out
VSS'
CR
VSS
SRout
Modulus Control
Enable
• High-Gain Analog Phase Detector
LD
Data
fin
Clock
Enable _1_3_ _ _ _ _ _ _--,
14
OSC out - - - - - - - - - - ,
18
CH
RR
RO
15
CR
17
APD out
19
VDD'
16
VSS'
20
fR
Analog
Phase
Detector
SR out
Charge
VDD= Pin 5
VDD' = Pin 19
Vss=Pin7
VSS' = Pin 16
Modulus Control
6*
Clock -
* Note:
....- - - - - - -....---------4~--------......I
Pin 6 is not and cannot be used as a digital phase detector output.
This document contains information on a new product. Specifications and information herein
are subiect to change without notice
6-120
Frequency Steering Out
MC145159·1
MAXIMUM RATINGS* (Voltages Referenced to VSS)
VOO
Yin, Vout
lin, lout
IDO, ISS
PD
T stg
TL
Value
Unit
-0.5 to + 10
V
Parameter
Symbol
OC Supply Voltage
- 0.5 to VOO + 0.5
V
Input or Output Current (DC or Transient), per Pin
±10
mA
Supply Current, VDD or VSS Pins
±30
mA
Power Dissipation, per Packaget
500
mW
-65 to + 150
°C
260
°C
Input or Output Voltage (OC or Transient)
Storage Temperature
Lead Temperature (8-Second Soldering)
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid applications of any voltage
higher than maximum rated voltages to
this high-impedance circuit. For proper
operation it is recommended that Yin and
V out be constrained to the range
VSS:s(Vin or Vout):sVDD·
Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
either VSS or VDO)·
* Maximum
Ratings are those values beyond which damage to the device may occur
tPower Dissipation Temperature Derating'
Plastic "P" Package: -12 mW/oC from 65°C to 85°C
Ceramic "L" Package: No derating
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
-40°C
Characteristic
Power Supply Voltage Range
Output Voltage
Vin=O V or VDD
10ut""0 p.A
oLevel
1 Level
6Voltage, VCH - VAPD out
IAPD out ",,0 p.A
Input Voltage
oLevel
V ou t=05 V or VDD-05 V
(All Outputs Except OSC out )
1 Level
Output Current V out = 2.7 V
V ou t=4.6 V
V ou t=85 V
Modulus Control
Source
V out =0.3V
Vout=OA V
V ou t=0.5 V
Sink
Output Current, CR
VCR=45 V, RR=240 k
Output Current, APDout
Ro=240 k, VCH=O V
VAPDout=4.5 V
Output Current - Other Outputs
Source
V ou t=2.7V
V out =4.6 V
V ou t=8.5 V
V out =0.3V
Vout=OA V
V out =0.5 V
Sink
85°C
25°C
Symbol
VDD
Min
Max
Min
Typ
Max
Min
Max
Units
VDD
-
3
9
3
-
9
3
9
V
VOL
3
5
9
-
0.05
0.05
0.05
0.05
0.05
0.05
V
-
0.001
0.001
0.001
-
-
3
5
9
2.95
4.95
8.95
2.95
4.95
8.95
2.999
4.999
8.999
-
2.95
4.95
8.95
VOH
-
-
0.05
0.05
0.05
-
6V
-
VIL
3
5
9
-
3
5
9
2.1
3.5
6.3
-
3
5
9
-0.60
-0.90
-1.50
-
3
5
9
1.30
1.90
3.80
VIH
-
-
-
-
-
V
1.05
-
0.9
1.5
2.7
0.9
1.5
2.7
-
1.35
2.25
4.05
-
2.1
3.5
6.3
1.65
2.75
4.95
-
-0.50
-0.75
-1.25
-1.5
-2.0
-3.2
-
1.10
170
3.30
5.0
6.0
10.0
-
-
-
-
-
0.9
1.5
2.7
21
3.5
6.3
-
-0.30
-0.50
-0.80
-
-
-
mA
IOH
IOL
V
-
-
-
-
-
0.66
1.08
2.10
-
-
-
ICR
9
-100
-120
p.A
IAPD
9
170
350
p.A
mA
IOH
IOL
3
5
9
-0.44
-0.64
-1.30
-
3
5
9
0.44
0.64
1.30
-
-
-
-0.22
-0.36
- 0.70
-
-
-
0.22
0.36
0.70
-0.35
-0.51
-1.00
-1.0
-1.2
-2.0
-
0.35
0.51
1.00
1.0
1.2
2.0
-
-
-
-
-
Input Current - Data, Clock, Enable
lin
9
-
±03
-
±0.00001
±0.1
-
± 1.0
p.A
Input Current - fin, OSCin
lin
9
-
±50
-
±1O
±25
-
± 22
p.A
Cin
Cout
-
-
10
-
6
10
-
10
pF
-
-
10
-
6
10
-
10
pF
10D
3
5
9
-
800
1200
1600
-
800
1200
1600
1600
2400
3200
p.A
-
200
300
400
-
-
9
-
±03
-
±0.0001
±01
-
±30
p.A
Inpt:lt Capacitance
3-State Output Capacitance Frequency Steering Out
Quiescent Current
Vin=O V or VDD
10ut=0p.A
3-State Leakage Current
V out = 0 V or 9 V
IOZ
-
6-121
-
-
MC145159-1
SWITCHING CHARACTERISTICS (TA=25°C, CL =50 pF)
Characteristic
Output Rise Time, Modulus Control (Figures 3 and 8)
Output Fall Time, Modulus Control (Figures 3 and 8)
Symbol
VOO
Min
Typ
Max
Units
tTLH
3
5
-
50
30
20
115
60
40
ns
60
34
30
ns
140
80
60
ns
125
80
50
ns
-
ns
tTHL
Output Rise and Fall Time, LD (Figures 3 and 8)
tTLH,
tTHL
Propagation Delay Time
fin to Modulus Control (Figures 4 and 8)
tpLH,
tpHL
Setup Times
Data to Clock (Figure 5)
tsu
-
3
5
-
9
-
25
17
15
3
5
-
60
-
40
9
-
30
3
5
-
55
-
40
9
-
25
3
5
30
20
18
12
10
70
32
25
30
16
12
12
12
15
-8
-6
-5
-
5
10
20
-15
-8
-
a
-
-
20
5
2
5
2
0.5
fLs
30
20
15
-
ns
9
Clock to Enable (Figure 5)
3
5
9
Hold Time
Clock to Data (Figure 5)
th
3
5
9
Recovery Time
Enable to Clock (Figure 5)
trec
3
5
9
Input Rise and Fall Times
Clock, OSCin, fin (Figure 6)
tr,tf
3
5
9
Input Pulse Width, Enable, Clock (Figure 7)
tw
I
3
5
9
6-122
-
9
-
40
35
25
9
-
ns
-
ns
-
-
MC145159·1
PIN DESCRIPTIONS
INPUTS
OSCin, OSCILLATOR INPUT (PIN 2), OSCout,
OSCILLATOR OUTPUT (PIN 3) - These pins form an onchip reference oscillator when connected to terminals of an
external parallel resonant crystal. Frequency setting
capacitors of an appropriate value must be connected from
OSCin to VSS and OSCout to VSS. OSCin may also serve
as input for an externally generated reference signal. This
signal will typically be ac coupled to OSCin, but for larger
amplitude signals (standard CMOS logic levels), dc coupling
may also be used. In the external reference mode, no connection is required to OSCout.
fin, FREQUENCY IN (PIN 10) - Input to the positive edge
triggered divide-by-N and divide-by-A counters. fin is
typically derived from a dual modulus prescaler and is ac
coupled into Pin 10. This input has an inverter biased in the
linear region to allow use with ac-coupled signals as low as
500 mV peak-to-peak or direct-coupled signals swinging
from VDD to VSS·
Data, SERIAL DATA INPUT (PIN 12) - Counter and
control information is shifted into this input. The last data bit
entered goes into the one-bit control shift register. A logic
one allows the reference counter information to be loaded into it's 14-bit latch when Enable goes high. A logic zero
entered as the control bit disables the reference counter
latch. The divide-by-AI divide-by-N counter latch is loaded,
regardless of the contents of the control register, when
Enable goes high. The data entry format is shown below.
Enable, TRANSPARENT LATCH ENABLE (PIN 13) - A
high on this input allows data to be entered into the divideby-AI divide-by-N latch and, if the control bit is high, into the
reference counter latch. Counter programming is unaffected
when Enable is low.
Clock, SHIFT REGISTER CLOCK (PIN 11) - A low-tohigh transition on this input shifts data from the Serial Data
input into the shift registers.
COMPONENT PINS
CR, RAMP CAPACITOR (PIN 15) - The capacitor connected from this pin to VSS is charged linearly, at a rate
determined by RR. The voltage on this capacitor is proportional to the phase difference of the frequencies present at
the internal phase detector inputs. A polystyrene or mylar
capacitor is recommended.
RR, RAMP CURRENT BIAS RESISTOR (PIN 20) - A
resistor connected from this pin to VSS determines the rate
at which the ramp capacitor is charged, thereby affecting the
phase detector gain (see Figure 11.
CH, HOLD CAPACITOR (PIN 18) - The charge stored on
the ramp capacitor is transferred to the capacitor connected
from this pin to either VDD' or VSS'. The ratio of CR to CH
should be large enough to have no affect on the phase
detector gain (CR > lOCH). A low-leakage capacitor should
be used.
RO, OUTPUT BIAS CURRENT RESISTOR (pIN 1) - A
resistor connected from this pin to VSS biases the output
N-Channel transistor, thereby setting a current sink on the
Analog Phase Detector Output (Pin 171. This resistor adjusts
the VCO input voltage change with respect to phase error
(see Figure 2).
OUTPUTS
APDout, ANALOG PHASE DETECTOR OUTPUT (PIN 17)
- This output produces a voltage that controls an external VCO. The voltage range of this output (VDD = + 9 V) is
from below + 0.5 V to + 8 V or more. The source impedance
of this output is the equivalent of a source follower with an
externally variable source resistor. The source resistor
depends upon the output bias current controlled by the output bias current resistor, RO. The bias current is adjustable
from 0.01 mA to 0.5 mAo The output voltage will not be more
than 1.05 V below the sampled point on the ramp. With a
constant sample of the ramp voltage at 9 V and the hold
capacitor at 50 pF, the instantaneous output ripple is not
greater than 5 mV peak-to-peak.
Charge, RAMP CHARGE INDICATOR (PIN 4) - This output is high from the time fR goes high to the time fv goes
high (fR and fv are the frequencies at the phase detector inputs). This high voltage indicates that the ramp capacitor,
CR, is being charged.
Frequency Steering Out, THREE-STATE FREQUENCY
STEERING OUTPUT (PIN 6) - If the counted down input
frequency on fin is higher than the counted down reference
frequency of OSCin, this output goes low. If the counted
down VCO frequency is lower than that of the counted down
OSCin, this output goes high.
The repetition rate of the Frequency Steering Output
pulses is approximately equal to the difference of the frequencies of the two counted down inputs from the VCO and
DATA ENTRY FORMAT
Latched When
Control Bit= 1
Shift
Register
Data In
Out
Latched When
Control Bit = 0
Control Bit
6-123
II
MC145159·1
OSCin. The output maintains a high-impedance state when
the counted down VCO (divided down fin pulse) and the
counted down OSCin are in a one-to-one ratio over a 271" window with respect to the counted down OSCin.
LD, PHASE LOCK INDICATOR (PIN 9) - This output is
high during lock and goes low to indicate a non-lock condition. The frequency and duration of the non-lock pulses will
be the same as either polarity of the Frequency Steering Output.
Modulus Control, DUAL MODULUS PRESCALER CONTROL (PIN 8) - The modulus control level is low at the
beginning of a count cycle and remains low until the divideby-A counter has counted down from its programmed value.
At that time, the modulus control goes high and remains
high until the divide-by-N counter has counted the rest of the
way down from its programmed value (N - A additional
counts, since both divide-by-N and divide-by-A are counting
down during the first portion of the cycle). Modulus control
is then set back low, the counters preset to their respective
programmed values, and the above sequence is repeated.
This provides a total programmable divide value of
NT=N.P+A, where P and P+l represent the
FIGURE 1 -
a
100 0
700
500i
~ 300 I
FIGURE 2 -
" "
~ 300
9V
f-VOO-3 V 1--5 V
z
~ 20 0
....
C(
~ 70
0
~ 5
0
~ 0
....
I
,"
20
20 30
1
~ 100
I\.
5 7 10
J
V3
I'
"
~ 50
10I
:)
VCO BIAS VOLTAGE
100 0
70 0
S50 0
VoO-3~ ~5V- ~9''''
~ 100
!i 70
30
POWER PINS
VDD, POSITIVE POWER SUPPLY (PIN 5) - Positive
power supply input for all sections of the MC145159-1 except
the Analog Phase Detector. VDD and VDD' should be
powered up at the same time to avoid damage to the
MC145159-1.
VSS, NEGATIVE POWER SUPPLY (PIN 7) - Circuit
ground for all sections of the MC145159-1 except the Analog
Phase Detector.
VSS', ANALOG PHASE DETECTOR CIRCUIT GROUND
(PIN 16), VDD', ANALOG POWER SUPPLY (PIN 19) Separate power supply and ground inputs are provided to
help reduce the effects in the analog section of noise coming
from the digital sections of this device and the surrounding
circuitry.
CHARGE CURRENT vs RAMP RESISTANCE
~ 200I
ti
dual modulus prescaler divide values, respectively, for high
and low Modulus Control levels; N is the number programmed into the divide-by-N counter, and A is the number programmed into the divide-by-A counter.
SRout, SHIFT REGISTER OUTPUT (PIN 14) - This pin is
the non-inverted output of the inner-most bit of the 32-bit
Serial Data Shift Register. It is not latched by the Enable line.
5070100
200300500
"'l\.
10
o
lk I 2k 3k
ICHARGE, CHARGE CURRENT IJtA)
I
I
1I
I
I
J
1
V
2
ANALOG VOLTAGE OUT (VOLTS)
DESIGN EQUATION
icharge
Kq,= 21f fR CR
where Kq, = phase detector gain, icharge is from Figure 1
fR = reference frequency, CR = ramp capacitor (in farads)
6-124
MC145159·1
SWITCHING WAVEFORMS
FIGURE4
FIGURE3
tTHL
----\tOJ
-vss
Modulus
Control
FIGURE6
FIGURE5
tf
Clock
OSCin, fin
Data
VSS
VSS
tsu
Clock
II
VSS
-
Enable
VOO
VSS
Previous
Data
Latched
FIGURE8 - TEST CIRCUIT
FIGURE7
Enable,
Clock
JtooI~:::::::_-_-_tw_-------------~-:lc'" VOO
50%
VSS
6-125
Output
Device
Under
Test
MC145159·1
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable is discussed first.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-~<)mpensated crystal
oscillators nXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-to-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Products, 2553 N. Edgington St., Franklin Park, IL 60131, phone
(312) 451-1000.
DESIGN AN OFF-CHIP REFERENCE
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference si.gnal from the MECL device is ac
. coupled to OSCin. For large amplitude signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD=5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
the area of 8 to 15 M Hz, and 10 pF for higher frequencies
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be'
CL",CinCout +Ca+CO+ C1·C2
Cin + Cout
C1 + C2
where
= 5 pF (see Figure C)
= 6 pF (see Figure C)
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
C1 and C2
External capacitors (see Figure A)
The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Couto
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified tw the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i.e. R1 =0 ohms .
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A.
TABLE A - PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp.
Crystek Crystal
Statek Corp.
ADDRESS
3605 McCart St., Ft. Worth, TX 76110
1000 Crystal Dr., Ft. Myers, FL 33906
512 N. Main St., Orange, CA 92668
PHONE
(817) 921-3013
(813) 936-2109
(714) 639-7810
RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro-Technologv, June, 1969.
Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.
6-126
MC145159·1
FIGURE A -
PIERCE CRYSTAL OSCILLATOR CIRCUIT
r-
-
I
-F;:enCy
Synthesizer
I
I
l
I
I
I
_ _ _ _ _ _ _ _ -.JI
I
IL_
OSCin
OSCout
o
C1I .T
Rl *
~--'VV'\r--'
* May
be deleted in certain cases. See text.
FIGURE B -
EQUIVALENT CRYSTAL NETWORKS
RS
101-0
2
~
C2
LS
Cs
~
II
Co
Values are supplied by crystal manufacturer (parallel resonant crystal).
FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER
a
~
II
O-.....I-----1--~ ~-I
I
==r= Cin
>--------.I---~O
I
I
=T= Cout
I
_1_
I
_1._
6-127
MC145159-1
FIGURE 9 - TIMING DIAGRAM FOR MINIMUM DIVIDE VALUE (N = 16)
~
____________~n~__________ __
~
~n~
'------________------'1
~~----------------------------------------------------~~~--------I
-----------------~~----~'---------~
------~
____________________________________________________
_J~
________________________________________________
6-128
~r__
CMOS Remote Control Functions
7-1
II
CMOS REMOTE CONTROL FUNCTIONS
Device
Number
Function
Transmitter
Receiver
Function
MCl4457
MCl4458
MCl4469
MCl4497
Remote Control Transmitter
Remote COiltrol Receiver
Addressable Asynchronous Receiver/Transmitter
PCM Remote Control Transmitter
MC145026
MC145027
MC145028
MC145029
Remote
Remote
Remote
Remote
Number of
Address Bits
0
0
Control
Control
Control
Control
Encoder
Decoder
Decoder
Decoder
Number of
Data Bits
5*
5*
Device
Number
Number
of Pins
Associated Device
Number(sl
MCl4457
MCl4458
16
24
MCl4458
MCl4457
MCl4497
18
MC3373
Encoder
Depends on Decoder
Depends on Decoder
MC145026
16
Decoder
Decoder
Decoder
5
9
4
4
0
5
MC145027
MC145028
MC145029
16
16
16
MC145027, MC145028,
MC145029
MC145026
MC145026
MC145026
Addressable UART
7
7/8
MCl4469
40
MCl4469, MC6850
Transmitter
0
6*
*These 5 or 6 bit codes specify commands or functions internal to the associated receiver devices
I
7-2
®
MCl4457
MCl4458
MOTOROLA
MC14457 TRANSMITTER
MC14458 RECEIVER
CMOS MSI/LSI
The MC14457 and MC14458 are a transmitter and receiver pair constructed in CMOS monolithic technology. These units are designed for
ultrasonic or infrared remote control of TV receivers, converters, communication receivers, and games. Selection of up to 16 channels may
be done single entry; or up to 256 channels may be done double entry.
The MC14457 encodes each keyboard position into frequencymodulated biphase data. This transmitter functions with a 20- to
32-position keyboard and provides either channel select/toggle information (single-word transmission I or analog information (continuous
transmission for the duration of key press). The MC14457 features low
standby power between data transmissions
(LOW-POWER COMPLEMENTARY MOSI
TRANSMITTER
RECEIVER
MCl4457 TRANSMITTER
iii
_I -
•
Low External Component Count
•
High Noise Immunity
•
One Analog Output from Receiver
•
•
Low Power
Operating Voltage Range: 4.5 to 10.0 V for MC14457
4.5 to 5.5 V for MC14458
---'
-
.
J',' I·.'
d
:
L SUFFIX
.
CERAMIC PACKAGE
CASE 620
P SUFFIX
16i~11I1\ \11\
PLASTIC PACKAGE
CASE 648
1\ 1\
1
MAXIMUM RATINGS* (Voltages Referenced to VSSI
MCl4458 RECEIVER
Symbol
Value
Unit
VDD
-0.5to+12
-0.5 to +6.0
V
Input Voltage, All Inputs
Yin
DC Input Current, Per Pin
lin
-05 to VOD+05
±10
TA
Tstg
-40 to +85
°C
L SUFFIX
-60 to + 150
°C
CERAMIC PACKAGE
CASE 623
Rating
DC Supply Voltage
MCl4457
MCl4458
Operating Temperature Range
Storage Temperature Range
V
mA
* Maximum Ratings are those values beyond which damage to the device may
occur
PIN ASSIGNMENTS
MCl4457
TRANSMITTER
R3
R4
R5
R2
Ri
Cf
C2
VSS
1.
VDD
Os c in
ORDERING INFORMATION
VDO
Out 2
Data In
Out 1
POR
A3
Mod
AFT
A2
On
A1
OS C out
11
MCl4458
RECEIVER
OSCin
C3
C4
Vol
UHF/VHF
AO
LBV
VA
M8
Data Ready
M4
L8
M2
L4
M1
L2
VSS
L1
7-3
MC14XXX
l
Suffix
Denotes
Ceramic Package
Plastic Package
This device contains circuitry to protect the inputs against damage due to high static voltages or
electric fields; however, it is advised that normal
precautions be taken to avoid application of any
voltage higher than maximum rated voltages to
this high impedance circuit. For proper operation,
it is recommended that Yin and Vout be constrained to the range VSS':::;(Vin or Vout)~VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or
VODl.
II
MC14457, MC14458
TRANSMITIER- MC14457
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
Output Voltage
Vin= VOD or 0
"0" Level
"1" Level
lout=O/lA
Input Voltage #
(VO=4.5 or 0.5 V)
(Vo=9.00rl.0V)
"0" Level
"1" Level
VOL
VOH
Pins 14, 15
Source
(VOL =2.5V)
(VOL =0.5 V)
Sink
Output Drive Current - Pin 13
(VOH=4.6V)
Source
(VOH=9.5 V)
(VOL =OAV)
(VOL =0.5 V)
Sink
-40°C
Min
25°C
+85°C
Max
Min
Typ
Max
Min
Max
Unit
0.05
0.05
-
0
0
0.05
0.05
-
0.05
0.05
V
-
4.95
9.95
-
V
5.0
10
-
5.0
10
4.95
9.95
-
4.95
9.95
5.0
10
-
5.0
10
-
1.5
3.0
-
2.25
4.50
1.5
3.0
-
1.5
3.0
5.0
10
3.5
7.0
-
3.5
7.0
2.75
5.50
-
3.5
7.0
-
5.0
10
-6.0
-3.2
-
-5.0
-2.6
-9.0
-4.5
-
-3.5
-1.8
-
5.0
10
6.0
3.2
-
5.0
2.6
9.0
4.5
-
3.5
1.8
-
5.0
10
-0.26
-0.6
-
-0.22
-0.55
-0.44
-1.12
-
-
-
-0.18
-0.45
-
5.0
10
0.26
0.6
0.44
1.12
-
0.18
-
-
022
0.55
-
-
-
-
-
-
V
VIL
-
V
VIH
(VO= 0.5 or 4.5 V)
(VO= 1.0 or 9.0 V)
Output Drive Current (VOH=2.5V)
(VOH=9.5 V)
Voo
V
-
-
mA
IOH
IOL
-
-
-
mA
IOH
IOL
mA
-
-
mA
50
500
1000
OA5
-
±03
-
±O.ooool
+0.3
-
-
-
-
5.0
7.5
-
-
pF
5.0
10
-
50
100
-
0.008
0.016
50
100
-
375
750
p.A
5.0
-
Input Current -
Pull-ups
lin
10
-
Input Current -
Pin 11
lin
10
-
Input Capacitance
Cin
-
Quiescent Current - Per Package
Oscin=O V, Other Inputs= Open,
lout= 0 /lA
Total Supply Current at an External
Load Capacitance (Cl) of Figure 4
f= 500 kHz (with any Analog
command)
IDD
-
-
-
+ 1.0
p.A
p.A
p.A
IT
10
-
-
-
-
Max
Min
0.05
-
-
-
-
-
-
Typ
Max
Min
Max
Unit
-
0
0.05
-
0.05
V
4.95
5.0
-
4.95
-
V
5.0
10
RECEIVER-MC14458
II
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Output Voltage
Vin=VDD or 0
10ut=0/lA
Input Voltage#
(VO=4.5 or 0.5 V)
(Vo=0.50r4.5VI
Output Drive Current
(VOH=2.5V)
-40°C
25°C
Symbol
VOO
V
"0" level
VOL
5.0
-
"1" Level
VOH
5.0
4.95
"0" Level
VIL
5.0
-
1.5
-
2.25
5.0
3.5
-
3.5
2.75
Characteristic
"1" level
VIH
Min
+ 85°C
V
1.5
-
-
1.5
3.5
-
V
mA
IOH
5.0
-0.5
-
-05
-1.7
-
-OA
IOL
5.0
OA5
-
0.78
-
0.34
Input Current (Oscin, Din)
lin
5.0
-
OA
-
+0.00001
+0.3
-
Input Current (POR)
lin
5.0
-
-
10
50
400
Input Capacitance
Cin
-
-
-
-
5.0
Quiescent Current, Per Package
POR = VDD, Other Inputs= VDD
or 0, 10ut=0 p.A
IDD
5.0
-
5.0
-
250
VHvs
5.0
-
0.25
-
-
-
V
5.0
-
-
-
IT
-
400
-
-
-
p.A
(VOL =OAV)
Source
Sink
Data Input Hysteresis
Total Supply Current at an External
Load Capacitance (CL) of Figure 6
f=500kHz
+0.3
#Noise immunity specified for worst-case input combination
Noise Margin for both "1" and "0" ieve;= 1.0 V rnif! @ VDD-5.0 V
2.0 V min @ VDD= 10 V
7-4
-
mA
+ 1.0
p.A
-
-
p.A
7.5
-
-
pF
1000
-
-
p.A
MC14457, MC14458
SWITCHING CHARACTERISTICS (MCl4457 - Transmitter VOO= 5 to 15 V MCl4458 - Receiver VOO= 5 V)
Symbol
Min
Typ
Max
Unit
Output Rise and Fall Time - Receiver
CL = 100 pF
Characteristic
tTLH.
tTHL
-
0.3
1.0
Jl.s
Oscillator Start-Up Time - Transmitter
ton
PRF
Clock Pulse Frequency
-
8.0
-
Jl.s
-
1500
600
kHz
MCl4457 - TRANSMITTER
Q
Shift
Register
AT
R2
R3
ROW!
Inputs
R4
R5
6
Colome {
Inputs
Ci
C2
10
C3
9
N
Pullup
Resistors
with
Keyboard
Encode
and
Oebounce
Modulation
Control
Mux
VOO= Pin 16
Vss=Pin8
Mod
(Oata Code)
II
7-5
MC14457, MC14458
FIGURE 1 -
EXAMPLE OF TRANSMITTED WORD
~
I
(~~~~:) I
Low Frequency
c:::J
High Frequency
IZZZ2I
I
----.J
VA rlTlI1 t'lA
PM
I LF*I
5-Bit Keyboard
Encoded Latched Data
I
VA
0 I 1 I 0 I 0 I 1 I 1 I 0 I
Zero One Funct LSB
LSB
LSB MSB
Start Start
+1
+2
-100 ms
4'
I
LF
I
I
•
* Low Frequency
FIGURE 2 -
DATA SIGNAL
(CLOCK
= 500 kHz)
Data
Signal
I
L...--_ILJ
Data _-:-_ _--:'-_--J
Code
6.656 _~__-.t..-...,....._6.144
ms
ms
12.8 ms
Bit Time
9983
ms
II
PreStart
Low F
Start
Bit
"0"
Start
Bit
"1"
Function
Bit
"0"
LSB
"0"
LSB+l
"1"
~ Start.pattern +tl.11{.....________
__
Fixed
LSB+2
"0"
MSB
"1"
End
Low F
I
command Pattern
-----+iVariable
.,..
MC14457 TRANSMITTER PIN DESCRIPTIONS
R1, R2, R3, R4, R5, ROW INPUTS (PINS 5, 4,1,2,3) These pins are the row inputs and are active in the low state.
On-chip pullup resistors are provided on each of these
inputs.
puts are at ground potential.
OSCin, OSCout, OSCILLATORS (PINS 11, 12) - These
pins are the input! output terminals of the oscillator. They
can be used with a ceramic resonator or crystal. The oscillator is automatically turned off after the data is transmitted
for low current quiescent operation.
If an external oscillator is used, a current limiting resistor
should be added, due to the presence of an internal pulldown device on the oscillator input.
6, C2, 5, C4, COLUMN INPUTS (PINS 6, 7, 10, 9)
These pins are the column inputs and are active in the low
state. On-chip pullup resistors are provided on each of these
inputs.
Out 1, Out 2, OUTPUTS (PINS 14, 15) - These pins provide push-pull output and can be used with ceramic transducers or LEOs. In the non-operating condition, both out-
Mod, MODULATION (PIN 13) - This pin is a data code
output. Note that there is no power-up reset.
7-6
MC14457, MC14458
TABLE 1 Key
Number
Operation
Row
Column
(Active Low) (Active Low)
DATA CODE
Transmitter Data and Receiver Output Address
MSB/A3
LSB+2/A2
LSB+ l/Al
LSB/AO
Function*
VA
Pulse
Notes
1
0
-
0
0
-
1
1
1
0
-
1
1
0
0
0
-
1
0
1
0
1
0
-
1
C1
0
1
1
0
0
-
1
R4
C2
0
1
1
1
0
-
1
R5
C1
1
0
0
0
0
1
R5
C2
1
0
0
1
0
-
Rl
C3
0
0
0
0
1
J/
2
14
t
Chan. Search t
Fine Tuning t
Fine Tuning t
15
Spare
16
Spare
17
Volume
18
Volume
1
Digit 0
R1
C1
0
0
0
0
0
2
Digit 1
R1
C2
0
0
0
1
3
Digit 2
R2
C1
0
1
4
Digit 3
R2
C2
0
0
0
5
Digit 4
R3
C1
0
6
Digit 5
R3
C2
7
Digit 6
R4
8
Digit 7
9
Digit 8
10
Digit 9
11
12
13
Chan. Search
t
t
1
1
R1
C4
0
0
0
1
1
J/
2
R2
C3
0
0
1
0
1
J/
3
R2
C4
0
0
1
1
1
J/
3
R3
C3
0
1
0
0
1
J/
3
R3
C4
0
1
0
1
1
J/
3
R4
C3
0
1
1
0
1
J/
3
R4
C4
0
1
1
1
1
J/
3
19
Mute on/off
R5
C3
1
0
0
0
1
J/
2
20
Off
R5
C4
1
0
0
1
1
J/
2
21
Digit 10
R2·R5
C1
1
0
1
0
0
-
1
22
Digit 11
R2·R5
C2
1
0
1
1
0
-
1
23
Digit 12
R3·R5
C1
1
1
0
0
0
-
1
24
Digit 13
R3·R5
C2
1
1
0
1
0
-
1
25
Digit 14
R2·R3·R5
C1
1
1
1
0
0
-
1
26
Digit 15
R2·R3·R5
C2
1
1
1
1
0
-
1
27
Spare
R2·R5
C3
1
0
1
0
1
J/
3
28
Spare
R2·R5
C4
1
0
1
1
1
J/
3
29
Spare
R3·R5
C3
1
1
0
0
1
J/
3
30
Spare
R3·R5
C4
1
1
0
1
1
J/
3
31
Spare
R2·R3·R5
C3
1
1
1
0
1
J/
3
32
Spare
R2·R3·R5
C4
1
1
1
1
1
J/
3
Notes:
1. Channel Select Keys (Function Bit = 0). Data is transmitted once each time a key is activated
2 Toggling type On/Off or counter advance type keys Data is transmitted once each time a key IS activated
3. Analog Up/ Down or On/ Off keys, i. e., one key for Down or Off and another key for Up or On Data transmission
key is operated.
IS
repeated as long as the
* The function bit is used only internally by the MC14458 receiver as a steering bit
In Table 1, all channel select data is noted by the function
bit equal to zero. For functions other than channel, the function bit equals one.
The four toggling or counter advance type keys that
transmit data once each time a key is activated are Mute,
Off, Channel Search Up, and Channel Search Down.
The twelve remaining analog keys (Vol, Tint, Color, etc)
transmit data as long as the key is activated. The keys' functions are arranged to provide the most typical application
without grounding of multiple row or columns required.
7-7
I
MC14457, MC14458
MCl4458 - RECEIVER
Data In_2_ _ _ _-l
Load
•
UHF/VHF
17 Data Ready
Q
4 AFT
Voo= Pin 24
VSS = Pin 12
I
MCl4458 RECEIVER PIN DESCRIPTIONS
Data Ready, DATA READY SIGNAL (PIN 17) - A
positive pulse with a duration of 768 P.s appears at Pin 17 of
the receiver approximately 0.1 second after a complete
command is entered on the remote control transmitter
keyboard. The negative going edge of this pulse may be used
for triggering purposes.
NOTE: A complete command is one digit in the single
entry mode or two digits in the double entry mode.
Data In, DATA INPUT (PIN 2) - The amplified ultrasonic
data signal (after amplification and limiting forms a square
wave with a peak-to-peak value of VOO) is applied to this input terminal.
OSCin, OSCILLATOR INPUT (PIN 1) - The oscillator input pin of the receiver is connected to an oscillator that provides, for example, a 500 kHz square wave signal. A typical
oscillator circuit is shown in Figure 5. Accuracy of one percent, relative to the oscillator frequency in the transmitter, is
recommended for satisfactory rerformance in very high echo
producing environments.
AFT, AUTOMATIC FINE TUNING ENABLE (PIN 4) - The
voltage level at this pin is low for a time duration of 0.393
seconds following a change in selected channel to allow
disabling the tuner AFT circuit. Also, miscellaneous commands 0000, 0001, 0010, and 0011 (Channel Search
Up/Down, Fine Tuning Up/Down) will cause this disable
feature.
L1, L2, L4, L8, Ml, M2, M4, M8, CHANNEL OUTPUTS
(PINS 13, 14, 15, 16, 11, 10, 9, 8) - The eight data output
pins provide latched data corresponding to the channel
selected on the transmitter keyboard. L1 through L8 are the
least significant bits; M 1 through M8 are the most significant
bits. The data on these pins is accompanied by a Data Ready
signal.
POR, POWER-ON RESET (PIN 3) - This pin is low for
power-on reset of the analog output t-o 0 pulse width and
off! on output to O. An internal pull-up device delivers 10 to
400 p.A to charge an external capacitor. Reset occurs until
the input voltage reaches 70 percent VDO. All internal
reyist81s will also be reset.
7-8
MC14457, MC14458
In the muted mode, the analog level is memorized and
cannot be varied by the up/ down controls on the
transmitter.
AD, A1, A2., A3, ADDRESS OUTPUTS (PINS 19, 20, 21,
22) - The address outputs of the receiver identify selected
analog and on/ off commands for use in system expansion.
The data on these lines is valid when accompanied by a Valid
Address pulse.
LBV, LOW BAND (PIN 7) - This pin will go HIGH
whenever channels 02, 03, 04, 05, or 06 are selected The
output is LOW for channels 00, 01, and 07 through 99.
VA, VALID ADDRESS (PIN 18) - A negative going pulse
with a duration of 768 /Ls appears at Pin 18 approximately 0.1
seconds after an analog on/ off key on the remote control
transmitter keyboard is operated. Either edge of this pulse
may be used for control of add-on circuits.
The Valid Address pulse is repeated every 102.4 ms for as
long as a key is operated which provides repeated transmission of data when held down.
The Valid Address signal may be used in conjunction with
the Address Outputs to drive memories to provide additional
control functions such as color, tint, etc
The Valid Address pulse may be used to provide a stepping clock for up/down counters in a memory. The least
significant address line (AO) is used to identify the up or
down mode, and the remaining address lines (A 1, A2, A3)
are decoded to enable each individual contra) circuit.
By adding up/ down counters to the Data Outputs, it is
possible to use the Valid Address pulse and a decoded address for implementing a channel up/down stepping function from the remote control. Additional On/Off functions
may be obtained by using the Valid Address pulse in combination with a decoded address for setting and resetting of
latches. The Valid Address Signal is disabled in the standby
mode (ON output at logical 0).
OPERATION
The receiver can be placed in a single-digit mode of operation by connecting the M4 data output (Pin 9) to VDD and
the UHF output (Pin 6) to VSS. In this mode, the L1 through
L8 channel outputs will change immediately after the entry of
a Single digit on the transmitter keys. The Ml through M8
outputs are not used in this mode (see Figure 6).
As one example of operation, a free-running ceramic
resonator oscillator (at 500 kHz), triggered by the depression
of any key, is divided by 12 or 13 to provide frequencies of
41.67 or 38.46 kHz. The transmitted data "zero" consists of
256 periods of the lower frequency followed by an equal
number of the higher frequency. Mark to space ratio is kept
at 1: 1 in each case. A data "one" reverses the order of the
two frequencies.
Rowand column information from the keyboard is encoded into a 5-bit word and loaded onto data latches on the
edge of transmit enable. This data, preceded by two bits, 0
and 1, is used in sequence to provide biphase control of the
divider and, consequently, the bit pattern transmitted from
the unit. Each 7-bit word begins and ends with a low frequency burst. Operation of a channel select key produces an
output data stream for a duration of approximately 100 ms.
UHFIVHF, ULTRA HIGH FREQUENCY IVERY HIGH FREQUENCY OUTPUT (PIN 6) - This pin of the receiver provides a low level when the selected channel is a VHF channel
(00 to 13, or 84 to 99). A high level on Pin 6 identifies selection of a UHF channel (14 to 83). This Signal is provided to
permit switching of VHF and UHF tuners
APPLICATIONS INFORMATION
Typical circuits for the transmitter and receiver chips are
shown in Figures 3 through 7.
The transmitters, with the keyboard shown, transmit the
first twenty codes from Table 1. The circuits of Figure 3
transmit via ultrasonic; whereas, the circuit of Figure 4
transmits infrared light. In Figure 3, a push-pull output at
Pins 14 and 15 allows a balance drive to the ceramic
microphone, which virtually doubles the transmitted power,
compared to a single-ended output.
The diagram in Figure 5 shows an amplifier connected to a
remote receiver. The bias resistor (photodiode) of the
amplifier requires bias. The bias voltage is determined by the
choice of photodiode and system considerations such as ambient light. Most of the required gain is realized using three
of the hex inverters in the MC14069UB package. A fourth inverter from the same package operates a 500 kHz oscillator
circuit.
Figure 6 shows a block diagram of a PLL system. The
receiver directly addresses a synthesizer. In this diagram, a
complete command consists of two channel digits fallowed
by an Enter code. The Enter code into the synthesizer is a
0101 in complementary logic. The transmitted code from the
transmitter is 1010, which is Function 10 from Table 1.
A block diagram of a tuning address system is shown in
Figure 7. This block diagram incorporates a one-chip microcomputer that would be programmed to the system's needs.
The system can be expanded up to 256 channels.
On, ON (PIN 5) - This pin of the receiver provides a low
level following operation of the Off command (1001) on the
remote-control transmitter. The signal on this pin changes to
a high level when a channel is selected.
Vol, VOLUME CONTROL (PIN 23) - An analog output
voltage in the range between 0 V and VDD is obtained by integrating the Signal at the Vol pin through a low-pass filter.
The analog voltage resolution has been chosen to be 64
steps. The value can be incremented or decremented in
steps of one by keys providing commands 0111 and 0110,
respectively (see Table 1).
This analog voltage can be varied up or down at a speed of
approximately 10 steps per second. The D/ A conversion is
performed with an underflow and an overflow limiting circuit. The Vol pin is normally used for the control of volume.
The first time power is applied to the remote-control
receiver, the volume output is 0 volts.
The Vol Signal may be increased after a channel has been
selected by operating the key providing a command 0111
(Volume Up).
The Vol signal may be muted by operating a key on the
transmitter providing command 1000. Return to the original
output prior to muting may be achieved by operating the
mute key a second time or by operating the volume-up key.
7-9
II
MC14457, MC14458
FIGURE 3 - TYPICAL ULTRASONIC SYSTEM
12
Ultrasonic
Ceramic
Microphone
__+-e-+-e-+-e-~~--_4~R2
MC14457
3 R5
C1 C2 C3 C4
6 7 10 9
--~~~--~~~~+---~
Note: CR is a ceramic resonator, Radio Materials Corp. type CR30 or equivalent.
FIGURE 4 - TYPICAL INFRARED SYSTEM
+6V
680
12
11
14
5 R1
15
4 R2
N.C.
330
.;r
MC14457
§
+6V
R3
<:t
0;
~
2 R4
3 R5
C1 C2 C3 C4
6 7 10 9
5O"F
-=
Note: CR is a ceramic resonator, Radio Materials Corp. type CR30 or equivalent.
7-10
MC14457, MC14458
FIGURE 5 - TYPICAL REMOTE CONTROL RECEIVER CIRCUIT DIAGRAM
r--
I
-,
I
1N914
+5
Bias t
1-1~
...--...._L..:----..-..H_....---+-I1-2-.2-k.....
PFr-:1,CX! pF
r.:l
'CX! pF
~I1~I1OOPF
-=
-=
+5V
560 1/6 MC14069UB
+5V
1/6 MC14069UB
+5V
1/6 MC14069UB
1°OPFI
**
-=
I
I
I
I
I
I
_...J
+5V
Ceramic
Data
VDD
lMSD
Data Outputs
Os c in
lLse
10Meg
lO PF
100 PFJ
I
MC14458
17
Data Ready
A3 22
A221
20
A1
19
AO
18
5
OA71' F
J
23
l
Add"" O",P""
VA
On/Off
Vol
Low Band VHF
UHFNHF
AFT
NOTES:
tBias used for photodiode only.
* It is mandatory to use an infrared filter in front of the photodiode Type Kodak 87C or similar
Select 2N5458 FETs with an lOSS of 2 to 4 mA
* * 100 pF capacitor should be placed as close as possible to Pin 2 of the MC14458
*
7-11
,i,i.
II
MC14457, MC14458
FIGURE 6 -
BLOCK DIAGRAM OF A PLL SYSTEM
MC14502B
3 State Inverter
+5V
~2
~~
~
~
6
I
24
9 t-"--+5V
MCl4458 16
Remote 15
Receiver
14
12
17
13
3
5
6
1
7
2
10
9
12 Inh
PLL
Synthesizer
I-
~
Strobe
I-
~
III III
,-, ,:,,-,
,:,
'---
FIGURE 7 -
Decoderl
Driver
One Shot - Adjust
output pulse width
to give a low on Inh
which
is
long
enough to enter data
without problem.
-{>r-J
Binary
Complement
Diode
Logic
f---
Y>
I
III III II
1
2
3
4
5
6
7
B
9
0
Enter
Note: Enter must be a 0101 in
complementary logic.
BLOCK DIAGRAM OF A TUNING ADDRESS SYSTEM FOR UP TO 256 CHANNELS
II
Band Switching
Synthesizer
CMOS
MPU/MCU
R2
Rl
RO
Kl K2 K4 KB
/'/'/
7-12
PLL
®
MC14469
MOTOROLA
ADDRESSABLE ASYNCHRONOUS
CMOS LSI
RECEIVER/TRANSMITTER
The MCl4469 Addressable Asynchronous Receiver Transmitter is
constructed with MOS P-channel and N-channel enhancement devices in a single monolithic structure (CMOS). The MCl4469 receives one or two eleven-bit words in a serial data stream. One of
the incoming words contains the address and when the address
matches, the MCl4469 will then transmit its information in two
eleven-bit-word data streams. Each of the transmitted words contains eight data bits, even parity bit, start and stop bit.
The received word contains seven address bits and the address of
the MCl4469 is set on seven pins. Thus 27 or 128 units can be interconnected in simplex or full duplex data transmission. In addition to
the address received, seven command bits may be received for data
or control use.
The MCl4469 finds application in transmitting data from remote
A-to-D converters, remote M PUs or remote digital transducers to
the master computer or M PU.
(LOW-POWER COMPLEMENTARY MOS)
ADDRESSABLE ASYNCHRONOUS
RECEIVER/TRANSMITTER
• Supply Voltage Range - 4.5 Vdc to 18 Vdc
L SUFFIX
CERAMIC PACKAGE
CASE 734
• Low Quiescent Current - 75 p.Adc maximum @ 5 Vdc
• Data Rates to 4800 Baud @ 5 V, to 9600 Baud @ 12 V
• Receive - Serial to Parallel
Transmit - Parallel to Serial
ORDERING INFORMATION
• Transmit and Receive Simultaneously in Full Duplex
Denotes
• Crystal or Resonator Operation for On-Chip Oscillator
Ceramic Package
• See also Application Note AN-8oo
Plastic Package
BLOCK DIAGRAMS
PIN ASSIGNMENTS
Transmit
Receive
40
Input Data
39
38
37'
36
35
34
33
32
31
30
29
28
Send Enable
L--. ~:~~; ~::~~ss
27
Pulse (VAP)
26
Clocks
?
25
O"'~D,t'R,teCIO'k
0"2
~
~Re,e,"eD,,'S"obe
24
23
22
21
7-13
II
MC14469
MAXIMUM RATINGS
This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit. For proper operation it is recommended
that V in and V out be constrained to the range
VSS';; (V in or V out ) .;; VOD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
(Voltages referenced to VSS, Pin 20.
DC Supply Voltage
Input Voltage, Ali Inputs
DC Current Drain per Pin
Operating Temperature Range
Storage Temperature Range
Symbol
Value
Unit
VDD
-0.5 to +18
Vin
-0.5 to VDO + 0.5
Vde
Vdc
I
10
mAde
TA
-40 to +85
T stg
-65 to +150
°c
°c
VSS or VDO).
ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
Output Voltage
Vin = VDD orO
"0" Level
"1" Level
VOL
VOH
Vin=OorVDD
I nput Voltage #
(VO = 4.5 or 0.5 Vde)
(VO = 9.0 or 1.0 Vde)
"0" Level
FI
(VOL
(VOL
(VOL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
Sink
Output Drive Current (Pin 2 Only)
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL
(VOL
(VOL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
Sink
Max
Min
Typ
Max
Min
Max
Unit
-
0.05
0.05
0.05
-
0.05
0.05
0.05
-
0.05
0.05
0.05
Vdc
-
0
0
0
4.95
9.95
14.95
5.0
10
15
-
4.95
9.95
14.95
-
Vdc
-
2.25
1.5
-
1.5
5.0
10
15
-
5.0
10
15
4.95
9.95
14.95
-
5.0
10
-
1.5
3.0
-
4.0
-
4.50
6.75
3.0
4.0
-
15
-
3.0
4.0
5.0
10
15
3.5
7.0
11.0
-
3.5
7.0
11.0
2.75
5.50
8.25
-
3.5
7.0
11.0
-
5.0
5.0
10
15
-1.0
-0.2
-0.5
-1.4
-
-0.8
-0.16
-0.4
-1.2
-1.7
-0.35
-0.9
-3.5
-
-0.6
-0.12
-0.3
-1.0
-
0.44
1.1
3.0
0.88
2.25
8.8
-
0.36
0.9
2.4
-
-0.16
-0.035
-0.08
-0.27
-0.32
-0.07
-0.16
-0.48
-
-0.13
-0.03
-0.06
-0.2
-
0.17
0.28
0.84
-
-
-
-
-
-
Vdc
Vdc
VIH
(VO = 0.5 or 4.5 Vde)
(Va = 1.0 or 9.0 Vdc)
(Va = 1.5 or 13.5 Vdc)
Output Orive Current (Except Pin 2)
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
+850 C
Min
VIL
(VO = 13.5 or 1.5 Vde)
"1" Level
25°C
-40°C
Voo
Vdc
-
mAdc
IOH
IOL
-
-
5.0
10
15
0.52
1.3
3.6
-
5.0
5.0
10
15
-0.19
-0.04
-0.09
-0.29
-
5.0
10
15
0.1
0.17
0.50
-
-
-
-
-
-
mAdc
IOH
IOL
mAdc
-
-
-
0.085
0.14
0.42
-
-
-
0.07
0.1
0.3
-
mAdc
-
f max
4.5
400
-
365
550
-
310
-
I nput Current
lin
15
-
±0.3
-
±0.00001
±0.3
-
±1.0
/lAdc
Pull-Up Current (Pins 4-18)
IUp
15
12
120
10
50
100
8.0
85
/lAdc
I nput Capacitance
(Vin = 0)
Cin
-
-
-
-
5.0
7.5
-
-
pF
Quiescent Current
(Per Package)
100
5.0
10
15
-
75
150
300
-
565
1125
2250
/lAdc
-
0.010
0.020
0.030
-
-
75
150
300
-
-
-
+4.5
+18.0
+4.5
-
+18.0
+4.5
+18.0
Vdc
Maximum Frequency
!Supply Voltage
VOD
·'Noise immunity specified for worst-case input combination.
Noise Margin both "1" and ..
level = 1.0 Vdc min@ VDD = 5.0 Vdc
2.0 Vdc min @ VDO = 10 Vdc
2.5 Vdc min @ VDO = 15 Vdc
a..
7-14
-
kHz
MC14469
DATA FORMAT AND CORRESPONDING DATA POSITION AND PINS FOR MC14469 AND MC6850
RECEIVE DATA (RI; Pin 19t
I_
Address
- - -.........I~_r T T
T
..
l1!.I_ 1_ L L. .L I-.L.J
MC14469
Pin Number
,L J
P
"
4
5
6
8
-,-
9
SP
Command
Identifier
Address
Identifier
10
38
37
36
35
34
33
CO C1
C2
C3 C4
C5
C6
21
20
19
18
17
16
02 03 04
05
06
39
Pin Designation
AO
A 1 A2 A3 A4 A5
A6
MC6850
ACIA Pin Number
22
21
20
17
16
22
Pin Oesignation
00
01
02 03 04 05
06
00 01
19
18
TRANSMIT DATA (TRO; Pin 21t
,-
____
Input Oata
~
~~ '" I L.
MC14469
Pin Numbers
--,...
12
13
14
15
16
17
18
100101102103104105 ID6 107
29
28
27
26
25
24
23
22
SO
S1
S2
S3
S4 S5
S6
S7
21
20
19
16
15
MC6850
ACIA Pin Number
22
21
20
19
18
16
15
22
Pin Designation
00 01
02
03
04 05 06
07
00 01
ST
~
p
~
SP
~
17
AO -+ A6 ~ Address Bits
Start Bit
ParitY Bit
Stop Bit
"I
Status
T T T T T "T T T;"1 spr;,T T "T T"" T .,. "T T pi SP
.L .J. J. J. .J. .J. .1. J.. .J..::.J '" L ..1. ..L .J. .J. ~ .J. .L ~ ....'......_ _ _ _ __
11
Pin Designation
.,
Command
~TTT,.o
T~~]"
..L ~ ..L .J. .J. -L
I.
T"""'~
T
T"
,-s
CO -+ C6
00 -+ 07
~
~
02 03
18
17
04 05
06 07
100 -+ 107 ~ MC14469 Identification Code
SO -+ S7
Command Bits
ACIA Bus Bits
~
MC14469 Status Code
TYPICAL RECEIVE/SEND CYCLE
M
Address
S
~B
SO 1 2 345 6 7
VOO
M
S
Command
S
_ _ _B
S
P So 1 234 567
fp'"
__ ~'"'~"''"'~''
...., T'-XTXTX"'XTXTXTX"" pnT!'"X'X"TX"'XTXTX"TX'
VSS
~~;&;~~:.t;"'~_L..,
Receiver Input (RI)
I
I
I
Valid Address Pulse
(VAP)
I
~~-------------------------------------
Internal Valid
Address Latch
(VAL)
I
Internal Send
~r---------'L-J
Enable Latch
(SEL)
Command Strobe
Output (CS)
________________
I
~n~
____ _____________________________
~
I
Send Input
(Send)
_ _ _ _ _ _ _ _ _ _- L_ _
I
~~~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
I
I
Transmit Out
(TRO)
M
M
I s s
I
B
S
B
S
VOOIS1i
VSS
I
10 k
10 k
10 k
RI
TRO
RI
TRO
VOO
VOO
107
107
107
••
VSS I
MC14469
o
AO,IOO
A1,I01
A2,I02
A3,103
A4,I04
A5,105
A6,I06
• •
S7
S7
MC14469
UART
10 k
TRO
VOO
S7
MC6850
ACIA
10 k
10 k
Address
0000001
CS
Send
A1,I01
A2,I02
A3,I03
A4,I04
A5,I05
A6,I06
Address
1111111
MC14469
127
CS
CS
Send
Send
Address
0000000
Master
Station
Remote MC14469 Stations
Note: For Simplex operation the 107 must be tied high, S7 must be
tied low and the 7-bit 10 must be the same as the 7-bit address
(or set to some unused address) to prevent erroneous responses.
3:
o
.....
~
~
CJ)
FIGURE 5 - DOUBLE LINE, FULL DUPLEX DATA TRANSMISSION
CD
V+
0
Voo
k~
1 k
~
MPS-005
10 k
~
":"I
.......
<0
.-Y
~
~
J
rJ;
VSS
MC6850
ACIA
UART
Master
Station
I
10k
RI
TRO
RI
MPS-005
MPS-005
10k~ ~
TAO
• ~
~ II
I
rJ;
---+-~~----------------------------~
7-30
VSS
MC145026, MC145027, MC145028, MC145029
FIGURE 2 -
MC145027 DECODER BLOCK DIAGRAM
Valid
Transmission
D6
Q)
'"c;,
D7
Q)
a:
D8
Sequencer
Circuit
4
D9
3
Al
A2
9
Data
Extractor
A3
Data
In
~VDD
A4
C2
R2~ ~vss
A5
FIGURE 3 -
MC145028 DECODER BLOCK DIAGRAM
Control
Logic
~
Valid
.~ Transmission
9-Bit
Shift
Register
~Data
Data
Extractor
~ In
~VDD
C2
6,0 R21-:],. ~vss
-=
7-31
-=
II
MC145026, MC145027, MC145028, MC145029
FIGURE 4 -
MC145029 DECODER BLOCK DIAGRAM
Valid
Transmission
D5
D6
D7
D8
D9
9
Data
Extractor
~VDD
~vss
6 10
FIGURE 5 -
II
Data
In
ENCODER OSCILLATOR INFORMATION
RS
RTC
-11
13
This oscillator will operate at a frequency determined by the external RC network; i.e.,
f=
1
(Hz)
2.3 RTC CTC'
for 1 kHzsfs400 kHz
where: CTc' = CTC + Clayout + 12 pF
Rs",2 RTC
The value for RS should be chosen to be 2: 2 times RTC. This
range will ensure that current through RS is insignificant compared
to current through RTC. The upper limit for RS must ensure that
RS x 5 pF (input capacitance) is small compared to RTC x CTC.
For frequencies outside the indicated range, the formula will be
less accurate The minimum recommended oscillation frequency of
this circuit is 1 kHz. Susceptibility to externally induced noise signals
may occur for frequencies below 1 kHz and/or when resistors utilized are greater than 1 MO.
RS2:20 k
RTC2: 10 k
400 pF< CTC< 15 J.'F
7·32
MC145026, MC145027, MC145028, MC145029
FIGURE 6 -
~ PW min
ENCODER/DECODER TIMING DIAGRAM
MC146026 ENCODER
TE~ _____________________________________________________ con~:U~~~ i~:~~~:~~:~~
..... NM.qL.OCD
~~~~R,c~~~~~g 2i3oobj&5a;~~55~g
~~~~~~~~N~
g?J~a5a;@~~
Oscilla~ ~J1JU1JUU1JlJU1JlJU4 J~ ~
Encoder
IPin 12)
.
/--!lth Blt-+l
1+-1st Blt-----.j
DataOutlPin15)
1+-1st Blt---+l
f+--9th BI1--!
i~~~ ~
f.t--- One - k - Trlnary----+J-- Zero ----1
I
I
I_
_I
1st Word
._
2nd
WOrd-----ir--~J
MC145027, MC145028, AND MC145029 DECODERS
Valid Transmis_s_io_n_I_Pi_n_l_l_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--if------/~
DataOutPu_ts_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~x~
FIGURE 7 -
_______
MC145026 ENCODER DATA WAVEFORMS
Encoder
Oscillator
(Pin 12)
I
Encoded
"One"
Data
Out
IPin 15)
Encoded
"Zero"
U
-.1
n
Jl
I
L
I
I
I
I
I
Encoded
"Open"
..J
1--
I·
LSl
·1
Data Pulse
Period
Data Bit Period
7·33
I
I
I
I
I
I
·1
II
MC145026, MC145027, MC145028, MC145029
FIGURE 8 -
MC145027/MC145029 FLOWCHART
No
Disable VT
on the 1st
Address Mismatch
and Ignore the
Rest of This Word
Store
the
Data
No
I
Disable VT
on the 1st
Data Mismatch
Latch Data
Onto Output
Pins and
Activate VT
Yes
7-34
Disable
VT
MC145026, MC145027, MC145028, MC145029
FIGURE 9 -
MC145028 FLOWCHART
No
Serially Shift the
Address ("1" = "1"1"
Into the Storage
Register up Until
Il.e., Excludlngl the
1st Mismatch
Store
the
Address
'1"
No
= "T"I"
Shift in
an Extra
"1"
Yes
No
Disable
VT
Activate
II
VT
Yes
Disable
VT
"For shift register comparisons, a "T"
IS
stored as a "1".
7-35
MC145026, MC145027, MC145028, MC145029
FIGURE 10 - f max vs Clayout
MC145027, MC145028, and MC145029
500
400
N
I 0
~-
X~
J~
300
200
100
10
20
30
40
Clayout (pF) on Pins 1-5 (MC145027); Pins 1-5 and 12-15 (MC145028);
Pins 1-4 (MC145029)
7-36
50
3:
o
~
FIGURE 11 - TYPICAL APPLICATION
CTC' = CTC + Clayout + 12 pF
100 pF5 CTC:515 ItF
RTC~ 10 k; RS'" 2 RTC
R1 ~10 k
C1 ~400 pF
R2~ 100 k
C2~ 700 pF
VDD
TE
VDD
.l-.
1:,]
116
I
01ltF
N
5»
3:
VDD
O.lItF
~
en
o
N
"'......
16
13
W
-....J
4-Bit
Binary
Data
!
~
I
3:
Trinary
Addresses
MC145027
MC145026
-....J
o
VDD
9
T
Trinary
Addresses
~
en
o
Rl
12
-¥
14
12
11
R2
=
R1Cl =3.95 RTCCTC
R2C2 = 77 RtCCTC
Repeat of
Above
ICTC' = CTC + 20 pF)
fosc (kHz)
RTC
R1
C1
R2
C2
10 k
GTC'
120 pF
RS
362
20 k
10 k
470 pF
100 k
910 P
181
10 k
240 pF
20 k
10 k
100 k
1800 pF
100 k
3900 pF
100 k
7500 pF
88.7
10 k
490 pF
20 k
10k
910 pF
2000 pF
42.6
10k
1020 pF
20 k
10k
3900 pF
21.5
10 k
2020 pF
20 k
10 k
8200 pF
100 k
0. 015 1t F
8.53
10k
5100 pF
20 k
10k
0.021tF
200 k
0.021t F
1.71
50k
5100 pF
100 k
50k
0.021t F
200 k
0.1 JLF
II
D7
o
~
D9
~
VT
en
o
N
CD
1
2.3 RTCCTC'
Example RIC Values
(All Resistors and Capacitors are ±5%)
S»
3:
!2.. D8
RS
fose
~
N
C1
10
11
~
en
o
RTC
I
o
Repeat
of Above
II
7-38
CMOS Smoke Detectors
8-1
CMOS SMOKE DETECTORS
Device
Number
MCl4466
MCl4467-1
MCl4468
Function
lonization- Type Smoke
Detector
lonization-Type Smoke
Detector with
Interconnect
Function
Low Cost Smoke Detector
Low Cost Smoke Detector
Interconnectable Smoke Detector
On-Chip High
Input Impedance
FET Comparator
.,..
Low Battery
Detector
Piezoelectric
Horn Driver
Device
Number
Number
of Pins
.,..
.,..
MC14466
16
.,..
.,..
.,..
MC14467-1
16
.,..
.,..
.,..
MC14468
16
I
8-2
®
MOTOROLA
MC14466
LOW-COST SMOKE DETECTOR
CMOS MS.
(LOW-POWER COMPLEMENTARY MOS)
The MC14466, together with an ionization chamber, will detect
smoke using a minimum of external components. When smoke is
sensed, an alarm is sounded via an external piezoelectric transducer and
internal drivers. This circuit is designed to comply with the UL217
specification.
•
Ionization Type with On-Chip FET Input Comparator
•
•
Piezoelectric Horn Driver
Guard Outputs on Both Sides of Detect Input
•
Low Battery Trip Point Internally Set Can Be Altered Via
External Resistor
•
Detect Threshold Internally Set Can Be Altered Via
External Resistor
•
•
•
Pulse Testing for Low Battery Uses LED for Battery Loading
Comparator Outputs for Detect and Low Battery
Internal Reverse Battery Protection
•
Chip Complexity: 239 FETs
LOW-COST SMOKE DETECTOR
16
P SUFFIX
PLASTIC PACKAGE
CASE 6488*
'Pins 15 and 16 are connected via a metal
shorting bar. See package detail In Figure 1.
BLOCK DIAGRAM
PIN ASSIGNMENT
VDD
VDD
Piezoelectric
co~pe~~i [rJi'...'16~ Guard
N.C. [ 2
15 J Detect
80 k
1045k
5
13
14
J
ComLg~~
[ 4
13
J Sensitivity
LED
I 5
12] Ext Capacitor
Guard
VDD [ 6
11 ] Silver
I 7
10' Brass
Ext Resistor
Feedback [ ....8_ _ _9...1~ VSS
1125 k
VDD= Pin 6
Detect Input 1_5~_ _--I
Vss=Pin 9
8-3
Input
Low V Set [ 3
Set
II
MC14466
MAXIMUM RATINGS (Voltages referenced to Vss)
Rating
Symbol
Value
Unit
VDD
-0.5 to + 15
V
Input Voltage. All Inputs
Yin
DC Input Current. per Pin
lin
-0.25 to VDD+0.25
10
mA
30
mA
DC Supply Voltage
V
DC Output Current. per Pin
lout
Operating Temperature Range
Storage Temperature Range
TA
T stg
-55 to + 125
°C
Reverse Battery Time
tRB
5.0
s
o to
+50
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields: however. it
is advised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to this high
impedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range VSS,s (Vin or
Vout),sVDD).
°C
RECOMMENDED DC OPERATING CONDITIONS (Voltages referenced to VSS)
Parameter
Symbol
Value
VDD
Cext
9.0
V
0.1
/L F
Rext
-
8.2
MO
10
mA
Supply Voltage
Timing Capacitor
Timing Resistor
Battery Load (Resistor or LED)
Unit
ELECTRICAL CHARACTERISTICS (T A = 25°CI
Symbol
Voo
Vdc
Min
Typ
Max
Operating Voltage
VDD
-
6.0
-
10
Output Voltage
Piezoelectric Horn Drivers IIOH = 16 mAl
Comparators (IOH = 30 /LAI
Piezoelectric Horn Drivers IIOL = - 16 mAl
Comparators (IOL = - 30 /LA)
VOH
Characteristic
VOL
Unit
V
V
74
9.0
74
9.0
6.5
8.5
-
8.8
0.1
0.9
0.5
-
-
mA
Output Current - LED Driver
(VOL =3.0 V)
IOL
74
10
Operating Current
(R ext =8.2 Mni
IDD
9.0
-
5.0
9.0
/LA
Input Current - Detect (40% R. H.)
lin
9.0
-
-
±1.0
pA
Internal Set Voltage - Low Battery
- Sensitivity
Vlow
V set
Vhys
9.0
-
7.2
47
50
7.8
53
9.0
75
100
150
V
%VDD
mV
9.0
9.0
-
-
-
-
± 100
±50
Hysteresis
Offset Voltage (measured at Vin = VDD/2)
Active Guard
Detect Comparator
mV
VOS
II
8-4
MC14466
TIMING PARAMETERS (C ext = 0 1 I"F, Rext = 82 MI], VDD = 9.0 V, T A = 25°Cl
Characteristics
No Smoke
Smoke
Oscillator Period
Oscillator Rise Time (Pin 12)
Min
Typ
Max
Units
1.34
32
1.67
40
2.0
48
s
ms
8
10
12
ms
On Time
Off Time
120
60
160
80
208
104
ms
ms
LED Output
(During No Smoke)
Off Time Between Pulses
On Time
32
8
40
10
48
12
s
ms
Hom Output
(During Low Ballery)
On Time
Off Time Between Pulses
8
32
10
40
12
48
ms
s
Hom Output
(During Smoke)
TIMING DIAGRAM
No Smoke
Smo~
Smoke
r--- No Low Battery ~ No Low Battery
~ I ..
1.67s~~ ~40ms
NoSmo~
~
Low Battery
IC
Low Battery ~
10ms-'l~
Oscillator
(Pin 12)
Detect
Comp (Pin 1)
nnr----------------~---1~
Low V
Comp (Pin 41
Horn
Modulation
LED
Pulse
High = Horn Enable
Low = Horn Disable
'--------l~
=~~
-.J
U~--------~~j---
* - 24 Clock Cycles ----.J
24 Clock Cycles
40s
1s
10 s
NOTES: 1. Horn modulation is self-completing. When going from smoke to no smoke, the alarm condition will terminate only when horn
2. Comparators are strobed on once per clock cycle 11.67 s for no smoke, 40 IT S for smokel.
3. Low battery comparator information is latched only during LED pulse.
FIGURE 1 -
PACKAGE DETAIL
* External lead connection (shorting barl between Pins 15 and 16
8-5
IS
off.
II
MC14466
DEVICE OPERATION
TIMING
nected between VDD and VSS. These voltages can be
altered by external resistors connected from Pins 3 or 13 to
either VDD or VSS. There will be a slight interaction here
due to the common voltage divider network.
The internal oscillator of the MCl4466 operates with a
period of 1.67 seconds during no-smoke conditions. Each
1.67 seconds, internal power is applied to the entire IC and a
check is made for smoke. Every 24 clock cycles a check is
made for low battery by comparing VDD to an internal zener
voltage. Since very small currents are used in the oscillator,
the oscillator capacitor should be of a low leakage type.
TEST MODE
Since the internal op amps and comparators are power
strobed, adjustments for sensitivity or low battery level could
be difficult and/or time-consuming. By forcing Pin 12 to
VSS, the power strobing is bypassed and the outputs, Pins 1
and 4, constantly show smoke/no-smoke and good battery/low battery, respectively. Pin 1 = VDD for smoke and
Pin 4 = VDD for low battery. In this mode and during the
10ms power strobe, chip current rises to approximately
50 p.A.
DETECT CIRCUITRY
If smoke is detected, the oscillator period becomes 40 ms
and the piezoelectric horn oscillator circuit is enabled. The
horn output is modulated 200 ms on, 40 ms off. During the
off time, smoke is again checked and will inhibit further horn
output if no smoke is sensed. During smoke conditions the
low battery detection is inhibited, but the LED pulses at a
1.0 Hz rate.
An active guard is provided on both pins adjacent to the
detect input. The voltage at these pins will be within 100 mV
of the input signal. This will keep surface leakage currents to
a minimum and provide a method of measuring the input
voltage without loading the ionization chamber. The active
guard op amp is not power strobed and thus gives constant
protection from surface leakage current. Pin 16 of the active
guard is connected to Pin 15 (the detect input) during shipping to protect Pin 15 from static damage (see Figure 1).
LED PULSE
The 9-volt battery level is checked every 40 seconds during
the LED pulse. The battery is loaded via alOmA pulse for
10 ms. If the LED is not used, it should be replaced with an
equivalent resistor such that the battery loading remains at
10 mAo
HYSTERESIS
When smoke is detected, the resistor/divider network that
sets sensitivity is altered to increase sensitivity. This yields
approximately 100 mV of hysteresis and avoids false triggering.
SENSITIVITY/LOW BATTERY THRESHOLDS
Both the sensitivity threshold and the low battery voltage
levels are set internally by a common voltage divider con-
FIGURE 2 - TYPICAL APPLICATION AS IONIZATION SMOKE DETECTOR
1M
16
15r--------------------------------o
II
330
n
Rext
MC14W6
~
::r----------------------------,
11 r----------,
0.1 JLF
Cext
1
10~----~~+_----~
8.2 M
0.1 JLF
1_
+
-=- 9 V
I
150 kn
1.5 Mn
NOTE: Component values may change depending on type of piezoelectric horn used
8-6
MC14466
FIGURE 3 - TYPICAL LED OUTPUT
I-V CHARACTERISTIC
100.0
~ ~ VO~
25°C
TA
9.0 Vdc
t==
.... ..-
1\
;{
E
~~
1""
VDO -7.2 Vdc
~
I
I
2:
~
1.0
I.
9
0.1
o
10
VDS, DRAIN TO SOURCE VOLTAGE (Vdc)
FIGURE 4 -
TYPICAL P HORN DRIVER OUTPUT
I-V CHARACTERISTIC
1000.0
1000.0
;{
E
r"
~
-
I---
TA = 25°C I---
r"
;{
VOD = 9.0 Vdc
./"./
'/
2:
TA = 25°C
I
-
~
~
VDD = 7.2 Vdc
~
9
p. CH SOURCE CURRENT
Voo = 9.0 Vdc
\
!r
U
z
V
10.0
r--- -
1
\.
VOO = 7.2 Vdc
II
I
10.0
Ci
f==
N - CH SINK CURRENT
=f==
I'
1.0
o
1.0
10
o
10
VOS, DRAIN TO SOURCE VOLTAGE (Vdc)
VOS, DRAIN TO SOURCE VOLTAGE (Vdc)
FIGURE 5 -
TYPICAL COMPARATOR OUTPUT
I-V CHARACTERISTIC
10.0
TA
;{
..s
I
~
II
VOO=9.0Vdc or 7.2Vdc
1.0
2:
~
25°C
./
1,/
0.1
.L"
-
p. CH SOURCE
ANO
N . CH SIN K
CURRENT
9
I
.01
I
o
10
VOS, ORAIN TO SOURCE VOL TAGE (Vdc)
8·7
®
MC14467·1
MOTOROLA
Advance Information
CMOS MSI
(LOW-POWER COMPLEMENTARY MOS)
LOW-COST SMOKE DETECTOR
The MCl4467-1, when used with an ionization chamber and a small
number of external components, will detect smoke. When smoke is
sensed, an alarm is sounded via an external piezoelectric transducer and
internal drivers. This circuit is designed to comply with the UL217
specification.
• Ionization Type with On-Chip FET Input Comparator
•
•
•
•
•
•
•
•
•
LOW-COST SMOKE DETECTOR
Piezoelectric Horn Driver
Guard Outputs on Both Sides of Detect Input
Input-Protection Diodes on the Detect Input
Low-Battery Trip Point, Internally Set, Can Be Altered Via
External Resistor
Detect Threshold, Internally Set, Can Be Altered Via External
Resistor
Pulse Testing for Low Battery Uses LED for Battery Loading
Comparator Outputs for Detect and Low Battery
Internal Reverse Battery Protection
Direct Replacement for the MCl4467, with Improved Alarm Stability
MCl4467Pl
PLASTIC PACKAGE
CASE 648
BLOCK DIAGRAM
PIN ASSIGNMENT
VDD
Detect Camp. Out
II
N/C
LowV Set
Low V Camp. Out
LED
VDD
Timing Resistor
Feedback
Guard Hi-Z
Detect Input
Guard Lo-Z
Sensitivity Set
Osc Capacitor
Silver
Brass
VSS
_________----J11'--------.J
This document contains Information on a new product. Specifications and information herein
are subiect to change without notice.
8-8
MC14467·1
MAXIMUM RATINGS* (Voltages referenced to VSS)
Rating
DC Supply Voltage
Input Voltage, All Inputs Except Pin 8
DC Current Drain per Input Pin, Except Pin 15= 1 mA
Symbol
Value
Unit
VDD
-0.5 to + 15
V
Yin
I
- 0.25 toVDD + 0.25
V
10
mA
I
30
mA
-10 to +60
°C
Storage Temperature Range
TA
Tstg
-55 to + 125
°C
Reverse Battery Time
tRB
5.0
s
DC Current Drain per Output Pin
Operating Temperature Range
"Maximum Ratings are those values beyond which damage to the device may occur.
RECOMMENDED DC OPERATING CONDITIONS (Voltages referenced to VSS)
Parameter
Supply Voltage
Timing Capacitor
Timing Resistor
Battery Load (Resistor or LED)
Unit
Symbol
Value
VDD
-
9.0
V
0.1
/L F
-
8.2
MO
10
mA
ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS, T A = 25°C)
Symbol
Voo
Vdc
Min
Typ
Max
Unit
Operating Voltage
VDD
-
6.0
-
12
V
Output Voltage
Piezoelectric Horn Drivers (lOH = - 16 mAl
Comparators (lOH = - 30 p.A)
Piezoelectric Horn Drivers (lOL = + 16 mAl
Comparators (lOL = +30 p.A)
VOH
7.2
9.0
7.2
9.0
6.3
8.5
-
-
8.8
-
-
0.1
0.9
0.5
Characteristic
Output Voltage -
VOL
LED Driver, IOL = 10 mA
Output Impedance, Active Guard
Operating Current (Rbias=8.2 MOl
Input Current - Detect (40% R.H.)
Pin 14
Pin 16
V
V
VOL
Lo-Z
Hi-Z
7.2
-
-
3.0
V
9.0
9.0
-
10
500
-
kO
IDD
9.0
12.0
5.0
p.A
-
9.0
12.0
-
±1.0
pA
-
-
lin
9.0
Internal Set Voltage
Low Battery
Sensitivity
Vlow
V set
9.0
-
7.2
47
50
7.8
53
V
%VDD
9.0
75
100
150
mV
9.0
9.0
-
-
±100
±50
Hysteresis
Vhys
Offset Voltage (measured at Yin = VDD/2)
Active Guard
Detect Comparator
VOS
Input Voltage Range, Pin 8
Yin
-
-10
-
VDD+ 10
V
Input Capacitance
Cin
-
-
5.0
-
pF
Common Mode Voltage Range, Pin 15
Vcm
-
0.6
-
VDD-2
V
mV
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation
it is recommended that except for pin 8, Yin and Vout be constrained to the range VSS :$ (Vin or Vout) :$ VDD. For pin 8, refer to the Electrical
Characteristics.
8-9
II
MC14467·1
DEVICE OPERATION
TIMING
SENSITIVITY/LOW BATIERY THRESHOLDS
The internal oscillator of the MC14467-1 operates with a
period of 1.67 seconds during no-smoke conditions. Each
1.67 seconds, internal power is applied to the entire IC and a
check is made for smoke, except during LED pulse, Low Battery Alarm Chirp, or Horn Modulation (in smoke). Every 24
clock cycles a check is made for low battery by comparing
VDD to an internal zener voltage. Since very small currents
are used in the oscillator, the oscillator capacitor should be
of a low leakage type.
Both the sensitivity threshold and the low battery voltage
levels are set internally by a common voltage divider connected between VDD and VSS. These voltages can be
altered by external resistors connected from pins 3 or 13 to
either VDD or VSS· There will be a slight interaction here
due to the common voltage divider network.
TEST MODE
Since the internal op amps and comparators are power
strobed, adjustments for sensitivity or low battery level could
be difficult and/or time-consuming. By forcing Pin 12 to
VSS, the power strobing is bypassed and the outputs, Pins 1
and 4, constantly show smoke/no smoke and good battery/low battery, respectively. Pin 1 = VDD for smoke and
Pin 4=VDD for low battery. In this mode and during the 10
ms power strobe, chip current rises to approximately 50 p.A.
DETECT CIRCUITRY
If smoke is detected, the oscillator period becomes 40 ms
and the piezoelectric horn oscillator circuit is enabled. The
horn output is modulated 160 ms on, 80 ms off. During the
off time, smoke is again checked and will inhibit further horn
output if no smoke is sensed. During smoke conditions the
low battery alarm is inhibited, but the LED pulses at a
1.0 Hz rate.
LED PULSE
The 9-volt battery level is checked every 40 seconds during
the LED pulse. The battery is loaded via a 10 mA pulse for
10 ms. If the LED is not used, it should be replaced with an
equivalent resistor such that the battery loading remains at
10 mA.
An active guard is provided on both pins adjacent to the
detect input. The voltage at these pins will be within 100 mV
of the input signal. This will keep surface leakage currents to
a minimum and provide a method of measuring the input
voltage without loading the ionization chamber. The active
guard op amp is not power strobed and thus gives constant
protection from surface leakage currents. Pin 15 (the Detect
input) has internal diode protection against static damage.
HYSTERESIS
When smoke is detected, the resistor/divider network that
sets sensitivity is altered to increase sensitivity. This yields
approximately 100 mV of hysteresis and reduces false triggering.
FIGURE 1 - TYPICAL APPLICATION AS IONIZATION SMOKE DETECTOR
1M
16
II
f
2 MCl4467-115 I----------------~
3
14
0.1
"r
220 kO *
1.5 MO*
* NOTE:
Component values may change depending on type of piezoelectric horn used.
8-10
MC14467·1
TIMING PARAMETERS (C=O.l p.F, Rbias=S2 MO, VOo=9.0 V, TA=25°C, See Figure 51
Characteristics
Oscillator Period
Symbol
Min
Typ
Max
Units
tCI
1.34
32
1.67
40
2.0
s
ms
No Smoke
Smoke
Oscillator Rise Time
tr
S
10
12
ms
On Time
Off Time
PWon
PWoff
120
60
160
SO
208
104
ms
ms
Between Pulses
On Time
tLED
PWon
32
S
40
48
10
12
s
ms
On Time
Between Pulses
ton
toft
8
32
10
40
48
Horn Output
(During Smokel
LED Output
Horn Output
(During Low Batteryl
FIGURE 2 - TYPICAL LED OUTPUT
I-V CHARACTERISTIC
100.0
I--f----- ~ Voo
TA
9.0 Vde
25 0 C
48
12
ms
s
FIGURE 3 - TYPICAL COMPARATOR OUTPUT
I-V CHARACTERISTIC
10.0
r===
TA - 25 0 C
~
I\,
~
E
b
;: 10.0
,
i
~
~
.§.
>-
Voo
~
:::0
u
2:
~
Cl
ff
./
~
lL
0.1
9.0 Vde or 7.2 Vdc
-
a:
a:
-
..
I.
1.0
Voo
1.0
2:
7.2 Vde
I
2:
~
....
5?
5?
~
P·CHSDURCE
ANO
N . CH SIN K
CURRENT
r
0.1
.01
o
10
\
I
o
10
VOS, ORAIN TO SOURCE VOLTAGE (Vdc)
VOS, ORAIN TO SOURCE VOLTAGE (Vdc)
FIGURE 4 - TYPICAL P HORN DRIVER OUTPUT
I-V CHARACTERISTIC
1000.0
1000.0
-~
E
r'
-
/./
~
7/
2:
~
,,r
1.0
~
E
r'
"VOO = 7.2 Vde
~
p. CH SOURCE CURRENT
10
N·CHSINKCURRENT
I
I
o
=
I--I---
I
10
VOS, DRAIN TO SOURCE VOLTAGE IVoe)
8-11
II
VOO = 7.2 Vde
I
10.0
10
VOS, DRAIN TO SOURCE VOLTAGE (Vdc)
I
r;;o"
fL
11
I
o
9.0 Vde
\
5?
f==
TA = 25 0 C I---
r------- r-- VOO
2:
V
10.0
5?
T A = 25 0 C I - - -
f-- VOO = 9.0 Vde
•
3C
n
......
.....
~
0)
.:a.
Standby:
No Smoke/
No Low Battery
I.
Oscillator \
(p'" 121
.1"
f'....
FIGURE 5 - TIMING DIAGRAM
Smoke/ No Low Battery
N
•
V 'J '
lfl.fiIlflfhU
nl
Detect out -, r--t
(Pin 1)
U U
I
r - 1 r - 1 r - 1 r--1 r - 1 r - 1 r - 1 r---1 I
U
U
U
U
U
U
U
U
r-t
Low Battery Out -, r - 1
(Pin 4)
U U
cp
....I.
I\)
Hysteresis (Internal)
(Pin 13) (Note4)
Sample (Internal)
Smoke
Horn
(Pins 10 & 11)
-----i~ -
~l-l- - - - - - - -
~
-----i
Low= Disable
High = I' Enable
--, r-----lh 1,--_ _ _ _ _ _ _ _ _ _ _ _B_a_tt_er_y_T_e_st_......
~
LED U .. _ ·U
U(Note3)
(Pin 5)
24 Clock Cycles
I~OS)I~.
NOTES:
~
(Notel)n
24 Clock Cycles (0.96 s)
.,e:
1
." Suppressed Chilt--.,
I
:
U(Note3)
24 clock cycles----ll
.,.
:
:
6 Clock Cycles (10.0 s)'"
Horn modulation is self-completing. When going from smoke to no smoke. the alarm condition will terminate only when horn is off.
2. Comparators are strobed on once per clock cycle (1.67 s for no smoke. 40 ms for smoke!.
3. Low battery comparator information is latched only during LED pulse.
4. - 100 mV p-p swing.
®
MC14468
MOTOROLA
Advance Information
CMOS MS.
LOW-COST SMOKE DETECTOR WITH INTERCONNECT
(LOW POWER COMPLEMENTARY MaS)
The MCl4468, when used with an ionization chamber and a small
number of external components, will detect smoke. When smoke is
sensed, an alarm is sounded via an external piezoelectric transducer and
internal drivers. This circuit is designed to comply with the U L217
specification.
LOW-COST SMOKE DETECTOR
WITH INTERCONNECT
• Ionization Type with On-Chip FET Input Comparator
• Piezoelectric Horn Driver
• Guard Outputs on Both Sides of Detect Input
• Input-Protection Diodes on the Detect Input
• Low-Battery Trip Point, Internally Set, Can Be Altered Via
External Resistor
P SUFFIX
PLASTIC PACKAGE
• Detect Threshold, Internally Set, Can Be Altered Via External
Resistor
CASE 648
• Pulse Testing for Low Battery Uses LED for Battery Loading
• Comparator Output for Detect
• Internal Reverse Battery Protection
•
Strobe Output for External Trim Resistors
• I/O Pin Allows Up to 40 Units to be Connected for Common
Signaling
• Power-On Reset Prevents False Alarms on Battery Change
BLOCK DIAGRAM
To Other Units
VDD vDD
I/O
2
Feedback
8
PIN ASSIGNMENT
Detect Compo Out
Sliver
Low V Set - + - - - i . /
[T.\-T'i6p Guard Hi-Z
I/O [ 2
15 P Detect Input
Low V Set [ 3
14
Strobe Out [ 4
13
P Guard Lo-Z
P Sensitivity Set
12
P Osc Capacitor
10
Brass
Detect
Camp Out
LED
VDD 16
Sensitivity 13
Set -+-----1
Timing Resistor
Feedback
LED
Strobe Oul
VDD~
Pin 6
VSS ~ Pin 9
This d"cument contains Information on a new product Specifications and Information herein
are subject to change without notice
8-13
11
Silver
10
n Brass
1..8
_ _ _9....
VSS
II
MC14468
MAXIMUM RATINGS* (Voltages referenced to VSS)
Rating
DC Supply Voltage
Input Voltage, All Inputs Except Pin 8
DC Current Drain per Input Pin, Except Pin 15= 1 mA
Symbol
Value
Unit
VDD
-0.5 to + 15
V
Yin
I
-0.25 toVDD +0.25
V
10
mA
mA
DC Current Drain per Output Pin
I
30
-10 to + 60
°C
Storage Temperature Range
TA
Tstg
-55 to + 125
°C
Reverse Battery Time
tRB
5.0
s
Operating Temperature Range
• Maximum Ratings are those values beyond which damage to the device may occur.
RECOMMENDED DC OPERATING CONDITIONS (Voltages referenced to VSS)
Parameter
Symbol
Value
VDD
9.0
V
-
0.1
Timing Resistor
-
8.2
/L F
MO
Battery Load (Resistor or LED)
-
10
mA
Typ
Supply Voltage
Timing Capacitor
Unit
ELECTRICAL CHARACTERISTICS IT A = 25°C)
Symbol
Voo
Vdc
Min
Max
Unit
Operating Voltage
VDD
-
6.0
-
12
V
Output Voltage
Piezoelectric Horn Drivers "OH = -16 mAl
Comparators "OH = - 30 /LA)
Piezoelectric Horn Drivers "OL = + 16 mAl
Comparators "OL = + 30 /LA)
VOH
7.2
9.0
7.2
9.0
6.3
8.5
-
-
Characteristic
VOL
Output Voltage - LED Driver, 10L = 10 mA
Output Impedance, Active Guard
Operating Current (Rbias =8.2 MOl
VOL
Lo-Z
Hi-Z
IDD
8.8
-
-
-
0.1
0.9
0.5
3.0
V
-
kO
/LA
7.2
-
-
9.0
9.0
-
10
-
500
9.0
12.0
-
5.0
-
-
9.0
12.0
V
Input Current - Detect (40% R.H.)
lin
9.0
-
-
± 1.0
pA
Input Current. Pin 8
lin
9.0
-
-
±0.1
Input Current @ 50°C, Pin 15
lin
-
-
-
+6.0
/LA
pA
Vlow
V set
Vhys
9.0
-
7.2
47
-
50
7.8
53
9.0
75
100
150
9.0
9.0
-
-
±100
±50
-10
-
VDD+ 10
Internal Set Voltage
Low Battery
Sensitivity
II
Pin 14
Pin 16
V
Hysteresis
Offset Voltage (measured at Yin = VDD/2)
Active Guard
Detect Comparator
mV
VOS
-
Input Voltage Range, Pin 8
Yin
-
Input Capacitance
Cin
-
-
5.0
Vcm
-
0.6
-
Common Mode Voltage Range, Pin 15
I/O Current, Pin 2
Input, VOL = VDD - 2
Output, VOH=VDD-2
V
%VDD
mV
-
VDD-2
V
pF
V
/LA
10L
10H
-
25
-4.0
-
100
-16
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation
it is recommended that Yin and Vout be constrained to the range VSS s (Vin or Vout ) s VDD·
8-14
MC14468
TIMING PARAMETERS (C=01I"F, RBias=82 MD, VOO=9.0 V, TA=25°C, See Figure 5)
Characteristics
Oscillator Period
Symbol
Min
Typ
Max
Units
tCI
1.34
32
1.67
40
2.0
48
s
ms
No Smoke
Smoke
Oscillator Rise Time
tr
PW on
PWoff
8
10
12
ms
On Time
Off Time
120
60
160
80
208
104
ms
ms
Between Pulses
On Time
tLED
PW on
32
8
40
10
48
s
ms
On Time
Between Pulses
ton
toff
8
32
10
40
Horn Output
(During Smoke)
LED Output
Horn Output
(During Low Battery)
FIGURE 1 - TYPICAL LED OUTPUT
I-V CHARACTERISTIC
t=
TA
9.0 Vdc
voo
25 0 C
~
TA
I\,
f" ,
25 0 C
~
I
<"
~
<"E
~~
VOO = 9.0 Vdc or 7.2 Vdc
.5- 1.0
I-
Z
7.2 Vdc
Voo
I
a::
a::
..-
:::>
I.
1.0
ms
s
10.0
I--I---
~
12
48
FIGURE 2 - TYPICAL COMPARATOR OUTPUT
I-V CHARACTERISTIC
100.0
z
12
z
~
I.
./
./"
V
0.1
-
9
9
p. CH SOURCE
AND
N·CHSINK
CURRENT
I
0.1
.01
o
10
I
o
10
VOS, ORAIN TO SOURCE VOLTAGE IVdc)
VOS, ORAIN TO SOURCE VOLTAGE (Vdc)
FIGURE 3 - TYPICAL P HORN DRIVER OUTPUT
I-V CHARACTERISTIC
1000.0
1000.0
I--- r-TA
<"E
i
r---- f-
./-'
:::>
V
'-'
z
10.0
f
9
fI-1.0
-.
a::
:::>
= 7.2 Vdc
2:
~
I
o
,
10.0
9
~
VDS. ORAIN TO SOURCE VOLTAGE IVdc)
10
II
7.2 Vdc
=
!-!--
,
o
10
VOS, DRAIN TO SOURCE VOLTAGE IVdc)
8-15
-
V
N· CH SINK CURRENT
--
10
9.0 Vdc
Voo
~ - - - ' - - Voo
'-'
P CH SOURCE CURRENT
---t
.1
~ 100.0 r--
11.
Voo
--j-- -
TA = 25 0 C
r---- r-
<"
=9.0 Vdc
100.0
a::
~
Voo
= 25 0 C r----
MC14468
DEVICE OPERATION
voltage. The I/O is disabled for three oscillator cycles after
power up, to eliminate false alarming of remote units when
the battery is changed.
TIMING
The internal oscillator of the MCl4468 operates with a
period of 1.67 seconds during no-smoke conditions. Each
1.67 seconds, internal power is applied to the entire IC and a
check is made for smoke, except during LED pulse, Low Battery Alarm Chirp, or Horn Modulation (in smokel. Every 24
clock cycles a check is made for low battery by comparing
VDD to an internal zener voltage. Since very small currents
are used in the oscillator, the oscillator capacitor should be
of a low leakage type.
SENSITIVITY/LOW BATTERY THRESHOLDS
Both the sensitivity threshold and the low battery voltage
levels are set internally by a common voltage divider connected between VDD and VSS· These voltages can be
altered by external resistors connected from pins 3 or 13 to
either VDD or VSS. There will be a slight interaction here
due to the common voltage divider network.
DETECT CIRCUITRY
If smoke is detected, the oscillator period becomes 40 ms
and the piezoelectric horn oscillator circuit is enabled. The
horn output is modulated 160 ms on, 80 ms off. During the
off time, smoke is again checked and will inhibit further horn
output if no smoke is sensed. During local smoke conditions
the low battery alarm is inhibited, but the LED pulses at a
1.0 Hz rate. In remote smoke, the LED is inhibited as well.
An active guard is provided on both pins adjacent to the
detect input. The voltage at these pins will be within 100 mV
of the input signal. This will keep surface leakage currents to
a minimum and provide a method of measuring the input
voltage without loading the ionization chamber. The active
guard op amp is not power strobed and thus gives constant
protection from surface leakage currents. Pin 15 (the Detect
input) has internal diode protection against static damage.
TEST MODE
Since the internal op amps and comparators are power
strobed, adjustments for sensitivity or low battery level could
be difficult and/or time-consuming. By forcing Pin 12 to
V S S, the power strobing is bypassed and the output, Pin 1,
constantly shows smoke/no smoke. Pin 10= VDD for smoke.
In this mode and during the 10 ms power strobe, chip current
rises to approximately 50 /-tA.
LED PULSE
The 9-volt battery level IS checked every 40 seconds during
the LED pulse. The battery IS loaded via a 10 mA pulse for
10 ms. If the LED IS not used, it should be replaced with an
eqUivalent resistor such that the battery loading remains at
10 mAo
INTERCONNECT
The I/O (Pin 2), in combination with VSS, is used to interconnect up to 40 remote units for common signaling. A
Local Smoke condition activates a current limited output
driver, thereby signaling Remote Smoke to interconnected
units. A small current sink improves noise immunity during
non-smoke conditions. Remote units at lower voltages do
not draw excessive current from a sending unit at a higher
HYSTERESIS
When smoke IS detected, the resistor/divider network that
sets sensitivity IS altered to increase sensitivity. This Yields
approximately 100 mV of hysteresis and reduces false triggering
FIGURE 4 - TYPICAL APPLICATION AS IONIZATION SMOKE DETECTOR
1M
r-
1
220 kn *
* NOTE:
Component values may change uef.)t:::rluirIY UII type of piezoelaCiTiC horn used.
8-16
Test
3:
o
.....
~
~
m
co
FIGURE 5 -
Standby:
No Smoke/
No Low Battery
I.
TIMING DIAGRAM
Smoke/Low Battery
• I'lli{
Smoke/No Low Battery
.111(
• I'lli{
10 ms
40 ms~ ~
O~~ii~a~~~
~~
.1
No Smoke/Low Battery
+i
J.-1.67 s
~
P-J't
Detect out -, r--T rl!
(Pin II
U U
Inn n
rih r--1 r--1r-1 r - I r--T r--1 r--1 r--T I
U U U U U U U U U U
r-I
UUUU
Low Battery -, r--T ri
(Internall
U U
HysteresIs (Internali
.
I
(Pin 131 (Note41 ~~
Sample (Internall
Smoke
cp
I
.
~f-I--------------.
n
n n n n n
n
!--l L--.-..J L-..J L-..J L-..J L-J L--.-..J I
---i
Horn
(Pins 10 & 111
(Notell
~
l
-L
I
I
"'""'-J
)!----,I INote 31
,.------------{\
LED
(Pin 51
U
::
I
l--'l.~I""'lII{f- 6 Clock Cycles (10.0 sl ~
1nrlnrlruuuU
Strobe Out
(Pin 141
I/O (Pin 21
Output (Local!
.
f-
~!r_--------------
----i/------J
I/O (Pin 21
rr------------------------~
Input (Remotel ~~
~I Note: Horn Modulation Not Self-Completing
LED
~1J
(Suppressed LED for Remote Onlyl
!~r------------
NOTES' 1 Horn modulation is self-completing. When going from smoke to no smoke, the alarm condition wrll termInate only when horn is off.
2. Comparators are strobed on once per clock cycle 11.67 s for no smoke, 40 ms for smokel
Low battery comparator Information is latched only during LED pulse.
4 - 100 mV p.p swing.
____L
II
8-18
Miscellaneous Functions
II
9-1
,.. "
.. ...
~
"."."...."
.--
MISCELLANEOUS FUNCTIONS
Device
'Number
Function
MCl4460 Automotive Speed Control Processor
MCl4490 Hex Contact Bounce Eliminator
MC14500B Industrial Control Unit
II
9-2
®
MC14460
MOTOROLA
CMOS LSI
AUTOMOTIVE SPEED CONTROL PROCESSOR
(LOW-POWER COMPLEMENTARY MOS)
The MC14460 device is designed to measure vehicle speed and
provide pulse-width modulated outputs to trim a throttle positioning servo to maintain an internally stored reference speed.
The stored reference speed Can be altered by the DECEL and
ACCEL driver commands. The DECEL command trims down the
speed, while ACCEL trims up the speed.
A BRAKE input is provided to turn off the outputs with a
RESUME driver command to return the vehicle to the last stored
speed.
AUTOMOTIVE SPEED
CONTROL PROCESSOR
•
On-Chip Master Oscillator for System Time Reference
•
Separate On-Chip Pulse Oscillator for Output Pulse Width
Adjustment (Analogous to System Gain)
•
P SUFFIX
PLASTiC PACKAGE
CASE 648
Diode Protection on All Inputs
•
Internal Redundant Brake and Minimum Speed Checks
•
Acceleration Rates Controlled During ACCEL and RESUME
Modes of Operation
•
Low Frequency Speed Sensors Used
PIN ASSIGNMENT
•
No Throttle Position Feedback Required
•
Power-On Reset
•
Buffered Outputs Compatible with Discrete Transistor
Driver Interface
•
Low Power Dissipation
16
15
14
13
12
11
10
BLOCK DIAGRAM
9
Pulse
Width
Converter
DEC
ACC
RES
BRK
POOo-----J
Vee
= Pin
16
VAC
VSS = Pin 8
9-3
This device contains circuitry to protect
the inputs against damage due to high static
voltages Or electric fields; however, it is
advised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to this high
impedance circuit. For proper operation it
is recommended that Vin and V out be
constrained to the range VSS .;; (Vin or
V out )';; VOO'
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VOO).
II
MC14460
MAXIMUM RATINGS (Voltages referenced to Vss)
Rating
Symbol
Unit
Value
DC Supply Voltage
VDD
-0.5 to +6.0
Vdc
Input Voltage, All Inputs
Vin
-0.5 to VDD + 0.5
Vdc
lin
±10
mAdc
Operating Temperature Range -
DC Input Current, per Pin
TA
-40 to +85
Storage Temperature Range
T stg
-65 to +150
°c
°c
ELECTRICAL CHARACTERISTICS (T A = -40 0 C to +85 0 C)
Characteristic
Symbol
VDD
Vdc
Min
Typ
Max
Unit
VOO
-
4.0
5.0
6.0
Vdc
-
0.5
Vdc
Supply Voltage
Pin 16
Output Voltage
Pins 1,2,5,6,14,15
Input Voltage
Pi ns 3, 7, 9, 10, 11, 12, 13
Pin 4
Input Hysteresis
Pin 4
(VIH - VIL)
VOL
5.0
-
VOH
5.0
4.5
VIL
-
-
VIH
-
0.7 VOO
VIL
-
VOO -1.5
2
VIH
-
-
HYS
-
0.4
Vdc
0.3 VOO
Vdc
-
Vdc
-
-
Vdc
-
VOO +15
2
.
Vdc
-
Vdc
Output Drive Current
Pins 1, 2, 5,6
VOH= 4.6 Vdc
IOH
5.0
-0.29
-
-
mAdc
VOL = 0.4 Vdc
IOL
5.0
+0.36
-
-
mAdc
Pins 14, 15
VOH = 2.5 Vdc
IOH
5.0
-2.0
-
-
mAde
Input Current
Pins 3,4, 7,10,11,12,13
VIL = 0.0 Vde
IlL
6.0
-
/LAd.::
IIH
6.0
-
-
-1.0
VOH = 6.0 Vdc
+1.0
/LAdc
Pin 9
VIL = 0.0 Vde
IlL
6.0
15
-
200
/LAde
VIH = 6.0 Vde
IIH
6.0
-
-
+1.0
/LAdc
100
6.0
-
1.0
10
mAdc
Supply Current
Pin 16
(Both Oscillators Active, VAC and
VENT Outputs High)
FIGURE 1 - SYSTEM TIMING
II
-
**FIGURE 2 - OSCILLATORS
JoooI:f-----~m" ~r-
Internali
To Internal Clock
'<,0
Speed
Sample I
Gate.:.....J
I"
Frequency of
Oscillation as
Measured at
Pin 1 (5) is:
I
VAC
f
= - 1- 2.43RC
R in kn
RS
R
C in J.lF
Asynchronous to
Speed Sample
RS '" 2R
f
9-4
= kHz
MC14460
SWITCHING CHARACTERISTICS (T A = 25°C, VOO = 4-6 Vdc)
Symbol
Min
Typ
Max
Unit
ACCEL Input Hold Time
Characteristics
tACC
16/fM
9.52"
-
ms
OECEL Input Hold Time
tOEC
16/fM
9.52*
-
ms
RESUME Input Hold Time
tRES
1
-
JJS
BRAKE Input Hold Time
tBRK
1
-
-
JJS
fM
1596
1344
16BO
16S0
1164
2016
Hz
Hz
fp
1596
400
16S0
1600
1764
3200
Hz
Hz
fS
-
-
300
Hz
600*
-
ms
-
ms
760*
SO*
ms
ms
Master Oscillator Frequency**
T A = -40°C to +S50C, RS = 100 kll
R = 43 kll, C = 5600 pF
Useful Range
Pulse Oscillator Frequency**
T A = -40 o C to +S5 0 C, RS
R = 43 kll, C = 5600 pF
Useful Range
= 100
kll
Speed Input Frequency
Speed Sample Time (100S/fM)
tsmpl
Speed Processing Time (16/fM)
tproc
System Cycle Time (1024/fM)
tcyc
Output Delay Time (9ifM)
tout
-
Output Pulse Width
Initializations ("" 1/f p)
Trim Outputs (""l/fp)
PWI
PWT
2S0*
10*
*fM
= 16S0
Hz, fp
= 1600
Hz, fS
= 2.222
S.9*
60S.9*
5.4*
-
ms
ms
Hz/MPH
SYSTEM PERFORMANCE (T A = 25 0 C, VOO = 5 Vdc, fM = 16S0 Hz, fS = 2.222 Hz/MPH)
Characteristic
Symbol
Typical
Unit
SRES
0.375
MPH
Speed Resolution (fM/2016 fS)
Minimum Operating Speed (fM/31.5 fS)
Smin
24
MPH
Maximum Stored Speed (fM/S.4 fS)
Smax
A
90
MPH
1.85
MPH/s
SRB
-12
MPH
Level Road (no wind, ± 1% grades)
.,.
BRAKE
SP~
GND
Lights
SENSOR
Electromagnetic Type
POles:
Output Freq:
Output Voltage:
Maximum Freq:
DC Resistance:
9-7
8/revolution
2.222 Hz/MPH
(8000 pulses/mile)
> 3.0 Vp-p @ 24 MPH
360 Hz (162 MPH)
<40n
MC14460
DEVICE OPERATION continued
mand is received. The flow diagram in Figure 3 gives the
detailed constraints/operation of this input.
RESUME (RES, Pin 12)
VENT (Pin 14)
This is the RESUME command input. When taken
HIGH the system will lock into a mode where the VAC
and VENT outputs are modulated to maintain a fixed rate
acceleration. This acceleration ends when the SPD input
sample matches the stored reference speed. The flow diagram in Figure 3 gives the detailed constraints/operation
of this input.
This is the VENT output.
operation.
See Truth Table for
VAC (Pin 15)
This is the VAC output. See Truth Table for operation.
GROUND (V SS , Pin 8)
Pin 8 is the ground connection for the package.
BRAKE (BRK, Pin 13)
This is the BRAKE command input. When this input is
taken HIGH the system is disabled (both VAC and VENT
outputs LOW) until a DECEL, ACCEL, or RESUME com-
POSITIVE POWER SUPPLY (VDD, Pin 16)
Pin 16 is the power supply connection for the package.
FIGURE 5 - PC BOARD MODULE FOR CRUISE CONTROL
VENT Coil
<100mAVAC Coil
<100mACoil COM
130
2W
0
Voo
~N
1 k
-Sensor
lW
4.7 V
lM4.7Z10 ~
~
MPSA~
+ 50
;; r- 25 V
0
~
~
~PSA13
~~ 27 V
~~ 1 W
N
~
~7WV ~~
1 k
1 k
16
4
VDD
0-- SPD
47 k
+Sensor
47 k
Brake
47 k
I
I
0.01
I(
-"'-
10
1\
~
Decel
~
47 k
0.01
J(
0.01
47 k
I
I
0.01
Accel
Resume
II
10 k
10 k
7
100 k
BRK
6
5100,5%
5
43 k, 1%
M02
0.01
J(
r
14
M03
13
1\
15
c
VAC
VENT
MC14460
DEC
MOl
1\
~
3
P03
11
1\
ACC
~
1
12
1\
RES
Gnd
100 k
~
2
P02
J(
JL
5100,5%
JL
1\
43 k, 1%
POl
POR
II
8(
1\
9 (
10 k
*0.1
Gnd
All Resistors
±10%, 1/4 W, U.O.S.
Environment
Ambient Temperature (T A) . . . . . -40°C to 85°C
V CC Operating Range . . . . . . ..
11-15 Vdc
VCC Transients . . . . . . . . . . . . 9-16 Vdc
Load Dump . . . . . . . . . . 80 V Peak decaying to
12 V in < 200 ms
Inductive
. . . . . . . . . . . ±300 V Peak decaying
in
Jump Start
< 1 ms
. . . . . . . . • . +24 Vdc for 5 min.
Reverse Battery. . . . . . . . -12 Vdc continuous
9-8
®
MCl4490
MOTOROLA
HEX CONTACT BOUNCE ELIMINATOR
CMOS LSI
The MC14490 is constructed with complementary MOS enhancement mode devices, and is used for the elimination of extraneous level
changes that result when interfacing with mechanical contacts. The
digital contact bounce eliminator circuit takes an input signal from a
bouncing contact and generates a clean digital Signal four clock periods
after the input has stabilized. The bounce eliminator circuit will remove
bounce on both the "make" and the "break" of a contact closure. The
clock for operation of the MC14490 is derived from an internal R-C
oscillator which requires only an external capacitor to adjust for the
desired operating frequency (bounce delay). The clock may also be
driven from an external clock source or the oscillator of another
MC14490 (see Figure 5),
(LOW-POWER COMPLEMENTARY MOSI
HEX CONTACT
BOUNCE ELIMINATOR
L SUFFIX
CERAMIC PACKAGE
CASE 620
• Diode Protection on All Inputs
•
•
•
•
Noise Immunity=45% of VDD Typical
Six Debouncers Per Package
Internal Pullups on All Data Inputs
Can Be Used as a Digital Integrator, System Synchronizer, or Delay
Line
P SUFFIX
PLASTIC PACKAGE
CASE 648
• Internal Oscillator (R-C), or External Clock Source
• TTL Compatible Data Inputs/Outputs
• Single Line Input, Debounces Both "Make" and "Break" Contacts
• Does Not Require "Form C" (Single Pole Double Throw) Input
Signal
ORDERING INFORMATION
• Cascadable for Longer Time Delays
• Schmitt Trigger on Clock Input (Pin 7)
Denotes
Ceramic Package
Plastic Package
• Supply Voltage Range=3.0 V to 18 V
• Chip Complexity: 546 FETs or 136.5 Equivalent Gates
BLOCK DIAGRAM
+VOO
voo = Pin 16
vss = Pin 8
<1>1
Gin
+
<1>2
+
Identical to Above Stage
Bin
3~
<1>1
* *
f--
2
Bout
<1>2
Identical to Above Stage
f - - 1 3 Cout
~--------------------------------------------~
<1>1
* *
<1>1
+
<1>2
to_Above
Stage
Oin12~L -_ _ _ _ _ _ _ _ _ _ _ _Identical
_____
____
________________
Ein
Fin
5~
<1>2
f--4
~
*
Identical to Above Stage
~--------------------------------------------~f - -
10
---I
<1>1
Identical to Above Stage
*
<1>2+
r-
~--------------------------------------------~
9-9
°out
11
6
E out
F out
MC14490
MAXIMUM RATINGS (Voltages referenced to VSS, Pin 8.)
Rating
DC Supply Voltage
Input Voltage, All Inputs
DC Input Current, per Pin
PIN ASSIGNMENT
Symbol
Value
Unit
VDD
-0.5 to + 18
V
Ain
VDD
Yin
-0.5 to
VDD+05
V
Bout
Aout
MCl4490L
MCl4490P
TA
Cin
mA
+10
lin
Operating Temperature Range
-55 to + 125
- 50 to +85
°C
Storage Temperature Range
Tstg
-65 to + 150
°C
Po
500
mW
FOU!
Eout
Fin
OS C out
VSS
.
ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSS)
Characteristic
Symbol
"0" Level
VOL
"1" Level
VOH
Voo
Vdc
-
10
-
15
-
5.0
4.95
9.95
14.95
15
"0" Level
T,ow
Min Max
5.0
10
Vin =0 or VOO
Thigh·
25°C
Typ
Max
Min
Max
0.05
0.05
0.05
-
0
0
0
0.05
0.05
0.05
-
0.05
0.05
0.05
V
-
4.95
9.95
14.95
5.0
10
15
-
4.95
9.95
14.95
-
V
-
2.25
4.50
6.75
1.5
3.0
4.0
2.75
-
5.50
-
8.25
-
-
-
-
-
-
-
-
V
-
5.0
10
15
-
5.0
10
15
3.5
7.0
11.0
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
V
VIH
IVO=05 or 4.5 V)
IVO = 1.0 or 9.0 V)
IVO= 1.5 or 13.5 V)
Output Drive Current
Source
Oscillator Output
IVOH = 2.5 V)
IVOH=4.6 V)
IVOH =9.5 V)
IVOH = 13.5 V)
Oebounce Outputs
IVOH =2.5 V)
IVOH=4.6 V)
IVOH=95V)
IVOH = 13.5 V)
IOH
Sink
Oscillator Output
(VOL=OA V)
(VOL = 0.5 V)
(VOL=1.5V)
Debounce Outputs
(VOL =OA V)
(VOL =0.5 V)
(VOL = 1.5 V)
IOL
Unit
Min
VIL
"1" Level
II
Din
Os c in
tPower DIssipation Temperature Derating
Plastic" P" Package - 12 mW / °C from 65 to 85°C
Ceramic "L" Package - 12 mW/oC from 100 to 125°C
Input Voltage #
(VA = 4.5 or 0.5 VI
IVO=9.0 or 1.0 VI
IVa = 13.5 or 1.5 V)
Cout
Ein
Power Dissipation, per Packaget
Output Voltage
Vln = VOO or 0
Bin
Dout
-
3.5
7.0
11.0
3.5
7.0
11.0
-
mA
5.0
5.0
10
15
-0.6
-0.12
- 0.23
-
-lA
-
5.0
5.0
10
15
-0.9
-0.19
-0.6C
-18
-
-
-
-
- 0.5 -15
-0.1 -0.3
- 0.20 -O.B
-1.2 -3.0
-0.75 -22
-016 - OA6
-0.50 -1.2
-1.5 -4.5
--
-OA
-
-
-O.OB
-0.16
-10
-
-
-
-0.6
-0.12
-
-
-OA
-
-
- 1.2
-
-
-
mA
-
5.0
10
15
0.36
0.9
4.2
5.0
10
15
2.6
4.0
12
-
-
-
0.30
0.75
3.5
0.9
2.3
10
4.0
9
35
0.2
0.24
0.6
2.B
-
-
1.B
2.7
B.l
-
2
-
11
-
±250
p.A
130
265
400
p.A
-
-
-
-
2.2
3.3
10
Input Curren!
Debounce Inputs (Vin = VDO)
IIH
15
-
2
-
Input Current Oscillator -
lin
15
-
±620
-
Pullup Resistor Source Current
Debounce Inputs
(Vin=VSS)
IlL
5.0
10
15
210
415
610
375
740
1100
140
280
415
190
3BO
570
750
70
145
215
Input Capacitance
Cin
-
-
-
-
5.0
7.5
-
-
pF
Quiescent Current
(Vin=VSS orVDD, 10ut=0p.A)
ISS
5.0
10
15
-
150
2BO
840
-
40
90
225
100
225
650
-
90
lBO
550
p.A
Pin 7 (Vin = VSS or VDD)
#NOfSC :mmunity spec~fied for \Norst case combination
Noise margin for both "1" and "0" level = 1.0 V min @ VOD=5.0 V
2.0 V min @ VOD= 10 V
2.5 V min @ VOO= 15 V
9-10
-
-
-
-
-
-
±255 ±400
255
500
-
-
• T low = - 55°C for L Device, - 40 ° C for P DeVice
Thigh= + 125°C for L DeVice, +B5°C for P DeVice
p.A
MC14490
SWITCHING CHARACTERISTICS ICL = 50 pF, TA = 25°Cl
Characteristic
Symbol
VDD
Vdc
tTLH
5.0
10
15
Output Rise Time
All Outputs
Min
Typ
Max
Unit
-
180
90
65
360
180
130
ns
-
100
50
40
-
60
-
30
20
200
100
80
120
60
40
285
120
95
570
240
190
370
160
120
740
320
240
2.8
6
9
14
3.0
4.5
MHz
50
-
ns
40
30
-
-
ns
Output Fall Time
Oscillator Output
tTHL
5.0
10
15
5.0
10
15
tTHL
Debounce Outputs
Propagation Delay Time
Oscillator Input to Debounce Outputs
-
-
ns
tPHL
tPLH
Clock Frequency 150% Duty Cycle)
IExternal Clock)
fcl
Setup Time I See Figure 1)
tsu
Maximum External Clock Input
Rise and Fall Time
Oscillator Input
-
5.0
10
15
-
5.0
10
15
-
5.0
10
15
tr,tf
Oscillator Frequency
OSC out
Cex t2: 100 pF*
5.0
10
15
fosc, typ
-
-
-
100
80
50
-
ns
5.0
10
15
No Limit
5.0
----
10
----
15
----
1.5
Hz
Cext lin I'F)
4.5
Cext (in I'F)
6.5
Cext (In I'F)
*POWER-DOWN CONSIDERATIONS
Large values of Cext may cause problems when powering down the MCl4490 because of the amount of energy stored in the capacitor. When
a system containing this device is powered down, the capacitor may discharge through the input protection diodes at Pin 7 or the parasitic
diodes at Pin 9. Current through these internal diodes must be limited to 10 mA; therefore the turn-off time of the power supply must not be
faster than t = IVDD - V S s) • Cext / I 10 mA). For example, if VDD - V SS = 15 V and Cext = 1 I'F, the power supply must turn off no faster than
t = 115 V) • I 1 I'F) / 10 mA = 1.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate
When a more rapid decrease of the power supply to zero volts occurs, the MCl4490 may sustain damage To avoid this possibility, use external clamping diodes, Dl and D2, connected as shown in Figure 2
FIGURE 1 -
SWITCHING WAVEFORMS
FIGURE 2 - DISCHARGE PROTECTION
DURING POWER DOWN
-VDD
Dl
'------0 V
Cext
Aout
Aout
MCl4490
---------
-
VDO
50j
f;)%t""
-------::D
ov
9-11
02
MC14490
THEORY OF OPERATION
After some time period of N clock periods, the contact is
opened and at N + 1 a low is loaded into the first bit. Just
after N + 1, when the input bounces low, all bits are set to a
high. At N + 2 nothing happens because the input and output are low and all bits of the shift register are high. At time
N + 3 and thereafter the input signal is a high, clean signal.
At the positive edge of N + 6 the output goes high as a result
of four lows being shifted into the shift register.
Assuming the input signal is long enough to be clocked
through the Bounce Eliminator, the output signal will be no
longer or shorter than the clean input signal plus or minus
one clock period.
The amount of time distortion between the input and
output signals is a function of the difference in bounce
characteristics on the edges of the input signal and the clock
frequency. Since most relay contacts have more bounce
when making as compared to breaking, the overall delay,
counting bounce period, will be greater on the leading edge
of the input signal than on the trailing edge. Thus, the output
signal will be shorter than the input signal - if the leading
edge bounce is included in the overall timing calculation.
The only requirement on the clock frequency in order to
obtain a bounce free output signal is that four clock periods
do not occur while the input signal is in a false state. Referring to Figure 3, a false state is seen to occur three times at
the beginning of the input signal. The input signal goes low
three times before it finally settles down to a valid low state.
The first three low pulses are referred to as false states.
If the user has an available clock signal of the proper frequency, it may be used by connecting it to the oscillator input (pin 7). However, if an external clock is not available the
user can place a small capacitor across the oscillator input
and output pins in order to start up an internal clock source
(as shown in Figure 4). The clock signal at the oscillator output pin may then be used to clock other MC14490 Bounce
Eliminator packages. With the use of the MC14490, a large
number of signals can be cleaned up, with the requirement
of only one small capacitor external to the Hex Bounce
Eliminator packages.
The MC14490 Hex Contact Bounce Eliminator is basically
a digital integrator. The circuit can integrate both up and
down. This enables the circuit to eliminate bounce on both
the leading and trailing edges of the signal, shown in the timing diagram of Figure 3.
Each of the six Bounce Eliminators is composed of a
4 Y2 -bit register (the integrator) and logic to compare the
input with the contents of the shift register, as shown in
Figure 4. The shift register requires a series of timing pulses
in order to shift the input signal into each shift register
location. These timing pulses (the clock signal) are
represented in the upper waveform of Figure 3. Each of the
six Bounce Eliminator circuits has an internal resistor as
shown in Figure 4. A pullup resistor was incorporated rather
than a pulldown resistor in order to implement switched
ground input signals, such as those coming from relay contacts and push buttons. By switching ground, rather than a
power supply lead, system faults (such as shorts to ground
on the signal input leads) will not cause excessive currents in
the wiring and contacts. Signal lead shorts to ground are
much more probable than shorts to a power supply lead.
When the relay contact is open, (see Figure 4) the high
level is inverted, and the shift register is loaded with a low on
each negative edge of the clock signal. To understand the
operation, we assume all bits of the shift register are loaded
with lows and the output is at a high level.
At clock edge 1 (Figure 3) the input has gone low and a
high has been loaded into the first bit or storage location of
the shift register. Just after the negative edge of clock 1, the
input signal has bounced back to a high. This causes the
shift register to be reset to lows in all four bits - thus starting the timing sequence over again
During clock edges 3 to 6 the input signal has stayed low.
Thus, a high has been shifted into all four shift register bits
and, as shown, the output goes low during the positive edge
of clock pulse 6.
It should be noted that there is a 3'h to 4 Y2 clock period
delay between the clean input signal and output signal. In
this example there is a delay of 3.8 clock periods from the
beginning of the clean input signal.
FIGURE 3 -
TIMING DIAGRAM
N+ 1
4
N+3
N+5
OSCin or OSCout
II
Inpu t
I1l1f1.f1
,
t
I
Outpu t
.n
\\
Contact Open
Contact Closed
Contact
Open
Contact
Bouncing
(Valid True Signal)
Contact
Bouncing
9-12
N+7
MC14490
FIGURE 4 - TYPICAL "FORM A" CONTACT DEBOUNCE CIRCUIT
(Only One Oebouncer Shownl
+VDD
~OA~,~_in----~.---~
=
Contact
OPERATING CHARACTERISTICS
paralleled standard gates or by the MCl4049 or MCl4050
buffers.
The clock input circuit (pin 7) has Schmitt trigger shaping
such that proper clocking will occur even with very slow
clock edges, eliminating any need for clock preshaping. In
addition, other MCl4490 oscillator inputs can be driven from
a single oscillator output buffered by an MC14050 (see
Figure 5). Up to six MCl4490s may be driven by a single buffer.
The MCl4490 is TTL compatible on both the inputs and
the outputs. When VDD is at 4.5 V, the buffered outputs can
sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as a
result of the internal input pullup resistors.
The single most important characteristic of the MCl4490 is
that it works with a single signal lead as an input, making it
directly compatible with mechanical contacts (Form A and
B).
The circuit has a built in pullup resistor on each input. The
worst case value of the pullup resistor (determined from the
Electrical Characteristics table) is used to calculate the contact wetting current. If more contact current is required, an
external resistor may be connected between VDD and the input.
Because of the built-in pullup resistors, the inputs cannot be driven with a single standard CMOS gate when VDD
is below 5 V. At this voltage, the input should be driven with
FIGURE 5 - TYPICAL SINGLE OSCILLATOR
DEBOUNCE SYSTEM
OSCin
From
Contacts
From Contacts
MC14490
MC14490
To System
Logic
•
7.••
To System
Logic
F rom Contacts
9-13
MC14490
To System
Logic
II
MC14490
TYPICAL APPLICATIONS
ASYMMETRICAL TIMING
MULTIPLE TIMING SIGNALS
In appl ications where different leadi ng and trail ing
edge delays are required (such as a fast attack/slow release
timer.) Clocks of different frequencies can be gated into
the MC14490 as shown in Figure 6. In order to produce a
slow attack/fast release circuit leads A and B should be
interchanged. The clock out lead can then be used to
feed clock signals to the other MC14490 packages where
the asymmetrical input/output timing is required.
As shown in Figure 8, the Bounce Eliminator circuits
can be connected in series. In this configuration each
output is delayed by four clock periods relative to its
respective input. This configuration may be used to gener·
ate multiple timing signals such as a delay line, for
programming other timing operations.
One application of the above is shown in Figure 9,
where it is required to have a single pulse output for a
single operation (make) of the push button or relay contact.
This only requires the series connection of two Bounce
Eliminator circuits, one inverter, and one NOR gate in
order to generate the signal AB as shown in Figures 9 and
10. The signal AS is four clock periods in length. If the inverter is switched to the A output, the pulse AS will be
generated upon release or break of the contact. With the use
of a few additional parts many different pulses and
waveshapes may be generated.
FIGURE 6 - FAST ATTACK/SLOW RELEASE
CIRCUIT
OSCout
FIGURE 8 - MULTIPLE TIMING CIRCUIT CONNECTIONS
K>--- - - - ( ) - - Sou t
LATCHED OUTPUT
The contents of the Bounce Eliminator can be latched
by using several extra gates as shown in Figure 7. If the
latch lead is high the clock will be stopped when the
output goes low. This will hold the output low even
though the input has returned to the high state. Any time
the clock is stopped the outputs will be representative of
the input signal four clock periods earlier.
K > - - - ( ) - - C ou t
K>------ F out
II
1----+_ OSCout
,
Clock
OSCin
Latch = 1
Unlatch = 0
9-14
1
,
~oscout
MC14490
FIGURE 9 - SINGLE PULSE OUTPUT CIRCUIT
A :; Active Low
S "" Active Low
FIGURE 10 - MULTIPLE OUTPUT SIGNAL TIMING DIAGRAM
OSCin or
OSCout
II
A
B
c
c'~,--_ _ _ _ _---,I
o
))
((
AS - - - - - - - - - - '
AB----------------------------------T('(~------------~
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit For proper
operation it is recommended that Vin and V out be constrained to the range VSS:5(Vin or V ou t):5VDD
9-15
I
@ MOTOROLA
MC14500B
INDUSTRIAL CONTROL UNIT
CMOS LSI
The MC14500B Industrial Control Unit (ICUI is a single-bit
CMOS processor- The ICU is designed for use in systems requiring
decisions based on successive single-bit information. An external
ROM stores the control program. With a program counter (and
output latches and input multiplexers, if required) the ICU in a
system forms a stored-program controller that replaces combinatorial
logic. Applications include relay logic processing, serial data manipulation and control. The ICU also may control an MPU or be
controlled by an MPU.
•
16 Instructions
•
DC to 1.0 MHz Operation at VDD
•
On-Chip Clock (Oscillator)
•
Executes One Instruction per Clock Cycle
•
3 to 18 V Operation
•
Noise Immunity Typically 45% of VDD
(LOW-POWER COMPLEMENTARY MOS)
INDUSTRIAL CONTROL UNIT
=5 V
L SUFFIX
P SUFFIX
CERAMIC PACKAGE
CASE 620
PLASTIC PACKAGE
CASE 648
ORDERING INFORMATION
•
low Quiescent Current Characteristic of CMOS Devices
•
Capable of Driving One low-Power Schottky Load or Two
Low-Power TTL Loads over Full Temperature Range
•
Detailed Operation and Applications Given in Handbook
HB-209
•
Development System Described in Application Note AN-889
Me,.x"",
I1SUffiX
L
P
A
C
Denotes
Ceramic Package
Plastic Package
Extended Operating
Temperature Range
Limited Operating
Temperature Range
BLOCK DIAGRAM
Data
PIN ASSIGNMENT
Write
16
lEN
I
15
VSS
X1~
1 13
OSC
14
4
X2
13
12
15
10
11
INST
REG
12
13
RST
4
~
n
REG. (RR)
RR
AI-
11
10
12
rJ Lj I--11
~I---
JMP
RTN
10
~r!
Flag 0
FlagF
' - - - - - -_ _ _I L - - - I_ - - - - '
9-16
MC14500B
MAXI MUM RATI NGS (Voltages referenced
Rating
to VSS)
Symbol
Value
Unit
VDD
-0.5 to +18
V
Input Voltage, All Inputs
Vin
-0.5 to VD D + 0.5
V
DC Input Current, per Pin
lin
±10
mA
DC Supply Voltage
Operating Temperature Range - A L Device
CLlCP Device
TA
-55 to +125
-40 to +85
°c
Storage Temperature Range
T stg
-65 to +150
°c
ELECTRICAL CHARACTERISTICS (Voltages Referenced
to VSS)
VDD
Characteristic
Output Voltage
Symbol
V
"0" Level
VOL
5.0
10
15
"1" Level
VOH
5.0
10
15
"0" Level
VIL
Yin = VDD or 0
Yin = 0 or VDD
Input Voltage
RST,D,X2
(VO = 4.5 or 0.5 V)
(Va = 9.0 or 1.0 V)
(Va = 13.5 or 1.5 V)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Output Drive Current
Other Outputs (AL Device)
(VOH
(VOH
(VOH
(VOH
=
=
=
=
Source
Output Drive Current
Other Outputs (CL/CP Device)
(VOH = 2.5 V)
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL=1.5V)
0.05
0.05
0.05
Max
Unit
0.05
0.05
0.05
V
V
4.95
9.95
14.95
5.0
10
15
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
3.5
7.0
11.0
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
V'
0.8
1.6
2.4
1.1
2.2
3.4
0.8
1.6
2.4
0.8
1.6
2.4
5.0
10
15
2.0
6.0
10
2.0
6.0
10
1.9
3.1
4.3
2.0
6.0
10
5.0
10
15
-1.2
-3.6
-7.2
-1.0
-3.0
-6.0
-2.0
-6.0
-12
-0.7
-2.1
-4.2
5.0
10
15
1.9
3.6
7.2
1.6
3.0
6.0
mA
IOH
Sink
IOL
Source
IOH
Sink
IOL
Source
IOH
Sink
0
Min
VIH
2.5 V)
4.6 V)
9.5 V)
13.5 V)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Max
0
4.95
9.95
14.95
1.5
3.0
4.0
5.0
10
15
"1" Level
Typ
VIL
(Va = 0.5 or 4.5 V)
(Va = 1.0 or 9.0 V)
(Va = 1.5 or 13.5 V)
Output Drive Current
Data, Write (AL/CL/CP Device)
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
0.05
0.05
0.05
4.95
9.95
14.95
Thigh *
25 0 C
Min
V
5.0
10
15
"0" Level
Max
VIH
(Va = 0.5 or 4.5 V)
(Va = 1.0 or 9.0 V)
(Va = 1.5 or 13.5 V)
Input Voltage #
10,11,12,13
(VO = 4.5 or 0.5 V)
(Va = 9.0 or 1.0 V)
(Va = 13.5 or 1.5 V)
Tlow *
Min
5.0
10
15
"1" Level
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high Impedance circuit. For proper
operation it is recommended that Vin and
V out be constrained to the range VSS .;;
(Vin or V out )';; VDD.
IOL
3.2
6.0
12
1.1
2.1
4.2
mA
5.0
5.0
10
15
-3.0
-0,64
-1.6
-4.2
-2.4
-0.51
-1.3
-3.4
-4.2
-0.88
-2.25
8.8
-1.7
-0.36
-0.9
-2.4
5.0
10
15
0.64
1.6
4.2
0,51
1.3
3.4
0.88
2.25
8,8
0.36
0.9
2.4
5.0
5.0
10
15
-2.5
-0.52
-1.3
-3,6
-2.1
-0.44
-1.1
-3.0
-4.2
-0.88
-2.25
-8.8
-1.7
-0.36
-0.9
-2.4
5.0
10
15
0.52
1.3
3,6
0.44
1.1
3.0
0.88
2,25
8.8
0.36
0,9
2.4
II
mA
9-17
MC14500B
ELECTRICAL CHARACTERISTICS (continued)
25°C
Tlow *
Voo
Thigh*
Max
Characteristic
Symbol
V
Min
Max
Min
Typ
Max
Min
Input Current, RST (AL/Cl/CP Device)
lin
15
25
-
150
-
-
250
JJA
Input Current (Al Device)
lin
15
-
±0.1
±0.00001
±0.1
-
± 1.0
JJA
Input Current (CL/CP Device)
lin
15
-
±0.3
±0.00001
±0.3
-
± 1.0
JJA
Input Capacitance (Data)
Cin
-
-
15
-
-
pF
Cin
-
-
-
Input Capacitance (All Other Inputs)
-
5.0
7.5
-
-
pF
Quiescent Current (Al Device)
(Per Package) lout = 0 JJA,
Vin=O or VDD
IDD
5.0
10
15
-
5.0
10
20
0.005
0.010
0.015
5.0
10
20
-
150
300
600
JJA
Quiescent Current (CL/CP Device)
(Per Package) lout = 0 JJA,
Vin=O or VDD
IOD
5.0
10
15
-
20
40
80
-
0.005
0.010
0.015
20
40
80
150
300
600
JJA
**Total Supply Current at an External
load Capacitance (Cl) on
All Outputs
IT
-
-
-
IT = (1.5 JJA/kHz) f
IT = (3.0 JJA/kHz) f
IT = (4.5 JJA/kHz) f
-
-
-
+ 100
+ 100
+ 100
Unit
JJA
* Tlow = -55°C for Al Device, -40°C for CL/CP Device.
Thigh = +125 0 C for Al Device, +85 0 C for CL/CP Device.
** The formulas given are for the typical characteristics only at 25°C.
SWITCHING CHARACTERISTICS ITA = 25°C; tr = tf = 20 ns for X and I inputs; CL = 50 pF for JMP, 'X1, RR, Flag 0, Flag F;
Cl = 130 pF + 1 TTL load for Data and Write.)
Characteristic
Propagation Delay Time, Xl to RR
VOD
Vdc
Symbol
tpLH,
tpHl
Xl to Flag F, Flag 0, RTN, JMP
Xl to Write
Xl to Data
RST to RR
RST to
Xl
RST to Flag F, Flag 0, RTN, JMP
RST to Write, Data
II
All Types
Min
Typ
Max
5.0
10
15
5.0
10
15
-
250
125
100
5.0
10
15
-
500
250
200
400
200
170
450
250
200
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
-
-
-
-
-
-
5.0
10
15
-
Clock Pulse Width, Xl
tW(d)
5.0
10
15
400
200
180
Reset Pulse Width, RST
tWIRl
5.0
10
15
500
250
200
Setup Time - Instruction
tsu(1)
5.0
10
15
400
250
180
200
100
80
100
50
50
Data
Ho!d Time - In.truction
Data
5.0
10
15
5.0
10
15
5.0
10
15
tsu(D)
thO)
th(D)
NOTE 1. Maximum Reset Delay may extend to one-half clock period.
9-18
200
100
100
200
100
85
225
125
100
250
120
100
250
125
100
450
200
150
500
240
200
500
250
200
Note 1
400
200
150
450
225
175
200
100
90
250
125
100
800
400
300
900
450
350
200
125
90
100
50
40
0
0
0
100
50
50
Unit
ns
-
ns
-
ns
-
ns
-
ns
-
-
ns
-
ns
-
MC14500B
FIGURE 1 - TYPICAL CLOCK FREQUENCY
versus RESISTOR (RC)
:J:
1M
Pin No.
1
2
3
4
5
6
7
~
>z
u
Function
Chip Reset
Write Pulse
Data In{Out
MSB Instruction Word
Bit 2 Instruction Word
Bit 1 Instruction Word
LSB Instruction Word
Negative Supply (Ground)
Flag on NOP F
Flag on NOP 0
Subroutine Return Flag
Jump Instruction Flag
Oscillator Input
Oscillator Output
Result Register
Positive Supply
8
9
'"o
10
11
12
13
14
15
16
1'-..
""
~ lOa k
"
'"
~
10 k
10 kl!
lOa kll
I MS2
Symbols
RST
Write
Data
13
12
11
10
VSS
Flag F
Flag 0
RTN
JMP
X2
Xl
RR
VDD
Rc. CLOCK FREQUENCY RESISTOR
TABLE 1. MC14500B INSTRUCTION SET
Instruction Code
Mnemonic
Action
0
0000
NOPO
1
0001
LD
Load result register.
2
0010
LDC
Load complement.
3
0011
AND
Logical AND.
4
0100
ANDC
5
0101
OR
6
0110
ORC
7
0111
XNOR
8
1000
STD
9
1001
STOC
A
1010
lEN
RR~RR,FlagO~..J1..
No change in registers.
Data
Data
RR'Data~
RR + Data
~
Store.
RR -> Data Pin,
Input enable.
~
If RR
Store complement.
1011
OEN
Output enable.
1100
JMP
Jump.
D
1101
RTN
Return.
Skip next instruction if RR
1110
SKZ
1111
NOPF
Data~RR
Data, RR
~
B
E
RR
~
1
Data Pin, Write->..J1..
I EN Register
C
F
~
RR
Write~..rL
RR
~
Data
RR
RR +
Logical OR complement.
Exclusive NOR.
RR
RR
RR·Data
Logical AND complement.
LogicalOR.
~
~
Data -> OEN Register
JMP Flag
-+.J1..
RTN Flag ~ ...f1.. and skip next instruction
No change in registers.
~
0
RR ~ RR, Flag F-..fL
FIGURE 2 - OUTLINE OF A TYPICAL ORGANIZATION FOR A MC14500B·BASED SYSTEM
Additional
Output Devices
L _________
I/O Address
Memory
'o"
1)
C2
MC14599B
a-Bit Addressable Latch
with Bidirectional Data
a.
a
Outputs
'-----
MC14512
a-Channel
Data Selector
/
U
I
I
I
I
-.-l
o
o
Program
Counter
MC14500B
ICU
Clock
Data
I----
9-19
J
fL-~---,
V
1\
,----------,
.,"
00
To Peripheral
Devices
I
Additional
I
:
Input Devices
:
I
I
8
Inputs
II
MC14500B
TIMING WAVEFORMS
Instructions NOPO, NOPF
RR, lEN, OEN remain unaffected
X1
RST
lEN
Register
OEN
Register
RR
f-
tpHL (RESET TO RRJ
4 Bit
\
Instruction_ _ _ _ _ _ _ _ _ _ _ _ _--'~------NOPO
FLAG 0
tPLH
(DATA TO FLAG)
FLAG F
-=1 /l
tPHL
r--\
r--\
NOPF
NOPO
Jk!
"'---\
Instructions SKZ, JMP, RTN
RR, lEN, OEN remain unaffected
X1
---l
f---
tW(cl)
4 Bit
Instruction
SKZ
RST
RTN
JMP
JMP
,-
------------------~1
RR~L_________________________________________~+----
II
--i!
fL
\
JMP Flag _ _ _ _ _ _ _ _ _ _ _ _ _
tpHL
RTN Flag __________________________________- ' /
SKP F/F
Internal _ _ _ _...J
*
-.-J!
L - - -_ _ _ _
Instructions Ignored.
9-20
\
(R ESET TO Jump)
~
MC14500B
TIMING WAVEFORMS
Instructions STO, STOC, OEN
X1
4-Bit
Instruction
STO
STOC
STO
STOC
NOP
OEN
STO
STOC
Data
RR
tpLH, tpHL (Xl to Data)
OEN Register
(internal)
Write
Valid when RST = L
NOTE 1. Valid output data.
Instructions
LD, LOC, AND, ANDC
OR, ORC, XNOR, lEN
LD, etc.
4 Bit
Instruction
Data
RR
lEN Register
(internal)
Valid when RST = L
9-21
II
II
9-22
Reliability
10-1
®
MOTOROLA
Introduction
This chapter is intended to demonstrate the quality and
reliability aspects of the semiconductor products supplied by
Motorola.
Quality in Manufacturing
QUALITY IN DESIGN
Motorola's quality activity starts at the product design
stage. It is its philosophy to "design in" reliability. At all
development points of any new design reliability orientated
guidelines are continuously used to ensure that a thoroughly
reliable part is ultimately produced. This is demonstrated by
the excellent in-house reliability testing results obtained for
all Motorola's semiconductor products and, more importantly, by our numerous customers.
NEW PRODUCT TYPICAL DESIGN FLOW
MATERIAL INCOMING CONTROLS
Each vendor is supplied with a copy of the Motorola Procurement Specification which must be agreed in detail between both parties before any purchasing agreement is made.
This is followed by a vendor appraisal report whereby each
vendor's manufacturing facility is visited by Motorola Quality
Engineers responsible for ensuring that the vendor has a well
organized and adequately controlled manufacturing process
capable of supplying the high quality material required to
meet the Motorola Incoming Inspection Specification. Large
investments have and are continuously being made and
Quality Improvement programs developed with our main
suppliers concerning:
Masks - Silicon - Piece-parts - Chemical products Industrial gas, etc.
Each batch of material delivered to Motorola is quarantined at Goods-in until the Incoming Quality Organization
has subjected adequate samples to the incoming detailed inspection specification. In the case of masks, this will include
mask inspection for:
1. Defect Density
2. Intermask Alignment
3. Mask Revision
4. Device to Device Alignment
5. Mask Type
Silicon will undergo the following inspections:
1. Type "N" or "P"
Engineering Sample
Commercial Sample
2. Resistivity
3. Resistivity Gradient
4. Defects
5. Physical Dimensions
6. Dislocation Density
Incoming chemicals are also controlled to very rigorous
standards. Many are submitted to in-house chemical analysis
where the supplier's conformance to specification is
This basic design flow-chart omits
some feedback loops for simplicity
meticulously checked. In many cases, line tests are performed before final acceptance. A major issue and responsibility
for the Incoming Quality Department is to ensure that the
most disciplined safety factors have been employed with
regard to chemicals. Chemicals can and are often rejected
because safety standards have not been deemed acceptable.
10-2
BIPOLAR WAFER FABRICATION
WAFER FABRICATION
All processing stages of Motorola products are subjected
to demanding manufacturing and quality control standards
A philosophy of "Do it Right the First Time" is instrumental
in assuring that Motorola has a reliability record second to
none.
The Bipolar and MOS Wafer Fabrication flow charts are
examples which highlight the various in process control
points audited by both Manufacturing and Quality people
The majority of these inspections are control audit points
with inspection gates at critical points of the process; this is
in line with Motorola policy of all personnel being responsible
for quality at each manufacturing stage.
Diffusion and ion implantation processing is subject to
oxide thickness controls penetration evaluations. Controls
are also performed on resistivity and defect density. Diffusion furnaces, metallization, and passivation equipment are
subjected to daily qualification requirements by using C-V
plotting techniques. C-V techniques are also used to ensure
ongOing stability as they do provide a very sensitive measurement of ionic species concentration.
In addition many other specific controls are used as a
means to ensure built-in reliability and provide statistical
trend data, which include:
•
Environmental monitoring for humidity, temperature
and particles
•
Deionized water resistivity,
checks in water
•
Epitaxial material: resistivity defects
thickness -
•
Oxide: thickness - charges -
pinhole density
•
Metallization: thickness - adherence - metal composition - ohmic contacts
•
•
•
Doping profiles
Pre and post etch inspections
In process S EM analysis for step coverage: metallization - grain size - phosphorous concentration
•
Passivation integrity checks
particles and
bacteria
crystal
• Calibration
• Final visual inspection gate.
After all processing stages are completed, every wafer lot
is subject to a detailed electrical parameter check.
Parameters such as threshold voltage, junction breakdown
voltages, resistivity, field inversion voltages, etc., are
measured and each batch is sentenced accordingly. The data
generated at this point is treated statistically as a control on
the distribution of each key electrical parameter thus allowing corrective action adjustments to be implemented in a
timely manner.
Every wafer lot is submitted to an electrical probe test during which every individual die is tested to its electrical
specification. Chips which fail are individually inked.
o
10-3
In Process
or Control Process
or Q.A. Inspection
MOS WAFER FABRICATION
In-Process
0
Inspection
II
ASSEMBLY
The assembly operation is of equal importance to the
wafer fabrication process as a manufacturing activity which
will effect the reliability of the finished product. Motorola
continuousiy make~ majol investroents in specialized
assembly areas located in Malaysia, the Philippines and
Korea. These assembly plants employ the latest technologies
10-4
available to ensure that all Motorola semiconductors are produced to the highest standards of Quality and Reliability. In
addition, each wafer fabrication facility has in-house
assembly capability which allows some production, specific
engineering activity and qualification of piece-parts suppliers. The major production volumes of Motorola's Integrated Circuits are assembled offshore in the Far East.
identical Quality and Reliability philosophies are practiced
in the assembly areas as within the wafer fabrication
facilities. Quality Assurance Audits for immediate corrective
actions are performed after major process steps as demonstrated in the flow-chart. In addition, screening options are
available. The statistical data obtained from quality audits are
reported to the appropriate business centers either daily,
weekly or monthly for review.
Motorola is particularly aware of the major impact
moisture can have on the reliability performance of either
plastic or ceramic parts. With this in mind several major new
innovations have been introduced to safeguard Motorola
products and thus enhance their overall reliability performance, these include:
•
•
Faraday shield vacuum packed wafer shipping system
Temperature and humidity controlled wafer inventory
stores
Inert atmosphere for metal can packages encapsulation
New design lead frames (plastic assembly)
•
•
New molding compounds
Low moisture content glass
•
•
•
•
Moisture content audit procedures
Super dry piece-part controls
FINAL TESTING
Each of Motorola'S facilties has a complete Final Test
capability for all of the products fabricated and assembled.
The majority of products, after assembly, are tested and
Q.A. released at the facility responsible for that product.
Some product is tested in the offshore assembly site;
however, this is always returned to the facility for Q.A.
release prior to final shipment to customer.
Final Test is a comprehensive series of dc, functional
and speed orientated electrical tests as well as adapted
forced tests. These tests are normally more stringent than
data sheet requirements and are finally sampled by Outgoing
Quality Assurance.
In practice, the test flow philosophies vary according to
product. For instance, most of the Discrete devices are double tested as part of a zero defect quality improvement program. As well, many Integrated Circuits are tested at various
temperatures. There are also many burn-in options available.
TYPICAL INTEGRATED CIRCUITS ASSEMBLY AND FINAL TEST FLOW CHART
10-5
OUTGOING QUALITY SAMPLING PLAN
A.Q.L.
Rectifiers
Linear
1979
1980
1981
1982
1983
Electrical Inoperative
0.10
0.10
0.065
0.065
0.065
Parametric
Visual! Mechanical
OAO
OAO
0.25
0.25
0.25
0.15
0.25
0.15
0.25
0.10
Electrical Inoperative
Parametric
Visual/ Mechanical
0.25
0.65
0.15
0.15
0.15
0.15
OAO
OAO
OAO
0.15
0.15
0.15
0.10
0.25
0.15
Electrical Inoperative
Parametric
Visual/ Mechanical
0.10
0.10
OAO
OAO
0.25
0.10
0.40
0.15
0.10
0.25
0.15
0.10
0.25
0.10
0.40
0.25
Electrical Inoperative
Parametric
Visual/ Mechanical
0.15
0.65
0.15
0.65
0.10
0.10
OAO
OAO
OAO
OAO
OAO
0.25
0.15
0.15
CMOS
Function/Parametric
Visual/ Mechanical
LTPD
(5.0)
LTPD
(5.0)
0.15
0.15
0.10
0.15
0.10
0.15
MOS Microprocessors
Function/ Parametric
Visual! Mechanical
LTPD
(5.0)
LTPD
(5.0)
0.15
0.15
0.10
0.15
0.10
0.15
NMOS Memories
Function! Parametric
Visual/ Mechanical
LTPD
(5.0)
LTPD
(5.0)
0.15
0.15
0.10
0.15
0.10
0.15
lS TTL ECl
Bipolar Memory/LSI
Function! Parametric
Visual/ Mechanical
0.15
0.65
0.15
0.15
0.065
0.065
0.065
0.065
0.065
0.065
AlS/FAST
Function!Parametric
Visual! Mechanical
0.065
0.065
Power Transistors
Small Signal Transistors
EVOLUTION OF AVERAGE OUTGOING QUALITY - A.O.Q.
(TOTAL A.O.Q. INCLUDING VISUAL, MECHANICAL AND ELECTRICAL)
Bipolar Linear I!C's
X - X Rectifiers
10
c
0
Transistors
Z - Z Bipolar Digital lie's
x
::2:
6
£l.
£l.
4
1976
1977
1978
1979
1980
II
10-6
1981
1982
1983
OUTGOING QUALITY
In many published cases, stated PPM values refer to Electrical Inoperative failures only.
At Motorola, the Electrical Inoperative, the Electrical
Parametric and the Visual! Mechanical failure rates are
calculated separately and then combined to reach an overall
total. In this way Motorola believes that is giving its
customers a true and accurate assessment of the quality of
the product. Unqualified PPM statements can be misleading
and cause the customer to expect quality levels which cannot be achieved. For example, Motorola MOS Logic A.O.Q.
is separated into Electrical Inoperative/ Electrical Parametric
(280 PPM) and Visual/Mechanical (486 PPM). Other product
families such as Small Signal Plastic Transistors are already
reaching 50 PPM in Electrical Inoperative failure rate.
The Motorola PPM graphs are excellent examples of what
has been achieved over the last years with regard to quality
improvements.
Reductions between 50% and 300% in average outgoing
quality are typical across the broad range of Motorola products.
Throughout the semiconductor industry there have been,
and there still are, examples of manufacturers offering higher
quality standards at a premium. This is not a Motorola
strategy, we believe that our customers should expect high
quality products at no extra cost. This is Motorola's aim and
we will continue to aggressively pursue Quality and Reliability· improvements which will be passed on to our customers
as an obligation on our part.
Also, we actively encourage our customers to provide
their quality results at their Incoming Inspection, during their
manufacturing process and from the field in order to better
correlate and further improve our quality performance.
Although test procedures may vary from product to product within Motorola, the same philosophy applies when
considering quality objectives. Motorola's mission is to be a
Quality and Reliability leader worldwide.
HIGHLIGHTS:
Motorola recognizes that you, our customers, are truly
concerned about improving your own quality image. You
are, therefore, concerned about the quality of the product
Motorola supplies you.
Our customers measure us by the level of defects in the
products we supply at incoming inspection, during assembly
and, most important, field reliability.
During the past years, Motorola has achieved impressive
reductions in defect rates known as A.O.Q. or Average
Outgoing Quality. Instrumental in this success has been the
planned continuous reduction in outgoing A. Q. L. to a point
where Motorola believes that over all products it can
demonstrate the most aggressive A.Q. L.'s in the industry.
This aggressive program has been designed to help eliminate expensive incoming inspection at our customers.
All of the facilities also practice an extremely demanding
parts per million program program (PPM).
The PPM performance of all Motorola products is
calculated in each location using the same method; they are,
therefore, directly comparable. Motorola is well aware that
when discussing PPM with existing or potential customers, it
is of paramount importance to explain exactly which failure
categories are included in the stated PPM figures.
Motorola's PPM figures will include:
• Electrical Inoperative Failure
• Electrical Parametric Failures (de and ae)
• Visual and Mechanical criteria.
MOTOROLA A.O.Q. PLAN
Power Transistors
Rectifiers
Small Signal Metal
Small Signal Plastic
Linear I/C's
L. and S.F.
Memory
Microprocessor
Bipolar Digital Logic
Bipolar Memory/LSI
1980
History
Average
1981
3400
1750
Goal
Dec
1982
1982
1400
1100
950
1100
1000
950
1983
700
700
4100
2200
1400
1100
800
1500
1200
1030
800
600
4300
1900
1380
2000
1150
1000
5000
2800
2370
7000
4360
2400
2900
1300
7000
3860
2450
2900
1300
1260
802
975
800
500
1620
1200
1000
151
700
A.O.Q. Includes all Defects: Visual, Mechanical,
Electrical Inoperative and Parametric.
10-7
500
AVERAGE A.O.a. IN P.P.M. FOR MOS PRODUCTS FIGURES
INCLUDE FUNCTIONAL/PARAMETRICIVISUALIMECHANICAL
9000
_ _ _ _ Micro
8000
x-x
Memory
7000
6000
5000
4000
3000
2000
1000
500
250
1979
1981
1980
mortality, useful life and wearout. When a device is produced, there is often a small distribution of failure
mechanisms which will exhibit themselves under relatively
moderate stress levels and therefore appear early. This
period of early failures, termed infant mortality, are reduced
significantly through proper manufacturing controls and
screening techniques. The most effective period is that in
which only occassional random failure mechanisms appear;
the useful life typically spans a long period of time with a
very low failure rate. The final period is that in which the
devices literally wear out due to continuous phenomena
which existed at the time of manufacture. Using strictly controlled design techniques and selectivity in applications, this
period is shifted well beyond the lifetime required by the
user.
RELIABILITY
Paramount in the mind of every semiconductor user is the
question of device performance versus time. After the applicability of a particular device has been established, its effectiveness depends on the length of troublefree service it
can offer. The reliability of a device is exactly that - an expression of how well it will serve the customer. The following
discussion will attempt to present an overview of Motorola's
reliability efforts.
BASIC CONCEPTS
It is essential to begin with an explanation of the various
parameters of Reliability. These are probably summarized
best in the Bathtub Curve (Figure 1). The reliability performance of a device is characterized by three phases: infant
FIGURE 1
FIGURE2
j j
~~
50% CL
T T l 1.-'
Infant Mortality
(Such as Early
Burn-In Failures)
I
\
;"Iii,;
17
I
II
1 I
Useful Life
1983
1982
II"
~
1/
I"---'Wearout
Failures
>-
u
c
~
1
11
10
100
1000 10,000 100,000
Time (Hours)
1,000,000
A, Failure Rate
10-8
Both the infant mortality and randum failure rate regions
Cdn be described through the same types of calculations.
During this· time the probability of having no failures to a
specific point in time can be expressed by the equation:
where A is the failure rate and t is time. Since A is changing
rapidly during infant mortality, the expression does not
become useful until the random period, where A is relatively
constant. In this equation A is failures per unit of time. It is
usually expressed in percent failures per thousand hours.
Other forms include FIT (Failures In Time= (%/10 3 hrs)
x 10- 4= 10- 9 failures per hour) and MTTF (Mean Time To
Failure) or MTBF (Mean Time Between Failures), both being
equal to l/A and having units of hours.
Since reliability evaluations usually involve only samples of
an entire population of devices, the concepts of the Central
Limit Theorem apply and A is calculated using x2 distribution
through the equation:
A :5 x2 (x, 2r+ 2)
2nt
where x = 100- CL
100
CL = Confidence Limit in percent
Number of rejects
Number of devices
Duration of test
The confidence limit is the degree of conservatism desired
in the calculation. The Central Limit Theorem states that the
values of any sample of units out of a large population will
produce a normal distribution. A 50% confidence limit is
termed the best estimate and is the mean of this distribution.
A 90% confidence limit is a very conservative value and
results in a higher A which represents the point at which 90%
of the area of the distribution is to the left of that value
(Figure 2). The term (2r+ 2) is called the degrees of freedom
and is an expression of the number of rejects in a form
suitable to x2 tables.
The number of rejects is a critical factor since the definition of rejects often differs between manufacturers. While
Motorola uses data sheet limits to determine failures
sometimes rejects are counted only if they are catastrophic:
Due to the increasing chance of a test not being representative of the entire population as sample size and test time
are decreased, the x2 calculation produces surprisingly high
values of A for short test durations even though the true long
term failure rate may be quite low. For this reason relatively
large amounts of data must be gathered to demonstrate the
real long term failure rate.
Since this would require years of testing on thousands of
devices, methods of accelerated testing have been
developed.
Years of semiconductor device testing has shown that
temperature will accelerate failures and that this behaviour
fits the form of the Arrhenius equation:
R (t) = Ro(t)e- 8/kT
where R(t) = Reaction rate as a function of time and
temperature
RO = A constant
t
Time
8
Activation energy in electron volts
k
Boltzman's constant
T
Temperature in degrees Kelvin
To provide time-temperature equivalents this equation is
applied to failure rate calculations in the form:
t = toe 8/kT
where t = time
to = A constant
The Arrhenius equation essentially states that reaction rate
increases exponentially with temperature. This produces a
straight line when plotted on log-linear paper with a slope expressed by 8. 8 may be physically interpreted as the energy
threshold of a particular reaction or failure mechanism. The
activation energy exhibited by semiconductors varies from
about 0.3 eV. Although the relationships do not prohibit
devices from having poor failure rates and high activation
energies, good performance usually does imply a high 8.
Studies by Bell Telephone Laboratories have indicated that
an overall 8 for semiconductors is 1.0 eV. This value has
been accepted by the Rome Air Development Command for
time-temperature acceleration in powered burn-in as
specified in Method 1015 of MIL-STD-883. Data taken by
Motorola on Integrated Circuits have verified this number
and it is therefore applied as our standard time-temperature
regression for extrapolation of high temperature failure rates
to temperatures at which the devices will be used (Figure 3).
For Discrete products, 0.7 eV is generally applied.
To accomplish this, the time in device hours (tl) and
temperature (Tl) of the test are plotted as point Pl. A vertical line is drawn at the temperature of interest (T2) and a
line with a 1.0 eV slope is drawn through point Pl.
Its intersection with the vertical line defines point P2, and
determines the number of equivalent device hours (t2). This
number may then be used with the x2 formula to determine
the failure rate at the temperature of interest. Assuming Tl
of 125°C at tl of 10,000 hours, a t2 of 7.8 million hours
results at a T2 of 50° C. If one reject results in the 10,000
device hours of testing at 125°C, the failure rate at that
temperature will be 20% 11,000 hours using a 60% confidence level. One reject at the equivalent 7.8 million device
hours at 50°C will result in a 0.026%/1,000 hour failure rate,
as illustrated in Figure 4.
Three parameters determine the failure rate quoted by the
manufacturer: the failure rate at the test temperature, the activation energy employed, and the difference between the
test temperature and the temperature of the quoted A. A
term often used in this manipulation is the "acceleration factor" which is simply the equivalent device hours at the lower
temperature divided by the actual test device hours.
Every device will eventually fail, but with the present
techniques in Semiconductor design and applications, the
wearout phase is extended far beyond the lifetime required.
During wearout, as in infant mortality, the failure rate is
changing rapidly and therefore loses its value. The parameter
10-9
mechanisms: electromigration of circuit metallization, electrolytic corrosion in plastic devices al')d metal fatigue for
Power devices.
used to describe performance in this area is "Median Life"
and is the point at which 50% of the devices have failed.
There are currently only few significant wearout
FIGURE 4
FAILURE RATE
FIGURE 3
NORMALIZED TIME-TEMPERATURE
REGRESSIONS FOR VARIOUS ACTIVATION
ENERGY VALUES
l000k
1.2
lOOk
1.6
2.0
2.4
3.2
2.8
1.2
100
3.6
1.6
2.0
~0
I
~
'#.
Ql
Ql
S
co
a:
f-
(J)
:::J
i\
i ,
I
1.0
1\
I
I
0.1
\
f
}"1 L...
~_L..
0.01
1\
I
I
11\
I
0.001
\
_\
.L
~
-<
3.6
i\
8
S
~0
3.2
,
10
}"2
2.8
1\
}"2
}"1
2.4
I
I
I
I
I
0.0001
~
0.00001
I
\
\
\
i
\
I
500
200
100
50
500
Temperature (OC)
200
100
50
Temperature (OC)
For increased flexibility in working with a broad range
of device hours, the time-temperature regression lines
have been normalized to 500°C and the time scale
omitted, permitting the user to define the scale based
on his own requirements.
Reliability
RELIABILITY TESTS:
DEFINITION, PURPOSE AND PROCEDURES
These definitions are intended to give the reader a brief
understanding of the test currently used at Motorola for
reliability checking. They also state which main failure
mechanisms are accelerated by the test.
HIGH TEMPERATURE STORAGE LIFE
An environmental test where only temperature is the
stress. Temperature and test duration must be specified.
Usually temperature is the maximum storage temperature of
the devices under test. Main failure mechanisms are
metallization, bulk silicon, corrosion.
II
HIGH TEMPERATURE REVERSE BIAS (HTRB)
An environmental stress combined with an electrical stress
whereby devices are subjected to an elevated temperature
and simultaneously reverse biased. To be effective, voltaqe
must be applied to the devices until they reach room
temperature at the completion of the test. Temperature, time
and voltage levels must be specified. Accelerated failure
mechanisms are inversion, channeling, surface contamination, design.
HIGH HUMIDITY, HIGH TEMPERATURE REVERSE
BIAS (H3TRB)
A combined environmental/electrical stress whereby
devices are subjected to an elevated ambient temperature
and high humidity, simultaneously reverse biased for a
period of time. Normally performed on a sample basis
(qualification) on non-hermetic devices. The most common
conditions is 85°C and 85%. relative humidity. More extreme
conditions generally are very destructive to the chambers
used. Time, temperature, humidity and voltage must be
specified. This accelerated test mainly detects corrosion
risks.
10-10
STEADY STATE OPERATING LIFE
An electrical stress whereby devices are forward (reverse
for zeners) biased at full rated power for prolonged duration.
Test is normally 25°C ambient and power is 100% of full
rated. (For power devices the lie's maximum operating Ti is
used.) Duration, power and ambient, if other than 25°C,
must be specified. Accelerated failure mechanisms mainly
are metallization, bulk silicon, oxide, inversion and channeling.
DYNAMIC OPERATING LIFE
An electrical stress whereby devices are alternately subjected to forward bias at full rated power or current and
reverse bias.
Duration, power, duty cycle, reverse voltage ambient and
frequency must be specified. Used normally for rectifiers and
silicon controlled rectifiers. Failure mechanisms are essentially the same as steady state operating life.
INTERMITTENT OPERATING LIFE
(POWER CYCLING)
An electrical stress whereby devices are turned on and off
for a period of time. During the "on" time the devices are
turned on at a power such that the junction temperature
reaches its maximum rating. During "off" cycle the devices
return to 25°C ambient. Duration, power, pr duty cycle must
be individually specified. Accelerated failures mechanisms
are mainly die bonds, wire bond, metallization, bulk silicon,
and oxide.
THERMAL SHOCK (TEMPERATURE CYCLING)
An environmental stress whereby devices are alternately
subjected to a low and high temperature with or without a
dwell time in between to stabilize the devices to 25°C ambient - the medium is usually air. Temperatures, dwell times
and cycles must be specified. Failure mechanisms are essentially die bonds, wire bonds, and package.
THERMAL SHOCK (GLASS STRAIN)
An environmental stress whereby the devices are subjected to a low temperature, stabilized and immediately
transferred to a high temperature. The medium is usually liquid. Failures mechanisms essentially are the same as
temperature cycling.
EXAMPLE OF NEW PROCESS QUALIFICATION TESTS
Condition
Duration
MIL-STD-883
Reference
Test Method
125°C, 5 V or 15 V
1,000 Hours
1005
85°C, 85% R.H.
5 V or 15 V
1,000 Hours
121°C, 100% R.H.
15P.S.I.G.
144 Hours
150°C
1,000 Hours
Thermal Cycle
(Air to Air)
- 65°C to 150°C
5 Min Dwell
1,000 Cycles
1010
Thermal Shock
(Liquid to Liquid)
- 65°C to 150°C
5 Min Dwell
1,000 Cycles
1011
1,500G, 3 per Axis
150- 2,000 Hz, 20 g
30 kg
0.5 MS
2 Hours
2002
2007
2001
200/250°C
1,000 Hours
Test
Operating Life
Temperature Humidity
Bias
Autoclave
High Temperature
Storage
Shock, Vibration, and
Constant Acceleration
Data Retention Bake
(Non Volation Memories)
II
10-11
MECHANICAL SHOCK
VIBRATION VARIABLE FREQUENCY
A mechanical stress whereby the devices are subjected to
high impact forces normally in two or more of the six orientations Xl, Yl, Zl, X2, Y2, Z2. Tests are to verify the physical
integrity of the devices. G forces, pulse duration, and number of shocks and axes must be specified.
Same as Vibration Fatigue except that frequency is logarithmically varied from 100 Hz to 1 kHz and back. Number
of cycles is normally four. Cycle time, amplitude and total
duration must be specified. Failure mechanisms are mainly
package, wire bond - this test is not applicable to molded
devices.
EXAMPLE OF NEW PACKAGE QUALIFICATION TESTS
Test
Operating Life
Temperature Humidity Bias
Autoclave
High Temperature Storage
Condition
Duration
MIL-STD-883
Reference
Test Method
125°C, 5 V or 15 V
1,000 Hours
1005
85°C, 85% R.H.
5 V or 15 V
1,000 Hours
121°C, 100% R.H.
15 P.S.I.G.
144 Hours
150°C
1,000 Hours
Thermal Cycle
(Air to Air)
-65°C to 150°C
5 Min Dwell
1,000 Cycles
1010
Thermal Shock
(Liquid to Liquid)
- 65°C to 150°C
5 Min Dwell
1,000 Cycles
1011
1,500 G, 3 per Axis
150-2,000 Hz, 20 g
30 kg
0.5ms
2 Hours
2002
2007
2001
Shock, Vibration, and
Constant Acceleration
Hermeticity
1.85,10- 8
atm cc/sec
1014
Visual Inspection
Dimensions
2008
Outline Dwg.
2016
Marking Permanency
Solderability
Wire Bond Strength
(Post Seal)
2015
230°C
1.5 Gram
Die Shear
3 Seconds
2003
2011
2027
10-12
EXAMPLE OF STANDARD RELIABILITY PROGRAM
Reliability
Engineering
Department
Motorola Reliability Program For:
Test Group
Reliability Audit
Life Tests
Test
SS
Frequency
Thermal Shock
25
1 Product Line
Per Week
High Temperature
Reverse Bias
40
High Temperature
Reverse Bias
25
(+2)
High Temperature
Storage
25
(+2)
TA= 150°C, 1,000 hours
Steady State
Life
25
(+2)
MIL-STD-883, Method 1005
TA=125°C, 1,000 hours
High Humidity
Test Methods/Conditions
MIL-STD-883, Method 1011
- 25°C, + 125°C.
Dwell Time 5 mn, 100 Cycles
T A = 150°C, VCB = .8 VCB max. 168 hours
3 Product Lines
Per Month
25
High Temperature
Reverse Bias
( + 2) devices for correlation purpose
T A = 150°C, VCB = .8 VCB max. 1,000 hours
TA=85°C, 85% Humidity
VCB = .8 VCB max. 1,000 hours
(+2)
Product Family
Test Conditions
Device Hours
No. Of
Failures
Activation
Energy
Derated
Temperature
% Per 1,000 Hours
At 60% Confidence
Non Hermetic
Interface lie's
Operating
Tj=155°C
591,552
64
1 eV
70°C
0.014
Consumer II C's
Operating
Tj= 125°C
13,082,000
39
1 eV
70°C
0.0029
D04/D05
Rectifier
Tj-150°C
VR=.8 BVR
798,000
5
.7 eV
70°C
0.009
Plastic
Axial Diodes
Tj-l00°C
VR=.8 BVR
295,000
3
.7 eV
70°C
0.21
Button Diodes
Tj= 150°C
VR=.8 BVR
520,000
5
.7 eV
70°C
0.014
Small Signal
Plastic
Transistor
Tj = 150°C
VCB=.8 BVCO
579,000
6
.7 eV
70°C
0.014
Small Signal
Metal
Transistor
Tj= 150°C
VCB=.8 BVCBO
3,944,000
12
.7 eV
70°C
0.0039
Tj= 150°C
364,416
2
.7 eV
70°C
0.0097
366,080
0
.7 eV
70 0 e
0.0028
297,024
3
.7 eV
70°C
0.016
247,104
3
.7 eV
70°C
0.019
Case 77
Power Plastic
Transistor
T0220
Power Plastic
Transistor
T03P
Power Plastic
Transistor
T03
Power Metal
Transistor
VBC=.8 BVCBO
Tj= 150°C
VCB=.8 BVCBO
Tj-150°C
VCB = .8 BVCBO
Tj-l50°C
VCB = .8 BVCBO
10-13
No. of
Failures
11
Activation
Energy
1 EV
Derated
Temperature
50 0 e
85°e
% Per 1,000 Hours
At 60% Confidence
0.00074
0.025
loB
17
1 EV
85°e
0.0088
125°e
Dynamic Bias
5V
2.88x 106
47
1 EV
70 0 e
0.039
125°e
Dynamic Bias
5V
250°C Bake
434,456
3
1 EV
70°C
0.009
519,120
3
0.7 EV
70°C.
0.0075
125°e
Dynamic Bias
5V
250 0 e
917,280
25
1 EV
70°C
0.027
966,672
1.05x lOti
19
6
0.7 EV
0.7 EV
70°C
70 0 e
0.020
0.028
Test Conditions
125°e
Static Basis
-5.2 V
125°e
Static Bias
5V
Device Hours
No. of
Failures
Activation
Energy
1.0 eV
Derated
Temperature
70 0 e
% Per 1,000 Hours
At 90% Confidence
0.0029
61.74x 106
7
1.0 eV
85°e
0.0189
Test Conditions
Operating
Tj=135°C
Operating
Tj= 135°C
Device Hours
437,472
No. of
Failures
2
Activation
Energy
1 eV
Derated
Temperature
70°C
% Per 1,000 Hours
At 60% Confidence
0.0026
718,848
4
1 eV
70 0 e
0.0033
Product Family
eMOS Ceramic
Test Conditions
125°e
Static Bias
CMOS Plastic
125°e
Static Bias
6800 Series
Plastic
U.V. EPROM
Life Test
Data Retention
EEPROM
Life Test
Data Retention
64K DRAM
Product Family
lS-TTl
ECl
Product Family
Operational
Amplifier
Hermetic
Interface I/C's
--
125°e
Dynamic Bias
5.5 V
Device Hours
6.5x 10'
2.1 x
The reliability approach at Motorola Semiconductors is
based on designing in reliability rather than testing for reliability only. This concept is reflected by Motorola's mandatory procedures which require product, process and
packaging qualification on three independently produced
lots before any product is released to volume production.
Reliability engineering approval supported by an officially
documented report is required before any product is released
to manufacturing. Tests at both maximum rated and accelerated stress levels are performed. Acceleration is important to determine how and at what stress level a new design,
product process or package would fail. This information proyides an indication of what design changes can be implemented to ensure a wider and safer margin between the
maximum rated stress condition and the devices stress
limitation .
an ongoing reliability monitor which covers all process and
packaging options. This program provides a continuous upto-date data base which is summarized in periodical reports.
Reliability statistics supporting all Motorola Semiconductor devices Can be obtained from any of the Motorola Sales
Offices upon request. The present operating life test results
demonstrates Motorola's reputation for producing semiconductors with reliability second to none.
The Quality organization in each facility is responsible for
preparing and maintaining a Quality Manual which describes
in detail the quality systems and associated Reliability and
Quality Assurance organization, policies, and procedures.
This manual must be appraised and ultimately approved by
the appropriate approval authority.
.A.S we!! as qualifying all new products. processes and
piece-parts, each Motorola manufacturing facility operates
10-14
Package Dimensions
PACKAGE DIMENSIONS
The package availability for each device is indicated on the front page of
the individual data sheets. Dimensions for the packages are given in this
chapter.
- - - - - - - - 1 4 · P I N PACKAGE - - - - - - - PLASTIC PACKAGE
CASE 646-05
NOTES:
1. LEADSWITHINO.13mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.
3. DIMENSION "B" DOES NOT
INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
II
11·2
MILLIMETERS
MIN
MAX
18.16 19.56
6.10
6.60
5.08
4.06
0.38
0.53
1.78
1.02
2.54 BSC
2.41
1.32
0.38
0.20
2.92
3.43
7.62 BSC
10 0
00
0.51
1.02
INCHES
MIN
MAX
0.715 0.770
0.240 0.260
0.160 0.200
0.015 0.021
0.040 0.070
0.100 BSC
0.052 0.095
0.008 0.015
0.115 0.135
0.300 BSC
100
00
0.020 0.040
PACKAGE DIMENSIONS (Continued)
- - - - - - - - 1 6 · P I N PACKAGE - - - - - - - PLASTIC PACKAGE
CASE 648-05
NOTES:
1. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.
3. DIMENSION "8" DOES NOT
INCLUDE MOLD FLASH.
4. "F" DIMENSION IS FOR FULL
LEADS. "HALF" LEADS ARE
OPTIONAL AT LEAD POSITIONS
1,8,9, and 16).
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
e
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
18.80 21.34
6.10
6.60
5.08
4.06
0.38
0.53
1.02
1.18
2.54 Bse
2.41
0.38
0.38
0.20
2.92
3.43
7.62 BSC
00
10 0
0.51
1.02
INCHES
MIN
MAX
0.740 0.840
0.240 0.260
0.160 0.200
0.015 0.021
0.040 0.070
0.100 Bse
0.015 0.095
0.008 0.015
0.115 0.135
0.300 BSC
00
10 0
0.020 0.040
MI LLIMETERS
MIN
MAX
19.05 19.94
7.49
6.10
5.08
0.38
0.53
1.18
1.40
2.54 Bse
1.14
0.51
0.30
0.20
4.32
3.18
7.62 BSC
150
0.51
1.02
INCHES
MAX
MIN
0.750 0.785
0.240 0.295
0.200
0.015 0.021
0.055 0.070
0.100 BSC
0.020 0.045
0.008 0.012
0.125 0.170
0.300 BSC
15 0
0.020 0.040
CERAMIC PACKAGE
CASE 620-08
t
B
~""T-rr-r-T-'--'-""'--T""T"""""I+8,...J ~
1. LEADS WITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITIDN AT SEATING PLANE
AT MAXIMUM MATERIAL CDNDITION.
2. PACKAGE INDEX: NDTCH IN LEAD
NOTCH IN CERAMIC OR INK DOT.
3. DIM "L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIM "A" AND "B" 00 NOT INCLUDE
GLASS RUN·O UT.
5. DIM "F" MAY NARROWTO 0.76 mm
(0.030) WHERE THE LEAD ENTERS
THE CERAMIC BODY.
11-3
DIM
A
B
e
D
F
G
H
J
K
L
M
N
PACKAGE DIMENSIONS (Continued)
- - - - - - - - 1 8 · P I N PACKAGE - - - - - - - - PLASTIC PACKAGE
CASE 707-02
MILLIMETERS
MAX
DIM MIN
A 22.22 23.24
6.60
6.10
B
3.56
4.57
C
0.56
0.36
0
1.27
1.7B
F
2.54 SSC
G
1.52
1.02
H
0.20
0.30
J
3.43
K
2.92
7.62 SSC
L
15°
M
0°
1.02
0.51
N
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm(O.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
r
0.240
0.140
0.014
0.050
0.100
0.040
O.OOB
0.115
0.260
O.IBO
0.022
0.070
BSC
0.060
0.012
0.135
0.300 BSC
0°
0.020
15°
0.040
CERAMIC PACKAGE
CASE 726-04
8 8 6 8 'LJ~ ,-~
I
,
I
I
I
--I G r--
I
L------
A ---t
'-- L ---.!
_-
; ~ I~I ~
I
I
~~NP' IJ91\
'l
.J
~ ~ ~ \~
llfJOOOOOO,
!
1
I
H ., ,'....
_I
fl...
'I
i
I
SEATING PLANE-
~
J
--if-- D
II
INCHES
MIN
MAX
0.B75 0.915
~,
J
\
M \--
DIM
A
B
C
0
F
G
H
NOTES:
2. DIM "L"TO CENTER OF
1. LEADS, TRUE POSITIONED
WITHIN 0.25 mm (0.010) DIA.
LEADSWHEN FORMED
AT SEATING PLANE, AT
PARALLEL.
MAXIMUM MATERIAL
3. DIM "A" & "B" INCLUDES
CONDITION.
MENISCUS.
11-4
J
K
L
M
N
MILLIMETERS
MIN
MAX
22.35 23.11
7.49
6.10
5.08
0.53
0.38
1.40
1.78
2.54
sse
1.14
0.51
0.30
0.20
4.32
3.18
7.62 BSC
00
15 0
1.02
0.51
INCHES
MIN
MAX
0.880 0.910
0.240 0.295
0.200
0.015 0.021
0.055 0.070
O.100BSC
0.020 0.045
0.008 0.012
0.125 0.170
0.300 BSC
15 0
00
0.020
0.040
PACKAGE DIMENSIONS (Continued)
- - - - - - - - 2 0 · P I N PACKAGE-------PLASTIC PACKAGE
CASE 738-02
DIM
A
B
C
D
F
G
J
K
L
M
N
NOTES:
1. DIM
IS DATUM.
2. POSITIONAL TOL FOR LEADS;
rn
Itl~
0.25 (0.010)@IT I A@I
m
3.
IS SEATING PLANE.
4. DIM "B" DOES NOT INGLUDE MOLD FLASH.
5. DIM [IJ TO GENTER OF LEADS WHEN
FORMED PARALLEL.
6. DIMENSIONING AND TOLERANGING
PER ANSI Y14.5, 1973.
t::--
MILLIMETERS
MIN
MAX
25.65 27.18
6.10
6.60
4.57
3.94
0.56
0.38
1.27
1.78
2.54 BSG
0.38
0.20
2.79
3.56
7.62 BSG
15°
0°
0.51
1.02
INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.155 0.180
0.015 0.022
0.050 0.070
0.100 BSG
0.008 0.015
0.110 0.140
0.300 BSG
15°
0°
0.020 0.040
CERAMIC PACKAGE
---:~
~-~~=j CLJ
CASE 732-03
------g- rl'A~'
_~--".j~;LANE
-IG~
F
C
!
!
! !!
I I
I I
SEATING
I
tN
J
MY
NOTES:
1. LEADS WITHIN 0.25 mm (0.010)
DIA, TRUE POSITION AT
SEATING PLANE, AT MAXIMUM
MATERIAL GONDITION.
2. DIM L TO GENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIM A AND B INCLUDES
MENISCUS.
PLCC PACKAGE -
MILLIMETERS
MIN
MAX
23.88 25.15
7.49
6.60
3.81
5.08
0.38
0.56
1.40
1.65
F
2.54 BSG
G
1.27
0.51
H
0.30
0.20
J
4.06
3.18
K
7.62 SSG
L
00
M
15°
1.02
0.25
N
DIM
A
B
C
D
SEE PAGE 11-9
11-5
INCHES
MIN
MAX
0.940 0.990
0.260 0.295
0.150 0.200
0.015 0.022
0.055 0.065
0.100 BSG
0.020 0.050
0.008 0.012
0.125 0.160
0.300 SSG
00
15°
0.010 0.040
PACKAGE DIMENSIONS (Continued)
- - - - - - - - 2 4 · P I N PACKAGE-------PLASTIC PACKAGE
CASE 709-02
-1
NOTES:
PLANE
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
MILLIMETERS
DIM MIN
MAX
A
31.37 32.13
13.72 14.22
B
3.94
C
5.08
0.56
D
0.36
F
1.52
1.02
2.54 BSC
G
H
1.65
2.03
J
0.20
0.38
K
2.92
3.43
15.24 Bse
L
M
15°
0°
1.02
N
0.51
INCHES
MIN
MAX
1.235 1.265
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 Bse
0.065 0.080
0.008 0.015
0.115 0.135
0.600 Bse
15°
0°
0.020 0.040
CERAMIC PACKAGE
CASE 623-05
III
NOTES:
1. DIM "L" TO CENTER OF
LEADS \,VHEN FORMED
PARALLEL.
2. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL
CONDITION. (WHEN FORMED
PARALLEL).
11-6
DIM
A
B
C
0
F
G
J
K
L
M
N
MILLIMETERS
MIN
MAX
31.24 32.77
12.70 15.49
4.06
5.59
0.41
0.51
1.27
1.52
2.54 Bse
0.20
0.30
3.18
4.06
15.24 BSC
15°
0°
0.51
1.27
INCHES
MIN
MAX
1.230 1.290
0.500 0.610
0.160 0.220
0.016 0.020
0.050 0.060
0.100 BSC
0.008 0.012
0.125 0.160
0.600 BSC
0°
15°
0.020 0.050
PACKAGE DIMENSIONS (Continued)
--------28·PIN PACKAGE-------CERAMIC PACKAGE
CASE 733-03
[::::::::::]J
NOTES:
1. DIM IAJ IS DATUM.
2. POSITIONAL TOl FOR lEADS:
Itlp 0.25 (0.010) 91 T I A91
3.
IS SEATING PLANE.
4. DIM A AND B INCLUDES MENISCUS.
5. DIM ·l· TO CENTER OF lEADS WHEN FORMED
PARAllEL.
6. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5,1973.
rn
DIM
A
B
C
D
F
G
J
K
L
M
N
MILLIMETERS
MIN
MAX
36.45
37.85
12.70
15.37
5.84
4.06
0.38
0.56
1.27
1.65
2.54 BSC
0.20
0.30
3.18
4.06
15.24 BSC
15°
5°
0.51
1.27
INCHES
MAX
MIN
1.490
1.435
0.605
0.500
0.230
0.160
0.022
0.015
0.065
0.050
0.100 BSC
0.012
0.008
0.160
0.125
0.600 BSC
15°
5°
0.050
0.020
PLASTIC PACKAGE
CASE 710-02
~::::::::::::J:
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN O.25mm(O.OlO) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
11-7
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
INCHES
MIN
MAX
36.45
13.72
3.94
0.36
1.02
2.54
1.65
0.20
2.92
15.24
0°
0.51
1.435
0.540
0.155
0.014
0.040
0.100
0.065
0.008
0.115
0.600
00
0.020
37.21
14.22
5.08
0.56
1.52
Bse
2.16
0.38
3.43
Bse
15°
1.02
1.465
0.560
0.200
0.022
0.060
Bse
0.085
0.015
0.135
Bse
15 0
0.040
II
PACKAGE DIMENSIONS (Continued)
- - - - - - - - 40-PIN PACKAGE-------PLASTIC PACKAGE
CASE 711-03
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (0),
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B ODES NOT INCLUDE
MOLD FLASH.
MI LLiMETERS
MAX
DIM MIN
A
51.69 52.45
B 13.72 14.22
3.94
C
5.08
0.56
D
0.36
F
1.02
1.52
2.54 BSC
G
H
1.65
2.16
0.38
J
0.20
2.92
3.43
K
15.24 BSC
L
M
15°
0°
0.51
N
1.02
INCHES
MIN
MAX
2.035 2.065
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.015
0.115 0.135
0.600 BSC
15°
0°
0.020 0.040
CERAMIC PACKAGE
CASE 734-04
NOTES:
1. DIM A IS DATUM.
2. POSITIONAL TOLERANCE FOR LEADS:
Itl
II
@I I
I
fJ 0.25(0.010)
T AG
3. [JJ IS SEATING PLANE.
4. DIM L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
5. DIMENSIONS A AND B INCLUDE
MENISCUS.
6. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5, 1973.
11-8
DIM
A
B
C
D
F
G
J
K
L
M
N
MILLIMETERS
MIN
MAX
51.31 53.24
12.70 15.49
4.06
5.84
0.38
0.56
I.L.I
1.65
2.54 BSC
0.30
0.20
3.18
4.06
15.24 BSC
15°
5°
0.51
1.27
INCHES
MIN
MAX
2.020
0.500
0.160
0.015
0.050
0.100
0.008
0.125
0.600
5°
0.020
2.096
0.610
0.230
0.022
0.065
BSC
0.012
0.160
SSC
15°
0.050
PACKAGE DIMENSIONS (Continued)
--------40·PIN PACKAGE-------PLCC PACKAGE
CASE 777-01
o
w
~~R~~~--1
I----~-
B
~~~-1
NOTES:
1. DIMENSIONS RAND U DO NOT INCLUDE MOLD
FLASH.
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. CONTROLLING DIMENSION: INCH
DIM
A
B
C
D
E
F
G
H
J
K
R
U
V
W
X
Y
MILLIMETERS
MAX
MIN
17.40
17.65
17.65
17.40
4.19
4.57
0.64
1.01
2.16
2.79
0.33
0.53
1.27 sse
0.66
0.81
0.38
0.63
14.99
16.00
16.51
16.66
16.66
16.51
1.07
1.21
1.07
1.21
1.07
1.42
0.00
0.50
INCHES
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.040
0.025
0.085
0.110
0.013
0.021
0.050 SSC
0.032
0.026
0.Q15
0.025
0.590
0.630
0.656
0.650
0.650
0.656
0.042
0.048
0.042
0.048
0.042
0.056
0.000
0.020
- - - - - - - - 2 0 · P I N PACKAGE-------PLCC PACKAGE
CASE 775-01
DIM
A
B
C
D
E
F
G
H
J
K
NOTES:
1. DIMENSIONS RAND U DO NOT INCLUDE MOLD
FLASH.
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. CONTROLLING DIMENSION: INCH
R
U
V
W
X
Y
AA
11-9
•
MILLIMETERS
MAX
MIN
9.78
10.02
10.02
9.78
4.19
4.57
1.01
0.64
2.16
2.79
0.33
0.53
1.27 Bse
0.66
0.81
0.13
0.38
7.37
8.38
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
0.00
0.50
2.34
2.71
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.040
0.OZ5
0.085
0.110
0.013
0.021
0.050 BSC
0.032
0.026
0.005
0.015
0.290
0.330
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
0.000
0.020
0.088
0.107
II
MC145453
ELECTRICAL CHARACTERISTICS (- 40°C ~ T A -<85°C, Voltages Referenced to VSS)
Symbol
Test Condition
Parameter
V
Guaranteed
Limit
Unit
VOO
-
3.0 to 10.0
V
VIL
Maximum Low-Level Input Voltage
{Data, Clock, BP In)
3.0
4.5
10.0
0.4
0.8
0.8
V
VIH
Minimum High-Level Input Voltage
{Data, Clock, BP In)
3.0
5.5
10.0
2.0
2.0
8.0
V
IOL
Minimum Low-Level Output Current
3.0
3.0
320
20
3.0
3.0
-320
-20
VOO
Power Supply Voltage Range
V out =0.3 V
(BP Out)
(Out 1 to Out 33)
IOH
Minimum High-Level Output Current
fAA
V ou t=2.7 V
(BP Out)
(Out 1 to Out 33)
fAA
Average DC Output Offset Voltage
(BP Out Relative to Out 1 through Out 33)
BP Out: CL =8750 pF
Out 1 to 33: CL = 250 pF
3.0
10.0
±50
±50
mV
Maximum Input Leakage Current
(Data, Clock, BP In)
Vin = VDD or VSS
10.0
± 1.0
fAA
100
Maximum Quiescent Supply Current
(per Package)
Osc In: Vin = VSS
BP In, Data, Clock: Vin = VDD or VSS
10ut=0 fAA
10.0
10
fAA
Idd
Maximum RMS Operating Supply Current
(per Package)
RX = 1.0 MO, Cx = 470 pF
BP Out Tied to BP In
ClocK, Data: Vin = VDD or VSS
10ut=0 flA
10.0
40
fAA
VOO
V
Guaranteed
Limit
Unit
Maximum Clock Frequency (50% Duty Cycle)
(Figure 1)
3.0
4.5
10.0
400
850
1800
kHz
tsu
Minimum Setup Time, Data to Clock
(Figure 1)
3.0
4.5
10.0
300
180
100
ns
th
Minimum Hold Time, Clock to Data
(Figure 1)
3.0
4.5
10.0
300
130
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
3.0
4.5
10.0
1250
585
275
ns
tr,tf
Maximum Input Rise and Fall Times, Clock
(Figure 1)
3.0
4.5
10.0
300
300
300
ns
Cin
Maximum Input Capacitance
-
10
pF
VOO
lin
AC ELECTRICAL CHARACTERISTICS
(-40°C~TA~85°C, Input t r =tf=50 n5)
Symbol
f max
Parameter
CLOCK
__ t_Isu
DATA
If
~_O_% _ _ _...J
-----VL
VH = 3.0 V, VL = 0 V @ VOO = 3.0 V, 4.5 V
Vfj= 10.0 V. VL =0 V @l VOO= 10.0 V
Figure 1. Switching Waveforms
Continuation of data sheet MC145453 page 3
50
MC145453
PIN DESCRIPTIONS
INPUTS
Osc In
Data
Oscillator input. As shown in Figure 3, this pin is used in
conjunction with an external resistor and capacitor to form an
oscillator. The oscillator frequency is divided by 16 and appears
at BP Out. With a 5 V supply, nominal values of 1 MD and
470 pF produce a 60 to 150 Hz waveform at BP Out. If the
on-chip oscillator is not used, Osc In must be tied to VSS
which minimizes power consumption and insures reliable chip
operation.
Serial data input. Data on this pin is serially entered into the
on-chip shift register on the rising edge of Clock. The data
stream consists of a Start Bit (high), followed by 33 Display
Bits, plus 2 Trailing Bits (don't cares). This device does not
contain a decoder, which allows the flexibility of formatting
the segment information externally. Display Bit 1 controls the
LCD segment connected to Out 1, Bit 2 controls Out 2, etc.
If a Display Bit is high, the associated segment is activated.
The Display Bits are stored in latches which eliminates display
flicker during shifting.
OUTPUTS
Clock
BP Out
Each rising edge on Clock causes Data to be shifted into
the 36-bit shift register. The shift register is completely static,
allowing clock rates down to DC in a continuous or intermittent
mode. Clock nE;!ed not be synchronous to Osc In nor BP In.
The internal load shown in Figure 2 transfers the 33 Display
Bits to the on-chip latches. The internal reset clears the shift
register (only) to ready the device for the next set of data.
Backplane output. This pin may be used to provide a 50%
duty cycle waveform to directly drive the backplane of the
LCD and BP In. (See Figure 3.) If the on-chip oscillator is not
used, BP Out must be left unconnected. (See Figure 4.) When
paralleling devices, BP Out fans out to drive the BP In pins of
other packages. (See Figure 6.)
Out 1 through Out 33
Frontplane driver outputs which are tied directly to the LCD.
BPln
Backplane in. The signal applied to this input must also be
tied to the backplane of the LCD. BP In is the common input
to the 33 gated drivers, and may be sourced from the on-chip
oscillator output, BP Out. (See Figure 3.) To reduce interference from the display driver in analog designs, BP In may be
synchronized with a system clock. The BP In waveform must
be a 50% duty cycle to minimize offset voltage to the LCD
which impacts display lifetime. (See Figures 4 and 5.) The BP
In frequency should be 25 to 250 Hz, depending on the display.
POWER
VSS
Most negative supply potential. This pin is usually ground.
VDD
Most positive supply potential. This voltage may range from
3 to 10 volts with respect to VSS.
START
START
"OCKJ1J\~r---fVV\jtJVL
DATA
1 H H~ S~~;T
BIT 34
BIT 35
t
HIGH
fl,
LOAD
IINTERNALI________
t
DUT 1
~
DUT 2
~
H
BIT 33 e
BIT 34 e BIT 35
B~~S~~;Te
BIT 1 e
BIT 2
e
t
OUT 33
DUT 3
~t
11o..-_ _ _ _ _ _ _ _ _ _ _ _...II\,'~--------
i
~_~D_P~_~;....... n
. !
RESET _ _ _ _ _
IINTERNALI
:
",,"""
,---------1I
}i
Figure 2. Timing Diagram
Continuation of data sheet MC145453 page 4
!Mh
.. !~-----------
MC145453
APPLICATIONS INFORMATION
+V
I
I
VOO
1M
S
>
--. BP IN
BACKPLANE
BP OUT
OSC IN
470 pF--'--
LCD
T
-=
CMOS
OR
NMOS
MPU/MCU
MC145453
OUT 1 THROUGH OUT 3 ) FRONTPLANES
DATA
CLOCK
Vss
1
1-=-
Figure 3. Using On-Chip Oscillator
+V
50% DUTY CYCLE
EXTERNAL
FREQUENCY
SOURCE
2X BACKPLANE
FREQUENCY
MC14013B
Voo
+2
BP OUT
NC
BACKPLANE
OSC IN
+V
LCD
MC145453
CMOS
OR
NMOS
MPU/MCU
OUT 1 THROUGH OUT 33
I----------------~OATA
t-----------------i~
CLOCK
VSS
Figure 4. Converting External Backplane Frequency Source
to 50% Duty Cycle
Continuation of data sheet MC145453 page 5
FRONTPLANES
MC145453
APPLICATIONS INFORMATION (CONT'D)
+V
+V
50% DUTY CYCLE
VDD
22=-H:.;:z_..._-+l
013 f------'l.=c
BP OUT
MC14020B
-7- 8192
RST
VSS
CMOS
OR
NMOS
MPUIMCU
MC145453
f - - - - - - - - - - - - - - - - - . t DATA
f - - - - - - - - - - - - - - - - - . t CLOCK
VSS
Figure 5. Using Low-Cost Divider to Sync Backplane Frequency
BP IN
BP OUT
BACKPLANE
-t V
MC145453
OUT 1 THROUGH OUT 33
FRONTPLANES
OSC IN
I
BP IN
BP OUT
NC
LCD
MC145453
OUT 1 THROUGH OUT 33
OSC IN
...-----.t BP IN
BP OUT
FRONTPLANES
NC
MC145453
OUT 1 THROUGH OUT 33
FRONTPLANES
OSC IN
Figure 6. Paralleling Devices to Increase Number of Driven Segments
Continuation of data sheet MC145453 page 6
I
Master Index
I
Handling and Design Guidelines
I
I
I
CMOS ADCs/DACs
CMOS Decoders/Display Drivers
I
CMOS/NMOS PLLs/Frequency Synthesizers
I
I
I
CMOS Remote Control Functions
I
Reliability
I
Package Dimensions
CMOS Operational Amplifiers/Comparators
CMOS Smoke Detectors
Miscellaneous Functions
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