1986_Fujitsu_Memories_Databook 1986 Fujitsu Memories Databook

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DATA BOOK

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Memories
Data Book
1986-87 Edition

Fujitsu Limited
Fujitsu Microelectronics, Inc.
Fujitsu Mikroelektronik GmbH
Worldwide Suppliers of Communications and Electronics Equipment

Copyright@) 1986 by Fujitsu Limited and Fujitsu Microelectronics, Inc.
All Rights Reserved.
No part of this publications may be copied or reproduced In any form or by any means, or transferred
to any third party without the prior written consent of Fujitsu limited ~
Printed In the U.S.A.

DEAPTM and QUICK PRO™ ,are trademarks of Fujitsu Limited, Tokyo, Japan.
Copyright" 1986 Fujitsu Limited, Tokyo, Japan, and Fujitsu Microelectronics, Inc.
All Rights Reserved.
This document contains information considered proprietary by Fujitsu Limited, Tokyo, Japan, and its
subsidiaries. No part of this document may be copied or reproduced in any form or by any means, or
transferred to any third party without the prior written consent of Fujitsu Limited.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor
applications. Consequentiy, complete information sufficient for construction purposes is not necessarily
given.
The information contained in this document has been carefully checked and Is believed to be entirely
reliable. However, Fujitsu Limited and its subsidiaries assume no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent
rights or trade marks claimed and owned by Fujitsu Limited or its subsidiaries.
Fujitsu Limited and its subsidiaries reserve the right to change praducts or specifications without notice.
This document Is published by the Technical Publications Department, Fujitsu Microelectronics, Inc.,
3320 Scott Blvd., Santa Clara, California, U.S.A. 95054-3197.
Printed in the U.S.A.

Fujitsu Limited
Fujitsu Limited, headquartered near Tokyo, Japan, is Japan's largest supplier
of computers and ranks in the top ten companies operating in Japan.
Fujitsu is also one of the world's largest suppliers of telecommunications
equipment and semiconductor devices.
Established in 1935 as the Communications Division spinoff of Fuji Electric
Company Lir,lited, Fujitsu Limited, in 1985, celebrated 50 years of service to
the world through the development and manufacture of state-of-the-art
products in data processing, telecommunications and semiconductors.
Fujitsu operates subsidiaries worldwide in two dozen countries and employs
over 70,000 people to generate annual sales in excess of six billion US dollars. (As of March 31, 1985 consolidated base.)
Fujitsu has five plants in key industrial regions in Japan covering all steps of
semiconductor production. Five wholly owned Japanese subsidiaries provide
additional capacity for production of advanced semiconductor devices. Two
additional facilities operate in the U.S. and Europe to help meet the growing
worldwide demand for Fujitsu semiconductor products. In all, Fujitsu operations occupy over 1.6 million square meters of manufacturing space
worldwide.
Semiconductor Products
In 1985 Fujitsu introduced 1M-bit DRAMs as well as a 256K-bit SRAM, 1M-bit
EPROMs and a 1M-bit ROM. A 1M-bit SRAM will be introduced in 1986 or
1987 to further compliment the already available full range of dynamic and
static memories in low-power CMOS as well as high-speed NMOS and ECl
versions.
Fujitsu offers a full line of 4-bit, 8-bit and 16-bit microprocessors and
peripherials to provide designers with a total of 150 products including 90
products in CMOS families, 50 products in NMOS families and 10 products in
bipolar peripherals.
Fujitsu's Digital Signal Processor provides deSigners of telecommunications
and speech recognition equipment with the world's fastest digital signal
processor. It is also one of the world's largest integrated circuit designed
using "standard cell" technology.
Other Fujitsu industry standard products include GaAs FETs, GaAs FET
amplifiers, Si MW transistors and light wave semiconductors. Discrete
products include a high speed switching power transistor and a Darlington
transistor.
Fujitsu's custom product lines include application-specific gate arrays and
standard-cell arrays using high-speed Bipolar and ECl technologies and advanced CMOS technologies. Gate arrays ranging in size from 350 to 20,000
gates are available, many with on-chip memory. Standard-cell arrays are
available up to 8000 gate equivalents and also include on-chip memory and
PlA.
Virtually every major type of electronics equipment on the globe utilizes
Fujitsu technology in integrated circuits. Fujitsu's leadership position in
worldwide integrated circuit development and manufacturing assures equipment manufacturers that they will always. be able to design with the latest in
technology utilizing the highest standards of quality and reliability.

iii

Fujitsu Microelectronics, Inc.
Established in 1979, Fujitsu Microelectronics, Inc., headquartered in Santa
Clara, California, markets Fujitsu semiconductors through representatives
located throughout the U.S. and North America.
The Component Division, Fujitsu Component of America, Inc., markets
bubble memories, keyboards, plasma displays, relay switches, hybrid ICs
and the newly introduced "IC Card" which incorporates a microprocessor
into a credit card.
FMI's San Diego manufacturing facility provides capacity for manufacturing of
many high-technology devices for the U.S. and North American market.
Customer support for custom designs is available through Fujtsu's design
centers in Santa Clara, Dallas and Boston. Technology Centers offering onsite customer training, CAE design facilities and design assistance are
planned for 1986.
Fujitsu Mikroelektronik GmbH (European Sales Center)
Fujitsu Mikroelektronick GmbH (FMG) was established 'in June, 1980, in
Frankfurt, West Germany, and is a totally owned subsidiary of Fujitsu
Limited, Tokyo. FMG is the sole representative of the Fujitsu Electronic
Device Group in Western Europe. The wide range of IC products, LSI
memories and, in particular, gate arrays are noted throughout Western
Europe for design excellence and unmatched reliability. Five branch offices
to support Fujitsu's semiconductor operations are located in Munich, London,
Paris, Stockholm, and Milan.
Fujitsu Microelectronics Ireland, Ltd (European Production Center)
Fujitsu Microelectronics Ireland, Ltd. (FME) was established in 1980 in the
suburbs of Dublin as Fujitsu's European Production Center for integrated circuits. FME supplies 64K/256K DRAMs, 64K CMOS/NMOS EPROMs, 256K
EPROMs, and other LSI memory products.
Fujitsu Microelectronics, Ltd (European Design Center)
Fujitsu Microelectronics, Ltd., Fujitsu's European VLSI Design Center, opened
in October of 1983 in Manchester, England. The Design Center is equipped
with a highly-sophisticated CAD system to ensure fast and reliable processing of input data. An experienced staff of engineers is available to assist in
all phases of the design process.

iv

Table of Contents
Section 1

1-1 NMOS Dynamic RAMs
1-2 MB8118
1-12 MB81256
1-30 MB81257
1-50 MB81256-W
1-66 MB81257-W
1-84 MB81416
1-102 MB81461
1-129 MB81464
1-148 MB811000
1-161 MB811001
1-176 MB8264A
1-192 MB8264A-W
1-199 MB8265A
1-219 MB8266A
1-239 MB85101A
1-241 MB85103A
1-243 MB85108A
1-245 MB85201
1-263 MB85203
1-282 MB85204
1-299 MB85208
1-318 MB85210
1-337 MB85211
1-354 MB85213
1-367 MB85214
1-379 MB85227

Section 2

2-1
2-2
2-22

Section 3

3-1
3-2
3-8
3-16
3-24
3-31
3-39
3-46
3-54
3-55
3-64
3-73
3-80
3-88
3-96
3-102
3-110
3-118
3-125
3-132
3-144
3-154
3-166
3-177

CMOS. Dynamic RAMs
MB81 C258
MB81 C466

CMOS Static RAMs
MB81C67
MB81 C67-W
MB81C68
MB81C68-A
MB81 C68-W
MB81 C69A
MB81 C71
MB81C74
MB81 C78
MB81C79
MB81 C86
MB8416/8416L
M B84 16AI 8416AL
MB8416W
MB8417/8417L
MB8417A/8417AL
MB8418/8418L
MB8418A18418AL
MB8464/8464L/8464LL
MB8464X/8464W
MB8464A/8464AL/8464ALL
MB8464AW
MB84256/84256L

v

Section 4

4-1
4·2
4·10
4·16
4·22

NMOS Static RAMs
MB8128
MB8167A
MB8168
MB8171

Section 5

5-1
5·2
5·10
5·17
5·27
5·36

NMOS EPROMs
MBM2764/2764X
MBM27128
MBM27128X
MBM27256
MBM27256X/27256W

Section 6

6-1
6·2
6·13
6·24
6·35
6·47
6·55
6·64
6·72
6·74
6·76

CMOS EPROMs
MBM27C64
MBM27C64X/27C64W
MBM27C128
MBM27C256
MBM27C256A
MBM27C256AW
MBM27C512
MBM27C1001
MBM27C1024
MBM27C1028

Section 7

7·1
7·2
7·10
7·18

CMOS EEPROMs
MBM28C64
MBM28C65
MBM2212

Section 8

8·1
8·2
8·8
8·12
8·18

ROMs
MB83256
MB83512
MB831 000
MB831124

Section 9

9·1
9·2
9·8
9·14
9·20
9·26
9·31
9·37
9·43
9·49
9·55
9·61
9·67
9·73
9·79
9·85
9·92
9·101

ECLRAMs
MBM10415AH
MBM10422A
MBM100422A
MBM10470A
MBM100470A
MBM10474A
MBM100474A
MBM10480
MBM100480
MBM10484
MBM100484
MBM10490
MBM100490
MB70801
MB70802
MB7700H Series
MBM93419

9·105
9·106

Advanced Information
MBM10422A
MBM100422A

vi

Section 9 - continued

9-107
9-108
9-109
9-110
9-111
9-112

Section 10

Section 11

10-1
10-2
10-3
10-4
10-5
10-11
10-12
10-13
10-14
10-23
10-24
10-33
10-34
10-43
10-52
10-61
10-70
10-80
10-88
10-99
10-109
10-120
10-129
10-139
10-147
10-156
10-157
10-166
10-172
10-173
10-186
10-199
10-200

MBM10474A
MBM100474A
MBM10480A
MBM100480A
M BM 10484A11 00484A
MBM10494/100494

Bipolar PROMs
Cross Reference
Temperature Ranges
Fujitsu PROM Technology
Programming Information
Fujitsu Approved PROM Programmers
DEAPTM Technique
DEAPTM Cell Structure
MB7111 E/H, MB7112E/H
MB7111 Ll7112L
MB7113E/H, MB7114E/H
MB7113L17114L
MB7115E/H, MB7116E/H
MB7117E/H, MB7118E/H
MB7121 E/H, MB7122E/H/Y
MB7123E/H, MB7124E/H
MB7127E/H, MB7128E/H/Y
MB7128E-W
MB7131 E/H,MB7132E/H/Y,MB7131 E-SK/H-SK,MB7132E-SK/H-SKIY-SK
MB7133E/H, MB7134E/HIY
MB7137E/H,MB7138E/H/Y,MB7137E-SK/H-SK,MB7138E-SK/H-SKIY-SK
MB7138E-W
MB7141E/H, MB7142E/H
MB7142E-W
MB7143E/H, MB7144E/H/Y
MB7144Y
MB7144E-W
MB7151 E/H, MB7152E/H/Y
MB7212RA17212RS
MB7226RA17226RS
MB7232RA17232RS
MB7238RA17238RS
MB7242RS

11-1 Application and Technical Notes
11-2 AN-006 Fujitsu EPROMs Programming, Erasing and Data Retention
11-9 AN-008 Fujitsu Registered PROMs after a New Tool for
the Logic Designer
11-13 Addressing Considerations When Testing the MB8125617
11-16 TB-001 Addressing Considerations When Testing the MB8264
and MB8265
11-19 TB-003 Leakage and Continuity Test Considerations Using
Fujitsu Microelectronics' Single Supply DRAMs

vii

Section 12

12-1 Ordering Information
12·2 Product Marking Specifications
12·2 Ordering Code

FUJITSU reserves the right to change products and specifications without notice.
This information does not convey any license under patent rights of FUJITSU LTO. or others.

viii

NMOS Dynamic

RAMs

MB8118 .................................. 1-2
MB81256 ................................ 1-12
MB81257 ................................ 1-30
MB81256-W .............................. 1-50
MB81257-W .............................. 1-66
MB81416 ................................ 1-84
MB81461 ................................ 1-102
MB81464 ...................... '" ....... 1-129
MB811000 ............................... 1-148
MB811001 ............................... 1-161
MB8264A ................................ 1-176
MB8264A-W ............................. 1-192
MB8265A ................................ 1-199
MB8266A ................................ 1-219
MB851 01 A ............................... 1-239
MB85103A ............................... 1-241
MB85108A ............................... 1-243
MB85201 ................................ 1-245
MB85203 ................................ 1-263
MB85204 ................................ 1-282
MB85208 .........•...................... 1-299
MB85210 ................................ 1-318
MB85211 ................................ 1-337
MB85213 ................................ 1-354
MB85214 ................................ 1-367
MB85227 ................................ 1-379

MB8118-10
MB8118-12

FUJITSU
MICROELECTRONICS

NMOS 16.384-BIT DYNAMIC
RANDOM ACCESS MEMORY
DESCRIPTION
The Fujitsu MB8118 is a fully decoded dynamic NMOS random access memory organized as 16,384
one-bit words. The design is optimized for high-speed, high performance applications such as
mainframe memory, buffer memory
peripheral storage and environments where low power dissipation
and compact layout are required.
Multiplexed row and column address inputs permit the MB8118 to
be housed in a standard 16-pin DIP.
Pin outs conform to the JEDEC approved pin out.

The MB8118 is fabricated using
silicon-gate NMOS and Fujitsu's advanced Double-Layer Polysilicon
process. This process, coupled with
single-transistor memory storage
cells, permits maximum circuit density and minimal chip size. Dynamic
circuitry is employed in the design,
including the sense amplifiers.
Clock timing requirements are noncritical, and power supply tolerance
is very wide. All inputs are TTL
compatible; the output is threestate TTL.

CERAMIC PACKAGE
DlP-16C-C03

FEATURES
.16,384 x 1 RAM, 16 pin package
• Silicon-gate, Double Poly
NMOS, single transistor cell
• Address access time:
100 ns max (MB8118-10)
120 ns max (MB8118-12)
• Cycle time:
235 ns min (MB8118-10)
270 ns min (MB8118-12)
• Low power:
182mW max (MB8118-10)
160mW max (MB8118-12)
16.5mW max (Standby)
• +5Vsinglepowersupply, ±10%
tolerance
• On chip substrate bias
generator

• All inputs TTL compatible, low
capacitive load
• Three-state TTL compatible
output
• Hidden refresh capability
• Common 1/0 capability using
"Early Write" operation
• Output unlatched at cycle end
allows extended page boundary and two-dimensional chip
select
• Read-Modify-Write, RAS-only
refresh, and Page-Mode
capability
• On-chip latches for Addresses
and Data-in
• Pin compatible with Intel 2118
and MCM4517

PLASTIC PACKAGE
DlP-16P-MOl

PIN ASSIGNMENT
N.C.
D'N

WE

MB8118
BLOCK DIAGRAM

Vss

CAS
DOUT

RAS

A.

Ao

A3

A2

A.

A,

vce

A.
N.C.

This device contsins circunry to protect the
inputs against damage due to high static voltages or electric fields. However, n is advised
that normal precautions be taken to avoid
application of any voltsge higher than maxi·
mum rated voltages to this high impedance
, circuit.

A,

A,

FUJITSU reserves the right to change products and specifications without notice. This information does not convey any license under patent rights
of FUJITSU LTD. or others.

1-2

MB8118-10/MB8118-12
ABSOLUTE MAXIMUM RATINGS

(See NOTE)

Rating
Voltage on any pin relative to vss

Symbol

Value

Unit

VIN, VOUT

-1to +7

V

Vcc

-1to+7
55 to +150

Voltage on VCC pin relative to V ss
eramic
Plastic

Storage temperature

TSTG

V

'c

55 to +125

Power dissipation

PD

1.0

W

Short circuit output current

-

50

mA

NOTE:

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detaited in the operational
sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Value
Parameter

Symbol

Min

Typ

Max

Vcc

4.5

5.0

5.5

V

VSS

0

0

0

V

Input High Voltage, all inputs

V,H

2.4

6.5

V

Input Low Voltage, all inputs

V,L

-1.0

0.8

V

Supply Voltage

CAPACITANCE

(TA

-

Operating
Temperature

Unit

O'Cto +70'C

= 25'C)
Value

Parameter
Input Capacitance Ao

-

Symbol

A6, DIN

Min

Input Capacitance RAS, CAS, WE

CIN2

Output Capacitance DOUT

COUT

Typ

-

CIN1

-

Max

Unit

5

pF

8

pF

7

pF

STATIC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

Parameter

Notes

Symbol

MB8118-10

MB8118-12

Min

Max

Min

Max

Unit

ITl

OPERATING CURRENT

ICCl

-

33

-

29

mA

ICC2

-

3.0

-

3.0

mA

ICC3

-

25

-

22

mA

ICC4

-

25

-

22

mA

I,L

-10

10

-10

10

/-LA

IOL

-10

10

-10

10

/-LA

Output Low Voltage (IOL = 4.2 mAl

VOL

-

0.4

-

0.4

V

OUTPUT LEVEL
Output High Voltage (IOH

VOH

2.4

-

2.4

-

V

Average Power Supply Current (RAS, CAS cycling; tRC

= Min)

STANDBY CURRENT
Average Power Supply Current (RAS
High Impedance)

= CAS = VIH, DOUT =

REFRESH CURRENT
Average Power Supply Current (RAS cycling, CAS

ITl

= V,H; tRC = Min)

PAGE MODE CURRENT

ITl

Average Power Supply Current (RAS

= V'L, CAS cycling, tpc = Min)

INPUT LEAKAGE CURRENT
Input Leakage Current, any input (OV ,,;; Y,N ,,;; 5.5)
Input pins not under test = OV, 4.5V,,;; Vcc";; 5.5V, Vss

= OV

OUTPUT LEAKAGE CURRENT
(Data out is disabled, OV,,;; VOUT";; 5.5V)
OUTPUT LEVEL

Nole:

[j]

=

-5 mAl

Icc IS dependent on output loading. Specified values are obtained with the output open.

MICROELECTRONICS __________________________________________________~
FUJITSU
1-3

MB8118-1O/MB8118-12
DYNAMIC CHARACTERISTICS

NOTES 1,2,3
(Recommended operating conditions unless otherwise noted.)
MB8118-10
Parameter

Notes

Symbol

Min

Time Between Refresh

tREF

-

Random Read/Write Cycle Time

tRC

235

Read-Write Cycle Time

tRWC

285

Page Mode Cycle Time

tpc

125

Typ
-

-

Access Time from RAS

moo

tRAC

-

Access Time from CAS

[[JOO

tCAC

-

tOFF

0

IT

3

tRP

110

RAS Pulse Width

tRAS

115

RAS Hold Time

tRSH

70

CAS Prechange Time (all cycles except page mode)

tCPN

50

tcp

60

CAS Pulse Width

tCAS

55

CAS Hold Time

tCSH

100

-

tRCD

25

-

CAS to RAS Precharge Time

tCRP

0

Row Address Set Up Time

tASR

0

Row Address Hold Time

tRAH

15

Column Address Set Up Time

tASC

0

Column Address HoldTime

tCAH

15

tAR

60

-

Read Command Set Up Time

tRCS

0

-

Read Command Hold Time

tRCH

0

-

twcs

0

-

Write Command Hold Time

tWCH

30

Write Command Hold Time Referenced to RAS

tWCR

75

twp

30

Write Command to RAS Lead Time

tRWL

60

Write Command to CAS Lead Time

tCWL

45

Data In Set Up Time

tDS

0

Data In Hold Time

tDH

30

tDHR

75

tCWD

55

tRWD

120

-

tRRH

20

-

Output Buffer Turn Off Delay
Transition Time
RAS Precharge Time

CAS Precharge Time (Page mode only)

RAS to CAS Delay Time

III 00

Column Address Hold Time Referenced to RAS

Write Command Set Up Time

00

Write Command Pulse Width

Data In Hold Time Referenced to RAS
CAS to WE Delay
RAS to WE Delay
Read Command Hold Time Referenced to RAS

00
00

Notes:

MB8118-12

Typ
-

Max

Unit

2

ms

-

-

ns

-

ns

145

-

100

-

-

120

ns

55

-

-

65

ns

45

0

50

ns

50

3

-

50

ns

-

ns

85

-

55

-

70

-

-

ns

10000

65

-

10000

ns

-

120

45

25

-

Max
2

-

10000

-

-

-

-

-

Min

270
320

120
140

10000

ns

ns

-

ns

-

ns

-

ns

55

ns

-

ns

-

ns
ns

-

ns

0

-

-

ns

0

-

-

ns

0

-

ns

35
90

-

35

-

-

65

~

0
0
15
0
15
70

-

-

-

ns
ns

ns
ns
ns
ns

-

ns

0

-

35

-

-

ns

90

-

ns

-

ns

120

-

25

-

-

ns

50

65

ns

ns

fIl Operation within the tRCO (max) limit insures that tRCO (max) can
be met. tRCO (max) is specified as a reference point only; iftRCO is
greater than the specified tRCO (max) limit, then access time is
controlled exclusively by tCAC.
00 tRCO(min)=tRAH(min)+2tT(tT=5ns)+lASC(min).
III twcs, tcwo and tRWO are not restrictive operating parameters.
They are included in the data sheet as electrical characteristics
only. If twcs>twcs (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout
entire cycle. Iftcwo>tcwo (min) and tRWO>tRWO (min), the cycle
is a read-write cycle and data out will contain data read from the
selected cell. If neither of the above sets of conditions is satisfied
the condition of the data out is indeterminate.

[]] An initial pause of 200"s is required. Then several cycles are
required after power up before proper device operation is
achieved. Any 8 cycles which perform refresh are adequate for this
purpose.
rn Dynamic measurements assume tT=5ns.
I!l VIH (min) and VIL (max) are reference levels for measuring timing
of input signals. Also, transition times are measured between VIH
and VIL.
I!l Assumes that tRCOtRCO (max).
00 Measured with a load equivalent to 2 TTL loads and 100pF.

1-4

MB8118-10/MB8118-12
READ CYCLE TIMING DIAGRAM

r---------------------tRc----------------------~

V IH _ _ _ _--./

f--_______ tAR-----t~_iAI S

V ,L tCSH--;- - -------~-1

----,t
I

ADDRESSES

tRSH
CAS - -

V'HV,L t--tRRH

~tRCH
WE

V'HV'L-

!---tCAC
tRAC

DOUT

VOHVOL-

J

tOFF

VALID
DATA

HIGH-Z

o

Don't Care

WRITE CYCLE (EARLY WRITE)

I tCSH--I

tRSH---+-1

VIH_-----J1:==~~;;::~t'~II----tCAS
V,L -

WE

V'HVIL- _ _ _ _ _

~-~--~--~--~--------~---------I
tWCR~'--~----~

r--tOS
D,N

DOUT

V'HV'L-

r-- tOH

VALID
DATA

VO H ----------------HIGH-Z---------------VO L Don't Care

o

MICROELECTRONICS ________________________________________________~
FUJITSU
1-5

MB8118-10/MB8118-12
READ- WRITE/READ-MODIFY-WRITE CYCLE

RAS

V'HV'L-

~-------------------------IRWVle~-=-==================~======:j
r--------------------RAs--~~--------IAR------~

----:-------tRsH----------""i

IReD------+~----'------leAs--------------__i

---'-'-----.1----.
CAS

r--lr---,

VIL -

ADDRESSES

V'HV'L-

WE

V'HV'L-

r-------- leWD --------1

DOUT

L,eAe=i~.,.......,,-------J~IOFF

VOH- - - - , - - - - - - - - - - H I G H - Z
VOL-

VIH-

V'L-

VALID

_

DATA

IIDSd~

IRAe
D,N

.

____~_____________________________J>t~~j;g=;<==:::==============
D Don't Ca,e
7);,*,

"RAS-ONLY" REFRESH CYCLE
NOTE: CAS = V'H, WE = Don't care

DOUT

VOH- _ _ _ _ _ _ _ _ _ _ _ _ _ _ HIGH_Z
VOL:------------------

D

1-6

Don't Care

MB8118-10/MB8118-12
PAGE MODE READ CYCLE

~------------------------tRAS---------------------~----~~
RAS

V'HV'L-

CAS

V'HV ,L-

~==~~~~======~--~------------,~~===tC=A=S~t:R:S~H~1:_~'-

ADDRESSES

tOFF

DOUT

VOHVOL-

WE

V,H V'L-

Jf

o

Oon't Care

o

Don't Care

PAGE MODE WRITE CYCLE

RAS

V'HV'L-

CAS

V'HV'L-

tASR
ADDRESSES

~:~

WE

V'HV'L-

D,N

V'HV'L-

MICROELECTRONICS __________________________________________________~

FUJITSU

1-7

MB8II8-10jMB8II8-I2
HIDDEN RAS-ONLY REFRESH CYCLE TIMING DIAGRAM
~-----------tAC------------~

~------tAAs------I .It---~

ADDRESSES

DOUT

VOH-_ _ _ _ _ _ _ _ _ _ _ _o(L

VALID DATA

~------------------~

VOL-

•

Don't C...

DESCRIPTION
Address Inputs
A total of fourteen binary input address bits
are required to decode anyone of 16,3B4
storage cell locations within the MBBllB.
Seven row-address bits are established on
the input pins (Ao through As) and latched
with the Row Address Strobe (RAS). Sev~n
column-address bits are established on the
input pins and latched with the Column Address Strobe (CAS). All input addresses must
be stable on or before the failing edge of RAS.
CAS is internally inhibited JQI:..:'gated") by
RAS to permit triggering of CAS as soon as
the Row Address Hold Time (tRAH) specification has been satisfied and the address inputs
have been changed from row-addresses to
column-addresses.
Write Enable
The read mode or write mode is selected with
the WE input. A logic "high" on WE dictates
read mode; logic "low" dictates write mode.
Data inpuU!..disabled when read mode is
selected. WE can be driven by standard
TTL circuits without a pull-up resistor.
Date Input:
Data is written into the MBB118 during a write
or read-write cycle. The last falling edge of

WE or CAS is a strobe for the Data In (DIN)
register. In a write cycle, if WE is brought low
(write mode) before CAS, DIN is strobed by
~, and the set-up and hold times are referenced to CAS. In a read-write cycle, WE will
be delayed until CAS has made its ~ative
transition. Thus DIN is strobed by WE, and
set-up and hold times are referenced to WE.
Data Output
The output buffer is three-state TTL compatible with a fan-out of two standard TTL loads.
Data-out is the same polarity as data-in. The
output is in a high impedance state until CAS
Is brought low. In a read cycle, or a read-write
cycle, the output is valid alter tRAC from transition of RAS when tRCD (max~atisfied, or
alter tCAC from transition of CAS when the
transition occurs after tRCD (max). Data remains valid until CAS is returned to a high
level. In a write cycle the identical sequence
occurs, but data is not valid.
Page-Mode
Page-mode operation permits latching the
row-address into the MBBllB and maintaining RAS at a logic "low" throughout all successive memory operations in which the

row-address doesn't change. This saves the
power required by a RAS cycle. Access and
cycle times are decreased because the time
normally required to strobe a new rowaddress Is eliminated.
RA8-0nly Refresh
Refresh of the dynamic memory is accomplished by performing a memory cycle at
each of the 12B row-addresses at least every
two milliseconds. RAS-only refresh prevents
any output during refresh because the output
buffer is in the high impedance state since
CAS is at VIH. Str.Q~ each of the 12B
row-addresses with RAS will cause all bits in
the memory to be refreshed. RAS-only refresh results in a substantial reduction in
power dissipation.
Hidden Refresh
RAS-ONLY REFRESH CYCLE may take
place while maintaining valid output data.
This feature is referred to as Hidden Refresh.
Hidden Refresh is performed by holding CAS
at VIL from a previous memory read cycle.
(See Figure 1 below)

~~_ _ _ _R_E_A~D~,Y_C_L_E---__:J:~_R_AS_O_N_LY-J:::,R_E_SH_C_Y_C_L_E~

FIG, I-HIDDEN REFRESH

~~

DOUT

__________________--J/

---HIGH-Z--<~_ _ _ _ _ _ _V_A_L_ID_D_A_T_A_ _ _ _ _ _..J)>-----

1·8

MB8118-10/MB8118-12
FIG. 2-CURRENT WAVEFORMS
R"AS"

RAS";c;D;S CYCLE

v"

LONG RAS/CAS CYCLE

II

!

V'H

CAS

= 5.0V, TA = 25°C)

ONLY CYCLE

I

V,H

RA!:

(Vee

V'L
V,H

~

1\

V,L

I

f-

-

-+1f-

-

I

:
I

~-

t

80

60

Icc
(rnA)

40

1/

20

I"

\

I"

n

1\
\

II

A

r---

A

.-

' \1
\ 1

~

,/

1-1-'

IIY

V'

i"

I-'

SOns/Division

TYPICAL CHARACTERISTICS CURVES
vs AMBIENT TEMPERATURE
o

w

w

T)70°C

:;;

i=

en
en
~
u

1.1

.:

"w 1.0
N

~

0.9

i2

I'\.

U
.:

f!.

«

"-~

.:
o
w

~

a:

o

O.S

z

z

4.0

::>

40

(!)

30

i=
~

20

z

'-

w

0.

o

O.S

10

r---.......

~As-SOOn'

;:;

u

.:0:

40

20

60

so

t RAS

o

200

400

600

='1'5ns
800

1000

TA, AMSIENT TEMPERATURE lOCI

'RC, CYCLE TIME In'l

OPERATING CURRENT
(TYPICAL) v. SUPPLY VOLTAGE

OPERATING CURRENT (TYPICAL)
vs AMBIENT TEMPERATURE

STANDBY CURRENT
(TYPICAL) vs SUPPLY VOLTAGE

~

TA 25°C
'Rc=235nS
'RAS=llSnS

50

40

(!)

30

~
a:

20

w

0.

o 10

--

«
E
f-

zw

Veel=S.OV
'RC=23Sns_
tRAS=115ns

50

a:
a: 40
30

>-

~
a:

20

~

"'"z

w

o

10

2
5.0
Vee. SUPPLY VOLTAGE IVI

6.0

3.01---+--+---1---1

2.0

I--_-+__+ __

+-_~

N

II

;:;
4.0

4.01----+--+--+---1

a:

0.

0

f-

zw

(!)

z

~

«
E

aa:

::>

u

;:;

2

a:
a:

Vccl=S.OV
TA=2SoC-

Vcc. SUPPLY VOLTAGE IVI

u

z

6.0

5.0

50

::>
u

U

w

a:
a:

/'

V

V

0.9

f-

zw

./

1.0

N

:;;

E
f-

/'

~ 1. 1

u

:;;

a:
o
z

1.2

«
E

Ved=4.SV

:;;

i= 1.2

OPERATING CURRENT
(TYPICAL) vs CYCL.E TIME

NORMALIZED ACCESS TIME

iliORMALIZED ACCESS TIME
vs SUPPLY VOLTAGE

0

o

40

20

60

so

T A , AMBIENT TEMPERATURE lOCI

1-9

1.01----+--+--+---l
4.0

5.0
Vce, SUPPLY VOLTAGE IVI

6.0

MB8118-10/MB8118-12

TYPICAL CHARACTERISTICS CURVES

STANDBY CURRENT (TYPICAL.)
vs AMBIENT TEMPERATURE

<1
i
f-

0:
0:

:>

u

Ve~=5.5V

r--

>-

""'
~

2.0

f-

en
N

..y

Ve~=5.0V

<1
i

1.0

----

fZ

UJ

UJ

40

20

40

0:
0:

:>

u

30

I

en

w

UJ

0:

0:

20

u.
w

10

'"

u

200

!z

UJ

0:
0:

30
20

~

0:
0:

.......

f-

0:

u

zw

6

10

o
o

20

40

1:
a

80

60

20

0

T A • AMBIENT TEMPERATURE lOCI

80

u

~
40

~

TA=125°C
V e e=4.5V-

f- 100

:>

Co.

UJ

'"

<1
i

T)25°C
Vee.=4.5V-

100

I

u.

OUTPUT LOW CURRENT
vs OUTPUT LOW VOLTAGE

!5 80
G 60

I

6.0

OUTPUT HIGH CURRENT

u

w

5.0
Vee. SUPPLY VOLTAGE (VI

0:

40

en
0:

4.0

w

tRAS=115nS

:>
U

o

vs OUTPUT HIGH VOLTAGE

i

tRe=235nS_

-

u

1000

800

<1

Vee~5.0

fZ

'"

10

tRe. CYCLE TIME In,l

REFRESH CURRENT (TYPICAL)
vs AMBIENT TEMPERATURE

50

0:

~

600

400

~

UJ

; "':RAs=500n,

t RAs -:15n,

o

80

20

u.

~ ......

0:

T A • AMBIENT TEMPERATURE (OCI

<1
i

40
30

I

en

60

tRe=235nStRAs=115nS

:>

u

~

o

50

Z

0:
0:

TA=~5°C

<1

i

TA=25°C-

50

f-

3.0

REFRESH CURRENT
(TYPICAL) vs SUPPLY VOLTAGE

REFRESH CURRENT
(TYPICAL) vs CYCLE TIME

4.0

z
UJ

(continued)

o

i'....

60

~

40

Co.

f-

6

~

20

.:,

.2

4.0

3.0

2.0

1.0

g

0

/

/

/

o

1.0

2.0

3.0

TYPICAL SUPPLY CURRENT vs SUPPLY VOLTAGE DURING POWER UP
11 RAS=V ee • CAS=V ee

I
5.0

~

t
'0

<1

>,.

i

0.

I"J
8:
,.2.0

Jl

u

~

0

Jl'"

u
u

4.0
3.0
2.0

•

-

I_

_I

I r-- ,
I

I'

-,-

I-

===

1.0

>

0

1_

21 RAS=VSS. CAS=Vss
I

-

I

Vee

5.0

~

--_.-

-

t

Icc

::.--

I
!a

4.0

>,.

!,. 

~

Ii

.~

--

.--

- _.

III

:-

0

I

I

-

Vee

-==

==

500SlS/Division

1·10

4.0

VOL. OUTPUT LOW VOLTAGE IVI

VOH. OUTPUT HIGH VOLTAGE (VI

11-

ICC

MB8118-10/MB8118-12
PACKAGE DIMENSIONS

Dimensions in inches (millimeters)

16-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
DIP-16C-C03
1
O"-15 U

.305(7.75)

------rr

.300(7.62)TYP

.325{S.26)

I

i

~rt_·_05_0_('_.2_7)_M_AX_ _ _ _ _ _ ___

Dimensionsm
inches (millimeters)

16-LEAD PI.;ASTIC DUAL IN-LINE PACKAGE
DIP-16P-MOl
1

. "E:::::J3~
,~:"~-LI

.748('9.00)

.798(20.27)

_,,.==-----r.°"-'5"

I

~'97(5.00)MAX

- + i " 8 ( 3 . 0 0 ) MIN.

I

--JI :::::::

=,.",."

1-11

.300(7.62} TYP.
)

FUJITSU

MOS Memories
•

MB81256-10, MB81256-12, MB81256-15
NMOS 262,144-Bit Dynamic
Random Access Memory

De.crlptlon
The Fujitsu MB81256 Is a fully decoded, dynamic NMOS random
access memory organized as 262,144 one-bit words. The design is
optimized for high speed, high performance applications such as
mainframe memory, buffer memory, peripheral storage and en·
vironments where low power dissipation and compact layout are
required.
The MB81256 features "page mode" which allows high speed ran·
dom access of up to 512·bits within the same row. Additionally, the
MB81256 offers new functional enhancements that make it more
versatile than previous dynamic RAMs. Multiplexed row and col·
umn address inputs permit the MB81256 to be housed in a Jedec
standard 16-pin dual in·line package and 16-pad lCC.
The MB81256 is fabricated using silicon gate NMOS and Fujitsu's
advanced Triple-layer Polysilicon process. This process, coupled
with single transistor memory storage cells, permits maximum cir·
cuit density and minimal chip size. Dynamic circuitry is used in the
design, including dynamic sense amplifiers.
Clock timing requirements are noncritical, and the power supply
tolerance is very wide. All inputs are TIL compatible.

Feature.
• 262,144 x 1·blt organization
• Row Access TIme/Cycle Time:
MB81256-10
100 nil MaxJ200 ns Min.
MB81256-12
120 ns MaxJ220 ns Min.
MB81256-15
150 ns MaxJ260 ns Min.
• low Power Dissipation:
314 mW max. (t RC = 260 ns)
25 mW (Standby)
• +5V supply voltage,
:1:10% tolerance
• All Inputs TIL compatible, low
capacitive load
• Three-state TIL compatible out·
put
• Common 110 capability using
"Early Write" operation
• On-chlp substrate bias
generator

• Page Mode Capability
• Fast Read-Write Cycle,
TRWC=TRC
• ~tWCR' tQll..&!IIWD eliminated
• CA5-betore-RAS on ~ refresn
• Hidden CAs-before-RAS on-chlp
refresh
• RA5-only refresh
• 4 msl256 cycle refresh
• Output unlatched at cycle end
allows two dimensional chip
select
• On-chlp Address and Data·ln
latchss
• Industry standard 16-pln
package

1·12

M881256·10
M881256·12
M881256-15

M8812118 Block Diagram
and Pin Aaslgnments
AS

V"

CAS

D

W

Q

As

RAS
A.

A,

A,

A,

A,

A,

Vee

A,

A,

Vss

CAS

Q
262,144.8IT
STORAGE CELL

'iii

~Vss

o As Vss CiS

lEADH1

Q

iiAS

At

N.C.

N.C.

(,
A6

CAS

Vi

As

Ao

A,

A7

A4

~
Q

Vss

D RAS

A2 Vee

A5

As"

16...)
ZIP.16p·M01
BOTTOM VIEW

W

--,
3 :

r---

--,

l~~_

4 oj:
RAS __
N.C 5 '

A.

s--!

A,

!j

LCC-18C-F04
TOP VIEW

A,

A,

A,

A.

Q

l~~-

A,;

113

Aa

:14 N.C.

r,-:i
L__

---1

A,

Vee

A,

A,

A,

r8-T~--r~~T111
Ai Vee A7 As
NOTE: The following IEEE Std. 662·1980 symbols are used In this data sheet: 0 = Data In, W= Wrlte Enable, Q = Data Out.

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Voltage on Any Pin relative to VSS

VIN. VOUT> Vcc

-1.0 to 7.0

V

Operating Temperature (ambient)

Tqp__.

o to 70

·C

-55 to +150
-55 to +125
1.0
50

W
mA

Storage Temperature

Ceramic
Plastic-

TSTG

Power Dissipation
Short Circuit Output Current

Po
los

·C

NOTE: Permanent device damage may occur it ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operations sections of this data sheet. 'Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated Yoltages to this high Impedance circuit.

Recommended Operating
Conditions
(Referenced to Vss)

Parameter

Symbol

Supply Voltage

Vr.r,

Input High Voltage All Inputs
Input Low Voltage All Inputs

VIH
VIL

Vss

FUJITSU
1-13

Value
Typ
Min

Max

Unit

4.5
0
2.4
-2.0

5.5
0
6.5
0.8

V
V
V
V

5.0
0

Operating Temperature

O·C to + 70·C (ambient)

-MB81256-10
MB81256-12
MB81256·15

Capacitance
(TA =25'C)

Velue
Min

S~mbol

Parameter

T~p

Max

Unit

C IN1

7

pF

Input Capacitance RAS, CAS and W

C IN2

10

pF

Output Capacitance Q

COUT

7

pF

Input Capacitance

An to As, D

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

MB81256·10 MB81256-12 MB81256·15
Min
Max Min
Max Min
Max Unit

Parameter

S~mbol

OPERATING CURRENT '1
Average Power Supply Current
(RAS, CAS cycling; tRC = Min.)

Icc1

70

65

57

rnA

STANDBY CURRENT
Power Supply Current
(RAS/CAS = V IH)

Icc2

4.5

4.5

4.5

mA

REFRESH CURRENT 1"
Average Powe!:..§!!pply Current
Icc3
(RAS cycling, CAS = V IH ; tRC = Min.)

60

55

50

mA

PAGE MODE CURRENT"
Average Power Supply Current
(RAS = V ll, CAS cycling; tpc = Min.)

1CC4

35

30

25

rnA

REFRESH CURRENT 2"
Average Power Supply Current
(CAS before RAS; tRC = Min.)

Ices

65

60

55

rnA

INPUT LEAKAGE CURRENT
Any Input, (VIN = OV to 5.5V,
Vcc = 5.5V, Vss=OV,
all other pins not under test = OV)

III

OUTPUT LEAKAGE CURRENT
(Data is disabled, VOUT=OV to 5.5V) 10l
OUTPUT LEVEL
Output Low Voltage
(Iol = 4.2 mAl
OUTPUT LEVEL
Output High Voltage
(loH = - 5.0 mAl

-10

10

-10

10

-10

10

I'A

-10

10

-10

10

-10

10

p.A

0.4

V

0.4

VOL

VOH

2.4

0.4

2.4

2.4

Nota: ·1 ICC is dependent on output loading and cyde rates. Specified values are obtained with the output open.

FUJITSU
1·14

V

MB81256·10
MB81256·12
MB81256·15

AC Characterlstics"1,2,3
(Recommended operating
conditions unless otherwise
noted.l

Parameter

Notes

Symbol
Alternate

Time between Refresh
Random Read/Write Cycle Time
Read-Write Cycle Time
Access Time irom RAS"',6
Access Time from CAS"5,6
Output Buffer Turn off Delay
Transition Time

'RAS
i'iMi
i'iMi
eAS
eAS

Precharge Time
Pulse Width
Hold Time
Pulse Width
Hold Time

RAS to CAS Delay Time"',?
CAS to RAS Set Up Time
Row Address Set Up Time
Row Address Hold Time
Column Address Set Up Time
Column Address Hold Time
Read Command Set Up Time
Read Command Hold Time Referenced to CAS'10
Read Command Hold Time Referenced to RAS'10
Write Command Set Up Time'S
Write Command Pulse Width
Write Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data In Set Up Time
Data In Hold Time
CAS to W Delay'S
Refresh Set Up Time for CAS Referenced to RAS
Refresh Hold Time for CAS Referenced to RAS

t AWC
t RAC
tOFF

tCSH

t CRS

tCAH

twcs
t WCH
tCWL

tCWD

CAS Precharge Time for eAS before
RAS Refresh Cycle

TRVRV
TRELREL
TRELREL
TRELOV
TCELOV
TCEHOZ
TT
TREHREL
TRELREH
TCELREH
TCELCEH
TRELCEH
TRELCEL
TCEXREL
TAVREL
TRELAX
TAVCEL
TCELAX
TWHCEL
TCEHWX
TREHWX
TWLCEL
TWLWH
TCELWH
TWLREH
TWLCEH
TDVCEL
TCELDX
TCELWL
TCELREL
TRELCEX
TCELCEL

Page Mode ReadIWrite Cycle Time
Page Mode Read-Write Cycle Time
Page Mode eAS Precharge Time
Refresh Counter Test RAS Pulse Width'.
Refresh Counter Test Cycle Time'.
RAS Precharge to CAS Active Time
Refresh Counter Test CAs Precharge Time'.

• Stendard

t ATC

t CPR

TCEHCEH
TCEHCEL
TRELREH
TRELREL
TREHCEL
TCEHCEL
TCEHCEL

MB81256·10
Min Max

MB81268·12
Min Max

4

4

200
200

1-15

120
60

150
75

Unit
ms
ns
ns
ns
ns

o

~

0

~

0

~

M

3
85
105

50

3

50

50

100000

120

100000

3
100
150

ns
ns
ns

55
105
20
10

100000

60
120
22
10

100000

75
150
25
10

100000

90

50

60

o

o

10

12

15

o

o

o

15

20

25

o
o

o

20

20

20

o

o

o

15
15
35
35

20
20
40

25
25
45
45

o

o

o

15
15
20
20
100
100
40

20
50

20
20
20
25
120
120
50
265
375
20
60

25
25
20
30
145
145
60
320
430
20
70

20

25

2~
3~

75

10000

~

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

o

40

10000

100000

o

o
o

Notes: -These symbols are described in IEEE STD. 662·1980: IEEE Standard terminology for semiconductor memory.

FUJITSU

4

260
260

220
220

100
50

MB812118·15
Min
Max

ns
ns
ns
ns
ns
ns

10000

ns
ns
ns
ns
ns
ns

MB81256.10
MB81256-12
MB812S6-15

AC Characteristics
(Continued)

Not..:

., An initial pause of 200~ is required after power up, followed by any 8 AAS cycles, before device operation Is achieved.

m

if the internal refresh counter is to be effective, a minimum of 8 CAS before
refresh Initialization cycles are required.
*2 AC characteristiCS assume
= 5 ns.
"3 VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also. transition times are measured between

tr

VIH and Vil'
*4 tRCD Is specified as a reference point only. If tRCD "" tRCO (Max.) the specified maximum ~alue of tRAe (Max.) can be met.
If tRCD > tACO (Max.) then tRAe is increased by the amount that tRCD exceeds tRCD (Max.).
·5 Assume. 'ha' 'RCD > 'RCD (Max.).
*6 Measured with a load equivalent to 2 TTL loads and 100pF.
·7 'RCD (Min.) = 'RAH (Min.) + 2I-r + 'ASC (Min.).
"8 twcs and leWD are nonrestrictive operating parameters, and are Included In the data sheet as electrical characteristics only. If
twcs > twcs (Min.), the cycle Is an early write cycte, and the data out pin will remain open circuit (High Impedance) throughout
the entire cycJe.

:~~~~:s ~~n~~~~~ ~~:~~i~~~ ~~~~~~~ ~C!~:~:~a~t~~I=~~~ta read from the selected cell. If neither of the
*9 Test mode write cycle only.
*10 Either tRCH or tRRH must be satisfied for a read cycle.

Timing Diagrams.

R.sd Cycl.
I~·~-------------------IRC--------------------~

VIH ---~~-------IRAS-------_.I

1-----.."L

RAS
VIL
VIH

~--~------~_---ICSH-----------+~~

"7f"7t"la:--------:s:::"\. i"'......
1 _-_-_-_-_-_-_~_IR_S_H-I-C-AS--------~~_+__+1

VIL

A

w
Q

~

·FUJITSU

1·16

Don'le...

MB812S8-10
MB81256012
MB81256·15

Timing Diagram.
(Continued)
I~--------------------IRC--------------------~
I---------------RAs ---------------I..U=-----:L
~--~----------_ICSH---------I~

~~~-----~~ ~--------IRSH~--~~~~r------~

VALID

DATA~XXXXXXX)<

--------------HIGH-Z------------~

Don'tCare

Re.d·WrltelRe.d.Modlfy.Wrlte Cycle

V'H

-----~ ~---------------

V'L

CAS

V'H

..,..,..,d::--+--------.l:......

1-00--------

'\..:!!"-------------if--''f"

V'L

A

w
Q

V,H~~~~~~~~~-~------:k
~ _ _~~~~o/'~DL~C.

V'L

VOH _______

VALID DATA
~~======~~====~~---~~~DD~;---~_3~-----

VOL
D

,IDsl

~

::~XXXXXXX_

L

~

IDH_

....,.~"A"'''''\7

VALID D A T A X X X X X X X

~Don'lcare

FUJITSU
1-17

MB81256·10
MB81256-12
MB81256-15

Timing Diagrams
(Continued)

"RAS·Only" Refresh Cycle
NOTE: W, D = Don't Care, As, V,H or V'L

IRC
tRAS

ADDRESS
(Ao to A7)

---

VIH
Vil

IRP

I--'RAH_

f-

tASR

IL

tAPe

ROW
AQDRESS

H'CRS

~
t-

tOFF

Q

HIGH·Z

~Don'tcare

Page Mode Read Cycle

RAS

RI ---

I-----------RAS----------....

11;:::~~~~~~~~----~r-~.-~,:R-sH--~.~
CAS

'~I.j<"'r""">ll

1'<'7...,.1-7..,....--::1..

...-tCAS

A

VIHIUI~70Oi;N:'_t--"""';;;.;..."1I:~H---'Hr-_t----_t--_tro'\J
VILo.~~Ql.Y

VALID
DATA

Q

FUJITSU
1-18

-MB81256·10
MB81256·12
MB81256·15

Timing Diagrams
(Continued)

Paga Moda Wrlta Cycla

'R.

RAS

' . A ' - " R,---

VOH

11::===~~==~~----------------~r---~----'-.-'H-~---~·

VOL

teAs ----. , -_ _ __

CAS

A
VOL

W

VOH
VOL

Q

VOH
VOL

0

VOH
VOL

~Don·IC.,.
Hidden Refresh Cycle
k-·------tRC----~~

RAS

V,H ---~.k----tRAS----I~U:-----::i-tRAS----I~
V'L

CAS

V,H
V'L

A

V,H
V'L

W (Read)

V,H
V'L
VOH

Q

VOL

Vi (Read·Wrlte)

V,H
V'L

~Don'tCar8

FUJITSU

1·19

MB81256·10
MB81256·12
MB81256-15

Timing Diagrams
(Continued)

"CiS·Before·RAS" Refresh Cycle
NOTE: A, W, D = Don't Care

RAS

V'H
V'L
V'H

CAS

V'L
V'H

~tOFF

----------H'GH-Z---------__

Q

V'L

rgz] Don't Car.

Page Mode Read·Wrlte Cycle

V'H

RAS

V'L

CAS
V'L
V'H

A
V'L

Vi

V'H
V'L
V'H

Q
V'L
VOH

D
VOL

mOon'tcare

FUJITSU

.1·20

MB81256·10
. MB81258·12
MB81256-15

Timing Diagrams
(Continued)

"CAS·Before·RAS" R.fresh Counter Test Cycle
~----------t"T·C----------I

iiAS

V,H
V,L
V,H

CAS

V,L
V,H

A

VI (Read)

Q

D

V,H
V,L

U'l:70ot70"O"IJ'tj'O'i:7'G'O'iJ'\.7O'onr-=:::-::=~kJ1'~~~1U'I~'J
Dl..l£l.DJ.:l.l:\'oDl..l£l.,Q.j~~D.J.~>U'I--':':':::::':=--"""\l£:~O£~Dl.lQ~

~

FUJITSU

1·21

Don'lCare

MB81256.10
MB81256·12
MB81256·15

Description

Simplified Timing Requirement
The MB81256 has improved circuitry that eases timing requirements for high speed access operations. The M B81256
can operate under the cond ition of tRCO (max) = t CAC, thus
providing optimal timing for
address multiplexing. In addition, the MB81256 has minimal
hold times for Addresses
(t CAH ), Write-Enable (t WCH) and
Data·in (t OH ). The MB81256 provides higher throughput in
inter-leaved memory system
applications. Fujitsu has made
the timing requirements that
are referenced to RAS nonrestrictive and deleted them
from the data sheet. These include tAR, t WCR , tOHR and t RWO·
As a result, the hold times of
the Column Address, 0 and Vi
as well as t cwo (CAS to Vi
Delay) are not restricted by
tRCO·
Fast Read·Wrlte Cycle
The M B81256 has a fast read·
modify-write cycle which is
achieved by precise control of
the three-state output buffer as
well as by the simplified timings described in the previous
section. The output buffer is
controlled by the state ofW
when CAS goes "low". When
Vi is "low' during a CAS transi·
tion to "low", the MB81256
goes into the early write mode
in which the output floats and
the common I/O bus can be used on the system level. When
Vi goes "low", after t cwo
following a CAS transition to
"low", the MB81256 goes into
Ihe delayed write mode. The
output then contains the data
from the cell selected and the
data from 0 is written into the
cell selected. Therefore, a very
fast read-write cycle
(tRwC = tRd is possible with
the MB81256.
Address Inputs
A total of eighteen binary input
address bits are required to
decode any 1 of 262,144 cell
locations within the MB81256.
Nine row-address bits are
established on the input pins
(Ao through A~ and are latched
with the Row Address Strobe
(RAS). Nine column address
bits are established on the input pins and latched with the

Column Address Strobe (CAS).
All row addresses must be
stable on or before the falling
edge of RAS. CAS is internally
inhibited (or "gated") b1Bt\S
to permit triggering of CAS as
soon as the Row Address
Hold/Time (t RAH ) specification
has been satisfied and the address inputs have been changed from row addresses to column addresses.
Write Enable
The read or write mode is
selected with the Vi input. A
logic "high" on Vi dictates
read mode. A logic "low" dictates write mode. The data input is disabled when the read
mode is selected.
Data Input
Data is written into the
MB81256 during a write or
read-write cycle. The last failing edge of Vi or CAS is a
strobe for the data-in (D)
register. In a write cycle, if Vi
is brougt1L"low" (write mode)
before CAS, 0 is strobed by
CAS, and the set·up and hold
times are referenced to CAS. In
a read-write cycle, Vi will be
delayed until CAS has made
its negative transition. Thus 0
is strobed by Vi, and set-up
and hold times are referenced
tow.
Data Output
The output buffer is three-state
TIL compatible with a fan-out
of two standard TIL loads.
Data out is the same polarity
as data in. The output is in a
!!!.II!! impedance state until
CAS is brought "low". In a
read cycle, or a read-write cycle, the output is valid after
tRAC from transition of RAS
when tRCO(maX) is satisfied, or
after tCAC from transition of
CAS when the transition occurs after tRCO(ma~ata remains valid until CAS is returned to "high". In a write cycle,
the identical sequence occurs,
but data is not valid.
Page Mode
Page mode operation permits
strobing the row address into
the MB81256 while maintaining
RAS at a logic low (0) throughout all successive memory
operations in which the row

FUJITSU
1-22

address doesn't change. Thus,
the power dissipated by the
negative going edge of RAS is
saved. Access and cycle times
are decreased because the
time normally required to
strobe a new row address is
eliminated.
RAS-Only Refresh
Refresh of dynamic memory
cells is accomplished by performing a memory cycle at
each of the 256 row·adresses
(&c- A7) at least every 4 ms.
RAS-only refresh avoids any
output during refresh because
the output buffer is in th~h
impedance state unless CAS is
brought "low". Strobing each
of the 256 row-addresses
(Ao - A7) with RAS will cause
all bits in each row to be
refreshed. RAS-only refresh
results in a substantial reduction in power diSSipation.
CAS·before·RAS Refresh
CAS·before·RAS refreshing
available on the MB81256 of·
fers an alternate refresh
method. If CAS is held "low"
for the ~cified period (t FCS)
before RAS goes to "low", onchip refresh control clock
generators and the refresh ad·
dress counter are enabled, and
an internal refresh operation
takes place. After the refresh
operation is performed, the
refresh address counter is
automatically incremented in
preparation for the next CASbefore·RAS refresh operation.
Hidden Refresh
A hidden refresh cycle may
take place while maintaining
the latest valid data at the out·
put by extending the CAS ac·
tive time. For the MB81256, a
hidden refresh cycle is a CASbefore·RAS refresh cycle. The
internal refresh address
counter provides the refresh
addresses as in a normal CAS·
before-RAS refresh cycle.
CAS·befora-RAS Refresh
Counter Test Cycle
A special timing se~ce us·
ing the CAS·before·RAS
counter test cycle provides a
convenient method of v~ing
the functionality of the CAS·
before-RAS refresh activated
circuitry.

MB81256·10
MB81256·12
MB81256·15

Description
(Continued)

After the CAS·before·RAS
refresh operation, if CAS goes
to "high" and then~s to
"low" again while RAS is held
"low", the read and write
operation are enabled.

Suggested CAS·belore·RAS
Counter Test Procedure
The timing, as shown in the
CAS·before·RAS Counter Test
Cycle, is used for all the
following operations:

This is shown in the CAS·
before·RAS counter test cycle
timing diagram. A memory cell
can be addressed with 9 row
address bits and 9 column ad·
dress bits defined as follows:

Current Waveforms (Vee
R'AS/CAS CYCLE
RAS ~
CAS

§.
0
0

40

5.5V, TA

= 25"C)
RAS ONLY REFRESH CYCLE

PAGE MODE CYCLE

r

r-- .r- r'-- V -

1\
\

120
80

(5). Complement the test pat·
tern and repeat steps (2), (3)
and (4).

(2). Write a test pattern of
"Iow"s into memory cells at a
single column address and 256
row address.

HIDDEN REFRESH CYCLE

160

"

=

(4). Read the "high"s written at
the last operation (Step 3).

(1). Initialize the internal
refresh counter. For this opera·
tion, 8 cycles are required.

A ROW ADDRESS
Bits AD through A7 are defined
by the refresh counter. The
other bit As is set "high" inter·
nally.

Typical Characteristics
Curves

(3). Using a read·modify·write
cycle, read the "low" written at
the last operation (Step 2) and
write a new "high" in the same
cycle. This cycle is repeated
256 times, and "high"s are
written into the 256 memory
cells.

A COLUMN ADDRESS
All the bits AD through As are
defined by latching levels on
AD through As at the second
falling edge of CAS.

1A..~
~ \ \. I-J

f\
\
I\t

\.."

V

A

I

\

\..'J

\.J -V \... l.J

\

1111 ~

'"1"-

'-

50 ns!DIVISION

Normalized Access time
vs. Supply Voltage

TA l25'C

w

lE

1.1



u

ia:i
u.

w

a:

ii

JJ

TA. AMBIENT TEMPERATURE ('c)

_ TA
vee'==25'C
S.5V

100

30

20
10

/

V

.. V
1
litRe. CYCLE RATE (MHz)

MB81256-10
MB81256·12
MB81256·15

Typical Characteristics
Curves
(Continued)

Page Mode Current
vs. Cycle Rate

Refresh Current 1
vs. Supply Voltage
80

60

70 f-TO J25"C
tAC

C

S.

~
il
II:
II:

= 200 ns

1

60

II:

~

40

"w

30

_ vcc L5.5V
T. = 25"C

t-

U

50

V

./

40

0

i-""

0
:I

w

~

,../'

W

II:

.e

50

II:
II:

:c

.f3

C

S.

j

30

20

10

V

,/

V

V

20
5.0

4.0

10

6.0
l/toe. CYCLE RATE (MHz)

Vee. SUPPLY VOLTAGE (V)

Refresh Current 2
vs. Cycle Rate

Page Mode Current
vs. Supply Voltage
60

!

50

tpc
TA

60

t

= 100 ns
= 25°C

C

40

"uw

30

II:
II:

0

I-- I--

0
:I

w

c$

2

20

----

10

4.0

5.0

N

!zw

40

":cu

30

.f3
II:

20

j

10

II:
II:

W

II:

/
.; V

Address and Data Input Voltage
vs. Supply Voltage
3.0
To

70

tRC

= 200 ns

":c

I!

::!
lil5>
c-

&0

./

50

..

V

f3II:

w 40
II:

~

2

V

=25"C

1

II:
II:

u

,/

l/tRe. CYCLE RATE (MHz)

80

_To J25"C

1/

6.0

Refresh Current 2
vs. Supply Voltage

~
!zw

= 5.5V

V

Vee. SUPPLY VOLTAGE (V)

C

I

TA = 25°C

S.

!zw

~

50 _Vee

VOtt!JN.)

2.0

m~

!!ig
0>

./

~~

1.0

t:::-

t--V
~

VOL(NAX.)

10-"

-

l-

~:!

?i

30

~

20
4.0

5.0

6.0

Vee. SUPPLY VOLTAGE (V)

1·25

4.0

5.0

Vee. SUPPLY VOLTAGE (V)

&.0

MB81256-10
MB81256-12
MB81258·15

Typical Charact.....tlc.
Curve.
(Continued)

HAl, CiS and W Input Voltage
v •• Supply Voltage

Addre•• and Data Input Voltage
v •• Ambient Temperature
3.0

i!;

Vee

::!
li!>
c"'w
",,,

3.0

~ 5.0V

TA = 25°C

2.0

~~

Co
c>

zs
c_

I

~5

~o
0:>

V,L(MAX.)

Z

c

~~
>0.
ci!l

1.0

,.

--

2.0

~~
.~

.L

,.0.
ci!l
~

--

VIH!J,N.)

~
C

VIlt{r'N.)

V,L(·AX.)
1.0

cz

,.
~

-20

20

40

60

80

4.0

100

RAS, CAS and W Input Voltage
v •• Ambient Temperature
3.0
Vee
I~

Acce•• Time
V •• Load Capacitance

~ 5.0V
20

c

~~

15~

S

w
::E
I"

!:i
~g

'"fa

~~

>0.

CZ

,:

1.0

20
40
60
80
T A, AMBIENT TEMPERATURE ("C)

TA = 25°C
250

V

1200
j

~

!5150

u

~

50

/

-- - -

V

-5

100

100

200

300

400

~r--

-

Vee = 5.SV

...

Vee = 4.5V-

TA = 25°C

-125

C"

!.

!Z

il!u§

"o~
-

/

-100

-75

-50

j
-25

VOL, OUTPUT VOLTAGE

M

1·26

""'\

~ee=5.5V

Vee - 4.SV

\

1\\
'\

0

r-

500

CL, LOAD CAPACITANCE (pF)

Output Current
v •• Output Voltage

V

5
100

10

..,j

Output Current
v •• Output Voltage

e:

15

U
U
C

VIL(MAX.)

-20

6

J

Vee 4.5V
TA = 25°C

1i'
VIlt{MIN.)

2.0

1c6

zc

6.0

5.0

Vee, SUPPLY VOLTAGE M

TA, AMBIENT TEMPERATURE rC)

4

VOlt, OUTPlIT VOLTAGE (V)

MB81256·10
MB81256·12
MB81256·15

Typical Characteristics
Curves

Current Waveform During Power Up

Substrate Voltage During Power Up

(Continued)
~>'
o.w

:1711111

0.-

='~~"

80

»

~

f-TA = 25'C

15

~l

RA

/

::>w
.0:

u::>

.l!u

jr

w

-2

li;w
~~

-3

~:E

RAS -

CAS

Vee orVIH-

\

1

= Vss

/

10

0.1-

o.Z

u>o:

= CA

Iii~

:

= 25°C

"

U>:oJ

50/Ls/Division

TA

-4

~

50 ,us/Division

Package Dimensions
Dimensions in inches
(millimeters)

16·Lead Ceramic (Melal Seall Dualln·Line Package
(Case No.: DIP.16C·A031

,~~[~::: :~]]j~
.
I..

.760(19.30)
.800(20.32)

.290(7.37)

.31

I

Jj

U

.200(5.08)MAX

.020( .51)
.043(1.10)

1-27

.120(3.05)
.150(3.81)

=k=i==>

MB81256-10
MB81256-12
MB81256-15

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

16·Lead Seam Weld DIP Package

l

ICase No.: DIP.16C·A04J

.-~
TVP

""~

INDEX AREA'\...,

] 1 j~

t\
.290(7.37)
'

-

•I

.760(19.30)
.800(20.32)

_-",1- .. -..

-

31

T.87)

~
.012(0.30)

16 Lead Plastic Zlg.Zag In-Line Package
ZIP.16P·M01
0.785(19.95)
0.813(20.85)

~I

~

t

0.250(6.35)
0.270(6.85)

~O-~IN~D~mnnnnm~~~~

f

0.350(8.90)

MAX

+-

0.008(0.20)
0.012(0.30)

0.102(2.60) MIN

_t_

j I~

~I

0.024(0.60)

16·Lead Plastic Dual In·Llne Package
DIP·16p·M03

::~:l::::: :Jj=
I

.748(19.01~

.776(19.7)

rv', r=::::;+-seATING

FUJITSU
1-28

PLANE

I.

0.100(2.54) TYP

MB81266·10
MB81256·12
MB81256-15

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

16-Pad Ceramic Leadless Chip Carrier
LCC·18C·F04
'PIN NQ 1 INDEX

j

n
.485(12.32)
.500(12.70)

TOP

VIEW

.145(3.88)
TVP

LJ"--+-";>I'-";>'--k'"--";>4--'i

0,"5(2.112)0"

.280(7.11)

.2I15(7A9)

'SHAPE OF PIN 1 INDEX SUBJECT TO CHANGE WITHOUT NOTICE

18·Lead Pla.tlc Chip Carrier
LCC·18P·M02

ni

.317(8.05)
.327(8.31)

~

.020(0.51) min.

-~--j

~: ~~

"'I" "'I'"
iiU

Ij

.288(7.32)

.132(3.35)
.140(3.55)
.080(1.52) min.

~I

.150(3.81)

o

-I-1
.

.030(0.76) typo

1-29

FUJITSU

MOS Memories
•

MB81257-10, MB81257-12, MB81257-15
NMOS 262,144·Bit Dynamic
Random Access Memory
With Nibble Mode

Description
The Fujitsu MB81257 is a fully decoded, dynamic NMOS random
access memory organized as 262,144 one-bit words. The design is
optimized for high speed, high performance applications such as
mainframe memory, buffer memory, peripheral storage and environments where low power dissipation and compact layout are
required.
The MB81257 features "nibble mode" which allows high speed
serial access of up to four bits of data. Additionally, the MB81257
offers new functional enhancements that make it more versatile
than previous dynamic RAMs. "CAS-before-RAS" refresh provides
an on-chip refresh capability that is an upward compatible version
of the MB8266A. Multiplexed row and column address inputs permit the MB81257 to be housed in a Jedec standard 16-pin dual inIi ne package and 18-pad LCC.
The MB81257 is fabricated using silicon gate NMOS and Fujitsu's
advanced Triple-layer Polysilicon process. This process, coupled
with single transistor memory storage cells, permits maximum circuit density and minimal chip size. Dynamic circuitry is used in the
design, including dynamic sense amplifiers.
Clock timing requirements are noncritical, and the power supply
tolerance is very wide. All inputs are TIL compatible.

Features

••
•
•
•
•
•
•

262,144 x 1-bit organization
Row Access Time/Cycle Time:
MB81257·10 100 ns Maxi
200 ns Min.
MB81257·12 120 ns Maxi
220 ns Min.
MB81257·15 150 ns Maxi
260 ns Min.
Low Power Dissipation:
314 mW max. (t RC = 260 ns)
25 mW (Standby)
+5V supply voltage,
±10% tolerance
All inputs TTL compatible, low
capacitive load
Three·state TIL compatible
output
Common I/O capability using
"Early Write" operation
On·chip substrate bias
generator

•
•
••
•
••
•
•
•

Nibble mode capability for
faster access
Fast Read·Write Cycle,
TRWC=TRC
~WCR' tD~WD eliminated
A ·before·
on chip
refresh
Hidden CAS before·RAS on·
~refresh

·only refresh
Refresh 4 ms/256 cycles
Output unlatched at cycle end
allows two dimensional chip
select
On·chip Address and Data·in
latches
Industry standard 16-pin
package

1-30

MB81257·10
MB81257·12
MB81257·15

MB81257 Block Diagram
and Pin Assignments

Vi

Vi

Q

RAlI

As

N.C.

N.C.

A,

A,

A,

A.

Q

A,

262,144.BIT
STORAGE CELL

Vee

A,

As

V __

"",-Vcc

D

"As

CAS

18

""'-VSS

17

V__
(

LEAO#1

W 3

AS

"-A6 CAS A8

Vi

Ao

A,

A7

A4

~
Vss 0 RAS A2 Vee As Aj,
Q

D

CAS

W

Q

lIAS

As

A.

A,

A2

A4

A,

As

Vee

A,

16.../

ZIP·16P.M01
BOTTOM VIEW

16

Q

15

A.

,.

N.C.

6

13

A,

7

12

A4

lIAS

•

N.C.

5

A.
A2

• AS (Pin 1) is assigned for
nibble (4-bit) address
NOTE: The following IEEE Std. 662-1980 symbols are used in this data sheet: 0

Absolute Maximum Ratings
(See Note)

LCC-18C-F04
TOP VIEW

A,

Vee

10

11

A,

As

= Data In, W= Write Enable, a = Data Out.

Rating

Symbol

Value

Unit

Voltage on Any Pin relative to VSS

V,N• VOUT• Vee

-1.0 to 7.0

V

Operating Temperature (ambient)

Top

Oto 70
-55 to +150
55 to +125
1.0
50

·C

Storage Temperature

Ceramic
Plastic

TSTG

Power Dissipation
Short Circuit Output Current

Po
los

·C

W
rnA

NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed In the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields. However, It Is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this high Impedance circuit.

R_mmended Operating
Conditions
(Referenced to Vssl

Parameter

Symbol

Value
Min
TyP

Max

Unit

Supply Voltage

Vcr.

4.5

5.0

5.5

V

Vss

0

0

0

rJ

Input High Voltage All Inputs
Input Low Voltage All Inputs

V,H
V,L

2.4
-2.0

6.5
0.6

V
V

FUJITSU
1-31

Operating Temperature
O'C to + 70·C ambient

M881257·10
M881257.12
M881257.15

Capacltanc.
(TA=25°C)
Parameter
Input Capacitance

DC Characterlatlca
(Recommended operating
conditions unless otherwise
noted.)

Valu.
Min

Symbol

Ao to As, D

Input Capacitance RAS, CAS and W

C IN1
C IN2

Output Capacitance Q

COUT

Typ

Max

Unit

7

pF

10
7

pF
pF

M881257·10 M8812&7·12 M8812&7·15
Symbol Min
Max Min
Max Min
Max Unit

Parameter
OPERATING CURRENT'1
Average Power Supply Current
(RAS, CAS cycling; I RC = Min.)

Icc1

70

65

57

mA

STANDBY CURRENT
Power Supply Current
(RAS/CAS = V IH)

Icc2

4.5

4.5

4.5

mA

REFRESH CURRENT 1'1
Average Power Supply current
Icc3
(RAS cycling, CAS = VIH ; tRC = Min.)

60

55

50

mA

NIBBLE MODE CURRENr 1
Average Power Supply current
Icc4
(RAS = Vll' CAS cycling; tNC = Min.)

22

20

18

mA

REFRESH CURRENT 2'1
Average Power Supply Current
(CAS before RAS; t RC = Min.)

65

60

55

mA

Icc5

INPUT LEAKAGE CURRENT
Any Input, (VIN = OV to 5.5V,
Vcc= 5.5V, Vss=OV,
all other pins not under test = OV)

III

OUTPUT LEAKAGE CURRENT
(Data is disabled, VOUT=OV to 5.5V) 10l
OUTPUT LEVEL
Output Low Voltage
(Iol = 4.2 mAl
OUTPUT LEVEL
Output High Voltage
(loH = - 5.0 mAl

-10

10

-10

10

-10

10

pA

-10

10

-10

10

-10

10

pA

0.4

V

0.4

VOL

VOH

2.4

0.4

2.4

2.4

Note: *1 ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

FUJITSU

1·32

V

MB81257·10
MB81257·12
MB81257·15

AC Characterlstlcs'l,2,3
(Recommended operating
conditions unless otherwise
noted,)
Parameter

Notss

Symbol
Alternate

Time between Refresh
Random ReadIWrite Cycle Time
Read-Write Cycle Time

tREF
t RC
t RWC

Access Time from RAS'4,6
Access Time from CAS'5,6
Output Buffer Turn off Delay
Transition Time
RAS Precharge Time
RAS Pulse Width
RA§ Hold Time
CAS Pulse Width
CAS Hold Time
RAS to CAS Delay Time'4,7
CAS to RAS Set Up Time
Row Address Set Up Time
Row Address Hold Time
Column Address Set Up Time
Column Address Hold Time
Read Command Set Up Time
Read Command Hold Time Referenced to CAS'10
Read Command Hold Time Referenced to RAS'10
Write Command Set Up Time's
Write Command Pulse Width
Write Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data In Set Up Time
Data In Hold Time
~ to iN Delay'S
Refresh Set Up Time for CAS Referenced to RAS
Refresh Hold Time for CAS Referenced to RAS

tRAC
t CAC
tOFF
tT
t RP
t RAS
t RSH
tCAS
tCSH
tRCO
tCRS
tASR
tRAH
t ASC
tCAH
t RCS
tRCH
tRRH
twcs
twp
t WCH
t RWL
tCWL
tos
tOH
t cwo
t FCS
t FCH

Not..:

• Standard

TRVRV
TRELREL
TRELREL
TRELQV
TCELQV
TCEHQZ
IT
TREHREL
TRELREH
TCELREH
TCELCEH
TRELCEH
TRELCEL
TCEHREL
TAVREL
TRELAX
TAVCEL
TCELAX
TWHCEL
TCEHWX
TREHWX
TWLCEL
TWLWH
TCELWH
TWLREH
TWLCEH
TDVCEL
TCELDX
TCELWL
TCELREL
TRELCEX

M881287·10 MB81287.12 MB81287·18
Min Max
Min Max
Min
Max

4
200
200

0
3
85
105
55
55
105
20
10
0
10
0
15
0
0
20
0
15
15
35
20
0
15
15
20
20

100000
100000
50

0
3
90
120
60
60
120
22
10
0
12
0
20
0
0
20
0
20
20
40
30
0
20
20
20
25

*These symbols are described In IEEE STD. 682-1980: IEEE Standard terminology for semiconductor memory.
*1 An initial pause of 200#,8 Is required after power up, followed by.!!!y 8 RAS ~es, before proper device operation is achieved.
If the internal refresh counter is to be effective, a minimum of 8 CAS before RAS refresh Initialization cycles are required.
*2 AC characteristics assume IT = 5ns.
~3 VIH (Min.) and VIL (Max.) are reference levels for measuring timing of Input signals. Also transition times are measured between
VIH and VIL·
*4

!=gg ~ ~~~;~:tt~:~~:~ raoii~~r~::~ ~~1~e ~~~~~ ~~a~~~~~ :=:de:t;~~(~~)(~~lue of tAAC (Max.) can be met. If

*5 Assumes that tACO> tACO (Max.).
*6 Measured with a load equivalent to 2 TTL loads and 100pF.

'7 'RCO (Min.)
*8

~

'RAH (Min.) + 2tT + 'ASC (Min.).

!~g~ ~n~~~~?M%~)~~hn:eCs~~I~irseaOt:~~~n~:~~:'~~~~~ea~~:~~~ni~~I~~::ns~;:~ ~~r:~:~~:~ ~~~::~~:;c::,~~~'h~ut
the entire cycle.
If tCWD > tCWD (Min.), the cycle is a read-write cycle and data out will contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of the data out Is indeterminate.

*10 Either tRCH or tRRH must be satisfied for a read cycle.

FUJITSU
1·33

260
260

220
220
100
50
25
50

4

4

120
60
25
50
100000
100000
60

0
3
100
150
75
75
150
25
10
0
15
0
25
0
0
20
0
25
25
45
35
0
25
25
20
30

150
75
30
50
100000
100000
75

Unit

ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

MB81257.10
MB81257·12
MB81257·15

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)
Parameter

Notes

Nibble Mode Read-Write Cycle Time
Nibble Mode ReadlWrlte Cycle Time
Nibble Mode Access Time
Nibble Mode CAS Pulse Width
Nibble Mode CAS Precharge Time
Nibble Mode Read RAS Hold Time
Nibble Mode CAS Hold Time Referenced to
Nibble Mode Write RAS Hold Time
Refresh Counter Test Cycle Time g
Refresh Counter Test ~ Precharge Time-g
Refresh Counter Test RAS Pulse Widlh"g
RAS Precharge to ~ Active Time
CAS Precharge Time for CAS before
RAS Refresh Cycle
Notes:

MB81257·10
Min Mall

MB81257·12 MB81257·15
Min Mall
Min
Mall

45

50

60

45

50

60

tNRRSH
tRNH
tNWRSH
t ATC
tCPT
t TRAS
t RPC

TCEHCEH
TCEHCEH
TCELQV
TCELCEH
TCEHCEL
TCELREH
TREHCEL
TCELREH
TRELREL
TCEHCEL
TRELREH
TREHCEL

t CPR

TCEHCEL

20

Symbol
Alternate

t NRWC
t NC
t NCAC
t NCAS
t NCP

RAS

• Standard

20
20
15
20
20
35
330
50
230
20

25
25
15
25

20
40

10000

375
60
265
20
25

10000

30
30
20
30
20
45
430
70
320
20

10000

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

30

*9 Test mode cycle only.

Timing Diagrams
Read Cycle
I~·~-------------------IRC--------------------~
VIH
RAS
VIL

VIH
CAS

--.....,.t. I~~----------- RAs-------------_U,..-------:>l..
I~-~----~-----ICSH---------r+~

~~~-----~~\~I~~~------~------I-RS-H~I-C-AS--------~~+_~~---~

VIL

A

w

Q

IZZI

FUJITSU
1-34

Don't Care

MB81257·10
MB81257·12
MB81257·15

Timing Diagrams
(Conti nued)

Write Cycle (Early Write,
I··.--------------------IRC--------------------~I

I---------------IRAS - - - - - - - - - - - - - -__

V,H

1

Jo-----"L

RAS
V,L

I....----------c-----ICSH - - - - - - - - - -.. 1

,...,.....,....,j.-+-+-_ _ _ _~ ,r----------IRSH.~--_:-t;..--r-------___...

V,H
CAS
V,L

A

V,H
V,L

__ ," It

W

0

VIL

V ,H

mxxx~

V IL

a

wcs

xm~E~~

V,H

f'M"',..."x"'x"x-.,.,-x-,.,-xxxx.,.,..."...,,....,,xx~xx~xx~

VALID DATA

VO H
- - - - - - - - - - - - - - HIGH-Z - - - - - - - - - - - - - - - - - -

VOL

~

Don't Care

Read·WrltelRead.Modlfy.Wrlte Cycle

V,H - - - - - , " RAS

1--.--------------

V,L

CAS

V,H .........,..l-~==~~r:::::1~1----V,L

A

Vi

V,H

=A7"'"""'~7n"'±_-~--.:..------:L

V,L C::L~l:oJ.~£::,L~.lY

a

VOHI VOL

~~==={=5~~VALID DATA

,Iosl
~

o

::~ XXXXXXXXXXXXXXXXXXXXX~

L

~
"""'XX""""XX"""'X""""XX"""""XX"""""X

tDH--+-

VALID DATA

~

FUJITSU

1-35

Don'tCare

MB8t257·t0
MB8t257·t2
MB8t257·t5

Timing Diagrams
(Continued)

uBl-Onl," Refr.. h C,e'e
Note: W, IN

= Don't Care, Aa = V ,H or V,l
I+---------IRC---------I~

t - - - - I ".. -----i~
V,H
V,L

ADDRESS

(Ao to A7)

VIH
V,L

V,H
V,L

Q

VOH
VOL

~Don'tcare

Hidden R.fr.sh C,e'.

RAS

V,H
V,l

CAS

V,H
V,L

A

V,H
V,L

W (Road)

V,H
V,L

Q

VOL
V,H
W (Read·W,'te)

V,L

FUJITSU

1-36

MB81257·10
MB81257·12
MB81257·15

Timing Diagrams
(Continued)

"CAS·Before·RAS" Refresh Cycle
NOTE: Address, W, D = Don't Care

•

IRC

~tRP-----'

-IRAS-1

RAS

-::: =3~tOFF'---¥
tCPR

CAS

I~

tFCH

Il-tRPc

V1H

Q

------------HIGH-Z------------VIL

rzZl

Don't Care

Nibble Mode Read Cycle

VIH ~--..frT";----1
VIL

A

w

VIH~~~7\,~r_r_------~v9~---~7VV_----~~~---_+--_i~~
VILi.:lI.=WL'"'-l"
VOH

Q

VOL--------------~~~~

lZ2QI Don't Care

FUJITSU
1-37

MB81257·10
MB81257·12
MB81257.15

Timing Diagrams
(Continued)

Nibble Mode Write Cycle

RAS

CAS

V,H
V,l

V,H
V,l

V,H
A

W

V,l
V,H
V,l

VOH
Q

VOL
V,H
0

V,l

~Don'tCar.
Nibble Mode Read·Wrlte Cycle

V,H D<:7-7-';---,l.

v"

w
Q

o
~DON'TCARE

FUJITSU
1-38

MB81257·10
MB81257·12
MB81257·15

Timing Diagrams
(Continued)

"CAS·Before·RAS" Refresh Counter Test Cycle
~------------------------IRT·C---------------------~

RAS

V'H

•

I----------------TRAs'----------------.-I ~---_.j.

V'L
~------IRSH'-----~~

CAS

V'H

1'-~-----ICAS----~.,,1

V'L
V'H
A

V'L
V'H
W (Read)

V'L

?\XXXXXl\X.XXXX

VOH
Q

VOL

V'H
W(Wrile)
V'L
V'H
D

V'L

00

FUJITSU

1-39

DON'T CARE

MB81257·10
MB81257·12
MB81257·15

De.orlptlon
Simplified Timing Requirement
The MB81257 has Improved circuitry that eases tlmlngrequlrements for high speed access operatlons_ The MB81257
can operate under the condition
of tRCo (max) t CAC' thus providing optimal timing for address multiplexing. In addition,
the MB81257 has minimal hold
times for Addresses (tCAH),
Write-Enable (tWCH) and Data-In
(tow. The MB81257 provides
higher throughput in Interleaved memory system applications. Fujitsu has made the timIng requirements that are referenced to RA§ non-restrictive
and deleted them from the data
sheet. These Include tAR, twcR,
tOHR and tRW?' As a result, the
hold times 0 the Column Address, 0 and Was well as tcwo
(CAS to W Delay) are not
restricted by tRCD'

=

Fast Read-WrHe Cycle
The MB81257 has a fast readmodify-write cycle which Is
achieved by precise control of
the three-state output buffer as
well as by the simplified timIngs described In the previous
section. The output buffer Is
controlled by the state of W
when CAS goes "low". When W
Is "low" during a ~ transition
to "low", the MB81257 goes into the early write mode in which
the output floats and the common 1/0 bus can be used on the
system level. When W goes
"low", after tcwo following a
CAS transition to "low", the
MB81257 goes Into the delayed
write mode. The output then
contains the data from the cell
selected and the data from 0 Is
written Into the cell selected.
Therefore, a very fast read-write
cycle (tRWC = tROlls possible
with the MB81257.

address bits are required to
decode any 1 of 262,144 cell
locations within the MB81257.
Nine row address bits are
established on the input pins
(Ao through A~ and are latched
with the Row Address Strobe
(RAS). Nine column address
bits are established on the Input pins and latched with the
Column Address Strobe (CAS).
All input addresses must be
stable on or before the failing
edge of RA§. eAS' Is Internally
Inhibited (or "gated") by RAS to
permit triggering of ~ as
soon as the Row Address
HoldlTlme (t RAH) specification
has been satisfied and the address inputs have been changed from row addresses to column addresses.
Write Enable
The read or write mode Is
selected with the W Input. A
logic "high" on W dictates read
mode. A logic "low" dictates
write mode. The data input Is
disabled when the read mode Is
selected.
Data Input
Data is written Into the
MB81257 during a write or readwrite cycle. The last falling
edge of Vi or CAS Is a strobe
for the Data-lnJ.D) register. In a
write cycle, If W Is brought
"low" (write mode) before CAS,
o Is strobed by CAS, and the
set-up and hold times are
referenced to ~. In a readwrite ~e, W will be delayed
until ~ has made Its negative
transition. Thus 0 Is strobed by
W, and set-up and hold times
are referenced to W.

Addre88 Inputs
A total of eighteen binary Input

Table 1
Nibble Mode Add....s
Sequenoe Example

Sequenoe
RASICAS (normal mode)
toggle CAS (nibble mode)
toggle CAS (nibble mode)
toggle CAS (nibble mode)
toggle CAS (nibble mode)

Data Output
The output buffer Is three-state
TTL compatible with a fan-out
of two standard TTL loads.
Data out Is the same polarity as
data In. The output Is In a high

Impedance state until CAS Is
brought "low". In a read cycle,
or a read-write cycle, the output
is valid after t RAC from transition of RA§ when tRCOlmax) Is
satisfied, or after tCAC from
transition of CAS when the
transition occurs after tRQQJmax)'
Data remains valid until CAS Is
returned to "high". In a write
cycle, the Identical sequence
occurs, but data is not valid.
Nlbbla Moda
Nibble mode allows high speed
serial read, write or readmodify-write access of 2, 3 or 4
bits of data. The bits of data
that may be accessed during
nibble mode are determined by
the 8 row addresses and the 8
column addresses. The 2 bits of
addresses (CAe, R~ are used
to select 1 of the 4 nibble bits
for Initial access_ After the flret
bit Is accessed by the normal
mode, the remaining nibble bits
~ be accessed by toggling
~ "high" then "low" while
!!lAS remains "low". Toggling
CAS causes RAe and CAe to be
Incremented Internally while all
other address bits are held constant and makes the next nibble bit available for access.
(See table I belOW).
If more than 4 bits are accessed during nibble mode, the address sequence will begin to
repeat. If any bit Is written durIng nibble mode, the new data
will be read on any subsequent
access. If the write operation Is
executed again on subsequent
access, the new data will be
written Into the selected cell
location.
In nibble mode, the three-state
control of the DOUT pin Is determined by the flret normal access cycle.
The data output Is controlled

Nibble
Bit

RAI

Row Addre.a C~ Column Add..- Comments

1
2
3
4

0
1
0
1

10101010
10101010
10101010
10101010
10101010

0

FUJITSU
1·40

0
0

0

10101010
10101010
10101010
10101010
10101010

Input addresses
generated internally
sequence repeats

MB81257·10
MB81257·12
MB81257·15

D ••orlptlon
(Continued)

only b~ W state referenced
at the CAS negative transition
of the normal cycle (first nibble
bit). That Is, when
t wcs > twcs(mln.) Is met, the
data output will remain in the
high-impedance state throughout
the succeeding nibble cycle regardless of the Vi state. When
t ewD > tcwD(mln.) Is met, the
data output will contain data
from the cell selected during
the succeeding nibble cycle
regardless of the W state. The
write operation Is done during
~erlod In which the Wand
CAS' clocks are low. Therefore,
the write operation can be performed bit by bit during each
nibble operation regardless of
the timing conditions ofW
(twcs and tcwel during the
normal cycle (first nibble bit).
(See table 2 and Figure 1 below).
iiA&Only Refresh
Refresh of dynamic memory
celis Is accomplished by performing a memory cycle at each
of the 256 row-adresses
(An - A7) at least every 4 ms.
RASonly refresh avoids any
output during refresh because
the output buffer Is in th~h
Impedance state unless CAS Is
brought "low". Strobing each of
the 256 row-addresses (Ae - A7)
with RAS will cause all bits In
each row to be refreshed. RASonly refresh results In a
substantial reduction In power
dissipation.
CAS-before-AD Refresh
CAS-befora-RAS refreshing
available on the MB81257 offers
an alternate refresh method. If
CAS Is held "low" for the
~Ifled period (tFcsl before
RAS goes to "low", on-chip
refresh control clock generators
and the refresh address counter
are enabled, and an Internal
refresh operation takes place.

FUJITSU
1-41

After the refresh operation Is
performed, the refresh address
counter Is automatically Incremented In preparation for
the next CAS-before-RAS
refresh operation.

Suggested CAS·before·RAS
Counter Test Procedure
The timing, as shown In the
CAS·before·RAS Counter Test
Cycle, is used for all the follow·
ing operations:

Hidden Refresh
A hidden refresh cycle may
take place while maintaining
the latest valid data at the output by extending the CAS active time. For the MB81257 a
hidden refresh cycle Is a ~
before-FIAS refresh cycle. The
Internal refresh address counter
provides the refresh addresses
as In a normal CAS-before-RAS
refresh cycle.

(1). Initialize the internal refresh
counter. For this operation, 8
cycles are required.

CAs.befo.... RAS Refresh
Counter Test Cycle
A specl&!!!,nlng se~ce usIng the CAS-befora-RAS counter
test cycle provides a convenient
method of verlf~ the functionality of the CAS-before-FIAS
refresh activated circuitry.
After the CAS-befora-RAS
refresh operation, If CAS goes
to "high" and then.JlQ!ls to
"low" again while RAS 15 held
"low", the read and write operation are enabled.
This Is shown In the CASbefore-RAS counter test cycle
timing diagram. A memory celi
can be addressed with 9 row
address bits and 9 column address bits defined as follows:
A ROW ADDRESS
Bits Ae through A7 are defined
by the refresh counter. The
other bit As Is set "high" Inter·
nally.
A COLUMN ADDRESS
All the bits Ao through As are
defined by latching levels on Ao
through As at the second failing
edge of CAS.

(2). Write a test pattern of
"Iow"s into memory cells at a
single column address and 256
row address.
(3). Using a read-modlfy·write
cycle, read the "low" written at
the last operation (Step (2» and
write a new "high" In the same
cycle. This cycle is repeated
256 times, and "hlgh"s are writ·
ten into the 256 memory cells.

(4). Read the "hlgh"s written at
the last operation (Step 3).
(5). Complement the test pattern and repeat steps (2), (3) and
(4).

MB81257·10
MB81257·12
MB81257·15

Figure 1
Nibble Mode

1) In this case the first nibble cycle is an Early Write cycle.

RAS

~~__________________________________~;---

WE~

/

~~________________~_____________

D
Q

\

=::)>------------- H i g h · Z - - - - - - - - - - - - - - - -

1-

Early Write

-I~ope~~tion...j- Write _ I - w r i t e - j
(increment
nibble counter)

f2Z2l

Valid Data

2) In this case the first nibble cycle is a delayed write (Read-Write) cycle.
RAS

--..

,--

~~.------------------------------~I

\
D

\~ _ _~I

I

---------~-------------~----------

Q

1_

Read.write-l_Read.write-l_Read_I __ Read.wrlte~

[ZZJ Valid Data
Table 2
Functional Truth Table
RAS

CAS

WE

DIN

DOUT

Read

Write

Refresh

Note

H
L
L

H
L
L

Don't Care
H
L

Don't Care
Don't Care
Valid Data

High·Z
Valid Data
High·Z

No
Yes
No

No
No
Yes

No
Yes
Yes

Standby.
Read.

L

L

L

Valid Data

Valid Data

Yes

Yes

Yes

L

H

Don't Care

Don't Care

High-Z

No

No

Yes

L

L

Don't Care

Don't Care

Valid Data

No

No

Yes

H

L

Don't Care

Don't Care

High·Z

No

No

No

FUJITSU
1-42

Early Write twcs '" twcs (min).
Delayed Write or Read-Write
tewD '" teWD (min).
RAS Only Refresh.
CAS·before-RAS Refresh. Valid
data selected at previous Read
or Read·Write cycle Is held.
CAS disturb.

MB81257·10
MB81257·12
MB81257·15

Typical Characteristics
Curves

=

Current Waveform (Vcc
RAS/CAS CYCLE
RAS
CAS

.§.
u
u

HIDDEN REFRESH CYCLE

RAS-ONLY REFRESH CYCLE

1\

80

A.~

J\ \

-

1\
\

\
ft. l\
'~ V \.

f-J

..J

\J

-vl~\.... J

TAl 25°C

'"
¢

¢

Vee

"" '"

1.1

1.0

'z"

0.9

a:

0

0.8

"''"w"
'"

4.0

""

c

60

50

a:
a:

40

f-

Vee

I=

..

a:
w
0

j

¢

0.9

1

0.8

0

-20

6.0

20

40

60

80

T A, AMBIENT TEMPERATURE (OC)

80

/

S.5V
C

/V

70 _T.J25 C
0

"

tRC

= 200 ns

I
~

.§.

....
z
w

/

30

10

V

:::J

'a:z"

/

/

Operating Current
vs. Supply Voltage

TA ::::: 25 C

60

a:
a:

::>
0

"

/

20

./

1.0

N

'-.

5.0

::>
0

"liz

,;

W

Operating Current
vs. Cycle Rate

....
z
w

A

A.

5.0V

1.1

Vee, SUPPLY VOLTAGE (V)

.§.

I
=;0

0
0

¢

j

"

ltJL~
'V
\

w

iTI

!:j

I"-

1.2

w

i=

\

Normalized Access Time
vs. Ambient Temperature

1.2

0
0

A
\

rf'\-- f-I"

50 ns/DIVISION

Normalized Access Time
vs. Supply Voltage

'"'"w

NIBBLE MOOE CYCLE

f-- .r

120

40

= 25°C)

"""""
- -

160

"

5.5V, TA

50

z

.li

a:
w

/

40

/

V

V

,/

0

u
u

30

20
4.0
1/tRC, CYCLE RATE (MHz)

1-43

5.0
Vee, SUPPLY VOLTAGE (V)

6.0

100

MB8t257·t0
MB8t257·t2
MB8t257·t5

Typical Characteristics
Curves
(Continued)

Standby Current
vs. Supply Voltage

Operating Current
vs. Ambient Temperature

I----'-1-,----r-,----,

8o.-------r

1
ffi

~

ri
Ii
ffi

70 60

~R"c": 2~";,.--+---t--+---l

I-+=~==:t:=::t==t:-l

50
40~-~-~--+---+--+--~

P;

~30I--t--t--t--t--+---f
2OL-_-'--_-'-_-'_ _' - _ - ' - - _ - '
-20
20
40
60
80
100

s.o

4.0

T •• AMBIENT TEMPERATURE Cc)

Standby Current
vs. Ambient Temperature

Nibble Mode Current
vs. Cycle Rate
60

Vee ls.sv
= 2S'C

C

50

Iiw

40

!.

T.

-

r--

0:
0:

"w
a

r--

0
:IE

40

TA = 25°C

30

w
oJ

'"'"

~

20

_~ee ls.sv

U

20

iii

-20

60

80

10

100

-

Refresh Current t
vs. Supply Voltage

!.

80

_!A J25'C

tRe = 200 os

60

Iiw
0:
0:

"U
0:

50

40

W

0:

~

1

50

~0:

40

"u

30

0:

:I:

.I!l

./'

V

~

20

0:

d

!J

30

4.0

16

l

TA

= 25°C

/

V

s.o

6.0

Vee. SUPPLY VOLTAGE (V)

FUJITSU

1·44

10

/

. .V
3
IlIAC. CYCLE RATE (MHz)

f-

20

_ vee = s.sv

m

/"

20

12

Refresh Current t
vs. Cycle Rate

80

70

--8

~ I--

lllHe. CYCLE RATE (MHz)

T •• AMBIENT TEMPERATURE Cc)

C

6.0

Vee. SUPPLY VOLTAGE (V)

MB81257·10
MB81257·12
MB81257·15

Typical Characteristics
Curves
(Continued)

Nibble Mode Current
vs. Supply Voltage

Aefresh Current 2
vs. Cycle Aate

w

wr---,----,---,----,---,----,

C_E-

ffi~
B

i

145

50"- tNe
ns+---i---t---t-----i
I TA = 25°C I

30r--~-_4--+_-_+--~-~

~

Iz 20r-~j:::~::::t:~=r=---~-1
I
]

..ili

40

:>

30

..."'

20

N

4Or--~-_4--+_-_+--~-~

10~--+_--~----j----t---1_--_1
4.0

5.0

50

C-

g
0:
0:

0
:J:

r- Vee
'= 5.5V
TA = 25°C

W

0:

.9

.-V

6.0

2

t/IRe. CYCLE RATE (MHz)

Aefresh Current 2
vs. Supply Voltage

Address and Data Input Voltage
vs. Supply Voltage

80

3.0
TA,

Cz

60

..~
W

r!AL5
C I
tRC = 200 ns

0

:r

..."'0:w

~

i!i
i!>

.. -

w

.,./

40

....--

0:",

....
.~~

/

Co
C>
~:>

~

-- -

V'H(JIN.)
2.0

m~

/

50

0:

.9

= 2S"C

0

0:
0:

:>

,/

to

Vee. SUPPLY VOLTAGE

70

/

W

0:

V

,/'

t.O

~

f-""

V!L(MAX.)
~~

z

30

~

;0

20
4.0

5.0

3.0
Vee

i!i

AAS, CAS and it Input Voltage
vs. Supply Voltage
3.0

~ 5.0V

TA = 25°C

~~

"'w
"'co
~~
eo

2.0

I;:
e

VIH(jIN.)

.-

~w

~S

..,:

e!:

z

1.0

-f----

~~
1~6
0:>

V'L(~AX.)

-

V,HCJIN.)

2.0

z>

e>

;0"

6.0

Vee. SUPPLY VOLTAGE (V)

Address and Data Input Voltage
vs. Ambient Temperature
~

5.0

4.0

6.0

Vee. SUPPLY VOLTAGE (V)

-

f-

VIL(IAX.)

~!; 1.0

> ..
e!:

..,:z
-20

20
40
w
80
TA. AMBIENT TEMPERATURE ("C)

1-45

100

4.0

5.0

Vee. SUPPLY VOLTAGE (V)

6.0

MB81257·10
MB81257·12
MB81257·15

Typical Characteristics
Curves
(Continued)

RAS, CAl and W Input Voltage
vs. Ambient Temperature
3.0
Vee
I~
Q

Access Time
vs. Load Capacitance

~ 5.0V
20

~~

I~~
lui~
:g

!w

V"t{MIN.)

2.0

1=

fa

,;;~

10

-

u

QZ

z-

15

:Ii

en

> ..

..

J

Vee 4.5V
TA = 25°C

~

V,L(MAX.)
1.0

I

~

80
20
40
60
TA, AMBIENT TEMPERATURE ('c)

-20

100

200

300

400

500

CL, LOAD CAPACITANCE (pF)

Output Current
vs. Output Voltage

k:±:::-

= 25°C

/

h

-S

100

Output Current
vs. Output Voltage
TA

~~

~

TA = 25°C
-12S

Vee = 4.5V-

/'

1IE

-100

i
8

-75

w

V

I

I

""'\

l\.vee = S.SV

-50

]

Vee = 4.SV

-25

V

\.

\\
\

0

3
VOL, OUTPUT VOLTAGE (V)

VOH. OUTPUT VOLTAGE (V)

Current Waveform During Power Up

Substrate Voltage During Power Up

n:[1/1 1111 U:I:t'l 1111
.-

»

r-TA = 2S"C

1S

RA

= cAl

/

I

V

-1

= Vss

w
Ie>
t;w
","
~~
·0

-2

= CAS

= Vee or VIH-

~>

50 Ms/Divlslon

'"

'",-

0:_

RAS

\

TA = 25°C

-3

-4
50 p,s/Division

1-46

-

MB81257·10
MB81257·12
MB81257·15

Package Dimensions
Dimensions in inches
(millimeters)

16·Lead Ceramic (Metal Seal) Dual In· Line Package
(Case No.: DIP.16C·A03)

nr

'"~~l~::: :~l]j~
I•

.760(19.30)
.800(20.32)

•

U

.31

I

~
.090(2.29)
.110(2.79)

.290(7.37)

=,===*==

'200(5'08)MAX
.120(3.05)
.150(3.81)

.020(0.51)
.043(1.10)
~--~--~~~~~--~~~

16·Lead Seam Weld DIP Package
(Case No.: DIP·16C·A04)

'"::~~~ ::::~ IH~
I•

.760(19.30)
.800(20.32)

- - - .050(1.27)MAX

1·47

•I

-I2"""i"':-==-~"'''5~1..

0" - 9"

1J

.290(7.37)

......::;~==i==.3101(7.87)

MB81257.10
MB812S7.12
MB81257.15

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

16 Lead Plastic Zlg.Zag In·Llne Package
ZIPo18PoU01

0.785(19.95)
0.813(20.85)

I
•

~

•

!

======i1-r

/~,

0.250(6.35)

II

0--INDEX

0'1(6.85)

~I

I_ 0.104(2.85)
0.120(3.05)

I

0.350(8.80)

L-

0.102(2.80) MIN

.:L..

II_

...j

0.024(0.60)
0.016(0.40)

~I

0.050(1.27) TYP

0.100(2.54) TYP

i8·Lead Plaatlc Dual In·Llne Package
DIP·i8P·M03

'::~::l::::: :J~:
~

.748119.01
.776119.71

FUJITSU
1-48

.1

-'---rJI'====~--rO' - 15'
.290(7.37)
.31017.871

MB81257·10
MB81257·12
MB81257.15

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

18·Pad Ceramic Leadless Chip Carrier
LCC·18C-F04
"PIN NO. 1 INDEX

/

TOP
VIEW

.Zl0{7.11}

.21111(7.49)

fl

.485(12.32)
.£500(12.70)

D'"~"')MAX

"SHAPE Of PIN 1 INDEX SUBJECT TO CHANGE WITHOUT NonCE

18·Lead Plastic Chip Carrier
LCC·18P·M02

-- :~=::::~

.080(1.52) min .
.020(0.51) min.

.150(3.81)

.030(0.78) typo

1-49

FUJITSU

MOS Memories
•

MB81256.12.W, MB81256·15·W
NMOS 262,144-8it Dynamic
Random Access Memory

Description
The Fujitsu MB81256-W is a fully decoded, dynamic NMOS random access memory organized as 262,144 one-bit words. The design is optimized for high speed, high performance applications
such as mainframe memory, buffer memory, peripheral storage
and environments where low power dissipation and compact layout
are required.
The MB81256-W features "page mode" which allows high speed
random access of up to 512-bits within the same row. Additionally,
the MB81256-W offers new functional enhancements that make it
more versatile than previous dynamic RAMs. MuRiplexed row and
column address inputs permit the MB81256-W to be housed in a
Jedec standard 16-pin dual in-line package and 18-pad LGG.
The MB81256-W is fabricated using silicon gate NMOS and
Fujitsu's advanced Triple-layer Polysilicon process. This process,
coupled with single transistor memory storage cells, permits maximum circuit density and minimal chip size. Dynamic circuitry is
used in the design, including dynamic sense amplifiers.
Glock timing requirements are noncritical, and the power supply
to.lerance is very wide. All inputs are TTL compatible.

Features
•

•

•
•

•
•

Wide temperature range:
Tc = -55·C to +110·C
262.144 x 1-blt organization
Row Access Time/Cycle Time:
MB81256-12-W
120 ns msx_/250 ns min.
MB81258-15-W
150 ns max_/280 ns min.
• Page cycle time
MB81256-12-W120 ns max_
MB81256-15-W 150 ns max.
• Low Power Dissipation:
347 mW max. (tRC
280 ns)
33 mW (Standby)
• +5V supply voltage.
±10% tolerance
• All Inputs TTL compatible.
low capacitive load
• Three-state TTL compatible

=

output
•

On-chip substrate bias
generator
Page Mode Capability
Fast Read-Write Cycle.

t RWC = ~c
tAR' t WCR' t OHR ' t RwO
eliminated
CAS-before-RAS on chip

•
•

rafreah
•
•
•
•

•
•

Hidden CAS-before-RAS
on-chip refresh
RAS-only refresh
2 ms/256 cycle refresh
Output unlatched at cycle
end allows two dimensional
chip select
On-chip Address and
Data-In latches
Industry standard 16-pln
package

Common I/O capability
using "Early Write" operation

1-50

MB81256·12.W
MB81256·15-W

MB81256 Block Diagram
and Pin Assignments

A,

'Ii
CAS----+------------+or~

VSS

D

CAS

'Ii

Q

RAS

A,

A,

A,

A2

A4

Al

A,

Vee

A,

D

Q
262,144-BI1
STORAGE CELL

D

A, V..

m

18

17

"",--Vcc

.....--Vss
'Ii 3
RAS

4

N.C.

S

LCC-18C·A06
TOP VIEW

Absolute Maximum Ratings
(See Note)

=

Q

IS

Ao

I.

N.C.

A,

6

13

A2

7

12

Al

Note: The following IEEE Std. 662~1980 symbols are used in this data sheet: 0 "" Data In, W

16

Vee

10

11

A,

A,

A,

A4

Write Enable, Q = Data Out.

Rating

Symbol

Value

Voltage on any pin relative to VSS

VIN ' VOUT, Vee

-1.0 to 7.0

V

Operating temperature (case)

Top

-55 to 110

'C
'C

Unit

Storage temperature

TSTG

-55 to +150

Power dissipation

PD

1.0

W

Short circuit output current

los

50

mA

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed In the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
. may affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to avoid application of any voltage high than maximum rated voltages to this high
impedance circuit.

FUJITSU
1-51

MB81256·12·W
MB81256·15·W

Description
the Column Address Strobe
(CAS). All row addresses must
be stable on or before the falling
edge of RAS. CAS is internally
inhibited (or "gated'~ RAS to
permit triggering of CAS as soon
as the Row Address Hold/time
(t RAH ) specification has been satisfied and the address inputs
have been changed from row addresses to column addresses.

Simplifed Timing Requirement
The MB81256-W has improved
circuitry that eases timing requirements for high speed access operations. The MB81256W can operate under the condition of t RCO (max) = tCAC ' thus
providing optimal timing for address multiplexing. In addition,
the MB81256-W has minimal
hold times for Addresses (t CAH ).
Write-Enable (tWCH ) and Data-in
(toH). The MB81256-W provides
higher throughput in inter-leaved
memory system applications.
Fujitsu has made the timing reqUirements that are referenced to
RAS nonrestrictive and deleted
them from the data sheet. These
include tAR, t WCR ' tOHR and tRWO ·
As a result, the hold times of the
Column Address, D and W as
well as tcwo (CAS to W Delay)
are not restricted by t RCO ·
Fast Read-Write Cycle
The MB81256-W has a fast readmodify-write cycle which is
achieved by precise control of
the three-state output buffer as
well as by the simplified timings
described in the previous section.
The output buffer is controlled by
the state of W when CAS goes
"low". When W is "low" during a
CAS transition to "low", the
MB81256-W goes into the early
write mode in which the output
floats and the common I/O bus
can be used on the system level.
When W goes "low", the
MB81256-W goes into the delayed write mode. The output
then contains the data from the
cell selected and the data from D
is written into the cell selected.
Therefore, a very fast read-write
cycle (tRWC = tRd is possible
with the MB81256-W.
Address Inputs
A total of eighteen binary input
address bits are required to decode any 1 of 262,144 cell locations within the MB81256-W. Nine
row-address bits are established
on the input pins (Ao through As)
and are latched with the Row Address Strobe (RAS). Nine column
address bits are established on
the input pins and latched with

Write Enable
The read or write mode is selected with the W input. A logic
"high" on W dictates write mode.
The data input is disabled when
the read mode is selected.
Data Input
Data is written into the MB81256W during a write or read-write_
cyc~he last falling edge of W
or CAS is a strobe for the data-in
(D) register. In a write cycle, if W
is br~t "low" (write mo~e
fore CAS, D is strobed by CAS,
and the set-up and hold times
are referenced to CAS. In a readwrite cycle, Wwill be delayed until CAS has made its negative
transition. Thus D is strobed by
W, and set-up and hold times are
referenced to W.

RAS-Only Refresh
Refresh of dynamic memory cells
is accomplished by performing a
memory cycle at each of the 256
row-addresses (Ao - A7) at least
every 2 ms. RAS-only refresh
avoids any output during refresh
because the output buffer is in
the high impedance state unless
CAS is brought "low". Strobing
each of the 256 row-addresses
(Ao - A7) with RAS will cause all
bits in each row to be refreshed.
RAS-only refresh results in a
substantial reduction in power
dissipation.
CA5-before-RAS Refresh
CAS-before-RAS refreshing
available on the MB81256-W offers an alternate refresh method.
If CAS is held "low" for th~eci
fied period (tFCS) before RAS
goes to "low", on-chip refresh
control clock generators and the
refresh address counter are enabled, and an internal refresh operation takes place. After the
refresh operation is performed,
the refresh address counter is
automatically incremented in
preparation for the next CAS-before-RAS refresh operation.
Hidden Refresh

Data Output
The output buffer is three-state
TTL compatible with a fan-out of
two standard TTL loads. Data out
is the same polarity as data in.
The output is in ~h impedance state until CAS is brought
"low". In a read cycle, or a readwrite cycle the output is valid
after tRAC from transition of RAS
when tRCO~X). Data remains
valid until CAS is returned to
"high". In a write cycle, the identical sequence occurs, but data is
not valid.
Page Mode
Page mode operation permits
strobing the row address into the
MB81256-W while maintaining
RAS at a logic low (0) throughout
all successive memory operations in which the row address
doesn't change. Thus, the power
dissipate.s!J2y the negative going
edge of RAS is saved. Access
and cycle times are decreased
because the time normally required to strobe a new row address is eliminated.

1-52

A hidden refresh cycle may take
place while maintaining the latest
valid data at the output by extending the CAS active time. For
the MB81256-W, a hidden refresh cycle is a CAS-before-RAS
refresh cycle. The internal refresh
address counter provides the refresh addresses as in a normal
CAS-before-RAS refresh cycle.
CAS·before-RAS Refresh
Counter Test Cycle
A special timing~ence using
the CAS-before-RAS counter test
cycle provides a convenient
method of ~ing the functionality of the CAS-before-RAS refresh activated circuitry.

MB812S6-12.W
MB812S6-15-W

Description
(Continued)

After the CAS-before-RAS refresh operation, if CAS goes to
"high" and then goes to "low"
again while RAS is held "low",
the read and write operation are
enabled.
This is shown in the CAS-beforeRAS counter test cycle timing
diagram. A memory cell can be
addressed with 9 row address
bits and 9 column address bits
defined as follows:

A Column Address
All the bits AD through As are defined by latching levels on Ao
through As at the second falling
edge of CAS.
Suggested CAS:-before-RAS
Counter Test Procedure
The timirllk as shown in the CASbefore-RAS Counter Test Cycle,
is used for all the following
operations:

A Row Address
Bits AD through A7 are defined by
the refresh counter. The other bit
As is set "high" internally.

Recommended Operating
Conditions
(Referenced to Vss )

Parameter

1) Initialize the internal refresh
counter. For this operation, 8
cycles are required.

Symbol

Supply voltage

Value
Min
Typ

Mal(

Unit

4.5

5.0

5.5

V

0

0

0

V

Input high voltage all inputs

V1H

2.4

6.5

V

Input low voltage all inputs

V1L

-2.0

0.8

V

Capacitance
(TA = 25°C)

Value
Min

2) Write a test pattern of "Iow"s
into memory cells at a single
column address and 256 row
address.
3) Using a read-modify-write
cycle, read the "low" written
at the last operation (Step 2)
and write a new "high" in the
same cycle. This cycle is repeated 256 times, and "high"s
are written into the 256 memory cells.
4) Read the "high"s written at
the last operation (Step 3).
5) Complement the test pattern
and repeat steps (2), (3)
and (4).

Operating Temperature ITcl

-55°C to +110°C (case)

Parameter

Symbol

Max

Unit

Input capacitance AD to As, D

C 1N1

7

pF

Input capacitance RAS, CAS and W

C 1N2

10

pF

Output capacitance Q

C OUT

7

pF

FUJITSU
1-53

Typ

MB81258·12·W
MB81256-15-W

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

MB81256-12·W
Min
Max

MB81256-15·W
Min
Max

Parameter

Symbol

Operating currenf '
Averag~wer supply current
(RAS, CAS cycling; tRC = min.)

Icc1

72

63

mA

Standby current
Power~ply current
(RAS/CAS = VIH )

Icc2

6.0

6.0

mA

Refresh currenf 1
Average power supply current
(RAS cycling, ~ = V IH ; t RC = min.)

ICC3

61

55

mA

Page mode current"'
Average power supply current
VIL , CAS cycling; tpc = min.)

ICC4

33

28

mA

Refresh current 2'1
Average power supply current
(CAS before RAS, t RC = min.)

Icc5

66

61

mA

Input leakage current
Any input, (VIN = OV to 5.5V,
Vcc = 5.5V, Vss = OV,
all other pins not under test = OV)

IlL

-10

10

-10

10

/LA

Output leakage current
(Data is disabled, V OUT = OV to 5.5V)

IOL

-10

10

-10

10

/LA

Output level
Output low voltage
(IOL = 4.2 rnA)

VOL

0.4

V

Output level
Output high voltage
(loH = -5.0 rnA)

V OH

(RAS =

0.4

2.4

2.4

Unit

V

Note: *1 ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol
Alternate

·Standard

MB81256·12·W
Min
Max

Time between refresh

tREF

TRVRV

Random read/write cycle time

t RC

TRELREL

250
250

MB81256·15-W
Max
Min

2

2

Unit
ms
ns

280

Read-write cycle time

t RWC

TRELREL

Access time from RAS'4,6

t RAC

TRELOV

120

150

ns

Access time from CAS'5,6

t CAC

TCELOV

60

75

ns

Output buffer turn off delay

tOFF

TCEHOZ

0

25

0

30

ns

Transition time

tT

n

3

50

3

50

ns

Notes: *1

280

ns

~~ ii~:~~~~:f~e~~2~~:,,~~~ i~e~U:d~::i~:.~e~~~~~~~~ ~n~:o~~c:::~~~~:~~:~nd~c~:sO~::~:~~i::,chieved. If

"2 AC characteristics assume tT = 5ns.
*3 VIH (min.) and VIL (max.) are reference levels measured between VIH and VIL'
*4 tRCD is specified as a reference point only. If IRCD os;. tACO (max.) the specified maximum value of tRAC (max.) can be met. If
tACO> IRCO (max.) then tRAC is increased by the amount that tRCD exceeds tRCD (max.)
"5 Assumes thai tRCD > tRCD (max.).
"'6 Measured with a load equivalent to 2 TTL loads and 1DO pF.

1-54

MB81256·12·W
MB81256·15·W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Symbol
Alternate

'Standard

MB81256·12·W
Min
Max

MB81256·15·W
Min
Max

RAS precharge time

IRP

TREHREL

120

120

RAS pulse width

I RAS

TRELREH

120

Parameter

RAS hold time

t RSH

TCELREH

60

CAS pulse width

I CAS

TCELCEH

60

CAS hold time

ICSH

TRELCEH

120

10000

150

ns

10000

75
10000

75

ns
ns

10000

150

ns
ns

RAS 10 CAS delay time"'·7

I RCO

TRELCEL

22

CAS 10 RAS set up lime

I CRS

TCEXREL

20

20

ns
ns

60

25

Unit

75

ns

Row address sel up lime

t ASR

TAVREL

0

0

Row address hold lime

IRAH

TRELAX

12

15

ns

Column address sel up lime

tASC

TAVCEL

0

0

ns

Column address hold time

ICAH

TCELAX

20

25

ns

Read command sel up time

t RCS

TWHCEL

0

0

ns

Read command hold lime
referenced to CAS "9

I RCH

TCEHWX

0

0

ns

Read command hold lime
referenced to RAS"9

IRRH

TREHWX

20

20

ns

Write command set up time"S

twcs

TWLCEL

0

0

ns

Write command pulse width

twp

TWLWH

20

25

ns

Write command hold time

t WCH

TCELWH

20

25

ns

Write command to
RAS lead time

t RWL

TWLREH

50

60

ns

Write command 10
CAS lead time

tCWL

TWLCEH

50

60

ns

Data in set up time

tos

TDVCEL

0

0

ns

Data in hold time

tOH

TCELDX

20

25

ns

CAS to W delay"S

t cwo

TCELWL

20

25

ns

t FCS

TCELREL

25

30

ns

Refresh hold time for CAS
referenced to RAS

t FCH

TRELCEX

25

30

ns

RAS precharge 10 CAS
aclive lime

t RPC

TREHCEL

20

20

ns

Page mode read/write
cycle time

tpc

TCELCEL

120

150

ns

Page mode read-write
cycle time

t pRWC

TCEHCEH

120

150

ns

Page mode CAS
precharge lime

tcp

TCEHCEL

50

65

ns

CAS precharge time for CAS
before RAS refresh cycle

t CPR

TCEHCEL

25

30

ns

Refresh set up time for
referenced to RAS

CAS

NOI..: *These symbols are described in IEEE STD. 662-1980: IEEE Standard terminology for semiconductor memory.
*4 tRCD is specified as a reference point only. If tACO";; tRCD (max.) the specified maximum value of tRAC (max.) can be met. If

tACO> tRCD (max.) then tRAC is increased by the amount that tRCD exceeds tRCD (max.)
= tRAH (min.) + 2tT + lASe (min.).
twes and tcw~ are non restrictive operating parameters, and are included in the data sheet as electrical characteristics only. If
Iwes > twes min.), the cyde is an early write cycle, and the data out pin will remain open circuit (High Impedance) throughout
the entire cycle. If tewD > tewD (min.), the cycle Is a read-write cycle and data out will contain data read from the selected cell. If
neither of the above sets of conditions is satisfied, the condition of the data out is indeterminate.

*7 tRCD (min.)

*8

*9 Either tACH or tARH must be satisfied for a read cyde.

FUJITSU
1-55

,--

-------

MB81251i-12.W
MB81258-15·W

Timing Diagrams
Readel/cle
IRC
IRAS
RAS

CAS

ADDRESS

V,H
V,L

V,H
V,L

V,H
V,L
I+-+-~IRRH

W

V,L
V,H
IRCH

a

t_IoFF_
_ _ _r-

VOH

VAUDDATA

VOL

~DON'TCARE

1·56

MB81256-12·W
MB81256·15-W

Timing Diagrams
(Continued)

Write Cycle (Early Write,
IRC

I+-- IRP -----

tRAS

RAS

CAS

ADDRESS

V,H
V,L

V,H
V,L

V,H
V,L

~

1\

-

~k.

tRSH

~,"CO

w~

Q

1/7

~

~

f----lCAHCOL. ADD.

ROW. ADD.

sf.-

~IWCH

__

Iwp

V,H
V,L

IDS
D

lCAS

1\\

IWC

W

"'--

ICSH

fool- ICRS

V,H

?\.

V,L

'Y.

VOH
VOL

--

'OH_
VALID DATA

---------------HIGH·Z------------~DON·TCARE

FUJITSU
1-57

MB81256-12·W
MB81258-15-W

Timing Diagrams
(Continued)

Read·Write/R_d.Modify.Write Cycle

tnwc

I!AiI

1:U

v,.
VIL

v,.
VL

~

Wf....

teB.

f-tcRs

Vi

v,.
VIL

~

""'"

i l' -

''CAB
RS.

r\ \
!+-'RA._

~

ADDRESS

~'RP~

"'AS

-------.

~ 'ASC

ROW. ADD.

V
_'CAH_

COL. ADD

H'RCS

'cwo

--'"~I
_twp_

V..
V'L

'I

_teAC"
Q

lewL

V,.

~

'OFF

VALID DATA

VIL

·I,~'DH

tRAe

los

D

~DON'TCA"E

1-58

MB81256·12·W
MB81256·15-W

Timing Diagrams
(Continued)

"RAS·Only" Refresh Cycle
Note: ~ = VIH, W, D = Don't Care, As

=

VIL or VIH

~-------------tRC------------------~

I__- - - I R A S - - - - - - - - I - !

~tRP------+I

ADDRESS
(AotoA7)

VOH

Q

VOL

00 DON'T CARE
Page Mode Read Cycle

V,H

iiAS
VOL

!lAS

V,H
VOL

V,H
ADDRESS

VOL

V,H
VOL

VOH
Q

VOL

00 DON'T CARE

FUJITSU
1-59

MB81256-12·W
MB81256·15·W

Timing Diagrams
(Continued)

Page Mode Write Cycle

ADDRESS

w

Q

yOH __________~4_~--~--------_++

VOL

D

ooa

1·60

DON'T CARE

MB8f256·f2·W
MB8f256·fSoW

Timing Diagrams
(Continued)

Hidden Refresh Cycle
IRC

tif

tRAS

V,H

ill

V,L
teRs

V,H
CAS

V,L

-

~

V,H
V,L

V,H

~

1\

IRCO_

,,\

tCAS

~
-

ROW. ADD.

-

i-

I------

teAH

IASC

COL. ADD.

i-

IRes

!.-IRRH_

I--

V,L

tRWL

-

~teAC-

I--

tRAe

VOH

VALID DATA

IRCS_

I-

~

~IOFF

j["--

VOL

W(READWRITE)

V-

I-IFCH _

I---IR... - -

W(READ)

Q

•

tRAS

-

tRAH

~
ADDRESS

_

RP

twp

\

V,H
V,L

m

FUJITSU
1-61

DON'T CARE

MB81256-12-W
MB81256-15-W

Timing Diagrams
( Continued)

"CAS-Before-RAS" Refresh Cycle
Note: A, W, D = Don't Care

~_ _ tOFF

a

~:~

-f--------------

HIGH-Z - - - - - - - - - - - - - - - -

(KXJ DON'T CARE
Page Mode Read-Write Cycle

RAS

CAS

ADDRESS

W

Q

V'H

v"

V'H

v"

V'H

v"

V'H

v"

VOH
VOL

V'H

0

VIL

~ DON'T CARE

1-62

MB81256·12·W
MB81256·15·W

Timing Diagrams
(Continued)

"CAS·Before·RAS" Refresh Counter Test Cycle

•.
V,

•

tRTe
tTRAS

H

v, L

r--'eSH- ~
lep-..

_ _ 'RP _ _

_---tAsH

,_ >'eo,

..-----tCAS

~

:\
..-tcAH________..

---ADDRESS

~tASC

Ie/X
f-\

COLUMN
ADDRESS

)"

L

---

1- .1

tRCS

W(REAO)

•

VOH

IRC~_

.r--

tOFF

VALID DATA

VOL

W (WRITE)

tRRH

'I

~ICAC

Q

~
}f

L

f.-tCWD-"

,

tRCS

'DS ,.-

f-'ew~L-=i
~tRWL
I---'wp-

~

I--'DH

D

~DON'TCARE

FUJITSU
1·63

~

,x.

MB8i258·i2·W
MB8i2Se-i5-W

Package Dimensions
Dimensions in inches
(millimeters)

ie-Lead Ceramic IMetal Seal) Dual In·Llne Package
ICase NO.1 DIP-i6C·A031

~t[~::: :~[G:
I

..

.760(19.30)
.800(20.32)

•

.260(7.37)

31
•

I

SJ

Ill=,====+==

·200(S.OS)MAX

.090(2.29)
.110(2.79)

~--r---~~~----~~

.12O(3.0S)
.150(3.81)

.000(0.Sl)
.043(1.10)

.015(0.38)
.023(0.59)

ie-Lead Seam Weld Dip Package
ICa.e NO.1 DIP·i8C·A041

11

.290(7.37)

. . . .=:::!,==i===.3T~
.780(19.30)
.800(20.32)

1-64

MB81256·12·W
MB81258.150W

Paeka.e Dimensions
(Continued)
Dimensions in inches
(millimeters)

18·Pad C.eramle L_dl.ss Chip Carrl.r
LCCo18C·AU8)

PIN NQ 1 INDEX

/

.045(1.14)TVP

6

.485(12.32)
.505(12.83)

.070(1.78)

.280(7.111

O'083(2'")MAX

.295(7A9)

1-65

TVP
.045(1.14)
TVP

FUJITSU

MOS Memories
•

MB81257.12.W, MB81257·15·W
NMOS 262,144-Bit Dynamic
Random Access Memory
With Nibble Mode

Description
The Fujitsu MB81257-W is a fully decoded, dynamic NMOS random access memory organized as 262,144 one-bit words. The design is optimized for high speed, high performance applications
such as mainframe memory, buffer memory, peripheral storage
and environments where low power dissipation and compact layout
are required.
The MB81257-W features "nibble mode" which allows high speed
serial access of up to four bits of data. Additionally, the MB81257W offers new functional enhancements that make it more versatile
than previous dynamic RAMs. "CAS-belore-RAS" refresh provides
an on-Chip refresh capability that is an upward compatible version
of the MB8266A. Multiplexed row and column address inputs permit the MB81257-W to be housed in a Jedec standard 16-pin dual
in-line package and 18-pad LCC.
The MB81257-W is fabricated using silicon gate NMOS and
Fujitsu's advanced Triple-layer Polysilicon process. This process,
coupled with single transistor memory storage cells, permits maximum circuit density and minimal chip size. Dynamic circuitry is
used in the design, including dynamic sense amplifiers.
Clock timing requirements are noncritical, and the power supply
tolerance is very wide. All inputs are TTL compatible.

Features
•

Wide temperature range:
Tc = -55°C to 110°C
• 262,144 x I-bit organization
• Row Access Time/Cycle Time:
MB81257-12-W
120 ns max./250 ns min.
MB81257-15-W
150 ns max./280 ns min.
• Low Power Dissipation:
347 mW max. (tRC = 280 ns)
33 mW (Standby)
• Nibble cycle time:
MB81257-12-W 65 ns max.
MB81257-15-W 80 ns max.
• +5V supply voltage,
± 10% tolerance
• All inputs TTL compatible,
low capacitive load
• Three-state TTL compatible
output
• Common I/O capability
using "Early Write" operation

•

On-chip substrate bias
generator
Nibble mode capability for
faster access
• Fast Read-Write Cycle,
•

t RWC
•

•
•
•
•
•
•
•

1-66

= t RC

tAR' t WCR' t OHR'

t RWO

eliminated
CA8-before-RMi on chip
refresh
Hidden CA8-before-RMi
on-chip refresh
RA!-only refresh
Refresh 2 ms/256 cycle
refresh
Output unlatched at cycle
end allows two dimensional
chip select
On-chip Address and
Data-In latches
Industry standard 16-pln
package

MB81257·12·W
MB81257·15-W

MB81257 Block Diagram
and Pin Assignments
RAS-------------"i

w
CAS----~----------_+or~

"Aa

vOO

CAS

0

W

o

Q

HAS

Aa

AO

A,

A,

A,

A,

A,

Vee

A7

Q

IS

17

262,144-BIT

STORAGE CELL
~Vcc

4 - - VSS

W 3

HAS

4

N.C.

5

Ao
A,

16 Q
15

Aa

14

N.C.

6

13

Ao

7

12

A,

LCC·1SC·ADS
TOP VIEW

A,

Note: The following IEEE Std. 662-1980 symbols are used in this data sheet: 0 = Data In, W = Write Enable,

Absolute Maximum Ratings
(See Note)

Vee

10

11

A7

A,

a = Data OUt.

Rating

Symbol

Value

Unit

Voltage on any pin relative to VSS

V IN • VOUT • Vee

-1.0 to 7.0

V

Operating temperature (case)

Top

-55 to 110

·C

Storage temperature

TSTG

-55 to +150

·C

Power dissipation

PD

1.0

W

ShDrt circuit output current

los

50

mA

Note: Permanent device damage may occur jf ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reUability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields.
However. it is adVised that normal precautions be taken to avoid application of any voltage high than maximum rated voltages to this high
impedance circuit.

FUJITSU
1-67

MB81257·12·W
MB81257·15-W

Description
Simplified Timing Requirement

Addresa Inputs

Data Output

The M881257 has improved circuitry that eases timing requirements for high speed access
operations. The MB81257 can
operate under the condition of
t RCD (max.) = !cAC' thus providing optimal timing for address
multiplexing. In addition, the
M881257 has minimal hold times
for Addresses (leAH)' WrHe-Enable (tWCH) and Data-in (tDH). The
MB81257 provides higher
throughput in interleaved memory
system applications. Fujitsu has
made the timing requirements
that are referenced to RAS nonrestrictive and deleted them from
the data sheet. These include
tAR' tWCR' tDHR and tAWD. As a result, the hold times of the Column
Address, 0 and 'iN as well as
!cwo (CAS to W Delay) are not
restricted by tACO'

A total of eighteen binary input
address bits are required to decode any 1 of 262,144 cell locations within the M881257. Nine
row address bits are established
on the input pins (Ao through As)
and are latched with the Row Address Strobe (RAS). Nine column
address bits are established on
the input pins and latched with
the Column Address Strobe
(CAS). All input addresses must
be stable on or before the falling
edge of RAS. CAS is internally
inhibited (or "gated") by RAS" to
permit triggering of eAS as soon
as the Row Address Hold/Time
(tRAH) specification has been satisfied and the address inputs
have been changed from row addresses to column addresses.

The output buffer is three-state
TTL compatible with a fan-out of
two standard TTL loads. Data out
is the same polarity as data in.
The output is in ~h impedance state until CAS is brought
"low". In a read cycle, or a readwrite cycle, the output is valid
after tRAC from transition of RAS
when tRAC from transition of RAS
when tRCD/max.) is satisfied, o:!!:....after t CAC from transition of CAS
when the transition accurs after
t RCJllomx.). Data remains valid until CAS is returned to "high". In a
write cycle, the identical sequence occurs, but data is not
valid.

Fast Read·Wrlte Cycle
The M881257 has a fest readmodify-write cycle which is
achieved by precise control of
the three-state output buffer as
well as by the simplified timings
described in the previous section.
The output buffer is controlled by
goes
the state of 'iN when
"low". When 'iN is "low" during a
~ transition to "low", the
MB81257 goes into the early
write mode in which the output
floats and the common I/O bus
can be used on the system level.
When 'iN goes "low", after tCWD
following a ~ transition to
"low", the MB81257 goes into the
delayed write mode. The output
then contains the data from the
cell selected and the data from 0
is written into the cell selected.
Therefore, a very fast read-wrHe
cycle (tRWC = tRd is possible
wHh the M881257.

m

Write Enable
The read or write mode is selected with the 'iN input. A logic
"high" on 'iN dictates read mode.
A logic "low" dictates write mode.
The data input is disabled when
the read mode is selected ..
Data Input
Data is written into the MB81257
during a write or read-write ~.
The last falling edge of IN or ~
is a strobe for the Data-in (D)
register. In a wrHe cycle, if W is
brou~low" (write mode) before CAS, 0 is strobed by CAS',
and the set-up and hold times
are referenced to CAS'. In a readwri~cle, 'iN will be delayed until CAS has made its negative
transition. Thus 0 is strobed by
IN, and set-up and hold times are
referenced to 'iN.

Nibble Mode
Nibble mode allows high speed
serial read, write or read-modifywrite access of 2-, 3- or 4-bits of
data. The bits of data that may
be accessed during nibble mode
are determined by the 8 row addresses and the 8 column addresses. The 2-bits of addresses
(CAe, RAe) are used to select 1
of the 4 nibble bits for initial access. After the first bit is accessed by the normal mode, the
remaining nibble bits may be accessed by toggling CAS "high"
then "low" while FiAS remains
"low". Toggling CAS causes RAe
and CAe to be incremented internally while all other address bits
are held constant and makes the
next nibble bit available for access. (See table I below).
If more than 4-bits are accessed
during nibble mode, the address
sequence will begin to repeat. If
any bit is written during nibble
mode, the new data will be read
on any subsequent access. If the
write operation is executed again
on subsequent access, the new
data will be written into the selected ceillacation.

Nibble Mode Address
Sequence Example
SEQUENCE

NleBLE err

RASICAS (normal mode)

m
m
toggle m
toggle m

RAe

COLUMN
ADDRESS

COMMENTS

10101010

10101010

Input addreaaea

ROW ADDRESS

cAe

toggle

(nibble mode)

10101010

10101010

toggle

(nibble m_)

10101010

10101010

(nibble mode)

10101010

10101010

(nibble modo)

10101010

10101010

1-68

generated internally

sequence repeats

MB81257·12.W
MB81257·15-W

D••crlptlon
(Continued)

In nibble mode, the threa-state
control of the DOUT pin is determined by the first normal access
cycle.

CA5-before-RAS Refresh
CAS-befora-RAS refreshing
available on the MB81257 offers
an altemate refresh method. "
CAS is held "low" for the~ci
fled period (t FCS) before RAS
goes to "low", on-chip refresh
control clock generators and the
refresh address counter are enabled, and an internal refresh operation takes place. After the
refresh operation is performed,
the refresh address counter is
automatically incremented in
preparation for the next CAS-befora-1'iAS refresh operation.

The data output is controlled only
~e W state referenced at the
CAS negative transition of the
normal cycle (first nibble bit).
That is, when twcs > twcs (min.)
is met, the data output will remain open circuit throughout the
succeeding nibble cycle regardless of the W state. When tewD
> IcWD(min.) is met, the data
output will contain data from the
cell selected during the succeeding nibble cycle regardless of the
W state. The write operation is
done during the period in which
the Wand CAS clocks are low.
Therefore, the write operation
can be performed bit by bit during each nibble operation regaro:!:
less of the timing conditions of W
(twcs and lewD) during the normal cycle (first nibble bit). (See
table" and Figure 2 below).

Hidden Refresh
A hidden refresh cycle may take
place while maintaining the latest
valid data at the output by extending the CAS active time. For
the MB81257, a hidden refresh
cycle is a CAS-before-RAS refresh cycle. The internal refresh
address counter provides the refresh addresses as in a normal
CAS-befora-RAS refresh cycle.

RAS-Only Refresh
Refresh of dynamic memory cells
is accomplished by performing a
memory cycle at each of the 256
row-address~o - A7) at least
every 4 ms. RAS-only refresh
avoids any output during refresh
because the output buffer is in
the high impedance state unless
CAS is brought "low". Strobing
each of the 256 row-addresses
(Ao - A7) with RAS will cause all
bits in each row to be refreshed.
RAS-only refresh results in a
substantial reduction in power
diSSipation.

CMi·before-RAS Refresh
Counter Test Cycle
A special timing ~uence using
the CAS-befora-RAS counter test
cycle provides a convenient
method of verifying the functionality of the CAS-befora-RAS rafresh activated circuitry.
After the CAS-before-RAS" refresh operation, if CAS goes to
"high" and then goes to "low"
again while RAS is held "loW",
the read and write operation are
enabled.

This is shown in the CAS-beforeRAS counter test cycle timing
diagram. A memory cell can be
addressed with 9 row address
bits and 9 column address bits
defined as follows:
A Row Address
Bits Ao through A7 are defined by
the refresh counter. The other bit
As is set "high" internally.
A Column Address
All the bits Ao through As are dafined by latching levels on Ao
through ~t the second falling
edge of CAS.
Suggested CAS·befora-RAS
Refresh Counter Test
Procedure
The tim~ as shown in the CASbefore-RAS Counter Test Cycle,
is used for all the following
operations:
1) Initialize the internal refresh
counter. For this operation, 8
cycles are required.
2) Write a test pattern of "Iow"s
into memory cells at a single
column address and 256 row
address.

3) Using a read-modify-write
cycle, read the "low" written
at the last operation (Step 2)
and write a new "high" in the
same cycle. This cycle is repeated 256 times, and "high"s
are written into the 256 memory cells.
4) Read the "high"s written at
the last operation (Step 3).

5) Complement the test pattern
and repeat steps 2, 3,
and 4.

Functional Truth Tabl.
RAS

CAS

w

IN

OUT

H

H

Don't Care

Don't Care

Hlgh-Z

H

Wrile

Refresh

No

No

No

Slendby

Note

Don'tCa,.

Valid Dale

Veo

No

Ves

Read

L

Valid Data

HIgh-Z

No

V..

Ves

Early Write
!wCS " IWCS (min.)

L

Valid Data

Valid Data

Vea

Vea

Ves

Delayed Write or Read-Write
leWD;;" leWD (min.)

L

L

Read

H

Don't Care

Don't Care

Hlgh·Z

No

No

Ves

RA&only Refresh

Don't Care

Don't Care

Valid Data

No

No

Vea

CAS-befor.RAS Refresh.
Valid data setected at previou8

Don't Care

Don't Care

Hlgh·Z

No

No

No

CASdl.turb

Read or Read-Write cycle is hefd

H

FUJITSU
1-69

MB81257·12·W
MB81257·15-W

Recommended Operating
Conditions
(Referenced to Vss )

Parameter
Supply voltage

Symbol

Value
Min
Typ

Max

Unit

Vcc

4.5

5.0

5.5

V

0

Vss

0

0

V

Input high voltage all inputs

VIH

2.4

6.5

V

Input low voltage all inputs

VIL

-2.0

0.8

V

Ii'

Operating Temperature IT

-55"C to +110"C (case)

Capacitance
(TA = 25"C)

Value
Typ

Parameter

Symbol

Min

Input capacitance Ao to As, D

C IN1

Max
7

Unit
pF

Input capacitance RAS, CAS and W

C IN2

10

pF

Output capacitance Q

COUT

7

pF

Parameter

Symbol

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

MB81257·12·W
Min
Max

MB81257·16·W
Min
Max

Unit

Operating Currenf 1
Averag~er ~upply curre~t

ICCl

72

63

mA

IC02

6.0

6.0

mA

Icca

61

55

mA

IcC4

22

20

mA

Refresh Current 2"1
Average power supply current
(CAS before RAS, tRC = min.)

Icc5

66

61

mA

Input Leakage Current
Any input, (VIN = OV to 5.5V,
VCC = 5.5V, Vss = OV,
all other pins not under test = OV)

IlL

-10

10

-10

10

I-'A

Output Leakage Current
(Data is disabled, VOUT = OV to 5.5V)

IOL

-10

10

-10

10

I-'A

Output Level
Output low vonage
(loL = 4.2 mAl

VOL

0.4

V

Output Level
Output high voltage
(IOH = -5.0 mAl

VOH

(RAS, C

cycling; t RC

= min.)

Standby Current
Power~PIY. current
(RAS/CA = VIH )
Refresh Current 1"1
Average ~Owe~pIY current
(RAS cycling, A = VIH ; tRC

= min.)

Nibble Mode Current"l
Average power supply current
(RAS = V IL , CAS cycling; tNC

= min.)

Note:

.

0.4

2.4

2.4

*' ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

1-70

V

MB81257·12·W
MB81257·15-W

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol
Alternate

·Standard

MB81257·12·W
Min
Max

MB81257·15-W
Min
Max

Time between refresh

tREF

TRVRV

Random read/write cycle time

t RC

TRELREL

250

280

Read-write cycle time

t RWC

TRELREL

250

280

Access time from RAS·4,6

t RAC

TRELQV

120

150

ns

Access time from CAS-5,6

t CAC

TCELQV

60

75

ns

2

2

Unit
ms
ns
ns

Output buffer turn off delay

tOFF

TCEHQZ

0

25

0

30

ns

Transition time

tT

TT

3

50

3

50

ns

RAS precharge time

t RP

TREHREL

120

RAS pulse width

t RAS

TRELREH

120

100000

ns

RAS hold time

t RSH

TCELREH

60

CAS pulse width

t CAS

TCELCEH

60

CAS hold time

tCSH

TRELCEH

120

RAS to CAS delay time·4,7

t RCD

TRELCEL

22

120
100000

150

ns

75
100000

75

ns

100000

ns

75

ns

150
60

25

ns

CAS to RAS set up time

t CRS

TCEHREL

20

20

ns

Row address set up time

t ASR

TAVREL

0

ns

Row address hold time

tRAH

TRELAX

0
12

15

ns

Column address set up time

t ASC

TAVCEL

0

0

ns

Column address hold time

tCAH

TCELAX

20

25

ns

Read command set up time

t RCS

TWHCEL

0

0

ns

Read command hold time
referenced to CAS·l0

tRCH

TCEHWX

0

0

ns

Read command hold time
referenced to RAS·l0

tRRH

TREHWX

20

20

ns

Write command set up time·s

twcs

TWLCEL

0

0

ns

Write command pulse width

twp

TWLWH

20

25

ns

Write command hold time

t WCH

TCELWH

20

25

ns

Write command to
RAS lead time

t RWL

TWLREH

50

60

ns

Write command to
CAS lead time

tCWL

TWLCEH

30

40

ns

Notes:

*

These symbols are described in IEEE STD. 662-1980: IEEE Standard tenninology for semiconductor memory.

*1 :

i~:~~~r;~~~~h20~:n~~~ i~e~u~~:~~~~:~~i!~~:,ed8~Yb:ro~SAA§I~~!~~~i:~::~:~~:::=i~~~r:~~ieVed. ~

*2 AC characteristics assume IT = 5 ns.
*3 VIH (min.) and VIL (max.) are reference"ievels for measuring timing of input signals. AlSo. transition times are measured between
VIH and V,L'
*4 IRCD is specified as a reference point only. If tRCD 0;; tRCD (max.) the specified maximum value of tRAC (max.) can be met. If
tRCD > tRCD (max.) then tRAC is increased by the amount that IRCD exceeds tRCD (max.).
*5 Assumes that tRCD > tRCD (max.)
·6 Measured with a load equivalent to 2 TTL loads and 100 pF.
*7 tACO (min.)

*8

=

tRAH (min.) + 2tT + tASC (min.).

!:g~ ~~~~~?m~~~),n~~ r=~~~:~::r~;i:~ea~~~e~nd~~: ~~~n!~~~~ ~II~:~:~ ~~:~c~~~e~;1 I~~a~::~fi::~~hol~t
~h~e~~:~:t~:· ~:~~ :r:~d\~~~~' i~:a~:di~t~::~d~~~ ~~:eadn::~: ~u~n~:~:~:~e~ata read from the selected cell.

*10 Either tACH or tRRH must be satisfied for a read cycle.

FUJITSU

1-71

MB81257.12.W
MB81257·15·W

AC Charact.rlstlcs
(Continued)
(Recommended operallng
condllions unless otherwise
noted.)

Paramet.r

Symbol
Alt.mat.

·Standard

Dala in set up lime

los

TDVCEL

Data in hold lime

CAS 10 W delay'S
Refresh set up time for
referenced to FlAS

eA1l

MB81257·12·W
Min
Ma.

MB81257·15·W
Min
Ma.

IOH
Icwo

TCELWL

20

0
25
25

ns

TCELDX

0
20

Unit

ns
ns

I FCS

TCELREL

25

30

ns

Refresh hold time for ~
referenced to RAS

t FCH

TRELCEX

25

30

ns

Nibble mode read·write
cycle time

t NRWC

TCEHCEH

65

80

ns

Nibble mode read/write
cycle time

t NC

TCEHCEH

65

80

ns

Nibble mode access lime

t NCAC

TCELQV

Nibble mode ~
pulse width

INCAS

TCELCEH

30

40

ns

t NCP

TCEHCEL

25

30

ns

tNRRSH

TCELREH

30

40

ns

tRNH

TREHCEL

20

20

ns

tNwRSH

TCELREH

50

60

ns

RAS' precharge to CAS
active time

t RPC

TREHCEL

20

20

ns

CAS precharge lime for ~
before JtiiS refresh cycle

t CPR

TCEHCEL

25

30

ns

Nibble mode CAS
precharge lime
Nibble mode read
hold time

RAS

Nibble mode CAS' hold lime
referenced to RAS
Nibble mode wrile
hold lime

Not..:

RAS

30

40

ns

.. These symbols are described In IEEE STD. 662~19BO: IEEE Standard terminology for semiconductor memory.
*8 twcs and tcw~ are non restrictlve operating parameters, and are Included in the data sheet as electrical characteristics only. If
twcs > t~ min.), the cycle is an early write cycle, and the data out pin will remain open circuit (High Impedance) throughout

~~~e~~:,eof th:' ~~~:,~e: ~~~~!~' i!h:a=~i.St~::~d~: ~:e ad~'!ad~: ~u~~~:n~!~e~ta read from the selected cell.
"9 Test mode cycle only.

1·72

MB81257·12·W
MB81257·15·W

Timing Diagrams
Read Cycle

iiAS

VIH
VIL

CAS

VIH
VIL

ADDRESS

VIH
VIL
tRRH

W

VIL
VIH

r'"

tRCH

Q

VOH

VALID DATA

VOL

~DON'TCARE

FUJITSU
1·73

MB81257·12·W
MB81257.15-W

Timing Diagrams
(Continued)

Write Cycle (Early Write)
IRe
IRAS

I---'"p-

----,
V,H
V,L

CAS

V,H
V,L

1\

-

ADDRESS

V,L

~ASR
~

,"SH

1\\
~

~
COL. ADD.

ROW. ADD.

I-

ro---Iwp

tweH - -

V,H
V,L

los

D

VI

~ICAH_

twes

Vi

ICAS

j.--,"eo

~

V,H

~

ICSH
fool-leRS

I--

V,H

10H_

VALID DATA

V,L

Q

VOlt

-----------------------------OPEN-----------------------------

VOl.

~DON·TCARE

1·74

MB81257·12·W
MB81257·15·W

Timing Diagrams
(Continued)
Read·Write/Raad·Modlfy·Write Cycle

,"we

;;AS

VIH

~IRP~

lA-AS

-----,

1\

VIL

if-

tesH

~

-eA§

V'H
V'L

~

IASR

ADDRESS

V'H
V'L

r-- 'CRS

~

_'RAH_

loco

IRSH
'CAS

-

f\ \

ROW.ADD.

lAse

11
_'CAH_

COL. ADD

_IRWL _ _ _
tCWD

H'RCS

\Ii

-Y::/',

_ 'wp_

V'H
V'L

!+tcAC_

Q

tCWL

V'H

~'DFF

VAUD DATA

V'L

±t:

tRAC

los

~DON'TCARE

FUJITSU

1-75

MB81257·12·W
MB81257·15-W

Timing Diagrams
(Continued)

"RAS-Only" Refresh Cycle
Note: W, D = Don't Care, Va = VIH or VIL

'AC

4

tRAS

4

L

ADDRESS
(Ao·oA7)

t'>..,

-----

L

'AP

~'AAHtASR

ROW
ADDRESS

,,
I

~

Q

H

Vo
VoL

1"-

H·APC

'OFF

HIGH-Z

00 DON'T CARE
"CAS-Before·RAS" Refresh Cycle
Note: Address, W, D

V..
Q

=

Don't Care

~_tOFF

VIL - { - - - - - - - - - - - - - OPEN - - - - - - - - - - - - - - -

[XX] DON'T CARE

1·76

MB81257·12·W
MB81257·15·W

Timing Diagrams
(Continued)

Hidden Refresh Cycle
~-

'RC

RAS

tRAS

kf

V,L

teRs

~

.

t'RP-

~·---'RAS

V,H

f\

V-

!-'FCH_

I---'OCD-!---'RSH_
teAS

V,H
CAS

V,L

~

1\\
tRAH

'ASR

t--V,H
ADDRESS

W(Read)

V,L

V,H

~

~

-

I-

ROW.ADD.

-

I--

COL. ADD.

I-

tRCS

!--'RRH_

V,L

~
Q

teAH

tAse

+-'CAC-

-

tRWL

~

tRAC

VOH

VALID DATA

VOL
'RCS_

W(ReadWrite)

I-

~

l--'OfF

r-

'WP

\

V,H
V,L

mDON'TeARE

FUJITSU
1-77

MB81257·12·W
MB81257·150W

Timing Diagrams
(Continued)

Nibble Mode

'1 THE CASE OF FIRST NIBBLE CYCLE IS EARLY WRITE

\'---__________r
\'---_/

w

o

Q

)

HIGH·Z-----------------

r-EARLYWRITE~NOOPEN

.,..

II-o"O-----WRITE--4

WRITE---i...

(ADD INCREMENT)

l?Z2l VALID DATA

1·78

MB81257·12·W
MB81257·15·W

Timing Diagrams
(Continued)

Nibble Mode
*2 THE CASE OF FIRST NIBBLE CYCLE IS DELAYED WRITE (READ-WRITE)

\'---____-------Jr
\'----~/

w

D

Q

i---READ-WRITE

. I.

READ-WRITE4~READ~READ-WRITE--.J

tZZl VALID DATA
Nibble Mode Read Cycle

ADDRESS

w

Q

VOH

VOL-------------- -O.SV.

FUJITSU
1·86

MB81418·10
MB81418·12
MB81418·15

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)
M881418.10

M881418·12 M881418·15

Min

Min

S""bol
Alternate

• Standard

Time between Relresh

tREF

TRVRV

Random ReadlWrite Cycle Time

t AC

TRELREL

t Rwe
t RAC
I CAC

TRELREL
TRELOV
TCELOV

Parameter

Not. .

ReadoWrite Cycle Time
Access Time from flAS
Access Time from CAS

(4),(6)
(5),(6)

Max

200
290

230
330
100

120
60

35
50

OulpUI Buffer Turn Off Delay

tOFF

TCEHOZ

30

tT
t RP

50

I RAS

RAS Hold Time
CAS Precharge Time (Page Mode only)

t RsH
tep

TT
TREHREL
TRELREH
TCELREH
TCEHCEL

90
100
50
45

CAS Precharge Time
(All cycles except page mode)

t

TCEHCEL

40

10000

100
120
60
50

Read Command Hold Time
Referenced 10 CAS
Wrile Command Set Up Time
Write Command Hold Time
Wrile Command Pulse Widlh
Write Command to RAS Lead Time
Write Command 10 CAS Lead Time
Data In Set Up Time
Data In Hold Time
CAS to W Delay
RAS to W Delay
Access Time from G

tRAH
t ASC
leAH
t Res

(9)

45

G to Data in Delay Time

55

Notes: See notes on next page.

(11)
(11)

15
0

20

20

ns
ns

o

o

-5

-5

-5

ns

20
20

25
25

30
30
60
60

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tCWD
t RWD

TDVCEL
TCELDX
TCELWL
TRELWL
TGLOV
TGHDV
lWLGL
TGHQZ
TCELCEL
TCEHCEH

45

50

45

50

20
85
135

25
100
160

o

25
30

o

30
120
195
30

30

o

40

40

35
35

o
145
240

ns
ns
ns

40

160

120
205

TCELREL

20

25

30

ns

TRELCEH

20

25

30

ns

20

20
325
435

20
390
500

ns
ns
ns

tOES

TREHCEL
TRELREH
TRELREL
TGLREH

ns

TDXCEL
TDXGL

o
o

o

loze
lozo

o

ns
ns

lePR

TCEHCEL

30

30

ns

CAS Hold Time Referenced
10 RAS (CAS before i'lAS Refresh)

G to RAS Inactive Setup Time

20

o

15

10

0

o

Page Mode Read·Wrlte Cycle Time
CAS Set ldE.Iime Referenced
10 RAS (CAS before RAS Refresh)

Dala in to CAS Delay Time
DalaintoGDelayTime
CAS Preehar~e
(CAS before RAS cycle)

15

o

75

TCEHWX

10EZ

(10)
(10)

ns

10000

ns
ns
ns
ns
ns
ns
ns
ns
ns

75
150
25
30

lWLCEL
TCELWH
lWLWH
lWLREH
lWLCEH

G Hold Time Referenced 10 W

RAS Precharge to CAS Active Time
Refresh Counter Test RAS Pulse Width
RefreshCounlerTeslCyeleTime

10000

ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

twcs

tOED

Oulpul Buffer Turn Off Delay from G
Page Mode Cycle Time

10

40
50

Unit

tACH

tCWL

(8)
(8)

TRELAX
TAVCEL
TCELAX
lWHCEL

Max

150
75

0
3
100
10000 150
75
60

C~A~S~P~u~ls~e~W_i~dt_h____________________~t~eA~s~____-=TC~EL~C~E~H~___5~0~__~10~00~0___6~0~__~1oooo~
CAS Hold Time
tCSH
TRELCEH
100
120
RAS to CAS Delay Time
(4), (7)
IACD
TRELCEL
20
50
20
60
CAS to i'lAS Set Up Time
t eRs
TCEHREL
20
25
Row Address Set Up Time
IASR
TAVREL
0

Row Address Hold Time
Column Address Set Up Time
Column Address Hold Time
Read Command Sel Up Time

Min

260
375

50

Transition Time
RAS Precharge Time
RAS Pulse Width

ePN

Max

IRPC
ITRAS
lATe

105

260
360

o

25

·These symbols are described in IEEE Std. 662-1980: IEEE Standard Terminology for Semiconductor Memory.

FUJITSU

1·87

M881418.10
M881418·12
M881418·15

AC Characterlatlcs
(Continued)

Notes:
1. An Initial pause of 2oo!'5 is required after
power up, followed by any 8 FiAS cycles,
before proper operation Is achieved. If the internal refresh counter is to be effective, a
minimum of 8 CA8-before-FiAS initialization
cycles instead of 8 RAS cycles are required.

7. tACo (min.)
tT = 5ns.

8. t wes, tCWD and tRWD are non-restrictive

operating parameters. They are included in
the data sheet as electrical characteristics only. If twcs'" twes (min.), the cycle is an early
write cycle and the data out pin will remain
open circuit (high impedance) throughout the
entire cycle.
If t CWD '" tCWD (min.) and t RWD ", tRWD (min.),
the cycle is a read-write cycle and data out
will contain data read from the selected cell. If
neither of the above sets of conditions is
satisfied, the condition of the data out is Indeterminate.

2. AC measurements assume tT = 5ns.
3. VIH (min.) and VIL (max.) are reference levels
for measuring timing of input signals. Transition times are measured between VIH (min.)
and VIL (max.).
4. t RCD is specified as a reference point only. If
t RCD s t RCD (max.) the specified maximum
value of t RAC (max.) can be met. If t RCD > t RCD
(max.) then t RAC is increased by the amount
that t RCD exceeds t RCD (max.).
5. Assumes that t RCD '" t RCD (max.).
6. Measured with a load equivalent to 2 TIL
loads and 1oopF.

=tRAH (min.) + 2tT + tASC (min.):

9. Either tRRH or t RCH must be satisfied for a read
cycle.
10. Refresh counter test cycle only.
11. Either t DZC or tozo must be satisfied for all
cycles.

Read Cycle

Timing Dlagrama

~-------IRC'----.,----+I

RAS

V,"
V"

CAS V,"
V"

V,"
V"

W

V,"
V"

DATA VOH
(OU1) VOL

DATA YOH
(IN)

VOL

G

V,"
V"

Write Cycle (Early Write)
G = Don't Care
RAS

CAS

v,"
v"
v,"
V"
V,"
V"

'Ii

V'H
V"

DATAVIH
(1M) VIL

OATA VIH
(OU1) VIL

HIGH.z

FUJITSU
1-88

~Donltc.r.

MBa141a·10
MBa141.·1.
MBa141.·1.

Timing DI.gr.ms
(Continued)

Writ. Cycl.
(Output Enable Controlled)
~----------------------IRC----------------------~
~------------------I~------------------~

--~----------~~----------~

A

DATA

(IN)

DATA
(OUT)

Nott1: When tcwo is satisfied and Gis low (Delayed-Wrlte Cycle), the data out will be "VAUO", But when

tcwo is not satisfied, the data out will be

"INVAUO",

R••d.Wrlt.' ....d·Mcdlfy·Wrlt. Cycl.

A

DATA
(IN)

DATA
(OUT)

~Don'tCare

FUJITSU
1·89

••• 141 .. 10
••• 141 •• 1 •
. . . 141 .. 1.

Tlmln.DI....._
P•••• od. RNd Cycl.

(Continued)

RAS

IRAS

VIH
VIL

CAS

IRSH_~

ICAS

VIH
VIL

A

VIH
VIL

Vi

VIH
VIL

DATA

VIH

6N)

VIL

DATA
(OUT)

Q

VOH
VOL
V,H
V,L

P••• Mod. Writ. Cycl.
(G = Don't Care)
IRAS

RAS

VIH
VIL

.=pRSH

CAS

VIH
VIL

A

VIH
VIL

Vi

VIH
V,L

DATA
(IN)

DATA
(OUT)

VIH
VIL
VOH
HIGH·Z--fI

VOL

~Don'Ic...

FUJITSU

1·90

M881418-10
M881418-12
M881418-18

Tlmln. Dla.ram.
Pa •• Mod. R. .d-Wrlt. Cl'cl.

(Continued)

A

DATA
(IN)

DATA
(OUT)

G

RAS Onll' R.fr•• h Cl'cl.
W, G = Don't Care

NOTE: CAS = VIH : A7 ,

VIH
RAS

VIL

VIH
A

VIL

DO

VOH
VOL

HIGH-Z

CAS-8.for.-RAS R.'r•• h Cl'cl.
NOTE: A, W, G = Don't Care

-

_ _ _ _ _ _ _ _ _ _ _ _ HIGH_Z _ _ _ _ _ _ _ _ _ _ _ __

DO

~

FUJITSU
1-91

Don't Care

. . . 1418·10
. . . 1418·1 •
••81418·1.

Timing Diagram.
(Continued)

Hidden .......... Cwole
I_----I.c-----;~"">-----

VI.

_+--;-;-_+.
1"'l'----+-----------''f'1

V"

xxxbxxx

1-,1...

VI.
V"

DATA

VALID DATA OUT

(OUT)

~:zl~X1~~-----HIGH.Z-------

DATA
~N)

cas-....,..D8 Rof,..h Coun.... Tnt Cwole
iiAi

CAS

V,.

~----------------~-----------------~

VIL
VI.
VIL
V,.

A
VIL
_

VIH

W(READ)

VIL

DATA
(READ)
~N)

DATA
(READ)

lOUT}

t~1

XXXxxxxxxxxxxxt II

::xxxx4f-

II @

H~H~---+~~~~~

HtGH.Z~11~~W:--

VOL
VI.

GCREAD)

VIL

DATA

YOH

(OUT)

VOL

(WRIT£)

------HIGH·Z---+---(]

Note 1: When tewD Is satisfied and G is Low (Delayed·Write Cycle), the data out will be "VALID". But when
tewD is not satisfied, the data out will be "INVALID".

FWITSU
1-92

MB81418·10
MB81418·12
MB81418·15

Description

Address Inputs
A total of 14 binary input address bits are needed to decode
anyone of 16,384 nibble wide
words from the MB81416's
65,536 memory cells. Addressing a Random 4-bit word
is initiated by establishing 8
row address bits on the address input pins, (Ao through
A7), and after they are stable,
latching these address bits with
the falling edge of the Row Address Strobe (RAS). Then 6 column address bits are established on the address input pins A,
through A6 . After the addresses
are stable, they are latched with
the falling edge of the Column
Address Strobe (CAS). Address
timing is made non-critical by
the MB81416's "gated CAS" circuitry which automatically inhibits CAS until the Row Address Hold time (t RAH) has been
satisfied and the address inputs have changed from row to
column addresses.
Data InputJOutput
The MB81416 has 4 common
1/0 pins (DO" 0°2, 0°3, and
004), Read or write modes are
selected with the write enable
pin i!N'J. An output enable pin
(G) controls the state of the output buffers making delayed
write and read-modify-write
cycles possible. The DO pins
provide TIL compatible inputs
and three-state TIL compatible
outputs with a fan-out of two
standard TIL loads. Data-out
has the same polarity as datain.
Write Enable
The read mode or write modes
are determined by the state of
the write enable pin i!N'J. A logic
high on IN selects the read
mode and a logic low on IN
selects the write mode. When
IN is high (read mode), the data
inputs are disabled. If IN goes
low and satisfies the write command set-up time (t wcs) before
CAS goes low, the data outputs
will remain in the highimpedance state for the duration of the cycle. This allows a
write cycle to occur regardless

of the state of the output
enable (G).
Output Enable
The output buffers are controlled by both CAS and output
enable (G). If either CAS or G
are high the output buffers are
in the high impedance state.
During a read or read-modifywrite cycle if both CAS and G
are low, the output buffers are
enabled. During an early write
cycle G has no effect on the
output buffers.
Data Inputs
Data may be written into the
MB81416 during a write or readmodify-write..9'9le. 'I!l.e last failing edge of CAS or W, strobes
the data into the 4 on-chip data
latches. In an early-write cycle,
IN is brought low prior to CAS,
and the data is strobed in by
CAS with both the set-up time
(tos) and hold time (t OH ) referenced to the falling edge of
CAS. The outputs are in the
high impedance state
regardless of G's state. In a
delayed write or a read-modifywrite ~e, IN is brought low
after CAS, data is strobed-in by
IN, and set-up and hold times
are referenced to W. To avoid
buss contention on 1/0 pins, it
is necessary during a delayed
write or a read-modify-write cycle for G to be high prior to
data input so that the output
buffers are in the high impedance state when data is being
written.
Data Outputs
Data can be read from the
MB81416 with either a read or a
read-modify-write cycle. These
cycles begin with the outputs in
the high impedance state. The
outputs contain activ~alid _
data only after both CAS and G
have been brought low and
have satisfied the minimum access time from RAS (tRAd and
the minimum access time from
the output enable tOED' Outputs
contain valid data as long as
both CAS and G are held low.
They return to the high impedance state when either CAS
or IT go high.

• Note: CAS Before RAS refresh available on request.

FUJITSU

1-93

RAS-Only Refresh
The MB81416's dynamic
memory cells may be refreshed
by performing any memory cycle at each of the 128 row addresses (AD through ~ at least
every 2 milliseconds. When a
row is accessed all bits in the
row are refreshed. During
refresh, A7 (Pin 10) is not used
and either V1H or V1L may be applied to this pin.
RAS-only Refresh is a simplified
cycle that consists of strobing
a row address with RAS while
CAS remains high. Durin~
RAS-only Refresh cycle, CAS is
high and the output buffers are
in the high impedance state.
Strobing each of the 128 row
addresses (Ao through AtY with
RAS will refresh all 65,536
memory cells in the MB81416.
RAS-only Refresh results in a
substantial reduction in power
dissipation compared to a full
RAS/CAS memory cycle.

CAS Before RAS Refresh'
CAS before RAS refreSh is an
on-chip refresh capability that
eliminates the need for external
refresh addresses. If CAS is
held low for the specified set-up
time (tFCs) before RAS goes
low, the on-chip refresh control
clock generators and refresh
address counter are enabled.
An internal refresh operation
automatically occurs and the
refresh address counter is internally incremented in preparation for the next CAS before
RAS refresh operation.

Hidden CAS Before RAS
Refresh
A hidden refresh cycle may be
performed while maintaining
the latest valid data at the output by extending the CAS active time and cycling RAS. The
refresh row address is provided
by the on-Chip refresh address
counter. This eliminates the
need for the external row address that is required by
DRAMs that do not have CAS
before RAS refresh capability.

• • • 1418-10
• • • 1418-12
• • • 1418-18

DHcrlptlon,
(Continued)

CAS Before "AAS Relrash
Counter Test Cycle

Suggested CAS Before RAS
Refresh Counter Test Procedure

A special timing sequence us·
Ing the 00 before RAS
Refresh Counter Test Cycle provides a convenient way to verify
the functionality of the CAS
before RAS refresh circu~
The cycle begins with a CAS
before RAS operation. Then
CAS is cycled "high" and then
"low". This enables a read,
write, or read·modify·write
operation to occur. Four
memory cells are accessed with
the location defined as follows~

The CAS before RAS Refresh
Counter Test Cycle timing is us·
ed in each of the following
steps:
1. Initialized the internal refresh
counter by performing 8
cycles.
2. Write a test pattern of
"lows" into each set of 4
memory cells at a single col·
umn address and 128 row
addresses. (The row ad·
dresses are supplied by the
on-chlp refresh counter.)
3. Using read·modlfy·write
cycles, read the "lows" writ·
ten during step 2 and write
"highs" into the same
memory locations. Perform
this step 128 times so that
"highs" are written into the
128 sets of 4 memory cells.
4. Read the highs written duro
ing step 3.
5. Compliment the test pattern
and repeat steps 2, 3, and 4.

Row Address Bits Ao through As are sup·
plied by the on-chip refresh
counter. Bit A7 Is set low Inter·
nally.
Column Address Bits A, through As are
strobed·in by the falling edge of
CAS as In a normal memory cy·
cle.

Page Mode
Page mode memory cycles provide faster access and lower
power dissipation than normal
memory cycles. In page mode,
It Is possible to read, write, or
read·modify·write. As long as
the applicable timing reo
quirements are observed, it is
possible to mix these cycles in
any order. A page mode cycle
begins with a normal cycle.
While RAS is kept low to main·
tain the row address, CAS is
cycled to strobe in additional
column addresses. This
eliminates the time required to
setup and strobe sequential
row addresses for the same
page. Up to 64 nlbbl.e wide
words may be accessed with
the same row address.

TypIcal Characterl.tlc.
Curve.
CURRBNTWAVEFORM (Vcc

RA!ICQ CYCLE

LONG ~w CYCLE

~

5.5V, TA

m-ONlY REFRESH CYCLE

~

25'C)

PAGE MODE CYCLE

CAS.BEFORE.J(A§ REFRESH CYCLE

~·~moo~~moo~~mM~m

O1!mlBllllliliERlililili1i

'80

°_l1li_ _ __

'80

.

12
J80

1

santlDlYlllon

FUJITSU

1-94

••8141 .. 10
. . . 1418.1 •
. . . 1418·18

TypIc" C...r.ct.....tlc.
Curv. .
(Continued)

NORMALIZED ACCESS TIME
VI SUPPLY VOLTAGE

NORMALIZED ACCESS TIME
AMBIENT TEMPERATURE

v,

J

TA "2s"C_

2

'-.

1

tACO'" 20ns

~

.............

vcJ4J

w
:;;

>=
:g

1.2 ' - -

tAco"'20ns . /

w

""«c

-

w

1.1

/v

1.0

N

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V

V

«
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5.5

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OPERATING CURRENT
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.5
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50

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30

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20

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....
iiia:

tAAS -100ns..

.. V

a:

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a

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51-

'z"

a:
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w

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..

25

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2D
-10

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0

2D

40

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60

SO

TA.AMBIENTTEMPERATURE ('C)

FV.n'I'BU

1·95

l-'

5.5

VI

-

0

trC"~n.

I"-

0

j

./

5

~
3D

.

T)25'C

tR~S' 101"'_

I-...

Z

v.

tRC· 20001

STANDBY CURRENT
SUPPLY VOLTAGE

- tors
--

;(

so

TA -'2s"C

4.5

OPERATING CURRENT ..
AMBIENT TEMPERATURE

a:
a:

60

VCC.SUPPLY VOLTAGE (V)

1/tRC. CYCLE RATE (MHz)

I-

40

40
5

~

o
o

.5

20

OPERATING CURRENT
SUPPLY VOLTAGE

I-- I-TA _25°C

a:
a: 40

«
a:

v.

VC~· 5.5~

;(

0

100

T A • AMBIENT TEMPERATURE rC)

Vee. SUPPLY VOLTAGE (V)

5

0
100

4.5

5.5

Vee. SUPPLY VOLTAGE tV)

MB81418·10
MB81418·12
MB81418·1S

Typlca. ~haracterl.t'c.
Curve.
(Continued)

STANDBY CURRENT VI
AMBIENT TEMPERATURE

"<
5

vr'51

3.5

!zw
a:
a:

o>

.

r-.

2.5

Q

~
j

REFRESH CURRENT 1
CYCLE RATE

"<

- ---

1.5

5

....

z
w

a:
a:

vdc·

tFlAS ·100ns

40

'"

30

w

..

20

II'"

10

'"wa:

o

0
20
40
60
80 100
TA.AM8IENTTEMPERATURE reI

ifi2
5
a:
a:

020
:I:

.
ffl
a:

15

--

"<

~

V

20

w

'"

15

a:

10

-

rr- f -

tAC· 200",
tAC -260ns

;rc:-; 0".-

G

.9
5.5

4.5

Vee. SUPPLY VOLTAGE (VI

1....

30 f - - I c . l .5v
TA·25"C

w

25 _tCAS-SOns

'"

20

Q
Q

:IE 15

V

w

10

I7'

l/

-20

20

40

50

-

/

80

VI

~5"C

--- TA '

tpc -

10Sn.

u

.9

o

4

6

10

1'tpe. CYCLE RATE (MHz)

FUJITSU

1·96

100

T A. AMBIENT TEMPERATURE rCI

PAGE MODE CURRENT
SUPPLY VOLTAGE

PAGE MODE CURRENT vs
CYCLE RATE

."<.

'"

il:w

0 10

w

25

:I:

.9

a:
a:

30

zw

;:
()

w

()

5

a:
a:

a:

z

6

4

REFRESH CURRENT 1 VI
AMBIENT TEMPERATURE

I

TA' 25"e
TRC" 200ns

V

1/tFlc. CYCLE RATE (MHz)

REFRESH CURRENT 1 vs
SUPPLY VOLTAGE

5301--....

...

V

a:

-20

"<

5.~V

f-- -TA" 25"e

50

:I:

()

v,

4.5

5.5

Vee. SUPPLY VOLTAGE (VI

.. 881418·10
..881418·12
.. 881418.18

Typical Characteristics
Curves
(Continued)

PAGE MODE CURRENT VI
AMBIENT TEMPERATURE

oS

J

VCC·S.5V
tCAS· SOnl

;(

30

REFRESH CURRENT 2
CYCLE RATE

tpc

:<

.

!

-105".

w
a: 25
a:

::>

"

w
0
0

20

~~

l:

20

w

Ifw

w

~

~tRAS-100ns

::>

."

:; 15

~

~ve~'5.L
TA' 2S"e

w

a: 25
a:

_ _ ,,"C' l SO N

t--

30

IZ

IZ

.

15

V

a:

10

u 10

0

20

40

60

80

t A. AMBIENT TEMPERATURE
REFRESH CURRENT 2
SUPPLY VOLTAGE

:<

30 TA' kS"e

ffi

25

G20

iJi
~

(Oe)

1/tRC. CYCLE RATE (MHz)

v,

REFRESH CURRENT 2 VI
AMBIENT TEMPERATURE

oS
N

TRC" 200n•

I-

a:
a:

100

V~e·5.~V

;(

..

!

...-

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.

4.5

tRC -300ns

~

10

I I

-20

TA • kS"e
0

0

:l~

VIHlmin),:::;

I-- ~

1-97

80

100

6

5.0
Vee -5V

=~

g5

3.0

1~
Oz

2.0

VIH(min) -

1.0

VILTaxl

~~

".>

....
z-

"I-

FUJITSU

I I

60

4.0

>~

5.5

40

ADDRESS AND DATA INPUT
VOLTAGE VI AMBIENT
TEMPERATURE

4,0

4.5

20

T A,AMBIENT TEMPERATURE rei

ADDRESS AND DATA INPUT
VOLTAGE VI SUPPLY VOLTAGE

Vee, SUPPLY VOLTAGE (VI

I

15

Vee, SUPPLY VOLTAGE (VI

--

I

Ifw

""

5.5

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20

a:

4

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tRC" 250n5

"w
l:

w

0

tRC" 200n.

w
a: 25
a:

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a:
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0

II II

30 r--tRAS· 100ns

IZ

15

0

V

v'

V

J!

J!

20

VI

o

-20

20

40

60

60

TA,AMBIENTTEMPERATURE rei

100

.881418.10
.881418·12
.881418.15

Typical Characteristics
Curve.
(Continued)

AU, CU, WE AND DE INPUT
VOLTAGE VI AMBIENT TEMPERATURE

Rn, en, WE
VDLTAGE

VI

AND DE INPUT
SUPPLY VOLTAGE

4.0

..
o
z

I~

TA

4.0

J

3.0

13~
_w

~ 5i
I0:1-

vcd.sv

2SoC

V,HCMin)_

V'HIMinl-----:

2.0

-I

-""'
;»
-'0

-

1

VOLIMax)

V,LIMax)

C .... 1.0

~~
~I~

4.5

5.5

o

6

-20

SUPPLY CURRENT

~~

~~ :[71 1 1 1 1 I

,?g

T A -2S0C

20
5

V

I
r

I I I

J.l.J-vss
I

1

20

40

60

80

TA' AMBIENT TEMPERATURE

vee,SUPPLY VOLTAGE IV)

1

11 I
I T I
I Tl

itli$-eAS=OE-vee-

101'l/Dlvision

FWITSU

1·98

VI

SUPPLY VOLTAGE DURING POWER UP

100

re)

• •81418·10
• •81418·12
••81418·15

Typical Characteristics
Curves
(Continued)

SUBSTARATE VOLTAGE
v. SUPPLY VOLTAGE
DURING POWER UP

i.I:1
~g

l/ 1
1\

1 1 1 I
I

TA - 25"C

1'IAS'.~-l5'E.vcc

\
i\.

....

5O",s/Divjsion

CURRENT WAVEFORM DURING POWER UP (ON MEMORY BOARD)

>->

\~ :0 I I I I I

»

"<
.§
I-

100~~~--~-4---+--~--~

i85~ 5[/1 I I 1 I I
0

"<

tAC'" 200"5

.§ 8

80

I-

a:
a: 60

:l!a:

w

Z

:J

>-

..J

'"U

6

:J

'-'

:J

01.

TA "25"C -

Z

..

1

> >10

Of'
Jl h

'-'4

40

~

i

~.. 2

20

.9

0

10J' Division

FUJITSU

1-99

~'!a8c~::r6(~.f:~fuPlinr
~~~~)I!:;,~ycapalitor
100",,/Division

••• 141.·10
••• 141.·12
••• 141 •• 11

Packa•• Dlmanalona
Dimensions in inches
(millimeters)

1.·....d C.nllp
Dual In·Lln. Paoka ••
DIP·1.C·C01

1.·Lead Plaatlc
Du.1 In·Lln. Packa ••
DIP·1.P·M01

...__---;_""''''''::::..,...0"-'5"
INDEX

1·100

...81418·10
...81418·12
...8141 .. 11

P.ck••e Dimensions
(Continued)
Dimensions in inches
(millimeters)

18-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
(CASE No_: LCC-18C-F02)
*PIN NO 1 INOE

/

A.012!O.30ITVP
14 PLeSI

.1125(2.86)
TVP

6

.420(1 0.67)
.435(11 .051

.02510.641
TVP

r
.045(1.14)

TVP

.28017.111
.29517.491

.067511.711
TVP
,195(4,95)TYP

"Shape of Pin 1 index: Subject to change without notice

1·101

Preliminary

FUJITSU

MOS Memories
•

MB81461-12, MB81461-15
NMOS 262,144-Bit Dual Port
Dynamic Random Access
Memory

De.crlptlon
The Fujitsu MB81461 is a fully decoded dual port dynamic NMOS
random access memory organized as a 65,536 word by 4-blt dynamic RAM port and a 256 word by 4-bit serial access memory
(SAM) port .
The DRAM port is identical to the Fujitsu MB81464 with four bit
parallel random access I/O while the SAM port is designed as four
256-blt registers each operating as a serial I/O. The four serial regIsters operate In parallel with each other during SAM port operation. Internal interconnects give the device the capability to transfer
data bi-directionally between the DRAM memory array and the
SAM data: registers.
The MB81461 offers completely asynchronous access of both the
DRAM and SAM ports except when data is being transferred between them internally.

•

-

- i j

-

.~

The design is optimized for high speed and performance which
makes the MB81461 the most efficient solution for implemE!nting
the frame buffer of a bH-mapped video display system. Multiplexed
row and column address inputs perrnitthe MB81461 to be housed
in a 400 mil wide 24 pin Dual-Inline-Package.
The MB81461 is fabricated using silicon gate NMOS and Fujitsu's
advanced Triple layer Polysilicon process technology. This process, coupled wHh single-transistor memory storage cells, permHs
maximum circuH densHy and minimum chip size.
All inputs and outputs are TTL compatible.

• Dual Port organization
64K x 4 Dynamic RAM Port (DRAM)
256 x 4 SerIal Acceaa Memory Port (SAM)
•

DRAM Port
Acceas 11me (tRAe)
Cycle 11me (tRe)

MB81461-12
120 ns max.
230 ne min.

MB81461-15
150 ns max.
260 ns min.

•

SAM Port
Acceas Time ('sAe)
Cycle 11me (tee)

MB81461-12
40 ns lIIax.
40 nsmln.

MB81461-15
60 na max.
60 ns min.

•

Low Power Dissipation
DRAM Port Active
SAM Port Active
Both Ports Standby

MB81461-12
523 mW max.
275 mW max.
110mWmax.

MB81461-15
468 mW max.
220 mW max.
110 mW max.

1-102

• Single +5V supply voltage, +/-10%
toleranca
• BI-dlrectlonal Data Transfer betWesn
DRAM and SAM
• Fsat serfal s _ asynchronous to
DRAM except transfer mocie operation
• Real11me Read Transfer capability
• Read-Modlfy-Wrlte capability
• Page mode capability for faster a _
• Bit Mask Write mode capability
• Refraah 4 ms{256 eycl..
• AAS-only refresh
• CXl-before.RU on chip refresh
• All Inputs and outputs TTL compatible
• 24 pin 400 mil wide plastic package

~ DI.....m of M881481
IIIId PIn As8lgnm.nt

A.

SAS-==~=~~~

Soo

Pin Number

Symbol

Parameter

1

SAS

Serial access
memory strobe

2,3,22,23

Sooto
SD3

sa~al

4

TR/CE

Transfer enableJ
output enable

5,6,19,20

to

MOO/DOG
MD3/0Q3
7

iiE/W

da1a I/O

Mask datal

I/O

Input

Mask mode enablel

S02

SD3

SAS

Vss

SOO

S03

SOl

TR/Ce
MOO/OQO

UO

M01/DQl

Me/W
Input

14,15,16,17

ArrA7

Address Input

12

Vee

Supply yoltage +5V

18

CAS

Column address

21

SE

Serial port enable

24

VSS

Ground

Input
Input
Power

supply

Input

strobe

1-103

Input
Power

supply

S02

liE
M03/0Q3
M02/DQ2
CAS
AO

write enable

RAS
9,10,11,13

Input

data uO

Rowaddl'888
strobe

8

SOl

A6

Al

AS

A2

A4

A3

Vee

A7

MB81461·12
MB81461·15

Absolute Maximum Ratings
Rating

Symbol

Value

Unit

Voltage on any pin
relative to V55

VIN' VOUT

-1 to +7

V

Voltage on Vee
relative to Vss

Vee

-1 to +7

V

Storage
Temperature

T STG

-55 to +125

'C

Power Dissipation

PD

1.0

W

50

mA

Short Circuit
output current

DRAM Operation
RAS;
This pin is used to strobe eight
row-address inputs from Ao to A7
and is used to select the operation mode of subsequent cycle,
such as DRAM operation or
transfer operation (by TRIO E)
and bit mask write cycle or not
(by ME/Wand MDO/DQO to
MD3/DQ3). Since RAS = "I.:' is
the active condition of circuit,
maintaining RAS = "H" (Standby
condition) lowers power
dissipation.
CAS;
This pin is used to strobe eight
column addres~uts at the failing edge. The CAS pin also functions to enable or disable the
output at "I.:' and 'H' respectively
during the read operation.
Another function of CAS is to select "early wril!r mode conditioned by MEIW = "I.::
MEliN;
This pin is used to select read or
write cycle. MEliN ="":':1.:' selects
write mode and MEIW = "H" selects read mode. This pin is also
used to enable bit mask write
cycle. If MEliN = "I.:' at the falling
edge of RAS, bit mask write is
enabled.
TR/OE;
This pin is used to select Transfer operation 0l1!0t at the falling
edge of RAS. TRIOE = "H"
enables DRAM operation and
TRIOE = "I.:' enables Transfer
operation between DRAM and
SAM. After the falling of RAS
with tyH , this pin is used for output enable.

The TRIOE controls the impedance of the output buffers.
TRIOE = "H" forces the output
buffers to high impedance state.
TRIOE = "I.:' brings the output
buffers to low impedance state.
However, in early write cycle, the
output buffers are in high impedance state even if TRIOE is low.
Ao to A7;
These are multiplexed address
input pins and used to select 4
bits of 262,144 memory ceillocations in parallel within the
MB81461. The eight row address
inputs are strobed by RAS and
the following eight column all:....
dress inputs are strobed by CAS.
These inputs are also used to select the start address of serial access memory.
MDO/DQO to MD3/DQ3;
These are common 1/0 pins of the
DRAM port. 1/0 mode is as specified for each functional mode in
the truth table.

Data Outputs;
The output buffers have threestate capability, "H'; "t:' and
"High-Z': To get valid output data
on the pins, one of the read operations is selected such as "readmodify-write" mode. During a
refresh cycle, if RAS-only or
CAS-before-RAS mode is
selected, output buffers are set in
"High-Z" state.
Data Inputs;
These are used as data input
pins when a data write mode
such as "Early-Write';
"OE-Write" or "Read-modifywrite" is selected. In any of the
above cases, these pins are set
at high-Z state to enable data-in
without any bus conflict.

1-104

In any operation mode; read,
write, refresh, transfer and their
combined functions, output states
"H'; "I.:; "Hi~' are set by..£.ontrol signals RAS, CAS, MEIW
and lor TR/OE. When "Bit mask
write" mode is set, these pins are
used as a control signal for inhibit
with MDi/DQi = "t:' on selected
bit i.
Page Mode;
The page mode operates by
strobingJtle column address
while RAS is maintained at "t.:'
through all the accessive memory
operations if the row address
doesn't change. This mode can
lower power dissipation and improve access time due to elimination of RAS function.
Refresh;
Refresh of the DRAM cells is
performed for all 256 rows every
4 milliseconds.
The MB81461 offers the following
thre~pes of refresh.
_
1) RAS-Only refresh; The RASQn!y refresh is performed with
CAS = "H" condition. Strob~all 256 row addresses,
RAS will complete all bits of
memory array to be refreshed
while all outputs are invalid
due to "High-Z" state. Further,
RAS-only refresh lowers
power dissipation substantially.

MB81481·12
MB81481·15

DRAM Operation
(continued)

2 CAS·before-RAS refresh; The
CAS-before-i'iA§ refresh offers
an alternate refresh method. If
CAS is set low for the specified period (tFcslJ>efore the
falling edge of~, refresh
control clock generator and refresh address counter are enabled, and a refresh operation
is performed. Aller the refresh
operation is performed, the refresh address counter Is incremented automatically for the
the next CAS-before-RAS
refresh.

3 Hidden refresh; The hidden refresh is performed by maintaining the valid data of last
read cycle at MD/DO pins
while extending CAS low. The
hidden refresh is equivalent to
CAS-before-RAS refresh because CAS stays low when
RAS goes low in the next
cycle.

mode is executed by selling
ME/W = "t.:' at the failing edge of
RAS during write mode (early,
C5E-wr~e or read-modify-wrlte
cycle). The b~s to be masked (or
inhibited to write) are determined
by MD/DO state at the falling
edge of RAS. For example, if
MDO/DOOand m::/iNare both low
at the falling edge of RAS, the
data on MDO/DOO pin is not written into the cell during the cycle.
wr~e

Bit Mask Write;
This mode Is used when some of
the bits should be inhibited to be
wrillen into cells. The bit mask

Example of Bit Ma.k Write
Operation
FALUNG EDGE OF RAS
FUNCllON
TR/OE

M02/0Q2

MEJW

Moo/DQD

MD1/OQl

MD3/OQ3

H

X

X

X

X

WRITE ENABLE

L

H

L

H

L

WRITE ENABLE FOR DQD AND DQ2
WRITE DISABLE FOR 001 AND OQ3

H

X:

Functional Truth Table for
DRAM Operation

lID

CAl

iIi/w

fIi/mi

Addre••

DQOto DQ3

Function

H

H

X

X

X

X

Standby
Read

~ON'T

CARE

L

L

H

H-L

Valid

Valid Data Out

L

L

L

H-X

Valid

Valid Data In

Early Write

L

L

H-L

H-+X ... H

Valid

Valid Dala In

DE-Write

L

L

H-L

H-L-H

Valid

Valid Data Out
-Valid Data In

Read-Modify-Write

L

H

X

H-X

Row address

High-Z

RAS-Only Refresh

H-L

L

X

H-X

X

High-Z

CAS-before-RAS Refresh

Transfer Operation
The transfer operali~n featured in
the MB81461 is used to transfer
256x4 data from DRAM to SAM
or from SAM to DRAM. The direction of transfer is determined
by the state of ME/iN at the falling
edge of RAS. ME/Vi = "H" defines the transfer from DRAM to
SAM.JRead Transfer Cycle} and
ME/W = "t.:' defines the transfer
from SAM to DRAM (Write Transfer Cycle).
I/O mode of SDO to SD3 is determined while the transfer operation is set (TR/OE = "t.:') in
conjunction w~h ME/iN state.

'm/C5E;
This pin is used to enable transfer~ratlon at the failing edge
of RAS. TR~ = "t:' enables the
transfer operation.

ME!W;
This pin is used 10 select the direction of transfer althe falling
edge ofRAS.

Ao to A7;
These pins are used 10 select the
row address of DRAM port to be
transfered from or to, and the
start address of SAM port for the

FUJITSU
1-105

serial read or write operation.
The row address is strobed by
RAS and the start address is
strobed by Q\S.
Pseudo Write Transfer;
To start serial write cycle, the SO
pins must be set to input mode.
To do this, a write transfer cycle
should be executed. This pseudo
write transfer cycle changes the
SO pins to input mode without
data transfer from SAM to
DRAM.

MB81461·12
MB81461·15

Serial Access Operation
The MB81461 has a 256 word by
4-bit Serial Access Memory
(SAM) corresponding to the 64K
word by 4-bit DRAM. The fast serial read/write access feature is
achieved by this SAM architecture. Read or write cycle is determined by the last transfer
operation. If the last transfer operation was read transfer, the serial port is in the output mode
until the next write or pseudo
write transfer cycle is executed.
On the other hand, if the last
transfer operation was wr~e or
pseudo write transfer, the serial
port is in the input mode. In the
serial write operation, 256 word
by 4-bit data stored in the SAM
can be transferred to the DRAM
under SE = "t:' condition. The
SE = "H" condition disables data
transfer from SAM to DRAM. The
serial access operation can run
asynchronously from the DRAM
port.
SAS;
This pin is used as a shift clock
for SAM port. The serial access
is triggered by the rising edge of
SAS. In the write cycle, the data
on the SD pins are strobed by
the rising edge of SAS and wr~
ten into the selected cell. In the

Functional Truth Table tor
Serial Acce••
(Asynchronous from DRAM
port)

read cycle, output data become
valid after tSAC from the rising
edge of SAS and the data remain
valid until the next cycle is defined. The SAS clock increments
the SAM address automatically.
When the SAM address exceeds
#255 (Most Significant Address)
it returns to #0 (Least Significant
Address).

Refresh;
SInce the SAM is composed of
dynamiC memory cells, refresh is
necessary to maintain the data in
~. The refresh of SAM must be
done by 256 cycles of SAS
clock/4 ms in e~er output or input mode. SE = "H" allows refresh of SAM with SD pins at
"Hlgh-Z" state.

SE;
This pin is used to enable serial
access operation. SE = "H" disables serial access operation. In
the serial read operation, this ~
is used for output enable, i.e., SE
= "H" drives SD pins to "High-Z"
state. SE = "t:' drives SD pins to
valid data with specified access
time. In the serial write operation,
this pin works as write enable
control pin.

Real Time Read Transfer;
This feature is used to obtain
continuous valid dsta output
when the row address is
changed. Data flow Is continuous
from the last b~ of the previoils
row to the first b~ of the new row
with no timing loss. Data transfer
irom DRAM to SAM is triggered
by the rising edge of TR/OE after
the preparation of internal cirellitry for this operation. The SAM
port can continue Its read operation asynchronoUsly from the
above mentioned Internal 0peration. Once 'i'R/aE returns to "H"
with the restricted timing speciflcations tTSL and tTSO referred to
SAS clock, SD pins cen output
valid data continuously. The key
to achieving this feature is to apply the SAS clock continuously
while giving consideration to the
timing requirements referenced
to the rising edge of maE.

SDOtoSD3;
These are used as data Input/
output pins for SAM port. Inpui or
output mode is determined by the
previous transfer operation. If the
previous operation was read
transfer mode, they are in output
mode. If the wr~e transfer mode
was set, SD pins are enabled to
write data into SAM.

Failing edge of iiAi

'I'II/OE
H

IIIE/W

SDOtoSDa

SAS

x

L

Input/output·

Sequential access enable

Clock

H

Input/output·

Sequential acceSs dsabllt

NOTE: • The read or write operation of SAM port is pre-determined by the IB8t occurred
Output mode is for read operation.
X; OON"TCARE

Rec_mended Operating
Condition.
(Referenced to VsS>

Func....

Clock

tranBfa' cycle: Input mode

Parameter

Symbol

.Mln

Typ

Mill(

UnH

Supply voltage

Vee
Vss

4.5
0

5.0
0

5.5
0

V
V

Input high voltage

V1H

2.4

6.5

V

Input low voltage

V1L

-2.0

0.8

V

1-106

is for write operation.

...........

~
O·C to +70*c

MB81481·12
MB81481·15

Capacitance
(TA = 25'C)

Parameter
Input capacitance

Symbol

(Ae to A7)

Input capacitance ("FiAS, CAS", W, m)

Max

Unit

7

pF

CIN2

8

pF

CIN3

10

pF

Input/output capacitance (000 to 003)

CI01

7

pF

Input/output capacitance (SOO to S03)

CI02

7

pF

Input capacitance

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Typ

CIN1

U!!Y 8 RAS and SAS cyoles before proper devlce.-!'l1.erallon 10

achieved, When using internal refresh counter, 8 minimum of 8 CAS-before-RAS Initialization cycles instead of 8 RAS cycles Is
required.
*2 AC characteristics assume tr = 5 ns.
*3 VIH (min.) and VIL (max.) are reference levels for measuring timing of Input signals. Also. transition times are measured between

VIH (min.) and VIL (max.).

*4 Assumes that tRCO os;; tRCO (max.). If tRCD Is greater than the maximum recommended value shown in this table. tRAe will be Inaeased by the amount that tRCD exceeds the value shown.
'5 Assumes Ihe tRCD .. tRCD (max.).
*6 Measured with a load equivalent to 2 TIL load and 100 pF.
'7 Operation within the tRCO (max.) 1m" insures that tRAC (max.) can be met. tRCD (max.) is s~ed as a referance point only; W
tRCD is greater than the specified tRCO (max.) limit, then access time Is conb'olled exclusively by tCAC-

'8 tRCD (min.)

-

tRAH (min.) + 2IT + tASC (min.).

1-108

MB81481·12
MB81481·15

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

CAS to RAS set up time

IeRS
tASR

Row address set up time

MB81461·12
Min
Max

MB81481·15
Min
Max

10

10

ns

0

0

ns

Unit

Row address hold time

tRAH

12

15

ns

Column address set up time

tASC

0

0

ns

Column address hold time

icAH
t RCS

20

25

ns

Read command set up time

0

0

ns

Read command hold time
referenced to RAS'10

tRRH

20

20

ns

Read command hold time
referenced to eJi;S'10

tRCH

0

0

ns

Write command set up time

twcs

-5

-5

ns

Write command hold time

tWCH

30

35

ns

Write command pulse width

twp

30

35

ns

Write command to RAS
lead time

t AWl

40

45

ns

Write command to CAS
lead time

tCWl

40

45

ns

Data in set up time

tos

0

0

ns

30

Data in hold time

tOH

Access time from OE'6

tOEA

OE to data in delay time

toED

25

tOEZ

0

Output buffer turn off delay
fromOE

ns

35
40

35

ns

30
25

0

ns

30

ns

DE hold time referenced to WE

tOEH

0

0

ns

OE to RAS inactive set up time

tOES

0

0

ns

Data in to CAS delay time

tozc

0

0

ns

Data in to OE delay time

tozo

0

0

ns

Refresh set up time for ~ referenced to
before RAS)

tFCS

25

30

ns

Refresh hold time for ~ referenced to RAS (~before RAS)

t FCH

25

30

ns

tAPe

20

20

ns

40

m (m

RAS precharge to
active time

CAS

Serial clock cycle time

tsc

Access time from SAS'11

tSAC

40

60

ns

Access time from SE'11

tSEA

40

50

ns

SAS precharge time

tsp

10

20

ns

SAS pulse width

tSAS

10

20

ns

50000

60

50000

ns

SE precharge time

tSEP

25

45

ns

SE pulse width

tSE

25

45

ns

Serial data out hold time after
SAS high

tSOH

10

10

ns

Notes:

*6 Measured with a load equivalent to 2 TTL loads and 100 pF.
*10 Either tRRH or tACH must be satisfied for a read cycle.
*11 Measured with a load equivalent to 2 TTL loads and 50 pF.

FUJITSU
1-109

M881461-12
M881461·15

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

M881461·12
Min
Ma.

M881461.1S
Min
Ma.

Unit

Serial output buffer turn off
delay from SE

tSEZ

0

0

ns

Serial data In set up time'16

tSDS
tSDH

0
20

0
25

ns

Serial data in hold time'16
Transfer command (TR) to
RAS set up time

tTS

0

0

ns

Transfer command (TR) to
RAS hold time

tRTH

90

110

ns

Transfer command (TR) to
CAS hold time

IcTH

30

35

ns

Transfer command (TR) to
SAS lead time

tTSL

5

10

ns

Transfer command (TR) to
RAS lead time

tTRL

130

140

ns

Transfer command (TR) to
RAS delay time

tTRD

-65

-50

ns

First SAS edge to transfer
command delay time

tTSD

25

35

ns

W to RAS set up time

tWSR
tRWH

0
15

ns

Wiii' RAS hold time

0
12

Mask data (DO) to RAS
set up time

~s

0

0

ns

Mask data (DO) to RAS
hold time

tMH

25

45

ns

Serial output buffer turn off
delay from RAS'13

tSDZ

10

25

60

10

30

ns

ns

75

ns

tSRS

40

RAS to SAS delay time'13

tSRD

30

60
45

Serial data input to SE
delay time

tSZE

0

0

ns

Serial data input delay from
RAS'13

tSDD

60

75

ns

tszs

0

0

ns

tESR

0

0

ns

tREH

12

15

ns

SAS to RAS set up time'16

Serial data input to !!iAS
delay time'15
Pseudo transfer command
(SE) to RAS set up time'14
Pseudo transfer command

(SE) to RAS hold time'14
Not..: ·13
*14
"15
"16

Write transfer and Pseudo write transfer only.
Pseudo write transfer only.
Read transfer only in the case that the previous transfer was write transfer.
Input mode only.

1-110

ns
ns

MB81481·12
MB81461·15

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Serial write enable set up
time"'6

MB81461·15
Min
Max

Unit

tsws

20

30

ns

Serial write enable hold time"'6

tSWH

80

120

ns

Serial write disable set up time

t SWIS

20

30

ns

Serial write disable hold time"'6

tSWIH

40

60

ns

tyS

0

0

ns

tYH

12

15

ns

RAS to SO buffer turn on Time

tSRO

0

Time between Transfer cycle

tREFT

Write Transfer Command Hold
Time Referenced 10 RAS

IRTHW

12

15

ns

tcPN

40

50

ns

As~ronous

command (TR)
to RAS set up time
~hronous

command (TR) to
hold time

CAS Precharge Time for
Normal Cycle
Note:

AC Test Conditions

MB81481·12
Min
Max

~16

Input mode only.

')INPUT

'--"'1
VIL

\'------

= O.8V

tT

= Sns

2) OUTPUT

_VO_H_=_2_.4_V____

~~'_

VOL= O.4V

____________________

\:

_"~~----~HI~G~H~.Z~--.j.

3) OUTPUT LOAD
MEASURING

FUJITSU
1-111

ns

0
4

4

ms

---~~-~---

-

MB81481·12
MB81481-15

Timing Diagrams
Readel/cle

V,H
V,L

V,H
V,L

ADDRESS

V,H
V,L

V,H
V,L

MDJDQ
(DUTPUT)

MDJDQ

(INPUT)

VOH ______-44-______~~~----------~----~
VOL

V,H
V,L

t72I DON'T CARE

1-112

MB81481·12
MB81481·15

Timing Diagrams
(Continued)

Write Cycle (Early Write,
~------------------------I"C--------------~--------~

V,H
V,L

CAS

ADDRESS

ilE/W

MD/DQ
(INPUlJ

MD/DQ
(OUTPUT)

V,H
V,L

V,H
V,L

V,H
V,L

V,H
V,L

VOH

HIGH-Z

VOL

VIM

V,L

NOTE: 'I WHEN IIEJW = "H': AU DATA ON THE MD/DQ CAN BE WRITTEN INTO THE CELL.
WHEN IIEJW = "~: THE DATA ON THE MD/DQ ARE NOT WRITTEN (MASKED)
EXCEPT WHeN MD/DQ = "H" AT THe FALUNG eDGE OF lilli,

FUJITSU
1-113

~DON'TCARE

M881481·12
M881481.15

in! Write Cycle

iiAs

CAli

ADDRESS

ME/W

VIH
V,L

V,.
V,L

V,.
V,L

V,.
V,L

MDIDQ
(INPUT)

MDIDQ
(OUTPUT)

VOH ________~--~~~----------_d
VOL

V,H

V,L

NOTES: 'I WHEN Iol!JW = "H'; ALL DATA ON THE MDIDQ CAN BE WRITTEN INTO THE
CELL,
.
WHEN Iol!JW - "C; THE DATA ON THE MDIDQ ARE NOT WRmEN (MASKED)
EXCEPT WHEN MDIDQ " "H" AT THE FALUNG-EDGE OF RAS.
'2 WHEN TIIIOE IS KEPT "H" THROUGH A CYCLE, MDIDQ IS KEPT IN HIGH·Z
STATE.

1·114

I72l DON'T CARE

MB81481·12
MB81481·15

Timing Diagrams
(Continued)

Read.Modlfy.Wrlte Cycle

RAS

CAS

ADDRESS

ilEiW

MD/DQ
(INPUT)

V,H
V,L

V,H
V,L

V,H
V,L

V,H
V,L

V,H
V,L

MDJDQ
VOH
(OUTPUT) VOL

= "H'; ALL DATA DN THE MD/DQ CAN BE WRITTEN INTD THE CELL.
WHEN ME/Vi = "c; THE DATA ON THE MD/DO AFiE NOT WRITTEN (MASKED)
EXCEPT WHEN MD/DQ = "H" AT THE FALLING EDGE DF An.

NDTE: ·1 WHEN!!EJW

FUJITSU

1·115

~DON'TCARE

M881481·12
M881481·15

Page Mode Read Cycle

liAs

V,H
V,L

V,H

CAs

ADDRESS

MEIW

V,L

V,H
V,L

V,H
V,L

VOH
MDIDQ
(OUTPUn VOL

MDIDQ
(INPun

V,H
V,L

V,H
TRIDE

V,L

E72l DON'T CARE

1-116

MB81481·12
MB81481·15

Timing Dlqrama
(Continued)

Palle Mode Write Cycle (Early Write'

V,H

~----------------------I~------------------rt"----~
~--'------.----_IR_A8---;-'-

_IRP

V,L
IRSH

VIH

V,L

ADDRESS V..

V..

V,H

V,L

MDIDQ

VIH

(INPUT)

V,L

MDIDQ

VOH

HIGH-Z

(OUTPUT) VOL

V,H

V,L

NOTE: 'I WHEN IolEIIV = "H'; ALL DATA ON THE MDIDQ CAN BE WRmEN INTO THE CELL.
WHEN IlE/IV = "c; THE DATA ON THE MDIDQ ARE NOT WRmEN (MASKED)
EXCEPT WHEN MDIDQ = "H" AT THE FALLING EDGE OF 1IAlI.

FUJITSU
1-117

o

DON'T CARE

MB81481·12
MB81481·15

Page Mode

RAS

OE Write Cycle

V,H
V,L

V,H
CAS

V,L

ADDRESS V,H
V,L

MD/DQ
(INPUT)

MD/DQ
VOH
(DUTPUT) VOL

'TR/OE

NOTES: 'I WHEN ME/W = "H': ALL DATA ON THE MD/DQ CAN BE WRITTEN INTO THE
CELL.
WHEN MEtW
THE DATA ON THE MD/DQ ARE NOT WRITTEN (MASKED)
EXCEPT WHEN MD/DQ = "H" AT THE FALUNG EDGE OF iiAli.
'2 WHEN fIi/i5E IS KEPT "H" THROUGH A CYCLE, MD/DQ IS KEPT IN HIGH.z
STATE.

= ".:

1-118

I7ZI DON'T CARE
IlSZlI VALID DATA IN

."t481.t2
. . .t48t.tS

m.

Tlmlntt DI.....
(Continued)

~--------------------------------------tRC------------------------------~------~

V,H
VIL

V,H
VIL

V,H
ADDRESS V..

MEtYi

MD/DO
(INPUTI

V,H
V,L

V,H
V,L

MDIDO
VOH
(OUTPIITIVOL

iii/OE

V,H

V,L

NOTE: '1 _EN II!/W = "H': ALL DATA ON THE MD/DO CAN BE WRmEN INTO THE CELL.
WHEN IIE/W = "C: THE DATA ON THE MD/DO ARE NOT WRITTEN (MASKEDI
EXCEPT _EN I4D/DO = "H" Ilf THE FAWNG EDGE OF lIAli.

t'ZZl DON'T CARE
~ VALID DATA IN

tSQQI VALID DATA OUT

1-119

MB81481.12
MB81481·18

iiiS-Only Refre.h Cycle
(iR/W = Don't Care'
~-----------------~c----------------~

______________~I~---------I~----------~

v--------~

V..

V,L

ADDRESS

V,H
V,L
..I..L.<'-'-'-t...I..l.~J.fJ

V,H
V,L ......1-/..1-/..1-/.......""

MD/DO

VOlt

(OUTPUT)

VOL

_________.1\

V,H
V,L J...r...L<<-L..<-L..<-L..l..t..~

MD/DO
(INPUT)

V,H _ _-,H",IG=H-=Z___
VIL

r.z2I DON'T CARE

1-120

MB81461·12
MB81461·15

Timing Diagrams
(Continued)

CD.Before.RB Refresh Cre.e
(Address, ME/li = Don't Care)

~-------------------'RC----~------------~

'-----------.R.. -----------+I

ill

V,H
V,L

MD/DQ
(OUTPUT)

MD/DQ
(INPUT)

VOH
VOL

-...:..::::HIG=.-H.Z

m

FUJITSU

1·121

DON'TeARE

'.'2

MB.' ...

Mae,...,·,.

HIdcI_ Refre.h Cycle

V,H
ADDRESS V,L

iiEiii

V,H
V,L

IIID/DO

VOH

(OUTPunYOL

-'-'-'-L.LL.L.L..L.,...,

--------~TTT-+-----~~----------------------------------'1

HIGH-Z

MDIDO
(INPun

~DON'TCARE

1-122

MB81461·12
MB81481·15

Timing Diagrams
(Continued)

Read Transfer Cycle"1
(DQ ~ Don't Carel

~-----------------------IRC------~__------------~~

RAS

V,H
V,L

CAS

V,H
V,L

ADDRESS VIH

V,L

TRICE

V,H
V,L

ME/v.;

V,H
V,L

SAS

V,H
V,L

so
(INPUT)

SO
(OUTPUT)

VOH _ _ _ _--{

VOL

PREVIOUS ROW
NOTES: "1 IN THE CASE THAT THE PREVIOUS TRANSFER IS READ TRANSFER.
*2 IF SE IS LOW, THE VALID DATA WILL APPEAR WITHIN tSAC or tSEA.

FUJITSU
1-123

-I

NEW ROW -

t7ZJ DON'T CARE

MB81461·12
MB81481·15

Read Transf.r Cycle'1
(DQ = Don't Care'

'AC
'AAS

'AP

V,H

m

V,L

V,H
CAS

V,L

V,H
ADDRESS

V,L

V,H

iii/liE

V,L

V,H

ME/iii

V,L

V,H

SAS

V,L

V,H

liE

SD
(INPUn

SO

VOH __________________~~~______~

(OUTPUT)

VOL

NOTES: "

IN THE CASE THAT THE PREVIOUS TRANSFER IS WRITE TRANSFER.

mooN'TCARE

VALID DATA INPUT.

~ INHIBIT TRANSITION

INEW DATA~
'2 IF !IE IS LOW AND THE PREVIOUS CYCLE IS SERIAL WRITE CYCLE, THIS SHOULD BE

VILTOVIH

1·124

MB81461·12
MB81461·15

Timing Diagrams
( Continued)

Write Transfer Cycle'

tRC
tRAS

V,H

RAS

V"

V,H

CAS

V"

ADDRESS

V,H
V,L

V,H

TR/OE

V,L

V,H

ME/VI

V,L

V,H

SAS

V,L

V,H

SE

V,L

so

V,H

(INPUT)

V,L

so

VOH

(OUTPUT)

NOTE: * 1 IF

HIGH·Z

VOL

SE IS HIGH THIS DATA IS NOT WRllTEN INTO THE SAM.

fZL} DON'T CARE

'IN THE CASE THAT THE PREVIOUS TRANSFER IS WRITE TRANSFER.

!;S'3 INHIBIT TRANSITION
VIL TO VIH

FUJITSU
1·125

MB81481ot2
MB81481·15

Pseudo Transfer Cycle
~-----------------------t"C---------------------;~

m

V,"
V'L

CAs

V,"
V'L

V,"
ADDRESS

V,L

mOe

V,"

iiE/w

V,"

V'L

V'L

SE

SAS

V,"
V,L

V,"
V,L

SO
(INPUT)

V,"
V'L

SO
YOH
(OUTPUT) VOL

NOTES: 'I IF III IS HIGH, THIS DATA IS NOT WRITTEN INTO SAM.
'2 IF IE IS HIGH, SO (SDO TO SD3) ARE IN HIGH-Z STATE AFTER ISEZ.

o

DON'T CARE

!;S.1INHIBrr TRANSInON
V.L TOV,H

1·126

MB.,4.,·,2
MB.,48,·,5

Timing DIagrams
(Continued)

V,.
VOL

_ _ _ _---J

SAS

so

VO.

(OUTPUT) VOL

~
V..

SD
(INPUT)

ISZE

__............................__~................................~HI~G~~~Z............................_

VOL

IN THE CASE OF

BE = "L"

V..
VOL
~----------.------------.-----------.--------

SAS

V,.
VOL

SD

YOM

(OUTPUT)

VOL

so

:~

________________________________

~H~~=H~~~

_______________________________

(INPUT)

m

DON'T CARE

~ INVAUD DATA

FUJITSU
1·127

MB81481-12
MB81461·15

Serial Write Cycle

.-----.".s
VOH
VOL

VOH
VOL

VOH

SAS

VOL

I·..
oo----.sc----'--~·....- - - . s c
SO
VOH
(OUTPUT) VOL

HIGH·Z

----------------~------------~~~------------------_+_r---------

VOH

so

(INPUT)

VOL

IN THE CASE OF liE

= "L"

VOH
SAS
VOL

VOH
SO
(OUTPUT) VOL

SD
(INPUT)

VOH
VOL

mDON'TCARE

1-128

Preliminary

FUJITSU
• MB81464-10, MB81464.12, MB81464.15
NMOS 65,536 Word By 4-Bit
Dynamic Random Access Memory

Description
The Fujitsu MB81464 Is a fully decoded, dynamic NMOS random
access memory organized as 65,536 words by 4 bits. The design Is
optimized for high speed, high performance applications such as
mainframe memory, buffer memory, peripheral storage and environments where low power dissipation and compact layout is
required.
Multiplexed row and column address inputs permit the MB81464 to be
housed in a standard 18-pin DIP and 18-pad LCC. Other package
options include a 20-pin plastiC zig zag in-line package. 18 and
22-pin PLCC packages, and a 22-pad LCC. Additionally, the
MB81464 offers new functional enhancements that make it more
versatile than previous dynamic RAMs. "~-before-RAS" refresh
provides an on-chip refresh capability. The MB81464 also features
"page mode" which allows high speed random access up to
256 bits within a same row.
The MB81464 is fabricated using silicon gate NMOS and Fujitsu's
advanced Triple-Layer Polysilicon process. This process, coupled
with single-transistor memory storage cells, permits maximum circuit density and minimal chip size. Dynamic circuitry is employed in
the design, including the sense amplifiers.
Clock timing requirements are non-critical. and power supply tolerance is very wide. All inputs and outputs are TTL compatible.

F ••tur••
• 65,536 x 4 RAM, 18 pin
package
• Silicon-gate, lHple Poly NMOS,
single transistor cell
• Row accesa time
100 ns max_ (MB81464-10)
120 ns max. (MB81464-12)
150 ns max_ (MB81464-15)
• Cycle time
200 ns min. (MB81464-10)
220 ns mln_ (MB81484-12)
280 ns mln_ (MB81464-15)
• Single +5V Supply, ±10%
toleranca
• Low power, (Active)
385mW max. (MB81464-10)
358mW max. (MB81464-12)
314mW max. (MB81464-15)
27_5mW max_ (atendby)

• On chip substrate bias gon_
tor for high porforrnaince
• All Inputs TTL compatible
• Three atate TTL compatlbie
outputs
• 4ms/256 refresh cycles
• Output unlatched at cycle end
• Early Write or G to Control
~t buffer Impedance
• "CAS-before-Fin and
m-Only refresh cspablllty
• Read-Modlfy-Wrlte, psge mode
capability
• On-chip latches for Address
and DQ

1-129

MB81484·10
MB81484.12
MB81484·15

MB81484 Block Diagram
and Pin Assignmants
DQ1

m-~}--I
~I~------------~~

G

.
..
..

001

~DQ4

DO'

D04

QQO

CAS

A,

Vi

D03

A,

W HC

001

RAS

AO

A6

A1

AS

A2

liAS

A,

As

'"

DQ2

CAS

A,

iI

DQ3

A.

Ao

m

AO

Vee

A,

NC

NC

NC

NC

A6

A1

AS

A2

At

BOTTOM VIEW

Absolute Maximum Rating
(See Note)

CAS
DQ3

A4 VCC A7 A3

LEAD
Ha'

CiI Vss

DQ2

iI

TOP VIEW

A,

LEAD
NO.2

DQ4

vss

A,

..

G VSS

20

TOP VIEW

..........

Value

Unit

Voltage on any pin relative to Vss

V1N' VoiJT

-1 to +7

V

Voltage on Vee supply relative to Vss

Vee

-1to+7

V

TSTG

-55 to +150
-55 to +125

·C

Po

1.0

W

50

mA

Rating

Storage temperature

Ceramic
Plastic

Power dissipation
Short circuit output current

NoIe: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation
should be restricted io the conditions as detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. This device contalns circUitry to protect
the Inputs against damage due to high static voltages or electric fields. H9W9V8I', It Is advised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.

Capaoltence (TA

=25 ·C)

Max

Unit

C1N1

7

pF

C1N2

10

pF

CD

7

pF

Paramell8r

.ymbol

Input Capacitance Ao-A7
Input capacitance RAS, W, G, CAS
Data I/O Capacitance DQ1 - DQ4

FUJITSU
1-130

Typ

MB81464.10
MB81464·12
MB81464·15

Recommended Operating
Conditions
(Referenced to Vss)

Parameter

Symbol Min

Supply Voltage

Vee

4.5

I7ss

II

Input High Voltage, all inputs

VIH

Typ Ma" Unit Operallng T ....peratur.
5.0
(j

5.5
0

\J

V

2.4

6.5

V

Input Low Voltage, all Inputs except DO VIL

-2.0

0.8

V

Input Low Voltage, DO

-1.0

0.8

V

VILO'

O·C to 70·C

'The device will withstand undershoots to the -2.0V level with a maximum pulse width of 20ns at the -1.5V level.

DC Characlerlstlcs
(Recommended operating
conditions unless otherwise
noted.)

Parameter

MB81464·10
Symbol Min
Max

MB81464·12
Min
Max

MB81464·15
Min
Max

Unit

Operating current'
Average power supply current
(RAS, CAS cycling; tRC = min.)

ICCl

70

65

57

mA

Standby current
Power sum current
(RAS = CA = VIH )

Icc2

5.0

5.0

5.0

mA

Refresh current l'
Average power supply current
(CAS = VIH , RAS cycling;
t RC = min)

Icc3

60

55

50

mA

Page mode current'
Average power supply current
(RAS = VIL, CAS = cycling;
tpc = min)

Icc4

40

35

30

mA

Refresh current 2'
Average power supply current
(CAS-before-RAS; tRC = min)

Iccs

65

60

55

mA

Input leakage current
Input leakage current,
any input (0 .. VIN .. 5.5V,
Vcc = 5.5V, Vss = OV,
all other pins not under testOV)

II(L)

-10

10

-10

10

-10

10

p.A

Output leakage current
(Data out is disabled,
OV .. VOUT = 5.5V)

IOQ(L)

-10

10

-10

10

-10

10

p.A

Output levels
Output high voltage
(loH = -5mA)
Output low voltage
(lOL = 4.2mA)

VOH
VOL

2.4

Note:

*

2.4
0.4

2.4
0.4

0.4

V

ICC is dependent on output loading and cyde rates. Specified values are obtained with the output open. ICC is dependent on input low
voltage level VILD' V1LD > -O.Sv.

FUJITSU
1-131

MB81464·10
MB81464·12
MB81464·15

AC Characteristics'1,2,3
(Recommended operating
conditions unless otherwise
noted,)

Parameter

MB81464·10
Max
Symbol Min

Time between refresh

tREF

MB81464·12
Min
Max

4

MB81464·15
Min
Max

4

4

Unit
ms

Random read/write cycle time tRC

200

220

260

Read-modify-write cycle time t RWC

270

305

345

ns

Page mode cycle time

tpc

100

120

145

ns

Page mode read-modifywrite cycle time

t pRWC

170

195

ns

225

ns

tRAC

100

120

150

ns

t CAC

50

60

75

ns

0

30

ns

3

50

ns

Access time from RAS'4,6
Access time from CAS'5,6
Output buffer turn off delay

tOFF

0

25

0

25

Transition time

tT

3

50

3

50

RAS precharge time

tRP

80

RAS pulse width

tRAS

100

90
100000 120

100

ns

100000 150

100000 ns

RAS hold time

t RSH

50

60

75

ns

CAS precharge time
(page mode only)

tcp

40

50

60

ns

CAS precharge time
(all cycles except page
mode)

t CPN

30

32

35

ns

CAS pulse width

tCAS

50

100000 60

100000 75

100000 ns

CAS

tCSH

100

RAS to CAS delay time'7,s

t Rco

20

CAS to RAS set up time

t CRS

10

10

10

ns

hold time

120
50

22

150
60

25

ns

75

ns

Row address set up time

tASR

0

0

0

ns

Row address hold time

tRAH

10

12

15

ns

Column address set up time

tASC

0

0

0

ns

Column address hold time

tCAH

15

20

25

ns

Read command set up time

tRcs

0

0

0

ns

Read command hold time
referenced to RAS'1o

tRRH

10

15

20

ns

Read command hold time
referenced to CAS'1o

tRCH

0

0

0

ns

-5

-5

ns

Write command set up time

twcs

-5

Write command hold time

t WCH

25

30

35

ns

Write command pulse width

twp

25

30

35

ns

Write command to RAS lead
time

t RWL

35

40

45

ns

Write command to CAS lead
time

tCWL

35

40

45

ns

Data in set up time

tos

0

0

0

ns

Data in hold time

tOH

25

30

35

ns

See note on the following pages.
"These symbols are described in lEE 662·1980: lEE Standard terminology for semiconductor memory.

FUJITSU
1-132

MB81464-10
MB81464-12
MB81464-15

AC Characteristics,
(continued)
Parameter

Symbol

Access time from G

toEA

MB81464-10 MB81464-12 MB81464-15
Min
Max
Unit
Min
Max
Min
Max

27

40

30

tOED

25

Output buffer turn off delay from G

toEZ

0

G hold time referenced to W

tOEH

0

0

0

ns

t FCS

20

20

20

ns

CAS hold time referenced to RAS
(CAS-before-RAS refresh)

tFCH

20

25

30

ns

RAS precharge to CAS active time

tRPC

10

10

10

ns

tePR

30

30

30

ns

CAS set up time referenced to
(CAS-before-RAS refresh)

RAS

CAS precha~me
(CAS-before-RA cycle)

RAS in active setup time

25
25

0

30

ns

G to data in delay time

25

0

ns

30

ns

toES

0

0

0

ns

IN to CAS delay time"11

t DZC

0

0

0

ns

IN to G delay time"11

t DZO

0

0

0

ns

G to

Notes:

*1 :~i~f~~~s~~r:o:'~~:h~~~i~~:r,a::I:n~~-,::: ~O~~~~~:~~~~~~a~~:~nb::::I~:a~~~i~~r~~~~!Sa~~~:~~~
tr

*2 AC characteristics assume = 5 ns,
*3 VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between
VIH (min.) and VIL (max.).
*4 Assumes that tRCD :,.; IRCD (max.). If IRCD is greater than the maximum recommended value shown in this table, tRAC will be
Increased by the amount that tACO exceeds the value shown.
*5 Assumes thai IRCD;;l!o tRCD (max.).
*6 Measured with a load equivalent to 2 TTL loads and 100 pF.

*7 Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference pOint only; if
tRCD is greater than the specified tRCD (max) limit, then access lime is controlled exclusively by tCAC'
~ IRAH (min.) + 21T(tr ~ 5 ns) + IASC (min.).
*9 twcs is not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs ;:;.
~cr:' (min.), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout entire

"S IRCD (min.)

*10 Either tAAH or tACH must be satisfied for a read cycle.
*11 Either tDZC or tDZO must be satisfied for all cycles.

FUJITSU
1-133

MB81484.10
MB81484·12
MB81484·15

Timing Diagrams
Read CI/ole

VIH _

_______~~==============~~==I~R~C========:;4J~::::::~
'RAS

VII.. -

I...-------IC.M--------<~

________-::II:"'"___
V'M _--ir-.....;..;...---+----,....----IRSH:::==::::r;U4
....... I-----IC.. - - - - I
V1L

ADDRESS

DATA
(OUT)

-

VIM -

VIL -'~-s..===F~

I IA=C==tlh.~
VOL ~OZC
I.'OEZ
~::= xxxxxx)q.--IDZ-O
=~';"""--""'I~-IO-_~

VOH

-

----------------.....,-HIGH.Z

tOEA

DATA
(IN)

:::= XXXXXXXXXXXX~

~
IXXI

DON'T CARE

Write CI/ole (lIarll/ Write'
Don't Care

<3:

..
RAS

en

lAC

V1H V1L -

VIH _

~

~

V 1L -

VIH _

ADDRESS
V 1L -

w

V'H-

V'L-~~~~~~~~

__

+_--+_--~~~~~~~~~~~~~~~~~

DATA
(IN)

DATA
(OUT)

VOM

--------------------------HIOH·Z---------------------------___

VOL -

IXXJ DON'T CARE

FUJITSU
1-134

.881484·10
M881464·12
M881464·15

Timing Diagrams
(Continued)

ii Write Cycle

RlII

CJIS

ADDRESS

V'HVII -

V1H V 1L -

V'HV1L -

iN
DATA
(IN)

DATA
(OUT)

VALID
DATA IN

~~:=

~

................~........................+-G

V'H- ~~7\,~~~~7\~~r.0~~~~""""""--~~~~~~~~~~~~~
VIL -

~t:::.I.:.::.I.:l.l,;~.o.D.I.~~~ty

I2lZI DON'T CARE
Read.Modlfy·Wrlte Cycla

!IllS

I~-----------------------I.WC------------------------.I
V'H- -----:1~ ""'>---------------------1 ••• -------------------11
V'L-

r----".Ij,

leo.

leAS
CAS

ADDRESS

V'HV'LV'H-

iN

DATA
(IN)

DATA
(OUT)

FUJITSU
1-135

....

MB81484.10
MB81484·12
MB81484·15

Timing Diagram.
(Continued)

Pag. Mod. Rud Crel.

ADDRESS

w
DATA
(IN)

DATA
(OUn
V'H- :7'I:7';:7';~~~7!l.1

VIL-~~~~~~~~~~~~~~~__~~~~~~~~~JL~~~JL~~~~~

rzzA

VALID DATA

Pag. Mod. Writ. Crel.

(13 = Don't Care)
RAS

CAS

ADDRESS

V1H V1L -

V'H-

V'lV 1H -

V1L -

W

V'HV'L-

DATA
(IN)

V'H-

DATA
(OUn

V1L -

V OH -

YOL -

-------------HIGH.Z~I,.,-------------

Il1XI DON'T CARE

FUJITSU
1·136

MB81484·10
MB81484·12
MB81484·15

Tlmln. Dla.ram.
(Continued)

Pa •• Mod. Read.Modlfy.Wrlt. Cycl.
V'H-

iIA!

V'L-

V 1H _

eAS

ADDRESS

V1L

_

V1H

-

V1l _

W

DATA
(IN)

DATA
(OUT)

if

VIH V 1L -

rx:xr DON'T CARE

RAt.Only Refr•• h Cycl.
(WE, OE = Don't Care)

r------------------, AC-------------------1
RAS

V'HV 1L-

ADDRESSES V'HV 1L-

CAS

DATA
(OUT)

V'HV'LV OH

HIGH..z

V OL -

IXXI DON'T CARE

FUJITSU

1-137

MB81464·10
MB81464·12
MB81464·15

Timing Diagram.
(Continued)

CAS·b.for.·RAS R.fr•• h Cycl.
Note: Address, W, G Don't Care

=

v,M_--------,lI---V'L-

DATA

~-------------------H~~--~--------------------

(OUT)

IRXI DON'T CARE
Hldd.n R.fr•• h Cycl.

1··.----------I~-------·I·4_-----·~------~

~:::

ADDRESS

w

I... 'IIO.M
~
~~ ~~

..

I

~::=d AD't~~S R;g=xxXXXXXXXXXXXXXXXXXXXXXX)
11~

DATA
(OUT)

DATA
(IN)

FUJITSU
1·138

I

~ ~IOOH

I

M881484·10
M881484·12
M881484·15

D•• crlptlon
Address Inputs:
A total of sixteen binary Input
address bits are required to
decode parallel 4 bits of 262144
storage cell locations within the
MB81464.
Eight row-address bits are
established on the Input pins
(Ao through A7) and latched with
the Row Address Strobe (RAS).
The eight column-address bits
are established on the input
pins (Ao through A7) and latched
with the Column Address
Strobe (eAS).
The row and column address
inputs must be stable on or
before the failing edge of RAS
and CAS, respectively. CAS is
internally inhibited (or "gated")
tlyBAS to permit triggering of
CAS as soon as the Row Address Hold Time (t RAH)
specification has been satisfied
and the address Inputs have
been changed from rowaddresses to column-addresses.
Write Enable:
The read mode or write mode Is
selected with the Write Enable
(Wi Input. A high on W selects
read mode and low selects
write mode. The data Inputs are
disabled when the read mode is
selected. When W goes low
prior to CAS, data-outs will remain In the high-Impedance
state allowing a write cycle.
Data Pins:
Data Inputs:
Data Is written during a write or
read-modlfy-write cycle. The
failing edge of CAS or W
strobes data into the on-chip
data latches. In early-write cycle, W brought low prior to CAS'
and the data is strobed In by
CAS' with setu~_!!!d hold times
referenced to CAS. In a readmodify-write cycle, CAS will
already be low, thus the data
will be strobed in by W with setup and hold times referenced to

W.
In a read-modify-write cycle, G
must be low after tozo to
change the data pins from Input mode to output mode and
then G must be changed to

high before tOED to return the
data pins to Input mode. In an
early write cycle, data pins are
In Input mode regardless of the
status of G.
Data Outputs:
The three-state output buffers
provide direct TIL compatibility
with a fan-out of two standard
TIL loads. Data-out is the same
polarity as data-in. The outputs
are In the high-impedance state
until CAS is brought low. In a
read cycle, the outputs go
active after the access time interval tRAC and tOEA are
satisfied. The outputs become
valid after the access time has
~sed and remain valid while
CAS and G are low. In a read
operation, either G or CAS
returning high brings the outputs into the high impedance
state.

Output Enable:
The G controls the impedance
of the output buffers. In the
high state on G, the output
buffers are high Impedance
state, input mode. In the low
state on G, the output buffers
are low Impedance state, output mode. But In early write cycle, the output buffers are in
high impedance state even if G
is low. In the page mode read
cycle, G can be allowed low
through the cycle. In the page
mode early write cycle, G can
be allowed high throughout the
cycle. In the page mode readmodify-write or delayed write
cycle, G must be changed from
low to high with tOED'
Page Mode:
Page Mode operation permits
strobing the row-address into
the MB81464 while maintaining
RAS at a low throughout all
successive memory operations
in which the row-address
doesn't change. Thus the power
dissipated by the negative
going edge of RAS Is saved.
Further, access and cycle times
are decreased because the time
normally required to strobe a
new row-address Is eliminated.

FUJITSU
1-139

RAS-only Refresh:
Refresh of the dynamic memory
cells Is accomplished by performing a memory cycle at each
of the 256 row-addresses (Ao ~t least every 4 ms. The
RAS only refresh avoids any
output during refresh because
the output buffer is in th~h
impedance state unless CAS Is
brought low. Strobing each 256
row-addresses (Ao - A7) with
RAS will cause bits in each row
to be refreshed. Further RASonly refresh results in a substantial reduction in power
dissipation.

CAS·before-liAS Refresh:
CAS'·before-RAS refreshing
available on the MB81464 offers
an alternate refresh method. If
CAS Is held on low for the
specified period (tFcsl before
RAS goes to low, on chip
refresh control clock generators
and the refresh address counter
are enabled, and an internal
refresh operation takes place.
After the refresh operation is
performed, the refresh address
counter is automatically incremented In preparation for
the next c:AS-before-RAS
refresh operation.

Hidden Refresh:
Hidden refresh cycle may take
place while maintaining latest
valid data at the output by extending eAS active time.
In the MB81464, hidden refresh
means CAS-before-'RiiS refresh
and the internal refresh addresses from the counter are
used to refresh addresses i.e., it
doesn't need to appl~resh
addresses, because CAS' is
always low when RAS goes to
low in this mode.

11881464·10
11881464·12
11881464·15

Typical Characteristics
Curves

CURRENT WAVEFORM (Vee = 5.5 V, TA = 25°C)

long Cvele

Raid/Writ. Cycle

I!A! f- l -

V- I-

i:A"I

r

O(

i

I-

-

200

160

.11 too
110

1/\
'\

11

'rl

r--.. lJ

V\
\

,

(\

,

rI

/

tJ

I\.

r\

~

LA

-

I'-

50 nl/DIVtSIOn

1'-

Fi'Al only Refresh Cycle

Page Mode Cycle

1\

[l

I

V

\~

I\.

'\

CAS-before-RAS Refresh Cycle

I!A! l - I-

V- M

eliI

II- t-

C-E
200

i

ISO I-

.!f

100

-

1-J

0
~

I-

IV I\) I\.

A

-r\ 11 ll\

-+-- ~- l - I- -

,

11\
I-- ~

,

50 mlO,,,.,,on

FUJITSU
1-140

r

II

.

-

"

_1.1 iLl

\V

t-

-

I' ,,"r-

lA
r- I--

11
V

" •• 1484-10
" •• 1484-12
" •• 1484-1.

Typical Characteristics
Curves
(Continued)

NORMALIZED ACCESS TIME
... SUPPL Y VOLTAGE

w

~A' 2~·C

:;
j:

~

1.2

~

1. 1

\.

~ 1.0
:i

«

:;

~

0.9

w

Ve~ = 5.dv

:;
j:
en

1.2

U>

W

'"

c

NORMALIZED ACCESS TIME
VI. AMBIENT TEMPERATURE

8«

1. 1

i".. r---....

~

1.0

«

:;
0:

0.9

o
Z

U O.B

::

::

«

«

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (VI

-20 0
20
40
~
BO 100
T A. AMBIENT TEMPERATURE (·CI

OPERATING CURRENT
SUPPLY VOLTAGE

OPERATING CURRENT
CYCLE RATE

VI.

6

o

Ve~. 5.Jv

a
CI

z

5O'-TA - 25·C

~

0:

w

~

j

•

./

20

I'

<

.§
0:
0:

60

tJ
CI

50

z

j:

«

0:

/

40

C

U

.9

~

BO

1
2
345
I/'Re. CYCLE RATE (MHzl

ve~ _ 5.Jv

70-'R _230n.-t--t---t--l

w

IE

a

~

~
0:
w

~

U
.9

",.,.

30
20

OPERATING CURRENT
VI. AMBIENT TEMPERATURE

1

,/

."...

W
0-

10

o

25·b

T2 =
70 I-- 'Re • 230 n.

:::>

/

80

f-

zw

/

40
30

VI.

/

w

IE

",.

/

:i

U O.B

1~

,. /

C

601--jf--I--t---t-+--l

50r--i"'-+~-F~4==-t--i
~~-1f--4--+--+-~-~

301---l--+--l--+--~--l

20

-k2o~~0~~20~-4~0~~~~~B~0-1~00
TA• AMBIENT TEMPERATURE (·CI

FUJITSU
1-141

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (VI

STANDBY CURRENT
VI. SUPPLY VOLTAGE

<
.§

TAl. 25·6
5

fZ

::!0:

4

a

3

C
Z

2

>
ID

~
N

~

1

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (VI

M881484-10
M881484-12
M881484-15

Typical Characteristics
Curves
(Continued)

REFRESH CURRENT 1
CYCLE RATE

STANDBY CURRENT

vs. AMBIENT TEMPERATURE
VclC

VI

KS.~V

<
.s

s

-- -

4

3
2

IZ

60

w

40

:>
u

30

a:
a:

:r
w

'"a:

II..
W

Vc~ -s.Jv

so - T

A '2SoC

./

/

20

/'

a:

M 10

,/

V

u

.2
-20

0

20

40

60

80

0

100

2

TA. AMBIENT TEMPERATURE (OC)

IZ

il!

a:

vs. SUPPLY VOLTAGE
T '-2sob
70 _ A
'RC =230 ns

w

- i..-- v

a:

o 30

.2

20

so - T

a:
a:

40

w

30

0
::!!
w

20

c

<
0-

..

o '"
0

PAGE MODE CURRENT
CYCLE RATE

REFRESH CURRENT 2
CYCLE RATE

40

~

30

::!!
w

20

a
o

1

-12J ns

N

I-TA - 2SoC

a:
a:

-----

;t
10

II

o

60

VC~ -S.S~

so - T A -2SoC

IZ

C>

..

2
4
6
8
10
I/,PC. CYCLE RATE (MHz)

VI.

60

w

"

u

VI.

IZ

V

V

.2

S.O
6.0
VCC. SUPPLY VOLTAGE

-

A -2SoC

C>

4.0

1 so ,pJ

VC~ = s.Jv

lZ

:>
u

40

60

w

60

iliw
e:

<
.s

80

a so

6

PAGE MODE CURRENT
VI. CYCLE RATE

REFRESH CURRENT 1

<
.s

4

I/'RC. CYCLE RATE (MHz)

4.0

S.O
6.0
VCC. SUPPLY VOLTAGE (V)

FUJITSU
1-142

w 40
a:
a:

a

~a:

20

II..
W

a:

j

/

30

V

/
/

0

o

4

S

I/'RC. CYCLE RATE (MHz)

• •81484.10
• •81484.12
• •81484.15

Typical Characteristics
Curves
(Continued)

«

80

oS

70 r-T ~ 25'C
A

....
z

W

0::
0::

a

.,
~
...

~

tR~ = 23d ns

3.0
TAl.

;3
~>
<-

60

~ 2.0 I---

U)

ID~
50

:I:

".

40

W

..

30

E

20

0::

ADDRESS AND DATA INPUT
VOLTAGE VI. SUPPLY VOLTAGE

REFRESH CURRENT 2
SUPPLY VOLTAGE

V$

.".-

'/

'/

~

25'~

~'bc.-

~
......
~IL(Max)
~

5

~ >

~~ 1.0

>~

0Z

<

o

l:

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (V)

:>

o

ADDRESS AND DATA INPUT
VOLTAGE VI. AMBIENT TEMPERATURE
0

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (V)

RAS. CAS, WE AND OE INPUT
VOLTAGE VI. SUPPLY VOLTAGE
3.0

Ve~' 5.0~

TAI~25,d

-V IH (IMinl

0

0

VIH (Min)

~

I
V IL IMax)
0

l:

:>

I~
o
z
<

VIL (Max)

o
-20
0
20
40
60
80
100
T A. AMBIENT TEMPERATURE ('C)

RAS. ~. WE AND OE" INPUT
VOLTAGE VI. AMBIENT TEMPERATURE
3.0

Ve~ - 5.0~

0 ~ 2.0

V IH Min)

j:

5~

S

1 ~"5
0::>
~!:i

1.0

~

VIL Max)

0-

:>

o

-20

/

5

/',1'

10
5

o

Z

<
l:

Ve~ =4.L

20 -TA-25'C

W

:;

1

>~

ACCESS TIME
LOAD CAPACITANCE

VI.

]

I~~

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (V)

o

/

V

-5
0
20
40
60
80
100
T A • AMBIENT TEMPERATURE ('C)

FUJITSU

1-143

100 200 300 400 500
CL. LOAD CAPACITANCE (pF)

"881484-10
.. 881484-12
"881484-15

Typical Characteristics
Curves
(Continued)

OUTPUT CURRENT
VI. OUTPUT VOLTAGE

OUTPUT CURRENT
vs. OUTPUT VOLTAGE

1 25

1-'25

0

I-

I-

~ 200

~-100

cr:
cr:

VCC-~

I-

V r-.:-r-

a 150
~

:>

o

.:,

.9

100

:,/
o

~

1

I

VCC -4.S1-

2

3

4

S

SUBSTRATE VOLTAGE
DURING POWER UP

It
w 51
:>Cl
"'<
.1U.J

»uO

w
1--

~ ~

I-w

0

-1

~~

i~

-2

:»

-3

.,0

-:

a

VI I I I I
1\

'\ r\:A·2S'C

"i'..

.......

r--

50 ""I Division

FUJITSU

1-144

-75

'\
'\ \V~c·S.SV

I-

~ -so

5

:i:
.9

VOL. OUTPUT VOLTAGE (V)

~~

cr:
cr:

T~.25!C
-I

\

-25

o
o

'"\

\

Vcc·4.

"f"
1

~

I•
2

~"

3

4

S

VOH. OUTPUT VOLTAGE (V)

M881484·10
M881484·12
M881484·15

Peoka•• Dlm.n.lon.
Dimensions in Inches
(millimeters)

18·L.ad Ceramlo IM.tal S.al) Dualln·Lln. Pack •••
ICe•• No.: DIP.18C·A01)

REF
~

INDEX AREA

~

'II h

]

[

'
W
UJ
mmm
I ..

.890(22.61)
.910(23.11)

2OO(S'08)MAX

.090(2.29
.110(2.79)

~J

.12O(3.0S)
.150(3.81)

.032(0.81)
REF
.800(2O.32)REF
.042(1.07)
.062(1.58)

I...-

.02O(0.SI)
.050(1.27)

18 Lead Pla.tlo Dual·ln·Lln. Pack•••
DIP·18P·MOa

INDEX·1

~~~==~==~--!
0.250
(8.35)

0.270
(8.85)
INDEl(.2

~~~~TTrrrr~~--1

o.a&0(2t.80)

o.B78(22,25)

lI-o:mrr--t---

1-145

SEATING PLANE

MB81464·10
MB81464·12
MB81464.15

Package Dimensions
Dimensions in inches
(millimeters)

L

18·Pad Ceramic (Metal Seal) Leadless Chip Carrier
(Case No.1 LCC·18C.A06)
PIN NQ 1 INDEX

.045(1.14)TYP

/

0_
.505(12.83)

.070(1.78)
.280(7.11)
.295(7A9)

TYP

Q'083(2'II)MAX

.045(1.14)
TYP

18·Lead Plastic Chip Carrier
(Case No.1 LCCo18P.M02)

I'

m

~~

~~
"!~

F:"N"

~i

- ::!~::::~:

.317(8.05)
.327(8.31)
.282(7.16)
.288(7.32)

.050(1.52) MIN.

'I

.020(0.51) MIN .

0.

'11

I

.030(0.76) TYR
.050(1.27) TYR

FUJITSU

1-146

MB81464·10
MB81464·12
MB81464·15

Package Dimensions
Dimensions in inches
(millimeters)

22·Lead Plastic Chip Carrier
(Case No.: LCC·22P·M01)

.026(0.65) TYP

.522(13.26)
.532(13.51)

.487(12.37)
.493(12.52)

L
R.030(O.76)TYP

20·Lead Plastic ZigZag. In· Line Package
(Case No.: ZIP.20P·M01)
0.104
(2.65)

1.024(26.00)
1.001 (25.43)

I
---~
I (3.05)
I~
0.250

~
(6.85)

~~~~~~rrrrrrmmm~~

I

(L

0.325 MAX

I

0.016

I

I

I'

O('-":=.2'-!7)-'T-'-'-YP
~~",0~",:0:;.1-~ ~ +j_ .....o-_0"'.o:c:5..:.
(0.60)

F

(0.30)

?.;1~~
--~

0.118 MIN
(3.0)

1·147

0.008
(0.20)

~

I

Preliminary

FUJITSU

MOS Memories
•

MB811000·12, MB811000·15
1,048,576-Bit Dynamic Random
Access Memory

Description
The Fujitsu MBSll000 is a fully decoded, dynamic NMOS random
access memory organized as 1,048,576 one-bit words. The design
is optimized for high speed, high performance applications such as
mainframe memory, buffer memory, peripheral storage and environments where low power dissipation and compact layout are
required.
The MBSII 000 features "page mode" which allows high speed
random access of up to 1024-bHs within the same row. AddHionally,
the MBSII 000 offers new functional enhancements that make H
more versatile than previous dynamic RAMs. Multiplexed row and
column address inputs permits the MB811000 to be housed in a
Jedec standard IS-pin dual in-line package or 20 lead SOJ package.
The MB811000 is fabricated using silicon gate NMOS and Fujitsu's
advanced Triple-layer Polysilicon process. This process, coupled
with an innovative stacked capacitor memory cell, permits maximum circuit density and minimal chip size. Dynamic circuitry Is
used in the design, including dynamic sense ampHfiers.
Clock timing requirements are noncritical, and the power supply
tolerance is very wide. All inputs are TTL compatible.

• 1,048,576 x I-bit organization
• Silicon-gate, NMOS, single
transistor cell
• Access time (too..,.)
120 ns max. (IIIMll00l).12)
150 ns max. (MB81101J0.15)
• Cycle time (tAd
230 ns min. (MB81101J0.12)
260 ns min. (MB811000015)
• Page cycle time (tpc)
120 ns min. (MB81100l).12)
150 ns min. (MB81101J0.15)
• Single 5V supply, ±10%
tolerance

• Low poww diaslpatlon
550 mW max. (MB81101J0.12)
490 mW max. (MB81101J0.15)
25 mW max. at standby
• Refresh 8 ms/512 eycl.
• RAS-only, ~before-RAS
and hidden refresh capability
• High speed resd-wrlte cycle
capability
• Output unlatched at eycle end
allows two dimensional chip
saleel
• On chip add,.. and data-ln
latch.
•

1-148

Induatry standard la-pin
DIP package

MB8110oo·12
MB8110CJO.15

MB811000 Block Diagram
and Pin Assignment

V__
0

W

Q

m

BLOCK DIAGRAM

RA'------I
CAS"------...-l

CAS

NC

As

Ao

A.

A,

A,

A,

As

As

A,

Vee

Ag

0
As

V"

W

..
..
A,

COLUMN
DeCODER

RAS

CAS

N.C.

A,

N.C.

N.C.

SENSE AMP. It
1I0GATE

A,

Q

A,
, ,048,576 BIT

As

STORAGE CELL

A,

A,

A,

A,

A,

..

A,

A,

A,

A,

VDD

A.

As

--vee

--v"

Absolute Maximum Ratings
Rating

Symbol

Value

Unit

Voltage on any pin relative to V SS

VIN. VOUT

-1 to +7

V

Voltage on Vee relative to Vss

Vee

-1 to +7

V

TSTG

-55 to +150
-55 to +125

Storage temperature

Ceramic
Plastic

PD

Power dissipation
Short circuit output current

·C

1.0

W

50

rnA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended penods may affect device reliability. This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

Recommended Operating
Conditions
(Referenced to Vssl

Value
Typ
Min

Parameter

Symbol

Supply Voltage

4.5
0

Input High Voltage All Inputs

Vr:,r:,
Vss
V IH

Input Low Voltage All Inputs

VIL

-2.0

FUJITSU

1·149

2.4

5.0
0

Max

Un"

Operating Temperature

5.5
0
6.5
0.8

V
V

O·G to +70·G (ambient)

V
V

MB811000·12
MB81100G-15

Capacitance
(T A = 25'C)

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Value
Parameter

Symbol

Mall

Unit

Input Capacitance Ao to AB, D
Input Capacitance RAS, CAS and W

C IN1

7

pF

C IN2

8

pF

Output Capacitance Q

COUT

7

pF

Parameter

Symbol

Min

MB811000·12
Max
Min

OPERATING CURRENT"
Avera~ower Supply Current
ICCl
(RAS, CAS cycling; t RC = Min.)
STANDBY CURRENT
Power Supply Current
ICC2
(RAS/CAS = VI H)
REFRESH CURRENT 1Average Power Supply Current
ICC3
(RAS cycling, CAS= V IH ; t RC = Min.)

Typ

MB81100G-15
Min
Max

Unit

100

90

mA

4.5

4.5

mA

90

80

mA

PAGE MODE CURRENTAverage Power Supply Current
ICC4
(RAS = V IL, CAS cycling; tpc = Min.)

45

40

mA

REFRESH CURRENT 2Average Power Supply Current
(CAS before RAS; t RC = Min.)

90

80

mA

ICC5

INPUT LEAKAGE CURRENT
Any Input, (VIN = OV to 5.5V,
Vcc = 5.5V, Vss=OV,
all other pins not under test = OV)

IlL

OUTPUT LEAKAGE CURRENT
(Data is disabled, VOUT=OV to 5.5V) 10L
OUTPUT LEVEL
Output Low Voltage
(IOL = 4.2 mAl
OUTPUT LEVEL
Output High Voltage
(IOH = - 5.0 mAl

-10

10

-10

10

"A

-10

10

-10

10

"A

0.4

V

0.4

VOL

VOH

2.4

2.4

Note": ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

1-150

V

118811000-12
118.11000-111

AC ~.rac'.rI.tlc.
(Recommended operating
conditions unless otherwise
noted.)

.....

Symbol
Altarna"

·S..ndard
TRVRV

Random ReadlWrite Cycle Time

tREF
t RC

Read·Write Cycle Time

t AWC

TRELREL

Access Time from RAS·'·6
Access Time from CAS·s.6

t RAC

TRELOV

tCAC

TCELOV

tOFF
tT
t RP

TCEHOZ

Parameter
Time between Refresh

Output Buffer Turn off Delay
TranSition Time

RAS
AMi
AMi

Precharge Time
Pulse Width

t RAS
t RSH

Hold Time

CA§ Pulse Width

TRELREL

n
TREHREL
TRELREH
TCELREH

t CAS

TCELCEH
TRELCEH

RAS to CAS Delay Time·'· 7
CA§ to RA§ Sel Up Time

tCSH
t RCO
t CRS

Row Address Set Up Time

t AsR

TAVREL

Row Address Hold Time

tRAH
t ASC

TRELAX

tCAH
t RCS
t RCH

TCELAX
TWHCEL

tRRH

TREHWX

twcs
twp
t WCH

TWLCEL

~HoldTime

Column Address Set Up Time
Column Address Hold Time
Read Command Sel Up Time
Read Command Hold Time Referenced to
Read Command Hold Time Referenced to
Write Command Set Up Time' s

CAS"o

m"o

Write Command Pulse Width
Write Command Hold Time

TRELCEL
TCEXREL

TAVCEL

TCEHWX

TWLWH
TCELWH

Write Command to

FlAS

Lead Time

tAWl

TWLREH

Write Command to

CAS Lead Time

tCWl

TWLCEH

1188ttOOo-12
Min Mall

.88ttOOO-1 II
Mall
Min
8

8
260
325

230
285

0
3
100
120
60
60
120
22
0
0
12
0
20
0
0
20
0

120
60
25
50
100000
100000
60

20
20
50
50
0
20
60

0
3
100
150
75
75
150
25
0
0
15
0
25
0
0
20
0
25
25
60
60
0
25
75

Data In Set Up Time

tos

TDVCEL

Data In Hold Time

IOH

TCELDX

CAS to W Delay"s

Icwo

TCELWL

~ Precharge Time (Normal Cycle)

tcPN

22

25

RAS to ViI Delay·S

tRWO

120

150

Notn:

*1. An inhlal pause of 200 p.S is required after power up, followed by any 8 ftAS~les, before proper device operation is achieved.
" the internal refresh counter Is to be effective. a minimum of 8 ~ before RAS refresh initialization cycles are required.
'"2. AC characteristics 888ume ty = 5 ns.
*3. V,H (Min.) and V'L (Max.) a'8 referenCe IeYeIs for
timing of input signals. Also, transition times are measured between
V,H and V,l'
*4. tACO Is spectflecl 88 a reIarence point only. tf tACO"" IReD (Max.) the specified maximum value of tRAe (Max.) can be met. If
tRCO > 'RCO (Max.) Ihan'RAC In 1 _ by !he amount lhal 'Rco exceeds 'RCO (Max.)
'5. Assumes lhat tRCO > 'RCD (Max.).
'6. Measured wIIh a load equivalent to 2 TTL loads and too pF.

meaamng

'7. tACO (Min.)
*S.

=

'RAH (Min.) + 2 t,. + 'ASC (Min.).

twcs and lew&::, non restrictive operating parameters. and are included in the data sheet as elecrical characteristics only. If
~:.t~.(

.), the cycle is an earty wriIe cycle, and the data out pin wtll remain open circuit (High Impedance) throughout

:ze

:.ere:::,c:::::.da':t':ti==':te~ta

~~ ~~ .::~~
'10. Ei_ tRCH or'RRH must be _ _ tor a . - cycle.

read from the selected cell. tf neither of the

1·151

Unit
ms
ns
ns

150
75

ns

35
50

ns

ns
ns
ns

100000

ns
ns

100000

ns
ns

75

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

MB811000012
MB811000015

AC Charact.rlstlcs
(Recommended opereting
conditions unless otherwise
noted.)

Paramet.r

Not.s

Refresh Set Up Time for CAS Referenced to ~
Refresh Hold Time for CAS Referenced to FiAS
Page Mode ReadlWrite Cycle Time
Page Mode Read-Write Cycle Time
Page Mode CAS Precharge Time
RAS Precharge to CAS Active Time

CAS Precharge Time for CAS before
~ Refresh Cycle

Symbol
Alternat.

·Stendard

t FCS
t FCH
tpc
t pRWC
tce
t RPC

TCELREL
TRELCEX
TCELCEL
TCEHCEH
TCEHCEL
TREHCEL

t CPR

TCEHCEL

MB811000·12
Min Ma ..

MB811000·15
Min
Ma ..

0
20
120
175
50

0
20
150
215
65

20

20

ns
ns
ns
ns
ns
ns

25

30

ns

Unit

Notu: -These symbols are described in IEE:E STD. 662·1980: IEEE Standard terminoloQV for semiconductor memory.

D.scrlptlon

Simplified Timing Requirement
The MB811 000 has improved circuitry that eases timing requirements for high speed access
op!lrations. The MB811000 can
operate under the conditions of
tRCO (max.) = !cAC' thus providing optimal timing for address
multiplexing. In addition, the
MB811000 has minimal hold
times for Addresses (leAH), WriteEnable (tWCH) and Data-In (tOH )'
The MB811 000 provides higher
throughput in inter-leaved memory system applications. Fujitsu
has made the timing requirements that are referenced to
RAS non-restrictive and deleted
them from the data sheet. These
Include tAR, tWCR ' tOHR and tRWO '
As a result, the hold times of the
Column Address, 0 and Was
well es !cwo (CAS to W Delay)
are not restricted by tRCO '
Fast Read-Write Cycle
The MB811000 has a fast readmodify-write cycle which is
achieved by precise control of
the three-state output buffer as
well as by the simplified timings
described in the previous section.
The output buffer is controlled by
the state of Wwhen CAS goes
"low'! When W Is "low': the
MB811000 goes into the early
write mode In which the output
floats and the common 1/0 bus
can be used on the system level.

When IN goes"low", alier lewD
following a CAS transition to
"low': the MB811000 goes into
the delayed write mode. The output then contains the data from
the cell selected and the data
from D is written into the cell selected. Therefore, a very fast
read-write cycle (tRWC = tRcl is
possible with the MB811 000.
Addrese Inputs

A total of twenty binary input address bits are required to decode
any 1 of 1,048,576 cell locations
wHhin the MB811000. Ten rowaddress bHs are established on
the input pins (Ao through A9)
and are latched with the Row Address Strobe (FiAS). Ten column
address bHs are established on
the Input pins and latched with
the Column Address Strobe
(CAS). All row addresses must
be stable on or before the falling
edge of RAS. CAS Is internally
inhibited (or "gated") by RAS to
permit triggering of CAS as soon
as the Row Address Hoid/Time
(tRAH ) specification has been satisfied and the address Inputs
have been changed from row addresses to column addresses.
Write Enable
The read or write mode is selected wHh the W input. A logic
"high" on W dictates read mode.
A logic "low" dictates wrHe mode.

1-152

The data input is disabled when
the read mode is selected.
Deta Input

Data is written into the MB811000
during a write or read-w.!:!!e ~
The last falling edge of W or CAS
is a strobe for the data-i!!JO) register. In a write cycle, if W is
brougllt"low" (wrHe mode) before CAS, 0 is strobed by CAS,
and the set-up and hold times
are referenced to ~. In a readwri~cle, W will be delayed until CAS has made Hs negative
transition. Thus 0 is strobed by
W. and set-up and hold times are
referenced to W.
Oats Output

The output buffer is three-state
TTL compatible wittl a fan-out of
two standard TTL loads. Data out
is the same polarity as data In.
The output is in !..!!!gh Impedance state until CAS is brought
"low'! In a read cycle, or a readwrite cycle, the output Is valid
alier tRAC from transition of i!iA§
when tRCD(max) is satisfied, ~
alier tCAC from transition of CAS
when the transition occurs alier
tRCO(max)' Data remains valid until
~ in returned to "high'! In a
write cycle, the identical sequence occurs, but data is not
valid.

MB81100Q.12
MB811000015

D••crtptlon
(Continued)

Page Mode
Page mode operation permits
strobing the row address into the
MB811000 while maintaining RAS
at a logic low (0) throughout all
successive memory operations in
which the row address doesn't
change, Thus, the power dissipated by the negative going edge
of RAS is saved. Access and
cycle times are decreased because the time normally required
to strobe a new row address is
eliminated.
RA8-0nly Refresh

Refresh of dynamic memory cells
is accomplished by performing a
memory cycle at each of the 512
row-addresses (Ao- As) at least

every 8 ms. RAS-only refresh
avoids any output during refresh
because the output buffer is in
the high impedance state unless
~ is brought "low': Strobing
each of the 512 row-addresses
(Ao - As) with RAS will cause all
bits in each row to be refreshed.
~-only refresh results in a
substantial reduction in power
dissipation.
CAS-befor.RA§ Refresh

CAS-befora-RAS refreshing
available on the MBB11000 offers
an alternate refresh method. If
CAS is held "low" for the~ci
fied period (t Fes ) before RAg
goes to "low': on-chip refresh
control clock generators and the

FUJITSU

1-153

refresh address counter are enabled, and an internal refresh operation takes place. After the
refresh operation is performed,
the refresh address counter is
automatically incremented in
preparation for the next CAS-belore-RAS refresh operation.
HIdden Refresh
A hidden refresh cycle may take
place while maintaining the latest
valid data at the out-put by extending the CAS active time. For
the MB811000, a hidden refresh
cycle is a CAS-befora-RAS rafresh cycle. The internal refresh
address counter provides the refresh addresses as in a normal
~-before-RAS cycle.

M881tOCJO.12
M881tOGO-15

Timing Diagrams
Read Cycle

..

1. .--------------------tRc--------------------~

RAS

VIH
VIL

CAS

VIH
VIL

1..------------- tRAs--------------_lr------:i.
1..----~----~------tCSH------------_rt_~1

~~~------------~~ 1~.~~-----~--------t-Rs-H~-tC-A-S===~~~~~

VIH
A

Vi

Q

~

Don't Care

Write Cycle (Early Write)
~------- __------------_tRC----------------------~

A

Vi

o

Q

twcs5

§WCH--.J

::~ Jk:._t_Ds_'---'--____tD_H_~
_ __::l
VIL
VALID OATA~XXXXXXX)(

I--.
0.850(21.60)
0.876(22.25)

..
1--,.-+-- SEATING PLANE

FUJITSU

1·159

~AX

MB811000.12
MB811000.15

Pecka.e Dimensions
(Continued)
Dimensions in Inches
(millimeter)

2& L_d SOJ Pecke••
.140 (355)MAX
•

•025(O.84)MlN.

,
I~
:Ii

..

0

-liZ

+

~ ~
~~~
. ~

I~
.085(2.25)

.675(17.15)NOM.
(0.81)MAX.

A

1-160

•013(0.33)
.021(0.53)

Advanced Information

FUJITSU

MOS Memories
•

MB811001.12, MB811001·15
1,048,576-Bit Dynamic Random
Access Memory

Description
The Fujitsu MB811001 is a fully decoded, dynamic NMOS random
access memory organized as 1,048,576 one-bit words. The design
is optimized for high speed, high performance applications such as
mainframe memory, buffer memory, peripheral storage and environments where low power dissipation and compact layout are
required.
The MB811001 features "nibble mode" which allows high speed serial access of up to four bits of data. Additionally, the MB811001 offers new functional enhancements that make H more versatile than
previous dynamic RAMs. "CAS-before-RAS" refresh provides an
on-chip refresh capability. Multiplexed row and column address inputs permH the MB811001 to be housed in a Jedec standard 18-pin
dual in-line package or 20 lead SOJ package.
The MB811001 is fabricated using silicon gate NMOS and Fujitsu's
advanced Triple-layer Polysilicon process. This process, coupled
with an innovative stacked capacitor memory cell, permits maximum circuit density and minimal chip size. Dynamic circuitry is
used in the design including dynamic sense amplifiers.
Clock timing requirements are r 'critical, and the power supply
tolerance is very wide. All inputs are TTL compatible.

• 1,048,576 x I-bit organization
• Slllco~ata, NMOS, 81ngle
tran81ator call
• ACC888 time (tRAeI
120 n8 max. (MB811001-12)
150 n8 max. (MB811001-15)
• Cycle time (tAeI
230 n8 min. (MB811001-12)
280 n8 min. (MB811001-15)
• Nibble mode capability for
faster acC888
• Single 5V supply, ±10%
toIeranca
• Low power dla8lpatloll
550 mW max. (MB811001-12)
490 mW max. (MB811001-15)
25 mW max. at atandby

• Refra8h 8 ma/512 eyclee
• RAS-only, CAS-before-RAS
8nd hidden rafreeh capability
• High 8peed read-write eycle
capability
• On chip addrea8 and data-In
latches

1-161

MB811001·12
MB811001·15

MB811001 Block Dlagra...
and Pin Assignment

1'iAS----;~

o

m---~

Voo

a

W
I'iAS

m

HC

Ae
As

As

Vee "-'\_ _ _ _ _ _---',114

IN

o

Voo

W

AU
AS

A.

OUT

N.C.

A.

N.C.

N.C.

As
4 - - VCC

Ae

"--Vss

AO

As

A,

A7

A2

As

A,

As

Vee

A4

Absolute Maximum Ratings
Rating

Symbol

Value

Unit

Voltage on any pin relative to Vss

VIN. VOUT

-1 to +7

V

Vcc

-1 to +7

V

Voltage on Vcc relative to Vss
Storage temperature

-55 to +150

Ceramic
Plastic

Power dissipation

TSTG

-55 to +125

Po

Short circuit output current

'C

1.0

W

50

rnA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operations sections of this data sheet. Exposure to absolute maximum rating condi·
tions for extended periods may affect device reliability. This device contains circuitry to protect the inputs against damage due to
high static voltages or electnc fields. However. it is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

Recommended Operating
Conditions
(Referenced to Vss)

Parameter

Symbol

Supply Voltage

Vee
'Jss
VIH
VIL

Input High Voltage All Inputs
Input Low Voltage All Inputs

FUJITSU
1-162

Value
Min
Typ

Max

Unit

4.5

5.0

5.5

V

II

a

!l

r:J

2.4

6.5

-2.0

0.8

V
V

Operating Temperature
O'C to +70'C ambient

MB811001·12
MB811001-15

Capacitance
(TA 25 "C)

=

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Value
Parameter

Symbol

Mall

Unit

Input Capacitance Ao to Ag, D

C IN1

7

pF

Input Capacitance RAS, CAS and W

C IN2

8

pF

Output Capacitance Q

COUT

7

pF

Parameter

Symbol

OPERATING CURRENT"
Avera~ower Supply Current
(RAS, CAS cycling; t RC Min.)
STANDBY CURRENT
Power Supply Current
(RAS/CAS VIH )
REFRESH CURRENT 1·
Average Power Supply Current
(RAS cycling, CAS V IH ; t RC Min.)
NIBBLE MODE CURRENT·
Average Power Supply Current
(RAS Vll, CAS cycling; t NC Min.)

=

=

=

=

=

=

REFRESH CURRENT 2·
Average Power Supply Current
(CAS before RAS; t RC Min.)

=

INPUT LEAKAGE CURRENT
Any Input, (V IN = OV to 5.5V,
Vcc 5.5V, Vss OV,
all other pins not under test

=

=

=OV)

MB811001·12
Mall
Min

MB811001-15
Mall
Min
90

mA

Icc2

4.5

4.5

mA

ICC3

90

80

mA

Icc4

25

23

mA

80

mA

90

Icc5

III

VOH

-10

10

-10

10

pA

-10

10

-10

10

pA

0.4

V

0.4

2.4

2.4

Note·: ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

1·163

Unit

100

VOL

=-

Typ

Icc1

OUTPUT LEAKAGE CURRENT
(Data is disabled, VOUT = OV to 5.5V) 10l
OUTPUT LEVEL
Output Low Voltage
(Iol = 4.2 mAl
OUTPUT LEVEL
Output High Voltage
(lOH
5.0 mAl

Min

V

MB8'11001-f2
M88'11oo1.15

AC Characlerlallca
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Notea

Time between Refresh
Random ReadlWrite Cycle Time
Read·Write Cycle Time

Access Time from RAS'4.S
Access Time from CAS's.s
Output Buffer Turn off Delay
Transition Time

RAS Precharge Time

Symbol
Alternate

·Stendard

M88'11001·12

M88'11oo1.15

Min

Min

Ma.
8

Ma.

Unll

8

ms

tREF
t RC

TRVRV
TRELREL

230

t RWC

TRELREL

285

tRAC
t CAC

TRELOV

120

150

ns

TCELOV

75

ns

tOFF
tT

TCEHOZ

60
25
50

35
50

ns

100000

ns

0
3
100

n

260
325

0
3

ns
ns

100

tRP
t RAS
t RSH

TREHREL
TRELREH
TCELREH

120
60

~ Precharge.T'me (Normal Cycle)

tCPN

TCELCEL

22

CAS Pulse Width

tCAS

TCELCEH

100000

tCSH

TRELCEH

75
150

100000

CAS Hold Time

60
120

tRCO

TRELCEL

60

TRELWL

25
150
0

75

IRWD
tCRS
t ASR

22
120
0

TRELAX

Column Address Set Up Time

tRAH
t ASC

Column Address Hold Time

tCAH

TCELAX

Read Command Set Up Time

tRCS

TWHCEL

Read Command Hold Time Referenced to CXS'10

tRCH

TCEHWX

Read Command Hold Time Referenced to FIX§'10
Write Command Set Up Time's

tRRH

TREHWX

twcs
twp
t WCH

TWLCEL

RAS Lead Time

tRWl

TWLREH

Write Command to CAS Lead Time

tCWl

TWLCEH

Data In Set Up Time

tos

TDVCEL

Data In Hold Time

tOH

TCELDX

tcJ.o
t FCS
t FCH

TCELWL

RAS Pulse Width

W

Hold Time

RAS to CAS Delay Time'4.7
~ to W Delay Time '8
CAS to RAS Set Up Time
Row Address Set Up Time
Row Address Hold Time

Write Command Pulse Width
Write Command Hold Time
Write Command to

CAS to iN Delay'S
Refresh Set Up Time for CAS Referenced to

RAs

Refresh Hold Time for CAS Referenced to RAS

-

-These symbols are described

In

TCEHREL

100000

TAVCEL

0
20
0
0
20
0
20

TWLWH
TCELWH

20
50
50
0
20

TCELREL

80
0

TRELCEX

20

IEEE STD, 662-1980: IEEE Standard terminology for semiconductor memory

., An initial pause of 200 ,",8 is required after power up. followed by any 8 RAS cycles. before proper device operation is achieved.
If the internal refresh counter is to be effective. a mmimum of 8 CAS before RAS refresh initialization cycles are required.
-2 AC characteristics assume IT '" 5 "S.
-3 VIH (Min.) and VIL (Max.) are reference levels tor measuring timing of input signals. Also, transition limes are measured between
VIH and VIL'
-4 tRCD is specified as a reference point only. If IRCO !$ IACO (Max.) the specified maximum value of tRAC (Max.) can be met. II
tRCO .> tRCO (Max.) then tRAC is increased by the amount that tReO exceeds IRCO (Max.).
'5 Assumes that lRCO > 'ACO (Max.).
'S Measured with a load _ivalen1lO 2 TIL loads and 100 pF.

=:n re:

'7 lRCO (Min.) = lRAH (Min.) + 2tT + 'ASC (Min.).
-8

::g: ~~~~~.~:
the entif----.:!'--+-E 1
o
~

~

a:
w

.9

;(

t

30

/

20

o
o

V

/

a

V

40

C1
Z

~
a:

.s
I-

w

2
3
4
5
I IIRC. CYCLE RATE (MHz)

30

4

~

4.5

5

5.5

6

VCC. SUPPLY VOLTAGE (V)

Fig. 8 - STANDBY CURRENT
vs SUPPLY VOLTAGE

VC~

TA =

;(

= 5.JV
50 -IR~S = lOOns

.s

~5°C

4

I-

z

w

w

IRC = 200n.

a:
a:

40

:>

3

>
a>
o
z

2

o

C1

z

IRC ='250ns

;i

IRC J300ns

i=

30

«

w

Iii

~

U

- ---

~

20

6

Z

.9

100

o

U
.9

a:
a:

a

80

C1.

Fig. 7 - OPERATING CURRENT
vs AMBIENT TEMPERATURE
;(

60

Z

a:
a:

,/

10

40

TA = 65°C
50 f---IRC :: 200n.

w

I.-

40

~

U

1

Vcc = 5.5V
50 I-- TA = 25°C
tRAS = lOOns

20

Fig. 6 - OPERATING CURRENT
vs SUPPLY VOLTAGE

Fig. 5 - OPERATING CURRENT
vs CYCLE RATE
;(

0

T A. AMBIENT TEMPERATURE (OC)

VCC. SUPPLY VOLTAGE (V)

w

V

1:
4

I-

V

/

0

w

1:

.s

~

w
0

.......

0

::;

ED

Cl

z

~

2

w

a:
a:

r--- """'-

tRAS = lOOn.
40

::l

u

J:

r-.

en
w
u.

a:
w

30
20

a:

, ./'

M
10
()

N

()

.9

Vcc = J.5V

50 f--- T A = 25°C

IZ

I-

.9

1
-20

0

20

40

60

80

o

100

T A , AMBIENT TEMPERATURE (OC)

Fig. 11 - REFRESH CURRENT
vs SUPPLY VOLTAGE

«

E
w

a:

gs

30

u
J:

en
w

B:

w

20

a:

«
E

-----

5.~V

::l
U

tRC = 200n.
30
tRC = 250n.

J:

en
w
a:
u.
w

20

a:

z
a:
a:

::l

u
w

4.5

5

5.5

6

-20

«

E

w

l!l

30

..

()

.9

40'--tpc = 105n.

i3

30

w

10

o

Cl

V

o

:i:

./

20

«

... /
2

w

V

60

80

100

l!l

20

-

-

«

Il.

~

.9
4

40

1 o
TA = 25 C

I-

z
w
a:
a:

0
:i:

20

Fig. 14 - PAGE MODE CURRENT
vs SUPPLY VOLTAGE

Vc~

Cl

0

T A , AMBIENT TEMPERATURE (oC)

= 5.5v'
40 - T A =25°C
tCAS = SOn.

Il.

300ns-

10

Fig. 13 - PAGE MODE CURRENT
vs CYCLE RATE

w

tRC

M
()

Vcc, SUPPLY VOLTAGE(V)

I-

6

vdc =
40 f--tR:"S = lOOns

w

a:
a:

.9

4

«

4
2
l/tRC, CYCLE RATE (MHz)

IZ

M
()
.9 10

E

./

Fig. 12 - REFRESH CURRENT
vs AMBIENT TEMPERATURE

TA = J5°C
40 f--T RC = 200ns

IZ

/

........- "

6

8

10

4

10

l/tpc. CYCLE RATE (MHz)

1-187

4.5
5
5.5
Vcc, SUPPLY VOLTAGE(V)

6

MB 8264A-l0
MB 8264A-12
MB 8264A-15

Fig. 15 - PAGE MODE CURRENT
vs AMBIENT TEMPERATURE
~

£

fZ

!

u

z>

<>:V> UJ 3"0
v>t:J
UJ<>:

trf0-'
00

;....

tpc -

,...

20

t:J

~

I'

0

W

~

~

~

I<>:

o

100

4

4"0

VC~" 5.dv

f-

o
~ 5:

<>:-

~ts
UJ<>:
a:: f-

025
~>

6

i c

T A " 2 50

o

I

3,0

~5: 3.0

2 .0

VIH(Min)-

IV> ;:;:;
5~
'fI ~ 25

VIL(Max)

>:)

tr,

>

VIH(Min)
2"0

='f-

>n.

~~

~ 1"0

VI L (Max)

1.0

<>:

<>:

I

I

>

5.5

Fig. 18 - RAS, CAS AND WE INPUT VOLTAGE
vs SUPPLY VOLTAGE

i~

-,f-

z

5

4"0

-:)

o

4.5

Vcc, SUPPLY VOLTAGE (V)

Fig, 17 - ADDRESS AND DATA INPUT VOLTAGE
vs AMBIENT TEMPERATURE
<>:

VI L (Max)

;:': 1"0

T A , AMBIENT TEMPERATURE (oC)

«

~

:>0

I

W

:: ~

o~

1

~O

VIH(Min)_

2"0

>0-

t pC " 200ns
10

>

'f-

=':)

J150ns_

I

<>:
n.

.:u

<>:

tpC" 105ns

I--

0
0

T A" 15°C

0_

30 - "

UJ

:;;
UJ

4.0
1

I

UJ

:>

o

"5"0~
VIH(Min)_

,I,

1

60

80

V IL (Max)

o

-20

0

20

40

4.5

5

5.5

Vcc, SUPPLY VOLTAGE (V)

Fig. 19 - RAS, CAS AND WE VOLTAGE
vs AMBIENT TEMPERATURE
vcl

o

4

-20
0
20
40
60
80
100
T A . AMBIENT TEMPERATURE (OC)

4"0

FUJITSU
1111111111111111111111111111111111111111111111111111

Fig. 16 - ADDRESS AND DATA INPUT VOLTAGE
vs SUPPLY VOLTAGE

VCC" 5.5V
40 -tCAS" 50ns

tr
tr
:)

I11111111111111111111111111111111111111111I111111111

100

T A , ANBIENT TEMPERATURE eC)

1-188

6

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

MB 8264A-l0
MB 8264A-12
MB 8264A-15

Fig. 20 - CURRENT WAVE FORM DURING POWER UP

~~
&~

i;l.~

»
5
0

0...1
00

»
~

z

20

~~

t:::::/l
VI

r-T~

= 250

»

b

~

w
~

15

::l

J

15

::l

u;{

(

::l

5

u> ~ 10

RM = CAS = VSS

~ E 10

0.0.
III

20 r-Tj = 25 0

Z

w

~

50t71

.~

0...1
00

J_.I

'I/'

RAS = CAS = VSS

~0.
::l

III

RAS = CAS = Vee

(

5

U
.2

-J-J

RAS = CAS = Vee

J
/

I

lOlLS/Division

I

100lJs/Division

Fig. 21 - CURRENT WAVE FORM DURING POWER UP
(ON MEMORY BOARD)

»
...1o.w
o.(!l

~

80

Z

w
a:
a:

t=2h
tRe = 270ns-

n

fZ

~;{

...IE

60
40

::l

III

20

\

\

80 -

T A I=25od

tRe = 270ns

w
a:
60
a:
::l
u;{

::l

Do
Do

t71

i;l.~ o
0...1
00
»

>
E
...1_

MB 8264A + DecOUrng
~apacitor (O}",F)

40

Do
Do

::l

III

U
.2

DecoJpling c~pacitoi
(O.l",F) only

20

MB 8264A + DecoluPlin
/ i\... capacitor (0.1 ",F)

~

100",s/Division

20us/Division

Fig. 22 - SUBSTRATE VOLTATE
vs SUPPLY VOLTAGE (DURING POWER UP)

1

'\
\\

TA =1 25oC I
RAS = CAS = Vee

r--....

............

-4

DecoUlpling c~paCito;
(O.l",F) only

r--

o
SOilS/Division

1-189

g

MB 8264A-10
MB 8264A-12 FUJITSU
MB 8264A-15

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Surfix : -ZI
16-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
(CASE No_ : DIP-16C-C04)

rn

::~'"1 ~ ~ ~ ~ ~ ~ ~Ij:;: '32SIlJ~:==-_--+-J
.313 (7.9S1

I.

r--.

--j

.754119.1S1
.788120.021

JI

.300(7.621TVP

./

OSO (1.271MAX

~ ~ IVI~~ U ~ ~ ~~

JII

.090(2.291
.110(2.791

.03210.811
TVP

~ ':::(:30::~AX
.1S0(3.811
.02010.SlI
.OSO(1.271
Dimensions in
inches (millimeters)

.01310.331
.023 (0.S81

Standard 16-pin Plastic DIP (Surfix : -PI
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M03)

::::::1:: ::: :)5~
I.

.-1-

...--..,,-==--.'0

0_

1so

.29017.37)
.31017.87)

1

.748119.0)
.776119.7)

.047(1.20)
.05911.50)

Dimensions in
inches (millimeters)

1·190

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

MB 8264A-10
MB 8264A-12
MB 8264A-15

PACKAGE DIMENSIONS
Standard 18·pad Ceramic LCC (Surfix : -TV)

IS-PAD CERAMIC (FRIT SEALI LEAD LESS CHIP CARRIER
(CASE No_' LCC-ISC-F021
.1125(2.86)

6;------1
~

PIN NO.1 INDEX

~

R.012W.30ITYP

~PLa)l~-~-=~~~=r~-+-·
12Si318)
TYP

1

R 008{O.20lTYP

r

i

L __.~28~O(~7.1~1(:--_1
.295(7.49)

·260(6.60)
TYP

(18PL-CST-

I

420(10.67)
435(11.05)

.200(5.08)
TYP

I

~-~
~

O

TYP

050('-3..;4.J
TYP

100(2.54IMAX

I

I

i

i r---------__+_
.150(3.81 lTYP

.04511.14)
TYP~

.0675(1.71)
---,=yp~

r-:-19514.95lTYp--l
Dimensions in inches
(millimeters)

~Shape of Pm 1 Index' Subject to change without notice

1·191

Preliminary

FUJITSU

MOS Memories
•

MB8264A-12-W, MB8264A-15-W
NMOS 65,536-Bit Dynamic
Random Access Memory With
Wide Temperature Range

D••crlptlon
The MB8264A·W is a 64K x 1 dynamic RAM Intended for operation
over the case temperature range -55·C to 110·C. The part is also
available with Fujitsu's 883B high reliability screening.
The MB8264A·W design has been optimized for high speed high
performance applications such as mainframe memory, buffer
memory, and peripheral storage where low power dissipation, com·
pact layout, or wide temperature range operation are required.
The MB8264A·W has fully TIL compatible inputs and output. It
operates on a single +5 V ± 10% power supply. An on chip
substrate bias generator provides high performance operation. The
MB8264A·W contains on·chip latches for the address inputs and
for the data input.
The MB8264A·W is fabricated with Fujitsu's advanced silicon gate
NMOS double layer polysilicon process. This process along with
the use of single transistor storage cells permits maximum circuit
density and minimum chip size. Multiplexed row and column ad·
dressing allows the MB8264A-W to be packaged in a standard 16-pin

DIP.

Feetur••
• Wide Temperature Range
TC., -55·C to 110·C
• 65,536 x 1 organization
• Row Access Time:
120 ns max. (MB8264A·12·W)
150 ns max. (MB8264A·I5-W)
• Cycle Time:
230 ns min. (MB8264A·12·W)
280 ns min. (MB8284A·I5-W)
• Low Power (Active)
305 mW max. (MB8284A·12·W)
275 mW max. (MB8284A·I5-W)
33 mW max. (Standby)

•
•
•
•
•

1 msl128 cycle refresh
RAS-Only and Hidden Refresh
Read·Modlfy·Wrlte capability
Page Mode capability
Common 1/0 capability using
the early write operation
• Output unlatched at cycle end
allows extended page boundary
• tAR, tWCR, tDHR are
eliminated
• 883B processing available

1·192

MB8284A-12-W
MB8284A-11S-W

Block Diagram and
Pin A •• lgnmenh

m--r~~------,

o N.C. V,, CAS
1

18

17

W

16 Q

"'h

RAS

0(")

...

N.C.

...,
..

.:.

.'<''''-!'1J#-

DOUT

~Don'lca ..
FUJITSU

1·197

M88284A·12.W
M88284A.15·W

Timing Diagrams, Continued
Pag. Mod. Read Cycl.
1~4~------------------IMS-------------------;~

RAS

CAS

VIH

-

vlL

-

VI" -

V1L

-

IZ1I Valid Data
Pag. Mod. Wrl18 Cyol.

VOH _

VIL

-*---.d.\

-

'f-o----f

ADDRESSES

VOH_==="7!!.1
VOL -DJ.~.o.~~~~.DJ.~.,Q,~+"-~~~~¥:-04W.-:---'~~D.I.~~~~

DON

VOH - =~'?..lr-ur.mf'

V1L

-

~Don'tca..

FUJITSU

1·198

MB 8265A-l0
MB 8265A-12
MB 8265A-15
65.536-BIT DYNAMIC RANDOM ACCESS MEMORY
The Fujitsu MB 8265A is a fully decoded, dynamic random access memory
organized as 65,536 one-bit words. The design is optimized for high-speed,
high performance applications such as mainframe memory, buffer memory,
peripheral storage and environments where low power dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MB 8265A to be
housed in a standard 16 pin DIP and 18 pad LCC. Pin-outs conform to the
JEDEC approved pin out.
The MB 8265A is fabricated using silicon gate NMOS and Fujitsu's advanced
Double-Layer Polysilicon process. This process, coupled with single-transistor
memory storage cells, permits maximum circuit density and minimal chip size.
Dynamic circuitry is employed in the design, including the sense amplifiers.

CERAMIC PACKAGE
CERDIP
DIP-16C-C04

Clock timing requirements are non-critical, and power supply tolerance is very
wide. All inputs and output are TTL compatible.
•

65,536 x 1 RAM, 16 pin DIP/18
pad LCC

•

Offers two variations of Hidden
refresh

•

Silicon-gate, Double Poly NMOS,
single transistor cell

•

Read-Modify-Write, and
Page-mode capabil ity

•

Row access time,
100 ns max (MB 8265A-10)
120 ns max (MB 8265A-12)
150 ns max (MB 8265A-15)

•

Common I/O capability using
Early Write operation

•

Output unlatched at cycle end
allows extended page boundary
and two-dimensional chip select

•

On-chip latches for Addresses and
Data-in

•

tAR, t WCR , tOHR are eliminated
Standard 16-pin Ceramic (Cerdip)
DIP: Suffix-Z
Standard 16-pin Plastic
DIP: Suffix-P
Standard 18-pad Ceramic
LCC: Suffix-TV

•

Cycle time,
190 ns min (MB 8265A-10)
230 ns min (MB 8265A-12)
260 ns min (MB 8265A-15)

•

Single +5V Supply, ±10% tolerance

•

Low power (active)
275 mW max (MB 8265A-l0)
248 mW max (MB 8265A-12)
220 mW max (MB 8265A-15)
25mW standby (max)

•

2 ms/128 refresh cycle

•

RAS-only and R FSH (pin 1)
refresh capability

•

PLASTIC PACKAGE
DIP-16P-M03

Voltage on any pin relative to Vss
Voltage on V CC supplV relative to Vss

Storage temperature

I
I

Power dissipation
Short circuit output current

DOUT

t~t:r~!~J

-WE 31-,

-<
RAS 41

Svmbol

Value

Unit

NC

V IN , VOUT

-1 to +7

V

A2

VCC

-1 to +7

V

Ceramic

Pastic

PIN ASSIGNMENT

iiFSH
OlrtiVss CAS

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

LCC-18C-F02: See Page 1-218

-55 to +150
TSTG

Po

-55 to +125
1.0
50

~l

Ao 61

TOP
VIEW

!J
fa Tgl1"Or;11

°c

A,.I A7 AS

W

LCC PAD CONFIGURATION: See Page 1-218,

Vee

mA

This device contains circuitry to protect the

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

1-199

inputs against damage due to high static volt-

ages or electric fields. However. it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi·

mum rated voltages to this high impedance
circuit.

1IIIIIIIIIIIIIIIImlllllllllllllillmlmlllili

FUJITSU
1111111111111111111111111111111111111111111111111

MB 8265A-10
MB 8265A-12
MB 8265A-15

Fig. 1 - MB 8265A BLOCK DIAGRAM

r-I

CLOCK GEN.
NO.1

~

REF.
CONTROL
CLOCK

Ao-

r--'\

As-

,.

SENSE AMPS
I/O GATING

f~
r-'-- _

A2-

A4-

f--

DATA
OUT
BUFF.

-

f=- lL

-

OC

0

OCLL
OLL
O:::l

"'"

r-

,

w
0

"'oc
"''''
Ww

A6-

DATA
IN
BUFF.

,

CLOCK GEN.
NO.2

COLUMN
DECODER

rv

A1-

A3-

I--

I

INTERNAL
ADDRESS
COUNTER

~.

WRITE
CLOCK
GEN.

U

A
'-,I

A,-

w
0

r--

65,536 BIT
STORAGE CELL

DOUT

:;:
0

SUBSTRATE
BIAS GEN.

OC

--

-Vee
-Vss

CAPACITANCE

(TA = 25°C)

Typ

Max

Unit

CIN1

5

pF

Input Capacitance RAS, CAS, WE, RFSH

C IN2

8

pF

Output Capacitance

CoUT

7

pF

Parameter
Input Capacitance Acto A"

DouT

Symbol
DIN

1·200

MB 8265A-l0
MB 8265A-12
MB 8265A-15

mllllllllllllllllllllllllllllllllllillmllllllill

FUJITSU
1111111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter

Symbol

Typ

Min

Max

Unit

Vcc

4.5

5.0

5.5

V

Vss

0

0

0

V

Input High Voltage, all inputs

V 1H

2.4

6.5

V

Input Low Voltage, all inputs

V 1L *

-1.0

0.8

V

Supply Voltage

Operating
Temperature

O°C to +70°C

Note * : The device can withstand undershoots to the -2V level with a pulse width of 20 ns.

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Symbol

Parameter
OPERATING CURRENT*
Average power supply current
(RFSH = V 1H , RAS, CAS cycling; tRC
STANDBY CURRENT
Standby power supply current (RAS

=min)

MB 8265A-12

REFRESH CURRENT 2*
Average power supply current
(RAS = CAS = V 1H , RFSH cycling; tFC

ICCI

MB 8265A-15

4.5

35

=min)

mA

35
32

Icc4

M88265A-15

28

MB 8265A-10

42

MB 8265A-12

mA

31

MB 8265A-10

=min)

mA

38
ICC3

MB 8265A-15

MB 8265A-12

Unit

40
ICC2

MB 8265A-12

PAGE MODE CURRENT*
Average power supply current
(RAS = V 1L , RFSH = V 1H , CAS cycling; tpc

INPUT LEAKAGE CURRENT
Input leakage current, any input
(OV ~ V 1N ~ 5.5V, Vcc = 5.5V, Vss
not test =OV)

50
45

MB 8265A-10

=min)

Max

MB 8265A·10

= CAS = RFSH = V 1H )

REFRESH CURRENT 1*
Average power supply current
(CAS = RFSH = V IH, RAS cycling; tRc

Min

38

Iccs

MB8265A-15

mA

mA

34

lULl

-10

10

/J.A

OUTPUT LEAKAGE CURRENT
(Data out is disabled, OV ~ V OUT ~ 5.5V)

IO(L)

-10

10

/J.A

OUTPUT LEVELS
Output high voltage (lOH = -5mA)
Output low voltage (lOL =4.2mA)

V OH
VOL

2.4

=OV, all other pins

0.4

Note*: Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open.

1·201

V

1111111111111111111111111111111111111111111111111

MB 8265A-l0

FUJITSU MB 8265A-12

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~I MB 8265A-15

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted
Parameter

I!mmI

I

IN.dttSl"~lt$I

Symbol

MB 8265A-l0
Min

Max

MB 8265A-12

MB 8265A-15

Min

Min

Unit
Max

Max

Ti me between Refresh

tREF

Random ReadlWrite Cycle Time

tRc

190

230

260

ns

Read-Write Cycle Time

t RwC

230

265

280

ns

Page Mode Cycle Time

tpc

105

120

145

ns

t PRWC

135

Page Mode Read-Write Cycle Time

2

2

155

2

180

ms

ns

Access Time from liAS

~[§J

t RAC

100

120

150

ns

Access Time from CAS

I§lI§J

t CAC

50

60

75

ns
ns

Output Buffer Turn Off Delay

tOFF

0

30

0

35

a

40

Transition Time

tT

3

50

3

50

3

50

RAS Precharge Tim

tRP

80

"RAS Pulse Width

t RAS

RAS" Hold Time

t RSH

~Precharge Time (Page mode only)

'CAS" Precharge Time (All cycles except page mode)
CAS Pulse Width
CAS Hold Time

100

100

100
10000

120

10000

150

ns
ns

10000

ns

"50

60

75

ns

tcp

45

50

60

ns

t CPN

20

20

25

tCAS

50

10000

60

50

20

10000

75

60

25

100

tRCO

20

t CRP

0

0

0

ns

Row Address Set Up Time

t ASR

0

0

0

ns

Row Address Hold Time

tRAH

10

10

15

ns

0

0

ns

1ZIf§J

150

ns

tCSH

RAS to CAS Delay Time
CAS to RAS Precharge Time

120

ns
10000

ns
75

ns

Column Address Set Up Time

t ASC

0

Column Address Hold Time

tCAH

15

15

20

ns

Read Command Set Up Time

t RCS

0

0

0

ns

tRCH

0

0

0

ns

RAS \WI

tRRH

20

20

20

ns

~

twcs

0

0

0

ns

Write Command Hold Time

tWCH

20

25

30

ns

Write Command Pulse Width

twp

20

25

30

ns

Write Command to RAS Lead Time

t RWL

35

40

45

ns

CAS Lead Time

tCWL

35

40

45

ns

tos

0

0

0

ns
ns

Read Command Hold Time Referenced to CAS
Read Command Hold Time Referenced to
Write Command Set Up Time

Write Command to

n

Data In Set Up Time
Data In Hold Time
CAS to WE Delay
RAS to WE Delay

Ii
ri1

RAS Precharge to CAS Hold Time (RAS-only refresh)

tOH

20

25

30

!cwo

40

50

60

ns

tRWO

90

110

120

ns

tRPC

20

20

20

ns

1-202

MB 8265A-l0
MB 8265A-12
MB 8265A-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted) INOtES 1" :2! 31
Parameter

~

MB 8265A-l0
Symbol

Min

Max

MB 8265A-12

MB8265A-15

Min

Min

Max

Unit

Max

i1FSR Set up Time Referenced to RAS

t FSR

90

100

100

ns

RAS to RFSH Delay (RFSH refresh)

t RFo

90

100

100

ns

RFSH Cycle Time (RFSH refresh)

t FC

200

230

260

ns

120

150

ns
ns

RFSH Pulse Width (RFSH refresh)

t FP

100

tFI

90

100

100

RFSH to RAS Delay

[j]

tFRo

20

30

40

ns

RFSH Hold Time

[j]

t FSH

30

40

50

ns

RFSH Inactive Time (RFSH refresh)

Notes:

[j]

An initial pause of 200 fJS is required after power-up
followed by any 8 RAS or R FSH cycles before proper
device operation is achieved_
If internal refresh counter is to be effective, a mininum of 8 active RFSH initialization cycles is required_ The internal refresh counter must be activated
a minimum of 128 times every 2 ms if the RFSH
refresh fUnction is used_
If the RFSH refresh function is not used, RFSH (pin 1)
pin can be open_

[i]

[ID t Rco (min) = tRAH (min) + 2tT (t T = 5ns) + t ASC (min)
[ID twcs, tcwo and tRWO are not restrictive operating
parameters. They are included in the data sheet as
electrical characteristics only. If twcs~twcs (min),
the cycle is ·an early write cycle and the data out pin
will remain open circuit (high impedance) throughout
entire cycle.
If tcwo~tcwo (min) and tRwO~tRWO (min), the
cycle is a read-write cycle and data out will contain
data read from the selected cell. If neither of the above
sets of conditions is satisfied the condition of the data
out is indeterminate.

III AC characteristics assume tT = 5ns_
!1l V 1H (min) and V 1L (max) are reference levels for

measuring timing of input signals. Also, transition times
are measured between V 1H (min) and V 1L (max.).

III Assumes

that tRCO ~ tRCO (max). If tRCO is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that t RCO
exceeds the value shown.

III Assumes that tRco ~ tRCO (max).
111 Measured with a load equivalent to

Operation within the tRCO (max) limit insures that
t RAC (max) can be met. tRCO (max) is specified as a
reference point only; if t RCO is greater than the
specified tRco (max) limit, then access time is controlled exclusively by tCAC.

IH!l

Either tRRH or t RCH must be satisfied for a read cycle.

~ RFSH counter test read/write cycle only.
2 TTL loads and

100 pF.

1·203

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

MB 8265A-l0
MB 8265A-12
MB 8265A-15

Read Cycle

RAS

V'H-

=r--7+---T,
'--+-------....,..--t'

V'L -

ADDRESSES

DOUT

V'HV'L-

VOH- _ _ _ _ _ _ _ HIGH_Z·_ _ _ _ _ _-\I

~--=;~'---'I

VOL

£Ill Don't Care

Write Cycle (Early Wirte)

tCRP

ADDRESSES

DOUT

~::..::-

VOH
VOL-

------------HIGH-Z------------•

1-204

Don't Car.

MB 8265A-10
MB 8265A-12
MB 8265A-15

Read-Write/Read-ModifY-Write Cycle

~~tF~S~R~__________________ tRWC ________________________-1
~------------------tRAS--------------------~

~____~

tCSH
tRSH
- -__+-------------tCAS----------~~

ADDRESSES

~::-=J-----tcwo---------I

LtCAC

1-----------tRAC-----~

o

Don't Car.

m

Don't ear.

Page Mode Read Cycle

~ Valid Data

1-205

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111

MB 8265A-l0

FUJITSU MB 8265A-12
1111111111111111111111111111111111111111111111111

MB 8265A-15

Page Mode Write Cycle

VOH- _ _ _ _ _ _ _ _ _ _ _ HIGH_Z _ _ _ _ _ _ _ _ _ _ _ _ _ __

DOUT

VO L -

EJ] Don't Ca ••
Page Mode Read-Write Cycle

ADDRESSES

DOUT

I'll Don't Ca••
1·206

MB 8265A-l0
MB 8265A-12
MB 8265A-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

RAS-only Refresh Cycle
WE, DIN=Don'tcare, A7=VIH orVIL

Note: RFSH=VIH,

VIH
VIL-

RAS

ADDRESSES

(Ao to As)

VIHVIL-

If'"A"~'' '"11--.-----tRP---I:~
~~

-tASR~

--------~)

ROW
ADDRESS

Kr-----~--~------------

-

,'--------

CAS"

V 1H VIL-

DOUT

VOH-----------HIGH-Z------------VOL-

/

D

Don't ear.

RFSH Refresh Cycle
Note: CAS = V 1H , WE, DIN = Don't care

,,,"=11-

VIH------",L
V IL -

ADDRESSES

~:~------~!: : : : . ,.-.-_-_-_tF_C::::::::-::1

,.,. .tA_S,. : x

_ _-:""'...--,..,.
•.•..

!k

VOH-_ _ _ _ _ _ _ _ _ _ _ HIGH_Z _ _ _ _ _ _ _ _ _ _ _ _ __
DOUT

VOL-

o

1-207

Don't Care

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

MB 8265A-l0
MB 8265A-12
MB 8265A-15

Hidden RAS only Refresh Cycle

Rm1

VIHVIL-

RAS

V IH V IL -

CAS

V IH V IL -

El!l Don't Care
Hidden RFSH Refresh Cycle

tCRP

VIH VIL -

--r-----J..'1<-_-+-_______________--'

VIH-

--+---+-+---t--~

VIL -

l<----"r

tR

ADDRESSES VIHVI L - =~"-,,",=a-

DOUT

~g~=-HIGH.Z--~-------~~~.:...------~
•

1-208

Don't Care

MB 8265A-l0
MB 8265A-12
MB 8265A-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

RFSH Counter Test ReadlWrite Cycle
Note: DOUT is the waveform in Read or Read Modify Write Cycles.
tFP
t FI
VIH-------..J
VIL-

j - - t RS H

tRCD----j

+ ______

VIH- _ _ _ _ _ _ _ _ _ _

~

I

1-----tCAS-----.o-l

j,_ __

VIL -

J:-------.....,,.....,.-,.....,.-

V IH- ~-,.,...------....:----_:.I..lt_±:!_,...,.",.,-:-:--.l
ADDRESSES VIL- ...._ _ _ _ _......_ _--:_ _ _ _-"f 1'-'-i":"~;;:.;;...11 '"_ _ _ _ _ _ _-!-_ __

WE

VIH VIL -

DIN

VIHVIL -

DOUT

VOH VOL -

D

Don't Care

DESCRIPTION
Address Inputs:
A total of sixteen binary input address
bits are required to decode any 1 of
65536 storage cell locations within the
MB 8265A. Eight row·address bits are
established on the input pins (Ao
through A7) and latched with the Row
Address Strobe (RAS)' The eight
column-address bits are established on
the input pins and latched with the
Column Address Strobe (00). All
input addresses must be stable on or
before the falling edge of RAS. 00 is
internally inhibited (or "gated") by
RAS to permite triggering of 00 as
soon as the Row Address Hold Time
(tRAH) specification has been satisfied
and the add ress inputs have been
changed from row-addresses to columnaddresses.

Write Enable:
The read mode or write mode is selected
with the WE input. A high on WE
selects read mode and low selects write
mode. Data input is disabled when read
mode is selected.
Data Input:
Data is written into the MB 8265A during a write or read-write cycle_ The later
falling edge of WE or CAS is a strobe
for the Data In (DIN) register. In a write
cycle, if WE is brought low (write
mode) before CAS, DIN is strobed by
CAS, and the set-up and hold times are
referenced to CAS. In a read-write
cycle, WE can be low after CAS has
been low and CAS to WE Delay Time
(tCWD) has been satisfied. Thus DIN is
strobed by WE, and set-up and hold
1-209

times are referenced to WE.
Data Output:
The output buffer is three-state TTL
compatible with a fan-out of two stand·
ard TTL loads. Data-out is the same
polarity as data-in. The output is in a
high impedance state until CAS is
brought low. In a read cycle, or readwrite cycle, the output is valid after
tRAC from the falling edge of RAS
when tRCD (max) is satisfied, or after
tCAC from the falling edge of CAS when
the transition occurs after tRCD (max).
Data remains valid until CAS is returned
to a high. In a write cycle the indentical
sequence occurs, but data is not valid.
Page Mode:
Page-mode operation permits strobing

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

MB 8265A-l0
MB 8265A-12
MB 8265A-15

the row-address into the MB 8265A
while maintaining RAS at low throughout all successive memory operations in
which the row-address doesn't change.
Thus the power dissipated by the falling
edge of RAS is saved. Further, access
and cycle times are decreased because
the time normally required to strobe a
new row-address is eliminated.
Refresh:
Refresh of the dynamic memory cells is
accomplished by performing a memory
cycle at each of the 128 row-addresses
(Ao - A 6 ) at least every two milliseconds. The M B 8265A offers the
following three types of refresh.
1) RAS-only Refresh;
RAS only refresh avoids any output
during refresh because the output buffer
is in the high impedance state unless
CAS is brought low. Strobing each of
128 row-addresses with RAS will cause
all bits in each row to be refreshed.
Further RAS-only refresh results in a
substantial reduction in power dissipation. During RAS only refresh, either
V 1L or V 1H is permitted for A 7 .
2) R FSH Refresh;
RFSH type refreshing available on the
MB 8265A offers an alternate refresh
method: (1) When RFSH is brought low
(active) during RAS is high (inactive),
on-chip refresh control clock generators
and a refresh address counter are
enabled and an internal refresh operation takes place.
(2) When R FSH is brought high (inactive). the internal refresh address
counter is automatically incremented in
preparation for the next R FSH refresh
cycle. Only RFSH activated cycles
affect the internal address counter.
The use of RFSH type refreshing elimi-

nates the need of providing any additional external devices to generate refresh addresses. Refer to the Fig. 2 for
the example of RFSH refresh.
3) Hidden Refresh;
Hidden Refresh Cycle may take place
while maintaining latest val id data at the
output by extending CAS active time
from the previous memory read or cycle
or read-write.
The MB 8265A offers two types of Hidden Refresh. They are referred to as
Hidden RAS-only Refresh and Hidden
R FSH Refresh.
A) Hidden RAS-only Refresh
Hidden RAS-only Refresh is performed
by holding CAS at V 1L and taking RAS
high and after a specified percharge
period (tAP). executing "RAS-only" refresh, but with CAS held low.
RFSH has to be held at V 1H •
B) Hidden RFSH Refresh
Hidden R FSH Refresh is performed by
holding CAS at V 1L and taking RAS
high and after a specified precharge
period (tAFD). executing RFSH refresh,
but with CAS held low.
A specified precharge period (tePN) is
required before normal memory Read,
Write or Read-Modify-Write cycle after
performing either type of Hidden Refresh.
Refresh Counter Test Cycle:
A special timing sequence provides a
convenient method of verifying the
functionality of the RFSH activated
circuitry.
(A) RFSH Test ReadlWrite Cycle:
When R FSH is given a signal in timing as
shown in timing diagram of RFSH
counter Test Read/Write Cycle, Read/
Write Operation is enabled. A memory
cell address (consisting of a row address

1-210

(8 bits) and a column address (8 bits»
to be accessed can be defi ned as follows:
• A ROW ADD RESS - Bits Ao - A6
are defined when contents of the
internal address counter are latched.
(The other bit A7 is set low internally.)
• A COLUMN ADDRESS - All the bits
Ao - A7 are defined by latching
levels on Ao - A7 pins in a high-tolow transition of CAS.
By using a 15-bit address latched into
the on-chip address buffers by means of
the above operation, any of 32K (in the
fixed half cell array) memory cells can
be read/written into/from.
(B) RFSH Test Read Modify Wirte
Cycle:
Also, Read Modify Write Operation (not
only the above normal Read/Write
Operations) can be used in this RFSH
Counter Test Cycle.
(C) Example of Refresh Counter Test
Procedure:
(1) Initialize the internal refresh counter. For this operation, 8 RFSH
cycles are required.
(2) Write a test pattern of lows into
memory cells at a single column
address and 128 row addresses by
using 128 RFSH Test Write Cycle
or RFSH Test Read Modify Write
Cycle.
(3) Verify the data written into the
memory cells in the above step (2)
by using the column address used in
step (2) and sequence through 128
row address combinations (Ao A6 ) by means of normal Read
Cycle.
(4) Compliment the test pattern and
repeat the steps (2) and (3).

MB 8265A-l0
MB 8265A-12
MB 8265A-15

Fig.2 -

FUJITSU
1111111111111111111111111111111111111111111111111111

EXAMPLE OF RFSH REFRESH

MB 74LS161A
1 MHz CLOCK- CK

1111111111111111111111111111111111111111111111111111

R

MB 74LS74A
R.E.

DATA

r-A

Q

CK

RAS1'

REF

-

~C

Q

~D

-

~RAS2'*

~B

p'-)--RFSH
CLR

t

7!
To CPU
(BUSY)

I

AAsl-.

I

R.E.

I

I

I

I

I

I

I

I

BUSY

I

I

RAS2----'

I

I

RFSH

NORMAL CYCLE

RFSH REFRESH CYCLE

NORMAL CYCLE

"If RFSH refresh in not used, RASl is connected to RAS input.
"RAS2 should be connected RAS input.

Fig.3 - CURRENT WAVE FORM (Vce = 5.5V. TA = 25°C)

LONG RA I A

AAS/CAS CYCLE

E

0
0
0

PAGE MODE CYCLIi,

ONLY REFRESH CYCLE

RF H REFReSH CYCLE

~

160
0

CYCLE

I~

IV

"' ...... r\-

f
I

.... (J\ I,J

ft

I~

A

I~I

1\

I
lJ \.-U

I

IV

11
II II
..... LJ li- I\,. I-U

lOOnS/DIVISion

1·211

n

A

I~I

1

MB 8265A-1O
MB 8265A-12
MB 8265A-15

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

TYPICAL CHARACTERISTICS CURVES
Fig. 4 - NORMALIZED ACCESS TIME
vs SUPPLY VOLTAGE
w
::;;

i=

'"'"

1.2

Fig. 5 - NORMALIZED ACCESS TIME
vs AMBIENT TEMPERATURE

~5°C

w
::;;

TA =
t-- tRCO = 20ns

tJ
tJ

......

«
Cl

w

N

::::;

1.0

I'-....

«

----

«

«

O.B

::::;

a:
0

z

«

5

4.5

VC~ = 5.JV
tRAS = lOOns

/

30

Z

a

V

III
o

~OOns

Z

~

o

U

TA



i"'-..

u

:I:

'"a:

30

w

2

u..

w

20

a:

'"

d
.2

t RAS = lOOns

Z

>

~

20

'"a:w
u.

!:l

5
5.5
4.5
VCC. SUPPLY VOLTAGE (V)

40

zw

tCAS = 50ns

f--TA =25 C
tpc = 105ns

a:
a:

a

30

(!l

..:
Q.

10

o

...V

o::;
w

V

6
8
4
l/tpc CYCLE RATE (MHz)
2

-

o

./

20

30

w

V

0
0

.2

I,

~

E
I-

w

()

10

Fig. 15 - PAGE MODE CURRENT
vs SUPPLY VOLTAGE

40 I-TA = 25'C

z
w
a:
a:

..

tRC - 300ns

-20
0
20
40
60
80
100
TA. AMBIENT TEMPERATURE ('C)

6

VCC~ 5.5V

~

::;
w

20

M
10

Fig. 14 -PAGE MODE CURRENT
vs CYCLE RATE

u

=~50ns

w

4

:>

tRC

a:

a:

E

tRC 200ns
30

:I:

w

I-

VC~

u

u..

9

6

= 5.Jv
40 f--tRAS = lOOns

w

-

30

:I:

'"~

4
2
l/tRC. CYCLE RATE (MHz)

IZ

I-

~
:>
u

/

....

Fig. 13 - REFRESH CURRENT 1
vs AMBIENT TEMPERATURE

Fig. 12 - REFRESH CURRENT 1
vsSUPPLY VOLTAGE
~

V
/"

-:7

20

~
Q.

3

.2
10

10

4

4.5

5

5.5

VCC. SUPPLY VOLTAGE (V)

1-213

6

MB 8265A-10
MB 8265A-12
MB 8265A-15

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

Fig. 17 - REFRESH CURRENT 2
vs CYCLE RATE

Fig. 16 - PAGE MODE CURRENT
vs AMBIENT TEMPERATURE
-;{

E
f-

zw

J

1

~

5

VCC = 5.5V
40 r-

N

tCAS = 50ns

f-

;:)

w

30

0

20

«
0..

..
u

.!:.J

;:)

--

w

:;;:
w

40

a::
a::

0

<.:)

tFP = lOOns

Z

a::
a::

()

Vcc = 5.Jv
50 I--- T A = 25°C

()

tpc = 105ns

./

30

:t
(I)

w

a::

(PC = 150ns

u..

20

tpc = 200ns

a::
.;;

10

1

.!:.J

w

1

10

u

1

/'

o

-20
0
20
40
60
80
100
T A. AMBIENT TEMPERATURE (oC)

TA =

-;{

fZ

~

-

30

()

:t

(I)

w

e:w

20

6

vcb =

40 r-tFP = lOOns

fZ

w

a::
a::
;:)

tFC = 200ns
30

tFC = 250ns

()

:t
en
w

a::

u..
w

a::

tFC = 300ns
20

a::

III

§

U

.!:.J

4

5.5~

-;{

E
N

--

---

w

a::

2

Fig. 19 - REFRESH CURRENT 2
vs AMBIENT TEMPERATURE

2~oC

40 -tFC = 200ns

/'

l/tFC. CYCLE RATE (MHz)

Fig. 18 - REFRESH CURRENT 2
vs SUPPLY VOLTAGE

£

V

,/

10

10

Vcc. SUPPLY VOLTAGE (V)

-20
0
20
40
60
80
100
T A • AMBIENT TEMPERATURE (OC)

Fig. 20 - ADDRESS AND DATA INPUT VOLTAGE
vs SUPPLY VOLTAGE

Fig. 21 - ADDRESS AND DATA INPUT VOLTAGE
vs AMBIENT TEMPERATURE

4.5

4

4.0
TA

0_

z>
«W
(1)<.:)
w«
a::f(I)

=

5

5.5

6

«
f«
o

~5°C

0_

3.0

'f:::;:)

V1H(Min)_

2.0

>0..

O~

~ ~ 1.0

::

-:::: ~

-

~

z >

3.0

o c5
~>

2.0

«~~
w«
a::f-

O..J

00

«>

4.0

VC~ = 5.dv

V1H(Min)-

.f-

V1L(Max)

.J;:)

V 1L (Max)

>~10
.

0-

r«

z

::>0

«

o

4

r

4.5

5

5.5

::>

6

o

-20

0

20

40

60

80

100

T A • AMBIENT TEMPERATURE (oC)

Vcc. SUPPLY VOLTAGE (V)

1-214

Fig. 22 - RAS, CAS AND WE INPUT VOLTAGE
vs SUPPLY VOLT AGE
4.0

I~
n

4.0

I~
n

~> 3.0

~

<{c:J
I"';;;
u.;::

~;5
111:.>
:! ...

~~

<{

'111'1"111"'1"'1"'' "' ""111""""""'' "

I = 5.0~

Ve

> 3.0

I~ ;5
.>
:! ...

>:J

MB 8265A-15

'"<{c:J;;;
Iu.;::

V1H(Min)

-

2.0

"PUJITSU
" 'I I" " I I'I I"'I1 ~" " " "'"

Fig. 23 - RAS, CAS AND WE VOLTAGE
vs AMBIENT TEMPERATURE

=~5°C

TA

MB 8265A-1O
8265A-12

V1H(Min)_

2.0

~IL(M}x)

>:J

V1L(M.x)

~~

1.0

<{

:r:

1.0

:r:

->

->

o

4.5

4

5

5.5

o

6

-20

Vee. SUPPLY VOLTAGE (V)

0

20

40

60

80

Fig. 24 - CURRENT WAVE FORM DURING POWER UP
~>

~. ~
o~

»

...z

~>

~. ~ :[71

:[71

00

20

o~

t-Tj=25°~

00

»

...z

w

II:
II:

w
~

5

:J

u-

~~

"-":J

'"

5

L
I.

20 t -T j=25oJ

15

:J
u~
~ E 10

RAS = CAS = Vss
10

RAS = CAS = Vss

~-

_J_.I

(

"-

:J

'"U

RAS = CAS = Vee

.2

oIf'

5

RAJ=CAs1=vee

J

oV

1OilS/Division

~>
..1"-w
"-c:J

1OOIlS/Division

Fig. 25 - CURRENT WAVE FORM DURING POWER UP
(ON MEMORY BOARD)
~>

..1-

"-w
"-c:J
:J<{

"'0..1
....

~.;::

0..1
00

~A = 2~oC

»

...2

80

II:
II:

60

00

»

...

tRe = 270ns-

TAI=

25°d

tRC = 270ns

w

II:
II:

:J

60

:J

40

"-

:J

'"U
.2

80 -

2

w

~~
..I.s
"-

20

o

I'
\

100

TA AMBIENT TEMPERATURE (oC)

u~
~
E 40
..1_

MB 8265A + Decou,ling
~p,citor (O.?IlF)

":J

"-

'"

DecoJpling c~pacito;
(O.IIlF) only

U
.2

20llS/Division

20

MB'8265A + DeC~UPlIng
/ f'\. capacitor (O.IIlF)

~

o

c~pacito;

Decoulpling
(O.IIlF) only

100llS/Division

1-215

1111111111111111111111111111111111111111111111111

MB 8265A-l0

FUJITSU MB 8265A-12
1111111111111111111111111111111111111111111111111

MB 8265A-15

Fig. 26 - SUBSTRATE VOlTATE
vsSUPPlY VOLTAGE (DURING POWER UP)

~~

~ ~ 51:....... •
U),f-

0

0 ....

~~
w

~>

0
-1

,\

~~

-2

U) ....

.. 0

:J>

TA

\\

a:-

Iii ~

I

r

-3

~

-4

=1 25,C I
= CAS = Vee

RAS

"

~

o

--

5Ol's/Division

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Surfix : -Z)
16-lEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
(CASE No. : DIP·16C-C04)

I

R.025(0.64)

REF

.284(7.21)

rn

.313(7.95)

Jf
.300(7.62)TYP

-r-~ -=r. '''[u~:=-_-+-J
67

h:::r-1=,.......,.::::a--..:::=--a::::,.--lr'I;----,.....

)

~________~.7~54~(1~:=~.~~)_~
_____ ~ ~ I
.788(20.02)
----l

~~-----------------------~--~
.200(5.08)MAX

.120(3.05)
.150(3.81)
.090(2.29)
.110(2.79)

.020(0.51)
.050(1.27)
.013(0.33)
.023(0.58)

1·216

Dimensions in
inches (millimeters)

MB 8265A-10
MB 8265A-12 FUJITSU
MB 8265A-15 IIIIIIIIIIIIIIIIIIIII~IIIIIIIIIIIIIIIIIIIIIIIIIIIII

1111111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
Standard 16-pin Plastic DIP (Surfix : -PI
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M031

INDEX·1

.250t.35)
.27016.85)

!


(.)

<

VC~ = 5.~V

3

E.

Z

~
d
2

=5.~V

VCC
50 - TA = 2SoC

tRAS = lOOns

t-

Z

w

r--...... I-...

a::
a::

............

>

(.)

40

w

a::

20

LL

w

a::

..;
u

1

!:?

10

TA=2~OC

Z
w

a
~
w

a::
LL

30

<
E.

20

-.---

-

40

tZ
w

f-

~

a

./

2
4
l/tRC. CYCLE RATE (MHz)

6

tRC· !cono
tRC = 250no
tRC = 300no

en
~

VC~· 5.Jv
-tRAS· lOOns

30

:I:

20

LL

w

W

a::

E

/

V

Fig. 16 - REFRESH CURRENT 1
vs AMBIENT TEMPERATURE

40 r-tRC = 200ns

t-

'"

o

Fig. 15 - REFRESH CURRENT 1
VI SUPPLY VOLTAGE

a::
a::

V

en

2

020406080
T A. AMBIENT TEMPERATURE (OC)

E.

.;

30

:I:

<

6

Fig. 14 - REFRESH CURRENT 1
VI CYCLE RATE

4

j'.....

4.5
5
5.5
VCC. SUPPLY VOLTAGE (V)

a::

11

10

4

4.5

5

5.5

!:?

6

10
-20
0
20
40
60
80 100
TA. AMBIENT TEMPERATURE (OC)

VCC. SUPPLY VOLTAGE (V)

1-233

MB 8266A-1O
MB 8266A-12
MB 8266A-15

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

Fig. 15 - NIBBLE MODE CURRENT
vs CYCLE RATE



::>

o:;

tNC = 60ns

D::

D::

~

TA=2~oC

..5

10

Z

o
o

--

w

o

~

~

o
:;

I--

W
..J

::l

10

Z

~

u
15
10
l/tNC. CYCLE RATE (MHz)

5

0


tJ

20
II-

W
..J

::l

tNC

..
u

0

-20


w

5.5

Fig. 18 - REFRESH CURRENT 2
vs CYCLE RATE

= 25ns

tNCAS

5

VCC. SUPPLY VOLTAGE(V)

VC~ = 5.5l

...z

4.5

4

20

Fig. 17 - NIBBLE MODE CURRENT
vs AMBIENT TEMPERATURE

..5

-

20

"'u

2

10

4

4.5

5

5.5

10
-20

6

VCC. SUPPL Y VOLTAGE (V)

0

20

40

60

80

100

T A • AMBIENT TEMPERATURE (oC)

1·234

MB 8266A-l0
MB 8266A-12
MB 8266A-1S

4.0.----r----,---,---,
TA = 25°C

0_

Z>

 3.0

 2 . 0 f - - - - + - - + -

w0-

6I- 2.0

V1H(Min)-


.JI-

o~
~ ~ 1.0f-----+---+---+-----j

->~
o ~ 1.0

V1L(Max)

z

!~



I

->

o~-~~-~--.~-~
4
4.5
5
5.5
6

o

-20

Fig. 23 - RAS. CAS AND WE INPUT VOLTAGE
vs SUPPLY VOLTAGE
4.0

I?!

TA =

o

20

0

40

100

4.0

I?!
o
~

~> 3.0

veJ

=

5.0t

> 3.0

I'"

I~ 6 2.0

V1H(Minl_

.>
>::>

~IL(M~xl

::'1-

::'1-

>::>

V1L(Maxl

~~

1.0



Ve~ = 5.dv

o


4.5

5

5.5

1.0

o

-20

0

20

40

60

80

100

TA AMBIENT TEMPERATURE (oCI

Vee. SUPPLY VOLTAGE (VI

.,'

1·235

WlllllllWIWlllWillllllllllllllllW
FUJITSU
1111111111111111111111111111111111111111111111111

MB 8266A-1O
MB 8266A-12
MB 8266A-15

Fig. 27 - CURRENT WAVE FORM DURING POWER UP

~ ~ . . :::::;r:==+==+==+==!

~j
I-

zw

r-T~~2501

20

:[71

I I

»

I-

20 r -Tj=25oJ

Z

w

~
15
::>
0;(
> E 10

t-

iii
o
J;

(J.J
(JO

5

~
15
::>
0;(
> E 10

RAS = CAS = VSS

(

-J-,I

,

'"

o
J;

RAS = CAS = Vee

I

RAS - CAS = VSS

t::>

o

(
5

J-J

RAS = CAS = Vee

J

o/

10jAS/Division

100jAS/Division

Fig. 28 - CURRENT WAVE FORM DURING POWER UP
(ON MEMORY BOARD)

»

.J-

"-w
"-(!I

»
.J-

l71

"-w
"-(!I
::><

iii.~ o
u.J
1)0
»

t?1

~A=2h

"'.~ o
80
»

tRe = 270ns-

I-

T 1=25"d
80 I--A
tRe = 270ns

II:
II:

60

Z
w

i3-

\
o

><
.J S

MBS 66A + DecOUrng
"""capacitor (O,lIlF)

t::>

'"

DecoJpling c~pacito;
(O,lIlF) onlv

\

.B

40

20

/

1-.

o

Fig. 29 - SUBSTRATE VOLTATE
vsSUPPLY VOLTAGE (DURING POWER UP)

~~

"'.1(J.J
~~

m

r

0

0
1

\
\\

I
= CAS = Vee

TA =125oC
RAS

.......
.............

DecoJpling JpaCito~
(O,lIlF) onlv
100llS/Division

lOllS/Division

~ ~ 5t----

MBS266A + Dec~luPling
' - capacitor(O,lIlF)

I'--

o
SOilS/Division

1-236

MB 8266A-l0
MB 8266A-12
MB 8266A-15

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Surfix : -ZI
16-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
(CASE No_ : DIP-16C-C04)

rn
:~"lI. ~ ~ ~ ~ ~ ~ ]j~;:
.313(7.951

'325ru~:=-_-/-

--j

r·

~
.090(2.291
.110(2.791

v

'-' I
-----I

.754(19.151
.788(20.021

.....

050 (1.271MAX

IVI~VUl! ~~

J

v

~ '~::(:3::~AX

v

.032(0.811
TYP

.150(3.811
.020(0.511
.050(1.271
Dimensions in
inches (millimeters)

.013(0.331
.023(0.581

Standard 16-pin Plastic DIP (Surfix :

-PI
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No_: DIP-16P-M03)

::::::1:::
:: :H:
I.
.748(19.0)
.776(19.71

.290(7.371
.310(7.871

.1

Dimensions in
Inches (millimeters)

1-237

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIImllllllllllillml

FUJITSU
1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllili

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

MB 8266A-1O
MB 8266A-12
MB 8266A-15

PACKAGE DIMENSIONS
Standard 18·pad Caramic LCC (Surfix : -TV)

l8·PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC-18C-F02)
-PIN NO.1 INDEX

/

rl

.420(10.67)
.435(11.05)

.280(7.111
.295(7.49)

Dimensions in inche,f
(millimeters)

~Shape of Pin 1 index: Subject to change without notice

1·238

FUJITSU
•

MB85101A-10, MB85101A-12, MB85101A-15
MOS 65,536 x 4-Bit

Dynamic RAM Module

De.orlptlon
The Fujitsu MB85101A is a 64K x 4 dynamic RAM high density
memory module. It consists of four MB8264A DRAMs in 18-pad
lCC packages mounted on a 22·pin multilayer ceramic substrate.
The MB85101A is intended for use in memory applications In
which large amounts of memory are required in a compact space
or in which board space is limited. Significant size reduction can
be realized In applications such as mainframe memory, buffer
memory, desktop computers and peripheral storage.

•

rf-

P.........

• 85,538 x 4-blt DRAM modille
• R_ Access Time
100 ns max. (MB85101A·10)
120 lIS max. (MB85101A-12)
150 ns max. (MB85101A·15)
• Cycle Time
200 lIS min. (MB85101A-10)
230 lIS min. (MB85101A·12)
280 lIS min. (MB85101A·15)
• Single +5 V supply, :t10%

toIeranos

• l _ power (active)
1100 mW max. (MB85101A·10)
890 mW max. (MB85101A·12)
880 mW max. (MB85101A·15)
88 mW max. (standby)

• 2 msl128 cycle refresh
• RASonly and Hidden refresh
capability
• Read·ModHy·Wrlte and Page
Mode capability
• Common 110 capability using
Early Write operation
• Output unlatched at cycle end
allows extanded page boundary
and two dimentional chip
selects.
• On-chlp latches for Addresses
and Data·ln

1·239

lu..

_'A

MB88101A.10
MB88101A·12
MB81101A·11

MB81101 Block Diagram
and Pin Assignmant

ADDRESS

VSS
Vee

RlIS
I:li§

W

DINO

DIN2

DOUTo

DING

CAS
A7
A5

CHIPO
Doun

DOUTO

A.
DIN1

DINI
DOUTI

W

Do.".

DOUT1

At
A3
As

Block Diagram for
.aoh Chip
CLOCK GEN.
NO.1

RAi

Doun

W

DIN2

~

Ao

1
2
3

4
5
6
7
8
9

10
11
12
13
14
15
16
17
18

m

CA§

D IN3

...

D,.

Doun

A,

VSS

A.
A,

..
A,
A,
A,

DOUT
85,536·BIT
STORAGE CELL

......- Vee
-+-GND

Packag_ Dlm_nslons
Dimensions in Inches
(millimeters)

aa·Lead Slngl_
In.Lln_ Packag_

(Module MSP·22S·CC01)
2.175155.251
2.225156.521

I

1.19014.571
MAX

r--~~~F=~~~~~~~
.30017.62ITYP

~

.02010.51ITYfl.09012.291
.11012.79)

.D08(0.201
.012(0.30)

J~ ~ ~.."
.02310.581

.04411.121

2.100153.34ITYP

~o~":! 1,;1 :O!OO II :o~":! ?';I :o!n~

j=={=
.05011.271
.07011.781

FUJITSU

1·240

FUJITSU
•

MB85103A.12, MB85103A·15
MOS 65,536 x a-Bit

Dynamic RAM Module

Dworlptlon
The Fujitsu MB85103A is a 64K x 8 dynamic RAM high density
memory module. It consists of eight MB8264A DRAMs in 18·pad
LCC packages mounted on a 22·pln multilayer ceramic substrate.
The MB85103A Is Intended for use In memory applications In
which large amounts of memory are required in a compact space
or In which board space Is limited. Significant size reduction can
be realized in applications such as mainframe memory, buffer
memory, desktop computers and peripheral storage.

I I I
I I I

iii
'-I

...........

IU'

• 86,538 x 8-bIt DRAM module
• R_ Acceas Time
120 na max. (MB86103A·12)
150 ns max. (MB851Q3A.15)

• 2 msI128 cycle refresh
• JiAS.onIy and Hidden refresh
capability
• Page Mode capability

• Cycle TIme
230 na min. (MB86103A-12)
280 ns min. (M!I851Q3A.15)
• Single +5 V IUpply, :10%

• Output unlatched at cycle end
allows extended paga boundary
and two dimentional chip

tel_nee

• Common 110

181ectB.

• ~ fIOWII" (actlvl)

• On-chlp latcllae for AdcIreBsaa
and Data·ln
1980 mW max. (MB86103A-12)
1780 mW max. (MB86103A·15)
178 mW mix. (standby)

1·241

r11

H1f

MB85103A.12
MB85103A-111 '

MB85103 BI
and Pin A. lOCk Diagram
• gnment

DC,
DC,

Block Dla ram
Each Chl:
for

Package DI

Dimensi

menslons

(millimet~~:) in

inches

22-Laad 81
In.LI
ngle
ne Packa
(Module
I
.CC02)

MSP-2~S·

~i1. . . . . . 1r:. . ~~~:::=1 1 1·,3~~:2)

3 0 0 { E [............

LI)MAXn

I
----r~
,012{O,30)

,120{3,05)
,150{3,81)
2,100{53,34)TVP

FUJITSU

1-242

FUJITSU
• MB85108A.12, MB85108A·15
MOS 262,144 x 1-Bit
Dynamic RAM Module

De.crlptlon
The Fujitsu MB85l08A is a 256K x 1 dynamic RAM high density
memory module. It consists of four MB8266A DRAMs in l8·pad
LCC packages mounted on a 22'pin multilayer ceramic substrate .
The MB85l08A is intended for use in memory applications in
which large amounts of memory are required in a compact space
or in which board space is limited. Significant size reduction can
be realized in applications such as mainframe memory, buffer
memory, desktop computers, and peripheral storage.
The MB85l08A features two new functional enhancements that
make it more versatile than previous dynamic RAM's. The CAS·
before-RAS refresh mode provides an on·chip refresh capability.
The nibble mode function allows high speed serial access to up
to 4 bits of data.

Feature.
.262,144 x l·blt DRAM module
• Row Access Time
120 ns max. (MB85108A·12)
150 ns max. (MB85108A·15)
• Cycle Time
230 ns min. (MB85108A·12)
260 ns min. (MB85108A·15)
• Nibble Cycle Time
70 ns min. (MB85108A·12)
90 ns min. (MB85108A·15)
• Single +5 V supply, :!:10%
tolerance
• Low power (active)
341 mW max. (MB85108A·12)
303 mW max. (MB85108A·15)
99 mW max. (standby)

• 2 msH28 cycle refresh
• RAS·on~ldden and CAS.
before-RAS" refresh capability
• Read·Modlfy·Wrlte capability
• Nibble Mode capability
• Common 110 capability using
Early Write
• On·chlp Address and Data·ln
latches
• Output unlatched at cycle end
allows extended page boundary
and two dimentional chip
selects.

1-243

lt-

•
f11

t

f-

MB85108A·12
MB85108A·15

MB85108 Block Diagram
and Pin Assignment

ADDRESS:===;+========:::;l
0,"
eAS:=:;~+======::;l
Vi

Vss

1

Vee

2

mo

4

RAS 0-++H--I

5
6

CHIP 0

RAS 1-+++-If-.....

D'N

7

W

8

RAS 1
CHIP 1

CHIP 3

A7
N.C.

9

10
11
12
13

'---------LDOUT

RAS 2 14

Block Diagram lor
Each Chip

RAS----_I

A2

15

Al
N.C.

16
17

A4
RAS 3

18
19

As

20

Vee

21

22

0,"

Dour

Package Dimensions
Dimensions in inches
(millimeters)

22·Lead Single
In·Llne Package
(Module MSP·22S-CC01)
2.175 (55.25)

!' .090
(2.29)
.110 (2.79)

-

II

015 (0 38)
':023 (0:58)

,.180 (4.57)
MAX

I

.036 (0.091)
.044 (1.12)

2.100 (53.34) TYP

t

.050 (1.27)
.070 (1.78)

FUJITSU

1-244

FUJITSU

MOS Memories
•

MB85201.12, MB85201·15
1,048,576 x 1-Bit Dynamic
Random Access Memory
SIP Module

De.crlptlon
The Fujitsu MB85201 is a fully decoded, 1,048,576 word x I-bit
NMOS dynamic random access memory module consisting of four
MB81256 DRAMs in IS-pad LCC packages mounted on a 22-pln
multilayer ceramic substrate.
The MB85201 is intended for use In memory applications where
large memory capacity is required wHhin limited physical volume.
Significant size reduction can be realized in applications such as
mainframe memory, buffer memory, desk top computers and
peripheral storage.

.--d~ -

-

Featu....

~
~

•

•
•

•
•

1,048,578 x I-BIt DRAM
2:z..pln SIP (MB81258x4)
Row._tlme
120
liliiii. (MB85201-12)
liliiii. (MB85201-1S)
150
CycIetime
230 .... min. (MB85201-12)
260 n. min. (MBa5201-1S)
Pege eycl. time
120 n. min. (MB85201-12)
150 ne min. (MBa5201-1S)
Single + 5V supply,

n.

n.

±10% tolerence

• 4 m./258 refreIIh eye...
~bllity

• JiWI-only,CA§..berore.:RAS
.nd Hidden refreIIh

cepebility
• Reed-Modify-WrIte and Page

Mode capability
• Common I/O cepebility usIng Early WrIte operation
• On-chlp latch.. for
Addreaaea and Data-fn
• Allinpute and OUIpute ere
TTL compatible

• Low power (.ctlve)
435 mW mo. (MB85201-12)
390 mW liliiii. (MB85201-1S)
100 mW mo. (etendby)

This device contains cirwitry to
protect tho inputs against damage
duo to high static voItagoo or __
trio ftoldo. HoweYOI". h Is advIoed
that normal precautions be taken to
avoid appIcalion of any voItago
higher than maximum rated YOIt~
ages to this high Impedance circuit.

1-245

i

I

rf -

111885101.11
111885101.15

111885101 810ck Diagrams
and Pin Assignment

810ck Diagram For Each Chip

v..

w
CAS -~'-------+or-,",

Vee

lIno
OUT
A3

Ao

6

IN

7

W

o

Q

262,144-BIT
STORAGE CELL

",-Vee

.....--Vss

RAIl

A.,

10

A7

11

A,

12

CAS

13

RAS2

14

A,

15

A,

16

NC

17

A.

18

RAS3

19

As

20

Vee

21

Vss

22

CJ

FUNCTIONAL TRUTH TABLE FOR EACH CHIP
Read

W~1e

Refre.h

No

No

No

Standby

Vaa

No

Ve.

Read

No

Vos

Yea

twcs .. lWCS (min)

V..

Yes

Y..

Delayed WrIte or And-wrtte
ICWD" ICWD (min)

Hlgh·Z

No

No

Yea

RA&-onIyR_h

Don't Care

Valid Data

No

No

Yea

data selected at previous Read

Don't Cere

Hlgl>-Z

No

No

No

CASdlaturb

RAS

CAS

W

IN

OUT

H

H

Don't Care

Don't care

Hlgh·Z

L

L

H

Don't care

Valid Data

L

L

L

Valid Data

Hlgh·Z

L

L

L

V.lld Data

Valid Data

L

H

Don't Care

Don't care

L

L

Don't Care

H

L

Don't Care

Note

Early Write

CA&-balore-RAS Rolreah Valid

or ReadooWrlte cycle I. held

Functional 810ck Diagram

RASO-+-t+t--I

RASI

CHIP 0

CHIP 2

CHIP 1

CHIP 3

-+lH-+--l

L--------~--OUT

f'UJITSU
1·246

MB85201·12
MB85201·15

FUNC110NAL TRUTH TABLE FOR MODULE
!IAlIo to

Valid Data

Read cycle

L-j

L

L

Valid Data

Hlgl\-Z

Wrhacycle

L-j

L

H_L"2

Valid Data

Valid Dahl

H_L"3

H ..... L·3

Don't Car.

Don't Care

Hlgh-Z

CA8-belore-!IAlI R","",h cycle

L

H

Don't Care

Don't Care

Hlgh-Z

RAS-only R","",h cycle

g

~

n

_

l

t

_

a

_

R

_

~

m

N

e

e

S

(

Absolute Maximum Ratings

____________________________

I

Don't Care

_

H

o

L

_

L-j

b

Hlgh-Z

_

OUT

Don'l Care

m

IN

Don't Care

_

W

H

y

CAS

H

~

iin3

S

MB85201 Block Diagrams
and Pin Assignments
(Continued)

Function
Standby

Read-write cycle

_____________________________
Value
Unit

Voltage on any pin relative toVss

VIN ' VOUT

-1 to +7

V

Voltage on Vcc supply relative to Vss

Vcc

-1 to +7

V

Storage temperature

Tstg

-55 to +150

·C

Power dissipation

Po

2.4

W

50

mA

Short circuit output current

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed In the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Description
Simple Timing Requirement

Address Inputs

RASOIO RAS3

The MB85201 has improved
cirCUitry that eases timing
requirements for high speed
access operations. The MB85201
can operate under the condition
of tRCO (max) = ~c thus providing optimal timing for address
multiplexing. In addition, the
MB85201 has the minimal hold
times of address (tCAH ), Vii (tWCH )
and IN (tOH )' Fujitsu has made
timing requirements that are referenced to RAS non-restrictive
and deleted them from the data
sheet. These include tAR' tWCR '
tOHR and t RWD ' As a result, the
hold times of the column address, IN.J!nd W as well as tCWD
(CAS to W Delay) are nm restricted by tRCD'

A total of eighteen binary input
address bits are required to decode anyone of 1,048,576 locations within the MB85201. Nine
row address bits are established
on the input pins (AD through As)
and latched with the RAS (one of
RASO to RAS3) of the selected
chip. Nine column address bits
are established on the input pins
and latched with CAS. All input
addresses must be stable on or
before the falling edge of RAS.
CAS is internally inhibited bLRAS to permit triggering of CAS
as soon as the Row Address
Hold Time (tRAH ) specification
has been satisfied and the address inputs have been changed
from row addresses to column
addresses.

The MB85201 has four RAS inputs in order to select a chi~
within the MB85201. Other RASs
except for one RAS to be selected must be high in order to
avoid data conflict during read,
delayed write or read-write
cycles.

1-247

Write Enable
The read mode or write mode is
selected with the W input. A high
on the Vii selects read mode, a
low selects write mode. Data input is disabled when read mode
is selected.

M88S201·12
M88S201·1S

Deacrlptlon
(Continued)

Data Input
Data Is written into the £!!ie selected by ~ (one of RA:lo to
RAS3) of MB85201 during a write
or read-write gycle. The later failing edge of VI or alrn is a strobe
for the IN register. In a wrHe
cycle, if VI Is brought low before
the setthe falling edge of
up and hold times are referenced
to alrn. In a delaLed write or
read-write cycle, W can be low
after alrn has already been low
and eAS to W Delay time (tcwo )
has been satisfied (read-write
cycle). Thus IN is strobed by
and set-up and hold times are
referenced to W.

m,

W.

Data Output
The output buffer of each chip Is
three-state TTL compatible with a
fan-out of two standard TTL
loads. OUT is the same polarity
as IN. The output is inJ!!g!l
impedance state until CAS is
brought low. In a read or readwrite cycle, the output Is valid
after tfl6C.!.rom negative transition
of the RAS when t RCO (max) is
satisfied, or after~ from negative transHlon of CAS when the
transition occurs after tRCD (max).
Data remains valid until ~ is
returned to a high level. In a wrHe
cycle, the identical sequence 00curs but data Is not valid.

Faat Read-While-Write Cycle
The MB85201 has a fast readwhile-write cycle which is
achieved by precise control of
the three-state output buffer as
well as by the simplified timings
described In the previous section.
The output buffer is controlled by
the state of VI when ~ goes
low. When Vii Is low during CAS
transition to low, the MB85201
goes into the early write mode in
which the output floats and the
common I/O bus can be used on
the system level. Whereas, when
~es low after tcwo following
CAS transition to low, the

MB85201 goes into the delayed
wrHe mode. The output then contains the data from the cell selected and the data from IN are
written into the cell selected.
Therefore, a very fast read write
cycle (tRC = tRwclls possible
with the MB85201.

Page-Mode
Page-mode operation permits
strobing the row-address Into the
MB85201 while maintaining RAS
(one of RASO·to ~) at a logic
low throughout all successive
memory operations in which the
row-address doesn't change.
Thus the power dissipat~~ the
negative going edge of RAS IS
saved. Access and cycle times
are decreased because the time
normally required to strobe a new
row address is eliminated.

Refresh
Refresh of the dynamic memory
cells is accomplished by performIng a memory cycle at each of
the 256 row address (Ao through
A7) for each chip at least every 4
ms. During refresh, either VIL or
VIH is permitted for & anc!!!!Y
combinations of RASO to RAS3
are allowed. When all chips are
refreshed simultaneously, the average power dissipation of the
module must be less than 640
mW at any 100 ms interval.
The MB85201 offers the following
three types of refresh.
1) RAS-Only Refresh;
RAS Only refresh avoids any
output during refresh because
the output buffer is in hl~
impedance state unless CAS
is brought low. Slr()bing each
of 256 row addresses with
RAS will cause all bits in each
row to be refreshed.

2) CAS-before-RAS Refresh;
CA8-before-RAS refresh
available on the MB85201 offers an alternate refresh
method. If CAS Is held low for
the specified period, eAS Set
Up Time Referenced to RAS
(tFcs)has been satisfied before the falling edge of RAS,
on chip refresh control clock
generators and the refresh
address counter for each chip
are enabled, and an Internal
refresh oparation takes place.
After the refresh operation
has been executed the refresh address counter is automatic!!!y.lncremented for the
next CAS-before-RAS refresh
operation.
3) Hidden Refresh;
Hidden refresh may take
place while maintaining latest
valid data at the output by extending CAS active time. In
the MB85201, hidden refresh
means CAS-before-RAS refresh and the intemal refresh
address is used, that is, no
external refresh address Is
needed.

CA§.before-iiA§ Refresh
Counter Test Cycle
~ecial tim.!DlLsequence using
CAS-before-RAS counter test
cycle provides a convenient
method of verifying the functionalify of eAS-before-RAS refresh
activated cirCUitry. After the CASbefore-RAS refresh operation,lf
~ goes into h!ll!!..!nd gqes Into
low again while RAS Is held low,
the read and write operation are
enabled. This Is shown in the
CA8-before-RAS counter test
cycle timing diagram. A memory
cell address (consisting of a row
address (9-blts) and a column
address (9-blts» to be accessed,
can be defined as follows:

1) A ROW ADDRESS-Bits Ao
through A7 are defined by the
refresh counter. The other bit
As is set high injemally.
2) A COLUMN ADDRESS-All
the bits Ao through As are defined by latching levels on Ao
through As at the second failing edge of CAS.

FUJITSU
1-248

MB85201·12
MB85201·15

Description
(Continued)

Suggested CASobefore-RAS
Counter Test Procedure

The timing, as shown in CAS-before-RAS Counter Test Cycle, is
used for all operations described
as follows:
1) Initialize the internal refresh
address counter. For this operation, the 8 CAS-beforeRAS refresh cycles are
required.

Decoupllng and Nolaa Reduction Recommendations for
MB85201

4) In order to avoid noise induction on the IN line at the failing edge of W when the
delayed write or read-modifywrite cycle is used, the falling
edge of Wsignal should not
coincide with the transition
point of address and OUT signals. Since decoupling capacitors on the module board
can't smooth the output current at the OUT pin, noise is
introduced on the power supply buss (Vee or Vss ) and
also on the IN line at t RAe or
tCAC in the read cycle.

To minimize noise induction between signal lines as well as between signal and power supply
lines, good board design practice
requires consideration of the
following.
1) Provide a capacitor of approx.
a few p.F for each module,
even though the MBB5201
has two decoupling capacitors
of 0.15p.F on each module.

2) Write a test pattern of lows
into memory cells at a single
column address and 256 row
addresses.
3) By using read-modify-write
cycle, read the lows written at
the last step and write a new
high in the same cycle. This
cycle is repeated 256 times,
and highs are written into the
256 memory cells.
4) Read the high written at the
last step.
5) Compliment the test pattern
and repeat the steps 2, 3 and
4.

2) Remove noise, ringing, overshoot and undershoot from
the address, control and datainput lines, so that the
MB85201 won't latch spurious
signals due to the noise induction between signal lines,
and between Signal and
power supply lines.

5) Provide appropriate damping
if necessary, to avoid excessive overshoot or undershoot
on the TTL input waveform.

3) Maintain sufficient timing margins and remove critical timing
in the board design to avoid
the problem mentioned in
lIem2.

6) Repeat the steps 2 through 5
for another 3 chips.

Recommended Operating
Conditions
(Referenced to Vss)

Capacitance
(TA = 25°C)

Parameter

Symbol

Min

Typ

Max

Unit

Supply vollage

4.5
0

5.0
0

5.5
0

V
V

Input high voltage

Vec
Vss
VIH

2.4

6.5

V

Input low voltage

VIL

-1.0

0.8

V

Parameter

Symbol

Ao through As,

Max

Unit
pF

CIN2

15

pF

CIN3

65

pF

COUT

55

pF

CIN1

Input capacitance ~O through RAS3
Input capacitance CAS
Output capacitance OUT

1·249

Typ

O°Cto +70°C

50

IN, W

Input capcitance

Operating
Temperature

MB8520t·t2
MB85201.15

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

MB85201·15
Min
Max

Unit

Symbol

Operating currenf'
Average power supply current
(one RAS'2, CAS cycling; t RC = min.)

Icc,

79

71

rnA

Standby current
Standby ~er supply current
(RAS = CAS = VIH )

Icc2

18

18

rnA

ICC3

220

200

rnA

Page mode currenf'
supply current
(one RAS'3 = Vll, CAS cycling;
tpc = min)

Icc4

44

39

rnA

Refresh current 2'4
power s~ current
(all RAS cycling, CAS-before-RAS)

Iccs

240

220

rnA

Input leakage current
Any input (0 E; VIN E; 5.5V,
Vcc = 5.5V, Vss = OV,
all other pins not under test

II(l)

-40

40

-40

40

fJ-A

IO(l)

-40

40

-40

40

fJ-A

Refresh current 1".4
Average power supply current
(CAS = VIH , all RAS cycling; t RC

= min)

Aver~ower

Ave~

= OV)

Output leakage current
(Data out is disabled,
OV E; VOUT E; 5.5V)
Output levels
Output high voltage (loH = -5 rnA)
Output low voltage (lOl = 4.2 rnA)
Notes: '1
*2
*3
*4

AC Characteristics ".2.3
(Recommended operating
conditions unless otherwise
noted.)

MB85201·12
Min
Max

Parameter

2.4

VOH
Val

0.4

V

ICC is dependent on output loading an~cle rates. Specified values are obtained with the output open.
The selected RAS is cycling and other RASs are in VIHThe selected RAS is in VIL and other RA8s are in VIH"
When all chips are refreshed simultaneously, the average power dissipation of the module must be less than 640 mW at any
100 ms interval.

Parameter

Symbol

MB85201·12
Min
Max

MB85201·15
Min
Max

4

Time between refresh

tREF

Random read/write
cycle time

tRC

230
230

4
260

Unit
ns
ns
ns

Read-write-cycle time

t RWC

Access time from RAS'4.s

t RAC

120

150

ns

Access time from CAS's.s

tCAC

60

75

ns

260

Output buffer turn off delay

tOFF

0

25

0

30

ns

Transition time

tT

3

50

3

50

ns

Notes:

*1 An initial pause of 200}.ts is required after power*up. And then several cycles of all RAS's (to which any 8 cycles to perform
refresh are adequate) are required before proper device operation is achieved.
If internal refresh counter is to be effective, a minimum of 8 CAS-before-RAS refresh cycles are required.
*2 AC characteristics assume IT = 5 ns.
*3 VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between
VIH (min) and VIL (max).
*4 Assumes that tRCD "" tRCD (max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will
increase by the amount that tRCD exceeds the value shown.
*5 Assumes that tRCD ;a. IReD (max).
·6 Measured with a load equivalent to 2 TTL loads and 100 pF.

FUJITSU
1-250

M885Z01·1Z
M885Z01·15

AC Characteristics '1,2,3
(Continued)
(Recommended operating
conditions unless otherwise
noted,)

Parameter

Symbol

M885Z01·1Z
Min
Max

M885Z01·15
Min
Max

100

RAS precharge time
RAS pulse width

tAP

100

tAAS

120

Unit
ns

10000

150
75

10000

75

10000

ns

RAS hold time

t ASH

60

CAS pulse width
CAS hold time
RAS to CAS delay time'7,S

tCAS

10000

tCSH

60
120

tACO

22

60

CAS to RAS set up time

tCAS

20

20

ns

Row address set up time

tASA

0

Row address hold time

tAAH

12

0
15

ns

Column address sel
up lime

IASC

0

0

ns

ns

150
25

ns
ns

75

ns
ns

Column address hold lime

ICAH

20

25

ns

Read command sel up lime

tACS

0

0

ns

Read command hold lime
referenced 10 CAS'10

tACH

0

0

ns

Read command hold lime
referenced 10 RAS'10

tAAH

20

20

ns

Wrile command sel
up lime

twcs

0

0

ns

Wrile command hold lime

IWCH

20

25

ns

Wrile command pulse width

twp

20

25

ns

Wrile command 10 RAS
lead lime

I AWL

50

60

ns

Wrile command to CAS
lead lime

ICWL

50

60

ns

Dala in sel up lime

tos

0

0

ns

Dala in hold time

lOH

20

25

ns

CAS 10 W delal 9

t cwo

20

25

ns

referenced to RAS (CAS·
before-RAS)

t FCS

25

30

ns

CAS hold lime referenced
RAS (CAS-before-RAS)

I FCH

25

30

ns

RAS precha~o CAS
active lime (CAS-beforeRAS)

tAPC

20

20

ns

CAS sel up lime

10

Not..: *1 An initial pause of 200 P.s is required after power~up. And then several cycles of all RAS's (to which any 8 cycles to perform
refresh are adequate) are required before proper device operation Is achieved.
If internal refresh counter is to be effective, a minimum of 8 eA§..before-'RAS refresh cyCles are required.
*2 AC characteristics assume IT = 5 ns.
*3 VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between

VIH

(min) and

VIL (max).

*7 Operation within the tRCD (max) tlmlt insures that tAAC (max) can be met. tRCD (max) is specified as a reference point only; If
tACO Is greater than the specified tRCD (max) limit, then access time Is controlled exclusively by tCAe-

's IACO (min)

-

lAAH (min) + 2tr (It - 5 ns) + IASC (min).

*9 twes and tewD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If
twcs ;O!O twes (min), the cyde Is an early write cycle and the data out pin will remain open circuit (high Impedance) throughout

~~~:~~~I~helfa~:~ :e~c:~o~~~~!~sC:tie~~ ~:~~~~:oc:~et~~dd~~tao~~s~~:~:~:~ read from the selected cell. If
*10 Either tRRH or tRCH must be satlsfied for a read cycle.

1-251

AC Charac.erlstlcs'I,2,3
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Symbol

MB8S201.12
Min
Max

MB85201.15
Min
Max

Unl'

CAS precha~me

tCPR

25

30

ns

Page mode read/write
cycle time

I,>c

120

150

ns

Page mode read-write
cycle time

ipRWc

120

150

ns

Page mode CAS precharge
time

tcp

50

65

ns

Refresh counter test cycle
time'll

t ATC

375

430

ns

Refresh counter test RAS
pulse width'll

tTRAs

265

tCPT

60

70

ns

tRAP

0

0

ns

Parame'.
(eAS-before-

cycle)

Refresh counter test
precharge time'll

eAS

fUI:S to FiAS precharge
time
_:

_-up.

1000

320

m'S

1000

ns

'I An initial pause of 200 "s is required after
And then s " - cYcles of all
(to which any 8 cycles to perform
refresh are adequate) are required before proper device operation is achieved.
If Internal refresh counter is to be effective, a minimum of 8 ~·m refresh cycles are required.
*2 AC characteristics assume tT = 5 ns.
*3 VIH (min) and Vil (max) are reference levels for measuring timing of Input signals. Also, transition Urnes are measured between
VIH (min) and VIL (max).
'II Refresh oounter test cycle only.

FUJITSU
1-252

MBa5201·12
MBa5201·15

Timing Diagrams
Readel/cle

1QlI"

~~~--------------------t"C-------~--------~
j.,.--------t"AS--------~
1QlI"

ADDRESS

VIH

V,L

'Ii

V,.
V,L

'"""'"t..I..I........'"'t"~

V,.
OUT

V,L - - - - - - - - - - -

NOTES: '1 IT IS FOR UNSELECTED 1IlIlI.
'2 IT IS FOR THE SELECTED 1IlIlI.

1·253

VAUD
DATA

rzz.J DON'T CARE

MB85201·12
MB85201·15

Timing Diagrams
(Continued)

Write Cycle (Early Write)

RAll-'
'RC
tRAS

RAll-2

V,H
VIL
tCSH
tRSH

teAs

CAS

ADDRESS

W

V,H
VIL

V,H
V,L

V,H
VIL

IN

VOH

---------------HIGH-Z---------------

OUT

VOL

NOTES: *1 IT IS f:OR UNSELECTED RAS.
-2 IT IS FOR THE SELECTED liAS.

FUJITSU
1-254

rz2l DON'T CARE

M885201·12
M885201·15

Timing Diagrams
(Continued)
Read·Write/Read·Modify·Write eVel.

fiAg"l

....

t~c----------------------------~------------~.~I

ftAS"2

ADDRESS

Vi

OUT

IN

V'H

v'L"!L(iLLiL:LL(iLLiL:LL{f.LLiLtLL{f.LLiL(LLLiL:LL{f.LLiL:LL{f.LLiLtLLt.l/l_"::':':':~.Jr"'.LLtLi.'.LL..CLLLL,,'.LLLL.I.'.LL.LL.I.'.L.I.
~DON'TCAAE

NOTES: *1 rT IS FOR UNSELECTED RAS.
*2 IT IS FOR THE SELECTED RD.

1·255

MB85201.12
MB85201.15

Timing Diagrams
(Continued)
Page Mode Read Cycle

W"

W"

V'H
VIL

~

V'H
VIL

ADDRESS

V'H
V'L

OUT

VOH
VOL

Vi

fZZl DON'T CARE

NOTES: *1 IT IS FOR UNSELECTED RAS.
*2 IT IS FOR THE SELECTED RiS.

I8XJ VAUD DATA

FUJITSU
1·256

MB85201·12
MB85201·15

Timing Diagrams
(Continued)

Page Mode Write Cycle

RD"

RD"

~4
V'L

tRRP

V'H
V'L

CAS

ADDRESS

V'H
V'L

V'H
V'L

Vi

V'H
V'L

IN

V'H
V'L

OUT

~~:--------------------------HIGH-Z---------------------

t7Zl DON'T CARE

NOTES: '1 IT IS FOR UNSELECTED RAS.
'2 IT IS FOR THE SELECTED RD.

1-257

."'201.12
. . .5201.15

Timing I)lagrama
(Continued)

Pag. Mod. R.....Wrlte erel.

RlIlI'1

....

..

~----------------------- u------------------------~

CAS

V..
V,L

ADDRESS

VIH
V,L

VI

OUT

V,.
V,L

VOlt
VOL

VIH
IN

VOL

NOTES, '1 IT IS FOR UNSELECTED lID.

fZlI DON'T CARE

*2 IT IS FOR THE SELECTED FlU.

FUJITSU
1-258

MB85201·12
MB85201·15

Timing Diagrams
(Conlinued)

CAS.belor•• RAS R.fr.sh Cycl.
Nole: Address,

W. IN =

Don'I care

An"

V,H
V,L

~_'OFF
~~~---{--------------HIGH-Z----------------

OUT

NOTE: "

ANY COMBINATIONS OF Ana TO An3 ARE ALLOWED AND An's

FZ21 DON'T CARE

TO BE NOT REFRESHED ARE IN VIH_

iiii.~~ly R.fr.sh Cycl.
Nole: WE, D'N = Don'I Care, As = V,H or V,L
~---------IAC------------IO-I

k----tRAs---_o-l
An"

ADDRESS
(Aato A7)

----------HIGH,Z-----------

VOH
VOL

OUT

NOTE: "

ANY COMBINATIONS OF RASa TO RAS3 ARE ALLOWED AND RAS'S

TO BE NOT REFRESHED ARE IN VIH.

1·259

E22I DON'T CARE

M88S20t·t2
M88S20t·tS

Timing Dlag,ama
(Continued)

Hidden Refresh Cycle

I----'OAO----o-t
lfBo,

lfBo,

ADDRESS

W(READ)

DUT

W(READ-

WRITE)

NDTES: "I IT IS FDR UNSELECTED lfBo
"2 IT IS FDR THE SELECTED lfBo

","ITaU
1-260

rlZl DON°T CARE

M885201.12
M885201·15

Timing Diagrams
(Continued)

CAS-bet_RAS Refr.... Counter T••t Crel.

I~----------------------------I~C--------------~------~·~I

lIlIlIo,

----~I
V,H
V,L

~--------------------~.s------------------~

Ir-----~I

I-----IO S H - - - - - + I
V,H
V,L

ADDRESS

V,H
V,L

W(READ)

V,H
V,L

OUT

W(WRITE)

~~----------------I

V,H
V,L

IN

rzzI

1·261

DON°T CARE

MB85201·12
MB85201·15

Package Dimensions
Dimensions in inches
(millimeters)

22·Lead Single In.Llne Package Module
(Module No.: MSP-228-CC04)

I_ .220(6.59}
MAX .

•008(O.20}
.012(O.30}

.090(U9}

.01S(O.38}

.110(2.79}

.023(O.56}

.036(O.91}
.044(1.12}

2.100(53.34}TYPp

I~ ~'!"" :'~~ ~'!'~? ~ ~,:'::?:

C:':': 1=t
.050(1.27}
.070(1.76}

1·262

FUJITSU

MOS Memories
•

MB85203-10,MB85203-12,MB85203-15
MOS 262,144 x 4-Bit
Dynamic RAM Module

Description
The Fujitsu MBB5203 is a fully decoded, 262,144'words x 4-bit
NMOS dynamic random access memory module conSisting of four
MBB1257 DRAMs in lB-pad LCC packages mounted on a 24-pin
multilayer ceramic substrate.
The MB85203 is intended for use in memory applications where
large memory capacity is required wilhin limited physical volume.
Significant size reduction can be realized in applications such as
mainframe memory, buffer memory, desk top computer and peripheral storage.

.262,144 x 4 DRAM 24-pln SIP
(MB81257 x 4)
• Row acces8 time
100 ns max. (MB85203-10)
120 ns max. (MB85203-12)
150 n8 max. (MB85203-15)
• Cycle time
210 ns min. (MB85203-10)
230 ns min. (MB85203-12)
260 ns min. (MB85203-15)
• Nibble cycle mode
50 n8 min. (MB85203-10)
65 ns min. (MB85203-12)
80 n8 min. (MB85203-15)
• Single +5V supply, ±10"
tolerance
• Low power (active)
1540 mW max. (MB85203-10)
1430 mW max. (MB85203-12)
1254 mW max. (MB85203-15)
100 mW max. (Standby)

• 4 ms/258 refresh eyelae
capability
• RAS-only, CAS-bet_JIll
and Hidden refresh capability
• Read-Modify-Wrlta and Nibble
mode capability
• Common I/O capability ualng
Early Write operation
• On-chlp latchae for Addraean
and DatlHn
• Allinputa and outputa are nL
compatible

This device contains circuitry to
protecl1l1e il"jlUlS against damage
due to high static voltages or oleotrie fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voIt~
ages to 1I1is high impedance cirouit.

1-263

~~

~;[L

~ :l

-

P'fI'l

~ ~"

~i"...r1I fJ'I

fI1

-

MB85203·10
MB85203·12
MB85203.15

MB85203 Block Diagrams
and Pin Assignment

Block Diagram for Each Chip
NC

Aa

w

Vee
INO

CAS----~----------~~

OUTO

CAS

6

A7
As

"-

IN

IN1

10

OUT111

OUT

W

12

A,

13

A,

14

A,

15

OUT216
262.144·BIT
STORAGE CELL
4--

Vcc

......--VSS

IN2

17

A,

18

Ao

19

RAIl

20

IN3

21

OUT3 22

Functional Block Diagram

Voo 23
NC

1",-++++--1
CHIP 2

OUT.

IN,-+H+---l
CHIP 3

CHIP 1

OUT~,,-____..,

FUJITSU

1·264

OUT.

24

MB85203·10
MB85203·12
MB85203·15

Absolute Maximum Ratings
(SeeNot~

!R~a~t~lng~

______________~__________~~S~Y:mb~O:I__________Value
~~~__________~___
Unit

Voltage on any pin relative to Vss

VIN , Vour

1 to +7

V

Voltage on VCC supply relative to Vss

VCC

1 to +7

V

Storage temperature

T sm

55 to +150

'C

Power dissipation

Po

Short circuit output current

2.4

W

50

mA

Not.· Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
• the conditions as detailed In the operational sections of this data sheet. Exposure to absolute maximum rating condltlons for extended
periods may affect device reliability.

Description
Simple TIming Requirement

Write Enable

The MB85203 has improved circuitry that eases timing requirements for high speed access
operations. The MB85203 can
operate under the ODndition of
tRCO (max) = tCAC thus providi~g
optimal timing for address multiplexing. In addition; the MB85203
has the minimal hold times of address (tCAH )' W (tWCH ) and IN
(toH )' The MB85203 provides
higher throughout in interleaved
memory system applications.
Fujitsu has made timing requirements that are referenced to
RAS non-restrictive and deleted
them from the data sheet. These
include tAR, tWCR ' tOHR and tRWO'
As a result, the hold times of the
column address, IN and Was
well as leW~ (CAS to W Delay)
are not restricted by t RCO '

The read mode or write mode is
selected with the W input. A logic
high on the W dictates read
mode, logic low dictates write
mode. Data inputs are disabled
when read mode is selected.
Data Inputs
The 4-bit data is written into the
MB85203 during a write or readwrite cycle. The latter falling edge
of W or eAS is a strobe for the
Data In ~) register. In a write
~, if W is brought low before
CAS, IN are strobed by CAS and
the set-up and hold times are referenced to CAS. In a dell!}led
write or read-writ~cle, W can
be delayed after ~ al~
ready gone low and CAS to W
Delay Time (tcwo ) has been
satisfied.

Address Inputs

Thus INO to IN3 are strobed by

A total of eighteen binary input
address bits are required to decode any 4-bits of data in
1,048,576 cell locatons within the
MB85203.

W, and set-up and hold times are

Nine row address bits are
established on the input pins
(AD through As) and latched
with RAS.
Nine column address bits are established on the input pins and
latched with CAS. All input addresses must be stable on or before the falling edge of RAS. CAS
is internally inhibite~ ~ to
permit triggering of CAS as soon
as the Row Address Hold Time
(tRAH ) specification has been satIsfied and the address inputs
have been changed from rowaddresses to ODlumn addresses.

referenced to W.
Data Outputs

The output buffers of each chip
are three-state TTL compatible
with a fan-out of two standard
TTL loads. OUT are the same
polarity as IN. The output is in
high impedance state until eAS
is brought low. In a read or readwrite cycle, the output is valid
after t RAC from the falling edge of
m;;s when tRco (max) is satisfied, or after IeAC from the falling
edge of CAS when the transition
occurs after tRCD (max). Data remain valid until ~ is returned
to a high level. In a write cycle,
the identical sequence occurs but
data are not valid.
Fast Read-Whlle-Writa-Cycle
The MB85203 has a fast readwhile-write cycle which is

1-265

achieved by precise ODntrol of
the three-state output buffer as
well as by the simplified timings
described in the previous section.
The output ~ffer is controlled by
the state of W when CAS goes
low. When W is low during CAS
transition to low, the MB85203
goes Into the early write mode in
which the output floats and the
common 110 bus can be used on
the system level. Whereas, when
~es low after tewo following
CAS transition to low, the
MB85203 goes into the delayed
write mode. The output then ODntains the data from the cell selected and the data from IN are
written into the cell selected.
Therefore, a very fast read write
cycle (tRC = tRwol is possible
with the MB85203.
Nibble Mode
Nibble mode allows high speed
serial read, write or read-modifywrite access of 2, 3 or 4-bits of
data. The bits of data that may
be accessed during nibble mode
are determined by the 8 row addresses and 8 column addresses.
The 2-bits of addresses (CAe,
RAe) are used to select 1 of the
4 nibble bits for initial access.
After the first bit is accessed by
normal mode, the remaining nibble bils may be accessed by toggling CAS "high" then "low"
while Rim remains low. Toggling
CAS causes RAe and CAs to be
incremented internally while all
other address bits are held ODnstant and makes the next nibble
bit available for access. (See
Table 1). If more than 4-bits are
accessed during nibble mode,
the address sequence will begin
to repeat.

MB8U03.tO
MB8IJaoa·t2
MB8IJ203·tS

Description
(Continued)

If any bit is written during nibble
mode, the new data will be read
on any subsequent access. If the
write operation is executed again
on subsequent access, the new
data will be written into the selected cell location.
In nibble mode, the three-state
control of the OUT pin is determined by the first normal access
cycle.
The data output is controlled only
~e Vii state referenced at the
CAS negative transition of the
normal cycle (first nibble bit).
That is, when twes > twcs (min)
is met, the data output will remain high impedance state
throughout the succeedir)g nibble
cycle regardless of the Vii state.
When leWD> tewD (min) is met,
the data output will contain data
from the cell selected during the
succeeding nibble cycle regardless of the W state. The write operation is done durin.llJlle period
in which the Vii and CAS clocks
are low.
Therefore, the write operation
can be performed bit by bit
during each nibble operation regardless of timing conditions
of W (twes and leWD) during the
normal cycle (first nibble bit).
See Fig. 3.
Refresh:
Refresh of the dynamic memory
cells is accomplished by performing a memory cycle at each of
the 256 row address (Ao through
A7) at least every 4 ms. During
refresh,either VIL or VIH is permitted for As.

The MB85203 offers the following
of refresh.
1) RAS Only refresh avoids any
output during refresh because
the output buffer is in hi~
impedance state unless CAS
is brought low. Strobing each
of 256 row addresses with
RAS will cause all bits in each
row to be refreshed.
2) CAS-before-RAS Refresh:
CAS-before RAS refresh
available on the MB85203
offers an alternate refresh
method. If CAS is held low for
the s~fied period (t FCS) before RAS goes to low, on chip
refresh control clock generators and the refresh address
counter for each chip are enabled, and an internal refresh
operation takes place. After
the refresh operation is performed, the refresh address
counter is automati~ncre
mented for the next CASbefore-RAS refresh operation.
3) Hidden Refresh:
Hidden refresh may take
place while maintaining latest
valid data at the output by extending CAS active time. In
MB85203, hidden refresh
means CAS-before-RAS refresh cycle. The internal refresh address counter
provides the refresh addresses as in a normal CASbefore-RAS refresh cycle.
thre~es

CA8-before-RAS Refresh
Counter Test Cycle
~ecial tim~equence using
CAS-before-RAS counter test
cycle provides a convenient
method of verifying the functionality of CAS-before-RAS refresh
activated circuitry. After the CASbefore-RAS refresh operation, if

CAS goes to high and then goes
low again while RAS is held low,
the read and write operation is
enabled. This is shown in the
CAS-before-RAS counter test
cycle timing diagram. A memory
cell can be addressed with x row
address bits to be defined as
follows:

1) A ROW ADDRESS-Bits Ao
through A7 are defined by the
refresh counter. The other bit
As is set "high" internally.
2) A COLUMN ADDRESS-All the
bits Ao through As are defined
by latching levels on Ao
through As at the second falling
edge of CAS.
Suggested CA8-before-RAS
Counter Test Procedure
1) Initialize the internal refresh
address counter b~ng
eight CAS-before-RAS refresh
cycles.
2) Throughout the test, use the
same column address, and
keep RAs high.
3) Write "low" to all 256 row address on the same column
address by using normal early
write cycles.
4) Read "low" written in step 3
and check, and simultaneously write "high" to the same
address by using internal refresh counter test read-write
cycles. This step is repeated
256 times, with the addresses
being generated by the internal refresh address counter.
5) Read "high" written in step 4)
and check by using normal read
cycle for all 256 locations.
6) Complement the test pattern
and repeat step 3), 4) and 5).

NIBBLE MOOE ADDRESS SEQUENCE EXAMPLE

Column
Nibble Bit

Sequence

RAS

AowAddrese

CAS

Address

0

10101010

mien (nonnel mode)

10101010

toggle CAS (nibble mode)

10101010

10101010

10101010

10101010

(nibble mode)

10101010

10101010

toggle CAS (nibble mode)

10101010

10101010

toggle CAl (nibble mode)
toggle

m

0

PWITSU
1-266

input addresses

generated
Internally

sequence repeats

MB85203.10
MB85203·12
MB85203·15

Description
(Continued)

Decoupllng and Noise
ReductIon RecommendatIons
for MB85203

3. Keep enough timing margin
and remove critical timing in
the board design, to avoid the
problem mentioned in the
above item 2.

To minimize noise induction between signal tines as well as between signal and power supply
lines, good board design practice
requires consideration of the
following:

4. In order to avoid noise induction on the IN line at the failing edge of W when the
delayed write or read-modifywrite cycle is used, the falling
edge of W signal should not
coincide with the transition
point of address and OUT sig-

1. Provide a capacitor of appox.
a few p,F for each module,
though the MB85203 has two
decoupting capacitors of
0.15 p,F on the each module.
2. Remove noise, riging, overshoot and undershoot from
the address, control and data
input lines, so that the
MB85203 won't latch wrong
signals due to the noise induction between signal lines
and between signal and
power supply lines.

nal.(Since decoupting capacitors on the module board
can't smooth the output current at the OUT pin, noise is
inducted on the power supply
line (Vcc or Vss) and also on
the IN line at tRAC or t CAC in
the read cycle).
5. Provide an appropriate damping if necessary, to avoid
excessive overshoot or undershoot on the TIL input
waveforms.

MB85203 Derating Curve

NOT ALLOWABLE

----

AtLOWABt

1

2

"'-~.- ......
i'-3

4

lilAc, CYCLE RATE (MHz)

AIR FLOW
Omls
- . - 1m/s
- - - - 3m/s

5
'.76 MHz

Recommended OperatIng
Conditions
(Referenced to V ss )

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vcc
Vss

4.5
0

5.0
0

5.5
0

V
V

Input high voltage

VIH

2.4

6.5

V

Input low voltage

VIL

-2.0

0.8

V

Operating
Temperature

O°C to

+ 70°C'1

Note: ., Maximum ambient temperature is permlssable under certain conditions. See derating curve.

Capacitance
(TA

= 25°C)

Parameter

Max

Unit

CIN1

40

pF

Input capacitance RAS, CAS, W

CIN2

50

pF

Input capacitance IN

CIN3

15

pF

Output capacitance OUT

COUT

15

pF

Input capacitance

Symbol

Ao to As

1-267

Typ

MB85203.10
MB8S203·12
MB8S203·1S

DC Characteriatlca
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Operating current"l
averag~wer supply current
(RAS. AS cycling; t RC = min.)

MB85203-12

Nibble mode current"l
a~ge power supply current
(RAS = Vil• CAS cycling; ~c

= min.)

Icc2

18

ICC3

220

= min.)

mA

mA

200
88
80

ICC4

mA

72

MB85203-15
MB85203-10
MB85203-12

mA

240

MB85203-15

MB85203-12

Unit

228

MB85203-10

Refresh current 2"1
average power supply current
(CAS-betora-RAS; tRC = min.)
Input leakage current
any input (0 '" VIN '" 5.5V.
Vcc = 5.5V. Vss = OV.
all other pins not under test

260

ICCl

MB85203-10
MB85203-12

Max
280

MB85203-15

Standby current
standby ~r supply current
(RAS = CAS = VIH)
Refresh current 1"1
average POWe~PIY current
(RAS cycling. A = VIH; t RC

Min

MB85203-10

260
Icc5

MB85203-15

240

220

mA

II(l)

-40

40

,.,A

Output leakage current
(data out is disabled. OV '" VOUT '" 5.5V)

IO(l)

-10

10

/LA

Output levels
output high voltage (IOH = - 5 mAl
output low voltage (IOl = 4.2 mAl

V OH
VOL

2.4

= OV)

Note: ·1 ICC is dependent on output loading and cycle rates. Specified values are obtained with the
output open.

I"WI'I'SU
1·268

0.4

V

M885203·tO
M885203·t2
M885203·t5

AC Charactarlstics'l,2,3
(Recommended operating
conditions unless otherwise
noted.)

Parameter

MB85203·tO
Symbol Min
Max

Time between refresh

tREF

Random read/write cycle time'12

tRC

210
210

MB85203·t2
Min
Max

4

M885203·t5
Min
Max

4
230

4
260

Unit
ms
ns

Read-write cycle time'12

tRWC

Access time from RAS",6

t RAC

100

120

150

ns

Access time from CAS'5,6

t CAC

50

60

75

ns

Output buffer turn off delay

tOFF

0

25

0

25

0

30

ns

TransHion time

tT

3

50

3

50

3

50

RAS precharge time

t RP

90

RAS pulse width

tRAS

110

RAS hold time

t RsH

60

CAS pulse width
CAS hold time

t CAS

60

230

100000

260

100

100

120

100000 150

60

75

100000

60

100000 75

50

22

ns
ns

100000

ns

100000

ns

ns

tCSH

110

t RCD

20

CAS to RAS set up time

t cAs

15

20

20

ns

Row-address set up time

ns

RAS to

eAS delay time'7,B

120

ns

150
60

25

ns

75

ns

tASA

0

0

0

Row-address hold time

tRAH

10

12

15

ns

Column address set up time

tASC

0

0

0

ns

Column address hold time

tCAH

15

20

25

ns

Read command set up time

tRCS

0

0

0

ns

Read command hold time
referenced to CAS'll

tRCH

0

0

0

ns

Read command hold time
referenced to RAS'll

tRRH

20

20

20

ns

Notes:

*1 An initial pause of 200 lLS is required after power-up. And then several cycles (to which any 8 cycle to perform refresh afe adequate) are required before proper device operation is achieved. If internal refresh counter is to be effective, a minimum of 8 CAS
before fti:S refresh cydes are required.
*2 AC characteristics assume IT = 5 ns.

*3 V,H (min) and V,l (max) are reference levels for measuring timing of input signals. Also, transition times are measured between
VIH (min) and VIL (max).
*4 Assumes that tRCD .;:;; tRCD (max). If tRCD is greater than the maximum recommended value shown in this table tRAC will
increase by the amount that tRCD exceeds the value shown.
*5 Assumes that tRCD ~ tRCD (max).
·6 Measured with a load equivalent to 2 TTL loads and 100 pF.

·7 Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if
tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC'
"'8 tRCD (min) = tRAH (min) + 2tT (tT = 5 ns) + tASC (min).
*11 Either tRRH or tRCH must be satisfied for a read cycle.
*12 The minimum cycle time is dependent on the ambient temperature and cooling conditions. See Fig. 4 for derating curve.

1-269

M885203·10
M885203.12
M885203.15

AC Characteristics
(Continued) .
(Recommended operating
conditions unless otherwise
noted.)

Parameter

M885203·10
Symbol Min
Mex

Write command set up time"9

twcs

Wr~e

twp

command pulse width

0
15

M885203·12
Min
Max

M885203.15
Min
Max

0

0

ns

20

25

ns

Unit

Write command hold time

t WCH

15

20

25

ns

Write command to RAS lead time

tAWL

50

tCWL

30

60
40

ns

Write command to CAS lead time

40
20

Data in set up time

los

0

0

ns

Data in hold time

tOH

15

20

0
25

~ to W delay"9

tcwo

15

20

25

ns

Refresh set up time for CAS
referenced to RAS

t FCS

20

25

30

ns

Refresh hold time for CAS
referenced to RAS"

tFCH

20

25

30

ns

CAS prechar~me
(CAS-before-RA cycle)

tCPA

20

25

30

ns

tAPC

20

20

20

ns
ns

RAS precharge to CAS active time
(refresh cycles)

ns

ns

Nibble mode read/write cycle time

tNC

50

65

80

Nibble mode read-write cycle time

t NAWC

50

65

80

Nibble mode access time

tNCAC

Nibble mode ~ pulse width

tNCAS

20

30

40

ns

Nibble mode CAS precharge time

t NcP

20

25

ns

Nibble mode read ~ hold time

tNAASH

20

30

30
40

!'iPS hold time

tNwASH

40

50

60

ns

Nibble mode ~ hold time
referenced to RAS

tANH

20

20

20

ns

Refresh counter test cycle time"10

t ATC

330

375

430

ns

tTRAS

230

t CPT

50

Nibble mode write

Refresh counter test
width"lO

!'iPS pulse

Refresh counter test
precharge time"10

Cii\S"

Notes:
*9

!~g~ !nd~~:?m~~~,

20

10000

265
60

10000

ns

40

30

320
70

ns

ns

10000

ns
ns

r: =4:ea~':~~ri:r:::d ~:daS: ~~'~~:,7 r:~!~~::~':i~~~=~ta::)ri::u~~~~tff

entire cycle. tf tewD ~ tcwo (min) the cycle is a reacf..write cycle and data out will contain data read from the selected cell. H neither of the above sets of conditions is satisfied the condition of the data out is indeterminate.
*10 Test mode write cycle only.

FUJITSU

1-270

MB85203·10
MB85203·12
MB85203·15

Timing Diagrams

Read Cycle
~-------------tRC-----~----~~
1---------tR.S-------~~

lIAS

CAS

ADDRESS

V,H
V,L

V,H
VIL

V,H
V,L

W

OUT
(OUToto
OUT,)

V,H
VIL

VOH
HtGH·Z

VOL

VALID
DATA

fZZl DON'T CARE

1·271

MB85203-10
M885203·12
M885203-15

Timing Diagrams
(Continued)

Write Cycle (Early Write)
lAC
IRAS

lID

VIH
VIL
ICSH
IRSH
ICAS

CAS

ADDRESS

VIH
VIL

VIH
VIL

W

VIH
VIL

IN
(INo to IN,)

OUT
(OUTolo
OUT.)

VOH
- - - - - - - - - - - - - - - HIGH-Z--------------VOL

rzn

FUJITSU

1-272

DON'T CARE

MB85203·10
MB85203·12
MB85203·15

Timing Diagrams
(Continued)

Read·Write/Read·Modlfy·Wrlte Cycle

~~---------------------------------------t.wc----------------------------~----------~

ADDRESS

w

OUT (OUTo

toaUTs)

IN
(IN to 1M3)

V,H
VIL
~~~~~~~~~~LULU~~~UL~~~

r.zzJ DON'T CARE

1·273

MB85203.10
MB8S203.12
MB85203.1S

Timing Diagrams
(Continued)

Nibble Mode

\'---____~r

-1 THE CASE OF FtRST NIBBLE CYCLE IS EARLY WRITE

\'----_/

w

IN

OUT

)>-------------HIGH-Z---------------

r--

EARLY WRITE-+NO

OPEN-i~...lfooo.t---WRITE--·~+I~-----WRITE_____f

(ADD INCREMENT)

~VALIDDATA

-2 THE CASE OF FIRST NIBBLE CYCLE IS DELAYED WAITE (READ-WRITE)

\~----------'/-

w

IN

\'----------.J/

\'------lr

-~--*-

OUT

ffi VALID DATA

FUJITSU

1-274

MB85203·10
MB85203·12
MB85203·15

Timing Diagrams
(Continued)

Nibble Mode Read Cycle

V'H
V'L

V'H
V'L

ADDRESS

V'H
VIL

w

V'H
V'L .I...J..i..i..i..i..i..i..Lf.i..i..i..i.J

OUT

YOH

(OUTO

------

tOOUT3) VOL

rzZJ DON'T CARE

1·275

MB85203·10
MB85203·12
MB85203·15

Timing Diagrams
(Continued)

Nibble Mode Write Cycle

IIlI!I

CU

ADDRESS

Iii

IN (INo to
IN,)

OUT (OUT.

to OUT,)

V,.
V,L

V,.
V,L

V,.
V,L

V,.
V,L

Viti
V,L

-----------------------------~G~-------------------------------

t2Zl DON'T CAllE

FWITSU

1·276

MB85203·10
MB85203.12
MB85203·15

Timing Diagrams
(Continued)

Nibble Mode Read.Wrlte Cycle

IIA!I

CiS

V,H
V,L

V,H
V,L

V,H
ADDRESS

W

IN
(IN. to IN,)

V,L

V,H
V,L

V,L

..(..(..I.:..t...t.....r..t...L£J..L.IJ

rzzl DON'T CARE

1-277

MB8S203·10
MB85203·12
MB85203·15

Timing Diagrams
(Continued)

iiAi.only Refresh Cycle
Note: W, IN = Don't Care, As = VIH or VIL
~----------------~c----------------~
I+------~.s------_+I

ADORESS
(1\0'0 A7)

OUT(OUTo
10 OUT,)

VOlt
VOL

------

--------------------~GH~--------------------

~DON'TCARE

CAI·before·iiAi Re1re.h Cycle
Note: Address, W, IN = Don't Care

=ll-~
O~TC:~~;. ~~:-f------------------------HIGH.Z---------------------------

fZLl DON'T CARE

FUJITSU

1·278

MB85203·10
MB85203·12
MB85203·15

Timing Diagrams
(Continued)

Hidden Re1resh Cycle
~------tRC-------<.!

ADDRESS

W(READ)

OUT (OUTo

tOOUT3)

W(READ-

WRITE)

I!Zl DON'T CARE

1-279

M885203·10
M885203·12
M885203.15

Timing Diagram.
(Continued)

CAS.be'or..iiAi Refre.h Counter Te.t Cycle
I..________________________~~~t~~c~==========~~------~

------.1

1.------------------ tm•• -

ADDRESS

W(READ)

~T~. ~~~'----------------!+--and IN
(tOH). Fujitsu has made timing reIjllirements that are referenced to
RAS non-restrictive and deleted
them from the data sheet. These
include tAR, tWCR ' tOHR and tRWO.
As a resu~, the hold times of the
column addre~N a~ Vii as
well as lewD (CAS to W Delay)
are not restricted by tRCO.

The 4-bit data is written into the
MB85204 during a write or readwrite cycle. The latter falling edge
of W or CAS is a strobe for the
IN register. In a write cycle, ifW
is brought low before the negative transition of CAS, the set-up
and hold times are referenced to
CAS. In a delayed write or readwrite cycle, W will be low after
CAS has already been low. Thus
INo to IN3 are strobed by W, and
set-up and hold times are referenced toW.

Page-mode operation permHs
strobing the row-address into the
MB85204 while maintaining RAS
at low throughout all successive
memory operations in which the
row-address doesn't change.
Thus the power dissipated by the
negative going edge of RAS is
saved. Access and cycle times
are decreased because the time
normally required to strobe a new
row address is eliminated.

Address Inputs
A total of eighteen binary input
address bits are required to decode any 4 bits of data in
1,048,576 storage cells within the
MB85204. Nine row address bits
are established on the input pins
(An through As> and latched wHh
RAS. Nine column address bits
are established on the input pins
and latched with ~. All input
addresses must be stable on or
before the falling edge of Rim.
CAS is internally inhibHed by
RAS to permit triggering of ~
as soon as the Row Address
Hold Time (tRAH ) specification
has been satisfied and the address inputs have been changed
from row addresses to column
addresses.

Write Enable
The read mode or write mode is
selected with the W input. A logic
high on the W dictates read
mode, logic low dictates write
mode. Data inputs are disabled
when read mode is selected.

Dats Outputs
The output buffers of each chip
are three-state TTL compatible
with a fan-out of two standard
TTL loads. OUT is the same polarRy as IN. The output is in high
impedance state until OAS is
brought low. In a read or readwrite cycle, the output is valid
after tf!b.C..!rom negative transition
of the RAS when tRCO (max) is
satisfied, or after~ from negative transHion of CAS when the
transHion occurs after tRccJ!!lax).
Data remains valid until CAS is
returned to a high level. In a write
cycle, the identical sequence occurs but data is not valid.

Faat Reacl-Whlle-Write Cycle
The MB85204 has a fast readwhile-write cycle which is
achieved by precise control of
the three-state output buffer as
well as by the simplified timings
described in the previous section.
The output buffer is controlled by
the state of VIi when CAS goes
low. When W is low during CAS
transition to low, the MB85204
goes into the early wrHe mode in
which the output floats and the
common I/O bus can be used on
the system level. Whereas, when
~oes low after t cwo following
CAS transition to low, the
MB85204 goes into the delayed
write mode. The output then contains the data from the cell selected and the data from IN are
written into the cell selected.
Therefore, a very fast read-write
cycle (tRC = tRwol is possible
wHh the MB85204.

1-284

Refresh
Refresh of the dynamic memory
cells is accomplished by performing a memory cycle at each of
the 256 row addresses (Ao
through A7) at least every 4 ms.
During refresh, either V 1L or V1H is
permitted for As. Then MB85204
offers the following three types of
refresh.

1) Rim-Only Refresh;

RAS Only refresh avoids any
output during refresh because
the output buffer is in high
impedance state unless OAS
is brought low. Strobing each
of 256 row addresses with
RAS will cause all bits in each
row to be refreshed.
2) CAS-before-RAS Refresh;
CAS-before-RAS refresh
available on the MB85204 offers an alternate refresh
method. If CAS is held low for
the s~ied period ("'cs) before RAS goes to low, on chip
refresh control clock generators and the refresh address
counter for each chip are enabled, and an internal refresh
operation takes place. After
the refresh operation has
been executed the refresh address counter is automat~
incremented for the next CASbefore-l'IAS refresh operation.

3) Hidden Refresh;
Hidden refresh may take
place while maintaining latest
valid data at the output by extending CAS active time. In
the MB85204, hidden refresh
means CA8-before-RAS refresh and the internal refresh
address is used; that is, no
external refresh address is
needed.

MB85204·10
MB85204·12
MB85204·15

Description
(Continued)

CAs.before-RAS Refresh
Counter Test Cycle
~ial tim~sequence using
CAS-before-RAS counter test
cycle provides a convenient
method of verifying the lunctionality of CAS-before-RAS refresh
activated circu~ry. After the CASbefore-RAS refresh operation, if
CAS goes into h~nd goes into
low again while RAS is held low,
the read and write operations are
enabled. This is shown in the
CAS-belore-RAS counter test
cycle timing diagram. A memory
cell address (consisting of a row
address (9 bits) and a column
address (9 b~» to be accessed,
can be defined as follows:

1) A ROW ADDRESS-Bits

To minimize noise induction between signal lines as well as between signal and power supply
lines, good board design practice
requires consideration 01 the
following:

E

addre!!.£ounter b~ing
eight CAS-before-RAS refresh
cycles.
2) Throughout the test, use the
same column address, and
keep RA8 high.

NOT ALLOWABLE

----

i

1

dress on the same column
address by using normal early
write cycles.

"'"

60

~

3) Write "low" to all 256 row ad-

5) Provide an appropriate damping il necessary, to avoid excessive overshoot or
undershoot on the TTL input
waveform.

MB85204 Derating Curve

~ 70

1) Initialize the internal refresh

tion on the IN line at the failing edge of W when the
delayed write or read-modifywrite cycle is used, the falling
edge of IN signal should not
coincide with the transition
point of address and OUT signals. (Since decoupling capacitors on the module board
can't smooth the output current at the OUT pin, noise is
inducted on the power supply
line (Vee or Vss) and also on
the IN line at t RAC or t CAC in
the read cycle.)

2) Remove noise, overshoot and
undershoot from the address,
control and data-input lines,
so that the MB85204 won't
latch wrong signals due to the
noise induction between signal lines, and between signal
and power supply lines.

Pia

Suggested CAs.before-RAS
Counter Test Procedure

4) In order to avoid noise induc-

') Provide a capac~or of approx.
a few p.F for each moduleeven though the MB85204
has two or four decoupling capacitors of 0.1 p.F on each
module.

through A7 are defined by the
refresh counter. The other bit
As is set high internally.
2) A COLUMN ADDRESS-All
the bits Pia through As are defined by latching levels on Pia
through As at the second failing edge of CAS.

3) Keep enough timing margin
and remove critical timing in
the board design to avoid the
problem mentioned in Item 2
above.

Decoupllng and Nolaa Reduction Racommendatlons for
MB85204

!c
t-

4) Read "low" written in step (3)

and check, and simu~ane
ously write "high" to the same
address by using internal refresh counter test read-write
cycles. This spec is repeated
256 times, with the addresses
being generated by internal
refresh address counter.
5) Read "high" written in step (4)
and check by using normal
read cycle for all 256
locations.
6) Complement the test pattern
and repeat step (3), (4) and
(5).

FUJITSU
1-285

~.- ......

AlLOWABlE

AIR FLOW
Om's

~

- . - 1m/s
- - - - 3m/s

50

40
1

2

3

4

1/'RC. CYCLE RATE (MHz)

5
4.76 MHz

MB8S204·10
MB8S204·12
MB8S2CJ4.1S

Recommended Operating
Conditions
(Referenced to Vss)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vcc
Vss

4.5
0

5.0
0

5.5
0

v

Input high voltage

VIH

2.4

6.5

V

Input low voltage

VIL

-2.0

0.8

Operating
Temperature

V

~--~--~----~--------~-----------------V~---

O°C to

+ 70°C"1

Note: 1* Maximum ambient temperature is permissible under certain conditions. See derating curve.

Capacitance
(TA = 25°C)

Parameter
Input capcitance

Symbol

Ao to As

Typ

Max

Unit

C IN1

40

pF

Input capacHance RAS, CAS, W

CIN2

50

pF

Input capacitance IN

CIN3

15

pF

Output capacitance OUT

COUT

15

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

MB8S204·10 MB8S204·12 MB85204·1S
Min
Max Min
Max
Min
Max Unit

Operating current
Averagmwer supply current
(RAS, CA cycling; tRC = Min.)

ICCl

280

Standby current
Standby power supply current
(RAS = CAS = VIH)

IC02

18

18

18

mA

ICC3

240

220

200

mA

Page mode current
Average power supply current
(RAS = VIL, CAS cycling; tpc = Min.)

ICC4

140

120

100

mA

Refresh current 2"1
Average power supply current
(CAS·belore-RAS; tRe = Min.)

Ices

260

240

220

mA

Input leakage current, any input (0 ..
V IN .. 5.5V, Vee = 5.5V, Vss = OV,
all other pins not under test = OV)

II(L)

-40

40

-40

40

-40

40

pA

Output leakage current
(Data out is disabled,
OV .. VOUT .. 5.5V)

IO(L)

-10

10

-10

10

-10

10

/LA

VOH
VOL

2.4

Refresh current 1"1
Average powe!:'!!pply current
(RAS cycling, CAS = VIH ; t RC

= Min.)

Output levels
Output high voltage (IOH = -5 mAl
Output low voltage (IOL = 4.2 mAl

260

228

2.4
0.4

2.4
0.4

Notes: "1 ICC Is dependent on output loading and cycle rales. Specified values are obtained with the output open.

1·286

mA

0.4

V

MB85204·10
MB85204·12
MB85204·15

AC Characteristics'1,2,3
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Time between refresh

tREF

MB85204·10
Min
Max

MB85204-12
Min
Max

MB85204·15
Min
Max

4

4

4

Unit
ms

Random read/write
cycle time'12

t RC

210

230

260

ns

Read-write-cycle time'12

tRWC

210

230

260

ns

Access time from RAS'4,5

tRAC

100

120

150

Access time from CAS'5,S

t CAC

50

60

75

ns

ns

Output buffer turn off delay tOFF

0

25

0

25

0

30

ns

Transition time

tT

3

50

3

50

3

50

ns

RAS precharge time

t RP

90

RAS pulse width

t RAS

100000

RAS hold time

t RSH

110
60

CAS pulse width

leAS

60

100000

CAS hold time

tCSH

110

RAS to CAS delay time'7,B tRCD

20

CAS to RAS set up time

t CRS

15

Row address set up time

t ASR

Row address hold time

tRAH

Column address set
uptime

tASC

Column address hold time

tCAH

100

100

120
60

100000

60

100000

120
50

22

ns

150
75

100000

75

100000

150
60

25

ns
ns
ns
ns

75

ns

20
0

ns

0

20
0

10

12

15

ns

0

0

0

ns

ns

15

20

25

ns

Read command set up time tRcs

0

0

0

ns

Read command hold time
referenced to CAS'11

t RCH

0

0

0

ns

Read command hold time
referenced to RAS'11

tRRH

20

20

20

ns

Write command set
up time'.

twcs

0

0

0

ns

Write command pulse width twp

15

20

25

ns

Write command hold time

t WCH

15

20

25

ns

Write command to RAS
lead time

tRWL

40

50

60

ns

Notes:

*1 An initial pause of 200 IA-S is required after power-up. And then several cycle (to which any 8 cycle to perform refresh are
adequate) are required before proper device operation Is achieved.
If internal refresh counter is to be effective, a minimum of 8 CAS before RA§ refresh cycles are required.
*2 AC characteristics assume IT = 5 ns.
*3 VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between
VIH (min) and V 1l (max).
*4

~C:~=S~:~!Ra~:tt';1,~t~~~)~:~~~~t~egv~~~rs~:~~~e maximum recommended value shown in this table, tRAC will

*5 Assumes that tACO :3' tACO (max).

*6 Measured with a load equivalent to 2 TIL loads and 100 pF.
*7 Operation within the tRCD (max) limit insures that tRAC (max) can be met. tACO (max) is specified as a reference point only; if
tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC*8 tRCD (min) "" tRAH (min) + 2tT (IT = 5 ns) + tASC (min).
*9 twcs and tCWD are not restrictive operating parameters. They are induded in the data sheet as electrical characteristics only. "

~~tf~ :~~CJ3~':ci,;h~c:~e(~i~n;::r~;:~ i:~:'~:~~::~ :tawi!~~~:7r: :.r:~tg~~p::a::e!..:0:~o~t
. neither of the above sets of conditions is satisfied the condition of the data out is indeterminate.
*11 Either tRRH or tRCH must be satisfied for a read cyde.
*12 The minimum cyde time is dependent on the ambient temperature and cooling conditions.
See derating curve.

FUJITSU

1-287

MB85204.10
MB85204·12
MB85204.15

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Symbol

MB85204·10
Min
Max

MB85204·12
Min
Max

MB85204·15
Min
Max

Unit

tCWL

40

50

60

ns

Data in set up time

tos

0

0

0

ns

Data in hold time

tOH

15

20

25

ns

CAS to W delay"g

lewD

15

20

25

ns

Refresh set up time for
CAS referenced to RAS

t FCS

20

25

30

ns

Refresh hold time for CAS
Referenced to RAS

tFCH

20

25

30

ns

active time

tRPC

20

20

20

ns

Page mode read/write
cycle time

tpc

100

120

150

ns

Page mode read/write
cycle time

tpRwC

100

120

150

ns

Page mode CAS
precharge time

tcp

40

50

65

ns

Refresh counter test cycle
time"10

tRTC

330

375

430

ns

Refresh counter test RAS
pulse width"10

tTRAS

230

Refresh counter test CAS
precharge time"10

tCPT

50

60

70

ns

CAS precharge time
(CAS-before-RAS cycle)

tePR

20

25

30

ns

Parameter
Write command to
lead time

CAS

RAS precharge to CAS

NotH:

*9

10000

265

10000

320

10000

ns

twcs and leWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. H

~~trr: ~~~1P~6,~h~c:~e(:i~n~r~:: i::.::~~:~a aO~ ~~tawt~~~~~~~ ~:i~~tg~~p::a::~~~~~~t
neither of the above sets of conditions is satisfied the condition of the data out Is indeterminate.
*10 Test mode write cycle only.

1-288

MB85204·10
MB85204·12
MB85204·15

Timing Diagrams
Read Cycle

1-~~~~~~~~~~~-tRC ~~~~~--;-~~~~---+j

1-~~~~~~~-tRAS-~~~~~~~~

F!OUl

V'H
V"

CAS

V'H
V'l

ADDRESS

V'H
V'l

W

V'H
V'l

V'H
OUT

HIGH-Z

V'l

VALID

DATA

rzzJ

FUJITSU

1·289

DON'T CARE

MB85204-10
MB85204-12
MB85204-15

Timing Diagrams
(Continued)

Write Cycle (Early Write,

IRe
tRAS

lIAS

V,H
V,L
....--tRP

tCSH
tRSH

teAs

as

ADDRESS

III

V,H
V,L

V,H
V,L

V,H
V,L

IN

VOlt

OUT

---------------HIGH-Z---------------

r72J DON'T CARE

1-290

M885204-tO
M885204-t2
M885204-t5

Tlmlnll Dlallrams
(Continued)

Read·Wrlte/Read.Modlfy.Wrlte Cycle

ADDRESS

w

OUT

IN

t'm DON'T CARE

FUJITSU
1·291

MB85204-10
MB85204·12
MB85204·15

Timing Dla.rams
(Continued)

Page Mode Read Cycle

IWi

V'H
V"

CAS

V'H
V'L

ADDRESS

V'H
V'L

OUT

Vo.
VOL

W

fZZ) DON'T CARE
(XXI VALID DATA

1-292

MB85204-10
MB85204·12
MB85204-15

Timing Diagrams
(Continued)

Itll!

l:)J;S

v,.
VOL

v,.
VOL

ADDRESS

VIH
V'L

W

V,.
V'L

VOH
OUT

IN

VOL

V,.
V'L

~DON'TCARE

FUJITSU
1·293

MB85204·10
MB85204·12
MB85204.15

Timing Diagrams
(Continued)
Page Mode Write Cycle

tRAS

!lAS

V,H
V"

CAS

ADDRESS

V,H
V"

V,H
V"

W

V,H
V"

IN

OUT

V,H
VOL

VOH

VOL

-------------------------HIGH-Z---------------------

I7ZLl DON'T CARE

1-294

. . .52....10
. . .5204012
•••52....15

Timing DI.grams
(Continued)

iiAl-only Refresh Cycle
Note: CAS

= VIH, W, IN = Don't Care, As = VIH or VIL
~---------IRC---------~
j.----RAS,----+i

IIJI"S"

ADDRESS
(Ao10 A7)

OUT

VOH

---------------------HIG~Z----------------------

VOL

NOTE: 'I ANY COMBINAnONS OF lIJI"So TO Rn3 ARE ALLOWED AND Rn's
TO BE NOT REFRESHED ARE IN V'H_

rz2I DON'T CARE

CAS·belore·AD Refresh Cycle
Note: Address, W, IN

=

Don't care

~t--I~F
OUT

~~~--f------------------------- HIG~Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

rzzJ DON'T CARE

FU.JJTSU
1-295

MB85204-1Cl
MB85204-12
MB85204-15

Timing Di.grams
(Continued)

Hidden R.tr.... Cycl.
t-------t"C-------~

ADDRESS

W(READ)

OUT

W(READWRITE)

o

1-296

DON'T CARE

MB85204.tO
MB85204·t2
MB85204·t5

Timing Diagrams
(Continued)

CAS·be'ore-RAS Refresh Counter Test Cycle

tRTe

ADDRESS

W(READ)

OUT

~~:------------------------------~~----------+01"""'

Vee

2

FQSo

3

OUT

4

A,

As

o

IN

7

W
I!Ul

8
10

A.

262,I44-BlT
STORAGE CELL

_Vee
_ V..

FUNCTIONAL TRUTH TABLE FOR EACH CHIP

iilII

en

w

IN

OUT

H

H

Don'I care

Don' care

HIgh-Z

Road

Write

No

No

-

A7

11

NC

12

CAS

13

nAI2

14

A2

15

A,

16

As
As

17

RAS3

19

A.

20

18

Vee

21

V..

22

Note

No

Standby

Vaa

Road

L

L

H

Don't Care

Valid Data

Vaa

No

L

L

L

Valid Data

Hlgh-Z

No

Vaa

Vaa

L

L

L

Valid Date

Valid Date

Vaa

Vaa

Vaa

Early Wrlte
twcs (min)

twcs "

DeIayacI Wrlte or _write
ICWO .. ICWO (min)

L

H

Don' care

Don'I Core

Hlgh-Z

No

No

Vaa

iiD-onlyRelreoh

L

L

Don't Cere

Don't Care

V.11d Data

No

No

V..

C!D-beIore-RAS ReIreoh Valid
date Hlacted at prevlOU8 Road
or Raad-Wrlte cycle I. haJd

H

L

Don't care

Don' care

HIgh-Z

No

No

No

CASdllllUrb

Functional Block Diagram

AAIo-+t-t-t----I

RASI

CHIP 0

CHIP 2

CHIP 1

CHIP 3

-+-++1----1

L----------~-OUT

FUJITSU
1-300

MB85208·12
MB85208.15

MB85208 Block Diagrams
and Pin Assignments
(Continued)

FUNcnONAL TRUTH TABLE FOR MODULE

RASOto

IIAS3

CAS

W

IN

OUT

Function

H

H

Don" Care

Don't Care

Hlgh-Z

Standby

L'1

L

H

Don't eare

Valid Data

Read cycle

L'1

L

L

Valid Data

Hlgh-Z

Write cycle

L'1

L

H __ L*2

Valid Oata

Valid Data

H .... L*3

H_L*3

Don't Care

Don't eare

Hlgh-Z

CAS-belo. .

'L

H

Don't Care

Don't Care

Hlgh-Z

RAS-only Refresh cycle

Read-write cycle

m

R_h cycle

Notes: *1 It 18 for the selected liAS, and other RAS. are high.
'2 ICWD '" ICWD (min).
'3 ~CS '" IFCS (min).

Absolute Maximum Ratings
(See Note)

.;;R_a_d;;n;:g..._ _ _ _ _ _ _ _ _ _ _ _...;S;;.:Y~m;;b;.;o;,;I_ _ _ _...;;.;;;;;.;;.
Value ....- - - - - ; ; . ; .Unit
;;;
Voltage on any pin relative to Vss

VIN , VOUT

-1 to +7

V

Voltage on Vcc supply relative to Vss

Vee

-1 to +7

V

Storage temperature

Tstg

-55 to +150

·C

Power dissipation

Po

2.4

W

50

mA

S~ort

circuit output current

Note: Permanent device damage may occur jf ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device retlability.

Description
Slmp'e llmlng Requirement
The MB85208 has improved circuitry that eases timing requirements for high speed access
operations. The MB85208 can
operate under the condition of
tRco (max) = !cAC thus providing
optimal timing for address multiplexing. In addition, the MB85208
has the minimal hold times of
address (tCAH)' W (twCH) and IN
(tOH)' Fujitsu has made timing reCJ!!!!!Iments that are referenced to
RAS non-restrictive and deleted
them from the data sheet. These
include tAR' tWCR' tOHR and tRWO'
As a result, the hold times of the
column address, IN and ViI as
wall as lewD (c;J;S to Vii Delay)
are not restricted by tRCO'

Address Inputs
A total of eighteen bin~nput
address bits and four RAS clocks
are required to decode any 1 of
1,048,576 locations within the
MB85208. Nine row address bits

are established on the input pins
(AD through As) and latched with
the RAS (one of RASO to RAS3)
of the selected chip. Nine column
address bits are established on
the input pins and latched with
~. All input addresses must
be stable on or before the falling
edge of FiMi. CAS is internally
inhibited byl!AS to permit triggering of CAS as soon as the
Row Address Hold Time (tRAH)
specification has been satisfied
and the address inputs have
been changed from row addresses to column addresses.
RASOto RAS3
The MB85208 has four RAS inputs in order to select a chi~
within the MB85208. Other RASs
except for one RAS to be selected must be high to avoid data
conflict during read, delayed write
or read-write cycles.

1-301

Write Enable
The read mode or write mode is
selected with the Vii input. A high
on the Vii selects read mode, a
low selects write mode. Data input is disabled when read mode
is selected.

Data Input
Data is written into the ~ selected by RAS (one of RASO to
FiMi3) of MB85208 during a
write or read-write.,9'cle. The latter falling edge of W or CAS is a
strobe for the IN register. In a
write cycle, if Vii is brought low
before the falling edge of CAS,
the set-up and hold times are referenced to 00. In a del~ed
write or read-write cycle, W can'
be low after CAS has already
been low and CAS to Vii Delay
time (tcwo) has been satisfied
(read-write ~cle). Thus IN is
strobed by W, and set-up and
hold times are referenced to Vii.

M88&208·12
M88&208·1&

Description
(Continued)

Data Output
The output buffer of each chip is
three-state TIL compatible with a
fan-out of two standard TTL
loads. OUT is the same polarity
as IN. The output is In~
Impedance stete until A is
brought low. In a read or readwrite cycle, the output is valid
after t RAC from the falling edge of
the selected FiAS when t RCD
(max) is satisfied, or after ~
from negative transition of
when the transition occurs after
t RCD
Data remains valid
until A is returned to a high. In
a write cycle, the identical saquence occurs but date is not
valid.

m).

Fast Read·Whlle-Write Cycle
The MB85208 has a fast readwhile-write cycle which is
achieved by preCise control of
the three-state output buffer as
well as by the simplified timings
described in the previous section.
The output buffer is controlled by
the state of W when CAS goes
low. When Wis low during CAS
transition to low,the MB85208
goes into the early write mode in
which the output floats and the
common I/O bus can be used on
.!!!,e system level. Whereas, when
~oes low after tCWD following
A transition to low, the
MB85208 goes into the delayed
write mode. The output then contains the data from the cell selected and the date from IN are
written into the cell selected.
Therefore, a very fast read-write
cycle (tRC = tRwol is possible
with the MB85208.
Nibble Mode
Nibble Mode allows high speed
serial read, write or read-modifywrite access of 2, 3 or 4 bits of
data. The date that will be accessed during nibble mode are
determined by the 8 row and 8
column addresses. The 2 addresses (CAs and RAe) are used
to select 1 of 4 nibble bits for initial access. After the first bit is
accessed by normal mode, the
followed nibble bits will be accessed by togg~CAS high
then low while RA remains low.
Toggling CAS causes RAs and
CAe to be incremented internally
while all other address bits are
held constant and makes the
next nibble bH available for

access. " more than 4 bits are
accessed during nibble mode,
the address sequence will begin
to repeat. If any bit Is written during nibble mode, the new data
will be read on any subsequent
access. If the write operation is
executed again on subsequent
access, the new data will be written into the selected cells. In nibble mode, three-state control of
OUT pin is determined by the
first normal access cycle. The
OUT is controlled only by the
state of W strobed by the falling
edge of ~ on the first nibble
bit. That is when twcs .. twes
(min) is met, the OUT will remain
high impedance throughout the
succeeding nibble cycle regardless of W state. Whereas, when
tcwD .. leWD (min) is met the
OUT will contain the accessed
date during the succeeding nibble cycle regardless of W stete.
The write operation is done during CAS and Ware low. Therefore, the write operation can be
done bit by bit during each nibble
operation reg!!!.,dless of the timing
conditions of W (twcs and tCWD )
during the first nibble bit.
Refresh
Refresh of the dynamic memory
cells is accomplished by performing a memory cycle at each of
the 256 row addresses (Ao
through A7) at least every 4 ms.
During refresh, either V1L or V1H is
permitted f~ and~ combi0 to RA 3 are ainations of
lOWed. When all chips are
refreshed simulteneously, the average power dissipation of the
module must be less than 640
mW at any 100 ms interval.
The MB85208 offers the following
three types of refresh.
1) RAS-Only Refresh;
RAS-only refresh avoids any
output data during refresh because the output buffer is in
~ impedance state unless
Is brought low. Strobing
each of 256 row addresses
with FiAS will cause all bits in
each row to be refreshed.
2) CAS-before-~ Refresh;
~-before-mrn refresh
available on the MB85208 offers an alternate refresh
method. If CAS'is brought low
before the specified period,
CAS Set Up TIme Referenced

FUJITSU
1-302

to ~ (tFCS ) has been satisfied before the failing edge of
~, on chip refresh control
clock generators and the refresh address counter for
each chip are enabled, and
an internal refresh operation
take place. After the refresh
operation has been executed
the refresh address counter Is
automati~ incremented for
the next A -before-RiiS refresh operation.
3) Hidden Refresh;
Hidden refresh may teke
place while maintaining latest
valid date at the output by extending ~ active time. In
the MB85208, hidden refresh
means CAS-befora-RAS refresh and the internal refresh
address Is used; that Is, no
refresh address is needed.
CAi-before-RAS Refresh
Counter Test Cycle
~ecial tim~sequence using

A -before-RA counter test
cycle provides a convenient
method of verifying the functionality of CAS-before-RAS refresh
activated cirCUitry. After the CASbefore-RAS refresh operation, If
CAS goes into h~nd goes into
low again while RAS is held low,
the read and write operation are
enabled. This is shown in the
CAS-before-RAS counter test
cycle timing diagram. A memory
cell address (consisting of a row
address (9 bits) and a column
address (9 bits)) to be accessed,
can be defined as follows:
1) A ROW ADDRESS-Bits Ac
through A7 are defined by the
refresh counter. The other bit
As is set high internally.
2) A COLUMN ADDRESS-All
the bits Ac through As are defined by latching levels on Ac
through As at the second falling edge of~.

MB85208-12
MB85208-15

Description
(Continued)

Suggested CAS-before-RAS
Counter Test Procedure

3) By using read-modify-write
cycle, read the lows written at
the last step and write a new
high in the same cycle. This
cycle is repeated 256 times,
and highs are written into the
256 memory cells.

1) Initialize the internal refresh
counter." For this o~tion,
the 8 CAS-before-RAS refresh cycles are required.
2) Write a test pattern of lows
into memory cells at a single
column address and 256 row
addresses.

4) Read the high written at the
last step.
5) Compliment the test pattern
and repeat the steps 2, 3 and
4.
6) Repeat steps 2 through 5 for
another 3 chips.

Nibble Mode Addreea Sequence Example
SEQUENCE

NIBBLE BIT

ROWADORESS

cAs

COLUMN
ADORESS

RAS/CAlI (normal m_)

1

0

10101010

0

10101010

1oggJo CAlI ( n _ mode)

2

1

10101010

0

10101010

en (nibble m_)

3

0

10101010

1

10101010

4

1

10101010

1

10101010

1

0

10101010

0

10101010

toggle

en (nibble m_)
togglo en (nlbble mode)
toggle

Decoupllng and Noise Reduction Recommendatlona for
MB85208
To minimize noise induction between signal lines as well as between signal and power supply
lines, good board design practice
requires consideration of the
following:
1) Provide a capacitor of approx.
a few ,...F for each moduleeven though the MB85208
has two or four decoupling capacitors of 0.5,...F on each
module.
2) Remove noise, overshoot and
undershoot from the address,
control and data-input lines,
so that the MB85208 won't
latch wrong Signals due to the
noise induction between signal lines, and between signal
and power supply lines.

Recommended Operating
Conditions
(Referenced to Vss )

RAS

3) Keep enough timing margin
and remove critical timing in
the board design to avoid the
problem mentioned in Item 2
above.

Input.deI.....

genended Internally

.equ.nce .......

5) Provide an appropriate damping if necessary, to avoid excessive overshoot or undershoot on the TTL input
waveform.

4) In order to avoid noise induction on the IN line at the failing edge of iii when the
delayed wr~e or read-modifywrite cycle is used, the falling
edge of Vii signal should not
coincide with the trans~ion
point of address and OUT signals. Since decoupling capacitors on the module board"
can't smooth the output current at the OUT pin, noise is
introduced on the power supply line (Vee or Vss ) and also
on the IN line at t RAe or tCAe
in the read cycle.

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee
Vss

4.5
0

5.0
0

5.5
0

V
V

Input high voltage

VIH

2.4

6.5

V

Input low voltage

VIL

-2.0

0.8

V

1-303

Operating
Temperature

O·Cto +70·C

MB85208·12
MB85208·1S

Capacitance
(TA

= 25°C)

Parameter

Symbol

Input capacitance _
Ao through As, IN, W

C'Nl

Input capacitance RASO through RAS3
Input capacitance

OAS

Output capacitance OUT

Typ

Max

Unit

50

pF

C'N2

15

pF

C'N3

65

pF

COUT

55

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

MB85208·12
Min
Max

MB85208·15
Min
Max

Parameter

Symbol

Operating currenf 1
Avera~ower supply current
(one
'2, CAS cycling; tRC = min.)

ICCl

79

71

mA

Standby current
Standby power supply current
(RAS = CAS = V'H)

ICC2

18

18

mA

ICC3

220

200

mA

ICC4

34

32

mA

Refresh current 2'4
Average power s m current
(ali flAS cycling,
-before-AAS)

Ice5

240

220

mA

Input leakage current
Any input (0 .. V'N .. 5.5V,
VCC = 5.SV, Vss = OV,
ali other pins not under test

I'(L)

-40

40

-40

40

p,A

IO(L)

-40

40

-40

40

p,A

VOH
VOL

2.4

Refresh current 1'1.4
Average power supply current
(CAS = V'H' ali RAS cycling; t RC

= min)

Unit

Nibble mode currenfl
Aver~ower sup~urrent

(one
'3
tpc = min)

= V'L' CA

cycling;

= OV)

Output leakage current
(Data out is disabled,
OV .. VOUT .. 5.5V)
Output levels
Output high voltage (lOH = -5 mAl
Output low voltage (IOL = 4.2 mAl
Notes:

2.4
0.4

0.4

V

:~ ~~ :e~::~ ~~ ~1~ '=':h:~m!ea~:t~~'v~~~cified values are obtained with the output open.

m

"3 The selected
is in V,L and other RA§s are in V,H'
"4 When all chips are refreshed simultaneously, the average power dissipation of the module must be less than 640 mW at any
100 ms interval.

FUJITSU
1-304

MB85208·12
MB85208·15

AC Characteristics"' ,2,3
(Recommended operating
conditions unless otherwise
noted.)

MB85208·12
Min
Ma.

Parameter

Symbol

Time between refresh

tAEF

Random read/write
cycle time

t AC

230
230

4

t AwC
t RAC

120

Access time from CAS"5,6

tCAc

60
25
50

ioFF
tT

RAS precharge time

tAP

RAS pulse width

tRAS

RAS hold time

tRSH

CAS pulse width

t CAS

CAS hold time

tCSH

FiAS to CAS delay time"7,S
CAS to RAS set up time

t RCO
IeRS

Row address set up time

t ASR

Row address hold time
Column address set
uptime

0
3
100
120
60
60
120
22

10000
10000

0
3
100
150
75
75

tRAH

20
0
12

25
20
0
15

ns

ns

150
75

ns

30
50

ns

ns

ns

ns

10000

ns
ns

10000

150
60

Unit

ns

260

Read-write-cycle time

Output buffer turn off delay

4
260

Access time from RAS"4,6

Transition time

MB85208·15
Min
Ma.

ns
ns

75

ns
ns
ns
ns

t ASC

0

0

ns

Column address hold time

leAH
t RCS

25
0

ns

Read command set up time

20
0

Read command hold time
referenced to CA§"'O

tRCH

0

0

ns

Read command hold time
referenced to fjAS"'O

tRRH

20

20

ns

Write command set
uptime

twcs

0

0

ns

Write command hold time

t WCH

ns

twp

20
20

25

Write command pulse width

25

ns

tRWL

50

60

ns

Write command to
lead time

RAS

Write command to CAS
lead time

ns

tCWL

30

40

ns

Data in set up time

tos

Data in hold time

tOH

0
20

0
25

ns

Notee:

ns

*1 An initial pause of 200 JA.S is required after power-up. And then several cycles of all m's (to which any 8 cycles to perform

~~~~~r~ a:~~~~~r~~r~:!~~~::ed~~~r::.eration Is achieved. If internal refresh counter is to be effective, a
*2 AC characteristics assume IT = 5 ns.
*3 V1H (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between
VIH (min) and VIL (max).
*4 Assumes that tACO" tRCD (max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will
increase by the amount that tRCD exceeds the value shown.
*5 Assumes that tRCD;;a. tRCD (max).
*6 Measured with a load equivalent to 2 TIL loads and 100 pF.
*7 Operation within the tRCD (max) Umit insures that tRAC (max) can be met. tRCD (max) Is specified as a reference point only; if
tACO is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC'
"S tRCO (min) - tRAH (min) + 2tT (tT - 5 ns) + tASC (min).
*10 Either tRRH or tRCH must be satisfied for B read cycle.

1-305

AC Characterlatlca'I,2,3
(Continued)
(Recommended operating
conditions unless otherwise
noted,)

."mbol

MB85208·12
Min
Max

MB85208·15
Min
Max

Unit

tCWD

20

25

ns

referenced to RAS
(GAS-before-RAS)

tFCS

25

30

ns

00 hold time referenced
to RAS (OO-before-RAS)

t FCH

25

30

ns

RAS precharge to
00 active time
(GAS-before-RAS)

tRPC

20

20

ns

CAS prechar~me
(CAS-before- S cycle)

tCPR

25

30

ns

Nibble mode read/write
cycle time

t NC

65

80

ns

Nibble mode read-write
cycle time

tNRWC

65

Nibble mode access time

tNCAC

Nibble mode CAS
pulse width

tNCAS

30

40

ns

Nibble mode CAS
precharge time

tNCP

25

30

ns

RAS hold time

~RRSH

30

40

ns

Nibble mode write
RAShold time

~WRSH

60

60

ns

Refresh counter test
cycle time'll

tATC

375

430

ns

AMi pulse width'll

tTRAS

265

Refresh counter test
CAS precharge time'll

tCPT

60

70

ns

Nibble mode CAS hold
time referenced to RAS

tRNH

20

20

ns

RAStoRAS
precharge time

tRRP

0

0

ns

Paramater
CAS to

W delay'9

CAS set up ti~

Nibble mode read

Refresh counter test

Notes:

80
30

10000

ns

40

320

10000

ns

ns

"9 twcs and leWD are not restrictive operating parameters. They are Included in the data sheet as electrical characteristics only. If

~9: :~i:.1ft6~6·;h~c:~(:i~nths:r~:~: i!:~:~::~ ~~w~~~~=~ :~i~~~~r!~~:~ct~~O~~~o~t
neither of the above sets of conditions is satisfied the condition of the data out is indeterminate.
"11 Refresh counter test cycle only.

FUJITSU
1-306

MB85208·12
MB85208·15

Timing Diagrams

R.adCycle

RJIS'I

~-+~---------------------'RC----------~--------~
I+--------'RAS--------~
RJIS"

ADDRESS

w

V,H
V,L '..LLl..J....i...u.:..t...J'f-''-'-LJ

OUT

V,H
V,L - - - - - - - - - - - - H I G H - Z

NOTES, ., IT IS FOR UNSELECTED 1IlI!.
'2 IT IS FOR THE SELECTED RJIS.

1·307

VALID
DATA

~DON'TCARE

MB85208·12
MB85208·15

Timing Diagrams
(Continued)

Write Cycle (Early Write)

lin"

VIH
V,L

~---------.~----------~
1+--------111•• ---------;~
lin"

V,H
V,L
1+-------:--tcSH--------;~

--*------••OH - - - - + - I

IIIp

~---tc'S-----iooJ

CAl

ADDRESS

W

V,H
V,L

V,H
V,L

V,H
V,L

IN

Yo.
---------------H~H~-----------------

OUT

VOL

NOTES: '1 IT IS FOR UNSELECTED AU.
'2 IT IS FOR THE SELECTED lin.

FUJITSU
1-308

mOON'TCARE

MB85208·12
MBaS208·1S

Timing Diagram.
(Continued)
Read.Wrlte/Read·Modlfy·Wrlte ewel.

lID"

lID"

ADDRESS

w

OUT

IN

rzzl DON'T CARE

NOTES: -1 IT IS FOR UNSELECTED RAJ.
*2 IT IS FOR THE SELECTED RAI.

1·309

MB85208·12
MB85208·15

Timing Diagrams
(Continued)

\'---____--.-Jr

'I THE CASE OF FIRST NIBBLE CYCLE IS EARLY WRITE

Nibble Mode

w

IN

OUT

)

HIGH-Z----------------

r--

EARLY

WRITE~NO OFEN

• (ADD INCREMENT)

WRITE--·
..+I-..---'WRITE--1

~VALIDDATA

\'---____--.-Jr

'2 THE CASE OF FIRST NIBBLE CYCLE IS DELAYED WRITE (READ-WRITE)

w

\'-----~/

\'-----Jr

IN

OUT

-----;*~READ-WRITE-j.--READ~READ-WRITE_.j
mVALIDDATA

FUJITSU
1-310

MBB5208·12
MBB5208·15

TIming Diagrams
(Continued)

Nibble Mode Read Cycle

flU"

V,H
V,L

V,H
V'L

ADDRESS

V'H
VIL

w

V'H
V'Lu..L.L.L.L.L.L.l..f.L.L.L.LJ

VOH _ _ _ _ __

OUT
VOL

IZZJ DON'T CARE

NOTES: ·1 IT IS FOR UNSELECTED RD.
-2 IT IS FOR THE SELECTED RD.

1-311

MB85208.12
MB85208·15

Timing Diagrams
(Continued)

Nibble Mode Write Cycle

RJ(S',

tRRP

1~------------------------tRM----------------------~

!lAS'2

ADDRESS

w

IN

VOH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HIGH,Z _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OUT

VOL

NOTES: 'I IT IS FOR UNSELECTED RAS,
'2 IT IS FOR THE SELECTED RAS,

FUJITSU
1-312

rzn

DON'T CARE

MB85208·12
MBB5208·15

TImIng DIagrams
(Continued) .

NIbble Mode Read·Wrlte Cycle

iiAli"

V,H
V,L

VIH

V,L

AOORESS

w

V,H
V,L

V,H
V,L

;ku...u.U

OUT

IN

NOTES: 'I IT IS FOR UNSELECTED iiAli,
'2 IT IS FOR THE SELECTED lin.

1-313

I'ZZI DON'T CARE

MBaSIOB·tl
MB85208·tS

Tlmln. Dlegrems
(Continued)

RAS·only Refresh ~cle
Note: As = V,H or V,L , W, IN = Dan" care
~-----------------I~------------------~

t-----·1RA.-------t

I00I''

ADDRESS
(AotoA,)

OUT

Y""

-------------H~~-----------

YOL

NOTE: 'I ANY COMBINAnONS OF Iino TO IIn3 ARE ALLOWED AND I0OI's
TO BE NOT REFRESHED ARE IN Y,H-

t72I DON'T CARE

CAS-llefor..RAS Refresh Cycle
Note: Address, W, IN = Don" care

I00I'2

~_I~F
OUT

~:-f---------------HIGH-Z--------------------

NOTE: 'I ANY COMBINAnONS OF Iino TO
TO BE NOT REFRESHED ARE IN Y,H-

IIn3 ARE ALLOWED AND I00I'.

FUJITSU
1-314

F22l DON'T CARE

MB85208·12
MB85208·15

Timing Diagrams
(Continued)

CAS.bator••RB R.fr.sh Count.r T.st Cycl.

Al\ll"
~~~~----------------------t~c----------------~--------~

1---------------- ITA_. ----------------+1

An"

ADDRESS

W(READ)

V,H
V,L

~~~~~~~~~

V,H
V,L

~~~~~~~~WJ

VOH __________
OUT

VOL

IN

V,H
V,L
~~~~~~~~~~~~

m,

NOTES: '1 IT IS FOR UNSELECTED
'2 IT IS FOR THE SELECTED !lAS.

1-315

~DON'TCARE

MB85208-12
MB85208-15

Timing Diagrams
(Continued)

Hlclclen Ref,.ah Cycle

.....
IiJWI

RJiI"

CAS

ADDRESS

W(READ)

V,H
V,L

V..
V,L

V..
V,L

V,H
V,L

VIH
VIL

OUT

W(REAI).
WAITE)

V,H
V,L
LLLLLLLLL.uJ

NOTES: -I IT IS FOR UNSELECTED IIAI.
-2 IT IS FOR THE SELECTED IIAI.

FUJITSU
1·316

rzn

DDN'T CARE

MB85208·f2
MB.5208·f5

Package Dimensions
Dimensions in Inches
(millimeters)

22·LeacI Single In-Line Package Module
(Module No.: MSP.22s.cco3)

,-

,-~~~~=v~~~~~
.300(7.12)TYP

~

f

.020(0.51)

TYP
.031(0.81)
.G44(1.12)

2.1GG(53.34)TYP

1-317

.120(3.05)
.150(3.81)

Preliminary

FUJITSU

MOS Memories
•

MB85210·12, MB85210·15
524,288 x 4-Bit Dynamic
Random Access Memory
SIP Module

Description

The Fujitsu MB85210 is a fully decoded, 524,288 word x 4-bit
NMOS dynamic random access memory module consisting of eight
MB8l257 DRAMs in l8-pad LCC packages mounted on a 24-pin
multilayer ceramic substrate.
The MB85210 is intended for use in memory applications where
large memory capacity is required within limited physical volume.
Significant size reduction can be realized in applications such as
mainframe memory, buffer memory, desk top computers and
peripheral storage.

Features
524,288 x 4 DRAM, 24 pin
~IP (MB81257x8)
• Row acceas time
120 ns max_ (MB85210-12)
150 ns max_ (MB85210-15)
• Cycletlme
230 ne min. (MB85210-12)
280 ns min. (MB85210-15)
• Nibble cycle time
65 ns mln_ (MB85210-12)
80 ns min. (MB85210-15)
• Single + 5V supply,
±10% toleranca
• Low power (active)
1529 mW max. (MB85210-12)
1353 mW max. (MB85210-15)
198 mW max. (standby)
•

• 256/4 ms refresh cycles
~bllity

•
•
•
•
•

RAS-only, CAS-before-RAS
and Hidden refresh
capability
Resd-Modlfy-Wrlta and
Nibble Mode capability
Common I/O capability usIng Early Writa operation
On-chip latch.. for
Addre.... and Data-In
All Inputa and outputa are
TIL compatible

This device contain. circuitry to
protect the inpuls against damage
due to high static voltages or e(ec.
trle fields. However, It Is advised
that normal precautions be taken 10

avoid applicaHon of any voltage
higher than maximum rated volt·
ages to this high impedance circuit.

1-318

-

II

-

-

'-

MB85210·12
M885210·15

MB85210 Block Diagrams
and Pin Assignment

Block Diagram for Each Chip

VSS

As
vee
INO

w

OUTO 5
CAS

6

AT
As

IN

.

As
IN' '0
OUT1 ••

A,
A,
A,

.
.
..

OUT

A,

A,

W

12

A1

13

As
As

.4
.5

OUT2tl

Functional Block Diagram

IN2

17

A2

18

Ao

19

iln.20
IN3

2.

OUT322
Vss

23

iiA§2 24

FUNCTIONAL TRUTH TABLE FOR EACH CHIP
RAS

c:AS

W

IN

OUT

Read

WrHe

Ralreoh

H

H

Don"CJlre

Don't Care

Hlgh-Z

No

No

No

L

L

H

Don't

Valid Data

Yea

No

V..

L

L

L

Valid oata

Hlgh-Z

No

Vaa

Vaa

L

L

L

Valid Data

Valid Data

Vaa

V..

V..

L

H

Don" Care

Don't Care

HIgh-Z

No

No

Vaa

L

L

Don't Care

Don't Care

Valid oata

No

No

Vaa

H

L

Don't Care

Don't Care

Hlgh-Z

No

No

No

care

Note

-

S18ndby

E aJIylweS .. 'WCS (min)
IIotayed _
or _WrIte

ICWO .. ICWD (min)
JiAi.only_

eD-bofore.lIlIlI Ralreoh Valid
_ _ _ 81 previous Raad
or Reall-_ cycle I. held

51_urb

FUNCTIONAL TRUTH TABLE FOR MODULE

IIlIlIl.nd
iiA§2

Not..

c:AS

DIN1
DIN3

WE

to

1Jouy, to

Po...

Function

Don'tC8re

Don't Care

H1gh-Z

L

H

Don't Care

V.lldDatll

R_CycIe

L

L2)

ValldOIlta

HIgh-Z

-Cycle

H

H

L')
L')

-by

L')

L

H -+ L3)

Valid Data

Valid DatIl

RaaIl-WriteCycle

L

H

Don't Care

Don'tCwe

HIgh-Z

1IlI-onIy-

L

L4)

Oon'tCare

Don'tC....

H1gh-Z

1):
2):
3):
4):

It Ie for the selected iaI, and other RAI ia high.
Iwcs~twcs (min).
ICWD"tcwo (min).
IFCS"IFCS (min).

FUJITSU
1-319

5J.beIore-IIU _

MB85210·12
MB8521 0·15

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Voltage on any pin relative to Vss

V 1N' VOUT

-1 to +7

V

Voltage on Vcc supply relative to Vss

Vee

-1 to +7

V

Storage temperature

Tstg

-55 to +150

·C

Power dissipation

Po

Short circuit output current

8.0

W

50

mA

Nota: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the concltlons as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Description
Simple Timing Requirement
The MB85210 has improved circuitry that eases timing requirements for high speed access
operations. The MB85210 can
operate under the condition of
tRco (max) = tCAC thus providing
optimal timing for address muRiplexing. In addition, the MB8521 0
has the minimal hold times of
address (tCAH )' W (tWCH) and IN
(IoH)' Fujitsu has made timing re~ments that are referenced to
non-restrictive and deleted
them from the data sheet. These
include tAR, tWCR ' tOHR and t RWO '
As a.result, the hold times of the
column address, IN and W as
well as tcwo (eAS to W Delay)
are not restricted by t RCO '

Row Address Hold Time (tRAH )
specification has been satisfied
and the address inputs have
been changed from row addresses to column addresses.
W I and RAS2
The MB85210 has RASI and
RAS2 inputs in order to select all
524,288 x 4 locations USi~
eighteen address inputs. RA 1 is
used to select the lower 262,144
x 4 locations and RAS2 is used
to select the upper 252,144 x 4
locations. In the read, del~
write or read-write cycle,
1
and RAS2 must not be low simultaneously in order to avoid data
conflict.

Fast Read-Whlle-Wrlte Cycle
Write Enable

Address Inputs
A total of eighteen binary input
address bits are required to dacode any 4-blts of data in
524,288 locations within the
MB85210. Nine row address bits
are established on the input pins
(Ao through As) and latched with
the Row Address Stro~~1
or RAS2). ~1 and RA 2 are
respectively applied to the lower
262,144 addresses and the upper 262,144 addresses. Nine column address bits are established
on the input pins and latched with
CAS. All input addresses must
be stable on or before the falling
edge of RAS. If the lower
262,144 addresses are used, it is
applied to RASI and if the upper
262,144 addresses are used, It is
applied to RAS2. CAS is internally inhibited~ AilS to permit
triggering of
as soon as the

Dete Outpute
The output buffers of each chip
are three-state TTL compatible
with a fan-out of two standard
TTL loads. OUT Is the same pelarity as IN. The output is in high
impedance state until CAS Is
brought low. In a read or readwrite cycle, the output is valid
after t~rom negative transRion
of the
when t RCO (max) is
satisfied, or after~ from negative transition of A when the
transition occurs after ~max).
Data remain valid until
is returned to a high. In a write cycle,
the identical sequence occurs but
data is not valid.

The read mode or write mode is
selected with the W input. A high
on the W selects read mode, low
selects write mode. Data inputs
are disabled when read mode is
selected.
Dete Inpute
The 4-bit data is written into the
MB85210 during a write or readwr~e cycle. The latter falling edge
of W or ~ Is a strobe for the
IN register. In a write cycle, if W
is brought low before the negative transition of CAS, the set-up
and hold times are referenCed to
CAS. In a delayed wrtte or readwrite cycle, W will be low after
CAS has already gone low. Thus
INO to IN3 are strobed by W, and
set-up and hold times are referenced toW.

1-320

The MB85210 has a fast readwhila-wrtte cycle which is
achieved by precise control of
the three-state output buffer as
well as by the simplified timings
described in the previous section.
The output buffer is controlled by
the state of W when eAS g09l!
low. When W is low during CAS
transition to low, the MB85210
goes into the early write mode in
which the output floats and the
common I/O bus can be used on
the system level. Whereas, when
~oes low after T cwo following
transition to low, the
MB8521 0 goes into the delayed
write mode. The output then contains the data from the cell selected and the data from IN is
written into the cell selected.
Therefore, a very fast read write
cycle (tRC = tRWC ) is possible
with the MB85210.

MB8521 0·12
MB85210·15

Description
(Continued)

Nibble Mode

Refresh

Nibble Mode allows high speed
serial read, write or read-modifywrite access of 2, 3 or 4 bits of
data. The data that will be accessed during nibble mode is determined by the 8 row and 8
column addresses. The 2 addresses (CAs, RAs) are used to
select 1 of 4 nibble bits for initial
access. After the first bit is accessed by normal mode, the following nibble bits can be
accessed by toll9l!!:1g CAS high
then low while RAS remains low.
Toggling CAS causes RAs and
CAs to be incremented internally
while all other address bits are
held constant. This accesses the
next nibble bit in sequence. If
more than 4 bits are accessed
during nibble mode, the address
sequence will begin to repeat. If
any bit is written during nibble
mode, the new data will be read
on any subsequent access. If the
wrije operation is executed again
on subsequent access, the new
data will be written into the selected cells. In the nibble mode,
three-state control of OUT pin is
determined by the first normal
access cycle. The OUT is controlled only by the state of W referenced at negative transition of
CAS on the first nibble bit. That
is, when twes '" twcs (min) is
met, the OUT will remain open
throughout the succeeding nibble
cycle regardless of Wstate.
Whereas, when tCWD '" 'cwo
(min) is met the OUT will contain
the accessed data during the
succeeding nibble cycle regardless of Vii state. The write operation is done during the time Oirn
and iN are low. Therefore, the
write operation can be done bit
by bit during each nibble operation regardless of the timing conditions of Vii (twes and tCWD )
during the first nibble bij.

Refresh of the dynamic memory
cells is accomplished by performing a memory cycle at each of
the 256 row addresses (Ao
through A7) for each chip at least
every 4 ms. During refresh, either
V1L or V1H is permitted for As and
~combinations of RASI and
RAS2 are allowed. When all
chips are refreshed simultaneously, the average power dissipation of the module must be less
than 640 mW at any 100 ms
interval.
The MB85210 offers the following
three types of refresh.
1) RAS-Only Refresh;
RAS-only refresh avoids any
output during refresh because
the output buffer is in hi!l!!.....
impedance state unless CAS
is brought low. Strobing each
of 256 row addresses with
RAS will cause all Ms in each
row to be refreshed. Both
RAS 1 and RAS2 can be refreshed simultaneously under
the specified power dissipationlimit.
2) CAS-before-RAS Refresh;
CAS-before-RAS refresh
available on the MB85210 offers an atternate refresh
method. If CAS is held low for
the s~fied period (tFCS ) before RAS goes low, on chip
refresh control clock generators and the refresh address
counter for each chip are enabled, and an internal refresh
operation takes place. After
the refresh operation has
been executed the refresh address counter Is automat~
incremented for the next CASbefore-'FiAS refresh operation.
3) Hidden Refresh;
Hidden refresh may take
place while maintaining latest
valid data at the output by extending CAS active time. In
MB85210, hidden refresh
means CAS-before-FiAS refresh and the internal refresh
addresses are used, that is,
no external refresh address is
needed. In hidden refresh,
FiASI and RAS2 cannot be
refreshed at the same time
because of data conflict.

FUJITSU
1-321

CA8-before-RAS Refresh
Counter Test Cycle
~ecial

tim.!!!lLsequence using
C:AS-before-RAS counter test
cycle provides a convenient
method of verifying the functionality of ~-before-RAS refresh
activated circuitry. After the CASbefore-RAS refresh operation, if
CAS goes high and then goes
low again while RAS is held low,
the reed and write operations are
enabled. This is shown in the
CAS-bafore-RAS counter test
cycle timing diagram. A memory
cell address (consisting of a row
address (9 bits) and a column
address (9 bits» to be accessed
can be defined as follows:
1) A ROW ADDRESS-Bits Ao
through A7 are defined by the
refresh counter. The other bit
As is set high internally.
2) A COLUMN ADDRESS-All
the bits Ao through As are defined by latching levels on Ao
through As at the second failing edge of CAS.
Suggested CA§.before-RAS
Refresh Counter Teat
Procedure
The timing, as shown in CAS-before-RAS Counter Test Cycle, is
used for all operations described
as follows:
1) Initialize the internal refresh
counter. For this o~tion,
the 8 CAS-before-RAS refresh cycles are required.
2) Write a test pattern of lows
into memory cells at a single
column address and 256 row
addresses.
3) By using read-modify-write
cycle, read the lows written at
the last step and write a new
high in the same cycle. This
cycle is repeated 256 times,
and highs are written into the
256 memory cells.
4) Read the high written at the
last step.
5) Compliment the test pattern
and repeat the steps 2, 3
and 4.

M885210·12
M885210·15

Description
(Continued)

Nibble Mode Address Sequence Example
NIBBLE BIT

RAe

ROW ADDRESS

CAe

COLUMN
ADDRESS

iiAiJCAi (normal m_)

1

0

10101010

0

10101010

toggla 51 (nibble ...-)

2

1

10101010

0

10101010

SEQUENCE

toggle 51 (nibble m_)

3

0

10101010

1

10101010

toggle ClIlr (nibble m_)

4

1

10101010

1

10101010

togaIe ClIlr (nibble mado)

1

0

10101010

0

10101010

Decoupllng and Noise Reduction Recommendations for
MB8521 0
To minimize noise induction between signal lines as well as between signal and power supply
lines, good board design practice
requires consideration of the
following:
1) Provide a capacitor of approx.
a few ,..F for each moduleeven though the MB85210
has two or four decoupling capacitors of 0.15 ,..F on each
module.
2) Remove noise, overshoot and
undershoot from the address,
control and data-input lines,
so that the MB85210 won't
latch wrong signals due to the
noise induction between signal lines, and between signal
and power supply lines.

I

Input_....

goneratad Internally

sequence repeats

nals. Since decoupling capacItors on the module board
can't smooth the output current at the OUT pin, noise Is
introduced on the power supply line (Vce or V ss ) and also
on the IN line at ~Ae or !cAe
in the read cycle.

3) Keep enough timing margin
and remove critical timing in
the board design to avoid the
problem mentioned in Item 2
above.
4) In order to avoid a noise induction on the IN line at the
falling edge of Vii when the
delayed wr~e or read-modifywrite cycle is used, the falling
edge of W signal should nof
coincide with the transition
point of address and OUT sig-

I

5) Provide an appropriate damping if necessary, to avoid excessive overshoot or undershoot on the TTL input
waveform.

MB85210 Derating Curve
AIRFLOW

~
w70

"-

a:

~

a:

~60

:Om/.
:1 m/.

""",

""l"-

- - - - - :3m/s

t'-

~

550

I.

'"40

Recommended Operating
Conditions
(Referenced to Vss)

o

2
3
I/1RC, CYCLE RATE (MHz)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voftage

Vee
Vss

4.5
0

5.0
0

5.5
0

V
V

Input high voltage

VIH

2.4

6.5

V

Input low voltage

VIL

-2.0

0.8

V

Note: *1 Maximum ambient temperature is permissible under certain conditions.

1-322

Operating
Temperature

O·C to

+ 70·C'1

MB85210·12
MB85210·15

Capacitance
(TA = 2S0C)

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Svmbol

Input Capacitance Ao to As

CIN1

Input Capacitance RAS1 and RAS2
Input Capacitance CAS

T,p

Unit

Max
70

pF

CIN2

SO

pF

CIN3

90

pF

Input Capacitance ~

CIN4

60

pF

Input Capacitance DINO to DIN3

CINS

19

pF

Output Capacitance DOUTO to DOUT3

COUT

21

pF

MB85210·12
Min
Max

MB85210·15
Min
Max

Parameter

Symbol

Operating currenf 1
Avera~ower supply current
'2, CAS cycling; tRC = min)
(one

ICCl

278

246

mA

Standby current
Standby power supply current
(RAS1 = RAS2=CAS=VIH)

Icc2

36

36

mA

Refresh current 1'1
Average power supply current
(Cirn = VIH , all RAS cycling; t RC = min)

Icc3

440

400

mA

ICC4

98

90

mA

Iccs

480

440

mA

Unit

Nibble mode currenf 1
Aver~ower sup~urrent

(one
'3 = Vll,
t NC = min)

A

cycling;

8m

Refresh currenf2
Ave~ power

(all RA

cycling,

current
A ·before·RAS)

Input leakage current
Input leakage current, any input
(0 .. VIN .. S.SV, VCC = S.SV, Vss = OV,
all other pins not under test = OV)

II(l)

-80

80

-80

80

Output leakage current
(Data out is disabled,
OV .. VOUT .. S.SV)

IO(l)

-80

80

-80

80

VOH
VOL

2.4

Output levels
Output high voltage (IOH = -S mAl
Output low voltage (Iol = 4.2 mAl
Notes:

0.4

V

a:

:~ mi~fdt:e:::e~n C~~~i~t ~~~n~g
'3

AC Characterlstlcs'l,2,3
(Recommended operating
conditions unless otherwise
noted.)

2.4
0.4

/LA

da~~I~~a~ ~:~~~~~. values are obtained with the output open.

RAS of the selected chip is in VIL and another RAS' is in VIH.

MB85210·12
Min
Max

MB85210·15
Max
Min

Parameter

Symbol

Time between refresh

tREF

Random read/write
cycle time'12

t RC

230

260

ns

Read-write cycle time'12

t RWC

230

260

ns

Notes:

4

4

Unit
rns

·1 An initial pause of 200 IA-S is required after power up. And then several cycles (any 8 cydes to perform refresh are adequate) are
required before proper device operation is achieved. If internal refresh counter is to be effective. a minimum of 8 eAS-before-m
refresh cycles are required.
*2 AC characteristics assume IT = 5 ns.

*3 VIH (min) and VIL (max) are reference levels for measuring liming of input signals. Also. transition times are measured between
VIH (min) and VIL (max).
·12 The minimum cycle lime is dependent on the ambient temperature and cooling conditions.

FUJITSU
1-323

MB85210·12
MB85210·15

AC Characteristics>1,2,3
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

MB85210·12
Max
Min

MB85210·15
Min
Max

Unit

Parameter

Symbol

Access time from RAS>4,6

tRAC

120

150

ns

Access time from CAS>5,6

t CAC

60

75

ns

Output buffer turn off delay

tOFF

0

25

0

30

ns

Transition time

tT

3

50

3

50

ns

RAS precharge time

tRP

100

RAS pulse width

tRAS

120

100000

ns

RAS hold time

tRSH

60

CAS pulse width

tCAS

60

CAS hold time

tCSH

120

RAS to CAS
CAS to RAS

tRco

22

delay time>7,a

100
100000

150

ns

75
100000

75

ns

100000

ns

75

ns

150
60

25

ns

set up time

tCRS

20

20

ns

Row address set up time

tASR

0

ns

Row address hold time

tRAH

0
12

15

ns

Column address set
uptime

t ASC

0

0

ns

Column address hold time

tCAH

20

25

ns

Read command set up time

tRCS

0

0

ns

Read command hold time
referenced to CAS>"

tRCH

0

0

ns

Read command hold time
referenced to RAS>"

tRRH

20

20

ns

Write command set
up time>9

twcs

0

0

ns

Write command hold time

t WCH

20

25

ns

Write command pulse width

twp

20

25

ns

t RWL

50

60

ns

tCWL

30

40

ns

Write command to
lead time

RAS

Write command to
lead time

CAS

Data in set up time

tos

0

0

ns

Data in hold time

tOH

20

25

ns

CAS to W

tcwD

20

25

ns

Notes:

Delay>9

*4 Assumes that tRCD .;;; tRCD (max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will

increase by the amount that tFlCD exceeds the value shown.
*5 Assumes that tACO ~ tRCD (max).
"6 Measured with a load equivalent to 2 TTL loads and 100 pF.
*7 Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if
tACO is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAG'
*8 tACO (min) = tRAH (min) +
(IT = 5 ns) + lASe (min).
·9 twcs and leWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If

2tr

~~fr: ~~~1P16:~,~h~:~(~i~~ t~~ri~~I~t~sc~~~a~~~\~e:~:: ~~~P~~:i~~~:i:i~oO~~~ ~~~~itr!~~~r~:~h~a~~~~~~:~~~t
neither of the above sets of conditions is satisfied the condition of the data out is indeterminate.
*11 Either tRAH or tACH must be satisfied for a read cycle.

1-324

MB85210·12
MB85210·15

AC Characteristics '1,2,3
(Continued)
(Recommended operaling
condilions unless otherwise
noted.)

Parameter

Symbol

MB85210.12
Min
Ma.

MB85210·15
Min
Ma.

Unit

Refresh sel up time for CAS
referenced 10 RAS
(eAS-before-RAS)

I FCS

25

30

ns

Refresh hold lime for eAS
referenced 10 RAS
(eAS-before-RAS)

I FCH

25

30

ns

RAS precharge 10
eAS active lime

IRPC

20

20

ns

Nibble mode read/wrile
cycle lime

INC

65

80

ns

Nibble mode read-wr~e
cycle time

INRWC

65

80

ns

Nibble mode access lime

INCAC

Nibble mode
pulse width

CAS

40

30

ns

INCAS

30

40

ns

Nibble mode CAS
precharge lime

INCP

25

30

ns

Nibble mode read
RAS hold lime

INRRSH

30

40

ns

Nibble mode wrile
RAS hold lime

~WRSH

50

60

ns

Nibble mode e:AS hold
lime referenced 10 RAS

IRNH

20

20

ns

Refresh counler lesl
eAS precharge Iime'10

!cPT

60

70

ns

eAS prechar~me
(eAS-beforecycle)

ICPR

25

30

ns

Refresh counter lesl
cycle lime

IATC

350

405

ns

Refresh counler lest
RAS pulse width

ITRAS

240

295

ns

RAS110 RAS2 precharge
lime

IRRP

0

0

ns

Notes: *10 Test mode write cycle only.

FUJITSU
1-325

M885210·12
M885210·15

Timing Diagrams

Read Cycle

iiAli1, RAS2

V,H
V,L
~-+

__------------t.c-----~----~~

1+---------1.,. ----------;~

CAS

ADDRESS

V,H
V,L

V,H
V,L

W

OUT(O-3)

V,H
V,L

VOH
----------HIGH.Z--------erformi~56 cycles
for CAS-before-RAS refresh.
all bits in a module are
refreshed.

MB85214·12
MB8521",15

Description
(Continued)

3. Hidden Refresh;
Hidden refresh may take
place while maintaining latest
valid data at the output by extending CAS active time. In
the MB85214, hidden refresh
means CAS-before-RAS refresh and the internal refresh
addresses are used, that is,
no external refresh address is
needed.

MB85214 Derating Curve
(Normal Cycle)

Decoupling and Noise
Reduction Reocmmendatlons
for MN85214

!

AIRFLOW

w70

I\.

II:

~~60

,

"

\. "

~

La

- - - :Omi.

...~OT ALLOWABLE - - - :1 mi.

----- :3mi.

"

.,

r--

'\

ALLOWABLE

,

'\.
i'

c

.... 40

To minimize noise induction between signal lines as well as between signal and power supply
lines, good board design practice
requires consideration of the
following:
1. Provide a capacitor for approx. a few /LF for each module, though the MB85214 has
four decoupling capacitors of
0.15/LF on the each modules.
2. Remove noise, overshoot and
undershoot from the address,
control and DO lines, so that
the MB85214 won't latch
wrong signals due to the
noise induction between signal lines, and between signal
and power supply lines.
3. Keep enough timing margin
and remove critical timing in
the board design, to avoid the
problem mentioned in the
above item 2.
4. Provide an appropriate damping if necessary, to avoid excessive overshoot or
undershoot on the TIL input
waveforms.

Recommended Operating
Conditions
(Referenced to Vss)

e

a

2

3

11tRe, CYCLE RATE (MHz)

MB85214 Derating Curve
(Page Mode Cycle)
U"

Airflow

NOT ALLOWABLE

'-70
w

" 1"-

~

r

II:

o

-"

-

~

---:1mi8
-----: 3 mil

"

I'-...

'"

ALLOWABLE

ffiiii 50

--:Omi.

~

~ 40

a

4

6

1/tpe, CYCLE RATE (MHz)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee
Vss

4.5
0

5.0
0

5.5
0

V
V

Input high voltage

V 1H

2.4

6.5

V

Input low voltage

V1L

-2.0

0.8

V

otterelln,
Te=eerature

O"C to

+ 7O"C'1

Note: "1 Maximum ambient temperature is permissible under certain conditions. See the derating curves for normal cycle and page
mode cycle.

FUJITSU
1-370

MB85214·12
MB85214·15

Capacitance
(TA = 25'C)

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Max

Unit

Input capacitance Ao to As

G'N'

70

pF

Input capacitance RAS, GAS, W

G'N2

90

pF

Input capacitance IN

G'N3

t7

pF

Output capacitance OUT

GOUT

17

pF

Parameter

Typ

Symbol

Operating currenf'
Averag~ower supply current
(RAS, GAS cycling; t RC = min.)

Min

MBS52t4-12
MBS5214-15

Standby current
Standby power supply current
(RAS = GAS = V'H)

=

min.)

MBS5214-15

Page mode currenf'
Average power supply current
(RAS = V'L, GAS cycling; tpc

=

min.)

MBS5214-15

Icc,

456
36

MBS5214-12

400
240

--

ICC4

mA

mA

mA

200

MBS5214-12
MBS5214-15

mA

440
ICC3

MBS5214-12

Refresh current 2"'
Average power supply current
(CAS-before-RAS; t RC = min.)

Unit

520

ICC2

Refresh current 1"
Average powe~ply current
(RAS cycling, GAS = V'H; t RC

Max

4S0
Iccs

440

mA

Input leakage current
Input leakage current, any input
(0 '" V'N '" 5.5V,
Vcc = 5.5V, Vss = OV,
all other pins not under test = OV)

I'lL)

-SO

80

p,A

Output leakage current
(Data out is disabled,
OV", VOUT '" 5.5V)

lOlL)

-10

10

p,A

Output levels
Output high voltage (loH = -5 mAl
Output low voltage (lOL = 4.2 mAl

VOH
VOL

2.4

0.4

V

Note: *1 ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

AC Characteristics"'·2.3
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Time between refresh

tREF

Random read/write cycle time"4

t RC

Access time from RAS"s.s

tRAC

Notes:: *1

MB85214·12
Min
Max

MB85214·15
Min
Max

4
230

4
260

120

Unit
ms
ns

150

ns

;:

~ni~~::~~i~e~~:s~f c2o~~te~ ;~~~r:~e:~~~~V:i~:~:I~~eg~~_:ro~e~~S~e~~!~~e :;~~:ra~:~~:u~~~ation is achieved.

'2 AC characteristics assume IT 5 ns.
*3 VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between
VIH (min.) and VIL (max.).
*4 The minimum cycle time is dependent on the ambient temperature and cooling conditions. See the Normal Cycle derating curve.
*5 Assumes that tRCD ",;; tACO (max.). If tACO is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown.
*6 Measured with a load equivalent of 2 TTL loads and 100 pF.

1·371

MB85214-12
MB85214·15

AC Chlll'acteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

MB85214·12
Min
Max

MB85214-15
Min
Max

60

75

Unit

Access time from CAS"S,7

tCAC

Output buffer turn off delay

tOFF

0

25

0

30

ns

Transition time

tT

3

50

3

50

ns

tRP
tRAS

100
120

100000

100
150

100000

ns

tRSH

60

~S

60

tCSH

120

tRCo

22
20

RAS precharge time
RAS pulse width
RAS hold time
CAS pulse width
CAS hold time
RAS to CAS delay time"B,g

ns

75
100000

75

ns

100000

150
60

25
20

ns

ns
ns

75

ns

CAS to RAS set up time

t CRS

Row address set up time

t ASR

0

0

ns

Row address hold time

tRAH

12

15

ns

Column address set up time

tASC

0

0

ns

Column address hold time

tCAH

20

25

ns

Read command set up time

t RCS

0

0

ns

Read command hold time
referenced to CAS"10

tRCH

0

0

ns

Read command hold time
referenced to RAS"10

tRRH

20

20

ns

ns

Write command set up time

twcs

0

0

ns

Write command pulse width

twp

20

25

ns

Write command hold time

t WCH

20

25

ns

Data in set up ti me

tos

0

0

ns

Data in hold time

toH

20

25

ns

Refresh set up time for CAS
referenced to RAS (CAS-before-RAS-cycle)

tFCS

25

30

ns

Refresh hold time for CAS
referenced to RAS (eAS-before-RAS-cycle)

t FCH

25

30

ns
ns

RAS precharge to CAS active time
(refresh cycle)

tRPC

20

20

Page mode read/write cycle time"11

tpc

120

150

ns

Page mode CAS precharge time

tcp

50

65

ns

CAS precharge time (CAS-before-RAS cycle)

t CPR

25

30

ns

Nates:

·7 Assumes that tRCD ~ tACO (max).
*8 Operation within the tRCD (max) limit insures that tRAC (max) can be met. tACO (max) is specified as a reference point only; if
tRCD is greater than the specified tACO (max) limit, then access time is controlled exclusively by tCAe .

•;~

~~~r ~m~~ ~:~~~H(:~~tbe~!~~ ~o~S! ~!~s~j:,ln).

*11 The ml~mum cycle time is dependent on the ambient temperature and cooling conditions,
See the Page Mode Cycle derating curve.

FUJITSU

1-372

M885214·12
M885214·15

Timing Diagrams
Read Cycle
~----------------------'OC----------~--------"

1----------------.OA5 -------------~~
An

en

ADDRESS

V,.
V,L

V,.
V,L

V,.
V,L

W

V,.
V,L

tRAC

DOoTHRU
Do-, (OUT)

VO.
HIGK-Z

VOL

VALID
DATA

rzzI DON'T CARE

1-373

MB85214-12
MB85214-15

Timing Diagrams
(Continued)

Write Cycle (Early Write)
~

____________________

t~

______________________

~~

~---------------t"AS--------------~

lin

i:l!I

ADDRESS

W

V,H
V,L

V,H
V,L

V,H
V,L

V,H
V,L

DOoTHRU
DOr(IN)

rzzJ DON'T CARE

FUJITSU

1-374

MB85214·12
MB85214·15

Timing Diagrams
(Continued)

Page Mode Read Cycle
tRAS

!WI

V,H
V,L

cxs

ADDRESS

V,H
V,L

V,H
V,L

DOoTHRU
00, (OUTJ

VOH
VOL

W

[ZZ) DON'T CARE

Klm VALID DATA

I------------------t".s----------------~---tr_

I'---------;-----------T)~,'~SH~t"P=t_

rzzJ DON'T CARE

1·375

MB85214·12
MB85214·15

Timing Diagrams
(Continued)

RAS·only Refr.sh Cycl.
Note: Vii = Don'l Care
~---------I"C---------+t
~---I"A.----+1

ADDRESS

DOoTHRU

VOH

(oun

VOL

DO,

----------HGH-z----------

E72I DON'T CARE
CAS·befor..RAS Refr.sh Cycle
Nole: Address W = Don'l Care

VOH,;ll_IOFF
=T~~ V~&5f-------------HIGH-Z:---------------

I'Z2l DON'T CARE

FWITSU
1-376

MB85214-12
MB85214-15

Timing Diagrams
(Continued)

Hidden Refresh Cycle

I-------.RC-------I

ADDRESS

w

~l~~

~::'----- HIGH-Z - - - - - - { I

VALID
DATA

~DON·TCARE

1-377

MB85214-12
MB85214·15

Package Dimensions
Dimensions in inches
(millimeters)

24·L_d Single In·Line Package Module
(Module No.: M....24s-cc02)

I-

1

"I

2.35(58.69)
2A5(62.23)

I~

EPDq~IDq~ rm

.03~
TYP

rrITrrITITwrrITrrIT
I...

090(2.29)
.110(2.79)

t

-..J

ITITJI-HHH 1

.015(0.38) _
.023(0.58)

2.300(58A2)REF

1·378

.038(0.91)
.044(1.12)

.120(3.05)
.150(3.81)

MAX

~

Preliminary

FUJITSU

MOS Memories
•

MB85227.12, MB85227·15
262,144 x 9-Bit
Dynamic Random Access
Memory Module

Description
The Fujitsu MB85227 is a fully decoded, 262,144 word x 9-bit
NMOS dynamic random access memory module consisting of nine
MB81256 DRAMs in 18-lead plastic LCC packages mounted on a
300pin Single-In Une Package (SIP).
The MB85227 is intended for use in memory applications utilizing
parity where large memory capacity is requirad within limited physical volume. Significant size reduction can be realized in applications such as mainframe memory, buffer memory, desk top
computers and peripheral storage.

~

II

tt-

lIt-

~""

F••tures
• 282,144 x 9 DRAM 300pln SIP
(MB81256 x 9)
• Row acesss time
120 ns max. (MB85227-12)
150 ns max. (MB85227-15)
• Cycle time
230 ns min. (MB85227-12)
280 ns min. (MB85227-15)
• Page cycle time
120 ns min. (MB85227-12)
150 ns min. (MB85227-15)
• Single + 5V supply,
±IO%toleranca
• Low power (active)
3218 mW max. (MB85227-12)
2822 mW max. (MB85227-15)
228 mW max. (Standby)

rr'f'

• 4 ms 258 ~ refresh

• ~nly, CAS-bafore-RAS

and Hidden refresh capability
• Page mode capability
• On-chip latches for Addressea
and Data-In
• Allinputa and outputs are
TTL compatible
• (D., Qalls generally used
for parity and Is controlled
by CU.

t-

tt- t-

t-

I-

tD. 11M

This device contains circuitry to
protect the Inputs against damage
due to high static voltages or alechie fieldS. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high impedance circuH.

1-379

MB85227.12
MB85227.15

MB85227 Block Diagrams
and Pin Assignment

o

Block Diagram For Each Chip
Vee

CAS

w

DO,
A,
A,
DO,
A,
A.

Vss

Ao

DO,
A,
As
DO.
A.
A7
DO,

A,

A.

A,

NC
NC
DOs

0

A.

0

Ao

W

As
A.
A7
A.

DOs

VSS

HC

oar
9i

RAS
CASa'

Da'
Vee

D

D
D

D

D
D
D
D
Do

*; For parity btt.

Functional Block Diagram

FUNCTIONAL TRUTH TABLE

WE

DOo'ooar.

H

Don'C8re

HIg/IoZ

L

L

H

Valid Dolo OUt')

RooclyCycIe

L

L

L

Valid Dolo 102)

W~"CycIe

Don'eore
Don,eore

HlgII-Z

m
H

llliIond
~

L

La)

L

H

L

H~
L(~

H_L4)

Not.. 1): DQ Plnl are output mode.
2): DO pi.. are Input mode.
3): 'FCS"'FCS (min).
4): tcwD"IcwD(mln).

FUJI"I'SU
1-380

FuncUon

D,andOo

Standby

exJ.before IIU R_h cycle

Hlgh.z

~Iy llelrelh cycle

HIgh-Z (000'0 oar)
Valid Dota In (Da>
Valid Dolo OUt (Oa>

JiliI.onty R_h "",Ie
(Except lor Parity bII)
R_WrIte/R_ModIfy'W~

(ParIty bII)

MB85227·12
MB85227·15

Absolute Maximum Ratings
(See Note)

Rating

Szmbol

Value

Unit

Voltage on any pin relative to Vss

V1N,VOUT

-1 to +7

V

Voltage on VCC supply relative to Vss

VCC

-1 to +7

V

Storage temperature

TSTG

-55 to 125

'C

Power dissipation

PD

Short circuit output current

4.5

W

50

mA

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Description
Simple Timing Requirement

Write Enable

Page-Mode

The MB85227 has improved circuitry that eases timing requirements for high speed access
operations. The MB85227 can
operate under the condition of
tRCO (max.) = !cAC' thus providing optimal timing for address
muHiplexing. In addition, the
MB85227 has minimal hold times
of address (tCAH)' W (tWCH) and
D (toH)' Fujitsu has made timing
re~ments that are referenced
to RAS non-restrictive and deleted them from the data sheet.
These include tAR' t WCR ' and
tOHR ' As a result, the hold times
of the column address. D and W
are not restricted by t RCD '

The read mode or write mode is
selected with the W input. A logic
"high" on the W dictates read
mode. A logic "low" dictates write
mode. Data inputs are disabled
when read mode is selected.

Page-mode operation permits
strobing the row-address into the
MB85227 while maintaining RAS
at a logic low throughout all successive memory operations in
which the row-address doesn't
change. Thus the power dissipated by the falling edge of RAS
is saved. Access and cycle times
are decreased because the time
normally required to strobe a new
row address is eliminated.

Address Inputs
A total of eighteen binary input
address bits are required to decode any 9-bits of data in
2359296 storage cells within the
MB85227.

Data Pins
The input and output pins of each
PLCC except for parity bit are directly connected on the mother
board to minimize the number of
I/O pins. The write cycle should
be early write cycle in order to
avoid data conflict between output data and input data. However, it is possible to execute
read-modlfy-write cycle on the
parity bit because the input and
output of parity bit are separated.

Refresh
Refresh of the dynamic memory
cells is accomplished by performing a memory cycle at each of
256 row addresses (Ao through
A7) at least every 4 ms. During
refresh, either V1L or V1H is permitted for As.

Data Input
The 9-bit data are written through
the DO pins (DOD to D07 and Ds)
during write (early write) cycle.

Nine row address bits are
established on the input pins
(AD through As) and latched
with RAS.

The falling edge of CAS is triggered by the data input register.
The set up and hold times are
referenced to CAS.

Nine column address bits are established on the input pins and
latched with CAS. All input addresses must be stable on or before the falling edge of RAS. 'CAS
is internally inhibited by RAS to
permit triggering of CAS as soon
as the Row Address Hold Time
(tRAH ) specification has been satisfied and the address inputs
have been changed from row addresses to column addresses.

Data Output
The output buffer of each chip
is three-state TIL compatible
with a fan out of two standard
TIL loads.
The outputs are in high impedance state until CAS is brought
low. In a read cycle, the output is
valid after tRAC from the transition
of RAS when tRCO (max.) is satisfied, or after tCAC from the transition of CAS when the transition
occurs after t RCD (max.). Data remain valid until ~ is returned
to high.

1-381

The MB85227 offers the following
three types of refresh.
1) RAS-Only Refresh;
RAS-Only refresh avoids any
output during refresh because
the output buffer is in high
impedance state unless CAS
is brought low. Strobing each
of 256 row addresses with
RAS will cause all bits in each
row to be refreshed.
2) 'CAS-before-RAS Refresh;
CAS-before-RAS refresh
available on the MB85227 offers an alternate refresh
method. If CAS is held "low"
for the specified period (tFCS )
before RAS goes "low'; on
chip refresh control clock generators and the refresh address counter for each chip
are enabled, and an internal
refresh operation takes place.

MB85227·12
MB85227·15

Description
(continued)

After the refresh operation
has been executed the reo
fresh address counter is auto·
matically incremented in
preparation for the next CAS·
before·RAS refresh operation.
So,.!!l.Performi~6 cycles
for CAS-before-RAS refresh,
all bits in a module are
refreshed.
3) Hidden Refresh;
Hidden refresh may take
pla~ while maintaining latest
valid data at the output by extending CAS active time. For
the MB85227 a hidden refresh
cycle is a CAS-before-RAS
refresh cycle and the internal
refresh addresses are used.
No external refresh address is
needed.

MB85227 Derating Curve
Normal Cycle
A.R FLOW

~
w 70

I\.

"~
" 60

i

"

"

"

,0 mi.
:1 mls

"

------ :3 mI.

1',

"

"

ALLOWABLE \

leo
~40

NOT ALLOWABLE

,

1\

,
[\

o

2

3

II'RC, CYCLE RATE (MHz)

MB85227 Derating Curve
Page Mode Cycle

":lOT ALLOWABLE

Decoupllng and Noise
Reduction Recommendations

t'---

for MB85227

To minimize noise induction between signal lines as well as between Signal and power supply
lines, good board design practice
requires consideration of the
following:
1. Provide a capac~or of approximately a few p,F for each
module, even though the
MBB5227 has the decoupling
capacitors of 0.15 p,F on each
module. (0.22 p.F x 9)
2. Remove noise, overshoot and
undershoot from the address,
control and DO lines, so that
the MB85227 will not latch
spurious signals due to the
noise induction between signel lines and between signal
and power supply lines.
3. Keep enough timing margin
and remove critical timing in
the board deSign, to avoid the
problem mentioned in the
above item 2.
4. Provide an appropriate damping if necessary, to avoid excessive overshoot or
undershoot on the TIL input
waveforms.

FUJITSU
1-382

-

-,

"',,-

-,

f".ALLOWABLE
AIR FLOW
:Om/.

- - - : 1 mI.

----- :3m/a

II'ec, CYCLE RATE (MHz)

MB85227·12
MB85227.15

Recommended Operating
Conditions
(Referenced to V ss)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee
Vss

4.5
0

5.0
0

5.5
0

V
V

Input high voltage

V,H

2.4

6.5

V

Input low voltage

V,L

-2.0

O.B

V

Operating
Temperature

O·C to + 70·C"

Note: "1 Maximum ambient temperature is permissible under certain conditions. See the derating curves for normal cycle and for
page mode cycle.

Capacitance
(TA = 25·C, f = 1MHz)

Parameter

Typ

Max

Unit

C ,N ,

Symbol

75

pF

Input capacitance, RAS

C'N2

BO

pF

Input capacitance, CAS

C 'N3

70

pF

Input capacitance, W

C'N4

55

pF

Input capacitance, CASs

C'N5

10

pF

Input capacitance, Os

C'N6

7

pF

1/0 capacitance, 000 to 00 7

C,o

17

pF

Output capacitance, as

Co

12

pF

Input capacitance, ~ to

As

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Operating current"'
averag~wer ~upply curre~t

(FiAS,

cycling; t RC

=

MBB5227-15

min.)

Standby current
standby power supply current
CAS = V,H)

Refresh current 1"
average p.owe~PIY current
(RAS cycling, C = V ,H ; tRC

=

Icc,

513
41

Page mode current"'
average power supply current
(RAS = V,L, CAS cycling; !Pc

= min.)

MBB5227-12
.
min.)

MBB5227-15

495
Icea

450

MBB5227-12

Refresh current 2"
average power supply current
(CAS-before-RAS; tRC = min.)

MBB5227-15

270
1CC4

225

MBB5227-12
MBB5227-15

Max
5B5

ICC2

(FiAS =

Input leakage current
(except for 000 - 007)
input leakage current,
any input (0 .. V,N .. 5.5V,
Vcc = 5.5V. Vss = OV,
all other pins not under test

Min

MBB5227-12

540
1CC5

I'(L)' (CASs. Del

495

-10

Unit
mA

mA

mA

mA

mA

10

- -90
90

p.A

1'(L)2 (others)

DO and as leakage current
(data out is disabled. OV .. VOLrr .. 5.5V)
each DO is high impedance

IO(L)

-10

p.A

Output levels
output high voltage (IOH = -5 mAl
output low voltage (lOL = 4.2 mAl

VOH
VOL

2.4

= OV)

Note: *1 ICC is dependent on output Ioacfing and cycle rates. Specified values are obtained wtth the output open.

1-383

10

0.4

V

MB85227·12
MB85227.15

AC Characteristics"1 ,2,3
(Recommended operating
conditions unless otherwise
noted,)

Parameter

Symbol

Time between refresh

tREF

Random read/write cycle time"4

t RC

Access time from RAS"5,S

tRAC

MB85227·12
Min
Max

MB85227·15
Min
Max

4

230

ms

150

ns

260
120

Unit

4

ns

Access time from CAS"S,7

tCAC

ns

tOFF

0

60
25

75

Output buffer turn off delay

0

30

ns

Transition time

tT

3

50

3

50

ns

RAS precharge time

tRP

100

RAS pulse width

t RAS

120

FiAS hold time

tRSH

60

CAS pulse width

leAS

60

CAS hold time

tCSH

120

RAS to CAS delay time"B,g

tRCO

22

CAS to RAS set up time

tCRs

20

20

ns

Row address set up time

tASR
tRAH

0
12

0
15

ns

Row address hold time
Column address set up time

tASC

0

0

ns

Column address hold time

tCAH

20

25

ns

Read command set up time

t RCS

0

0

ns

Read command hold time
referenced to CAS"10

t RCH

0

0

ns

Read command hold time
referenced to FiAS"10

tRRH

20

20

ns

100

ns

100000

150

100000

ns

100000

75
75

100000

ns

60

25

ns

150

ns

75

ns

ns

Write command set up time

twcs

0

0

ns

Write command pulse width

twp

20

25

ns
ns

Write command hold time

tWCH

20

25

Data in set up time

tos

0

0

ns

Data in hold time

tOH

20

25

ns

Refresh set up time for CAS
referenced to RAS
(CAS-before-RAS-cycle)

tFCS

25

30

ns

Refresh hold time for CAS
referenced to RAS
(CAS-before-'RAEl-cycle)

t FCH

25

30

ns

Notes:

*1

~~I i::s':,a~~~nf~?sOt~Sb~ ~~r::,a:~i~:~~~'~O~:~e~r:~~~~:!e:~~!::rr=~:~~~peration is achieved. If inter-

*2 AC characteristics assume tr = 5 ns.
*3 VIH (min.) and VIL (max.) are reference levels for measuring timing
VIH (min.) and VIL (max.).

of input signals. Also, transition times are measured between

*4 The minimum cycle time is dependent on the ambient temperature and cooling conditions. See Normal Cycle Diagram for
derating curve.
*5 ~:~e:/~:! ~~o~n~ t~~?~~~~~1R~~~':~~o:~ the maximum recommended value shown in this table, tRAC will in*6 Measured with a load equivalent to 2 TTL loads and 100 pF.
"7 Assumes that tRCD i;;o tRCO (max.).
"8 Operatlon within the tRCD (max.) limit insures that tRAC (max.) can be met. tACO (max.) is specified as a reference point only; if
tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC'

"g 'RCO (min.)

~1RAH (min.)

+ 2tr ('T ~ 5 ns) + 'ASC (min.).

*10 Either tRRH or tRCH must be satisfied for a read cycle.

PUJITSU

1·384

MB85227·12
MB85227·15

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Parameter
RAS precharge to CAS active time
(refresh cycle)

Symbol

MB85227·12
Min
Max

MB85227·15
Min
Max

Unit

tAPC

20

20

ns
ns

Page mode read/write cycle time' 11

tpc

120

150

Page mode CAS precharge time

tcp

50

65

ns

CAS precharge time (eAS-before-RAS cycle)

tCPA

25

30

ns

Write command to RAS lead time'12

t AwL

50

60

ns

Write command to CAS lead time'12

tCWL

50

60

ns

CAS to W delay time'12

tCWD

20

25

ns

Read-write cycle time'12

t AWC

230

260

ns

Notes: *11 The minimum cycle time is dependent on the ambient temperature and cooling conditions. See Fig. 4 for derating curve.
*12 Only for parity bit.

Timing Diagrams
Read Cycle
~------------------------tRC--------------------~~
~----------------tRAS

RlIS

CAS

ADDRESS

-----------------;»1

V,H

v"

V,H
V,L

V,H
V,L

W

V,H
V,L

DOo TO DO, VOH
-------------HIGH·z--------{1
ANDQ8
VOL
(OUTPUT)

VALID
DATA

rzzJ

1-385

DON'T CARE

MB85227·12
MB85227·15

Timing Diagrams
(Continued)

Write Cycle (Early Wrltel

'RC
tRAS

IllS

VOH
VOL
tCSH

'4----tRP
tASH

leAS

CH

ADDRESS

VOH
VOL

VOH
VOL

IV

VOH
VOL

rzzJ DON'T CARE

FUJITSU

1-386

MB85227·12
MB85227·15

Timing Diagrams
(Continued)

Page Mode Read Cycle

t-------------------tAAs------------------+j
lin

V'H
V'L

ell

V'H
VIL

ADDRESS

V'H
VIL

VOH

:r.~ 00, V O L - - - - - - - + - (OUTPUT)

w

[ZZ] DON'T CARE

lXXI VALID DATA

1-387

M885227·12
M885227·15

Timing Diagrams
(Continued)

Page Mode Write Cycle

ADDRESS

000 TO DO,
AND

De

(INPUT)

m

FUJITSU
1-388

OON'T CARE

MB85227·12
MB85227·15

Timing Diagrams
(Continued)

RAS.Only Refresh Cycle
Note: W= Don't Care, As = VIH or VIL
~---------t"C,----------t
~---t"AS'-----+I

ADDRESS

(A. 10 A71

--------------------HIGH~--------------------

E'Z2l DON'T CARE
CAS·Before-RAS Refresh Cycle
Note: Address, W = Don't Care

'Fes

~

_'OFF

~~

i:! DOt : :

(OUTPUll

-------------------------- HIGH-Z:----------------------------

IZ2l DON'T CARE

1-389

MB85227-12
MB85227-15

Timing Diagrams
(Continued)

Hidden Refresh Cycle
\.-------tAC-------~

ADDRESS

w

000 TO D

;
l-

0

I

~"":

I

.007(0.lB)
.010(0.25)

2-21

.132(3.35)
.140(3.55)
.060(1.52) MIN.

FUJITSU

MOS Memories
•

MB81C466-10, MB81C466-12, MB81C466-15
65,536 x 4 Static Column
CMOS Dynamic Random
Access Memory

Description
The MB81C466 is a 262,144-bit (configured as 65,536 x 4-bits)
CMOS Static Column Dynamic Random Access Memory
(SC DRAM). The design is optimized for high speed, high performance applications, such as mainframe memory, buffer memory,
graphics terminals, video RAM, and peripheral storage devices
where high speed access, very low power dissipation, compact layout and low cost are required.
The SC DRAM features a static mode of operation in which very
fast random access within the same row is performed by changing
the column address. The advantage of using the SC DRAM Is to
achieve the fast read or write operation of the static mode by using
dynamic memory.
The MB81C466 has fully TTL compatible inputs and outputs. It operates on a single + 5V ± 10% power supply. An on-chip substrate
bias generator provides high performance operation. The
SC DRAM contains on-chip address input and data input latches.
The MB81C466 is fabricated using Fujitsu's silicon gate CMOS and
Fujitsu advanced triple-layer polysilicon process which decreases
power dissipation, and can easily be used in battery (backed-up)
systems such as hand held computers.
Features
• 65,536 x 4 SC DRAM,
18-pin package
• Silicon-gate, CMOS, Single
transistor cell
• Row access time
100 ns max_ (MB81C466-10)
120 ns max. (MB81C466-12)
150 ns max_ (MB81C466-15)
• Address access time
45 ns max_ (MB81C466-10)
55 ns max, (MB81C466-12)
70 ns max_ (MB81C466-151
• Random CYCle time
200 ns min. (MB81C466-10)
230 ns min. (MB81C466-12)
260 ns min. (MB81C466-15)
• Static cr.cle time
50 ns m n. \MISII11,;1MI1I-10)
60 n8 min. (MB81C466-12)
75 ns min. (MB81C466-15)

•

•
•
•
•
•
•
•
•

Single +5V supply,
±10% tolerance
Low power, (Active)
385 mW max. (MB81C466-10)
330 mW max. (MB81C466-12)
275 mW max. (MB81C466-15)
11 mW max. (Standby with TTL
level Input)
1.1 mW max. (Standby with,
CMOS elinput)
4 ms/256 refresh cycles
On chip substrate bias
Static Mode Boundary
258 x 4-Blt/P~
Common I/O (CE Control)
Fast eA!I Control
Edge triggered write operation
Internal wr~erfod control
RAS-only, CAS-before RA§ refresh capability

2-22

MB81C466-10
MB81C466-12
MB81C466-15

MB81C466 Block Diagram
and Pin Assignment

RAS---_oo-l

iii
Vss
DQ,

DO.

CAS
DQ,

CAS

!!Ali

Ao

"-

A,

As

A,

AO

~

A,

Vee

LEAD
NQ,

LEAD
NO.2

...---- Vee

DQ3

oa.. 6E

CA

Vsa

RAi

DO,

00,

Ne

.

NC

W

"

A,

20

BOTTOM VIEW

~Vss

Absolute Maximum Ratings
Ratlng8

Symbol

Value

Unit

Voltage on any pin relative to Vss

VIN, VOUT, Vee

-1.0107.0

V

TSTG

-55 to +155
-55 to +125

·C

1.0

W

50

mA

Storage Temperature

Ceramic
Plastic

Power Dissipation

Po

Short circuit output current

Recommended Operating
Conditions
(Referenced to Vss )

Paramater

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee
Vss

4.5
0

5.0
0

5.5
0

V

Input high voltage, all inputs

VIH

2.4

6.5

V

Input low voltage, all inputs

¥Il

-1.0

0.8

¥

Symbol

Typ

Operating
Temperature

O·C to +70"C

Capacitance
(TA = 25"C, f = 1 MHz)
Parameter
Input capacitance,

An to A7

Input capacitance, RAS, CAS, W,

m:

Input/output capacitance, DO, - D04

FUJITSU

2-23

Max

Unit

CIN ,

7

pF

C IN2

10

pF

CIO

7

pF

MB81C488-10
MB81C486-12
MB81C488-15

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Symbol Min

Parameter
Operating currenf 1
averagMSwer supply current
(RAS, C cycling, tRC = min)

Max Unit
70

MB81C466-10
MB81C466-12
MB81C466-15

s0-

ICC1

TTL level RAS = co;s = VIH

Standby current
power supply current

CMOS level

RAS = CAS =

mA

~
2

Vcc ± 0.2V

ICC2

--rnA
0.3

s0-

Static mode
operating current'1
~ge ~er supplWcurrent
(RAS = AS = V IL ,
or
address cycling; tsc = min)

MB81C466-10
MB81C466-12
MB81C466-15

ICC3

Refresh current
average power supply current
(CAS-before-RAS; tRC = min)

MB81C466-10
MB81C466-12
MB81C466-15

ICC4

70

mA

50

~
~ rnA
45

Input leakage current
input leakage current, any input
(Vcc = 5.5V, Vss = OV,
OV .. VIN .. 5.5V
all other pins not under test = ov)

IIIL)

-10

10

p.A

Output leakage current
(data out is disabled,
OV .. VOUT .. 5.5V)

lOlL)

-10

10

p.A

Output levels
output high voltage
(IOH = -5 rnA)
output low voltage
(IOL = 4.2 rnA)

V OH

2.4

V
0.4

VOL

Note: *1 ICC is dependent on output loading and cycle rates. The specified values are obtained with the output open.

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.),1,2

Parameter

Symbol

MB81C468-10
Min
Max

MB81C466-12
Min
Max

MB81C466-15
Min
Max

Unit

Time between refresh

tAEF

Random read/write cycle time

tAC

200

230

260

Read-modify-write cycle time

tAWC

270

315

360

Access time from Jtl(S"3,5

tAAC

Access time from ~'S

tCAC

25

Output buffer turn off delay time

'oFF

0

25

0

25

Transition time

tT

3

50

3

50

Column address access tlme'4,S

tAA

Output hold time from column
address change

tAOH

Access time from W precharge

twPA

30

35

45

ns

Access time relative to last write '6

tALW

90

110

140

ns

Notes:

4

4

100

45

5

4

ms
ns
ns

120

150

ns

30

35

ns

0

30

ns

3

70

ns

55

ns

55

5

5

ns

*1 An Initial pause (RAS = CAS = V,H) of 200 /Ls Is required after power-up, followed by any 8 RAS-only ~s, before proper device operation is achieved. If the internal refresh counter is to be effective, a minimum of 8 CAS-before-RAS initialization cycles
are required.
*2 AC characteristics assume IT = 5 ns, VIN = OV to 3V, VIH = 2.4V, VIL = O.8V, VOH = 2.4V, and VOL = O.4V.
*3 Assumes that tRAD ;a. tRAD (max). If tRAD is greater than the maximum recommended value then tRAC is increased by the
amount that IRAD exceeds tRAD (max).
*4 Assumes thailRAD $I> tRAD (max).
*5 Measured with a load equivalent to 2 TIL loads and 100 pF.
*6 Assumes that ILWAD .., tLWAD (max). If tLWAD is greater than the maximum recommended value then tALW is increased by the
amount that ILwt\D exceeds tLWAD (max).

2-24

MB81C486-10
MB81C466-12
MB81C466-15

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
notedr 1,2

Parameter

Symbol

MB81C466-10
Min
Max

MB81C466-12
Min
Max

MB81C466-15
Min
Max

Unit

RAS precharge time

tRP

90

100

100

ns

RAS pulse width

tRAS

65

RAS hold time (read)

tRSH

25

30

35

ns

<::AS pulse width (read)

tCAS

25

100000 30

100000 35

100000 ns

~ pulse width (write)

tCAS

15

100000 20

100000 25

100000 ns

~ hold time (read)

tcSH

100

120

150

ns

<::AS hold time (write)

tCSH

80

95

115

ns

RAS to ~ delay time

tRCD

25

~ to RAS set up time

tCRS

20

25

30

Row address set up time

tASR

0

0

0

ns

Row address hold time

tRAH

15

15

20

ns

Column address set up time '7

tASC

0

0

0

ns

Column address hold time'7

tCAH

15

15

20

RAS to column address delay
time'8,9

tRAD

20

Column address hold time
referenced to RAS

tAR

100000 75

75

55

25

20

100000 95

90

65

30

25

100000 ns

115

ns
ns

ns
80

ns

100

120

150

ns

Write address hold time referenced
tAWR
toRAS

80

90

110

ns

Read address to RAS lead time

tRAL

45

55

70

ns

Column address hold time
referenced to RAS rising time '10

tAHR

15

15

20

ns

Last write to column address delay
time· 11 ,12

tLWAD

20

Column address hold time
referenced to last write

tAHLW

90

110

140

ns

Read command set up time
referenced to <::AS

tRCS

0

0

0

ns

Read command hold time
referenced to RAS'13

tRRH

10

10

10

ns

Read command ,hold time
referenced to <::AS'13

tRCH

0

0

0

ns

W pulse width

twp

15

20

25

ns

W inactive time

tWI

15

20

25

ns

Write command hold time

twCH

15

20

25

ns

Write command to RAS lead time

tRWL

25

30

35

ns

Write command to CAS" lead time

tCWL

25

30

35

ns

Notes:

45

20

55

25

70

ns

·7 Write eyda only.
·8 Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if
IRAQ is greater than the specified lRAD (max) limit. then access time Is controlled by tAA

*9 tRAD (min)

=

tRAH (min) + IT (IT

=

5 ns).

·10 tAHR is speclffed to latch column address by the rising edge of RAS.

*11 Operation within the tLWAD (max) Umit insures that tALW (max) can be met. tLWAD (max) is specified as a reference point only; if
tLWAD is greater than the specified tLWAD (max) limit, then access time Is controlled by T AA'
*12 tLWAD (min) '" teAH (min)

+ IT (tT '"

5 ns).

*13 Either tRRH or tRCH must be satisfied for a read cycle.

F'UJI'I'SU

2-25

MB81C466-10
MB81C466-12
MB81C466-15

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
nOled.)",2

Parameter

RAS to Wdelay time"4
~ to W delay time

Symbol

MB81C466-10
Min
Max

MB81C466-12
Min
Max

MB81C466-15
Min
Max

Unit

!Awo

125

150

185

ns

tcwo

50

80

70

ns

Column address to W delay time

tAWO

70

85

100

ns

RAS to second write delay lime

IRSWO

100

120

150

ns

Wrlle command hold lime
referenced 10 RAS

twCR

80

95

115

ns

RAS precharge time from lasl write

IRPLW

135

155

165

ns

Write sel up lime for outpul
disable"4

IWS

0

0

0

ns

Wrlle hold lime for oulput disable"4

twH

0

0

0

ns

INseluptime

loS

0

0

0

ns

IN hold time

tOH

0

15

20

ns

IN hold time referenced 10 RAS

toHR

80

90

110

Access time from OE

IOEA

30

25

OE 10 data in delay time

IOEO

20

Output buffer turn off delay time
fromOE

IOEZ

0

25
20

0

ns
35

30
25

0

ns
ns

30

ns

l5E hold lime referenced to RAS "5

IOEHR

20

20

20

ns

OE hold lime referenced 10 ~"5

toEHC

10

20

20

ns

Refresh set up time for ~
referenced 10 RAS (~-B-R)

tFCS

25

25

30

ns

Refresh hold time for ~
referenced 10 RAS (~-B-R)

tFCH

25

25

30

ns

~ precharge lime (~-B-R)

!cPR

25

25

30

ns

time (refresh cycles)

IRPC

20

20

20

ns

RAS precharge lime to ~ active
Static mode read/write cycle time

ISC

50

60

75

ns

Static mode read-modify-wrlle cycle
time

tSRWC

120

145

180

ns
ns

Static mode ~ precharge time

ICp

15

20

25

OE to RAS inactive sel up time

toES

25

30

35

ns

INlo~delaytime"6

tozc

0

0

0

ns

IN 10 OE delay lime"6

lozO

0

0

0

ns

Refresh counler test cycle time ',7

IRTC

465

550

645

ns

Notes: *14 tW5. and IRWD are specified as a reference point only. If tws ~ tws (min) and tWH ;;;;. tWH (min), the data output pin will remain
High-Z state throughout entJre cycle. It tRWD;;;;' tAwe (min). The data output will contain data read from the selected cell.
"15 Either tOEHR or tOEHC is satisfied, output is disabled.
"'16 Either IDZC or tozo must be satisfied.
*17 CAS-before-RAS refresh counter test cycle only.

2-26

MB81C466-10
MB81C466-12
MB81C466-15

AC Characteristics
(Continued)
(Recommended operating
conpitions unless otherwise
not9,d.r ' ·2

MB81C466-12
Min
Max

MB81C466-15
Min
Max

Unit

440

535

ns

Parameter

Symbol

MB81C466-10
~Max
Min

Refresh counter test RAS pulse
width'17

tTRAS

365

Refresh counter test CAS precharge
time'17

tCPT

50

Refresh counter test RAS to column
address delay time'17

tCADT

100

120

150

ns

Refresh counter test access time
from CAS'17

tCACT

135

165

205

ns

Refresh counter test CAS to W
delay time'17

tCWDT

135

10000

10000

60

165

10000

70

ns

205

ns

Notes: '17 CAS-before-RAS refresh counter test cycle only.

Description
Address Inputs

Data Output

Output Enable

A total of sixteen binary input address bits are required to decode
parallel 4-bits of the 262,144 storage cells within the MB81 C466.
Eight row address bits are established on the address input pins
(Ao to A7) and latched with the
Row Address Strobe (RAS).
Eight column address bits are
established on the address input
pins (Ao to A7) after the Row
Address Hold Time has been satisfied. In read cycle, the column
addresses are not latched by the
Column Address Strobe (CAS),
so the column address must be
stable until the output becomes
valid. In write cycle, the column
addresses are latched by the
later falling edge of CAS or W.

The output buffer is three-state
TTL compatible with a fan out of
two standard TTL loads. Data out
has the same porality as data in.
The output is in high impedance
state until CAS is brought low. In
a read cycle, the access time is
determined by the following
conditions:

The DE controls the impedance
of the output buffers. If the DE is
high the output buffers are in the
high impedance state. If the DE
is low the output buffers are in
the low impedance state. In the
write cycle (W controlled), the DE
must be high before the data applied to DO pins. When W controlled write cycles is not used,
DE can be low throughout the
operation.

1. tRAC from the falling edge of
RAS.
2. tAA from the column address
inputs.

3. tCAC from the falling edge of
CAS.
4 . .to.oA from the falling edge of
OE.

Write Enable
Read or Write cycle is selected
with the W inputs. A high on W
selects read cycle and low selects write cycle. The write operation is asserted on the latter
falling edge of CAS or W (Both
CAS and Ware low.). The time
period of the write operation is
determined by internal circuit,
thus the next write operation will
be inhibited during the write
operation.

When both t RCD and tRAD satisfy
their maximum limits, tRAC ~ t RCD
+ tCAC or tRAC ~ tRAD + t AA ·
Data output remains valid while
the column address inputs are
kept constant. However, when
either CAS or OE goes high, the
output returns to a high impedance state. In the static write
cycle (CAS controlled), if both
tws"" tws (min) and tWH "" tWH
(min) are met, data pins are input
mode regardless of the state of
OE.

Data Pins
Data Inputs;
Data is ~!tten into the
MB81C4i6 during write or readmodify-write cycle. The input data
is strobed and latched by the
later falling edge of CAS or W.

FUJITSU
2-27

Static Mode
The static mode operation allows
continuous read, write, or readmodify-write cycle within a row by
applying new column address. In
the static mode, CAS can be kept
low throughout static mode operation. The following four cycles
are allowed in the static mode.
1. Static mode read cycle;
In a static mode read cycle,
the access time is Iae..c from
the falling edge of RAS or tAA
from the column address input
or ~A from the falling edge
of OE. The data remains valid
for a time t AOH after the column address is changed.

2. Static mode write cycle;
In a static mode write cycle,
the data is written into the cell
triggered~the ~ter falling
edge of CAS or W. If both tws
and tWH are greater than their
minimum limits, the data output pin is kept high impedance state through the static
mode write cycle. The DE
must be high before the data
are applied to DO pins.

MB81C466-10
MB81C466-12
MB81C466-15

Description
(Continued)

2. CAS-before-RAS refresh;
CAS-before-RAS refreshing
available on the MB81C466
offers an alternate refresh
method. If CAS is held low for
the s~fied period (tFOS) before RAS goes low, on chip
refresh control clock generator
and the refresh address
counter are enabled, and an
internal refresh operation
takes place. After the refresh
operation, the refresh address
counter is automatically incremented in preparation for the
next CAS-before-RAS refresh
operation.

3. Static mode read-modify-write
cycle;
In a static mode read-modifywrHe cycle, W goes low after
t AWD from the column address
inputs and leWD from the failing edge of ~. the data and
column address inputs are
strobed and latched by the
falling edge of W. The OE
must be high before the data
are applied to DQ pins.
4. Static mode mixed cycle;
In a static mode, read, write,
and read-modify-write cycles
can be mixed in any order.
In the next static mode read,
write cycle or read-modify-write
cycle, the access time is determined by the following
conditions.
1 . .!ALW from the falling edge of
W at previous write cycle.
2. tM from the column address
inputs.

3.

tWPA from the rising edge of W
at the read cycle.

4. ~ from the falling edge of
CAS.

3. Hidden refresh;
A hidden refresh cycle may
take place while maintaining
latest valid data at the output
pin by extending. the CAS low
time. For the MB61C466, a
hidden refresh cycle is CASbefore-RAS refresh. The internal refresh address counter
provides the refresh address,
as in a normal CAS-beforeRAS refresh cycle.
CAS·Before-~ Refresh

Counter Test

5. tOEA from the falling edge of
OE.

~ecial tim~sequence

Refresh
Refresh of dynamic memory cells
is aocomplished by performing a
memory cycle at each of the 256
row addresses (AD to A7 at least
every 4 ms.)

using
CAS-before-RAS refresh counter
test cycle provides a convenient
method of veri~ the function
of CAS-before-RAS refresh activated circuitry. After the CAS-before-RAS refresh operation, if
CAS goes to high and then goes

The MB61C466 offers the following three types of refresh.
1. RAS only refresh;
RAS-only refresh avoids any
output during refresh because
the output buffer is high in the
Impedance state due to CAS
= high. Strobing of each 256
row address (Ao to A7) with
RAS will cause all bits in each
row to be refreshed.

2-28

1) Initialize the internal refresh
address counter b~ng
eight CAS-before-RAS refresh cycles.
2) Throughout the test, use the
same column address.
3) Using a write cycle, write Os
to all 256 row addresses.
4) Using CAS-before-RAS refresh counter test cycle in
read-modify-write mode, read
the 0 written in step 3), and
simultaneously wrHe 1 to the
same cell. This step is repeated 256 times and row address is generated by internal
refresh address counter.
5) Using a normal read cycle,
read back the 1 written in step
4), from all 256 locations.
6) Complement the test pattern
and repeat step 3), 4), and 5).
to low again while RAS is held
low, the read and read-modifywrite cycles are enabled according to the state of W. This is
shown in the CAS-before-RAS
counter test cycle timing diagram.
A memory cell address, consisting of a row address (8-bits) and
a column address (8-bHs), to be
accessed are shown below.
ROW ADDRESS-Bits AD to A7
are provided by the refresh
counter.
COLUMN ADDRESS-All the
bits Ao to A7 are provided by externally after t CADT .
The recommended procedure of
CAS-before-RAS refresh counter
test is shown below. The timing
of CAS-before-RAS refresh
counter test cycle should be
used.

MB81C466-10
MB81C466-12
MB81C466-15

Timing Diagrams
Read Cycle
~---------------------IRC:--------------------------~
~

m

Cli§

_______________ IRAS _____________

~

VOH
VOL

VOH
VOL

ADDRESS

VOH
VOL

W

VOH
VOL

DATA

VOH

(OUT)

VOL

DATA
(IN)

VOH
VOL !.L.L.L.t...I.J..I.:..t...'-L.u.u..l.J!

VOH

~L~~LL~~~~LL~~~~LL~________~LL~~~~LL~~~~
• IF tRAD

~

tRAD (MAX), ACCESS nME IS tAAo

FUJITSU

2-29

t'ZZl DDN'T CARE

MB81C468-10
MB81C486·12
MB81C466·15

Timing Diagrams
(Continued)

Write cycle

(W controlled)
~-------------------IOC----------------------------~

1+--------- 10,8-----------+1
V,H
V,L

V,H
V,L

ADDRESS

V,H
V,L

V,H
V,L

DATA
(IN)

V,H
V,L

'-'-'-'-L..t...L.L.L..<.Lf=1

DATA
(OUT)

rZZJ DON'T CARE
~ INVALID DATE

2-30

MBa1C466-10
MB81C466-12
MB81C466·15

Timing Diagrams
(Continued)

,en Controlled)

Write Cycle
OE; Don't Care

~-------------------IRC--------------------------~~
~----------------IRM--------------~~

CAS

V,H
V,L

V,H
ADDRESS

V,L

W

DATA
(IN)

DATA
(OUT)

V,H
V,L

V,H
V,L

VOl< - - - - - - - - - - - - - - - - - - - - - - - H I G H - Z . - - - - - - - - - - - - - - - - - VOL
IF OE IS KEPT HIGH THROUGH A CYCLE OR tws ~ tws (MIN) and tWH ~ tWH (MIN) ARE

MET, DO PINS ARE KEPT HIGH IMPEDANCE STATE,

FU.JlTSU

2-31

rzz.l DON'T CARE

MB81C466-10
MB81C466-12
MB81C466-16

Timing Diagrams
(Continued)

RNd-Uodlf.-Wrlts Crels
~----------------------tRWC----------------------~

1+---------- t"••, - - -_ _ _ _ _

m

v,"

CAS

V,"

~

v,.

v,.

ADDRESS

v,"

\Ii

v,"

DATA
(IN)

"'v,."

V,.

v,.

DATA
(OUT)

OE

IZZJ DON'T CARE

m

2·32

INVAUD DATA

MB81C466-10
MB81C486·12
MB81C466·15

Timing Diagrams
(Continued)

Static Mode Read Cycle
tRe
tCSH

RAS

CAS

VIH
VIL

VIH
VIL

VIH
ADDRESS

W

DATA
(OUT)

VIL

YoH
VIL

VOH
VOL

DATA

VIH

(IN)

VIL

OE

YoH
VIL

fZZ) DON'T CARE

FUJI'I'SU

2·33

MB81C466-10
MB81C466·12
MB81C466-15

Timing Diagrams
(Continued)

Static Mode Write Cycle
'RC

IRAS

iiAS

"'"

CAS

"'"

VOL

VOL

ADDRESS

V,"
V,L

W

V,H
V,L

DATA
(IN)

V,H

DATA

VOti

(OUT)

OE

V,L

VOL

V,H
V,l

I7Zl DDN'T CARE
Ii?:3J INVALID DATA

2-34

MB81C466-10
MB81C466-12
MB81 C466-15

Timing Diagrams
(Continued)

Static Mode Read-Modlfy-Wrlte Cycle
~

_______________________ tRC __________________________

~

f+-------------------tRAS,-----------------~

V,H

V,L

V,H

V,L

ADDRESS

w

V,H

DATA

V,H

V,L

(IN)

V,L l..I..I.L.I.L.I.L.i..I..LJ1

DATA
(OUT)

V,H

V,L

~~~~~~--~

VALID DATA.

rzzl DON'T CARE

m

FUJITSU

2-35

INVALID DATA

MB81C466-10
MB81C466-12
MB81C468-15

Timing Diagrams
(Continued)

Static Mode Mixed Cycle
~----------------------------------I~------------------------------------------~
~----------------------------I~----------------------------~

V,H

V,L

ADDRESS

V,H

Vi

V,L .L..i..LJ.CL.H;

.

-••
-.

Truth Table

H
L
L

Absoluta Maximum Ratings
(See Note)

x
L
H

..-.-

~ 3~
A3
~ 5I
A, 6 I
As 7 I

Mode

Output

Power

NOT SELECTED
WRITE
READ

HIGHZ
HIGHZ
Q

STANDBY
ACTIVE
ACTIVE

Dour

118 Au

"7 A"
"6 AID

-.-.
-.
!!

:',;; At
:'_4 As
~ 1..3

"7

~5rlJ'
(LCC-2OC-F01)

RatIng

Symbol

Value

Unit

Supply Voltage
Input voltage on any pin with respect to GND
Output voltage on any pin with respect to GND
Temperature Under Bias
Ceramic
Storage Temperature
Plastic
Power Dissipation
Output Current

Vet;
VIN
VOUT
T BIAS

-0.5 to +7
-3.5 to +7
-0.5 to +7
-10to +85
-65 to +150

V
V
V
·C
·C

-40 to +125
1.0

W
rnA

±20

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. This device contains Circuitry to protect the Inputs against damage due to high static voltages or
electric fields. However, it is advised that noonal precautions be taken to avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.

Capacitance
(fA = 25·C, f = 1 MHz)

Parameter

Symbol

Input Capacitance (VIN =OV)
E Capacitance (VE =OV)

CIN
CE
COUT

Output Capacitance (VOUT

=OV)

FUJITSU

3·3

~p

Ma.

Unit

5

pF
pF
pF

7

8

MB81C87·35
MB81C87·411

Recommended Operating
Conditions
(Referenced to Vss )

Parameter

S,Imboi

Min

Typ

Ma"

Unit

Supply Voltage

Vee
V IL

4.5

5.0

5.5

V

0.8

V
V
·C

Input Low Voltage
Input High Voltage

-3.0'
2.2

VIH

6.0
70

Ambient Temperature

0
TA
'-3.0 V Min. for Pulse width less than 20n8. (VIL Min= -1.0V at DC level)

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Te.t Condition

S,Imbol

Min

Ma"

Unit

Input Leakage Current

VIN = OV to Vcc

-2

Output Leakage Current

E = VIH' VOUT = OV to Vee

III
ILO

+2
+2

,.A
,.A

Active Supply Current

E=VIL,loUT=OmA
VIN = VIL or V IH
E=VIL,IOUT=OmA
Cycle = min, CL = OpF

IcCi

40

mA

Icc2

60

mA

IS81

15

mA

ISB2
VOL
VOH

25
0.4

mA
V
V

Operating Supply Current
Standby Supply Current
Standby Supply Current
Output Low Voltage
Output High Voltage

AC Characteristics
Recommended operating
conditions unless otherwise
noted.)

E""Vcc- 0.2V
VIN"" Vcc-0.2V or
VIN" 0.2V
E=VI~

IOL=16mA
10H= -4mA

M8
81C87·35

Read Cycle

Parameter

Symbol

Min

Read Cycle Time

TAVAX
TAVQV

35

Address Access Time

."'
AC

Ma"

TELQV
TAXQX

5

Chip Enable to Output in Low-Z

TELQX

Chip Enable to Output in High-Z

TEHQZ

5
0

Chip Selection to Power UP
Chip Deselection to Power Down

TELIH
TEHIL

5
25
30

0.6V to 2.4V
5ns
Inputs: 1.5V
Output: 1.5V

2V

T
>

<)1000
<

<> 1000
>

(

1-

I

30PF

(For

FUJITSU
3-4

I-

0

25

0

0

T

45
45
5

Output Load:

1"">---0

M8
81C87·45
Min
Max
45

Test Conditions

)

2.4

35
35

Chip Select Access Time
Output Hold from Address Change

Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Measurement Reference Levels:

-2

0

5PF

TEHOZ, TWLOZ, TELOX, TWHOX)

40

MB81C87-35
MB81C87-45

Read Cycle Timing Diagram·'
Read Cycle, Addre •• Controlled· 2
~-------------TAVAX----------~·~I

Address

f4------- TAVQV

•

TAXQX

Data Out (Q)

Read Cycle,

Data Valid

Previous Data Valid

E Controlled ·3
f4-------------TAVAX----------~.~1

I~..
------ TAVQV-----..~I
-TElQX
High·Z
Data Out (Q) ----~--------~

~

:: -n--f},,%

______

~

______.JI

_TEHll_l

50%

Note: ·1) W is high for Read cycle.
*2) Device is continuously selected, E == V 1L.
*3) Address valid prior to or coincident with

~
E transition

Write Cycle

Don't Care

MB
81C87-35
Parameter

Symbol

Min

Write Cycle Time

TAVAV

MB
81C87-45
Max

Min

Chip Enable to End of Write

TELEH

Address Valid to End of Write

TAVWH

Address Setup Time

TAVWL

a

a

Write Pulse Width

TWLWH

Data Valid to End of Write

TDVWH

20
20

25
20

a
a
a
a

a
a
a
a

TWHAX

Data Hold Time

TWHDX

Write Enable to Output in High-Z

TWLQZ

Output Active from End of Write

TWHQX

FUJITSU
3-5

Max

45
35
35

35
30
30

Write Recovery Time

: Undefined

IZ::ZI :

low.

25
25

25
25

MB81C87.311
MB81C87.411

Write Cycle Timing Diagram
Write Cycle: W Controlled

Address

w

Data In (D)

Data Out
(Q)

~

IZ:ZI :

: Undefined

Don'! Car.

Write Cycle: i Controlled
I~•.--------------TAVAX-------------'·~I

Address

TAVEL

I+"---!....._---TELEH-----I~

w

DATA

Data Out

V~LlD

TWLQZ~
__ _ _ _~=_T.ELQX
_

•_ _H...;Ig;,.h_"Z_____________

(Q)

~ : Undefined
FUJITSU
3·6

~ : Don'! Care

M881C87·as
M881C87·4S

Packa•• Dlm.n.lon.
20·L. .d C.ramlc CC.rdlp)
Dual In·Lln. Packa ••
DIP·20C·COa
1'1.02510.141

."

20·Load PI. .tlc
Dual In·Lln. Packa••
DIP·20P·M01

20·Pad C.ramlc C"rlt S. .I)
Loadl ••• Chip Carrl.r
LCC.20C·"01
~

3-7

FUJITSU

MOS Memories
•

M881C67·45·W, MB81C67·55·W
CMOS 16,384-Bit Static
Random Access Memory

Description
The Fujitsu MB81C67 is a 16,384 word x 1-bit static random
access memory fabricated with a CMOS silicon gate process. This
device is fully static and requires no clock or timing strobes.
All pins are TTL compatible and a single 5 volt power supply
is required.
For ease of use, chip enable (E) permits the selection of an individual package when outputs are OR-tied, and automatically powers
down the MB81C67. All devices offer the advantages of low power
dissipation, low cost, and high performance.

Features
• Organization:
16,384 words x 1-bit
• Static operation:
no clocks or refresh
required
• Fast access time:
45 ns max. (MB81C67-45-W)
55 ns max_ (MB81C67-55-W)
• Single +5V supply,
±10% tolerance
• Separate data Input and
output
• TTL compatible inputs and
output

• Three-state output with
OR-tie capability
• Chip enable for simplified
memory expansion, automatic power down
• All inputs and output have
protection against static
charge
• Standard 2G-pin DIP
package
• Pin compatible with
Fujitsu MB8187A

This device contains circuitry to
protect the inputs against damage

due to high static voltages or electric fields. However, It is advised
that normal precautions be taken to
avoid application of any voftage
higher than maximum rated vottages to this high impedance circuit.

3-8

MB81C87·45·W
MB81C87·55·W

MB81C87 Block Diagram
and Pin Asslgnm_t

A"
A13

Vee

...-Vcc

Ao

CELL ARRAY
128 ROWS
128 COLUMNS

ROW
SELECT

A,
A2

""'-Vss

At
A4

A,

A13

A,

A,2

A,

Al1

A4

A,.

At
COLUMN I/O CIRCUITS

D

At

Q

A,
D

E

!

VB.

iN
(TOP VIEW)

TRUTH TABLE

E

W

MODE

OUTPUT

POWER

H

X

NOT SELECTED

HIGH-Z

STANDBY

L

L

WRITE

HIGH-Z

ACTIVE

L

H

READ

Q

ACTIVE

1li!~[lJ'
(LCC-20C-F01 )

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Supply voltage

Vee

-0.5 to +7.0

Unit
V

Input voltage on any pin
with respect to Vss

VIN

-3.5 to +7.0

V

Output voltage on any pin
with respect to Vss

VOUT

-0.5 to +7.0

V

Temperature under bias

T BIAS

-55 to +125

'C

Storage temperature

TSTG

-65 to +150

'C

Power dissipation

Po

1.0

W

Output current

lOUT

±20

mA

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS afe exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Recommended Ope.etlng
Conditions
(Referenced to Vss)

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.5

5.0

5.5

V
V

Parameter
Input low voltage

VIL

-2.0- 1

0.7

Input high voltage

VIH

2.3

6.0

V

Ambient temperature

TA

-55

125

'C

Note: *1 -2.0 min. tor pulse width less than 20 ns (V,L min. = -O.5Vat DC Jevel).

FUJITSU
3-9

MB81C87·45·W
MB81C87·55·W

Capacitance
(TA

= 25'C, I =

1 MHz)

Parameter

Symbol

Input capacHance (VIN

E capacitance (VE =

= OV)

0V)

Output capacitance (VOUT

Typ

CIN

= OV)

Max

Unit

5

pF

C'E

7

pF

COUT

8

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Test Condition

Symbol

Min

Max

Unit

Input leakage current

VIN

= OV to Vcc
E = VIH'
VOUT = OV to Vee
E = VIL, lOUT = 0 rnA
VIN = VIL or VIH
E = VIL, lOUT = 0 rnA
Cycle = min, C L = 0 pF

'll

-10

10

/LA

ILO

-50

50

/LA

ICCl

80

rnA

Icc2

70

rnA

VIN ;. Vcc -0.2V or
VIN .. 0.2V

IS81

25

rnA

E

= VIH
= 8 rnA
IOH = -4 rnA

ISB2

35

rnA

IOL

VOL

0.4

V

Output leakage current
Active supply current
Operating supply current

E ;. Vee -0.2V
Standby supply current
Standby supply current
Output low voltage
Output high voltage

VOH

2.4

V

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle
Parameter

Symbol

MB81C67.4S·W
Min
Max

MB81C87·S5·W
Min
Max

Unit

Read cycle time

TAVAV

45

55

ns

Address access time

TAVQV

45

55

ns

Chip select access time

TELQV

45

55

ns

Output hold Irom address change

TAXQX

5

5

Chip enable to output active

TELQZ

5

5

Chip enable to output in high-Z

TEHQZ

0

3-10

25

0

ns
ns
30

ns

MB81C67·45·W
MB81C67.55·W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle Timing Diagram"'
Read Cycle: Address Controlled"2

~

~------TAVAX

A

TAVQV----..
~'

----

TAXQX
PREVIOUS DATA
VALID

Q

Read Cycle:

DATA VALID

E Controlled"a
~-------~VAX-------~

HIGH-Z

Q

I7Zl DON"T CARE

NOTE: "' Vi IS HIGH FOR READ CYCLE.
"2 DEVICE IS CON11NUOUSLY SELECTED, E= V,L • E
"3 ADDRESS VALID PRIOR TO OR COINCIDENT WITH TRANSI110N LOW

~UNDEFINED

Write Cycle

Parameter

Symbol

MB81C67-45-W
Min
Max

MB81C67·55·W
Min
Max

Unit

Write cycle time

TAVAX

45

55

ns

Chip enable to end of write

TEIEH

35

45

ns

Address valid to end of write

TAVWH

45

ns

Address setup time

TAVWL

35
5

5

ns

Write pulse width

TWLWH

25

30

ns

Data valid to end of write

TOVWH

20

25

ns
ns

Wr~e

TWHAX

5

5

Data hold time

TWHDX

0

5

Write enable to output in high-Z

TWHOZ

0

25

0

30

ns

Output active from end of write

TWHOX

0

25

0

30

ns

recovery time

FUJITSU

3-11

ns

MB81C67·45·W
MB81C67·55·W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Diagram
Write Cycle: VI Controlled
k - - - - - - - - - T A V A X ----------1~

ADDRESS

w

DATA IN (D)
------I~TWLQZ

I------;~

TWHQX

HIGH·Z

DATA OUT(Q)

~UNDEFINED

rzzJ DON'T CARE

3·12

MB81C67·45·W
MB81C67·55·W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Wrlle ercl.: i Controlled

ADDRESS

w

DATA IN (D)

HIGH·Z

DATA OUT (0)

riQljI UNDEFINED

f22I
AC Test Conditions

OVto 3.0V
Input Pulse Levels:
5 ns
Input Pulse Rise and Fall Times:
Timing Measurement Reference Levels: Input: 1.5V
Output: 0.B/2.2
Output load:

2V

2V

10QU

100U

.....- - - - 0

r

.....- - - - Q

r

(FOR TEHQZ, TWLQZ, TELQZ, AND TWHQZ

FUJITSU
3-13

DON'T CARE

MB81C87.45·W
MB81C87·55·W

Packa.e Dlmen.lon.
Dimensions In inches
(millimeters)

200L_d Ceramic (CERDIP) Dl/alln-Llne Packa.e.
(ea.e NO.1 DIP.2OC·C03)

~t:~~:~:~:I'~
.

1.000(25A)

.014(0.36)

20·Pad Ceramic (Frlt S_I) Leadle•• Chip Carrier
(Ca. . NO.1 LCCo20CoF01)

PIN NO.1 INOEX

\

R.012(0.30)TYP

n

(4PLCS)

.420(10.67)
.435(11.05)

I, ~ .1

.280(7.11)
.295(7A9)

.050(1.27)
TYP

.100(2.54)

.045(1.14)

MAX

TYP
TYP

3·14

MB81C67·45·W
MB81C67·55·W

Packa•• Dlm.nslons
(Continued)
Dimensions in inches
(millimeters)

ZO·Lead Ceramic (C.rdlpl Flat Packa••
(Cas. No•• FPT.ZOC·COZI

--j I

475(1207)
.500(12.70)

.015(0.38)
• .020(0.51)

.2J

.86)
.300(7.62)

l

.290(7.37)
.315(6.00)

.855(21.72)MIN

Y

PIN #1 IDENT /

.025(0.54)MA

.025(0.54)
.045(1.14)

.27016.86)
.300(7.52)

i:=

--J
.450(11.43)REF

3·15

~

TV P

• .050(1.27)

-

.004(0.10)
.007(0.18)
.100(2.54)MAX

FUJITSU

MOS Memories
•

MB81C68-35, MB81C68-45
16,384-Bit Static Random
Access Memory with
Automatic Power Down

Description
The Fujitsu MB81 C68 is a 4,096 word x 4-bn static random access
memory fabricated using C-MOS silicon gate technology. This device is fully static and requires no clock or timing strobe. All pins
are TTL compatible, and a single + 5 vo~ power supply required.
A separate chip enable (E) pin simplifies muHipackage system design. It permits the selection of an individual package when outp~
are OR-tied. Furthermore, when selecting a single package by E,
the other deselected devices automatically power down.
The MB81C68 offers the advantages of low power dissipation, low
cost, and high performance.

Features
Organization:
4,096 words x 4-blts
Static operation: no clocks
or timing strobe required
• Fast accass time:
TAVQV = TElQV =
35 ns max. (MB81C68-35)
TAVQV = TElQV =
45 ns max. (MB81C68-45)
• Single +5V supply
±10% tolerance
• TTL compatible inputs and
outputs
• Low power consumption:
385 mw max. (oparatlng)
138 mw max. (standby)

Three-state outputs with
OR-tie capability
Chip enable for simplified
memory expansion, automatic p _ down
• Ali Inputa and outputs have
protection against static
charge

•

•

•

•

• Standard ZO-pin DIP
•

package
Pin compatible with Fujitsu
MB8188

This device contains circuitry to
protect the inputs against ~
due to high static voltages or .....

tric fields. H......r, II is advi*
lhat normal precautions be taken to
avoid appRcatIon of any voltage
higher than maximum rated volt·
ages to this high impedance circu~.

3-16

MB81C68·35
MB81C68·45

MB81C68 Block Diagram
and Pin Assignments

A4~-------t~===f----1

Vee
..........a Vss

..........0

A5o---------~~==:1

Vee

Ao

128 x 128
MEMORY CELL
ARRAY

Aoo---------CK===:j
A70---------~~==~ S~~E~T

A,

A,.

AaG-----Q==:j
A.o---------~===:j

A"

A,. o---------J~===t_____.J
COLUMN
000 O______~~~----,-----~E3~~'/:O~~:R=C:U:'TS~~~~~nn
F

DO.

DO,

DO:!

DO,o-----11~1C~--_1

Da"

DO:! o--.,-H+-I>--_1

Vii

oa. o------1+H4--f>---j
(TOP VIEW)

E 0--+-0.--'"
w~~~------------------------J

:1.!'

At

~1! Ata
~ 1..6 A11
'15 I/O,

:;4

Absolute Maximum Ratings
(See Nole)

E

W

MODE

DO

POWER

H
L
L

X

NOT SELECTED
WR'TE
READ

H'Gtl-Z

STANDBY
ACTIVE
ACTIVE

L
H

~~T

1/02

!t! 1/°3

TRUTH TABLE

~~~~
(LCC-20C-FOl )

Rating

Symbol

Value

Unit

Supply voltage

Vee

-0.510 +7

V

Inpul vollage on any pin
wilh respect 10 Vss

V'N

-3.510 +7

V

OulpUI vollage on any DQ
pin with respect to Vss

V

VOUT

-0.510 +7

Output current

lOUT

±20

rnA

Power dissipation

Po

1.0

W

Temperature under bias

TB'AS

-10to +85

°C

Storage temperature

TSTG

Ceramic

-65 to +150

Plastic

-45 to +125

°C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

FUJITSU
3-17

MB81C68-35
MB81C68-45

Recommended Operating
Conditions

Parameter

Symbol

Min

Typ

Max

Unit

(Referenced to Vss )

Supply voltage

Vcc

4.5

5.0

5.5

V
V

Input low voltage

V IL

-OS

0.8

Input high voltage

V IH

2.2

6.0

V

Ambient temperature

TA

0

70

°C

Note: *-2.0V min for pulse width less than 20 ns.

Capacitance
(TA = 25°C, f = 1 MHz)

Max

Unit

Input capacitance (VIN

Parameter

Symbol

Typ

7

pF

DQ capacitance (VIIO

7

pF

= OV)= OV)-

Note: "This parameter is sampled and not 100% tested.

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Test Conditions

Symbol

Min

Max

Unit

Input leakage current

V IN

= OV to Vcc
E = VIH '
VI/O = OV to Vcc
lOUT = 0 mA
lOUT = 0 mA, cycle =

III

-10

10

/LA

ILO

-10

10

/LA

Output leakage current
Active (DC) supply current
Operating supply current
Standby supply current
Standby supply current
Output low voltage
Output high voltage

E = Vcc
= Vss or Vcc
E = V IH
10L = 8 mA
10H = -4 mA

VIN

3-18

min

Typ

ICC1

50

mA

Icc2

70

mA

ISB1

15

mA

ISB2

25

mA

VOL

0.4

V OH

2.4

V
V

MB81C68·35
MB81C68·45

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle
Parameter

Symbol

MB81C68·35
Min
Max

MB81C68·45
Min
Max

Unit

Read cycle time

TAVAX

35

45

ns

Address access time

TAVQV

35

45

ns

Chip enable access time

TELQV

35

45

ns

Output hold from address change

TAXQX

5

5

ns

Output hold from E

TEXQX

0

0

ns

Power up from E

TELIH

0

0

ns

Chip enable to output in low-Z

TELQX

5

5

ns

Chip deselection to output in high-Z

TEHQZ

0

Power down from E

TEHIL

15

0

30

20

ns

40

ns

Read Cycle Timing Diagrams"
Read Cycle: Address Controllad'2

ADDRESS

1 - - - - - TAVQV----+j
DO

DATAVAUD

Read Cycle: E Controlled '3

DATAVAUD

NOTES: "

W IS HIGH FOR READ CYCLE.

'2 DEVICE IS CONTINUOUSLY SELECTED, E = V,L.
.
'3 ADDRESS VAUD PRIOR TO OR COINCIDENT WITH E TRANSITION LOW.

FUJITSU
3-19

HIGH-Z

MB81C68·35
MB81C68·45

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle
Parameter

Symbol

MB81C68·35
Min
Max

MB81C68·45
Min
Max

Write cycle time

TAVAX

35

45

ns

Chip enable to end of write

TEIWH

30

35

ns

Unit

Address valid to end of write

TAVWH

30

35

ns

Address setup time

TAVWL,
TAVEL

0

0

ns

Write pulse width

TWLWH

30

35

ns

Data setup time

TDVWH

20

20

ns

Write recovery time

TWHAX,
TEHAX

0

0

ns

Data hold time

TWHDX

0

Output high-Z from W

TWLOZ

Output low-Z from W

TWHOX

ns

0

15

15

5

ns
ns

5

Write Cycle Timing Diagram
Write Cycle:

VI Controlled"

'2

~---------------------TAVAX--------------------~

ADDRESSES

J----------------TEIWH--------------~

J-+-----------------TAVWH--------------__+-----~~
TAVWL---~~.---------

w

D

HIGHZ

TELQX

"-TWLQZ

HIGHZ

Q

NOTES: "

IF E GOES HIGH SIMULTANEOUSLY WITH W HIGH, THE OUTPUT REMAINS IN A
HIGH IMPEDANCE STATE.

*2 E OR W MUST BE HIGH DURING ADDRESS TRANSITIONS.

3-20

00 UNDEFINED
!CZLl

DON'T CARE

.a.ieee·35
.B8iC88·45

AC Characteristics
(continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Diagram
Write Cycle: E Controlled"'2

ADDRESSES

w

o

Q

I)Qg

NOTES: 'I IF It GOES HIGH SIMULTANEOUSLY WITH W HIGH. THE OUTPUT REMAINS IN A
HIGH IMPEDANCE STATE.
'2 E OR W MUST BE HIGH DURING ADDRESS TRANSITIONS.

UNDEFINED

IZZl DON'T CARE

AC Test Conditions
Input pulse levels:
OV to 3.0V
Input pulse rise and fall times:
5 ns (Transient time between O.BV and 2.2V)
Timing measurement reference levels: Input: 1.5V
Output: 1.5V

s.ov

Output Load:

48011
: CL: 30 pF
: CL: 5 pF FOR TELQX, TEHQZ,
TWHQX AND TWLQZ

D Q - -......- - -..

CL
(INCLUDING SCOPE AND
FIXTURE CAPACITANCE)

f't1.JITSU
3-21

I

-=

2550

M881caa·35
MB81Caa·45

Package Dimensions
Dimensions in inches
(millimeters)

2o.Lead Ceramic ICerdlp) Dual In·Line Package
lease No.: DIP-2QC.C03)

~f~~~:~~~J1~
1.000(35A)

20·Lead Plastic Dual In.Llne Package
ICase No.: DIP-20P.M01)

.008(0.20)
.012(0.30)

tl'~'.118(3.O)MIN

.100(2.84)

fyp

.020(0.51)MIN

3·22

I

MB81C68·35
MB81C88.45

Package Dimensions
(continued)
Dimensions in inches
(millimeters)

2O·Pad Ceramic (Frlt Seal) Leadle.. Chip Carrier
(CBBe No.: LCC·20C·F01)

PIN NO.1 INDEX

~

b

n

R.0121O.30ITYP
14 PLCSI

.420110.671
.435111.051

.28017.111
.29517.491

.10012.541
MAX

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NonCE

3·23

.04511.141
TYP

Preliminary

FUJITSU
•

MB81C68A·25, MB81C68A·30, MB81C68A·35
4K x 4(16,384) Bit Super High
Speed Random Access Memory
with Automatic Power Down

Description
The Fujitsu MB81C68A is a 4,096 word x 4-bit static random
access memory fabricated using CMOS silicon gate process. This
device is fully static and required no clock or timing strobes. All
pins are TTL compatible, and a single + 5V voR power supply
is required.
A separate chip enable (E) pin simplifies multipackage systems
design. It permits the selection of an individual package when outputs are OR-tied. Furthermore, when selecting a single package by
E, the other deselected packages automatically power down.
All Fujitsu devices offer the advantages of low power dissipation,
low cost, and high performance.

• Organization:
4K words x 4-blts
• Static operation:
no clocks or timing strobe
required
• Fast access time:
TAVAV = TAVQV = 25 ns max.
(MB81C68A-25)
TAVAV = TAVQV = 30 ns max.
(MB81C68A-30)
TAVAV TAVQV 35 ns max.
(MB81C68A-35)

=

=

• Low power consumption
70 mA max. (active)
25 mA max. (standby. TTL
Input levels)
15 mA max. (standby, CMOS
Input levels)
• Single +5V supply ±100/0
• TTL compatible Inputs and
outputs
• Standard 20 pin DIP
• Automatic power down mode

This device contains circuitry to
protect the inputs against damage
due to high static voltages or elec·
tric fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

3-24

MB81C68A.25
MB81C88A.30
MB81C88A·35

MB81C88A Block DIagram
and PIn As.lgnments

~~----~~==r---I

~Vcc

A7o---------~==::j

A,so-----D=:::::::I

A7

vee

128 x 128

A.

A,

MEMORY CELL
ARRAY

A,

A,

A.

A,.

.....-0

"oo-----I)(:=::j
A,s0-----D=:::::::I
ROW
SELECT

vss

Aoo-----Oi==::1

A,·o---------R===L____J

COLUMN
I/O CIRCUITS

000 ~-____,-.J>_--f"--13

A,

An

A_

DO,

A,

DO_

A.

DO,

E

00.

o--~rtt_H>_---1

DO.

W

Vss

DO, o---"-+l+-HI>---~

(TOP VIEW)

w~~~----------------------~

As ~:

~1~

A4 ~!

~1! A,D

A3 ~!

~1..6 A11

~
A,

TRUTH TABLE

Absolute Maximum Ratings
(See Note)

!:

Ag

~': I/O,

!!

114 1/02

~ '=3 1/03

Ao ~!

E

W

MODE

0/0

POWER

H

X

NOT SELECTED

HIGH-Z

STANDBY

L

L

WRITE

IN

AC11VE

I:l ~ 1~ ~

L

H

READ

OUT

AC11VE

(LCC-20C-F01 )

Rating

Symbol

Value

Unit

Supply voltage

Vee

-0.5 to +7

V

Input voltage on any pin with
respect 10 GND

V IN

-3.510 +7

V

Output voltage on any I/O pin
with respect to GND

VOUT

-0.510 +7

V

Output current

lOUT

±20

mA

Power dissipalion

Po

1.0

W

T elAs

-1010 +85

'C

Temperalure under bias
Ceramic

Slorage temperature

Plastic

T STG

-6510 +150
-4510 +125

'C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions tor extended periods
may affect device reliability.

FUJITSU
3-25

MB81C68A·25
MB81C68A.30
MB81C68A·35

Recommended Operating
Conditions
(Referenced to V ss)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.5

5.0

5.5

V

Input low voltage
Input high

vo~age

Ambient temperature

VIL

-OS

0.8

V

V IH

2.2

6.0

V

TA

0

70

°C

Note: • -2.0V min. for pulse width Jess than 20 ns.

Capacitance
(TA = 25°C, f = 1 MHz)

Parameter

Symbol

= OV)
D/Q capacitance (VIIO = OV)

CIN

5

pF

CliO

7

pF

CS capacitance (VCS = OV)

Ccs

6

pF

Input capacitance (VIN

Typ

Max

DC Characteristics
(Reoommended operating
oonditions unless otherwise
noted.)

Parameter

Test Condition

Input leakage current

VIN

E

=

OV to Vcc

=

Output leakage current

VIH,
VIO = OV to Vcc

Active (DC) supply current

lOUT = 0 rnA, CS
VIN = VIL or VIH

Operating supply current
Standby supply current

=

!miT = 0 rnA, cycle
CS

=

VIL,
- min,

VIL

E - Vcc -0.2V, VIN ";0.2Vor
VIN ""-VCC -0.2V

= VIH
= BmA

Standby supply current

E

Output low voltage

IOL

Output high voltage

IOH

=

-4mA

3-26

Symbol

Min

lu
ILO

ryp

Unit

Max

Unit

-10

10

p.A

-10

10

p.A

ICC1

25

50

mA

ICC2

40

70

rnA

15B1

0.5

15B2

10

VOL
VOH

2.4

15

rnA

25

rnA

0.4

V
V

MB81C68A·25
MB81C68A·30
MB81C68A·35

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle
Parameter

MB81C68A·25 MB81C68A·30 MB81C68A·35
Symbol Min
Min
Max
Min
Max
Max
Unit

Read cycle time

TAVAX

Address access time

TAVQV

25

30

35

Chip select access time

TElQV

25

30

35

Output hold from address change

TAXQX

3

3

3

Output hold from E

TEXQX

0

0

0

ns

Chip enable to output in low-Z

TElQX

5

5

5

ns

25

Chip deselection to output in High-Z TEHQZ
Power up from E

TELIH

Power down from E

TEHll

30

35

10

ns

0

ns
ns

13

0

ns

15

ns

0

20

ns

25

30

ns

Read Cycle Timing Dlagram' 1
Read Cycle: Address Controlled"2

~~~-------------TAVAX--------------~~~
ADDRESS

~ ~I-'-~~====~--TA-V-O-V~~~---------~

1 ~_

... __________

PREVIOUS
DATA VALID

a

DATA VALID

Read Cycle: E Controlled '3

..

-TAVAX

~

V
J

\

.

....TEHOZ··....

TELOV_

f.-TEXOX-

-TELQX·· ....
HIGH-Z

a

'\

DATA VALID

~

_TELlH_

HIGH-Z

'Y

},

TEHIL

I
Icc
\

50%/

50%

\

SUPPLY
CURRENT

NOTES: "1

Vi IS HIGH FOR READ CYCLE.

=

-2 DEVICE IS CONTINUOUSLY SELECTED, E
VIL.
*3 ADDRESS VALID PRIOR TO OR COINCIDENT WITH E TRANSITION LOW.

'4 TRANSITION IS MEASURED AT THE POINT OF ± 0.5 V FROM STEADY-STATE VOLTAGE.

FUJITSU
3-27

00

UNDEFINED

f7Ll

DON'T CARE

MB8i C88A.25
MB8i C88A·30
MB8iC68A.3S

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle
Parameter

MB8iC68A·25
Symbol Min
Max

MB8iC68A·30
Min
Max

MB8i C68A.3S
Min
Max

Unit

Write cycle time

TAVAX

25

30

35

ns

Chip enable to end of write

TEIWH

20

25

30

ns

Address valid to end of write

TAVWH

20

25

30

ns

Address setup time

TAVWL
TAVEL

0

0

0

Write pulse width

TWLWH

20

25

30

ns

Data setup time

TDVWH

13

15

15

ns

Write recovery time

TWHAX
TEHAX

2

2

2

0

Data hold time

TWHDX

Output High-Z from W

TWLQZ

Output Low-Z from W

TWHQX

13

5

ns

0

0
10

ns

5

ns

15

ns
ns

5

Write Cycle Timing Diagrams
Write Cycle: WControlled'5,6

TAVAX

ADDRESS

TAVWH

E
TAVWH
TWLWH

Vi
TDVWH----~~----~

D

Q

NOTE: '5 IF E GOES HIGH SIMULTANEOUSLY WITH Vi HIGH. THE OUTPUT REMAINS IN A
HIGH IMPEDANCE STATE.
'6 E OR W MUST BE HIGH DURING ADDRESS TRANSITIONS.
'7 TRANSITION IS MEASURED AT THE POINT OF ± 0.5 v FROM STEADY STATE VOLTAGE.

3-28

m

KXlI

DON'T CARE

UNDEFINED

MB81C68A·25
MB81 C68A·30
MB81C68A·35

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle: E Controlled'S,9
~-------------------TAVAX-------------------'

ADDRESS

----------------TEIwH ----------------~

TAVEL~----~~----------TAVWH-----------~~

~TEHAX

I...-------TWLWH--------~

~TDVWH----~~----~I

D

o

________________-i_-LQ-Z-.-'O-----------HIGH.Z - - - - - - - - - - - - - - - - - - - - - -

NOTE: '8 IFE GOES HIGH SIMULTANEOUSLY WITH W HIGH. THE OUTPUT REMAINS IN A
HIGH IMPEDANCE STATE.
'9 E OR WMUST BE HIGH DURING ADDRESS TRANSITIONS.
'10 TRANSITION IS MEASURED AT THE POINT OF ± 0.5 V FROM STEADY ST ATE VOLTAGE.

AC Test Condition

OV to 3.0V
5 ns (Transient Time between O.BV and 2.2V)
Input: 1.5V
Output: 1.5V

Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Reference Levels:
Output Load:

s.ov

480Jl

DO

CL: 30 pF
CL: 5 pF FOR TELOX, TEHQZ,
TWHOX AND TWLOZ

----..------t
CL

(INCLUDING SCOPE AND
FIXTURE CAPACITANCE)

I

25511

-=-

FUJITSU
3-29

E'ZJ DON'T CARE
KXlI UNDEFINED

MB8iC68A.25
MB8i C68A·30
MB8iC68A.35

Package Dimensions
Dimensions in inches
(millimeters)

20·Lead Ceramic ICerdip) Dual In·Line Package
ICase No•• DIP·20C·C03)

'~'f~~~:~~~],~
1.000(35.4)

20·Lead Plastic Dual In· Line Package
ICase No •• DIP·20P·MOi)

INDEX·1

~
.012(0.30)

3·30

FUJITSU

MOS Memories
•

MB81C68.4S.W, MB81C68·S5·W
CMOS 16,384-Bit Static
Random Access Memory
With Automatic Power Down

Description
The Fujitsu MB81C68 is a 4,096 word x 4-bit static random access
memory fabricated using CMOS silicon gate process. This device
is fully static and requires no clock or timing strobe. All pins are
TTL compatible, and a single + 5 volt power supply is required.
A separate chip enable (E) pin simplifies multipackage systems
design. It permits the selection of an individual package when outputs are OR-tied. Furthermore when selecting a single package by
E, the other deselected devices automatically power down.
The MB81C68W offers the advantages of low power dissipation,
and high performance.

Features
• Organization:
4096 words x 4-blts
• Static operation:
no clocks or timing strobe
required

• Fast access time:
TAVQV = TELQV =
45 ns max. (MB81C68-45-W)
TAVQV TELQV
55 ns max, (MB81C68-55-W)
• Low power consumption:
385 mW max, (Operating)
138 mW max. (Standby)
• Single +5V supply.
±10% tolerance

=

=

• TTL compatible Inputs and
outputs
• Three-state outputs with
OR-tie capability
• Chip enable for simplified
memory expansion, automatic
power down
• All Inputs and outputs
have protection against
static charge
• Standard 2D-pin DIP package
• Pin compatible with
Fujitsu MB8168

this device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields. However, it Is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high Impedance circuit.

3-31

MB81C68·45·W
MB81C68·55·W

MB81C68W Block Diagram
and Pin Assignment

~Vcc

'"

AT

Vee

128 x 128

A,

As

MEMORY CELL
ARRAY

As

A.

'"

A,.

....-..0

As

A,
ROW
SELECT

AT

Vss

As

A,

A.
A,.

COLUMN
If 0 CIRCUITS

DO.

DO.

A,

DO,

A.

DO,

E

DO,

DO,
DO,

Al1

A,

Vss

iN

DO,

w~~~--------------------~

TRUTH TABLE

Absolute Maximum Ratings
(See Note)

E

W

MODE

DO

POWER

H

X

NOT SELECTED

HIGH-Z

STANDBY

L

l

WRITE

IN

ACTIVE

l

H

READ

OUT

ACTIVE

Rating

Symbol

Value

Unit

Supply voltage

Vee

-0.5 to +7

V

Input voltage on any pin
with respect to Vss

V,N

-3.5 to +7

V

Output voltage on any DO
pin with respect to Vss

VOUT

-0.5 to +7

V
rnA

Output current

lOUT

±20

Power dissipation

PD

1.0

W

Temperature under bias

T BIAS

-55 to +125

°C

Storage temperature

TSTG

-65 to +150

°C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

FUJITSU

3-32

MB81C68·45·W
MB81C68·55·W

Recommended Operating
Conditions
(Referenced to Vss )

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vcc

4.5

5.0

5.5

V

Input low voltage

VIL

-0.5'1

0.7

V

Input high voltage

VIH

2.3

6.0

V

Ambient temperature

TA

-55

125

°C

Note: *1 -1.0V min. for pulse width less than 20 ns.

Capacitance
(TA = 25°C, f = 1 MHz)

Parameter

Max

Unit

Input capacitance (VIN

C IN

Symbol

7

pF

I/O capacitance (VI/O

CliO

7

pF

= OV)
= OV)

Typ

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Test Condition

Symbol

Min

Max

Unit

Input leakage current

VIN

= OV to Vcc
E = V IH ,
V I/O = OV to Vcc

III

-10

10

I'A

ILO

-10

10

I'A

Output leakage current
Active (DC) supply
current

lOUT

0 rnA

Icc1

50

rnA

Operating supply current

lOUT = 0 rnA,
Cycle = min

ICC2

70

rnA

Standby supply current

E = Vee
V IN = Vss or Vce

ISB1

15

rnA

ISB2

25

rnA

VOL

0.4

Standby supply current
Output low voltage
Output high voltage

=

= VIH
IOL = 8 rnA
IOH = -4 rnA
E

3·33

VOH

2.4

V
V

M881C88-4S·W
M881C68·SS-W

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle
Parameter

Symbol

M881C68·45·W
Min
Max

M881C68·55·W
Min
Max

Unit

Read cycle time

TAVAX

45

55

ns

Address access time

TAVQV

45

55

Chip enable access time

TELQV

45

55

Output hold from address change

TAXQX

3

3

ns

Output hold from E

TEXQX

0

0

ns

Power up from E

TELIH

0

0

ns

Chip enable to output in low-Z

TELQX

5

5

ns

Chip deselection to output in
high-Z

TEHQZ

0

Power down from E

TI;HIL

0

17

40

ns
ns

20

ns

50

ns

Read Cycle Timing Diagram"l
Read Cycle: Address Controlled"2

~~~-------------TAVAX--------------~~
ADDRESS

--f~~...~-_-_-_-_-_-_--"t-'JII.-WQ-V--_-_-_-_-~~~.~I-----------'/~_
PREVIOUS
DATA VALID

Q

DATA VALID

Read Cycle: E Controlled"3

•

TAVAX

~

/
/

\
TElQV _ _

_TEHOZ._
_TEXOX_

-TElOX
HIGH·Z

Q

_---J~i
_

Vee SUPPLY

:---

CURRENT

ISB

TELIH

NOTES: "1 W IS HIGH FOR READ CYCLE.
::

HIGH-Z

DATA VALID

-TEHll

_ _

lcc_-l'---50%
"\ _

~~~~~ ~~~~~:b~s~~ ~~l~gJ:g.D~~V~TH E TRANsmoN lOW.

FUJITSU
3-34

\SSSI DON'T CARE

IZZll UNDEFINED

MB81C68·45·W
MB81C68·55-W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle

Symbol

Parameter

MB81C68·45·W
Min
Max

MB81C68·55-W
Min
Max

Unit

Write cycle time

TAVAX

45

55

ns

Chip selection to end of write

TEIWH

40

45

ns

Address valid to end of write

TAVWH

40

45

ns

Address setup time

TAVWL,
TAVEL

0

0

ns

Write pulse width

TWLWH

40

45

ns

Data setup time

TDVWH

23

25

ns

Write recovery time

TWHAX,
TEHAX

5

5

ns

Data hold time

TWHDX

3

Output high-Z from W

TWLOZ

Output low-Z from W

TWHOX

3
17

5

ns

20
5

ns
ns

Write Cycle: Ii Controlled'4.5

ADDRESS

TDVWH----~.---~~

D

TWHQX
Q

1

=3~~HIGH-Z ~

NOTES: '4) IF E GOES HIGH SIMULTANEOUSLY WITH iii HIGH, THE OUTFUT REMAINS IN A
HIGH IMPEDANCE STATE.
'5) E OR iii MUST BE HIGH DURING ADDRESS TRANSITIONS.

3-35

~DON'TCARE

~UNDEFINED

MB81C88·45.W
MB81C&a.55-W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Diagram
Write Cycle:

E Controlled·s,7
TAVAX
ADDRESS VAUD

ADDRESS

~-------- TAVWH

_.!!TA~,,:!e!:.L.I:!:=~t'-----

TElWH - - - - - - . j

~---------_

w
TDVWH

---.-14---+1

D

Q

-----~~~~~~----

HIGH-Z-------

NOTES: .6) IF E GOES HIGH SIMULTANEOUSLY WITH W HIGH, THE OUTPUT REMAINS IN A
HIGH IMPEDANCE STATE.
"7) E OR W MUST BE HIGH DURING ADDRESS TRANSITIONS.

AC Test Conditions
Input Pulse Levels:
OVto 3.0V
Input Pulse Rise and Fall Times: 5 nil (Transient Time between O.BV and 2.2V)
Timing Reference Levels:
Input: 1.5V
Output: 1.5V
Output Load:

5.0V

48011
: CL: 30pF
: CL: 5 pF FOR TELQX, TEHOZ,
TWHQX AND TWLOZ

Do -----T---i

CLr
(INCLUDING SCOPE AND
FIXTURE CAPACITANCE)

FUJITSU
3·36

25511

....1C...41·W
....1C880I..W

PIIclulge Dlm.nslon.
Dimensions in inches
(millimeters)

2G-Lead C.ramlc CCERDIPI Dual I ...Lln. Packa••
CCa•• No.: DIP.2OC·C031

~~t~~~:~~~~],~
1.000(35.4)

2O·Lead C.ramlc CCardlpl Fla. Packa••
CCe•• No.: FPT.2GC-C021

-..j

I

I"

A75(12.D7)
.500(12.70)
.015(0.38)
.020(0.51)

r:r~

.300(7.82)

l

.290(7.37)

PIN #110ENT

.1125(0.64)
.IJ45(1.14)

.855(21.72)_

/h-r"""'' ' ' IT"''IT"Tr-nr-n"''TT.....IY-

.OZS(O.64)MA

3-37

.004(0.10)
.1107(0.18)

.100(2.64)1IAX

MB.1C.....S-W
MB81Cea.S5.W

Package Dimensions
(continued)
Dimensions in inches
(millimeters)

20·PacI Ceramic (Metal S. .II Leadless Chip Carrier
(Case No.: LCC·20C-A011

PIN 1 INDEX

*PlN 1 INDEX

/

.195(4.95) TYP

n
.420(10.67)
435(11.05)

.335(8.51)
TYP

~4~~~) TYP

•280(7.11)

.000(1.27)TYP

I I

.000(1.27)TYP:_

I
..

.295(7.49)
.l&o(3.81)TYP

"SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOnCE

3-38

Preliminary

FUJITSU

MOS Memories
•

MB81 C68A-25, MB81 C68A-30, MB81 C68A-35
CMOS 16,384-Bit
Static Random Access Memory
with Fast Chip Select Access Time

Description
The Fujitsu MB81 C69A is a 4,096 word x 4-bit static random
access memory fabricated using CMOS silicon gate process. This
device is fully static and requires no clock or timing strobe. All pins
are TIL compatible, and a single +5 voH power supply is required.
A separate chip enable (E) pin permits the selection of an individual device when outputs are OR-tied.

The MB816C69A offers the advantages of low power dissipation,
high performance and low cost.

F.atures
• TIL compatible Inputs and
• Organization:
4,096 words x 4-blts
outputs
• Three-8late outputs with
• Static operation:
No clocks or timing strobe
OR-tie capebility
required
• Chip select for 81mpllfled
memory axpen810n
• Fsst acCHs time:
TAVAV TAVQV 25 ns max. • All InpUIa and outputs have
TElQV = 15 ns max.
8tatlc charge protection
• low power consumption:
• Standard 2O-pln DIP
385 mW max_ (Active)
• Slandard 2o-pln lCC
• Single +5V 8Upply ±10%
tolerance

=

=

This device contains circuitry to
protect the Inputs against damage
due" to high static voltages or electric fields. However, It Is advised
that norrnaJ precautions be taken to
avoid application of any vohage
higher than maximum rated voltages to this high Impedance circuit.

3-39

MB81C69A.25

MB81C69A Block DI.gr.m
.nd Pin Asslgnm.nt

Aoo-------bc::::::f--,

--..0 Vee
--..0

A5o---------4C~==~

V..

128 x 128

As o----~=::j

MEMORVCELL
ARRAV

AT o---------4C~==~ S~~E~
AsG-----OIi=:=:l
A.o---------~==::j

.J

A'D o--------I~==t____

COLUMN

DOo O______~~~----r_----~~3-~I/:o~a:R:C:u:rrs~~~~~nn
F
DO,o-----~+_t>--__1

A7

Vee

A.

A.

A,

A.

A.

A'D

A3

A"

A.

DOD

A,

DO,

AD

DO.
DOo

E

DOoo--~rr~-~

W

Vss

DOoo-~~++~--_4

Eo-.....,"'"

[1~ At
~1! Al0

w~~~----------------~

(TOI' YEW)

~1.6 AI1

:1':; 1/01
014 1/02

~1!

Absolut. M.xlmum R.tlngs
(See Note)

1/03

.;.R;;;••tl.n;.'ljg:..._ _ _ _ _ _ _ _ _ _ _ _ _....;;;S;:.y;;;m;;;b;,;:o;;.I_ _ _...;V;.;.;;;I,;;;u,;;;._ _ _ _ _ _U,;;;;;;n;.;.it
Supply voltage

-0.5 to +7

V

Input voltage on
any pin with
respect to GND

Vce

-3.5 to +7

V

Output voltage on
any 1/0 pin
with respect to GND

-0.5 to +7

V

Output current

±20

mA

Power dissipation

1.0

w

-10 to +85

'C

Temperature under bias
Storage temperature

TB1AS
Ceramic

-65 to +150

Plastic

-45 to +125

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

FUJITSU
3-40

MB81C69A·25

Recommended Operating
Conditions
(Referenced to Vss)

Parameter

Symbol

Min

Typ

Max

Supply voltage

Vcc

4.5

5.0

5.5

Unit
V

Input low voltage

VIL

-0.5'1

0.8

V

Input high voltage

VIH

2.2

6.0

V

Ambient temperature

TA

0

70

°C

Note: "' -2.0V min. for pulse width less than 20 ns.

Capacitance
(TA = 25°C, f = 1 MHz)

Parameter

Symbol

= OV)
Input capacitance (VE§ = OV)

CIN

Input capacitance (VIN

DQ capacitance (Vila

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

= OV)

Typ

CliO

Parameter

Test Condition

Symbol

Active supply current

= 0 mA
lOUT = 0 mA, cycle = min.
VIN = OV to Vcc
E = VIH, Vila = OV to Vcc
IOL = 8 mA
IOH = -4mA

Icc1

Operating supply current
Input leakage current
Output leakage current
Output low voltage
Output high voltage

lOUT

3-41

Max

Unit

5

pF

6

pF

7

pF

Min

Icc2
III

-10

ILO

-10

VOL
VOH

2.4

Max

Unit

50

mA

70

mA

10

/LA

10

/LA

0.4

V
V

MB81C69A.2S

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle
Parameter

Symbol

MB81C69A·25
Min

Read cycle time

TAVAX

25

Address access time

TAVQV

Max

Unit

25

ns

15

ns

ns

Chip select access time

TELQV

Output hold from address change

TAXQX

3

ns

Output hold from E

TEXQX

0

ns

Chip enable to output
inlow-Z

TELQX

3

ns

Chip deselection to output
in high-Z

TEHQZ

10

ns

R_d Cycle Timing Dlagram"1
Read Cycle: Address Controlled'2

~~'--------------TAVAX--------------~~~
ADDRESS

-------I~~~~~~~~~~~~-TA-V-Q-V~~~~-----~-.~I-----------/~,

...

Q

Read Cycle:

PREVIOUS
DATA VAllO

DATA VALID

E Controlled'3
~---------------TAVAX--------------~.~

DATA VALID

Q

NOTES: '1 W IS HIGH FOR READ CYCLE.
'2 DEVICE IS CONnNUOUSLY SELECTED, E = V,L.
'3 ADDRESS VALID PRIOR TO OR COINCIDENT WITH E TRANsmON LOW.

FUJITSU

3-42

HIGH-Z

MBB1C69A·25

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle
Parameter

Symbol

MBB1C69A·25
Min

Write cycle time

TAVAV

25

ns

Chip enable to
end of write

TE1WH

20

ns

Address valid to
end of write

TAVWH

20

ns

Address setup time

TAVWL
TAVEL

0

ns

Write pulse width

TWLWH

20

ns

Data setup time

TDVWH

13

ns

Write recovery time

TWHAX
TEHAX

2

ns

Data hold time

TWHDX

0

Output high-Z from W

TWLOZ

Output low-Z from W

TWHOX

Write Cycle:

Max

Unit

ns
10

ns

5

ns

iii Controlled'4.S
TAVAX

ADDRESS

TAVWH

E
TAVWH

TWLWH

iii

D

Q

NOTE: '4 IF E GOES HIGH SIMULTANEOUSLY WITH W HIGH, THE OUTPUT REMAINS IN A
HIGH IMPEDANCE STATE.
's E OR W MUST BE HIGH DURING AODRESS TRANSITIONS.

3-43

m

m

DON'TCARE
UNDEFINED

MB81C69A.25

AC Charactet'lstlcs
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle:

E Controlled'6.7
~--------------------TAVAX--------------------~

ADORESS

TAVEL

~---------------TEIWH~:::======:r____...j TEHAX
TAVWH

I_---TWLWH-----..;.-I

~TDVWH----~_----~

D

Q

_ _ _ _T_EL_QX_.....
_ _. t - T W - L - Q Z - - - - - - H I G H . z - - - - - - - - - - -

NOTE: *6 IF ~ GOES HtGH SIMULTANEOUSLY

wmt W HIGH, THE OUTPUT REMAINS IN A

HIGH IMPEDANCE STATE.
.
'7 E OR W MUST BE HIGH DURING ADDRESS TRANsmONS.

AC Test Condition
Input Pulse Levels:
Input Pulse Rise And Fall Times:
Timing Reference Levels:
Output Load:

OV to 3.0V
5 ns (Transient Time between O.BV and 2.2V)
Input: 1.5V
Output: 1.5V

5.0V

480ll

Q

Cl! 30 pF
Cl' 5 pF FOR TELQX. TEHQZ.
TWHQX AND TWLQZ

--.-----+
Cl

(INCLUDING SCOPE AND
FIXTURE CAPACITANCE)

I

255.0

-=-

FUJITSU
3-44

l7J DON·T CARE

m

UNDEFINED

MB81C88A.25

Paoka•• Dlm.nslons
Dimensions in inches
(millimeters)

........ Ceramic (CERDIPt Dualln·Lln. Paoka••
(Case 110.. DlP-2OC-COat

~i~~~=~~~J1~
1.000(25.4)

........ Plastic Dualln.Llne Packa••
(Case ..... DI...2OP-1I01t

.290(7.37)
.310(7.87)

.008(0.20)
.012(0.30)

W
-t-l

172(4.36)MAX

11 8(3.o)MlN

.1l1li(2.54)

TfP

.020(0.51)MlN

3-45

I

Preliminary

FUJITSU

MOS Memories
•

M881 C71-45, MB81 C71-55
65,536-Bit Static Random
Access Memory with Separate
Data Input, Data Output and
Automatic Power Down

Description
The Fujitsu MB81C71 Is a 65,536 word x 1-bit static random access memory fabricated with CMOS technology. It uses fully static
circuitry throughout and therefore requires no clocks or refreshing
to operate.
The MB81C71 is designed for memory applications where high
performance, low cost, large bit storl!ge and simple interfacing are
required.
All pins are TTL compatible and a single + 5 voH power supply is
required.

~~

-

.~~~

-

Features
• Organization
65,536 words x 1-blt
• Static operation: no clocks
or refresh required
• Fast access time:
TAVQV TELQV
45 ns max.
(MB81C71-45)
TELQV
TAVQV
55 nsmax.
(MB61C71-55)
• SIngle +5V supply
±10% tolerance
• Separste data Input and
output
• TTL compatible Inputs and
outputs

=

=

=

=

• Three-stata output with
OR-tie capability
• Chip enable for almpllfled
memory expsnslon, automatic
power down
• All Inputs and output have protection against static chsrge
• Standard 300 mil. width
22-pln Dual In-Line package
• Standard 22-pad LCC package

This device contains circuitry tq
protect the inputs against damage
due to high static voltages or elec-

tric fields. However, It is advised
that normal precautions be taken to
a~d application of any voltage
higher than maximum rated voltages to this high Impedance circuit.

3-46

~

MB81C71-45
MB81C71·55

MB81C71 Block Diagram
and Pin Assignments

Ao
A,
A2
A3
As
As
A7

.....- Vee

CELL
ARRAY
256 ROWS
256 COLUMNS

ROW
SELECT

-+- Vss

A,

Vee

A3

As
A,

A2
A,

As

A14

A1S

A'3
Au

Al1

A.

D

COLUMN I/O CIRCUITS
INPUT
DATA
CONT.

Q

Q

COLUMN SELECT

Vi

As

A.

A,.
A,

Vi

D

Voo

E

E

TRUTH TABLE
E
W MODE
H
X
NOT SELECTED
L
L WRITE
L
H
READ

Absolute Maximum Ratings
(See Note)

OUTPUT
HIGtf..Z

HIGH·Z
Q

POWER
STANDBY
ACTIVE
ACTIVE

Rating

Symbol

Value

Unit

Supply voltage

Vee

-0.5 to +7

V

Input voltage on any pin
with reference to Vss

VIN

-3.5* to +7

V

Output voltage on any pin
with reference to Vss

VOUT

-0.5 to +7

V

Output cUlTent

lOUT

±50

mA

Power dissipation

Po

1.0

W

Temperature under bias

TBIAS

-10 to +85

·C

Storage temperature

TSTG

Ceramic

-65 to +150

Plastic

-45 to +125

·C

*DC: min. = -O.SV

Note: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed In the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

FUJITSU
347

MB81C71·45
MB81C71·55

Recommended Operating
Conditions
(Relerenced to Vss )

Parameter

Syinllol

Supply voltage

Vee

....
4.5

!!!
5.0

Max

Unit

5.5

V
V

Input low voltage

VIL

-0.5"

0.8

Input high voltage

V IH

2.2

6.0

V

Ambient temperature

TA

0

70

·C

Note: *-3.0V min. for pulse width less than 20 ns.

Capacitance
(TA = 25·C, I = 1 MHz)

Parameter

Max

Unit

Input capacitance (V IN = OV)

5

pF

E capacitance (VIN = OV)

8

pF

Output capacitance (Vour = OV)

8

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Test ConditIMs

SYIMoi

111ft

Input leakage current

VIN = OV to Vee
Vee = max.

lu

ILO

~ = VIH ,

Output leakage current

Vour = OV to 4.5
Vee =max.

Operating power supply
current

E = VIL, Vee =

Typ

Max

Unit

-10

10

/LA

-SO

50

/LA

80

mA

max.
I
lOUT = 0 mA, cycle = min. ee

~ = min. to max.

= Vee -0.2V
VIN .. O.2Vor
VIN ;;. Vee -0.2V

ISSI

~e = min.'to max.
= VIH

1882

Output low voltage

10L = 16mA

VOL

Output high voltage

10H = -4mA

VOH

Peak power on current

~e = 0 to Vee min.
= lower of Vee
orVIH min.

IPO

Standby current

3-48

15
mA
25
0.45
2.4

V
V

30

mA

MB81C71·45
MB81C71·55

AC Characteristics
(Recommended operating
conditions unless otherwise
noted,)

Read Cycle

Parameter

Symbol

MB81C71·45
Min
Max

MB81C71.55
Min
Max

Unit

Read cycle time'1

TAVAX

45

55

ns

Address access time

TAVOV

45

55

Chip enable access time'2

TELOV

45

55

Output hold from address change

TAXOX

5

Chip enable to output in IOW_Z'3"

TELOX

5

Chip enable to output in high-Z'3,4

TEHOZ

0

Chip enable to power up time

TELIH

0

Chip enable to power down

TEHIL

Nota: *1
*2
*3
·4

ns
ns

5

ns

5
25

ns

0

30

ns

0

ns

40

35

ns

All read cycles are determined from the last valid address transitioning to the first address transitioning of next cycle.
Chip enable for a finite time Is less than TAVAX prior to selection.
Transition Is measured at the point of ±500 mV from steady state voltage.
This parameter is measured with the loading specified in Figure 1.

Read Cycle Timing Diagrams
Read Cycle: Address Controlled'1

'2

ADDRESS

~-----TAvav

a

DATA VALID

Read Cycle: i Controlled'2
TAVAX

~

1\

/

~

TELav

~ TELax""'I.
HIGH,Z

a

1Jt.

~TEHaz",'-

/

1\

DATA VALID

Icc

ISO

_1-

--

~TELIH

I--TEHIL

---

l7i(l , UNDEFINED
*2 W IS HIGH TO READ CYCLES.
'3 TRANSITION IS MEASURED AT THE POINT OF ±500 mV FROM STEADY STATE VOLTAGE.

• , THIS PARAMETER IS MEASURED WITH THE LOADING SPECIFIED IN FIGURE 1,

3-49

---

=1:,----50%

NOTES, '1 E,IS LOW,

FUJITSU

HIGH-Z

V

\

m'

DON'T CARE

MB81C71-4S
MB81C71·S5

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle

Parameter

Symbol

MB81C71·45
Min
Max

MB81C71·55
Min
Max

Write cycle time

TAVAX

45

55

ns

Chip enable to end of wr~e

TELWH

40

50

ns

Unit

Address valid to end of write

TAVWH

40

50

ns

Address setup time

TAVWL

5

5

ns

Address setup time

TAVEL

0

0

ns

Write pulse width

TWLWH

30

ns

Data valid to end of write

TDVWH

25

35
30

Write recovery time

TWHAX

5

5

ns

Data hold time

TWHDX

0

0

ns

Write enable to output in high-Z'l '2

TWLOZ

0

Output active from end of write'l '2

TWHOX

0

25

ns

0

30

0

Notea: "1 Transition Is measured at the point of ±500 mV from steady state vohage.
·2 This parameter Is measured with the loading specified in Figure 1.

Write Cycle Timing Diagrams
Write Cycle: iii Controllecf1

ADDRESS

TDVWH

D

--~~.....-<~

TWHDX

DATA VALID

1+---1 TWHQX'2.'3
HIGH-Z

Q

f,2Qg:

UNDEFINED
NOTE: '1 E OR Vi MUST BE HIGH DURING ADDRESS TRANSmONS.
'2 TRANSITION IS MEASURED AT THE POINT OF ±500 mV FROM STEADY STATE VOLTAGE.
'3 THIS PARAMETER IS MEASURED WITH THE LOADING SPECIFIED IN FIGURE 1.

3·50

ns
ns

~: DON'T CARE

MB81C71045
MB81C71·55

AC Characteristics
(continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Dlagram'1
Write Cycle:

E Controlled
~-----------------"TAVAX----------------~~

ADDRESS

-1--------- TELWH

------------.1

~--------TWlWH-------~

~------TDVWH-----~

o

DATA VALID

HIGH·Z

Q

[XX1 : UNDEFINED
NOTES, • ALL WRITE CYCLES ARE DETERMINED FROM LAST VALID ADDRESS
TRANSITIONING TO THE FIRST ADDRESS TRANSITIONING OF NEXT CYCLE.
·1

E OR Vi MUST BE

HIGH DURING ADDRESS TRANSITIONS.

'2 TRANSITION IS MEASURED AT THE POINT OF ± 0.5 v FROM STEADY STATE VOLTAGE.
'3 THIS PARAMETER IS MEASURED WITH THE LOADING SPECIFIED IN FIGURE 1.

AC Test Conditions
Input pulse levels:
O.6V to 2.4V
Input pulse rise and fall times:
5 ns
Timing measurement reference levels: Input: 1.5V
Output: 1.5V

2V

b

,Jr
T

Cl

(INCLUDING PROBE AND S:AY CAPACITANCE)
'CL'30 pF FOR ALL EXCEPT TEHQZ, TWHQZ, TELQZ, TWHQX
5 PI FOR TEHQZ, TWHQZ, TELQZ, TWHQX.

Figure 1. Output Loading

FUJITSU
3·51

rz2l ' DON'T CARE

MB81C71045
MB81C71·55

Package Dimensions
Dimensions in inches
(millimeters)

22·Lead Ceramic (Metal Seal) Dual In·Llne Package
(Case No.: DIP-22C·A02)

1~045(1.14)MAX

~

I II

.090(2.29)
.110(2.79)

~

•.042(1.09)
.054(1.37)

-II •.

.200(5.08)MAX

__~ ~-W:::~~

015(0.38)
.023(0.58)

.020(0.51)
.050(1.27)

1.00D(25AO)REF

22·Lead Plastic Dual In·Llne Package
(Case No.: DIP.22P.M02)

EJECTOR MARK

~6.35)

INDEX·l

.270(6.85)

INDEX-2

~nT~nT~nT~~
1.052(26.73)
1.077(27.38)

.050(1.27)MAX
.183(4.66)MAX

.118(3.0)MIN

.100(2.54)1

.020(0.51 )MIN

TYP

3·52

MB81C71-45
MB81C71·55

Packaga Dimensions
(Continued)
Dimensions in inches
(millimeters)

22·Pad Ceramic IMetal Seal) Leadle •• Chip Carrier
ICase No.: LCC·22C·A01)
.. '9S(4.95)TVP. ..

PIN NQ 1 INDEX

.045(1.14)

\

fP.

.485(12.32)
.505(12.83)

R.OO8(O.20)TYP.
(22 PLeS)

.0975(2.48)

~

..

.280(7.11)
.295(7.49)

oi0675(~~

.. I

3-53

Advanced Information
MOS Memories
•

MB81C74-25, MB81C74-35

64K Bit CMOS Static
Random Access Memory

Description
The Fujitsu MBal C74 is a 16K word by 4-bit static random
access memory fabricated using MIX-MOS technology. The
memory utilizes asynchronous circuitry and requires no
clock or timing strobe. All pins are TTL compatible and a
single +5 volt power supply is required.
Features
•
•
•

Organization:
16K words x 4-bits
Static operation: no clocks
or timing strobe required
Fast Access Time:
TAVQV = 25ns
(MB81 C74-25)
TAVQV = 35ns
(MB81C74-35)

A

vee

A

A

A

A

A

A

A

A

A

A

A
A

A

E
•

Low Power Consumption
605 mW max. (active)
138 mW max. (standby)

•

Single +5 volt ±10% supply

•

TTL compatible inputs and outputs

•

NMOS ceil and CMOS periphery

• Common 1/0
•

.22 pin DIP (300mil)

3-54

FUJITSU

MOS Memories
•

MB81C78·45, MB81C78·55
CMOS 6S,S36-Bit Static
Random Access Memory

Deacrlptlon
The Fujitsu MB81C78 is a 8,192.word x 8-bit static random access
memory fabricated wHh a CMOS process. The memory utilizes
asynchronous circuHry and may be maintained in any state for an
indefinite period of time. All pins are TTL compatible and a single
+5 volt power supply is required.
A separate chip enable (E,) pin simplifies multipackage systems
design. It permHs the selection of an individual package when outputs are OR-tied, and furthermore on selecting a single package by
E1, the other deselected devices are automatically powered down.
The MB8l C78 offers the advantages of lower power dissipation,
low cost, and high performance.

F••tur.a
•

Organlzstlon:
8192 worda x 8-blts
StstIc opsrstlon:
no clocks or timing strobe
required
• Fast accesa time:
TAVQV = TELQV = 45 na max.
(MB81 C78-45)
TAVQV
TELQV
55 na max.
(MB81 C78-55)
• Low power conaumptlon:
880 mW max. (Operating)
138 mW max. (Standby)
• Single +5V supply
±10% tolsrsnce
•

=

=

• TTL compatible Inputs and
outputs
• Three-state outputs with
OR-tie capability
• Chip enable for Simplified
memory expansion, automatic
power down
• All Inputs and outputs have
protection against ststlc
charge
• Standard 28-pln DIP packsge

This device contains circuitry to
protect 111. Inputs againet damage

due to high static voltages or aectric fields. However, It Is advised
that normal precautions ba taken to
avoid applcatlon of any voltage
higher than maximum rated vollages to this high impedance circuit.

3-55

V~

7:-~. ,

-

"

~•i~(l
:..1m ~ -

,,',- ~iM

~~'(.

Ii

M88tC7S....
M881C78·.5

M8S1C78 Block Diagram
and Pin Assignment

Ao

Vee
Vss

A,
A.

256x32x8

A,

MEMORY CELL
ARRAY

II<
A,
At;
A7

Ao
Ao

110 GATE
&
COLUMN DECODER

A,.

A"
A12o-1--.__}---------~----------------_,J

G
E

iii

E'5

NC

vee

At;

IV

At;

E.

Ao

Az

A7

A,

At
At

Ao
G

A,.

Az

Au

E,

A,.

00,

DOe

DOe

DO,

DO.

00.

DO.

Vss

DOs

DO. DO, DOs DOs DOe DO. DOe DOt

E2

E'

POWER
DOWN

TRUTH TABLE
E2

G

MODE

X

H

X

X

STANDBY

ISB

HIGH-Z

X

L

L

X

DESELECT

ICC

HIOH-Z

H

L

H

H

OUT DISABLE

ICC

HIGH-Z

H

L

H

L

READ

ICC

OUT

L

L

H

X

WRITE

ICC

IN

W E,

SUPPLY CURRENT

DQSTATE

Ab80lute Maximum Ratings
(Sse Note)

Rating

.,mbal

Value

Unit

Supply voltage

Vee

-0.5 to +7

V

Input voltage on any pin
with respect to GND

VIN

-3.5 to +7

V

Output voltage on any DQ
pin with respect to GND

VOUT

-0.5 to +7

V

Output current

lOUT

±20

mA

Power dissipation

Po

1.0

W

-10 to +85

·C

-65 to +150

·C

Temperature under bias

TBIAS

Storage temperature

TSTG

Ceramic

Note: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Func:lional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absofuIe maximum rating concltlons for extended periods
may affecl_ reliability.

FUJITSU

3·56

MB81C78·45
MB81C78·55

Recommended Operating
Conditions

Parameter

Symbol

Min

Typ

Max

Unit

(Referenced to Vss )

Supply voltage

Vee

4.5

5.0

5.5

V

Input low voltage"

VIL

-0.5

0.8

V

Input high voltage

VIH

2.2

6.0

V

Ambient temperature'2

TA

a

70

'C

Not•• : *1 -2.0V min. for pulse width less than 20 ns.
(Vll min. = -O.5V at DC level)

"'2 The operating ambient temperature range is guaranteed with transverse airflow exceed 2 m/sec.

Capacitance
(TA = 25'C, 1 = 1 MHz)

Typ

Max

Parameter

Symbol

l!]Jut ca~c~nce (VIN = OV)
(E" E2, G, W)

CIN'

7

Input capacitance (VIN = OV)
(other inputs)

CIN2

6

DQ capacitance (VI/O = OV)

COUT

8

Unit

pF

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Test Condition

Symbol

Min

Max

Unit

Input leakage current

VIN = OV to Vee

III

-10

10

/LA

Output leakage current

E,..:' VIH or E2 = VIL or W = VIL
or G = VIH ' VOUT = OV to Vee

ILO

-10

10

/LA

Operating supply eurrent

Standby supply current

E,

= V IL

1/0 = open, cycle = min.

lee

120

mA

Vee = min. to max. E, = Vee - 0.2
VIN '" 0.2V or VIN "" Vee - 0.2V

19B ,

15

mA

Vee = min. to max.
= V IH

ISB2

25

rnA

0.4

1::,
Output low voltage

IOL=8mA

VOL

Output high voltage

IOH = -4 mA

VOH

Peak power-on current

~ee = OV to Vee min.

E, = lower 01 Vee or VIH min.

3-57

Ipo

2.4

V
V

50

mA

Ma8iC78·45
M88iC78·55

AC Ch.r.ct.....tfc.
(Recommended operating
conditions unless otherwise
noted.)

Re.dCycle"
P.r.meter

Symbol

Ma8iC78-45
Min
M ••

Ma8iC78·55
Min
M ••

Unit

Read cycle time

TAVAX

45

55

ns

Address access time'2

TAVOV

45

55

Chip enable access time'3

TE1LOV

45

55

ns

Chip enable access time'3

TE2HOV

30

40

ns

Output hold from
address change

TAXOX

5

5

ns

Output enable to output valid

TGLOV

Output active from chip select '4,5

TEl LOX

Output active from chip select '4,5

TE2HOX

5

5

ns

Output active from
output enable '4,5

TGLOZ

0

0

ns

Output disable from chip enable '4.5

TE1LOZ

25

30

ns

Output disable from chip enable'4,5

TE2HOZ

25

30

ns

Output disable from
output enable'4,5

TGHOZ

25

30

ns

Notes: *1
*2
"3
*4
*5

20

ns

25
10

10

Wis high for read cycle.
Device is continuously selected, E1 = V,LI E2 = V,H and (§ == V,L'
Address valid prlor to or coincident with ~1 transition low. 'C"S"2 transition high.
Transition is measured at the point of ±500 mV from steady state voltage.
This parameter is measured with speclfied Load II in Fig. 2.

Re.d Cycle Timing Di.gr.m"
Re.d Cycle: Addre•• Controlled'2

~~~---------------TAVAX--------------~~~

ADDRESS

DATA OUT

-{""o---------- - - -T.-AV-Q-V~ ~-=- - - - - ~ ------------~1_
..
--,

PREVIOUS DATA VAUD

NOTES: " Vi IS HIGH FOR READ CYCLE.
'2 DEVICE IS CON11NUOUSLY SELECTED. il,

FUJITSU
3-58

DATA VALID

= V,L. Eo = v,•• ii = V,L.

ns
ns

MB81C78·45
MB81C78·55

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle Timing Diagram"
Read Cycle:

E, • E2 Controlled'3

ADDRESS

DO

HIGH-Z

NOTES:" iii IS HIGH FOR READ CYCLE.
*3 ADDRESS VAUD PRIOR TO OR COINCIDENT WITH E1 TRANSITION LOW E2
TRANsmON HIGH.
'4 TRANsmDN IS MEASURED AT THE POINT OF ,,500 mV FROM STEADY STATE
VOLTAGE.
'5 THIS PARAMETER IS MEASURED WITH SPECIFIED LOAD II IN FIG. 2.

3-59

fZ21 DON'T CARE
rxzl UNDEFINED

MB81C78.45
MB81C78·55

AC Characteristics
(Continued)
(Recommended operating
conditions unless otharwise
noted.)

Write Cvcle"'

Parameter

Svmbol

MB81C78·45
Min
Max

MB81C78·55
Min
Max

Unit

Write cycle time"2

TAVAX

45

55

ns

Chip enable to
end of write

TE1LE1H

40

45

TE2HE2L

25

30

Address valid to end of write

TAVWH

40

45

Address setup time

TAVWL

5

5

ns

Write pulse width

TWLWH

25

30

ns

Data setup time

TDVWH

25

30

ns

Write recovery time'3

TWHAX, TE1HAX, TE2LAX

5

5

ns

Data hold time

TWHDX

0

Output high-Z from W'4,5

TWLOZ

Output low-Z from W'4,5

TWHOX

3-60

ns
20

0

Notea: *1 If E1 goes high simultaneously with iii high, the output remains In high impedance state.
*2 All write cycles are determined from the last address transition to the first address transition of next address.
"'3 TWHAX is defined from the end point of write mode.
.
"'4 Transition is measured at the point of +500 mV from steady state voltage.
"'5 This parameter is measured with spec/fled Load II in Fig. 2.

FUJITSU

ns

0
20

0

ns

ns
ns

MB81C78·45
MB81C78·55

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Diagram"
Write Cycle 1

(E,.

E2 Controlled)

!-+---------TAVAX'2----------!

ADDRESS

~--------

TAYWH

-------~

+1-------- TE1LE1H

------iO"",,-----<~

E,

,.....--+--'.:==-~---- TE2HE2L

-----.f------I

E2

DQ

-TWHQX'4.'.

NOTE: 'I IF G, E, AND E2 ARE IN THE READ MODE DURING THIS PERIOD, DQ PINS ARE IN
THE OUTPUT STATE SO THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE
OUTPUTS MUST NOT BE APPUED.
'2 ALL WRITE CYCLES ARE DETERMINED FROM THE LAST ADDRESS TRANSITION OF NEXT ADDRESS.
·3 tWA IS DEFINED FROM THE END POINT OF WRITE MODE.
'4 TRANSITION IS MEASURED AT THE POINT OF ± 0.5 Y FROM STEADY ST ATE VOLTAGE.
'5 THIS PARAMETER IS SPECIFIED WITH LOAD II.

~ UNDEFINED

t22I DON'T CARE

3-61

MB81C78·45
MB81C78·55

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Dlagram'l
Write Cycle 2 ,W Controlled)

!+---------TAVAX'2-----------+!
ADDRESS

E,

DQ

~H~' 5~T~ ~A~Es~ ~!T

s~~=~~~ ;'~~~~~E ~~~~ST~~I:

Ri:J'I:r?.JrE
OUTPUTS MUST NOT BE APPUED.
'2 ALL WRITE CYCLES ARE DETERMINED FROM THE LAST ADDRESS TRANSITION TO
THE FIRST ADDRESS TRANSITION OF NEXT ADDRESS.
'3 lWR IS DEFINED FROM THE END POINT OF WRITE MODE.
'4 TRANSITION IS MEASURED AT THE POINT OF ± 500 mV FROM STEADY STATE VOLTAGE.
'5 THIS PARAMETER IS SPECIFIED WITH LOAD II.

NOTE: '1

~

AC Test Conditions
Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Measurement Reference Levels:

O.SV to 2.4V
5 ns (Transient time between O.SV and 2.2V)
Input:
1.5V
Output: 1.5V

Output Load I.

Output Load II.

For all except TE1LQH, TE2HQH,
TE2LQL, TE2HQL, TWLHQZ, TWHLQZ

For TE1LQH, TE2HQH, TE2LQL, TE2HQL,
TWLHQZ, TWHLQZ
5V

5V

48Ol1

48011
Q

--.---<

Q

--,----i
25511

25511

(INCLUDING SCOPE
AND PROBE CAPACITANCE)

(INCLUDING SCOPE
AND PROBE CAPACITANCE)

FUJITSU
3-62

UNDEfiNED

MB8iC78·41
MB8iC78·11

Package Dlmen.lon.
Dimensions in inches
(millimeters)

28·Lead Ceramic (CERDIP) Dual In· Line Package
(Ca.e No•• DIP-28C·C02)

.010(2.29)
.110(2.79)

~----------·I~~~3~3~.0~~"R~EF~-------ff~
.013(0.33)

.023(0.58)

3·63

FUJITSU

MOS Memories
•

MB81 C79-45, MB81 C79-55
73,728-Bit Static Random
Access Memory with
Automatic Power Down

The Fujitsu MB81 C79 is an 8,192 words x 9-bits static random access memory with a CMOS process. The ninth bit optimizes parity
check. The memory utilizes asynchronous circuitry and may be
maintained in any state for an indefinite period of time. All pins are
TTL compatible and a single, +5 volt power supply is required.
A separate chip enable (£:1) pin simplifies multipackage systems
design. It permits the selection of an individual device when outputs or OR-tied, and furthermore on selecting a single device by 1:1
the other deselected devices are automatically powered down.
The MB81C79 offers the advantages of low power dissipation, low
cost, and high performance.

Features
• Organization:
8,192 words x 9-blta
• StatIc operation:
no clocka or timing strobe
required
• Fast access time:
TAVQV = TELQV =
45 ns max.
o

(MB81C79-45)
TELQV
TAVQV
55 ns max.
(MI381C79-55)

=

=

• Low power consumption:
660 mW msx. (Operating)
138 mW max. (Standby)
• Single +5V power supply

• TTL compatible inputs and
outputa
• Three-state outputa with
OR-tie capability
• Chip enable for simplified
memory expansion, automatic
power down
• All Inputs and outputs have
protection against static
charge
• Standard 2B-pln DIP
package
• Also available In 2B-pln
ceramic LCC and
ceramic Flatpack

This device contains circuitry to

protect the inputs against damage
due to high static voltages or electric flefds. However. It Is advised

that normal precautions be taken to
avoid application of any vottage
higher than maximum rated voltages to this high impedance circuit.

3-64

MB81C79·45
MB81C79·55

MB81C79 Block Dia9ram
and Pin Assignments

Ao
A,

Vee
V..

A,

256x32x9
MEMORY CELL
ARRAY

As

A<

Vee

A,

W

A.

E,

A,

A,

As

As

A,

A,

A.

A.

A<
A,

As
As

&

COLUMN DECODER

A"

A"o-1--r__}---------~----------------_,J

el

A"

As

A"

E,

DOo

DOs

DO,

DO,

110 GATE

A,.

A,.

DO,

DOs

Do,

DO,

Vss

DO,

iN

DOo DO, DO, Do, DO,DO, DOooo,DOa

E,

W
A,

E,

E,

As

A,

A,

A,
A.
NC

As
As

TRUTH TABLE
W

E,

E.

G

MODE

X
X
H
H
L

H
L
L
L
L

X
L
H
H
H

X
X
H
L
X

STANDBY
DESELECT
OUT DISABLE
READ
WRITE

SUPPLY CURRENT

DQSTATE
HIGH-2
HIGH·Z
HIGH-Z
OUT
IN

ISB
ICC
ICC
ICC
ICC

A,.

TOP VIEW

G
A,

A"

E,

A"
DClo
DO,

DOs
DO,

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Supply voltage

Vee

-0.5 to +7

V

Input voltage on any pin
with respect to Vss

VIN

-3.5 to +7

V

Output voltage on any D/Q
pin with respect to Vss

VOUT

-0.5 to +7

V
mA

Output current

lOUT

±20

Power dissipation

Po

1.0

W

Temperature under bias

TBIAS

-10 to +85

Storage temperature

TSTG

-65 to 150

·C
·C

Note: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data. sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

FUJITSU
3·65

MB81C7....5
MB81C78-55

Recommended Operating
Conditions

Parameter

Symbol

Min

Typ

Max

Unit

(Referenced to Vss )

Supply voltage

Vee

4.5

5.0

5.5

V

Input low voltage

V IL

-2.0"'

0.8

V

Input high voltage

V IH

2.2

6.0

V

Ambient temperature

TA"2

0

70

'c

Max

Unit

Notes: *1 -2.0V min. for pulse width less than 20 ns (VIL min. = -O.5V at DC LEVEL).
~2

Capacitance
(TA = 25'C, f = 1 MHz)

The operating ambient temperature range is guaranteed with transverse airflow exceed 2rntsec.

Parameter

Symbol

I!!put callilciJ!lnce (VIN = OV)
(E" E2, G, W)

Typ

CIN'

7

Input capacitance (VIN = OV)
(other inputs)

CIN2

6

D/Q capacitance (VI/O = OV)

COUT

8

pF

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Symbol

Min

Max

Unit

III

-10

10

",A

G = VIH, VOUT = OV to Vee

ILO

-10

10

",A

~ = V IL
D/Q = open, cycle = min.

lee

120

rnA

Vee = min. to max.
V IN = OV or Vee

Parameter

Test Condition

Input leakage
current

V IN

Output leakage
current
Operating supply
current

E,

= OV to Vee
=

VIH or E2 = V IL or

ISB'

15

rnA

E, = V IH

ISB2

25

rnA

Ouptut low
voltage

IOL=8mA

VOL

0.4

V

Output high
voltage

IOH = -4 rnA

V OH

Peak power-on
current

~e = OV to Vee min.
, = lower of Vee or V IH min.

Ipo

Standby supply
current

3·66

V

2.4
50

rnA

M881C78-45
MB81C78-55

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle

Parameter

Symbol

MB81C79-45
Min
Max

MB81C79-55
Min
Max

Unit

Read cycle time

TAVAX

45

55

ns

Address access time

TAVOV

45

55

ns

Chip enable access
time

TELOV

45

55

ns

TE2HOV

30

40

Output hold from
address change

TAXOX

Output enable
to output valid

TGLOV

Output active
from chip select
Ou1put active
from output enable
Output disable
from chip enable
Output disable
from outpu1 enable

5

20

25

TEl LOX

10

10

TE2HOX

5

5

TGLOX

0

0

ns
ns

5

ns
ns
ns

TE1HOZ

25

30

TE2LOZ

25

30

TGHOZ

25

30

ns
ns

Read Cycle Timing Diagrams *1
R_d Cycle: Address Controlled*2
~--------~VAX--------~

~/r------------------'\I
ADDRESS

Ir-..'--_ _ __

-.-I \
~----~vov------~

_

TAXQX

PREVIOUS DATA VALID
\ /
DATA VALID
\V
_ _ _ _ _ _ _ _..J/\'--_ _ _ _-J1r-..'--_ __

DATA OUT 0

N....' "1 W IS HIGH FOR READ CYCLE.
"2 DEVICE IS CONTINUOUSLY SELECTED, E, = V'L, E2 = VIH'~ = V,L.

FUJITSU
3-67

MB81C79·45
MB81C79·55

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle: &1 Controlled'1.'2

.1

TAVQV

t+------ TE'lQV
,/

\-1\

1

f.- TE'lOZ"."

TE'HOZ'3."
...-

~ ...

-l

E,

/

TE2HQV
~".',

..

~:TE2HQLZ

1\

I-- TE2LOZ"."

TGlQV+

~Ir
1\

-/

I

_ _ TGHQZ·'." _ _

TGLQX',g,"4

HIGH·Z

DIQ

....

~

OUT VALID

Iii IS HIGH FOR READ CYCLE.
'2 ADDRESS VALID PRIQR TQ QR COINCIDENT WITH E, TRANSITION LOW,
E, TRANSITION HIGH.
'3 TRANSITION IS MEASURED AT THE POINT OF ±500 mV FROM STEADY STATE
VOLTAGE.
'4 THIS PARAMETER IS MEASURED WITH SPECIFIED LOADING LOAD II IN FIG. 2.

NOTES: *1

Write Cycle"

rxzJ

UNDEFINED

Parameter

Symbol

MB81C79·45
Min
Max

MB81C79·55
Min
Max

Unit

Write cycle time'2

TAVAX

45

55

ns

Chip enable to
end of write

TE1LE1H

40

45

TE2HE2L

25

30

Address valid tQ
end of write

TAVWH

40

45

Address setup time

TAVWL

5

5

ns

Write pulse width

TWLWH

25

30

ns

ns
ns

Data setup time

TDVWH

25

30

ns

Write recovery time '3

TWHAX

5

5

ns

Data hold time

TWHDX

0

0

Output high-Z from W'4,5

TWLQZ

Output low-Z from W'4.5

TWHQX

0

0

Notes: *1 If E1 goes high simultaneously with W high, the output remain is high impedance state.
*2 All write cycles are determined from last address transition to the first address transition of next address.
*3 TWHAX is defined from the end point of Write mode.
*4 Transition is measured at the point of ±500 mV from steady state voltage.

*5 This parameter is measured with specified loading load II in Fig. 2.

3·68

ns
20

20

ns
ns

MB81C7....S
MB81C7"SS

AC Characterlatlca
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

WrIte Cycle Timing Diagrama
Write CyclellE lO E2 • Controlledr ' ·2
~----

______________ TAYAX'3 ____________________

~

E,

DIG

NOTES: ., IF it r, AND Eo ARE IN THE IiEAD MODE DURING THIS PERIOD, DIG PINS ARE
IN THE OUTPUT STATE so THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO
THE OUTPUTS MUST NOT BE APPLIED.
"2 IF r, GOES HIGH SIMULTANEOUSLY WITH W HIGH THE OUTPUT REMAIN IN HIGH
IMPEDANCE STATE,
"3 ALL ~E CYCLES ARE DETERMINED FROM LAST ADDRESS TRANSI110N TO
THE FIRST ADDRESS TRANSITION OF THE NEXT ADDRESS.
·4 TWHAX IS DEFINED FROM THE END POINT OF WRITE MODE.
·5 TAAIISITION IS MEASURED AT THE POINT OF "500 mY FROM STEADY STATE

VOLTAGE.
.. THIS Pl\AAMETER IS MEASURED WITH SPECIFIED LOADING LOAD II IN FIG. 2

FWITSU
3-69

~UNDEFtNED

rz.zJ DON'T CARE

Ma8iC?I-4.
Ma8iC?8-••

AC Charact.rlatlca
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Writ. Cycl. II

(ii Controll.dr1.2
!---------TAVAX'3----------!

ADDRESS

E,

D/Q

NOTES: '1 IF ii, £1 AND E, ARE IN THE READ MODE DURING THIS PERIOD, I/O PINS ARE IN
THE OUTPUT STATE SO THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO
THE OUTPUTS MUST NOT BE APPUED.
'2 IF £1 GOES HIGH SIMULTANEOUSLY WITH 'it HIGH THE OUTPUT REMAIN IN HIGH
IMPEDANCE STATE.
'3 ALL WRITE CYCLES ARE DETERMINED FROM LAST ADDRESS TRANSITION TO
THE FIRST ADDRESS TRANSITION OF THE NEXT ADDRESS.
'4 TWHAX IS DEFINED FROM THE END POINT OF WRITE MODE.
'5 TRANSITION IS MEASURED AT THE POINT OF ±500 mY FROM STEADY STATE
VOLTAGE.
'6 THIS PARAMETER IS MEASURED WITH SPECIFIED LOADING LOAD II IN FIG. 2.

3·70

~UNDEFINED

m

DON"TCARE

MB81C79·45
MB81C79·55

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

AC Test Conditions
Input pulse levels:
Input pulse rate and fall times:
Timing measurement reference levels:

O.6V to 2.4V
5 ns (transient time between O.BV and 2.2V)
Input: 1.5V
Output: 1.5V

Output Load I.
For all except TEl LOZ, TE1HOZ
TWLOZ, TWHOX, TGHOZ,
TGLOX

Output Load II.
For TEl LOZ, TEl HOZ, TGHOZ,
TGLOX, TWLOZ, TWHOX
5V

5V

48011

48011

0--,----+

O-~---1
25511

]

255!1

(INCLUDING SCOPE
AND FIXTURE CAPACITANCE)

(INCWDlNG SCOPE
AND FIXTURE CAPACITANCE)

Packa.e Dimensions
Dimensions in inches
(millimeters)

rn

280Lead Ceramic ICERDIP) Dual In·Llne Packa.e
ICase No.: DIP.2SC·C02)

~~--~

1

R.025(O.64)

R~)j i)

.570{14.48)
.585{15.11)

~CrL:Jcrt: L:Jrc:CJrc:L J:r-cL:J r1A35(-CL:J :r-I: :r45. ,)L:J : r1L:J : J" 1CJcr CJ. -.: :r-c~.I'

J~

11. . . . .

1.5OO{38.10)

.090{2.29)
.110{2.79)

foo------:-1,3OO(==33'"'.02)=R=EF=-----t1-+!
.013{G.33)

.023(0.58)

FUJITSU

3·71

T'

.600{15.24)REF

1If;;;;;5,,==="+-_.L

MB8iC79.4S
MB8iC79·55

Packalle Dlm_slons
Dimensions in inches
(millimeters)
(Continued)

32·Pad Ceramic (Metal Seal) Leadless Chip Carrier
(Case No.: LCC·32CoA02)
'PIN 1 INDEX
C.Ol5(O.38)TYP

/

.445(11.30)

.460(11.68)

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

M88iC79 Ceramic Flat Package
(Case No.: FPT.28C·C02)

-----.II
-I"

11.25(.443)
11.89(.468)

TYP

MIN

n fl'1

0.51(.020)

1.27(.050)

0.05(.002)

~~l
-0.38(.015)
0.51(.020)

16.51(.850) REF
17.27(.880)
18.03(.710)

3-72

0.76(.030)
MAX

13.335(.525)

11.81(.465)
12.1 9(.480)

TYP

13.97(.550)
14.27(. 582)

11 1

IJ

0.10(.004) •
0.20(.~

0.80(.0315)
TYP

2.79(.110) MAX

Preliminary

FUJITSU

MOS Memories
•

MB81 C88-55, MB81 C88-70
65,536 Words x 4-Bits CMOS
Static RAM with Automatic Power Down

Description
The Fujitsu MB81 C86 is a 65,536 word by 4-bit Static Random
Access Memory fabricated with a CMOS silicon gate process .
The memory utilizes asynchronous circuitry and may be
maintained in any state for an indefinite period of time. All pins
are TTL compatible, and a single +5 volt power supply is
required.
The MB81C86 is ideally suited for use in large computer
systems where fast access time and ease of use are required.
The MB81C86 offers the advantages of low power dissipation,
low cost, and high performance.

• Organization:
65,536 words x 4-blll
• Fast Access TIme:
TAVQV = TELQV = 55ns
max. MB81C86-55
TAVQV TELQV 70ns
max. MB81C86-70
• Completely Static
Operation
No Clock Required
• TTL Compatible
Input/Output

=

=

-

c-

-

f--f---

-

-

•

• Three State Output
• Separate Data Input/Output
• Single +5 Volt Power
Supply, ±10% Tolerance
• Low Power Standby:
550 mW max. Active
55 mW max. (Standby)
• Available In 28-pln Ceramic
Package (600 mil)
32-pln LCC

...,

'

3-73

r-

M.8iC8S-55
M.8iC8S-70

Block Diagram
& Pin Assignments

--

As

A,
A,
A,

...

ROW
SELECT

As

Vee
Vss

CELL ARRAY
512 ROWS

128 COLUMNS
x4

--,
5,

A.
AlO
A11
A"
A13
AM

,-,29
,.,,28

--,

!..J

roi7
,--

7 '
-~

-89 . ,'

, 26

l-'i5
'-'_
'24

TOP VIEW

10-'
_co

A15

11'
12,

-..

"''23
'-'_

D,

f3]

'21
L_

NC

'22
'--

As

A,
As

0

DIN1

DOUT1

DOUT2

DIN2
DIN3

0

DOUT3

DIN4

0

OOUT4

E

A.
A,
As
A.
A,.
A11
A"
A13
AM
A15
D.
D,

Vee

As
As
A,
A,
A,
Ao
D,
D,
0,
0,
0,

o.

E

W 0

'n'uth 'nIble

Absolute Maximum
Ratings

W

Vss

I

W

Mode

Output

Power

H

HIGH-Z

STANDBY

X

NOT SELECTED

L

L

WRITE

HIGH-Z

ACTIVE

L

H

READ

DOUT

ACTIVE

Rating

Symbol

Supply Voltage

Vee

Input Voltage

V1N

Output Voltage

VO UT

Output Current

lOUT

Power Dissipation

Po

Temperature Under Bias

TB1AS

Storage Temperature Range

TSTG

Value
-0.5 to +7.0
-3.0 to +7.0
-0.5 to +7.0
±20
1.0
-10 to +85
-65 to +150

Unit
V
V
V
mA
W
·C
·C

Nole: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating condition for extended periods may affect device reliability.

FWlTSU
3-74

A,
A,
NC

A,
As
D,
D,
0,
0,

MB81C88·55
MB81C86·70

Capacitance
(TA

=25°C, f = 1 MHz)

Parameter

Symbol

Output Capacitance (Vila

=OV)

=OV)
Input Capacitance (V'N = OV)
Input Capacitance (V,N

Recommended Operating
Conditions
(Referenced to VSS)

Typ

Min

Max

Unit

C OUT

8

pF

Cas

7

pF

C 'N

6

pF

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

4.5

5.0

5.5

V

Input Low Voltage

Vee
V,L

-3.0'

0.8

V

Input High Voltage

V,H

2.2

6.0

V

Ambient Temperature

TA

a

70

°C

Note: '-3.0V Min. for pulse width less than 20 ns. (V,L min. = -0.5 V at DC level)

DC Characteristics
(Recommended operating
conditions unless
otherwise noted.)

Parameter

Symbol

Standby Supply Current

ISB

IIln

Max

Unit

Teet Conditions

10

mA

V'N=VssOrVee
E=V'H
Cycle = Min., IOUT= OmA

Operating Supply Current

lee2

100

mA

Input Leakage Current

IL,

-5

5

,.A

V,N=OVto Vee

Output Leakage Current

IL'/O

-5

5

,.A

E=V'H
VOUT=OV to Vee

Output High Voltage

VOH

2.4

V

IOH=-4mA

Output Low Voltage

VOL

0.4

V

IOL =8mA

Peak Power-on Current

Ipo

40

mA

Vee=O to Vee min.
CS = Lower of Vee or V,H min.

Note: All voltages are referenced to vss.

AC .st Conditions
•
•

•

Input Pulse Levels:
0.6V to 2.4V
Input Pulse Rise & Fall
Times:
5ns (Transient between O.BV
and2.2V)
Timing Reference Levels:
Input: V,L = 0.8V, V,H = 2.2V
Output: VOL 0.8V, VOH
2.2V
Output Load

=

•

+5V

Rl
DOUT

0----.,----1
R2

=

'Including Probe and Stray Capacitance

Ri

R2

CL

Parameters Measured

Load I

4800

2550

30 pF

except TELOX, TEHOX, TWLOZ, TWHOX

Load II

4800

2550

5pF

TELOX, TEHOZ, TWLOZ, TWHOX

FUJITSU
3-75

MBB1CBII·5S
MBB1CBII·70

AC Characteristics
(Recommended operating
conditions unless
otherwise noted.)

Timing Dlagrama (Note 1)

Read Cycle

Parameter

Symbol

MB81C86·55 MB81C86·70
Min
Max
Min
Max
Unit

55

Read Cycle Time

TAVAX

Address Access Time

TAVQV

E Access Time

TELQV

Output Hold from Address Change

TAXQX

Output Hold from E

TEXQX

Chip Selection to Output Low-Z

TELQX

Chip Deselection to Output High-Z

TEHQZ

Power Up from E

TELIH

Power Down from E

TEHIL

70

ns

55
55
5
5
10
5
0

70
70
5
5
10
5
0

25

ns
ns
ns
ns
ns

25

ns
ns

40

40

ns

Read Cycle I: Addre.. Controlled (Note 3)

TAVAX

(NOTE2)------ItL-~

ADDRESS _ _{
1!=TAXQX_
Q

DATA VALID

PREVIOUS DATA VAUD

Read Cycle II: E Controlled (Note 4)

_____

ADDRESS

~------"~Ir---

HIGH-Z

Q

Vee

[~•.----------TAVAX----------~~~

ICC ___

HIGH-Z

DATA VALID

1_____________.; . __T_E_H_'L~

-'~~E~I~-5O%
__

SUPPLY
CURRENT

Icc

UNDEFINED:

~

50%

DON'T CARE:

~

Notes:
1. Vii is high for Read Cycle.
2. All Read Cycle timings are referenced form the last valid address to the first transitioning address.
3. Device is continuously selected, E = V'L _
4. Address valid prior t%r coincident with E transition low.
5. Transition is measured ±500 mV from steady state voltage with specified load in Fig. II.

FWI"1'SV

3·76

M881C81S-SS
M881C81S-70

Timing Diagram. (Note 1,2)
(Continued)

WrIte Cycle

Paremeter

Symbol

Write Cycle Time
Address Valid to End of Write

TAVAX

Chip Select to End of Write
Data Valid to End of Write

TEIWH
TDVWH

Data Hold Time

TWHDX

Write Pulse Width

TWLWH

Address Setup Time

TAVWL

Write Recovery Time

TEHAX

Output High-Z from W

TWLOZ

Output Low-Z from W

TWHOX

MB81C86-55 MB81C86-70
Min
Max
Min
Max
Unit
55
45

TAVWH

45
25
5
30
5
5
0
5

ns

70
50
50
30
5
35
5
25
30

ns
ns
ns
ns
ns
ns
ns

5
0

ns

25
35

5

ns

Write Cycle I WControlled

•
ADORESS

•

TAVAX (NOTE 3)

-)

•

•

TEIWH

-

TWHAX

l\\\\\\\\\\\\\

\\'\ ':\\\'\
•

•

TAVWH

•

TWLWH

i-TAVEL-i

\'\
....---TDVWH----+-

)

D

TWLQZ (NOTE 4)

-.------.-

--

DATA VALID

TWHDX

!(

II

TWHQX (NOTE 4) I •

Q

UNDEFINED:

~

DON'T CARE:

~

Not..:
1. EQr Wmust be high during addresUransitions.
2. "E goes high simultaneously with W high. the output remains in high impedance state.
3. All Read cycle timings are referenced from the alst valid address to the first transitioning address.
4. Transition measured ±500mV from steady state voltage with specified load in Fig. II.

I"WlTSU

3-77

MB81C88·55
MB81C88.7()

Timing Diagram. (Note 1.2)
(Continued)

Write Cycle II

E Controlled

•
ADDRESS

-

•

TAVAX (NOTE 3)

)

·•

TAVWH
TEIWH

-4-TAVEL1

....-

TEHAX

l
L
w

•

TWLWH

\\\\\\\\\'i
•

TOVWH

0.\\\\\\\\\\\\\\

.I_ITEHDX

D

UNDEFlNED:~

DON'T CARE:

~

Notes:
1. E Qr Iii must be high during addresUransitlons.
2. If E goes high simultaneously with W high, the output remains in high impedance state.
3. All Read cycle timings are referenced from the alst valid address to the firsl transitioning address.

FUoJI'I'SU
3·78

MB81C88·55
MB81C88·70

Packa.. e Dimensions
Dimensions in inches
(millimeters)

32·PIIeI Ceramic IMetal 8_11 Leadle•• Chip Carrier
ICa.e No.: LCC.32C·A021
'PIN 1 INDEX
C.OI5(O.38)TvP

/

.445(11.30)
.460(11.88)

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

3·79

3.6O(9.14)TYP

FUJITSU

MB8416·20
MB8416·20L

MICROELECTRONICS. INC.

CMOS 16384·BIT STATIC
RANDOM ACCESS l\&EJJIORY
DESCRIPTION
The Fujitsu MB8416 is a 2048
word by 8-bit static random access memory fabricated with high
density, high reliability Complementary MOS silicon-gate technology.
The memory utilizes asynchronous circuitry and may be maintained in any state for an indefinite period of time. All input
and output pins are TTL-compatible, and a single 5 volt power sup-

FEATURES
• Extended temperature range:
MB8416-20: -40° to +85°C
MB8416-20·L: -40° to +70°C
• Organized as 2048 words by
8-bits
• Fast Access TIme: 200 ns Max.
• Low Standby Power:
MB8416·20: 55 JLW
MB8416-20L: 5.5 JLW

ply is used. It is possible to retain
data at low power supply voltage.
The MB8416 can be optimized for
high performance applications
such as microcomputer systems
where fast access time and ease
of use .!fe required. Output
Enable (G) input permits the
disable of all outputs when out·
puts are OR-tied. The MB8416 is
packaged in an industry standard
24-pin dual in-line package, or
32-pin lead less chip carrier.

CUDI" PACKAGE
DlP-24CoC03

PLASTIC PACKAGE
DlP-24P-1I02

o

• Completely Static Operation,
no clocks required
• Single +5 Volt Power Supply
• TTL Compatible
Inputs/Outputs
• Low Data Retention Voltage:
2.0V Min.
• Pin compatible with HM6116,
TC5517 and JLPD446

UADLESS CHIP CARRIER
LCC-32CoA02

MB8416 BLOCK DIAGRAM

~CFLATPACKAG.

FPT·24P-1I02

~Vcc

~V..
BUFFER

ROW
DEC.

PIN ASSIGNMENTS

MEMORY MATRIX
128 x 16 x 8

A7

Vee

At!
At!

At!
At!

W

Ao

o

Aa
Ae

A,.

A.

E

Au

007

DOD

DOB

D01

005

DQ2

~

V.. --.._ _---'

DQ3

A7 Ne Ne Ne vee Ne Ne

.Vi

DO,

TRUTH TA.BI.E
i

li Ii

H
L
L
L

X
H
L
X

X
H
H
L

AI

54

AS

•

3

2

1

32 31 30 21

AI

..

AS
Ne

A4

1

27

AS

8

.. W
25 G

MBU.B

AS

9

IIODE

CURRENT

110 PIN

A'

••

2'

Ai0

Not Selected

Iss

HIgt>Z
Hlgh-Z

AD

11

23

E

NC

.2

22 . DO,

Dour
0..

DOo

SUPP\.Y

Dour Disable
Read

Icc
Icc

Write

Icc

(2048.8)

13•• 15 .B .7 18 19 20 2•

Do, 00. VSS NC DO. 110. 00.

3-80

DOs

MB84l6·20 1MB8416·20 L
ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

I
Storage Temperature

Cerdip

I Plastic

Tstg

Min

Max

Unit

-65
-40

150
125

·C

Tbias

-40

85

·C

Supply Voltage

Vee

-0.5

8.0

V

Input Voltage

V,N

-0.5

Vee + 0.5

V

Input/Output Voltage

V,/O

-0.5

Vee +0.5

V

Temperature Under Bias

NOTE:

Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation shOuld be restricted to the conditions as detailed in the
operational sections of this data sheet. This device contains circuitry to protect the Inputs against damage due to high static voltages or electric fields. However, it Is
advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high Impedance circuit.

RECOMMENDED OPERATINGCONDmONS
Parameter
Ambient Temperature

TA

Supply Voltage
Input High Voltage
Input Low Voltage

(Referenced to VSS = OV)

Symbol
I MB8416·20L
I MB8416·20
Vcc

MB8416
Typ

-40
-40

-

4.5
2.2
-0.3

5.0

Max
+70
+85
5.5

-

Vee +0.3
0.8

Min

V,H
V,L

-

Unit
·C
V
V
V

CAPACITANCE
(TA = 25·C, f = 1 MHz)
Parameter
Input Capacitance
Input/Output Capacitance

Symbol

Min

Max

Unit

Condition

C'N

-

7
10

pF
pF

V,N =OV
V,/O -OV

C,iO

STATIC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted.)
Parameter

Symbol

Condition

E=

MB8416-20L

Vee - 0.2toVee + 0.2V

Standby Supply Current
Standby Supply Current
Active Supply Current
Operating Supply Current
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage

ISBI
MB8416·20

V,N = -0.2V to Vee +0.2V
E=V,H
V,N = -0.2V to Vee +0.2V
E=V,L
V,N = V,L or V,H; lOUT = 0
Cycle - Min, Duty - 100%
'OUT=O
V,N - OV to Vcc
'!..IIO = OV to Vee
E=V,H
lOUT = -1.0 mA
IOUT-4.0 mA

ISB2
leel
ICC2

3-81

Min

Max

-

1

Units
pA

10
2
60

mA
mA
mA

III

-1.0

60
1.0

'LO

-1.0

1.0

pA

VOH
VOL

2.4

-

V
V

-

0.4

pA

MB84l6·20 1MB84l6·20 L

AC TEST CONDmONS
Input Pulse Levels:
Input Pulse Rise and Fall Times:
Input Timing Reference Level:
Output Timing Reference Level:
Output Load:

0.6V to 2.4V
10 ns
0.8V to 2.2V
0.8V to 2.2V
1 TTL Gate and
CL 100 pF for all others.

=

Output
0

D

I

r

>-----0

CL

-=

DYNAMIC CHARACTERISTICS
Parameter

Symbol

Min

Max

Unit

Read Cycle Time
Write Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Output Low Z from E
Output High Z from E
Output Low Z from G
Output High Z from G
Output Low Z from Vi
Output High Z from W
Output Enable to Output Valid
Address Set Up Time
Read Set Up Time
Read Hold Time
Write Set Up Time
Write Hold Time
Address Valid to End of Write
Chip Enable to End of Write
Write Pulse Width
Write Recovery Time
Data Set Up Time
Data Hold Time

TAVAX

200
200

-

ns
ns
ns
ns
ns
ns
ns

TAVAX
TAVQV
TELQV
TAVQX
TELQX
TEHQZ
TGLQX
TGHQZ
TWHQX
TWLQZ
TGLQV
TAVEL, TAVWL
TWHEL, TWHAV
TAXWL, TEHWL
TWLEL
TEHWH
TAVWH
TELEH
TWLWH
TWHAX, TEHAX
TDVEH, TDVWH
TWHDX, TEHDX

3-82

15
15

15

15

200

200

60

60

-

-

60
100

0
0
0
0
0
160
160
140
10
60
0

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

MB84l6·20 IMB84!6·20L

WAVEFORMS
MODE 1, W Controlled,

(J!

=Low, G =Low)

Read Cycle

~----------------TAVAX----------------~

ADD

Vi
~----------TAVQV--------~~

Q VALID

Q

o
HIGH·Z

Write Cycle
~----------------TAVAX----------------~

Vi

Q

HIGH-Z

O----------~~~--------~~

3·83

MB8416·20/MB8416-20 L

WAVEFORMS (Continued)
MODE 2:! Controlled, (G; = Low)
Read Cycle
~----------------TAVAX----------------~

D- _ _ _ _ _

...;.;H;.;;IG~H..;;.Z;....

______________________ _

Write Cycle
~----------------TAVAX------------------~

~----------TELEH------------f

w

-------------------+-+----- ---HIGH·Z

Q- - - - -

-- - - - - - - - - - - - - - - _ r-----_.I ,.._-D

-__ --------------1
3-84

~~20/~20L

WAVEFORMS (Continued)
Enable/Disable G Controlled; (E

=Low,W =High)

Read Cycle
G

Q

~T.LQV

{roHQZJ

TGLQX

HIGH-Z

HIGH-Z

Q VALID

DYNAMIC CHARACTERISTICS
Data Retention Characteristics,
Parameter

NOTES~(Recommended operating conditions unless otherwise noted.)

Notes

Symbol

Data Retention Supply Voltage

m

VDR

Data Retention Supply Current

@]

lOR

Data Retention Set Up Time
Recovery Time

~

TEHVCL
TVHEL

~

MB8416-20
MB8416-20L

Min

Max

Unit

2.0

5.5

-

10
1

V
,..A

u.A

-

0
60

ns
ns

NOTES:
[I ~ = 2.2V to VDR + 0.3V when VDR = 2.5V to 5.5V

E = VDR ± 0.3V when VDR = 2.0 to 2.5V.
~Vcc= VDR = 2.0V, E= VDR ± 0.2V Y,N = - 0.2V to VDR + 0.2V.
IjJVL = 4.5V on the falling transition, VH = 4.5V on the rising transition.

DATA RETENTION

MODE

Vee

4.SV"

~

,.... --(VDRl--

,... ' 4.SV

Ir.

J

E!!I2.2V-' ________ '

3·85

~
2.2V~

MB84l6·20 IMB84J.6.20L

PACICAGE DIMENSIONS

Dimensions in inches (millimeters)

24-LEAD CERDIP DUAL IN·LINE PACKAGE
Dlp-24C·C03
R.026i0.641

REf"",

1.200(30.481

1.300(33.02)

~f;~~.'~~~2.~~~'MFAX~~~~~~~

~.230'''''MAX
.1lO13.OS}
.15013.811

,09012.29)

I-

.110(2.79,'~--+--TiOoffi'li4ij;",-+.-

.020(0.51 I

,060(1.27)

24-LEAD PLASTIC DUAL IN·LINE PACKAGE
Dlp-24p·M02

INDEX

32-PAD CERAMIC (METAL SEAL) LEAD LESS CHIP CARRIER
LCC-32-A02
·PIN 1 INDEX

C.015(0.38ITVP

/

.445 (11.301
.460( 11.681

3·86

MB8416·20 IMB84l6·20L

PACKAGE DIMENSIONS

Dimensions in inches (millimeters) (Continued)

24-LEAD PLASTIC FLAT PACKAGE
FPT-24P-M02

fll

·38619.8)
.417110.6)

.28717.3)
.31117.9)

~r=n=n:=;;::::;;::;:;:=n=;;=;;r=;:?!~

.01210.3)
.02810.7)
Details of .. A" part

.10612.7)

MAX

.05011.27)
TYP

.02710.68)

MAX

3·87

FUJITSU

MOS Memories
•

MB8416A.12, MB8416A.12L,
MB8416A.15, MB8416A·15L
CMOS 16,384-Bit
Static Random Access Memory

The Fujitsu MB8416A Is a 2048-word by 8-bit static random ac·
cess memory fabricated with CMOS silicon gate process. The
memory utilizes asynchronous circuitry and may be maintained In
any state for an Indefinite period of time. All pins are TTL com·
patlble, and a single 5 volt power supply is required.
The MB8416A is Ideally suited for use in microprocessor systems
and other applications where fast access time and ease of use
are required. All devices offer the advantages of low power
dissipation, low cost, and high performance.

PMtur••
• Organization: 2048 words x
8-blts
• Fast Accesa
120 na max. (MB8418A·12112L)
150 na max. (MB8416A·15115L)
• Compl.t.1y ststlc operation:
No clocks required
• TTL compatlbl. Inputs/outputs
• Th.....atat. output
• Common data InpuVoutput

nme:

• Singi. +5V power supply
• Low power standby:
5.5 mW max. (MB8418A-12115)
275,.W max. (MB8416A·12U15L)
• Data ret.ntlon: 2.0V min.
• Jedec Standard 240pln DIP
(CeramiC CerdlplPlaatlc Mold)
• Pin compatlbl. with HM8118,
TC5517 and ,.PDj48
• Output Enabl. (0) pin for
precise data bUB control

3-88

MB8418A·12
MB8418A·12L
MB8418A·lIJ
MB84'18A·15L

MB8418A Block Diagram
and Pin A . .lgnment

.....--.0 Vee

A"

AT

....--...0 vss
ADDRESS

ROW

128 x 16x 8

BUFFER

DECODER

MEMORY CELL

Vcc

Ae

AS

AS

3

22

Ag

A4

4

21

W

Aa

5

A2

6

A,

At

7

~

Ao

8

DQO

9

ARRAV
A,

.:

~3:

... 111

>< ...
.S!~

DQ1
G

w

20

G

19

A tO

18

E

17

DQ7

16

DQ6

15

DQ5

DQ2

11

14

DQ4

VSS

12

13

DQ3

CEO

DQ,

DO.
~

Truth Table

E Q W
H
L
L
L

Ab.olute Ma.lmum Rating.
(See Note)

X
H
L
X

X
H
H
L

Supply
Current 1/0 Pin

Mode
Not Selected

High-Z
Hlgh-Z

IS8
DOUT Disable Icc
Read
Icc
Write
Icc

DOUT
D'N

Rating
Storage Temperature

Symbol
Cerdip
Plastic

Tstg

Temperature Under Bias
Supply Voltage
Input Voltage
Input/Output Voltage

Tbias
Vee
V,N
VI/O

Value

Unit

-65 to +150
45 to +125
-10to+85
-0.5 to +7.0
-0.5 to Vee + 0.5
-0.5 to Vee + 0.5

·C
·C
V
V
V

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, It Is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high Impedance circuit.

Capacitance

Recommended Operating
Condition.
(Referenced to Vss)

Parameter

Symbol

I/O CapaCitance (V,IO = OV)
Input CapaCitance (V ,N = OV)

C,IO

Min

Typ

C 'N

Ma.

Unit

10
7

pF
pF

Parameter

Symbol

Min

Typ

Ma.

Unit

Supply Voltage
Input Low Voltage
Input High Voltage
Ambient Temperature

Vee
V,L
V,H

4.5
-0.3
2.2

5.0

5.5
0.8

V
V
V

TA

0

FUJITSU
3-89

Vee +0.3
70

·C

MB8418A·12
MB8418A·12L
MB8418A·15
MB8418A·15L

DC Charactarlstlcs
(Recommended operating
conditions unless otherwise
noted.)

Parametar

Condition

Symbol

E=Vcc-0.2 to Vcc+0.2V,
Standby Supply Current 1
VIN = -0.2V to Vcc+0.2V
E=VIH,
Standby Supply Current 2
VIN = -0.2V to Vcc +0.2V
E=VIL
Active Supply Current
VIN = VIL or VIH; lOUT = 0
Cycle - Min, Duty - 100%
Operating Supply Current
10UT=0
Input leakage Current
Output Leakage Current
Output High Voltage
Output low Voltage

VIIO=OVto Vcc
E=VIHorG=VIH
10UT= -1.0 mA
lOUT = 4.0 rnA

MB8418A·
12115
Ma"
Min

MB8418A·
12U15L
Min
Ma"

0.05

mA
rnA

2

60

ICC1

Unit

60

60

rnA

60

rnA

III

-1.0

1.0

-1.0

1.0

ILO

-1.0

1.0

-1.0

1.0

"A
"A

VOH

2.4

0.4

V
V

1=

2.4
0.4

VOL

Nota:. All voltages are referenced to GND.

AC Tast Conditions

AC Charactarlstlcs
(Recommended operating
conditions unless otherwise
noted.)

2.2v

Input Pulse Levels:
O.6V to 2.4V
Input Pulse Rise and Fall Times: 5ns
(Transient Time between O.BV and 2.2V)
Timing Reference Levels:
Inpul: VIL =O.8V, VIH=2.2V
Output: VOL = O.BV, VOH = 2.2V
Output Load:
CL = 5PF for TEHOZ, TGHOZ and TWHOZ
CL = 100 pF for all others.

3200

3KU

MB8418A·
12112L
Min
Ma"

MB8418A·
15115L
Min
Ma"

120
120

150
150

Paramater

Symbol

Read Cycle Time
Write Cycle Time
Address Access Time
Chip Enable Access Time

TAVAX

Output Hold from Address Change
Output low Z from E
Output High Z from E
Output low Z from G

TAXOX
TElOX
TEHOZ
TGlOX

Output High Z from G
Output Low Z from W
Output High Z from W

TGHOZ
TWHQX
TWLQZ

Output Enable to Output Valid
Address Set Up Time
Read Set Up Time
Read Hold Time
Write Set Up Time

TGLQV
TAVEL, TAVWL
TWHEL, TWHAV
TAXWL, TEHWL

0
0
0

0
0
0

TWLEL
TEHWH
TAVWH

0
0
100

0
0
120

TElEH
TWLWH
TWHAX, TEHAX
TDVEH, TDVWH
TWHDX, TEHDX

100
70
5
35
0

120
90
5
40
0

TAVAX
TAVOV
TElOV

Write Hold Time
Address Valid to End of Write
Chip Enabled to End of Write
Write Pulse Width
Write Recovery Time
Data Set Up Time
Data Hold Time

120
120
15

ns
ns

15
40

10

50
10

40
15

15

40

60

50

3·90

---------

50

150
150

FUJITSU

-------

50

ns
ns
ns
ns
ns
ns
ns
ns
ns

15

15

-~-----

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

MB8416A·12
MB8416A·12L
MB8418A·15
MB8418A·15L

Mode 1 -

(E =

Low,

Vii Controlled

G = Low)

Read Cycle Timing Diagram
~-------------------TAVAX------------------~

ADDRESS

ADDRESS VALID

w
~----------TAVQV----------~

Q VALID

Q

o

HIGH·Z

Write Cycle Timing Diagram
~------------------TAVAX------------------~

ADDRESS

ADDRESS VALID
~---------------'TAVWH--------------~

~----------TWLWH----------"

w

TWHQX
HIGH·Z
Q

TWHDX

D

HIGH·Z

HIGH·Z

FUJITSU
3·91

MB8418A·12
MB8418A·12L
MB8418A·1II
MB8418A·15L

Mode 2 .(~ Low)

=

i

Controlled
Read C,cle Timing Diagram
~-----------------TAVAX

ADDRESS

E

w

Q

D

HIGH·Z

Write C,cle Timing Diagram
~-----------------TAVAX------------------~

ADDRESS

ADDRESS VALID
r-----------·TELEH------------~

Q

HIGH·Z
TEHDX

D

FUJITSU

3·92

MB8418A·12
MB8418A·12L
MB8418A·15
MB8418A·15L

Mode 3 - G Controlled
Low, W = High, Address
Valid)

(E =

-{T.HQZ~

~

iL-TGLQ-V
HIGH·Z
Q

Data Retention
Characteristics
(Recommended operating
conditions unless otherwise
noted.)

,I

Q VALID

MB8418A·
MB8418A·
12115
12U15L
Mal(
Mal(
Min
Min

Parameter

Symbol

Data Retention Supply Voltage
Data Retention Supply Current

V OR

2.0

lOR
TEHVL
TVHEL

0
40

Data Retention Set Up Time
Recovery Time

5.5
0.5

2.0

5.5
0.03

0
40

Note 1. E=2.2V to VDR+O.3V when VDR=2.5V to S.5V, E=VDR±O.3V when VDR =2.0 to 2.SV.
Note 2. VCC=VOR=3.0V, E=VOR-O.2V to VOR+O.2V, VIN = -O.2V to VOR +O.2V.
Note 3. VL = 4.5V on the falling transition, VH = 4.5V on the rising transition.

Data Retention Timing
Diagram

DATA RETENTION
MODE

Vee

,

,

"'--(VDIV--""

FUJITSU

3·93

HIGH·Z

Unit

Test Condition

V
mA

Note 1
Note 2

ns
ns

Note 3
Note 3

MB8418A·12
MB8418A·12L
MB8416A·15
MB8416A·15L

Typical Characteristics
Curves

Standby Supply Current
VS. Ambient Temp

Standby Supply Current
Supply Voltage

VS.

VCC=~=5.5V

_

_

E=VCC
T,.=2S"C

-1r-+--+-t--I

./

",

V
,/'
./'

Supply Current
(Active/Operating)
VS. Ambient Temp
VCC=5.5V

r- ......

V

...... ......

V

10- 1
10
20
30
40
50
60
TA AMBIENT TEMPERATURE ('C)

Supply Current
(Active/Operating)
vs. Supply Voltage

10

-

l....- i--"""

_r-

40

50

Access Times
Supply Voltage

Vcc ,.4.5V

/'

:lO

VS.

,/

V

20

TA =2S'C

"'-..

~
.............

/
10

Access Times
vs. Load Capacitance

Vee =~.5V
TA"'ZS'C

/

Vee

./""

300

30

40

so

80

70

= 5.5V

-~~N:~:\L - + - - - - - /

400

CL LOAD CAPACITANCE (pF)

f FREQUENCY (MHz)

FUJITSU

3-94

5.25
Vee SUPPLY VOLTAGE (V)

Supply Current
vs. Frequency

/""

200

20

TA AMBIENT TEMPERATURE ('C)

Vee SUPPLY VOLTAGE (V)

60

T A AMBIENT TEMPERATURE ('C)

Access Times
vs. Ambient Temp

/

TA=ZS'C

3
3.5
4
4.6
Vee SUPPLY VOLTAGE (V)

70

",

70

Package Dimensions
Dimensions in inches
(millimeters)

24-Lead Ceramic (Cerdlp)
Dual In-Line Package
DIP-24C-C03

5j

.23015.84I MAX

.12013.05)

.150(3.81)

~

,020(0.51)

.050(1.27)

24-Lead Plastic
Dual In-Line Package
DIP·24P·M02

l

0.52411331)

~=rFTFr=r=r=;=r~~IJ3791
1171(29.74)
1.197(30.40)

.

Ii"". ·.
118(300JMIN

020(051)MIN
.080(203)

24·Lead Plaatlc
Dualln·Llne Package
DIP·24P·M03

:::::~::::: ~'~:.:~]~
I

I

I

1.152129.271
1.178(29.92)

,034(0.861

~I"""'"''
1r I I UU

,100(2.54)
TYP

I

I

~~...!..
.Q70(1.77)

.1181301MIN

---JI

3-95

.01510.38)
.021 (0.54)

.020(O.51)MIN

FUJITSU

MOS Memories
• MB8416·25·W

CMOS 16,384-Bit
Static Random Access Memory

D••crlptlon
The Fujitsu MB8416 is a 2048·word by a·bit static random access
memory fabricated with a CMOS silicon gate process. The memory
utilizes asynchronous circuitry and may be maintained in any state
for an indefinite period of time. All pins are TTL·compatible, and a
single 5 volt power supply is required,
The MB8416 Is ideally suited for use in microcomputer systems
and other applications where fast access time and ease of use are
required, This device offers the advantages of low power dissipa·
tlon, low cost, and high performance,

'- ,-l-

fL-

I)f lti

I- -

-.r

P••tur••
• Organized as 2048 words x 8 bHs
• Fast Access Tima:
250 ns max.
• Completely static oparatlon:
No clock required
• TTL compatible input/output
• Th....stata output
• Common data input/output

• Single +S V power supply
• Low standby power
• Data retention:
2.0 V min.
• Standard 24-pln DIP
(Ceramic Cerdip)
• Standard 32-pad
leadless chip carrier
• Wide Temperatura Range:
TA = -ssoC to +12SoC

r-'

,'';;'

-/

/--

II- /
f-

If-

3-96

~

~ ,-~-

AIIIIIPI

l-'cl.~J 11 ~- l -

f-;-;A.

aA,

_

I-

MB8418-25-W

MB8418 Block Diagram
and Pin Assignment

...

....--.aVec

A"

..
A,

A7

--0'"
ADDRESS
BUFFER

128x1&xl

ROW
DECODER

3

A4

4

A3
A2

5
6

Al

7

Ao

8

OQo

9

ARRAY

A,
A.

Functions and
Pin Connections

-;;oil

Vi
G

t~

A l0

001

.. '"
-~

E

01--

OQ7
OQs
OQs

OQ2

OQ.

12

OQ3

OQo DO, OQ2 003 004 DQ5 DGa DOt

Mode

E

Q

Vi

Supply
Current

DQPln

~

Vcc

QND

Standby
Output Disable

H

X

X

ISB

High-Z

Don't Care

Vee

Vss

L

H

H

lee

High-Z

Don't Care

Vee

Vss

Read
Write

L
L
H

L

H
L

Icc
Icc
IDR

DOUT
DIN
High-Z

AIN
AIN
Don't Care

Vee
Vee
VOR

Vss
Vss
Vss

Data Retention

Absolute Ma"lmum Ratings
(See Note)

Ag

OQ 1

Vss

,o---{>o--4>---E

As

As

MEMORY CELL

"

Vee

As

X
X

X

Rating

Symbol

Valua

Unit

Tstg

-65 to +150

Temperature Under Bias

Tblas

-55 to +125

'c
'c

Supply Voltage
Input Voltage

Vee
VIN

-0.5 to +8.0

Output Voltage

VOUT

Storage Temperature Range

Ceramic

-0.5 to Vee+0.5
-0.5 to Vee +0.5

V
V
V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields, However, It Is advised that normal precautions be taken to
avoid applications of any voltage higher than maximum rated voltages to this high Impedance circuit.

Capacitance
(TA= 25'C, f=1MHz)

Recommanded Operating
Conditions
(Referenced to V55)

Paramater

Symbol

Min

Typ

Ma"

Unit

ItO CapaCitance (VIIO = OV)

10

Input Capacitance (V I/O = OV)

7

pF
pF

Parameter

Symbol

Min

Typ

Ma"

Unit

Supply Voltage
Input Low Voltage

4.5

5.0

5.5

V
V

Input High Voltage

Vcc
VIL
VIH

Ambient Temperature

TA

-55

FUJITSU
3-97

-0.3
2.2

0.7
Vee + 0.3
125

V

'c

MB8416·25·W

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Max

Unit

Test Conditions

ISB1

300

~A

E=V cc -0.2V to Vcc+0.2V.
VIN = -0.2V to Vcc+0.2V

ISB2
Icc1

2

mA

E=V IH • V IN = -0.2V to Vcc+0.2V

65

mA

65
5
5

E = VIL• VIN - VIL or VIH• lOUT - 0
Cycle = Min. Duty=100%.l oUT =0

~

Standby Supply Current
Active Supply Current
Operating Supply Current
Input Leakage Current
Output Leakage Current
Output High Voltage

ILO
VOH

Output Low Voltage

VOL

ICC2
III

-5
-5
2.4

0.45

mA
~A

VIN =OV to Vcc
VlfO-OVtO·Vcc. E-VIH

V

10UT= -1.0 mA

V

IOUT=4.0mA

Note: All voltages are referenced to VSS.

AC Test Conditions

Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Reference Levels:
Output Load:

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

0.6 V to 2.4 V
10 ns (Transient Time between
0.8 V and 2.2 V)
Input: VIL = 0.8 V. VIH = 2.2 V
Output: VOL = 0.8 V. VOH = 2.2 V
1 TIL Gate and C L = 100 pF for
all AC parameters except TEHQZ
and TWLQZ. TGHQZ
CL = 5pF for TEHQZ. TWLQZ
andTGHQZ

Parameter

Symbol

Min

Read Cycle Time

TAVAX

Write Cycle Time
Address Access Time

TAVAX
TAVQV
TELQV

250
250

Chip Select Access Time
Output Hold from Address Change
Output Low Z from E
Output High Z from

E

Output Low Z from G
Output High Z from G
Output Low Z from W
Output High Z from W

ns
250

15

TELQX
TEHQZ

15

TGLQX

15

Unit

ns
250

TAXQX

TGHQZ
TWHQV

Max

ns
ns
ns

70

ns
ns
ns

70

ns
ns

70

ns
ns

15

Output Enable to Output Valid

TWLQZ
TGLQV

Address Set Up Time

TAVEUTAVWL

0

Read Set Up Time

TWHEUTWHAV

0

ns

Read Hold Time
Write Set Up Time

0
0

Write Hold Time

TAXWUTEHWL
TWLEL
TEHWH

ns
ns
ns

Address Valid to End of Write

TAVWH
TELEH

200
200

ns

Chip Selection to End of Write
Write Pulse Width
Write Recovery Time

TWLWH
TWHAXJTEHAX

160
10

ns
ns

Data Set Up Time

TDVEHfTDVWH

70

ns

Data Hold Time

TWHDXfTEHDX

0

ns

FUJITSU
3-98

--

---- --- ----

120

0

ns

ns

MB8418·26·W

Mode.1 CE=Low,

W Controlled
0 .. Low)

Read Cycle Timing Diagram
~-----------------TAVAV----------------~

ADDRESS VALID

w
~---------TAVQV-------+l

Q

D

HIGH·Z

Write Cycle Timing Diagram
~-----------------TAVAV------------------~

ADDRESS VALID
TAVWH-------------~

~------TWLWH--------~~

TWHQV

HIGH·Z
Q

TWHDX

D__________~H~IG~H~.Z~___________(X

Mode 2 -

(0 =Low)

HIGH·Z

E Controlled
Read Cycle Timing Diagram
TAVAV
ADDRESS

ADDRESS VALID

' ..
TElQX

~TELQV

Q-------~~~------

D____________

~H~IG~H~~~

•
_ _ _ _oJ

__________________________________________________

FUJITSU

3·99

M88418·25·W

Mode 2 - i Controlled
Cii =Low), (continued)

Write Cycle Timing Diagram
~----------------TAVAV-----------------"

ADDRESS VALID
f-----------TELEH ----------j

Q __________~H~IG~H~~~____________________________

_1_r---------------

D

Mode 3 - ii Controlled
Ci =Low, W=High,
ADDRESS VALID)

Q---------------~
Data Retention
Characlerlstlcs

HIGH·Z

DATA VALID

Parameter

Symbol

Min

Max

Unit

T_t Condition.

Data Retention Supply Voltage
Data Retention Supply Current
Data Retention Set Up Time
Recovery Time

VDR
lOR
TEHVCCL
TVCCHEL

2.0

5.5
300

V
p.A
ns
ns

Note 1
Note 2

Note 1: E =2.2V to VDR + O.3V whon VDR = 2.5V to 5.5V.
E=VDR±O.3V when VDR=2.0 to 2.5V.
No.. 2: VCC=VDR, E=VDR±O.2V, VIN= -O.2V to VDR+O.2V.

Date Retention Timing
Diagram

DATA RETENTION
MODE

Vcc

4.5V"

,

,

'---(VDRl--"

TEHVCCL

FUJITSU
3·100

0
60

MB8416·25·W

Packa.a Dlman.lon.
Dimensions in inches
(millimeters)

24·Laad Ceramic ICerdlp)
Duel In·Llne Pecka.e
DIP·24C·C03

1-

n J~ -1"

R.025\O.841

"EF

.570114.481
.595115.111

,6251,L~_"-':':::'lI"""","J~ITVp

1.200(30.481
1.300(33.02)

I

.10012.54IMAX

~.230C5."'MAX
.12013.051

.150(3.811

~

32.Pad Ceramic (Metal "al)
Leadle•• Chip Carrier
LCC·32CoA02

;--

"
.546113
.560( 4

.445(11.30)
,460111.68)

"Shape of Pin 1 Index: SUbject to change without notice

3-101

.O~O.511

.05011.271

FUJITSU

MB8417·20
MB8417·20.L

MICROELECTRONICS. INC.

CMOS 16,384·BIT STATIC
RANDOM ACCESS lVIElVIORY
J)~ON

The Fujitsu MB8417 is a 2048
word by 8-bit static random access memory fabricated with high
density, high reliability Complementary MOS silicon-gate technology.
The memory utilizes asynchronous circuitry and may be maintained in any state for an indefinite period of time. All input
and output pins are TTL-compatible, and a single 5 volt power sup-

ply is used. It is possible to retain
data at low power supply voltage.
The MB8417 can be optimized for
high performance applications
such as microcomputer systems
where fast access time and ease
of use are required. Chip Select EO
permits the fast access time. The
MB8417 is packaged in an industry standard 24-pin dual in-line
package or 32-pin lead less chip
carrier.

CERDIP PACKAGE
Dlp·24C·C03

FEA.'1'1JRfS
• Extended temperature range:
MB8417·20: -40°C to +85°C
MB8417·20L: -40°C to +70°C
• Organized as 2048 words by
8·bits
• Fast Access Time:
200 ns Max. (E' Controlled)
100 ns Max. (EO Controlled)
• Low Standby Power:
MB8417·20: 55 p.W
MB8417-20L: 5.5 p.W

• Completely Static Operation,
no clocks required
• Single +5 Volt Power Supply
• TTL Compatible Inputs/Outputs
• Low Data Retention Voltage:
2.0V Min.
• Pin compatible with TC5516
and p.PD447

PLASTIC PACKAGE
DIP·24p·M02

o

LEADLESS CHIP CARRIER
LCC·32C·A02

MB8417 BLOCK DIAGRAM
- - 0 Vee

'"

--oVss
BUFFER

ROW

MEMORY MATRIX

DEC.

128 ... 18)(8

PIN ASSIGNMENT

"At

....
At

"
"

W
E"

',.i
D<>r

DO.
DO,
DO,

DO.

v..

DO,

A7
A6

54

A,

•
•

A_

TRUTH TABLE
E

Ii' ii

H
L

X

L
L

H

L
L

X
X
H

L

MODE
Not Selected
Not Selected
Read
write

SUPPLY
CURRENT I/O PIN
Hlgh·Z
I~R
Hlgh·Z
Icc
Ir.c
DOL T
Icc
DIN

A,
A.

DQ,
DQ_

Ne Ne Ne Vee Ne Ne
3

2

1

32 31

7

S

'7

MB8417

" "
Ao
"

'5
24

11

NC

000,

..
..

30 29

13

NC

Vi
E'

'10

.,

i

22

QQ,

21

DQe

14 15 18 17 18 19 20
DQ1 DQ2 Vss NC OQa DQ4 DOs

3-102

As

A,

MB8417-20 /MB8417-20L

ABSOLUTE MAXIMUM RATINGS
Parameter
Storage Temperature

i

Ceramic
Plastic

Symbol

Min

Max

Unit

T51g

-65
-45

150
125

·C

Tbias
Vee

-40

85

·C

-0.5

8.0

V

Input Voltage

Y,N

-0.5

Vee +0.5

V

Input/Output Voltage

Vila

-0.5

Vee +0.5

V

Temperature Under Bias
Supply Voltage

NOTE:

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed In the
operational sections of this data sheet. This device contains circuitry to protect the Inputs against damage due to high static voltages or electric fields. However, il is
advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit.

RECOMMENDED OPERATING CONDITIONS,
Parameter
Ambient Temperature

TA

Supply Voltage
Input High Voltage
Input Low Voltage

Vss = GND

Symbol
I MB8417-20L
MB8417-20

I

Vee
V,H
V,L

MB8417
Typ

Min

-40
-40

-

4.5
2.2
-0.3

5.0

-

Max
+70

Unit
·C

+85
5.5
Vee + 0.3
0.8

V
V
V

CAPACITANCE
(TA = 25·C, f= 1 MHz)
Parameter
Input Capacitance
Input IOutput Capacitance

Symbol

Min

Max

Unit

Condition

C'N
CI/O

-

7
10

pF
pF

Y,N =OV
VI/O=OV

STATIC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Condition
E=Vee-0.2V to Vee + 0.2V

Standby Supply Current
Standby Supply Current
Active Supply Current
Operating Supply Current
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage

Min

Max

-

1

MB8417-20

-

10

IS82

-

2

lee1

-

60

lee2

-

III

-1.0

60
1.0

'LO

-1.0

1.0

pA

VOH
VOL

2.4

-

V
V

pA

IS81
Y,N = -0.2V to Vee +0.2V
E=V,H
Y,N = -0.2V to Vee +O.2V
E=V,L
V,N = V,L or V,H; lOUT = 0
Cycle = Min, Duty = 100%
lOUT = 0
Y,N = OV to Vee
V'IO = OV to Vee
E=VIH.orE'=V,H
lOUT = -1.0 mA
lOUT = 4.0 mA

3-103

Units

MB8417-20L

-

0.4

mA
mA
mA
pA

MB8417·20 IMB84l7·20L
AC TEST CONDmONS
Input Pulse Levels:
Input Pulse Rise and Fall Times:
Input Timing Reference Level:
Output Timing Reference Level:
Output Load:

0.6V to 2.4V
10 ns
0.8V to 2.2V
0.8V to 2.2V
1 TTL Gate and
CL 100 pF for all others.

=

D

Output

o--------~][~------~

------~o

r

CL

DYNAMIC CHARACtERISTICS
Parameter
Read Cycle Time
Write Cycle Time
Address Access Time
Chip Enable Access Time
Chip Select Access Time
Output Hold from Address Change
Output Low Z from E or E'
Output High Z from 1: or E'
Output Low Z from W
Output High Z from W
Address Set Up Time
Read Set Up Time
Read Hold Time
Write Set Up Time
Write Hold Time
Address Valid to End of Write
Chip Enable to End of Write
Chip Selection to End of Write
Write Pulse Width
Write Recovery Time
Data Set Up Time
Data Hold Time

Symbol

Min

Max

Unit

TAVAX

200
200

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

TAVAX
TAVQV
TELQV
TSLQV
TAXQX
TELQX, TSLQX
TEHQZ, TSHQZ
TWHQX
TWLQZ
TAVWL, TAVSL, TAVEL
TWHAV, TWHEL, TWHSL
TEHWL, TAXWL, TSHWL
TWLSL, TWLEL
TSHWH, TEHWH
TAVSH, TAVWH
TELEH
TELEW
TWLWH
TEHAX, .TWHAX, TSHAX
TDVWH,TDVEH,TDVSH
TEHDX, TWHDX, TSHDX

3-104

15
15

15

0
0
0
0
0
160
160
100
140
10
60
0

200
200

100

60

60

-

MB84l7-20 /MB8417-2·0L

WAVEFORMS
MODE 1: W Controlled: (E = Low, E·

Low)

Read Cycle

~-----------------TAVAX----------------~

ADD

w
~---------TAVQV--------~~

Q VALID

Q

D _ _ _ _-.;.;,;.;;;,.;,;..;;...
HIGH·Z _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Write Cycle
~-----------------TAVAX-----------------;~

Q

HIGH-Z

D---------~-----_(x

3-105

MB8417-20 /MB84l7-20 L

WAVEFORMS (Continued)
MODE 2: E Controlled, (E· = Low)
Read Cycle
....- - - - - - - -

TAVAX--------_~

Q ______~H~IG~H~~~______________~

D _________
HI_G_H_oZ_________________________________________ _

Write Cycle
~-------- TAVAX---------~

I-+-----TELEH

-----+-1

-...;.;.;.;.;.;..;..;;;....-------------H-------HIGHoZ

Q- - - - -

D

-- - ----------------

---------------3-106

MB8417·20 IMB8417·20 L

WAVEFORMS (Continued)
MODE 3: E* Controlled, (E = Low)
Read Cycle

'X--____

TAVAX--------

TWHSL

.L...I-.l-~~~::~-::----"""7IT.~------:
I___
TSLQV_I

Q

-- -

-

---------------<

D----------------------------HIGH·Z

Write Cycle

~

T'Y~-J

~

ADD

-----

•

moo

:

_ T A V S L _ I~~_---TSLSH

W

Q

D

\\\\\\\\'I

14

:ts-H-AX----

_. I_----"'T""'!""""~

TWLSL

Wl!/~

&

_ _ _ _ .:..:.:.=.:..:.HIGH.Z _ _

--------:--II~

____
--------------.J-7.~ ~',...H-DX-_______________
X
~

3·107

MB8417-20/MB84l7-20L

DYNAMIC CHARACTERISTICS
Data Retention Characteristics,
Parameter

Notes

NOTES ill~(RecOmmended operating conditions unless otherwise noted.)
Symbol

m

VDR

Data Retention Supply Current

lID

IDR

Data Retention Set Up Time
Recovery Time

~
~

TEHVL
TVHEL

Data Retention Supply Voltage

MB8417·20
MB8417·20L

DATA RETENTION
MODE

4.5V·
, .... - -(VDRl.

_J'

TEHVL

PACKAGE DIMENSIONS

Max

2.0

5.5

V

-

10
1

p.A
p.A

-

ns
ns

0
60

NOTES:
1. E=2.2V to VDR+ 0.3V when VDR=2.5V to 5.5V, E = VDR±0.3V when VDR=2.0 to 2.5V.
2. Vee=VDR=2.0V, E=VDR±0.2V VIN= -0.2V to VDR+0.2V.
3. VL = 4.5V on the falling transition, VH = 4.5V on the rising transition.

Vee

Min

Dimensions In inches (millimeters)

24-LEAD PLASTIC DUAL IN·LINE PACKAGE
Dlp-24P-M02

O

l

.524113.311
.&43!13.7Bl

1.171(29.74)

.197C&'OOIMAX

"lT

300

" 4 (360))

·Symbols in extra bold type are industry standards. See IEEE STD 662 for details.
3-108

Unit

MB84l7-20 1MB84l7-20L

PACKAGE DDa:NSIONS

Dimensions in inches (millimeters) (Continued)

24-LEAD CERAMIC DUAL IN·LINE PACKAGE
DIP·24C-C03

LEADLlSS CHIP CARRIER
LCC·32C·A02

. . . . '" Pin 1 Io\dt.. : SUbjllCttoc..... wilhoulnoUce

3-109

FUJITSU

MOS Memories
•

MB8417A.12, MB8417A·12L,
MB8417A.15, MB8417A·15L
CMOS 16,384-Bit
Static Random Access Memory

D.sorlptlon
The Fujitsu MB8417A is a 2048-word bya·bit static random ac·
cess memory fabricated with CMOS silicon gate process. The
memory utilizes asynchronous circuitry and may be maintained in
any state for an indefinite period of time. All pins are TIL com·
patlble, and a Single 5 volt power supply Is required.
The MB8417A is Ideally suited for use in microprocessor systems
and other applications where fast access time and eaae of use
are required. All devices offer the advantages of low power
dissipation, low cost, and high performance.

F.atur.s
• Organization: 2048 words x
8-blts
• Fast Access Time:
E Controlled:
120 ns max.
(MB8417A·12112l)
150 ns max.
(MB8417A·1!i115l)
'E* Controllsd:
SOns max.
(MB8417A·12112L)
60ns max.
(MB8417A-1!i115l)
• Completaly static operation:
No clocks required

•
•
•
•
•

TIL compatible Inputs/outputs
Three-state output
Common data Input/output
8111gle +5V power supply
Low power atandby:
5.5 mW max. (MB8417A·12115)
275,.W max. (MB8417A·121J15L)
• Data retention: 2.0V min.
• Jeclec Standard 24·pln DIP
(Ceramic Cerdlp/Plastlc Mold)
• Pin compatible with TC5516

3-110

MB8417A·12
MB8417A·12L
MB8417A·111
MB8417A·111L

MB8417A Block Diagram
and Pin Aaalgnment

.....--.0 vee

'"

A7
Ae
AS
A4
A3
A2
Al
Ao

..--...0 Vss
ADDRESS
BUFFER

ROW
DECODER

128x16 x 8
MEMORY CELL

ARRAY

'4

Dao

Vcc

2

23

Ae

3

22
21

W

4

5
6

031:

7
8

DOO
DOl
D02

9

V55

12

Em
>
+5V

Rl
Do
+5

R2
-:-

'Includlng probe and stray capacitance

FU.JI~U

3-134

MB8464·12
MB8464·12L
MB8464·15
MB8464·15L
MB8464·12LL
MB8464·15LL
AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle 'I
Parameter

Symbol

MB8464.12/12L
Min
Max

MB8464.15/15L
Min
Max

Unit

Read cycle time

TAVAX

120

150

ns

Address access time '2

TAVQV

120

150

ns

E, access time

TEILQV

120

150

ns

E2 access time

TE2HQV

120

150

ns

Output enable to output valid

TGLQV

50

60

ns

Output hold from address change TAXQX

10

10

Chip enable to output low-Z '3

TEILQX, TE2HQX

10

10

ns

Output enable to output low-Z '3

TGLQZ

5

5

ns

Chip enable to output high-Z '3

TEIHQZ, TE2LQZ

Output enable to output high-Z '3 TGHQZ

ns

40

50

ns

40

50

ns

Write Cycle

Parameter

Symbol

MB8464.12/12L
Min
Max

MB8464·15/15L
Min
Max

Write cycle time

TAVAV

120

150

ns

Address valid to end of write TAVWH, TAVEIL, TAVE2H

85

100

ns

85

Unit

Chip enable to end of write

TEILEIH, TE2HE2L

100

ns

Data valid to end of write

TDVWH, TDVEIL, TDVE2L 40

50

ns

Data hold time

TWHDX, TEIHDX, TE2LDX 0

0

ns

Write pulse width

TWLWH

70

90

ns

Address setup ti me

TAVWL, TAVEIL, TAVE2H

0

0

ns

Write recovery time

TWHAX, TEIHAX, TE2LAX 0

0

ns

Write enable to output low-Z TWHQX '3'4
Write enable to output high-Z TWLQZ '3'4
NOTE: '1
'2
'3
'4

5

5
40

ns
50

ns

WE IS HIGH FOR READ CYCLE.
DEVICE IS CONTINUOUSLY SELECTED, CS, ~ OE ~ VIL, CS, ~ V,H.
TRANSITION IS MEASURED AT THE POINT OF ±500 mV FROM STEADY STATE VOLTAGE.
IfOE, Cli, AND CS, ARE IN THE READ MODE DURING THIS PERIOD,II0 PINS ARE IN THE OUTPUT STATE SO THAT THE
INPUT SIGNALS OF OPPOSITE PHASE TO THE OUTPUTS MUST NOT BE APPLIED.

FUJITSU

3-135

MB8484·12
MB8484·12L
MB8484·15
MB8484·15L
MB8484.12LL
MB8464·15LL
Read Cycle Timing Diagrams
Read Cycle

ADDRESS

1"1,2

~14----~:===-~_VQV~TAVAX~.,~_

I}I--<--

---TAXQX

.. '

PREVIOUS DATA VALID

Q

DATA VALID

Read Cycle 11"1

-JI---_

-_"_AVAX---=d_

ADDRESS

~1

- - 1 r o - I - - - - - - T A V Q V - - - -.....

Jt

E,

E,

Q

~ DON'T CARE

NOTE:

:~ ::'~~G: ~g:T~~gu~i~L:ELECTED.

=

G

£1
= VIL. E2 = VIH.
'3 TRANsrnON IS MEASURED AT THE POINT OF ±500 mV FROM STEADY STATE VOLTAGE.

FUJITSU
3-136

m

UNDEFINED

MB8484·12
MB8484·12L
MB8484·1S
MB8484·15L
MB8484·12LL
MB8484·15LL
Write Cycle Timing Dla.rams
Write Cycle I (W Controlled)
~---------------------TAVAX--------------------~

ADDRESS

~-------------- TAVWH ----------------I..j

E,

HIGH·Z

D

I+------;~ TWHQX" '0

TWLQZ"'O

HIGH-Z

Q

IZZJ DON'T CARE
fS1SZI UNDEFINED

a,

IF E" AND Eo ARE IN THE READ MODE DURING THIS PERIOD, 1/0 PINS ARE IN
THE OUTPUT STATE SO THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE
OUTPUTS MUST NOT BE APPUED
'2 TRANSITION IS MEASURED AT THE POINT OF ± 500 mV FROM STEADY STATE VOLTAGE.

NOTE:"

FUJITSU

3·137

MB8464·12
MB8464·12L
MB8464·15
MB8484·15L
MB8464·12LL
MB8464·15LL
WriteCrele
Timing Diagrams

Write Cycle II (E1 Controlled)

(Continued)

~-----------------~V~-------------------4~
ADDRESS

~--------TAVE1L---------I

~------TE1LE1H-------..J

~------TE2HE2L-------.I

w

D

Q

HIGH-Z

HIGH-Z

HIGH-Z

IZ'i/Sl UNDEFINED
NOTE: '1 IF OE, CS. AND WE ARE IN THE READ MODE DURING THIS PERIOD, 1/0 PINS ARE IN THE OUTPUT STATE SO THAT THE
INPUT SIGNALS OF OPPOSITE PHASE TO THE OUTPUTS MUST NOT BE APPLIED.
'2 TRANSITION IS MEASURED AT THE POINT OF ±500 mV FROM STEADY STATE VOLTAGE.

FUJITSU

3-138

MB8464·12
MB8464·12L
MB8464·15
MB8464·15L
MB8464·12LL
MB8464·15LL
WrlteCycle
Timing Diagrams
(Continued)

Write Cycle III (E2 Controlled)
~-------------------~v~--------------------~

ADDRESS

J---------TAVE2H---------+!

J-------TE1LE1H - - - - - - - + 1

J-------TE2HE2L -------+-1

E,

w

D

HIGH-Z

HIGH-Z

HIGH-Z
Q

NOTE: *1 IF li, ~ AND

W ARE IN THE READ MODe DURING THIS PERIOD, D/Q PINS ARE IN

~~~::1rr~~S~E~:~~~.INPUT SIGNALS OF OPPOSITE PHASE TO THE

·2 TRANSITION is MEASURED AT THE POINT OF ±500 mV FROM STEADY STATE VOLTAGE.

3·139

~ UNDEFINED

MB8484"12
MB8484"12L
MB8484"15
MB8484"15L
MB8464"12LL
MB8484"15LL

Data Retention
Chllracterldlca

(Recommended operating
conditions unless otherwise
noted)

Parameter

Symbol

Min

Max

Unit

Date Retention Supply Voltage "I

VOR

2.0

5.5

V

lOR

1.0"3

mA

L Version

lOR

25"3

".A

LL Version

lOR

25"3/2"4

Standard
Data Retention Supply Current "2

Date Retention Setup Time

tORS

Operation Recovery Time

IR

",A

o

ns
ns

Note: *1 ~1 controlled: E2 .s;; O.2V
~1 controlled: ~, .. VOR - O.rN (E2 '" O.2V or E2 .. VOR - O.2V)
"2 E2 controlled: VOR = 3.0V. E2" O.rN
~, con1rollod: VOR = 3.0V. E, .. VOR - O.2V (~ " O.2Vor E2 .. VOR - O.2V)
*3 For TA = 00 to 70°C
*4 For TA = 0" to +40°C

Data Retention Tlmlnll
Data Ratantlon I (E2 Controlled)

1+---- DATA RETENTION MODE ------i~
Vee

4.5V

\'-

Data Retantlon II

4.5V

_ _ _ _ V!!! _ _ _ _ .J

(E, Controlled)

=f:= ~~4.5V

'- ____

Vee
TE1HVL

~

~

4.5V

_ _ _ _ .J

TVHE1L

2.2V .

2.2Y

tZi:l DON'T CARE
EXlIUNDEFINEO

FUJITSU
3-140

MB8484·12
MB8484·12L
MB8464·15
MB8484·15L
MB8484·12LL
MB8484·15LL
Typical Characteristics
Curves

Fig. 3.-NORMALIZED ACCESS TIME
VI Vee SUPPLY VOLTAGE

Fig. 4.-NORMALIZED ACCESS TIME
vs AMBIENT TEMPERATURE
>

9w

1.01-----_t-:

~~

En~
:.:w

~~

>@
~~

O.8'f-:~----t---t--__j

~~i

Vee = 4.5V

i;o
~z

4

5

o

6

Vee. SUPPLY VOLTAGE IV)

50
70
TA. AMBIENT TEMPERATURE 1°C)

Fig. 5.-NORMALIZED POWER
SUPPLY CURRENT
VI Vee SUPPLY VOLTAGE

Fig. 6.-NORMALIZED POWER
SUPPLY CURRENT
vs AMBIENT TEMPERATURE

Ir

~
O

Ir

1.2!1------+---------7'i

"I-

e Z

wW

w
~I-

~ ~ 1.0'1------+-----7""--__j

elI:
WIr

o~>
.J

.JU

~a

z8;

0.811------,,,,,."-:.fF-----__j

~:::J

~ ~ o.

Ir ..

0"

ziil

N::l

u'"
2
iii

1

~f5

LV
1V

V

V"

Vee 1= 5.5V

iii

~

~

0.0 1

o

6

20

40

60

80

T A • AMBIENT TEMPERATURE 1°C)

Vee. SUPPLY VOLTAGE IV)

Fig. B.-NORMALIZED POWER
SUPPLY CURRENT
vs CYCLE TIME

Fig. 7.-NORMALIZED POWER
SUPPLY CURRENT
VI AMBIENT TEMPERATURE

1.0.-.------,-------,
Ir
W

0

~~

T A = 25"C
Vee = 5.5V

"w
elI:

wlr
N::l

~ ~ 0.51-+---.......~_t----__j

::;;.J

8

~~
Z'"

= 5.5V
'eye] = m;n
Vee

o

20

40

60

N

U

2
80

TA. AMBIENT TEMPERATURE 1°C)

FUJITSU
3·141

0L-:0~.1~------~---------i10
'eye CYCLE TIME I~S)

MB8484·12
MB8484·12L
MB8484·15
MB8464·15L
MB8464·12LL
MB8484·1SLL
Packaga Dimensions
In Inches (millimeters)

28·Lead Plastic
Duel In-Una Peckage
DlP.28P.M02

I

INDEX

.533(13.54) .590 14.99)
.610 15.49)

t~~~~~~~~~~~~~~~J405)
I

28·Lead PI....c Plat Package
PPT·28·M01

.005(0.13)
.008(0.201
VIEW A

FUJITSU

3·142

IL

,.012(0.3)
.02810.71

MB8464·12
MB8464·12L
MB8464·15
MB8464·15L
MB8464·12LL
MB8464·15LL
Package Dlmenslona
Continued

32·Pad Ceramic (Metal Seal)
Leadle.. Chip Canter
LCC·32·A02

·PIN 1 INDEX

C.015(O.38)TVP

/
cf

.445 (11.301
.460( 11.681

·Shape of Pin 1 index: Subject 10 change without notice

3·143

PUJITSU

MOS Memories
•

MB8464-15-X, MB8464-15-W• .,88464-20-W
CMOS 65,536-Bit Static Random Access Memory
with Data Retention Mode

Description
The Fujitsu MB8464-X/W is a 8,192 word by 8-blt static random
access memory fabricated with a CMOS silicon gate process. The
memory utilizes asynchronous circuitry and may be malntalnild in
any state for an indefinite period of time. All pins are TTl compatible, and a single + 5 vo~ power supply Is required.

Features
• Organization:
•
8,192 words x 8-blts
•
• Fast accass time:
TAVQV = TELQV = 150 ns max. •
(MB8484-15X/W)
TAVQV = TELQV = 200 ns max••
(MB8484-20W)
• Completely static oj)eratlon:
•
No clock required

• TTL compatible Input/output
• Three-stste output
• Wide temperature range:
-55 to + 125°C
(MB8484-15/20-W)
-40 to +85°C
(MB8464-15-X)

Common data Input/output
Single +5V power supply,
±10% tolerance

Low p _ etsndby:
11 mW mex.
Date retention:
2.OV min.
Ceramic Package (28-pln)
(-X, -W),

LCC (32-pad) (-X, oW)
Standard 28 Pin Plastic
DIP (-X), and Pleetlc
Flatpack (-X)

1hIs device contains circuitry to
proIect !he Inputs agam.t damage
duo to high _
WlI1agoo ... oIoc>
\ric fields. _ . h 10 odvlood
that iIormaI procau\IonI be taken to
avoid appllcatloo 01 any voltage
higher !hen maximum rated VQIt.
agee to this high Impadanco cln:uh.

3-144

MB84.4·lI'·X
MB84.... 1!1-W
MB8484·20·W

MB8484 Block Diagram and
Pin Assignments

---0 Vee
---0 VIS

ADDRESS
BUFFER

256.32x8

ROW
DECODER

MEMORY CELL
ARRAY

G
E

w
DID, 0/04 010. 010.
DID, DID, DID, 0/07

NC

Vee

A12

W

A7

E,

A.

Aa

A,

A,

Aa

An

A,

G

A,

A,.

A,

E,

AD

Dlo,

0/00

0/00

010,

0/0,

DID,

DID.

V••

DiDo

TRUTH TABLE

El
H
X
L
L
L

~

li

W

MODE

X
L
H
H
H

X
X
H
L
X

X
X
H
H
L

NOT SELECTED
NOT SELECTED
OUT DISABLE
READ
WRITE

SUPPLY CURRENT

1/0 PIN

Isa
ISB
Icc
ICC
ICC

HIGH-Z
HIGH-Z
HIGH-Z
°OUT
OjN

Ne

W
E,

: 4:312 ~ 1:32:31:30:
L--'----- i---'--_I_-iL __'

---I

Aa
A,

Aa
Aa

5 1

~~J
7 i

a-I

A,

9-1

A,

101

Ae
NC

0/00

r--

,29

A.

~-~

An

126

NC

[~~
! 24

G

:-28
TOP VIEW

11-1
!~J

~~J

Aa

A,.

ru!-22-

E,

l21
L __

0/00

0/0,

.--1---1---1---1--'---'---'
: 14 :15116 :17118 119120:

010,
DID,

Absolute Maximum Ratings
(See Note)

,;;R;;a;,;tl;;n;:g:..._ _ _ _ _ _ _ _,;:S:.Y;;m;;b;;o;;.I_ _ _ _ _ _ _ _....;;.;;;;;;._~----..;;;,;;;,
Value
Unit

Storage temperature range

TSTG

Temperature under bias

TBIAS

-65 to +150.

Ceramic
Plastic

-45 to +125

-w

-55 to +125

X

40 to +85

·C
·C

Supply voltage

Vee

-0.5 to +7.0

V

Input voltage

VIN

-0.5 to

Vee

+0.5

V

Output voltage

VOUT

-0.5 to

Vee

+0.5

V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliablltty.

FUJITSU
3·145

MB8464·150X
. MB8484·150W
MB8464·20·W

Recommended Operating
Conditions
(Referenced to Vsal

Parameter

Symbol

Min

Typ

Max

Supply voltage

Vee

4.5

5.0

5.5

V

Input low voltage

V IL

-0.3

0.6

V

Input high voltage

VIH

2.4

Vee +0.3

V

-55

+125

°C

-40

+85

°C

Ambient temperature

MB8464-15-W

TA

MBB464-20-W
MB8464-15-X

TA

Capacitance
(TA = 25°C, f = 1 MHz)

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Max

Unit

1/0 capacitance (VI/O = OV)

CI/O

10

pF

Input capacitance (VIN = OV)

C IN

7

pF

Parameter
Standby supply current

MB8484
·150X
Symbol Min Max

Min

MB8484
.15·X/.15·W
Min Max Unit Test Conditions
rnA

0.2

2

ISB2

5

5

leel

30

30

Operating supply current lee2

70

90

Active supply current

Input leakage current

ISBl

-10

III

Output leakage current

ILiIO

-so

Output high voltage

VOH

2.4

Output low voltage

VOL

10
50

Typ

Unit

-10
-50

E1 =VIH orE2=VIL ..

10

rnA

E1 - VIL, E2 - VIH
VIN = V IH or VIL , lOUT = 0 rnA

rnA

Cycle = min., duty = 100%,
lOUT = 0 rnA

/-LA

V IN = OV to Vee

/-LA

VI/O = OV to Vee
E1 =VIH or E2=VIL or
G=VIHorW=VIL

50

2.4
0.4

E2S;0.2V, E1 ;;'Vcc -0.2V
(E2 "" 0.2V or E2 '" Vee - 0.2V

0.4

V

IOH = -1.0 rnA

V

IOL = 2.1 rnA

Note: All voltages are referenced to GND.

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

R_dCycle
Parameter

Symbol

MB8464-150X
MB8464·15·W
Min
Max

MB8464·20·W
Min
Max

ISO

200

Unit
ns

Read cycle time

TAVAX

Address access time

TAVQV

ISO

200

ns

El access time

TE1LQV

150

200

ns

E2 access time

TE2HQV

150

200

ns

Output enable to output valid

TGLQV

60

70

Output hold from address change

TAXQX

10

10

ns
ns

Chip enable to output low-Z

TE1LQX, TE2HQX

10

10

ns

Output enable to output low-Z

TGLQZ

5

5

ns

Chip enable to output high-Z

TEl HQZ, TE2LQZ

SO

60

ns

Output enable to output high-Z

TGHQZ

50

60

ns

3-146

MB8464·15·X
MB8464·15·W
MB8464·20·W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle Timing Diagrams
Read Cycle 1"·2

ADDRESS

~ ~-: : ~- : : ~- -~-A~X-Q~-X~=-~_~_·"~W_Q~_V~ '_CI~ _A-V_A-X: : _~: : - ~: : - :';-I- - ~ ~ ~ -~
.•

Q

-----

DATA VALID

PREVIOUS DATA VALID

Read Cycle If'

____

======_~X~~~~_-_~~

ADDRESS

1------

TAVQV ----....

~I

El

NOTES:

HIGH·Z

HIGH·Z

Q

DATA VALID

~ 1 W IS HIGH FOR READ CYCLE.
__
*2 DEVICE IS CONT1NUOUSLY SELECTED, E1
G
Vllo E2 = VIH·
*3 TRANSITION IS MEASURED AT THE POINT OF ± 500 mV STEADY STATE VOLTAGE.

=

=

[ZZ) DON'T CARE

lllJ UNDEFINED

Write Cycle

Parameter

Symbol

MB8464·15·X/
MB8464·15·W
Min
Max

Write cycle time

TAVAV

150

200

ns

Address valid to end of write

TAVWH
TAVE1L, TAVE2H

100

140

ns

Chip enable to end of write

TE1LE1H, TE2HE2L

100

140

ns

Data valid to end of write

TDVWH
TDVEI L, TDVE2H

50

60

ns

FUJITSU
3·147

MB8464·20·W
Min
Max

Unit

MB8484·1s.X
MB848401s.W
MB8464·20·W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cvcle (Continued)

MB8464·15.X/
MB8464·15·W
Max
Min

Min

MB846402o-W
Max

Unit

Parameter

Svmbol

Data hold time

TWHDX, TE1HDX,
TE2LDX

0

0

ns

Write pulse wid1h

TWLWH

90

100

ns

Address setup time

TAVWL, TAVEIL
TAVE2H

0

10

ns

Write recovery time

TWHAX TE1HAX
TE2LAX

5

5

ns

WrHe enable to output low-Z

TWHOX

5

5

Write enable to output high-Z

TWLOZ

50

ns
60

ns

Write Cvele Timing Diagrams
Write Cvele I

(W Controlled)

ADDRESS

1 + - - - - - - TE1LE1HI-----......~

TWLWH ----i~

w

D

HtGH-Z

DATA IN VAUD

1-__~1WHQX'I,2
Q

HIGH,z

NOTE: 'I IF G, E, AND EzARE IN THE READ MODE DURING THIS PERIOD, DO PINS ARE IN
THE OUTPUT STATE so THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE
OUTPUTS MUST NOT BE APPUED.
'2 TRANSITION IS MEASURED AT THE POINT OF ±5OO mV FROM STEADY STATE
VOLTAGE.

3-148

IZZI DON'T CARE
mUNDEFINED

MB84.... 15·X
MB8464·15·W
MB8464.2o-W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Diagrams (Continued)
Write Cycle 111151 Controlled)
~---------------------TAVAX--------------------~

ADDRESS

~----------------TAVE1L----------------~

1. .----------- TE1LE1HI------------.....,

. .- - - - - - - - - - - TE2HE2L ------------~

TWLWH

w

o
. .____.... TWHQX· 1,2

a

HIGH·Z

HIGH-Z

NOTE: 'I IF G, E, AND "iii ARE IN THE READ MODE DURING THIS PERloD,D/a PINS ARE IN
THE OUTPUT STATE so THAT THE INPUT SIGNALS OF opPOSrrE PHASE TO THE
OUTPUTS MUST NOT BE APPUED.
*2 TRANsmON IS MEASURED AT THE POINT OF ± 500 mV FROM STEADY STATE

VOLTAGE.

FUJITSU
3·149

rzzJ DON'T CARE
~UNDEFINED

MB8464·15-X
MB8464.15-W
MB8484-200W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Diagrams (Continued)
Write Cycle III (E2 Controlled)
~----------------------TAVAX----------------------~

ADDRESS

i--------------TAVE2H---------------t

1----------- TE1LE1H

-------------t

1------------ TE2HE2L ------------+1

1----------

TWLWH

---------+I

w
TDVE2H

HIGH-Z

DATA IN VAUD

D

r.----..j TWHQX '1,2
Q

HIGH-Z

HIGIl-Z

NOTE: 'I IF G, Ea, AND W ARE IN THE READ MODE DURING THIS PERIOD, DQ PINS ARE IN
THE OUTPUT STATE SO THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE
OUTPUTS MUST NOT BE APPUED.
*2 TRANSITION IS MEASURED AT THE POINT OF :!:500 mY FROM STEADY STATE

VOLTAGE.

3-150

E72I DON'T CARE
I2Qg UNDEFINED

MB8484-15-X
MB8484-15-W
MB8464-200W

Data Retention
Characteristics
(Recommended operating
conditions unless otherwise
noted)

Parameter

Symbol

Min

Ma.

Unit

Data retention supply voltage"

V OR

2.0

5.5

V

MB8464-15/20-W

0.5

rnA

MB8464-15-X

0.05

rnA

Data retention supply currenf 2
Data retention setup time

TE1HVL
TE2LVL

0

ns

Operation recovery time

TVHE1L
TVHE2H

TAVAX

ns

Not.. :

*'

:

~~ :=:::~~ ~ ~.~~ -O.2V (E2 ,,;; O.2V or E2 ~ VOR -D.2V)

*2 E2 controlled: VOR "" 3.aV, E2 ... O.2V
~11 controlled: VOR "" 3.aV, 'E11 ~ VOR -O.2V (E2 .,;; O.2V or E2

;a,

VOR -O.2V)

Data Aetentlon Timing
Data Retention I lEa Controlled)
DATA RETENTION MODE---.....,~

•

vee

4.5V

=t-

E.

,

4.SV
~

"---------~

I

O.4V

Data Retention II

IE,

Controlled)
I~.t----DATA

Vee

RETENTION MODE - - -......~

4.5V

,'-

i---

E,

v

4.5V

_ _ _ _ _D~ _ _ _ - - . /

I

'~

'DRS

-1 \'--________
-'--'.;.;....__________~
_

2.2V I
---./

E1

;?-

VOR -O.2V

2.2V

.

AC Test Conditions
Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Reference Levels:

0.4Vto2.6V
5 ns (Transient Time between
0.6Vand 2.4V)
Input: VIL = 0.6V, VIH = 2.4V
Output: VOL = O.BV, VOH = 2.0V

< OUTPUT LOAD >
+5V

Output Load:
OUTTiR'
(I/O)
R,

Ra

CL

Paramater8
Measured

CL'I

":"

R.

H.-pt TE1LQX
Load I

1.8KO

99CJ(l

Load II

I.SKU

9900

100pF

5pF

TE1HOZ, TE2LOZ,
TGHOZ, TWLOZ, and
TWHQX
TEl LOX,
TEl HOZ, TE2LOZ,
TOHQZ, TWLQZ, and
TWHQX

FUJITSU
3-151

'INCLUDING PROBE AND STRAY CAPACITANCE

MB8464·150X
M88464·150W
MB846+200W

P.cka•• Dlmen.lons
Dimensions in inches
(millimeters)

28.L••d PI••lic DueI.ln·Lln. Peck•••
IC... No.: DIP·28P.M02)

I

.533 (13.54)

INDEX

1~=====~:;;:::===;;2=======~IJ4'0~
1.389 (35.28)
1A15 (35.94)

~I

W.l97

(5.00) MAX.

- p . 1 1 S (3.00) MIN.

.020 (0.51) MIN.

28.L_d PI••llc FI.I P.ck•••
IC••• No.: FPT·28P-M01)

l~
.287(7.3)

1.!;;:::;;::;;;::;::;=;n=n=n=::;;::::;;:::;;=;:M;=;;;:::~~7,B)

DETAILS DF "1/1' PART

.024(0.8)
.007(0.18)

MAX
.027(0.68)

MAX

3-152

MB848401s.X
MB....... 1s.W
MB.......2o-W

Packa.e Dlmen.lon.
(Continued)
Dimensions in inches
(millimeters)

32·Pad Ceramic IMetal Seal) Leadle•• Chip Carrier
ICa.e No.: LCC·32C.A02)
·PIN 1 INDEX
C.015(0.38)TVP

/

.445(11.30)
.460(11.88)
3.6O(9.14)TYP

28·Lead Ceramic Dual·ln·Llne Packa.e
ICa.e No.: DIP.28C.A07)

050(1.27) REF

~C=
INDEX AREA

..... ~

D

.S9O(14.99)
.610(IS.49)

.58S(14.86)
.605(15.37)

.1

1.386(35.20)
1.414(35.92)

t

.008(0.20)
.012(0.30)

- I m m n MAX
mm.061(1.55)

~ ___!_
I•.

-II •.

090(2.29)
0IS(0.38)
.110(2.79)
.023(0.58)
1.300(33.02) REF

___

·SHAPE OF PIN 1 INDEX, SUBJECT TO CHANGE WITHOUT NonCE

3-153

II

.040(1.02)

t

t.2OO(S.08) MAX

+ .120(3.0S)

..:..06.:..;0c:.(I"'.5:::2)'--_ _ _L! .150(3.81)
.046(1.17)
.054(1.37)

Preliminary

FUJITSU

MOS Memories
•

MB8464A· 70, MB8464A· 70L, MB8464A· 70LL
MB8464A-10, MB8464A-10L, MB8464A-10LL
MB8464A-15, MB8464A-15L, MB8464A-15LL
8,192 Words x 8-Bit CMOS
Static RAM with Low Power
and Data Retention

Description
The Fujitsu MB8464A is a 8,192-word by 8-bit static random
access memory fabricated with a CMOS silicon gate process.
The memory utilizes asynchronous circuitry and may be maintained in any state for an indefinite period of time. All pins are TTL
compatible, and a single +5V volt power supply is required.
The MB8464A is ideally suited for use in microprocessor systems
and other applications where fast access time and ease of use are
required. The MB8464A offers the advantages of low power dissipation, low cost, and high performance.

Features
• Organization:
8,192 words x 8-bits
• Fast access time:
TAVQV ~ TElQV ~ 70 ns max.
(MB8464A-70/70L/70LL)
TAVQV = TE1QV = 100 ns max.
(MB8464A-l 01 101/1 Oll)
TAVQV ~ TElQV ~ 150 ns max.
(MB8464A-15/15L/15LL)
• Completely static operation:
No clock required
• TTL compatible input/output
• Three-state output

• Common data input/output
• Single +5V power supply,
±10% tolerance
• Low power standby:
11 mW max. (70110/15)
0.55 mW max. (70l/10L/15L)
(70LL/l0LL/15LL)
• Data retention: 2.0V min.
• Package
28 pin DIP 600 mil, 300 mil
28 pin plastic flatpak
32 pin LCC

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

3-154

MB8484A·70
MB8484A·70L
MB8484A·70LL
MB8484A·10
MB8484A.10L

MB8484A.10LL
MB8484A·15
MB8484A·15L
MB8484A.15LL

MB8464A Block Diagram
and Pin Assignments

---0

Vee
NC

Vee

256x32x8

A"

W-

MEMDRYCELL
ARRAY

A7

E,

A,

Ao

--avss
ADDRESS
BUFFER

ROW
DECODER

E

w
D01
DO.

00,

DO,

DOs

DO.

oeq

Do"

As

A.

Ao

An

Ao

G

A,

A,.

A,

E,

Ao

Dar

DO.

DOo

DO,

DO.

DO,

DO.

V"

DO,

TRUTH TABLE

.t"C' Uz ~ ~ l~
N

E,

~

G

W

MODE

H

X

X

X

NOT SELECTED

X

L

X

X

NOT SELECTED

ISB

HIGH-Z

L

H

H

H

OUT DISABLE

ICC

HIGH·Z

SUPPLY CURRENT

"0 PIN

ISB

HIGH-Z

L

H

L

H

READ

ICC

°OUT

L

H

X

L

WRITE

ICC

IN

tr

~ ~!~! ~ i:?·2!32!3..°!
As
As

s.!

:2..9 As
:2! At
'27 A"

..

6..!

A~ ~!
A3

a..!

~

9 •

~~ Me

-.

.-..-.-

(Top VIEW)

'25
'24
'23
'22
'2,

,0'
Ao ii:

A,

..

Ne ,2'
I/O, ,3'

~

I5E

A,o
CS,

Vo"
'/~

1';1;; 1'6; '-7; 18; t9;20~
N

~"

~~~

li!

...

~

~

~.g..g.

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Ceramic

-65 to +150

Plastic

-45 to +125

·C

Storage temperature range

tSTG

Temperature under bias

t SIAS

-10 to +85

·C

Supply voltage

Vee

-0.5 to +7.0

V

Input voltage

V ,N

-O.S'toVee +0.5

V

Output voltage

V OUT

-0.5 to Vee +0.5

V

• -2.0 V for pulse width less than 20 ns.
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Recommended Operating
Condltl_s
(Referenced to V ss )

Parameter

Symbol

Min

Typ

Max

Supply voltage

Vee

4.5

+5.0

5.5

V

Input low voltage

V,L

-2.0'

0.8

V

Unit

Input high voltage

V,H

2.2

Vee +0.3

V

Ambient temperature

tA

0

70

·C

--2.0V Min. for pulse width less than 20 ns. (VIL Min. = -0.3 V at DC level)

FUJITSU
3-155

MB8464A·70
MB8464A·70L
MB8464A.70LL
MB8464A·10
MB8464A·10L

MB8464A·10LL
MB8464A·15
MB8464A·15L
MB8464A.15LL

Capacitance
(TA = 25°C, f = 1 MHz)

Symbol

Parameter

= OV)
Input capacitance (V'N = OV)
I/O capacitance (Vila

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Min

Typ

C'iO
C'N

Max

Unit

B

pF

6

pF

MB8464A·
MB8464A· 70L/10L/15L
70/10
70LL/10LL/15LL
Symbol Min
Max Min
Max Unit Test Conditions

Parameter
Standby supply current

ISB'

2

0.1

ISB2

3

3

mA

E2 ", 0.2V, E, "> Vcc - 0.2V
(E2 '" 0.2V or E2 ." Vcc - 0.2V)
E,

= V,H or E2 = V,L

Icc,

55

55

mA

E, = V,L' E2 = V,H
Y'N = V,H or V,L, lOUT

Operating supply current Icc2

65

65

mA

Cycle = min., Duty
lOUT = a mA

/LA

Y'N

Active supply current

Input leakage current

-1

lu

Output leakage current

IUIO

-2

Output high voltage

VOH

2.4

Output low voltage

VOL

-1
2

-2

= OV to Vcc
= OV to Vcc
~, = V,H or..§2 = V,L or
G = V,H or W = V,L
IOH = -1.0 mA
1m = 2.1 mA
'!.'IO

2

/LA
V

2.4
0.4

= a mA
= 100%,

0.4

V

Note: AU voltages are referenced to VSS

AC Test Conditions
Input pulse levels:
Input pulse rise and fall times:
Timing reference levels:

0.6V to 2.4V
6 ns (transient time between O.BV and 2.2V)
Input: V,L = O.BV, V,H = 2.2V
Output: VOL = O.BV, VOH = 2.0V

Output load:


Parameters

R,

R2

CL

Load 1

1.8n

99011

'DO pF

Load II

1.80

99011

5 pF

Measured

except TE1 LQX,

TE2HOX, TE1HOZ,
TE2LOZ, TGHOZ
TWHOK, TWLQZ
TEl LOX, TEl LOZ,
TELQZ, TEl HOZ,
TE2LOZ, TGHOZ,
TWLOZ, TWHOX

+sv

~~::
'INCLUDING PROBE AND STRAY CAPACITANCE

3·156

.B8484A-70
.B8484A-70L
.B8484A-70LL
.B8484A-10
.B8484A·1OL

. . .484A·1OLL
.B8484A-18
.B8484A·1SL
MB8484A-18LL

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

MB8464A
.70/70L/70LL
Min
Max

Read cycle time

TAVAX

70

Address access time

TAVQV

70

100

150

ns

E, access time

TE1LQV

70

100

150

ns

E2 access time

TE2HQV

70

100

150

ns

Output enable to
output valid

TGLQV

MBMMA
·100/100L/100LL
Min
Max

M88484A
.1S0/1SOL/150LL
Min
Max

Unit

100

150

ns

45

35

Output hold from
address change

TAXQX

10

10

Chip enable to
outputlow-Z"

TE1LQX
TE2HQX

10

10

Output enable to
outputlow-Z"

TGLQZ

5

5

Chip enable to
output high-Z"

TE1HQZ
TE2LQZ

35

35

Output enable to
output high-Z"

TGHQZ

30

35

Note:

*

55
10

ns
ns

10

ns

5

ns
40
40

ns
ns

11'ansition is measured at the palnt of ±SOO mV from steady.

Raad Cycle Timing Diagrams
R_d Cycle 1"'.2

ADDRESS

Q

=t!

TAVAX

TAVQV
TAXQX

PREVIOUS DATA VALID

.1

.1

~
DATA VALID

~DON·TCARE

!OO UNDEFINED

FUJITSU

3-157

MB8404A-70
MB8404A-70L
MB8404A-70LL
MB8404A-10
MB8404A-10L

MB8404A-10LL
MB8484A-15
MB8484A-15L
MB8484A-15LL

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted,)

Read Cycle 11"1

ADDRESS

~1----_TAYAX_~_
..- - - . l 1

-1f<~~---~TAYQV----"'-~'

Q

Notes: "1 W IS HIGH FOR READ CYCLE,
*2 OEVICE IS CONllNUOUSLY SELECTED, E1 =

G = VIL,

E2

= VIH.

IZLl DON'T CARE
IZZJ UNDEFINED

3-158

MB8484A·70
MB8484A·70L
MB8484A.70LL
MB8484A·10
MB8484A·10L

MB8484A·10LL
MB8484A·15
MB8484A·15L
MB8484A·15LL

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle

Parameter

MB8484A
.70/70L/70LL
Symbol Min
Max

MB8464A
·1 OO/100L/1OOLL
Max
Min

MB8464A
.150/150L/150LL
Min
Max

Unit

Write cycle time

TAVAX

70

100

150

ns

Address valid to
end of write

TAVWH
TAVE1L
TAVE2H

60

80

100

ns

Chip enable to end TE1LE1H
60
of write
TE2HE2L

80

100

ns

Data valid to end
of write

TDVWH
TDVE1L
TDVE2H

30

35

40

ns

Data hold time

TWHDX
TE1HDX
TE2LDX

5

5

5

ns

Write pulse width

TWLWH

60

70

90

ns

0

0

0

ns

TWHAX
Write recovery time TEl HAX 10
TE2LAX

10

10

ns

Write enable to
output low-Z·

TWHQX

5

5

ns

Write enable to
output high-Z·

TWLQZ

TAVWL
Address setup time TAVEl L
TAVE2H

5
30

"Transition is measured at the point of ± 500 mV steady state voltage.

FUJITSU
3-159

35

40

ns

MB8484A.70
MB8484A·70L
MB8484A·70LL
MB8484A.10
MB84.4A·10L

MB8484Ao10LL
MB8484A.15
MB8484A.15L
MB8484A.15LL

AC Characteristics
(Continuect)
(Recommended operating
conditions unless otherwise
noted.)

Write

C~cle

Timing Diagrams

Write C~cle I (Vi Controlled)

~--------------------TAVAX--------------------~

ADDRESS

1·4.----------------TAVWH--------------~

j4------TE'LE'HI----------~

~-----TE2HE2L.---------_+i

TWlWHI------<~

D

HIGH-Z

DATAINVAUD

I+----;~ TWHOX"

o
Note: "

HIGlf.Z
IF il, ~, AND

Eo ARE IN THE READ MODE DURING THIS PERIOD, DO PINS ARE IN

THE OUTPUT STATE SO THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE

OUTPUTS MUST NOT BE APPUED.

3-160

t?Z1~CARE

~UNDEFINED

MB8484A·70
MB8484A.70L
MB8484A·70LL
MB8484A·10
MB8484A·10L

MB8484A·10LL
MB8484A·15
M1J8484A.15L
MB8484A.15LL

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle II

IE.

Controlled)
~--------------------TAVAX--------------------~

ADDRESS

E,

j.---------TWLWH---------+i

w

o

HIGH-Z

DATA IN VALID

HIGH.z

o

e..

Note: ·1 IF ll,
AND Vi ARE IN THE READ MODE DURING THIS PERIOD, DO PINS ARE IN
THE OUTPUT STATE SO THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE
OUTPUTS MUST NOT BE APPLIED.

FUJITSU

3-161

!ZJ DON'T CARE
~UNDEFINED

MB8464A·70
MB8464A·70L
MB8464A.70LL
MB8464A·10
MB8464A·10L

MB8464A·10LL
MB8464A·15
MB8464A·15L
MB8464A·1 ~LL

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted,)

Write Cycle III (E2 Controlled)
~---------------------TAVAX----------------------~

ADDRESS

E,

E,

~---------TWLWHI--------~~

w

DATA IN VALID

D

HIGH·Z

HIGH·Z

a
Note: *1 IF G, E1 AND W ARE IN THE READ MODE DURING THIS PERIOD, DQ PINS ARE IN
THE OUTPUT STATE SO THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE
OUTPUTS MUST NOT BE APPLIED.

3·162

t'ZLl DON'T CARE
~UNDEFINED

MB8464A-70
MB8464A-70L
MB8464A-70LL
MB8464A-10
MB8464A-10L

MB8464A-10LL
MB8464A-15
MB8464A-15L
MB8464A-15LL

Data Retention
Characteristics
(Recommended operating
conditions unless otherwise
noted)

Typ

Min

Symbol

Parameter

Data retention supply voltage"'

2.0
Standard

Data retention supply currenf 2

L-Version-3 /LL"4

1.0

Data retention setup time

TE1HVL
TE2LVL

o

Operation recovery time

TVHE1L
TVHE2H

TAVAX

Max

Unit

5.5

V

1.0

ma

25/2

I"A
ns

Notes: *1 E2 controlled: E2 "'" O.2V
E1 controlled: E1 "'" VOR - O.2V (E2 ""'" O.2V or E2

il'

V OR - O.2V)

'2 E2 controlled: V OR = 3.0V, E2 .,,; O.2V
E1 controlled: VDR = 3.0V, E1 :e< VOR - O.2V (E2 .,,; O.2V or E2 ~ VOR - O.2V)

*3 For TA = 0° to 70 0 e
·4 For T A = QGe to 40"C, VDA = 3.0 V

Data Retention Timing
Data Retention I

IE. Controlled)

J - - - - - DATA RETENTION MODE ----~
4.SV

vee

4.SV

I

VOR

Data Retention II

IE,

Controlled)

I~..
. - - - - - DATA RETENTION MODE -----i~

4.SV

vee

\L

4,5V

___ _

VOR

_ _ -.J I

rzL) DON'T CARE

rlil UNDEFINED

FUJITSU

3-163

MB8484A.70
MB8484A.70L
MB8484A·70LL
MB8484A·10
MB8484A.10L

MB8484A·10LL
MB8484A.18
MB8484A·1 SL
MB8484A.1 SLL

Package Dimensions
28·Lead Plastic Dual In.Llne Package
ICase No.1 DIP-28P-M021

Dimensions in inches
(millimeters)

I

.533(13.54)

INDEX

~~~~J4.0~
1.389(35.28)
1.415(35.14)

~I

--t-t

UI197(5.00)MAX
118(3.00)MIN

.020(0.51)MIN

28.L_d Plastic Dualln.Llne Package
ICase No.: DIP.28P.M041

0.008

(0.20)
0.012

(0.30)

1AOO(35.56)
1.374(34.91)

~--'1+--.--t--SEATING PLANE.

0.118 MIN
(3.0)

0.050 MAX
(1.27)

3·164

MB8484A-70
MB8484A-70L
MB8484A-70LL
IIB8484A-10
IIB8484A-10L

MB8484A-10LL
MB8484A-15
IIB8484A-15L
IIB8484A-15LL

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

28-Lead Plastic Flat Package
(Case No.: FPT·28P.M02)

OIOIMIN
ISTAND OFFI

VIEW A

.00810.21

J

.00810.181
MAX
.02710.681
MAX

Detail of "A" part

32·Pad Ceramic (Metal Seal) Leadless Chip Carrier
(Case No.: LCC.32CoA02)
·PlN 1 INDEX
C.OI5(O.38)TYP

/
0

.545(1

.S6OiI

.445(11.30)
.480(11.68)

·SHAPE OF PIN 1 INDEX: SUII.JECT TO CHANGE WITHOUT NOTICE

3-165

3.6O(9.14ITYP

Preliminary

FUJITSU

MOS Memories
•

MB8464A.10·W, MB8464A·15·W
CMOS 65,536-Bit Static
Random Access Memory
with Data Retention Mode

Description
The Fujitsu MB8464A-W is a 8,192-word by 8-bit static random
access memory fabricated with a CMOS silicon gate process.
The memory utilizes asynchronous circuitry and may be maintained in any state for an indefinite period of time. All pins are TTL
compatible, and a single + 5 volt power supply is required.
The MB8464A-W is ideally suited for use in microprocessor systems and other applications where fast access time and ease of
use are required. All devices offer the advantages of low power
dissipation, low cost, and high performance.

Features
• Organization: 8,192 words
•
x 8-bits
•
• Fast access time:
TAVQV = TELQV = 100 ns max.•
(MB8464A-l0-W)
TAVQV = TELQV = 150 ns max_.
•
(MB8464A-15-W)
• Completely static operation:
No clock required
• TTL compatible input/output
•
• Three-state output
•

Common data input/output
Single +5V power supply,
± 10"'{' tolerance
Low power standby:
11 mW max.
Data retention: 2.0V min.
28-pin ceramic package
(300 mil width)
(600 mil width)
32-pad leadless chip carrier
Pin compatible with MB8464-W

3-166

MB8464A·1G-W
MB8464A·I5-W

MB8464A·W Block Diagram
and Pin Assignment
A,.
AI1
A,.

As

ADDRESS
BUFFER

A,
A,

--0

Vee

----0

Vss

256x32x8

ROW
DECODER

MEMORY CELL
ARRAY

As
A,

As

A,
A.
A,

A"

G

0/0, 0/0, 0/0, 0/0,
0/0. 0/02 0/04 0/0.

Vee
W

A,

E.

As

As

A,

As

A.

AI1

A,

G

A.

A,.

A,

E,

A"

0/0,

0/00

D/Ils

0/0,

0/0,

E

W

NC
A,.

0/0.

O/a.

Vss

0/0,

TRUTH'mBLE
El

EZ

G W

MODE

SUPPLY CURRENT

I/O PIN

H

X

X

X

NOT SELECTED

'SB

HIGH-2

X

L

X

X

NOT SELECTED

ISB

HIGH-Z

L

H

H

H

OUT DlSABLE

ICC

HIGH-z

L

H

L

H

READ

ICC

L

H

X

L

WRITE

ICC

°OUT
IN

W
E.

i 2 ~ 1 !32!31;30:
L--'----- :------ --0

I

4 :3

A,

As

!

:-29
i-i8
:27

i

: 26

NC

5 i

s- -:
--~

As

7
--I

A,

8

A.

9-1

A,

!~J

A"
NC

0/00

iL __

I

---I

As

.---

A,
AI1

!

[25
L __
! 24
fi3-

~~J
!!J

r22-

0/0,

[~~

0/0,

11

TOP VIEW

G
A,.

E,

r--I---' ---,- --1--,---1---'
: 14 115 i16 : 17:18 119:20:

Absolute Maximum Ratings
(See note)

Ratin!

51mbol

Value

Unit

Storage temperature range

TSTG

-65 to +150

Temperature under bias

T B1AS

-55 to +125

·C
·C

Supply voltage

-0.5 to +7.0

V

Input voltage

Vee
V,N

-0.5 to Vee + 0.5

V

Output voltage

VOUT

-0.5 to Vee + 0.5

V

Note: Perman~nt device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

FUJITSU
3·167

MB8484A·100W
MB8484A·15-W

Recommended Operating
Conditions
(Referenced to GND)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vce

4.5

5.0

5.5

V
V

Input low voltage

VIL

-0.3

0.6

Input high voltage

V IH

2.4

Vcc + 0.3

V

Ambient temperature

TA

-55

+125

'C

Capacitance
(TA

= 25'C, f =

1 MHz)

Parameter

Symbol

= OV)
(VIN = OV)

Min

Max

TZP

Unit

I/O capacitance (VIIO

CliO

8

pF

Input capacitance

CIN

6

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter
Standby supply current

MB8464A·10·W
MB8464A·15·W
Min
Max

Unit

Test Condition

1881

Symbol

2

rnA

E2 .. 0.2V, E1 .. Vcc - 0.2V
(E2 .. 0.2V or E2 .. Vee - 0.2V)

ISB2

5

rnA

E1

=

VIH or E2

=

VIL

Active supply current

Icc1

70

rnA

El = V IL, E2 = V IH
VIN = VIH or V IL , lOUT

Operating supply current

Icc2

90

rnA

Cycle = min., duty
lOUT = 0 rnA

Input leakage current

III

10

/LA

VIN

/LA

~IO = OV to Vcc
g1 = VIH 0~2 = V IL or
G = VIH or W = VIL

V

IOH

V

IOL

Output leakage current

-10

ILiIO

-50

Output high voltage

V OH

2.4

Output low voltage

VOL

Note: All voltages are referenced to

vss

50

0.4

=

= 0 rnA
100%,

= OV to Vce

= -1.0 rnA
= 2.1 rnA

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle

Parameter

Symbol

MB8464A·10·W
Min
Max

MB8464A·15·W
Min
Max

Unit

Read cycle time

TAVAX

100

150

ns

Address access time

TAVQV

100

150

ns

E1 access time

TE1LQV

100

150

ns

E2 access time

TE2HQV

100

150

ns

Output enable to output valid

TGLQV

45

60

ns

Output hold from address change

TAXQX

10

10

ns

Chip enable to output low-Z'

TE1LQX
TE2HQX

10

10

ns

Output enable to output low-Z'

TGLQZ

5

Chip enable to output high-Z'

TE1HQZ
TE2LQZ

40

50

ns

Output enable to output high-Z'

TGHQZ

40

50

ns

Note: "Transition is measured at the point of + 500 mV from steady state voltage.

3-168

ns

5

MB8464A·10·W
MB8464A·15·W

AC Charactarlstlcs
(Conti nued)
(Recommended operating
conditions unless otherwise
noted)

Raad Cycle Timing Diagrams
Read Cycle 1",·2

~,,~, -f. :~t- _~=-_.~=-__=-__~"_lI-V_Q-v~ _"_lI_V_"X=-_~=- _~ ~." I-_~-_-_-_-_-_-~

II

Q

_ _ __

TAXQX---__I

PREVIOUS DATA VALID

DATA VALID

Read Cycle 11"'

'""=

~==-=-=-TA_.~_,~~~~_

~~'-'------TAVQV----;'~'

ii,

E,

Q

HIGH-Z

HIGH-Z

DATA VALID

NOTES: *1 W IS HIGH FOR READ CYCLE.

__

~2 DEVICE IS CONTINUOUSLY SELECTED, E1

=

G

= Vll, E2 = VIH·

"3 TRANSITION IS MEASURED ATTHE POINT OF ± 500 mV STEADY STATE VOLTAGE.

FUJITSU

3-169

[22] DON'T CARE

f2ICil UNDEFINED

MB8464A·1G-W
MB8464A·15-W

AC Characterletlce
(Continued)
(Recommended operating
conditions unless otherwise
noted)

Write Cycle
Parameter

Symbol

MB8464A·10·W
Min
Max

MB8464A·15·W
Min
Max

Unit

Write cycle time

TAVAX

100

150

ns

Address valid to end of write

TAVWH, TAVE1L,
TAVE2H

80

100

ns

Chip enable to end of write

TE1LE1H,TE2H2EL

80

100

ns

Data valid to end of write

TDVWH, TDVEI L,
TDVE2H

40

50

ns

Data hold time

TWHDX, TEl HDX,
TE2LDX

5

5

ns

Write pulse width

TWLWH

60

70

ns

Address setup time

TAVWL, TAVEl L,
TAVE2H

0

10

ns

Write recovery time

TWHAX, TE1HAX,
TE2LAX

10

10

ns

Write enable to output 10w·Z·

TWHOX

5

5

Write enable to output high-Z·

TWLOZ

'TRANSITION IS MEASURED AT THE POINT OF ±500 mV STEADY STATE VOLTAGE.

3-170

40

ns
50

ns

MB8464A-10-W
MB8464A-15-W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted)

Write Cycle Timing Diagrams
Write Cycle I

ADDRESS

Iii Controlled)

?F~--~TAVWH_TAVAX- j t~~.j1------

TE1LE1H------+j

E,

TWLWH

D

----+I

HIGH-Z

DATA IN VALID

i.----+lTWHQX'1,2

Q

HIGH-Z

NOTE: *1 IF G, E1 AND E2ARE IN THE READ MODE DURING THIS PERIOD, DQ PINS ARE IN
THE OUTPUT STATE SO THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE

EZ2l DON'T CARE

OUTPUTS MUST NOT BE APPLIED_
*2 TRANSITION IS MEASURED AT THE POINT OF ±500 mV FROM STEADY STATE

VOLTAGE.

FUJITSU

3-171

mUNDEFINED

MB8464A.10.W
MB8464A.15·W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted)

Write Cycle II IE1 Controlled)
I------------TAVAX------------+I

ADDRESS

1---------TAVE1L---------.!

1.------

TE1LE1HI---------i~

i-------

TE2HE2L

E,

TWLWH

w
TDVE1L

i----I

D

HIGH-Z

DATA IN VAUD

D

TWHDX'1,2

HIGH-l

HIGH-Z

NOTE: '1 IF G, ~ AND W ARE IN THE READ MODE DURING THIS PERlOD,DID PINS ARE IN
THE OUTPUT STATE so THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE
OUTPUTS MUST NOT BE APPUED.
'2 TRANSITION IS MEASURED AT THE POINT OF ±500 mV FROM STEADY STATE
VOLTAGE.

3·172

rzZJ DON'T CARE
~UNDERNED

MB8464A·10·W
MB8464A·15·W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted)

Write Cycle III (E2 Controlled)
~---------------------TAYAX----------------------~

ADDRESS

~--------------TAY~H--------------~~

1-44----------

TE1LE1H ------------~

1----------- T~HE2L ----------~~
E.

~--------

TWLWH --------~

w
TDYE2H

HIGH-Z

DATA IN YAUD

D

i+-----ITWHOX'I,2

o

HIGH-Z

HIGH-Z

NOTE: 'I IF G, Eo. AND W ARE IN THE READ MODE DURING THIS PERIOD, DO PINS ARE IN
THE OUTPUT STATE so THAT THE INPUT SIGNALS OF OPPOSITE PHASE TO THE
OUTPUTS MUST NOT BE APPUED.
'2 TRANsmON IS MEASURED AT THE POINT OF ±500 mY FROM STEAOY STATE
YOLTAGE.

Data Retention
Characteristics
(Recommended operating
conditions unless otherwise
noted)

E7J DON'T CARE
(2Qg UNDEFINEO

Parameter

Symbol

Min

Max

Unit

Data retention supply voltage'l

V OR

2.0

5.5

V

Data retention supply current'2

Standard

0.5

lOR

Data retention setup time

TEl HVL, TE2LVL

0

Operation recovery time

TVHE1L, TVHE2H

TAVAX

Not. .: ·1 E2 controlled: E2 .... O.2V

~, controlled: ~, '" VOR - O.2V (~ " O.2V or E2 " VOR - O.2V)
'2 E2 controlled: VOR - 3.0V, E2 " O.2V
E1 controlled: VOR

=

3.0V, E1

$!o

VOR - O.2V (E2 '" O.2V or E2 ~ VOR - O.2V)

FUJITSU

3·173

mA
ns

MB8464A·1G-W
MB8464A·15·W

Data Retention
Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted)

Data Retention Timing
Data Retention I IE2 Controlled)

1 4 - - - - - DATA RETENTION MODE - - - - - I

4.SV

Vee
,

VOR

'------

=t~

E2

0.4V

Data Retention"

lEI

Controlled)

14-----DATA RETENTION MODE - - - - .

4.5V

Vee

\

~ID~

'"

4.5V

'---- -

VDR

/

-

----I

I~

J-1I \\.
. _________....:.._=___________~
2.2V

E1"'YDR-O.2V

.

2.2V

AC Test Conditions
< OUTPUT LOAD >

Input Pulse Levels:
O.4V to 2.6V
Input Pulse Rise and Fall Times: 5 ns (Transition time between O.6V and ~2.4v)
+sv
Tlmmg Reference Levels:
Input: V IL ~ O.6V, VIH ~ 2.4V
Output: VOL ~ O.BV, V OH ~ 2.0V
Output Load:
R,
OUT

(I/O)
PARAMETERS MEASURED

Rl

R2

CL

LOAD I

1.8 K!l

9900

l00pF

LOAD II

1.8 K!l

9900

SpF

EXCEPT TEHQX, TGLQZ,
TEl HQZ. TGHQZ. TWHQX
ANDTWLQZ
TEl LQX. TGLQZ, TEl HQZ.
TGHQZ. TWHQX AND
TWLQZ

3·174

C.'r
-=-

R2

-=-

'INCLUDING PROBE AND STRAY CAPACITANCE

M88464A·10·W
M88464A·15·W

Package Dimensions
Dimensions in inches
(millimeters)

28·Lead Ceramic Dual·ln·Llne Package
(Case No.: DIP.28C.A07)

050(1.27) REF

~C=

-----...~
I~

INDEX AREA

-*r_~<~

l

D

585(14'86)
.605(15.37)

[

•t -

.1

1.386(35.20)
1.414(35.92)

.610(15.49)

.008(0.20)
.012(0.30)

'061(1'55)MAX

~~ ___;_
I_

II_

.090(2.29)
__
.015(0.38)
.110(2.79)
.023(0.58)
1.300(33.02) REF

~I

t

t

.200(5.08) MAX

t

.040(1.02)
.120(3.05)
- 2.....:..5
) _ _ _ _"- .150(3.81)
"".06-"0;,,:(_1
.046(1.17)
.054(1.37)

32·PAD Ceramic (Metal Seal) Leadless Chip Carrier
(Case No. LCC·32C·A02)
·PIN 11NOEX

C.015(0.38)TYP

/

.445(11.30)
.460(11.88)
3.6O(9.14)TYP
·SHAPE OF PIN 1 INDEX, SUBJECT TO CHANGE WITHOUT NOTICE

3-175

.Ba484A·10·W
.Ba484A·1S·W

Package Dimensions
(Continued)
Dimensions in inches
(millimeter)

la·L.ad Ceramic ( ....1. . .1) Dulin-Lin. Packag.
(Case No.: DIP-2ac.AOa)

~:::,l ~~ :,:;,: ~[~ ~ ~p~
1.420136.071

ffifOj
J

.09012.291
.11012.791

.04011.021
.06011.S21

-11

1.300133.02IREF

3-176

.01SI0.381
.02310.581

.04011.021
.060I1.S21

.200IS.08IMAX
.12013.0SI
.15013.811

.01210.301

Preliminary

FUJITSU

MOS Memories
•

MB84256-10, MB84256-10L,
MB84256-15, MB84256-15L
CMOS 262,144-Bit Static
Random Access Memory
with Data Retention Mode

Description
The Fujitsu MBB4256 is a 32,766-words by 8-bits static random
access memory fabricated with a CMOS silicon gate process. The
memory utilizes asynchronous clrcu~ry and may be maintained in
any state for an indefinite period of time. All pins are TTL compatible, and a single +5 volt power supply is required.
The MB84256 is ideally suited for use in microprocessor systems
and other applications where fast access time and ease of use are
required. All devices offer the advantages of low power dissipation,
low cost and high performance.

F••tures
• Organlzstlon:
32,766 worda x B-blts
• Fast access time:
TAVQV TELQV
100 ns max.
(MB84258-10/10L)
TAVQV TELQV
150 ns max.
(MBB4256-15/15L)
• Completely static operation:
No clock required
TTL compatible Input/output
• Three-state output

=

=

=

=

• Common data Input/output
• Single +5V power supply
±10% tolerance
• Low power standby:
5.5 mW max. (MB84258-10/15)
1.1 mWmax.
(MBB4258-10L/15L)
• Data ratentlon: 2.0V min.
• Stsndard 211-pln DIP (BOO mil)
• Standard 2B-pln Plaatlc Flat
pack (450 mil)
• Standard 32-pad LCC

This device contains circuitry to
protect the inputs against damage
due to hlg1 static voltages or electric fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

3-177

MB84256·10
MB84256·10L
MB84256·15
MB84256·15L

MB84256 Block Diagram
and PIn Assignments

A'4~--'

--0

Vee

Vee

A13

A,.

A"

A"
A,

A,.

ADDRESS
BUFFER

512 x 64 x 8
MEMORY CELL
ARRAY

ROW
DECODER

A"

A.

A"

A"

A,.
E

G

Ao

D/Or

0/00

0/00

E

w
0/00 D/O:! D/a. 0/00
DID, 0/00 DID, DID,

0/Q1

0/0,

DID.

DID,

v.s

0/00

RUTH TABLE
E

G

W

MODE

H

X

X

NOT SELECTED

ISB

HIGH-Z

L

H

H

OUT DISABLE

ICC

HIGH-l

L

L

H

READ

ICC

QOUT

L

X

L

WRITE

ICC

IN

SUPPLY CURRENT

1/0 PIN
A,

: 4 : 3: 2: 1 :32:31:30 1

..

5--1

A,

~]

A.

7

l--}---'---'

L-~I--..!--i

.

A,
A,

W

NC

A"

L __'

:-2i
r,--

!

'27

i-a

a-I
9-1

TOP VIEW

. !2J

10-1
11-[

fii

Ne
Ola,

~~J

D/~

Absolute Maximum Ratings
(See note)

Rating

f25
124-

Symbol

Value

TSTG

-40 to + 125

Ne

..

A"

Ne

•

A"

122-

010,

:21
L ••

01'"

0/04

Unit

Storage
Ceramic
-65 to +150
--~------------------~---------------------·C
Temperature range

Plastic

Temperature under bias

TBIAS

-10 to +85

·C

Supply voltage

Vee

-0.5 to

V

Input voltage

VIN

Output voltage

VOUT

+ 7.0
-0.5 to Vee + 0.5
-0.5 to Vee + 0.5

V
V

Note: Permanent device damage may occur it ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating condtions for extended periods
may affect devlce reliat»lity.

Recommended Operating
Conditions
(Referenced to VSS)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.5

5.0

5.5

V

Input low voltage

VIL
VIH

2.0·
2.2

0.8

Input high voltage
Ambient temperature

TA

0

70

• - 2.0 V Min. for pulse width less than 20 ns (VJL Min.-

FUJI'l'SU

3-178

0.3 v a' DC la.al)

Vee

V

+ 0.3

V

·C

MB8425&·10
MB8425&·10L
MB8425&·15
MB8425&·15L

Capacitance
(TA = 25°C, f = 1 MHz)

Max

Unit

D/O capacHance (Vila = OV)

Symbol

8

Input capacitance (V IN = OV)

7

pF
pF

Parameter

Min

Typ

DC Characteristics
(Recommended operating
conditions otherwise noted.)

Parameter
Standby supply
current
Active supply
current

J"

Symbol

MB8425&·
10/15
Min
Max

MB8425&·
10L/15L
Min
Max

0.2

ISB1
ISB2

3

3

Icc1

45

45

Tast Conditions

Unit

E,.

mA

E = V IL , VIN = VIH or
VIL , lOUT = 0 mA

mA

Operating supply
current

Icc2

Input leakage
current

III

-1

-1

p.A

Output leakage
current

ILIIO

-1

-1

p.A

Input high
voltage

VOH

Output low
voltage

VOL

70

Vcc - 0.2

E = VIH

Cycle = min.,
Duty = 100%, lOUT = 0 mA

70

VIN = OV to Vcc
'{IIO = OV to Vcc

§. = VIH
G=VIHorW=VIL

Note: All voltages are referenced to

2.4

2.4
0.4

0.4

V

IOH = -1.0 mA

V

IOL = 2.1 mA

vss

AC Characteristics
(Recommended operating
conditions unless otherwise
noted)

Read Cycle"1

Parameter

Symbol

MB8425&·
10/10L
Min
Max

Read cycle time

TAVAV

100

Address access time"2

TAVOV

100

150

ns

E access time"3

TELOV

100

150

ns

Output enable to
output valid

TGLOV

40

60

ns

Output hold from
address change

TAXOX

20

20

ns

Chip select to
output low"Z"'·5

TELOX

10

10

ns

Output enable to
output low-Z"'·5

TGLOZ

5

5

ns

Chip select to
output high-Z"•.5

TEHOZ

40

50

ns

Output enable to
output high-Z"••5

TGHOZ

40

50

ns

Note: *1
*2
*3
*4
*5

iN is high for Read cycle.
Device is continuously selected, ~ = ~ = VIL'
Address valid prior or coincident with as transition low.
Transition is measured at the point of ±500 mV from steady state Voltage.
This parameter is measured with specified loading Load II in AC Test Conditions Diagram.

3-179

MB8425&·
15/15L
Min
Max

Unit

150

ns

MB84218·10
MB84258·10L
MB84258.11
MB84258.15L

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted,)

R_d Cycle Timing Diagrams
R_d Cycle I: Addre. . Controlled

=l:~~~~~~~~~~~-~-ItI-yQ-V--

----------TAvAV'----------i~

ADDRESS

..

-

Q

~I;-------~~-----

-,--_-_-_-_-_-_-_-_-_-......

TAXQX---......~I

PREVIOUS DATA VALID

DATA VALID

Read Cycle II: Ii Controlled

~ ~==-=--=-TA_VA.V_,~~~~_

41-.--------

TAVQV - - - - . - .

Q

r2Zl DON'T CARE
ri(S1I UNDEFINED

FUJITSU

3·180

MB84256·10
MB84256·10L
MB84256·15
MB84256·15L

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted,)

Write Cycle'1,2
Parameter

Symbol

MB84256·
10/10L
Min
Max

Write cycle time'3

TAVAV

100

150

ns

Address valid to
end of write

TAVWH
TAVEL

80

100

ns

Chip select to
end of write

TELEH

80

100

ns

Data valid to
end of write

TDVWH

40

50

ns
ns

MB84256·
15/15L
Min
Max

Unit

Data hold time

TWHDX

a

a

Write pulse width

TWLWH

60

90

ns

Address setup time

TAVWL
TAVEL

a

a

ns

Write recovery time'4

TWHAX
TEHAX

5

5

ns

Write enable to
output low-Z'5,6

TWHQX

5

5

ns

Write enable to
output high-Z'5,6

TWLQZ

40

50

ns

Note: *1 If G, E are in the Read Mode during this period, D/Q pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
*2 If E goes high simultaneously with W high the output remain in high Impedance state.
'3 All write cycles are determined from last address transition to the first address transition of the next address.
*4 TWHAX is defined from the end point of write mode.
*5 Transition is measured at the point of ±500 mV from steady state voltage.
'6 This parameter is measured with specified loading Load II In Fig. 2.

3-181

MB84256·10
MB84256·10L
MB84256·15
MB84256·15L

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Diagram
Write Cycle I

(iii Controlled)
~--------------------TAVAX--------------------~

AOORESS

D

Q

HIGH-Z

rzz.J DON'T CARE
i(ZI

FUJJ'I'SU

3·182

UNDEFINED

MB842S8·10
MB84258·10L
MB842S8·15
MB842S8·15L

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted,)

Write Cycle" (E controlled)
~---------------------TAVAX--------------------~

ADDRESS

w

D

HIGH·Z

HIGH,z
Q

!ZZl DON'T CARE
flll UNDEFINED

3-183

M8842H·10
M8842H·10L
M8842H·15
M8842H·15L

Data Retention
Characteristics
(Recommended operating
conditions unless otherwise
noted)

Parameter

Symbol

Data retention"
supply voltage

Min

Max

Unit

2.0

5.5

v

Standard

Data retention '2
supply current

mA

50

L-version

Data retention
setup time

TEHVL

o

ns

Operation
recovery time

TVHEL

TAVAX

ns

Note: 'I

E;. vOR -

O.2V

'2 VOR - 3.0V. E ;. VOR - O.2V

DATA RETENTION MODE

4.5V

Vee

E

4.SV

\

~ TEHVL_
~.,.......,..",p\

V

'- -

-

-

-

_o~ -

/

-

-

--./

!-- TVH~EL
2.2V

~

E;;'VDR-O.2V

AC Test Conditions
Input Pulse Levels:
0.6V to 2.4V
Input Pulse Rise and Fall TImes: 5 ns (Transient between O.BV and 2.2V)
Timing Reference Levels:
Input: VIL = O.BV, VIH = 2.2V
Output: VOL = O.BV, VOH = 2.2V
Output Load

OUTPUT LOAD
+5V

Q

'INCLUDING PROBE AND STRAY CAPACITANCE
P_ _ ured

Load I
Load II

Rt

R2

CL

tAKU

99O!l

tOOpF

t.SKU

99O!l

5pF

PU.JITSU

3-184

Except TE1LQX, TGLaz, TE1HQZ,

TWHQX and TWLOZ
TEtLQX, TGLOZ, TEtHQZ,
TGHOZ, TWHQX and TWLOZ

MB84256·10
MB84256·10L
MB84256·15
MB84256·15L

Package Dimensions
Dimensions in inches
(millimeters)

28.Lead Plastic Dual In·Llne Package
(Case No.: DIP.28P.M021

I

.533 (13.54)

INDEX

1~======~==::;Z:======jIJ4'05)
1.389 (35.28)
1.415 (35.94)

~
m"97

(5.00)

MAX.

f . 1 1 8 (3.00) MIN .

.020 (0.51) MIN.

28-Lead Plasic Flat Package
(Case No.: FPY-28P-M02)

~~~~r=fl '"0(2'8)MAX'li-+=;~~~~DOFF)
I.l

.453 (11.50)
.477 (12.10)

.331 (8.40)

NOM.

~r=n=;:;=;;:::::n:=;;=n=;:;=;:;:::=rr=n=;:?!~8'80)

~
.004 (0.1)
.008 (0.2)
DETAILS OF "1<1' PART

...,....R""'....""'=n=l'1I=\'"F=n=".,.=rF=I'1I=\'"F=rID .108(2.7}

•

MAX

.024(0.8)

.007(0.18)
MAX
.027(0.88)
MAX

3·185

I
.402 (10.2)

MB84256-10
MB84256-10L
MB84256-15
MB84256-15L

32-Pad Ceramic (Metal Seal) Leadless Chip Carrier
(Case No_: LCC-32CoA02)
-PIN 1 INDEX
C.Ol5(O.38)TYP

.445(11.30)
.460(11.68)

-SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

3-186

MB 8128-10
MB 8128-15

16384-BIT STATIC RANDOM ACCESS MEMORY WITH
AUTOMATIC POWER DOWN
The Fujitsu MB 8128 is a 16384 bit static random access memory organized as
2048 words by 8 bits. The MB 8128 is fabricated using N-channel silicon gate
MOS technology. It uses fully static circuitry throughout and therefore
requires no clocks or refreshing to operate.
MB 8128 is designed for memory applications where high performance, low
cost, large bit storage, and simple interfacing are required. The MB 8128 is
compatible with TTL logic families in a" respects; inputs, outputs and a single
+5V supply.

•

CERAMIC PACKAGE
(CERDIP)
DIP-24C-COl

2048 words x 8 bits organization

• Static operation: no clocks or refresh required
• Fast access time: 100nsmax. (MB8128-10)
: 150ns max. (MB 8128-15)
PLASTIC PACKAGE
DIP-24P-MOl

• Single +5V supply, ±1 0% tolerance
• Common data input/output
• TTL compatible inputs/outputs

PIN ASSIGNMENT

• Three-state output with OR·tie capability
• Chip select for simplified memory expansion, automatic power down
A7

vee

• A" inputs and outputs have protection against static charge

A6

As

• Standard 24 pin DIP package

As

A9

A4

WE

A3

OE

A2

Alo

Al

CS

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Voltage on Any Pin with
respect to G ND
Temperature under Bias

I CERAMIC
Storage Temperature I
PLASTIC
Power Dissipation

Symbol
V ,N , VOUT , Vee
T B1AS
TSTG
Po

Value
-3.5 to +7
-10 to +85
-65 to +150
-40 to +125
1.2

Unit

°c
°c

I/Os

1/0 1

1/0 7

1/02

1/06

1/03

1/0 5

GND

1/04

W

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
4-2

Ao

V

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of anV voltage higher than maximum rated voltages to this high impedance

circuit.

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB 8128-10
MB 8128-15

Fig. 1 - MB 8128 BLOCK DIAGRAM

...

~

.

~

Vee

GND

j

j

I'"~

..

...

ROW
SELECT

--Z

I'"~

...
,>
... ...
:2
...

fMEMORY ARRAY
128 ROWS BY
128 COLUMNS

f-

...

I

I

f-;-

:G>-

~

COLUMN SELECT

INPUT
DATA
CONT.

~

I/O~

~

I/O CIRCUITS

~

J.

1

~

A7

HR
~

J.

~

As

D1

A IO

Ag

).J

~

I

TRUTH TABLE
POWER
DOWN
CIRCUIT

CAPACITANCE

CS
H
L
L

OE
X
H
L

WE
X
H
H

L

X

L

SUPPLY CURRENT

I/O PIN
HIGH·Z
HIGH-Z
D OUT
DIN

ISB
Icc
I ee
Icc

(TA = 25°C. f= 1 MHz)

Parameter
Input Capacitance (V IN

MODE
NOT SELECTED
DOUT DISABLE
READ
WRITE

= OV)*

Input/Output Capacitance (VI/O = OV)*

Symbol

Typ

Max

Unit

C IN

-

5

pF

CI/O

-

7

pF

4-3

1111111111111111111111111111111111111111111111111111

MB 8128-10 FUJITSU
MB 8128-15

1111111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Symbol

Min

Typ

Max

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

Input Low Voltage

V IL

-3.02)

-

0.8

V

Input High Voltage

V IH

2.2

-

6.0

V

Parameter

Note:

Ambient')
Temperature

O°C to +70°C

1) The operating ambient temperature range is guaranteed with transverse airflow exceeding 2m/sec.
2) -3.0 V Min. for pulse width less than 20 ns. (VIL Min. = -0.5 V at DC level).

DC CHARACTERISTICS
(Recommended operating Conditions unless otherwise noted.)
Symbol

Parameter

Min

Typ

Max

Unit

Input Leakage Current (V IN = GND to Vee, Vee = Max.)

II LI I

10

JlA

Input/Output Leakage Current
(CS or OE = V IH , VI/O = GND to Vee' Vee = Max.)

IILol

10

JlA

MB 8128-10

70

TA =25°C
MB 812B-15

Power Supply Current
(Vee = Max., CS = VIL,II/O = Open)

50
Icc

mA

MB 8128-10

100

MB 8128-15

70

TA=O°C

Output Low Voltage (IOL = 2.1 mAl

VOL

Output High Voltage (iOH= -1.0 mAl

VOH
MB 8128-10

Standby Current (Vee = Min. to Max., CS = V IH )

Note:

MB 8128-10

8

20

6

15

mA

20
Ipo

MB 8128-15

V

V

2.4

ISB
MB 8128-15

Peak Power-On Current (Vee = GND to Vee Min.,
CS = Lower of Vee or V IH Min.)

0.4

mA
15

A pull-up resistor to Vee on the CS input is required to keep the device deselacted. Otherwise, power-on current
approaches lee active.

4-4

1IIIImlmimllmlmillmimmmmllmm

FUJITSU
1IIIIIIIIIIImllllllllllllllllllllllllllllllllllili

MB 8128-10
MB 8128-15

Fig. 2 - AC TEST CONDITIONS
Input Pulse Levels:

0.8V to 2.4V

Input Pulse Rise and Fall Times:

10 ns

Timing Measurement Reference Levels:

Input:
Output:

Output Load:

1 TTL Gate and C L = 100 pF

D

Output

0

1.5V
1.5V

I

r

0

eL

-=

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.!
READ CYCLE
MB 8128-15

MB 8128·10
Parameter

Unit

Symbol
Min

Typ

Max

100

Min

Typ

Max
ns

Read Cycle Time

t RC

150

Address Access Time

tAA

100

150

ns

Chip Select Access Time

t ACS

100

150

ns

Output Hold from Address Change

tOH

15

20

ns

Chip Select to Output Active

tLZ

0

0

ns

Chip Select to Output in High Z

tHz

40

60

ns

Output Enable to Output Valid

tOE

50

60

ns

Output Enable to Output Active

tOLZ

Output Enable to Output in High Z

tOHZ

Chip Select to Power Up Time

tpu

Chip Select to Power Down Time

tpD

10
40
0

60

ns
ns

0
40

4-5

ns

10

60

ns

1111111111111111111111111111111111111111111111111111

MB 8128-10 FUJITSU
MB 8128-15

1111111111111111111111111111111111111111111111111111

READ CYCLE TIMING DIAGRAM')
READ CYCLE: ADDRESS CONTROLLED 2 )

ADDRESS

I/O

l~A~:q X Xl~-----D-A-T-A-V-A-L-ID-----~t:==
___
'RC

_ _

READ CYCLE: CS CONTROLLED3 )
'OE-

I-------

~

1

'OLZ

I--'HZ~

'ACS

r-----'OHZ

'LZ

XXXXK

I/O

~C~PLY

DATA VALID

-tpu

ICC-----

----=? . .

I

HIGH-Z

~tpD

-~
D:

5 0 - % - - - - - - - - - - - - - - = 1 50%

CURRENT I S B - - - - - J

Don't Care

~:
Note:

1) WE is high for Read Cycle_
2) Device is continuously selected, CS = V 1L , OE = V 1L 3) Addresses valid prior to or coincident with CS transition low_

4-6

Undefined Data

Ilm~llllllllllllmlmllllllllllllllll~11111111
FUJITSU MB 8128-10
1111111111111111111111111111111111111111111111111111

MB 8128-15

WRITE CYCLE
MB

8128-10

MB

8128-15

Symbol

Parameter

Unit
Min

Typ

Max

Typ

Min

Max

Write Cycle Time

twc

100

150

ns

Address Valid to End of Write

tAW

95

140

ns

tcw

95

140

ns

Data Valid to End of Write

tow

40

60

ns

Data Hold Time

tOH

5

5

ns

Write Pulse Width

twp

85

130

ns

Write Recovery Time

tWR

5

10

ns

tAS1

0

0

ns

t As2

0

0

ns

Output Active From End of Write

tow

10

10

ns

Write Enabled to Output in High Z

twz

Chip Select to End of Write

Address Setup Time

40

60

WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE:

WE

CONTROLLED 2)
twc

ADDRESS

tAW
tcw

tWFl-

\.

J

tAS1----j

\twz
DOUT

twp

-

tOH

tow

(

DATA IN VALID

)I
~tow~

>0000000000<11'

HIGH-Z

D: Don't Care

m:
4-7

Undefined Data

ns

1~llmllll~IIII~I~I~IIMI~II~m
MB 8128-10 FUJITSU
MB 8128-15 1111~IIIIIIIIIMIOOMIII~I~II~111

WRITE CYCLE TIMING DIAGRAM (Cont'd)
WRITE CYCLE: CS CONTROLLED 2 )
Iwe
~

ADDRESS

lAW
lew
IAS2CJ

IWR-

IWp

lOW

t--Iwz-

V

IOH

DATA IN VALID

~
_IOW~

DOUT

XXXXXXXXXXX

r-")(5(5(5('il

HIGH-Z

D: Don't Care
•

Note:

: Undefined Data

1) If CS goes low simultaneously with WE low, the outputs remain in a high impedance state.
2) CS or WE must be high during address transitions.

DESCRIPTION
The MB 8128 from Fujitsu is high
performance part. This is designed for
high speed and low system power
requirements.
The high speed is obtained by advanced
NMOS processing. The low system
power requirements are achieved by the
use of the MB 8128 chip select (active
low). The MB 8128 automatically enters
standby drawing only ISB whenever
the chip select is high. Upon activation
of chip select (CS = LOW) the MB 8128
automatically powers up and draws Icc.

This automatic power up/down is an
extremely useful feature. However, care
must be used as proper decoupling and
PC board layout is required to minimize
power line glitches.
PC board layout with proper Vee
decoupling will minimize power line
glitches.
Input and data bus lines are an additional area of concern. Unless bus lines are
properly designed and terminated, cross
coupling, cross talk and reflections can
4-8

occur. Of particular importance is the
undershoot on address lines. Once again,
careful attention to good PC board
layout and proper termination techniques will yield a well designed and
reliable memory system.

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllllili

FUJITSU

MB 8128-10

IIIIIIIIIIIIIIIIIIIIIIIII~IIIIIII~III~III~IIIIII MB 8128-15

PACKAGE DIMENSIONS
24-LEAD CERAMIC ICERDIPI DUAL IN-LINE PACKAGE
ICASE No.: DIP-24C.Q)l)

-j~~~.'00~{R2.5~4'M~A~X~FR~~~~

~

'230"'84'MAX
.12013.05)
.150(3.81)

.020(0.511
,05011.271

.015(0.381
.023(0.58)

Oi""8n510n.ln
inch... (millimel"rs)

24-LEAD PLASTIC DUAL IN-LINE PACKAGE
ICASE No.: DIP-24P.M01)

l

INDEX

.524(13.31)

J
I

3

1'n='FF'FF'FF'FF'FF'FFr='FF'FF'FFffi
D D
1.171(29.74)

'''{

.

1.197130.40)
.050(1.27IMAX

1'····.11813.00IMIN

.020 (O.511MIN
Olm .. nl;o,15In
;nch•• (mlilimllta.,j

4·9

FUJITSU

MOS Memories

• MB8167A·55, MB8167A·70
NMOS 16,384-Bit
Static Random Access Memory

Description
The Fujitsu MB8167A Is a 16,384 words by 1-blt static random access memory fabricated using N-channel silicon gate MOS technology_ Separate Input/output pins are provlded_ All devices are fully
compatible with TTL logic families in all respects: Inputs, output
and the use of a single +5 V DC supply.
For ease of use, chip enable (E) parmits the selection of an individual package when outputs are OR-tied, and automatically
powers down the MB8167A. This device offers the advantages of
low power dissipation, low cost, and high performance.

Feature.

x

.ThrM-state output with OR-tie
capabilHy
.Chlp enable for simplified
memory expansion ancl
• Fast Access Time:
automatic power down
.Allinputs and output have
MB8167A-55 55 nB Max.
protection against static charge
MB8187A-70 70 ns Max.
.Slngle +5 V DC supply voltage .Standard 2O-pln DIP package
.Separate data Input and output
.TTL compatible Inputs .nd
output

.Organized as 16,384 words
1·bH

.Statlc operation: no clocks
refresh required

or

4-10

MB8187A·45
MB8187A·55
MB8187A·70

MB8187A Block Diagram
and Pin Assignment

.. - - - - - - - - 1

Ao

A1-------j)¢=~

_ v..

~----------1

A,-------t;¢==j

Vel:.

Al

A'3

A2

A'2

A3

All

A4

A'0

A5

Ag

CELL ARRAY

ROW
SELECT

128 ROWS
128 COLUMNS

'" - - - - - - - - 1

'" -------{)t::;:===1
A"-~~===:C~L
Q

COLUMN 110 CIRCUITS

A6

As

Q

A7

W

D

E

VSS
w-~-+--!

TOP VIEW

Truth Table

i
H
L
L
Absolute Mallimum RatIng.
(See Note)

x
L
H

Mode

Output

Power

NOT SELECTED
WRITE
READ

HIGHZ
HIGHZ

STANDBY
ACTIVE
ACTIVE

Dour

(LCC·2OC-F01)

RatIng

Symbol

Value

Unit

Voltage On Any Pin with Respect to Vss
Temperature Under Bias

VIN, VOUT, VCC
TA

-3.5 to +7
-10 to +85

V
·C

Storage Temperature

Ceramic

TSTG

-65 to +150

Plastic

TSTG
PD

-40 to +125
1.2

Power Dissipation

·C
W

Note: Permanent device damage may occur if ABSOWTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Capacitance
(TA=25·C;f=1 MHz)

Recommended Operating
Conditions
(Referenced to VSS)

Parameter

Symbol

Input Capacitance (VIN = OV)
Output Capacitance (VOUT = OV)

CIN
COUT

Typ

Mall

Unit

5
6

pF
pF

Parameter

Symbol

Min

Typ

Mall

Unit

Supply Voltage
Input Low Voltage
Input High Voltage

VCC
VIL
VIH

4.5
-3.02)
2.0

5.0

5.5
0.8
6.0

V
V
V

Ambient"
Tempereture
O·C to +70·C

Note: (1) The operating ambient temperature range is guaranteed with transverse airflow exceeding 2 linear meters/second.
(2) -3.0 V Min. for pulse width less than 20 ns. (Vll Min. = -0.5 at DC level)

FUJITSU
4·11

MB81.7A·4.
MB81.7A•••
MB81.7A·70

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

=

=

=

= Max)

Power Supply Current
(VCC = Max, E= VIL, lOUT = OmA)
Output Low Voltage (IOL = 16mA)

Max

Unit

III

0.01

10

,.A

ILO

0.1

50

,.A

ICC

90

120

rnA

0.45

V
V

25

rnA

25

rnA

Min

VOL
VOH

Output High Voltage (IOH - -4mA)
Standby Current
(VCC = Min to Max, E = VIH
Peak Power-On Current
(VCC = VSS to VCC Min, i: = Lower of VCC or VIH Min)

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Typ

8J111bol

Input Leakage Current
(VIN VSS to VCC, vee
Max)
Output Leakage Current
~ VIH, VOUT = VSS to VCC Min, VCC

2.4

19B

15

IPO

Read Cycle
Parameter

8J111bol

MB81.7.....
Min
Max

_81.7&-70
Min
MIIlt

Read Cycle Time
Address Access Time

TAVAV

55

70

Chip Enable Access Time

TAVQV
TELQV

Output Hold from Address Change

TAVQX

ill lID
ill lID

Chip Enable to Output Active
Chip Enable to Output In High Z
Chip Enable to Power Up Time
Chip Enable to Power Down Time

TELQX
TEHQZ
TELIH
TEHIL

§
~

55

70
70

55
5
10
0
0

5
10

30

0
0

ns
ns
ns
n8
n8

40

35

30

Unit

n8
ns
ns

Read Cycle: Address Controlled 3.4

A

TAVAV----------------~~-----------

TAVQV'-----1
TAVQX

Ir-----------------------DATA VALID

Q

Read Cycle:

i Controlled 3. 5
r-----------------·TAVAV------------------;
TI;HQZ

VCC

ICC - - - -TELIH)
- - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

SUPPLY ISB
CURRENT

_

50%

Notes:
1. Transition is measured al the point of ±5OOmV from steady state voltage.

2. This parameter is measured with specified k>adlng In Flg.2.
3. W is high for Read Cycle.
4. Device is continuously selected, g ::-. VIL
5. Addr~ valid prior to or coincident with transition low.

E

FUJITSU
4·12

M.8187A~411

M.8187A·SII
M.8187A·70

AC Cherecterletlc.
(Recommended operating
conditions unless otherwise
noted.) (continued)

Write Crcle

IMotHl

Parameter

Srmbol

Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Data Valid to End of Write
Data Hold Time
Write Pulse Width
Write Recovery Time

TAVAV
TAVWH
TElEH
TDVWH
TWHDX
TWlWH
TWHAX
TAVWl

Address Setup Time
Output Active From End of Write
Write Enable to Output In High Z

Write Cycle:

TAVEL
TWHQX
TWlQZ

IZlIS1
IZlIm

M88187WII
Min
Mu

. .8187Ao70
Min
Mex

55
45
50
35
0
35
5
5
0
0

70
50
60
45
0
45
10
10
0
0
30

ns
ns
ns
ns
ns
ns
ns
ns

35

W Controlled6.9
TAVAV

xx.

A

TELEH

\\'i K.J.

'1111, II/II//!/

TWHAX
TAVWH·
I-TAVWL-----j
r--TWLWH--

-

\\

t

-TDVWH

Q

~

XXXXX

.ITWHDX

DATA VALID

D X .XXX lX :XXXX .X.lll

IlX.lX

:XxJ{)(X

-TWHQX

HIGH·Z

Write Cycle: Ii Conlrolled6,9
TAVAV
ADDRESSES

~

.XX .XXX .X

TAV EL_

-

TELEH

h
TAVWH

t---- TWLWH-

D

.t

.XXXX .XXXXlt..

-TDVWH

.ITWHQX

I xxx .. XXXXXN'

DATA VALID
-TWLQj

·TELQX
Q

TWHAX

'I I I I II/!I I I I I II

\\\\ I\\\\\\\\\\\\\\'

.XXXXXXXXX

xX

HIGH·Z

NoI88:
6. If E goes high simultaneously with Vi high, the output remains in a high impedance state.
7. Transition is measured at the point of ±5OOmV from steady state voltage.
This parameter is measured with specified loading In Fig. 2.
9. E or W must be high during address transitions.

a
FUJITSU

4·13

Unit

ns
ns
ns

M881e7~.45

M8!1187A.66
M88187A·70

AC Test Conditions

Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Measurement Reference Levels:
Load Capacitance:

0.8 V to 2.2 V
5 ns
Inputs: 1.5 V
Output: 1.5 V
5 pF for TEHQZ, TWLQZ, TELQX and TWHQX
30 pF for all others

Fig. a: Output Load
2V

1001l

DouT-------------t

I
Package Dimensions
Dimensions In inches
(millimeters)

CL
(Including
Scope and Jig)

aO·Lead Cerdip
Dual In·Llne Package
DIP·aOC·coa

I

A .025(0.64)
REF ,,~

.284(7.211

.302t671

.940 (23.881
1.000 (25.41

qj

~H-__.O_~_,_,.2_'_IM_A_X__________________

.200I •.OEIMAX
,12013.051
.150(3.81)

,020(0.51)

I------+--------.===~--H_~

,1SO(3.81)

,013(0.33)

.023(0.581

,062(1.581

FUJITSU
4·14

MB8187A·46
MB8187A·65
MB8187A·70

Packa.e Dlmenalon.
Dimensions in inches
(millimeters) (continued)

20·Lead Plaatlc
Dual In·Llne Packa.e
DIP·20P·M01

.172!4.36JMAX

r"V

'.f--;'--j-SEATING
.11SIJ.OIMIN

20.Pad Ceramic (Prlt Seal)
Leadle•• Chip Carrier
(Ca. . No.: LCC·20C·P01)

R.012(0.30ITVP
14 PLCSI

n
.420(10.67)
.435(11.05)

.280(7.111
.29517.49)

1·10012.54)

MAX

4·15

PLANE

FUJITSU

MB8168·55
MB8168·70

MICROELECTRONICS. INC.

NMOS 16,384·BIT STATIC
RANDOM ACCESS MEMORY
DESCRIPTION
The Fujitsu MB8168 is a 4096
word by 4·bit static random ac·
cess memory fabricated using
N·channel silicon gate MOS
technology. The memory is fully
static and requires no clock or
timing strobe. All pins are TTL
compatible and a single 5V power
supply is required.
A separate chip select E pin
simplifies multi package system

design. It permits the selection of
an individual package when out·
puts are OR·tied. Furthermore,
when selecting a single package
by E, the other deselected pack·
ages automatically power down.
All Fujitsu devices offer the ad·
vantages of low power dissipa·
tion, low cost and high perfor·
mance.

CERDIP PACKAGE
DIP-20C-C03

FEATURES
• Organized as 4096 words x
4·bits
• Fully Static Operation, no
clocks or timing strobe
required
• Fast Access Time:
MB8168·55 55 ns Max.
MB8168·70 70 ns Max.
• Low Power Consumption:
ICC 150mA Max. (Active)
IS8
40mA Max.(Standby)

=
=

• Single +5V DC Supply
Voltage, :t:10% tolerance
• Common data input and output
• Three-state outputs with OR-tie
capability
• Chip select for simplified
memory expansion, automatic
power·down
• Standard 20·pin DIP package
• Pin compatible with Intel 2168

PLASTIC PACKAGE
DIP-20P-M01

MB8168 BLOCK DIAGRAM
A,

<>----~=r--,

,-----,

LCCPACKAGE
LCC-20C-F01

~Vcc

--oVss

A,o-----IX=::::J
MEMORY ARRAY
128 ROWS
128 COLUMNS

PIN ASSIGNMENTS

TOP VIEW

LCC-20C·FOI

4·16

MB8168·55/MB8168·70
ABSOLUTE MAXIMUM RATINGS

(See Note)

Rating
Voltage On Any Pin with Respect to Vss

Symbol

Value

V'N, VOUT, Vee

-3.5to +7.0

V

Iso

20

mA

Short Circuit Output Current
Temperature Under Bias

TBIAS

Storage Temperature

Ceramic
Plastic

Tstg

Power Dissipation

Unit

-10to +85

·C

-65 to +150
-40 to +125

·C

1.2

W

Po

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability. This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. It is advised that normal precautions be taken to avoid application of any
voltage higher than maximum rated voltages to this high impedance circuit.

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss )

Parameter

Symbol

Supply Voltage

Min

Typ

Max

Unit
V

Vee

4.5

5.0

5.5

Input Low Voltage

Vil

-3.02)

0.8

V

Input High Voltage

V,H

2.0

-

6.0

V

Ambient 1)
Temperature
O·C to +70·C

Note: 1. The operating ambient temperature range is guaranteed with transverse airflow exceeding 2 linear metersl second.
2. - 3.0 V Min. for Pulse width less than 20 ns. (VIL Min. = - 0.5 V at De level)

CAPACITANCE

(TA

=

25· C, f

=

1 MHz)

Parameter
Input Capacitance

Address, W: V,N = OV

Input Capacitance

E: V,N =OV

Output Capacitance Data I/O, VOUT = OV

Symbol
C'N
CE
CliO

Typ

Max

Unit

-

7

pF

-

8

pF

-

8

pF

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Input Leakage Current
(V,N = VSS to Vee, Vcc = Max)
Output Leakage Current
(E = V'H, VOUT = VSS to 4.5V, Vee = Max)
Power Suppl~ Current
(Vee = Max, E = V'l, lOUT = OmA)
Output Low Voltage (IOl = 8mA)

Min

Max

Unit

III

-10

10

pA.

ILO

-50

50

pA.

150

mA

VOL

-

0.4

V

VOH

2.4

-

V

-

40

mA

50

mA

ICC

Output High Voltage (IOH = -4mA)
Standby Current
(Vee = Min to Max, E = V'H, lOUT = OmA)
Peak Power.Qn Current
(Vee=Vssto Vee Min, E = Lower of Vcc or VIH Min)"

19B
IPO

Note: "A pull-up resistor to Vcc or the es input is required to keep the deVIce deselected.
Otherwise. power-on current approaches Icc active.
4-17

MB8168·55 / MB8168·70
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)

READ CYCLE
Parameter

Symbol

INOTESI

Min
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output Active
Chip Enable to Output in High Z
l1J
j]]
Chip Enable to Power Up Time
Chip Enable to Power Down Time j]]

mllJ
m

TAVAV
TAVQV
TELQV
TAXQX
TELQX
TEHQZ
TELIH
TEHIL

MB8168-55
Typ
Max

55
-

5
10

0

-

-

-

Min
70

-

MB8168-70
Typ
Max

-

-

55
55

-

-

10

-

-

0

55

-

READ CYCLE, ADDRESS CHANGING

70
70

-

5

30

40

70

4,5

~------------------TAVAV----------------~~

--r---------------------------~.,Il~-------,
ADDRESS VALID
)I(

ADDRESSES

-J--'l"--------------'JI''----~------TAVQV------~

r-------TAXQX-j

DQ

DATA VALID

PREVIOUS DATA VALID

~ Undefined Data

READ CYCLE, CS CHANGING 4,6
TAVAV
~

E

TElQV
-TElQX
HIGH-Z

DQ

~~~PLY

{X X

DATA VALID

B

- - - -

[

HIGH-Z

~TEHll

-TElIH

:CSc -

M

s-O-%-------------------s-ooL

- - )....

CURRENT

~
Notes: 1. Transition is measured at the point of ±500mV from steady state voltaae.
2. This parameter is measured with specified loading in Fig. 2.
3. I H'; ICC (Max), IL= ISB (Max)
4. W is high for Read Cycle.
5. Device is continuously selected. E VIL.
6. Addresses valid prior to or coincident with E transition low.

=

4-18

Undefined Data

Unit
ns
ns
ns
ns
ns
ns
ns
ns

MB8168-55 / MB8168-70
WRITECYCLE
MB8168-55
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Data Valid to End of Write
Data Hold Time
Write Pulse Width
Write Recovery Time
Address Setup Time
Output Active From End of Write
Write Enable to Output in High Z
Chip Enable to Output Active

rn

tlI

rID
rnJ

MB8168-70

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

TAVAV
TAVWH
TElWH
TDVWH
TWHDX
TWlWH
TWHAX, TEHAX
TAVWL, TAVEL
TWHQX
TWlQZ
TElQX

55
50
50
25
0
50
0
0
0
0
10

-

-

70
60
60
30
0
60
0
0
0
0
10

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

INOTESI

WRITE CYCLE,

W

-

-

-

-

-

-

30

-

-

-

-

-

-

-

-

40

-

CONTROLLED10

TAVAV
ADDRESSES - - I
TELWH

~I\'

/ 'j I I I I I I I
TAVWH
I
I-I--TAVWL--I
-TWLWH- - - - TWHAX
'l~

--TDVWH- b,TWHDX

HIGHZ

~X

-

TWLQZ-

WRITE CYCLE,

)QL

VALID

TWHQX
HIGH Z

E CONTROLLED 10
TAVAV

ADDRESSES

ADDRESS VALID

TAVELE11

-

TELWH

h
TAVWH
I--TWLWH-

TEHAX

1111111111111,

\\\ \ \ \ \ \ \ \ \ \ \ \ \

-TDVWH ~=I TWHDX
HIGHZ

-

rTELQX

VALID

-

Jl\XXXXXXXXX

-TWLQZ
HIGHZ

.XXXXX .xx
P9'iiI Undefl_ Data
bOOI

1771 }

UA

~

Can Change Any Time
In the Direction Shown

Notes: 7. Transition is measureed at the point of ±500 mV from steady state voltage.
8. This parameter is measured with specified loading in Fig. 2.
9. If E goes high simultaneously with Whigh, the output remains in a high impedance state.
10. E or W must be high during address transitions.
11. If W is low for the entire cycle Data Out remains High Z throughout the cycle.
12. Q shows when the DQ pin Is driven by the memory chip. 0 shows when the DQ pin is externally driven.

4-19

MB8168·55 IMB8168·70
Input Conditions:
Input Pulse Levels:
Input Pulse Rise/Fail Times:
Input Timing Reference Level:
Output Conditions:
Output Timing Reference Level:
Output Load:
R1

R2

C

AC TEST CONDmONS

Vcc

OV to 3.0V

5 ns
1.5V
DOUT ____~~------_.
(1/0)

O.SV to 2.0V

Parameters Measured

load I 48011 25511 30pF except TElQX, TEHQZ, TWLQZ, and
TWHQX
load" 48011 25511 5pF TElQX, TEHQZ, TWlQZ, and TWHQX

OUTPUT LOAD

DEVICE OPERATION
Controls
The MB8168 has two control inputs, Chle Enable
and Write
Enable rN). When E ~ VIH, the
device is deselected and automatically controlled to the standby mode, reducing the power requirements to less than one-s.!.xth
of the selected state. When E s
Vll, the device is selected (active)
and read or write cycles may be
performed. Eshould be controlled
to track Vcc during the initial
system power-on to prevent all of
the MB8168's in a system from
drawing active ICC during powerup.
When W ~ VIH and the chip is
selected, a read cycle may be per-

iE>

formed. When W s Vil and the
chip is selected a write cycle may
be performed.
Read Cycle

A read cycle is selected when E s
Vil and W ~ VIH. Read access
time is measured from either the
E high to low transition or from
valid address as shown in the
read cycle timing diagrams.
Write Cycle

A write cycle is seleted when E s
VIL and W s VIH. The actual
beginning of the write 9'cle is initiated by the latter of E or W going low as shown in the write cycle timing diagrams. The address
setup times shown in the timing

4-20

diagrams must be met and the addresses must remain stable for
the entire write cycle. The w..!ite
~cle is terminated by either E or
W going high. If the timing
specifications are not met, data
may be altered or lost.
In summary, the write cye!! m~
be initiated by the latter of E or W
going low and may be terminated
by E or W going high, whichever
occurs first, and the setup and
hold times must be referenced to
the controllinQJ!ignal transitions.
Either E or W must be high
(greater than VIH), during an address transition.

MBS168·55/ MBSl68·70
PACKAGE DIMENSIONS

Dimensions in inches (millimeters)

20-LEAD CERDIP DUAL IN-LINE PACKAGE
DIP-20C-C03

-----I

.0500,27)MAX

)H-------------,-T
~

i·20015.081MAX

-r--+,20IJ.OSl

+_J.,50(381l

1,02010.51)
050(1.27)

~~----~~~~~~--~~

20-LEAD PLASTIC DUAL IN-LINE PACKAGE
DIP-20P-MO 1
INDEX·'

INoeX.2'1'=rr=rn==r=rn=r=r=n==r=r=n==r=r=i~

.17214.36)MAX

r'rF=i'-+-SEATING PLANE
.11Si3.0IMIN

20-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
LCC-20C-FO 1

n

R.012(Q,30ITVP
(4 PLeS)

.420(10.671

.435( 11.05)

.280(7.111
.295(7.491

MAX

4·21

FUJITSU

MOS Memories
•

MB8171·55, MB8171·70
65,536-Bit Static Random
Access Memory with Separate
Data Input, Data Output
and Automatic Power Down

Description
The Fujitsu MB8171 is 1\ 65,536 word x l-bit static I'lIndom access
memory fabricated with N-channel Silicon gate MOS technology. It
uses fully static circuitry throughout and threrefore requires no
clocks or refreshing to operate.
The MB6l7l is designed for memory applications where high
performance, low cost, large bit storage and simple interfacing
are raquired.
All pins are TTL compatible and a single + 5 volt power supply
is required.

• Organization:

65,536 words xl-bit
• StatIc operation: no clocks
or refresh required
• Fast scceas time:

=

=

=

=

TAVQV
TELQV
55ns max_
(MB8171-55)
TAVQV
TELQV

70 ns max.

• Chip enable for slmplHled
memory expansion, automatic
power down
• All Inputs and output have protection against static charge
• Standard 22-pln Ceramic
packsge (300 mll_)

(MB8171-70)

• Single +5V supply
± 10% tolerance
• Separate data Input and
output
• TTL compatible Inputs and
output

This device contains circuitry to
protect the inputs against damage
due to high static voltages or eteotric fields. However. " 18 advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltag•• to this high Impedance circuH.

4-22

III-

-

~

I-

-

MB8171·55
MB8171.70

MB8171 Block Diagram and
Pin Assignments

CELL
ARRAY
512 ROWS
128COLUMNS

ROW
SELECT

~

Vee

4---

Vss

"-

vee

A.

As

A.

A7

A,

As

A.

As

A,.

A,.

A,.

A"
A,.

Au
D

a

COLUMN I/O CIRCUITS
INPUT
DATA
CONT.

a

As

Vi
v••

COLUMN SELECT

D

i!

TRUTH TABLE
E

W

MODE

OUTPUT

POWER

H
L
L

X
L
H

NOT SELECTED
WRITE
READ

HIGIf.Z
HIGIf.Z

STANDBY
ACTIVE
ACTIVE

a

Absolute Maximum Ratings
(See Note)

RaUng

Symbol

Value

Unit

Voltage on any pin with
respect to Vss

V IN• V OUT' Vee

-3.5 to +7

Temperature under bias

T BIAS

-to to

Storage temperature

TSTG

-85 to +150

°C

Power dissipation

Po

1.2

W

+85

V

°C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed In the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

FUJITSU
4·23

MB8171·55
MB8171·70

Recommended Operating
Conditions
(Referenced to Vss )

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.5

5.0

5.5

V

Input low voltage

V1L

-3.0"

O.B

V

Input high voltage

V 1H

2.0

6.0

V

Ambient temperature'

TA

0

70

°C

Note:

*

The operating ambient temperature range is guaranteed with transverse airflow exceeding 2m/s .

.... -3.0 V Min. Pulse width tess than 20 ns. (V'L Min. = -0.5 V at DC level)

Capacitance
(TA = 25°C, f = 1 MHz)

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Typ

Max

Unit

Input capacitance (VIN = OV)"

5

pF

E capacitance (V1N = OVr

9

pF

Output capacitance (VOUT = OV)"

6

pF

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

Input leakage current

V1N = OV to Vee
Vee = max.

III

-10

0.01

10

/LA

Output leakage current

E = V1H, VOUT = OV to 4.5V
Vee = max.

ILO

-SO

0.1

50

/LA

Power supply current

E = V1L
Vee = max.
lOUT = 0 mA

90

TA = 25°C
TA = O°C

lee

Standby current

Vee = min. to max.
E = V1H

ISB

Output low voltage

IOL=16mA

VOL

Output high voltage

IOH = -4 mA

VOH

Peak power on current

Vee = OV to Vee min."
E = lower of Vee or V1H min.

Note:

*

Ipo

A pull-up resistor to Vee on the E input ;s required to keep the device deselected.
Otherwise, power-on current approaches ICC active.

4-24

125
27

mA

35

mA

0.45

V

40

mA

2.4

V

MB8171.55
MB8171·70

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Read Cycle
Parameter

Symbol

MB8171·55
Min
Max

MB8171·70
Min
Max

Unit

Read cycle time

TAVAX

55

70

ns

Address access time

TAVQV

55

70

ns

Chip enable access time

TELQV

55

70

ns

Output hold from address change

TAXQX

5

5

Chip enable to output in low-Z'l.2

TELQX

10

10

Chip enable to output in high-Z'l.2

TEHQZ

0

Chip enable to power up time

TELIH

0

Chip enable to power down

TEHIL

30

ns
ns

0

ns

40

ns

0
30

ns

35

Notes: *1 Transition is measured at the point of ::!:5QO mV from steady state voltage.

Read Cycle Timing Diagrams
Read Cycle: Address Controlled'l '2

~~~---------------TAVAX---------------)l(~
ADORESS

= t = - T A X O X- - - - . - - -

o

PREVIOUS DATA
VAUD

'-----

DATAVAUD

Read Cycle: i Controlled'2'3

TAVAX

~
/
TELOV
--TELOX1,
HIGH,Z

o

DATA VALID

_ _ TELIH

ICC

_TEHOZ_

- - ---

_TEHIL

1\

HIGH-Z

V

--=1:,----50%

I••

t'iQ(l:
NOTES: '1 E IS LOW.

'2 VI IS HIGH TO READ CYCLES.
'3 ADDRESS VALID PRIOR TO OR COINCIDENT WITH E TRANSITION LOW.

FUJITSU
4-25

UNOEFINED

MB8171·55
M88171·70

AC Ch....ct.rI.tlc.
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Writ. Cycl.
P.r.m.t.r

Symbol

M88171·55
Min
M.x

M88171.70
Min
M.x

Unit

Wr~e

TAVAX

55

70

ns

cycle time

Chip enable to end of write

TELWH

45

55

ns

Address valid to end of write

TAVWH

45

55

ns

Address setup time

TAVWL

5

10

ns

Address setup time

TAVEL

0

0

ns

Write pulse width

TWLWH

35

45

ns

Data valid to end of write

TDVWH

35

45

ns

Write recovery time

TWHAX

5

10

ns

Write recovery time

TEHAX

10

15

ns

Data hold time

TWHDX

0

0

ns

Data hold time

TEHDX

5

5

ns

Write enable to output in high-Z".2

TWLQZ

0

Output active from end of write"·2

TWHQX

0

30

0

ns

35

ns

0

Notea: ·1 Transition Is measured at the point of ±500 mV from steady state voltage.

Write Cycle Timing Diagrams
Writ. Cycl.:

iii Controlled"

'2

TAVAX
ADDRESS

~I

\1
/\

--.-11\
TELWH

~ ~l\

/~ ~
TAVWH

!+--TAVWL_

TWHAX

TWLWH

\

1\

J

\
_TOVWH

\I

D

/\

TWHDX

\V
/1\

DATA VALID

-TWLDZ_

TWHQX

HIGH-Z

Q

NOTES: " ~ OR W MUST BE HIGH DURING ADORESS TRANSITIONS.
'2 IF E GOES HIGH SIMULTANEOUSLY WITH WHIGH. THE
OUTPUT REMAINS IN A HIGH IMPEDANCE STATE.

4-26

~:

UNDEFINED

MB8171·55
MB8171·70

AC Characteristics
(continued)
(Recommended operating
conditions unless otherwise
noted.)

Write Cycle Timing Diagram
Write Cycle:

E Controlled"
~---------------~v~----------------~

ADDRESS

...., . . - - - - - - - - - - TELWH -----------0-1

~--------TWLWH-------~

~------TDVWH-------i·----"i

DATA VALID

HIGH-Z

~; UNDEANED
NOTES; "

t72I ; DON'T CARE

E OR W MUST BE HIGH DURING ADDRESS TRANSITIONS.

AC Test Conditions
Input pulse levels:
O.BV to 2.2V
Input pulse rise and fall times:
5 ns
Timing measurement reference levels: Input: 1.5V
Output: 1.5V
Output Load:

2V

J'NCLUDING SCOPE AND STRAY CAPACITANCE)

FUJITSU
4-27

Mil8171.55
MB8171·70

Package Dimensions
Dimensions in inches
(millimeters)

22·Lead Ceramic (Metal Seal) Dual In·Llne Package
(eas. No.: DIP-22C-A01)

lfWmftml!I: ~
I

.090(2.29)
.110(2.79)

.1

.

I

•.

042(1.09}
.054(1.37)

-II •.

1.000(25AO)REF

4·28

.1ao(3.05)
.150(3.81)

015(0.38)
.023(0.58)

.0a0(0.51)
.050(1.27)

•

MBM2764/2764X .......................... 5-2
MBM27128 ................................ 5-10'
MBM27128X .............................. 5-17
MBM27256 ................................ 5-27
MBM27256X/27256W ...................... 5-36

FUJITSU

:MBM2764·20
MBM2764·25
:MBM2764·30
:MBM2764-3()'X

MICROELECTRONICS, INC.

NMOS 65,536·BIT UV ERASABLE AND
ELECTRICALLY PROGRAMMABLE
READ ONLY MDJIORY
DESCRIPTION
The Fujitsu MBM2764 is a highspeed 65,536-bit static N-channel
MOS erasable and electrically
reprogrammable read only memory (EPROM). It is especially
suited for applications where
rapid turn-around and/or bit pattern experimentation are important.
A 28-pin dual in-line package with
a transparent lid is used to
package the MBM2764. The transparent lid allows the user to expose the device to ultraviolet light

in order to erase the memory bit
pattern previously programmed.
At the completion of erasure, a
new pattern can then be written
Into the memory.
The MBM2764 is fabricated using
N-channel double polysilicon
gate technology with single transistor stacked gate cells. It is
organized as 8,192 words by 8 bits
for use in microprocessor applications. Single + 5V operation
greatly facilitates its use in
systems.

CERDIP PACKAGE
Dlp·28C·C01

FEATURES
• Organized as 8192 words
by 8-blts, fully decoded
• Fast Access Time:
MBM2764-20
200 ns
MBM2764-25
250 ns
300 ns
MBM2764-30
MBM2764-30·X 300 ns
• Simple programming
requirements
• Single location
programming
• Programs with Quick ProTM
(see page 4-7)
• Low power requirement:
550mW active
193mW standby

• Extended temperature
range: MBM2764-3()'X:
-40°C to +85°C
• No clocks required, Fully
static operation
• TTL compatible
Inputs/outputs
• Three·state output
with OR·tie capability
• Output Enable G pin for
simplified memory
expansion
• Single +5V Operation
• Standard 28-pin DIP
package
• Pin compatible with
Intel 2764

PIN ASSIGNMENT
Vpp

NC

A7

Ag

A10

E
07

a,

aD

YBM2'164 BLOCK DIAGRAM

LCC Package
LCC·32C·A01

Vpp Vee
A7 A12
D.

0,

..

V.

,

:

COLUMN
GATING

V"

X.

"

25&.. 258
CEL.I..MATRIX

XJU

t

V~

t

V"

t

VSS

5-2

Ne

l' Ne

MBM2764

ABSOLUTE MA.XD.roM RATINGS

(see NOTE)

Parameter

Symbol

Value

Unit

TA

-25 to +85
-50 to +95

·C

Storage Temperature

Tstg

-65 to + 125

·C

Inputs/Outputs with Respect to Vss

VIN, VOUT

V

VCC with Respect to VSS
Vpp with Respect to VSS

Vcc
Vpp

-0.6 to +7
-0.6 to +7

I MBM2764-20/-25/30

Temperature Under Bias

I MBM2764-30-X

V
V

-0.6 to + 22

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed In the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

FUNCTIONS AND PIN CONNECTIONS

~
(DIP Pin
No_)

Vcc (28)

= +5, Vss (14) =GND

Address Input
(2 -10,21,23 - 25)

Data Q
(11 -13,15 -19)

E

G

Ii

(20)

(22)

(27)

VIL
VIH
Don't Care

VIH
Don't Care

ICC
Supply
(28)

Vpp
(1)

ICC2

VCC

ICC2

Vcc

ICC1

Vcc
Vpp

Mode
Read

AIN

DOUT

VIL

Output Disable

AIN

High Z

VIL

Stand By

Don't Care

High Z

VIH

Don't Care

Program

AIN
AIN
Don't Care

DIN

VIL

VIH

DOUT
High Z

VIL
VIH

VIL
Don't Care

Program Verify
Program Inhibit
Note: 1.

P works

VIL
Don't Care
VIL
VIH
Don't Care

ICC2
ICC2
ICC1

Vpp
Vpp

as if G (output enable) during reading operation.

CAPACITANCE
(TA = 25·C, f = 1 MHz).

Input Capacitance (VIN

Typ

Max

Unit

CIN

4
8

6
12

pF

COUT

Symbol

Parameter

=OV)
=OV)

Ouput Capacitance (VOUT

pF

RECOMMENDED OPERATING CONDmONS
(Referenced to VSS

=GND)

Operating Temperature
Parameter

Supply Voltage
Supply Voltage
Supply Voltage

Symbol

Min

Typ

Max

Unit

Vcc
Vpp

4.50
Vee -0.6

5.0

5.50

V

-

-

Vcc+ 0.6

VSS

GND

V
V

Vcc +1
0.8

V

Input High Voltage

VIH

2.0

Input Low Voltage

VIL

-0.1

-

-

5-3

V

MBM2764-2OI-251-30

MBM2764-3()'X

O·C to + 70·e

-40·C to +85·C

MB:M2764
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Conditions

Input load Current
Output Leakage Current
Vpp Supply Current
Vcc Standby Current
Vcc Supply Current (Active)
Input low Voltage
Input High Voltage
Output low Voltage
Output High Voltage

VIN = 5.5V
VOUT = 5.5V
Vpp = Vcc :t: 0.6V
E=VIH
E-VIL

Symbol

Min

Max

Unit

III
ILO
Ipp

-

10
10
15
35
100
+0.8
VCC+ 1
0.45

pA
pA
rnA
rnA
rnA
V
V
V
V

ICCl
ICC2
VIL
VIH
VOL
VOH

IOL = 2.1mA
IOH = -400pA

-0.1
2.0

-

-

2.4

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

Parameter

Address to Output Delay
E to Output Delay
G to Output Delay
Output Enable High to Output Float
Address to Output Hold

Symbol

TAVQV
TElQV
TGlQV
TGHQZ,
TEHQZ
TAXQX

MBM2764-30
MBM2764·20 MBM2764-25 MBM2764-3()'X
Min

Max

Min

Max

Min

Max

-

-

250
250
100

-

300

10
0

200
200
70
60

0

-

0

10
0

60

10
0

300
120
105

-

0

-

Unit

Test Conditions

E=G = VIL

ns
ns
ns
ns

E-VIL
E=VIL
E- VIL

ns

E=G = VIL

Output Load:

AC TEST CONDITIONS
Input Pulse levels:
Input Rise and Fall Time:
Timing Measurement Reference Levels:

O.8V to 2.2V
s20nsec
1.0V and 2.0V for inputs
O.8V and 2.0V for outputs
1 TTL gate and CL = 100 pF

OPERATION TIMING DIAGRAM
ADDRESSES _ _ _ _ _

...J~~----A-D-~-~-~~-;-E-S--r,--------

OUTPUT - - - - H I G H

z-----f-H1:<

H-*~-HIGH

Notes: (1) G may be delay up to TAVQV-TGLQV after the falling edge of E without impact on TAVQV.
(2) TGHQZ or TEHQZ are specified from G or E, whichever occurs first.

5·4

z-

MBM2764

TYPICAL CHARACTERISTICS CURVES
SUPPLY CURRENT (STANDBY)
vs SUPPLY VOLTAGE

f-

z

UJ

UJ

~ 1.2
u

~

TA~2S0C

~ 1.1

1.1

c"-

_....

-

Ul

1.0

UJ

~

r-

...J

~ 0.9

~ f-"

Ul

o 1.0

1,..0- f- I-"

UJ

N

::::;

~ 0.9
a::
o

z

0.8

N O. 8
u

u

~

4

~

6

S

4

SUPPLY CURRENT (STANDBY)
vs AMBIENT TEMPERATURE

fZ
UJ

SUPPL Y CURRENT (ACTIVE)
vs AMBIENT TEMPERATURE

fZ
UJ

1.2

a:: 1.2
a::

Vee~SV

::J

~ 1.1
""-

r-....

::J
Ul

o 1.0

u
~ 1.1

"c-

::J

i'

N

::::;
~ 0.9

o 1.0

::::;

"

a::
o

z

. 0.8
u

i'-

so

N

~

100

o

w
:::i:

(/J
(/J

«

ffi

N

:J

~

TA~2S0C

Q

1.S

c
«
cw

g

Q

(/J

a:
c

>

ADDRESS ACCESS TIME
vs SUPPLY VOLTAGE

i=

Vee=SV

w

oz

100

w

w

~
a:

so

T A, AMBIENT TEMPERATURE 1°C)

~
Q
Q

«

...........

z

vs AMBIENT TEMPERATURE

i=

.............

a::

o

........

ADDRESS ACCESS TIME

w

........

~ 0.9

T A , AMBIENT TEMPERATURE 1°C)

::.

~

UJ

N

.........

o

I"-..

Ul

r-......

UJ

.0.8
u
u

Vee~SV

::J

u

(/J
(/J

6

S
Vee, SUPPLY VOLTAGE IV)

Vee,SUPPLY VOLTAGE IV)

a::
a::

-

::J

I-" f-

a::

o
z

1.2

::J

u

::J

o

~

TA~2S0C

::J

""-

SUPPLY CURRENT (ACTIVE)
vs SUPPLY VOLTAGE

fZ

1.0

~~

~~

.--.--

I.S

a:
c

c

-

«
cw

r-...
i'..

N

:J

«

~ 1.0

o
Z

>

o

so

g

100

~

T A , AMBIENT TEMPERATUFlE 1°C)

5-5

4

i'

.......

--r--

S
Vee, SUPPLY VOLTAGE IV)

6

MBM2764

TYPICAL CHARACTERISTICS CURVES
E TO

~w

G TO OUTPUT DELAY

OUTPUT DELAY

~w

vs AMBIENT TEMPERATURE

o

~
~

t-

5 1.5

o

~

1.5

~

IW

o

W

.....
i,...-o .....

N

::::;
<
:::;;

..... i-"'"

1.0

Z

>
9
w

l

DB

g

1~

~

VOL. OUTPUT LOW VOLTAGE IV)

5-6

0

200

400

C L • LOAD CAPACITANCE IpF)

MBM2764

PROGRAMMING/ERASING INFORMATION
MEMORYCELL
DESCRIPTION
The MBM2764 is fabricated using a
single-transistor stacked gate cell
construction, implemented via
double-layer polysilicon technology_
The individual cells consist of a bottom floating gate and a top select
gate (see Fig. 1). The top gate is connected to the row decoder, while the
floating gate is used for charge
storage. The cell is programmed by
the injection of high energy electrons
through the oxide and onto the floating gate. The presence of the charge
on the floating gate causes a shift in
the cell threshold (refer to Fig. 2). In
the initial state, the cell has a low
threshold (VTH1) which will enable the
transistor to be turned on when the
cell is selected (via the top select
gate). Programming shifts the threshold to a higher level (VTHO), thus
preventing the cell transistor from
turning on when selected. The status
of the cell (i.e., whether programmed
or not) can be determined by examining its state at the sense threshold
(VTHS), as indicated by the dolled line
in Fig. 2.

CONVENTIONAL
PROGRAMMING
Upon delivery from Fujitsu, or after each
erasure (see Erasure section), the
MBM2764 has all 65,536-bits in the "1"
or high state. "O's" are loaded into the
MBM2764 through the procedure of programming.
The programming mode is entered
when +21V is applied to the Vpp pin
and E and P are both at VIL. During
programming, E is kept at VIL. A 0.1 p.F
capacitor between Vpp and Vss is
needed to prevent excessive voltage
transients, which could damage the
device. The address to be programmed
is applied to the proper address pins.
Eight bit patterns are placed on the
respective output pins. The voltage
levels should be standard TTL levels.
When both the address and data are
stable, 50 msec,-TTL low level pulse is
applied to the P input to accomplish
the programming.
The procedure can be done manually,
address by address, randomly, or automatically via the proper circuitry. All
that is required is that one 50 msec
program pulse be applied at each address to be programmed. It is necessary that this program pulse width not
exceed 55 msec. Therefore, applying a
De level to the P input is prohibited
when programming.

Fig_ 1 - MEMORY CELL

SELECT GATE

~

~
:

DRAIN
FLOATING GATE
SOURCE

Fig_ 2 - MEMORY CELL THRESHOLD SHIFT
PROGRAMMED

NOT PROGRAMMED

"'"

"0"

PROGRAM
ERASE

V TH1

VTHS

(NOT PROGRAMMED)

(SE'NSE THRESHOLD)

VTHO

(PROGRAMMEO)

SELECT GATE VOLTAGE (V)

QUlCKPROTM
In addition to the standard 50 millisecond pulse width programming procedure, the MBM2764 can be programmed with a fast programming algorithm
designed by Fujitsu called Quick Pro1M.
The algorithm (shown in figure 3)
utilizes a sequence of 1 millisecond
pulse to program each location. This algorithm will typically yield a savings of
86% in programming time per device
when utilized in commercially available
programmers. However, in custom programmer deSigns that require less overhead the savings can be even greater.
The programming mode is entered
when +6V is applied to the vee pin
followed by applying +21V to VPP pin.
A TTL low input must be applied to the
E input. Conversely, a TTL high input
must be applied to the G Input. After the
programming voltages and TTL levels
have stabilized, a sequence of 1 millisecond pulses must be applied to the P
pin for programming. After each pulse,
a pulse counter must be incremented
and the location should be checked for
accuracy. Upon verification, an additional sequence of 1 millisecond pulses
equal to the present value of the pulse
counter must be applied to the location
to ensure proper levels of stored
charge. An alternate approach to the
additional pulses would be to apply a
single TTL low pulse with a width equivalent to the value of the pulse counter
multiplied by 1 millisecond. When the
pulse counter reaches a maximum of
20, the verification procedure is skipped

5-7

and a flag is set to indicate a program
failure. Upon completion of programming of the entire device, a final array
verification (all locations) is required.
All Fujitsu devices will typically require
only two 1 millisecond pulses (one initial and one additional) to reach proper
stored charge levels.

ERASURE

In order to clear all locations of their
programmed contents, it is necessary
to expose the MBM2764 to an
ultraviolet light source. A dosage of
15W-seconds/cm2 is required to completely erase an MBM2764_ This
dosage can be obtained by exposure
to an ultraviolet lamp (wavelength of
2537 Angstroms (A) with intensity of
12,OOOp.W/cm2 for 15 to 20 minutes.
The MBM2764 should be about one
inch from the source and all filters
should be removed from the UV light
source prior to erasure.
It is important to note that the
MBM2764 and similar devices, will
erase with light sources having
wavelengths shorter than 4000 A.
Although erasure times will be much
longer than with UV sources at 2537
A, nevertheless, the exposure to
fluorescent light and sunlight will
eventually erase the MEiM2764 and
such exposure should be prevented to
realize maximum system reliability. If
used In such an environment, the
package windows should be covered
by an opaque label or substance.

MBM2764

PROGRAMMING/ERASING INFORMATION
DC CHARACTERISTICS

(Continued)

(TA = 25±5°C, Vee = 5V ±5%, Vpp = 21V ±0.5V)
Parameter

Symbol

Input Leakage Current
Output Low Voltage
Output High Voltage
Vee Supply Current
Input Low Voltage
Input High Voltage
Vpp Supply Current

III
VOL
VOH
lee
VIL
VIH
Ipp

Min

Max

Unit

Test Conditions

-

10
0.45

"A.

VIN = 0.45V-5.25V

V
V
mA
V
V
mA

IOL=2.1 mA
IOH = - 400"A.

-

2.4

-

100
0.8

-0.1
2.0

Vee +1
30

-

-

CE= PGM =VIL

AC CHARACTERISTICS
(TA = 25±.5°C, Vee = 5V ±5%, Vpp = 21V ±0.5V)
Parameter

Symbol

Min

Typ

Max

Unit

Address Setup Time
E Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
f1l
Chip Enable to Output Float Delay
Vpp Setup Time
P Pulse Width·Conventional
J5 Pulse Width·Quick·Pro™
GSetupTime
Data Valid from G

TAVPL
TELPL
TDVPL
TGHAX
TPHDZ
TGHQZ
TVPPHL
TPLPH
TPLPH
TDZGL
TGLQV

2
2
2
0
2

-

-

fLS

fL5
fL5

130

ns

-

fLS
ms·
ms

rn

Notes:
[I TPHDZ + TDZQL '" 5O"s.

ADDRESSES

2

45
0.95
2

-

50
1.00

55
1.05

-

150

-

PROGRAMMING WAVEFORM

)(

K

ADDRESS N
TGHAX

TAVPL
DATA

HIGHZ

DATA IN STABLE
TDVPL

TGLQV

TPHDZ

DATA OUT
VALID
TGHQZ

Vpp
Vpp
Vee

I
TVPPHPL

E

VIH

\

VIL
TELPL

ji

VIH
VIL

G

TPLPH

f-TDZGL-j

VIH

~

VIL

5-8

/

fL5
fLS

fLs
ns

MBM2'164
PACKAGE DIMENSIONS

Dimensions in inches (millimeters)

28-LEAD CERAMIC (CERDIP WITH TRANSPARENT LID) DUAL IN·LINE PACKAGE
Dlp·28C·C01

R .02510.64)
REF

l rn
J LU
.570114.48)
.595115.111

c::J

c::J

c::J

w

.600115.24)
.625115.88)

I
--j

i·l0012.54)MAX

q[

H

.09012.29)
.11012.79)

:

~

:

Ii

11u ~Tf(~ ~lrr
-

.04211.07)
.06211.57)

-

.03210.81)
REF

H

nJ:23015.84)MAX

~.12013.05)

-f-1.15013.81)
.02010. 511
.05011. 27)

1.300133.02)REF
~

5-9

.01310.33)
.02310.58)

.00810.20)
.01410.36)

.600115.24)REF

FUJITSU

MOS Memories

•

MB,..27128-20, MBM27128-25, MBM27128-30
UV Erasable 131,072-Bit
Read Only Memory

Desorlptlon
The Fujitsu MBM27128 Is a high speed 131,072-bit static N-channel MOS erasable and electrically reprogrammable read only
memory (EPROM). It is especially well suited for applications
where rapid turn-around and/or bit pattern experimentation are
important.
A 28-pln dual In-line package or leadless chip carrier (32-pin) with
a transparent lid Is used to package the MBM27128. The transparent lid allows the user to expose the device to ultraviolet light
in order to erase the memory bit pattern previously programmed.
At the completion of erasure, a new pattern can then be written
into the memory.
The MBM27128 is fabricated using N-channel double polysilicon
gate technology with single transistor stacked gate cells. It is
organized as 16,384 words by 8-bits for use In microprocessor applications. Single + 5V operation greatiy facilitates its use In
single supply systems.

• Organized as 18,384 x 8 fully
decoded
• Low power requirement:
1550 mW (act),
193 mW (standby))
• No clocks required (fully static
operetlon)
• Programmable utilizing the
Quick Pro™Algorithm
• Program compatible with the
Intellntallgent Programming ™
Algorithm
• Fast Access Time:
MBM27128-20 200 ns max.
MBM27128-25 250 ns max.
MBM27128-30 300 ns max_

• TTL compatible
inputs/outputs
• Th....state output with OR-tie
capability
• Output Enable G pin provides
precise control of the data bus
• $Ingle +5V operation
• Standard 28-pln DIP package
• Pin compatible with Intel 27128

Quick Pro™ is a trademark of Fujitsu Microelectronics Inc.
Inteligent Programming ™ Is a trademark of Intel Corporation.

5-10

el-

e-

a
~'I

' rr

-

v , ~.

V

"-

~?/O'~ --

~
~

~
~

MBM27128·20
MBM27128·25
MBM27128·30

...

MBM27128 Block Diagram
and Pin A •• lgnment.

Q,

Vee

V"

p

A"

A,
A,

A"
A,

..."

A"

As

ii

"
"

A,.

.,
.,.,
E

A,

.••
As

Q•

,

••

·3

Vss

A.
A,

A,
A"

!

v..

!

!

Vee

..

:sJ

M

2]

-10
00

J!!

 Vpp must not be
switched from Vee to 21 volts or vise·versa.

AC Characteristics
(TA = 25 ±5°C,
Vee = 5V ±5% (Conventional),
Vee = 6V ± O.25V (Quick Pro TM)
Vpp = 21V ±0.5V)

Parameter

$,.mbol

Min

Address Setup Time
Chip Enable Setup Time

TAVPL

2

TELPL
TDZGL

2

p's
p's

2
2

,.s

0
2

p's
p's

Output Enable Time

111

Data Setup Time
Address Hold Time
Data Hold Time
III
Output Enable to Output Float Delay

TDVPL
TGHAX
TPHDZ

TVPPHPL
TPLPH

P Pulse Width-Qulek·ProTM

TPLPH

Programming Waveform

Q

V pp
Vcc
V IH

E

P

G

130
150

TGLQV

Note [l TPHDZ + TDZGL '" 50~s.

V IL
V 1H
V 1L
V 1H
V 1L

FUJITSU
5-15

Max

ns
ns

,.s

2
25
0.95

Unit

"s

TGHQZ

Data Valid from Output Enable
Vpp Setup Time
P Pulse Wldth.conventional

Vpp

TlfP

50

55

ms

1.00

1.05

ms

- ..----MBM27128·20
MBM27128·25
MBM27128.30

Packa.e Dimensions
Dimensions in inches
(millimeters)

28·Lead Cerdlp
(With Trsnsparent Lid)
Dual In·Llne Packa.e
DIP·28C·C01

l

R .025(0.64)
REF

r'" nor .

.570(14.48)

u

u

u

U

U

WWL:Jut:Jut::J

1.435(36.45)
1.500(38.10)

--j

.080(2.29)
.110(2.79)

I-

.6oo(15.24)REF

1lii;;;S:::::-1f---'-

-.loo(2.54)MAX
:

0

.600(15.24)

H

~

:

H H H I- H H H

H

-

.042(1.07)
.062(1.57)

~

J-l

1~230(5.64)MAX

~.120(3.06)

-_p.160(3.81)

-

.032(0.81)
REF

.020i0.511
.05Q( 1.27)

1.300(33.02)REF
.013(0.3 3)
.023(0.58)

32·Pln Leadless Chip Carrier
LCC·32C·A01
·PIN l' INDEX
.015(0.38)

Tl

.545(13.64)
.68a(14.22)

.445(11.30)
.460(11.68)

*Shape of Pin 1 index: Subject to change without notice

FUJITSU
5·16

FUJITSU
•

MBM27128-25-X, MBM27128-30-X
UV Erasable 131,072-Bit
Read Only Memory

D••crlptlon
The Fujitsu MBM27128·X is a high speed 131,072·bit static
N·channel MOS erasable and electrically reprogrammable read
only memory (EPROM). It is especially well suited for appllca·
tions where rapid turn·around and/or bit pattern experimentation
are important.

-

A 28'pin Dual·ln·line package with a transparent lid is used to
package the MBM27128·X. The transparent lid allows the user to
expose the device to ultraviolet light in order to erase the memo
ory bit pattern previously programmed. At the completion of
erasure, a new pattern can then be written into the memory.
The MBM27128·X is fabricated using N·MOS double polysilicon
gate technology with single transistor stacked gate cells. It is
organized as 16,384 words by 8 bits for use in microprocessor ap·
plications. Single + 5V operation greatly facilitates its use in
systems.

F ••tur••

• Extended temperature range:
-40°C to +85°C
• 16,384 words x 8 bits organlza·
tlon, fully decoded
• Simple programming
requirements
• Single location programming
• Programmable utilizing the
Quick Pro™ Algorithm
• Programs with one 50ms or
1ms pulses
• Low power
Active: 860mW
Standby: 220mW
• No clocks required (fully static
operation)

•
•
•
•
•
•
•

Fast access time:
250ns max. (MBM27128·25-X)
300ns max. (MBM27128·30-X)
TTL compatible
Inputs/outputs
Thre.state output with OR·tie
capability
Output Enable (OE) pin for
simplified memory expansion
Single +5V Supply, :1:10%
tolerance
Standard 28·pln DIP package
Interchangeable with Intel
27128·type device

5·17

-

II

-

-

~. rdl , Facl ~.t I.

MBM27128-25-X
MBM27128-aO-X

MBM27128-X Block Diagram
and Pin Assignmant
0,

Yo

AO--~~r---~7.::-~1--+~~~

0,

COLUMN
GATING

A5--~~L-~~~~--J--t-,t---~------------~
Y"
Xo

A,

512 x 256

CELL MATRIX

A13--'---L_==:::::.-_J------::::--IL_____________...J

Vpp

Vee

A12
A7

PGM
A13

As

As

As

As

A4

All

A3

Of

A2

Al0

Al

CE

Ao
01

OS
07

02

Os

03

05

GND

04

X 225

Vpp

GND

Vee

Abaoluta Mulmum Ratings
(See Note)

Paramelar

Symbol

Value

Unit

Temperature Under Bias

T BIAS

-50 to +95

·C

Storage Temperature

TSTG

-65to +125

·C

AlllnputsiOutputs Voltage with Respect to GND

VIN. VOUT

-0.6 to +7

V

Voltage on Ag with Respect to GND

- 0.6 to + 13.5
-0.6 to +22

V

Vpp Voltage with Respect to GND

VA9
Vpp

Supply Voltage with Respect to GND

Vee

-0.6 to +7

V

V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. II is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high impedance circuit.

Capacitance
= 25·C, f = 1 MHz)

(TA

Parameler

Symbol

= OV)
Ouput Capacitance (Vour = OV)

C IN

Input Capacitance (VIN

COUT

FUJITSU
5-18

Min

Typ

Ma..

Unit

4
8

6

pF

12

pF

.

MaM27128·211·X
MaM27128·30·X

Punatlon and
Pin Connection.

Function
(Pin No.)
Addr... lnput
2-10,23-28,
(21)

Data
11-13,
(111-18)

CE OE
(20) (22)

PQM
(27)

Vee Vpp QND
(28) (i) (14)

Mode
Read

AIN

DOUT

V IL

Vee

Vee GND

Output Disable AIN

HlghZ

VIL

V IH
Don't Care

Vee GND

HlghZ

Don't Care

Vee

DIN

VIH
VIL

V IL
Don't Care

Vee

Stand by

V IH

V IL

Vee

DOUT
High Z

VIL
VIH

V IL
Don't Care

V IH
Don't Care

Vee
Vee

Vee GND
Vpp GND
Vpp GND

Don't Care

Program
Program Verify

AIN
AIN
Program Inhibit Don't Care

Recommended Operating
Condition.
(Referenced to GND)

VIL
VIH
Don't Care

Vpp GND

Peramatar

Symbol

Min

Typ

Max

Unit

Vee Supply Voltage'

Vee
Vpp
V IH
V IL

4.5

5.0

5.5

V

Vee+ O.S
Vee +1
0.8

V
V

Vpp Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature

TA

Vee-O.S
2.0
-0.1
-40

V
·C

85

Note: 'Vee must be applied either before or coincident with Vpp and removed either after or coincident with
Vpp.

DC Charaoterl.tlc.
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Input Load Current (V IN = 5.5V)
Output Leakage Current (VOUT
Vee Standby Current

= 5.5V)

«;E =V1H)

=

Vee Supply Current (CE V1J
Vpp Supply Current (Vpp Vce ± O.SV)
Output Low Voltage (VOL 2.1mA)

=

=
Output High Voltage (loH = - 400"A)

FUJITSU
5·19

2.4

Max

Unit

10

pA

10

pA

40
120

mA
mA

5
0.45

V

mA
V

MBM27128·25·X
MBM27128·aO·X

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Address Access Tlme'1
CE to Output Delay
OE to Output Delay'1

tCE

MBM27128·25·X
Min
Max
Tl/P

tACC

Address to Output HoldTime
Output Enable High to Output Float'2

tOE
tOH
tDF

MBM27128·ao·x
Max
Min
Tl/P

300
300
120

250
250
100
0
0

60

0
0

105

ns
ns
ns
ns
ns

Note:
*1. OE may be delayed up to tA!;C.-tOE ailer the falling edge of CE without impact on tACC'
*2. tDF Is specified from OE or CE, whichever occurs first. Output Float is defined as the point where data Is no
longer driven.

Fig. 2 AC Teat Conditions
(Including programming)

Input Pulse Levels:
0.45V to 2.4V
Input Rise and Fall Times:
s20ns
Timing Measurement Reference Levels: 1.0V and 2.0V for Inputs
0.8V and 2.0V for outputs
1 TTL gate and C L = 100 pF
Output Load:

Operation Timing Diagram

ADDRESSES

CE

V,H

-

V1L

-

V1H

-

V1L

-

V1H _

OE

OUTPUT

V1L

-

VOH

-

VOL - _ - - - - - H I G H Z

-----+t-t-t<
'--"--'>....>..t-----

u

VTH1

(NOT PROGRAMMED)

YTHS

(SENSE THRESHOLD)
SELECT GATE VOLTAGE

pulse, which is 3 times as wide
as previous pulse, is applied to EO
to accomplish the programming.

Programming
Upon delivery from Fujitsu, or
after each erasure (see Erasure
section), the MBM27256 has all
262,144-bits in the "1", or high
state. "O's" are loaded into the
MBM27256 through the procedure of programming.

FLOATING GATE

Procedure of QuickProTM (Refer
to the attached flowchart.)

The MBM27256 is programmed
with a fast programming algorithm called QuickProTM designed by Fujitsu. The
programming mode is entered
when +12.5V and +6V are applied to Vp~ and ~ respectively, and E and OE are V1H . A
0.1 p.F capacitor between Vpp
and GND is needed to prevent
excessive voltage transients
which could damage the device.
The address to be programmed
is applied to the proper address
pins. The 8-bit data pattern to be
written is placed on the respective data output pins. The voltage
levels should be standard TTL
levels. When both the address
and data are stable, alms programming pulse is applied to E
and after that one additional

5-31

1) Set the start address (= G)
at the address pins.
2) Set Ys;e = 6V, Vpp = 12.5V
and E = V1H .
3) Clear the programming pulse
counter (X- 0).
4) Input data to respective pins.
5) Apply ONE programming
pu~e (tpw = 1 ms Typ.)
to E.
6) Increment the counter
(X-X + 1).
7) Compare the number (= X)
of applied programming
pulse with 25 and then verify
the programmed data: " programmed data is verified, go
to the next step regardless
of X value. " X = 25 and
programmed data is not verified, the device fails. " X =
25 and programmed data is
not verified, go back to the
step 5).

YTHO

(PROGRAMMED)

M

8) Apply one additional wide
programming pulse to E (3X ms).
9) Compare the address with
an end address (=N). If the
programmed address is the
end address, proceed to the
next step. " not, increment
the address (G-G+l) and
then go to the step 3) for the
next address.
10) Set Vee = Vpp = 5V.
11) Verify all programmed data:
" the verification succeeds,
the programming is complete. " any programmed
data is not the same as original data, the device fails.
A continuous TTL low level
should not apply to EO input pin
during the program mo~ (Vpp =
12.5V, Vee = 6V and OE = V1H)
because it is required that one
programming pulse width does
not exceed 78.75 ms at each
address.

MBM2725e·17
.8.2725 .. 20
MBM272.e·2.

ProgrammlngiEraslng
Information
(Continued)

Erasure
In order to clear all locations of
their programmed contents, it is
necessary to expose the
MBM27256 to an ultraviolet light
source. A dosage of 15 W-seeonds/cm2 is required to completely erase an MBM27256.
This dosage can be obtained by
exposure to an ultraviolet lamp
(wavelength of 2537 Angstroms
(A» with intensity of 120001l.w1

cm2 for 15 to 20 minutes. The
MBM27256 should be about one
inch from the source and all filters should be removed from the
UV light source prior to erasure.
It is important to note that the
. MBM27256 and similar devices,
will erase with light sources having wavelengths shorter than
4000 A. Although erasure time

will be much 10IJ.Qer than with UV
source at 2537 A, nevertheless
the exposure to fluorescent light
and sunlight will eventually erase
the MBM27256, and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment,
the package windows should be
covered by an opaque label or
substance.

Programming Waveform
PROGRAM

ADDRESS

DATA

VERIFY

ADDI110NAL PROGRAM

V,H
V,L

VIHIVOH
VII}VOL

Vpp

Vpp
vee

Vee

Vee+ 1

tvpo
Vee

Ii

V,H
V,L

DE

V,H
V,L

~ DON'T CARE

FUJITSU
5-32

M.M2721515·17
M.M272158·20
M.M272158·211

DC Charaotertstlos
(TA = 25± 5°C,
Vee -1 =6V±0.25V,
Vpp -2 = 12.5V±0.3V)

Parameter

Symbol

Min

Typ

Max

Unit

10

/LA

Input Leakage Current (VIN = 6.25V/0.45V)
Vpp Supply Current (E =VIL ,

OE =

VIH )

Vpp Supply Current (OE = VILl

IpP3

Vee Supply Current

lee

50

mA

5

mA

100

mA

Input Low Level

-0.1

0.8

V

Input High Level

2.0

Vee + 1

V

0.45

V

Output Low Voltage During Verify (lOL = 2.1 mAl
Output High Voltage During Verify (IOL = -400/LA)

VOH

V

2.4

AC Charaotertstlos
(TA = 25±5°C,
Vee = 6V±0.25V,
Vpp = 12.5V±O.3V)

Parameter

Symbol

Min

Address Setup Time

t AS

2

Typ

Max

Unit
/LS

Output Enable Setup Time

tOES

2

/LS

Chip Enable Setup Time

t ES

2

/LS
/LS

Data Setup Time

tos

2

Vpp Setup TIme

tvps

2

/LS

Vee Setup Time

tvs

2

/LS

Address Hold Time

tAH

2

/Ls

Data Hold TIme

tOH

2

/LS

Chip Enable Hold Time

tEH

2

Output Enable to Output Valid

icE

120

ns

Output Disable to Output Float Delay

tOF

105

ns

Programming Pulse Width

tpw

0.95

Programming Pulse Number
Additional Programming Pulse Width

5-33

t APW

2.85

/LS

1.05

ms

25

times

63

ms

M8M272se-17
M_272Se-20
M8M272Se-2S

Programming Flow Chart
Vcc=6V±O.25V

Vpp=12.5V±0.3V
G:START ADDRESS
N:STOP ADDRESS
X:COUNTER VALUE
MAXIMUM 105 molBVTE
MINIMUM 3.8 molBVTE

NG

FUJITSU
5-34

.8.27258·17
.8.27258·20
.8.27258·25

Packag. Dimensions
Dimensions In
inches (miUimeters)

28.L.ad Ceramic ICERDIP with Transparent Lid) Dual In-Lin. Packag.
ICes. No.• DIP·2BC·C01)

J . ") rn

R .025(0.64)
REF

.595(15.11)

.600(15.2')

88
.625(r ) ..

.100(2.54)MAX

.080(2.29)
.110(2.79)

.042(1.06)
.062(1.56)

0.32(0.81)
TVP

~----------~1~.3OO(~~~.0=2)=RE=F~-------f~
.013(0.33)
.023(0.56)

5·35

I

.6OO(15.24)REF

i

:o;;;;;~::-t--~

FUJITSU

MOS Memories
•

MBM27256-20-X, MBM27256-25-X,
MBM27256-30-X, MBM27256-30-W
MOS 262,144-Bit UV Erasable
and Electrically Programmable
Read Only Memory

Description
The Fujitsu MBM27256-X and MBM27256-W are high speed
262,144-biI static NMOS erasable and electrically reprogrammable
read only memories. It is especially well suited for applications
where rapid turnaround and/or bit pattern experimentation are
important.

rA 28-pin Dual-In-Une package with a transparent lid is used to
package the MBM27256-X and MBM27256-W. The transparent lid
allows the user to expose the device to ultraviolet light in order to
erase the memory bit pattern previously programmed. At the completion of erasure, a new pattern can then be written into the
memory.
The MBM27256-X and MBM27256-W are fabricated using NMOS
double polysilicon gate technology with single transistor stacked
gate cells. It is organized as 32,768 words by 8 bits for use in m~
croprocessor applications. Single + 5V operation greatly facilitates
its use in systems.

Features
• 32,768 words x 8-blt
organization, fully decoded
• Single location
programming
• Programmable utilizing the
faster programming algorithm
• Program voltage: 12.SV
iii Low power requlremant
MBM27258-X active: 830 mW
MBM27258-W active: 650 mW
Standby: 237 mW
• No clocks required
(fully static oparation)
• Fast acceH time:
200 ns max.
(MBM27256-20-X)
250 ns max.
(MBM27258-25-X)
300 na max.
(MBM27256-30-X)
300 ns max.
(MBM27256-30-W)

• nL compatible Inputs!
outputs

Three-state output with
OR-tie capability
• Output Enable (<

ADDRESS

Erasure
In order to clear all locations
of their programmed contents,
it is necessary to expose the

MBM27C64 to an ultraviolet
light source. A dosage of
15W-seconds/cm2 is required to
completely erase an MBM27C64.
This dosage can be obtained by
exposure to an ultraviolet lamp
('!!'avelength of 2537 Angstroms
(A) with intensity of 12,000
,..,W/cm2) for 15 to 20 minutes.
The MBM27C64 should be about
one inch from the source and all
filters should be removed from
the UV light source prior to
erasure.
It is important to note that the
MBM27C64 and similar devices,
will erase with light sources having wavelengths shorter than
4000 A. Although erasure times
will be much longer than with UV
sources at 2537 A, nevertheless,
the exposure to fluorescent light
and sunlight will eventually erase
the MBM27C64 and such exposure should be prevented to realize maximum data retention. If
used in such an environment, the
package windows should be covered by an opaque label or
substance.

f- 'AS

r-

-1

Q

DATA IN STABLE

I-- 'DS--

High Z

vee

VALID

I-'OE->O

f-'DH-

!--'DF--

~
~'VS--

~
f-.eES .....

f\-------J

~
tpwa

~tOES-

/
FUJITSU

6-7

'AH_

DATA OUT

vpp
vpp

C

ADDRESS N

· MBM27C84·20
MBM2.7C64·25
MBM27C64·30

DC Characteristics
(TA = 25 ± 5'C,
Vee = 5V ± 5%,
Vpp = 21V ± 0.5V)

Parameter

Symbol

Input leakage current

III

Output low voltage during verify

VOL

Output high voltage during verify

V OH

V cc supply current

ICCl

Min

Max

Unit

Test Conditions

10

mA

VIN = 0.45V-5.25V

0.45

V

IOL = 2.1 mA

V

IOH = -400 rnA

2.4

mA

30

Input low voltage

V 1L

-0.1

0.8

Input high voltage

V 1H

2.0

Vcc

V pp supply current during
programming pulse

Ipp2

V

+

30

0.3

V
mA

Notes: *1 Vee must be applied either coincidently or before Vpp and removed either coincidently or after Vpp.
*2 Vpp must not be greater than 21.5 volts including oVE!'"Shoot. Permanent device damage may occur if the device is taken out or put
into socket remaining Vpp = 21 volts. Also, during E = j5 = VIL' Vpp must not be switched from 5 volts to 21 volts or vise-versa.

AC Characteristics
(TA = 25 ± 5'C,
Vee = 5V ± 5%,
V~~ = 21V ± 0.5V)

Parameter

Symbol

Min

Address setup time

t AS

2

Typ

Max

Unit
/LS

E setup time

icEs

2

/LS

Data setup time

tos

2

/LS

Address hold time

tAH

0

/LS

Data hold time

tOH

2

Chip enable to output float delay

tOF

0

/LS
130

ns

ms

V pp setup time

tvs

2

P pulse width-conventional

t pwc

25

50

55

1.00

1.05

P pulse Width-Quick-ProTM

tpwo

0.95

G setup time

IoEs

2

Data valid from G

tOE

6-8

/LS

ms
/LS

150

ns

MBM27C64·20
MBM27C64·25
MBM27C64·30

Typical Characteristics
Curves

Standby Current
vs. Supply Voltage

ffi
>

~

~

c

w

~[§

1.2

1.0

0.8

z

j

T~:2:~~

1.4

a:
a:

a

Standby Current
vs. Ambient Temperature

----- --

V,ec = 5V
E Yee

_'000
!

=

~

j

10

V

1

-40

6.0

5.0
Vee. SUPPLY VOLTAGE (V)

=>
z

:
w

~

Yee

=

sv

f=4MHz

1.4

./'

1.2

0.8

~

.B

V

10

./
1

0.6
4.0

6.0

5.0
Vee. SUPPLY VOLTAGE (V)

6·9

= 5V
= 25°C

Vee
TA

/

w

120

YIN = Ycc/Vss

V

o

~

ffi
~CJ

/

1.0

a:

80

40

Operation Current
VB. Frequency

a:
a:

CJ

/

TA. AMBIENT TEMPERATURE rC)

Operation Current
vs. Supply Voltage

o

V

/

0.6
4.0

ffi

/

ffi

a: 100

8
8z

0.1

V

L

f. FREQUENCY (MHZ)

/

10

MBM27C84·20
MBM27C84.25
MBM27C84.30

Typical Characteristics
Curves
(Continued)

Address Access Time
vs. Ambient Temperature
w

!

Vee

Address Access Time
vs. Supply Voltage
w

= 5V

1.4

m 1.3

"
~

V

1. 2

m 1. 1

8
.
~

~
~
~

V

1.0

0.9
0.8

./
......

./

./

~

m

~ 1. 2~ .......
m
~
~

V

TA = 25°C

1.4

1.0

...............

w

~
~

~

0.7

g

0.6

:::::......

0.8

o.6

:f

- 40

so

40

120

4.0

Vee. SUPPLY VOLTAGE (V)

G, Ii to Output Delay
vs. Ambient Temperature

E to Output Delay
vs. Ambient Temperature

1.4

~

1.3

!:;

5

1.2

o

1. 1

IW

1.0

~

~

:;:

~
~

5

..
~

V

O. 9

o.s~
o.7
o.6

V

- 40

L

~
o

/

TA. AMBIENT TEMPERATURE ("C)

FUJITSU

6·10

120

= sv

1.

TGLQVJ,.

3

1. 2
1. 1

I~

0.9

~

so

Vee
1.4

e

I~

V

40

6.0

5.0

TA. AMBIENT TEMPERATURE ("C)

5

............

c

./

V-

1. 0

O.S

~

o. 7

~

o.6

~V

V
40

V

40

so

TA. AMBIENT TEMPERATURE ('C)

120

MBM27C64·20
MBM27C64·25
MBM27C64·30

Typical Characteristics
Curves
(Continued)

G, P High to Output Float
vs. Ambient Temperature

Output Source Current
vs. Output High Voltage

Vee

= SV

1.4

!i:w
1

0
9

8

-

TGHQZ(P)
TGHQZ(G)

Vee

c

.§.

Q

20

a:
a:
::>
u
w
u
a:

..
::>
0

10

::>

i!:

::>
0

~

o.6
80

40

-40

120

Vee

/'

= 5V

a:
a:
::>
u

~'"

.
I-

w

..'"
..'"
;::

/

IZ
W

U
U

f

0
0

'"
w

~

!:i

/

0

o

= 2S C

1.'

1.2

~

''a:""

1.0

~

0.8

0

L
oV

TA

0

::>
::>

Vee = 5V

1.6

w
a:

/

I-

....

....V

V

1--

z

0.2

0.4

0.6

"

w

/
10

'.0

3.0

Address Access Time
vs. Load Capacitance

TA = 2S"C

.§.

...........

VOH. OUTPUT HIGH VOLTAGE (V)

Output Sink Currant
vs. Output Low Voltage

20

..........

r--...

TA. AMBIENT TEMPERATURE eC)

C

--

r--

I-

7

= 5V

TA = 2S C

0.8

1.0

VOL. OUTPUT LOW VOLTAGE (V)

6-11

1.2

200

400

CL. LOAD CAPACITANCE (pF)

D

5.0

MBM27C64.20
MBM27C84-25
MBM27C84·30

Package Dimensions
Dimensions in inches
(millimeters)

28.Lead Ceramic (Cerdlp with Transparent Lid)
Dual In·Line Package
DIP·28C·C01

R .025(0.64)
REF

.570(14.48)
.595(15.11)

r·

.600(15.24)
25
.•

..

1.5T38. 0)

88
) ..

\S;;:~-"'--.....L

-

.100(2.54)MAX

~~~;;;;;;;~~;;d~
--.i230(5.84)MAX
~ .120(3.05)
.150(3.81)
.090(2.29)
.110(2.79)

--r

~--------~1~.300(==33~.0=~~RE=F~----~~

.020(0.51)
.050(1.27)

32·Pad Ceramic (Metal Seal) Leadless Chip Carrier
LCCo32C·A01
.360(9.14)TYP

n

.015(0.38) TYP

.545(13.84)
.560(14.22)

.445(11.30)
.460(11.68)

.130(3.30)MAX

·SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NonCE.

6-12

FUJITSU

MOS Memories
•

MBM27C64-25X, MBM27C64-30X, MBM27C64-30W
CMOS 65,536-BIT UV Erasable
and Electrically Programmable
Read Only Memory

Description
The Fujitsu MBM27C64 is a high speed 65,536-bit static Complementary MOS erasable and electrically reprogram mabie read only
memory (EPROM). It is especially suited for applications where the
extremely low power consumption of CMOS is essential. The device dissipates only 40 mW/MHz in the active mode and 5,..W
in the standby mode. It provides the same high speed performance
as the NMOS MBM2764-type devices.
This package is available in either a 28-pin dual-in-line package or
a 32-pin LCC package both of which have a transparent lid. The
transparent lid allows the user to expose the device to ultraviolet
light in order to erase the memory bit pattern previously programmed. At the completion of erasure, a new pettern can be programmed into the memory.
The MBM27C64 is fabricated using CMOS double polysilicon gete
techoology with single transistor stacked gate cells. It is organized
as 8,192 words by 8-bits for use in microprocessor applications.
Single +5V operation greatly facilitates its use in systems.

Featurea
• Extended temp. range:
MBM27C64X -400C to +8S"C
MBM27C64W -55"C to +12S"C
• CMOS po_ conaumptlon:
S5O,..W max. (Standby)
S,..W typ_ (Standby)
42 mW/MHz (Active)
• Faat accesa time:
MBM27C64-2SX 250 ns max.
MBM27C64-30X 300 ns max.
MBM27C64-30W 300 ns max.
• Utilizes the same simple
programming requirements
as MBM2764

• Single +5V operation
• 10% Vcc tolerance stsndard

• TTL compatible Inputs/outputs
• Threa-atate output provides
OR-tie cepablillL
• Output Enable (OE) pin providea preclae data bua control
• Pin and function compatible
with 2764-type devices

6-13

MBM27C64-25X
MBM27C64-30X
MBM27C64-30W

MBM27C64 Block Diagram
and Pin Assignments

Or

00

V••

Vee

A,_

P

A7

Do

Dr

v.

At>

"-

COLUMN
GATING

V3'

X.

A,

256 x 256
CELL MATRIX

NC

Ao

At>

As

A,

"-

All

A.

li

A_

A,.

A,

E

At>

Or

o.

00

0,

0,

0_

00

Vss

0.

Au

X...

t

t

Vpp

Vpp Vee

t

A7A12

Ne

P Ne

141312.1132131.30,

Vss

Vee

L_.L_J._...

A6
As

~J

!J

r_.I._..L_.J

LJ

!J

A11

L2~ ~c
~jG

A2~~
A, 19~
Ao 1_~

~2~ ~10
~~3 E
~2_2 Or
L2] Qs

Ne '.?:.l
00

As
~.!I Ag

L':!

A4 ~~

-'3

§t

1~J

r;4T15T1sT17T18T19T201
0, G.z NC G.z00 0,
Vss

Absolute Maximum Ratings
(See Note)
Parameter

Symbol

MBM27C64X
Value

MBM27C64W
Value

Unit

Temperature under bias

TA

-50 to +95

-65 to +135

·C

Storage temperature

TSTG

-65 to +125

-65 to +150

·C

Inputs/outputs with respect to Vss

VIN • VOUT

-0.6 to +7

-0.6 to +7

V

Vee with respect to Vss

Vee

-0.6 to +7

-0.6 to +7

V

Vpp with respect to Vss

Vpp

-0.6 to +22

-0.6 to +22

V

FUJI'I'SU

6-14

MBM27C64·25X
MBM27C64·30X
MBM27C64·30W

Functions and Pin
Connections
(VeC<28)

Function
(Pin No.)

= +5, Vss(14) = GND)

Read

VIL

Output disable

(Referenced to Vss = GND)

Vpp
(i)

VIL

V IH

Vee

Vee

V IH

Don't Care

Don't Care

High Z

VIL

Vee

Vee
Vee

Don't Care VIL

High Z

V IH

Don't Care Don't Care Vee

IN

VIL

V IH

VIL

Vee

Vpp

Program verify

OUT

VIL

VIL

V IH

Vee

Vpp

High Z

V IH

Don't Care Don't Care Vee

Vpp

Don't Care

Program inhibit

Don't Care

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage'1

Vee

4.50

5.0

5.50

V

Vee -0.6

Vee +0.6

V

Supply Voltage

Vpp

Supply Voltage

Vss

Input High Voltage

VIH

2.0

Vcc +0.3

V

Input Low Voltage

VIL

-0.1

0.8

V

Note: ·1

Capacitance
(TA = 25'C, f = 1 MHz)

Vee
Supply
(28)

Ii

Program

Stand by

Recommended Operating
Conditions

(27)

Address Input
Data 1/0
E G
(2.10,21,23·25) (11·13, 15·19) (20) (22)

Mode

GND

Parameter

-40'C to +85'C MBM27C64X
-55'C to +125'C MBM27C64W

V

Vee must be applied either before or coincident with Vpp and

Operating Temperature

removed either after or coincident with Vpp.

Typ

Max

Unit

Input capacitance (VIN = OV)

Symbol

4

6

pF

Output capacitance (VOUT = OV)

8

12

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Input load current (VIN

=

5.50V)

Output leakage current (VOUT

=

5.50V)

V pp supply current

=

Vec standby current (E

V IH )

=

VIC>

=4

Vec active current (E

Output low voltage (lOL

Output high voltage (lOH
Note: *1

Vee =

=

=

MHz, lOUT

2.1 mAl

=

Max

Unit

10

/LA

ILO

10

/LA

Ipp

100

-400 p.A)

5.0V and TA = 25°C.

6·15

0 mAl

=

0 mAl

/LA
mA

ISB1

V,,;c standby current
(E = Vee - 0.3V to Vcc + 0.3V, lOUT

Vce operation current (f

Min

Typ"

III

ISB2

100

/LA
mA

ICC1

30

ICC2

30

mA

VOL

0.45

V

VOH

2.4

V

MBM27C64·25X
MBM27C64·30X
MBM27C64·30W

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

MBM27C64·25X
Min
Max

Symbol

MBM27C64-30X
MBM27C64·30W
Min
Max

Unit

Address to Output Delay
(E = G = VIL • ]5' = VIH )

TAVAV

250

300

ns

E to Output Delay (G = VIL • j5 = VIH )

TELOV

250

300

ns

= VIL • P' = VIH)
= G = VIL )

TGLOV

100

120

ns

TPHOV

100

120

ns

Output Enable High to Output Floaf2

TGHOZ

0

105

ns

Address to Output Hold

TAXOX

0

G to Output Delay (E
P to Output Delay (E

Note: *2 TGHQZ is specified from E,

a

90

ns

0

G, or P, whichever occurs first.

Operation Timing Diagram
ADDRESSES

~

~

ADDRESSES VALID

TAVAV

_TAXQX......

/

\
I---TELQV _ _

/

\
_TGLQV_

/

\
_TPHQV_

HIGHZ

OUTPUT

NOTE:

/1/

\\\

G MAY BE

I+--TGHQZ

.......
~~

OUTPUT VALID

HIGHZ

'IV

DELAYED UP TO TAVAV-TGLQV AFTER THE FALLING EDGE OF E WITHOUT IMPACT ON TAVAV.

AC Test Conditions
Input Pulse Levels: 0.8 V to 2.2 V
Input Rise and Fall Time: .. 20 nsec
Timing Measurement Reference Levels: 1.0 and 2.0V for inputs
0.8 and 2.0V for outputs
1 TTL gate and CL = 100 pF

OUTPUT LOAD:

~
I

FUJITSU

6·16

MBM27C84-2SX
MBM27C64·30X
MBM27C64·30W

Programmlng/Era.lng
Informa.lon

Memory Cell Description
The MBM27C64 is fabricated
using a single-transistor stacked
gate cell construction, implemented via double-layer polysilicon technology. The individual
cells consist of a bottom floating
gate and a top select gate (see
Memory Cell Diagram). The top
gate is connected to the row decoder, while the floating gate is
used for charge storage. The cell
is programmed by the injection of
high energy electrons through the
oxide and onto the floating gate.
The presence of the charge on
the floating gate causes a shift in
the cell threshold (refer to Memory Cell Threshold Shift diagram).
In the initial state, cell has a low
threshold (VTH1 ) which will enable the transistor to be turned on
when the cell is selected (via the
top select gate). Programming
shifts the threshold to a higher
level (VTHO)' thus preventing the
cell transistor from tuming on
when selected. The status of the
cell (i.e., whether programmed or
not) can be determined by examining its state at the sense
threshold (VTHS), as indicated by
the dotted line in Memory Cell
Threshold Shift diagram.

The procedure can be done manually, address by address, randomly, or automatically via the
proper circuitry. All that is required is that one 50 msec program pulse be applied at each

address to be programmed. It is
necessary that this program
pulse width not exceed 55 msec.
Therefore, applying a DC level to
the j5 input is prohibited when
programming.

Memory Cell

DRAIN

SELECT

GAT~ ....

0----

_ _- -

&--_---

FLOATING GATE

SOURCE

Memory Cell Threshold Shift

Upon delivery from Fujitsu, or
after each erasure (see Erasure
section), the MBM27C64 has all
65,536 bits in the "I" or high
state. "O's" are loaded into the
MBM27C64 through the procedure of programming.

NOT PROGRAMMED

PROGRAMMED

"1"

"0"

PROGRAM

ERASE

VTHt

VTHS

(NOT PROGRAMMED)

(SENSE THRESHOLD)

VTHO

(PROGRAMMED)

SELECT GATE VOLTAGE (V)

Conventional Programming
The programming mode is
entered when +21V is applied to
the Vpp pin and E and j5 are both
at VIL . During programming, EO is
kept at V IL • A O.Ip.F capacitor between Vpp and Vss is needed to
prevent excessive voltage transients, which could damage the
device. The address to be programmed is applied to the proper
address pins. A pattern of eight
bits are placed on the respective
output pins. The voltage levels
should be standard TTL levels.
When both the address and
data are stable, 50 msec, TTL
low level pulse is applied
to the j5 input to accomplish
the programming.

6-17

MBM27C84·25X
MBM27C84·30X
MBM27C84·30W

Programming/Erasing
Information
(Continued)

Quick Pro™ Programming

pulse counter must be incremented and the location should
be checked for accuracy. Upon
verification, an additional sequence of 1 millisecond pulses
equal to the present value of the
pulse counter must be applied to
the location to ensure proper levels of stored charge. An alternate
approach to the additional pulses
would be to apply a single TTL
low pulse with a width equivalent
to the value of the pulse counter
multiplied by 1 millisecond. When
the pulse counter reaches a maximum of 20, the verification procedure is skipped and a flag is
set to indicate a program failure.
Upon completion of programming
of the entire device, a final array
verification (all locations) is required. All Fujitsu devices will
typically require only two 1 millisecond pulses (one initial and
one additional) to reach proper
stored charge levels.

In addition to the standard
50 millisecond pulse width programming procedure, the
MBM27C64 can be programmed
with a fast programming algo·
rithm designed by Fujitsu called
Quick ProTM. The algorithm
(shown in figure 3) utilizes a sequence of 1 millisecond pulses to
program each location. This algorithm will typically yield a savings
of 86% in programming time per
device when utilized in commercially available programmers.
However, in custom programmer
designs that require less overhead the savings can be even
greater.
The programming mode is entered when + 6V is applied to the
Vee pin followed by applying
+21V to Vpp pin. A TTL low input
must be applied to the E input
and a TTL h.!lJh input must be applied to the G input. After the programming voltages and TTL
levels have stabilized, a sequence of 1 millisecond pulses
must be applied to the j5 pin for
programming. After each pulse, a

Programming Waveform

=>

ADDRESS

Q

Erasure
In order to clear all locations
of their programmed contents, it
is necessary to expose the

MBM27C64 to an ultraviolet
light source. A dosage of
15W-seconds/cm2 is required to
completely erase an MBM27C64.
This dosage can be obtained by
exposure to an ultraviolet lamp
(wavelength of 2537 Angstroms
(A) with intensity of 12,000
!-,W/cm2) for 15 to 20 minutes.
The MBM27C64 should be about
one inch from the source and
all filters should be removed from
the UV light source prior to
erasure.
It is important to note that the
MBM27C64 and similar devices,
will erase with light sources having wavelengths shorter than
4000 A. Although erasure times
will be much 10n9.,er than with UV
sources at 2537 A, nevertheless,
the exposure to fluorescent light
and sunlight will eventually erase
the MBM27C64 and such exposure should be prevented to realize maximum data retention. If
used in such an environment, the
package windows should be covered by an opaque label or
substance.

r-

i--'AS ..,
HighZ

DATA IN STABLE

'r;.
j+-'DH ....

I-- 'os ......
vee

j.-'OE-+

I--'DF--

-----.l
1- .........

~
l--.eES ......

I\-----J
'pwe

~

1--'0.. -

/
FUJITSU

6-18

·AH .....

DATA OUT
VALID

vpp
vpp

L

ADDRESS N

MBM27C64.25X
MBM27C64·30X
MBM27C64·30W

DC Characteristics
(TA = 25 ± 5'C,
Vee = 5V ± 5%
Vpp = 21V ±0.5V)

Parameter

Symbol

Max

Unit

Test Conditions

Input leakage current

III

10

/LA

VIN

Output low voltage during verify

VOL

0.45

V

IOL

Output high voltage during verify

V OH

Vcc supply current

Icc1

Input low voltage

VIL

Input high voltage

VIH

Vpp supply current during
programming pulse

Min

2.4

V
30

mA

-0.1

0.8

V

2.0

Vcc + 0.3

V

30

mA

Ipp2

= 0.45V-5.25V
= 2.1 mA
IOH = -400 mA

E

=

P

=

VIL

Notes: ·1 Vee must be applied either coincidently or before Vpp and removed either cOincidently or after Vpp.
"2 Vpp must not be greater than 21.5 volts including ov~rsho~t. PermAnent device damage may occur if the device is taken out or put
into socket remaining Vpp = 21 volts. Also, during E = P = V1L . Vpp must not be switched from 5 volts to 21 volts or vise-versa.

AC Characteristics
(fA = 25 ± 5'C,
Vee = 5V ± 5%
Vpp = 21V ±0.5V)

Parameter

Symbol

Min

Address setup time

t AS

2

E setup time

t CES

2

Data setup time

tos

2

Address hold time

tAH

0

Typ

Max

Unit

130

ns

Data hold time

toH

2

Chip enable to output float delay

toF

0

Vpp setup time

tvs

2

P pulse width-conventional

t pwc

25

50

55

ms

P pulse Width-Quick-ProTM

1.00

1.05

ms

150

ns

tpWQ

0.95

G setup time

toES

2

Data valid from G

tOE

6-19

/LS

MBM27C84·25X
MBM27C84-30X
MBM27C84.30W

Typical Characteristics
Curves

Standby Cunent
vs. Supply Voltage

Standby Current
vs. Ambient Temperature

11.

T\:=.. 2:~~

4

..

§
i!

..

1.2

1.0

I --l!5

O.8

z

j

Vie==v~~

--

--~

0

lr-

•
•.0

S.O

-40

Vee, SUPPLY VOLTAGE (V)

!;i
iii

~

Vee = 5V

1.4

=

V

1.0

]

D••

~

= vcclvss

./

1.2

0.8

120

Vee = 5V
TA
2S"C

f=4MHz
VIN

~

:IE

80

Operation Current
vs. Frequency

~

~

40

T A, AMBIENT TEMPERATURE ("C)

Operation Current
vs. Supply Voltage

il

/

/

o.

4.0

Ii

/

V

/

./
/'

4.0

./

./
1

S.O

6.0

Vee, SUPPLY VOLTAGE (V)

6-20

0.1

V

V

I, FREQUENCY (MHZ)

/

10

MBM27C84·25X
MBM27C84·30X
MBM27C84·30W

Typical Characterl.tlc.
Curve.

Addre•• Acce •• Time
v•• Ambient Temperature
Vee

Addre•• Acce •• Time
v •• Supply Voltage

= 5V

4

/'

3

V

2
1

V

0

9

8f-""

./

./

~

1, 4

~c~

1,2

TA = 25°C

~

~

/"

C~
~

"'-

1.0

'" ~

0,8

II:

11

7

~

6
40

80

40

120

0.6

Vee. SUPPLY VOLTAGE (V)

0, Ii to OUtput Delay
v •• Ambient Temperature

E to Output Delay
v•• Ambient Temperature

1. 3

~

1.2

o

1.1

IW

1.0

g

5

1.4

~

V

./

~

Vee - 5V

1. 4
TGLQVl

I-

~

1.

o

1, 2

g

1. 1

3

II

1.0

l[!f

0, 9

!>!
~

o.7

I

o. 8

o. 6

~

o. 6

9

~

./

V

9 o. V
I o.8""
-40

V

w

40

6,0

5,0

4,0

TA. AMBIENT TEMPERATURE ('C)

5

---

~

80

TA. AMBIENT TEMPERATURE ("C)

PUJITSU

6·21

120

. . . .V

V

/'

~V

V

o.7
40

40

80

TA. AMBIENT TEMPERATURE ("C)

120

MBM27C64·20
MBM27C64·25
MBM27C64-30

G. Ii High to Output
Float vs. Ambient Temp

Output Source Current
vs Output High Voltage
Vee = 5V
TA
25°C

Vee = SV

=

1.4

~

1.3

liI!~

1.2

r.i:o

0

~itl. 1
a~
~J!: 1.0
.... :>

i~

--

TGHQZ~

TGHQZ(G)

!""""

O.9

!i I-

o.8

~

0.7

..........
..........
..........
.......

0.6
40

40

..........

120

80

3.0

TA, AMBIENT TEMPERATURE ("C)

Address Access Time
vs L_d Capacitance
w

/'

Vee = 5V
TA = 25°C

0

:E

1=

'"'"0w
0

/'

e

./

'"'"w
a

/

Vee = SV
TA = 25°C

1.6

1.4

,/'

0:

a
e

/

1.2

ill

l:le

/

:E
0:
0

1.0

1---

........... i-"""

..... V

Z

/

oV

5.0

VOH, OUTPUT HIGH VOLTAGE (V)

Output Sink Current
vs Output Low Voltage

0

4.0

"

$
0.2

0.4

0.6

0.8

1.0

VOL, OUTPUT LOW VOLTAGE (V)

6·22

1.2

0.8
200

400

CL, LOAD CAPACITANCE (pF)

MBM27C84-25X
MBM27C84-30X
MBM27C84-30W

Package Dlmonslons
Dimensions in inches
(millimeters)

28·Lead Ceramic ICerdlp with Transparent Lid)
Dual In· Line Package Dlp·28C·C01

R .025(0.84)
REF
.570(14.48)
.595(15.11)
.600(15.24)

.625T·88) .. "'"';;;:;:::-f'----'-

.090(2.29)
.110(2.79)

~--------~==~~=~----~~

32·Pad Ceramic IMetal Seal) Leadless Chip Carrier
LCC·32C·A01
.36O(9.14)TYP

.015{0.39)TYP

rl

.545(13.84)
.560(14.22)

LL

.445{11.30)
.460(11.68)

.130(3.30)MAX

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE.

6-23

MBM 27C128-20
MBM 27C128-25

CMOS 131072 BIT UV ERASABLE AND ELECTRICALLY
PROGRAMMABLE READ ONLY MEMORY
The Fujitsu MBM 27C128 is a high speed 131,072 bit static complementary
MOS erasable and electrically reprogrammable read only memory (EPROM).
It is. especially well suited for application where rapid turn·around and/or bit
pattern experimentation, and low-power consumption are important.
A 28-pin dual-in line package with a transparent lid and 32-Pad Leadless Chip
Carrier (LCC) are used to package the M8M 27C128.The transparent lid allows
the user to expose the device to ultraviolet light in order to erase the memory
bit pattern previously programmed. At the completion of erasure, a new pattern can then be written into the memory.

CERAMIC PACKAGE
DIP·28C-COl

The MBM 27C128 is fabricated using CMOS double polysilicon gate technology with single transistor stacked gate cells. It is organized as 16,384
words by 8 bits for use in microprocessor applications. Single +5V operation
greatly facilitates its use in systems.
• CMOS power consumption
Standby: 550j.lW max.
41 mW/MHz
Active
• 16,384 words x 8 bits orga·
nization, fully decoded
• Single location programming
• Programmable utilizing
the Quick Pro™ Algo~ithm
• Programs with one 50ms or
1ms pulses
• No clocks required (fully
static operation)
• TTL compatible inputs/outputs

•

Fast access time:
200ns max. (MBM 27C128-20)
250ns max. (MBM 27C128-25)

CERAMIC PACKAGE
LCC-32C·AOl

• Three·state output with
OR ·tie capabi lity
• Output Enable (OE) pin for
simplified memory expansion
• Single +5V supply, ± 10%
tolerance
• Standard 28-pin DIP package
and 32-pad LCC
• Interchangeable with 27128type device

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating

Symbol

Value

Unit

T BIAS

-25 to +85

°c

TSTG

-65 to +125

°c

VIN, VOUT

-0.6 to +7

V

Voltage on Ag with Respect to GND

VAg

-0.6 to +13.5

V

Vpp Voltage with Respect to GND

Vpp

-0.6 to +22

V

Vee

-0.6 to +7

V

Temperature under Bias
Strage Temperature
All Inputs/Outputs Voltage
with Respect to GND

Supply Voltage with Respect to GND

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to.
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Quick Pro ™ is a trademark of FUJITSU LIMITED
6-24

rr41fsTlsT17mlT191:i01
~Oa

NCo.OsOt;

This device contains circuitry to protect the
inputs against damage due to high static volt·
ages or electric fields. However, it is advised
that normal precautions be taken to avoid

application of any voltaga higher than maxi·
mum rated voltages to this high impedance
circuit.

1111111111111111111111111111111111111111111111111

FUJITSU

MBM 27Cl28-20
MBM 27Cl28-25

1111111111111111111111111111111111111111111111111

Fig. 1 - MBM 27C128 BLOCK DIAGRAM

0,

OE

OUTPUT ENAB LE &
CHIP ENABLE &
PROGRAM LOGIC

CE
PGM

OUTPUT
BUFFER

-

!

DO

DATA INPUT
BUFFER &
PROGRAMMING
CONTROL

D7

1···1 -t
0,

--

Os

COLUMN
GATING

Yo

COLUMN
DECODER

:
Y63

!
:

512 x 256
Xo

CELL MATRIX

ROW
DECODER
X 255

t

GND

Vee

CAPACITANCE

(TA =

25°C, f

=1 MHz)
Symbol

Parameter

Min

Typ

Max

Unit

Input Capacitance (V IN = OV)

C IN

4

6

pF

Output Capacitance (V OUT = OV)

COUT

8

12

pF

6-25

MBM 27Cl28-20 1111111111111111111111111111111111111111111111111111
MBM 27Cl28-25 FUJITSU

11~11~1111111111~111111~lmlll~II~II~III~11

FUNCTIONS AND PIN CONNECTIONS

~

(Pin No.)

Address Input
(2~10, 21,

Data I/O

23~26)

15~19)

Mode

Read

AIN

Output Disable

AIN

Standby

Don't Care

Program
Program Verify
Program Inhibit

(11~13,

DOUT
High'Z

CE
(20)

OE
(22)

V IL

PGM
(27)

Vee
(28)

Vpp
(1)

GND
(14)

V IL

V IH

Vee

Vee

GND

V IH

Don't Care
V IL

Vee

Vee

GND

Don't Care
Don't Care

Don't Care

Vee

Vee

GND

V IL

High·Z

V IH

AIN

DIN

V IL

V IH

V IL

Vee

Vpp

GND

AIN

DOUT

V IL

V IL

V IH

Vee

V pp

GND

Don't Care

High'Z

V IH

Don't Care

Vee

Vpp

GND

Don't Care

RECOMMENDED OPERATING CONDITIONS (Referenced to GND)
Parameter

Symbol

Min

Typ
5.0

Max

Unit

Vec Supply Voitage'l

Vee

4.5

5.5

V

V pp Supply Voltage

V pp

Vee -0.6

Vee +0.6

V

Input High Voltage

V IH

2.0

Vee +0.3

V

Input Low Voltage

V IL

-0.1

0.8

V

Operati rig Temperatu re

TA

0

70

°c

Note: '1

Vee must be applied either before or coincident with V pp and removed either after or coincident with Vpp .

DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Parameter

Symbol

Min

Typ

Max

Unit

Input Load Current (V IN = 5.5V)

ILl

10

j.lA

Output Leakage Current (V OUT = 5.5V)

I LO

10

j.lA

V pp Supply Current

Ipp

100

j.lA

Vee Standby Current (CE = V IH )

IS61

1

mA

Vee Standby Current
(CE"=Vee -0.3V to Vee +0.3V, louT=OmA)

IS62

100

j.lA

Vee Active Current (CE = V IL )

leel

30

mA

Vee Operation Current (f = 4MHZ, lOUT = OmA)

lec2

30

rnA

Output Low Voltage (lOL = 2.1mA)

VOL

0.45

V

Output High Voltage UOH = -400j.lA)

V OH1

2.4

V

Output High Voltage UOH = -100j.lA)

V OH2

Vec ·0.7

V

1

6-26

1

MBM 27C128-2O
MBM 27Cl28-25

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

Fig.2 - AC TEST CONDITIONS (INCLUDING PROGRAMMING)
Input Pulse Levels:
Input Rise and Fall Times:

0.8V to 2.2V
~ 20ns

Timing Measurement Reference Levels:

1.0V and 2.0V for inputs
0.8V and 2.0V for outputs
1 TTL gate and C L = 100pF

Output Load:

~
I

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
MBM 27C128·20
Parameter

MBM 27C128·25
Unit

Symbol
Typ

Min

Max

Min

Typ

Max

Address Access Time"

t ACC

200

250

ns

CE to Output Delay

tCE

200

250

ns

OE to Output DelaY*'

tOE

70

100

ns

Address to Output Hold

tOH

0

Output Enable High to Output Float2

tOF

0

Notes:

*1
*2

ns

0

60

0

ns

60

OE may be delayed up to tACC - tOE after the falling edge of CE without impact on tACC.
tOF is specified from OE or CEo whichever occurs first.
Output Float is defined as the point where data is no longer driven.

OPERATION TIMING DIAGRAM

ADDRESS

CE

OE

V1H -

VII~_

)

V1H V1L -

K

ADDRESS
VALID

I

~

tCE

V1H V1L -

I
1

tOE
tOH

tACC
OUTPUT

~

HIGH·Z

////,
~

6-27

VALID OUTPUT

k:, ~ HIGH·Z
f// ~

MBM 27C128-20
MBM 27C128-25 FUJITSU

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

PROGRAMMING/ERASING INFORMATION
MEMORY CELL DESCRIPTION
Fig. 3 - MEMORY CELL

The MBM 27C128 is fabricated using a
single-transistor stacked gate cell construction, implemented via doublelayer polysilicon technology. The individual cells consist of a bottom
floating gate and a top select gate (see
Fig. 3). The top gate is connected to
the row decorder, while the floating
gate is used for charge storage. The cell
is programmed by the injection of high
energy electrons through the oxide
and onto the floating gate. The presence of the charge on the floating gate
causes a shift in the cell threshold
(refer to Fig. 4). In the initial state, the
cell has a low threshold (V TH1 ) which
will enable the transistor to be turned
on when the cell is selected (via the top
select gate). Programming shifts the
threshold to a higher level (V THO ).
thus preventing the cell transistor
from turning on when selected. The
status of the cell (i.e., whether programmed or not) can be determined by
examining its state at the sense threshold (V THS ), as indicated by the dotted
line in Fig. 4.
PROGRAMMING
Upon delivery from Fujitsu, or after
each erasure (see Erasure section), the
MBM 27C128 has all 131,072 bits in the
"1", or high, state. "O's" are loaded
into the MBM 27C128 through the
procedure of programming.
Standard Programming
The programming mode is entered when
+21 V is applied to the Vpp pin and CE
and PGM are both at V 1L • During programming, CE is kept at V IL . A O.lMF
capacitor between Vpp and GND is needed to prevent excessive voltage transients, which could damage the device. The
address to be programmed is applied to
the proper address pins. 8 bit patterns
are placed on the respective data output
pins. The voltage levels should be standard TTL levels. When both the address
and data are stable, a 50 msec, TTL
low-level pu Ise is appl ied to the PGM

SELECT GATE

~

~:

DRAIN
FLOATING GATE
SOURCE

Fig.4 - MEMORY CELL THRESHOLD SHIFT
...J
...J

I

NOT PROGRAMMED

I

"'"

w

u
:La:
1.:10
=>10",
a::L'"
I- Z
<{
I-a:
ZIw
a:
a:
=>
u

PROGRAMMED

I
I

.

"0"

I
I
I PROGRAM
I
I
I
I ERASE
I

.

I
I
I
I

V T H1

VTHS

(NOT PROGRAMMED)

(SENSE THRESHOLD)

VTHO

(PROGRAMMED)

SELECT GATE VOLTAGE IV)

input to accomplish the programming.
The procedure can be done manually,
address by address, randomly, or automatically via the proper circuitry. All
that is required is that one 50 msec
program pulse be applied at each address to be programmed. It is necessary that this program pulse width not
exceed 55 msec. Therefore, applying a
DC level to the PGM input is prohibited
when programming.
Quick Programming
In addition to the standard 50 msec
pulse width programmi ng procedure,
the MBM 27C128 can be programmed
with a fast programming algorithm
designed by Fujitsu called Quick Pro TM.
The algorithm utilizes a sequence of a
1 ms pulse to program each location.
The programming mode is entered when
+21 V and +6V are applied to the Vpp
pin and Vee pin respectively, and

QUick Pro™ is a trademark of FUJITSU LIMITED
6-28

PGM and OE are V IH. During programming, CE is kept at V IL . A O.lMF
capacitor between Vpp and GND is
needed to prevent excessive voltage
transients which could damage the
device. The address to be programmed
is applied to the proper address pins.
The 8 bit patterns are placed on the
respective data output pins. The voltage
levels should be standard TTL levels.
When both the address and data are
stable, a sequence of a 1 msec, TTL lowlevel pulse is applied to the PGliJI pin
and after that additional pulse is applied
to the PG1ii1 pin to accomplish the programming.
Procedure of Quick Pro TM (Refer to the
attached flow chart.)
1) Input the start address (Address=G)
2) SettheV cc =6V and Vpp=21V
3) I nput data.
4) Compare the input data with FF.

1111111111111111111111111111111111111111111111111

FUJITSU

MBM 27Cl28-2O
MBM 27Cl28-25

1111111111111111111111111111111111111111111111111

PROGRAMMING/ERASING INFORMATION (continued)

5)

6)

7)
8)

9)

10)

11)

12)

If data are FF, go to the step 11).
If not, proceed the next step.
Clear the counter (X +-0).
Apply ONE programming pulse to
PGM pin (tpw = lms Typ.).
Inclement the counter (X+-X+l).
Compare the counter value with 20.
If X=20, go to the step 10). If
X<20, proceed the next step.
Verify the data. If the programmed
data are the same as the input data,
proceed the next step. If not, go
back to the step 6).
Apply the additional programming
pulse to the PGM pin (1 ms x X or
Xms xl).
Compare the address with the end
-address. If the programmed address
is the end address, proceed the next
step. If not, go back to the step 3)
for next address (G+-G+l).
Verify the data. If the programmed
data are not the same as the input

data, the part is failed. If the pro·
grammed data the same as the input
data, programming is at an end.
All that is required is that initial 1 msec
program pulse and additional program
pulse (21 msec Max.) be applied at each
address to be programmed. It is neces·
sary that one program pulse width does
not exceed 21 msec. Therefore, apply·
ing a DC level to the PGM input is pro·
hibited when programming.

ERASURE
In order to clear all locations of their
programmed contents, it is necessary to
expose the MBM 27C128 to an ultra·
violet light source. A dosage of 15 W·
seconds/cm 2 is required to completely
erase an MBM 27C128. This dosage can
be obtained by exposure to an ultra·

violet lamp (wavelength of 2537 Angstroms U\)) with intensity of 12000pWI
cm 2 for 15 to 20 minutes. The
MBM 27C128 should be about one inch
from the source and all filters should be
removed from the UV Iight source prior
to erasure.
It is important to note that the
MBM 27C128 and similar devices, will
erase with light sources having wavelengths shorter than 4000A. Although
erasure time will be much longer than
with UV source at 2537 A, nevertheless
the exposure to fluorescent light and
sunlight will eventually erase the
MBM 27C128, and exposure to them
should be prevented to realize maximum system reliability. If used in such
an environment, the package windows
should be covered by an opaque label or
substance.

PROGRAMMING WAVEFORM
ADDRESS

V,...V'L-

--

")
'AS

VIH,VOH -

DATA

IAH

-I

V'LiVOL -

VppVee

HIGH-Z

DATA IN STABLE
lOS

Vpp

c-

ADDRESS N

DATA OUT
VALID

~

~

IDH

---.J
IVS

1--- -----CE

V 1H V 1L -

~
teES

PGM

j

VIH-

V 1L -

IpW

DE

-I

tOES

I

V'H

1

V 1L -

6-29

)

MBM 27C128-20
MBM 27C128-25

111111111111111111111111111111111111111111I111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

1. Standard Programming
DC CHARACTERISTICS
(TA = 25±5°C, V;~ = 5V±5%, V;~ = 21 ±0.5V)
Parameter

Symbol

Min

Typ

Max

Unit

I nput Leakage Current
(V IN = 5.25V/O,45V)

ILl

10

IJ.A

Vpp Supply Current During
Programming Pulse
(CE = PGM = V IL )

Ipp

30

mA

Vee Supply Current

lee

30

mA

Input Low Level

V IL

-0.1

0.8

V

Input High Level

V IH

2.0

V ee + 0.3

V

Output Low Voltage During Verify
(lOL =2.1mA)

VOL

0.45

V

Output High Voltage During Verify
(lOH = -400IJ.A)

V OH

Note:

*1
*2

2.4

V

Vee must be applied either coincidently or before Vpp and removed either coincidently or, after Vpp .
V pp must not be greater than 22 volts including overshoot. Permanent device damage may occur if the device is
taken out or put into socket remaining Vpp = 21 volts. Also, during CE=PGM = V IL , Vpp must not be switched
from 5 to 21 volts or vise-versa.

AC CHARACTERISTICS
(T A = 25±5°C, Vee = 5V±5%, Vpp = 21±0.5V)
Typ

Symbol

Min

Address Setup Time

tAs

2

IJ.s

Chip Enable Setup Time

teEs

2

IJ.S

Output Enable Setup Time

tOES

2

IJ.S
IJ.S

Parameter

Data Setup Time

Max

Unit

tos

2

V pp Setup Time.

tvs

2

IJ.S

Address Hold Time

tAH

0

IJ.S

Data Hold Time

tOH

2

IJ.S

Output Enable to Output Float Delay

tOF

0

Data Valid from Output Enable

toE

PGM Pulse Width

tpw

45

6-30

50

130

ns

150

ns

55

ms

1111111111111111111111111111111111111111111111111

FUJITSU

MBM 27C128-2O
MBM 27C128-25

1111111111111111111111111111111111111111111111111

PROGRAMMING/ERASING INFORMATION (continued)
2. Quick Programming
DC CHARACTERISTICS
(T A: 25±5°C, Vee": 6V±0.25V, V pp' 2 =21V±0.5V
Parameter

Symbol

Min

Typ

Max

Unit

Input Leakage Current
(V'N : 6.25V/0.45Vl

ILl

10

/1 A

V pp Supply Current During Programming
Pulse (CE = PGM: V,d

Ipp

30

mA

Vee Supply Current

Icc

30

mA

Input Low Level

V 1L

-0.1

0.8

V

2.0

Input High Level

V 1H

Output Low Voltage During Verfify
(lOL: 2.1mAl

VOL

Output High Voltage During Verify
(l oH : -400/1Al

V OH

Vee+ 0.3
0.45

V
V
V

2.4

Note: • 1 Vee must be applied either coincidently or before V pp and removed either concidently or after V pp .
• 2 V pp must not be greater than 22 volts including overshoot. Permanent device damage may occur if the device is
taken out or put into socket remaining V pp : 21 volts. Also, during CE: PGM : V 1L , V pp must not be switched
from 6 to 21 volts or vise·versa.
AC CHARACTERISTICS
(T A: 25±5°C, Vee = 6V±0.25V, V pp : 21V±0.5Vl
Parameter

Symbol

Min

Typ

Max

Unit

Address Setup Time

t AS

2

/15

Chip Enable Setup Time

tCES

2

/15

Output Enable Setup Time

tOES'

2

/15

Data Setup Time

tos

2

/15

V pp Setup Time

tvs

2

/15

Address Hold Time

tAH

0

/15

Data Hold Time

tOH

2

/15

Output Enable to Output Float Delay

tOF

Data Valid from Output Enable

tOE

PGM Pulse Width

tpw

.

0

0.95

• tOH + tOES ~ 50/15

6·31

1

130

ns

150

ns

1.05

ms

MBM 27Cl28-20
MBM 27C128-25 FUJITSU

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

PROGRAMMING FLOW CHART FOR Quick Pro™

Vee = 6ViO.25V
Vpp = 21V±O.5V

Tpw = 1ms±50J..l.s
(*= Xms±5%)

G: START ADDRESS
N: STDP ADDRESS
X: COUNTER VALUE
MAXIMUM 42ms/BYTE
MINIMUM 1.9ms/BYTE

FAIL

Quick Pro ™ is a trademark of FUJITSU LIMITED

6-32

1111111111111111111111111111111111111111111111111

FUJITSU

MBM 27C128-20
MBM 27C128-25

1111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
28-LEAD CERAMIC (CERDIP WITH TRANSPARENT LID) DUAL IN-LINE PACKAGE
(CASE No.: DIP-28C-C01)

I

R .02510.64)
REF

.570114.48)
.595115.11 )
.600115.24)

1""1.W=-=W:r--.::-W-'-'-W--'-'=-'-=C:;'-.4-':-:""1-':3';=.4--'5~=-=r--.:-W'--':W--'-'W=-r-Wr'1

J

'6251r:u~~--+-_--,-

1.500138.10)

--j

j.10012.54)MAX

:

:

~
23015.84)MAX

0 H D ~t~ I,qp DH"H ;=: H 11~
~.12013.05)
H

~

.09012.29)
.11012.79)

-

U

.04211.06)
.06211.58)

~

~.15013.81)

u
.03210.81)
TYP

.02010. 51)
.05011. 27)

1.300133.02)REF
~

6-33

.01310.33)
.02310.58)

Dimensions in

inches and (millimeters)

MBM 27Cl28-20 1IIIIIIIIImllllllllllllllllllllllllllll~II~~111
MBM 27Cl28-25 FUJITSU

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~I

PACKAGE DIMENSIONS
32-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No. : LCC-32C-A01)

.36019.14)TYP
PIN NO.1
INDEX

.015(o.38ITYP

fr

.545(13.84)
.560(14.221

l

0400110.16)
TYP

R.008(0.20)TYP
(32PLCS)
.025(0.64) TYP

.460(11.68)
TYP

L

!
.04011.02)TYP

0445(11.301
A60( 11.681

I I 13PLCS)
1--1-. 13013.30)MAX

.30017.62)TYP

Dimensions in
inches (millimeters)

*Shape of Pin index: Subject to change without notice

6·34

FUJITSU

MOS Memories
•

MBM27C256·25, MBM27C256·30
CMOS 32,768 x 8-Bit UV Erasable
and Electrically Programmable
Read Only Memory

Description
The Fujitsu MBM27C256 is a high speed 262,144-bits complementary MOS erasable and electrically reprogrammable read only
memory (EPROM). It is especially well su~ed for application where
rapid tum-around and/or bit pattern experimentation, and low-power
consumption are important.
A 2B-pin dual-in line package with a transparent lid and 32-pad
Leadless Chip Carrier (LCC) are used to package the MBM27C256.
The transparent lid allows the user to expose the device to ultraviolet light in order to erase the memory bit pattern previously programmed. At the completion of erasure, a new pattern can then be
written into the memory.

' ;;<"'~'-;.p ...
I/O'~'
7
"';-

If-

i!:u

DII

-

....21C. CO

r..••"

The MBM27C256 is fabricated using CMOS double polysilicon
gate technology with single transistor stacked gate cells. It is organized as 32,768 words by B-bits for use in microprocessor applications. Single + 5V operation greatly facilitates its use in systems.

•

~:I!o.. o'#f.'
~I~

I/C::::
f-

• CMOS Po_r Consumption:
550 ",W max. (Standby)
40 mW/MHz(Actlve)
• 32.768 words by 8-blts organization, fully decoded
• Simple programming
requirements
• Single location
programming
• High speed programming
algorithm (typically two
1 ms pulses)
• No clock required (fully
static operation)

• Single +5V supply, ±10%
• TTL compatible inputs and
outputs
• 3-state output with
OR-tie capabililL
• Output Enable (OE) pin for
simplified memory
expansion
• Fast Access Time:
MBM27C256-25 250 ns max.
MBM27C256-30 300 ns max.
• Single +5V operation
• Standard 28-pln DIP
packege/32-pad LCC

6-35

ff-

~/O~ --

~~
~
LC c.

.

~:u .41 ~t .

-

-

MBM27C256·25
MBM27C256·30

MBM27C256 Block Diagram
and Pin Asslgnmants

o.

0,

OE
E

Yo

COLUMN
GATING

AD

At.

V..
512x512
CELL MATRIX

Xo

At.
A,.

I

~

Vpp

A,.

A,

At.

As

A.

A.

Al1

A.

OE

A,

A,.

A,

E

Ao

Os

0,

0,

0,

O.

0.

0,

GND

O.

Xs"
Vpp

A,.

A"
A,

Au Vpp Vee
NC A14 Au

A,
GND

Vee

Absolute Maximum Ratings
(See Note)

Paramatar

Symbol

Value

Unit

Temperature under bias

T BIAS

-25 to +85

Storage temperature

TSTG

-65 to +125

'C
'C

Inputs/outputs with respect to GND

VIN,VOUT

-0.610 +7

V

VAg

-0.6 to + 13.5

V

Vpp with respect 10 GND

Vpp

-0.6 to +22

V

Vee with respect to GND

Vee

-0.610 +7

V

Vollage on

As wilh respect 10 GND

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may effect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. It is
advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high Impedance
circuit.

FUJITSU
6·36

MBM27C256·25
MBM27C256·30

Functions and
Pin Connections

Function
(Pin No.1

Data 1/0
(11-13,
15-191

Address Input

(2-tO, 21,
Mode

23-271

E

OE
(221

(201

Vpp
(11

Vee
(281

Read

AIN

OUT

VIL

VIL

Vee

Vee

GND

Output disable

AIN

High Z

VIL

VIH

Vee

Vee

GND

Stand by

Don't care

HighZ

VIH

Don't care

Vee

Vee

GND

Program

AIN

IN

VIL

V IH

Vee

Vpp

GND

Program verify

AIN

OUT

VIL

V IL

Vee

Vpp

GND

Program inhibit

Don't care

High Z

VIH

Don't care

Vee

Vpp

GND

Operating
Temperature

Recommended Operating
Conditions
(Referenced to GND)

GND
(141

Parameter

Symbol

Min

Typ

Max

Unit

Vee supply voltage'l

Vee

4.5

5.0

5.5

V

Vpp supply voltage

Vpp

Vee - 0.6

Vee + 0.6

V

Input high voltage

VIH

2.0

Vee +0.3

V

Input low voltage

VIL

-0.1

0.8

V

Nota: *1

OOG to +70oG

Vee must be applied either before or coincident with Vpp and removed either after or coincident with Vpp.

Capacitance
(TA

=

25°G, f

=

1 MHz)

Typ

Max

Unit

Input capacitance (VIN

Parameter

GIN

Symbol

4

6

pF

Output capacitance

GOUT

8

12

pF

= OV)
(VOUT = OV)

Min

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Input load current (VIN

=

5.5V)

Output leakage current (VOUT

= 5.5V)

V pp supply current
Vee standby current (E
V~e

(E

=

=

VIH)

=

Typ

Max

Unit

10

/LA

ILO

10

/LA

Ipp

100

=

0 mAl

Vld

= 4 MHz, lOUT = 0 mAl
Output low voltage (loL = 2.1 mAl
Output high voltage (loH = -400,.A)
Output high voltage (lOH = -100 /LA)
Vee operation current (f

6-37

/LA
mA

ISBl

standby current
Vee -0.3V to Vee +0.3V, lOUT

Vee active current (E

Min

III

ISB2

100

/LA

leel

30

mA

leC2

30

mA

VOL

0.45

V

V OH1

2.4

V

V OH2

Vee - 0.7

V

MBM.7C2S.·25
MBM27C2S.·30

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

MBM27C256-25
Min
Max

MBM27C258030
Min
Max

Parameter

Symbol

Address access time .,
(E = DE = V1d

tACC

250

300

ns

tE

250

300

ns

toE

100

120

ns

E to output valid (OE

= V1d

OE to output valid
(E= V1d"

DE,

E high to output floal"2

Address to output hold

tDF

0

tOH

0

60

Unit

105

0

ns

0

ns

Notes: *1 DE may be delayed up to lAce-toE after the following edge of E without impact on lACe*2 tDF is specified from (5E, E, whichever occurs first. Output float is defined as the point where data is a no longer driven.

Operation Timing Diagram

)!

ADDRESS

K

ADDRESS
VALID

I

"
"

~

IE

c;::

IOH

tAce

OUTPUT

VOH
VOL

HIGH·Z

////.

'"""""'\'

VAUDOUTPUT

."\:
f/

"'"

HIGH-Z

AC Test Conditions
(Including programming)

Input Pulse Levels: ................................. O.BV to 2.2V
Input Rise and Fall Time: ................................ ,,;;20 ns
Timing Measurement Reference Levels: .... 1.0V and 2.0V for inputs
O.BV and 2.0V for outputs
Output Load: ....................... 1 TTL gate and CL = 100 pF

PU.JITSU

6·38

~
I

MBM27C256·25
MBM27C256·30

Programming/Erasing
Information

Memory Cell Description
The MBM27C2S6 is fabricated
using a single-transistor stacked
gate cell construction, implemented via double-layer polysilicon technology. The individual
cells consist of a bottom floating
gate and a top select gate as
shown in Memory Cell diagram.
The top gate is connected to the
row decoder, while the floating
gate is used for charge storage.
The cell is programmed by the
injection of high energy electrons
through the oxide and onto the
floating gate. The presence of
the charge on the floating gate
causes a shift in the cell threshold as shown in Memory Cell
Threshold Shift diagram. In the
initial state, the cell has a low
threshold (VTH1 ) which will enable the transistor to be turned on
when the cell is selected (via the
top select gate). Programming
shifts the threshold to a higher
level (VTHO) , thus preventing the
cell transistor from turning on
when selected. The status of the
cell (Le., whether programmed or
not) can be determined by examining its state at the sense
threshold (VTHS) , as indicated by
the dotted line as shown in Memory Cell Threshold Shift diagram.

9. Verify the programmed data.
" the programmed data are
the same as the input data,
proceed to the next step. "
not, go back to step 6.

lowed by an additional pulse to
the EO pin to accomplish the
programming.
Procedure of Quick Pro™ (Refer
to the attached flow chart.)

10. Apply the additional programming pulse to the E pin
(1 ms x X or X ms x 1).

1. Input the start address (start
address = G).

11. Compare the address with
the end address. "the programed address is the end
address, proceed to the next
step. If not, proceed from
step 3 for next address
(GG + 1).

2. Set the Vee = 6V and
Vpp = 21V.

3. Input data.
4. Compare the input data with
FF. If the data are FF, go to
step 11. If not, proceed to
the next step.

12. Verify all the data. "the programmed data is not the
same as the input data, the
part failed. " it is, the program is completed.

5. Clear the counter (X = 0).
6. Apply ONE programming
pulse to the EO pin
(tpw = 1 ms typ.).

A continuous TTL low input
should not be applied to the E
pin during the program mode
(Vpp = 21V, Vee = 6Vand
OE = V1H ). Because it is required
that one programming pulse
width does not exceed 21 msec
at each address.

7. Increment the counter
(X =X + 1).
8. Compare the number of
counter value with 20. If
X = 20, go to step 10. "
X < 20, proceed to the next
step.

Memory Cell

_ _- - DRAIN

Upon delivery from Fujitsu, or

SELECT GATE

~

after each erasure (see Erasure
section), the MBM27C256 has all
262,144-bits in the "1", or high,
state. "O's" are loaded into the
MBM27C2S6 through the procedure of programming.
The MBM27C256 is programmed
with a fast programming algorithm designed by Fujitsu called
Quick ProTM. The programming
mode is entered when +21V and
+6V are applied to the Vpp pin_
and ~ pin respectively, and E
and OE are at V1H. A 0.1 p.F capacitor between Vpp and GND is
needed to prevent excessive
voltage transients, which could
damage the device. The address
to be programmed is applied to
the proper address pins. The
8-bit pattern are placed on the
respective output pins. The voltage levels should be standard
TTL levels. When both the address and data are stable, a sequence of single TTL low-level
pulse is applied to the E pin fol-

II

.!._L_-----

FLOATING GATE
SOURCE

Memory Cell Threshold Shift

6-39

NOT PROGRAMMED

PROGRAMMED

"I"

"0"

VTH1

(NOT PROGRAMMED)

VYHS

VTHO

(SENSE THRESHOLD) (PROGRAMMED)
SELECT GATE VOLTAGE (V)

MBM27C256·25
MBM27C256·30

Programming/Erasing
Information
(Continued)

Erasure

/LW/cm2) for 15 to 20 minutes.
The MBM27C256 should be
about one inch from the source
and all filters should be removed
from the UV light source prior to
erasure.

In order to clear all locations of
their programmed contents, it is
necessary to expose the
MBM27C256 to an ultraviolet
light source. A dosage of 15Wseconds/cm2 is required to completely erase an MBM27C256.
This dosage can be obtained by
exposure to an ultraviolet lamp
(wavelength of 2537 Angstroms
(A) with intensity of 12,000

It is important to note that the
MBM27C256 and similar devices,
will erase with light sources having wavelengths shorter than

4000 A. Although erasure times
will be much longer than with UV
sources at 2537 A, nevertheless,
the exposure to fluorescent light
and sunlight will eventually erase
the MBM27C256, and such exposure should be prevented to
realize maximum system reliability. If used in such an environment, the package windows
should be covered by an opaque
label or substance.

AC Characteristics
(TA = 25 ± 5°C,
Vee = 6V ± 0.25V,
Vpp = 21V ± 0.5V)

Parameter

Symbol

Min

Address setup time

tAS

2

/LS

Chip enable setup time

Ices

2

/Ls

Output enable setup time

tOES

2

/Ls

Data setup time

tos

2

/LS

Vpp setup time

tvs

2

/LS

Address hold time

tAH

2

/LS

Output enable hold time

tOEH

2

/Ls

Data hold time

tOH

2

/Ls

Output enable recovery time

tOR

2

/LS

Chip enable to data valid

tov

Output disable to output float delay

tOF

Typ

Max

Unit

/LS
105

ns

Programming pulse width

tpw

0.95

1.05

ms

Additional programming pulse width

tAPW

0.95

21

ms

FUJITSU
6-40

MBM27C256·25
MBM27C256·30

Programmlng/
Erasing Information
(Continued)

DC Characteristics
(TA = 25 ± 5°C,
Vee = 6V ±0.25V,
Vpp = 21V ± 0.5V)
Parameter

Symbol

Typ

Min

Input leakage current
(VIN = 5.25V/0.45V)
Vpp supply current during
programming pulse (E = Vld
Vee supply current

Max

Unit

10

,..A

Ipp

40

mA

Ice

30

mA

Input low level

-0.1

0.8

V

Input high level

2.0

Vee + 0.3

V

0.45

V

Output low voltage during verify
= 2.1 mAl

(lOL

Output nigh voltage during verify
(lOH = -400 p.A)

2.4

V

Notes: Vee must be applied either coincidently or before Vpp and removed either coincidently or after Vpp.
Vpp must not be greater than 21.5V inctu~lng overshoot. Permanent device damage may occur if the device is taken out or put into
socket with Vpp = 21 volts. Also, during E = VIL. Vpp must not be switched from 5 volts to 21 volts or viS9 versa.
M

Programming Waveform

ADDRESS

VIH
VIL
tDY

DATA

v••

v••

vee

6·41

tDF

MBM27C258·25
MBM27C258·30

Programmlng/Eraalng
Information
(Continued)

Quick Program Flow Chart

YES

APPLY 1 PROG. PULSE (lMS)

YES

NG

APPLY AoomONAL PROG. PULSE
1ms xX OR Xms· x 1

Tpw

= 1ms:t 50~8

('Xms,5%)

G: START ADORESS
N: STOP ADDRESS
X: COUNTER VALUE
MAX1MUM 42MS/BYTE
MINIMUM 1.9ms/BYTE

FUJITSU

6-42

"">---..:.N=G----j~I(

FAIL)

MBM27C256.25
MBM27C256·30

Characteristics Curves
(Dotted curves are for "HA"
version.)

= 5.0Y, TA = 25°C

Current Waveform Y ce

ADDRESS

E

-

60

1
~

,...

I ,
L

, Il. \.

40
20

J

o

" ' ....

~

~

4

.....

,.-..:::

50 ns/Dlvlslon

Standby Current
vs. Supply Yoltage

Standby Current
vs. Ambient Temperature

r=vcc

= 2S'C I

1A

t-

Z
w
0:
0:

"u>

V

1.2

'z"

1.0

0

W
0.8
:J
N

""

""0:

::i
0
Z

0.6

J

"

./

~100
0:

13

""

>

~

10

;!'

V
"

II>

J

...

4.0

5.0

L

1.2

OtOZ

NO:

./'

::l§

:!u
0:
0

0.8

z

I-""'

./'

V

---

./

V

Ii

!J

"J"~

"

100

~

Z
0

1.0

~

Vee
SV
TA = 2S'C
VIN = Vcc/Vss

1A

WW

~

Operation Current
va. Frequency
10

w

/J

"

50

f-i~~:~

0:

,

TA. AMBIENT TEMPERATURE ('e)

Operating Current
vs. Supply Yoltage

!;i

V

6.0

vee. SUPPLY VOLTAGE (V)

..

,I
y

E = Yee

!50:

./

0

~

Vee = 5V
DARK CONDInON

/
./

V
;7

V

/

""

,.-'

0.6

4.0

5.0

6.0

Vee. SUPPLY VOLTAGE (V)

6-43

0.1

t
f. FREQUENCY (MHz)

10

MBM27C256.25
MBM27C258·30

Characteristics Curves
(Continued)
(Dolled curves are for "HA"
version.)

Address Access Time
vs. Supply Voltage

Address Access Time
vs. Ambl_t Temperature

T~=2S0C-

,...

1.4

m

II:

c

!i!~

",,' ...

1.2

IS~

c

.............

~~

1.2

:III>
.. W

1.0

fill"
Nil>
~

:l U

z

1.4

'~~

0.8

]

:l U
II: U

0"

z

0.8

0.6

5.0

vee.

TA. AMBIENT TEMPERATURE (0C)

OE to Output Delay
vs. Ambient Temperature

Vee = 5V

Vee = SV

1.'

~
c .... 1.2

-..

1W:C

9~

1.0

~I"'"

-~

1A

..--

~

l:!l~

.,..~ ~

~:!l

.. "
~S

1.2
~

:I ..

~

1.0

~o
oil

0.8

E

~

~

~

0.8

0.6

0.6

50
TA. AMBIENT TEMPERATURE (0C)

FUJITSU

100

50

6.0

SUPPLY VOLTAGE (V)

E to Output Delay
vs. Ambient Temperature

~

~

U

4.0

ISS
zo

,..--

~~.

~

u
:f

0.6

:I!;

..
r-- --

II:

""'-

fai=
~Ia
.. w 1.0

Vee = 5V
II>
II>
W

100

50
TA. AMBIENT TEMPERATURE rC)

100

MBM27C258-25
MBM27C258-30

Characteristics Curves
(Continued
(Dotted curves are for "HAn
version.)

OE High to Output Float
Ambient Temperature

Output Source Current
vs. Output High Voltage

VS.

~v

t-Vee =
TA = 25"C

Vee = SV

-20

1.4

"

!2

WC
I""
og

co.

~5

I§

00

1.2

.--1.0

-.........

~---

"-

0.8

~

....

-I--

z ...

....

~

0.6

.

..-.......:
.

so

3.0

100

Output Sink Current
Output Low Voltage
Vee = 5V
TA = 25'C

Vee =15V

L

1.6

v,.....

20

'"'"

/.,
./

"

./

1.4

511=

1.2

~!Il

ig

V

~C 1.0
z
u

~

0.4

= 25°C

/

1/.: ...
~

I'

. -'

~

V

U

/
0.2

W
II:
C

TA

~~

/

a

5.0

Address Access Time
vs. Load Capacitance

VS.

aV

4.0

VaH. OUTPUT HIGH VOLTAGE (V)

TA. AMBIENT TEMPERATURE ('C)

V

~

0.6

0.6

1.0

VOL. OUTPUT LOW VOLTAGE (V)

6-45

1.2

0.8

200

400

CL. LOAD CAPACITANCE (pF)

600

.....27C258.2S
.....27C2S8·30

Packa. . Dimensions
Dimensions in inches
(milfimeters)

28·Lead Ceramic (CERDIP with Transparent Lid)
Dual In·Line Package
(Case No.: DIP.28CoC01)

R .025(0.64)
REF

"

I~~=-=--=-=-=,J
w_=__w_l:=:1~1 ______
o.jl

If-o....
: ___

~

~

q

- I..

.100(2.54)MAX

+

I-' ~

H H H

r

l.J.:
HHH~ ~

23O(5.84)MAX
.120(3.05)

~ .150(3.81)

.090(2.29)
.110(2.79)

J ..... ~
.082(1.58)

....

0.32(0.81)
TYP

.020(0.51)
.050(1.27)

1.3OO(33.02)REF
.013(0.33)
.023(0.58)

32·Pad Ceramic (Metal Seal) Leadless Chip Carrier
(Case No.: LCCo32C·A01)
.360(9.14)TYP
PINHO. 1
INDEX

.015(0.38)TYP

LL

.445(11.30)
.460(11.68)

.130(3.30)MAX

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE.

6-46

Advanced Information
•

MBM27C256A-20, MBM27C256A-25
CMOS UV Erasable 262,144-Bit
Read Only Memory

D.scrlptlon
The Fujitsu MBM27C256A is a high speed 262,144-bit complementary MOS erasable and electrically reprogram mabie read only
memory (EPROM). It is especially well suited for application where
rapid turn-around and/or bit pattern experimentation, and low-power
consumption are important.
A 28-pin dual-in line package with a transparent lid and 32-pad
Leadless Chip Carrier (LCe) are used to package the
MBM27C256A. The transparent lid allows the user to expose the
device to ultra-violet light in order to erase the memory bit pattern
previously programmed. At the completion of erasure, a new pattern can then be written into the memory.
The MBM27C256A is fabricated using CMOS double polysilicon
gate technology with single transistor stacked gate cells. It is organized as 32,768 words by 8-bits for use in microprocessor
applications.

F••tur.s
• CMOS power consumption
Stsndby: 550,...W max.
Active: 41 mW/MHz
• 32,768 words x B-blts organlzatlon, fully decoded
• Program voltage: 12.5V
• Programmable utilizing the
Quick Pro™ algorithm
• Programs with 1 ms pulses
• No clocks required (fully static
operation)
• Fast access lime:
200 ns max. (MBM27C256A-20)
250 ns max. (MBM27C256A-25)

• TIL compatible Inputs/outputs
• Three-atste output with OR-tie
capablllty_
• Output Enable (OE) pin for
simplified memory expansion
• Single +5V supply; +10%
tolerance
• Standard 2B-pln DIP package
and 32-pad LCC

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields. However. it Is advised

that normal precautions be taken to
avoid appIicatton of any voltage
higher than maximum rated volt·
ages to thts high Impedance circuit.

Quick ProTM is a trademark of FUJITSU
LlMITEO

6-47

FUJITSU

MBM27C256A·20
MBM27C256A·2S

MBM27C2S6A Block
Diagram and Pin
Assignments

o.

0,

Yo

AO
A,

COLUMN
GATING

Ya

512x512

Xo

A,

CELL MATRIX

Vpp

Vee

A12

A,.

A,

A13

A,

A.

As

A,

A.

A"

A,

DE

A,

AlO

A,

E

Ao

0,

0,

0,

0,

0,

0,

Os

GNO

O.

"",

A,.

A'2 Vpp Vee
A, \
NC Al4 Al3
,4; 3' 2' 1 '32'31'30:

I

Vpp

GND

Vee

'- _. _L

I

_~_:_4_

L_,

H8~'" I~
At 1~~

~2~ Ato
123 E
~~2 08
~2_1 07

Ao 11'

NC

t~~

0, 1~~
:-,4:15:-,6.,7i1-8-;'-9·io~

o,o,/Ncloso,
GND

Absolute Maximum Ratings
(See Note)

04

==;..._________

...
Riiiaiiit'iii·n;;,;g_.._ _ _ _ _ _ _ _ _ _ _ _.....S.y'"m=b,;,o;.1_ _ _ _ _Value

Unit

Temperature under bias

TBIAS

-25 to +85

°C

Storage temperature

TSTG

-65 to +125

°C

All inputs/outputs voltage with
respect to GND

-0.6 to +7

V

Voltage on A9 with respect to GND

-0.6 to +13.5

V

Vpp voltage with respect to GND

Vpp

-0.6 to +14

V

Supply voltage with respect to GND

Vee

-0.6 to +7

V

Note: Permanent device damage may occur jf ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

FUJITSU
6·48

MBM27C2HA·20
MBM27C258A·25

Functions and Pin
Connection.

Data I/O

Addre•• Input
(2 - 10,21,
23 1 25 - 271

(11 - 13, CE
15 - 191 (201

Read

A'N

OUT

Output
disable

A'N

Standby

DE
(221

Vee
(281

Vpp
(11

GND As
(141 (241

V,l

V,L

+5V

+5V

GND

A'N

High-Z

V,l

V,H

+5V

+5V

GND

A'N

Don't care

High-Z

V,H

Don't care

+5V

+5V

GND

Don't care

Program

A'N

IN

V,l

V,H

+6V

+12.5V

GND

A'N

Program
verify

A'N

OUT

Don't care

V,l

+6V

+12.5V

GND

A'N

Program
inhibit

Don't care

High-Z

V,H

V,H

+6V

+12.5V

GND

Don't care

Code

Vu..

V,l

+5V

+5V

GND

+12V

Electronic
Signature A'N

Recommended Operating
Condition.
(Referenced to GND)

Parameter

Symbol

Min

Typ

Max

Unit

Vee supply voltage"

Vee

4.5

5.0

5.5

V
V

Vpp supply voltage

Vpp

Vee - 0.6

Vee + 0.6

Input high voltage

V,H

2.0

Vee + 0.3

V

Input low voltage

V,l

-0.1

0.8

V

Operating temperature

TA

0

70

·C

Note: ·Vee must be applied either before or coincident with Vpp and removed either after or coincident with Vpp_

DC Characteristic.
(Recommended operating
conditions unless otherwise
noted)

Parameter
Input load current (V'N

Symbol

=

Output leakage current (VOUT
Vpp supply current (Vpp
Vee standby current (E

Unit
/loA

'l

10

/loA

± 0.6V)

Ipp

100

/loA
rnA

1581

= 0 rnA)
Vcc active current (E = V,Ll

Vcc operation current
(f = 4 MHz, lOUT = 0 rnA)

=

Max

Ilo

Vlfc standby current
( = Vcc ± 0.3V, lOUT

Output low voltage (IOl

Typ

5.5V)

=

= Vee
= V,H)

Min

10

5.5V)

2.1 rnA)

1582

100

/loA

lec1

30

rnA

Icc2

30

rnA

0.45

V

Val

Output high voltage (IOH = -400 /loA)

VOH1

2.4

V

Output high voltage (IOH = -100 /loA)

VOH2

Vcc - 0.7

V

6-49

M8M27C258A-20
M8M27C2S6A-2S

AC CII.r.ct.....tlc.
(Recommended operating
conditions unless otherwise
noted)

M8M27C256A-20
Min
Typ
M ••

M8M27C258A-2S
Min
Typ
M ••

P.r.meter

Symbol

Address access time-'
(E=OE=V,L>

t ACC

200

250

ns

tE

200

250

ns

tOE

75

100

ns

E to output delay (OE = V,L>
OE to output delay-' (E

=

V,L>

Address to output hold
Output enable high to output'2
float'2

Notes: "'1

tOH

0

tDF

0

Units

0

60

ns

0

ns

60

DE may be delayed up to lACe - toe after the failing edge of Ewithout impact on tAce-

*2 tOF is specified from

DE or E, whichever occurs first. Output float is defined as the point where data is no longer driven.

Operation Timing DI.gr.m

ADDRESS

V,H
V,L

E

V,H
V,L

)

It

I
OE

K

ADDRESS
VALID

IE

I

'"

toE

IOH

lAce

OUTPUT

AC Te.t Conditions
(Including Progr.mmlng)

:..

V,H
V,L

VOH

HIGH·Z

VOL

////,

"'-"<

0.45V to 2.4V
Input pulse levels:
.;;20 ns
Input rise and fall times:
Timing measurement reference levels: 1.0V and 2.0V for inputs
0.8V and 2.0V for outputs
Output load:
1 TTL gate and Cl = 100 pF

PU.JITSU
6-50

VALID OUTPUT

<'\:

,

HIGH·Z

f/. /

~
I

MBM27C256A·20
MBM27C256A·25

Programming/Erasing
Information

7) Compare the number (= X)
of applied programming
pulse with 25 and then verify
the programmed data. If programmed data is verified, go
to the neX1 step regardless
of X value. If X = 25 and
programmed data is not verified, the device fails. If X =
25 and programmed data is
not verified, go back to the
step 5).

Programming

Upon delivery from Fujitsu, or
after each erasure (see Erasure
section), the MBM27C256A has
all 262,144 bits in the "1': or hIgh
state. "O's" are loaded into the
MBM27C256A through the procedure of programming.
The MBM27C256A is programmed with a fast programming algorithm designed by
Fujitsu called Quick Pro TM. The
programming mode is entered
when + 12.5V and +6V are applied to Vpp and Vee respectively,
and E and OE are V,H. A O.lp.F
capacitor between Vpp and GND
is needed to prevent excessIve
voltage transients which could
damage the device. The address
to be programmed is applied to
the proper address pins. Eight bit
data patterns are placed on the
respective data output pins. The
voltage levels should be standard
TTL levels. When both the address and data are stable, a
1 ms programming pulse is applied to E and after that one additional pulse which is 3 times as
wide as previous pulse is applied
to E to accomplish the
programming.

8) Apply one additional wlQe
programming pulse to E
(3Xms).
9) Compare the address with
an end address (= N). If the
programmed address is the
end address, proceed to the
next step. If not, increment
the address (G +- G + 1)
and then go to the step 3)
for the neX1 address.
10) Set Vee = Vpp = 5V.
11) Verify the all programmed
data. If the verification succeeds, the programming
completes. If any programmed data is not the
same as original data, the
device fails.

Procedure of Quick Pro™ (Refer
to the attached flowchart.)
1) Set the start address (=G)
at the address pins.
2) Set '{ce = 6V, Vpp = 12.5V
and E = V,H.
3) Clear the programming pulse
counter (X +- 0).
4) Input data to respective pins.
5) Apply ONE programming _
pulse (tpw = 1 ms Typ.) to E.
6) Increment the counter
(X+-X+1).

This dosage can be obtained by
exposure to an ultraviolet lamp
(wavelength of 2537 Angstroms
(All with intensity of
12000p.W Icm 2 for 15 to 20
minutes.
The MBM27C256A should be
about one inch from the source
and all filters should be removed
from the UV light source prior to
erasure.
It is important to note that the
MBM27C256A and similar devices, will erase with light
sources having wavelengths
shorter than 4000A. Although
erasure time will be much longer
than with UV source at 2537A,
nevertheless the exposure to
fluorescent light and sunlight will
eventually erase the
MBM27C256A, and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment,
the package windows should be
covered by an opaque label or
substance.
Electronic Signature

A continuous TTL low level
should not apply to E input pin
during the program mode (Vpp =
12.5V, Vee = 6V and OE = V,H)
because it is required that one
programming pulse width does
not exceed 78.75 ms at each
address.

The MBM27C256A has electronic signature mode which is
intended for use by programming
equipment for the purpose of
automatically matching the device to be programmed with ~s
corresponding programming
algorithm.

Erasure

The electronic signature is activated when +12V is applied to
address Ag (pin 24) of the
MBM27C256A. Two identifier
bytes are read out from the outputs by toggling address line 1.0
(pin 10) from V,L to V,H • The address lines from A1 to A 13 must
be held at V,L to keep the electronic signature mode.

In order to clear all locations of
their programmed contents, it is
necessary to expose the
MBM27C256A to an ultraviolet
light source. A dosage of 15 Wseconds/cm 2 is required to completely erase an MBM27C256A.

01

Note: Ag = 12V ± O.SV
A1 - AS = A10 - A 13 = E

DefInition

= OE =

Vil'

6·51

o·

Manufacture

o

DevIce

MBM27C256A·20
MBM27C256A·25

Programming/Erasing
Information

Programming Waveform

(Continued)
PROGRAM

ADDRESS

VERIFY

ADDITIONAL PROGRAM

VOH
VOL

DATA

Vpp

V••
Vee

Vee

Vcc+ 1
Vee

VOH
VOL

VOH
VOL

DC Characteristics
(TA = 25 ± 5'C, VCC'1

= 6V ±
0.25V, Vpp '2 = 12.5V ± 0.3V)

~

Parameter

Symbol

Min

Typ

Input leakage current (V'N = 6.25V /0.45V)
Vpp supply current (E

= V,L, OE = V,H )

Vpp supply current (OE

=

V,L>

Vcc supply current

DON'T CARE

Max

Unit

10

/LA

50

rnA

5

rnA

30

rnA

Input low level

-0.1

0.8

V

Input high level

2.0

Vee

Icc

Output low voltage during verify
(lOL = 2.1 rnA)

0.45

Output high voltage during verify
(IOH = - 400 /LA)

2.4

+ 0.3

V
V
V

Not.. : *1 Vee must be applied either coincidently or before Vpp and removed either coincidently or after Vpp.

2 Vpp must nol be greater than 14 volts Including overshoot. Permanent device damage may occur If the device is taken out or put
into socket remaining Vpp = 12.5 volts, Also, during E = VIL' OE = VIH' Vpp must not be switched from Vee to Vpp volts or
vice versa.

FUJI'I'SU

6·52

MBM27C256A·20
MBM27C256A·25

AC Characteristics
(TA = 25 ± 5°C, Vcc = 6V ±
0.25V, Vpp = 12.5V ± 0.3V

Parameter

Symbol

Min

Address setup time

t AS

2

P.s

Output enable setup time

tOES

2

p.s

Chip enable setup time

t ES

2

p.s

Data setup time

tos

2

p's

Vpp setup time

t vps

2

p's

Vcc setup time

tvcs

2

p's

Address hold time

tAH

2

p's

Data hold time

tOH

2

p's

Chip enable hold time

tCEH

2

Output enables to output valid

tOE

Typ

Max

UnIt

p.s
120

ns

Output disable to output float delay

tOF

105

ns

Programming pulse width

tpw

0.95

1.05

ms

25

times

t APW

2.85

78.75

ms

Programming pulse number
Additional programming pulse width

ProgrammIng Flow Chart

Vee = 6V·0.25\1

Vpp

=

12.SV±G.3V

G: START ADDRESS
N: STOP ADDRESS
X: COUNTER VALUE
MAXIMUM 105msJBYTE
MINIMUM 3.8m./BYTE

6-53

MBM27C2S8A.20
MBM27C258A·25

Package Dlm_slons
Dimensions in inches
(millimeters)

28·Lead Ceramic (C.rdlp With Transparent Ud) Dual In·Une Package
(Ca. . No•• DIP.28C.C01)

rn

I

R .025(0.64)
REF

CJ

c::J

w

•

J

I

•090(2.29)

.110(2.79)

~----------~1~~~"~.02=)=R=EF~--------~~

32·Pad Ceramic (Me.al S.al) Leadless Chip Canie,
(Cese No•• LCCo32C.A01)
.36O(9.14)TYP
PIN NO. 1

O.15(O.38)TYP

INDEX

tShape of Pin Index: Subject to change without notice

6·54

FUJITSU

MOS Memories
•

MBM27C258A-20-W
MBM27C258A-25-W
CMOS 32,768 x 8-Bit UV Erasable
and Electrically Programmable
Read Only Memory

Description
The Fujitsu MBM27C256A-W is a high speed 262,144-bits UV
erasable and electrically reprogrammable read only memory
(EPROM) with CMOS technology. It is especially well suited for
applications where rapid turn-around and/or bit pattern experimentation, and low-power consumption are important.
A 28-pin dual-in line package with a transparent lid and 32-pad
Leadless Chip Carrier (LCC) are used to package the
MBM27C256A-W. The transparent lid allows the user to expose
the device to ultraviolet light in order to erase the memory bit
pattern previously programmed. At the completion of erasure, a
new pattern can Ihen be written into the memory.
The MBM27C256A-W is fabricaled using CMOS double polysilicon gale technology with single transislor slacked gale cells. II
is organized as 32,768 words by 8-bits for use in microprocessor
applications. Single + 5V operation greatly facilitates its use in
systems.

Ceramic Package
DIP-2SC-C01

Featu....
• Wide temperature range:
-55'C to +125'C
• CMOS Power Consumption:
550 ",W max. (Standby)
41 mW/MHz (Active)
• 32,768 words by II-blts organization, fully decoded
• Simple programming
requirements
• Single location programming
• High speed programming
algorithm (typically two
1 ms pulses)
• No clock required (fully
static operation)
• Programming voltage: 12.5V

• Single +5Vsupply, ±10%
• TTL compatible Inputs and
outputs
• 3-atate output with OR-tie
capability
• Output Enable (DE) pin fOr
simplified memory expansion
• Fast access time:
MBM27C258A-200W
200ns max.
MBM27C256A-25-W
250 ns max.
• Single + 5V operation
• Standard 28-pln DIP package/32-pad LCC

6-55

LeadleH Chip Carrier
LCC-32C·A01

MBM27C25eA-20-W
MBM27C258A-25-W

MBM27C256A Block
Diagram and Pin
Assignments

0"

0,

OE
E
Do

DT

v.

Ao
Ao

COLUMN
GATING

V..

Xo

Ao

512x512
CELL MATRIX

A,.

Vpp

Vee

A,.

A,.

AT

A,.

Ao

Ao

A.

Ao

Ao

A"

As

liE

As

A,.

A,

!

Ao

O.

0,

0.

0.

Os

Os

Os

GND

O.

XS11

I

VPI'

Vee

C256-4

I

A12 Vpp Vee

GND

AT

C256-3

NC

GND

A14 A13

O.
C256-5

Absoluta Maximum Ratings
(See Note)

Parameter

Symbol

Valua

Unit

Temperature under bias

TBIAS

-65 to +125

·C

Storage temperature

TSTG

-65 to +150

'C

Inputs/outputs with respect to GND

VIN. Your

-0.6 to +7

V

Voltage on A9 with respect to GND

VA9

-0.6 to +13.5

V

Vpp with respect to GND

Vpp

-0.6 to +14

V

Vee with respect to GND

Vee

-0.610 +7

V

Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the condltfons as detailed In the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields. It Is advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this high Impedance circuit.

FUJITSU
6-56

MBM27C258A·20·W
MBM27C258A.25.W

Functions and Pin
Connections

Function
(Pin No.)
Mode
Read

Data I/O

Addre.. lnput
(2-10,21,
Ae
23-27)
(24)

(11-13, I!
OE
15-19) (20) (22)

Vee Vpp

GND

(28) (1)

(14)

AIN

AIN

OUT

VIL

+5V

+5V

GND

HighZ

VIL

VIH

+5V

+5V

GND

VIH

GND

VIL

Output disable

AIN

AIN

Stand by

Don't care

Don't care HighZ

Don't care

+5V

+5V

Program

AIN

AIN

IN

VIL

VIH

+6V

+12.5V GND

Program verify

AIN

AIN

OUT

VIL

VIL

+6V

+ 12.5V GND

Program inhibit

Don't care

Don'teare

HighZ

VIH

Don't care

+6V

+ 12.5V GND

Electronic signature

AIN

+12V

Code

VIL

VIL

+5V

+5V

Recommended Operating
Conditions
(Referenced to GND)

Parameter

Symbol

Min

Typ

Max

Unit

Vee supply voltage (1)

Vee

4.5

5.0

5.5

V

Vpp supply voltage

Vpp

Vee- 0.6

Vcc+ 0.6

V

Input high voltage

VIH

2.0

Vcc+ 0.3

V

N_.

VIL

-0.1

O.B

V

Input low voltage

GND

Operating
Temperature

- 55'C to + 125'C

1. Vee must be applied either before or coincident with Vpp and removed either after or coincident with Vpp.

Capacitance
(TA

=

25'C, f

=

1 MHz)

Parameter
OV)

=

Output capacitance (VOUT

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Typ

Max

Unit

CIN

4

6

pF

COUT

B

12

pF

Symbol

=

Input capacitance (VIN

OV)

Parameter

Max

Unit

III

10

JoLA

ILO

10

JoLA

Ipp

100

Symbol

Input load current (VIN

=

5.5V)

=

Output leakage current (VOUT

5.5V)

Vpp supply current
Vee standby current (E

=

VIH)

=

Vee operation current (f
Output low voltage (IOL

=

0 mAl

VIL)

= 4 MHz, lOUT =
= 2.1 mAl

Output high voltage (IOH

= -

Output high voltage (IOH

=

Min

Typ

0 mAl

JoLA
mA

1881

Vee standby current
(10 = Vee-0.3Vto Vcc+0.3V,loUT
Vee active current (10

Min

1882

100

JoLA
mA

lee1

30

ICC2

30

mA

VOL

0.45

V

400 JoLA)

VOH1

2.4

V

-100 JoLA)

VOH2

Vee- 0.7

V

FUJITSU
6-57

MBM27C2S8A·20·W
MBM27C258A·25·W

AC Characterl.tlea
(Recommended operating
conditions unless otherwise
noted.)

MB1I!I27C258A.20
Parameter

Symbol

Address access time (t)
(E = OE = VII">

E to output valid (aE = VIl)
5E to output valid
(E= VII..>(t)
5E, E high to output float (2, 3)

!oF

Address to output hold (3)

!oH

MBM27C258A·25

Max

Min

toE

o
o

Mall

Unit

200

250

ns

200

250

ns

75

100

ns

60

ns

Min

o
o

60

ns

Noter.
t. OE may be delayed up to tACC·toE after the following edge of E without Impact on tACC'
2. toF Is specified from <5E. 'E. whichever occurs first. Output float Is defined as the point where data Is no longer driven.
3. Sampling, not 100% tested.

Operation Timing Diagram

ADDRESS

iii

v..
V,L

)!

K

ADDRESS
VAUD

V..

V,L

~

Ie
lIl!

v..
VL

c;;::

toto

lAce

OUTPUT

VOlt
VOL

HJGH..Z

////0

''''''<

VAUDDUTPUT

<"\.

HJGH..Z

'/. II
C256-6

AC Tnt Condition.
(Including programming)

Input Pulse Levels: ............................ 0.45V to 2.4V
Input Rise and Fall Time: ............................ ,;20 ns
Timing Measurement Reference Levels: 1.0V and 2.0V for inputs
0.8V and 2.0V for outputs
Output Load: ................... 1 TTL gate and CL = 100 pF

~
I
C256-7

FUJITSU
6-58

M.M27C2seA-2G-W
M.M27C2SeA-2S-W

Prognmmln.,.........
Informallon

MemolY Cell Ducrlptlon
The MBM27C256A-W is fabricated using a single-transistor
stacked gate cell construction,
implemented via double-layer
polysilicon technology. The individual cells consist of a bottom floating gate and a top
select gate as shown in Memory Cell diagram. The top gate
is connected to the row decoder, while the floating gate
is used for charge storage.
The cell is programmed by the
injection of high energy electrons through the oxide and
onto the floating gate. The
presence of the charge on the
floating gate causes a shift in
the cell threshold as shown in
Memory Cell Threshold Shift
diagram. In the initial state,
the cell has a low threshold
(VTH1) which will enable the
transistor to be turned on
when the cell is selected (via
the top select gate). Programming shifts the threshold to a
higher level (VTHO), thus preventing the cell transistor from
turning on when selected. The
status of the cell (i.e., whether
programmed or not) can be
determined by examining its
state at the sense threshold
(VTHsJ, as indicated by the
dotted line as shown in Memory Cell Threshold Shift diagram.
Upon delivery from Fujitsu, or
after each erasure (see Erasure section), the
MBM27C256A-W has all
262,144-bits in the "1", or
high, state. "O's" are loaded
into the MBM27C256A-W
through the procedure of programming.

vice. The address to be programmed is applied to the
proper address pins. The 8-bit
pattern is placed on the respective output pins. The voltage levels should be standard
TTL levels. When both the address and data are stable, a
sequence of single TTL lowlevel pulses are applied to the
E pin followed by an additional pulse to the E pin to accomplish the programming.

8)
9)

Procedure of Quick ProTM
(Refer to the attached flow
chart.)
1) Input the start address
(start address = G).
2) Set Vee = 6V, Vpp =
12.5V and E = VIH.
3) Clear the programming
pulse counter (X +- 0).
4) Input data to respective
pins.
5) Apply ONE programming
pulse (tpw = 1 ms Typ.)
to E.
6) Increment the counter
(X+-X+1).
7) Compare the number
(= X) of applied programming pulse with 25 and
then verify the pro-

10)
11)

grammed data. If the programmed data is verified,
go to the next step regardless of X value. If X
= 25 and programmed
data is not verified, the
device fails.
Apply one additional wide
programming pulse to E
(3Xms).
Compare the address
with an end address
(=N). If the programmed
address is the end address, proceed to the
next step. If not, increment the address
(G +- G+ 1) and then go
to the step 3) for the next
address.
Set Vee = Vpp = 5V.
Verify all the data. If the
programmed data is not
the same as the input
data, the part failed. If it
is the same, the program
is completed.

A continuous TTL low level
should not apply to CE input
pin during the program mode
!YeP = 12.5V, Vee = 6Vand
OE = VIH) because it is required that one programming
pulse width does not exceed
78.75 ms at each address.

MemolY Cell
......._---DRAIN

SELECT

GA~
I 711~-------

FLOATING GATE

L_---SOURCE

C256-8

MemolY Cell Threshold Shift

The MBM27C256A-W is programmed with a fast programming algorithm designed by
Fujitsu called Quick ProTM.
The programming mode is entered when + 12.5V and + 6V
are applied to the Vpp pin and
Vee pin respectively, and E
and C>E are at VIH. A 0.1 ",F
capacitor between Vpp and
GND is needed to prevent excessive voltage transients,
which could damage the de-

NOT PROGRAMMED
"1"

PROGRAMMED

"0··

PROGRAM

ERASE

V11t1

(NOT PROGRAMMED)

VlMS

VTHO

(SENSE THRESHOLD) (PROGRAMMEDI
SELECT GATE VOLTAGE (VI

Quick ProTM Is a trademark of Fulltsu Umlted.

FWlTStJ
6-59

C256-9

M.M27C256A-20-W
M.M27C256A-25-W

Programming/Erasing
Information (Continued)

Erasura

12,000 ".W/cm2:) for 15 to 20
minutes. The MBM27C256A-W
should be about one inch
from the source and all filters
should be removed from the
UV light source prior to
erasure.

In order to clear all locations
of their programmed contents,
it is necessary to expose the
MBM27C256A-W to an ultraviolet light source. A dosage of
15W-seconds/cm2 is required
to completely erase an
MBM27C256A-W. This dosage can be obtained by exposure to an ultraviolet lamp
(wavelenj;Jth of 2537 Angstroms (A) with intensity of

It is important to note that the
MBM27C256A-W and similar
devices, will erase with light
sources having wavelengths
shorter than 4000 A.. Although

erasure times will be much
longer than with UV sources
at 2537 A., nevertheless, the
exposure to fluorescent light
and sunlight will eventually
erase the MBM27C256A-W
and such exposure should be
prevented to realize maximum
system reliability. If used in
such an environment, the
package windows should be
covered by an opaque label or
substance.

AC CharactarllltlCII
(TA = 25'C ± 5'C,
Vee = 6V ± 0.25V,
Vpp = 12.5V ± 0.3V)
Symbol

Min

Address setup time

tAS

2

".S

Chip enable setup time

teES

2

".s

Output enable setup time

toES

2

".s

Data setup time

tos

2

".S

Vpp setup time

tvs

2

".S

Address hold time

tAH

2

".s

Output enable hold time (1)

toEH

2

".s

Data hold time

tOH

2

,.S

Output enable recovery time (1)

toR

2

".S

Chip enable to data valid

tov

Output disable to output float delay

tOF

Programming PUI69 width

tpw

Additional programming pulse width

tAPW

Programming pulse number

X

Paramater

Typ

Max

Unit

".s
105

ns

0.95

1.05

ms

2.85

78.75

ms

25

times

N_,
1. toEH + toR" 50,.s.

Electronic Slgnatura

responding programming algorithm.

The MBM27C256A-W has
electronic signature mode
which is intended to be used
with programming equipment
for the purpose of automatically matching the device to
be programmed with its corAO

01

02

VIL

0

0

VIH

0

Notea:
A. - 12V ±

The electronic signature is activated when + 12V is applied
to address line Ag (pin 24) of
the MBM27C256A-W. Two
identifier bytes are read out

03

0

o.sv.

A, thru A" - A'0 thru A'3
A14 = Either VIL or VIH.

- ~ - l:5E -

V,L.

FUJITSU
6-60

from the outputs by toggling
address line Ao (pin 10) from
VIL to VIH. The address lines
from Al and A13 must be held
at VIL to keep the electronic
signature mode. See the table
below.

04

05

06

07

Os

Definition

0

0

0

0

0

Manufacture

0

0

0

Device

• •M27C2seA·20·W
• • •27C2SeA·2S·W

Programmlng/.ra.lng
Infol'llUltion (Continued)

DC Characteristics
(TA = 25'C ± 5'C,
Vee = 6V ± 0.25V,
Vpp = 21V ± 0.5V)
Parameter

Symbol

Input leakage current
(VIN = 5.25V /0.45V)

Vpp supply current during
programming pulse (E = VII)
Vcc supply current

Icc

Min

Typ

Max

Unit

III

10

)J.A

Ipp

40

mA

30

mA

Input low level

-0.1

0.8

V

Input high level

2.0

Vcc

Output low voltage during verify
(IOL = 2.1 mAl

-.

V
V

0.45

VOL

Output high voltage during verify
(IOH = -400 )J.A)

+ 0.3

2.4

V

vee must be applied either coincident with or before Vpp and removed either coincident with or after Vpp.
Vpp must not be greater than 21.5V including overshoot. Permanent device damage may occur if the device is taken out or put
into socket with Vpp = 21 V. Also, during E' = VIL. Vpp must not be switched from 5V to 21 V or vice-versa.

Programming Waveform
PROGRAM

ADDRESS

VERIFY

ADDITIONAL PROGRAM

I

V..

V,L

DATA

Vpp

v••

Vee

V",

V,L

V,.
VOL

C256-10

FUJITSU

6-61

• • • 27C2S6A·2o-W
• •M27C2SeA·2S·W

Programmlng/Era.lng
Information (Continued)

Quick Program Flow Chllrt

(

FAIL

)

PROGRAMMING FLOW CHART
Vee - 5V ± 0.25V
Vpp - 12.5V ± 0.3V

(

Tpw = 1 ms-50,..,s
(·Xms e 5%)

FAIL

)

G: START ADDRESS
N: STOP ADDRESS
X: COUNTER VALUE
MAXIMUM 105 me/BYTE
MINIMUM 3.8 me/BYTE
C258-11

FUJITSU
6-62

.B.27C2S8A·2G-W
.B.27C2S8A·2S·W

P.cka•• Dlm.nslons
Dimensions in Inches
(millimeters)

28 .....d C.r.mlc (CIIRDIP with Transp.rent Lid)
Dual In...ln. Pack•••
(C••• No.: DIP.28C-C01)

"~(::::2:::]3~~~
-'"j~IOC1(2.54)MAX
' :
-----.

-.t23O(5.84)MAX

~.IIO(3.DI)

~.I5O(UI)
.010(2.211)

.00(1.08)

0.32(0.81)

.110(2.711)

.082(1.88)

TYP

,

=~:~

UOO(33.02)REF
.013(0.33)
·0000o.88)

32·Pad C.ramlc (M.taISe.1) Le.dl.s. Chip C.rrl.r
(C••• No.: LCC·32CoA01)
.36O(9.14)TYP

PIN NO. 1

'll
8
280(7,11)
CIA TYP

.5015(13.84)
.360(14.22)

.445(11.30)
~1.88)

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WI11IOUT NonCE.

6-63

FUJITSU

MOS Memories
•

MBM27C512-25, MBM27C512-30
CMOS 524,288-Bit UV Erasable
and Electrically Programmable
Read Only Memory

Description
The Fujitsu MBM27C512 is a high speed 524,288-bit static complementary MOS erasable and electrically reprogrammable read only
memory (EPROM). It is especially well suited for application where
rapid tum-around and/or-bit pattern experimentation, and lowpower consumption are important.
A 28-pin dual-in line package with a transparent lid and 32-Pad
Leadless Chip Carrier (LCC) are used to package the
MBM27C512. The transparent lid allows the user to expose the device to ultraviolet light in order to erase the memory-bit pattern previously programmed. At the completion of erasure, a new pattern
can then be written into the memory.
The MBM27C512 is fabricated using CMOS double polysilicon gate
technology with single transistor stacked gate cells. It is organized
as 65,536 words by 8-blts for use in microprocessor application.
Single + 5V operation greatly facilitates Its use in systems.

Features
•
•
•
•
•
•
•
•
•

CMOS power consumption
Standby: 525p.W max.
40 mWIMHz
Active:
65,536 words x 8-blta organization, tully decoded
Single location
programming
Programmable utilizing
the Quick Pro Algorithm
VPP
l2.5V
Programs with 1 ms pulsea
No clocks required
(fully static operation)
nL compatible Inputs!
outputa
Fast access time:
250 ns max.
(MBM27C5l2-25)
300 ns max.
(MBM27C5l2-30)

=

•
•
•
•
•

Three-state output with
OR-tie capsblllty
Output Enable (OE) pin
tor simplified memory
expansion
Single +5V supply,
± 5% tolerance
Standsrd 2B-pln DP packsge snd 32-pad LCC
Interchangeable with
275l2-type device

This device contains circuitry to

protect the inputs against damage
due to high static voltages or
electric fields. However, It is
advised that normal precautions be
taken to avoid application of any
voltage higher than maximum rated
voltages to this high impedance
circuit.

6-64

MBM27C512·25
MBM27C512·30

MBM27C512 Block Diagram
and Pin Assignments

o.

0,

A"

Vee

A"

A"

A,

A"

.

A.

..
A,

A•
A"

.,
A,

OE/Vpp

..

A"

A,

0,

'"
'"

ONO

0.

0,

0,

0,

0,

COLUMN
GATING

A12 A15 Vee
A14 A13
NC

A7

512 x 1024
CELL MATRIX

GNO

GNO

o.

Absolute Maximum Ratings
(See Note)

Rating

S,.mbol

Value

Unit

Temperature under Bias

TBIAS

-25 to +85

°C

-65 to +125

°C

-0.6 to +7

V

Storage Temperature

All InputS/Outputs VoHage wHh
Respect to GND
Voltage on

Ag with Respect to GND

-0.6 to 13.5

V

Vpp Voltage with Respect to GND

Vpp

-0.6 to +14

V

Supply Voltage with Respect to GND

Vee

-0.6 to +7

V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

Capacitance
(TA

= 25°C, f = 1 MHz)

Parameter

S,.mbol

= Ov, except OENpp)
OENpp Input Capacitance (VIN = OV)
Output Capacitance (VOUT = OV)

Input Capacitance (VIN

FUJITSU
6·65

CIN.

Min

Typ

Max

Unit

4

6

pF

20

pF

8

12

pF

C IN2
COUT

MBM27C512·25
MBM27C512·30

Functions and Pin
Connections

Recommended Operating
Conditions
(Referenced to GND)

Function IPln No.)
Data 1/0
111 - 13,
15 - 19)

i

GllVpp

Mode

Address
Input
11 - 10,21,
23 - 27)

120)

122)

128)

Vee

OND
114)

Read

AIN

OUT

Vil

Vil

5V

GND

Output Disable

~N

High-Z

Vil

VIH

5V

GND

Standby

Don't Care

High-Z

VIH

Don't Care

5V

GND

Program

AIN

IN

Vil

12.5V

BV

GND

Program Verify

AIN

OUT

Vil

Vil

BV

GND

Program Inhibit

Don't Care

High-Z

VIH

12.5V

BV

GND

Parameter

Symbol

Min

Typ

Max

Unit

Vee Supply Voltage

Vee

4.75

5.0

5.25

V

Input High Voltage

VIH

2.0

Vee +0.3

V

Input Low Voltage

Vil

-0.1

0.8

V

Operating Temperature

TA

0

70

·C

DC Characteristics
(Recommended operating
conditions unless
otherwise noted)

Parameter
Input Load Current (VIN

Symbol

=

5.25V)

Output Leakage Current (Vour
Vee Standby Current (E

=

=

5.25V)

VIH )

=

Min

Typ

Unit

10

pA

ILO

10

pA
mA

ISB1

~e Standby Current

= 0 mAl
Vee Active Current (E = Vld
Vee Operation Current (f = 4 MHz,
lour = OmA)
Output Low Voltage (Iol = 2.1 mAl
Output High Voltage (lOH = -400 pA)
Output High Voltage (lOH = -100 p,A)

(E

Max

III

Vee ±0.3V, lour

6-66

ISB2

100

lee1

30

mA

lee2

30

V

0.45

VOL

p,A

V

VOH1

2.4

V

VOH2

Vee -0.7

V

MBM27C512-25
MBM27C512-30

AC Test Conditions
(including programming)

Input Pulse Levels:
Input Rise and Fall Times:

0.45V to 2.4V
",20 ns

Timing Measurement
Reference Levels:

0.8V and 2.0V for inputs
0.8V and 2.0V for outputs
1 TIL gate and CL = 100 pF

Output Load:

AC Characteristics
(Recommended operating
conditions unless
otherwise noted)

Parameter

Symbol

Address Access Time"' (E
E to Output Delay (OE

=

OE to Output Delay" (E

= OE = V1L)
V1d

=

V1Ll

~
I

MBM27C512-25
Min
Max
TyP

MBM272C512·30
Min
Typ
Max

t ACC

250

300

tE

250

300

tOE

100

Address to Output Hold

tOH

0

OE, E High to Output Floa\"2

tOF

0

120
0

60

0

105

Notes: *1 DE may be delayed up to lACe - toE after the falling edge of E without impact on lACe*2 tOF is specified from DE or ~, whichever occurs first. Output Float is defined as the point where data is no longer driven.

Operation Timing Diagram
(including programming)

>

ADDRESS

K

ADDRESS
VALID

I

~

tE

I

~
tOE
tOH

tAce

OUTPUT

VOH
VOL

HIGH-Z

////,

",-""

FUJITSU
6-67

VALID OUTPUT

k,

1"'F/,I/

HIGH-Z

MBM27CS12.2S
MBM27CS12·30

Programming/Erasing
Information

Memory Cell Description
The MBM27C512 is fabricated
using a single-transistor stacked
gate cell construction, implemented via double-layer polysilicon technology. The individual
cells consist of a bottom floating
gate and a top select gate (see
Memory Cell diagram). The top
gate is connected to the row decorder, while the floating gate is
used for charge storage. The cell
is programmed by the injection of
high energy electrons through the
oxide and onto the floating gate.
The presence of the charge on
the floating gate causes a shift in
the cell threshold (refer to Memory Cell Threshold Shift). In the
initial state, the cell has a low
threshold (VTH1 ) which will enable the transistor to be turned on
when the cell is selected (via the
top select gate). Programming
shifts the threshold to a higher
level (VTHO )' thus preventing the
cell transistor from turning on
when selected. The status of the
cell (i.e., whether programmed or
not) can be determined by examining its state at the sense
threshold (VTHS), as indicated by
the dotted line in Figure 4.
Programming
Upon delivery from Fujitsu, or
after each erasure (see Erasure
section), the MBM27C512 has all
524,2BB-bits in the "1 ", or high,
state. "D's" are loaded into the
MBM27C512 through the procedure of programming.
The MBM27C512 is programmed
with a fast programming algorithm designed by Fujitsu, called
Quick ProT~ The programming
mode is entered when + 12.5V
and + 6V are applied to the
OE/Vpp pi!!, and Vce pin respectively and E is V 1H . ~D.I /LF
capacitor between OE/Vpp Pin
and GND Pin is needed to prevent excessive voltage transients
which could damage the device.
The address to be programmed
is applied to the proper address
pins. The B-bit pattern is placed
on the respective data output
pins. The voltage levels should

Memory Cell

SELECT GATE

~

DRAIN

I

~:

FLOATlNG GATE
SOURCE

Memory Cell Threshold Shift

NOT PROGRAMMED

PROGRAMMED

"1"

"0"

PROGRAM
ERASE

VTH1

VYHS

VTHO

(NOT PROGRAMMED) (SENSE THRESHOLD) (PROGRAMMED)
SELECT GATE VOLTAGE (V)

be standard TTL levels. When
both the address and the data
are stable, a sequence of 1 ms
TTL lOW-level pulse is applied to
the E pin and after that, an a!!ditional pulse is applied to the E
pin to accomplish the programming. Refer to the attached flow
chart.
Procedure of Quick Pro™ (Refer
to the attached flowchart.)
I) Input the start address (=G).
2) Set Vee = 6V, VPP = 12.5V.
3) Clear the programming pulse
counter (X'" 0).
4) Apply ONE programming
pulse (tpw = 1 ms Typ.) to E.
5) Increment the counter
(X-X+l).
6) Compare the number (=X)
of applied programming
pulse with 20. If X = 25, go
to step B). If X < 25, proceed to next step.

6-68

7) Verify the data. If programmed data is the same
as input data, proceed to
next step. If not, go back to
step 6).
B) Apply the additional programming pulse (3 x ms).
9) Compare the address with
an end address (=N). If the
programmed address is the
end address, proceed to
next step. If not, increment
the address (G ... G+I) and
then go to step 3) for the
next address.
10) Verify the all prOgrammed
data. If the programmed data
are the same as original
data, programming was
successful.
A continuous TTL low level
should not apply to 1: input pin
during the program mode
because it is required that one
programming pulse width does
not exceed 7B.75 msec at each
address.

MBM27C512.2S
MBM27CS12·30

Protlirammlng/Eraslng
Information
(Continued)

Erasure

m2 for 15 to 20 minutes. The
MBM27C512 should be about
one inch from the source and all
filters should be removed from
the UV light source prior to
erasure.

In order to clear all locations of
their programmed contents, it
is necessary to expose the
MBM27C512 to an ultra-violet
light source. A dosage of 15 Wseconds/cm 2 is required to completely erase an MBM27C512.
This dosage can be obtained by
exposure to an ultra-violet lamp
(wavelength of 2537 Angstroms
(A)) with intensity of 12000 ,.WI

It is important to note that the
MBM27C512 and similar devices
will erase with light sources having wavelengths shorter than
4000A. Anhough erasure time will

be much longer than with UV
source at 2537A, nevertheless
the exposure to fluorescent light
or sunlight will eventually erase
the MBM27C512, and such exposure should be prevented to realize maximum system reliability. If
used in such an environment, the
package windows should be covered by an opaque label or
substance.

Programming Waveform

ADDRESS

DATA

vee

~vpp

I!

DC ChIIrscterlstlcs
(TA = 25±5°C,
Vcc·' = 5V±5%,
Vpp·2 = 12.5±0.3 V)

Parameter

Symbol

Input Leakage Current
(VIN = 5.25 V/0.45 V)
Vpp Supply Current During
~ogramming Pulse
(E= V1d

Min

Max

Unit

III

10

,.A

Ipp

50

rnA

TyP

Vcc Supply Current

Icc

30

rnA

Input Low Level

V1L

-0.1

0.8

V

Input High Level

V1H

2.0

Vee

Output Low Voltage During Verify
(lOL = 2.1 rnA)

VOL

Output High Voltage During Verify
(IOH = -400,.A)

VOH

0.45
2.4

+ 0.3

V
V
V

Note: *1 Vee must be applied either coincidently or before Vpp and removed either coincidently or after Vpp.
*2 Vpp must not be greater than 14 volts Including O!ershoot. Permanent device damage may occur If the device Is taken out of or put
Into a socket with Vpp "" 12.5 volts. Also, during E = VIL. Vpp must not be switched from 5 to 12.5 volts or vice-versa.

FUJITSU
6-69

MBM27C512.25
MBM27C512·30

AC Characteristics
(TA = 25±~oC,
Vee = 6V±0.25V,
Vpp = 12.5V±0.3V)

Typ

Parameter

Symbol

Min

Address Setup Time

tAS

2

Max

/LS

Unit

/LS

Chip Enable Setup Time

t ES

2

Output Enable Setup Time

IoEs

2

/LS

Data Setup Time

tos

2

/LS

Vee Setup Time

tvs

2

/LS

Address Hold Time

tAH

2

/LS

Data Hold Time

tOH

2

/LS

Output Enable Hold Time

tOEH

2

/LS

Vpp Recovery Time

tVA

2

Chip Enable to Data Valid

tov

Output Disable to Output Float Delay

tOF

0

Vpp Program Pulse Rise Time

tpAT

50

Programming Pulse Width

tpw

0.95

Additional Programming Pulse Width

tAPW

2.85

Programming Flow Chart

Vee = 6V±O.25V

OE/Ypp '" 12.5V:!:O.3V
G: START ADDRESS

N: STOP ADDRESS
X: 4?OONTER VALUE
MAXIMUM 105IM/BYTE
MINIMUM 3.8I1'18!BYTE

6·70

/LS
/LS

130

ns

1.05

ms

78.75

ms

ns

3

MBM27C512.25
MBM27C512·30

...cka•• Dlm.nslons
Dimensions in inches
(millimeters)

28.L.ad Ceramic (ERDP with Transpar.nt IIdl Dual In· Lin. Pack. . .
(Cas. No.: DP.28C·C011

I

R .025(0.64)
REF

.570(14.48)
.585(15.11)

rn

.800(I5.24)REF

.100(15.24)

1OT-=-=-=--<=r=-=-c::r'IIJ

I'-c-cC
C:r=-I:C
c:::r-=-cL:J""""L:J'"C

1.436(36.45)
1.500(38.10)

1 "~~=i~---L

G5 5A8
.
)

.

.013(0.33)
.023(0.58)

32·...d C.ramlc (M.tal "all L.adl... Chip Carrl.r
(Cas. No.: LCCo32C-A011
.38O(9.14)TVP
O.I5!~~P
..-~-,t,.,,...,..,..,...,..,..,.rm-<

.445(11.30)
.480(11.88)

• Shape of Pin Index: Subject to change wHhout notice

6-71

Advanced Information

FUJITSU

MOS Memories
•

MBM27C1001-20-, MBM27C1001-25
CMOS 1,048,576-Bit UV Erasable
Read Only Memory

Description
The Fujitsu MBM27C1001 is a high speed 1,048,576-bits complementary MOS erasable and electrically reprogrammable read only
memory (EPROM). It is especially well suited for application where
rapid turn-around and/or bit pattern experimentation, and low-power
consumption are important.
A 32-pin dual-in line package with a transparent lid is used to
package the MBM27C1001. The transparent lid allows the user to
expose the device to ultraviolet light in order to erase the memory
bit pattern previously programmed. At the completion of erasure, a
new pattern can then be written into the memory.
The MBM27C1001 is fabricated using CMOS double polysilicon
gate technology with single transistor stacked gate cells. It is organized as 131,072 words by 8-bits for use in microprocessor
applications.

Features
• 131,072 words x B-bit organIzation, fully decoded
• Four words programming
• Programmable utilizing the
Quick Pro™ algorithm
• Programming voltage: 12_5V
• Low power consumption:
42 mW/MHz max_ (Active)
550 p,W max_ (Standby)
• No clocks required (fully
static operation)
• TTL compatible Inputs/outputs

• Three-State output for
wired-OR capability
• Output Enable pin for simplified memory expansion
• Single +5V supply,
± 10%tolerance
• Fast access time:
200 ns max_ (MBM27C1001-20)
250 ns max. (MBM27C1001-25)
• 32-pln Ceramic (Cerdip)
DIP package

6-72

Iiw

Ria

MBM27C1001·20
MBM27C1001·25

MBM27C1001 Block
Diagram
and Pin Assignment

,

OE

""'"

0,
0,

A,
A,

A,

CHIP ENABL.E"
OUTPUT ENABL.E "
PROGRAM LOGIC

r ·1

I
r-

Vee

PllII

Ne

OUTPUT
BUFFER

A,.

.

A"

•

DATA INPUT
BUFFER

•
,

COLUMN

DeCODER

A,

0,

I

A"

.,

0,

COLUMN

GATING

v,"

1024 x 1024

X,
ROW
DECODER

A"

CELL MATRIX

I

A,

0,

0,

0,

0,

O.

'"

Vo<

GND

Package Dimensions
Dimensions in inches
(millimeters)

0,

0,

X'023

Vee

A"

A,

V,

I

OE

32·Lead Ceramic (Cerdlp with Transparent Lid) Dual In·Llne Package

6-73

FUJITSU

Advanced Information
•

MBM27C1024.20, MBM27C1024·25
CMOS 1,048,576-Bit UV Erasable
Read Only Memory

Description
The Fujitsu MBM27C1024 is a high speed 1,048,576-b~s complementary MOS erasable and electrically reprogrammable read only
memory (EPROM). It is especially well su~ed for application where
rapid tum-around and/or bit pattern experimentation, and low-power
consumption are important.
A 4O-pin dual-in line package with a transparent lid and 44-pad
leadless chip carrier (LCC) are used to package the MBM27C1024.
The transparent lid allows the user to expose the device to uHraviolet light in order to erase the memory bit pattern previously programmed. At the completion of erasure, a new pattern can then be
written into the memory.
The MBM27C1024 is fabricated using CMOS double polysilicon
gate technology with single transistor stacked gate cells. It is organized as 65,536 words by 16-bits for use in microprocessor applications. Single + 5V operation greatty facilitates its use in systems.

• 65,536 words x 16-blt organizetlon, fully decoded
• Single location programming
• Programmable utilizing the
Quick Pro™ algorithm
• Programming voltage: 12_5V
• Low power consumption:
. 42 mW/MHz max. (Active)
550".W max. (Standby)
• No clocks raqulred (fully
static operation)
• TTL compatible Inputs/outputa
• Three-State output for
wlrad-OR capability

• Output Enabla pin for slmpllfled mamory axpanslon
• Single +5V aupply,
±10% toleranca
• Fast access time:
200 na max_ (MBM27C1024-20)
250 ns max. (MBM27C1024-25)
• JEDEC approved
pin aSSignment
• 4O-pln Ceramic (Cerdlp)
DIP package
/44-pad Ceramic LCC

6-74

MBM27C1024·20
MBM27C1024·25

MBM27C1024 Block
Diagram and
Pin Assignment

Do

=:

-

CHIP ENABLE &
OUTPUT ENABLE &
PROGRAM LOGIC

J

r--

0"

r

r
OUTPUT
BUFFER

t
Do

DO

DATA INPUT
BUFFER

0"

AO

A,

A,

-

..

:

0"

,

Vb
COLUMN

COLUMN

DECODER

GATING

,

V63

Xo
ROW
DECODER

1024 x 1024
CELL MATRIX

X1023

t

Vpp

t

Vee

6·75

t

GND

1

Vpp

Vee
PGM

0"

NC

0,.

A"

0"

A,.

012

A"

0"

A,.

0'0

A"

D.

A,o

Do
GND

A.
GND

0,

Ao

Os

A,

0,

As

D.

A,

0,

A<

0.

Ao

0,

A.

Do

A,

OE

Ao

FUJITSU

Advanced Information
•

MBM27C1028-15, MBM27C1028-20,
MBM27C1028-25
CMOS 1,048,576-Bit UV
Erasable Read Only Memory

Description
The Fujitsu MBM27Cl028 is a high speed 1,048,576-blts complementary MOS erasable and electrically reprogrammable read only
memory (EPROM). It is especially well suited for application where
rapid turn-around and/or bit pattern experimentation, and low-power
consumption are important.
Multiplexed address and data pin permit the MBM27Cl028 to be
housed in a 28-pin dual-in-line package and 32-pad LCC. The
transparent lid allows the user to expose the device to ultraviolet
light in order to erase the memory bit pattern previously programmed. At the completion of erasure, II new pattern can then be
written into the memory.
The MBM27Cl028 is fabricated using CMOS double polysilicon
gate technology with single transistor stacked gate cells. It is
organized as 65,536 words by l6-bits for use in the newer microprocessor applications.

Features
• 65,536 words x 16-blt organization, fully decoded
• Single location programming
• Programmable utilizing the
Quick Pro™ algOrithm
• Programming voltage: 12.5V
• Low power consumption
42 mW/MHz max. (Active)
550 p.W max. (Standby)
• On-chip latches for addresaes
• Output unletched at
read/programming cycle
• Provide electrical chengeable
control algnallRE and ADD
pin (fOr word transfer or byte
trsnsfer upper half or lower
half)

• TTL compatible Inputs/outp"'!!
• No Interface Is required to the
MBLl066/MBLl0186
• Single +5V supply,
± 10% tolerance
• Faat aecaas time:
200 ns max. (MBM27C1028-20)
250 ns max. (MBM27C1028-25)
• JEDEC approved pin
assignment
• 28-pln Ceramic (C8rdlp) DIP
package/32-pad Ceramic LCC

6-76

MBM27C1028·15
MBM27C1028·20
MBM27C102a.25

MBM27C1028 Block
Diagram and Pin
Assignment

eE
DE

CHIP ENABLE.
OUTPUT ENABLE •
INPUT LOGIC.
PROGRAM LOGIC

.([E

i'GiI

AD,

AD15

IIHE

DUTPUT
BUFFER

v••

Vee

NC

I'l!I.l

~

BHE

E

.([E

NC

NC

AD,

A,.

ADo

AD15
D"

AD15

AD,

AD-,

AIlg

AD1.

AD,

AD.

AD10

AD13

Do

AD,

AD.

ADa
AD,

Y,

AD.

Yea

AD-,

X.

A16

CDLUMN
GAnNG

ADs

AD11

AD12

GND

AD,

1024 x 1024
CELL MATRIX

X,023

t

t

V••

t

GND

Vee

FUNcnONAL TRUTH TABLE
ADO

Al-AIS

AlB

ALE

BHE

E

OE

PGM

VCC

Vpp

HIGK-Z

HIGH-Z

X

X

X

VIH

X

X

SV

SV

AIN

AIN

t

VIL

VIH

VIH

SV

SV

OUT'

OUT'

X

VIL

X

VIL

VIL

VIH

SV

SV

HIGH-z

X

VIL

X

VIH

X

HIGH-Z

VIL

X ~

SV

SV

PROGRAM ADDRESS LATCH

VIL

~N

AIN

VIL

VIL

VIH

VIH

6V

12.SV

PROGRAM

IN

IN

X

VIL

X

VIL

VIH

VIL

6V

12.5V

STANDBY
READ ADDRESS LATCH
READ
OUTPUT DISABLE

t

PROGRAM VERIFY

OUT

OUT

X

VIL

X

VIL

VIL

VIH

6V

12.SV

PROGRAM INHIBIT

HIGH·Z

HIGH-Z

X

X

X

VIH

X

X

BV

12.5V

X:
Either VIL or VIH
A'N: Address Input
IN:
Data Input
OUT: Da1a Ou1pul
'OUTPUT TRUTH TABLE
ADo

BHE

ADo-ADy

ADS-AD15

VIL

VIL

DO-D7

DS-D15

VIL

VIH

DO-Dy

HIGH·Z

VIH

VIL

HIGH-Z

OS-DIS

VIH

VIH

HIGH·Z

HIGK-Z

FUJITSU

6·77

MBM27C1028·15
MBM27C102a.20
MBM27C102a.25

Recommended Operating
Conditions
(Referenced to GND)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vcc

4.5

5.0

5.5

V

input high level

V 1H

2.0

Vcc

Input low level

V 1L

-0.1

O.B

V

Operating temperature

TA

0

70

'C

DC Characteristics
(Recommended operating
conditions unless otherwise
noted)

Typ

V

Parameter

Symbol

Min

Max

Unit

Input high level leakage current

III

-10

10

p.A

Output leakage current

ILO

-10

10

p.A

Vcc standby current (E = TTL V 1H)

ISBl

Vcc standby current (E = CMOS V 1H )

ISB2

100

p.A

V cc active current (E = V1J

ICCl

50

mA

Vcc operation current (E = V1J

Icc2

50

mA

V pp supply current

Ipp

100

p.A

Output low level (loL = 2.1 mAl

VOL

0.45

V

Output high level (loH = -400 p.A)

V OH1

2.4

V

Output high level (loH = -100 pA)

VOH2

Vcc - 0.7

V

AC Characteristics
(Recommended operating
conditions unl.ess otherwise
noted)

+ 0.3

mA

MBM27C1028
·15
·20
Min Max Min

Max

150

200

·25
Min

Parameter

Symbol

ALE active to output valid

tACC

ALE precharge time

tpc

60

75

ALE setup time

t ALS

0

0

0

ns

Address setup time

t AS

20

25

30

ns

Address hold time

tAH

20

25

30

ns

E setup time

tCES

60

75

100

DE to output valid'1

tOE

60

70

100

ns

DE high to output float'2

tOF

60

60

60

ns

OE setup time

tOES

20

25

Note: ·2 Output float is definlKl as the point where data is no longer driven.

6·78

Max

250
100

30

Unit
ns
ns

ns

MBM27C1028·15
MBM27C1028·20
MBM27C1028·25

Read Waveform

1
-.. ~
.
II

teEs

~

tACC

/
I----Ipc
IAH _ _

1--1. .

)

VALID

(

I
ADDRESS/DATA

It-

ADDRESS VAUD

DATAVAUD

~~"I
'1\

FUJITSU

6-79

--

}-

........... IOF
10E

/

MBM27C1028·15
MBM27C1028·20
MBM27C1028·25

Read Waveform

V,H

E

V,L

V,H

ALE

V,L

V,H

BHE

V,L

ADo

VIH/VOH
VIL/VOL

VIH/VOH

AD1-7

V'UVOL

VIH/VOH

ADa-15

Vll/VOL

V,H
A"

Oe

OUTPUT

V,L

V,H
V,L

LOWER & UPPER

BYTE

DATA

6·80

LOWER

BYTE

UPPER

BYTE

UPPER

BYTE

MBM27C1028·15
MBM27C1028·20
MBM27C1028·25

DC Characteristics
During Programming
(TA = 25°C ± 5°C,
Vcc = 6V ± 0.25V,
V pp = 12.5V ± 0.3V)

AC Characteristics
During Programming

Parameter

Symbol

Min

Max

Unit

Input high level

V 1H

2.0

Vee + 0.3

V

Input low level

Typ

V1l

-0.1

0.8

V

Input load current

III

-10

10

,."A

V cc supply current

IcC3

50

mA

V pp supply current

Ipp2

50

mA

Output low level (IOl = 2.1 mAl

VOL

0.45

V

Output high level (lOH = -400,."A)

V OH

2.4

V

Parameter

Symbol

Min

Vcc setup time

tvcs

4

Typ

V pp setup time

t vps

4

,."S

E setup time

tCES

4

,."s

Max

Unit
,."s

Address setup time

t AS

Address hold time

tAH

ALE precharge time

tpc

2

ALE low hold time

tAlH

2

,."s

Data setup time

tos

2

,."s

,."s
,."s
,."s

Data hold time

tOH

2

,."s

OE setup time

tOES

2

,."s

OE to output valid

tOE

120

OE to output float

tOF

105

ns

Programming pulse width

tpw

1.05

ms

Additional programming, pulse number

n

25

times

FUJITSU

6·81

0.95

1.00

ns

MBM27C1 02..1S
MBM27C1028-20
MBM27C1028-2S

Programming Waveform
6V

Vee

5V

12.5V
5V

Vpp

"'.

I!

V,L

V,.
V,L

Pll1II

1DH

AD"

VIH/VOH

V,UVOI.

A,".R

V,.
V,L

ALE

V,.
V,L

lm

Viii
V,L

6-62

MBM27C1028·15
MBM27C1028·20
MBM27C1028·25

28.Lead Ceramic (Cerdip with Transparent Lid) Dual In. Line Package
(Case No.: DIP.28C·C01)

R .025(0.64)
REF

.570(14.48)

.'-c::::n=--=r-.:::::n=--=rc:::.--=-.::::,--,=-=--c::::n=--=. . ,

=__

f o l. . .

O_O
____

rn

T" jt: . ","~=-r-

::~~!~:~~l--------Jo... . j l -

.008(0.20)

~.Ol4(O.36)

.090(2.29)
.110(2.79)

~----~==~~~--~~

32·Pad Ceramic (Metal Seal) Leadless Chip Carrier
(Case No.: LCC.32C·A01)
.36O(9.14)TYP

·Shape of Pin index: Subject to change without notice

6-83

.•_o_T-

FUJITSU

Advanced Information
•

MBM28C64.25, MBM28C64·35
CMOS 65,536-Bit Electrically
Erasable Read Only Memory

DeBcrlption
The Fuptsu MBM28C64 is a 65,536-bit CMOS electrically erasable
read-only memory (EE PROM). The MBM28C64 uses internally
latched address, and data protection circuitry 10 protect against
short write pulses and noise on W. The device dissipates only 110
mW in the active mode and 550,.W in standby.
The MBM28C64 is ideal for a wide variety of applications which require non-volatility and in system data modification. The
MBM28C64 is available in a 26-pin ceramic dual in-line package.

-

-

Featurea

• S,192 words x B-blt, fully
decoded
• Internally latched address/data
In writing
• Automatic Byte-Erase
before Write
• Selt-tlmed Byte Write
• Data protection against short
write pulse and noise on W
• On chip data verification
• DATA POLLING

• Lowpower

Active: 165 mW
Standby: 55O,.W
• Access time
250 ns max. (MBM26C64-25)
350 ns max. (MBM2BC64-35)

• Chip erase capability
• TTL compatible Input/output
for fully MPU Interface
• Three-state output for
wired-OR cepability
• Output enable (OE) for slmpHfled memory expansion
• Single +5V supply,
± 10%tolerance
• Minimum Endurance of 10000
Erase/Write cycle per Byte
• JEDEC approved pin out
and package

7-2

•

MBM28C84·25
MBM28C84·35

MBM28C84 Block Diagram
and Pin Assignment

GNO-_

NC

Vee

A,.

W

Vee
IIOB

1/0,
WRITE INHIBIT

CIRCUIT

CE
CE

CHIP ENABLE &.
OUTPUT ENABLE LOGIC

WE

WRITE
CONTROLLER

INPUT/OUTPUT
BUFFER &
LATCH

A7

NC

At;

Aa

A.

Aa

"-

An

Aa

(j!

A.

A,.

E

A,

COLUMN

GATING

Ao
I/O,

110s

1/0.

110s

1/0.

1/0.

GND

1/04

I/~

A.
ADDRESS
LATCH

256:11 256

A"

CELL MATRIX

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Supply voltage with respect to GND

Vee

-0.3 to +7.0

V

All input/output voltage
with respect to GND

VIN' VOUT

-0.3 to Vee + 0.3

V

Voltage on Ag w~h respect to GND

VAg

-0.3 to +13.5

V

Voltage on OE with respect to GND

VOE

-0.3 to +15.5

V

Temperature under bias

TelAs

-25 to +85

·C

Storage temperature

TSTG

-65 to +125

·C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Function and Pin
Connections

Mode

Addr.sslnput
12 to 10, 21,
23 to 25)

(20)

IE

OE
(22)

(27)

VI

Data I/O
1121014,
181020)

Power

Read

AIN

VIL

VIL

VIH

OUT

Active

Don't
care

High-Z

Standby

VIL

IN

Write

I/Oe = 18
1/0, to 1/07
= High-Z

Write

Function IPin No.)

Standby and
write inhibit

Don't care

VIH

Don't
eare

Write

AIN

VIL

VIH

DATA polling"

Wr~e

inhibit

Chip erase

AIN

V IL

VIL

VIH

OUT

Active

AIN

Don't
care

VIL
Don't
care

Don't
care
VIH

High-Z

Active

Don't care

VIL

VOE

VIL

VIH

Chip Erase

Note: • The address must be applied to the address. From then on all output data becomes Input data from the point where the write mode
Is completed.
VOE: 13.5V ± 1.5V

FUJITSU
7-3

MBM28C84·2&
MBM28C64·35

Recommended Operating
Conditions
(Referenced to GND)

Parameter

Symbol

Min

Typ

Max

Unit

Vcc supply voltage

Vcc

4.5

5.0

5.5

V

Input high voltage

VIH

2.0

Vcc +0.3

V

Input low voltage

V ll

-0.1

0.8

V

Operating temperature

TA

0

70

°C

Capacitance
(TA = 25°C, f = 1 MHz)

Min

Typ

Parameter

Symbol

Max

Unit

Input capacitance (VIN = OV)

CIN

10

pF

Output capacitance (VOUT = OV)

COUT

10

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Condition

Symbol

Min

Max

Unit

Input leakage current

VIN = 5.5V

III

-10

10

p,A

Output leakage current

VOLn = 5.5V

ILO

-10

10

p,A

Vcc standby current

~=VIH

ISBl

1

mA

Vcc standby current

~ = Vee ±0.3V

ISB2

100

p,A

Vcc active current

~=VIL

ICCl

30

mA

Vcc active current

f = 4 MHz, lOUT = 0 mA

Icc2

30

mA

Vcc write current

~ = VIL, WE = VIL

Iccw

30

mA

rn: =

Vcc chip erase current

CE = WE = VIL,

ICCE

60

mA

Output low level

IOl = 2.1 mA

VOL

0.45

V

Output high level

IOH

= 400 p,A

V OH

VOE

Operation inhibit level

VINH

Chip erase voltage

VOE

V

2.4

12

3

V

15

V

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

MBM28C64·25
Min
Max

MBM28C64·35
Min
Max

Parameter

Symbol

Address access time

tACC

250

350

Unit
ns

EO to output delay

tE

250

350

ns

Oi: to output delay"

tOE

100

120

ns

E, OE high to output float'2

tOF

60

80

ns

OE high to output

tOH

Notes: *1

*2

0

toe is specified the point where both tee and lACe settled.

~t~~tS~I::~sd~~~ef~O~h;' :~h:~:~O:~a~:~~· kJnger driven.

7·4

0

ns

MBM28C64·25
MBM28C64·35

AC Characteristics
(Byte Write)
(Recommended operating
conditions unless otherwise
noted.)

AC Characteristics
(Chip Erase·')
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Address setup time

t AS

20

Typ

ns

Chip enable setup time

tcs

20

ns

Output enable setup time

tOES

20

ns

Write pulse width

twp

100

ns

Address hold time

tAH

50

ns

Data setup time

tos

50

ns

Data hold time

tOH

20

ns

Chip enable hold time

tCH

0

ns

Output enable hold time

tOEH

20

ns

Write enable hold time

tWEH

10

Byte write cycle time

tWR

Write recovery time

tRE

50

ns

Number of write per byte

N

10

x1000

Symbol

Min

Chip enable setup time

tcs

150

Unit

ns

10

Parameter

Max

Typ

40

Max

ms

Unit
ns

Ouput enable setup time

tOES

150

Write pulse width

twp

5

Data setup time

tos

150

Data hold time

tOH

100

ns

Chip enable hold time

tCH

100

ns

Output enable hold time

tOEH

100

ns

Note: '1

5E

= 13.5V

:!:

1.SV.

FUJITSU

7·5

ns

20

ms
ns

MBM28C64·25
MBM28C84·35

Timing Diagrams
Read Waveform

).

ADDRESS

K

ADDRESS VAUD

tAce

tE
~t""...

FIoE-

DATA

1LLL

VOl<

\ \\\

VOL

DUTPUTVAUD

Byte Write Waveform

V,H
ADDRESS
V,L

VALID

DON'TeARE

te.
E

V,H
DON'T CARE

V,L

w

V,H

IN
V,L

--------------~

7·6

1- tOH
1.\ 1.\
Cj 'j

MBM28C64·25
MBM28C64·35

Timing Diagrams
(Continued)

Chip Erase Waveform

V,H

E

V,L

VOE
V,H
toES

W

V,H
V,L

V,H
tN

V,L

AC Test Conditions
Input Pulse Levels:
Input Rise/Fall Times:
Input Reference Levels:
Output Reference Levels:
Output Load:

0.45V to 2.4V
.;;20 ns
0.8V to 2.0V
0.8V, to 2.0V
1 TTL Gate and CL

~

100 pF

Write Information

Byte Write
The MBM28C64's write mode is
similar to that of Static RAM. The
write cycle is cpmpletely selftimed, and initiated by a low
going TTL pulse on the W pin.
On the falling edge of W, the address data is latched. On the rising edge of W, the input data are
latched. During the write cycle,
the MBM28C64 automattcally
erases the memory data previously written, write new data into
the memory and verify to ensure
successfully the byte write.
Chip Erase
The MBM28C64 has a chip
erase mode using external power
supply which all data can be written to high state (~the erased

state). The erase mode is initiated by setting OE to 13.5V and
applying low TTL level to W while
holdi ng all data inputs on high
TTL level.

DATA Polling
The MBM28C64 features DATA
Polling to signal the completion
of a byte write cycle. During a
write cycle, an attempted read of
the last byte written results in the
data complement of that byte at
1/08 , After completion of the write
cycle, true data is available.
DATA Polling allows a simple
read/compare operation to determine the status of the chip eliminating the need for external
hardware.

FUJITSU
7-7

DATA Protection
The MBM28C64 has three features to prevent an erroneous

initiation of write mode.
Vee Detector: When the Vee is
less than +3V during Vee power-on
and power-off, all
functions are inhibited.
Noise Filter: When initiating
write cycle, the
write pulse of less
than 20 ns is
locked.
Write Inhibit: When OE is low
TTL or E is high
TTL, the initiation
of write cycle is
inhibited.

MBM28C84·25
MBM28C84·35

AC Characteristics
(DATA Polling)
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Max

Unit

Address access time

350

ns

Output enable access time

120

ns

Address setup time to W

Typ

ns

20

Nota: *1 tOE delays up to lACe - tOE after the 1al6ng edge of ~ without impact on lACe·

Data Polling Waveform

ADDRESS

V,H
VIL

J

~

ADDRESS N

__ lACS .....

.'es. !--'AH-V,H
V,l

CE

V,H

~

...

tOES

'o.~

V,l

!+'o...

t

V,l

V,H

!+'Aee"

\

-'AS-

'II

ADDRESS N

DON'TCARE

~twp-----'

\

/
!+-'DS- !---'DH"

...

V,H
IN

VALID

V,l

VOH

0,'

18

Val
IWR

NOTE: '0, THROUGH 0, ARE IN HIGH·Z STATE TILL END
OF WRITE.

7·8

MBM28C84·25
MBM28C84·U

Package Dimensions
Dimensions in Inches
(millimeters)

28·Lead Ceramic Dual In·Llne Package
(Case No•• DIP.28C·C02)

rn
J

r

R.025(O.84)
R~ ~

.570(14.48)
.595(15.11)

"

-~,

II'4t:::r-tw=r-cw:r-tw:::rcw:r-tW:::J1-.435(cw:r3"",;":::JA-5)cw:r-tW:::rcw:r-tw::rwc:r-="....I'
1.500(38.10)

.090(2.29)
.110(2.79)

~--------~~~==-------ff~

7·9

.600(15.24)REF

-j . . 6;::=-t~-~

FUJITSU

Advanced Information
•

MBM28C65.25, MBM28C65·35
CMOS 65,536-Bit Electrically
Erasable Read Only Memory

Description
The Fujitsu MBM28C65 is a 65,536-bit CMOS electrically erasable
read-only memory (EE PROM). The MBM28C65 uses internally
latched address, and' data prc;>tection circuitry to protect against
short write pulses and noise on W. The device dissipates only 110
mW in the active mode and 550 ",W in standby .
The MBM28C65 is ideal for a wide variety of applications which
require non-volatility and in system data modification. The
MBM28C65 is available in a 28-pin ceramic dual in-line package,
and 32-pin LCC.

-

-

Features
• 8,192 words x 8-bit, fully
decoded
• Internally latched address/data
in writing
• Automatic Byte-Erase
before Write
• Self-timed Byte Write
• Data protection against short
write pulse and noise on W
• On chip data verification
• 'Two write status identifiers
READY/BUSY (open drain) and
DATA POLLING
• Low power
Active: 165 mW
Standby: 550/LW
Access
time
•
250 ns max. (MBM28C65-25)
350 ns max. (MBM28C65-35)

• Chip erase capability
• TTL compatible input/output
for fully MPU interface
• Three-state output for
wired-OR capability
• Output enable (OE) for simplified memory expansion
• Single +5V supply,
1: 10%tolerance
• Minimum Endurance of 10000
Erase/Write cycle per Byte
• JEDEC approved pin out
and package

7-10

•

MBM28C85·25
MBM28C85.35

MBM28C85Block Diagram
and Pin Assignment
RDY/liIY

GNO-_

Vee

I/O,
WRITE INHIBIT
CIRCUIT

CE
CE

CHIP ENABLE &t
OUTPUT ENABLE LOGIC

WE

INPUT/OUTPUT
aUFFER&
LATCH

WRITE
CONTROLLER

RDY/RV

Vee

W

A12

"0"

COLUMN
GATING

AD

A7

NC

A.

As

AS

A.

As

Al1

A,

CE

A2

A'D

A,

E

As

I/O.

1/0,

I/Or

1/0 2

I/Ds

I/O,

I/Ds
I/O,

GND

ADDRESS
LATCH

25611: 256

A"

Absolute Maximum Ratings
(See Note)

CELL MATRIX

Rating

Symbol

Value

Unit

Supply voltage with respect to GND

Vee

-0.3 to +7.0

V

All input/output voltage
with respect to GND

VIN' VOUT

-0.3 to Vee + 0.3

V

Voltage on Ag

w~h

respect to GND

VAg

-0.3 to +13.5

V

Voltage on OE with respect to GND

VOE

-0.3 to +13.5

V

Temperature under bias

TBIAS

-25 to +85

°C

Storage temperature

TSTG

-65 to +125

°C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may aHeet device reNability.

Function and Pin
Connections

RDY
BSY
Data I/O
(Open Drain) (12 to 14,
(1)
16 to 201 Power
1271

•

Mode

Address Input
(2 to 10, 21,
23 to 25)

Read

AIN

VIL

VIL

VIH

High-Z

OUT

Active

Standby and
write inhibit

Don" care

VIH

Don't
care

Don't
care

High-Z

High-Z

Standby

Write

AIN

VIL

VIH

VIL

VOL

IN

Write

VOL

I/Oa = 18
1/0, to 1/°7 Write
= High-Z

Function IPin No.1

DATA polling·

Write

inhib~

Chip erase

E
(201

OE
122)

VIL

iN

VIH

AIN

VIL

AIN

VIL
Don't
Don't
care
care

Don't
care
VIH

Don't care

VIL

VIL

VOE

High-Z
VOL

OUT

Active

High-Z

Active

VIH

Write

Note: • The address must be applied to the address. From then on all output data becomes input data from the point where the write mode
is completed.
VOE: 13.5V ± 1.5V

FUJITSU
7-11

MBM28C85.25
MBM28C85·35

Recommended Operating
Conditions
(Referenced to GND)

Parameter

Symbol

Min

Typ

Max

Unit

V cc supply voltage

Vcc

4.5

5.0

5.5

V

Input high voltage

V IH

2.0

Vcc +0.3

V

Input low voltage

V IL

-0.1

0.8

V

Operating temperature

TA

0

70

'C

Capacitance
(TA

= 25'C, f =

1 MHz)

Parameter
Input capacitance (VIN

Symbol

=

OV)

Output capacitance (VOUT

= OV)

Min

Typ

Max

Unit

CIN

10

pF

C OUT

10

pF

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Condition

Input leakage current

VIN

Outp~t leakage current

= 5.5V
= VIH
E = Vcc ± 0.3V
E = V IL , f = 0 MHz
f = 4 MHz, lOUT = 0 mA
E = V IL , W = V IL
IOL = 2.1 mA
IOH = 400/LA

Vcc standby current
V cc standby current
V cc active current
V cc active current
V cc write current
Output low level
Output high level

Symbol

Max

Unit

-10

10

/LA

V OUT

ILO

-10

10

/LA

E

ISBl

5.5V

100

ICCl

20

mA

Icc2

20

mA

Iccw

40

mA

0.45

V

V OH

Chip erase voltage

VOE

2.4

12

ICCE

DE =

/LA

VOL

V INH
E - W = VIL
VOE

mA

ISB2

Operation inhibit level

Vee Chip Erase Current

Min

III

=

V
3

V

15

V

100

mA

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

MBM28C64·25
Min
Max

MBM28C64·35
Min
Max

Parameter

Symbol

Address access time

tACC

250

350

Unit
ns

E to output delay

tE

250

350

ns

OE to output delay'l

tOE

100

120

ns

E,

tDF

60

80

ns

OE high to output floaP

OE high to output

tOH

0

Notes: *1 tOE is specified the point where both tCE and lACe settled.
*2 tOF is specified from DE or E, whichever occurs first.
Output Float is defined as the point where data is no longer driven.

7-12

0

ns

MBM28C85.25
MBM28C85·35

AC Characteristics
(Byte Write)
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Address setup time

t AS

20

ns

Chip enable setup time

tcs

20

ns

Output enable setup time

tOES

20

ns

Write pulse width

twp

100

ns

Address hold time

tAH

50

ns

Data setup time

tos

50

ns

Data hold time

tOH

20

ns

Chip enable hold time

tCH

0

ns

Output enable hold time

tOEH

20

ns

Write enable hold time

tWEH

10

Time to device busy

tOB

Byte write cycle time

tWR

Write recovery time

AC Characteristics
(Chip Erase"')

Max

Unit

ns

10

120

ns

40

ms

tRE

50

ns

Number of write per byte

N

10

xl000

RDY /i3§Y to output time'

tRBO

Note: -If E

(Recommended operating
conditions unless otherwise
noted.)

Typ

=

100

ns

OE = VIL and RDY/t:m'Y is going to OFF. the read data is valid after lAse

Parameter

Symbol

Min

Chip enable setup time

tcs

150

Typ

Max

Unit
ns
ns

Ouput enable setup time

tOES

150

Write pulse width

twp

5

Data setup time

tos

150

Data hold time

tOH

100

ns

Chip enable hold time

tCH

100

ns

Output enable hold time

tOEH

100

Time to Device Busy

tOB

120

ns

Time to Device Ready

tOR

120

ns

Note: ·1

DE =

13.5V ± 1.5V.

FUJITSU

7-13

20

ms
ns

ns

M.M28C85.28
M.M28C88·38

Timing Diagrams
Read Waveform

ADDRESS

VOH
VOL

)

K

ADDRESS VAUD

tAce
VO~

VOL
FIE

~IDf.

DE

VOH
VOL

DATA

~~E_
I III
\\\\"1\

VOH
VOL

~
OUTPUTVAUD

IOH

It\ ,\
t-1 '/

.yte Write Waveform

ADDRESS

VOH
VOL

VAUD

..-tcs

DON'T CARE

IAN

VOH
DON'T CARE

VOL

VOH
VOL

VOH

W

VOL

VOH

VAUD

IN
VOL

i------IWR------+i
RDY!ISV

H-Z
VOL

7-14

MBM28C8S-25
MBM28C8s-as

Timing Diagrams
(Continued)

Chip Erase Waveform

E

V,H

VOE

V,H _ _ _oJ

W

V,H
V,L

V,H

IN

RDY/lifi

V,L

H-Z
VOL

AC Test Conditions
Input Pulse Levels:
Input Rise/Fall Times:
Input Reference Levels:
Output Reference Levels:
Output Load:

0.45V to 2.4V
",20 ns
0.8V to 2.0V
0.8V, to 2.0V
1 TTL Gate and CL = 100 pF

Write Information
Byte Write

The MBM28C65's wrHe mode is
similar to that of Static RAM. The
wme cycle is completely seHtimed, and inHiated by a low
going TTL pulse on the W pin.
On the falling edge of W, the address data is latched. On the rising edge of W, the input data are
latched. During the write cycle,
the MBM28C65 automatically
erases the memory data previously written, write new data into
the memory and verify to ensure
successfully the byte wme.
Chip Erase

The MBM28C65 has a chip
erase mode using external power
supply which all data can be written to high state (=the erased

state). The erase mode is initiated by setting OE to 13.5V and
applying low TTL level to W while
holding all data inputs on high
TTL level.
DATA Polling

The MBM28C65 features DATA
Polling to signal the completion
of a byte write cycle. During a
write cycle, an attempted read of
the last byte written results in the
data complement of that byte at
I/Oa. After completion of the write
cycle, true data is available.

DATA Polling allows a simple
read/compare operation to determine the status of the chip eliminating the need for external
hardware.

FUJITSU
7-15

DATA Protection

The MBM28C65 has three features to prevent an erroneous
initiation of write mode.
Vee Detector:When the Vee is
less than +3V during Vee power-on
and power-off, all
functions are inhibited.
Noise Filter: When initiating
write cycle, the
write pulse of less
than 20 ns is
locked.
Write Inhibit: When OE is low
TTL or E is high
TTL, the initiation
of write cycle is
inhibited.

M8M28C ••·U
M8M28Ces·3S

AC Characteristics
(DATA Polling)
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Address setup time 10 W

Max

Typ

20

Address access time
Outpul enable access lime

10E

Note: *1 tOE delays up to lACe - tOE after the falling edge of

'E without impact on lACe.

Data Polling Waveform

ADDRESS

V,H
VOL

)

K

_IAe,_ ~IAee ...

.'es.. _'AH_
V,H
V,l

OE

V,H

\

~

.'OE~

tOES

V,H
V,l

.'OE'"

~

V,l

_'AS _
W

ADDRESS N

DON'TeARE

ADDRESS N

_

Iwp-

\
1-""05_ ~IDH'"

V,H
IN

VALID

V,l

VOH

0,"

VOL

RDY/IIV

H-Z

;;
tWR

\
__ ID8_

NOTE: ·01 THROUGH 07 ARE IN
OF WRITE.

7-16

HIGH~Z

STATE TILL END

Unit
ns

350

ns

120

ns

M8M28ca5·25
M8M28Ca5.35

Package Dimensions
Dimensions in inches
(millimeters)

28·Lead Ceramic Dual In·Line Package
ICase No.: DIP.28C.C02)

R.025(0.64)
R~.,.

III

~7O(14.4B)
-~

J
1' -.l: :r-.=-l:w:nwW- =rt:=r1-'.43' 5r(36-=.4r5)=-;c' ':n=-=r-.:=r~' ' 'i TllIS;~;::j;--....L.
.595(15.11)

"1.500(36.10)

.090(2.29)

.110(2.79) 1+------1:c,3::00:::(:::33::-.:::02:::)R:::E::F:-----tt-l
.013(0.33)
.023(0.58)

7·17

.600(15.24)REF

FUJITSU

MOS Memories
•

MBM2212.20, MBM2212·25
1,024-Bit Non-Volatile
Random Access Memory

Description
The Fujitsu MBM2212 is a 1,024-bit non-volatile static random
access memory (NVRAM) combined 1,024-bit static random aocess memory (SRAM) and electrically erasable and reprogrammable read only memory (EEPROM) on one-chip. It is designed for
applications such as system potentiometer or electrical switch to
memorize the system condition etc.
The MBM2212 is organized as 256 words by 4-bil. Each one bit is
constituted with a combination of SRAM and EEPROM cell. The
read and write operations are performed on the SRAM cell. The
data transfer between SRAM and EEPROM is performed using two
control pins. The store mode (transferring SRAM data to _
EEPROM) is executed with a single pulse applied to the ST pin.
The recall mode (transferring EEPROM data to SRAM) is executed
in 1.2 p's with one short pulse applied to the RC pin. Both store
and recall operations are completed for all bits at one time.
The MBM2212 is fabricated using N-MOS silicon gate technology
with stacked gate cells. Single +5V supply and TTL input/output
level operations greatly facilitate microprocessor applications.

• 256 words x 4-bit organization,
fully decoded
• 10 ms self-timed auto store
• 10 years data retention for
each store
• Unlimited endurance for recall
• TTL compatible inputs/outputs
• 1I"1-state output
• Wrfte protection on poweron/off and surge pulse

• Low power consumption;
Active: 330 mW max_
Standby: 165 mW max.
• Fast access time;
200 ns max. (MBM2212-20)
250 ns max. (MBM2212-25)
• Standard 18-pin DIP package

7-18

~

I-

-

U

~

ru I~

1:. ,dl, ,DIP

..

:..

MBM2212·20
MBM2212·25

MBM2212 Block Diagram
and Pin Asslgnmant
A7

Vee

A4

A4

ST

A.

A,

RC

A.

1/0,

A,o---t:Id
A.o---I~"1

A. C>--~=L_J

A,

1/0.

Au

1/0.

§

I/O,o--~H

GND

1/0. o--..+CH'NPUT
DATA
BUFFER

1/00

1/0 CIRCUIT

S'i'

COLUMN SELECT

•

1/0, ~+I-tlc.--I

§<>-_.d"_

FUNCTIONAL TRUTH TABLE
S

W

RC

ST

1/0

VCC

GND

POWER

Standby

V,H

X

V,H

V,H

Hlgh·Z

5V

GND

Standby

Read

V,L

V,H

V,H

V,H

OUT

5V

GND

Active

Write

V,L

V,L

V,H

V,H

IN

5V

GND

Active

V,L

V,H

Hlgh-Z

5V

GND

Standby

V,H

V,L

Hlgh-Z

5V

GND

Active

MODE

X

V,H

V,H

X

X

V,H

V,H

X

Recall

Store

Absolute Maximum Ratings
(See Note)

Symbol

Value

Unit

Supply voltage with respect to GND

Rating

Vee

-1.0 to +7.0

V

All input/output voltage with respect
toGND

V,N. VOUT

-1.0 to +7.0

V

Output current with respect to GND

lOUT

+5.0

rnA

Temperature under bias

TBIAS

-10 to +85

·C

Storage temperature

TSTG

-65 to +125

·C

Nota: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

FUJITSU

7·19

MBM2212·20
MBM2212·25

Recommended Operating
Conditions
(Referenced to GND)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vcc

4.5

5.0

5.5

V

Input high level

VIH

2.0

Vcc + 0.5V

V

Input low level

V IL

-1.0'

0.8

V

Operating Temperature

TA

0

70

°C

Note: * For Jess than 50 ns undershoot, but -O.5V for DC.

Capacitance
(TA = 25°C, f = 1 MHz)

I/O capacitance (Vila

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Max

Unit

CIN

Min

6

pF

CliO

8

pF

Symbol

Parameter
Input capacitance (VIN

= OV)
= OV)

Parameter

Condition

Input leakage current

VIN

I/O leakage current

S

Vcc standby current

S

Vcc active cu rrent
Output low level
Output high level

= GND to

Typ

Symbol
5.5V

= V IH , Vila =
= V IH '1
S = VIL '2
IOL = 4.2 rnA
IOH = -2.0 rnA

GND to 5.5V

Max

Unit

Ilul

10

p.A

IILOI

10

p.A

ISB

30

rnA

Icc

60

rnA

VOL

0.4

V

V OH

Store inhibit voltage

Min

2.4

VIHBT

V
V

3

Note: "1 Supply current increases to ICC while store mode regardless o!...S level
'2 Supply current reduces to ISB while recall mode regardless of S level

SRAM Mode AC
Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Read Mode
= ST = RC

(w

=

VIH )

Parameter

Symbol

MBM2212·20
Min
Max

MBM2212·25
Min
Max

Unit

Read cycle time

t RC

200

250

ns

Address access time

tM

200

250

Chip select access time

t ACS

200

250

Output hold after address change

tOH

50

Chip select to output active

tLZ

10

Chip select to output disable'

tHZ

Note: * Transition is measured at point of ± 500 mV from steady state voltage.

7·20

50

ns
ns

10
100

ns

ns
100

ns

MBM2212-20
MBM2212-25

SRAM ModeAC
Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Write mode
(81' ~ RC ~ V,H )
Parameter

Symbol

MBM2212-20/25
Min
Max

Unit

Write cycle time

twc

300

ns

tcw

150

ns

t AS

50

ns

twp

150

ns

Chip select to end of write (W

V,L )

~

Address setup time
Write pulse width (8

~

V,L )

Write recovery time"

tWA

25

ns

Data valid to end of write

tow

100

ns

0

Data hold time

tOH

Write enable to output high-Z'2

twz

Output active from end of write'3

tow

10

Notes: '1 tWR is defined from the end point of write.
*2 Transition is measured at point of ±500 mV from steady state voltage.

'3 If

AC Test Conditions
(including EEPROM mode)

Read Cycle Timing
Diagrams

S goes high coincident with W high transition, DATA OUT remains in a high impedance state.

Input pulse levels:
Input rise/fall times:
Input reference levels:
Output reference levels:
Output Load:

0.6V to 2.4V
,,;10 ns
0.aV,2.2V
0.aV,2,2V
1 TTL gate and CL

Address Control Mode
(5 ~ V,L , W ~ V, H)

ADDRESS

DATA

FUJITSU

7-21

~

ns
100

100 pF

ns
ns

MBM2212·20
MBM2212·25

Read Cycle Timing
Diagrams
(Continued)

S Control Mode"
{W = V 1H)

~--------------------tRe--------------------~

VOH
DATA

DATA VALID

- - - - HIGH·Z - - - - - - - - - {
VOL

D
NOTE: • ADDRESS BECOMES VALID PRIOR TO OR COINCIDENT WITH SLOW
TRANSITION.

Write Cycle Timing
Diagrams

Vi Control Mode
twe
ADDRESS

V,H

ADDRESS VALID

V,L

tew
V,H
V,L

W

DATA IN

V,H
V,L

V,H
V,L

VOH
DATA OUT

VOL

UNDEFINED DATA

7·22

HIGH·Z

UNDEFINED DATA

MBM2212·20
MBM2212·25

Write Cycle Timing
Diagrams
(Continued)

5

Control Mode

ADDRESS

V,H

V,L

=f~----------------------twe---------------------1=~~
_

ADDRESS VALID

---------'-----tAS- t W R

1---------- tew -----------i~

Vi

~------------twP------------~

V,H
V,L

V,H

DATA IN

VIL

VOH
DATA OUT

VOL

-----------------HIGH-Z----------------

FUJITSU

7-23

MBM2212·20
MBM2212·25

EEPROM Read/Write
Information

The MBM2212 can not read or
write EEPROM data externally
and it must be transferred from/to
SRAM cell array corre~ondin9....
to each EEPROM bit. RC and ST
pins are assigned to execute
these operations easily.

Store Mode
The store mode is initiated when
negative pulse (u) is applied to
pin while either S = V'H or
W = V'H and is completed within
10ms automatically by the onchip timer. During this operation
mode, all input and output pins
are inhibited. The original SRAM
data remains after the store mode.

B

Recall Mode
The recall mode is initiated when
~ative pulse (u) i~ applied t~
RC pin while either S = V'H or W
= V'H and is completed within
1.2 ,"s. The supply current is reduced to standby current automatically. Please notice that the
SRAM data is replaced by the
EEPROM data after the execution of this operation.

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

chip. Auto-standby circuit prevents the stored data on the
EEPROM cell array from destruction when Vcc is less
than +3V.
When Vcc power is ON or OFF,
the V,H i.!!Qut level must be applied to ST pin before or while
Vcc is greater than +3V.
These operation modes, store
mode, recall mode and SRAM
write mode have the same logical
priority. Normally the first set logical condition determines the ensuing operation mode among ST,
RC and IN pins.

The MBM2212 has two security
circuits to prevent an erroneous
store mode. Noise filter circuit for
duration of less than 20 ns negative pulse on ST pin is on the

Recall Mode
(IN = ST = V'H)
Parameter

Symbol

MBM2212·20/25
Min
Max

Recall cycle ti me

t RCC

1200

ns

Recall pulse width

tRCP

450

ns

RC to output disable'

t RCZ

RC to output active

t ORC

RC to output valid

t ARC

Unit

150

ns

750

ns

10

ns

Note: * Transition is measured at point of ±500 mV from steady state voltage.

Store Mode
(W = RC = V,H)
MBM2212·20
Min
Max

MBM2212·25
Min
Max

Parameter

Symbol

Store cycle time

tST

Store pulse width'1

tSTP

Store to output disable'2

tSTZ

500

500

ns

Output Valid from End of Store loST

200

250

ns

10
100

20
100

Unit
ns
ns

Note: *1 It is protected from entry into the store mode by less than 20 ns pulse width.
"2 Transition is measured at point of ±500 mV trom steady state voltage.

Endurance
Number of store cycles

Number of data changes per bit

Unit

100,000

10,000

Times

7-24

·

"

MBM2212·20
MBM2212·25

EEPROM Read/Write
Information
(Continued)

Store Cycle Timing Waveform

tST

tSTP

VOH-

OUTPUT

DATA OUT

VAUD

Recall Cycle Timing Waveform
~-------------------~~--------------------"1
ADDRESS V,H

~L

ADDRESS VAUD

________

~~------------~~~----------------------~~~-------

V,H
V,L

~~~~~~~~~~~----------------r---~~~~~

'ORe
VOH
DATA OUT

-------------&--------- HIGK-Z - - - - - - - - - {

VOL __________-'1

OUTPUTVAUD

o

FUJITSU

7·25

UNDEFINED DATA

MBM2212-20
MBM2212·25

Package Dimensions
Dimensions in inches
(millimeters) (Suffix: -Z)

18·Lead Ceramic ICERDIP) Dual·in·Line Package
ICase No.: DIPo1SC-C01)

1~~~~~~~~]j~
I~

.8~22.40:=:

.912(23.16

7-26

..

I

FUJITSU

MOS Memories
•

MB83256·25
CMOS 262,144-Bit
Mask-Programmable
Read Only Memory

Description
The Fujitsu MB83256 is a CMOS Si-gate mask-programmable
static read only memory organized as 32,768 words by 8-bits.
The MB83256 has TIL-compatible 1/0 and TRI-state output level
with fully-static operation (i.e. no need of clock signal) and single
+ 5V power supply. The device is designed for applications such as
character generator or program storage which require large memory capacity and high-spee~/low-power operation.
The MB83256 is packaged in a 28-pin dual-in-line package and its
pin-out is compatible' with standard 28-pin EPROM.

f---f----

-

•
IDI. ~

Features
.32,768 words x 8-bits
organization
• Fast access time:
250 ns. max.
• Complete static operation:
No clock required
• ALL inputs and outputs are
TIL compatible
• Three-state outputs

• +5V supply voltage
• Low power consumption:
83 mW (Operation)
8.3 mW (Standby, TIL
input level)
165 fJ-W (Standby, CMOS
input level)
• Standard 28-pin DIP

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated volt·
ages to this high impedance circuit.

8-2

...

MB83256-25

MB83256 Block Diagram
and Pin Assignment
Ao
A,
A,
Ao
A4
A.

32768 X B-BITS
ROM CELL ARRAY

E·liE

liE

LOGIC

Ao
A7
Ao
A.
A,.
A"
A12
A'3
A,.
Vee ----.

Vss ------.
0,0,0.0. o. 0. 07 0.

NC

Vee

A"
A7

A,.

Ao

Ao

A.

A.

A'3

A4

All

A3

DE

A,

A,.

A,

E

Ao
0,

o.

0,

0.

03

O.

vss

O.

07

TRUTH TABLE
Output

Power
Consumption Mode

Non-selected

Hlgh-Z

Standby

Non-setected

Hlgh-Z

Active

Selected

Output

Active

E

OE

Mode

H

X

L

H

L

L

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Storage temperature range

Tstg

-40 to +125

°C

Operating temperature

TA

-10 to +85

°C

Supply voltage

Vee

-0.3 to +7.0

V

Input voltage

VIN

-0.3 to Vee

Output voltage

VOUT

-0.3 to Vee

+ 0.3
+ 0.3

V
V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Capacitance
(TA = 25°C, f = 1 MHz)

Recommended Operating
Conditions
(Reference to GND)

Parameter

Symbol

Max

Unit

Output Capacitance (VOUl = OV)

Caul

Min

10

pF

Input Capacitance (VIN = OV)

CIN

7

pF

Typ

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.5

5.0

5.5

V

V

Input low voltage

VIL

-0.3

0.8

Input high voltage

VIH

2.2

Vce + 0.3

V

Ambient temperature

TA

0

70

°C

FUJITSU
8-3

MB832&8·25

DC Charact.rl.tlc.
(Recommended operating
conditions unless otherwise
noted.)

AC Charact.rlstlcs
(Recommended operating
conditions unless otherwise
noted.)

Param.t.r

MB83258·25
Min
Ma.

8ymbol

T ••t Condition.

ISB1

Standby supply current E = VIH
E = Vee. VIN = GND or Vee

ISB2

Active supply current

E-

Icc

Input leakage current

VIN = OV to Vee

III

Output leakage current

E=

Output high voltage

IOH = -400 /LA

ILIO
VOH

Output low voltage

IOL = 2.1 mA

VOL

VIL • minimum cycle
VIH • or i5E = VIH

Param.t.r

Symbol

i5E = Vld
Chip enable access time (OE = Vld

tAee

Output enable access time'1

Address access time (E =

-10
-10
2.4

mA

15
10
10

mA

0.4

V

V

MB8325..25
Typ
Min
Ma.

ns

tE
tOE

100

ns

TDF

Output hold time

tOH

ns

80

ns
ns

0

l5E may be delayed up to (tAce - tOe) after the falHng edge of Ewithout Impact on tACe'
*2 tOF Is specified from OE: or E, whichever occurs earlier.

Note: *1

Timing Diagram

)
-tcE-

\

I
...- tOF*2
_10. 1 •

\

/
!--IoF'2_

lAce

III/-,
\. \. \.\:'

DATA VALID

<"ee - toe) AFTER THE FALLING EDGE OF E

NOTES: '1 OE MAY BE DELAYED UP TO
WITHOUT IMPACT ON lAce.
'2 ID. IS SPECIFIED FROM OE OR

E. WHICHEVER OCCURS EARLIER.

8·4

Unit

250
250

Output disable time'2

ADDRESS

Unit

1.5
30

...

MB83256·25

AC Test Conditions
Input Pulse Levels:
Input Pulse Rise and Fall Time:
Timing Reference Levels:
Output Load:

Typical Characteristics
Curves
(Continued)

to 2.4V
10 ns
Input: V IL = o.av. V IH = 2.2V
Output: VOL = o.av. V OH = 2.2V
1 TTL Gate and CL = 100 pF

0.6V

tT

=

Output Low Current
Output Low Voltage

Output High Current
Output High Voltage

VS.

VS.

10

.I

-10

=I.

-Vee 4.5V
TA = 25°C

V

V

§. -8
z

...

::>

u
:z:

i"'- r......

-6

...::> -,

.

........

r...... ......

I-

::>
0

/

]

/

-2

o
0.1

0.3

0.2

0.4

0.5

2.4

VOL. OUTPUT LOW VOLTAGE (V)

2.6

2.8

3.0

3.2

3.4

VOH. OUTPUT HIGH VOLTAGE (V)

Power Supply Current
V cc Supply Voltage

Power Supply Current
Ambient Temperature

VS.

VS.

10

i"'- .......

:z:

/

i/

Ve~
= 4~5V
TA = 25°C

!2

V

o

r---. . . .

W
II:
II:

/

o

r-...

;(

/

Hl=2~C 1 1
OUTPUTS OPEN

,,-

,.

-

l- I-'"

;(

§.
z

...
W

II:
II:

::>

u

.::;
.,
::>

II:
W

;;:
0

0-

o

li

4

0

0

20

40

80

TA. AMBIENT TEMPERATURE

Vee. SUPPLY VOLTAGE (V)

FUJITSU
8·5

80

eCI

100

MB83256·25

Typical Characteristics
Curves
(Continued)

Address Access Time
vs. Vcc Power Supply Voltage
300

Power Supply Current
vs. Cycle Time
20

T~Cl == 2~'C
I
100 pF

!w
::;

"!z

1=
II)
II)

w
a:
a:

w

.
()

II)
II)

w

\

=>

()

\

0

200

a:

..
0
0

~
Q.

1"-

10

Q.

=>

II)

........


Q.

60

II)

I-

=>

40

Q.

l-

=>

0

l-

=>

~

20

0

~

20

Vee, SUPPLY VOLTAGE (V)

Vee, SUPPLY VOLTAGE (V)

Address Access Time
Load Capacitance

Address Access Time
vs. Ambient Temperature

VS.

300

300

vdc== l.sv

!w

TA

::;

!w

25"C

-

~~c==1~05~F

::;

1=

1=

II)

II)
II)

rn
w

w

.
31
.8

..

()
()

()

0

II)

200
m
a:

- --

.8
0
0

~

:;

100

o

200

a:
0
0

~

b--

:;

100

100

200

CL, LOAD CAPACITANCE (pE)

8·6

o

- -

20

r-

40

fo-

~

60

80

TA, AMBIENT TEMPERATURE eC)

100

MB83256·25

Package Dimensions
Dimensions in inches
(millimeters)

28·Lead Plastic Dual In· Line Package
(Case No.: DIP.28P.M02J

I

.533 (13.64)

INDEX

1~=====~==::::;Z::.=====::jIJ4'~
~I

1.389 (35.28)
U15 (35.94)

=,r~
~

"97(5'00)MAX'

.100 (2.54)
TYP

I.. I ~ 1.,059

.118 (3.00) MIN.

(1.50)
.080 (2.03)

--11 ...

8·7

015 (0.38)
.023 (0.58)

.020 (0.51) MIN.

Preliminary

FUJITSU

MOS Memories
•

MB83512·15
CMOS S24,288-Bit
Mask-Programmable
Read Only Memory

Description
The Fujitsu MB83512 is a CMOS Si-gate mask-programmable
static read only memory organized as 65,536 words by 8-bits .
The MB83512 has TIL-compatible I/O and TRI-state output level
with fully-static operation (i.e. no need of clock signal) and single
+5V power supply. The device is designed for applications such as
character generator or program storage which require large memory capacity and high-speed/low-power operation.
The MB83512 is packaged in a 28-pin dual-in-line package and its
pin-out is compatible with standard 28-pin EPROM.

Features
• 65,536 words x 8-bits
organization
• Fast access time:
150 ns max.
• Complete static operation:
No clock required
• ALL inputs and outputs are
TTL compatible
• Three-state outputs

• +5V supply voltage
• Low power consumption:
220 mW (Operation)
16.5 mW (Standby, TTL
input level)
• 275 p.W (Standby, CMOS
input level)
• Standard 28-pin DIP

This device contains circuitry to
protect the inputs against damage

due to high static voltages or alec-tric fields. However, it fs advised

that normal precautions be taken to
avoid application of any vohage
higher than maximum rated voltages to this impedance circuit.

8-8

'"-

•
....

r-

I-

MB83512·15

MB83512·15 Block Diagram
and Pin Assignment

A15

A,

E'CE

65,536 x 8-BITS
ROM CELL ARRAY

A,

CE

LOGIC

A,
A7

A,
A,
AIO
Al1

Vee

A12

A14

A7

A13

A,

A,

A,

A.

~

A"

A,

CE

A,

AIO

A,

A12

A13
A16

A,

0,

0,

07

Vee - - . .

0,

Oe

Vss -----

0,

0,

Vss

0,

0102030405 06 07 Oe
TRUTH TABLE

OE

MODE

OUTPUT

POWER
CONSUMPTION MODE

H

X

NON·SELECTED

HIGHoZ

STANDBY

L

H

NON·SELECTED

HIGH-Z

AcnVE

L

L

SELECTED

OUTPUT

AcnVE

E

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Storage temperature range

TSTG

-45 to +125

°C

Temperature under bias

T BIAS

-10 to +85

°C

Supply voltage

Vee

-0.3 to +7.0

V

Input voltage

VIN

-0.5 to Vee + 0.5

V

Output voltage

VOUT

-0.5 to Vee + 0.5

V

Note: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detaited in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Capacitance
(TA = 25°C, f = 1 MHz)

Symbol

Parameter
Output Capacitance (VOUT
Input Capacitance (VIN

= OV)

= OV)

Min

Max

Unit

COUT

Typ

10

pF

CIN

7

pF

Recommended Operating
Conditions
(Reference to GND)

Parameter

Symbol

Min

Typ

Max

Supply voltage

Vee

4.5

5.0

5.5

Unit
V

Input low voltage

VIL

-0.3

0.8

V

Input high voltage

VIH

2.2

Vee + 0.3

V

Ambient temperature

TA

0

70

°C

FUJITSU

8-9

MB83512·15

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Test Conditions

Standby supply current

E

~

V 1H

E

~

V cc , V 1N

Active supply current

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Input leakage current

V 1N
E

~

~

GND or Vcc

Output high voltage

IOH

~

IOL

~

ISB2

50

I"A

Icc

40

rnA

III

-10

10

I"A

-10

10

I"A

- 4OO l"A

VOH

2.4

2.1 rnA

VOL

0.4

V

~

V 1H

Parameter

Symbol

Address access time (E ~ OE ~ V 1L)

t ACC

~

Unit
rnA

ILO

OV to Vcc

V 1H , or OE

Output low voltage

3

ISB1
~

E = VIL, minimum cycle

Output leakage current

MB83512·15
Min
Max

Symbol

V

MB83512·15
Min
Typ

Max

Unit

150

ns
ns

tE

150

Output enable access time'1

tOE

80

ns

Output disable time'2

TDF

60

ns

Output hold time

tOH

Chip enable access time (OE

Notes: *1

V 1L )

ns

0

Ci'E may be delayed up to (lACe - tOE) after the falling edge of E without impact on tACe·
BE or E, whichever occurs earlier.

*2 'OF is specified from

Timing Diagram

ADDRESS

(

)
_'CE_

-.

\

/
...-tOE*1.

\
•

/
....--tOF· 2 ...........

tA.ce

1111,

\\\\.)

DATA VALID

BE MAY BE DELAYED UP TO (lAce - toe) AFTER THE FALLING EDGE OF E
WITHOUT IMPACT ON lAce'2 tOF IS SPECIFIED FROM OE OR E, WHICHEVER OCCURS EARLIER.

NOTES: '1

8·10

----

- . - tOH

tOF*2

MB83512·15

AC Test Conditions
Input Pulse Levels:
Input Pulse Rise and Fall Time:
Timing Reference Levels:
Output Load:

Package Dimensions
Dimensions in inches
(millimeters)

0.6V to 2.4V
= 5 ns
Input: V IL = O.BV, V IH = 2.2V
Output: VOL = O.BV, VOH = 2.2V
1 TTL Gate and CL = 100 pF

tT

28·Lead Plastic Dual In·Line Package
(Case No.: DIP.28P·M02)

I

.533 (13.54)

INDEX

1~=====::S:;::::::==;L======lIJ4'05)
~1.~

____________~1·738~9~(3~5~.2~~~
1.415 (35.94)

8·11

___________

~
.014 (0.36)

FUJITSU

MOS Memories
•

MB831000·15, MB831000·20
CMOS 1M-Bit Mask-Programmable
Read Only Memory

Description

_1.1

The Fujitsu MBM MB831000 is a CMOS Silicon gate Maskprogrammable static read only memory organized as 131,072
by 8- bits.
The MB831000 has TTL-compatible I/O and TRI-STATE output
level with fully-static operation (i.e., no need of clock signal) and
single + 5V power supply. The device is designed for applications
such as character generator or program storage which require
large memory capacity, high-speed and low-power operation.

l - I""""
~

r- l -

I""""

r- I~ Isti : I lac Ira IuL

Features
•
•
•
•
•
•

131,072 words x 8-blts
organization
Access time:
150 ns (MB831 000-15)
200 ns (MB831000-20)
Completely static operation:
No clock required
All inputs and outputs are
TTL compatible
TRI-state output
Single +5V supply. ±10%
tolerance

•

•

Low Power:
220 mW max. (Active)
16.5 mW max. (Standby.
TTL Input level)
275 iJ-W max. (Standby.
CMOS Input level)
Standard 28-pln DIP

This device contains circuitry to
protect the inputs against damage
due to high static voltages or elec-

tric fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

8-12

I""""

r- r-

MB831000·15
MB831000·20

MB831000 Block Diagram
and Pin Assignment

A,
A,
A,

.. E

A,
A.
A,
A,
A,

131.072 x 8·BITS

E

ROM CELL ARRAY

LOGIC

A"

Vee

A12

A14

A,

A13

A.

A,

As

A,

A,

Al1

A,
A,

A,

A,.

A"
Au

A2

AlO

A,

A"
A"
A"

AO

Vee
Vss

0,

0,

0,

02

O.

0,

Os

VSS

0,

TRUTH TABLE
E

Mode

Output

Power Dissipation Mode

H

Not selected

Hlgl1-2:

Standby

L

Selected

Output

Active

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Supply voltage

Vee

-0.3 to +7.0

V
V

Input voltage

V IN

-0.5 to Vee + 0.5

Output voltage

V OUT

-0.5 to Vee + 0.5

V

Operating temperature

TBIAS

-10 to +85

'C

Storage temperature range
Referenced to GND

TSTG

-45 to +125

'C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Recommended Operating
Conditions
(Referenced to GND)

Capacitance
(TA = 25'C, f = 1 MHz)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.5

5.0

5.5

V

Input low voltage

V IL

-0.3

0.8

V

Input high voltage

VIH

2.2

Vee + 0.3

V

Ambient temperature

TA

0

70

'C

Parameter

Symbol

Output capacitance (VOUT
Input capacitance (VIN

=

OV)

= OV)

FUJITSU

8-13

Max

Unit

COUT

Min

Typ

10

pF

CIN

7

pF

MB831000·15
MB831000·20

DC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Active supply current

ICC

Min

Standby supply current

Unit

Test Condition

mA

E=

3

mA

= VIH
E = Vee, VIN = GND or Vee
VIN = 0 to Vee
E = V IH
10H = -400 fJ-A
10L = 2.1 mA

50

fJ-A

Input leakage current

III

-10

10

fJ-A

Output leakage current

ILiIO

-10

10

fJ-A

0.4

V

Output high voltage
Output low voltage

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Max

40

V

2.4
VOL

MB831000·15
Min
Max

VIL, minimum cycle

E

MB831000·20
Min
Max

Parameter

Symbol

Address access time (E = V IL)

t Aee

150

200

ns

Chip enable access time

tE

150

200

ns

Output disable time

tDF

60

60

ns

Output hold time

IoH

0

0

Timing Diagram

ADDRESS
tCE

0,-0.

tOH

VALID

AC Test Condition
Input pulse level:
0.6 to 2.4V
Input pulse rise and fall time: tT = 10 ns
Timing reference levels:
Input: VIL = 0.8 V, VIH = 2.2 V
Output: VOL = 0.8 V, VOH = 2.2 V
Output load:
1 TTL Gate and 100 pF

8·14

Unit

ns

MB831000·15
MB831000·20

MB831000 ROM Code Data
Input Formats.

Fujitsu requires customers to
provide ROM Code Data in the
form of programmed EPROMs or
Magnetic Tapes using Fujitsu's
computer system. Fujitsu then
will fabricate the MASKs utilizing
the DATA provided from the
customer.

• 256K EPROM:
When the customer releases his
Mask ROM Data in the form of
EPROMs, he should use 4 pcs of
MBM27C256 or equivalent and
program data of 4 address blocks
(Address 0 to 32K, 32K to 64K,
64K to 96K and 96K to 128K) of
MB831000 to each MBM27C256
EPROM.

(Address 0 to 16K, 16K to 32K,
32K to 48K, 48K to 64K, 64K to
80K, 80K to 96K, 96K to 112K
and 112K to 128K) of MB831000
to each MBM27128 EPROM.
Fujitsu requires 3 sets, total 24
pcs, of such programmed
EPROMs. (Two sets, total 16
pcs, are acceptable.)

Mask ROM Code Data Release

by EPROMs:
• t28K EPROM:
When the customer releases his
Mask ROM Data in the form of
EPROMs, he should use 8 pcs of
MBM27128 or equivalent and
program data of 8 address blocks

In addition to the programmed
sets, Fujitsu requires an additional set of blank EPROMs (8
pcs) for supplying customer ROM
Data Code verification.

In addition to the programmed
sets, Fujitsu requires an additional set of blank EPROMs (4
pcs) for supplying customer ROM
Data Code verification.

Msa
A16

A1S

A14

A13

Fujitsu requires 3 sets, total 12
pcs, of such programmed
EPROMs. (Two sets, total 8 pcs,
are acceptable.)

I I MI~I~IMlulululul~1

I A12 I A11

Al0

0

0

0

MBM27128 (No.1:

0

0

1

MBM27128 (No.2:

16 K to

0

1

0

MBM27128 (No.3:

32 K to

48 K)

0

1

1

MBM27128 (No.4:

48 K to

64 K)

0

LSB
AO

to 16 K)
32 K)

1

0

0

MBM27128 (No.5:

64 K to

80 K)

1

0

1

MBM27128 (No.6:

80 K to

96 K)

1

1

0

MBM27128 (No.7:

96 K to 112 K)

1

1

1

MBM27128 (No.8: 112 K to 128 K)

A16

A1S

A14

0

0

MBM27C256 (No.1:

0

1

MBM27C256 (No.2: 32 K to 64 K)

1

0

MBM27C256 (No.3: 64 K to

1

1

MBM27C256 (No.4: 96 K to 128 K)

Lsa

MSB

I A13 I A12 I All I Al0 I

Mask ROM Code Data Release

by Magnetic Tapes
When the customer releases his
Mask ROM Code Data in the
form of Magnetic Tapes (MT), he
should use tapes that can be
used on IBM compatible equipment and meet the following
requirements.

MI~I~IMlulululul~1

• Physical Requirements:
1 Length: 2400 feet, 1200
feet, or 600 feet
2 Width: V, inch
3 Track: 9 tracks
4 Density: 800 BPI or 1600
BPI

0

AO

to 32 K)

96 K)

• MT Format:
1 Label: No tape mark on the
header of tape
2 Record Size: 80 bytes/record
3 Block Size: Single record/
block
4 File: Single file/volume
5 Code Used: EBCDIC code

2400/1200/600 feet

!

TRACKS

•

BOT

DATA

DATA

SLOCK

BLOCK

-----

--------

-----

DATA

DATA

BLOCK

BLOCK

TM

TM

EOT

NOTE: BOT: BEGINNING OF TAPE
EeT: END OF TAPE
TM : TAPE MARK

~

FUJITSU

8·15

MB831000·15
MB831000·20

MB831000 ROM Code Data
Input Formats:
(Continued)

• Data Block Fonnal:
9

1

ROW
NUMBER

NUMBER
OF BYTE

15

10

19

16

20

68

67

72

73

80

UNDEFINED
FIELD

ADDRESS
FIELD
(1 HEAD
ADDRESS)

UNDEFINED
FIELD

(16 WORDS)

UNDEFINED
FIELD

SEQUENCE

9 BYTES

6 BYTES

4 BYTES

48 BYTES

5 BYTES

8 BYTES

DATA FIELD

NOTE: 1 BYTE/ROW

Undefined Field (Row 1 9/Row 16 - 19/Row 68 - 72):
In this field, blanks (iii) should be
recorded.
Address Field (RQW 10 - 15):

recorded in the form of a fivedigit hexadecimal number following a symbol "#". The COrre-

In the address field, the header
address of the 16·word data that
follow the address field should be

spondence of actual binary
address to this hex address is
shown in the following example.

LSB

MSB
ADDRESS BIT

A16

BINARY ADDRESS

0

HEX ADDRESS

0

~ll~IMIMI~IMIMIMIMIMI~IM

A151 A141 A131 A12
01 0

I I
1

1

1

I

3

01111

RECORDED FORM

In this field, 16-word data with 16
successive addresses should be

DB

DATA BIT

1

0

1 1 10J

I

9

1

recorded in the form of two-digit
hexadecimal numbers followed
by a blank (iii). (The header data
is for the address recorded in the

I
I

HEX DATA

07
1

I
I

06
1

I
I

o

il

1 0

2

Sequence Number Field (Row

73 - 80)
In this field, the sequence number of each record (data block)

address field.) The correspondence of actual binary data to this
hex data is shown in the following example.

05

04

1

0

I
I

03
0

I
I

02
1

I
I

01
0

2

F
F2~

RECORDED DATA

should be recorded in the form of
an eight-digit decimal number,
which must be counted up by
tens. All digits to the left of the

ADDRESS

10

1 0

#03892

Data Field (Row 20 - 67):

BINARY DATA

1 1

I

B

most significant dig~ should be
zeros, not blanks. Refer to the
following example.

SEQUENCE NO.

15

#03892

8-16

MB831000·15
MB831000·20

Package Dimensions
Dimensions in
inches (millimeters)

28·L.ad Plastic Dual In· Line Package (Case No•• DIP.28p.M02)

l

INDEX

r~-

.533(13.54)

.590(14.99)

1~=====::3~==;Z======~IJ4.05)
.1

.610(15.49)

1.389(35.28)
1.415(35.94)

8·17

FUJITSU

MOS Memories
•

MB831124·35
1M-BIT (131 ,072x8) CMOS
Read Only Memory

Description
The Fujitsu MB831124 is a CMOS Si-gate mask-programmable
static read only memory organized as 131,072 words by 8 bits.
The MB831124 has TTL-compatible I/O and 3-state output level
with CE clocked operation and single +5V power supply. The
MB831124 is designed for applications such as character generator or program storage which require large memory capacity, highspeed and low power operation .

r-

The package for the MB831124 is a standard 28-pin dual-in-line
package.

•

cr-

Features

• Organization:
• Single +5V supply, ±10%
131,072 words x 8 bits
tolerance
• Fast access time:
• Power consumption:
350 ns max. (MB831124-35)
138 mW (Operation)
5.5 mW (Standby, TTL input
• Fast cycle time:
460 ns max. (MB831124-35)
level)
0.165 mW (Standby, CMOS
• Clocked control (CE) periphery
Input level)
• TTL compatible inputs!
outputs
• Standard 28-pin DIP
• Three-state outputs

This device contains circuitry to
protect the Inputs against damage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to

avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

8-18

c-

PII ~.ti C

ff-

MB831124·35

MB831124
Block Diagram
and Pin Assignment
Ao
A,
A,

Ao
A.
A,

ADDRESS

ROW

BUFFER

DECODER

A,
A,

LATCH

...
A,
A,.
A11
A12
A'3
A,.
A"
A,.
VCC-

VSS-

Absolute Maximum Ratings
(See Note)

Rating

Unit

Supply Voltage

V

Input Voltage on Any Pin
with respect to GND

V

Output Voltage on Any Pin
with respect to GND

V

·c
·c

Temperature under Bias
Storage Temperature

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

Recommended Operating
Conditions
(Referenced to GND)

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

Input Low Voltage

V 1L

-0.3

0.8

V

Input High Voltage

V 1H

2.2

Vee +0.3

V

Ambient Temperature

TA

0

70

·C

FUJITSU
8·19

MB831124.35

Capacitance
(TA = 25'C, f = MHz)

Parameter

Symbol

Max

Unit

Input Capacitance (VIN = 0 V)

CIN

Typ

10

pF

Output Capacitance (VOUT = 0 V)

COUT

15

pF

DC Characteristics
(Recommended operating
conditions unless
otherwise noted.)

Parameter

Test Condition

Symbol

Min

Max

Unit

Input Leakage Current

III

-10

10

/LA

ILO

-10

Standby Supply Current

= OVtoVcc
CE = VIH ' VOUT = 0 V to Vcc
tCYC = 460 ns, tCE = 350 ns
CE = VIH

Standby Supply Current

Vcc -0.2",CE",Vcc +0.2

V IN

Output Leakage Current
Active Supply Current

Output Low Voltage

IOL

Output High Voltage

IOH

ICCl

/LA
mA

30

/LA

0.4

V

mA

IS51
ISB2

= 2.1 mA
= -400/LA

10
25

VOL
VOH

V

2.4

AC Characteristics
(Recommended operating
conditions unless
otherwise noted.)

Parameters

Symbol

MB831124·35
Min
Max

Unit

Cycle Time

tCYC

460

ns

Chip Enable
Pulse Width

tCE

350

ns

Address Access
Time

tACC

350

ns

Output Disable
Time

ioFF

80

ns

Address Setup
Time

t AS

0

ns

Address Hold
Time

tAH

80

ns

Chip Enable
Off Time

tcc

100

ns

FUJITSU
8·20

Conditions

tCYC = tCE + Icc + 2tT
IT = 5 ns

MB831124·35

Timing Diagram
t-----------ICyC--------~__I

I-----ICE-----I
CH'P ENABLE CE ----~-.L

ICC
IAH

Aoto
ADDRESS A16

g! to

OUTPUT

H'GH-Z

-=«i....,;q..__V_AL_'O_'O_"3_--=.;H:;;:'GH::.:_Z~_

AC Test Conditions
Input Pulse Levels:
Input Pulse Rise and Fall TImes:
Timing Reference Levels:
Output Load:

MB831124 ROM Code Data
Input Method

Mask ROM Code Data Release
by EPROMs:
128K EPROM:
When the customer releases his
Mask ROM Data in the form of
EPROMs, he should use eight
MBM27128 or equivalent and

0.6 to 2.4 V
5 ns
Input: V'L = 0.8 V, V'H = 2.2 V
Output: VOL = 0.8 V, VOH = 2.2 V
1 TTL Gate and C L = 100 pF

In addition to the programmed
sets, Fujitsu requires an
additional set of blank EPROMs
(8 pes) for supplying customer
ROM Data Code verification.

program data of 8 address blocks
(Address 0 to 16 K, 16 K to 32 K,
32 K to 48 K, 48 K to 64 K, 64 K
to 80 K, 80 K to 96 K, 96 K to
112 K and 112 K to 128 K) of the
MB831124 to each MBM27128
EPROM. Fujitsu requires 3 sets,
total 24 pes, of such programmed
EPROMs. (Two sets, total 16
pcs, are acceptable.)

MSB

LSB

A16

AIS

A14

A13

I A12 I AI1 I Al0 I

A9

I

AS

I

A7

I

I

AS
0

AS

I

A4

0

0

0

MBM27128 (No.1:

0

0

1

MBM27128 (No.2:

0

1

0

MBM27128 (No.3:

32 K to 48 K)

0

1

1

MBM27128 (No.4:

48 KIa 64 K)

1

0

0

MBM27128 (No.5:

64 K to 80 K)

1

0

1

MBM27128 (No.6:

80 K to 96 K)
96 K to 112 K)

10

16 K)

16K to 32 K)

1

1

0

MBM27128 (No.7:

1

1

1

MBM27128 (No.8: 112 K to 128 K)

FUJITSU
8·21

I

A3

I

A2

I

AI

I

AO

MB831124-35

256K EPROM:

64 K to 96 K and 96 K to 128 K)
of the MB831124 to each
MBM27C256 EPROM.

When the customer releases his
Mask ROM Data in the form of
EPROMs, he should use four
MBM27C256 or equivalent and
program data of 4 address blocks
(Address 0 to 32 K, 32 K to 64 K,

In addition to the progra:mmed
sets, Fujitsu requires an
additional set of blank EPROMs
(4 pcs) for supplying customer
ROM Data Code verification.

Fujitsu requires 3 sets, total 12
pcs, of such programmed
EPROMs. (Two sets, total 8 pes,
are acceptable.)

MSB

LSB

I

I

I

I

I

I

I

I

I

I

A1S

A1S

0

0

MBM27C256 (No.1;

0

1

MBM27C256 (No.2: 32 K to 64 K)

1

0

MBM27C256 (No.3: 64 K to 96 K)

1

1

MBM27C256 (No.4: 96 K to 128 K)

Al.

A13

A12

Al1

Mask ROM Code Data Release

•

by Magnetic Tapes:
When the customer releases his
Mask ROM Code Data in the
form of Magnetic Tapes (Mn, he
should use tapes that can be
used on IBM compatible equipment and meet the following
requirements.

Al0

A9

A8

A7

AS
0

Physical Requirements:
1 Length: 2400 feet,
1200 feet, or 600 feet
2 Width: V2 inch
3 Track: 9 tracks
4 Density: 800 BPI or
1600 BPI

AS

A.

I

A3

I

A2

I

Al

I

AO

to 32 K)

•

MT Format:
1 Label: No tape mark on the
header of tape
2 Record Size: 80 bytes/
record
3 Block Size: Single record/
block
4 File: Single file/volume
5 Code Used: EBCDIC code

2400112001600 _

!

TAA~KS

BDT

DATA
eLoCK

DATA
BLOCK

---------- - ----- ----

~
NOTE: BOT: BEGINNING OF TAPE
EOT: END OF TAPE
TM : TAPE MARK

FUJITSU
8-22

DATA
BLOCK

DATA
BLOCK

TM

TM

EDT

MB831124·35

•

Data Block Format:

ROW
NUMBER

1

NUMBER
OF BYTE

9

10

15

16

19

20

67

80

73

72

66

UNDEFINED
FIELD

ADDRESS
FIELD
(1 HEAD
ADDRESS)

UNDEFINED
FIELD

DATA FIELD
(16 WORDS)

UNDEFINED
FIELD

SEQUENCE

9 BYTES

6 BYTES

4 BYTES

49 BYTES

5 BYTES

8 BYTES

NOTE: 1 BYTE/ROW

Undeflnad Field (Row 1-91
RQW 16-19/Row 68-72):
In this field, blanks
recorded.

(}J)

should be

be recorded in the form of a fivedigit hexadecimal number
following a symbol "#". The

Address Field (Row 10-15):
In the address field, the header
address of the 16-word data that
follows the address field should

corresponding binary address to
this hex address is shown in the
following example.

MSB
ADDRESS BIT

LSB

A161 A1sI A141 A131 A121 All

BINARY ADDRESS

010

HEX ADDRESS

oI

lol

11

1 [1

I

3

I Al0 I A9 I AB I A7 I A6 I AS I A4 I A3 I A2 I Al I AD
I o[ 1 L l 11 I ojo I 1 j ojol 1 [ 0
B
9
2
I
I

RECORDED FORM

#03892

Date Field (Row 20-67):

DATA BIT

DB

BINARY DATA

1

address field.) The corresponding
binary data to this hex data is
shown in the following example.

recorded in the form of two-digit
hexadecimal numbers followed
by a blank ~). (The header data
is for the address recorded in the

In this field, 16-word data with 16
successive addresses should be

07

1

I

HEX DATA

1

l

I
F

06
1

05

1

I

1

J
I
I

04
0

1
I

03
0

Sequence Number Field
(Row 73-80):
In this field, the sequence number of each record (data block)

1

I
I

01
0

2

should be recorded in the form of
an eight-digit decimal number,
which must be counted up by
tens. All digits to the left of the

most significant digit should be
zeros, not blanks. Refer to the
following example.

ADDRESS

SEQUENCE NO.
15

#03892

02

F2~

RECORDED DATA

10

I
I

I" n. T .. lmmnnmmnmn-l" ~ "I

FUJITSU
8-23

BO

73

00000010

MB831124-35

Package Dlmenalona
Dimensions In
inches (millimeters)

28·Lead Plaatlc Dual In-Line Package (Caae

NO.1

DIP.28P.M02)

I

.533(13.54)

INDEX

11====~==;;Z::::===llj4'O~
1.389(35.28)
1.415(35.94)

I

U]:'197(5.00)MAX

-f-l'
.02O(O.51)MIN

FUJITSU
8-24

118(3.QO)MIN

MBM10415AH ............................ 9-2
MBM10422A ............................. 9-8
MBM100422A ............................ 9-14
MBM10470A ............................. 9-20
MBM100470A ............................ 9-26
MBM10474A ............................. 9-31
MBM100474A ............................ 9-37
MBM1 0480 ............................... 9-43
MBM100480 ............................. 9-49
MBM10484 ............................... 9-55
MBM100484 ............................. 9-61
MBM10490 ............................... 9-67
MBM100490 ............................. 9-73
MB70801 ................................ 9-79
MB70802 ................................ 9-85
MB7700H Series .......................... 9-92
MBM93419 .............................. 9-101

Advanced Information
MBM10422A ............................. 9-105
MBM100422A ............................ 9-106
MBM10474A ............................. 9-107
MBM100474A ............................ 9-108
MBM10480A ............................. 9-109
MBM100480A •...........•............... 9-110
MBM10484A/100484A .................... 9-111
MBM10494/100494 ....................... 9-112

FUJITSU

MBMl0415AH

MICROELECTRONICS. INC.

ECL l024·BIT BIPOLAR
RANDOM ACCESS lVIEMORY
DESCRIPTION
The Fujitsu MBM10415AH is a fully decoded 1024-bit ECL readl
write random access memory
designed for high-speed scratch
pad, control and buffer storage
applications. It is organized as
1024 words by one bit, and
features on-chip voltage compensation for improved noise margin.
The MBM10415AH offers extremely small cell and chip sizes;
realized through the use of
Fujitsu's patented DOPOS

(Doped Polysilicon), as well as
lOP (Isolation by Oxide and Polysilicon) processing. As a result,
very fast access time with high
yields and outstanding device
reliability are achieved in volume
production.
Operation for the MBM10415AH
is specified over a temperature
range of from O·C to 75·C (ambient). It also features frit-sealed 16pin dual in-line packaging, and is
fully compatible with industry-standard 10K-series ECL families.

CERAMIC PACKAGE
DIP·16C·F01

FEATURES
• 1024 words x 1_-bit organization
• On·chip voltage compensation
for Improved noise margin
• Fully compatible with Industry·
standard 10K·serles ECL
families
• Address access time:
MBM10415AH: 20 ns Max.

• Chip select access time:
MBM10415AH: 8 ns Max•
• Open emitter output for ease
of memory expansion
• Low power dissipation of
0.5mWlbit
• DOPOS and .lOP processing
• Pin compatible with
F10415 and MCM10146

PIN ASSIGNMENT

MBMl0415AH
BLOCK DIAGRAM

Q

Vcc·

AO

0

AI

S

A2

Vii

A3

Ag

A4

AS

A5

A7

VEE

A6

'Vec grounded

TRUTBTABLE

32x 32
MEMORY CELL ARRAY

INPUT

S

W

H
L
L

X
L
L
H

L

DIN
X
L
H
X

H= HIGH VOLTAGE LEVEL
L= LOW VOLTAGE LEVEL
X=DON"T CARE

s~r--.....,

W
D~1--_--'

Q

9-2

OUTPUT

MODE

L
L

DISABLED
WRITE"L"
WRITE"H"
READ

L
DOUT

MBMl0415AH

ABSOLUTE MAXIMUM: RATINGS (See Note)
Rating

Symbol

Value

Unit

VEE Pin Potential to Ground Pin (Vee)
Input Voltage
Output Current (DC, Output High)
Temperature Under Bias
Storage Temperature

VEE
VIN
lOUT
TA

+0.5 to -7.0
+0.5 to VEe

-30

V
V
mA

-55 to +125
-65 to +150

'c
'c

Note:

TSTG

Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed In the

operational sections of this data sheet. Small geometry bipolar Integrated circuits are occasionally susceptible to damage from static voltages or electric fields. It is
therefore advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this device.

GUARANTEED OPERATING CONDmONS
(Referenced to Vee)
Parameter

Symbol

Min

Typ

Max

Supply Voltage

Vee

-5.46

-5.2

-4.94

Unit

Ambient Temperature

V

O'C to + 75'C

CAPACITANCE
Parameter

Symbol

Input Pin Capacitance

CIN

Output Pin Capacitance

COUT

Min

Typ

Max

Unit

-

4
7

5
8

pF
pF

DC CHARACTERISTICS
(Vee = OV, VEE = -5.2V, Output load = 500 to -2.0V and Airflow

2:

Typ

Max

Unit

TA

VOH

-1000
- 960
- 900

-

- 840
- 810
- 720

mV

O'C
25'C
75'C

Output Low Voltage
(VIN =VIH max. or VIL min.)

VOL

-1870
-1850
-1830

-

-1665
-1650
-1625

mV

O'C
25'C
75'C

Output High Voltage
(VIN ;: VIH min. or VIL max.)

VOHC

-1020
980
- 920

-

mV

O'C
25'C
75'C

Output Low Voltage
(VIN VIH min. or VIL max.)

VOLC

-

-

-1645
-1630
-1605

mV

O'C
25'C
75'C

Input High Voltage
(Guaranteed Input Voltage High for All Inputs)

VIH

-1145
-1105
-1045

-

- 840
- 810
- 720

mV

O'C
25'C
75'C

Input Low Voltage
(Guaranteed Input Voltage Low for All Inputs)

VIL

-1870
-1850
-1830

-

-1490
-1475
-1450

mV

O'C
25'C
75'C

220

p.A

O' to 75'C

-

p.A

O' to 75'C

p.A

O' to 75'C

mA

75'C
O'C

Parameter
Output High Voltage
(VIN =VIH max. or VIL min.)

=

Input High Current (VIN

=VIH max.)

Input Low Current (V IN = VIL min.)
S Input LowCurrent (VIN

=VIL min.)

Power Supply Current
(All Inputs and Outputs Open)

Symbol

2.5 m/s unless otherwise noted.)
Min

-

IIH

-

IlL

-50

IlL

0.5

lEe

-125
-150,

9·3

-

-

170

-

MBMI0415AH
AC CHARACTERISTICS
(Full Guaranteed Operating Ranges, Output Load = 500 to -2.0V and 30pf to GND and Airflow
otherwise noted.)

~

2.5 mls unless

AC TEST CONDmONS
GND
-0.9V-

-

80%

/

1\

-1.7V-----J1
----.. tr

~

-4---

20%

t, .......-

t, = t, = 2.5ns typ
Output Load: RL = SOil
CL = 30pF
(including jig and stray capacitance)

NOTE: All timing measurements referenced to 50% input levels.

READ CYCLE
Parameter

Symbol

Address Access Time
Chip Select Access Time
Chip Select Recovery Time

tAA
tAC
tRB

MBM10415AH
Typ
Max

13
5
5

20

8
8

Unit

ns
ns
ns

READ CYCLE

ADDRESSES

V,H MIN

Q

Q

9-4

V ,L MAX

MBMI0415AH
WRITE CYCLE
MBM10415AH
Parameter

Symbol

Write Pulse Width
Write Disable Time
Write Recovery Time
Address Set Up Time
Chip Select Set Up Time
Data Set Up Time
1--7-Address Hold Time
Chip Select Hold Time
Data Hold Time

Unit

tww
tws
tWR
tSA
tsc
tso
tHA
tHC
tHO

Min

Typ

14

9
5
5
3
0
0
0
0
0

5
4
4
3
4
4

Max

-

os
ns
os
ns
ns
ns
ns
os
ns

10
10
-

-

WRITE CYCLE
\

7"-

-~

j~
1\

-

ADDRESS

~~

V

D

J~

-

-

tso

-

-'

--------- -----

tsc

\

-

1\
t-

7!=:--tHAtww

-tsA

Q

tHO

tws

tHC-

/

V1LMAX

-

V 1H MIN

I-tWR-

RISE TIME AND FALL TIME
Parameter

Symbol

Min

Output Rise Time
Output Fall Time

tr
tf

-

9-5

MBM10415AH
Typ

Max

Unit

5
5

-

ns
ns

MBMl0415AH
APPlJCATIONS INFORMATION
·LARGE SYSTEM APPLICATION

16K WORDS x n BIT
MEMORY SYSTEM

...
:

------

ADDR_IUS

-------

W

~

~

...... ~W

I

i

~W

DIN~

a

[

i

~

a_

CH'P

eLECT

{~,,,-

...-- l..r-I -

At

f

i

~

a
L--

L--

L"."
~w

~

...

~

.......

I

a

i

U"IL

~

~w

P-

~w

a
L--

L--

... l-

~

...

~w

~W

~t

...t-

L

4.,.

DOCODE

A,a -

......

~

ENABLE

~

L"."
~w
[

I

L...- I -

~w
r

.......
a

ii

L--

~w

r

I

'INt-

a

~
1

~

0 ..

a
L--

W-

... t-

~

Vi

i

i

L--

L

w

11

a

DINt-

DINt-

a

L'a

r--? "

ao
a, •
ON:

5011

500

~5011

? -2."

9-6

MBMl0415AH

PACKAGE DIMENSIONS

Dimensions in Inches (millimeters)

16·LEAD CERAMIC (FRIT SEAL) DUAL IN·LINE PACKAGE
DIP·16C·F01

"--1 [~~]]j=
INDEX AREA

I

I

.780119.30)

.800120.321

9·7

FUJITSU

MBMI0422A·7

MICROELECTRONICS. INC.

ECL l024·BIT BIPOLAR
RANDOM ACCESS MEMORY
DESCRIPTION
The Fujitsu MBM10422A is a fully
decoded 1024-bit ECl read/write
random access memory designed
for high-speed scratch pad, control and buffer storage applications. This device is organized as
256 words by 4-bits and features
on-chip voltage compensation for
improved noise margin.
The MBM10422A offers extremely
small cell and chip size, realized
through the use of Fujitsu's patented DOPOS (Doped Polysilicon), as well as lOP-II (Isolation by

Oxide and Polysilicon), processing. As a result, very fast access
time with high yields and outstanding device reliability are achieved in volume production.
Operation for MBM10422A is
specified over a temperature
range of O'C to 75'C (TA for DIP,
TC for flat package). It features
cerdip 24-pin dual in-line and flat
packaging, and is fully compatible with industry standard 10Kseries ECl families.

CERDIP PACKAGE
Dlp·24C·C05

FEATURES
• 256 words x 4-bits organization
• On·chip voltage compensation
for improved noise margin
• Fully compatible with industry·
standard 10K-series Eel
families
• Address access time: 7ns max.

FLAT PACKAGE
FPT·24C·C02

• Block select access time:
5nsmax.
• Open emlHer output for easy
memory expansion
• Power dissipation of 0.7 mWlblt
• DOPOS and IOp·1I processing
• Pin compatible with F10422

PIN ASSIGNMENT
VeCA

Vee

0,

MBMl0422 BLOCK DIAGRAM

.

'0-

ii,

ii_

o.

Q,

D~1

8,
0.

a.
0'.

0,

W

A_

As

A,

A.

A.

A7

A,

A"

VEE

·Vcc Grounded

I

I

I

MEMORY CELL ARRAY

Small geometry bipolar integrated circuits
are occasionally susceptible to damage from
stalic voltages or electric field, It is therefore
advised that normal precautions be taken to
avoid appliction of any voltage higher than
maximum rated voltages to this device.

TRUTH TABLE
INPUT

B

W

D,N

OUTPUT

MODE

H

X

L

DISABLED

L

L

L

WRITE'"H"

L

L

L

WRITE'"L"

L

H

X
H
L
X

DOUT

READ

H: HIGH VOLTAGE LEVEL
L:LOW VOLTAGE LEVEL
X: DON'T CARE

9-B

MBMI0422A·7
ABSOLUTE MAXIMUM RATINGS

(See Note)

Rating

Symbol

VEE Pin Potential to Ground Pin (Vee)
Input Voltage
Output Current (DC, Output High)
Temperature Under Bias
Storage Temperature
Note:

Value

Unit

Y,N

+0.5 to -7.0
+0.5 to VEE

lOUT
TA
TSTG

-55 to +125
-65 to +150

V
V
mA
·C
·C

VEE

-30

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed In the
operational sections of this data sheet Small geometry bipolar Integrated circuits are occasionally susceptible to damage from static voltages or electric fields. It Is
therefore advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this device.

GUARANTEED OPERATING CONDmONS
(Referenced to Vee)

Parameter

Symbol

Min

Typ

Max

Supply Voltage

VEE

-5.46

-5.2

-4.94

Unit

Temperature·

V

O·C to +75·C

• Ambient Temperature for DIP, case temperature for flat package

CAPACITANCE
Parameter
Input Pin Capacitance

Symbol
C'N

Output Pin CapaCitance

COUT

Typ
4
6

Min

-

Unit
pF
pF

Max
5
8

DC CHARACTERISTICS
(Vee=OV, VEE= -5.2V, Output load = 500 to -2.0V, TA=O·C to 75·C for DIP, Te=O·C to 75·C for flat package, and
Airflow = ~ 25 mIs, unless otherwise noted.)

Typ

Max

Unit

VOH

-1000
- 960
- 900

-

- 840
- 810
- 720

mV

Output Low Voltage
(V'N = V,H max. or V,l min.)

VOL

-1870
-1850
-1830

-

-1665
-1650
-1625

mV

O·C
25·C
75·C

Output High Voltage
(V'N = V,H min. or V,l max.)

VOHC

-1020
- 980
- 920

-

mV

O·C
25·C
75·C

Output Low Voltage
(V'N = V,H min. or V,l max.)

VOle

-

-

-1645
-1630
-1605

mV

O·C
25·C
75·C

Input High Voltage
(Guaranteed Input Voltage High for All Inputs)

V,H

-1145
-1105
-1045

-

- 840
- 810
- 720

mV

O·C
25·C
75·C

Input Low Voltage
(Guaranteed Input Voltage Low for All Inputs)

V,l

-1870
-1850
-1830

-

-1490
-1475
-1450

mV

O·C
25·C
75·C

Parameter
Output High Voltage
(V'N = V,H max. or V,l min.)

Input High Current (V'N = V,H

max.)

Symbol

Min

-

Input Low Current (V'N = V,l min.)

I'H
I,l

-50

B Input Low Current (V'N = V,l min.)

I,l

0.5

Power Supply Current
(All Inputs and Outputs Open)

lEE

-200

9-9

-

-

220

170

-

TA
O·C
25·C
75·C

p.A

O· to 75·C

p.A.

O· to 75·C

p.A

O· to 75·C

mA

O· to 75·C

lVIBMl0422A·7
FUNcnONALD~ON

Enable W input. With Wand B' held low, the
data at DIN is written Into the addressed location. To
read, W is held high, while B is held low. Data at
the addressed location is then transferred to DOUT
and read out non-inverted. Open emitter outputs are
provided to allow for maximum flexibility in output
wired-OR connection.

The Fujitsu MBM10422A-7 is fully decoded 1024-blt
read/write random access memory organized as 256
words by 4-bits. Memory cell selection Is achieved
by means of a 8-blt address designated Ao - A7. The
active low Block Select B input is provided for
memory expansion. The read and write operations
are controlled by the state of the active low Write

AC CHARACTERISTICS
Output Load

Airflow

=500 to

- 2.0V and 30pF to GN D, TA

= 22.5 mIs, unless otherwise noted.

=O·C to 75·C for 01 P, TC =O·C to 75·C for flat package, and

AC TEST CONDmONS
GND

-0.9V-

-1.7V---JI

-It,l-

t, = I, = 2.Sns Iyp

- 1'1-

Oulpul Load: RL = 5011
CL=30pF
(Including jig and slray capacilance)

NOTE: All timing measurements referenced to 50% Input levels.

READ CYCLE
Parameter
Address Access Time
Block Select Access Time
Block Select Recovery Time

Symbol
tAA
tAB
tRB

Min.

Typ

Max

Unit

-

5
2.5

7
4

2.5

4

ns
ns
ns

READ CYCLE TIMING DIAGRAMS
i

ADDRESS

Q

Q

9-10

MBMl.0422A·7

WRITECYCLE
Parameter

Symbol

Min

Typ

Max

Write Pulse Width

tww

5

tws
tWR

-

-

Write Disable Time
Write Recovery Time
Address Set Up Time

tSA

Block Select Set Up Time
Data Set Up Time
Address Hold Time

tSB
tso
t HA

Block Select Hold Time
Data Hold Time

tHB
tHO

1
1
1
1
1
1

-

4
8

-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

WRITE CYCLE

.,~

~Ir

J

1\

ii

~J t\.

Addresses

~~
/ 1\

~J If-

o

-- -, -.--

tSD

tHD

I....

I

7~tJiA-

--------Q

.

- t S A - ~tww- - tHB -

.

tSB

--

)'1- 50%

\

-~50%

tws

....

~tWR----

RISE TIME AND FALL TIME
Parameter

Symbol

Min

Typ

Max

Unit

Output Rise Time

t,

Output Fall Time

t,

-

1.5
1.5

-

ns
ns

9·11

MBMl0422A·7

TYPICAL CHARACTERISTICS CURVES
OUTPUT HIGH VOLTAGE

OUTPUT LOW VOLTAGE

vs AMBIENT TEMPERATURE

vs AMBIE'NT TEMPERATURE

SUPPLY CURRENT
vs AMBIENT TEMPERATURE

~ -0.7

~ -1.4

w

w

;(

"

:t

>!

:t

-0.9

f-

:::l

~ -1.0

-- -

~

f-

f5a:

0

>

;:
0

..J

:::l

o

:::l

-1. 6

u

100

-1. 7

i;l

~

0

0
0

>
20

40

60

-

I--.

r-

-

w
w

~

-1. 1

r-

15 0

a:

f-

ii'f-

:::l

:i
~

200

-1. 8

0
40
20
60
80
T A. AMBIENT TEMPERATURE ( C)

80

T A. AMBIENT TEMPERATURE ( C)

ADDRESS ACCESS TIME'

20

ADDRESS ACCESS TIME
vs SUPPL Y VOLTAGE

vs AMBIENT TEMPERATURE

40

60

80

T A. AMBIENT TEMPERATURE j"C)

WRITE PULSE WIDTH
vs AMBIENT TEMPERATURE

!w

I

::;

>=

V>
V>
W

r-- -

U
U

-

--

-11
processing
• Pin compatible with the
F100422

9-14

MBM100422A·7

MBM100422A
Block Diagram and Pin
Assignment

As

At

A7
D.

0,

B,

A,

0,

Ao

II.

A.

O.

A,

Ao

AO

VCC'

II:
W

c

A,

VeCA

0

u

w

256 x 4 BITS
MEMORY CELL ARRAY

0,

A7

w

II,

At

c
c

..

o.

As

*

II.

W

0,

D.

c
gj

A.

II:

A,

A,

VEE

I

'Vee GROUNDED

W

Dualln-Une Package
NOTE: DIP AND FLAT PACKAGE STYLES
CONFORM TO THE SAME PIN ASSIGNMENT.

TRUTH TABLE
INPUT
As
B

W

D,N

OUTPUT

H
L
L
L

X
L
L
H

X
H
L
X

L
L
L
OUT

MODE

W

,DISABLED
WRITEuH"
WRITE u!:,
READ

D.
0,

a.
""";''='-m'T+;':;:''--' 0,

H = HIGH VOLTAGE LEVEL
L = LOW VOLTAGE LEVEL
X = DON'T CARE

84 04VCC
01 81
Vee

Leadless Chip Carrier

Flatpack

Block Select (B) input is provided
for memory expansion. The read
and write operations are controlled by the state of the active
~w Wri~ Enable (W) il!Put. With
Wand B held low, the B data at
0'_4 is written into the addressed
location. To read, W is held high,

while B is held low. Data at the
addressed location is then transferred to OUT and read out noninverted. Open emitter outputs
are provided to allow for maximum flexibility in output wired-OR
connection.

Functl_al Description
The Fujitsu MBM100422A is a
fully decoded 1024-bit read/write
random access memory organized as 256 words by 4 bits.
Memory cell selection is achieved
by means of a S-bit address designated Ao-A7' The active low

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

VEE

+0.5 to -7.0

V

Input voltage

V,N

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

mA

Temperature under bias

TA

-55 to +125

'C

Storage Temperature

TSTG

-65 to +150

'C

VEE pin potential to ground pin

01cel

Note: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the concltions as detailed In the operational sections of this data sheet. Small geometry bipolar integrated circuits are occasionally susceptible
to damage from static voltages or electric fields. It Is therefore advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this device.

FUJITSU
9-15

MBM100422A·7

GUIII'anteed Operating
Condl--'
(Referenced to Veel

Parameter

Symbol

Min

Typ

Max

Unit

Ambl_t Templll'atura

Supply voltage

VEE

-5.7

-4.5

-4.2

V

O·C to +85·C

capacitance

DC Ch_cterlstlcs
(Vee = OV, VEE = -4.5V, Output
Load = SOO to -2.0V, TA = O·C
to 85·C and Airflow ... 2.5 mis,
unless otherwise noted.)

Parameter

Symbol

Input pin capacitance

C'N

4

pF

Output pin capacitance

COUT

6

pF

Typ

Max

Parameter

Symbol

Min

Max

Unit

VOH

-1025

-880

mV

Output low voltage
(V'N = V,H max. or V'L min.)

VOL

-1810

-1620

mV

Output high voltage
(V,N = V,H min. or V'L max.)

VoHe

-1035

Output low voltage
(V,N = V'H min. or V'L max.)

VOLe

Input high voltage
(Guaranteed input voltage high for all inputs)

V ,H

Input low voltage
(Guaranteed input voltage low for all inputs)

V,l

= V,H max.)
= V,l min.)
(V,N = V,l min.)

Typ

Unit

Output high voltage
(V'N = V,H max. or V'L min.)

Input high current (V'N

mV

-1165

-880

mV

-1810

-1475

mV

220

I'H
I'l

-50

B input low eurrent

I'l

0.5

lEE

-200

Parameter

mV
-1610

Input low current (V,N

Power supply current
(All inputs and outputs open)

AC Characteristics
(Vee = OV, VEE = -4.5V ±5%,
TA = O·C to 85·C, Output
Load = 500 to -2.0V and 30 pF
to GND, and Airflow ... 2.5 m/s;
unless otherwise noted.)

Min

Symbol

Min

Address access time

pA
p.A

170

p.A
mA

Typ

Max

Unit

5

7

ns

Block select access time

2.5

4

ns

Block select reeovery time

2.5

4

ns

Read Cycle

Ii

OUT

{:..-----.1]

9-16

ii

\"-----

M8M100422A·7·

Write Cycle
Parameter

Symbol

Min

Write pulse width

tw

5

Write disable time
Write recovery time

Typ

Max

Unit

tws

4

ns

tWR

8

ns

ns
ns

Address set up time

ns

Block select set up time

tWSBS

Data set up time

tWSD

ns

Address hold time

tWHA

ns

Block select hold time

tWHBS

ns
ns

Data hold time

Write Cycle
II

ADDRESSES

w
OUT

Rise Time and Fan Time
Parameter

Symbol

Output rise time

t,

2

ns

Output fall time

It

2

ns

Typ

Min

Max

AC Teet Conditions
GND

::~

Yee
OUT
VEE

~

tr = tf

RL

= 2.5ns typ

,

OUTPUT LOAD: RL = SOH
Oo01p.F

=

I

CL 30pF
(INCLUDING PROBE AND STRAY CAPACITANCE)

-2.0V
VEE

NOTE: ALL TIMING MEASUREMENTS REFERENCED TO 50% INPUT LEVELS.

FUJITSU
9-17

Unit

.BM100422A.7

PIIcu•• Dlm.nslons
Dimensions in inches
(millimeters)

240L.ad C.rdlp Dual In·Lln. Packa ••
DIP-24C·COS

n

R.025(O.64)
REF

.354(8.99)

.378(9.60)

1.180(29.97)
1.220(30.99)

.090(2.29)
.110(2.79)

24·L.ad C.rdlp (Frlt S.al) Flat Packa••
FPT·24C-C02

.371(9.42)
.389(9.88)

PIN #IIDENT

~

r

333(846)
.360(9:14)

~~
.371A2)
.389(9.66)

=-4r-

.,333(8.46)
14)
360
.

.05O(I.27)TYP . .

~.250(6.35)

-+- .0678(1.72)MAX
.010(0.25)
.020(0.51)

TYP

9·18

.004(0.10)
0.20)
.100(2.54)MAX

MBM100422A·7

Package Dimensions
Dimensions in Inches
(millimeters)

24·Pad Ceramic (Frit Seal) Leadless Chip Carrier
(Case No•• LCC·24C·F02)

'PIN NO.1 INDEX

I

n

.085(2.16)

R.012(0.30)TYP
(4 PLCS)

R.008(0.20)TVP
(24 PLCS)

.395(10.03)
.410(10.41)

.395(10.03)
.410(10.41)

D'105(2'67)MAX
.310(7.B7)TVP

'SHAPE OF PIN 1 INDEX, SUBJECT TO CHANGE WITHOUT NonCE

9·19

FUJITSU

Bipolar Memories
•

MBM10470A-10, MBM10470A-15, MBM10470A-20
4096-Bit Bipolar Eel Random
Access Memory

De.crlptlon
The Fujitsu MBM10470A is a fully decoded 4096-bit ECl read/write
random access memory designed for high-speed scratch pad, control and buffer storage applications. This device is organized as
4096 words by one bit, and it features on-chip voltage compensation for improved noise margin.
The MBM10470A offers extremely small cell and chip size, realized
through the use of Fujitsu's patented DOPOS (Doped Polysilicon),
as well as lOP-II (Isolation by Oxide and Polysilicon), processing.
As a result, very fast access time with high yields and outstanding
device reliability are achieved in volume production.
Operation for the MBM10470A is specified over a temperature
range of from 0' to 75'C (ambient). It also feature 1a-pin dual-inline oeramic packaging, and is fully compatible with industry-standard 10K-series ECl families.

Feature.
•

4096 words x 1 bit
organization
• On-chip voltage compenaatlon for improved noise
margin
• Fully compatible with
industry-standard
10K-series ECl families
• Addresa accesa time:
10 nsec. max.
(MBM10470A-10)
15 nsec. max.
(MBM10470A-15)
20 nsec. max.
(MBM10470A-20)

•

Chip aelect acceaa time:
6 naec. max.
(MBM10470A-10)
8 nsec. max.
(MBM10470A-15)
15 nsec. max_
(MBM10470A-20)
• Open emitter output for
ease of memory expanalon
• Low power dissipation for
0.22mW/bit
• DOPOS and lOP-II
proceSSing
• Pin compatible with the
F10470

Small geometry bipolar Integrated
circuits are occasionally susceptible
to damage from static voltages or
electric fields. It is therefore
advised that normal precautions be
taken to avoid application of any
voltage higher than maximum rated
voHages to this device.

9-20

MBM10470A-10
MBM10470A-15
MBM10470A-20

MBM10470A
Block DIagram
and Pin Assignment
WORD
DRIVER

OUT

Vee

Ao

D

A,

S

A2

'II

A,

An

A.

A,.

'II
X-ADDRESS

DECODER
D

As

Ao

Ao

A,

VEE

Ar

Dual In-Line Package
TRUTH TABLE

--

INPUT
S

W

D

H
L
L
L

X
L
L
H

X
H
L
X

OUTPUT

MODE

L
L
L
OUT

DISABLED
WRITE"H"
WRITE"!:'
READ

x

= HIGH VOLTAGE LEVEL

L

=

X = DON'T
CARE
·Vcc GROUNDED

LOW VOLTAGE LEVEL

Leadless Chip Carrier

Flat Package

Functlenal Description
The Fujitsu MBM10470A is a fully
decoded 4096-bit read/write random access memory organized
as 4096 words by one bit. Memory cell selection is achieved by
means of a 12-bit address designated Ao-A 11 • The active low

Absolute Maximum Ratings
(See Note)

Chip Select (8) input is provided
for memory expansion. The read
and write operations are controlled by the state of the
active low Write Enable (IN) input. With \N and 8 held low, the
data at DIN is written into the
addressed location. To read, \Nis

held high, while 8 is held low.
Data at the addressed location is
then 'transferred to OUT and read
out non-inverted. Open
emitter outputs are provided to
allow for maximum flexibility in
output wired-OR connection.

Parameter

Symbol

Value

Unit

VEE pin potential to ground pin

+0.5 to -7.0

V

Input voltage

VEE
VIN

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

mA

Temperature under bias

TA

-55 to +125

'C

Storage temperature

T STG

-65 to +150

'C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

Guarant_d Operating
Conditions
(Referenced to Vcel

Parameter
Supply voltage

Symbol

Min

Typ

Max

Unit

Ambient Temperature

-5.46

-5.2

-4.94

V

O'C to 75'C

FUJITSU
9-21

MBM10470A-10
MBM10470A-15
MBM10470A-20

Capacitance
Parameter

Symbol

Input pin capacitance

CIN

Min

Typ
4

pF

Output pin capacitance

COUT

6

pF

Max

Unit

DC Characteristics
(Vcc = OV, VEE = -5.2V, Output
Load = 500 to -2.0V, unless
otherwise noted.)

Parameter

Symbol

Min

Max

Unit

Ta

Output high voltage
(VIN = VIH max or VIL min)

VOH

-1000
-960
-900

Typ

-840
-810
-720

mV

O°C
25°C
75°C

Output low voltage
(VIN = VIH max or VIL min)

VOL

-1870
-1850
-1830

-1665
-1650
-1625

mV

GOC
25°C
75°C

Output high voltage
(VIN = VIH min or VIL max)

VOHC

-1020
-980
-920

mV

O°C
25°C
75°C

Output low voltage
(VIN = VIH min or VIL max)

VOLC

-1645
-1630
-1605

mV

O°C
25°C
75°C

Input high voltage
(guaranteed input voltage high for all inputs)

VIH

-1145
-1105
-1045

-840
-810
-720

mV

O°C
25°C
75°C

Input low voltage
(guaranteed input voltage low for all inputs)

V IL

-1870
-1850
-1830

-1490
-1475
-1450

mV

O°C
25°C
75°C

Input high current (VIN

= VIH max)
= VIL min)
S input low current (VIN = VIL min)

IIH

-220

!LA

O°C to 75°C

Input low current (VIN

IlL

-50

IlL

0.5

Power supply current
(all inputs and output open)

lEE

-200

170

".A

O°C to 75°C

!LA

O°C to 75°C

mA

O°C to 75°C

AC Characteristics
(Full Guaranteed Operating
Ranges, Output Load = 500 to
-2.0V and 30pF to GND, and
Airflow", 2.5 mis, unless
otherwise noted.)

Read Cycle
MBM10470A·10 MBM10470A·15 MBM10470A·20
Min Typ Max Min Typ Max Min Typ Max Unit

Parameter

Symbol

Address access time

tM

10

15

20

ns

Chip select access time

tACS

6

8

15

ns

Chip select recovery time

t RCS

6

8

15

ns

Read Cycle Timing Diagrams

OUT

-----J]

9·22

MBM10470A-10
MBM10470A-15
MBM10470A-20

Write Cycle

Parameter

Symbol

MBM10470A·10 MBM10470A·15 MBM10470A·20
Min Typ Max Min Typ Max Min Typ Max

Unit

Write pulse width

tw

12

ns

Write disable time

tws

6

8

15

Write recovery time

tWA
tWSA

10

10

15

Address set up time

15

15

ns
ns

3

ns
ns

Chip select set up time

twscs

2

Data set up time

tWSD

2

ns

Address hold time

tWHA

2

2

2

ns

Chip select hold time

tWHCS

2

2

2

ns

Data hold time

tWHD

2

2

2

ns

Write Cycle Timing Diagram

\

V

ADDRESSES

V

~IWSD ~ ---

D,N

w

------OUT

___..t:--- 1WSA

~IWHAIWHes _

Iw

_Iwscs_

50%

---

Iws

IWHf=

50%

I---IWR

Rise Time and Fall Time
MBM10470A·10 MBM10470A·15 MBM10470A·20
Min Typ Max Min Typ Max Min Typ Max Unit

Parameter

Symbol

Output rise time

I,

1.5

1.5

1.5

ns

Output fall time

~

1.5

1.5

1.5

ns

AC Test Conditions

-0'9V~_80%

GND

20%

-1.7V

Vee

~

tr

OUT

tr

= t, = 2.5n8 typ

OUTPUT LOAD: RL = 50H
CL = 30pF
(INCLUDING PROBE AND STRAY CAPACITANCE)

NOTE: ALL TIMING MEASUREMENTS REFERENCED TO 50% INPUT LEVELS.

FUJITSU
9·23

MBM10470A-10
MBM10470A-15
MBM10470A-20

Packa.e Dimensions
Dimensions in Inches
(millimeters)

1a.Lead Ceramic ICerdlpl Dualln·Llne Packa.e
lcase tIIo.: DIP.18C-C011

18·Lead Ceramic ICERDIPI Flat Packa.e
lca. . No.: FPT.18C-C011

-- r

II

A35(11 05)
ASO(I1.43)
·00000.64)MAX

.030(0.78)

•

.045(1.15)

l

.364(9.25)
AOO(10.18)

PIN #1 IDENT

'rrn-n-n-rr-rr~U

/'

.Q5O(1.27)TYP _

I
II
I-- ---+l •
.396(10.03)
A05(10.29)

9-24

.016(0.40)
.018(0.46)

.900(22.88)MIN

J
l

.250(6.35)

.3T~

~--f-----L---'
.004(0.10)

.006(0.15)

---- .090(2.29)MAX

MBM10470A-10
MBM10470A-15
MBM10470A-20

Packaga Dimensions
(Continued)
Dimensions in inches
(millimeters)

18-Pad Ceramic (Frlt Seal) Leadless Chip Carrier
(Case No.: LCC:.18C·F01)
"'PIN NO. 1 INDEX

n

R.012(0.30)TVP
(4 PLCS)

.340(8.64)

c~JI"
.295(7.49)

·SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

9-25

.100(2.54)
TVP

FUJITSU

Bipolar Memories
•

MBM100470A-10, MBM100470A-15
4096-Bit Bipolar Eel Random
Access Memory

Description
The Fujitsu MBM100470A is a fully decoded 4096-bit ECl
read/write access memory designed for high-speed scratch pad.
control and buffer storage applications. This device is organized as
4096 words by one bit. and it features on-chip voltage/temperature
compensation for improved noise margin.
The MBM100470A offers extremely small cell and chip size. realized through the use of Fujitsu's patented DOPOS (Doped Polysilicon). as well as lOP-II (Isolation by Oxide and Polysilicon).
processing.
Operation for the MBM100470A is specified over a temperature
range of from 0' to 85'C (TA for DIP. Tc for Flat Package). It also
features 18-pin Ceramic DIP and Flat Package. and is fully compatible with industry-standard lOOK-series ECl families.

Features
•

4096 words x 1 bit
organization
• On-chip Yoltage/
temperature compensation
for improYed noise margin
• Fully compatible with
industry-standard
lOOK-series ECl families
• Address access time:
10 nsec. max.
(MBM100470A-l0)
15 nsec. max.
(MBM100470A-15)

•

•
•
•
•

Chip select access time:
6 nsec. max.
(MBM100470A-l0)
8 nsec. max.
(MBM100470A-15)
Open emitter output for
ease of memory expansion
low power dissipation of
0.19mW/bit
DOPOS and lOP-II
processing
Pin compatible with the
Fl00470

Small geometry bipolar integrated

circuits are occasionally susceptible
to damage from static vOltages or

electric fields. It is therefore
advised that normal precautions be
app~catlon of any
voltage higher than maximum rated

taken to avoid

voltages to this device.

9-26

MBM100470A-10
MBM100470A-15

MBM100470A
Block Diagram
and Pin Assignments
WORD
DRIVER

X·ADDRESS
DECODER

TRUTH TABLE
INPUT
Ii
W
H
X
L
L
L
L
L
H

OUT

Vee

Au
A,

I!,N

I

A,

W

Ao

Au

A"
A,.

A,

Au

A,

Au

VEE

A7

D,N

D,N

OUTPUT

MODE

L
L
L
OUT

DISABLED
WRITE "H"
WRITE "L"
READ

X

H
L
X

H = HIGH VOLTAGE LEVEL
L = LOW VOLTAGE LEVEL

OUT
Au
A,
A,
Au

Vee

1

I!,N

II
W
A"
A,.
Au
Au
A7

FLAT
PACKAGE

Au

Au
VEE

·Vee GROUNDED

x = DON'T CARE

Functional D.scrlptlon
The Fujitsu MBMt00470A is fully
decoded 40gB-bit read/write random access memory organized
as 4096 words by one bit. Memory cell selection is achieved by
means of a 12-bit address designated Ao - A". The active low

Absolute Maximum Ratings
(See Note)

Chip Select (8) input is provided
for memory expansion. The read
and write operations are controlled by the state of the active
low Write Enable (W) input. With
Wand 8 held low, the data at D'N
is written into the addressed location. To read, W is held high,

while ~ is held low. Data at the
addressed location is then transferred to OUT and read out noninverted. Open emitter outputs
are provided to allow for maximum flexibility in output wiredOR connection.

Rating

Symbol

Value

Unit

VEE pin potential to ground pin

VEE

+0.5 to -7.0

V

Input voltage

V,N

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

mA

TA for DIP

-55 to +125

Temperature under bias

Te for flat
package

-55 to +t25

Storage temperature

TSTG

-65 to +150

OC

'C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

Guaranteed Operating
Conditions
(Referenced to Vee>

Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature for DIP
Case Temperature for Flat Packa!!

Supply voltage

VEE

-5.7

-4.5

-4.2

V

O°C to 85°C

FUJITSU
9-27

MBM100470A-10
MBM100470A-15

Capacitance
Typ

Parameter

Symbol

Input pin capacitance

C IN

Min

4

Ma.

pF

Unit

Output pin capacitance

COUT

6

pF

DC Characteristics
(Vcc = OV, VEE = -4.5V, Output
load = 500 and 30pF to -2.0V,
TA = O°C to 85°C for DIP,
T c = O°C to 85°C for Flat
Package, Airflow .. 2.5 mis,
unless otherwise noted.)

Ma.

Unit

-1025

-880

mV

VOL

-1810

-1820

mV

Output high voltage
(VIN = VIH min or VIL max)

VOHC

-1035

Output low voltage
(VIN = VIH min or VIL max)

VOLC

Input high voltage
(guaranteed input voltage high for all inputs)

V IH

-1165

Input low voltage
(guaranteed input voltage low for all inputs)

VIL

-1810

Parameter

Symbol

Min

Output high voltage
(VIN = VIH max or VIL min)

V OH

Output low voltage
(VIN = VIH max or VIL min)

= V IH max)
Input low current (VIN = VIL min)
S input low current (VIN = VIL min)

IlL

-50

IlL

0.5

Power supply current
(all inputs and output open)

lEE

-200

Input high current (VIN

IIH

Typ

mV
-1610

mV

-880

mV

-1475

mV

220

!LA

170

/loA

/loA

mA

AC Characteristics
(VCC = OV, VEE = -4.5V ± 5%,
Ouput load = 50n to -2.0V and
30pF to GND, TA = O°C to 85°C
for DIP, TC = O°C to 85°C for
Flat Package, Airflow .. 2.5 mis,
unless otherwise noted.)

Read Cycle
MBM100470A·10
Min
Typ
Ma.

MBM100470A·15
Min
Typ
Ma.

Parameter

Symbol

Address access time

tAA

10

15

Unit

Chip select access time

tACS

6

8

ns

Chip select recovery time

tRCS

6

8

ns

ns

Read Cycle Timing Diagrams

\'------

9-28

MBMt00470AotO
MBMt00470Ao15

Write Cycle

Parameter

Symbol

MBMt00470A·tO
Min
Typ
Max

MBM100470A·t5
Min
Max

Unit

Write pulse widlh

Iw

12

15

ns

Write disable time

Iws

6

8

ns

Write recovery time

tWA

12

12

ns

Address set up lime

IWSA

Chip select set up time

twscs

ns

Data set up time

twso

ns

Address hold time

tWHA

2

2

Chip select hold time

tWHCS

2

2

ns

Data hold time

tWHO

2

2

ns

ns

ns

Write Cycle Timing Diagram

ADDRESSES

w
OUT

RI. . Time and Fall Time
Parameter

Symbol

Outpul rise lime

I,

Min

Typ

Output fall time

Max

ns

1.5

ns

AC Te.. Conditions
GND

::~

.

Vee

~

tr

OUTPUT LOAD: RL

= tt = 2.508 typ

= SOIl

CL = 30pF

(INCLUDING PROBE AND STRAY CAPACITANCEI
NOTE: ALL TIMING MEASUREMENTS REFERENCED TO 50% INPUT LEVELS.

FUJITSU

9-29

Unit

1.5

MBMi00470A-i0
MBMi00470A-i5

Package Dimensions
Dimensions in inches
(millimeters)

i8·Lead Ceramic ICERDIP) Dual In·Llne Package
ICase No.1 DIP·i8CoCOi)

n

r

.285(7.24)
30

h:::r=::r-=,.--,=r-t=-,:=-.:::::r"'1:::T''''ClM .
.882(22.40)
.91 23.16)

n

is-Lead Ceramic ICERDIP) Flat Package
ICase No.1 FPT.i8C.COi)

- r--

435(1105)
.450(11.43)
.025(0.64)MAX

1

l

I

~ .030(0.76)
.045{1.14)

J
---.t

.250(6.35)
.300(7.62)

.364(9.25)
0.16)
'41'

.9OO(22.88)MIN

t

PIN #1 IDENT "

J

.250(6.35)

.300(~62)

.05O(1.2nTYP . .

I- -11 ~.016(0.41)

.018(0.46)
.395(10.03)
.405( 10.29

9·30

.004(0.10)
.006(0.15)

i4-- .090(2.29)MAX

FUJITSU

Bipolar Memories
•

MBM10474A-10, MBM10474A-15
4096-Bit Bipolar Eel
Random Access Memory

Description
The Fujitsu MBM10474A is a fully decoded 4096-bit ECl read/write
random access memory designed for high speed scratch pad, control and buffer storage applications. This device is organized as
1024 words by 4 bits, and it features on-chip voltage compensation
for improved noise margin.
The MBM10474A offers extremely small cell and chip size, realized
through the use of Fujitsu's patented DOPOS (Doped Polysllicon),
as well as lOP-II (Isolation by Oxide and Polysilicon) processing.
Operation for the MBM10474A is specified over a temperature
range of from O°C to 75°C (TA for DIP, Tc for Flat Package and
lCC). It also features 24-pin Ceramic DIP, Flat Package, or lCC,
and is fully compatible with industry standard 10K-series ECl
families.

F••tur.s
1024 words x 4 bits
organization
• On-chip voltaga
compensation for Improved
noise margin
• Fully compatible with industry standard 10K-series ECl
families
• Address access time:
10 ns max. (MBM10474A-10)
15 ns max. (MBM10474A-15)
•

•

Chip select access time:
6 ns max. (MBM10474A-10)

8 ns max. (MBM10474A-15)
•

Open emitter output for
ease of memory expansion
• low power dissipation of
0.26 mW/bit typo
(MBM10474A-10)
0.20 mW/blt typo
(MBM10474A-15)
• DOPOS and lOP-II

Small geometry bipolar integrated
circuits are occasionally susceptible
10 damage from static voltages or

electric fields. II is therefore
advised that normal precautions be
taken to avoid application of any
voJtage higher than maximum rated
voltages to this device.

9-31

MBM10474A·10
MB~10474A·15

MBM10474A
Block Diagram
and Pin Assignments

Vee

I

A4
A,

i<

As

c

0,

O.

0,

Ao

D.

A,

0.

A,

D,

I
I
I

w

0

~

!

I

:
I

:
I

I
I

MEMORY CELL ARRAY I
I
,
I

"w~

Ar
As
A.

Vee

00

S
W

Ao

0,

A4

li

As

Iii

NC

A,

As

As

VEE

Ar

Dual Inline Package
As As A7 VeE A6 Ne

TRUTH TABLE
INPUT

S

W

D,N

H
L
L
L

X
L
L
H

X
H
L
X

OUTPUT

MODE

L
L
L
OUT

DISABLED
WRITE"H"
WRITE"!:'
READ

H = HIGH VOLTAGE LEVEL
L = Low. VOLTAGE LEVEL
X = DON'T CARE

Iii

As

S
0,

A4
As

0,

A,

Do

A,

D.

As
0, 02 VCCVCCA03 O.
Vec GROUNDED

Flatpack

Ao

A1

A2

-4-!

:__~_j _~.i 1 l~~j~~;~~j
:..i

_~-_-!

TOP VIEW

51

A3 7:
A4

-o-!

As

:~:i

r21

04

!:~~~

Ll2

;-20 03
:18 01

r---'----c---·---j----r--.,

:17 S
ti~_ w

110: 11 :12i13i14 !151

Leadless Chip Carrier

Functional Description
The Fujitsu MBM10474A is a fully
decoded 4096 bit read/write ran·
dom access memory organized
as 1024 words by 4 bits. Memory
cell selection is achieved by
means of a 10·bit address
designed Pta through ALThe
active low Chip Select (::i) input is

provided for memory expansion.
The read and write operations
are controlled by the state of the
Enable (W) input. With Wand S
held low, the data at D'N is writ·
ten into the addressed location.
To read, W is held high, while

FUJITSU
9·32

S is held low. Data at the addressed location i~ then transferred to OUT and read out non·
inverted. Open emitter outputs
are provided to allow for maximum flexibility in output wired-OR
connection.

MBM10474A·10
MBM10474A·15

Absolute Maximum Rating ..
(See Note)

Rating

Symbol

Value

Unit

VEE pin potential to ground pin

VEE

+0.5 to -7.0

V

Input voltage

VIN

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

rnA

TAforDIP

-55 to +125

°C

Temperature under bias

Te for flat
package and LCC

-55 to +12S

°C

Storage temperature

TSTG

-65 to +ISO

°C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

Guaranteed Operating
Conditions
(Referenced to Veel
Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature for DIP,
Ca.e Temperature for Flat
Package and LCC

Supply voltage

VEE

- S.46

-S.2

-4.94

V

O°C to 7SoC

Capacitance

DC Characteristics
(Vee = OV, VEE = -S.2V, Output
Load = SOD to -2.0V, TA = O°C
to 7SoC for DIP, Airflow ~2.Sm/s,
T c = O°C to 7SoC for Flat
Package and LCC, unless
otherwise noted.)

Parameter

Symbol

Typ

Max

Unit

Input pin capacitance

CIN

Min

4

S

pF

Output pin capacitance

COUT

6

8

pF

Typ

Operating
Unit Temperature

Parameter

Symbol Min

Output high voltage
(VIN = VIH max or VIL min)

VOH

-1000
-960
-900

-840
-810
-720

mV

O°C
2SoC
75°C

Output low voltage
(VIN = VIH max or VIL min)

VOL

-1870
-18S0
-1830

-1665
-1650
-1625

mV

O°C
2SoC
7SoC

Output high voltage
(VIN = VIH min Or VIL max)

VOHC

-1020
-980
-920

mV

O°C
2SoC
7SoC

Output low voltage
(VIN = VIH min or VIL max)

VOLC

-164S
-1630
-160S

mV

O°C
2SoC
7SoC

Max

Input high voltage
V IH
(guaranteed input voltage high for all inputs)

-114S
-IIOS
-1045

-840
-810
-720

mV

O°C
25°C
7SoC

I nput low voltage
(guaranteed input voltage low for all inputs)

-1870
-1850
-1830

-1490
-1475
-1450

mV

O°C
25°C
75°C

220

p.A

O°C to 7SoC

p.A

O°C to 75°C

p.A

O°C to 7SoC

rnA

O°C to 7SoC

VIL

Input high current (VIN = VIH max)

IIH

Input low current (VIN = V IL min)

IlL

-SO

S input low current (VIN

IlL

O.S

= V IL min)

MBM10474A-l0
Power supply current
(all inputs and output open) MBM10474A-1S lEE

9-33

170

-230
-200

MBM10474A·10
MBM10474A·15

AC Characteristics
(Vee = OV, VEE = -5.2 ±5%,
Output Load = 50n to -2.0V
and 30pF to GND, TA = O°C to
75°C for DIP, Airflow .. 2.5 mis,
Te = O°C to 75°C for Flat
Package and LCC, unless
otherwise noted.)

Read Cycle
Parameter

Symbol

MBM10474A·10
Min
Typ
Max

MBM10474A·15
Min
Typ
Max

Unit

Address access time

tM

2

Chip select access time

tAes

Chip select recovery time

t RCS

7

10

3

10

15

ns

1.5

3

6

2

4

8

ns

1.5

3

6

2

4

8

ns

Read Cycle Timing Diagram

{:cs-

lt8O%
50%

OUT

20%

-------'1

Write Cycle
Parameter

Symbol

MBM10470A.10
Min
Typ
Max

MBM10474A·15
Typ
Max
Min

Write pulse width

tw

12

15

Write disable time

tws

Write recovery time

tWR

Address set up time

tWSA

Chip select set up time

15

10
2

ns

8

6

Unit
ns
ns

2

ns
ns

twscs

2

Data set up time

twso

2

ns

Address hold time

tWHA

3

ns

Chip select hold time

tWHcs

2

ns

Data hold time

tWHO

2

ns

Write Cycle Timing Diagram

ADDRESSES

D,N

w
OUT

FUJITSU
9·34

MBMI0474A·10
MBMI0474A·15

Rise Time and Fall Time
Max

Unit

Output rise time

Parameter

Symbol

3.5

ns

Output fall time

3.5

ns

Min

Typ

AC Test Conditions
GND

-0'9V~-80%
20%

-1.7V

Vee

,

OUT

~

tr

L..._..:.r::""'.....J RL

=

tt =

2.5"5 typ

= son

OUTPUT LOAD: RL
CL = 30pF
(INCLUDING PROBE AND STRAY CAPACITANCE)

NOTE: ALL TIMING MEASUREMENTS REFERENCED TO 50% INPUT LEVELS.

Package Dimensions
Dimensions in inches
(millimeters)

24.Lead Ceramic ICERDIPI Dual In·Llne Package
ICa. . No.: DIP.24C·C051

'~OO_150

IT

R.025(0.64)
REF

.354(8.99)
.37 9.80)

1.180(29.97
1.220(30.99)

9·35

rn~~

'n
.403(10.24)

AOO(10.16)TYP

1

MBM10474A·10
MBM10474A.15

Package Dimension.
(continued)
Dimensions in inches
(millimeters)

24·Lead Ceramic (CERDIP) Flat Package
ICa. . NO.1 FPT.24C.C02)
370(940)

333(848)

.400( 1O. 16)

.360(9.14)

PlNNl IDENT

"

J 9.40)
.400(1 0.16)

1
t

.333(8.46)
.380(9. 14)

050(1.27)TYP __

~I__
.250(6.38)
REF

t
1+-.075(1.91)MAX
.016(0.40)
.018(0.46)

J

.004(0.10)
.008(0.20)

24·Pad Ceramic IFRIT SEAL) Leadle•• Chip Carrier.
ICase No: LCC.24C-F02)

'PIN NO.1 INDEX

,

n

R.OI2(O.30 TYP
(4 PLCS)

.395(10.03)

n:=n:=~.PM"

lti

.::=:;:;::;;;:'3=95;:;:(1=0'03;:;::;)
.410(10.41)

W"05(2'67)MAX

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

9-36

.25O(6.35)TYP
.310(7.87)TYP

.100(2.54)MAX

FUJITSU

Bipolar Memories
•

MBM100474A·10, MBM100474A·15
4096-Bit Bipolar Eel
Random Access Memory

Description
The Fujitsu MBM100474A is a fully decoded 4096-bit ECl
read/write random access memory designed for high speed scratch
pad, control and buffer storage applications. This device is organized as 1024 words by 4 bits, and it features on-chip
voltage/temperature compensation for improved noise margin.
The MBM100474A offers extremely small cell and chip size, realized through the use of Fujitsu's patented DOPOS (Doped Polysilicon), as well as lOP-II (Isolation by Oxide and Polysilicon)
processing.
Operation for the MBM100474A is specified over a temperature
range of from O°C to 85°C (TA for DIP, T c for Flat Package and
lCC). It also features 24-pin Ceramic DIP, Flat Package, or lCC,
and is fully compatible with industry standard lOOK-series ECl
families.

Features
• 1024 words x 4 bits
organization
• On-chip voltage
temperature compensation
for Improved noise margin
• Fully compatible with industry standard lOOK-series
ECLfamllies
• Address access time:
10 ns max.
(MBM100474A-l0)
15 ns max.
(MBM100474A-15)

Chip select access time:
6 ns max. (MBM100474A-l0)
8 ns max. (MBM100474A-15)
• Open emitter output for
ease of memory expansion
• Low power dissipation of
0.22 mW/bit
(MBM100474A-l0)
0.20 mW/bit
(MBM100474A-15)
• DOPOS and lOP-II
•

Small geometry bipofar integrated
circuits are occasionally susceptible

to damage from static voltages or
electric fields. It is therefore
advised that normal precautions be
taken to avoid application of any
voltage higher than maximum rated
voltages to this device.

9-37

MBM100474A·10
MBM100474A·15

MBM100474A
Block Diagram
and Pin Assignments

Ao
0.

0,

0,

S
W

0,

A,

I

..

I
I
I

ii:

A,

C
C

A,
A7
A.
A,

I
,
I
MEMORY CELL ARRAY,

!

()

l!!
><

:

;

I

I

I

I

I,

I

!I
W

0,

A.

O.

A,

Vee

A7

Vee

VEE

0,

A,

0,

NC

AD

A,

A,

A,

A,

A,

Dual Inllne Package
TRUTH TABLE

A, A. A7 VEE A6 Ne

INPUT

H
L
X

S

W

D,N

H
L
L
L

X

X

L
L
H

H
L

X

OUTPUT

MODE

L
L
L
OUT

DISABLED
WRITE"H"
WRITE"L"
READ

= HIGH VOLTAGE LEVEL

=LOW VOLTAGE LEVEL

W
Ii

A,

0,

A,

D.

A.

A,

0,

A,

0,

Ao

= DON'T CARE

0, 02 Vee Vee 03 0,
Vee GROUNDED

Flatpack

Ao

"4"!

A1

"51

A2

iq

L~j ~~.J 1 L~~L~~J.~~j
I..j
TOP VIEW

As -.,";

[i,

04

rio 03

[1-9" OJ

:1i 01

"" -i-:

[11"

S

A, _-9_1_

tie__
L

w

!10r1-;Tii 17ii11-4"jisl
NC A,I A7A,A,
VEE

Leadl.s. Chip Carrier

Functional Description
The Fujitsu MBM100474A Is a
fully decoded 4096 bit read/write
random access memory organized as 1024 words by 4 bits.
Memory cell selection is achieved
by means of a 10-bit address
designed Ac through Ag. The

active low Chip Select (S) input is
provided for memory expansion.
The read and write operations
are controlled by the state of the
active low Write Enable (iN) input. With iii and S held low, the
data at D'N is written into the_
addressed location. To read, W is

FUJITSU
9-38

held high, while S is held low.
Data at the addressed location is
then transferred to OUT and read
out non-inverted. Open emitter
outputs are provided to allow for
maximum flexibility in output
wired-OR connection.

MBM100474A·10
MBM100474A·15

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

VEE pin potential to ground pin

VEE

+0.5 to -7.0

V

Input voltage

VIN

+0.5 to VEE

V

lOUT

-30

rnA

TA for DIP

Output current (DC, output high)
Temperature under bias
Storage temperature

-55 to +125

'e

Te for flat
package and Lee

-55 to +125

'e

TSTG

-65 to +150

'e

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

Guaranteed Operating
Conditions
(Referenced to Veel
Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature for DIP,
Case Temperature for Flat
Package and LCC

Supply voltage

VEE

-5.7

-4.5

-4.2

V

o'e to 85'e

Capacitance
Parameter

DC Characteristics
(Vee = OV, VEE = -4.5V, Output
Load = 50n to -2.OV, T A = o'e
to 85'e for DIP, Airflow ;;.2.5m/s,
T e = o'e to 85'e for Flat
Package and Lee, unless
otherwise noted.)

Typ

Max

Unit

Input pin capacitance

Symbol

4

5

pF

Output pin capacitance

6

8

pF

Parameter

Min

Symbol

Min

Max

Unit

-1025

-880

mV

-1810

-1620

mV

Output high voltage
(VIN = VIH max or VIL min)
Output low voltage
(VIN = VIH max or VIL min)
Output high voltage
(VIN = VIH min or VIL max)

-1035

Output low voltage
(VIN = V1H min or VIL max)

VOLe

Typ

mV
-1610

mV

Input high voltage
(guaranteed input voltage high for all inputs)

-1165

-880

mV

Input low voltage
(guaranteed input voltage low for all inputs)

-1810

-1475

mV

220

/LA

170

!LA
!LA

Input high current (VIN = VIH max)
Input low current (VIN = V1L min)

-50

S input low current (VIN

0.5

= V IL min)

Power supply current
(all inputs and output open)

MBM100474A-l0
MBM100474A-15

9-39

-230
lEE

-200

rnA

MBM100474A-10
MBM100474A-15

AC Characteristics
(Vcc = OV, VEE = -4.5 ±5%,
Output Load = 500 to -2.0V
and 30pF to GND, TA = O°C to
85°C for DIP, Airflow"" 2.5 mis,
T c = O°C to 85°C for Flat
Package and LCC, unless
otherwise noted.)

Read Cycle

Parameter

Symbol

MBM100474A-10
Min
Typ
Max

MBM100474A·15
Max
Min
Typ

Address access time

tAA

2

7

10

3

10

15

Chip select access time

tACS

1.5

3

6

2

4

8

ns

Chip select recovery time

tRCS

1.5

3

6

2

4

8

ns

Unit
ns

Read Cycle Timing Diagram

50%

50%

80%
50%

OUT

OUT

Write Cycle

Parameter

Symbol

MBM100474A·10
Min
Typ
Max

MBM100474A-15
Typ
Max
Min

Write pulse width

tw

12

15

Write disable time

tws

Write recovery time

tWR

Address set up time

t WSA

ns
8

6
10
2

Unit

15

ns
ns

2

ns
ns

Chip select set up time

twscs

2

Data set up time

t WSD

2

ns

Address hold time

tWHA

3

ns

Chip select hold time

t WHCS

2

ns

Data hold time

tWHD

2

ns

Write Cycle Timing Diagram

\
/

V

t/

ADDRESSES

-dftWSD

w

OUT

------L.:--

tWSA _ _

twscs-'"

FUJITSU
9·40

--

-- tWH~

~
r--

- - tWHA--tw

tWHCS --------------

50%

tws

50%

...-tWR

MBM100474A.10
MBM100474A·15

Rise Time and Fall Time
Parameter

Symbol

Output rise time

t,

Typ

Min

Output fall time

Max

Unit

3.5

ns

3.5

ns

AC Test Conditions
GND

::~

Vee

OUT

~

~

tr

= tt =

2.5"s typ

OUTPUT LOAD: Rl = son
CL = 30pF
(INCLUDING PROBE AND STRAY CAPAcrrANCE)

NOTE: ALL TIMING MEASUREMENTS REFERENCED TO SO% INPUT LEVELS.

Package Dimensions
Dimensions in inches
(millimeters)

24·Lead Ceramic ICERDIP) Dual In·Llne Package
ICase No.: DIP·24C·C05)

n III

R.025(0.84)
REF

.354(8.99)
.378(9.80)

.403(10.24)

.41°·92)

1.180(29.97)
1.220(30.99)

.090(2.29)
.110(2.79)

9-41

=::C::~",""I--.L-

MBM100474A.10
MBM100474A·15

Package Dimensions
Dimensions in inches
(millimeters)

24·Lead Ceramic (CERDIP) Flat Package
(ease No.: FPT·24CoC02)
310(940)

333(846)

.400(10.16)

.360(9.14)

PIN #1 IDENT

'"

. 3 140)
.400(1 0.16)

tt

.333(S.46)
.360(9. 14)

OS0(1.27)TVP __

Ij""" __
.250(6.36)
REF

t

.075(1.91)MAX
.016(0.40)
.018(0.46)

J

.004(0.10)
.008(0.20)

24·Pad Ceramic (FRIT SEAL) Leadless Chip Carriers
(ease No: Lcc.24C·F02)

I

'PIN NO.1 INDEX

n

R.012(0.30)TVP
(4PLCS)

.395(10.03)

1\ 4: : n: : n:'3=95(;: '=0':;<03=):;<: : ;: ;:~' " IJ.410(10.41)

.105(2.67)MAX

.25O(6.35)TYP
.310(7.S7)TYP

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

9·42

.100(2.54)MAX

FUJITSU

Bipolar Memories
•

MBM10480·15, MBM10480·25
16384-Bit Bipolar Eel
Random Access Memory

Description
The Fujitsu MBM10480 is a fully decoded 16384-bit ECl read/write
random access memory designed for main memory. control and
buffer storage applications. This device is organized as 16384
words by one bit. and it features on-chip vo~age compensation for
improved noise margin.
The MBM10480 offers extremely small cell and chip size. realized
through the use of Fujitsu's patented DOPOS (Doped Polysilicon).
as well as lOP-II (Isolation by Oxide and Polysilicon). processing.
Operation for the MBM10480 is specified over a temperature range
of from O°C to 75°C (TA for DIP. Tc for Flat Package and lCC). It
also features 20-pin Ceramic DIP. Flat Package. and lCC. and is
fully compatible with industry standard 10K-series ECl families.

Features
16384 words x 1 bit
organization
On-chip vonage compensation for Improved noise
margin
• Fully compatible with industry standard 10K-series ECl
families
• Address access time:
15 ns max. (MBM10480-15)
25 ns max. (MBM10480-25)
•

•

Chip select access time:
8 ns max. (MBM10480-15)
10 ns max. (MBM10480-25)
• Open emitter output for
ease of memory expansion
• Low power dissipation of
0.05 mW/bit
• DOPOS and lOP-II
• Pin compatible with the
•

F10480

Small geometry bipolar integrated
circuits are occasionally susceptible
to damage from static voltages or

electric fields. It is therefore
advised that normal precautions be
taken to avoid application of any
voltage higher than maximum rated
voltages to this device.

9-43

MBM10480-15
MBM10480-25

MBM10480
Block Diagram and Pin
Assignments

OUT

VCC'

As

D

A,

II

A,

W

A.

A13

Ao

A12

As

A"

A.

AlO

Vi

O'N

A7

Ag

VEE

As

Dual In-Line Package
TRUTH TABLE

Vec·

INPUT
OUTPUT

S

W

DIN

H
L
L
L

X

X

L
L
H

H
L

X

L
L
L
OUT

MODE
DISABLED
WRITE"H"
WRITE"!.:'
READ

Ao

D

A,

5
Iii

A4

A'3
A12

As

A11

A7

A,.
Ag

H = HIGH VOLTAGE LEVEL
L

=

LOW VOLTAGE LEVEL

VEE

A,

X = DON'T CARE
*Vcc GROUNDED

Flat Package
(TOP VIEW)

A1
A2

-,

.,

r-

3'

-~

A3
A.
A5
AS

,1.

S

"S

A'3

r1'7
r-

-~

5 ,

-i
S,

1-,15

71

",
r-

.

r-

-i

-i,

'II

A'2
A11

,,3 AlO
L_

_J

r-T.-"'T"'-'-"

I 9 110111 I 12 I
A7 VEE As AS

Leadlesa Chip Carrier

Functional Description
The Fujitsu MBM10480 is a fully
decoded 16384 bit read/write random access memory organized
as 16384 words by one bit. Memory cell selection is achieved by
means of a 14-bit address
designed Ao through A ,3 . The

active low Chip Select (8) input is
provided for memory expansion.
The read and write operations
are controlled by the state of the
Enable (W) input. With Wand S
held low, the data at DIN is written into the addressed location.
To read, W is held high, while

FUJITSU
9-44

S is held low.

Data af the addressed location is then transferred to OUT and read out noninverted. Open emitter outputs
are provided to allow for maximum flexibility in output wired-OR
connection.

MBM10480·15
MBM10480·25

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

VEE pin potential to ground pin

VEE

+0.5 to -7.0

V

Input voltage

VIN

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

mA

T'; for DIP

-55 to +t25

°e

Temperature under bias

Te forllat
package and Lee

-55 to +125

°e

TSTG

-65 to +150

°e

Storage temperature

Note: Pennanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

Guaranteed Operating
Conditions
(Referenced to Veel
Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature for DIP,
Case Temperature for Flat
Package and LCC

Supply voltage

VEE

-5.46

-5.2

-4.94

V

oOeto 75°C

Capacitance
Parameter

DC Characteristics
(Vee = OV, VEE = -5.2V, Output
Load = 50n and 30pF to -2.0V,
TA = ooe to 75°C for DIP, Airflow
>2.5m/s, Te = ooe to 75°C for
Flat Package and Lee, unless
otherwise noted.)

Symbol

Min

Typ

Unit

Max

Input pin capacitance

5

pF

Output pin capacitance

6

pF

Parameter

Symbol Min

Output high voltage
(VIN = VIH max or VIL min)

VOH

Typ

Max

Operating
Unit Temperature

-1000
-960
-900

-840
-810
-720

mV

ooe
25°C
75°C

Output low voltage
(VIN = VIH max or VIL min)

-1870
-1850
-1830

-1665
-1650
-1625

mV

ooe
25°C
75°C

Output high voltage
(VIN = VIH min or VIL max)

-1020
-980
-920

mV

ooe
25°C
75°C

-1645
-1630 mV
-1605

ooe
25°C
75°C

Output low voltage
(VIN = VIH min or VIL max)
Input high voltage
(guaranteed input voltage high for all inputs)

-1145
-1105
-1045

-840
-810
-720

mV

ooe
25°C
75°C

Input low voltage
(guaranteed input voltage low for all inputs)

-1870
-1850
-1830

-1490
-1475 mV
-1450

ooe
25°e
75°C

220

pA

ooe to 75°C

pA

ooe to 75°C

p.A

ooe to 75°C

mA

ooe to 75°C

Input high current (VIN = VIH min)
Input low current (VIN

=

S input low current (VIN

VIL min)

IlL

-50

= VIL min)

IlL

0.5

Power supply current
(all inputs and output open)

MBM10480-15

-220

MBM10480-25 lEE

-220

9-45

170

MBM10480·15
MBM10480·25

AC Characteristics
(Vcc = OV, VEE = -5.2 ±5%,
Output Load = 50n to -2.0V
and 30pF to GND, TA = O°C to
75°C for DIP, Airflow;" 2.5 mis,
T c = O°C to 75°C for Flat
Package and LCC, unless
otherwise noted.)

Read Cycle
MBM10480·15
Typ
Min

MBM10480·25
Min
Typ
Max

Parameter

Symbol

Address access time

tM

15

25

ns

Chip select access time

t ACS

8

10

ns

Chip select recovery time

tACS

8

10

ns

Max

Unit

Write Cycle

Parameter

Symbol

MBM10480·15
Min
Typ

Write pulse width

tw

15

Write disable time

tws

8

10

ns

Write recovery time

tWA

18

20

ns

Address set up time

tWSA

2

5

ns

Chip select set up time

twscs

2

5

ns

Max

MBM10480·25
Min
Typ
Max

Unit

25

ns

Data set up time

t WSD

2

5

ns

Address hold time

tWHA

3

5

ns

Chip select hold ti me

tWHCS

3

5

ns

Data hold time

tWHD

3

5

ns

Read Cycle Timing Diagram

S

OUT

-----J]

Write Cycle Timing Diagram

ADDRESSES

w
OUT

FUJITSU
9-46

MBM10480·15
MBM10480·25

Rise Time and Fall Time
Parameter

Symbol

Output rise time

t,

Min

Typ

Output fall time

Max

ns

3

ns

AC Test Conditions
GND

-0.9V--~~

-1.7V-=1l

Vee

~

~

r:-

~

tr = It = 2.5na typ
OUTPUT LOAD: R. = SOIl

C. = 30pF
(INCLUDING PROBE AND STRAY CAPACITANCE)

NOTE: ALL TIMING MEASUREMENTS REFERENCED TO 50% INPUT LEVELS.

Package Dimensions
Dimensions in inches
(millimeters)

20·Lead Ceramic ICERDIPI Dual In·Llne Package
ICsse No.1 DIP.20C·C031

'~1I. :::::::: :B~
I
.940(23.88)
1.000(25.4)

9·47

..

Unit

3

11111110480.1 •
...1110480-25·

Packa. . Dlmenal_s
(continued)
Dimensions in inches
(millimeters)

ZO·Lead c...amlc ICERDIP) Flat Package
ICase NO.1 FPT.ZOC·C01)

.

.482(12.24)
.500(12.70)
.014(0.35)
.019(0.48)

I

I"
-I

~

.085(2.16)
.. MAX

~

.250(6.35)

.350(8.89)

lJ.UUU.LIL.u....u...u...u...l.\

T'

J~.'

.384( 9.75)

lmr"1T"TMMrnrrnrTf·

Je=

.250(6.35)
.350(8.89)

~

I

I .050(1.27)
.445(11.30~."TVP
.455(11.58)

I I

~

~

.004(0.10)
... 006(0.16)
.030(0.76)
.045(1.14)

Zo.Pad Ceramic IFRIT SEAL) Leadless Chip Carrier
ICase No: LCC·ZOC.F01)
PIN NO.1 INDEX

o

n
.420(10.67)

bdJ'~

..

.295(7.49)

,00(2.54)
1.MAX

·S.HAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

9-48

FUJITSU

Bipolar Memories
•

MBM100480·15, MBM100480·25
16384-Bit Bipolar Eel
Random Access Memory

De.criptlon
The Fujitsu MBM100480 is a fully decoded 16384-bit ECl
read/write random access memory designed for main memory, control and buffer storage applications. This device is organized as
16384 words by one bit, and it features on-chip voltage/temperature
compensation for improved noise margin.
The MBM100480 offers extremely small cell and chip size, realized
through the use of Fujitsu's patented DOPOS (Doped Polysilicon),
as well as lOP-II (Isolation by Oxide and Polysilicon), processing.
Operation for the MBM100480 is specified over a temperature
range of from O°C to 85°C (TA for DIP, Tc for Flat Package and
lCC). It also features 20-pin Ceramic DIP, Flat Package, and lCC,
and is fully compatible with industry standard 100K-series ECl
families.

Feature.
•

16384 words x 1 bit
organization
• On-chip voltage/
temperature compensation
for Improved noise margin
• Fully compatible with Industry standard 100K-series
EClfamilies
• Address access time:
15 ns max. (MBM100480-15)
25 ns max. (MBM100480-25)

Chip select access time:
8 ns max. (MBM100480-15)
10 ns max. (MBM100480-25)
• Open emitter output for
ease of memory expansion
• low power dissipation of
0.04 mW/blt
• DOPOS and lOP-II
• Pin compatible with the
F100480
•

Small geometry bipolar integrated
circuits are occasionally susceptible
to damage from static voltages or
electric fields. It is therefore

advised thai normal precautions be
taken to avoid application of any

voltage higher than maximum rated
voltages to this device.

9-49

MBM100480·15
MBM100480·25

MBM100480 Block Diagram
and Pin Asslgnmants
Vee·

OUT

W

D'N

Ao

D

A,

Ii

A2

W

Ao

A13

A.

A'2

A5

All

Ao

A,.

A7

A.

VEE

A,

Dual In.Line Package
(TOP VIEW)
TRUTH TABLE
INPUT
OUTPUT
S

MODE

W DIN

H

X

X

L
L
L

L
L
H

H
L
X

Al
L
L
L
OUT

DISABLED
WRITE"H"
WRITE "a.:'
READ

A2
A3
A,

H = HIGH VOLTAGE LEVEL

AS

L = LOW VOLTAGE LEVEL
X = DON'T CARE

A6

-,3 I

r-

118 Ii

-~
• I

f--

Vee·
D

1'7 iii

-~

1--

A,

r-

A2
A,

1--

Ao

5 I

,,6 A'3

6,

,IS A12

-~

-1
71

II. All

81

113 A'0
L_

S
W
A13
A12
All
A,.
A.
A,

r-

-i
_J

r-.,..-,..-,--,
I 9 110111 I 12 I

VEE

A7 VEE AS Ag

Leadless Chip Ca....ier

'Vee GROUNDED

Flat Package

Functional Description
The Fujitsu MBM100480 is a fully
decoded 16384 bit read/write random access memory organized
as 16384 words by one bit. Memory cell selection is achieved by
means of a 14-bit address
designed Ao through A ,3 . The

active low Chip Select (S) input is
provided for memory expansion.
The read and write operations
are controlled by the state of the
Enable (W) input. With iii and S
held low, the data at DIN is written Into the addressed location.
To read, W is held high, while

S is held low.

Data at the addressed location is then transferred to OUT and read out noninverted. Open emitter outputs
are provided to allow for maximum flexibility in output wired-OR
connection.

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

VEE pin potential to ground pin

+0.5 to -7.0

V

Input voltage

VEE
VIN

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

rnA

TA for DIP

-55 to +125

'C

Temperature under bias

Tc for flat
package and LCC

-55 to +125

'C

Storage temperature

TSTG

-65 to +150

'C

Note: Permanent device damage may occur it ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU
9-50

MBM100480·15
MBM100480·25

Guaranteed Operating
Conditions
(Referenced to Veel
Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature for DIP,
Case Temperature for Flat
Package and LCC

Supply voltage

VEE

-5.7

-4.5

-4.2

V

O°Cto 85°C

Capacitance
Parameter

DC Characteristics
(Vee ~ OV, VEE ~ -4.5V, Output
Load ~ 500 and 30pF to -2.0V,
TA ~ O°C to 85°C for DIP, Airflow
>2.5m/s, Te ~ O°C to 85°C for
Flat Package and LCC, unless
otherwise noted.)

Symbol

Min

Typ

Unit

5

pF

Output pin capacitance

6

pF

Parameter

Symbol

Min

Output high voltage
(VIN ~ VIH max or VIL min)

Max

Unit

VOH

Output low voltage
(VIN ~ V IH max or VIL min)

-1025

-880

mV

VOL

-1810

-1620

mV

Output high voltage
(VIN ~ VIH min or VIL max)

VOHC

-1035

Output low voltage
(VIN ~ VIH min or VIL max)
Input high voltage
(guaranteed input voltage high for all inputs)

VIH

Input low voltage
(guaranteed input voltage low for all inputs)

Typ

mV
-1610

mV

-1165

-880

mV

-1810

-1475

mV

Input high current (VIN ~ VIH max)

220

Input low current (VIN ~ V IL min)

-50

S input low current (VIN ~ V IL min)

0.5
MBt-1100480-25

p.A
p.A

170

p.A

-220

MBM100480-15

Power supply current
(all inputs and output open)

AC Characteristics
(Vee ~ OV, VEE = -4.5 ±5%,
Output Load = 50n to -2.0V
and 30pF to GND, TA = O°C to
85°C for DIP, Airflow .. 2.5 mis,
T e = O°C to 85°C for Flat
Package and LCC, unless
otherwise noted.)

Max

Input pin capacitance

lEE

mA

-220

Read Cycle
MBM100480·15
Typ
Min
Max

MBM100480·25
Min
Typ
Max

Parameter

Symbol

Address access time

tM

Chip select access time

tAes

8

10

ns

Chip select recovery time

tRcs

8

10

ns

15

Read Cycle Timing Diagram

§

~I.C.-'
I";" {I"~50%

OUT

9-51

80%
SO%
20%

25

Unit
ns

MBM100480·15
MBM100480·25

Write Cycle

Parameter

Symbol

MBM100480·15
Min
Typ
Max

MBM100480·25
Typ
Min
Max

Write pulse width

tw

15

25

Write disable time

tws

Write recovery time

tWA

Address set up time

t WSA

2

5

Chip select set up time

twscs

2

5

ns

Data set up time

t WSD

2

5

ns
ns

Unit
ns

8
18

10

ns

20

ns
ns

Address hold time

tWHA

3

5

Chip select hold time

t WHCS

3

5

ns

Data hold time

tWHD

3

5

ns

Write Cycle Timing Diagram

ADDRESSES

w
OUT

Rise Time and Fall Time
Parameter

Symbol

Output rise time

t,

Min

3

Typ

ns

Output fall time

Ir

3

ns

Max

AC Test Conditions
GND

::~

Vee

,

OUT

~

tr

= It

= 2.5"5 typ

L-_..:.Vr:EE'--l RL
OUTPUT LOAD: RL = son
CL = 30pF
(INCLUDING PROBE AND STRAY CAPACITANCE)

-2.0V

NOTE: ALL TIMING MEASUREMENTS REFERENCED TO 50% INPUT LEVELS.

FUJITSU
9·52

Unit

MBM100480·15
MBM100480·25

Package Dimensions
Dimensions in inches
(millimeters)

20·Lead Ceramic ICERDIP) Dual In·Llne Package
ICase No.: DIP.20C.C03)

2C1-Lead Ceramic ICERDIP) Flat Package
ICase No.: FPT·20C.C01)

.482(12.24)
.500(12.70)

--..!
.I

I"

.014(0.35)
.019(0.48)

I

.085(2.16)

.. MAX

-t
.250(6.35)
.350(8.89)

~J.L.JJ...JJ....rl

J

irTtMrrTr-n."..,.,..tMrrT(.

.025(0.64)
MAX

..

.1

.384( 9.75)
•400(10.16)

~~

.350(8.89)

_

I
.445(11.30~

~)
TYP

.455(11.56)

9-53

--lI ...

~

004(0.10)
.006(0.16)
.030(0.76)
.045(1.14)

MBM100480·15
MBM100480·25

Packa.e Dimensions
(continued)
Dimensions in inches
(millimeters)

20·Pad Ceramic (FRIT SEAL) Leadle.s Chip Carrier
(Case No. LCCo2GC-F01)

PIN NO.1 INDEX

\
o

n
.420(10.67)
.435(11.05)

.280(7.11)
•. 295(7.49)

..

100(2.54)
1.MAX

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

9-54

FUJITSU

Bipolar Memories
•

MBM10484·15
16384-Bit Bipolar Eel
Random Access Memory

Description
The Fujitsu MBM10484 is a fully decoded 16,384-bit ECl read/write
random access memory designed for main memory, control, and
buffer storage applications. The device is organized as 4,096
words by 4-bits, and it features on-chip voltage compensation for
improved noise margin.
The MBM10484 offers extremely small cell and chip size, realized
through the use of Fujitsu's patented DOPOS (Doped Polysilicon),
as well as lOP-II (Isolation by Oxide and Polysilicon), processing.
Operation for the MBM10484 is specified over a temperature
range of O"C to 75'C (TA for DIP, Tc for Flat Package). The
MBM10484-15 features a 28-pin Ceramic DIP or Flat Package,
and is fully compatible with industry standard 10K-series ECl
families.

Features
•

4096 words x 4-bits
organization
• On-chip voltage
compensation for improved
noise msrgln
• Fully compatible with
Industry standard
10K-series ECl families
• Address access time:
15 ns max.

•

Chip select access time:
B ns max.
Open emitter output for
ease of memory expansion
• low power dissipation of
0.07 mW/bit
• DOPOS and lOP-II
•

9-55

MB..,,10484-15

MBM10484 Block Diagram
and Pin Assignment

Vee

Vee

0,

0,

Cla

00

Ao

0,

I

A,

0,

I

A,

0,

~

A,

Do

I

I

I

MEMORY CELL ARRAY

A4

W,

As

EO-----j

If/,/W, 0----1

As

lf/,

A,

NO

A,

A"

NO

AlO

VEE

A.

FPT Pinout Is Equivalent

TRUTH TABLE
INPUT

a

E

W,/!f12

IN

H
L
L
L

X

X

-L
"L
"H

H
L
X

L
L
L
OUT

'L = BOTH Vii AND ~ ARE LOW,
'H = EITHER Wl,.OR W2 'S HIGH,
DR BOTH W'S ARE HIGH,

MODE

0,

DISABLED
WRITE "H"
WME"L"
READ

D,

D, Do

E ~W;

2.

23 22

21

20

lEADlESS
CERAMIC CHIP
CARRIER

H = HIGH VOLTAGE LEVEL
L = LOW VOLTAGE LEVEL
X = DON'T CARE

A,

A,

8

A, A4

9

NO

17

A"

16

AlO
A,

15

,.

(TOP VIEW)
7

"18

10

VEE
NO

13
12
11

Aa

As As A,

Functional Description
The Fujitsu MBM10484 is a fully
decoded 16384-bit read/write random access memory organized
as 4096 words by 4-bits, Memory
cell selection is achieved by
means of a 12-bit address
designed An through A", The

Absolute Maximum Ratings
(See Note)

active low Chip Enable (E) input
is provided for memory expansion, The read and write operations are controlled by the state
of the active low Write Enable
(W) inputs, With Wand E held
low, the data at IN (Do-D3) is
written into the addressed
location,

To read, Ware/is held high, while
E is held low, Data at the
addressed location is then transferred to OOUT (00-03) and read
out non-inverted. Open emitter
outputs are provided to allow for
maximum flexibility in output
wired-OR connection.

Rating

Symbol

Value

Unit

VEE pin potential to ground pin

+0.5 to -7.0

V

Input voltage

VEE
V,N

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

mA

TA for DIP

-55 to +125

'C

Temperature under bias

Tc forllat
package

-55 to +125

'C

Storage temperature

T STG

-65 to +125

'C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU

9-56

MBM10484·15

Guaranteed Operating
Conditions
(Referenced to Veel
Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature for
DIP, Case Temperature
for Flat Package

Supply voltage

VEE

-5.46

-5.2

-4.94

V

O'C to 75'C

Capacitance

DC Characteristics
(Vee = OV, VEE = -5.2V, Output
Load = 50n to -2.0V, TA = O'C
to 75'C for DIP, Airflow >2.5m/s,
Te = O'C to 75'C for Flat
Package, unless otherwise
noted.)

Symbol
CIN

4

pF

Output pin capacitance

COUT

6

pF

Parameter

Symbol

Min

Output high voltage
(VIN = VIH max or VIL min)

VOH

Output low voltage
(VIN = VIH max or VIL min)

Typ

Typ

Max

Operating
Temperature

Max

Unit

-1000
-960
-900

-840
-810
-720

mV

O'C
25'C
75'C

VOL

-1870
-1850
-1830

-1665
-1650
-1625

mV

O'C
25'C
75'C

Output high voltage
(VIN = VIH min or VIL max)

VoHe

-1020
-980
-920

mV

O'C
25'C
75'C

Output low voltage
(VIN = VIH min or VIL max)

VOLe

-1645
-1630
-1605

mV

O'C
25'C
75'C

Input high voltage
(guaranteed input voltage high for
all inputs)

VIH

-1145
-1105
-1045

-840
-810
-720

mV

O'C
25'C
75'C

Input low voltage
(guaranteed input voltage low for
all inputs)

VIL

-1870
-1850
-1830

-1490
-1475
-1450

mV

O'C
25'C
75'C

Input high current (VIN

= VIH max)
= VIL min)
E input low current (VIN = VIL min)

IIH

Input low current (VIN

IlL

-50

IlL

0.5

lEE

-240

Power supply current
(all inputs and outputs open)

AC Characteristics
(Vee = OV, VEE = -5.2 ±5%,
Output Load = 50n to -2.0V
and 30pF to GND, TA = O'C to
75'C for DIP, Airflow >2.5 mis,
Te = O'C to 75'C for Flat
Package, unless otherwise
noted.)

Min

Unit

Parameter
Input pin capacitance

220

170

p.A

O'C to 75'C

p.A

O'C to 75'C

p.A

O'C to 75'C

rnA

O'C to 75'C

Read Cycle
Parameter

Typ

Max

Unit

12.0

15.0

ns

t ACS

8.0

ns

t RCS

8.0

ns

Symbol

Address access time

tAA

Chip enable access time
. Chip enable recovery time

9-57

Min

MBM10484·15

AC Characteristics
(continued)
(Vcc = OV, VEE = -S.2 ±S%,
Output Load = SOO to -2.0V
and 30pF to GND, T A = DoC to
7SoC for DIP, Airflow ;;.2.S mis,
T c = DoC to 7SoC for Flat
Package, unless otherwise
noted.)

Read Cycle Timing Diagram

Q

Write Cycle
Parameter

Symbol

Min

Write pulse width

tw

1S.0

Write disable time

tws

Typ

Max

Unit

8.0

ns

17.0

ns

ns

Write recovery time

tWR

Address set up time

t WSA

3.0

Chip enable set up time

twscs

3.0

ns

Data set up time

t WSD

3.0

ns

Address hold time

tWHA

2.0

ns

Chip enable hold time

t WHCS

2.0

ns

Data hold time

tWHD

2.0

ns

ns

Write Cycle Timing Diagram

E

ADDRESSES

D

W

-----Q

Rise Time and Fall Time
Parameter

Symbol

Output rise time

tr

2.S

ns

Output fall time

It

2.S

ns

FUJITSU
9-58

Min

Typ

Max

Unit

MBM10484·15

AC Test Conditions
GND

:~

Vee
Q

VEE
O.OI1'F

I

~

~

Ir =

RL

tr = 2.5ns typ

OUTPUT LOAD, RL = 50Il
CL = 30pF
(INCLUDING PROBE AND STRAY CAPACITANCE)

-2.0V
VEE

NOTE, ALL TIMING MEASUREMENTS REFERENCED TO 50% INPUT LEVELS.

Peckage Dimensions
Dimensions in inches
(millimeters)

28·Lead Ceramic (Metal Seal) Dual In.Llne Package
(Ca.e No.1 Dlp.28CoA06)

--.~

1.38O(35.OS)
1.420(38.07)

R.050(1.27)REF

[[]

1

.374(9.50)
.403(10.24)

L--L...--=--=-"'~!!!i='i!!F"E~...........--..."..J~

~
~

[4-=r

.350(9.91)

.008(0.20)
.012(0.30)

~200(S.08)MAX

.090(2.29
.110(2.T9)

~I

.040(1.02) ...11
.060(1.S2)

1.300(33.02)REF

9·59

I

...015(0.38)

.00000.S8)
•

.040(1.02)
.060(1.52)

+ .120(3.05)
.150(3.81)

A1
)

MBM10484.15

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

28·Lead Ceramic ICERDIP) Flat Package
ICase NO.1 FPT·28CoC01)

.004(0.10)
.008(0.16)

-r.250(6.35)
.350(8.69)

+

t

.375(9.53)
INDEX AREA

~lrr'rnrlTT1'TTTnrlTT1'TTTITT1-r1

.900(22.B6)MIN

__
,4OO(-lr6)

t

INDEXPIN#I
/
===-"-'---/

.250(6.35)
.350(8.89)

-

I .050(1::~ I
..

..

~.014(0.35)
.. •018(0.48)

14-_ _ _.764~5(1',;6.~38:l_)--_+I ...028(0.71)MAX
.655(16.64)
.677(17.20)

28·Pad Ceramic IFrit Seal) Leadless Chip Carrier
ICase NO.1 LCC.28CoF01)

PIN NQ I INDEX

/
.015(0.38)
.445(11.30)
.460(11.68) SO

9-60

FUJITSU

Bipolar Memories
•

MBM100484·15
16384-Bit Bipolar Eel
Random Access Memory

D.scriptlon
The Fujitsu MBM1004B4 is a fully decoded 16.3B4-bit ECl
read/write random access memory designed for main memory.
control. and buffer storage applications. The device is organized as
4.096 words by 4-bits. and it features on-chip voltage and temperature compensation for improved noise margin.
The MBM1004B4 offers extremely small cell and chip size. realized
through the use of Fujitsu's patented DOPOS (Doped Polysilicon).
as well as lOP-II (Isolation by Oxide and Polysilicon). processing.
Operation for the MBM100484 is specified over a temperature
range of O°C to B5°C (TA for DIP, T c for Flat Package). The device
also features 2B-pin Ceramic DIP or Flat Package. and is fully
compatible with industry standard 100K-series ECl families.

F••tur••
• 4096 words X 4-blts
organization
• On-chip vOltage and
temperature compensation for
improved noise margin
• Fully compatible with
industry standard
100K-serles ECl families
• Address access time:
15 ns max.

• Chip select access time:
8 ns max.
• Open emitter output for
ease of memory expansion
• Low power dissipation of
0.06 mW/blt
• DOPOS and lOP-II

9-61

MBMIC1q484.15

MBMI00484 Block Diagram
and Pin Assignment

A7

A,

Vee

a,
0,
AO

,I

A,

I

I

I
I
MEMORY CELL ARRAY

A,

I
I
,

A3

I

A.

I

I

A5

I
I

A.

A7
E 0----1
W,/W2 0----1

A,

NC
VEE
Do

TRUTH TABLE
INPUT
is W, iW2
H
X
L
'L
L
'L
L
'H

Do

0,

0,

02

a.

0,

a.
FPT Pinout Is Equivalent

IN
X

H
L
X

0

MODE

L
L
L
OUT

DISABLED
WRITE"H"
WRITE "L"
READ

LEADLESS
CERAMIC CHIP
CARRIER

28

'L = BOTH W.1.AND W2 ARE LOW.
'H = EITHER WLOR W2 IS HIGH,
OR BOTH W'S ARE HIGH.

NC
A11
A10
A,

27

H = HIGH VOLTAGE LEVEL
L = LOW VOLTAGE LEVEL
X = DON'T CARE

Vee

a.

VEE
NC

(TOP VIEW)

0,

3

Ao

4

5

6

7

8

9

As

10

A, A, A, A. A5 A. A7

Functional Description
The Fujitsu MBM100484 is a fully
decoded 18384 bit read/write random access memory organized
as 4096 words by 4 bit. Memory
cell selection is achieved by
means of a 12-bit address
designed Ao through A", The

Absolute Maxlml!m Ratings
(See Note)

active low Chip Enable (E) input
is provided for memory expansion. The read and write operations are controlled by the state
of the active low Write Enable
(iN) inputs. With Vii and E held
low, the data at DIN (00-03) is
wrijten into the addressed loca-

Rating

tion. To read, Vii are/is held high,
while E is held low. Data at the
addressed location is then transferred to 00UT (00-03) and read
out non-inverted. Open emitter
outputs are provided to allow for
maximum flexibility in output
wired-OR connection.

Symbol

Valua

Unit
V

Input voltage

VEE
VIN

+0.5 to -7.0
+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

mA

TA for DIP

-55 to +125

·C

Temperature under bias

Tc for flat
package

-55 to +125

·C

Storage temperature

TSTG

-65 to +125

·C

VEE pin potential to ground pin

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU
9-62

MBM100484·15

Guaranteed Operating
Conditions
(Referenced to Vcd
Parameter

Symbol

Supply voltage

Min

Typ

Max

Unit

-5.7

-4.5

-4.2

V

Ambient Temperature for
DIP, Case Temperature
for Flat Package

Capacitance

DC Characteristics
(Vcc = OV, VEE = -4.5V, Output
Load = 500 to -2.0V, TA = O°C
to 85°C for DIP, Airflow >2.5m/s,
Tc = O°C to 85°C for Flat
Package, unless otherwise
noted.)

AC Characteristics
(Vcc = OV, VEE = -4.5 ±5%,
Output Load = son to -2.0V
and 30pF to GND, T A = O°C to
85°C for DIP, Airflow ;;.2.5 mis,
T c = O°C to 85°C for Flat
Package, unless otherwise
noted.)

Parameter

Symbol

Input pin capacitance

CIN

4

pF

Output pin capacitance

COUT

6

pF

Min

Typ

Max

Max

Unit

-1025

-880

mV

VOL

-1810

-1620

mV

VOHC

-1035

Parameter

Symbol

Min

Output high voltage
(VIN = VIH max or VIL min)

VOH

Output low voltage
(VIN = VIH max or VIL min)
Output high voltage
(VIN = VIH min or VIL max)
Output low voltage
(VIN = VIH min or VIL max)

VOLC

Input high voltage
(guaranteed input voltage high for
all inputs)

V IH

Input low voltage
(guaranteed input voltage low for
all inputs)

VIL

Typ

Unit

mV
-1610

mV

-1165

-880

mV

-1810

-1475

mV

220

Input high current (VIN = VIH max)

IIH

Input low current (VIN = VIL min)

IlL

-50

E input low current (VIN = VIL min)

IlL

0.5

Power supply current
(all inputs and outputs open)

lEE

-240

IJ.A
IJ.A

170

IJ.A
mA

Read Cycle
Parameter

Symbol

Address access time

tM

Min

Typ

Max

Unit

12.0

15.0

ns

Chip enable access time

tACS

8.0

ns

Chip enable recovery time

tRCS

8.0

ns

Read Cycle Timing Diagram

E

50%.

80%
Q

a

9·63

MBM100484·15

AC Characteristics
(continued)
(Vcc = OV, VEE = -4.5 ±5%,
Output Load = 500 to -2.0V
and 30pF to GND, TA = DoC to
85°C for DIP, Airflow ;;.2.5 mis,
T C = DoC to 85°C for Flat
Package, unless otherwise
noted.)

Write Cycle
Max

Typ

Parameter

S!mbol

Min

Write pulse width

tw

15.0

Write disable time

tws

8.0

Write recovery time

tWA

17.0

Address set up time
Chill enable set up time

set up time

Data

Address hold time
Chip enable hold time
Data hold time

Unit
ns
ns
ns

tWSA

3.0

ns

twscs

3.0

ns

twso

3.0

ns

tWHA

2.0

ns

tWHCS

2.0

ns

t WHO

2.0

ns

Write Cycle Timing Diagram

~

ADDRESSES

~

J

J

- ~Dt

~~-

o

w

------Q

____-=1wsA

tw

r---~--

-

Rise Time and Fall Time

-~A-_
~es

50%

50%\

tws~

-tWR

Parameter

Symbol

Output rise time

t,

2.5

ns

Output fall time

It

2.5

ns

Min

Typ

Max

AC Test Conditions
GND

::~

Vee

,

Q

L...--r~--'

tr = If =

2.5"s typ

-

RL
OUTPUT LOAD: RL = 5011
CL
30pF
(INCLUDING PROBE AND STRAY CAPACITANCE)

=

VEE
NOTE: ALL TIMING MEASUREMENTS REFERENCED TO 50% INPUT LEVELS.

FUJITSU
9-64

Unit

MBM100484·15

Package Dimensions
Dimensions in inches
(millimeters)

28·Lead Ceramic IMetal Seal) Dual In· Line Package
ICase No.• DIP.28C·A06)

_"O~_9'

1.380(35.05)
1.420(36.07)

R.05O(I.27)REF

~~~JO.24)
~ [ ]]] I

--

.374(9.50)

'J.91)

[

.4110.41)

t

~
~

.008(0.20)
.012(0.30)

[dj2OO(5.08)MAX

.090(2.29)
.110(2.79)

I

__

I

.040(1.02) .... 11 •.015(0.38)
.060(1.52)
.023(0.58)

.040~.02):

.060(1.52)

.120(3.05)
.150(3.81)

•

1.300(33.02)REF

28·Lead Ceramic ICERDIP) Flat Package
ICase No •• FPT·28C·C01)
.004(0.10)
.006(0.1

-1.250(6.35)
.350(8.89)

1-J.-l.Ll.'UJ...LLlL.U...1.LJLLLL1.L.Ll.11.J.I,-+

t

.375(9.53)
INDEX AREA

~fnJrTTTTTTrTT"ITT1rTT"1rTTTTTT~_·4O-1rI6)

-"IN",D",E"X-,-P-"IN,-,#,,--,-I_~/

.900(22.86)MIN

.2sol.3S)
.350(6.89)

II .050(1~:~ II

_.

..

.014(0.35)
• .019(0.48)

1~____~·MF.5m(I~6·736~)____~
.655(16.64)

.677(17.20)
.706(17.93)

9·65

-+.028(0.71)MAX

-

:::~:~I·

• .090(2.29)MAX

MBM100484·15

Package Dlmen.lons
(Continued)
Dimensions in inches
(millimeters)

28.Pad Ceramic IFrit Saall Leadle•• Chip Carrier
ICa. . No.: LCC.28C.F011

PIN NQ 1 INDEX

/

I.

,I

.445(11.30)
•460(11.88)

sa

•

.015(0.38)
• •066(1.85) TYP
...045(1.14) TYP

9·66

FUJITSU

Bipolar Memories
•

MBM10490
65,536-Bit Bipolar Eel
Random Access Memory

Description
The Fujitsu MBM10490 is a fully decoded 65,536-bit ECl
read /write random access memory designed for main memory,
control, and buffer storage applications. The device is organized as
65,536 words by 1-bit, and it features on-chip voltage compensation for improved noise margin.
The MBM 10490 offers extremely small cell and chip size, realized
through the use of Fujitsu's patented lOP-II (Isolation by Oxide and
polysilicon) and fine lithography processing.
Operation for the MBM10490 is specified over a temperature range
of DoC to 75°C (TA for DIP, Te for Flat Package). It also features
22-pin Ceramic DIP or Flat Package, and is fully compatible with
the industry standard 10K-series ECl families.

fo-

rfo-

~

~

f--

Features

• 65,536 words x 1-blt
organization
On-chip voltage compensation for improved noise
margin
• Fully compatible with Induatry standard 10K-series Eel
families
• Address access time:
15 ns max_ (MBM10490-15)
25 ns max. (MBM10490-25)

•

Open emitter output for
ease of memory expansion
low power dissipation of:
0_024 mW/blt max_
(MBM1049O-15)
0.014 mW/blt max.
(MBM1049O-25)
• DOPOS and lOP-II

•

-

•

Small geometry bipolar integrated
circuits are occasionally susceptible
to damage from static voltages or
electric fields. It is therefore
advised that normal precautions be
taken to avoid application of any
voltage higher than maximum rated
voltages to this device.

9-67

fofo-

r-

•
...

... 1..,

'--

f-f--

MBMt0490

MBMt0490 Block Diagram
and Pin Assignments
A.,

Vee
D

A,

S

A,

iR

Ao

A,.

Q

11

W

A.,

A'4

As

A'3

As
A,

A"
Al1

0

TRUTH TABLE
INPUT
S iN IN
H X
L L
L L
L H

X

H
L
X

OUTPUT

MODE

L
L
L
OUT

DISABLED
WRITE"H"
WRITE "t!'
READ

1
2
3
4
5
6
7
8

9
10
11

As

A,O

VEE

As

22
21
20
19
18
17
16
15
14
13
12

As

As
A.
A,
As
VEE

As
A,o
Al1
A"
Au

H = High Voltage Level
L = Low Voltage Level
X = Don't Care

Functional Description
The Fujitsu MBM10490 is a fully
decoded 65,536-bit read/write
randDm access memory organized as 65,536 words by 1-bit.
Memory cell selection is achieved
by means of a 16-bit address designed ~ through A, Q.' The active low Chip Select (S) input is

provided for memory expansion.
The read and write operations
are controlled by the state of the
active low Write Enable (W) input. With Wand S held low, the
data at D is written into the addressed location. To read, W is

held high, while S is held low.
Data at the addressed location is
then transferred to Q and read
out non-inverted. Open emitter
outputs are provided to allow for
maximum flexibility in output
wired-OR connection.

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

VEE pin potential to ground pin

VEE

+0.5 to -7.0

V

Input voltage

V IN

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

mA

TA for DIP

-55 to +125

·C

T c for flat-package

-55 to +125

·C

TSTG

-65 to +150

·C

Temperature under bias
Storage temperature

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detaiJed in the operational sections of this data sheet.

FUJITSU
9-68

MBM10490

Capacitance
Parameter

Symbol

Min

Max

Unit

Input pin capacitance DIP /FPT

2.0/1.0

5.0/4.0

pF

Output pin capacitance DIP /FPT

3.0/2.0

6.0/4.0

pF

Guaranteed Operating
Conditions
(Referenced to Vcd

DC Characteristics
(Vcc = OV, VEE = -5.2V, Output
load = 50n to -2.0V, TA = O°C
to 75°C for DIP, Tc = O°C to
75°C for Flat Package, Airflow
;>2.5m/s, unless otherwise
noted.)

Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature for DIP,
Case Temperature for Flat
Package

Supply voltage

VEE

-5.46

-5.2

-4.94

V

O°C to 75°C

Symbol

Min

Max

Unit

Output high voltage
(VIN = VIH max. or VIL min.)

VOH

-1000
-960
-900

-840
-810
-720

mV

Output low voltage
(VIN = VIH max. or VIL min.)

VOL

-1870
-1850
-1830

-1665
-1650
-1625

mV

O°C
25°C
75°C

Output high voltage
(VIN = VIH min. or VIL max.)

VOHC

-1020
-980
-920

mV

O°C
25°C
75°C

Output low voltage
(VIN = V IH min. or V IL max.)

VOLC

-1645
-1630
-1605

mV

O°C
25°C
75°C

Input high voltage
(guaranteed input voltage
high for all inputs)

V IH

-1145
-1105
-1045

-840
-810
-720

mV

O°C
25°C
75°C

Input low vo~age
(guaranteed input voltage low
for all inputs)

VIL

-1870
-1850
-1830

-1490
-1475
-1450

mV

O°C
25°C
75°C

Input high current (VIN = VIH max.)

IIH

110

/LA

O°C to 75°C

S input high current (VIN

IIH

220

/LA

O°C to 75°C

Parameter

= VIH max.)

Typ

Ta/TIj
O°C
25°C
75°C

Input low current (VIN = VIL min.)

IlL

-50

90

/LA

O°C to 75°C

S input low current (VIN

IlL

0.5

170

!LA

O°C to 75°C

rnA

O°C to 75°C

= VIL min.)

Power supply current
(all inputs and outputs open)

MBM10490-15
MBM10490-25

9-69

-300
lEE

-200

MBM10490

AC Characteristics
(Vee = OV, VEE = -5.2V ±5%,
Output Load = 500 to -2.0V
and 30 pF to GND, TA = O'C to
75'C for DIP, Te = O'C to 75'C
for Flat Package, Airflow ;;.2.5
mis, unless otherwise noted.)

Read Cycle
Parameter

Symbol

MBM10490·15
Min
Typ
Max

MBM10490·25
Min
Typ
Max

Unit

Address access time

15

25

Chip select access time

10

15

ns
ns

Chip select recovery time

10

15

ns

Read Cycle Timing Diagram

ii

f

~

50%

I+'AC-' '1.-,oc;8O%
50%

Q

AOORESS~

50%

~I~----'AA-_---~"T"""-50%

Q

~

------'1

-~Write Cycle
Parameter

Symbol

MBM10490·15
Min
Typ
Max

MBM10490·25
Min
Typ
Max

Unit

Write pulse width

tww

15

20

ns

Write disable time

tws

10

20

Write recovery time

tWR

17

25

Address set up time

tSA

2

Chip select set up time

tse

2

3

ns

Data set up time

tso

2

3

ns

3

ns
ns
ns

Address hold time

tHA

2

ns

Chip select hold time

tHe

2

ns

Data hold time

tHO

2

ns

FUJITSU
9·70

MBM10490

AC Characteristics
(Continued)
(Vcc = OV, VEE = -5.2V ±5%,
Output Load = 50n to -2.0V
and 30 pF to GND, TA = OOG to
75°G for DIP, Tc = O°C to 75°C
for Flat Package, Airflow ;;.2.5
mis, unless otherwise noted.)

Write Cycle Timing Diagram

ADDRESS

D

----------------+~
Q

Rise Time and Fall Time
Parameter

Symbol

Min

Max

Output rise time -15/-25

t,

1.0/1.0

2.0/3.0

ns

Output fall time -15/-25

1.0/1.0

2.0/3.0

ns

OUTPUT LOAD:

INPUT WAVEFORM

AC Test Conditions
RL

= SOH

CL=30pF
(INCLUDING PROBE AND
STRAY CAPACITANCE)

-1.7V _ _ _ _JI

'R

GND

"

tR "" IF = 2.5 ns TYP
NOTE: ALL TIMING MEASUREMENTS REFERENCED 50% INPUT LEVELS.

Vee

VEE

O.01,uF

~

VEe

9·71

Unit

MBM10490

Package Dimensions
Dimensions in Inches
(millimeters)

22·Lead Ceramic IMetal Seall Dual In·Llne Package
ICase No.• DIP.22C.A021

1

~~ :~~~: :I ;13~·
I

1.090(27.69)

.014(0.36)

ltmimfflftB.2OO(S.08)MAX
~I

.090(2.29)
.110(2.79)

.120(3.05)
.150(3.81)

...042(1.09}
.054(1.37)
..

I

-J I...

015(0.36)
.023(0.58)

1.000(25.40)REF

·00000.Sl)
.050(1.27)

•

22·Lead Ceramic ICerdlpl Flat Package
ICase No•• FPT·22C.C011

.030(0.78) MAX

+

I

f

.352(8.94)
.360(9.14)

.300(7.62) TYP

1•

r

.007S(0.19)
.010S(0.27)

INDEX AREA
920(23.37)
960(24.38)

•
.090(2.29) MAX

.190(4.83)
.210(5.33)

I..

9·72

~

I

I
.S32(13.51)
.540(13.72)

.I.

.190(4.83)
.210(5.33)

.I

i

.004(0.10)
.006(0.15)

[.032(1.81)
.042(1.07)

FUJITSU

Bipolar Memories
•

MBM100490
65,536-Bit Bipolar Eel
Random Access Memory

Description
The Fujitsu MBM100490 is a fully decoded 65,536-bit ECl
read/write random access memory designed for main memory,
control, and buffer storage applications. The device is organized as
65,536 words by I-bit, and it features on-Chip voltage and temperature compensation for improved noise margin.
The MBM100490 offers extremely small cell and chip size, realized
through the use of Fujitsu's patented lOP-II (Isolation by Oxide and
polysilicon) and fine lithography processing.

/"-,

-

-

Operation for the MBM100490 is specified over a temperature
range of O°C to 85°C (TA for DIP, Tc for Flat Package). It also features 22-pin Ceramic DIP or Flat Package, and is fully compatible
with the industry standard lOOK-series ECl families.

~~
...

f-

r-

Features
• Open emitter output for ease
• 65,536 words x 1-bit
of memory expansion
organization
• On-chip voltage and temper- • low power dissipation of:
ature compensation for Im0.021 mW/bit max.
proved nolae margin
(MBM100490-15)
0_014 mW/bit max.
• Fully compatible with Industry
(MBM100490-25)
standard 100K-serles Eel
families
• DOPOS and lOP-II
• Address access time:
15 ns max, (MBM100490-15)
25 ns max. (MBM100490-25)

Small geometry bipolar integrated
circuits are occasionally susceptible
to damage from static voltages or

electric fields. It is therefore advised
thai normal precautions be taken to
avoid application of any vottage

higher than maximum rated voltages
to this device.

9-73

fff-

•

ffff-

MBM100480

MBM100490 Block Diagram
and Pin Asslgnmants
Q

Vee

As

D

A,

S

II,

Vi

B

""-

A,s

Vi

As

A,.

As

A,.

A7

An

As

A,.

VEE

As

D

A,.

TRUTH TABLE
1
2
3
4
5
6
7
8
9
10
11

INPUT

H

11

W IN

H
L
L
L

X

X

L
L
H

H
L
X

MODE

OUTPUT
L
L
L
OUT

DISABLEO
WRITE "H"
WRITE "C'
READ

= High Voltage Level

L = Low V.ltage
X = Don't Care

A.

22
21
20
19
18
17
16
15
,4
13
12

As
As
A7

As

VEE

A.
A,.
A"
A,.
A,.

Lev"

Functional Dascription
The Fujitsu MBM100490 is a fully
decoded 65,536-b~ read Iwrlte
random access memory organized as 65,536 words by I-bit.
Memory cell selection is achieved
by means of a 16-bit address designed Ao through A'5' Ihe
active low Chip Select (5) input is

provied for memory expansion.
The read and write operations
are controlled by the state of the
active low Write Enable (W)
input. With Wand S held low, the
data at 0 is written into the
addressed location. To read, ViI is

held high, while S is held low.
Data at the addressed location is
then transferred to Q and read
out non-inverted. Open emitter
outputs are provided to allow for
maximum flexibility in output
wired-OR connection.

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

VEE pin potential to ground pin

+0.5 to -7.0

V

Input voltage

VEE
VIN

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

rnA

TA for DIP

-55 to +125

·C

Temperature under bias
Storage temperature

Tc for flat-package

-55 to +125

·C

TSTG

-65 to +150

·C

Note: Permanent device damage may occur it ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU
9-74

MBM100490

Capacitance
Parameter

Symbol

Min

Max

Unit

Input pin capacitance DIP /FPT

C IN

2.0/1.0

5.0/4.0

pF

Output pin capacitance DIP /FPT

COUT

3.0/2.0

6.0/4.0

pF

Guaranteed Operating
Conditions
Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature lor DIP,
Case Temperature lor Flat
Package

Supply voltage

VEE

-4.7

-4.5

-4.2

V

O'C to 85'C

(Referenced to Vccl

DC Characteristics
(Vcc= OV. VEE = -4.SV. Output
Load = son to -2.0V. TA=O'C
to 8S'C for DIP. Tc = O'C to
8S'C for Flat Package. Airflow
';;2.5m/s. unless otherwise
noted)

Parameter

Symbol

Min

Output high voltage
(VIN = VIH max. or VIL min.)

VOH

Output low voltage
(VIN = VIH max. or VIL min.)

Typ

Max

Unit

-1025

-880

mV

VOL

-1810

-1620

mV

Output high voltage
(VIN = VIH min. or VIL max.)

VOHC

-1035

Output low voltage
(VIN = VIH min. or VIL max.)

VOLC

Input high voltage
(guaranteed input voltage
high for all inputs)

VIH

Input low voltage
(guaranteed input vo~age
low for all inputs)

VIL

Input high current
(VIN = VIH max.)

mV
-1610

mV

-1165

-880

mV

-1810

-1475

mV

IIH

110

/LA

O'Cto
85'C

S input high current
(VIN = VIH max.)

IIH

220

/LA

O'C to
85'C

Input low current
(VIN = VIL min.)

IlL

-50

/LA

O'Cto
85'C

S input low current
(VIN = VIL min.)

IlL

0.5

/LA

O'C to
85'C

rnA

O'Cto
85'C

Power supply current
(all inputs and outputs
open)

MBM100490-15
MBM100490-25

9-75

-300
lEE

-200

170

MBM100480

AC Characteristics
(Vee = OV, VEE = -4.5V'±5%;
Output Load = 500 to -2.0V
and 30 pF to GND, TA = O·C to
85·C for DIP, Tc = O·C to 85·C
for Flat Package, Airflow ;;.2.5
mis, unless otherwise noted.)

Read Cycle
Parameter

MBM100490·15
Min
Typ
Max

Symbol

Address access time
Chip select access time
Chip select recovery time

t RC

MBM100480-25
Min
Typ
Max

Unit

15

25

ns

10

15

ns

10

15

ns

Read Cycle Timing Diagram

Write Cycle
Parameter

Symbol

MBM100480-15
Min
Typ
Max

MBM100490·25
Min
Typ
Max

Write pulse width

tww

15

20

Write disable time

tws

10

Unit
ns

20

ns

25

ns

Write recovery time

tWR

Address set up time

tSA

2

3

Chip select set up time

tsc

2

3

ns

Data set up time

tso

2

3

ns

Address hold time

tHA

2

ns

Chip select hold time

tHC

2

ns

Data hold time

tHO

2

ns

FUJITSU

9-76

17

ns

MBM100490

AC Characteristics
(Continued)
(Vee = OV, VEE = -4.5V ±5%,
Output Load = 500 to -2.0V
and 30 pF to GND, TA = O°C to
85°C for DIP, Te = O"C to 85°C
for Flat Package, Airflow ""2.5
mis, unless otherwise noted.)

Write Cycle Timing Diagram

ADDRESS

D

w
....-tsA--OO~
....---tsc~

----------------4~
Q

Rise Time and Fall Time
Parameter

Symbol

Min

Max

Unit

Output rise time

tr -15/-25

1.0/1.0

2.0/3.0

ns

Output fall time

tf -15/-25

1.0/1.0

2.0/3.0

ns

AC Test Conditions
OUTPUT LOAD:
RL = 50H
CL=30pF
(INCLUDING PROBE AND
STRAY CAPACITANCE)

INPUT WAVEFORM

JI

-'.7V _ _ _ _

'.

GND

I,

tA = IF

= 2.5 ns

TVP

NOTE: ALL TIMING MEASUREMENTS REFERENCED 50% INPUT LEVELS.

Vee

VEE

0.0'." I-=- VEe

9-77

MBM100490

Package Dimensions
Dimensions in Inches
(millimeters)

22·Lead Ceramic IMetal Seal) Dualln·Llne Package

.1

(Ca. . No.: DIP.22C·A02)

.~f[ ~ ~~,~ ~ ]~ ;13~-r
fflj
WiFm1fm
~ l!l
1.090(27.69)

.014(0.38)

.2OO(5.G8lMAX
.120(3.05)
.150(3.81)

.090(2.29)
.110(2.79)

I" ~ I
..

I

.042(1.09)
.054(1.37)

1

--II •.

015(0.38)
.023(0.58)

1·0000025.4O)REF

.020(G.51)
.050(1.27)

•

22·Lead Ceramic ICERDIP) Flat Package
(Case No.: FPT·22C-C01)

.030(0.76) MAX

t

f

.352(8.94)
.360(9.14)

.300(7.82) TYP

1
.0075(0.19)
.0105(0.27)

INDEX AREA

!
.1

920(23.37)
960(24.38)

.004(0.10)

I
!
:=2~~~~~~~~~~~~~~~4~t~d:'
~ I.
~I t
.532(13.51)
.540(13.72)

9-78

.190(4.83)
.210(5.33)

.008(0.15)

.032(!81)
.042(1.07)

FUJITSU

Bipolar Memories
•

MB70801·15
4,608-Bit Bipolar
Random Access Memory

D.scrtptlon
The Fujitsu MB70801-1S is a fully decoded 4608-bit ECl read/write
random access memory designed for high-speed scratch pad, control and buffer storage applications. This device is organized as
512 words by 9-bits, and H features on-chip voltage compensation
for improved noise margin.
The MB70801-1S offers extremely small cell and chip size, realized
through the use of Fujitsu's patented DOPOS (Doped Polysilicon),
as well as lOP-II (Isolation by Oxide and Polysilicon), processing.
As a result, very fast access time with high yields and outstanding
device reliability are achieved in volume production.

v

ir-

""'" r-

v~lY~ r~K::uW

[I

I

Operation for the MB70801-1S is specified over a temperature
range of 0" to 7S"C (ambient). It also features metal-sealed 32-pin
dual-in-line packaging, and H is fully compatible with industrystandard 10K-series ECl families.

F••tures
•
•
•

•

512 words x 9-blta
organization
On-chip voltage cornpensatlon for Improved
nolae margin
Fully compatible with
Induatry-etandard
10K-series ECl families
Address acesss time:
15 ns max.
12 ns typo

•

Chip select aceess time:
10 ns max.
B ns typo
• Open emitter output for
ease of memory expansion
• Low power dlBBlpatlon of
0.2S mW/blt typo
• DOPOS and lOP-II
processing

Small geometry bipolar integrated
circuits are occasionally susceptible
to damage from static voltages or
electric fields. It is therefore

acMsed that normaf precautions be
taken to avoid applIcadon of any
voltage higher than maximum rated
voltages to this device.

9-79

... .-

-g'

MB70801·15

MB70801·15 Block Diagram
and Pin Assignm.n'

Os
A.

I

Au

I
I

I
I

I

Vee

I
I

~

!

x-

I
I
MEMORY CELL ARRAY

DECDDER!
DRIVER

I
I
I
I
I
I
I
I
I
I
I

I

I

I

I

I
:
I
I
I
I

I
I
I
I
I
I

I
I
I

I
I

VEE

Vee
Clo

I
I
I
I
I
I
I
I

I
I
I

r

"10-----1
Eo-------t

mUTHTABLE
INPUT
S

W

IN

OUTPUT(Q)

MODE

H
L
L
L

X

X

L
L
H

H
L

L
L
L
OUT

DISABLE
WRITE"H"
WRITE"L"
READ

X

H = HIGH VOLTAGE LEVEL
L = LOW VOLTAGE LEVEL
X = DON'T CARE

Absolu.e Maximum Ra.ings
(See Note)

.;;R;;a;;.I;;n;.::g:..._ _ _ _ _ _ _ _ _ _ _ _S;;.y:;m;,;,;;;b;;o;.I_ _ _ _....;V.;a;;;lu;;;.;..._ _ _ _ _ _ _...;U;;;n;;;I;;'

Vee pin potential to ground pin

Vee

+0.5 to -7.0

Input voltage

V'N

+0.5 to Vee

V
V

Output current (DC, output high)

lOUT

-30

mA

Temperature under bias

TA - 5 5 to + 125

·C

Storage temperature

TSTG

-65 to +150

·C

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU
9-80

MB70801·15

Functional Description
The Fujitsu MB70801-15 is a fully
decoded 4,608 bit read/write random access memory organized
as 512 words by 9 bits. Memory
cell selection is achieved by
means of a 9- bit address designated Ao through As. The active

Guaranteed Operating
Conditions
(Referenced to Veel

Parameter

while S is held low. Data at the
addressed location is then transferred to OUT and read out noninverted. Open emitter outputs
are provided to allow for maximum flexibility in output wired-OR
connection.

low Chip Select (8) input is provied for memory expansion. The
read and write operations are
controlled by the state of the active low Write Enable (W) input.
With Wand 8 held low, the data
at IN is written into the address
location. To read, IN is held high,

Symbol

Supply voltage

Min

Typ

Max

Unit

Te

-5.46

-5.2

-4.94

V

O'Cto 75'C

Capacitance

DC Characteristics
(Vee = OV, VEE = -5.2V, Output
Load = 500 to -2.0V, unless
otherwise noted.)

Parameter

Symbol

Typ

Max

Unit

Input pin capacitance

CIN

4

6

pF

Output pin capacitance

COUT

6

8

pF

Parameter

Min

Symbol Min

Typ

Max

Unit Te

-840
-810
-720

mV

O'C
25'C
75'C

-1665
-1650
-1625

mV

O'C
25'C
75'C

mV

O'C
25'C
75'C

-1645
-1630
-1605

mV

O'C
25'C
75'C

Output high voltage
(VIN = VIH max or VIL min)

VOH

-1000
-960
-900

Output low voltage
(VIN = VIH max or VIL min)

VOL

-1870
-1850
-1830

Output high voltage
(VIN = VIH min or VIL max)

VoHe

-1020
-980
-920

Output low voltage
(VIN = VIH min or VIL max)

VOLe

Input high voltage
(guaranteed input voltage
high for all inputs)

VIH

-1145
-1105
-1045

-840
-810
-720

mV

O'C
25'C
75'C

Input low voltage
(guaranteed input voltage
low for all inputs)

VIL

-1870
-1850
-1830

-1490
-1475
-1450

mV

O'C
25'C
75'C

220

p.A

O'C to 75'C

Input high current (VIN

= VIH max)
= VIL min)

IIH
IlL

-50

S input low current
(VIN = VIL min)

IlL

0.5

Power supply current
(all inputs and outputs open)

lEE

-260

Input low current (VIN

9-81

170

p.A

O'C to 75'C

p.A

O'Cto 75'C

mA

O'C to 75'C

MB70801·1S

FUJITSU
9·82

MB70801·15

AC Characteristics
(Continued)

Write Cycle Timing Diagram

1=-.wses

-.WHes=F

--f+-----

ADDRESS

50%

DATA IN

VI

OUT

Rise Time and Fall Time
Parameter

Symbol

Min

Typ

Max

Unit

Output rise time

t,

1.0

2.0

5.0

ns

Output fall time

It

1.0

2.0

5.0

ns

AC Test Conditions
GND

Vee

OUTPUT LOAD:
RL = 50Il
CL=30pF
(INCLUDING PROBE AND
STRAY CAPACITANCE)

INPUT WAVEFORM

-1.7V _ _ _ _oJ

t.

NOTE: ALL TIMING MEASUREMENTS REFERENCED 50% INPUT LEVELS.

9-83

MB70801.15

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

32·Lead Ceramic (Metal 5_1) Dual In·Llne Package
(Case No.: DIP.32C.A01)

A.050(1.27)AEF

~[Dl

.585(14.86)
.605(15.37)

·~_J,~r:_~:_~~_::_~;_~-I!.:;.090(2.29)
.110(2.79)

~

.046(1.17)
.054(1.37)
1.300(33.02)AEF

9·84

~ I.. .

015(0.38)
.023(0.58)

FUJITSU

Bipolar Memories
•

M870802·20
4,608-Bit Buffer Address Array

Description
The Fujitsu MB70802 is a 4608-bit ECl read/write buffer address
array which can be used for wider tag addresses or deeper tag
memories. The device is organized as a high speed 512 words by
9-bits static RAM array, parity generator/checker, and 9-bit high
speed comparator. It also features on-chip voltage compensation
for improved noise margin.
The MB70802 offers extremely small cell and chip size, realized
through the use of Fujitsu's patented DOPOS (Doped Polysilicon),
as well as lOP-II (Isolation by Oxide and Polysilicon), processing.
As a result, very fast access time, high yields, and outstanding
device reliability are achieved in volume production.
Operation for the MB70802 is specified over a temperature range
of from 0' to 75'C (ambient). It also features standard ceramic 24pin dual-in-line packaging, and it is fully compatible with industrystandard 10K-series ECl families.

Features

• 512 words x 9-bita organization
• On-chip parity
generator/checker
• 9-blt high speed comparator.
• On-Chip voltage compen_
tion for Improved nolae
margin
• Fully compatible with
industry-standard 10Kseries ECl families
• Parity Error addrass
access time:
20 nsmax.
18 na typo

•
•
•
•
•
•

Match address access time:
20 ns max.
18 ns typo
Match data In access time:
15 ns max.
12 ns typo
Chip select access time:
10 ns max.
6 ns typo
Open emitter output for
ease of memory expansion
low po_r dissipation of
0.25 mW/bit typo
DOPOS and lOP-II
processing

Small geometry bipolar integrated
circuits are occasionally susceptible
to damage from static voltages or
electric fietds. It Is therefore
advised that normat precautions be
taken to avoid application of any
voltage higher than maximum rated
Yoltages to this device.

9-85

-

rr-

I'

MB70802-20

MB70802 Block Diagrams
and Pin Assignment

Vi

PE
Vee

I
I

I
I

512 WORDS x
I

;

I

9am; RAM
I ; ;

I

I

I

I

I
I
I
I
I

I
I
I
I
I

I
I
I
I
I

I
I

PE

PC/I

PARITY

GENERATOR

Do--a,

Read Operating Data-Signal Flow
W"H"

l! "L"

ADDRESS DECODER/DRIVER

512 WORDS x 9 BITS RAM

Do

01

I

i

!

I

I

i
\

i

i

I

I

\

i ~ ! Oa ! 04 i 051 Os i Or

PARITY
CHECKER

PE

COMPARE

MA

aD

DATAO-DATA7
INPUT/OUTPUT
CONTRaL

A,
A.

S

MA

:

A.

a,
a,

INPUT/OUTPUT
CONTROL

PC/I

MA
Do

PARITY DATA

PC/I

FUJITSU
9-86

W

MB70802·20

MB70802 Block Diagram
and Pin Assignment
(Continued)

Write Operating Data - Signal Flow
W"I.:'
ADDRESS DECODER/DRIVER

S"I.:'

wlS BUFFER

II
I

I
I
I
I
I
512 WORDS )( 9 BITS RAM

PARITY
CHECKER

I I i I I I

PE "I.:'

~ ~!~!~I~!~l~i~
~
I
I
I
I
I
I

Q.-Or

PCII

TRUTH TABLE
INPUT

OUTPUT

PC/I

S

W

01

MATCH

PE

X

H
L
L
L
L
L

X

X
01
01
01
01
01

L
L
L
L
H
H

L
L
PI

PI
PI
PI
PI
PI

L
H
H
H
H

Pi
PI

Pi

DISABLE
WRITE"D(
EQUAL
UNDEFINED ERROR
NOT EQUAL
PARITY ERROR

(READ)
(READ)
(READ)
(READ)

H = HIGH VOLTAGE LEVEL
L = LOW VOLTAGE LEVEL
0, = DATA IN
pl=HORL
X = DON'T CARE

Absolute Maximum Ratings

(SeeNm~

~R~a~t_ln~g~............................................~S~y~m~b~o_I................_V~a_l_u_e................................~U_n..
lt
VEE pin potBntialto ground pin
VEE
+0,5 to -7,0
V
Input voltage

VIN

+0,5 to VEE

V

Output current (DC, output high)

lOUT

-30

rnA

Temperature under bias

TA

-55 to +125

Storage temperature

TBIg

-

65 to

+ 150

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

9-87

MB70802·20

Functional Description
The Fujitsu MB70802 is a
4,608-bit buffer address array
organized as a high speed 512
words by 9-bits static RAM array,
parity generator/checker, and 9-bit
high speed comparator. Word
selection is achieved by means
of a 9-bit address designated

Ar,-Aa·
The active low chip select (8)
input is provided for memory
array expansion. The read

Guaranteed Operating
Conditions
(Referenced to Vccl

Parameter

held high, while § is held low.
The 8-bit data and parity bit data
are input to all the comparators
which perform a match of the
nine inputs (one word) against
the stored word. If a particular
word is identical to the input
word, such comparators generate
a match signal. Simultaneously,
the 9-bit stored data is checked
by the parity checker.

(Compare/Parity Checker) and
write operations are controlled by
the state of the active low Write
Enable (Wj input. With Vii and 8
held low, the 8-bit data on Q o to
Q 7 and a parity bit data generated by parity generator are written into the addressed location. If
a PC/I input holds low (high)
under the write operation, a parity error flag is high (low) un~
the read operation. To read, W is

Symbol

Supply voltage

Min

Typ

Max

Unit

-5.46

-5.2

-4.94

v

Capacitance
Parameter

Symbol

Typ

Max

Unit

Input pin capacitance

CIN

Min

4

6

pF

Output pin capacitance

COUT

6

8

pF

DC Characteristics
(Vcc = OV, VEE = -5.2V, Output
Load = 500 to -2.0V, unless
otherwise noted.)

Parameter

Symbol Min

Max

Unit TA

-960

-840
-810

mV

-900

-720

O°C
25°C
75°C

-1870

-1665
-1650
-1625

mV

O°C
25°C
75°C

mV

O°C
25°C
75°C

-1645
-1630
-1605

mV

O°C
25°C
75°C

-840
-810
-720

mV

O°C
25°C
75°C

-1000

Output high voltage
(VIN = VIH max or VIL min)

VOH

Output low voltage
(VIN = VIH max or VIL min)

VOL

Output high voltage
(V'N = V,H min or V,L max)

V OHC

Output low voltage
(VIN = VIH min or VIL max)

VOLC

Input high voltage
(guaranteed input voltage
high for all inputs)

V IH

Input low voltage
(guaranteed input voltage
low for all inputs)

V IL

-1850
-1830
-1020

-980
-920

-1145
-1105
-1045
-1870

-1490

-1850
-1830

-1475
-1450

mV

O°C
25°C
75°C

220

JJ.A

O°C to 75°C

JJ.A

O°C to 75°C

JJ.A

O°Cto 75°C

mA

O°C to 75°C

Input low current (VIN

= VIH max)
= VIL min)

IlL

-50

Sand PC/I
Input low current (VIN

=

I'L

0.5

lEE

-260

Input high current (VIN

Typ

V IL min)

Power supply current
(all inputs and outputs open)

FUJITSU
9-88

IIH

170

MB70802·20

AC Characteristics
(Full Guaranteed Operating
Ranges, Output Load = 500 to
-2.0V and 30pF to GND and
Airflow ;;.2.5 mls unless otherwise
noted.)

Read Cycle
Parameter

Symbol

Min

Typ

Max

Unit

Parity error address access time

tAAP

4

18

20

ns

Match address access time

tAAM

4

18

20

ns

Match data in access time

tADM

2

12

15

ns

Chip select access time

tAC

2

6

10

ns

Chip select recovery time

tRC

2

6

10

ns

Read Cycle Timing Diagram

MA and PE

~~ 50%

ADDRESS

DATA IN

\~ 50%

/1\

tAAP

\I
/\50%

PE

~.

_1_~'~0%
tAAM

tADM

MA

9-89

_

MB70802.20

AC Characteristics
(Continued)
(Full Guaranteed Operating
Ranges, Output Load = 500 to
-2.0V and 30pF to GND and
Airflow ;;.2.5 m/s unless otherwise
noted.)

Write Cycle
Parameter

Symbol

Min

Write pulse width

tww

17

Typ

Write disable time

tws

10

Write recovery time

tWR

18

Address set up time

tSA

Max

Unit
ns
ns
ns

1.5

ns

Chip select set up time

tsc

1.5

ns

Data set up time

tso

1.5

ns

Address hold time

tHA

1.5

ns

Chip select hold time

tHC

1.5

ns

Data hold time

tHO

1.5

ns

Write Cycle Timing Diagram

§

~~

I..

tHe

F

50%

ADDRESS

DATA IN

MAANDPE

Rise Time and Fall Time
Parameter

Min

Typ

Max

Unit

Output rise time

Symbol

1.0

2.0

5.0

ns

Output fall time

1.0

2.0

5.0

ns

FUJITSU

gogO

.870802.20

AC Test Conditions
GND

Vee

DUTPUT LOAD:

AL =

son

CL=30pF
(INCLUDING PROBE AND
STRAY CAPACITANCE)

VEE

INPUT WAVEFORM

-1.7V

----...II
I,

10
tA

= tF

= 2.5 ns TVP

NOTE: ALL TIMING MEASUREMENTS REFERENCED 50% INPUT

9-91

~EVELS.

FUJITSU

Bipolar Memories
•

MB7700H Series
Eel Bipolar RAM

Description
The Fujitsu MB7700H series are 4K-bit Eel read/write random
access memories designed for applications of high-speed scratch
pad, control and buffer storage. The device consists of 4-planes of
256 words x 4-bits memory arrays. By means of the metal options,
several kinds of organizations for various usages wHhin a system
are realized (e.g. 256 words x 16-bits, 512 words x 8-bits and
so on).
The MB7700H series offers extremely small cell size realized
through the use of lOP-II (Isolation by Oxide and Polysllicon)
processing. As a result, very fast access times are achieved.

Fe.ture.
• 256 words x 18-blts
organization (basic)
• On-chip voltage compensation 'or Improved
noise margin
• Fully compatlbla with
10K Eel 'amllles
• Address access time
5 ns(max.)
4 n. (typ.)

• Power dissipation
6W(max.)
3.6W(typ.)
• Open emitter output 'or
_
of memory expansion
• 60 Pin FLAT package
• Metal options

9-92

f-

r-

~

~v, $

""

!;)"~ --

~ f'" £'.""

MB7700H

MB7700H Block Diagram
and Pin Assignment

EMITTER
FOLLOWER

iiS(4)

AD(5)
AD(3)

1N(4)

iiS(4)
W(1)

TRUTH TABLE
INPUT
BS

W

D

OUTPUT

MDDE

H
L
L
L

X

X

L
L
H

H
L

L
L
L
0

DISASLE
WRITE "H"
WRITE"'"
READ

X

H = HIGH VOLTAGE LEVEL
L = LOW VOLTAGE LEVEL
X = DON'T CARE

FUJITSU
9-93

Ma7700H

Pin Assignment Table
nolH

7702H

ParI No.
1703H 7704H

7706H

7708H

°0..0

31

°01.0

00..

°0••

Oo.c

00••

Do.cd

0, ...

32

Ou••

°1 ••

°1 ••

°1.0

°1 ••

Dl.cd

Ao.ab Ao

Ao.ab

33

DO••

Oz..

°2..

Oz..

02..

il:!.cd

A, ..b

A,

Al.ab

34

D1.0

OJ..

OJ..

A2

A2.ob

A2

Az

35

N.C.

OJ.•
N.C.

DZ••

~.cd

OJ••
N.C.

OJ.cd
N.C.

Aa

AS.ab

AS

Aa

38

N.C.

N.C.

Da••

A5.cd

N.C.

N.C.

°O.b

°Oob

°Oob

Oo.ab

37

Da.

N.C.

Dl ••

As.cd

N.C.

N.C.

°1.b

°1.b

°1.b

°1.b

D1.ab

aB

D2••

N.C.

DOoe

A7.cd

N.C.

N.C.

°2.b

°2.b

Oz.b

°2.b

il:!.ab

39

D1.cd

Da.•

Dl.cd

D••

N.C.

DOocd
N.C.

D2.a

DOocd

iio

ft.e

lIi.e

llil

Iilio.cd
B 1.cd

Pari No.

Pin No. no'H

1703H

7704H

OS••

Oaa

Oa..

OJ••

°0' ..

°2••

Oz..

Oz••

Oz.o

S

Ao

Ao

Ao

4

A,

A,

A,

5

Az

Az

6

Aa

Aa

7

001.b

°O.b

8

°U.b

8

ilo.b

,

On.

2

7702H

770IH

770IH

Pin No.

10

Dl.b

°ab

OJ.b

OJ.b

OJ.b

Da.ab

40

BSa
BIIo

11

~

A4

~

~.ob

~

~

41

N.C.

12

As

AS

AS

AS.•b

AS

AS

42

W••

W.o.

W.cd

W.cd

W..

W...

IS

Au

A8

As

As.ob

As

As

43

BS..

A7

A7

A7

A7.ab

A7

A7

44

iiS.ob
N.C.

ft.o

14

W••
N.C.

N.C.

N.C.

W••
N.C.

ii!ia.ab

15

D2.b

D1.ab

D1.b

D1.ab

D.b

N.C.

45

DO.o

D3.ab

DO••

Da.ab

N.C.

18

Dab

DO.ab

DO.b

DO.ab

Ha

Ro.ab

48

D1.•

D2.ob

Dl.a

D2.ab

D.o

B 2.ab
N.C.

N.C.

17

N.C.

N.C.

B.b

B.b

II:!

B 1.ab

47

Oz..

°1 ••

°1 ••

°1.0

°1 ..

Oa..ac

18

W.b

W.beI

W•• b

W.ab

W.b

W.beI

4B

Da..

00..

00..

Do..

00.•

Oz.oe

19

W.d

lIi.cd

lIi.d

lIi.d

W.d

N.C.

49

Vcc.a

VCC••

VCC..

VCe..

Vee..

Vee..

20

N.C.

N.C.

N.C.

N.C.

N.C.

BSacd

50

VCCO

Vcco

Vcco

VCCO

Vcco

Vcco

21

BS2

D3.cd

Da.b

Da.cd

N.C.

IiliZ•cd

5'

Vee

VCC

VCC

VCC

Vee

Vee

22

iii,

il:!.cd

D2.b

il:!.cd

D.d

N.C.

52

VEEZ

VEEZ

VEEZ

VEEZ

VEEZ

VEE2

23

N.C.

°u

°u

°1.d

°1.d

OJ.beI

63

VEEI

VEEI

VEEI

VEEI

VEE'

VEEI

24

N.C.

°O.d

°O.d

°O.d

°O.d

°2.beI

54

VEE2

VEE2

VEEZ

VEE2

VEEZ

VEEZ

25

Ou.d

OJ.d

OJ.d

°3.d

°3.d

°O.beI

55

Vee

VCC

VCC

Vee

VCC

Vee

28

°01.d

Oz.d

02.d

°2.d

Oz.d

°1.beI

58

Vcco

VCCO

VCCO

Vcco

Vcco

Vcco

27

Da.d

N.C.

Dl.d

AOocd

N.C.

Ao.cd

57

VCC

Vee

Vee

VCC

VCC

VCC

28

il:!.d

N.C.

DO.d

Al.cd

N.C.

Al.cd

5&

VEEZ

VEEZ

VEEZ

VEEZ

VEE2

VEEZ

28

Dl.d

N.C.

il:!.d

A2.cd

N.C.

N.C.

59

VEEI

VEEI

VEEI

VEEI

VEEI

VEEI

30

DO.d

N.C.

Da.d

Aa.cd

N.C.

N.C.

80

VEEZ

VEEZ

VEEZ

VEEZ

VEEZ

VEEZ

Vee = Veca = OV, VEE1 .= -3.6V, VEE2 = -S.2V
Note: Pin name definition

°T~PIBne

location
Terminal name of plane

0'.2.a

-=--0"

O:! dot (between terminals In a plane)

O,.ab

'-t::........Plane "a", plane "b" dot (between planes)

N.C.

Non connection

9·94

M87700H

Abaolute Maximum Ratings
Rating

Symbol

Value

VEE' pin potential to ground pin (Vcc)

+0.5 to -7.0

V

VEE2 pin potential to ground pin (Vcc)

VEE'
VEE2

Unit

+0.5 to -7.0

V

Input voltage

VIN

+0.5 to VEE

V

Output current (DC, output high)

lOUT

-30

mA

Temperature under bias

TA

-25 to 100

°C

Storage temperature

TSTG

-55 to 125

°C

Nota: Input pins except (85) should not be left open.

Guaranteed Operating
Conditions

DC Characteristics
(MB7701/MBn02/MBn03/
MB7704/MBn05/MBn06
Vee = Vcco = OV, VEE' =
-3.aV, VEE2 = -5.2V Output
Load = 50 Ohm to -2.0V)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

-3.78

-3.60

-3.42

V

Supply voltage

VEE'
VEE2

-5.46

-5.20

Case temperature

TA

0

-4.94

V

55

°C

Symbol

Min

Unit

Ta

Output high voltage
(VIN = VIH max or VIL min)

VOH

-1000
-960
-925

-840
-810
-755

mV

O°C
25°C
55°C

Output low voltage
(VIN = VIH max or VIL min)

VOL

-1870
-1850
-1840

-1630
-1615
-1600

mV

O°C
25°C
55°C

Output high voltage
(VIN = VIH min or VIL max)

VOHC

-1020
-980
-945

mV

O°C
25°C
55°C

Output low vo~age
(VIN = VIH min or VIL max)

VOLC

-1610
-1595
-1580

mV

O°C
25°C
55°C

Input high voltage

VIH

-1145
-1105
-1070

-840
-810
-755

mV

O°C
25°C
55°C

Input low voltage

VIL

-1870
-1850
-1640

-1490
-1475
-1460

mV

O°C
25°C
55°C

Parameter

Input high
current
(VIN = VIH max)

Input low
current
(VIN = VIL min)

Typ

Max

Address

IIH(A)

220

/LA

Data in

IIH(D)

220

/LA

Write enable

IIH(W)

220

/LA
/LA

Block select

IIH(BS)

220

Address

IIL(A)

170

/LA

Data in

IIL(D)

170

/LA

Write enable

IIL(W)

170

/LA

Block select

0° to 55°C

11L(88)

0.5

Power supply current

IEEl

-480

mA

0° to 55°C

Power supply current

IEE2

-800

mA

0° to 55°C

FUJITSU
9-95

170

0° to 55°C

/LA

MB7700H

AC Characteristics
Parameter

Symbol

Min

Max

Unit

Block select access time

tAB

0.5

Typ

3.0

ns

Block select recovery time

tRB

0.5

3.0

ns

Address access time

tM

1.5

5.0

ns

Write pulse width

tww

3.5

ns

Address set up time

tSA

1.5

ns

Block select set up time

tSB

1.5

ns

Data set up time

tso

0.5

ns

Address hold time

tHA

1.5

ns

Block select hold time

tHB

1.5

ns

Data hold time

tHO

2.5

Write disable time

tws

4.0

ns

ns

Write recovery time

tWR

4.0

ns

Input capacitance

C 1N

6.5

pF

Output capacHance

COUT

8.0

pF

9-96

MB7700H

Internal Plane Connection
Diagrams

MBn01H
AO(8)
0(4)
H(4)
W(1)

A

0(4)

B

MB7702H
0(1)
0(1)

AO(8)
Q(4)
H(1)
W(1)

A

0(4)

B

0(4)

C

0(4)

0

0(4)

0(1)
0(1)

W(1)

W(1)
0(1)

0(4)

C

0(1)

0(4)
H(1)

W(1)
0(1)
0(4)

0

0(1)

W(1)

MBno3H
AO(8)
0(4)

A

~1)

MBnG4H

I--- 0(4)

W(1)

0(4)
H(1)

~1)

1

B

t------

0(4)

H(1)

C

t------

0(4)

AO(8)
0(4)

0

I--- 0(4)

BS(1)

AO(6)
AO(2)
0(4)
~4)
W(1)

L

1
L

~m

MB770SH

0(4)

B

0(4)

C

0(4)

0

0(4)

MB7706H

AO(8)
0(1)
!!!I(4)
W(1)

A

r-- 0(4)

0(1)

B

t---

W(1)

0(4)
W(1)

0(1)

C

r-- 0(4)

0

t---

W(1)

0(1)

A

W(1)

0(4)
BS(1)
W(1)
0(4)
BS(1)

AO(8)
0(4)

'--

0(4)

ill

AO(2)
...!!(4)
BS(4)

r- 0(4)

B

r- 0(4)

c

fill

~

W(1)

A

0

t-

NOTES: "1 VALUES IN () SHOW THE NUMBER OF EXTERNAL PINS HAVING THE SAME PIN NAME.
"2 "A", "B", "C" AND "0" IN THE BOXES SHOW FOUR MEMORY PLANES IN A CHIP.

FUJITSU

9-97

MB7700H

*

Timing Diagrams
Input Conditions

-O.9·----t--

---------

-1.7.

tR

--------~-tA=tF= t.on.TYP.

Read Cycle Timing Diagram

Write Cycle Timing Diagram

50%

ADDRESS

D

o

9-98

80%

!"'"

MB7700H

Package Dimensions
SEE NOTE 3

o

1.20(30.5)

sa :~~~;::~~:

.118(3.0) TVP

FUJITSU

9-99

MB7700H

.185(18.9) DlA
.181(17.3) DlA

r·224(5.7) CIA-1

t

I

~c:====~==~:====~
.787 (20.0) MAX

T ==:=;:==:::=:==
c::::

1

.087(1.7)

.038(0.96)

+

~.I- .il+_03:.~~(~I.52)~j~r~lj
)L
======::::E:!I=='l~L====:::::JI~
--1
f----ABO(I2.2)CIA----.~1I

IlfoI
..

I..

AI8 (12.35) DlA

.780 (19.80)

.905 (20A5)

NOTES: ·1 DIMENSIONS IN INCHES AND (MILUMETEAS)
·2 CDDUNG FIN CENTER IS WIllIIN .02(0.5)
·3 BOTTOM PATTERN OF CERAMIC BASE IS CONNECTED TO Vee

9·100

.1

1--.024(0.6) MIN

~

MBM93419

FUJITSU

MICROELECTRONICS. INC.

TTL 576·BIT BIPOLAR
RANDOM ACCESS MEMORY
DESCRIPTION
The Fujitsu MBM93419 is a high
speed TTL read/write randomaccess memory, organized as 64
words by 9 bits, with opencollector outputs.
MBM93419 is packaged in a
28-pin dual-in-line package, and is
plug-in replaceable with F93419.lt

is ideally suited for scratchpad,
small buffer and other applications where the number of required words is small and the
number of required bits per word
is relatively large. The ninth bit
can provide parity for 8-bit word
systems_

FEATURES
• Chip Select Access Time:
40ns Max_
• Power Dissipation:
1_3mW/bit Typ_
• Compatible with F93419

• Organization:
64 words x 9-bits
• +5V Single Power Supply
• TTL Inputs and Outputs
• Open Collector Outputs
• Address Access Time:
45 ns Max_

CERAMIC PACKAGE
DIP·28C·A01

MBM93419 BLOCK: DIAGRAM

PIN ASSIGNMENT

AS
A.
A,

ADDRESS
DECODER

Ao

A3
A4
AS

32 x 18

WORD
DRIVER

CELL
ARRAY

A,

DO

AD

01
02
03
0,4

SENSE
AMP
WRITE
DRIVER

°0_8

Os
Os

S
QD-8

Vi

x9

Vee
A2
A1
AO

Qo
Ql
Q2
{i3
04

Os

07

Qs

Os

'°7

Vii,

GNO

·Qs
S

TRUTH TABLE
INPUT

S VI

D

X
L
L
H

X
H
L
X

H
L
L
L

OUTPUT

MODE

H
H
H

DISABLED
WRITE"H"
WRITE"L"
READ

DOUT

H = HIGH VOLTAGE LEVEL
LOW VOLTAGE LEVEL
L
X = DON'T CARE
"DATA OUTPUT IS THE
COMPLEMENT OF DATA INPUT

=

9-101

Small geometry bipolar Integrated circuits
are occasionally susceptible to damage from
stalic voltages or electric field. It is therefore
advised that normal precautions be taken to
avoid application of any voltage higher than
the maximum rated voltages to this device.

MBN93419

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

Power Supply Voltage
Input Voltage (DC)
Input Current (DC)
Output Voltage (YOUT = "H")
Output Current (DC, VOUT = "L")
Storage Temperature

Vee
VIN
liN
VOUT
lOUT
TSTG

-0.5 to +7.0
-0.5 to +5.5
-12.0 to +5.0
-0.5 to +5.5
+20.0
-65 to +150

V
V
mA
V
mA
·C

Note:

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet.

GUARANTEED OPERATING RANGES
Parameter

Symbol

Min

Typ

Max

Unit

Ambient Temperature

Power Supply Voltage

Vee

4.75

5.0

5.25

Input High Voltage

VIH
VIL

2.1

-

O·C to +75°C

0.8

V
V
V

Input Low Voltage

-

-

CAPACITANCE
(TA = 25·C, Vee =5.0V, VIN = 2.0V, f = 1 MHz)
Parameter
Input Pin Capacitance

Symbol

Min.

Typ.

Max.

Unit

CIN

-

-

COUT

-

5.0
8.0

pF
pF

Output Pin Capacitance

-

DC CHARACTERISTICS
(Vee;" 5V ±5%, TA = O·C to 75·C, Air Flow
Parameter

2.5m/sec, After Warm·up

Symbol

Output Low Voltage

VOL

Input High Voltage
Input Low Voltage

VIH
VIL

Input Low Current
Input High Current

ilL
IIH1

Input High Current
Input Clamp Diode Voltage

IIH2
leEx
Veo

Power Supply Current

Icc

Output Leakage Current

~

Vee

~

2 min.)
Min

Typ

-

-

0.4
1.6

-

-

Test Condition
IOL = 12mA

= Min,

Max
0.5

Unit
V

-

V

-

V
p.A

Vee - Max, VIN - 0.4V

-

1.5
-250

Vee = Max, VIN
Vee = Max, VIN

-

1.0

40

p.A

1.0

mA

-

1.0
-1.0

100
-1.5

p.A

-

160

200

= 4.5V
= 5.25V
Vee = Max, VOUT = 4.5V
Vee = Max, VOUT = 4.5V
Vee = Max, TA = 25°C
All Input GND

9·102

-

-400

V
mA

MBM93419

AC CHARACTERISTICS
(Vee

= 5V

± 5%, TA

=O°C to 75'o C, Air Flow;;::

2.5 m/sec, After Warm·up ;;:: 2 min.)

Vee

vee

RL1

Q

o-a
RL2

Input Pulse Vollage:3.5Vp-p
Input Pulse Rise and Fall Time: 10ns
Output Load:
RL 1 ~ 450!l
RL2 ~ 750!l
CL ~ 30pF (Including Jig)
Timing Measurement Levels: Input ~ 1.5V
Output ~ 1.5V

eL

READCYCLE
Parameter

Symbol

Min

Address Access Time
Chip Select Access Time

tAC

-

Chip Select Recovery Time

tRC

-

tAA

READ CYCLE

9-103

Typ

26
18
18

Max
45

Unit
ns

40
40

ns
ns

MBM93419

WRITE CYCLE
Symbol

Min

Typ

35

Write Recovery Time
Write Delayed Time

tww
twR
tws

Address Setup Time

tSA

Chip Select Setup Time
Data Setup Time

tsc
tso

Address Hold Time
Chip Select Hold Time

tHA
tHC

Data Hold Time

tHO

5
5
5
5
5
5

7
20
20
0
0
0
0
0
0

Parameter
Write Pulse Width

-

Max

Unit

-

ns

45
40
-

ns

ns

-

ns
ns

-

ns
ns

ns
ns

WRITE CYCLE

i

-i

-'f\

I

~~
11\

\1
J\

D

~C

~i
If\.

If\.
~

,I..

- --

J

\

---.

tso

- t S A - - ..
_tsc

tww

tHO ~
.-tHA--tHC-

,'/.

- - J

tws

9-104

,jr~

tWR

~

Advanced Information
Bipolar Memory
• MBM10422A-5
1K Bit Eel RAM

Target Specifications

•
•
•
•

•

organization:
25 x 4
Access Time:
5ns (Max)

vee

VCCA

Power Dissipation:
1040mW (200mA)
Package:
24 Pin DIP/FPT
24 Pad LCC
Availability:
Samples - 1st Qtr. 1986
Production - 2nd Qtr. 1986

°
_0

2

23

BSO

3

22

BS 3

°1

4

Top

21

°2

B~

5

View

20

BS 2

DO

6

19

D3

D1

7
8
9
10

18

D2

17
16

A4

15

A2

11
12

14
13

w

As
As
Ar
VEE

°3

A3

A1

:::J

AO

... V CO grounded

Note:
DIP and Flat Package styles
conform to the same pin
assignment.

9·105

Advanced Information
Bipolar Memory
• MBM100422A-5
1K Bit Eel RAM

Target Specifications

•

•
•
•
•

Organization:
256 x 4
Access Time:
5ns (Max)

°3

Power Dissipation:
900mW (200mA)
Package:
24 Pin DIP/FPT
24 Pad LCC

°2

BS3

2

23

A4

°2

3

A3

B~

4

Top

22
21

°3

5

View

20

A1

VCC·

6

19

AO

18
17
16

VEE

°1

7
8
9
10

BS2

11

°0

12

14
13

vCCA

Availability:
Samples - 1st Qtr. 1986
Production - 2nd Qtr. 1986

°0
BS1

* VCO

A2

Ar
As
As

15

w

:J

°1

grounded

Note:
DIP and Flat Package styles
conform to the same pin
assignment.

9-106

Advanced Information
Bipolar Memory
• MBM10474A-5
4K Bit Eel RAM

Target Specifications

•
•
•
•
•

Or~anization:

10 4

x4

Access Time:
5ns (Max)

VCCA
Q2

Power Dissipation:
1560mW (300mA)
Package:
24 Pin DIP/FPT
24 Pad LCC
Availability:
Samples - 1st Qtr. 1986
Production - 3rd Qtr. 1986

2

23

Q1

22

Qo

Q3

3

AO

4

Top

21

D3

A1

5

View

20

D2

A2

6

19

D1

A3

7
8
9
10
11
12

18
17
16
15

DO

A4

%
NC

~

9-107

VCC

14
13

s

w
Ag
AS

:J "r

Advanced Information
Bipolar Memory
• MBM100474A-5
4K Bit Eel RAM

Target Specifications

•
•
•

•
•

Organization:
1024 x 4
Access Time:
5ns (Max)

D,
D2

Power Dissipation:
1350mW (300mA)
Package:
24 Pin DIP/FPT
24 Pad LCC
Availability:
Samples - 2nd Qtr. 1986
Production - 3rd Qtr. 1986

23

s

22

w

21

A9

20

AS

D:3

3

°0

4

0,

5

vee

6

19

A7

vee

7
8
9
10
11
12

18
17
16
15

vEE

14
13

A4

°2
°3
AO
A,
A2

9·108

DO

2
Top
View

AS
Ne
AS
A3

Advanced Information
Bipolar Memory
• MBM10480A-10
16K Bit Eel RAM

Target SpeCifications

•
•
•
•
•

Organization:
16.384 x 1
Access Time:
10ns (Max)

vc~

Q

A
D

Power Dissipation:
1150 mW (220 mAl

Al
A
2

Package:
20 Pin DIP/FPT
20 Pad LCC
Availability:
Samples - 3rd Qtr. 1986
Production - 4th Qtr. 1986

2
3
4

Top
View

19

0

18

S

17

W
A 13

~

5

16

A4

6

15

A12

"s
As

7

14
13
12
11

All

"r

8
9
10

AID
Ag
AS

* Vee grounded

Nole:
DIP and Flat Package styles
conform to the same pin
assignment.

9-109

Advanced Information
Bipolar Memory
•

MBM100480A-10
16K Bit Eel RAM

Target Specifications

•
•
•
•
•

Organization:
16,384 x 1
Access Time:
10ns (Max)

vee

Q

A
0
Al

Power Dissipation:
1000mW (220mA)
Package:
20 Pin DIP/FPT
20 Pad LCC
Availability:
Samples - 3rd Qtr. 1986
Production - 4th Qtr. 1986

2

19

0

3

18

S

A
2

4

17

iN

A3

5

16

A 13

A4

6

15

A12

'\

7

All

As
Ar

8
9
10

14
13
12
11

A 10
Ag
AS

* VCO grounded

Note:
DIP and Flat Package styles
conform to the same pin
assignment.

9·110

Advanced Information
Bipolar Memory
•

MBM1 0484A-1 0, MBM1 00484A-1 0
16K Bit Eel RAM

Target SpeCifications

•

•
•
•

•

Organization:
4096 x 4
Access Time:
10ns (Max)

vcc
Q2

Power Dissipation:
< 1500mW

Q

A

Package:
28 Pin DIP/FPT
28 Pad LCC

3

0

A

Q1

3
4

03

6

2

A3

7

A4

8
9
10

AS
AS

vcc
Q

o

O2

5

Al

Availability:
Samples - 4th Qtr. 1986
Production - 1st Qtr. 1987

28
2

Top

°

1

View

DO

21

C

~

"'2
NC

AS

11
12

All

NC

13

A 10

v

14

Ag

A7

EE

Note:
DIP and Flat Package styles
conform to the same pin
assignment.

9-111

Advanced Information
Bipolar Memory
•

MBM10494-15, MBM100494-15
64K Bit Eel RAM

Target Specifications

•
•
•
•
•

Organization:
16,384 x 4
Access Time:
15ns (Max)

28

vee

Power Dissipation:
< 1500mW

2

27

Q1

Q

3

26

Q

3

A

Package:
28 Pin DIP/FPT
28 Pad LCC

A1

5

A

6

A3

7

A4

8

o

03

4

0

2

Availability:
Samples - 1st Qtr. 1987
Production - 3rd Qtr. 1987

vee

Q2

O2

Top

°1

View

DO

21

S

AS

9

WE1

A6

10

w~

Ar
As

11

A 13

12

A12

Ag

13

A11

v

14

A 10

EE

Note:
DIP and Flat Package styles
conform to the same pin
assignment.

9-112

Cross Reference ......................... 10-2
Temperature Ranges ..................... 10-3
Fujitsu PROM Technology ................. 10-4
Programming Information ................. 10-5
Fujitsu Approved PROM Programmers ...... 10-11
DEApTM Technique ...................... 10-12
DEApTM Cell Structure .................... 10-13
MB7111 E/H, MB7112E/H ................ 10-14
MB7111 L17112L ......................... 10-23
MB7113E/H, MB7114E/H ................ 10-24
MB7113L17114L ......................... 10-33
MB7115E/H, MB7116E/H ................ 10-34
MB7117E/H, MB7118E/H ................ 10-43
MB7121 E/H, MB7122E/H/Y .............. 10-52
MB7123E/H, MB7124E/H ................ 10-61
MB7127E/H, MB7128E/HIY .............. 10-70
MB7128E-W ............................ 10-80
MB7131 E/H, MB7132E/HIY, MB7131 E-SKI
H-SK, MB7132E-SK/H-SKIY-SK ......... 10-88
MB7133E/H, MB7134E/H/Y .............. 10-99
MB7137E/H, MB7138E/HIY, MB7137E-SKI
H-SK, MB7138E-SK/H-SKIY-SK ......... 10-109
MB7138E-W ............................ 10-120
MB7141E/H, MB7142E/H ................ 10-129
MB7142E-W ............................ 10-139
MB7143E/H, MB7144E/HIY .............. 10-147
MB7144Y ............................... 10-156
MB7144E-W ............................ 10-157
MB7151E/H, MB7152E/HIY .............. 10-166
MB7212RA17212RS ............ , ........ 10-172
MB7226RA172226RS .................... 10-173
MB7232RA17232RS ..................... 10-186
MB7238RA17238RS ..................... 10-199
MB7242RS ............................. 10-200

...

'6'
t

9:

~~~~~/,~ ~/'//?PftA
r:-~
~

~

MB7111
MB7112
MB7113
MB7114

o

""

MB7115
MB7116
MB7117
MB7118
MB7121
MB7122
MB7123
MB7124
MB7127
MB7128
MB7l31
MB7132
MB7133
MB7134
MB7137
MB7138
MB7141
MB7142
MB7143
MB7144
MB7151
MB7152
MB7226RA
MB7232RA

/

0"

cJ!..J~
0<£

OC
3S
OC
35

q'l>Ci

~

ffl'<:?

ti;t'"

+#

...'

DM54i74S188
DM54/74S288

TBP18SA30
TBP18S030
TBP24SA10
TBP24S10

DM54/74S387
DM54/745287
DM54/745570
DM54/74S571
DM54/74S471
DM54/745572
DM54/745573
DM54i74S473
DM54i74S472
DM77/87S184
DM77/87S185
DM77/87S180
DM77/87S281

N/S625191

AM27S185
AM27S180
AM27S181
AM27540
AM27541
AM275190
AM275191

63S1681

DM77/87S195
DM77/87S190
DM77/87S191

N/S62S321

AM27S43

6353281

DM77/87S321

82HS641

AM27S49
AM27S40
AM27S41
AM27S25
AM27S35

N/S62H5195

N/S625195

53/6351641

TBP28LA22
TBP28L22
TBP24SA41
TBP24S41
TBP28SA42
TBP28S42
TBP24SA81
TBP24S81
TBP28SA86
TBP28S86

~~..

DM77/87S195
DM87SR25
DM87SR181

~",

HM7602
HM7603
HM7610
HM7611
HM7620
HM7621

HM7642
HM7643

HM76161

93452
93453

HN25044
HN25045

~

n

a

r=cr
ig

MCM7643

ac:

29623

93450
93451

HN25088
HN25089

937510
932511

HN25168
HN25169

a:

MCM7685

29651

MCM7681

29631

3628

29681

3636

29671

3632

MCM76165
MCM76161

HM76321

HM76165

,#

MCM7621

HM7685
HM7681

;n
HI·pin
18·pin
18·pin

18·oin
2O·pin

201'ln
20·pin
2O.jlin
18·pin
18·pin
181'in
la-pin

16·Pin
241'ln
24-pln
24·pin

~t~~

2()..pin

20-pin
2O-pin
20·pin
20-p;n
24-pin
24-pin
24-pin

~~~

24-pin
24-pin

~t~~

24-pin
24-pln
24-pln
24-pin
2O-pin
2O-pin
201'in
201'ln
201>ln
24·pin
24-pin
24·pin

24-pin

_d.d T.mp...ture"".... (-55·C to + 125'C)

(max)

...v_.....,

Current
(Icc)

p.......

55n8
55n8
55n8
65n8
70n8

+5V
+5V
+5V
+5V
+5V

155mA
175mA
180mA
185mA
190mA

16· in
241>in
24· in
24-p;n
24·pin

Ace•••

Device

MB7128E·W
MB7132E·W
MB7138E·W
MB7142E·W
MB7144E·W

CIrgIon_
2Kx4
lKx8
2Kx8
4Kx8
8Kx8

Outpul

TS
T8
T8
T8
T8

Powe,

nm.

Powe,

IuppIr

Fujitsu also offers a family of DEAP PROMs available in extended temperature range (- 55°e to
+ 125·C). These PROMs are of the same generic family as the commercial temperature range product
and utilize lhe same progremming methods and more elaborate testing procedures. This product Is
available processed to Mil. 8td. 883B or 883C.

10-3

Fujitsu PROM Technology
The
Fujitsu
MB7100
and
MB7200 series Schottky PROMs
are fabricated using Schottky
TIL, passive isolation technology
known as Isolation by Oxide and
Poly-silicon (lOP). The isolation
is achieved by a thin-epitaxial
and Shallow V-Grooving (SVG) ,
Diffused Eutectic Aluminum
Process (DEAPTM) technology
with fine emitter. It uses a pulse
programming method which
achieves high-speed operation,
high-speed programming, high
programmability and high reliability.
The memory cell is originally
structured with an open-base
NPN transistor and then programmed by shorting the baseemitter junction, i.e. shorted junction type cell which is achieved by
eutectically melting aluminum
and silicon adjacent to the P-N
junction of the cell diode with relatively low temperatures.
Fast programming time of typically 150 !-'s/bit is achieved with a
fine emitter cell which requires
less programming energy. The
result is negligible thermal stress.
This high reliability feature eliminates aluminum migration in the
programmed cell. Further, Fujitsu's advanced technology allows
very high programmability.

Programmed Cell (Cro•• Section)

o·

~------~,--,r----

/

-----.

Cover Gis••

Substrate

Programmed by DiffUSed Eutectic
Aluminum Process

•

Internal Programming Circuit

Special Factory Testing
Extra rows and extra columns of
test cells, plus additional circuitry
built into the PROM chip, allow
improved factory testing of DC,
AC and programming characteristics. These test cells and test
circuitry provide enhanced correlation between programmed and
unprogrammed circuits in order to
guarantee high programmability
and reliability.

OUTPUT

A _____.....
y

I

~----_4

Ay---,~

Ax

lx~~~~~~~~~~

CE A-_.J"

40

I

II:
II:

<>

~

30

§

20

5

~

/

10

o

o

V

/
200

2.0

Y,N. INPUT VOLTAGE (V)

~ I,)

.L

~~~
V
~

0~ee = 4.5V-

V
-60
600

VOL. OUTPUT LOW VOLTAGE (mV)

FUJITSU

10-19

-

MB7112

MB~1112

400

=

" " Yee
S.OY
Vee = 5.5V-

o
VQH. OUTPUT HIGH VOlTAGE (V)

MB7111E/H
MB7112E/H

Typical Characterl.tlc.
CUrve.
(Continued)

tM Acce•• Tim.
v•. Am..I.nt Temper.tur.

tM Acce•• Time
v •• Am"lent Temperature

70

70

80

80

Vee = 4.5V

Vee = S.ov
Vee = s.sv

~

Vee = 4.SV
Vee = s.ov
Vee = S.SV

.....

P
~~
10

-

10
MB7111

o

-60

60

MB7112

o

100

-60

TA. AMBIENT TEMPERATURE ('C)

v •• Ambient T.mp.rature

70

70

80

80

..
.....
Ij
I

60

1=

40

!15

30

j

20
10

o

:Ii

1=

~

-60

v Vee == 5.0V
4.5V
~~ee

100

t DIS DI....le Tim.

v •. Am..lent Temperature

II

60

TA. AMBIENT TEMPERATURE ('C)

t DiS DI....I. Time

..!
.....

~
); ~

1

Vveel = 5.5

60
40

~~ee = 4.SV
r-- t%:'ee
= S.ov
/, '/ Vee = S.SV
20

30

:::::e

14::.

~
10
MBr11

60

100

TA. AMBIENT TEMPERATURE ('C)

10·20

MB7112

o

-60

60

100

TA. AMBIENT TEMPERATURE ('C)

MB7111E/H
MB7112E/H

Typical Characteristics
Curves
(Continued)

tEN Enable Time
vs. Ambient Temperature

tEN Enable Time
vs. Ambient Temperature

70

70
MB7111

...
.:.

...,...
:IE
~

..
z

.

!

50

:IE

40

~

.,.....w

30

z
w

w

~

MB7112

60

60

20

t--vcc = 4.SV

10

lL

vcc=s.SJS

-'

j

50
40

20

10

o

-50

50

Vee

30

~

= 4.5V
= S.OV
= S.SV

~

o

-50

100

50

Delay Time Increase
vs. C L Load Capacitance

70

70

MB7111

MB7112

60

.~
.
.

.,.
w
0:
U

60

!
.,..

50

I:l0:

40

U

!!;
:IE

50
40

!!;

30

t--

w

ADD. 10 1M DELAY

~V

~

>~

100

TA. AMBIENT TEMPERATURE (OC)

TA. AMBIENT TEMPERATURE (0C)

Delay Time Increase
vs. C L Load Capacitance

Vee
Vee

20

0

.......

10

o ~

o

~ r:-100

V

:IE

30 t-- ADD. to tM DELAY

5w

20

~

k": I--

0

V

10

ADD. to tAA DELAY
300

200

Ct.. LOAD CAPACITANCE (pF)

FUJITSU

10-21

o

o

"'~r--.I-""

~ ~ I"""' ADD.';;; 1EN DELAY
100

200

CL. LOAD CAPACITANCE (pF)

300

MB7iiiE/H
MB7ii2E/H

Package Dimensions
Dimensions in inches
(millimeters)

ie-Lead Ceramic ICEADIP) Dualln·Llne Package
ICase No.: DIP.i6C.C02)

.090(2.29)
.110(2.79)

~--~--------------~~
.013(0.33)
.023(0.58)

ie-Lead Plastic Dualln·Line Package
ICase No.: DIP.i6P.M02)

f
INDEX

.234(5.94)
.254(6.45)

~::::::r=r=::;:=r==;:::::;==;=;==;=;==;:::;=:?1~
.756(19.20)
.760(19.81)

10·22

.290(7.37)
.310(7.87)

Advanced Information
Availability Q2 '86

FUJITSU

Bipolar PROM
•

MB7111 L/7112L
Low Power 256-Bit
Schottky TTL PROM

Features

• Organization:
32 x 8-bits
• Process:
Schottky TTL
• Program:
Diffused Eutectic Aluminum
Process (DEAP)
• Output:
Open Collector (MB7111)
Thre.State (MB7112)
• Power Supply:
+5V ±S%
• Power Dissipation:
200 mW max.
• Address Access Time:
55 ns max.
• Package:
16-pln DIP

Vee

D1

(PVcc)
15

10-23

~PVE)

FUJITSU

Bipolar Memories
•

MB7113E/H, MB7114E/H
Programmable Schottky
1,024-Bit Read Only Memory

Description
The Fujitsu MB7113 and MB7114 are high speed Schottky TTL
electrically· field programmable read only memories organized as
256 words by 4-bits. With uncommitted collector outputs provided
on the MB7113 and three-state outputs on the MB7114, memory
expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable DEAP
(Diffused Eutectic Aluminum Process) according to simple programming procedures.
The sophisticated passive isolation termed SVG (Shallow VGroove) wijh thin epitaxial layer and Schottky TTL process permits
minimal chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuijs in
order to perform AC, DC and programming test prior to shipment.
This results in extremely high programmability.

Fe.tures
• Single +5V supply voltage
• 256 words x 4-bits organization, fully decoded
• Proven high programmability and reliability
• Programming by DEAP (Diffused Eutectic Aluminum
Process)
• Simplified low power
programming
• Low current PNP Inputs
• AC characteristics guaranteed over full operating volt·
age and temperature range
via unique testing
techniques

•
•
•
•
•

•
•

Fast access time, 20 ns typo
H: 30 ns max.
E: 40 ns max.
TTL compatible inputs and
outputs
Open collector outputs
(MB7113)
3-state outputs (MB7114)
Two chip enables lead for
simplified memory
expansion
Standard 16-pln DIP
package
JEDEC approved pin out

This device contains circuitry to
protect the inputs against damage
due to high static voltages or elec-

tric fields. However, it is advised
that normal precautions be taken to
avoid application of any vohage
higher than maximum rated voltages to this high impedance circuit.

10-24

MB7113E1H
MB7114E/H

MB7113/7114 Block Dlegrem
end Pin A.slgnments

1024 (32

x 32) BIT

MEMORY CELLS

A,

Vee
(PV cc)

As

A7

Ao

Aa
E(Pve)

Ao
Aa
A,

Absolute Mexlmum Ratings
(See Note)

0,
0,

A,

0,

GND

0,

Retlng

.,1mbol

Velue

Unit

Power supply voltage

Vee

-0.5 to +7.0

V

Power supply voltage
(during programming)

Vee

-0.5 to +7.5

V

Input voltage

VIN

-1.5 to +5.5

V

Input voltage (during programming)

VIPRG

22.5

V

Output voltage (during programming)

VOPRG

-0.5 to +22.5

V

Input current

liN

-20

Input current (during programming)

IIPRG

+270

mA
mA
mA
mA

Output current

lOUT

+100

Output current (during programming)

IOPRG

+150

Storage temperature

Ceramic

-65 to +150
TSTG

Plastic

Output voltage

VOUT

-40 to +125
-0.5 to Vec

·c
V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed In the operational sections of this data sheet.

FUJITSU

10-25

MB7113E/H
MB7114E/H

Guaranteed Operating
Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.75

5.0

5.25

V

Input low voltage

Vil

0

0.8

V

VIH

2.0

5.5

V

TA

0

75

·C

Input high

vo~age

Ambient temperature

Capacitance
(! = 1 MHz, Vee = +5V,
VIN = +2V, TA = 25·C)

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Max

Unit

Input capacitance

CI

10

pF

Output capacitance

Co

12

pF

Typ

Min

Parameter

Symbol

Input leakage current
(VIH = 5.5V)

Min

Typ

Max

Unit

IR

40

p.A

Input load current
(Vll = 0.45V)

IF

-250

p.A

Output low voltage
(Iol = 10 rnA)

VOL

0.45

V

Output low voltage
(lOl = 16 rnA)

VOL

0.50

V

Output leakage current
(V 0 = 2.4V, chip disabled)

MB7113

10lK

40

p.A

Output leakage current
(Vo = 2.4V, chip disabled)

MB7114

10lH

40

p.A

Output leakage current
(Vo = 0.5V, chip disabled)

MB7114

lOll

-40

p.A

Input clamp voltage
(liN = -18 rnA)

Vie

-1.2

V

Power supply current
(VIN = OPEN or GND)

Icc

100

rnA

60"2

Output high voltage
(10 = -2.4 rnA)

MB7114

VOH "1

2.4

Output short circuit current
(Vo = GND)

MB7114

los"1

-15

V
-60

rnA

Notes: *1 Denotes guaranteed characteristics of the output high-level (ON) state when the chip is enabled (VE "" O.4V) and the programmed
bit is addressed. These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.
"2 This value denotes conditions at TA = 25°C and Vee:;;; +5.0V.

AC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

MB7113/MB7114E
Typ
Max

MB7113/7114H
Typ
Max

Unit

Access time
(via address input)

tAA

20

40

20

30

ns

Output disable time

t DIS

15

25

15

25

ns

Output enable time

tEN

15

25

15

25

ns

10·26

MB7tt3E1H
MB7114E/H

Oparetl_ Tlml... Diagram
ADDRESS

\/I.SV

INPUT

\/ISV

/1\ .

/\

CHIP
ENABLE
INPUT

-+

1M

-

'AA

-f,:,------,r,:-VOH
OUTPUT

1.~

1~V

----------~
CHIP
ENABLE
INPUT

E _ _ _ _ _ _ _ _ _J

~---------~

I.SV
' - - - - - - - - - - - - - V,L
'EN

OUTPUT
'------------VOL

NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
IMPEDANCE STATE WHEN SOME OF THE CHIP ENABLES ARE TAKEN HIGH
(DISABLED). OUTPUT ENABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO
BECOME ACTIVE WHEN THE CHIP ENABLES ARE TAKEN LOW (ENABLED). THE
HIGH IMPEDANCE STATE IS DEFINED AS A POINT ON THE OUTPUT WAVEFORM
EQUAL TO A b. V OF O.SV FROM THE ACTIVE OUTPUT LEVEL.

AC T••t C-dltlons
-~t--Vcc

Input CondltlonB
Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to 3V
Rise and Fall Time ..........................• 5 ns from 1V to 2V
Frequency .............................................. 1 MHz
TRUTH TABLE
MB7113/MB7114

I
l
I

tAA

Rl

R2

CL

300n

aoon

30pF

tDIS

3QO{l

6OO/l

30pF

tEN

300Il

600/1

30pF

10·27

MB7113I/H
MB71141/H

Input/Output Circuit
Information

Input

In the input circuit, Schottky TTL
circuit technology is used to
achieve high-speed operation. A
PNP transistor In the first stage
of input circuit remarkably improves input high/low current
characteristics. Also, the input
circuit includes a protection diode
for reliable operation.

physical damage under these
conditions is unlikely, system
noise problems could result.
Therefore, the system deSigner
.should consider these factors to
ensure that this condition does
not exist.

Also in the output circuit,
Schottky TTL circuit technology is
used to achieve high-speed operation. Also, a PNP transistor provided in the output circuit is
effective to decrease a load for
the Chip Enable cirCUit.

MB7113/MB7114 Input

Open-Collector Output
The open-collector output is oiten
.utilized in high speed applications
where power dissipation must be
minimized. When the device is
switched, there is no current
sourced from the supply rail.
Consequently, the current spike
normally associated with TTL
totem-pole outputs Is eliminated.
In high frequency applications,
this minimizes noise problems
(false triggering) as well as
power drain. For example, the
transient current (low impedance
high-level to low impedance lowlevel) is typically 30 mA for the
MB7114 (3-state) compared to
o mA for the MB7113 (opencollector).

INPUT

o-~-I~-I(\--"".r

MB7113 Output

OUTPUT

Three-State Output
A "three-state" output is a logic
element which has three distinct
output states of ZERO, ONE and
OFF (wherein OFF represents a
high impedance condition which
can neither sink nor source current at a definable logic level).
Effectively, then, the device has
all the desirable features of a
totem-pole TTL output (e.g.,
greater noise immunity, good rise
time, line driving capacity), plus
the ability to connect to busorganized systems.

MB7U4 Output

In the case where two devices
are on at the same time, the possibility exists that they may be in
opposite low impedance states
simultaneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While

10-28

OUTPUT

MB7113E/H
MB7114E/H

Typical Characteristics
Curves

IINC Input Current
vs. V IN Input Voltage

IINA Input Current
vs. V IN Input Voltage

TA

= 2S"C

TA = 25°C

-

~

0

:::::~ K""
~

~

!

W

~vee=4.5V
Vee

."
at=<
....

= S.OV

r--

Vee = j"SV

~~~

-10

'\Svee = 4.5V

Vee = S.OV
Vee = 5.5V

z-

WI-

.. Z

jt3
M~7113/'14
1.0

MBr113/'~

-30
-1.0

2.0

1.0

ION Output High Current
vs. VON Output High Voltage

~A 2S~C

II

=
80 f- Vee = 5.OV

S.

i

/

50

W

0:
0:

"
0

~

I-

"I!:

5
~

40

I

30

o

= 25°C

1
!itW

V ,,J/ I

-10

0:
0:

B -20 /'"
:z:

:z: -30

~ -40

"/ ~ ~o

0 /'

Vee = 4.5V- f----

' " Vee
Vee

= s.ov
= 5.5V- r--

:l

o

~-50

/
200

TA

52

/

10

o

V

V

20

2.0

VIN. INPUT VOLTAGE (V)

10L Output Low Current
vs. VOL Output Low Voltage

:c

r--

-20

V,N. INPUT VOLTAGE (V)

70

f----

%~

00:

0

-30
-1.0

----= .......~

I-

i"""""

MB7113/14
400

600

VOL. OUTPUT LOW VOLTAGE (mV)

FUJITSU

10-29

M87114

-80

o
VOH. OUTPUT HIGH VOLTAGE (V)

MB7113E/H
MB7114E/H

Typical Characteristics
Curves
(Continued)

tAA Access Time
VS. Ambient Temperature

tAA Access Time
VS. Ambient Temperature

70

70
MB7113

MBil14

60

!..
::E

r::

.."'"'
...

60

40

u
u

30

:f

20

...s.r::
.~j
;;

50

::E

= 4.5V
r-- /"VCC
Vee = 5.0V

~

' / .Vee = 5.5V

~L

---

10

o

-50

~~

u

40
30
20

Vee = 4.5V

~VCC=S.ov

r-- ~VCC=5.5V

o

-50

t DIS Disable
VS. Ambient

t DlS Disable Time
vs. Ambient Temperature

MBil14
60

!..

50

Ol

.r::
::E

40

~
j

40

~

30

oJ

m

Vee = 4.5V

30

~~ ~ ~:~~

\
\

20

50

..r::
::E

oJ

m

Time
Temperature

70

M~113

60

;;
S-

~

I~ ~

Vee = 4.5~~ I - Yee = S.OY

is

.;

;9

Vee
20

o

-50

50

o

100

-50

50

70

70

Maim

MBJll3

60

60

I..

50

..r::
....
::E

40

50
40

oJ

oJ

z

100

TA. AMBIENT TEMPERATURE rC)

tEN Enable Time
VS. Ambient Temperature

tEN Enable Time
VS. Ambient Temperature

m

5.5Y,\

\~

T A. AMBIENT TEMPERATURE ("C)

.~
.
...
j

=

10

10

!

100

50

TA. AMBIENT TEMPERATURE ('C)

TA. AMBIENT TEMPERATURE ("C)

70

~

~

10

100

50

50

30
20

§

m

Vee = 4.5V
Vee = S.OY
Vee = 5.5V

z

~

:::-"'-L

o

20

-

h

Vee = 4.5V
Vee = 5.0V
Vee = 5.5V

=-"""

10

10

-50

30

50

100

TA. AMBIENT TEMPERATURE ('C)

10-30

o

-50

50

100

TA. AMBIENT TEMPERATURE ('C)

MB7113E/H
MB7114E/H

Typical Characteristics
Curves
(Continued)

Delay Time Increse
C L Load Capacitance

Delay Time Increase
vs. C L Load Capacitance

VB.

70

70

MB~113

MB7114

60

60

~

UJ

~

50

w

U>

"w
II:

40

UJ

:&

30

"<>

20

~~ V

F
>

..J
UJ

,./'
10

o

Ul

I~ ~DD. T~ 'EN DELAY

(.)

l!;

/ v ,..o

100

50

U>

ADD. TO tAA DELAY

~

-

II:

(.)

l!;
UJ

A~. TO tAA DELAY

:&

30

:s>w

20

F

~

<>

~

o

300

o

100

300

200

el, LOAD CAPACITANCE (pF)

eL, LOAD CAPACITANCE (pF)

Package Dimensions
Dimensions in inches
(millimeter)

ADD. TO tEN DELAY

D, I~ ~
f.-::::: r:::- f---" f---"

10

I--"-

200

40

16·Lead Ceramic (CERDIP) Dualln·Line Package
(Case No.: DIP·16C·C02)

::~1~:::::]1::'
--

I

.754(19.15)
.788(20.02)

.
I

.020(0.51)
.050(1.27)

FUJITSU

10-31

lo

15

tr
.305(7.75)

.300(7.62)TVP

.325(8.26)

~
.014(0.36)

MB7113E/H
MB7114E/H

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

1&-Lead Plastl D
.
ICase No.: DIP~16=~~~,;~'ne Package

,-!:::::]j~
I
I~

.75~19.20)

.780(19.81)

r __.",_"",,::::::=:l==-O" -15'
.290(7.37)
.310(7.87)

•

::-Lead Plastic Flat Package
ase No.: FPT-16P-M02)

~R: ! :~: : !h~ '!1:d!RR~~ I

IrRR

c/

INOEX

Details of "A" part

l·29117.41
.32318.21
.19715.01

'lr=nr==;n=;;=::;:;:::::;:;;::::::;=dJ~5.61

.26016.61

-' _

,
'k I
~_
A ,\

.03911.0)

~.28317.21
,,
I

- .00510.131
T
.00810.201
.08512.151
MAli

10·32

.01210.31

~.028(0.71

.02010.51
.00710.181
MAX
.02710.681
MAX

Advanced Information
Availability Q2 '86

FUJITSU

Bipolar PROM
•

MB7113L/7114L
Low Power 1024-Bit
Schottky TTL PROM

F•• tur.s
• Organization:
258 x 4-blts
• Procass:
Schottky TTL
• Program:
Dlffusad Eutsctlc Aluminum
Proc... (DEAP)
• OUtput:
Open Collector (MB7113)
Thre.State (MB7114)
• Power Supply:

+5V ±5%

• Power Dlsslpstlon:
200 mW max.

• Add,..s Accaas Time:
55 na max.
• Package:
1~ln DIP

10·33

FUJITSU

Bipolar Memories
•

MB7115E/H, MB7116E/H
Programmable Schottky
2,048~Bit Read Only Memory

Description
The Fujitsu MB7115 and MB7116 are high speed Schottky TTL
electrically field programmable read only memories organized as
512 words by 4-bits. With uncommitted collector outputs provided
on the MB7115 and three-state outputs on the MB7116, memory
expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable DEAP
(Diffused Eutectic Aluminum Process) according to simple programming procedures.
The sophisticated passive Isolation termed SVG (Shallow VGroove) with thin epitaxial layer and Schottky TTL process permits
minimal chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuits in
order to perform AC, DC and programming test prior to shipment.
This results in extremely high programmability.

Featurea
• Single +5V supply voHege
• 512 words x 4-blts orgenlza•
•
•
•
•

tlon, fully decoded
Proven high programmability
and reliability
Programming by DEAP
(Diffused Eutectic
Aluminum Procesa)
SlmplHled low power
programming
Low current PNP Inputs
AC characteristics guaranteed
over full operating voltege and
temperature range via unique
testing tschniques

•

Fast access time, 20 ns typo
H: 35 ns max.

•

TTL compatible Inputs and
outputs
Open collector outputs

E: 45 ns max.

•

(MB7115)

3-stste outputs (MB7118)
Chip enable lead for simplified memory expansion
• Standard 16-pln DIP
package
• JEDEC approved pin out
•
•

This device contains circuitry to
protect the inputs against damage
due to high static voltages or alech'lc fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voIt~
ages to this high impedance circuit.

10-34

MB7115E/H
MB7116E/H

MB7115/7116 Block Diagram
and Pin Assignments

Ao

Vee
(Pveel

As

A,

Ao

Aa
E(pve)
0,

A,

2048 (64 x 321 alT

MEMORY CELLS

Ao
A,

0,
0,

GND

O.

A,

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Valua

Unit

Power supply voltage

Vee

-0.510 +7.0

V

Power supply voltage
(during programming)

Vee

-0.5 to +7.5

V

VIN
VIPAG

-1.510 +5.5

V

Inpul voltage (during programming)

22.5

V

Output voltage (during programming)

VOPAG

-0.5 to +22.5

V

Input CUlTent

Input voltage

liN

-20

mA

Input current (during programming)

IIPAG

+270

mA

Output cUlTent

IOLIT

+100

mA

Oulput CUlTent (during programming)

IOPAG

+150

mA

Storage temperature

Ceramic
Plastic

Output voltage

TSTG

VOUT

-65 to +150
-40 to +125
-0.5 to Vee

"C
V

Note: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU

10·35

MB7115E/H
MB7118E/H

Guaranteed Operating
Conditions

Capacitance
(! = 1 MHz, Vee = +5V,
VIN = +2V, TA = 25·C)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.75

5.0

5.25

V

Input low voltage

Vil

0

0.8

V

Input high voltage

VIH

2.0

5.5

V

Ambient temperature

TA

0

75

·C

Parameter

Symbol

Max

Unit

Input capacitance

CI

10

pF

Output capacitance

Co

12

pF

Typ

Min

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Input leakage current
(VIH = 5.5V)

Min

Typ

Max

Unit

IR

40

pA

Input load current
(Vll = 0.45V)

IF

-250

pA

Output low voltage
(IOl = 10 rnA)

VOL

0.45

V

Output low voltage
(lOl = 16 rnA)

VOL

0.50

V

Output leakage current
(Vo = 2.4V, chip disabled)

MB7115

10lK

40

/LA

Output leakage current
(Vo = 2.4V, chip disabled)

MB7116

10lH

40

/LA

Output leakage current
(Vo = 0.5V, chip disabled)

MB7116

lOll

-40

pA

Input clamp voltage
(liN = -18 rnA)

Vie

-1.2

V

Power supply current
(VIN = OPEN or GND)

lee

120

rnA

70'2

Output high voltage
(10 = -2.4 rnA)

MB7116

VOH 'l

2.4

Output short circuit current
(Vo = GND)

MB7116

105'1

-15

V
-60

rnA

Not..: "1 Denotes guaranteed characteristics of the output high-level (ON) state when the chip is enabled (V~ = O.4V) and the programmed
bit is addressed, These characteristics cannot be tested prior to programming. but are guaranteed by factory testing.
*2 This value denotes conditions at TA = 25°C and Vee = +5.0V.

AC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

E
Typ

Max

H
Typ

Max

Unit

Access time (via address input)

tM

20

45

20

35

ns

Output disable time

t OIS

15

30

15

30

ns

Output enable time

tEN

15

30

15

30

ns

10-36

MB7115E/H
MB7116E/H

Operation Timing Diagram
ADDRESS
INPUT

r-------------

\V I5V

V,L

"-___-+_________-+______________

V,L

CHIP
ENABLE
INPUT

-------~Fr~~--=\f.IAA
OUTPUT

CHIP
ENABLE
INPUT

V,H

\i/15V

_ _ _ _ _ _ _-'/1\'1-· _ _ _ _ _~/I\'-·_ _ _ _ _ _ _ _ _

1.~

__________ J

E _ _ _ _ _ _ _ _J

VOH

1.W
'I- _ _ _ _ _ _ _ _ _

~

1.5V
' - - - - - - - - - - - - - V,L

OUTPUT

" - - - - - - - - - - - - VOL

NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
IMPEDANCE STATE WHEN THE CHIP ENABLE IS TAKEN HIGH (DISABLED). OUTPUT
ENABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN
THE CHIP ENABLE IS TAKEN LOW (ENABLED). THE HIGH IMPEDANCE STATE IS

DEFINED AS A POINT ON THE OUTPUT WAVEFORM EQUAL TO A .lV of O.5V FROM
THE ACTIVE OUTPUT LEVEL.

AC Test Conditions

Input Conditions

--~-Vcc

Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to 3V
Rise and Fa" Time ........................... 5 ns from lV to 2V
Frequency .............................................. 1 MHz
TRUTH TABLE
MB71IS/MB7116

I
I
I

RI

R2

CL

IAA

300n

800!!

30pF

lOIS

300!!

6OO!l

30pF

lEN

3000

GOO!!

30pF

FUJITSU

10·37

MB7115E!H
MB7118E/H

Input/Output Circuit
Information

Input
In the input circuit, Schottky TTL
circuit technology is used to
achieve high-speed operation. A
PNP transistor in the first stage
of input circuit remarkably improves input high/low current
characteristics. Also, the input
circuit includes a protection diode
for reliable operation.

physical damage under these
conditions is unlikely, system
noise problems could resutt.
Therefore, the system designer
should consider these factors to
ensure that this condition does
not exist.

Also in the output circu~,
Schottky TTL circuit technology is
used to achieve high-speed operation. Also, a PNP transistor provided in the output circu~ is
effective to decrease a load for
the Chip Enable circuit.

MB7115/MB7118 Input

Open-Collector Output
The open-collector output is often
utilized in high speed applications
where power dissipation must be
minimized. When the device is
switched, there is no current
sourced from the supply rail.
Consequently, the current spike
normally associated with TTL
totem-pole outputs is eliminated.
In high frequency applications,
this minimizes noise problems
(false triggering) as well as
power drain. For example, the
transient current (low impedance
high-level to low impedance lowlevel) is typically 30 mA for the
MB7116 (3-slate) compared to
mA for the MB7115 (opencollector).

INPUT

o-.....-I"'""-IK~-4--["

MB7115 Output

o

Three-State Output
A "three-slate" output is a logic
element which has three distinct
output states of ZERO, ONE and
OFF (wherein OFF represents a
high impedance condition which
can neither sink nor source current at a definable logic level).
Effectively, then, the device has
all the desirable features of a
totem-pole TTL output (e.g.,
greater noise immunity, good rise
time, line driving capacity), plus
the ability to connect to busorganized systems.

MB7118 Output

In the case where two devices
are on at the same time, the possibility exists that they may be in
opposite low impedance states
simultaneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While

10-38

OUTPUT

MB7115E/H
MB7116E/H'

Typical Characteristics
Curves

IINA Input Current
vs. V IN Input Voltage

IINC Input Current
vs. V IN Input Voltage

TA = 25'C

TA

!!;:sl-10

~ ~ :::: -

= 4.5V
Vee = S.OV
Vee = S.5V

Co:

I-:: ~
I""'"'"
~~~

0

~vee

~~
Co:

Q

--

........-: ~

i

= 2S C

I~vee=
Vee

r--

_iG -20
MB7115/16
-1.0

1.0

MB7115/16

-30
-1.0

2.0

1.0

V'N, INPUT VOLTAGE (V)

70

.fA =

60 I-- Vee = 5.0V

Ii

50

""3t

40

1/

.E.

J

"'a:a:

S
0

~

J

30

II

o

/
200

= 2S"'C

1
~

-10

a

-20

:z:

!2

::c -30

i
!;
o

1/

10

TA

"'a:

V

20

o

10H Output High Current
vs. V OH Output High Voltage

~'C

~

2.0

V'N, INPUT VOLTAGE (V)

IOL Output Low Current
vs. VOL Output Low Voltage

!;

r--

0

-30

9

4.5V

= S.OV

Vee = J5V

~ llll

~ ~K
LS:
~V
./

~ Vcc= 4.5V-

r--

Vee = S.OV
Vee = 5.5V-

r--

-40

~-50
MB7115/16

600

400

VOL, OUTPUT LOW VOLTAGE (mV)

FUJITSU

10·39

MB7116

-60

o
VOH, OUTPUT HIGH VOLTAGE (V)

MB7115E/H
MB7116E/H

Typical Characteristics
Curves
(Continued)

tAA Access Time
vs. Ambient Temperature

!w
~

m

~
j

tAA Access Time
vs. Ambient Temperature

70

70

60

.

60

.,.,1=
w

40

50

So

w
:;

40
30
20

;:r--

~

u
u

":f.

10

50

30
20

~ t::- t--

~

10
MB7116

7115

o

-50

o

100

50

-50

TA. AMBIENT TEMPERATURE (0C)

t DIS Disable Time
vs. Ambient Temperature

t DIS Disable Time
vs. Ambient Temperature
70

60
50

1=

40

:;

....ill

..
So
w
1=
w
:Ii

."...

w
30

~

Zi

j

20

k:::::

10 t:::...

j

60
50

40
30
20

1=
10

MB7115

o

-50

100

TA. AMBIENT TEMPERATURE (0C)

70

Iw

50

50

100

TA. AMBIENT TEMPERATURE (OC)

10·40

MB7116

o

-50

50

100

TA. AMBIENT TEMPERATURE ("C)

MB7115E/H
MB7118E/H

Typical Characteristics
Curves
(Continued)

tEN Enable Time
vs. Ambient Temperature

tEN Enable Time
vs. Ambient Temperature

70

..
S
w
::E

1=

MBJl16

60

50

Iw

50

1=

40

::E

40

..

30

~

20 r-

w
....
c
zw

70

MB7~15

60

..

w
....
cz

-

30

w

~

10

20

~

10

o

-50

o

100

50

-50

TA. AMBIENT TEMPERATURE (0C)

Delay Time Increase
C L Load Capacitance

..::::- :--50

Delay Time Increse
C L Load Capacitance

VS.

VS.

70

70
MB7115

MB7116

60

60

Iw

!w

50

U>

:ia:

u
i!!

40

cw

~ !DD. T61EN DELAY

~

1=

20

/

Q

10

o

/.
o

100

50

U>

ADD. TO tAA DELAY

w
::E 30

5w

100

TA. AMBIENT TEMPERATURE rC)

40

::E

30

5w

20

i!!
w

AD~. TO tAA DELAY

1=

/
~

-

a:
u

"'-

Q

.->-

200

CL. LOAD CAPACITANCE (pF)

FUJITSU

10-41

300

10

o

ADD. TO tEN DELAY

'" ""

I--"

o

100

200

CL. LOAD CAPACITANCE (pF)

300

MB71tSE/H
MB71t811/H

Packalle Dlmen.lon.
Dimensions in inches
(millimeter)

18-Lead Ceramic ICERDIP) Dualln.Llne Packalle
ICa. . No.• DIP.18c.c02)

i::::::I~~ .32IJJ~==-_T_-'.305(7.75)

I~

.7~19.15)

.788(20.02)

~I

18·Lead Pla.tlc Dual In.Une Packalle
ICa.e NO.1 DIP.18P·M02)

t
INDEX

.234(5.94)
.2~6.45)

~=r=;=:;:::;:==r::::r==;=;=r=r=:::;::::r==?!~
.758(19.20)
.780(19.81)

10-42

.290(7.37)
.310(7.87)

FUJITSU

Bipolar Memories
•

MB7117E/H, MB7118E/H
Schottky TTL 2048-Bit
Bipolar Programmable
Read-Only Memory

Description
The Fujitsu MB7117 and MB711B are high speed Schottky TTL
electrically field programmable read only memories organized as
256 words by B-bits. With uncommitted collector outputs provided
on the MB7117 and three-state outputs on the MB711B memory expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable
DEApTM (Diffused Eutectic Aluminum Process) according to simple
programming procedures.
The sophisticated passive isolation termed lOP (Isolation by Oxide
and Polysilioon) with thin epitaxial layer and Schottky TTL process
permits minimal chip size and fast access time.
Extra test cells and unique testing methods provide enhanced correlation between programmed and unprogrammed circuits in order
to perform AC, DC and programming test prior to shipment. This
results in extremely high programmability.

Features
• Single +5V supply voltage
• Organized as 256 words by
8-bits, fully decoded
• Proven higher programmability and reliability
• Programming by DEApTM
(Diffused Eutectic Aluminum Process)
• Simplified, low power
programming
• Low current PNP Inputs
• AC characteristics guarantead over full operating voltage and temperature range
via unique testing
techniques

• Fast access time, 25 nsec
typo
E-45 nsec max.
H-35 nsec max.
• TTL compatible Inputs and
outputs
• Open collector outputs,
MB7117

• Three-state outputs, MB7118
• Two chip enables for simplified memory expansion
• Standard 2G-pin DIP
package
• JEDEC approved pin out

10-43

MB7117E/H
MB7118E/H

MB7117E/H, MB7118E/H
Block Diagram and Pin
Assignment

AO

(PVee)
Vee

A,

A,

Ao

A,

A,

A,

A:o

As

2048 (64 X 32)

A,

BIT

14

E,

A,

0,

E,(PVE)

14

0,

0,

0,

0,

MEMORY CELLS

As

A,
A,

0,

0,

GND

Ds

A2 A1

Ao

Vee A7

1 3__ !: ____
2 : I : 20 iL 19:
___ J
t ____• ____

:'~

4---!

A,

A:o __ oj

14

5..1

0,

6

0,
0,

0,

00

Ds

0,

0,

02

0,

0,

i

As

E2
E,

TOP VIEW

Il

O.

0, GND Os O. 0,

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Power supply voltage

Vee

-0_510 +7_0

V
V

Power supply voltage (druing programming)

Vee

-0.5 to +7.5

Input vollage

VIN

-1.5 to +5.5

V

Input voltage (during programming)

VpRG

22.5

V

Output voltage (during programming)

V

VPRG

0.510 +22.5

Inpul current

liN

-20

mA

Inpul current (during programming)

IpRG

+270

mA

Oulput current

lOUT

+100

mA

OUlput current (during Programming)

IpRG

+150

mA

Ceramic
Siorage lemperature

-6510 +150
TSTG

Plaslic

Output voltage

VOUT

-4010 +125
-0.510 Vee

'C
V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
conditions as detailed in the operational sections of this data sheet. This device contains circuitry to protect the inputs against damage due to
high static voltages or electric ftelds. However. It is advised that normal precautions be taken to avoid application of any voltage higher than
maximum rated vohages to this high impedance circuit.

FUJITSU

10·44

M87117E/H
M87118E/H

Guarantaed Operating
Conditions

Capacitance
(I = lMHz, Vee = + 5V,
VIN = +2V, TA = 25'C)

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Typ
5.0

Supply voltage

Vee

4.75

Input low voltage

Vil

0

Max

Unit

5.25

V

0.8

V

Input high voltage

VIH

2.0

5.5

V

Ambient temperature

TA

0

75

'c

Parameter

Symbol

Max

Unit

Input capacitance

CI

10

pF

Output capacitance

Co

12

pF

Min

Parameter
Input leakage current (VIH

Typ

Symbol

= 5.5V)

Min

Typ

IR

= 0.45V)
= lOrnA)
Output low voltage (lOl = 16mA)
Output leakage current (Vo = 2.4V, chip disabled)
Output leakage current (Va = 2.4V, chip disabled)
Output leakage current (Va = 0.45V, chip disabled)
Input clamp voltage (liN = -18mA)
Power supply current (VIN = OPEN or GND)
Output high voltage (10 = -2.4mA)
Output short circuit current (Va = GND)

Max

Unit

40

!LA

Input load current (Vll

IF

-250

p.A

Output low voltage (IOl

VOL

0.45

V

VOL

0.50

V

MB7117

10lK

40

p.A

MB7118

10lH

40

p.A

-40

p.A

Note:

AC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Min

MB711a. lOll
VIC
80

lee
MB7118

VOH "

2.4

MB711B

los"

-15

-1.2

V

140

rnA

-60

rnA

V

O.4V) and the programmed
d, y factolY
testing.

·1 Denotes guaranteed characteristics of the output high~lever (ON) state when the chip is enabled (V
bit is addressed. These characteristics cannot be tested prior to programming, but are guarantee

=

Parameter

Symbol

M87117E/
M87118E
Typ
Max

Access time (via address input)

tM

25

Output disable time

t DIS

30

30

ns

tEN

30

30

ns

Output enable time

10-45

45

MB7117H/
M87118H
Typ
Max

Unit

25

35

ns

MB71t7E/H
MB71t8E/H

Operation Timing Diagram
r-----------------------v~

ADDRESS
INPUT

\

1.SV

\V1.5V

_______-JJ \'--_____-JJ[\'-_ _ _ _ _ _ _ _ _ V,L
E --------""\

CHIP
ENABLE
INPUT

V,H

'-------+-------------------+---------------------------

- -f.:r~AA----=\~"'"
1.~

OUTPUT

L~

----------~

V,L

VOH

~------------~
V,H

CHIP
ENABLE
INPUT

E ________________J

1.SV

~-----------------------V~

OUTPUT

~-----------------------V~

NOTE: OUTPUT DISABLE llME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS TAKEN HIGH (DISABLED).
OUTPUT ENABLE llME IS THE llME TAKEN FOR THE OUTPUT TO BECOME AC11VE
WHEN ALL OF CHIP ENABLES ARE TAKEN LOW (ENABLED). THE HIGH
RESISTANCE STATE IS DEFINED AS A POINT ON THE OUTPUT WAVEFORM EQUAL
TO A IlV OF O.~ FROM THE AC11VE OUTPUT LEVEL

AC Test Conditions
Input Conditions
Amplitude: OV to 3V
Rise and Fall Time: 5 ns from 1V to 2V
Frequency: 1MHz

Rl

R2

CL

lAA

3000

6000

30pF

lDiS

3000

6000

30pF

lEN

3000

6000

30pF

R,

FUJITSU
4

----t---VCC

10-46

MB7117E/H
MB7118E/H

Input/Output
Circuit Information

Input Circuit
Schottky TTL circuit technology is
used in the input circuit to
achieve high-speed operation. A
PNP transistor in the first stage
of the input circuit improves input
high/low current characteristics
remarkably. The input circuit also
includes a protection diode for
reliable operation.

Also in the output circuit,
Schottky TTL circuit technology is
used to achieve high-speed
operation. A PNP transistor is

also provided in the output circuit
and is effective in decreasing a
load for the Chip Enable circuit.

MB7117/MB7118 Input Circuit

-.---+--.....- vee

Open Collector Output
The open collector output is
oiten utilized in high-speed
applications where power
dissipation must be minimized.
When the device is switched,
there is no current sourced from
the supply rail. Consequently, the
current spike normally associated
with TTL totem-pole outputs is
eliminated. In high-frequency
applications, this minimizes noise
problems (false triggering) as
well as power drain. For
example, the transient current
(low impedance high-level to low
impedance low-level) is typically
30mA for the MB7t 18 (threestate) compared to OmA for the
MB7117 (open-collector).

INPUT

o-.....-t:=--ll<\--.....-t'

MB7117 Output Circuit

Three-Slate Output
A "three-state" output is a logic
element which has three distinct
output states of ZERO, ONE and
OFF (wherein OFF represents a
high-impedance condition which
can neither sink nor source
current at a definable logic level).
Effectively, then, the device has
all the desirable features of a
totem-pole TTL output (e.g.,
greater noise immunity, good rise
time, line driving capacity), plus
the ability to connect to busorganized systems.

MB7118 Output Circuit

In the case where two devices
are on at the same time, the
possibility exists that they may be
in opposite (one a ONE and one
a ZERO) impedance states
simultaneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While
physical damage under these
conditions is unlikely, system
noise problems could result.
Therefore, the system designer
should consider these factors to
ensure that this condition does
not exist.

10-47

OUTPUT

MB7117E/H
MB7118E/H

Typical Characteristics
Curves

IINA Input Current
V IN Input Voltage

IINC Input Current
vs. VIN Input Voltage

VS.

TA = 25 C

TA

-

~~~

0

~vee = 4.SV
Vee

= S.OV

Vee = S.OV

0

Mr71111 !8

M~7117/1~

-30

-30
-1.0

2.0

1.0

~1.0

VIN. INPUT VOLTAGE (V)

10L Output Low Current
VOL Output Low Voltage

10H Output High Current
VOH Output High Voltage

VS.

70

iA =
60 -

2S~C

/
I

V

a:
a:

::>

";=0
....

5

I!:

::>
0

~

40
30

/

20
10

o

VS.

Vee = S.OV

50

o

/

TA

!Zw

~VI

-10

a:

B
:z:

-20

/

!2

:z: -30

5
~
o

/

/

..
:;
1=

w

MB7118

-60

600

400

o
VQH, OUTPUT HIGH CURRENT(V)

..""j

tAA Access Time
vs. Ambient Temperature

60

60

30
20

.........:

-

~

V

i

= 4.5V
Yee = S.OV
Vee = S.SV

Vee

-

"e. ~

"""

i

!
j

10

.I.Vee = 4.SV
I

50

40

30

~vee=5.OV

~

V

VCC =5.5V

.....::::;;

~

20

10
MB1118

MB7117

o

-50

S.OV

= S.sv- f---

.9 -50

70

~

Vee

V

-40

70

40

Vee = 4.5V- c - -

~vcc=

;;

tAA Access Time
VS. Ambient Temperature

v

~~K
o

v::V

MB7117/18

200

50

= 2S'C

1

VOL. OUTPUT LOW VOLTAGE (mA)

!w

2.0

1.0

YIN. INPUT VOLTAGE (V)

g
!Z

-

Vee = S.SV

-20

w

~

~vee = 4.SV

f---

Vee = j.SV

C-

-

i-": ~

-: !:;;I
~~~

-10

= 25 C

100

50

TA, AMBIENT TEMPERATURE ('C)

FUJITSU

10-48

o

-50

50

100

T A. AMBIENT TEMPERATURE ('C)

MB7117E/H
MB7118E/H

Typical Characteristics
Curves
(Continued)

t DS Disable Time
vs. Ambient Temperature

t DIS Disable Time
vs. Ambient Temperature

70

70

60

!w

50

1=

40

..
.....

w

C

"'

60

....ill

40

~

Vee

30
20

50

w

/ Vee = 4.5V

~

15

j

;;
S.
w

= 5.0V

/Vee = 5.5V

.,,/"

::-L(/ ;/

/
30

j

10

20
10

~cc = 4.5V
Vee

15

-

= S.OV

/, ~vee=

..-:

o

o

100

50

-50

TA. AMBIENT TEMPERATURE ( C)

70

60

60

1=
w

40

C

30

'..."

..

zw

j

tEN Enable Time
vs. Ambient Temperature

70

50
.. _Vcc=4.5V
Vcc=5.0V
Vcc=5.5V

./:

L~ ; /

20

100

50

T A. AMBIENT TEMPERATURE rC)

tEN Enable Time
vs. Ambient Temperature

!w

-

;;
S.
w

50

.:Ii...

40

~

w
30

w

j

20

-

~

~V

Vcc=4.5V
Vcc=5.0V

MBrn8

MBr17

o

-50

50

o

-50

100

TA. AMBIENT TEMPERATURE ('C)

Delay Time Increase
vs. C L Load Capacitance

70

MB~n7

;;
S. 50
40

!E
w 30
1=

..

"'"

~DD. T~

20

~

10

V

0

/.
o

100

!w

50

II:

40

!IIw

ADO. TO tAA DELAY

o

MB~t18

60

.,w

5w

100

TA. AMBIENT TEMPERATURE ('C)

60

U

50

Delay Time Incr_se
vs. C L Load Capacitance

70

II:

-

Vcc=S.SY

10

10

~

~

MB7118

MB7117

-50

.....-

5.5V

L

U

tEN DELAY

~
~

-

!E
w 30

AD~. TO tAA DELAY

~

5w

~

20

0

I--"""

200

CL. LOAD CAPACITANCE (pF)

10-49

300

10

o

ADD. TO tEN DELAY

"" ""

~~,....

o

100

200

CL. LOAD CAPACITANCE (pF)

300

MB7117E/H
MB7118E/H

Package Dimensions
Dimensions in inches
(millimeters)

20·Pln Cerdlp Dual In· Line Package
DIP·20C·C01

.090(2.29)
.110(2.79)

~---r--------~.~~0(=22~.8~6~)R~E~F---------H--~

20·Pln Plastic Dual In·Line Package
DIP·20P·M02

115oMAx.

~~==-.

.254(6.45)

~~~TTTTTT~~~~~

J

.953(24.2)
.976(24.8)

~
~ I.",,~ d~ ~

..,'" 1 .1

TYp.

.062(1.57)

1; : :

.015(0.38)· .046(1.16)

.021(0.54)

FUJITSU
10-50

.172(4.36) MAX .

.118(3.0) MIN.

MB7117E/H
MB7118E/H

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

20·Pad Ceramic (Frlt Seal) Leadless Chip Carrier
(Case No.: LCC·20C·F02)

PIN NO.1 INDEX

j

n

.040(1.02)TVP

(3 PLCS)

.345(8.76)80

~======~,.O"~

.25O(8.35)TYP

10·51

FUJITSU

Bipolar Memories
•

MB7121 E/H, MB7122E/H/Y
Programmable Schottky 4,096Bit Read Only Memory

Description
The Fujitsu MB7121 and MB7122 are high speed Schottky TIL
electrically field programmable read only memories organized as
1024 words by 4-bits. With uncommitted collector outputs provided
on the MB7121 and three-state outputs on the MB7122, memory
expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable DEAP
(Diffused Eutectic Aluminum Process) according to simple programming procedures.
The sophisticated passive isolation termed lOP (Isolation by Oxide
and Poly-silicon) with thin epitaxial layer and Schottky TIL process
permits minimal chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuits in order to perform AC, DC and programming test prior to shipment.
This results in extremely high programmability.

Fe.tures
• Single +5V supply voltage
• 1,024 words x 4-blts organization, fully decoded
• Proven high programmability and reliability
• Programming by DEAP (Diffused Eutectic Aluminum
Process)
•
Simplified, low power
programming
• Low current PNP Inputs
• AC charactarlStlcs guaranteed over full operating voltaga and tamperature ranga
via unique testing
techniques

•

•
•
•
•

•
•

Fast access time, 25 ns typo
MB7122Y: 30 ns max.
H: 35 ns max.
E: 45 ns max.
TIL compatible inputs and
outputs
Open collector outputs
(MB7121)
3-state outputs (MB7122)
Two chip enable leads for
simplified mamory
expansion
Standard 18 pin DIP
package
JEDEC approved pin out

This device contains circuitry to
protect the inputs against da"lage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to
avoid application of any vahage
higher than maximum rated voltages to this high impedance circuit.

10-52

MB7121E/H
MB7122E/H/Y

MB7122 Block Diagram
and Pin Assignments

A,

Vee
(PVec)

As

A7

A,
4096 (64 x 64) BIT

0,

MEMORY CELLS

02
AS

...

GND

As
A,

As

A6 Ne Vee A7

A,
., (PVE)

01

.2

NC

02

02

0,

As

AgNCNCNC01 02

[-L803

A7 2-6-:
NC
Vee
Ne

Absolute Maximum Ratings
(See Note)

27i
28:

11 04
[16 E(PVe)

115 Ne

Ne

-l
_2_~-J

A6

_3J

~4 GND
[~ Ne

As

~~

~!2

-1 -

LCC-28C-A01
TOP VIEW

Ne

Rating

Symbol

Value

Unit

Power supply voltage

Vee

-0.5 to +7.0

V

-0.5 to +7.5

V

Power supply voltage
(during programming)
Input voltage

-1.5 to +5.5

V

Input voltage (during programming)

22.5

V

Output voltage (during programming)

-0.5 to +22.5

V

Input current

-20

mA

Input current (during programming)

+270

mA

Output current

+100

mA

Output current (during programming)

+150

mA

Ceramic
Storage temperature

-65 to +150
TSTG

Plastic

Output voltage

-40 to +125
-0.5 to Vee

V

Nota: Pennanent device damage may occur jf ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU

10-53

M87121E/H
M87122E/H/Y

Guaranteed Operating
Conditions

Capacitance
(I = 1 MHz, Vee = +5V,
VIN = +2V, TA = 25'C)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.75

5.0

5.25

V

Input low voltage

Vil

0.8

V

Input high voltage

VIH

2.0

Ambient temperature

TA

0

75

'C

V

Parameter

Symbol

Max

Unit

Input capacitance

CI

Typ

10

pF

Output capacitance

Co

12

pF

Min

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Input leakage current
(VIH = 5.5V)

Min

Typ

Max

Unit

IR

40

fJ.A

Input load current
(Vll = 0.45V)

IF

-250

fJ.A

Output low voltage
(IOl = 10 mAl

Val

0.45

V

Output low voltage
(IOl = 16 mAl

Val

0.50

V

Output leakage current
(Va = 2.4V, chip disabled)

MB7121

10lK

40

fJ.A

Output leakage current
= 2.4V, chip disabled)

MB7122

10lH

40

fJ.A

Output leakage current
(Va = 0.5V, chip disabled)

MB7122

lOll

-40

fJ.A

Input clamp voltage
(liN = -18 mAl

VIC

-1.2

V

Power supply current
(VIN = OPEN or GND)

Icc

150

mA

(VA

105

Output high voltage
(10 = -2.4 mAl

MB7122

VOH 'l

2.4

Output short circuit current
(Va = GND)

MB7122

108'1

-15

V
-60

mA

Note: *1 Denotes guaranteed characteristics of the output high-level (ON) state when the chip is enabled (VICE = O.4V) and the programmed
bit is addressed. These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

M87121/7122E
Typ
Max

M87121/7122H
Typ
Max

M87122Y
Typ
Max

Unit

Access time (via
address input)

1M

25

25

25

Output disable time
Output enable time

45

30

ns

lOIS

30

30

25

ns

tEN

30

30

25

ns

10·54

35

MB7121E/H
MB7122E/H/Y

Operation Timing Diagram
,------------V'H

\V 1.5V
\ / , .SV
______-..JJI\'--_____-.J/I\'--_ _ _ _ _ _ _ _ V'L

ADDRESS

INPUT

CHIP

E" E2

ENABLE
INPUT

'----+----------+------------V'L

-------~~r~~--=,fIAA

OUTPUT

CHIP

_ _ _ _ _ _ _ _ _ _ -1

1.SV

VOH

1.SV

'-- _ _ _ _ _ _ _

VOL

Eh E2

ENABLE
INPUT

1.SV
'------------V'L

lEN

OUTPUT

'------------------V~
NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS TAKEN HIGH. OUTPUT ENABLE
TlME IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN THE CHIP
ENABLE IS TAKEN LOW. THE HIGH RESISTANCE STATE IS DEFINED AS A POINT ON

THE OUTPUT WAVEFORM EQUAL TO A 'V OF O.SV FROM THo ACTlVE OUTPUT
LEVEL

AC Test Conditions
Input Conditions

-----<~--VCC

~~~

............................................. W~W
Rise and Fall Time ........................... 5 ns from 1V to 2V
Frequency .............................................. 1 MHz
TRUTH TABLE
MB7121/MB7122

I
I
I

R,

R2

CL

lAA

300n

600n

3D pF

tOlS

300n

600n

30 pF

tEN

3OO!l

600/1

30 pF

FUJITSU

10-55

MB7121E/H
MB7122E/H/Y

Input/Output Circuit
Infor_tlon

Input
In the input circuit, Schottky TTL
circuit technology is used to
achieve high-speed operation. A
PNP transistor in the first stage
of input circuit remarkably improves input high/low current
characteristics. Also, the input
circuit includes a protection diode
for reliable operation.

physical damage under these
conditions is unlikely, system
noise problems could result.
Therefore, the system designer
should consider these factors to
ensure that this condition does
not exist.

Also in the output circuit;
Schottky TTL circuit technology is
used to achieve high-speed operation. Also, a PNP transistor provided in the output circuit is
effective to decrease a load for
the Chip Enable circuit.

MB7121/MB7122 Input

Open-Collector Output
The open-collector output is often
utilized in high speed applications
where power dissipation must be
minimized. When the device is
switched, there is no current
sourced from the supply rail.
Consequently, the current spike
normally associated with TTL totem-pole outputs is eliminated. In
high frequency applications, this
minimizes noise problems (false
triggering) as well as power
drain. For example, the transient
current (low impedance highlevel to low impedance low-level)
is typically 30 mA for the MB7122
(3-state) compared to 0 mA for
the MB7121 (open-collector).

MB7121 Output

Three-State Output
A "three-state" output is a logic
element which has three distinct
output states of ZERO, ONE and
OFF (wherein OFF represents a
high impedance condition which
can neither sink nor source current at a definable logic level).
Effectively, then, the device has
all the desirable features of a totem-pole TTL output (e.g., greater
noise immunity, good rise time,
line driving capacity), plus the
ability to connect to bus-organized systems.

OUTPUT

MB7122 Output

In the case where two devices
are on at the same time, the possibility exists that they may be in
opposite low impedance states
simultaneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While

10-56

OUTPUT

MB7121E/H
MB7122E/H/Y

Typical Characteristics
Curves

IINA Input Current
vs. VIN Input Voltage

TA

IINC Input Current
vs. V IN Input Voltage

= 25~C

TA = 25°C

-:: ~
i"""
~ ~ :":

-:: ~

I--

'\Svee = 4.5V
Vee

:::::~ ~ -

0

~~eC=4.5V

= 5.0V

Vee = 5.0V

Vee = i"5V r---

r---

Vee = j'SV
0

~Bn21l22

MBn211f
-30

-1.0

1.0

-30
-1.0

2.0

1.0

V,N. INPUT VOLTAGE (V)

10L OUtput Low Current
vs,VOL Output Low Voltage
70

-i.

=

60 I-- Vee = 5.0V

Ii;

so

::0

40

.5.

"'0:0:
0

~

30

::0

20

~

10

~

0

o

10H Output High Current
vs. VOH Output High Voltage

25~C

C-

/

T"

Ii;

/

o

/

I

~ 1/ ~

-10

1-20

5

:E -30

./

MB7122

-60

600

400

o
VOH. OUTPUT HIGH VOLTAGE (V)

60

60

.."'

40

0
0

30

:IE
j:::

~cc

Ul

.."'j

tAA Access Time
vs. Ambient Temperature
70

v

~

20

v/
L

V

I

= 4.SV

Vee = S.OV
Vee

--

= 5.5V

/

~

e

."'
:IE

J.

so

j:::

40

f30

30

j

20

II

10

Vee

I

= 4.SV

~vee= 5.0V

~

/vcc=

5.SV

.....::::::

-SO

:6

10
MBn22

MBn21

o

I--

~-so
MB7121/22

70

'iii'

Vee = 5.5V-

o

VOL. OUTPUT LOW VOLTAGE (mV)

.s.

0~cc= 4.5Y- r---

l~vcC = S.ov

~ -40

tAA Access Time
vs. Ambient Temperature

so

~ t5< K

v::V

::0

1/

200

= 2SCC

1

j

I

2.0

V,N. INPUT VOLTAGE (V)

so

100

TA. AMBIENT TEMPERATURE ('C)

FUJITSU

10-57

o

-SO

so

100

TA. AMBIENT TEMPERATURE ('C)

MB7121E/H
MB7122E/H/Y

Typical Characteristics
Curves
(Continued)

t DS Disable Time
vs. Ambient Temperature

!w

70

70

60

60

50

~

40

~

30

w
....

~

t DlS Disable Time
vs. Ambient Temperature

20

10

-

i

!w

50

.

40

,.1=

i/ vT 4'S

i

.....w

;VCc1=s,or

is

,..,...-::

jvcr=sy

~

30

$

20

VCC-4.S~ \

I

I

vcc=5.0~\
I
I

r-

Vcc=S.5V
~~

10
~IB7122

MB7121

so

Q

o

100

50

100

TA. AMBIENT TEMPERATURE ("C)

T A, AMBIENT TEMPERATURE ("C)

tEN Enable Time
vs. Ambi_t Temperature

tEN Enable Time
vs. Ambient Temperature

70

70
MB7121

60

60

I

50

!

40

i
j

!

,.1=

50

.

40

YO
....
c

30

iii

20 ~

YO

Vcc=4.5V
/

30

'i.vcc=s.ov
Vcc=6.6V

-

'iV

/

20

-

iii
z

10

VCC=4.5V
/ ; Vcc=5.0V
/
Vcc=5.5V

L VI

10

o

-50

0

50

MBt22

o

-50

100

TA, A_ENT TEMPERATURE ("C)

Delay Time Increase
C L Load Capacitance

50

Delay Time Increase
C L Load Capacitance

VSo

VBo

70

70
MB7122

MB7121

60

60

!w

1i'

oS 50
YO

~
II:

"!:

,.1=
YO

~
II:

ADD. TO tAA DELAY

40
""

30

20
S
w
Q

10

o

100

TA, AMBIENT TEMPERATURE (0C)

l..--'::
o

~

100

~DD. ~
~

V

lEN DELAY

,-/'

~

"!:w
:IE
1=

50
40
ADD. TO tAA DELAY

30

"'-

20
S
w
Q

.->300

200

CL, LOAD CAPACITANCE (pF)

10·58

10

o

o

100

ADD. TO lEN DELAY

~

~

---

200

CL, LOAD CAPACITANCE (pF)

300

MB7121E/H
MB7122E/H/Y

Package Dimensions
Dimensions in inches
(millimeters)

18·Lead Ceramic (CERDIP) Dual In· Line Package
ICase No.: DIP.18C.C01)

r---

t

0" -15

+t

I
I

.305(7.75)
.325(8.26)

1

.090(2.29)
.110(2.79)

I

300(7.62)TVP

J

.020(0.51)
.050(1.27)
.013(0.33)
.023(0.58)

Dimensions in
inches (millimeters)

18·Lead Plastic Dual·ln·Line Package
(Case No.: DIP.18P·M02)

t

INDEX-'

.240(6.10)
.260(6.60)

INDEX-2

0

/j'p;=;r=;r=;r=;r=;=;=;=r=;=r=:;=;=:;=r=i~~

.I

.850(21.60)
.876(22.25)

.016(0.40)

~

FUJITSU

10-59

",,=====~1;C;15'

MAX

.290(7.37)
.310(7.87)

MB71211/H
MB7122E/H/Y

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

20·Pad Ceramic (Frlt Seal) Leadle. . Chip Carrier
(Ca.e No.: LCC.20C·F02)
.040(1.02)TYP
(3 PLCS)

PIN NO.1 INDEX

j

.100(2.54)
MAX
.060(1.52)
TYP

-:;T"'Y;';P=-'-1"'1

.250(6.35)TYP

.050(1.27)
TYP

.040(1.02)
TYP

2a·Pad C.ramlc (Metal Seal) Leadl ••• Chip Carrier
(Ca •• No.: LCCo2aCoA01)
.085(2.16)TYP

'PIN 1 INDEX

I
C.015(0.38)TYP
.445(11.30)
.480(11.66)

.05O(1.27)TYP

.300(7.62)TYP

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

10·60

FUJITSU

Bipolar Memories
•

MB7123E/H, MB7124E/H
Programmable Schottky
4096-Bit Read Only Memory

Description
The Fujitsu MB7123 (open collector) and MB7124 (three-state) are
high-speed, Schottky TTL electrically field programmable read-only
memories organized as 512 words by 8-bits.
Fujitsu PROMS utilize a unique Shallow V-Groove (SVG) passive
isolation process which, combined with a very thin epitaxial layer
and the Schottky TTL process, provides small die sizes and very
fast access times.
The memory is fabricated with all cells low, the "zero" value for
positive logic. Logical "one" for a cell is achieved by programming.
Individual cells are programmed to a logical "one" using the highly
reliable Diffused Eutectic Aluminum Process (DEAP).
High programming yields are insured through the use of special
test cells to verify programmability on each device prior to
shipment.
Two guaranteed maximum access time options are available: the
7123 or 7124 "E" versions guarantee 45 ns maximum access time;
the 7123 or 7124 "H" versions guarantee 35 ns maximum access
time.

F••tures
•
•
•
•

•
•
•

Single +5V power supply
requirement
512 words x B-blts: fully
decoded
High lavels of programmability and reliebillty proven
in usa
Unique, reliable DEAP programming process
Low power, simplified programming techniques
Low current PNP inputs
AC characteristics gueranteed over the full operating
range

•

Fast. 25 ns typical access
time with two guaranteed
options:
7123m24 E: 45 ns max.
7123/7124 H: 35 ns max.
• TIL compatible Inputs and
outputs; open collector or
three-state
• Single Chip Enable Input
• JEDEC standerd pinout;
2O-pln package

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fiefds. However. it is advised
that normal precautions be taken to
avoid applicatlon of any voltage

higher than maximum rated voltages to this high impedance circuit.

10-61

MB7123E/H
MB7124E/H

MB7123/7124 Block Diagram
and Pin Assignment

AD
A,
4096 (64 X 64) BIT
MEMORY CELLS

A2

Ao

vcc(PVccJ

A,

As

A.

A7

As

As

Ao

As

A,

0,

~PVEI

Ao

a-

00

0,

0.

O.

00

GND

Os

As
As
A7

As

E(PVE)

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Power supply voltage

Vee

-0.5 to +7.0

V

Vee

-0.5 to +7.5

V

Power supply voltage
(during programming)

Unit

Input voltage

VIN

-t.5 to +5.5

V

Input voltage (during programming)

VpRG

22.5

V

Output voltage (during programming)

VpRG

-0.5 to +22.5

V

Input current

liN

-20

rnA

Input current (during programming)

IpRG

+270

rnA

Output current

lOUT

+tOO

rnA

Output current (during programming)

IpRG

+150

rnA

Storage temperature

-65 to +150

Ceramic
TSTG

Plastic

Output voltage

'C

-40 to +125

VOUT

V

-0.5 to Vec

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

Guaranteed Operating
Conditions

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.75

5.0

5.25

V

Input low voltage

VIL

Input high voltage

VIH

2.0

Ambient temperature

TA

0

Parameter

FUJITSU
10-62

0.8

V
V

75

'C

MB7123E/H
MB7124E/H

Capacitance
(I = 1 MHz, Vee = +5V,
VIN = +2V, TA = 25 C)
Q

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Max

Unit

Input capacitance

CI

Typ

10

pF

Output capacitance

Co

12

pF

Min

Parameter

Symbol

Input leakage current
(VIH = 5.5V)

Min

Typ

Max

Unit

IA

40

/LA

Input load current
(Vll = 0.45V)

IF

-250

/LA

Output low voltage
(Iol = 10 rnA)

Val

0.45

V

Output low voltage
(Iol = 16 rnA)

Val

0.50

V

Output leakage current
(Va = 2.4V, chip disabled)

MB7123

10lK

40

/LA

Output leakage current
(Va = 2.4V, chip disabled)

MB7124

10lH

40

/LA

Output leakage current
(Va = 0.45V, chip disabled)

MB7124

lOll

-40

/LA

Input clamp voltage
(lIN = -18 rnA)

VIC

-1.2

V

Power supply current
(VIN = OPEN or GND)

Icc

170

rnA

120

Output high voltage'1
(10 = -2.4 rnA)

MB7124

VOH

2.4

Output short circuit current'1
(Va = GND)

MB7124

los

15

V

-60

rnA

Note: ·1 Denotes guaranteed characteristics of the output high·level (ON) state when the chip is enabled (V,CE = O.4V) and the programmed
bit is addressed. These characteristlcs cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

H

E
Parameter

Symbol

Typ

Max

Typ

Max

Access time (via address input)

tM

25

45

25

35

ns

Output disable time

t DIS

15

30

15

30

ns

Output enable time

tEN

15

30

15

30

ns

10-63

Unit

MB7123E/H
MB7124E/H

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Operation Timing Diagram

ADDRESS
INPUT

\vr15V- - - - - - -.....\

11\'_ _ _ _ _ _ _ _ _ _ /

_ _ _ _ _ _ _ _ _ _ _ _- f

CHIP
ENABLE
INPUT

~

1.5V
~_ _ _ _ _ _ _ _ _ _ _ _ _ V,L

=, LIM

~---+---------+-------------- V,L

______
-_, I;~~ __
OUTPUT

~

j r - - - - - - - - - - - V,H

_ _ _ _ _ _ _ _ _ _ J ~~V

CHIP
ENABLE
INPUT

VOH

~1.W_ _ _ _ _ _ _ _ _
~

~

1.SV
~-------------VIL

lEN

OUTPUT
~------------VOL

NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS TAKEN HIGH. OUTPUT ENABLE
TIME IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN THE CHIP

ENABLE IS TAKEN LOW. THE HIGH RESISTANCE STATE IS DEFINED AS A POINT ON
tHE OUTPUT WAVEFORM eQUAL TO A ~v OF O.5V FROM THE ACTIVE OUTPUT
LEVEL.

AC Test Conditions

Input Conditions

TRUTH TABLE

MB7123/7124

Amplitude ................................... OV to 3V
Rise and Fall Time ........................... 5 ns from 1V to 2V
Frequency .................................. 1 MHz

---

o

j-50
IIIBrl23/~
-30
-1.0

1.0

2.0

liB 7124

-60

o
VOH. OUTPUT HIGH VOLTAGE (V)

V,N. INPUT VOLTAGE (V)

IlL Output Low Current
vs. VOL Output Low Voltage
70
iA =

IOL Output Low Current
vs. VOL Output Low Voltage

25~C

/

r-Yee= 5.OV

70
iA
-

Yee

= 25~C
= S.OV

/
/

J

/

/

J

I

V

1/
o

o

/
200

MB7123

400

800

YOLo OUTPUT LOW VOLTAGE (mV)

FUJITSU

10-66

o

o

/
200

J

1/
IIIB7124

400

600

VOL. OUTPUT LOW YOI.TAGE (mV)

MB7123E/H
MB7124E/H

Typical Characteristics
Curves
(Continued)

tu. Access Time
vs. Ambient Temperature

tAA Access Time
vs. Ambient Temperature
70

70

80

80

.I.
/~cc

-

f'"'o.,<;

10

~
/

vee = 5.OV
"/ Vee = 5.5V

-

-

f"""""'"

I

vee = 4.5V

- 4.5V

l0~ee= ~ov

~~

V/

VV

CC =5.5Y

~

10
MB7124

MB7123

o

-50

50

100

o

-50

TA. AMBIENT TEMPERATURE ("C)

50

t DIS Disable Time
vs" Ambient Temperature

70

70

80

80

/Vee = 4.5V

/~ee=
, 4.5V
,

vee = S.OV

-2

/vee = 5.5V

lLL '/

10

--

/

./
~

vee = 5.oV
'
I
jVCC
= 5.5V

/':

o

50

100

TA. AMBIENT TEMPERATURE ("C)

10·67

./

/

10

MB7123

-50

100

TA. AMBIENT TEMPERATURE ("C)

t DIS Disable Time
vs. Ambient Temperature

~

~

MB7124

o

-50

50

100

TA. AMBIENT TEMPERATURE ("C)

MB7123E/H
MB7124E/H

Typical Characteriatlca
Curvea
(Continued)

tEN Enable Time
va. Ambient Temperature

tEN Enable Time
va. Ambient Temperature

70

to

80

80

10

-

L

.L'

//

!w

50

.
!

40

•
1=
w

Yee ~ 4.SV
Vee,,: s.ov
Vee = 5.5V

J

30
20

10

Vee = 4.5V

-

/

/

~

I

Vee ": 5.OV

Vee = 5.5V

MB7123

o

-50

MB7124

o

100

50

-50

TA. AMBIENT TEMPERATURE ('C)

Delay Time Increaae
va, C L Load Capacitance

Delay Time Increaae
va. CL Load Capacitance

70

70

MB~123

80

I

~

5

I

40
",I
I
ADD. TO lEN DELAY

iE

5

20

1=

"

~

ADD. TO 1M DELAY

30

10

o

MB~124

80

50

~

100

50

TA. AMBIENT TEMPERATURE ('C)

V

"

100

200

--

300

CL. LOAD CAPACITANCE (PF)

FUJITSU

10-68

AD~. TO IA. DELAY

w 30
1=

~~ V
~

40

iE

•

~
o

II:
U

50

~
w

"-

20

10

o

o

100

ADD. TO leN DELAY

-

"- "200

Ce. LOAD CAPACITANCE (pF)

300

MB7123E/H
MB7124E/H

Package Dimensions
Dimensions in inches
(millimeters)

20·Lead Plastic Dual In·Line Package
(Case No.: DIP.20P.M02)

1

~;;;2-=--.

~
~ ll! ~

.172(4.36) MAX•

=51)

•100(2.54)
TYP

I •• 1

.050(1.27)
.062{1.57)

J l.- _ I•.
~
.021(0.54)

20·Lead Ceramic (CERDIP) Dual In·Line Package
(Case No.: DIP.20C.C01)

10-69

MIN .

034(0.86)
.046(1.16)

.118(3.0) MIN.

15 0 MAX.

FUJITSU

Bipolar Memories
•

MB7127E/H, MB7128E/H/Y
High Speed Schottky TTL
8,192-Bit PROM

Description
The Fujitsu MB7127/MB7128 are high speed Schottky TTL electrically field programmable read only memories. With open collector
outputs on the MB7127 and three-state outputs on the MB7128,
memory expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable
DEApTM (Diffused Eutectic Aluminum Process) during a simple
programming procedure.
The sophisticated passive isolation termed lOP (Isolation by Oxide
and Poly-silicon) with thin epitaxial layer and Schottky TTL process
permits minimal chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuits in
order to perform AC, DC and programming test prior to shipment.
This results in extremely high programmabily.

Feature.
• Organization: 2,048 x 4-blts
• TTL compatible input/output

ill Fest eccess time, 30 ns typ_

•
•
•

•

MB7127/MB7128E:
55 ns max.
MB7127/MB7128H:
45 ns max.
MB7128Y: 35 ns max.
Low power dissipation:
155 mA max.
Single +5V supply voltage
Proven high programmabilIty and reI/ability of DEApTM
(Diffused Eutectic Aluminum Process) PROM
Chip enable leads for simple memory expansion

• Simplified, low power
programming
• Low current PNP inputs
• 3-stata outputs on MB7128
• Open collector outputs on
MB7127
• Standard 18-pln DIP
package
• MB7128 pin compatible with
Industry standard products,
82S185, HM7685, 63S841
• MB7127 pin compatible with
82S184, HM7684, 63S840,
27S184

This device contains circuitry to

protect the inputs against damage
due to high static voltages or electric fields. However, It is adVised

that normal precautions be taken to
avoid applications of any voltage
higher than maximum rated voltages to this high impedance circuit.

10-70

MB7127E/H
MB7128E/H/Y

MB7127/MB7128 Block Diagram
and Pin Assignment
Vee
A7

8192·BIT
MEMORY CELLS
A,

ADDRESS
BUFFERS

A,

A,.
GNO ---.. _ _ _ _ _...J

f

-ell) ""fIJ

~ ~ >8 I~.t'

14 I 3. 2 11 128127126_

...... _.-!. ... !' ............ .

.

-

Nt 5

~2: As

I

:2!

A. ~!

CHIP

As 7_!

ENABLE

Ao

'!.;

Absolute Maximum Ratings
(See Note)

At

~2~

Ne

'23 Nt

(TOP VI£W)

At ~!
Az ~O;
A'0 111

03

.-

~2: Nt

~2J 0,
~1! O2

Rating

Symbol

Value

Unit

Power supply voltage

Vee

-0.5 to +7.0

V
V

Power supply voltage (during programming)

Vee

-0.5 to +7.5

Input voltage

VIN

-1.5to +5.5

V

Input voltage (during programming)

VIPRG

22.5

V

Output voltage (during programming)

VOPRG

-0.5 to +22.5

V

Input current

liN

-20

mA

Input current (during programming)

IIPRG

+270

mA

Output current

lOUT

+100

mA

Output current (during programming)

IOPRG

+150

mA

Storage temperature

TSTG

-65 to +150

'C

Output voltage

VOUT

-0.5 to +Vee

V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU

10-71

MB7127E/H
MB7128E/H/Y

Recommended Operating
Conditions

Capacitance
(! = 1 MHz, Vee = +5V,
VIN = +2V, TA = 25'C)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.75

5.0

5.25

V

Input low voltage

Vil

0.0

0.8

V

Input high voltage

VIH

2.0

Vee

V

Ambient temperature

TA

0

75

'C

Parameter

Symbol

Max

Unit

Input capacitance

CI

Min

Typ

10

pF

Output capacitance

Co

15

pF

DC Characteristics
(Full guaranteed operating
ranges unless otherwise noted.)

Parameter

Symbol

Input leakage current
(VIH = 5.5V)
Input load current
(Vll = 0.45V)

Min

Typ

Max

Unit

IR

40

/LA

IF

-250

/LA

Output low voltage
(lOl = 10 mAl

VOL

0.45

V

Output low voltage
(lOl = 16 mAl

VOL

0.50

V

Output leakage current
(V0 = 2.4V, chip disabled)

MB7127

10lK

40

/LA

Output leakage current
(Vo = 2.4V, chip disabled)

MB7128

10lH

40

/LA

Output leakage current
(V0 = 0.45V, chip
disabled)

MB7128

lOll

-40

/LA

Input clamp voltage
(liN = -18 mAl

VIC

-1.2

V

Power supply current
(VIN = OPEN or GND)

lee

155

mA

110

Output high voltage
(10 = -2.4 mAl

MB7128

V OH '1

2.4

Output short circuit current
(Vo = GND)

MB7128

los'1

-15

V
-60

mA

Note:: *1 Denotes guaranteed characteristics of the output high-level (ON) state wh~n the chip is enabled (VCE "" O.4V) and the programmed
bit is addressed. These characteristics cannot be tested prior to programming. but are guaranteed by factory testing.

AC Characteristics
(Full guaranteed operating
ranges unless otherwise noted.)

MB7127H
MB7128H
Typ
Max

Typ

Max

Unit

30

26

35

ns

Parameter

Symbol

MB7127E/
MB7128E
Typ
Max

Access time (via address input)

tM

30

Output disable time

t DiS

40

30

25

ns

Output enable time

tEN

40

30

25

ns

10,72

55

45

MB7128Y

MB7127E/H
MB7128E/H/Y

Operation Timing Diagram

,-------------- V,H

ADDRESS
INPUT

\/ '.5V
\I,.5v
_______-J/I\'--______--.J/ '---_________

V,L

,----+----------+--------------

V,H

CHIP
ENABLE
INPUT

-------~, I;~~OUTPUT

CHIP

ENABLE
INPUT

__________ J

l'.5V

_~f'.5V
----

OUTPUT

-=

'-----+----------+-------------- V,L

'f.-"'-----VOH
'.5V_ _ _ _ _ _ _ _ _

~

'¥~1.5V- - V ' H
II\~------------

~'DlS~

____________

VOL +0.5V

___________ VOL

AC Test Conditions
--op---Vcc

Input Conditions
Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to 3V
Rise and Fall Time ........................... 5 ns from 1V to 2V
Frequency ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 MHz

10-73

V,L

'EN

1.5V

NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS DISABLED. OUTPUT ENABLE TIME
IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN THE CHIP ENA~
BlE IS ENABLED. THE HIGH RESISTANCE STATE IS DEFINED AS A POINT ON THE
OUTPUT WAVEFORM EQUAL TO A:::'V OF O.5V FROM THE ACTIVE OUTPUT LEVEL.

FUJITSU

~

MB7127E1H
MB7128I!/H/Y

Typical Characterlatlca
Curves

ION Output High Current
va. VON Output High Voltage

liN Input Currant
va.V IN Input VOltage

TA = 25"C

TA = 25°C
~.

_f-:: ~

.;!.

S~

-10

~ ~ [\..

~vee=4.5V

a~

Vee

0

~U

-10

~~ ~
V
~Vec=
~

II!
G -20

Vee = S.OV

lUi.

il...

i

.-

~

!I!!!i
-u

1

= S.SV I--

-20

"

r:
i

Vee =

1.0

-60

2.0

o

V"", OUTPUT HIGH VOLTAGE (Y)

V'N, INPUT VOLTAGE (Y)

10L Output Low Current
VOL Output Low Voltage

10L Output Low Current
VOL Output Low Voltage

VS.

VS.

70

~. = 25~C

J

-Vee= 5.0V

~A = 25~C
~Vee=

/

/

5.OV

/

J

V

J

/
MB7127

/
200

400

V

L

/
o

I--

MB7128

MB7127/MB1128

-1.0

o

t---

.LIIO

G -30

70

sr-

Vee=4.5VS.OV

600

VOL, OUTPUT LOW VOLTAGE (mY)

10-74

o

o

V

rB712j'

/
200

400

600

VOL, OUTPUT LOW VOLTAGE (mY)

MB7127E/H
MB7128E/H/Y

Typical Characteristics
Curves
(Continued)

tAA Access Time
Ambient Temperature

tAA Access Time
Ambient Temperature

VS.

VS.

70

70

60

!w

50

1=

40

!!l

30

::&

!lc
j

-

60

~CC=4.~V
L

V/./

Vcc=6.0Y

~

Vvcc';s.sv

~ F"""

!w

50

1=

40

~

30

j

20

::&

I

Vcc=4.5V

/
f-- V./

V./v~c=s.o~
/vcc=s.sv

20

10

10

rB71~

MB7127

o

-50

o

100

50

-50

tD,s Disable Time
VS. Ambient Temperature

tDS Disable Time
VS. Ambient Temperature

70

70

MB712~

MB7127
60

60
50

1=
w

40

::&

...

m

:liIS

0\

.9

30

vcc=s.S\,\

\

10

-50

r--

~CC=4.~V-

VCp=5.0V~· \

20

o

100

50

TA. AMBIENT TEMPERATURE ('C)

TA. AMBIENT TEMPERATURE ('C)

Iw

I:::::::::

c

1\

~

!w

50

1=

40

c

30

::&

...mw
~

j

20

100

50

FUJITSU

10-75

-50

~\\

~ \~

10

o

TA. AMBIENT TEMPERATURE ('C)

V'1C=4.5~\
Ycc=5.0V

Vcc-5.5V

~

50

100

TA. AMBIENT TEMPERATURE ('C)

MB7127E/H
MB7128E/H/Y

Typical Characteristics
Curves
(Continued)

tEN Enable Time
vs. Ambient Temperature

..
.s.
w
:&

1=
w

70

70

60

60

50

/VCC=4.5V

/

~
w

;

30
20

50

1=

40

....w

~/cr5.0V

ID

~
w

l/Vcc =S.5V

:::- ~ /

!w
:&

40

....

ID

tEN Enable Time
vs. Ambient Temperature

i

i!J

10

o

50

.........
20

-

10

r

1

B712

-50

30

70

~B712i

40

:&

5w

20

Iw
ADO. to tAA DELAY
\

1=

..--~

10

o

100

)

.....-

-

,... ,...

A1\'O 'EN DELAY-

\

0

o

100

~B712~

60

50

30

50

Delay Time Increase
vs. C L Load Capacitance

en

";:;w

MBr128

o

60

illII:

-

/Vcc = 5.5V

TA. AMBIENT TEMPERATURE (·C)

Delay Time Increase
vs. C L Load Capacitance

!w

/~~~:::~~ -

-50

100

TA. AMBIENT TEMPERATURE eC)

70

0

-

300

200

CL. LOAD CAPACITANCE (pF)

10-76

50

~
II:

40

:&

30

5w

20

";:;w

ADD. to tAA DELAY
ADD. to tEN DELAY

1=

\

0

10

o

o

100

\

.'>.

-

f-:::

200

CL. LOAD CAPACITANCE (pF)

300

-

MB7127E/H
MB7128E/H/Y

MB7127/MB7128 Bit Map
0

o

0

0

I

0,

1 1 1 0
0 o 0 0

I

02

1 1 1 0
0 o 0 0

I

03
1 1
0 0

1

o.
1 1
A7 0
A6 0
A5 0
A4 1

AS Ag A2 A10

1 0

0
0
1
0
1
1
1

-

A, 0
Ao 0
A3 0

1 0
0 0

000 0
o 1
1

o
Multiplexer

1

1 0

0

1 1 0

o

1 1 1

o

1 0
1
1 0

o

1 0
1 0
1 0
1 0 0
1 0 1

1 1 1

Decoderl Driver
A7 01100110 01100110
As 00111100 11000011
A5

00001111

00001111

1 1 0

01100110 01100110 01100110 01100110 01100110 01100110
11000011 00111100 11000011 00111100 00111100 11000011
00001111 00001111 00001111 00001111 00001111 00001111
11111111 00000000
00000000 00000000
11111111 11111111

11111111
11111111
11111111

00000000
11111111
11111111

00000000 00000000

00000000

00000000

01100110 01100110 01100110

01100110
00111100

A,

00000000 11111111 00000000
00000000 11111111 11111111
00000000 00000000 00000000
00000000 00000000 00000000

A7

Ao

01100110 01100110 01100110 01100110
11 0000 11 00111100 00111100 11000011
00001111 00001111 00001111 00001111
11111111 00000000 11111111 00000000
00000000 00000000 11111111 11111111
00000000 00000000 00000000 00000000

00111100 11000011 11 0000 11
00001111 00001111 00001111
11111111 00000000 11111111
00000000 00000000 11111111
11111111 11111111 11111111

A3

11111111

11111111

11111111
A, 00000000
Ao 00000000
A3 00000000

As
A5
A,
A,

11111111

11111111

FUJITSU

10-77

11111111

11111111

11111111

00001111
00000000
11111111
11111111
11111111

MB7i27E/H
MB7i2SE/H/Y

Package Dimensions
Dimensions in inches
(millimeters)

is· Lead Ceramic (CERDIPI Dual In·Line Package
(Case No.: DIP.iSC.COil

"~{~~~~~~~]j~
I

.

I

~~~~~~~~

.882(22.40)
.912(23.16)

~

"I

is·Lead Plastic Dual In· Line Package
(Case No.: DIP.iSP.M021

--r->===,==-==1'--;-1,soMAX

P t

INDEX-1

~~~

INDEX-2

A~;=r=;=;=:;=:::;=:::;=::;=::;=:::;::::;::::;:::;=;=;;::;:~J

.240(6.10)

.260(6.60)

~

~____________~.~85~0(~2~'.~60~)________
.876(22.25)

.~
.100(2.54)
TYP

I

•

II

I

~~:::
~~
.059(1.50)

JL----t-J

r~ ~

~

.023(0.59)

10-78

.200(0.51)

MIN

.290(7.37}
.310(7.87}

MB7127E/H
MB7128E/H/Y

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

28·Pad Ceramic (Metal Seal) Leadless Chip Carrier
(Case No.: LCC.28C·A01)

'PIN 1 INDEX

I

.085(2.16)TVP

n

C.Ol5(O.38)TYP
.445(11.30)
.460(11.68)

.05O(1.27)TVP

.300(7.62)TYP

10·79

FUJITSU

Bipolar Memories
•

MB7128E·W
High Speed Schottky TTL
8,192-Bit PROM

Description
The Fujitsu MB712BE-W is a high speed Schottky TTL electrically
field programmable read only memory. With three-state outputs on
the MB712BE-W, memory expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
logic level "ones" can be programmed by the highly reliable
DEAPTM (Diffused Eutectic Aluminum Process) during a simple
programming procedure.
The sophisticated passive isolation termed lOP (Isolation by Oxide
and Poly-silicon) with thin epitaxial layer and Schottky TTL process
permits minimal chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuits in
order to perform AC, DC and programming test prior to shipment.
This results in extremely high programmability.

Features
•
•
•
•
•
•

Extended temperature
ranges:
- 55°C to + 125°C
Organization: 2,048 words x
4-blts
TTL compatible Input/output
Fast access time:
55 ns max.
30 ns typo
Single +5V supply voltage
Proven high programmabilIty and reliability of DEApTM
(Diffused Eutectic Aluminum Process) PROM

• Simplified, low power
programmlng_
• Low current PNP Inputs
• MB7128E-W: Three-state
outputs
• Chip enable Inputs for easy
memory expansion
• Standard 18-pln DIP
package
• Also available In 28-pad
LCC

This device contains circuitry to

protect the inputs against damage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to
avoid applications of any voltage
higher than maximum rated volt-

ages to this high impedance circuit.

10-80

MB7128E·W

MB7128E·W Block Diagram
and Pin Assignment
Ao

Vee

A,

A,
As

A,

A,

8192·BIT
MEMORY CELLS

A,

Q,
Q,

ADDRESS
BUFFERS

Q,
Q,

GND -..._ _ _ _ _...r- EIPVEI

A,

A10

CHIP
ENABLE

Q,

Absolute Maximum Ratings
(See Note)

Q,

Q,

Q,

Rating

Symbol

Value

Power supply voltage

VCC

-0.5 to +7.0

v

-0.5 to +7.5

v

Power supply voltage (during programming)

Unit

Input voltage

-1.5 to 5.5

v

Input voltage (during programming)

22.5

v

-0.5 to +22.5

v

Output voltage (during programming)

VOPRG

Input current

-20

mA

Input current (during programming)

+270

mA

Output current

+100

mA

Output current (during programming)

+150

mA

Storage temperature

-65 to +150

°C

Output voltage

-0.5 to +VCC

v

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU

10-81

MB7128E·W

Recommended Operating
Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vcc

4.50

5.0

5.50

V

Input low voltage

VIL

0.0

0.8

V

Input high voltage

VIH

2.0

Vcc

V

Ambient temperature

TA

-55

+125

·C

Capacitance

(I = 1 MHz, Vcc = +5V,
V IN

=

+2V, TA

= 25·C)

Parameter

Symbol

Max

Unit

Input capacitance

CI

Min

Typ

10

pF

Output capacitance

Co

15

pF

DC Characteristics
(Full guaranteed operating
ranges unless otherwise noted.)

Parameter

Symbol

Max

Unit

Input leakage current
(VIH = 5.5)

IR

40

/LA

Input load current
(VIL = 0.45V)

IF

-250

/LA

Output low voltage
(lOL = 16 rnA)

VOL

0.50

V

Output leakage current
(Vo = 2.4V, chip disabled)

10lH

40

/LA

Output leakage current
(Vo = 0.45V, chip
disabled)

lOlL

-40

/LA

Input clamp voltage
(lin = -18 rnA)

VIC

-1.2

V

Power supply current
(VIN = OPEN or GND)

Icc

155

rnA

Output high voltage
(10 = -2.4 rnA)

VOH "l

2.4

Output short circuit current
(Vo = GND)

10S"1

-15

Min

Typ

110

V
-60

rnA

Note: "'1 Denotes guaranteed characteristics of the output high-level (ON) state when the chip ;s enabled (VeE = O.4V) and the programmed
bit is addressed. These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Full guaranteed operating
ranges unless otherwise noted.)

Parameter

Symbol

Typ

Max

Unit

Address access time

tAA

30

55

ns

Output disable time

t OIS

40

ns

Output enable time

tEN

40

ns

10-82

M87128E·W

Operation Timing Diagram

\ 1'.5V

\V'5V

ADDRESS
INPUT

/1\.

CHIP
ENABLE
INPUT

-

/

t------f.
'AA

1.~

OUTPUT

1.~

_ _ _ _ _ _ _ _ _ _ --'

E
CHIP
ENABLE
INPUT

'.

'AA

' - - _ _ _ _ _ _ _ • VOL

~----------- VI"

---------~

1.SV

E-------.......I

-

OUTPUT

'------------VIL

'EN

0 _ _ _ _ _ _ _ _ _ _/
' - - - - - - - - - - - - VOL

NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS DISABLED. OUTPUT ENABLE TIME
IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN THE CHIP
ENABLE IS ENABLED. THE HIGH RESISTANCE STATE IS DEFINED AS A POINT ON
THE OUTPUT WAVEFORM EQUAL TO A.J.Y OF O.5V FROM THE ACTIVE OUTPUT

lEVEL.

AC Test Conditions
Input Conditions

--,--Vcc

Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to 3V
Rise and Fall Time ........................... 5 ns from 1V to 2V
Frequency ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 MHz

I

MB7128E·W

300ll

I

soo!!

I

30pF

I

FUJITSU

10·83

MB7128E·W

Input/Output Circuit
Information

Input

MB7128E·W Input Circuit

In the input circuit, Schottky TIL
circuit technology is used to
achieve high-speed operation. A
PNP transistor in the first stage
of the input circuit improves input
high/low current characteristics.
Also, the input circuit includes a
protection diode for reliable
operation.

---1r---~------t

Three-State Output
A "three-state" output is a logic
element which has three distinct
output states of lOW, HIGH, and
OFF (wherein OFF represents a
high impedance condition which
can neither sink nor source current at a definable logic level).
Effectively, then, the device has
all the desirable features of a
totem-pole TIL output (e.g.,
greater noise immunity, good rise
time, line drive capacity), plus the
ability to connect to busorganized systems.

MB7128E·W Output Circuit

In the case where two devices
are on at the same time, the possibility exists that they may be in
opposite low impedance states
simultaneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While
physical damage under these
conditions is unlikely, system
noise problems could resuR.
Therefore, the system designer
should consider these factors to
ensure that this condition does
not exist.
Also in the output circuit,
Schottky TIL circuit technology is
used to achieve high-speed operation. Also, a PNP transistor is
provided in the output circuit to
decrease load on the Chip Enable circuit.

10-84 '

OUTPUT

MB7128E·W

Typical Characteristics
Curves

I'NA Input Current
vs. V ,N Input Voltage

TA

0

I'NC Input Current
vs. V ,N Input Voltage

= 25°C

TA

-~-

I--: ~

I--: ~
I-~

~

= 25°C

;:::~ R:-

0

~vee=4.sv

Vee = 5.OV
Vee = 5.5V

i-'"

~vee=4.sv
Vee = S.OV

-

Vee

~

= 5.5V

0

-30
-1.0

-30
-1.0

2.0

1.0

2.0

1.0
V,N. INPUT VOLTAGE (V)

V,N. INPUT VOLTAGE (V)

10H Output High Current
vs. V OH Output High Voltage

10L Output Low Current
VOL Output Low Voltage

VB.

70

iA = 25\C

C

60

/

f- Vee = S.OV

/

oS

..Ii:

50

il

40

/

II:
II:

~

..

30

~

20

0

..t

I

~

I!:

0

~

I

10

o

/
o

200

TA = 25°C

i

..

!z

~ l/I

-10

II:
II:

a

LI

:E:

!2
:E:

V

/'

-20

!:i

~
o

~ r5< K

~ /"
-30

~~cc=

4.SV- -

~Vcc=5.0V

Vee = S.SV-

-40

11_50

LI

-60
400

600

VOL. OUTPUT LOW VOLTAGE (mV)

FUJITSU

10·85

o
VOH. OUTPUT HIGH VOLTAGE (V)

-

MB7128E·W

Typical Characteristics
Curves
(Continued)

tAA Access Time
vs. T A Ambient Temperature

t DIS Disable Time
vs. T A Ambient Temperature
70

70

60

!

50

!II
'"

~
j

..

VJ=4.5V

40
30

-

/
V/

S-

//vee=5.0V
I

60

50

UI

I

:IE

/ VCC=S.5V

~

...'w"

40

c

30

OJ

~

j

20

Vqc=4.5~\

Vcc=S.OV

Ycc- 5.5V

20

'\.... \\

10

10

o

-50

50

~

o

-50

100

tEN Enable Time
vs. T A Ambient Temperature

70

60

60

...'w"

40

cz

30

~

20

OJ

100

Delay Time Increase
vs. C L Load Capacitance

70

50

:Ii

50

T A. AMBIENT TEMPERATURE ('C)

TA. AMBIENT TEMPERATURE ('C)

!w

~\\

!w

50

Ul

w

~

II:

r---...
....

~

U

v Vee
= 4.5V
Vee = 5.0V

w

:IE

/Vcc = 5.5V

5'w"

30

ADD. to tA,A DEL~Y

ADD. to tEN DELAY

20

~~

Q

10

o
-so

40

i!!

10

50

100

TA. AMBIENT TEMPERATURE ('C)

10·86

o

o

100

200

CL. LOAD CAPACITANCE (pF)

300

MB7128E·W

Package Dimensions
Dimensions in inches
(millimeters)

18·Lead Ceramic (CERDIP) Dual In·Line Package
(Case No.: DIP.18C.C01)

~
wwwm
.~,~ LJLU'~'"

1'200(5,08)MAX
.120(3.05)

.110(2.79)

:~~g~~:~~~

TYP

.800(20.32)REF

.013(0.33)
.023(0.58)

O,mtlnsions in
inches (millimeters)

28·Pad Ceramic (Metal Seal) Leadless Chip Carrier
(Case No.: LCC·28C·A01)

*PIN 1 INDEX

j

/

n

,085(2,16)TYP
,050(1.27)TYP

LJ
t

.445(11.30)
.460(11.68)

I

L

,445(11,30)
.460(11.68)

J

I

'SHAPE OF PIN 1 INDEX, SUBJECT TO CHANGE WITHOUT NOTICE

10-87

.050(1.27)TYP

FUJITSU

Bipolar Memories
•

MB7131E/H, MB7132E/H/Y, MB7131E.SK/H.SK,
MB7132E·SK/H·SK/Y·SK
Programmable Schottky
8,192-Bit Read Only Memory

Description
The Fujitsu MB7131 and MB7132 are high speed Schottky TTL
electrically field programmable read only memories organized as
1024 words by 8-bits. With uncommitted collector outputs provided
on the MB7131 and three-state outputs on the MB7132, memory
expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable DEAP
(Diffused Eutectic Aluminum Process) according to simple programming procedures.
The sophisticated passive isolation termed lOP (Isolation by Oxide
and Poly-silicon) with thin epitaxial layer and Schottky TTL process
permits minimal chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuits in order to perform AC, DC and programming test prior to shipment.
This results in extremely high programmability.

Features
•
•
•
•
•
•
•

Single +5V supply voltage
1024 words x B-blts organization, fully decoded
Proven high programmability and reliability
Programming by DEAP
(Diffused Eutectic
Aluminum Process)
Simplified and lower power
programming
Low current PNP inputs
AC characteristics guaranteed over full operating voltage and temperature range
via unique testing
techniques

• Fast access time, 30 ns typ
Y: 35 ns max. (MB7132)
H: 45 ns max.
E: 55 ns max.
• TTL compatible inputs
and outputs
• Open collector outputs
(MB7131)
• 3 state outputs (MB7132)
• Four chip enable leads for simplified memory expansion
• 300/600 mil 24-pin DIP package
• JEDEC approved pin out

This device contains circuitry to
protect the inputs against damage
due to high static voltages or elec-

tric fietds. However, it is advised
thai normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

10-88

MB7131E/H
MB7132E/H/Y
MB7131E·SK/H·SK
MB7132E.SK/H.SK/Y·SK

MB7131/7132 Block Diagram
and Pin Assignments
A7

Vee
(PVee)

Ao

A,
A.

A,

8192(128x84) BIT
MEMORY CELl.S

,..

Eo
E,
(pvE)
Eo

A3
A,
A,

E,

A.

O.

0,

Or

0,

0,

03

0,

GNO

O.

E,(PVE)

Eo \

E3 E,

NC

JOoOr
[1~ De
~1! 05

,1804

~15 Ne
~4 GND

[1~ ~
l1~ 02

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Power supply voltage

Vee

-0.5 to +7.0

V

Power supply voltage
(during programming)

Vee

-0.5 to +7.5

V

Input voltage

VIN

-1.5 to 5.5

V

Input voltage (during programming)

VPRG

22.5

V

Output voltage (during programming)

VPRG

-0.5 to +22.5

V

Input current

liN

-20

mA

Input current (during programming)

IpRG

+270

mA

Ouput current

lOUT

+100

mA

Output current (during programming)

IpRG

+150

mA

Storage temperature

Tsm

-65 to +150

·C

Output voltage

VOUT

-0.5 to Vee

V

Note: Pennanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU

10-89

MB7131E/H
MB713ZE/H/Y
MB7131E·SK/H·SK
MB713ZE·SK/H·SK/Y·SK

Guaranteed Operating
Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.75

5.0

5.25

V

Input low voltage

Vil

0

0.8

V

Input high voltage

VIH

2.0

5.5

V

Ambient temperature

TA

0

75

°C

Capacitance
(f = 1 MHz, Vee = +5V,
VIN = +2V, TA = 25°C)

Parameter

Symbol

Max

Unit

Input capacitance

CI

10

pF

Output capacitance

Co

15

pF

Min

Typ

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Typ

Min

Max

Unit

Input leakage current
(VIH = 5.5V)

40

Input load current
(Vll = 0.45V)

-250

/LA

Output low voltage
(IOL = 10mA)

0.45

V

Output low voltage
(Iol = 16 mAl

0.50

V

Output leakage current
(Va = 2.4V, chip disabled)

MB7131

40

/LA

Output leakage current
(Va = 2.4V, chip disabled)

MB7132

40

/LA

Output leakage current
(Va = 0.5V, chip disabled)

MB7132

-40

/LA

-1.2

V

175

mA

Input clamp voltage
(liN = -'18 mAl
Power supply current
(VIN = OPEN or GND)

125

Icc

Output high voltage
(10 = -2.4 mAl

MB7132

Output short circuit current
(Va = GND)

MB7132

V

2.4
-15

los'1

-60

mA

Note: *1 Denotes guaranteed characterIstics of the output high-level (ON) state when the chip is enabled (VICE = O.4V, VICE = 2.4V) and
the programmed bit is addressed. These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

E
Typ

Max

H
Typ

Max

MB713ZY/·SK
Typ
Max

Unit

Access time (via address input)

tM

30

55

30

45

26

35

ns

Output disable time

t OIS

40

30

25

ns

Output enable time

tEN

40

30

25

ns

10·90

MB7131E/H
MB7132E/H/Y
MB7131 E·SK/H.SK
MB7132E-SK/H·SK/Y·SK

Operation Timing Diagram

\ / r - - - - - - - - - - - VIH

\I

ADDRESS
INPUT

/\1.5V_ _ _ _ _ _ _ _ _ __ J/\1.5V
_ _ _ _ _ _ _ _- J
~

,--------t-------------------t----------------------------VIH

CHIP
ENABLE
INPUT

E _ _ _ _oJ

OUTPUT

Q

'-------+-------------------+--------------------------- VIL

--------fr~~--=,f.'AA
1.5V

---------------~
CHIP
ENABLE
INPUT

E--------~

VOH

1.5V

~-----------~
, - - - - - - - - - - - - - - - - - - - - - - - - - VIH

1.SV

E--------J

' - - - - - - - - - - - - - - - - - VIL
lEN

OUTPUT
~------------------VOL

NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS TAKEN HIGH. OUTPUT ENABLE
TIME IS THE nME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN THE CHIP

ENABLE IS TAKEN LOW. THE HIGH RESISTANCE STATE IS DEFINED AS A POINT ON
THE OUTPUT WAVEFORM EQUAL TO A ;V OF O.5V FROM THE ACTIVE OUTPUT
LEVEL.

AC Test Conditions
Input Conditions

Amplitude. .. .. . . .. . .. . . .. . .. .. .. . . . .. . . .. .. . .. .. . .. . .. OV to 3V
Rise and Fall Time ........................... 5 ns from lV to 2V
Frequency .............................................. 1 MHz
TRUTH TABLE
MB7131/MB7132

I
I
I

Rl

R2

CL

'AA

300!1

30pF

lOIS

300!1

'EN

30011

soon
soon
soon

30pF
30pF

FUJITSU

10·91

---
and Polysilicon) with thin epitaxial layer and Schottky TTL process
permits minimal chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuits in
order to perform AC. DC and programming test prior to shipment.
This results in extremely high programmability.

Features

• Single +5V supply voltage
4096 words x 4-blts organization, fully decoded
• Provan high programmability and reliability
• Programming by DEAP (diffused eutectic aluminum
process)
• Simplified, low power
programming
• Low current PNP Inputs
• AC characteristics guaranteed over full operating voltage and temperature range
via unique testing
techniques
•

• Fast aceess time, 35 ns typ
MB7134Y: 35 ns max.
H: 45 ns max.
E: 55 ns max.
• TTL compatible Inputs and
outputs
• Open collector (MB7133)
• 3-state outputs (MB7134)
• Two chip enable inputs for
simplified memory expansion
• 300 mll20-pln
DIP package

This dfriice contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high Impedance circuit.

10-99

MB7133E/H
MB7134E/H/Y

MB7134 Block Diagram
and Pin Assignments

Vee

(PVecl

A7

Aa
Aa

a.
a,
a,
a,

A,

A,

A,.
E,

A"

GND

E,(PVe)

AS AgNCNCNCQoQ,

~{8 Q2
11703

~(6 A11

115 ~1

;14

GND

[{3 NC
~~2 E2

Aa AaNCNCNca.a,
A7 ~J
He 271

(PVeelVee
NC
Ne

~L,
1
21

'

-r-.J

TOP VIEW

As =3J
As

Absolute Maximum Ratings
(See Nole)

~J

~18

Q2

11

03

~1~ ~11
,15 E, (PVe)
GND

i14

[{3 Ne
~!.2 ~2

Rating

Symbol

Value

Unit

Power supply voltage

Vee

-0.510 +7.0

V

Power supply voltage
(during programming)

Vee

-0.510 +7.5

V

Input voltage

VIN

-1.5 to 5.5

V

Input voltage (during programming)

VpRG

22.5

V
V

Output voltage (during programming)

VpRG

-0.5 to +22.5

Input current

liN

-20

mA

Input current (during programming)

IpRG

+270

mA

Output current

lOUT

+100

mA

Output current (during programming)

IpRG

+150

mA

Storage temperature

TSTG

-65 to +150

'C

Output voltage

VOUT

-0.5 to Vee

V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU
10·100

MB7133E/H
MB7134E/H/Y

Guaranteed Operating
Conditions

Capacitance
(! = 1 MHz, Vcc = +5V, VIN =
+2V, TA = 25°C)

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Typ

Max

Supply voltage

Vcc

4.75

5.0

5.25

V

Input low voltage

Vil

0

0.8

V

Input high voltage

VIH

2.0

5.5

V

Ambient temperature

TA

0

75

°C

Min

Parameter

Symbol

Max

Unit

Input capacitance

CI

10

pF

Output capacitance

Co

15

pF

Parameter

Typ

Unit

Max

Unit

IR1

40

p,A

IF

-250

p,A

Output low voltage
(IOl = 10mA)

VOL

0.45

V

Output low voltage
(IOl = 16 rnA)

Val

0.50

V

Input leakage current
(VIH = 5.5V)
Input load current
(Vll = 0.45V)

Symbol

Min

Typ

MB7133

10lK

40

p,A

MB7134

10lH

40

p,A

MB7134

lOll

-40

p,A

Input clamp voltage
(liN = -18 rnA)

VIC

-1.2

V

Power supply current
(VIN = OPEN or GND)

Icc

170

rnA

Output leakage current
(Va = 2.4V, chip disabled)
Output leakage current
(Va = 0.45V, chip disabled)

120

Output high voltage
(10 = -2.4 rnA)

MB7134

VOH '1

2.4

Output short circuit current
(Va = GND)

MB7134

los'1

-15

V
-60

rnA

Note: *1 Denotes guaranteed characteristics of the output high-level (ON) state when the chip is enabled (VfE' = D.4V) and the programmed
bit is addressed. These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

MB7133/7134E
Typ
Max

MB7133/7134H
Typ
Max

MB7134Y
Typ
Max

Unit

Access time (via
address input)

tM

Output disable time

tolS

40

40

30

ns

Output enable time

tEN

40

40

30

ns

35

10-101

55

35

45

28

35

ns

MB7133E/H
MB7134E/H/Y

Operation Timing Diagram

CHIP
ENABLE
INPUT

\V. 5V

)K1.5V

ADORESS
INPUT

/1\ .

V,L

---f::r------'J0
lAA

OUTPUT

----------~

CHIP
ENABLE
INPUT

•. ~

lAA

VOH

'JV

~----------

1.5V

E--------------~

~-----------------------V~
lEN

OUTPUT

~---------------------V~
NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS DISABLED. OUTPUT ENABLE TIME
IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN THE CHIP
ENABLE IS ENABLED. THE HIGH RESISTANCE STATE IS DEFINED AS A POINT ON

THE OUTPUT WAVEFORM EQUAL TO A .lV OF O.SV FROM THE ACTIVE OUTPUT
LEVEL.

AC Test Conditions
Input Conditions
Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to 3V
Rise and Fall Time ........................... 5 ns from 1V to 2V
Frequency .............................................. 1 MHz
TRUTH TABLE
MB7'33/MB7134

l
l
l

'AA

R.

R2

CL

300n

8000

3DpF

'DIS

3000

eoon

30pF

'EN

3000

8000

3DpF

FUJITSU

10-102

---,.....--Vcc

MB7133E/H
MB7134E/H/Y

Input/Output Circuit
Information

Input
In the input circuit, Schottky TTL
circuit technology is used to
achieve high-speed operation. A
PNP transistor in the first stage
of the input circuit remarkably improves input high/low current
characteristics. Also, the input
circuit includes a protection diode
for reliable operation.

physical damage under these
conditions is unlikely, system
noise problems could result.
Therefore, the systems designer
should consider these factors to
ensure that this condition does
not exist.

In the output circuit, Schottky
TTL circuit technology is used to
achieve high-speed operation.
Also, a PNP transistor provided
in the output circuit is effective to
decrease a load for the Chip
Enable circuit.

MB7133/MB7134 Input

Open Collector Output
The open-collector output is ollen
utilized in high speed applications
where power dissipation must be
minimized. When the device is
switched, there is no current
sourced from the supply rail.
Consequently, the current spike
normally associated with TTL
totem-pole outputs is eliminated.
In high frequency applications,
this minimizes noise problems
(false triggering) as well as
power drain. For example, the
transient current (low impedance
high-level to low impedance lowlevel) is typically 30 mA for the
MB7134 (3-state) compared to 0
mA for the MB7133 (open
collector).

INPUT

o-.....-I~---1I(1.-......-t"

MB7133 Output

OUTPUT

Three-State Output
A "three-state" output is a logic
element which has three distinct
output states of ZERO, ONE and
OFF (wherein OFF represents a
high impedance condition which
can neither sink nor source current at a definable logic level).
Effectively, then, the device has
all the desirable features of a
totem-pole TTL output (e.g.,
greater noise immunity, good rise
time, line driving capacity), plus
the ability to connect to busorganized systems.

MB7134 Output

In the case where two devices
are on at the same time, the possibility exists that they may be in
opposite low impedance states
simultaneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While

10-103

OUTPUT

MB7133E/H
MB7134E/H/Y

Typical Characteristics
Curves

10L Output Low Current
VOL Output Low Voltage

liN Input Current
vs. V IN Input Voltage

VB.

70

i.

TA = 25°C

r:::::: - -

;(

~

:,

!zw

a:
a:

-10

--: ~

~~

::J

~

50

:>

40

0

r---

-20

9

30

50

20

~

~

/
/

10

1.0

o

2.0

./V
o

i.

=

25~C

t-

z

50
40

w

u

~

30

I!::::>

20

5
0

:§

/
I

V

o

o

200

w
a:
a:

-10

~V

l:

5
~
o

-30

:::--.Vee = 4.5V-

r--

S.OV

Vee = 5.5V- r---

-40

]-50
MB7134

MB7134
-60

400

{

~ r5< ~
V
~~cc=
~

G -20 / '
:z:

/

V

1IE
!2

/

10

600

TA = 25°C

Vee = 5.0V

So
II:
II:
::J

MB7133
400

10H Output High Current
VS. V OH Output High Voltage

10L Output Low Current
VOL Output Low Voltage

VS.

60 -

200

VOL, OUTPUT LOW VOLTAGE (mV)

V,N. INPUT VOLTAGE (V)

;(

/
J
V

MB~33/~

-30
-1.0

70

~·C

~

= S.OV
Vee = rosv

Vee

0
t-

!zw

=

t-- Vee = 5.0V

a:
a:

i\S'vee = 4.5V

::J

";;;

1

~

110

600

VOl, OUTPUT LOW VOLTAGE (mV)

FUJITSU

10-104

o
VQH, OUTPUT HIGH VOLTAGE (V)

MB7133E/H
MB7134E/H/Y

Typical Characteristics
Curves
(Continued)

tAA Access Time
vs. Ambient Temperature

tAA Access Time
vs. Ambient Temperature
70

70

60

60
/

50

I
:&
"'
1=

40

il

30

~
j

i--

Iw

50

1=

40

:&

~ ~Vee=4.5V

_

"' Vee = 4.0V
Vee = 5 5V

j

20

"'w

"'
"."
..
$

30

r-.... I-.....
t:-

~

V'

Vee = 4.SV
Vee
5.0~ _
Vee = 5.5V

=

20
10

10
MB7133

o

-50

MB7134

o

100

50

-50

talS Dlseble Time
vs. Ambient Temperature

lats DI. .ble Time
vs. Ambient Temperature
70

70

60

60

50

~

40

Iw

w

."'
~

CD

30

is

~

Vee = 4.5;
Vee = 4.0V
Vee

= S.SV

~
'"

20

~

-

~

~

~
«

"'

50
40
30

is

,;,

.9

20

VCC=4.5~~
Vee = S.OV ~
Vee

-

"'-

~

MBt33

o

= S.SV

10

10

-50

100

50

TA, AMBIENT TEMPERATURE (OC)

TA. AMBIENT TEMPERATURE ('C)

~

I--

50

100

TA. AMBIENT TEMPERATURE ('C)

10-105

MBI'34

o

-50

50

100

TA. AMBIENT TEMPERATURE ('C)

MB7133E/H
MB7134E/H/Y

Typical Characterlatlca
Curvea
(Continued)

tm. Enable Time
VB. Ambient Temperature

!w
"F
.,<~
zw

Z

j!}

taN Enable Time
va. Ambient Temperature

70

70

60

60

50

VJ.

40

Vee

'l~cc
Vee

30

!w

50

F

40

zw

30

"

= 4.5V
= 5.5Y

.,~
<

= 5.0V

-...;. './

ffi

20

10

V
~

Yee

= 4.5V

Vee = S.OV
Vee = 5.5V

P V

20
10

MBr33

o

-50

MBr34

o

100

50

-50

T •• AMBIENT TEMPERATURE ('C)

70

~

60

!w

50
ADD TO IA. DELAY \.

40

w
:II

30

j

20

ADD TO

I~

c

10

o

o

?

V
~
100

!a:

/

u

1/~
~

50
40

!

/

DEJIY

F

w

70

M8~33

60

!a:

100

T•• AMBIENT TEMPERATURE ("C)

Dalal' Time Increase
vs. C L Load Capacitance

Delay Time Increaae
vs. C L Load Capacitance

!w

50

30

j

20

F

-~
300

200

w
:II

Ct.. LOAD CAPACITANCE (pF)

FUJITSU

10·106

w

c

AiD TO jAA DEIAY,,-

1 IEj
o -~
o
AD

TO

DELA~

10

100

~
MB7I34

200

CL. LOAD CAPACITANCE (pF)

300

MB7133E/H
MB7134E/H/Y

Package Dimensions
Dimensions in inches
(millimeter)

20·Lead Ceramic ICERDIPI Dualln·Llne Package
ICa. . No •• DIP.20CoC031

~~l~~~:~~~:I'~
1.000(35.4)

28·Pad Ceramic IMetal Seall Leadless Chip Carrier
ICase No •• LCC·28C·A01)

~PlN

1 INDEX

I

n

R.OO8(O.20)TYP
(28PLCS)

.085(2.18)TYP

fl
J~TYP

C.Ol5(O.38)TYP
.445(11.30)
.480(11.88)

.05O(1.27)TYP

.300(7.82)TYP

10·107

·00001.27)TYP

M87133E/H
M87134E/H/Y

Package Dimensions
(Continued)"
Dimensions in inches
(millimeter)

280Ped Ceramic (Metal Seall Leadle. .Chlp Carrier
(Cese No.: LCCoaCoA021

'PIN 1 INDEX

!

r

n

R.OO8(O.20)TYP

.085(2.16)TYP

lapClS)

.445(11.30)

]~

.445(11.30)

.460(II.68)SO

t

C.OI5(O.38)TYP
.000(I.27)TYP

.300(7.62)TYP

10-108

FUJITSU

Bipolar Memories
•

MB7137E/H, MB7138E/H/Y,
MB7137E·SK/H·SK, MB7138E·SK/H·SK/Y·SK
Programmable Schottky
16,384-Bit Read Only Memory

Description
The Fujitsu MB7137 and MB7138 are high speed Schottky TTL
electrically field programmable read only memories organized as
2048 words by 8-bits. With uncommitted collector outputs provided
on the MB7137 and three-state outputs on the MB7138, memory
expansion is simple.

f- -

r- -

The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable DEAP
(Diffused Eutectic Aluminum Process) according to simple programming procedures.

II
V

r- The sophisticated passive isolation termed lOP (Isolation by Oxide
and Polysilicon) w~h thin epitaxial layer and Schottky TTL process
perm~s minimal chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuits in order to perform AC, DC and programming test prior to shipment.
This results in extremely high programmability.

f- f-

.:;;:a

v--ii'i11i ~N
~

f--

= j'5V

iI: -20

u
31:

::>

40

..SS

9

30

j

V

/

20

0

j

i

10

/

MB7137/38

-30
-1.0

1.0

o

2.0

o

200

jA =

g
!i:

IU

80

25~C

I

r- Vee = 5.OV

/

so

J
V

II:
II:

::>

u

40

......

30

~
....

/

::>
::>

20

~

10

0

o

./
o

200

V

600

TA = 25'C

1!i:
Il!

a

-20

~

:I:

~)

-10

-30

5~ -40
.Lso

/

./

600

VOL, OUTPUT LOW VOLTAGE (mY)

FUJITSU

10·114

I

~~ (

0 /'

MB~138

400

MB7137

400

10H Output High Current
vs V OH Output High Voltage

10L Output Low Current
VOL Output Low Voltage

V8

C-

J

VOL, OUTPUT LOW VOLTAGE (mY)

V'N, INPUT VOLTAGE (Y)

70

IL

SO

W

::>

u

J

II:
II:

~vee = 4.5V

II:
II:

2~'C

jA =
80 -Vee= 5.OV

0~ee= 4.5V-

-

Vee = 5.5V-

-

~~cc=5.0V

MB7138

-60

o
VOH, OUTPUT HIGH VOLTAGE (Y)

MB7137E/H
MB7138E/H/Y
MB7137E.SK/H.SK
MB7138E.SK/H.SK/Y.SK

Typical Characteristics
Curves
(Continued)

tAA Access Time
vs Ambient Temperature

tAA Access Time
vs Ambient Temperature

70

7D

60

60

!w

50

lw

50

1=

40

1=

40

:IE

.:::::I"--

UI

faCJ

..j

CJ

3D

:IE

~ ~ Vee = 4.SV

.t=

10

r- r--

UI

,---

~Vee= S.OV

20

VL4.L-

-

IS'SV

fa

~
j

«

/

20

o

100

50

-50

TA. AMBIENT TEMPERATURE (OC)

t DS Disable Time
vs Ambient Temperature

rB713~

1=
w

40

~

30

$

20

:E

....
15

7D
60
~

50

w
:IE
1=

40

oS

Vee

= 4.5V

Vee = S.ov
Vee = s.sv '\

.
.8j
r!I

~ ......,.:

10

30

VCC=5.5V ~
Vee = S.OV

Vee=4.SV ~

20

~

10
MBr3S

MB7i37

o

-50

100

t DlS Disable Time
vs Ambient Temperature

60

Iw

50

T A. AMBIENT TEMPERATURE rC)

70

50

.-

10
1

-50

= 5.0V

30

MB7137

o

Vee

/Vcc = S.SV

50

100

TA. AMBIENT TEMPERATURE (OC)

10-115

o

-50

50

100

TAo AMBIENT TEMPERATURE (0C)

MB7137E/H
MB7138E/H/Y
MB7137E·SK/H·SK
MB7138E.SK/H·SK/Y·SK

Typical Characteristics
Curves
(Continued)

tEN Enable Time
vs Ambient Temperature

Iw
:E

1=

.

tEN Access Time
vs Ambient Temperature

70

70

80

60

50
40

~ Vcc=5.0V

w

-'

~

30

j

20

w

/ Vee = 4.5V

/

I"--..

Iw

50

1=

40

m
u
u

30

j

20

:E

Vee = S.SV

~ I'..

c

10

-50

t::=::::: ~
MBI'38

o

-50

100

50

Delay Time Increase
vs C L Load Capacitance
70

70

MB7138

MB7137

60

80

Iw
~0:

U

!w

50
ADD TO 1M DELAY

I'\.

40

ADD TO tEN DELAY

!

w
:E
1=

30

~
c

20

100

50

TA. AMBIENT TEMPERATURE ("C)

TA. AMBIENT TEMPERATURE ("C)

Delay Time Increase
vs C L Load Capacitance

-

10

Mar137

o

~ Vcc=4.5V' /.. Vee = S.OV
Vc=S.SV

10

o ~
o

V
~~
100

~
I-""'"

./

./

40

w
:E

30

~

20

~
!

ADD TO ..... D~LAY- f---

1=

~~
300

200

50

~

CL. LOAD CAPACITANCE (pF)

FUJITSU

10·116

I!I

I

10

o

I

I--- f-ArTOrD~~

o

~
100

200

CL. LOAD CAPACITANCE (pF)

300

MB7137E/H
MB7138E/H/Y
MB7137E.SK/H.SK
MB7138E·SK/H·SK/Y·SK

Package Dimensions
Dimensions in inches
(millimeter)

24·Lead Ceramic ICERDIPI Dual In·Line Package
ICase No.: DIP.24C·C011

l

R.025(O.64)
REF

.514(13.06)
.541(13.75)

h--Tr-r-r-rr-1~~~
00000000000

1 ..

1.200(30.46)
1.300(33.02)

:=:~:~

u~

I

•

.014(0.36)

~

.230(5.64)MAX
.120(3.05)
.150(3.81)

.020(0.51)
.050(1.27)
.015(0.38)
.023(0.58)

24·Lead Ceramic ICERDIPI Dual In·Line Package I·SKI
ICase No.: DIP·24C·C041

n

R.025(O.64)
REF

""'9

.284(7.21)
.3OJ.67)

1.180(29.97)
1.230(31.24)

~
.020(0.51)
.050(1.27)

10·117

.6OO(15.24)REF

.230(5.84)MAX
.120(3.05)
.150(3.81)

MB7137E/H
MB7138E/H/Y
MB7137E·SK/H.SK
MB7138E·SK/H·SK/Y·SK

Package Dimensions
(Continued)
Dimensions In Inches
(millimeters)

24·Lead Plastic Dual In·Llne Package
eCase No.: DIP·24P.M01)

l

INDEX

.524(13.31)

.590(14.99)
.610(15.49)

or
J
1!,~'-

!'i=r=;==;=r=;=;==r=;==;=;=;=;==r=;==;=r=;=;==r=;==;=;=F!
1.171(29.74)
1.197(30.40)
.039(0.99)

.118(3.00)MIN

.020(0.51)MIN

28·Pad Ceramic (Metal Seal) Leadle.. Chip Carrl.r
(Case No.: LCC·28CoA02)

.08512.16ITYP

*PIN 1 INDEX

!

n

.445111.301
.460111.681

so

C.01510.38ITYP
.445111.301
.460111.681 so

.05011 .271 TYP

.30017.62ITYP

*Shape of Pin 1 index: Subject to change without notice

FUJITSU

10·118

MB7137E/H
MB7138E/H/Y
MB7137E.SK/H·SK
MB7138E·SK/H·SK/Y·SK

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

28·Pad Ceramic IMetal Seal) Leadless Chip Carrier
ICase No.: LCC·28C.A01)
.OBS{2.16)TYP

rl

;--PIN 1 INDEX

.445(11.30)

]~

.445(11.30)
A60(11.68)SQ

J

C.015(0.3B)TYP
.050(1.27)TYP

.300(7.62)TYP
·SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

24C·Lead Ceramic IMetal Seal) Flat Package
ICase No.: FPT·24C·A01)
.010(0.25)
MIN

f

INDEX AREA

.250(6.35)

1.~
.-i
D
'"

407(10.34)

I~'
--,-.260TY(7p.ll)

~~~:~:l J~~

~T·05Oyp(1.27)

k... -.II ~.015(0.3B)

.020(0.51)

.004(0.10)
.007(0.18)

....--.'>:.;:..;"'~ ;:i':..~"'\--~ ~

:~~:!::~

.588(14.94)
.612(15.55)

10·119

..

~--

FUJITSU

Bipolar Memories
•

MB7138E·W
High Speed Schottky
TTL 16,384-Bit PROM

Description
The Fujitsu MB7138E-W is a high speed Schottky TIL electrically
field programmable read only memory. With three-state outputs on
the MB7138E-W, memory expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable
DEAPTM (Diffused Eutectic Aluminum Process) during a simple
programming procedure.
The sophisticated passive isolation termed lOP (Isolation by Oxide
and Polysilicon) with thin epitaxial layer and Schottky TIL process
enables small chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuits in order to perform AC, DC, and programming tests prior to shipment.
This results in extremely high programmability.

•
•
•
•
•

•

Extended temperature
range:
-55° to +125°C
Organization:
2,048 words by B-bits
Fast access time:
55 ns max.
35 ns typo
TIL compatible input/output
AC characteristics are guaranteed over full operation
voltage and temperature
ranges via unique tasting
techniques
Proven high programmability and reliability of DEApTM
(Diffused Eutectic Aluminum Process)

•

Simplified, low power
programming
Low current PNP Inputs
MB7138E-W: three-state
outputs
• Three-chip enable leads for
easy memory expansion
• Standard 24-pin DIP
package
• Also available in 2B-pad LCC,
24-pin narrow dip, and 24-pin
flatpack
•
•

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields. However, It is advlsed
thai normal precautions be taken to
avoid applications of any voltage
higher than maximum rated voltages to this high impedance circuit.

10-120

MB7138E·W

MB7138E·W Block Diagram
and Pin Assignment

..r---------,

AD "-__

A,
A,

A,

As

A.

Vee
(PVcc)

As

As

11,.

A.

As

16,384·BIT
MEMORY CELLS

A,

A,

A,
A,

ADDRESS
BUFFERS

A,

A,a

E,
(PV E)

Au

A,

E,

Aa

00

0,

0,

As

0,

00

A9

0,

O.

A,o

GND

O.

Al1..,---...________....

E2

CHIP
ENABLE

E 3 y--'-______--I

O.

Absolute Maximum Ratings
(See note)

07 O. 05

O.

0, O2

0,

Rating

Symbol

Value

Unit

Power supply voltage

Vee

-0.5 to +7.0

V
V

Power supply voltage (during programming)

Vee

-0.5 to +7.5

Input voltage

VIN

-1.5 to +5.5

V

Input voltage (during programming)

VIPRG

22.5

V
V

Output voltage (during programming)

VOPRG

-0.5 to +22.5

Input current

lin

-20

mA

Input current (during programming)

IIPRG

+270

mA

Output current

lOUT

+100

mA

Output current (during programming)

IOPRG

+150

mA

Storage temperature

TSTG

-65 to +150

'C

Output voltage

VOUT

-0.5 to +Vee

V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU

10-121

MB7138E·W

Recommended Operating
Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vcc

4.50

5.0

5.50

V

Input low voltage

VIL

0.0

0.8

V

Input high voltage

VIH

2.0

Vcc

V

Ambient temperature

TA

-55

+125

°C

Capacitance

(I = 1 MHz, Vcc = +5V,
VIN

=

+2V, TA

= 25°C)

Parameter

Symbol

Max

Unit

Input capacitance

CI

10

pF

Output capacitance

Co

15

pF

Min

Typ

DC Characteristics
(Full guaranteed operating
ranges unless otherwise noted.)

Parameter

Symbol

Max

Unit

IR

40

/LA

= 0.45V)
= 16 mAl

=

Min

Typ

5.5V)

Input leakage current (VIH

IF

-250

/LA

Output low voltage (lOL

VOL

0.50

V

Output leakage current
(Va = 2.4V, chip disable)

10lH

40

/LA

Input load current (VIL

Output leakage current
(VOL = 0.45V, chip disabled)
Input clamp voltage (liN

=

Power supply current (VIN
Output high voltage (10

=

-18 mAl

=

OPEN or GND)

-2.4 mAl

Output short circuit current (Va

= GND)

lOlL

-40

/LA

VIC

-1.2

V

180

mA

130

Icc
V OH "

2.4

los"

-15

V
-60

mA

Note: *1 Denotes guaranteed characteristIcs of output high-level (ON) state when the chip is enabled and the programmed bit is addressed.
These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Full guaranteed operating
ranges unless otherwise noted.)

Parameter

Symbol

Typ

Max

Unit

Address access time

tAA

35

55

ns

Output disable time

tOlS

40

ns

Output enable time

tEN

40

ns

10-122

MB7138E·W

Operatl_ Timing Diagram
------------~\Vr-------------\I/~------------------VM
ADDRESS

/1\ 1.SV

INPUT

}I\ 1.SV

_ _ _ _ _ _ _.J

,--------1--------------------1----------------------------

CHIP
ENABLE
INPUT
E

'--------1--------------------1----------------------------

______-~~/~~--=\f.'AA
1.SV

OUTPUT

I.SV

----------~
CHIP
ENABLE
INPUT

E

VOH

VOH
VOL

~----------~
, - - - - - - - - - - - - - - - - - VOH

1.5V

E

' - - - - - - - - - - - - - - - - VOL
lEN

OUTPUT
' - - - - - - - - - - - - - - - - - - - - - - - VOL

NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A
HIGH RESISTANCE STATE WHEN THE CHIP ENABLE IS DISABLED. OUTPUT
ENABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE
WHEN THE CHIP ENABLE IS ENABLED. THE HIGH RESISTANCE STATE IS

DEFINED AS A POINT ON THE OUTPUT WAVEFORM EQUAL TO 'V OF O.SV
FROM THE ACTIVE OUTPUT LEVEL.

AC Test Conditions
Input Conditions

- -......-Vee

Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to 3V
Rise and Fall Time ........................... 5 ns from 1V to 2V
Frequency ............................................... 1 MHz

6000

30pF

FUJITSU

10-123

MB7138E·W

Input/Output Circuit
Information

MB7138E·W Input Circuit

Input
In the input circuit, Schottky TTL
circuit teChnology is used to
achieve high-speed operation. A
PNP transistor in the first stage
of the input circuit improves input
high/low current characteristics.
Also, the input circuit includes a
protection diode for reliable
operation.

.....o_____t

INPUT o----.-T---j(~r

Three-atate Output
A "three-state" output is a logic
element which has three distinct
output states of LOW, HIGH and
OFF (wherein OFF represents a
high impedance condition which
can neither sink nor source current at a definable logic level).
Effectively, then, the device has
all the desirable features of a totem-pole TTL output (e.g.,
greater noise immunity, good rise
time, line driving capacity), plus
the ability to connect to bus-organized systems.

MB7138E.W Output Circuit

In the case where two devices
are on at the same time, the possibility exists that they may be in
opposite low impedance states
simultaneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While
physical damage under these
conditions is unlikely, system
noise problems could result.
Therefore, the system designer
should consider these factors to
ensure that this condition does
not exist.
Also in the output circuit,
Schottky TTL circuit technology is
used to achieve high-speed operation. Also, a PNP transistor is
provided in the output circuit to
decrease the load on the Chip
Enable circuit.

10-124

---T----.-

vee

- { ) OUTPUT

MB7138E·W

Typical Characteristics
Curves

I'NA Input Current
vs. V ,N Input Voltage

I'NC Input Current
vs. V ,N Input Voltage

T. = 25"C

TA

-

-10

f..-:: .......
~

~~~
~

= 25°C

----=ts? -

~

~~~
~

0

~vee=4.5Y

Vee = S.OV
Vee S.SV

Vee = 4.5V
Vee = 5.0V
Vee = 5.5V

r--

=

r--

-20

-30

-30
-1.0

-1.0

2.0

1.0

1.0

10L Output Low Current
vs. VOL Output Low Voltage
70

10H Output High Current
V OH Output High Voltage

VS.

-i. = 25~C

C

60 r- Vee = 5.0V

!i:w

50

::>

40

J

/

§.

/

II:
II:

u
;t

9

30

~
0

20

~

~

j

/

10

o

o

TA

= 25°C

c

/ )'1
a /" ~ ~ ~
o ==
11
v:::V ~vcc

§.

Iiw

-10

II:
II:

-20

V

::t: -30

V

~

~
o

4.5Y- f - S.OV
Yee = S.SV- f - -

Vee

J:

I-'

-40

~ -50

L
200

2.0

V,N. INPUT VOLTAGE (Y)

V,N. INPUT VOLTAGE (Y)

-60

600

400

VOl.. OUTPUT LOW VOLTAGE (mY)

FUJITSU

10·125

o
VOH. OUTPUT HIGH VOLTAGE (Y)

MB7138E·W

Typical Characteristics
Curves
( Continued)

tAA Access Time
vs. Ambient Temperature

t DiS Disable Time
vs. Ambient Temperature
70

70

v L J - I--

60

!w

50

;::

40

:IE

-""'---""'-"<::>'-I::L.....s:L-'<=L...£1-JClc....<:"'n

9

AEF,,.,.

1

.254(7.21)
.302f67 )

1.180(29.97)
1.230(31.24)

FUJITSU

10-127

J.

0" _15"

~"""""'=--'rT

MB7138E·W

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

24·Lead Ceramic (Metal Seal) Flat Package
ICase No.: FPT.24C·A01)

-I~
II-MIN

t

INDEX AREA

~

.250(6.35)

I~'

I,
.-i

o

407(10.34)

-----*:.280(7TYp.11)

~~L:r~l

}Mr------'""

~ I- ..J1":~~~l~·!~l

::~:~:~~l

~_ _,.5",4"i.5(",'3".8,,4"")_ _. , ~M03A'X(0.79)
.555(14.10)
.588(14.94)
.612(15.55)

.070(1.78)
.100(2.54)

I-MAX

28·Pad Ceramic IMetal Seal) Leadless Chip Carrier
ICase No.: LCC·28C.A01)
R.008(0.20)TVP
(28PLCS)

·PIN 1 INDEX

!

.085(2.16)TYP

~l

.445(11.30)
.460(11.68)

.".445(11.30)
.460(11.68)

a

C.040(1.02)TYP
(3PLCS)

I

C.015(0.38)TYP

--.j
.05O(1.27)TVP

.085(2.16)MjI,,-_
.300(7.62)TVP

·SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NonCE

10·128

.05O(1.27)TYP

FUJITSU

Bipolar Memories
•

MB7141 E/H, MB7142E/H
Programmable Schottky 32,768-Bit Read Only Memory
(4,096 Words x 8-Bits)

Description
The Fujitsu MB7141 (open collector) and MB7142 (three-state) are
high-speed, Schottky TTL electrically field programmable read-only
memories organized as 4,096 words by a-bits. With uncommitted
collector outputs provided on the MB7141 and three-state outputs
on the MB7142, memory expansion is simple.
Fujitsu PROMS utilize a unique Shallow V-Groove (SVG) passive
isolation process which, combined with a very thin epitaxial layer
and the Schottky TTL process, provides small die sizes and very
fast access times.
The memory is fabricated with all cells low, the "zero" value for
positive logic. Logical "one" for a cell is achieved by programming.
Individual cells are programmed to a logical "one" using the highly
reliable Diffused Eutectic Aluminum Process (DEAP).
High programming yields are insured through the use of special
test cells to verify programmability on each device prior to
shipment.
Two guaranteed maximum access time options are available: the
7141 or 7142 "E" versions guarantee 65 ns maximum access time;
the 7141 or 7142 "H" versions guarantee 55 ns maximum
access time.

Feetures
•
•
•
•
•
•
•

•

Single +5V power supply
requirement
4096 words x B-bits; fully
decoded
High levels of programmability and reliability proven
in use
Unique, reliable DEAP
programming process
Low power, simplified
programming techniques
Low current PNP Inputs
AC characteristics guaranteed over the full operating
range
Fast. 45 ns typical access time
with two guaranteed options:
7141/7142 E: 65 ns max.
7141/7142 H: 55 ns max.

• TTL compatible inputs and
outputs; open collector
(MB7141) or three-state
(MB7142)
• Two Chip Enable Input
• JEDEC standard pinout.
• 24-pin flat, 28-LCC or 24-pln
DIP packages

This device contains circuitry to
protect the inputs against damage

due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage

higher than maximum rated voltages to this high impedance circuit.

10-129

MB7141E/H
MB7142E/H

MB7141/7142 Block Diagram
and Pin Assignment
A7

Vee (PVce)

A6

As

32768 (256.,28)

BIT

MEMORY CELLS
A2

A11

A1

E2

Ao

Oa

0,

07

02

Os

03

05

[1~

0&

117 Os
t-

11604

~15

Ne

i14

GND

~1~ 0,
~1~ 02

;-5~ 6T7-;-819-r10:11~

A.a

A3A2 A1 AoNCO,

Pad Configuration

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Power supply voltage

Vee

-0.5 to +7.0

V

Power supply voltage
(during programming)

Vee

-0.5 to +7.5

V

Input voltage

VIN

-1.5toVee

V

Input voltage (during programming)

VpRG

22.5

V

Output voltage (during programming)

VpRG

-0.5 to +22.5

V

Input current

liN

-20

rnA

Input current (during programming)

IpRG

+270

rnA

Output current

lOUT

+100

rnA

Output current (during programming)

IpRG

+150

rnA

Storage temperature

TSTG

-65 to +150

'C

Output voltage

VOUT

-0.5 to Vee

V

Note: Permanent device damage may occur jf ABSOLUTE rYlAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU
10-130

MB7141E/H
MB7142E/H

Guaranteed Operating
Conditions

Capacitance
(I = 1 MHz, Vee = +5V,
VIN = +2V, TA = 25°C)

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.75

5.0

5.25

V

Input low voltage

Vil

0

0.8

V

Input high voltage

VIH

2.0

Vee

V

Ambient temperature

TA

0

75

°C

Parameter

Symbol

Max

Unit

Input capacitance

CI

Min

10

pF

Output capacitance

Co

15

pF

Parameter

Symbol

Input leakage current
(VIH = 5.5V)

Typ

Min

Typ

Max

Unit

IR

40A

/LA

Input load current
(Vll = 0.45V)

IF

-250

/LA

Output low voltage
(lOl = 10 mAl

Val

0.45

V

Output low voltage
(lOl = 16 mAl

Val

0.50

V

Output leakage current
(Va = 2.4V, chip disabled)

MB7141

10lK

40

/LA

Output leakage current
(Va = 2.4V, chip disabled)

MB7142

10lH

40

/LA

Output leakage current
(Va = 0.45V, chip disabled)

MB7142

lOll

-40

/LA

Input clamp voltage
(lIN = -18 mAl

Vie

-1.2

V

Power supply current
(VIN = OPEN or GND)

lee

185

mA

140

Output high voltage"
(10 = -2.4 mAl

MB7142

VOH

2.4

Output short circuit curren!"'
(Va = GND)

MB7142

los

-15

V
-60

mA

Note: *1 Denotes guaranteed characteristics of the output high-level (ON) state when the chip is enabled (VIE'" O.4V, VIE = 2.4V) and the
programmed bit is addressed. These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

E

H

Parameter

Symbol

Typ

Max

Typ

Max

Unit

Access time (via address input)

tAA

45

65

45

55

ns

Output disable time

tOIS

40

40

ns

Output enable time

tEN

40

40

ns

10-131

MB7141E/H
MB7142E/H

AC Characteristics
(Continued)

Operation Timing Diagram
~-------------V'H

ADDRESS
INPUT

CHIP
ENABLE

\ / t sv

\V t.sv

_ _ _ _ _ _----J/\'-·_ _ _ _ _----JJI\'--_________ V'L
E,-------...

,----+---------+--------------V'H

E,-----J

'----+---------+--------------V'L

INPUT

______
-_, I;~~ __ =_J:-'AA
OUTPUT

CHIP
ENABLE
INPUT

__________ J

It.5V

VOH

*1.5V

'- _________

~

E,

,--------------V'H

E,

'-------------V'L
lOIS

'EN

OUTPUT

'-------------VOL
NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS TAKEN DISABLE. OUTPUT ENABLE
TIME IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN THE CHIP
ENABLE IS TAKEN ENABLE. THE HIGH RESISTANCE STATE IS DEFINED AS A POINT
ON THE OUTPUT WAVEFORM EQUAL TO A ~v OF O.5V FROM THE ACTIVE OUTPUT

LEVEl.

AC Test Conditions
Input Conditions

TRUTH TABLE

MB7141/7142

Amplitude. . . .. ............................. OV to 3V
Rise and Fall Time ........................... 5 ns from IV to 2V
Frequency ................................
I MHz
--f--Vcc

FUJITSU
10-132

I
I
I

Rt

R2

CL

'AA

300n

600n

30 pF

tors

300n

600n

30 pF

'EN

300n

600n

30 pF

MB7141E/H
MB7142E/H

Input/Output Circuit
Information

Schottky TTL circuit technology is
used in the input circuit to
achieve high-speed operation.
The PNP transistor in the first
stage of input circuit remarkably
improves input high/low current
characteristics. A protection
diode for reliable operation protects against voltage transients.

opposite low impedance states
simultaneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While
physical damage under these
conditions is unlikely, system
noise problems could result.
Therefore, the system designer
should consider these factors to

Open-Collector Output

MB7141/7142 Input

Input

The open-collector output is often
utilized in high speed applications
where power dissipation must be
minimized. When the device is
switched, there is no current
sourced from the supply rail.
Consequently, the current spike
normally associated with TTL
totem-pole outputs is eliminated.
In high frequency applications,
this minimizes noise problems
(false triggering) as well as
power drain. For example, the
transient current (lOW impedance
high-level to low impedance lowlevel) is typically 30 rnA for the
MB7142 (three-state) compared
to 0 rnA for the MB7141 (opencollector).

ensure that this condition does
not exist.
Also in the output circuit,
Schottky TTL circuit technology is
used to achieve high-speed operation. A PNP transistor provided
in the output circuit decreases
the load for the Chip Enable
circuit.

INPUT o---..--IF---I<'"I~""--Y

MB7141 Output

Three-State Output
A "three-state" output is a logic
element which has three distinct
output states of ZERO, ONE and
OFF (wherein OFF represents a
high impedance condition which
can neither sink nor source current at a"definable logic level).
Effectively', then, the device has
all the desirable features of a
totem-pole TTL output (e.g.,
greater noise immunity, good rise
time, line driving capacity), plus
the ability to connect to busorganized systems.

OUTPUT

MB7142 Output

In the case where two devices
are on at the same time, the possibility exists that they may be in

10-133

OUTPUT

MB7141E/H
MB7142E/H

Typical Characteristics
Curves

IINA Input Current
vs. VIN Input Voltage

IINC Input Current
vs. VIN Input Voltage

TA = 2SoC

TA = 2S°C

~
;;....-

~~

~~

~~~

~vee=4.sv

~~ee=4.sv

Vee = S.OY
Vee = 5.5V

Vee = S.OY
Vee = S.SY

r---

1.0

-30
-1.0

2.0

1.0

V,N. INPUT VOLTAGE (Y)

IOL Output Low Current
vs. VOL Output Low Voltage
70

~. = 2SIoC
r- Vee =

c-

60

!i:w

50

u

::>

40

.~

30

5

20

~

10

.§.

/

II:
II:

0

J

o

/V

V

V

o

200

600

400

10M Output High Current
vs. VOM Output High Voltage

TA = 2SoC

&~

m-10
iii
i3

/. ~ ~ ~VCC = 4.SV r-' " ,ve~ = 6.~V -

-20

i:c -30 8?

Vee = 5.5V

!;

§

-40

j-50
MB71..

-60

-

=

2S~C

Vee = S.OV

i:
~

Ii

/
/

30

V

20

/

10

V

MB7141

VOL. OUTPUT LOW VOLTAGE (mV)

1

i.

1 60

S.OV

::>

2.0

V,N. INPUT VOLTAGE (Y)

IOL Output Low Current
vs. VOL Output Low Voltage
70

r---

MB~1411717'

MB~141171f2

-30
-1.0

-

-: ~

I-

o
VOH. OUTPUT HIGH VOLTAGE (Y)

FUJITSU
10·134

o

o

200

MB7142
400

600

YOL. OUTPUT LOW VOLTAGE (mY)

MB7141E/H
MB7142E/H

Typical Characteristics
Curves
(Continued)

tAA Access Time
vs. Ambient Temperature

!
:I
"'
1=

70

70

60

60

..

t-- t--.
so
I--

40

:g

"""'
"j

tAM Access Time
vs. Ambient Temperature

30
20

"-

l - I--

: I-

:..-

~ 0vee=4.sv_ r -

0

1'\ S:

~v~e= s:ov

vre = yv_

r-

10

"-

Vee

= 4.SV

Vee

= S.sv

Vee = S.ov r-

0
0

MBj141

o

-so

so

100

-SO

TA, AMBIENT TEMPERATURE eC)

t DIS Disable Time
vs. Ambient Temperature

MB7142

o

so

100

150

TA, AMBIENT TEMPERATURE ("C)

t DIS Disable Time
vs. Ambient Temperature

70

70
MB7141

!
:I
"'
1=
....
"'

.

60

60

so

so

40

01

30

$

20

IS

40
.vee = ~.sv "yec = ~.ov
Vee = S.SV "-

10

o

-SO

~
I":::."- ~

Vee = 4.SV,
Vee = s.o~,
Vee = 5.5V

30
20

D~

0
so

100

TA, AMBIENT TEMPERATURE ("C)

10-135

o

-SO

f:;
MB7142

o

50

100

TA, AMBIENT TEMPERATURE ("C)

150

MB7141E/H
MB7142E/H

Typical Characteristics
Curves
(Continued)

tEN Enable Time
vs. Ambient Temperature

tEN Enable Time
vs. Ambient Temperature
70

70
M81141

80

..
..

!

:IE
~

....
ID

ffi

j

80

50
40

30
20

~

t"--..

Vee

= 4.5V

Vee

= 5.0V

Vee

= S.SV

50
40

r:::: ~ ~ r--

0

Vee = 4.SV

..

/

/vcc =
Vee

= 5.0V
5.5V

.,.../

..:::::
20

10

0

o

-50

MB7142

o

100

50

-50

50

150

100

T •• AMBIENT TEMPERAlURE (0C)
T•• AMBIENT TEIIIPERAlURE ("C)

Delay Time Increase
vs. C L Load Capacitance

Delay Time Increase
vs. CL Load Capacitance

70

MB~141

80

!..
~II:

..
0

~
5

40

.

lAA DELAY
tEN DELAY
'\

20
10

o

,,/

o

"" >-K

V

100

60
50
40

!!

30

~

~c

...
.s

50

!!
:IE

70

./

'"

/

-

300

200

CL. LOAD CAPACITANCE (PF)

FUJITSU

10-136

:IE

30

lAA DELAY

..5

20

TEN DELAY

~

I I I

C

.....

10

o

o

100

"'-

-- ""--

200

'",-

~

IIIB7142

300

CL. LOAD CAPACITANCE (pF)

400

MB7141E/H
MB7142E/H

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

24·Lead Ceramic ICERDIP) Dual In·Line Package
ICase No.: DIP·24C·C01)

1

R.025(O.64)
REF

.514(13.06)

O·

:=~~:~

1J~1

75

hrr..-rr-rrr..-TT-rr-T-rTT"T,,-rTT-r-:
00 0 0 0 0 000 00
I
1..
1.200(30.48)

.6OO(15.24)REF

)

~

1.300(33.02)

.014(0.36)

~

.230(5.64)MAX
.120(3.05)
.150(3.81)

.090(2.29)

.110(2.79)

~--~--~====~--~-

.020(0.51)
.050(1.27)

.015(0.38)
.023(0.58)

24·Lead Ceramic IMetal Seal) Flat Package
ICase No.: FPT·24C·A01)

-1
!

rit--------.-

.250(6.35
.300(1.62

-t
-ir

t

.393(9.98)
.401(10.34

INDEX AREA

~

.010(0.25)
MIN

I

.907(23.04)

.280(1.11)
TYP

.250(6.35
300
•

.050(1.21)

TYP

L -II ..

-r-

015(0.38)
.020(0.51)

.545(13.84)
.555(14.10)
.588(14.94)
.612(15.55)

10-137

.031(0.79)
MAX

-

.004(0.10)
.001(0.18)
.010(1.18)
.100(2.54)

MIN

MB7141E/H
MB7142E/H

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

28·Pad Ceramic (Metal Seal) Leadless Chip Carrier
(Case No.: LCC·28C·A01)
.085(2.16)TVP

I

-PIN 1 INDEX

n

.445(11.30)

I~..4 =~'~Jr
A6O(11.68)

C.015(0.36)TYP

.050(1.27)TYP

.300(7.62)TVP

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

10·138

.050(1.27)TYP

FUJITSU

Bipolar Memories
•

MB7142E·W
High Speed Schottky
TTL 32,768-Bit Prom

Description
The Fujitsu MB7142E-W is a high speed electrically field programmable read only memory. With three-state outputs on the
MB7142E-W, memory expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable
DEApTM (Diffused Eutectic Aluminum Process) during a simple
programming procedure.
The sophisticated passive isolation termed lOP (Isolation by Oxide
and Polysilicon) with thin epitaxial layer and Schottky TIL process
enables small chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed circuits in order to perform AC,
Dc and programming test prior to shipment. This results in extremely high programmability.

Features
•
•
•
•
•
•

Extended Temperature Range:
_55" to +125"C
Organization:
4096 words by 8-bits, fully
decoded
TTL compatible input/output
Fast access time:
65 ns Max.
45 ns Typ.
Single +5V supply voltage
Simplified, low power
programming

•

•
•
•
•
•

Proven high programmability
and reliability of DEAPTM (Diffused Eutectic Aluminum
Process)
Low current PNP inputs
MB7142E-W: Three-state
outputs
Two chip enable Inputs for
easy memory expansion
Standard 24-pin DIP package
Also available In 28-pad LCC

This device contains circuitry to

protect the i~ts against damage
due to high static voltages or electric fields. However, it is advised
that nannal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

10-139

MB7142E·W

MB7142E·W Block Diagram
and Pin Assignment

A,
A,

A,

As

As

As
AIO

E,

A:I

ADDRESS
BUFFERS

AIO
Al1

Vee
(PVee)

As

Ae

32766·BIT
MEMORY CELLS

As

A7

A,

(PVE)
Al1

A,

E,

Ao

Os

0,

Ot

0,

0.

0,

0,

GND

O.

~-"""L_ _ _ _- l

CHIP
ENABLE

o. Ot 0. 0,

o. 0, 0, 0,

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Power supply voltage

Vee

-0.5 to +7.0

V

Power supply voltage
(during programming)

Vee

-0.5 to +7.5

V

Input voltage

VIN

-1.5to +5.5

V

Input voltage
(during programming)

VIPRG

22.5

V

Output voltage
(during programming)

VOPRG

-0.5 to +22.5

V

Input current

liN

-20

rnA

Input current
(during programming)

IIPRG

+270

rnA

Output current

lOUT

+100

rnA

Output current
(during programming)

IOPRG

+150

rnA

Storage temperature

Tstg

-65 to +150

'C

Output voltage

VOUT

-0.5 to +Vcc

V

Note: Permanent device damage may occur jf ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU

10·140

MB7142E·W

Recommended Operating
Conditions

Capacitance
(I = 1 MHz, Vee = +5V,
VIN = +2V, TA = 25"C)

DC Characteristics
(Full guaranteed ranges unless
otherwise noted.)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.5

5.0

5.5

V

Input low voltage

V IL

0.0

0.8

V

Input high voltage

V IH

2.0

Vee

V

Ambient temperature

TA

-55

+125

"C

Parameter

Symbol

Max

Unit

Input capacitance

CI

Typ

10

pF

Output capacitance

Co

15

pF

Min

Parameter

Symbol

Input leakage current
(VIH = 5.5V)
Input load current
(VIL = 0.45V)

Min

Typ

Max

Unit

IR

40

p.A

IF

-250

p.A

Output low voltage
(lOL = 16mA)

VOL

0.50

V

Output leakage current
(VA = 2.4V, chip disable)

10lH

40

p.A

Output leakage current
(VOL = 0.45V chip disabled)

lOlL

-40

p.A

Input clamp voltage
(liN = -18 mAl

Vie

-1.2

V

Power supply current
(VIN = OPEN or GND)

lee

185

mA

Output high voltage
(10 = -2.4 mAl

V OH'1

2.4

Output short circuit current
(VA = GND)

105'1

-15

140

V
-60

mA

Note: *1 Denotes guaranteed characteristics of output high-level (ON) stale when the chip is enabled and the programmed bit is addressed.
These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Full guaranteed operating
ranges unless otherwise noted.)

Parameter

Symbol

Typ

Max

Unit

Address access time

tAA

45

65

ns

Output disable time

tDIS

40

ns

Output enable time

tEN

40

ns

10-141

MB7142.·W

Op....on Timing ""gram

\1/15V

ADDRESS
INPUT

CHIP
ENABLE
INPUT

V,.

\V 1.5V

J~'

/~

V,.
E

---;f,------'f.
IAA

DUTPUT

CHIP
ENABLE
INPUT

1.5V

----------~

IAA

V""

1.5V

~---------

r---------- V,.

E---------------,
1.5V

E--------------~

' - - - - - - - - - - - V,L
lEN

DUTPUT

~------------------V~

NOTE: DUTPUT DIBABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO
REACH A HIGH RESISTANCE STATE WHEN THE CHIP ENABLE IS
DIBABLED. OUTPUT ENABLE TIME IS THE TIME TAKEN FOR THE
OUTPUT TO BECOME ACTIVE WHEN THE CHIP ENABLE IS ENABLED.
THE HIGH RESISTANCE S'DI.TE IS DEFINED AS A POINT ON THE OUTPUT
WAVEFORM EQUAL TO A ~ V OF O.5V FROM THE ACTIVE OUTPUT LEVEL.

AC Test Conditions

INPUT CONDITIONS
Amplitude.. . . .. . . . .. .. . .. . . . . . . . . .. . . .. . . . . .. . . . . . .. .. OV to 3V
Rise and Fall Time ........................... 5 ns from IV to 2V
Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 MHZ

- -.....--vcc

FUJITSU

10·142

30pF

MB7142E·W

Input/Output Circuit
Information

Input

MB7142E·W Input Circuit

In the input circuit, Schottky TIL
circuit technology is used to
achieve high-speed operation. A
PNP transistor in the first stage
of the input circuit remarkably
improves input high/low current
characteristics. Also, the input
circuit includes a protection diode
for reliable operation.

INPUT

o-....--F----K:~

Three·State Output
A "three-state" output is a logic
element which has three distinct
output states of LOW, HIGH and
OFF (wherein OFF represents a
high Impedance condition which
can neither sink nor source current at a definable logic level.)
Effectively, then, the device has
all the desirable features of a
totem-pole TTL output (e.g.,
greater noise immunity, good rise
time, line driving capacity), plus
the ability to connect to busorganized systems.

MB7142E·W Output Circuit

In the case where two devices
are on at the same time, the possibility exists that they may be in
opposite low impedance states
simu~aneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While
physical damage under these
conditions is unlikely, system
noise problems could result.
Therefore, the system designer
should consider these factors to
ensure that this condition does
not exist.
Also in the output circuit,
Schottky TTL circuit technology is
used to achieve high-speed operation. Also, a PNP transistor is
provided in the output circuit to
decrease the load on the Chip
Select circuit.

10·143

MB7142E·W

Typical Characteristics
Curves

IINA Input Current
vs. V IN Input Voltage

TA

=

IINC Input Current
vs. V IN Input Voltage

TA

2S C
D

-

---: ~
~ ~ ::::

5

~c -10

-:;t

rn-

I-

co:
co:

w" -10

~-=~!Z

50
U
~

1.0

= 4.5V
Vee = S.OV
Vee = S.SV

"0:

jO -20

-30
-1.0

~.vee

w~

-

Vee = 5.5V

.",

~ ~ ::::

i!:_

= 4.5V
Vee = S.OV

-30
-1.0

2.0

1.0

10M Output High Current
vs. VOM Output High Voltage

J

TA

25'C
S.OV

vee =

-10

i3

-20

~V

~ ~ 0,

-60

600

400

o
VOH, OUTPUT HIGH VOLTAGE (V)

t DIS Disable Time
vs. Ambient Temperature
70

70

60

m

u
u

"j

-

~-

40

30

60

I--

50
'iO

I'" t'\ l\ycc = 4.SV-

.5.
w 40

Vee

1=

Vee =

lI!

~ 30

~~ec = 5.0V

is 20

2
50

100

T .. AMBIENT TEMPERATURE Fc)

FUJITSU

10-144

'\ t\",

III

10

-50

= 4.SV
5.0~0
Vee = 5.5V

II

Vcc=5.5V_

20

o

Vee = 5.5V- f - -

~ -50

V

tAA Access Time
vs. Ambient Temperature

w
lI!

r--

o

VOl., OUTPUT LOW VOLTAGE (mV)

1=

~~cc= S.OV

~
::;) -40

V

50

0~CC= 4.5V-

/"
""~ -30 ~

)V

200

!itw
0:
0:

J

~

= 25°C

1

/

o

2.0

V'N, INPUT VOLTAGE (V)

10L Output Low Current
vs. VOL Output Low Voltage

o

r--

-20

V,N. INPUT VOLTAGE (V)

T.

-

---: ~

.."

~~ee

fIl!Z
o:w

= 25°C

150

~~

10

o

-50

50

100

TA, AMBIENT TEMPERATURE FC)

150

MB7142E·W

Typical Characteristics
Curves
(Continued)

Delay Time Increase
vs. C L Load Capacitance

tEN Enable Time
vs. Ambient Temperature
70

70

..
.,

60

..

.5.
w

.,

60

.5. SO

50
40

....:!! ....... :"''/' ~
:E

w

/~cc = 4.5V
/ Vee 5.0V

UI

=
/Vee = 5.5V

5

40

i!:

.,

w
:E 30

w 30

~

w 20

j

t:":!~~Y "

20

"- ')
:-....... Ir~

c

.....

10

10

o

o

so

-SO

100

150

o

100

TA, AMBIENT TEMPERATURE ('c)

200

300

400

CL, LOAD CAPACITANCE (pF)

Package Dimensions
Dimensions in Inches
(millimeters)

24·Lead Ceramic ICERDIP) Dual In· Line Package
lcase No•• DIP·24C·C01)

l

R.025(O.64)
REF

.514(13.06)

h,...,..,-rr...,..,,...,..,-rr,--r-r.--TT..,-r-r.--TT-r--i

1.

00000000000
1.200(30.46)
1.300(33.02)

..

I

.6OO(15.24)REF

.625(15.87)

'541(rS)

Ul"==='f--'.014(0.36)

~
.020(0.51)
.050(1.27)
.015(0.38)
.023(0.58)

10·145

.600(15.24)

,23O(5'84)MAX
.120(3.05)
.150(3.81)

MB7142E·W

Package Dimensions
(continued)
Dimensions in inches
(millimeters)

24.Lead Ceramic (Metal Seal) Plat Package
(Case No.: FPT.24CoA01)
.011Jj0.25)
- - --MIN

t

'--'

.250(6.35)

D -i-~r.

1
MIN
---.t.280TY(7p.")

.393(9.98)

407(10.34)

INDEX AREA

""frr'TT;;=;;=;;=~~::~l
.050(1.27)
TYP

J!j-------L

I..- -J

1...015(0.38)
.020(0.51)
.545(13.84)
.555(14.10)
.588(14.84)
.612(15.55)

.004(0.10)
.007(0.18)
031(079)

~

:::~:~:~
Dimensions in
Inches (millimeters)

28·Pad Ceramic (Metal Seal) Leadless Chip Carrier
(case No.: LCC'28C'A01)

n
I~...4 5(=, ~dJ'·
!

.085(2.16)TYP

'PIN 1 INDEX

.445(11.30)

A6O(1'.88)

C.Ol5(O.38)TYP
·00001.27)TYP
.3OO(7.62)TYP

'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

10·146

·00001.27)TVP

FUJITSU

Bipolar Memories
•

MB7143E/H, MB7144E/H/Y
Programmable Schottky 65,536-Bit Read Only Memory
(8,192 Words x 8-Bits)

Description
The Fujitsu MB7143 (open collector) and MB7144 (three-state) are
high-speed Schottky TTL electrically field programmable read-only
memories organized as 8,192 words by 8-bits. With uncommitted
collector outputs provided on the MB7143 and three-slate outputs
on the MB7144, memory expansion is simple.
Fujitsu PROMS utilize a unique Shallow V-Groove (SVG) passive
isolation process which, combined with a very thin epitaxial layer
and the Schottky TTL process, provides small die sizes and very
fast access times.
The memory is fabricated with all cells low, the "zero" valy.e for
positive logic. Logical "one" for a cell is achieved by programming.
Individual cells are programmed to a logical "one" using the highly
reliable Diffused Eutectic Aluminum Process (DEAP).
High programming yields are insured through the use of special
test cells to verify programmability on each device prior to
shipment.
Three guaranteed maximum access time options are available: the
7143 or 7144 "E" versions guarantee 65 ns maximum access time;
the 7143 or 7144 "H" versions guarantee 55 ns maximum access
time. The 7144Y guarantees 45 ns maximum access time.

Fe.tures
• Single +5V supply voltage
• 8192 words x B-bits; fully
decoded
• High levels of programmability and reliability proven
In uae
• Unique, reliable DEAP
programming process
• Low power, simplified
programming techniques
• Low current PNP Inputs
• AC characteristics guaranteed over the full operating
range
• Fast. 40 ns typical access.
time with three guaranteed
options:
7143/7144 E: 85 ns max.
7143/7144 H: 55 na max.
7144 Y: 45 ns max.

• TTL compatible inputs and
outputs; open collector
(MB7143) or three-state
(MB7144)
• Single Chip Enable Input
• JEDEC standard pinout;
24-pln flat, 28-LCC or 24-pin
DIP packages

This device contains circuitry to
protect the inputs against damage
due to high static voltages or elec-

tric fields. However, it is advised
that normal precautions be taken to
avoid apptication of any voltage
higher than maximum rated vohages to this high impedance circuit.

10-147

MB7143E/H
MB7144E/H/Y

MB7143/7144 Block
Diagram and Pin
Assignments

Ao
A,
A,

A7

Vee (PVee)

Ao

Ao

As

A.

Ao

AlO

Ao

E(PYE)

As

A,

A11

A.

A,

A"

Ao

Og

0,

0,

A,
65536 (256x256) BIT

Ao

MEMORY CEllS

A7
A.
A.

0,

Og

A11

O.

O.

A"

GNO

O.

AlO

(PVEl A" o.
A,oEA11I NC 10,

~1~ 0&
~1.! 05
11604

r15 NC

i14

GND

[1~ 03
L1~ 02

Pad Configuration

Absolute Maximum Ratings
(See Note)

Rating

Symbol

Value

Unit

Power supply voltage

Vee

-0.5 to +7.0

V

Power supply voltage
(during programming)

Vee

-0.5 to +7.5

V

Input voltage

VIN

-1.5 to 5.5

V

Input voltage (during programming)

VPRG

22.5

V

Output voltage (during programming)

VPRG

-0.5 to +22.5

V

Input current

liN

-20

mA

Input current (during programming)

IpRG

+270

mA

Output current

loUT

+100

mA

Output current (during programming)

IpRG

+150

mA

Storage temperature

TaTG

-65 to +150

'C

Output voltage

VOUT

-0.5 to Vee

V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU
10-148

MB7143E/H
MB7144E/H/Y

Guaranteed Operating
Conditions

Capacitance
(I = 1 MHz, Vee = +5V,
Y'N = +2V, TA = 25"C)

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

Vee

4.75

5.0

5.25

V

Input low voltage

V,L

0

0.8

V

Input high voltage

V,H

2.0

5.5

V

Ambient temperature

TA

0

75

"C

Parameter

Symbol

Max

Unit

Input capacitance

C,

Min

Typ

10

pF

Output capacitance

Co

15

pF

Parameter

Symbol

Max

Unit

Input leakage current
(V'H = 5.5V)

IR

Min

Typ

40

p.A

Input load current
(V'L = 0.45V)

IF

-250

p.A

Output low voltage
(lOL = 10 rnA)

VOL

0.45

V

Output low voltage
(loL = 16 rnA)

VOL

0.50

V

Output leakage current
(Va = 2.4V, chip disabled)

MB7143

10LK

40

p.A

Output leakage current
(Va = 2.4V, chip disabled)

MB7144

10lH

40

p.A

Output leakage current
(Va = 0.45V, chip disabled)

MB7144

lOlL

-40

p.A

Input clamp voltage
(l,N = -18 rnA)

Vie

-1.2

V

Power supply current
(V'N = OPEN or GND)

lee

190

rnA

160

Output high voltage"
(10 = -?.4 rnA)

MB7144

VOH

2.4

Output short circuit current"
(Va = GND)

MB7144

los

-15

V
-60

rnA

Note: *1 Denotes guaranteed characteristics of the output high·level (ON) state when the chip is enabled (VIE = 2.4V) and the programmed
bit is addressed. These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

H

Parameter

Symbol

Typ

Max

Typ

Max

MB7144Y
Typ
Max

Access time (via address input)

tM

40

65

40

55

40

Output disable time

tOiS

40

40

40

ns

Output enable time

tEN

40

40

40

ns

E

10-149

45

Unit
ns

MB7143E/H
MB7144E/H/Y

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Operation Timing Diagram
~------------- V,H

ADDRESS
INPUT

CHIP
ENABLE
INPUT

\/,.5V

JI\

_ _ _ _ _ _ _ _ _ _ _ _- J

~

\/'5V

__________

/

~

~

.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _

E-----..
~---+----------+-------------- V,L

------------ff~~--=\;G'AA
1.5V

OUTPUT

VOH

1.5V

----------~
CHIP
ENABLE
INPUT

V,L

~---------~

1.5V

E---------J

' - - - - - - - - - - - - - - - V,L
'EN

OUTPUT
' - - - - - - - - - - - - - - VOL

NOTE: OUTPUT DISABLE 11ME IS THE 11ME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS TAKEN HIGH. OUTPUT ENABLE
TIME IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN THE CHIP
ENABLE IS TAKEN LOW. THE HIGH RESISTANCE STATE IS DEFINED AS A POINT
ON THE OUTPUT WAVEFORM EQUAL TO A OV OF 0.5V FROM THE AC11VE OUTPUT
LEVEL.

AC Test Conditions

Input Conditions

TRUTH TABLE
MB7'43/7144

Amplitude ................................... OV to 3V
Rise and Fall Time ........................... 5 ns from IV to 2V
Frequency .................................. 1 MHz

--.--Vcc

R,

FUJITSU
10-150

I
I
l

R,

RZ

CL

'AA

300ll

8000

30 pF

'DIS

3000

8000

30pF

'EN

3000

8000

30pF

MB7143E/H
MB7144E/H/Y

Input/Output Circuit
Information

Input

In the input circuit, Schottky TTL
circuit technology is used to
achieve high-speed operation.
The PNP transistor in the first
stage of input circuit remarkably
improves input high/low current
characteristics. Also, the input
circuit includes a protection diode
for reliable operation.

In the case where two devices
are on at the same time, the possibility exists that they may be in
opposite low impedance states
simultaneously; thus, the short
circuit current from one enabled
device may flow through the
other enabled device. While
physical damage under these
conditions is unlikely, system
noise problems could result.

Open-Collector Output

The open-collector output is often
utilized in high speed applications
where power dissipation must be
minimized. When the device is
switched, there is no current
sourced from the supply rail.
Consequently, the current spike
normally associated with TTL
totem-pole outputs is eliminated.
In high frequency applications,
this minimizes noise problems
(false triggering) as well as
power drain. For example, the
transient current (low impedance
high-level to low impedance lowlevel) is typically 30 rnA for the
MB7144 (three-state) compared
to 0 rnA for the MB7143 (opencollector).

Therefore, the system designer
should consider these factors to
ensure that this condition does
not exist.
Also in the output circuit,
Schottky TTL circuit technology is
used to achieve high-speed operation. A PNP transistor provided
in the output circuit decreases
the load for the Chip Enable
circuit.

MB7143/7144 Input

INPUT o-~-f~"""'K

MB7143 Output

Three-State Output
A "three-state" output is a logic
element which has three distinct
output states of ZERO, ONE and
OFF (wherein OFF represents a
high impedance condition which
can neither sink nor source current at a definable logic level).
Effectively, then, the device has
all the desirable features of a
totem-pole TTL output (e.g.,
greater noise immunity, good rise
time, line driving capacity), plus
the ability to connect to busorganized systems.

OUTPUT

MB7144 Output

OUTPUT

10-151

MB7143E/H
MB7144E/H/Y

Typical Characteristics
Curves

liN Input Current
vs. VIN Input Voltage

10L Output Low Current
VOL Output Low Voltage

VS.

70
TA

~

Ii:l -10~~=---+---~~~~--~+-~
i
j

C

60

~

50

Vee = 5.5V

-20 ~I-----+-------+-------+-~
MB7143
MB7144

a:
a:
::>
u

40

...

5
~
0
~

I

20
10

o
o

~ -20
~
l:

-30

~::> -40

/

200

'I

/

MB7143
MB7144

400

70

= 25°C

60

~V

~~~
~~CC=5.0V
~V
=

0~cc=4.5V- I - Vee

5.5V--

I--

!
,.'"
.,1=

e
u

"j

j-50

50

'"'"'------.

40
30

-

/'

~~

"''~' '

-50

70

i=

r-....

w

"j

-

t--.... 1-00.
40

tJ)
tJ)

0
0

30

20

.&

r-.

~

l-""' ......

"~

'\

"Vee - 4.5V
Vee = S.OV

Vee

-,

10

= 5.SV-

,

MB7144

o

= 5.5V

-50

50

100

TA. AMBIENT TEMPERATURE (0C)

FUJITSU
10·152

50

100

TA. AMBIENT TEMPERATURE (0C)

60
50

Vee

-

MB7143

o

o

tAA Access Time
vs. Ambient Temperature

~

= 4.5V
= S.OV

10

VON. OUTPUT HIGH VOLTAGE (V)

w

Vee

Vee

20

MB7144

:;

600

tAA Access Time
vs. Ambient Temperature

o

-60

/

VOL. OUTPUT LOW VOLTAGE (mV)

10M Output High Current
vs. VOM Output High Voltage

~ -10

/

/

30

V,N. INPUT VOLTAGE (V)

1

= S.OV

~

0

-~~.~0~----~------~lL.O~----~2f.o~~

TA

/

= 25"C

Vee

!.

MB7143E/H
MB7144E/H/Y

Typical Characteristics
Curves

t DIS Disable Time
vs. Ambient Temperature

(Continued)

!

70

70

60

60

50

w

:IE

;::

v::

40

~
m

!!l'"
]

tEN Enable Time
vs. Ambient Temperature

30
20

I-

!w

50

~cc = ~.OV

;::

40

= 5.5V

~
w

Vee

' / Vee

/

:IE

= 4.SV

w
....
m

j

to

o

~

30

I--

20

MB7t43

o

o

-50

tOO

50

Vcc= 5.0V_

~VCC=5.5V

to

MB7t43
MB7144

-50

/,Ycc= 4.SV

tOO

50

TA. AMBIENT TEMPERATURE ('e)

TA. AMBIENT TEMPERATURE ('e)

Delay Time Increase
vs. C L Load Capacitance

tEN Enable Time
vs. Ambient Temperature
70

70

60

60

MB7t43

!w
:IE

;::

50

v~=

40

w
....

m

~

30

j

20

w

!w

/~cc = 4.5V

-""""'-

/

5.0V_

-

~

II:

50

u

40

:IE

30

.

!

/VCC=5.5V

;::

~

./
ADD. TO 1M D~

S 20

~

w

c

to

to
MB7144

o

-50

50

tOO

Delay Time Increase
vs. C L Load Capacitance
70

oS
w

~
5

MB7t44

60

50
40

!

w
:IE
;::

30

ADD. TO 1M DELA~

S
w 20

..,......, I--""

c

to

o

o

~ =-----.:;,
tOO

V
L...-

TO

~ DELAY

200

300

CL. LOAD CAPACITANCE (pF)

10-153

o

tOO

Ct..

TA. AMBIENT TEMPERATURE ('e)

..

o

-

.£.~:o:.TO~ DELAY
200

LOAD CAPACITANCE (pF)

300

MB7143E/H
MB7144E/H/Y

Package Dimensions
Dimensions in inches
(millimeters)

24·Lead Ceramic ICERDIP) Dualln·Llne Package
ICase No.• DIP.24C.C01)

l

R.02S(O.64)
REF

J.

.514(13.06)
75

)

1~-'D--rro-'-'--rro....or-rTo-rrD"'T"'TD--rro-'-'o--rrD-'-'Dr-r~..
..

._

I·

1.200(30.48)
1.300(33.02)

_ .

~

.600(15.24)
.625{15.87)

.6OO(15.24)REF

LU~

'23O(5'64)MAX
.120(3.05)
.150(3B1)

.020(0.51)
.050(1.27)

24.Lead Ceramic (Metal "al) Flat Package
ICase No•• FPT·24C·A02)

.004(0.10)
.007(0.18)

.25O(t35)
.300{7.62)

1-

I

04) MIN

INO

.300(7.62} TYP

.393(9.98)
.407(10.34)

EXARE\

~

-i7.

.250(6.35)
62)
.30

.050(1.27)

TYP

I-- -..II •.

015(0.38)
.020(0.51)
.545(13.84)
.555{14.10)
.588{14.94)
.612(15.55}

FUJITSU

10·154

j

.010(0.25)

MIN
.031(0.79)

.070{1.78}

MAX

.100(2.54)

MB7143E/H
MB7144E/H/Y

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

28·Pad Ceramic IMetal Seal) Leadless Chip Carrier
ICase No., LCCo28C·A02)
.085(2.16)TYP

·PIN 1 INDEX

I

rl

.445(11.30)
.460(11.68)

1'14~= : =:=:=: =: =~=dJ ,lL~m
'SHAPE OF PIN 1 INDEX: SUBJECT TO CHANGE WITHOUT NonCE

10-155

.300(7.62)TVP
I

C.015(0.38)TVP
.05O(1.27)TVP

Advanced Information
Availability Q2 '86

FUJITSU

Bipolar PROM
•

MB7144Y
High Speed 65536-Bit
Schottky TTL PROM

Features
• Organization:
8192 x B-blts
Process:
Schottky TTL
Program:
Diffused Eutectic Aluminum
Process (DEAP)
• Output:
Three-State
• Power Supply:
+5V ±5%
• Power Dissipation:
998 mWmax,
• Address Access Time:
45 ns max.
• Package:
24-pln DIP/FPT
2B-pad LCC

•
•

.

Vee

A,

(pVcc)

A,

.

A,

A,

A"

A,

E(PVE)

A,

Au

A,

A"

A,

08

01

07

02

08

03

05

GNO

04

A.
A,
A,
A,
A,

,
,

25 Al(I
24 E(PVe)

23 All

TOP VIEW
9

21 NC

2008

0111

1007
12 13 14 15 16 17 18
02 03GNDNC 04 05 06
28-PAD L.eC

10·156

22 A12

NC 10

FUJITSU

Bipolar Memories
•

MB7144E-W
Programmable Schottky
65,536-Bit Read Only Memory

Description
The Fujitsu MB7144E-W is a wide temperature range version of the
7144E field programmable read-only memory. Like the 7144E, it is
organized as 8192 words by 8-bits.
The 7144E-W operates from 125 degrees C to - 55 degrees C.
Fujitsu PROMS utilize a unique Shallow V-Groove (SVG) passive
isolation process which, combined with a very thin epitaxial layer
and the Schottky TTL process, provides small die sizes and very
fast access times.
The memory is fabricated with all cells low, the "zero" value for
positive logic. Logical "one" for a cell is achieved by programming.
Individual cells are programmed to a logical "one" using the highly
reliable Diffused Eutectic Aluminum Process (DEAP).
High programming yields are insured through the use of special
test cells to verify programmability on each device prior to
shipment.

Features

•
•

•

•
•
•

125°C to -55°C operating
temperature range
8192 words x 8-bits; fully
decoded
High levels of programmability and reliability proven
in use
Unique, reliable DEAP
programming process
Low power, simplified
programming techniques
Low current PNP Inputs

•

AC characteristics guaranteed over the full operating
range
• Fast. 40 ns typical; 65 ns
maximum access time
• TTL compatible inputs and
outputs; open collector or
three-state
Single Chip Enable input
JEDEC standard pinout;
24-pin flat, 28-LCC or
24-pin DIP packages

••

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.

10-157

MB7144E·W

MB7144 Block Diagram
and Pin Assignments

Pin Configuration
for DIP/Flatpack

65536 (256x256)

BIT

MEMORY CELLS
ADDRESS
BUFFERS

A,

Vee
(PVee)

Ao

Aa

As

A,

Aa

A,.

A:!

E(PVE)

A,

A"

A,

A12

Aa

a,

Q.

Q,

Q,

Qs

Q,

Q,

GND

Q3

CHIP
ENABLE

Pad Configuration
(PVel
A10

A12

E A11

Ne

Q,

06

[1~ 05

,-

11704
11603

~15 Ne

:;4

GND

l1!

01

[1~ 02

~5~

ST7-:-olgT10:1fi

A4 Aa A2 A1

Absolute Maximum Ratings
(See Note)

AoNe 00

""'R.a.t.in;,:;g;..._ _ _ _ _ _ _ _ _ _ _ _ _...;.::.;;.;_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Symbol
Value
Unit
Power supply voltage
Power supply voltage
(during programming)

Vee

-0.5 to +7.0

V

Vee

-0.5 to +7.5

V

Input voltage

VIN

-1.5t05.5

V

Input voltage (during programming)

VPRG

22.5

V

Output voltage (during programming)

VpRG

-0.5 to +22.5

V

Input current

liN

-20

mA

Input current (during programming)

IpRG

+270

mA

Output current

lOUT

+100

mA

Output current (during programming)

IpRG

+150

mA

Storage temperature

TSTG

-65 to +150

°c

Output voltage

VOUT

-0.5 to Vee

V

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet.

FUJITSU
10·158

MB7144E-W

Guaranteed Operating
Conditions

Capacitance
(! = 1 MHz, Vcc = +5V,
VIN = +2V, TA = 25'C)

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Min

Typ

Max

Supply voltage

Vcc

4.5

5.0

5.5

V

Input low voltage

Vil

0

0.8

V

Input high voltage

VIH

2.0

5.5

V

Ambient temperature

TA

-55

125

'C

Parameter

Symbol

Max

Unit

Input capacitance

CI

10

pF

Output capacitance

Co

15

pF

Parameter

Min

Max

Unit

111

40

pA

IF

-250

/LA

Output low voltage
(Iol = 16 mAl

VOL

0.50

V

Output leakage current
(Vo = 2.4V, chip disabled)

10lH

40

/LA

Output leakage current
(Vo = 0.45V, chip disabled)

lOll

-40

/LA

Input clamp voltage
(liN = -18 mAl

VIC

-1.2

V

Power supply current
(VIN = OPEN or GND)

Icc

190

mA

Output high voltage"1
(10 = -2.4 mAl

VOH

2.4

Output short circuit currenf 1
(Vo = GND)

los

-15

Input leakage current
(VIH = 5.5V)
Input load current
(Vll = 0.45V)

Symbol

Typ

Unit

Min

Typ

160

V
-60

mA

Note: ·1 Denotes guaranteed characteristics of the output high-level (ON) state when the chip is enabled (VICE"" O.4V. VICE = 2.4V) and
the programmed bit is addressed. These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Recommended operating
conditions unless otherwise
noted.)

Parameter

Symbol

Typ

Access time (via address input)

tM

40

MB7144E-W
Max
65

Unit
ns

Output disable time

t DIS

25

40

ns

Output enable time

tEN

25

40

ns

10-159

MB7144E·W

AC Characteristics
(Continued)
(Recommended operating
conditions unless otherwise
noted.)

Operation Timing Diagram

CHIP
ENABLE
INPUT

OUTPUT

CHIP
ENABLE
INPUT

,------------- V,.

\V

I

ADDRESS
INPUT

t .sv
t .SV
_ _ _ _ _ _ _ _ _--'/ \'--_ _ _ _ _ _ _--'/\.'-_ _ _ _ _ _ _ _ _ _ _ _ _ V,L

V,.

E - - - -.....

'-----t----------t-------------- V,L

Q

---------~/~~--=,f~·
__________ J

t.SV

VOH

t.SV

~

_________

~

V,.
E _ _ _ _ _ _ _ _ _J

1.SY
'--------------V,L

'EN

OUTPUT

Q------------"r

~------------------y~

NOTE: OUTPUT DISABLE TIME IS THE TIME TAKEN FOR THE OUTPUT TO REACH A HIGH
RESISTANCE STATE WHEN THE CHIP ENABLE IS TAKEN HIGH. OUTPUT ENABLE
TIME IS THE TIME TAKEN FOR THE OUTPUT TO BECOME ACTIVE WHEN THE CHIP
ENABLE IS TAKEN LOW. THE HIGH RESISTANCE STATE IS DERNED AS A POINT ON
THE OUTPUT WAVEFORM EQUAL TO A ~V OF O.SV FROM THE ACTIVE OUTPUT
LEVEL.

AC Test Conditions
Input Conditions

TRUTH TABLE
MB7144-W

Amplitude ................................... OV to 3V
Rise and Fall Time ........................... 5 ns from IV to 2V
Frequency .................................. I MHz
----

40

9

30

TA

/

= 2S'C

Vee = S.OV

a:
a:

/

;:

.

I-

/

/

::>

I-

::>

20

~

10

0

o

-~1.~0J-----~------~1L.0-------2~.0~-"

/

o

VIN. INPUT VOLTAGE (V)

200

/

MB7144

400

600

VOL, OUTPUT LOW VOLTAGE (mV)

tAA Access Time
VS. Ambient Temperature

10M Output High Current
V OM Output High Voltage

VS.

70
TA

...s

= 25°C
60

~ l/

~ -10

w
a:
a:

G -20

":E -30 ~
~ -40
:I:

~~~
/'

~

50

'-.....

i=

40

~

,.

w

0~CC

= 4.5V- - -

~~cc = S.OV

Vee = 5.5V--

-

::::I

o

~-50



~

10

o

o

~

100

200

V

-

,...-/'

f-"--:o;;;:o~

50

~

100

TA, AMBIENT TEMPERATURE ("C)

lA. AMBIENT TEMPERATURE ( C)

()

f---

10

-50

w

5.0V_

V~VCC=4.5V

MB7144

w
a:

= 5.5V

VC~ =::

40

~

m

~

§

50

w

40

DELAY
300

CL, LOAD CAPACITANCE (pF)

10-163

MB7144E·W

Package Dimensions
Dimensions in inches
(millimeters)

24·Lead Ceramic IMetal Seal) Flat Package
lCase No.: FPT·24C·A02)

J

.004(0.10)
.007(0.18)

.250(6.35)
.300(7.62)

1-

I

04) MIN

INO

.300(7.62) TVP

.393(9.98)
.407(10.34)

EXARE\

~

--i

.250(6.35)
.31.62 )

.050(1.27)
TVP

I-- --II ...

015(0.38)
.020(0.51)
.545(13.84)
.555(14.10)

j

.010(0.25)
MIN

.031(0.79)

.070(1.78)
.100(2.54)

MAX

.588(14.94)
.612(15.55)

24·Lead Ceramic ICERDIP) Dual In· Line Package
ICase No.: DIP·24C·C01)

Tl
J.

l

R.025(O.64)
REF

.514(13.06)
75

r.

)

'O-'TO"TlO-'To..,rr,o-rrO"TlO-'TO"TlorrTO"'Orr-1l·

._

1.200(30.48)
1.300(33.02)

..

~

.600(15.24)
.625(15.87)

lJ~

.230(5.84)MAX

.020(0.51)
.050(1.27)
.015(0.38)
.023(0.58)

FUJITSU

10-164

I
.600(15.24)REF

.120(3.05)
.150(3.81)

MB7144E·W

Package Dimensions
(Continued)
Dimensions in inches
(millimeters)

28·Pad Ceramic (Metal Seal) Leadless Chip Carrier
ICase No.: LCC.28C.A01)

·PIN 1 INDEX

I

n

R.OO8(O.20)TVP
(28PLCS)

.085(2.16)TYP

.300(7.62)TVP

I

_J

C.OI5(O.38)TVP
.445(11.30)
.480(11.68)

.05O(1.27)TYP

.3OO(7.62)TVP

'SHAPE OF P1N INDEX: SUBJECT TO CHANGE WITHOUT NOTICE

10-165

.050(1.27)TYP

FUJITSU

Bipolar Memories
•

MB7151E/H, MB7152E/H/Y

Schottky TTL 16,384-Bit
Bipolar Programmable
Read-Only Memory

D•• crlptlon

The Fujitsu MB7151 and MB7152 are high speed Schottky TIL
electrically field programmable read only memories organized as
4096 words by 4-bits. With uncommitted collector outputs provided on the MB7151 and three-state outputs on the MB7152,
memory expansion is simple.
The memory is fabricated with all logic "zeros" (positive logic).
Logic level "ones" can be programmed by the highly reliable
DEApTM (Diffused Eutectic Aluminum Process) according to
simple programming procedures.
The sophisticated passive isolation termed lOP (Isolation by
Oxide and Polysllicon) with thin epitaxial layer and Schottky TIL
process permits minimal chip size and fast access time.
The extra test cells and unique testing methods provide enhanced
correlation between programmed and unprogrammed circuits in
order to perform AC, DC and programming test prior to shipment.
This results In extremely high programmability.

F ••tur••

• Single +5V supply voltage
• Organized as 4096 words by
4-blts, fully decoded
• Proven higher programmability and reliability
• Programming by DEApTM
(Diffused Eutectic Aluminum
Process)
• Simplified and lower power
programming
• Low current PNP Inputs
• AC characteristics
guaranteed over full
operating voltage and
temperature range via
unique testing techniques

• Fast access time, 35nsec
typo
E-55nsec max.
H-45nsec max.
Y-35nsec max.
• TIL compatible inputs and
outputs
• Open collector outputs,
MB7151
• Three-state outputs, MB7152
• Two chip enables for
simplified memory
expansion
• 300mll 20-pln DIP package

10-166

Ma7i5iEI"
Ma7i5Z!!I"1Y

alock Diagram and
Pin Assignment

Ae

VcdPVccl

A,

A7

A,

A,

As

Aw

A,

A,

16384 BIT
MEMORY CELLS

A,

A,
A,

A,

A"

A,

E,

A3

E,(PV,)

A,

0,

A,

0,

A,
A,

Ao

03

GND

0,

A,
A"
An

0,

Absolute Maximum Ratings
(See Note)

0,

0,

0,

Rating

Symbol

Value

Power Supply Voltage
Power Supply Voltage (during programming)
Input Voltage
Input Voltage (during programming)
Output Voltage (during programming)
Input Current
Input Current (during programming)
Output Current
Output Current (during programming)
Ceramic:
Storage Temperature Plastic:

Vee

-0.5 to
-0.5 to
-1.5 to
22.5
-0.5 to

Output Voltage

Vour

Unit
+7.0
+7.5
+5.5
+22.5

-20
+270
+100
+150
-65 to +150
40 to +125
-0.5 to Vee

V
V
V
V
V
mA
mA
mA
mA

·C
V

Note: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to conditions as detailed in the operational sections of this data sheet. This device contains circuitry to protect the In·

puts against damage due to high static voltages or electric fields. However, It Is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high Impedance circuit.

Capaoltance
(f=1MHz, Vee = +5V,
VIN = +2V, TA =25·C)

Guaranteed Operating
Conditions

Parameler

Symbol

Input Capacitance
Output Capacitance

CI

Parameter

Symbol

Min

Typ

Max

Unit

Vee
VIL
VIH

4.75
0
2.0
0

5.0

5.25
0.8

V
V
V
·C

Supply Voltage
Input Low Voltage
Input High Voltage
Ambient Temperature

Min

Typ

Co

TA

FUJITSU
10·167

Max

Unit

10
15

pF
pF

Vee
75

MB7151E/H
MB7152E/HIY

DC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Max

Unit

Input Leakage Current (V,H = 5.5 V)
Input Load Current (V ,L = 0.45 V)

IR
IF

40
-250

p.A
p.A

Output Low Voltage (IOL = 10 mAl

VOL
VOL

0.45
0.50

V

Output Low Voltage (IOL = 16 mAl
Output Leakage Current (Vo = 2.4V, Chip disabled)

MB7151
Output Leakage Current (Vo = 2.4V, Chip disabled) MB7152
Output Leakage Current (Vo = 0.45V, chip disabled) MB7152

10LK

40

p.A

10lH
lOlL

Input Clamp Voltage (l,N = - 18 mAl

40
-40
-1.2

p.A
p.A
V

Output High Voltage (10 = - 2.4 mAl

MB7152

V'c
Icc
V OH '

Output Short Circuit Current (Vo = GND)

MB7152

los

Power Supply Current (V'N = OPEN or GND)

Typ

Min

120

170

2.4
-15

,

V

mA
V

-60

mA

*Note: Denotes guaranteed characteristics of the output high-level (ON) slate when the chip is enabled (VICE = O.4V) and the programmed
bit is addressed. These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

AC Characteristics
(Full guaranteed operating
conditions unless otherwise
noted.)

Parameter

Symbol

Access Time (via address input)
Output Disable Time

tAA
t DIS

Output Enable Time

tEN

E
Typ
35

H

MB7152Y

Max

Typ

Max

Typ

Max

Unit

55
40

35

45

28

35

ns

30

ns

30

ns

40
40

40

AC Test Conditions

MB7151/MB7152

Input Conditions
Amplitude: OV to 3V
Rise and Fall Time: 5ns from 1V to 2V
Frequency: 1MHz

R,

R2

CL

tAA
t DIS

3ODI)

6001)

30pF

3ODI)

tEN

3001)

6000
6001)

30pF
30pF

Operation Timing Diagram
Address Input

1.5V

E - - -....
Chip Enable Input

(tAA -

r-----~f t A A

Output

_______ J

1.5V

1.5V
L _______

V OH
~

V,H

Chip Enable Input

E _ _ _ _ _ _...J
' - - - - - - - - - - - Vil

t OIS

1.5V

Output

~---------

VOL

Note: Output disable time is the time taken for the output to reach a high resistance state when' the chip enabte.is taken high (disabled).
Output enable time is the time laken for the output to become active when all of chip enables are taken low (enabled). The high resistance
state is defined as a point on the output waveform equal to a !l.V of O.5V from the active output level.

10-168

MB7151EIH
MB7152EIHIY

Typical Characteristics
Curve.

liN Input Current
VIN Input Voltage

IOL Output Low Current
vs. VOL Output Low Voltage

IOL Output Low Current
VOL Output Low Voltage

VS.

VS.
70

1

60

70

t-

/

T... =2S D C
Vcc =5.DV

II

1:
~

!o,
.2

/
/

30

/

20

MB7151/52

-10

8

-20

~

~

-30

-s

-40

VV

"

S

~

::--. Vcc -4.5V

-

V cc =5.0V
Vee = 5.5V

!

20

j

'0

o

70

j

~

I
~

;;:
~

Vcc =4.5V

Vee = 5.0V

vT=sor-

20

j
-~

'0

.2

MB7152

50
40

30

50

0

l

50

~ so

W 50

i=

40

~

~

i=

Vcc =4.5V

20

~

""'~

~

~

'0

o

-50

50

VCC.4.5:~
Ycc""S.OY

~

Ycc =5.5V

20

~

-50

ij

~ I:G

50

/

:::::: ~

Vcc =4.5V

-

t---

-

I-

MB7l51

'00

Delay Time Increase
vs. CL Load Capacitance

Add to tEN Delay

30

;3

20

o

'00

TA• Ambient Temperature (DC)

j:

Add to tAA Delay '\

40

o

?

V
f'00

/

V

'"
--

~ ~

::-

M87151

200

300

C L• Load Capacitance (pF)

FUJITSU

10-169

I
I

0

l

'0
50

Vee =4.5V
Vee = 5.0V
Vee = 5.5V

50

0

50

~

MB7152

o
-50

- f-

l
!
j
i=
~

'0

_I.

.1.

o
-so

'00

80

~ ~~~:::~:

t--- ~
~

20

70

40

20

30

Delay Time Increase
vs. CL Load Capacitance

-1--

50

30

j

-

T A' Ambient Temperature (DC)

70

-

'00

'0

o

'00

tEN Access Time
vs. Ambient Temperature

!
~

~

i

40

MB7152

TA• Ambient Temperature (DC)

80

j

40

'0

MB11S1

MB7152

50

0

70

~

V,:;

tEN Enable Time
vs. Ambient Temperature

tOIS Disable Time
vs. Ambient Temperature
eo

J

........

~Vcc=5.5V

T A • Ambient Temparature (DC)

70

~

-

t---

~~~~:::~~ t---

o
-so

'00

80

VCC.5.5:~
Vee = 5.0V

400

..I. I.

T .... Ambiant Temperature (OC)

tOIS Disable Time
VS. Ambient Temperature

200

20

MB71S1

-50
VOH. Output High Voltage (V)

~

M87152

o

'0

o

o

v

/

tAA Access Time
vs. Ambient Temperature
60

50

/

VOL' Output Low Voltage (mY)

70

40

i: -50

-.0

30

60

i=

J

o

~

tAA Access Time
vs. Ambient Temperature

.

.....::: Vlf
~~

40

600
400
VOL' Outpullow Voltage (mV)

IOH Output High Current
vs. VOH Output High Voltage

1'E

50

200

YIN' Input Voltage (V)

T... =25°C

~

6

B71 1

-~_L'.~0~~~L-~'~.0-J~2~.0~

II

S

0

/

10

... =25°C
:c eo f- TVee
= 5.0V

M

I

- "d,.L."."
be.
1

20 - 7 " ' j ' ' ' 1

'0
o

I

.~

~
o

'00

200

-

-

~

-

MB7152

300

CL• Load Capacitance (pF)

Input/Output Circuit
Information

Input Circuit
Schottky TTL circuit technology is used in the input circuit
to achieve high-speed operation_ A PNP transistor in the
first stage of input circuit improves input high/low current
characteristics remarkably_ The
input circuit also includes a
protection diode for reliable
operation_
Open Collector Output
The open-collector output is
ollen utilized in high-speed applications where power dissipation must be minimized_
When the device is switched,
there is no current sourced
from the supply rail. Consequently, the current spike normally associated with TTL
totem-pole outputs is eliminated_ In high-frequency applications, this minimizes
noise problems (false triggering) as well as power drain_ For
example, the transient current
(lOW impedance high-level to
low impedance low-level) is
typically 30mA for the MB7152
(three-state) compared to OmA
for the MB7151 (open-collector)_
Three·State Output
A "three-state" output is a
logic element which has three
distinct output states of ZERO,
ONE and OFF (wherein OFF
represents a high-impedance
condition which can neither
sink nor source current at a
definable logic level)_ Effectively, then, the device has all the
desirable features of a totempole TTL output (e_g_, greater
noise immunity, good rise time,
line driving capacity), plus the
ability to connect to bus-organized systems_

Schottky TTL circuit technology is also used in the output
circuit to achieve high-speed
operation_ A PNP transistor is

also provided in the output circuit and is effective in decreasing a load for the chip enable
circuit.

Common Input Circuit
------------~----~---vcc

Input

Common Open Collector Output Circuit

Output

Common Three·State Output Circuit

In the case where two devices
are on at the same time, the
possibility exists that they may
be in opposite low impedance
states simultaneously; thus,
the short circuit current from
one enabled device may flow
through the other enabled
device_ While physical damage
under these conditions is
unlikely, system noise problems could result. Therefore,
the system designer should
consider these factors to ensure that this condition does
not exist.

10·170

Output

MB7151E/H
MB7152E/H/Y

Package Dimensions
Dimensions in inches
(millimeters)

2o.Pln Cerdlp Dual In·Llne Package
DIP·20C·C03

r

R.025(0.64)
REF

.284(7.21)
.302(7.67)

.940(23.88)
1.000(25.4)

qJ
=~
l~JI.~..,_. ,

.200(5.08)MAX

.120(3.05)
.150(3.81)

.050(1.27)

.900(22.86)REF

Package Dimensions
(Coniinued)
Dimensions in inches
(millimeters)

20·Pln Plastic Dual In-Line Package
DIP-20P·M01

.250(6.35)
.270(8.85)

.290(7.37)
.310(7.87)

~~~~~~~~-+
~_ _ _ _ _ _----'~E~_________.I(EJECTOR MARK)
.008(0.20)
.012(0.30)

10-171

I

Advanced Information
Availability Q4 '86

FUJITSU

Bipolar PROM
•

MB7212RA-20/-25, MB7212RS-20/-25
Schottky 256-Bit
Registered Output PROM

Features
• Organization:
32 x B-bits
• Process:
Schottky TTL
• Program:
Diffused Eutectic Aluminum
Process (DEAP)
• Output:
Three-State Output
Output register can be
initialized asynchronously
(MB7212RA) or synchronously (MB7212RS)
• Clock Access Time:
20 ns max,
(MB7212RA/R8-20)
25 ns max.
(MB7212RA/R8-25)
• Power Supply:

_

•. r-""T""7""-,--

..

(1'IiS'fs)

A,

+5V ±5%
•

Power Dissipation:
788 mW max.
• Package:
2Q-pln DIP/FPT
2Q-pad LCC

...

1IiIT.
1BCIRITa>

" ..

A, 5

Ao

6

TOP VIEW

16 eLK

00 7

15 Or

a,

1

8

9 10 11 12 13
Dl!GNDC4

a..

:zo.PAD LCC

10·172

Os

Oe

FUJITSU

Bipolar Memories
•

MB7226RA.20, MB7226RA·25, MB7226RS·20,
MB7226RS·25
Schottky 4,096-Bit Registered
Output PROM

Description
The Fujitsu MB7226 is a 4 K-bit bipolar programmable read-only
memory circuit, with registered output (output data is latched
in a register). The output register can be initialized to all Os or
all 1s, either synchronously (MB7226RS) or asynchronously
(MB7226RA). Three-state outputs can also be enabled either synchronously or asynchronously, in either model. DEAP memory cells
are used to provide fast and reliable programming.

Features
• 512 word x 8 bit PROM data
organization
• Fast clock access time:
20 ns (MB7226RAlRS-20)
25 ns (MB7226RAlRS-25)
• Output register for data
reads
• Register can be initialized to
all Os or ls.
• Register can be initialized
synchronously (MB7226RS)
or asynchronously
(MB7226RA).
• Single-supply +5V
operation
• TTL-compatible 1/0
• Fast Schottky bipolar
circuitry

• Low current inputs
• Three-state outputs
• Outputs can be enabled
either synchronously or
asynchronously.
• DEAP (diffused eutectic alu· minum process) memory
cells are reliable and easily
programmed.
• Test cells allow extensive
testing of AC. DC, and programming characteristics
before shipment.

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to
avoid application of any voltage
higher than maximum rated volt·
ages to this high impedance circuit.

10-173

LCC-28C-A01

MB7228RA.20
MB7228RA·25
MB7228RS·20
MB7228RS·25

MB7228RA Block Diagram
and Pin Assignments
A7

Ao

~

iii
II:

!!i

ID

i

MEMORY CELL
(PROM DATA)

ii!
w

"

a.
c

!l

At.

A,

lSIIliTA

A4

EA

A,

ClLRA

A.

Es(PVeE)

A,

CLK

A.
D.

Cl7
0,

0,

D.

D.

D•

GND

0,

MB7226RA Pinout

MULTIPLEXER

At.

Vee

A,

Vec(PVee)
A, A, A7 NC / At. PiiS'f.

CLRA

I'III'i'A

~4.1~.Ij..: 1 :~ijZ:i§:
1__ 1

A4 5~

;25 EA

s: l

t2~ iDA
...2~ !'s(PVc)

A3
A2 7.;

MASTER
FLlP·FLOPS

A, 8:
Ao fi
Ne

00

CLK

191

TOP VIEW

.22 CLK
~i1 NC

1J~

~9

Q7

~1J1 Q8

:-12ii3if4~f5'i6'";f71f8'
0, D. f NCD,DoD,
GND

MB7226RA LCC Pinout

Input
Output
PRSTA

CLRA

Op...tlng

mode

CLK EA ES

Remarkl

L

L

X

L

L

H

'1

L

H

X

L

L

INITIAL
DATA (H)

INITIALIZE

PROGRAMMED

L

INITIAL
DATA(L)

INITIALIZE

PROGRAMMED

PROM
DATA

LOAO
REGISTER

H

L

H

H

X

X

X

X

X

t
t
X

L
L

L

X

H

Z

CHIP
DISABLE

H

X

Z

CHIP
DISABLE

*1 When the PRSTA and CLRA Inputs are brought high at the same time, the output
CBnnot be determined either H or L.

FUJITSU
10·174

MB7226RA·20
MB7226RA·25
MB7226RS·20
MB7226RS.25

MB7226RS Block Diagram
and Pin A ••lgnm_t.

..
..

..II:

i!:

II:
C

II:

MEMORY CELL
(PROM DATA)

ii:

.

c

:>

c~

m
II:
:3c

Vee

lie

lie

A.

PRSTs

'"

EA

AI
AI

II:

Ao

A7

A,

CLK

A.

a.

00

00

Q,

Q,

Q,

00

GND

a.

MB7226RS Pinout

MULTIPLEXER

Ae

CLRs

EslPVeEl

CLRs
PRSTs

CLK
:-12ii'3if4~i5'i6;1-7~f8'
Q,

0.1

NC
GND

0.00 Q,

MB7226RS LCC Pinout

Input

iiAS'fS

CLRS

CLK

L

L

t

L

H

H

L

H

H

X

X

X

X

t
t
t
t
X

Oulput

Operating

Remark8

EA

is

L

L

L

L

INITlAL
DATA (H)

INITlALIZE

pROGRAMMED

L

INITIAL
DATA(L)

INITIALIZE

PROGRAMMED

LOAD
REGISTER

L

-

modo

-

L

L

PROM
DATA

X

H

Z

CHIP
DISABLE

H

X

Z

CHIP
DISABLE

FUJITSU
10-175

MB7226RA·20
MB7226RA·25
MB7226RS·20
MB7226RS.25

Absolute Maximum Ratings
Parameter

Symbol

Rating

Unit

Power-supply voltage

Vee

-0.5 to +7.0

V

Input voltage

VIN

-1.5to +5.5

V

Input current

liN

-20

mA

Output current

lOUT

+100

mA

Power-supply voltage
(during programming)

Vecp

-0.5 to +7.5

V

Input voltage
(during programming)

VIPRG

+22.5

V

Input current
(during programming)

IIPRG

+270

mA

Output voltage
(during programming)

VOPRG

-0.5 to +22.5

V

Output current
(during programming)

IOPRG

+150

mA

TSTG

-65 to +150

·C

Storage temperature

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Read Operations
Overvi_
During PROM reads, data is
shifted through a register, made
of master-slave flip-flops, before
appearing at the outputs. When a
new address is applied to the address inputs (Ao through As), new
data appears in the master register. At the next clock pulse this
data is transferred to the slave
register. The slave register data
appears at the three-state outputs when both chip-enable inputs are low. (Outputs are
automatically disabled during
power-up, when the inputs are in
an indeterminate state.) For synchronous operation, the ~ input
is kept low. Bringing the Es input
low will then enable the outputs
at the next clock pulse, while
bringing Es high will disable them
at the next clock pulse. For asynchronous operation, I!!e Es input
is kept low. Bringing EA low will
then immediately enable the outputs, while bringing it high will
immediately disable them.

If the ClR or PRST input is
brought low the register latch is
loaded with all Os (ClR) or allis
(PRST), rather than with PROM
data. In the MB7226RS the master register is loaded Immediately, and the contents are
transferred to the slave register
at the next clock pulse. In the
MB7226RA both the master and
slave registers are loaded
immediately.

Timing Considerations
a) PROM Data Read
After an address change, address setup time !seA) must
elapse before the master register
contains valid new PROM data.
The clock must then rise, within
address hold time tH(A), to shift
the data to the slave register.
The data will appear at the out~
puts within clock access time
tA(ClK) after the rising edge of
the clock, if the outputs had been
previously enabled.
If the outputs were disabled
when the data was shifted, and
are subsequently enabled by
bringing EA low, asyn.2hronous
chip enable time tEN(EA) must
elapse before the data appears
at the outputs.

FUJITSU
10-176

If Es is brought low to enable the
outputs, clock enable time
tEN(ClK) must elapse after the
riSing edge of the next clock.
During this time the data from the
master register is shifted to the
slave register and appears at the
outputs.
In the MB7226RA, when the registers have been initialized by
ClR or PRST, and the initialize
input is then brought high to select PROM data, asynchronous
initialize recovery time tR(ClRA)
or tR(PRSTA) must elapse before
the clock signal is applied.
b) Initial Data Read
In the MB7226RA after the ClR
or PRST input is brought low,
asynchronous initialize access
time tA(ClRA) or tA(PRSTN must
elapse before the initial data appears at the outputs.
In the MB7226RS, after the ClR
or PRST input is brought low,
synchronous initialize access
time tA(ClRs ) or tA(PRSTs) must
elapse before valid initial data
appears in the master register. It
is then shifted and output in the
same manner as PROM data.

MB7228RA·20
MB7228RA·25
MB7228RS.20
MB7228RS.2S

Ao thru Ae

Irr-r""'T'T"7'T'r-r"T'lr-rrr V,H
1.5 V

es

1'----!---'tLL""t'--+--......tL-L.l...................u.L.l....................-

V,L

V,H
1.5V

I ' - - - - - v..

r--Ttt"T,I-~1;=::;;t.J.rT1"T"t"TJ"\1n-rrT

V,H

CLK

1.5V
1~'+'-.u,,u"""',+,~~..1..1""'" V,L

VOlt
1.5V
VOL
NOTE:

'I

ClR AND PRST ARE HIGH.

Asynchronous Initial Data
Read Timing IMB7226RAI'l

Ao thru Ae
~----t--------------- V,H
1.5V
V,L

Ir"T"T"T"T"T"T"T"T"T7"T77-r- V,H

CLK

1.5V
..l.....l.....l.....l.....l.-jl......l.....l.....l....Jo..-fl.._ _ _ _'t-..............................................&..............&....&....... V,L

00 thru a.
NOTES:

__........,.........,,..;.,..................."71. ,.---....;..-....;......;.."\ , . - - - - - - - - VOH
1.5V
................................,...........~ ' - _ _ _ _ _ _ _...J , , - - - - - - - - - VOL

'I EA, Es INPUTS ARE LOW.

'2

m

OON'T CARE.

'3 two. (CLRAl, IWL(PRSTA)
'4 I.(CLRA), t,,(PRSTA)
'5 IA(CLRA), IA(PRSTA)

Synchronous Initial Data
Read Timing IMB7228RSI'l

Ao thru Ae
Ir----r---,,""T'"T"r~n"""t'""T'"T"~ V,H
1.5V

' -.......................~.....'"-'... VOL

Irr7"1~~"T-r-rIIIIr-. V,H
ClK

1.5V

~=.b~~~::::::=:::VIL

00 thru a.
NOTES:

-

..

------------...J,~------Eo INPUTS ARE lOW.
'3 ts(CLRs), Is(PRSTs)

'I EA,
'2

m

DON'T CARE.

'4 IH(CLRs),IH(PRSTs)

FUJITSU
10·177

VOlt
1.5V

,'---------VOL

MB7228RA·20
MB7228RA·2S
MB7228RS-20
MB7228RS-25

Data Read &pecHlcatlona
(Guaranteed Operating
Conditions)

Parameter

Symbol

Min

Typ

Max

Unit

Power-supply voltage

Vcc

4.75

5.0

5.25

V

Input low voltage

V1L

0

0.8

V

Input high voltage

V1H

2.0

5.5

V

Operating Temperature
TA = O"C to 75'C

AC Characterlatlca
MB7228RA/RS.20
Parameter

Symbol

Typ Min

Address setup
time

ts(A)

20

Address hold time tH(A)

-5

Clock access time tA(CLK)

16

Clock pulse width

tWH(CLK)

Max

30
0

MB7228RA/RS-25
Min

Max

Unit Remarka

35

ns

0

ns

20

25

ns

10

20

20

ns

Synchronous
enable setup time Is(Es)

5

10

15

ns

Synchronous
enable hold time

0

5

5

ns

twdCLK)

tH(Es)

Asynchronous
initialize access
time

tA(CLR A)

Asynchronous
initialize recovery
time

tR(CLR,J

Asynchronous
initialize pulse
width

twdCLR,J

Synchronous
initialize setup
time

ts(CLRs)

17

tA(PRSTA)

25

25

ns

MB7226RA

8

20

20

ns

MB7226RA

12

20

20

ns

MB7226RA

TBD TBD

TBD

ns

MB7226RS

~(CLRs)
Synchronous
initialize hold time tH(PRST )
s

TBD TBD

TBD

ns

MB7226RS

tR(PRSTA)

tWL(PRST,J

ts(pRSTsl

Cloek enable time tEN(CLK)

18

25

30

ns

Asynchronous
enable time

tEN(E,J

15

25

30

ns

Clock disable
time'2

to1s(CLK)

18

25

30

ns

Asynchronous
disable tlme'2

tols(EA)

11

25

30

ns

_ : '1 AI TA = 25'C and vce = 5.OV.
"2 Measured at a point on the output waveform O.SV from the active output level.

FUJITSU
10-178

MB7226RA·20
MB7226RA·25
MB7226R5-20
MB7226RS·25

DC Characteristics
(Under Guaranteed
Operating Conditions)

Parameter
Input current
Input clamp voltage
Output low voltage

Symbol

Condition

IIH

VIH = 5.5V

IlL
VIC
VOL

Output leakage current (Chip disabled)

Min

Typ

Max

Unit

40

p.A

VIL = 0.45V

-250

p.A

11=-18mA

-1.2

V

10l = 10 mA

0.45

V
p.A

10l = 16 mA

0.5

lOll

Vo = 0.45V

-40

p.A

10lH

Vo = 2.4V

40

p.A

-60

mA

Output high voltage"1

VOH

10H = -2.4 mA

2.4

Output short-circuit current"1

los

Vo = OV

-15

V

Power supply current

Icc

VI = Open or OV

120

170

mA

Power dissipation

Po

VI = Open or OV

600

893

mW

Note:·' Denotes guaranteed characteristics of the output hlgh-Ievef state when the chip is enabled and the programmed bit is addressed.
These characteristics cannot be tested prior to programming, but are guaranteed by factory testing.

Terminal Capacitance
(TA = 25'C, Vee = +5.0V,
VIN = +2.0V, f = 1 MHz)

Parameter

Symbol

Typ

Input terminal capacitance
Output terminal capacitance

COUT

Max

Unit

10

pF

15

pF

AC Test Conditions
INPUT CONDITIONS
Amplitude:
Rise and Fall Time:
Frequency:

LOAD CONDmON

OVto 3V
5 ns from 1V to 2V
1MHz

--.--vcc

R2

R, ..• 3000

R2 .. , soon
CL ..• 50pF

FUJITSU

10-179

MB722iRA.20
MB7228RA·25
MB7228RS·20
MB7228RS·25

Fabrication Technologll

Input/Output Circuits
The inputs use Schottky TTL circuitry to achieve a fast response
time. A PNP transistor is used in
the first stage to minimize switchIng current. Protection diodes are
also included.
The three-state outputs (high,
low; and high-impedance states)
combine the advantages of tatem-pole outputs (high noise immunity, fast rise time, ample linedriving capacity) and direct connection to bus-oriented systems.
Schottky TTL Circuitry is used for
fast operation. A PNP transistor
in the output circuit minimizes the
load on the chip enable circuitry.

Memory Celie
The memory cells In the MB7226
are of the junction-shorting type,
using DEAP (Diffused Eutectic
Aluminum Process) technology.
They are initially all In the 0 (lOW
voltage) state. In this state, the
cell's programmable element, a
PN diode, blocks current flow.
During programming, the diode's
junction is shorted, allowing it to
conduct current, and permanently
changing the cell's state to 1
(high).
By applying reverse current
pulses to the diode's cathode,
the temperature at the junction is
raised. When the temperature
reaches the point where the silicon and aluminum form a eutectic, the eutectic diffuses from the

FUJITSU
10-180

surface of the metal-silicon contact region to the anode of the
PN diode, and shorts the junction. The power dissipation at the
junction immediately drops to
less than one fifth, thus lowering
the temperature. This drop in
temperature stops further diffusion of the eutectic, and protects
the PNP transistor from
destruction.
In the memory cell array, the
word line islands are divided by
lOP (Isolation by Oxide and Polysilicon) passive isolation. Memory
cells in the same island are divided by SVG (Shallow VGroove) passive isolation. The
vertically structured memory cells
permit a high packing density.

MB7226RA·20
MB7226RA·25
MB7226RS·20
MB7226RS·25

Typical Characteristics
Curves

liN Input Current

IOH Output High Current

vs. V IN Input Voltage

vs. V OH Output High Voltage

DC Characteristics
TA = 25"C

TA = 2SOC

.-,,::::

1

'-vee = 4.5V

a:
II:

~ '/
~~~

I~ -10

,,""-

~

I

I

I

" " Vee = 4.SV

G-20

vee = 5.0VI

~

:I:

Vee = S.5V

"% -30

""

~

Vee

= 5.0V

Vee = 5.5V

~

-

J!: -40

is

--30
-1.0

~ -50

I

I

o

1.0

-60

2.0

o

V,N. INPUT VOLTAGE (V)

VOH. OUTPUT HIGH VOLTAGE (V)

IOL Output Low Current

vs. VOL Output Low Voltage
70
TA = 25°C

C

80

!iw

50

Vee = S.OV

oS

a:
a:

:::>

"0

I

V

40

/

~

....

.

30

I-

J

:::>

I-

:::>

20

/

0

~

10

o
o

V
200

400

600

VOL. OUTPUT LOW VOLTAGE (mY)

AC Characteristic
tslA) Address Setup Time

tHIA) Address Hold Time

vs. Ambient Temperature

vs. Ambient Temperature

50

!w

40

:.

..~
F

30

II>

:l
w

I!i

30

MB~228RAlRS

/CCI ve~

//t

MB7228RAIRS

I

4 5V
•
= 5.0V

20

!II
F

Vee = 4.SV

"

II

10

~

e =S.5V

i!l

20

~

"c
;t

I I

i-

'j 10

10

-20

50

100

TA. AMBIENT TEMPERATURE ('C)

FUJITSU

10-181

Vee = 5.0V. 5.5V

o

50
TA. AMBIENT TEMPERATURE ("C)

100

M87228RA·20
M87228RA.25
M87228RS·20
M87228RS.25

tAICLKI Clock Access Time
vs. Ambient Temperature

twHICLKI and IwLICLKI Clock Pulse
Width vs. Ambient Temperature

50

50
MB7226RA/RS

!

40

~

~
~"u

I

I

30

"
9
u

40

30

/ee=.4.5V

of

Ii

20

i

MB7228RA/RS

E

,vee i 4.5V
Vee = 5.OV
/ /~e=5.5V

1=

ill

.
!l

:it
of-

~i

10

Vee = S.ov

20

II/ee=5.5v
10

100

50

T .. AMBIENT TEMPERATURE rC)

tBlfsl Synchronous Enable Setup
Time vs. Ambient Temperature

ii

U
;f"
;§~

tHlfsl Synchronous Enable Hold
Time vs. Ambient Temperature
30

50

i

100

50

TA. AMBIENT TEMPERATURE rC)

M~A/RS

MB7iRA/RS

40

1

V"7 = 4.5V. 5.OV. 5.5V
30

20

II

I

10

o

/

~~f-~
Vee =5.OV
I

tee =5.5V

III I
I
o

100

50

-20

o

T •• AMBIENT TEMPERATURE ('C)

tAICLRAI and tAIPRSTAI AsynchronouB
Inltlall.e Access Time vs. Ambient
Temperature
50

100

50
T•• AMBIENT TEMPERATURE

reI

tRICLRAI and tRliiRITAI Asynchronous
Inltlall.e Recovery Time vs. Ambient
Temperature
50

MB~28RA

M~RA
I

Vee -= 4.SV

I

vee = 4.5V

11;:~==5~:

/IVe~
= s.OV
/ I
/ //ee=5.5V
I

o
o

100

50
TA. AMBIENT TEMPERATURE rC)

FUJITSU
10·182

50
T•• AMBIENT TEMPERATURE rC)

100

MB7228RA.20
MB7228RA·25
MB7228RS.20
MB7228RS·25

twLCCLRAland twdPRSTAI A.vnchronou.
Inltlall•• Pul.e Width VB. Ambient
T.mperature

.

I'"

50

50

MB7~2fJRA

I
~

So 40
w
:I
1=
w

40

li

.. -

n

c~

3D

j~

20

I,"!!j

10

li~

Vcc = 4.5V

~

30

9u

20

II

..of
50

10

o
o

100

TA. AMBIENT TEMPERATURE ('C)

100

50

TA. AMBIENT TEMPERATURE ('C)

taNCiAI A.ynchronou. Enable
Time v •• Ambl.nt T.mperature
0

~e=5.OV
/ / JCC= 5.5V

J

o
o

MB722fJRAlRS

Vee = 4.5V

,.ili

Ve~ = 5.OV. 5.5V

/

~w

!!.g
1!

tENCCLKI Clock Enabl. Tim.
v •• Ambient Temp.rature

tDlsCCLKI Clock DI.abl. Time
vs. Ambient Temperature
50

M~RS

M~RA/RS

~

So

40

w 40

.1

:I

/ /}

i,.

~cc = 5.0V

30

is

vee = 5.5V

~

/

i

0

o
o

llvee = 4.5V

1=

/'f"=4.5V

50

100

CC =5.5V

20

10

o
o

TA, AMBIENT TEMPERATURE ('C)

100

50

TA. AMBIENT TEMPERATURE ('C)
Delav Time Incr••••
v •• Load Capacltanc.

tDIICEAI A.vnchronou. DI.able
Tim. v •• Ambl.nt Temp.rature
50

Vee = 5.0V

jLt

MB~IIA/RB

MB722fJRAlRS

.l

vee = 4.5V, 5 . O V -

vee=5.~\

ADD. 10 IE. DELAY
ADD. 10 IA DELAY \

~

10

o

o

o

50

100

TA. AMBIENT TEMPERATURE rC)

FUJITSU

10-183

\ ....

\

~~

10

o

~- ~

100

50

300

CL, OUTPUT LOAD CAPACITANCE (PF)

MB7226RA·20
MB7226RA·25
MB7226RS·20
MB7226RS·25

Package Dimensions
Dimensions in inches
(millimeters)

24·Lead Ceramic ICERDIP) Dual In· Line Package
ICase No•• DIP.24C·C04)

REF

10"-15'

n

R. 025(0.64)

~

.284(7.21)
.3021"67)

1.180(29.97)
1.230(31.24)

---I

.065(1.65)MAX

H - I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

11-'.120(3.05)
.150(3.81)

.090(2.29)
.110(2.79)

~----4-----~1~.17.00(~~~.~~)~R='EF~-------~-<

.020(0.51)
.050(1.27)

.014(0.36)
.023(0.58)

24·Lead Ceramic IMetal Seal) Flat Package
ICase No_. FPT-24C·A01)

!

.250(6.35)

i
O ---1

!

_M~ " '~
'--'TT=iT~'Trii"'Ti';;=;T-rr! ·407r· )
34

Cl

.250(8.35)
62
)

~
TYP

L -II

.015(0.38)
.020(0.51)
.545(13.84)
.555(14.10)
.588(14.~)

.612(15.55)

FUJITSU
10-184

.031(0.79)

MAX

I

.907(23.04)
MIN

.280(7.11)

--.7

J1~ - : -(~-: -: . J.
.070(1.78)
.100(2.54)

MB7226RA·20
MB7226RA·25
MB7226RS-20
MB7226RS·25

28·Pad Ceramic (M.tal S.al) L.adl ••• Chip Carrl.r
(Ca •• No.: LCC·28C·A01)
.086(2.18)TYP

·PlN 1 INDEX

I
.026(Q.84)TVP
.446(11.30)
.480(11.68)

.050(1.27)TYP

.300(7.62)TYP

·Shape of PI" 1 Index: Subject to change without notice

FUJITSU

10·185

C.OI6(O.38)TVP
.05O(1.27)TYP

FUJITSU

Bipolar Memories
•

MB7232RA·20, MB7232RA.25, MB7232RS·20,
MB7232RS·25
Schottky 8,192-Bit Registered
Output PROM

Description
The Fujitsu MB7232 is an 8 K-bit bipolar programmable read-only
memory circuit, with registered output (output data is latched in a
register). The output register can be InHialized to a programmable
value, either synchronously (MB7232RS) or asynchronously
(MB7232RA). Three-state outputs can also be enabled either synchronously or asynchronously, in either mOdel. DEAP memory cells
are used to provide fast and reliable programming.

Fe.tures
•
•
•
•

•
•
•
•

1024 word x 8 bit PROM
data orgsnlZllllon
Fast clock access tlmo:
20 ns (MB7232RA1R8-20)
25 ns (MB7232RA1R8-25)
Output register can be p ....
set to a field-programmable
value
Register can be preset synchronoualy (MB7232RS) or
asynchronously
(MB7232RA)
Single +5V operation
TTL-compatlble I/O
Low current Inputs
Three-atate outputs

Outputs can be enabled
either aynchronously or
asynchronously
• Outputs ara kept disabled
on power-up
• DEAP (diffused eutectic aluminum procsas) memory
cells ara rallable and _lIy
programmed
• Teat cells allow extensive
teatlng of AC, DC, and programming characterlatlca
before ahlpment
•

This device contains circuitry to
protect: the inputs against damage
due to high static voltages or electric fields. However. it is advised
that ~ precautions be taken to
avok:l application of any voltage
higher than maximum rated voltages to this high Impedance circuit.

10-186

MB7232RA.20
MB7232RA.25
MB7232RS.20
MB7232RS·25

MB7232RA Block Dlegrem
end Pin Assignments

,.,

Vee

Aa
Aa

Aa
Aa

A.

E.

A:.

INITA

A:.

E.(PVCE )

A,

CLK

"0

0.,

0.
0,

0.
0.
0.

°3
MB7232RA Pinout

VCc(PVCC)

A. A,A7 NCL A, A.

:"4..l!.1..:1__
1 1:~'in:i':
A.

5_:

A3 8.:
A2 7'

A181

Ao

f!

TOP VIEW

NC 10·

00 {);

r12:'i3i f4":'fs'ifiifi':'i"s'i
0,0.1 NCo"o.O.
GND

MB7232RA LCC Pinout

Input
Output
INITA CLK

!A

ES

-

OperaIIng

L

X

L

L

INITIAL
DATA

INITIALIZE

H

t

L

L

PROM DATA

LDAD
REGISTER

X

t

X

H

Z

CHIP
DISABLE

X

X

H

X

Z

CHIP DISABLE

FUJITSU

10·187

Remarks

PRC).
GRAMMABLE

MB7232RA.20
MB7232RA·25
MB7232RS·20
MB7232RS.25

MB7232RS Block Diagram
and Pin Assignments
A,

Vee

As
As

A"
A"

A.

EA
INIT.

Ao

Eo(PVc.)

II:

i

CLK

"

fli
II:

I

ii!

e
I

°7

MEMORY CELL
(PROM DATA)

~

0.
0.
0.
0.

A"

MULTIPLEXER

MB7232RS Pinout

1liIIT.

VcclPVcc)
As As A7 HC LAs A.
:"'\1.!",J.,: 1 :~';i!:!!l
1.._.

TOP VIEW

i"12rf3i f4i fs'i6if71fa'
a,

Q,I NCOs0.a,
GND

MB7232RS LCC Pinout

Input
Operating
modo

Output

INITS

CLK

EA

ES

L

t

L

L

INITIAL
DATA

INllAUZE

H

t

L

L

PROM DATA

LOAD
REGISTER

X

t

X

H

Z

CHIP
DISABLE

X

X

H

X

Z

CHIP DISABLE

FUJITSU
10-188

Rem_

PROORAMMABLE

MB7232RA·20
MB7232RA·25
MB7232RS·20
MB7232RS·25

Absolute Maximum Ratings
Parameter

Symbol

Power-supply voltage

Vee

Input voHage
Input current
Output current

lOUT

+100

mA

Veep

-0.5 to +7.5

V

Power-supply voltage
(during programming)

Rating

Unit

0.5 to +7.0

V

VIN

1.5 to +5.5

V

liN

20

mA

Input voltage (during programming)

VIPRG

+22.5

V

Input current (during programming)

IIPRG

+270

mA

Output voltage (during programming)

VOPRG

Output current (during programming)

10PRG

Storage temperature

TSTG

.

0.5 to +22.5
+150
65 to +150

V
mA
°C

if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to

t~~~~r:~n::d::~: f~~~~P:iti=u;ections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

Read Operations
Overview
During PROM reads, data is
shifted through a register latch,
made of master-slave flip-flops,
before appearing at the outputs.
When a new address is applied
to the address inputs (Ao through
Ag), new data appears in the
master register. At the next clock
pulse this data is transferred to
the slave register.
Both of the chip enable inputs
must be low in order for the data
in the slave register to appear at
the outputs (00 through 0 7 ). If
the Es input is already low, bringing the asynchronous chip enable
(EAllow imm~iately e~ab!es the
outputs. With EA low, brlng,!)g the
synchronous chip enable (Es)
low enables the outputs at the
next clock pulse. Likewise, when
the outputs are enabled, bringing
either input high will cause them
to be disabled, in other words put
into a high-impedance state.
When EA is brought high, the
outputs are immediately disabled,
whereas when Es is brought
high, they are disabled after the
next clock pulse.
If the INIT input is brought low
the register latch is loaded with a
field-programmable initial value,
rather than with PROM data. In
the MB7232RS the master register is loaded immediately, and
the contents are transferred to

the slave register at the next
clock pulse. In the MB7232RA
both the master and slave registers are loaded immediately.
Timing Considerations
a) PRM Data Read
After an address change, address setup time ts(A) must
elapse before the master register
contains valid new PROM data.
The clock must then rise, within
address hold time 4i(A), to shift
the data to the slave register.
The data will appear at the outputs wHhin clock access time
tA(CLK) after the rising edge of
the clock, if the outputs had been
previously enabled.
If the outputs were disabled
when the data was shifted, and
are subsequently enabled by
bringing EA low, asynEhronous
chip enable time tEN(E A ) must
elapse before the data appears
at the outputs.
If Es is brought low to enable the
outputs, clock enable time
tEN(CLK) must elapse after the
rising edge of the next clock.
During this time the data from the
master register is shifted to the
slave register and appears at the
outputs.

FUJITSU
10-189

In the MB7232RA, when the registers have been initialized by
INIT, and INIT is then brought
high to select PROM data, asynchronous initialize recovery time
tR(INITA ) must elapse before the
clock rises to shift the new data.
b) Initial Data Read
In the MB7232RA, after the
INIT input is brought low, asynchronous initialize access time
tA(INITA) must elapse before
the initial data appears at the
outputs.
In the MB7232RS, after the INIT
input is brought low, synchronous
initialize access time tA(INITs)
must elapse before valid initial
data appears in the master register. H is then shifted and output in
the same manner as PROM
data.

MB7232RA.20
MB7232RA·2S
MB7232RS·20
MB7232RS.2S

1T"I'I'TT"T"I'I'TT"T"I""T':rrT" V,H
1.5 V

1'---f--.tt¥..LI1l---+--Lf"'J...I..L.LJ.J...I..L.LJ...J..j'-L..L.L. V,L
V..

1.5V

I ' - - - - - v..

~--Ir=~~~~~~\I~t:=:~~~~~~~~~
1.5V

CLK

~~~~~~~~. .~V..
VOIO

1.& V

VOL

NOTE: '1 INIT IS HIGH.

Asynchronous Initial Data
Read Timing (MB7232RAfl

,..-----+-------------- v

lH

1.5V
V,L

Ir-rT""T""T""r-r-r-r-r-,.....,,.....,,.....,,.....,ClK

V,H
t.5V

~~..l.....l.....l..~J....~~"-f.....~=::-~"-L-L-'-''-''-''-'"-oI"-oI;...c;...c....L....L.... V,L

NOTES: '1 EA,

E" INPUT ARE lOW.

'2 mDDN'T CARE.

Synchronous Initial Data
R.ad Timing (MB7232RSi '

Ao Ihru A. 7\.7'\.~"'\7'I~A.~"'\7'I7\.~...IJ'-------'\IJ"\1\7'1~A.7'\1\7'1~7\: ~.~ v
~~~~~~Q£~~~~~------------Jr~O£~~~~QLv..

ClK

NOTES: '1 EA, E.INPUT ARE lOW.
'2 m

DON'T CARE.

FUJITSU
10·190

MB7232RA·20
MB7232RA·25
MB7232RS·20
MB7232RS.25

Data R_d Specifications
(Under Guaranteed
Operating Conditions)

Parameter

Symbol

IIln

Typ

Max

Unit

Power-supply voltage

Vee

4.75

5.0

5.25

V

Input low voltage

V 1L

0

0.8

V

Input high voltage

V 1H

2.0

5.5

V

Operating Temperature
TA = O·C to 75·C

AC Characteristics
IIB7232RA/RS·20
Parameter

Symbol

Typ Min

Address setup
time

ts(A)

lIax

MB7232RA/RS·25
Min

20

30

35

Address hold time ~(A)

-5

0

0

Clock access time tA(CLK)

15

Clock pulse width

twH(CLK)

20

lIax

Unit

Remarks

ns
ns
25

ns

10

20

20

ns

twL(CLK)
Synchronous
enable setup time

ts(Es)

5

10

15

ns

Synchronous
enable hold time

tH(Es)

0

5

5

ns

Asynchronous
initialize access
time

tA(INIT,J

20

Asynchronous
initialize recovery
time

tR(INIT,J

11

20

Asynchronous
initialize pulse
width

twdiNITA) 13

Synchronous
initialize setup
time

ts(lNITs)

Synchronous
initialize hold time

tH(INITs )

30

30

ns

MB7232RA

20

ns

MB7232RA

20

20

ns

MB7232RA

TBD

TBD

TBD

ns

MB7232RS

TBD

TBD

TBD

ns

MB7232RS

Clock enable time tEN(CLK)

18

25

30

ns

Asynchronous
enable time

tEN(EA)

15

25

30

ns

Clock disable
time'2

to1s(CLK)

18

25

30

ns

Asynchronous
disable time'2

to1s(EA)

11

25

30

ns

Notes: -1 At TA = 25°C and Vee = 5.0V.
"2 Measured at a point on the output waveform O.SV from the active output level.

FUJITSU
10-191

MB7232RA·20
MB7232RA.25
MB7232R$.20
MB7232RS.25

DC Characteristics
(Under Guaranteed
Operating Conditions)

Parameter
Input current
Input clamp voltage
Output low voltage

Symbol

Condition

Max

Unit

IIH

VIH = 5.5V

40

/LA

IlL

V IL = 0.45V

-250

/LA

VIC

11=-18mA

-1.2

V

10L = 10 rnA

0.45

V

VOL

Min

TyP

10L = 16 rnA

0.5

/LA

lOlL

Vo = 0.45V

-40

/LA

IOIH

Vo = 2.4V

40

/LA

Output high voltage' l

V OH

IOH = -2.4 rnA

2.4

Output short-circuit current"l

los

Vo = OV

-15

-60

rnA

Power supply current

Icc

VI = Open or OV

140

185

rnA

Power dissipation

Po

VI = Open or OV

700

972

mW

Output leakage current (Chip disabled)

Note: *1

V

Denotes guaranteed characteristics of the output high-level state when the chip is enabled and the programmed bit is addressed.
These characteristics cannot be tested prior to programming, but are guaranteed by factory tasting.

Terminal Capacitance
(T A = 25"C. Vcc = +5.0V.
VIN = +2.0V. f = 1 MHz)

Parameter

Symbol

Typ

Input terminal capacitance
Output terminal capacitance

COUT

Max

Unit

10

pF

15

pF

AC Test Conditions
INPUT CONDITIONS
Amplitude:
Rise and Fall Time:
Frequency:

LOAD CONDITION

OV 10 3V
5 ns from tv 10 2V
1 MHz

--.,.....- vee

~~:::::::::::=

f'UJITSU

10-192

M87232RA·20
M87232RA.25
M87232RS·20
M87232RS·25

Fabrication Technology
Input/Output Circuits

Memory Cells

The inputs use Schottky TTL circuitry to achieve a fast response
time. A PNP transistor is used in
the first stage to minimize switching current. Protection diodes are
also included.

The memory cells in the MB7232
are of the junction-shorting type,
using DEAP (Diffused Eutectic
Aluminum Process) technology.
They are initially all in the 0 (low
vo~age) state. In this state, the
cell's programmable element, a
PN diode, blocks current flow.
During programming, the diode's
junction is shorted, allowing it to
conduct current, and permanently
changing the cell's state to 1
(high).

The three-state outputs (high,
low, and high-impedance states)
combine the advantages of totem-pole outputs (high noise immunity, fast rise time, ample linedriving capacity) and direct connection to bus-oriented system.
Schottky TTL circuitry is used for
fast operation. A PNP transistor
in the output circuit minimizes the
load on the chip enable circuitry.

By applying reverse current
pulses to the diode's cathode,
the temperature at the junction is
raised. When the temperature
reaches the point where the silicon and aluminum form a eutectic, the eutectic diffuses from the

FUJITSU

10-193

surface of the metal-silicon contact region to the anode of the
PN diode, and shorts the junction. The power dissipation at the
junction immediately drops to
less than one fifth, thus lowering
the temperature. This drop in
temperature stops further diffusion of the eutectic, and protects
the PNP transistor from
destruction.
In the memory cell array, the
word line islands are divided by
lOP (Isolation by Oxide and Polysilicon) passive isolation. Memory
cells in the same island are divided by SVG (Shallow VGroove) passive isolation. The
vertically structured memory cells
permit a high packing density.

MB7232RA·20
MB7232RA·25
MB7232RS-20
MB7232RS-25

Typical Characterl.tlc.
Curve.

liN Input Current
v •• V ,N Input Voltage

10H Output High Current
vs. V OH Output High Voltage

DC Characterl.tic.
TA = 2SOC

TA = 25'C

1

~r

r-

!".""-

.-k,V

!5 -10

§u -20

["-vee = 4.5V

v~ = 5.0~

§

vee = 5.5V

% -30

~

!:i
o

~

~

~ ~ !"-Veecc==S.DV
V

""-

4.SY

Vee = 5.SV

_

-

-40

_~-50
-30

-60

-1.0

1.0
V

2.0

o

'N' INPUT VOLTAGE (V)

1

3

4

VOH' OUPUT HIGH VOLTAGE (V)

10L Output Low Current
v •• VOL Output Low Voltage
70
TA = 25'C

:cg

60

IE

50

iii'"::>

40

~

30

!;

20

-~

10

u

..!:i

Vee = 5.0V

I

/
/

V

0

o

V

/
o

200

400

600

VOL' OUTPUT LOW VOLTAGE (mV)

AC Characterl.tlc
tslAI Addre•• Setup Time
v •• Ambient Temperature
50

I
vee

tHIAI Addre•• Hold Time
vs. Ambient Temperature
30

MB72~RA/RS

MB7226RA/RS

!

= 4.5V

I, Ve~

20

'"

:E

= 5.0V

Vee = 4.SV

1=

g

/ / /ee= 5.5V

II

10

l:

a
.
a:
c
c

Vee = 5.0V, 5.5V

I I

~-10

o

o

100

50
TA' AMBIENT TEMPERATURE rC)

FUJITSU

10·194

-20

o

50
TA' AMBIENT TEMPERATURE re)

100

MB7232RA·20
MB7232RA·25
MB7232R5-20
MB7232R5-25

tAICLKI Clock Access Time
vs. Ambient Temperature

twHICLKI and twLiCLKI Clock Pulse
Width vs. Ambient Temperature

50

50
MB7226RA/RS

I

MB7226RAlRS
W

40

W

It

..,.

u>
-'
::>

I

I Vee ~ 4.5V

:Ii

;::

lZW

.,.

30

u

9
u

20

~

10

u
u

!!.
_c

40

U

9U

C =5.0V
/ Vee = S.SV

30

~

/ Vee =,4.5V

!!.

,"

o

o

.1--

20

ji

10

Vee

g!

o
o

100

50
T., AMBIENT TEMPERATURE ("C)

.
W

tHIEsl Synchronous Enable Hold
Time vs. Ambient Temperature
30

MB~32RAlRS

MBrRAlRS

.
~

40

-'

J

I vee = 4.5 v, 5.0V, 5.5V

W

W

u>

Z

~!
UW

..

Z:Ii

20

~I=

_"'u>

If"·
1//t
Vee

10

= 5.0V

lii~
"i.o
IW-'

- 0 -10
_"':z:

ill

o
o

/

Z

~.
:z:
~

UzW

CC =5.5V

",::>

llet;

I

10

'"0

30

0

~

20

Z

Z

u>
::>

100

50
T A, AMBIENT TEMPERATURE ("C)

tslEsl Synchronous Enable Setup
Time vs. Ambient Temperature
50

= 5.0V

II (c~=5.5V

50

-20

100

T., AMBIENT TEMPERATURE rC)

o

tAIINITAI Asynchronous Initialize
Access Time vs. Ambient Temperature

tRIINITAI Asynchronous Initialize
Recovery Time vs. Ambient Temperature
50

50

MB7232RA

MB7232RA

~

I

Vee = 4.5V

!:
0::;;'

40

:z:a:
~~

30

~j::
0:>-

r

V
(,c:c: :05 5V

~a:

20

t:

10

;!;

100

50
T A' AMBIENT TEMPERATURE rC)

FUJITSU
10-195

I vee =1 4 .5V

>0

:IIlll
liC~
:f~

0

100

50
T A' AMBIENT TEMPERATURE ("C)

I

Vee 1= 5.0V

I

r;

Vee = 5.5V

50
T A' AMBIENT TEMPERATURE ("C)

100

MB7232RA·20
MB7232RA·25
MB7232RS.20
MB7232RS.25

t.N(CLK) Clock Enable Time
vs. Ambient Temperature

twL(fNI'f A) Asynchronous Initialize
Pulse Width vs. Ambient Temperature

50

50
MB7232RA

!I!
~~

S;

~~

20

~~

n
I

40

/ vie =4.5V

'"

:Ii

vee = 4.5V

30

~i

I

40

1=

vee ~ S.ov

....
'"

S!

IV~=5.5V

.

I Vee = 5.0V
30

m
u

~
g'
e

I II

10

J

50

/ //ee=5.5V

20

10

100

T A, AMBIENT TEMPERATURE rC)

tEN(E A ) Asynchronous Enable
Time vs. Ambl_t Temperature

tols(CLK) Clock Disable Time
vs. Ambient Temperature
50

50

MB7n1RAlRS

MB7:zJRAlRS

40

~I
~i

Jm

F

/ V

/

/

!

'"~

=4.5V

30
lee ==

~

5~~:v

~.

20

50

I

Vee

= B.OV

}ee = 5.5V

e

10

o

100

-Il-~

30

20

J

o

40

9u

...
:'i

10

o

100

50

TA, AMBIENT TEMPERATURE ("C)

~
~~t

MB7232RAlRS

.I

o

TA' AMBIENT TEMPERATURE ("C)

100

50
T A' AMBIENT TEMPERATURE rC)

tDls(iE A ) Asynchronous Disable
Time vs. Ambient Temperature

Delay Time Increase
va. Load Capacitance

50
MB7232RAlRS

MB72JRAlRS

.,
::I

..

I

40

.s

0

~
0:-

lit

30

Vee = 4.5 V, J o v -

~'"

~~

~~

l!!.!
~~15

vee

=5.5~~

20

'"

80

u

50

'"
1=

40

'"0:

ill
:Ii

~

10

~

ADD. to tEN DELAY
ADD. I. IA DELAY\

S 30
I!l

....... ~

10

o

o

100

50
T A' AMBIENT TEMPERATURE rC)

FUJITSU

10-196

o

\ ....
....~-

\

20

o

100

200

300

CL' OUTPUT LOAD CAPACITANCE (PF)

MB7232RA·20
MB7232RA·25
MB7232RS·20
MB7232RS·25

Package Dimensions
Dimensions in inches
(millimeters)

24-Lead Ceramic ICERDIPI Dual In· Line Package
ICa.e No.: DIP.24C-C041

n

R.02S(O.64)
REF"

~

.284(7.21)
.3021'67)

1.160(29.97)
1""'(31.24)

24·Lead Ceramic IMetal Seall Flat Package
ICa.e No.: FPT.24C·A011
.010(0.25)
MIN

I

.250(6.35)

O -l,

"-.,

~

I~'

'407(10'34)

INDEX AREA

1n'ii'i'FiF'i'FfFi'Fi'i''i'FfFi'hTer
.060(1.27)
TYP

L -J I .015~.381
.51
.020(
.545(13.84)
.555(14.10)
.588(14.84)
.612(15.55)

FUJITSU
10·197

~

MAX

~.2BOTY(7p.11)

I

nHt--~

JJJ

.004(0.10)
.007(0.18)
.070(1.78)
.100(2.54)

MB7232RA·20
MB7232RA·25
MB7232RS.20
MB7232RS.25

2a.Pad C.ramlc (M.tal Seal) Leadl ••• Chip Carrier
(Ca•• No.: LCC.28C·A01)
.08I(2.11)TVP

-PIN 1 INDEX

;C.G15(O.38)TYP

.445(11.30)
.480(11.80)

.cJ8O(1.27)TVP

.300(7.82)TYP

* Shape of Pin 1 index : Sub)ect to change without notice

FUJITSU
10-198

Advanced Informalion
Availability Q4 '86

FUJITSU

Bipolar PROM
•

MB7238RA-20/-25,MB7238RS-20/-25
Schottky 16K-Bit
Registered Output PROM

Feature.
• Organization:
2048 x B-blta
• Process:
Schottky TTL
Program:
Diffused Eutectic Aluminum
Process (DEAP)
Output:
Three-State Output
Output register can be
Initialized asynchronously
(MB7238RA) or synchronously (MB7238RS)
• Clock Access Time:
20 ns max,
(MB7238RAJR5-20)
25 ns max.
(MB7238RAJR5-25)
• Power Supply:
+5V ±5%
• Power Dissipation:
945 mW max.
• Package:
24-pln DIP/FPT and
2B-pad LCC

•
•

v"

A,
A,

(PVcd
A.

A,

A.

A.

A"

A,

(iNi'fsl

INlfA
EAlEs

A,

(PVE)

A,

elK

A,

0,

a,
a,
a,

a,
a,
a.
a,

GND

25 Alo
Aa
A2

~

6
7

A,

8

Ao

9

24 (INITs)
23 EA/~s

TOP VIEW

22
2

00 l'

19 08

~~12~13~1~4~15~1~'~1~7~16rr/
OJ Q2GNDNC 03 04 as
28-PAD Lee

10·199

6~:

21 Ne

Ne 10

07

Advanced Information
Availability Q4 '86

FUJITSU

Bipolar PROM
•

MB7242RS·20/·25
Schottky 32K-Bit
Registered Output PROM

F••tur••
• Organization:
4096 x 8-bits
• Process:
Schottky TTL
• Program:
Diffused Eutectic Aluminum
Process (DEAP)
• Output:
Three-Stete Output
Output register csn be
initialized synchronously
• Clock Access Time:
20 ns max. (MB7242RS-20)
25 ns max. (MB7242RS-25)
• Power Supply:
+5V ±5%
• Power Dissipation:
971 mW max.
• Package:
24-pln DIP/FPT and
28-pad LCC

..

V"

(PVcd

24-PIN DIPIFPT

.....,NCr ....
Vcc(PVcc)

.l..!.l...!.l..!1~

At 51
-'3

LJ

6

-'2

7

41

8

24 A11

23f~r
TOP VIEW

Au

22 elK

21 Ne

NC10

20r

00 11

18
12 13 14 15 16 17 18
Q,OtGNDNCIl3Clt Os
28-PAD Lee

10·200

25A10

Os

Application and
Technical Notes

AN-006 Fujitsu EPROMs Programming,
Erasing and Data Retention .............. 11-2
AN-008 Fujitsu Registered PROMs Offer a
New Tool for the Logic Designer .......... 11-9
Addressing Considerations When Testing the
MB8125617 ............................ 11-13
TB-001 Addressing Considerations When
Testing the MB8264 and MB8265 ......... 11-16
TB-003 Leakage and Continuity Test Considerations Using Fujitsu Microelectronics'
Single Supply DRAMs ................... 11-19

Fujitsu EPROMS
Programming, Erasing, and Data Retention
FIGURE2

INTRODUCTION

Most microprocessor based systems have long
and fluctuating development cycles. This includes
both hardware and software modifications. Software must be stored in a nonvolatile device to insure that the micro-code will not change during a
system power down period. Therefore, a nonvolatile device with easily alterable characteristics is
the most efficient media for storage in this application. Fujitsu's EPROM devices can provide the microprocessor user with just such a dependable device. Simple programming procedures, quick and
easy erasure procedures, and access times fast
enough to interface with today's popular microprocessors make Fujitsu's EPROMs ideal for
microprocessor applications. This application note
will examine the programming, erasure, and data
retention characteristics of Fujitsu's EPROMs.

MEMORY CELL THRESHOLD SHIFT

:

: PROGRAM
I

!

ERASE

VTHO
(NOT PROGRAMMED) (SENSE THRESHOLD). (PROGRAMMED)

SELECT GATE VOLTAGE (V)

This injection is accomplished by raiSing the
voltage on the select gate and drain to attract the
high energy electrons from the substrate through
the thin gate oxide region into the storage gate.
Since this storage gate is electrically isolated
(completely surrounded by silicon dioxide, Si02)
these electrons are trapped. The presence of an
electrical charge causes the threshold of the cell to
shift upward (see figure 2). This shift will not allow
the transistor to turn on when accessed. When the
cell is programmed, it is said to be programmed to
output a logic "0" when it is accessed. The status
of the cell (programmed or unprogrammed) can be
determined by testing the cell at its sense threshold voltage. This voltage is indicated by the dotted
line in figure 2. The threshold voltage of aMOS
transistor is one the most important and basic
parameters in MOS device structures. If there is
any ion surface charge contamination during
fabrication, the threshold of the cell will tend to
drift. If the contamination content becomes excessive, the threshold might drift undesirably after
extended periods of operation. Figure 3 indicates
that the Fujitsu EPROM fabrication techniques
have minimized these contamination effects.

FAMOS STACKED GATE N-CHANNEL
EPROM MEMORY CELL

4~
:

no"

I
I
I

FIGURE1

SELECT GATE

PROGRAMMED

I

DRAIN
FLOATING GATE
SOURCE

PROGRAMMING

The reliability proven FAMOS stacked gate
EPROM cell (figure 1) is used in all of Fujitsu's
EPROMs. The cell consists of the conventional
n-channel MOS transistor drain and source along
with a specialized stacked double gate construction. The top gate, also known as the select gate, is
connected to the row decoder which activates that
particular cell when it is accessed. The bottom
gate, also known as the storage gate, is where the
charge is stored when the cell has been programmed. This cell is programmed by the injection of high
energy electrons onto this storage gate.

11-2

FIGURE3

UVERASING

As stated in the previous section, the entire array
must be erased before being reprogrammed. Electrons in the conduction and valence energy bands
of the programmed storage gate will absorb photons from various light sources. These electrons
eventually become excited enough to photo-emit
from the storage gate into the surrounding oxide.
They are then swept away into the substrate or
select gate depending on the orientation of the internal electric fields. Although electrons from both
energy bands can absorb these photons, emission
out of the conduction band requires the absorbed
photons to have 3.2 eV of energy compared to 4.3
eV for the valence band. However, the rate of
photo-emission for the valence band electrons is
much higher than that of the conduction band electrons. This is due to the availability of many more
valence band electrons in the programmed gate.
A dosage of 15 watt-seconds per square centimeter (W-sec/cm2) is required to entirely erase an
EPROM array. The most commonly used source of
these high energy photons is the mercury vapor
ultraviolet lamp. Placed one inch away from the array, this source emits ultraviolet light with a
wavelength of 2537 angstroms (A), equivalent to
4.9 eV with a level of radiation intense enough
(12000 uW/cm2) to erase the entire array in approximately 15 to 20 minutes.
Light sources with wavelengths less than 4000
angstroms will eventually erase an EPROM array.
The time required to do so is dependent upon the
intensity of the source. Fluorescent light and sunlight (even after atmospheric filtering) have wavelengths short enough to eventually erase an array.

EPROM THRESHOLD DRIFT

t>.V~ I

::1------

TEST CONDITIONS: 20V. 200·C

1000

500

(HRS)

Table 1 points out the status of the control pins
for each particular device that is to be programmed. Due to the continual increase in density. the
increase in physical chip size, and a corresponding
increase in pin count, these changes in programming procedures and voltages were unavoidable.
These changes have however given the programmer a more definitive programming procedure. The
memory array should be entirely erased before programming to avoid any partial programming. A
valuable standard procedure for the user would be
to include an initial erasure period before programming the device. For detailed timing specifications
on the programming of each device, consult each
device's respective data sheet. Consult Fujitsu
Technical Brief TB-002 for a detailed 32k bit
EPROM programming hardware list for a few of the
most popular commercially available prom programmers.
TABLE 1

CONTROL PIN STATUS WHILE PROGRAMMING
Device

Vpp Vpp Location

OE

OE Location

CE

CE Location

PGM

PGM Location

MBM2716

25V

Pin 21

VIH

Pin 20

Pulsed to VIH

Pin 18

MBM2732

25V

Pin 20

Note 1

Pulsed to VIL

Pin 18

MBM2732A

21V

Pin 20

-

Note 1

Pulsed to VIL

Pin 18

-

-

MBM2764
MBM27C64

21V

Pin 1

VIH

Pin 22

VIL

Pin 20

Pulsed to VIL
(Note 2)

Pin 27

MBM27128
MBM27C128

21V

Pin 1

VIH

Pin 22

VIL

Pin 20

Pulsed to VIL
(Note 2)

Pin 27

Note 1: Vpp and OE are multiplexed on the same pin.
Note 2: The MBM27C64 PGM pulse width can be reduced to 25 msec minimum versus 45 msec for all
other devices. This is an approximate 44% savings in programming time.
Note 3: The Fujitsu Quick-pro algorithm can be used to program the 64K and 128K families of EPROMs.

11-3

Their minimum wavelengths .of - 3000 angstroms,
corresponding to 4.1 eV, are strong enough to
cause photoemlssion of electrons out of the conduction band. As discussed earlier, photoemission
of conduction band electrons is at a much lower
rate than the valence band electrons. Therefore,
this would require extended exposure times to
these sources, approximately three orders of magnitude longer than exposure to the above mentioned mercury vapor light source. However, care must
be taken to insure that arrays are not subjected to
prolonged periods of exposure to such common
sources. An opaque label may be placed on the
window of the device to block out the undersired
wavelengths. Periodic intensity measurements
should be performed on the UV source to insure
that it is continually emitting the proper intensity of
UV light.

as though the storage gate is in the relative center
of the gate region, the charge will be flowing into
the storage gate on one side and out of the storage
gate on the other side, as noted In figure 4. When
the electric fields are oriented to cause flow Into
the storage gate from the substrate, the gate will
experience an Increase in charge. These fields will
also cause the electrons to leave the gate through
the interpoly oxide onto the select gate. This will
cause the storage gate to experience a decrease in
electrical charge.
FIGURE4
CELL STRUCTURE AND CHARGE FLOW
_ _ SELECT GATE
..... INTSRPOLY OXIDE
STORAGE GATE

t

DATA RETENTION
Data retention is one characteristic that needs
to be addressed when determining the quality of
EPROMs. Since ultra-violet light is present in most
every form of light, data retention is affected during
normal use as well as when purposely erasing the
cells as in the previous UV ERASING section. In addition to accidental array erasures affecting the
data retention characteristics, numerous physics
phenomena and manufacturing defects can affect
the data retention. This section will discuss the
use of the Arrhenius relationship, the various
failure mechanisms, and three methods for
calculating the failure rates of UV erasable
EPROMs.
FAILURE MECHANISMS
Failure mechanisms cause the charge on the
storage gate to vary. The cell cross section in
figure 4 is a graphic illustration of the FAMOS
n-channel stacked gate cell used in all of Fujitsu's
EPROMs. Since each cell is in one of two states,
programmed or unprogrammed, these mechanisms
will affect the stored charge in various ways.
Therefore, the programmed and unprogrammed
states need to be discussed separately.
When the cell has been programmed, this
charge will flow either through the interpoly oxide
onto the select gate or through the thin gate oxide
into the substrate. Charge flow in either direction
will cause a reduction in trapped charge, which in
turn will reduce the threshold voltage of the cell.
Failure mechanisms also cause memory degradation when the cell has been erased or unprogrammed. Charge flow, however, will tend to flow
in one direction toward the select gate, located in
the upper most region of the cell in figure 4. Seen

W '+ '\::l

CHARGE FLOW
UNPROGRAMMED
CELL

• CHARGE FLOW
I PROGRAMMED
I CELL

GATE
OXIDE

WELL

WELL

SUBSTRATE

When the storage gate experiences a net gain In
charge, the flow through the gate oxide is said to
have been the predominant flow. This will cause a
rise in the threshold voltage of the cell. As this
threshold becomes higher, it begins to approach
the seperation threshold between the programmed
and unprogrammed states shown by the dotted
line in figure 2.
Failure mechanisms are device dependent due
to the properties of the particular memory cell. The
most common failure mechanisms that relate to
UV erasable EPROMs, their activation energies
and descriptions are listed in table 2. These
mechanisms are described in the following sections.
TABLE 2
FAILURE MECHANISMS
Activation
Energy

Failure Result

0.3eV

Infant Random
Bit Loss
Random Bit
Charge Loss or Gain
Random Bit
Charge Loss
Edge Bit Charge Loss

O.SeV
0.75 to
O.80eV
1.2eV
1.4eV

11-4

Multiple Bit
Charge Loss

Failure
Mechanism
Silicon Defects
Oxide Defects
Thermo·Chemical
Reaction
Ionic
Contamination
Wear Out From
Intrinsic Charge
Loss

OXIDE DEFECTS
The oxide defect mechanism, which is associated with a 0.6 eV activation energy, seems to ef·
fect a single bit at random in either a positive or
negative threshold shift. This failure is most often
related to manufacturing defects; and it usually occurs during the early period of the device's life
span. However, this failure is seldom seen with
Fujitsu's expertise in manufacturing techniques.

Therefore, these lower energy electrons are trapped in this gate oxide region. Since ultra-violet
erasure techniques are relatively ineffective at
removing these electrons from the oxide, repeated
programming cycles will cause a sizeable collection of electrons. This will result in a permanent
threshold shift of the cell. This threshold shift may
reduce the device's operating margin eventually
leading to device wear-out.
The actual failure rate would be determined by
summing up the contributions from all failure
mechanisms. Studies have shown that quality
EPROMs from Fujitsu and other manufacturers
can conservatively evaluated using only thermochemical reactions (0.80 ev) as failure mechanism
contributions.

SILICON DEFECTS
This failure mechanism is associated with a 0.3
eV activation energy. It manifests itself in a manner
similar to that of the oxide defect previously mentioned; but it is characterized by only a negative
threshold shift (charge loss). The trapped charge
on the storage gate can emit through these silicon
defects and scatter into other regions of the cell.

FAILURE RATES (F_R_)
THERMO-CHEMICAL REACTIONS
When no environmental or mechanical stresses
exist, the majority of failures in EPROMs can be attributed to thermo-chemical reactions. These reactions, associated with a 0.75 to 0.80 eV activation
energy, become activated primarily during high
temperature storage or data retention bakes. This
failure mechanism is also characterized by a
charge loss, resulting from thermo-emission of
electrons to and from the storage gate.

F.R. AT A SINGLE TEMPERATURE
In order to compare device quality, failure rates,
herein referred to as F.R., from competetive devices
can be used. Using a set of actual test results, a
calculation for the failure rate at a single temperature can be determined by using equation 1.
FAILURES
F.R. = - - - - - - - - - - - (equ. 1)
# OF DEVICES x HOURS TESTED

IONIC CONTAMINATION
The ionic contamination effect, associated with
a 1.0 to 1.4 eV activation energy, appears to start on
an edge bit. It then disperses throughout the array
effecting more and more bits. The ionic impurities,
which have penetrated beneath the layers of protective glass, diffuse along the storage gate connections spreading the effect. These i!llpurities
compensate (pair-up) for the electrons in the gates
which yields a net loss in charge and a corresponding drop in threshold voltage.

INTRODUCTION OF A STATISTICAL CONCEPT
The introduction of a statistical approach to this
failure rate will yield a much higher level of confidence in obtaining a failure rate value. Using the
concept that these failures are randomly distributed throughout the time frame, the "Chi-,square"
(x2) distribution analysis becomes applicable. Using the same set of actual test results with the Chisquare formula in equation 2, the adjusted failure
rate can be determined as the Mean Time Between
Failure (MTBF) for a single temperature.

INTRINSIC WEAR-OUT
Intrinisic wear-out is associated with activation
energies of 1.4 eV and greater. As previously
discussed in the PROGRAMMING section, programming is accomplished by the injection of hotenergy electrons through the gate oxide and into
the storage gate. A small percentage of these electrons may obtain enough energy to enter the gate
oxide, but not enough to proceed through it.

MTBF=----FAILURE RATE

2xT
x2

(equ.2)

where "T" is equal to the number of device
hours and "x2" can be extracted from the x2
distribution table found in table 3.

11-5

TABLE 3

CHI·SQUARE DISTRIBUTION

~
vel

d.o.f.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

48

49
50

0.10

0.20

0.0158
0.211
0.584
1.06
1.61
2.20
2.83
3.49
4.17
4.87
5.58
6.30
7.04
7.79
8.55
9.31
10.1
10.9
11.7
12.4
13.2
14.0
14.8
15.7
16.5
17.3
18.1
18.9
19.8
20.6
21.4
22.3
23.1
24.0
24.8
25.6
26.5
27.3
28.2
29.1
29.9
30.8
31.6
32.5
33.4
34.2
35.1
35.9
36.8
37.7

0.0642
0.446
1.00
1.65
2.34
3.07
3.82
4.59
5.38
6.18
6.99
7.81
8.63
9.47
10.3
11.2
12.0
12.9
13.7
14.6
15.4
16.3
17.2
18.1
18.9
19.8
20.7
21.6
22.5
23.4
24.3
25.1
26.0
26.9
27.8
28.7
29.6
30.5
31.4
32.3
33.3
34.2
35.1
36.0
36.9
37.8
38.7
39.6
40.5
41.4

0.30
0.148
0.713
1.42
2.19
3.00
3.83
4.67
5.53
6.39
7.27
8.15
9.03
9.93
10.8
11.7
12.6
13.5
14.4
15.4
16.3
17.2
18.1
19.0
19.9
20.9
21.8
22.7
23.6
24.6
25.5
26.4
27.4
28.3
29.2
30.2
31.1
32.1
33.0
33.9
34.9
35.8
36.8
37.7
38.6
39.6
40.5
41.5
42.4
43.4
44.3

0.40
0.275
1.02
1.87
2.75
3.66
4.57
5.49
6.42
7.36
8.30
9.24
10.2
11.1
12.1
13.0
14.0
14.9
15.9
16.9
17.8
18.8
19.7
20.7
21.7
22.6
23.6
24.5
25.5
26.5
27.4
28.4
29.4
30.3
31.3
32.3
33.3
34.2
35.2
36.2
37.1
38.1
39.1
40.0
41.0
42.0
43.0
43.9
44.9
45.9
46.9

0.50

0.60

0.455 0.708
1.39
1.83
2.37
2.95
4.04
3.36
5.13
4.35
6.21
5.35
7.28
6.35
7.34
8.35
9.41
8.34
9.34 10.5
10.3
11.5
11.3
12.6
13.6
12.3
14.7
13.3
14.3
15.7
15.3
16.8
17.8
16.3
18.9
17.3
18.3
19.9
21.0
19.3
22.0
20.3
23.0
21.3
24.1
22.3
25.1
23.3
26.1
24.3
25.3
27.2
28.2
26.3
29.2
27.3
30.3
28.3
31.3
29.3
32.3
30.3
31.3
33.4
34.4
32.3
35.4
33.3
36.5
34.3
35.3
37.5
38.5
36.3
39.6
37.3
40.6
38.3
41.6
39.3
42.7
40.3
43.7
41.3
44.7
42.3
45.7
43.3
44.3
46.8
47.8
45.3
46.3
48.8
49.8
47.3
50.9
48.3
49.3
51.9

11·6

0.70

0.80

0.90

0.95

1.07
2.41
3.67
4.88
6.06
7.23
8.38
9.52
10.7
11.8
12.9
14.0
15.1
16.2
17.3
18.4
19.5
20.6
21.7
22.8
23.9
24.9
26.0
27.1
28.2
29.2
30.3
31.4
32.5
33.5
34.6
35.7
36.7
37.8
38.9
39.9
41.0
42.0
43.1
44.2
45.2
46.3
47.3
48.4
49.5
50.5
51.6
52.6
53.7
54.7

1.64
3.22
4.64
5.99
7.29
8.56
9.80
11.0
12.2
13.4
14.6
15.8
17.0
18.2
19.3
20.5
21.6
22.8
23.9
25.0
26.2
27.3
28.4
29.6
30.7
31.8
32.9
34.0
35.1
36.3
37.4
38.5
39.6
40.7
41.8
42.9
44.0
45.1
46.2
47.3
48.4
49.5
50.5
51.6
52.7
53.8
54.9
56.0
57.1
58.2

2.71
4.61
6.25
7.78
9.24
10.6
12.0
13.4
14.7
16.0
17.3
18.5
19.8
21.1
22.3
23.5
24.8
26.0
27.2
28.4
29.6
30.8
32.0
33.2
34.4
35.6
36.7
37.9
39.1
40.3
41.4
42.6
43.7
44.9
46.1
47.2
48.4
49.5
50.7
51.8
52.9
54.1
55.2
56.4
57.5
58.6
59.8
60.9
62.0
63.2

3.84
5.99
7.81
9.49
11.1
12.6
14.1
15.5
16.9
18.3
19.7
21.0
22.4
23.7
25.0
26.3
27.6
28.9
30.1
31.4
32.7
33.9
35.2
36.4
37.7
38.9
40.1
41.3
42.6
43.8
45.0
46.2
47.4
48.6
49.8
51.0
52.2
53.4
54.6
55.8
56.9
58.1
59.3
60.5
61.7
62.8
64.0
65.2
66.3
67.5

0.975
5.02
7.38
9.35
11.1
12.8
14.4
16.0
17.5
19.0
20.5
21.9
23.3
24.7
26.1
27.5
28.8
30.2
31.5
32.9
34.2
35.5
36.8
38.1
39.4
40.6
41.9
43.2
44.5
45.7
47.0
48.2
49.5
50.7
52.0
53.2
54.4
55.7
56.9
58.1
59.3
60.6
61.8
63.0
64.2
65.4
66.6
67.8
69.0
70.2
71.4

0.99
6.63
9.21
11.3
13.3
15.1
16.8
18.5
20.1
21.7
23.2
24.7
26.2
27.7
29.1
30.6
32.0
33.4
34.8
36.2
37.6
38.9
40.3
41.6
43.0
44.3
45.6
47.0
48.3
49.6
50.9
52.2
53.5
54.8
56.1
57.3
58.6
59.9
61.2
62.4
63.7
65.0
66.2
67.5
66.7
70.0
71.2
72.4
73.7
74.9
76.2

Before extracting the x2 value from the table. the
level of confidence and number of degrees of
freedom need to be determined. The formula for
degrees of freedom (df) is shown in equation 3
where uf" is equal to the number of failures in the
test resu Its.
df=2f+2

FIGURES
ARHENNIUS PLOT

l

1.4ev/

I

1.oav

106

(equ.3)

O.BeV

I

Confidence levels of 60 and 90% are commonly
used by the semiconductor industry. The 60% level
is normally used with EPROMs.

/ L L

105

I...

CONVERTING AMBIENT TEMPERATURES TO
JUNCTION TEMPERATURES
The junction temperature. as seen in equation 4.
is a function of the outside ambient temperature
(TAl. maximum power dissipation of the part
(P-the product of maximum Vee and maximum
ICC). and the thermal impedance of the package
from outside the package to the junction regions
(eJAl·

II

I

V L

:::I

~

104

0.5aV

Z
0

~

.........

L

VV

J

103

(.I

II

!a!

J J

1(12

/

/

10'

The thermal impedance. e JA. is package (type
and size) dependent and approximately 56·C per
watt maximum for the 24 pin cerdip package and
51·C per watt maximum for the 28 pin cerdip
package. Thus for specific ambient temperatures.
the junction temperature can be determined. Note
that the temperatures used in this evaluation must
be junction temperatures.

/'

V/

J~ ~ ~V

•

l(;.v

/

/

(equ.4)

L

1

O~

I..-"""

JJL ~ '-"""

100

~

50
250 200175150125 100 75
JUNCTION TEMPERATURE (OC)

25

failure rate at temperature T1 by the acceleration
factor F[f(T1. T2l1. the failure rate at temperature T2
is obtained.

F.R. AT ALL TEMPERATURES USING
ACCELERATION FACTORS
Since extended life testing can become long in
duration and tediously repetitive. accelerated
testing becomes the most viable approach to
failure rate evaluation. Failure rates can be deter·
mined by subjecting the EPROMs to elevated
temperatures for comparably shorter periods of
time. One can estimate the failure rate at any
temperature by obtaining the failure rate at the
elevated test temperature (using one of the two
previous methods) and using the Arhennius plot in
figure 5 to determine the acceleration factor F[f(T1.
T2l1 = F.R. (T1) I F.R. (T2).
One can estimate the failure rate for any other
temperature (T2l by using equation 5. Dividing the

F[f(T1. T2l1 x F.R. (T2l = F.R. (T1)

(equ.5)

F.R. CALCULATION EXAMPLE
After obtaining test results from a controlled test
set-up. the previously discussed methods can be
used to determine the failure rate. The following
hypothetical test results will be used for an example:
3600 NMOS EPROMs devices were tested at
an ambient temperature of 70·C for 1000
hours. The tests performed indicated that 2 of
the devices failed some portion of the tests.

11-7

AN·006

APPLICATION NOTE
Using equation 1 with these test results will yield
a failure rate of

70·C. One must note that to keep the Junction temperature at 70·C, the outside ambient temperature
must be kept at approximately room temperature,
24·C.
Using equation 5, and the results from the Chisquare method, the failure rate at junction temperature T2 (70·C) would then be

F.R (T1) =
2 failures
=.055% per 1000 hours
.
3600 device hours
An alternate approach would be to use the Chlsquare statistical approach. Using equation 3, the
number of degrees of freedom would be equal to
df

F.R.(T2) = F·R.(T1)112
= .086% per 1000 hours/12
= .007% per 1000 hours

=2(2) + 4 =6

FUJITSU'S CHARACTERISTICS
Fujitsu entire line of EPROMs have a MTBF
value of 1.28 x 1()8 hours, which corresponds to a
failure rate of .00078% per 1000 hours. This failure
rate was determined at TA = 75 ·C, for a confidence level of 60%, and for an activation energy
of 0.75 eV (thermo-chemical reactions).
Figure 6 shows an Arhennius plot of failure rate
versus junction temperature for an activation
energy of 0.80 eV with a normalized failure rate at a
junction temperature of 70·C.

For a 60% confidence level, the X2 value would
be equal to 6.2 (extracted from table 3). Using equation 2, the test results would then yield a failure
rate of
MTBF = 2x3.6x1()6 device hours
6.2
.
= 1.16 per 1000 hours
F.R. (T1) = _1_= .086% x 1()6 hours
MTBF

FIGURE 6
FAILURE RATE vs_ JUNCTIO~ TEMPERATURE

A typical 32K EPROM in a 24-pin Cerdip package
has the following characteristics:

...

Max Vpp = 5.5 volts; Max ICC = 150 mA;
9JA = 56·CIW

1\

\

R=Ro.XP{-k~)
E.=O.8OeV -

1\

!\.

Assuming an ambient temperature TA of 70·C,
equation 4 yields a junction temperature TJ of

\

•

TJ = 70·C + (825 mW) (56 ·CIW)
= 70·C + 46.2·C
= 116·C

•

..

Using this value for TJ, EA = O.80eV and the plot
in figure 6, the failure rate for a device whose Junction temperature is kept at 116·C Is shown to be
over 12 times (8·x 10416.5 x 1()3 = F[f(T1, T2>D that of
a device whose junction temperature Is kept at

\\

-2

\
IDO 210 200

110 121 100

70

21

0

JUNCTION TEMPERATURE (OC)

11-8

-

10

FWITSU REGISTERED PROMs
OFFER A NEW mOL FOR THE lOGIC DESIGNER

FUJITSU'S OUTPUT REGISTERED PROMS
In the world of microprocessor and microcontroller design, the more common so-called "logic primatives",
often hamper the speed and efficiency of these machines. The ability to combine one or more necessary
devices onto a single I.C. enhances the performance of the resultant circuitry. In the case of Programmable
Read Only Memories (PROMs), the requirements of pipelined instruction sets call for a more flexible and
cost/space efficient method of providing the microcode instruction as required by the processor.
A PROM is a permanent memory that can be given its data "in the field", that is to say, it can be programmed
at any time after it has been manufactured. This unique characteristic makes PROMs ideal for instruction
storage for computers, processors, and other automated equipment. They make modification easy. All one
has to do in order to change some parameters is to replace the PROM with another one which incorporates
the changes desired. One of the major characteristics of standard PROMs is that the data will remain on
the output (in the read mode) only as long as the address remains unchanged. In other words, if the input
address changes, or goes away, the data on the PROM output will change as well. Under most Circumstances,
this is not a drawback. But in some applications, it is necessary to hold data on the outputs of the PROMs
while a new address is being loaded in. In the past, it has been necessary to use outboard registers with
their uncertain timing characteristics to accomplish this task. In order to accomodate this mode of operation,
Fujitsu Microelectronics has just introduced a family of PROMs which have the registers and all control inputs on the same chip. These are called Registered Proms or R-PROMs.
The Fujitsu Registered PROMs are being offered in two initial configuarations: a 4K device organized as 512
words by a-bits, and an aK device organized as a 1024 words by a-bits. Each of these devices is, in turn,
offered in either synchronous or asynchronous form.
R-PROMs are especially advantageous to designers of pipelined microprogram mabie systems because the
register which contains the instruction, during execution, is now located on the PROM chip itself. This feature offers significant advantages over conventional design methods for this type of architecture. Improvements are seen in the areas of power consumption, cycle times and board space. A further advantage to
the R-PROM is in its ability to allow for the upgrade of current systems to pipeline status without resorting
to complicated PC board changes.

THE FUJITSU REGISTERED PROMs
There are four Fujitsu registered PROMs in this current plan:
MB7226RA - 512 x a organization, asynchronous
MB7226RS - 512 x a organization, synchronous
MB7232RA - 1024 x a organization, asynchronous
MB7232RS - 1024 x a organization, synchronous

THREE STATE OUTPUTS
All Fujitsu fI-PROMs have outputs which are of the three state configuration and are compatable with the
low-power Schottky three-state bus standard. The three states are; 1 (on), 0 (off) and the "Tri-Stated" or high
impedence mode. This configuration effectively provides the device with all of the desirable features of a
totem pole TIL output. These include greater noise immunity, high source current for good line driving capability, and fast, symetrical rise and fall times.

EDGE TRIGGERED REGISTERS
The outputs of the PROM sections of the R-PROMs are loaded into the on-board a bit register on the rising
edge of the clock. It should be noted here that a 'register' contains master-slave flipflops and is different
from a 'latch' which contains gated or R-S flipflops.

SYNCHRONOUS AND ASYNCHRONOUS ENABLES
Optionally, the user may choose either synchronous or asynchronous enables. The Fujitsu R-PROMs may
be distinguished as synchronous or asynchronous by the suffix (A) for asynchronous or (S) for synchronous
on the part number. The synchronous enable option is to be chosen when multiple R·PROMs are bused
together for increased word length (such as in 16- or 32·b~ systems). When this option is chosen (see figure
one), the enables become the most Significant address bits and must be registered along with the rest of
the data word. In other words, when the clock goes high, the address is free to change. This of course requires that the enable information be stored at some location on the R·PROM.
In cases where the enable is not used, or when the PROM outputs are to be gated onto a system bus, the
synchronous enable becomes a disadvantage. In cases such as these it is advantageous for the designer
to choose the asynchronous enable option, which allows direct control of the enable function (figure two).

11·9

FWITSU REGISTERED PROMs
OFFER A NEW TOOL FOR THE LOGIC DESIGNER

..
....
....

Figure 1 Synchronous Enable

ClOCK

-=

..
....
....
..

Figure 2 Asynchronous Enable

ADDRESS

ADDRESS

PROM

PROM

C~Kf

REGISTER

..

3-STATE DRIVERS

ENABLE

-1

REGISTER

3-STATE DRIVERS

OUTPUTS

OUTPUTS

INITIAL DATA READOUT
Either of the following two types of initial data can be selected:
(1) All lows (mask programmed on the MB7226RAlS)
(2) All highs (mask programmed on the MB7226RA1S)
These options can be selected by the flNITs on the MB7232RS and the flNITa on the MB7232RA. On the
MB7226RA, the initial data option can be selected using the IClRa and the fPRSTa pins and the felRs and
fPRSTs pins are used for this purpose on the MB7226RS.
The method used to read the initial data is the same as for PROM data readout.

THE MEMORY CELL
The Fujitsu family of Registered PROMs are junction - shorting types. This means that ones are programmed
instead of zeros. A memory cell in these devices consists of a programmable element, which includes a PN
diode and a vertically connected PNP transistor. The normal current blocking stete of the reverse diode can
be biased in the programming mode to conduct current.
During programming, reverse current pulses are applied to the cathode of the PN diode increasing the temperature at the junction. When the temperature reaches a high enough point, the silicon and aluminum form
a eutectic bond (start to alloy) which diffuses from the surface of the metal-silicon contact region to the anode
of the PN diode, thus shorting the junction. As soon as the junction becomes shorted, the power dissipation
at the Junction drops rapidly along with the eutectic keeping it from diffusing further, and protects the PNP
transistor from destruction. This programming method is called the Diffused Eutectic Aiumlnum Process or
DEAp, and is the basis for all current Fujitsu PROM technology.
Each word line island in the memory cell area is divided from its neighbors by passive isolation called Isolation by Oxide and Polysilicon or lOP. Each memory on the word line island is in turn separated by a passive
isolation process called shallow V-groove or SVG. The vertical structure of the junction shorting cell makes
a high packing density possible.

11-10

~.

\
FUJIlSU REGISTERED PROMs
OFFER A NEW lOOl FOR THE LOGIC DESIGNER

PROGRAMMING PROCEDURE
Fujitsu registered PROMs are manufactured wHh the contents of all memory cells low which results in a "posHive
logical zero". 1b make the contents of a particular cell high (in other words, a one) the blocked state of the
reverse PN junction must be changed to the conducting state. This happens when the R-PROMs are
programmed.
A logical one can be permanently programmed Into a selected bit location. The bit to be programmed is selected
using the address inputs to turn on transistors 01 and Q2 (see figure three). By applying the PVCE pulse
voltage, the chip is disabled and transistor 03 is held 011. When the train of programming pulses is applied
to the appropriate output, It passes through the memory cell into transistor 01. This programming current
changes the state of the junction so that it will conduct. The pulse train stops as soon as the output voltage
indicates that the state of the selected bit has reached a logical one (1). Two additional programming pulses
are applied to ensure that the element has been programmed properly.
Each memory cell has to be programmed individually because the Internal decoding circuH can sink the
programming current of only one bit at a time.

PROGRAMMING INITIAL DATA
On the MB7232RA and the MB7232RS (1024 x 8) Fujitsu Registered PROMs, the Initial data can be programmed
by the user. The memory cells which comprise the Initial data portion of the R-PROM are fabricated as logical zeros at the factory in addition to the rest of the PROM memory celis. Ones can be programmed by selecting
the Initial data cells through applying a logical zero signal to the initialize-input pin (/INIl) and applying programming current pulses to the output terminals (00 through Q7) as directed In on the initial data programming
chart shown In figure four.

Figure 3 Programming Circuit of Fujitsu R·PROMs

...

...

...
A.

EslPYCEI

eA

o-!:===~

Figure 4 Programming Chart for R·PROMs

. '"
PVc,

H:
L:
)C:

PVce:

,"OM"'"

HtghI_1
Low level
Oon~ CIte

20V

%:
t:

High impedMCe

"I:

II an H I_I II ctllrIQ8d 111M Nmillmi PASTNC~ '1npuI,1tI,0000uto.nnOIbitdlllermlllld(eltherHorL).

Rilinged\JI

11-11

FUJITSU REGISTERED PROMs
OFFER A NEW mOL FOR THE lOGIC DESIGNER

PIPELINED MICROPROGRAMMABLE SYSTEMS
Microprogrammed processors and controllers are generally either pipelined or non-pipelined. The difference
between these two types of systems is that in the non-pipelined system the "instruction fetch" command
is not given until the processor is ready to accept it and in a pipelined system, the instruction fetch for the
next instruction is given while the previous instruction is being executed. Therefore, the pipelined approach
is much faster than non-pipelined because the microcyle of the pipelined system is defined by the length
of either the fetch or execution time and not by the sum o! both as in a non-pipelined arrangement. This
improvement in speed can be as great as 2:1 depending on the microprocessor used, the location of the
registers used to hold the next instruction, and the length of the fetch and execution cycles. The testest time,
o! course, is when fetch and execution times are equal. Any gain in cycle time is lost, however, when a branch
circuit requires the look-ahead fetch to be discarded. A typical pipelined microprogrammed system is shown
in figure five.

BENEFITS OF REGISTERED PROMS IN PIPELINED SYSTEMS
As can be seen, the R-PROM is ideal for use in pipelined microprogram mabie systems. The major advantages are:
• Faster Cycle Times
• Lower Parts Count For Simplified Board Layout
• Lower Power Consumption

STATE MACHINES AND OTHER STRUCTURED LOGIC CIRCUITS
Fujitsu R-PROMs can be used as basic logic circuits which, when used in conjunction with other basic logic
building blocks can define a number of structured logic architectures.
One of the most basic logic circuits possible with the R-PROM is a state machine. As shown in figure six,
such a sequencer is formed by feeding the outputs of the register back into the address inputs. The resultant
state machine will then sequence from one state to the next as defined by the present state as it appears
on the register outputs, and the address inputs which contain both the present state information as well as
the inputs from outside.
Powerful microprogrammer sequencers can be constructed using the R-PROM as a state machine in conjunction with other memory elements and logic elements.
The example applications contained in this note demonstrate that Fujitsu Registered PROMs offer the logic
designer a new tool in the field of computer and processor architecture.

Figure 5

<

Typical Pipelined Microprogrammable System

~>

DATA BUS

D

B

Figure 6 State Machine Using R-PROM
SEQUENCE ADDRESS

SEQUENCER
BRANCH
ADDRESS

~

~

PROM
MICRO
PROGRAM
PROM

----REG

MICROCONTROLS

11-12

ADDRESSING CONSIDERATIONS
WHEN TESTING THE MB81256/7

ADDRESSING CONSIDERATIONS WHEN TESTING THE MB8125817
To properly test a random access memory a detailed description of the internal topology and
address decoding of the device is required in order to run complex disturb petterns and to optimize
testing procedures. This applications note supplies sufficient addressing information to properly
test the MB81256 (page mode) and MB812S7 (nibble mode).
ADDRESS SCRAMBLING
It is often necessary to access a particular memory cell location when testing the MB8125617.
However, the internal addresses corresponding to the actual physical memory cell locations are
different from the addresses applied to the external address pins of the device. The address
scrambler converts the logical or external address to the internal or physical address corresponding
to the physical memory location (Fig 1). To determine the actual internal address, a transformation
must be made jn accordance with the follOWing logic diagram and equations as shown in fig 2
and fig 3. This address, when converted to decimal, can then be physically located on the die
using the internal bit topology diagram (Fig 4).

Figure 1. Address Scrambling
RAO

co

to

to and to

,--_ _-,CAB

'--_ _---' CB

RS

(Physical Address)

(Logical Address)

Figure 2.

Figure 3. Addre.. Scramble Equations

AODRESS DESCRAMBLER

AA,

RO

-----ID-,.
D-"
D-',
D-"
D-"
D-"'
D-"

-1-+---+--- "

-t+--+--- "
-++---+----~

DATA TOPOLOGY

11·13

RD
R1
R2
R3
R4
RS
R6
R7
~8

CD
C1
C2
C3
C4
CS
C6

'"'
=
=
=
..
=
..
=
..

RAD
RA1
RA2
RA3
RA4
RAS
RA6
RA7
RA8

EOR
EOR
EOR
EOR
EOR
EOR
EOR

RA2
RA2
RA7
RA7
RA7
RA7
RA7

EOR CAD

= RA8
=
=
=
..

CA2
CA3
CA4
CAS
CA6
= CA7
C7 .. CAS
C8 = (RA8 and CAD)
EOR CA1
RN and CA: Internal physical address
RAN and CAN: Pattern generator address
(external logical address)
EOR: Exclusive OR Gate

ADDRESSING CONSIDERATIONS
WHEN TESTING THE MB8125617

Example of address scrambling,
Logical address (by pattern generator);
RAO

RA1

o

AA2
0

AA3

AA4
0

AAS

AA6 RA7 AAS CAO
0100

CA1

CA2
0

CA3

CA4
0

CAS

CAS
0

CA7

CAB
0

Address Scrambler

Physical Address (to the memory array)

AO
0

A1

I

A2

A3
0

A4

AS
0

A6

A7
1

I

AS
0

CO
0

C1
0

C2

C3
0

C4

C5
0

C6

C7
0

CS

,

C2

C3

C4

C5

C6

C7

CS

C9

C1

CO

C:338 (Decimal)

R:214 (Decimal)

This address (R:214 and C:338) Is location "X" In the Internal bit topology shown In

Fig. 4.
Figure 4. Internal Bit Topology

RO,C512

• RO,C1023
CELL ARRAY

SENSE AMP.
CELL ARRAY
R255,C512

R255,C 1023
R255,C511

R255,CO
CELL ARRAY X
SENSE AMP.

.RO,C511

RO,CO

11-14

,

ADDRESSING CONSIDERATIONS
WHEN TESTING THE MB81256/7

MB81256/MB81257 Bit Map (Lower 128k)

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Addressing Considerations When
Testing the MB8264 and MB8265
This inversion is automatically done by internal
circuitry so it is transparent to the user. If it is
necessary to write all bits to the same internal
state, the data transformation in Figure 4 must
be observed. To understand topologically which
quadrants store same polarity data and which
store inverted polarity data, refer to Figure 6.

To properly test a random access memory reo
quires a detailed description of the internal topol·
ogy and address decoding of the device in order to
properly run complex disturb patterns and to opti·
mlze testing procedures. This note will supply this
Information for the MB8264 and MB8265, 64K·bit
dynamic RAMs.
Since the design of this product is quite com·
plex, four separate considerations must be made
when determining bit topology:

BIT TOPOLOGY
Optimum design strategies resulted in the ac·
tual bit topology as presented in Figure 5. Note
that the cells of the M 88264 and M 88265 are laid
out in pairs, one on each side of the column, or
bit line. This topology layout as well as the address decoding must be taken into consideration, especially when running disturb patterns
designed to check for bit to bit shorts, leakage,
or crosstalk.

ADDRESS TOPOLOGY
The address pins were labeled on the MB8264
and MB8265 data sheets for marketing conve·
nience and do not correspond to the actual inter·
nal address designations. To determine the ac·
tualinternal address, a transformation must be
made in accordance with Figure 1.
Any further references in this paper refer to ac·
tual internal MB8264 and MB8265 addresses,
not data sheet labeling.
DECODING TOPOLOGY
Optimizing row and column decoder layouts reo
suited in a scrambling of the addressing se·
quence. This scrambling must be taken into con·
sideration If bits are to be addressed in a topolog·
Ical sequential manner. A logic diagram is supplied in Figure 2 to decode this scrambling.
Figure 2 gives the resulting descrambled ad·
dresses In terms of row (Rn) and column (Cn)
addresses. By multiplexing the row and column
addresses, Rn is produced from An at RAS time
and Cn is produced during CAS time. For compar·
ison, a bit map Is supplied in Figure 3 showing
the addressing scheme before descrambling.

To understand the actual physical arrangement
of the MB8264 and MB8265, Figure 6 is pre·
sented to relate the array orientation to the input
pad orientation on the actual chip.
FIGURE 1
TRANSFORMATION FROM DATA SHEET
ADDRESS NOTATION TO ACTUAL
MB8264/MB8265 INTERNAL ADDRESSES
PIN
NUMBER
13
12
11
5
6

DATA POLARITY
Since balanced sense amplifiers are used, posi·
tioned between rows 6310 and 6410, and 19110
and 19210 of the matrix, this requires that the
data on one side of the sense amplifiers be
stored at an inverted polarity from the other side.

7
10
9

11·16

DATA
SHEET
LA8EL

ACtUAL
INTERNAL
ADDREsS

As

AO
A1
A2
A3

A3
A4
Ao
A2
A1
As
A7

AI.
AS

As
A7

FIGURE 2

FIGURE4

EXTERNAL ADDRESSING TRANSFORMATION
REQUIRED TO DESCRAMBLE INTERNAL
ADDRESSING SEQUENCE

EXTERNAL DATA TRANSFORMATION TO
DECODE THE INTERNAL DATA INVERSION OF
THE MB8264/MB8265

D--RO

AD
A1

D--.,

A'

D--R'

A3

D--R3

A.

D--R.

DA::

===j D--

DIN

(ROW ADDRESS)
.OW
ADDRESSES

NOTE: The same transformation is required on the data out
pin when verifying data written with the above transforma·
tion.

D--.S

ADDRESS
INPUTS

A6

D-- ..

A7

.7

~O

AD
A1

DOUl

DATA

(ROW ADDRESS)

C1

A'

---iD-

A6~

CO

C'

A3

C3

A.

C.

AS

CS

COLUMN

ADDRESSES

A.

C.

A7

C7

=l

u.x:-OR

NOTE: The above logic symbol logic symbol is used solely
to represent Ihe "exclusive or" function and is not a suggested implementalion of logic.

---t>o-.oT

NOTE: The above logic symbols are used solely to represent
"exclusive or" and "not" functions, and are not a suggested implementation of logic.

FIGURE3
MB8264 and MB8265 BIT MAP SHOWING INTERNAL ADDRESS SCRAMBLING

11111111

.'
".
" ..
....
.....
.

+

111111

A,11

"-1

,,

,
,

00 ,00

11-17

1

1

1

1

1

1

1

ODD

(I

0

0

(I

II

...
000

TB·OOI
TECHNICAL BRIEF
FIGURE 5

FIGURE 6
CHIP ARCHITECTURE OF THE
MB8264 and MB8265

INTERNAL BIT TOPOLOGY OF THE
MB8264 and MB8265

...

TO SENSE AMPLIFIERS

co

C1

A,

C2

Dour

' " R128
CO

··s"

R128/
C255

CAS
Vss

S.A.fCOLUMN DECODER

R255
/CO

IMB8265

Onlyl

I'R127
CO

"'"
"1"

R255
C255"

R127

'"4
's

"

;t

C255

[3---+- Vee

S.A.ICOLUMN DECODER

RO
/CO

"5"

RO
C255"

."'2

NOTE: "S" - Same polarity as DIN
"I" - Inverted polarity from DIN
NOTE: Address labeling reflects data sheet notation, not
actual Internal addressing. Corners are labeled above in
transformed column and row notation.

11·18

Leakage and Continuity Test Considerations
Using Fujitsu's Single Supply DRAMs
that the device be actively biased to insure proper operation of the IPC. The proper test conditions recommended
are a!L!Qllows: Vee = 5.5V, RAS = CAS = OV (except
when RAS/CAS pins are under test), all other pins are left
open. The test is conducted by forCing a 11'A current
through the pin and measuring the voltage impressed
across the pin. If the voltage across the pin is less than
7V, continuity on that pin can be guaranteed. If a voltage
of greater than 7V is detected, the pin has a continuity
problem.

INPUT PROTECTION CIRCUIT
When electrostatic discharge (ESD) is induced on the
pin of an integrated circuit, voltages in the KV range can
occur. This can cause gate breakdown of an unprotected
MOS structure. If this breakdown occurs, the gate of the
input transistor may be shorted and a heavy current will
flow through the pin. Therefore, precautions against electrostatic breakdown of the gate are important. All the inputs of Fujitsu's single supply DRAMs have an ingenious
Input Protection Circuit (IPC) (see Figure 1) that isolates
the internal chip circuitry from damage caused by electrostatic discharge generated by normal handling procedures. In order to provide adequate protection for the
device, the IPC provides two separate low impedance
paths to Vss for static charge to traverse. The threshold
circuit A is activated if a voltage of 12V or greater is
detected between the pin and Vss. This provides a path to
VSS for the charge to travel. When no power is applied, a
transistor contained within circuit B provides the second
low impedance path to Vss. At normal bias, this shunt
transistor is clamped off by Vee. Normal operating
parameters are not affected by the IPC in any way.

TESTING THE IPC FOR
ELECTROSTATIC PROTECTION
Testing for ESD protection is accomplished by charging a capacitor of 100pF to a specified voltage, then
discharging it through a 1.5K ohm load into an input (see
figure 2). This test method is consistent with the ESD protection test procedure described in MIL STD 883B
Method 3015.1. The voltage impressed on the input pin
should not exceed 600V or else the reliability of the
device may be affected.
FIGURE 2

FIGURE 1
IPC BLOCK DIAGRAM

.:. Vss

.----L----,CHARGE

TEST CIRCUIT

1

~ ~N=pXU~
,,.,,

INPUT
PAD

INPUT CAPACITANCE
The input capacitance of the various inputs of Fujitsu's
64K DRAMs have been measured and the results are
summarized in table 1.
INPUT LEAKAGE MEASUREMENTS
As described above, Fujitsu implements an input protection circuit to guard against electrostatic breakdown
of the input transistor on the input pin and protect the interior from surge voltages. However, the way the IPC was
designed necessitates that power be applied during
leakage and continuity tests. Once a static bias is attained, leakage measurements can be taken by the usual
methods. First, all input pins not under test should be tied
to OV. The supply voltage, Vee, should be set to 5.5V for a
worst case test. The input leakage current can be
measured by impressing a voltage (V,N) between OV and
5.5V. Normal leakage currents will be between -10 and
+10 microamps. If a larger leakage current is detected,
the device has a leakage problem.

Test conditions: Vee = SV, Vss = OV, Pins not under
test should be set to 2.0V.lnstrument: Bontoon meter @
1Mhz.

CONTINUITY MEASUREMENTS
Previous generations of integrated circuits used continuity measurement techniques that involved forward
biasing an equivalent diode structure that usually existed
between the input and the substrate. However, to accurately test Fujitsu's Single supply DRAMs it is required

DATA OUTPUT CIRCUIT
When making leakage mearurements on the data output pin it is necessary to insure that both of the output
transistors are off. This is done simply by insuring that
~ is in the normal operating range and that the level of
CAS is above 2.4V (V, H).

TABLE 1
TYPICAL INPUT CAPACITANCE OF MB8264/65
Input

Typical Value

Spec_ Value

AO
A1-A7
D,N

3.5pF
2.SpF
2.6pF
3.7pF
4.SpF
3.8pF

5pF
SpF
SpF
8pF
8pF
8pF

FiAS
CAS
WE

11·19

Ordering
Information

Ordering Information

L

MB 8284-15 Z

PACKAGE
C-CERAMIC
P-PLASTIC
Z·CERDIP
PERFORMANCE VARIATIONS (WHEN USED)
E. H·OR DASH NUMBERS DENOTE ACCESS TIME VARIATIONS
L-DENOTES LOW POWER

' - - - - - DEVICE TYPE
' - - - - - - MANUFACTURER DESIGNATOR
MB·DEVICE TYPE IS FUJITSU INTERNAL NUMBER
MBM·DEVICE TYPE IS INDUSTRY STANDARD MEMORY NUMBER

12-2

•

•

Headquarters Locations

World Headquarters

U.S.A. Headquarters

European Headquarters

Fujitsu Limited
Furukawa Sogo Bldg., 6-1
Marunouchl 2-chrome, Chlyoda-ku
Tokyo 100, Japan
Phone National (03) 216-3211
International (Int'l Prefix)
81-3-216-3211
Telex: 2224361 FT TOR J

Fujitsu Microelectronics, Inc.
3320 Scott Blvd.
Santa Clara, Ca. 95054-3197
Phone: (408) 727-1700
Telex: (910) 338-0190
FUJITSU SNTA

Fujitsu Mlkroelektronlk GmbH
Arabella Center 9, OG./A
Lyoner Strabe 44-48 0-6000
Frankfurt 71, F.R. Germany
Phone: 069/66 320
Telex: 0411 963

Sales Office Locations - USA

HEADQUARTERS
FujitSu Microelectronics. Inc.
3320 Scott Boulevard
Santa Clara, CA 95054-3197
(408) 727-1700
TWX: 910-338-0190

ATLANTA
Fuj"su Microelectronics. Inc.
3169 Holcomb Bridge
SUite 506
Norcross, GA 30071
(404) 449-8539

DALLAS
FujitSu Microelectronics. Inc.
1101 East Arapaho Road
Suits 225
Richardson, TX 75081
(214) 669-1616

NORTHERN CALIFORNIA

BOSTON

HOUSTON

Fujitsu Microelectronics, Inc.
595 Millich Drive
Suite 210
Campbell, CA 95008
(408) 866-5600

Fuj"su Microelectronics, Inc.
57 WellS .....enue
Newton Centre, MA 02159
(617) 964-7080

Fujitsu Microelectronics, Inc.
10550 W. Office Drive
Su"e 102
Houston, TX 77042
(713) 784-7111

SOUTHERN CALIFORNIA
Fujitsu Microelectronics. Inc.
840 Newport Center Drive
Suite 460
Newport Beach, CA 92660
(714) 720-9668

FujitSu Microelectronics, Inc.
1501 Woodfield Road
Su"e 202, South Bldg. IV
Schaumburg, IL 60195
(312) 665-1500
TWX: 910-667-7378

FUJITSU

CHICAGO

MINNEAPOLIS
Fuj"su Microelectronics, Inc.
3460 Washington .....enue
Eagan, MN 55122
(612) 454-0323
NEW YORK
Fuj"su Microelectronics, Inc.
601 Veterans Memorial Highway - - - - - " " " - - ' - . . . .
Hauppauge, NY 11788
(516) 361-6565
TWX: 510-227-1049

1. (408) 886-5800
2. (714) 7»8888

3. (214) 889-1616
4. (312) .5-1500
5. (617) 1184-7080

•

•

Sales Office Locations

Europe

United Kingdom

North Germany

SOuth Germany

Fujitsu Microelectronics Ltd.
Hargrave House
Belmont Road
Maidenhead
Berkshire SL6 6NE
Phone: (06 28) 7 6100
Telex: 848955

Fujitsu Mlkroelektronlk GmbH
Lyoner Strasse 44-48
Arabella Center 9 .0<31A
0-6000 Frankfurt-Nlederrad 71
Phone: (0 69) 6 63 20
Telex: 411 963
Fax: (0 611) 6 63 21 22

FUJitsu Mlkroelektronlk GmbH
Arbeostras.. 5
0-8057 Echlng bel Muenohen
Phone: (089) 3 1910 15
Telex: 5 213 905

Soandlnavla

Italy

Francs

Fujitsu Microelectronics Ltd.
Industrlgaten 2A. plan 7
S-112 46 Stockholm. Sweden
Phone: 8 785 00 67/68
Telex: 13411 FNAB
Fax: 8531634

Fujitsu Mlkroelektronlk
Centro Olrezlonale Mllanoflorl
Palazzo A2
20090 Assago - Milano

Fujitsu Mlkroelektronlk
Bureau de Walson
Tour Roany II
93118 Rosny Soua Bois Cedex
Phone: (1) 48 55 1646
Telex: 2 31 684

Representatives - Europe
Austria
Atel Electronics
Eltnergasse 6
1232 Wlan
Phone: (222) 86 15 31
Telex: 112344

France

Norway

United KIngdom

ERN
237 rue de Faumy
Z.A. Buc
78630 Bue
Phone: (33) 96600 11

Ambar Component. Ltd.
Rabana Close
Aylasbwy Bucks

Belgium

Odin Elt\ictronles AS
EDV Grleg.veI 2
1472 FJalihamar
P:O. Bcx 72
Phone: (02) 70 37 30
Telex: 19732

Mlcrorarn
6. rau Ie Corbusler
Sille 424
94583 Rungls Cedex
Phone: (1) 6868170
Telex: 206962

ERIAT SA
International S.A.
Rue de Fralslers 89
4410 Herstal-Vottem
Phon.: (41) 27 42 83
Telex: 41 782

Denmark
Nordlsk Elektronlk AS
TransformerveJ 17
2370 Herlev
Phone: (02) 84 20 00
Telex: 35 200

Germany
MHV Mlerohalblelter GmbH
Jaegerweg 10
80120ttobrunn
Phone: (0 89) 8 06 60 68
Telex: 5 213 807

Netherlands
Finland
Gadallus OY
Kauplntle 18
00440 Helsinki
Phon.: (80) 5 826844
Telex: 121274
OYComdaxAB
Itaelahderkato 23A
00210 Helsinki 21
Phone: (90) 0 67 02 77
Telex: 125876

FUJITSU

P & T Electronic. Int. B. V.
Esse Baan 77
P.O. Box 329
2900 W Capelle AID IJ....I
Phone: (31) 1050 1444
T.lex: 26 096
Mlcrotronlca
Kasp d. Goade Hooplaan II
3526 AR Utrecht
Phone: (0 30) 88 00 84
Telex: 40 744

HP leaRS
Phone: (02 98) 341 41
Hawke

Sweden
Naxab
P.O. Bcx4115
17104 Solna
Phone: (OS) 98 5140
Telex: 17 912

Switzerland
EIJapexAG
Hardstruse 72
6430 WBttlngan
Phone: (0 56) 26 30 52
Telex: 68 068

Spain
Dloda
Edlflclo iberia Mart
Avda. de Brasil 6
Madrid 20
Phona: (1) 4553888
Telex: 42 148
Litton Pnscl.lon
Condas del Val a
28030 Madrid
Phcna: (1) 250 15 07
Talex: 44 730

AmotaxHcu..
45 Ha_h Road
SUnbury
Mldox
TW18SDA
Phona: 19 79 77 98
Telex: 1123592

•

Representatives - USA
Alabama

illinois

New York

Canada

The Novus Group, Inc.
14005 Coy's Drive
Huntsville, AL 35803
(205) 881-2207

Beta Technology
510 Mitchell Road
Glendale HeIghts, IL 60139
(312) 790-9886

Quality Components
116 Fayette Street
Manlius, NY 13104
(315) 682-8885

Great Northern Technology
3700 Gilmore Way
Suite 425
Burnaby, BC V5G 4M1

Quality Components
3343 Harlem Road
Buffalo, NY 14225
(716) 837-5430

PIpe Thompson LImited
5468 Dundas Street W.
Suite 206
Islington, Ontario M9B 6E3
(416) 236-2355

Arizona

Indiana

Thorn Luke Sales
2940 North 67th PI ace
Suite H
Scottsdale, AZ 85251
(602) 941-1901

Fred A. Dorsey and AssocIates
6525 East 82nd Street
Suite 112
IndIanapolis, IN 46250
(317) 842-0060

California

Kansas

Harvey King, Inc.

Kebco, Inc.
10111 Santa Fe DrIve
Suite 18
Overland Park, KS 66212
(913) 541-8431

6393 Nancy Ridge Drive
San Diego, CA 92121
(619) 587-9300
HI-Tech Rep Company
31332 Via Collnas
Suite 109
Westlake Village, CA 91362
(818) 706-2916
HI-Tech Rep Company
1111 Laguna Road
Suite 108
Tustin, CA 92680
(714) 730-9561
Norcomp, Inc.
2975 Scott Blvd.
Santa Clara, CA 95054
(408) 727-7707

Massachusetts
Mill-Bern AssocIates
120 Cambridge Street
SuIte 8
Burlington, MA 01803
(617) 273-1313

Maryland
Component Sales
106 Old Court Road
Suite 204
Baltimore, MD 21208
(301) 484-3647

Michigan
Florida
Semtronlc Associates, Inc.
657 Maitland Avenue
Altamonte Springs, FL 32701
(305) 831-8233
Semtronic Associates, Inc.
1467 S. Missouri Avenue
Clearwater, FL 33516
(813) 461-4675

Semtronic Associates, Inc.
3471 N. W. 55th Street
Ft. Lauderdale, FL 33309
(305) 731-2484

Georgia
The Novus Group, Inc.
4556 Canda Drive
LIlburn, GA 30247
(404) 381-1015

Iowa
Electromec Sales
1500 2nd Avenue
Suite 205
Cedar Rapids, IA 52403
(319) 362-6413

Idaho
Cascade Components
2419 W. State Street
Suite 10
Boise, 10 83702
(208) 343-9886

AP Associates
225 E. Grand River
P.O. Box 777
Brighton, MI 48116
(313) 229-6550

Technical ApplIcations Marketing
1757 Veterans MemorIal Highway
SuIte 408
South Hauppauge, NY 11722
(516) 348-0800

Ohio
Bear MarketIng
3623 Brecksville Road
P.O. Box 427
Richfield, OH 44286
(216) 659-3131
Bear MarketIng
1563 E. Dorothy Lane
Suite 104
KetterIng, OH 45429
(513) 229-5877

Oklahoma
Genzel Sales Associates
4135 South 100 East Avenue
Suite 101
Tulsa, OK 74146
(918) 622-7744

Oregon
L-Squared Limited
4540 S. W. Hall Blvd
Beaverton, OR 97005
(503) 644-8555

Minnesota
Electromec Sales
101 W. Burnsville Parkway
Suite 100
Burnsville, MN 55337
(612) 894-8200

Missouri
Kebco, Inc.
75 WorthIngton DrIve
Maryland Heights, MO 63043
(314) 576-4111

North Carolina
The Novus Group, Inc.
4234 Bertram DrIve
Raleigh, NC 27604
(919) 872-3966

New Jersey
BGR AssocIates
Evesham Commons
525 Route 73, Ste 100
Marlton, NJ 08053
(609) 983-1020
TechnIcal ApplIcations MarketIng
2 Ridgedale Avenue
Suite 370
Cedar Knolls, NJ 07927
(201) 285-9094

Texas
Technical Marketing, Inc.
3320 Wiley Post Road
Carrollton, TX 75006
Technical Marketing, Inc.
9027 Northgate Blvd.
SUite 140
Austin, TX 78758
TechnIcal Marketing, Inc.
2901 Wllcrest Drive
Suite 139
Houston, TX 77042

Utah
Front Range Marketing
2520 S. State Street
Suite 117
Salt Lake City, UT 84115
(801) 364-6481

Washington
L-Squared LImited
10502 RIviera Place, NE
Seattle, WA 98125
(206) 526-0641

Wisconsin
Beta Technology

9401 Beloit Street
Suite 304C
Milwaukee, WI 53227
(414) 543-6609

FUJITSU

PIpe Thompson LImited
RR2 North Gower
Ottawa, Ontario KOA 2TO
(613) 258-4067
Pipe Thompson LImited
769 Madeleine Street
Laval, Quebec H7P 3W6
(514) 628-1393

Puerto Rico
Rep 1092
Eastern Airlines Building
Suite 501
Santurce, Puerto Rico 00911
(809) 722-6942

•

Distributors - USA
Alabama
Marshall industries

3313 S. Memorial Highway
Suite 121
Huntsville, AL 35801
(205) 881-9235

Arizona
Cetec Electronics
3617 N. 35th Avenue
Phoenix, AZ 85017
(602) 272-7951
Marshall Industries
835 W. 22nd Street
Tempe, AZ 85281
(602) 968-6181
Western Mlcrotechnology

Marshall Industries
336 Las Coches Street
Milpitas, CA 95035
(408) ~600
Marshall Industries
10105 Carroll Canyon Road
San Diego, CA 92131
(619) 578-9600
Time Electronics
1339 Moffett Park Drive
Sunnyvale, CA 84086
(408) 734-9SS8
Time Electronics
9751 Independence Ave.
Chatsworth, CA 91311
(818) 998-7200

7848 E. Redfield Drive
Suite 17
Scottsdale, AZ 86260
(602) 846-4240

Time Electronics
2410 E. Cerritos Ave.
Anaheim, CA 92806
(714) 937-0911

California

Time Electronics
19210 S. Van Ness Ave.
Torrance, CA 90501
(213) 320-0880

Cetec Electronics

5610 E. Imperial Highway
Southgate, CA 90280
(213) 773-8521
Cetec Electronics
1962 Browning
Irvine, CA 92714
(714) 250-4141
Cetec Electronics

3840 Ruffin Street
Suite E
San Diego, CA 92123
(619) 278-6020
Cetee Electronics

2300 Owen Strest
Santa Clara, CA 95051
(408) 980-0110
Cetec Electronics
21730 Nordhoff Street
Chatsworth, CA 91311
(818) 700-0914
Image Electronics
1342 Bell Ave.
Tustin, CA 92680
(714) 730-0303

Western Mlcrotechnology
10040 Bubb Road
Cupertino, CA 95014
(408) 725-1660

Colorado
Diplomat Electronics
3974 Youngfleld Street
Wheatrldge, CO 80033
(303) 422-9229
IEC Corporation
420 E. 58th Avenue
Denver, CO 80216
(303) 292-5537
IEC Corporation
5750 N. Logan Street
Logan, CO 80216
(303) 292-8121
Marshall Industries
7000 N. Broadway
Denver, CO 80221
(303) 427-1818
Time Electronics

Insight Electronics

7399 S. Tucson Way

6855 Flanders Drive
Suite G
San Diego, CA 92126
(619) 587-0471

Suite A-7
Inglewood, CO 80112
(303) 799-8551

Connecticut

Florida

Classic Components

1300 N. W. 55th Place
Ft. Lauderdale, FL 33309
(305) 974-8700

3336 Commerclal,Ave.
Northbrook, IL 60062
(312) 272-9650

Diplomat Electronics
2120 Calumet Street
Clearwater, FL 33515
(813) 443-4514

2200 N. Stonington
Hoffman Estates, IL 60195
(312) 843-2040

Marshall Industries
4205 34th Street, SW
Orlando, FL 32805
(305) 841-1878

1101 NW 62nd Street
Suite 360 D
Ft. Lauderdale, FL 33309
(305) 928-0661

Reptron
33320 N. W. 53rd Street
Suite 206
Ft. Lauderdale, FL 33309
(305) 735-1112
Reptron

13700 McCormick Drive
Tampa, FL 33624
(813) 855-4556
Time Electronics
6610 NW 21st Avenue
Ft. Lauderdale, FL 33309
(305) 974-4800
Time Electronics
4405 Vineland Road
Suite C15
Orlando, FL 32811
(305) 841-6555

Wood Dale, IL 60191

Indiana
Classic Compnents

8152 Zionsville Road
Indianapolis, IN 46268
(317) 872-4777
Marshall Industries

6990 Corporate Drive
IndianapoliS, IN 46278
(317) 297-0483

Kansas
Marshall Industries

8321 Melrose Drive
Lenexa, KS 66214
(913) 492-3121
Mligray
6901 W. 63rd Street
Overland Park, KS 66202
(913) 236-8800

Massachusetts
Interface Electronics

Diplomat Electronics
6559 Peachtree Industrial Blvd.
Suite B
Norcross, GA 30092
(404) 449-4133

Marshall Industries
One Wilshire Road
Burlington, MA 01803
(617) 272-8200

Marshall Industries
4350J International Blvd.
Norcross, GA 30093

(404) 923-5750

Mllgray
378 Boston Post Road
Orange, CT 06477
(203) 795-0711

Raptron
3040 H Buslnes. Park Drive
Norcross, GA 30071
(404) 446-1300

Time Electronics
1701 Milldale Road

Time Electronics
5555 Oakbrook Parkway
Suite 535
Norcross, GA 30093
(404) 448-4448

FUJITSU

Time Electronics
945 N. Edgewood Drive
Suite G

228 South Street
Hopkinton, MA 01748
(617) 435-6658

Marshall Industries
8015 Dearing Ave.
Canoga Park, CA 91304
(213) 999-5001

(203) 271-3200

1261 Wiley Road
Suite F
Schaumburg, IL 60195
(312) 490-0155

Georgia

Marshall Industries
20 Sterling Barnes Park N.
Wallingford, CT 08492
(202) 265-3622

Chealre, OT 06410

Marshall Industries

(312) 350-0610
Mllgray
1550 Lee Road
Suite 104
Winter Park, FL 32789
(305) 847-5747

Mllgray
17 Dunwoody Park
Suite 102
Atlanta, GA 30338
(404) 393-9666

17321 Murphy Ave.
Irvine, CA 92714
(714) 660-095 1

Intercomp

Marshall Industries

Marshall Industries
9674 Telatar Ava.
EI Monte, CA 91731
(818) 442-7204

Marshall Industries

illinois

Diplomat Electronics

Mligray
79 Terrace Hall Avenue
Burlington, MA 01803
(617) 272-6800
RC Components
222 Andover Street
Wilmington, MA 01887
(617) 273-1860
Time Electronics
IDA Centennial Drive
Peabody, MA 01960
(617) 532-8200

Maryland
Diplomat Electronics
Runsey Center I Suite AS
9150 Rumsey

Columbia, MD 21045
(301) 995-1226

Marshall Industries
8445 Helgerman
Gaithersburg, MD 20877
(301) 840-9450

Mllgray
9801 Broken Land Parkway
Columbia, MD 21045
(301) 995-6169

Michigan
Calder Electronics
4245 Brockton Drive, S. E.
Grand Rapids, MI 49508
(616) 698-7400
Marshall Industries
13760 Merriman Road
Livonia, MI 48150
(313) 525-5850
Reptron
34403 Glendale
Livonia, MI48150
(313) 525-2700

Minnesota
Diplomat Electronics
14920 28th Ave. N.
Plymouth, MN 55441
(612) 559-2500
Marshall Industries
3800 Annapolis Lane
Plymouth, MN 55441
(612) 559-2211
Time Electronics
7488 West 78th Street
Bloomington, MN 55435
(612) 944-9192

Missouri
Time Electronics
330 Sovereign Court
St. Louis, MO 63011
(314) 391-6444

North Carolina
Marshall Industries
5221 North Boulevard
Raleigh, NC 27604
(919) 878-Q882

New Jersey
Diplomat Electronics
2091 Springdale Road
Suite 2
Cherry Hili, NJ 08003
(609) 754-0518

Diplomat Electronics
490 S. River View Drive
Totawa, NJ 07512
(201) 785-1830
Marshall Industries
101 Fairfield Road
Fairfield, NJ 07006
(201) 882-0320
Marshall Industries
1021 Gaither Drive
Mt. Laurel, NJ 08054
(609) 234-9100

FUJITSU

Mligray
3002 Greentree Exec. Campus
Suite B
Marlton, NJ 08053
(609) 983-5010

Reptron
404 E. Wilson Bridge Road
Suite A
Worthington, OH 43085
(614) 436-6675

Vantage Electronics
23 Sebago Street
Clifton, NJ 07013
(201) 777-4100

Time Electronics
6175H Shamrock Court
Dublin, OH 43017
(614) 761-1100

New York

Oklahoma

Current Components
215 Marcus Boulevard
Hauppauge, NY 11787
(516) 273-2600

Radio Inc.
1000 South Main
Tulsa, OK 74119
(918) 587-Q123

Diplomat Electronics
110 Marcus Drive
Melville, NY 11747
(516) 454-6400
Marshall Industries
129 Brown Street
Johnson City, NY 13790
(607) 798-1611
Marshall Industries
1280 ScottSVille Road
Rochester, NY 14624
(716) 235-7620
Marshall Industries
275 Oser Ave.
Hauppauge, NY 11788
(516) 273-2424
Mast Distributors
215 Marcus Blvd.
Hauppauge, NY 11788
(516) 273-4422

Mllgray
77 Schmidt Blvd.
Farmingdale, NY 11788
(516) 420-Q800
Mllgray
57 Monroe Ave.
Pittsford, NY 14534
(716) 385-9330
Rome Electronics
216 Erie Boulevard, E.
Rome, NY 13440
(315) 337-5400
Vantage Electronics
356 Veterans Memorial Highway
Commack. NV 11725
(516) 543-2000

Ohio
Marshall Industries
6212 Executive Blvd.
Dayton, OH 45424
(513) 236-8088
Marshall Industries
5905B Harper Road
Solon, OH 44139
(216) 248-1788

Mllgray
6155 Rockslde Road
Cleveland, OH 44131
(216) 881-8800

Oregon

Time Electronics
2210 Hatton
Suite 101
Carrollton, TX 75006
(214) 241-7441

Utah
Diplomat Electronics
3007 South West Temple
Salt Lake City, UT 84115
(801) 486-4134

Washington
IEC Corporation
1750 124th Avenue NE
Bellevue, WA 98005
(206)

Marshall Industries
8230 S.W. Nimbus Avenue
Beaverton, OR 97005
(503) 644-5050

Marshall Industries
14102 NE 21st Street
Bellevue, WA 98007
(206) 747-Ql00

Western Mlcrotechnology
1800 N. W. 169th Place
Suite 6300
Beaverton, OR 97006
(503) 629-2082

Western Mlcrotachnology
14636 NE 95th Street
Redmond, WA 98052
(206) 881-6737

Pennsylvania
Time Electronics
600 Clark Ave.
King of Prussia, PA 19406
(215) 337-0900

Texas
Diplomat Electronics
4951 Airport Parkway
Suite 590
Dallas, TX 75248
(214) 980-1888

Diplomat Electronics
3130 Regardale
Suite 160
Houston, TX 77042
(713) 975-6447
Diplomat Electronics
6448 Highway 290E, Bldg. A
Suite 108
Austin, TX 78723
(512) 452-5254

Marshall Industries
14205 Proton Road
Dallas, TX 75234
(214) 233-5200
Marshall industries
3698 Westchase Drive
Houston, TX 77042
(713) 789-6600
Marshall Industrlas
8504 Cross Park Drive
Austin, TX 78758
(512) 458-5654

Mllgray
17060 Dallas Parkway
Suite 105
Dallas, TX 75248
(214) 248-1603

Wisconsin
Classic Components
2925 S. 160th Street
Naw Berlin, WI 53151
(414) 786-5300

Marsh Electronics
1563 S. 101st Street
Milwaukee, WI 53214
(414) 475-6000

Canada
Carsten Electronics
3791 Victoria Park Ave.
Scarborough, O,ntarlo M1W 3K8
(416) 495-7705

Space Electronics
5851 Rue Ferrier Street
Montreal, Quebec H4P 2K5
(514) 697-8876
Space Electronics
3070 Klngsway
Vancou_, B.C. V5R 5J7
(604) 438-5545

•

FUJITSU LIMITED
ComnuuIicaJionj and 6lectronicJ

6 -1, Marunouchi 1-chome, Chi y oda -ku, Toky o 100, Japan
Phone : National (03) 216-32 11 I nternational (lnt'l Prefi x ) 81 -3 -216-3211

Telex J22833 Cable: "FUJ I T SU LIMI T ED T OKYO"

For further information please contact :
FUJITSU LIMITED
Semiconductors Marketing: Furukawa Sogo Bldg ., 6-1, Marunouchi 2-chome, Chiyoda-ku, Tok y o i 00, Japan
Phone : National 103) 216-321 1 International (Int'I Prefix) 81 -3-2 16-3211 Telex : 222436 1 FTTOR J
FUJITSU MICROELECTRONICS. INC ,:
33 20 Scott Blvd ., Santa Clara, CA95054-3 197, U .S.A .
Phone : 408-727-1700 Telex : 910-338-0 190 FUJ ITSU SNTA
FUJITSU MIKROELEKTRONIK GmbH. :
Arabella Center 9 . OG ./A
L yoner St rar..e 44-48 D-6000 Frankfu r t 7 1, F .R. Germany
Pho ne : 069/ 66320 Telex : 04 11963

Printed in USA June 1986.
1986_Fujitsu_Memories_Databook 1986 Fujitsu Memories Databook

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